1991_Harris_Linear_and_Telecom_ICs 1991 Harris Linear And Telecom ICs

User Manual: 1991_Harris_Linear_and_Telecom_ICs

Open the PDF directly: View PDF .
Page Count: 1234

Download
Open PDF In Browser	View PDF

m

~

HARRIS
SEMICONDUCTOR
NEW HIGH SPEED LINEAR PRODUCTS
AMPLIFIERS

. •. •:•.:·lfJ~·6~~A~;dd~~~~~~E2e~~~b~:~~~i~~r:;:;i::;i~~b!~~A;~~i~~~~~~J$p.~~~bG~~~Nf~,6~'b:;:
... . .... ,::,. ;:.:....

>" ,. ' ..".."".;.. '... '

,.

.

.. , , """.,:,.,.,:., ,. " ..".'.'.'.'.. !

, ,.. , ....,.,...

"-'-"'-'---';;;.;.....,.,.,...;
. ,., ,.;..;
...,. ,_.'.'_. '_..."'-"-;....;..='"'-""-'-.;;....;.~=--"""

(Page 3-368)

(Page 3-344)

.. UNITY GAIN BANDWIDTH ............... 100MHz

0

HIGHSLEWRATE ....................... 375V//ls
GAIN BANDWIDTH PRODUCT ............. SOMHz

o DIFFERENTIAL GAIN .................... <0.02%

0

.. DIFFERENTIAL PHASE ................... <0.03°

.. HIGH OUTPUT CURRENT ............... ±100mA

o SLEW RATE ............................ 800V//ls

0

DIFFERENTIAL GAIN/PHASE ......... 0.02%/0.030

o GAIN FLATNESS .......................... 0.1dB

0

LOWOFFSETVOLTAGE .................... 1mV

(Page 3-335)

(Page 3-341)

o

HIGH SLEW RATE .........•............ 625V//ls

.. HIGH SLEW RATE ....................... 240VIlls

o

WIDE GAIN BANDWIDTH ................ 600MHz

o UNITY GAIN BANDWIDTH ................. 54MHz

o DIFFERENTIAL GAIN/PHASE ........ 0.03%/0.03°

o LOWOFFSETVOLTAGE .................... 1mV

o

LOW OFFSET VOLTAGE .................. 0.6mV

o DIFFERENTIAL GAIN/PHASE ......... 0.03%/0.03°

o

FULL POWER BANDWIDTH ............... 10MHz

o LOW DISTORTION .....................•. >S3dB

o

LOW SUPPLY CURRENT ............. 8.0mA Max

o

o

HIGH SLEW RATE ...................... 340V//ls

.. LOW OFFSET DRIFT .................... 2/lV/OC

o

WIDE GAIN BANDWIDTH ................ 470MHz

.. LOW SUPPLY CURRENT ................ <1mA/A

o

DIFFERENTIAL GAIN/PHASE ........ 0.04%/0.04°

o LOW BIAS CURRENT ........................ 5nA

o

LOW OFFSET VOLTAGE .................. 0.6mV

.. HIGH CMRR/PSRR ....................... 110dB

(Page 3-47S)

(Page 3-347)

LOWOFFSETVOLTAGE .............. 300/lVMax

(Page 3-481)
• VERY LOW POWER ................ 150/lA (7712)
15nA (7713)
o LOW OFFSET VOLTAGE .................. 250/lV

• LOW INPUT BIAS CURRENT ................ 20pA
• WIDE OPERATING RANGE ............. 4Vt016V

mHARRIS
~ SEMICONDUCTOR
NEW HIGH SPEED LINEAR PRODUCTS
(Continued)

MULTI-CHANNEL AMPLIFIERS

(Page 8-50)

(Page 3-255)

• 5 MULTIPLEX VIDEO CHANNELS
~ 1 Independent Channel
~ 4 Channels With Enable

• UNITY GAIN BANDWIDTH ................. 45MHz

• UNITY GAIN BANDWIDTH ..............•. 25MHz

• GAIN FLATNESS TO 10MHz ................ 0.1dB

• PROGRAMMABLE VIDEO AMPLIFIER GAIN

• CROSSTALK REJECTION ...•............. >60dB

• HIGH SIGNAL DRIVE CAPABILITY

• FAST CHANNEL SELECTION ................ 60ns

• DIFFERENTIAL GAIN ..................•.. 0.03dB
• DIFFERENTIAL PHASE .................... 0.030

COMPARATORS

MULTIPLIERS

(Page 4-31)

(Pages 8-86 & 8-89)

• LOW PROPAGATION DELAY ...•....... 2.0/2.1 ns

• CHANNEL BANDWiDTH ............. 301100MHz

• LOWOFFSETVOLTAGE ................... 1mV

• DIFFERENTIAL GAIN ....................... 0.1%

• WIDE COMMON MODE RANGE ....... +5.2/-2.8V

o DIFFERENTIAL PHASE ..................... 0.1 0

• USER PROGRAMMABLE HYSTERESIS

• GAIN FLATNESS TO 1OMHz ................ 0.1 dB

• WIDE TRACKING BANDWIDTH ........... 270M Hz

• SLEW RATE ............................ 350V/IIS

TELECOM SLiCs

(Page 9-102)

(Page 9-75,9-88 & 9-95)
o MEETS WORLDWIDE PBX REQUIREMENTS

• PROGRAMMABLE LOOP CURRENT

• DIGITAL LOOP CARRIER MARKET (5504DLC)

• THERMAL SHUTDOWN FEATURE

• +5V AND +12V OPERATION

• TRANSMIT SIGNALS WHILE ON-HOOK

(Page 9-111)
• PROGRAMMABLE LOOP CURRENT
• -24V BATTERY
• THERMAL SHUTDOWN FEATURE

II

m

~

HARRIS
SEMICONDUCTOR
NEW POWER PROCESSING ICs
DC/DC CONVERTERS AND REGULATORS

Produced on low power CMOS, these product offer superior performance over other second source devices while
providing latch-free operation at very competitive prices.

(Page 2-87)

(Page 2-87)

• OUTPUT FROM A SINGLE CELL .....•• +3V or +5V

• SAME AS ICL64X WITH SHUT DOWN FEATURE

• START-UP VOLTAGE ...................... 0.9V

• QUIESCENTCURRENT ...................... 5IJA

• lOUT ...........•.......•. 200mA (INT. MOSFET)
350mA (EXT. MOSFET)

• AVAILABLE IN PDIP/SOIC

• STANDBY CURRENT ...................... 80(JA

MOSFET DRIVERS
The "HV" family of MOSFET drivers utilize the benefits of Dielectric Isolation Technology to achieve cost effective
SCR topologies with high voltage and high speed performance.

(Page 2-54)

(Page 2-62)

• +40V TO +450V, DC-30kHz (HV-350)

• PEAK SOURCE/SINK CURRENT. . . . . . . . .. 6N30A

• +40V TO +450V, 10kHz-100kHz (HV-355)

• RISE TIME ................................. 70ns

• 2 AMPs PEAK

• FALL TIME ................................ 30ns

• RISE/FALL TIME ............ 75ns Max at 10000pF

• FREQUENCY RANGE ................... 300kHz

OFFLINE POWER SUPPLIES
Utilizing Harris Dielectric Isolation Technology and proprietary design, this product family provides direct offline to
regulated DC conversion integrating the functions of rectifier, transformer, and 3 terminal regulator into a single cost
saving IC.

(Page 2-76)
• INPUT RANGE ........•......... 18V to 264Vrms
• OUTPUT RANGE . . . . . . . . • .. 5V to 24VDC at 50mA
• 250mA OUTPUT WITH APP. NOTE AN9101
• UL RECOGNIZED (FILE # E130808)

III

$5.00-

m

HARRIS
SEMICONDUCTOR

....,

THE NEW HARRIS SEMICONDUCTOR
In December 1988, Harris Semiconductor acquired the General Electric
Solid State division, thereby adding former GE, RCA, and Intersil devices to
the Harris Semiconductor line.
This linear IC databook represents the full line of Harris Semiconductor
linear products for commercial applications and supersedes previously
published linear databooks under the Harris, GE, RCA or Intersil names.
For a complete listing of all Harris Semiconductor products, please refer to
the Product Selection Guide (SPG-201 R; ordering information below).
For complete, current and detailed technical specifications on any Harris
device please contact the nearest Harris sales, representative or distributor
office; or direct literature requests to:
Harris Semiconductor Literature Department
P.O. Box 883, MS CB1-28
Melbourne, FL 32901
(407) 724-3739
FAX 407-724-3937

u.s. HEADQUARTERS

EUROPEAN HEADQUARTERS

Harris Semiconductor
1301 Woody Burke Road
Melbourne, Florida 32902
TEL: (407) 724-3000

Harris Semiconductor
Mercure Centre
Rue de la Fusse 100
Brussels, Belgium 1130
TEL: (32) 2-246-2111

SOUTH ASIA

, Harris Semiconductor HK Ltd
13/F Fourseas Building
208-212 Nathan Road
Tsimshatsui, Kowloon
Hong Kong
TEL: (852) 3-723-6339

NORTH ASIA

Harris K.K.
Shinjuku NS Bldg. Box 6153
2-4-1 Nishi-Shinjuku
Shinjuku-Ku, Tokyo 163 Japan
TEL: 81-3-345-8911

Harris Semiconductor products are sold by description only. All specifications in this
product guide are applicable only to packaged products; specifications for die are
available upon request. Harris reserves the right to make changes in circuit design,
specifications and other information at any time without prior notice. Accordingly, the
reader is cautioned to verify that information in this publication is current
before placing orders. Reference to products of other manufacturers are solely
for convenience of comparison and do-not imply total equivalency of design,
performance, or otherwise.

See our
specs in

CAPS

Copyright @ Harris Corporation 1991
- (All- rights reserved)
Printed in U.SA-, 8/1991

iv

FOR COMMERCIAL APPLICATIONS
General Information

III

Power Processing Circuits

Ell

Operational AmPlifiers.
Comparators.
Sample and Hold Amplifiers.
Differential Amplifiers.
Arrays.
Special Analog Circuits.
Telecommunications.
Harris Quality and Reliability

III

Application Note Abstracts

III

Packaging and Ordering Information.
Sales Office Information

v

III

LINEAR PRODUCT TECHNICAL ASSISTANCE
For technical assistance on the Harris products listed in this databook. please
contact Field Applications Engineering staff available at one of the following
Harris Sales Offices:

UNITED STATES
CALIFORNIA

Costa Mesa ••.•.•....••... 714-433-0600
San Jose ..••.....•.......• 408-922-0977
Woodland Hills .......••... 818-992-0686

FLORIDA

Melbourne •••.•..•.••••... 407-724-3576

GEORGIA

Norcross ..•••...•...••..•• 404-246-4660

ILLINOIS

Schaumburg ........•....• 708-240-3480

MASSACHUSETTS

Burlington •..••.••.•...•.. 617-221-1850

NEW JERSEY

Mt. Laurel .•......••....... 609-727-1909

NEW YORK

Great Neck •.......••...... 516-829-9441

TEXAS

Dallas ...••.......•.....•• 214-733-0800

INTERNATIONAL
FRANCE

Paris •....•..••.....•..... 33-1-346-54046

GERMANY

Munlch ..........•..•..... 49-8-963-8130

ITALY

Milan •..•••.•.........••.. 39-2-262-22141

JAPAN

Tokyo .......••........... 81-3-345-8911

KOREA

Seoul. ..•....••...••...... 82-2-551-0931

U.K.

Camberley ..•.•........•.. 44-2-766-86886

For literature requests. please contact Harris Telemarketing at 407-724-3739.

vi

GENERAL INFORMATION

ALPHA NUMERIC PRODUCT INDEX ........................................................... ..

1-2

Z
-,0


0:0
a. 0:
0:C3

w

==

0
a.

Selection Guide
POWER PROCESSING CIRCUITS
TYPE

DESCRIPTION

FUNCTION

PIN COUNT
PACKAGE

CONVERTERS
ICL644/645/
646/647/
ICL7644/7645/
7646/7647

LowVoliage Step-Up
Converters

Designed to provide 3V or 5V output from a single 1.5V battery (645 and 7645)
use two cells. Low quiescent current coupled with low start up voltage, insure long
battery life.

14/PDIP
14/S01C

ICL7660S

Voltage Converter

Performs supply voltage conversion from posillve to negative. Input range is
+1.5V to +10V resulting In complementary output voltages of -1.5V to -12V.
Can be connected as a voltage doubler to generate output voltage of -lB.6V. TA
Range: COC to +700C, -550C to +1250 C. ICL7660S improved version of
ICL7660. Has extended supply voltage range, lower supply current, and ESD
protection (>2000V).

8/S0IC,
8/PDIP
B/TO-99

ICL7662S

Voltage Converter

Similar to the ICL7660S In Its operation, except the output voltages are -4.5V to
-20V. Doubler output 22.6V.

81PDIP
8/TO-99

Power CMOS FET

Complementary power MOSFET driver. Wide supply range (20V 10 450V). High
peak output current of 2A. High switching speed 200ns. New product in
development

16/CDIP
16/PDIP

MOSFETDRIVERS
HV-250/255 ""

Driver

HV-350/355

Totem Pole N-Channel
Power MOSFET Driver

Tolem pole n-channel power MOSFET driver. Wide supply range (20V to 450V).
high peak output current of 2A. High switching speed of 200ns. New product in
development

16/CDIP
16/PDIP
16/S01C

HV-400

High Speed MOSFET
Driver

Single, non-inverting high speed driver (up to 300kHz) designed to drive large
capacitive loads in 5,000pF to 100,000pF range. Capable of sourcing 6A and
sinking lOA.

B/PDIP
B/CDIP
B/SOIC

ICL7667

Dual Power
MOSFET Driver

TTL-compatible high-speed CMOS driver designed to provide high output
current (1.5A) and voltage (up to +15V) for driving the gates of power MOSFETs
in high-frequency switched-mode power converters. TA Range: OOC to + 7COC,
-550C 10 +1250C.

BISOIC
B/PDIP
8/CDIP
8/TO-99

OFFLINE POWER SUPPLIES
HV-1205

l20VAC OfI1ine
Monolithic Power
Supply

AC to DC converter designed for l20VAC input Output is capable of 5VDC
to 24VDC @ OmA to 50mA of curren!. This part Is UL recognized (File# 130B08)
and UL listed.

B/PDIP

HV-2405

240VAC Offline
Monolithic Power
Supply

AC to DC converter designed for 240VAC input Output is capable of 5VDC
to 24VDC @ OmA 10 50mA of current This part is UL recognized (File# 130B08)
and UL listed.

8/PDIP

Programmable MicroPower Positive
Voltage Regulator

Low-power, high-efficiency device (10 = 4f1A max.) that accepts an input of 1 to
l6V and provides an adjustable output over the sarne range at up to 40mA load.
TA Range: OOC to + 700C, -250C to +B50C. Line and load regulation and ESD
protection (>2000V).

B/SOIC
8/CDIP
B/PDIP
8/TO-99

REGULATORS
ICL7663S

VOLTAGE MONITORING CIRCUITS
ICL7665S
ICL766S

Programmable MicroPower Under/Over
Voltage Detector

Contains two individually programmable voltage comparators and requires only
3f1A supply current Intended for battery-operated systems that require low or
high voltage warnings, etc. Open drain outputs for interfacing. TA Range: oOC to
+ 700C, -250C to +85OC. ICL7665S improved ICL7665. For features, see
ICL7663S.

B/SOIC
8/CDIP
B/PDIP
8/TO-99

ICL7673

Aulomatic Battery
Backup Switch

Automatically switches between a main power supply (eg., +SV) and a battery
back-up supply, when the main supply is removed. Wide supply range: 2.5V to
to TA Range: OOC to + 700C, -250C to +B50C.

B/SOIC
B/PDIP

ICLB211

Programmable Voltage
Level Detector

Contains a 1.lSV reference, a comparator, a hysteresis output and a noninverting main-output. Provides a 7mA current-limited output sink when voltage
on threshold terminal is <1.15V. TA Range: OOC to +7COC, -550C to +12SoC.

B/SOIC
B/CDIP
B/PDIP
B/TO-99

ICLB212

Programmable Voltage
Level Detector

Similar in operation to the ICL8211 except that its main output is inverting as
opposed to non-inverting. Requires a voltage in excess of 1.15V to switch its
output current limit). TA Range: Same as ICL8211.

B/SOIC
8/PDIP
8/TO-99

2-2

Selection Guide
POWER PROCESSING CIRCUITS

TYPE
CA3085

DESCRIPTION

VI
RANGE
V

Vo
RANGE
V

10
(MAX)
rnA

Voltage regulators

LOAD
REGULATION
%VO(MAX)

VI-VO
V
(MIN)

SHORT-CIRCUIT
CURRENT LIMIT
rnA (TYP)

PIN COUNT
AND PACKAGE
TYPE*

7.5t030

1.8t026

12**

0.1

4

96

8E,8S

CA3085A

7.5t040

1.7t036

100

0.15

4

96

8E,8S

CA3085B

7.5t050

1.7t046

100

0.15

3.5

96

8E,8S

CA723

9.5 to 40

21037

150

0.03

3

65

10T,14E

9.5 to 40

21037

150

0.03

3

65

10T,14E

CA723C

**This value may be extended to 1OOmA; however, regulation is not specified beyond 12mA.
Operating temperature range (TA): -55 to +125 0 C. Electrical characteristics at TA = 250 C

TYPE

DESCRIPTION

V+
RANGE
V

Vo
RANGE
V

LOAD
REGULATION
%VO(TYP)

8t040
8t040
8t040

4.810 5.2
4.810 5.2
4.6105.4

0.2
0.2
0.2

(!J

RIPPLE
REJECTION
dB (TYP)

TOTAL STANDBY
CURRENT IS (rnA)
(MAX)

VCESAT
V
(TYP)

66
66
66

10
10
10

0.8
0.8
0.8

:z

en
fflU)

01-

05
0::0

CA1524
CA2524
CA3524

Regulating
pulse-width
modulators

Electrical characteristics at V+ = 20V, I = 20kHZ.
TA = -55 to +125 0 C lor CA1524; 0 to + 700C lor CA2524, CA3534. 16-lead dual-in-line (E) & (F) packages.
Short-circuit current limit 1OOmA typo Temperature stability: 1% max.

TYPE
CA3059
CA3079

DESCRIPTION
Zero voltage
switches

AC INPUT VOLTS
@ 50-60 & 400Hz
(VAC)

MAX. DC
SUPPLY
VOLTS (V)

24
120
208/230
277

MAX. INPUT
CURRENT
(1lA)

SENSOR
RANGE(Rxl

14

1

2toloo

10

2

21050

kO

CONTROL CURRENT TO
THYRISTOR GATE
(rnA)
Up to 124 with internal supply; up
10 240 with one external supply

Electrical characteristics atTA = 25 0C. 14-lead dual-in-line plastic package (no suffix).
Operating temperature range (Till: -55 to +1250 C.
·Sea Packaging and Ordering Information in Section 12.

2-3

c..o::

0::0

w

~
c..

m

CA723
CA723C

HARRIS

Voltage Regulators Adjustable from 2V to 37V at Output
Currents Up to 150mA Without External Pass Transistors

August 1991

Features

Description

• Up to l50mA Output Current

The CA723 and CA723 are silicon monolithic integrated circuits
designed for service as voltage regulators at output voltages
ranging from 2V to 37V at currents up to 150 milliamperes.

• Positive and Negative Voltage Regulation
• Regulation in Excess of lOA with Suitable Pass
Transistors
• Input and Output Short-Circuit Protection
• Load and Line Regulation ••••••••••••••.••••• 0.03%
• Direct Replacement for 723 and 723C Industry Types
• Adjustable Output Voltage ••••••••••••••.• 2V to 37V

Applications
• Series and Shunt Voltage Regulator
• Floating Regulator
• Switching Voltage Regulator
• High-Current Voltage Regulator
• Temperature Controller

Pinouts

Each type Includes a temperature-compensated reference
amplifier, an error amplifier, a power series pass transistor, and a
current-limiting circuit. They also provide Independently accessible
inputs for adjustable current limiting and remote shutdown and, in
addition, feature low standby current drain, low temperature drift,
and high ripple rejection.
The CA723 and CA723C may be used with positive and negative
power supplies in a wide variety of series, shunt, switching, and
floating regulator applications. They can provide regulation at load
currents greater than 150mA and in excess of 10A with the use of
suitable n-p-n or p-n-p external pass transistors.
The CA723 and CA723C are supplied In the 10 lead TO-5 style
package (T suffix), and the 14 lead dual-In-line plastiC package
(E suffix), and are direct replacements for industry types 723,
723C, ~A723, and ~723C in packages with similar terminal
arrangements. They are also available in chip form (UH" suffix).
All types are rated for operation over the full military-temperature
range of -55 0 C to +1250 C.

Functional Block Diagram

E SUFFIX PACKAGE
TOP VIEW

,------"

NC

CURRENT

FREQUENCY
COMPENSATION

FREQ
COMP

LIMIT

y+ UNREG

CURRENT
SENSE

INI!UT

NON-INV.
INPUT

Vo

Vo REGULATED
OUTPUT

vz
v'

T SUFFIX PACKAGE
TOP VIEW
CURRENT UhIT

CAUTION; These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

2-5

File Number

788.1

CJ

:z

m

~~

0::::>
a: 0

a.. a:

a:o
w

1'a..5

CA 723, CA 723C
Absolute Maximum Ratings
DC Supply Voltage (Between V+ and V- Terminals) ••••••••.•••••••••••••••••••••••••••••••••••.•••••••••••••••••••••••••••• 40V
Pulse Voltage for 50ma
Pulse Width (Between V+ and V- Terminals) •••••••••••••••••.•••••••••••••••••••••••••.•••••••••••••••••.••••••••••••••• 50V
Differential Input-Output Voltage ••••••.•••••.•••••••••.••••••.•••••••.••••••••••••••••••••••••••••••••••••••••••••••••••• 40V
Differential Input Voltage
Between Inverting and Non-Inverting Inputs •••••••••••••••••.•••••••••••••••••.•••••••.•••••••••••••••••.••••••••••••••• ±5V
Between Non-Inverting Input and V- ••••.•••••••••••••••.•••••••••••••.••••.••.••••••.••••••.••••••••••••••••.••••••••••• 8V
Current From Zener Diode Terminal (Vzl •.•••.••••••••••••••.••••••••••••••••••••••••••••••••••••••••••••••••.•••••••••.• 25mA
Current From Voltage Reference Terminal (VREF) ••••••••••.•.•••••••••••••••••••••••••••••••••.•••••••••.••••.•••• '••••••• 15mA
Device Dissipation
Up to TA = +250 C
CA723T. CA723CT ............................................................................................. 800mW
CA723E.CA723CE ............................................................................................ 1000mW
Above TA = +250 C
CA723T. CA723CT. Derate Linearly ............................................................................. 6.3mWJOC
CA723E. CA723CE. Derate Linearly ............................................................................ 8.3mWJOC
Ambient Temperature Range
Operating .............................................................................................. -550 Cto+1250 C
Storage ................................................................................................ -650 Cto+1500 C
Lead Temperature. During Soldering ............................................................................. ~ .... +2650 C
At a distance 1/16" ±1/32" (1.59 ± 0.79mm) from case for 108 max

y+

yz
+-----c~F,~~~~iION

1-_ _-
a: 0
D.. a:
a:u

V

~
D..

Reference Voltage,

w

6.95

7.15

7.35

6.8

7.15

7.5

VI=12
to 40 V

-

0.02

0.2

-

0.1

0.5

VI = 12
to 15 V

-

0.01

0.1

-

0.01

0.1

VREF

Line Regulation
(See Note 1)

Load Regulation
(See Note 1)

Output-Voltage
Temp. Coefficient,
tWo

Ripple Rejection
(See Note 2)

(!J

:z

u;

Differential InputOutput Voltage,
VI-VO

VI = 12
to 15 V,
TA = -55 to
+125°C

-

-

0.3

-

-

-

VI=12
to 15 V,
TA=Oto
70°C

-

-

-

-

-

0.3

IL = 1
to 50 mA

-

0.03

0.15

-

0.03

0.2

IL = 1
to 50 rnA,
TA = -55 to
+125°C

-

-

0.6

-

-

-

IL = 1
to 50 rnA,
TA=O
to 70°C

-

-

-

-

-

0.6

TA = -55
to +125°C

-

-

-

-

TA=O
to 70°C

-

-

-

-

0.003

f = 50 Hz
to 10 kHz

-

74

-

-

74

f= 50 Hzto
10kHz,
CREF = 5~F

%VO

-

0.002

86

2-7

0,015

-

-

86

%VO

%fC

0.015

-

dB

CA 723, CA 723C
ELECTRICAL CHARACTERISTICS (Cont'd)
LIMITS
,CHARACTERISTIC
S!1ort·Circuit
Limiting Current.
ILiM

TEST
. CONDITIONS
RSCp = 10
VO=O

CA723
Max.
Min. Typ.

CA723C
Min. Typ.
Max.

n.

BW- 100 Hz
to 10kHz.
Equivalent Noise RMS CREF = 0
Output Voltage. VN
BW= 100 Hz
(See Note 2)
10 kHz.
CREF = 5IJ.F

-

65

-

-

65

-

-

20

-

-

20

-

-

2.5

-

-

2.5

-

UNITS

rnA

IJ.V

Note 1: Line and load regulation specifications are given for condition of a constant chip
temperature. For high-dissipation condition, temperature drifts must be separately
taken into account.
Note 2: For CREF (See Figure 20).
TYPICAL CHARACTERISTICS CURVES FOR TYPE CA723

MAX JUNCTION TEMP IT.. loI50·C
'"

•

ISO

THERMAL RESISTANCE z150·C/W
QUIESCENT DISSIPATION IPQ).60mW
(NO HEAT SINK)

!

o

o

10
40
20
DIFFERENTIAL INPUT-OUTPUT VOLTAGE (VI-YO I-V

'"

OUTPUT CURRENT flO J-rnA

FIGURE 2. MAX LOAD CURRENT vs DIFFERENTIAL
INPUT-OUTPUT VOLTAGE

FIGURE 3. LOAD REGULATION WITHOUT CURRENT
LIMITING

OUTPUT VOLTAGE 1VO'-511
INPUT VOLTAGE IV,! )-12 V

SHORT-CIRCUIT PROTECTION

IiTANCE '·SCp}·lon

I?

I~

I!

-0.1

I~

OUTPUT CURRENT l.lel-rnA

OUTPUT CURRENT {Iel-mA

FIGURE 5. LOAD REGULATION WITH CURRENT LIMITING

FIGURE 4. LOAD REGULATION WITH CURRENT LIMITING

2-8

CA 723, CA 723C
TYPICAL CHARACTERISTICS CURVES FOR TYPE CA723 (Continued)

OUTPUT VOL.TAGE (Va I-REFERENCE

VOt,.TAGE IVREF)
L010 CURRENT I.ILI 00

i •

~

Ia

4

~

2

-

•

~
~

. ~

\roI~\tN1 ~~MPERATUREITAI.-!WC
; 2~·C

'12.5·C

IIiHIl

I

10

20
30
INPUT VOL.TAGE lVII-V

OUTPUT CURRENT IIOI-mA

(!I

flUl1i4.

en

f3U)

01-

FIGURE 7. QUIESCENT CURRENT vs INPUT VOLTAGE

FIGURE 6. CURRENT LIMITING CHARACTERISTICS

:z

oS
a:O
a. a:
a:U
w
~

TYPICAL CHARACTERISTICS CURVES FOR TYPE CA723C

o

a.

· ".
E

1

. ".

MAl(. JUNCTION TEMP tTJ '0150·C
THERMAL RESISTANCE o150·C/W
QUIESCENT DISSIPATION IPo)l6OmW
TO-!i STYL,E PACKAGE WITH NO
HEAT SINK

a

THERMAL RESISTANCE oI2!1·C/W
QUIESCENT DISSIPATION IPQl;6OrnW

DUAL-IN-I.INE PLASTIC PACICAGE

!

WITH NO HUT SINK

"

"

§

MAX. JUNCTION TEMP. ITJ 1-125·C

E

~

;
. ••
I••

I ••

~

~

~
•ii ••
•

~

2

ii

I.

2.

30

I.

4.

2.

••

4.

DIFFERENTIAL INPUT-OUTPUT VOL.TAGE IVrVo I-V

DIFFERENTIAL INPUT-OUTPUT VOLTAGE IVrVo I-V

FIGURE 9. MAX LOAD CURRENT vs DIFFERENTIAL
INPUT-OUTPUT VOLTAGE FOR CA723CE

FIGURE 8. MAX LOAD CURRENT vs DIFFERENTIAL
INPUT-OUTPUT VOLTAGE CA723CT

I

OUTPUT VOL.TAGE 1Vol-5\1
INPUT VOLTAGE I'll: I~ 12 V
SHORT-CIRCUIT PROTECTION
RESISTANCE 1Rscpl-JOn

II l'

OUTPUT CURRENT (:r o l-mA

OUTPUT CURRENT (:rOJ-mA

FIGURE 11. LOAD REGULATION WITH CURRENT LIMITING

FIGURE 10. LOAD REGULATION WITHOUT CURRENT
LIMITING

2-9

CA 723, CA 723C
TYPICAL CHARACTERISTICS CURVES FOR TYPE CA723C (Continued)

OUTPUT VOLTAGE I Vo ,_REFERENCE
VOLTAGE (VREFI

.

LOAD CURRENT ItLloa

E

I

~
~

4

AMBIENT TEMPERATURE! TA,025·C

O'c
70'<

10

20

30

40

INPUT VOLTAGE (VI I-V

OUTPUT CURRENT (:[0 I-rnA

FIGURE 12. CURRENT LIMITING CHARACTERISTICS

FIGURE 13. QUIESCENT CURRENT vs INPUT VOLTAGE

TYPICAL CHARACTERISTICS CURVES FOR TYPES CA723 AND CA723C

OUTPUT VOLTAGEIVo ,o5V

LOAD CURRENT IIL.)"mA
AMBIENT TEMPERATURE (TA 'o;25·C
::.."";.: r INPUT VOLTAGE (.6.V1lo3\j

--~_Rscpy.6 PROTECTION RESISTANCE

~-o.'

.,

·0.

"

35

45

OIFFERENTIAL. INPUT-OUTPUT VOLTAGE IVrVo J-V

OlrFERENTlAL INPUT-OUTPUT VOLTAGE Il/rVo I-V

FIGURE 14. LOAD REGULATION vs DIFFERENTIAL
INPUT-OUTPUT VOLTAGE

FIGURE 15. LINE REGULATION vs DIFFERENTIAL
INPUT-OUTPUT VOLTAGE

FIGURE 16. LINE TRANSIENT RESPONSE

FIGURE 17. CURRENT LIMITING CHARACTERISTICS vs
JUNCTION TEMPERATURE

JUNCTION TEMPERATURE ITJ I_"C

2-10

CA 723, CA 723C
TYPICAL CHARACTERISTICS CURVES FOR TYPES CA723 AND CA723C (Continued)

2

4611

I k
FREQUENCY Ill-HI

TINE (tl-JLS

"

I Ok

, , ,.

CI

1M

FIGURE 19. OUTPUT IMPEDANCE vs FREQUENCY

FIGURE 18. LOAD TRANSIENT RESPONSE

:z
u;
en

~~
05
0::0

D..O::

0::(3

w

~
D..

TYPICAL APPLICATION CIRCUITS

NON
LNV'
INPUT

CIRCUIT PERFORMANCE DATA:

REGULATED OUTPUT VOLTAGE ••

15

V

CIRCUIT PERFORMANCE DATA:

LINE REGULATION (llV,- 3 VI . . . . 1.5 mV

REGULATED OUTPUT VOLTAGE • ••

LOAD REGULATION {!:IlL"' 50 mAl

5

v

LINE REGULATION It.VI-3VI • • • • 05 mV
LOAO REGULATION 't.'L" 50 mAl. . • 1.5 mV
Note: R3·

Nota: R3 -

:~+;; for mimmum 1fIIIperatllr. d .. h

•• 45 mV

=~+:~ for minimum temperiltu" drift

R3 may be ellmlnilted fDl minimum component count.

FIGURE 21. HIGH VOLTAGE REGULATOR CIRCUIT
(VO = 7V TO 37V)

FIGURE 20. LOW VOLTAGE REGULATOR CIRCUIT
(VO = 2V TO 7V)

v+¢r---<}---------,

CA72J
CA7lJC
CURRENT
SENSE

REGULATED

NON

OUTPUT

~~--~~~--r-~
CIRCUIT PERFORMANCE DATA:
REGULATED OUTPUT VOLTAGE "
LINE REGULATION IllV, =3 VI •
LOAD REGULATION (toiL" 100 mAl.

INV

'NPUT

-15
V
1 mV

2 mV
C.RCU.T PERFORMANCE DATA:
REGULATED OUTPUT VOLTAGE • • • 15
V
LINE REGULAT.ON IAV. - 3 VI • • • • 1.5 mV
LOAD REGULAT.ON 1.... 1.. -1 AI. • • • 15 mV

Note. For applicatIons emplOYlnglhl TO·5IWI8 paclcage

andwheraVZllrequlled,anexternal6.2woll
zenerd,odalhouldbaconnectedm5e"eSWllh

VolTermlnal6J.

FIGURE 23. POSITIVE VOLTAGE REGULATOR CIRCUIT
(WITH EXTERNAL n-p-n PASS TRANSISTOR)

FIGURE 22. NEGATIVE VOLTAGE REGULATOR CIRCUIT

2-11

CA 723, CA 723C
TYPICAL APPLICATION CIRCUITS (Continued)

.,

.on

v+

y+

vo

Vc

Vo

REGUl.ATED
DUTPUT

.,

..

2.7
CA723
CA7Z3C

CURRENT
LIN

56kn.

f---0-...,
INV
INPUT

COMP

CIRCUIT PERFORMANCE DATA:
REGULATED OUTPUT VOLTAGE • •• 5 V
LINE REGULATION IllVI·3VI • • • • 0.5 mY
LOAD REGULATloN!l>IL -lOmAI. . . 1 mV
SHORT·CIRCUIT CURRENT • . • • • • 2ft rnA

CIRCUIT PERFORMANCE DATA~
REGULATEDOUTPUTVOL1AGE • ••
5
V
LINE REGULATION , .... Vl'· 3 VI • • • • 0.5 mV
LOAD REGULATION ' .... Il.·' AI. • •• I» mV

FIGURE 24. POSITIVE VOLTAGE REGULATOR CIRCUIT
(WITH EXTERNAL p-n-p PASS TRANSISTOR)

FIGURE 25. FOLDBACK CURRENT LlMlnNG CIRCUIT

DI

>2V
51<3062

.,

>kg

CIRCUIT PERFORMANCE DATA:
REGULATED OUTPUT VOLTAGE ••• -100 Y
LINE REGULATION IllVl',20VI . • •
30 mV
LOADREGULATlON!l>IL"'OOmA)..
20 mY

Notl':Fotlpp/iClilions.mploylngtIMTO-6IWIe
pae k llllllenc!whllre Vzisrequired,ln.lI.·
la'nal 6.2''I01t ziner diode should be con·
nllCledinllll"leswlthVoITerminaI8).
CIRCUIT PERFORMANce DATA:
REGULATED OUTPUT VOLTAGE • • • 60

Note: For applic:atlonnmploying,.. TQ.5 'lYle
peckageandwlWraVZ i,requlred.an IX,
tlrnal &,2·valtzener diodelhould be con·

V

LINE REGULATION (,WI=20VI • • • 15 mV
LOAD REOULATION (..\Il

~

~

50 mAl ••• 20 mY

FIGURE 26. POSITIVE FLOATING REGULATOR CIRCUIT

in seneswilh Vo ITerm11ll161.

FIGURE 27. NEGATIVE FLOATING REGULATOR CIRCUIT

..

NOTE 2

lOOn

REGULATED
OUTPUT

.,

CA723
CA7Z3C

CAU3
CA7Z3C

NON
INV
R2

INPUT

INV

NON
INY INPUT

INPUT

CCSC

LOGIC

.2

INPUT

v-

COMP
.:J;.0'6051'F

CIRCUIT PERFORMANCE DATA:
REGULATEDOUTPUTVOLTAOE • .• 5
V
LINE REGULATION lINt· 10 VI . . . 0.5 mV
LOADREGULATlONll"L=l00mA} .• 1.5 mV
Note For .ppIlCi11'0ns employmg ilia TO·S Itvle package

CIRCUIT PERFORMANCE DATA:
REGULATED OUTPUT VOLTAGE

LlNEREGULATlON!lI.V.-3VI . . • . 05 mV

LOAD REGULATION 1t.IL· 50 mAl . . . 1.5 mV
NoIII 1: A currenilimilmg tranl.dor.".y be utad for
dlutdQwn if c:unent Imlitlng is not reqmr«l.

andwheraV2'$l'tquirad • .nllJlternal8.2-volt
zaner dIOde should bec:onnected.nserllll w.th

VolTermlnllSI.

No.2: AddldlOde.,VO>10V.

FIGURE 28. REMOTE SHUTDOWN REGULATOR CIRCUIT
WITH CURRENT UMITING

FIGURE 29. SHUNT REGULATOR CIRCUIT

2-12

mlHARRIS

CA1524,CA2524
CA3524
Regulating Pulse
Width Modulator

August 1991

Features

Description

• Complete PWM Power Control Circuitry

The CA1524, CA2524, and CA3524 are silicon monolithic
integrated circuits designed to provide all the control
circuitry for use in a broad range of switching regulator
circuits.

• Separate Outputs for Single-Ended or Push-Pull
Operation
• Line and Load Regulation of 0.2% (Typ)
• Internal Reference Supply with 1% (Max) Oscillator
and Reference Voltage Variation Over Full
Temperature Range
• Standby Current of Less Than lOrnA
• Frequency of Operation Beyond 100kHz
• Variable-Output Dead Time of 0.51lS to 51ls
• Low VCE(sat) Over the Temperature Range

Applications

The CA1524, CA2524, and CA3524 have all the features of
the industry types SG1524, SG2524, and SG3524,
respectively. A block diagram of the CA1524 series is
shown In Fig. 1. The circuit includes a zener voltage
reference, transconductance error amplifier, precision R-C
oscillator, pulse-width modulator, pulse-steering flip-flop,
dual alternating output switches, and current-limiting and
shutdown circuitry. This device can be used for switching
regulators of either polarity, transformer-coupled dc-dc
converter, transformerless voltage doublers, dc-ac power
inverters, highly efficient variable power supplies, and polarity converter, as well as other power-control applications.
The CA 1524 is specified for the military temperature range
of -55 0 C to +1250 C.

• Positive and Negative Regulated Supplies
• Dual-Output Regulators

• Variable Power Supplies

The CA2524 and CA3524 'are speciifed for the
commmercial temperature range of OOC to 700 C. All types
operate over a supply voltage range of 8 to 40 V, have a
rated operating temperature range of -550 C to +125 0 C,
and are supplied in 16 lead, dual-in-line plastic packages
(E suffix, and dual-in-line frit-seal hermetic packages
(F suffix)). The CA3524 is available in chip form (H suffix).

Pinout

Maximum Rating,

• Flyback Converters
• DC-DC Transformer-Coupled Regulating Converters
• Single-Ended DC-DC Converters

16 LEAD DUAL-IN-L1NE PACKAGE
TOP VIEW

INV.INPUT
NON INV.INPUT
OSCOUT
(+) C.L.
SENSE
( -) C.L.
SENSE
RT
CT
GND

Absolute-Maximum Values

Input Voltage (Between VIN and GND Terminals) ............ 40V
Operating Voltage Range (VIN to GND) •.•••••.••.•••••• 8 to 40V
Output Current Each Output:
(Terminal 11, 120r13, 14) ........................... 100mA
Output Current (Reference Regulator) ••••..•••••••••••••• 50mA
Oscillator Charging Current.. • . • . • .. . .. . . . .. • • . . • • • . .. ... 5mA
Device Dissipation:
UptoTA=250 C ...................................... lW
Above TA = 250C .................... Derate linearly 8mW/oC
Opemting Temperature Range .................. -55 to +1250 C
Storage Temperature Range ••••••••.•••.•••.••. -65 to +1500 C

V REF
V+
EMITTER B
COLLECTOR B
COLLECTOR A
EMITTER A
SHUTDOWN
COMPENSATION
AND COMPARATOR

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed,
Copyright @ Harris Corporation 1991

2-13

File Number

1239.1

CA 1524, CA2524, CA3524

+5V TO ALL

INT. CKTS.

IKII
10

COMPENSATION
AND
COMPARATOR

SHUTDOWN
10Kli

92CM-3266~

®

GND

:;j".
Fig. 1 - Functional block diagram of CA 1524 series.

8-4DV--~------------------------------------------------~--,
2KII
IW

2KII
IW

r---r-----------------------------------------~-l--~--~12

2KII

92CM-32666

Fig. 2 - Open loop test circuitror CA 1524 series.

2-14

OUTA

CAI52~CA252~CA3524

ELECTRICAL CHARACTERISTICS at TA=-55 to +125°C for CA1524,

o to +70° C for the CA2524 and CA3524; V+=20 V·and f=20 kHz, unle.s otherwlle stated.
CHARACTERISTIC
Reference Section:
Output Voltage
Line Regulation
Load Regulation
Ripple Rejection
Short Circuit Current Limit
Temperature Stability
Long Term Stability
Oscillator Secllon:
Maximum Frequency
Initial Accuracy
Voltage Stability
Temperature Stability
Output Amplitude
Output Pulse Width (Pin 3)
Ramp Voltage Low
Ramp Voltage High
Capacitor Charging Current
Current Range
Timing Resistance Range
Charging Capacitor Range
Dead Time Expansion Capacitor on
Pin 3 (when a small osc. cap is used)
Error Amplifier Section:
Input Offset Voltage
Input Bias Current
Open Loop Voltage Gain
Common Mode Voltage
Common Mode Rejection Ratio
Small Signal Bandwidth
Output Voltage
Amplifier Pole
Pin 9 Shutdown Current
Comparator Section:
Duty Cycle
Input Threshold
Input Threshold
Input Bias Current
Current Limiting Section:
Sense Voltage For 25% Output
Duty Cycle
Sense Voltage T.C.
Common Mode Voltage
Rolloff Pole of R51 C3 + 064

TEST CONDITIONS

LIMITS
I
CA3524
I UNITS
r::A1524, CA25241
IMln. ITyp. IMax.1 Min. ITyp. IMax.1
4.8

V+=S to 40 V
. IL=0 to 20 mA
f=120 Hz, TA-25°C
VREF-O, TA=25° C
Over Operating Temperature Range
TA-25°C

-

5
10
20
66
100
0.3
20

5.2
20
50

5
10
20
66
100
0.3
20

5.4
30
50

300
5

-

300
5

-

-

-

2

0.03

-

-

1

-

4.6

-

-

1

-

V
mV
mV
dB
mA
%
mVlkhr
CJ

CT=O.OOl p.F, RT=2 KCl
RT and CT constant
V+-S to 40 V, TA=25° C
Over Operating Temperature Range
Terminal 3, TA-25°C
CT=O.Ol p.F, T A-25° C
Pin 7
Pin 7
Pin 7
0.03
(5-2 VB.)/RT
1.8
Pin 6
0.001
Pin 7

-

Pin3
VCM-2.5 V
VCM=2.5 V
TA=25°C
TA-25°C
Av= 0 dB, TA=25°C
TA=25°C

100

-

72
1.S

0.5

External Sink
% Each Output On
Zero Duty Cycle
Max. Duty Cycle

Terminal 9-2 V with Error Amplifier Set for Max Out, TA=25° C

-

1
2

120 1.8
0.1 p.OOl
1000 100
5
10

-

-

3.4

60
l.S

70
3

-

-

3.8

0.5

0.5
1
80

-

-

-

250
200

-

0

-

45

-

1
3.5
1

190 200

-

-1

I

3.5
0.5
0.6
3.5

-

-

-

i'

-

0.2

-

300

-

210

+1

-

-

3.5
0.5
0.6
3.5

2
1
SO

-

70
3

-

1
2

2

mA

120
0.1

KCl
p.F

1000

pF

10
10

mV
p.A
dB
V
dB
·MHz
V
Hz
p.A

-

3.4

-

-

3.8

-

250
200

-

0

-

-

z

kHz
%
%
%
V
p.s
V
V

45

-

%
V
V
p.A

180 200

220

mV

-

-

mV/oC

+1

-

-1

1
3.5
1

0.2

-

300

V
Hz

Highm
low.
where t = OSC period in microseconds
It,
t '" RTar with CT in microfarads and RT in ohms.
Output frequency at each output transistor Is half OSC frequency when each output is used separately and lis equal to the OSC frequency
when each output is connected In parallel.

'Ramp voltage at Pin 7

2-15

iii
rn
w rn
U!::

o=>

a:u
c.. a:
a:C3
w

~

CA1524,CA252~CA3524

ELECTRICAL CHARACTERISTICS (Cont'd)

. I
CHARACTERISTIC
Output Section: (Eech Output)
Collector-Emitter Voltage
Collector Leakage Current
Saturation Voltage
Emitter Output Voltage
Rise Time
Fall Time
Total Standby Current:" Is

TEST CONDITIONS

LIMITS
I
PA1524, CA25241
CA3524
I UNITS
IMln. ITyp. IMe• .jMln.ITyp.IMe•• 1
40

17
-

Vce=40 V
V+=40 V, Ic=50 mA
V+=20V
Rc=2 KO, TA=25°C
Rc=2 KO, TA=25° C
V+-40V

-

-

-

-

40

-

50
2

-

17
-

-

0.1
0.8
18
0.2
0.1
4

50
2

10

-

0.1
0.8
18
0.2
0.1
4

"Excluding oscillator charging current, error and
cUrrent limit dividers, and with outputs open.

---~---------------REF SECTION

A

r---------~---B

I

I
I
I

I
I

c

1

I
1

I

1__'-_-t_=_~_~_=_=_==_=_~_~~_===_~~~+==t:~==::t::l==~
92CL-32686

Fig. 3 - Schematic diagram.

2-16

-

10

V
IlA
V
V
/is
/is
mA

CA152~CA252~CA3524

A

- - - -- - - - - - - - --- - -- - - - -I
I

OUTPUT A

OUTPUT

B

I
I
I
I COLL. B
13

~

z

en

f3~
~L5

0::0
D.. 0::

0::0
W

:=:

o

D..

92CL-:S2686

Fig. 3 - Schematic diagram (cont'd).

2-17

CA152~CA2524,CA3524

CIRCUIT DESCRIPTION

Oscillator Section

Voltage Reterence Section

Transistors 042, 043 and 044, in conjunction with an
external resistor RT, establishesaconstantcharging current
into an external capacitor CT to provide a linear ramp
voltage at terminal 7. The ramp voltage has a value that
ranges from 0.6 to 3.5 volts and is used as the reference for
the comparator in the device. The charging current is equal
to (5-2VBE)/RT or approximately 3.6/RT and should be kept
within the range of 30 pA to 2 mA by varying RT. The
discharge time of CT determines the pulse width of the
oscillator output pulse at terminal 3. This pulse has a
practical range of 0.5ps to 5psfora capacitor range of 0.001
to 0.1 pF. The pulse has two internal uses: as a dead-time
control of blanking pulse to the output stages to assure that
both outputs cannot be on simultaneously and as a trigger
pulse to the internal flip-flop which controls the switching
of the output between the two output channels. The output
dead-time relationship is shown in Fig. 7. Pulse widths less
than 0.5 ps may allow false triggering of one output by
removing the blanking pulse prior to a stable state in the
flip-flop.

The CA 1524 series contains an internal series voltage
regulator employing a zener reference to provide a nominal
5-volt output, which is used to bias all internal timing and
control circuitry. The output of this regulator is available at
terminal 16 and is capable of supplying up to 50-mA output
current.
Fig. 4 shows the temperature variation of the reference
voltage with supply voltages of 8 to 40 volts and load
currents up to 20 mAo Load regulation and line regulation
curves are shown in Figs. 5 and 6, respectively.

'02

~,,".4\O

1.\..0'0

'01 .. 2.0 1.\..,"0

","" .40'1 _2.0 mA

y+.e

r

1:\..,"0

~

Y+.B I.\..s20mA

496

-flO

-40

-20

0

20

40

60

80

100

AMBIENT TEMPERATURE-·C

120

140

92CS-32668

Fig. 4 - Typical reference voltage as a function
of ambient temperature .

• .1

4.'
>

01

4.

~
t!: 4.D

0.000,

~~ 4.

i~

Fig .. 7 - Typical output stage dead time as a
function of timing capaCitor value.

4.1
3.9 AMBIENT TEMPERATURE I TA I. 2S·C
y t s 20V

3.

3.

o

~

M

~

~

~

~

REFERENCE OUTPUT CURRENT-mA

n

~
IleS-326S!

M

Fig. 5 - Typical reference voltage as a function
of reference output current.

> •
I

:g.
Il

~

4

o

2488
2.1.
2
488
0.001
0.01
0.1
TIMING CAPACITOR (CTI-,.F

10
20
30
SUPPLY VOLTAGE (Y+)-V

~

92CS-5287d

Fig. 6 - Typical reference voltage as a function
of supply voltage.

If a small value of CT must be used, the pulse width can be
further expanded by the addition of a shunt capacitor in the
order of 100 pF but no greater than 1000 pF, from terminal 3
to ground. When the oscillator output pulse is used as a
sync input to an oscilloscope, the cable and input capacitances may increase the pulse width slightly. A 2-Kn
resistor at terminal 3 will usually provide sufficient decoupling of the cable. The upper limit of the pulse width is
determined by the maximum duty cycle acceptable.
The oscillator period is determined by RT and CT, with an
approximate value of t=RTCT, where RT is in ohms, CT is in
pF, and t is in ps. Excess lead lengths, which produce stray
capacitances, should be avoided in connecting RT and CTto
their respective terminals. Fig. 8 provides curves for
selecting these values for a wide range of oscillator periods.
For series regulator applications, the two outputs can be
connected in parallel for an effective 0-9C% duty cycle with
the output stage frequency the same as the oscillator
frequency. Since the outputs are separate, push-pull and
flyback applications are possible. The flip-flop divides the
frequency such that the duty cycle of each output is 0-45%
and the overall frequency is half that of the oscillator.
Curves of the output duty cycle as a function of the voltage
at terminal 9 are shown in Fig. 10. To synchronize two or
more CA1524's, one must be designated as master, with
2-18

CAI52~CA252~CA3524

AMBIENT TEMPERATURE ITA). 2!l·C

y+. zov

2

4

.IIOO:CIL~A~:~otP;RIO~C~)!.~.'

o.a

0.4

4.'104

12
~6
2
2.4
2.8
COMPARATOR YOLTAGE- V

3.2

3.6

4

92C5-!2874RI

.CS-Nln

(!J

Fig. 10 - Typical duty cycle as a lunction 01
comparator vol/age (at terminal 9).

Fig. 8 - Typical oscillator period as a lunction
01 RT and CT.

z

en
en

~~
05
0::0

RTCT set for the correct period. Each of the remaining units
(slaves) must have a CTof 'hthe value used in the master and
approximately a 10% longer RTCT period than the master.
Connecting terminal3together on all units assures that the
master output pulse, which occurs first and has a wider
pulse width, will reset the slave units.
Error Amplifier Section
The error amplifier consists of a differential pair (OS6, OS7)
with an active load (061 and 062) forming a differential
transconductance amplifier. Since 061 is driven by a
constant current source, 062, the output impedance Roul'
terminal 9, is very high (~S MO).
The gain is:
Av =gmR=8 Ie R/2KT=10',
Rout

RL

where R = - - - , RL =00, Av ex: 10'
Rout+RL

Since Roul is extremely high, the gain can be easily reduced
from a nominal 10' (80 dB) by the addition of an external
shunt resistor from terminal 9 to ground as shown in Fig. 9.

80

HL-IO

TO

m

l'Z

:l

60
.0

1

w

~

40

~

o·

g

~

L

"L"-'"

..

~q,
-"(~

L"

.""

o~<:

"',

~

~4.rt"

10

•

4 ••

II

102

.

10'
FREQUENCY -Hz

..
10·

Since most output filter designs introduce one or more
additional poles at a lower frequency, the best network to
stabilize the system is a series RC combination at terminal 9
to ground. This network should be designed to introduce a
zero to cancel out one of the output filter poles. A good
starting point to determine the external poles is a 1000-pF
capacitor and a variable series SO-KO potentiometer from
terminal 9 to ground. The compensation point is also a
convenient place to insert any programming signal to
override the error amplifier. Internal shutdown and current
limiting are also connected at terminal 9. Any external
circuit that can sink 200pAcan pull this pointto ground and
shut off both output drivers.
While feedback is normally applied around the entire
regulator, the error amplifier can be used with conventional
operational amplifier feedback and will be stable in either
the inverting or non-inverting mode. Input common-mode
limits must be observed; if not, output signal inversion may
result. The internal S-volt reference can be used for
conventional regulator applications if divided as shown in
Fig. 11. If the error amplifier is connected as a unity gain
amplifier, a fixed duty cycle application results.

i~

..

.....".~ -

r----.

phase shift curves are shown in Fig. 10. The uncompensated
amplifier has a single pole at approximately 2S0 Hz and a
unity gain cross-over at 3 MHz.

4 ••

1,1 TA -55- TO 12!!ise

IL-50mA
V+-40 v

li
w
4

:

~

90"

""10'

92CS-:5261&

0.7

Fig. 9 - Open-loop error amplifier response
characteristics.

-75

-50

-25

0

25

50

75

100

125

150

175

AMBIENT TEMPERATURE ITA}-·C 92CS-!3240

The output amplifier terminal is also used to compensate
the system for ac stability. The frequency response and

Fig. 11 - Typical output saturation voltage as a
lunction 01 ambient temperature.

2-19

D..O::
O::U

w

:s:

o

D..

CA152~CA252~CA3524

Output Section

The CA1524 series outputs are two identical n-p-n transistors with both collectors and emitters uncommitted.
Each output transistor has antisaturation circuitry that
enables a fast transient response for the wide range of
oscillator frequencies. Current limiting of the output section
is set at 100 mA for each output and 100 mA total if both
outputs are paralleled. Having both emitters and collectors
available provides the versatility to drive either n-p-n or
p-n-p external transistors. Curves of the output saturation
voltage as a function oftemperature and output current are
shown in Figs. 11 and 12. respectively.

The internal 5-volt reference can be used for conventional
regulator applications if divided as shown in Fig. 14. If the
error amplifier is connected as a unity gain amplifier. a fixed
duty cycle application results.

There are a number of output configurations possible in the
application of the CA1524 to voltage regulator circuits
which fall into three basic classifications:
1. Capacitor-diode coupled voltage multipliers
2. Inductor-capacitor single-ended circuits
3. Transformer-coupled circuits
92CS-32676

Fig. 14 - Error amplifier biasing circuits.

Fig. 12 - Typical output saturation voltage as a
function of output current.

V+CANNOT
EXCEED 6V
NOTE:

v+ SHOULD BE IN THE 5V RANGE
AND MUST NOT EXCEED 6V

Device Application Suggestions

92CS-37297

For higher currents. the circuit of Fig. 13 may be used with
an external p-n-p transistor and bias resistor. The internal
regulator may be bypassed foroperation from a fixed 5-volt
supply by connecting both terminals 15 and 16 to the Input
voltage. which must not exceed 6 volts.

Fig. 15 - Circuit to allow external bypass of the
reference regulation.

To provide an expansion of the dead time without loading
the oscillator. the circuit of Fig. 16 may be used.

v""'-+ ...._ _

~

L

~::-+-~F-1

·~ll~~

P

8

IL TO IA
DEPENDING
ON CHOICE
FOR QI

aKa-3lef!

92CS-32667

Fig. 16 - Circuit for expansion of dead time. without using
a capacitor on pin 3 or when a low value
oscillator capacitor Is usad.

Fig. 13 - Circuit for expanding the reference current
capability.

2-20

CA152~CA252~CA3524

...,..-0
SAUSe

Table I - Input VI. Output voltage. and
Feedback Realstor Valuea tor
IL=40 mA (For capacitor-diode
output circuli In Fig. 21)
V+ (Min.)
R2
Vo
(V)
(V)
(Kn)

RI

.--

~

R2

-

II.
VOR2)
IMAX .-R;\VTH+RI+R2

RS

.

5
SENSE

-0.5
-2.5
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16

1SC =V:H WHERE

~

4

VTH =200mV

92CS·32677RI

Fig. 17 - Foldback current-limiting circuit used to
reduce power dissipation under shorted
output conditions.

-17

-18
-19
-20

8
9
10
11
12
13
14
15
16

6
10
11
13
15
17

19
21
23
25
27
29
31
33
35
37
39
41
43
45

17

~~

ceo
D..ce

Fig. 1B - Capacitor-diode coupled voltage multiplier
output stages. (Note: Diode 01 is necessary
to prevent reverse emitter-base breakdown 01
transistor switch SA).

SAlSa

r

r

~I

I
I

+Vo
v+< Vo

SA'Sa

V+---o""C.~I--f-

05
0::0

c... 0::

41.

0::0
W

50

o

c...

4"

4"

6"
Fig. 29 - Schematic diagram of digital readout scale.

92CS-33326

Dimensions and pad layout for CA3524H chip.

Dimensions in parentheses are in millimeters and are derived from
the basic inch dimensions as indicated. Grid graduations are in
mils (10- 3 inch).

The layout represents a chip when it is part of the wafer. When the
wafer is cut into chips, the cleavage angles are 57' instead of 90'
with respect to the face of the chip. Therefore, the isolated chip is
actually 7 mils (0.17 mm) larger in both dimensions.

2-27

CA3059
CA3079

mHARRIS

Zero-Voltage Switches
For 50/60 and 400Hz Thyristor Control Applications

August 1991

Features

Description

• Relay Control

• On-Off Motor Switching

The CA3059 and CA3079 zero-voltage switches are
monolithic silicon integrated circuits designed to control a
thyristor In a variety of AC power switching applications for
AC input voltages of 24V, 120V, 208/230V, and 277Vat
50/60 and 400Hz. Each of the zero-voltage switches
incorporates 4 functional blocks (see Fig. 1) as follows:

• Differential Comparator with Self-Contained Power
Supply for Industrial Applications

1. Limiter-Power Supply - Permits operation directly
from an AC line.

• Photosensitive Control

2. Differential On/Off Sensing Amplifier - Tests the
condition of external sensors or command signals.
Hysteresis or proportional-control capability may easily
be implemented in this section.

• Valve Control
• Synchronous Switching of Flashing Lights

• Power One-Shot Control
• Heater Control
• Lamp Control

3. Zero-Crossing Detector - Synchronizes the output
pulses of the circuit at the time when the AC cycle Is at
zero voltage point; thereby eliminating radio-frequency
Interference (RFI) when used with resistive loads.

Type Features
CA3059 CA3079
• 24V, 120V, 208/230V, 277Vat 50/60 ••••
or 400Hz Operation

..;

V

• Differential Input •••••••••••••••••••••••

..;

..;

• Low Balance Input Current (Max) - pA ••••

2

\'

• Built-In Protection Circuit for ••••••••••••
Opened or Shorted Sensor (Term 14)

• Sensor Range (Rx)- kO • • •• • •• •• • • • • •• •• 2 - 100

V
2 - 50

V
V

• DC Mode (Term 12) •••••••••••••••••••••
• External Trigger (Term 6) •••••••••••••••
• External Inhibit (Term 1) ••••••••••••••••

\'

• DC Supply Volts (Max) ••••••••••••••••••

14

• Operating Temperature Range (OC) ••.••

-55 to +125

10

4. Triac Gating Circuit - Provides high-current pulses
to the gate of the power controlling thyristor.
In addition, the CA3059 provides the following important
auxiliary functions (see Fig. 1).
1. A built-in protection circuit that may be actuated to
remove drive from the triac if the sensor opens or shorts.
2. Thyristor firing may be inhibited through the action of an
Internal diode gate connected to Terminal 1.
3. High-power dc comparator operation Is provided by
overriding the action of the zero-crossing detector. This
is accomplished by connecting Terminal 12 to Terminal 7.
Gate current to the thyristor is continuous when Terminal
13 is positive with respect to Terminal 9.
The CA3059 and CA3079 are supplied in 14 lead dual-inline plastic packages. They are is also available in chip form
(H suffix).

Pinouts
CA3079
TOP VIEW

CA3059
TOP VIEW
INHIBiT

FAIL • SAFE

DO NOT USE

SENSE AMP IN

DC SUPPLY

HIGH CURRENT
NEG. TRiGGER

ZCD OVERRIDE

HIGH CURRENT
NEG. TRIGGER

TRIGGER OUT

R DRIVER (COM)

TRIGGER OUT
ACIN

R DRIVER v+
TRIGGER IN

DO NOT USE
SENSE AMP IN
DO NOT USE
R DRIVER (COM)
R DRIVER v+

SENSE AMP REF

SENSE AMP REF

COMMON

COMMON

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright 6:) Harris Corporation t 991

2-28

File Number

490.1

CA3059, CA3079
MAXIMUM RATINGS. Absolute-Maximum Values at TA = 25° C
DC SUPPLY VOLTAGE (BETWEEN TERMS. 2 AND 7):
CA3059 ................................................................................................................... 14V
CA3079 ................................................................................................................... 10V
DC SUPPLY VOLTAGE, (BETWEEN TERMS. 2 AND 8):
CA3059 ................................................................................................................... 14V
CA3079 ................................................................................................................... 10V
PEAK SUPPLY CURRENT (TERMS. 5 AND 7) ............................................................................. ± 50 mA
OUTPUT PULSE CURRENT (TERM. 4) .................................................................................... 150 mA
POWER DISSIPATIONS:
Up to TA = 55°C - CA3059, CA3079 ...................................................................................... 700 mW
Above TA = 55°C - CA3059, CA3079 ................................................................... Derate linearly 6.67 mWI"C
AMBIENT TEMPERATURE RANGE:
Operating ...................................... , ........................................ , ........................ -55 to +125°C
Storage ......................................... , ................................................................ -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16" ± 1/32" (1.59 ± 0.79 mm) from case for 10 seconds max................................... , .............. +265 0 C

MAXIMUM
CURRENT
RATINGS

MAXIMUM VOLTAGE RATINGS alTA = 25°C

TERMINAL
NO.
1
Nota 3

2
3

4

5
Note 1

6

Note3

7

8
9
10

11
12
Nota 3

13

1 2
~~t.
3

3

4

5

.. .·

6

Not No.
1
3

7

8

9

10

11 12 13
Note

3

14

Note

2.3

liN

rnA

10

0.1

···· ··
·
.
.
· .······· ·
·. ·······
· · ·· ···
o. · · · · · · · ·
· ·
·
···· ·
···· · ·
· ·· · ·
··· ·
··
··

15
0
0 0 2 0
-15 -15 -14 -14
0
-15

10

-2
0" 0" 0 0 0
-14 -14 -14 -14 -14

•

0 0 150 10
-14 -14

2•
-10

7
-7
14

14
0
10
0

14

Nota 3

20
0

lOUT

rnA

·

0.1

150

50

10

2.5 14 6
2.5 0 -6

0.1

·
·
2

·

·

·
·

50

50

2

2

This chart gives the range of voltages which can be applied to the terminals listed horizontally

with respect to the terminals listed vertically. For example, the voltage range of horizontal
Terminal 6 to vertical Terminal 4 is 2 to -10 volts.
Note 1 - Resistance should be inserted between Terminal 5 and external supply or line voltage for limiting current into Terminal 5 to less than 50 rnA.
Note 2 - Resistance should be inserted between Terminal 14 and external supply for limiting
current into Terminal 14 to less than 2 mAo
Note 3 - For the CA3079 indicated terminal is internally connected and. therefore, should
not be used.

"For CA3079 (0 to -10 VI.
"Voltages are not normally applied between these terminals; however, voltages appearing
between these terminals are safe, if the specified voltage limits between all other terminals
are not exceeded.

2-29

CA3059, CA3079
Dissipation Rating

Input Series
Resistor (RS)

AC Input Voltage
(50/60 or 400 Hz)
VAC

for RS
W

Ul

24
120
208/230
277

2
10
20
25

0.5
2
4
5

NOTE:
Circuitry. within shaded areas. not included in

CA3079
• See chart
.. IC = Internal Connection· . DO NOT USE
(Terminal Restriction applies only
to CA30791.

NEGATIVE TEMPERATURE COEFFICIENT

Fig. 1 - Functional block diagram of CA3059 and CA3079.
-:' COMMON

"

--------------.

"

LINE

[

!NPUT

I

I
",.

)'Jj(RU5(O
GATEIJIII't[

I

[

,.

I

!I



~~

IZO-V RUS, 50-60 Hz OPERATION

0::>
0:0

c..o:
0:0
W

~

c..

~
g0.45

:.

~040

~O.35

AMBIENT TEMPERATURE (TAI--C

Fig. 6(c) - Peak output current (pulsed) vs ambient
temperature tor CA3059.

-50

-25

0

25

50

75

100

125

AMBIENT TEMPERATURE ITA I-·C

Fig. 7(b) - Input inhibit voltage ratio vs ambient temperature tor CA3059
andCA3079.
120 V RIIS, SO/6O-H~DPERATIOH
AMBJENT TEMPERATURE (TAJ. 250 c

ZERO

VOLTAGE

~o

~~~LLOSCOPE
HIGH·GAlN
INPUT

0.01
.l.LLRE5IHAMCEVAlUES

NOTE:CIRCUITRyWITHINSHADEO.fJtEA

Fig. 8(a) - Gate pulse duration test circuit with associated wavetorm
tor CA3059 and CA3079.

004

D.DS

006

0.07

0.01

0.09

jCfExnl .... F

Fig. 8(b) - Total gate pulse duration vs external capacitance tor CA3059
andCA3079.
«It---

L20VRMSSO/6Q_KaOPERATION

? 600

0.03

EXTERNAL CAPACITANCE

NOT INCLUDED IN CA3019

120VRMS.4OQ-H1(lPERATLOM

AMBIENTTEMPERATURE(TAJ·2S·C

AMBlall TEMPERA.ruRE (TAl· 2SOC

e~

;"
s

SOD

!l

L

i'OO

'M INEGATIVEd~/dd

004

O.OS

006

007

008

009

,

0.1

Fig. 8(c) - Pulse duration after zero crossing vs external capacitance
tor CA3059 and CA3079.

10

..

,,

EXTERMAL RESISTAMCE [RIExnl- kn

EXTERNAL CAPACITJJ«:E (C(EXTI)- pF

Fig. 8(d) - Total gate pulse duration vs external resistance tor CA3059.

2-33

CA3059, CA3079
100,

y+. 6V

120 YAMS SO/6o-Hz OPERATION

' 3V - . . r - " - f - - - '

01
-80 -60 -40 -20 0
20 40 60
60 100
AMBIENT TEMPERATURE ITA)-- C

120

140

92SS-4267

Fig. 9-0utput leakage current (inhibit mode) vs.
ambient temperature for CA3059' and
CA3079.

Fig. 10-lnput bias current test circuit for CA3059
endCA3079.

I

ZlOv IIMS

1~~~~O~~~f~~~~~~:SI:lOkll =="P=9f--,

I

o

600

220 V RMS, 50.f60-Hr OPERATION
INPUT RESISTANCE !RS1·ZOk!l

1'00f--+-+f-f-+-_-+1---++---t~--;
_

~

•

~ 200 ---~-

.

~~;:.-- ~

~ 200~::::::::....--

CURVE

~:;::;j!

A
B

~g~!}INI~~:EtodE¥~:t-l

006

008

[XTERNALCAPACITANCE-"F

006

0,04

0.02

-

110
"> 'p"'""".
60H,'!.
TIVEdv/dfl_

g

;:!

'-

FREQUENCY

EXTERNALCAPACITANCE-I"F

(b)
(a)

600

220 V RMS, SO/SO-HI OPERATION
INPUT RESISTANCE IRSJ-IOkQ

~t

~~ 400

• k::::
f-:::: ~ ~ ~

i~
~i

i!~

<0
.~

200

k::::;: ~ J::::;:::: po j.--- 01
: 1~~~:}INlt~:E'.i;:;)
~~~
:::;;;VE

~~

~

0

002

FREQUENCY

C

50 HZ} 'PllrOR POSI-

o

60 HI

00.

00'

TIVE dv/dlJ

008

01

EXTERNAL CAPACITANCE-,.F
EXTERNAL CAPACITANCE-.uF

(c)

(d) .

Fig. II-Relative pulse width and location of zero crossing for 220-volt operation for CA3059
BndCA3079.
SENSOR RESISTANCE-!5 k.fl

187 30

..~

=.:

TERMS. 7 AND 12 CONNECTED

>" 12~ 20

DC GATE CURRENT

58

~Nit) cp;30!5 9 )

MODEl~')O

:'!

TERM.12 OPEN

Moot

~JI.\..\..ltt

PULSED GATE cuRREN'T

-75

-50

-25

0

25

50

75

100

125

AMBIENT TEMPERATURE ITAI-·C

" "

AMBIENT TEMPERATURE

'2C$-18072

Fig. 12-Sensitivio/ vs. ambient temperature

.oc

Fig. 13-0perating regions for built-in protection
circuit for CA3059.

for CA3059 and CA3079.

2-34

CA3059, CA3079

r-,-

OFF

'ZOVAC
60 ••

15VOC+

'ON-06? R, C,
RI(MAX VALUE ALLOWABLE}-IM!1

Fig. 15-Line-operated thyristor control time
delay turn-on circuit.

Fig. 14-Line-operated one-shot timer.

C!l

z

(i5

lacn
0 .....

05
a:o


a:u
a.. a:
a:u
w

==
a..
0

Notes:
to = Total time delay = nl t + n2 t + •.. nnt.
C = Connect. For example, interconnect terminal a of the CD4020A and terminal A
of the CD4048A.
NC = No Connection. For example, terminal b of the CD4020A open and terminal B
of the CD4048A connected to +VDD bus.
Fig. 7Blb}-"Programming" table for Fig. 7Bla).

AC
SUPPLY
VOLTAGE

CA3059
OUTPUT
(PINS 4 AND 6)

CD4048A
OUTPUT

92CS-25988
Fig. 7Ble}-Timing diagram for Fig. 7Bla}.

2-37

CA3059, CA3079
OPERATING CONSIDERATIONS
Power Supply Considerations for CA3059
and CA3079
. The CA3059 and CA3079 are intended for
operation_as self-powered circuits with the
power supplied from an AC line through a
dropping resistor. The internal supply is
designed to allow for some current to be
drawn by the auxiliary power circuits.
Typical power supply characteristics are
given in Figs. 3(b) and 3(c).
Power Supply Considerations for CA3059
The output current available from the internal
supply may not be adequate for higher power
applications. In such applications an external
power supply with a higher voltage should be
used with a resulting increase in the output
level. (See Fig. 5 for the peak output current
characteristics). When an external power
supply is used, Terminal 5 should be con·
nected to Terminal 7 and the synchronizing
voltage applied to Terminal 12 as illustrated
in Fig. 5(a).

2. Set the value of Rp and sensor resistance
(RX) between 2 kn and 100 kn.
3. The ratio of RX to Rp. typically, should
be greater than 0.33 and less than 3. If
either of these ratios is not met with an
unmodified sensor over the entire antici·
pated temperature range, then either a
series or shunt resistor must be added to
avoid undesired activation of the circuit.
If-operation of _the protection circuit is desired under conditions other than those
specified above, then apply the data given
in F-ig. 13.
External Inhibit Function for the CA3059

A priority inhibit command may be applied
to Terminal 1. The presence of at least +1.2 V
at 10 IJ.A will remove drive from the thyristor.
This required level is compatible with DTL
or T2L logic. A logical 1 activates the inhibit
function.
DC Gate Current Mode for the CA3059

Operation of Built·in Protection for the
CA3059
A special feature of the CA3059 is the
inclusion of a protection circuit which.
when connected. removes power from the
load if the sensor either shorts or opens.
The protection ci rcuit is activated by
connecting Terminal 14 to Terminal 13 as
shown in Fig. 1. To assure proper operation
of the protection circuit the following
conditions should be observed:
1. Use the internal supply and limit the ex·
ternal load current to 2 rnA with a 5 kn
dropping resistor.

Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions
.. indicated. Grid gradations are in mils (10- 3 inch!.

Connecting Terminals 7 and 12 disables the
zero-crossing detector and permits the flow
of gate current on demand from the differential sensing amplifier. This mode of operation is useful when comparator operation i_s
desired or when inductive loads are switched.
Care must be exercised to avoid overloading
the internal power supply when operating
in this mode. A sensitive gate thyristor
should be used with a resistor placed between
Terminal 4 and the gate in order to limit the
gate current.
For a list of RCA thyristors, see RCA Thyristor
Data Bulletin, File No. 406, dated 5·75.

The photographs and dimensions represent a
chip when it Is part of the wafer. When the wafer
is cut into chips, the cleavage angles are 57"
instead of90° with respect to the face of the chip.
Therefore, the isolated chip is actually 7 mils
(0.17 mm) larger in both dimensions.

Dimensions and pad layout for CA3059H and CA3079H.

2-38

mHARRIS

CA3085,CA3085A
.CA3085B
Positive .Voltage Regulators
From 1.7V to 46V at Currents Up to 100mA

August 1991

Features

Description

• Up to 100 mA Output Current

The CA30SS, CA308SA, and CA308S8 are silicon monolithic
integrated circuits designed specifically for service as voltage
regulators at output voltages ranging from 1.7 to 46 volts at
currents up to 100 milliamperes.

• Input and Output Short-Circuit Protection
• Load and Line Regulation ••••••••••••••••••••••••• 0.025%
• Pin Compatible with LM100 Series

A block diagram of the CA3085 Series is shown in Fig. 1. The
diagram shows the connecting terminals that provide access to the
regulator circuit components. The voltage regulators provide
important features such as: frequency compensation, short-circuit

• Adjustable Output Voltage

Applications

protection, temperature-compensated reference voltage, current limiting, and booster input. These devices are useful in a wide range of

• Shunt Voltage Regulator

applications for regulating high-current, switching, shunt, and posi·
tive and negative voltages. They are also applicable for current and
dual-tracking regulation.

• Current Regulator
" Switching Voltage Regulator

The CA3085A and CA308S8 have output current capabilities up to
100 mA and the CA3085 up to 12 rnA without the use of external
pass transistors. However, all the devices can provide voltage
regulation at load currents greater than 100' rnA with the use of
suitable external pass transistors. The CA3085 Series has an
unregulated input voltage ranging from 7,S to 30V (CA308S), 7,5 to
40V (CA308SA), and 7.S to SOV (CA308S8) and a minimum
regulated output voltage of 26V (CA3085), 36V (CA3085A), and 46V
(CA308S8).

• High-Current Voltage Regulator
• Combination Positive and Negative Voltage Regulator
• Dual Tracking Regulator

TYPE

VIN
RANGE
V

VOUT
RANGE
V

MAX
lOUT
mA

MAX LOAD
REGULATION
%VOUT

CA3085
CA3085A

7.5 to 30
7.5 to 40

12·

CA30858

7.5 to 50

1.8t026
1.7t036
1.7t046

0.1
0.15
0.15

100
100

These types are supplied in the 8 lead TO-S style package (CA308S,
CA30S5A, CA308S8, and the 8 lead TO-S with dual-in-line formed
leads ("OIL-CAN", CA308SS, CA308SAS, CA30858S). The CA3085
is also supplied in the 8 lead dual-in-line plastic package ("MINIDIP", CA3085E), and in chip form (CA30B5H).

*This value may be extended to 100 rnA; however, regulation is not specified
beyond 12 mAo

Pinouts

Functional Block Diagram

8 LEAD PLASTIC DIP
TOP VIEW
COMPENSATION AND
EXTERNAL INHIBIT

OUT
CURRENT
BOOSTER

v+IN

V·

8 LEAD TO-5 OIL-CAN
8 LEAD TO-5 STYLE

6ehR'Q~
LIMIT

CURRENT
BOOSTER

v
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

2-39

File Number

491.1

CJ

:z
(j)
en

~~

0::::>
0:0

D..O:

0:0

W

~
D..

CA308~CA3085A,CA3085B

MAXIMUM RATINGS, ABSOLUTE-MAXIMUM VALUES.t TA. 250 C
POWER DISSIPATION: WITHOUT HEAT SINK

WITH HEAT SINK (TO-6 ONLY)

uptoTA= 55°C ............... 630mW

uptoTC= 5SoC .••• 1.6W

above TA = 55°C

above TC = 5sDc ••.• derate linearly at
16.7mWf'C

derate linearly @6.67 mWf'C

TEMPERATURE RANGE:
Operating ..•••••.•..••.•• ":55 to +1250 C
Storage . . . . • • • • . . • . • . . . .• -65 to +1500 C
UNREGULATED INPUT VOLTAGE:
CA3085 ......•.•..• .' .•......• 30 V
CA30B5A ... . . . . • . . • . . • . . . . • .• 40 V
CA3085B ..................... 50 V
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 t 1132 Inch (1.59:!: O.79mml
from case for 10 seconds m.x .•••••••• +2SSoC

Maximum Voltage Ratings
The following chart gives the range of voltages which can be applied to the terminals
listed vertically with respect to the terminals listed horizontal IV. For example. the
voltage range between vertical Terminal No.7 and horizontal Terminal No.1 is +3 to -10 volts.

MAXIMUM
CURRENT RATINGS

MAXIMUM VOLTAGE RATINGS
TERM·
INAL "5
No.

6

5

-

+5
-5

6

-

-

7
8
1

-

-

- -

-

7

1

8

2

.

,

3

.

.
-

-

+3
-10

-

+3
-10
+5
-1

.

-

+10

+10
0

.

..-

-t

-:t
0

2

-

-

-

-

-

-

3

-

-

-

-

-

-

-

4

-

-

-

-

-

-

-

liN
mA

lOUT
mA

5

10

1.0

6

1.0

-0.1

7

1.0

-1.0

are not exceeded.

8

0.1

10

t30V for CA30B5
40 V for CA30B5A
50V for CA3085B

1

20

150

2

150

60

3

150

60

4

-

No •

+t
0

0

J::~

4

+t
0
+t
0
+t
0

• Voltages are not normally
appl ied between these
terminals; however. voltages
appearing between-the. .'
terminals are safe, if the
specified voltage limits

between all other terminals

Substrate
& Case

V+,NQ}---,---t---4r----,r---~--------~
UNREGULATE
INPUT

Fig.2-Schematic diagram of CA3085 Series.

2-40

-

CA308~CA3085A,CA3085B

ELECTRICAL CHARACTERISTICS
LIMITS

TEST CONOITIONS
CHARACTERISTICS

SYMBOL

Test
Circuit

MIN.

[Unless indicated otherwise)

MAX.

MIN.

TYP.

1.6

1.8

1.5

1.6

3.3

4.5

TYP.

CA3085B

CA3085A

CA3085

T A ' 250 C

MAX.

MIN.

TYP.

MAX.

1.5

1.6

1.7

UNITS

'Fig. No.
Reference Voltage

VREF

4

V+IN = 15V

1.4

V+IN = 30V
QUiescent Regulator

V+IN = 40V

'quiescent

Current

V+IN
Input Voltage Range

MaXimum Output

Voltage
Minimum Output
Voltage

Input-Output Voltage
Differential
LImiting Current

load

7.5
V+IN = 30.4U.50V#; RL = 365 n;
Term. No.6 to God.

VOl min.)

V+IN = 30V

Temperature Coef·
ficient of Reference

and Output Voltages
load Transient
Recovery Time:
Turn On
Turn Off
lme TranSient
Recovery Time:
Turn On
Turn Off

36
1.8

120

96

RSCp· = 6n

a

IL'" 1 to lOOmA, RSCp - 0

TA:: OOC to +70o C

IL = 1 to 12mA, RSCp:: 0

0003

0.1

I L' I mA, RSCp - 0

0.025

0.1

IL - 1mA, RSCp - 0
TA:: oOe to +70o C
VNOISE

11
12

'0

12

IIVREF,
I1Vo

tON

tOFF

tON

40

7.5

16

V+IN = 25V
V+IN

=

25V

f:: 1 kHz

0.04

015

.50

7.5
47

46

37
1.6

1.7

1.6
3.5

38

28

IL = 1 to lOOmA, RSCp=

Ripple Rejection

Output ReSistance

30
27
1.6

V+ IN = l6V. V+ OUT = lOV

lme Regulation·

Equivalent NOIse

26

VIN,VOUT

.

Output Voltage

4.05

VIN(range)

Regulation

V

mA

3.65

= 50V

Volmax.)

ILiM

1.7

120
0.15

0.035

06

0.035

0.6

0.025

0.075

0.025

0.04

0.1

0.04

0.5

0.5

0.3

0.3

CREF - 0

50

50

45

CREF = 2~F

56

56

50

0.0035

mA

96
0.025

0.5

IL= 0, VREF = 1.6V

V

120

0.3

1.1

48

0.15

CREF = 0.22~F

0.075

V

96

CREF - 0

V+IN = 25V. f:: 1kHz

1.7

0.025

0.04

0.075

0.3

50
56
0.D75

0.08

%VOUT

%/V

mVp·p

dB
0.3

0.0035

0.0035

V
V

n
%/oC

V+'N = 25V, +50mA Step

~5

V+,N:' 25V, -SOmA Step

~5

V+'N

= 25V, f

= 1 kHz, 2V Step

tOFF

#30V (CA30B51, 40V(CA3085AI, 50V(CA30B5BI
• RSCP: Short·circuit protection resistance

• load Regulation

=

0.8

O.B

0.8

0.4

0.4

0.4

I1VOUT

X 100%

.. Line Regulation =

VOUr(initlall

(VOUT(initiall( (I1V1NI

TI
STANCOR TP3

Your

'.2

KO

10
KO.

5pF
35V

lKO

Your" 3 5V 10 20Y (0 TO 90mA)
REGULATION" 0 2~ (LINE AND LOAD)
RIPPLE < 0.5 mV AT FULL LOAD

92CS-IB093

Fig.3-Application of the CA3085 Series in a typical power
supply.

2-41

(I1VOUT'

~5
~5

X 100%

CA308~CA3085A,CA3085B

TEST CIRCUITS AND TYPICAL CHARACTERISTICS CURVES FOR CA3085 SERIES

IQU,EsaNT

'=1

CONNECT

~T=E~~____~AL~=V~IN~T=EA="~.N=O~.61-~_100PF
YREF.
+1.6 OPEN
OPEN
IQUIESCENT

+ 40 OPEN
Your (MAX.) 16Sn + 40 GROUND

Your (MIN,)

10 k

OPEN

CLOSED

-Vour"

92CS-IB094

1.6

( AI' A2)

-A-'-

"THE LIMITING CURRENT IS
INVERSELY PROPORTIONAL TO

.30 TERM. NO.1 OPEN

RSCp (SHORT.CIRCUIT PROTECTION RESISTANCE)
92CS-18097

Fig.4-Test circuit for VREF, Iquiescent, VOUT(max.),
VOUT(min.).

Fig.7- Test circuit for limiting current

i! :tH+-

: i,NPUT VOLTS IV+,N )-15

it

±l:
-75

a

- 50

- 25

25

50

75

100

125

AMBIENT TEMPERATURE" tTAl--C

Fig.5-lquietiCent vs. VtN'

Fig.8-ILIM vs. TA.
:INPUT VO

NORMALIZED CURVE GENERATED FROM
rQU1ESCENT vs V+'N CURVE WITH TA&2S-C=1

rs

{V~I.~~.':, .

E~':,~~/-~~!':;_~~:~2-LTj

)-25·C

1.1

::'"

l-

e!

.
>

PO,

I

z

0

5 -0.1
:>

Ii:
II:

l~
-0.3
0.8
-55

-50
-25
O'
25
50
75
AMBIENT TEMPERATURE (TA)-·C

100

-0.·

125

40

6'

80

100

LOAD CURRENT (I.L)- mA

92C5-18096

12CS-I7!51

Fig.9-Load regulation characteristics.

Fig.6-Normalized Iquiescent vs. TA.

2-42

CA308~CA3085A,CA3085B

TEST CIRCUITS AND TYPICAL CHARACTERISTICS CURVES FOR CA3085 SERIES

± INPUT VOLTS CV+IN). 20

+-

~.

OUTP~T VOLTS (V"'OUT)aIO

s.n
zo.04

o

!;;

...

~O.o3

820n

a:
~O.02
::i
lQOpF

loon

0.01

o

92CS-18099

-75

-50

-25
0
25
50
75
100
AMBIENT TEMPERATURE ITA)-·C

Cl

:z

125

en

ffirn

92CS-I7345

01:

Fig. , , - Test circuit for noise voltage.

Fig. 'O-Line regulation temperature characteristics.

o=>
a: 0
a. a:
a:u
w

isa.

TEST PROCEOURES FOR TEST CIRCUIT FOR
RIPPLE REJECTION AND OUTPUT RESISTANCE

S6n

Output Resistance

Your

EI

. J]

1. VIN" +25V, CREF = D. Short E1
2. Set ES2 at 1 kHz so that E2 = 4V rms
3. Read VOUT on a VTVM, such as a Hewlett·Packard.
HP400D or equivalent

Ol
300n

4. Calculate ROUT from ROUT" VOUT 'IRL/E2 )

8200
YTVM

HEWLETT

Ripple Rejection - I

PACKARD
HP 400D

11. T2" STAHCOR
TP·3

ES~

Conditions:

Conditions:

00
EQUIVALENT

loon

1. VIN'" +25V. CREF '" 0, Short E2
2. Set ES1 at 1 kHz so that E1 '" 3V rms

3. Read VOUT on a VTVM. such
or equivalent

_ _ _ _ _ _ _ _ _ _ _ _ _-.::.B::lA::C:::.,KT2 GREEN

~II

BLACK

Ripple Rejection - II
Conditions'
92CS-19000

IDa INPUT VOLTS IV+IN)=27V

4Tr

'"'"

'"

0

2,

I

~

-

t

-

~ : 1 " ..

"j'

I

••

..

.,...

.

-

/

I
OB

O<+l- 0.'

~O·~.OB
I-

0.06

0

0.04

.-

f

----

r-

0.2

a:
:>

i -.\

I

'

~

,

-

-.,...

'

.

-~
'

'"~ 1.3
;!
::i'"a:::

-

.S

0.01
2

• ••

2

1.2

~

'

o

1.1

o

'"::i

..

N

g'"

I

0.02

0.1

~

~~

'2

, .

+-t-J---;~~~'~+-r- + -t 4

6 AMBIENT TEMPERATURE ITA): 2S·C I

~

1. Repeat Ripple Relectlon I with CREF .2 ",F

'2- Test circuit for ripple rejection and output resistance.

Fig.

~

Hewlett·Packard, HP400Q

4. Calculate Ripple Relectlon from 2010g IE,JVOUTI

E2' IV O.S
_RED

& YElLOW-

'"uz

8S 8

I
4

••

10

2

•••

fREQUENCY If)- kHz

100

2

0.9
0.8

• ••

~

1000

_

_

0

~

~

~

~

~

AMBIENT TEMPERATURE ITA)--C

92CS-17350
92CS-17349

Fig. '3-ro vs. f.

Fig. '4-Normalized ro vs. TA.

2-43

CA308~CA3085A,CA3085B

TEST CIRCUIT AND TYPICAL CHARACTERISTICS CURVES FOR CA3085 SERIES

REFERENCE VOLTS (VREF) -+1.6V IAT

"5

TA·2~·C)

LOAD CURRENT (XL)"'O

~
I

Z

..

E
!:i

S!

I-

"

a.

I-

",a.

~§

..""
0

0

z

i

~!-O.I

10

"''''
zZ
"''''
"''''
QG-o.2
<1<1
-0.3
-15

-50

-25

0

25

50

75

100

125

o

AMBIENT TEMPERATURE ITA)-OC

20

40

60

eo

100

OUTPUT MILLJAIoIPERES {ZOUTI

92,CS-I7346

'2CS-llao!

Fig. 15- Temperature coefficient of VREF and VOUT.

Fig.17-Dissipation limitation (V/N-VOUT

IOOIlF

l-'\N'V-._----.---<(J VbUT • 15 V

QUIESCENT OUTPUT
CURRENT ~ 1.5 mA

rTtr(Off)

VOUT

VPULSE
GEN.

_

tIlLS/em

92CS-19001

Fig. 16- Tum-on and tum-off recovery time test circuit with
associated waveforms.

2-44

lIS.

'OUT),

CA308~CA3085A,CA3085B

TYPICAL REGULATOR CIRCUITS USING THE CA3085 SERIES

Your
{REGULATED
OUTPUT)

(!I

z

VOUT

Fig.1B- Typical high-current voltage regulator circuit.

iii

en
~~
oS
a: (.)
c.. a:
a:C3
w

s:
o
c..

*lL=M2001lA.:!:IL ':!!:2A
QI

VOUT

ANY H·P·H SILICON TRANSISTOR
THAT CAN HANDLE A 2A
LOAD CURRENT SUCH AS
RCA·2H1772 OR eOUIVALEtH

92C5-\9004

ALL RESISTANCE VALUES ARE IN OHMS

Fig. 19- Typical current regulator circuit.

01 RCA·2N2102 OR eQUIVALENT
02 ANY P-M-P SILICON TRANSISTOR
(RCA·2N5322 OR EQUIVALENT)
Q3

ANY H.P-N SILICON TRANSISTOR THAT CAN

.Your = ~RI:1R2)
"RSCp SHORT·CIRCUIT
PROTECTION RESISTANCE

HANDLE THE DESIRED LOAD CURRENT
(RCA·2Nl172 OR EQUIVALENT)

Fig.21-Combination -positive and negative voltage regulator
circuit.

I } - - . . -_ _-OUTPUT

O.OOII'F
ALL RESISTANCE VALUES ARE IN OHMS

92CS-\9005

DJ RCA·1NI76JA OR EQUIVALENT
QI RCA·2NSl22 OR EQUIVALENT
-RI ; 0.7 IL (MAX.)

Fig.20- Typical switching regulator circuit.

2-45

til HARRIS

HV250

PRELIMINARY

Half Bridge
Complementary MOSFET Driver

May 1991

Features

Description

•
•
•
•
•
•
•

The HV2S0 is a monolithic dlelectrically Isolated high voltage integrated circuit. The circuit provides an interface from
digital signals to the gates of complementary power
MOSFETs. The circuit has wide supply voltage range, from
BOVDC to 450VDC in unipolar connection or :l:40VDC to
+450VDC and -100VDC. In addition the logic supply can
float within the high voitage rails.

Bipolar or Unipolar Supply Operation
Wide Supply Range ••••••••• :l:40V to +4S0V, -100V
Complete MOSFET Protection
High Output to Logic Supply Isolation
High Peak Output Current ••••••••••••••••••••••• 2A
Fast Switching Times •••••••••••••••••••••••• 100ns
Frequency Range •••••••••••••••••••••• DC -30kHz

The inputs are TIL compatible when the logic supply is SV,
but will operate up to 15V logic supply.

Applications
•
•
•
•
•

The outputs provide up to 2A current spikes to drive the
gates of power MOSFETs. The actual voltage that the gates
are driven to is set by the user, up to 20V for VGS.

High Switchmode Power Supplies
PWM Servo Drives
Stepper Motor Drives
DC-DC Converters
Uninterruptible Power Supplies

Also on board the chip is an overcurrent sense circuit,
which independently sense overcurrent on the high side
and the low side. An overcurrent condition sets a latch that
disables both outputs. In order to enable the output the
reset input must be toggled.

Ordering Information
PART
NUMBER
HV250CP

TEMPERATURE
RANGE
OOC

FAULT

RESET

r

LOW SIDE-

!

swrrCH

Y-t?-t =!

I·OCS~

-----r·vcL1
o

L

I

1 _ _ _ _ _ _ _ _ _ _ _ VEE.J

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed,
Copyright @) Harris Corporation 1991 • Offered at a later date.

2-46

File Number

2846

Specifications HV250
Absolute Maximum Ratings

Operating Temperature Range

Voltage Between +Vs and -VS .•••••••••.••.•••••••••.••• SOOV
Voltage Between +VI and -VI ••••••••••••••••••.•••••.••.•• 30V
Voltage Between -VS and -VI ..••.•••.•••••.•••.•••••.••. 2S0V
Peak Output Current ..••..•••.••..•.•.....•.•..•••••.•••.• 2A
Logic Input Voltage ••.••.......••..••.......•..••••..•••. +VL
Over Current Sense to 1Vs I •••••••••••••..••••.••...•••.••• 7V
Fault Output Current. • • • . . • • • . • • • • • • • . • • . • . • • . • • • • . • . . •. 1mA

HV250CP ••.•••••••.••••..••••.••••.••••• 00C:$TA:$+7S0 C
HV2S0lP ••.•••.•••••.•••••••.•.••••.••• -400C :$ TA :$ +8So C
HV250MJ* .•••.••...•••..•..•••...•••.. -SSoc :$ TA :$ +12So C
Storage Temperature Range •••.••••••.•• -6So C :5 TA:$ +1S0 0 C
Maximum Junction Temperature ••••••••••••••••••••••• +17So C

Electrical Specifications vcc

* Offered at a Later Oate

= +40V, VEE = -40V, CL = 10nF, VL = SV Unless Otherwise Specified
HV250CP, HV2SOIP

PARAMETER

TEMP

MIN

Input Voltage, High (VI H)
Input Voltage, Low (VILl
Input Current (IIH)

Full
Full
+2SoC

2.4

-

Input Current, Low (11Ll

Full
+2SoC

TYP

MAX

UNITS

-

V
V

INPUT CHARACTERISTICS

Full
+2S0C
Full

-1S0

-

-

I1A
I1A
I1A
I1A

80
7S

100
100

120
12S

mV
mV

Turn-On Oelay (T01, T03)

+2SoC

-

-

1
1

~s

Turn-On Oelay Skew (T01, TOal

Full
+2SoC

-

ns

Overcurrent Input Threshold

-

-1S0

0.8
300
300

-

TRANSFER CHARACTERISTICS

Full
+2SoC
Full
+2SoC

Turn-Off Oelay (T02, TO 41
Turn-Off Oelay Skew (T02, T04)

Current Limit Sense to Fault Output Turn-Oil Oelay

Full
+2S0C
Full
+2SoC

Reset Oelay (T0s!

Full
+2SoC

Current Limit Sense to Output Turn-Off Oelay

Full

-

SO
SO

±300
±300

-

-

1
1

±100
±100
SOO

-

SOO

-

-

1S0
1S0

~s

ns
~s
~s

ns
ns
ns
ns
ns
ns

-

SOO
SOO

-

-

ns
ns

-

100
100

150
150

ns
ns
V
V
V
V
V
V

OUTPUT CHARACTERISTICS
Output Rise Time
Output Fall Time
oun Voltage (High)
oun Voltage (Low)

Full
Full
Full
Full
Full
Full
Full
Full

OUT2 Voltage (High)
OUT2 Voltage (Low)
Fault Output (VOH)
Fault Output (VOL)

-

+VS-0.2

-

-

+VS-19

-

-VS+0.2

-

-

0.8

-

-

200
200
4

-VS+19

-

4.5

-

-

POWER SUPPLY
Full
Full
Full

ICC
lEE
IL

2-47

I1A
I1A
mA

CJ

:z

en
f3(1)

01:::

o=>
0:0
c..o:
0:<3

w

~
c..

HV250
Parameter Definitions

(Refer to Switching Waveforms)

SYMBOL

DEFINITIONS

T02

Delay time as measured from the logic Input high to low transition (1 to 0) at the 10% point, to the 10% point of the
output transition for the high side switch.

TDI

Delay time as measured from the logic input low to high transition (0 to 1) at the 10% point, to the 10% point of the
output transition for the high side switch.

T04

Same as T00-1 for the low side switch.

T03

Same as T 01-1 for the low side switch.

TRI

Output rise time from the 10% - 90% points for the high side switch.

TR2

Output rise time from the 1 0% - 90% points for the low side switch.

TFI

Output fall time from the 10% - 90% pOints for the high side swHch.

TF2

Output fall time from the 10% - 90% points for the low side switch.

T05

Delay time as measured from the overcurrent Input 10% point to the fault output high to low transition at the 10%
point

T06

Delay time as measured from the reset Input 10% polnlto the fault output low to high transition at the 90% point

T07

Delay time as measured from the overcurrentl input 10% poinlto output 1 low to high transition althe 90% point.

T06

Delay time as measured from the overcurrent 2 input 10% pOinlto output 2 high to low transition at the 10% point.

Switching Time Test Circuits

INPUT

0---+-1

~>-+---.--+---o OUTPUT

INPUT

-

'VL

0---+-1

> - + - - - . - - 0 OUTPUT

-Vs

+sv
INPUTI
·0.4V
·Vs

INPUT2

10'lI0

10%
-O.4V---JI
.VS + 1 B V - - -

90%

OUTPUT1

OUTPUT2
-VS ----..;.;.;..--1'

FIGURE 1. INVERTING DRIVE SWITCHING TIME (HIGH SIDE)

2-48

FIGURE 2. NON-INVERTING DRIVER SWITCHING TIME
(LOW SIDE)

HV250
Overcurrent Test Waveforms
OVER CURRENT TEST CIRCUIT

Vee

OVERCURRENT
INPUT
(1 OR 2)

OUT1

+ Vs - 20 _ _400/
OUT2 - Vs + 20 _ _-!=~

FAULT
OUTPUT

RESET
INPUT

5V---F"5V-----OV _ _ _ _ _ _~l~o%~~

90%
CI

:z
Ui
U)

w

U)

g5
ceo
I>..ce

ceo
W
~

o

I>..

2-49

mHARRIS

HV255

PRELIMINARY

Half Bridge
Complementary MOSFET Driver

May 1991

Features

Description

•
•
•
•
•
•
•

The HV255 is a monolithic dielectrically isolated high volt·
age integrated circuit. The circuit provides an interface from
digital signals to the gates of complementary power
MOSFETs or IGBTs. The circuit has wide supply voltage
range, from 80VDC to 450VDC in unipolar connection or
±40VDC to ±225VDC. In addition the logic supply can float
within the high voltage rails.

Bipolar or Unipolar Supply Operation
Wide Supply Range •••••••••••••••• ±40V to ±225V
Complete MOSFET Protection
High Output to Logic Supply Isolation .
High Peak Output Current •••••.•••••.•••••••••••• 2A
Fast Switching Times •••••••••••••••••••••••• 100ns
Frequency Range •••••••••••••• ~ •• 10kHz to 100kHz

The Inputs are TIL compatible when the logic supply is 5V,
but will operate up to 15V logic supply.

Applications
•
•
•
•
•

The outputs provide up to 2A current spikes to drive the
gates of power MOSFETs or IGBTs. The actual voltage that
the gates are driven to is set by the user, up to 20V for VGS.

High Switchmode Power Supplies
PWM Servo Drives
Stepper Motor Drives
DC-DC Converters
Uninterruptible Power Supplies

Also on board the chip is an overcurrent sense circuit,
which independently sense overcurrent on the high side
and the low side. An overcurrent condition sets a latch that
disables both outputs. In order to enable the output the
reset Input must be toggled.

Ordering Information
PART
NUMBER
HV255CP
HV2551P
HV255MJ*

TEMPERATURE
RANGE

DESCRIPTION

OOC -~--,--+---oOUT~

INPUT

-

· VL

0---+-1

>-+--.....- - 0 OUT~

·Vs

·Vs

+sv
INPUTI
·O.4V
·Vs

INPUT2

10%

10'1&
·O.4V---jJ

9O'l6

OUTPUTI

OUTPUT2

-r

-V __________
__
10'1&
S

FIGURE 1. INVERTING DRIVE SWITCHING TIME (HIGH SIDE)

2-52

FIGURE 2. NON-INVERTING DRIVER SWITCHING TIME
(LOW SIDE)

HV255
Overcurrent Test Waveforms
OVERCURRENT TEST CIRCUIT

Vee

OVERCURRENT
INPUT
(1 OR 2)

oun
+ Vs ,20'--4.../
OUT2 'VS+20---j:~

FAULT
OUTPUT

RESET
INPUT

2-53

5V'---!=:;;;:

5V-----OV _________~1~~~~

9~

HV350

mHARRIS
PRELIMINARY

Half Bridge
N-Channel MOSFET Driver

May 1991

Features

Description

•
•
•
•
•
•
•

The HV350 is a monolithic dlelectrically Isolated high volt·
age integrated circuit. The circuit provides an interface from
digital signals to the gates of totem pole power MOSFETs
or IGBTs. The circuit has wide supply voltage range. from
40VDC to 450VDC. In,additlon the logic supply can float
within the high voltage rails.

Unipolar Supply Operation
Wide Supply Range •••••••••••••••• +40V to +450V
Complete MOSFET Protection
High Output to Logic Supply Isolation
High Peak Output Current ••••••••••••••••••••••• 2A
Fast Switching Times •••••••••••••••••••••••• lOOns
Frequency Range •••••••••••••••••••••• DC -30kHz

Applications
•
•
•
•
•

The outputs provide up to 2A current spikes to drive the
gates of power MOSFETs or IGBTs. The actual voltage that
the gates are driven to Is set by the user. up to 20V for VGS.

Switch mode Power Supplies
PWM Servo Drives
Stepper Motor Drives
DC-DC Converters
Uninterruptible Power Supplies

Also on board the chip is an overcurrent sense circuit.
which independently sense overcurrent on the high side
and the low side. An overcurrent condition sets a latch that
disables both outputs. In order to enable the output the
reset Input must be toggled. An oscillator and charge pump
current are Integrated for high side operation.

Ordering Information
PART
NUMBER
HV350CP
HV350lP
HV350MJ*

TEMPERATURE
RANGE

DESCRIPTION

OOC +1S0o C
Maximum Junction Temperature ••.••.•••..••••.••••••• +17S oC

Electrical Specifications

vcc

s:
s:

* Offered at a Later Date

= +40V. VEE = GND. CL = 10nF. VL = SV Unless Otherwise Specified
HV3S0CP. HV350fP
TEMP

MIN

TYP

Input Voltage. High {VI H)

Full

2.4

-

Input Voltage. Low (VII)
Input Current (IIH)

Full
+2SoC

Input Current. Low {IIU

Full
+2SoC

Overcurrent Input Threshold

Full
+2SoC

PARAMETER

MAX

UNITS

-

V
V

INPUT CHARACTERISTICS

Full

-

-

-

0.6

-

-

-1S0

-

IlA
IlA
IlA
IlA

60
75

100

120

mV

100

125

mV

-

1

Jls
Jls
ns

-150

-

300
300

TRANSFER CHARACTERISTICS

Turn-On Delay Skew (TD1. TD3)

+250 C
Full
+2SoC

Turn-Off Delay (TD2. TD4)

Full
+2SoC

Turn-Off Delay Skew (TD2. TD4)

Full
+2SoC

Current Umit Sense to Output Turn-Off Delay

Full
+2SoC

Current Umit Sense to Fault Output Turn-Off Delay

Full
+250 C

Reset Delay (TD6)

Full
+2SoC

Turn-On Delay (TD1. TD3)

-

-

-

50
SO

:1:300
:1:300

:1:100
:1:100
SOO
SOO

-

1

-

ns

1

Jls

1

Jls
ns

-

ns

-

ns

1S0

ns
ns

1S0

ns

-

SOO

Full

-

SOO

-

-

100
100

150
1S0

ns
ns

-

V

0.5

V

ns
ns

OUTPUT CHARACTERISTICS
Output Rise Time
Output Fall Time
oun Voltage (High)

Full
Full

-

Full

+VS+19

oun Voltage (Low)

Full

-

OUT2 Voltage (High)

Full

19

OUT2 Voltage (Low)

Full

-

Fault Output (VOH)
Fault Output (YoU

Full
Full

4.S

-

-

0.5

V

-

V
V

0.6

V

POWER SUPPLY
ICC

Full

lEE
IL

Full
Full

2-55

-

-

-

2

mA

2
4

mA
mA

C!J

:z

u;

fflU)

01-

05
a: 0
a.. a:
a:o
w

;;:

o

a..

HV350
Parameter Definitions

(Refer to Switching Waveforms)

SYMBOL

DEFINITIONS

T02

Delay time as measured from the logic input high to low transition (1 to 0) at the 10% point, to the 10% point of the
output transition for the high side switch.

TOI

Delay time as measured from the logic Input low to high transition (0 to 1) at the 10% point, to the 10% point of the
output transition for the high side switch.

T04

Same as TOO-l for the low side switch.

T03

Same as T 01-1 for the low side switch.

TRI

Output rise time from the 10% - 90% points for the high side switch.

TR2

Output rise time from the 10% - 90% pOints for the low side switch.

TFI

Output fall time from the 1 0% - 90% points for the high side switch.

TF2

Output fall time from the 10% - 90% points for the low side switch.

T05

Delay time as measured from the overcurrent input 10% point to the fault output high to low transition at the 10%
point

T06

Delay time as measured from the reset input 10% pointto the fault output low to high transition althe 90% point.

T07

Delay time as measured from the overcurrent 1 input 10% point to output 1 low to high transition at the 90% point.

T08

Delay time as measured from the overcurrent 2 input 10% poinlto output 2 high to low transition at the 10% pOint.

Switching Time Test Circuits
+VS

veOOST

INPUT

o---f-l

+VS

~>-+--t---O OUTPUT HI
~--~------~FOBK

INPUT

0---+--1

>-f--......--o OUTPUT
·VS

INPUTI

INPUT2

10'1&

·0.4V-----.;JrTRI

T02

·O.4V

10'1&

T03

TFI

·VS + I 8 V - - -

·VS + I 8 V - - -

OUTPUTI

TR2

T04

TF2

OUTPUT2

10'1&

OV------r

-Vs

FIGURE 1. INVERTING DRIVE SWITCHING TIME (HIGH SIDE)

2-56

10'1&

FIGURE 2. NON-INVERTING DRIVER SWITCHING TIME
(LOW SIDE)

HV350
Overcurrent Test Waveforms
OVER CURRENT TEST CIRCUIT

Vee

OVERCURRENT
INPUT

OUTl

+VS+20 _ _-+-...

OUT2 -VS+20---+-...

FAULT
OUTPUT

fN--+...

RESET
INPUT
OV-----~~~~

2-57

m

HV355

HARRIS

PRELIMINARY

Half Bridge
N-Channel MOSFET Driver

May 1991

Features

Description

•
•
•
•
•
•
•

The HV355 Is a monolithic dielectrically isolated high voit·
age integrated circuit. The circuit provides an interface from
digital signals to the gates of totem pole power MOSFETs
or IGBTs. The circuit has wide supply voltage range, from
40VDC to 450VDC. In addition the logic supply can float
within the high voltage rails.

Unipolar Supply Operation
Wide Supply Range •••••••••••.•••• +40V to +450V
Complete MOSFET Protection
High Output to Logic Supply Isolation
High Peak Output Current •••••••••••••••••••.••• 2A
Fast Switching Times ••••••••••••••.••••••••• 100ns
Frequency Range ••••••••••••••••• 10kHz to 100kHz

Applications
•
•
•
•
•

The outputs provide up to 2A current spikes to drive the
gates of power MOSFETs or IGBTs. The actual voltage that
the gates are driven to is set by the user, up to 20V for VGS.

Switchmode Power Supplies
PWM Servo Drives
Stepper Motor Drives
DC-DC Converters
Uninterruptible Power Supplies

Also on board the chip is an overcurrent sense circuit,
which independently sense overcurrent on the high side
and the low side. An overcurrent condition sets a latch that
disables both outputs. In order to enable the output the
reset input must be toggled. An oscillator and charge pump
current are integrated for high side operation.

Ordering Information
PART
NUMBER

TEMPERATURE
RANGE

DESCRIPTION

OOC~TA<+750C

16 Pin Plastic DIP

HV3551P

-40oC < TA S +850 C

16 Pin Plastic DIP

HV355MJ*

-550 C $.TA $. +1250C

16 Pin Ceramic DIP

HV355CP

The inputs are TTL compatible when the logic supply is 5V,
but will operate up to 15V logic supply.

Pinout

Functional Diagram
HV355CP (16 PIN PLASTIC DIP)
TOP VIEW

+YCL

oun
FDBK

+ocs
·YCL
INI

OUT2

r

r----~

I LOW SIDE
SWITCH

~1N2~Lr"--r~1

I
I

.YeLI
I

"t-oUT21

t

LVEE

L- _ _ _ _

I
JI

FAULT

RESEr

·oes
CAUTION: These devices are sensitive to electrostatic discharge. Proper
Copyright @ Harris Corporation 1991

I.e. handling procedures should be followed.

... Offered at a later date.

2-58

Ale Number

2849

Specifications HV355
Absolute Maximum Ratings

Operating Temperature Range

Voltage Between +VS and -VS ••.••••.•.•••••.•.••••.••.• 500V
Voltage Between +VI and -VI •••.•••...••.•.••••.••••.•..•. 30V
Voltage Between -VS and -VI ••...•...••••.•••••••••••..•.• OV
Peak Output Current ••..••.........•....•...••••..•••..••• 2A
logiC Input Voltage .••••...••. . . • • . . . • • • • • • • • • • • • • • • • • . •• + VI
Over Current Sense to 1Vs I ...•••..•••.•••.•.•••..••••••••• 7V
Fault Output Current. • • • . . . • • • . . • • • . . . • . • . . • • . • • • • • • • • •• 1mA

HV355CP •••••••.••••••..•••••••.•••••••• oOC $. TA :S +75 0 C
HV3551P ..••..•••...•••..•••...•••..•.• -400C:S T A :S +850 C
HV355MJ* .•••••••••...•••...•••..••••. -55°C $. TA$.+ 1250 e
Storage Temperature Range .•••••••••.•• -650C :S TA $. +1500 C
Maximum Junction Temperature ••••.••.•••••••••.••••• +175 0 C

Electrical Specifications vec

* Offered at a Later Oate

= +40V, VEE = GNO, CL = 10nF, VL = 5V Unless Oth~rwise Specified
HV355CP, HV3551P

PARAMETER

TEMP

MIN

TYP

MAX

UNITS

Input Voltage, High (VI H)

Full

2.4

V

-

0.8
300

pA

300

pA

oS

Input Current, Low (IlL)

Full
+250 C

-1S0

-

pA

a.

Full

-lS0

-

V

Input Current (IIH)

Full
+250 C

-

-

Input Voltage, Low (VIL)

-

pA

Overcurrent Input Threshold

+250 C

80

100

120

mV

Full

7S

100

12S

mV

+2SoC

-

-

1

1'8

1

I's
ns

INPUT CHARACTERISTICS

-

TRANSFER CHARACTERISTICS
Turn-On Oelay (To 1,T03)

Full
Turn-On Oelay Skew (T01, T03)

+2SoC

Turn-Olf Oelay(T02, T04)

+2SoC

Full
Full
Turn-Olf OelaySkew (T02, T04)

+2SoC

Current Umit Sense to Output Tum-Olf Oelay

+2SoC

Current Umit Sense to Fault Output Turn-Off Oelay

Full
+2SoC

Reset Oelay (T06)

Full
+250 C

Full

Full

-

-

-

-

:1:300
:1:300

-

:1:100
:1:100
SOO
SOO

50

-

-

SOO

SO

-

500

-

ns

1

I's

1

I's
ns

-

ns
ns

-

ns

lS0

ns

150

ns

-

ns
ns

OUTPUT CHARACTERISTICS
Output Rise Time

Full

lS0

ns

Full

-

100

Output Fall Time

100

150

ns

OUTl Voltage (High)

Full

+VS+19

-

V

OUTl Voltage (Low)

Full

-

OUT2 Voltage (High)

Full

19

-

OUT2 Voltage (Low)

Full

-

Fault Output (VOH)

Full

4.5

Fault Output (VOL)

Full

-

ICC

Full

-

lEE
IL

Full

-

O.S

V

-

V

O.S

V
V

-

-

0.8

V

-

200

pA

POWER SUPPLY

Full

2-59

-

-

200

pA

4

mA

CI

:z

rn
[3U)

010::0
0::
0::0

w

;;::

oa.

HV355
Parameter Definitions

(Refer to Switching Waveforms)

SYMBOL

DEFINITIONS

T02

Delay time as measured from the logic input high to low transition (1 to 0) at the 10% point, to the 10% point of the
output transition for the high side switch.

TDI

Delay time as measured from the logic Input low to high transition (0 to 1) at the 10% point, to the 10% paint of the
output transition for the high side switch.

T04

Same as T 00-1 for the low side switch.

TD3

Same as TD1-l for the low side switch.

TRI

Output rise time from the 10% - 90% points for the high side switch.

TR2

Output rise time from the 10% - 90% points for the low side switch.

TFI

Outpullall time from the 10% - 90% points for the high side swHch.

TF2

Output fall time from the 10% - 90% points for the low side switch.

T05

Delay time as measured from the overcurrent input 10% point to the fault output high to low transition at the 1 0%
point

T06

Delay time as measured from the reset input 10% poinlto the fault output low to high transition at the 90% point

T07

Delay time as measured from the overcurrent 1 input 10% poinlto output 1 low to high transition at the 90% point.

T08

Delay time as measured from the overcurrent2 input 10% poinlto output 2 high to low transition althe 10% point

Switching Time Test Circuits
VBOOST

INPUT

0---1--1

~>-+--f----o OUTPUT HI

G.

t - -......---oFDBK
INPUT

0---+-1

>-+-__.--0 OUTPUT
G.

INPUTI
·0.4V

INPUT2

10!!.
TOI

-0.4V

TRI

-VS+18V---

T03
-VS + I 8 V - - -

OUTPUTI
OV

10'1&

TFI

TR2

T04

TF2

OUTPUT2

10'1&

-Vs

FIGURE 1. INVERTING DRIVE SWITCHING TIME (HIGH SIDE)

2-60

10'1&

FIGURE 2. NON-INVERTING DRIVER SWITCHING TIME
(LOW SIDE)

HV355
Overcurrent Test Waveforms
OVERCURRENT
INPUT

OVER CURRENT TEST CIRCUIT

Vcc

oun

+VS+20

OUT2 -Vs +20

FAULT
OUTPUT

5V

CJ

RESET
INPUT

:z

OV

us
en

~~

o=>
0:0
a..

0:

0:0
w

~

2-61

mHARRIS

HV400

PRELIMINARY
High Speed MOSFET Driver

May 1991

Features

Description

• Fast Fall Times •••••••••••••••••••• 22ns (10,OOOpF)

The HV400 is a single monolithic, non-inverting high speed
driver designed to drive large capacitive loads at high slew
rates. The device is optimized for capacitive loads in the
5,000pF to 1OO,OOOpF range. It featues an output stage ca'
pable of sourcing up to 6A through the high-side NPN
switch and sinking up to 30A through the low-side SCR
switch. Rise and fall times of 70ns and 30ns respectively
are achieved driving a 20,OOOpF load. The output high and
low side switches are pinned out separately allowing Inde'
pendent control of power MOSFET gate rise and fall times.

• No Supply Current in Quiescent State
• Peak Output Source Current ••••••••••••••••••••• SA
• Peak Output Sink Current ••••••••••••••••••••• 30A
• High Frequency Capability •••••••••••••••••• 300kHz

Applications

Special features are included in the device to provide a
simple, high speed gate drive circuit for power MOSFET in
application using pulse transformers. An optional on-chip
diode works with an external storage capacitor to store
energy from the pulse transformer after the gate drive pulse
has completed its low to high transition. The storage capaci·
tor supplies the gate drive current to turn on the MOSFET
wich overcomes the dVdt limitations of the pulse transformer. The high current drive capability of the HV400 using the
floating supply provides a cost effective improvement over
existing methods.

• Switching Power Supplies
• DC/DC Converters
• Motor Controllers
• Uninterruptible Power Supplies

Ordering Information
TEMPERATURE
RANGE

PACKAGE

HV4000P

0 0 0 to +7500

8 Pin Plaslic Mini-DIP

HV4000B

0 00 to +7500

8 Pin Plasllc SOlO

HV400lP

-400010 +8500

8 Pin Plastic Mini-DIP

HV400IB

-4000 10 +8500

8 Pin Plastic SOlO

PART
NUMBER

Another feature of the HV400 is the absence of quiescent
current. When used with PWM control ICs, additional low
voltage supply current to power the MOSFET driver during
startup, is not needed.
The device Is fabricated In the High Frequency Bipolar 01
process which provides latchproof operation in the
presence of transients on the power and signal lines. It is
available in the 8 pin Plastic DIP and 8 pin SOIC
(Commercial and Industrial grades).

Pinout
HV400CP (PLASTIC DIP)
HV400CB (SOIC)
TOP· VIEW

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

2-62

File Number

2850

Specifications HV400
Absolute Maximum Ratings

Operating Temperature Range

Voltage Between V+ and GND Terminals •••.••••..•••...•.. SOV
Input Vollage (Max) ••..••..••••••.••.•.•..••...•••••• +V + lV
InputVollage(Min) .••••••••••••••••••••.•.•..•..••.. GND-1V
Max Clamp Current (Pin 7) •••.••.•••••••.•••..••.••...••.• TBD
Peak Output Source Current •.••.•••••••.•••..••.••..•••• " 6A
Peak Output Sink Current •..••......•..•••.••.••.••••..••• SOA
Power Dissipation alTA = +250 C ••.••...•...•.. 1.2W Mini-DIP
Derate Above 650C .••.•...••..•.•.•••.•• 15mW;oC Mini-DIP

HV400CP/CB ••••••••••••••••••.••••.•••.• OOC:S;TA:S;+70oC
HV400IP/IB •••••.•••.•••.••••••.••••.•.• -400C ~ TA :S; +850C
Storage Temperature Range ...•.......•. -650C :S; TA :S; +150 oC

Electrical Specifications (Static) Test Conditions: +V = +20V at +25 0C
MINIMUM REQUIREMENT
'SYMBOL

PARAMETER

TEST CONDITIONS

VIH

Input Vollage, High

VOUT=OV, IOUTHI=lmA

Vll

Input Voltage, Low

VOUT = 18V,IOUT lO = -SmA

IIH

Input Current, High (Pin 2)

VIN = +20V, lOUT HI = OmA

MIN

TYP

MAX

UNITS

1.5

1.9

2.S

V

16.8

17.1

17.S

V

11

14.2

17

mA

11.25

14.7

18

mA

0

0.7

1.0

pA

(!)

lOUT HI = 150mA
Input Current, low (Pin 2)

VIN=OV

VOH

Output Vollage, High

VIN=+V,

lOUT = 150mA

16.7

16.9

17.1

V

VOL

Output Vollage, Low

VIN=OV,

IOUT=-150mA

0.8

0.88

1.0

V

III

VF

Clamp Diode Forward Vollage

10= 100mA

0.9

1.02

1.1

V

IR

Reverse leakage Current

VR=20V

-

0.1

1.0

pA

Off leakage Current (Pin 6)

VOUT= OV, VIN=OV

0

10

50

pA

IOl

Electrical Specifications (Dynamic) Test Conditions: +V = 20V, CL = 10nF
MINIMUM REQUIREMENT
SYMBOL

PARAMETER

TEST CONDITIONS

TDl

Delay, Input to Output

Figure 1

TD2

Delay,lnputlo Output

Figure 1

TR

Output Rise Time

Figure 1

TF

Output Fall Time

Figure 1

TOR

Output, Recovery Time

Figure 1

TRR

Clamp Diode, RecoveryTime

2-63

MIN

TYP

MAX

UNITS

-

10

-

ns

-

22

-

1000

1200

ns

-

TBD

-

ns

10
66

ns
ns
ns

z

(j)

!3

a: 0
0. a:
a:o
w

~

HV400
Timing Diagram

+V

INPUT
10'l&

OV---"'J

VOUT
OUTPUT
OV _ _ _ _ _
_,
10'l&

+v

7r-----------+-~

2
~

CtO.tp.F

~

INPUT
SOASOURCE
(RISE & FALL TIMES

OUTPUT

< tOns)

GND
NOTE: Wiring Inductance Reduced to Absolute Minimum
FIGURE 1. HV400 TEST CIRCUIT

Application Circuit

- - - - - - - - - -1-

TO
MOSFET
LOAD

1_4&~

FIGURE~.

_ _ _ _ _ _ _ __'

PRIMARY APPLICATION FOR HV400 IS WITH A PUSH-PULL DRIVEN PULSE
TRANSFORMER

2-64

mHARRIS

HV-1205

UL RECOGNIZED
Single Chip Power Supply

August 1991

Features

Description

• Direct AC to DC Conversion

The HV-1205 is asingle chip power supply that can supply
5V to 24V at 50mA output current. Just a few inexpensive
external components are needed to provide a compact,
light weight, cost effective power supply. The HV-1205
replaces a transformer, rectifier, and voltage regulator. This
chip Is made in the new Harris High Voltage Dielectric
Isolation Process. This high breakdown process (400V)
allows a patented switching circuit to draw current from the
AC line only as necessary to supply the load. The HV-1205
operates from -400 C to +85 0 C (with no derating necessary
due to package power dissipation). The HV-1205 is
available in an 8 Pin Plastic Mini-DIP.

• Wide Input Voltage Range •••.•••• 18Vrms-132Vrms
• Multiple Output Voltages
• Guaranteed Output Current ••••••••••••••••• 50mA
• Output Voltage ••••••••••••••••••••••••••• 5V to 24V
• Line and Load Regulation •••••••••••••••••••••• <2%
• UL Recognition, File # E130808

Applications

• Battery Back-Up Systems

CAUTION: This Product Does Not Provide Isolation
From the AC Line

• Dual Output Supply for OFF-LINE Motor Controls

Functional Diagram

HV3-1205 (PLASTIC MINI-DIP)
TOP VIEW

PRE -REG
CAP (C2)
GND
INHIBIT
CAP (C3)

ACHIGH
NC

ACHIGH
~

,1

8

VOUT

6

VOUT

SWITCHING
PRE· REGULATOR
4

C3=f
AC RETURN

HV -1205

...
P'

R1
Cl

VSENSE

en
en

wen
05
01-

0::0
0..0::
0::C3

~
0..

• Appliance Control

AC RETURN

:z

w

• Compact, Low Cost, Power Supply for Non-Isolated
Applications

Pinout

CJ

VOLTAGE
REGULATOR
VSENSE

INHIBIT

~

C4

3

1
PRE - REGULATOR CAP. 2

-"

GND

~'!

+
C2

CAUTION: Thl. Product Doe. Not Provide Isolation From the AC Line
Copyrighl @ Harris Corporalion 1991

File Number
2-65

2854

Specifications HV-1205
Absolute Maximum Ratings

Operating Temperature Range

Voltage Between Pin 1 and 8, Continuous Vrms •••••••• 132Vrms
Voltage Between Pin 1 and 8, Peak •...••.•.••.••••••.•••• 400V
Voltage Between Pin 2 and 6 •.•.••••..••••.•..••••••.•••.• 15V
InputCurrent,Peak •••..••••••.•..•.••..••..•••••••.••.• 1.IA
Output Current •••••.•..•..•...•.••..••• Short Circuit Protected
Output Voltage ..•••••..•.••.••.•....•.••••.•••.•••.••..• 30V
Maximum Junction Temperature •.•.••••..••••••.•••.•• +150 0 C

HV3-1205-9 .•..••.•.••.••.••••••.••.•••••.• -400 Cto+850 C
HV3-1205-5 •••••••••••••.•••••••...•••••.••••• OOC to + 75 0 C
Storage Temperature Range •••••••.••.••.•.. -650 C to +175 0 C
Thermal Constants (OC/W)
Sja
ajc
Plastic DIP
82
16

Electrical Specifications

Unless Otherwise Specified: VIN =120Vrm,s at 60Hz, C1 = 0.05"F, C2 = 470"F, C3 = 150pF,
VOUT = 5V,IOUT = 50mA, Source Impedance, Rl = 1500. Parameters are Guaranteed at the Specific
VIN and Frequency Conditions, Unless Otherwise Specified. See Functional Diagrams for Component
Location.
HV-1205-9
-40 0 C to +8S0 C

PARAMETER

HV-120S-S
OOC to +7So C

VIN

TEMP

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

120V

+25 0 C

4.75

5.0

S.25

4.75

5.0

5.25

V

120V

Full

4.65

5.0

5.35

4.65

5.0

5.35

V

Output Voltage TC

120V

Full

-

0.02

-

%/oC

120V

+25 0 C

10

-

mV

120V

Full

20

-

mV

30

-

0.02

Output Ripple (Vp-p)
(C4 = 1 JlF, f = 60Hz)

-

50

0

Output Voltage
(At Preset 5V)

Line Regulation

80Vrmsto
132Vrms

+250 C
Full

Load Regulation
(lOUT = 5mA to 50mA)
Output Current
Short Circuit Current Limit
Drop-Out Voltage
QUiescent CUrrent
Post Regulator

-

120V

+250 C

120V

Full

-

120V

Full

0

Full

55

120V
Pin2-Pln6

+250 C

11 VDC to 30VDC
OnPln2

+250 C

10
20

-

-

-

15
30
15

-

20

mV

40

mV

20

mV

40

mV

-

50

rnA

-

rnA

95

-

55

95

2.2

-

-

2.2

2

-

-

2

-

V
rnA

C5 I~OJ.LF

Equivalent Circuit For
Output Voltage Adjustment

''"

RSENSE(R2)

--

".

(SENSE) PIN 5

3.79K.
R2=VOUr-5V Where R2 is the Approximate Value of Resistor
Between Pin 5 and Pin 6 (in Kn), Your Is the
resired Output Voltage, See Graph.

I~
1.21K.
~

-LVREF

~

1.21V

RSENSE IS ZERO OHMS FOR SVoUT
FIGURE 1.

PIN6 (VOUT}

HV-1205

Schematic
SWITCHING
PRE - REGULATOR
CAl

Cl

:z
en
en
wen
0

.....

05
0::0

UNEAR VOLTAGE REGULATOR

c..o::

0::0

w

:s:

o
c..

AC
RETURN

2-67

HV-1205
Application Information
How The HV-1205 Works
The HV-1205 converts AC voltage into regulated DC voltage to power low voltage components such as integrated
circuits. This is accomplished In two stages on the monolithic chip. First, the pre-regulator momentarily connects a
large capacitor to the AC high line until it charges to about
6V above the selected output voltage. The pre-regulator
then switches to a blocking mode and stays in that blocking
mode until the next line cycle begins. The large capacitor
supplies power to the series pass regulator, providing DC
current to power the user's circuit. Providing current to the
post regulator causes the large cap to discharge at a rate
dependent on load current. Each line cycle refreshes the
charge on the electrolytic capacitor. For a detailed explanation of HV-1205 operation see Application Note 558.

A zener diode between pins 5 and 6, as shown in Figure 6,
sets the output voltage above 5V by the zener's breakdown
voltage at 1 rnA. This voltage has the accuracy and tolerance
of the zener. An added advantage is that two outputs are
now available, pin 5 at 5Vand pin 6 at Vz + 5V. All the current from the 5V supply flows through the reference diode.
The sum of both output currents should not exceed SOmA.
Output Current
Any current draw up to SOmA continuous is acceptable.
More current can be drawn momentarily. Care should be
taken to make sure C2 is not discharged below the dropout
voltage and that the duty cycle of the excess current is low
enough to not cause a package power dissipation problem.
The output is current limited as shown In the graph to
protect against shorted loads.
Component Selection

Input Voltage
The HV-1205 operates over a wide range of input voltages.
Most applications will use the 120Vrms line from the power
grid. A standard circuit for this application is shown in Figure 2. Much smaller input voitages can be used. The size of
the external components used will be determined by the
output voltage and current required and the Input voltage
available. Several graphs have been provided to help
choose component values for a specific application. The
section below called Component Selection discusses
trade-offs related to component sizing.
Input Frequency
The HV-1205 is designed to operate from 48Hz to 380Hz.
Higher operating frequency in possible. Keep in mind that
the HV-1205 will refresh C2 once per line cycle.

One of the most powerful features of the HV-1205 is its
flexibility. One standard configuration allows enormous
variation in input voltage and output current while stili
maintaining a regulated output. For example, with R1 =
1500, C2 = 470llF and VOUT = 5V, the HV-1205 will
provide a regulated SOmA output when input voltage is
anywhere from 132VAC down to about 28VAC. The designer can choose components tailored to his application in
order to save cost, space, power dissipation etc.
Below is a list of external components, description of their
purpose, and a recommended value. This is a full list of
possible components all of which may not be required for
an intended application. Most designs will use a subset of
this list.
F1:

Fuse. Opens the connections to the power line
should chip fail. Recommended value = 1/4A, 2AG
similar to Littlefuse 225.250®.

R1:

Source Resistance. Limits current into HV-1205.
Needs to be large enough to limit inrush current
when C2 is discharged fully. VpEAKlR1 = 1.1A
Maximum. R1 will dissipate power as shown in the
graphs. The equation for Pd in R 1 is:
Pd = 1.33 y'iiR1 VPEAK(IOUT)3. Low average
output currents would allow for source resistors with
lower Pd ratings. Similarly, lower VAC or smaller
value R1 will cause less dissipation in R1. Sizing of
R1 should be tailored to the intended application
keeping in mind not to let the maximum inrush
current be exceeded. Should an external method of
limiting inrush current be used (such as NTC resistors) then the value of R1 and its associated heat
could be reduced. Recommended value = 1500. To
reduce Pd see App. Note AN91 07.

C1:

Snubber CapaCitor. R1 and C1 form a low pass filter
thereby limiting the rate of voltage rise at the input of
the HV-1205. Recommended value = 0.05IlF, AC
rated.

Setting Output Voltage
The HV-1205 can be set to provide a regulated output voltage anywhere from 5V to 24VDC. Refer to Figures 4, 5 and
6 for several ways of adjusting output voltage. Any time an
output voltage greater than 5V is chosen, a 10llF capacitor
between the output and the sense pin is required. That
capacitor allows C2 to charge gradually.
As seen in Figure 1, output voltage is set by feedback to the
sense pin. The output will rise to the voltage necessary to
keep the sense pin at 5V. For a 5V output, pins 5 and 6 are
shorted together. There are three ways to increase the output voltage beyond 5V. The simplest method is to increase
the feedback resistor by adding an external resistor
between pins 5 and 6. The disadvantage is that the Internal
circuit resistors have a tolerance of approximately ±15%
which limits the accuracy of the predicted output (see
graph). The internal thin film resistors have low temperature
coefficients.
An external voltage divider as shown in Figure 5 improves
the accuracy as long as the external resistors are much lower in value than those of the internal divider. Approximately
1mA flows into pin 5. If a potentiometer is used as the
divider, an additional resistor between the lower leg and
ground will insure that the output never exceeds its maximum rated voltage.

MOV: Surge suppressor. Metal Oxide Varistor clamps voltage to a level that the HV-1205 can handle.
Recommended value = V130LA20 or equivalent.

littlefuse 225.250 is a Registered Trademark of Tracor, Inc.

2-68

HV-1205
Application Information
C2:

C3:

(Continued)

Pre-Regulator capacitor. This capacitor is charged
once each line cycle. The post-regulator portion of
HV-1205 is powered by C2 for most of the line
cycle. Normally the smallest C2 that will supply the
load current (see graph) is used. Using a large C2
will supply temporary high load currents or normal
load current during a short power loss. Using a
larger C2 will reduce ripple at Pin 2, the input to the
post regulator, which will reduce output ripple. C2
should have a ripple current rating consistent with
the application. Small capacitors with high ESR may
not store enough charge to maintain load current.
See graph. Recommended value = 470IlF, voltage
rating should be about 10V greater than chosen
VOUT·

HV-1205 will never turn on. If sized too small, no
protection from transients Is offered. For 60Hz
(or 50Hz) use the recommended value of 150pF,
voltage rating should be at about 10V greater than
VOUT. For 400Hz use 47pF.
C4:

Output filter capacitor. At least 11lF is required to
maintain stability of the output stage. Larger values
will not reduce ripple but will reduce spiking which
may occur on the output coincident with the
HV-1205 going into blocking mode. 100llF reduces
the spike amplitude to about 25mVp-p.

R2:

Feedback component. A resistor or diode that
causes a voltage drop between the SENSE and
OUTPUT pins and thereby adjusting the output voltage. See voltage adjustment equivalent circuit. Also
see graph for approximate resistor value.

Inhibit capacitor. Keeps the HV-1205 from turning
on during input transients. If sized too large,

(!)

z

en

ffl~
0
_
o~

0:: 0
Il. 0::
0::0

lU

:;:

o

Il.

VOUT ADJUSTMENT
FIGURE 4
METHOD
R2

Vo

FIGURES
METHOD

FIGURE 6
METHOD

RA/Rs

Vo

Vo

0

5V

0/00

5V

-

lK

6V

l60/1K

6V

1V

6V

3K

BV

5l0/1K

BV

3V

BV

Fl
Cl

Vz'

5V

5K

10V

B20/1K

10V

5V

10V

7K

l2V

1.2K/1K

12.2V

7V

12V

9K

14V

1.5K/1K

14V

9V

14V

11K

16V

1.BK/1K

15.BV

llV

16V

13K

lBV

2.2K/1K

lB.2V

13V

lBV

15K

20V

2.4K/1K

19.4V

15V

20V

17K

22V

3.0K/1K

23V

17V

22V

19K

24V

3.17K/1K

24V

19V

24V

FIGURE 2. HV-120S STANDARD +SV APPLICATION

'VZ@lmA

+s+vz

6

5
+5V

3

FIGURE 3. VOUT = +SV

FIGURE 4. VOUT> +5V

FIGURE 5. VOUT> +SV

2-69

FIGURE 6. VOUT = +SV,
+5 +Vz

HV-1205
Application Information

(Continued)

OPERATION WITH VOUT > 5V

r----p---o VOUT

120VAC

OPERATION FROM A BRIDGE RECTIFIER
R1

R1

2

2

120VAC

SURGE PROTECTION USING MOV

.-------60

C..l

~

~4O

o

::E
::>
::E 20

~

o

..iJ

100

147~~~

I!!!.

<:

.§.

...

1000~F

1"-1-0

~

...

::> 40
0

::E
::>
::E 20

100~F

18

22

26

30

II

34

~

~
o

::E

38

42

~

.....

I

I

330~F

..1

r-

.l.

1 I

220~F

0..

2T~f

470~F
1000~F

11 -- - l'

...::>

i-

-

....

::> 60

C..l

r--r-- 1-0

14

Ill'"

80

Z

w
a:
a:

i"'

330~F

V

10

MAXIMUM OUTPUT CURRENT FOR 24V REGULATED
OUTPUTvs.INPUT VOLTAGE AND PRE-REGULATOR
CAPACITOR SIZE (C2)
R, = 240

46

~

1

",.

1000.

, .,

100~F

~

22

46

30
34
38
42
INPUT VOLTAGE (Vrms)

26

INPUT VOLTAGE (Vrms)

Pd IN R1 vs. R, VALUE
Vrms= 120V

50

Pd IN R1 vs. lOUT
120Vrms, R1 = 1500
4.5
~ 4.0
~

a:
i!:

z

o

~ 3

z

1-+-1::.....III!::I-:::Iaoo.....r::r-l-1-

c

2

1/

3.0

0 2.5

0..

iii
r!2

L

3.5

~
0..

2.0

rn

1.5

iii

F++-t-....."I........""'==t-l-r-

~ b~t:r:~~k:k:t:t:t:t:t:t:r:[]

C

a:
w Lo

L

;:

0.. 1

0 0.5
0..

5mALOAD

o

o_~~~~~~~~~~~
50
70
90
110
130
150
170
190

V

L

L

/

".,

o

40

R1 (n.)

PEAK C2 VOLTAGE vs. OUTPUT VOLTAGE

a:

~

MINIMUM C2 VALUE VS. LOAD CURRENT

35

13

340

~

30

'"z
Ii:

25

<
w
~

20

/

:;
~

15

~

10

0..

~'"

..,

3BO

V

/

~300

c
w
w

220

w

180

Z

~
'"C..l

/
o

140

25

2-72

~

100

20

5
10
15
20
OUTPUT VOLTAGE (VOLTS)

L L
L'LI"'"

0260
w

60

5

50Hz @ 120Vrms . /

/ ~z@
"/

120Vrms

~~

1/

o

10

20
30
LOAD CURRENT (rnA)

40

50

HV-1205
Typical Performance Curves

=
=

=

=

CHIP POWER DISSIPATION VS. OUTPUT CURRENT
800

§" 700

.§.

z
o

24VOUT_
600

gj

~

.., ,."

~ 500

.;'

V .., ......-: k
. / '" ~ V

400

i5
II: 300

~

~ 200

./

, V
-..,.

o

o

5

10

15

20

25

z 3.0

0::

r-....
~
........

..-:::: .,/

...........
r....
-- ~
-==s
~

15VOUT

5V, SOmA
5VOUT

30

=

DROPOUT VOLTAGE vs. TEMPERATURE

co

./

.;'

~k

.,.,

=

35

~~

sv, 5mf

~ :;....--

100

=

Unless Otherwise Specified: TA +2So C, VAC
120Vrms, f
60Hz,
R1
1S00, C1
O.OSIlF, C2 470llF, C3
1S0pF, C4 = 11lF, VOUT = SV

40

45

50

-15

~

T'
10

- ... r....

~4v,somA

..........

.......
(!J

:z

en
en
w

25 35

60

75

85

c..a:
a:O

TEMPERATURE (0 C)

OUTPUT CURRENT (mA)

~

QUIESCENT CURRENT vs. OUTPUT VOLTAGE @ = +2S o C
lOUT = SmA to SOmA

=

5

V
o

ac..

OUTPUT RIPPLE VOLTAGE vs. OUTPUT VOLTAGE
lOUT SOmA

4

V

/'
./

5

./

-

~4

.§.

~3

;.J

§2
~ 2

0.
0.

iE

~

1

I;:J

0 0
10

5

10

20

15

15
VOUT (V)

20

25

VOUT(V)

OUTPUT RIPPLE VOLTAGE vs. LOAD CAPACITANCE AND
OUTPUT CURRENT

OUTPUT RIPPLE VOLTAGE vs. TEMPERATURE
C4

=

lJ1F

4.0

~
c.
>

Co

g4+--+--+--+--+--+--+--+--r-~~~~~~~
w

.5.

:; 31=:t::4=~:t::t:~=r=r==rt1rT1

:;

2+--+--t-+--i--+--+--t-+-t--+--+--II--~

~
iE

w

~

§2
~
"-

iE

~

SOmA
40mA
2.0

30mA
20mA

.... 1.0

I-

;:J

1

0.
I-

;:J

o

3.0

~

§2

;:J

-40 -30 -20

-10

0

10

20

30

40

50

60

70

80

5mA

o

0+-~~--+-~~--+-~-4--~~-4--~~

0.0

90

010

50

100

lSO

200

C4 OUTPUT FILTER CAPACITANCE (I'-F)

TEMPERATURE (DC)

2-73

en

g!3
a:O

250

HV-1205
Typical Performance Curves

Unless Otherwise Specified: TA = +25OC, VAC = 120Vrms, f = 60Hz,
R1 = 1500, C1 = 0.0511F, C2 = 470llF, C3 150pF, C4 = 111F, VOUT

=

= 5V

NORMALIZED QUIESCENT CURRENT VB. TEMPERATURE
Actual Quiescent Current at +250 C: VOUT = 24V: 3A2mA
VOUT = 5V: 0.41mA

OUTPUT RIPPLE VOLTAGE VB. C2 SIZE
lOUT = 50mA, VOUT = 5V
5

1.4

!z
.W
a::
a::

\.

B 1.2

--

~

~

...z

w

(J

ffl

5

1. 0

o

V OUT

~:J

V OUT

~~

=

= 5V

24V

~ 0.8

a::

oz

o
200

400

600

0.6

890. 1000 1200 1400 1600 1800 2000 2200

-40

(J1 F)

C2 SIZE

-15

10

35

60

85

TEMPERATURE ( ° C)

OUTPUT CURRENT LIMIT (SVOUT)
SOmA is the Maximum Specified Output Current

OUTPUT CURRENT LIMIT (24VOUT)
SOmA is the Maximum Specified Output Current
30

-

.

.' [\
,

~4

\

W

~

:; 3

~

5
e:
:>

""'

........

50°C

;-- 25°C

-2S~C-

01

I

o
20

30

40

50

60

70

90

_4QOCI

I
I

\

~ 12

...

:>

oOc

50°C

o

I

80

1\

...~

-

-4QoC- i--

\

85 0 C -

"

:;

2

17SOC

100 110 120 130

2S0C

'or,:'~

~ 18

OOC~

75 0 C -

" "

~
w

-

I

I
F

.'

24

6

-

I

OUTPUr CURRENT (rnA)

,------.

85°C

25°C

I

o
20

30

40

I

50

60

70

80

90

100 110 120 130

OUTPUT CURRENT (rnA)

VOUT vs. R2 WITH TOLERANCES
Internal Resistors 15% High or Low
24

22

LJw

"/

20

~

18

lI'

v..; ~

10

8
6
4

10"'.....
"

I"/f

/
r

MINIMUM ALLOWABLE R1 FOR INPUT VOLTAGE
170

10'
~"GH

NOMINAL

"
z
Si

2

r

V

3 110

;;

r--. A V

~

./

130

w

~~

o

,;'

150

~ /1

90
70

,/

50

"""

10'

30

4

6

8

10 12 14
R2 (kA)

16

18

20

22

""

10
10

24

2-74

30

50

70

Vrms (V)

90

110

130

HV-1205
HV-1205 Parallel Operation

(Method #1)
R1

AC
HIGH

(!J

z

en
en

w en
0105
0:0

c..o:

AC
RETURN

0:(3
W

:;;:

1.n
NOTE: Operational Amplifier Causes Each HV-1205 to
Contribute Equally to Output Current.

HV -1205#2

HV-1205 Parallel Operation

(Method #2)

R1

C1
C2

AC
HIGH

R1

C1
AC
RETURN
~10UT

=

C2

~VOUT

R3

NOTE: This Method Requires that the Output Voltages of
Each HV-1205 are Close In Value.

2-75

o

c..

HV-2405£

mHARRIS
UL RECOGNIZED

World-Wide
Single Chip Power Supply

August 1991

Features

Description

• Direct AC to DC Conversion

The HV-240SE is a single chip power supply that can
supply SV to 24V at SOmA output current. Just a few
inexpensive external components are needed to provide a
compact, light weight, cost effective power supply. The
HV-240SE replaces a transformer, rectifier, and voltage
regulator. This chip is made in the new Harris High Voltage
Dielectric Isolation Process. This high breakdown process
(SOOV) allows a patented switching circuit to draw current
from the AC line only as necessary to supply the load.

• Wide Input Voltage Range •.•••.•• 18Vrms-264Vrms
• Multiple Output Voltages
• Guaranteed Output Current ••••••••••••••••• SOmA"
• Output Voltage ••••••••••••••••••••••••••• SV to 24V
• Line and Load Regulation •••••••••••••••••••••• <2%
• UL Recognition, File # E130808

The wide Input voltage range makes the HV-240SE an
excellent choice for use in equipment which must operate
from either 240V or 120V. Unlike competitive AC-DC
convertors, the HV-240SE can use the same external
components for operation from either voltage. In addition
the HV-240SE can be connected across any two phases of
a 3-phase system (208Vrms)*. This great flexibility in input
voltage allows a single design for worldwide use.

Applications
• Compact, Low Cost, Power Supply for Non-Isolated
Applications
• Appliance Control
• Battery Back-Up Systems

The HV-240SE is pin for pin compatible with the HV-120S
but allows twice the Input voltage. Additionally, the output
and sense pins are connected through a zener diode to limit
output voltage should the sense pin to output connection
become open.

• Dual Output Supply for OFF-LINE Motor Controls
• Housekeeping Supply for Switch-Mode Power
Supplies

Ordering Information

Further flexibility can be obtained from the HV-240SE by
using it with other Harris chips. For example, the high
efficiency ICL-766OS and ICL-7662 provide positive to
negative voltage conversion. For automatic switch-over to
battery back-up use the ICL 7673. Harris also offers a line
of extremely low power op amps.

OPERATING
TEMPERATURE
RANGE

PACKAGE
DESCRIPTION

HV3-2405E-5

00Cto+750C

8 Lead Plastic Mini-DIP

HV3-2405E-9

-40 0C to +85 0C

8 Lead Plastic Mini-DIP

PART NUMBER

" CAUTION: When used in this mode, GND and AC
RETURN operate at high voltage with
respect to earth ground.

CAUTION: This Product Does Not Provide Isolation
From the AC Line
"See App Note AN9101 for 2S0mA output.

Pinout

Functional Diagram

HV3-2405E (PLASTIC MINI-DIP)
TOP VIEW

AC HIGH
--"

AC RETURN
PRE-REG
CAP (C2)
GND
INHIBIT
CAP (C3)

AC HIGH

,l

R1
Cl

NC

.....

HV ·2405E

SWITCHING
PRE· REGUlATOR

4

VOUT
VSENSE

6

VOLTAGE
REGUlATOR
VSENSE

INHIBIT

C3f

AC RETURN

-5

C4

3

GND

1
PRE· REGULATOR CAP. 2

-C2+
CAUTION: This Producl Doe. Not Provide Isolallon From the AC Line
Copyright @ Harri. Corporation 1991

6

"i7

File Number
2-76

2487.1

Specifications HV-2405E
Absolute MaxImum RatIngs

OperatIng Temperature Range

Voltage Between Pin 1 and 8, Continuous Vrms .••••••. 264Vrms
Voltage Between Pin 1 and 8, Peak ....................... 500V
Voltage Between Pin 2 and 6 .............................. 10V
Input Current, Peak ..................................... 2.5A
Output Current ......................... Short Circuit Protected
Output Voltage .......................................... 30V
Maximum Junction Temperature ....................... +150 0C

HV3-2405E-9 .............................. -40 0C to +85 0C
HV3-2405E-5 ................................. oOC to +750C
Storage Temperature Range ••..••...••.•.•.• -650 C to +1750C
Thermal Constants (OC/W)
Oja
Ojc
Plastic DIP
82
16

=

=

=

=

264Vrms at 50Hz, C1
0.05~F, C2
470pF, C3
150pF,
VOUT 5V, lOUT 50mA, Source Impedance, R1 1500. Parameters are Guaranteed at the Specific
VIN and Frequency Conditions, Unless Otherwise Specified. See Functional Diagrams lor Component
Location.

Electrical SpeCifications Unless Otherwise Specified: VIN

=

=

=

HV-2405E-9
-40 0 C 10 +850 C

HV-2405E-5
00Clo+75 0 C

(!J

VIN

TEMP

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

264V

+250C

4.75

5.0

5.25

4.75

5.0

5.25

V

264V

Full

4.65

5.0

5.35

4.65

5.0

5.35

V

Output Voltage TC

264V

Full

0.02

-

264V

+25 0C

24

-

%/oC

Output Ripple (Vp-p)
(C4 1 ~F, I 50Hz)

-

10

20

mV

15

40

mV

-

20

mV

40

mV

50

rnA

PARAMETER
Output Voltage
(At Preset 5V)

=

=

Full

264V

-

+250C

264V

+250C

264V

Full

Output Current

264V

Full

0

Short Circuit Current Limit

264V

Full

55

-

Full
Load Regulation
(lOUT 5mA to 50mA)

=

(j)

f3(J)

01-

05
0::0

80Vrmsto
264Vrms

Line Regulation

:z

Drop-Oul Voltage

Pin 2- Pin 6

+250C

Quiescent Current
Post Regulator

11VDCt030VDC
On Pin 2

+250C

22
24

-

10

15

15

30

95

15

-

0.02
22

50

0

-

-

55

95

-

2.2

30

2.2

-

2

-

2

-

mV
mV

rnA
V
rnA

--

Equivalent Circuit For
Output Voltage Adjustment

RSENSE(R2)

'"

(SENSE) PIN 5

3.79K ;-

I~
R2=VOur-5V Where R2 is the Approximate Value of Resistor
Setween Pin 5 and Pin 6 (in KO). Your is the

1.21K":

-LVREF

~

Desired Output Voltage. See Graph.

1.21V

RSENSE IS ZERO OHMS FOR 5V OUTPUT

FIGURE 1.

2-77

PIN 6 (VOUT)

Q.o::

0::C3

~

Q.

HV-2405E

Schematic

DA.

AC
RETURN

SWITCHING PRE - REGULATOR

UNEAR VOLTAGE REGULATOR

,Patent pending on the above circuit.

2-78

HV-2405E
Application Information
How The HV-2405E Works
The HV-2405E converts AC voltage into regulated DC voltage to power low voltage components such as integrated
circuits. This is accomplished in two stages on the monolithic chip. First, the pre-regulator momentarily connects a
large capacitor to the AC high line until it charges to about
6V above the selected output voltage. The pre-regulator
then switches to a blocking mode and stays in that blocking
mode until the next line cycle begins. The large capacitor
supplies power to the series pass regulator, providing DC
current to power the user's circuit. Providing current to the
post regulator causes the large cap to discharge at a rate
dependent on load current. Each line cycle refreshes the
charge on the electrolytic capacitor.
Input Voltage
The HV-240SE operates over a wide range of input voltages. Most applications will use the 240Vrms or 120Vrms
line from the power grid. A standard circuit for this application is shown in Figure 2. Much smaller input voltages can
be used. The size of the external components used will be
determined by the output voltage and current required and
the input voltage available. Several graphs have been provided to help choose component values for a specific application. The section below called Component Selection
discusses trade-ofts related to component sizing.
Input Frequency
The HV-240SE is designed to operate from 48Hz to 380Hz.
Higher operating frequency is possible. Keep in mind that
the HV-240SE will refresh C2 once per line cycle.

The HV-240SE has an internal zener diode to clamp
the output above the 24V maximum but below a damaging
level.
Output Current
Any current draw up to SOmA continuous is acceptable.
More current can be drawn momentarily. Care should be
taken to make sure C2 is not discharged below the dropout
voltage and that the duty cycle of the excess current is low
enough to not cause a package power dissipation problem.
The output is current limited as shown in the graph to protect against shorted loads.
Component Selection
CI

One of the most powerful features of the HV-240SE is its
flexibility. One standard configuration allows enormous
variation in input voltage and output current while still maintaining a regulated output. For example, with R1 = 1S00,
C2 = 470flF and VOUT = SV, the HV-240SE will provide a
regulated SOmA output when input voltage is anywhere
from 264VAC down to about 28VAC. The designer can
choose components tailored to his application in order to
save cost, space, power dissipation etc.
Below is a list of external components, description of their
purpose, and a recommended value. This is a full list of possible components all of which may not be required for an intended application. Most designs will use a subset of this
list.
F1:

Fuse. Opens the connections to the power line
should chip or C2 fail. Recommended value = 1/2A,
2AG similar to Littlefuse 22S.S00<1>.

R1:

Source Resistance. Limits current into HV-240SE.
Needs to be large enough to limit inrush current
when C2 is discharged fully. VpEAKlR1 = 2.SA
Maximum. R1 will dissipate power as shown in the
graphs. The equation for Pd in R 1 is:
Pd = 1.33 y'iiR1 VPEAK(lOUT)3.
Low average output currents would allow for source
resistors with lower Pd ratings. Similarly, lower VAC
or smaller value R 1 will cause less diSSipation in R 1.
Sizing of R1 should be tailored to the intended application keeping in mind not to let the maximum inrush current be exceeded. Should an external method of limiting inrush current be used (such as NTC
resistors) then the value of R1 and its associated
heat could be reduced. Recommended value =
1S00. To reduce Pd see App Note AN91 07.

C1:

Snubber Capacitor. R1 and C1 form a low pass filter
thereby limiting the rate of voltage rise at the input of
the HV-240SE. Recommended value = O.OSflF, AC
rated.

Setting Output Voltage
The HV-240SE can be set to provide a regulated output
voltage anywhere from 5V to 24VDC. Refer to Figures 4, S
and 6 for several ways of adjusting output voltage.
As seen In Figure 1, output voltage is set by feedback to the
sense pin. The output will rise to the voltage necessary to
keep the sense pin at SV. For a SV output, pins Sand 6 are
shorted together. There are three ways to increase the output voltage beyond SV. The simplest method is to increase
the feedback resistor by adding an external resistor
between pins Sand 6. The disadvantage is that the internal
circuit resistors have a tolerance of approximately ±1S%
which limits the accuracy of the predicted output (see
graph). The internal thin film resistors have low temperature
coefficients.
An external voltage divider as shown in Figure S improves
the accuracy as long as the external resistors are much lower in value than those of the internal divider. Approximately
1mA flows into pin S.
A zener diode between pins Sand 6, as shown in Figure 6,
sets the output voltage above SV by the zener's breakdown
voltage at 1mA. This voltage has the accuracy and tolerance
of the zener. An added advantage is that two outputs are
now available, pin S at SV and pin 6 at Vz + SV. All the current from the SV supply flows through the reference diode.
The sum of both output currents should not exceed SOmA.

MOV: Surge suppressor. Metal Oxide Varistor clamps voltage to a level that the HV-240SE can handle.
Recommended value = V130LA20 or equivalent for
120V applications and gas tube which arcs over at
less than SOOV for 240V applicatons.

Llttlefuse 225.500@ is a Registered Trademark of Tracor, Inc.

2-79

z

u.;
fficn
0105

a: 0
0... a:
a:o
w
;;::

a0...

HV-2405E
Application Information
C2:

(Continued)

Pre-Regulator capacitor. This capacitor is charged
once each line cycle. The post-regulator portion of
HV-2405E is powered by 02 for most of the line
cycle. Normally the smallest 02 that will supply the
load current (see graph) is used. Using a large 02
will supply temporary high load currents or normal
load current during a short power loss. Using a
larger C2 will reduce ripple at Pin 2, the input to the
post regulator, which will reduce output ripple. 02
should have a ripple current rating consistent with
the application. Small capacitors with high ESR may
not store enough charge to maintain load current.
See graph. Recommended value
4701lF, voltage
rating should be about 10V greater than chosen
VOUT.

protection from transients is offered. For 50Hz
or 60Hz use the recommended value of 150pF, voltage rating shouid be at about 10V greater than
VOUT.

04:

Output filter capacitor. At least 11lF is required to
maintain stability of the output stage. Larger values
will not reduce ripple but will reduce spiking which
may occur on the output coincident with the
HV-2405E going into blocking mode.

R2:

Feedback component. A resistor or zener diode that
causes a voltage drop between the SENSE and
OUTPUT pins and thereby adjusting the output voltage. See voltage adjustment equivalent circuit. Also
see graph for approximate resistor value. About
1 mA flows through this component.

=

03:

Inhibit capacitor. Keeps the HV-2405E from turning
on during input transients. If sized too large,
HV-2405E will never turn on. If sized too small, no

VOUT ADJUSTMENT

Rl

Rl

2

2
,.

'A

FIGURE 4
METHOD

~
.........

I

r
I
I

Fl
Gl

8

N.G
7

h
6

GH

1

2

3

Vo

RA/RB

Vo

Vz*

Vo

0

SV

O/Open

5V

-

5V

lK

6V

160/1K

6V

lV

6V

3K

8V

510/1K

8V

3V

8V

5K

10V

820/1K

10V

5V

10V

7K

12V

1.2K/1K

12.2V

7V

12V

9K

14V

1.5K/1K

14V

9V

14V

11K

16V

1.8K/1K

15.8V

l1V

16V

13K

18V

2.2K/1K

18.2V

13V

18V

15K

20V

2.4K/1K

19.4V

15V

20V

17K

22V

3.0K/1K

23V

17V

22V

19K

24V

3.17K/1K

24V

19V

24V

LOAD

4

:!:G3

G2 +

T
'1;7

FIGURE 2. HV-240SE STANDARD +SV APPLICATION

FIGURE 6
METHOD

R2

5

HV ·2405E

FIGURES
METHOD

'VZ@lmA

~

n

6

5

3

V
FIGURE 3. VOUT = +SV

-

~

6

5

3

~

r6

6

5

RB
3

~

V

FIGURE S. VOUT> +SV

FIGURE 4. VOUT> +SV

2-80

'.4 ~

RA

R2

>

+5+VZ

5
+5V

3

V
FIGURE 6. VOUT = +SV,
+S +Vz

HV-2405E
Application Information

(Continued)
OPERATION WITH VOUT

> SV

240 VAC

CJ

OPERATION FROM A BRIDGE RECTIFIER'
AI

AI

"2

:z

en
en

~~

"'2

oS
a: 0
D..a:
a:O

w

~
D..

*See App Note AN9006 for additional information.

SURGE PROTECTION USING GAS TUBE
R1

R1

"2

"'2

240VAC

*Carbon composition resistor

USING SWITCH TO TURN OFF OUTPUT
R1

R1

2"

2"

.-----..--~o V OUT

240 VAC

2-81

HV-2405E
HV-2405E Waveforms

Unless Otherwise Specified: TA = +25 0 C, VAC = 240Vrms, f = 50Hz,
R1 = 1500, C1 = 0.05"F, C2 = 470"F, C3 = 150pF, C4 = 1"F,
VOUT = 5V @ 50mA, 5ms/div

Top Trace: Input Voltage at Pin 8, AC High (200V/Div)
Boltom Trace: Current into Pin 8, (O.5NDiv)

Top Trace: Input Voltage at Pin 8, AC High (200V/Div)
Bottom Trace: Pre-Regulator Capacitor Voltage, C2 (5V/Div)
@ Approximately 10V DC

Top Trace: Input Voltage at Pin 8, AC High (200V/Div)
Bottom Trace: Inhibit Capacitor Voltage (10V/Div)

Top Trace: Load Current Step (50mNDiv)
Boltom Trace: Output Voltage (20mV/Div) @ 5VDC

Top Trace: Input Voltage at Pin 8, AC High (200V/Div)
Boltom Trace: Ripple or Switch Spike on Regulator 5V DC Output (50mV/Div)
This Is Worst Case Ripple due to Worst Case Operating Conditions
(High Line Voltage, Minimum R1 Value, Maximum lOUT)

2-82

HV-2405E

100

MAXIMUM OUTPUT CURRENT FOR 24V REGULATED
OUTPUT VS. INPUT VOLTAGE AND PRE-REGULATOR
CAPACITOR SIZE (C2)
R1 = 240

ffi
a:
a:

::>60

~

lJ

...

~

!:;4O
o

330jlF

........ -

-

E-

...z

II

80

w
a:
a:

40
0
::IE
::>
::IE 20

2Tjlf
100jlF

14

18

II

22
26
30
34
INPUT VOLTAGE IVrms)

42

.....

1000jlF

.....

-~ ~

'I

I

-

22

I

330jlF

I I
220jlF

II
I '1

C:J

z

en

 60
lJ

...::>
Q,

V'
10

<"

...::>

Ir.4

o

1000jlF

-I-

1.4

::IE
::>
::IE 20

~

~

100

147ljl~

~~

-80

=

Unless Otherwise Specified: TA +2S0 C, VAC
240Vrms, f
SOHz,
R1 = 1S00, C1 = O.OSIJF, C2 = 470IJF, C3 = 1S0pF, C4 = 1IJF, VOUT = SV

MAXIMUM OUTPUT CURRENT FOR 5V REGULATED
OUTPUT VS. INPUT VOLTAGE AND PRE-REGULATOR
CAPACITOR SIZE (C2)
R1 = 240

<"
E

=

=

Typical Performance Curves

26

30
34
3B
42
INPUT VOLTAGE IVrms)

46

oS

N

5~
0:::

.2-

I-

::>

a.
~

=

=

=

=

QUIESCENT CURRENT va. OUTPUT VOLTAGE @
lOUT 5mA to 50mA

=

DROPOUT VOLTAGE va. TeMPERATURE
...J

=
=

Unless Otherwise Specified: TA
+250 C, VAC
240Vrms, f
50Hz,
R1
1500, C1
0.051lF, C2
470llF, C3
15OpF, C4
11lF, VOUT

= 5V

=+250 C

4

.....

" .... .......

-25

0

<"
oS

3

V

l-

z

~

W
0:
0:

....... ....

25

::>

.......

so

u

--

2

/

I-

z

W

U

:-

fll

:;
0

85

./

1 /

V

TEMPERATURE (C)
0

10

5

15

20

25

VOUT(V)
OUTPUT RIPPLE VOLTAGE va. TEMPERATURE

C4

= l~F

OUTPUT RIPPLE VOLTAGE va. LOAD CURRENT

25

I'
> 24
C1

oS

w

w

(!l

(!l

~

23

'"

0

>

~

22

I-

21

~

~~

-

0'

>

C1

~:e

a.~

a.

cr

::>

I!:::>
0

20
-40 -30 -20 -10

0

10

20 30 40

so

60 70

80 90

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8

RIPPLE

4

12

8

16

24 28 32
lOUT (mA)

20

TEMPERATURE (OC)

NORMALIZED QUIESCENT CURRENT VB. TEMPERATURE
Actual Quiescent Current at +25OC: VOUT 24V: 3.42mA
Your 5V: O,4lmA
1.4

=
=

5

0:

ffi
fll
:;

.............

U

V OUT

............... ~

= 5V

1.0

~

VOUT= 24V

SOoC

aw

4

!:i

g

3

5
a.

2

~

0

~
:i!

.......

\,
I

75 0 C-

oOC-

I-

::>

I

85 0 C-

0:

0

0

z

20
0.6
-15

10
35
TEMPERATURE ( 0 C)

80

48

~250C

01

0.8

-40

44

6

a:

::> 1.2

40

OUTPUT CURRENT LIMIT (5VOUTI
50mA is the Maximum Specified Output Current

IZ
W

u

36

30

40

so

60

70

\
80

-25~C-

-

-4(J°C-

I-

-I

90

OUTPUT CURRENT (mA)

85

2-84

\

100 110 120 130

HV-2405E
Typical Performance Curves Unless Otherwise Specified: TA = +250 C, VAG = 240Vrms, f = 50Hz,
R1 = 1500, G1 = 0.05J.1F, G2 = 470J.lF, G3 = 15OpF, C4 = 1J.1F, VOUT = 5V
OUTPUT CURRENT LIMIT (24VOUT)
SOmA is the Maximum Specified Output Current

VOUT vs. R2 WITH TOLERANCES
Internal Resistors 1S% High or Low

30

24

I

22

Ldw

'/

20

/-250C
24

,

18

~
w

!:i

g

I-

~ 12

I-

~ 16

-JKJoc7

"\

~ 18

I

~ 14

I

0

>

DoC

6

B

4

I

0
20

30

40

I--

2

4

(!I

:z
Cii

6

8

10 12 14 16
R2 (kll)

I

180
HiD

Q
w

140

~

100

:3

120

~

80

C
w
C

60

Z

w
::;
::;
a
u
w
a:

40
20
0
0

20

22

24

men

01-

05
0::0
"- 0::
0::0

~

MINIMUM RECOMMENDED R1 FOR NOMINAL INPUT VOLTAGE
(j)

16

W

50 60 70 80
90 100 110 120 130
OUTPUT CURRENT (rnA)

::;

~UGH

~

25°C

:t

NOMINAL

A~
- J7'
0

I
85°C

~

Ih ~

8

175OC -

~...,.,i"""

,

-"' V1

~ /

12
10

50°C

:>
0

~

~IA

/

40

80

CREATING SYNTHESIZED

8
HV- 2405E

120
200
160
AC INPUT (VRMS)

±

1I

280

SUPPLIES USING FALSE GROUND
+VSUPPLY

RA

..... +v

'---1; r.--o FAlSE GND

C4

5

3

240

...... - v

.

RS

- VSUPPLY
(ACTUALLY AT AC RETURN POTENTIAL)

NOTES:
1. RA, RB voltage divider' sets voltage of false ground anywhere between VOUT of HV-2405E and ground.

2. RA and RS should be large values (e.g. 470K)
3. Circuits powered with this method must ALL be referred to "False Gnd"
4. Op amp must be able to source/sink load current

5. Example: RA = 4701<, RS = 470K. VOUT set to 24V. +VSUPPLY would be'" +12V
-VSUPPLY would be '" -12V

2-85

'HV-2405E
HV-2405E Parallel Operation

(Method #1)

R1
HV -2405E#1

3

6t-.....- - - . . . ,

1Q

AC
RETURN

7

61--+--'WIr-+-...,
51-;------'

NOTE: Operational Amplifler Cau.e. Each HV-2405E to
Contribute Equally to Output Current.

C4

HV-2405E Parallel Operation

(Method #2)

R1
C1
C2

AC
HIGH

R1

C1
AC
RETURN

C2

AIOUT ~ AVOUT

R3

NOTE: This Method Require. that the Output Voltage. of
Each HV-2405E are Close In Value.

C4

2-86

HV - 2405E#2

m

ICI.644/645/646/647
ICI.7644/7645/7646/7647

HARRIS

Low Voltage Step-Up Converters

July 1991

Features

Description

• +5V @ 40mA from a Single Cell Battery. Note: Output
Current can be Increased by Changing L2 (See Table 1)

The ICL644, ICL645 and ICL646 are low power fixed +5V
output step-up DC-DC converters designed for operation
from very low input voltages, All control functions and a
power FET are contained in the ICL644, ICL645 and
ICL647, minimizing external components, The ICL646
contains an output pin to drive an external FET when higher
output currents are required, A control pin changes be·
tween high power and low power standby modes. Standby
mode allows operating for extended periods with minimum
battery drain, and a power ready function is available for
controlling external-devices when the device is switched
between standby and high power. In high power mode, the
output current is approximately 40mA; in standby mode, it
is about 500IlA.

• Guaranteed Start-up ••••••••••••••••••••••• @1.15V
Typ O.9V
• Standby Mode ••••••••••••• SOIlA Quiescent Current
• Low Battery Indication
• Power Ready Function
• Shutdown Feature on
, 764X Series •••••••••••••••••••• 51lA Max Quiescent
• Pin to Pin Compatible to MAX65X Series
• Efficiency •••••••••••••••••••••••• 75% @ 1.2V Input

Applications
• Battery Powered Devices
• Single Cell Instruments
• Solar Powered Systems
• Pagers and Radio Controlled Receivers
• Portable Instruments
• 4-20mA Loop Powered Instruments

Minimum' startup voltage is 1.15V, but once started the
device will operate to lower voltages as the battery
discharges. A separate low battery monitor is available; it
can be used at its default value of 1.17V or may be adjusted
by the designer to any higher voltage.
The ICL644, ICL646 and ICL647 are optimized for single
cell (1.15V to 1.6V) battery operation and can also be used
with input voltages up to 4.0V. The ICL645 is designed for
two cell (or single lithium cell) operation with typical battery
voltages of 2.0V to 3.6V. The ICL647 is identical to the
ICL644 except its output voltage is preset to +3V. The
ICL764X series of products offer the same features as the
ICL64X with the addition of a shutdown feature. In the shut·
down mode the quiescent current is less than 51lA.

Pinouts

Ordering Information

ICL644, ICL645 & ICL647
ICL7644, ICL7645 & ICL7647
TOP VIEW

·ICL646
ICL7646
TOP VIEW

PART
NUMBER
ICL64XCPD

HP
GND

PACKAGE

OOCto +700C

14 Pin Plastic DIP
14PinSOlC

ICL64XCBD

OOCto +700C

ICL64XIPD

-400G to +850C

14 Pin Plastic DIP

ICL64XIBD

-400 C to +850C

14PinSOlC

CTL

HP
GND

TEMPERATURE
RANGE

PR
OUT

ICL764XCPD

OOCto+70OC

14 Pin Plaslic DIP

ICL764XCBD

OOCto+70OC

14 Pin SOIC

ICL764XIPD

-400C to +850C

14 Pin Plastic DIP

ICL764XIBD

-400 C to +850C

14PinSOlC

X=4,5,60r7

• Pin B Used On 764X Sorio. Only.
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

2-87

File Number

2781.1

~
u;
tJ)

~~

oS

ceo
D.ce

ceo
W

~
D.

ICL7644/7645/7646/7647

. Specifications ICL644/645/646/647

Operating Temperature

. Absolute Maximum Ratings
Peak Voltage at LX1 Pin ................................ +16V
Peak Voltage at LX2 or VCC Pin ••••••••••••.••••••••••.• +6.6V
Supply Voltage to l1 .•••••••••••••••••••••.•••••••••••• + 1 5V
Supply Voltage to l2, VCC •••••••••••••••••••••••••••.•• +5.6V
Peak Current, LX1 •••••••••••.•.••.••••••••.••• ; ••••••• 50mA
Peak Current, lX2 •••••••••••••••••••••••••••••••••••••• 1.6A
LBO Output Current ••••••••••••••••••••••••••••••••••• 50mA
Input Voltage, Cll, lBI (See Note) ••••••••••• -0.3V to (V+ +0.3V)
NOTE:

ICl64XCXX •••••••••••••••••••••••••••••••••••• OoC to +700 C
ICl64XIXX •.••••.•••....•••••••••••••••••.•• -400 C to +850 C
Storage Temperature. • • • . • • • • • • • • • • • • • • • • • •• -650 C to +1600 C
lead Temperature (Soldering, 10 Sec) •••••••••••••••••• +3000 C
Power Dissipation
PlasticDIP(derate10mWfOCabove700 C) •.•••••••.• 800mW
SOIC (derate 8.7mWfOC above 700C) ••••••••••••••.• 695mW

v+ Is generated at LX1. I", low current mode, it is 4.5V to S.6V (2.6V

to 3.6V on ICL646 & ICL7646); in high current mode. it is 10V to 15V.
Stresses above those listed under ,"Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those Indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device rei/ability.

ElectrIcal Specifications:

ICl644, ICl646, ICl647, ICl7644, ICl7646, ICl7647
(GND = OV, VBATT = 1.2V, TA = 250 C, Unless Otherwise Specified.)
UMITS

SYMBOL
VOUT

VlX1

TEST CONDITIONS

MIN

TYP

ICl644,ICl646 TA=OverTemp.*

4.5

5.0

5.5.

ICl647

2.7

3.0

3.3

V

-

0.9

1.0

V

PARAMETER
Output Voltage

Minimum Input Voltage to LX1

Il = OpA(Note 1)
Il=OpA

VlX1

Minimum Startup Voltage to LX1

VLX2

Input Voltage to LX2.

TA=OverTemp.*

MAX

UNITS
V

-

0.9

1.15

V

0.5

-

5.6

V

-

-

1.5

A

80

-

pA

ILX2

Peak LX2 Switch Current

ICl644, ICl647 (Note 1)

10

Standby Current

Il = 0pA, CTl = Open

fO

Switching Frequency

VBATT= 1.0to 1.6V

15.5

18

24

kHz

%ON

LX2, D Switch Duty Cycle

ICl644,ICl646

66

75

80

%

ICl647

50

66

75

%

ICl644,ICl646

27

36

49

liS

20

37

47

liS

0.40

-

0.67

tON

lX2, D Switch On Time

RDSON

lX2 On Resistance

ICl646,ICl647 (Note 1)

D Output Saturation Current

ICl646, Source Sink
(Short Circuit Current) .

ICl647

-

low Battery Input Threshold Voltage

1.12

low Battery Input Threshold Tempco
IlBI

low Battery Input Bias Current

VlBO

low Battery Output

VlBI

VlBI< 1.12V,llBO= 1.6mA
VlBI> 1.18V,llBO = -1pA

VPR

Power Ready

PR High,lpR = -1 pA

VCTl

CTllnput Threshold
Efficiency

NOTE:

100

V

-

-

mVfOC

-

0.Q1

10

nA

-

-

0.4

V

V+-1

-

-

-

VOUT
-0.2

-

0.3
0.07

5ma ::; IlOAD ::; 40ma

= OOe to +70 0 C
= -40oC to +850 C

2-88

rnA

-0.5

-

1. Not tested, guaranteed by design and characterization .

-

n
rnA

1.18

PR low,lpR = 1 pA

• Commercial Temperature Range
Industrial Temperature Range

-25

75

-

V
V
V
V
%

Specifications ICL 644/645/646/64 7

ICL7644/7645/7646/7647

Electrical Specifications: ICL645 & ICL7645 (GNO = OV, VBATI = 2.4V, TA = 25 0C, Unless Otherwise Specified.)
LIMITS
PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VOUT

Output Voltage

TA = OverTemperature"

4.5

5.0

5.5

V

VLX1

Minimum Input Voltage to LX1

IL=OJIA

-

0.9

1.0

V

VLX1

Minimum Startup Voltage to LX1

IL =0~A(Note1)

-

0.8

1.15

V

VLX2

Input Voltage to LX2

-

5.6

V

ILX2

Peak LX2 Switch Current

-

1.5

A

IQ

Standby Current

IL = OJlA, CTL = Open

fO

Switching Frequency

VBATI= 2.0 to 3.2V

(Note 1)

-

40

-

JIA

15.5

18

24

kHz

%ON

Switch Duty Cycle

40

50

60

%

CJ

tON

Switch On Time

15

28

38

I1s

ROSON

LX2 On Resistance

0.40

-

m

0.67

n

VLBI

(Note 1)

Low Battery Input Threshold Voltage

1.12

Low Battery Input Threshold Tempco

-

-0.5

V+-1

-

ILBI

Low Battery Input Bias Current

VLBO

Low Battery Output

VLBI < 1.12V,ILBO= 1.6mA
VLBI> 1.18V,ILBO = -1JIA

VpR

Power Ready

VCTL

Input Threshold
Efficiency

NOTE:

PR High,lpR = -1 JIA

-

PR Low,lpR = 1 mA

-

5mA::; ILOAD ::; 150mA

-

1. Not tested, Guaranteed by design and characterization.

* Commercial Temperature Range = OOC to +70 0C
Industrial Temperature Range

= -400C to +850 C

2-89

1.18

V

-

mVjOC

0.Q1

10

nA

-

0.4

VOUT
-0.2

-

:z

~~

o=>

0::0

c..o::

0::0

V
V
V

0.3

-

V

0.7

-

V

75

-

%

w

~
c..

ICL644/645/646/647

ICL 7644/7645/7646/764 7

Pin Description
ICL646,
ICL7646
PIN NUMBER

-

ICL644,ICL7644
ICL645,ICL7645
ICL647,ICL7647

NAME

FUNCTION

1

LX2

Output drain of high power N-channel MOS FET.

VCC

Connect to battery positive terminal.

-

2

V+

Output of low power up converter; 10 to 15V in high power
mode. 4.5V to 5.5V in standby mode.

2

-

V+

Output of low power up converter. 10 to 15V in high power
mode. 2.6 to 3.6V in standby mode.

3

3

IIC

Internal Connection. Leave this pin unconnec.ed. '·Do not ground."

-

7

GND

Low power ground.

4

4

VREF

1.295V bandgap reference output; should be decoupled with a
capacitor to pin 7. This terminal is high impedance and cannot
source or sink current.

5

5

LBO

Low battery monitor output Sinks 1.6mA when LBI is less than
1.17V, otherwise sources 1JlA from V+.

6

6

LBI

Low battery monitor input. Very high input impedance•.

S",14

S"

NC
"SD

No connection. "Shutdown pin on ICL764X series and no connect
pin on ICL64X series. Allows user to turn part off by grounding
pinS.

1

9

9

LX1

Output (drain) of low power N-channel power driver.

10

10

OUT

+5V (+3V on ICL647). Feedback (input) pin for high power
operation; output pin in standby mode.

11

11

PR

Power ready output; high (+5V on ICL644, 645, 646; +3V on
ICL647) when high power converter Is ready to supply power.

7·

12,14

HP,GND

High power ground.

13

13

CTL

Control mode switch Input; ·open circuit or high for slandby
mode, ground for high power mode.

12

-

D

Driver output to external FET. Output voltage swings from GND
toVOUT·

Low Voltage Step-Up Converters
Operating Principle
The ICL644, ICL645, ICL646 and ICL647 are flyback, or
boost converters: energy from the battery Is first stored in a
coil and then discharged to the load. Essentially, the circuit
consists of a battery in series with a coil, a high power FET,
rectifier, and filter, as shown in Figure 1. When the switch is
closed, current builds up in the coil, creating a magnetic
field. During the second half, or flyback part of the cycle, the
power FET opens, the magnetic field collapses and the voltage across the inductor reverses polarity, adding to the voltage of the battery and discharging through the rectifier into
the load.
The switch is controlled by a constant frequency oscillator
whose output is gated on and off by a comparator that
monitors the vutput voltage. When the output voltage is
above the comparator threshold, the power FET skips an
entire cycle of the oscillator. This pulse skipping technique
varies the average duty cycle to achieve regulation, rather
than varying the period or duty cycle of each cycle of the
power FET; it eliminates a number of linear circuits that
would otherwise add both circuit complexity and quiescent
operating current.

The key to operating CMOS circuitry from a 1V supply
depends on a technique called bootstrapping. A specially
designed oscillator starts itself up on a very low voltage and
builds up (or bootstraps) a higher voltage that in turn is used
as the supply for further operation. This supply yields higher
efficiency because the bootstrapped voltage drives the gate
of the internal power FET transistor to lower on resistance.
When power is first applied, the circuit is very inefficient (for
the first cycle) until a higher voltage is generated on the
flyback half of the first cycle. This higher voltage is rectified
and filtered, and powers the whole IC (and thus the oscillator) for the next cycle. Since each cycle generates a higher
voltage for the next cycle, the voltage builds up very rapidly.
An internal regulator limits the voltage to about 12V. The
load for this supply is only the CMOS chip itself, so the
requirements for the components, particularly the external
inductor L 1, are very broad. This voltage is brought out to
the V+ pin and is connected to a tantalum capacitor for
filtering.

2-90

ICL7644/7645/7646/7647

ICL644/645/646/647

Dl

This bootstrapped 12V drives an internal N-channel power
FET that furnishes the switching power for the load. Since
the gate of this FET is driven from a 12V supply, it has a very
low on resistance and can efficiently switch high currents
through a second inductor, L2. It is the power stored in this
second inductor that is delivered to the SV load via an
external Schottky diode. The rectified and filtered SV output
is connected back to the OUT pin to provide feedback. The
ICL644/64S/646/647 thus has two separate switching
circuits and uses two separate inductors.
Circuit Details
A typical application circuit is shown in Figure 2. The higher
value inductor, L1, is typically 4.7mH, and may have fairly
high losses. It is used for the low power section of the circuit
and is rectified by an internal diode and routed to pin 2, V+,
where it is filtered by an external capacitor, C 1. The second
inductor, L2, varies from 3911H to SOOIlH, depending on
input voltage and load current. It must have low series
resistance and sufficient core material to handle the load
power without saturating. The inductor is connected to pin 1
(LX2), the drain of the Low Power FET, and is rectified by an
external Schottky diode, D1, and filtered by an external
capacitor, C2. This is the main +SV output (+3V on the
ICL647), and it is connected to OUT, pin 10, which is the
feedback input in high power mode. Figure 3 shows a
similar circuit for the ICL646 using an external FET for
higher power output.

FIGURE 1. ICL644/645 BLOCK DIAGRAM

By lowering the internal 12V supply to SV, the leakage currents of the CMOS circuits and the losses aSSOCiated with
its voltage reference and oscillator are reduced to a minimum. The internal low power SV supply can furnish up to
SOOIlA, and it is connected to the normal SV output pin
(OUT) to supply current to the load, keeping alive standby
circuits.

~~
05

v+

a: (,)
c..a:
a:o
w

~
c..

+

BAn~

4

lBI

ICL644

REF

ICl645
ICl647
ICl7644

GND

-

12.14

OUT

10

ICL7645
ICL7647

CTl

Cl
22}4F

v+

+

HP GND
SEE TABLE 1.

FOR L2 INDUCTOR
PART NUMBERS

5

L1 • TOKQ
PART NUMBER
lOllY' 472

NC

*

Pin 8 used on 764X series only.

FIGURE 2. ICL64X/764X TYPICAL APPLICATION

+

vee

+

BAn~

LXl

C2~

D

470jl.f

lBI
4

Power Ready Output Pin
During initial start up (and when placed in standby mode),
the ICL644/64S/646/647 internal voltages are too low to
drive the power FET efficiently. A separate comparator
determines when this voltage has reached a high enough
value to drive the FET. The output of this comparator gates
the FET drive voltage. This scheme extends battery life in
standby mode and prevents the power FET from stalling
when switching to high power mode. The comparator
output is also brought out to the POWER' READY (PR) pin
and can be used to control external circuits, further
reducing battery drain.

z

en

(J)

Low Power Standby Mode
A control pin (CTL) is available for putting the device into
standby mode to conserve power. When this pin is held low,
the IC operates in the high power mode, if it is driven high or
left open the following occurs: the POWER READY (PR) pin
is driven low, the high power FET is gated off, the 12V (V+)
switching supply is reduced to sv (+3Von the ICL647) and
is connected to the VOUT pin.

(!j

REF
ICl646
ICl7646

OUT

+5V
2SOmA

-=-

10
Cl
22jl.F +

CTL
v+

2
SEE TABLE 1.
FOR L2 INDUCTOR
PART NUMBERS

L1 -TOKO
PART NUMBER
la7lY -332

2-91

NC

*

Pin 8 used on 7646 series only.

FIGURE 3. ICL646/7646 TYPICAL APPLICATION

ICL7644/7645/7646/7647

ICL644/645/646/647
Start Up and Mode Considerations

Inductor Selection

The ICL644/64S/646/647 may be started up in either the
low power (standby) or high power mode. When starting In
the high power mode, both the low power switch and the
high power switch start Immediately. Whether or not the
load Is connected, the output voltage will rise to SV in the
first few cycles. The OUT pin becomes an Input for
feedback to control regulation.

Low Power Coli

If the high power load (greater than about SOOjlA) Is
connected to the OUT pin and the device Is placed In the
low power mode (CTL pin driven high or left open), the low
power oscillator will have to furnish all of the SV power via
the OUT pin, and the low power oscillator will stall. It Is,
therefore, Important to disconnect any load currents
(greater than 500jlA) whenever the low power or
standby mode Is selected. The POWER READY (PRI pin
may be used to disconnect the load via an external transistor. This way the mode and connection of the high power
load are both controlled through the CTL Input.
Input Filtering
It is Important to limit the rate of rise of the battery voltage
when the circuit is first turned on with a mechanical switch
or the Installation of the battery(ies). A simple R-C network
made up of the battery Internal resistance and a 10llF
tantalum capacitor placed at the battery side of L2 input is
sufficient for this purpose. This capacitor also helps to
absorb the (relatively) high peak currents that are drawn
from the battery In the high power mode.
Output Filtering
It Is also important to limit the speed at Which V+ decreases
to sv when the mode is switched from high power to
standby. This is accomplished by putting a 2211F capacitor
between the V+ and OUT pins. Also, a 220llF capacitor
placed on the OUT pin provides both filtering and serves to
hold up the SV during the switchover period. Without these
capacitors, the SV may spike negatively during the
switchover.
Low Battery Function
A completely independent low battery monitor is built Into
the ICL64X series and the ICL764X series. Its Input (LBI) is
the + input of a CMOS comparator whose - input is connected to the Internal 1.17V band-gap reference. This input
can be connected directly to the battery In single cell circuits or connected to a high resistance voltage divider for
higher voltage monitoring. The output (LBO) can sink 1.6mA
or source several microamperes from V+.
Shutdown Function

The choice of the low power Inductor, L1, is not critical. A
4.7mH coli with a DC resistance of less than 400 Is
adequate for most applications. In general, higher
inductance values allow lower start up voltages, while lower
resistances yield lower quiescent current In standby mode.
I! the inductance is made too high, the low power (V+)
output voltage and current are reduced. This in turn reduces
the efficiency of the power section, so the +SV output (in
standby mode) supplied less current. Lower values of
inductance raise the minimum start up voltage.
High Power Coli
The high power coil, L2, must store most of the energy that
flows Into the load. Accordingly, it should have a powdered
Iron or ferrite core and should have low resistance to
minimize losses. It also must have an adequate current ratIng to prevent saturation.
Calculating the worst case inductor for the high power
section (LX2) of the ICL644/64S/646/647 Is a two step
process:
1. Determine the smallest Inductor value that will not cause
the circuit to exceed the peak current rating of the ICL644/
64S/647 with the highest expected input voltage (VINMAX),
the longest on time (tONMAxl, and the lowest total resistance (R(MIN». R(MIN) is the sum of the minimum coli
and FET resistances. Note that th Is peak purrent relates to
the inductor and the FET switch and Is several times the
load current.
The following example assumes the minimum frequency
fO(MIN) and the maximum % ON(MAX) for the calculation of
tON(MAX). Although the calculated value for tON(MAX) Is
above that specified In the electrical characteristics table
(49I1S), the illustration is still a valid one that yields a worst
case minimum Inductor value.
NOTE: Units with both fO(MIN) and %ON(MAX) values near
the ends of the allowed distributions will be rejected for
tON(MAX)·
From the Electrical Characteristics table:
IpK LX2 = 1.SA
RDSON(MIN) = 0.40
fO(MIN) = 1S.500Hz
Duty Cycle Maximum, %ON(MAX) = 0.8
then:
tON(MAX)

The ICL764X series is equipped with a shutdown feature.
Pin 8, a no connect pin on ICL64X series, is used to power
the part down. During shutdown the part draws less than
SjIA quiescent current. The part can be shutdown by
grounding pin 8. When pin 8 is left floating the part is
identical to the ICL64X series.

= %ON(MAXjlfO(MIN) = 0.8/15500 = 51.611S

Assume that the minimum coli resistance. RCOIL(MIN) Is:
RCOIL(MIN)

= 0.10

The minimum total resistance, R(MIN) is:
R(MIN)

2-92

= ROSON(MIN) + RCOIL(MIN) = 0.4 + 0.1 = 0.50

ICL 7644/7645/7646/764 '7

ICL644/645/646/647
then:
IpK = 1.5A = VIN(MAX)
R(MIN)

x [1-e -R(MIN) x tON(MAXyl(MIN)]

Using a 47 ± 10% IlH coil with a resistance of 0.150, an input
voltage of 1.1V, and the worst case highest output voltage of
5.5V. The calculated minimum DC output current is 32mA This
assumes a D.3V forward drop in the 1N5818 diode.

or:
-R(MIN) tON(MAX)
In [(1 -R(MIN)XIPKNIN(MAX»]

For a maximum input voltage of 1.56V (single alkaline cell),
and a minimum coil resistance of 0.10, the minimum
permissible inductance for the ICL644/645/647 is
39.37IlH.
2. Having determined the minimum inductance (L(MIN))
that keeps the peak current below the individual component
ratings, we next calculate a new peak current (I'PK) using
the highest resistance (R(MAX)), the lowest input voltage
(VIN(MIN)) and the shortest on time (tON(MIN)).
Using these parameters, we will calculate the minimum
available output (DC) current.

When selecting a coil, care should be exercised to insure that
the minimum inductance value, including all the manufacturing
tolerances, is never lower than the calculated inductance, or the
peak current rating of LX2 may be exceeded. In addition, the
current rating of the coil should be greater than the peak
current used in the calculation (1.5A, normally), to avoid
saturating the core.

H the worst case output current is too small, then either the
minimum input voltage must be increased or the maximum
input vottage should be decreased. It is always desirable to
decrease the ratio between maximum and minimum input
voltages. The coil resistance also has a significant effect on the
output current, so selecting a lower coil resistance will increase
the output current and increase the overall efficiency.

H no satisfactory value of inductance can be found for the

From the Electrical Characteristics table:

desired current, the ICL646 may be used with an external FET
whose peak current exceeds 1.5A The calculations are similar
for the ICL644 except the external FETs RDSON and current
rating should be substituted in the above equations.

RDSON(MAX) = 0.670
iO(MAX) = 24kHz
Duty Cycle Minimum, %ON(MIN) = 0.66

Hthe worst case output current is significantly higher than the

then:
tON(MIN)

= %ON(MIN)/fO(MAX) = 0.66/24000 = 27.511S

Assume that the maximum coil resistance, RCOIL(MAX) is:
ReOIL(MAX) = 0.150

The maximum total charging resistance, R(MAX) is:
R(MAX)

= RDSON(MAX) + ReOll(MAX) = 0.820

At the end of the ON period:
I'PK = VIN(MIN) x
R(MAX)

1-e -R(MAX) x tON(MIN)/L(MIN)

The energy stored in the coli is:
l(MIN) x I'PK2
2

EeOll

And the power put into the coil Is:
iO(MAX) x EeOll

PeOll

4MIN) x I'PK2 x fO(MAX)
2

The minimum DC output current, lOUT, is:
IOUT(MIN)

=

PlOAD =
PeOll - PLOSS
VlOAD
VOUT(MAX) + VDIODE - VIN(MIN)

required load curren~ a higher inductance value may be used.
This will tend to reduce the peak current and the ripple voltage.
Be sure to adjust the coil resistance and recalculate all the
values.
When the maximum battery voltage exceeds 1.65V, the
ICL645 should be used. Calculations for the ICL645 are
identical to the ICL644 calculations, except that different values
must be used for the maximum and minimum duty cycles.
In general, if a choice of batteries is available, higher input
voltages are preferred for two reasons. First, as the input
voltage approaches 1V, the load on the battery increases while
the losses increase. The losses become so dominant that
efficiency suffers and little output current can be
maintained. Second, certain losses, such as the coil
resistance and the FET on resistance are less significant with
higher input voltages. This means not only higher
effiCiency, but a greater range of input voltages are
tolerable; this in turn means that more of the chemical
energy can be converted into electricity. For example, three
NiCd cells, with a fully charged voltage of 4.05V, may still be
used down to 1.1V (with about 5mA of 5Voutput current), far
beyond the normal life expectancy.
The inductance values for commonly encountered battery
operated power supplies are tabluated in Table 1.

PeOll -I'PK2 x (ReOll(MAXy'3) x (1 - %ON(MIN»
VOUT(MAX) + VDIODE - VIN(MIN)

2-93

(!I

z

en
en

~f!?
a:u
Il.a:
a:C3
UJ

05

s:
o
Il.

ICL7644/7645/7646/7647

ICL644/645/646/647

TABLE 1. MINIMUM INDUCTANCE FOR COMMON BATTERIES
COIL SPECIFICATIONS (L2)
TOKO aRBS 262LYF SERIES

BATTERY VOLTAGE
BATTERY TYPE

*

OUTPUT

I'H'

OHMS

PART NO.

43mA

39

0.09

-OO87K

43mA

47

0.10

-0088K

SV

150mA

33

0.80

-0086K

2.70V

SV

64mA

68

0.16

-0090K

2.40V

3.10V

SV

62mA

82

0.17

-0091K

2.60V

3.60V

SV

64mA

100

0.22

-0092K

MIN

MAX

1 NiCads(ICL644)

1.lSV

1.3SV

SV

1 Alkaline (ICL644)

1.20V

1.SSV

SV

1 Alkaline (ICL644)

2.SV

3.SV

2 NiCads (ICL64S)

2.30V

2 Alkallnes (ICL64S)
1 Lithium (ICL64S)
1 NiCad (lCL646)*'

1.lSV

1.3SV

SV

2S0mA

12

0.049

-0081K

1 Alkaline (ICL646)**

1.20V

1.SSV

SV

275mA

6.8

0.037

-0079M

1 Alkaline (ICL647)

1.20V

1.SSV

3V

60mA

39

0.09

-0087K

COils are from Toka.lnductance (pH) is the MINIMUM allowed for tho listed
baHery voltage range (BaHery Voltage: MIN, MAX). Lower values are not
recommended, except when using thelCL646/7646 converters since they
use an external MOSFET. If less current than listed in the Output column is
needed, a higher inductance coil will reduce losses. The optimum induct-

ance varies inversely with required outRut current if all other conditions are
unchanged. for example, refer to line 3 and the 10mA output. 120~H
supplies this current more effiCiently than the 39/lH coil of line 2. L2 may also
be calculated using the equations in the Inductor Selection Section.

.. These ICl646 circuits use an external current switch. Peak switch current
is typically 3.5A.

CapaCitor Selection

Rectifier Selection

The high current fast rise-time pulses associated with
switcbing power supplies demand good grounding and
bypassing techniques. The ICL644/645/647 have 3 ground
pins to improve grounding. In addition, the internal voltage
reference is brought out for connection to an external 1nF
capacitor, minimizing noise and modulation on the
reference.

The ICL644 - 647 and ICL7644 - 7647 use one external
rectifier. To achieve specified performance at low voltage, a
Schottky type, such as the 1N5818, is recommended
because it combines low forward voitage drop with fast
switching speed. This maximizes power conversion
efficiency and output current when the DC-DC converter is
in high power mode. One drawback of Schottky rectifiers is
relatively high reverse leakage current (at 5V reverse,
lN5818 leakage is typically 601lA at 250 C and 4501lA at
750 C), which is quite large with respect to the circuit's
quiescent current in standby mode (typical standby current
ICL644/646/647 and ICL7644/7646/7647: 801lA, ICL645
and ICL7645: 40flA). If standby mode is not used or used
only for short periods, reverse leakage is not a significant
additional loss compared to the normal load current, and
need not be considered.

The two output voltages, V+ and +5V should be filtered with
tantalum capacitors, or other capacitors with low effective
series resistance, to minimize transients. If aluminum
electrolytic capactors are used, they should be paralleled
with O.lflF disc ceramics.
Selecting Low Power Switching Diodes
The ICL644/645/646/647 use one external diode, and this
diode must be a Schottky. A common Schottky type that
performs well is the 1N5818.
In applications where standby current must be minimized,
the diode's reverse leakage characteristics are especially
important. The ICL644/646/647 (40flA for the ICL645)
standby current is typically 80flA, while the reverse current
of some Schottky rectifiers can exceed this value,
particularly at high temperature. If necessary, diode leakage
can be reducpd with higher voltage Schottky types such as
1N5817. If standby mode is not used or is used only for
short periods, then diode leakage is not a significant
additional loss compared to the normal load current and
need not be considered.

If quiescent operating current Is a primary concern, or if the
ICL644 - 647 and ICL7644 - 7647 spends most of its time
in standby mode, a silicon rectifier such as the 1N4933 or
Unitrode UESl 001 may be preferred. Silicon rectifiers have
less reverse leakage cu rrent than do Schottky rectifiers
(1 N4933 leakage current is typically 1IlA at 25 0 C and 501lA
at 1000 C). In circuits where the standby mode is the
predominant mode of operation, battery life may be
extended by trading conversion efficiency for lower standby
quiescent current.

2-94

ICL7644/7645/7646/7647

ICL644/645/646/647·

Output Current vs. Input Voltage,

INDUCTOR

TOKO PART NUMBER

331lH
471lH
100llH
150llH
220llH

-0086K
-0088K
-0092K
-0094K
-0096K

Figures 4 through 7 show output current versus -input
voltage using typical inductor values for each part in the
ICL644 - 647 and ICL7644 - 7647 series. Where curves
end in the middle of the graphs, the peak current limit of the
internal LX2 switch has been reached. A highe[ input
voltage than indicated by.that line (for the given inductor)
may damage the device. Figure 6 assumes that an IRF541
MOSFET is used (0.0850 maximum on resistance).

The coils used in Figure 6 are the Toko series inductors.

Dashed lines indicate regions where the LX2 current limit
hasn't been exceeded, but the current rating of the selected
coil has. The actual voltages where lines end or become
dashed are indicated by arrows on the graphs. The output
currents indicated by dashed lines can be achieved only
with inductors of higher current rating than the indicated
coil. The coils used in Figures 4, 5 and 7 are as follows:

The graphs in Figures 4 - 7 were calculated· using worst
case data, so individual circuits may supply more current
than indicated. If the coils' current ratings are not exceeded,
smaller, lower-cost coils than those indicated may be used _
in low-current applications. Use the equations in the text to
calculate worst case peak coiVswitch current to be sure that
a particular coil's current rating is sufficient

~

U5

fficn

0>-

oS
0::0

ISO

c..o::
o::u
w

2CCl

o
==
c..
ISO

47~H

100
68!JH

1 100
:a

I~H

SO

lSOII-H
SO

220tJH

o
09

0
11

13

15

17

2I

16

19

=5V)

RGURE 5. ICL645/7645, lOUT vs. VIN (VOUT = 5V)

500

200
l.

12~H

400

:a

ISO

300

l.15I1H.

200

l.22J1H

100

l =4711H

<
§.

.a

l.33I1H

0

36

VI" (V)

RGURE 4. ICL644/7644, lOUT vs. VIN (VOUT

1

3I

26

VINIV)

09

II

13

15

17

SO

19

0

09

1.1

13

IS

17

VINIV)

VI" (VI

RGURE 6. ICL646/7646, lOUT vs. VIN (VOUT

100

=5V)

FIGURE 7. ICL647/7647, lOUT vs. VIN (VOUT = 3V)

2-95

19

ICL7660
CMOS Voltage Converter
GENERAL DESCRIPTION

FEATURES

The Harris ICL7660 is a monolithic CMOS power supply
circuit which offers unique performance advantages over
previously available devices. The ICL7660 performs supply
voltage conversion from positive to negative for an input
range of + 1.5V to + 10.0V, resulting in complementary output voltages of -1.5V to -10.0V. Only 2 non-critical external capacitors are needed for the charge pump and charge
reservoir functions. The ICL7660 can also be connected to
function as a voltage doubler and will generate output voltages up to + 18.6V with a + 10V input.
Contained on chip are a series DC power supply regulator, RC oscillator, voltage level translator, and four output
power MOS switches. A unique logic element senses the
most negative voltage in the device and ensures that the
output N-channel switch source-substrate junctions are not
forward biased. This assures latchup free operation.
The oscillator, when unloaded; oscillates at a nominal frequency of 10kHz for an input supply voltage of 5.0 volts.
This frequency can be lowered by the addition of an external capacitor to the "osc" terminal, or the oscillator may
be overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV) operation. At medium to high voltages (+ 3.5 to + 10.0 volts),
the LV pin is left floating to prevent device latchup.

• Simple Conversion of + SV Logic Supply to ± SV
Supplies
• Simple Voltage Multiplication (VOUT=(-) nVIN)
• 99.9% Typical Open Circuit Voltage Conversion
Efficiency
• 98% Typical Power Efficiency
• Wide Operating Voltage Range 1.SV to 10_0V
• Easy .to Use - Requires Only 2 External
Non-Critlcal Passive Components
• No External Diode Over Full Temperature and
Voltage Range

APPLICATIONS
• On Board Negative Supply for Dynamic RAMs
• Localized ,..-Processor (8080 Type) Negative
Supplies
• Inexpensive Negative Supplies
• Data Acquisition Systems

ORDERING INFORMA110N
Part Number

An enhanced direct replacement for this part, the
ICL7660S, Is now available and should be used for all
new designs.

Temp. Range

ICL7660CTV

0' to +70'C

ICL7660CBA

O'Cto +70'C

ICL7660CPA

0' to +70'C

ICL7660MTV'

-55' to + 125'C

Package
TO-99
8PINSOIC
8 PIN MINI DIP
TO-99

• Add 18838 to part number if 8838 processing is required.

v+ (and CASEI

v+

8

OSC
LV

0319-1

(Outline Dwg BA)
8 LEAD S.O.

0319-3

0319"2

(Outline Dwg TV)
8 LEAD TO-99

(Outline Dwg PAl
8 LEAD MlnlDIP

Figure 1: Pin Configurations

HARRIS SEMICONDUCTOR'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE
CONDITION OF sALE. THE WARRANTY SHAll BE EXCLUSIVE AND SHALL BE IN ·UEU OF All. OTHER WARRANTIES. EXPRESS, IMPUED OR STATUTORY. INCLUDING THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
302063-005

NOTE: AU typical values haV8 been chsrsclBrized but are not testBd.

~-96

ICL7660
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................. 10.5V
LV and OSC Input Voltage
(Note 1) ............ - 0.3V to (V + + 0.3V) for V + < 5.5V
(V + - 5.5V) to (V + + 0.3V) for V + > 5.5V
Current into LV (Note 1) ............. 20fLA forV+ >3.5V
Output Short Duration (VSUPPLy:5: 5.5V) ....... Continuous
Power Dissipation (Note 2)
ICL7660CTV ............................... 500mW
ICL7660CPA ............................... 300mW
ICL7660MTV ............................... 500mW

Operating Temperature Range
ICL7660M ........................ -55"Cto + 125"C
ICL7660C ............................ O"C to + 70"C
Storage Temperature Range .......... - 65"C to + 150"C
Lead Temperature
(Soldering, 10sec) .............................. 300"C

NOTE: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sec/ions of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended pen"ods may affect device reliability.

CI

V+
CAP +
CAP-

z

en


0319-9

NOTE:AUtyplcal _ _ _ chaJoc_bulsronottostod.

2-98

--

~ I-""'"

..........

~=+2Y

-

~

V+=5V

-50' -25· 0" +25" -+50' +75'+100"+125"
TEMPERATURE I'C)
0319-10

ICL7660
TYPICAL PERFORMANCE CHARACTERISTICS
POWER CONVERSION EFFICIENCY
AS A FUNCTION OF OSC.
FREQUENCY
100

g

T

98

to

=+25"<:
lOUT

96

i3

§

1

:z

["--..,

90

=15mA

88

~

:z
0

86

~

84

u

0

~

8

z

~ 14

g
fE
a:

y+

80

100

OSC. FREQUENCY

10

::!

8

V+=+5V

g

10

10k

lk

100

1000

10K

o

"'

'-..
~

6
--50

Cose (pI)

lose (Hz)

"\

12

o

~

-$V

~Allt~'?

=+5V

6:\

>- 1
u

"\

v+

82

~

~

2

"

-

1

lOUT

UNLOADED OSCILLATOR
FREQUENCY
AS A FUNCTION OF TEMPERATURE

!!

I

92

~

.....

=1 rnA

94

(Circuit of Figure 3) (Continued)

FREQUENCY OF OSCILLATION AS
A FUNCTION OF EXTERNAL
OSC. CAPACITANCE

25

0 +25 +50 +75 +100 +125
TEMPERATURE ('C)

0319-12

0319-13

0319-11

5

:

J25·b

,-iA=
V' =+5V

~ 2

I:

1

-1

o

~

il!
8

l

::>-2

i

-3

./

-4

"

-5 0

80

z

'I

0

~

~

w

!:i
o
>
....
t....

g

100
90

r.....

PEFF

70
50

\

1/

40

\

/

/

TA ;:: +25OC
v+ = +5V

/

V
10

SLOPE 550
10 20 30 40 50 60 70
LOAD CURRENT IL(mA)

jif-o

1/

60

30
20
10

.,

I""S-

I 00
1·- 90

20

40

50

+2

~
~

:g

80 !<
70
~
60
50
40 3'
30 .e.
20 z
~
1o

~

-.

o
30

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

.e-

TA b +2~'C
V+=2V

wH

"~

\

\
\

\

0

>

....

::>

""::>....

0_1

60

LOAO CURRENT IL (mA)

80

-2
0319-15

0319-14

.- .....

l./
......
~rpEI150{
......

~

0123456
LOAD CURRENT IL (mA)
0319-16

SUPPLY CURRENT & POWER CONVERSION EFFICIENCY
AS A FUNCTION OF LOAD CURRENT
100

I"""--..

g90

t;
is

ro

~

50

z

30

~

20

~z

8

~

,.

"""I..

~

PErr -"' .......

70

/r-,

60
40

fA

= +2SOC

v·

= +2.0V

./

/

~

I 4.0
I 2.0

g

8.0

10

o

I 6.0

I 0.0

/'

o/

20.0

NOTE 3. These curves include 1n the supply current that current fed directly
into the load RL from V+ (See Agure 3). Thus. approx1mately half the supply

current goes directly to the positive side of the load. and the other half,

18.0~

through the ICL76aO, to the negative side of the load. Ideally. V OUT ::.! 2 V 1N •

IS ~ 2 IL• so VIN x IS ~

ill

~

!

6.0
4.0

Z

2.0

!ol

~

OmA
1.5

3.0

4.5

6.0

7.5

9D

LOAD CURRENT IL (rnA)
0319-17

NOTE: AlllyplCal values have been characterized but are not tested.

2-99

rn

~~
0::;
0:0

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

C!J
Z

U)

Your x IL•

D..O:

0:0
W

~

ICL7660
~ y+
1 8 I - - - - - - _ H f - o (+5V)

V,N

o>-_ _ _s~ ~
I

7 ---------.

~!
-=:
·Cosu.

±

~•

: Cl
I
I
I
1
S31

~
RL

..l.

::
I
I
I
I

JlJ1JlQ

rVOUT

_

C2

S41~

-~:
0319-19

Figure 4: Idealized Negative Voltage Converter

0319-18

NOTE: 1.

For large values ofCosc (>1000pF) the values of C, and
C2 should be increased to 100"F.

Figure 3: ICL7660 Test Circuit

THEORETICAL POWER EFFICIENCY
CONSIDERATIONS
In theory a voltage converter can approach 100% efficiency if certain conditions are met:
A
The drive circuitry consumes minimal power.
8
The output switches have extremely low ON resistance and virtually no offset.
C
The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The ICL7660 approaches these conditions for negative
voltage conversion if large values of C, and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E=Y.C, (V,2-V22)
where V, and V2 are the voltages on C, during the pump
and transfer cycles. If the impedances of C, and C2 are
relatively high at the pump frequency (refer to Figure 4)
compared to the value of RL, there will be a substantial
difference in the voltages V1 and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly
large value for C, in order to achieve maximum efficiency of
operation.

DETAILED DESCRIPTION
The ICL7660 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2
external capacitors which may be inexpensive 10ILF polarized electrolytic types. The mode of operation of the device
may be best understood by considering Figure 4, which
shows an idealized negative voltage converter. Capacitor
C, is charged to a voltage, V+, for the half cycle when
switches 5, and 5a are closed. (Note: 5witches 52 and 54
are open during this half cycle.) During the second half cycle of operation, switches 52 and 54 are closed, with 5, and
5a open, thereby shifting capacitor C, negatively by V +
volts. Charge is then transferred from C, to C2 such that the
voltage on C2 is exactly V+, assuming ideal switches and
no load on C2. The ICL7660 approaches this ideal situation
more closely than existing non-mechanical circuits.
In the ICL7660, the 4 switches of Figure 4 are M05 power switches; 5, is a P-channel device and 52, 5a & 54 are
N-channel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of 5a & 54
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON" resistances. In addition, at circuit startup, and under output short
circuit conditions (VOUT=V+), the output voltage must be
sensed and the substrate bias adjusted accordingly. Failure
to accomplish this would result in high power losses and
probable device latchup.
This problem is eliminated in the ICL7660 by a logic network which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of 5a & 54
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7660 is an integral
part of the anti-latchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore,
to improve low voltage operation the "LV" pin should be
connected to GROUND, disabling the regulator. For supply
voltages greater than 3.5 volts the LV terminal must be left
open to insure latchup proof operation, and prevent device
damage.

DO'S AND DON'TS
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GROUND for supply
voltages greater than 3.5 volts.
3. Do not short circuit the output to V+ supply for supply
voltages above 5.5 volts for extended periods, however,
transient conditions including startup are okay.
4. When using polarized capacitors, the + terminal of C1
must be connected to pin 2 of the ICL7660 and the
+ terminal of C2 must be connected to GROUND.
5. If the voltage supply driving the 7660 has a large source
impedance (25 - 30 ohms), then a 2.2!1f capacitor from
pin 8 to ground may be required to limit rate of rise of
input voltage to less than 2V/IlS.
6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will
occur under these conditions.
A 1N914 or Similar diode placed in parallel with C2 will
prevent the device from latching up under these
conditions. (Anode pin 5, Cathode pin 6).

NOTE: AN typical vsJues haYS be8n chBraclfllizsd but arB no/ tBSI8d.

2-100

ICL7660

' - " , , - 0 YOUT

=-v+

y+

~10J'F

+

0319-30

a) Configuration

~

YOUT

0319-20

b) Thevenin Equivalent
Figure 5: Simple Negative Converter
CJ

:z

en
faU)
01-

05
a:o
Q.a:

a:o
w

~
Q.

0319-28

Figure 6: Output Ripple

0319-21

Figure 7: Paralleling Devices

NOTE: All typical values have been characterized but lU8 not tested.

2-101

ICL7660

YOUT=-nY·

0319-22

Figure 8: Cascading Devices for Increased Output Voltage
C1 > 10 fLF and there is no longer enough time to fully
charge the capacitors every cycle. In a typical application
where fosC= 10 kHz and C = C1 = C2 = 10 fLF:

TYPICAL APPLICATIONS
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660 for generation of negative supply voltages. Figure
5 shows typical connections to provide a negative supply
where a positive supply of + 1.5V to + 10.0 volts is available. Keep in mind that pin 6 (LV) is tied to the supply negative (GND) for supply voltages below 3.5 volts.
The output characteristics of the circuit in Figure 5a can
be approximated by an ideal voltage source in series with a
resistance as shown in Figure 5b. The voltage source has a
value of -V+. The output impedance (Ro) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 4), the switching frequency, the value of C1 and C2,
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for Ro is:

1
Ro "" 2 (23) + (5 e 103) (10 5) + 4 (ESRC1) + ESRC2

Ro '" 46 + 20 + 5 (ESRd
Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1l(fpUMP e C1) term, rendering
an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as
high as 100..

Output Ripple
ESR also affects the ripple voltage seen at the output.
The total ripple is determined by 2 voltages, A and B, as
shown in Figure 101. Segment A is the voltage drop across
the ESR of C2 at the instant· it goes from being charged by
.C1 (current flow into C2) to being discharged through the
load (current flowing out of C2). The magnitude of this current change is 2 elout, hence the total drop is 2 elouteeSRc2
volts. Segment B is.the voltage change across C2 during
time t2 .. the half of the cycle when C2 supplies current to the
load. The drop at B is lout et2/C2 volts. The peak-to-peak
ripple voltage is the sum of these voltage drops:

Ro "" 2(RsWl + RSW3 + ESRC1) +
2(RSW2 + RSW4 + ESRC1) +
1
----+ESRC2
(fpUMP) (C1)
(fpUMP = fo: c , Rswx = MOSFET switch resistance)
Combining the four Rswx terms as Rsw, we see that:

V'ipple '" [2

1
Ro "" 2 (Rsw) + (fpUMP)(C1) + 4 (ESRC1) + ESRC2

(fpu~p) (C2) + 2 (ESRC2)] lout

Again, a low ESR capacitor will result in a higher performance output.

Rsw, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resistance graphs), typically 230. @ 25°C and 5V. Careful selection of C1 and C2 will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce
the 1l(fpUMP e C1) component, and low ESR capacitors will
lower the ESR term. Increasing the oscillator frequency will
reduce the 1/(fpUMP e C1) term, but may have the side
effect of a net increase in output impedance when

Paralleling Devices
Any number of ICL7660 voltage converters may be paralleled to reduce output -resistance. The reservoir capacitor,
C2, serves all devices while each device requires its own
pump capacitor, Cl. The resultant output resistance would
be approximately:
ROUT

NOTE: AN typical values haVfJ been characterizsd but ars not tested.

2-102

ROUT (of ICL7660)
n (number of devices)

ICL7660
Cascading Devices
The ICL7660 may be cascaded as shown to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical
limit is 10 devices'for light loads. The output voltage is defined by:

Cosc
C,

VOUT= -n (VIN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7660 ROUT
values.

m---4>---o

0319-24

Changing the ICL7660 Oscillator
Frequency

Figure 10: Lowering Oscillator Frequency

It may be desirable in some applications, due to noise or
other .considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an external clock, as shown in Figure 9. In order to prevent possible
device latchup, a 100kO resistor must be used in series with
the clock output. In a situation where the designer has generated the external clock ·frequency using TTL logic, the addition of a 10kO pullup resistor to V + supply is required.
Note that the pump frequency with external clocking, as
with internal clocking, will be 'Iz of the clock frequency. Output transitions occur on the positive-going edge of the
clock.

Positive Voltage Doubling
The ICL7660 may be employed to achieve positive voltage doubling using the circuit shown in Figure 11. In this
application, the pump inverter switches of the ICL7660 are
used to charge Cl to a voltage level of V+ -VF (where V+
is the supply voltage and VF is the forward voltage drop of
diode 01). On the transfer cycle, the voltage on Cl plus the
supply voltage (V +) is applied through diode 02 to capacitor C2. The voltage thus created on C2 becomes
(2V+)-(2VF) or twice the supply voltage minus the combined forward voltage drops of diodes 01 and D2.
The source impedance of the output (VOUT) will depend
on the output current, but for V + = 5 volts and an output
current of 10mA it will be approximately 60 ohms.
v+

CMOS

GATE

Figure 9: External Clocking

VOUT

0319-23

It is also possible to increase the conversion efficiency of
the ICL7660 at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 10. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (Cl) and reservoir (C2) capacitors; this is overcome
by increasing the values of Cl and C2 by the same factor
that the frequency has been reduced. For example, the addition of a 1OOpF capaCitor between pin 7 (Osc) and V + will
lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate
a corresponding increase in the value of Cl and C2 (from
lO,..F to 100,..F).

NOTE:
D, & D:! CAN BE ANY
SUITABLE DIODE

0319-25

Figure 11: Positive Voltage Doubler

NOTE: All typical values have been characterized but are not tested.

2-103

<:J

:z
ii5

fflcn

o!::
0::::>

a:o
a.. a:
a:C3
w

3:
o
a..

ICL7660
Combined Negative Voltage Conversion
and Positive Supply Doubling
Figure 12 combines the functions shown in Figures 5 and
11 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for
example, suitable for generating +9 volts and -5 volts
from an existing + 5 volt supply. In this instance capacitors
C1 and Ca perform the pump and reservoir functions respectively for the generation of the negative voltage, while
capacitors C2 and C4 are pump and reservoir respectively
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will
be somewhat higher due to the finite impedance of the
common charge pump driver at pin 2 of the device.

Regulated Negative Voltage Supply
In some cases, the output impedance of the ICL7660 can
be a problem, particularly if the load current varies substantially. The circuit of Figure 14 can be used to overcome this
by controlling the input voltage, via an ICL7611 low-power
CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since
the ICL7660's output does not respond instantaneously to
change in input, but only after the switching delay. The' circuit shown supplies enough delay to accommodate the
7660, while maintaining adequate feedback. An increase in
pump and storage capacitors is desirable, and the values
shown provides an output impedance of less than 50 to a
load of 10mA.
SOk

+BY
561<

SOk
lOOk

_ +
. Dz
Your = (2)r)L..._ _ _ _......::..j~:.......--~...."__-':O (Yro ,)-(YF02)

1CL8069

c.

ID-_+YOIIT
0319-26

Figure 12: Combined Negative Voltage
Converter and Positive Doubler

BOOk

0319-31

Voltage Splitting

Figure 14: Regulating the Output Voltage

The bidirectional characteristics can also be used to split
a higher supply in half, as shown in Figure 13. The combined load will be evenly shared between the two sides.
Because the switches share the load in parallel, the output
impedance is much, lower thaI) .in' the standard circuits, and
higher currents can be drawn from the device. By using this
circuit, and then the circuit of Figure 8, + 15V can be converted (via +7.5, and -7.5) to a nominal -15V, although
with rather high series output resistance (- 250n).

.. 5\11 LOGIC.."..."

r-~---~-----------'-v+

RU

.....

•... r-I
n
I I-.JL..

-IV

R12
0319 C29
L-------~--

________________

~v-

Figure 15: RS232 Levels From
A Single 5V Supply

0319-27

Figure 13: Splitting A Supply in Half

OTHER APPLICATIONS
Further information on the operation and use of the
ICL7660 may be found in A051 "Principals and Applications
of the ICL7660 CMOS Voltage Converter".

NOTE: Aft typical values have been clumJ.cterlzed but 8f'9 not tssted.

ICL7660S

HARRIS
SEMICONDUCTOR

Super Voltage Converter

GENERAL DESCRIPTION

FEATURES

The ICL7660S Super Voltage Converter is a monolithic
CMOS voltage conversion IC that guarantees significant
performance advantages over other similar devices. It is a
direct replacement for the industry-standard ICL7660 offering an extended operating supply voltage range up to 12V,
with lower supply current. No external diode is needed for
the ICL7660S. In addition, a Frequency Boost pin has
been incorporated to enable the user to achieve lower output impedance despite using smaller capacitors. All improvements are highlighted in bold Italics in the Electrical
Characteristics section. Critical parameters are guaranteed over the entire commercial, industrial and military
temperature ranges.
The ICL7660S performs supply voltage conversion from
positive to negative for an input range of 1.5V to 12V, resulting in complementary output voltages of -1.5V to -12V.
Only 2 non-critical external capacitors are needed for the
charge pump and charge reservoir functions. The ICL7660S
can be connected to function as a voltage doubler and will
generate up to 22.8V with a 12V input. It can also be used
as a voltage multiplier or voltage divider.
The chip contains a series DC power supply regulator, RC
oscillator, voltage level translator, and four output power
MaS switches. The oscillator, when unloaded, oscillates at
a nominal frequency of 10kHz for an input supply voltage of
5.0 volts. This frequency can be lowered by the addition of
an external capacitor to the "OSC" terminal, or the oscillator may be over-driven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV) operation. At medium to high voltages (3.5V to 12V), the LV pin
is left floating to prevent device latchup.

• Guaranteed Lower Max Supply Current for All
Temperature Ranges
• Guaranteed Wider Operating Voltage Range
-1.5V to 12V
• No External Diode Over Full Temperature and
Voltage Range
• Boost Pin (Pin 1) for Higher Switching Frequency
• Guaranteed Minimum Power Efficiency of 96%
• Improved Minimum Open Circuit Voltage Conversion
Efficiency of 99%
• Improved SCR Latchup Protection
• Simple Conversion of + 5V Logic Supply to ± 5V
Supplies
• Simple Voltage Multiplication VOUT=(-)nV'N
• Easy to Use-Requires Only 2 External
Non-Critical Passive Components
o Improved Direct Replacement for Industry-Standard
ICL7660 and Other Second-Source Devices

APPLICATIONS
• Simple Conversion of + 5V to ± 5V Supplies
• Voltage Multiplication VOUT = ±nV'N
• Negative Supplies for Data Acquisition Systems &
Instrumentation
• RS232 Power Supplies
• Supply Splitter, VOUT = ±Vs/2

ORDERING INFORMATION
Part Number

Temp. Range

Package

ICL7660SCBA

O·Cto +70·C

8-PinSOIC
8-Pin Minidip

ICL7660SCPA

O·Cto +70·C

ICL7660SIBA

-25·Cto +85·C

ICL7660SCTV

O·Cto +70·C

ICL7660SIPA

-25·Cto +85·C

8-Pin Minidip

ICL7660SITV

- 25·C to + 85·C

TO-99

ICL7660SMTV*

-55·C to + 125·C

TO-99

8-PinSOIC
TO-99

'Add IBB38 to part number if BB38 processing is required.

v+(and CASE)

0088-1

(BA)

0088-2

(TV)

0088-3

(PA)

Figure 1: Pin Configurations

HARRIS SEMICONDUCTOR'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE
CONDITION OF SALE. THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

302163-003

NOTE: All typical values have b66n characterized but are not tested.

2-105

ICL7660S
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ...•...•.................•....... 13.0V
LV and OSC Input Voltage
(Note 1) .......... -0.3Vto(V+ + 0.3V) forV+ <5.5V
. . . • . . . . . . . • (V+ - 5.5V) to (V + + 0.3V) for V+ > 5.5V
Currentinto LV (Note 1) •......... ~ .. 20 ,...A for V + > 3.5V
Output Short Duration (VSUPPLY ~5.5V) •...••. Continuous
Power Dissipation (Note 2)
ICL7660SCTV ....•....•.•....••...•....•.... 500 mW
ICL7660SCPA •.•..•....••.................. 300mW
ICL7660SCBA ...•....•..............•....•• 300 mW
ICL7660SITV ................•....•.....•... 500 mW
ICL7660SIPA ...•...•.•...............•..... 300 mW
ICL7660SIBA ....•.......................... 300 mW
ICL7660SMTV ....•..........•...•.•.•...•.. 500 mW
Operating Temperature Range
ICL7660SM ............•.•.......•• - 55°C to + 125°C
ICL7660S1 .....•.................... -25°C to +85°C
ICL7660SC ......•.....•............... 00Cto +70"C
Storage Temperature Range ....•.•.... - 65°C to + 150"C
Lead Temperature
(Soldering. 10 sec) •.....•..•..•...•..•..•...... 300"C

BOOST

NOTE: Stresses above those lisied under "Absolut9 Maximum Ratings"
may cause psmISJI9nt dsms[J9 to the device. TheS9 are stress relings only

and functional optNBtion of the deviCe at these or any other conditions
above those indicated in the operational sections of the specifications is not
Implied. Exposure to absolute maximum rating conditions for extended per;.
ods may affect device rs/iabllity.

r--------.--------~--~-------------o~
r_--------oCAp·
. . . - - - - - ( ) CAP-

0088-4

Figure 2: Functional Diagram

NOTE: AN typical values havebtHm cluuactsrlzsdbulars not /osted.

2-106

ICL7660S
ELECTRICAL CHARACTERISTICS
V+

= 5V, TA = 25'C,OSC = Free running, Test Circuit Figure 3 (unless otherwise specified)

Symbol

Parameter

Limits

Test Conditions
Min

/+

Units

Typ

Max

80

160
180
180
200

/LA

Supply Current
(Note 3)

RL = co, 25'C
O'C < TA < +70'C
-25'C < TA < +85'C
-55'C < TA < +125'C

V~

Supply Voltage Range-Hi
(Note 4)

RL = 10K, LV Open
Tmin

...

86

0:

3

84

10

IIII II

8
7
6
5
4
3
2

r\

III

0

lk

10k

50k

20

0

18

~
>u

16

~

v+=5v_l_
TA=25OC

VI

...:::>
...a
...
0:

..J

U

1\

14 1\
12

0:

3

'\

U

80
100

'N'
:I:

z

..J

82

UNLOADED OSCILLATOR
FREQUENCY
AS A FUNCTION OF TEMPERATURE

10

\

"

....,J- V+ = 1OV

~

""'I'-..,

8

I,-V+=5V

/1-----

I--l-- r--- ----

-

III

0

0

1

10

100

lK

-50 -25

0

25

50

75 100 125

TEMPERATURE (OC)

osc FREOUENCY FOSC (Hz)
0088-9

0088-8

NOTE: AU typical values have bsen charactBrfz8d but arB not tested.

2-108

0088-10

ICL7660S
TYPICAL PERFORMANCE CHARACTERISTICS

(Circuit of Figure 3) (Continued)

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT
2

~

">!''-''"
0

...>
::>

I!:
::>
0

r-....

0

/

",.......
~

-1

V

~

-2
-3

-4
-5

,,/'"
o

/'

.......

/

1/
Y+=5V

V

,!,,-5
TA=25"O

V

/

1
10

10

20

T.=25"C -

30

40

20

30

40

50

100
90
80
70
60
50
40
30
20
10

Y+=2Y
T. =25"0

£...
~'"
g
...::>

~

I"
u

I!:
::>

~

0

"'"

0

-2

o

./

-1

60

4

i--'

5

6

7

8

9

LOAD CURRENT(mA)

LOAD CURRENT(m.)-

LOAD CURRENT (mA) -

--

i--' i--'
o 123

J

0088-13

0088-12

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT
90

...........

60

-

so

1
"'-\...

40
30
20
10

o/
o

.....

~

Y+-2Y
D<...
T.=25"O /
.........

S

16.0
14.0
12.0
10.0

/

4.0

4.5

6

200

::>
0

o
3

~

0:

2.0
1.5

300

.....5

6.0

400

£tl
z

~

8.0

/

05
a: 0
a.. a:
a:C3
w

OUTPUT SOURCE RESISTANCE
AS A FUNCTION OF
O.SCILLATOR FREQUENCY

=5Y
~~I=~ll~J
T. =25"C
\ 1=1 10mA
c!llIM.=W.

1\

1\

100

o C,=C,=I06;r
100

7.5

~
a..

Jl

y+

~

men

01-

0088-11

80
70

CJ

Z
(j)

IK

r-

\

-

10K

lOOK

OSCILLATOR FREQUENCY(Hz)

LOAD CURRENT(mA)

0088-15

0088-14

NOTE 6: These curves include in 1he supply current that current fed directly Into the load RL from V+ (see Figure 3). Thus apprOXimately half the supply current
goes directly 10 the positive slde aftha load, and the olherhalf, throughtthe ICL76aOS, to1f1e negative side of the load. Ideally. Vour::.: 2 VIN,IS::=:: 2 ILl
so YIN' IS ~ VOUT • IL'

NOTE: All typical values have been characterized but are not tested.

2-109

ICL7660S
IS V·

181-----_-+-0 (+5V)

0088-16

NOTE 1: For large values of CoSc (> 1000pF) Ihe values of C, and

0088-17

C2 should be increased 10 1OOI'F.

Figure 4: Idealized Negative Voltage Converter

Figure 3: ICL7660S Test Circuit

THEORETICAL POWER EFFICIENCY
CONSIDERATIONS

DETAILED DESCRIPTION
The ICL76608 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2
external capacitors which may be inexpensive IOIlF polarized electrolytic types. The mode of operation of the device
may be best understood by considering Figure 4, which
shows an idealized negative voltage converter. Capacitor
C1 is charged to a voltage, V+, for the half cycle when
switches 81 and 83 are closed. (Note: 8witches 82 and 84
are open during this half cycle.) During the second half cycle of operation, switches 82 and 84 are closed, with 81 and
8a open, thereby shifting capacitor C1 negatively by V +
volts. Charge is then transferred from C1 to C2 such that the
voltage on C2 is exactly V+, assuming ideal switches and
no load on C2. The ICL76608 approaches this ideal situation more closely than existing non-mechanical circuits.
In the ICL76608, the 4 switches of Figure 4 are M08
power switches; 81 is a P-channel device and 82, 83 & 84
are N-channel devices. The main difficulty with this approach is that in integrating the switches, the substrates of
83 & 84' must always remain reverse biased with respect to
their sources, but not so much as to degrade their "ON"
resistances. In addition, at circuit startup, and under output
short circuit conditions (VOUT=V+), the output voltage
must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power
losses' and probable device latchup.
This problem is eliminated in the ICL76608 by a logic network which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of 8a & 84
to the.correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL76608 is an integral part of the anti-Iatchup circuitry, however its inherent
voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation the "LV" pin should
be connected to GROUND, disabling the regulator. For supply voltages greater than 3.5 volts the LV terminal must be
left open to insure latchup proof operation, and prevent device damage.

In theory a voltage converter can approach 100% efficiency if certain conditions are met:
A
The drive circuitry consumes minimal power.
S
The output switches have extremely low ON resistance and virtually no offset.
C
The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The ICL76608 approaches these conditions for negative
voltage conversion if large values of C1 and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E=Y2C1 (V12-V22)
where V1 and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of C1 and C2 are
relatively high at the pump frequency (refer to Figure 4)
compared to the value of RL, there will be a substantial
difference in the voltages V1 and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly
large value for C1 in order to achieve maximum efficiency of
operation.

DO'S AND DON'TS
1. Do not exceed maximum supply voltages.
2. Do not connect LV terminal to GROUND for supply
voltages greater than 3.5 volts.
3. Do not short circuit the output to V+ supply for supply
voltages above 5.5 volts for. extended periods, however,
transient conditions including startup are okay.
4. When using polarized capacitors, the + terminal of Cl
must be connected to pin 2 of the ICL7660 and the
+ terminal of C2 must be connected to GROUND.
5. If the voltage supply driving the 7660S has a large
source impedance (25 ,... 30 ohms), then a 2.2,..F capacitor from pin 8 to ground may be required to limit rate of
rise of input voltage to less than 2W,..s.
6. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will
occur under these conditions.
A 1N914 or similar diode placed in parallel with C2 will
prevent the device from latching up under these
conditions. (Anode pin 5, Cathode pin 6).

NOTE: AU typical valuB8 have been characterized but are not tested.

2-110

ICL7660S

r

RO

YOUT

y+

+

I---.. . . .

OY OUT

=-y+

B:.l0~f

a

b

0088-18

Figure 5: Simple Negative Converter and its Output Equivalent
C!l

:z

en
en

w en
o!::
o~

0::0
<>'0::
0::0
W

:;:

o

<>.

0088-28

Figure 6: Output Ripple

0088-19

Figure 7: Paralleling Devices

NOT£.: All typical values have been characterized but are not tested.

2-111

ICL7660S

0088-20

'NOTE 1: VOUT =

-nV+

for 1.5V

,;; V+ ,;; 12V.

Figure 8: Cascading Devices for Increased Output Voltage
Since the ESRs of the capaCitors are reflected in the output impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(fpUMPXC1) term, rendering
an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capaCitors may have ESRs as
high as 10n.

TYPICAL APPLICATIONS
Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660S for generation of negative supply voltages. Figure
5 shows typical connections to provide a negative supply
where a positive supply of + 1.5V to + 12V is available.
Keep in mind that pin 6 (LV) is tied to the supply negative
(GND) for supply voltages below 3.5 volts.
The output characteristics of the circuit in Figure 5a can
be approximated by an ideal voltage source in series with a
resistance as shown in Figure 5b. The voltage source has a
value of - (V +). The output impedance (Ro) is a function of
the ON resistance of the internal MOS switches (shown in
Figure 4), the switching frequency, the value of C1 and C2,
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for Ro is:

Output Ripple
ESR also affects the ripple voltage seen at the output.
The total ripple is determined by 2 voltages, A and B, as
shown in Figure 6. Segment A is the voltage drop across
the ESR of C2 at the instant it goes from being charged by
C1 (current flowing into C2) to being discharged through the
load (current flowing out of C2). The magnitude of this current change is 2 X lOUT, hence the total drop is
2XIOUTxESRC2 volts. Segment B is the voltage change
across C2 during time t2, the half of the cycle when C2
supplies current to the load. The drop at B is lOUT X t2/C2
volts. The peak-to-peak ripple voltage is the sum of these
voltage drops:

Ro "" 2(RSW1 + RSW3 + ESRC1) + 2(RSW2 + RSW4 +
1
ESRc1) +
+ ESRC2
fpUMPXC1

Vripple ""

(fpUMP = fo;c, Rswx = MOSFET switch resistance)
Combining the four Rswx terms as Rsw, we see that:
1
Ro "" 2XRsw +
+ 4XESRC1 + ESRC2 n
fpUMpX C1
Rsw, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resistance graphs), typically 23n @ 25°C and 5V. Careful selection of C1 and C2 will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce
the 1/(fpUMPXC1) component, and low ESR capacitors will
lower the ESR term. Increasing the oscillator frequency will
reduce the 11 (fpUMP x C1) term, but may have the side effect of a net increase in output impedance when C1 >
10 /LF and there is no longer enough time to fully charge the
capaCitors every cycle. In a typical application where fosc
= 10 kHz and C=C1 =C2= 10 /LF:
Ro ""2X23+

LXfpU~PXC2 + 2XESRC2) X lOUT

Again, a low ESR capaCitor will result in a higher performance output.

Paralleling Devices
Any number of ICL7660S voltage converters may be'paralleled to reduce output resistance. The reservoir capaCitor,
C2, serves all devices while each device requires its own
pump capacitor, C1. The resultant output resistance would
be approximately:
ROUT

ROUT (of ICL7660S)
n (number of devices)

Cascading Devices
The ICL7660S may be cascaded as shown to produce
larger negative multiplication of the initial supply voltage.
However, due to the finite efficiency of each device, the
practical limit is 10 devices for light loads. The output voltage is defined by:

1
3
+4XESRCI + ESRC2
(5X10 X10X10- 6)
Ro "" 46 + 20 + 5xESRcn

NOTE: An typical values have been characterized but are not tested.

2-112

ICL7660S
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7660S ROUT
values.

Cosc

Changing the ICL7660S Oscillator
Frequency
It may be desirable in some applications, due to noise or
other considerations, to alter the oscillator frequency. This
can be achieved simply by one of several methods described below.
By connecting the Boost Pin (Pin 1) to V + , the oscillator
charge and discharge current is increased and, hence, the
oscillator frequency is increased by approximately 3%
times. The result is a decrease in the output impedance and
ripple. This is of major importance for surface-mount applications where capacitor size and cost are critical. Smaller
capacitors, e.g. 0.1 IJ-F, can be used in conjunction with the
Boost Pin in order to achieve similar output currents compared to the device free running with Cl = C2 = 10 IJ-F or
100 IJ-F. (Refer to graph of Output Source Resistance as a
Function of Oscillator Frequency).
Increasing the oscillator frequency can also be achieved
by overdriving the oscillator from an external clock, as
shown in Figure 9. In order to prevent device latch up, a
100 kn resistor must be used in series with the clock output. In a situation where the deSigner has generated the
external clock frequency using TTL logic, the addition of a
10 kn pullup resistor to V+ supply is required. Note that the
pump frequency with external clocking, as with internal
clocking, will be % of the clock frequency. Output transitions occur on the positive-going edge of the clock.

st--1,""""-oVOUT

0088-22

Figure 10: Lowering Oscillator Frequency

~

~

VOUT=
2V+- 2V r

Wen
O!:::

0::;)
0:0
D..O:

0:C3
W

~
D..
0088-23

NOTE: Dl & D2 can be any suitable diode.

Figure 11: Positive Voltage Doubler

Positive Voltage Doubling
The ICL7660S may be employed to achieve positive voltage doubling using the circuit shown in Figure 11. In this
application, the pump inverter switches of the ICL7660S are
used to charge Cl to a voltage level of V+ -VF (where V+
is the supply voltage and VF is the forward voltage drop of
diode 01). On the transfer cycle, the voltage on Cl plus the
supply voltage (V+) is applied through diode 02 to capacitor C2. The voltage thus created on C2 becomes
(2V+)-(2VF) or twice the supply voltage minus the combined forward voltage drops of diodes 01 and 02.
The source impedance of the output (VOUT) will depend
on the output current, but for V + = 5 volts and an output
current of 10mA it will be approximately 60 ohms.

CMOS
GATE

ISSiJ---.---OVOUT

0088-21

Figure 9: External Clocking

Combined Negative Voltage Conversion
and Positive Supply Doubling

It is also possible to increase the conversion efficiency of
the ICL7660S at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is shown
in Figure 10. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the
pump (Cl) and reservoir (C2) capacitors; this is overcome
by increasing the values of Cl and C2 by the same factor
that the frequency has been reduced. For example, the addition of a 1OOpF capacitor between pin 7 (Osc) and V+ will
lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate
a corresponding increase in the value of Cl and C2 (from
10IJ-F to 100IJ-F).

Figure 12 combines the functions shown in Figures 5 and
11 to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for
example, suitable for generating +9 volts and -5 volts
from an existing + 5 volt supply. In this instance capacitors
Cl and C3 perform the pump and reservoir functions respectively for the generation of the negative voltage, while
capacitors C2 and C4 are pump and reservoir respectively
for the doubled positive voltage. There is a penalty in this
configuration which combines both functions, however, in
that the source impedances of the generated supplies will
be somewhat higher due to the finite impedance of the
common charge pump driver at pin 2 of the device.

NOTE: All typical values havs been characterized but are not tested.

2-113

ICL7660S
Regulated Negative Voltage Supply
In some cases, the output impedance of the ICL7660S
can be a problem, particularly if the load current varies substantially. The circuit of Figure 14 can be used to overcome
this by controlling the input voltage, via an ICL7611 lowpower CMOS op amp, in such a way as to maintain a nearly
constant output voltage. Direct feedback is inadvisable,
since the ICL7660S's output does not respond instantaneously to change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the 7660S, while maintaining adequate feedback. An
increase in pump and storage capacitors is desirable, and
the values shown provides an output impedance of less
than 50 to a load of 10mA.

.-+--......-OVOUT = -Y,N
VOUy =2V+-

'--------1C"'2' - - - -.......-+.....--oVrD1 -VrD2

,:cC4
0088-24

Figure 12: Combined Negative Voltage
Converter and Positive Doubler

OTHER APPLICATIONS

Voltage Splitting

Further information on the operation and use of the
ICL7660S may be found in A051 "Principals and Applications of the ICL7660 CMOS Voltage Converter".

The bidirectional characteristics can also be used to split
a higher supply in half, as shown in Figure 13. The combined load will be evenly shared between the two sides, and
a high value resistor to the LV pin ensures start-up. Because the switches share the load in parallel, the output
impedance is much lower than in the standard circuits, and
higher currents can be drawn from the device. By using this
circuit, and then the circuit of Figure 8, + 15V can be converted (via +7.5, and -7.5) to a nominal -15V, although
with rather high series output resistance (- 2500).

+8V

~-v-

10l'F

lOOk

r-~--------~~----------~~

vOUT = - 2 -

SOk

56k
SOk

ICL8069

+
50~r

2S0k
VOLT~GE

ADJUST

L-~~~v-

0088-26

Figure 14: Regulating the Output Voltage

0088-25

Figure 13: Splitting A Supply in Half
+5V LOGIC SUPPLY

mOATA
INPUT
RS232 DATA
OUTPUT

IHSI42

13

14

+ 5V

n

- 5v l

n

L-...J L
0088-27

Figure 15: RS232 Levels From A Single 5V Supply

NOTE: All typical values hsvs been charscterized but are not tested.

2-114

ICL7662
CMOS Voltage Converter
GENERAL DESCRIPTION

FEATURES

The Harris ICL7662 is a monolithic high-voltage CMOS
power supply circuit which offers unique performance advantages over previously available devices. The ICL7662
performs supply voltage conversion from positive to negative for an input range of +4.5V to +20.0V, resulting in
complementary output voltages of -4.5V to -20V. Only 2
non-critical external capacitors are needed for the charge
pump and charge reservoir functions. The ICL7662 can also
function as a voltage doubler, and will generate output voltages up to + 38.6V with a + 20V input.
Contained on chip are a series DC power supply regulator, RC oscillator, voltage level translator, four output power
MOS switches. A unique logic element senses the most
negative voltage in the device and ensures that the output
N-channel switch source-substrate junctions are not forward biased. This assures latchup free operation.
The oscillator, when unloaded, oscillates at a nominal frequency of 10kHz for an input supply voltage of 15.0 volts.
This frequency can be lowered by the addition of an external capacitor to the "OSC" terminal, or the oscillator may
be overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV) operation. At medium to high voltages (+10 to +20V), the LV
pin is left floating to prevent device latchup.

• No External Diode Needed Over Entire Temperature
Range
• Pin Compatible With ICL7660
• Simple Conversion of + 15V Supply to -15V Supply
• Simple Voltage Multiplication (VOUT=(-) nVIN)
• 99.9% Typical Open Circuit Voltage Conversion
Efficiency
• 96% Typical Power Efficiency
• Wide Operating Voltage Range 4.5V to 20.0V
• Easy to Use - Requires Only 2 External Non·Crltlcal
Passive Components
CJ

APPLICATIONS
• On Board Negative Supply for Dynamic RAMs
• Localized ".·Processor (8080 Type) Negative
Supplies
• Inexpensive Negative Supplies
• Data Acquisition Systems
• Up to - 20V for Op Amps

ORDERING INFORMATION
Part Number

Temperature Range

Package

ICL7662CTV

00Cto+700 C

TO-99

ICL7662CPA

00Cto+700C

8 Pin Mini DIP

ICL7662CBD

00Cto+700C

ICL7662MTV*

-55 0 C to +1250 C

14PinSOlC
TO-99

"Add /8836 \0 Part Number for 8836 Processing.

8 LEAD PIN MINI DIP
TOP VIEW

14 LEAD PIN SOIC
TOP VIEW

TO-99 PACKAGE
TOP VIEW
V+

TEST
CAP+
GND
CAP'

V+
OSC
LV
VOUT

TEST
NC
CAP+
NC
GND
NC
CAP

Figure 1: Pin Configurations

HARRIS SEMICONDUCTOR'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE
CONDITION OF SALE. THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN UEU OF AU OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTOAY, INCLUDING THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
302064-005

NOTE: AN typical values havs been chsractBfizsd but am not tostsd.

2-115

:z
ii5

ffil!?
u_

0::>

a: u
... a:
a:u
w

...~

ICL7662
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................... 22V
Oscillator Input Voltage (Note 1) ....................... .
-0.3Vto (V+ +0.3V) forV+ <10V
(V+ -10V) to (V+ +0.3V) forV+ >10V
Current into LV (Note 1) ..•........... 20 p.A for V + > 1OV
Output Short Duration ...................... Continuous

Power Dissipation (Note 2)
ICL7662CTY ............................... 500mW
ICL7662CPA ............................... 300mW
ICL7662MTY ............................... 500mW
Lead Temperature (Soldering, 10sec) ............. 300'C

NOTE: Stresses above thosalisted under '"Absolute Maximum Ratings" mey cause permanent damege to the device. These are stress ratings only and functional

operation of the devies at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect devies reliability.

ELECTRICAL CHARACTERISTICS

v+ = 15V, TA= 25'C, COSC= 0, unless otherwise stated. Test Circuit

Figure 3.
Symbol

limits

Test Conditions

Parameter

Min
V+L
V+H

Supply Voltage Range-Lo
Supply Voltage Range-Hi

RL =10kn, LV=GND
RL =10kn, LV=Open

Min

51a:

IL

a:

LV=OPEN

0

S

5

100

H

4

10

3

10

2

100

Cosc(PFl

o 2 4 6 8 10 12 14 16 18 20
SUPPLY VOLTAGE (V)
0320-8

NOTE: All typical valuBs have been characterized but aro not tested.

2-117

1000

13
en
u!=

o=>

V+

/

V

0320-5

POWER CONVERSION EFFICIENCY
AND OUTPUT SOURCE RESISTANCE
AS A FUNCTION OF OSCILLATOR
FREQUENCY

100

ioI""Y+=5V_
IL=3mA-

/

U)

V+ VOLTS

/'1
/

(!J

:z

2 4 6 8 10 12 14 16 18 20

0320-4

OUTPUT SOURCE RESISTANCE AS
A FUNCTION OF TEMPERATURE

8

LV = OPEN

30

10K

0320-9

ICL7662
TYPICAL PERFORMANCE CHARACTERISTICS
UNLOADED OSCILLATOR FREQUENCY
AS A FUNCTION OF TEMPERATURE
15K
v+= 15V
14K
COse =0 pF
'N'

C.

\.
\.

13K
12K

11K

7K
6K
5K
-20

0

"

+25

-s

i =:-.
~

~

>

"

-tD

~ -11
8 -12

r-.....

+70

.....

.....

-13

...........

-1'
-1.

+125

1

= 15V 1--1-= +25"C 1-+LV = OPEN

v+
TA

fi! -4
~

8K

-55

I

-2
-3

~ -5

'"

9K

OUTPUT VOLTAGE AS A
FUNCTION OF LOAD CURRENT

-1

,

10K

(See Test Circuit of Figure 3) (Continued)

...

..... 1-'" SLOPE - 650

I I
LLlll

i"""'i""'"

TEMPERATURE (OC)

i-'"

LOAD CURRENT IL (rnA)

0320-10

0320-11

OUTPUT VOLTAGE AS A
FUNCTION OF LOAD CURRENT
2

V+=5~J:±-

g

TA=+25OC
LV=GND

~

l:;
z

0

...~
<0

~

-1

~

....:::>

-2

I!:
:::>

-3

...z~
...'">z

-4

c:

40
36

85

32
28, $3
24 ~
20 +
16 ~
12 ~

CII

80

8

75

~

70

...'"
...

SLOPE= 140A

8
4

0

o

2 4

6 8 10 12 14 16 18 20

LOAD CURRENT IL (mA)

II>

90

Q

0

-5

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT
100
V+=5VJ:±95
TA =+25"C

6S

o

:g
...
rg

~

2 4 6 8 10 12 14 16 18 20
LOAD CURRENT It(mA)

0320-12

0320-13

g
l:;

...z~

SUPPLY CURRENT & POWER
CONVERSION EFFICIENCY AS A
FUNCTION OF LOAD CURRENT
100
v+= 15V}
TA=+25OC
95

90

PBFF

85

Q

CII

'"
~

80

0

75

z

u

...'"
...
~

RL = CIO
TA =+25OC
Cosc=OpF

~
200
80·"<
.
1
+ 160 g
140 !8
120 ~
100 +
80 ~
60
40
20

;I!

70

o

lJU

11
10
9
8
7
6

!

0

6S

FREQUENCY OF OSCILLATION AS A
FUNCTION OF SUPPI:Y VOLTAGE

UU

LV=GND
LV = OPEN

5
4
3
2

10 20 30 40 50 60 70 80 90 100

o

2 4

6 8 10 12 14 16 18 20
SUPPLY VOLTAGE (V)

LOAD CURRENT IL (mA)

0320-15

0320-14

NOTE: AD typical vstues have been chstactsrizfId but arB not teslBd.

2-118

ICL7662
This problem is eliminated in the ICL7662 by a logic network which senses the output voltage (VOUT) together with
the level translators, and switches the substrates of S3 & S4
to the correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7662 is an integral
part of the anti-Iatchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore,
to improve low voltage operation the "LV" pin should be
connected to GROUND, disabling the regulator. For supply
voltages greater than 11 volts the LV terminal must be left
open to insure latchup proof operation, and prevent device
damage.

TYPICAL PERFORMANCE
CHARACTERISTICS(See Test Circuit of Figure 3) (Continued)
SUPPLY CURRENT AS A FUNCTION OF
OSCILLATOR FREQUENCY
150 r-:;:---mr-rTTlTIT11r--rrITTTm
140 y+ = 15Vtttt---++t-+tttIt-+-t-ttttill

1.
~

130 RL=oo

120 TA=+25"Ct-t-+ttHittt--+t-HtIH
110 1--Hrl+++III-H++I+ttt----l-+!-HIfHl

100 I-t+HttItl-+-l-ttltllt--++Hfttll
90t-++~mr~+H~t-t-+~~

801-t+HttItl-+-l-ttltllt--+~~
701--t-t+H+ttt---+-H+*ffi--r~~

LOAD CURRENT IL (rnA)

601-t+HttItl-+-l-ttltllt--J.I'H-I~

Is V+

501--t-t+H+ttt---+-H+*~~t-H~

(8j-------,.....;-01+5V

401-t+HttItl-+-l-+±l;lHf--++H~

C)

z

301---1I+1+H+1Hf'fTWHl-tttttffi

ii5
en

wt-++~mr~+H~t-t-+ttH~

wen

10L-LLUWlli--LLllllW~-UWllW

10

100

lK

10K

01-

,

*

OSCILLATOR FREQUENCY (Hz)

Gl

0320-16

~
rVOUT

Note that these curves include in the supply current that current fed directly
into the load RL from V+ (see Figure 3). Thus, approximately half the supply
current goes directly to the positive side of the load, and the other half,
through the ICL7662, to the negative side of the load. Ideally, VLOAO '"
2VIN, Is .. 2 Il' so VIN • Is '" VLOAD· Il

0320-17

NOTE: For large value of Cose (> 1000pi) the values of Cl and C2
should be increased to 100"F.

CIRCUIT DESCRIPTION
The ICL7662 contains all the necessary circuitry to complete a negative voltage converter, with the exception of 2
external capacitors which may be inexpensive 1OJ.LF polarized electrolytic capacitors. The mode of operation of the
device may be best understood by conSidering Figure 4,
which shows an idealized negative voltage converter. Capacitor C1 is charged to a voltage, V+, for the half cycle
when switches S1 and S3 are closed. (Note: Switches S2
and S4 are open during this half cycle.) During the second
half cycle of operation, switches S2 and S4 are closed, with
S1 and S3 open, thereby shifting capacitor C1 negatively by
V+ volts. Charge is then transferred from C1 to C2 such
that the voltage on C2 is exactly V+, assuming ideal
switches and no load on C2. The ICL7662 approaches this
ideal situation more closely than existing non-mechanical
circuits.
In the ICL7662, the 4 switches of Figure 4 are MaS power switches; S1 is a P-channel device and S2, S3 & S4 are
N-channel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of S3 & S4
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON" resistances. In addition, at circuit startup, and under output short
circuit conditions (VOUT=V+), the output voltage must be
sensed and the substrate bias adjusted accordingly. Failure
to accomplish this would result in high power losses and
probable device latchup.

Figure 3: ICL7662 Test Circuit

0320-18

Figure 4: Idealized Negative Converter

NOTE: All typical values have been characterized but aro not tssted.

2-119

0::0
0.0::

o::u
W

·Cose;

NOTE 4.

oS

~

ICL7662
TYPICAL APPLICATIONS
Simple Negative Voltage Converter

THEORETICAL POWER EFFICIENCY
CONSIDERATIONS
In theory a voltage multiplier can approach 100% efficiency if certain conditions are met:
A
The drive circuitry consumes minimal power
B
The output switches have extremely low ON resistance and virtually no offset.
C
The impedances of the pump and reservoir capacitors are negligible at the pump frequency.
The ICL7662 approaches these conditions for negative
voltage multiplication if large values of Cl and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
VOLTAGE OCCURS. The energy lost is defined by:
E=1jzCl (V12-V22)
where VI and V2 are the voltages on C1 during the pump
and transfer cycles. If the impedances of Cl and C2 are
relatively high at the pump frequency (refer to Figure 4)
compared to the value of RL, there will be a substantial
difference in the voltages VI and V2. Therefore it is not only
desirable to make C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly
large value for Cl in order to achieve maximum efficiency of
operation.

The majority of applications will undoubtedly utilize the
ICL7662 for generation of negative supply voltages. Figure
5 shows typical connections to provide a negative supply
where a positive supply of +4.5V to 20.0V is available.
Keep in mind that pin 6 (LV) is tied to the supply negative
(GND) for supply voltages below 11 volts.
The output characteristics of the circuit in Figure 5a can
be approximated by an ideal voltage source in series with a
resistance as shown in Figure 5b. The voltage source has a
value of - (V +). The output impedance (Ro) is a-function of
the ON resistance of the internal MOS switches (shown in
Figure 4), the switching frequency, the value of C1 and C2,
and the ESR (equivalent series resistance) of C1 and C2. A
good first order approximation for Ro is:
Ro '" 2(RSWI + RSW3 + ESRC1)
1
+ 2(RSW2 + RSW4 + ESRC1) + f
C + ESRC2
PUMpX 1
(fpUMP = fo: c , Rswx = MOSFET switch resistance)
Combining the four Rswx terms as Rsw, we see that:
1
Ro'" 2XRsw + f
C + 4XESRCI + ESRc2 fi
PUMpX 1
Rsw, the total switch resistance, is a function of supply
voltage and temperature (See the Output Source Resistance graphs), typically 240. @ 25°C and 15V, and 530. @
25°C and 5V. Careful selection of C1 and C2 will reduce the
remaining terms, minimizing the output impedance. High
value capaCitors will reduce the 1/(fpUMP x C1) component, and low ESR capacitors will lower the ESR term. Increasing the oscillator frequency will reduce the 1/(fpUMP x
C1) term, but may have the side effect of a net increase in
output impedance when C1 > 10 p.F and there is no longer
enough time to fully charge the capaCitors every cycle. In a
typical application where fosc = 10kHz and C = C1 = C2
= 10 p.F:

DO'S AND DON'TS
1. Do not exceed maximum supply voltages.
2. Do npt connect LV terminal to GROUND for supply
voltages greater than " volts.
3. When using polarized capaCitors, the + terminal of C,
must be connected to pin 2 of the ICL7662 and the
+ terminal of C2 must be connected to GROUND.
4. If the voltage supply driving the 7662 has a large source
impedance (25 - 30 ohms), then a 2.21lF capacHor from
pin 8 to ground may be required to limit rate of rise of
input voltage to less than 2V1lls.
5. User should insure that the output (pin 5) does not go
more positive than GND (pin 3). Device latch up will
occur under these conditions.
A 1N914 or similar diode placed in parallel with C2 will
prevent the - device from latching up under these
conditions. (Anode pin 5, Cathode pin 6).

Ro"'2X23+

L..--..-oVOUT

1
3
6 +4XESRCI + ESRC2
(5X10 X10X10- )
Ro '" 46 + 20 + 5 x ESRcfi

=-or

~10pr

a

b

Figure 5: Simple Negative Converter and Its Output Equivalent

NOTE: All typical va/uos have bsen characterized but Il/'8 not testtHI.

2-120

0320-19

ICL7662
Again, a low ESR capacitor will result in a higher performance output.

Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of 5, a high value could
potentially swamp out a low 1/(fpUMP X C1) term, rendering an increase in switching frequency or filter capacitance
ineffective. Typical electrolytic capacitors may have ESRs
as high as 10n.

Paralleling Devices
Any number of ICL7662 voltage converters may be paralleled to reduce output resistance. The reservoir capacitor,
C2, serves all devices while each device requires its own
purnp capacitor, C1. The resultant output resistance would
be approximately
ROUT (of ICL7662)
ROUT n (number of devices)

Output Ripple
ESR also affects the ripple voltage seen at the output.
The total ripple is determined by 2 voltages, A and B, as
shown in Figure 6. Segment A is the voltage drop across
the ESR of C2 at the instant it goes from being charged by
C1 (current flowing into C2) to being discharged through the
load (current flowing out of C2). The magnitude of this current change is 2 X lOUT, hence the total drop is 2 X lOUT
X ESRc2 volts. Segment B is the voltage change across
C2 during time t2, the half of the cycle when C2 supplies
current to the load. The drop at B is lOUT X t2/C2 volts.
The peak-to-peak ripple voltage is the sum of these voltage
drops:
Vripple '" (

f 1
C
2 X PUMP X 2

+2

Cascading Devices
The ICL7662 may be cascaded as shown to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical
limit is 10 devices for light loads. The output voltage is defined by:
VOUT= -n (VIN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL7662 ROUT
values.

X ESRC2) X lOUT

0320-28

Figure 6: Output Ripple

NOTE: All typical values haV6 been charactBrized but are not tested.

2-121

CJ

:z

m
wen

01-

oS
a:o
c..a:
a:o
w

~

ICL7662

0320-20

Figure 7: Paralleling Devices
V+

.......--<>

~----

Your

0320-21

Figure 8: Cascading Devices for Increased Output Voltage
v+

It is also possible to increase the conversion efficiency of
the ICL7662 at low load levels by lowering the oscillator
frequency. This reduces the switching losses, and is
achieved by connecting an additional capacitor, Case, as
shown in Figure 10. However, lowering the oscillator frequency will cause an undesirable increase in the impedance
of the pump (C1) and reservoir (C2) capacitors; this is overcome by increasing the values of C1 and C2 by the same
factor that the frequency has been reduced. For example,
the addition of a 100pF capacitor between pin 7 (Osc) and
V + will lower the oscillator frequency to 1kHz from its nominal frequency of 10kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C1 and
C2 (from 10",F to 100",F).

v+
1K

CMOS
GATE

i------------

'0""

uP

'0'

1.6
1.4

I

I

0.&

.YT I--'
k::;;'-

!
::i

Ie

W

U

~

SD

1111111111

~ ~

VIN =+9.0V
AVIN =2V

TA-+25~

lS

~

.5>

40

30
20

"...

3D

1

A=+7~

2.S
2D
1.5

lk

5 10 15 20 2S 30 35 40 4S 50

-

~
~

-

5.00
4.75
'.50
4.25
'.00
3.75
.5> 3.50

~

"- .....
I'

01::
o =>

'"

3.25
3.00
2.75

ceo
c.. ce
ceu
w

~

c..

V+=+15V

......
......

r-..

V+=+9V

~

.......(

.....

....

V+=+2V 1""' ....

2.50
0

2

•

FREQUENCY (Hz)

6

8

10 12 "

16

-20

V:. (V)

0

20

40

6Q

80

TEMPERATURE (~)

0092-5

DETAILED DESCRIPTION
The ICL7663S is a CMOS integrated circuit incorporating all
the functions of a voltage regulator plus protection Circuitry
on a single monolithic chip. Referring to the functional diagram (Figure 2), the main blocks are a bandgap-type voltage reference, an error amplifier, and an output driver with
both PMOS and NPN pass transistors.
The bandgap output voltage, trimmed to 1.29V ± 15 mV for
the ICL7663SA, and the input voltage at the VSET terminal
are compared in amplifier A. Error amplifier A drives a Pchannel pass transistor which is sufficient for low (under
about 5 rnA) currents. The high current output is passed by
an NPN bipolar transistor connected as a _follower. This
configuration gives more gain and lower output impedance.
Logic-controlled shutdown is implemented via aN-channel
MOS transistor. Current-sensing is achieved with comparator C, which functions with the VOUT2 terminal. The
ICL7663S has an output (VTcl from a buffer amplifier (8),
which can be used in combination with amplifier A to generate programmable-temperature-coefficient output voltages.
The amplifier, reference and comparator circuitry all operate
at bias levels well below 1 /LA to achieve extremely low
quiescent current. This does limit the dynamic response of

the circuits, however, and transients are best dealt with outside the regulator loop.

BASIC OPERATION
The ICL7663S is designed to regulate battery voltages in
the 5V to 15V region at maximum load currents of about
5 rnA to 30 rnA. Although intended as low power devices,
power dissipation limits must be observed. For example, the .
power dissipation in the case of a 10V supply regulated
down to 2V with a load current of 30 rnA clearly exceeds the
power dissipation rating of the Minidip:
(10 - 2) (30) (10- 3) = 240 mW
The circuit of Figure 4 illustrates proper use of the device.
CMOS devices generally require two precautions: every input pin must go somewhere, and' maximum values of applied voltages and current limits must be rigorously observed. Neglecting these precautions may lead to, at the
least, incorrect or nonoperation, and at worst, destructive
device failure. To avoid the problem of latchup, do not apply
inputs to any pins before supply voltage is applied.

NOTE: AU Iypicsl values have been characterized but are not tested.

2-127

z

en
wen

I
I
I

I'

CJ

iii

(mA)

Quiescent Current
as a Function
of Temperature

0
102

I

o

IoU12

o.s
'0'

1/

V,~=15V'

o
20

lD

lrP

V1;=9V

(mA)

TA=-2~

4D

... 1-

0.&

0.2

I

4S

V,~=2V

lD

DB

Quiescent Current
as a Function
of Input Voltage

11111111

TA=+25~

1.&
1.4
12

0.4

I I

louT1

so

10
0
10-2 '0""

~

V,~= 15V

02. 6 8 W

Input Power Supply
Rejection Ratio

ro

I

"'r..,....r'1

o ~tI"

100
~

§
~

Y,N =9V

0.&

0.2

102

E

I

loUT (mA)

90

I
I

lD

I

1.&

TA=+25~

V:'=2V

1.2

2D

I

I

0.4

USS ~IHIII~~+W~~~H!III
4.9SO , 0"'3 10-2

I

1.&

VOUT2 Input-Output
Differential vs
Output Current

ICL7663S
Y~

SENSE
YOUT2

204

Ret.

: 0.047 pF
YIN _

Youn I-604k4
ICl7663S YTC
I--

R2

YSEr

210k4

L-....._ _l"'M4~OI.4Y 
<
>
<

1.3V,
1.3V,
1.3V,
1.3V,

oun
oun
OUT2
OUT2

switch
switch
switch
switch

ON
OFF
OFF
ON

HYSn
HYSn
HYST2
HYST2

switch
switch
switch
switch

ON
OFF
ON
OFF

·See Operating Characteristics for exact thresholds.

Figure 2: Functional Diagram

NOTE: All typical values have been characterized but are not tested.

2-133

0090-4

....

05
0::0

c..

~
c..
±5

ROUT, RHYST = 1 MOo

ICL7665SA

SEll

0

V

w

ICL7665SA

NOTE 1: Derate above

0.2
0.15
0.11

V
V
V

G

VSET Input Leakage Current

Output/Hysteresis Difference

Units
Max

-0.15 -0.30
-0.05 -0.15
-0.02 -0.10

ISET

VSET1-VSET2 Difference in Trip Voltages

Typ

ICL7665S

04.7k,o

rf~~:;~:::;=1~::t=::=J---,~-------------oO~1
t----r--~----------~Hml
O1----~----r---;_--_+--_4~----~oun

HPUT

I.GY -

I.OV

Lt--====-.JID+--.....---+----iI---+---+--.....

n

.----1

-oHYST2

L..

0090-5

Figure 3: Test Circuits

..--------,--------1.6V

.....---------------·1.0V
O~I

tSOld

1F------__I---......;~·F-'---GNo

HYST1

isH'.

LJ..----+-~t::_;_----y+ (5V)
____ e. GND

OUT2

Iso,.

u=--=-~:H:;±:--------y+ (5V)

F....;;.;.--------·

GNO

..LJr-;----:::l:ii=-.::::------ y+ (5V)

HYST2

IF--------------· GNO

0090-6

Figure 4: Switching Waveforms

A.C. ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Limits

Test Conditions
Min

tS01d
tSH1d
tS02d
tSH2d
tS01d
tSH1d
ts02d
tSH2d
t01r
t02r
tH1r
tH2r
t01f
to2f
tH1f
tH2f

Output Delay Times
Input GOing HI

Input Going LO

-~-

Output Rise Times

Output Fall Times

Typ

Units
Max

VSET Switched between 1.0V to 1.SV
ROUT = 4.7 kO, CL = 12 pF
RHYST = 20 kO, CL = 12 pF

85
90
55
55

jJ.s

VSET Switched between 1.SV to 1.0V
ROUT = 4.7 kO, CL = 12 pF
RHYST = 20 kO, CL = 12 pF

75
80
60
SO

p.s

VSET Switched between 1.0V to 1.SV
ROUT = 4.7 kO, CL = 12 pF
RHYST = 20 kO, CL = 12 pF

0.6
0.8
7.5
0.7

p.s

VSET Switched between 1.0V to 1.SV
ROUT = 4.7 kO, CL = 12 pF
RHYST = 20 kO, CL = 12 pF

O.S
0.7
4
1.8

p's

NOTE: All typicsJ values have been characterlzed but are not tssted.

2-134

ICL7665S
Typical Performance Characteristics
OUT1 Saturation Voltage as a
Function of Output Current

-20

20r----.----,-----,----,
V+

HYST1 Output Saturation Voltage
vs HYST1 Output Current

OUT2 Saturation Voltage as a
Function of Output Current

-16

-12

-8

-4

=2V
en

~

~:I:

VI

=I

-0.8

0"",

z-

<0
0<::

~~

-12

:=;l""'

:3
5

10

15

20

5

10u~UT1 (mA)

10

15

0090-9

-20

oS

Supply Current as a
Function of Ambient
Temperature

-1.0

5.0

j

r-

3.5

t:::: ~115Y

~
a..
a..

::>

'"

1
,I

1

1

5.0

I--

1

1

j
>-

.1

~~
y+ =2Y

25
20

y+

1

=9V

r-

Ci

::>

25

""""

u
~
a..
a..

::>

1.5

'"

1.0
0.5

0090-10

-25

OV

=
tF-- TA =+25"C

20

TA

1.5

+40

+60

AMBIENT TEMPERATURE (Oe)

rb--"

I-- ~

=+70oe

I I

1.0

I I

0.5

o

+20

w

L

o
0

:s YSETl ' YSET2 :s y+

4.5 -II
4.0
3.5 - - -- TA -20oe
3.0

o

HYST2 OUTPUT CURRENT (mA)

0::0
0..0::
0::0

Supply Current as a
Function of Supply Voltage

:s VSETl ' VSET2 :s v+

4.5
4.0

>Ci 3.0

""""
::>
u

OV

I I
8

10

12

14

16

SUPPLY YOLTAGE (y+)
0090-12

0090-11

DETAILED DESCRIPTION

PRECAUTIONS

As shown in the Functional Diagram, Figure 2, the
ICL7665S consists of two comparators which compare input voltages on the SET1 and SET2 terminals to an internal
1.3V band-gap reference. The outputs from the two comparators drive open-drain N-channel transistors for OUT1
and OUT2, and open-drain P-channel transistors for HYST1
and HYST2 outputs. Each section, the Under-Voltage De, tector and the Over-Voltage Detector, is independent of the
other, although both use the internal 1.3V reference. The
offset voltages of the two comparators will normally be unequal so VSET1 will generally not quite equal VSET2.
The input impedances of the SET1 and SET2 pins are
extremely high, and for most practical applications can be
ignored. The four outputs are open-drain MaS transistors,
and when ON behave as low resistance switches to their
respective supply rails. This minimizes errors in setting-up
the hysteresis, and maximizes the output flexibility. The operating currents of the bandgap reference and the comparators are around 100 nA each.

Junction-isolated CMOS devices like the ICL7665S have
an inherent SCR or 4-layer PNPN structure distributed
throughout the die. Under certain circumstances, this can
be triggered into a potentially destructive high-current
mode. This latchup can be triggered by forward-biasing an
input or output with respect to the power supply, or by applying excessive supply voltages. In very-low current analog
circuits, such as the ICL7665S, this SCR can also be triggered by applying the input power supply extremely rapidly
("instantaneously"), e.g. through a low impedance battery
and an ON/OFF switch with short lead lengths. The rate-ofrise of the supply voltage can exceed 100 V / I's in such a
circuit. A low-impedance capaCitor (e.g., 0.05 I'F disc ceramic) between the V+ and GrouND pins of the ICL7665S
can be used to reduce the rate-ol-rise of the supply voltage
in battery applications. In line-operated systems, the rate-ofrise of the supply is limited by other conSiderations, and is
normally not a problem.

NOTE: All typical values have been characterized but are not tested.

2-135

:z
u;
en
wen
01-

0090-8

HYST2 Output Saturation Voltage
vs HYST2 Output Current
-3.0

CI

HYSTI OUTPUT CURRENT (mA)

lou~UT2 (rnA)
0090-7

-5.0 -4.0

20

~

0..

ICL7665S
If the SET voltages must be applied before the supply
voltage V+, the input current should be limited to less than
0.5 mA by appropriate external resistors, usually required
for voltage setting anyway. A similar precaution should be
taken with the outputs if it is likely that they will be driven by
other circuits to levels outside the supplies at any time. See
MOll for some other protection ideas.

Either detector may be used alone, as well as both together, in any of the circuits shown here.
When VIN is very close to one of the trip voltages, normal
variations and noise may cause it to wander back and forth
across this level, leading to erratic output ON and OFF conditions. The addition of hysteresis, making the trip pOints
slightly different for rising and falling inputs, will avoid this
condition.

SIMPLE THRESHOLD DETECTOR

THRESHOLD DETECTOR WITH
HYSTERESIS

Figure 5 shows the simplest connection of the ICL7665S
for threshold detection. From the graph (b), it can be seen
that at low input voltages OUTl is OFF, or high, while OUT2
is ON, or low. As the input rises (e.g., at power-on) toward
VNOM (usually the eventual operating voltage), OUT2 goes
high on reaching VTR2. If the voltage rises above VNOM as
much as VTR1, OUT1 goes low. The equations giving VSET1
and VSET2 are from Figure 5(a):

Figure 6(a) shows how to set up such hysteresis, while
Figure 6(b) shows how the hysteresis around each trip pOint
produces switching action at different points depending on
whether VIN is rising or falling (the arrows indicate direction
of change). The HYST outputs are basically switches which
short out R3l or R32 when VIN is above the respective trip
point. Thus if the input voltage rises from a low value, the
trip point will be controlled by Rln, R2n, and R3n, until the
trip point is reached. As this value is passed, the detector
changes state, R3n is shorted out, and the trip pOint becomes controlled by only Rln and R2n, a lower value. The
input will then have to fall to this new point to restore the

Rll
R12
VSETl = VIN (Rll + R2l); VSET2 = VIN (R12 + R22)

Since the voltage to trip each comparator is nominally
1.3V, the value VIN for each trip point can be found from
V
- V
(Rll +R2l) - 13 (Rll +R2l) for detector 1
TRl SETl
Rll
-.
Rl1

and
VTR2 = VSET2 (R12+ R 22) = 1.3 (R12+ R 22l for detector 2
R12
R12
Your

YIN

J

i

I

Rp2

R21

Y·
OUTI

OUT2

t

OFF
Rpl
R22

J,~~

ICL7665S
SETI
R"

V~

SET2
R'2

I

.J:-

0090-13

(a) Circuit Configuration

ON

.."

I---

YTR2
DETECTOR 2

YNOM

-1---

YTR1
DETECTOR 1

J

---I
0090-14

(b) Transfer Characteristics
Figure 5: Simple Threshold Detector

NOTE: All typical vs/uss have been chsracteriz6d but am not tsstBd.

2-136

ICL7665S
APPLICATIONS
OUT

1
I
I
I

~

T

Rll

R"

I
I
I
I

R32 I

V·
I - - HYSTI

I

HYST2 --<

ICL7665S
I - - SETI

SET2

OUTI

ON

I

R22

-

~
I
I
I
I

OUT2
GND

LTAGE RIO

R'2

1

UNDER-VOLTAGE
OFF '----i~----_+_-----__l V'N

I--- DillCTOR 2

0090-15

(a) Circuit Configuration

DillCTOR 1
VNOM

CI

0090-16

(b) Transfer Characteristics
Figure 6: Threshold Detector with Hysteresis

~
c..

a) NO HYSTERESIS

Over-Voltage VTRIP =

R11
R12 + R22
R12

X VSET1

R22
HYSTI
HYST2
ICL7665S
SETI
SEl2

X VSET2

b) HYSTERESIS PER FIGURE 6A
V

Rl2

R31

R'2

- R11 + R21 + R31
V
U1 R11
X SET1
0090-17

Over-Voltage VTRIP

Figure 7: An Alternative Hysteresis Circuit

R11 + R21
VL1 =
R
X VSET1
11
R12+R22+R32
V
U2 =
R
X VSET2
12
Under-Voltage VTRIP
VL2 =

R12 + R22
R
X VSET2
12

c) HYSTERESIS PER FIGURE 7
VU1 =

R11 + R21
R11

X VSET1

Over-Voltage VTRIP

Over-Voltage VTRIP

NOTE: AU typical values have been characterized but are not tested.

2-137

U)

01-

V'N

R11 + R21

iZ
w

05
a:o
c..a:
a:C3
w

Table 1: Set-Point Equations

Over-Voltage VTRIP =

:z

ICL7665S
ON and OFF conditions. The two outputs are connected in
a wired OR configuration with a pullup resistor to generate a
power OK signal.

THRESHOLD DETECTOR WITH
HYSTERESIS (Continued)
initial comparator state, but as soon as this occurs, the trip
pOint will be raised again.
An alternative circuit for obtaining hysteresis is shown in
Figure 7. In this configuration, the HYST pins put the extra
resistor in parallel with the upper setting resistor. The values
of the resistors differ, but the action is essentially the same.
The governing equations are given in Table 1. These ignore
the effects of the resistance of the HYST outputs, but these
can normally be neglected if the resistor values are above
about 100 kO.

Multiple Supply Fault Monitor
The ICL7665S can simultaneously monitor several supplies when connected as shown in Figure 9. The resistors
are chosen such that the sum of the currents through R21A,
R21B, and R3l is equal to the current through Rll when ~he
two input voltages are at the desired low voltage detection
point. The current through Rll at this point is equal to
1.3 V/R11. The voltage at the VSET input depends on the
voltage of both supplies being mon!tored. The trip voltage of
one supply while the other supply IS at the nominal ~oltage
will be different than the trip voltage when both supplies are
below their nominal voltages.
The other side of the ICL7665S can be used to detect the
absence of negative supplies. The trip points for OUT1 depend on both the negative supply voltages and the actual
voltage of the + 5V supply.

APPLICATIONS
Single Supply Fault Monitor
Figure 8 shows an over/under-voltage fault monitor for a
single supply. The over-voltage trip point is centered around
5.5V and the under-voltage trip point is centered around
4 5V Both have some hysteresis to prevent erratic output
+5V SUPPLY

1

I
V+

r---

324 kD.

HYST1

13Mn
5%
OPEN

HYST2

t---

249 kD.

7.5 MD.
5%

ICL7665S

VOLTALG-E~----1 VSETI

VSETZ .....- ......~-::U~NDER VOLTAGE
OUTl
OUT2
DETECTOR
100 kD. L-~r.;.;.---r-'" 100 kD.
Vu = 4.55W

DETECTOR
Vu = 5.55V

~

VL = 5.45V

IV+

-::~ VL = 4.45V

HiD.
L _ _ _~....._ _ _ _ _.... POWER
OK

0090-18

Figure 8: Fault Monitor for a Single Supply
+5V
v+
274kD.

HYST2

+5V

22MD.
R21

R21A

HYST1

ICL7665S
VSETZ

R21S

~

1.02MD.

-:~

+15V

49.9 kD.
RI1

-

100 kD.

22MD.

VSETI

y

OUT2

t---

OUT1

301 kD. ~
~
-5V

~ 787kD.
+5V
~

-15V

Figure 9: Multiple Supply Fault Monitor

NOTE: AU typical values have be9n charact6lized but are not tested.

2-138

1 MD.
POWER
OK

0090-19

ICL7665S
R31

R32

Y+
HYSTI

R21

HYST2

IM4
R22

ICL7665S

+

SEn

SET2

ICL7663S
SHUTDOWN
GND

R12
GND

-

-

SENSE
YSET

Y+
RII

1

+5Y
IA

1004

IM4

-

-

LOW BATTERY WARNING

LOW BATTERY SHUTDOWN

0090-20

Figure 10: Low Battery Warning and Low Battery Disconnect
above the trip point, OUT1 is low. When the DC input drops
below the trip pOint, OUT1 shuts OFF and the power fail
warning goes high. The voltage on the input of the 7805
decays at a rate of lOUT/C. Since the 7805 will continue to
provide 5V out at 1A until VIN is less than 7.3V, this circuit
will provide a certain amount of warning before the 5V output begins to drop.
The ICL7665S OUT2 is used to prevent a microprocessor
from writing spurious data to a CMOS battery backup memory by causing OUT2 to go low when the 7805 5V output
drops below the ICL7665S trip point.

Combination Low Battery Warning and Low
Battery Disconnect
When using rechargeable batteries in a system, it is important to keep the batteries from being overdischarged.
The circuit shown in Figure 10 provides a low battery warning and also disconnects the low battery from the rest of the
system to prevent damage to the battery. OUT1 is used to
shutdown the ICL7663S when the battery voltage drops to
the value where the load should be disconnected. As long
as VSETl is greater than 1.3V,
is low, but when VSET1
drops below 1.3V, OUT1 goes high, shutting off the
ICL7663S. OUT2 is used for low battery warning. When
VSET2 is greater than 1.3V, OUT2 is high and the low battery warning is on. When VSET2 drops below 1.3V, OUT2 is
low and the low battery warning goes off. The trip voltage
for low battery warning can be set higher than the trip voltage for shutdown to give advance low battery warning before the battery is disconnected.

oun

Simple High/Low Temperature Alarm
Figure 12 illustrates a simple high/low temperature alarm
which uses the ICL7665S with an NPN transistor. The voltage at the top of Rl is determined by the VBE of the transistor and the position of Rl'S wiper arm. This voltage has a
negative temperature coefficient. Rl is adjusted so that
VSET2 equals 1.3V when the NPN transistor's temperature
reaches the temperature selected for the high temperature
alarm. When this occurs, OUT2 goes low. R2 is adjusted

Power Fail Warning and Powerup/Powerdown
Reset
Figure 11 shows a power fail warning circuit with powerup/powerdown reset. When the unregulated DC input is

I

UNREGULATEO
DC INPUT

lJOF

.:l470o

I

7505
5Y
REGULATOR

I
I

~

5Y.IA
OUTPUT
470±

JOFI
BACKUP
BATTERY

I

5.86kll
715kJl

Y'
HYSTI

VSETI

130kll

~

HYST2 I--

ICL7665S
OUTI

22 Mil
2.2 Mil

VS£T2

OUT2

I

I Mil

-=I Mil

Figure 11: Power Fail Warning and
Powerup/Powerdown Reset

NOTE: All typical values haVB baM characterized but arB not tested.

2-139

r-1MII
RESET
OR
WRITE ENABLE
POWER
FAIL
WARNING

0090-21

CJ

:z

en
film
o!:::

0::::>

a: 0
c..a:
a:o
w

~
c..

ICL7665S
+

I
TEMPERATURE
SENSOR
(GENERAL
PURPOSE
NPN
TRANS ISTOR)

,,

,, ,- -,,

\

,,
,
~
,,
;,
,, ( ,
I

I

R3

\

'- -'

,,

HYST2

HYSTI

--

r--

LOW TEMPERATURE
22k.o.

R4

ICL7665S

R6 :

22 M.o.

R7

1.5M.o.

J~T ADJUST

R5
VSE12

J
Rl

I

\

470k.o.

1

5V

v+

r--

:1111111 -

L- -

27k.o.

VSET1
lM.o.

oun

OUT2

V+
10k.o.
HIGH
TEMPERATURE
LIMIT
ADJUSTMENT

-=-

ALARM SIGNAL
FOR DRlYING
LEOS, BELLS, ETC.

lM.o.

0090-22

Figure 12: Simple High/Low Temperature Alarm
charge C, once every cycle, approximately every 16.7 ms.
When the AC input voltage is reduced, OUT1 will stay OFF,
so that Cl does not discharge. When the voltage on C,
reaches 1.3V, OUT2 turns OFF and the power fail warning
goes high. The time constant, R,Cl, is chosen such that it
takes longer than 16.7 ms to charge C, 1.3V.

so that VSETI equals 1.3V when the NPN transistor's temperature reaches the temperature selected for the low temperature alarm. When the temperature'drops below this limit, OUT1 goes low.

AC Power Fall and Brownout Detector
Figure 13 shows a circuit that detects AC undervoltage by
monitoring the secondary side of the transformer. The capacitor, C" is charged through R, when OUT1 is OFF. With
a normal 110 VAC input to the transformer, OUT1 will dis-

750S
5V
REGULATOR

....J

~

11£111
6U r1 -- ........

.... 20V

~

CENTERED
TAPPED
TRANS.

.L

4700

.",I..-

IpF

-

--

5V,1A

i--

I +5V
601 k.o.

HYST1

•I

ICL7665S

I

10Ok.o.
-:~

-

f

HYST2

VSET1
VSE12
1 MD.

OUTI
1

I
I

IM.o.

OUT2
I

-.

Rl
I
I
I
I

r+I
I
I
I

It.t4

.L

POWER
FAIL
WARNING

0090-23

Figure 13: AC Power Fail and Brownout Detector

NOTE: AU Iypicsl vs/ut:Is hIlWI beBn characl6riZ«l but IU6 not testtJd.

2-140

ICI.7667

mHARRIS

Dual Power
MOSFET Driver

August 1991

Features

Description

• Fast Rise and Fall Times
.. 30ns with 1000pF Load

The ICL7667 is a dual monolithic high-speed driver
designed to convert TTL level signals into high current
outputs at voltages up to 15V. Its high speed and current
output enable it to drive large capacitive loads with high
slew rates and low propagation delays. With an output
voltage swing only millivolts less than the supply voltage
and a maximum supply voltage of 15V, the ICL7667 is well
suited for driving power MOSFETs in high frequency
switched-mode power converters. The ICL7667's high
current outputs minimize power losses Inthe power
MOSFETs by rapidly charging and discharging the gate
capacitance. The ICL7667's input are TTL compatible and
can be directly driven by common pulse-width modulation
control ICs.

• Wide Supply Voltage Range
.. VCC 4.5 to 15V

=

• Low Power Consumption
.. 4mW with Inputs Low
.. 20mW with Inputs High
• TTL/CMOS Input Compatible Power Driver
.. ROUT = 70, Typ
• Direct Interface with Common PWM Control ICs
• Pin Equivalent to 050026/050056; TSC426

Cl

:z

~

~~

05
teo
te

0..

teo
w
~

0..

Typical Applications
• Switching Power Supplies
• DC/DC Converters
• Motor Controllers

Packages

Order Information
TO-99 CAN (TV)
TOP VIEW
V+

PART
NUMBER

TEMPERATURE
RANGE

ICL7667CBA

OoCto +70 0 C

8PinSOlC

ICL7667CPA

OOCto+70 0 C

8 Pin Plastic

ICL7667CJA

OOCto+70 0 C

8 Pin Ceramic DIP

ICL7667ClV

OOCto +70 0 C

TO-99 Can

ICL7667MlV*

-55 0 C to + 1250 C

TO-99 Can

ICL7667MJA*

-55 0 Cto+1250 C

8 Pin Ceramic DIP

PACKAGE

*Add IBB3S to Part Number for 8838 Processing

Functional Diagram
8 LEAD DUAL-IN-LINE PACKAGE (PA, JA, BA)
TOP VIEW

NJC

NJC

INA

OUT A

v-

Vce - - _ - - - - - _ - - - - - ,

v+
IN

INB

OUTB

--1
-

-

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright

©

Harris Corporation 1991

2-141

File Number

2853

ICL7667
ABSOLUTE MAXIMUM RATINGS
Supply Voltage v+ to v- ......................... 15V
Storage Temperature ................ - 65·C to + 150·C
Input Voltage .........•...... (V- -0.3V) to (V+ +0.3V)
Operating Temperature Range
ICL7667C ............................ O·C to + 70·C
Package Dissipation, T A = 25·C .....•........... 500mW
ICL7667M .....•.................. -55·Cto + 125·C
Linear Derating Factors
Lead Temperature (Soldering, 10sec) ............• 300·C
TO-99
Plastic
Cerdip
5.6mWI"C
6.7mWI"C
6.7mW'·C
above50·C
above50·C
above 36·C
NOTE: stresses above those listed under "Absolute Maximum RaUngs" may cause permanent damage to the device. These are stress raUngs only and functional
operation of the device atlllese or any oilier conditions above lIIose indicated in the operational sections of lIIe specifications is not imp/iad. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (STATIC)
,

Symbol

Parameter

ICL7667C,M

ICL7667M

TA=2S·C

-SS·CS;TAS; + 125"C

Test Conditions

Min

Typ

Max

Min

Typ

Units

Max

VIH

Logic 1 Input Voltage

Vee = 4.5V

2.0

2.0

VIH

Logic 1 Input Voltage

Vee=15V

2.0

2.0

V

VIL

Logic 0 Input Voltage

Vee=4.5V

VIL

Logic 0 Input Voltage

Vee=15V

IlL

Input Current

Vee = 15V, VIN=OVand 15V

VOH

Output Voltage High

Vcc=4.5Vand 15V

VOL

Output Voltage Low

Vee=4.5V and 15V

0

0.05

0.1

V

ROUT

Output Resistance

VIN=VIL, IOUT= -10 mA,
Vee=15V

7

10

12

.!l

ROUT

Output Resistance

VIN=VIH, IOUT= 10mA,
Vcc=15V

8

12

13

.!l

Icc

Power Supply Current

Vee = 15V, VIN=3V both inputs

5

7

8

mA

Icc

Power Supply Current

Vee= 15V, VIN=OV both inputs

150

400

400

/LA

V
0.5

0.8
0.8
-0.1

0.1

Vee- 0.05

-0.1

0.8

V

0.1

/LA

Vee- O.1

Vee

V

V

ELECTRICAL CHARACTERISTICS (DYNAMIC)
ICL7667C,M

ICL7667M

TA=2S·C

-SS·CS;TAS; + 12S·C

Symbol

Parameter

Typ

Max

T02

Delay Time

Figure 3

35

50

60

ns

TR

Rise Time

Figure 3

20

30

40

ns

TF

Fall Time

Figure 3

20

30

40

ns

T01

Delay Time

Figure 3

20

30

40

ns

" .Test Conditions
Min

NOTE: AU typical vsiu9s hsvs been chsracterizsd but IlI'fJ not If1Sted.

2-142

Min

Typ

Units

Max

ICL7667
V+ = 15V
+5V
INPUT
INPUT

---+-1:>0-1-_--- OUTPUT

INPUT RISE ANO
FALL TIMESsl0na

"'.4V

---..:,=-..1

15V

.---+-[>0

OV
0323-4
0323-5

Figure 3: Test Circuit
CJ

z

en
13rn
o!::

Typical Performance Characteristics'

0:::;)

Rise and Fall Times vs CL

100

1",

/

/

..100
c

...I

./

TRISE

~

tr:

.. 10

rl

c

10

D2

60
60

~~

40

30

rr+"

1

80
70

20
10

I-"'"

I-'"

1000

10K

lOOK pF

40

-

TR"?

30
20

V

~

~

l..---'

CL=lnF
VCC=15V

T01-::;

10

~

OL-_~_L-

100

a:o
w

50

I
~;~~rv-

90

.

/

a:o
"-a:

TOI. T02 vs Temperature

-55

o

__

+25

~

____-'

70

O~--~~--~----~

+125

-55

0

+25

70

+125

·C

'C

Icc vs Frequency

No Load Icc VB Frequency

VCC=15V

30

C

10

E

~3.0

I-

-

lJ"

i-"'"

V

/

-

~

c

20kHz

I

E

l00~----~-----+--~~

l00~----1-----~--~-i

lD~----~~~~~---f

1I 10~----4---~~-----i

~

~
CL= 10pF

l00~A

1

10pF

100pF

lnF

10nF

VCC=15V

L-_ _.J-_ _-J._ _-.J

10k

lOOk

1M

FREOUENCY

10M

IOO~A

L ____..1-.____...L..____.....I

10k

lOOk

1M

10M

FREQUENCY
0323-6

NOTE: AU typical values hsvs bsBn charactsrfzed but lU9 not Issted.

2-143

ICL7667
Typical Performance Characteristics

(Continued)
Rise Time vs Vcc

. Delay and Fall Times vs Vcc
50

50

40

40

'"

...........

...-

TF
CL=1nF

TD1

10

o

'"

............

TR=TD2
eL= 10pF

10

5

10

o

15

5

Vee

10

15
Vee
0323-13

0323-12

power dissipation of the ICL7667 at high frequencies. It can
be minimized by keeping the rise and fall times of the input
to the ICL7667 below 1,...s.

DETAILED DESCRIPTION
The ICL7667 is a dual high-power CMOS inverter whose
inputs respond to TTL levels while the outputs can swing as
high as 15V. Its high output current enables it to rapidly
charge and discharge the gate capacitance of power MOSFETs, minimizing the switching losses in switchmode power
supplies. Since the output stage is CMOS, the output will
swing to within millivolts of both ground and Vee without
any external parts or extra power supplies as required by
the DS0026/56 family. Although most specifications are at
Vee=15V, the propagation delays and specifications are
almost independent of Vee.
In addition to power MOS drivers, the ICL7667 is well
suited for other applications such as bus, control signal, and
clock drivers on large memory of microprocessor boards,
where the load capacitance is large and low propagation
delays are required. Other potential applications include peripheral power drivers and charge-pump voltage inverters.

APPLICATION NOTES
Although the ICL7667 is simply a dual level-shifting inverter, there are several areas to which careful attention must
be paid.

GROUNDING
Since the input and the high current output current paths
both include the ground pin, it is very important to minimize
any common impedance in the ground return. Since the
ICL7667 is an inverter, any common impedance will generate negative feedback, and will degrade the delay, rise and
fall times. Use a ground plane if possible, or use separate
ground returns for the input and output circuits. To minimize
any common inductance in the ground return, separate the
input and output circuit ground returns as close to the
ICL7667 as is possible.

INPUT STAGE

BYPASSING

The input stage is a large N-channel FET with a P-channel constant-current source. This circuit has a threshold of
about 1.5V, relatively independent of the Vee voltage. This
means that the inputs will be directly compatible with TTL
over the entire 4.5 -15V Vee range. Being CMOS, the inputs draw less than 1,...A of current over the entire input
voltage range of ground to Vee. The quiescent current or no
load supply current of the ICL7667 is affected by the input
voltage, gOing to nearly zero when the inputs are at the 0
logic level and rising to 7mA maximum when both inputs are
at the 1 logic level. A small amount of hysteresis, about 50 100mV at the input, is generated by positive feedback
around the second stage.

The rapid charging and discharging of the load capacitance requires very high current spikes from the power supplies. A parallel combination of capacitors that has a low
impedance over a wide frequency range should be used. A
4.7,...F tantalum capacitor in parallel with a low inductance
0.1,...F capacitor is usually sufficient bypassing.

OUTPUT DAMPING
Ringing is a common problem in any circuit with very fast
rise or fall times. Such ringing will be aggravated by long
inductive lines with capacitive loads. Techniques to reduce
ringing include:
1)
Reduce inductance by making printed circuit board
traces as short as possible.
2)
Reduce inductance by using a ground plane or by
closely coupling the output lines to their return
paths.
3)
Use a 10 to 30n resistor in series with the output of
the ICL7667. Although this reduces ringing, it will
also slightly increase the rise and fall times.
4)
Use good bypassing techniques to prevent supply
voltage ringing.

OUTPUT STAGE
The ICL7667 output is a high-power CMOS inverter,
swinging between ground and Vee. At Vee=15V, the output impedance of the inverter is typically 7n. The high peak
current capability of the ICL7667 enables it to drive a
1000pF load with a rise time of only 40ns. Because the
output stage impedance is very low, up to 300mA will flow
through the series N- and P-channel output devices (from
Vee to ground) during output transitions. This crossover current is responsible for a significant portion of the internal

NOTE: AN typicallllllus$ have been chanICtsrized but are not tested.

2-144

ICL7667
is dissipating significant amounts of power. The very high
current output of the ICL7667 is able to rapidly overcome
this high capaCitance and quickly turns the MOSFET fully
on or off.

POWER DISSIPATION
The power dissipation of the ICL7667 has three main
components:
1)
Input inverter current loss
2)
Output stage crossover current loss
3)
Output stage 12R power loss
The sum of the above must stay within the specified limits
for reliable operation.
As noted above, the input inverter current is input voltage
dependent, with an Icc of 0.2mA maximum with a logic 0
input and 6mA maximum with a logic 1 input.
The output stage crowbar current is the current that flows
through the series N- and P-channel devices that form the
output. This current, about 300mA, occurs only during output transitions. Caution: The inputs should never be allowed to remain between VIL and VIH since this could leave
the output stage in a high current mode, rapidly leading to
destruction of the device. If only one of the drivers is being
used, be sure to tie the unused input to a ground. NEVER
leave an input floating. The average supply current drawn
by the output stage is frequency dependent, as can be seen
in Icc vs. Frequency graph in the Typical Characteristics
Graphs.
The output stage 12R power dissipation is nothing more
than the product of the output current times the voltage
drop across the output device. In addition to the current
drawn by any resistive load, there will be an output current
due to the charging and discharging of the load capacitance. In most high frequency circuits the current used to
charge and discharge capacitance dominates, and the power dissipation is approximately

II

In

!:i
g
I
In

~

1 'II r
1/

ID=IA

18
14

VDD-/'

sov '/

12
10

IlIIJpFL

./

I

6

4375oJ=

~VDO· I-

'f'"'

Vl30pF

o
-2

1
1
1

/2t2pF

1

024

e

8101214161120

00 -NANO COULOMOS

Figure 4: MOSFET Gate Dynamic
Characteristics

DIRECT DRIVE OF MOSFETs
Figure 6 shows interfaces between the ICL7667 and typical switching regulator ICs. Note that unlike the OS0026,
the ICL7667 does not need a dropping resistor and speedup capacitor between it and the regulator IC. The ICL7667,
with its high slew rate and high voltage drive can directly
drive the gate of the MOSFET. The 1527 IC is the same as
the 1525 IC, except that the outputs are inverted. This inversion is needed since ICL7667 is an inverting buffer.

TRANSFORMER COUPLED DRIVE OF
MOSFETs

PAC= CVcc2f
Where C = Load Capacitance
f = Frequency
In cases where the load is a power MOSFET and the gate
drive requirements are described in terms of gate charge,
the ICL7667 power dissipation will be

Transformers are often used for isolation between the
logic and control section and the power section of a switching regulator. The high output drive capability of the
ICL7667 enables it to directly drive such transformers. Figure 6 shows a typical transformer coupled drive circuit.
PWM ICs with either active high or active low outputs can
be used in this circuit, since any inversion required can be
obtained by reversing the windings on the secondaries.

PAc=QGVccf
Where QG = Charge required to switch the gate, in
Coulombs.
f = Frequency

BUFFERED DRIVERS FOR MULTIPLE
MOSFETs
In very high power applications which use a group of
MOSFETs in parallel, the input capacitance may be very
large and it can be difficult to charge and discharge quickly.
Figure 8 shows a circuit which works very well with very
large capacitance loads. When the input of the driver is
zero, Q1 is held in conduction by. the lower half of the
ICL7667 and Q2 is clamped off by Q1. When the input goes
positive, Q1 is turned off and a current pulse is applied to
the gate of Q2 by the upper half of the ICL7667 through the
transformer, T1. After about 20ns, T1 saturates and Q2 is
held on by its own Cgs and the bootstrap circuit of C1, 01
and R1. This bootstrap circuit may not be needed at frequencies greater than 10kHz since the input capaCitance of
Q2 discharges slowly.

POWER MOS DRIVER CIRCUITS
POWER MOS DRIVER REQUIREMENTS
Because it has a very high peak current output, the
ICL7667 excels at driving the gate of power MOS devices.
The high current output is important since it minimizes the
time the power MOS device is in the linear region. Figure 4
is a typical curve of charge vs. gate voltage for a power
MOSFET. The flat region is caused by the Miller capacitance, where the drain-to-gate capaCitance is multiplied by
the voltage gain of the FET. This increase in capacitance
occurs while the power MOSFET is in the linear region and

NOTE: All typical values have been characterized but arB nat tested.

2-145

(!I

:z
Cii
en
w en

01-

05
a:o
"-a:

a:o
w

~
"-

ICL7667
15V

+I65VOC

A~.f~-f---J·~I"~ ~
501527 B
GND

1-+-r:>O-lI-..J ~ IRF730
V-

0323-15

+15

0323-16

Figure 5: Direct Drive of MOSFET Gates

15V

11--------

+165V

~----~~~Lr----OV

"----.....-+--+--- -165V
L--~""-VOUT

0323-17

Figure 6: Transformer Coupled Drive Circuit

NOTE: AU typical values have been charscterized but 818 not tested.

2-146

ICL7667
v+

v+

I).SV

S'1..

INPUT FROM
PWMIC

Cl

:z
Ci5

ffiU)

01-

05
a:o
a. a:
a:C3
w

0323-18

Figure 7: Very High-Speed Driver

o
==
a.

Output Current vs
Output Voltage

+15

~·~tO:RHi

WAVE
TIL LEVELS

J
IN~1~11--""'--1III1111'~I--""-IN4001

lOj.F

'I

ICL7667

--

r
., 'IN4001 ;:f. 47~F

---

= 10kHz

-4t+++++ f
_sl-t-+-H-+ I

-13.5V

'"§!

..L
--

!:i

- 8 t+-t-+-SLOPE =6IKlt-:,,""~

~-10

0323-19

I

~

:::>

"

~ -121-t-+::..toEl--ll--rl-+-+-+-I

"

-14Ft-+-+-+-+-+-+-+-t-t~

5

20

40

80

80

100

IOUT-mA
0323-20

Figure 8: Voltage Inverter

NOTE: All typical values have been characterized but are not tested.

2-147

ICL7667
+15

+15

~~k"lWAVEIN ~ +:...t_.I-""_~+2I.5V
..

TTL LEVELS

V.

10~F

ICL71187

0323-21

Figure 9: Voltage Doubler

OTHER APPLICATIONS
RELAY AND LAMP DRIVERS
The ICL7667 is suitable for converting low power TTL or
CMOS Signals into high current, high voltage outputs for
relays, lamps and other loads. Unlike many other level
translator/driver ICs, the ICL7667 will both source and sink
current. The continuous output current is limited to 200mA
by the 12R power dissipation in the output FETs.

CHARGE PUMP OR VOLTAGE INVERTERS
AND DOUBLERS
The low output impedance and wide Vee range of the
ICL7667 make it well suited for charge pump circuits. Figure

8 shows a typical charge pump voltage inverter circuit and a
typical performance curve. A common use of this circuit is
to provide a low current negative supply for analog circuitry
or RS232 drivers. With an input voltage of + 15V, this circuit
will deliver 20mA at -12.6V. By increasing the size of the
capacitors, the current capability can be increased and the
voltage loss decreased. The practical range of the input frequency is 500Hz to 250kHz. As the frequency goes up, the
charge pump capacitors can be made smaller, but the internal losses in the ICL7667 will rise, reducing the circuit efficiency.
Figure 9, a voltage doubler, is very similar in both Circuitry
and performance. A potential use of Figure 8 would be to
supply the higher voltage needed for EEPROM or EPROM
programming.

CLOCK DRIVER
Some microprocessors (such as the 6BXX and 65XX families) use a clock signal to control the various LSI peripherals of the family. The ICL7667's combination of low propagation delay, high current drive capability and wide voltage
swing make it attractive for this application. Although the
ICL7667 is primarily intended for driving power MOSFET
gates at 15V, the ICL7667 also works well as a 5V highspeed buffer. Unlike standard 4000 series CMOS, the
ICL7667 uses short channel length FETs and the ICL7667
is only slightly slower at 5V than at 15V.

NOTE: AN typicsJ values have been charsct6lized but 8m not tested.

2-148

ICL7673

HARRIS
SEMICONDUCTOR

Automatic Battery
Back-up Switch

GENERAL DESCRIPTION

FEATURES

The Harris ICL7673 is a monolithic CMOS battery backup
circuit that offers unique performance advantages over conventional means of switching to a backup supply. The
ICL7673 is intended as a low-cost solution for the switching
of systems between two power supplies; main and battery
backup. The main application is keep-alive-battery power
switching for use in volatile CMOS RAM memory systems
and real time clocks. In many applications this circuit will
represent a low insertion voltage loss between the supplies
and load. This circuit features low current consumption,
wide operating voltage range, and exceptionally low leakage between inputs. Logic outputs are provided that can be
used to indicate which supply is connected and can also be
used to increase the power switching capability of the circuit
by driving external PNP transistors.

• Automatically Connects Output to The Greater Of
Either Input Supply Voltage
• If Main Power to External Equipment Is Lost, Circuit
Will Automatically Connect Battery Backup
• Reconnects Main Power When Restored
• Logic Indicator Signaling Status Of Main Power
• Low Impedance Connection Switches
• Low Internal Power Consumption
• Wide Supply Range: 2.5 to 15 Volts
• Low Leakage Between Inputs
• External Transistors May Be Added If Very Large
Currents Need to Be Switched

APPLICATIONS

oS

ORDERING INFORMATION

o On Board Battery Backup for Real-Time Clocks,
Timers, or Volatile RAMs
• Over/Under Voltage Detector
• Peak Voltage Detector
• Other Uses:
-Portable Instruments, Portable Telephones, Line
Operated Equipment

D..O:

Part Number

Temperature Range

Package

ICL7673CPA

OOCto+700 C

S Pin Mini DIP

ICL7673CBA

OOCto+700 C

SPinSOIC

ICL76731TV

-250C to +S5 0C

S Pin TO-99

Vp o---t"------..

PI

. -_ _ _OSbar

Pbar

GNDo-----------------~--L-~
0324-1

Vp> Vs, PI SWITCH ON AND Pbar SWITCH ON
Vs> Vp, P2 SWITCH ON AND Sbar SWITCH ON
Figure 1: Functional Diagram

HARRIS SEMICONDUCTOR'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE
,- CONDITION OF SALE. THE WARRANTY SHALL BE EXCLUSIVE AND SHALL -::: IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.

302070-005

NOTE: All typical values have been characterized bul are not tes/9d.

2-149

::z

U5

f3en
010: 0

~;-::-:----.,.....-------oVo

~o-~~~-----~-__,

(!J

0:0

w

~

ICL7673
ABSOLUTE MAXIMUM RATINGS
Input Supply (Vp or Vs) Voltage .... (GND - 0.3) to + 18V
Output Voltages Pbar and Sbar ..... (GND - 0.3) to + 18V
Peak Current
InputVp (@Vp=5V)(note 1) ................... 38mA
InputVs (@VS=3V) .......................... 30mA
Pbar or Sbar ..........................•...... 150mA
Continuous Current
InputVp (@Vp=5V)(notel) ................... 38mA
Input Vs (@ Vs = 3V) ...................•...... 30mA
Pbar or Sbar .................................. 50mA
Note 1. Derate above 25'C by O.3BmArc.

Package Dissipation ...•.•...•.•...•••....••.. 300mW
Derate .......•..•••••.•.....•••••..••••.••• 6.1 mW;oC
Operating Temperature Range:
ICL7673C ...•••..•••••.••••••••..•••• OOC to +700C
ICL76731 ...........•••..•••....•••. -250 C to +850 C
StorageTemperature •...••..•••.....• -65 0CtO+150oC
Lead Temperature (soldering, lOs) .••••.•.••••••• 3000C

NOTE: Stresses above those/isted under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of /he specifications is not implied. Exposure to absolute
maximum rating conditions tor extended periods may affect device reliability.

vp

Vp

Vo

Vp

NC

Vs

NC

PBAR

S8AR

NC

PBAR

GND

NC

GND

(Outline Dwg BA)
8 LEAD SOIC

(Outline Dwg TV)
8 LEAD TO-99

(Outline Dwg PAl
8 LEAD Mlnldlp

Figure 2: Pin Configurations

ELECTRICAL CHARACTERISTICS
Symbol
Vp

Parameter
INPUT VOLTAGE

Vs

ITA = 25°C unless otherwise specified)
Test Conditions

Min

Typ

Max

Vs=Ovolts
Iload=OmA

2.5

-

15

Vp=Ovolts
Iload=OmA

2.5

-

15

-

1.5

5

",A

-

8

15

n

@TA=85°C

16

-

Vp=9volts
Vs=3volts
I load = 15mA

-

6

-

n

Vp=12volts
Vs=3volts
I load = 15mA

-

5

-

n

1+

QUIESCENT SUPPLY
CURRENT

Vp=Ovolts
Vs=3volts
Iload=OmA

Rds(on)Pl

SWITCH RESISTANCE
P1
(NOTE 2)

Vp=5volts
Vs=3volts
I load = 15mA

NOTE: All typical values have been characterized but 8rB not tested.

2-150

Units

V

ICL7673
ELECTRICAL CHARACTERISTICS

(TA = 25°C unless otherwise specified) (Continued)

Min

Typ

Max

Units

-

0.5

-

%I"C

-

40

100

n

@TA=85°C

60

-

Vp=Ovolts
Vs=5volts
Iload=1mA

-

26

-

n

Vp=Ovolts
Vs=9 volts
Iload=1mA

-

16

-

n

Symbol

Parameter

TC(P1)

TEMPERATURE COEFFICIENT
OF SWITCH RESISTANCE P1

Vp=5volts
Vs=3volts
I load = 15mA

SWITCH RESISTANCE
P2
(NOTE 2)

Vp=Ovolts
Vs=3volts
Iload=1mA

Rds(on)P2

TC(P2)

IL(PS)

TEMPERATURE COEFFICIENT
OF SWITCH RESISTANCE P2
LEAKAGE CURRENT
(VptoVs)

Test Conditions

Vp=Ovolts'
Vs=3 volts
Iload=1mA
Vp=5volts
Vs=3 volts
Iload=10mA
@TA=85°C

IL(SP)

LEAKAGE CURRENT
(Vsto Vp)

Vp=Ovolts
Vs=3volts
Iload=1mA
@TA=85°C

VOPbar

OPEN DRAIN OUTPUT
SATURATION VOLTAGES

VOSbar

Cl

01-

oS

-

0::0

0.7

-

%I"C

-

0.Q1

20

35

-

-

0.01

50

120

-

nA

nA

-

85

400

-

120

-

Vp= 9 volts
Vs=3volts
I sink=3.2mA
Iload=OmA

-

50

-

mV

Vp=12volts
Vs=3 volts
I sink=3.2mA
Iload=OmA

-

40

-

mV

-

150

400

mV

@TA=85°C

210

-

Vp=Ovolts
Vs=5volts
I sink=3.2mA
Iload=OmA

-

85

-

mV

Vp=Ovolts
Vs=9volts
I sink = 3.2mA
Iload=OmA

-

50

-

mV

2-151

w

~

@TA=85°C

NOTE: AU typical values have bsen characterized but arB not testBd.

Q.o::

0::0
Q.

Vp=5volts
Vs=3volts
I sink = 3.2mA
Iload=OmA

Vp=Ovolts
Vs=3volts
I sink = 3.2mA
Iload=OmA

z

1i5
en
wen

mV

ICL7673
ELECTRICAL CHARACTERISTICS
Symbol

(TA= 25°C unless otherwise specified) (Continued)

Parameter

Test Conditions

OUTPUT LEAKAGE
CURRENTS
OF Pbar AND Sbar

IL Pbar

Min

Typ

Max

Units

-

50

500

nA

900

-

-

50

500

@TA=85°C

900

-

Vs=3volts
I sink = 3.2mA
I load = OmA

-

±10

±50

Vp=Ovolts
Vs= 15 volts
Iload=OmA
@TA=85°C
Vp=15volts
VS=Ovolts
Iload=OmA

ILSbar

SWITCHOVER UNCERTAINTY
FOR COMPLETE SWITCHING
OF INPUTS AND OPEN
DRAIN OUTPUTS.

Vp -Vs

nA

mV

NOTE 2. The minimum input to output voltage can be determined by multiplying the load current by the switch resistance.

TYPICAL PERFORMANCE CHARACTERISTICS
ON·RESISTANCE SWITCH PI AS A FUNCTION
OF INPUT VOLTAGE Vp

ON·RESISTANCE SWITCH P2 AS A FUNCTION
OF INPUT VOLTAGE Vs

100

100

ILOAO - mA

ILOAD - 15mA
iii

iii

~

~

=
...zA:

=
......
z

!a

!a

.
.,.

:!

........

...,.
N

1\

10

:!

-

...;;;a::

o

2

4

6

8

r--

iooo.

.-r-

10

...;;;a::

iooo.

Z

CI

......

Z

CI

o

10 12 14 16

INPUT VOLTAGE Vp IV)

2

4

6

8

10

INPUT VOLTAGE Vs
0324-6

0324-5

NOTE: All typicBI values haV9 bsBn charact6rizBd bul BrB not fBsted.

2-152

ICL7673
TYPICAL PERFORMANCE CHARACTERISTICS

(Continued)

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

Pbar OR Sbar SATURATION VOLTAGE
AS A FUNCTION OF OUTPUT CURRENT

5

en
w

~

.'"
.
.

0.8

ffi

.

Vo=3V

Vo=5V

/VO=9V

V

4

::!;

II

!:;

Q

a:

Q

0.6

Co>

::-

~

J

Z

Q

0Z

i=

w

a:

::::>

~

0-

::::>

Co>

en

:::;
Q.
Q.

0.2

::::>

/
o

2

::::>

+ 85 C

Q

Q.

i

L

en

4

8

10

12

J

0-

40°C
+25°(;-

V V

::::>

~~

05
a:u
tLa:

80

40

120

140

180

tL

As shown in the functional diagram (Figure I), the
ICL7673 includes a comparator which senses the input voltages Vp and Vs. The output of the comparator drives the
first inverter and the open-drain N-channel transistor Pbar.
The first inverter drives a large P-channel switch, PI, a second inverter, and another open-drain N-channel transistor,
Sbar. The second inverter drives another large P-channel
switch P2. The ICL7673, connected to a main and a backup
power supply, will connect the supply of greater potential to
its output. The circuit provides break-before-make switch
action as it switches from main to backup power in the
event of a main power supply failure. For proper operation,
inputs Vp and Vs must not be allowed to float, and, the
difference in the two supplies must be greater than 50 millivolts. The leakage current through the reverse biased parasitic diode of switch P2 is very low.

Vs .. 0 VOLTS

+85~C

lOlA

""""
G
w

".

OUTPUT VOLTAGE
The output operating voltage range is 2.5 to 15 volts. The
insertion loss between either input and the output is a function of load current, input voltage, and temperature. This is
due to the P-channels being operated in their triode region,
and, the ON-resistance of the switches is a function of output voltage Yo. The ON-resistance of the P-channels have
positive temperature coefficients, and therefore as temperature increases the insertion loss also increases. At low load
currents the output voltage is nearly equal to the greater of
the two inputs. The maximum voltage drop across switch PI
or P2 is 0.5 volts, since above this voltage the body-drain
parasitic diode will become forward biased. Complete
switching of the inputs and open-drain outputs typically occurs in 50 microseconds.

1000pA

10p4
+25°&

IIIIII

",

10

a:u

w

o

DETAILED DESCRIPTION

110AD "IOmA

~

(!)

:z

U5
U)

0324-8

IDOnA

.1!.'

V

$:

'''

.

V /' Vo=15V

OUTPUT CURRENT ImA)

IS LEAKAGE CURRENT Vp to Vs AS
A FUNCTION OF INPUT VOLTAGE

,.

/1"

~ t:/

0324-7

til

V

~~
o

SUPPLY VOLTAGE IV)

....

/

I V~ ~ V

0-

14 16

V

/

a:

0.4

a:

VO=12}1

J

w

Q.

12

INPUT Vp VOLTS
0324-9

NOTE- All typical values have been characterized but are not tested.

2-153

ICL7673
INPUT VOLTAGE
+5 VOLT
PRIMARY
SUPPLY

The input operating voltage range for Vp'or Vs is 2.5 to 15
volts. The input supply voltage (Vp or Vs) slew rate should
be limited to 2 volts per microsecond to avoid potential
harm to the circuit. In line-operated systems, the rate-of-rise
(or fall) of the supply is a function of power supply design.
For battery applications it may be necessary to use a capacitor between the input and ground pins to limit the rate-ofrise of the supply voltage. A low-impedance capacitor such
as a 0.047 p.F disc ceramic can be used to reduce the rateof-rise.

LITHIUM _

8 Vp

Yot'1'--1-0VO
+5 VOLTS OR
ICL
+3 VOLTS
7673
Pbar
8
STATUS
INDICATOR

BAITERYGNDo--+----~~------o
0324-11

STATUS INDICATOR OUTPUTS

Figure 4: ICL7673 Battery Backup Circuit

The N-channel open drain output transistors can be used
to indicate which supply is connected, or can be used to
drive external PNP transistors to increase the power switching capability of the circuit. When using external PNP power
transistors, the output current is limited by the beta and
thermal characteristics of the power transistors. The application section details the use of external PN P transistors.

+5 VOLT O--t------...;8"1Vp
Yo 1
PRIMARY
SUPPLY
ICL
1673

Vo
+5 VOLTS
OR
+3.6 VOLTS

APPLICATIONS
4

A typical discrete battery backup circuit is illustrated in
Figure 3. This approach requires several components, substantial printed circuit board space, and high labor cost. It
also consumes a fairly high quiescent current. The ICL7673
battery backup circuit, illustrated in Figure 4, will often replace such discrete designs and offer much better performance, higher reliability, and lower system manufacturing
cost. A trickle charge system could be implemented with an
additional resistor and diode as shown in Figure 5. A complete low power AC to regulated DC system can be implemented using the ICL7673 and ICL7663S micropower voltage regulator as shown in Figure 6.
+5 VOLT
PRIMARY
DC PDWER

GNDo-----4---+----o
0324-12

Figure 5: AppliCation Requiring Rechargeable
Battery Backup
Applications for the ICL7673 include volatile semiconductor memory storage systems, real-time clocks, timers, alarm
systems, and overI under voltage detectors. Other systems
requiring DC power when the master AC line supply fails
can also use the ICL7673.
A typical application, as illustrated in Figure 7, would be a
microprocessor system requiring a 5 volt supply. In the
event of primary supply failure, the system is powered
down, and a 3 volt battery is employed to maintain clock or
volatile memory data. The main and backup supplies are
connected to Vp and Vs, with the circuit output Vo supplying
power to the clock or volatile memory. The ICL7673 will
sense the main supply, when energized, to be of greater
potential than Vs and connect, via its internal MaS
switches, Vp to output Vo. The backup input, Vs will be disconnected internally. In the event of main supply failure, the
circuit will sense that the backup supply is now the greater
potential, disconnect Vp from Vo, and connect Vs.
Figure 8 illustrates the use of external PNP power transistors to increase the power switching capability of the circuit.
In this application the output current is limited by the beta
and thermal characteristics of the power transistors.
If hysteresis is desired for a particular low power application, positive feedback can be applied between the input Vp
and open drain output Sbar through a resistor as illustrated
in Figure 9. For high power applications hysteresis can be
applied as shown in Figure 10.
The ICL7673 can also be used as a clipping circuit as
illustrated in Figure 11. With high impedance loads the circuit output will be nearly equal to the greater of the two
input signals.

Vo
+5 VOLT OR
+3 VOLT

STATUS

.IOICATOA

-=-

NielD
BATTERY
STACK

GIDo--+--+-....----~-+_<>
0324-10

Figure 3: Discrete Battery Backup Circuit

NOTE: AU typical values haveiHHm chsracl9lfzed but 8M not tesllId.

2-154

ICL7673
Vp 8

8

II

BRIDGE
RECTIFIER

ICL
7663

i

120/240
VAC

4

Vo
ICL
7673

6

4

GND

STEPDOWN
TRANSFORMER

BATTERY
STACK
0324-13

Figure 6: Power Supply for Low Power Portable AC to DC Systems
C!l

:z

en

+5VOUo-----~------------------~~----------------_,

:TIm
01-

MAIl
POWER

oS
a:o

POWER

FAIL

MICROPROCESSOR

D..a:
a:u

~

DETECTOR

LLI

r----:':IC~L;....-., 'Is

Yo

INTERRUPT SIGNAL

7673
BACKUP
CIRCUIT

GND

VOLATILE
RAM

~

o

D..

-=- BACKUP

rnm
0324-14

Figure 7: Typical Microprocessor Memory Application

PNP

~

PNPl

1Vp 8

MAIN
SUPPLY

Vo LNC
ICL
7673

6

GND

3

Vs 2

!,:
3V
BACKUP
SUPPLY

P

'---

.

S

1

T

EXTERNAL
EQUIPMENT

Figure 8: High Current Battery Backup System

NOTE: All typical values haV8 been characterized but ars not tiJSted.

2-155

I
*>1MO

0324-15

ICL7673

RF

1

...Hs

MAlI ,..
SUPPlY -

1

Vp 8

110

ICL
7673

£2
T

S

3'--

BATTERY IGID
BACKUP

_

0324-16

Figure 9: Low Current Battery Backup System With Hysteresis

PNP

~

PNP
Rr

1

Rs

MAIN
SUPPLY

Vp

~
l....-

I-NC

8
ICL
7673

6

4

3

Vs 2
-_- BACKUP
BATTERY

T

P

EXTERNAL
EQUIPt.lENT

5

1

0324-17

Figure 10: High Current Backup System With Hysteresis

f--01lo

\/PO-ICL
7673

Vso--

-

~

:t{~i5~--

1GID
0324-18

Figure 11: Clipping Circuits

NOTE: An typical values havs been characterized but IU6 not tested.

2-156

ICL8211/ICL8212

HARRIS
SEMICONDUCTOR

Programmable Voltage Detectors

GENERAL DESCRIPTION

FEATURES

The Harris ICLB211/B212 are micropower bipolar monolithic integrated circuits intended primarily for precise voltage detection and generation. These circuits consist of an
accurate voltage reference, a comparator and a pair of output buffer/drivers.
Specifically, the ICLB211 provides a 7mA current limited
output sink when the voltage applied to the 'THRESHOLD'
terminal is less than 1.15 volts (the internal reference). The
ICLB212 requires a voltage in excess of 1.15 volts to switch
its output on (no current limit). Both devices have a low
current output (HYSTERESIS) which is switched on for input voltages in excess of 1.15V. The HYSTERESIS output
may be used to provide positive and noise free output
switching using a simple feedback network.

• High Accuracy Voltage Sensing and Generation:
Internal Reference 1.15 Volts Typical
• Low Sensitivity to Supply Voltage and Temperature
Variations
• Wide Supply Voltage Range: Typ. 1.8 to 30 Volts
• Essentially Constant Supply Current Over Full Supply
Voltage Range
• Easy to Set Hysteresis Voltage Range
• Defined Output Current Limit -ICL8211
High Output Current Capability -ICL8212

APPLICATIONS
• Low Voltage Sensor/Indicator
• High Voltage Sensor/Indicator
o Non Volatile Oui.of.Voltage Range Sensor/Indicator
• Programmable Voltage Reference or Zener Diode
o Series or Shunt Power Supply Regulator
o Fixed Value Constant Current Source

ORDERING INFORMATION
Part Number

Temperature Range

ICLB211CPA
ICLB211CBA
ICLB211CTY
ICLB211 MTYo
ICLB212C'PA
ICLB212CBA
ICLB212CTY
ICLB212MTYo

O'Cto +70'C
O'Cto +70'C
O'Cto+70'C
- 55'C to + 125'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C
- 55'C to+ 125'C

Package
Blead Mini DIP
B lead SOIC
TO-99 Can
TO-99 Can
Blead Mini DIP
61eadSOlC
TO-99 Can
TO-99 Can

• Add 18838 to part number if 8838 processing is required.
VOLTAGE REFERENCE COMPARATOR OUTPUT BUFFERS

~~=;4==;:~~:~~==,~,~~~==~,

____!oo v+
AS
4.5klI

.1::-_ _+

HYSTERESIS

NlCO.7 Nle
v+
HYSTEnEGIS 2
NlC
8

~RUHOLO

__..:2", HYST

OUTPUT 4

OUTPUT 2

5 GROUND

GROUND
(outline dwg PAl

OT9

(ouUlne dwg TVI

0328-2

3
THRESHOLD

I

I

I

,)

•

4

L{Q20 ~R6
''''II
I
I

I

0328-3

(outline dwg BA)
Figure 2: Pin Configurations



0::0

c..o::

0::0
W

Max Available
Output Current

(Note 3 &4)
VOUT=5V

Hysteresis Leakage
Current

V+ =10V
VTH= 0.8V
VHYST=GROUND

0.2

0.2

/LA

VHYS(max)

Hysteresis Saturation Voltage

IHYST= -7/LA VTH=1.3V
measured with respect to V +

0.3

0.3

V

IHYS(max)

Max Available
Hysteresis Current

IOH
IlHYS

VTH=0.8V
VTH=1.3V

VTH=1.3V

NOTE: All typical values haw been characterized but IlrB not t8Sted.

2-159

3

15

mA
rnA

9

10

10

p.A

U)

01::

~

c..

ICL8211/ICL8212
TYPICAL PERFORMANCE CHARACTERISTICS COMMON TO ICL8211 AND ICL8212
THRESHOLD INPUT CURRENT AS A
FUNCTION OF THRESHOLD VOLTAGE
10,000
TA=25"C

HYSTERESIS OUTPUT SATURATION CURRENT
AS A FUNCTION OF TEMPERATURE

l 0
1-5

V' = 5V
VTH = 1.2'1
VHYS =4.5V
(0' ~.5V wllh
:)-10
I-- respecl to V' supply)
u

v+=10V

I

ICL8211 OR ICL8212

I'.. ,

~-2O

I

0-25

'"iii-3O r--

I'

E
~

I

ICI211

-40 -20

10
0.0 1.1 1.15 1.2 2.0 3.0 6.0 8.0 10.0
THRESHOLD VOLTAGE-VTH
(IRREGULAR SCALE)

j'

ICj12

r--

0 +20 +40 +80 +80
TEMPERATURE'C
0328-5

0328-4

TYPICAL PERFORMANCE CHARACTERISTICS ICL8211 ONLY
SUPPLy CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

SUPPLY CURRENT AS A
FUNCTION OF THRESHOLD VOLTAGE

150

150

~

1125

I I

1100

Ii

..t

ll25

rc.VrH=UV.i±
TA=J.s,C
OUTPUTS ,PEN CIRCUIT

I:i

50

Ict1

"'25

i;l

'VTH=bv

o

,

I

150

CIRCUIT

, 100

:)

TA =25'C
V'=5V

\~UTSOPEN

:.

ipS

r.......

SUPPLY CURRENT AS A
FUNCTION OF TEMPERATURE

1~L82Jl-

rr:l=+=::CT'

ll25
, 100

Ii~

75 I---+---If--+---I-+---I

:)

U501---+--:-::-If-+--I-~"'"
~

25

i

.......

25

1-+---1:::-+,,=+--+--1

oL-~~

10
20
SUPPLY VOLTAGE

0.0

30

1.0 1.1 1.15 1.2 2.0 4.0
THRESHOLD VOLTAGE - VTH
(IRREGULAR SCALE)

-55 -2!i

___

~~~~

+5 +35 +85 +95 +125
TEMPERATURE ·C

0328-6

0328-8

0328-7

OUTPUT SATURATION CURRENTS
AS A FUNCTION OF
THRESHOLD VOLTAGE
12
,_ 10

$i.

I

TA=2i'C

t--t--tt-V' = $V
ICl!'211
I

I

r-HyJreRJSIS
u
O~
1\~rT
~ 4
S
I
I

d r-alnv

l

-5 $iIi

8

-IS!;

s

-200

III

~:~

1.12 1.13 1.14 1.15 1.18 1.17 1.1'
THRESHOLD VOLTAGE

~

THRESHOLD VOLTAGE TO TURN
OUTPUTS "JUST ON" AS A
FUNCTION OF SUPPLY VOLTAGE

1.11

III

Vo = O.sv
VHYS = V' - o.25V - 10

I

o:

0

THRESHOLD VOLTAGE TO TURN
OUTPUTS "JUST ON" AS A
FUNCTION OF TEMPERATURE

11.15

h..-F-l-+~L..+--I

91.14 1---+---1_.....-+--1---1

iii

...j!

I I \I
OUTPUT.....

e1.11

9

V-

§l1.1s
IIIII:

I

-55 -25 +5 +35 +85 +85 +125
TEMPERATURE ·C
0328-10

0328-9

NOTE: AU typical valu8s have been characterized but are not testsd.

2-160

V- /

./

. / 'HY.~

_
OUTPUT

~1.14

~1.13

11V

-101= l..!.~ Vo
1 1 II
7 A, VHYS = (Y' -2) V
1:11.17 -IHrS
III

IIJ~~lYi"!'

1.13
1

2 345 10 20304050 100
SUPPLY VOLTAGE
0328-11

ICL8211/ICL8212
TYPICAL PERFORMANCE CHARACTERISTICS ICL8211 ONLY
OUTPUT SATURATION CURRENT
AS A FUNCTION OF
TEMPERATURE

• :-/'

OUTPUT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE
12r-~~r-~~r-~~

IC~1

I

-

9

f-

ffi
"'

i"""-

~~L~5Vl11 1tH--+-++tH
,.,

I

VTH -1.147V

E 3 H-I-++I-+--1f4++-+-+H-H

~ E:/J~=F.::I=lfij
111~1tH

VrH = 1.1V

1.0r

0~~~~V~m~'.1.• 1~52V~~~

5
-55 -25 +5 +35 +85 +85 +125
TEMPERATUREOC

0.1

0

!Z

-5

..
lI1-

yy 1j1"fl'

10

irrYir

u -15

VTH = 1.0V

t::

i

::>

B8 t-fM-tI-t-1t-+I+t-li-+J--t-+ifH

v' =5V
vo l =

r-- N~Jocl

(Continued)
HYSTERESIS OUTPUT CURRENT
AS A FUNCTION OF HYSTERESIS
OUTPUT VOLTAGE

1.0
10.0
OUTPUT VOLTAGE

100.0

~-2O
0-25

~

~1.18V

!!I-30

'I

I
ICL8211
TA'; 25~C'

r110~11

III

m-35

II)

....-:,..-

IIIW

-.10

~ -10.00

-1.00
-0.10
-0.10
HYSTERESIS OUTPUT VOLTAGE
0328-23

0328-13

0328-12

TYPICAL PERFORMANCE CHARACTERISTICS ICL8212 ONLY
SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE
150

150

I

TA = 25°C

C125 --OUTP'fS 0tENJIRCUIT-

!Z1oo
~

B

I

75

-r--

i:

VrH

1.3V

I

I

TA -25°C

I--

ICLr2 , - I--

I

150

I

C

.a 125

..lI1

75

i

50

-

-

B

I

ij!25

1 I
10
20
SUPPLY VOLTAGE

yo =5V
OUTPUTS OrEN CIRCUIT

~1oo

I
I

r-- ICJ212

/VTH -o.9V

o

I

V'=5V
OUTPUTj OPEN CIVT":::

.a

.

SUPPLY CURRENT AS A
FUNCTION OF TEMPERATURE

SUPPLY CURRENT AS A
FUNCTION OF THRESHOLD VOLTAGE

I I

."...

o

30

-55 -25

0.0 1.0 1.1 1.15 1.2 2.0 4.0
THRESHOLO VOLTAGE· VTH
(IRREGULAR SCALE)

Ict12.t
tr=0'19V - "VrH = t3V

+5 +35 +85 -HIS +125
TEMPERATUREoC
.

0328-15

0328-17
0328-16

OUTPUT SATURATION CURRENTS
AS A FUNCTION OF
THRESHOLD VOLTAGE

THRESHOLD VOLTAGE TO TURN
OUTPUTS "JUST ON" AS A
FUNCTION OF TEMPERATURE

..!Z'"
~

o

t-tt-+-7F--+-i--l

20

,J--+'I-~

;! 1.16 1--+-+---'1--+--1-:.....-1

15

I-+\:A--,

9o

~

~

5 t-~t--t-,.­

1CL8212

\!I 1.17

25

~ 10 t-t-t-l~~

1.1'

1.17 ,---,-..,--,---r-..,---,

3Or-"TT"-r--r-r--r--,

I

THRESHOLD VOLTAGE TO TURN
OUTPUTS "JUST ON" AS A
FUNCTION OF SUPPLY VOLTAGE

i!:

~1.1'

9

:c

!;!

~

1.15

~ ~O rTi

11.15

1--+-----,""""

~

HYSTERESIT
j!:1.14 :fA = 25· C O~PUT
IOUT=_. VOUT = 1V
._
2) V
1.13 IHVS = -7~. VH~S =

lV' -

O~~~~~~~~
1.14

1
-25

+5

+35

+65

495 +125

TEMPERATURE "C
0328-18

0328-19

NOTE: All typical values have bsen characteriz8d but SI9 nol testrJd.

2-161

2 345 10 20304050 100
SUPPLY VOLTAGE
0328-20

ICL8211/ICL8212
TYPICAL PERFORMANCE CHARACTERISTICS ICL8212 ONLY
OUTPUT SATURATION VOLTAGE
AND CURRENT AS A FUNCTION
OF TEMPERATURE

OUTPUT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

!

30 H+ft-h>"H-tHl-+ttt....

iB

20 Hl-HiTI-t+H-t-i:m....

~10~~R-+-~+r~~~~
o

1.0

10.0 30.0 100.0

OUTPUT VOLTAGE

(Continued)
HYSTERESIS OUTPUT CURRENT
AS A FUNCTION OF HYSTERESIS
OUTPUT VOLTAGE

10

.... 1iII'"

1'?~~'3l ~

1-=
B-15

I:

Yr = 1.1S3V

11

I::::: ~;'~8VI

I:

1

II

,ICj11i
TA =ZSoC

-1.00

-0.10

DETAILED DESCRIPTION

-0.01

HYSTERESIS OUTPUT VOLTAGE

0328-22

0328-21

l-

rtITl1

>- -10.00
Z

J

0328-14

R3 kT
Thus 1.15=VeE (09 or 010)+- X-ln7
R2 q

The ICL8211 and ICL8212 use standard linear bipolar integrated circuit technology with high value thin film resistors
which define extremely low value currents.
Components 01 thru 010 and R1, R2 and R3 set up an
accurate voltage reference of 1.1 5 volts. This reference
voltage is close to the value of the bandgap voltage for
silicon and is highly stable with respect to both temperature
and supply voltage. The deviation from the bandgap voltage
is necessary due to the negative temperature coefficient of
the thin film resistors (- 5000 ppm per °C).
Components 02 thru 09 and R2 make up a constant current source; 02 and 03 are identical and form a current
mirror. 08 has 7 times the emitter area of 09, and due to the
current mirror, the collector currents of 08 and 09 are
forced to be equal and it can be shown that the collector
current in 08 and 09 is
1 kT
Ie (08 or09)=-x-ln7
R2 q
or approximately 1/LA at 25°C
Where k = Soltzman's constant
q = charge on an electron
and
T = absolute temperature in OK
Transistors Os, Os, and 07 assure that the VeE of 03, 04,
and 09 remain constant with supply voltage variations. This
ensures a constant current supply free from variations.
The base current of 01 provides sufficient start up current
for the constant source; there being two stable states for
this type of circuit - either ON as defined above, or OFF if
no start up current is provided. Leakage current in the transistors is not sufficient in itself to guarantee reliable startup.
04 is matched to 03 and 02; 010 is matched to 09. Thus
the Ie and VeE of 010 are identical to that of 09 or 08. To
generate the bandgap voltage, it is necessary to sum a voltage equal to the base emitter voltage of 09 to a voltage
proportional to the difference of the base emitter voltages
of two transistors 08 and 09 operating at two current densities.

which provides R3 = 12 (approx.)
R2
The total supply current consumed by the voltage reference section is approximately 6/LA at room temperature. A
voltage at the THRESHOLD input is compared to the reference 1.15 volts by the comparator consisting of transistors
011 thru 017. The outputs from the comparator are limited
to two diode drops less than V+ or approximately 1.1 volts.
Thus the base current into the hysteresis output transistor is
limited to about 500nA and the collector current of 019 to
100/LA.
In the case of the ICL8211, 021 is proportioned to have
70 times the emitter area of 020 thereby limiting the output
current to approximately 7mA, whereas for the ICL8212 almost all the collector current of 019 is available for base
drive to 021, resulting in a maximum available collector current of the order of 30mA. It is advisable to externally limit
this current to 25mA or less.

APPLICATIONS
The ICL8211 and ICL8212 are similar in many respects,
especially with regard to the setup of the input trip conditions and hysteresis circuitry. The following discussion describes both devices, and where differences occur they are
clearly noted.

General Information
THRESHOLD INPUT CONSIDERATIONS
Although any voltage between -5V and V+ may be applied to the THRESHOLD terminal, it is recommended that
the THRESHOLD voltage does not exceed about + 6 volts
since above that voltage the threshold input current increases sharply. Also, prolonged operation above this voltage will
lead to degradation of device characteristics.

NOTE: All typIcsI values haV8 been charactrHfzed but are not testild.

2-162

ICL8 211/ICL8 212
A principal application of the ICL8211 is voltage level detection, and for that reason the OUTPUT current has been
limited to typically 7mA to permit direct drive of an LED
connected to the positive supply without a series current
limiting resistor.
On the other hand the ICL8212 is intended for applications such as programmable zener references, and voltage
regulators where output currents well in excess of 7mA are
desirable. Therefore, the output of the ICL8212 is not current limited, and if the output is used to drive an LED, a
series current limiting resistor must be used.
In most applications an input resistor divider network may
be used to generate the 1.15V required for VTH. For high
accuracy, currents as large as 50J.!A may be used, however
for those applications where current limiting may be desirable, (such as when operating from a battery) currents as
low as 6J.!A may be considered without a great loss of accuracy. 6J.!A represents a practical minimum, since it is about
this level where the device's own input current becomes a
Significant percentage of that flowing in the divider network.

V'

INPUT
VOLTAGE
(RECOIIIIENOED RANGE -5 TO
+5 VOLTS)

(Y'MUST
EOUALOR
EXCEED 1.8
VOLTS)

VTH---'--....

RLI

I

Vo

V~ST

VO'
":"

I

VOl

0328-24

V~~~~~E 1.15V:.....,f--\-_ _-f---\ _ _-I'--_\_
VTH

ov --LHJ-----lJ:1
I I
ICL8211 OUTPUT

W

:;;:
o
D..

ICLB212 OUTPUT

0328-25

Figure 3: Voltage Level Detection
The outputs change states with an input THRESHOLD
voltage of approximately 1.15 volts. Input and output waveforms are shown in Figure 3 for a Simple 1.15 volt level
detector.
The HYSTERESIS output is a low current output and is
intended primarily for input threshold voltage hysteresis applications. If this output is used for other applications it is
suggested that output currents be limited to 10J.!A or less.
The regular OUTPUT's from either the ICL8211 or
ICL8212 may be used to drive most of the common logic
families such as TTL or C-MOS using a single pull up resistor. There is a guaranteed TTL fanout of 2 for the ICL8211
and 4 for the ICL8212.

v-~~------------~
0328-27

Figure 5: Input Resistor
Network Considerations
Case 1. High accuracy required, current in resistor network
unimportant Set 1= 50J.!A for VTH = 1.15 volts
:.Rl-20k!l.
Case 2. Good accuracy required, current in resistor network
important Set 1=7.5J.!A for VTH=1.15 volts
:.Rl - 150k!l.

SETUP PROCEDURES FOR VOLTAGE LEVEL
DETECTION

v'

Case 1. Simple voltage detection - no hysteresis
Unless an input voltage of approximately 1.15 volts is to
be detected, resistor networks will be used to divide or multiply the unknown voltage to be sensed. Figure 7 shows
procedures on how to set up resistor networks to detect
INPUT VOLTAGES of any magnitude and polarity.
For supply voltage level detection applications the input
resistor network is connected across the supply terminals
as shown in Figure 8.

0328-26

Figure 4: Output Logie Interface

NOTE: All typical values have been characterized but are not tested.

2-163

en

en
wen

o!::
0:::>
ceo
D..ce

ceo

INPUT

V'

OV

C)

:z

ICL8211/ICL8212
hysteresis is to provide positive feedback to the input trip
pOint such that there is a voltage difference between the
input voltage necessary to turn the outputs ON and OFF.
The advantage of hysteresis is especially apparent in
electrically noisy environments where simple but positive
voltage detection is required. Hysteresis circuitry, however,
is not limited to applications requiring better noise perform·
ance but may be expanded into highly complex systems
with multiple voltage level detection and memory applica·
tions - refer to specific applications section.
There are two simple methods to apply hysteresis to a
circuit for use in supply voltage level detection. These are
shown in Figure 9.
The circuit (a) of Figure 9 requires that the full current
flowing in the resistor network be sourced by the HYSTER·
ESIS output, whereas for circuit (b) the current to be
sourced by the HYSTERESIS output will be a function of the
ratio of the two trip points and their values. For low values
of hysteresis, circuit (b) is to be preferred due to the offset
voltage of the hysteresis output transistor.
A third way to obtain hysteresis (ICL8211 only) is to con·
nect a resistor between the OUTPUT and the THRESHOLD
terminals thereby reducing the total external resistance be·
tween the THRESHOLD and GROUND when the OUTPUT
is switched on.

INPUT
VOLTAGE

0328-28

Input voltage to change the output states
= (R1 + R2) x 1.15 volts
R1

Figure 6: Range of Input Voltage
Greater Than + 1.15 Volts

Practical Applications
a)

0328-29

Range of input voltage less than + 1.15 volts.
Input voltage to change the output states
(R1+ R2)X1.15 _ R2VREF .
R1

In this application the high trip voltage VTR2 is set to be
above the normal supply voltage range. On power up the
initial condition is A. On momentarily closing switch S1 the
operating point changes to B and will remain at B until the
supply voltage drops below VTR1, at which time the output
will revert to condition A. Note that state A is always reo
tained if the supply voltage is reduced below VTRl (even to
zero volts) and then raised back to VNOM.
c)
Non·Volatile Power Supply Malfunction Recorder
(Figures 12 and 13)
In many systems a transient or an extended abnormal (or
absence of a) supply voltage will cause a system failure.
This failure may take the form of information lost in a vola·
tile semiconductor memory stack, a loss of time in a timer or
even possible irreversible damage to components if a supply voltage exceeds a certain value.
It is, therefore, necessary to be able to detect and store
the fact that an out-of-operating range supply voltage
condition has occurred, even in the case where a supply
voltage may have dropped to zero. Upon power up to the
normal operating voltage this record must have been reo
tained and easily interrogated. This could be important in
the case of a transient power failure due to a faulty compo·
nent or intermittent power supply, open circuit, etc., where
direct observation of the failure is difficult.

R1

Figure 7: Input Resistor Network
Setup Procedures

r-------------1---oy+
R2
INPUT VOLTAGE
OR SUPPLY VOLTAGE

~----------~~vo

0328-30

Figure 8: Combined Input
and Supply Voltages
Case

Low Voltage Battery Indicator (Figure 10)

This application is particularly suitable for portable or reo
mote operated equipment which requires an indication of a
depleted or discharged battery. The quiescent current taken
by the system will be typically 35/LA which will increase to
7mA when the lamp is turned on. R3 will provide hysteresis
if required.
b)
Non-Volatile Low Voltage Detector (Figure 11)

2. Use of the HYSTERESIS function

The disadvantage of the simple detection circuits is that
there is a small but finite input range where the outputs are
neither totally 'ON' nor totally 'OFF'. The principle behind

NOTE: AI/typical values haV8 bgen ch8ract6Jized but ars not tested.

2-164

ICL8211/ICL8212
r--------...........,y.

150kll

L-------------+--oyo
0328-34

Figure 10: Low Voltage Battery Indicator

0326-31

Low trip voltage
(Rl +R2X1.15
]
VTR1= [
Rl)
+0.1 volts

Cl

~------~~-~Y'

:z
W

en
w en

High trip voltage
(Rl+ R2+ R3)
VTR2 =
X 1.15 volts
Rl

01-

05
a: 0
D..a:
a:o
w

Rl

;:;:

r---------...........,y.

o

D..

'-------------+-<~-<> OUTPUT

0328-35

(a)
~----------_+--oVo

S
~
o

"'OFF

0328-32

Low trip voltage
RoRs
]
1
VTR1= [ - - - +RP x-x1.15volts
(Ro+Rs)
Rp
High trip voltage

~ ON
~
~

(Rp+RO)
VTR2=--R-p-X 1.15 volts

r--rr-

s
~

!::!

ON

--

I

.----

IVrRl

IVTR2

::

0328-36

(b)

Figure 11: Non-Volatile Low Voltage Indicator

ON

~5

r----------~~-------------__.~~~

~

o

OFF~

~

~

SUPPLY VOLTAGE
0328-33

Figure 9: Two alternative voltage
detection circuits employing
hysteresis to provide pairs of
well defined trip voltages.

0328-37

Figure 12: Non-Volatile Power Supply
Malfunction Recorder

NOTE: All typical values have been characterized but are not tested.

2-165

ICL8211/ICL8212
A simple circuit to record an out of range voltage excursion may be constructed using an ICL8211, an ICL8212
plus a few resistors. This circuit will operate to 30 volts without exceeding the maximum ratings of the I.C.'s. The two
voltage limits defining the in range supply voltage may be
set to any value between 2.0 and 30 volts.
OUTPUT .CLI21'

1CU212 DISCONNECTED

OUTPUT .CU1l2
OFF

OUTPUT .CLI21'
AS PER FIGURE.
1 =25"" (ICU212)
I- 1 _ (ICU211,

-

ON

0328-39

Flgure'14: Constant Current,
Source Applications

0328-38

Figure 13: Output States of the
ICL8211 and ICL8212 as a
Function of the Supply Voltage

•

The ICL8212 is used to detect a voltage, V2, which is the
upper voltage limit to the operating voltage range. The
ICL8211 detects the lower voltage limit of the operating
voltage range, V,. Hysteresis is used with the JCL8211 so
that the output can be stable in either state over the operating voltage range V, to V2 by-making Vs-the upper trip
point of the ICL8211 much higher in voltage than V2.
The output of the ICL8212 is used to force the output ofthe ICL8211 into the ON state above V2. Thus there is no
value of the supply voltage that will result in the output of
the ICL8211 changing from the ON state to the OFF state.
This may be achieved only by shorting out Rs for values of
supply voltage between V, and V2.
d)
Constant Current Sources (Figure 14)
The ICL8212 may be used as a constant current source
of value of approximately 25/LA by connecting the
THRESHOLD terminal to GROUND. Similarly the ICL8211
will provide a 130p.A constant current source. The equivalent parallel resistance is in the tens of megohms over the
supply voltage range of 2 to 30 volts. These constant current sources may be used to provide biasing for various
circuitry including differential amplifiers and comparators.
See Typical Operating Characteristics for complete information.
e)
Programmable-Zener
Voltage
Reference
(Figure 15)
The ICL8212 may be used to simulate a zener diode by
connecting the OUTPUT terminal to the Vz output and using a resistor network connected to the THRESHOLD terminal to program the zener voltage
(R,+R21
Vzener = --R-,-X 1.15 volts.

T,,=25°C

5

JYV'

'LIs

t\.v· ;:~~~
50CIk II:!

o
0.0'

~

Vn!

OUT

'~I

~

'5Ok

.. --t

R,

a:
w

z

5"F~

I
I jill 11111

0.'
1.G.,o
'00
SUPPLY CURRENT-I 1_)
0328-40

Figure 15: Programmable Zener
Voltage Reference-

~~--------------.---.

YOUT =

'r-'-_-V'

110;' R, X 1.15 YOLTS
0328-41

Figure 16: Precision Voltage Regulator·

Since there is no internal compensation in the ICL8212 it
is necessary to use a large capaCitor across the output to
prevent oscillation.
Zener voltages from 2 to 30 volts may be programmed
and typical impedance values between 300/LA and 25mA
will range from 4 to 7n. The knee is sharper and occurs at a
significantly lower current than other similar devices available.

f)
Precision Voltage Regulator (Figure 16)
The ICL8212 may be used as the controller for a highly
stable series voltage regulator. The output voltage is simply
programmed, using a resistor divider network R, and R2.
Two capaCitors C, and C2 are required to ensure stability
since the ICL8212 is uncompensated internally.

NOTE; AN typIcsI values have been chMIctfItized but IIffI not fBst6d.

2-166

ICL8211/ICL8212
any commercial regulator. Applications would therefore include battery operated equipment especially those operating at low voltages.
g)
High Supply Voltage Dump Circuit (Figure 17)
In many circuit applications it is desirable to remove the
power supply in the case of high voltage overload. For circuits consuming less than 5mA this may be achieved using
an ICL8211 driving the load directly. For higher load currents it is necessary to use an external pnp transistor or
darlington pair driven by the output of the ICL8211. Resistors Rl and R2 set up the disconnect voltage and R3 provides optional voltage hysteresis if so desired.
h)
Frequency Limit Detector (Figure 18)
Simple frequency limit detectors providing a GO/NO-GO
output for use with varying amplitude input signals may be
conveniently implemented with the ICL8211/8212. In the
application shown, the first ICL8212 is used as a zero crossing detector. The output circuit consisting of Ra, R4 and C2
results in a slow output positive ramp. The negative range is
much faster than the positive range. Rs and Rs provide hysteresis so that under all circumstances the second ICL8212
is turned on for sufficient time to discharge Ca. The time
constant of R7 Ca is much greater than R4 C2. Depending
upon the desired output polarities for low and high input
frequencies, either an ICL8211 or an ICL8212 may be used
as the output driver.
This circuit is sensitive to supply voltage variations and
should be used with a stabilized power supply. At very low
frequencies the output will switch at the input frequency.

v+O--.---------------1~--~

r------

:

R3

L·"VAyA..r

v-~~----------~

a
0328-46
v+~~--------------~~--_,

r-----: Ra

v+

L-'VVV·

CIRCUIT
BEING
PROTECTED

v-

b
0328-42

Figure 17: High Voltage Dump Circuits
This regulator may be used with lower input voltages than
most other commercially available regulators and also consumes less power for a given output control current than

V'~~----------~~--------------~~--------~~

C,
INPUTo;t+_-ill

As

... OUTPUT

'------------+-~

TIME CONSTANT Ra C. 

o!::
0::0


short circuits at V+ 15 V can cause excessive power dissipation and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of the device.
tThis input current will only exist when the voltage at any of the input leads is driven negative. This current
is due to the collector-base junction of the input p-n-p transistors becoming forward biased and thereby
acting as input diode clamps. In addition to this diode action, there is also lateral n-p-n parasitic transistor
action on the Ie chip. This transistor action can cause the output voltages of the amplifiers to go to the
V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative.
This transistor action is not destructive and normal output states will re-establish when the input voltage,
which was negative, again returns to a value greater than -0.3 V dc.

v'
r-_4-_ _ _ _ _.-_~--.--~>--~_T02,3.4

+

~
2

6

7

-

'+
~
" 4

·sc

~
o+

, Vo

3

9

L - - 4 - - . - -.....- .....- - -.....----'--+---+---4-_TO 2,3,4
9:i'CM

2420'jRl

Fig. 2-Schematic diagram-one of four operational amplifiers.

3-12

-

8

4

CA 124, CA224, CA324, CA2902, LM324, LM2902
ELECTRICAL CHARACTERISTICS (Values Apply For Each Operational Amplified
TEST CONDITIONS
CHARACTERISTIC

CA124
LIMITS

Supply Voltage (V+) = 5 V
Unless Otherwise Specified Min.

UNITS
Typ.

Max.

TA=25 0 C
Input Offset Voltage, V 10

Note 3

-

2

5

mV

Output Voltage Swing, VOPP

RL = 2 kn

0

-

V+-1.5

V

Input Common-Mode
Voltage Range, VICR

Note 2, V+=30 V

0

-

V+-1.5

V

Input Offset Current, 110

11+-11

3

30

nA

Input Bias Current, liB

II+or II ' Note 1
VI+=+1 V, VI =OV,
V+=15 V

-

45

150

nA

20

40

-

rnA

VI+=O V,VI-=1 V,V+=15 V 10

20

-

rnA

VI+=O V,VI =1 V,
VO=200 mV

12

50

-

J1A

94

100

-

dB

Output Current (Source), 10
Output Current (Sink), 10

Large-Signal Voltage Gain, A

RL;;>2 kn,V+=15 V
(For large Vo swing)

Common-Mode Rejection Ratio,
DC
CMRR

70

85

-

dB

DC

Amplifier-to-Amplifier
Coupling

f=1 to 20 kHz (Input referred)

Input Offset Voltage, V 10
Temperature Coefficient of
I nput Offset Voltage, o:V 10

w:;;

65

100

-

dB

-

-120

-

dB

Note 3

-

-

7

mV

Rs = 0

-

7

-

pV/oC

11+-11

-

-

100

nA

-

10

-

pAjOC

T A = -55 to +125 0 C

Temperature Coefficient of
Input Offset Current, 0:110
Input Bias Current, liB

11+ or II

-

-

300

nA

,Total Supply Current, 1+

RL = 00 On All Ampl.

-

0_8

2

rnA

Input Common-Mode
Voltage Range, V ICR

V+= 30 V

0

-

V+-2

V

RL;;>2 kn,V+=15 V
(For large Vo swing)

88

-

-

dB

R L =2 kn, V+=30 V

26

-

RL-10 kn

27

28

-

V

RL =10 kn

-

5

20

mV

Source, 10

V I +=1 VDC,VI-=O,
V+=15 V

10

20

-

mA

Sink,lO

VI =1 VDC,VI+=O,
V+=15 V

5

8

-

mA

Note 2

-

-

V+

V

Large-Signal Voltage Gain,

Ii.

Output Voltage Swing:
High-Level, VOH
Low-Level, VOL
Output Current:

Differential Input Voltage

~§

a:: a.

Power Supply Rejection Ratici,
PSRR

Input Offset Current, 110

--'
«en

:z a::
OW

NOTE 1:

Due to the p-n-p input stage the direction of the input current Is out of the IC. No loading change
exists on the input lines because the current is essentially constan~ Independent of the state of the
output.
NOTE 2: The Input signal voltage and the Input common-mode voltage should not be allowed to go negative
by more than 0.3 V. The positive limit of the common-mode voltage range is V+ - 1.5 V, but either or
both inputs can go to +32 V without damage.
NOTE 3: Vo = 1.4 VDC, RS = 0
with V+ from 5 V to 30 V; and over the full input common-mode voltage
range (0 V to V+ - 1.5 V).

n

3-13

g;«

CA 124, CA224, CA324, CA2902, LM324, LM2902
ELECTRICAL CHARACTERISTICS (Values apply for each operational amplifier)
CA224, CA324
LIMITS

TEST CONDITIONS
CHARACTERISTIC

Supply Voltage (V+) = 5 V
Unless Otherwise Specified Min. Typ.

UNITS
Max.

TA = 25 0 C
Input Offset Voltage, VIO

Note 3

-

2

7

mV

Output Voltage Swing, VOpp

RL = 2 kn

0

-

V+ -1.5

V

Input Common-Mode
Voltage Range, VICR

Note 2, V+= 30 V

0

-

V+-1.5

V

Input Offset Current, 110

11+-11-

5

50

nA

Input Bias Current, liB

11+ or II ' Note 1
VI+=+l V, VI =OV,
V+=15 V

-

45

250

nA

20

40

-

mA

VI+=O V,VI-=l V, V+=15 V 10

20

-

mA

12

50

-

fJA

88

100

-

dB

Common-Mode Rejection Ratio,
DC
CMRR

65

70

-

dB

Power Supply Hejection Ratio,
PSRR

DC

65

100

-

dB

Amplifier-to-Amplifier
Coupling

f = 1 to 20 kHz
(Input referred)

-

-120

-

dB

Output Current (Sourcel.lo

Output Current (Sink), 10

VI+=O V,VI-=l V,
VO=200 mV

Large-Signal Voltage Gain,A

RL;;>2 kn,V+=15 V
(For large Vo swing)

T A = -40 to +85 0 C (CA224), T A = 0 to 70 0 C (CA324)
Input Offset Voltage, V 10

Note 3

-

-

9

mV

Temperature Coefficient of
Input Offset Voltage,exVIO

Rs = 0

-

7

-

p.V/oC

Input Offset Current, 110

11+-11

-

-

150

nA

-

10

-

pAfOC

-

500

nA

0.8

2

mA

Temperature Coefficient of
Input Offset Cu rrent,ex I 10
Input Bias Current, liB

II+or II

Total Supply Current, 1+

RL ="" On All Ampl.

-

Input Common-Mode
Voltage Range, VICR

V+=30 V

0

-

V+-2

V

RL;;>2 kn,V+=15 V
(For large Vo swing)

83

-

-

dB

Large-Signal Voltage Gain,A
Output Voltage Swing:

R L = 2 kn, V+ = 30 V

26

-

RL=10kn

27

28

-

V

RL=10kn

-

5

20

mV

Source, 10

VI+=l VDC,VI-=O,
V+=15 V

10

20

-

mA

Sink,lO

VI =1 VDC,VI+=O,
V+=15 V

5

8

-

mA

Note 2

-

-

V+

V

High-Level, VOH
Low-Level,VOL
Output Current:

Differential Input Voltage

NOTE 1: Due to the p-n~p Input stage the direction at the Input current is out of the IC. No loading change
exists on the input lines because the current is essentially constant. independent of the state of the
output.
NOTE 2: The input signal voltage and the input common-mode voltage should not be allowed to go negative
by more than 0.3 V. The positive limit of the common-mode voltage range is V+ -1.5 V. but either or
boIh inputs can go to +32 V without damage.
NOTE 3: Vo =1.4 VOC. RS = 0 n with V+ from 5 V to 30 V; and over the full input common-mode voltage
renge (0 V to V+ - 1.5 V).
3-14

CA 124, CA224, CA324, CA2902, LM324, LM2902

ELECTRICAL CHARACTERISTICS

(Values apply for each operational amplifier)
2902
UMITS

TEST CONDITIONS
CHARACTERISTIC

Supply Voltage (V+) = 5 V
Unless Otherwise Specified

UNITS
Min.

Typ.

Max.

TA = -40 to +85 0 C (CA2902)
Input Offset Voltage, Via

Note 3

-

-

10

mV

Temperature Coefficient of
Input Offset Voltage, CX:VIO

RS=O

-

7

-

I'VJOC

Input Offset Current, 110

II+-IC

-

45

200

nA

-

10

-

pAJOC

Temperature Coefficient of
Input Offset Curren~ oc:IIO
Input Bias Current, liB

11+ orlC, Note 1

-

40

500

nA

Input Common-Mode
Voltage Range, VICR

V+= 26 V,Note 2

0

-

V+-2

V

0.7

1.2

-

1.5

3

RL>2kO, v+= 15V
(For large Va swing)

83

-

-

RL=2kO, V+= 26V

22

-

RL=10kO

23

28

-

RL=10kO

-

5

100

mV

Source,lo

VI+ = 1 VDC, VC = 0,
V+=15V

10

20

-

mA

Sink,IO

Vc = 1 VDC, VI+ = 0,
v+=15V

5

8

-

mA

Note 2

-

-

V+

V

RL =

00

On All Ampl.

RL=oo,V+=26 V
Large-Signal Voltage Gain, A

mA

Low-Level, VOL

dB

V

Output Current:

Differential Input Voltage

Due to the p-n-p input stage the direction of the Input current is out of the IC. No loading change
exists on the input lines because the current is essentially constant, independent of the state of the
output.
NOTE 2: The input signal voltage and the input common-mode voltage should not be allowed to go negative
by more than 0.3 V. The positive limit of the common-mode voltage range is V+ - 1.5 V, but either or
both inputs can go to +32 V without damage.
NOTE 3: Vo = 1.4 VDC, RS = 0 0 with V+ from 5 V to 30 V; and over the full input common-mode voltage
range (0 V to V+ - 1.5 V).
NOTE 1:

3-15

!;i§
0: 0..

Output Voltage Swing:
High-Level, VOH

-de

I

. ..

10

-~

FREQUENCY tfl-Hz

25
50
75
-25
AMBIENT TEMPERATURE ITA l - t

-50

100

Fig. 6-0utput current VS. ambient temperature.

Fig. 5-Large-signal frequency response.

AMBIENT TEMPERATURE ITA 1- 2S.C

"'0
LOAD RESISTANCE (RL.)- 20 lin

-

100

"
00

"
10

20

10

20

30

SUPPLY VOLTAGE CV+)-V

SUPPLY VOLTAGE !V·J-V

Fig. 8- Voltage gain vs. supply voltage.

Fig. 7-lnput current vs. supply voltage.

3-16

40

CA 124, CA224, CA324, CA2902, LM324, LM2902
TYPICAL CHARACTERISTICS CURVES (CONT'O)

AM. lENT TEMPERATURE CTAI-Z5-C
SUP PLY VOLTAGE (Y+)-30 V

>E
1.00

9

~4~
1!

g40C

l-

:>
~ 350

6

• IF.

10k

roo II

O"I

3 ••
VI

l:

-=

'1Hr,-tHH
1"1 111.114-

OUTPUT·

300

LOO

~

1\

I I1

1110

.

·~~I~~~T 1

4. fIT'
,
.,
, rn ~.
III It

3
4
•
TIME (Il-,..

IOU

FREQUENCY III-HI

t
I"

HI!

Fig. IO-Voltage follower pulse response

Fig. 9-0pen·/oop frequency response.

(small signa/).

-'
«
en

:zcr::
OW

~~

W::5

~«

AMBIENT TEMPERATURE CTA'.Z5·C
SUPPLY VOLTAGE 1"'+1-15V
LOAD .RESISTANCE (RL I- Zlitl

I""
Iii"

,
,

'0 TIME

-,...

Fig. 11- Voltage follower pulse response.

3-17

til HARRIS

CA 158, CA 158A,CA258,
CA258A,CA358,CA358A,
CA2904, LM358*, LM2904*

Dual Operational Amplifiers
For Commercial, Industrial, and Military Applications

August 1991

Features

Description

• Internal Frequency Compensation for Unity Gain

The CA158, CA158A, CA258, CA258A, CA358, CA358A
and CA2904 types consist of two Independent, high gain,
Internally frequency compensated operational amplifiers
which are designed specifically to operate from a single
power supply over a wide range of voltages. They may also
be operated from split power supplies. The supply current Is
basically Independent of the supply voltage over the
recommended voltage range.

• High DC Voltage Gain •••••••••••••••• 100dB (Typ.)
• Wide Bandwidth at Unity Gain. • • • • • • •• 1MHz (Typ.)
• Wide Power Supply Range:
~ Single Supply ••••••••••••••••••••••••••• 3 to 30V
~ Dual Supplies •• ~ ••••••••••••••••••• ±1.5to±15V
• Low Supply Current ••••••••••••••••• 1.5 rnA (Typ.)
• Low Input Bias Current
• Low Input Offset Voltage and Current
• Input Common-Mode Voltage Range Includes
Ground
• Differential Input Voltage Range. Equal to V+ Range
• Large Output Voltage Swing ••••••••• OtoV+-1.5V

These devices are particularly useful in Interface circuits
with digital systems and can be operated from the single
common 5 Vdc power supply. They are also intended for
transducer amplifiers, dc gain blocks and many other con'
ventional op amp circuits which can benefit from the single
power supply capability.
The CA158, CA 158A, CA258, CA258A. CA358, CA358A,
and CA2904 types are supplied In 8-lead Small Outline
packages (M suffix), 8-lead dual-in-line plastic packages
(MINI-DIP, E suffix), 8-lead TO-5 style packages with
standard leads (T suffix), and with dual-in-lineformed leads
(OIL-CAN, S suffix). The CA358 is also supplied in chip
form (H suffix).
The CA158, CA158A, CA258, CA258A, CA358, CA358A,
and CA2904 types are an equivalent to or a replacement for
the Industry types 158, 158A, 258, 258A, 358, 358A, and
CA2904.

Pinouts
CA 158, CA258, and CA358
S-SUFFIX AND T-SUFFIX TYPES

CA158, CA258, CA358, AND CA2904
E-SUFFIX AND M-SUFFIX TYPES

INV.
INPUT (A)
OUTPUT (A)
INV.
INPUT (A)
NON -INV.
INPUT (A)

OUTPUT (B)

L.;;;..j--

L---l~

V-

INV.
INPUT (B)
NON -INV.
INPUT (B)

INV.
INPUT (B)
FIGURE 1.

FIGURE 2.

* Technical Data on LM Branded types is identical to the corresponding CA Branded types.
CAUTION; These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991
3-18

File Number

1019.1

CA 158, CA 158A, CA258, CA258A, CA358
CA358A, CA2904, LM358, LM2904
MAXIMUM RATINGS, Absolute-Maximum Values at TA =2!PC
SUPPLY VOLTAGE. v+:
CA2904 • . .

26Vor±13V
32Vor±16V

Other Types .
DIFFERENTIAL INPUT VOLTAGE:

±32V
-0.3 V to V+ V
50mA

All Type.

INPUT VOLTAGE.
INPUT CURRENT (VI <-O.3V) +
OUTPUT SHORT CIRCUIT TO GROUND
(V+<15V)* .
DEVICE DISSIPATION:
Up to T A = 55°C .
Above T A = 55°C.
AMBIENT TEMPERATURE RANGE:

Continuous

. •
630mW
derate linearly at 6.67 mW/oC
-55 to + 125°C
-65 to + 150°C

Operating .
Storage •
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm)
from case for 10 seconds max. .

+ This input current will only exist when the voltage at any of the input leads is driven negative. This current

*

is due to the collector-base junction of the input p-n-p transistors becoming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral n-p-n parasitic transistor action on the Ie chip. This transistor action can cause the output voltages of the amplifiers to go to the V+
voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This
transistor action is not destructive and normal output states will re-establish when the input voltage. which
was negative, again returns to a value greater than -0.3 V dc.
The maximum output current is approximately 40 rnA independent of the magnitude of V+. Continuous
short circuits at V+ 15 V can cause excessive power dissipation and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of the device. Destructive dissipa~
tion can result from simultaneous short circuits on both amplifiers.

>

r-__-*__________1-__~--_.----~--~~~T02

:tr
+

2

6

"sc
I Vo

92CM-29569

Fig.3 - Schematic diagram - one of two operational amplifiers.

3-19

-

7

CA 158, CA 158A, CA258, CA258A, CA358
CA358A, CA2904, LM358, LM2904
ELECTRICAL CHARACTERISTICS (Values Apply For Each Operational Amplifier)

TEST CONDITIONS
CHARACTERISTIC
Supply Voltage (V+) = 5 V
Unless Otherwise Specified

LIMITS
CA158A (E, T, S)
Min. Typ.

UNITS

Max.

TA = 25°C
Input Offset Voltage, VIO

Note 3

-

1

RL = 2 kn

0

-

2
V+-l.5

mV

Output Voltage Swing, VOpp
Input Common·Mode
Voltage Range, VICR

Note 2, V+ = 30 V

0

-

V+ -1.5

V

-

2

10

nA

20

50

nA
mA
mA

V

Input Offset Current, 110

11+-11

Input Bias Current, liB

11+ or II ,Note 1

Output Current (Source I. 10

VI+=+l V, VI-=O V,
V+= 15 V

20

40

VI+=O V, VI-= 1 V, V+=15 V

10

20

-

12

50

-

f.I.A

Output Current (Sink), 10

VI+=O V, VI-= 1 V,
Vo=200mV

Short Circuit Output Current

R L = 0 (to Ground) Note 4

-

40

60

mA

Large Signal Voltage Gain, AOL

RL;;"2 kn, V+= 15 V
(For large Vo swing)

50

100

-

V/mV

Common·Mode Rejection
Ratio, CMRR

DC

70

85

-

dB

Power Supply Rejection
Ratio, PSRR

DC

65

100

-

dB

Amp( ifier·to·Amplifier
Coupling

f = 1 to 20 kHz (I nput referred)

-

-120

-

dB

Input Offset Voltage, VIO

Note 3

-

-

4

mV

Temperature Coefficient of
Input Offset Voltage,oVIO

Rs = 0

-

7

15

f.I.V/ o C

Input Offset Current, 110

11+-11-

-

-

30

nA

-

10

200

pA/oC

TA = -55 to +1250 C

Temperature Coefficient of
Input Offset Current, 0:110
Input Bias Current, liB

.11+or 11-

-

40

100

nA

Input Common·Mode
Voltage Range, VICR

V+ = 30 V, Note 2

0

-

V+-2

V

RL = 00 On All Amp!.

-

0.7

1.2

1.5

3

Supply Current, 1+

RL = 00, V+ = 30 V

mA

NOTE 1: Due to the p-n-p input stage the direction of the input current is out of the IC. No loading change eXists

on the input lines because this current is essentially constant, independent of the state of the output.
NOTE 2: The input signal voltages and the input common-mode voltage should no, be allowed to go negative by
more than 0.3 V. The positive limit of the common-mode voltage range is V+ - 1.5 V. but either or both
inputs can go the + 32 V without damage.
NOTE 3: Vo = 1.4 VOC, Rs = 0 11. with V+ from 5 V to 30 V, and over the full input common·mode voltage range
(OVtoV+-1.5V).

NOTE 4: The maximum output current is approximately 40 rnA independent of the magnitude of V+. Continuous
short circuits at V+ 15 V can cause excessive power dissipation and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of thedevice. Destructive dissipation can result from simultaneous short circuits on both amplifiers.

>-

3-20

CA 158, CA 158A, CA258, CA258A, CA358
CA358A, CA2904, LM358, LM2904
ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)

TEST CONDITIONS
CHARACTERISTIC
Supply Voltage (V+) = 5 V
Unless Otherwise Specified

LIMITS
CA258A (E, T, S)
Min. Typ.

UNITS

Max.

TA = 250 C
Input Offset Voltage, VIO

Note 3

-

1

3

mV

Output Voltage Swing, VOpp

RL = 2 Hl

0

-

V+ -1.5

V

Input Common·Mode
Voltage Range, VICR

Note 2, V+ = 30 V

0

-

V+ -1.5

V

Input Offset Current, 110

11+-11

2

15

nA

Input Bias Current, liB

11+ or II ,Note 1

-

40

80

nA

20

40

-

mA

10

20

-

mA

12

50

-

!lA

Output Current (Source), 10

VI+=+1 V, VI-=O V,
V+= 15 V
VI+=O V, VI-= 1 V, V+=15 V

Output Current (Sink), 10

VI+=O V, VI-= 1 V,
Vo=200mV

Short Circuit Output Current

RL = 0 (to Ground) Note 4

-

40

60

mA

Large Signal Voltage Gain, AOL

RL;;' 2 Hl, V+: 15 V
(For large Vo swing)

50

100

-

V/mV

Common·Mode Rejection
Ratio, CMRR

DC

70

85

-

dB

Power' Supply Rejection
Ratio, PSRR

DC

65

100

-

dB

Ampl ifier-to-Ampl ifier
Coupling

f = 1 to 20 kHz (Input referred)

-

-120

-

dB

Input Offset Voltage, VIO

Note 3

-

-

4

mV

Temperature Coefficient of
Input Offset Voltage,o:VIO

Rs = 0

-

7

15

!lV/oC

Input Offset Current, 110

It-II-

-

-

30

nA

T A = -25 to +85 0 C

Temperature Coefficient of
Input Offset Current, 0:110

-

10

200

pA/oC

Input Bias Current, liB

II+or 11-

-

40

100

nA

Input Common-Mode
Voltage Range, VICR

V+ = 30 V, Note 2

0

-

V+-2

V

RL = 00 On All Amp!.

-

0.7

1.2

1.5

3

Supply Current, 1+

RL = 00, V+ = 30 V

mA

NOTE 1: Due to the p-n-p input stage the direction of the input current is out of the IC. No loading change exists
on the input lines because this current is essentially constant, independent of the state of the output.
NOTE 2: The input signal voltages and the input common-mode voltage should not be allowed to go negative by
more than 0.3 V. The positive limit of the common-mode voltage range is V+ - 1.5 V. but either or both
inputs can go the + 32 V without damage.
NOTE 3: Va = 1.4 VOC. Rs = a n with V+ from 5 V to 30 V, and over the full input common-mode voltage range
(0 V to V+ - 1.5 V).
NOTE 4: The maximum output current is approximately 40 rnA independent of the magnitude of Vi. Continuous
short circuits at V+ 15 V can cause excessive power dissipation and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of thedevice. Destructive dissipation can result from simultaneous short circuits on both amplifier...

>

3-21

CA 158, CA 158A, CA258, CA258A, CA358
CA358A, CA2904, LM358, LM2904
ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)

TEST CONDITIONS
CHARACTERISTIC
Supply Voltage (V+) = 5 V
Unless Otherwise Specified

LIMITS
CA35RA (E. T. S)
Min. Typ.

UNITS

Max.

TA = 25 0 C
Input Offset Voltage, VIO

Note 3

-

2

3

mV

Output Voltage Swing, VOpp

RL = 2 k!1

0

-

V+ -1.5

V

Input Common·Mode
Voltage Range, VICR

Note 2, V+ =30 V

0

-

V+-l.5

V

Input Offset Current, 110

11+ -II

-

5

30

nA

Input Bias Current, liB

11+ or II ,Note 1

-

45

100

nA

Output Current (Source), 10

VI+=+l V. VI
V+= 15 V

20

40

-

mA

10

20

-

mA

12

50

-

j.tA

=0 V,

VI+=O V, VI-= 1 V, V+=15 V
Output Current (Sink), 10

VI+=OV, VI-=l V,
Vo=200mV

Short Circuit Output Current

RL =0 (to Ground) Note 4

-

40

60

mA

Large Signal Voltage Gain, AOL

RL;;;' 2 k!1, V+= 15 V
(For large Vo swing)

25

100

-

VlmV

Common-Mode Rejection
Ratio, CMRR

DC

65

B5

-

dB

Power· Supply Rejection
Ratio, PSRR

DC

65

100

-

dB

Amplifier-to-Amplifier
Coupling

f = 1 to 20 kHz (I nputreferred)

-

-120

-

dB

Input Offset Voltage, VIO

Note 3

-

-

5

mV

Temperature Coefficient of
Input Offset Voltage,a=VIO

Rs = 0

-

7

20

j.tV/oC

Input Offset Current, 110

11+- 11-

-

-

75

nA

TA = 0 to +700 C

Temperature Coefficient of
Input Offset Current, 

3-22

CA 158, CA 158A, CA258, CA258A, CA358
CA358A, CA2904, LM358, LM2904
ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)
LIMITS
CA158 (E, T, S)
CA258 (E, T, 5)

TEST CONDITIONS
CHARACTERISTIC
Supply Voltage (V+) =5 V
Unless Otherwise Specified
TA

Min. Typ.

UNITS

Max.

=25°C
-

2

5

mV

0

-

V+ -1.5

V

Note 2, V+=30 V

0

-

V+ -1.5

V

Input Offset Current, 110

11+-11

-

3

30

nA

Input Bias Current, liB

11+ or II ,Note 1

-

45

150

nA

20

40

-

mA

10

20

-

mA

12

50

-

/lA

Input Offset Voltage, VIO

Note 3

Output Voltage Swing, VOpp

RL

Input Common·Mode
Voltage Range, VICR

Output Current (Source), 10

=2 kn

VI+=+l V, VI -=0 V,
V+= 15 V
VI+=O V, VI-= 1 V, V+=15 V

Output Current (Sink), 10

VI+=OV, VI-=l V,
Vo=200mV

Short Circuit Output Current

RL = 0 (to Ground) Note 4

-

40

60

mA

Large Signal Voltage Gain, AOL

RL;;'2kn,V+=15V
(For large Vo swing)

50

100

-

VlmV

Common· Mode Rejection
Ratio, CMRR

DC

70

85

-

dB

Power' Supply Rejection
Ratio, PSRR

DC

65

100

-

dB

Amplifier·to·Amplifier
Coupling

f = 1 to 20 kHz (Input referred)

-

-120

-

dB

TA = -55 to + 1250 C (CA158); TA = -25 to +850 C (CA258)
Input Offset Voltage, VIO

Note 3

-

-

7

mV

Temperature Coefficient of
Input Offset Voltage,exVIO

Rs = 0

-

7

-

/lV/oC

I nput Offset Current, 110

11+-11-

-

-

100

nA

-

pA/oC

II+or 11-

-

10

Input Bias Current, 118

40

300

nA

Input Common·Mode
Voltage Range, VICR

V+ = 30 V, Note 2

0

-

V+-2

V

RL = 00 On All Ampl.

-

0.7

1.2

1.5

3

Temperature Coefficient of
Input Offset Current, exiiO

Supply Current, 1+

RL =00, V+= 30 V

mA

NOTE 1: Due to the p-n-p input stage the direction of the input current Is out of the IC. No loading change exists
on the input lines because this current is essentially constant, independent of the state of the output
NOTE 2: The input signal voltages and the input common-mode voltage should not be allowed to go negative by
more than 0.3 V. The positive limit of the common-mode voltage range is V+ -1.5 V, but either or both
inputs can go the +32 V without damage.
NOTE 3: Vo = 1.4, VDC, RS =0 n with V+ from 5 V to 30 V, and over the full input common-mode voltage range
(0 V to V+ -1.5 V).
NOTE 4: The maximum output current is approximately 40 mA Independent of the magnitude of V+. Continuous
short circuits at V+ > 15 V can cause excessive power dissipation and eventual destruction. Short
circuits from the output to V+ can cause overheating and eventual destruction of the device. Destructive
dissipation can result from simultaneous short circuits on both amplifiers.

3-23

-'
2 kn, V+= 15 V
(For large Vo swing)

25

100

-

V/mV

Common-Mode Rejection
Ratio, CMRR

DC

65

70

-

dB

Power' Supply Rejection
Ratio, PSRR

DC

65

100

-

dB

Amplifier-to-Amplifier
Coupling

f = 1 to 20 kHz (Input referred)

-

-120

-

dB

Input Offset Voltage, VIO

Note 3

-

-

9

mV

Temperature Coefficient of
Input Offset Voltage,o:VIO

Rs = 0

-

7

-

/J.V/oC

Input Offset Current, 110

It-II-

-

-

150

nA

-

pAloC

11+ or 11-

-

10

Input Bias Current, liB

40

500

nA

Input Common-Mode
Voltage Range, VICR

V+ = 30 V, Note 2

0

-

V+-2

V

RL = 00 On All Ampl.

-

0.7

1.2

1.5

3

TA = 0 to +70o C

Temperature Coefficient of
Input Offset Current, 0:110

Supply Current, 1+

RL=oo,V+=30V

mA

NOTE 1: Due 10 the p-n-p Input stage the direction of the Input current is out of the IC. No loading change exists
on the input lines because this current Is essentially constant, independent of the state of the output.
NOTE 2: The Input signal voltages and the Input common-mode voltage should not be allowed 10 go negative by
more than 0.3 V. The positive limn of the common-mode voltage range is V+ -1.5 V, but either or both
inputs can go the +32 V without damage.
NOTE 3: Vo = 1.4, VDC, RS = 0 n with v+ from 5 V 10 30 V, and over the full Input common-mode voltage range
(0 V to V+ -1.5 V).
NOTE 4: The maximum output current Is approximately 40 mA Independent of the magnitude of V+. Continuous
short circuits at V+ > 15 V can cause excessive power dissipation and eventual destruction. Short
circuits from the output to V+ can cause overheating and eventual destruction of the device. Destructive
dissipation can result from simultaneous short clrcuHs on both amplifiers.

3-24

CA 158, CA 158A, CA258, CA258A, CA358
CA358A, CA2904, LM358, LM2904
ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)

LIMITS

TEST CONDITIONS
CHARACTERISTIC

CA2904E
Supply Vollage (V+) = 5 V
Unless Otherwise Specified

Min.

Typ.

UNITS

Max.

TA=25 0 C
Input Offset Voltage, V 0

Note 3

-

2

7

mV

Output Voltage Swing, VOPP

RL = 10 kO

0

-

V+ -l.S

V

Input Common·Mode
Voltage Ra~ge, VICR

Note 2, V+ =30 V

0

-

V+ -1.5

V

Input Offset Current, 110

11+ -II

-

S

50

nA

Input Bias Current, liB

11+ or II ' Note 1

-

45

2S0

nA

20

40

-

mA

10

20

-

Output Current (Source), 10

Output Current (Sink), 10

VI+=+l V, VI

=0 V,

V+= 15 V

VI+=O V, VI-= 1 V,V+:1S.V

rnA

-'
<(I)
ow

;za:

i=U::

<::::;
a: 0.

Short Circuit Output Current

RL = 0 (to Ground) Note 4

-

40

60

rnA

Large Signal Voltage Gain, AOL

RL;;' 2 kf!, V+ = 15 V
(For large Va swing)

-

100

-

V/mV

Common·Mode Rejection
Ratio, CMRR

DC

50

70

-

dB

Power' Supply Rejection
Ratio, PSRR

DC

50

100

-

dB

Amplifier·to·Amplifier
Coupling

f = 1 to 20 kHz (Input referred)

-

-120

-

dB

Input Offset Voltage, VIO

Note 3

-

-

10

mV

Temperature Coefficient of
Input Offset Voltage,o:VIO

Rs = 0

-

7

-

/-lV/oC

Input Offset Current, 110

11+-11-

-

45

200

nA

TA = -40 to +85 0 C

Temperature Coefficient of
Input Offset Current, exiiO

-

10

-

pA/oC

Input Bias Current, liB

11+ or II

-

40

SOO

nA

Input Common·Mode
Voltage Range, VICR

V+ = 30 V, Note 2

0

-

V+-2

V

RL = 00 On All Ampl.

-

0.7

1.2

R L = 00, V+ = 30 V

-

1.S

3

Supply Current, 1+

mA

NOTE1: Due to the p-n-p input stage the direction of the input current is out of the IC. No loading change exists
on the Input lines because this current is essentially constant, Independent of the state of the output
NOTE 2: The input signal voltages and the input common-mode voltage should not be allowed to go negative by
more than 0.3 V. The positive limit of the common-mode voltage range is V+ -1.5 V, but either or both
inputs can go the +32 V without damage.
NOTE 3: Vo = 1.4, VDC, RS = 0 n with V+ from 5 V to 30 V, and over the full input common-mode voltage range
(0 V to V+ -1.5 V).
NOTE 4: The maximum output current is approximately 40 mA Independent of the magnitude of V+. Continuous
short circuits at V+ > 15 V can cause excessive power dissipation and eventual destruction. Short
circuits from the output to V+ can cause overheating and eventual destruction of the device. Destructive
dissipation can result from simultaneous short circuits on both amplifiers.

3-25

w::;;

~<

CA 158, CA 158A, CA258, CA258A, CA358
CA358A, CA2904, LM358, LM2904
INPUT COMMON-MODE VOLTAGE
RANGE (VIeR)· 0 v

'i!
I

H

SUPPLY VOLTAGE {V""-'!OV

5

H

;:.

•• v

10

_o

_

~

0

~

~

~

~

~

AMBIENT TEMPERATURE {TA)-"C

SUPPLY VOLTAGE (V+)-V

Fig. 5 - Input current as a function of
ambient temperature.

Fig. 4 - Input voltage range as a function of
supply voltage.

AMBIENT TEMPERATURE {TA}-

C TO +125-C

-S!>O

o

1015202530
SUPPLY VOLTAGE (Y-+}-V

INPUT FREQUENCY (fIN)- Hz

Fig. 6 - Supply current drain as a function of
supply voltage.

Fig. 7 - Common mode rejection ratio as a
function of input frequency.

~ .ol-~----+----H~

I

601----l----J.'P ;:..a..!---.--..--"r---l

~ .ol-_+-_+-_+--2>~.

i 201--+--+--!--l-';""~
10

0

30

40

SUPPLY VOLTAGE IV.)-V

10

100

10k

lit

I.M

lOOk

FREQUENCY ttl-Hz

Fig. 8 - Voltage gain as a function of supply
voltage.

Fig. 9 - Open-loop frequency response.

-

AMBllNT TEMPERATURE (TA).25-C
SUPPLY VOLTAGE (V+)-30 V

AMBIENT TEMPERATURE ITAI-25-C
SUPPLY VOL.TAGE IY+)-'5V
LOAD RESIST.t.NCE I RL ,- 2 lin

~
:1 ""PFr

1"0

5'.
.00

+.

-

INPUT

OUTPUT

• •en-,..•

eo

TIME

TIMe(t)-,a

Fig. 11 - Voltage follower pulse response
(small signal).

Fig. 10 - Voltage follower pulse response.

3-26

CA 158, CA 158A, CA258, CA258A, CA358
CA358A, CA2904, LM358, LM2904
IOOkn

20 AMBIENT TEMPERATURE

I? ,.

f - l--ITA J oZ5·C.

_

AMBIENT TEMPERATURE {TA I- 25-C

Q~
!

0

z

~

10

r\

~

!•
0

.
I
~

Zk,Q.

r

'\

. ,.

,

. ..'" , . , .

,

10k

10

1M

.0

20

SUPPLY VOLTAGE I"'·I-V

fREQUENCY It 1- Hz

Fig. 13 -Inputcurrentasa function of
supply voltage.

Fig. 12 - Large·signal frequency response.

•
7

1+
E~

~~
g~

~~
~!!O

5

•
•

+t-

10

~

..,+· . . 5 Voc

+Y+/2

+

_I
IO.

_

!- =

=

INDEPENDENT OF
TA"+25"C

I

~

"'+·+15 Voc
V"'·+30VOC
I

~

v'"

I
II

3
2

~

V+/2

OJ

[IV
001

I

0.01

01

100

10

OUTPUT SOURCE CURRENT (Ial-mA

0001

=

V-

I I

_

i~

Xo

W:E

~--®_~r--+V'OUT

,N
V

.l.
92CS-15746

FIGURE 7. TRANSIENT RESPONSE TEST CIRCUIT FOR ALL TYPES

Chip Photos
DIMENSIONS AND PAD LAYOUTS
CA741CH

CA1458H
104

NOTE: Dimensions in parentheses are in millimeters and are derived from the basic Inch dimensions as Indicated. Grid graduations are in mils (10-3 inch).

3-34

CA3020
CA3020A

mHARRIS

Multipurpose Wide-Band Power Amplifiers
Military, Industrial & Commercial Equip. @ Freq. Up to 8MHz

August 1991

Description

Features
o

High Power Output Class B Amplifier
.. CA3020 ••••••••••••••••••••••••••.••. O.5WTyp.atVCC=+QV
.. CA3020A •••••••••••••••••••••••••••••• 1.0WTyp. atVcc +12V

o

Wide Frequency Range ••••••••• Up to 8MHz With Resistive Loads

o

High Power Gain •••••••••••••••••••••••••••••••••••••• 75dB Typ.

o

Single Power Supply For Class B Operation With Transformer
.. CA3020 " ••••••••••••••••••••••••••••••••••••••••••• 3V to QV
.. CA3020A ••••••••••••••••••••••••••••••••••••••••••• 3V 10 12V

o

Built-In Temperature-Tracking Voltage Regulator Provides Stable
Operation Over - 55 0 C to +125 0 C Temperature Range

Applications
o

AF Power Amplifiers For Portable and Fixed Sound and
Communications Systems

o

Servo-Control Amplifiers

o

Wide-Band Linear Mixers

o

Video Power Amplifiers

The CA3020 and CA3020A are particularly suited for
service as class B power amplifIers. The CA3020A
can provide a maximum power output of 1 watt from a
12 volt dc supply with a typical power gain of 75dB.
The CA3020 provides 0.5 watt power output from a 9
volt supply with the same power gain.
These types are supplied in hermetically sealed
TO-5 style 12 lead packages.

o

Transmission-Line Driver Amplifiers (Balanced and Unbalanced)

o

Fan-In and Fan-Out Amplifiers For Computer LOQlc Circuits

o

Lamp-Control Amplifiers

o

Motor-Control Amplifiers

o

Power Multlvlbralors

o

Power Switches

o

Companion Application Note, ICAN-5766, "Application of CA3020
and CA3020A Integrated Circuit Multipurpose Wide-Band Power
Amplifiers"

Pinout

The CA3020 and CA3020A are integrated-circuit,
multi-stage,
multipurpose,
wIde-band
power
amplifiers on a single monolithic silicon chip. They
employ a hIghly versatile and stable direct-coupled
circuit configuration featuring wide frequency range,
high voltage and power gain, and high power output.
These features plus inherent stability over a WIde
temperature range make the CA3020 and CA3020A
extremely useful for a wIde variety of applications In
military, industrial, and commercial equipment.

Schematic Diagram
CA3020

v'

OUTPUT

NPN·E

FIGURE1. DIAGRAM FOR CA3020 AND CA3020A
The resistance values included on the schematic diagram have been supplied as a convenience to
assist Equipment Manufacturers in optimizing the selection of "outboard" components of
equipment designs. Tho values shown may vary as much as ± 30%.
Harris reserves the right to make any changes in the Resistance Values provided such changes do
not adversely affect the published performance characteristics of the device.
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-35

File Number

339.1

.....

...---.'. •
e OUT2
Total Harmonic Distortion

1.
2.
3.
4.

Close SI and S2; open S3
Apply desired values of V CC and V CC
Adjust e IN for desired level Jmplifier o,nput power
Record Total Harmonic Distortion (THD) in 'Y.
Fig.12

3-42

m

CA3060

HARRIS

Operational Transconductance
Amplifier Arrays

August 1991

Features

Description

• Low Power Consumption as Low as 100mW Per
Amplifier

The CA3060 monolithic integrated circuit consists of an array of
three independent Operational Transconductance Amplifiers!
This type of amplifier has the generic characteristics of an
operational voltage amplifier with the exception that the forward
gain characteristic is best described by transconductance rather
than voltage gain (open-loop voltage gain is the product of the
transconductance and the load resistance, gmRL). When
operated into a suitable load resistor and with provisions for
feedback, these amplifiers are well suited for a wide variety of
operational-amplifier and related applications. In addition, the
extremely high output impedance makes these types particularly
well suited for service in active filter.

• Independent Biasing for Each Amplifier
• High Forward Transconductance
• Programmable Range of Input Characteristics
• Low Input Bias and Input Offset Current
• High Input and Output Impedance
• No Effect on Device Under Output Short-Circuit
Conditions
• Zener Diode Bias Regulator

Applications
• For Low Power Conventional
Amplifier Applications

Operational

• Active Filters
• Comparators
• Gyrators
• Mixers
o Modulators

The three amplifiers in the CA3060 are identical push-pull Class
A types which can be independently biased to achieve a wide
range of characteristics for specific application. The electrical
characteristics of each amplifier are a function of the amplifier
bias current(IABC). This feature offers the system designer
maximum flexibility with regard to output current capability,
power consumption, slew rate, input resistance. input bias
current, and input offset current. The linear variation of the
parameters with respect to bias and the ability to maintain a
constant dc level between input and output of each amplifier also
makes the CA3060 suitable for a variety of non-linear
applications such as mixers, multipliers, and modulators..
In addition, the CA3060 incorporates a unique Zener diode
regulator system that permits current regulation below supply
voltages normally associated with such systems.

• Multiplexers
• Multipliers

The CA3060 is supplied in a 16-lead duaHn-line plastic package
(E suffix) and In chip form (H suffix). This device is operational
from -40 0 C to +85 0 C.

• Strobing an d Gating Functions
• Sample and Hold Functions

Block Diagram
TOP VIEW
REGUlATOR OUT

1

REGUlATOR IN

2

OUTPUT No.1
BIAS No.1

NON· INV. INPUT No.1
INV. INPUT No.3 4NON - INV. INPUT No.3

INV. INPUT No.1
INV. INPUT No.2

5

NON· INY. INPUT No.2
OUTPUT No.3 7

BIAS NO.2

9 OUTPUT No.2

FIGURE 1 FUNCTIONAL BLOCK DIAGRAM FOR THE CA3060

*Generic applications of the OTA are described in ICAN-S66S. For improved input operating ranges, refer to CA30aO and CA3280 data bulletins (File Nos.
475 and 1174) and application notes ICAN-6668 and ICAN-6818.
CAlTTION: These devices are sensitive to electrostatic discharge. Proper
Copyright @ Harris Corporation 1991

I.e. handling

3-43

procedures should be followed.

File Number

537.1

.....



E

I

~

1.5

-0
H

/i

~

a
>

I

...
.."...
t;

V'

0.5

a

VOLTAGE~";;~V.-:_::i;~

/'

J/
'#

I

~~

••4

./

, / ~"
,,/
tfY
- - ~...~
•

,./

2

UI

-55'C

~

.,.."

!5'"u

/,~25OC

...
~

~

'25 ' C

AMBIENT TEMPERATURE (TA1=2SoC
SUPPLY

2

~IOO

~

"~

•

4

10

6

?:

4

./

2

0
2

4

6 •

10

2

4

6

•

100

AMPLIFIER B I AS CURRENT I.I ABC) -

2

4

6

I
2

1000

po A 92CS-19612

4

6

2

4

••

2

4

••

10
100
1000
AM PLlFlfR BIAS CURRENT (lABe)- JJ-A 92CS-19618

Fig.4-lnput offset current vs. amplifier bias current.

Fig.3-lnput offset voltage vs. amplifier bias current.

3-45

CA3060

10.

.

•

4

I

~

..
.,.
l-

z

~

•4•

II:
II:

:>

u

.•
2

iii

~ 0.1

"-

~

V

r--- ~l'F'E:R B'A~

"-

I

I

...
!:!
...

"

----

I

-",

~
V /'J'"
.("q

V+'157'V-'-I~V

..

~Yr

2

I

10 SUPPLY VOLTAGE:V··6V.V---6V

AMBIENT TEMPERATURE (TA)=25°C
SUPPLY VOLTAGE: V+=6V,V-. 6V
V+=15 V V-=-15V

IZ
II:
II:

:>

..
.,u

V

I-

:>

"-

~

2

0.01
2

4

••

4

2

••

4

2
100
AMPLIFIER BIAS CURRENT IIABC)-p.A
~

0.01

-75

••

~oo

cxlBC!'IOOI'A

-

r--

- ----

OJ

iD

4,./

CURRkNT

50

-

o

25

25

I---

10l'A

-

!I'A_

50

75

125

100

AMBIENT TEMPERATURE(TA)-OC
92CS-19S04

92CS-19614

Fig.5a-lnput bias current vs. amplifier
bias current

Fig.5b-lnput bias current vs. ambient
temperature.

.

c(IOOO SUPPLY VOLTAGE: yt-6V,Y-=-6V

..dOOOa AMBIENT TEMPERATURE (TAl-25°C

"-

,.

AN~~;~~~;t;;IA~5~uRREh-'IABC)"IOOI'A -

r-k,4
0

2

f1'!.
W
l-

30I'A
100

••

3
!i!

10~A

'" •

S

I-

15
II:

2

31'A

II:

:>

u

10

••

l-

:>

"-

•

l-

:>
0

."

It
4

6

8

6

10

4

B

100

II'A

1-----=

2

I

75

••

50

25

1000

AMPLIFIER BIAS CURRENT IIABCI-I'A

o

25

75

125

100

AMBIENT TEMPERATURE ITA )_·C 92CS-19608
92CS-19615

Fig.6a-Peak output current vs. ampli·
fier bias current.

14
13

>
I

"....
0

>

~

0

>

I-

~

I I

12

I

L

.

VOM+ ITVPICAl! ±15V SUPPLY

"-

~uplpl~1
61-- ~tOM~I~I~IMUMj[±15V
i "1Iii'
I i -I" I

J

5

~

4
31- YOM' IMINIMUM46~ SUPPLV]_ VOM.ITVPICALl~6V SUPPlV]

...z

·3

I I I II
I
I I II
AMBIENT TEMPERATURE (TA)" 2S·C I I

-4
-6

"
~

-12
-13

-14
-I

VOM-tMI~IMUM)&:15V SUPPL
I
2

I

•

II

~

.. ,

:T~P~CAl!

~

2

it

--I

4

1>
~'7

-1-'' '

4

"'~ /'

"'/

~ 100

I

••
•
..,.
ffi

;;:

::;
"-

I

6

V/,

2

±15/ SIUPPllt

•• I
2
4
2
10
100
AMPLIFIER BIAS CURRENT II.ABCI-I'A

)y~ -

2

••

SUPPLY

I I II
It
I VOM-ITVPICAl!j±6V SUPPl~
VOIM-

AMBIENT TEMPERATURE I TA )= 25°C
SUPPLY VOLTAGE V+"SV, v-,,-SV
v+,. 15 V. v-" -ISV

1-1000

a

'1

•

4

II:
II:

I

I

r VOM-(MINIMUM~6V

-5

:>

"-

10,000a

I.

I

I-

0

Fig.6b-Peak output current vs. ambient
temperature.

,n 1'"/
2

•

1000

••

• ••

2
2
4
10
100
AMPLIFIER BIAS CURRENT tIABc)-pA

92CS-19607

Fig.8a-Amplifier supply current (each
amplifier) vs. amplifier bias current.

Fig.7-Peak output voltage vs. amplifier
bias current.

3-46

4

••

1000

CA3060

..

1000
6

""
I

0

t:!
Iz

100
8

II:
II:

0

SUPPLY

t - - t- AMPLIFIER BIAS eURREN,-' IABel -100 "A

E

2

'4

'"

-

10"A

6

=>

3"Ai

u

..

2

~

~

I

./

I"A

8
6

ffi

..

;;:

'"""

I
~

750

...'"~

100

.,>
""
...;;:

650

~

,,/

~

in

II:

'"""

2 SUPPLY VOLTAGE:V -SV, V-.-SV
Y+-15V,Y-a-15V
I
75
50
25
o
25

-

,,/

0

600

~

0

::;

VOLTAGE: V+"'6V, V-"-SV
V+",5V,V-·-15V

>

JO"A- -

./

550

./'

,/

V

500

-

50

7S

125

100

2

4

0
6 •
2
0
6 •
2
10
100
AMPLIFIER BIAS CURRENT (lABC 1--.,.... A

AMBIENT TEMPERATURE ITA)-·C 92CS-19606

6 •

1000

92CS-19617

Fig.8b-Amplifier supply current (each
amplifier) lIS- ambient temperature.

Fig.9-Amplifier bias voltage vs. amplifier bias current.
-'
«en
za:

10008 AMBIENT TEMPERATURE IT AJ-2'S-C

•

E
E

.

I

1.

~=>

0

••

0

II:
l-

Ii!

2
I

10

•
2

""

).9,f

V

J

ABC I - I00 I'A_

r--

3011' A -

r---

6

4

1-

z

~z

9"

""

II:

./

~«

eURREN~ I I

•

0

".\~

./

t--h

- _AMPLifiER BIAS
100

~

2

1°I'A
10

8

I-

..

•

0
II:

I

It

a:

lii
l!

I ~\<.?-"

10.

z

.,z
""

~

I.&J

2

u

2

N

•

U
Z

~~
w:;;

"l!

....N IOO e

::
...

OW

c'0008 SUPPLY VOLTAGE: V+=SV, V-a -6V
V+·,5Y Y-·'5Y
6
'
E
0 FRE JENey f - kH,

SUPPLY YOLTAGE. Y+a6Y, V-a -6Y
Y+·,5Y.V-.-I'5Y
2 FREQUENCY tt)-lkHz

4

11

4

;0

II:

It
2

• ••

2

• ••

•

2

10
100
AMPLIFIER BIAS CURRENT IrABC)-~A

2

'I'A

I
6 •

-50

1000

-25
0
25
50
15
,00
125
AMBIENT TEMPERATURE (TAl-"C 92CS-19603

92CS-I9621

Fig.l0b-Forward transconductance vs.
ambient temperature.

Fig.l0a-Forward transconductance vs.
amplifier bias current.

100

~

E

1

~

'"u
~u

=>

0
Z

0

l;\

z

""

II:

I0

iIt

•

r-....

0

2

10~A

';'),

AMPLIFIER BIAS CURRENT
crABe I:: IOO.uA r

,-

1--;

-100

8

•

r~

0

-150

I
8

- 200

•

o PHASE ANGLE ____ "
2 FORWARD
0.1 TRANSCONDUCTANCE
8

..,
:J:

fh

,.'"z
~

2,- 1,,1

\

•

.e:'"

'il

2

1.
...

~IOOO

8

.:;;

•4

~

2

lii

T

II:

Q

... 100

-250 ~
-300

10,0008 AMBIENT TEMPERATURE (TAl" 2S·C
SUPPLY YOLTAGE: y+: 6V, Y-"-S V
V+"15 v, Y-"-15Y
0
FREQUENCY tt I" I kHz

•

50

,Il.... ~
"'4

10

0

ill
G:

-350
4 SUPPLY VOLTAGE· V -SV,V-. OV
V+:15V,V- =-15V
2
0.01 AMBIENT TEMPERATURE (TA) ~25·C
2 4 68 L 2 468-'. 2 0.8
2 0.8
2 4.8
0.001
0.01
0.1
10
100
FREQUENCY If) - MHz
92CS-19605

~

""

......

..........
i'

.........

8

~r

0

.,'+~

.c,

•

;;

~"'.,

2

10
2

•• 10

2

4

'N..

6 8
Z
100
AMPLIFIER BIAS CURRENT (IABC)-.uA
0

4

6 8
1000

9ZCS-19616

Fig. 12-lnput resistance vs. amplifier bias
current.

Fig." -Forward transconductance vs.
frequency.

3-47

CA3060

INPUT

RZ

RS
OUTPUT

= [(V+)-(V·)·O.7]
12

EXTERNAL

m'OMn
tL£

RABC = VZ' VABC
IABC

Supply Voltage: for both ±6 V and ±15 V.

TYPICAL SLEW RATE TEST CIRCUIT PARAMETERS
IABC

92CS-15855RI

Vz is measured between terminals 1 and B.

12

RABC

RS

RF

RB

IJA

Vips

100

8

200

62 k

1

200

620k

1M

1M 510k

0.1

2

6.2M

10M

10M 5.1M

10

VABC is measured between terminals 15 and B.

SLEW
RATE

1

RC

ohms

IJA

lOOk lOOk

Cc
IJF

51k 100

0.02

lk 0.005
co

0

Fig. 13-Slew rate test circuit for amplifier No. I of CA3060.
1000S AMBIENT TEMPERATURE (TA )-25-C

,

6 SUPPLY VOLTAGE V+,.6V. V-·-6V
V.,'5V. V-'15V
4 -

FREQUENY (f)-1kHz

i

2

I

'0100

!!O

•

tlz

6

~

4

;!

*..'" •

.. "..

2

~" ,

0:

I-

:>

10

I-

6

0

4

:>

{

I'

2

I
2

•

6

•

10

2

4

6

•

I'
100

2

4

AMPLIFIER BIAS CURRENT IIABC)-p.A

6 •

1000

a

92CS-19620

Fig. 14-0utput resistance vs. amplifier bias current.

200
400
600
800
1000
BIAS REGULATOR CURRENT UZlp.A

Fig. 15-Bias regulator voltage

vs.

92CS-19619

bias regulator current.

OPERATING CONSIDERATIONS

The CA3060 consists of three operational amplifiers similar
in form and application to conventional operational ampli·
fiers but sufficiently different from the standard operational
amplifier (op-amp) to justify some explanation of their
characteristics. The' amplifiers incorporated in the CA3060
are best described by the term Operational Transconductance
Amplifier (OTA). The characteristics of an ideal OTA are
similar to those of an ideal op-amp except that the OTA has
an extremely high output impedance. Because of this
inherent characteristic the output signal is best defined in
terms of current which is proportional to the difference
between the voltages of the two input terminals. Thus, the
transfer characteristic is best described in terms of transconductance rather than voltage gain. Other than the difference
given above, the characteristics tabu lated on pages 3 and 4 of
this data ~ulletin are similar to those of any typical op·amp.
The OTA circuitry incorporated in the CA3060 (See Fig. 16)
provides the equipment designer with a wider variety of

circuit arrangements than does the standard op-amp; because
as the curves in the data bulletin indicate, the user may select
the optimum circuit conditions for a specific application
simply by varying the bias conditions of each amplifier. If
low power consumption, low bias, and low offset current, or
high input impedance are primary design requirements, then
'low current operating conditions may be selected. On the
other hand, if operation into a moderate load impedance is
the primary consideration, then higher levels of bias may be
used.
Bias Considerations for Op-Amp Applications
The operational transconductance amplifiers allow the circuit
designer to select and control the operating cond itions of the
circuit merely by the adjustment of the input bias current
IABC' This enables the designer to have complete control
over transconductance, peak output current and total power
consumption independent of supply Voltage.

3-48

CA3060
r----.--------~----~------~~Ov+

AMPLIFIER
BIAS

CURRENT-

IABC)

v-o---~-----+----------------~~--~--~~---------------+-----ov-

COMPLETE OTA CIRCUIT

9ZeU-19GII

Fig. 16-Complete schematic diagram showing bias regulator and one of the three operational transconductance amplifiers.

In addition, the high output impedance makes these
amplifiers ideal for applications where current summing is
involved.
The design of a typical operational amplifier circuit (See Fig.
17) would proceed as follows:

g21 = AOL/RL
= 100/18 kn
~

5.5 mmho

(R L = 20 kn in parallel with 200 kn

+6V

~

18kn)

2. Selection of suitable amplifier bias current.
The amplifier bias current is selected from the minimum
value curve of transconductance (F ig. lOa) to assure that
the amplifier will provide sufficient gain. For the required
g21 of 5.5 mmho an amplifier bias current IABC of 20 IlA
is su itable.

9ZCS-19104

Fig. 17-2()'d8 amplifier using the CA3060.

Circuit Requirements
Closed loop voltage gain = 10 (20 dB)
Offset voltage adjustable to zero
Current drain as low as possible
Supply voltage = ±6 V
Maximum input voltage = ±50 mV
Input resistance = 20 kn
Load resistance = 20 kn
Device: CA3060
Calculation
1. Required transconductance 921.
Assume that the open loop gain AOL must be at least ten
times the closed loop gain. Therefore, the forward
transconductance required is given by
3-49

3. Determination of Output Swing Capability.
For a loop gain of 10 the output swing is ±0.5 V and the
peak load current 25 IlA. However, the amplifier must
also supply the necessary current through the feedback
resistor and for RS = 20 kn than RF = 200 kn if AOL =
10. Therefore, the feedback loading = 0.5/200 kn = 2.5 IlA.
The total amplifier current output requirements are,
therefore, ±27.5 IlA. Referring to the data given in Fig. 6a
we see that for an amplifier bias current of 20 IlA the
amplifier output current is ±40 IlA. This is obviously
adequate and it is not necessary to change the amplifier
bias current IABC.
4. Calculation of bias resistance.
For minimum supply current drain the amplifier bias current
IA8C should be fed directly from the supplies and not
from the bias regulator. The value of the resistor RABC
may be directly calculated using Ohm's law.

CA3060
Capacitive loading also has an effect on slew rate; because the
peak output current is established by the amplifier bias
current, IABC (see Fig. 6a), the maximum slew rate is limited
to the maximum rate at which the capacitance can be
charged by the 10M' Therefore,

R
-~
ABC - 20 x 10-6

SR
= 568_5 kn or ~ 560 kn

5. Calculation of offset adjustment circuit.
In order to reduce the loading effect of the offset
adjustment circuit on the power supply, the offset control
should be arranged to provide the necessary offset
current. The source resistance of the non-inverting input is
made equal to the source resistance of the inverting input.
20 x 200 x 106 ohms - 18 kn
220 x 103

i.e.

Because the maximum offset voltage is 5 mV and an
additional increment due to the offset current (Fig. 4)
flowing through the source resistance
(i.e. 200 x 10-9 x 18 x 103 volts I, therefore,
the Offset Voltage Range = 5 mV + 3.6 mV = ±8.6 mV
The current necessary to provide this offset is
8.S x 10-3
0 48 A
18x103 or. IJ.
With a supply voltage of ±S V, this current can be provided
by a 10 Mn resistor. However, the stability of such a resistor
is often questionable and a more realistic value of 2.2 Mn
was used in the final circuit.
OTHER CONSIDERATIONS
Capacitance Effects
The CA30S0 is designed to operate at such low power levels
that high impedance circuits must be employed. In designing
such circuits, particularly feedback amplifiers, stray circuit
.:apacitance must always be considered because of its adverse
effect on frequency response and stability. For example a
10-kn load with a stray capacitance of 15 pF has a time
constant of 1 MHz. Fig. 18 illustrates how a 10-kn 15-pF
load modifies the frequency characteristic.
o

=dV/dt = IOM/CL

where CL is the total load capacitance including strays. This
relationship is shown graphically in Fig. 19. When measuring
slew rate for this data bulletin; care was taken to keep the
total capacitive loading to 13 pF.
Phase Compensation
In many applications phase compensation will not be
required for the amplifiers of the CA3060. When needed,
compensation may easily be accomplished by a simple RC
network at the input of the amplifier as shown in Fig. 13.
The values given in Fig. 13 provide. stable operation for the
critical unity gain condition, assuming that capacitive loading
on the output is 13 pF or less. Input phase compensation is
recommended in order to maintain the highest possible slew
rate.
In applications such as integrators, two OTAs may be
cascaded to improve current gain. Compensation is best
accomplished in this case with a shunt capacitor at the
output of the first amplifier. The high gain following
compensation assures a high slew rate.
APPLICATIONS
Having determined the operating points of the CA30S0
amplifiers, they can now function in the same manner as
conventional op-amps, and thus, are well suited for. most
op-amp applications, including inverting and non-inverting
amplifiers, integrators, differentiators, summing amplifiers
etc.
TRI-LEVEL COMPARATOR
Tri-Ievel comparator circuits are an ideal application for the
CA30S0 since it contains the requisite three amplifiers. A
tri-Ievel comparator has three adjustable limits. If either the
upper or lower limit is exceeded, the appropriate output is
activated until the input signal returns. to a selected
intermediate limit. Tri-Ievel comparators are particularly
suited to many industrial control applications.
ouuvo

••

"i
0

-201f----1----"i<----f----i
m

:3
ffi

.

l'z

'"

~;;

~-40~--~~---+-_\~~~---i
>
;::

...
'""'

'

!:! 100.

.
.'"'"

.J

~

~

-601----1----+~~-_\---~

0

c

-eo
0.01

01

I
10
FREQUENCY If)-MHz

~~~VV
,.

•

•,
100

./

••
'/

••
0.01

~<.~'t-7

./

IL

0/

./

~~

Fig.T8-Effect of capacitive loading on frequency response.

~

~L

~

0" 17""

V
2

/
4

•

• .1

./

,

•• 0

/

~

,

4

68,

,

4

•

01)0

92CS-I~858

Fig. 19-Effect of load capacitance on slew rate.

3-50

V

o·

SLEW RATE (VI,.."

92CS-15884RI

L--"

i

~

,,':/
V

V

\.~~

0

c,'t-q'"

V

V

,0(;1"<

7'

/

I.

'/

100

L--"

V

CA3060
Circuit Description
Fig. 20 shows the block diagram of a trHevel comparator
using the CA3060. Two of the three amplifiers are used to
compare the input signal with the upper·limit and lower·
v+
V+
UPPER LIMIT
REFERENCE VOLTAGE
INPUT SIGNAL

----I

INTERMEDIATE-LIMIT
REFERENCE VOLTAGE
LOWER LIMIT
REFERENCE VOLTAGE

92CS-19609

Fig.20-Functional block diagram of a tri·level comparator.

limit reference voltages. The third amplifier is used to
compare the input signal with a selected value of intermediate-limit reference voltage. By appropriate selection or
resistance ratios this intermediate·limit may be set to any
voltage between the upper-limit and lower-limit values. The
output of the upper-limit and lower-limit comparator sets the
corresponding upper or lower-limit flip-flop. The activated
flip-flop retains its state until the third comparator (intermediate-limit) in the CA3060 initiates a reset function,
thereby indicating that the signal voltage has returned to the
intermediate-limit selected. The flip·flops employ two
CA3086 transistor-array IC's, with circuitry to provide
separate "SET" and "POSITIVE OUTPUT" terminals.

The circuit diagram of a tri-Ievel comparator appears in Fig.
21. Power is provided for the CA3060 via terminals 3 and 8
by ±6-volt supplies and the built-in regulator provides
amplifier-bias·current (I ABC) to the three amplifiers via
terminal 1. Lower-limit and upper-limit reference voltages are'
selected by appropriate adjustment of potentiometers R1
and R2, respectively. When resistors R3 and R4 are equal in
value (as shown). the intermediate-limit reference voltage is
automatically establ ished at a value midway between the
lower-limit and upper-limit values. Appropriate variation of
resistors R3 and R4 permits selection of other values of
intermediate·limit voltages. Input signal (ES) is applied to the
three comparators via terminals 5, 12, and 14. The "SET"
output lines trigger the appropriate flip-flop whenever the
input signal reaches a limit value. When the input signal
returns to an intermediate-value, the common flip·flop
"RESET" line is energized. The loads in the circuits, shown
in Fig. 21 are 5-V, 25-mA lamps.
Active Filters - Using the CA3060 as a Gyrator
The high output impedance of the OTAs makes the CA3060
ideally suited for use as a gyrator in active filter applications.
Fig. 22 shows two OTAs of the CA3060 connected as a
gyrator in an active filter circuit. The OTAs in this circuit can
make a 3-~F capacitor function as a floating 10-kilohenry
inductor across Terminals A and B. The measured a of 13 (at
a frequency of 1 Hz) of this inductor compares favorably
with a calculated a of 16. The 20-kilohm to 2-megohm
attenuators in this circuit extend the dynamic range of the
OTA by a factor of 100. The 100-kilohm potentiometer,
across V+ and V-, tunes the inductor by varying the g21 of
the OTAs, thereby changing the gyration resistance.

CA3086

INPUT SIGNALIEsl

"

EU

9

UPPER LIMIT
FLIP-FLOP
RESEr
WHEN INTERMEDIATE
REFERENCE LIMIT
IS REACHED

EU-EL
-2-

CA3086

SET

WHEN LOWER LIMIT
IS EXCEEDED
LOWER LIMIT
FLIP-FLOP

NOTE2· ES >Eu::QI(ON 1,02 (OFF)
LOWER- LI MIT

REFERENCE
VOLTAGE

ES< ElJ;El ::Q,(OFFI, Q 2(OFFI
ES < EL -02ION),C, (OFF)

NorE I :ITEMS IN SHADED AREAS ARE EXTERNAL
TO THE CA3086
RESISTANCE VALUES ARE IN OHMS
92CL- 19622

Fig.21- Tri-Ievel comparator circuit.

3-51

CA3060

20K

current (IABC) terminal of each amplifier should be
decreased to maintain 100 jJ.A of strobe-"ON" current at
this lower supply voltage. Second, the drain resistance for the
MOS/FET should be decreased to maintain the same value of
source current. The low cost dual·gate protected MOS/FET,
RCA-40841, may be used when operating at the low supply
voltage.
The phase compensation network consists of a single 390n
resistor and a l000-pF capacitor, located at the interface of
the CA3060 output and the MOS/FET gate. The bandwidth
of the system is 1.5 MHz and the slew rate is 0.3 volts!j.lsec.
The system slew rate is directly proportional to the value of
the phase compensation capacitor. Thus, with higher gain
settings where lower values of phase compensation capacitors
are possible, the slew rate is proportionally increased.

20K

12
AMP 2

NON LINEAR APPLICATIONS
AM Modulator (Two-Quadrant Multiplier)

2M

Iv-,

TERMINAL B

ALL RESISTANCE VALUES ARE IN OHMS
92CS-156SIRI

Fig.22- Two operational transconductance amplifiers of the
CA3060 connected as a gyrator in an active filter
circuit.
CA3060

2k
2k

2k

STROBE

2k
STROBE

Fig. 24 shows Amplifier No.3 of the CA3060 used in an AM
modulator or 2·quadrant multiplier circuit. When modulation
is applied to the amplifier bias input, Terminal B, and the
carrier frequency to the differential input, Terminal A, the
waveform, shown in Fig. 24, is obtained. Fig. 24 is a result of
adjusting the input offset control to balance the circuit so
that no modulation can occur at the output without a carrier
input. The linearity of the modulator is indicated by the
solid trace of the superimposed modulating frequency. The
maximum 'depth of modulation is determined by the ratio of
the peak input modulating voltage to V-:
The two-quadrant multiplier characteristic Of this modulator
is easily seen if modulation and carrier are reversed as shown
in Fig. 24. The polarity of the output must follow that of the
differential input; therefore, the output is positive only
during, the positive half cycle of the modulation and negative
only in the second half cycle. Note, that both the input and
output signals are referenced to ground. The output signal is
zero when either the differential input or IABC are zero.

2k
2k

'on

STROBE
STROBE 'OFF'

TERMINAL A

MODULATED
OUTPUT

+15V
-15 V

STROBF.
RESISTANCE VALUES ARE IN OHMS
92C5-19610 RI

Fig.23- Three·channel multiplexer.
THREE CHANNEL MULTIPLEXER
Fig. 23 shows a schematic of a three channel multiplexer
using a single CA3060 and a 3N 153 MOS/FET as a buffer
and power amplifier.

ALL RESISTANCE VALUES ARE
IN OHMS
92~S

-15863RI

When the CA3060 is connected as a high·input impedance
voltage follower, and strobe "ON," each amplifier is
activated and the output swings to the level of the input of
that amplifier. The cascade arrangement of each CA3060
amplifier with the MOS/FET provides an open loop voltage
gain in excess of 100 dB, thus assuring excellent accuracy in
the voltage follower mode with 100% feedback.
Operation at ±6 volts is also possible with several minor
changes. First, the resistance in series with amplifier bias

3-52

Fig.24- Two·quadrant multiplier circuit using the CA3060
with associated waveforms.

CA3060
Four-Quadrant Multiplier
The CA3060 is also useful as a four-quadrant multiplier. A
block diagram of such a multiplier, utilizing Amplifier Nos.
1, 2, and 3, is shown in Fig. 25 and a typical circuit is shown
in Fig. 26. The multiplier consists of a single CA3060 and, as
in the two-quadrant multiplier, exhibits no level shift
between input and output. In Fig. 25, Amplifier No. 1 is
connected as an inverting amplifier for the X-input signal.
The output current of Amplifier No. 1 is calculated as
follows:

+-.,---{2)k

xv

V
INPUT

(Eq.3)
Ampl. No.2 is a non-inverting amplifier so that
(Eq.4)

Fig. 25-Four-quadrant multiplier'using the CA3060.

Because the amplifier output impedances are high, the load
current is the sum of the two output currents, for an output
voltage
(Eq.5)
Va = VXRL [921(2)- 921(1)1

Figures 27b and 27c, respectively, show the squaring of a
triangular wave and a sine wave. Notice that in both cases the
outputs are always positive and return to zero after each
cycle.

The transconductance is approximately proportional to the
amplifier bias current; therefore, by varying the bias current
the g21 is also controlled. Amplifier No.2 bias current is
proportional to the V-input signal and is expressed as
(V-)+Vy
IABC(2) ""--R-1-

a:
"w::;;:

&<1:

Hence,
g21 (2) "" k [ (V-) + Vy

I.

(Eq.7)

10M

ALL RESISTANCE
VALUES ARE IN
OHMS

92CS-IS6S7R1

g21(1)""k [(V-)-Vyl.

(Eq.8)
Fig.26- Typical four-quadrant multiplier circuit.

Combining equation 5, 7, and 8 yields:
Va""Vx' k' RL I[(V-) + Vyl - [(V-)- Vyl! or

ov

Va"" 2 k RL Vx Vy
Fig. 26 shows the actual circuit including all the adjustments
associated with differential input and an adjustment for
equalizing the gains of Amplifiers No. 1 and No.2.
Adjustment of the circuit is quite simple. With both the X
and Y voltages at zero, connect Terminal 10 to Terminal 8.
This procedure disables Amplifier No. 2 and permits
adjusting the offset voltage of Amplifier No. 1 to zero by
means of the 100-kn potentiometer. Next, remove the short
between Terminals 10 and 8 and connect Terminal 15 to
Terminal 8. This step disables Amplifier No.1 and permits
Amplifier No.2 to be zeroed with the other potentiometer.
With AC signals on both the X and Y input, R3 and R 11 are
adjusted for symmetrical output signals. Fig. 27 shows the
output waveform with the multiplier adjusted. The voltage
waveform in Fig. 27a shows suppressed carrier modulation of
l-kHz carrier with a triangular wave.

en
za:

10
~

loao

:2

468

10000

Z

AMBIENT TEMPERATURE ITA1·25-C

V"

g100.~IT~A!"2~'!'Cnp~~f~~ijY!=!l!~~
CA3078

100

Fig. 4 - Input offset current vs. total quiescent
current.

~ ~
4

10

TOTAL QUIESCENT MICROAMPERES 1101

Fig. 3 -Input offset voltage vs. total quiescent
current.
:2 AMBIENT TEMPERATURE

.. 68

:2

1000

10
100
TOTAL QUIESCENT MICROAMPERES {Ial

4 SUPPlY VOL.TSV •• ,..6.V-'-6

--

,

~ ~~~-+~++--~~+++-~-+

~

B~~-+~++--~+++~+-I-+-J-j;l
z
~ 1261-+-1-+++---1-+-1-+-1-+--+-++1'"
~

~

lOB

LOAD RESISTANCE (RLI"1 MR

108

~

90

10KR

90

.0\:

54

~

,,1-+-1-+++-- l--iH+I---I-++--R

§ ~=!f-+-I-++--I-+~+- -12

01

,~+-+++~-+-+++~~~~-+~++~~
2

468

:2

2468

10

:2

468

100

1000

TOTAL QUIESCENT MICROAMPERES

o

468

468

10000

468

10
100
TOTAL aUIESCENT MICROAMPERES IIO)

1000
92CS~196291i1r

Fig. 5 - Input bias current vs. total quiescent
current.

001 ,

864:2
8642.
864:2
1000
100
10

8642

I

Fig. 6 - Open-loop voltage gain vs. total
quiescent current.

86428642.
8
01
001
0001

TOTAL QUIESCENT MICROAMPERESllol

01

2

468

10

468

2

488

100
TOTAL QUIESCENT MICROAMPERES (la'

1000

Fig. 8 - Maximum output current VS. total
quiescent current.

Fig. 7 - Bias-setting resistance VS. total
quiescent current.

3-57

~§

a: a..

,,~+-+~++--~+-I-+~+-+-l-+1

IIal

-'
ctcn

z: a:
OW
w:;;;

&ct

CA3078, CA3078A

~nrswuugul.U

120

I KR

100
80

~
~!i

100

~~40

~~ 20
SUPPLY VOLTS V+. +1.5, V-'-I.! I

L

~

AMBIENT TEMPERATUREIT,.lo 25·C
.~

~

W

~

01

TOTAL QUIESCENT MICROAMPERES tIOI

Fig. 10 - Open-loop voltage gain vs. frequency
fOrlO= 100/JA - CA3078.

Fig. 9 - Output voltage swing vs. total

quiescent current.

- Iocr. TOTAL QUIESCENT CURRENTlIQ1'20

120

po'"

100
80

~

0

~~I::--..'

~t'0~t~ ~

..
i!

40

g

20 CA3078A

~

OUIESCENT

60

~.

&g

~~

I'......~"'\

SUPPLY VOLTS.V+'6,V-'-6)~

&

CURRENTI~I'20,.A

0 LOAD RESISTANCE 'R )·Okn

~:~~~EI~M::~:T~:LESIT':':~C

- 0
01

""

10

I

~,

.

100

"

•

~

\

~
;3

:i

400

l\\ 1\
10

10'

~
~
10'

Fig. 12- Open·7oop voltage gain vs. frequency
for 10 = 20 /JA - CA3078.
1.75 SUPPLY VOLTS ~

y+. +6. V-'-6

"

CA5078

10"100 ",A

I-

CA3078A

075

10 " 20 Il-A

~

?

05

~025
-75

-50

-25

0

25

50

75

100

125

AMBIENT TEMPERATUREITAI-"C

Fig. 11 - Output and common-mode voltage
Fig. 13 - Input offset voltage VS. temperature.

vs. supply voltage.
SUPPLY VOL.TS:V

_+6,V-·-6

II.

~

3
!
IO~

I

"ii

8~
I

A3078

2

-50

-250
255075
AMBIENT TEMPERATURElTAI-"C

~

61

-IOOp.A

4

-5

!:!

~

I

i

SUPPLY VOLTS: v+

• +6, V-·-6

~

00

~

;j':""'.ta

IOO~

O"~8

10

..1

i

75 ~

75

~
50:1

C,'''

8
0"'60",.

m

~

~

125

:I

~

~

25 ~

2.

~

_

_

0

~

~

AMBIENT TEMPERATURE ITAJ -

~

~

~

~c

Fig. 15 - Input bias current VI. temperature.

Fig. 14 -Inputoffsetcurrent VS. temperature.

3-58

CA3078, CA3078A
SUPPLY VOLTS.

y+. +6, Y-·-6

I I IIOHfffiffiffiffim-tttttttttttl-H1f1trttHtttl-H1

~ 10'mlmmmttmim
IIIHmi
il [tttlttmttttHttt111
i

.rHIJ11~

100

+++++1++11++1++++++1

+'

Io o 20.uA- .

C~18

~

~ ~

III
~

~

10

~

eo
-50

-1$

-25

0

25

50

75

-TO

'"

100

AMBIENT TEMPERATURElTAI-"C

~~
~
~

-w

-20

,.

"

TO

AMBIENT TEMPERATURE (TA I - · C

Fig. 16 - Open·loop voltage gain vs.

100

Fig. 17- Total quiescent current vs.
temperature.

t-..

temperature.

c· "

6V,V-O-61t81t
1

100 AMBIENT
SUPPL.Y VOlTAGE:V
•• 11A1 0 25"C
TEMPERATURE

U.

•

.

___ _

_I.

~

' C A ' 0 7 8 A T ! ..
4
-SUPPL.Y CURRENT IIQloZ(\oA-

~

2~

IIIOOJA

~

+-

--'
<
---'V'\I\,..-<

I MEG ;>4-.J\)V\r--{

v-

vRI

Vdlueof RB reqUired to hdve a
nuliadiu~tmentr

,-5:;;

~
g

:~90

i

-21--I--ltT+I-+-+t+I-t-+-J-t+-If-H-H

j

v'" =+15, v-. -15

"0-lLl

o

+25

~ -31--I-A-t+i-+-+t+I-t-+-J-t+-If-H-H
~ -"'1-+11;1,,",,;o:.,,.c+t--t--l+t+--+-+-t1ct--t--++H
~ -'I-f--H
1II+t-l-I-+++--+-+++-I--I---Hrti

:;11

I1
z

0.1

,

1
.. ell

2:

001

.. 68

10
100
AMPLIFIER BIAS MICROAMPERES (lAecl

2

1000

t

0.1

..

88

..

68

I
10
100
AMPLIFIER BIAS MICROAMPERES IIABCI

1000

;:;g.3 - Input offset voltage as a function of
amplifier bias current.

Fig.4 - Input offset current as a function of
amplifier bias current.

10: SUPPLY VOLTS:V+'+l5.V-~-15

101; SUPPLY VOLTS: Y+'+15, Y-~-15

~

~

§
~

it
.. 68

0.1

468

I
10
100
AMPLIFIER BIAS MICROAMPERES IIABCI

.

,
,

IL

.1
461

1000

468

I
10
100
AMPLIFIER BIAS MICROAMPERES (IABCI

Fig.6 - Peak output current as a function of
amplifier bias current.

Fig.5 - Input bias current as a function of
amplifier bias current.

3-65

1000

CA3080, CA3080A
TYPICAL CHARACTERISTICS CURVES AND TEST CIRCUITS (Cont'd)

0.1

2
4".
2
I
/0
roo
AMPLIFIER BIAS MICROAMPERES IIABCI

2

4 6.

1000

0.1

Fig.7 - Peak output voltage as a function of
amplifier bias current.

•

4 I'

'0

100

1000

Fig.8 - Amplifier supplV current as a function
amplifier bias current.

10'
: AMBIENT TEMPERATURE (TA1~2~·C

I

4 ,.

I

AMPLIFIER BIAS MICROAMPERES (lABel

or

10', SUPPLY VOLTS:V+"'+15.V·.·,5

2 4._
I
10
100
AMPLIFIER BIAS MICROAMPERES (IABCI

...

1000

~I

Fig.9 - Total power dissipation as a function of
amplifier bias current.

Fig.

to -

-.

SUPPLY VOLTS:Y.... '5. Y-··15

··
·
! ··,
i ·
·

.36.

4

1000

100

Transconductance as a function of
amplifier bias current.

L

i

il
~

10

/'

I

...

E

·'"

.I!"
/'

"

V

L

Q

/'

0.1

.. D.OI

."".~~
""

.""~

~
~

Fig. II - Leakage current test circuit

... ...

~

I

AMPLIFIER BIAS MICROAMPERES «IABCI

/'

1L

L

"

00

100

125

AMBIENT TEMPERATURE (T.I-C·

Fig. 12 - Leakage current as a function of temperature.
SUPPLY VOLTS:V "+e,v-a-I'

V-,.·15V

I

Fig. 13 - Differential input current test circuit

2

:5

"

INPUT OIFFtRENTIAL VOLTS

Fig. 14 -Inputcurrentas a function of
input differential voltage.

3-66

CA30BO, CA30BOA
TYPICAL CHARACTERISTICS CURVES AND TEST CIRCUITS (Cont'd)
SUPPLY VOLTS: V.... +15, v-. -15
AMBIENT TEMPERATURE t TAI'2S'C

900 SUPPL.Y VOLTS;V+.+I!I. \1-'-15

I

-y

!eoo~+-~~--t-+=bY~~+9~~~~-H

;

7oo'F-~9FfTr-+-~rH~±7~~~~~RH

~600r-t-~HH~~~H1~r-~HH--r-~-H
i 5oo~~~HH--t-+-rH~~+-~~~~-H

! 400't--+--r++t--t-~~~~~rtt--t-+-t-H
~ 300't--~~tf~t-~tHt--t-~rtt--t-+-t-H

~ 200'~~-i--t-ttr-t~-tH--t~-tH--t~-t-H
,
~

..

IOO't-+-+++r-+-~rHr-t-~t+r-r-+-1+I
2:

a.,

.. 68
10

I

2

a.,

".8

100

1000

•

10

"6.
100

1000

AMPLIFIER BIAS MICROAMPERES I lABel

AMPLIFIER BIAS MICROAMPERES LIASCI

Fig. 15 - Input resistance as a function of
amplifier bias current.

Fig. 16 - Amplifier bias voltage as a function of
amplifier bias current.

1 SUPPLY VOLTS: \/+'+15,\1"'-15
..... SIENT TEMPERATURE ITA'. 25'C
f"REQUENCY IIlo'MHI

...J

o-l-V\,I\r-...J

601 H,

ALL RESISTORS lIZ WATT
UNLESS OTHERWISE SPECIFIED

Fig.29 - Thermocouple temperature con trol with CA3079 zero voltage switch as
the vutput amplifier.

3-69

CA30BO, CA30BOA
+7.5

.,
INPUT

2 K

i

SAMPLE

OV]f_
STROBE

HOLD

15 K

-7.5

Fig.30 - Schematic diagram of the CA3080A in a sample·
hold circuit with SiMas output amplifier.

TOP TRACE: OUTPUT-20 mV/DIV. a 100 ns/DIY.
BOTTOM TRACE: INPUT-200 mV/DIY. a 10D nI/DIV.

TOP TRACE: aUTPUT-5V/DIV. 8 21's/0IV.
CENTER TRACE: 01 FFERENTIAL COMPARISON OF

e. OUTPUT-2mVlDIV. 6: 2,.,.s/0IY
TRACE: INPUT-5 V/OIV. a 2,u.s/DlY
INPUT

BOTTOM

Fig.31 - Large-signal response for circuit shown
in Fig. 30.

Fig.32 - Small-signal response for circuit shown

in Fig. 30.
V t '15V

50

m~_..r:1._ IN

-50 mV

J-L

OUT

.r=t.. r:::J...,

;)-

zc::

ow
~§
c:: "w::;;;

&«

CA3094,CA3094A,CA30948
ELECTRICAL CHARACTERISTICS at T A'" 25·C For Equipment Design

CHARACTERISTIC

LIMITS

TEST CONDITIONS
Single Supply y+ = 30 Y
Dual Supply y+ = 15 Y.
Y-= 15Y

Min. Typ.

Max.

UNITS

IABC· 100p.A
Unless Otherwise
Specified
INPUT PARAMETERS

TA=250 C

Input Offset Voltage

VIO

Input-Offset-Voltage Change

I[Wlol

TA = Oto

700 C

-

0.4.

5

mV

-

-

7

mV

8

mV

Change in VIO

-

1

-

0.02

0.2

p.A

TA = 0 to 70 0 C

-

0.3

p.A

TA = 25 0 C

-

0.2

0.50

p.A

TA = 0 to 700 C

-

-

0.70

p.A

Between IABC = 100 p.A
and IABC = 5 p.A
TA=250 C

Input Offset Current

110

Input Bias Current

II

Device Dissipation

Po

lout = 0

Common-Mode Rejection Ratio CMRR
V+ = 30 V
Common-Mode InputVICR

Voltage Range

High
low

8

10

12

mW

70

110

-

dB

27

28.8

1.0

0.5

-

V+ = 15 V

+12 +13.8

V-= 15 V

-14 -14.5

V
V
V
V

IC= 7.5 mA
Unity Gain-Bandwidth

VCE = 15 V

-

30

-

MHz

-

4

-

kHz

-

0.4

-

1.4

-

%

-

0.68

-

V

IABC= 500p.A
Ic=7.5mA

Open-loop Bandwidth

BWOl VCE=15V

At -3 dB Point

IABC = 500p.A
Total Harmonic Distortion
(Class A Operation)

THO

PD= 220 mW
Po = 600 mW

Amplifier Bias Voltage

VABC
(Terminal (No.5 to Terminal No.4)

Input Offset Voltage

tN I 0/In

Temperature Coefficient
Power-Supply Rejection

tNIO/!'J.\J
f = 10 Hz

l/F Noise Voltage

EN

l/F Noise Current

IN

Differential Input Resistance

RI

Differential I nput Capacitance

CI

IABC= 50p.A
f = 10 Hz
IABC = 50 jI.A
IABC= 20/lA
f = 1 MHz

V+= 30 V

3-72

p.v/oc

-

4

-

-

15

150

-

18

-

T/V/JHz

-

1.8

-

PA/iiZ

1

-

Mn

2.6

-

pF

0.50

-

/lVjv

CA309~CA3094A,CA3094B

ELECTRICAL CHARACTERISTICS at T A = 25°C For Equipment Design
TEST CONDITIONS

LIMITS

Single Supply V+ = 30 V
Dual Supply V+ = 15 V,
V- = 15 V

CHARACTERISTIC

Min.

Typ.

26

27
0.01

Max.

UNITS

IABC= 100j.LA
Unless Otherwise
Specified

OUTPUT PARAMETERS (Differential Input Voltage = 1VI
Peak Output Voltage:
(Terminal No.6)
V+OM
With 013 "ON"
With 013 "OFF" V-OM
Peak Output Voltage:
(Terminal No.6)
Positive
V+OM
V-OM
Negative
Peak Output Voltage.:
(Terminal No.8)
V+OM
With 013 "ON"
With 013 "OFF" V-OM
Peak Output Voltage:
(Terminal No.8)
V+OM
Positive
V-OM
Negative
Collector·to·Emitter
Saturation Voltage
(Terminal No.8) VCE(sat)
Output Leakage Current
(Terminal No.6 to
Terminal No.4)
Composite Small·Signal
Current Transfer Ratio (Beta)
(d12 and 013)
hfe
Output Capacitance:
Terminal No.6
Co
Terminal No.8

V+ = 30 V
RL = 2 kn to ground

V+=+15V,V-=-15V
RL=2kHto-15V

+11

-

+12
-14.99

0.05
0.5

-14.95

V
V

V
V

za:

RL=2kHt030V
V+=15V.V-=-15V
RL=2kSlto+15V

29.95
-

29.99
0.040

-

+14.99
14.96

V+-30 V
IC= 50mA
Terminal No.6 grounded

-

0.17

V+ = 30 V

-

2

V+= 30 V
VCE = 5 V
Ic=50mA
f= 1 MHz
All Remaining
Terminals Tied to
Terminal No.4

+14.95

-

-

V
V

-

V
V

0.80

V

10

j.LA

100,000

-

-

5.5
17

-

pF
pF

20,000

100,000

-

V/V

86

100

-

dB

1650

2200

2750

IABC= 500j.LA
RL = 2 kn

-

500
50

-

-

-

V/j.Ls
V/j.Ls

IABC= 500j.LA
RL = 2 kn

-

0.7

-

V/j.Ls

, 16,000

TRANSFER PARAMETERS

Voltage Gain

A

Forward Transconductance
gm
To Terminal No.1
Slew Rate:
Open Loop:
Positive Slope
Negative Slope
Unity Gain
(Non-Inverting,
Compensated)

-'
«tI)
OW

V+ = 30 V

V+= 30 V
IABC= 100j.LA
6V out = 20 V
RL =2 kSl

3-73

j.Lmhos

~§

a: a..

w:;;
~«

CA3094,CA3094A,CA3094B
MAXIMUM RATINGS. Absolute-MaKimum Values:
DC SUPPL Y VOLTAGE:
Oual Supply ................................. .
Single Supply ............................... .
DC DIFFERENTIAL INPUT VOLTAGE
(Terminals 2 and 3) .......................... .
DC COMMON·MODE INPUT VOLTAGE •.............
PEAK INPUT SIGNAL CURRENT
(Terminals 2 and 3) ........................... .
PEAK AMPLIFIER BIAS CURRENT
(Terminal 5) ................................ .
OUTPUT CURRENT:

CA3094

CA3094A

CA30948

± 12V
24V

± 18V
36V

±22V
44V

V
V

± 5"

Term. 4

V

< Term. 2 &. 3 < Term. 7
+ 1·

mA
mA

Peak ....................................... .
Average ..............................•......
DEVICE DISSIPATION:
Up to TA = 550C:
Without heat sink .......................... .
........................... .
With heat sink
Above T A = 55°C:
Without heat sink derate linearlv
............. .
With heat sink derate linearly
THERMAL RESISTANCE
(Junction to Air) .............................. .
AMBIENT TEMPERATURE RANGE:
Operating ................................... .
Storage .......•...............................
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 in. (1.59 ± 0.79 mm)
from case for 10 5 max.

300
100

mA
mA

630
1.6

mW
W

6.67
16.7

mW/oC

140

oCIW

mW/oC

551o +125
-6510+150

°C
°C

+ 300

°C

·Exceeding thiS voltage rating will not damage the device unless the pea'" input signal current t 1 mA) IS also exceeded.

TYPICAL CHARACTERISTICS CURVES
SUPPLY VOLTS:V -+15,

0.'

2:

.. 61

V-~-15

2:
.. 61
2:
I
10
100
AMPLIFIER BIAS MICROAMPERES I !ABC I

101: SUPPLY VOLTS: V+=+15, V-·-15

..

61

1000

Fig.2 - Input offset voltage vs. amplifier bias
current (J ABC. terminal No.5).

0.'

.. 61

... 1

I
10
tOO
AMPLIFIER BIAS MICROAMPERES (lABel

Fig.3 - Input offset current VS'. amplifier bias
current (IABC- terminal No.5).

3-74

1000

CA309~CA3094A,CA3094B

TYPICAL CHARACTERISTICS CURVES (Cont'd)

.

[;:~i;iS~UPi~~'j~~ni'~'Vl'i+l"i'Vj-'j-il5~~III1~il;!1
.

10: AMBIENT TEMPERATURE t TA'025.C

.

";.103

!:!

:. 10"

•

~

~

!

102•

~

10:

~

Z

i "
• I
0.1

··

~
"I'
0'....... I

Z

0,1

2.

10

10

V

"51

100

2

1000

0.1

"SI

"&11

I

AMPLlFI£R 81AS MICROAMPERES IIASC'

10

100

1000

AMPLIFIER BIAS CURRENTllA8CI-}"A

Fig.5 - Device dissipation vs. amplifier bias

Fig.4 - Input bias current vs. amplifier bias

current (lABe. terminal No.51.

current (IABC. terminal No.51.

15
--15
14.5~A~.~BI;EN~T;TFE·RP:E:RAFT=UR~E~I~TA~":'~"~ClnGt~~
I• I.
.,1
~
f ""I-+-+-t-H-I-+-t-++--t-1H-++--I-~"1'1Ft
SUPPLY VOLTS:\I+.+IS,V-

_+I!),Y-._15

;

131t-1-~+++-+-4-~~+-+44+-4-~~

~
~

13..51-+-+H-I-j-.J-jH+--If--I-++I--+---l+l-141-+-+++I-l-+-IH+-1r---f-++I--+-l--t+,
V-CIIIR
3-14.51-+-+++I-t--Hftt-1f--I-t*!..f-!!!!"~
~

Z

0.1

"SI

Z

I
10
AMPLIFIER BIAS CURRENT

"

...

••

100

I I

2

0.1

1000

IrABCJ-~A

Fig.6 - Amplifier supply current vs. amplifier
bias current (I ABC. terminal No.51.

..

4

6.

2

4

6 I

I
10
100
AMPLIFIER BIAS CURRENT ClABC I-}"A

1000

Fig.7 - Common mode input voltage vs. amplifier
bias current (I ABC, terminal No.51.

>C

~

SUPPlY VOlTAGE 'V+I.~I:5 v,tV'--'5v
SOURCE RESISTANCE CRs"OO

f ::~-I

~

~
~

~
-

-

AMBIENT TEMPERATURE IT""25·C
FOR TEST CIRCUIT, SEE FIG 21

,o~""",,.... l

i

",..

""""........,;,;,;,~URR£... ~I1ABC.I.~

"

...... r--..,.

'0

"

r--

'0

100,.•

. ..,

~

'0

1--1-

~

..

• c'

'0

I

10

6

1105

Fig.9 - IIF Noise current vs. frequency.

Fig.8 - IIF Noise voltage vs. frequency.
.JV""""'e

,

FREQUENCY ttl-H.

FREQUENCY It I-HI

1000:

fORCED BETA 0'0

L--+--7-~'~'~'~'O~-t-t'-'~'oo~-7-4-~~ooo
COLLECTOR MILLIAMPERES IICI-mA

COLLECTOR CURRENT tIC'"mA

Fig. 11 - Composite dc beta vs. collector currenr
of Darlington-connected output tran-

Fig. TO - Collector-emitter saturation voltage
VS. collector current of output transistor Q'3-

sistors (0,2. 0,31.

3-75

-'
r=·'l<'-=_.-I-IOO ~

+ ->r-I--'-\-I-I~

.
.

~ 10':'

-t-''''-'It---''''-t---''ct---j-OO I

~oof---!---t--t­

~

~

o

~

-ZOO~

2

-'0

I

....
100

10

2

.. , .
1000

AMPLIFIER 81AS IJIrCROAMPERES (:lABel

10

Fig. 13 - Forward transconductance

VI

amplifier bias current.

Fig_12 - Open-loop voltage gain vs_ frequency_

100, SUPPLY VOLTAGE 1..,+1-+1''', Iv-l--I'"
, AMPLIFIER BIAS CURRENT lI,lIe,e,OO,. ..
.. AMBIENT T[MPERATURE ITAI-!,·C
FOR TEST CIRCUIT SEE fiG 24

~

.
• ,
.
~

10,

5
~

I

0.1
4

6 810

4 6 1 100

• '<>00

20

40

60

80

100

CLOSED-LOOP VOLTAGE GAIN 1ACl.)- dB

AMPLIFIER BIAS CURRENT {lAse1-,.A

Fig. 14 - Slew rate vs amplifier bias current.

Fig_15 - Slew rate vs closed-loop voltage gain_

Fig. 16 - Phase compensation capacitance and
resistance VI closed.Joop voltage gain.

OPERATING CONSIDERATIONS
The "Sink" Output (terminal No_8) and the
"Drive" Output (terminal No_6) of the
CA3094 are not inherently current (or power)
limited_ Therefore, if a load is connected
between terminal No_6 and terminal No.4
(V- or ground), it is important to connect a
current-limiting resistor between terminal
8 and terminal No-_7 (V+) to protect transistor Q13 under shorted load conditions_
Similarly, if a load is connected between
terminal No_8and terminal No_7, the currentlimiting resistor should be connected between terminal No_6 and terminal No.4 or
ground_ In circuit applications where the
emitter of the output transistor is not connected to the most negative potential in
the system, it is recommended that a 100ohm current-limiting resistor be inserted between terminal No_7 and the V+ supply_

3-76

TEST CIRCUITS
IIF Noise Measurement Circuit
When using the CA3094, A, or B audio amplifier circuits, it is frequently necessary to
consider the noise performance of the device_ Noise measurements are made in the
circuit shown in Fig_21_ This circuh -is a
3D-dB, non-inverting amplifier with emitterfollower output and phase compensation
from terminal No_2 to ground_ Source resistors (Rs) are set to
or 1
for
E noise and I noise measurements, respectively_ These measurements are made at
frequencies of 10, Hz, 100 Hz, and 1 kHz
with a 1-Hz measurement bandwidth_ Typical values for 1/f noise at 10 Hz and 50/J-A
IABC are En = 18 nV!JWl and IN = 1.8
PA/.,jFf£-

o_n

Mn

CA309~CA3094A,CA3094B

TEST CI RCUITS
+30Y

IN'UTOHSUVOLfAGE

v,o.t~::
fOAI'OWEASUPPLV

REUCTIOfIITEST
IUVA"YV·SV-lVOLT$,
THEN 121 VARY 10'-1'1

IMO

'ZVOLT$
EQUATIONS
mY·REJECTiONEQOUT~E' OUT

(ZIV-AEJECTlONEOOUT-f20UT

150Kfi

'"

fOWfA SUl'Pl Y REJECTION

~100&:f

EOUT

'MAXIMUM READING OF
SYE'IOFISTEPZ

tlSV

[OUT

(118] -20LOG V'*uECTION'

+3010'

. 15V_..J----I====~--.o
P01SS1PATION'IVt'III

Fig. 11 - Input offset voltage and power·supply

rejection test circuit.

EOUT
OHSEr CURRENT reS '10 6

~~;~

Fig.1S - Input offset current test circuit.
+3010'

IOKfi

-'
«en
za:

Ow

~~
w:;;

&«
+1510'

+1510'

-----+,----,-----'

CMRR·I~
[ZOUT-EIOUT

Fig. 19 - Input bias current test circuit.

I

I

INPUT VOLTAGE RANGE fOR eMRR" TO 21V

CMRRldB\-ZOLOG

I~
EZQUT-EIOUT

Fig.20 - Common-mode range and rejection ratio
test circuit.
tl5V

R,

3eKn

R,·

IOKa

.'5V

.-

R,

IABC

".

.00

n

'60'

.0

".

1200
RS '~Nrt NOISE vOLTAGE

OUTPUT (R"'5)

"0
-1510'

Fig.21 - IIF noise test circuit.

Fig.22 - Open-loop gain vs frequency test circuit.

EOUT

tOUT

-15'01

Fig.23 - Open-loop slew rate vs IABC test circuit.

Fig.24 - Slew rate vs. non-inverting unity gain
test circuit.

3-77

CA309~CA3094A,CA3094B

TEST CIRCUITS (Cont'd)
120 VAC

RL~O 1
'I"'

CLOSED

LOOP
GAIN
dB

20

'0

C

10

10

'0

01

RCA

40529

10

COMMON
CI·O.5~F

",_-1____

DI .. IN914

-I'V

AI: 0.51 Mn"'3MIN.
H2"' 5·1 M,n·30 MIN.
R3"' 22MJl:2HRS.
R4~ 44M.n-4HRS.

Fig.25 - Phase compensation test circuit.

R5"' '.5 K.n
R6- 50K.n
R7~ 5.IK.n
Re"' 1.5K.n

*

POTENTIOMETER REQUIRED FOR INITIAL TIME SET
TO PERMIT DEVICE INTERCONNECTING TIME VARIATION
WITH TEMPERATURE < 0.3'"

,-c.

Fig.26 - Presettable analog timer.

TYPICAL APPLICATIONS
For .Additional Application Information, reo
fer ..to Application Note ICAN·6048 "Some
'" Applications of a Programmable Powerl
Switch Amplifier IC".
Design Considerations
The selection of the optimum amplifier bias
current (I ABC) depends on 1. The Desired Sensitivity· - the higher the
IABC. the higher the sensitivity - i.e .• a
greater·drive current capability at the out·
put for a specific voltage change at
the input.

2. Required Input Resistance - the lower
the IABC. the higher the input resistance.
If the desired sensitivity and requred input
resistance are not known and are to be ex·
perimentally determined. or the anticipated
equipment design is sufficiently flexible to
tolerate a wide range of these parameters. it
is recommended that the equipment designer
begin his calculations with an IABC of 100
/lA. since the CA3094 is Characterized at
this value of amplifier bias current.
The CA3094 is extremely versatile and can
be used in a wide variety of applications.
IN A NON~INV[RTING MODE
AS A FOLLOWER

~-JVV~-~~+

z,

CA3094

1

"N

WHERE

:~~T .. f (*1

EOUT*

WHERE [OUT"' EIN
DEPENDS ON THE

*'N SINGlE~ ENDED OUTPUT OPERATION. THE CA3094
MAY REQUIRE A PUU UP OR PULL DOWN RESISTOR

CHARACTERISTICS OF II AND Z2

101

(01.

Fig.27 - Application of the CA3094: (a) a. an inverting op-amp. and
(b) in a non·inverting mode. a. a follower.

v" -IBV

51

~~~-~--~~-,

,

2/3V+-- ---~

o~i

VOLTAGE A

I

+1~==rL
VOLTAGE AT TERMINAL

Problem: To calculate the maximum value of R
required to switch a 100-mA output current
comparator
Given:
IABC = SjJA. RABC = 3.6MIl""~~
II = SOO nA@IABc=l00jJA(from Fig.4)
II = S jJA can be determined by drawing a line on
Fig.4 through I ABC = 100 jJA and I B = 500 nA
parallel to the typical T A = 2SoC curve.
Then:
II = 33 nA @ IABC = S jJA

N~.

Rmax =

TIME DElAY ISECONDSI-RC APPRCJX. "='"

18~::0It. = 180 Mil @TA=25 0C

Rmax = 180 Mil x 2/3* = 120 MO@
--TA = -55°C
* Ratio of II at TA = +250 C to II at TA = -55°C
for any given value of I ABC.
Fig.2JJ - RC timer.

3-78

CA309~CA3094A,CA3094B

TYPICAL APPLICATIONS (Cant'd)

..

v'

o---~--~--~--~--~

,.,

INPUT

v'

AO_~

HOleD

.o~

D.O_IIF a

A

K.
""

100KO

CO

.CA

12VOC

~~-----

_ __ _

DO'~

44003

E~~_______________

100KO

1001C0

v-o---.l~-""'--+----'------'

At the end of the time constant determined by Cl.

On a negative-going transient at input (AI. a
negative pulse at C will turn "on" the CA3094,
and the output (E) will go from a low to a high
level.

Rl. R2. R3. the CA3094 will return to the "off"
state and the output will be pulled low by
A LOAD. This condition will be independent of
the interval when input A .eturns to a high level.

Fig.29 - Re timer triggered by external negative pulse.

...J


za:
Ow

~§

a: c..

TYPE

LN914

w:;;;
~76 dB

±12

+14
-13

-

V

VI Common Mode = ± 12 V

76

90

-

dB

+9

+11

-9

-11

-

V

Differential Input Voltage = 0

V

Differential Input Voltage =0 ±O.1 V

RL

Negative, 10M

± 0.1

RL = 2 KIl

=250 Sl

VO=OiO.l V,RL210KSl

Supply Current. 1+

Power·Supply

Rejection Ratlo,PSRR

/';V+

=.±

lV,fW' =:t lV

+15

+30

-

-15

-30

-

rnA

-

8.5

10.5

rnA

60

70

-

dB

-

38

-

MHz

36

42

-

dB

50

70

-

-

25

-

DYNAMIC
Unlty·Galn
Crossover Frequency, fT
l·MHz Open-Loop

Cc
f

Voltage Galn.AOL

= O.

Vo

= 1 MHz.

Slew Rate, SR:
20·dB Amplifier

AV

Follower Mode

AV

=03 V (P·PI

Cc

= 0,

Vo

= 10 V

{P.PI

= 10. CC: 0, VI = 1 V {Pulsel
= 1. Cc = 10 pF. VI =10 V {Pulsel

V/Ms

Power Bandwidth, PBW·:
20-dB Amplifier

AV= 10. CC: O. Vo = 18 V {p·PI

Follower Mode

AV = 1. Cc

= 10 pF. Vo =18 V (P·PI

0.8

1.2

-

-

0.4

-

MHz

Open-Loop Differential
Input Impedance, 21

F

= 1 MHz

-

30

-

Kn

Open-Loop
Output Impedance, Zo

F = 1 MHz

-

110

-

n

-

8

-

MVRMS

-

0.6

-

MS

Wideband Noise Voltage Relerred to Input, eNlTotal)

BW

= 1 MHz. RS

RL

=2

= 1 KIl

Settling Time, ts
[TO Within ± 50 mV of 9 V

KIl. CL

= 20 pF

Output SWing
.. Power BandWidth = Slew Rate

• Low-frequency dynamic characteristic

TrVO (P-P)

3-83

CA3100
MAXIMUM RATINGS, Absolute-Maximum Values:
Supply Voltage (between V+ and V- terminals).
Differential Input Voltage.
Input Voltage to Ground· •
Offset Terminal to V- Terminal Voltage.
Output Current .

36
±12
±15
:10.5
50

V
V
V
V
mA-

630
6.67

mW
mWtC

Device Dissipatio"d

Up to T A = 55 oF
AboveT A =55 C

Ambient Temperature Range:
Operating:
E and M Types .

Sand TTypes
Storage

.

-40 to +85
-55 to +125
-65 to +150

°c
°c
°c

+265

°c

Lead Temperature (During Soldering):

At distance 1/16 ± 1/32 inch (1.59 ±0.79 mml from case for 10 s max ..

* If the supply voltage is less than ±15 volts, the maximum input voltage to ground is equal to the supply

voltage.
• CA3l 00 does not contain circuitry to protect against shart circuits in the output.

TYPICAL CHARACTERISTIC CURVES
SUPPl.Y VOLTAGE IV • Y-'"" v
COMPENSATION CAPACITANCE {tcloO

7

rg

~ ~~JJl= I

50

!

40r-

~
g

'0

--

~

~

10

0001

""

,

.,

,

~Ol

.

OMPENSATION CAPACITANCE (Cc)-

50

~

40

~
g

,0

~

20

~

T

r--~ '~~J

N.'V~.

~

~
~

i

LOAD CAPACITANCE !CL)'ZO pF

I

Zi

I

t-I-t.

~20
~

~

.

. . ,.

, " , " , "
001

"

f\~'\
,

15

11
~

10

i

5

3

~12~

7.

'0
1

25

~

I~ .~>J:.+----

10

'",>:

'> !ti"

"'C¥,,,.,,
'''1.'$"
IOV
10

20

t.lONINVERTING GAIN-dB

~OO

0

6

INVERTING GAIN -

101

dB

CLOSED-LOOP GAIN (Aul-dB

FRECUENCY {fI-MHz

Fig. 4 - Open-loop gain vso frequency and supply
voltage.

Fig. 5 - Require" compensation capacitance vs.
closed-loop gain.
o

AMBIENT TEMPERATURE (TAI-2.S"C :::: ;::: -:-;:: ;:.:.: :.::: ::.::
LOAO RESISTANCE (RLJ'2 Kg
---- .....•.• -•• - -._- .-

LOAD CAPACITANCE (CL'o20pF

~

. .

, " , " , ~, ~O

AMBIENT TEt.FER4TURE ITAI02S·C
LOAD RESISTANCE {RL.l-2 Kg
LOAD CAPACITANCE (CL.,,20pF

~

~:~~;ES~;;~~~ ~:1~2itri'2 j.[;

t-.f'I~1

hl

Fig. 3 - Open-loop gain vs. frequency and
temperature.
.

frequency.

60

., '01

- -

FREQUENCY Ifl-MH!

FREQUENCY I' I-MHz

Fig. 2 - Open-loop gain. open-loop phase shift vs.

rg

-

p:

r;:.

20

~

r-

\.~
~
~'1l"',

-- --

I-

~

10

L.OAD RESISTANCE (RL,02 Kfi

60

~~~ ::~: ~:~: ~~ ~~~ ;~

~

1

AMBIENT TEMPERATURE ITA)'25.C
SUPPLY VOLTAGE IV~V-)'15V

300

~

~

i 200
s
~

c~
2

~

=-

~

-

~~~o

'5'

CA3

~""

54

I

-.'
~'::f:~~~

-15V..2..

AOJUST FOR
Vo~OtOIVOC

10

15

°

20

10

20

30

'0

FREQUENCY In-MHz

COMPENSATION CAPACITANCE (Ce I PINS I TO 8-pF

Fig. 6 - Slew rate

v£

Fig. 7 - Typical open-loop output impedance vso
frequency.

compensation capacitance.

3-84

CA3100

..,.

TYPICAL CHARACTERISTIC CURVES (Cont'd)
30 A~BIENT TEMPERATURE {TA)'Z5"C

I

BANDWIDTH IBWI AT 6dB'IMHl

~

~g

.

10~e

~

~
6

;
~I
"'"

f'.

10~

,

~ ,
i\ '0'

B 10'

'"

,

~

C:-:~

T

'c,~

i

ZOI--f----

:~:~~~\~~~:::::~.R:.~:~~'~S'C t-

6
IC :

,I

III, ,

SOURCE RESISTANCE IRsl-n

,

-

-

i

i
I

it.

If

0- i'.,

, '0

,

,"

FREOUENCY (f)-104Hz

Fig, 8 - Wideband input noise voltage vs. source
resistance.

Fig. 9 - Typical open-loop differential input
impedance vs. frequency.

--'
«en

zc:

Ow

~§

c: c...
w::;;:

g,«
±2S

:!:.s

±75

:!:.IO

±125

±IS

=175

±20

SUPPLY VOLTAGE {V",V-)-V
FREOUENCYlf)-MHz

Fig, 10 - Maximum output voltage swing vs.
frequency.

Fig. 11 - Common-mode input voltage range vs.
supply voltage.
AMBIENT TEMPERATURE IT,.;1_·25·C

I

I

,~

1
Z-IZ5
~
g

10

"ii

75

1 125

~

10

G 75

§

.

rJ

2

~

5

>

25

~

:!:.Z5

:!:.5

::75

:!:.IO

S

=75

!;15

±12S

±IO

±12S

±IS

SUPPLY VOLTAGElv",V-I-V

SUPPLY VOLTAGE (V",V-I-v

Fig, 12 - Maximum output voltage vs. supply
voltage.

Fig. 13 - Supply current vs. supply voltage.

AMBIENT TEMPERATURE (TA)'2S"C

05

!;S

±12S

!;15

SUPPLY VOLTAGE Iv",V-I-V

Fig. 14 - Input bias current vs. supply voltage.

3-85

CA3100
TEST CIRCUITS
y'

RX~O.Ij.F
NULL '~~fu;T
POTENTIOMETER

AT fREOUENCY>IMHI "1 8110
MEASURED WITH HP8405A

VECTOR VOLTMETER

Fig. 15 - Open-loop voltage gain test circuit.

Fig. 17 - Follower slew rate test circuit.

Fig. 16 - Slew rate in TOX amp/ifier test circuit.

Fig. 18 - Wideband input noise voltage test
circuit.
I,F

SETTLING POINT

Fig. 19 - Output voltage swing (VOM)' output
current swing (J OM' test circuit.

to

SCOPE

Fig. 20 - Settling time test circuit

TYPICAL APPLICATIONS

3d8 BANDWIDTH'15MHz

CLG'2DdB

OUTPut TO
TERMINATED

,on

TRANSMISSION
LINE

OUTPUT

-3d8 BANOWIOTH:::f20MHI

.,F

TOTAL INPUT NOISE
VOLTAGE REFERRED TO INPUT
%3'-"VRMS
GAIN-20dS

Fig. 22 - 20 dB video line driver.

Fig. 21 - 20 dB video amplifier.

3-86

CA3100
TYPICAL APPLICATIONS (Cont'd)

INPUT IMPEDANCE
~~OI(!1

TEST
VI lAC}

LEADS

IrnA fULL
SCALE DC
METER

-=fULL

SCALE

CALIBRATION
ADJUST

Fig. 23 - Fast positive peak detector.

Fig. 24 - 1 MHz meter-driver amplifier.

-'
' •

"~
~

4

~ ,

~

§

2

~l-~".

8J~~~o
~t;~;M
~ ~'" e:.""

II
. ~~t1I!
Gl,mmm VO~AGE
DC

I

~AC=::u~E:oML~A~Ea. e!i~ ~
1000

1500 2000 21500 3000
TIME ttl-HOURS

I

!

.

I

"

Iii!
3!1OO 4000

Fig. 13 - Typical incremental offset-voltage shift
vs. operating life.

100

2c----

AMBlE
N~
T

sao

>-

6

~

7

f•

100

120

140

AMBIENT TEMPERATURE (TAI--C

Fig. 12 - Input current vs. ambient temperature.

In applications requiring the lowest practical
input current and incremental increases in
current because of "warm-up" effects, it is
suggested that an appropriate heat sink be
used with the CA3130. In addition, when
"sinking" or "sourcing" significant output
current the chip temperature increases,
causing an increase in the input current. In
such cases, heat-sinking can also very markedly reduce and stabi! ize input current
variations.
Input-Offset-Voltage (VIol Variation with
DC Bias vs_ Device Operating Life
It is well known that the characteristics of a
MOS/FET device can change slightly when a
dc gate-source bias potential is appl ied to the
device for extended time periods. The magni-

3-94

Power-Supply Considerations
Because the CA3130 is very useful in singlesupply applications, it is pertinent to review
some considerations relating to power-supply
current consumption under both single- and
dual-supply service. Figs. 14a and 14b show
the CA3130 connected for both dual- and
single-supply operation.
Dual-supply operation: When the output
voltage at Term. 6 is zero-volts, the currents
suppl ied by the two power supplies are equal.
When the gate terminals of 08 and 012 are
driven increasingly positive with respect to
ground, current flow through 012 (from the
negative supply) to the load is increased and
current flow through 08 (from the positive
supply) decreases correspondingly. When the
gate terminals of OS and 012 are driven increasingly negative with respect to ground,
current flow through OS is increased and
current flow through 012 is decreased
accordingly.
Single-supply operation: Initially, let it be
assumed that the value of R L is very high
(or disconnected), and that the input-terminal
bias (Terms. 2 and 3) is such that the output terminal (No.6) voltage is at V+ /2, i.e.,

CA3130A, CA3130

-1*
-r
1

POSITIVE
SUPPL.Y

+

la)

Ibl SINGLE POWER-SUPPLY OPERATION

DUAL POWER-SUPPLY OPERATION

Fig. 14 - CA313D output stage in dual and single power·supply operation.

in the order of 1 megohm or more, In this
case, the total input·referred noise voltage
is typically only 23 J1V when the test·circuit
amplifier of Fig. 15 is operated at a total
supply voltage of 15 volts. This value of
total input·referred noise remains essentially
constant, even though the value of source,
resistance is raised by an order of magnitude.
This characteristic is due to the fact that
reactance of the input capacitance becomes a
significant factor in shunting the source
resistance. It should be noted, however, that
for values of source resistance very much
greater than 1 megohm, the total noise
voltage generated can be dominated by the
thermal noise contributions of both the
feedback and source resistors.

the voltage·drops across 08 and 012 are of
equal magnitude. Fig. 7 shows typical quies·
cent supply·current vs. supply·voltage for the
CA3130 operated under these conditions.
Since the output stage is operating as a
Class A amplifier, the supply·current will
remain constant under dynamic operating
conditions as long as the transistors are
operated in the linear portion of their
voltage·trans,fer characteristics (see Fig, 6).
If either 08 or 012 are swung out of their
linear regions toward cut·off (a non·linear
region), there will be a corresponding reo
duction in supply·current. In the extreme
case, e.g., with Term. 8 swung down to
ground potential (or tied to ground), NMOS
transistor 012 is completely cut off and the
supply·current to series·connected transistors
08, 012 goes essentially to zero.' The two
preceding stages in the CA3130, however,
continue to draw modest supply·current (see
the lower curve in Fig. 7) even though the
output stage is strobed off. Fig. 14a shows a
dual·supply arrangement for the output stage
that can also be strobed off, assuming R L=00,
by pulling the potential of Term. 8 down to
that of Term. 4.
Let it now be assumed that a load·resistance
of nominal value (e.g., 2 kilohms) is con·
nected between Term. 6 and ground in the
circuit of Fig.14b. Let it further be assumed
again that the input·terminal bias (Terms. 2
and 3) is such that the output terminal (No.
6) voltage is a V+/2. Since PMOS transistor
08 must now supply quiescent current to
both R L and transistor 012, it should be
apparent that under these conditions the
supply·current lI1ust increase as an inverse
function of the R L magnitude. Fig. 9 shows
the voltage·drop across PMOS transistor 08
as a function of load current at several supply·
voltages. Fig. 6 shows the voltage·transfer
characteristics of the output stage for several
values of load resistance.

TYPICAL APPLICA nONS
Voltage Followers
Operational amplifiers with very high input
resistances, like the CA3130, are particularly
suited to service as voltage followers.- Fig. 16
shows the circuit of a classical voltage
follower, together with pertinent waveforms
using the CA3130 in a split·supply config·
uration.
A voltage follower, operated from a single
supply. is shown in Fig. 17, together with
related waveforms. This follower circuit is

+7.5 v

Wide band Noise
From the standpoint of low·noise perform·
ance considerations, the use of the CA3130
is most advantageous in applications where
in the source resistance of the input signal is

3-95

BWI-3dB)-ZOO kHz
TOTAL NOISE VOLTAGE (REFERRED
TO INPUTI-23,.V TYP

!kg

Fig. 15 - Test-circuit amplifier (3D·dB gain) used

for wideband noise measurements.

--'
«(I)

za:

OW

~~

w:;;

:5«

CA3130A, CA3130
+75 V

10

lin

un
8Wl·3dB}·4MH.
SR-IOY/pl

OII'F

92CS-2413S

9lCS-24727

ov
(a) Output-waveform with input-signal ramping
(2 V/div. and 500 !'s/div.)

Top Trace: Output
Bottom Trace: Input
(a) Small-signal response (50 mV/div.
and 200 ns/div.)

92CS-24728RI

Top Trace: Output signal (2 V/div.
and 5 !'s/div.)

92CS·24739

Top Trace: Output (5 V/div. and 200 !,s/div.)
Bottom Trace: Input (5 V Idiv. and 200 !'s/div_)
(b) Output-waveform with ground-reference
sine-wave input

Center Trace: Difference signal (S mV!div.

Fig_17 - Single-supply voltage-follower with

and 5 !'s/div.)
Bottom Trace: Input signal (2 V/div.
and 5 !'s/div.)
(b) Input-output difference signal showing

associated waveforms. (e.g., for use

settling time (Measurement rna.de with

Tektronix 7 A 13 differential amplifier)
Fig. 16 - Split-supply voltage follower with

associated waveforms.

linear over a wide dynamic range, as illustrated by.the reproduction of the output
waveform in
Fig_ 17a with input-signal
ramping. The waveforms 'in Fig_ 17b show
that the follower does not lose its input-tooutput phase-sense, even though the input is

in single-supply D/A converter; see
Fig_9 in ICAN-6OBOI.

being swung 7.5 volts below ground potential_
This unique characteristic is an .important
attribute in both operational amplifier and
comparator applications. Fig. 17b also shows
the manner in which the CMOS output
stage permits the output signal to swing down
to the negative supply-rail potential (i.e.,
ground in the case shown). The digital-toanalog converter (DAC) circuit, described in
the following section, illustrates the practical
use of the CA3130 in a single-supply voltagefollower application.

3-96

CA3130A, CA3130
9-Bit COS/MOS DAC
A typical circuit of a 9-bit Digital-to-Analog
Converter (DAC)" is shown in Fig_18 This
system combines the concepts of mUltipleswitch CMOS IC's, a low-cost ladder network of discrete metal-oxide-film resistors,
a CA3130 op amp connected as a follower,
and an inexpensive monolithic regulator in
a simple single power-supply arrangement.
An additional feature of the DAC is that it is
readily interfaced with CMOS input logic,
e_g_, 10-volt logic levels are used in the
circuit of Fig_ lB.

of one per cent tolerance metal-oxide film
resistors_ The five arms requiring the highest
accuracy are assembled with series and
parallel combinations of 80G,000-ohm resistors from the same manufacturing lot.
A single 15-volt supply provides a positive
bus for the CA3130 follower amplifier and
feeds the CA3085 voltage regulator. A
"scale-adjust" function is provided by the
regulator output control, set to a nominal
10-volt level in this system. The line-voltage
regulation (approximately 0_2%) permits a
9-bit accuracy to be maintained with varia-

10 V LOGIC INPUTS
I

.,T

REQUIRED
RATIO- MATCH

STANDARD

to 1"4
t02%
t04%

6-'

toe%
tt%. ASS

ALL RESISTANCES IN OHMS

,

.

B06 K

,

PARALLELED
RESISTORS

REGULATED
IIOLTAGE
AOJ

OOOII£F

.

3 B3

,

t<

2.

OI,u.F

'J2CL - 24 729

Fig. 18-9-bit DAC using CMOS digital switches and CA3130.

The circuit uses an RI2R voltage-ladder
network, with the output potential obtained
directly by terminating the ladder arms at
either the positive or the negative powersupply terminal. Each CD4007 A contains
three "inverters", each "inverter" functioning as a single-pole double-throw switch to
terminate an arm of the R/2R network at
either the positive or negative power-supply
terminal. The resistor ladder is an assembly
• "Digital:'to-Analog Conversion

Using

the

Harris

CD4007 A COS/MOS IC", Application Note ICAN-BOBO.

3-97

tions of several volts in the supply. The
flexibility afforded by the COS/MOS building
blocks simplifies the design of DAC systems
tailored to particular needs.
Single-Supply, Absolute-Value, Ideal FullWave Rectifier
The absolute-value circuit using the CA3130
is shown in Fig. 19_ During positive excursions, the input signal is fed through me
feedback network directly to the output_
Simultaneously, the positive excursion of the
input signal also drives the output terminal (No_ G) of the inverting amplifier in a

CA3 730A, CA3 730
negative-going excursion such that the 1 N914
diode effectively disconnects the amplifier
from the signal path. During a negative-going
excursion of the input signal, the CA31;30
functions as a normal inverting amplifier with
a gain equal to''-R2/R1. Vtihen the equality
of the two equations shown in Fig. 19 is
satisfied, the full-wave output is symmetrical.

Error-Amplifier in Regulated-Power Supplies
The CA3130 is an ideal choice for erroramplifier service' in regulated power supplies
since it can function as an error-amplifier
when the regulated output voltage is required to approach zero. Fig. 21 shows the
schematic diagram of a 40-mA power supply
capable, of providing regulated output volt-

ft'
2k4

GAIN·

+t5Y

fax. RI+::+R3

R3.RI (X+X2)
I-X

FOR X-O.S:

:::.~

92CS- 24738RI

R3. no (Oo~:). un

Top Trace: Output signal (2 V/div.1
Bottom Trace: Input signal 110 VIdiv.)
Tome base on both traces: 0.2 ms/div.

20 Y p-p INPUT: BW(-3dBI- 230IIH:r, DC OUTPUT (AYG.) .3.2 v
I VOLT p-p INPUT. BW(-3dBI-I30IIHz,DCOUTPUT(AVG.).t60mY

Fig. 19 -' Single-supply, absolute-value, ideal full-wave
rectifier with associated waveforms.

Peak Detectors
Peak-detector circuits are easily implemented
with the CA3130, as illustrated in Fig. 20
for both the peak-positive and the peaknegative circuit. It should be noted that with
large-signal inputs, the bandwidth of the
peak-negative circuit is much less than that of
the peak-positive circuit. The second stage
of the CA3130 limits the bandwidth in this
case. Negative-going output-signal excursion
requires a positive-going signal excursion at
the collector of transistor Qll, which is
loaded by the intrinsic capacitance of the
associated circuitry in this mode. On the
other hand, during a negative-going signal
excursion at the collector of Qll, the
transistor functions in an active "pull-down"
mode so that the intrinsic capacitance can be
discharged more expeditiously.

age by continuous adjustment over the range
from 0 to 13 volts. Q3 and Q4 in IC2 (a
CA3086 transistor-array IC) function as
zeners to provide supply-voltage for the
CA3130 comparator (lC1). Ql, 02, and
Q5 in IC2 are configured as a low impedance,
temperature-compensated source of adjustable reference voltage for the error amplifier.
Transistors Ql, Q2, Q3, and Q4 in IC3
(another CA3086 transistor-array IC) are
connected in parallel as the series-pass element. Transistor Q5 in IC3 functions as a
current-limiting device by diverting base
drive from the series-pass transistors, in
accordance with the adjust..,ent of resistor
R2.
Fig. 22 contains the schematic diagram of a
regulated power-supply capable of providing
regulated output voltage by continuous ad-

-DC

OUTPUT

.,..
(a) PEAK POSITIVE DETECTOR CiRCUIT

Ibl PEAK NEGATIVE DETECTOR CIRCUIT

Fig_20 - Peak-detector circuits.

3-98

CA3130A, CA3130

r -__~5IlVv

CURRENT
LlIlIT

__~~~~__~____________________'-__-r__~+
R2

I'll
IC5

[Ci;oa6 - - - I
I

I
I

L_I
20llQ

OUTPUT
OTOl3V
AT
40 mA

I til

39011

2.2 kll

0.01

-,
HOV

I

INPUT

1

~cn

Za::
OW

I

~§

30 kll

141

a::

1~\Il>+-----t-JVlIIr~

&'"

3-.1
62k1l

REGULATION (NO LOAD TO FULL LOAD)' < 0.01""
INPUT REGULATION: O.o2"-/V

HUll ANO NOISE OUTPUT: < 25".V UP TO 100 kHI
92C"-24752

Fig. 21-Voltage regulator circuit (0 to 13 Vat 40 mAl.

+~~------------------~-------4h

4.3 kll
IW

+

1000 pF

+

43kn

-

2.2 kll
+5~V

INPUT

1C2

[CA30a6

1
I

04

4

100
I'F
OUTPUT:
0.1 TO ~OV
AT I A

-,

10, II

1
1

I

1

I

8.2~1l

L __ __
Ikll

50kll~~____----------~------~

62kll

REGULATION (NO LOAD TO FULL LOAD)' <0.005%
INPUT REGULATION: < 0.01 "" IV
HUM AND NOISE OUTPUT: < 250 I'V RMS UP TO 100 kHz
92CM-24734

Fig.22 - Voltage regulator circuit (0.1 to 50 Vat 7 A).

3-99

D..

W::;;

CA3130A, CA3130
justment over the range from 0.1 to 50 volts
and currents up to 1 ampere. The error
amplifier (lCl) and circuitry associated with
IC2 fu,nction as previously described, al·
though the output of ICl is boosted by a
discrete transistor (04) to provide adequate
base drive for the Darlington-connected series·
pass transistors 01, 02. Transistor 03 functions in the previously described currentlimiting circuit.
Multivibrators
The exceptionally high input resistance presented by the CA3130 is an attractive feature
for multivibrator circuit design because it
permits the use of timing circuits with high
RIC ratios. The circuit diagram of a pulse
generator lastable multivibrator), with provisions for independent control of the "on"
and "off" periods, is shown in Fig. 23.
Resistors R1 and R2 are used to bias the
CA3130 to the mid-point of the supply-voltage and R3 is the feedback resistor. The
pulse repetition rate is selected by positioning 51 to the desired position and the rate
remains essentially constant when the resistors which determine "on-period" and
"off-period" are adjusted.
Function Generator
Fig. 24 contains a schematic diagram of a
function generator using the CA3130 in the
integrator and threshold detector functions.
This circuit generates a triangular or square-

wave output that can be swept over a
1,000,000:1 range 10.1 Hz to 100 kHz) by
means of a single control, Rl. A voltagecontrol input is also available for remote
sweep-control.
The heart of the frequency-determining system is an operational-transconductance-amplifier IOTA)', IC1, operated as a voltage-controlled current-source. The output, la, is a
current applied directly to the integrating
capacitor, Cl, in the feedback loop of the
integrator IC2, using a CA3130, to provide
ths triangular-wave output. Potentiometer
R2 is used to adjust the circuit for slope
symmetry of positive-going and negativegoing signal excursions.
Another CA3130, IC3, is used as a controlled
switch to set the excursion limits of the
triangular output from the integrator circuit.
Capacitor C2 is a "peaking adjustment" to
optimize the high-frequency square-wave
performance of the circuit.
Potentiometer R3 is adjustable to perfect the
"amplitude symmetry" of the square-wave
output signals. Output from the threshold
detector is fed back vi a resistor R4 to the
input of ICl so' as to toggle the current
source from plus to minus in generating the
linear triangular wave.
'See File No. 475 and ICAN-6668.

iOOll"F
RI
100 kn

R2
100 kn

FREQUE>lCY RANGE
POSITION OF SI

°

OOII"F
OOII"F
OII'F

II"F

PULSE PERIOD
4 ",s TO
40",5 TO
04 ms TO
4 msTO

I ma
IOms
lOOms
Is
92CS

Fig.23 - Pulse generator (astable multivibratorl with
provisions for independent control of "ON"
and "OFF" periods.

3-100

24733

CA3130A, CA3130
R4

INTEGRATOR

CI
THRESHOlD

VOL.TAGE - CONTROLLEO
CURRENT SOURCE

Hn

DETECTOR

3kn
+HV

RZ
LOQkO

SLOPE
SYMMETRY
ADJUST

-75V

IOk{l

VOL.TAGE

CONTROLLED
INPUT

FREQ

i

ADJUST

CLOD kHz MAX 1
-TOV

""SEE FILE NO 415 AND ICAN-6668

FOR TECHNICAL INFORMATION

Fig. 24 - Function generator (frequency can be varied

1,000,000/1 with a single control)_

-'
«en

:z a:
OW

-u:::

Operation with Output-Stage Power-Booster
The current-sourcing and -sinking capability
of the CA3130 output stage is easily supplemented to provide power-boost capability_
In the circuit of Fig. 25, three CMOS
transistor-pairs in a single CA3600E' IC
array are shown parallel connected with the
output stage in the CA3130. In the Class A
mode of CA3600E shown, a typical device
consumes 20 mA of supply current at 15-V

operation. This arrangement boosts the
current-handling capability of the CA3130
output stage by about 2.5X.
The amplifier circuit in Fig. 25 employs
feedback to establish a closed-loop gain of
48 dB. The typical large-signal bandwidth
(-3 dB) is 50 kHz.
*See File No. 619 for technical information.
+I~

II

IMn

7~O

kn

IN~'f--,\211·lIn".....t-!

5001

II'F

RL"'IOO

n

(PO·I!50 mW
AT THO·
-=10%)

AI/(eL) = 48 dB
LARGE SIGNAL
Bwt-3 dB)" 50 kHz

510 kn
NOTE.

·SEE FILE NO. 619

TRANSISTORS pi, p2, p3 AND nl, n2, n3 ARE
PARALLEL-CONNECTED WITH as AND QI2,
RESPECTIVELY, OF THE CA3130
92CM-24137

Fig. 25 - CMOS transistor array (CA3600E)

connected as power-booster in the
output stage of the CA3130_

3-101

~~

w:;;
~«

CA3140A
CA3140

mHARRIS

BiMOS Operational Amplifiers
with MOSFET Input/Bipolar Output

August 1991

Features

Description

• MOSFET Input Stage
~ Very High Input Impedance (ZIN) -1.5 TO (Typ.)

The CA3140A and CA3140 are Integrated-circuit
operational amplifiers that combine the advantages of highvoltage PMOS transistors with high-voltage bipolar
transistors on a single monolithic chip. Because of this
unique combination of technologies, this device can now
provide designers, for the first time, with the special
performance features of the CA3130 CMOS operational
amplifiers and the versaility of the 741 series of industrystandard operational amplifiers.

o

~

Very Low Input Current (II) -10 pA (Typ.) @ ±15V

~

Wide Common-Mode Input-Voltage Range (VICR)
- can be Swung 0.5 Volt Below Negative SupplyVoltage Rail

~

Output Swing Complements Input CommonMode Range

Directly Replaces Industry Type 741 in Most
Applications

Applications
• Ground-Referenced Single-Supply Amplifiers in
Automobile and Portable Instrumentation
• Sample and Hold Amplifiers
• Long-Duration Timers/Multivibrators
(Microseconds-Minutes-Hours)
• Photocurrent Instrumentation
• Peak Detectos
• Active Filters
• Comparators
• Interface in 5V TTL Systems and Other Low-Supply
Voltage Systems
• All Standard Operational Amplifier Applications
• Function Generators
• Tone Controls
• Power Supplies
• Portable Instruments
• Intrusion Alarm Systems

Pinouts

The CA3140A and CA3140 BiMOS operational amplifiers
feature gate-protected MOSFET (PMOS) transistors In the
Input circuit to provide very-high-input impedance, verylow-input current, and high-speed performance. The
CA3140A and CA3140 operate at supply voltage from 4 to
36 volls (either single or dual supply). These operational
amplifiers are internally phase-compensated to achieve
stable operation In unity-gain follower operation, and
additionally, have access terminal for a supplementary ex·
ternalcapacitor if additional frequency roll-off is desired.
Terminals are also provided for use in applications requiring
Input offset-voltage nUlling. The use of PMOS field-effect
transistors In the input stage results in common-mode
input-voltage capability down to 0.5 voit below the
negative-supply terminal, an important attribute for singlesupply applications. The output stage uses bipolar
transistors and includes built-In protection against damage
from load-terminal short-circuiting to either supply-rail or
to ground.
The CA3140 Series has the same 8-lead terminal pin-out
used for the "741" and other industry-standard operational
amplifiers. They are supplied in either the standard 8-lead
TO-5 style package (T suffix), or in the 8-lead dual-ln-Iine
formed-lead TO-5 style package "OIL-CAN" (S suffix). The
CA3140 is available in chip form (H suffix). The CA3140A
and CA3140 are also available in an 8-lead Small Outline
package (M suffix) and in an 8-lead dual-In-line plastic
package (MINI-DIP - E suffix). The CA3140A and CA3140
are intended for operation at supply voltage up to 36 volts
(±18 volts). All types can be operated safely over the
temperature range from -550 C to +1250 C.

SAND T SUFFIXES
TOP VIEW
TAB /STROBE

E AND M SUFFIXES
TOP VIEW

8

OFFSET

NULL

INV.
INPUT
NON ·INV.
INPUT

V·

V+
OUTPUT
OFFSET

NULL

4

V· AND CASE

STROBE

FIGURE 1.

CAUTION: These devices are sensitive to electrostatic dIscharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-102

File Number

957.1

CA3140A, CA3140

TYPICAL ELECTRICAL CHARACTERISTICS'
TEST
CONDITIONS
V+=+15V
V-=-15V
TA = 25°C

CHARACTER ISTIC

Typ.Value 01 Resistor Between
Term. 4 and 5 or
4 and 1 to Adjust
Max. Via

Input Ollset Voltage
Adjustment Resistor

CA3140A CA3140

UNITS

IT, S, E, M) (T, s, E, M)

18

4.7

kn

Input Resistance

Rl

1.5

1.5

H2

Input Capacitance

CI

4

4

pF

Output Resistance

RO

60

60

n

48

48

/lV

40
12

40
12

nV/../Hz

Short·Circuit Current to
Opposite Supply Source IOM+
Sink
IOM-

40
18

40
18

rnA

Gain·Bandwidth
Product. (See Figs. 5 &18)

IT

4.5

4.5

MHz

SR

9

9

V//ls

220

220

/lA

0.08
10

0.08
10

/lS
%

4.5
1.4

4.5
1.4

/lS

Equivalent Wide band
Input Noise Voltage
(See Fig_ 39)

en

Equivalent Input
Noise Voltage
(See Fig.l0)

en

Slew Rate. (See Fig.6)

BW = 140 kHz
RS = 1 Mn
1= 1 kHz

I RS

=

1= 10kHz 1100n

Sink Current From Terminal 8
To Terminal 4 to Swing
Output low
Transient Response:
Rise Time
Overshoot (See Fig. 37)
Settling Time
at 10 Vp.p,
(See Fig.17)

1 mV
10mV

tr
ts

RL=2kn
CL=100pF
Rl = 2 kn
el = 100 pF
Voltage Follower

3-103

rnA

CA3140A, CA3140
ELECTRICAL CHARACTERISTICS FOR EQUIPMENT DESIGN
At V+ =15 V. V- =15 V. TA

=2SOC Unless Otherwise Specified
LIMITS

CHARACTERISTIC

Input Offset Voltage.IVlol
Input Offset Current.

11101

Input Current. II
Large·Signal
Voltage Gain. AOL •
(See Figs. 4,18)
Common·Mode
Rejection Ratio. CMRR
(See Fig.9)
Common·Mode
Input·Voltage
Flange. VICR
(See Fig.20)

CA3140A
Min. Typ. Max.

-

2

5

-

0.5

20

10

40

20 k 100 k
86
100

70

32
90

-

CA3140
Min. Typ. Max.

...,
-

UNllS

5

15

mV

0.5

30

pA

10

50

pA

20 k 100 k
86
100

-

-

VN
dB

320

-

-

70

-15

-15.5
to
+12.5

11

V

320 IlVN
- dB

32
90

-15

-15.5
to
+12.5

12

-

100

150'

-

100

150

IlVN

76

80

-

76

80

-

d8

+12

13
-14.4

-

-

V

Power·Supply
IWIOII'N
Ratio. PSRR
(See Fig.ll)
Rejection

Max. Output
Voltage-

VOM+
(See Figs.13.20) YOM

~14

-

13.
+12
-14 -14.4

Supply Current. 1+
(See Fig.7 )

-

4

6

-

4

6

. rnA

Device Dissipation. Po

-

120

180

-

120

180

mW

Input Offset Voltage
Temp. Drift, !:NIOID.T

-

6

-

-

8

-

J.l.vtc

• At Va = 26Vp. p • +12V, -14V and RL = 2 kn.

3-104

• At RL = 2 kn.

CA3140A, CA3140
MAXIMUM RATINGS, Absolute-Maximum Values:
CA3140, CA3140A
DC SUPPLY VOLTAGE
(BETWEEN v+ AND V- TERMINALS) ...............•....................•..............•........••...... 36 V
DIFFERENTIAL-MODE INPUT VOLTAGE ..........•........••............................•...........•.. ± 8 V
COMMON-MODE DC INPUT VOLTAGE .........•.........•.............................. (v+ +8 V) to (V- -0.5 V)
INPUT-TERMINAL CURRENT .............•.........••...............................................•... 1 rnA
DEVICE DISSIPATION:
WITHOUT HEAT SINK UP TO 55'C ....•..•.....•............•......•..........•.•.....•.......................... _....•• 630 rnW
ABOVE 55°C ......•...............................................•............ Derate linearly 6.67 mW/oC
WITH HEAT SINKUP TO 55'C ..............................•..•..........•......•............................•.....••.. 1 W
ABOVE 55°C .....•...............................•...........................•. Derate linearly 16.7 mW/QC
TEMPERATURE RANGE:
OPERATING (ALL TYPES) ..•....................•...........................•.................. -55 to +125'C
STORAGE (ALL TYPES) .......•.......•... _... _••.. _...••.......•....•..•..................•.... -65 to +150'C
OUTPUT SHORT-CIRCUIT DURATION' .................•.....................•..........•........ INDEFINITE
LEAD TEMPERATURE (DURING SOLDERING):
AT DISTANCE 1/16 ± 1/32 INCH (1.59 ± 0.79 MM)
FROM CASE FOR 10 SECONDS MAX. .....•••....•.•......•......................................... +265'C
it

Short circuit may be applied to ground or to either supply.

-'
«en
za:
ow

~~

w:;;
~«

TYPICAL ELECTRICAL CHARACTERISTICS FOR DESIGN GUIDANCE
At V+ = 5 V, V- = 0 V, TA = 25°C
CA3140A
(T. S, E, M)

CHARACTERISTIC
I nput Offset Voltage

UNITS
mV

IVlol

2

/1101

0.1

5
0.1

II

2

2

pA

1
lOOk

1
100 k

H2

100

100

dB

CMRR

32

32

90
VICR

-0.5
2.6

90
-0.5
2.6

/lV/V
dB

6VIOIIW+

100

100

80

80

I nput Offset Current
Input Current
Input Resistance
Large-Signal Voltage Gain

AOL

(See Figs.4,l 8)
Common-Mode Rejection Ratio,
Common·Mode Input·Voltage Range
(See F ig.20)
Power·Supply Rejection Ratio

CA3140
(T, S, E, M)

Maximum Output Voltage
(See Figs.13,20)

VOM+
VOM

3

3

0.13

0.13

pA

V/V

V
/lV/V
dB
V

Maximum Output Current:
Source

10M+

10

10

Sink

10M

1

1

Slew Rate (See Fig.6)
Gain·Bandwidth Product (See Fig.5)
Supply Current (See Fig.7)
Dev;ce Dissipation

mA

7

7

IT
1+

3.7

3.7

1.6

1.6

mA

Po

8

8

mW

200

200

/lA

Sink Current from Term. 8 to
Term. 4 to Swing Output Low

3-105

V//ls
MHz

CA3140A, CA3140

r--+------------~-.~7~Y+

OFFSET

NULL

Fig.2 - Block diagram of CA3140 series.

,--------, r---------BIAS CIRCUIT

I
I
I
I
I

INPUT STAGE

II

r-++---+--,
QI

I

OFFSET NULL

y-

STROBE

ALL RESISTANCE VALUES ARE IN OHMS.

Fig.3 - Schematic diagram of CA3140 series.

CIRCUIT DESCRIPTION

Fig.2 is a block diagram of the CA3140
Series PMOS Operational Amplifiers. The
input terminals may be operated down to
0.5 V below the negative supply rail. Two
class A amplifier stages provide the voltage
gain, and a unique class AB amplifier stage
provides the current gain necessary to drive
low-impedance loads.
A biasing circuit provides control of cascoded
constant-current flow circuits in the first and
second stages. The CA3140 includes an on-

chip phase·compensating capacitor that is
sufficient for the unity gain voltage-follower configuration.
Input Stages - The schematic circuit diagram
of the CA3140 is shown in Fig.3. It consists of a differential-input stage using PMOS
field·effect transistors (09, 010) working
into a mirror pair of bipolar transistors (all,
012) functioning as load resistors together
with resistors R2 through R5. The mirrorpair transistors also function as a differen-

3-106

CA3140A, CA3140
tial-to-single-ended converter to provide basecurrent drive to the second-stage bipolar
transistor (0131_ Offset nulling, when desired, can be effected with a 10-kU potentiometer connected across terminals 1 and
5 and with its slider arm connected to terminal 4_ Cascode-connected bipolar transistors
02, 05 are the constant-current source for
the input stage_ The base-biasing circuit for
the constant-current source is described subsequently _ The small diodes 03, 04, 05 provide gate-oxide protection against high-voltage transients, e.g_, static electricity_
Second Stage - Most of the voltage gain in
the CA3140 is provided by the second amplifier stage, consisting of bipolar transistor
013 and its cascode·connected load resis·
tance provided by pipolar transistors Q3, 04_
On-chip phase compensation, sufficient for
a majority of the applications is provided by
Cl_ Additional Miller-Effect compensation
(roll-off) can be accomplished, when de·
sired, by simply connecting a small capacitor between terminals 1 and 8. Terminal
8 is also used to strobe the output stage into
quiescence_ When terminal 8 is tied to the
negative supply rail (terminal 4) by mechanicalor electrical means. the outDut terminal 6
swings low, i.e_, approximately to terminal
4 potential.
Output Stage - The CA3140 Series circuits
employ a broadband output stage that can
sink loads to the negative supply to complement the capability of the PMOS input stage
when operating near the negative rail. Ouiescent current in the emitter-follower cascade
circuit (Q17, Q18) is established by transistors (014, Q15) whose base-currents are
"mirrored" to current flowing through diode
02 in the bias circuit section_ When the
CA3140 is operating such that output terminal 6 is sourcing current, transistor Q18
functions as an emitter-follower to source
current from the V+ bus (terminal 7). .via
07, R9, and R 11. Under these conditions,
the collector potential of Q13 is sufficiently high to permit the necessary flow of
base current to emitter follower Q17 which,
in turn, drives Q18.
When the CA3140 is operating such that
output terminal 6 is sinking current to the
V- bus, transistor 016 is the current-sinking

element. Transistor Q16 is mirror-connected
to 06, R7, with current fed by way of 021,
R12, and Q20. Transistor Q20, in turn, is
biased by current-flow through R 13, zener
08, and R 14. The dynamic current-sink
is controlled by voltage-level sensing. For
purposes of explanation, it is assumed that
output terminal 6 is quiescently established
at the potential mid-point between the V+
and V- supply rails. When output-current
sinking-mode operation is required, the collector potential of transistor Q13 is driven
below its quiescent level, thereby causing
Q17, Q18 to decrease the output voltage at
terminal 6. Thus, the gate terminal of PMOS
transistor Q21 is displaced toward the V- bus,
thereby reducing the channel resistance of
Q21. As a consequence, there is an incremental increase in current flow through
Q20, R12, 021, 06, R7, and the base of
Q16. As a result, Q16 sinks current from
terminal 6 in direct response to the incremental change in output voltage caused by
Q18. This sink current flows regardless of
load; any excess current is internally supplied
by the emitter-follower Q18. Short-circuit
protection of the output circuit is provided
by Q19, which is driven into conduction by
the high voltage drop developed across R11
under output short-circuit conditions. Under
these conditions, the collector of 019 diverts current from 04 so as to reduce the
base-current drive from Q17, thereby limiting current flow in 018 to the short-circuited load terminal.
Bias Circuit - Quiescent current in all stages
(except the dynamic current sink) of the
CA3140 is dependent upon bias current
flow in R1. The function of the bias circuit is to establish and maintain constantcurrent flow through 01, Q6, Q8 and 02_
01 is a diode-connected transistor mirrorconnected in parallel with the base-emitter
junctions of Ql, 02, and Q3. 01 may be
considered as a current-sampling diode that
senses the emitter current of Q6 and automatically adjusts the base current of Q6
(via 01) to maintain a constant current
through Q6, 08, 02_ The base-currents in
02, Q3 are also determined by constantcurrent flow 01. Furthermore, current in
diode-connected transistor 02 establishes the
currents in transistors Q14 and Q15.

3-107

CA3140A, CA3140
20

LOAD RESISTANCE tRL'. 2 kn
LOAD CAPACITANCE (ell. 100 pF

~

Ir.~~§
.-~~~
AMBIENT TE"PERATUREITA

...

125-<:

I
SUPPLY VOLTAGE {V-t; V-I-VOLTS

5
10
15
SUPPLY VOLTAGE IV+, Y"I- VOLTS

20

'"

Fig.5 - Gain-bandwidth product vs supply voltage
and temperature.

Fig.4 - Open-loop voltage gain vs supply voltage
and temperature.
20 LOAD RESISTANCE (RL'-2 kl1

LOAD RESISTANCE IRL'·II)

LOAD CAPACITANCE (ell-IOO pF

. ,.

t
~

!!!

~IO

12S-C

5

10

15

20

5

25

10

15

20

25

SUPPLY VOLTAGE (y+, v-l-VOLTS

SUPPLY VOLTAGE (V+, Y-'-VOL TS

92C$-2190t

Fig.6 - Slew rate

VI

supply voltage andtemperature.

Fig.7 - Quiescent supply current vs supply voltage
and temperature.

AMBIENT TEMPERATURE (TAl -25·C

>

SUPPLY VOLTAGE:

v+. IS V, Y-.-15 V

\

§'

;;;20
~

g ,.

f
~

~~'MTV~kJ~~i.;'u~~WA)'-:'-i5-;~ v

I

"fZ5

~

120

~

I

i

~

z
Q 60

1\\
,

0
10 K

. .,

r-:

~80

\

10

5

1111

lOO

,

lOOK

~.1.

~~
~'V°i

"'o!-.~

*~
~
~

r--.

. . , I -,
I.

40

18

20

,

0

10

4M

10

FREQUENCY (f)-Hz
92CS-2190B

10'

,

10

Fig.9 - Common-mode rejection ratio
V$ frequency.

Fig.8 - Maximum output voltage swing
VI

t"

.

lol
10
~
FREQUENCY (I) - Hz

frequency.

I

i

POWER SUPPLY
REJECTION RATIO
IPSRRI-,6VIO/AV

SUPPLY VOLTAGE: V+-IS Vi V---IS V
AMBIENT TEMPERATURE (TA'- 25- C

~

~K)()

L

CA3140B

r-....

CA3140A,
130 CA3140

"-

1;60

L
[

~

,~
'~~-t;0

~20

10

IOZ

I~

10'

10'

FREQUENCY If) - Hz

Fig. to - Equivalent input noise voltage
VI

i

10

10'

.

10'
10
IQlI
FREQUENCY (n - Hz

Fig.tt - Power supply rejection ratio
VI frequency.

frequency.

3-108

,

10

CA3140A, CA3140
APPLICATIONS CONSIDERATIONS
Wide dynamic range of input and output
characteristics with the most desirable high
input-impedance characteristic is achieved in
the CA3140 by the use of an unique design
based upon the PMOS-Bipolar process. Inputcommon-mode voltage range and outputswing capabilities are complementary, allowing operation with the single supply down
to four volts.
The wide dynamic range of these parameters
also means that this device is suitable for
many single-supply applications, such as,
for example, where one input is driven below the potential of terminal 4 and the
phase sense of the output signal must be
maintained - a most important consideration in comparator applications.

ate both power transistors and thyristors
directly without the need for level-shifting
circuitry usually associated with the 741
series of operational amplifiers.
Fig.16 show some typical configurations.
Note that a series resistor, R L, is used in both
cases to limit the drive available to the driven
device. Moreover, it is recommended that a
series diode and shunt diode be used at the
thyristor input to prevent large negative
transient surges that can appear at the gate of
thyristors, from damaging the integrated
circuit.

. ...

OUTPUT CIRCUIT CONSIDERATIONS

.:~

Excellent interfacing with TTL circuitry is
easily achieved with a single 6.2-volt zener
diode connected to terminal 8 as shown in
Fig.12. This connection assures that the
maximum output signal swing will not go
more positive than the zener voltage minus
two base-to-emitter voltage drops within the
CA3140. These voltages are independent
of the operating supply voltage.

....I

 8
I 6

~

4

~
g

0

~

-2

w

"';- ~/
/

--4
-6
-8
-10
01

/"

.....

FOLLOWER
INVERTING

- -

~;~ ~~r/'
~ RESISTANCE (RL)· 2 kO

./

2

-

1--

LOAD CAPACITANCE IC,)-IOO

fo-::

f'::;¥~
1>'~
0., 1--'0. , \
, \.
1>

. . ..

I~

,

(01 SETTLING TIME - , . ,

". . .

10

FOLLOWER

Fig. 16 - Methods of utilizing the VCE(sat) sinkingcurrent capability of the CA3140 series.

INVERTING

5 kn

BANDWIDTH AND SLEW RATE

For those cases where bandwidth reduction
is desired, for example, broadband noise reduction, an external capacitor connected between terminals 1 and 8 can reduce the openloop -3 dB bandwidth. The slew rate will,
however, also be proportionally reduced by
using this additional capacitor. Thus, a 20%
reduction in bandwidth by this technique
will also reduce the slew rate by about 20%.

SIMULATED
LOAD

>-r-'

100

PF~ ~2
I ~

511Ul

Fig.17 shows the typical settling time required to reach 1 mV or 10 mV of the final
value for various levels of large signal inputs for the voltage-follower and inverting
unity-gain amplifiers. The exceptionally
fast setting time characteristics are largely
due to the high combination of high gain and
wide bandwidth of the CA3140; as shown in
Fig. 18.

kn

L."
-.b-

92CS-27917RI

(b) TEST CIRCUITS

Fig. 17 - Input voltage vs settling time.

INPUT CIRCUIT CONSIDERATIONS

As mentioned previously, the amplifier inputs can be driven below the terminal 4
potential, but a series current-limiting re-

3-110

CA3140A, CA3140

VOLTAGE·V'o'"V·V-o-"V

SUPPL.Y
AMBIENT TEMPERATURE IT~I.Z~·C
v 100

UllI-!!

-

t. ?~

-

'1

(0"; '"' ,

J

~

~~.r~

:!",

~"?

I

~~

~

~

v+ ...,5 V. V-.·'5

V

.~

/

f ..

..""V..

~60

10 K: SUPPLY VOLTAGE.

~OL~;'.

fb'9a

i'.f.q(

~

°·0

~

~

40

~

20

10

C''"1,o'''C},1'

,

10

10

,

~<'"
I I'hl:'o
, IIIII~
10
10'
10

10"
FREQUENCY If) -

Hz

.

-60

10

-40

20

0

2.0

40

60

80

100

120

140

AMBIENT TEMPERATURE ITAJ _·C

Fig. 19 - Input current vs ambient
temperature.

Fig.f8 - Open-loop vo/raga gain and phase lag
vs frequency.

sistor is recommended to limit the maximum
input terminal current to less than 1 mA to
prevent damage to the input protection
circuitry.
Moreover, some current-limiting resistance
should be provided between the inverting
input and the output when the CA3140 is
used as a unity-gain voltage follower. This
resistance prevents the possibility of extremely large input-signal transients from
forcing a signal through the input-protection
network and directly driving the internal
constant-current source which could result
in positive feedback via the output terminal.
A 3.9-kQ resistor is sufficient_
The typical input current is in the order of
10 pA when the inputs are centered at nominal device dissipation. As the output supplies
load current, device dissipation will increase,
raising the chip temperature and resulting in
increased input current. Fig.19 shows typical input-terminal current versus ambient
temperature for the CA3140.
It is well known that MOS/FET devices can
exhibit slight changes in characteristics (for
example, small changes in input offset voltage) due to the application of large differential input voltages that are sustained over
long periods at elevated temperatures.
Both applied voltage and temperature accelerate these changes. The process is reversible and offset voltage shifts of the opposite
polarity reverse the offset. Fig.14 shows the
typical offset voltage change as a function of
various stress voltages at the maximum rating
of 125°(; (for TO-5); at lower temperatures
(TO-5 and plastic). for example, at 85°C,
this change in voltage is considerably less.
In typical linear applications, where the
differential voltage is small and symmetircal,
these incremental changes are of about the
. same magnitude as those encountered in an
operational amplifier employing a bipolar a
transistor input stage.
SUPER SWEEP FUNCTION GENERATOR

A function generator having a wide tuning
range is shown in Fig.21. The 1,000,000/1

3-111

LOAD RESISTANCE (RL.laCD

-'._- - - OUTPUT VOLTAGE (+VOUT)

-<>5

- - COMMON-MOOE INPUT VOLTAGE (+VICRJ

-15·~I~'~V~OU@T~A~T~A~.~.'~EN~T~T~EMiPjERi.A~TUiRiE~(T~A~JO~'~25I'CII
VIeR AT TA"'25"C

-2

+VOUT AT TA "2!S"C

-2.5
-3

05

-<>5

-25
5

10

15

20

25

SUPPLY VOLTAGE (V+, V-I-VOLTS

Fig.20 - Output-voltage-swing capability and
common-mode input-voltage range
vs supply voltage and temperature.

adjustment range is accomplished by a single
variable potentiometer or by an auxiliary
sweeping signal. The CA3140 functions as a
non-inverting read-out amplifier of the triangular signal developed across the integrating capacitor network connected to the
output of the CA3080A current source.
Buffered triangular output signals are then
applied to a second CA3080 functioning as
a high-speed hysteresis switch. Output from
the switch is returned directly back to the

--I
<[en

;Za:
OW

~§

a:
"w::;:

~<[

CA3140A, CA3140
input of the CA3080A current source, there·
by, completing the positive feedback loop.
The triangular output level is determined by
the four 1N914 level·limiting diodes of the
second CA3080 and the resistor·divider net·
work connected to terminal No.2 (input) of
the CA3080. These diodes establish the in·
put trip level to this switching stage and,
therefore, indirectly determine the ampli·
tude of the output triangle.
Compensation for propagation delays around
the entire loop is provided by one adjust·

ment on the input of the CA3080. This
adjustment, which provides for a constant
generator amplitude output, is most easily
made while the generator is sweeping. High·
frequency ramp linearity is adjusted by the
single 7·to·60 pF capacitor in the output of
the CA3080A.
It must be emphasized that only the CA·
3080A is characterized for maximum output
linearity in the current·generator function.

-15V

CENTERING
100
kg,

+15 V

+15 V

THIS NETWORK IS USED WHEN THE
OPTIONAL BUFFER CIRCUIT IS NOT
USED

(a) Circuit

FREQUENCY
ADJUSTMENT

TOP TRACE OUTPUT AT JUNCTION OF

2.7 nAND 5Ul RESISTORS

5 VIDIV AND 500 ml/DIV

CENTER TRACE' EXTERNAL OUTPUT OF

TRIANGULAR FUNCTION

GENERATOR

2 VlON AND 500 ms IDIV

BOTTOM TRACE: OUTPUT OF "LOG n

GENERATOR
lOVlDIV AND 500 ml/DIV

INT

~EXTERNAL

INPUT

(b 1) Function generator sweeping

'-------~~~~5fH
V-

fe) Interconnections

lV/DIV and 1 sec/DIV
Three tone test signals, highest frequency;;'
0.5 MHz. Note the slight assymmetry at the
three·second/cycle signal. This assymmetry
is due to slightly different positive and nega·
tive integration from the CA3080A and from
the pc board and component leakages at the
100·pA level.
(b2) Function generator with fixed frequencies

Fig.21 - Function generator.

3-112

CA3140A, CA3140

FREQUENCY
CALIBRATION
MINIMUM

-15 V

Fig. 22 - Meter driver and buffer amplifier.

.....


5ICn.~

IOlln

RI

R"lOkn(OoT;) 15kfi
20 V pop INPUT

92CS-27887RI

BW(-3dBl'290 kHr, OC OUTPUT !AVG I,;, 2 V

Fig. 37 - Single-supply, absolute-value, ideal full-wave rectifier with associated waveforms.
+15 V

SIMULATED

LOAD

>-~-,
I

IODPF::.t

],

~*

l...,...l
-J:BWi-3dBI-4.5 MHz
SRo9 VI".,
005 ".F

TOP TRACE :OUTPUT

(SOmV/DIVAND 200ns/DIY)

BOTTOM TRACE: INPUT

15 VIOl'll. AND 5".5/0IV.1
CENTER TRACE: DifFERENCE SIGNAL
15m VlDIY·AND 5,...,/0IY.)
BOTTOM TRACE ~ INPUT SIGNAL
15V1DIV. AND 5".s/DIVI

150 mVlQIVAND 2oons/DIV)
la) SMALL- SIGNAL RESPONSE
150 mY/DIY ANO 2oons/OIV}

92C5-21879

Ib) INPUT- OUTPUT DifFERENCE SIONAL
SHOWING SETTLING TIME (MEASUREMENT
MADE WITH TEKTRONIX 7AI3 DIFFERENTIAL

AMPLIFIER)

Fig. 38 - Split-supply voltage-follower test circuit and associated waveforms.

3-120

92CS-27880

CA3140A, CA3140
+ 1511

NOISE
., - - - - " VOLTAGE
OUTPUT

30lkn

Bwl-3dBI= 140 kHz

TOTAL NOISE VOLTAGE (REFERRED
TO INPUT) ~48 ~V TYP

Ikn

9ZCS-27888

Fig. 39 - Test circuit amplifier 130-dB gainl used
for wideband noise measurement.

10
I

20
I

30

40

60 65

~I• •I~1IIi.~1

I

1
58-66

Dimensions and pad layout for CA3140H.

The photographs and dimensions represent
a chip when it is part of the wafer. When the
wafer is cut into chips, the cleavage angles
are 57° instead of 90° with respect to the

face of the chip. Therefore, the isolated
chip is actually 7 mils 10.17 mml larger

Dimensions in" parentheses are in millimeters and
are derived from the basic inch dimensions as in-

in both dimensions.

dicated. Grid graduations are in mils (10- 3 inch).

3-121

(II

CA3160A
CA3160

HARRIS

BiMOS Operational Amplifiers
with MOSFET Input/CMOS Output

August 1991

Features

Description

• MOSFET Input Stage Provides:
~ Very High ZI
1.STO (1.5 x 1012 0) (Typ.)
~ Very Low II = SpA Typ. @ 1SV Operation
= 2pA Typ. @ SV Operation

The CA3160A and CA3160 are Integrated circuit
operational amplifiers that combine the advantage of both
CMOS and bipolar transistors on a monolithic chip. The
CA3160 series are frequency compensated versions of the
popular CA3130 series.

=

• Common-Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can Be
Swung O.SV Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either
(or Both) Supply Rails

Applications
• Ground Referenced Single Supply Amplifiers
• Fast Sample Hold Amplifiers
• Long Duration Timers/Monostables
• High Input Impedance Wideband Amplifiers
• Voltage Followers (e.g. Follower for Single Supply
DIA Converter)
• Wien-Bridge Oscillators
• Voltage Controlled Oscillators
• Photo Diode Sensor Amplifiers

Gate-protected p-channel MOSFET (PMOS) transistors
are used In the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field effect transistors In the
input stage results in common-mode Input voltage
capability down to 0.5 volt below the negative-supply
terminal, an Important attribute In single-supply
applications•
A complementary symmetry MOS (CMOS) transistor-pair,
capable of swinging the output voltage to within 10
millivolts of either supply voltage terminal (at very high
values of load impedance), is employed as the output
circuit.
The CA3160 Series circuits operate at supply voltages
ranging from 5 to 1 6 volts, or ±2.5 to ±a volts when using
split supplies, and have terminals for adjustment of offset
voltage for applications requiring offset null capability.
Terminal provisions are also made to permit strobing of the
output stage.
The CA3160 Series is supplied in standard a-lead TO-5
style packages (T suffix), a-lead dual-in-line formed lead
TO-5 style "OIL-CAN" packages (S suffix). The CA3160 is
available in chip form (H suffix). The CA3160 and CA3160A
are also available In the Mini-DIP a-lead dual-In-line plastic
package (Mini-DIP-E suffix). All types operate over the full
military temperature range of -550 C to +1250C. The
CA3160A offers superior Input characteristics over those of
the CA3160.

Pinouts
SAND T SUFFIXES
TOP VIEW

ESUFFIX
TOP VIEW
TOP VIEW

SUPPLEMENTARY

COMPENSAno~ T~B /

~~~ET

1

STROBE
7

OFFSET
NULL
INV.
INPUT

v+

NON -INV.
INPUT

v4
V- AND CASE

STROBE

OUTPUT
5 OFFSET
NULL

NOTE: CA3160 Series devices have an on-chip frequency-compensation
network. Supplementary phase-compensation or frequency roll-off
(if desired) can be connected externally between terminals 1 and 8.

FIGURE 1.

CAUTION: The.e deylce. are .en.ltive 10 electrostatic discharge. Proper I.C. handling procedure. should be followed.
Copyright @ Ha"is Corporation 1991

3-122

File Number

976.1

CA3160A, CA3160
ELECTRICAL CHARACTERISTICS at TA=25 0 C, V+=15 V. V- = 0 V (Unless otherwise specified)
LIMITS
CA3160A (T, S, E)

CHARACTERISTIC

Typ.

Input Offset Voltage,
IvloI, V±=±7.5 V

-

2

5

Input Offset Current.
\110\' V±=±7.5 V

-

0.5

20

Input Current, II
V±=±7.5 V
Large·Signal Voltage
Gain, AOL
VO=10Vp.po RL=2kfl
Common· Mode
Rejection Ratio,CMRR
Common·Mode Input·
Voltage Range, V ICR
Power·Supply Rejection
Ratio,6.VIO//W±
V±=±7.5 V

CA3160 (T, S, E)

Units

Typ.

Max.

-

6

15

mV

-

0.5

30

pA

Max. Min.

Min.

-

5

30

-

5

50

pA

50 k

320 k

-

50 k

320 k

-

VIV

94

110

-

94

110

-

dB

80

95

-

70

90

-

dB

0

-0.5
to
12

0

-0.5
to
12

10

V

10

....I



za:

ow
~§
a:

~o" :n
:;:

II!:· i:;1
II ~ q 111
2~

5

75

illl
II
10

125

15

GATE VOLTAGElVG) [TERMS 4 Ii

II
II
115

III

20

225

e]-v

Fig.7 - Quiescent supply current vs. supply voltage.

Fig.6 - Voltage transfer characteristics of
COS/MaS output stage.

to

2468

12

ODD.

TOTAL SUPPLY VOLTAGE \V+]-V

Fig.8 - Quiescent supply current vs. supply voltage
at several temperatures.

0001

2468
Z
001

41i8
01

2468

I

2468
10

Q..

w::;;;
~z

~

w

~

CA3193

(o..c TO

70"C)

4

CA3193A
(-25"C TO 8S·C)

o

a

50
TEMPERATURE (T) -

50

CA3193A

150

100
°C

50

TEMPERATURE IT) -

IOZ~

AMBIENT TEMPERATURE ITAI- 25°C

~

z

~

w

a'"

3

IO~~===f===i====!:~;;:=:j
w

~
5

S

I

m

2

4 68

~

2

4 68

~

2

FREQUENCY -

4 68

~

2

4 68

I
2

~

HZ

6

10

14

POWER SUPPLY VOLTAGE

Fig. 9 - Input noise voltage and current density vs. frequency.

IB

22

UV+1l - v

Fig. 10 - Power supply voltage (V+, \1"") vs. supply current.

3-143

CA3193A, CA3193
100

160 AMBIENT TEMPERATURECTA)-25.C

~
I

-:.0

80

5

.~

40

z

0

~

~
.........

0

g

AMBIENT TEMPERATURE (TAJ • 25·C
tiS

-eo

120

0

"""
~

AOL

f'-..

-"""['\r"
•

10

I

0

..

"z

IOO~

II:
leo

1\

QI

-....

50 ~

-40
-80

CA319!A AND CA3193

3-

~

~

~

v-

140

ao5

102
lOS
10
FREQUENCY - Hz

200

106

6
10
14
18
POWER SUPPLY VOLTAGE (v", Y-I- Y

107

Fig. 11 - Open-loop gain and phase-shift response for CA3193B.

22

Fig. 12 - Open-loop gain vs. power-supply voltage.

!g
1130

-:.
~
z
~

~ 120

g~
g
oJ

CA3193A

(25·c;T08~

110

~

CA3193

(O·C TO 7O-CI

100

-eo

50

150

100

TEMPERATURE (TI-·C

SUPPLY VOLTAGE (Y+. V-) -

V

Fig. 13 - Open-loop gain vs. temperature for CA3193 series.

40

AMBIENT TEMPERATURE (TA) • 2.5·C

-

~ 3.

~

~

0"

30

~

i

li

'"

Y- --15V

r--....

25

~~20

~~

RL .2. K
y+ -15 V

'\

I.

\

\

10

1\

e
0
2

468'0

2

46'022

46'03 2

FREQlENCY -

~

46'04 2

4 ••

105

SUPPLY VOLTAGE (Y+. V-I -

Hz

Fig. 14 - Maximum undistorted output voltage vs. frequency.

v

Fig. 15 - Output-voltage-swing capability and common-mode
input-voltage vs. supply voltage.

3-144

CA3193A, CA3193
Offset Voltage Nulling
The input offset voltage can be nulled to zero by any of the
three methods shown in the table below. A 10K
potentiometer between terminals 1 and 5, with its wiper
returned to V-, will provide a gross nulling for all types. For
finer nulling, either of the other two circuits shown below

may be used, thus providing simpler improved resolution
for all types.
CAUTION: The CA3193 amplifiers will be damaged if they
are plugged into op-amp circuits employing nulling with
respect to the V+ supply bus.

Offset Voltage Nulling
Offset
Nulling
Circuits

ZV-

v-

~

W
v-

R

I

R

5

R

10K

R

IK

Type

Resistor R Value

Resistor R Value

Resistor R Value

CA3193A
CA3193

10K
10K

50K
20K

10K
5K

Gross Offset
Adjustment

Finer Offset
Adjustments

TEST CIRCUITS
vro.IVOUTI

10K

100

6

i

-15 V

v-

VOUT

9ZCS-32979

Fig. 16 - Input offset voltage test circuit.
10 K

92CS-32980

a
TOP TRACE: INPUT VOLTAGE
BOTTOM TRACE: OUTPUT VOLTAGE

o

VERT.: IOV
DIV

o

V+ = 15V
V- =-15V

92CS-32989

b
Fig. 17 - Inverting amplifier (a) test circuit (b) response to 1-kHz,
20- V pop square wave.

3-145

CA3193A, CA3193
+15V

200 pF I

,=,=,
a

SIMULATED

LOAD

TOP TRACE·: INPUT VOLTAGE
BOTTOM TRACE: OUTPUT VOLTAGE
V+ = 15 V

VERT:6~~

V-

HOR: .Ims
DIV

b
Fig. 18 - Voltage follower (a) test circuit (b) response to 20-V POp,
I-kHz square-wave input.

2.2Mn
1%

+15V

loon
1%

VOUT]
[vNOISE .--.!:.!?
22X10'
-15V

a

c

b

Fig. 19 - Low frequency noise (s) test circuit - 0.1 to 10 Hz (b)
output A waveform - 0 to 10 Hz noise (c) output B
waveform - 0 to 10 Hz noise.

3-146

= 15V

CA3193A, CA3193
APPLICATION CIRCUITS
R2

VCC

Vlo-_-'\iIR..,.1.,-.....~
10K

6

6

R3
V2o--~Ar-'-~
10K

RI
IK
R3
IK
R2
9K

ALL RESISTANCE VALUES ARE IN OHMS

R4
9K

IF R4'R2,R3' RI

:~

VOUT·-V. (

VOUr"'Yb -Va ( ::
A'

THEN VOUT - (V2-V,) (

+1) : ; +vb ( * + 1 )

FOR IDEAL RESISTORS WITH

:~.

AND*-~

:!

:~ I

FOR VALUES ABOVE VOUT- 2(V2 -VI)

-'

«00

:z a:
QUJ
-;:;:

IF AV IS TO BE MADE I AND IF RI • R3 • R4 • R
WITH R2· 0.999R (0.1% MISMATCH IN R2)

+ I)

vOUT . ( R4 +1)
vb-Va
R3
THEN VOCM • 0.0005 VIN OR CMRR • 66 dB
THUS, THE CMRR OF THIS CIRCUIT IS LIMITED BY
THE MATCHING OR MISMATCHING OF THIS NETWORK
RATHER THAN THE AMPLIFIER.

FOR VALUES ABOVE VOUT' (vb - V.)(IO)

Fig. 20 - Typical two-op amp bridge-type dIfferential amplifier.

Fig. 21 - Differential amplilier (simpls subtractor) using CA3193.

R2

VI

R3

RF

10K.
R2

20K

V2
10 K
RI
V3

r-- --l
I

RL
(011 TO 3.0 kll
WITH V-IV)

I

I

RS

I

I

I

: v-

:

10 K

R4
2.B K

L ____ ...l

VOUT'-(:~

VI+

~V2+ ~V3)

1

ALL RESISTORS ARE 1%
VOUT' -(2 VI + 2 v2 + 2 V3)
IF RI

=R3

AND R21::: R4+R5 THEN

IL IS INDEPENDENT OF VARIATIONS IN RL
FOR RL VALUES OF 011 TO 3kll WITH vol V

.
IL'

v

R4

ii3ii5'

v 1M
(2M)(lK)'

ALL RESISTANCE VALUES ARE IN OHMS

v

TI' 500,.A

Fig. 23 - Typical summing amplifier application.

Fig. 22 - Using CA31 gs as a bilateral current source.

3-147

~~
UJ:;;
15«

CA3193A, CA3193
The CA3193 is an excellent choice for use with
thermocouples. In Fig. 24, the CA3193 amplifies the signal

generated 500 times. The three 22-megohm resistors will
provide full-scale output if the thermocouple opens.

y+
15 Y

22M

22M

22M

10 k

~6----~----~-oYOUT
8.2K
20K
499K

THERMOCOUPLE

IK

2K

10.
IK

O-lmA

ALL RESISTORS ARE 1%
92CS-32986

ALL RESISTANCE VALUES ARE IN OHMS

Fig. 24 - The CA3193 used in a thermocouple circuit.

3-148

CA3240A
CA3240

mHARRIS

Dual BiMOS Operational Amplifiers
With MOSFET Input, Bipolar Output

August 1991

Features

Description

• Dual Version of CA3140

The CA3240A and CA3240 are dual versions of
the popular CA3140 series integrated circuit
operational
amplifiers. They combine the
advantages of MOS and bipolar transistors on the
same monolithic chip. The gate-protected
MOSFET (PMOS) input transistors provide high
input impedance and a wide common-mode input
voltage range (typically to O.5V below the negative
supply rail). The bipolar output transistors allow a
wide output voltge swing and provide a high
output current capability.

• Internally Compensated
• MOSFET Input Stage
(al Very High Input Impedance (ZINI ••••••••••••••••••••• 1.5TO Typ.
(bl Very Low Input Current (III •• •• • • •• •• ••••• • ••• 1OpA Typ. at ±15V
(cl Wide Common-Mode Input Voltage Range (VICRI: Can be Swung
0.5 Volt Below Negative Supply Voltage Rail
• Directly Replaces Industry Type 741 In Most Applications

Applications
• Ground Referenced Single Supply Amplifiers In Automobile and
Portable Instrumentation
• Sample and Hold Amplifiers
• Long Duration T1mers/Multlvlbrators (Mlcroseconds-Mlnutes-Hours)
• Photocurrent Instrumentation
• Active Rlters
• Intrusion Alarm Systems
• Comparators

• Function Generators

• Instrumentation Amplifiers

• Power Supplies

Pinouts

ESUFRX
(Pin compatible with the industry standard 1458)
TOP VIEW

The CA3240A and CA3240 are supplied in the
8 lead dual-in-line plastic package (Mini-DIP,
E suffix), and in the 14 lead dual-in-line plastic
package (El suffix). The CA3240A and CA3240
are compatible with the Industry standard 1458
operational amplifiers In similar packages. The
CA3240A and CA3240 have an operating
temperature range of -40oC to +850 C. The offset
null feature is available only when these types are
supplied In the 14 lead dual-in-Iine plastic
package (El suffix). The CA3240 is also available
in chip form (H suffix)•

Block Diagram

2mA

OUTPUT (A)
INV.
INPUT (A)
NON -INV.
INPUT (A)

v"

OUTPUT
INV.
INPUT (B)
NON -INV.
INPUT (B)

V-

E1 SUFFIX
TOP VIEW
INV.
INPUT (A)
NON -INV.
INPUT (A)
OFFSET
NULL (A)
OFFSET
NULL (8)
NON-INV.
INPUT (8)
INV.
INPUT (8)

4mA

V+

12pF
OFFSET
NULL (A)
V+*
OUTPUT

~~------~~--------------+---~v-

OFFSET
NUll."

'Only available wilh

14

lead DIP (E1 Suffix)

(A)

5

NC
OUTPUT

FIGURE 2. BLOCK DIAGRAM OF ONE-HALF CA3240 SERIES

(8)

OFFSET
NULL (8)

·Pins 9 & 13 internally
connected through
approximately 30
FIGURE 1
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.e. handling procedures should be followed.

Copyright

@)

Harris Corporation 1991

3-149

File Number

1050.1


I

"f25

1\

-?
~20

\

~

g IS

~

1\

10

\

I

•

I'\.

. . .. . . ..'--.

0

10 K

lOOK

1M

4M

10

10'

FREQUENCY {f)-HI'

Fig. 8 - Maximum output voltage swing
as a function of frequency.
~

105
104
10'
FREQUENCY (f I - Hz

10'

10'

Fig. 9 - Common-mode rejection ratio
as a function of frequency.

a SUPPLY VOLTAGE: '.1+.,15 V, '.1-.-15 V

RS·,oon

~

.·
·
·
§'" ·
·
~'OO8
~

g

....0



FREQUENCY (fJ-kHr

92CS-30024

0.01

. ..

0.1
1.0
LOAD (SINKINGI CURRENT - mA

...
92t5-27913

Fig. 14 - Crosstalk as a function of frequency.

Fig. 15 - Voltage across output transistors
015 and Q16 as a function of
load current.

3-155

10

CA3240A, CA3240
=i~T~=A;;;;J51~~r::5-;lg v

LOAD RESISTANCE(RLI-CO

~

0

10

.

~ -Q5 ~--- OUTPUT VOLTAGE I+VOI
~
~.-- COMMON-MODE INPUTVOLTAGEftYlCRI
~

~!

>

?:

~ 25'"C

TA

i~-l

4

,

ill

*8S·Cl

AMBIENT TEMPERATURE ITA I*SS*C

~

TA

~~-

g
~

0-'
o

--4

~>-

0

.....

-2

,.-

~

'S1~
-b'~
",., :--'''''' \
of>

-.

. . . . . -,. . .

-8
-10

~,

\

ID

0.1

la) SETTLING TIME -

~

'5

~.

FOLLOWER

20

25
INVERTING

Fig. 16 - Output-voltage-swing capability and

common-mode input-voltage range
as a function of supply voltage and
temperature.
10

FOLLOWER
INVERTING

~;~ ~:-;/'
~~~....
.....
./
~
RESISTANCE (~:. 211A
,LOAD CAPACITANCE I ) -100

8

.!. •

~

-- -

5 kR

tc: SUPPLY Ya..TAGE: Y+.+15 V, V~.-15 V

SIMULATED

"-J"~..L..>-f!~

/

00

PF~I ~2,

kR

L."

511k.o

-h-

92CS-30026

(b) TEST CIRCUITS

Fig. 17 - Input voltage 8$ a function of settling
-60

-40 -20

0

20

40

60

eo

100

120

time.

140

AMBIENT TEMPERATURE (TA) _·C
,IC$-271.,

Fig. 18 - Input current as a function of

ambient temperature.
SUPPLY
Wl.TAGE:.'C.~+I'V;"-· -15 V ~~
AMBIENT TEMPERATURE {TAl- 25'"C

II!

1.
+Ill ..

III

t:."~.

<%11111

1:,'-~-,
I

),

_.L. ZK"

'OOPFT n~
I

I

L~J
~~

BWI-3dS)-4.5 MHz

SRag VII'-'

0.05 ".F

·TOP TRACE: INPUT
J 50 mV/DIYi 200 ns/OIV)
BOTTOM TRACE: OUTPUT

( SO mVl ON ~ 200 ns/OIVI

la I SMALL SIGNAL RESPONSE

TOP TRACE: INPUT
(5V/OIV; I J's/DIV.)
BOTTOM TRACE: OUTPUT

(5 VlDIV ,I ns/DIV)

(bl LARGE SIGNAL RESPONSE
92CS- 30029

Fig. 20 - SpliNupply voltage·follower test
circuit and associated waveforms.

8 SUPPLY VOLTAGE ('11-)-0 V

NOISE

r-....- - u VOLTAGE
OUTPUT

30.1 kn

1.0

BW(-3dBI= 140 kHz
TOTAL NOISE VOLTAGE (REFERRED
TO INPUT)" 48 ~ V TYP.

0.01

...

0.1

1.0

. ..

LOAD (SINKING) CURRENT - rnA

Fig. 22 - Voltage across output transistors
015 and 016 as a function of
load current.

92CS- 30027

Fig. 21 - Test-circuit amplifier (30.tJ8 gain)

used for wideband noise measurement.

3-157

10

CA3240A, CA3240
load current, device dissipation will increase,
raising the chip temperature and resulting in
increased input current. Fig. 24 shows typi·
cal input·terminal current versus ambient
temperature for the CA3240.
,It is well known that MOS/FET devices can
exhibit sl ight changes in characteristics (for
example, small changes in input offset voltage) due to the application of large differential input voltages that are sustained over
long periods at elevated temperatures.
Both applied voltage and temperature accelerate these changes. The process is reversible and offset voltage shifts of the opposite
polarity reverse the offset. In typical linear
applications, where the differential voltage is
small and symmetrical, these incremental
changes are of about the same magnitude as
those encountered in an operational amplifier
employing a bipolar transistor input stage,

APPLICATIONS CONSIDERATIONS
Output Circuit Considerations
Fig. 22 shows output current·sinking capa·
bilities of the CA3240 at various supply
voltages. Output voltage swing to the nega·
tive supply rail permits this device to operate
both power transistors and thyristors directly
without the need for level·shifting circuitry
usually associated with the 741 series of
operational amplifiers.
Fig. 23 shows some typical configurations.
Note that a series resistor, R L, is used in both
cases to limit the drive available to the driven
device. Moreover, it is recommended that a
series diode and shunt diode be used at the
thyristor input to prevent large negative
transient surges that can appear at the gate of
thyristors, from damaging the integrated cir·
cuit.

10 K: SUPPLY Ya.TAGE: Y -+I!S V, V-.·I!5 V

-60

-40

-20

a

20

40

60

eo

100

120

140

AMBIENT TEMPERATURE (TA) _·C
92CS-300}1

Fig. 24 - Input current 8S a function of

92CS-30030

ambient temperature.

Fig. 23 - Methods of utilizing the V CE(sat)
sinking-current capability of the
CA3240 series.

Input Circuit.Considerations
As indicated by the typical VICR, this device
will accept inputs as low as 0.5 V below V-.
However, a series current·limiting resistor is
recommended to limit the maximum input
terminal current to less than 1 mA to prevent
damage to the input protection circuitry.
Moreover, some current·limiting resistance
should be provided. between the inverting
input and the output when the CA3240 is
used as a unitYilain voltage follower. This
resistance prevents the possibility of ex·
tremely large input·signal transients from
forcing a signal through the input·protection
network and directly driving the internal
constant-current source which could result
in positive feedback via the output terminal.
A 3.9·kO resistor is sufficient.
The typical input current is in the order of
10 pA when the inputs are centered at n0":1i'
nal device dissipation. As.the output supplies

Offset-Voltage Nulling
The input-offset voltage of the CA3240AE1
and CA3240E1 can be nulled by connecting
a 10-kO potentiometer between Terminals 3
and 14 or 5 and 8 and returning its wi per arm
to Terminal 4, see Fig. 25a. This technique,
however, gives more adjustment range than
required and therefore, a considerable portion
of the potentiometer rotation is not fully
utilized. Typical values of series resistors that
may be placed at either end of the potentiometer, see Fig. 25b, to optimize its utiliza~ion
.range are given in the table "Electrical
Characteristics For Design Guidance" shown
in this bulletin.
An alternate system is shown in Fig. 25c.
This circuit uses only one additional resistor
of approximately the value shown in the
table, For potentiometers, in which the
resistance does not drop to zero ohms at
• either' end of rotation, a value of resistance
10% lower than the values shown.in the table
should be used.

3-158

CA3240A, CA3240

In)

2(6)

vQ

v-

BASIC

b

IMPROVED
RESOLUTION

c. SIMPLER
IMPROVED
RESOLUTION

* SEE
CHARACTERISTICS CHART
FOR VALUE R

92CS-30032

Fig. 25 - Three offset-voltage nulling methods.
(CA3240AE1, CA3240El onIV.)

TYPICAL APPLICATIONS

--'
«(1)

z cc

the triac is turned on and held on by the
CA3059 and its associated positive feedback
circuitry (51-kQ resistor and 36-kQ/42-kQ
voltage divider). When the positive pulse
occurs at Terminal 1 (CA3240E), the triac is
turned off and held off in a similar manner.
Note that power for the CA3240E is supplied
by the CA3059 internal power supply.

On/Off Touch Switch
The on/off touch switch shown in Fig. 26
uses the CA3240E to sense small currents
flowing between two contact points on a
touch plate consisting of a PC board metallization "grid". When the "on" plate is
touched, current flows between the two
halves of the grid causing a positive shift in
the output voltage (Term. 7) of the CA3240E.
These positive transitions are fed into the
CA3059, which is used as a latching circuit
and zero-crossing triac driver. When a positive
pulse occurs at Terminal 7 of the CA3240E,

The advantage of using the CA3240E in this
circuit is that it can sense the small currents
associated with skin conduction while allowing sufficiently high circuit impedance to
provide protection against electrical shock.

44M

~---"AJ'v---~-n ~OV/220V
60Hz/&lHz

t 6V
SOURCE

44 M

*AJ's:reO~.~~ERAT'ON. TRIAC SHOULD

BE T23oo0,

Fig. 26 - On/off touch switch.

3-159

ow
~§
cc
"w:;;

~«

CA3240A, CA3240
Dual Level Detector (window comparator I

PC board grid, is converted to a voltage level
by the CA3240E in a circuit similar to that
of the on loff touch switch shown in Fig. 26.
The changes in voltage for both the upper
and lower level sensors are processed by the
CA3140 to activate an LED whenever the
liq uid level is above the upper sensor or
below the lower sensor.

Fig. 27 illustrates a simple dual liquid level
detector using the CA3240E as the sensing
amplifier. This circuit operates on the principle that most liquids contain enough ions in
solution to sustain a small amount of current
flow between two electrodes submersed in
the liquid. The current, induced by an 0.5-V
potential applied between two halves of a
12 M

LOW
LEVEL

92CM-30006

Fig. 27 - Dual level detector.

r-----------------------------------~~VO

Io-

2N6385
10K

DARLINGTON

100

K

loon

2.71<

INSI4

lOOK

o 05S",F
82K

000n

680
K

SOK

~--------~----------~--~~--~--~--~------_1--------_J~~
Vo RANGE

= 20 mV-

100 K

25 II

LOAD REGULATION'

In

IW

92CL- 30007

VOLTAGE < 008 %
CURRENT<005%
OUTPUT HUM AND NOISE. < ISO"V RMS
(10 MHz BANDWIDTH)
Cl:NE REGULATION· < a J %/vo
I.o RANGE-IOmA-I.3A

Fig. 28 - Constsnt-voltagelconstant-currsnt power supply.

3-160

CA3240A, CA3240

Constant-Voltage/Constant-Current Power Supply
The constant-voltage/constant-current power
supply shown in Fig. 28 uses the CA3240E
as a voltage-error and current-sensing amplifier. The CA3240E is ideal for this application
because its input common-mode voltage-range
includes ground, allowing the supply to
adjust from 20 mV to 25 V without requiring
an additional negative input voltage. Also,
the ground reference capability of the CA3240E allows it to sense the voltage across

,-

-

r

29 shows the transient response of the
supply during a 100-mA to l-A load transition,
Precision Differential Amplifier
Fig,30 shows the CA3240E in the classical
precision differential amplifier circuit. The
CA3240E is ideally suited for biomedical
applications because of its extremely high
input impedance. To insure patient safety, an
extremely high electrode series resistance is
required to limit any current that might

[

'T~

TOP TRACE: OUTPUT VOLTAGE
1500 mVlcm AND 5 __ s/cm)

"'1

,

BOTTOM TRACE COLLECTOR OF LOAD

... !

SWITCHING TRANSISTOR
LOAQ;IOOmA TOIA
(SVlcm AND 51's/em)

.,'!~\
,
¥ i '.'
,

92(;S-30034

TRANSIENT RESPONSE

Fig. 29 - Transient response.

the l-n current-sensing resistor in the negative output lead of the power supply. The.
CA3086 transistor array functions as a reference for both constant-voltage and constantcurrent limiting. The 2N6385 power Darlington is used as the pass element and may be
required to dissipate as much as 40 W. Fig.

result in patient discomfort in the event of a
fault condition. In this case, 1O-Mn resistors
have been used to limit the current to less
than 2 IlA without affecting the performance
of the circuit. Fig. 31 shows a typical
electrocardiogram waveform obtained with
this circuit.

+l5V

10M

GAIN
CONTROL

r'I
, I
I

~
TWO COND
SHIELDED
CABLE

FREQUENCV RESPONSE (- 3dBI DC TO I MHI
SLEW RATE- I 5V/". SIC
COMMON MODE REJ: 86 dB
GAIN RANGE: 35 dB -SOdB

-15V

92C:M-3OOO8

Fig. 30 - Precision differential amplifier.

3-161

CA3240A, CA3240

VERTICAL: I.OmVlDIV
{AMPLIFIER GAIN -IOOX'
(SCOPE SENSITIVITY. a.IV/OII/.
HORIZONTAL: >0 2 SEC/DIV (UNCAL)
92CS-30033

TYPICAL ELECTROCARDIOGRAM WAVEFORM

Fig. 37 - Typical electrocardiogram waveform.

Differential Light Detector
In the circuit shown in Fig. 32, the CA3240E
converts the current from two photo diodes
to voltage, and applies 1 V of reverse bias to
the diodes. The voltages from the CA3240E
outputs are subtracted in the second stage

(CA3140) so that only the difference is
amplified. In this manner, the circuit can be
used over a wide range of ambient light
conditions without circuit component adjustm.ent. Also, when used with a light source,
the circuit will not be sensitive to changes in
light level as the source ages.

+ 15V

RCA
C30909
PHOTO
DIODE

92CM-30009

Fig. 32 - Differential light detector.

3-162

CA3260A
CA3260

mHARRIS

BiMOS Operational Amplifiers
With MOSFET Input/CMOS Output

August 1991

Features

Description

• MOSFET Input Stage provides
~ Very High ZI = 1.5TO (1.5 x 1012 0) Typ.
~

Very Low II

CA3260A and CA3260 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
biploar transistors on a monolithic chip. The CA3260 series
circuits are dual versions of the popular CA3160 series.

= SpA Typ. at 1SV Operation
= 2pA Typ. at SV Operation

• Ideal for Single Supply Applications
• Common-Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can be Swung
0.5V Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either
(Or Both) Supply Rails

Applications

A complementary symmetry MOS (CMOS) transistor pair,
capable of swinging the output voltage to within 10
millivolts of either supply voltage terminal (at very high
values of load impedance), is employed as the output
circuit.

• Ground Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
o

Long Duration TimerslMonostables

• Ideal Interface with Digital CMOS
• High Input Impedance Wide-band Amplifiers
• Voltage Followers (e.g. Follower for Single Supply
DIA Converter)
• Voltage Regulators (Permits Control
Voltage Down to Zero Volts)

of

Gate-protected p-channel MOSFET (PMOS) transistors
are used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field-effect transistors In
the input stage results in common-mode input voltage
capability down to 0.5 volt below the negative supply
terminal, an important attribute in single supply
applications.

Output

• Wien-Bridge Oscillators
• Voltage Controlled Oscillators

The CA3260 Series circuits operate at supply voltages
ranging from 4 to 16 volts, or :1:2 to :1:8 volts when using
split supplies. The CA3260 Series Is supplied In standard 8
lead TO-5 style packages (T suffix) and 8 lead
dual-In-line formed lead TO-5 style "DIL-CAN" packages
(S suffix). The CA3260 is available in chip form (H suffix).
The CA3260 and CA3260A are also available in the 8 lead
dual-in-line plastic package (Mini-DIP E suffix). All types
operate over the full military temperature range of -55 0 C to
+125 0 C. The CA3260A offers superior input characteristics
over those of the CA3260.

• Photo Diode Sensor Amplifiers

Pinouts
ESUFFIX

SAND T SUFFIXES

(Pin compatible with the Industry standard 1458)
TOP VIEW

(Pin compatible with the industry standard 1458)
TOP VIEW

OUTPUT (A)
INV.
INPUT (A)
NON -INV.
INPUT (A)
V-

INV.
INPUT (AI

v+
OUTPUT (8)
INV.
INPUT (8)
NON -INV.
INPUT (8)

INV.
INPUT (8)

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

Copyright

© Harris Corporation 1991
3-163

File Number

1266.1

..J
«(I)

za:
-u:::

OW

~~

~~

o

CA3260A,CA3260

Fig. 1 - Schematic diagram of CA3260 series.

3-164

CA3260A, CA3260

ELECTRICAL CHARACTERISTICS for Each Amplifier at TA=25°C,
V+=15 V, V-=O V (Unless otherwise specified)

CHARACTERISTIC
Input Offset Voltage,
IVIO I, V±=±7.5 V
Input Offset Current,
1110 I, V±=±7.5 V
Input Current, II
V±=±7.5 V
Large-Signal Voltage
Gain, AOL
VO=10 V p_p, RL =10 kn
Common-Mode
Rejection Ratio, CMRR

LIMITS
CA3260A (T,S,E) CA3260 (T,S,E) UNITS
Min. Typ. Max. Min. Typ. Max.

-

2

5

-

6

15

mV

-

0.5

20

-

0.5

30

pA

-

5

30

-

5

50

pA

-

VN

-

dB
dB

50 k 320 k
94
80

110
95

-

-

50 k 320 k
94
70

90

0

-0.5
to
12

10

V

:z a:
ow
i=Li:


za:

ow
Fig. 3 - Block diagram of linearized VOA.

~~
w::;;

g;<
OUTPUT,
21 vp _p

Fig. 2 - VOA showing linearization diodes and
current drive.

14mV AGe
FEEDTHRU

400 "V

NOISE~

MAX. GAIN

15 kn

+15V

v-

2kn
SINGLEENDED
OUTPUT

DIFFERENTIAL
INPUT

2kn

Fig. 5 - Typical gain control circuit.

10kn

-15V

Fig. 4 - Differential to single-ended converter,

10

102

la'

104

10'

106

107

108

109

FREQUENCY (f)-Hz

Fig. 7 - Two-channellinear multiplexer.

Fig. 6 - Amplifier gain as a function of frequency.

3-171

CA3280A, CA3280

3.6kll
V...·+7.5V

200n
200n

v+'(}'-'VV'Ir--(~v-

Ikll

100kll

10kn

MIN.
FREQ.
SET

2 kll

500 II-

MAX. FREQ
SET

Fig. 8 - CA3280 used in conjunction with a CA3160

to provide a function generator with a
tunable range of from 2 Hz to 1 MHz.

Fig. 9 shows a triangle wave-to-sine wave converter using
the CA3280. Two 100KO resistors are connected between
the differential amplifier emitters and V+ to reduce the cur-

rent flow through the differential amplifier. This allows the
amplifier to fully cut off during peak input signal excursions. THO is approximately 0.37% for this circuit.

Fig. 9 - Triangle wave--to·sine wave converter.

v+

30V

OUTPUT

ov
IOkll

Ikn

Fig. 11 - Channel separation test circuit.

Fig. 10 - Leakage current test circuit.

3-172

CA3280A, CA3280

I a bc· 650 ".A

10 "200/,A
VERT -200,...A/DIV
HOR-I VlOIV

a) With diode programming terminal active

--'
«en
Za:

OW

Ikll

-u:

~~

~~

o
Iabe -650 pA
10-0
VERT- 200 "A/DIV
HOR- 25 mV/OIV

b) With diode programming terminal cut-off
Fig. 72 -

CA3280 transfer characteristics.

,
,
,

103a

10 a AMBIENT TEMPERATURE(TA)-Z!5-C

6 SUPPLY VOLTAGE(Ytl-ISV

"r-~'-rnr-~'-rn--r-~Ht~r-~ii

~

i

~
u

~

w

0

~

.,
., .,.....
,t::=:-

z
I

10'

2 AMBIENT TEMPERATURE RANGEITAI~FULL J~
TEMPERATURE RANGE

25·C

>
I

::r:::t=

~
Z

0

~

-1~-+--~+44--4--~4-t+--+--+-+~

(TAI'-~

~
~

~

g

/

~

~

..II
-5

6 8 10

4

6 8 10 2

2

4

0

25"C

-14

-55-<:
125-C

4

6 8 103

6 810

2

4

6 8 ,0 2

2

4

AMPLIER BIAS CURRENT (IABcl-I'A

AMPLIFIER BIAS CURRENT (IABC'-I'A

Fig. 15 -

2S-C
-5S·C

"

~

/

4

12S-C
14

~

~ -2~-+~+-+44--4--~4-t+--+--+-+~

~~ ·'1 I

. . . ., . , . , .

16 AMBIENT TEMPERATURE(TAI-2S.C
SUPPLY VOLTAGE (V:!:)-15Y

125°C

~

L

Fig. 14 - Input offset current as a function of
amplifier bias current.

current.

~

.;"

Ie"

AMPLIFIER BIAS CURRENT (IABC1-".A

Fig. 13 - Supply current as a function of diode

MBIENT TEMPERATURE

~.<

,~

.~']/ ./

./

./

10

DIODE CURRENT (ID) -".A

r--

V

V

,/

~

~

,"

~~~'(,

2f--+---~ '\t;..~
10 I-- ~~~..;;

~

I

~"

,

0

10

I
,;"

10'

~

z

«
«

~

SUPPLY VOLTAGE(v!:)-rsv

Input offset voltage as a function of
amplifier bias current.

Fig. 16 - Peak output voltage as a function of
amplifier bias current.

3-173

68 ,0 3

CA3280A, CA3280

10

10'
10'

1.

~

':l

.rr~ -t-IZSoC

1

8'

104 ~BIENT TEMPERAiURE ( A

~

10 2

Vj

!<

z

t#V
t}f

~ 10

~
~

:iI

I

~

~,

~

10-2

o

234567

-7,

10

- 0

DIFFERENTIAL INPUT VOLTAGE-V

~

~25°C

!i 1200

~
~

f--

ei

800

;;;

l - I-"
f-

__ l-

~

~ 600

f-I400 I4

,

68,0

r

I-

16

l'4

100

12

•

I50

17

f--P-.J-++I--+-+++f-t--t--H-l-r--t-Hi

~t-+~~++n-~~~-r~

.~ ~

HTl

. II

6 ' 102

,

4

. . I~

10

102

103

10'

10'

FREQUENCY if)-Hl

AMPLIFIER BIAS CURRENT (:[ABC)-,.A

Fig. 19 - Amplifier bias voltage as a function of
amplifier bias current.

Fig. 20 - I/F noise as a function of frequency.

10, SUPPLY VOLTAGE (V!.I-J5V

10

·,•
•
i ·,
.

I.,J~J

~~

1
~I028

r."~

of

,s-"
~~

~ 10

6
4

.'

I

t--,+12SoC

..'-~

~

6

+25°C

<,,'"

1l
~

I"

-..Y

.,

~

7.

~ ~:I-I\..~++tl--i--i-H+-+-+ttt-++t-H

I-f-m

J.-

1000

II

50

"!-.,.-..,-rrr-,-..,-rrr--ri-Hi-ri-m

J.1

MPERAiURE l A
AMBIENt tE

~r400

25

temperature.

~~

~

0

24 AMBIENT TEMPERATURE (TA)'zeoC

11

SUPPLY VOLTAGE(Vt)-15V

Vv

Fig. 18 - Leakage current as a function of

1800
E 1600

25

AMBIENT TEMPERATURE ITA) _&C

Fig. 17 - Input current as a function of input
differential voltage.
>

.

~~ t-~

10-t

I

~

r-il2~·1

-'Z·C.#f'

.

I~i'n
,

6 ' 10

,

.

6,

10'

,

AMPLIFIER BIAS CURRENT UABCI-p.A

.

L....-"IO'-;I=O_:OI'-L..L.'CI-'-'-.....",O~'---'-'-C,:::O',...~~IO"~~~,O.

6 ' 10'

DIODE CURRENT (Iol-p.A

Fig. 22 - Diode resistance as a function of diode
current.

Fig. 21 - Peak output current as a function of
amplifier bias current.
10

SUPPLY VOLTAGE (V:!)-IS V

104 SUPPLY CURRENT (Vt)-IS v

10'

,a-'
10-3

10-2

10-1
I
10"
10
102
AMPLIFIER BIAS CURRENT IIABCI-p.A

I
10
10 2
AMPLIFIER BIAS CURRENT (lABel -p.A

_10 4

Fig. 23 - Amplifier gain as a function of amplifier
bias current.

10'

Fig. 24 - Supply current as a function of amplifier
bias current.

3-174

CA3280A, CA3280

l.l~~

~

~'O'

~,,?«,'f

.

~<

~

.....,.~'~

~ 10 2

B
0

ill

JI

III

10 4 SUPPLY VOLTAGE (V±)-15V

'- I-

"\~

+Z5.C
+12S·C

~

[:;;<'

~

~ 10

'"
1

-

10 1

I

10

10 2

AMPLIFIER BIAS CURRENT (:[ABC)-I'A

Fig. 25 - Input bias current as a function of amplifier

bias current.

-'


AMBIENT TEMPERATURE (TAI-2S-C
RL.- 1OOKn

08

+------1

~~06r_----~----_+----~
~~

~~ O.4r_----~----_+----__j
..g

~i O·'E~~~:§~VO~-~~
~~ 0
~~-o2

I
I
I

~~~8~-----~-----+----~

L~~~-2-Ik-+,,~~~~-L-L-L-L~.,L~~~~
o IV
5\1
la'll
ISV

OTA BUFFER

HIGH GAIN
150 K I

IX 21

SUPPLY

Fig. 2 - Output-voltage-swing and common-mode input-voltage

Fig. 1 - Functional diagram lor CA3420.

2 LO

VOLTAGE IV+,V-I-V
92CS-34401

92C5-34156

~

VTrA-

8i~6~========~----~;;~-~--~
~~
VIeR +

I
I
BUFFER AMPS; I
BOOTSTRAPPED I
INPUT PROTECTION I
NETWORK
I

vat

g~
~~-04

I

I

SUPPLY VOLTAGE IV-I=OY

AMBIENT TEMPERATURE ITA 1 ~25gC

I

range versus supply voltage.
-'
< en
r::r::
:z
w
;::: ;:;:

I

0

'5

--"-

Y+.+2V
---y+-tSV
------- vt·t 10 v

~

a::

~~6

__ :.~

~_1108

::::;
<
r::r:: c.

/V
yo

2

w ::;;

c.
0

---vt~+20V

~

~~
~g
:

___

~~\

2

~-

---- v-·-·IOV

§
1000 8

\I

10
46'b,

-

- - - Y-.-IOV
II1

~

0001

Y-=-2V

I--- ------- ", .. -5 V

468,

468

468'0

001

LOAD (SOURCING) CURRENT-mA

I

468

01

1

468

I

10

J,-OAD ISINKINGICURRENT-mA

92CS-3440Z

92CS-34403

Fig. 4 - Output voltage versus load sinking current.

Fig. 3 - Output voltage versus load sourcing current.

"\

10

102

10 3
FREQUENCY -Hz

104

10 5

10

106

10'

"" '"

10'

10'

~
10'

FREQUENCY (Hzl

92CS-34404

Fig. 6 - Open-loop gain and phase-shift response.

Fig. 5 - Input noise voltage versus frequency.

3-179

<

CA3420A, CA3420
Application Circuits

IOkM.n

Plcoameter Circuit

The exceptionally low input current (typically 0.2 pAl
makes the CA3420 highly suited for use in a picoameter
circuit. With only aSingle 10K megohm resistor, this circuit
covers the range from ±1.5 pA. Higher current ranges are
possible with suitable switching techniques and current
scaling resistors. Input transient protection is provided by
the 1-megohm resistor in series with the input. Higher
current ranges require that this resistor be reduced. The
10-megohm resistor connected to pin 2 of the CA3420
decouples the potentially high input capacitance often
associated with lower current circuits and reduces the
tendency for the circuit to oscillate under these conditions.

1.5k
1.5k,l%

Ik
430.0.,1%
-1.5V
±1.5 pA

150.!l..I%

6eA

Ilk

Hlgh-Input-Reslstance Voltmeter

Advantage is taken of the high input impedance of the
CA3420 in a high-input-resistance dc voltmeter. Only two
1.5 V "AA" type penlite batteries power this exceedingly
high-input resistance (>1,OOO,OOO-megohms) dc voltmeter.
Full-scale deflection is ±500 mV, ±150 mV, and ±15 mY.
Higher voltage ranges are easily added with external input
voltage attenuator networks.

1%

92CS-34002

Fig. 7 - Picoameter circuit.

+1.5V

The meter is placed in series with the gain network, thus
eliminating the meter temperature coefficient error term.
Supply current in the standby position with the meter
undeflected is 300 /LA. At full-scale deflection this current
rises to 800 /LA. Carbon-zinc battery life should be in excess
of 1,000 hours.

1.5k
1.5k,l%

Ik
430.0.,1%
150.0.,1%

±15mV
1.1 k

92CS-34004

Fig. 8 • High input resistance voltmeter.

3-180

(II

CA3440A
CA3440

HARRIS

Nanopower BiMOS Operational Amp

August 1991

Features

Description

o

Standby Power at v+ = 5V ••.•••••••••• 300nW (Typ)

o

Supply Current, BW, Slew Rate Programmable Using
External Resistor

• Input Current ••••••••.••••••••••••••••• 10pA (Typ)
• 5V to 15V Supply
• Output Drives Typical Bipolar-Type Loads
o

Low Cost a-Lead Mini-DIP, TO-5

The CA3440A and CA3440* are integrated circuit operational amplifiers that combine the advantages of MOS and
bipolar transistors on a single monolithic chip.
The CA3440A and CA3440 BiMOS op amps feature gateprotected PMOS transistors in the input circuit to provide
very high input impedance and very low input current
(10pA). These devices operate at total supply voltage from
SV to lSV and can be operated over the temperature range
from -SSoC to +12SoC. Their virtues are programmability
and very low standby power consumption (300nW). These
operational amplifiers are internally phase compensated to
achieve stable operation in the unity gain follower configuration. Terminals are also provided for use in applications
requiring input offset voltage nulling. The use of PMOS in
the input stage results In common-mode input voltage
capability down to O.SV below the negative supply terminals, an important attribute for single supply applications.
The output stage uses MOS complementary source follower form which permits moderate load driving capability
(10KO) at very low total standby currents (SOnA).
The CA3440A and CA3440 have the same 8-lead terminal
pin-out used for "741" and other Industry standard op
amps with two exceptions: terminals one and five must be
connected to the negative supply or to a potentiometer if
nulling Is required. Terminal 8 must be programmed
through an external resistor returned to the negative supply.
These devices are supplied In either the standard 8-lead
TO-S style package (T suffix), 8-lead dual-in-line formedlead TO-S style "OIL-CAN" package (S suffix), or in the
8-lead dual-in-line plastic package "Mini-DIP" (E suffix).
"Formerly Cev. Type No. TAl 0590.

Pinouts
SAND T SUFFIXES
TOP VIEW

ESUFFIX
TOP VIEW

V·/
OFFSET
NULL

INV.
INPUT
NON -INV.
INPUT

INV. 2
INPUT

ISET

V+
OUTPUT

V -/
OFFSET
NULL

V·
CASE

FIGURE 1.

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

3-181

File Number

1318.1

...J

«en
za::

OW

-u:::

~~
w::;:
~«

CA3440A, CA3440
MAXIMUM RATINGS. Absolute-Maximum Values:
DC SUPPLY VOLTAGE
(BETWEEN V+ AND V- TERMINALS) •....•...••.•...••.••••..•.•..•••.•..•.•.••..•.•••.•..•.•..••.•....•••.•.••.••.•..•. 25 V
DIFFERENTIAL-MODE INPUT VOLTAGE .•.••.•....•.•••..••..••.....•••••....•.•..•.••.•..•••••..••.•••••.•..•.•..•.•••••• ±9 V
COMMON-MODE DC INPUT VOLTAGE .•.•.•.•••••.•••••.••..•••••••••••.••••.••••••••••••.•••..•••••... (V+ +8 V) to (V- -0.5 V)
INPUT-TERMINAL CURRENT ••...•.•.••..•.........•.•.•.•..•.•..••.•••.•..•.•.••..••••.•..••••...•..•.••....•.•.•.•..•... 1 rnA
DEVICE DISSIPATION:
WITHOUT HEAT SINKUP TO 55'C ••••••..••..•..•.•....•.•.••.••.••.•.•••••••••.••.•••.••...•..•.•.••...•.••.••.••••.•....•....•...••.••. 630 mW
ABOVE 55'C •.•...•..••..••..•.•..•..•.•...•...•..•..•.•.....•..•••.•..•.•.......••.•........•.•. Derate linearly 6.67 rnW/'C
WITH HEAT SINKAT 125'C ••.•••..•..•...••...••.•.•.•.•••••.•.•..•..•••.••.•.......•..••....•.•....•.••..•..••..•.........•.•...•.•. 418 rnW
BELOW 125'C ••••.•.•••.•.•.•..•..•..••.....•.....•....••.••.••...•..••••.•.......•.•..••...•.... Derate linearly 16.7 rnW/'C
TEMPERATURE RANGE:
OPERATING ..•••.•..••..••.•.....•....••..•...•...•.....•....•.........•..•.•....•..•.....•..•....•••..•..... -55 to +125' C
STORAGE .....•.•....••.••.••.•....•...••.•.......•..•...•••..•..•..••.••....•.•............•.•....•...••....• -65 to +150' C
OUTPUT SHORT-CIRCUIT DURATION ••..••.•.••....•.•••..•.......•.•..•.•......•..•.•.........•..•........•..•... INDEFINITE
LEAD TEMPERATURE (DURING SOLDERING):
AT DISTANCE 1/16 ± 1/32 IN. (1.59 ± 0.79 MM) FROM CASE FOR 10 SECONDS MAX...•..•..•..•..•.•....•.•..•.....•. +265'C
TYPICAL VALUES INTENDED ONLY FOR DESIGN GUIDANCE
TEST CONDITIONS
Y+=+5 Y; Y-=-5 Y

CHARACTERISTIC

CA3440A

CA3440

UNITS

RSET=10 MO; TA=25'C
I nput Resistance. RI

2

2

TO

Input Capacitance. CT

3.5

3.5

pF

Ouput Resistance. Ro

450

450

0

110

110

110

110

15

15

4.5

4.5

Equivalent Input

1= 1 kHz

Noise Voltage. en

1=10 kHz

I

I RS=100 0

nVlvHz

Short-Circuit Current
Source IOM+

mA

To Opposite Supply
Sink IOMGain-Bandwidth Product. IT
Slew Rate. SR

63

63

kHz

0.03

0.03

Vips

Transient Response
Rise Time. tr

RL= 10kO

5.6

5.6

ps

Overshoot

CL=100 pF

10

10

%

~~ 1.• I-----I======1~-='y.:.'o~--___1

SUPPLY VOLTAGE yt_+5V, Y-. -5V

v

~~ 1.21__----1__-------1r----___i

2g

AMBIENT TEMPERUURE ITA J-Z5·C

~~ Q B I - - - - - + R L -100 ICO

u.

~~Q41__----I__---~I__---___i

~~

IY+OO V-)

~~ ol__----I__~~~-I__---___i

~~~O.41-----I-----I-------l
~Q

~~.8,1-------Ff_==-=+~=y,::c="-=--l
~~-1.21-----F=-=-~::-='y'-C-,R.------I
~~-161-------t-f-----+-----l
-4

~
!5V
lOY
SUPPLY VOLTAGE IY+,Y-}-Y 9lC!t-MIt8

15V

10

100

4

6 ~ooo

SUPPL.Y CURRENT I ISJ-nA

4

6 '0.000

92CS-Zl4a97

Fig. 2 - Set current versus supply current.

Fig. f - Output-voltage-swing and common-mode input-voltage
range versus supply Voltage.

3-182

CA3440A, CA3440

ELECTRICAL CHARACTERISTICS FOR EQUIPMENT DESIGN
At v+ = +5 V, V- = -5 V, TA = 25·C Unless Otherwise Specified, RSET=10 MQ
LIMITS
CA3440A

CHARACTERISTIC
Min.

Typ.

CA3440
Min.

Typ.

-

5

10

2.5

30

10

50

10K

100K

-

80

100

-

dB

-

100

320

pVIV

Input Offset Voltage, IVIOI

-

2

5

Input Offset Current, 11101

-

2.5

20

Input Current, IIII

-

10

40

10K

100K

(RL=10 KQ)

80

100

Common-Mode

-

-

100

320

Large-Signal Voltage Gain, AOL

mV
pA
VIV

70

80

-

dB

+3.7

-5.0

-5.3

-

V

320

-

32

320

pVIV

-

70

90

-

dB

+3.2

-

+3
-3

+3.2

-3.2

-3.2

-

V

80

+3.5

+3.7

Voltage Range,

-5.0

-5.3

-

l:..VIOIl:..V

-

32

PSRR

70

90

+3
-3

VICR-

Max.

+3.5

70

Common-Mode Input VICR+

Rejection Ratio, CMRR

UNITS

Max.

Power Supply Rejection Ratio,

Maximum Output Voltage,
VOM+
VOM-

-

10

17

-

10

17

pA

Device Dissipation, Po

-

100

170

-

100

170

pW

Input Offset Voltage Temperature

-

4

-

-

4

-

pV/· C

10

SET CURRENT IISET)· I"A

e~~--+--+--+--4-

1;.

6~~~t--+--+--4-'~~

~

o

>=
~

""z
~

It ~

>

I
;:;

in

I

°
-.
.'.
: -.

SUPPLY VOLTAGE Vt- .... SV. V-=-5V
AMBIENT TEMPERATURE (TAI-2SoC

E
z

a::<>w:;;

:5«

Supply Current, 1+

Drift, l:..VIOIl:..T

~

....I
«

12 PRO~eR_~.~b~'b ~nSI!'OSTO~R--'____I__
-"v-,.+,--,.-v-----4

:.'.

~I~------~------~--+---~----~

I'"

V""~V-'"

\.

~ e
~

V"',Y-. 'tZ5V

6;~------~------~~~--~----~

+ V-·+SV

~ 41~------~~V-·'~.5~V~_7~--_t------~

V • y. -!IOV

g
~~
~ 2r-~~~~~~~F-----~~----_l
001 2

4

61101

2
4 6 8 1 2
4 68 10 2
4 6 8 100
LOAD SINKING CURRENT-mA
9leS-3.,12

10

"

6 8 102
2
FREQUENCY-Hz

810~

2

4

6 8104

9ZCS-34301

Fig. 6 - Input noise voltage versus frequency.

Fig. 5 - Output voltage versus sinking load current.

3-183

CA3440A, CA3440

10",

10 :

10

102
SET CURRENT

2

10'

U:•• I-,J.

468'0

.. 68'022

468'032

4681042

468,0'

SET CURRENT (I. •• , I-"A

92CS-IU03

Fig. 7 - Bandwidth versus set current.

Fig. 8 - Slew rate versus set current.

STAGE I
(HIGH GAIN]
100 db

STAGE 2

BU FFER]
[ LOW Z
OUTPUT

l.

92CS-34S04

Fig. 9 - Nanopower op amp (supply current programmable using
RSET) 1-pA typicalinput bias current. 4.0 to 15-volt supply.

+5V

As RSET is increased.ISET and the standby power decrease
while the BW/SR also decreases.
Operating at a +5 V single supply. the CA3440 exhibits the
following characteristics:
Standby

RSET
1 MO
10 MO
100 MO
1000 MO
92CS-54S05

Fig. 10 - Nanopower op amp (usable standby power versus
programming resistor RSET).

Power
250pW
25pW
2.5pW
250 nW

BW
164 kHz
27 kHz
2.6 kHz
7BHz

SR

0.17 VIps
0.017 VIps
.0017 VIps
0.00017 VIps

The CA3440 is pin-compatible with the 741 except that pins
1 and 5 (typical negative nulling pins) must be connected
either directly to pin 4 orto a negative nulling potentiometer.
In addition. pin B. the ISET terminal. must be returned to
either ground or -V via RSET.

3-184

CA3440A, CA3440
r-----.---_4~----------~----~-------4~------_.----~--_{7

V+

R2
30
~VV\4----------1___{6

OUTPUT

INVERTING
INPUT

-'

«en

za:
ow

~~
~~

o
Fig. 11 - Schematic diagram far CA3440.

92CM-!430S

APPLICATIONS CIRCUITS

+ 9V

4.7 Mil

2.2MlI
INPUT
()--jf--l~r-----Q)--l

22 Mil

OUTPUT
6
9,11

500pF

IOMa

4.7 Mil
Rin>20 MQ.
5TANO-BYPOWER-90~W

GAIN- 20db
BW' 20-Hz TO 3- KHz
SR- 0.016 V/~.
92CS-34309

Fig. 12 - High-input impedance amplifier.

Fig. 13 - Micrapawer bandgap reference.

3-185

mHARRIS

CA3450
Video Line Driver,
High-Speed Operational Amplifier

August 1991

Features

Description

• High Open Loop Gain at Video Frequencies

The CA3450* is a large signal video line driver and high
speed operational amplifier capable of driving 50n transmission lines and flash NOs. The uncompensated unity
gain crossing occurs at 230M Hz without load. It can operate dual or single supplies of ±7.25V or 14.5V, respectively.
The CA3450 can be compensated with a single capacitor
network. It has output drive capability of 75mA SINK or
SOURCE. The CA3450 is capable of driving Flash NO's in
video or high-speed instrumentation (accurate) applications with bandwidth up to 10MHz. Offset voltage nulling
terminals are also available.

I>

AOL ••••••••••••••••••••••••• >40dBatf=5MHz

• Power Bandwidth of 10MHz; AClosed Loop = 5;
Vo ±3.5V

=

• Slew Rate at Full Load ••••••••• 330V/llsec (AV ~ 10)
• fT = 220MHz; Cc = OpF With a Load of son 1120pF II
1MO (Scope Input)
• VOUT

=±4.1V Into 750

• Offset Null Terminals

The CA3450 is available in a l6-lead dual-in-line plastic
package (E suffix).

Applications

"Formerly RCA Development Type No. TA11371A.

• Video Line Driver
• High-Frequency Unity Gain Buffer
• Pulse Amplifier
• High-Speed Comparator
• High-Frequency Oscillator and Video Amplifiers
• Driver for AIDs in Video Applications ••••• 10MHz BW

Block Diagram

Pinout
16 PIN PLASTIC DIP
TOP VIEW

1

1

~

OFFSET
NULL

9

11

~

. PHASE

COMP

FIGURE 1.

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

Copyright

© Harris Corporation 1991

3-186

File Number

1732.1

CA3450
MAXIMUM RATINGS, Absolute-Maximum Values
DC SUPPLY VOLTAGE (BE1WEENV+ AND V-TERMINAL) ...................................................................... 14.5V
DIFFERENTIALINPUTVOLTAGE .............................................................................................. ±5V
DEVICE DISSIPATION:
Upt0550 C ............................................................................................................. 1.5W
Above 550 C ....................................................................................... Derate linearly at 16.6 mWfOC
OUTPUT CURRENT (SINK OR SOURCE) ..................................................................................... 100 mA
TEMPERATURE RANGE
Operating ..................................................................................................... , -400 C to 850 C
Siorage ....................................................................................................... -650 C to 15QOC
MAXIMUM JUNCTION TEMPERATURE.. • . . . • • • . • • • . . .. • • . .. • .. . . . .. • • • .. . • • .. • .. • . . • • .. • • • .. . .. • . • .. .. . .. . .. • • • • . .. . . . .. . . .. 15QOC
MAXIMUM THERMAL RESISTANCE
Junction to Air (8J-A) .................................................................................................. 600C/W
Junction to Case (8J-C) ................................................................................................ 120 C/W
To pins 4, 5,12, 13 at seat

ELECTRICAL CHARACTERISTICS, At TA = 250 C, Cc = 5 pF, V+, V- = 6 V*
LIMITS
CHARACTERISTICS

CONDITIONS

MIN.

TYP.

TA = -400C to 85 0C

-

Input Bias Current,lllB I

TA=250 C

-

100

400

Input Offset Current, I110 I

TA=250C

-

Open Loop DC Gain, AoL

VOUT = ±2.5 V; RL = 50 n

MAX.

UNITS

8

20

mV

10

35

STATIC
Input Offset Voltage, IVIO I

TA=250 C

I -400C to 850C
I 250 C

50

200

55

-

-

60

70

-

-

Power Supply Rejection Ratio, PSRR

AV=±1 V

55

65

Common-Mode Rejection RatiO, CMRR

VICR± = ±3.5 V

50

60

Common-Mode Input Range, VICR

TA = -400 C to 850 C

±3.0

-

TA=250 C

±3.5

±3.7

-

-

50

30

40

Supply current, I

TA=-400Cto850 C
TA=25 0C

nA

dB

V

mA

*AII test are performed with ± 6 volts at the terminals of the device.

A 10 ohm, V. watt supply decoupling resistor is shown in all application
circuits of this device. The resistor serves two purpose, first provides a

means of decoupling the IC directly at its terminal without introducing

additional supply resonance due to parallel connected capacitors.
Secondly, it also provides protection for the device in event of a
substained short circuit applied direclly to the output terminals.

3-187

-'

IL

""z

I-

a.

9
9

100

~

w w

10

........

c

w
rn

I

. .'" ~ r--

~

0

~

Z

PHASE

0

(.)

...... 1"-

1111
1111

-10
1

10

'\
\

,

100

o

f[

45

IX:

90

-'
>

:;

W

I-

lil

-

-'

a 0>
w

w

10

0'"

e.

z

w

135 ~

::t:

1\

180 a.
300

10

10 2

FREQUENCY (MHz)
Figure 11 - Closed loop gain and phase vs frequency.

10 3

10 4

FREQUENCY - Hz

(AV = 10)

Figure 12 - Curve showing the equivalent input noise "en" of the op amp.

l00r-~-'-rTTnmr-~-'-rTT~r--'

90~-4~~+++H~-4~~+++H~-4

10.0
9.0

OOr--+-+-rHH+*---r-r++++~~

Wr--+-+-HHH+*---r-r++++~~

~

AV=10
Cc=O pF

RL=66onJl20pF

8.0

~~ 7.0

-RL=50aIl20pF-

00

,,>
ct.

w"

6.0

"-z
~ j; 5.0

«'"

~~ 40

:;«

~~

3.0

><>
<
2.0

10r--+-;-rt+~r--+-;-rt+~r--;

oL-~~~~~ITTIHL~
1
10
100 200
FREQUENCY (MHz)
Figure 13 - Output resistance vs frequency.

:;

1.0
O.OL-_-1_ _-'-_...L---L--'--_ _-'---_ _-'--'_LJ.,.-_-'-_=
1
FREQUENCY (MHz)

Figure 14 - Output voltage as a function of frequency for the CA3450
3-191
under various loads.

CA3450

5pF

r-----:-......-

......-'IIVV-o + 6V

75A

220A

lOA
0.1 t--p--'VI/'v--O
-6V

-!- -!-

4.7,.F

Figure 15 - Configuration used to measure differential gain and phase.

+8 V

Ion
75 OHM
IV p _ p

VIDEO
INPUT

Ion

16
AID FLASH

390

Ion

-4V

750

21

INPUT

110

0·1

o TO -IOV
OFFSET SOlJRCE
RS < Ion
Figure 16 - Typical high-bandwidth X5 amplifier for driving the CA3318 Flash NO.

3-192

o

TEKTRONIX 520A
NTSC VECTORSCOPE

CA3450

R7

6

OUTPUT

FREQUENCY
COMPENSATION
~----+---~--{)9

-'
<(I)

R'

za:

lOOK

OW

~u:::

a:~

w:;;

&<
R9
780

R'O
3.2K

Figure 17 - Full schematic diagram of the CA3450.

f-----------I

a 6 ( 2.692)

--_.

M-Sondlng wire to Chip Mounling Pad.
Pins 12 and 13 Connected 10 Chip MounlLng Pad.
No Chip Pads lor 2,10.12.13.15

Figure 18 - Dimensions and pad layout for CA3450H.

The photographs and dimensions of each CMOS chip represent a chip
when it is part of the wafer. When the wafer is separated into individual
chips, the angle of cleavage may vary with respect to the chip face for
diflerent chips. The actual dimensions of the Isolated chip, therefore, may
differ slightly from the nominal dimensions shown. The user should

consider a tolerance of -3 mils to +16 mils applicable to the nominal
dimensions shown.
Dimensions in parentheses are in millimeters and are derived from the
basic inch dimensions as indicated. Scale graduations are in mils (10-3
inch).

3-193

(II

CA5130A
CA5130

HARRIS

BiMOSMicroprocessor Operational Amplifiers
With MOSFET Input/CMOS Output

August 1991

Features

Description

• MOSFET Input Stage
~ Very High ZI •••••••••••• 1.5 TO (1.Sx 10 120) Typ.

CA5130A and CA5130 are integrated-circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip. They are designed
and guaranteed to operate in microprocessors or logic
systems that use +5V supplies.

~

•
•

•
•
•
•

Very Low II ••.•••••••••• SpA Typ. at 1SV Operation
2pA Typ. at SV Operation
Ideal for Single-Supply Applications
Common-Mode Input-Voltage Range Includes
Negative Supply Rail; Input Terminals Can Be Swung
O.SV Below Negative Supply Rail
CMOS Output Stage Permits Signal Swing to Either
(or Both) Supply Rails
CAS130A, CAS130 Have Full Military Temperature
Range Guaranteed Specifications for V+ SV
CAS130A, CAS130 Are Guaranteed to Operate Down
to V+ = 4.SV for AOL
CA5130A, CA5130 Are Guaranteed to Operate at
±7.5 CA3130A, CA3130 Specifications

=

Applications
•
•
•
•
•
•
•
•
•
•
•
•

Ground-Referenced Single Supply Amplifiers
Fast Sample-Hold Amplifiers
Long-Duration Timers/Monostables
High-Input-Impedance Comparators (Ideal Interface
with Digital CMOS)
High-Input-Impedance Wideband Amplifiers
Voltage Followers (e.g. Follower for Single-Supply
D/A Converter)
Voltage Regulators (Permits Control of Output
Voltage Down to Zero Volts)
Peak Detectors
Single-Supply Full-Wave Precision Rectifiers
Photo-Diode Sensor Amplifiers
5V Logic Systems
Microprocessor Interface

Gate-protected p-channel MOSFET (PMOS) transistors
are used in the input circuit to provide very-high-input
impedance, very-low-input current, and exceptional speed
performance. The use of PMOS field-effect transistors In
the input stage results in common-mode input-voltage
capability down to O.5V below the negative-supply terminal,
an important attribute in single-supply applications.
A complementary-symmetry MOS (CMOS) transistor-pair,
capable of swinging the output voltage to within 10mV of
either supply-voltage terminal (at very high values of load
impedance), is employed as the output circuit.
The CA5130 Series circuits operate at supply voltages
ranging from 4 to 16 volts, or ±2 to ±8 volts when using
split supplies. They can be phase compensated with a sin·
gle external capacitor, and have terminals for adjustment of
offset voltage for applications requiring offset-null capabili·
ty. Terminal provisions are also made to permit strobing of
the output stage.
The CA5130 Series is supplied In standard 8-lead TO-5
style packages (T suffix) and 8-lead dual-in-line formed
lead TO-5 style "DIL-CAN" packages (S suffix). The
CA5130 is available In chip form (H suffix). The CA5130
and CA5130A are also available in the a-lead Small Outline
package (M suffix) and in the 8-lead dual-in-line plastic
package (Mini-DIP E suffix).
The CA5130A, CA5130 have guaranteed specifications for
5V operation over the full military-temperature range of
-550 C to +1250 C.

Pinouts
SAND T SUFFIXES

E AND M SUFFIXES

TOP VIEW

TOP VIEW
OFFSET
NULL
INV.
INPUT
NON -INV.
INPUT

INV.
INPUT

V-

STROBE
V+
OUTPUT
OFFSET
NULL

4
V- AND CASE
FIGURE 1.
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-194

File Number

1266.1

CA5130A, CA5130
MAXIMUM RATINGS, Absolute-Maximum Values
DC SUPPLY VOLTAGE
(Between V+ and V- Terminals) .•.••..•.. " .•••.... , ....••..••.•••...••••.••.••..••..•••..•...... '" ...••...•.••...•........ 16 V
DIFFERENTIAL-MODE INPUT VOLTAGE .••.••••.••.•••..••...•...•.......•..•.....•..•.......•.••..••.••.................... ±8 V
COMMON-MODE DC INPUT VOLTAGE ...................................................................... (V+ +8V) to (V- -0.5V)
INPUT-TERMINAL CURRENT .....••.•..•.••..........•.•..••.•....•..•..•..........•..••...•..•••..••........•...•.••.••••.• 1 mA
DEVICE DISSIPATION:
WITHOUT HEAT SINKUP TO 55°C .......................................................................................................... 630 mW
ABOVE 55°C ••.•.....•.•...••......•..•...••..•.....••.••..••.•••.••.•..•..•.......••••..••.••••.• Derate Linearly 6.67 mW/oC
WITH HEAT SINKUPT090°C .............................................................................................................. IW
ABOVE 90°C ...................................................................................... Derate Linearly 16.7 mW/oC
SMALL OUTLINE PACKAGE ............................................................................................ 250 0 /W
TEMPERATURE RANGE:
OPERATING (all types) ........................................................................................... -55 to +125°C
STORAGE (all types) ............................................................................................. -65 to +150°C
OUTPUT SHORT-CIRCUIT DURATION· .............................................................................. INDEFINITE
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1132 inch (1.59 ± 0.79 mm) from case for 10 seconds max................................................ +265°C

• Short circuit may be applied to ground or to either supply.

r-----,'----------,
BIAS CIRCUIT

I I CURRENT

SOURCE FOR Q6 AND Q7

7 v+

I

--'
«(J)
:z a:
ow

i=LL

«::i
a:D..
w::;;

g,«
I I
I I

ZI
B.3V

II

RI

I I
I I

40kn

Q5

R2

SECOND
STAGE

.------

I OUTPUT

I STAGE
I

I

I
I
I
I
I
I
I
IL __ _
NOTE:
DIODES 05 THROUGH DB PROVIDE GATE-OXIDE PROTECTION
FOR MOS/FET INPUT STAGE.

Fig. 2 - Schematic diagram of the CA5130 series.

3-195

CA5130A, CA5130
ELECTRICAL CHARACTERISTICS AT T" = 25'C, y+ = 5 Y, Y- = 0 Y
LIMITS
CHARACTERISTIC

Input Offset Voltage

CA5130A
MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

V'O

-

1.5

4

-

2

10

1'0

-

0.1

5

-

0.1

10

I,

-

2

10

-

2

15

Vo = 2.5 V
Input Offset Current
Vo = 2.5 V
Input Current

CMAA
75

87

-

70

85

CMAR

60

69

-

60

69

-

V'CR+

2.5

2.8

2.5

2.8

-

-

-

V'CR-

-0.5

0

-

-0.5

0

60

75

-

55

73

VCM = 0 to 1 V
VCM = 0 to 2.5 V

mV

pA

Va = 2.5 V
Common-Mode Rejection Ratio

UNITS

CA5130

dB

Input Common-Mode Voltage Range

Power-Supply Rejection Ratio

PSRR

~+ = 1 V; ~- = 1 V

Large-Signal Voltage Gain·

dB

AOL

Va = 0.1 to 4.1 V

RL = 00

100

105

105

RL = 10 k

90

97

-

95

Vo=0.lt03.6V

85

95

-

1.0

3.1

4.0

1.0

2.6

4.0

1.0

1.6

4.0

1.0

1.7

4.0

4.99

5

-

-

0

0.Q1

4.4

4.7

-

-

0

0.01

Source Current

ISOURCE

Vo=OV
Sink Current
Vo·= 5V
VOUT

RL = 00

VOM+

4.99

5

-

-

VOM-

0

0.01

VOM+

4.4

4.7

-

-

VOM-

0

0.01

VOM+

2.5

3.5

2.5

3.5

-

-

0

0.Q1

-

-

VOM-

0

0.Q1

-

50

100

50

100

260

400

-

260

400

RL = 2 k
Supply Current

V

ISUPPLY

Vo=OV
Va = 2.5 V

rnA

IS'NK

Output Voltage

RL = 10 k

V

ISUPPLY

·For V+ = 4.5 V and V- = Gnd; VOUT = 0.5 V to 3.2 V at RL = 10 k.

3-196

IlA

CA5130A, CA5130
ELECTRICAL CHARACTERISTICS AT TA = -55°C to +125°C, V+ = 5 V, V- = 0 V
LIMITS
CHARACTERISTIC

CA5130A

MAX.

MIN.

TYP.

MAX.

-

2

10

-

3

15

1,0

-

0.1

5

-

0.1

10

I,

-

2

10

-

2

15

V,O

Vo = 2.5 V
Input Offset Current
Vo = 2.5 V
Input Current

C MRR
60

80

80

55

80

-

60

CMRA

50

80

-

V,CA+

2.5

2.8

-

2.5

2.8

-

V'CR-

-

-0.5

0

-

-0.5

0

45

70

-

40

66

-

VCM = 0 to 1 V
VCM = 0 to 2.5 V

mV

nA

Vo = 2.5 V
Common-Mode Rejection Ratio

UNITS

TYP.

MIN.
Input Offset Voltage

CA5130

dB

Input Common-Mode Voltage Range

Power-Supply Rejection Ratio

..J

dB
AOL

Vo = 0.1 to 4.1 V

RL = QQ

94

98

-

90

98

Vo = 0.1 to 3.6 V

RL = 10 k

80

88

-

75

85

-

0.6

2.2

5.0

0.6

-

5.0

0.6

1.15

5.0

0.6

-

5.0

4.99

5

-

-

0

0.01

4.0

4.6

-

-

0

0.01

Source Current

ISOUACE

Vo =OV
Sink Current
Vo = 5 V
VOUT

RL = QQ

VOM+

4.99

5

-

-

VOM-

0

0.Q1

V OM +

4.0

4.6

-

VOM-

-

0

0.01

V OM +

2.0

3.0

-

2.0

3.0

-

VOM-

-

0

0.Q1

-

0

0.01

-

80

220

-

80

220

-

300

500

-

300

500

RL = 10 k
RL = 2 k
Supply Current

V

ISUPPLY

Vo=OV
Vo = 2.5V

rnA

ISINK

Output Voltage

ISUPPLV

'For V+ = 4.5 V and V- = Gnd; VOUT = 0.5 V to 3.2 V at RL = 10 k.

3-197

OW

~§

a: c..
w:;;
~«

PSAA

t.+=1V;t.-=1V
Large-Signal Voltage Gain'

«en
za:

V

I1A

CA5130A, CA5130
ELECTRICAL CHARACTERISTICS AT TA = 2SoC, y+

= 1S Y, Y- = 0 Y (Unless olherwlse specified)
LIMITS

CHARACTERISTIC

Input Offset Voltage

CA5130A
MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

V'O

-

2

5

-

8

15

mV

"0

-

0.5

20

-

0.5

30

pA

-

5

30

-

5

50

pA

50 k

320 k

320 k

-

VN

110

94

110

90

70

90

-

dB

80

-

50 k

94

0

V

320

IlVN

V± = ±7.5 V
Input Offset Current
V± = ±7.5 V
Input Current

I,

V± = ±7.5 V
Large-Signal Voltage Gain

AOL

Vo=10Vp - p,RL=2kQ
Common-Mode Rejection Ratio

CMRR

Common-Mode Input-Voltage Range

V'CR

-0.5
10

to

dB

-0.5
0

10

12
Power-Supply Rejection Ratio

UNITS

CAS130

to
12

PSRR

-

6.V,oI6.V±

32

150

-

32

V± = ±7.5 V
Maximum Output Voltage
VOM+

12

13.3

-

12

13.3

-

VOM-

-

0.002

0.01

-

0.002

0.Q1

VOM+

14.99

15

-

14.99

15

VOM-

-

-

0

0.Q1

-

0

0.Q1

10M+ (Source) @ Vo = 0 V

12

22

45

12

22

45

10M- (Sink) @Vo = 15 V

12

20

45

12

20

45

-

10

15

15

3

2

3

-

10

-

-

10

2

10

-

At RL = 2 k
At RL = 00

V

Maximum Output Current

Supply Current

mA

1+

Vo = 7.5 V, RL = 00
Vo=OV, RL=co
Input Offset Voltage Temp. Drift
6.V,oI6.T

3-198

mA
IlV/oC

CA5130A, CA5130
TYPICAL VALUES INTENDED ONLY FOR DESIGN GUIDANCE
TEST CONDITIONS
V+ = +7.5 V
V- = -7.5 V
TA = 25°C
(Unless otherwise specified)

CHARACTERISTIC

Input Offset Voltage

UNITS

CA5130A

CA5130

±22

±22

mV

10 kO across

Adjustment Range

Terms. 4 and 5 or 4 and 1

I nput Resistance

R,

Input Capacitance

C,

Equivalent Input Noise
Voltage

TYPICAL VALUES

f = 1 MHz

1.5

1.5

TO

4.3

4.3

pF

23

23

/iV

BW=0.2 MHz

en

Rs = 1 MO"
Cc =0

15

15

fT

Cc = 47 pF

4

4

Cc= 0

30

30

Cc = 56 pF

10

10

0.09

0.09

/is

10

10

%

1.2

1.2

/is

Unity Gain Crossover

MHz
Frequency
Slew Rate, SR:
Open Loop

~~
D..

a:

w:;;

V//iS
Closed Loop
Transient Response:
Cc = 56 pF
Rise Time

t,
CL = 25 pF

Overshoot
RL = 2 kO
Settling Time (4 Vp-p Input to
(Voltage Follower)
<0.1%)

" Although a l-MO source is used for this test, the equivalent input noise remains constant for values of Rs up to 10 MO.

3-199

--'
«en

:z a:
O!!!

:5«

CA5130A, CA5130
CIRCUIT DESCRIPTION
Fig. 3 is a block diagram of the CA5i30 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5 V below the negative supply rail. and the output
can be swung very close to either supply rail in many
applicaUons. Consequently. the CA5130 Series circuits are
ideal for single-supply operation. Three Class A amplifier
stages. having the individual gain capability and current
consumption shown in Fig. 3. provide the total gain of the
CA5130. A biasing circuit provides two potentials for
common use in the first and second stages. Term. 8 can be
used both for phase compensation and to strobe the output
stage into quiescence. When Term. 8 Is tied to the negative
supply rail (Term. 4) by mechanical or electrical means. the
output potential at Term. 6 essentially rises to the positive
supply-rail potential atTerm. 7. This condition of essentially
zero current drain in the output stage under the strobed
"OFF" condition can only be achieved when the ohmic load
resistance presented to the amplifier is very high (e.g .• when
the amplifier output is used to drive CMOS digital circuits in
comparator applications).
Input Stages
The circuit of the CA5130 is shown in Fig. 2. It consists of a
differential-input stage using PMOS field-effect transistors.
(06, 07) working into a mirror-pair of bipolar transistors
(09. 010) functioning as load resistors together with
resistors R3 through R6. The mirror-pair transistors also
function as a differential-to-single-ended converter to
provide base drive to the second-stage bipolar transistor
.(011). Offset nulling, when desired. can be effected by
connecting a 100.00o-ohm potentiometer across Terms. 1
and 5 and the potentiometer slider arm to Term. 4. Cascodeconnected PMOS transistors 02. 04 are the constantcurrent source for the input stage. The biasing circuit for
the constant-current source is subsequently described.
The small diodes 05 through 08 provide gate-oxide
protection against high-voltage transients. e.g .• including
static electricity during handling for 06 and 07.
Second-Stage
Most of the voltage gain in the CA5130 is provided by the
second amplifier stage. consisting of bipolar transistor011
and its cascode-connected load resistance provided by
PMOS transistors 03 and 05. The source of bias potentials

~3i~-------------------' ~
200p.A

om.· II

BmA*

I
I
I
I

for these PMOS transistors is subsequently described.
Miller-Effect compensation (roll-off) is accomplished by
simply connecting a small capacitor between Terms. 1 and
8. A 47-picofarad capacitor provides sufficient
compensation for stable unity-gain operation in most
applications.
Bias-Source Circuit
At total supply voltages. somewhat above 8.3 volts. resistor
R2 and zener diode Z1 serve to establish a voltage of 8,3
volts across the series-connected circuit, consisting of
resistorR1. diodes 01 through 04. and PMOS transistor 01.
A tap at the junction of resistor R1 and diode 04 provides a
gate-bias potential of about 4.5 volts for PMOS transistors
04 and 05 with respect to Term. 7. A potential of about 2.2
volts is developed across diode-connected PMOS transistor
01 with respect to Term. 7 to provide gate bias for PMOS
transistors 02 and 03. It should be noted that 01 is "mirrorconnected" to both 02 and 03. Since transistors 01, 02,
03 are designed to be identical. the approximately 200microampere current in 01 establishes a similar current in
02 and 03 as constant-current sources for both the first
and second amplifier stages. respectively.
At total supply voltages somewhat less than 8.3 volts. zener·
diode Z1 becomes non-conductive and the potential,
developed across series-connected R1. 01-04. and 01.
varies directely with variations in supply voltage.
Consequently. the gate bias for 04.05 and 02, 03 varies in
accordance with supply-voltage variations. This variation
results in deterioration of the power-supply-rejection ratio
(PSRR) at total supply voltages below 8.3 volts, Operation
at total supply voltages below about 4.5 volts results in
seriously degraded performance.
Output Stage
The output stage consists of a drain-loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance load. the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier. its
gain is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail ,are shown in Fig. 6. Typical op-amp
loads are readily driven by the output stage. Because largesignal excursions are non-linear. requiring feed-back for
good waveform reproduction. transient delays may be
.encountered. As a voltage follower. the amplifier can
a'ChieveO.01 percent accuracy levels. including the negative
supply rail.

i

OllTPUT
6

120
m

i

roo

z

00

w

~

eo

~

40

;

100

ii

TOTAL SUPPLY VOLTAGE (FOR INDICATED YOLTAGE GAINS) -I' V
·WITH INPUT TERMINALS BIASED SO THAT TERM 6 POTENTIAL
IS +7~V ABOVE TERM 4

~

·WITH OUTPUT TERMINAL DRIVEN TO EITHER SUPPLY RAIL

Fig. S - Block diagram of the CA51S0 series.

-200_

~
-300\)1

~

OFFSET
NULL

i~
.L

20

f

~

~

Fig. 4 - Open-loop voltage gain and phase shift vs. frequency for
various values of Cc. C", and R...

3-200

CA5130A, CA5130

v·.

W·,. ,..

17. SUPPLY VOLTAGE.
15, Y-. OV ~
..... BIENT TEMPERATURE ITA}. 2!5'"t :

>

"

I

";0

: '2.5

~ I.
~ 75
~

I

~

::::Ii:::
,t ..

~"'#Q

IfI:
j(,.

g

25
25

5

AMBIENT TEMPERATURE ITAI - Oc

75

10

125

lili

Ilfl

17.5

20

225

a e)-v

GATE VOLTAGE (Y'GJ [TERMS 4

Fig. 5 - Open-loop gain vs. temperature.

'''' , ' "

jlj I!;;

'!>(J

'00 4

i

I;::

".

•

~

i

~.
'}~~i

~
'!J2

~

2

1111

Fig. 6 - Voltage transfer characteristics of CMOS output stage.

....J



"en 150

~

2

5a

75

o

0.5

1.5

2

2.5

3

3.5

o

4.5

1

10

OUTPUT VOLTAGE (V)

9

~

.

B

5
4

...>
."...

"a

v+=5Y'

v+-5V

V-=GND

V-eGND

~

6

'~"
a

Fig. 10 - Output voltage swing vs. load resistance.

7

Ul

11

LOAD RESISTANCE (kll)

Fig. 9 - Supply current vs. output voltage.

'Z"
§

GND

.. 4

~ 225

~

5V

V-

~ 6
25"C

a:

§

v+

~

125 DC

1
I-

tv+,-v

Fig. 8 - Quiescent supply current vs. supply voltage at several
temperatures.

6

;::5
Z

.

a:

~ 4

u

V

3

/

2

~

3

a"

2

SINK
SOURCE

1

0:"0.1 0.2

0.61

2

4 68

20 40 80

200

o_

600

LOAD RESISTANCE (KJl)

_

_

W

~

~

~

100

1W

TEMPERATURE (DC)

Fig. 11 - Output swing vs. load resistance.

Fig. 12- Output current VS. temperature.

3-201

1~

CA5130A, CA5130
Input Current Variation with Common-Mode Input Voltage

Input-Current Variation with Temperature

As shown in the Table of Electrical Characteristics, the
input current for the CAS130 Series Op-Amps is typically S
pA at T A = 2S· C when terminals 2 and 3 are at a commonmode potential of +7.S volts with respect to negative supply
Terminal 4. Fig. 1S contains data showing the variation of
input current as a function of common-mode input voltage
at TA = 2S·C. These data show that circuit designers can
advantageously exploit these characteristics to design
circuits which typically require an input current of less than
1 pA, provided the common-mode input voltage does not
exceed 2 volts. As previously noted, the input current is
essentially the result of the leakage current through the
gate-protection diodes in the input circuit and, therefore, a
function ofthe applied voltage. Although the finite resistance
of the glass terminal-to-case insulator of the TO-S package
also contributes an increment of leakage current, there are
useful compensating factors. Because the gate-protection
network functions as if it is connected to Terminal 4
potential, and the TO-S case of the CAS130 is also internally
tied to Terminal 4, input terminal 3 is essentially "guarded"
from spurious leakage currents.

The input current of the CAS130 Series circuits is typically S
pA at2S· C. The major portion ofthis input current is due to
leakage current through the gate-protective diodes in the
input circuit. As with any semiconductor-junction device,
including op amps with a junction-FET input stage, the
leakage current approximately doubles for every 10·C
increase in temperature. Fig. 16 provides data on the typical
variation of input bias current as a function of temperature
in the CAS130.

Offset Nulling
Offset-voltage nulling is usually accomplished with a
1OO,OOO-ohm potentiometer connected across Terms. 1 and
S and with the potentiometer slider arm connected to Term.
4. A fine offset-null adjustment usually can be effected with
the slider arm positioned in the mid-point of the
potentiometer's total range.

0.001

I

. . .1

0.01

I:

....

0.1

1:

. . . 11

1:

.. II 8

10

I:

In applications requiring the lowest practical input current
and incremental increases in current because of "warm-up"
effects, it is suggested that an appropriate heat sink be used
with the CAS130. In addition, when "sinking" or "sourcing"
significant output current the chip temperature increases,
causing an increase in the input current. In such cases,
heat-Sinking can also very markedly reduce and stabilize
input current variations.
Input-Offset-Voltage(V,o) Variation with DC Bias vs. Device
Operating Llle
It is well known that the characteristics of a MOS/FET
device can change slightly when a dc gate-source bias
potential is applied to the device for extended time periods.
The magnitude of the change is increased at high
temperatures. Users of the CAS130 should be alert to the
possible impacts of this effect If the application of the
device involves extended operation at high temperatures
with a significant differential dc bias voltage applied across

.. I '

0001

100

I:

....

0,01

2

....
0.1

MAGNITUDE OF

MAGNITUDE OF LOAD CURRENT IIL}- mA

Fig. 13 - Voltage across PMOS output transistor (08) vs. load
current.

1:""
l.(W)

,

1:"'1
10

I:

....

100

CURRENT (IL1- mA

Fig. 14 - Voltage across NMOS output transistor (012) vs. load
current.
4000

V+~75V

2 V-=-75Y

L

'000,,

r

;
~

~
~

IL

,

10°8

I

~ ,
'0,

-80 -60

INPUT CURRENT tIT 1- pA

Fig. 15 - CA5130 input current vs. common-mode voltage.

II

-40 -20 0
20 40 60 80
AMBIENT TEMPERATURE ITAI--C

100

120

140

Fig. 16 -Input current vs. ambient temperature.

3-202

CA5130A, CA5130
Single-supply operation: Initially, let it be assumed that
the value of RL is very high (or disconnected), and that the
input-terminal bias (Terms. 2 and 3) is such that the output
terminal (No.6) voltage is at V+/2, i.e., the voltage-drops
across 08 and 012 are of equal magnitude. Fig. 7 shows
typical quiescent supply-current vs. supply-voltage for the
CA5130 operated under these conditions. Since the output
stage is operating as a Class A amplifier, the supply-current
will remain constant under dynamic operating conditions
as long as the transistors are operated in the linear portion
of theirvoltage-transfer characteristics (see Fig. 6). If either
08 or 012 are swung out of their linear regions toward
cut-off (a non-linear region), there will be a corresponding
reduction in supply-current. In the extreme case, e.g., with
Term. 8 swung down to ground potential (or tied to ground),
NMOS transistor 012 is completely cut off and the supplycurrent to series-connected transistors 08, 012 goes
essentially to zero. The two preceeding stages in the
CA5130, however, continue to draw modest supply-current
(see the lower curve in Fig. 7) even though the output stage
is strobed off. Fig. 14a shows a dual-supply arrangement for
the output stage that can also be strobed off, assuming RL =
.. , by pulling the potential of Term. 8 down to that of Term.
4.
Let it now be assumed that a load-resistance of nominal
value (e.g., 2 kilohms) is connected between Term. 6 and
ground in the circuit of Fig. 18b. Let it further be assumed
again that the input-terminal bias (Terms. 2 and 3) is such
that the output terminal (No.6) voltage is a V+/2. Since
PMOS transistor 08 must now supply quiescent current to

Terms. 2 and 3. Fig. 17 shows typical data pertinentto shifts
in offset voltage encountered with CA5130 devices (TO-5
package) during life testing. At lower temperatures (TO-5
and plastic), for example at 85° C, this change in voltage is
considerably less. In typical linear applications where the
differential voltage is small and symmetrical, these
incremental changes are of about the same magnitude as
those encountered in an operational amplifier employing a
bipolar transistor input stage. The two-volt dc differential
voltage example represents conditions when the amplifier
output stage is "toggled", e.g .. as in comparator applications.
Power-Supply Considerations

Because the CA5130 is very useful in single-supply
applications, it is pertinent to review some considerations
relating to power-supply current consumption under both
single- and dual-supply service. Figs. 18a and 18b show the
CA5130 connected for both dual- and single-supply
operation.
Dual-supply operation: When the output voltage at Term.
6 is zero-volts, the currents supplied by the two power
supplies are equal. When the gate terminals of 08 and 012
are driven increasingly positive with respect to ground,
current flow through 012 (from the negative supply) to the
load is increased and current flow through 08 (from the
positive supply) decreases correspondingly. When the gate
terminals of 08 and 012 are driven increasingly negative
with respectto ground, currentflowthrough 08 is increased
and current flow through 012 is decreased accordingly.

>

f •

~~
.....

~"\~~~

~ "UllUnllJ:~~.~~~o
~
~"\~+~~

f!:5
;0'
-

ft.",ff. "J ~ ","'ft1++++

~~~~t:tltltt

DIFFERENTIAL DC VOLTAGE

~~;~::u;E:oML~A~Ea.e~~ vJ.1-R+l+I-I+I++-I-1-I+I
500

1000

1500

2000

2500

3000

3!500 4000

TIME (1I- HOURS

Fig. 17 - Typical Incremental offset-voltage shift vs. operating life.

-1*
"T" POSITIVE
1

SUPPLY

+

iNEGATIVE
.L
SUPPLY

~
10 I DUAL POWER-SUPPLY OPERATION

tbl SINGLE POWER-SUPPLY OPERATION

Fig. 18 - CA5130 output stage in dual and single power-supply operation.

3-203

-'
oiII-SL-O-PE-----'

/V

SYMMETRY
ADJUST

-75V

IOkQ

VOLTAGE
CONTROLLED
INPUT

i

RI

10kn

FREQ.
ADJUST

-75 V

(100 kHz MAX.l

·SEE FILE NO. 475 AND lCAN-6668
FOR TECHNICAL INFORMATION

Fig. 28 - Function generator (frequency can be varied 1,000,00011
with a single control).

Operation with Output-Stage Power-Booster
The current-sourcing and -sinking capability olthe CA5130
output stage is easily supplemented to provide powerboost capability. In the circuit of Fig. 29, three CMOS
transistor-pairs in a single CA3600E' IC array are shown
parallel connected with the output stage in the CA5130. In
the Class A mode of CA3600E shown, a typical device
'See File No. 619 for technical information.

consumes 20 mA of supply current at 15-V operation. This
arrangement boosts the current-handling capability of the
CA5130 output stage by about 2.5X.
The amplifier circuit in Fig. 29 employs feedback toestab/ish
a closed-loop gain of 48 dB. The typical large-signal
bandwidth (-3 dB) is 50 kHz.

+15 V

IMn

750

kn

5001
RL"loon
(PO" 150 mW
AT THO"

=-

AV(CLI • 48 d8
LARGE SIGNAL
BWI-3 dBI ' 50 kHz

NOTE:

510

kn

TRANSISTORS pi, p2, p3 AND 01,02,03 ARE
PARALLEL - CONNECTED WITH Q8 AND QI2,
RESPECTIVELY, OF THE CA5130

·SEE FILE NO. 619

Fig. 29 - CMOS transistor array (CA3600E) connected as powerbooster in the output stage of the CA5130.

3-210

10 ...1

CA5160A
CA5160

mHARRIS

BiMOS Microprocessor Operational Amplifiers
With MOSFET Input/CMOS Output

August 1991

Features

Description

o MOsFET Input Stage

CAS160A and CAS160 are integrated circuit operational
amplifiers that combine the advantage of both CMOS and
bipolar transistors on a monolithic chip. The CA5160 series
circuits are frequency compensated versions of the popular
CA5130 series. They are designed and guaranteed to operate in microprocessor or logic systems that use +5V
supplies.

.. Very High ZI •••••.••••••• 1.STO (l.S x 10 120) Typ.
.. Very Low II ............ . SpA Typ. at lSV Operation
2pA Typ. at SV Operation
o Common-Mode
Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can Be Swung
O.SV Below Negative Supply Rail
o CMOS Output Stage Permits Signal Swing to Either
(or Both) Supply Rails
o CAS160A, CAS160 Have Full Military Temperature
Range Guaranteed Specifications for V+ SV
o CAS160A, CAS160 Are Guaranteed to Operate Down
to 4.SV for AOL
o CAS160A, CAS160 Are Guaranteed Up To +7.S

=

Applications
o Ground Referenced Single Supply Amplifiers
o Fast Sample-Hold Amplifiers
o Long Duration TimerslMonostables
o Ideal Interface With Digital CMOS
o High Input Impedance Wideband Amplifiers
o
o

Voltage Followers (e.g. Follower for Single Supply
D/A Converter)
Wien-Bridge Oscillators

• Voltage Controlled Oscillators
o Photo Diode Sensor Amplifiers
o SV Logic Systems
• Microprocessor Interface

Gate-protected p-channel MOSFET (PMOS) transistors
are used in the input circuit to provide very high input
impedance, very low input current, and exceptional speed
performance. The use of PMOS field effect transistors in the
input stage results in common-mode input voltage capability down to O.5V below the negative supply terminal, an
important attribute in single supply applications.
A complementary symmetry MOS (CMOS) transistor pair,
capable of swinging the output voltage to within 10mV of
either supply voltage terminal (at very high values of load
impedance), Is employed as the output circuit
The CA5160 Series circuits operate at supply voltages
ranging from 5V to 16V, or ±2.5V to ±8V when using split
supplies, and have terminals for adjustment of offset voltage
for applications requiring offset-null capability. Terminal
provisions are also made to permit strobing of the output
stage.
The CA5160 Series is supplied in standard 8-lead TO-5
style packages (T suffix), a-lead dual-in-line formed lead
TO-5 style "OIL-CAN" packages (S suffix), and a-lead
dual-in-Iine plastic package (Mini-DIP E suffix). The
CA5160 is available in chip form (H suffix). They have guaranteed specifications for 5V operation over the full military
temperature range of -550 C to +125 0 C.

Pinouts
SAND T SUFFIXES
TOP VIEW
SUPPLEMENTARY
COMPENSATION
~TAB
\
OFFSET
NULL

ESUFFIX
TOP VIEW
OFFSET
NULL 1
STROBE

INV.
INPUT 2
NON -INV.
INPUT

8/

STROBE

OUTPUT
5 OFFSET
NULL

4
V - AND CASE

CA5160 Sories devices have an on-chip frequency-compensation network.
Supplementary phase-compensation or frequency roll-off (if desired) can be
connected externally between terminals 1 and 8.

FIGURE 1.

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

Copyright

© Harris Corporalion 1991

3-211

File Number

1924.1

<[ en
z a:

--'

OW

~§

a: c..
w::;;;

(5<[

CA5160A, CA5160

MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE
(Between V+ and V- Terminals) ........................... 16 V
DIFFERENTIAL-MODE
INPUT VOLTAGE ..•....••........•.......••...•.•..•.•. ±8 V
COMMON-MODE DC
INPUT VOLTAGE ...................... (V+ +8 V) to (V- -0.5 V)
INPUT-TERMINAL CURRENT ......•.•....•....•..•..... 1 rnA
DEVICE DISSIPATION;
WITHOUT HEAT SINKUPT055°C ...................•..•....•..•......•. 630mW
ABOVE 55°C ...•...............•. Derate linearly 6.67 mW/oC
WITH HEAT SINKUP TO 90°C .......•...........•.......••...•......... 1 W
ABOVE 90°C ..................... Derate linearly 16.7 mW/oC

r------,

I

'Short circuit may be applied to ground or to either supply.

r---------..,
as

I I CURRENT

BIAS CIRCUIT

TEMPERATURE RANGE;
OPERATING (All Types) ...................... -55 to +125°C
STORAGE (All Types) ......................... -65 to +150°C
OUTPUT SHORT-CIRCUIT
DURATION" ............•.........•............ INDEFINITE
LEAD TEMPERATURE
(DURING SOLDERING);
AT DISTANCE 1/16 ± 1/32 INCH
(1.59 ± 0.79 MM) FROM CASE
FOR 10 SECONDS MAX ............................. +265°C

SOURCE FOR

AND 07

I

I
I

I
I
I

I
I

I
I
I

ZI

05

.3V

RI
4Qkn

R2

L___ -=~
SECOND
STAGE

,-----I OUTPUT
I STAGE

I

I

NOTE.

DIODES 05 THROUGH 08 PROVIDE GATE-OXIDE PROTECTION
FOR MOS/FET INPUT STAGE

Fig. 2 - Schematic diagram of the CA5160 Series.

3-212

9~O"'285!>G

CA5160A, CA5160

ELECTRICAL CHARACTERISTICS al T A = 25° C, V+ = 5 V, V- = 0 V
LIMITS
CA5160A

CHARACTERISTIC
Min.
Input Offset Voltage

V'O

CA5160

Typ.

Max.

-

1.5

4

-

0.1

-

Min.

UNITS

Typ.

Max.

-

2

10

5

-

0.1

10

2

10

-

2

15

-

70

80

-

60

69

-

2.5

mV

Va = 2.5 V
Input Offset Current

1,0

Va = 2.5 V
pA
I,

Input Current
Va = 2.5 V
Common-Mode Rejection Ratio
VCM = 0 to 1 V

CMRR

75

87

VCM = Oto 2.5 V
C MRR
Input Common-Mode Voltage Range
+
V'CR
V'CR-

60

69

2.5

2.8
-0.5

0

-

2.8
-0.5

-

60

75

-

55

67

-

100
90

117
102

-

95
85

117
102

-

-

1.0

3.1

4.0

1.0

2.2

4.0

Power-Supply Rejection Ratio

PORR

6. V+ = 1 V; 6. V- = 1 V
Large-Signal Voltage Gain'
Vo=0.1 to 4.1 V
Va = 0.1 to 3.6 V

AOL
RL = 00
RL = 10k

dB

V

0

dB

ISOURCE

rnA
Sink Current
Vo = 5 V
Output Voltage
RL =

00

RL = 2k

VOUT
YOM+
YOM+
YOM
YOMYOM

+

VO M-

Va = 2.5 V

1.6

4.0

1.0

3.4

4.99

5
0

-

4.99

5

-

0.Q1

-

0

0.01

4.7

-

4.4

4.7

-

0

0.Q1

-

0

0.01

3.3

-

2.5

3.3

-

0

0.01

-,-

0

0.Q1

4.0

ISINK

RL = 10k

Supply Current
Vo=OV

1.0

4.4

2.5

-

V

ISUPPLY

ISUPPLY

-

50

100

-

50

100

-

320

400

-

320

400

'For V+ = 4.5 V and V- = GND; VOUT = 0.5 V to 3.2 V at RL = 10k

3-213



I

I

a:: a..

I
I

:5«

~~

w:;;

OFFSET
NULL
TOTAL SUPPLY VOLTAGE (FOR INDICATED VOLTAGE GAINS) -15

"'WITH INPUT TERMINALS BIASED
JS+75VABQVE TERM 4

so

v

THAT TERM 6 POTENTIAL

92C5-28573

·WITH OUTPUT TERMINAL DRIVEN TO EITHER SUPPLY RAIL

Fig. 3 - Block diagram of the CA5160 Series.

00 LOAD RESISTANCE (RI.. J" Z kQ .

!I

~ 140
I

I

:l

"'

~

~

<..\~·..tO.o.('

'"~

I 6
10'
I'
FREQUENCY (O-Hz

~

~

I
~

~

107

110

~ 100

is

~ 90

80
-100

I

-50

0

100

50

AMBIENT TEMPERATURE ITA) -

Oc

92CS-28538

Fig. 5 - Open-loop gain vs. temperature.

Fig. 4 - Open-loop voltage gain and phase shift
vs. frequency.

3-217

...J
«en
za::

OW

~

~~r.
r.p ~.1

40

7

0

\S'~"I:~C!

~

v+

200IJ-A

I

,~ Q

is}

0

I

IOO~

~~'" ..C/.)o

>

r---------------------I
I

.50~

'" I«~.,.,".

60

voltages below about 4.5 volts results in seriously degraded
performance.
Output Stage - The output stage consists of a drain-loaded
inverting amplifier using CMOS transistors operating in the
Class A mode. When operating into very high resistance
loads, the output can be swung within millivolts of either
supply rail. Because the output stage is a drain-loaded
amplifier, its gain is dependent upon the load impedance.
The transfer characteristics of the output stage for a load
returned to the negative supply rail are shown in Fig. 6. Typical op-amp loads are readily driven by the output stage.
Because large-signal excursions are non-linear, requiring
feedback for good waveform reproduction, transient delays
may be encountered. As a voltage follower, the amplifier can
achieve 0.01 per cent accuracy levels, including the negative
supply rail.

CA5160A, CA5160

2~

S

7S

10

125

15

175

20

225

GATEVOLTAGEIVGI {n::RMS 46 B}-V

Fig. 6 - Voltage transfer characteristics of CMOS
output stage.

Fig. 7 - Quiescent supply current vs. supply voltage.

10
12
14
TOTAL SUPPLY VOLTAGE IV+)-V

OUTPUT VOLTAGE IVI

Fig. 8 - Quiescent supply current vs. supply voltage

Fig. 9 - Supply current vs. output voltage.

at several temperatures.
v+=5V

~

0
~

t---HHtHtlt-iH-ttttffi--t-ttttttlt-v- =GND
7

" •
~w •
"<~

4

>

3

0

~

V

2

0

0.1 0.2

0.61

2

LOAD RESISTANCE (kg)

4 68

20 40 80

200

800

LOAD RESISTANCE IKJlI

Fig. 10 - Output voltage swing vs. load resistance.

Fig. 11 - Output swing vs. load resistance.

2411

140

0.001

TEMPERATURE (0e)

Fig. 12 - Output current vs. temperature.

Fig. 13 -

3-218

2

001

....

2

....

24&1

0.1
I
10
MAGNITUDE OF LOAD CURRENT tILJ- mA

2461

100

Voltage across PMOS output transistor (Q8) vs.
load current.

CA5160A, CA5160

10008 AMBIENT TEMPERATURE ITA)· Z:!I"e

,
0001

"6"

Z

001

468

2468

01

2461

L

10

2468

2 .. (, 810 2:

100

46B

2:

10'

Fig. 15 - Equivalent noise voltage vs. frequency.

Voltage across NMOS output transistor (012) vs.
load current.

Offset Nulling
Offset-voltage nulling is usually accomplished with a 100,000ohm potentiometer connected across Terminals 1 and Sand
with the potentiometer slider arm connected to Terminal 4. A
fine offset-null adjustment usually can be affected with the
slider arm positioned in the mid-point of the potentiometer's
total range.

.. 68 11P 2

FREQUENCY IfJ-Hz

MAGNITODE OF LOAD CURRENT (Il.I-mA

Fig. 14 -

.. 68. 02 2:

.

pA at 2SoC. The major portion of this input current is due to
leakage current through the gate-protective diodes in the
input circuit. As with any semiconductor-junction device,
including op amps with a junction-FET input stage, the leakage current approximately doubles for every 10° C increase
in temperature. Fig. 17 provides data on the typical variation
of input bias current as a function of temperature in the
CAS160.

Input Current Variation with CommonMode Input Voltage
As shown in the Table of Electrical Characteristics, the input
current for the CAS160 Series Op-Amps is typically S pA at
TA = 2SoC when Terminals 2 and 3 are at a common-mode
potential of +7.S volts with respect to negative supply Terminal 4. Fig. 16 contains data showing the variation of input

j

-80

-60 -40 -20
0
2.0 40 60 80 100 1ZO
AMBIENT TEMPERATURE ITAI-·~2CS_ZI2'H

140

Fig. 17 -Input current vs. ambienttemperature.

INPUT CURRENT U:T 1- pA

current as a function of common-mode input voltage at TA =
2SoC. These data show that circuit designers can advantageously exploit these characteristics to design circuits which
typically require an input current of less than 1 pA, provided
the common-mode input voltage does not exceed 2 volts. As
previously noted, the input current is essentially the result of
the leakage current through the gate-protection diodes in
the input curcuit and, therefore, a function of the applied
voltage. Although the finite resistance of the glass terminalto-case insulator of the TO-S package also contributes an
increment of leakage current, there are useful compensating
factors. Because the gate-protection network functions as if
it is connected to Terminal 4 potential, and the TO-S case of
the CAS160 is also internally tied to Terminal 4, input terminal 3 is essentially "guarded" from spurious leakage currents.
Input-Current Variation with Temperature
The input current of the CAS160 Series circuits is typically S

~it

~~

o

f-t--I-t--I

Fig. 16 - CAS160 input current vs. common-mode voltage.

--'
tv.>;;-o

92CM-2B586RI

Fig. 27(a) -

CA5160 1,000,00011 single-control function
generator - 1 MHz to 1 Hz.

3-224

CA5160A, CA5160

Function Generator
A function generator having a wide tuning range is shown in
Fig. 27. The adjustment range. in excess of 1.000.000/1. is
accomplished by a single potentiometer. Three operational
amplifiers are utilized: a CA5160 as a voltage follower. a
CA3080 as a high-speed comparator. and a second CA3080A

as a programmable current source. Three variable capacitors
C1. C2. and C3 shape the triangular signal between 500 kHz
and 1 MHz. Capacitors C4. C5 and the trimmer potentiometer in series with C5 maintain essentially constant (±10%)
amplitude up to 1 MHz.

92CS·28588

Fig. 27(b) -

Fig. 27(c) - Triple-trace of the function generator
sweeping to 1 MHz. The bottom trace
is the sweeping signal and the top trace
is the actual generator output. The
center trace displays the 1 MHz signal
via delayed oscilloscope triggering of
the upper swept output signal.

Two-tone output signal from the function
generator. A square-wave signal modulates
the external sweeping input to produce
1 Hz and 1 MHz. showing the 1.000.000/1
frequency range of the function generator.

Staircase Generator
Fig. 28 shows a staircase generator circuit utilizing three
CMOS operational amplifiers. Two CA5130's are used; one

as a multivibrator. the other as a hysteresis switch. The third
amplifier. a CA5160. is used as a linear staircase generator.
S.IKa

IN914

+ ISV
100

Kn

100
ICJl

MUl.TIVIBRATOR

MULTIVIBRATOR RETRACE INHIBIT
51 KD
+15mVTO+IOV
IOOKQ

Fig. 28(a) - Staircase generator circuit
utilizing three CMOS operational amplifiers.
Picoammeter Circuit
Fig. 29 is a current-to-voltage converter configuration utilizing a CA5160 and CA3140 to provide a picoampere meter for
±3 pA full-scale meter deflection. By placing Terminals 2 and
4 of the CA5160 at ground potential. the CA5160 input is
operated in the "guarded mode". Under this operating condition. even slight leakage reistance present between Terminals 3 and 2 or between Terminals 3 and 4 would result in
zero voltage across this leakage resistance. thus substantially reducing the leakage current.

If the CA5160 is operated with the same voltage on input
Terminals 3 and 2 as on Terminal 4. a further reduction in
the input current to the less than one picoampere level can
be achieved as shown in Fig. 16.
To further enhance the stability of this circuit. the CA5160
can be operated with its output (Terminal 6) near ground.
thus markedly reducing the dissipation by reducing the
supply current to the device.
The CA3140 stage serves as a X100 gain stage to provide the
required plus and minus output swing for the meter and

3-225

....I
«en

:z a:

aU!

~§
Q.

a:

U!:;;
~«

CA5160A, CA5160

feedback network. A 100-to-1 voltage divider network consisting of a 9.9-KO resistor in series with a 100-ohm resistor
sets the voltage at the 1Q-KMO resistor (in series with Terminal 3) to ±30 mV full-scale deflection. This 3Q-mV signal
results from ±3 volts appearing at the top of the voltage
divider network which also drives the meter circuitry.

By utilizing a switching technique in the meter circuit and in
the 9.9 KO and 100-ohm network similar to that used in
voltmeter circuit shown in Fig. 26, a current range of 3 pA to
1 nA full scale can be handled with the single 10-KMO
resistor.

STAIRCASE OUTPUT

2 VOLT STEPS

COMPARATOR

OSCILLATOR

92C5-28596

Fig. 28 (b) - Staircase Generator Waveform
Top Trace: Staircase Output
2 Volt Steps
Center Trace: Comparator
Bottom Trace: Oscillator

loon

Fig. 29 - Current-Io-voltage converter to provide a
picoammeter with ± 3 pA full-scale deflection.

Single-Supply Sample-and-Hold System
Fig. 30 shows a single-supply sample-and-hold system using
a CA5160 to provide a high input impedance and an inputvoltage range of 0 to 10 volts. The output from the input
buffer integrator network is coupled to a CA3080A. The
CA3080A functions as a strobeable current source for the
CA3140 output integrator and storage capacitor. The CA3140
was chosen because of its low output impedance and constant gain-bandwidth product. Pulse "droop" during the hold

interval can be reduced to zero by adjusting the 100-KO
bias-voltage potentiometer on the positive input of the
CA3140. This zero adjustment sets the CA3080A output voltage at its zero current position. In this sample-and-hold circuit it is essential that the amplifier bias current be reduced
to zero to minimize output signal current during the hold
mode. Even with 320 mV at the amplifier bias circuit terminal
(5) at least ± 100 pA of output current will be available.

3-226

CA5160A, CA5160

"'I~V

1M..

STROBE INPUT

SA"':~CDI~~ -"""L...s-

an

92CM-28590

Fig. 30(a) - Single-supply sample-and-hold systeminput O-to-to volts.

<[

--' en
:z ex:
OW

~§

ex: a..

w:;;
g;<[

92CS-28595

(b) - Sample-and-hold waveform.
Top Trace: Sampled Output
Center Trace: Input Signal
Bottom Trace: Sampling Pulses

(c) - Sample-and-hold waveform.
Top Trace: Sampled Output
Center Trace: Input
Bottom Trace: Sampling Pulse

Wien Bridge Oscillator
A simple, single-supply Wien Bridge oscillator using a
CA5160 is shown in Fig. 31. A pair· of parallel-connected
1N914 diodes comprise the gain-setting network which
standardizes the output voltage at approximately 1.1 volts.

The 500-ohm potentiometer is adjusted so that the oscillator
will always start and the oscillation will be maintained.
Increasing the amplitude of the voltage may lower the threshold level for starting and for sustaining the oscillation, but
will introduce more distortion.

51 lUI

.,

100 KQ

••

100 KQ

I

1·22~.j~~.~lrrll~.'~I~C~'.~>~C~2

9ZCS-Z859IAI

Fig. 31 - CA5160 Single-supply Wien Bridge oscillator.

3-227

CA5160A, CA5160

Operation with Output-Stage Power-Booster
The current sourcing and sinking capability of the CA5160
output stage is easily supplemented to provide power-boost
capability. In the circuit of Fig. 32, three CMOS transistorpairs in a single CA3600 IC array are shown parallel-connected with the output stage in the CA5160. In the Class A mode
of CA3600E shown, a typical device consumes 20 mA of

supply current at 15-V operation. This arrangement boosts
the current-handling capability of the CA5160 output stage
by about 2.5X.
The amplifier circuit in Fig. 32 employs feedback to establish
a closed-loop gain of 20 dB. The typical large-signalbandwidth (-3 dB) is 190 kHz.

-+1& Y

IMn

500i

INHI--"ii\f\,-'-{
II'F

son
lOa mW

-=- AT IO%THD·
A~20

dB
LARGE SIGNAL
BW(-3dS·'90KHz

20 Kn
*SEE FILE NO. 619

NOTE:
TRANSISTORS pi. p2, p3AND n1, n2. n3
ARE PARALALEL- CONNECTED WITH as
AND 012, RESPECTIVELY, OF THE

92CM-28592

CAs16D

Fig. 32 - CMOS transistor array (CA3600E) connected as
power booster in the output stage of the CA5160.

3-228

CA5260A
CA5260

mJHARRIS

BiMOS Microprocessor Operational Amplifiers
With MOSFET Input/CMOS Output·

August 1991

Features

Description

• MOSFET Input Stage
.. Very High ZI .••••••••••.. 1.STO (l.Sx 1012 0) Typ.
.. Very Low II ••••••••••••• SpA Typ. at lSV Operation
2pA Typ. at SV Operation
• Ideal for Single-Supply Applications
• Common-Mode Input Voltage Range Includes
Negative Supply Rail; Input Terminals Can Be Swung
O.SV Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either
(or Both) Supply Rails
o CAS260A, CAS260 Have Full Military Temperature
Range Guaranteed SpeCifications V+ SV
o CAS260A, CAS260 Are Guaranteed to Operate Down
to 4.SV for AOL
o Fully guaranteed to operate at -SSoC to +12S o C at
V+ SV, V- Gnd

The CA5260A and CA5260 are integrated-circuit operational amplifiers that combine the advantage of both CMOS
and bipolar transistors on a monolithic chip. The CA5260
series circuits are dual versions of the popular CA5160
series. They are designed and guaranteed to operate in
microprocessor or logic systems that use +5V supplies.

=

=

=

Applications
Fast Sample-Hold Amplifiers

o Long Duration Timers/Monostables
o Ideal Interface With Digital CMOS
o High Input Impedance Wide band Amplifiers
o Voltage Followers (e.g. Follower for Single Supply

D/A Converter)
Regulators (Permits Control of Output
Voltage Down to Zero Volts)
• Wien-Bridge Oscillators
o Voltage Controlled Oscillators
o Photo Diode Sensor Amplifiers
o SV Logic Systems
o Microprocessor Interface
o Voltage

Pinouts

A complementary-symmetry MOS (CMOS) transistor-pair,
capable of swinging the output voltage to within 10mV of
either supply-voltage terminal (at very high values of load
Impedance), is employed as the output circuit
The CA5260 Series circuits operate at supply voltages
ranging from 4.5V to l6V, or ±2.25V to ±av when
using split supplies.

o Ground Referenced Single Supply Amplifiers
o

Gate-protected p-channel MOSFET (PMOS) transistors
are used in the input circuit to provide very-high-input
impedance, very-low-input current, and exceptional speed
performance. The use of PMOS field-effect transistors in
the input stage results in common-mode input-voltage
capability down to O.5V below the negative-supply terminal,
an important attribute in single-supply applications.

The CA5260 Series is supplied in standard a-lead TO-5
style packages IT suffix) and a-lead dual-in-line formed
lead TO-5 style "DIL-CAN" packages (S suffix). The
CA5260 is available in chip form (H suffix). Both devices are
also available in a-lead Mini-DIP (E suffix) and a-lead Small
Outline (M suffix) packages.
The CA5260A, CA5260 have guaranteed specifications for
5V operation over the full military-temperature range of
-55 0 C to +125 0 C.
.

SAND T SUFFIXES
TOP VIEW

E AND M SUFFIXES
TOP VIEW

INV.
INPUT (A)
OUTPUT (A)
INV.
INPUT (A)
NON -INV.
INPUT (A)

V-

OUTPUT (6)
INV.
INPUT (6)
NON -INV.
INPUT (6)

INV.
INPUT (6)
NOTE: Pin compatible wilh the industry standard 1458

FIGURE 1.
CAUTION: These devices are sensitive to electrostatic discharge. Proper
Copyright @ Harris Corporation 1991

I.e. handling
3-229

procedures should be followed.

File Number

1929_1

-'


Za:
OW
-;:;:

~~

w::;:
~ OB

1.5

1

VOUT
VoM+
VoMVOM+
VOMVOM+
VOM-

RL = 2k

-

-

ISINK

RL = 10k

Max.

V,O

V'CRPSRR

Power-Supply Rejection Ratio
b,+ = 1 V; b,- = 1 V
Large-Signal Voltage Gain
Vo = 0.5 to 4 V
Vo = 0.5 to 4 V
Vo = 0.7 to 3 V
Source Current
Vo=OV
Sink Current
Vo=5V
Output Voltage
RL = 00

UNITS

CA5420
Typ.

fJA

:5<

CA5420A, CA5420

ELECTRICAL CHARACTERISTICS-at TA = -SS'C to +12S'C, y+ = S Y, Y- = 0 Y
LIMITS
CA5420A
Min.
Typ.
Max.
Min.

CHARACTERISTIC
Input Offset Voltage
Vo= 2.5V
Input Offset Current
Vo = 2.5 V (Up to TA = 85' C)
I nput Current
Vo = 2.5 V (Up to T A = 85' C)
Common-Mode Rejection Ratio
VCM = 0 to 3.7 V; Vo = 2.5 V
Input Common-Mode Voltage Range
Vo = 2.5 V

Iv

~

mV

1.5
2
2
15

3
10
5
25

nA
pA
nA
pA

CMRR

70

80

--

65

75

--

dB

V,CR+

3.7

--

4
-0.3

--

3.7

V

I

4
-0.3

----

65

80

--

--

80
80
75

85
85
80

0

70

83

85
80
75

87
87
80

ISOURCE

1

2.7

--

1

2.7

--

ISINK

1

2.1

--

1

2.1

--

4.8

4.9
0.16
4.9
0.15
4
0.14

--0.2
--

4.8

4.9
0.16
4.9
0.15
4
0.14

430

550

480

600

ISUPPLY

SUPPLY VOLTAGE tV-)aOV
AMBIENT TEMPERATURE (TA I ""2!i°C

--

--

0

AOL
RL = 00
RL - 10k
RL =2k

VOUT
VOM+
YOM
VOM+
VOMVOM+
YOM
ISUPPLY

Supply Current
Vo=OV
Vo = 2.5 V

~

15

--

------

3

3
10
5
15

V'CRPSRR

RL = 2k

~

10

II,I
IIII

RL = 10k

UNITS

2

1,0
100

Power-Supply Rejection Ratio
A+ = 1 V; A- = 1 V
Large-Signal Voltage Gain
Vo = 0.5 to 4 V
Va = 0.7 to 4 V
VOUT = 0.7 to 2.5 V
Source Current
Vo=OV
Sink Current
Vo=5V
Output Voltage
RL = 00

Max.

1.5
2
2
10

V,O

---:--

CAS420
Typ.

--

4.7

-3

----

--

0.2

4.7

-3
----

0.2

dB

----

-rnA

-0.2

---

V

0.20
0.2

430

550

480

600

pA

I

'r-~~-+-H--~~-+-Hr-~~-+-H
- - '11+=+2'11

:.

=~= ~::!~O\

~~ 6~_~~F3_~.~:~~_.~__~+'-r-r--,vrt~·~+r20~V-H

~ .\O'Q.8r-~~-+-H---F-~~W--HI--~~-+-H
e:~
~g

:

21--~~~4-H1--~--~~~\~,\~~~-H

~

41--~--~-H1--~--~~1--~--~-H

o

'I--~--~-Hf--~--~~I--~--~-H

1000 8

0001

..

EI 80 I
.. 6 8 I
2
.. 68 tO
LOAD (SOURCING) CURRENT-mA
92CS-34402

oar

468

468

468

OJ

10

LOAD ISINKINGICURRENT-mA
92CS-!4403

Fig. 3 - Output voltage vs load sourcing current.

Fig. 4 - Output voltage vs load sinking current.

3-238

CA5420A, CA5420

ELECTRICAL CHARACTERISTICS FOR EQUIPMENT DESIGN
AI V+ =1 V, y- =-1 Y, TA =25°C Unle•• Otherwise Specified

CHARACTERISTIC
Input Offset Voltage
Input Offset Current
Input Current
Large-Signal Voltage Gain
AL 10 kO

V,O

11,01
1111
AOL

=

Common-Mode Aejection Ratio

CMRR

LIMITS
CAS420A
Typ.
Max.
Min.
Min.
2
5
0.01
4'
0.02
5'
20k
100k
10k
86
100
80
560
1000
65
55
60

-

Input Common-Mode Voltage Range
V,CR+
V,CR
PSRR

Power Supply Aejection Ratio
1!.v,O/l!.V
Maximum Output Voltage
RL oc

-

70
VOUT
Vo M+
Vo.[

=

Supply Current
Device Dissipation
Input Offset Voltage Temp. Drift

0.2
-1

'SUPPLY
Po
l!.V,oIl!.T

0.9
-0.85

-

0.5
-1.3
32
90
0.95
-0.91
350
0.7
4

320
-

650
1.1

-

-

-

0.2

-

60
0.9
-0.85

-

CAS420
Typ.
5
0.01
0.02
100k
100
560
65
0.5
-1.3
100
80
0.95
-0.91
350
0.7
4

UNITS
Max.
10
4'
5'

1800
-

mV
pA
pA
VN
dB

pVN
dB

-

V

1000

pVN

-

650
1.1

-

dB

V
pA
mW
pV/oC

'The maximum limit represents the levels obtainable on high-speed. automatic test equipment.
Typical values are obtained under laboratory conditions.
ELECTRICAL CHARACTERISTICS FOR EQUIPMENT DESIGN
At V+ = 10 V, Y- = -10 V, TA = 25°C Unless Otherwise Specified

CHARACTERISTIC
Input Offset Voltage
Input Offset Current
Input Current
Large-Signal Voltage Gain
AL 10 kO

V,O

11,01
1111
AOL

=

Common-Mode Rejection Ratio

CMRR

LIMITS
CA5420A
Typ.
Max.
Min.
Min.
2
5
0.03
4'
0.05
5'
10k
100k
20k
86
100
80
100
320
70
70
80

-

-

-

Input Common-Mode Voltage Range
V,CR+
V,CR
PSRR

Power Supply Rejection Aatio
l!.V,oIl!.V
Maximum Output Voltage
RL  5.75

.,

!III
~0

I
II

"-"

AMBIENT TEMPERATURE

(TA}~25·C

v..... sv
V-a GND
Rt TO GND

...>

~
~ 1.25
0

oV-

/

2

• 6.

OUTPUT Vot_TAl" I'VOL_TS'

2

•••10

2

• • '00

LOAD RESISTANCE ( tetl)

92C5-42286

2

•••1000

'2C5-42287

Fig. 6 - Output voltage swing vs load resistance.

Fig. 5 - Supply current VB output voltage.

800 AMBIENT TEMPERATURE (TAJ"2S-C
V... ·SV
700 V-a GND

~600

~500
!S.

100

o

10 2

to

25

3~

45

55

65

75

85

95

105

115

10 3
FREQUENCY -Hz

125

10"

(0 5
92CS-34404

TEMPERATURE (Oe)

Fig. 8 - Input noise voltage vs frequency.

Fig. 7 - Input bias current drift (i!J.I.r i!J. T).

~ 100

I

'd
sz

".,...
~

80

SUPPLY VOLTAGE vt ..... l0V. V-.,10V
AMBIENT TEMPERATURE (TA'-2SoC
LOAD RESISTANCE (RLI" 10 Kn
LOAD CAPACITANCE (el' = 0 pF

~ "'-

,---""

60

0

> 40

§
ffi

0
-45

2;
0

10

10 2

103

f
'd

-90 ~

'" I"'..

20

...'"
.,'"...

-13S§

'\ -ISCi

'"

10"

.
0

g
z

~
la'

~

10'

FREQUENCY 'Hz)

Fig. 9 - Open-loop gain and phase-shift response.

3-240

10 6

CA5420A, CA5420
APPLICATION CIRCUITS
Plcoammeter Circuit
The exceptionally low input current (typically 0.2 pAl
makes the CA5420 highly suited for use in a picoammeter
circuit. With only asingle 10K-megohm resistor, this circuit
covers the range from ±1.5 pA. Higher current ranges are
possible with suitable switching techniques and current
scaling resistors. Input transient protection is provided by
the 1-megohm resistor in series with the input. Higher
current ranges require that this resistor be reduced. The
10-megohm resistor connected to pin 2 of the CA5420
decouples the potentially high input capacitance often
associated with lower current circuits and reduces the
tendency for the circuit to oscillate under these conditions.
10k Mil

Hlgh-Input-Reslstance Voltmeter
Advantage is taken of the high input impedance of the
CA5420 in a high-input-resistance dc voltmeter. Only two
1.5-V "AA"-type penlite batteries power this exceedingly
high-in put-resistance (>1 ,000,000 megohms) dc voltmeter.
Full-scale deflection is ±500 mY, ±150 mY, and ±15 mY.
Higher voltage ranges are easily added with external input
voltage attenuator networks.
The meter is placed in series with the gain network, thus
eliminating the meter temperature coefficient error term.
Supply current in the standby position with the meter
undeflected is 300 /lA. At full-scale deflection this current
rises to 800 /lA. Carbon-zinc battery life should be in excess
of 1,000 hours.
+1.5V

1.5k
1.5k,l%

ow
Ik

430A,I%
±1.5 pA

150.!l.,1%

seA

Ilk

I50A,I%

±15mV
1.1 k

1%

seA
1%

92C5-34oo4

92C5-34oo2

Fig. 10 - CA5420 picoammeter circuit.

Fig. 11 - CA5420 high-input-resistance voltmeter.

3-241

-'
«en
za:

~~
w:;;

:SeC

;II

CA5470

HARRIS

Quad Microprocessor BiMOS-E Operational
Amplifiers With MOSFET Input/Bipolar Output

August 1991

Features

Description

• High-Speed CMOS Input Stage Provides

The CA5470 series are integrated circuit operational
amplifiers that combine the advantages of both
high-speed CMOS and bipolar transistors on a single
monolithic chip. They are constructed in the
BIMOS-E process which adds drain-extension
implants to 3f1m polygate CMOS, enhancing both the
voltage capability and providing vertical bipolar
transistors for broadband analog/digital functions.
This process lends Itself easily to high-speed
operational amplifiers, comparators, analog switches
and interface peripherals, resulting in twice the speed
of the conventional CMOS transistors having similar
feature size.

~ Very High ZI ••••••••••••••••••••••• 5TO (Sxl 0 120) Typ.
~

Very Low II ••••••••••••••••• 0.SpA (Typ) at SV Operation

~

Very Low 110 ••••••••••••••• 0.SpA (Typ) at SV Operation

• ESC Protection to 2000V
• 3V to 16V Power Supply Operation
o Fully Guaranteed Specifications Over Full Military Range
o Wide BW (14MHz)j High SR (SV/fls) at SV Supply

• Wide VICR Range From -O.SV to 3.7V (Typ) at SV Supply
• Ideally Suited for CMOS and HCMOS Applications
• +5V Characteristics for Microprocessor Applications

Applications
• Bar Code Readers
• Photo diode Amplifiers (IR)
• Microprocessor Buffering

BiMOS-E are broadbased bipolar transistors that
have high transconductance, gains more constant
with current level, stable "precision" base-emitter
offset voltages and superior drive capability. Excellent
Interface with environmental potentials enable use in
5V logic systems and future 3.3V logic systems .
ESO capability exceeds the standard 2000 volt level.
The CA5470 series can operate with single supply
voltages from 3V to 16V or ±1.5V to ±8V. They have
guaranteed speciflcations at both 5V and ±7.SV at
room temperature as well as over the full -550 C to
+1250 C military range.

• Ground Reference Single Supply Amplifiers
• Fast Sample and Hold
• Timers
• Voltage Controlled Oscillators

The CA5470 series Is supplied In the standard 14
lead dual-in-line plastiC package (E sufflx) and the 14
lead small outline package (M suffix). The CA5470 is
also available in chip form (H suffix).

• Voltage Followers
• V to I Converters
• Peak Detectors
• PreCision Rectifiers
• SV Logic Systems
• 3V Logic Systems

Pinout

E AND M SUFFIXES

TOP VIEW
OUTPUT 1

OUTPUT 4

NEG.
INPUT 1

NEG.
INPUT 4

POS.
INPUT 1

POS.
INPUT 4

V·

V+
POS.
INPUT 2

POS.
INPUT 3
NEG.
INPUT 3

NEG.
INPUT 2

OUTPUT 3

OUTPUT 2

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

3-242

File Number

1946.1

CA5470
MAXIMUM RATINGS, Absolute-Maximum Values
DC SUPPLY-VOLTAGE
(Between V+ and V- Terminals) •.••.•••.••••••.••••••..••.•..••.•...••...............................•.•.••••.•••••••••.•••• 16 V
DIFFERENTIAL MODE INPUT VOLTAGE .•.••...•••.••••••.•.••••.•••••••...••••.•••••••.••.•••••••••..••••...••••..•..••..••••. ±8 V
COMMON-MODE DC INPUT VOLTAGE •••.•.••.•••.••••..•.•••••••.••••.•••••••••••••••••••••••••.•.•••••.•..•. (V+ +8 V) 10 (V- -0.5V)
INPUTTERMINALCURRENT •••..••••.••••..•••..•.•••••.•••..••••.••••.••••.•••••.••••••.••.•.•••••••.••.••••.••••...••...••. 1 mA
DEVICE DISSIPATION:
WITHOUT HEAT SINK up 10 550 C .••••••.•.••...•••...•••.•..••.•.••••••••••••••••••••.••••.••••••••••••.•..•..••.•••.•••••••....•••..•••. 630 mW
above 550 C ••.••••••••..••••••.••.•.•••..••••..•.•••..••••..•.••••.••.••••••.•••.••••••••..••.•••. Derale Linearly 6.67 mWfC'C
WITH HEAT SINKupI0900 C •••..••.••..•••...•••••..•••.•••••••.••••.••••••..•.••.•.•••..••••••..••.••••••••.••••.••..••.•••..••...••.•• 1 W
above 900 C ••.•••.•••••.••••.••.•...•••..•••••.••••..••••...•••.••.•.•••.••••••••••••.••••.••••••• Derale Linearly 16.7 mW/oC
SMALL OUTLINE PACKAGE up 10 650C .••.•••.••••..••.•.•••••.•••...•.••...•••...•••.•.•....•...••.••..••..•••••.••••.•••••••••••••••••••.•••• 500 mW
above 650 C .••...••...•••...•.•••.••.••••.••..••.•••••.•..•••••..••••..•••.•••.••..••.•.•••.•••.• Derale Linearly a15.9 mW/oC
TEMPERATURE RANGE:
OPERATING(alitypes) .•••..•••.•••••••.••.••.•.•••..•••••.••••..•••.•..•••..............••.........•....••....• -55to+1250C
STORAGE (all types) .••..•.••.•..•••...•.•..•.•••..••...•••.•..•....•.•••.•..•.••..•...•.•...•.....•...•.•.....• -6510 +150o C
OUTPUT SHORT-CIRCUIT DURATION' ...•.•..•.••.••....•.•.•••••••••••..•.•....••.••••••.••.••.••.•••..••.••••••..•••. INDEFINITE
LEAD TEMPERATURE (DURING SOLDERING):
AI distance 1/16 ± 1/32 (1.59 ± 0.79 mm)lrom case lor 10 seconds max ...•••....•..••.•.•••....•••..••..••.•..•••..••...••. +2650 C

-'
<[CJ)

za:

*Short circuit may be applied to ground or to either supply,

OW

~~

a: c..
TYPICAL VALUES INTENDED ONLY FOR DESIGN GUIDANCE V+ = 5 V,
CHARACTERISTIC
Inpul Resistance

RI

Input Capacitance

CI

Unity Gain Crossover Frequency

IT

Slew Rale

SR

Transient Response:

Ir

Rise Time/Fall Time
Overshool

5V/~s

w::;;:

= 250 C (Unless Otherwise Specified)

TEST CONDITIONS

TYPICAL VALUES

UNITS

5

TO

1=1 MHz

3.1

pF

14

MHz

5

v/~s

RL=2kO

27/25

ns

(Voltage Follower)

20

%

1

~s

436

kHz

VOUT=3.65Vo- o
CL=25pF

Settling Time (4Vp _p Inpullo < 0.1 %)
Full Power BW (VOUT = 3.65Vp _p) SR =

v- = 0, TA

AV=l

3-243

&<[

CA5470
ELECTRICAL CHARACTERISTICS At TA = 250 C. V+ = 5 V. V- = Gnd
LIMITS
CHARACTERISTICS

MIN.

Input Offset Voltage

IVlol

Input Offset Current

hlol

TYP

MAX.

UNITS

6

22

mV

0.5

5

pA
pA

-

Input Current

II

-

0.5

10

Common-Mode Input Range

VICR

3.5

-0.5 to 3.7

0

V

Common-Mode Rejection Ratio
VICR = 0 to 3.5 V

CMRR

55

70

-

dB

Power-Supply Rejection Ratio
AV=2V

PSRR

60

75

-

dB

Positive Output Voltage Swing
RL=2ktoGND

VOM+

4

4A

-

V

Negative Output Voltage Swing
RL=2ktoGND

VOM-

-

0.06

0.10

V

10

Total Supply Current VOur=2.5V

ISUPPLY

-

8

Unity Gain Bandwidth Product

fr

10

14

Slew Rate

SR

4

5

mA

-

V/~s

-

mA

MHz

Output Current
Source to opposite supply
Sink to opposite supply
Open Loop Gain

0.5Vto 3.5 V

4

5.5

ISINK

0.8

1.2

RL= 10k

80

90

ISOURCE

-

mA
dB

ELECTRICAL CHARACTERISTICS At TA = -550 C to +1250C. V+ = 5 V. V- = Gnd
LIMITS
CHARACTERISTICS

MIN.

II

-

Input Offset Voltage

IVlol

Input Offset Current

11101

Input Current
Common-Mode Input Range

TYP

MAX.

UNITS

6

25

mV

550

5500

pA

550

11000

pA

-0.5 to 3.7

0

V

VICR

3.5

Common-Mode Rejection Ratio
VICR=Ot03.5V

CMRR

50

65

-

dB

Power-Supply Rejection Ratio
AV=2V

PSRR

58

75

-

dB

Positive Output Voltage Swing
RL=2ktoV-

VOM+

3.8

4.2

-

V

Negative Output Voltage Swing
RL=2 ktoV-

VOM-

-

0.08

0.11

V

Total Supply Current VOUT = 2.5 V

ISUPPLY

-

9

11

Unity Gain Bandwidth Product

fr

8

12

Slew Rate

SR

3

5

-

mA
MHz
V/~

Output Current
Source to opposite supply

ISOURCE

4

5.5

Sink to opposite supply

ISINK

0.8

1.2

-

RL=10k

80

90

-

Open Loop Gain

0.5Vto3.5V

3-244

mA
mA
dB

CA5470
ELECTRICAL CHARACTERISTICS At TA = 250 C, V+ = 7.5 V, V- = -7.5 V
LIMITS
CHARACTERISTICS
Input Offset Voltage

TYP

MAX.

UNITS

25

mV

hlol

-

5
0.5

5

pA

II

-

1

10

pA

-7.8 to 6.0

-7.5

V

MIN.
IVlol

Input Offset Current
Input Current
Common-Mode Input Range

VICR

5.8

Common-Mode Rejection Ratio
VICR=Ot03.5V

CMRR

60

70

-

dB

Power-Supply Rejection Ratio
l;.V=2V

PSRR

65

76

-

dB

Positive Output Voltage Swing
RL=2ktoGND

VOM+
6.3

6.5

6.4

6.6

-

-

-7.47

-7.45

-

-7.3

-7.1
11

V

RL = 10ktoGND
Negative Output Voltage Swing
RL= 2kloGND

V

VOM-

RL=10ktoGND
ISUPPLY

-

10

Unity Gain Bandwidth Product

IT

12

16

SlewRaie

SR

4

7

Output Current
Source to opposite supply

ISOURCE

6.2

6.8

1

1.4

80

90

Total Supply Current VOUT=GND

Sink to opposite supply
Open Loop Gain

ISINK

-5Vto+5V

RL = 10k

ELECTRICAL CHARACTERISTICS At TA = 550 C to +125 0 C, V+ = 7.5

V. V-

-

-'

«en

rnA
MHz

VIps
rnA
rnA
dB

= -7.5 V
LIMITS

CHARACTERISTICS

MIN.

Input Offset Voltage

IVlol

Input Offset Current

hlol

Input Current

-

TYP

MAX.

UNITS

5

30

mV

550

5500

pA

II

-

1100

11000

pA

Common-Mode Input Range

VICR

5.8

-7.8 to 6.0

-7.5

V

Common-Mode Rejection Ratio
VICR=Olo3.5V

CMRR

58

70

-

dB

Power-Supply Rejection Ratio
6V=2V

PSRR

60

76

-

dB

Positive Output Voltage Swing
RL= 2kloV-

VOM+
6

6.2

-

6.1

6.4

-

-7.47

-7.45

-7.3

-7.1

11

12

RL = 10k to GND
Negative Output Voltage Swing
RL=2kloV-

VOM-

V

ISUPPLY

-

Unity Gain Bandwidth Product

IT

10

15

Slew Rate

SR

3

7

6.2

6.8

1

1.4

60

90

RL = 10ktoGND
Tolal Supply Current

VOUT=GND

Output Current
Source to opposite supply
Sink to oPposite supply
Open Loop Gain

-5Vlo+5V

ISOURCE
ISINK
RL= 10k

3-245

V

-

rnA
MHz

VIps
rnA
rnA
dB

za::
ow
~§

a::
"w:;;

@)«

CA5470
v+
4

ISmA/AMP

,-

1-----------1
1

- ------

I

TO
BIAS
CIRCUIT

50lJ-A

~--'--_+_-(

'2 rnA

-INPUT

2k

I

2k

+-+-__-+_ _ _.-.-_ _ _

L-_-+_-4_ _ _ _ _

1_- _________I
PMOS
DIFFERENTIAL
INPUT STAGE

_____ -.J

~

__

_+~----.-~---~~~1\

________ 1

_________
OUTPUT
STAGE

COMPOSITE
MILLER
GAIN STAGE

GROUNDED GATE
LEVEL SHIFTER

~

GNDOR
-SUPPLY

Figure 2 - Block diagram of the CA5470.

69.7

T
91.2

(2.461

V~ !S:w. v ~ d 1_1~~m,
14

30

J

12

20

10

r--

""-

>I-

~

8

:::> 6
0

69.7(,.77)------1·1

>

Dimensions in parentheses are In millimeters and are derived from the
basic inch dimensions as indicated. Grid graduations are in mills (10-3
inch). The layout represents a chip when it is part of the wafer. When the
wafer is cut into chips, the cleavage angles are 570 instead of 9(JO with
respect to the face of the chip. Therefore, the isolated chip Is actually
7 mils (0.17 mm) larger in both dimensions.
Figure 3 - Dimensions and pad layout for CA5470H.

V+=5V.V-=OV
4

~

2

~~
10K

lOOK

1M
10M
FREQUENCY

100M

Figure 4 - Maximum output voltage swing vs frequency.

3-246

mHARRIS

HA-2400/04/05
PRAM Four Channel
Programmable Amplifier

August 1991

Features

Applications

o Programmability

• Thousands of Applications; Program:
~ Signal Selection/Multiplexing

o

High Rate Slew •••••••••••••••••••••••••..•• 30V/IIS

o Wide Gain Bandwidth •••••••••.•••.••••..•• 40MHz

~

• High Gain ••••••••••••••••••••••••••••••••• 1S0kVN

~

Oscillator Frequency

• Low Offset Current ••••••••••••••••••••••.••••• SnA

~

Filter Characteristics

• High Input Impedance •••••••••.••••••••••••• 30MO

~

Add-Subtract Functions

• Single Capacitor Compensation

.. Integrator Characteristics

Operational Amplifier Gain

.. Comparator Levels

• DTL/TTL Compatible Inputs

• For Further Design Ideas, See App. Note S14.

Description
HA-2400/04/05 comprise a series of four-channel
programmable amplifiers providing a level of versatility
unsurpassed by any other monolithic operational amplifier.
Versatility is achieved by employing four Input amplifier
channels, anyone (or none) of which may be electronically
selected and connected to a single output stage through
DTLmL compatible address inputs. The device formed by
the output and the selected pair of inputs is an op amp
which delivers excellent slew rate, gain bandwidth and
power bandwidth performance. Other advantageous
features for these dielectrically Isolated amplifiers include
high voltage gain and input impedance 'coupled with low
input offset voltage and offset current. External
compensation is not required on this device at closed loop
gains greater than 10.

Pinout

Each channel of the HA-2400/04/05 can be controlled and
operated with suitable feedback networks in any of the
standard op amp configurations. This specialization makes
these amplifiers excellent components for multiplexing
signal selection and mathematical function designs. With
30V/lls slew rate, 40MHz gain bandwidth and 30M ohms
input impedance these devices are ideal building blocks for
signal generators, active filters and data acquisition
designs. Programmability, coupled with 4mV typical offset
voltage and SnA offset current, makes these amplifiers
outstanding components for signal conditioning circuits.
HA-2400/04/0S are available in a 16 pin Dual-In-Line
package. HA-2400 is specified from -55 0 C to +125 0 C.
HA-2404 is specified over the -25 0 C to +85 0 C range,
while HA-240S operates from OOC to +750C.

Schematic

HA1-2400/04/0S (CERAMIC DIP)
TOP VIEW

HA-2400

-IN1
+IN1
-IN2

TRUTH TABLE
01

DO

EN

SELECTED
CHANNEL

L

L

H

1

L

H

H

2

H

L

H

3

H

H

H

4

X

X

L

NONE

~~~~¥1~~~=¥==f===I=)TDAODITIONAL
INPUT STAGES

0<,

AT'

16K
DO

-VEE

01

Diagram Includes: One Input Stage, Decode Control,
Bias Network, and Output Stage.

CAUTION: These devices are sensitive to eleclrostalic discharge. Proper I.C. handling procedures should be followed.
Copyright @) Harris Corporation 1991

3-247

File Number

2891

...I
«

~

SLEW RATE

0.9

§

I'"

""

-

0

~T

I -551-50

~

'"'"

I"-

0

f-

-c

0

0

+
S

\

:z
0.8

+50

+75

-551-50 -25

+100 +125

Temperature (oC)

+25

+50

+75

'"

+100

Temperature (oC)

+125

-'
«en
z a:
ow

OPEN LOOP FREQUENCY AND PHASE RESPONSE

iii"

;'2o~~~-r-nnr-'''Tr'-rn~"",,-rTTI-r-rrnl
•• ".
CROSSTALK REJECTION, AV = +1

wW

-

~100~~~~··~_~~~~~~~~~~;H~;:++~~T~30 ~

POWER SUPPlY CURRENT DRAIN
AS A FUNCTION OF TEMPERATURE

~~~::~~ : ~~~.~~ ~

t-- VSUPPl Y .. !10,OV ~

~

~

;::::~

~

80

~
9

-

~

o

10

iii"
E.

::;~

S!

'25

.50

.15 HOO ,,25

80

60
40

9

0

-r--

~o

1M

10M

15PFI~

~

.."

T i I f l -11

~

1'

lK

100

,

K

00

10K
lOOK
FREQUENCY (Hz)

10M

1M

OPEN LOOP VOLTAGE GAIN
vs. TEMPERATURE

1.1

1051-- vSUPPLV

~VLpPLyl. "oLo,~~
VSUPPLV" .±.15

1.0

. / 'l VsLEWRATE

I

V

BANDWIDTH'

--

l--

- ,:t100V

-.... ~
~

r-+ ~~

iii
-c

o
c 10
';;;

-

'"
5

0.9

/'/'

~
"
i

:z

I

D.8

±ID

±IS

100M

'I<:

II 0

~
-c.~_

TOOK

0, -551-50 -25

±20

0

.25

.50

>15

Temperature (oC)

Supply Voltage

3-249

+100

+12

~
~

"z
~
:2
(f.I

m~

JI:II

r::::

1.2

~

..'"

10K

Op

..::::
......

NORMALIZED A.C. PARAMETERS
vs. SUPPLY VOLTAGE

c:

lK

H1tr- ;001'1 p'r--

-20
~
10

{;

150

FREQUENCY RESPONSE vs. CCOMP

ffi

-c

120

...

I~~

120

~ 20

Temperature (oC)

.s

90

I- 1I11
GAI.N4-++-H-+.j:j>~!';.'N,~'+1-H 180

CCOMP • 15p'

100

;,t

60

FREQUENCY (Hz)

~ 100

0

---

"

~

--CCOMP"OpF

~_

z

1-551-50 -25

I II

20

z

w

3

,,~_

"

~ 60~-++U-+~~~~~~,~_~-k~~,.~,~~++H-~rH~E
> 40

100M

~§

a:

Q.

w:;;

:5«

HA-2400/04/05
Typical Performance Curves (Continued)
OUTPUT VOLTAGE SWING vs. FREQUENCY

EQUIVALENT INPUT NOISE VS. BANDWIDTH
100

CCOMP

OpF

CCOMP

15 F

I

i"

:>

~

10
1---,10K SOURCE RESISTANCE

W

1= r-OSOURCE RESISTANCE

'"

5z

1::::> 1.0
0..

I--:::rtt

V

!?:

v

0"·"
~O,'bt.

..~.,.,0"

"'~\.

....~~ff.

/f

IIIII

0.1

10K

100Hz

10M

lOOK
1M
FREQUENCY (Hz)

100

lK

10kHz

100kHz

1MHz

UPPER 3dB FREQUENCY
LOWER 3dB FREQUENCY-10Hz
BROADBAND NOISE CHARACTERISTICS

INPUT NOISE VS. FREQUENCY

10

1kHz

SLEW RATE AND TRANSIENT RESPONSE

10K

lOOK

FREQUENCY (H:rJ

Typical Applications
HA-2400
SAMPLE AND HOLD

HA-2400
AMPLIFIER, NONINVERTING PROGRAMMABLE GAIN
INPur

..
,.

Sample Charging Rate

=2 VlSec.
C

500

Hold Drift Rate =

~ VlSec.
C

500

Q

Switch Pede.tal Error = _Volts

C

tl '" 150 x 10-6A
12 '" 200 x 10-9 A @ +2SoC
'" 600 x 1O-9A @ -550C
100 x 10-9A @ +12SoC
Q '" 2 x 10-12 Coulomb

For More Examples. Sse Harris Application Note 514

3-250

HA-2406

(IlHARRIS

Digitally Selectable Four Channel
Operational Amplifier

August 1991

Features

Applications

• TTL Compatible Inputs

• Digital Control Of:
Analog Signal Multiplexing
,. Op Amp Gains

~

• Single Capacitor Compensation
• Low Crosstalk •••••••••••••••••••••••••••••• -110dB

,. Oscillator Frequencies

• High Slew Rate ••••••••••••••••••••••••••••• 20V/IlS

,. Filter Characteristics

• Low Offset Current. • • • • • • • • • • • • • • • • • • • • • • • • • •• 5nA

,. Comparator Levels

• Offset Voltage ••..•••.••••••••••••••.•.•••••••• 7mV

• For Further Design Ideas See Application Note 514

• High Gain-Bandwidth •••••••••••••••••••••. 30MHz
• High Input Impedance ••••••••••.•••••••••••• 30Mn

Description
The HA-240S is a monolithic device consisting of four op
amp input stages that can be individually connected to one
output stage by decoding two TTL lines into four channel
select signals. In addition to allowing each channel to be
addressed, an enable control disconnects all input stages
from the output stage when asserted low.

Dielectric isolation and short-circuit protected output
stages contribute to the quality and durability of the
HA-240S. When used as a simple amplifier, its dynamic
performance is very good and when its added versatility is
considered, the HA-240S is unmatched in the analog world.
It can replace a number of individual components In analog
signal conditioning circuits for digital signal processing
systems. Its advantages include saving board space and
reducing power supply requirements.

Each input-output combination of the HA-240Sls designed
to be a 20V/lls, 30MHz gain-bandwidth amplifier that is
stable at a gain of ten but by connecting one external 15pF
capacitor all amplifiers are compensated for unity gain
operation. The compensation pin may also be used to limit
the output swing to TTL levels through suitable clamping
diodes and divider networks (see Application Note 514).

Pinout

HA9P2406-5, -9
HA3-2406-5, HA1-2406-5
TOP VIEW

The HA-240S Is available In a lS pin dual-in-Iine package
and is guaranteed for operation over the full commercial
temperature range (OOC to +75 0 C). An SOIC package
option is also available with -5 and -9 temperature grades.

Schematic
HA-2406

liN·

liNt-

01 R2
EZ-

~i'- i'- I'VSUPPL Y =± 20.0V

"f".i'-

0.

0.

::l
(f)

4.0

VSUPPLY
VSUPPLY

FreQuencv ·Hz

=±15.0V
=±10.0V

FREQUENCY RESPONSE vs CCOMP

III
25

50

75

Temperature (DC)

NORMALIZED A. C. PARAMETERS vs SUPPLY VOLTAGE
2

OPEN LOOP VOLTAGE GAIN vs TEMPERATURE

1

/"
9

VSUPPLY =± 20.0~"

-::::::
it"

0

I----' 7'

VSUPPLY
VSUPPLY

BANDWIDTH

=±15.0~.",
=± 10.OV

105

l/slEWRATE /

V
V

~

"
8

±15

 10
4. Vo = ±10.0V
5. CL

= 50pF

6. Absolute Maximum Ratings are limiting values, applied individually. beyond which the
serviceability of the circuit may be Impaired.

7. Vo = ±200mV
8. See Transient Response Tesl Circuits and
Waveforms.

9.

t..v =

10. This parameter value is based on design calculations.
11. Full Power Bandwidth guaranteed based on

slew rate measurement using:
FPBW = S.R./2nVpeak.
12. VOUT = ±5V.

±5.0V

3-259

~~
~~

o

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
(Note 1,4)

-'

 10
4. Vo = ±10.0V
5. CL

= 50pF

6. Absolute Maximum Ratings are limiting values, applied individually, beyond which the

serviceabilHy of the circuit may be impaired.
7. Vo

= ±200mV

8. See Transient Response Test Circuits and
Waveforms.

10. This parameter value is based on deSign cal-

culations.
11. Full Power Bandwidth guaranteed based on

slew rate measurement using:
FPBW = S.R.l2.Vpeak.
12. VOUT = ±5V.

9. AV = ±5.0V

3-263

....I

 10
4. Vo

= ±10.0V

5. CL

~

50pF

6. Vo

~

±200mV

7. fl.V

en

Za:

-

40
±10.0

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
(Notes 1,4)

-'
 1.0

+25

26

~,. 10

-

BIAS CURRENT

toM

1M

100M

FREDUENCY(HlJ
0.7

·55-50

•

-25

+25

+5.

+15

+100

+125

TEMPERATURE(OCI

OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
BANDWIDTH CONTROL PIN TO GROUND

NORMALIZED AC PARAMETERS va.
SUPPLY VOLTAGE AT +250 C
1.1

'"

SLEW,Y , /

BA~DWIJTH

BANDWIDTH

~TE

"'"~
~

~
0

9

120

I

100

0"

••

11111

IIIIiII
30pF

60

I.-'

.0
30DpF

20

"~

JI

dW

-20

10

100

i",.

1DOpF

I
10K

tOUK

1M

10M

±tS

±ZII

NOTE: External compensation components are not required for stabmty. but
may be added to reduce bandwidth if desired.

SUPPLY VOLTAGE

OPEN LOOP VOLTAGE GAIN vs. TEMPERATURE
B8
87

••

OUTPUT VOLTAGE SWING va. FREQUENCY AT +25 0 C
35

VSUJPLY"'~20V

H'
vsurlY,x.
V SUl.'l

-.........

v· i:y

./
-55 -50

-25

V SUPP'L ~ ~'±20V

3D

.

i'-- ~
- -- ...... "

i

~>

+15

+100

LlL'J!tJ
11111111

20

I\.

I

11111111 I

15

v SUPPLY" ±10V

10

"""" "+25
0
+50
TEMPERATURE(OC)

V

25

~

...........

83

.2

100M

FREQUENCY (HZ)

..•±to

+125

o
10K

100K

1MEG

llMEG

FREnUENCY(H:r)

3-268

HA-2520/2520/2525
Performance Curves

(Continued)

POWER SUPPLY CURRENT vs.
TEMPERATURE

.

VOLTAGE FOLLOWER PULSE
RESPONSE

POWER SUPPLY REJECTION RATIO vs.
FREQUENCY
UD

..

I I

I I

144
~42

.
"
"

\lS~Ppt'f.1~29V

h ~

IISU'PlY·tISV

D

CI

IOOkH.

UH,

10kH.

LlIIlkH.

1MH.

fREQUENtYIH.}

RL = 2Kn. CL = 50pF

Horizontal = 1aOns/Div.

Upper Trace: Input; 1.67V/Div.

TA = +250 C. Vs = x15V

Lower Trace: Output; 5V/Div.

Test Circuits
SLEW RATE AND
SETTLING TIME

+1':1

INPUT
·1.67V

+5V

OUTPUT

I

~:

-91=--=---

I

-I

~'V

L

±67~
INPUT
OV

:1

stew : !~~~~ ~~~~

I I ~T I RATE

SLEW RATE AND
TRANSIENT RESPONSE

TRANSIENT
RESPONSE

I ANAL VALUE

L

OVERSHOOT

±::~-----~

Ls~!~~
TIME

~

SUGGESTED
VOS ADJUSTMENT

+200mVand OV to -200mV at tho output

IN~

- 5PFf j1333S1.

l667S1.

i
=

OUT

50pF

.. ~

~~

o

RT

~B~

OUT

Tested Offset Adjustment Range is Ivas +1 mV Iminimum referred to ouput.
Typical range Is +20mV to -18mV with RT = 20kn.

Settling Time Circuit

+V~~
2J'. 7 .001p.F

INPUT 667.2.0.

1667.0.

p;~~
-~

2N44~G
-iI
2000.0.

CR1QCR2
"::"

-

.001p.F"::"
2001.0.

OUTPUT

i'-

4999.9.0.
SETTUNG TIME
TEST POINT

• AV=-3
• Feedback and Summing Resistor Ratios Should be 0.1 %
matched.
• Clipping Diodes CR1 and CR2 are Optional. HP5082-2810
Recommended.

3-269

!;i§

a: a..

~RISETIME

NOTE: Measurement on both positive and negative transitions from OV to

....I
«(I)
za:
ow

HA-2520/2522/2525
Typical Application

FREQUENCY RESPONSE FOR
INVERTING UNITY GAIN CIRCUIT

10K
IN:: 10K
2K

~OUT
+

-!- -=

500pF

15

HA-2520

10

GAIN

5K

"'" ,
:i

i"o

-,
-lD

NOTE: Compensation Circuit for AV =-1
Slew Rate'" 120V/1'8
Bandwidth'" 1OM Hz
Selliing Time (0.1 %) '" 500ns
Capacitance at pin B must be minimized for maximum bandwidth.
Tested and functional with supply voltages from ±4V to ±15V.

Die Characteristics
Transistor Count .............•..................... 40
Die Dimensions ...•................... 57 x 65 x 19 mils
Substrate Potential ........................... Unbiased
Process •................................... Bipolar-DI
Thermal Constants (OCIW)
9ja
9jc
HA2-Metal Can (-2, -5, -7)

206

56

HA2-Metal Can (-8,/883)

168

52

HA3-Plastic Mini-DIP (-5)

90

39

HA4-Ceramic LCC (/883)

99

37

HA7-Ceramlc Mini-DIP (-8, /883)

100

28

HA7-Ceramic Mini-DIP (-2, -5, -7)

204

112

3-270

TASI'

-15

lDK
START 10000.000Hz

I

lOUie

1M

I

,

1\

'-

"-4,'
.f"
-135 0
-1800

lDM
STOP 30 DOII.OOOHz

HA-2529

;J)HARRIS

Uncompensated, High Slew Rate
High Output Current, Operational Amplifier

August 1991

Features
o

•
o

•
•
•
•

Applications

High Slew Rate ••••••••••••••.••••••••••••• 150VIjJs
Fast Settling .......•••..•.•..•••••••.••••••• 200ns
Wide Power Bandwidth ••••••.•••••••••••••••• 2MHz
Wide Gain Bandwidth (AV ~ 3) •••••••••••••• 20MHz
High Inputlmpedance •••••••••••••.•••••••• 130MO
Low Offset Current •••••.•••••••••••••••••••••• 5nA
High Output Current ••••.••••••••••.•••••••• ±30mA

o Data Acquisition Systems
o R.F. Amplifiers
o

Video Amplifiers

o Signal Generators
o Pulse Amplification

Description
The HA-2529 is a monolithic operational amplifier which
typifies excellence of design. With a design based on years
of experience coupled with the reliable dielectric isolation
process, these amplifiers provide an outstanding
combination of DC and AC parameters at closed loop gains
greater than 3.
The HA-2529 offers 150VljJs slew rate and fast settling
time (200ns), while consuming a mere 6mA of quiesent
current, making these amplifiers ideal components for video
circuitry and data acquisition designs. With 20MHz
gain-bandwidth combined with 7.5kVN open loop gain, the
HA-2529 is an ideal component for demanding signal
conditioning designs.These devices provide ±30mA output

Pinouts

current drive with an output voltage swing of ±10V making
then suited for pulse amplifier and R.F. amplifier
components.
The HA-2529 will upgrade output current, slew rate, offset
voltage drift and offset current drift in systems presently
using the HA-2520/22/25 or EHA-2520/22/25.
The HA-2529-2 has guaranteed operation over the military
temperature range (-55 0 C to +125 0 C) and the HA-2529-5
has guaranteed operation over the commercial temperature
range (OOC to +750 C). MIL-STD-SS3 product and data
sheets are available upon request.

Schematic

HA7-2529 (CERAMIC MINI-DIP)
HA3-2529 (PLASTIC MINI-DIP)
TOP VIEW

COMP

v+

INPUT+
OUTPUT

RIB

30

HA2-2529 (TO-99 METAL CAN)
TOP VIEW

DI3A

COMP

v·
INRJT·

v·

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyrighl © Harris Corporation 1991

3-271

File Number

~895

Specifications HA-2529
Absolute Maximum Ratings (Note 1)

Operating Temperature Ranges

Voltage Between V+ and V- Terminals ••••••••••••••••••• 40.0V
Differential Input Voltage ••••••••••.••••••••••••••.•••••• ±15V
Output Current .•.••.••.••••.••.••••••.••••.••••• 90mA (Peak)
Internal Power Dissipation (Note 10) •••••••••••••••••.• 300mW
Maximum Junction Temperature ••••••••••••••••••••••• +1750 C

HA-2529-2 ••••••••••••.••••••••••••••• -550C S TA:=; +1250 C
HA-2529-5 •••••••••.•••••••••.••••••••.•• ooc:=; TA :5 +750 C
Storage Temperature Range ••••••••••••• -650C :5 TA:5 +1500 C

Electrical Specifications Vs =±15V, CL = 50pF, RL = 2kO, Unless Otherwise Specified
HA-2529-2
-550C to +1250 C
PARAMETER

HA-2529-5
oOC1o +75 0 C

TEMP

MIN

TVP

MAX

MIN

+250 C
Full
Full
+250 C
Full
Full
+250 C
Full
Full
Full
+250 C
+250 C
+250 C
+250 C

-

2

5
8

-

TVP

MAX

UNITS

2

10
14

mV
mV
I'VloC
nA
nA
nNoC
nA
nA
nNCC
V
MO
pF
nVl..;rti.

INPUT CHARACTERISTICS
Offset Voltage (Note 8)
Average Offset Voltage Drift (Note 8)
Bias Current (Note 8)
Average Bias Current Drift (Note 8)
Offset Current (Note 8)
Average Offset Current Drift
Common Mode Range
Differential"lnput Resistance (Note 11)
Differenliallnput Capacitance
Input Noise Voltage (f = 1 kHz)
Input Noise Current (f = 1 kHz)

-

-

10
50
80
0.2
5
10
0.02
±13
130
3
20
1.8

±10
50

-

-

200
400

-

25
50

-

±10
50

-

-

-

10
50
80
0.2
5
10
0.02
±13
130
3
20
1.8

-

250
400

-

50
100

-

pN..;rti.

TRANSFER CHARACTERISTICS
large Signal Voltage Gain (Note 3)
Common Mode Rejection Ratio (Note 5)
Gain-Bandwidth Product (Note 2, 11)
Minimum Stable Gain

+250 C
Full
Full
+250 C
+250C

10
7.5
80
15
3

18
15
100
20

-

Full
+250 C
+250 C
Full
+250 C

±10
2.1
30
25

±12
2.6
35
30
30

-

-

20
10
150
200

45
30

4.5
90

8

-

-

7.5
5
74
15
3

18
15
100
20

±10
2.1
30
25

±12
2.6
35
30
30

-

-

-

kVN
kVN
dB
MHz
VN

OUTPUT CHARACTERISTICS
Output Voltage Swing
Full Power Bandwidth (Notes 3 & 6)
Output Current (Note 8)
Output Resistance (Open loop)

-

-

-

-

V
MHz
rnA

rnA
0

TRANSIENT RESPONSE (AV = +3)
Rise Time (Note 2, 7)
Overshoot (Note 2, 7)
Slew Rate (Note 3, 7)
Settling Time (Note 4, 7)

+250 C
+250C
+250 C
+250 C

135
-

Full
Full

80

-

-

135

-

20
10
150
200

50
30

ns
%
VII's
ns

4.5
90

8

rnA
dB

-

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 12)

-

NOTE:
1. Absolute maximum ratings are limiting values, applied individually boyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.
2. VOUT = ±200mV. AV ~ 3.
4. Settling Time is specified to 0.1 % of final value for a 10V output step and
AV = -1.

= ±10V.

6. Full Power Bandwidth Is guaranteed by equation: FPBW =

74

-

7. See Transient Response and Settling Time Test Circuits.
8. Refer to typical performance curve In data sheet.
9. VOUT = ±5V.
10. Refer to package thermal constants in Die Information section.

3. VOUT = ±10V.

5. ----0 OUT

TIME

Tested Offset Adjustment is IVos +1 mV I

NOTE: Measured on both positive and
negative transitions from 0 to

minimum referred to output Typical range

is +2BmV to -18mV with RT = 20kO.

+200mV and 0 to -200mV.

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

Horizontal Scale: (200n8/Div.)
Vertical Scale: (2V/Oiv. Input)
(5V/Oiv. Output)

Horizontal Scale: (200n8/0iv.)
Vertical Scale: (50mV/Oiv. Input)
(100mV/Oiv. Output)

--'

"
g

5
4

III'"''

+-+-+-+-+-+-+-+.-..+..-.t.-:..I:..:-::.r..~..Irm~ • ...
.

II" u.U' ...

,11

II

~Fi~;-~rt-r;-~rt-r;-~rt~

3+-~-r;-~rt-r;-~rt-r;-~~~

.

2i:i;i~~~~~~·t·~f.~·t·~. t.~·t·~. t.~·t·j. ~. ~·t.~·~. ~·~~"j
.-

•

1111

I'"

11'111"

, .. " . . . . . . . . . . . . . . . .

II

<"
.s

~II'

ttd ,-~

..

-80

I-

z

-90

w

ct -100
ct

'" "'11....... .

• 2 .f-I~-t-+-~~~\lWIJIU(o

-150

-160

....

"

1_'" ,,,
,o-

I,
00'

~

-140

,"""",,,.,\,•...1.1:.:
...:*.:::1
.. ""'
...:-1-.,-/,

..

~~

rn -120
iii -1~

«

·~6~0~.~4O~~-~20~~0-L~2~0-L~4~0~6~0~~80~~10~0~1~2~0

111""

...

•

u.II' II

".

~

:J -110

tl

~~.,Qft~~~~~~~~~~~-i-i-i-i

1..1l~

'r

"~I

",
",

"

.L.;..L-I~-L...1-.L.JL-I....1.-L.....1-.L.JL-I....1.-L.....1-~

-60 -40 -20

0

20

40

60

80

100 120

TEMPERATURE (oC)

TEMPERATURE (oC)

OPEN LOOP GAIN vs. TEMPERATURE
6 Typical Units From 3 Lots @ Vs = ±15V

OFFSET CURRENT VS. TEMPERATURE
5 Typical Units From 3 Lots @ Vs = ±15V

:>

>-C
..J

0

;:;:

22
21
20
l."oI
19
18
17
16
"" ,
15
14
'
13
.'lII!
12
'F ,
11
10
1,1;
9
8
7
6
-60 -40 -20

""

..

., . ... . ,
• 11111

""" I,

'U'II

.. II, I,

•

"I>r

'"

..

-~~~-L~~~-L~~~~~~-L~

-60 -40 -20

0

20

40

60

80

HIO 120

TEMPERATURE (oC)

OUTPUT VOLTAGE SWING

OUTPUT CURRENT VS. SUPPLY VOLTAGE

<"
E
:t!

50 ,.--,--.---,---,,-....---r-.--.-,.--,---,

,

40 +--t-+--t-+--t-+--t-+--t.---=.....£::.t

:>
~

C!l

~ +--+--+--+--+-+-......"......oq:l--"'~--I--I

~

20+--+-+-~~~£F~~;--4-+--t--i

~

10+~~. .~~+--t-+--t-+--t-+--4-~

rn
w

~

O+--t--~__~-t--+--t--~__~-t--+-~

«

~~..,~~t--t-+--t-+--t-+--+~
""" I",•• ,

~

z

"'

~
(,)

1--"'--

,.,.~

-10

~ -20 +--+-+--+....;.::p. ''''''
..::-f-+--4-;--4-~

n..

I- - ~ +-~I--t--+:J

o

I'••••••••••••

__~-+-~--=F''''.'''''.;:,.. I--+---I
"'".......

_4OL--L_L--L~~~~_~~_L--L~

4

6

8

10
12
SUPPLY VOLTAGE (± V)

0
20 40 60
TEMPERATURE (oC)

C!l

z
§:
C!l

~

14
12 _RL= 2kn
10
8
4
i--""
2
0
-2 ~
-4

!U-..

"'...

I-6
:J
D-8
l:J -10

0

14

.......

,.,.
~

..... "

.... "

''r,;,;;.

-12
4

3-274

"

100 120

vs. SUPPLY VOLTAGE

,.,. ,.,.

6

80

6

8
10
12
SUPPLY VOLTAGE (± V)

14

HA-2529
Typical Performance Curves

(Continued)

SUPPLY CURRENT vs. SUPPLY VOLTAGE
Over Full Temperature

<"
oS
!z

~

5.2
5.41=E~~E~=i::j:::J:~§t;1;;]+
125° C
5.0
I
......
+ 2S0C

1:~
t::i'~""~"~:''':~;;;;'+';;;''';;;''f';;:''';;:''f''=''=''~=t:=t=:t:~- 55° C
4.4 +

ti.~·l;r~=E~=E~=El=El~

4.2

B 3.8
'./.,...-+_+--+_+--+_+---+_+---+--1
3.6 +H
~.;oL
~3.4"t,tI:=t=::j:=t=::j:=I=:t~I=:t:::jI=~

a.. 3.2

'-+-+---+-+---1--1--1--1--1---11--1

3.0 -ji''-l'

'" 2.8 ~:t=t=::j:=t=:t=I=:t=I=:t:::jI=~

2.6 .,
2.4 .I--'---''----L.......1._'--'---''----L.......1._'-...J
12
14
6
8
10
4
SUPPLY VOLTAGE (± V)

+t. ~ bJ!L L~Jp' ~AIJ

........I..!U.....

80

unulu,,1I1

a:: 4.0

~

FREQUENCY RESPONSE AT VARIOUS GAINS
100

iD SO

il~vLl:0 R' "
'"

GU

"C

i" 40
~

jH}s~l~ lv~ \00

20

\

""

r:.-

....

0-

o

g

II(j

0
UnUr, ,

......

Z

~

"

o

'" ""

IUU.

UII III

II

,

.

OPEN LOOP PHASE

""-

I

1111
lK

100

:

-180 0

10K
lOOK
1M
FREQUENCY (Hz)

10M

100M

...J



~

15

~

10

0-

I I I I D"1,
III

1-0..

vstp~~J lI'toJ

,

~

1.1

G;

1.0

BANDWIDT~~

~

~

0.8

0.7

'"

""" ....

.•.•. ~

~

::! 0.6

§il

1M

10M

FREQUENCY (Hz)

3-275

........

V

i'-NEGATlVE,_
S~Ef RATE f- f-

"'POSITIVE

0.5
0.4

o

....

I....: r.::i:i

~"

S,LEj Rtl

a:

lOOK

10K

VS! 15V, RL ~ 2K,
CL ~ 50pF. T ~ + 25°C

+1 0.9

\

5

10K

100
lK
FREQUENCY (Hz)

1.2

V
5J
SUPPLY - '"
I

o
0-

0.1
lOOK

NORMAUZED A.C. PARAMETERS vs. SUPPLY VOLTAGE

VSUPPLY - ± 20V

30

!Il

0.5 ~
:>

~

10

35

a:
a:

:>

~

Cl
Z

~
~
.e:

10 Z

I"ilj
~

o

~<

INPUT NOISE CHARACTERISTICS
_1000

5

7

9
11
13
15
17
SUPPLY VOLTAGE (± V)

19 20

~

HA-2529
Typical Applications
FREQUENCY RESPONSE FOR
INVERTING UNITY GAIN CIRCUIT

10~

INo-

.A12~

.
2K

500PF~

f~

15

OUT

10

GAIN

iii' 5
:!!. -0
z

«Cl

.,\

-5
-10

PHisE
I II

-15

II
II

10K
NOTE: • Compensation Circuit for AV = -1
• Slow Rala '" 120Vl~s
• Bandwidth:::: 10MHz

• Sellling Time (0.1 '!O) '" 500ns
• Capacitance at pin 8 must be minimized for
maximum bandwidth.
• Tested and functional with supply voltages from
±4V to ±15V.

Die Characteristics
Transistor Count ...............................•... 40
Die Dimensions ...... _...... 1660Jlm x 1300Jlm x 485J1m
(65 mils x 51 mils x 19 mils)
Substrate Potential .................................

v-

Process .................................... Bipolar-DI
Thermal Constants (OC/W) .............

Sja

Sjc

HA2-Metal Can (-2, -5, -7) .•.........

206

56

HA2-Metal Can (-8, /883) ............

168

52

HA3-Plastic Mini-DIP (-5) ............

90

39

HA4-Ceramic LCC V883) ............

99

37

HA7-Ceramic Mini-DIP (-8, /883) .....

140

65

HA7-Ceramic Mini-DIP (-2, -5, -7) ....

204

112

3-276

lOOK
1M
FREQUENCY (Hz)

00

\

"

10M

-450
-900

en
w
w

a:

Cl

w

e.

~ 135° ~
-180 0

f

HA-2539

mHARRIS

Very High Slew Rate Wide band
Operational Amplifier

August 1991

Features

Applications

• Very High Slew Rate ••••••••••••••••••.•••• 600V/I's

0

Pulse and Video Amplifiers

• Open Loop Gain ............................ 15kVIV

0

Wideband Amplifiers

• Wide Gain-Bandwidth (AV ~ 10) ••.•••••••• 600MHz

• High Speed Sample-Hold Circuits

• Power Bandwidth .••••••••••••••••••••••••• 9.5MHz

• RF Oscillators

• Low Offset Voltage ••••••••••.••••••••••••••••• 8mV
• Input Voltage Noise •••••••••••••••••••••• 6nV/yfHZ
• Output Voltage Swing ••••••••••••••.••••.•••• ±10V
• Monolithic Bipolar Dielectric Isolation Construction

Description

...I

The Harris HA-2539 represents the ultimate in high slew
rate, wide band, monolithic operational amplifiers. It has
been designed and constructed with the Harris High
Frequency Bipolar Dielectric Isolation process and features
dynamic parameters never before available from a truly
differential device.
With a 600VII's slew rate and a 600MHz gain bandwidth
product, the HA-2539 is ideally suited for use in video and
RF amplifier designs, in closed loop gains of 10 or greater.
Full ±10V swing coupled with outstanding A.C. parameters
and complemented by high open loop gain makes the
devices useful in high speed data acquisition systems.

Pinout

The HA-2539 is available in 14 pin ceramic and plastic DIP.
The HA-2539-2 operates over -550 C to +125 0 C
temperature range while the HA-2539-5 operates over the
OoC to + 750 C range. Additionally, SOIC packaging is available in -5 and -9 temperature grades.
For further design assistance please refer to Application
Note 541 (Using The HA-2539 Very High Slew Rate
Wideband Operational Amplifiers) and Application Note
556 (Thermal Safe-Operating-Areas For High Current
Operational Amplifiers).
For military grade product information, the HA-2539/883
data sheet is available upon request.

Schematic

HA1-2539/2539C (CERAMIC DIP)
HA3-2539/2539C (PLASTIC DIP)
HA9P2539/2539C (SOIC)
TOP VIEW

+IN

-IN

NC

NC

-V

NC

NC

NC

NC

+V

NC

NC

NC

OUTPUT

R22

+

INPUT

OP23

• INPUT

Z1

QOZ1
QOZ2

(N.C.) No Connection pins may be tied to a
ground plane for belter isolation and heat
dissipation.
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

3-277

File Number

2896

->-

~~t.1

........ ~

"""

"'~

~;; 1.0

/

B~NOW10TH

"'

w+

SLEW RATE

-....;

~~

~ffi .9

"'"
"''''
~~

~

'"

.8

.1
.6

200

400

600

800

lK

-80

1.2K

-40

RESISTANCE (Ohms)

+40
+80
TEMPERATURE (DC)

+120

+1&0

POWER SUPPLY CURRENT vs.
TEMPERATURE AND SUPPLY VOLTAGE

SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES

8

/'

10mV

, ./

./
/

10mV

./

4

lmV-

~lmv"-

I

I

0

VSUPPLY - ±15V

6

VSUPPL yo ± 5V?

2

""

40

80

120
SETTLING TIME (ns)

160

200

0

240

-80

3-281

-40

+40
+80
TEMPERATURE (DC)

+120

+160

HA-2539
Applications
STABILIZATION USING ZIN

FREQUENCY COMPENSATION
BY OVERDAMPING
=5

REDUCING DC ERRORS

DtFFERENTtAL GAtN ERROR (3%)
HA-2539 20dB VtDEO GAtN BLOCK

COMPOSITE AMPLIFIER

RS1K.o.

R410K.o.

INPUT

l

R1

10K.o.

C2

O.039Ji.F

3900pF

OUTPUT

l
NOTE: No connect pins (NC) on the HA-2539 should be tied to a ground
plane.
Refer to Figure 4 in Application Note 541 for detailed Application
suggestions.

Die Characteristics
Transistor Count .•.•..•••••.•..••.•••...•....••.....•••..• 30
Die Dimensions •..••..••..••...•...•••••.... 75 x 61 x 19 mils
(191 O~m x 1550~m x 483~m)
Substrate Potential (Power Up)' ••.•...••••.•.••.••.••...... VProcess ••..•••••.•.•.•••••.••..•.. High Frequency Bipolar-DI
Passivation .•••••.•.••••.••..•...•..••......•..•.•.... Nitride
9ja
9jc
Thermal Constants (OC/W)
HA1-2539/2539C Ceramic DIP
104
48
HA3-2539/2539C Plastic DIP
HA9P2539/2S39C SOIC

SetAv =

95

46

119·

36

"The substrate may be left floating (Insulating Die Mount) or It may be
mounted on conductor at V- potential.

3-282

2l~
RI

=-3

HA-2540

mHARRIS

Wide band, Fast Settling
Operational Amplifier

August 1991

Features
o

Description

Very High Slew Rate ••...•••..•••..••••.••. 400V /J.lS

• Fast Settling Time ••••••.•••••••••.•.•••••••• 140ns
• Wide Gain-Bandwidth (AV ~ 10) ••••••••••• 400MHz
• Power Bandwidth ••••••••••••.••••••••••••••• 6MHz
o Low Offset Voltage •••••••••••.•••••.••••••••.• 8mV
o Input Voltage Noise ••••••••••••••••.••••• 6nV/y'Hi

• Output Voltage Swing .•••••••••••••.••••••••• ±1 OV
• Monolithic Bipolar Construction

Applications
• Pulse and Video Amplifiers

The Harris HA-2540 is a wideband, very high slew rate,
monolithic operational amplifier featuring superior speed
and bandwidth characteristics. Bipolar construction
coupled with dielectric isolation allows this truly differential
device to deliver outstanding performance in circuits where
closed loop gain Is 10 or greater. Additionally, the HA-2540
has a drive capability of ±10V into a 1Kn load. Other
desirable characteristics include low input voltage noise,
low offset voltage, and fast settling time.
A 400V/J.ls slew rate ensures high performance in video and
pulse amplification circuits, while the 400MHz galn-bandwidth-product Is ideally suited for wideband signal
amplification. A settling time of 140ns also makes the
HA-2540 an excellent selection for high speed Data
Acquisition Systems.
The HA-2540-2 Is specified over the -55 0C to +1250C
range while the HA-2540-5 is specified from OOC to
+75 0C. The HA-2540 Is available In the 14 pin Ceramic
and Plastic DIP packages. A SOIC packaging option is also
available in -5 and -9 temperature grades.

• Wideband Amplifiers
o High Speed Sample-Hold Circuits
o Fast, Precise CIA Converters

Refer to Application Note 541 and ApplIcation Note 556 for
more information on High Speed Op-Amp applications.
MIL-STD-883 data sheet Is available on request.

Pinout

Schematic

HA1-2540/2540C (CERAMIC DIP)
HA3-2540/2540C (PLASTIC DIP)
HA9P2540/2540C (SOIC)
TOP VIEW

NC

NC

NC

NC

NC

NC

-IN

V+

R ••

+ INPUT

+IN

OUTPUT

V-

NC

NC

NC

• INPUT

NC No Connection. These pins may be tied to a
ground plane for added isolation and heat
dissipation

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @) Harris Corporation 1991

3-283

File Number

2897

-'


e,

,

BIAS CURRENT
3

2

,

2
0
-80

40

.

.

120

80

"0

0

tlBD

TEMPERATURE=DC

--'
oCt en
za:

OW
BROADBAND NOISE (O.lHZ to 1 MHz)
Vertical Scale: 10mV/Div.
Horizontal Scale: 50ms/Div.

~~

COMMON MODE REJECTION RATIO vs. FREQUENCY

V!.15V RL

=

a: c..

w:;;:
~oCt

lK

120

1--+--++I-tlirlt---1-++++-IH-I-++++HlfH--f-'H+I-ItH

100

1--+--++I-tlirlt---1-++++-IH-I-++++HlfH---1-H+I-ItH

80

r--t-t,,~tr-t-++++~t--r-rtt++Ht-t-ri,,*H

-.
IK

lOOK

10K

1M

10M

FREQUENCY - Hz

POWER SUPPLY REJECTION RATIO vs. FREQUENCY

OPEN LOOP GAIN/PHASE vs. FREQUENCY HA-2540

100

0'

80
45'

100

GAIN

60
80

SO'

PHA~EI

40
60

1350

~SUPPLV

40

NEGATIVE SUPPLY

-....;

20

.. .

1800

\
-10

20

225 0
100

'K

'OK

lOOK

,M

10M

FREQUENCY -Hz

3-287

"

10K

lOOK

1M

FREQUENCY - Hz

10M

100M

HA-2540
Applications
WIDE BAND SIGNAL SPLITTER

With one HA-2540 and two low capacitance switching
diodes, signals exceeding 10MHz can be seperated. This

ru

circuit is most useful for full wave rectification, AM detectors
or sync generation.

rvL

2K
200

-=

rv

OFFSET

ADJUST

'"

-=

\JV

2K
':'

BOOTSTRAPPING FOR MORE OUTPUT CURRENT AND VOLTAGE SWING

R1*

C1*

~

J+----. 4K

+V

1K
R2*
4K
SIGNAL
OUT

1K
R3*
4K
R4*
4K

T
~

NOTES:

1. Used for experimental purposes. Cf
2. C,

is optional (0.001 pF _

0.Q1 pF

~

3pF.

ceramic)

3. RS Is optional and can be utilized to reduce input signal amplitude and/or balance Input conditions. R5

= 500n to 1kn.

Refer to Application Note 541 For Further Applications Information.

Die Characteristics
Transistor Count ................................... 30
Die Dimensions ....................... 75 x 61 x 19 mils
(1910llm x 1550llm x 4831lm)
Substrate Potential (Power Up)* ...................... V-

Thermal Constants (OC/W)
HA-2540/2540C Ceramic DIP
HA-2540/2540C Plastic DIP

Process .......•............. High Frequency Bipolar-DI
Passivaton .................................... Nitride

*The substrate may be left floating (Insulating Die Mount) or It may be
mounted on a conductor at v- potential. V- potential.

HA-2540/2540C SOIC

3-288

Sja
104
95
119

Sjc

48
46
36

mJ HARRIS

HA-2541
Wideband, Fast Settling, Unity Gain Stable,
Operational Amplifier

August 1991

Applications

Features
o Unity Gain Bandwidth •••••••••••••••••••••• 40MHz

• Pulse and Video Amplifiers

• High Slew Rate •••••••••••••••••••••••••••• 250V/flS

• Wideband Amplifiers

• Low Offset Voltage •••••••••••••••••••••••••• O.SmV

• High Speed Sample-Hold Circuits

• Fast Settling Time (0.1%) ••••••••••••••••••••• 90ns

• Fast, Precise D/A Converters

• Power Bandwidth ••••••.•••••••••.•••••.••••. 4MHz

• High Speed AID Input Buffer

• Output Voltage Swing (Min) •••••••••••••.••••. ±10V
o Unity Gain Stability
o Monolithic Bipolar Dielectric Isolation Construction
....I

Description
The HA-2541 is the first unity gain stable monolithic
operational amplifier to achieve 40MHz unity gain bandwidth. A major addition to the Harris series of high speed,
wideband op amps, the HA-2541 is designed for video and
pulse applications requiring stable amplifier response at
low closed loop gains.
The uniqueness of the HA-2541 is that its slew rate and
bandwidth characteristics are specified at unity gain.
Historically, high slew rate, wide bandwidth and unity gain
stability have been incompatible features for a monolithic
operational amplifier. But features such as 250VlflS slew
rate and 40MHz unity gain bandwidth clearly show that this
is not the case for the HA-2541. These features, along with

Pinouts

90ns settling time to 0.1 %, make this product an excellent
choice for high speed data acquisition systems.
Packaged in a metal can (TO-S) or 14 pin ceramic DIP, the
HA-2541 Is pin compatible with the HA-2540 and
HA-5190 op amps. The HA-2541-2 is specified over the
temperature range of -55 0 C to +125 0 C. The HA-2541-5 is
specified over the temperature range of OOC to + 75 0 C. For
the military grade product, refer to the HA-2541 military
data sheet.
For further application suggestions on the HA-2541, please
refer to Applicaton Note 550 (Using the HA-2541), and
Application Note 556 (Thermal Safe-Operating-Areas For
Current Operational
Amplifiers).
Also see
High
'Applications' in this data sheet.
BALANCE

HA1-2541 CERAMIC DIP

r1-'~------------~---r---r~~+-+-T-~'v

TOP VIEW

HA2-2541 METAL CAN (TO-8)

TOP VIEW
v+
NC
NC
BAL
BAL

·IN
+IN

OUT

v·
NC
NC
NC

VCASE = V-

-v

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-289

File Number

2898

 -0.5
~

-- - - r-..

.::;:: '"

.

i
•

1

!
i

1
lOOK

3-292

"...
2-

~
~

~

16
15

"-

l"\

.... ,
~

(".

14
13
12
11
10
g

.......

.

a
1
6
5
4
-60

.

-40

h

.

-20

o

-

~"'"

-.

1- •

20
40
60
TEMPERATURE ('C)

aD

100

-

120

HA-2541
Typical Performance Curves (Continued)
OUTPUT CURRENT VS. SUPPLY VOLTAGE
At Various Temperatures

OUTPUT VOLTAGE SWING VS. SUPPLY VOLTAGE
At Various Temperatures
12
10

f--

"

+25'~-(VOUT,\

1_-- ~
;;; ~--

~
>

1

-550C +VOUT
+VOUT

f--

!;

I

__;:;.

-

1,- -;:::. r.:::;

-::; f';:::.

40

F.:::

3D

.~-:~

Y-

-4

-55'C_4,;; ~~..."
-VOUT +25'C
-8 Ir-VOUT +125'C
-10
I
I
I-VO~T
-6

~

I

I

.;;::

9

.s

20

!;

::

10

-20

~

I

3

250C

-i......

0
-PSRR
:; 60

~

~~

-+-----1

16r----t-___
--~~~~===F====~~~~~

~ 15V"'

~ 14~--+--4_--~--+--+_--4--~

""I'--.

40

o

~ 13~--+--4_--~--+--+_--+--~

1".

20

12 ~--_I__----~--_I__ ±AYOL@T=-550C

-+-----/

11~-_+--4=_._ ~~-~-=--=F-=-=--=-=-+_--------+_-___I

10~-~.~~~~-~~-~4_~---~--~-_+--+_-___I
~~

#~

8L-__
lK

100

10K
lOOK
FREnUENCY 1Hz)

1M

10M

____

~

__- L__

~

____~__~

10
12
SUPPLY YOLTAGE 1+I-Y)

=

14

=

II~U

-

-

. .

-- ----

10

100

15

..... 1
j

- -. ./.

-

I

r:~
,

odB
PHASE
i'1 800

~

I.,..

-5
-10

135 0

•

IV

RS~
:

~"n

~T

lK

10K
1001:
1M
10M
100M
FREQUENCY 1Hz)
OPENLOOP _ _ Ay=-100 - . _ Ay=-IO .-~ AY=-I·-----

~

,

10K
lOOK
1M
10M
FREQUENCY 1Hz)
RS=0>2 _ _ RS=5kU _._ RS=50kU

vs. TEMPERATURE

CLOSE LOOP FREQUENCY RESPONSE

PHASE
lDEGREES)
YCC = +1-8Y
AV=+1
RL =2kU
CL"lopF

"""

I i~ ~ ~;250C

GAIN

I--

I"

ITA = +25 0C
i T A=-55 0C, " "

~ 00

l..::

I~

i"""'oloo.

-3
-6
PHASE

TA = +125 O C."
TA=+25OC

W

T~li~~~c-m
111111
1M

.

10M
FREQUENCY 1Hz)

3-294

"

-450

-90 0
-1350

~
100M

PHASE

IDEGREES)
-45
-90
-135

~

-180

'7

lK

GAIN
IdB)

lOOK

>...

.".

l!Jon

+ 10
Vs ~ :t15V
T~ +Z50C
AV

00

-9

~

90 0
450

,~HASE

\

P~A~EIi
VIN

\ II.., •

"

TTl

10

r-.

1\

Vs= ±15Y
RL=lkU
CL"lOpF
T= +Z50C

III
~Arr tt'<

20

",/

.....

60

20

~

GAIN
IdB)

80

40

__

SMALL SIGNAL BANDWIDTH vs. SOURCE RESISTANCE
Vs ±15V, RL 1kO

GAIN AND PHASE FREQUENCY RESPONSE
Vs = ±15V, RL = 1k, CL ~ 10pF, TA = +250 C
GAIN
IdO)
100

~

8

-180 0

-2250

100M
._~

HA-2541
Applications

(Also See Application Note 550)

50U

"

lOAOI6SI1.6000pF
OR

125n,6000pF

APPLICATION 1. DRIVING POWER TRANSISTORS TO GAIN ADDITIONAL CURRENT BOOSTING

APPLICATION 1
High power amplifiers and buffers are in use In a wide
variety of applications. Many times the "high power"
capability is needed to drive large capacitive loads as well
as low value resistive loads. In both cases the final driver
stage is usually a power transistor of some type, but
because of their inherently low gain, several stages of
pre-drivers are often required. The HA-2541, with its 10mA
output rating, is powerful enough to drive a power transistor
without additional stages of current amplification. This

capability is well demonstrated with the high power buffer
circuit in Application 1.

-'
<(I)

za:

OW

The HA-2541 acts as the pre-driver to the output power
transistor. Together, they form a unity gain buffer with the
ability to drive three 50 ohm coaxial cables in parallel, each
with a capacitance of 2000pF. The total combined load is
16.6 ohms and 6000pF capacitance.

APPLICATION 2
Video
One of the primary uses of the HA-2541 is in the area of
video applications. These applications include signal
construction, synchronization addition and removal, as well
as signal modification. A wide bandwidth device such as the
HA-2541 is well suited for use in this class of amplifier.
This, however, is a more involved group of applications than
ordinary amplifier applications since video signals contain
precise DC levels which must be retained.
The addition of a clamping circuit restores D.C. levels at the
output of an amplifier stage. The circuit shown in Application 2 utilizes the HA-5320 sample and hold amplifier
as the D.C. clamp. Also shown is a 3.57MHz trap in series,
which will block the color burst portion of the video signal
and allow the D.C. level to be amplified and restored.

Die Characteristics
Transistor Count .......................................... 41
Die Dimensions ............................. 89" 79 x 19 mils
(2250~m x 1990~m x 485~m)
Substrate Potential (Power Up» ............................ VProcess .............................. High Frequency Bipolar
Dielectric Isolation
Passivation ............................................ Silox
Thermal Constants (OC/W)
aja
ajc
Ceramic DIP
91
35
Metal Can
66
30
*The substrate may be left floating (lnsulaling Die Mount) or it may be
mounted on a conductor at V- potential.

3-295

HAliUO

7511

APPLICATION 2. VIDEO D.C. RESTORER

~§

a:

D..

w::;;;

g;<

HA-2542

;JIHARRIS

Wideband, High Slew Rate, High Output
Current Operational Amplifier

August 1991

Features

Applications

• Stable at Gains of 2 or Greater

• Pulse and Video Amplifiers

• Gain Bandwidth •••••••••••••••••••••••••••• 70MHz

• Wideband Amplifiers

• High Slew Rate (Min.) •••••••••••••••••••••• 300V/lls

• Coaxial Cable Drivers

• High Output Current (Min.) •••••••••••••••••• 100mA

• Fast Sample-Hold Circuits

• Power Bandwidth (Typ.) •••••••••••••••••••• 5.5MHz

• High Frequency Signal Conditioning Circuits

o Output Voltage Swing (Min.) •••••••••••••••••• ±10V

• Monolithic Bipolar Dielectric Isolation Construction

Description
The HA-2542 is a wideband, high slew rate, monolithic
operational amplifier featuring an outstanding combination
of speed, bandwidth, and output drive capability.
Utilizing the advantages of the Harris D. I. technology this
amplifier offers 350V/liS slew rate, 70MHz gain bandwidth,
and ±100mA output current. Application of this device Is
further enhanced through stable operation down to closed
loop gains of 2.

frequency signal conditioning circuits and pulse video
amplifiers. Other applications utilizing the HA-2542
advantages Include wldeband amplifiers and fast samplehold circuits.

For additional flexibility, offset null and frequency
compensation controls are Included in the HA-2542 pinout.

The HA-2542 is available in ceramic or plastic 14 lead DIP
packages, or a 12 lead metal can (TO-a) which is pin
compatible with the HA-2541, HA-5190, LH0032 and
HOS-050C. The HA-2542-2 is specified over the -550C to
+1250C temperature range and Is also offered as a military
part. The HA-2542-5 Is specified over the commercial
temperature range of OOC to +750 C.

The capabilities of the HA-2542 are Ideally suited for high
speed coaxial cable driver circuits where low gain and high
output drive requirements are necessary. With 5.5MHz full
power bandwidth, this amplifier is most suitable for high

For more Information on the HA-2542, please refer to
Application Note 552 (Using The HA-2542), or Application
Note 556 (Thermal Safe-Operating-Areas For High Current
Op Amps).

Pinouts

Schematic

HA1-2542 (CERAMIC DIP), HA3-2542 (PLASTIC DIP)
TOP VIEW

HA2-2542 (TO-8 METAL CAN)
TOP VIEW

+IN

CAUTION: These devices are sensitive to electrostatic discharge. Proper
Copyright @ Harris Corporation 1991

I.e. handling procedures should be fol/owed.

3-296

File Number

2899

Specifications HA-2542
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage between V+ and V- Terminals •.••.•.•••.••••.•••••• 35V
Differential Input Voltage ....•....••••••••••.•.••...••.•.•• ±6V
Output Current ••..••••••••••.•.•••••.•.••••.•.• 125mA (Peak)
107mA rms (Continuous)

HA-2542-2 •....••.••.••.••••••••••••.• -55°C :S TA :S +1250 C
HA-2542-5 •••..••.••.••.•••..•..••••.•..• OOC :S TA:S +750 C
Storage Temperature Range .••..••.••..• -650C.:S TA :S +1500 C
Maximum Junction Temperature (Note 11) ••.••.••••.••. +175 0 C

Electrical Specifications VSUPPLY

~ ±15 Volts; RL ~ lkO, CL:S 10pF, Unless Otherwise Specified.

HA-2542-2
-550C 10 +125 0 C
PARAMETER

HA-2542-5
OOClo+750C

TEMP

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

-

5
8
14
15
26
45

mV
mV

-

Average Bias Current Drift
Offset Current

-

10
20

Full
Full
+25 0C

5
8
14
15
26

10
20

Average Offset Voltage Drift
Bias Current

+250 C
Full
Full
+250 C

"VloC
j1A
j1A
nNoC

INPUT CHARACTERISTICS
Offset Voltage

Full
+250 C
+250 C

Input Resistance

Input Capacitance
Common Mode Range
Input Noise Voltage (0.1 Hz to 100Hz)
Input Noise Voltage Density (fo ~ 1 kHz, Rg
Input Noise Current Density (to ~ 1 kHz, Rg

~

00)
~ 00)

-

66
1

100
1

Full
+250 C
+250 C
+25 0 C

±10

-

-

2.2

-

10
3

+250 C
Full
Full
+25 0C
+25 0 C

10k
5k

-

70

Full
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C
+25 0 C

±10
100

±11

-

5
5.5
0.1
0.2
<0.04

+25 0 C
+250 C
+250 C
+250 C
+250 C

-

-

35
50

7
9

-

±10

-

35
50

-

1

7

-

9

100
1

-

-

2.2
10
3

-

-

10k
5k

30k
20k

-

-

70
2

100

-

-

70

-

±10
100

±11

-

j1A
j1A
kO
pF
V
"Vp-p
nV/,;Hz
pN,;Hz

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)
Common-Mode Rejection Ratio (Note 4)
Minimum Stable Gain
Gain-Bandwidth-Product (Note 5)

70
2

30k
15k
100

-

-

-

-

VN
VN
dB

VN
MHz

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 3)
Output Current (Note 6)
Output Resistance
Full Power Bandwidth (Note 3 & 7)
Differential Gain (Note 2)
Differential Phase (Note 2)
Harmonic Distortion (Note 10)

4.7

-

-

-

-

5

4.7

5.5
0.1
0.2
<0.04

-

-

-

V
rnA
0
MHz
%
Degrees
%

TRANSIENT RESPONSE (Note 8)
Rise Time
Overshoot
Slew Rale
Settling Time:

10VSteptoO.l%
1OV Step to 0.01 %

300

-

4
25
350
100

-

-

-

-

300

200

-

-

30
31
79

34.5

-

-

70

4
25
350
100
200

-

ns
%

-

V/"s

-

ns
ns

POWER REQUIREMENTS
Supply Current
Power Supply Rejection Ratio (Note 9)

+250 C
Full
Full

70

3-297

30
31
79

40

-

rnA
rnA
dB

-'
«en
za:

OW

~~

w:;;;
~«

HA-2542
NOTES:
1. Absolute maximum ratings are limiting values, applied individually.
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions Is not necessarily Implied.

2. Differential gain and phase are measured at 5MHz with a 1 Volt
differential input voltage.

3. RL = lkO, Vo = ±10V
4. VCM = ±10V
5. AVCL = 100
6. RL = 500, Vo = ±5V
7. Full Power Bandwidth guaranteed based on slew rate measurement using
FP8W = Slew Rate
2nVpEAK

8. Refer to Test Circuits section of this data sheet.
9. VSUPPLY = ±5VDC to ±15VDC
10. VIN = tVRMS; I = 10kHz; AV = 10.
11. This value assumes a no load condition: Maximum power dissipation
with load conditions must be designed to maintain the maximum junetTon
temperature below + 1750C. 8y using Application Note 556 on Sale
Operating Area equations, along with the packaging thermal resistances
listed in the Die Characteristics section. proper load conditions can be
determined. Heat sinking Is recommended above +75 0 C with suggested
models:
14 Lead Ceramic DIP:
Thermalloy 1/6007 or AAVlD 1/56028 (Bsa = 160CIW).
12 Lead Metal Can (TO-8):
Thermalloy 1/2240A (Bsa = 270CIW) or 1/22688 (Bsa = 240CIW)

Test Circuits
TEST CIRCUIT

IN

>-......-0

OUT
Vs = ±15V
AV=+2
CL S,10pF

LARGE SIGNAL RESPONSE
Vertical Scale (Volts: VIN 2.0V/Div., VOlJT 5.0V/Div.)
Horizontal Scale (Time: 200ns/Div.)

=

SMALL SIGNAL RESPONSE
Vertical Scale (Volts: 100mV/Dlv.)
Horizontal Scale (Time: 50ns/Div.)

=

TIME DELAY
Vertical Scale (Volts: 100mV/Div.)
Horizontal Scale (Time: 10ns/l:iv.)

Vs = ±15V, RL = lkO
T = +250C
Propagation delay variance is negligible
over full temperature range.

3-298

HA-2542
Test Circuits (Continued)
SETTLING TIME TEST CIRCUIT

SUGGESTED OFFSET VOLTAGE ADJUSTMENT

SETTUNG
POINT

+V

VOUT

• AV ~-2
• Feedback and summing resistors must be matched (0.1%)

• HP50a2-2810 clipping diodes recommended
• Tektronix P6201 FET probe used at seWing point

Suggested compensation scheme 5-20pF

• For 0.01 % settliing time, heal sinking is suggested to reduce thermal
effects and an analog ground plane with supply decoupling is suggested

Typical range is ±20mV with Rr

Tested Offset Adjustment Range is I Vas +1 mV Iminimum referred to output.

= 5kO.

OW

~§

Typical Performance Curves

a: "W:E

INPUT NOISE VOLTAGE AND INPUT NOISE CURRENT
vs. FREQUENCY
100 0

~«

OFFSET VOLTAGE DRIFT WITH TEMPERATURE
Of Six Representative Units, Vs = ±12V

1DOD

o~

!

1

_-_-.+---I--I--t--+--i

4 -h=±:-._1-.-_-1.f-_-.•-1

~ 0 ~~- :::::-::;:;,-=:-:+-*;;;;;~;;::t:=t::::j-j

....

-- - -.,+-- -- -- ---- -

~-2+--r--+--r-+--r--+----l-r~~~-~---~.~

INPUT NOISE VOLTAGE

0

.....

INPUT NOISE CURRENT

III

~

1111
1K

1DO

10

-

i-

10K

1

~-4+--+--I/--I--t-+-+-+--+--H

-6EEeft~
-8 ' ...

1

-10

1BOK

4

4

W

~

00

~

00

m

~

FREQUENC'f(Hz)

TEMPERATURE IOC)

BIAS CURRENT DRIFT WITH TEMPERATURE
Of Six Representative Units, Vs = ±12V

INPUT RESISTANCE vs. FREQUENCY
29
TA +250C
VS-±15V

lOOK

ew

10K

.'"

In

1O00

u

ffi
a:
~
~

25

.3-

100

...

~~
~

~

...

' ....

27

<

~
:z:

i:ii
a:

.

~

~

iii

900n

,,

. ,...... "

2J
21
19

"" "..... ~".... ...., ,
......

a:

B

-

v-

17
15
13

~

"- ~

~.

~

~~

loon

7
1M

10M
FREUUENCV (Hz)

-60

100M

. r--..

"0

11

10
lOOK

.....
«CJ)

za:

to minimize ground loop errors.

-40

-20

20

~......
~

40

~ tr

0

0

-."

60

TEMPERATURE (oC)

3-299

-

-:~

"'-;;.- ........
80

100

120

HA-2542
Typical Performance Curves

(Continued)

BIAS CURRENT VS. POWER SUPPLY
Six Units At Various Supplies At +250 C
18
17

-

//

16
15

<1:
2-

!f

14

I-

::;
'"

!,
!I ,

13

.'"
'"

12

'",

'il

11

;;;

/1

10

.,' ---. --~-.:.

;'

PSRR AND CMRR VB. TEMPERATURE
VS= ±15V
120

-

--

.-

-

.-.----. ---. --- ---- ---

110

.

CMRR

~-

100

:s
90

""-

l/
'/

.....- ---- .....- ..--:JS~'!.-- ---- ---- --- ---- -

80

70
9
11
SUPPLY VOLTAGE (+I-V')

13

15

-40

-60

.",..

--- --- --- --- ...-- --- --12 0

E

'I,

" 26

~

+PSRR

I-

I....

--

.. 60

~f'It;

1',

40

.~

+250C 1

18

120

f-

RL =2kf!
TA =+2S0C

-PSRR

'" 20
B

~

100

Js~lfI5~

I
I

80

,

'" 22

80

,~'!!.

100

24 r--550C~I/'

~

60

PSRR AND CMRR VS. FREQUENCY

I

<1: 28

~
I-

40

TEMPERATURE (OC)

SUPPLY CURRENT vs. SUPPLY VOLTAGE
At Various Temperatures
30

20

-20

20

16
14 r---Jf+1250C
12
8
10
12
SUPPLY VOLTAGE (+I-V)

4

14

SLEW RATE VS. TEMPERATURE
At Various Supply Voltages With RLoad =
500

400

~ 300

~

200

--

AV=12

RL = lOon

55

I

50

>

45

±107'

0
-50

J

-25

±5V

-

40

-

'"

±10V
±5V

75

100

10M

125

3-300

10

~

....... ~r-

.- .
~

,. 10-

VS=±8~,

\ / ~vs=±'2vi ~~ ;...Vs =\ ±7V r,10-'

// ,.

25

15

.

/~ f-P"

.~V'

20

I

"I.-'V

VS=±15V

~ 30

±15V

Av=10
25
50
TEMPERATURE oC

~"

....

AV-l0
AV=10

I

I..... •

g~ 35

AV 2

1M

OPEN LOOP GAIN VS. TEMPERATURE
At Various Supply Voltages

loon

1.

100

10K
lOOK
FREQUENCY 1Hz)

±15V_

AV=12

'-

lK

100

;.!~,.

r"

~'

/:'

.1

fo"

~~ 1''''
-60

-40

-20

20
40
80
TEMPERATURE (OC)

80

100

IZO

HA-2542
Typical Performance Curves

(Continued)

OUTPUT VOLTAGE SWING vs. SUPPLY VOLTAGE
At Various Temperatures
12.0
10.0
8.0

I

+1250C
+Vour"

125 C
0

. .'"

.....

r-- - 550C -+Vour
~
6.0 I-+vour _
::.;1ii~'
4.0

~

'"

"
~

.

2.0
0.0
-2.0
> -4.0 ~
1; -6.0
~~
1=
-550C /
7- ~-8.0
/
-10.0
-Vour '+125 0C
-12.0
I jvour

.

.::::.

~ f"""

NORMALIZED AC PARAMETERS vs.
COMPENSATION CAPACITANCE
1.4

~

'"

"

... -

"'"

ff"250C~J

--

----~MARGIN

1

w

'":;

-- -

o~

."-~

--

8

."i"$i;,;~

~

-14.0
9

11

~ I:.z..
--::

13

1

SLEW RATE

~

'-8ANrIDTH~1:::::--..

15

SUPPLY VOLrAGE (+I-VI

~~

5

"

"

10
COMPENSATION CAPACITANCE - pF

25

......

-<>

+Z50C

soon
+1250C-

soon

III
III

10M

f-

~

i

-I-

-5 50C

\~

~

\

\~

PHASE

DO

"'5 0
_90 0

-1350

I),

-180 0

~
100M

HA-2542
Die Characteristics
Transistor Count ..... . . . . . . . . . . . . . . . . . . . . . . .. 43
Die Dimensions ................ 72 x 105 x 19 mils
(1820~m x 2670~m x 485~m)
Substrate Potential* .......•................... vProcess ................ High Frequency Bipolar-DI
Passivation ............................... Nitride
Thermal Constants (OC/W)
Sja
Sjc
HA1-2542 Ceramic DIP
86.6
32.5
78.8
HA3-2542 Plastic DIP
30.6
58
HA2-2542 Metal Can
29
*Tho substrate may be laft floating (Insulating Die Mount) or it may be

mounted on a conductor at V- potential.

Typical Applications

Frequency Compensation

(Refer to Application Note 552 for Further Information)

The HA-2542 may be externally compensated with a single
capacitor to ground. This provides the user the additional
flexibility in tailoring the frequency response of the amplifier.
A guideline to the response is demonstrated on the typical
performance curve showing the normalized A.C. parameters versus compensation capacitance. It is suggested that
the user check and tailor the accurate compensation value
for each application. As shown additional phase margin is
achieved at the loss of slew rate and bandwidth.

The Harris HA-2542 is a state of the art monolithic device
which also approaches the "ALL-IN-ONE" amplifier
concept. This device features an outstanding set of AC
parameters augmented by excellent output drive capability
providing for suitable application in both high speed and
high output drive circuits.
Primarily intended to be used in balanced 50n and 750
coaxial cable systems as a driver, the HA-2542 could also
be used as a power booster in audio systems as well as a
power amp in power supply circuits. This device would also
be suitable as a small DC motor driver.
The applications shown on the following page demonstrate
the HA-2542 at gains of +100 and +2 and as a video cable
driver for small signals.

Pro to typing Guidelines
For best overall performance in any application, it is
recommended that high frequency layout techniques be
used. This should include: 1) mounting the device through a
ground plane: 2) connecting unused pins (N.C.) to the
ground plane: 3) mounting feedback components on Teflon
standoffs and or locating these components as close to the
device as possible; 4) placing power supply decoupling
capacitors from device supply pins to ground.
As a result of speed and bandwidth optimization, the
HA-2542 can's case potential, when powered-up, is equal
to the V- potential. Therefore, contact with other circuitry or
ground should be avoided.

For example, for a voltage gain of +2 (or -1) and a load of
500pF/2kO, 20pF is needed for compensation to give a
small signal bandwidth of 30MHz with 400 of phase margin.
If a full power output voltage of ±10V is needed, this same
configuration will provide a bandwidth of 5MHz and a slew
rate of 200V/~s.
If maximum bandwidth is desired and no compensation
is needed, care must be given to minimize parasitic
capacitance at the compensation pin. In some cases where
minimum gain applications are desired, bending up or
totally removing this pin may be the solution. In this case,
care must also be given to minimize load capacitance.
For wideband positive unity gain applications, the HA-2542
can also be over-compensated with capacitance greater
than 30pF to achieve bandwidths of around 25MHz. This
over-compensation will also improve capacitive load
handling or lower the noise bandwidth. This versatility along
with the ±100mA output current makes the HA-2542 an
excellent high speed driver for many power applications.

3-302

HA-2542

Typical Applications

FREQUENCY (OdS) = 44.9MHz
PHASE MARGIN (OdS) = 40 0

NONINVERTING CIRCUIT (AVCL = 100)
(dB)

IN

40

OUT

30
990.n.

20
10

00

0

1O.n.

-45 0
-90 0
-1350
-1800

NONINVERTING CIRCUIT (AVCL = 2)

AVCL = 100 PHASE AND GAIN

®

FREQUENCY (3dS) = 56MHz
PHASE (3dS) = 40 0

:z a:
a w
u:::
i= :::::;

....I

-9~~~~==:t~-«OUT

1k.n.

75.n.

1k.n.

VIDEO CASLE DRIVER PULSE RESPONSE
(1V/Div.; 100ns/Div.)

3-303

en

mHARRIS

HA-2544
Video Operational Amplifier

August 1990

Features

Applications

•
•
•
•
•
•

•
•
•
•
•
•
•

Gain Bandwidth •••••••••••••••••••••••••••• 50MHz
High Slew Rate •••••••••••••••••••••••••••• 150Vl/Js
Low Supply Current ••••••••••••••••••••••••• 10mA
Differential Gain Error ••••••••••••••••••••••• 0.030/0
Differential Phase Error •••••••••••••••• 0.03 degree
Gain Flatness at 10MHz ••••••••••••••••••••• O.12dB

Video Systems
Video Test Equipment
Radar Displays
Imaging Systems
Pulse Amplifiers
Signal Conditioning Circuits
Data Acquisition Systems

Description
The HA-2544 is a fast, unity gain stable, monolithic op amp
designed to meet the needs required for accurate
reproduction of video or high speed signals. It offers
high voltage gain (6kVN) and high phase margin
(65 degrees) while maintaining tight gain flatness over the
video bandwidth. Built from high quality Dielectric Isolation,
the HA-2544 is another addition to the Harris series of
high speed, wideband Op-Amps, and offers true video
performance combined with the versatility of an op-amp.
The primary features of the HA-2544 include 50MHz Gain
Bandwidth, 150V//Js slew rate, 0.03% differential gain
error and gain flatness of just O.12dB at 10MHz. High
performance and low power requirements are met with a
supply current of only 10mA.

Pinouts

Uses of the HA-2544 range from video test equipment,
guidance systems, radar displays and other precise
imaging systems where stringent gain and phase requirements have previously been met with costly hybrids and
discrete circuitry. The HA-2544 will also be used in nonvideo systems requiring high speed signal conditioning
SUCh as data acquisition systems, medical electronics,
specialized instrumentation and communication systems.
The HA-2544-2is guaranteed over the military temperature
range (-550C to + 1250 C); the HA-2544/2544C-5 over the
commercial range (OOC to + 75 0C) and the HA-2544!
2544C-9 over the industrial range (-400 C to +85 0C). The
HA-2544 is available in TO-99 Metal Can, SOiC, and both
Plastic and Ceramic Mini-DIP packages. Military (/883)
product and data sheets are available upon request.

Schematic

~-r--~~--Tr--~II-r~

HA9P2544/2544C (SOIC)
HA7-2544 (CERAMIC MINI-DIP)
HA3-2544/2544C (PLASTIC MINI-DIP)
TOP VIEW

BAL

NC

-IN

V+

+IN

OUT

v-

BAL

HA2-2544 (TO-99 METAL CAN)
TOP VIEW

NC

ailD

lur41

NOTE: VCASE = V-

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @) Harris Corporation 1991

3-304

File Number

2900

Specifications HA-2544
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- Terminals •••.•.•••..••.•.••••. 35V
DifferenUallnput Voltage (Note 11) •.•.••..•.•••..••.••••••. ±6V
Output Current (Peak) ••.••...•.••..••.••..•.••..•..••• ±40mA
Internal Power Dissipation •...•.••.••••••..•.....•..•• 700mW

HA-2544/2544C-5 .••.••..•.•••.•••••••••. OOC:5 TA:5 +750 C
HA-2544-9 .•••.•••••••.•.•.••...••••••• -400C :5 TA :5 +850 C
HA-2544-2 •••..•••••.•••.••.••...••.•• -550 C:5 TA:5 +125 0 C
Storage Temperature Range ..•••••.••..• -650C :5 TA ::; +150oC
Maximum Junction Temperature .•••.••••••••••.••••.•• +1750 C

Electrical SpeCifications Vs = ±15V, CL 5 10pF, RL = 1kn, Unless Otherwise Specified
HA-2S44-2/-S
PARAMETER

TEMP

MIN

+2S oC

Full

-

Full
+2So C

HA-2S44C-S

TYP

MAX

MIN

TYP

MAX

UNITS

6

15

-

15

25

mV

-

20

-

-

40

mV

-

40

mV

10

-

~VfOC

9

18

~A

INPUT CHARACTERISTICS
Offset Voltage

-2,-5

-9
Average Offset Voltage Drill (Note 9)
Bias Current

Average Bias Current Drill (Note 9)
Offset Current

Offset Current Drill
Common Mode Range

Full
+25 0 C

-

25

10

-

7

15

-

20

-

0.04

-

0.2

Full

-

-

Full

-

10

-

30

~

-

-

0.04

-

~OC

2

-

0.8

2

~

3

-

-

3

~A

-

-

10

-

nNoC

±10

±11.5

50

90

-

kO

Full

±10

±11.5

Differenliallnput Resistance

+2SoC

50

90

Differenliallnput Capacitance

+250 C

-

-

pF

20

-

-

3

+250 C

-

3

=1kHz)
Input Noise Current (I = 1kHz)

20

-

nV/y'HZ

2.4

-

-

2.4

-

pNVHz

Input Noise Voltage (I

+250 C

V

Input Noise Voltage
0.1 Hz to 10Hz (Note 9)

+25 0 C

-

-

1.5

+250 C

-

1.5

O.lHztolMHz

4.6

-

-

4.6

-

~Vr.m.s.

+250 C

3.5

6

-

3

6

-

kVN

Full

2.5

-

-2,-5

75

89

-9

75

Minimum Stable Gain

+25 0 C

Unity Gain Bandwidth (Notes 3, 9)

+25 0 C

Gain Bandwidth Product (Notes 3, 9)

+250 C

Phase Margin

+250 C

~Vp-p

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 4, 9)

Common Mode Rejection Ratio (Notes 6, 9)

2

-

70

89

89

-

65

89

-

+1

-

-

+1

-

-

-

45

-

-

45

50

-

-

50

65

-

-

65

-

3-305

kVN
dB
dB
VN
MHz
MHz
Degrees

.....

",en

;za:
OW

~§

a:

0-

w:;;

&'"

Specifications HA-2544
Electrical Specifications (Continued)
HA-2544-2/-5
PARAMETER

TEMP

MIN

TYP

HA-2544C-5

MAX

MIN

TYP

MAX

UNITS

:1:10

:1:11

3.2

4.2

-

MHz

OUTPUT CHARACTERISTICS
Output Voltage Swing

-

Full

:1:10

:1:11

Full Power Bandwidth (Note 7)

+250 C

3.2

4.2

Peak Output Current (Note 9)

+250 C

:1:25

:1:35

:1:35

+250 C

:1:10

-

-

:1:25

Continuous Output Current (Note 9)

:1:10

-

-

Output Resistance (Open Loop)

+250 C

-

20

-

-

20

-

0

Rise Time (Note 3)

+250 C

-

7

-

7

-

ns

Overshoot (Note 3)

+250 C

-

10

Slew Rate

+25 0 C

100

VIps

+250 C

V

mA
rnA

TRANSIENT RESPONSE

-

10

150

-

100

150

-

-

120

-

-

120

-

ns

-

-

0.03

-

Degree

0.0026

-

0.0026

+250 C

-

0.03

-

-

0.03

-

5MHz

+250 C

-

0.10

+250 C

-

0.10

10MHz

Settling Time (Note 5)
VIDEO PARAMETERS

RL=1kO

%

(Note 10)

Differential Phase (Note 12)

+25 0 C

Differential Gain (Notes 2, 12)

+250 C

0.03

dB

%

Gain Flatness

Chrominance to Luminance Gain (Note 13)

+250 C

-

Chrominance to Luminance Delay (Note 13)

+25 0 C

-

0.12

7

-

0.1

dB

7

-

0.12
0.1

dB
dB
ns

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Notes 8, 9)

Full

-

10

12

-

10

15

mA

-2,-5

70

80

-

70

80

-

dB

-9

65

80

-

"65

80

-

dB

NOTES:
1. Absolute maximum ratings are limiting values, applied individually

beyond which the serviceability of the circuit may be impaired.
Functional operabUity under any of these conditions is not

8. AVS = ±10 to ±20V
9. Refer to typical performance curve in Data Sheet.

, O. The video parameter specifications will degrade as the output load

necessarily implied.

resistance decreases.

AO(dB)
2. Aol'!!»

11. To achieve optimum AC performance, the input stage was designed

= [ 10 2 0 - 1 I x 100

without protective diode clamps. Exceeding the maximum differential in-

put voltage results in reverse breakdown of the base-emitter junction of
the input transistors and probable degradation of the input
parameters especially Vas, lOS and NOise.

3. VOUT "'" ±l00mV. For Rise Time and Overshoot testing, VOUT is
measured from 0 to +200mV and 0 to -200mV.
4. VOUT =±5V

5, Settling Time is specified to 0.1 % of final value for

a 10V step and

12. Tested with a VM700A video tester, using a NTC-7 CompOSite input signal. For adequate test repeatability, a minimum warm-up of 2 minutes is

suggested. AV

AV =-1
6. AVCM = ±10V
7. Full Power Bandwidth is guaranteed byequalion:
Full Power Bandwidth

= +1.

13. C-L Gain and C-L Delay was less than the resolution of the test
equipment used which Is O.ldB and 7ns, respectively.

= ~ (Vpeak used"", 5V)
2n Vpeak

3-306

HA-2544

Test Circuits
TRANSIENT RESPONSE
Vs = ±15V
AV= +1
RS = 50 or 750 (Optional)
RL = 1kO
CL < 10pF
~--~--,---,--oVOUT

VIN for Large Signal = ±5V
VIN for Small Signal = 0 10 +200mV
and 010 -200mV

-Vs

LARGE SIGNAL RESPONSE
VOUT = 0 to +10V
Vertical Scale: (YIN 5V/Div.; VOUT 2V/Div.)
Horizontal Scale: (100ns/Div.)

SMALL SIGNAL RESPONSE
VOUT = 0 to +200mV
Vertical Scale: (YIN = 100mV/Div.; VOUT = 100mV/Div.)
Horizontal Scale: (100ns/Div.)

SETTLING TIME TEST CIRCUIT

OFFSET VOLTAGE ADJUSTMENT

=

=

SETTUNG
POINT

VOUT

• AV =-1

• Feedback and Summing Resistors Must 8e Matched (0.1 %)

Tested Offset Adjustment Range Is I Vas +1mV I Minimum Referred
To Output. Typical Range For RT = 20kO Is Approximately ±30mV

• HP50B2-2810 Clipping Diodes Recommended.

• Tektronix P6201 FET Probe Used At Settling Point.

3-307

HA-2544
Typical Performance Curves
INPUT NOISE VOLTAGE AND
NOISE CURRENT VB. FREQUENCY

INPUT OFFSET VOLTAGE VS. TEMPERATURE
3 Typical Units

1000

@,
~

100

.... -'

1000

zr--- -

...

-r--

:>

.sw

.....

--

to

INPUT NOISE VOLTAGE

~ -1 ~~-1-t-t-r-r~~+-t-r-~~-1-t-t-t-r~

n111mr-TiT

10

~-2 ~~-+-+-+-t-t~4-+-+-r-~~-+-+-+-t~~
tA
.......

'"
~

~
~

~ -3 ..,.;±_::t-_-+-_+_-+_-t_-_I-.~.±.:±.-.r.",:- ,t"~""·"F·~·-+-+-+-H

2

INPUT NOISE CURRENT

Q~ ~~-1-t-t-t-r~~+-t-r-~~-1-t-t-t-r~

l"ttttIll10

tOO
lk
FREQUENCY (Hz)

10k

.DOk

~o

-60

-20

20

40

60

80

100

120

140

TEMPERATURE (DC)

NOISE VOLTAGE
(AV= 1000)
0.1 Hz to 10Hz, Noise Voltage =

INPUT BIAS CURRENT vs. TEMPERATURE
Vs = ±15V, RL lkO

=

0.97~Vp-p

15
14

13

"

I,

!

12

311

...

~ 10
a:

-

.....

g;

.
u

'"a;

-

f--

r--.

r--.
1'-01'-0

r-

r-r-

4
~o

-60

-20

20

40

60

80

100

120

140

TEMPERATURE (DC)

PSRR and CMRR vs. TEMPERATURE
Vs = ±15V, RL = 1 kO

OPEN LOOP GAIN vs. TEMPERATURE
Vs ±15V, RL lkO

=

=

r
-AVDL

I , , ,- '
,

~.

..... ...

..... -r-:, I," -

, \-"

, "

, ,

-

1-1-

-!-

- ....

,

+AVDL

....

:!/"
-60

~o

-20

20

40

60

TEMPERATURE (DC)

TEMPERATURE (OCI

3-308

80

100

120

140

HA-2544
Typical Performance Curves (Continued)
FREQUENCY RESPONSE AT VARIOUS GAINS
RL = 1kO, Vs = ±15V

OUTPUT VOLTAGE SWING vs. SUPPLY VOLTAGE
(Over Full Temperature)

-..

12
10

-550C
+250C _
+125 0C ......

!-!--

.-

;,;;;.i

.::::0,; ~

GAIN
IdBI
80

~~ ~

~ ~-

:--

-550C -

I--

-

"--

~250C
+125 C
0

'

~ 1:.:-'~-.i-_

It:::

.;:~

.....

AV = 100

f-<~~.!!'~
AV=-l ......

I
-

c

11

13

100

15

'r'-

I

IlltrIOIIl-t~~i:

III
lK

I->

- -. I--

AV-l00

III

.~

i""

r-

III
III

t;:.--_

I

RL = lkll
Vs = ±15V

-p

OPEN LO~'{,"'r-.

.

r

IIII I

III
OPEN LOOP

60
40

20

--- --....

riii;:

--

-r-i-

."': ~

1800

~,

SUPPLY VOLTAGE (! VI

"'\.

I
10M

10K
lOOK
1M
FREQUENCY 1Hz)

I

~ .....

V

'"r:;a:

135 0

900

~

45 0

"'~

DO

il:

100M

-'

50
40

1

30

550

~ 20

~
....

'"a:~

0

B~10

....

!'$;:: !;::.--

~-20

~--30

-

l1li.

40

~

~i:15V

V'.
~
~

-j25 0 C

~
1-. -

..

f-. -

-40

-

..

1-- -

--- r-. -,;" --..

11

-

PHASE

-I-.

Do

-450

+15V

.±8V

-900

$

-135 0

+5V
1,,-

"

13

15

100

r--- _ .
0.8

I

,

0.7

l

0.5
0.4

V

If.-

GAIN
(dBI

,

I' ....- I

10K
lOOK
1M
FREQUENCY (Hzl

=

1.1

0.9

lK

-1800
10M

ff-

/

~+1250C

/ , I_+--- +250C
-550C
V,

Il~=I)

=

III

I

VOUT =.:!:100mV
RL = lkll
CL =';;10pF

-~

-3
-6

J /
/

,"

t-

-

t-

---- =

0.1
11

13

100M

VOLTAGE FOLLOWER RESPONSE vs. SUPPLY VOLTAGE
AV +1, RL 1K, CL < 10pF

SUPPLY CURRENT vs. SUPPLY VOLTAGE
Normalized at Vs = ±15V at +25 0 C

0.2

~I.o.

Ni

SUPPLY VOLTAGE I!VI

0.3

-1--

-50

0.6

i;8V
.±5V

I'll ...

20
-550C
+250C

~~

o

I I

--

60

~ 1'>. ~ ~

-' !.::?- -'----.

10

!;i~

a: c..

80

jiIiiii
-.-:; Jo;.i.ii

+250C ---- t--""'-

+1250~

OW

GAIN
dB

-J_ J .
"--

«00
za:

OPEN LOOP RESPONSE vs. SUPPLY VOLTAGE
VOUT = ±100mV

OUTPUT CURRENTvs. SUPPLY VOLTAGE
(Over Full Temperature)

15

100

SUPPLY VOLTAGE I! VI

3-309

t-..

=+15V

+5V

I II1I

UI

IIII

lK

10K

PHASE
Do

-45 0

~~

- - =+8V
III

,,
,

-90 0
-1350
-1800

1M
lOOK
FREQUENCY IHzl

10M

100M

HA-2544
Typical Video Performance
A.C. GAI.N VARIATION vs. D.C. OFFSET LEVELS
(Differential Gain)

A.C. PHASE VARIATION vs. D.C. OFFSET LEVELS
(Differential Phase)

0.004

0.200

.. 0.003

;;; 0.150
~ 0.100

!;;:

0.002

......
E

-......

o

-0.002

~ -0.003

r--

,

'13.58 & 5.ooIMHZ

Q -0.004

1

-0.005
-0.006

....... ~

I

0

I

~

-0.20

a..

-0.25 0

.....

~.

......... ~

'-tooMHZ

'-3.58MHz ,/

,..,"""'"f-............

-0.300

2
3
D.C. VOLTAGE LEVel

............

---

D.C. VOL lAGE LEVel

DIFFERENTIAL GAIN
NTSC Melhod, RL = 1kO
Differential Gain < 0.05% at TA = +7SoC
No Visual Difference atTA = -550 C or +1250 C

DIFFERENTIAL PHASE
NTSC Melhod, RL = 1 kO
Differential Phase < O.OS Degree at TA = +7S oC
No Visual Difference at TA = -S50 C or +1250C

GAIN FLATNESS
AV +1, VIN = ±100mV
RL = 1K, CL < 10pF

CHROMINANCE TO LUMINANCE DELAY
NTSC Method, RL = 1 kO
C-L Delay < 7ns at TA = +750C
No Visual Difference at TA = -550C or +125 0C

INPUT

0.15

0.1
0.05

:i!
ffi

"

...~ -0.05

..

0.050

w -0.15: -

...........

1

o

~

~

c::J -0.05 0
z
~ -D.10 0

=

co
:!!
~

,

II:

0.001

-D.OD1

ffi

I
SYSlEJ ALONE -

~ -0.10

OUTPUT

-0.15
-0.20
100

1\
lK

lOOK
1M
10K
FREQUENCY (Hz)

10M

100M

Vertical Scale: Input = 100mV/Dlv.
Output = 50mV/Div.
Horizontal Scale: SOOns/Div.

3-310

HA-2544
Typical Video Performance Curves

(Continued)

±2 VOLT OUTPUT SWING
With RLOAD 750 (Frequency 5.00MHz)

=

L

I

I

I

-- --

,-

I

r-

-VOUT

TI

~ ~~
25O.000n5

VIN

r

':-..

--

=

13

.,

L.

BANDWIDTH vs. LOAD CAPACITANCE
AV +1, Vs ±15V, RL 1kO

=

.'"

I

I

I

-~ I-' ""1'
-r

.L

···--20

---40

-- --./.
-- --- ~ -;.-0.

O.OOOOOs

=

BANDWIDTH
(-3<18)
CL(pF)
___ , 0
35.5
40.8
--10
SO.1
55.8
-30
54.8

-

1--

~-

-

Y,N

25O.000n5

-12

= 2.0V/Div., VOUT = 2.0V/Div.
Timebase = 50ns/DiY.

-15
-18

lOOK

so

~

-

=

PHASE
(-3<18)

-77.10
-89.60
-122.00
-150.7°
-179.10

~

Vo

I ~K~CL

1M

-

'I!i

o

ra~

459.'"
oot:

:;:

135'"

w

10M

oo!il

1
100M

it

Applications And Product Guidelines
The HA-2544 is a true differential op amp that is as versatile
as any op amp but offers the advantages of high unity gain
bandwidth, high speed and low supply current. More
important than its' general purpose applications is that the
HA-2544 was especially designed to meet the requirements found In a video amplifier system. These
requirements include fine picture resolution and accurate
color rendition, and must meet broadcast quality standards.
In a video signal, the video information is carried in the
amplitude and phase as well as in the D.C. level. The
amplifier must pass the 30Hz line rate luminance level and
the 3.58MHz (NTSC) or 4.43MHz (PAL) color band without
altering phase or gain. The HA-2544's key specifications
aimed at meeting this include high bandwidth (50MHz), very
low gain flatness (0.12dB at 10MHz), near unmeasurable differential gain and differential phase (0.03% and
0.03 degrees), and low noise (20nV/y'Hz). The HA-2544
meets these quidelines and are sample tested for /883
grade product at 5 and/or 10MHz. If a customer wishes to
100% test these specifications, arrangement can be made.
The HA-2544 also offers the advantage of a full output voltage swing of ±1 OV into a 1K ohm load. This equates to a full
power bandwidth of 2.4MHz..for this ±10V signal. If video
signal levels of ±2V maximum is used (with RL = 1K ohm),
the full power bandwidth would be 11.9MHz without
Clipping distortion. Another usage might be required for a
direct 50 ohm or 75 ohm load where the HA-25.44 will still
swing this ±2V signal as shown in the above display. One
Important note that must be realized is that as load
resistance decreases the video parameters:· are also
degraded. For optimal video performance a 1kO load is
recommended.
If lower supply voltage 'are required, such as ±5V; many of
the characterization curves indicate where the parameters
vary. As shown the bandwidth, slew rate and supply current
are still very well maintained.
Prototyplng and PC Board Layout
When designing with the HA-2544 video op amp as with
any high performance device, care should be taken to use

high frequency layout techniques to avoid unwanted
parasitic effects. Short lead lengths, low source impedance
and lower value feedback resistors help reduce unwanted
poles or zeros. This layout would also include ground plane
construction and power supply decoupling as close to the
supply pins with suggested parallel capacitors of 0.1 !IF
and 0.001 !IF ceramic to ground.
In the non inverting configuration, the amplifier is sensitive to
stray capacitance «40pF) to ground at the inverting input.
Therefore, the inverting node connections should be kept to
a minimum. Phase shift will also be Introduced as load
parasitic capacitance is increased. A small series resistor
(20 ohm to 100 ohm) before the capacitance effectively
decouples this effect.
Stability/Phase Margin/Compensation
The HA-2544 has not sacrificed unity gain stability in
achieving its superb AC performance. For·thls device, the
phase margin exceeds 60 degrees at the unity crossing
point of the open loop frequency response. Large phase
margin is critical in order to reduce the differential phase
and differential gain errors caused by most other op amps.
Because this part is unity gain stable, no compensation pin
is brought out. If compensation is desired to reduce the
noise bandwidth, most standard methods may be used.
One method suggested for an Inverting scheme would be a
series R-C from the Inverting node to ground which will
reduce bandwidth, but not effect slew rate. If the user
wishes to achieve even higher bandwidth (>50MHz), and
can tolerate some slight gain peaking and lower phase
. margin, experimenting with various load capacitance can
be done.
Shown in Application 1 is an excellent Differential Input,
Unity Gain Buffer which also will terminate a cable to 75
ohm and reject common-mode voltages. Application 2. is a
method of separating a video signal up into the Sync. only
signal and the Video and' Blanking signal. Application 3
shows the HA-2544 being used as a 100kHz High Pass
2-Pole Butterworth Filter. Also shown is the measured
frequency response curves.

3-311

....I

oCt en
za:

OW

~§

a: c..

w:;;
~oCt

HA-2544
Typical Application
APPLICATION 2
Composite Video Sync. Separator

APPLICATION 1
750 Differential Input Buffer
SHIELDED

1K

1.211<

~ ~'"

'~l'l~
yy-

+

1.21K

.... J.

l~

JL1K

-

~~~

COMPOSrrE
VIDEO

HA-2544

SYNC ONLY

~1.21K

&

~ IN5711

~IN5711

1K

VIDEO AND BLANK

APPLICATION 3
100kHz High Pass 2-Pole Butterworth Filter

Measured Frequency Response of Application 3

.

2.1K
750pF

0--1'
INPUT

1

&

750pF

"

2.1K~
.~

..

.&

0

3

~

rV
+

....,--, II

-20

z

~

-40

,

10 =105.3KHz

= -&0

OUTPUT

~

I-

~ -80

HA-2544

1

-100

PHASE
+180

....

+135

1
f 0-21f(2.1K. 750pF)

+90
"

-145
0

t....
10

Die Characteristics
Transistor Count .............•.............•....... 44
Die Dimensions ....................... 80 x 65 x 19 mils
(2030 x 1630 x 48511m)
Substrate Potential* ................................ vProcess ..••................. High Frequency Bipolar 0.1.
Passivation .................................... Nitride
Thermal Constants (OCIW)
9ja
9jc
Metal Can TO-99, HA2-2544
Plastic Mini-DIP, HA3-2544/2544C
Ceramic Mini-DIP, HA7-2544
SOIC, HA9P2544

186
80
185
160

50
20
98
42

*The substrate may be left floating (Insulating Die Mount) or it may be
mounted on a conductor at V- potential.

3-312

100

IK

10K
lOOK
FREQUENCY (Hz)

1M

10M

-45

HA-2548

m)HARRIS

Precision, High Slew Rate,
Wideband Operational Amplifier

August 1991

Features

Description

• High Slew Rate •••••••••••••••••••••••••••• 120VlllS

The HA-2548 Is a monolithic op amp that offers a unique
combination of bandwidth, slew rate, and precision specifications. These features can eliminate the need for composite op amp designs and external calibration circuitry.

• Low Offset Voltage •••••••••••••••••••••••••• 300llV
• High Open Loop Gain ••.••••••••••••••••••••• 130dB

Optimized for gains ~5, the HA-2548 has a gain-bandwidth product of 150MHz and a slew rate of 120V/lls while
maintaining extremely high open loop gain (130dB typ) and
low offset voltage (3001lV typ). These specifications are
achieved through uniquely designed input circuitry and a
single ultra-high gain stage that minimizes the AC signal
path. Capable of delivering over 30mA of output current, the
HA-2548 is ideal for precision, high speed applications
such as signal conditioning, instrumentation, video/pulse
amplifiers and buffers.

• Gain Bandwidth Product ••••••••••.•••••••• 150MHz
• Low Voltage Noise @ 1kHz •••••••••••••• 8.3nVlyIHz
• Minimum Gain Stability ••••••• '" •••••••••.••••• ~5

Applications
o

High Speed Instrumentation

• Data Acquisition Systems
o

The HA-2548 is offered with a -5 temperature grade guaranteed between OOC and +75 0 C and a -9 temperature
grade guaranteed between -400 C and +85 0 C. Both grades
are available in either a Ceramic Sidebrazed DIP or a TO-99
Metal Can. The HA-2548 Is also available in SOIC packaging with -5 temperature range. For information on the
military version of this device please refer to the
HA-2548/883 datasheet.

Analog Signal Conditioning

• Precision, Wideband Amplifiers
• Pulse/RF Amplifiers

Pinouts
HA7-2548
(CERAMIC SIDEBRAZED DIP)
HA9P2548 (SOIC)
TOP VIEW

Schematic

(Simplified)

~nDa
01'0211

RD<

lQPD3

...

HA.

OPD<

OPAl

=e,
ne.

..

R821

OPA>
QP21

~F

I

~,

QPllD

QNI3~ ~ONI4

CO
OPAS

~

rr'

- -t opb

Nn

OND '

HA2-2548
(TO-99 METAL CAN)
TOP VIEW

~~

ROil

RDrn

QPD2CI

(

1-'"

~,

COMP

- -

nil

.".

P 1O
ONti '

~f'

~~QHOI

no,

f-

HI2

J_

QP117

ON113

ONII<]

QHAM

~opo.~
ON02

~QNAOO

~~

~,

'l0N011
OND
13

JOND1S

n013

Ru1&

ONDI01

1

~~OPOII
OP07

ONAI!

(I

OHllll1

RAD
ALI

ROilS

·u

DAL

~

It :0 ~~ ..
RA~
12

;:

...

ItW 2St827AGEM

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

3-313

RO<

ONOO

. .A

.'N

f-

no.

h

RD.

QNA11~

~Ir

QNU1~
RD1~

.,

0'"

II

ON018

RA

,

OAL

..

RD

DAL

File Number

-v

2901

Specifications HA-2548
Absolute Maximum Ratings

Operating Temperature Range:

(Note 1)

Voltage Between V+ and V- Terminals ••••••••••••••••••••• 40V
Differential Input Voltage ••••••••••••••••••.•••••••••••••••• 5V
Output Current •••••••••••••••••••••••••••••••••••••••• 40mA

Electrical Specifications

HA-2548-5 •••••••••••••••••••••••••.••••• OOc ~ TA ~ +750C
HA-2548-9 •••••••••••••••••.••••••••••• -400C ~ TA':> +850C
Storage Temperature Range ••••••..•.••• -650C ~ TA ~ +1500C
Maximum Junction Temperatura ••••••••••••••••••••••• +1750C

V+ = +15V, V- = -15V, RL = lK, CL = 10pF. (Unless Otherwise Specified)

I
PARAMETER

TEMP

I

HA-2548-5, -9
MIN

I

HA-2548A-5

TYP

MAX

300
400
4
5
20
5

900
1200

MIN

TYP

MAX

IUNITS

-

100
200

300
600
7
50
100
50
100

/IV
IIV
IIVJOC
nA
nA
nA
nA

INPUT CHARACTERISTICS
Input Offset Voltage
Average Offset Voltage Drift (Note 12)
Input Bias Current
Input Offset Current
Common Mode Range
Differantiallnput Resistance
Input Noise Voltage
10=0.lHztol0Hz
10 =0.1 Hz to 1 MHz
Input Noise Voltage Density 10=10Hz
(Note 2)
10=100Hz
10=1000Hz
Input Noise Current Density 10=10Hz
(Note 2)
10=100Hz
10=1000Hz

+250C
Full
Full
+250C
Full
+250 C
Full
+250C
+250C
+250C
+250C
+250C
+250C
+250C
+250C
+250C
+250 C

:1:7
-

20
:1:10
1
0.2
0.8
30
12
8.3
1.9
0.7
0.4

9
50
100
50
100

-

-

3
5
20
5
20
:1:10
1
0.2

0.7
0.4

-

120
118
80
130
110
5

130
125
90
150
125

-

:1:11

:1:12

:1:30

:1:33
5
1.91

:1:7

-

0.8
30
12
8.3
1.9

V
MO
IIVrinS
IIVrms
nV/.jHi
nV/.jHi
nV/.jHi

pN.jHi
PN.jHi
pNv'Hz

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)
Common Mode Rejection Ratio (Note 4)
Gain Bandwidth Product (Note 5,12)

+250C
Full
Full
+250C
Full
Full

Minimum Stable Gain

114
108
80
130
110
5

130
125
90
150
125

-

-

-

-

dB
dB
dB
MHz
MHz

-

VN

-

Volls

-

mA
0
MHz

OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current (Note 8)
Output Resistance
Full Power Bandwidth (Note 7,12)

Full

:1:11

:1:12

Full
+250C
+250C

:1:30

:1:33
5
1.91

+250 C
Full
+250 C

80
70

-

-

-

-

-

-

TRANSIENT RESPONSE
Slew Rate (Note 8,12)

Positive
Negative

Rise Time (Note 9,12)

Full
+250C

Fall Time (Notes 9,12)

Full
+250 C

Overshoot (Note 9,12)

Positive

Full
+250C

Negative

Full
+250 C

70
60

Full
+250C

-

PSRR (Note 11 )

Full

86

ICC

Full

-

Settling Time (Note 1 0,12)

120
105
110
105
16.5
19
16
18
15
25
8
20

-

20
23

20
23
25
35
15

80
70
70
60

-

30
260

-

95

-

86

12

18

200

120
105
110
105
16.5
19
16
18
15

-

25
8
20
200

20
23
20
23
25
35
15
30
260

95
12

18

V/IIS
V/IIS
V/IIS
V/JIS
ns
ns
ns
ns
%
%
%
%
ns

POWER SUPPLY

3-314

-

-

dB
mA

HA-2548
NOTES:
1. Absolute maximum ralings are limiting values. applied individually,

7. Full Power Bandwidth is calculated by:

beyond which the servicability of the circuit may be impaired.

FPBW = Slew Rale

Functional operation under any of these conditions is not nessarily
implied.

,Vpeak = 10V

2. Vpeak

8. VOUT = ±5V, AV = +5.

2. Refer to typical performance curve in data sheet

9. VOUT = ±1 OOmV, AV = +5.

3. VOUT = ±10V.

10 Settling time is specified to 0.01 % with a 10V step and AV = -5.

4. VCM = ±2V.

11. Celta Vs = ±10V to ±20V.

5. Characterized in an AV = -100 configuration from 100kHz to 10MHz.

6. RL = lkn, VOUT > 10V.

12. These parameters are nollested. The limits are guaranteed based on lab
characterization and reflect lot to lot variation.

Test Circuits and Waveforms
LARGE AND SMALL SIGNAL RESPONSE CIRCUIT
IN

>-"",--0 OUT
800A

AV~

+5

200A

-'
«en
za:

OW

LARGE SIGNAL RESPONSE
YOUT = ±5Y, Ay = +5, RL = 1K, CL ~ 10pF

SMALL SIGNAL RESPONSE
YOUT=±100mY, Ay=+5, RL=1K,CL~10pF

IN OV

OUT OV

HA-2548 SETTLING TIME
Ay = -5, Output = -10Y Output Scale Yertical: 1mV/Div
Horizontal: 50ns/Div

SETTLING TIME TEST CIRCUIT

100

~~~~~~___~___~TO

IN OV

OSCILLOSCOPE

>-+-'l--O VOUT
OUT OV
2K
• AV =-5
• Feedback and summing resistors should be 0.1 % matched.
• Clipping diodes are optional. HP5082-2810 recommended.

3-315

~~

w:;;
~«

HA-2548
Typical Performance Curves Vs = ±15V, TA = +25 0 C
VIO vs TEMPERATURE
(3 Representative Units)

:;::1.

1000
800
600
400
200

OFFSET CURRENT/SIAS CURRENT VB TEMPERATURE
20
18
16

0
Q -2D
> -400
-1m
-1Ul
-1000
-55

~14

...

;:-12

\
tt.1

ffil0
[ 8

13

6

I' ~

4
2
-25

0

+25

+75

+ 125

110

r--.

iooJ..

IS

J

-55

,I
-25

0

TEMPERATURE (DC)

t!l
Z
<
J:

Q
I-

W

r'"
200

10-

i"'oo

~

r'"

....

100

r'"

0

~

i"'oo

PSRR

10-

-100

10-

1"00

In

u..
u..
0

+ 125

92

300

~
w

+75

PSRR/CMRR va TEMPERATURE
VCC = :l:l5V, VCM = :l:2V, Vs = :l:l0V to :l:20V

VIO WARM-UP DRIFT (NORMALIZED FROM ZERO)
(4 Representative Units)

:;-

+25

TEMPERATURE (DC)

CMRR

-200
82
-55

-300

o

1.0

2.0

3.0

4.0

5.0

-25

0

+25

+75

+ 125

TEMPERATURE (DC)

6.0

TIME (MIN)

AVOLvsTEMPERATURE
VCC = :l:15V, RL = lKn
CL :S10pF, VOUT :l:l0V

=

ICC vs TEMPERATURE

=

150
13.0 +-H-t++-H-t++-H-t++-H-I

140

~

130

I""

.....

§: 120

...

<

110
100
-55

11.~ ...
55.......-'-_.L2--5~'10.&........+.....25:::"-'-......-'-+-'::7=5~--'--'-+~125
TEMPERATURE (DC)

-25

0

+25

+75

TEMPERATURE (DC)

3-316

+ 125

HA-2548
Typical Performance Curves (Continued) Vs = ±15V, TA = +250 C
VOUTvsTEMPERATURE
Vee;±15V, RL;lkO, eL;s;lopF

VIO vs ±Vcc vs TEMPERATURE

13

~

"

12

I-

o

>

::I.

L..oo ....

....

:::J

;;Q

>

500
400
300
200
100
0
-100
-200

...

-300

11

-400
-500

9

10

11

12

10

-55

-25

0

+25

+ 125

+75

13

14

15

16

17

18

,:!:VCc(V)

TEMPERATURE (DC)

-'
«(I)
za:
oW

AVOL vs ±Vce vs TEMPERATURE

Vour; ±5V @ Vee; ±10V, Vour; ±10V @ Vee; ±15V
Vour; ±12V @ Vee; 18V

iD

"-:,
0

>

<:

136
134
132
130
128
126
124
122
120
118
116

16
15
14
13
~ 12
....:J
0 11
> 10
+1 9

+25"C

i-'
+ 125°C

-55"c

11

12

13

14

15

16

17

~

i"!;.o
100'

.,.

100'

;.0

7
6

18

10

9

11

12

!VCC(V)

13

14

15

16

II

140
14

8

",....

130

'r

..J

§2

I;

<:

6
8

10

12

14

16

115

105

18

~~

120

110
6

V-

iD 125
:!1.

J

10

8

lv~~

135

12

18

AVOL/VOUT vs RL
VIN; ±3V For 1000, VIN; ±5V For 2000
VIN ; ±10V For 6000 to 10kO

16

<'

17

.:!:vcc(V)

SUPPLY CURRENT vs ±SUPPLY VOLTAGE

.§.

w::;;;

15«

~

8
10

i=LL
«::::;
a: c..

±VOUT VS ±Vcc vs TEMPERATURE
RL; lK

L~

10
9

8

V
400 600 1000

2000

RL (ohms)

3-317

12
11

~

~/

200

13

VO UT

/ l/

100
100

.:!:VCC(V)

II

4000

10000

~

....

:J

0

>

HA-2548

Typical Performance Curves

(Continued) Vs

= ±15V, TA = +250 C
. RISE TIME vs TEMPERATURE
VCC = :l:15V, RL = lkO, CL = :$.10pF
AV = +5, VOUT = :l:l00mV(200mVp-p)

SLEW RATE vs TEMPERATURE
VCC = :l:15V, RL = lkO, CL =:$. 10pF
Av = :1:5, VOUT = :l:5V(10Vp-p)

en

140

22

130

21
20

g

:1.

:>w

~

<
a: 110

~
en

...

120

i"

100

90
-55

0

-25

+25

19

w 18

f= 17
w 16

"

en

it

... -

15
13
12
- 55

-25

TEMPERATURE (0C)

......

>

5

o

-55

o

-25

0

+25

+75

+75

+ 125

f:~.111111

~

a: 10
w
0

+25

GAIN BANDWIDTH PRODUCT va
COMPENSATION CAPACITANCE

35

30
I- 25
0
0 20
::t:
en 15

0

TEMPERATURE (OC)

% OVERSHOOT vs TEMPERATURE
AV = +5, VOUT = :l:l00mV(200mVp-p)
RL = 1kO, CL ::;'10pF

t

"""

14

+ 125

+75

"""

~

::!

10

+ 125

20

30

40

50

CAPACITANCE (pF)

TEMPERATURE (oC)

GAIN AND PHASE vs FREQUENCY
RL = lkO, CL:$. 10pF

SLEW RATE vs COMPENSATION CAPACITANCE

~;~.~IIIIIII~
o

5

10

15 20 25 30 35
CAPACITANCE (pF)

40

1111
1111

100

80

A;;:'L

~60
z

~

45

.....

40

AV --5

20

-

o

0°
45°

til
w
w

tt

90°
135 0
180°

ffi
e.

w
~

J:

C.

10

100

lK

10K

lOOK

FREQUENCY (Hz)

3-318

1M

10M

100M

HA-2548
Typical Performance Curves

(Continued) Vs = ±15V. TA = +25 0 C

INPUT NOISE VOLTAGE DENSITY

INPUT NOISE CURRENT DENSITY

~

40

>
oS

30

I\...

UJ
(!l

~
o

>

r---

o
z

z
UJ

1.0

:::J

()

UJ

!!l

1.5

a:
a:

I'

10

<
.e

,

1\

f-

1\

20

2.0

~

i"""""o

0.5

UJ

en

0

a

100

10

lK

10K

100K

z

o
10

100

FREQUENCY (Hz)

PEAK TO PEAK NOISE 0.1 HZ TO 10HZ
p-p(RTI) 691.4nV. rms(RTI)
116.5nV, AV 25000

=

=

lOOK

lK
10K
FREQUENCY (Hz)

PEAK TO PEAK NOISE O.lHZ TO lMHZ
p-p(RTI) 4.00411V, rms(RTI) 664.5nV, AV 25000

=

=

=

=

...J
«(I)

:z a:
OW

~~
0..

a:

w:;;

:5«

REJECTION RATIOS vs FREQUENCY
AV = ±10, VIN = 300mVrms

·20
·30

;

·40
• PSRR.(;MR

iii"
~

a:
a:

-50

I

I

j

·60

·70

~

·80

11
+PSRR

·90

I

-100

I
10

100

lK

10K

lOOK

FREQUENCY (Hz)

3-319

1M

10M

mHARRIS

HA-2600/02/05
Wideband, High Impedance
Operational Amplifiers

August 1991

Features

Applications

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•

Wide Bandwidth ••••••••••••••••••••••••••• 12MHz
High Input Impedance •••••••••••••••••••••• 500MO
Low Input Bias Current •••••••••••••••••••••••• 1 nA
Low Input Offset Current •••••••••••••••••••••• 1 nA
Low Input Offset Voltage •••••••••••••••••••• O.5mV
High Gain ••••••••••••••••••••••••••••••••• 150kVN
High Slew Rate ••••••••••••••••••••••••••••••• 7V/IlS
Output Short Circuit Protection
Unity Gain Stable

Video Amplifier
Pulse Amplifier
Audio Amplifiers and Filters
High-Q Active Filters
High-Speed Comparators
Low Distortion Oscillators

Description
HA-2600/2602/2605 are internally compensated bipolar
operational amplifiers that feature very high input impedance (500MO, HA-2600) coupled with wideband AC
performance. The high resistance of the input stage Is complemented by low offset voltage (O.5mV, HA-2600) and low
bias and offset current (1 nA, HA-2600) to facilitate accurate
signal processing. Input offset can be reduced further by
means of an external nulling potentiometer. 12MHz unity
gain-bandwidth, 7VIIlS slew rate and 150kV/V open-loop
gain enables HA-2600/2602/2605 to perform high-gain
amplification of fast, wide band signals. These dynamic
characteristics, coupled with fast settling times, make these
amplifiers ideally suited to pulse amplification designs as
well as high frequency (e.g. video) applications. The
frequency response of the amplifier can be tailored to exact
design requirements by means of an external bandwidth
control capacitor.

Pinouts

In addition to Its application In pulse and video amplifier
designs, HA-2600/2602/2605 are particularly suited to
other high performance designs such as high-gain low
distortion audio amplifiers, high-a and wideband active
filters and high-speed comparators. For more Information,
please refer to Application Note 515.
The HA-2600 and HA-2602 have guaranteed operation
from -550 C to +125 0 C and are available In Metal Can and
Ceramic Mini-DIP packages. Both are offered as 1883
Military Grade; product and data sheets are available upon
request. The HA-2605 has guaranteed operation from OOC
to +75 0 C and is available in Plastic and Ceramic Mini-DIP
and Metal Can packages. SOIC packaging is also available
for the HA-2605 with guaranteed operation from OoC to
+70 0 C (-5) and -400 C to +85 0 C (-9).

Schematic

HA9P2605 (SOl C)
HA7-2600/02/05 (CERAMIC MINI-DIP)
HA3-2605 (PLASTIC MINI-DIP)
TOP VIEW

COMPENSATION

HA2-2600/02/05 (TO-99 METAL CAN)

TOP VIEW
COMP

NOTE: VCASE =

v-

CAUTION: These devices are sensitive to electrostatic discharge. Proper

I.e. handling procedures should be followed.

Copyright @ Harris Corporation 1991

3-320

File Number

2902

Specifications HA-2600/02/05
Absolute Maximum Ratings (Note 13)

Operating Temperature Ranges

Voltage Between V+ and V- Terminals ••••••••••••••••••. 45.0V
Differentiallnput Voltage •••••••.••.•••.•..••••••••.•••• ±12.0V
Peak Output Current •.••••••••.••.•• Full Short Circuit Protection
Internal Power Dissipation •..••..••.••.••.•••.••.•.•.• 300mW
Maximum Junction Temperature •.•.•••.••.••••••.••••• +175 0 C

HA-2600/HA-2602-2 .••••••••••••••••• -550 C::; TA ~ +125 0C
HA-2605-5 •••••••••••.•••..••••••..•..••. 00C::;TA5.+750C
HA-2605-9 •..••.••••••••.•••••..••••..• -400C.:S.TA5 +85 0C
Storage Temperature Range ••••••.••.•.. -650 C 5. TA 5 +150oC
Lead Solder Temperature (1 0 Seconds) •..•••••.•...•. '. +2750 C

Electrical Specifications Vs = ±15V D.C., Unless Otherwise Specified.

HA-2600-2
PARAMETER

TEMP

MIN

+250 C
Full
Full

-

HA-2G02-2

TYP MAX MIN

HA-2605-5

TYP MAX MIN

(NOTE 15)
HA-2605-9

TYP MAX

MAX

UNITS

5
7

5
7

mV
mV

-

25
40
25
40

25
70
25
70

INPUT CHARACTERISTICS
Offset Voltage

0.5

Bias Current

+250 C
Full

Offset Current

+250 C
Full

-

2
5
1
10
1
5

Differential Input Resistance
(Note 10)
Input Noise Voltage Density
10=lkHz
Input Noise Current Density
10 = 1kHz
Common Mode Range

+250 C

100

500

+250 C

-

11

+250 C

-

0.16

Full

±11

±12

Average Offset Voltage Drift

-

-

4
6

-

10
30
10
30

-

-

5
15

-

-

-

40

300

-

-

0.16

±11

±12

-

5
7

3

5

-

3

5
5

-

-

40

300

-

-

I1V;oC
nA
nA
nA
nA
Mn

-

-

11

-

-

nVl,jHZ

ow
~§

0.16

-

-

pNv'Hz

l5100~~~r---~r---~r---~r----'

10

3w

<-.s

rn

5

I-

zw

a:
a:
u

BROADBAND NOISE CHARACTERISTICS

0

OFFSET

:;)

- 5
BIAS
-10

./

..,..-

/

~
Iir

--

!z

~

!l!
5

@-1
- 25

10kHz 100kHz lMHz 10MHz
UPPER adB FREQUENCY
LOWER 3dB FREQUENCY (10Hz)

OPEN LOOP FREQUENCY AND PHASE RESPONSE
00120

z

$ 100
W 80

~
~

§2
D..

o

I---

........
..........

GAI'N-

I
I
VS=t l 5V _
TA=t2SOC _

20°

40

9

20

Z
~

0

.......

60°

.........

""-.. ~

~ r-

INPUT IMPEDANCE VB. TEMPERATURE, 100Hz

1000
0°

NHASE.........
60

1000

t!l
Z

800

<
w

rn

~

0

rn
D..

140°

t!l

~400
200

180°

0
-55

r--..

"'"

""-....

-35 -15 +5 +25 +45+65+85+105+125
(oC)

OPEN-LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND

m
12Or---,----,----r---,----,----"
.:g

~t
2OV~~~~~:===~c=====~======~
I-o~ I 10V
±!

~

.........

TEMPERATURE

OUTPUT VOLTAGE SWING VB. FREQUENCY

~

!'....

'"

~800

10Hz 100Hz 1kHz 10kHz 100kHz lMHz 10MHz 100MHz
FREQUENCY (Hz)

~w

-........

~

0_ 20

t!l
Z

~~~~__~~__~~__~~__~

100Hz 1kHz

0
+25
+50 +75 +100+125
TEMPERATURE (OC)

.:g

I---l----+_----,

!:

V

- 15
- 50

10

Z

$
w

~

lVr-----~--~~~~---t----~

~

§2
D..

o

0.1V r-------+------+----"""'~----___i

9

§2

z

~

~

T= 25°C
~ O.OlV L -_ _ _' -_ _ _..L-_ _ _....I..._ _ _....J
10kHz
100kHz
lMHz
10MHz
100MHz
FREQUENCY (Hz)

o
10kHz 100kHz lMHz 10MHz
FREQUENCY

(Hz)

NOTE: External Compensation Components are not required for stability.
but may be added to reduce bandwidth if desired. If External Com·
pensatiol'l is used, also connect 100pF capacitor from output to

ground.

3-322

HA-2600/02/05
Typical Performance Curves

(Continued)

COMMON MODE VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE

>20

I

±!

1

I

-5SOC:::;T A :::;+ 125°C

w

r2
::;;

z
~
::;;
o(.l

5 "...

V

V

/

V

w

t.lov sluppL

/

~ 15

810

OPEN - LOOP VOLTAGE GAIN vs. TEMPERATURE
120

-

-

+15\'

-

SU~PlY

-- -

--

r-- rt.!.OV SUPPL Y - r-- '-- r---:t 5V suPPLYr-=:.r--=_

,,/

10

5

15

80
- 55 - 35 -15

20

SUPPLY VOLTAGE (VOLTS)

525456585

105 125

TEMPERATURE (oC)
...J



...

~40

o

~

-

II:

(.l

<

<

Z

el

I'-...

80

~

5

w

Z

o
~
o
~

10

.5

~ 100
II:
o
~
~

,N

~1000
>

"C

;

NOISE DENSITY vs. FREQUENCY

10

10K
lK
100
(Hz)
FREQUENCY

:!:

lMHz

Test Circuits
TRANSIENT RESPONSE

SLEW RATE

1200mv

~
INPUT
i200mv~
____ --

~
INPUT

~T

~9''''

:

10'1b___

:

:

,

t5V _ _ _ _ _ _

90%- -

--

OUTPUT

OmV

5V

-5V

rN

90'lIl- -

SLEW RATE AND
TRANSIENT RESPONSE

1_ RISE TIME

!

- - - -

OUTPUT
10'1b _ _ _ _ _

-5V-

,

""1 -

I

AV

J_t_

SUGGESTED VOS ADJUSTMENT AND COMPENSATION
HOOK-UP

+v

-""1>._" OUT

; i--hT.J SLEW RATE
, t

:

j,V/AT

Tested Offset Adjustment is
IVas +lmV I minimum referred to

NOTE: Measured on both positive
and negative transistions
from a to +200mV and 0
to -200mV at output.

output. Typical range is ±10mV

with RT = 100kll.

3-323

u:
i= ::::;
~~V_Oo=

(1+

Ib~S

"

IfC= 1000pF
Drift = 0.01 V/m. Max.

VOLTAGE FOLLOWER

:~

IN 0---1

) VREF

OUT

VREF

5OP
-15V
liN = 1012 Min.
lOUT = 0.D1 Max.
Slew Rate 4V/JIS Min.

FEATURES:
1. Minimum bias current In reference cell
2. Short circuit protection

=

F*-r
"

B.W. = 12MHz Typ.
Output Swing = ±10V Min. to 50kHz

* A small load capacitance Is recommended in all applications where practical to prevent possible high frequency oscillations resulting from external wiring
parasitics. Capacitance up

to 100pF has negligible effect on the bandwidth or slew rate.

Die Characteristics
Transistor Count .................................. 140
Die Dimensions ....................... 73 x 52 x 19 mils
Substrate Potential ........................... Unbiased
Thermal Constants (OC/W)
HA2-Metal Can (-2, -5, -7)
HA2-Metal Can (-8,/883)
HA3-Plastlc DIP (-5)
HA4-Ceramic LCC (/883)
HA7-Ceramic DIP (-2, -5, -7)
HA7-Ceramic DIP (-8,/883)
HA9P-SOIC-(-5, -9)

9ja

9jc

202
161
83
96
204
100
160

55
48
33
35
112
27
42

3-324

{II

HARRIS

HA-2620/22/25
Very Wideband,
Uncompensated Operational Amplifiers

August 1991

Features

Applications

Gain Bandwidth Product (AV ~ 5) .••••••.•• 100MHz
High Input Impedance .•••.••••••••••••••••• 500Mn
Low Input Bias Current •••••••••••••••••••••••• 1 nA
Low Input Offset Current •••••••••••••••••••••• 1 nA
Low Input Offset Voltage •••.•••••.•••••••••• O.5mV
High Gain ••••••••••••••••••••••••••••••••• 150kVIV
o High Slew Rate ••••••••••••••••••••••••••••• 35V/~s
• Output Short Circuit Protection

• Video and R.F. Amplifier
• Pulse Amplifier
o Audio Amplifiers and Filters
• High-Q Active Filters
• High-Speed Comparators
• Low Distortion Oscillators

•
•
•
•
•
•

Description
HA-2620/2622/2625 are bipolar operational amplifiers that
feature very high input impedance (500Mn, HA-2620)
coupled with wideband AC performance. The high
resistance of the input stage is complemented by low offset
voltage (O.SmV, HA-2620) and low bias and offset current
(1 nA, HA-2620) to facilitate accurate signal processing.
Input offset can be reduced further by means of an external
nulling potentiometer. 100MHz gain-bandwidth product
(HA-2620/2622/2625 are stable for closed loop gains
greater than 5), 35V/~s slew rate and 150kV/V open-loop
gain enables HA-2620/2622/2625 to perform high-gain
amplification of very fast, wideband signals. These dynamic
characteristics, coupled with fast settling times, make these
amplifiers ideally suited to pulse amplification designs as
well as high frequency (e.g. video) applications. The
frequency response of the amplifier can be tailored to exact

Pinouts

design requirements by means of an external bandwidth
control capacitor.
In addition to its application in pulse and video amplifier
designs, HA-2620/2622/2625 is particularly suited to
other high performance designs such as high-gain low
distortion audio amplifiers, high-Q and wideband active
filters and high-speed comparators. For more information,
please refer to Application Notes 509, 519 and 546.
The HA-2620 and HA-2622 have guaranteed operation
from -550C to +1250C and are available in Metul Can and
Ceramic Mini-DIP packages. Both are offered as /883
Military Grade with the HA-2622 also available in LCe
packages. MIL-STD-883 data sheets are available upon
request. The HA-2625 has guaranteed operation from ooe
to +750 C and is available in Plastic and Ceramic Mini-DIP
and Metal Can packages. Additionally the HA-2625 is available in sOle packaging with -5 and -9 temperature grades.

Schematic

HA9P2625 (SOIC)
HA7-2620/22/25 (CERAMIC MINI-DIP)
HA3-2625 (PLASTIC MINI-DIP)
TOP VIEW

COMPENSATION

r---~--~~--~-----------------I'--~~~~~~~'V

HA2-2620/22/25 (TO-99 METAL CAN)
TOP VIEW
COMP

CAUTION: These devices are sensitive to electrostatic discharge. Proper
Copyright © Harris Corporation 1991

I.e. handling procedures should
3-325

be followed.

File Number

2903

....
«en

z a:

OW

~~

~~

o

Specifications HA-2620/22/25
Absolute Maximum Ratings (Note 13)

Operating Temperature Ranges

Voltage Between V+ and V- Terminals ................... 45.0V
Differential Input Voltage ............................... :l:12.0V
Peak Output Current ......•••••..••• Full Shori Circuit Protection
Internal Power Dissipation ............................ 300mW
Maximum Junction Temperature •••••.•••••••••••..•••• +1750 C

HA-2620/HA-2622-2 .................. -550 C STA'S+1250 C
HA-2625-5 ............................... oOC 5 TA S +750 C
HA-2625-9 ............................. -400C S TA S +80oC
Storage Temperature Range: ............. -650C $. TA5 +150oC
Lead Solder Temperature (1 0 Seconds) ................. 2750C

Electrical Specifications

Vs =

±15V D.C., Unless Otherwise Specified.
HA-2620-2

PARAMETER

TEMP

MIN

+250 C
Full

-

HA-2622-2

TYP

MAX

0.5
2

4
6

MIN

HA-2625-5, -9

TYP

MAX

3

5
7

MIN

TYP

MAX

UNITS

3

5
7

mV
mV

INPUT CHARACTERISTICS
Offset Voltage (Note 1)
Average Offset Voltage Drift
Bias Current

Full
+250 C
Full

5

-

1
10

15
35

-

1
5

Offset Current

+250 C
Full

Differential Input Resistance (Note 11)

+250 C

65

500

=1kHz
Input Noise Current Densllylo = 1kHz

+250 C

-

11

+25 0 C

-

Full

:1:11

+250 C
Full

lOOK
70K

150K

-

Full

80

Minimum Stable Gain

+250 C

Gain Bandwidth Product
(Notes 2, 5 & 6)

+250 C

Input Noise Voltage Density 10
Common Mode Range

-

5

-

5

15
35

-

5

-

25
60

300

-

-

-

-

40

0.16

-

-

0.16

:1:12

-

:1:11

:1:12

-

-

80K
60K

150K

100

-

74

100

5

-

-

100

-

5

-

-

100

-

:1:10

:1:12

:1:10

:1:18

320

11

25
60

-

-

-

..VfOC

5

25
40

nA
nA

5

25
40

nA
nA

40

300

-

11

-

nVlVHz

-

5

-

MO

-

0.16

-

pN..;Hz

:1:11

:1:12

-

V

-

80K
70K

150K

-

-

-

VN
VN

74

100

-

dB

5

-

-

VN

-

100

-

MHz

:1:10

:1:12

:1:10

:1:18

600

-

320

600

-

TnANSFER CHARACTERISTICS
Large Signal Voltage Gain
(Noles 2 &3)
Common Mode Rejection Ratio
(Note 4)

-

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 2)

Full

:1:10

:1:12

Output Current (Note 3)

+250 C

:1:15

:1:22

Full Power Bandwidth
(Notes 2, 3, 7 & 12)

+250 C

400

600

-

-

V
mA
kHz

TRANSIENT RESPONSE (Note 8)
Rise Time (Notes 2, 7 & 8)

+250 C

-

17

45

-

17

45

-

17

45

ns

Slew Rate (Notes 2, 7,8 & 10)

+250 C

:1:25

:1:35

-

:1:20

:1:35

-

:1:20

:1:35

-

VI..s

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 9)

+250 C

-

3

3.7

-

3

4

-

3

4

mA

Full

80

90

-

74

90

-

74

90

-

dB

NOTES:
1. Offset may be externally adjusted to zero.

9. AVS = ±5V

2. RL = 2kO

10. VOUT = ±5V

3. VOllT = ±10.0V

11. This parameter value guaranteed by design calculations.

4. VCM = ±10V

12. Full Power Bandwjdth guaranteed by slew rate measurement:
FPBW = S.R./2nVpEAK.

5. VOllT

< 90mV

6. 40dB Gain

7. See Transient Response Test Circuits & Waveforms.
8. AV

=5

(The HA-2620 family is not stable at unity gain without

external compensation.)

13. Absolute Maximum Ratings ara IImiling values applied individually
beyond which the serviceability of the circuit may be impaired.
Functional operation under any of these conditions is not necessarily
implied.

3-326

HA-2620/22/25
Typical Performance Curves

Vs = ±15V D.C., TA = +250 C, Unless Otherwise Specified.

INPUT BIAS CURRENT AND OFFSET CURRENT
AS A FUNCTION OF TEMPERATURE

BROADBAND NOISE CHARACTERISTICS

>100 r-~--r-----~----'------r----~

15

310

w

(fJ

';;(

~

5

0:

j::'
Z

10 I------f-----+_____

f-

::J

w

0

c:
c:

~

::J
U - 5

BIAS

-10

0-

OFFSET

~

~

fZ

~
W
>

/'"

:3

V

- 15
- 50

@-lL....:~

- 25

0

+25

+50

TEMPERATURE

__.l.__ _ _ _-'--_ _ _ _-L.______'_______J

100Hz 1kHz

10kHz 100kHz lMHz 10MHz
UPPER 3dB FREQUENCY
LOWER 3dB FREQUENCY (10Hz)

+75 +100+125
(OC)

-'
...:

_OPEN LOOP FREQUENCY AND PHASE RESPONSE

ow
~§

120

in

~ 100
;;:

(!l

w 80

(!l

«

~

80

-

>
0-

40

9

20

a: c..

""- ........

'\

-..........

~t

2

PHASE

1

0

Z
W
0-

0

w:;;;
g,...:

1000

'-

0

0

800

r--.....

"" """

(fJ

~800
o
(!l

1'-..

~

\\
1

~400

1

200
1

o

I'...

"'"

..........

- 55 - 35 - 15 +5 +25 +45 +65 +85 +105 +125
TEMPERATURE (oC)

- 20
10Hz 100Hz 1kHz 10kHz 100kHz lMHz 10MHz 100MHz
FREQUENCY (Hz)

OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND

OUTPUT VOLTAGE SWING vs. FREQUENCY

12Or----r----r----.-----r----,----"

in

:g

z

~
w

~

lV~------+--------+--~~~~----~

~

~
0-

o

9
z

W

0-

o
100kHz

lMHz
10MHz
FREQUENCY (Hz)

Ol----~--_+--~----+-~~~~
-20~

O.OW'---------'---------'-----------"'---------'
10kHz

U)

:z a:

INPUT IMPEDANCE vs. TEMPERATURE,100Hz

__

~

____

~

__-'-____L -__

~

____~

10Hz 100Hz 1kHz 10kHz 100kHz lMHz
FREQUENCY (Hz)

100MHz

NOTE:

External Compensation is required for closed loop gain < 5. If
external compensation is used, also connect 1OOpF capacitor from
output to ground.

3-327

10MHz

HA-2620/22/25
Typical Performance Curves

(Continued)

COMMON MODE VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE

>20

I

±!

1

I

- 5s"C::; T A::;+ 125°C

w

,./

~ 15

~

::;
Z

~

../

5

::;

V

V

+ivduppL

V

V

w

810

OPEN LOOP VOLTAGE GAIN VS. TEMPERATURE
120

-

SU~PLY

+15V

--

- - - -r--_ -.t..!OVSUPPLY

- t 5V sup""PLY-

,/

o
u

10

5

15

80
- 55 - 35 -15

20

SUPPLY VOLTAGE (VOLTS)

5

NOISE DENSITY vs. FREQUENCY

1i1Ooo
~w

10

~

45

65

85

105 125

li<
E:
f-

Z

e.!)

<

25

TEMPERATURE (oC)

W

100

a:
a:

0

:::l

>
W
en
az

U

w

0.1

f-

en
az
f-

:::l

:::l

D..

D..

:!:

1
1

10

1K
100
FREQUENCY

10K

0.01
100K

:!:

(Hz)

Test Circuits
TRANSIENT RESPONSE

SLEW RATE

L

±2OOmV_~_
_ _ _
_
9O'KI- - - OUTPUT

:

10%-__

:

OmY

I

1__ RISE TIME

!

SUGGESTED VOS ADJUSTMENT AND COMPENSATION
HOOK-UP

OUT

~
INPUT

w

...':'::Vr---I

ov~

SLEW RATE AND
TRANSIENT RESPONSE

1.6Kst

-w

50pF
9O'IL- -

-

-

OUTPUT
11J'K, _ _ _

- 5V-

I

-

i-

IN

I I1V

-_J_t
r

: :--.6.1 --I SLEW RATE
I I
~ I1Vi aT

Tested Offset Adjustment is

NOTE: Measured on both positive
and negative transistions
from 0 10 +200mV and 0 to
-200mV al oulput.

IvOS +lmV I minimum referred 10
output. Typical range is ±10mV
wilh AT = 100kO.

3-328

HA-2620/22/25
Typical Applications
HIGH IMPEDANCE COMPARATOR

FUNCTION GENERATOR

+15V
2.2kA

~~~--~----~--OVOUT
+S.OV,OV

SOpF*
lN9l6
f=
OUTPUT

VREF

1
4 (R 1+ R2) C

' " OUTPUT

-15V

VIDEO AMPLIFIER

-'

-'--0
+

VOUT

5OpF"

BW= 1MHz
GAIN = 4QdB

'\lT

* A small load capacitance of at least 30pF (Including stray capacitance) is
recommended to prevent possible high frequency oscillations.

Die Characteristics
Transistor Count .....•............................ 140
Ole Dimensions ....................... 73 x 52 x 19 mils
Substrate Potential ........................... Unbiased
Thermal Constants (OC/W)
HA2-Metal Can (-2, -5, -7)
HA2-Metal Can (-8,/883)
HA3-Plastic DIP (-5)
HA4-Ceramic lCC (1883)
HA7-Ceramic DIP (-2, -5, -7)
HA7-Ceramic DIP (-8,/883)

Sja

Sjc

202
161
83
96
204
81

55
48
33
35
112
32

3-329

HA-2640/45

{iHARRIS

High Voltage
Operational Amplifiers

August 1991

Features

Applications

•
•
•
•
•
•
•

•
•
•
•
•

Output Voltage Swing •••••••••••••••••••••••• ±3SV
Supply Voltage •••••••.••••••••••••••• ±10Vto :!:40V
Offset Current •••••••••••••••••••••••••••••••• SnA
Bandwidth ••••••••••••••••••••••••••••••••••• 4MHz
Slew Rate •••••••••••••••••••••••••••••••••••• SV!/lS
Common Mode Input Voltage Swing •••••••••• , ±3SV
Output Overload Protection

Industrial Control Systems
Power Supplies
High Voltage Regulators
Resolver Excitation
Signal Conditioning

Description
HA-2640 and HA-2645 are monolithic operational amplifiers which are designed to deliver unprecedented dynamic
specifications for a high voltage Internally compensated
device. These dielectrically isolated devices offer very low
values for offset voltage and offset current coupled with
large output voltage swing and common mode input
voltage.
For maximum reliability, these amplifiers offer unconditional
output overload protection through current limiting and a
chip temperature sensing circuil. This sensing device turns
the amplifier "off", when the chip reaches a certain
temperature level.
These amplifiers deliver ±35V common mode input voltage
swing, ±35V output voltage swing, and up to ±40V

Pinouts

supply range for use in such designs as regulators, power
supplies, and Industrial control systems. 4MHz gain
bandwidth and 5V//ls slew rate make these devices
excellent components for high performance signal
conditioning applications. Outstanding input and output
voltage swings coupled with a low 5nA offset current make
these amplifiers excellent components for resolver
excitation designs.
The HA-2640/2645 are available in Metal Can (T0-99) or
Ceramic Mini-DIP and can be used as high performance
pin-for-pin replacements for many general performance
amplifiers. HA-2640 is speCified from -550C to +125 0C
and HA-2645 is specified over the OOC to +750C range.

Schematic

HA7-2640/2645 (CERAMIC MINI-DIP)
TOP VIEW
SAl.

COMP

-IN

v+

+IN

OUT

Y-

SAl.

HA2-2640/2645 (TO-99 METAL CAN)
TOPYIEW
CaMP

Y(TO-99 Case Voltage = -V)
CAUTION: These devices are sensitive to electrostatic discharge. Proper
Copyright @ Harris Corporation 1991

I.e. handling procedures should
3-330

be followed.

File Number

2904

Specifications HA-2640/2645
Absolute Maximum Ratings (Note 12)

Operating Temperature Ranges

Voltage Between V+ and V- Terminals •••••.••••••••.••••• 100V
Input Voltage Range •.••.•.•••••••.•••••••.••••• ±1 OV to ±37V
Output Current ••.•.••.••••.•••••••• Full Shorl Circuit Protection
Internal Power Dissipation .•.•••••..•.••..•.••••.•.•• 680mW •
Maximum Junction Temperature ••.•.••.•••••••••.••••• +175 0 C

HA-2640-2 ••••••••••••••••••••••••••.• -550 C ~;TA::; +1250 C
HA-2645-5 ••.•••••••••••••••••••••••••.•• 0 0 C::;TA.:5+75 0 C
Storage Temperature Range •••••••••••.• -6S o C ::; TA :5 +1500 C

*

Derale by 4.6mW;oC above +2SoC

Electrical Specifications VSUPPLY

= ±40V, RL = 5k!1, Unless Otherwise Specified.
HA-2640-2
-SSOC to +12S OC

PARAMETER

TEMP

MIN

HA-264S-5
OCCto+7S o C

TYP

MAX

MIN

2

4
6

-

TYP

MAX

UNITS

2

-

6
7

mV
mV

15
12

-

~VfJC

30

nA

-

50

nA

30
50

nA

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current

+25 0 C
Full
Full
+25 0 C

Input Resislance (Note 10)
Common Mode Range

15
10

50
±35

5
250
-

+250 C
Full

100K

200K

Full
+250 C

80
1

Full
Offset Current

-

+250 C
Full
+250 C
Full

-

-

-

25

-

50
12

40
±35

200
-

100K

200K

75K

-

74

100

35

-

15

-

nA
Mn
V

-

VN

-

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 8)
Common Mode Rejection Ratio (Note 1)
Minimum Stable Gain
Unity Gain Bandwidth (Note 2)

75K

+250 C

-

-

100

4

-

1

-

-

VN
dB

4

-

VN
MHz

-

-

kHz

100

ns

-

-

OUTPUT CHARACTERISTICS
Full

±35

-

Output Current (Note 9)
Output Resistance

+250 C
+250 C

±12

±15

-

Full Power Bandwidth (Notes 3 & 11)

+250 C

500
23

-

Output Voltage Swing

-

±35
±10

-

±12
500
23

V
mA
n

TRANSIENT RESPONSE (Nole 7)
60
15

-

:1:2.5

:1:5

3.8
:1:40

-

3.2

:1:10

-

-

74

90

Rise Time (Notes 4 & 6)

+25 0 C

100

+25 0 C

-

60

Overshoot (Notes 4 & 6)

15

30

Slew Rate (Note 6)

+25 0 C

:1:3

:1:5

+25 0 C
Full

-

3.2

:1:10

-

Full

80

90

40

-

%
V/~s

POWER SUPPLY CHARACTERISTICS
Supply Current
Supply Voltage Range
Power Supply Rejection Ratio (Note 5)

4.5
:1:40

-

NOTES:

= :l:20V
= 90mV
VOUT = :l:35V
VOUT = :l:200mV
Vs = :l:10V 10 :l:40V

1. VCM

9. RL

= 1kO

2. YOUT

10. This parameter based upon design calculations.

3.

11. Full Power Bandwidth guaranteed based upon slew rate measurement:

4.
5.

6. AV= +1

FPBW = S,R.l2nVpEAK; VpEAK = 35V.

12. Absolute Maximum Ratings are limiting values applied individually
beyond which the serviceability of the circuit may be impaired. Functional operalion under any of these conditions is not necessarily implied.

7. CL = 50pF. RL = SkO

B. VOUT = :l:30V

3-331

mA
V
dB

-'
c:(U)

z a:

OW

~§

a: c..
w::

~c:(

HA-2640/2645
Typical Performance Curves

v+

= v- = 40V D.C., TA = +250 C, Unless Otherwise Specified.

INPUT BIAS AND OFFSET CURRENT vs. TEMPERATURE
25

INPUT NOISE CHARACTERISTICS

~1000

<.:.

.:.

15

I-

zw

II:
II:

10

w
C!l 100
..:

1\

5

BIAS CURRENT

OFFjET CUrENT
0
- 50

II:
II:

B

0

o

- 25

- """

+ 25
+ 50
+ 75
TEMPERATURE (OC)

+ 100

w

Ul

0

w

Ul

oz

10

Z
I:::J

~

0..

3:

l!~
!zw

>

'~ r--...

C)

10

:;

I\.'\ "-

:::J

mmllD.1II
~

;;;
20

3:

1
1

100

10

10K

lK

lOOK

FREQUENCY (Hz)

+ 125

NORMALIZED AC PARAMETERS vs. TEMPERATURE

OPEN LOOP FREQUENCY AND PHASE RESPONSE
00

1.4

1.2

1.0

~

~

SLEWRAT~ r--......
BAN;:;~

.8

- 50

""""'"""'

&r 120

:;!.

- 25

o

it 25

+50
+75
TEMPERATURE (oC)

,

+100

80

~

-.

!:i

40

~

0

~

+125

PHASE

~

GA~

w

~ "-.

~

.....--...
r-.....

1\

r-\

~ -40
10

100

lK

10K
lOOK
FREQUENCY (Hz)

1M

2700
10M

OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND

NORMALIZED AC PARAMETERS vs.
SUPPLY VOLTAGE· AT +250 C

g+.

r".
~

1.2

~

iii
a:
a:
~
w
a:

1.1
SLEWRAT~

w 1.0

'~"

I
o
Z

.9

o

9
~

/'

20

80

;;:
~ 40~----~----~~~~~~~

z:~ ~
/

.8
10

~
z

0

o
40~----~----~----+-----+-----+---~~

30

40

SUPPLY VOLTAGE (VOLTS)

10

100

lK

10K
lOOK
FREQUENCY (Hz)

1M

10M

NOTE: External Compensation Components are not required for stability,
but may be added to reduce bandwidth if desired. If External Compensation is used, also connect 100pF capacitor from output to
ground.

3-332

HA-2640/2645
Typical Performance Curves (Continued)
OUTPUT VOLTAGE SWING vs. FREQUENCY AT +25 0 C

OUTPUT CURRENT CHARACTERISTIC

'00
AV= 1, VSUPPLY
VSUPPLY -

t

40V

VSUPPLY""

t

20V

VSUPPLY =

t

lOY

=t

VIN=

40
40V

+ 35V
30

"""'~

20
AVe 1, VSUPPLY =
V,N",

-+~\C
I
I
.\~OC
\'\.OC

-~

-20

-15

\11/1 III
\.
J
1

""" ~
~

.••0C

I
I

~ 15V

..I

-10

+,~.OC r~'OC/-~'°cf

+ 20V
'0

I
I

I

/I 1/ /11

.,.

0
5 .L'O'1~250~i-5
/..0," .10/
oc

+ 1250 C

AV= 1.VSUPPLY ..
V,N", -15V
·2.

t

20V

2Stt/+ 1250C
·3.
AV= 1, VSUPPLY ..

o.,

t

40V

Y,N= -35V

10K

,K

·4.

,M

lOOK
FREQUENCY (Hz)

OUTPUT LOAD CURRENT (rnA)

...J

SUPPLY CURRENT vs. SUPPLY VOLTAGE

OUTPUT VOLTAGE SWING vs. SUPPLY VOLTAGE

>'

2.5

<'

g

2.0
1.5

~

1.0

+1

W

w

-1.0

W -2.0
- 2.5
10

-ICC

~

o

~

-20

15

20

25

SUPPLY VOLTAGE

30

35

40

I

+VOUT

----~

10

~ -10

g; -1.5

-30

-40
10

---15

20

-~
-VOUT
25

SUPPLY VOLTAGE

(± V)

3-333

,.,,-.-

40

i : -----I"'"

+ICC

~ 0.5
;:) 0.0
U -0.5

~

TA:S.+75 0 C
HA-2839-9 ••••••••••••••••••••••.••.••• -4ooC !> TA :S. +850 C
Storage Tempsrature Range •••••.••••.•• -65°C :S. TA:S. +1500 C

VSUPPLY = :l:l5V, RL = lkO, CL ~ 10pF, Unless Otherwise Specified.
HA-2839-5, -9

PARAMETER

TEMP

MIN

TYP

MAX

UNITS

+250 C

-

0.6

2

mV

2

6

mV

20

-

..V!OC

5

14.5

8

20

J1A
J1A
J1A
J1A

INPUT CHARACTERISTICS
Offset Voltage

Full
Average Offset Voltage Drift
Bias Current

Full
+250 C
Full

Offset Current

+25 0 C
Full

-

Input Resistance

+250 C

Input CapaCitance

+250 C

-

Common Mode Range

Full

:1:10

Input Noise Voltage
(f 1kHz, RSOURCE
Input Noise Current
(f 1 kHz, RSOURCE

+250 C

1

4

-

8

6

-

nVl..jHZ

6

-

pN..jHZ

10
1

-

kO
. pF
V

+250 C

-

+250 C

20K

25K

Full

15K

20K

Full

75

80

Minimum Stable Gain

+25 0 C

10

-

-

VN

Gain Bandwidth Product (Notes 5 & 12)

+250 C

-

600

-

MHz

=

=00)

=

=10kO)

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)
Common-Mode Rejection Ratio (Note 4)

-

VN
VN
dB

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 3)

Full

:1:10

Output Current (Note 3)

Full

. :1:10

-

-

V

:1:20

-

mA

Output Resistance

+250 C

-

30

Full Power Bandwidth (Notes 3 & 7)

+250 C

8.7

10
0.03

-

Differential Gain (Notes 6 & 11)

+250 C

-

0.03

Differential Phase (Notes 6 & 11)

+250 C

-

Degrees

4

-

ns
VIliS

0
MHz
%

TRANSIENT RESPONSE (Note 8)
RiseTime

+25 0 C

Overshoot

+250 C

-

20

Slew Rate (Notes 3 & 10)

+250 C

550

625

Settling Time: 10V Step to 0.1 %

+250 C

-

180

-

%

ns

POWER REQUIREMENTS
Supply Current

Full

-

13

15

rnA

Power Supply Rejection Ratio (Note 9)

Full

75

90

-

dB

3-336

HA-2839
NOTES:
1. Absolute maximum ratings are limiting values. applied individually. beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.
2. This value assumes a no load condition: Maximum power dissipation
with load conditions must be designed to maintain the maximum junction
temperature below +175OC for ceramic packages and below +150oC
for plastic packages.
3. RL = 1kO. Vo = ±10V. 0 to ±10V for slew rate.

7. Full Power Bandwidth guaranteed based on slew rate measurement
using FPBW =

Slew Rate

; VpEAK = 10V

2nVpEAK
B. Refer to Test Circuit section of data sheet.
9. VSUPPLY = ±10VDC to ±20VDC.
10. This parameter is not tested. The limits are guaranteed based on lab
characterization, and reflect lot-Io-Iot variation.
11. Differential gain and phase are measured with a VM700A video tester,
using a NTC-7 composite VITS.

4. VCM = ±10V.

5. Vo = 90mV.

12. AV = +100.

6. AV = +10.

Test Circuits
TEST CIRCUIT
IN 0----1

>-t---oOUT
Vs = ±15V
AV= +10
CL < 10pF

.....

-_--0

OUT
Vs

~

±15V

AV =+10
CL

< 10pF

loon

SETTLING TIME TEST CIRCUIT

• AV = -10

INPUT

• Load Capacitance should be less than 1OpF.
• It is 'ecommended that resistors be carbon composition and that feedbacit and summing network ratios be matched to 0.1 %.
• SETTLING POINT (Summing Node) capacitance should be less than
10pF. For optimum settling time results. it is recommended that the test
circuit be constructed directly onto the device pins. A Tektronix 568 Sampling Oscilloscope with S-3A sampling heads is recommended as a settle
point monitor.

v21m
SETTLING
POINT

3-340

HA-2841

;)HARRIS
PRELIMINARY

Wideband, Fast Settling, Unity Gain Stable,
Video Operational Amplifier

May 1991

Features

Applications

• Low Supply Current ••••••••••••••• _••••••••• 10mA

• Pulse and Video Amplifiers

• Unity Gain Bandwidth •••••••.•••••••••••••• 54MHz
• High Slew Rate ••••••••••••••••••••••••••••

240V/~s

• Wideband Amplifiers
• High Speed Sample-Hold Circuits

• Low Offset Voltage •••••••••••••••••.•••••••••• 1mV

• Fast, Precise DIA Converters

• Fast Settling Time (0.10/0) ••••••••••••••••••••• 90ns

• High Speed AID Input Buffer

• Full Power Bandwidth •••••••••••••••••••••• 3.BMHz
• Differential GainlPhase ••••••••••••• , • •0.03%10.03 0
• Enhanced Replacement for ADB41 and EL2041
--'
83

0
MHz
%
Degrees
dB

TRANSIENT RESPONSE (Note 8)

-

33

-

-

240
gO

-

V/JIS
ns

-

10

-

mA

Full

10

11

mA

Full

70

80

-

dB

Slew Rate (Note 12)

+250 C
+250 C
+250 C

200

Settling Time:

+250 C

+250 C

Rise Time
Overshoot
1 OVStep to 0.1%

3

ns
%

POWER REQUIREMENTS
Supply Current
Power Supply Rejection Ratio (Note 9)

3-342

HA-2841
NOTES:
1. Absolute maximum ratings are limiting values, applied individually. beyond which the serviceability of the circuit may be impaired. Functional
operability under' any of these conditions Is nol necessarily Implied.

2. Differential gain and end phase are measured with a VM700A video
tester, using a NTC-7 composite VITS. RF = Rl = lK, RL = 700n.

3. Vo = ±10V.

4. VCM = ±10V.
5. AVCL

:::I

8. Refer to Test Circuit section of data sheet.

9. VSUPPLY = ±1 OVDC 10 ±20VDC.
10. Vo = 2Vp-p; f = 1MHz; AV = +1.
11. Maximum power dissipation, including output load, must be designed to
maintain tho maximum junction temperature below +1750 C for ceramic
packages, and below +150 oC for the plastic packages.

+1. This parameter is not tested. The limits are guaranteed based
on lab characterization, and reflect lol-Io-Iot variation.

12. AV =

1000, Measured at unity gain crossing.

6. Va = ±10, RL unconnected. Output duty cycle must be reduced if lOUT
> 10mA.
7. Full Power Bandwidth guaranteed based on slew rata measurement
using FPBW

= Slew Rate ; VpEAK = 10V
2nVpEAK

Test Circuits
TEST CIRCUIT

SETTLING TIME TEST CIRCUIT

SETIUNG
POINT

Vs = ±15V
AV=+1
CL < 10pF

v+
~-_-OVOUT

V• AV =-1
• Feedback and summing resistors must be matched (0.1%).

• HP5082-2810 clipping diodes recommended.
• Tektronix P6201 FET probe used at settling point.

Die Characteristics
Transistor Count .••...••................••.•....••• 43
Die Dimensions ..................••... 7.7x81 x.19 mils
(19601lm x 2060llm x 4851lm)
Substrate Potential·......••...•...•.....•••..•...••. v.Process ..••.•...•.•.•....... High Frequency Bipolar~DI'
Thermal Constants (OC/W)
9ja
9jc
HA3B28'41, Plastic DIP
89
28
HA9P2841,SOIC·
157
42
HA3-2841, Plastic Minl~DIP
92"
30'
*The subslrale may be lell floaling (Insulaling Die Mounl) or it may be
mounted on a conductor aI V- potential~

3-343

m

HA-2842

HARRIS

PRELIMINARY

Wideband, High Slew Rate, High Output Current,
Video Operational Amplifier

August 1991

Features

Applications

• Stable at Gains of 2 or Greater

• Pulse and Video Amplifiers

• Gain Bandwidth. • • • • • • • • • • • • • • • • • • • • • • • • • •• 80MHz

• Wideband Amplifiers

• High Slew Rate •••••••••••••••••••••••••••• 400Vl/Js

• Coaxial Cable Drivers

• High Output Current (Min) •••••••••••••••••• 100mA

• Fast Sample-Hold Circuits

• Differential Gain/Phase •••••••••••••••• 0.02%/0.030

•

High Frequency Signal Conditioning Circuits

• Low Supply Current (Max) ••••••••••••••••••• 1SmA
• Low Input Offset Voltage •••••••••••••.•••••••• 1mV
• Enhanced Replacement for AD842

Description
The HA-2842 is a wideband, high slew rate, monolithic
operational amplifier featuring an outstanding combination
of speed, bandwidth, and output drive capability.
Utilizing the advantages of the Harris D. I. technology this
amplifier offers 400V//Js slew rate, 80MHz gain bandwidth,
and ±100mA output current. Application of this device Is
further enhanced through stable operation down to closed
loop gains of 2.
For additional flexibility, offset null controls are Included in
the HA-2842 pinout.
The capabilities of the HA-2842 are Ideally suited for high
speed coaxial cable driver circuits where low gain and high
output drive requirements are necessary. With 6MHz full

Pinouts
HA3B2842 (PLASTIC DIP)
TOP VIEW

power bandwidth, this amplifier is most suitable for high
frequency signal conditioning circuits and pulse video
amplifiers. Differential gain and phase are a low 0.02% and
0.03 degrees, respectively, making the HA-2842 ideal for
video applications.
The HA-2842 is available in a Plastic 14 lead DIP package,
which is pin compatible with the HA-2542 and AD842. The
HA-2842 is also available In PlastiC 8 Lead DIP and SOIC
packages. See the "Ordering Information" section below for
more Information.
For information about using high output current operational
amplifiers, please refer to Application Note 556 (Thermal
Safe-Ope rating-Areas For High Current Op Amps). Please
refer to the /883 data sheet for military compliant product.

HA3-2842 (PLASTIC DIP)
HA9P2842 (SOIC)
TOPV1EW

Ordering Information
PART
NUMBER

TEMPERATURE
RANGE

HA3B2842-5

OOClo+750C

14 Pin Plastic DIP

HA3~2842-5

OOClo+750C.

8 Pin Plastic DIP

HA9P2842-5

OOClo+750C

8PinSOlC

HA3B2842-9

-400C 10 +850C

14 Pin Plasllc DIP

HA3-2842-9

-400C 10 +850C

8 Pin Plaslic DIP

HA9P2842-9

-400C 10 +850 C

8 Pin SOIC

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-344

PACKAGE

File Number

2766.2

Specifications HA-2842
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage between V+ and V- Terminals •••••.•••.••••••••.•.• 35V
Differential Input Voltage ••••••••••.•••.•..••.••••••••••••. ±6V
Output Current ...••••.••.••.•••.••••.••.••.•••• 125mA (Peak)
100mA (50% Duty Cycle)
Maximum Junction Temperature (Note 11) ••.••••.••••.• +1750 C
Maximum Junction Temperature (Plastic Packages) •••.• +1500 C

HA-2842-5 •••.••••••••••.•..•••••••••••.• 00C:5 TA:5+750 C
HA-2842-9 •••••.••••••••.••••••••.••.•• -400C :5 TA:5 +850 C
Storage Temperature Range .•••.•••••••. -650 C $TA:S; +150 oC

Electrical Specifications VSUPPLY = ±15 Volts; RL = 1kO, CL:5 10pF, Unless Otherwise Specilied.
HA-2842-5/-9
TEMP

PARAMETER

MIN

TYP

MAX

UNITS

-

1

3

-

6

mV
mV

-

"VloC

10
15

IlA
IlA

INPUT CHARACTERISTICS

Average Offset Voltage Drift
Bias Current

+250C
Full
Full
+250C

Average Bias Current Drift
Offset Current

Full
Full
+250 C

Offset Voltage

Full
Full
+250 C

Average Offset Current Drift
Input Resistance
Input Capacitance
Common Mode Range
Input Noise Voltage (10Hz to 1 MHz)

=
=

=
=

Input Noise Voltage Density (10 1kHz, RS 00)
Input Noise Currant Density (10 1kHz, RS 100kO)

+25OC
Full
+250 C
+250 C
+250C

-

-

±10

13
5

20
0.5

1.3
170
1

-

-

16

-

16
2

-

-

nAfOC

1.0
1.5

IlA
IlA

-

nAfOC
kO
pF
V
"Vrms
nVly'Hz
pNy'Hz

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)
Common-Mode Rejection Ratio (Note 4)
Minimum Stable Gain
Gain-Bandwidth-Product (Note 5)

-

+250 C
Full
Full
+250C
+250C

50k
30k
80
2

100k
60k
110

-

80

-

Full
Full
+250 C
+250 C
+250 C

±10
100

±11

-

-

8.5
6
0.02
0.03
>81

-

-

VN
VN
dB
VN
MHz

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 3)
Output Current (Note 6)
Output Resistance
Full Power Bandwidth (Note 3 & 7)
Differential Gain (Note 2)
Differential Phase (Note 2)
Harmonic Distortion (Note 10)

+25OC
+250C

5.2

-

-

-

-

V
mA
0
MHz
%
Degrees
dB

TRANSIENT RESPONSE (Note 8)
RiseTime

Overshoot
Slew Rate (Note 12)
Settling Time:
10VSteptoO.1%

+250C
+250C
+250C
+250C

325

-

-

4
25
400
100

-

14.2
14.3
80

15

-

ns
%

VlJls
ns

POWER REQUIREMENTS
Supply Current
Power Supply Rejection Ratio (Note 9)

+250 C
Full
Full

3-345

70

-

-

mA
mA
dB

HA-2842
NOTES:

1. Absolute maximum ratings are limiting values. applied individually.
beyond which the serviceabDity of the circuit may be impaired. Functional
operability under any of these conditions Is not necessarily Implied.

2. Differential gain and phase are measured with a VM700A video tester,
using a NTC-7 composil. VITS. RF = Rl = lK. RL = 7000.

3. RL = lkO. Vo = ±10V
4. VCM

=±10V

5. AVCL = 100
6. Vo = ±5V. RL Unconnected
7. Full Power Bandwidth guaranteed based on slew rate measurement uSing

FPBW

=

Slew Rat.

= 10V

; VpEAK

10. Vo = 2Vp _p; I = lMHz; AV = +2.
11. This value assumes a no load condition: Maximum power dissipation,
Including output load, must be designed 10 maintain the maximum june·
tion temperature below +175 0C for ceramic packages. and below
+1500 C lor plastic packages. By using Applicalion Note 556 on Safe
Operating Area equations. along with the packaging thermal resistances
listed in the Die Characteristics section, proper load conditions can be
determined. Heal sinking is recommended above +7SoC with suggested
models:
14 Lead Ceramic OIP:
Thermalloy #6007 or AAVIO #5602B (Osa = 160 CIW).
12 Lead Melal Can (TO-B):
Therm.lloy #224OA (O.a = 270 CIW) or #226BB (Osa = 24OClW)
12. AV =- +2. this parameter Is not tested. The limits are guaranteed based
on lab characterization and reflect lol-to-Iot variation.

2nVpEAK
8. Refer to Test Circuits section of this data sheet.

9. VSUPPLY = ±10VOC to ±20VOC

Test Circuits

Die Characteristics
TEST CIRCUIT

IN

Transistor Count ................................... 43
Die Dimensions ....................... 77 x 81 x 19 mils
(1960",m x 2060",m x 485",m)
Substrate Potential* ................................ vProcess .••..•.•..•..••••.... High Frequency Blpolar-DI
Passivation. . . • . . • • . . . . . . . . . . . . . • . • • . • • • • . . . • •. Nitride
Thermal Ccmstants (OC/W)
Sja
Sjc
HA3B2842 Plastic DIP
89
28
HA3-2842 Plastic Mini-DIP
92
30
HA9P2842 SOIC
157
42

OUT

500.0.

Vs = ±15V
AV=+2
CL :>.10pF

500.0.

*The substrate may be left noatlng (Insulating Die Mount) or it may be
mounted on a conductor at V- potential.

Typical Applications
SETTLING TIME TEST CIRCUIT

SEnUNG
POINT

2.Sk.n.

Primarily Intended to be used In balanced 500 and 750
coaxial cable systems as a driver, the HA-2842 could also
be used as a power booster in audio systems as well as a
power amp in power supply circuits. This device would also
be suitable as a small DC motor driver.

Sk.n.

1k.n.

5OO.n.

The Harris HA-2842 is a state of the art monolithic device
which also approaches the "ALL-IN-ONE" amplifier
concept This device features an outstanding set of AC
parameters augmented by excellent output drive capability
providing for suitable application in both high speed and
high output drive circuits.

v+

Prototyping Guidelines
For best overall performance in any application. it is
recommended that high frequency layout techniques be
used. This should include: 1) mounting the device through a
ground plane: 2) connecting unused pins (N.C.) to the
ground plane: 3) mounting feedback components on Teflon
standoffs and/or locating these components as close to the
device as possible; 4) placing power supply decoupling
capacitors from device supply pins to ground.

v• Av =-2
• Feedback and summing resistors must be matched (0.1%)
• HPS082-2810 clipping diodes recommended
• Tektronix P6201 FET probe used at settling point
• For 0.01 % settliing time, heat sinking is suggested to reduce thermal
effects and an analog ground plane with supply decoupling is suggested
to minimize ground loop errors.

3-346

HA-2850

mHARRIS
PRELIMINARY
August 1991

Low Power, High Slew Rate, Wide band
Operational Amplifier
Applications

Features
• Low Supply Current ••••••••••••••••••••••••• 7.5mA

• Pulse and Video Amplifiers

• High Slew Rate ••••••••••••••.••••••••••••• 340V/IlS

• Wideband Amplifiers

• Open Loop Gain •••••••••••••••••••••••.•••• 25kVN

• High Speed Sample-Hold Circuits

• Wide Gain-Bandwidth (AV ~ 10) ••••••••••• 470MHz

• Fast, Precise D/A Converters

• Full Power Bandwidth •••••••••••••••••••••• 5.4MHz
• Low Offset Voltage •••••••••••••••••••••••••• 0.6mV
• Input Noise Voltage ••••••••••••••••••• 11.0nV/yIHz
• Differential Gain/Phase ••••••••••••••• •0.040/0/0.040
....I

«en

• Lower Power Enhanced Replacement for AD840 and
EL2040

:z a:
OW

!;i~
D.

a:

w:;;;
~«

Description
The HA-2850 Is a wideband, high slew rate, operational
amplifier featuring superior speed and bandwidth charac'
teristics. Bipolar construction, coupled with dielectric
isolation, delivers outstanding performance in circuits with a
closed loop gain of 10 or greater.

A 340VlllS slew rate and a 470MHz gain bandwidth product
ensure high performance in video and wideband amplifier
designs. Differential gain and phase are a low 0.04% and
0.04 degrees respectively, making the HA-2850 ideal for
video applications. A full ±10V output swing, high open

Pinouts
HA1-28S0 (CERAMIC DIP)
HA3B28S0 (PLASTIC DIP)
TOP VIEW

loop gain, and outstanding A.C. parameters, make the HA2850 an excellent choice for high speed Data Acquisition
Systems.
The HA-2850 is available in commercial and industrial
temperature ranges, and a choice of packages. See the
"Ordering Information" section below for more information.
For military grade product, refer to the HA-2850/883 data
sheet.

HA7-28S0 (CERAMIC DIP)
HA3-2850 (PLASTIC DIP)
HA9P28S0 (SOIC)
TOP VIEW

(N.C.) No Connection pins may be tied to a ground plane for better isolation
and heat dissipation.

Ordering Information
PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

HA1-28S0-5

oOCto+750 C

14 Pin Ceramic DIP

HA3B2850-S

oOCto+750 C

14 Pin Plastic DIP

HA7-2850-5

oOCto+750 C

8 Pin Ceramic DIP

HA3-2850-5

oOCto+75 0 C

8 Pin Plastic DIP
8PinSOlC

HA9P2850-5

oOCto+750 C

HA1-2850-9

-400 C to +850 C

14 Pin Ceramic DIP

HA3B2850-9

-400 C to +85 0 C

14 Pin Plastic DIP

HA7-2850-9

-40 0 C to +850 C

8 Pin Ceramic DIP

HA3-2850-9

-400 C to +850 C

8 Pin Plastic DIP

HA9P2850-9

-40 0 C to +S50 C

SPinSOIC

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @) Harris Corporation 1991

3-347

File Number

2844.1

Specifications HA-2850
Absolute Maximum Ratings

Operating Temperature Range

(Note 1)

Voltage Between V+ and V- Terminals ••••••••••••••••••••• 35V
Differentiallnput Voltage •••••••••••••••••••••••••••••••••• ±6V
Maximum Junction Temperature ••••••••••••.•..•.••.•. +1750 C
Maximum Junction Temperature (Plastic Packages) ••••. +1500 C

Electrical Specifications

VSUPPLY

HA-2850-5 ••••••••••••••••••••••••••••.•• COC:$ TA :$ + 75°C
HA-2850-9 ••••••••••.••••.••••••••••.•• -4COC :$ TA :$ +850 C
Storage Temperature Range •••••••••••.• -650C:$ TA :5 +1500 C

= ±15V. RL = 1kO. CL :$10pF. Unless Otherwise Specified.
HA-2850-5, -9

PARAMETER

TEMP

MIN

+250 C

TYP

MAX

UNITS

0.6

2

mV

2

6

mV

20

-

I'V{JC

5

14.5

8

20

INPUT CHARACTERISTICS

Input Resistance

+250 C

Input Capacitance

+250 C

-

Full

:1:10

Input Noise Voltage
(fo = 1 kHz. RSOURCE = 00)

+250 C

Input Noise Current
(10 = 1kHz. RSOURCE = 10kO)

+250 C

-

+250 C

20K

25K

Full

15K

20K

-

Full

75

80

-

Minimum Stable Gain

+250 C

10

Gain Bandwidth Product (Notes 5 & 11)

+250 C

-

470

Output Voltage Swing (Note 3)

Full

:1:10

±11

Output Current (Note 3)

Full

:1:10

:1:20

Offset Voltage

Full
Average Offset Voltage Drift
Bias Current

Full
+250 C
Full

Offset Current

+250 C
Full

Common Mode Range

1

4

-

8

JJA
JJA
JJA
JJA

-

kO

10
1

11
6

-

pF
V
nVly'Ffz
pNy'l1z

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 3)
Common-Mode Rejection Ratio (Note 4)

VN
VN
dB

-

MHz

-

mA

VN

OUTPUT CHARACTERISTICS
V

Output Resistance

+250 C

-

30

-

0

Full Power Bandwidth (Notes 3 & 7)

+250 C

4.8

5.4

MHz

Differential Gain (Notes 2 & 6)

+250 C

Differential Phase (Notes 2 & 6)

+250 C

-

-

0.04

-

%

0.04

-

Degrees

TRANSIENT RESPONSE (Note 8)
RlseTime
Overshoot
Slew Rate (Notes 3 & 10)
SeltiingTime: 1OVStep to 0.1%

+250 C
+250 C
+250 C
+250 C

-

5

-

25

300

340

-

200

-

ns
%
VII's
ns

POWER REQUIREMENTS
Supply Current

Full

-

7.5

8.0

mA

Power Supply Rejection Ratio (Note 9)

Full

75

90

-

dB

3-348

HA-2850
NOTES:
1. Absolute maximum ratings are limiting values. applied individually. b9~
yond whIch the serviceabilily of the circuit may be impaired. Functional

7. Full Power Bandwidth guaranteed based on slew rate measurement

using FPBW =

operability under any of these conditions is not necessarily implied.

Slew Rale

; VPEAK = 10V

2nVpEAK

2. Differential gain and end phase are measured with a VM700A video
tester. using a NTC-7 composite VlTS.

8. Refer to Test Circuit section of data sheet.
9. VSUPPLY = ±10VDC 10 ±20VDC.

3. RL = lkO. Vo = ±10V. 0 10 ±10V fo' slew ,ale.

10. This parameter is not tested. The limits are guaranteed based on lab

4. VCM = ±10V.

characterization, and reflect lot-Io-Iot variation.

5. Vo =90mV.

11. AV = +100.

6. AV=+10.

Test Circuits
TEST CIRCUIT

IN 0----1

>-+---0

OUT

Vs = ±15V
AV = +10
CL < 10pF

.....
«00
za:

OW

~§
w~
&«

SETTLING TIME TEST CIRCUIT

V+

-:h

INPUT

• AV = -10

OUTPUT

O--<~Nv-_--I

• Load Capacitance should be less than 10pF.
• It is recommended that resistors be carbon composition and that feed-

back and summing network ratioS be matched to 0.1%.
• SETTLING POINT (Summing Node) capacitance should be less Ihan
10pF. For optimum settling time results, it is recommended that the test
circuit be constructed directly onlo the device pins. A Tektronix 568 Sampling Oscilloscope with 5-3A sampling heads is recommended as a settle
point monitor.

V-

2Kn.
SETTUNG
POINT

3-349

mHARRIS

HA-4741

August 1991

Quad Operational Amplifier

Features

Applications

•
•
•
•
•
•
•
•

•
•
•
•

Slew Rate •••••••••••••••••••••••••••••••••• 1.GV/lls
Bandwidth ••••••••••••••••••.•••••••••••••• 3.SMHz.
Input Voltage Noise .••••••.•••••••••.•••• 9nVly'Hi
Input Offset Voltage .•••••••••••••••.•••••••• O.SmV
Input Bias Current ••.••••••••••••••••••••••••• GOnA
Supply Range ••••••••••••••••••••••••• ±2V to ±20V
No Crossover Distortion
Standard Quad Pinout

Universal Active Filters
03 Communications Filters
Audio Amplifiers
Battery-Powered Equipment

Description
HA-4741, which contains four amplifiers on a monolithic
chip, provides a new measure of performance for general
purpose operational amplifiers. Each amplifier in the
HA-4741 has operating specifications that equal or exceed
those of the 741-type amplifier in all categories of
performance.
HA-4741 is well suited to applications requiring accurate
signal processing by virtue of its low values of input offset
voltage (O.5mV), input bias current (60nA) and input voltage
noise (9nVly'HZ at 1kHz). 3.5MHz bandwidth, coupled with
high open-loop gain, allow the HA-4741 to be used in des·
igns requiring amplification of wide band signals, such as
audio amplifiers. Audio application is further enhanced by
the HA-47 41 's negligible output crossover distortion.

Pinouts

These excellent dynamic characteristics also make the
HA-4741 ideal for a wide range of active filter designs.
Performance integrity of multi-channel designs is assured
by a high level of amplifier-to-amplifier isolation (108dB at
10kHz).
A wide range of supply voltages (±2V to ±20V) can be used
to power the HA-4741, making it compatible with almost
any system Including battery-powered equipment.
The HA-4741 Is available in plastic or ceramic 14 lead DIP
packages. The HA-4741-2 operates from -550 e to
+1250 e and the HA-4741-5 operates over the ooe to
+ 750 e temperature range. HA-4741/883 product and data
sheets available upon request. This device is also offered in
a 16 pin sale package with -5 or -9 temperature options.

Schematic

HA1-4741 (CERAMIC)
HA3-4741 (PLASTIC)
TOP VIEW

.. ~~--;E~~--------t---~
+VIN

-YIN

HA9P4741 (SOIC)
TOP VIEW
OUT4

-1N4

+IN4

..

v+IN3
-IN3
OUT3

Y. HA-4741
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-350

File Number

2922

Specifications HA-4741
Absolute Maximum Ratings (Note 13)

Operating Temperature Ranges

TA = +250 C Unless Otherwise Stated
Voltage Between V+ and V- Terminals .•••.••.•.•.•••.•.•• 40.0V
Differential Input Voltage '" ..•.•....••.••.....••.••••.• "30.0V
Input Voltage (Note 1) ••.•..••..•..••..••.......•..•••.• "15.0V
Output Short Circuit Duration (Note 2) ....•..••...••...•• Indefinite
Power Dissipation For Plastic Package (Note 3). . • . . . . • . .• SSOmW

HA-4741-2 ......••..••..••.••...••••.. -55 0 C.=:;TA:;::+1250 C
HA-4741-5 •••••.•.••••.••.••.•.••.••.•..• OOC:;::TA'=:;+750 C
HA-4741-9 ..•••.•.•....•••..••...... '" -400 C.:<;TA:;::+S50 C
Storage Temperature Range •..••..•..•... -65 0 C':;: TA :;:: +150o C

Electrical Specifications

V+ = +15V, V- = -15V, Unless Otherwise Specified.

HA-4741-2
PARAMETER

TEMP

MIN

TYP

+250 C

-

(NOTE 14)
HA-4741-9

HA-4741-5
MAX

MIN

TYP

0.5

3
5

-

1

4

4

5

-

5

MAX

MAX

UNITS

5

5

mV

6.5

S.5

-

mV

-

60

300

300

I'VflC
nA

-

400

400

nA

30

50

50

nA

....I
oe(U)

-

100

100

-

nA

OW

-

MO
nV/yIHz

-

-

VN

-

-

INPUT CHARACTERISTICS
Offset Voltage

Full
Average Offset Voltage Drift
Bias Current

Full
+250 C

Offset Current

Full
+250 C

Common Mode Range

-

Full

-

60

200

-

325

15

30

-

75

-

Full

.. 12

+250 C
+250 C

-

0.5

Large Signal Voltage Gain (Notes 4)

+250 C

50K

lOOK

25K

-

Common Mode Rejection Ratio

Full
+250 C

SO

95

Full

74

-

+250 C
+250 C

90

lOS

2.5

3.5

Full

.. 12

..13.7

Full
-+250 C

.. 10

..12.5

14

25

Differential Input Resistance
Input Voltage Noise (f = 1 kHz)

-

9

-

-

.. 12

-

-

0.5

25K

50K

15K

-

SO

95

9

Z

~~
w::;;

V

TRANSFER CHARACTERISTICS

Channel Separation (Note 5)
Small Signal Bandwidth

-

-

VN
dB

74

-

90

lOS

2.5

3.5

..12

.. 13.7

..10

:1:12.5

14

25

.. 5

.. 15
300

-

-

mA

-

-

75

140

140

ns

25

40

40

%

:1:1.6

-

-

VII's

-

5

7

7

mA

SO

95

-

-

dB

dB

-

dB
MHz

OUTPUT CHARACTERISTICS
Output Voltage Swing (RL = 10K)
(RL =21<)
Full Power Bandwidth (Notes 4 & 9)

-

-

Full

.. 5

:1:15

+250 C

-

300

-

+250 C
+250 C

-

75

140

Overshoot (Note 11)

25

40

Slew Rate (Note 12)

+250 C

-

..1.6

-

+250 C

-

4.5

5

Full

SO

95

-

1. For supply voltages less lhan ±15V, the
input voltage is equal to the supply voltage.

absolute

maximum

Output Current (Note 6)
Output Resistance

-

V
V
kHz

0

TRANSIENT RESPONSE (Note 7 & 10)
Rise Time (Note 11)

-

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note S)
NOTES:

2. One amplifier may be shorted to ground indefinitely

9. Full power bandwidth guaranteed
measurement FPBW = S.R./2n VpEAK
10. RL = 2K, CL = 50pF

3. Derate 5.8mWfOC above TA = +2500

11. VOUT = ±200mV

4. VOUT = ±10. RL = 2K

12. VOUT = ±5V

5. Referred to Input: f

= 10kHz, RS = 1 K

6. VOUT = ..10
7. See Pulse Response Characteristics

8. l>.V = ..5V

based

upon

slew

rate

13. Absolute maximum ratings are limiting values, applied individually beyond
which the serviceability of the circuit may be impaired. Functional operability under any of Ihese conditions is not necessarily implied.
14. Typical and Minimum speCifications for the -9 version are the same as
those for the -5 version.

3-351

a:

@joe(

HA-4741
Typical Performance Curves v+ =+15V, V- = -15V, TA = +250 C, Unless Otherwise Specified.
OUTPUT VOLTAGE SWING

OPEN LOOP FREQUENCY RESPONSE

."
.,

D

11111111
1IIIIIi
1IIIIm

.10D
D

!g +8D

~+10

~ +5 0

~

i="

+4 0

~ +3 0

*
z

+2

IJ~I~2q

I

~+a 0

0

FREQUENCY

IIIIL

1111111 II
CL'" 50pF

VB.

30
D

Vo =Z8V

[vS·!15V

VO=lBV

VS=·IOV

VO=8V

~\:!5V

vo-zv

v

45'

IIIII

,

0'

=±2V

"-

135'

0

"

1.0'

0

-1 0

10

100

lK
10K
FREQUENCY (Hz)

1M

lOOK

10M
(VOLTAGE FOLLOWER)
1

Rl-OO
CL=50pf

100

1K

10K

lOOK

1M

FREQUENCY (Hz)

NORMALIZED AC PARAMETERS VB. SUPPLY VOLTAGE

NORMALIZED AC PARAMETERS VB. TEMPERATURE

,

1

f.

1.0

./

~
~

BANDWJO~

•

,

SLEW RATE
BANDWIDTH

)

~ 0.9

,.

V

~
c

V

/

0,'

-

,I

•

-55

,/

I--"'"

SLE

RATE

r- ',;;-...

8ANDWI

~

." ." ." .." .

_25

125

TEMPERATURE (OOC)

)

!2

!5

!ID
SUPPLY VOLTAGE

!15V

!ZO

SMALL SIGNAL BANDWIDTH AND PHASE
MARGIN va. LOAD CAPACITANCE

INPUT NOISE VB. FREQUENCY

,

,

I.

"

.,

D

"

,

,

·

40

·

D

I", .........
,
,

,,,.

•

,

~VOLTAGENOISE

·
·

D
CURREN NOISE

10

.DO

10K

2

I'....

10

D
1K

3

1\

,
2D

•

D

lOOK

10

FREQUENCY (Hz!

3-352

,
,
•

~

30

D

.........

)

RL-ZK

,0'

10D

.1l1lD
LOAD CAPACITANCE (pF)

10,oao

,
lDD,ODD

HA-4741
Typical Performance Curves

(Continued)
MAXIMUM OUTPUT VOLTAGE SWING vs.
LOAD RESISTANCE

CHANNEL SEPARATION vs. FREQUENCY
0

·14 0

--

·120

z

~
:l:
~

~
~

-8

.....

100<

r-rv~'

ot--

IK

t 100<

,.

11111111
11111111

0

V

0

or-

,.
r,
-4 or.,or- I IUIIIII

-6

5

r---

~-10 0

10

5

• 2DlOGC~~01) ,

C.S

v'"

0/

HA'4741 -02

II LI

I II
I II

5

,.

100

10'

FREQUENCY (Hz)

lOOK

0

tOO

tK

tOK

tOOK

INPUT BIAS AND OFFSET CURRENT VS. TEMPERATURE

POWER CONSUMPTION VS. TEMPERATURE

".

100

·

VS·±15V

D

.-"
•

·

"

--t"--

BIAS CURRENT

.........

I'.....

'"

-

sa

-

-

VS~±lOV

I-

VS":t5V

~URREr

"

·50
+25

+50

+100

.50

'25

'15

-

TEMPERATURE (Gel

+125

TEMPERATURE (OCI

Pulse Response
TRANSIENT RESPONSE/SLEW
RATE CIRCUIT

SLEW RESPONSE

TRANSIENT RESPONSE

(Volts: 5V/DiY., Time: 51's/DiY.)

(Volts: 40mV/Diy., Time: 100ns/DiY.)

"

••v
INPUT

200m v

·w

,.v
-ov

'/

\.

I

V
0

3-353

'"

I

J

....I

en
<
z a::
0 w
;:: u:::
::::;
<
c..
a::
w :::;;
D.. <
0

LOAD RESISTANCE (OHMS)

HA-5002

m·HARRIS

Monolithic, Wideband, High Slew Rate,
High Output Current Buffer

August 1991

Features

Applications

• Voltage Gain _•••••••••••••••••••••••••••••••• 0.995

• Line Driver

• High Input Impedance ••••••••••••••••••••• 3000kO

• Data Acquisition
• 110MHz Buffer

• Low Outputlmpedance ••••••••••••••••••••••••• 30
• Very High Slew Rate ••••••••••.•••••••• 1300Vlllsec

• High Power Current Booster

• Very Wide BandwIdth •••••••••••••••••••••• 110MHz

• High Power Current Source

• High Output Current ••••••••••••••••••••••• ±200mA

• Sample and Holds

• Pulsed Output Current ••••••••••••••••••••• 400mA

• Radar Cable Driver

• Monolithic Construction

• Video Products

Description
The HA-5002 is a monolithic, wldeband, high slew rate,
high output current, buffer amplifier.

allowed a more preCise buffer to be developed with more
than an order of magnitude smaller gain error.

Utilizing the advantages of the Harris 0.1. technologies,
the HA-5002 current buffer offers 1300V/llsec slew rate
with 110MHz of bandwidth. The ±200mA output current
capability is enhanced by a 30 output impedance.

The HA-5002 will provide many present hybrid users with a
higher degree of reliability and at the same time increase
overall circuit performance.

The monolithic HA-5002 will replace the hybrid LH0002 with
corresponding performance increases. These characteristics
range from the 3000kO input impedance to the Increased
output voltage swing. Monolithic design technologies have

Pinouts

The HA-5002 Is available in an 8 pin SOIC package, an
8 pin Metal Can, and 8 pin Ceramic and Plastic Mini-DIPs.
For the military grade product, refer to the HA-5002/883
Data Sheet.

Schematic

HA9P5002 (SOIC)
HA7-5002 (CERAMIC DIP)
HA3-5002 (PLASTIC DIP)
TOP VIEW

.VI+

V1+

OUT

V2 -

V2+

RNI

09
NO

NO

IN

V1 -

vt

RI

01

OUT

HA2-5002 TO-99 (METAL CAN)
TOP VIEW
IN

02
015
V2'

RN3
VI-

lCC Package Available for HA-5002lSS3.
See HA-5002lSS3 Oata Sheet
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedul'es should be followed.
Copyright © Harris Corporation 1991

3-354

File Number

2921

Specifications HA-5002
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- pins •••••••••••••••••••••.•••• 44V
Input Voltage ••••••.••••••.•••••••••••••.•••. Equal to Supplies
Output Current •••••••••••••••••.••••••••• Continuous :l:200mA
Oulput Current ••••••••..•••.•.•..•• (SOms On, ls Off) :l:400mA
Internal Power Dissipation (Note 2)
TO-99 (+2S0C) •••••••••.•..•••••••••••••••••••••••• 1.13W
Mini-DIP (+2S 0C) •••••••••..••.••••••.•••••••••••.•• 1.22W
Plastic DIP (+250 C) •.•••••••.••.•••••••••••..•••••••• 1.88W

Maximum Junction Temperature •••••••••.•••••.••••••. +150oC
(Plastic Packages)
Maximum Junction Temperature .••••••••.••••••.••••.• +17SoC
HA-S002-2 ••••••.••••••••••••••.•••••. -55°C S TA S +1250C
HA-5002-S •••.•••••••••••.••..••.••.••••• 00 CSTAS+750C
HA-5002-9 •••••••••.••••••••••••••••.•• -400C S TA S +850C
Storage Temperature Range •••.••••..••• -6S oC S TA S +1500C

Electrical Specifications VSUPPLY = :l:12V to :l:15V, RS = 500, RL = lkO, CL = 10pF, Unless Otherwise Specified.
HA-5002-2
PARAMETER

HA-5002-5, -9

TEMP

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

+2SoC
Full
Full
+2SoC
Full
Full
+250C

1.S
-

S
10
30
2
3.4
3
4

20
30

-

S
10
30
2
2A
3
4

20
30

mV
mV
"VloC

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current
Input Resistance
Input Noise Voltage (1 OHz-l MHz)

-

7
10

-

1.S
-

-

7
10

-

fJA
"A
MO
"Vp-p

TRANSFER CHARACTERISTICS
Voltage Gain (Note 7)

RL=1000
RL=lkO
RL=lkO

-3dB Bandwidth (Note 4)
AC Current Gain

RL=1000
RL = 1 kO (Note 3)
RL = 1 kO (Note 5)

Output Resistance
Harmonic Distortion (Note 6)

+25 0C
+25 0C
Full
+25 0C
+2SoC

0.990
-

0.971
0.995

+250C
Full
Full
Full
+25 0C

:1:10
:1:10
:1:10

-

:1:10.7
:1:13.5
:l:l0.S
3
<0.005

+250C
+250C
+250C
+25 0C
+25 0C
+2SoC

1.0
-

41
3.6
2
30
1.3
50

--

8.3

-

110
40

-

0.980
-

0.971
0.995

-

:1:10
:1:10
:1:10

:1:11.2
:1:13.9
:1:10.5
3
<0.005

-

110
40

-

VN
VN
VN
MHz
NmA

10

-

-

-

10

-

V
V
V
0
%

TRANSIENT RESPONSE
Full Power Bandwidth (Note 8)
Rise Time
Propagation Delay
Overshoot
Slew Rate
Settling Time to 0.1 %

-

-

-

-

1.0

-

41
3.6
2
30
1.3
50

-

MHz
ns
ns
%
Vlns
ns

-

mA
mA
dB

-

POWER REQUIREMENTS
Supply Current
Power Supply RejectiOn Ratio
(Note 9)

+250C
Full
Full

S4

-

-

10

64

-

54

NOTES:
1. Absolute maximum rallngs are limiting values, applied Individually beyond
which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.

7. VOUT = ±10V

2. See thermal constants data in Die Characteristics section.

8. FPBW = Slew Rate Vp = SV(10Vp-p)

6. VIN = WRMS; f = 10kHz.

2nVp

3. VSUPPLY = ±lSV
4. VIN

= W p _p

 -9

"

0-

\
\

0

filf/J
9

~

\

'"
E

-12

,

0

"-

-15

1BOO
100M

-18
10M
FREQUENCY (Hz)

1M

I

0

9
!ll<
!;j

6

3
0

-3

-

-6

00

P

0

> -9

fil
f/J
9

\

E

W

goO

"-l. -1350

-15

" -18

lBOo
100M

10M
FREQUENCY (Hz)

1M

VOLTAGE GAIN VS. TEMPERATURE
Vee = :!:lSV, RLOAD = loon

VOLTAGE GAIN VB. TEMPERATURE
Vec = :!:lSV, RLOAD = lkn

0_994

0.998

_ 0_992

~ 0.99

i' 0_968

~

~ 0.968

z

w

0.984
~ 0.982
!:; 0.98
~ 0.978
0.976
0.974

~

0.997
0.996

~I-ol-o

\tOUT = 0 'rd + 10V
r-- ....

~ 0.995

~\OUT= -10VTO + 10V

-ro-~-ro

tlI

<
!:;

~

0 ro

~

ro ro l001ro

I-oi"

0.994

0.993

VOUT= OT

-10V

0.992
0.991

TEMPERATURE (DC)

....

1-01-0 ..

-ro-~-ro

0 ro

~

ro ro l00lro

TEMPERATURE (DC)

OFFSET VOLTAGE VB. TEMPERATURE
Vec= :!:lSV

BIAS CURRENT VB. TEMPERATURE
Vce= :!:15V
7
6

<
,35
I-

zw

4

II:
II:

::> 3

.....

(J

~

2

III

o

-ro-~-ro

0 ro

~

ro ro l00lro

TEMPERATURE (DC)

3-358

f/J

450 ~

\

-12

I;:

;:

if

HA-5002
Typical Performance Curves

(Continued)

MAXIMUM OUTPUT VOLTAGE VS. TEMPERATURE
Vee = ±15V. RLOAO = 1000

SUPPLY CURRENT VS. TEMPERATURE
Vee = ±15V. lOUT = OmA
10

15

;;C 9

LLl

~ 14

w

<
~

0

>

~

7

a6

i

r"'r--r-

-VOUT

Q,

0

8

a:

.~~
13

I:::l
I:::l

oS

!z

(!)

Q,

:::l

12

til

.....

5
4
3

-oo-~-~

0

~

~

00

00

l00l~

TEMPERATURE (OC)

11

-oo-~-~

~

0

~

00

l00l~

00

TEMPERATURE (OC)

SUPPLY CURRENT VB. SUPPLY VOLTAGE
lOUT = OmA

INPUT/OUTPUT IMPEDANCE VS. FREQUENCY
Vee = ±15V

+ 125°C. + 25°C

~

/

o

o

If
'/
.ill
2

lOOK

3

-55°C

w
z

tl 1000

i5

100

2!

10

~

4

6

8

10

12

14

16

N

~

@l
Q,

ci.
til

!:;
0
>

~
:;
I:::l

~

~

19
18

ZOUT

1M

lOOK

~

100M

10M

FREQUENCY (Hz)

VOUT MAXIMUM VS. VSUPPLY
RLOAO= 1000

20

-

~

1

18

SUPPLY VOLTAGE (± V)

23
22
21

- ZIN

10K

PSRR VB. FREQUENCY
00

.......
,......",

17

16
15
14
13
12
11
10
9

70

""

.......

.........

......
,......",
.......
...... ........

......... ........

00

.,50

" "

~30

12
SUPPLY VOLTAGE

8

(t V)

"

~

"....... .......
..................
.........

"

8
7

......"

:!:!.
a: 40
a:

_TA",+2SO"

TA=+1250" ................
TA= -55Dr.
........

15

.........

10

--- --

5

3-359

o

10K

lOOK

1M
FREQUENCY (Hz)

10M

100M

HA-5002
Typical Performance Curves

(Continued)

SLEW RATE vs. SUPPLY VOLTAGE

GAIN ERROR VS. INPUT VOLTAGE

-

'500

_'400

~
<:'.300

~1200

~ 1100
.000
900

k--:"

,.".. ~

w

~

'00

;;;

!

50

z

r---.. ........

'-.

>'

/"

~

V
6

'50

0

VS= ±.'5V

......

r--...

r..::::.. ~ ~

$"50

.0

8

VCC

(±

.2

VOLTS)

.4

.6

'8

TA=j5OC

RL=.IK

I,

"00
-'50
-'0

-8

-8

-4

-2

~-:d-

........ ~

I RL=

tel'"

0

2

tL=F'

J"i......
4

6

8

.0

INPUT VOLTAGE (VOLTS)

Typical Applications
OPERATION AT REDUCED SUPPLY LEVELS

CAPACITIVE LOADING

The HA-5002 can operate at supply voltage levels as low as
±5Vand lower. Output swing is directly affected as well as
slight reductions in slew rate and bandwidth.

The HA-5002 will drive large capacitive loads without
oscillation but peak current limits should not be exceeded.
Following the formula I Cdv/dt implies that the slew rate or
the capacitive load must be controlled to keep peak current
below the maximum or use the current limiting approach as
shown. The HA-5002 can become unstable with small
capacitive loads (SOp F) If certain precautions are 'not taken.
Stability is enhanced by anyone of the following: a source
resistance in series with the input of son to 1K; increasing
capacitive load to 150pF or greater; decreasing CLOAD to
20pF of less; adding an output resistor of 10n to son; or
adding feedback capacitance of 50pF or greater. Adding
source resistance generally yields the best results.

SHORT CIRCUIT PROTECTION
The Output current can be limited by using the following
circuit:
RUM=

V+

~

=

~

IOUTMAX
IOUTMAX
IOUTMAX = 200mA (CONTINUOUS)

RUM
IN

OUT

Die Characteristics
Transistor Count ................................... 27
Die Dimensions ............. , ......... 80 x 81 x 19 mils
(2030/lm x 2050/lm x 480/lm)
Substrate Potential* ............................... V1Process ..................................•. Bipolar-DI
Sja
Sjc
Thermal Constants (OC/W)
HA7-5002 Ceramic Mini-DIP
122
39
HA3-5002 Plastic DIP
80
20
HA2-5002 Metal Can
103
31
HA9P5002 SOIC
160
42
*The substrate may be left floating (Insulating Die Mount) or it may be
mounted on a conductor at V- potential.

3-360

=

HA-5004

mHARRIS

100MHz Current Feedback Amplifier

August 1991

Features

Description

• Slew Rate ••.••••••••••••••••••••••••••••• 1200Vl)ls

The HA-5004 current feedback amplifier is a video/
wideband amplifier optimized for low gain applications. The
design is based on current-mode feedback which allows
the amplifier to achieve higher closed loop bandwidth than
voltage-mode feedback operational amplifiers. Since feedback is employed, the HA-5004 can offer better gain
accuracy and lower distortion than open loop buffers.
Unlike conventional op amps, the bandwidth and rise time
of the HA-5004 are nearly independent of closed loop gain.
The 100MHz bandwidth at unity gain reduces to only
65MHz at a gain of 10. The HA-5004 may be used in place
of a conventional op amp with a significant Improvement in
speed power product.

• Output Current •••••••••••••••••••••••••••• ±100mA
• Drives ••••••••••••••••••••••••••••.. ±9V into 100n
• VSUPPLY ••••••••••••••••••••••••••••• ±5Vto ±18V
• Thermal Overload Protection and Output Flag
• Bandwidth Nearly Independent of Gain
• Output Enable/Disable

Applications
• Unity Gain Video/Wideband Buffer

Several features have been designed in for added value. A
thermal overload feature protects the part against excessive
junction temperature by shutting down the output. If this
feature is not needed, it can be inhibited via a TIL input
(TOI). A TIL chip enable/disable (OE) input is also provided;
when the chip is disabled its output is high Impedance.
Finally, an open collector output flag (TOL) is provided to
indicate the status of the chip. The status flag goes low to
indicate when the chip is disabled due to either the internal
Thermal Overload shutdown or the external disable.

• Video Gain Block
• High Speed Peak Detector
• Fiber Optic Transmitters
• Zero Insertion Loss Transmission Line Drivers
• Current to Voltage Converter
• Radar Systems

In order to maximize bandwidth and output drive capacity,
Internal current limiting is not provided. However, current
limiting may be applied via the VC+ and VC- pins which
provide power separately to the output stage.
The HA-5004 is available In a 14-pln Ceramic DIP and Is
specified for operation from ooC to +75 0 C (HA1-5004-5)
and -400 C to +85 0 C (HA1-5004-9). For Military grade
product refer to the HA-5004/883 data sheet.

Pinouts
INPUTS

HA1-5004 (CERAMtC DIP)
TOP VIEW

Ve OUT

VEE

+BAL

FB

-BAL

IN

TEMP

TOLOUTPUT
(OPEN
COLLECTOR)

OE

TOI

TJ

OPERATION

0

0

Normal

1

Normal

0

0

High"

0

Auto Shutdown, Hi-Z OUT

0

1

X

1

Normal

1

X

X

0

Manual Shutdown, Hi-Z OUT

'>1800 CTypical

Vee
TOI

GND

NJC

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-361

File Number

2923

Specifications HA-5004
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Supply Voltage. • • • • • • • • • • • • • • • • • • • . • • • • . • • • • • • • • • • • • •• ±20V
Differential Input Voltage ••••••••••••••••••••••••••••••.•••• 5V
Common Mode Input Voltage •••••.•••••••••••.•••• ±VSUPPLY
Output Current. • • • • • • • • • • . • • • • • . . • • • • • • • • • • • . • • • • •• ±120mA

HA-5004-9 •••••••••••.••.••••.•••••••.• -400C ~TA~ +850C
HA-5004-5 ••••••••••••••.••••.•••••••.••• OOC.5TA~+750C
Storage Temperature ••••••••••••••••.••• -650C~TA~ +1500C
Maximum Junction Temperature ••••••.•••••••••••••••• +1750C

Electrical Specifications VCC = Vc+ = +15V, VEE = VC- = -15V, RS = 500, RL =1000, Av = +1, RF = 2500, OE = OJ3V,
TOI = 0.8V or 2.0V Unless Otherwise Specified.
HA-5004-5, -9
PARAMETER

TEMP

MIN

TYP

MAX

UNITS

+250C
Full
Full
+250 C
Full
+25 0C
+250C
Full

-

1

5
20

mV
mV

±10

-

-

+25 0C
+250C
+250C
+250 C
+250 C

-

-72
-70
-68
15
2.2
2.2
6
4

-

2.0

-

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current (+Input Only) (Note 2)
Input Resistance (+Input Only) (Note 2)
Input Capacitance
Common Mode Range

-

10
2

3
3

-

5
20

~VloC

~
~

MO
pF
V

DISTORTION AND NOISE
Total Harmonic Distortion 2Vp _p, 200kHz

Input Noise Voltage 10Hz to 1 MHz
Input Noise Voltage Density (Note 3)
Input Noise Current Density (Note 3)

AVCL=+1
AVCL=+2
AVCL=+5
10
10
10
10

=
=
=
=

10kHz
100kHz
10kHz
100kHz

dBc
dBc
dBc
~Vp_p

nVlVHz
nVl,fHz

pAJ,fHz
pNv'f!Z

DIGITAL I/O CHARACTERISTICS
Logic Inpuls (OE and TOI)

Full
Full

VIH
VIL
IIH @ VI = 2.4V

Full
Full
Full

IlL @ VI = 0.4V
Logic Output (TOL) (Open Collector)

VOL@800~A

-

-

V
V

-

0.8

~

0.05

1
10
0.4

0.43
0.75
0.43
0.75

%
%
%
%
VN
VN
VlmA
VlmA
MHz
dB
dB
%
%
%
%
Degree
Degree
Degree
Degree
dB
VN

-

~

V

TRANSFER CHARACTERISTICS
DC Gain Error

Small Signal (±1 OOmV)
Large Signal (±1 OV) (RL = 1 K)

DC Voltage Gain (Note 4)
DC Transimpedance (Note 5)
-3dB Bandwidth AV = +1 (Note 6)
Gain Flatness
Differential Gain (Notes 6, 7, 8) 3.58MHz
Differential Gain (Notes 6, 7, 8) 4.43MHz
Differential Phase (Note 6, 7) 3.58MHz
Differential Phase (Note 6, 7) 4.43MHz

DC to 5MHz
DCt010MHz
AVCL=+1
AVCL=+2
AVCL=+1
AVCL=+2
AVCL=+1
AVCL=+2
AVCL=+1
AVCL=+2

Common Mode Rejection Ratio (Note 9)
Minimum Stable Gain

3-362

+250C
Full
+250 C
Full
+250C
Full
+250C
Full
+250 C
+250 C
+250C
+250C
+250 C
+250 C
+250 C
+250C
+250C
+250C
+250 C
Full
Full

-

233
133

33

-

-

-

1

0.25
0.25
0.25
0.25
400
400
100
100
100
0.03
0.05
0.035
0.058
0.035
0.058
0.15
0.23
0.17
0.24
58

-

-

-

Specifications HA-5004
Electrical Specifications (Continued) VCC = VC+ = +15V, VEE = VC- = -15V, RS = 500, RL =1000, AV = +1, RF = 2500,

OE =

0.8V, TOI = 0.8V or 2.0V Unless Olherwise Specified.
HA-5004-5, -9

PARAMETER

TEMP

MIN

TYP

MAX

UNITS

+250 C
+25 0C
Full
Full
+250 C
+250 C

:1:9.0
:1:11.5
:1:8.0
:1:10.5

-

+25 0 C
Full
Full
Full
Full

:1:90
:1:80

:1:9.5
:1:11.8
:1:9.5
:1:11.8
100
5
:1:100

-

V
V
V
V
MHz
0
rnA
rnA
ns

-

I'S

1

JJA

OUTPUT CHARACTERISTICS
Output Voltage Swing

(RL=100fl)
(RL= 1kO)
(RL=1000)
(RL=1kfl)

Full Power Bandwidth (AV = +1)(Note 10)
Output Resistance, Open Loop
Output Current
Output Enable time (Hi Z to :l:2V)
Output Disable time (:l:2V to Hi Z)
Output Leakage (Disabled)

-

-

:1:100
100

3

-

-

-

TRANSIENT RESPONSE
Rise Time/Fall Time
Propagation Delay (1 OV Step)
Slew Rate

+250 C

SetllingTime(0.1%,10VStep)
Overshoot

-

+250 C
+250 C
+250 C
+250 C

-

+250C
Full
+250C
Full

-

-

6.3
7
1200
50
10

-

ns
ns

-

VII's
ns

-

%

POWER SUPPLY CHARACTERISTICS
Supply Current

(Enabled)
(Disabled)

Power Supply Rejecton Ratio
NOTES:

-

50

12

7
60

16
22

-

rnA
rnA
rnA
dB

1. Absolute maximum ratings are limiting values, applied Individually, beyond which the serviceabUity of the circuit may be impaired. Functional
operation under any of these conditions is not necessarily implied.

2. Inverting (FB) input is a low impedance point; Bias Current, Offset Current, and Input ReSistance ara not specified for this terminal.
3. See typical performance curves.

1
4. DC Voltage Gain = _ __
Gain Error
5. DC Transimpedance

RF
=---,RF

= 2500

Gain Error

8. VIN = 300mVp-p

7. VOFFSET = 1.0V
8. Differential Gain (dB) = 0.0869 Differential Gain ('If>)

9. VCM = :l:l0V
Slew Rate
10. Full power bandwidth guaranteed by equation: Full Power Bandwidth = - - - - I V peak. = 2V
2.Vpeak

3-363

g
~

g.

a
ATI7

~
RT7

~

~T4

AT5

ATIS

AT>

OPT2 QPT3

o

a[

AT,
OPT10

AT"

ATlft

ATI.

OPT13

I

PT12

AOS

~ A23

A30

h

QN25

~

BZ4ARMBIt'

aNa

aPTI'tiFttW

CPT~CPT"~

Cf
Co)

01£- ~PT5

QNT4~

er

AT'

~

~ ~aHTII

PTI

T18
~
PH QPU

ATII

QNT8

aNTI

ON..

0'"

R2I

r~

t

AXU'

A5

.~CPS
+---t--II:~aN7

"'DDI

A35

~---I---4'QH'

t;;;;;:-l....
~

~FB

OPT15

MIG

R32

QP4

I_

~QPT"
-RT1'"

t"'j'

~

0 ....

ONT12

R3

OHao a

Q

+--+---t~::::aP2'

RTZO

,_z

~r'

I---

~
ON6A.

0011

ONes

Fli

I

Nr.l

~

CCI

CHT2

'" '"

QN4

-..;;--.r

I£~~CNT'I
ATI

DZT2

p-

DZT1
ONTO

C ....

.QCNT7

AT.

""'
GND

A'

A27

A'

...

~

DD.
~

~

Jp,

A37

A368

QNS

..
VEE

nve-

~
I

~

2

HA-5004
Typical Performance Curves

VSUPPLY = ±15V, TA = 250 e, Unless Otherwise Specified.

GAIN AND PHASE vs. FREQUENCY

FREQUENCY RESPONSE vs. SUPPLY VOLTAGE

15
."V~+5

12

iii'

9

Z

6

~

~

I

Av=l11WI
INPUT _ 300mVp· p

I

AV=+2

I

iii a

I

"z
~

--1

Av=+1

o

{
PHAS E

II II

AV=+l
AV=+2-

~

~

-4

"

;"5V
10M
FREQUENCY (Hz)

1M

100M

MAX. UNOISTORTED SINEWAVE OUTPUT vs. FREQUENCY

= ±15V, AV = +2, RL = 1 kO, Input = 10mV

12r---'-~~-rrrrn----~-r-r""Tr---'

~~
w:;;

40 r35

-+..

Q.
Q,

3r--+-+~~~--+_~~~~r-~

G
I-

"
-A
O~---r--~~-HHH+---~--+-~k+~~--~

~

-B

>0

A = O.OpF
10pF

1---+--4 B =

30

25

r-

FF

~<

""'"

r15 r10 r5 r-

20

o 7'::lK

=-C. .

1---+--4 D = 100pF +----I---+-HH-tflI~__ ,D--l

10K

lOOK
1M
FREQUENCY (Hz)

10M

I IIIII
1M

10M
FREQUENCY (Hz)

100M

CLOSED LOOP OUTPUT IMPEDANCE vs. FREQUENCY
10.0

S
w

1.0

z
«

c
w
0.

;;!

.s<"
~

=
-

u

0.1

SUPPLY CURRENT vs. SUPPLY VOLTAGE

!Z
l:!It 12

~

:::l

U 8

•

it

'"

10K

2

4

6

8

10

12

SUPPLY VOLTAGE (± V)

111111 I

lK

4

/"

:::l

IIilL

0.01

/

~

lOOK
1M
FREQUENCY (Hz)

10M

3-365

--'
<(I)

:z a:
Ow

Vee = ±15V, AV = +1, Sinewave Input

~ 9r----r--r-r;-HHH+----i--+-+-rttttr--~
z 6L...
+-;-+;~~....~..~~.tktH_--__1
~ r
~~

C=~~

:t. 3•5V

-6

100M

FREQUENCY RESPONSE vs. CL

VCC

:!: 15V
~~ov

-5

AV=+5

10M
FREQUENCY 1Hz)

1M

-2
-3

14

16

18

HA-5004
Typical Performance Curves (Continued)

VSUPPLY

= ±15V, TA = 25 0 C, Unless Otherwise Specified.

YOLTAGE NOISE vs. FREQUENCY

CURRENT NOISE vs. FREQUENCY

~C=~~

~C=~~

55
50

8 r7 I-

:r-

~ ~~
~
"
"

4

3
2
1

o

40

~

.....30

I-

20

I-

45

-

~35 I-~

~ ...

-

-

100

r-

-

125 I-

....

15
10

II-

lK

10K

lOOK

5

o

-

10

FREQUENCY (Hz)

100

10

1K

10K

FREQUENCY (Hz)

Switching Waveforms
LARGE SIGNAL RESPONSE, Ay = +1
Vertical Scale: 5V/Div.
Horizontal Scale: 20ns/Div.

TEST CIRCUIT

VINO~--~--I

2rVo~
249.n.

INPUT

OUTPUT

Ay = +1, YSUPPLY = ±15Y
PROPAGATION DELAY
Vertical Scale: 2V/Div.
Horizontal Scale: 20ns/Div.

SMALL SIGNAL RESPONSE
Vertical Scale: 100mV/Div.
Horizontal Scale: 20ns/Div.

INPUT

INPUT

OUTPUT

OUTPUT

Ay

= +1, YSUPPLY = ±15Y

Ay

3-366

= +1, YSUPPLY = ±15Y

lOOK

HA-5004
Applications Information
Theory of Operation

Power Supplies

The HA-5004 is a high performance amplifier that uses
current feedback to achieve. its outstanding performance.
Although it is externally configured like an ordinary op amp
in most applications, its internal operation is significantly
different

The HA-5004 will operate over a wide range of supply
voltages with excellent performance. Supplies may be
either single-ended or split, ranging from 6V (±3V) to 36V
(±18V). Appropriate reduction in input and output signal
excursion is necessary for operation at lower supply
voltages. Bypass capacitors from each supply to ground
are recommended, typically a 0.01 ~F ceramic in parallel
with a 4.7J.lF electrolytic.

Inside the HA-5004, there is a'unity gain buffer from the
non-inverting (+) input to the Inverting (FB) input (as
suggested by the circuit symbol), and the inverting terminal
is a low impedance point. Error currents are sensed at the
inverting input and amplified; a small change In input
current produces a large change in output voltage. The ratio
of output voltage delta due to input current delta is the
transimpedance of the device.
Steady state current at the inverting input is. very small
because the transimpedance is large. The voltage across
the input terminals is nearly zero due to the buffer amplifier.
These two properties are similar to standard op amps and
likewise simplify circuit analysis.
Resistor Selection
The HA-5004Is optimized for a feedback resistor of 2500,
regardless of gain configuration. It is important to note that
this resistor Is required even for unity gain applications;
higher gain settings use a second resistor like regular op
amp circuits as shown in Figure 1 below.

+sv

Current limit
No internal current limiting is provided for the HA-5004 in
order to maximize bandwidth and slew rate. However,
power is supplied separately to the output stage via pins 1
(Vc+) and 14 (VC-) so that external current limiting
resistors may be used. If required, 1000 resistors to each
supply. rail are recommended.
Enable/Disable and Thermal Overload Operation
The HA-5004 operates normally with a TTL low state on pin
7 (OE) but it may be disabled manually by a TTL high state
at this input. When disabled, the output and Inverting (FB)
input go to a high impedance state and the circuit is
electrically debiased, reducing. supply current by about
SmA. It is important to keep the differential input voltage
below the absolute maximum rating of 5V when the device
is disabled.
If the power dissipation becomes excessive and chip
temperature exceeds approximately 1800 C, the HA-5004
will automatically disable itself. The thermal overload
condition will be indicated by a low state at the TOl output
on pin 10. (TOl is also low for manual shutdown via pin 7).
Automatic thermal shutdown can be bypassed by a TTL
high state on Thermal Overload Inhibit (TOI) pin 6. See the
truth table for a summary of operation.'

101<.0.
r-----;::::::::!-T~HERMAL OVERLOAD

Offset Adjustment

VOUT

1---+-.-0

Offset voltage may be nulled with a 5KO potentiometer
between pins 3 and 4, center tapped to the positive supply.
Setting the slider towards pin 3 (+BAl) increases output
voltage; towards pin 4 (-BAl) decreases output voltage.
Offset can be adjusted by about ± 1OmV with a 5K pot; this
range is extended with a lower resistance potentiometer.

Die Characteristics
249A
249A

FIGURE 1: TYPICAL APPLICATION CIRCUIT, AV = +2

Transistor Count ...•.....•..•...•.•....•...•....•.. 64
Die Dimensions . . . . . . . . . . • . . . . . . • . . . .. 93 x 63 x 19mils
(2370 x 1600 x 480~m)
Substrate Potential .•.....•..........•.•.......... VEE
Process .•..•..•............................ Bipolar 01
Thermal Constants (OCIW)
aja
ajc
HAl-Ceramic DIP
107
25

3-367

til HARR.IS

HA-5020
100MHz Current
Feedback Video Amplifier

August 1991

Features

Applications

• Wide Unity Gain Bandwidth ___ • __ • __ •• __ •• _ 100MHz

• Unity Gain Video/Wideband Buffer

• Slew Rate ____ • ___ ••••••••••••••••••••••••• 800V/IlS

• Video Gain Block

• Output Current •••••••••••••••••••••••• :!:30mA (Min)

• Video Distribution Amp/Coax Cable Driver

~

Drives ••••••••••••••••••••••••••••••• 3.5V into 750

• Flash AID Driver

• Differential Gain. • • • • • • • • • • • • • • • • • • • • • • • • •• <0.02%

• Waveform Generator Output Driver

• Differential Phase ••••••••••••••••••••••••• <0.03%

• Current to Voltage Converter; D/A Output Buffer

• Low Voltage Noise •••••••••••••••••••.• 4.5nVl..jHZ

• Radar Systems

• Low Supply Current""."."., •••• , •• -, 10mA (Max)

• Imaging Systems

• Wide Supply Range ••• , •• , •• , •••••••• , :!:5V to ::I:15V
• Output Enable/Disable
• High Performance Replacement for EL2020

Description
The HA-5020 Is a wide bandwidth, high slew rate amplifier
optimized for video applications and gains between 1 and
10. Manufactured on Harris' Reduced Feature Complementary Bipolar DI process, this amplifier uses current mode
feedback to maintain higher bandwidth at a given gain than
conventional voltage feedback amplifiers. Since it is a
closed loop device, the HA-5020 offers better gain accura'
cy and lower distortion than open loop buffers.
The HA-5020 features low differential gain and phase and
will drive two double terminated 750 coax cables to video
levels with low distortion. Adding a gain flatness performance of 0.1dB makes this amplifier ideal for demanding
video applications. The bandwidth and slew rate of the
HA-5020 are relatively independent of-closed loop gain.
The 100MHz unity gain bandwidth -only decreases to
60MHz at a gain of 10. The HA-5020 used in place of a
conventional op amp will yield a significant improvement in

Pinout

the speed power product. To further reduce power, the
HA-5020 has a disable function which significantly reduces
supply current, while forcing the output to a true high impedance state. This allows the outputs of multiple amplifiers
to be wlre-OR'd Into multiplexer configurations. The
device also Includes output short circuit protection and output offset voltage adjustment.
The HA-5020 offers significant enhancements over
competing amplifiers, such as the EL2020. Improvements
include unity gain bandwidth, slew rate, video performance,
lower supply current, and superior DC specifications.
The HA-5020 is available in commercial and industrial
temperature ranges, and a choice of packages. See the
"Ordering Information" section below for more information.
For military grade product, please refer to the HA-5020/
883 data sheet.

Ordering Information
HA3-5020 (PLASTIC DIP)
HA9P5020 (SOIC)
TOP VIEW

PART
NUMBER

SAL
-IN

TEMPERATURE
RANGE

PACKAGE

HA3-5020-5

OOCto +750 C

8 Pin Plastic DIP

HA9P5020-5

OOCto +750 C

8 Pin SOIC

HA3-5020-9

-400 C to +850 C

8 Pin Plastic DIP

+IN

V-

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @) Hal'ris Corporation 1991

3-368

File Number

2845.1

Specifications HA-5020
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- Terminals ••••••••••••••••••.•. 36V
Common Mode Voltage ••••••.•.••..••....•.•••.•••• VSUPPLY
DillerentiallnputVoltage ••••••••.••.••.•.••.•••.••.•..•. :l:l0V
Output Current Short Circuit ••••..••••.••.••.•.•••••. Protected
Maximum Junction Temperature (Note 19) ••••.•.•••.••• +17SoC
Maximum Junction Temperature (Plastic Packages) ••.•. +lS00 C

HA-S020-S .••••••.•••••••.••....•.•.••.•• 00C:5 TA:5+7SoC
HA-S020-9 •••.••.••.•••••••••••••••.••• -40°C :5 TA :5 +8SoC
Storage Temperature Range .••.•••••..•. -6SoC :5 TA :5 +lS0 oC
Thermal Package Characteristics
ajc
aja
8 Pin Plastic DIP
32
94
Pin SOIC
43
161

Electrical Specifications V+ = +15V, V-

= -15V, RF = lkn, Av = +1, RL = 400n, CL :5 10pF, Unless Otherwise Specified.
HA-5020-5, -9

PARAMETER

TEMP

MIN

TYP

MAX

UNITS

mV

INPUT CHARACTERISTICS
Input Ollset Voltage (Note 2)

+250C

-

2

8

Full

-

-

10

mV

20

IIV/ oC
dB

I!A
I!A

Full

50

58

VIO Power Supply Rejection Ratio (Note 4)

+250 C

64
60

-

Non-Inverting Input (+IN) Current

Full
+25 0C

-

-

3

8

Full

-

-

20

Average Input OllsetVoltage Drift
VIO Common Mode Rejection Ratio (Note 3)

Full

Full

-

-

0.5

+IN Power Supply Rejection (Note 4)

+250C

-

-

0.06

Full

0.2

+250 C

-

-

Inverting Input (-IN) Current

12

20
50

-IN Power Supply Rejection (Note 4)

Full
+25 0C

-

25

-IN Common Mode Rejection (Note 3)

Full
+250 C

-

-

0.2

Full

+250 C

3500

-

Full

1000

-

+250 C

70

Full

65

+250C

60

-

Full

55

-

-

+IN Common Mode Rejection (Note 3)

-

0.4
0.5
0.5

dB
dB

!JAN
!JAN
!JAN
I!A
I!A

!JAN
!JAN
!JAN
!JAN

TRANSFER CHARACTERISTICS
Transimpedence
Open Loop DC Voltage Gain
RL

=400n, VOUT =:l:l0V

Open Loop DC Voltage Gain
RL

=lOOn, VOUT =:l:2.SV

-

VIrnA
VIrnA
dB
dB
dB
dB

OUTPUT CHARACTERISTICS
OuputVoltage Swing
Output Current
(Guaranteed by Output Voltage Test)

250C to +850C

:1:12

:1:12.7

-

-40 0CtoOOC

:1:11

:1:11.8

-

+250 C

:1:30

:1:31.7

Full

:1:27.5

-

-

V
V
rnA
rnA

POWER SUPPLY CHARACTERISTICS
Quiescent Supply Current

Full

Supply Current, Disabled (Note 5)

Full

51Sa:liiEi Pin Input Current (Note 5)

Full

-

Minimum Pin 8 Current to Disable (Note 6)

Full

350

Maximum Pin 8 Current to Enable (Note 7)

Full

-

3-369

7.5

10

rnA

5

7.5

rnA

1.0

1.5

rnA

-

20

I!A
I!A

Specifications HA-5020
Electrical Specifications (Continued) V+

=

=

+15V, V- -15V, RF
Unless Otherwise Specified.

= lkO, AV = +1, RL = 4000, CL ~ 10pF,
HA-5020-5, -9

TEMP

MIN

Slew Rate (Note 8)

+250 C

600
500

Full Power Bandwidth (Note 9)

Full
+250 C

9.6

12.7

Full

8.0

11.1

Rise Time (Note 10)

+250 C

Fall Time (Note 10)

+250 C
+25 0 C

-

100

-

100

PARAMETER
AC. CHARACTERISTICS (AV

TYP

MAX

UNITS

800

-

VIliS

700

-

VIliS

=+1)

(Guaranteed by Slew Rate Test)

Propagation Delay (Note 10)
Settling Time to 1%,1 OV Output Step

+25 0 C
+250 C

Settling Time to 0.25%, 1OV Output Step

+250 C

3-dB Bandwidth (Note 11)

A.C. CHARACTERISTICS (AV

5
5
6
45

-

-

MHz
MHz
ns
ns
ns
MHz
ns
ns

=+1 0, RF =3830)

Slew Rate (Notes 8,12)

+250 C

gOO

1100

750

-

Full Power Bandwidth (Note 9)

Full
+250 C

14.3

17.5

Full

11.9

+250 C
+250 C

-

-

+250 C
+250 C

-

9

-

60

+250 C
+250 C

-

+250 C
+250 C

-

(Guaranteed by Slew Rate Test)
Rise Time (Note 10)
Fall Time (Note 10)
Propagation Delay (Note 10)
3-dB Bandwidth (Note 11)
SeWing Time to 1%,1 OV Output Step
SeWing Time to 0.25%, 10V Output Step

8
8

-

VIliS
VIliS

MHz
MHz
ns
ns

-

MHz

55

-

ns

90

-

ns

-

pM/HZ

ns

HARRIS VALUE ADDED SPECIFICATIONS

=1kHz)
=1kHz)
-Input Noise Current (f =1kHz)
Input Noise Voltage (f

+Input Noise Current (f

4.5
2.5

+250 C

-

30

-

Full

:1:50

:1:65

-

mA

1

IIA

+250 C

-

25

Input Common Mode Range

Fuil

:1:10

:1:12

-Ibias Adjust Range (Note 2)

Full

:1:25

:1:40

Overshoot
Output Current (Shor! Circuit, Note 13)

Full

-

-

+250 C
+250 C

-

10

+250 C
+250 C

5

-

15

Differential Gain (Note 18)

+250 C

-

0.02

Differential Phase (Note 18)

-

Gain Flatness to 5MHz

+250 C
+250 C

Chrominance to Luminance Gain (Note 18)

+250 C

-

Chrominance to Luminance Delay (Note 18)

+25 0 C

-

0.3

Output Current (Disabled, Notes 5, 14)
Output Disable Time (Note 15)
Output Enable Time (Note 16)
Supply Voltage Range
Output Capacitance (Disabled, Notes 5,17)

nVly'FiZ

1

-

pNy'FiZ
V

IIA
%

liS

lIB

15

V

-

pF

0.03

-

Degrees

0.1

-

dB

0.02

-

VIDEO CHARACTERISTICS

3-370

%

dB
ns

HA-5020
NOTES:
1. Absolute maximum ratings are limiting values. applied individually. bee
yond which the servicability of the circuit may be impaired. Functional
operation undor any of these conditions is not necessarily implied.

9. FPBW=

Slew Rate

10. Rl = 1000, Vour::o 1V. Measured from 10% to 90% points for rise/fall
times; from 50% pOints of input and output for propagation delay.

2. The inverting input current (-Ibias) can be adjusted with an external
10kO pot between pins 1 and 5, wiper connected to V+. Since -Ibias
flows through the feedback resistor (RF>, the result is an adjustment in
offset voltage. The amount of offset voltage adjustment is determined by
the value of RF (/l.VOS = /l.-lbias·RF).

II. RL

3. VCM = ±IOV.

13. VIN = ±IOV, VOUT

4. ±4.SV So. Vs S ±I ev.

14. VOUT - ±IOV.

5. Disable = OV.

6. RL -= lOOn. VI~' This is the minimum current which must be
pulled out of the Disable pin in order to disable the outpul The output is
considered disabled when -10mV ~ Vour .:s. +10mV.

av.

7. VIN =
This is the maximum current that can be pulled out of the
Disable pin wilh the HA-5020 remaining enabled. The HA-5020 is con..
Sidered disabled when the supply current has decreased by at least
0.5mA.
8. Vour switches from -1 OV to +1 av, or from + 1av to -1 OV. Specification
is from the 25% to 75% paints.

: VpEAK =IOV.

2nVpEAK

= 4000, VOUT = lOOmV.

12. This parameter is not tested. The limits are guaranteed based on lab
characterization, and reflect lot-to-Iot variation.

= OV.

15. VIN = +1 OV, ffiSabiii = +I5V to OV. Measured from the 50% point of
Disable fo Vour = OV.
16. VIN = +10V, i5iSaiiii = OV to +15V. Measured from the 50% point of
Disable to Vour = lOV.
17. VIN = OV, Force VOUT from OV to ±IOV, trllt

= 50ns.

18. Measured with a VM700A video tester using a NTC-7 compOSite VITS.
19. Maximum power dissipation, 'ncluding output load, must be designed to
maintain junction temperature below +1750 C for ceramic packages,
and below + 1500C for plastic packages.

File Number

3-371

2845

HA-5033

mHARRIS

Video Buffer

August 1991

Features

Applications

•
•
•
•
•
•
•
•
•

•
•
•
•
•
•
•
•

Differential Phase Error •••••••••••.•••••• 0.1 Degree
Differential Gain Error ••••••••••••.••••••••••• 0.1 %
High Slew Rate ••••••••••••••••••••••••••• 1300V/ps
Wide Bandwidth (Small Signal) ••••••••••••• 250MHz
Wide Power Bandwidth •••••••••••••••• DC to 65MHz
Fast Rise Time ••••••••••••••••••••••••••••••••• 3ns
High Output Drive ••••••••••••• ±8V With 1000 Load
Wide Power Supply Range ••••••••••••• ±5V to :!:16V
Replace Costly Hybrids

Video Buffer
High Frequency Buffer
Isolation Buffer
High Speed Line Driver
Impedance Matching
Current Boosters
High Speed AID Input Buffers
For Further Application Ideas, See App. Note 548

Description
The HA-5033 Is a unity gain monolithic I.C. designed for
any application requiring a fast, wideband buffer. Featuring
a bandwidth of 250MHz and outsanding differential phase!
gain characteristics, this high performance voltage
follower Is an excellent choice for video circuit design.
Other features, which include a minimum slew rate of
1000V/ps and high output drive capability, make the
HA-5033 applicable for line driver and high speed data
conversion circuits.

Pinouts

The high performance of this product is a result of the Harris
Dielectric Isolation process. A major feature of this process
is that it produces both PNP and NPN high frequency
transistors which makes wide bandwidth designs, such as
the HA-5033, practical. Alternative process methods
typically produce a lower AC performance.
The HA-5033 is available in a 12 pin (TO-8) Metal Can or In
8 pin Plastic Mini-DIP and SOIC packages.

Schematic

HA3-5033-5 (PLASTIC MINI-DIP)
HA9P5033-5/-9 (SOIC)
TOP VIEW

+vcr--~~----r-~--------------~----r-~~~-,

RI2

R2

OUT
08

aiD

NC
01

SUBSTRATE

R11
VOUT

VIN

V-

RIO
02

HA2-5033-2/-5 (TO-8 METAL CAN)
TOP VIEW
Rl

R13

~cr--~-+---1--~--------------~--~+--1--~

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harrl. Corporalion 1991

3-372

File Number

2924

Specifications HA-5033
Absolute Maximum Ratings (Note 1)

Operating Temperature Ranges

Voltage Between V+ and V- Pins •••.••••.•••..••.•.••••••• 40V
Input Voltage •••.••••••••.•••••••••••••.••••• Equal to Supplies
Output Current (Peak) (SOms On/1 Second Off) .••.•..• ±200mA
Internal Power Dissipation (Note 2)
TO-8 (+2S0 C) •.•••.•.••••.•••.•••...••..••..••••.•• 1.7SW
Mini-DIP (+2S0 C) .•.••••••••••.•.•.••••..••.••••.••• 1.9SW

HA-S033-2 •..•...••..••••.••..••...••• -SSoC ~ TA ~ +12SoC
HA-S033-S .•••.•••••.•••.••••••.••••.•••. OOC ~ TA S +7SoC
HA-S033-9 •...••...••..•...••.•.•.•..•• -400 C.$ TA.$ +8S oC
Storage Temperature Range •..•.•...•••• -650C ~ TA ~ +1S0 0 C
Maximum Junction Temperature ..•••...•••••..••••••.• +175 0 C
Maximum Junction Temperature (Plastic Packages) ••..• +1S0 0 C

Electrical Specifications VSUPPLY

= ±12V, RS = 50n, RL = lOOn, CL = 10pF, Unless Otherwise Specified.
HA-5033-2

PARAMETER

TEMP

MIN

+250 C
Full
Full
+250 C
Full
+250 C
+250 C
+2SoC

-

+250 C
+2So C
Full
+2SoC

0.93
0.93
0.92

Full
Full
+250 C
+2So C

:1:8
±11
:1:80

NOTE 10
HA-5033-9

HA-5033-5

TYP

MAX

5
6
33
20
30
1.5
1.6
20

15
25
35
50

-

-

MIN

TYP

MAX

MAX

UNITS

5
6
33
20
30
1.5
1.6
20

1S
25

15
30

mV
mV

35
50

35
SO

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current
Input Resistance
Input Capacitance
Input Noise Voltage (Note 3)

-

-

-

-

-

-

-

-

-

-

p.vtoc

vA
vA

-

MO
pF
)JVp-p

-

-

VN
VN
VN
MHz

TRANSFER CHARACTERISTICS
Voltage Gain
RL=1000
RL = 1kO
RL = 1000
-3dB Bandwidth

2S0

-

-

-

:1:10
:1:12
:1:100
S

-

-

146

-

-

0.99

0.93
0.93
0.92

0.99

-

-

2S0

-

:1:8
±11
:1:80

-

:1:10
±12
:1:100
S

-

-

-

146

-

-

-

-

-

-

OUTPUT CHARACTERISTICS
Output Voltage Swing
RL=1000
RL = 1 kO (Note 4)
Output Current
Output Resistance
Full Power Bandwidth
(NoteS)
(Note 7)

+2SoC
+2So C

15.9

-

1S.9

-

-

-

V
V
mA
0
MHz
MHz

TRANSIENT RESPONSE
Rise Time (Note 6)
Propagation Delay
Overshoot
Slew Rate (Note 7)
SettlingTimetoO.1%
Differential Phase Error (Note 8)
Differential Gain Error (Note 8)

+250 C
+250 C
+250 C
+250 C
+250 C
+250 C
+250 C

-

-

3
1
10
1.3
50
0.1
0.1

+250 C
Full
Full
+250 C

-

-

1

-

-

-

-

-

3
1
10
1.3
50
0.1
0.1

21
21

25
30

-

21
21

2S
30

25
30

<0.1

-

<0.1

-

-

-

-

1

-

-

ns
ns
%
V/ns
ns
Degree
%

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio
Harmonic Distortion (Nole 9)

54

-

-

NOTES:
1. Absolute maximum ratings are limiting values, applied individually
beyond which the serviceability of the circuit may be Impaired. Function~
aI operability under any of these conditions is not necessarily implied.
2. TO-8: 9ja =101 OC/W. 0je = 33 0 CNI Recommended heat sinks for the
TO-8: Thermalloy 2240A. Bsa - 27 0 C/W. IERC Up-TO-8-48CB.
asa - 100CIW. Mini-DIP: Bja - 91 °C/W. asa = 40oCIW.
3. 10Hz 10 1 MHz
4. ±VSUPPLY - ±15V
5. VOUT - lVRMS. RL - 1 kO
6. VOUT = 500mV
7. ±VSUPPLY = ±15V. VOUT - ±10V. RL = lkO.

-

S4

-

-

-

-

mA
mA
dB
%

6. Differential gain and phase error are non-linear signal distortions found
in video systems and are defined as follows: Differential gain error Is
defined as the change in amplitude at the color subcarrier frequency as
the picture signal is varied from blanking to while level. Differential phase
error is defined as the change in the phase of the cotor subcarrier as the
picture signal is varied from blanking to while level. Differential gain and
phase error were too small to be measured with a Tektronix 520A NTSC
Vector Scope.
9. VIN = tVRMS
10. Typical and minimum specification for the -9 version are the same as
those for the -5 version.

3-373

HA-5033

Operating Instructions
Layout Considerations
The wide bandwidth of the HA-5033 necessitates that high
frequency circuit layout procedures be followed. Failure to
follow these guidelines can result in marginal performance.
Probably the most crucial of the RF/video layout rules is the
use of a ground plane. A ground plane provides isolation
and minimizes distributed Circuit capacitance and
inductance which will degrade high frequency performance. This ground plane shielding can also incorporate the
metal case of the HA-5033 since pin #2 is internally tied to
the package. This feature allows the user to make metal to
metal contact between the ground plane and the package,
which extends shielding, provides additional heat sinking
and eliminates the use of a socket, IC sockets contribute
inter-lead capacitance which limits device bandwidth and
should be avoided.
For the plastic Mini-DIP, pin 6 can be tied to either supply,
grounded, or simply not used. But to optimize device

performance and improve isolation, it is recommended that
this pin be grounded.
Other considerations are proper power supply bypassing
and keeping the input and output connections as short as
possible which minimizes distributed capacitance and
reduces board space.
Power Supply Decoupling
For optimum device performance, it is recommended that
the positive and negative power supplies be bypassed with
capacitors to ground. Ceramic capacitors ranging in value
from 0.01 to 0.1 flF will minimize high frequency variations in
supply voltage. Solid tantalum capacitors 11'F or larger will
optimize low frequency performance.
It is also recommended that the bypass capacitors be
connected close to the HA-5033 (preferably directly to the
supply pins).

Test Circuits
SLEW RATE AND SETTLING TIME

IN

0-----1

TRANSIENT RESPONSE

OUT

IN

0-----1

:>----~~--o OUT

100.n.

RISE TIME

SETTLING TIME

~::::J

o~::Jr---------------~

OV

L

OVERSHOOT

I
I
I

OUTPUT
10%

-

I ERROR BAND
I ±10mV FROM
I SLEW I FINAL VALUE
IWRATE=I

_....J_

I

II

I V/IH I

NOTE:

3-374

Measured on both positive and negative transitions.

HA-5033
Test Circuits (Continued)
+10V RESPONSE

TA

+10V RESPONSE

= +25 0 C, RS = son, RL = loon

TA

= +250 C, Rs = son, RL = 1 kn

--'
«en

za:

+O.5V PULSE RESPONSE
TA = +25 0 C, RS = 50n, RL = loon

OW

~§

a:
"w::;;;

g;«

Typical Performance Curves
INPUT OFFSET VOLTAGE vs.
TEMPERATURE VS. SUPPLY VOLTAGE

INPUT BIAS CURRENT vs.
TEMPERATURE vs. SUPPLY VOLTAGE
40r----.--------r---·----,--------r~

_.-

8. 0

7.0
6.0

5.0
4. 0
3.0

2.0
1.0

/

~

...----::::::--

V
,~

"

V

-- --

--

-40

...z

B

c

w

II:
II:

::>
u

D-

~

iii

...
A: V+=+'5V
~ 'Of-----t--B: V+=+'2V
~
c: V+= +10V
D: V+=+5V

v-= -15~_

A: V+: +15V
B: V+ '" +l:2V V-

= -12V
C; V+ = +10V V- = -lOV
D: V+ = +5V V-=-5V -

1

-80

A

+40
+80
TEMPERATURE (CCl

I
+120

+160

V-=-'5V
V- = -'2V
V-=-'OV
V- = -5V

----j:-i

~5~5-----2~5-------+~25~------+~75-------+-'2~5~
TEMPERATURE (OC)

3-375

HA-5033
Typical Performance Curves (Continued)
SUPPLY CURRENT vs.
TEMPERATURE VS. SUPPLY VOLTAGE

SLEW RATE vs. TEMPERATURE
3000r----r-------r-------.-------,
±V = t15V
VIN =+10V

3or----r-------r------~------_,

~

,g
20

I-

'a:a:"
w

w

:J

>-"
....

..

1----+--------+:; ~:: :~~~

10

~

~=: =~~~

a:

~ 1000~---+::~==~R~IS;E~(~R~L~=~1~0:on~I~~--_i

C: V+ = +10V V- = -10V
D: V+ = +5V V- =-5C

:J

"'


.s
"'0

40
20

>

..
..iI'" '"

~

I-

:J

RL=~n........

-20

:J

I-

:J

-40

0

-60

V

-BO
-10

-8

V

--..

~

-6

riL =

/.

.L~

100
~

'" -100

~ -300

-4
-2
0
+2
+4 +6
INPUT VOLTAGE (VOLTSI

+8

RL=100n/

I::J

±V=±15V
TA=+250 C -

0_ 500

i"

V

-900

V
-10

V
i"

./

V

RL-100n

.e:.

.L
tv = ±15V
TA=250 C

RLi501
-B

-6

-4

-2

4

INPUT VOLTAGE (VOL TSI

3-376

V

~

/

-700

+10

5~n

/V

300

iI

10,000

5000

INPUT VOLTAGE

VB.

500

--~
>~

/V

I

~

1000
CAPACITANCE (pF!

700

.A'
V ~~
~

I

r--..

900

/

L~rr

.~

100

GAIN ERROR

RL=11Kn

.~

200

INPUT VOLTAGE

60

FALL

'\

"

300

100

BO

~~:!~::VIN=±10V-

RISE_, _'-

400

10,000

+V=±15V -

::-.,.

;:: 600
~ 500


r- _ /
/ ,/v;;;'

120

oS

-

~ 100

>

RL ° lKU

I-

~

80

I-

:J

60

0

40

~

:=
:J

~ 600

,-

!;
~

500

/
/-/ /

/

~ 40 0

>

300

vootov-25

+25

CURRENT

vou~OSOLRCING

fl

CURRENT

V l/' k-'"'
100
-::;:.. f;:/ V

±V::: ±15V

-55

I

Your = +10
= 0 SINKING

~v

200

20

VOJ=-10

10

~

~

~

~

~
M
lOUT (mA)

~

~

100

+125

+75

TEMPERATURE IOC)

Y - PARAMETERS PHASE vs. FREQUENCY

,.

0

g
ill

§

r-

Ir

135

-'
<

I
HA-5111 LARGE SIGNAL TRANSIENT RESPONSE
Ch. 1 2.5V/Dlv.
Timebase 200ns/Dlv.

=

+200mV

II""

1
1

ov

1\
0\

'f

-5V

=
=

=

r

+100mV

+5V

-5V

V

/

:~

ov

1

I.

1\

~

"

\.

-l00mV

HA-5111 LARGE AND SMALL SIGNAL RESPONSE CIRCUIT
IN 0-----1

'"

HA-5101 SMALL SIGNAL TRANSIENT RESPONSE
Ch. 1 5OmV/Dlv.
Timebase 100ns/Dlv.

=

ov

.....
I

-200mV

HA-5101 LARGE SIGNAL TRANSIENT RESPONSE
Ch. 1 2.5V/Div.
T1mebase 1.001lS/Dlv.

/..

l-i'"

OOUT

HA-5111 SMALL SIGNAL TRANSIENT RESPONSE
Ch.1 = 100mV/Div.
Timebase 100ns/Div•

=
=

+5V

I I

SETTLING TIME CIRCUIT

'5~R 2::6 :fl5V ~~CILLOSCOPE

>-.....- - - i l - - - - o OUT

r--~~--4~~~

2kA

+15V
>~r-"",-oVOUT

• AV = -1 (HA-5101). *AV = -10 (HA-5111)
• Feedback and summing resistors should be 0.1% matched.
• Clipping diode. are optional. HP5082-2810 recommended.

3-384

HA-5101/5111
Typical Performance Curves
HA-5101/11 NOISE SPECTRUM

OFFSET VOLTAGE VS. TEMPERATURE
1500

~;;:

1\

;;

.:>

w

Co

~

'\

"-

"\

":;
l;j

:J

~

w

/

500

~

t.l

a

Ul

az

CURRENT

f..-- !-"

V

§?

c:
c:

VOLTAGE

"-

'" 1000

I-

o
-so

·25

o

+25
+50
+75
TEMPERATURE (oC)

~

+ 100

+ 125

~

I
100
lK
10K
FREQUENCY (Hz)

10

lOOK

PEAK-TO-PEAK NOISE 0.1Hz to 10Hz
AV = 25000 Vee = ±15V
(2.25~Vp-p RTO)

PEAK-TO-PEAK TOTAL NOISE 0.1Hz 10 1MHz
AV 25000, Vee ±15V
(12.B9mVp-p RTO)

=

=

-'

« en

za:

OW

~§

a: a.

w:;;

g,«

IN~UT

OFFSET CURRENT VS. TEMPERATURE

INPUT BIAS CURRENT vs. TEMPERATURE

20

~

250

1

0

IZ

w

a:
a:

""w

-20

a

·40

I-

~

--....

.;"

~

I-

";!;"-

~

-60

Y

-25

-55

J
25
50
TEMPERATURE (OC)

75

I-

z
w
c:
c:

"

100

200

"-......

150

:J 100
t.l
Ul

'"

iii

125

50

C

....

RISE TIMEt..,.

1

~

~ 0.9

.... ""

SLEW RATE

..1

... ...
1""" ...

.............

-55

-25

o

25
50
75
TEMPERATURE (DC)

...
10

"a:
10

O.9~

HA-5101
GAIN

60

O.B~

HA-5111
PHASE

...

>=

;:

~~-5!11

...

6
:;J

a

w

"'

0.722

"'

HA-5101

1

PHI"r~

0.6

0.6
-60

125

GAIN

:::J

a

~ 0.7

I

12O

"'I'-o~

10
~ 08

100

OPEN-LOOP GAIN/PHASE VS. FREQUENCY
1.1

~

"'- .......

o

SLEW RATE/RISE TIME VS. TEMPERATURE
RL = 2K, eL = 50pF, Vee = ±15V
'-1

"

-40

- 20

20
40
60
TEMPERATURE (OC)

BO

100

100

IIIII

120
10

3-385

100

10K
lOOK
FREQUENCY (Hz)

1M

10M

100M

HA-5101/5111

Typical Performance Curves

(Continued)

INPUT OFFSET WARMUP DRIFT vs. TIME
(Normallzd To Zero Final Value)
(Six Representative Units)

,

30
20

~

10

:t:

0

Iii
Ul

-10

'CJz"
<

I

TA= +25DC
VCC=±l5V -

U

LILI-

0

"- ,.,.
-.....

SUPPLY CURRENT vs. SUPPLY VOLTAGE
5

I

.1_

MAXIMUM

r-~
~

I"-

TYPIICAL
MINIMUM

TA=

- -

+ 25°C

ioo-""'"

~

-20

o

o

2

6

4

8

10

12

14

16

18

20

SUPPLY VOLTAGE (± V)

-30

o

50

100

150 200 250

300 350 400 450 500

TIME (SECONDS)

SHORT CIRCUIT CURRENT vs. TIME

DC OPEN-LOOP VOLTAGE GAIN VS. SUPPLY VOLTAGE
dB (VN)

60

140 (107 ) - . - - - - , ; - - - - . - - - - - ,

<"

50

.§.

z

~

tlj120 (106 )

<

!z

'"a:a:

+----ir-----+----I

:l

!J
~
Q.
o

40

30

U

I-

it

~ ~ vD
.....::: ~

"-

0

9
Z 100 (105) +-----f----+----j
~

B

~

20
10

±15V
TA= +2SOC

c/
A

V ,N

I:l

Vee =

VOUT

A

+ 15mV

+15V

B

·lSmV

+15V

C

+ 15mV

OV

0

w,SmV

OV

0

o

o

20

40

60

80

100

120

140

160

TIME (SEC)

80 (10 4 )

+-----f'----+----j
5

18

10
15
SUPPLY VOLTAGE (± V)

HA-5111 CLOSED-LOOP GAIN AND PHASE
AT HIGH AND LOW TEMPERATURE
(Typical Rresponse Of One Amplifier)
VCC ±15V, AV 10VN, RL 2K, CL 50pF

=

=

25

=

"'
w

0

(!l

"~
~

+55OC

-5

PHASE

lila(

-10

+,11511,), ..,

-15

:limi

- 20
-25
10K

11111
lOOK

1M
10M
FREQUENCY (Hz)

40

~

a:

AV= 10

ffi

c."'
0:2-

o

Ii:

-45

~

'(!l

-90

~
J:

e.

r""--

II II

30

~
w

~

- -

(!l

=

AV= 100

GAIN

GAIN

:2- 10
z
;;: 5

=

50
-55"<:

~~;~~

15

=

=

lllIL

20

HA-5111 CLOSED-LOOP VOLTAGE GAIN FREQUENCY
AT DIFFERENT CLOSED-LOOP GAINS
TA +250 C, VCC ±15V, AV 100,
lOVN, RL = 2K, CL = 50pF

9~

ffi~

20

10
0

w

8;!

-10

-135 C.

"§Z

-20

9-'

-

-- -

-

'"
-

-30

-180

-225

-40

100M

-50
10K

lOOK

1M
FREQUENCY (Hz)

3-386

10M

100M

HA-5101/5111
Typical Performance Curves

(Continued)

HA-S101 CLOSED-LOOP GAIN AND PHASE
AT HIGH AND LOW TEMPERATURE
(Typical Response 01 One Amplifier)
Vee ±15V, AV 1VN, RL 2K, eL 50pF

=

HA-S111 REJECTION RATIOS vs. FREQUENCY
TA = +250 e, Vee = ± 15V

=

-40

11111 .J,o~

0

1)~!;~

-- - - - -

-so

~
w

GAIN

ffi

a

t

-45

~

- 90

~

1550 C
PI'ASE

-12

~

c

§

~,Wi~~~l

I 11111

1M
FREQUENCY (Hz)

-180

-140
100

HA-S101 CLOSED-LOOP VOLTAGE GAIN vs. FREQUENCY
AT DIFFERENT CLOSED-LOOP GAINS
TA +25 0e, Vee ±lSV, RL 2K, eL SOpF

=

=

=

,

-

~

,,'-

-

~

I'

"

-120

-225
100M

10M

V

~

,

1.' .. PSRR

V
I.'

-135 [:

~

I 11111

u

lOOK

-PSRRICMRR

EO

-

10K

- -

a:

-6

g,~ -9

,

GAIN

lUll

-3

~S'

9

=

3

z
~
~

~

=

lK

10K
100K
FREQUENCY (Hz)

1M

10M

HA-S101 REJECTION RATIOS vs. FREQUENCY·
TA = +250 e, Vee = ±lSV

=

AV= 100

40

11

30

1""--....

~-so~~-rtt~~-r++Hff~~~.1~Htffir-i-rHt~

AV- 1O

Q5" 20

::;
Z

;;:
"

::;

r-ro-

II

10

AV-l

... ~-

0
-10
-20

-120

10K

1M
FREQUENCY (Hz)

lOOK

10M

100M

-14O,_LOO~L-.L.JL..L1.l.llJ,Il:K:-'......L..L1J~1'!:OK::-LL..u..":'':'00K:::-.L.J-LJ~,M
FREQUENCY (Hz)

--

HA-S111 SETTLING WAVEFORM SOOns/DIV.

,,

I

,,

VOUT
4V/div

:

'1

,
VSETTiw ,,
I
I
---01 r~ 320 ,"sec
,,

I
I

I

-

100/lV

~

T

1-tt1tl--+--HH-HHtt--i-+ttttttt-HttHill-t-i;tittffi

.,

A -

HA-S101 SETTLING WAVEFORM 1.Sps/DIV.
I

-

1 VERROR
1 lmV
+

1
'2_65/l5

11 1

j

1

3-387

t

!-:'~

HA-5101/5111
Applications Information
Operation At ±5V Supply

Input Protection

The HA-5101/11 performs well at Vee = ±5V exhibiting
typical characteristics as listed below:

The HA-5101/11 has built-In back-to-back protection
diodes which will limit the differential Input voltage to
approximately7V.1f the 5101/11 wlll be used in conditions
where that voltage may be exceeded, then current limiting
resistors must be used. No more than 25mA should be
allowed to flow In the HA-5101/11's Input.

ICC ..•.••.•.•.•...•...•.......
VIO ....•......•........•.•.•..
IBIAS ............•.......•.••.
AVOL (Vo = ±3V) . . . . . . . . . . . . . • .
VOUT ..••..•..................
lOUT··························
CMRR(aVCM =±2.5V) .•.....••
PSRR(aVCC=0.5V) ..•.•...••.
Unity Bandwidth (51 01) . . • . • • • • •
GBW(5111) ..•..•.... ... ...•..
Slew Rate (5101) .........•...•.
SlewRate(5111) .....•..•......

3.7
0.5
56
106
3.7
13
90
90
10
100
7
40

rnA
rnA
nA

KVN

v

Comparator Circuit

rnA
dB
dB

V+

MHz
MHz

6

V/~s
V/~s

v-

Offset Adjustment
The following Is the recommended VIO adjust configuration:

Choose RUM Such That: (aVINMAX -7V) < 2RUM
25rnA
Output Saturation
When an op amp is overdriven, output devices can saturate
and sometimes take a long time to recover. Saturation can
be avoided (sometimes) by using circuits such as:

v+

* Proper decoupling Is always recommended. O.lpF high quality capacitor
should be at or very near the devices's supply pins.

Compensation
An external compensation capacitor can be used with the
HA-5111 connected between pin 8 and ground (or V-, V+
not Recommended). A plot of gain bandwidth product vs.
compensation capacitor has been included as a design aid.
The capacitor should be a high frequency type mounted
near the-device leads to minimize parasitics.
200

-

i==
==
f= =

f= ::

r-- ,1
.1

If saturation cannot be avoided the HA-5101{11 recovers
from a 25%. overdrive in about 6.511S (see photos).

. .
ic.

~
,
,
:II

'

, ......,

~

.,,,

"'"

1

10

loo:lOO

COMPENSATION CAPACITANCE (nF)

3-388

HA-5101/5111
Applications Information (Continued)
TOP: Input
BOTTOM: Output, 5V/Div.,

2~s/Div.

INPUT

OUTPUT

Output is overdriven negative and recovers in 6/ls.
...I
<[

Z

en
a:

OW

~~

Die Characteristics

a: c..
w:;;;

Transistor Count ................................... 54
Die Dimensions ....................... 69 x 69 x 19 mils
(1800 x 1800 x 4~OJ.lm)
Substrate Potential* .....•.......•........... V- or Float
Process .................................. " Bipolar 01
Thermal Constants (OC/W)
HA2-5101/5111 (-2/-5/-7)
HA2-5101/5111 (/883)
HA3-5101/5111 (-5)
HA7-5101/5111 (-2/-5/-7)
HA7-5101/5111 (/883)
HA9P5101/5111 (-5/-9)

* The

aja

al c

192
158
80
190
136
160

52
48
29
102
61
42

Substrate may be left floating (Insulating Die Mount) or it may be

mounted on a conductor at V- potential.

3-389

:5<[

HA-5101/5171

Schematic

.,.

,.

BAL

3-390

BAL

(II

HARRIS

HA-5102/04/12/14
Low Noise High Performance
Operational Amplifiers

August 1991

Features

Applications

Low Noise •••.••••••••••••.••..••••••••• 4.3nV/v'Hz
o Wide Bandwidth •.••.•••••••• BMHz (Compensated)
60MHz (Uncompensated)
• High Slew Rate •••••••••••.••• 3V/~s (Compensated)
20V/~s (Uncompensated)
• Low Offset Voltage ••.•••••.••••••••..•.••.•• O.5mV
o Available in Duals or Quads

High Q, Active Filters
Audio Amplifiers
• Instrumentation Amplifiers
• Integ rators
o Signal Generators
• For Further Design Ideas, See App. Note 554.

o

o
o

Description
Low noise and high performance are key words describing
HA-Sl 02/04/12/14. These general purpose amplifiers offer
an array of dynamic specifications ranging from a 3V/lls
slew rate and 8MHz bandwidth (S102/04) to 20V/lls slew
rate and 60MHz gain-bandwidth-product (HA-Sl12/14).
Complementing these outstanding parameters is a very low
noise specification of 4.3nV/,!HZ at 1kHz.
Fabricated using the Harris high frequency 01
process, these operational amplifiers also offer excellent
input specifications such as a O.SmV offset voltage and
30nA offset current. Complementing these specifications
are 108dB open loop gain and 108dS channel separation.
Consuming a very modest amount of power (90mW/
package for duals and 1S0mW/package for quads),
HA-Sl02/04/12/14 also provide lSmA of output current.

This impressive combination of features make this series of
amplifiers ideally suited for designs ranging from audio
amplifiers and active filters to the most demanding signal
conditioning and instrumentation circuits.
These operational amplifiers are available in dual or quad
form with industry standard pinouts allowing for immediate
inter-changeability with most other dual and quad
operational amplifiers.
HA-Sl02 Dual, Compo
HA-S112 Dual, Uncomp.

HA-S104 Quad, Compo
HA-S114 Quad, Uncomp.

Each of these products are available in -2 (-SSOC to
+12S 0 C), -S (OOC to +7S 0 C), -9 (-400 C to +8S 0 C)
or /883 grades. Refer to the /883 data sheet for military
product.

Pinouts
HA3-51 02/5112 (PLASTIC MINI-DIP)
HA7-5102/5112 (CERAMIC MINI-DIP)
TOP VIEW

HA9P51 02/5112 (SOIC)
TOP VIEW

HA2-5102/5112 (TO-99 METAL CAN)
TOP VIEW
v+

HAl-5104/5114 (CERAMIC DIP)
HA3-5104/5114 (PLASTIC DIP)
TOP VIEW

HA9P5104/5114 (SOIC)
TOP VIEW

OUT I
NC
NC

v+
NC
NC

OUT 2

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @) Harris Corporation 1991

3-391

File Number

2925

...I

+850 C
Storage Temperature Range ••••••••••••• -650 C .::; TA'::; +150oC

Electrical Specifications V+ = 15V D.C., V- = -15V D.C., Unless Otherwise Specified
HA-5102-2, -5
HA-5112-2, -5
PARAMETER

TEMP

MIN

+250C
Full

-

Full

-

TYP

MAX

0.5

2.0
2.5

HA-5104-2, -5
HA-5114-2,-S
MIN

TYP

MAX

0.5

2.5
3.0

HA-5104-9
HA-SII4-9

HA-5t02-9
HA-SI12-9
MIN

TYP

MAX

0.5

2.0
2.5

MIN

TYP

MAX

UNITS

-

0.5

2.5
3.0

mV
mV

INPUT CHARACTERISTICS
Offset Vollaga

Offset Voltage Average Drift

30

75
125

-

±12

-

3

-

+25OC

500

Full

±12

-

+250C
Full

100
100

250

- -

100
100

250

Full

86

95

-

86

95

-

8

-

-

8

-

-

108

±12
±10

±13
±12

±10

±15

+250C
Full

Offs .. Current

+250C
Full

Input Resistance

200
325

3

-

-

Bias Current

Common Mode Ranga

130

-

-

-

-

130

200
325

30

75
125

-

500

-

-

±12

-

3

- -

130

200
500

30

75
125

-

-

500

-

-

-

-

-

-

pV/OC

130

200
500

nA
nA

30

75
125

nA

3

-

-

500

±12

-

80

250

-

-

nA

kn
V

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
(Nota 5)
Common Mode Rejection Ratio
(NotaS)

Small Signal Bandwidth
+25OC

-

Gain Bandwidth Product
HA-51 I 2151 14 (AV - 10)

+25OC

-

60

Channal Saparallon (Note 7)

+25OC

-

106

OutputVoitaga Swing
(RL = 10K)
(RL =2K)

Full
Full

±12
±10

±13
±12

Output Current (Note 8)

HA-510215104(AV~

I)

-

-

60

eo

-

95

-

80

95

-

8

-

-

8

-

MHz

-

-

so

-

MHz

-

106

±12
±10

±13
±12

±7

±15

16
191

47
318

-

110

-

I
10

-

-

80
80

250

80

-

-

-

-

106

-

±12
±10

±13
±12

-

±7

±1S

-

16
191

47
318

-

-

eo

-

kVN
kVN
dB

dB

OUTPUT CHARACTERISTICS

-

-

-

Full

±10

±15

-

Full Power Bandwidth (Note 9)
HA-5102/5104
HA-5112/5114

+250C
+25OC

16
191

47
318

-

16
191

47
318

Output ReSistance

+250C

-

110

-

-

110

-

-

110

-

Full
Full

1
10

-

-

I
10

-

-

I
10

-

-

-

-

-

V
V

mA

kHz
kHz
n

STABtLiTY
Minimum Stable Closed Loop Gain

HA-51 02/51 04
HA-511215114

3-392

VN
VN

Specifications HA-5102/04/12/14
Electrical Specifications (Continued) V+ = 15V D.C., V- = -15V D.C., Unless Otherwise Specified
HA-5102-2, -5

PARAMETER

HA-5102-9
HA-Sl12-9

HA-5104-2, -5
HA-5114-2, -5

HA-5112-2, -5

TYP

MAX

MIN

TYP

MAX

UNITS

-

108
48

200
100

-

108
48

200
100

ns
ns

40

-

20
,30

-

20
30

35
40

%
%

±3
±20

-

±12

±3
±20

-

V/iJS
V/ps

-

4.5
0.6

-

-

-

4.5
0.6

-

-

ps
ps

-

9
4.3

17
6.0

-

-

9
4.3

17
6.0

nV/,;Hz
nV/,;Hz

-

5.1
0.57

12
3

-

5.1
0.57

12
3

pA/,;Hz
pA/,;Hz

-

-

870

3.0
5.0

5.0
6.5

-

100

-

86

TEMP

MIN

TYP

MAX

+250 C
+250 C

-

108
48

200
100

+250 C
+250 C

-

20
30

+250 C
+250 C

±1
±12

±3
±20

+250C
+250 C

-

+2SoC
+250 C

MIN

TYP

MAX

-

108
48

200
100

35
40

-

20
30

35

-

±1
±12

4.5
0.6

-

-

9
4.3

17
6.0

+250C
+250 C

-

5,1
0.57

12
3

+250 C

-

870

+250C
+250C

-

Full

86

MIN

HA-5104-9
HA-Sl14-9

TRANSIENT RESPONSE (Nole 10)
RisaTime
HA-51 02/51 04
HA-511215114

-

Overshoot
HA-51 02151 04
HA-511215114
Slew Rate
HA-51 02/51 04

HA-5112/5114
Setlling Time (Nolell)
HA-5102/5104
HA-5112/5114

-

-

-

±1

-

35
40

±3
±20

-

±1
±12

-

4.5
0.6

-

-

-

9
4.3

17
6.0

-

-

-

5.1
0.57

12
3

-

-

870

-

-

870

-

nVrms

3.0
5.0

5.0
6.5

-

-

3.0
5.0

5.0
6.5

-

-

3.0
5.0

5.0
6.5

mA
mA

100

-

80

100

-

80

100

-

dB

NOISE CHARACTERISTICS
Input Noise Voltage (Note 12)

f=10Hz

f=lkHz
Input Noise Current (Note 12)

f=10Hz
f=lkHz

Broadband Noise Voltage
f = DC 1030kHz

-

-

-

POWER SUPPLY CHARACTERISTICS
Supply Current

HA-5102l5112
HA-5104/5114

Power Supply Rejection Ratio
(Nole6)

NOTES:
1. Absolute maximum ratings are limiting values, applied individual/y.

beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is nol necessarily implied.

B. Output current is measured with VOUT

= ±5V.

9. Full power bandwidth is guaranteed by equation:
Full power bandwidth

2. For supply voltages < ±15V, the absolute maximum input voltage is
equal to the supply voltage.

Slew Rate

=--21'1 Vpeak

10. Refer to Test Circuits section of the data sheet.
3. Anyone amplifier may be shorted to ground indefinitely.
4. Derate 9.6mW/oC above TA

11. Settling time is measured to 0.1 % of final value for a 1 volt input step,

= +2S oC.

and AV = -10 for HA-5112/5114, and a 10 voll inpul slep.
AV = -1 for HA-51 02/51 04.

5. VOUT ~ ±10V. RL ~ 2K

12. Sample tested.

6. VCM = ±5.0V
7. Channel separation value is referred to the input of the amplifier. Input
test conditions are: f = 10kHz; V,N = 200mV peak to peak; RS = 1 kO.
(Refer 10 Channel Separation vs. Frequency Curve for test circuits.)

3-393

HA-5702/04/72/74

Test Circuits
LARGE SIGNAL RESPONSE CIRCUIT
Volts: 5V/Div., Time: 5ps/Div. (AV = -1)
HA-5102/S104

SMALL SIGNAL RESPONSE CIRCUIT
Volts: 40mV/Dlv., Time: 50ns/Div. (AV = +1)
HA-S102/S104

2kA
2kA
INo-......JW\r-.....-t

~~~--~-----oOUT

OUTPUT"

+5V

II

OV

II

200mV
INPUT

-5V

II

\

t- ~

r-:j ff-

+5V

OV

ov _.L. r-

-5V

-

---

---f-.. _f.. - f -

-

r--

-

- - -

--'--

--'-

LARGE AND SMALL SIGNAL RESPONSE CIRCUIT
HA-5112/S114 (AV = +10)
IN 0--------1

>--"""--T--~ OUT

ri;a

OV
-o.5V

INPUT A

I

OUTPUT B

II

+5V

i\

-. ,---

I

+O.5V

INPUT

ov

I

AJ

-5V

I
I

~'

r-- I-'

-

-f-

-

""t
t
f---'
-+
I
I, \

+-

~V

200mV

OV

. L _.

Volts: Input A: O.01V/Div., Output 8: SOmV/Div.
Time: SOns/DiY.

Volts: Input A:. 0.5V/Div., Output B: SV/Div.
Time: 50ns/Div.

SETTLING TIME CIRCUIT
+15V

>-t-..--o VOUT
2kA

• AV=-l (HA-5102/5104),*AV=-10(HA-5112/5114)

• Feedback and summing resistors should be 0.1% matched.
• Clipping diodes are optional, HP5082-2810 recommended.

3-394

HA-5102/04/12/14
Typical Performance Curves
INPUT NOISE VOLTAGE DENSITY
Vee = ±15V, TA = +250e

INPUT NOISE CURRENT DENSITY
Vee = ±15V, TA = +250e

,--------------r-------------,

15

Gt,0~--~.-----_r----------~
~

10

lK

100
FREQUENCV (Hz)

0.1~

10

lUOO

100
FREQUENCY (Hz)

0.1Hz TO 10Hz NOISE
Vee = ±15V, TA = +250e
50I'V/Div.,ls/Div., AV = 1000 VN
Input Noise = 0.232flVP-P

0.1 Hz TO 1MHz NOISE
Vee = ±15V, TA = +250 e
500flV/Div., ls/Div., AV = 1000 VN
Total Output Noise = 2.075flVP-P

VIO vs. TEMPERATURE
Vee = ±15V

VIOVS, Vee
TA= +25 0e

>
~

1.5

~

1

>

~

I
o
-60

-40

-20

20

40

60

80

100

120

10

TEMPERATURE (OCI

12

SUPPLY VOLTAGE (tV)

3-395

14

16

18

HA-5702/04/72/74
Typical Performance Curves

(Continued)
IBIAS vs. TEMPERATURE
Vee=±15V

110 VS. TEMPERATURE
Vee = ±15V
'00
90

Ci -2

<"

oS -4

i
_

80

5

....

10

-6
-8

B -10

~ &0

.....

~-1Z

u

...~

::: -14

~-16

I"--

50

....

40

~ 30

~-18

"

:!!: -20
-22
-24

20

'0

-26 -60

-40

-20

20

40

60

80

100

120

-60

-40

20

-20

TEMPERATURE (OCI

40

60

80

100

12.0

TEMPERATURE (DC)

Icc vs. Vcc
TA = +250 e, lOUT = 0

ICC VS. TEMPERATURE
Vee = ±15V,IOUT = 0

-f- -I-

,
0
-60

-40

-20

20
~
00
TEMPERATURE 10C)

~

100

120

10

AVOL vs. TEMPERATURE
Vee = ±15V, AVo = ±10V, RL = 2K

...
....

f-'"

-

12

14

16

,.

SUPPLY VOLTAGE (:tV)

AVOL vs. LOAD RESISTANCE
Vo = ±10V, Vce = ±15V, TA = +250 C

- 3- --

,

...--.....-

f-

...-

+125 OC

~

I

-550~

I

,.

o
-60

-40

-20

2.

4.

LOAD RESISTANCE (n)

20

40

60

80

100

120

TEMPERATURE (OCI

3-396

I

6K

BK

10K

HA-5102/04/12/14
Typical Performance Curves

(Continued)

AVOLvs. VCC
TA = +25 0 e, RL = 2K

VOUTVS. Vce

TA

290 r-r-r-r-r-r-r-r-r-r-r-r-r-r-r-r-r-.-.
280

260
21D

'3

I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-I-H
Ir.::l=l=l=l=l=l=l=l=l=b:~j:::j::j::;t=t=!=j

12

11
;:10

~~~ I-t-t-t-t-I-I-~~t-t-t-I-I-I-I-I-H

.

.t! 9

~230 I-t-t-+-t-t-~~t-t-I-t-I-I-I-I-I-~

~

220

= +250 e, RL = 2K

./

:! 8

I-t-+-+-+-~~t-t-I-I-I-I-I-I-I-I-~

'L

...i);

~ 210 I-t-I-+-I-~I-t-t-I-I-I-I-I-I-I-I-~
g zoo I-t-t-+-t.f-t-t-t-t-I-t-I-I-I-I-I-~
~ 190 I-I-I-+-~I-I-I-I-I-I-I-I-I-I-I-I-~

~

~

~ tBO I-I-I-+-~I-I-I-I-I-I-I-I-I-I-I-I-~
c
~+-+-+'~+-+-+-+-+-+-+-+-+-+-I-I-~
'60 I-I-I-~+-+-I-t-t-t-t-t-t-t-t-I-I-~
'50 I-I-I-~+-t-I-t-t-t-t-t-t-I-t-I-I-~
I-I-+-f-+-+-+-t-t-t-t-t-t-t-t-I-I-~

i

"0

5
4

'.0

'30 L-L-L-L-L-L-L-'---L-LJ'---LJLJLJLJ.-JLJ'--J

10

12

14

16

18

'0

OUTPUT SHORT-CIRCUIT CURRENT VS. TIME
Vee = ±15V, TA = +250 e

I'....

14

16

18

CMRR VS. FREQUENCY

-20

--

VOlT'-'!V

r--... "'-

I-'"

iii -40

'""'"'
'c.J_60
"

VOUT "'+15V

20
50

12

SUPPLY VOLTAGE (.:tV)

SUPPLY VOLTAGE (.tV)

100

1bD

200 250
JOO
TIME (SECONDS)

350

400

I-'

I...-""

450

-80

L
-'00

,K

'M

tOOK

'OK

HA-5104 CHANNEL SEPARATION vs. FREQUENCY
10Hz ~ f ~ 10MHz

PSRR VS. FREQUENCY

-BOdD
;

I'"

-20

~

~-10DdB

z

c

ti

~ -40

-80

~

+PSRR

~ -60

"'w
~

S-no

~

III

,.

z

~

......

-<-

........

~

10K

-140 dB

-PSRR

IIIII

IIIII

-'00

'K

i-"

dB

~

w

tOOK
FREQUENCY 1Hz)

'0

'M

3-397

'00

lK

10K
tOOK
FREQUENCY (Hz)

'M

'OM

HA-5102/04/12/14
Typical Performance Curves

(Continued)

HA-51 04/02 UNITY GAIN FREQUENCY RESPONSE
VCC ±15V, RL 2K, CL 50pF

=

=

HA-5112/14 FREQUENCY RESPONSE
AVCL 10, TA +25 0 C, RL 2K, CL 50pF

=

=

=

=

=

25

225

G~'~ I

20

-550C
GAIN

-

-

.r

+1250C

~ ~

;~~;i
III

-24

tOOK

10K

100

~

.

~>

I IIN..l1 Il'I"-

60

~

1'1

10M

~

~

0

~

-5

PHASE_
-15

-25
100

l"-

i'
i'
45

1.

98

HA-5102/5104

135

I

I\.
10K

lK

180
100M

10M

tOOK
1M
FREQUENCY (Hz)

10K

tOOK

10M

1M

100M

SMALL SIGNAL OVERSHOOT VB. CLOAD
VCC ±15V, TA +250 C, RL 2K

=

=

=

!

tOO
lK
lOAD CAPACITANCE (pF)

=

10K

t=~

..
~

f

SLEW RATE VS. TEMPERATURE
RL 2K, CL 50pF, VCC ±15V

=

,.

FREOUENCY (Hz)

HA-5112f5114
PHASE

100

1111
1111

-20
-225

'OM



-40,

-211

20

40

60

100

10

6

c

"-

-5 0

0
..ICJ

TA=+2S oC

\

....... r.

-2

.

'"""

VCC"±15V

-

r--..

•
•
-, •

= :l:15V

NOISE CHARACTERISTICS

r-...

4

VOLTAGE NOISE

-

r-

UI

J UIII~ J

'"-

120

TEMPERATURE {OCI

IcIJ~~I;~T
N~IS'
~;;',.,.

'00

10

1111111

,.

"-

10.

,M

tOOK

FREQUENCY (Hz)

NOISE vs. SUPPLY VOLTAGE

CMRR vs. FREQUENCY
14 0
12 0

i'-

100

~

r--.

0
8

u,

:--.

~

0

.....

0

......

0
IZ

10

16

14

18

2D

0
10

SUPPLY VOL rAGE (±VDl TS D.C.)

100

OFFSET VOLTAGE DRIFT vs. TIME

7
(uV)

I

I

TA~

+45oC _

6.0

I

>"-

.....
y~

6

~ ~ V' J--

w
z
<
J:

"
W

<

4.0

3.0

~
0

>

4

Iii

"'......

10

20

DAYS

30

tOOK

,.

I"'
10M

40

0

,..,.--

5.0

(!l

(!l

5

o

10K
FREQUENC't (HI)

OFFSET VOLTAGE WARM UP DRIFT

9
8

,.

L

r

2.0

1.0

0.0

~ .,,-

f"
0.0

3-402

5 TYPICAL UNITS

I

I

2.0
3.0
4.0
1.0
TIME AFTER POWER ON (MINUTES)

5.0

HA-5127
Typical Performance Curves

Unless Otherwise Specified: TA = +250 C. VSUPPLY = ±15V

PSRR VS. FREQUENCY

,

14 D

r-r-

12D

...... _PSRR

...... 1--..

D

GAIN
I

D
......

D

i'

"-

.PSRR

IdB)

lOOK

tDEGREES}

1'1..
......

,

-,,
-,,

~
10K

,

-1 D

D

1K

II
PHASE

I"-

D

100

II

,

......

......

D
10

II

,

............

10 D

CLOSED LOOP GAIN AND PHASE VS. FREQUENCY

10M

1M

FREOUENCY IHd

,

"

1

100

10M

1M

lOOK

10K

IK

100M

FREQUENCY 1Hz)

NORMALIZED SLEW RATE vs. TEMPERATURE

AVOL AND VOUT vs. LOAD RESISTANCE
11

16
15

-

TA=+25 0 C

14

g
~

",

13
12

/
1/

.

~ 11

~ 10

~
g

=

--

~

--

1.05
~

RU

1.0J

r-

TA=+250C

'.I'"

CL"50pf

Your

""

/
/'

1.01

//

1.0

V
V

0.'1

10

,

LOAD RESISTANCE (0)

""""

/

•
0.',

0.'

/

0.'

0.' 5
-60

-20

-40

2D

4D

TEMPERATURE (DC)

"

28
-

VO"DV
Vee= ±15V

./
./

2.110

24

./
./

2.71

"

./
./

2.76

18

/'

2.74

·~L"KI

TA=250C _

\.

"\.

12

":---.... ........

/.
./

/'

2.10

u.

DA

./

D.'
FREQUENCY (Mllz)

V

-55

........
-~

./

"

125

TEMPERATURE loCI

3-403

-

CL"SDpF-

\.

/'

2.72

100

VOUT MAX vs. FREQUENCY
UNDISTORTED SINEWAVE OUTPUT

SUPPLY CURRENT vs. TEMPERATURE
2.B2

"

a:

Il.

w:;;;

15<

1.02

II
I

•

1.04

--'
-+-+-<> OUT

>--.-.-.-0 OUT

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

Vertical Scale: (Volts: Input = O.5V/Div.)
(Output = 5V/Dlv.)
Horizontal Scale: (Time 1Jls/Div.)

Vertical Scale: (Volts: 100mV/Div.)
Horizontal Scale: (200ns/Div.)

=

3-405

HA-5127
Typical Performance Curves

Unless Otherwise Specified: TA = +25 0 C, VSUPPLY = ±15V
SETTLING TIME TEST CIRCUIT

SK.n

• AV =-1

• Feedback and summing resistors
should be 0.1% matched.

2K.n

• Clipping diodes are optional.
HP5082-2610 recommended

SUGGESTED STABIUTY CIRCUITS

Low resistances are preferred for low noise applications as a 1 KO resistor has 4nV/VHz of thermal noise. Total
resistances of greater than 10Kn on either input can reduce stabilUy. In most high resistance applications. a few,·
picofarads of capacitance across the feedback resistor will improve stability,

3-406

HA-5127
0.1 Hz TO 10Hz NOISE WITH ACL = 25,000V/V

Die Characteristics
Transistor Count ..........•........................ 63
Die Dimensions .................... 65 x 104.3 x 19 mils
(17001lm x 2600/lm x 480/lm)
Substrate Potential' ................................ vProcess .................................... Bipolar-DI
Thermal Constants (OC/W)
9ja
9jc
HA7-5127 Ceramic Mini-DIP
160
79
HA2-5127TO-99 Metal Can
172
48
*The substrate may be left floating (Insulating Die Mounl) or it may be
mounted on a conductor at V- potential.

Horizontal Scale = 1sec/Diy.
Vertical Scale = O.002J.1V/Oiv.
O.OBpVp-p

3-407

HA-5130/35

mHARRIS

Precision Operational Amplifier

August 1991

Features

Applications

• Low Offset Voltage ..... .. • • • .. • .. • • .. • .. • • ... 10llV

• High Gain Instrumentation

• Low Offset Voltage Drift •••••••••••••••••. O.4IlVloC

• Precision Data Acquisition

• Low Noise ............................... 9nV/y'HZ

• Precision Integrators

• Open Loop Gain ............................. 140dB

• Biomedical Amplifiers

• Unity Gain Bandwidth •••••••••••••••••••••• 2.5MHz

• Precision Threshold Detectors

• Ail Bipolar Construction

Description
The Harris HA-5130/5135 are precision operational
amplifiers manufactured using a combination of key
technological advancements to provide outstanding input
characteristics.
A Super Beta Input stage Is combined with laser trimming,
dielectric isolation and matching techniques to produce
251lV (Maximum) input offset voltage and O.41lV/OC Input'
offset voltage average drift. Other features enhanced by this
process include 9nV/y'HZ (Typ.) Input Noise Voltage, 1 nA
Input Bias Current and 140dB Open Loop Gain.
These features coupled with 120dB CMRR and PSRR
make HA-5130/5135 an ideal device for precision DC

Pinouts

instrumentation amplifiers. Excellent Input characteristics In
conjunction with 2.5MHz bandwidth and O.8V/lls slew rate,
make this amplifier extremely useful for precision
integrator and biomedical amplifier designs. These
amplifiers are also well suited for precision data acquisition
and for accurate threshold detector applications.
HA-5130/5135 is packaged in an 8 pin (TO-99) Metal Can
and an 8 lead Cerdip and is pin compatible with many
existing op amp configurations. It offers added features
over the Industry standard OP-07 in regards to bandwidth
and slew rate specifications. For the military grade
product. refer to the HA-5135/883 data sheet.

Schematic

HA7-5130/5135 (CERAMIC MINI-DIP)
TOP VIEW

BAL

BAL 1

·IN

v+

+IN

OUT

v-

BALl

HA2-5130/5135 (TO-99 METAL CAN)
TOP VIEW
BAL 1

(Both BAL 1 Pins are Connected Together
Internally)
CAUTION: These devices are sensitive
Copyright @) Harris Corporation 1991

to electrostatic discharge. Proper I.C. handling procedures should be followed.

3-408

File Number

2907

Specifications HA-5130/5135
Absolute Maximum Ratings (Note 1)

Operating Temperature Ranges

TA '" +25 0 C Unless Otherwise Slated
Voltage Between V+ and V- Terminals .•••.••.••••••••••• 40.0V
Differenliallnput Voltage •.•..•..•••.•••••.•••.••..••.•. ±15.0V
Output Short Circuit Duration •..•••.••..•...••..•..•• Indefinite
Power Dissipation (Note 2) •••....••..••...•..•.••••.•• 300mW

HA-5130/5135-2 ••..•••••••••••••••••• -550C~TA:OS'+1250C
HA-5130/5135-5 •••..•.•••.•.•....••.•.•• oOC :os.TA:os. +750 C
Storage Temperature Range •••.••.•..•.• -65°C :os. TA :os. +1500 C

Electrical Specifications V+ '" +15V, V- '" -15V
HA-5130-2/-5
PARAMETER

TEMP

HA-5135-2/-5

MIN

TYP

MAX

-

10
50
0.4
±1

0.02

25
60
0.6
±2
±4
0.04
2
4
0.04

-

-

±12
20

30

-

0.6

-

-

-

18.0
13.0
11.0
30

-

-

13.0
10.0
9.0
15

-

0.4
0.17
0.14

0.8
0.23
0.17

+250 C
Full
Full
+25 0 C

120
120
110
0.6

140

-

+250 C
Full
+250 C
+250 C
+25 0 C

±10
±10
8
±15

10
±20
45

-

340
0.8
11

-

MIN

TYP

MAX

UNITS

10
50
0.4
±1

75
130
1.3
±4
±6
0.04
4
5.5
0.04

0.6

IlV
IlV
IlV/OC
nA
nA
nAJDC
nA
nA
nAJOC
V
MO
IlVp-p

13.0
10.0
9.0
15

18.0
13.0
11.0
30

nVl.,jHz
nVl..jHZ
nVl.,jHz
pAp-p

OA
0.17
0.14

0.8
0.23
0.17

pNyHz
pN.,jHz
pNyHz

120
120
106
0.6

140

-

dB
dB
dB
MHz

±10
±10
8
±15

±12

-

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current
Bias Current Average Drift
Offset Current
Offset Current Average Drift
Common Mode Range
Differential Input Resistance
Input Noise Voltage 0.1 Hz to 10Hz (Note 3)
Input Noise Voltage Density (Note 3)
'0'" 10Hz
'0'" 100Hz
'0'" 1000Hz
Input Noise Current 0.1 Hz to 10Hz (Note 3)
Input Noise Current Density (Note 3)
'0'" 10Hz
'0'" 100Hz
'0'" 1000Hz

+250 C
Full
Full
+250 C
Full
Full
+250 C
Full
Full
Full
+25 0 C
+250 C
+250 C

-

-

-

0.02

-

±12
20

30

-

+250 C
+250 C

-

-

-

-

-

0.02

-

0.02

-

-

-

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 4)
Common Mode Rejection Ratio (Note 5)
Closed Loop Bandwidth (AVCL '" +1)

120
2.5

120
2.5

-

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 6)
Full Power Bandwidth (Note 7)
Output Current (Note 8)
Output Resistance (Note 8)

±12

-

-

-

10
±20
45

-

V
V
kHz
mA

-

0

-

340
0.8
11

-

ns
VlIlS
Ils

1.0
130

1.7

mA
dB

-

TRANSIENT RESPONSE (Note 10)

-

+25 0 C
+25 0 C
+250 C

Rise Time
Slew Rate
SeHiing lime (Note 11)

0.5

-

0.5

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 12)

-

Full
Full

1.0
130

100

1.3

-

-

94

-

NOTES:
1. Absolute maximum ratings are limiting values. applied individually
beyond which the serviceability of the circuit may be impaired. Funtional
operability under any of these conditions is not necessarily implied.

2. Derate at e.8mWJOC for operation at ambient temperatures above +750C.
3. Not tasted. 90% of units meet or exceed these specifications.

4. VOUT = :1:1 OV; RL = 2K.

5. VCM

~

Gain dB = 20 logl 0 Av
:.120dB = lMVN
140dB= 10MVN

7. RL = 2Ki Full power !Jandwldlh guaranteed based on slew rate
measurement using FPBW = SLEW RATE

2nVpEAK
8. VOUT = 10V
9. Output resistance measured under open loop conditions (f

100Hz).

11. Settling time is measured to 0.1 % of final value for a 10V output step and

AV

:l:l0V DC

6. RL = 600n.

=:

10. Refer to test circuits section of the data sheet.
~-1.

12. VSUPPLY = :l:5V DC to :l:20V DC.

3-409

....I

«en

:z a:
OW

~~
~~

o

HA-5130/5135

Test Circuits
SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT

>-.-.........-0

IN

OUT

SMALL SIGNAL RESPONSE
Vertical Scale: (Volts: 5OmV/Div. Output)
(Volts: 100mV/Div.lnput)
Horizontal Scale: (Time: 1I'1sDiv.)

LARGE SIGNAL RESPONSE
Vertical Scale: (Volts: 5V/Div.)
Horizontal Scale: (Time: 5ps/Div.)

1
l

INPUT

OV

f\
OV

INPUT

"~

l/
OUTPUT

11

OV

OUTPUT

/'

"-

.......

r--....

OV

SETTLING TIME CIRCUIT

TO
. -....- - 0 OSCILLOSCOPE
2kr2

>--.....--.....----0 VOUT
100pF

• Av=-1.
• Feedback and summing resistors should be
0.1 % matched.

• Clipping diodes are optional.
HP5082-2810 recommended.

2kr2

3-410

HA-5130/5135
Typical Performance Curves
INPUT OFFSET VOLTAGE, INPUT BIAS AND
OFFSET CURRENT vs. TEMPERATURE

"-

~ 80
w

~
g

50

o~

40

..

'""'-.. INPUT BIAS CURRENT

;;
.E

60

t;

~

~

70

INPUT BIAS CURRENT vs. DIFFERENTIAL INPUT VOLTAGE

....
iiia:

....

a:

'\ ~

30

""-

0
0
0

-80

.......

,- .......

::>

INPUT OFFSET CU RENT

'""'-..

""-

./"
IVOS
.>r--... TYP~lAL-

r

+80

+40

-40

~

1

-2

;;;-4

ffia:
a:

V

f-""

-6

a

-4
+160

+120

-10

-8

HA-S130 OFFSET VOLTAGE STABILITY vs. TIME

bO~DIr,6Js, I

~

3:

0

t:

oa:

II

~~

ENVIRONMENTAL SYSTEMS

1A

12

1.2

-~

-5

~~ -10

...

~

2 4 6 8 10

20

30

~

10

~
g
III
oz

ZATION PERIOD.

------

\"'--

8

\

6

4

\

~ECURRENT

lK

100

10

~ 160

~

§
z

::!

~

80
60

00

1
1

140

~'00

..... .......

45 0

~ASEANGLE

GAIN

........

40
20

"-

1350

........ .\.

0

0_20

1

10

100

lK

10K

FREQUENCY (Hz)

3-411

tOOK

"'o
z

ffi

,6

1M

"

1800

10M

!i
u

~

.4 ~

/
10K

FREQUENCY (Hz)

1-""""
~ 120 t-...."

1.0 w

a:

OPEN LOOP FREQUENCY RESPONSE

g

..-""

.7

o

40

~

1

NOISE vlLTAGE

TIME-DAYS

i

10

14

w

ALLOWED 12 HOUR STABILI-

6

-2

INPUT NOISE vs. FREQUENCY

NOTE: MEASUREMENT AND

:I:

t:

I

VSUPPLY '" ±15V
TC=±l oC
AV= 1000

w

-4

-6

DIFFERENTIAL INPUT VOLTAGE (VOLTS)

TEMPERATURE lOCI

~ 10

-

v

,-

0

.2

tOOK

HA-5130/5135
Typical Performance Curves

(Continued)
SMALL SIGNAL BANDWIDTH AND
PHASE MARGIN vs. LOAD CAPACITANCE

CLOSED LOOP FREQUENCY RESPONSE
FOR VARIOUS CLOSED LOOP GAINS
0
iii 70
:!!
z" 60

......

"

~50

:s

60<>

~

4

5QO

I"..

"""'-

9 30
~20
9u 10

,

-1 0

10

100

.

""

:E

~

'"

10K
100K
lK
FREQUENCY 1Hz)

PHASE MARGIN

C; 400
a:

"..4

0

2.6

z

1M

300

:1:

b
ia

2.5

BANDWIDTH

it
200

10M

00
10

100

35

~

~

2A

\'

1000

2.35

10.000

MAXIMUM OUTPUT VOLTAGE SWING vs.
LOAD RESISTANCE AND SUPPLY VOLTAGE

~
0

VSUPPLVf,±I~

25

~

'"z

I.

20

~

..!:i'"

VSUPPLY-~OV

30

VSUPPL

,"1±10V

W

"

16

0

> '0

I-

~

"

0

r- VSUPPlr:±5V

5

100

I

1K

~

AL·2K

~

30

~0

25

'"z

20

~

~\

~

W

~
g

\
_\

f

10

I-

~

"

"""- t-..

10K
FREQUENCY IHzl

(VSUPPLY=-:±1s1

15

0

100K

1M

/'

1K

LOAD RESISTANCE (OHMS)

I

1.1

B~NDWlbTH

~!;t 1.0

Vl

a: W

.f~O.9
~>

I/-+SLEWRATE

Oe-o.8

~fit

i~ 0.7
a:~
owO.S

z a:

VSUPfL Y • ±10V

VSUjLY.±5V
100

NORMALIZED AC PARAMETERS vs. SUPPLY VOLTAGE

ffi~
Iii"

I

1

'0

0

±2

:t4

ta ±10 ±12 ±14 ±16 ±18 ±2O
SUPPLVVDLTAGE (VOLTS)

±6

3-412

z

"

LOAD CAPACITANCE IpF)

OUTPUT VOLTAGE SWING vs.
FREQUENCY AND SUPPLY VOLTAGE

...
z

~

100

~

!i

10K

HA-5130/5135
Typical Performance Curves

(Continued)
PSRR vs. FREQUENCY

CMRR vs. FREQUENCY
140

140

-..........

120

~

100

:;

"60
40
20

10

100
IK
FREQUENCY IHd

'"""

iii

:!lBQ

a:
a:

!e60

"- r-....

40

'"

10K

~

100

'"""""

:c
:!l80
II:
a:

0,

-.........

120

20
0

lOOK

01

~~ 10
5

CO
... :;

5~

> ..
.....
=>!:i

0
-5

~!LIO0
o

10mV

V. V
'I"---- t--10mV

2

4

....



I'"-' ~
14

"-'>

..

16

II:
=>

~<

±t.D

a:
a:

tmv'

•

look

.!

±tA

k ~~
tmV

8
10
12
SETTLING TIME Ip,l

10K

POWER SUPPLY CURRENT vs.
TEMPERATURE AND SUPPLY VOLTAGE

SETTLING TIME FOR VARIOUS OUTI1UT STEP VOLTAGES

1;;-'
~g

100
lK
FREQUENCY IH,I

10

VS ... +5V

±.6
±A

±.2
0
-80

-40

0

<40

+80

+120

+160

TEMPERATURE lOCI

Applying the HA-5130/5.135 Operational Amplifiers
1. POWER SUPPLY DECOUPLlNG: Although not absolutely
necessary, it is recommended that all power supply lines
be decoupled with 0.011lF ceramic capacitors to ground.
Decoupling capacitors should be located as near to the
amplifier terminals as possible.
2. CONSIDERATIONS FOR PROTOTYPING: The following
list of recommendations are suggested for prototyping.
• Resolving low level signals requires minimizing
leakage currents caused by external.clrcuitry. Use of
quality Insulating materials, thorough cleaning of
insulating surfaces and implementation of moisture
barriers when required is suggested.
• Error voltages generated by theromocouples formed
between dissimilar metals in the presence oftemperature gradients should be minimized. Isolation of low
level circuity from heat generating components is
recommended.

3. When driving large capacitive loads (> 500pF), a small
value resistor (z 500) should be connected in series
with the output and inside the feedback loop.
4. OFFSET VOLTAGE ADJUSTMENT: A 20kO balance
potentiometer is recommended if offset nulling is
required. However, other potentiometer values such
as 10kO, 50kO and 100kO may be used. The minimum
adjustment range for given values is ±2mV.
5. SATURATION RECOVERY: Input and output saturation
recovery time is negligible in most applications. However,
care should be exercised to avoid exceeding the absolute
maximum ratings of the device.
6. DIFFERENTIAL INPUT VOLTAGES: Inputs are shunted
with back-to-back diodes for overvoltage protection. In
applications where differential input voltages in excess
of 1V are applied between the inputs, the use of limiting
resistors at the inputs is recommended.

• Shielded cable input leads, guard rings and shield drivers are recommended for the most critical applications.

3-413

HA-5130/5135
Applications
OFFSET NULUNG CONNECTIONS

PRECISION INTEGRATOR

c

V+

----,
I
I
I
I

R

I

OUT

I

OPTIONAL
CONNECTION

I
I

I
I
I

_ _ ...J

* Although Rp is shown equal to 20K, other values such as SOK, 1OOK and

1 M may be used. Range of adjustment Is approximalely :l::2.5mV. Vas TC
of tile amplifier Is optimized at minimal VOS'
Tested Offset Adjustment Is I Vos + 1mV I minimum referred to output.

The excellent Input and gain characteristics of HA-5130 are well suited for
precision Integrator applications. Accurate integration over seven decades of
frequency using HA-5130, virtually nullifies the need for more expensive
chopper-type amplifiers.

ZERO CROSSING DETECTOR

INPUT

OUTPUT
!o13V
2001l./DIV

INPUT

±'5mV
2001l,/DIV.

RIN

)

1\
.1 .\

l

II.

"I

II'
1\

I

I

o--NV'-1
I

I
I
1----- -./IN'----~
:

J

-

'

:

I

I

~

I

Low

Ves

RF

I

• Optional for Output
Swing Limiting

coupled wilh high open loop Gain. high CMRR and high PSRR

make HA-S130 ideally suited for precision detector applicalions.

PRECISION INSTRUMENTATION AMPLIFIER (AV
2K

2K

500n
+15V

2K

3-414

2K

= 100)

m

HA-5134

HARRIS

Precision Quad Operational Amplifier

August 1991

Features

Applications

• Low Offset Voltage •••••••••••••••••••••• Max 200flV

• Instrumentation Amplifiers

• Low Offset Voltage Drift •••••.•.••.•••• Max 2flVfoC

• State-Variable Filters

• Offset Voltage Match (5134A) •• Full Temp. Max 250flV

• Precision Integrators

• High Channel Separation •••••.•••••••••••••• 120dB

• Threshold Detectors

• Low Noise •••••••••••••••••••.••••.•••••• 7nVfVHz

• Precision Data Acquisition Systems

• Wide Unity Gain Bandwidth .•.••••.•.••••••••• 4MHz

• Low-Level Transducer Amplifiers

• High CMRR/PSRR (Typ) •••••••••••••••••••••• 120dB
• Dielectric Isolation

.....

Description

« en
za::

The HA-5134 is a precision quad operational amplifier that
is pin compatible with the OP-400, LT1014, OP1',
RM4156, and LM148 as well as the HA-4741. Each
amplifier features guaranteed maximum values for offset
voltage of 200flV, offset voltage drift of 2flV/oC, and offset
current of 75nA over the full military temperature range
while CMRR/PSRR is guaranteed greater than 94dB and
AVOL is guaranteed above 750kVN from -550 C to
+1250 C.
Precision performance of the HA-5134 is enhanced by a
noise voltage density of 7nV/..(Ffi. at 1kHz, noise current
density of 1pN..(Ffi. at 1kHz and channel separation of
120dB. Each unity-gain stable quad amplifier is fabricated

using the dielectric isolation process to assure performance
in the most demanding applications.
The HA-5134 is ideal for compact circuits such as
instrumentation amplifiers, state-variable filters, and
low-level transducer amplifiers. Other applications include
precision data acquisition, precision integrators, and
accurate threshold detectors in designs where board space
is a limitation.
The HA-5134-2 has guaranteed operation from -55OC to
+125 0 C and can be ordered as a military grade part The
HA-5134-5 is guaranteed from OOC to +750 C and all devices
are available in ceramic dual-in-line packages. For military
grade product, refer to the HA-5134/883 Data Sheet

Schematic

Pinout

(Each Amplifier)

HA1-5134 (CERAMIC DIP)
TOP VIEW

OUT 1

OUT 4

-IN 1

-IN4

+ IN 1

+IN4

V+

V-

+IN2

+IN3

-IN2

-IN3

OUT 2

OUT 3

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @) Harris Corporalion 1991

3-415

File Number

2926

OW

~§
a::

0-

w:;;
~«

Specifications HA-5134
Absolute Maximum Ratings

Operating Temperature Ranges

(Note 1)

TA = +250 C Unless Otherwise Stated
Voltage Between V+ and V- Terminals •••••••••••••••.••• 40.0V
Differential Input Voltage (Note 2) ••••.••••••••••••••••••• :l:6.0V
Internal Power Dissipation (Note 3) ••..••••••••••••••••• 800mW
Output Current ••••••••••.••••••.••• Full Short Circuit Protection
Voltage at any Op Amp Terminal ••••••••••••••••••••••••• V+, VMaximum Junction Temperature •••••.••.•••.•••••••..• +1750 C

Electrical Specifications

HA-5134N5134-2 •••••••••••••••••.••• -550C::: TA::: +1250 c
HA-5134N5134-5 •••••••••.•••••••.•••••• 0 0C::;TA:::+750 C
Storage Temperature Range ••••••••••••• -650C::; TA ::: +150o C

VCC = :l:15V, RLOAD = 2K, CLOAD = 50pF, Rs::; 1000 Unless Otherwise Specified
HA-5134A-2/-5

PARAMETER

TEMP

MIN

+250 C
Full
Full
Full
+250 C
Full
+250 C
Full
Full
Full
+250 C
+250 C
+250 C

-

HA-5134-2/-5

TYP

MAX

50
75
0.3

100
250
1.2
250
:1:25
:1:50
25
50

MIN

TYP

MAX

UNITS

50
75
0.3

200
350
2

:1:10
:1:20
10
15
0.05

:1:50
:1:75
50
75

IN
"V
"VloC
"V
nA
nA
nA
nA
nAfOC
V
MO
"Vp-p
nVl.,jHZ
nVlv'H!
nvt/Hz

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Offset Voltage Match
Bias Current
Offset Current
Averege Offset Current Drift
Common Mode Range
Differential Input Resistance
Input Noise Voltage (0.1 Hz to 10Hz)
Input Noise Voltage Density
fO =10Hz
fO = 100Hz
fO = 1kHz
Input Noise Current Density
fO = 10Hz
fO= 100Hz
fo= 1kHz

:1:10

-

-

+250 C

-

-

:1:10
:1:20
10
15
0.05

-

30
0.2
10
7.5

7
3
1.5
1

-

:1:10
-

-

-

30
0.2
10
7.5
7
3
1.5
1

-

-

pNVHz

pN~
pNVHz

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
(VOUT = :l:10V)
Common Mode Rejection Ratio
(VCM =:l:10V)
Minimum Stable Gain
Unlty-Galn Bandwidth

4

-

12
120

13.5
20
16
136

-

-

200
1.0
20
13

400

6.5
120
115

8

+250 C
Full
+250 C
Full
+250 C
+250 C

1500
1000
115
110
1

Full
+250 C
+250 C
+250 C

12

-

3000
2000
120
115

-

1200
750
100
94
1

3000
2000
120
115

-

-

4

-

VlmV
VlmV
dB
dB
VN
MHz

OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Full Power Bandwidth (Note 4)
Channel Seperation (VOUT = :l:10V)

-

-

12

-

12
120

13.5
20
16
136

-

200
1.0

400

20

40

-

V
mA
kHz
dB

TRANSIENT RESPONSE (Note 5)
Rise TIme (Note 6)
Slew Rate
Overshoot
Settling Time (Nole 7)

+250 C
+250 C
+250 C
+250 C

0.75

40
-

-

0.75

-

13

-

6.5
120
115

8

ns
VI"s
%

lIS

POWER SUPPLY CHARACTERISTICS
Supply Current (All Amps)
Power Supply Rejection Ratio (Note 8)

-

Full
+250 C
Full

110
100

-

100
94

-

mA
dB
dB

NOTES:
1. Absolute maximum ratings are limiting values, applied Individually beyond
which the serviCeability of the circuit may be Impaired. Functional
operability under any of these conditions Is not necessarily implied.

4. Full power bandwidth guaranteed based on slew rate measurement using

2. For differential input voltages greater than 6V, the Input current must be
limited to 25mA to protect the back-lo-back tnput diodes.

5. Refer to Test Circuits section of the data sheat.

3. Derate at 10mWJOC for ambient temperatures greater than +9So C.

7. Specified to 0.01% of a 10V step, AV = -1.

FPBW -

SLEW RATE : Vpaak = 10V
2,VPEAK

6. Time from 10% to 90% of 200mV output step. AV
8. Vs = ±5V to ±18V.

3-416

= 1.

HA-5134
Test Circuits
SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT

IN

>-......~~-.......-o OUT
50pF

SMALL SIGNAL RESPONSE
Vertical: 5OmV/Div. Horizontal: 200ns/Div.
TA = +250 C, VCC = ±15V
AV +1, RL 2K, CL 50pF

=

=

LARGE SIGNAL RESPONSE
Vertical: 2V/Div. Horizontal: 2JlslDiv.
TA = +250 C, VCC = ±15V
AV +1, RL 2K, CL 50pF

=

=

=

=

~cn
za:

Ow
-;:;:

~~
w::;;;
~<

PEAK-TO-PEAK NOISE O.lHz TO 10Hz
TA +250 C, VCC
±15V, AV 1000

SETTLING TIME CIRCUIT

=

=

TO

1-....- - 0 OSCILLOSCOPE

2Hl

VIN

o--....-"NV'-....-t
2kQ

=

enp_p 0.167JlVp_p
0.05JlV/Div., 1s/Div.

2kQ
• AV = -1.
• Feedback and summing resistors should be 0.1 % matched.
• Clipping diodes are optional. HP5082-2810 recommended.

3-417

=

HA-5134
Performance Curves
VIO WARMUP DRIFT
TA = +250 C, VCC = ±15V

INPUT OFFSET VOLTAGE VS. TEMPERATURE
&0
50

~

~
~

-1

~ ./

,..,

....-

30

:;;

5 -2 1\./r-\
~-3

3

2

......

20
10

.......

t;

~

I-

~

0>-4

r--.

40

,

-10
-20

"

-30

~

-40

-5

-50
-&

o

10

-40

-20

-3

100

120

~

.... r-,

~
~

w

z
z
c

.. -4

~

-5

-6
-60

-40

-

m

'"..z
i

I'-

E -1
~

80

CHANNEL SEPARATION vs. FREQUENCY

......

-2

&0

TEMPERATURE (OC)

OFFSET CURRENT vs. TEMPERATURE
ACL = +1, VCC = ±15V

~

40

20

TIME (MINUTES)

1

~
I'

-60
-&0

-20

20

40

60

80

100

--

-

- -

40

80

120

I--~

-~

120

10

TEMPERATURE (OC)

lK

100

10K

lOOK

FREQUENCY (Hz)

REJECTION RATIOS vs. TEMPERATURE
VCC = ±5Vlo ±20V, VCM = ±10V

NOISE VOLTAGE DENSITY vs. FREQUENCY
10

128

1

127

~

'iii 126

'"!;i
1:1

125

"-

,

..

POSITIVE -

:; 124

r-.

.. § -123
~

PSRR

......

...

"I--

t-

I

"'

/~EGATIVE
PSRR

122

121

f-

120
-60

f-4tI

CMR/

-rT

-20

l"- I--::: 1--1-- --l
I
-r-t-f
20

40

60

80

100

o

1

r....
200
FREQUENCY (Hz)

120

TEMPERATURE (OC)

3-418

400

HA-5134
Performance Curves

(Continued)

CMRR vs. FREQUENCY

PSRR vs. FREQUENCY

-

--

..

-

-

20

~

:s

'"'"

1i

~
40

40

·PSRR

ftttlf-t-I-tHf!I!--t-Hftt+IIt-+J.I"I'HIlII--H+fttlil

",

60

~

+PSRR

""":~'.LI-...J...J..J.W~..J.....;L.1.J.~:::-'L....LLllJ~:-'-.J...J..LLI.':'!
100
lK
10K
lOOK
1M

100

lK

1M

"

FREQUENCV (Hz)

CLOSED-LOOP FREQUENCY RESPONSE vs. TEMPERATURE

I

I

lOOK

10K

FREQUENCY IH,)

~

II

V

80
.80

CLOSED-LOOP GAIN/PHASE vs, FREQUENCY
TA = +250 e, Vee = :!:15V

-'


~

iE

~"

"oSffi .

Q

13.9

lDK

5.00

I

I--'~

I-

lK

5.10

"!; 14.1
14

18Do

lUi

5.20

LW+

14.4

"~ 14.2

e
~

900

SUPPLY CURRENT vs. TEMPERATURE
Vee = :!:15V

=

,,1-

P~~~E

II~

_

.~

FREOUENCY CHz)

14.5

:a 14.3

DO

"'i-lI1

IIII

. MAXIMUM OUTPUT VOLTAGE vs. TEMPERATURE
RLOAD 2K, AV 1000, VIN :!:2V

=

t--)$:

-

f(.

I,",
IIII

AV' IOD

+1250C~

...

-II

.",

a:

"" I I
AV' IODO

t--

6D

D

W

~

~

~

~

rn

4.3°..fi0

-40

.20

20

4D

&0

TEMPERATURE CDC)

TEMPERATURE CDC)

3-419

80

100

120

0..

HA-5134
Performance Curves

(Continued)

OVERSHOOT vs. CLOAD
Vce = :t15V, TA = +250e, AV = 1, Vour = 200mV
40

I
I

38
36

34 r--

I- FALL1NGE~

32

~ 30
I-

g

28

~ 26
::i 24

>

"

22

I
I

-,-

.---

.,,-

I

.......

--

i.-'"'"

r--

.--

OPEN LOOP GAIN & PHASE vs. FREQUENCY

--

120
100

I'.....

.....

""""-;;,S,NG EDGE

GAIN

20

I'-

"
PHASE

20
18

1111

16
1.2

lA
1.6
LOAD CAPACITANCE (nF)

1.8

10

100

lK

WI

10K
lOOK
FREQUENCY (H,)

1M

10M

100M

Applications Information
SMALL SIGNAL TRANSIENT RESPONSE
CLOAD = 1nF

n,ANSIENT RESPONSE OF APPLICATION
CIRCUIT #1

TA = +250 e, Vee = :t15V,
Av= 1,RL= 10K
20mV/Div, 1Ils/Div.

VOUT = :t10V, RLOAD = 50V
eLOAD = O.Q1mF, AV = 3, Vee = :t15V
Top: Input, 2V/Div., 20IlS/Div. Bottom: Output, 5V/Dlv, 20Ils/Dlv.

APPLICATION CIRCUIT #1:
INSTRUMENTATION AMPLIFIER WITH POWER OUTPUT

R,

RZ

",on-100n recommended fDr
t.hartcircllitlimltlng.

son
NOTE: When driving heavy loads lhe HA-5002
may contribute to thermal errors. Proper
thermal shielding Is recommended.

3-420

HA-5134
Applications Information

(Continued)

APPLICATION CIRCUIT #2: PROGRAMMABLe GAIN AMPLIFIER
R

8R

R

4R

2R

G1

Go

0

0

-1

0

1

-2

1

0

-4

1

1

-8

AV

>-"--+VOUT

High AVOL of HA-5134 reduces gain error.
Gain Error", 0.004% @ AV = B
4R

8R

R

....I

«en
za:
ow

!;i§
a: c..
w:;;;
~«

APPLICATION CIRCUIT #3: PRECISION COMPARATOR

VIN IBOTTOM TRACEI

PULSE
GEN.

OUTPUT
(TOPTRACEI

Horizontal: 50ps/Div.
VIN = ±25mV, VOUT = ±14V
NOTE: If differenlial input voltages greater than 6Vare present. Input current
must be limited to less than 2SmA.

General Considerations
1. POWER SUPPLY DECOUPLlNG: Although not
absolutely necessary, it is recommended that all power
supply lines be decoupled with O.Ol/1F ceramic capacitors to ground. Decoupling capacitors should be located
as near to the amplifier terminals as possible.

• Error voltages generated by thermocouples formed
between dissimilar metals in the presence of temperature gradients should be minimized. Isolation of low
level circuitry from heat generating components is
recommended.

2. CONSIDERATIONS FOR PROTOTYPING: The following
list of recommendations are suggested for prototyping.

• Shielded cable input leads, guard rings and
shield drivers are recommended for the most critical
applications.

• Resolving low level signals requires minimizing
leakage currents caused by external circuitry. Use of
quality Insulating materials, thorough cleaning of
insulating surfaces and implementation of moisture
barriers when required Is suggested.

3-421

HA-5137

mHARRIS

Ultra-Low Noise Precision
Wideband Operational Amplifier

August 1991

Features

Applications

• High Speed •••••••••••••••••••••••••••••••• 20V//ls

• High Speed Signal Conditioners

• Wide Gain Bandwidth (AV ~ 5) •••••••••••••• 63MHz

• Wide Bandwidth Instrumentation Amplifiers

• Low Noise ••••••••••••••••••••••• 3nVlVHz at 1KHz

• Low Level Transducer Amplifiers

• LowVOS ••••••••••••••••••.•••••••••••••••••• 10/lV

• Fast, Low Level Voltage Comparators

• High CMRR •••••••••••••.•••••.•••••.••••••.• 126dB

• Highest Quality Audio Preamplifiers

• High Gain ••••••••••••••••••••••••••••••• 1800V/mV

• Pulse/RF Amplifiers
• For Further Design Ideas See Application Note 553

Description
The HA-5137 monolithic operational amplifier features
an unparalleled combination of precision DC and wideband high speed characteristics. Utilizing the Harris
D. I. technology and advanced processing techniques, this
unique design unites low noise (3nVl/HZ) precision
instrumentation performance with high speed (20Vl/ls)
wideband capability.
This amplifier's impressive list of features include low Vos
(1 O/lV), wide gain-bandwidth (63MHz), high open loop gain
(1800VlmV), and high CMRR (126dB). Additionally, this
flexible device operates over a wide supply range (±5V to
±20V) while consuming only 140mW of power.

Pinouts

Using the HA-5137 allows designers to minimize errors
while maximizing speed and bandwidth in applications
requiring gains greater than five.
This device is ideally suited for low level transducer signal
amplifier circuits. Other applications which can utilize
the HA-5137's qualities include instrumentation amplifiers,
pulse or RF amplifiers, audio preamplifiers, and signal
conditioning circuits.
This device can easily be used as a design enhancement
by directly replacing the 725, OP25, OPOS, OP07, OP27
and OP37 where gains are greater than five. The HA-5137
is available in TO-99 Metal Can and Ceramic 8 pin
Mini- DIPs. For the military grade product, refer to the
HA-5137/883 data sheet.

Schematic

HA2-5137 (TQ-99 METAL CAN)

TOP VIEW
BAL

~

4
V· (CASE)

.. ..

~

,.-<'~

~.n
f€
0II11.,.1IIIM

RIl

.,
.n

HA7-5137 (CERAMIC MINI-DIP)

TOP VIEW

o.

CAUTION: These devices are .ensillYe to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Hartis Corporation 1991

3-422

I.: .,

0

File Number

2908

Specifications HA-513 7
Absolute Maximum Ratings (Note 1)

Operating Temperature Ranges

TA = +250 C Unless Otherwise Stated
Voltage Between V+ and V- Terminals ••••••••••••••••••• :l:22V
Differential Input Voltage (Note 2) ........................ :l:0.7V
Internal Power Dissipation ............................ 500mW
Output Current •••••••••••••••••.••• Full Short Circuit Protection

HA-5137/37A-2 ....................... -550C::5TAS+1250C
HA-5137/37A-5 .......................... OOCSTA::5+750C
Storage Temperature Range ............. -650C S TA S +150 oC
Maximum Junction Temperature •••••••••.••••••••••••• +175 0C

Electrical Specifications V+ = 15V, V- = -15V, CL::5 50pF, RS S 1000
HA-5137A
PARAMETER

TEMP

HA-5137

MIN

TYP

MAX

-

10
30
0.2
:1:10
:1:20
7
15
:1:11.5
6
0.08
3.5
3.1
3.0
1.7
1.0
0.4

25
60
0.6
:1:40
:1:60
35
50

MIN

TYP

MAX

30
70
0.4
:1:15
:1:35
12
30
:1:11.5
4
0.09
3.8
3.3
3.2
1.7
1.0
0.4

100
300
1.8
:1:80
:1:150
75
135

UNITS

INPUT CHARACTERISTICS
Offset Voltage
Average Offset Voltage Drift
Bias Current
Offset Current
Common Mode Range
Differential Input Resistance (Note 3)
Input Noise Voltage 0.1 Hz to 10Hz (Note 4)
Input Noise Voltage Density (Note 5) fO = 10Hz
fO = 30Hz
fO=1000Hz
Input Noise Current Density (Note 5) fO = 10Hz
fO=30Hz
fo= 1000Hz

+25 0C
Full
Full
+250C
Full
+250C
Full
Full
+25 0C
+250 C
+250C

+250C

-

:1:10.3
1.5

-

-

0.18
5.5
4.5
3.8
4.0
2.3
0.6

-

:1:10.3
0.8

-

-

-

~V
~V
~V/OC

nA
nA
nA
nA
V
MO

:z a:
OW

~<

0.6

nV/.jHz
nV/y'Hz
nV/v'Hz
pNVHz
nV/v'Hz
nV/y'Hz

V/mV
V/mV
dB
VN
MHz
MHz

V
V
KHz
0
mA

-

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 6)
Common Mode Rejection Ratio {Note 7)
Minimum Stable Gain
Gain-Bandwidth-Product
fO= 10KHz
fO=1MHz

+250 C
Full
Full
+250 C
+250 C
+250 C

1000
600
114
5
60

1800
1200
126
80
63

-

+250C
Full
+250C
+250C
+250C

:1:10.0
:1:11.7
220

:1:11.5
:1:13.8
320
70
25

-

-

100

-

-

700
300
100
5
60

1500
800
120

80
63

--

:1:10.0
:1:11.4
220
16.5

:1:11.5
:1:13.5
320
70
25

-

-

-

100

20
1.0
20

-

-

OUTPUT CHARACTERISTICS
Output Voltage Swing

RL=6000
RL=2KO

Full Power Bandwidth (Note 8)
Output Resistance, Open Loop
Output Current

-

16.5

-

TRANSIENT RESPONSE (Note 9)
RiseTime
Slew Rate (Note 11)
SeHling Time (Note 10)
Overshoot

+25 0C
+25 0C
+250 C
+250 C

14

-

20
1.0
20

-

3.5

-

40

14

-

ns
V/~s
~s

40

%

-

mA
mA

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Nole 12)

+250 C
Full
Full

-

3-423

-

2

-

4.0
4

-

3.5

-

16

....

-.....

OUT

50pF

LARGE SIGNAL RESPONSE

SMALL SIGNAL RESPONSE

Vertical Scale: (Volts: Input = tV/Div.)
(Volts: Output = 5V/Div.)
Horizontal Scale; (Time =- 1/ls/Div.)

Vertical Scale: (Volts: Input = 20mV/Div.)
(Volts: Oulput = 100mv/Div.)
Horizontal Scale: (Time = 100ns/Div.)

3-426

HA-5137
Typical Performance Curves

(Continued) Unless Otherwise Specified: TA = +25 0 C, VSUPPLY = ±15V
SETTLING TIME TEST CIRCUIT

1000.0.

IN o-~-...NV--p-I~

• AV =-5
• Feedback and summing resistors
should be 0.1 % matched.

2k.n.

• Clipping diodes are optional.
HP50B2-2810 recommended.

SUGGESTED STABILITY CIRCUITS

-'
«en
za:

Ow

Cs

~~
c..

r······ll·······j

a:

I

~«

I

w::;;;

•

I

Low resistances are preferred for low noise applications as a 1 Kn resistor has 4nVlY'Hz of thermal noise. Tolal
resistances of greater than 10KO on eithor input can reduce stability. In most high resistance applications. a few
picofarads of capacitance across the feedback resistor will improve stability.

O.lHz TO 10Hz NOISE WITH ACL

= 25,OOOVN

Die Characteristics
Transistor Count ................................... 63
Die Dimensions .................... 65 x 104.3 x 19 mils
(1700~m x 2600~m x 480flm)
Substrate Potential' " .............................. VProcess .................................... Bipolar-DI
Thermal Constants (OC/W)
8ja
8jc
HA7-5137 Ceramic Mini-DIP
160
79
HA2-5137 TO-99 Metal Can
172
48
*The substrate may be left floating (Insulating Die Mount)
mounted on a conductor at V- potential.

Horizontal Scale = 1 sec/Diy.
Vertical Scale = O.002~V/Div.
O.08~Vp-p

3-427

Of

it may be

m

HA-5142/44

HARRIS

Dual/Quad Ultra-Low Power
Operational Amplifiers

August 1991

Features

Applications

• Low Supply Current ••••••••••••••••••••• 45JJA/Amp

• Portable Instruments

• Wide Supply Voltage Range •••••••• Single 3V to 30V
or Dual :!:1.5V to :!:15V

• Meter Amplifiers
• Telephone Headsets

• High Slew Rate ••••••••••••••••••••••••••••• 1.5V1I1S

• Microphone Amplifiers

• High Gain ••••••••••••••••••••••••••••••••• 100kVN
• Unity Gain Stable

• Instrumentation
• For Further Design Ideas See Application Note 544

• Available in Duals and Quads

Description
The HA-5142/44 ultra-low power operational amplifiers
provide AC and DC performance characteristics similar
to or better than most general purpose amplifiers while
only drawing 1/30 of the supply current of most general
purpose amplifiers. In applications which require low power
dissipation and good A.C. electrical characteristics, this
family offers the industry's best speed/power ratio.

a 400kHz bandwidth make the HA-5142/44 Ideal for use in
low power instrumentation, audio amplifier and active filter
designs. The wide range of supply voltages (3V to 30V) also
allow these amplifiers to be very useful In low voltage
battery powered equipment. These parts are also tested
and guaranteed at both :!:15V and single ended +5V
supplies.

The HA-5142/44 provides accurate signal processing by
virtue of their low input offset voltage (2mV), low input bias
current (45nA), high open loop gain (100kVN) and low
noise, for low power operational amplifiers (20nV/y'HZ).
These characteristics coupled with a 1.5V/IIS slew rate and

These amplifiers are available In duals (HA-5142, Sale,
Can or Mini-DIP) or quads (HA-5144, SOIC or DIP) with
industry standard pinouts which allow the HA-5142/5144's
to be interchangeable with most other operational amplifi·
ers. For military grade product refer to the 5142, 5144/883
data sheet.

Pinouts

TOP VIEWS

HA3-5t42 (PLASTIC MINI-DIP)
HA7-5t42 (CERAMIC DIP)

HA2-5t42 (TO-99 METAL CAN)

HAt-5t44 (CERAMIC DIP)
HA3-5t44 (PLASTIC DIP)

V+
OUT1

OUT 4

OUTt

V+

-INt

OUT2

·INt

·1N4

+IN1

-IN2

+INt

+1N4

V-

+IN2

v-

v+
+IN2

+1N3

-IN2

-1N3

OUT 2

CAUTION: Those devices are sensitive to electrostatic discharge. Proper IC handling procedure. should be followed.
Copyright @ Harris Corporation 1991

3-428

OUT 3

File Number

2909

Specifications HA-5142/44
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- Terminals ••••••••••••••••••.•. 35V
DifferentlallnputVoltage ••..•••••••••.•••••..•.••••.••• '" ±7V
Output Current ••.••.••••.••.•••••••.•.••...•.•• SIC Protected
Intemal Power Dissipation. • • . • • . • • . • . • • • . . . . • . . • • . . •• 500mW

HA-5142/44-5 ••.•••..••.••••••••.••.•..•• OOC ~TA~ +75 0 C
HA-5142/44-2 •••••••..••••.•.•••.••••. -550 C ~TA~ +125 0 C
HA-5142/44-9 ••••.•••.••••.•••••.••••.• -400C ~ TA ~ +85 0 C
Storage Temperature Range ••••.•••••.•. -650C ~ TA:S +150 0 C
Maximum Junction Temperature •.•••••••.••.••..•••••• +175 0 C

Electrical Specifications RS = 1000, CL:S 1OpF Unless Otherwise Specified.
-2,-5
V+ = +5V, V- =OV
PARAMETER

-2,-5
V+ = +15V, V-= -15V

TEMP

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

+250 C
Full
Full
+250 C
Full
+25 0 C
Full
Full
+250 C
+25 0 C
+25 0 C

-

-

2

6
8

-

-

2

6
8

mV
mV
!lVloC
nA
nA
nA
nA
V
MO
nV/y'Hz
pNy'Hz

INPUT CHARACTERISTICS
Offset Voltage (Note 11)
Average Offset Voltage Drift
Bias Current (Note 11)
Offset Current (Note 11)
Common Mode Range
Differential Input Resistance
Input Noise Voltage (I = 1kHz)
Input Noise Current (I = 1kHz)

Ot03
-

-

3
45

100
125
10
20

0.3

-

0.6
20
0.25

-

-

3
45

0.3

-

100
125
10
20

-

±10

-

-

-

-

0.6
20
0.25

-

20k
15k

100k

-

77

±10
±10

-

-

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 2, 4)
Common Mode Rejection Ratio (Note 7)
Bandwidth (Notes 2, 3)

+250 C
Full
Full
+250 C

20k
15k

100k

77

105
0.4

-

+25 0 C
Full
+25 0 C

1.0 to 3.8
1.2t03.5

0.7 to 4.2
0.9 to 4.0
240

-

-

0.8

-

600
1.5
10

-

45

-

80
100

-

100

-

150
200

77

105

77

105

-

-

-

105
0.4

-

-

VN
VN
dB
MHz

-

±13
±13
24

-

V
V
kHz

-

600
1.5
10

-

VIliS
liS

-

-

OUTPUT CHARACTERISTICS
Output Voltage Swing (Notes 2, 10)
Full Power Bandwidth (Notes 2,4,8)

-

TRANSIENT RESPONSE (Notes 2, 3)
+250 C
+250 C
+25 0C

Rise Time
Slew Rate (Note 6)
Settling Time (Note 5)

0.8

ns

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 9)

+250 C
Full
Full

-

-

IINAmp
pNAmp
dB

NOTES:

1. Absolute maximum ralings are limiting values, applied individually beyond
which the selViceability of the circuit may be impaired. Functional
operability under any of thase conditions Is not necessarily implied.

2. RL

9. INS
10. For

= 50kO

11. Vo

= 1.4 to 2.5V for Vee = +5. OV; Vo = ±10V lor Vee = ±15V.

5. Settling Time is specified to 0.1 % of final value for a 3V output step and
AV = -1 lor Vee = +5V. OV. Oulpul slep = 10V lor Vee = ±15V.
6. Maximum input slew rate

= 10V/p.s.

7. VeM = 0 103V lor Vee = +5.0V; VeM

= ±10V lor Vee =

co

+5, OV terminate RL at +2.SV. Typical output current is

:l:3mA.

3. eL = 50pF
4. Vo

= +10V lor Vee = +5, OV; l!.VS = ±5V lor Vee = ±15V.

Vee

±15V

8. Full Power Bandwidth Is guaranteed by equation:
Full Power Bandwidth = Slew Rate
2nV Peak

3-429

= 1.4V lor Vee = +5V, OV.

Specifications HA-5142/44
Electrical Specifications

RS = 1000, CL ~ 10pF Unless Otherwise Specified.
-9
V+=+5V, V-=OV

PARAMETER

TEMP

-9
V+ =+15V, V-=-15V

MIN

TYP

MAX

--

-

2

6
8

MIN

TYP

MAX

UNITS

2

6
8

mV
mV
IIV10C
nA
nA
nA
nA
V
MO
nV/y'HZ
pNy'HZ

INPUT CHARACTERISTICS
Offset Voltage (Note 11)
Average Offset Voltage Drift
Bias Current (Note 11)
Offset Current (Note 11)
Common Mode Range
Differential Input Resistance
Input Noise Voltage (f = 1 kHz)
Input Noise Current (f = 1 kHz)

+250 C
Full
Full
+250 C
Full
+250 C
Full
Full
+250 C
+250 C
+250 C

-

3
45

-

-

0.3

-

Ot03

-

0.6
20
0.25

--:1:10
-

-

100
125
10
20

--

3
45

-

0.3

-

0.6
20
0.25

-

100
125
10
20

--

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 2, 4)
Common Mode Rejection Ratio (Note 7)
Bandwidth (Notes 2, 3)

+250 C
Full
Full
+250 C

20k
12k
70

lOOk

+25 0 C
Full
+250 C

1.0t03.8
1.2 to 3.5

0.7104.2
0.910 4.0
240

-

105
0.4

-

-

--

20k
12k
70

lOOk

:1:10
:1:10

:1:13
:1:13
24

-

-

105
0.4

-

-

VN
VN
dB
MHz

OUTPUT CHARACTERISTICS
Output Voltage Swing (Notes 2, 10)
Full Power Bandwidth (Notes 2, 4, 8)

-

-

-

-

-

-

V
V
kHz

TRANSIENT RESPONSE (Notes 2, 3)
+250 C
+250 C
+250 C

Rise Time
Slew Rate (Note 6)
Settling Time (Note 5)

-

0.8

600
1.5
10

--

0.8

80
100

-

-

-

600
1.5
10

-

ns

VIliS
liS

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply Rejection Ratio (Note 9)

+250 C
Full
Full

-

45

-

70

105

-

70

100

-

105

150
200

-

NOTE: The notes from the -2. -5 table apply to this -9 table. Absolute maximum ratings and the operating temperature range. also apply.

sOle Pinouts

TOP VIEWS
HA9P5144 (SOle)

HA9P5142 (SOle)

OUT
-INl
+INl

v+
+1N2
-1N2
OUT2
NC

3-430

/lNAmp
/lNAmp
dB

HA-5142/44

Test Circuits
SLEW RATE AND TRANSIENT RESPONSE TEST CIRCUIT

IN[=C>

o

OUT

~ J~t,""F

LARGE SIGNAL RESPONSE
Vertical Scale: (Volts: Input 5V/Div.; Output
Horizontal Scale: (TIme: 2)ls/Div.)

=

= 2V/Div.)

SMALL SIGNAL RESPONSE
Vertical Scale: (Volls: Input 100mV/Div.; Output
Horizontal Scale: (TIme: 2)ls/Div.)

=

= 50mV/Div.)

INPUT

-'
«en
zec

INPUT

Ow
t=i:L

«::;

ecc..
w::;;;

&«
OUTPUT

OUTPUT

+VSUPPLY = +15V, -VSUPPLY = -15V

LARGE SIGNAL RESPONSE
Vertical Scale: (Volts: Input = 2V/Div.; Output = lV/Div.)
Horizontal Scale: (TIme: 5)ls/Div.)

+VSUPPLY

SMALL SIGNAL RESPONSE
Vertical Scale: (Volts: Input = 100mV/Div.; Output = 50mV/Div.)
Horizontal Scale: (Time: 5)ls/Div.)

INPUT

INPUT

OUTPUT

OUTPUT

+VSUPPLY

= +15V, -VSUPPLY = -15V

= +5V, -VSUPPLY = OV

+VSUPPLY = +5V, -VSUPPLY = OV

3-431

HA-5142/44
Performance ClIrves

Vs

= :l:2.5V. TA = +250 C Unless Otherwise Specified
INPUT OFFSET CURRENT AND BIAS CURRENT VB.
TEMPERATURE

OPEN LOOP FREQUENCY RESPONSE
110

I

lDO
m so

~
~

70
6D

~o

50

~

0

CL" SOpF

60
00

.
•

50
0

4

00

0 00
1000

30

12 I

i

1

0

1

120D

-1 0

.-t-r

0
~

~

~

0

2D

100

1K
10K
lOOK
FREQUENCY (Hz)

.J..

1.6

•.1.I,Jk6

I

RL .. SOkS'l
CL -=SOpf

~

I

I--::: f-"'"'

~

. . . 1'--. "-

~400

O.2~
~

-......

f

2OOr---r-~-t-t-rt+++---+-t--r-r-t--t+-HO., §
OA

O~~O---L-~-L-L-L~~,~DO.--~--L-L-LJ-L~,~OOO

14

v,LLLU

0

I

0

...

~

~~

4

V'~PPL ~ -~3~

2

v'rTi i'!

lK

:l~ 0.9

10K

c

'\

~
~
SUPPLY-VOLTAGE (VOLTS)

~

~

BANDWIDTH

SLEW RATE

fo--

r-

,

~-r-r--r--r--t--r--t--r--t--~

~ O.7l--t--t--~--r-t--t--t---I--r-H

O~oo~-~io-_~~.-_~IO.-'O~~ro~~~f,,-!..O.-~OO.-..
IOO~·,2D~

~~

TEMPERATURE joe)

i"'
lOOK

. -. . .

IO~r--+-+--1--r--+--+--+--1---r--~

'\ ~

2

0

1.1
0

~

VSUPPL V .. +5V

"

1.2 ~~: ::~ 1--l--+-"f---r-t--l---t----jH

3o ,.

.~

~g •

BANDWIDTH

NORMALIZED AC PARAMETERS vs. TEMPERATURE

VSj"l"m

RL"5bkn
2

1/
1/
~

LOAD CAPACITANCE (pF)

OUTPUT VOLTAGE SWING VS.
FREQUENCY AND SINGLE SUPPLY VOLTAGE

I---

I.~~

S 6~r---r-~-t-t-rt+++'~~~~--t~
~~kd-rrHO~~

~W

m m

80

(ae)

NORMALIZED AC PARAMETERS va. SUPPLY VOLTAGE

o..r-=M~N~DWf'~DT=H~-t-t-r+++*-=~-i--t-r-ri-rrH°A~
PHASE MARGIN
--....~
...
z
r-~~~~~+-+-~JJ1~
~~

>

80

1M

10Qo,.---,.---,-,---,,---,rrTT-,----,--,---,.........-rrn

"z

~

TEMPERATURE

1000

10

BANDWIDTH AND PHASE MARGIN vs. LOAD CAPACITANCE

i51

~

INPUT OFFSET CURRENT

2D

......

z 2D
~
o 10

..

1o

200

40

9

INPUT BIAS CURRENT
20

PHA~

80

W

'R~=60kn

1M

fREQUENCY (Hz)

3-432

HA-5142/44
Performance Curves

(Continued) Vs

= ±2.5V, TA = +250 C Unless Otherwise Specified
MAXIMUM OUTPUT VOLTAGE SWING vs.
LOAD RESISTANCE AND SINGLE SUPPLY VOLTAGE

INPUT NOISE vs. FREQUENCY

VSUPPl V .. +20V

6
4

.......

'000 ,
2

I

o

~

LT••

10

'00

~

8

g

6

VSUPPLY" +10V

/

w

,.-

1

~

I

VSUP~L V ! +5V

~

,,
fREQUENC

'DI

VH'J

i!o

10

5

lOOK

1

4
VSUPPL

v! +3V

I

,#
,K
10K
LOAD RESISTANCE (OHMS)

'00

POWER SUPPLY CURRENT vs.
TEMPERATURE AND SINGLE SUPPLY VOLTAGE

PSRR AND CMRR vs. FREQUENCY
140

0

,,, t-....

0
0-""""""""

t-...

100

1-

0

.......

t-...

0

0

ifr~

j"-....
0

1

0

+PSAR,CMRR

j"-....

0

.......

40

.......
20

-60

'00

lK

20

20

,M

CHANNEL SEPARATION vs. FREQUENCY
·'40

-120

-.of--

-I--

'"

-60 I---

. ot---

~
-

-=-

lKn·

100Kfl

of--

0
'00

I

VOl

c.s... 20 LOG (V02

~
lK!2
•

-2

-t--.

lDOKS'l

)

100 V.,
V02

'Kn

~I ""'"

lK

' ' ' 'f

FREQUENCY

3-433

10K
Hz I

,.-

V

40

60

TEMPERATURE

lOOK

10K
FREQUENCY (H~)

vs ... +3'1

-- rfV -

-40

'OOK

toe)

--'

«en

ZO:
oW
~§
0:0.

w::;;;
~«

"S .. +5\1

,.- f.-

.......

0

10

.......

0

--/ -

v~.+"\v

,OOK

80

100

120

140

HA-5142/44

Schematic
r-~--~----------~----r-~~~----~--~--~--r-----~-o+V

+---+IW'-O OUTPUT
+V

~4---~--------~~

____________-+__

Die Characteristics
Transistor Count
HA-S142 ....•.................•....•..••...•..•. 66
HA-S144 ....................................... 132
Substrate Potential* .....•..•.......•....•..•....... vProcess .................•..........••...... Bipolar-DI
9ja
9jc
Thermal Constants (OC/W)
HA1-S144(-2,-S,-7)
101
33
HA1-S144(1883)
7S
22
206
S6
HA2-S144 (-2, -S, -7)
HA2-S142(-2,-S,-7)
184
SO
HA2-S142 (1883)
143
43
HA3-S142 (-S)
80
20
HA3-S144 (-S)
7S
20
HA7-S142(-2,-S,-7)
177
92
HA7-S142 (1883)
80
20
HA9PS142 (-S, -9)
94
26
HA9PS144 (-S, -9)
90
26
*The substrate may be left floating (Insulating Die Mount) or it may be
mounted on a conductor at V- potential.

NOTE: Consult Harris for LCC/PLCC information.

3-434

~~

____~-o_V

m

HARRIS
Ultra-Low Noise Precision High Slew Rate
Wideband Operational Amplifier

August 1991

Features

Applications

• High Speed •••.•••••••.••••••.••.•••••.•••• 35V/IIS

• High Speed Signal Conditioners

• Wide Gain Bandwidth (AV ~ 10) .••.•••••.••• 120MHz

• Wide Bandwidth Instrumentation Amplifiers

• Low Noise ••••••••••••..•••••••• 3nVly'HZat 1 KHz

• Low Level Transducer Amplifiers

• LowVOS •••.•.••••••••.••••••••..••••••.•••• lOIlV

• Fast, Low Level Voltage Comparators

• High CMRR •.••••.•••••.•••••••••.•••••.••.• 126dB. • Highest Quality Audio Preamplifiers
• High Gain ••••.•••••••• , •••••••••• " ••••. 1800VlmV

• Pulse/RF Amplifiers

Description
This device is ideally suited for low level transducer signal
amplifier circuits. Other applications which can utilize the
HA-5147's qualities include instrumentation amplifiers,
pulse or RF amplifiers, audio preamplifiers, and signal
conditioning circuits. Further application ideas are given in
Application Note 553.

The HA-5147 monolithic operational amplifier features an
unparalleled combination of precision DC and wideband
high speed characteristics. Utilizing the Harris D. I.
technology and advanced processing techniques, this
unique design unites low noise (3nV/y'HZ) precision
instrumentation performance with high speed (35V/IIS)
wideband capability.

This device can easily be used as a design enhancement by
directly replacing-the 725, OP25, OP~S, OP07, OP27 and
OP37 where gains are greater than ten. The HA-5147 is
available in TO-99 Metal Can and Ceramic 8 pin
Mini-DIPs. For military grade product, refer to the
HA-5147/883 data sheet.

This amplifier's impressive list of features include low Vos
(10IlV), wide gain-bandwidth {120M Hz), high open loop
gain (1800V/mV), and high CMRR (12SdB). Additionally,
this flexible device operates over a wide supply range (±5V
to ±20V) while consuming only 140mW of power.
Using the HA-5147 allows designers to minimize errors
while maximizing speed and bandwidth in applications
requiring gains greater than ten.

Pinouts

Schematic

TOP VIEWS
HA7-5147
(CERAMIC MINI-DIP)

BALg" BAL
...., 2

+IN

3

v-

4

7

-

6

OUT
NO

Pi
li-1

,

V+

5

)1'__

[.

.n

'"
''''

l1,n

...

L. ..

~

.
~~~
I
_

I1MI4

,

~I

O"~

...

HA2-5147
(TO-99 METAL CAN)

BAL

~
M

m

l..

)

~QW

~r~

~
QDSt

"

11.24

~o.GlltR'

QUI

.

Rl

11...

~"

UT1'UT

.,
CliO

11I· C2

n

R21 '

11'36

rfl""

' 'r
··1

!.

".. J,

~lIl1a

."

0

CAUTION: These devices are sensilive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

3-435

1:

::!!

Q1II1Ii

,...

~'m

o.an

1....;---1: ""

all

'"'u,:"

,

111m

A.'.

All

(III'.

\"

.dl.

1

j'

I

~SU~AJE

~"

am:2:

s:mij
S:Qau

.

If

J;"

~:

15

"~
l

~QO'

CI

QIU

''''

v· (CASE)

""

.

""
"

.... I
.,

" . -1

---rp

''''

CJ

JI1"5

...

IA~A"tl

!!J

File Number

2910

-'

-I--

IdS)

. . . . r-- GAIN

~WI~I,I,v
fA

V+

III

11111111

40

SUGGESTED OFFSET VOLTAGE ADJUSTMENT

~+250C

RL"ZK

"-

CL=5DpF

10

,

( DEGREESI

PHASE

9

18D

,.

10.

lOOK

10M

1M

FREQUENCY (Hz)

100M

Tested Offset Adjustment Range is I Vas +1 mV Iminimum referred to output.
Typical range Is ±4mV with RT = 10kO.
....1

«en
;za:
OW

~~

a: c..

LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT

w::;;;

&«
IN

>-.....----cp--o OUT

SMALL SIGNAL RESPONSE

LARGE SIGNAL RESPONSE

IN
IN

OUT

OUT

=

Vertical Scale: (Volts: Input = 10mV/Div)
(Volts: Oulput 100mV/Div)
Horizontal Scale: (Time: 100ns/Dlv)

Vertical Scale: (Volts: Input O.5V/Dlv.)
(Volts: Oulput = 5V/Div.)
Horizontal Scale: (lime: 500ns/Div)

=

3-439

HA-5147
Typical Performance Curves

(Continued) Unless Otherwise Specified: TA = +250 C, VSUPPLY = ±15V
SETT1.ING TIME TEST CIRCUIT

• AV=-10
• Feedback and summing resistors should be 0.1 %
• Clipping diodes are optional. HP5082-2810 recommended
SUGGESTED STABILITY CIRCUITS

Low resistances are preferred for low noise applications as a 1kO resistor has 4nV/VHz of thermal noise. Total
resistances of greater than 10kO on either input can reduce stability, In most high resistance applications. a few
picofarads of capacitance across the feedback resistor will improve stability.

O.1Hz TO 10Hz NOISE WITH ACL = 25,OOOVN

Die Characteristics
Transistor Count •••••.•••••••..••....•.....•.....•• 63
OieOimensions ••••.•.•••••.••••••• 65x 104.3 x 19 mils
Substrate Potenlial* .•••.••.••...•••.•.••••.•.•..... vProcess .••••.•.•••...•••••.••.•.••••.•••.•. Bipolar-Ol
Thermal Constants (OC/W)
Gja
Sjc
HA7-5147 Ceramic Mini-DIP
160
79
HA2-5147 TO-99 Metal Can
172
48
*The substrate may be left rlealing (Insulating Die Mount) or it may be
mounted on a conductor at V- potential.

Horizontal Scale = 1sec/Diy.
Vertical Scale = 0.OO2~V/Div.
0.08IlVp-p

3-440

;m HARRIS

HA-5160/62
Wideband, JFET Input High Slew Rate,
Uncompensated, Operational Amplifier

August 1991

Features
•
•
•
•
•
•

Applications

Wide Gain Bandwidth (AV ~ 10) •••••••••••• 100MHz
High Slew Rate •••••••••••••••••••••••••••• 120VIlls
Settling Time •••••••••••••••••••••••••••••••• 280ns
Power Bandwidth •••••••••••••••••••••••••• 1.9MHz
Offset Voltage ••••••••••••••••••••••••••••••• 1.0mV
Bias Current ••••••••••••••••••••••••••••••••• 20pA

•
•
•
•

Video and RF Amplifiers
Data Acquisition
Pulse Amplifiers
Precision Signal Generation

Description
The HA-s160 is a wideband, uncompensated, operational
amplifier with FET/Bipolar technologies and Dielectric
Isolation. This monolithic amplifier features superior high
frequency capabilities further enhanced by precision laser
trimming of the input stage to provide excellent input
characteristics. This device has excellent phase margin at a
closed loop gain of 10 without external compensation.
The HA-S160/S162 offers a number of important
advantages over similiar FET input op amps from other
manufacturers. In addition to superior bandwidth and
settling characteristics, the Harris devices have nearly
constant slew rate, bandwidth, and settling characteristics
over the operating temperature range. This provides the
user predictable performance in applications where settling
time, full power bandwidth, closed loop bandwidth, or
phase shift is critical. Note also that Harris specifies all
parameters at ambient (rather than junction) temperature to

Pinout

provide the designer meaningful data to predict actual
operating performance.
Complementing the HA-s160/S162's predictable and
excellent dynamic characteristics are very low input offset
voltage, very low input bias current, and a very high input
impedance. This ideal combination of features make these
amplifiers most suitable for precision, high speed, data
acquisition system designs and for a wide variety of signal
conditioning applications. The HA-S160 provides excellent
performance for applications which require bolh precision
and high speed performance. The HA-S162 meets or
exceeds the performance specifications of National's
hybrid op amp, the LH0062.
The HA2-s160-2 denotes a temperature range of -ssoC
to +12S0C and the HA2-s160/62-S denotes a OoC to
+7SoC range. Military version (/883) data sheets are
available upon request.

Schematic
HA2-5160/5162
(TO-99 METAL CAN)
TOP VIEW
COMPENSATION

Case Connected to V-

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-441

File Number

2911

....I

«en
za:

OW

~§
a: c..

~:i
o

Specifications HA-5160/5162
Absolute Maximum Ratings

Operating Temperature Ranges:

Voltage Between V+ and V- .••••••••••••••••••••••.••••••• 40V
DifferentiallnputVoltage ..•••••••••.•••••••••••••••••••• :l:40V
Peak Output Current ••••.••••••.••••. Full Shori Circuit Protection
Internal Power Dissipation (Note 2) ••••••••••.•••••••••• 675mW

HA-5160-2 .••••.•••••••••..•••.••••••• -550 C ::;TA:S +1250 C
HA-S160-S ••••••••••••••••••••••••••••••• COC :STA:S +750 C
HA-S162-S ••.••••.••.••••••.••••.•••••••• COC:S TA:S +75 0 C
Storage Temperature Range .•••••••••••• -650 C TA :S +lS00 C
Maximum Junction Temperature (Note 2) .•••.•••••••..• +1750 C

Electrical Specifications V+

:s

= +15V, V- = -15V, UnJess Otherwise Specified.
HA-S160-2
-ssoC 10 12So C

PARAMETER

HA-S162-S
00Clo+7SoC

HA-S160-S
OOC1o +7So C

TYP

MAX·

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

-

1
3

3
5

-

1
3

3
S

-

3
S

15
20

mV
mV

Full

-

10

-

20

-

-

20

35

VVJOC

+250 C
Full

-

20
5

50
10

20
5

50
10

20
5

65
10

pA
nA

2
2

10
5

-

2
2

10
5

-

2
2

10
5

pA
nA

5

5

TEMP

MIN

INPUT CHARACTERISTICS
Offset Voltage

Offset Voltage Average Drift
Bias Current

Offset Current

+250 C
Full

+250 C
Full

-

-

Input Capacitance

+250 C

Input Resistance

+250 C

-

Full

:1:10

+25 0 C
Full

-

-

-

-

-

-

-

1012

-

pF

1012

:1:11

-

:1:10

:1:11

-

:1:10

:1:11

-

V

75K
60K

150K
lOOK

-

75K
60K

150K
100K

-

25K
25K

lOOK
75K

-

VN
VN

Full

74

60

-

74

80

-

70

80

-

dB

+250 C

10

-

-

-

-

VN

100

-

100

-

10

-

-

10

Full

-

100

-

MHz

Output Voltage Swing
(Note 5)

+250 C
Full

:1:10
:1:10

:1:11
:1:11

,-

-

:1:10
:1:10

:1:11
:1:11

:1:10
:1:10

:1:11
:1:11

Output Current (Note 6)

+250 C

:1:10

:1:20

:1:10

:1:20

-

:1:10

:1:20

-

-

:1:35

-

-

1.6

1.9
50

Common Mode Range

5
1012

n

TRANSFER CHARACTERISTICS
targe Signal Voltage Gain (Note 3)

.Common Mode ReJection Ratio
(Note 4)
Minimum Stable Gain
Gain Bandwidth Product
(AV> 10)
OUTPUT CHARACTERISTICS

Output Shori Circuit Current

+25 0 C

-

:1:35

Full Power Bandwidth (Note 3, 7)

+250 C

1.6

1.9

-

Output Resistance (Note 8)

+250 C

-

50

-

-

-

20

100

120

-

-

-

:1:35

0.8

1.1

-

.50

-

-

V
V
mA
rnA
MHz

n

TRANSIENT RESPONSE (Note 9)
Rise TIme

+25 0 C

-

20

Slew Rate

+250 C

100

120

Seflling Time (Note 10)

+250 C,

-

280

-

Full

-

8

10

+250 C

74

86

-

-

20

50

70

280

-

-

-

8

10

74

86

-

Viva

400

-

-

8

12

rnA

70

86

-

dB

na

ns

POWER SUPPLY CHARACTERISTICS
Supply Current
Power Supply ReJectlon'Ratio
(Note 11)

3-442

HA-5160/5162
NOTES:
1. Absolute maximum ratings are limiting values, applied individually.

7. Full Power Bandwidth guaranteed, based on slew rate

beyond which the serviceability of the circuit may be Impaired.
Funclional operability
necessarily implied.

under

any of these

at 6.BmW/oC for operation
above +75 0C.

2. Cerate

3. VOUT

~

4. VCM

~

5. RL

2K

~

6. VOUT

±10V. RL

~

conditions

at ambient

is

measurement using FPWB = Slew Rate
2nVpeak

not

a. Output resistance measured under open loop conditions.

temperatures

9. Refer to Test circuits section of the data sheet, where

AV

2K

±10V DC

~

~

+10.

' O. Setlllng Time Is measured to 0.2% of final value for a 1 0 volt
output step and AV = 10.

11. VSUPPLY

~

±10V DC to ±20V DC

±10V

Test Circuits
LARGE AND SMALL SIGNAL RESPONSE CIRCUIT
IN

~f

5PF

1

-r~'
1.BkA

LARGE SIGNAL RESPONSE
Vertical Scale: A = O.5V/Div., B = 5V/Div.
Horizontal Scale: Time = 500ns/Div.

SMALL SIGNAL RESPONSE
Vertical Scale: A = 10mV/Div., B = 100mV/Div.
Horizontal Scale: Time = 100ns/Div.

J

INPUT A

J

,

I\.

A

I

OUTPUTB

OUT

I

OV

i\

OUTPUTB

I

"

OV

OV
INPUT A

OV

SETTLING TIME CIRCUIT

*~

~

J~
SOO.o.

5k.o.

+15V

~~N4416
2k.o.

+ 15V

VIN

y~

~~
200A

TO
OSCILLOSCOPE

lr1

)
-uVOUT

;:r' 50pF

-15VC
2k.n.

3k.n.
• AV=-10

~

• Feedback and summing resistors

should be 0.1% matched.

*

Clipping Diodes are optional.

HP5082-2B10 recommended.

3-443

HA-5760/5762
Typical Performance Curves
INPUT OFFSET VOLTAGE AND
BIAS CURRENTvs. TEMPERATURE

OPEN LOOP FREQUENCY RESPONSE
+2.50

!

iii

+2.0

4K

I

I

+1.5

I

OFFSET VOLTAGE

3K

~

+1.0

w

fl).50 ~

!... 2K

+0.0

i!ia:

-

BIAS CURRENT

lK

1.0

iD

70

VSUPPL Y •

±20V

30

~

tsi!i

40

'\

I
0

5
0

5

lK

VLPPLY. ± 10V

..I

VSUPPLY • ± 7V

I

I

10K

----

lOOK
FREOUENCY (Hz)

DO

"

GAIN

I'..
L ~

PliASE

I

-10
10

45<>

~
~

I
I
I

10

100

10K

lK

135 0

~

I,.,.

\,

lOOK

1M

10M

100M

FREQUENCY IHzl

-

OPEN LOOP FREQUENCY RESPONSE
FOR VARIOUS BANDWIDTH CONTROL
CAPACITANCES

~
Z

;;:

"
">!...

1\
1\\
\

1M

...........

30
0

110
100

VSUPPLy=±15V

" r-..

2.0
+160

+120

-

"

:
g

OUTPUT VOLTAGE SWING vs. FREQUENCY
35

r-.....
.......

~

§

-1.50

VI
+110
+40
TEMPERATURE (OC)

-40

-80

~

w

~
~

-0.50

a:

all!

110

100

;S90
Z 80

w

g

40

30

9

20

~

3-444

I

"-

OpF

"- "'-" V
I"~

"

10
-10
10

10M

~ f""-..-.
r--....~

60

:!;
Z

~

90

80
70
60

100

,.

~
~L

60pF

L

l00pF -

.,,,- ""'-x
~

300pF

" .,'",

10K
lOOK
FREQUENCY (Hz)

X

=

\.

::-...., I\,
\.
\.

1M

10M

100M

HA-5160/5162
Typical Performance Curves

(Continued)

INPUT NOISE VOLTAGE AND
NOISE CURRENT VS. FREOUENCY
160
w

140

~

~

120

g~100
~r; 80

~:>s
~

60

i'..

40
20

.,

I

"\."\.
"\."\.

10

0.8

I

ffi

0.7
0.6 II:

_/ SOURCE RESISTANCE = l00KSl

"\.""-

I

""- K...........

...........

NORMALIZED AC PARAMETERS
VB. TEMPERATURE

a:
./DURCE RESISTANCE - on 0.5 :JWUI~
t:;
iNPUT NOISE CURRENT 0.4

I

100

lK

B~NDWfoTJ

........

0.7

fa~

o

0,6

~e

100K

10K

FREQUENCY (Hz)

,

~SLEWRATE

O.B

..'~3"

~

0.1

$
a:

ffi~
~~

0.2 ~

I

1.1
1.0

ClJO 0.9 -

~~

0.3

~
a:

~

~

BANDWIDTH

~
r--

0.5

!!1

0.4
-80

OUTPUT VOLTAGE SWING
VS. LOAD RESISTANCE

+40
+80
TEMPERATURE (DC)

-40

+120

+160

--'
 1OpF) between the output and the inverting input of

the device This small capacitor compensated for the
input capacitance of the FET.
3. CAPACITIVE LOADS: When driving large capacitive
loads (> 1OOpF), it is suggested that a small resistor
(::::100n) be connected in series with the output of the
device and inside the feedback loop.
4. POWER SUPPLY MiNIMUM: The absolute supply
minimum is ±6V and the safe levei is ±7V.

Applications
Suggested Compensation For Unity Gain Stability·
INVERTING UNITY GAIN CIRCUIT

INVERTING UNITY GAIN PULSE RESPONSE

2k.n.

INn.

2k.o.

210.0. ~

--V

1

OUTPUT~ir-r~--+-~-+--r-~-r-;

OUT

...J
c:(-6......___3V·5Vk"A_......-o OUT

~4.7Jl.F

100A
2.5MA

~

10Hz FILTER
AV= 25,000

3-450

HA-5170
Typical Performance Curves

OFFSET VOLTAGE vs. TEMPERATURE DRIFT
OF REPRESENTATIVE UNITS

INPUT VOLTAGE NOISE vs. FREQUENCY

o.6

1000

---

----

-

o.5
o.4

f-

I-

0

o.31'-,
o.2b-,..........

Icc:
INPUT NOise CURRENT

o. 1

Or-

§INPUT NOISE VOLTAGE

r:

1--

1111
111111111

1

1

100

0.001
lOOK

10K

lK

o. 1
o.2

f-

1111111

10

v-::

~ t"-"

.,.,.... V

o.3

L

o.4
o. 5
o.6

FREQUENCY !Hz)

IL
_

-550

25 0

=

-

""""
~

25 0

0

~

75 0

500

1000

1250

TEMPERATURE (OC)

BIAS CURRENT vs. TEMPERATURE

SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES

0

0

5

--'
«en
z a:

OW

~V

~~

a: a..

lmV

w:;;

....... V

/

&«

1

0

5

~....... t-........

~~

-1 0

1

0.5

L

.1

/

1.5

SETTLING TIME (jJs)

0.0 1

POWER SUPPLY CURRENT vs.
SUPPLY VOLTAGE AND TEMPERATURE

/'

3
0,00, /
-50 0
250

+1~50C

2

1

V:i..c
,_5

,_ 10

25 0

0

75 0

500

1000

125

TEMPERATURE (OC)

-55°C

,_ 15

,

SUPPLY VOLTAGE (V)

POWER SUPPLY REJECTION RATIO vs. FREQUENCY

......

120

100

III

l~lA-

0

0,

0

0

10

100

1K

10K

1--

120

I;i~r'

It'

so

COMMON·MODE REJECTION RATIO vs. FREQUENCY

-

10 0

,

,
,
lOOK

-_.

0

'I'

0

20

1M

10

FREQUENCY 1Hz}

100

lK

10K

FREQUENCY (Hz)

3-451

,
lOOK

1M

HA-5170
Typical Performance Curves (Continued)
SMALL SIGNAL BANDWIDTH AND PHASE MARGIN
LOAD CAPACITANCE
RL

60

vs.

=',.b

OUTPUT VOLTAGE SWING vs.
FREQUENCY AND SUPPLY VOLTAGE

•

"

II

8

t5viuppLJs

1-

"
az 40"
~
~ 30"
20

?:2•

5

50

..........

"'PHASEMARG~

~

"

,

•

5

8

1000
LOAD CAPACITANCE

NORMALIZED AC PARAMETERS

5o

1

t'-.
100

g

:;1

10

10

w

~

"

0

10000

II

'"z~,0

•

BANDWIDTH

RL"2K
CL = 50pF

"

±10vluppLJs

II

±15V UPPLIES

II

•
0
lK

II

10K

vs. SUPPLY VOLTAGE

MAXIMUM OUTPUT VOLTAGE SWING vs. LOAD RESISTANCE
35

~~ 1.0

II

0

wI-

v,I."kv

"'-.....-..--0 VOUT

• AV =-1
• Feedback and summing resistors
should be 0.1% matched.

• Clipping diodes are optional.
HP5082-2810 recommended.

3-455

HA-5177
Typical Performance Curves

Vs = ±15V, TA = +250 C
VARIOUS CLOSED LOOP GAINS vs. FREQUENCY
RL = 2K, CL = 50pF

OPEN LOOP GAIN AND PHASE va. FREQUENCY

""
,..,
i1

,00r-TO~nmr-rTTnmrrr-rrnn~-'-rnmmr~"TTIm

1111

LIII

120

.1Ji~

'00

o

i

45

Ii:

~

;; '"
" ..,'"

z

20

a

90

III I

0.01

10

0.'

100

ii5

w

135 ~
180

PHASE

·20

lK

10K

lOOK

1M

s:

10M

FREQUENCY (Hz)

'00

'K

PSRR vs. FREQUENCY
'60

....
....

r-...

+PSRR

10

'OM

CMRR vs. FREQUENCY

'60

II I

,..,
,'"

·PSRR

~

.....
.....

r---

i1

~

00

~

....
r---

~

" ..,60

,K

100

.....

'00

~

o

o
0.'

'M

10K
lOCK
FREQUENCY (Hz)

'OK

0.'

10

CLOSED LOOP GAIN AND PHASE vs. FREQUENCY
AV = -1, RL = 2K, CL = 50pF

'K

100

FREQUENCY 1Hz)

FREQUENCY (Hz)

'OK

CLOSED LOOP GAIN AND PHASE vs. FREQUENCY
AV = +1, RL = 2K, CL = 50pF

6
GAIN
3

t\

GAIN

0

1\

3

\

6

•

.,

~

I

0

\

2

.,

i1

~
Ii:
.,:E

45

PHASE

5

I

6

I

'0

'00

tK

10K
tOOK
FREQUENCY (Hz)

90

1\
,M

W

'351.1
il:

'00
'OM

3-456

z

;;

"

~

·3

..
·6

o

."

PHASE

·15

'0

'00

I

lK

10K
tOOK
FREQUENCY (Hz)

Ii:

9O~

\
,M

ffi

45a

1\

I

.,.

m-

w

135~

'OM

'80

il:

HA-5177
Typical Performance Curves

Vs = ±15V, TA = +250 C

OFFSET CURRENT vs. TEMPERATURE
Five Representative Units

!

2

: "r-. ....

1

1l

~

1

.... to--

I
l-

Ii;

BIAS CURRENT vs. TEMPERATURE

i"

r-

0

u

1--

.1

"~

1-1- """"',... 1-i--'

-2

-3

-.
-5

-60

-40

-20

20

40

eo

60

100

2.6
2.5
2.'
2.3
2.2
2.1
2
I.'
1.8
1.7
I .•
1.5
I.'
1.3
1.2
1.1
1
0.'
0.8
0.7
0.6
0.5

~

-55

120

-25

25

50

75

--

125

100

TEMPERATURE (oC)

TEMPERATURE (OC)

-'


/

<

!Q

/'

0

Z

l-

~

8
6

,...---r-r-rnrmr-,-rJ."W"WlLmr--rTTTTrTrr-T""1nTTIm

.....

J LLlIIL JJ.
1-'t:+-P'kH+ttt-+-+ NO~S~'VOlTAGE tttttll--t+t+lttIl

1.2

\.
r'd-+I-H'l'l'II...::I--H-ttttlt-+-ttttlrtlt-t-l-tttttlt
1.0

t~~~~tlt-"~~~~~=*:$$$~l=:$~~~

0.8

75

100

;:

100

lK

10K

lOOK

FReQUENCY (Hz)

OFFSET VOLTAGE vs. SUPPLY VOLTAGE
Six Representative Unita

OFFSET VOLTAGE WARM-UP DRIFT
30

1.4
1.3

20

1'1"-

1.2
1.1

W

"~
Z

0.'

u 0.8
w

"<~

!l
Ii;

~

0

0.7
0.6

,/

0.5

/

Q.4

0.3
0.2
0.1

I

I

-

0

~

-

f"""

-

r-

r-

0

to--

/

-20

-30

5

10

15

SUPPLY VOLTAGE (tv)
TIME AFTER POWER ON (MINUTES)

3-457

'"

Co

TEMPERATURE (DC)

~

a

f-++I-Hfflf-+-H-ttttlt-t-ttttl;/ff--t-I-tttttlt 0.2
125

1.5

ffi
~

I-

1D

50

i

• 1-++I-H+ttt--f''I-lCl:l:HI-+-Ht-HrtIt-t-t+tttttt 0.'

~

25

~

f-++H'I-tflf-+-H-ttttlt-t-ttttl'tfl--t-I-tttttlt 0.6 ~
o
f-++I-H-tfli""<;::1- NOISE CURRENT H-l+HlI-+-H+H~
z

OL-~~LllllL~-LUU~__~~~~~~Lll~

-25

a: c..

I..

20

~~

o

HA-5177
Typical Performance Curves

Vs

= ±15V, TA = +250 C

SLEW RATE vs. SUPPLY VOLTAGE
AV -1, RL 2K, CL 50pF

=

=

0.'

rn

~

0.8

w
~
a:
~

~

0.7

U)

--

BIAS CURRENT vs. DIFFERENTIAL INPUT VOLTAGE

+ SL£WRAYE
I I I

.....

...... ~

=

:;...oSz
w

-SLEW RATE

a:
a:

:J

"j'I

1
0
·1
·2

" ·3
·4

0.6

·5
·6
·7

0.5

·8
-10

20

10
15
SUPPLY VOLTAGE (tV)

5

-8

=

I'

1.26

1'~~.

~ 1,...0

+2SOC

...

~ j;.oo

I'

1..6""

1.18

~ 1.16

.....

:J

~

I'

1.1
(/) 1.08

!J

g"

9.0

...

7.5

~

:J

°

-ssoc

~

~

1/

1.06

~

1.04

12.0

6.0

3.0

10K

1K

=

=

25

17

j

I
!I/

15

0

10

111111

..1

111111

I

OVERSHOOT VS. LOAD CAPACITANCE
Vs ±15V, AV +1, VOUT ±200mV

=

=

27
FAWNG EDGE

24

Ilt~l= tl,~

[

21

(;

18

°

15

'"!J"a:

II

°

Vs= "t5

0

=

30

!.III

~

1M

tOOK

FREQUENCY (Hz)

19

=

I ~~~II~ 15 1

20

0

';::;"

r-

o

OUTPUT VOLTAGE vs. LOAD RESISTANCE
AV -1, VIN 100Hz, Cl 50pF

:=:J

,
"

1.5

11
13
15
SUPPLY VOLTAGE (V)

...>

=

\

4.5

1.02

:J

11

~ 10.5

V

+ 1250C
./
1/

~~

~

aw
:;"
"

=

13.5

a

~

I-"'"

1.24

1.12

10

15.0

1.28

~

-2

OUTPUT VOLTAGE vs. FREQUENCY
AV -1, RL 2K, Cl 50pF

1.3

01.14

-4

DIFFERENTIAL INPUT VOLTAGE (V)

SUPPLY CURRENT vs. SUPPLY VOLTAGE

ffi

-6

J..,..o-

V
V
I'

12

~

....-

I----' t--

~

1.0---"

I-' I-"'"

., ,,-

~i-""'"
RISING EDGE

>;-

.

'";::;

i"
10

1111111
1111111

100
lK
LOAD RESISTANCE (n)

10K

300

3-458

600

900 1200 1500 1800 2100 2400 2700 3000
LOAD CAPACITANCE (pF)

HA-5177
Typical Performance Curves

Vs = ±15V, TA = +25 0 C

SMALL SIGNAL BANDWIDTH AND PHASE MARGIN YS.
LOAD CAPACITANCE
AV= +1
1.05

00

.........

1.03

BO

.........

" ......

1.01

¥ 0.99

"""" I,

BANDWIDTH

~

i!:
0

0.95

§
0
z

0.93

;'i

PHASE MARGIN'
0.92

~

1'0......

0.91

1",\

0.89
0.87

a

PEAK-TO-PEAK NOISE O.1Hz TO 10Hz
Av = 25,000, 0.22~Vp_p RTI

500

i\,

10

0
1000 1500 2000 2500 3000 3500 4000 4500 5000
LOAD CAPACITANCE (pFJ

--I


'"~

OUT

1_6k>

~200.n

.J>

400.n.~

-&
Av = 5
*CL < 10pF

-'


g

OFFSETVOLTAGE~

1

~
~ 0

I

100

BIAS CURRENT - 1.2 -'

r--....

I

I

+40

+80

+120

Unless Otherwise Specified.

I

I

+160

.8

t;

A

0

w

00

80

f\
60

"

«

~ 40

..

0

;;

0
0

PHASE ./

450

GAIN

900

r-..

~

if:

1350

20

-'

z

\

~

1800

0

-10
lK

OUTPUT VOLTAGE SWING vs. FREQUENCY

10K

lOOK

2250

lMEG lOMEG 100MEG
FREQUENCY - (Hz)

NORMALIZED AC PARAMETERS VS. TEMPERATURE
Q

18

w

1.2

~
~\?

1. 1

a:
a:

16

r---

~!:!J 1.0

w+
......

i~

.9

~~

.8

a:",

- :--r--...
/'

~ANDWIDTH~

SLEWRA+E_

~

"

Q>

~g
3

0

.7

«

~
~

8

-80

-40

o
+40
+80
TEMPERATURE - (DC}

+120

6

4

lK

10K

lOOK

10MEG

lMEG

100MEG

FREQUENCY -1Hz)

NORMALIZED AC PARAMETERS VS.
LOAD CAPACITANCE

INPUT NOISE VOLTAGE AND
NOISE CURRENT VB. FREQUENCY

1.2

BANDWy

~

SLEWRATE

10

.8
10

100
LOAD CAPACITANCE - (.F}

200

250

3-464

100
lK
FREQUENCY (Hz)

10K

+160

HA-5190/5195
Typical Performance Curves

(Continued)

OUTPUT VOLTAGE SWING VB. LOAD RESISTANCE

~....
0

SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES

,

"z§E

5J~

12

2:

10

~

I'

on

"........'"
0

>

....
1=

'"
'"

/

0

/

..

2.5

Iii
w

0

~

I

w

5

,

oJ,?"

-

;/"

t---

, /""

w

L

~ -2.5
g
~

200

400

lK

BOO

600

:=

1.2K

...

.....

..J

...........

-5

"

'o"

LOAD RESISTANCE -IOHMSI

o

10

20

30

40

50

60

...........

-

70

~I
80

90

t---

100 110

SETTLING TIME - (ns)

COMMON MODE REJECTION RATIO VB. FREQUENCY

iii"
::!.

POWER SUPPLY REJECTION RATIO VS. FREQUENCY

a:

120

~ tOO

r-....

is

80

~

60

w
c

40

~

z

~
o

::;

'-'

D..

w::;;;

~<

o

~

-'
 5. Gains < 5 are covered elsewhere in
-·this data sheet. Feedback resistors should be of carbon
composition located as near to the Input terminals as
possible.

should be used. When ground planes cannot be used,
good single point grounding techniques should be
applied.
4.

OUTPUrSHORT CIRCUIT: HA-5190/5195 does not
have output short circuit protection. Short Circuits to
ground can be tolerated for approximately 10 seconds.
Short circuits to either supply will result in immediate
destruction of the device.

5.

HEAVY CAPACITIVE LOADS: When driving heavy
capacitive loads (> 100pF) a small resistor ( lOOn)
should be connected in series with the output and inside the feedback loop.

3. WIRING CONSIDERATIONS: Video pulse circuits
should be built on a ground plane. Minimum point to
. point connections direcUy to the amplifier terminals

Typical Applications

(Also see Application Notes 525 and 526)

SUGGESTED COMPENSATION FOR UNITY GAIN STABILITY: NON INVERTING

>-.....-11--0 OUT

>-"""-'-0 OUT
2OO.n.

R1 750.n. *

Vertical Scale: (Volts: 2V/Dlv.)
Horizontal Scale: (Tome: lOOns/Diy.)

Vertical Scale: (Volts: 2V/Diy.)
Horizontal Scale: (Time: lOOns/Diy.)

1

.,.

OUTPU"f

OUTPUT

.. ,

..

'"

lA

,A

y

m

INPUT

INPUT

J
... Values were determined experimentally for optimum speed and settling time. R1 and C1 should be optimized for each
particular application to ensure best overall frequency response.

INVERTING
Vertical Scale: (Volts: 2V/Div.)
Horizontal Scale: (SOns/Diy.)

INo--'\M,....._OO...

>-+-0

OUT

OUTPUT

I-

-,

\

.\.

INPUT

3-466

~

I

I

HA-5190/5195
Typical Applications

(Continued)

VIDEO PULSE AMPLIFIERnSO COAXIAL DRIVER
IN

VIDEO PULSE AMPLIFIER COAXIAL LINE DRIVER

~:c:rl"

120.11

75.11

FAST DAC OUTPUT BUFFER
GAIN

Vertical Scale: (Volts: 2V/Div.)
Horizontal Scale: (Time: SOns/Div.)
B VOUT C Digital Input

=

=

--I

 - - " - - 0 VOUT

• Feedback and summing resistors must be matched
(0.1%).
• HP5082-2810 clipping diodes recommended.
• Tektronix P6201 FET probe used at .ellilng point.

3-470

HA-5221/22
Typical Performance Curves

Vs = ±15V, TA = 250 C

OPEN LOOP GAIN AND PHASE vs FREQUENCY
RL = 1K, CL = 50pF

CLOSED LOOP GAIN vs FREQUENCY
AV = +1, RL = 1K, CL = 50pF
12

iD

"z

""

120
100
80
60
40
20

r-

~

~

GAIN

180

r- r-

135

PHASE

90
45
2

4

clcl

'K

2

GAIN

~

4 6

4

81

tOOK

'OK

2

4 6

f

·6

~

'80

PHAi E

'"

~

46

4

,OOM

'OM

'M

"

·3

8

4

~

6 B 1

2

2

4 6 B 1

4

'\.

2

4

681

'M

90
45
0

40
20

-;....

z

Av-'O

~

<;-10

~

~

AV- ·1000

IE
4 6

,

2\

4

681

'M
FREQUENCY (Hz)

CMRR vs FREQUENCY
AV=+1,RL=1K

PSRR vs FREQUENCY
AV = +1, RL = 1K

'00
80

- -

r-

20

8 ,

,OOK

4

8 ,

,M

4

68 ,

'OM

2

4

m
s
~

:e

60

r-;....
-r-

r-.

,ooM

'OM

FREQUENCY (Hz)

-r4

4

8'

lOOK

'OK

'OOM

'OM

~~
w::;;

&--=~6=--_-o vOUT

Offset Adjustment
The following diagram shows the offset voltage adjustment
configuration for the HA-5221. By moving the potentiometer wiper towards pin 8 (+BAL), the op amps output
voltage will increase; towards pin 1 (-BAL) decreases the
output voltage.
+15V

PC Board Layout Guidelines
When designing with the HA-5221 or the HA-5222, good
high frequency (RF) techniques should be used when building
a p.c. board. Use of ground plane is recommended. Power
supply decoupling Is very important. A 0.011'f to 0.11'f high
quality ceramic capacitor at each power supply pin with a
2.2J.1f to 10l'f tantalum close by will provide excellent
decoupling. Chip capacitors produce the best results due to
ease of placement next to the op amp and basically no lead
inductance. If leaded capacitors are used, the leads should
be kept as short as possible to minimize lead inductance.

Die Characteristics

6

- 15V

A 20kO trim pot will allow an offset voltage adjustment of
about 10mV.
Capacitive Loading ConSiderations
When driving capacitive loads >80pF, a small resistor, 50 to
1000, should be connected in series with the output and
inside the feedback loop.

Transistor Count
HA-5221 .•...•.•.•••..•.••.•...••.••...•.•..••.. 64
HA-5222 •.••.•.•....•....•....•.•.............. 128
Die Dimensions
HA-5221 ....•..•................... 94x 72 x 19mils
(2400 x 1840 x 4801'm)
HA-5222. . • • • . . . . . . . . . . . . . . . • • • • .. 185 x 78 x 19mils
(4690 x 1980 x 4801'm)
Substrate Potential· .•••....•..•••......••.•....•.•. VProcess .•.•••....•..••..•... High Frequency, Bipolar, 01
Passivation ..•.......•.........•......•...•••.••. Silox
Thermal Constants (OC/W)
Ilja
Bjc
HA2-5221 .•.••.•....•.•••..•.•..•.... 163
36
76
HA7-5221 ....•..........•....•.•...•. 152
HA7-5222.. . .•. .• ... . . .•. .. . .. . •. . ... 134
59
·The substrate may be left floating (Insulating Cie Mount) or it may be on a
conductor at V- potential.

Saturation Recovery
When an op amp Is over driven, output devices can saturate
and sometimes take a long time to recover. By clamping the
input, output saturation can be avoided. If output saturation
can not be avoided, the maximum recovery time when
overdriven into the positive rail is 10.6I's. When driven into
the negative rail the maximum recovery time is 3.8I1S.
Input Protection
The HA-5221/5222 has built In back-to-back protection
diodes which limit the maximum allowable differential input
voltage to approximately 5 volts. If the HA-5221/5222 will
be used In circuits where the maximum differential voltage
may be exceeded, then current limiting resistors must be
used. The Input current should be limited to a maximum
of 10mA.

3-476

(I)

g.
(l)

:s
...IIIC:;'

R8
CCS

R7

+BAL

-8AL

I

I

L

CCI

R13

R12

OP54

R26

OP28

.

~~N47
QP48

ON3
">T"10P26
OP22

;:P0N25
QPl

.,.

Ul
I

-oJ
-oJ

y-v

CC3

'=~ ..

44~

QN44

f-------t

OP21

ON2

OZ4

OZS
+IN

I

OZ3

ON4

q;;ONS9~

-g,
RIO

M

CC4

OP16

~QN10
ON6l

I

~
R33
ONs.ON14

I - OP9

,

I---

~

UT

R32

CC7

JONSO
OZI

~ R3S

J

ON55

OP49

QP62

QN32

ON57

C6

r---

ON43

QN33
R23

R24

R27

QN41

R21

ON39
R19

ON37

QN38

R18~

I

QN35

ON36

R17~

r

OPERATIONAL
AMPLIFIERS

R16

RIS

R14

ON34

I

N

....

~
N

R2S
ON45

~

R34

R4

R3

ON1

OP13

.::l.

I - OPS3

o~r-

nONS

~

R11

OP7

OPI2~

r

OP24

ON46

QP23
LL-

OZ2

~

R2A
R2B

.r0PS~

,

OP31

OPSI

~ONS8

CJ)

L

RIA
R1B

R9

OP29

L-

'0
:l

OP11

HA-5232
HA-5234

mHARRIS
PRELIMINARY

Low Cost Precision
Operational Amplifiers

August 1991

Features

Applications

• Low Offset Voltage •••••••••••••••••••• 300JlV (Max)

• Audio Amplifiers

• Low Offset Drift •••••••••••••••••••••••••••• 2JlV/OC

• Low Impedance Sensors

• Low Supply Current •••••••••••••••••.•• <1mAlAmp

• Universal Active Filters

• High Gain, CMRR and PSRR

• Process Control Equipment

Description
The HA-5232 and HA-5234 are dual and quad precision
bipolar-input op amps. They are intended for use in multichannel data acquisition systems where moderate-to-high
level of accuracy is required. This relatively high level of
accuracy is maintained across temperature with an Average
Offset Drift of 2JlV/OC for the high grade parts.
The HA-5232 and HA-5234 were designed to offer a
solution between the lower performance parts like the
HA-4741 or CA324 and the higher priced precision
multiple op amps like the OP-400. These parts will allow the
designer to get a relatively high level of preCision in his
transducer preamp without having to worry about offset
trimming.

Large volume applications will be In process control and en'
vlronment monitoring where many low impedance sensors
such as thermocouples, thermistors, strain gauges, and
pressure transducers are used to assess the state of the
system. Other systems with similar requirements include
mainframe computers, aircraft, and semiconductor fab and
test equipment.
The HA-5232 and HA-5234 are available in commercial
and Industrial temperature ranges, and a choice of pack·
ages. See the "Ordering Information" section below for
more Information.
For military grade product, refer to the HA-5232/883 and
HA-5234/883 data sheet.

Ordering Information

Pinouts
HA9P5232 (8 PIN SOIC)
HA3-5232 (8 PIN PLASTIC DIP)
TOP VIEW

PART
NUMBER

TEMPERATURE
RANGE

HA3-5232-5/A-5

OOCto +700C

8 Pin Plastic DIP

HA9P5232-5/A-5

OOCto +700C

8PinSOlC

HA3-5234-5/A-5

00Cto+700 C

14 Pin Plastic DIP

HA9P5234-5/A-5

00Cto+700C

16PinSOlC

PACKAGE

HA3-5232-9/A-9 -400C to +850C 8 Pin Plastic DIP
HA9P5232-9/A-9 -400C to +850C 8PlnSOlC
HA3-5234 (14 PIN PLASTIC DIP)
TOP VIEW

HA9P5234 (16 PIN SOIC)
TOP VIEW

HA3-5234-9/A-9 -400C to +850C 14 Pin Plastic DIP
HA9P5234-9/A-9 -400C to +850C 16PinSOlC

OUT4

·1N4
+IN4
VEE

+1N3
-1N2

·1N3
OUT3

Tho functional pinouts will comply to tho JEDEC standards for dual and quad op

amps as shown above.
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

3-478

File Number

2851

HA-5234

HA-5232
Schematic

5

0

;:

i0

i!

!

0

I

;;
~
0

~

!
~

"
l
"

~

~

~

0

.

~

K1

11,

~

~

~

"

"

~

.....



+INC)--~--+---~~-------r--~

OUTPUT

INTERNAllY
TRIMMED
INTERNAllY
.....-/TRIMMED

vOFFSET ADJUST

Detailed Description
Overview
The HA-7712/13 BiMOS op amps are pin compatible with
the ICL-7611 CMOS op amp, however pin 8 on the
HA-7712/13 is not connected (pin 8 on the ICL-7611 is the
IQ set pin, which is not required for the HA-7712/13). The
HA-7712 has a quiescent current of 150/lA, and the
HA-7713 has a quiescent current of 1S/lA.
These op amps operate with supply voltages of ±2V to ±8V.
They have very low offset voltages: 2S0",V for the A grade
and SOO",V for the B grade. The HA-7712/13 op amps
offer high open-loop gain, CMRR, PSRR, slew rate and
unity-gain bandwidth. They also have excellent noise performance due to p-channel inputs and NPN loads. The
common mode voltage range of the HA-7712/13 op amps
include the negative supply rail which allows for am plication
of signals including ground In a single supply application.
Static Protection
All devices are static protected by the use 01 Input protection diodes. However, strong static fields should be
avoided, as it Is possible for the strong fields to cause
degraded diode Junction characteristics, which may result
in increased input leakage currents.
Latchup Avoidance
Junction-isolated BiMOS circuits employ configurations
which produce a parasitic 4-layer (p-n-p-n) structure. The
4-layer structure has characteristics similar to an SCR and
under certain circumstances may be triggered into a low
impedance state resulting in excessive supply current. To

avoid this condition, no voltage greater than O.3V beyond
the supply rails may be applied to any pin. In general, the op
amp supplies must be established simultaneously with, or
before any Input signals are applied. If this is not possible,
the drive circuits must limit input current flow to 2mA to
prevent latch up.
Output Stage and Load Driving Considerations
The HA-7712/13 op amps consist of three gain stages:
Input stage, intermediate stage and output stage. The quiescent current flows primarily in the Intermediate and output
stages. The Intermediate stage is for level shifting and the
output stage consists of a common source p-channel
device for sourcing current and a common emitter NPN for
sinking current. The outputs swing to almost the supply rails
for output loads of 1 MO for the HA-7713 and 100kO for the
HA-7712. The gain of the op amp is directly proportional to
the load impedance.
Input Offset Nulling
Offset nulling may be achieved by connecting a 20kO pot
between the OFFSET terminals with the wiper connected to
V-. If offset nulling is not required, the OFFSET terminals
should be left open.
Frequency Compensation
The HA-7712/13 are Internally compensated and are stable
for closed loop gains as low as unity with capacitive loads
up to 100pF.

3-482

Specifications HA-7712

HA-7713

Absolute Maximum Ratings
Storage Temperature Range ................. -650C to +1500 C
Lead Temperature (Soldering, 10 sec) ........ , ......... +3000C
Operating Temperature Range
HA-7712/13-5 (Commercial) .................. OOC to +700 C
HA-7712/13-9 (Industrial) .................. -400 C to +850 C

Total Supply Vo/!age (V+ to V-) ............................ 18V
Input Voltage ...................... '" (V+ +0.3V) to (V- -0.3V)
Differential Input Voltage ...•..•...•... ±[(V+ +0.3V) - (V- -0.3V))
Duration of Output Short Circuit ...................... Indefinite
Current/nto Any Pin .................................... 10mA
Continuous Total Power Dissipation (fA = +25 0C)
Plastic Package ................................... 250mW
SOIC Package .................................... 200mW
TO-99 ........................................... 250mW

Stress above those Jjsted under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Electrical SpeCifications

Test Conditions: V+ = +5V, V- = -5V, TA = +25 0 C Unless Otherwise Specified.
HA-7712/13A

PARAMETER
Input Offset Vo/!age

SYMBOL

TEST CONDITIONS

Vas

HA-7712 RL = 100kCl
HA-7713RL = lMO

HA-7712/13B

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

-

250
350

650

~V

-

-

400

-

~~
w:;;

-400C::: TA :::. +850 C

-

~V

-

-

500

00C--li:--~

Your

~-+--------~--------~~~-------4----~~----~-<~
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @) Harris Corporation 1991

3-485

File Number

2916

Specifications HFA-0001
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- Terminals ••••••••••••••••••••• 12V
Differential Input Voltage ••••••••••••.•••••••••••••••••••••. 5V
Common Mode Input Voltage ••••••••••••••.••••.••••••••• ±4V
Output Current ••••••••••••••••.••.•••.•••••••••••••••• 60mA

HFA-OOOl-9 ••.•••••••.•••••••••••.••••• -400C ~TA~+850C
HFA-OOOl-5 •.••••.••••••••••••••••••.•.•• OOC:S.TA~+750C
Storage Temperature ••.••.••••••..•••••• -650C ~ TA ~ +1500C
Maximum Junction Temperature ••••••••••••••••••••••• +1750C

Electrical Specifications V+ = +5V, V- = .-5V, Unless Otherwise Specified
HFA-0001-9
PARAMETER

HFA-0001-5

TEMP

MIN

TYP

MAX

MIN

+250C

-

12.5

50

TYP

MAX

UNITS

6

30

-

4.5

30

-

6

30

mV

4.5

30

-

12.5

mV

35

mV

INPUT CHARACTERISTICS
Offset Voltage

High
low

100

-

15

100

20

100

"A
,.A

-

18

50

,.A

-

22

50

,.A

-

-

KO

High

-

50

low

-

100

-

+250C

15

100

Full

-

20

100

+25OC

-

18

50

Full

-

22

50

Common Mode Range

+250C

±3

-

-

±3

Differential Input Resistance

+25OC

-

-

2

-

3.5

-

-

640

-

-

170

-

0.57

-

nNy'Hz

0.18

-

nN.,;Hz

-

150

200

100

170

150

220

42

47

40

45

-

42

48

-

-

350

1

-

Average Offset Voltage Drill

Bias Current

Offset Current

+250C

-

Input Noise Voltage

0.1 Hz to 10Hz

+250C

-

10HztolMHz

+25OC

Input Noise Voltage

10= 10Hz

+25OC

Input Capacitance

Input Noise Current

10
2
3.5

10= 100Hz

+250C

1o = 1000Hz

+250C

'0=10Hz

+25 0C

10= 100Hz

+250C

10= 1000Hz

+250C

-

+250C

150

200

High

150

170

6.7
640
170
43
2.35
0.57
0.16

-

50

10

6.7

43
2.35

"VloC
"VJOC

V

pF
"Vrms
"Vrms
nVl.,;Hz
nVl.,;Hz
nVl.,;Hz
nNy'Hz

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Note 2)

low

150

220

+250C

45

47

High

40

45

low

45

48

Unity Gain Bandwidth

+250C

-

350

Minimum Stable Gain

Full

1

-

Common Mode Rejection Ratio (Note 3)

-

VN
'IN
VN
dB
dB
dB
MHz
VN

OUTPUT CHARACTERISTICS
RL=1000

+250C

-

±3.5

RL=lk

+25 0C

±3.5

±3.7

High

±3.0

±3.6

low

±3.5

±3.7

Full Power Bandwidth (Note 5)

+250C

Output ReSistance, Open loop

+250C

-

Full

±30

Output Voltage Swing

Output Current

3-486

53
3
±50

-

-

±3.5

±3.5

±3.7

±3.0

±3.6

±3.5

±3.7

±3O

53
3
±50

-

V

-

V
V
V
MHz
0
mA

Specifications HFA-OOO 1
Electrical Specifications (Continued) V+ = +5V, V- = -5V, Unless Otherwise Specified
HFA-00Ol-5

HFA-OOOl-9
PARAMETER

TEMP

MIN

TYP

MAX

MIN

TYP

480

-

1000

36

75

UNITS

MAX

TRANSIENT RESPONSE
Rise Time (Note 4, 6)
Slew Rate (Note 4, 7)
Settling Time (3V Step)

+250 C
RL=lK

+250 C

RL=l00n

+250 C

0.1%

+25 0 C

Overshoot (Note 4, 6)

+250 C

-

1000
875
25

V/~s

36

-

-

65

75

rnA

37

42

-

dB

-

480
875
25

ps
V/~s

ns
%

POWER SUPPLY CHARACTERISTICS
Full

-

65

+250 C

40

42

Supply Current
Power Supply Rejection Ratio (Note 8)

High

35

41

Low

40

42

-

35

41

37

42

dB
dB

NOTES:
....I



15

~ 10

!z

5

Iii
en
tt

-10

"'IE 0
a -5

I-'

-15

0-20

-::06O,L,-J1.._.14O~_""20~.JO,-L-:!20l:-l""'401:-l""60~-80:l::-J1..1-!-00:.1-1~20~

-25

-60 -40 -20

TEMPERATURE \"C)

0

20

40

60

80 100 120

TEMPERATURE (DC)

3-489

!.i§
a: a..
~...:

TEMPERATURE (DC)

BIAS CURRENT vs TEMPERATURE
3 Representative Units

--'
...: en
:z a:
OW

HFA-0001
Typical Performance Curves

(Continued) Vs = ±5V, TA = +250 C, Unless Otherwise Specified

OPEN I:OOP GAIN vs TEMPERATURE
RL = 11<, VOUT = 0 to ± 2V

OUTPUT VOLTAGE SWING VB TEMPERATURE
RL= lK
4.6
4.4

300

280
280

~2~

~ ::~

-AVOL

--220
z 200
;;: 180
"180
&140

+AVOL

~ 3.6

~i!i

~ ~~

9 ~~
Z

o

+VOUT

~ 3.0
II.

80
80
40
20

~

-VOUT

~ 3.8

2.8

~ 2.6

o 2.4

o

-80-40-20

0

20

40

80

80

2.2
2.0
-80-40-20

100120

TEMPERATURE (DC)

SLEW RATE vs TEMPERATURE
Av
+1, RL 100, VOUT ± 3V

=

=

=

I I

moo

-CMRR

~48

+SL~WIRATE

~
~

600

46
44

~

+CMRR

42
40

38
38

500

-80 -40 -20

0

20 40

34

80 100 120

80

-80-40-20

TEMPERATURE (DC)

90

20

40

<"80

E
;:50

,

/

Z

~50

!l!4O

~4O

G30

II:

+PSRR

ill

10

0

20 40

80

10

o

80 100 120

TEMPERATURE (DC)

~
o

2

/
3

SUPPLY VOLTAGE

3-490

/

/

~

8:20

20

-40 -20

100120

SUPPLY CURRENT vs SUPPLY VOLTAGE

..!P~R~

~30

80

80

70

I II

.

0

TEMPERATURE (DC)

PSRR vs TEMPERATURE
I:J.Vs = ±4V to ±6V

-80

100120

54

52

700

o

80

56

~ste~~lTJ

800

mIlO

80

-58

900

70

40

80

1100
'iii'
:I. 1000

80

20

CMRR vs TEMPERATURE

- 1200

~

0

TEMPERATURE (DC)

4

ttY)

5

HFA-0001
Typical Performance Curves

(Continued) Vs = ±5V, TA = +250 C, Unless Otherwise Specified
MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY
AV = +1, RL = 100n, THD < 1%
5.0

SUPPLY CURRENT vs TEMPERATURE
70
68
~ 66

-S64

~

I- 62

(!l

4.5
4.0

z

moo

§

~58

rn 3.5

~54

(!l

w
<

3.0

!J
0

2.5

I-

2".0

;;) 56
[

52

0..50

>

iil48

;;)

46

44
-50 -40 -20

0..
I-

0
20 40 60 80
TEMPERATURE (DC)

1.5

;;)

100 120

I' I'.

0

"15

1.0

0..

0.5
0
1M

OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
AV = +1, 10 = 50kHz, THO < 1%

~
(!l

z

§

rn

w

(!l

~
0

0..
I-

;;)

5.0

240

4.5

220

4.0

200

3.5

~180

3.0

z
;;:

0..

Il~loL
+ AVOL

160

0

9
zW

1.5

120

0.. 100

0
1.0

80

0.5

60

0
10

100
1K
LOAD RESISTANCE (.0.)

40
10

10K

100

4-

!J

3

>

2

<
0

w

~ 1
0

Z 0

6 ....


w

w

rn 100

1 ~
0
100K

~

0

0

10K

-~

0 200

2(.)

~-~~
'" I

CURRENT

Z

Z

~

k:

~

0
100

3-491

N~EVOLTAGE

)

500~
...

<
4OO-S

\.

300

!J

;;)

I:- NoiSE VOLTAGE

600

>

4 Z
w
0:
30:

\

1

~~500 ~OISEI

7:r:

\

=-5
W

600

~

~7 IV
>-6
(!l

INPUT NOISE vs FREQUENCY

B

NOISE CURRENT

10K

1K

LOAD RESISTANCE (.0. )

INPUT NOISE vs FREQUENCY

B

1K
10K
FREQUENCY (Hz)



I-

;;)

10M
100M
FREQUENCY (Hz)

300m0:

0:
200 ;;)
()

w

100 rn

0

0
100K

Z

HFA-0001
Typical Performance Curves

(Continued) Vs = ±SV, TA = +2S o C, Unless Otherwise Specified

INPUT VOLTAGE NOISE
0.1Hz to 10Hz
AV = 50, Noise Voltage = 1.60511Vrms (RTI)
Noise Voltage = 10.12I1Vp-P

INPUT NOISE VOLTAGE
10Hz to 1MHz
AV = 50, Noise Voltage = 5.3611Vrms (RTI)
Noise Voltage = 29.88/lVp-p

Applications Information
Offset Adjustment

PC Board Layout Guidelines

When applications require the offset voltage to be as low as
possible, the figure below shows two possible schemes for
adjusting offset voltage.

When designing with the HFA-0001, good high frequency
(RF) techniques should be used when making a PC board.
A massive ground plane should be used to maintain a low
impedance ground. Proper shielding and use of short
interconnection leads are also very important.

Adjustment
Range"'±V
FIGURE 1. INVERTING GAIN
For a voltage follower application, use the circuit in Figure 2
without R2 and with Ri shorted. R1 should be 1Mo. to
1OMo.. the adjustment resistors will cause only a very small
gain error.

Adjustment
Range"'±V

To achieve maximum high frequency performance, the use
of low impedance transmission lines with Impedance
matching is recommended: SOo. lines are common in communications and 7So. lines in video systems. Impedance
matching Is important to minimize reflected energy
therefore minimizing transmitted signal distortion. This Is
accomplished by using a series matching resistor (SOo. or
7So.), matched transmission line (SOo. or 7So.), and a
matched terminating resistor, as shown in the figure below.
Note that there will be a 6dB loss from input to output. The
HFA-0001 has an integralSOo. ±20% resistor connected to
the op amps output with the other end of the resistor pinned
out. This SOo. resistor can be used as the series resistor instead of an external resistor.

Gain "'1+
FIGURE 2. NON-INVERTING GAIN

3-492

HFA-0001
Applications Information

(Continued)

PC board traces can be made to look like a 50n or 75n
transmission line, called microstrip. Microstrip is a PC
board trace with a ground plane directly beneath, on the
opposite side of the board, as shown below.
SIGNAl
TRACE

L

_

I-w-l ___ _

1
t

-T

h

t

Er

DIELECTRIC
(PC BOARD)

GROUND
PLANE

When manufacturing pc boards, the trace width can be
calculated based on a number of variables. The following
equation is reasonably accurate for calculating the proper
trace width for a 50n transmission line.

ZO=

~

v'E r + 1.41

input to safe levels, output saturation can be avoided. " output saturation cannot be avoided, the recovery time from
25% over-drive is 20ns and 30ns from 50% over-drive.
Thermal Management
The HFA-0001 can sink and source a large amount of
current making it very useful in many applications. Care
must be taken not to exceed the power handling capability
of the part to insure proper performance and maintain high
reliability. The following graph shows the maximum power
handling capability of the HFA-0001 without exceeding the
maximum allowable junction temperature of 1750 C. The
curves also show the improved power handling capability
when heats inks are used based on AWID heatsink
#5801 B for the B pin Plastic DIP and IERC heatsink
#PEP50AB for the 14 pin Sidebraze DIP. These curves are
based on natural convection. Forced air will greatly Improve
the power dissipation capabilities of a heatsink.
3.0
2.8

Ui 2.6

t:

2.4
~ 2.2

In ( 5.9Bh )n

O.Bw+t

r--- .....
f--"o.

-

Power supply decoupling is essential for high frequency op
amps. A 0.011lf high quality ceramic capacitor at each
supply pin in parallel with a 11lf tantalum capacitor will
provide excellent decoupling as shown in Figure 3. Chip
capacitors produce the best results due to ease of
placement next to the op amp and they have negligible lead
inductance. " leaded capacitors are used, the leads should
be kept as short as possible to minimize lead inductance.
The figures below illustrate two different decoupling
schemes. Figure 4 improves the PSRR because the resistor
and capacitors create low pass filters. Note that the supply
current will create a voltage drop across the resistor.

2.0
1.8
~ 1.6
~ 1.4
!!l 1.2
c 1.0
0.8
00.;:: 0.6

15

...J

_B _A: 8 PIN PLASTIC DIP WITH HEATSINK

f-=:;

ffi

._

~; ~":.~Np~;r:~~~ ~I~L~H HEATSINK_

<.: ~~:
.......

14 PIN SIDEBRAZE DIP ONLY

- --- " ""' ....."'
D

-

..... r--...

~

IIlIIt..

C

r"'IIIII

........ ::......
......

;,:000....

...;:
I"IIIb

0.4

0.2
020

40

60
60
100
AMBIENT TEMPERATURE (OC)

Thermal Constants (OCM)

Saturation Recovery
When an op amp is over driven output devices can saturate
and sometimes take a long time to recover. By clamping the

HFA1-0001-5/-9 ............ .
HFA3-0001-5 ............... .
HFA9P-0001-5/-9 ........... .

120

9ja

Sjc

75
98

36

96

27

13

+V

+v

-v

FIGURE 3. POWER SUPPLY DECOUPLING

FIGURE 4. IMPROVED DECOUPLING/CURRENT LIMITING

3-493

----P-....-OVOUT

son.

LARGE SIGNAL RESPONSE
Input: O.2V/Div. Output 2V/Div.
Horizontal Scale: 20ns/Div.

SMALL SIGNAL RESPONSE
Input 10mV/Div. Output 100mV/Div.

O.3V

10mV
IN OV

IN

OV

-10mV
-O.3V
3V

100mV

OUT OV

OUT OV
-100mV

-3V

·SETTLING TIME SCHEMATIC
~---",,-,--oVSErrr£

• AV =-1
• Feedback and summing resistors must be matched

lK

(0.1%)

10K

• HP5082-2810 clipping diodes recommended

5K

• Tektronix P6201 FET probe used at setlling point

500
>--<~-oVOUT

3-496

HFA-0002
Typical Performance Curves Vs = ±5V, TA = +250 C, Unless Otherwise Specified
CLOSED LOOP GAIN vs FREQUENCY
AV = +10, RL = 5K, CL = 20pF

OPEN LOOP GAIN AND PHASE vs FREQUENCY

,
~

z

~

120 f100 I-

ao f-

...

...

60 f40 f20 f-

f-

f-

ffia:

""

ffff-

7:-

lK

w

40

~

e.

PHASE

lao ~

1M
10M
FREQUENCY (Hz)

lOOK

ifiw

'- "

<.!l

90 ""
45 ::;

a:

""'-.

"'",

-20

<.!l

w

o
45
90

e.
~
rn

w

135 ~

o ~

5'D.!
10K

GAIN

20

135~

PHASEf-

i"'-

60

10
:!!.
Z
;;:

<.!l

o f-

1=

I

ao
GAIN

180

1M

10M
FREQUENCY (Hz)

100M 500M

100M

B:

200M

®
--'

~
_
z

-

0

tu -200
~

=

200~~~~~~-r-r-r-r-r~~-'-'-'-'r-r-~

700

400
300
200
100

120

TEMPERATURE (oC)

OFFSET CURRENT vs TEMPERATURE
4 Representative Units

<
.s
!z

100

80

~ :~

~

-600
-700

_

-600

-60

-40

-20

o

20

40

60

80

100

120
110
100
90

§

130

20
10

111111111111111111111

o

-60

120

-40

o

-20

TEMPERATURE (oC)

20

40

60

80

100

120

TEMPERATURE (oC)

OUTPUT VOLTAGE SWING vs TEMPERATURE
RL=5K

OUTPUT CURRENT vs TEMPERATURE
VOUT= ±3V
15

4.8

>"
.±!
w
«

Cl

~

~

...

:J

..."-

:J

0

.:

US
"-

4.6
4A
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4

<14
E

I-

_I"'"

±!
io'"

!zw 13
1€:J
tJ 12

~

511

-60

-40

-20

o

20

40

60

80

100

10

120

TEMPERATURE (oC)

-60

-40

-20

0

20

40

60

TEMPERATURE (OC)

3-498

80

100

120

HFA-0002
Typical Performance Curves (Continued) Vs

= ±5V, TA = +25 0 C, Unless Otherwise Specified

CMRR vs TEMPERATURE
VCM = 0\0 ±3V

PSRR vs TEMPERATURE
~Vs = ±4V \0 ±6V
140

140

130

130

+ PSRR

120

in
::?

120

i' i'r--

a:
a:
~ 110

in
::?

a: 110

r--~

a:
c.

'"

100

90

-PSRR
100

90

-60

-40

-20

020406080

100

80
-60

120

-40

·20

0204060

TEMPERATURE (OC)

80

100

120

TEMPERATURE (OC)
...J

«en
za:

SUPPLY CURRENT vs SUPPLY VOLTAGE

15

:?
/'

E
;:: 14

I'

Z

w
a:

~
c.
c.

6
5
4
3

;:J

(J

I......

~ 12
c.
c.

ri""

io-"i-"'i"""

a: 13

7

'"

~~
:5«
w::;;;

(J

:J

-u::

SUPPLY CURRENT vs TEMPERATURE
16

16
15
14
13
:? 12
511
....z 10
w
a: 9
a: 8
:J

OW

1"'1'

:J

'"

1/

11

~

1

o
2.0

2.4

3.2

2.8

3.6

4.0

4.4

10
·60

4.8

·40

-20

0204060

80

100

120

TEMPERATURE (oG)

SUPPLY VOLTAGE (t V)

OUTPUT VOLTAGE SWING vs FREQUENCY
AV = +10, RL = 5K,

OPEN LOOP GAIN vs LOAD RESISTANCE
VOUT = ±3V

5

200
180

~

t!l

z

4

;:

'"t!lw 3
<:

~

§:

:;-

.g

1\
\

1M

c.

9

80

zw

c.

60

0

40
20

~

o

120
100

0

!\

~ 1
w
c.

Z

~

\

....
;:J
o

140

C!.

\

~ 2
c.

160

10M

100M

~

0
10

lG

100

lK

LOAD RESISTANCE (ll.)

FREQUENCY (Hz)

3-499

10K

HFA-0002
Typical Performance Curves

(Continued) Vs = ±5V, TA = +250 C, Unless Otherwise Specified

OUTPUT VOLTAGE SWING vs LOAD RESISTANCE

RISE TIME vs TEMPERATURE
5

5~~-'-rTTnmr-~~~rMnn---r~~rnTM

4

... 1"""

..-."-'~

o
-60

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (DC)

°l~O--~-L~-U~l~oo---L~-L~~l~K~~-L~-U~l~OK

LOAD RESISTANCE (n.)

INPUT NOISE vs FREQUENCY
10

~:;

9

9~

8

8 ~

-w

7

<

t!l

6

!J
0

5

c

III

....:::J

3

........."",OISE CURRENT

t-...

" i""'-...

~60

6 c:ffi

~50
<

0!: 1

III

~40
>
lJl30

z

15
z

§

5
4 ~.
3

15

2 ....

2

:::J
0-

NOISE VOLTAGE

!:

o

o

100

lK
10K
FREQUENCY (Hz)

~ 70

,e

7 ....

> 4
w

15
z

INPUT NOISE vs FREQUENCY
80

10

....

20

80

~

\

o

....
50ffi

1\ \
\\
\'

c:

, "- -

1

100
lK
FREQUENCY (Hz)

INPUT NOISE VOLTAGE
10Hzto1MHz

= 25,000, Noise Voltage = 3.31nVrms (RTI)

AV

3-500

4O§U
30lJl

15

20 Z

....:::J

100-

'-

10

INPUT NOISE VOLTAGE
0.1 Hz to 10Hz

AV

8O,e

~ 10 NOISE
!:
VOLTAGE

lOOK

70~

NOISE CURRENT

!:

10K

= 25,000, Noise Voltage = 17.89nVrms (RTI)

o

lOOK

HFA-0002
Applications Information
Offset Voltage Adjustment
The HFA-0002, due to its low offset voltage, will typically
not require any external offset adjustment. If certain applications do require lower offset, the following diagram shows
one possible configuration.
+5V

output and at the high impedance inputs should be kept
to a minimum, to prevent any unwanted phase shift and
bandwidth limiting.
When breadboarding remember to keep feedback resistor
values low (~5kn) for optimum performance. The use of
metal film resistors for values over 200n and carbon film
resistors under 200n typically gives the best performance.
Remember to keep all lead lengths as short as possible to
minimize lead inductance.
Sockets will add parasitic capacitance and inductance
and therefore can limit AC performance as well as reduce
stability. If sockets must be used, a low profile socket with
minimum pin to pin capacitance will minimize any performance degradation.
Power supply decoupling is essential for high frequency
op amps. A 0.011lF high quality ceramic capacitor at each
supply pin in parallel with a 11lF tantalum capacitor will
provide excellent decoupling. Chip capacitors produce the
best results due to the ease of placement next to the op amp
and they have negligible lead inductance. If leaded capaCitors are used, again the lead lengths should be kept to a
minimum.
Saturation Recovery

The power supply lines must be well decoupled to filter any
power supply noise. A 20K trim pot will allow an offset
adjustment of about 3mV, referred to input.
PC Board Layout Guidelines
When designing with the HFA-0002, good high frequency
(RF) techniques should be used when doing pc board
layouts. A massive ground plane should be used to maintain
a low impedance ground. PC board traces should be kept
as short as possible and kept wide to minimize trace inductance and impedance. Stray capacitance at the op amps

When an op amp Is over driven output devices can saturate
and sometime take a long time to recover. By clamping the
input to safe levels, output saturation can be avoided. If output saturation cannot be avoided, the recovery lime for an
input sine wave at 25% overdrive is 100ns.
Thermal Constants (OC/W)

3-501

HFA2-0002-5/-9 ............ .
HFA3-0002-5/-9 ............ .
HFA7-0002-5/-9 ............ .
HFA9P-0002-5/-9 ........... .

Sja

Sjc

117

36

96

34
13
43

75
158

....I


g

15

w
~
~

10
5
0

r..

I-

Z
w
~

§: - 5
tu ~ 10

50
40
30
20
10
0

13 - 10

*-

- 20

- 25

- 60 - 40 - 20 0

20 40

60 80 100 120

OFFSET CURRENT vs TEMPERATURE
3 RepresentatiYe Units

30

350
~ 300

10

I- W

~

20

~

~AVOL

200

"-

",,,,

0150

g

z 100
w

-

0-

JA~JL
.iT

;250

0
10

:::l
U

80 80 100 120

OPEN LOOP GAIN vs TEMPERATURE
RL = lK, VOUT = 0 \0 ±2V

::;- 20

.:;

20 40

TEMPERATURE (DC)

TEMPERATURE (DC)

IZ
W
0:
0:

...

(I) - 20
iii - 30
- 40
- 50
- 60 - 40 - 20 0

..;

15

40
50
- 80- 40- 20 0

"-

o 50

o

20 40 80 80 100 120

- 60 - 40 - 20 0

TEMPERATURE (DC)

20 40

60 80 100 120

TEMPERATURE (DC)

OUTPUT VOLTAGE SWING vs TEMPERATURE
RL= lK

SLEW RATE vs TEMPERATURE
AV = +1, RL = lOOn, VOUT = 3V

600

5.0,-,r-r-r..-"-r-r-r-rT-r..-"r-r-r,,
~ 4.8t-!H-++-f-t-!H-++-f-Hn-++-I-H

-SLEW RATE

~

4.6t-!H-++-f-t-!H-++-I-H-+++-I-H
- 4.4H-++-f-H-++-HH+-f-H-++-H

"iii

~ 4.2+:~~;+~~~$:~~:t~~~~~~

500

¢400

+ SLEW RATE

~

w 4.0+
~ 3.8i-HH-+-+++-i-HH-+-+++-i-HH
~ 3.6i-HH-+-+++-i-HH-+-+++-i-HH
§: 3.4i-HH-+-+++-i-HH-+-+++-i-HH
I- 3.2i-HH-+-+++-i-HH-+-+++-i-HH
:::l 3.0t-Hri-+++-f-t-Hri-+++-f-t-Hri
~ 2.8t-Hri-+++-f-t-Hri-+++-f-t-Hri
2.6t-!H-++-f-t-!ri-++-I-H-+++-I-H
2.4.L-1'-1.....L....L..L-1....L-'-.l-JL-L....L....L...L-I'-1.....L..1-J
-80 -40 -20 0 20 40 60 80 100 120

w

I-

..;

300

0:

:;: 200
w
..J

(I)

5

100

o

-60 -40 -20 0

20 40

60 80 100 120

TEMPERATURE (DC)

TEMPERATURE (DC)

3-506

HFA-0005
Typical Performance Curves

(Continued) Vs

= ±5V, TA = 25 0 C, Unless Otherwise Specified
PSRR vs TEMPERATURE
avs ~ ±4V to ±6V

CMRR vs TEMPERATURE

70

100
90
80
70
CD 60

60

j

50

CD

'a:"

'"
a: 40
a:
::;; 30
tl

a:

I I I
I I I

:_ket

R

I I I

50

40

+ PSRR

20

30

10~-+~~~-r~~-+~~~-r~~

20
10

I I I
I II

(/)

"-

o

?60~__L40~-~2~0~0~~20~~40~~60~~60~~10~0~12~0~

I I I

- 60 - 40 - 20

0

20

40

60

80 100 120

TEMPERATURE (DC)

TEMPERATURE (DC)

SUPPLY CURRENT vs SUPPLY VOLTAGE

--'
«en
za::
ow

SUPPLY CURRENT vs TEMPERATURE

~§
a:: D.

34

32

.§.

!z 35t1=rlrTiIt-tt-tl~~~ttj:±:ti

24
22
20
a: 18
~ 16
tl 14
>- 12
~

!zUJ

:l

(/)

w:;;
~«

< 40H-+++-H++-H-++H-+++-H

=

3.0

1\

2.5

>

200
100
-60 -40 -20

C!l
Z

0

20

40

60

80 100 120

TEMPERATURE (DC)

f:l

2.0

:l

1.5

"f-

0

>::
« 1.0

UJ

"- 0.5

.......

o

1M

10M

100M

FREQUENCY (Hz)

3-507

lG

HFA-0005
Typical Performance Curves

(Continued)

Vs = ±5V, TA = +250 C,

OPEN LOOP GAIN vs LOAD RESISTANCE
VOUT = 0 to ±3V

OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
5.0

~ 4.0
Cl

Z

~w
~
~
§;
t~
t-

El

250

-VO~T

4.5

>

+VOUT

-AVOL

-

225
200

V

3.5

Unless Otherwise Specified

+AVOL

~ 175

Z

;;:

3.0

150

Cl

2.5

"- 125

2.0

g

100

zw

75

0

1.5

"-

0

1.0

50

0.5

25

o

o
10

100
lK
LOAD RESISTANCE (n.)

10

10K

100
lK
LOAD RESISTANCE (n.)

INPUT NOISE vs FREQUENCY

INPUT NOISE vs FREQUENCY

10

~:;

:

W
Cl

6

7

=

5

~

4

UJ
til

2

i5

1

Z

0

10

i"o...
1

:>

.:.

"I '

"'

10

I
I
vNOISE VOLTAGE

7"-100.
100
lK
FREQUENCY (Hz)

10K

o

700

700~

600

600;':

Co

-" 500 I\.
w
"\./NOISE CURRENT
(!j

!z

NOISE CURRENT

~

~ 3

~

7 <
6
5 w
4 c::
c::
::>
3 ()
2 W

I\,
\.

BOO

BOO

:~

,

10K

~
0

400

W 200

'5"
Z

lOOK

Z

400~

"\.

300

>

'"5Z

500;:-

r-.....

100

o
100

300g;

~

()

"'

. / NOISE ViLTAGE- 200w

lK

o
10K

FREQUENCY (Hz)

INPUT NOISE VOLTAGE
AV = 50, Noise Voltage = 1.646~Vrms (RTI)

INPUT NOISE VOLTAGE

AV

3-508

'"z

1005

~

= 50, Noise Voltage = 5.56811V,ms (RTI)

lOOK

HFA-0005
Applications Information
Offset Adjustment

PC Board Layout Guidelines

When applications require the offset voltage to be as low as
possible, the figure below shows two possible schemes for
adjusting offset voltage.

When designing with the HFA-OOOS, good high frequency
(RF) techniques should be used when making a PC board.
A massive ground plane should be used to maintain a low
impedance ground. Proper shielding and use of short
interconnection leads are also very important.
To achieve maximum high frequency perforn)ance, the use
of low impedance transmission lines with impedance
matching is recommended: son lines are common in communications and 7Sn lines in video systems. Impedance
matching is important to minimize reflected energy
therefore minimizing transmitted signal distortion. This is
accomplished by using a series matching resistor (50 or
7Sn), matched transmission line (50 or 7Sn), and a
matched terminating resistor, as shown in the figure below.
Note that there will be a 6dB loss from input to output. The
HFA-OOOS has an integral son ±20% resistor connected to
the op amps output with the other end of the resistor pinned
out. This son resistor can be used as the series resistor
instead of an external resistor.

Adjustment (RR21 )
Range",±V

FIGURE 1. INVERTING GAIN

For a voltage follower application, use the circuit in Figure 2
without R2 and with Ri shorted. R1 should be 1 MVto 10MV.
the adjustment resistors will cause only a very small gain
error.

50A

50A COAX CABLE

:5«

SIGNAL
TRACE

LI-w-l - - - (RR21)

~§

a: c..

UJ::;;:

PC board traces can be made to look like a 50 or 7Sn
transmission line, called microstrip. Microstrip is a PC
board trace with a ground plane directly beneath, on the
opposite side of the board, as shown below.

Adjustment
Range"'±V

...J

«en
za:

QUJ

+

t

-T

t

h

Gain'" 1 + (Ri :fR2 )

1

Er

RGURE 2. NON-INVERTING GAIN
GROUND
PLANE

3-509

DIELECTRIC
(PC BOARD)

HFA-0005
Applications Information

(Continued)

When manufacturing pc boards the trace width can be
calculated based on a number of variables.
The following equation is reasonably accurate for calculating
the proper trace width for a son transmission line.

Zo=

87
v'E r + 1.41

In ( S.98h
0.8w + t

)n

Power supply decoupling is essential for high frequency op
amps. A 0.01/1f high quality ceramic capacitor at each
supply pin in parallel with a 1/1f tantalum capacitor will
provide excellent decoupling. Chip capacitors produce the
best results due to ease of placement next to the op amp
and they have negligible lead Inductance. If leaded capacitors are used, the leads should be kept as short as possible
to minimize lead inductance. The figures below Illustrate
two different decoupling schemes. Figure 4 improves the
PSRR because the resistor and capacitors create low pass
filters. Note that the supply current will create a voltage drop
across the resistor.

Saturation Recovery
When an op amp is over driven output devices can saturate
and sometimes take a long time to recover. By clamping the
input to safe levels, output saturation can be avoided. If output saturation cannot be avoided, the recovery time from
2S% over-drive is 20ns and 30ns from SO% over-drive.
Thermal Constants (OC/W)
HFA2-000S-S/-9 .............
HFA3-000S-S ................
HFA7-000S-S/-9 ••••.•.......
HFA9P-000S-S/-9 .•...••...••

+v

+v

c

c~
c~
c

-v

FIGURE 4.

FIGURE 3.

3-S10

eja

ejc

120
98
7S
1S8

37
36
13
43

m

ICI.76XX

HARRIS

ICL76XX Series Low Power
CMOS Operational Amplifiers

August 1991

Features

Applications

• Wide Operating Voltage Range ±1V to ±8V

• Portable Instruments

• High Input Impedance - 1012 0

• Telephone Headsets

• Programmable Power Consumption - Low as 20IJW

• Hearing Aid/Microphone Amplifiers

• Input Current Lower Than BIFETs - Typ 1 pA

• Meter Amplifiers

• Available as Singles, Duals, and Quads

• Medical Instruments

• Output Voltage Swings to Within Millivolts of
V- and V+

• High Impedance Buffers

• Low Power Replacement for Many Standard
Op Amps
...I

---------+

3K

900K

OFFSET CD

6.3Y

lOOK

+INPUT++

'--+---ti--4--

y-

OUTPUT

Cc = 33pF

y+
-INPUT

y-

6.3Y

TABLE OF JUMPERS

ICL-7611
ICL-7612
ICL-7621
ICL-7641
ICL-7642

B, F, H

B,F,H
C,E
C,G
A,E

~--~~--~------+-~_r----+-----+---~--~~Y-

y+
o---li....~---.T Temperature Coefficient of VOS Rs"; 1OOkO (Note 5)
los

Typ

20
25

20

TA=25°C
.HA=C
f>.TA=M

0.5

TA=25°C
.HA=C
f>.TA=M

1.0

0.5

50
500
4000

1.0

±4.4
±4.2
±3.7

±4.4
±4.2
±3.7

10=10p.A(1), RL =1MO
TA = 25°C
f>.TA=C
f>.TA=M

±4.9
±4.8
±4.7

±4.9
±4.8
±4.7

10= 100/LA(3), RL = 100kO
TA=25°C
f>.TA=C
f>.TA=M

±4.9
±4.8
±4.5

±4.9
±4.8
±4.5

10= 1mA(2), RL =10kO
TA=25°C
f>.TA=C
f>.TA=M

±4.5
±4.3
±4.0

±4.5
±4.3
±4.0
104

80
75
68

104

Vo= ±4.0V, RL = 100kO(3)
10=100p.A(3), TA=25°C
f>.TA=C
f>.TA=M

80
75
68

102

80
75
68

102

VO= ±4.0V, RL = 10kO(2)
10=1mA(2), TA=25°C
f>.TA=C
f>.TA=M

76
72
68

98

76
72
68

98

1012

NOTE: An typical values have b8Bn chsrBctsriz9d but are not test8d.

3-518

70
70
60

96
91
87

70
70
60

pA

50
500
4000

pA

V

80
75
68

Rs";100kO,lo=10p.A(1)
Rs"; 100kO,IO= 100p.A
Rs";100kO,lo=1mA(2)

30
300
800

V

Vo= ±4.0V, RL =1MO(1)
10=10p.A(1), TA=25°C
f>.TA=C
f>.TA=M

0.044
0.48
1.4

mV
flV/oC

30
30
300
800

io=10p.A(1)
10=100p.A(3)
10=1mA(2)

10= 10/LA(1)
la=100p.A(3)
10=1mA(2)

Units
Max

dB

0.044
0.48
1.4

MHz

1012

0

96
91
87

dB

ICL76XX
ELECTRICAL CHARACTERISTICS (7641/42 ONLY)

(Continued)

(VSUPPLY= ± 5.0V, T A = 25'C, unless otherwise specified.)
Symbol
PSRR

Parameter
Power Supply Rejection Ratio
VSUPPLY= ±8V to ±2V

76XXC(6)

Test Conditions
Rs:S:100kn,lo= 10,.,A(1)
Rs:S:100kn,lo= 100,.,A
Rs:S: 100kn, 10 = 1mA(2)

Min

Typ

80
80
70

94
86

Max

77

76XXE(6)
Min

Typ

80
80
70

94
86
77

Units

Max
dB

en

Input Referred Noise Voltage

Rs= 1000., f= 1kHz

100

100

nV/v'Hz

In

Input Referred Noise Current

RS= 1000., f= 1kHz

0,01

0.01

pAlv'Hz

ISUPPLY

Supply Current
(Per Amplifier)

No Signal, No Load
7642 ONLY
10= 1O,.,A(1) Low Bias
10 = 100,.,A Medium Bias
10 = 1mA(2) High Bias

0,01

0.03

0,01

0.03

0,01
0.1
1.0

0.022
0.25
2.5

0.01
0.1
1.0

0.022
0.25
2.5

120

mA

V01 1V02

Channel Separation

Ay=100

SR

Slew Rate

Ay= 1, CL = 100pF
VIN=8Vp-p
10=10,.,A(1), RL =1Mn
10= 100,.,A, RL = 100kn
10=1mA(2),RL =10kn

0,016
0.16
1.6

0,016
0.16
1.6

VI,.,s

VIN=50mV,CL =100pF
10= 10,.,A(1), RL = 1Mn
10= 100,.,A, RL = 100kn
10= 1mA(2), RL = 10kn

20
2
0.9

20
2
0.9

,.,s

VIN=50mV, CL =100pF
10=10,.,A(1), Ri.. =lMn
10= 100,.,A, RL = 100kn
10= 1mA(2), RL = 10kn

5
10
40

5
10
40

Rise Time

tr

Overshoot Factor

NOTES: 1. Does not apply to 7641.
2. Does not apply to 7642.

120

dB
-'
«U)
:z a:
ow
w:::;;

:5«

%

For Test Conditions:
C = Commercial Temperature Range: o"e to + 70"C
M ~ Military Temperature Range: - 55°C to + 125°C

ELECTRICAL CHARACTERISTICS (7642 ONLy)
(VSUPPLY= ± 1.0V, 10 = 1O,.,A, T A = 25'C, unless otherwise specified.)
Symbol

Parameter

76XXC

Test Conditions
Min

VOS

Input Offset Voltage

Typ

Rs:S:100kn, TA=25'C

Units
Max
10
12

TMIN:S:TA:S:TMAX

mV

I1Vosll1T

Temperature Coefficient of VOS

Rs:S:100kn

20

los

Input Offset Current

TA=25'C
I1TA=C

0.5

30
300

pA

ISlAS

Input Bias Current

TA=25'C
I1TA=C

1.0

50
500

pA

VeMR

Common Mode Voltage Range

±0.6

NOTE: All typical valuss have been characterized but am not tested.

3-519

i=U::
«::::;
a: c..

,.,VI'C

V

ICL76XX
ELECTRICAL CHARACTERISTICS (7642 ONLY)

(Continued)
(VSUPPLY = ± 1.0V, IQ = 10pA, T A = 25°C, unless otherwise specified.)
Symbol

Parameter

76XXC

Test Conditions
Min

VOUT

Output Voltage Swing

RL = 1MO, TA=25°C
~TA=C

AVOL

Large Signal Voltage Gain

Vo= ±0.1V, RL =1MO
TA=25°C

Typ

Units
Max

±0.98
±0.96

V

90
80

dB

Unity Gain Bandwidth

0.044

MHz

RIN

Input Resistance

1012

0

CMRR

Common Mode Rejection Ratio

Rs,;;100kO

80

dB

~TA=C

GBW

PSRR

Power Supply Rejection Ratio

80

dB

en

Input Referred Noise Voltage

Rs= 1000, f= 1kHz

100

nVlv'Hz

in

Input Referred Noise Current

Rs= 1000, f= 1kHz

0.Q1

ISUPPLY

Supply Current
(Per Amplifier)

No Signal, No Load

6

VOllV02

Channel Separation

Av=100

SR

Slew Rate

Av= 1, CL = 100pF
VIN=0.2Vp-p
RL =1MO

tr

Rise Time
Overshoot Factor

NOTE:

C~Commerci.1

pAlv'Hz
15

".A

120

dB

0.016

V/".s

VIN=50mV, CL=100pF
RL =1MO

20

".S

VIN=50mV, CL =100pF
RL=1MO

5

%

Temperature Range (O"C to +70"C)

NOTE: AU typIcs/ values have been characterfzsd but IU8 not tested.

3-520

ICL76XX
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT PER AMPLIFIER
AS A FUNCTION OF FREE·AIR
TEMPERATURE

SUPPLY CURRENT PER AMPLIFIER
AS A FUNCTION OF SUPPLY
VOLTAGE

104

10K

~~~~~!~ c

I- NO SIGNAL
1

~

f-- l-~g~~~L

1.I

,oJ

.

-

10 = 10o,..A

I

I

a~

10 ·'00,..A

I

10

12

14

-so

16

.25

-25

.50

+75

10

/

;;

~

I'--

1

10

/

~

-

10 ",o,..A

I

100

'"~'"

r-- t--

I

102

>

...-

10" lOIlA

Y+·+5VOLTS
Y- .. ..sYOLTS

§

I

:-

1 :,

1000

vl-V-~'0vbLTS

f-'o-lmA

t

10" lmA

.....

lK

INPUT BIAS CURRENT AS A
FUNCTION OF TEMPERATURE

l/

1.0

./

o. 1

-so

+100 +125

SUPPLY VOLTAGE - VOL TS

a

-25

FREE·AIR TEMPERATURE _·c

+25

+50

+75

+100 +125

FREE·AIR TEMPERATURE _·C

0307-13

0307-14

0307-12

~
I

100

Hl -tOOKH

~
o

RL~

la=l00.,.A _

'a=lmA

-

>

:ij::

1

10

~~
PHASE

1

~
1

75

F=
I--

25

0

+25

+50

TA = +25OC

o

~

~
I\.

1
0.1

1

+15 .'00 +125

10

100

I-~I~.'~
:""--.
_

~
10 = lmA

~

lk

~s

90

~"

35

10.: 1180

..

~
~

:!i

10k lOOk 1M

~

I-- ~lmA

90

80

~

8

0307-16

a

-25

+25

+50

+75 +100 +125

FREE·AIR TEMPERATURE _·C

0307-15

POWER SUPPLY REJECTION RATIO
AS A FUNCTION OF FREE·AIR
TEMPERATURE
100

IQ:I,mA
os
go
85

r-- I-

~~....

..... r-....

IQ·'~A

.0

........ .........

75

.......

7.
6S
-75

-SO

-25

--

Vsupp" tOY

0

+25 +50

N

.......

15
70
-75 -50

rREQUENCY - Hz

fREE·AIR TEMPERATURE - C

:""--.
:""--.

-~-

Ul
~ 85

~

w:::;;:
~«

I-- ~A

a: os

0307-17

It

-

+75 "'00 +125

FREE·AIR TEMPERATURE - C

~

600

I

SOO

~

400

lo1i

300

~

200

o
>

.
z

PEAK·TO·PEAK OUTPUT
VOLTAGE AS A FUNCTION
OF FREQUENCY

EQUIVALENT INPUT NOISE
VOLTAGE AS A FUNCTION OF
FREQUENCY

I

w

~.

§"

di~ !

!

!:IIi!il"l:

....
~w:
II::,++-- i i
i

100

,

1.

I

~II!II

\i"!II

>

T,,"+25C
3V " VSUPP c;;, 16V

t--

1K

10K

lOOK

FREaUENCY - Hz

NOTE: AN typical values have bosn characlBJized but at8 not Jested.

3-521

1Isu;·

2

0

•

,BV

"""\

TA .. +2!i""C

I,

1a-1mA
---'0.10....
""".'0.,00 ....

\

I

a-

:'\
,\
.
, I \ '\

I.?~

100

,

Vsupp - ,
,fN
\

..

V"""j'2V r~
o

I

lK

10K

!

~,

..

'- ~~

lOOK

1M

10M

FREOUENCY - Hz

0307-19

0307-18

,.~
~

4

....I

«en
zec

OW

!i§
eco.

Vsuw -10V

III

I 100

'\

T
50

SHI~'

('a = lmA)

T T
VOUT .. 8 VOL T5

105

= 15V

I\. ~

t::::,...

Vsupp = 10VOLTS

6

Vsupp

~= 100pA

t-

HI.. =fAlm

~ ~ I::::::, /IO·'O$1A

Z

~

107

-I

1000

COMMON MODE REJECTION
RATIO AS A FUNCTION OF FREE·AIR
TEMPERATURE

LARGE SIGNAL DIFFERENTIAL
VOLTAGE GAIN AND PHASE SHIFT
AS A FUNCTION OF FREQUENCY

LARGE SIGNAL DIFFERENTIAL
VOLTAGE GAIN AS A FUNCTION
OF FREE·AIR TEMPERATURE

0307-20

ICL76XX
TYPICAL PERFORMANCE CHARACTERISTICS
MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE AS A FUNCTION OF
SUPPLY VOLTAGE

MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE AS A FUNCTION OF
FREQUENCY

>

>

W

"~

I

I

6

6

I!:

"
~
::

~

~

~
~

"
I

~

g

10 '" lmA

>
>-

1.0

"
0
0

z
<

>-

~

-2

INPUT
-4

v

I
10 =tmA.::

1=
~~I~LLLL_,L.O~-LLL_,LO~-LLL~'00

10

12

14

16
LOAD RESISTANCE - K!!

0307-26

0307-25

>
I

w

10 = l00,..A

VSUPf .. lOV

I--+-+-+---+- ~ : ~::!

~g

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

"- f\.

I

r

";!'"
>

i--

~

~
6
Q
II
>-

-2

-6

-6

10

12

0307-28

0307-27

NOTE: AU typIcs/ vaJues Iunr6 besn charscteffzfld but lU8 not t6sted.

3-522

I--

--t
:

r-

'\

,
~;PUT

-+\:

l

.

i

I

I

200

400

600

I

,I

j

800

1000 1200

TIME -SIS

TIME- ..s

T1ME-,IoI1

"\:

/!

/OUTPUT

'

i -.

~

CL .. l00pF
TA'"'+-25C

I

Q

II

VsuPP .. lOV
f\. .. lM!!

10 -tOpA

>

6

>-

\

/oUTPUT

~

10I-tt*+-++±:I=-I-+-l+!--l

~ 'OOjJ~

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

1\

I

+100 +125

0307-23

SUPPLY VOLTAGE - VOLTS

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

6

'7'

MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE AS A FUNCTION OF LOAD
RESISTANCE

I
10

0

16

VsuPP: lOV
= 10K!!
R,
~ l00pF
C,
= +25 C
TA

'SO

121-+f-H-t-+-rtl-t--i-f+i---i

~

IQ"'1mA

-2' 0 '2'

FREE.AIR TEMPERATURE _ DC

v· -v-

0307-24

~

-SO

= IOVOlTS
TA = 25 C

~

14

10'" 1rnA

I

I

"
12

VSUI'P " 10 VOL TS

'0" lOjJA

;;

l/ I

"
X
"" 0
<
" -7'

0307-22

z

10

'6

MAXIMUM OUTPUT SINK CURRENT
AS A FUNCTION OF SUPPLY
VOLTAGE

5~

I

,.

SUPPLVVOLTAGE - VOLTS

0307-21

1/

.........

~

~

j

t--....

~

~

1

RL" 10K!!

......

Rl =2K!!

0

0

1/

r-.....

S

"[;

1

RL" l00KU

'0

>

>

>-

MAXIMUM OUTPUT SOURCE
CURRENT AS A FUNCTION OF
SUPPLY VOLTAGE

'2

W

"~

FREQUENCY _ Hz

MAXIMUM PEAK-TO-PEAK VOLTAGE
AS A FUNCTION OF FREE-AIR
TEMPERATURE

0307-29

DETAILED DESCRIPTION
Static Protection
All devices are static protected by the use of input diodes.
However, strong static fields should be avoided, as it is possible for the strong fields to cause degraded diode junction
characteristics, which may result in increased input leakage
currents.

Latchup Avoidance
Junction-isolated CMOS circuits employ configurations
which produce a parasitic 4-layer (p-n-p-n) structure. The 4layer structure has characteristics similar to an SCR, and
under certain circumstances may be triggered into a low
impedance state resulting in excessive supply current. To
avoid this condition, no voltage greater than 0.3V beyond
the supply rails may be applied to any pin. In general, the
op-amp supplies must be established simultaneously with,
or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to 2mA to
prevent latch up.

Choosing the Proper IQ
Each device in the ICl76XX family has a similar 10 set-up
scheme, which allows the amplifier to be set to nominal
quiescent currents of 1O,...A, 100,...A or 1mA. These current
settings change only very slightly over the entire supply voltage range. The ICl7611/12 have an external 10 control
terminal, permitting user selection of each amplifiers'
quiescent current. (The 7621 and 7641/42 have fixed 10
settings - refer to selector guide for details.) To set the 10 of
programmable versions, connect the 10 terminal as follows:
10= 10,...A-la pin to V+
10 = 1OO,...A -10 pin to ground. If this is not possible, any
voltage from V+ -0.8 to V- +0.8 can be used.
la=lmA-la pin toVNOTE: The output current available is a function of the quiescent current setting. For maximum pop output voltage
swings into low impedance loads, 10 of 1mA should be selected.

Output Stage and Load Driving
Considerations

This allows output swings to almost the supply rails for output loads of 1M.a, 100k.a, and 10k.a, using the output stage
in a highly linear class A mode. In this mode, crossover
distortion is avoided and the voltage gain is maximized.
However, the output stage can also be operated in Class
AS for higher output currents. (See graphs under Typical
Operating Characteristics). During the transition from Class
A to Class S operation, the output transfer characteristic is
non-linear and the voltage gain decreases.

Input Offset Nulling
For those models provided with OFFSET NULLING pins,
nulling may be achieved by connecting a 25K pot between
the OFFSET terminals with the wiper connected to V+. At
quiescent currents of lmA and 100,...A, the nulling range
provided is adequate for all Vos selections; however with
10 = 10,...A, nulling may not be possible with higher values of
Vos·

Frequency Compensation
The ICl76XX are internally compensated, and are stable
for closed loop gains as low as unity with capacitive loads
up to 100pF

IExtended Common Mode Input Range
The ICl7612 incorporates additional processing which allows the input CMVR to exceed each power supply rail by
0.1 volt for applications where Vsupp;;' ± 1.5V. For those
applications where Vsupp:S: ± 1.5V, the input CMVR is limited in the positive direction, but may exceed the negative
supply rail by 0.1 volt in the negative direction (eg. for
Vsupp= ±1.0V, the input CMVR would be +0.6 volts to
-1.1 volts).

OPERATION AT VSUPP=

± 1.0 VOLTS

Operation at Vsupp = ± 1.0V is guaranteed at 10 = 10,...A
for A and S grades only. This applies to those devices with
selectable la, and devices that are set internally to
10 = IOllA (i.e., ICl7611, 7612, 7642).
Output swings to within a few millivolts of the supply rails
are achievable for RL;;' 1M.a. Guaranteed input CMVR is
±0.6V minimum and typically +0.9V to -0.7V at
Vsupp = ± 1.0V. For applications where greater common
mode range is desirable, refer to the description of ICl7612
above.

Each amplifiers' quiescent current flows primarily in the
output stage. This is approximately 70% of the 10 settings.

NOTE: All typ;ca./ valuBs have been characterized but ar8 not tested.

3-523

--'
-I~~-..J\N

V'N
+5

V,N

IM'UT

~

STAGE

'---H--VOL

VOUT
TOCMQSOR

OJ,

LPTTL LOGIC
COMMON

-

1M

0307-34

Figure 7: Averaging AC to DC Converter for A/D
Converters Such as ICL7106, 7107, 7109, 7116,
7117

0307-31
'By using the ICL7612 in these applications, the circuits will follow rail
to rail inputs.

Figure 4: Level Detector'

1.F

+

~

::!~A

":"

TO

SUCCEEDING

+5

+

lOOk

__-,

VOUT

":"

0307-32
-low leakage currents allow Integration times up

to several hours.

Figure 5: Photocurrent Integrator

NOTE: All typical VB/u68 have been characterized but 81'8

no, tested.
3-524

ICL76XX
O.2pF

O.2pF

11--

30k

1601<

0

T~

6801<

%

r-

O.2pF

lOOk

7

1

51.

~
"

r--

360k

INPUT

O.lpF

O.2pF

I

O.l/JF

:

L_-It=_.J

360k

1M

7

1M

:L_-It=_...J:

OUTPUT

The low bias currents permit high resistance and low capacitance values to be used to achieve low frequency cutoff. fc =10Hz, AVCL =4, Passband
ripple=O.ldB

• Note that small capacitors (25 - 50pF) may be needed for stability in some cases.

Figure 8: Fifth Order Chebyshev Multiple Feedback Low Pass Filter

+8V

NOTE 1. For devices with programmable standby current, connect
10 pin 10 V + (10 = 10"" mode).

v'

Figure 9: Burn-In and Life Test Circuit

Figure 10: VOS Null Circuit

NOTE: AU typical valu6s havs been characterized but are noI tested.

3-525

ICL7650S
Super Chopper-Stabilized
Operational Amplifier
GENERAL DESCRIPTION

FEATURES

The ICL7650S Super Chopper-Stabilized Amplifier offers
exceptionally low input offset voltage and is extremely stable with respect to time and temperature. It is a direct replacement for the industry-standard ICL7650 offering
Improved input offset voltage, lower input offset voltage
temperature coefficient, reduced input bias current, and
wider common mode voltage range. All improvements are
highlighted in bold italics in the Electrical Characteristics
section. Critical parameters are guaranteed over the entire commercial, Industrial and military temperature
ranges.
Harris' unique CMOS chopper-stabilized amplifier circuitry
is user-transparent, virtually eliminating the traditional chop·
per amplifier problems of intermodulation effects, chopping
spikes, and overrange lock·up.
The chopper amplifier achieves its low offset by compar·
ing the inverting and non·inverting input voltages in a nulling
amplifier, nulled by alternate clock phases. Two external ca·
pacitors are required to store the correcting potentials on
the two amplifier nulling inputs; these are the only external
components necessary.
The clock oscillator and all the other control circuitry is
entirely self·contained. However the 14-lead version in·
cludes a provision for the use of an external clock, if reo
quired for a particular application. In addition, the ICL7650S
is internally compensated for unity·gain operation.

• Guaranteed Max Input Offset Voltage for All
Temperature Ranges
• Low Long-Term and Temperature Drifts of Input
Offset Voltage
• Guaranteed Max Input Bias Current-10 pA
• Extremely Wide Common Mode Voltage Range+3.5 to -5V
• Reduced Supply Current-2 mA
• Guaranteed Minimum Output Source/Sink Current
• Extremely High Gain-150 dB
• Extremely High CMRR and PSRR-140 dB
• High Slew Rate-2.5V/p.s
• Wide Bandwidth-2 MHz
• Unity-gain Compensated
• Clamp Circuit to Avoid Overload Recovery Problems
and Allow Comparator Use
• Extremely Low Chopping Spikes at Input and Output
• Characterized Fully Over All Temperature Ranges
• Improved. Direct Replacement for Industry-Standard
ICL7650 and other Second-Source Parts

ORDERING INFORMATION
Part

Temperature Range

ICL7650SCPA·1

O·Cto +70·C

Package
8-Pin Plastic

ICL7650SCPD

14·Pin Plastic

ICL7650SCTV·1

8·PinTO·99

ICL7650SIPA-1

- 25·C to + 85·C

8·Pin Plastic

ICL7650SIPD

14-Pin Plastic

ICL7650SIJD

14·Pin CERDIP

ICL7650SITV·1

8·PinTO·99

ICL7650SMJD

- 55·C to + 125·C

ICL7650SMTV·1

14·Pin CERDIP
8·PinTO·99

HARRIS SEMICONDUCTOR'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE
CONDITION OF SALE. THE WARRANTY SHALL BE EXCLUSIVE AND SHAll BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED

WARRANTIeS OF MERCHANTABILITY AND FITNESS FOR A PARTICUlAR USE.

NOTE: AU typicsI values have b8en characterized but IUS not 16S16d.

3-526

File Number . 2920

ICL7650S
ABSOLUTE MAXIMUM RATINGS
Total SupplyYoltage (V+ toY-) .................... 18Y
InputYoltage ................... (Y+ +0.3) to (Y- -0.3)
Yoltage on Oscillator Control Pins .............. y+ to YDuration of Output Short Circuit ................. Indefinite
Current into Any Pin ............................. 10 mA
-while operating (Note 1) ....................... 100 "A
Continuous Total Power Dissipation (TA = 25°C)
CERDIP Package ...............•............ 500 mW
Plastic Package ............................. 375 mW
TO-99 ...................................... 250 mW

Storage Temperature Range ............. -55°C to 150°C
Lead Temperature (Soldering. 10 sec) ............ + 300°C
Operating Temperature Range
ICL7650SC ............................ 0°Cto +70°C
ICL7650SI .......................... -25°C to +85°C
ICL7650SM ........................ - 55°C to + 125°C
NOTE: Stresses above those listed under ''Absolute Maximum Ratings"
may cause permanent damage /0 the devico. These are stress ratings only
and functional operation 01 the device at these or any other conditions

above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
Test Conditions: (Y+ = +5Y, Y- = -5Y, TA = + 25°C, Test Circuit as in Fig. 3 (unless otherwise specified)
Symbol

Parameter

Limits

Test Conditions
Min

Vos

Input Offset Voltage
(Note 2)

Average Temperature
Coefficient of Input Offset
Voltage (Note 2)

±0.7

±5

±1

±8

-25°C,;;: TA';;: +85°C

±2

± 10

«::::;
a: Co

±4

±20

l5«

0.02
0.02
0.03

0.1

O°C,;;: TA ,;;: +70°C
-25°C,;;: TA';;: +85°C
-55°C,;;: TA';;: + 125°C

b.Yoslb.t

Change in Input
Offset with Time

Iblas

Input Bias Current
11(+)1.11(-)1

los

Input Offset Current
11(-)-1(+)1

TA = 25°C
O°C,;;: TA';;: +70°C

20

+85°C';;: TA';;: +125°C

100

TA = 25°C

8

10
20
20

O°C,;;: TA ,;;: +70°C

+85°C ,;;: TA ,;;: + 125°C

A VOL

Large Signal Voltage Gain
(Note 2)

RL =10 kO,Yo= ±4Y,TA = 25°C
O°C';;: TA';;: +70°C
-55;C,;;: TA';;: +125°C

Output Yoltage Swing
(Note 3)

20

1012

-25°C,;;: TA';;: +85°C

Your

20
50
50
500
20
40
40
40
50

20

-55°C,;;: TA';;: +85°C
Input Resistance

10

5

-55°C';;: TA ,;;: +85°C

RL = 10kO
RL=100kO

NOTE: All typicaJ values baWl been charact6rized but are not tested.

3-527

135

",y

pA

pA

0

150

130
130

dB

120
±4.7

±4.85
±4.95

«en
:z a:
ow
i=Li:

w::;;

nVl~month

4

-25°C,;;: TA ,;;: +85°C

....I

",VloC

100

-25°C,;;: TA ,;;: +85°C

RIN

Units
Max

O°C,;;: TA';;: +70°C

TA = +25°C

-55°C,;;: TA';;: +125°C

b.Voslb.T

Typ

Y

ICL7650S
ELECTRICAL CHARACTERISTICS (Continued)
Test Conditions: (V+ = +5V, V- = -5V, TA = +25'C, Test Circuit as in Fig. 3 (unless otherwise specified)
Symbol

CMVR

CMRR

Parameter

Limits

Test Conditions

Common Mode Voltage Range

TA = 25'C

(Note 2)

s: TA s:
-25'C s: TA s:
-55'C s: TA s:
O'C

Min

Typ

-5

-5.2 to +4

-5

+3.5

+85'C

-5

+3.5

-5

+ 125'C

Common Mode Rejection Ratio

CMVR= -5Vto +3.5V,TA=25'C

120

(Note 2)

s: TA s:
s: TA s:
-55'C s: TA s:
O'C

+70'C

120

25'C

+85'C

115

+125'C

110

Power Supply Rejection Ratio

V+, V- = ±3Vto ±8V

120

en

Input Noise Voltage

RS = 1000, f = OCto 10 Hz

in

Input Noise Current

f = 10 Hz

GBW

Gain Bandwidth Product

SR

Slew Rate

dB

140

dB

2

p.Vp·p

0,01

pM/Hz
MHz
Vlp.s

Rise Time

0.2

p.s

Overshoot

20

Operating Supply Range

Isupp

CL = 50 pF, RL = 10 kO

Output Source Current

2

No Load, T A = 25'C
O'C

+70'C

3.2

+85'C

3.5

+125'C

O'C

+70'C

2.3

-25'C

+85'C

2.2

+125'C

4.5
mA

2
25

TA = 25'C

s: TA s:
-25'C s: TA s:
-55'C s: TA s:

+70'C

20

+85'C

19

+125'C

30
mA

17

Internal Chopping Frequency

Pins 12 & 14 Open

120

250

Clamp ON Current (Note 4)

RL = 100 kO, TA = 25'C

25

70

Clamp OFF Current

-4V

(Note 4)

s:

You! s: +4V, TA =
s: TA s: +70'C
-25'C s: TA s: +85'C
-55'C s: TA s: +125'C

mA

4
2.9

TA = 25'C

O'C

V

3

-25'C

s: TA s:
s: TA s:
-55'C s: TA s:
Output Sink Current

%
16

4.5

s: TA s:
s: TA s:
-55'C s: TA s:

fch

+3.5
140

2.5

Supply Current

10 sink

V

2

V+ toV-

10 source

+3.5.

+70'C

PSRR

tr

Units
Max

25'C

0.001

O'C

375

Hz
p.A

5
10

nA

10
15

NOTE 1: Limiting input current to 100 /lA is recommended to avoid latchup problems. Typically 1 mA is safe, however this is not guaranteed.
2: These parameters are guaranteed by design and characterization, but not tested at temperature extremes because thermocouple effects prevent precise
measurement of these voltages in automatic test equipment

3: OUTPUT CLAMP not connected. See typical characteristic curves for output swing vs. clamp current characteristics.
4: See OUTPUT CLAMP under detailed description.

5: All significant improvements over the industry-standard ICL7650 are highlighted in bold Italics.

NOTE: AJlIypicaI values have bs8n charscl8rized but are not tested.

3-528

ICL7650S

~:8r

EXT'CLKIN

osc.

:

CUCOUT

C

~;P

.IN
OUTPIn

- I.

CLAMP

T

~EXTCl.KIN

~ •• CL'OUT
~i

...r-L..-r-.
~C

-'

0089-1

< en

za:
ow

Figure 1: Functional Diagram

i=Li:

<:::;
a: 11.
w::;;

CEXTA

CEXTS

CEXTS

INT/EXT

CEXTA

+IN

Y+/CASE NC(GUARD)
-IN
OUTPUT
+IN

Y-

CRETN

-IN

l5<

EXT ClK IN
INT ClK OUT
Y+
OUTPUT

NC(GUARD)
Y-

OUTPUT CLAMP
CRETN

14- PIN DIP
(PD. JD)

8- PIN DIP
(PA - 1)

8 lEAD TO 99

(TV-1)

Figure 2: Pin Configurations

NOTE: AIIIypk;aI values have been characteriz8d but arB not testsd.

3-529

0089-2

ICL7650S
TYPICAL PERFORMANCE .CHARACTERISTICS
Supply Current
vs. Supply Voltage

Supply Current
vs. Ambient Temperature

Maximum Output Current
vs. Supply Voltage

1

I --

..!iii

-

r- t-- l-

5

12

14

-50 -25

16

0

25

50

75 100 125

AMBIENT TEMPERATURE-CC

TOTAL SUPPLY VOLTAGE-VOLTS

I-

~

.,/

"5
...

-+- ....- -

0

0

o
10

a:
a:
u

I

o
4

r-

I

v

•
•~"
•

-10 I--

-20

--

r--....

-30
2

0089-4

0089-3

r----- ;;;:::::
4

10

I

--

-

12

TOTAL SUPPLY VOLTAGE -

I-

14

11

VOLTS

0089-5

Common-Mode Input Voltage
Range vs. Supply Voltage

~i

L

~!

..Be.
!i

~
~'"

~<,..

#?r-

1OO

\

~~

V~r-t--

/

10Hz P-P Noise Voltage vs.
Chopping Frequency

Clock Ripple Referred to the
Input vs. Temperature

.. ::!

:2:

'/

BROADINIDr-J
1D """,NOISE
CAy - 1000)

--

~=:.

012345678

gS

! :

21

0089-6

....

I

I

0.1

G!Ii

-EACH SUPPLY VOLTAGE(+AHD-)

\

====

_._-

.. I

t:
iii:

o

,~

50

75

100

125

150

to

TEMPERATURE - ·C

J

tao

tk

'Ok

CHOPPING FREQUENCY (CLOCK-OU1) lIZ

0089-7

0089-8

Input Offset Voltage Change
vs; Supply Voltage

Output with Zero Input;
Gain = 1000; Balanced Source
Impedance = 10 kn

Input Offset Voltage
- vs. Chopping Frequency

":. +. Hf-t-HlfHl-+1-tt

ti ..
!i 0
.
gao

...

III

!I +8 Hf-t-HlfHl-+1-tt
!:i
g

5i +4
t

o

~~HHHr~~

+2

I-f-t-HlfHl-+1-tt

1214517

••

nME·ma
10

12

14

II

TOTAL SUPPLY VOLTAGE - VOLTS

tk

tOk

c..-G FREQUENCY (CLOCK-OUl) lIZ

0089-9

0089-10

NOTE: All typical values havs been character/z8d but am not tested.

3-530

0089-11

Dell. 8'6505
TYPICAL PERFORMANCE CHARACTERISTICS

(Continued)

Open Loop Gain and Phase Shift
vs. Frequency

Open Loop Gain and Phase Shift
vs. Frequency
leo

leo

,,

--

""-"" ---

&0

RL. = 10k.{\.
QOjbF

cay

10

0.01 0.1

1011

III

~...

co

...

c:J

CI

oat:

,.

i

UO§
1""-

~

120

;::

10m
f.~

..:a

,

0

a:

'-

I"

fa

1(0

lCO

III

~

--

./

a

lID ~

J'-,

1""-

40 I-RL = 10k.{\.

Cer

f'
0.01

lk 10k lCOk

c:

10mc

"I-- co!;;

"-

co

0

l:of

&OfiI
OJ

v" r\

Qll,O~r

1k

10k lCOk

FREQUENCY liz

FRI!QUI!NCY liz

0089-13

0089-12

Voltage Follower Large Signal
Pulse Response'

Voltage Follower Large Signal
Pulse Response'

I!
...

+2

§!

+1

III

c:J

~
§!

0

-

CLOCK OUT
LOW
'"lIlo

V

~

~

o

~

0

.......
0

>

I

CLOCK OUT /7 \
HIGH

1--1-.
=> -1

2

CLOCK OUT
LOW

~

1\\

=> -2

0

0.6
1.6
TIME·,S

~§

a:

"-

o

2.5

J
f1

0.5
1
TIME ·.S

1.5

2

0089-14

0089-15

'THE TWO DIFFERENT RESPONSES CORRESPOND TO THE TWO PHASES OF THE CLOCK.

P-Channel Clamp Current
VS. Output Voltage

N-Channel Clamp Current
vs. Output Voltage
1011,.A

..

...
z
WW
za:
~!!i
:.:U
qA.
z~
U

~

1011,.A

1I!,.A

1/

1O,.A

1,.A
IDOnA

u:i
za:

7

1,.A

IDOnA

z=>

10nA

CU 1 _

:':A.

:t~

InA

InA

U l00pA

l00pA
10pA

10pA 7

lpA
+0.8

+0.1

+004

+0.2

lpA

o

-0.8

OUTPUT YOLTAGE IlY-

-0.8

-0.4

-0.2

o

OUTPUTYOLTAGE IlY+
0089-16

0089-17

NOTE: All typical values have been characterized but are not tested.

3-531

D..

w::;;;
~«

\

=:- +1
w

c:J

II

-2

+2

-'
«en
za:

OW

I

0

CLOCK OUT
HIGH

J

.. -I

~

!J,

f

I"
11111

10

0.1

1:10

ICL7650S
Output Clamp
The OUTPUT CLAMP pin allows reduction of the overload recovery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or summing junction, a current path between this point and the OUTPUT pin
occurs just before the device output saturates. Thus uncontrolled input differential inputs are avoided, together with the
consequent charge build-up on the correction-storage capacitors. The output swing is slightly reduced.

OUTPUT

Clock
0089-18

The ICl7650S has an internal oscillator, giving a chopping frequency of 200 Hz, available at the CLOCK OUT pin
on the 14-pin devices. Provision has also been made for the
use of an external clock in these parts. The INT/EXT pin
has an internal pull-up and may be left open for normal operation, but to utilize an external clock this pin must be tied
to V- to disable the internal clock. The external clock signal
may then be applied to the EXT CLOCK IN pin. An internal
divide-by-two provides the desired 50% input switching duty
cycle. Since the capacitors are charged only when EXT
CLOCK IN is high, a 50%-80% positive duty cycle is recommended, especially for higher frequencies. The external
clock can swing between V+ and V-. The logic threshold
will be at about 2.5V below V+. Note also that a signal of
about 400 Hz, with a 70% duty cycle, will be present at the
EXT CLOCK IN pin with INT/EXT high or open. This is the
internal clock signal before being fed to the divider.
In those applications where a strobe signal is available,
an alternate approach to avoid capacitor misbalancing during overload can be used. If a strobe signal is connected to
EXT ClK IN so that it is low during the time that the overload signal is applied to the amplifier, neither capacitor will
be charged. Since the leakage at the capacitor pins is quite
low at room temperature, the typical amplifier will drift less
than 10 fJ-V/sec, and relatively long measurements can be
made with little change in offset.

Figure 3: ICL7650S Test Circuit

DETAILED DESCRIPTION
Amplifier
The functional diagram shows the major elements of the
ICl7650S. There are two amplifiers, the main amplifier, and
the nulling amplifier. Both have offset-null capability. The
main amplifier is connected continuously from the input to
the output, while the nulling amplifier, under the control of
the chopping oscillator and clock circuit, alternately nulls
itself and the main amplifier. The nulling connections, which
are MOSFET gates, are inherently high impedance, and two
external capacitors provide the required storage of the nUlling potentials and the necessary nulling-loop time constants. The nulling arrangement operates over the full common-mode and power-supply ranges, and is also independent of the output level, thus giving exceptionally high
CMRR, PSRR, and AVOL.
Careful balancing of the input switches, and the inherent
balance of the input circuit, minimizes chopper frequency
charge injection at the input terminals, and also the feedforward-type injection into the compensation capacitor, which
is the main cause of output spikes in this type of circuit.

Intermodulation

BRIEF APPLICATION NOTES
Component Selection

Previous chopper-stabilized amplifiers have suffered from
intermodulation effects between the chopper frequency and
input signals. These arise because the finite AC gain of the
amplifier necessitates a small AC signal at the input. This is
seen by the zeroing circuit as an error signal, which is
chopped and fed back, thus injecting sum and difference
frequencies and causing disturbances to the gain and
phase vs. frequency characteristics near the chopping frequency. These effects are substantially reduced in the
ICl7650S by feeding the nulling circuit with a dynamic current, corresponding to the compensation capacitor current,
in such a way as to cancel that portion of the input signal
due to finite AC gain. Since that is the major error contribution to the ICl7650S, the intermodulation and gain/phase
disturbances are held to very low values, and can generally
be ignored.

The two required capacitors, CEXTA and CEXTB, have optimum values depending on the clock or chopping frequency. For the preset internal clock, the correct value is 0.1 fJ-F,
and to maintain the same relationship between the chopping frequency and the nulling time constant this value
should be scaled approximately in proportion if an external
clock is used. A high-quality film-type capacitor such as mylar is preferred, although a ceramic or other lower-grade
capacitor may prove suitable in many applications. For
quickest setting on initial turn-on, low dielectric absorption
capacitors (such as polypropylene) should be used. With
ceramic capacitors, several seconds may be required to
settle to 1 fJ-v.

Capacitor Connection

Static Protection

The null/storage capacitors should be connected ~(. the
CEXTA and CEXTB pins, with a common connection to the
CRETN pin. This connection should be made directly by either a separate wire or PC trace to avoid injecting load current IR drops into the capacitive circuitry. The outside foil,
where available, should be connected to CRETN.

All device pins are static-protected by the use of input
diodes. However, strong static fields and discharges should
be avoided, as they can cause degraded diode junction
characteristics, which may result in increased input-leakage
currents.

NOTE: AD typical values have been chsrscIrHizsd but aM not t6stBd.

3-532

ICL7650S
Rl
R2
INPUT-'I/I/Ir-....----Wlr--.

EXTERNAL
CAPACITORS

R2

OUTPUT

OUTPUT

OUTPUT

OU1PUT~~70
CRETN,.«i 4

/
Inverting Amplifier

Follower

NOTE:

~ ~Hp~~i~~: F~:
Rl

+ R2

OPTIMUM GUARDING

Non-Inverting Amplifier
Figure 4: Connection of Input Guards

~2
~

~l'
~

GAURD
BOTTOM VIEW

BOARD LAYOUT FOR INPUT
GUARDING WITH 10-99
PACKAGE'
00B9-19

realize the extremely low offset voltages that the chopper
amplifier can provide, it is essential to take special precautions to avoid temperature gradients. All components
should be enclosed to eliminate air movement, especially
that caused by power-dissipating elements in the system.
Low thermoelectric-efficient connections should be used
where possible and power supply voltages and power dissipation should be kept to a minimum. High-impedance loads
are preferable, and good separation from surrounding heatdissipating elements is advisable.

Latchup Avoidance
Junction-isolated CMOS circuits inherently include a parasitic 4-layer (p-n-p-n) structure which has characteristics
similar to an SCR. Under certain circumstances this junction
may be triggered into a low-impedance state, resulting in
excessive supply current. To avoid this condition, no voltage greater than 0.3V beyond the supply rails should be
applied to any pin. In general, the amplifier supplies must be
established either at the same time or before any input signals are applied. If this is not possible, the drive circuits
must limit input current flow to under 1 mA to avoid latchup,
even under fault conditions.

Guarding
Extra care must be taken in the assembly of printed circuit boards to take full advantage of the low input currents
of the ICL7650S. Boards must be thoroughly cleaned with
TCE or alcohol and blown dry with compressed air. After
cleaning, the boards should be coated with epoxy or silicone rubber to prevent contamination.
Even with properly cleaned and coated boards, leakage
currents may cause trouble, particularly since the input pins
are adjacent to pins that are at supply potentials. This leakage can be significantly reduced by using guarding to lower
the voltage difference between the inputs and adjacent
metal runs. Input guarding of the 8-lead TO-99 package is
accomplished by using a 10-lead pin circle, with the leads of
the device formed so that the holes adjacent to the inputs
are empty when it is inserted in the board. The guard, which
is a conductive ring surrounding the inputs, is connected to
a low impedance point that is at approximately the same
voltage as the inputs. Leakage currents from high-voltage
pins are then absorbed by the guard.
The pin configuration of the 14-pin dual in-line package is
designed to facilitate guarding, since the pins adjacent to
the inputs are not used (this is different from the standard
741 and 101 A pin configuration, but corresponds to that of
the LM108).

Output Stage/Load Driving
The output circuit is a high-impedance type (approximately 18 kn), and therefore with loads less than this value, the
chopper amplifier behaves in some ways like a transconductance amplifier whose open-loop gain is proportional to
load resistance. For example, the open-loop gain will be
17 dB lower with a 1 kn load than with a 10 kn load. If the
amplifier is used strictly for DC, this lower gain is of little
consequence, since the DC gain is typically greater than
120 dB even with a 1 kn load. However, for wideband applications, the best frequency response will be achieved with a
load resistor of 10 kn or higher. This will result in a smooth
6 dB/octave response from 0.1 Hz to 2 MHz, with phase
shifts of less than 10· in the transition region where the
main amplifier takes over from the null amplifier.

Thermo-Electric Effects
The ultimate limitations to ultra-high precision DC amplifiers are the thermo-electric or Peltier effects arising in thermocouple junctions of dissimilar metals, alloys, silicon, etc.
Unless all junctions are at the same temperature, thermoelectric voltages typically around 0.1 p.Vrc, but up to tens
of p.V
for some materials, will be generated. In order to

rc

NOTE: AI/ typical values have been characterized but ar9 not test8d.

3-533

-'

..JV\I\,-+...
OUTPUT

(A,IIA2l ;:, 100 kn
FOA FULL CLAMP EFFECT

0089-2'

Figure 6: Inverting Amplifier
With (Optional) Clamp
NOTE: R,/R2 indicates the parallel combination of A, and A2

Figure a shows the use of the clamp circuit to advantage
in a zero-offset comparator. The usual problems in using a
chopper stabilized amplifier in this application are avoided,
since the clamp circuit forces the inverting input to follow
the input signal. The threshold input must tolerate the output clamp current::::: VIN/R without disturbing other portions
of the system.

TYPICAL APPLICATIONS
Clearly the applications of the ICL7650S will mirror those
of other op amps. Anywhere that the performance of a circuit can be significantly improved by a reduction of input-offset voltage and bias current, the ICL7650S is the logical
choice. Basic non-inverting and inverting amplifier circuits
are shown in Figures 5 and 6. Both circuits can use the
output clamping circuit to enhance the overload recovery
performance. The only limitations on the replacement of
other op amps by the ICL7650S are the supply voltage
(±aV max.) and the output drive capability (10 kO load for
full swing). Even these limitations can be overcome using a
simple booster circuit, as shown in Figure 7, to enable the
full output capabilities of the LM741 (or any other standard
device) to be combined with the input capabilities of the
ICL7650S. The pair form a composite device, so loop gain
stability, when the feedback network is added, should be
watched carefully.

OUT

0089-22

Figure 7: Using 741 to Boost
Output Drive Capacity

VOUT

INPUT
OUTPUT
CLAMP

R

'---t-'IM'-< VTH
200 kJl - 2 MJl

0089-23

Figure 8: Low Offset Comparator
R3 + (R,IIR21 ;:, 100 kG
FOR FULL CLAMP EFFECT

Normal logarithmic amplifiers are limited in dynamiC range
in the voltage-input mode by their input-offset voltage. The
built-in temperature compensation and convenience features of the ICLa04a can be extended to a voltage-input
dynamic range of close to 6 decades by using the ICL7650S
to offset-null the ICL8048, as shown in Figure 9. The same
concept can also be used with such devices as the HA2500
or HA2600 families of op amps to add very low offset voltage capability to their very high slew rates and bandwidths.
Note that these circuits will also have their DC gains,
CMRR, and PSRR enhanced.

0089-20

Figure 5: Non Inverting Amplifier
With Optional Clamp
NOTE: R,/R2 indicates the parallel combination of A, and A2

NOTE; All typical values hsVII been characterized but are not testBd.

3-534

ICL7650S

> .....-o...... VOUT

600 k.Q

R2 15.9 k.Q

(LOW T.C.)

10 k.Q

0089-24

Figure 9: ICL8048 Offset Nulled by ICL7650S
...J

FOR FURTHER APPLICATIONS ASSISTANCE, SEE A053 AND R017

---1--1

6V+
5

CURRENT
CONTROL

COMPARATOR

v·
FIGURE 1. BLOCK DIAGRAM OF CA3098 PROGRAMMABLE SCHMITT TRIGGER
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyrighl © Harris Corporalion 1991

4-8

File Number

896.1

CA3098

ELECTRICAL CIiARACTERISTICS at T A = 25°C Unless Otherwise Specified
CHARACTERISTIC

TEST CONDITIONS

Fig.
No.

Min.

LIMITS
Typ. Max.

UNITS

Input Offset Voltage:
"Low" Ref., VIO(LR)

VLR = Gnd, VHR = 3 V
ISIAS= 100f..lA

5

-15 -3

"High" Rei., VIO(HR)

VHR = Gnd, VLR = -3 V
ISlAS = 100 f..IA

6

-10

±10

10

-55°C to + 125 °c
-55°C to + 125 °c

7
8

-

4.5
±8.2

-

VREG=6V,V+=12V
IBIAS= lOOf..lA

9

-

3

20

-55°C to + 125°C

10

-

6.7

-

-

0.72

1.2

Temp. Coell:
"Low" Rei.
"High" Rei.
Min. Hysteresis
Voltage VIO(HR.LR):
Temp. Coeff.
Output Saturation Voltage,
VCE(SAT)

VI=4V,VREG=6V,
11,12
V+= 12V, IBIAS=lOOf..lA

6

-

mV

f..IV;"C

mV
f..IV;"C
V
E IN >0
S;;;>E IN >4

2
3
2

12

EIN>S
S;;;>E IN >4
4;;;>E IN >0

12

o
U)

0::

Fig. 4 - Resultant output states of the CA3098, shown in
Fig. 3 as a function of various input signal levels.

Fig. 3 - Basic hysteresis switch (Schmitt trigger).

j

:;;

o

o
TYPICAL CHARACTERISTIC CURVES
~ -5 AMBIENT TEMPERATURE ITA '-2'·C
E
SUPPLY vOLTAGE t v+ I -12 V
"HIGH" REFERENCE VOLTAGE IVHR'·6V
~ -4 "LOW· REFERENCE VOLTAGE IYLR'·6V
0:
VIOILRI=VI-VLR

~

.-b

.£

i

V

i!I
-3

~MuB~~~; ~~~::;:~~~~ ~~~ ~.2!i·C

!:4

~

"HIGH" REFERENCE VOLTAGE (VHR'.6V
"LOW' REFERENCE VOLTAGE (VLR'.OV

~

1

v

~ .. ~

g

v

+----j,....\-l-I--l---l-W-l

±3 VIOIHR1:VI-VHR

\5

..
'"
~

/

"'-,

/

~
~

...

. ..

~
..

100
10
PROGRAMMING BIAS CURRENT IrBIASI-I'A

68

.,.

0

r
1000

I
I

. , .,

100

10

1000

PROGRAUNING BIAS CURRENT IIBIAS'-I'A

Fig. 5 -Input-offset voltage ("low" reference) vs. programming bias
current.

Fig. 6 - Input-offset voltage ("high" reference) vs. programming
bias current.
PROGRAMMING BLAS CURRENT IIBIAS'-LOO,.A
VIOIHRI-Vr-VHR

~

•

,

'"

II!

~

25

50

75

100

o
-15

125

AMBIENT TEMPERATURE (TAI-"e

-so

-25

25

50

75

100

125

J!oMBIENT TEMPERATURE ITAJ--C

Fig. 8 - Input-offset voltage ("high" reference) vs. ambient
temperature.

Fig. 7 - fnput-offset voltage ("fow" reference) vs. ambient
temperature.

4-11

CA3098
TYPICAL CHARACTERISTIC CURVES (Cont'd)
~

4

~~

,

~

2

AMBIENT TEMPERATURE ITA 1-25-C
SUPPLY VOLTAGE Cv. J K 12 V
"LOW· REFERENCE VOLTAGE {VLR1.6V

/i

~

~

~

~

I

"HIGH" REFERENCE VOLTAGE (VHR)'6V

'--"

I

"1 ,;

!

;

I

,

. ,.

'++

./

I

Z
i

,

. ,.

10

,

..
,

100

PROGRAMMING BIAS CURRENT {IBrAsJ-~A

-100

1000

-75

-50

25

-25

50

75

(10

125

AMBIENT TEMPERATURE ITAI-"C

Fig. 9 - Min. hysteresis voltage vs. programming bias current.

Fig. 10 - Min. hysteresis voltage vs. ambient temperature.
SUPPLY VOLTAGE IV+}=IOV

~

PROGRAMMING BIAS CURRENT IISIAS 1= IOO,..A

I

10

a

6

100

11>00

-100

-75

Fig. 11 - Output saturation voltage vs. output sink current.

1

50

75

100

125

Fig. 12 - Output saturation voltage vs. ambient temperature.

!

BIASCURRENTlIBIAS)-,..A

-75

-50

-25

0

25

50

75

100

AMBIENT TEMPERATURE (T A )- ore

125

Fig. 14 - Total supply current vs. ambient temperature.

Fig. 13 - Total supply current vs. programming bias current.

"
rio
a+--+-+-+-

Jl... '
is
~

a

::/
1D

~

"

25

·25

AMBIENT TEMPERATURE ITAI-"C

OUTPUT SINK CURRENT (ILOAOI-mA

PROGRAMMING

-50

..:::.:

01

Fig. 15 - Input bias current vs. programming bias current.

4-12

CA3098
TEST CIRCUITS

lion

HYSTERESIS VOLTAGE-VI "OFF"-V£'ON"

Fig. 16 - Input-offset voltage test circuit.

Fig. 17 - Min. hysteresis voltage, total supply current,
and input-bias-current test circuit.

en

a:

~

::;:

Fig. 18 - Switching time test circuit.

TYPICAL APPLI.CATIONS
+6V

Fig. 19 - Time delay circuit: Terminal 3 "sinks" after

Fig. 20 - Time delay circuit: "sink" current interrupted

T seconds.

after T seconds.
+6V

SINE

WAVErU--~~'--'

SQUARE-

WAVE

INPUT

OUTPUT

-6

v

Fig. 21 - Sine-wave to square-wave converter with duty-cycle
adjustment (V, and V.).

4-13

o
o

CA3098
TYPICAL APPLICATIONS (Cont'd)

::2~======t-;
I3
l---f---------L-

Notes (a) Motor pump is "ON" when water level rises above
thermistor TH 2 .

_

WATER
LEVEL

Fig. 22(b) - Water level diagram for circuit of Fig. 22(a).

(b) Motor pump remains "ON" until water level falls

below thermistor TH"
(e) Thermistors, operate in self-heating mode.

Fig. 22(a) - Water-level control.

+ 6V

.3
IOOKll
INPUT PULSE MUST

120n
60,,-

BE GREATER THAN
I ms BUT LESS
THAN DESIRED tON

RI

IOOKQ

SENSOR

••

OOKlll

R2

or

VALUE
CI (pr)

[DOKn

001
01
0.2
-6V

Fig. 24 - One· shot multivibrator.

Fig. 23 - OFF/ON control of triac with programmable hysteresis.

58

Dimensions in parentheses are in millimeters and are derived from
the basic inch dimensions as indicated. Grid graduations are in
mils (10- 3 inch).

o_lIiilil_ _1IiI
IJoo
..- - - - - - 63 (1.600) - - - - - I

The layout represents a chip when it is part of the wafer. When the
wafer is cut into chips, the cleavage angles are 57° instead of 90°
with respect to the face of the chip. Therefore, the isolated chip is
actually 7 mils (0.17 mm) larger in both dimensions.

Dimensions and pad layout for the CA3098H.

4-14

CA3290A
CA3290

mtHARRIS

BiMOS Dual Voltage Comparator
With MOSFET Input, Bipolar Output

August 1991

Features

Description

• MOSFET Input Stage
~ Very High Input Impedance (ZIN) •••••• 1.7TO (Typ)

The CA3290A and CA3290 types consist of a dual voltage
comparator on a single monolithic chip. The common mode
input voltage range includes ground even when operated
from a single supply. The low supply current drain makes
these comparators suitable for battery operation; their
extremely low input currents allow their use in applications
that employ sensors with extremely high source impedances.
Package options are shown in the table below.

v+ = +sv .... a.SpA (Typ)

~

Very Low Input Current @

~

Wide Common Mode Input Voltage Range (VICR) can be Swung 1.SV (Typ) Below Negative Supply Voltage Rail

~

Virtually Eliminates Errors Due to Flow of Input
Currents

• Output Voltage Compatible with TTL, DTL, ECL, MOS,
and CMOS Logic Systems in Most Applications

Selection Chart
CHARACTERISTIC

Applications
• High Source Impedance Voltage Comparators
• Long Time Delay Circuits

PACKAGE AND SUFFIX
TO-S

MAX MAX
MIN
II
VIO
SELECTION (mV) (pA) AOL

V+
(V)

PLASTIC

OIL- 814-STO CAN LEAD LEAD

• Square Wave Generators

CA3290A

10

40

25K

36

T

S

E

E1

• AID Converters

CA3290

20

50

25K

36

T

S

E

E1

• Window Comparators

The CA3290 is also available in chip form (H suffix)

Pinouts

Basic CA3290 Comparator

CA3290A, CA3290
TOP VIEW
OUTPUT
(A')

1

INV. INPUT
(A')
NON· INY. INPUT
(A')

V·

v+

,.....~~-,

2

7

3

6

4

5

OUTPUT
(A2)
INY. INPUT
(A2)
NON· INY. INPUT
(A2)

vp-o-.......----,

TOP VIEW
INV.INPUT

1

NC"

2

NC'

(A')

NON· INY. INPUT
(AI)

OUTPUT
(A')

FIGURE 1.

OUTPUT
(A2)

NON· INY. INPUT
(A2)
.NV.INPUT
(A2)

6

7

• Tie to GNO or V+ for besllnpuVOulput isolation
TOP VIEW

V+ lAB

INV.

IN~.~ 2

6 INY. INPUT
(A2)

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

4-15

File Number

1049.1

CA3290A, CA3290
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY VOLTAGE:
Single Supply:
CA3290A, CA3290
Dual Supply:
CA3290A, CA3290
DIFFERENTIAL INPUT VOLTAGE

+36 V
. . . _ . . ±18 V
± 36 Vor ± [(V+-V-I+5 VI
(whichever is less)
V++5 Vto V--5 V

COMMON-MODE INPUT VOLTAGE
DEVICE DISSIPATION:
Upto550C
Above 55°C
OUTPUT-TO-V- SHORT CIRCUIT DURATION'
TEMPERATURE RANGE, ALL TYPES:
Operating
Storage
INPUT TERMINAL CURRENT
LEAD TEMPERATURE (DURING SOLDERINGI:
AT DISTANCE 1/16 ± 1/32 INCH (1.59 ±0.79 MMI
FROM CASE FOR 10 SECONDS MAX.

630mW
Derate linearly at 6.67 mWfDC
CONTINUOUS
-55 to +1250 C

-65 to +150 o C
1 mA

*Short circuits from the output to V+ can cause excessive heating and
eventual destruction of the device.

I
I ~gMPARATOR
NO 0

01

00

Fig. 2 - Schematic diagram of CA3290
(only one is shown).

CIRCUIT DESCRIPTION

The Basic Comparator
Fig. 1 shows the basic circuit diagram for
one of the two comparators in the CA3290.
It is generically similar to the industry-type
"139" comparators, with PMOS transistors
replacing p-n-p transistors as input stage
elements. Transistors 01 through 04 comprise the differential input stage, with 05
and 06 serving as a mirror-connected active
load and differential-to-single-ended converter_ The differential input at 01 and 04 is
amplified so as to toggle 06 in accordance
with the input-signal polarity. For example,
if +VIN is greater than -VIN, 01, 02, and
current mirror transistors 05 and 06 will be
turned off; transistors 03, 04, and 07 will
be turned on, causing 08 to beturned off.

The output is pulled positive when a load
resistor is connected between the output and
V+.
In essence, 01 and 04 function as sourcefollowers to drive 02 and 03, respectively,
with zener diodes D1 through D4 providing
gate-oxide protection against input voltage
transients (e_g., static electricity). The current flow in 01 and 02 is established at
approximately 50 microamperes by constantcurrent sources 11 and 13, respectively. Since
01 and 04 are operated with a constant current load, their gate-to-source voltage drops
will be effectively constant as long as the
input voltages are within the common-mode
range_

4-16

CA3290A, CA3290

The detailed schematic diagram for one com·
parator and the common current·source
biasi ng is shown in .Fig. 2. PMOS transistors
Q9 through 012 are the current·source
elements identified in Fig. 1 as 11 through 14,
respectively. Their gate·source potentials
(VGS) are supplied by a common bus from
the biasing circuit shown in the right·hand
portion of the Fig. 2. The currents supplied
by 010 and 012 are twice those supplied by
Q9 and 011. The transistor geometries are
appropriately scaled to provide the requisite
currents with common VGS applied to Q9
through 012.

As a result, the input offset voltage (VGSIO" +
VBEI02.-VBEI03.-VGSIO•• ) will not be degraded
when a large differential dc voltage is applied
to the device for extended periods of time at
high temperatures.
Additional voltage gain following the first
stage is provided by transistors 07 and OB.
The collector of OB is open, offering the user
a wide variety of options in applications. An
additional discrete transistor can be added if
it becomes necessary to boost the output
sink-current capability.

ELECTRICAL CHARACTERISTICS at TA = -55 to +125 0 C
CHARACTERISTIC

TEST
CONDITIONS
V+
VCM=I.4 V 5V
Vo=1.4 V
VCM-O V,
±15 V
VO=O V

Input Offset
Voltage, Via

4.5

-

B.5

B.5

-

B.5

B

-

B

-

/1VPC

2
7

2B
2B

2
7

32
32

nA

2.B
13

45

2.B

55

±15 V

45

13

55

5V

0.B5

1 0.B5

1.6

30V

1.62

3

1.62

3.5

150

-

150

-

Temp. Coefficient
of Input Offset
Voltage,lWIO/Ll.T
Input Offset

VCM=I.4 V

Current, 110
Input Current, 11&
Supply Current, 1+

VCM=O V
VCM=I.4 V

.

VCM=O V

RL =

00

5V
±15 V
5V

Voltage Gain, AOL

RL=15kn ±15 V

Saturation

V+=5 V,
+VI=O V,
-VI=l V

Voltage
ISINK = 4 mA
Output Leakage
Current, IOL

VALUES
CA3290A CA3290 UNITS
Typ. Max. Typ. Max.

mV

103

103

+125 0 C 0.22

0.7 0.22

-55 0 C

0.1

-

0.1

-

15 V
36V

65
130

lk

65
130

lk

~At T A = +125 0 C
At TA

-

= -55°C

4-17

0.7

-

nA
mA
V/mV
dB
V

nA

CA3290A, CA3290

ELECTRICAL CHARACTERISTICS AT TA = 25°C

CHARACTERISTIC

TEST
CONDo
V+

LIMITS
CA3290A

CA3290

Min.

Typ.

Max.

Min.

Typ.

Max.

U
N
I
T
S

Input Offset Voltage,
VIO

VCM=l.4 V
VO=l.4 V

5V

-

4

10

-

7.5

20

VCM:-O V
VO=OV

±15 V

-

4

10

-

7.5

20

VCM=l.4 V

5V

40

50

12

40

-

3.5

±15 V

-

3.5

VCM-O V

12

50

2

25

7

25

-

-

V+-3.5
V-

mV

Input Current, II

Input Offset Current, 110
VCM=l.4 V
VCM=O V

-

5V
±15 V

2

30

7

30

pA

pA

Common-Mode InputVoltage Range, V ICR

VO=l.4V
VO=O V
Supply Current, 1+

V+-3.5

5V

VV+-3.8
V-

±15 V
30 V

5V

RL = 00
Voltage Gain, AOL
RL=15k!1
Output Sink Current
VO=1.4 V

V+-3.1
V--1.5
V+-3.4
V--l.6

-

-

1.35

3

0.8

1.4

V+-3.8

V-

V+-3.1
V--1.5
V+-3.4
V--l.6

V
-

-

1.35

3

0.8

1.4

rnA

25

800

-

25

800

-

V/mV

88

118

-

88

118

-

dB

5V

6

30

-

6

30

-

rnA

5V

-

0.12

0.4

-

0.12

0.4

-

100

-

500

-

±15 V

Saturation Voltage

+VI=O V,
-VI=l V,
ISINK = 4 rnA
Output Leakage Current,
10L
Response Time
RL=5.1k!1 Rising Edge

15 V

-

100

-

36 V

-

500

-

-

-

1.2

--

200

-

44

562

5V

-

100

562

-

Power-Supply Rejection
Ratio, PSRR

±15 V

-

15

316

Large-Signal Response
Time
RL=5.1 k!1

15 V
5V

-

500
400

-

Falling Edge
Common-Mode Rejection
Ratio, CMRR

15 V
±15 V

4-18

-

1.2

-

200

-

44

562

100

562

-

15

316

-

500

-

400

-

V

pA

Ils
ns

IlVN
IlVN

ns

CA3290A, CA3290

~::~LIO~AO~R~E~SI~STftANfCftEf'R~Lf"~~I-~~~'~~_
~=v.
~30~~~+H+H+R+H+~+H+H

~"~~~~~~!m~~~Yi~~~~~
a2o~~~~~tHtHtH~HtHfHt~~tt_~,~,~.c

~

~

"

12,'C

10

A'

ilillillll!!!I!II!lIIIIIiIlIlI'j'II'c
j'
10
15
20
25
30
TOTAL SUPPLY VOLTAGE Iv·} -

35
II

40

45
INPUT COMMON-MODE VOLTAGE (VICl-V

Fig. 4 - Input current as a function
of input common-mode voltage.

Fig. 3 - Supply current as a function
of supply voltage (both amplifiers).

>

~

v'
-10

z v'

~
~

t

1.5

v'
-2.0

'"
v'
~ -2.5
25'C

10
INPUT COMMON MODE VOLTAGE (VIC)-V

15
20
25
30
35
SUPPLY VOLTAGE (v+)- v

40

45

Fig. 6 - Positive common-mode input voltage
range as a function of supply voltage.

Fig. 5 - Input current as a function
of input common-mode voltage.

1.0

A.'

jj
12.S"C

A.'
- 1.0

-1.5

25"C

-2.0

10

15

20

25

30

SUPPLY VOLTAGE (v+) -

35

40

"o L

45

v

w

~

w

~

~

~

AMBIENT TEMPERATUREITA}--C

Fig. 7 - Negative common-mode input voltage

Fig. 8 - Input current as a function of ambient
temperature.

range as a function of supply voltage.

4-19

~

CA3290A, CA3290

: ~p+

··,

'OV

>
I

i~
~

!I

~

~

f

,v

~

CI)

5

·,
··
·
··,+_~!t

~

10 mV

N

Ik

V'ND-..J>vV'v-+--I
TO X\D SCOPE
PROBE

~

~tOOnN
~

N

+

//

Ik

~

+12S-C

, mV

2

IOp.A

IOOI'A

46a

ImA

IOmA

OUTPUT SINK CURRENT-rnA

Fig. 9 - Output saturation voltage as .;
function of output sink current.

WITH Ce'
TOP TRACE ;:i;I:4.5mV/OIV" VIN

BOTTOM TRACE "IOv/DIV" YouT
H a S",s/DIV

!'

100 mV
OVERDRIVE

\

20 mV

'-.....

WITHOUT Cc

5 mV

OVERDRIVE

TOP TRACE

OVERDRIVE

IrS

4,5 mY/DIV

BOTTOM TRACE" IOVlDIV
H" 5~s/DlV

Fig. 10 - Parasitic-oscillations test circuit

and associated waveforms.

INPUT

"
Ik

Fig. 11 - Non-inverting comparator response-time
test circuit and waveforms.

", "

100 mV

OVERDRIVE

Fig. 12 - Inverting comparator response-time
teft circuit and waveforms.

4-20

20mV
OVERDRIVE

5 mV
OVERDRIVE

CA3290A, CA3290

OPERATING CONSIDERATIONS
Input Circuit
The use of MOS transistors in the input stage
of the CA3290 series circuits provides the
user with the following features for comparator applications:
1. Ultra-high input impedance (~1.7 Tn);
2. The availability of common-mode rejection for input signals at potentials
below that of the negative powersupply rail;
3. Retention of the in-phase relationshi p
of the input and output signals for
input signals below the negative rail.
Although the CA3290 employs rugged bipolar (zener) diodes for protection of the
input circuit, the input-terminal currents
should not exceed 1 mAo Appropriate seriesconnected limiting resistors should be used in
circuits where greater current flows might
exist, allowing the signal input voltage to be
greater than the supply voltage without
damaging the circuit.
Output Circuit
The output of the CA3290 is the open collector of an n-p-n transistor, a feature providing
flexibility in a broad range of comparator
applications. An output ORing function can
be implemented by parallel·connection of
the open collectors. An output pull-up resistor can be connected to a power supply
having a voltage range within the rating of
the particular CA3290 in use; the magnitude
of this voltage may be set at a value which is
independent of that applied to the V+
terminal of the CA3290.
Parasitic Oscillations
The ideal comparator has, among other
features, ultra-high input impedance, high
gain, and wide bandwidth. These desirable
characteristics may, however, produce parasitic oscillations unless certain precautions
are observed to minimize the stray capacitive

coupling between the input and output
terminals. Parasitic oscillations manifest them·
selves during the output voltage transition
intervals as the comparator switches states.
For high source impedances, stray capacitance
can induce parasitic oscillations. The addition
of a small amount (1 to 10 mV) of positive
feedback (hysteresis) produces a faster tran·
sition, thereby reducing the likelihood of
parasitic oscillations. Furthermore, if the
input signal is a pulse waveform, with rela·
tively rapid rise and fall times, parasitic
tendencies are reduced.
When dual comparators, like the CA3290,
are packaged in an B·lead configuration, the
output terminal of each comparator is adja·
cent to an input terminal. The lead·to·lead
capacitance is approximately 1 pF, which
may be sufficient to cause undesirable feed·
back effects in certain applications. Circuit
factors such as impedance levels, supply
voltage, toggling rate, etc., may increase the
possibility of parasitic oscillations. To mini·
mize this potential oscillatory condition, it
is recommended that for source impedances
greater than 1 kn a capacitor (;;;. 1-2 pF) be
connected between the appropriate input
terminal and the output terminal. (See Fig.
10.)
The CA3290A and CA3290 are also supplied
in a 14·lead dual-in-line plastic package. To
minimize the possibility of parasitic oscillations the input and output terminals are
positioned on opposite sides of the package.
In addition, there are two leads between the
output terminal of each comparator and its
corresponding inverting input terminal, reducing the input/output coupling significantly. These leads (B, 9,13,14) should be
tied to either the V+ or V- supply rail. If
either comparator is unused, its input terminals should also be tied to either the V+
or V- supply rail.

TYPICAL APPLICATIONS
Light-Controlled One-Shot Timer
In Fig. 13 one comparator (A 1) of the
CA3290 is used to sense a change in photo
diode current. The other comparator (A2)
is configured as a one-shot timer and is
triggered by the output of A1. The output
of the circuit will switch to a low state for
approximately 60 seconds after the light
source to the photo diode has been interrupted. The circuit operates at normal room
lighting levels. The sensitivity of the circuit
may be adjusted by changing the values of
R1 and R2. The ratio of R1 to R2 should be

constant to insure constant reverse voltage
bias on the photo diode.
Low-Frequency Multivibrator
In this application, one-half of the CA3290
is used as a conventional multivibrator circuit. Because of the extremely high input
impedance of this device, large values of
timing resistor (R1) may be used for long
time delays with relativelY small leakage
timing capacitors. The second half of the
CA3290 is used as an output buffer to insure
that the multivibrator frequency will not be
affected by output loading.

4-21

CA3290A, CA3290

Fig. 13 - Light-controlled one-shot timer.

+1!5V
+I~V

I MEG

20 MEG

3.3 K

(3}-i

R I - > t - - -.....
IMEG

PER 100"10 SEC/CYCLE

T-2RC In[~ +1]
1 MEG

Fig. 14 - Low·frequency multivibrator.

Window Comparator
Both halves of the CA3290 can be used in a
high input·impedance window comparator
as shown in Fig. 15. The LED will be

turned "on" whenever the input signal is
above the lower limit (VU but below the
upper limit (VU), as determined by the
R1/R2/R3 resistor divider.

lOOK

LED
+ISV

47 "
RI

670.0

INPUT

47"
R2
lOOK

Fig. 15 - Window comparator.

4-22

CA3290A, CA3290

LED Bar Graph Driver
The circuit in Fig. 16 demonstrates the use
of the CA3290 in a bar graph display. The
non-inverting inputs of both comparators
are tied to the voltage divider reference and
the in put signal is appl ied to both of the

inverting inputs. The LED for a particular
comparator will be turned "on" when the
input voltage reaches the voltage on the
resistor divider reference. The CA3290 is
ideal for this application where input-signal
loading is critical even though many comparator inputs are driven in parallel.

I MEG

0-10 V
INPUT

Fig. 16 - LED bar-graph driver.

The photographs and dimensions of each chip
represent a chip when it is part of the wafer.
When the wafer is cut into chips. the cleavage
angles are 57' instead of 90' with respect to the
face of the chip. Therefore. the isolated chip is
actually 7 mils (0.17 mm) larger in both dimen-

sions.
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as in-

dicated. Grid graduations are in mils (10- 3 inc").

NOTE: NOS. IN PADS ARE FOR 8-LEAD DIP AND TO-5
NOS. OUTSIDE OF CHIP ARE FOR 14- LEAD DIP
9ZCM-30091

Dimensions and pad favour for rhe CA3290H.

4-23

mHARRIS

HA-4900/02/05
Precision Quad Comparator

May 1990

Features

Applications

•
•
•
•
•
•

•
•
•
•
•
•

Fast Response Time ••••••••••••••••••••••••• 130ns
Low Offset Voltage •••••••••••••••••••••••••• 2.0mV
Low Offset Current ••••••••••••••••••••••••••• 10nA
Single or Dual-Voltage Supply Operation
Selectable Output Logic Levels
Active Pull-Up/Pull-Down Output Circuit-No
External Resistors Required

Threshold Detector
Zero-Crossing Detector
Window Detector
Analog Interfaces for Microprocessors
High Stability Oscillators
Logic System Interfaces

Description
The HA-4900 series are monolithic, quad, precision
comparators offering fast response time, low offset voltage,
low offset current and virtually no channel-to-channel
crosstalk for applications requiring accurate, high speed,
signal level detection. These comparators can sense
signals at ground level while being operated from either a
single +5 volt supply (digital systems) or from dual supplies
(analog networks) up to ±15volts. The HA-4900 series
contains a unique current driven output stage which can be
connected to logic system supplies (VLogic + and VLogic-)
to make the output levels directly compatible (no external
components needed) with any standard logic or special
system logic levels. In combination analog/digital systems,

Pinouts

the design employed in the HA-4900 series input and
output stages prevents troublesome ground coupling of
signals between analog and digital portions of the system.
These comparators' combination of features makes them
ideal components for signal detection and processing in
data acquisition systems, test equipment and microprocessor/analog signal interface networks.
All devices are available in 16 pin dual-in-line ceramiC
packages. The HA-4900/4902-2 operates from -550e to
+1250 C and the HA-4905-5 operates over a ooe to
+750e temperature range. For military grade product, refer
to the HA-4902/883 data sheet

Schematic

HA1-4900/02/05
(CERAMIC DIP)
TOP VIEW
OUT 4
-IN4

..I-IN4

lLllllICI-)

...
ALL RUISTDI\S "'tOI

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1 991

4-24

File Number

2855

HA-4900/02/05
Absolute Maximum Ratings (Note 1)

Operating Temperature Ranges

Voltage Between V+ and V- Terminals .•••••••••••••••••••• 33V
DifferenUalinput Voltage ••••••••••••••••.••.••••••••••• , ±15V
Voltage Between VLogic (+) and VLogic (-) ••••••••••••.•••• 18V
Peak Output Current •••••••••••••••••••••••••••.•••••• ±50mA
Internal Power Dissipation (Note 7, 8) ••.•.•••••.•••••••••• 2.0W

HA-4900-2 ••••••••••••••••••••• " ••••• -550C.:5 TA.:5 +1250C
HA-4902-2 ••.••••••.••.••••••••••••••• -550C.:5 TA :S +1250C
HA-4905-5 ••••••••••••••••••••••••••••••• ODC:5 TA :5 + 7SoC
Storage Temperature Range: ••••••••••••• -65°C :5 TA.:5 +150 0C

Electrical Specifications V+

= +lSV, V- = -15V, VLogic (+) = sv, VLoglc (-) = GND.
HA-4900-2
-5S OC to +125 0 c

PARAMETER

TEMP

MIN

TYP

MAX

2

3

HA-4902-2
-550C to +1250 C
MIN

TYP

MAX

HA-4905-S
OOCto+750C
MIN

TYP

MAX

UNITS

4

7.5

mV

10

mV

50

nA

70

nA

150

nA

INPUT CHARACTERISTICS
Offset Voltage (Note 2)

+250C
Full

Offset Current

+250C

10

Full
Bias Current (Note 3)
Input Sensitivity (Note 4)

+250C

50

Differential Input Resistance

5
8

25

10

35

35

25

45

75

50

150

100

Full

150

200

300

nA

+250C

VIO+·3

VIO+·5

VIO+·5

mV

VIO+·7

mV

Full
Common Mode Range

2

4

Full

VIO+·4
V-

(V+)-2.4

+25 0C

250

VIO+·6
V-

(V+)-2.6

V-

250

(V+)-2.4
250

V
MO

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain

+250C

400K

Response Time (I"pdO) (Note 5)

+25OC

130

200

130

200

130

200

ns

Response Time (Tpd 1) (Note 5)

+25OC

180

215

180

215

180

215

ns

0.2

0.4

0.2

0.4

0.2

0.4

400K

400K

VN

OUTPUT CHARACTERISTiCS
Output Voltage Level
Logic "Low State" (VoLl (Note 6)

Full

Logic "High State" (VOH) (Note 6)

Full

3.5

Full

3.0

3.0

3.0

mA

Full
ISource
POWER SUPPLY CHARACTERISTICS

3.0

3.0

3.0

mA

4.2

3.5

4.2

3.5

4.2

V
V

Output Current
ISlnk

Supply Current, Ips (+)

+25OC

6.5

20

6.5

20

7

20

Supply Currer.t, Ips (-)

+25 0C

4

8

4

8

5

8

mA
mA

Supply Current, Ips (Logic)

+2SoC

3.5

4

3.5

4

3.5

4

mA

Supply Voltage Range
VLogic (+) (Note 7)

Full

0

+15.0

0

+15.0

0

+15.0

V

VLogic (-) (Note 7)

Full

-15.0

0

-15.0

0

-15.0

0

V

4-25

HA-4900/02/05
NOTES:
input step, 10mVoverdrive. Frequency~100Hz; Duty Cycle~50%;
Inverting input driven. See Test Circuit below. All unused inverting inputs
tie to +5V.

1. Absolute maximum ratings are limiting values, applied individually.
beyond which the serviceability of the circuit may be Impaired. Functional operability under' any of these conditions Is not necessarily implied.
2. Minimum differential input voltage required to ensure a defined output

6.

state.
3. Input bias currents are essentially constant with differential input
voltages up to ± 9 volts. With differential input voltages from ±9 to ±15
volts, bias current on the more negative input can rise to approximately
500~ This will also cause higher supply currents.
4.

RS ~ 2000 VIN 'S. Common Mode Range. Input sensitivity is the worst
case minimum differential input voltage required to guarantee a given
output logic state. This parameter includes the effects of offset
voltage, offset'current, common mode rejection, and voltage gain.

5.

For Tp d(1); 100mV Input step, -10mV overdrive. For Tpd(O); -100mV

For VOH and VOL: 'Sink =- 'Source :::::< 3.0mA. For other values of Vl09iC;
VOH (min.) = VLoglc + -1.5V.

7. Total Power Dissipation (T.P.D.) is the sum of individual dissipation
contributions ofV+, V- and VlOgic shown in curves of Power Dissipation
vs. Supply Voltages (see Performance Curves). The calculated T.P.D. Is
then located on the graph of Maximum Allowable Package Dissipation
vs. Ambient Temperature to determine ambient temperature operating
limits imposed by the calculated T.P.D. (See Performance Curves). For
instance, the combination of +15V, -15V, +5V, OV (V+, V-, VLogiC+.
VLogic-) gives a T.P,D. of 350mW, the combination +15V, -15V. OV
gives a T.P,D. of 450mW.
B, Derate By 5.BmW/Dc aboveTA = +750 C.9ja = 75 0CIW,9jC = 200 C/W.

Test Circuits

+15V

>---oVOUT

Tpd(O)

DVERDRI~r-_ _ _ _ __

INPUT

T

----- -

f~

VTH=OV

100mV

~

100mV

------VTH=OV

T
OVERDRIVE

OUTPUT

For input and output voltage waveforms for various Input overdrives see Performance Curves.

4-26

HA-4900/02/05
Typical Performance Curves

V+ = 15V, VLogic (+) = 5V, VLogic (-) = OV, TA = +250 C,
Unless Otherwise Specified.

INPUT BIAS CURRENT vs. TEMPERATURE

INPUT OFFSET CURRENT vs. TEMPERATURE

ID0

0

5

.

0

0

""""-

r--..

0

5

-

V-

/

~

/
0

0

-55

-25

50

25

75

125

IDD

TEMPERATURE,IOC)
0

-55

75

50

25

-25

100

125

TEMPERATURE. (IIC)

INPUT BIAS CURRENT VS. COMMON MODE INPUT VOLTAGE
(VDlFF. = OV)
D

I--

............

D

I..............

-....

D

\

D

D
15

12

12

\
15

COMMON MODE INPUT VOLTAGE

SUPPLY CURRENT vs. TEMPERATURE
FOR ±15V SUPPUES AND ± 5V LOGIC SUPPLY

SUPPLY CURRENT vs. TEMPERATURE
FOR SINGLE +5V OPERATION

12r----r----,-----r----r----,-~~r---_r--__,

V+" 15.0V
V-"15.DV

v+"s.ov

5.ov

Ips'"

VlOGIC(+)=

Va UP L

VlOGIC(-) = GND

1D~---r~==j:====~===+~~~~~~~:t==~

IpsL

-~---+--~--~--~~~--~--~

-

f----It-"_--I__--I_-I-IPS.

1
~~ 6f----+----+----f----+VOUT

VLDGICi+1= 5.DV
y_ ". VLOGlcf-1 z GND

....

--+,/--+--+---;

VOUT-H

------

5

~

~

~

=

VOUT-H

L1-.......
----+----1-----1

4

f----+-----+----f----+~~g~T· HI-/----+----I-----I

3

.. V

IpS'"
VOUT"'L

....

7--....

IpsL

IpsL
VQUT"L

Vour=L
IpSL

-"-

IPS"

VOUT",H

~

~

2

/

VOUT"H

·50

-25

25

50

75

100

1

125

TEMPERATURE,IUCI
D

-50

·25

25

TEMPERATURE,loCI

4-27

50

75

IDD

125

HA-4900/02/05
Typical Performance Curves

=

=

(Continued) V+ 15V, VLogic (+) 5V, VLogic (-)
Unless Otherwise Specified.

= OV, TA = +250 C,

RESPONSE TIME FOR VARIOUS INPUT OVERDRIVES

'1\\

~\'

VOUT
VOLTS

\

•

°

v,.

~OVERORIVE. 2~V

DVERDRI~E

• 5~V
-ZmV

.-/

i=

.. 2OmV............

·':"V.....,
•""V....., "':;, ~ ~

VOUT
VOLTS

~

/. V
f 'J

\1\\

•

"00

v,.

·.00

v

.00

200

lIl'

mV

.,

200

'00

TIMEns

MAXIMUM POWER DISSIPATION VS. SUPPLY VOLTAGE
(NO LOAD CONDITION)

MAXIMUM PACKAGE DISSIPATION VS. TAMBIENT
2.0
1.15

".

'\

200

1\

1.50

I,;

\

v.

~ ISO

1.25

iii
0;

./

I
5.

0.50

/'

,/

r-:::

0.2 5

--

...... I--

75

100

~

v· ..... 1-- 7'
V ..... Ie-"
1\
I-- r--vlOGlet - -

•
10
SUPPLV VOL TAGE,IYOLTSJ

50

/

V

V

a:: 100

1\

0.7 5

j.) V

If

'\

25

...

'00

TIMEns

12

It

125

AMBIENT TEMPERATURE' oc

Applying the HA-4900 Series Comparators
1. SUPPLY CONNECTIONS: This device is exceptionally
versatile in working with most available power supplies.
The voltage applied to the V+ and V- terminals
determines the allowable input signal range; while the
voltage applied to the VL+ and VL- determines the
output swing. In systems where dual analog supplies
are available, these would be connected to V+ and V-,
while the logic supply and return would be connected
to VLogic+ and VLogic-. The analog and logic supply
commons can be connected together at one point in the
system, since the comparator is immune to noise on the
logic supply ground. A negative output swing may be
obtained by connecting VL+ to ·ground and VL- to a
negative supply. Bipolar output swings (15V P-P, max.)
may be obtained using dual supplies. In systems where
only a single logic supply is available (+5V to 15V), V+
and VLoglc+ may be connected together to the positive
supply while V- and VLogic- are grounded. If an input
signal could swing negative with respect the Vterminal, a resistor should be connected in series with
the Input to limit Input current to < 5mA since the C-B
Junction of the input transistor would be forward biased.

2.

UNUSED INPUTS: Inputs of .unused comparator
sections should be tied to a differential voltage source
to prevent output "chatter".

3.

CROSSTALK: Simultaneous high frequency operation
of all other channels in the package will not affect the
output logic state of a given channel, provided that its
differential input voltage is sufficient to define a given
logic state (AVIN 2: ±VOS). Low level or high
Impedance Input lines should be shielded from other
signal sources to reduce crosstalk and interference.

4.

POWER SUPPLY DECOUPLlNG: Decouple all power
supply lines with .01 f1F ceramic capacitors to ground
line located near the package to reduce coupling
between channels or from external sources.

5.

RESPONSE TIME: Fast rise time « 2oons) input
pulses of several volts amplitude may result in delay
times somewhat longer than those illustrated for 100mV
steps. Operating speed Is optimized by limiting the
maximum differential input voltage applied, with
resistor-diode clamping networks.

4-28

HA-4900/02/05
Typical Applications

r----------,

r-------- - - --.,

I
I

-

ANALOG
INPUTS

1

COMPARATORS

I

MICROPROCESSOR

I
I
INTERFACE

I
L
__________ _J

ANALOG INPUT MODULE

PROCESSOR

Data Acquisition System
In this circuit the HA-4900 series is used in conjunction
with a 0 to A converter to form a simple, versatile,
multi-channel analog input for a data acquisition system. In
operation the processor first sends an address to the 0 to A,
then the processor reads the digital word generated by the
comparator outputs.
To perform a simple comparision, the processor sets the 0
to A to a given reference level, then examines one or more

comparator outputs to determine if their inputs are above or
below the reference. A window comparison consists of two
such cycles with 2 reference levels set by the 0 to A. One
way to digitize the inputs would be for the processor to
increment the 0 to A in steps. The 0 to A address, as each
comparator switches, is the digitized level of the input.
While stairstepping the 0 to A is slower than successive
approximation, all channels are digitized during one
staircase ramp.

tS.OV

TTL TO CMOS

CMOS TO TTL

Logic Level Translators
The HA-4900 series comparators can be used as versatile
logic interface devices as shown in the circuits above.
Negative logic devices may also be interfaced with
appropriate supply connections.

If separate supplies are used for V- and VLogic-, these
logic level translators will tolerate several volts of ground
line differential noise.

4-29

HA-4900/02/05
Typical Applications

(Continued)
+10.

INPUT

4.7K
3W'

>!.....- - - - O H I

HI REF

0--++-1

LO REF

0--++-1

lK

.>1r+----O LO

lK

RS-232 To CMOS Line Receiver

Window Detector

This RS-232 type line receiver to drive CMOS logic uses a
Schmitt trigger feedback network to give about 1 volt Input
hysteresis for added noise Immunity. A possible problem In
an interface which connects two equipments, each plugged
into a different AC receptacle, is that the power line voltage
may appear at the receiver input when the Interface
connection is made or broken. The two diodes and a 3 watt
input resistor will protect the inputs under these
conditions.

The high switching speed, low offset current and low offset
voltage of the HA-4900 series makes this window detector
circuit extremely well suited to applications requiring fast,
accurate, decision-making. The circuit above is ideal for Industrial process system feedback controllers or "out-oflimit" alarm indicators.

+15V

V+

C>----.-oO

VOH"'4.2V

"2

'U
,

2K

-15V
1

F"'2.1lIi"f1

Rl

loonl

R3

13K

-15V

Schmitt Trigger (Zero Crossing Detector
With Hysteresis)

Oscillator/Clock Generator
this self-starting fixed frequency oscillator circuit gives
excellent frequency stability. R1 and C1 comprise the
frequency determining network while R2 provides the
regenerative feedback. Diode 01 enhances the stability by
compensating for the difference between VOH and
VSupply. In applications where a precision clock generator
up to 100kHz is required, such as in automatic test
equipment, C1 may be replaced by a crystal.

This Circuit has a 100mV hysteresis which can be used in
applications where very fast transition times are required at
the output even though the signal input is very slow. The
hysteresis loop also reduces false triggering due to noise
on the input. The waveforms helow show the trip points developed by the hysteresis loop.
VOH

OV~U-

__________

Input to Output Waveform
Showing Hysteresis Trip Points

4-30

~L-

_____

~_

HFA-0003
HFA-00031.

mHARRIS
PRELIMINARY

Ultra-High Speed Comparator

August 1991

Features

Pinouts

• Low Propagation Delay (0003/0003L) ••••.••••••••••••••••••••• 2.0/2.1 ns
• Low Latch Set·up Time ••..•••••.••.••••••••••••••••••••••••••••••• 0.8ns
• Low Offset Voltage, Drift Coefficient. •••••••••••••••••••••• 1.0mV, 4JlVloC
• Wide Common Mode Range •••••••.••••••••••••••••••••••••••• +5.21-2.8V

HFA7-0003-5/-9
(CERAMIC SIDEBRAZE DIP)
HFA3-0003-5/-9 (PLASTIC MINI-DIP)
HFA9P0003-5/-9 (SOIC)
TOP VIEW

• Low Power Dissipation •••••••••••••••••••••.•••••••••••••••••••• 200mW
• Large Differential Input Resistance ••••••••••••••••••••.••••••••••••. 1 MO
• Complementary ECL Outputs; 500 Driving Capability
• Resistor Programmable Hysteresis with '0003L
• Pin Compatible with MAX9690/9685 & AD96685
• Available in SOIC

Applications
• Window Detector
• High Speed Peak Detector
• High Speed Threshold Detector
• High Speed Data Acquisition Systems

HFA1-0003L-5/-9
(CERAMIC SIDEBRAZE DIP)
HFA3-0003L-5/-9 (PLASTIC DIP)
HFA9P0003L-5/-9 (SOIC)
TOP VIEW

• Fiber Optic Decision Circuits
• High Speed Phase Detector
• Frequency Counter

Description

GND 1

The HFA-0003/0003L are monolithic, ultra high speed, voltage comparators. These
comparators combine a low input offset voltage (1.0mV) with a low propagation
delay (2.0ns) to achieve a large dynamic input range. The low offset voltage also
makes these comparators ideally suited for high speed, precision analog-to-digital
processing applications. The circuits have differential analog inputs, and provide
complementary, ECL compatible (10K and 100K) logic outputs. The outputs are
capable of supplying the current required by terminated 500 transmission lines.
Both outputs are open emitter structures, requiring external pull-down resistors.
The recommended circuit is 500 connected to -2.0V, but any equivalent ECL
termination circuit may be used.

GND2

V+

NC

+IN

NC
NC

NC

COUT

LE

a OUT
NC

NC

HYS

The HFA-0003L Is a latched version of the HFA-0003. The latch function allows the
HFA-0003L to operate in sample-hold or track-hold modes, when synchronous
detection is required. The Latch Enable (LE) input can be driven by a standard ECL
gate. See the Applications section on page 4 for more information on this feature.
The HFA-0003L also has an additional feature, user programmable hysteresis. By
connecting a resistor from the HYS pin to GND the user can select up to 20mV of
input hysteresis. See the Applications section on page 4 for more information on this
feature.

HFA2-0003L-5/-9
(TO-l00 METAL CAN)
TOP VIEW
GNDl

The HFA-0003 is pin compatible with the MAX9690, and SP9680 while providing
improved performance. The HFA-0003L is pin compatible with the MAX9685,
AD96685, SP9685, HCMP96850, and the VC7695 while providing improved
performance.
The performance of the HFA-0003/0003L-9 is guaranteed from -400 C to +850 C,
while the HFA-0003/0003L-5Is guaranteed from OOC to +75 0 C. The HFA-0003 is
available In 8 pin Plastic DIP, Ceramic Sidebraze DIP, and SOIC. The HFA-0003L Is
available In 16 pin Plastic DIP, Ceramic Sidebraze DIP, SOIC, and a TO-1 00 Metal
Can package. Refer to the /883 datasheets for military compliant product.
CAUTION: Electronic devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

Copyright @ Harrl. Corporation 1991

4-31

v·
File Number

2749.2

Specifications HFA-0003/HFA-0003L
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- Terminals ••••••.••••.••••••..• 20V
SupplyVoltage(GNDtoV+) ••••••••••.••••••••.•••••••.•.• 8V
Supply Voltage (GND to V-) .••••••.••.•••.•••..••..•...••. 1BV
Differential Input Voltage ••••••••••••••••••••..•••..•.•••• 5.5V
Common Mode Voltage •••••••.••.••.•.••.••••.••••.•..•• ±5V
Differential Ground Voltage (GNDl to GND2) •••.••••••.••••• ±1V
Peak (Short Duration) Output Current (Note 2) ..•••.•••.•• -35mA
Maximum Junction Temperature ••••....•••••.••••.•... +175 0 C
Maximum Junction Temperature (Plastic Packages) ....• +1500 C

HFA-0003/HFA-0003L-9 .••..•.••.••.••. -400 C $TA$+850 C
HFA-0003/HFA-0003L-5 .•....•...•..••••• COC S TA S +750 C
Storage Temperature Range •••••.•..••.• -65 0 C S TA ::; +150 0 C
Thermal Package Characteristics
0jc
0ja
8 Pin Ceramic Sidebrazed DIP .••••
39
95
8 Pin Plastic DIP. • • • • • • • • . • • • • • • • .
34
96
8PinSOIC. ••.•• ••• .•• .••.••. ••••
42
161
16 Pin Ceramic Sidebrazed DIP. . • • •
34
79
16 Pin Plastic DIP. • . . . • • . • • • . • • . • • •
32
92
16PinSOlC ... ..•..•.. ..... ....••
35
114
TO-l00 Metal Can.................
32
108

Electrical Specifications V+ = 5V, v- = -5.2V, RL = son to -2V, Unless Otherwise Specified
HFA-0003-5/-9
PARAMETER

HFA-0003L-5/-9

TEMP

MIN

TYP

MAX

+250 C
Full

-

1

3
4

MIN

TYP

MAX

UNITS

1

3
4

mV
mV

INPUT CHARACTERISTICS
Input OllsetVoltage (VOS)
Average Ollset Voltage Drift (Note 8)
Input Bias Current
Input Ollset Current
Common Mode Range
Dillerentlallnput Resistance
Common Mode Input Resistance
Input Capacitance

Full
+25 0 C
Full
+250 C
Full
Full
+2S oC

-

-

-

-

-

5

-

8

-

0.15

-2.8

-

+2S oC
+250 C

-

+2S oC
Full

-

+25 0 C
Full

70
70

75

+250 C

-

270

+2SoC
Full

2.0

Full

-

+250 C
Full

-

-1.83

-

-1.83

+2So C
Full

-0.938
-1.05

Full

-30

1
9.S
1

4

-

-

-

-

S

4

~VjOC

8
13

~
~A

-2.8

-

0.2
0.3
+5.2

-

1
9.S
1

-

V
Mn
Mn
pF

-

3100

-

VN

8
13

-

0.2
0.3

-

+5.2

-

-

8
0.15

~A

~A

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
Common Mode Rejection Ratio (Note 3)
Tracking Bandwidth (Note 4)

-

3100
1200

-

-

-

-

1200

-

70
70

7S

-

-

270

-

2.1

-

VN
dB
dB

-

MHz

SWITCHING CHARACTERISTICS
Propagation Delay Input to Output (tpd)
(Notes 5, 8, 9)
Maximum Dispersion (Notes 6, 8)

2.6
3.0

ns
ns

-

-

200

ps

-1.65
-1.57

-

-1.83
-1.83

-1.65
-1.57

V

-0.8S
-0.96

-

-0.938
-1.05

-0.85
-0.96

V
V

-

-

-30

-

-

-

2.4
2.8

-

200

OUTPUT CHARACTERISTICS
Output Voltage Level
Logic Low (VOL)
Logic High (VOH)
Continuous Output Current (Note 2)

4-32

V

mA

Specifications HFA-0003/HFA-0003L
Electrical Specifications (Continued)

V+ ; SV,

v- ;

-S.2V, RL ;

son to -2V, Unless Otherwise Specified

HFA-0003-S/-9
PARAMETER

HFA-0003L-5/-9

TEMP

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Logic Low (VII)

Full

-

-

-

-1.475

V

Full

-

-

Logic High (VIH)

-1.10S

-

-

V

-

-

-

LATCH CHARACTERISTICS (HFA-0003L ONLY)
LE Input Voltage Level

LE Input Current Level
Logic Low

(VIL;-l.BSV)

Full

Logic High

(VIH; -0.B1V)

Full

Propagation Delayfrom LE to Oufput (tpdL)
(Notes 5, 8, 9)
Minimum Set-Up lime (tsl

(NotesB,9)

+250 C
Full
+2So C
Full

Minimum Hold Time (th)

(NotesB,9)

Minimum LE Pulse Width (t pw)

(NotesB,9)

Full
+2So C
Full

-

-

-

-

-

-

0.06

0.5

pA

-

11

20

pA

-

2.2
2.6

2.7
3.1

ns
ns

O.B

1.2

ns

-

1.5

ns

0.5

1.0

ns

0.9

0.95

ns

-

1.1

ns

-

-

-

BO

-

70

80

65

-

-

-

POWER SUPPLY
PSRR (Note 7)

+2SoC
Full

ICC

Full

lEE

Full

Power Dissipation

Full

70
6S

-

-

11

13

19

22

-

200

-

NOTES:

1. Absolute maximum ratings are limiting values, applied individually. beyond which the servicability of the circuit
may be impaired. Functional operation under any of thesa conditions Is not necessarily Implied. Exposure to
absolute maximum rating conditions may affect device reliability.
2. Outputs have no sink current (+1) capability, since they are opsn emitter NPN transistors.

3. -2.0V .:S VCM":s +4.0V.
4. Tracking Bandwidth (TBW) is defined as the maximum input frequency at which the outputs still switch between
VOL and VOH- Y,N = 15mVp_p sinewave centered on av.
5. VIN ... l00mV. VOO Is the amount of input overdrive.
6. Dispersion is defined as the change in propagation delay for input overdrives between O.1V and 1.0V.

7. +4.0V..:S V+ .:S +5.5V or -6.2V .:S V- .:S -4.7V.
8. This parameter Is not tested. It Is guaranteed by design, and by device characterizallon.

9. VOD = 10mV.

4-33

-

-

dB
dB

11

13

rnA

19

22

rnA

-

200

mW

U)

IX:

i
::;:

o

o

HFA-0003/HFA-0003L
Applications Information
HFA-0003L Latch Functionality
The Latch Enable (lE) pin of the '0003l controls the function of the on chip latch. When the LE input is at an ECl
Logic 1, the latch is open (transparent) and the comparator
functions normally. When the LE input switches to a Logic
0, the outputs are latched in unambiguous states dependant on the current input state, providing the set-up and
hold times are met. If the latch function is not utilized, the LE
input must be connected to an ECl Logic 1 (e.g. GND).

current not exceed 1mA. The input current can be approximated from the following formula:
IH =

GND-(V-)-0.7V
RH

The table below gives approximate levels of hysteresis for
some values of IH, at TA = +2S o C.
IH (mA)

0.2

0.4

0.6

0.8

1.0

1

4

8

13

22

HFA-0003L Hysteresis Functionality

HYS(mV)

To improve performance in systems with slow transition
times, and/or high noise levels, the HFA-0003L allows the
user to easily set the amount of input hysteresis. The hysteresis level is set by the current flowing into the HYS input;
the larger the current the larger the level of hysteresis. This
current Is provided by connecting a resistor (RH) between
the HYS pin and GND, and it is recommended that the input

If the hysteresis function isn't used, the HYS input may be
left floating, or may be connected to V-. The HYS input
MUST NEVER BE CONNECTED directly to GND or V+, as
device damage will occur. Before inserting an
HFA-0003l into a competitor socket, the user must
ensure that the corresponding socket pin is a true
no-connect (i.e. is floating).

Timing Diagram
COMPARE
LE·---.r

ts---

LATCHED

J~-----~

--

tpw

~I--------:----

~~-~~------------------+
__

5()C!(,

Vos

tpdl ___

____

tpd ___

a - - - - - - - - - - - .-"'-.....J~ _ _ _ _ _ -7J...f-------------

a

.----------~

----

10;;::------------

4-34

5()C!(,

SAMPLE AND HOLD

AMPUF~ERS

PAGE
SELECTION GUIDE. . .. . . .. ... . .. . .. . ... .. . .. . . ... .. . .. . . . . . . . .. . .. . . .. .. . . .. . .. . .. . .. . .. . . ... ..

5-2

SAMPLE AND HOLD DATA SHEETS
HA2420,25

Fast Sample and Hold Amplifier ................................................... 5-3

HA5320

High Speed Precision Monolithic Amplifier. .. . .. . . . . . .. . . . . . .. . .. . .. . .. . .. . .. . . .. ...

5-10

HA5330

Very High Speed Monolithic Amplifier ........................................... ' "

5-17

HA5340

High Speed, Low Distortion, Monolithic Amplifier .................. .. . .. .. . ... . . . ....

5-21

o
.....

OU)

::J:a:

Ow

~§

We..
.....
:;;
e..c(

!

5-1

Selection Guide
SAMPLE-AND-HOLD AMPLIFIERS

TYPE

SAMPLE/HOLD
TYPE

TEMPERATURE
RANGE

PACKAGE'

-ssOC to +12S oC
-ssOC to +12SOC
00Cto+7SoC
00Cto+750C
OOCto+750C
-S50C to + 1250C
OOCto +7SoC

14-Pin Cerdip
14-Pin Cerdip
14-Pin Cerdip
14-Pin Cerdip
14-Pin Epoxy
20-Pin LCC Ceramic
20-Pin PLCC Epoxy

HA1-2420-2
HA1-2420-8
HA1-242S-S
HA1-2425-7
HA3-2425-5
HA4-2420/883
HA4P2425-S

Low Droop Rate

HA1-5320-2
HA1-5320-5
HA1-5320-7
HA1-5320-a
HA3-5320-5
HA4-5320-8

High Speed
Low Charge
Transfer Precision
Complete-Includes
Hold Capacitor

-S50 C to + 1250C 14-Pin Cerdip
00Cto+750C
14-Pin Cerdip
14-Pin Cerdip
OoCto +750 C
-S5OC to +12SOC 14-Pin Cerdip
OoCto +750 C
14-Pin Plastic DIP
-550 C to +1250 C 20-Pin LCC Ceramic

HA1-5330-S
HA1-5330-4
HA1-S33O-2
HA1-S330/883
HA4-S330/883

Very High Speed
Precision
Monolithic
Complete-Includes
Hold Capacitor

OOCto+750C
14-Pin Cerdip
-250C to +8SoC 14-Pin Cerdip
-SSoC to + 1250 C 14-Pin Cerdip
-S5OC to + 1250 C 14-Pin Cerdip
-550C to +12SoC 20-Pin LCC Ceramic

HA1-S340-S
HA1-S340-9

High Speed
Low DislortionIncludes Hold
Capacitor

00Cto+750 C
-400C to +8SoC

14-Pin Cerdlp
14-Pin Cerdip

• See Packaging and Ordering Information in Section 12

5-2

ACQUISITION
TIME
(TO 0.01%)
TYP,+250C

CHARGE
TRANSFER
TYP,
+250 C

APERTURE
GAIN
TIME
~ANDWIDTH
TYP,
PRODUCT
+250 C
TVP,+250C

3.21'8

10pC

30ns

2.5MHz

0.1 pC

25ns

2.0MHz

(CH =1,OOOpF)

1~s

(CH = Intemal)

CH=100pF

500ns

0.05pC

20ns

4.5MHz

700n8

0.5pC

1Sns

iOMHz

HA 242 0/25
Gm

Fast Sample and Hold

August 1991

Features

Applications

Maximum Acquisition Time (10V Step to 0.1%) ••• 41ls
(10V Step to 0.01%) .••••••••••••••.••••••••••• 61ls
o Low Droop Rate (CH
1000pF) ••••••• SIlV/ms (Typ.)
• Gain Bandwidth Product •••••••••••••• 2.SMHz (Typ.)
• Low Effective Aperture Delay Time •••• •• 30ns (Typ.)
o TTL Compatible Control Input
• ±12V to ±lSV Operation

o 12-Bit Data Acquisition
• Digital to Analog Deglitcher
o Auto Zero Systems
• Peak Detector
o Gated Operational Amplifier

o

=

Description
The HA-2420/2425 is a monolithic circuit consisting of a
high performance operational amplifier with its output in
series with an ultra-low leakage analog switch and
MOSFET input unity gain amplifier.
With an external holding capacitor connected to the switch
output, a versatile, high performance sample-and-hold or
track-and-hold circuit is formed. When the switch is closed,
the device behaves as an operational amplifier, and any of
the standard op amp feedback networks may be connected
around the device to control gain, frequency response, etc.
When the switch is opened the output will remain at its last
level.
Performance as a sample-and-hold compares very favorably with other monolithic, hybrid, modular, and discrete
circuits. Accuracy to better than 0.01% is achievable over

Pinouts

14 PIN CERAMIC/PLASTIC DIP
TOP VIEW
14

the temperature range. Fast acquisition is coupled with
superior droop characteristics, even at high temperatures.
High slew rate, wide bandwidth, and low acquisition time
produce excellent dynamic characteristics. The ability to
operate at gains greater than 1 frequently eliminates the
need for external scaling amplifiers.
The device may also be used as a versatile operational
amplifier with a gated output for applications such as
analog switches, peak holding circuits, etc. For more information, please see Application Note 517.
The HA-2420/25 is offered in a 14 pin Ceramic or Plastic
DIP and a 20 pad Ceramic LCC or 20 pad PLCC. The
MIL-STD-883 data sheet for this device is available on
reques!.

Functional Diagram

SiH CONTROL

OFFSET
ADJUST

+v

~

3

OFFSET ADJ. 3

4

9

HA - 242012425

OFFSET ADJ. 4

• IN "'-:.r...... ,..~I

> .....-+7:...0 OUT

+IN

CONTj~~~--~I~~

OUTPUT 7

20 PAD LCC/PLCC
TOP VIEW

11
GND

~~~I~~
t~J
OFFSET ADJ.

1]

NC

~]

HOLD
CAPACITOR

tgj t~J t~qj Lt9J

[fa

NC

if7 NC

OFFSET ADJ.

~

[~6 HOLD CAP.

NC

!]

[15

NC

~ P_' P_' P_' P_' P_' [f4

NC

v·

-v

19 1 11m 111 1 '121 113'

~

8~

~ ;t

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyrighl @) Harris Corporalion 1991

5-3

File Number

2856

Cl
.....

0

00

:::t:a:

ClUJ
z
«!!::

w~
.....
:;:

~«

«

00

Specifications HA-2420/2425
Absolute Maximum Ratings

Operating Temperature Range

Voltage Between V+ and V- Terminals ••••••••••••••••••••• 40V
Differential Input Voltage •••••.•••••••••••••••••••••••••• ±24V
Digital Input Voltage (Sample and Hold Pin) •••.••••..• +BV. -15V
Output Current ••.•••••••••••••••••••••• Short Circuit Protected
Junction Temperature •.••••.••••••••••••••••••••••••• +1750 C

HA-2420-2/-B ••••••••••••••••••••••••• -550C!'> TA ~ +1250 C
HA-2425-5/-7 ••••••••••••••••••••••••••••• 00C STA!'> +750 C
Storage Temperature Range •••••••.••••• -650C!'> TA!,> +1500 C

Electrical Specifications

Test Conditions (Unless Otherwise Specified) VSUPPLY = ±15.0V; CH
Digital Input: VIL = +O.BV (Sample). VIH = +2.0V (Hold).
Unity Gain Configuration (Output tied to -Input)
HA-2420-2/-8

PARAMETER

HA-2425-5/-7

TYP

MAX

MIN

-

-

±10

2
3
40

4
6
200
400

-

TEMP

MIN

Full
+250C
Full
+250C
Full
+25OC
Full
+250 C
Full

±10

5
±10

10
-

Full
Full
Full
+250 C

25K

50K

-BO

-

-90
-76
2.5

Full
+25OC
+250 C
+250 C

±10
±15

-

-

100
0.15

+250 C
+250 C
+25 0C

-

= 10oopF;

TYP

MAX

UNITS

INPUT CHARACTERISTICS
Input Voltage Range
Offset Voltage
Bias Current
Offset Current
Input Resistance
Common Mode Range

-

-

-

-

6

40

200
400
50
100

10

5
±10

10

25K
-74

50K
-90
-76
2.5

100

-

-

-

50

10

3
4

-

-

V
mV
mV
nA
nA
nA
nA
MO
V

-

VN

-

dB
dB
MHz

B

TRANSFER CHARACTERISTICS
Large Signal Voltage Gain (Notes 1. 4)
Common Mode Rejection (Note 2)
Hold Mode Feedthrough Attenuation (Note 3)
Gain Bandwidth Product (Note 3)

-

-

-

-

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 1)
Oulput Current
Full Power Bandwidth (Notes 3. 4)
Oulput Resistance (D.C.)

-

-

±10
±15

-

-

-

-

100
0.15

-

V
mA
kHz

0

TRANSIENT RESPONSE
Rise Time (Notes 3. 5)
Overshoot (Notes 3. 5)
Slew Rale (Notes 3. 6)

-

3.5

75
25
5

100

-

-O.B

2.3
3.2
30
30
5
5

4
6

40

-

-

75
25
5

100
40

ns
%
VlJls

--

-0.8
20

mA
pA
V
V

-

2.3
3.2
30
30
5
5

4
6

-

-

0.1
7.5
10

1.0
10.0
20

3.5
2.5
-90

5.5
3.5

-

3.5

-

DIGITAL INPUT CHARACTERISTICS
Dlgilallnput Current (VIN = OV)
Digital Input Current (VIN = +5.0V)
Digital Input Voltage (Low)
Digital Input Voltage (High)

-

Full
Full
Full
Full

2.0

+250C
+250C
+250 C
+25 0C
+250 C
+250C
Full
Full
Full
+250 C

-

-

20
0.8

-

-

2.0

-

O.B

-

SAMPLE AND HOLD CHARACTERISTICS
Acquisition Time to 0.1 % 1 OV Step (Note 3)
Acquisition Time to 0.01 % 1 OV Step (Note 3)
Aperture Time (Note 9)
Effective Aperture Delay Time
Aperture Uncertainly
Drift Current (Notes 3. 7)
HAI-2420. HA4-2420
HAI-2425
HA3-2425.HA4P2425
Hold Step Error (Note 7)

-

-

10
-

10

20

-

3.5
2.5
-90

5.5
3.5

-

I.B

-

-

Jls
Jls
ns
ns
ns
pA
nA
nA
nA
mV

POWER SUPPLY CHARACTERISTICS
Supply Currenl (+)
Supply Current (-)
Power Supply Rejection
NOTES:

1. RL = 2kn.
2. VCM = ±10VDC.
3. AV = ±1. RL = 2kn. CL = 5OpF.

+25OC
+25OC
Full

-BO

4. Your = 20V peak-to-peak.
5. Your = 200mV peak-to-peak.
6. Your = 10.0V peak-to-peak.

5-4

-

-74

-

mA
mA
dB

7. VIN =OV.
B. ftN:s. 100kHz.
9.

Derived from computer simulation only; not tested.

HA-2420/2425
Performance Curves

VSUPPLY = ±15VDC, TA = +250C, CH = 1000pF Unless Otherwise Specified

TYPICAL SAMPLE AND HOLD PERFORMANCE
AS A FUNCTION OF HOLDING CAPACITOR

BROADBAND NOISE CHARACTERISTICS
1000

MINIMUM SAMPLE TIME
1000
~pRIFT DURING HDLD@

~~: ~'I~t;:~~e~~Z

250C MILLIVOLT/SEC

"'

100

UNITY GAIN PHASE
MARGIN: DEGREE'

r-~

10

-

1.0

OUTPUT NOISE
"HOLD"MODE

/
"

-.

:::;;;

/

~

./ MILLIVOLTS

"'

UNITY-GAIN
BANDWIDTH:
MHz

1=
r-

HOLD STEP
OFFSET ERR OR

/

./

100

EaUIVAL
T NOISE
"SAMPLE" MODE .- lOOK
SOURCE RESISTANCE

10

0:::-

.-::::
EQUIV.INPUT NOISE
"SAMPLE" MODE a
SOURCE RESISTANCE

'\.

IIIIIII

I

0.1

10

"-

" '"

I

100

"-

SLEW RATE/CHARGE
RATE: VOLTSI
MlfROSECON?

II

IK
10K
lOOK
BANDWIDTH
(LOWER 3dB FREQUENCY = 10Hz)

1M

...........

.01
10pF

100pF

1000pF

0.01 "F

CH VALUE

DRIFT CURRENT vs TEMPERATURE

OPEN LOOP FREQUENCY RESPONSE

1000

IDa

90

...z
III

/

~
w

60
50

g

40
30

V

100

~

,

~
_

15

~

" """
"

"' ~

"-.

o

-'

CH =100pF

Ow

Ow

z;:;:

:I: a:

TRANSFER CHARACTERISTICS

V
V

!1A
!1A

....I:;;

~

e

w'

1.5

ClI

,1.0,

CH = 100 pF

i!..J

0.1

CH = 1000 pF

...>w

0

1.0

ti
0

..J

-10 -8

-6 -4 -2

0
J:

2

4

6

8

0.5

10,

DC INPUT (VOLTS)

0.0
2

3

4

LOGIC LEVEL HIGH (VOLTS)

5-14

5

HA-5320

Test Circuits
CHARGE TRANSFER AND DRIFT CURRENT

- INPUT
2

Sill

OUTPUT

+ INPUT

Vo

8

N.C.

11

Sill CONTROL

CONTROL
INPUT

7

N.C.

HA-5320
(C H = l00pF)

CHARGE TRANSFER TEST

1.

1. Observe the voltage "droop", AVO/aT:

-

Sill CONTROL

2.

DRIFT CURRENT TEST

Observe the "hold step" voltage Vp:

Compute charge transfer:

-

HOLD (+3.5V)
SAMPLE (oV)

a "" VpCH

Sill CONTROL

-

-,---,

---I

2.

,---,- -

I-...J

ANALOG
MUXOR
SWITCH

10Vpp
100kHz

OUT

SINE WAVE

Sill

CONTROL
INPUT

TO

Feedthrough in dB = 20 Log

VOUT
VIN

VOUT = Voltsp _p • Hold Mode,
VIN = VolISp _p•

5-15

TO

N.C.

SUPPLY
COMMON

...r-'\..-

HOLD (+3.5V)

Measure the slope of the output during hold, aVO/aT,
and compute drift current: 10 "" CH aVO/aT.

HOLD MODE FEED THROUGH ATTENUATION

V IN

-

L - - SAMPLE (OV)

SIGNAL
GND

where:

N.C.

1-!7~_fO)

HA-5320
Glossary of Terms
EFFECTIVE APERTURE DELAY TIME (EAOT):

ACQUISITION TIME:

The time required following a "sample" command, for the The difference between the digital delay time from the Hold
output to reach its final value within ±0.1% or ±0.01%. This command to the opening of the S/H switch, and the propais the minimum sample time required to obtain a given . gation time from the analog input to the switch.
accuracy, and includes switch delay time, slewing time and
EADT may be positive, negative or zero. If zero, the 5/H
settling time.
amplifier will output a voltage equal to VIN at the instant the
Hold command was received. For negative EADT, the
CHARGE TRANSFER:
output in Hold (exclusive of pedestal and droop errors) will
The small charge transferred to the holding capacitor from
correspond to a value of VIN that occurred before the Hold
the inter-electrode capacitance of the switch when the unit
command.
is switched to the HOLD mode. Charge transfer Is directly
proportional to sample-to-hold offset pedestal error, where: APERTURE UNCERTAINTY:
Charge Transfer (pC) = CH (pF) x Offset Error (V)
APERTURE TIME:
The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is the interval
between the conditions of 10% open and 90% open.
HOLD STEP ERROR:
Hold Step Error is the output error due to Charge Transfer
(see above). It may be calculated from the specified parameter, Charge Transfer, using the. following relationship:
HOLD STEP (V) = CHARGE TRANSFER (pC)

The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay
Uncertainty, Aperture Time Jitter, etc.) sets a limit on the
accuracy with which a waveform can be reconstructed from
sample data.
DRIFT CURRENT:
The net leakage current from the hold capacitor during the
hold mode. Drift current can be calculated from the droop
rate using the formula:
10 (pA) = CH (PF) x

AV

(Volts/sec)

AT

HOLD CAPACITANCE (pF)
See Performance Curves.

Die Characteristics
Transistor Count .................................. 175
Ole Dimensions .................. 90.2 x 143.7 x 19 mils
Substrate Potential ......................... -VSUPPLY
Process .•.•.••..............•.........•.... Bipolar 01

Thermal Constants (CIW)
Ceramic DIP
CeramicLCC

5-16

Bja
75
76

9jc
15
19

m

HA-5330

HARRIS

Very High Speed Precision
Monolithic Sample and Hold

August 1991

Applications

Features
o

Very Fast Acquisition ••••••••••••••••• 350ns (0.1 %)
500ns (0.01 %)

• Low Droop Rate ......................... 0.01IN/JlS
• Very Low Offset ............................. 0.2mV

o Precision Data Acquisition Systems

• C/A Converter Ceglitching
• Auto-Zero Circuits
• Peak Detectors

• High Slew Rate ............................. 90VlJls
• Wide Supply Range .................. ±11V to ±18V
• Internal Hold Capacitor
• Fully Differential Input
• TTL/CMOS Compatible

Description
The HA-S330 is a very fast sample and hold amplifier
designed primarily for use with high speed ND converters. It
utilizes the Harris Dielectric Isolation process to achieve a
SOOns acquisition time to 12-bit accuracy and a droop rate of
0.01 JlV/Jls. The circuit consists of an input transconductance
amplifier capable of producing large amounts of charging
current, a low leakage analog switch, and an integrating
output stage which includes a 90pF hold capacitor.

VIN. Charge injection is held to a low value by compensation
circuits and, if necessary, the resulting O.SmV hold step
error can be adjusted to zero via the Offset Adjust terminals.
Compensation is also used to minimize leakage currents
which cause voltage droop in the Hold mode.

The analog switch operates into a virtual ground, so charge
injection on the hold capacitor is constant and independent of

The HA-S330 will operate at reduced supply voltages (to
±11 V) with a reduced signal range. This monolithic device
is available in a 14 pin Ceramic DIP and a 20 pad LCe
package. The MIL-STD-883 data sheet for this device is
available on request.

Pinouts

Functional Diagram

14 PIN CERAMIC DIP
TOP VIEW

OFFSET
ADJUST
,........A-.-.

3

+v

4

OFFSET ADJ. 3
OFFSET ADJ. 4

11 SUPPLY GND.

-IN

> ....-+7'-0 OUT

+IN

cONTI~~8~--~~-,
OUTPUT

7

8

SiH CONTROL
12

20 PAD (LCC)
TOP VIEW

SUPPLY
GND

-V

SIGNAL
GND

~ ~ ~ ~ ~
L~J LgJ t~J i?;.q: L1..9J
OFFSET ADJ.

~]

[ia

NC

~]

[f7 NC

SIGNAL GND.

OFFSET ADJ.

~]

[~6 SUPPLY GND.

NC

f]

[fs Ne
[f4 v+

v- ~]
rg1 rr~ f111 rr21

rr31

. CAUTION: Electronic devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

S-17

File Number

2858

en

c:
zu:;
 ___
HI..:7_ 0 OUT

+INv--r-...-

8JH 14
CONTROL~~----~

N.C.
6

ill

Buffer acts as a buffer in sample mode. acts as a closed switch in hold mode.

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyrighl @ Harris Corporation 1991

5-21

File Number

2859

Specifications HA-5340
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- Terminals ••..•••...••..•..•••• 36V
Differential Input Voltage .................................. 24V
Digital Input Voltage ................................ +8V. -6V
Output Current. Continuous ............................ ±20mA
Junction Temperature ................................ +1750 C

HA-5340-9 ............................. -40°C TA +850 C
HA-5340-5 ............................... OOC.s.TA + 75°C
Storage Temperature Range ............. -650C TA +1500 C

:s. :s.
:s.
:s. :s.

Electrical Specifications Test Conditions (Unless Otherwise Specified) VSUPPLY =±15.0V; CH =Internal =135pF; Digital Input:
VIL = +0.8V (Sample). VIH = +2.0V (Hold). Non-Inverting Unity Gain Configuration (Output tied to
-Input). RL 2K. CL 60pF

=

=

HA-5340-9
HA-5340-5
PARAMETER

TEMP

MIN

TYP

MAX

UNITS

Full

-10

-

+10

+25 0C
+25 0 C
+25 0 C
Full
Full
+25 0 C

-

1

-

V
Mn
pF
mV

INPUT CHARACTERISTICS
InpulVoltage Range
Input Resistance (Note 2)
Input Capacilance
Input Offset Voltage
Offsel Voltage Temperalure Coefficient
Bias Current

Full
+25 0 C
Full
Full
+250 C

Offset Current
Common Mode Range
CMRR (±1 0 Vdc)(Note 3)

-

-

±70

-

3
1.5
3.0
30

-

±350

±50

±350

-10

-

-

83

+10

-

-

-

140
10
9.6

-

mV
J1V/OC
nA
nA
nA
nA
V
dB
dB

Full

72

+250 C
Full
Full
Full

110

-

6.7

-

+250 C
+250 C
+250 C

-

20
35

30
50

40

60

-

Full
Full
Full
Full

2.0

-

-

7

0.8
40

f1A

-

4

40

J1A

Full
Full
Full
+250 C

-10
-10

-

-

+10
+10

Full

-

0.9
0.05
0.07

0.1
0.15

V
mA
MHz
n
n

+25 0 C
+25 0 C

-

325
325

400
400

"Vrms
J1Vrms

TRANSFER CHARACTERISTICS
Gain. DC
Gain Bandwidth Product CH External
CH External
CH External

=OpF
=100pF
=1000pF

-

dB
MHz
MHz
MHz

TRANSIENT RESPONSE
Rise Time
Overshoot
Slew Rate

(200mV step)
(200mV step)
(10Vstep)

ns
%

V/J1S

DIGITAL INPUT CHARACTERISTICS
Input Voltage (High).
Input Voltage (Low).
Input Current VIL
Input Current VIH

=OV
=5V

VIH
VIL
IlL
IIH

-

-

-

V
V

OUTPUT CHARACTERISTICS
Output Voltage
Output Current
Full Power Bandwidth (Slew Rate Limited) (Note 4)
Output Resistance - Hold Mode

0.6

-

-

TOTAL OUTPUT NOISE. D.C. TO 10MHz
Sample Mode
Hold Mode

5-22

-

Specifications HA-5340
Electrical Specifications Test Conditions (Unless Otherwise Specified) VSUPPLY = ±15.0V; CH = Internal = 135pF; Digital Input:
VIL = +0.8V (Sample), VIH = +2.0V (Hold). Non-Inverting Unity Gain Configuration (Output tied to
-Input), RL = 2K, CL = 60pF
HA-5340-9
HA-5340-5
PARAMETER

TEMP

MIN

TYP

VIN = 200kHz (20Vp-p)

Full

-

115

VIN =
VIN =
VIN =
VIN =

Full
Full
Full
Full

-90
-76
-70
-66

-100
-82
-74
-7S

Full

-78

-83

200kHz, SVp-p
200kHz, 10Vp-p

+2SoC
+2S0C

76
76

200kHz, SVp-p
200kHz, 10Vp-p
200kHz, 20Vp-p

+250C
+250C
+250 C

VIN = 100kHz, 5Vp-p
VIN = 100kHz, 10Vp-p
VIN = 100kHz, 20Vp-p

+25 0C
+2SoC
+250C

-

VIN= 20kHz, 5Vp-p
VIN= 50kHz, 5Vp-p
VIN = 100kHz, 5Vp-p

+250C
+250C
+250C

-

VIN=10Vp-p
(11 = 20kHz,I2 = 21 kHz)

MAX

UNITS

DISTORTION CHARACTERISTICS
SAMPLE MODE
Signal to Noise Ratio
(RMS Signal to RMS noise)
Total Harmonic Distortion

Intermodulation Distortion
VIN= 10Vp-p

(11 = 20kHz, 12 = 21 kHz)

HOLD MODE (50% Duty Cycle 5tH)
Signal 1o Noise Ratio
(RMS Signal 1o RMS noise)
Fs= 450kHz
VIN =
VIN =
Total Harmonic Distortion
Fs=4S0kHz
VIN =
VIN =
VIN =
Fs = 450kHz

Fs = 21IN(Nyquist)

Intermodulation Dislortlon
Fs = 450kHz

200kHz, 5Vp-p
200kHz, 10Vp-p
200kHz, 20Vp-p
SOOkHz, SVp-p

-72
-66
-56
-84
-71
-61

-

dB

-

dBc
dBc
dBc
dBc

-

dBc

-

-

dB
dB
dBc
dBc
dBc

-

dBc
dBc
dBc

-

-95
-91
-82

-

dBc
dBc
dBc

+250C

-

-79

-

dBc

+250C
Full
+250C
+2SoC
Full
+250C
Full
Full
+250C
+250C

-

-

700

-

-

900
600

ns
ns
ns
IlVlIlS
IlVlIlS
mV
ns
dB
ns
ns

SAMPLE/HOLD CHARACTERISTICS
Acqulsllion Time

1OV Step to 0.01 %
10VSleploO.l%

Droop Rate (CH = Inlernal)
Hold Step Error (VIL = OV, VIH = 4.0V,1r = 5ns)
Hold Mode Selliing Time (to :1:1 mV)
Hold Mode Feedthrough (20Vp-p, 200kHz, sine)
EADT (Effective Aperture Delay Time)
Aperture Uncertainly

-

430
0.1

-

15
200
-76
-15
0.2

300
95

POWER SUPPLY CHARACTERISTICS
Positive Supply Current
Negative Supply Current
PSRR (V or -V, 10% della)

Full
Full
Full

NOTES: 1. Absolute maximum ratings are limiting values, applied individual-

75

19
19
82

25
25

-

mA
mA
dB

Functional operation under any of these conditions is not neces-

2. Derived from Computer Simulation only. not tested.
3. +CMRR is measured from OV to +10V, -CMRR is measured from OV
to -10V

sarily Implied.

4. Based on the calculation FPBW

Iy,beyondwhichthosarvic:eabifityofthecircuitmayboimpaired.

5-23

= Slaw R.teJ2nVpeak (Vpe.k = 10V).

0
....

0

:c en
a:
0
w
z u:::


18
w 16
~
a: 14
0- 12
0 10
0
a: 8
Q
6 ~
4
2

"

ACQUISITION TIME (0.01%) vs. HOLD CAPACITANCE
2300

........
~

...So

.........

~

~ 1900

-""-........

I'!

........

~

1500

~

1300

1=

........

1250C~

f""..

.........

100°C

i'l
:J

........

........

75°C

~

10
100
EXTERNAL HOLD CAPACITOR (pF)

~~

L

~

1100

900
700

°

o
1000

5-26

~

/

:;::1 1700

:!-

1

.;

2100

--'

~

l/

000
1200
1600
EXTERNAL HOLD CAPACfTANCE (pF)

2000

HA-5340
Performance Curves

(Continued) Vs = ±15V, TA = +25 0 C, unless otherwise specified.
HOLD STEP ERROR vs. HOLD CAPACITANCE
TRiSE = 5ns; Temperature = +25 0C

HOLD STEP ERROR vs. TRISE
CH = Internal; Temperature = +250 C
13

14

12

13

11

12

~ 10

:;-

11

§.

10 ; - -

-

a: 9
8

rr
0

9

ffi 7
a. 6
w

rr

8

o

rr

Iii
9
~

~IH 3V

5

4
3

VIH

5

6

7

8

9

7

I-

I
I I

2
1

o

a:
w
a.
w

6

III
0

5

0

4

..J

J:

"

3
4J

1

10 11 12 13 14 15 16 17 18 19 20
TRISE (ns)

o

I

200 300 400 SOD 600 700 BOO 900 1000
EXTERNAL HOLD CAPACITANCE (pF)

20

~ 10

:;-

ffi

ffi
fu
Iii
9

§.
a:
oa:

a:
oa:
a.

0

oJ:

-1 0
-55

100

VIH,4V

HOLD STEP ERROR vs. TEMPERATURE
VIH = 4V, CH = Internal
t r=5ns, 10ns, 20n8

20

9

"

2

HOLD STEP ERROR vs. TEMPERATURE
VIH = 4V, CH = 470pF

~

-.

10

r-:.: ......

~

5no'f0 ~~ ~
.... ..

oJ:

-35 -15

0

25
50
75
TEMPERATURE (OC)

100

10ns
20ns

-10
- 55

125

5-27

-- - .

~
..... ~...

0

I
- 35

-15

0

75
25
SO
TEMPERATURE (OC)

~

--~

100

125

HA-5340
Performance Curves

(Continued) Vs = ±15V, TA = +250 C, unless otherwise specified.
CLOSED LOOP PHASE/GAIN

Av

= +100, ±15V and ±12V Supplies'

40

~

CO
::!.

"-

MAGNITUDE

UJ
Cl

:::> 20

'"

!::

z
C!J
«

:E

-

0

.. ~

10K

100K

UJ
0::

~

C!J
UJ

e.
UJ

..J

~

PHASE

I"""'~ ..

1K

en
UJ

1M

C!J
Z

«
UJ
(J)

~~

,

-

90 0

10M

• ±15V and ±12V supplies trace the same line within the width of the line, therefore only one line is shown.

5-28

:2

a.

HA-5340
Performance Curves

(Continued) Vs = ±15V, TA = +250 C, unless otherwise specified.
CLOSED LOOP PHASE/GAIN
AV = +100

40

~~

1il
~

CH

w
Cl

=

CH

=> 20

t:::

1000pF

=

470pF

CH

z
«

=

~

c>"' ~~

OpF

C!l

MAGNITUDE

~~,

1"'1~

:::E

0

W

w

a:

C!l

w

,

e.
w

0°

...J

C!l

~~

~

Ill~ ~
C H = 1000pF !J1'
CH

U)

90°

Z

«

w

(J')

PHASE

= 470PF~
C H = OpF

«

:r::

- 90 0

0..

", ~

0

-'

0",

~

Ie::

Ow

~~

- 180

0

w

~p

!""

I

-- -

c--

2.

z

~

20f---

'"

~
1(

----

CAScaDE CONFIGURATION
AMBIENT TEMPERATURE ITA )-2'·C
FREQUENCY (f) -IDa MHz

i
I

_-!-'
~Q

I

L>

~r--~sr~l-tt

t:::~~.•

9~
I I

f-i

I

~
w

8

~

7

10
. f - - - 1-0
10

,

2

4

,

FREQUENCY (fl - MHz

.

!

, ,

'J

100

10
II
12
DC COLLECTOR SUPPLY VOLTS ('tel

Fig lOb - Power gam vs. frequency (cascade configuratIOn) for

FIg. tOe - 100 MHz nOIse figure vs. collector supply volts (cascodo

CA3028A and CA30288.

configuratIOn) for CA3028A and CA30288

TYPICAL NOISE FIGURE AND POWER GAIN TEST CIRCUITS AND CHARACTERISTICS
r-~------~--~----~c
DIFFERENTIAL-AMPLIFIER CONFIGURATION
AMBIENT . TEMPERATURE (TA) ~25°C

40

J

:::--t.!:o" ,.,,J

35

II
I

2.

~

"
~
'"~

1(

A

(jpp

~t:-(>

I '
bot- VoLrs~

P

I

20

t"

'9

It::;;

,

2

FREQUENCY (f)- MHl

.

,

.

C«

,

,

, 10

Fig. lib - Power gain vs, flequency (dlfferential-amptlfler
configuratIOn) for CA3028A and CA30288.
5K

, t 0.7 MHz Power Gain Test Onty,
DIFFERENTIAL-AMPLifiER CONfIGURATION
AMBIENT TEMPERATURE (fA 1=2~·C
FREQUENCY (f)= IOQMHz
.

•
10

II

12

A

FOR POWER GAIN TEST
FOR NOISE FIGURE TEST

DC COLLECTOR SUPPLY VOLTS (Vec)

Fig. lIe - 100 MHz noise figure vs. col/ector supply voftage
(differential-amplifier configuration) for CA3028A and
CA30288

6-9

-'
«(I)
~ffi

wU::
0::::;
w C-

10

FOR POWER GAIN TEST
FOR NOISE FIGURE TEST

Fig. l1a - Power gain and noise figure test circuit (differentia/amplifier configuration and terminal No.7 connected
to Vee) for CA3028A, CA30288 and CA3053'.

)'~/e

15

10
it

Co Lec

30

Fig, lId - Power gain and noise figure test CIfCUIt (differentlafamplifier configuratIOn) for CA3028A and CA30288.

CA3028A,CA30288,CA3053

TYPICAL NOISE FIGURE AND POWER GAIN TEST CIRCUITS AND CHARACTERISTICS (Continued)

Fig. lIe - 100 MHz noise figure and power gain vs. base-toemitter bias (terminal No.7) for CA302BA and CA302BB.

TYPICAL ADMITTANCE PARAMETERS
DIFFERENTIAL-AMPLIFIER CONFIGURATION
AMBIENT TEMPERATURE ITA) =2S·C

CAscaDE CONFIGURATION

AMBIENT TEMPERATURE {TA l :25°C

~&t~~~~~ ~~rr~:M~~J~ WCfJ~;~ACH

STAGE COLLECTOR MILLIAMPERES [IC(STAGEI] =4,5

COLLECTOR SUPPLY VOLTS (VCC):+9

,.RANSIST(

"2.

7

~ ~ sl----+-+-+-H--t1-tt--+--t-H-t-tt*9
-~
=d 5,f-----+-t-~+i-H~--~_i--H-vtT~

~!

~i4

/

~~ 311----+-+-+-H-HH+-b-",,·~/'~/_t~H_j_tt~
8~

'Y

s~

/911

--+--+-I-+-bI41-1/
__tL-+-t-H-+++-H

~ ~

III-

6
8 10
2
FREQUENCY tf) - MHz

6

6 100

6

Fig. 12 - Input admittance (y,,) vs. frequency (cascode
configuration) for CA302BA, CA302BB and CA3053.

N

o

~I

[Ic

6

8 100

Fig. 13 -Input admittance (Y I1 ) vs. frequency (differentiafamplifier configuration) for CA302BA, CA302BB and
CA3053.

CASCaDE CONFIGURATION
AMBIENT TEMPERATURE ITA )=25°C

;~~~~CJ8~L:~r~YM~~il~p=;Rb

8 10

FREQUENCY tfl-MHl

DIFFERENTIAL-AMPLIFIER CONFIGURATION
AMBIENT TEMPERATURE (TA 1= 2~·C

~tti~~~~ ~Gk~E~Tfl 1(~~8~=t~ANSISTOR"2.2

TAGE] =45

20

t5;1----+-+-+H-HH-I--+-t--H-+~~

lo'f-----t-+--+-H_H-I-I--+-+-tri-l-'HH

~~ 5,f-----+-+--+-rt_H~~~~_i~~-rtTH
8~

g'2 _ /

ffi~ o'~---+--+-+-~~~~~~~~If-HttH
~~

b'2

.........

~~ ·*--_t-+_j_+tttTr-~-t-r-~~~il

: ~ -IO,f-----+-+--~rt_H_t_I--~_i-lH-t--~J_1
~~

~o _I
-

-:>C
6
8 10
FREQUENCY (f)-MHz

4

6

8 100

10

1

8 9100

FREQUENCY (fI-MHl

Fig. 14 - Reverse transadmittance (Y.. ) vs. frequency (cascode
configuration) for CA302BA, CA302BB and CA3053.

Fig. 15 - Reverse transadmittance (Y'2) vs. frequency
(differential-amplifier configuration) for CA302BA,
CA3028B and CA3053.

6-10

CA3028A,CA3028B,CA3053

TYPICAL ADMITTANCE PARAMETERS (Continued)
DIFFERENTIAL-AMPLIFIER CONFIGURATION
AMBIENT TEMPERATURE-ITA 1;25°C

COLLECTOR SUPPLY VOLTS'+9
COLLECTOR MILLIAMPERES, EACH TRANSISTOR

(Ie 1=2 2

'"

.~

~~20'~--r-+-~~tB--~~~-rrHit~-t-t-i
~~

~21

~ ~ 'O'~--r-+-~~tB--~~H*t9lit---"-"-t-t-i
81.",
~e

o'~--r-+-~~tB="'==-tr--~H-rrHit---t~-i

Ww

~ ~ -'or----r--+-t-titHt----tH--t+lCJitb"'f+tfH-rHHl
y

~

i
~

--'
en
«
;::: a:
w
:z ;:;:

~
~

w

a:
w

ii!

~ 02r-4-+-r+++~_H~~~--bfi-ttt-rHHl0.5 ~
/' V
~
~ O.I~++r+++tt1I-tI=*~P4-t++ttI-rHH1
§ 0
, 0
, , V
• 10

tL
tL

• 100

2

FREQUENCY (I)-MHz

Fig. 18- Output admiltance (y,,) vs. frequency (cascade
configuration) for CA3028A, CA3028B and CA3053.

Fig. 19 - Output admittance (Y,,) vs. frequency (dlfferentia/amp/lfler configuration) for CA3028A. CA3028B and
CA3053.

TYPICAL TEST CIRCUITS AND CHARACTERISTICS
OIFFERENTIAL-AMPLIFI ER CONFIGURATION
AMBIENT TEMPERATURE (TA )= 25-C
CONSTANT powER Ir.FUT z 2,..W

10,

Vee

.

50

.!.
Ie

0

20 10gl0 (A*) (2) (0.3)
VDIFF(RMS)

A "':" Sing Ie-ended voltage gain.

FIg. 24 - Common-mode rejectIOn ratio and common-mode

Fig. 23 - Differential voltage gain. maximum peak-to-peak output
voltage. and bandwidth test circuit for CA3028B.

rnput-voltage range test circUit lor CA3028B.

.....
 55°C Derate at:
5
6.67mWfC
Temperature Bange:
Operating ............ , -55 to + 125 -55 to + 1.25 °c
Storage . . . . . . . . . . . . .. -65 to + 150 -6~ to + 150°C

15
20
20
5
50

V
V
V
V
mA

-The collector of each transistor of the CA3049T and CA3102 Is
Isolated from the substrate by an Integral diode. The substrate
(terminal 9) must be connected to the most negative point in the

external circuit to maintain Isolation between transistors and to
provide for normal transistor action.

ELECTRICAL CHARACTERISTICS at TA = 25"C

CHARACTERISTICS

TEST CONDITIONS

SYMBOLS

TEST
CIR·
CUlT
FIG.

STATIC CHARACTERISTICS
For Each Differential Am liner
Input Offset Voltage

Input Offset Currant

Input BI.I Currant
Temperawre Coefficient Magnltude of Input-Offset Voltage
For Each Transistor
De Forward Base-toEmitter Voltage
Temperature Coefficient of
BaIG-to·Emltter Voltage
Collector-Cutoff Current
Collector-to-Emlner
Breakdown Voltage
Collec:tor-to·Base
Breakd~wn Voltage
Collector-to..substrate
Breakdown Voltage
Emltter-t~Ba.. Br.akdown
Voltage
DYNAMIC
CHARACTERISTICS
llf Noise Figure (For
Singl. Tran.istor)
Galn·Bandwldth Product
(For Single Transistor)

V8E

";iT
ICRO

~MAX. MIN.

VeE III 6 V
le"1 mA

674

774

I

TYP.

IMAX.

0.3
13.5

33

874

UNITS

mv

0.25

1.1

TYPICAL
CHARAC·
TERISTICS
CURVES
FIG.

-4

~A

33

~A

1.1

fjV/oC

4

774

mV

8

-I

-0.9

VCE .. 6 V, Ie - 1 mA

0.0013

VCB'" 10 V. Ie" 0

-0.9
0.0013

'00

en
~ Wa:
u::
a: ::;

mV/oC

Z

100

W

V(BR)CEO

IC" 1 rnA. IB" a

1.

24

lS

.4

v

V(BR)CBO

'C.-l0pA.le" 0

20

60

20

60

V

V(BR)CIO

IC"'0I'A"B -O.IE- 0

20

60

20

60

V

V(BR)EBO

IE

NF

fA looKHz,Rs - 500U
Ie'" 1 rnA

1••

'.S

dB

12

fT

VCE .. 6 V, Ie

1.35

1.35

GH,

11

0.28
0.15
1.65

0.28
0.28
1.65

pF
pF
pF

100
7.

100
7S

d8
d8

22

22

dB

23
4.6

23
4.6

d8
d8

:II

10 pA. IC

:II

:z

5 mA

ee8

IC'" 0

VCB" 5V

IC'" 0

VC,"SV

eMR
AGe

Input Admittance

V11

13"19- 2 rnA
Blal Voltage" -6V
81al VOltege - -4.2V
f- 10MHz
f- 200 MHz
Cascode
Cascade
VCC" 12V
For Cascod.
Cascod.
Configuration

A
Go
NF

V12

V.,
V2.

13""'9-2 rnA
For 0111.
Amplifier
Configuration
'3"'9- 4mA
(each
collector
Ic:=2mA)

W
LL

18

Diff.Amp.

1.5 + 12.45

1.5 + J 2.45

0.878+ 11.3

0.878 +

J 1.3

Cascode

O-IO.OOS

0-10.008

Olff.Amp.

0-10.013

0-) 0.013

J 30.7

Cascod.

17.9 -) 30.7

17.9 -

Dlff.Amp.
Ceacod.
01 .Amp.

- 10.5 +) 13
-O.60a-J 15
0.071 + I 0.62

- 10.5 + J 13
-0.603-) 15
0.071 + I 0.62

• Terminals 1 & 14 or 7 & 8. (CA3102) 1 & 12 or 6 & 7 (CA3049T)
•• Terminals 13 &4, or6 & 11. (CA3102) 10 & 11 or 4 & 5 (CA3049T)

6-15

9,10

14.16,18
mmho

15.17,19

mmho

mmho

26.28.30
27,29.31

rpmho

a..

:;;

LL
is ocs:

V

0

ee.

Output Admittance

TYP.

CA3049T LIMITS

0.25

-W-

4VSE

LIMITS

0.3
13.5

13-'g-2mA

Collector-Ba.. Capacitance

Forward Transfer Admittance

MIN.

V,O
'10
'.8
4VIO

Coliector·Substrate Capacitance
For Each Olff.rentlel
Amoll1l.r
Common-Mode Rejection Retlo
AGC Renge, One Stage
Voltage Gain. Single-Ended
Outout
I n.ertlon Powe, Gain
Noise Filiur.

Raver. Transfer Admittance

CA3102

20.22.24
21,23.25

CA3049, CA3102
V+(+6V)

+IV

IKn

IKfi

V- (-6V)

•• v---+-----------------+-----1

Fig. 7-Static characteristics test circuit for CA3 702

L1, L2 - Approx. 1/2 Turn #18 Tinned Copper Wire, 5/8" Dia.
C" C2 - 15 pF Variable Capacitors (Hammarlund, MAC·'5; or
Equivalent)
All Capacitors in p.F Unless Otherwise Indicated
All Resistors in Ohms Unless Otherwise Indicated
50Wl
-6V

Fig.2-AGC range and voltage gain test circuit for CA3102

Fig.3-200 MHz cascode power gain and noise figure test circuit.

Typical Characteristics for CA3049T and CA31 02
!I

. ·'r--,
I ,·
~ ·
··,

AMBIENT TEMPERATURE (T,). z5"'c

~::

104
~

,----

~

M
t:

L.
~

02

" I--

f""

. ..

,

,

EMITTER CURRENT

. ..

. .,

,

0,

-

"

~
~ '""", P'

;--

~.(.

,,'I

'I--- --:-. ",,'

~

IP
~

,

,

EMITTER CUflRENTI13.1gl-I!IA

1I3,~I-mA

Fig. 4-lnput offset voltage vs. emitter current

.

Fig. 5-lnput bias current vs. emitt.r current

, ,

>

jI 09

~

~
~
~

0'

*O.

i

f~~
.. '2.~C

~

A)l6\EMT TEMPERA.TURE

08

t==~~
~r-

08

,

..

r- ~ '-~
,

..

_

_

•

_

0

•

~

•

_

AIoIIBIENT TEMPERATURE (TAI-"C

ta..LECTOA MREHT tlel-mA

Fig. 6-Sase-to-emitter voltage vs. collector current

Fig. 7-Collector-cutoff current vso temperature.

6-16

CA3049, CA3102
Typical Characteristics for CA3049T and CA3102

(cont'd)

AMBIENT TEMPERATURE ITAI':!:!)'C
POSITIVE DC SUPPLY VOLTAGE tV+Io +6V

AMBIENT TEMPERATUREITA,·25·C

- r-f--t-t-Ht-- 15f---

1\
001

Fig. 8-Capacitance

VI.

Z

4

~ 801

2

4

II 8 I

2

4 6810

2

4

II

'Joo

FREOUENCYUl-NHI

DC BtAS VOLTAGE (VeJ-v

DC BLAS VOLTAGE ON TERt.lINALS 2 AND 10-\1

Fig. 10- Voltage gain vs. frequency.

Fig. 9- Voltage gain vs. de bias voltage.

de bias voltage.

"

-AMBIENTTEMPERATUREtTA'·25·C
30 RSOORCE·~on

AMBIENT TEMPERATURElTA '·25'C
RSOURCE'lKn

20

4

COLLECTOR CURRENT [Iel-mA

II

801

.'

/

- . -YJ.
-

'0;::::::-

,
 550 C •••.•••.•••••••••••••
TEMPERATURE RANGE:
Operating •••••.•••••••.•••••••••.•
Storage •••••••••••••••••.••••.••••

CA30S4
300
750
6.67

mW
mW
mWfOC

Oto+85
-6510+150

oC
oC

=250 C
The following ratings apply for each transistor in the device:
COLLECTOR-TO-EMITTER VOLTAGE, VCEO .•• 15
COLLECTOR-TO-BASEVOLTAGE, VCBO .••••• 20
COLLECTOR-TO-SUBSTRATEVOLTAGE, VCIO· 20
5
EMITIER-TO-BASEVOLTAGE,VEBO •.••.•••••
COLLECTOR CURRENT,IC •••••••••••.•••••.•. 50

V
V
V
V
mA

LEAD TEMPERATURE (During Soldering)
At distance 1/16 :I: 1/32 inch (1.59 :1:0.79 mm) from case for 10 seconds max •••••••••••••••••••••••••••••••.••.••••••..••••.•••• +2650 C
*The collector of each transistor of the CA3054 is isolated from the substrate by an
integral diode. The substrate must be connected fa a voltage which is more
negative than any collector voltage in order to maintain iso/aUon between

transistors and provide for normal transistor action. The substrate should be
maintained at signal (AC) ground by means of a suitable grounding capacitor, to
avoid undesired coupling between transistors.

Maximum Voltage Ratings
The following chart gives the range of voltages which can be applied to the terminals listed vertically with
respect to the terminals listed horizontally. For example, the voltage range between vertical terminal 2 and
horizontal terminal 4 is +1 5 to -5 volts.

-

CA3054
Terminal No.

l
13
14
1
2

3
4
6

7
8

9

13

14
0
-20

1

.
.

2

3

4

+5
-5

·

+15
-5

. ·

+20
0

·
·

+20
0
+20
0
+15
-5
+1
-5

6

7

8

9

11

· · · · ·
· · · · ·
· · · · ·
· · · · ·
· · · · ·
· · · · ·
0
-20

12

·

+15
-5

+20
0

+15
-5
-1
-5

11
12
5

lOUT
mA

13

5

0.1

+20
0

14

50

0.1

+20
0

1

50

0.1

2

5

0.1

3

5

0.1

4

0.1

50

6

5

0.1

+20
0

7

50

0.1

+20
0

8

50

0.1

9

5

0.1

11

5

0.1

12

0.1

50

·
·
·
·
·
·

·

Ref
Substrate

*Voltages are not nonnally applied between these terminals. Voltages appearing between these terminals wHI be safe if the
specified limits between all other terminals are not exceeded.

6-20

CA30S4
Terminal
No.-

liN
mA

· ·
·

·
·
· · ·
· · · ·
· ·
·
+5
-5

5

Maximum Current Ratings

• Terminal No.1 0 of CA3054 is not
used.

CA3054
ELECTRICAL CHARACTERISTICS at T A = 2Sa C

CH ARACTERISTIC.S

SYMBOLS

TEST CONDITIONS

TEST
CIRCUlT
FIG.

TYPICAL
CHARACTERISTICS
CURVES

CA30S4
LIMITS
MIN.

TYP.

MAX.

UNITS

FIG.

-

0.4S

S

mV

6

-

0.3

2

/lA

7

10

24

/lA

3

STATIC CHARACTERISTICS
For Each Differential Amplifier
Input Offset Voltage

VIO

Input Offset Current

'10
VCB = 3 V

Input Bias Current
QUiescent Operating
Current Rat I 0
Temperature Coefficient
Magnitude of Input-Offset Voltage
For Each Transistor
DC Forward Base-toEmitter Voltage
Temperature Coefficient of Baseto· Emitter Voltage
Collector-Cutoff Current

'C(Qll " 1C((5)

-0''C(Q:1l

IC(Q6)

-

IE(Q3tIE(Q4t2 rnA

16 VIOl
~

VBE

Ll.VBE
Ll.T
'CBO

0.98 to
1.02

3

l.l

\ IC =SO I,A
V B =3 V .
I rnA
C
3 rnA
.
\0 rnA

t

0.630
O.7IS
0.7S0
0.800

-

0.700
0.800
0.8S0
0.900

-1.9

VCB =3 V, IC:I rnA

0.002

Vcs=IOV,IE=O

100

/lV/oC

S

V

6

/lV 1°C

4

nA

2

Collector ·to· Emi tter
Breakdown Voltage

V(8R)CEO

IC =1 rnA, IB =0

-

IS

24

V

Collector-to-Base
Breakdown Voltage

V( BR)CBO

'c ~ 10/lA, 'E ~ 0

-

20

60

V

Co Ilector -to-Substrate
Breakdown Voltage

V( BR)CIO

'c ~ 10/lA, ICI ~ 0

-

20

60

V

Emltter-to-Base Breakdown Voltage

V(BR)EBO

'E~ 10/lA, 'c~O

-

S

7

V

8a

100

dB

8b

9a

7S

dB

9b

9a

32

dB

9b

IDa

IDS

dB

lOb

IDa

60

dB

lOb

DYNAMIC CHARACTERISTICS
Common-Mode Re,ectlon Rallo
For Each Amplifier

CMR

AGC Range, One Stage

AGC

Voltage Gain, Single Stage
Double-Ended Output
AGC Range, Two Stage
Voltage Gain, Two Stage
Double-Ended Output

A
AGC

VCC =12 V
VEE =-6 V
Vx =-3.3 V
f =1 kHz

A

Low-Frequency, Small-Signa I
EqUivalent-Circuit Characteristics:
(For Single Transistor)
Forward Current-Transfer Ratio

hfe

-

110

Short-Circuit Input Impedance

hie

-

3.S

lin

11

-

IS.6

jlmho

11

-

1.8 x 10- 4

Open-Circuit Output Impedance
Open-Circuit Reverse VoltageTransfer Ratio

hoe

f =1 kHz, VCE =3 V,

hre

IC =1 rnA

6-21

11

11

CA3054
DYNAMIC CHARACTERISTICS CONTrO.
1/1 Noise Figure
(For Sing Ie Transistor)

NF

I = 1 kHz, VCE = 3 V

-

Gain-Bandwidth Product
(For Single Transistor)

IT

VCE = 3 V, IC = 3 mA

-

Y21

VCB = 3 V
Each Collector
IC~ 1.25 mA
1= 1 MHz

-

3.25

.

dB

-

-

550

-

MHz

12

·20+jO

13a

0.22+jO.l

-

mmho

-

mmho

13b

-

O.OhjO

-

mmho

13c

mmho

13d

Admittance Characteristics;
Differential Circuit Conliguration:
(For Each Amplifier)
Forward Transler Admittance
Input Admittance

Yll

Output Admittance

Y22

Reverse Transfer Admittance

-

Yl?

-0.003 +jO

Admittance Characteristics;
Cascode Circuit Configuration:
(For Each Amplifier)
Forward Transler Admittance

Yll

Output Admittance

Y22

Reverse Transfer Admittance

Y12
NF

Noise Figure

-

VCB = 3 V
Total Stage
IC~ 2.5 mA
f = 1 MHz

Y21

Input Admittance

f = 100 MHz

mmho

14a

mmho

14b

0+jO.02

mmho

14c

0.004-jO.005

i-!flIho

14d

dB

-

G8·jO

-

0.55+jO

-

-

-

8

TYPICAL STATIC CHARACTERISTICS
IOZ~

EMITTER cuRRENT (IE)"O

<

..I

/.
//

2

10

~

B
6

:,'

<

..

'0

~v'b. ".,

2

u

o.:;.~ /'

~

0-

i:l
a:

•B
6

i?

u

2

"

o'~~/'/'

2

:l
0

2
10-3

'"a:

""v

.

~

i
iii
"'"

/'

B
6

10
6

4

0-

"~

25

50

75

100

/'

e

:>

2

o

!/

",,;

<
.0-<

2

OJ

/y/
.............
/

/'

OJ

viY/ ' / /
/' V/

<

<

!:!

~o

~ IO-~
:.! 6
u

-;.

~":///

10-

~
<

I::

lODe COLLECTOR-TO-BASE VOLTS (Vee)-3
6 AMBIENT TEMPERATURE {TA)=25°C

",""

<

a:

"u

~

2

V

V

./

.25

AMBIENT TEMPERATURE (TA )_·C ..

0,'

4

6

8

I

2

6

•• 0

COLLECTOR M.LLlAMPERES (rC)

• For CA30S4: use data from OOC to 8SoC only

F ig.2 - C ollector-to-base cutoll current vs ambienttemperature lor each transistor.

6-22

F ig.3 - Input bias current characteristic vs collector
current lor each transistor.

CA3054
TYPICAL STATIC CHARACTERISTICS
COLLECTOR-TO-BASE VOLTS (VCBI' 3

COLLECTOR-TO-BASE VOLTSIVCBl z3
4

EMITTER

0.9

UILLIAMPERES \1:£.'0\0
m

'"
~

;;; 0.8

~

g

o

ffi

::1

0.1

....
....
~ 0.6

~ 0.50

I

o

~

.

~

0.75

"....

0.\

o
Q25

0.5
0.4
-75

-SO

o

-25

25

50

o

(00

75

125

~

_

_

0

AMBIENT TEMPERATURE (TAI-IIIC'"

Fig.4 . Base·to·emitter voltage characteristic for each
transistor vs ambient temperature.

*

V>

!:;

>

~
....

"'"~
...'"

I

0.6

~

-0
3

~

t!

lJ

II:

IJ

2

I

~

0.5

INPUT OFFSET VOLTAGE=\\leEI
0..4
0.01

4

II

6 80.1

4

-~

.a
..lli

....

./

V

2

...'"...0 0.1•
.... 6

./

II>

t;

::>

~0
z

.....-

IL

4

H

V
2

z

fi'

0

4

II:

....

I

0

u

>
I

1/

•

6

:E

!:;

/

I

IL

0

V>

'"
'"

..'"

z

I

~

2

V>

0

VV

0

~

10. COLLECTOR-TO-BASE VOLTS lVeal =3
6 AMBIENT TEMPERATURE (TA I=25°C
4

E

~V

~

~

Fig.S - Offset voltage characteristic vs ambient temperature for clifferential pairs.

>

V

V

..

~

For CA3054: use data from OOC to 85°C only

08 COLLECTOR-TO-BASE VOUS (Vca)=3
AMBIENT TEMPERATURE (TA)=25"C

W 0.1

~

AMBIENT TEMPERATURE (TA)-"C ...

f-"'

0.01

6 8 I

0.01

4

6

8 0 •1

4

6

8 I

4

6 8 10

COLLECTOR MILLIAMPERES tIcl

EMITTER MILLIAMPERES lIE)

Fig.7 - Input offset current for matchecl clifferential
Fig.6 - Static base-to-emitter voltage characteristic ancl
pairs vs collector current.
input offset voltage for clifferential pairs vs emitter
current.
TYPICAL DYNAMIC CHARACTERISTICS
COMMON MODE REJECTION RA TIO

Vx Vee = +12V

POSITIVE DC SUPPLY VOLTS (Vccl = +12
NEGATIVE DC SUPPLY VOLTS (VEEI = -6
FREQUENCY (fl' I kHz

~ 110

I

lK 'T' 0.1

2

-LJl.F

~
z

~ 100

~

8
'oz" 90
'8"

lK

B

VEE= Vec=
-6V +12V

(a) Test setup

0.

Fig.S
6-23

-I

-2

DC BIAS VOLT ON TERMINAL

-3

® (VX)

(b) Characteristic

-4

CA3054
TYPICAL DYNAMIC CHARACTERISTICS (cont'd)

SINGLE-STAGE VOLTAGE GAIN
Vx vcc= +12V

POSITIVE DC SUPPLY VOLTS (Vcci • +12
NEGATIVE DC SUPPLY VOLTS (VEEI' -6 .
FREQUENCY (fl' kHz
SIGNAL INPUT
• 10 (rm,1

'1" 0.1

1K

CD

-LJl.F

i

3
z
~

0.1 J1.F '1"

VEE=

-L

VCC=

-W

+ 12V

-I

-2
DC BIAS VOLT ON TERMINAL

(a) Test setup

@ Me.)

(b) Characteristic

Fig.9

TWO-STAGE VOL TA;.:Gc.::Ec..:G:..;ACij:INiim:=-_ _ _ _ _ _...,..-,---===
1~F

POSITIVE DC SUPPLY VOLTS (Vcci • +12
NEGATIVE DC SUPPLY VOLTS (VEEI'-6
FREQUENCY (fl, I kHz
SIGNAL INPUT MILLIVOLTS· I (rm.)

+12V

ll!
~

U)

I

N

1~F

-I

-2

-3

-4

DC BIAS VOLTS ON TEAMINALS@AND

(0) Test setup

Fig.l0

-,

@ (Yxi

-6

(b) Characteristic

TYPICAL DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR'
100 COLLECTOA-TO-BASEVOLTS IVCB,'3
6 FREQUENCY (fl' I kHz
4 AMBIENT TEMPERATURE (TAl' 25"C

I
U)

a:

:;;"'

."
a:
;f

2110 ' - 8
S

t--......

.."'
N

hie '110

....

2
I
8
S
4

2

_

'hoe

/

"- "I">-

/

V

_hfe __

~ ....hrt.

...-

I--

//

0.1

-

.,-

~

/

V'
2

4

S 8

ru

COLLECTOR-TO-BASE VOLTS (VCB"S
AMBIENT TEMPERATURE (TA)-2S- C

}

r:......

4

:J

"aa:z

,

I II

hie =3.5 Kg
hre=I.88XIO-4 at ImA
hoe =15.6 J'mho

~

c

I

2

4

S 8 I

2

4

S 8

~

COLLECTOR MILLIAMPERES (ICI

o

Fig.l1 - Forward current-transfer ratio (hfe)' short-circuit
input impedance (hie); open-circuit output impedance
(hoe)' and open-circuit reverse voltage-transfer ratio
(h re ) vs collector current for each transistor.

6-24

2345678

10

COLLECTOR MILLIAMPERES IIcl

Fig.12 - Gain-bandwidth product (fT) vs collector
current.

CA3054
TYPICAL DYNAMIC CHARACTERISTICS FOR EACH DIFFERENTIAL AMPLIFIER
OlFFE_REN IAL CONFIGURA!ION
COLLECTOR-TO-BASE VOLTS Weel'"
COLLECTOR CURRENT IIel Of EACH TRANSISTOR =-1.25 mA

DIFFERENTIAL CONFIGURATION
COLLECTOR-TO-BASE VOLTS IYCBI-3
COLLECTOR CURRENT (Ie) OF EACH TRANSISTOR =:II 1.25 rnA
20 AMBIENT TEMPERATURE ITA)~25·

0:

0

-=.'"
NO

- ,.
~ ~
" ,.

-

5 AMBIENT TEMPERATURE (1A)"25-

0::<

o!!

-:.-'
10

S!
U

-

'"

N

" '"
'"ZU

17

",-

0:

~Z

L..-

b21

0

E=
-,.

'\

uu

~~

2

~g

/

-10

i!:g

~
~

:/f

-20
0.1

4

2

6

4

2

•

6 •

4

2

10

)l

I

921

0:

I

t::~

"''''
"'z

Z

U

./

a
6 •

2

lOa

468,

0.1

DIFfERENTIAL CONFIGURATION
COLLECTOR-TO-BASE VOLTS IVCBI-3
COLLECTOR CURRENT tIel OF EACH TRANSISTOR =-1.25 rnA
0.5 AMBIENT TEMPERATURE (TA)= 25-

U)

-'

0

~

'"UZ

:;;
2

1:!U

,

j

;

'"z

~ !
z

03

1'U!

b22/

"z

0

0.2

0
U

I

"
"

a.

I-

--"

a
46B,

0.1

4

468,0

o~

UE
",E
~,

1'a.!
'"g

(I)

Z

'"w~O.OOI

::J

a.

f--

I
6 6

I-

>

::J
0

2

6
4

6
4

2

2

QI2

V

W

U
Z

a.
10 w
U o

2

2

~~

~I
U)

.
Z

...J

0:

~w

I-

2

'"
'">w

0.1 ~
6
4

V

0.1

U)~

I

~

..
I-

6
4

-9(2

1/1:

'"O:OOOO~

0

100

6
4

6
4

N

Ii

100

2

Z

-

z

6
4

~b

0:

I-

1000

6
4

0.01

"

I-

U)

V ~22
1,/ / -,

01

0

4 6 8 10

b12/

::J
0
0.1
Zo

::J

J

....

..1;1

!

-

:<

N

0

V

10 DIFFERENTIAL CONFIGURATION
COLLECTOR-lO-BASE VOLTS (VCB)s3
COLLECTOR CURRENT (Ic) OF EACH
2
TRANSISTOR =:r 1.25 rnA
I AMBIENT TEMPERATURE (TAl: 25-

~

,.

rl

04

-

U)
0

II

:J

",

/ II

F ig.13(b) . Input admittance (Y 11).

Fig.13(a) - Forward transfer admittance (Y21) vs frequency.

0

/

FREQUENCY (f)-MH7.

FREQUENCY( f)-MHz

,.:<

IT

II

" =3

,/

0

0
0:

4

~I
z_

"....U

".... "
0
0:

I

U)

0

:<

<>

0:
2
0.01

4

6.

FREQUENCY (II-MHz

4 6.
2
4 68
2
2
10
100
FREQUENCY (II-MHz

4

6.

1000

Fig. 13(d) - Reverse transfer admittance (YI2) vs frequency.

Fig.13(c) - Output admittance (Y22) vs frequency.

TYPICAL DYNAMIC CHARACTERISTICS FOR EACH CASCODE AMPLIFI ER
CASCaDE CONFIGURATION

CASCODE CONFIGURATION
0:

0

~(I) BO
"'0

~

60

5~

z

I

40

0:<>

w~~ 20

:i~

~f!j

0

t--

g

-40
4

"',
z=

1\



1-'-

6 6 10

Ii

3

U'"
::J
o

Oz

z"

01-

2

OilA'
J...-'l1'

::JU

o.U)

4

T

'I

4

u_

I-W

~t--.

"6 6 I

~i

uo.

;o::J
(1)-20

4

/

--'

~I

. . U)

0.1

5

o'!!

~

"'I-

",U

rnA

U)

",,,,0

""

u-'

8@

6 AMBIENT TEMPERATURE ITA1" 25·C

AMBIENT TEMPERATURE (TA). 25·C

0",

~~

;~i~~c~~C:gT~S~U~~~~T(~Cc~~i.5

~~~~CJg~L:g;~S~~~:~/{~CC~~:.5 rnA

Z::J

I

V

2

6 6100 200

0.1

FREQUENCY ( f I - MHz

Fig.J4(a) - Forward transfer admittance (Y21)vS frequency.

6-25

-

-IV

-U)

4

6 •

2

4

"II
6 •

I
10
FREQUENCY (II-MHz

2

4

6 •

100 200

Fig.14(b) - Input admittance (Yll) vs frequency.



::

i:'-..

-2

"I
~

1.

I"---

4

'":J:
0

~

:>

!!

2 ::;

II

..J

u E

~

u-

"I

-4

w
~ -s

z'l

8 -8

l'!
z

uu

6
4

~

~~ 0.1
zw

I-

i;lo:

!;

~ -10

b22

0

L


w

0

0:

0

0.1

6

•

2

4

6 •

10
FREQUENCY (f)-MHz

2

4

6.

100

2

Fig.14(c). Output admittance (Y22)vS frequency.

/'

6
4

/v

2

V

6

4

nODI
4

IL
12

2

2

-12
2

QI2

0::00.01

I-

I-

L

2

I

0

rnA

AMBIENT TEMPERATURE (TAl" 2S·C

6
4

"ru
0;;
zOw
o:z
w-:::
2

4

6 8

2

4

6

a

10

2

4

6

a .

roo

200

FREQUENCY-MHz

Fig.14(d) - Reverse transfer admittance (Y 12) vs frequency.

6-26

ARRAYS
PAGE
SELECTION GUIDE ............................................................................ .

7-2

ARRAY DATA SHEETS
CA 3018, A

General-Purpose Transistor Array ................................................ .

7-5

CA 3039

Diode Array .................................................................... .

7-11

CA 3045

General-Purpose N-P-N Transistor Array ......................................... .

7-15

CA 3046

General-Purpose N-P-N Transistor Array ......................................... .

7-15

CA 3081

General-Purpose High-Current N-P-N Array ...................................... .

7-21

CA 3082

General-Purpose High-Current N-P-N Array ...................................... . 7-21

CA 3083

General-Purpose High-Current N-P-N Array ...................................... .

CA 3086

General-Purpose N-P-N Transistor Array ......................................... . 7-28

7-24

CA 3096, A, C

N-P-N/P-N-PTransistor Array ................................................... .

7-33

CA 3127

High-Frequency N-P-N Transistor Array .......................................... .

7-43

CA 3141

High-Voltage Diode Array ....•................................................... 7-48

CA 3146, A

High-Voltage Transistor Array .................................................... . 7-51

CA 3183, A

High-Voltage Transistor Array .................................................... .

7-51

CA 3227

High-Frequency N-P-N Transistor Array .......................................... .

7-58

CA 3246

High-Frequency N-P-N Transistor Array .......................................... .

7-58

7-1

en
> 300M Hz. 2 matched pairs :!:5mV
CA3081

General-Purpose n-p-n High-CurrentTransistors

16

20

Seven Common-Emitter
CA3082

16

20

Seven Common-Collector
15

CA3083

20

Five independent transistors.
01 and 02 matched: 110 (at 1 mAl 2.5~A maximum.
CA3066

Three Isolated Transistors plus a Differential Pair

15

20

40

50

14E,14F,
14M

20

16E,16F,
16M
14E,14M

IT> 550MHz typo Operation from DC to 120MHz
CA3127

Five Independent Transistors

15

20

40

IT> 1 GHz. Operation from DC to 500MHz.
CA3146

Three Transistors plus a Differential Pair

CA3146A

30

40

30

50

40

50

30

50

IT> 500MHz typo Operation from DC to 120MHz.
CA3183

Five High-Current Transistors

CA3183A

30

40

40

75

40

50

40

75

16E,16M

High-voltage versions of CA3083 Transistors
01 and 02 matched atl mA.
CA3227

Five Independent Transistors

8

12

40

20

16E,16M

20

14E,14M

IT ~ 3GHz typ. Operation from DC to 1.5GHz.
CA3246

Three Independent Transistors plus a Differential Pair

8

12

40

IT ~ 3GHz typ. Operation from DC to 1.5GHZ.
• See Packaging and Ordering Information in Section 12.

7-2

Selection Guide
TRANSISTOR ARRAYS

(Continued)

Electrical Characteristics at TA

= 25 0 C

Type

Pin Count
V(BR)
V(BR)
CEO
CBO
and
IC
hFE
(Mln.)V
(Min.) V
(Min •• )
(Max.)
Package
n-p-n/p-n-p n-p-n/p-n-p n-p-n/p-n-p n-p-n/p-n-p
Type'

Description

35/-40

45/-40

150/20

50/-10

CA3096A

35/-40

45/-40

150/20

50/-10

CA3096C

24/-24

30/-24

100/15

CA3096

Five Independent Transistors, 3 n-p-n, 2 p-n-p

16E,16M

50/-10
p-n-p

n-p-n

IVIO I= 5mV max.

5mVmax.

1110 I= 0.6 pA max.

0.25pAmax.

DIODE ARRAYS
Electrical Characteristics at TA = 250 C. Apply for each Diode

Type
CA3039

Description

V(BR)R
(Min.) V

IR
(Max.) "A

CD
(Typ.)pF

VF1- VF2
(Max.)mV

Pin Count
& Package
Type'

5

0.1

0.65

5(IF=1 rnA)

12T,14M

6 Individual

• Ultra-fast low-capacitance matched diodes
CA3141

10 High Reverse Breakdown Voltage Diodes

°°

30

0.1

0.3

0.55 (typ.
ea. diode pr.)

16E

• Low-noise performance
• Low-leakage current
C

Cl Six connected to form 3 common-cathode diode pairs.
Four connected to form 2 common-anode diode pairs.

S
«

* See Packaging and Ordering Information in Section 12.

a:

7-3

CA3018
CA3018A

mHARRIS

General-Purpose Transistor Arrays Range

August 1991

Features

Description

• Matched Monolithic General Purpose Transistors

The CA3018 and CA3018A consist of four general purpose
silicon n-p-n transistors on a common monolithic sub·
strate.

• HFE Matched ••.••••.•••••••••••••••••••••••• ±10%
• VBE Matched CA3018A ••••••.••••••••••••••• ±2mV
CA3018 ••••••••••••••••••••••• ±5mV
• Operation From DC to 120MHz
• Wide Operating Current Range
• CA3018A Performance Characteristics Controlled
from 10~A to 10mA
• Low Noise Figure •..•••.•.•••• 3.2dB Typical at 1KHz
• Full Military Temperature Range ••• -550C to +125 0 C

Applications
• Two Isolated Transistors and a Darlington-Con'
nected Transistor Pair for Low-Power Applications at
Frequencies from DC Through the VHF Range
• Custom Designed Differential Amplifiers

Two of the four transistors are connected in the Darlington
configuration. The substrate is connected to a separate
terminal for maximum flexibility.
The transistors of the CA3018 and the CA3018A are well
suited to a wide variety of applications in low-power sys·
tems in the DC through VHF range. They may be used as
discrete transistors in conventional circuits but in addition
they provide the advantages of close electrical and thermal
matching inherent in integrated circuit construction.
The CA3018A is similar to the CA301a but features tighter
control of current gain, leakage, and offset parameters
making it suitable for more critical applications requiring
premium performance.
Both devices are supplied in a 12-lead TO-5 style can
package (T suffix).

• Temperature Compensated Amplifiers
• See Application Note,ICAN-5296 "Application of the
CA3018 Integrated-Circuit Transistor Array" for
Suggested Applications

Pinout

Schematic
CA3018T,CA3018AT
12 LEAD METAL CAN
TOP VIEW

t3a...-"-.. . .----'~'
T

1

o

:"' 7 t.=02:
~
SUBSTRATE
010

FIGURE 1. SCHEMATIC FOR CA3018 AND CA3018A
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

7-5

File Number

338.1

CA3018, CA3018A
Maximum Ratings, Absalute-Maximum Values, at TA=2SoC
CA30lS

CA3018A

300
450

300
450

The following ratings apply for each transistor in the device:

CA3018
Collector-to-Emitter Voltage, VCEO· 15
Collector-to-Base Voltage, V CBO .. 20
Collector-to-Substrate Voltage, V CIO' 20
Emitter-to-Base Voltage, VEBO . . .
5
Collector Current, IC . . . . . • . . . .
50

Power Dissipation. P:
Anyone transistor . . . . . . . . .

Tota 1 pac kage . . . . . . . . . . . .

mW
mW

Derate at 5 mW JOC for T A> 85 0 C

CA3018A
15
V
30
V
40
V
5
V
50
mA

'The collector of each transistor of the CA3018 and CA3018A
is isolated from the substrate by an integral diode. The
substrate (terminal 10) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide fOT normal transistor action.

Temperature Range:

Operating . . . . . . . . . . . . . . . -55 to + 125 -55 to + 125 0 C
Storage . . . . . . . . . . . . . . . . . -65 to + 150 -65 to + 1500 C

LI:AD TEMPERATURE (During Soldering)
At distance 1/16 ± 1/32 inch (1.59 ± 0.79111111)
from case for 10 seconds max.

Characteristics apply for each transistor in the CA30l8 and CA30l8A as specified.
ELECTRICAL
CHARACTERISTICS
at TA = 25°C

SYMBOLS

CA3018A
LIMitS

CA3018
LIMITS

SPECIAL TEST CONDITIONS

Typ.

Max.

0.001

100

-

0.001

40

nA

2

5

-

See Curve

0.5

!lA

3

-

-

-

5

!lA

-

24

-

15

14

-

V

-

10

60

-

30

60

-

V

-

IE"IQuA,IC"O

5

7

-

5

7

-

V

-

V(BR)CIO

IC"IQuA.ICt"O

20

60

-

40

60

-

V

-

Coliector·to·Emltter
SatUlation Voltage

VCES

IB"lmA,I C"lOmA

-

0.23

-

-

0.23

0.5

V

-

Static Forward Current
Tmnsler Ratio (Note 1)

tC"UlnA
VCE"3V.) Ic, tmA
IC"IQuA

30

-

100
100
54

-

200

UIO
100
54

200

-

50
60
30

-

hFE

-

-

4

VCE"3V,ICI:IC2"lmA

0.9

0.97

-

0.9

0.97

-

-

4

hFED

VCE:3V { Ic: ImA
Ic:IOQuA

1500

5400

-

2000
1000

5400
2800

-

-

5

Base·to·Emiller Voltage

VBE

VCE:3V

0.800
0.900

V

6

Input Offset Voltage

rI

mV

6.8

Min.

STATIC CHARACTERISTICS
Collecl,,·Cutoff Currenl

ICBO

VCB"IOV,IE"O

-

Collector·Cutoff Current

ICEO

VCE "IOV.I B"O

-

See Curve

ColiectOl·Cutoff Current
Darlington Pair

ICEOD

VCE "IOV,I B"O

-

-

Collect,,·to·Emitter
Breakdown Voltage

V1BR)CEO

IC"loA.IB"O

15

Collector·te-Base
Breakdown Voltage

V(BR)CBO

Ic" IQuA.IE"O

Emilter·to·Base
Breakdown Voltage

V(BR)EBO

Collector·to·Substrate
Breakdown Voltage

f

Magnitude of Static·Beta Ratio
(Isolated Transist"s QI and Q2)
Slatic Forward Current Transfer

Ratio Darlington Pair
(Q3 & Q4)

Temperature Coefficient:

BE
.VBE~

-

-

~

Mm.

Typ.

Umts

CHARACTERISTICS
CURVES

Max.

-

-

0.715
0.800

-

0.600

-

0.715
0.800

VCE=3V,I E:lmA

-

0.48

5

-

0.48

2

-

·1.9

-

-

.I.g

-

-

IE:lmA
IE:IIlnA

Base·to·Emitter Voltage
QI,Q2

ItwBEI

-xr

VCE:3V,I E"lmA

Base (Q3~te-Emitter (Q4)
Voltage·Daolington Pair

VBED
(Vg•I)

VCE :3V

Temperature Coefficient:
Base·to·Emitter Voltage
Darlington Pair·Q3,Q4

ItwBEDI
M

VCE=3V,I E:lmA

IE:IIlnA
IE: ImA

~BEI·VBE21 VC C:·6V,VEE:-6V,
Temperature Coefficient:
tCI=IC1:lmA
Magnitude of tnput·Offset Voltage ~

-

1.10

1.46
1.32

1.60
1.50

4.4

-

-

4.4

-

10

-

-

10

-

1.46
1.31

7-6

-

-

Fi .

mV/
°c
V

mV/
°c
!lV/OC

7

9

10

-

CA3018, CA3018A
ELECTRICAL CHARACTERISTICS, (CONT'O)
DYNAMIC CHARACTERISTICS
f~1 KHz,VCE~3V,IC~10~

NF

Low Frequency Noise Figure

Source resistance=l Kn

-

-

3.25

-

3.25

-

dB

lI(b)

Low·FrequencY,Small·Signal
Equivalent-Gircuit
Characteristics:

Forward Current·Transfer Ratio

hfe

Shat·Circuit Input Impedance

hie

Open·Circuit Output Impedance

h..

Open-Circuit Reverse

hre

Voltage·Transfer Ratio

I

MkHz,VCE~3V ,IC~lmA

I
I

Admittance Characteristics:

Forward Transfer Admittance

Yre

Input Admittance

Vie

Output Admittance

Yoe

Reverse Transfer Admittance

Yre

f~IMHz,VCE~3V ,IC~lmA

I

-

110

-

-

110

12

3.5

Kil

12

15.6

-

3.5

-

-

-

-

-

15.6

-

I"ffiho

12

-

1.8x10-4

-

-

1.8x10-4

-

-

-

31·j1.5

-

-

3!·j1.5

-

0.3tjO.04
0.OOltjO.03

-

0.3tjO.04
0.00ltjO.03
See Curve

See Curve

12

mmho

13

mmho

14

mmho

15

mmho

16

Emitter·to·Base Capacilance

CEB

VEB~3V,IE~O

.

0.6

-

Coliector·to·Base Capacitance

CCB

VCB~3V,IC~O

-

0.58

-

-

0.58

-

pF

-

Vc i~3V,IC~O

-

2.8

-

-

2.8

-

pF

-

Gain·Bandwidth PrlXiuct

300

VCE~3V,IC~3mA

fT

Coliecta·to·Substrate Capacitance CCI

500

300

500

-

MHz

17

0.6

-

pF

NOTES:
1. Actual forcing current is via the emiHer for this lest

STATIC CHARACTERISTICS

I02~

EMITTER CURRENT (IE) =0

103a

4
2

'il

..I

"0
u

10

•

!:J

I.

I-

0

...z
0:
0:

::>

u

it
0

.,
~
0~Y- '/

4

u

2

0:

l:!

10-2

:::l
0

4

101
u

••
2

10""'

••

...

~'O"l//

0:
0:

~....'/V/

......

"-V

•

::>

l:! la'•
6
4

-'
-'

'//
~/ V

8

/

2

//

10- 2•

•
4

--

2

a

g/

~/
0.::17/
c.;

0:

101

",'0/7

~

2

U

4

IQ"'I

1f7

0

-':

4

I-

ifF

t:-

2

I.

0

ver) "//
/V/

17."

0'"

~
~

::>

u

f"O

::>

2

~ IO~
I4
z

~

10-g

4

13

..,'<-

2

••

'il
I

:-.,+

4

I-

102

~v'?>.

2

7-

2

//

6
4

~
a:

BASE CURRENT(IB)'O

4

/.

25

50

75

100

2

10- 3

125

--

~~/
I-"

a

25

50

75

100

'5

AMBIE:NT TEMPERATURE (TA)-OC

AMBIENT TEMPERATURE (TA )_·C

Fig.3 - Typical Callectar- To-Emmiter Cutoff Current

Fig.2 - Typical Collector- To-Base Cutoff Current vs
Ambient Temperature for Each Transistor.

Ambient Temperature for Each Transistor.

7-7

vs

a:

0

~~

I--

80

/

V

...

z~

'"
0

I~ V V
i

0

50

4

2

6 BO.l

4

2

6 B I

4

6

B

~J

V

5000

"'0
0: ....
0:",

.'"

60

0.01

Zz

li

70

6000

0:0:

~f

~~HhFE2lhFE2
hFEI

ii'"

I~

..",,,,-'"

I

V'

1

vf-

7000

ffic

110

'"

~
z

0: ..

1i O

3000

0:0:

.......

/

00

....

2000

'"

1000

~Q
........

COLLECTOR -TO-EMITTER VOLTS (VCE)' 3

.... 0:

AMBIENT TEMPERATURE (TA )=25°C ~

a

4

01

10

0.8 COLLECTOR-TO-EMITTER VOLTSIVCE)'3

,.-

AMBIENT TEMPERATURE (TA). 25°C

!
'"':i0

'"'"....

.'"
f'?
.'"'". as

/

2

I

<~~

~UT OfFSET VOLTAGE·\'IIa"1

I

2

4

1

3

0.9

..
..

;; 0.8

0
[jl

':i
o

':i0

....~

~ 0.7

....
i:l
I::0

4

a

0.6

~_

0.5

1

.

....

0
2

6 B I

2

'"
.ff'

>

~L

6 80.1

~
N

I

4

B 10

COLLECTOR-TO-EMITTER VOLTS (VCE) • 3

"cz

!:

2

6

I

V""-

04
O. I

4

0

~V

1

2

E

3

0.6

B I

Fig.5 - Typical Static Forwf!rd Current - '(ransfer Ratio
for Darlington-conne~ted Transisters Q3
and Q4 vs Emitter Current.
>

/"

>

6

EMITTER MILLIAMPERES (IE)

Fig.4 - Typical Static Forward Current- Transfer
Ratio and Beta Ratio for Transistors Q,
and Q2 vs Emitter Current.

0.7

"

V

EMITTER MILLIAMPERES lIE)

~

/

,/

V

G~ 4000
..J
co:

-...

/

~

ii'z

0.4

75

6 B 10

-50

a

-25

25

50

75

100

125

AMBIENT TEMPERATURE (TA)-OC

EMITTER MILLIAMPERES (IE)

Fig.6 - Typical Static Base-to-Emitter Voltage
Characteristic and Input Offset Voltage for
Q, and Q2 vs Emitter Current.

Fig.7 - Typical Base-To-Emitter Voltage Characteristic
for Each Transistor vs Ambient Temperature
1.7

COLLECTOR-TO-EMITTER VOLTS (VCE)'3
AMBIENT TEMPERATURE (TA)=25°C

COLLECTOR-TO-EMITTER VOLTS (VCE)=3

1.6
N

'"
'"
~
'"':i

EMITTER MILLIAMPERES

~

",0
~~

It..,
>-

1

ffi~

.... 0;

t:~

"'Iz....
"'<>

g
::1

/

1.5

~~

. ...

0.75

/'"

1.4

~C1

'...."

/'"

",

"0

~ 0.50

0.1

1.3

V V

o
025

0.1
~

_

~

0

~

~

~

00

V

V

/

V
68 1

6 8 10

EMITTER MILLIAMPERES (:tE)

~

AMBIENT TEMPERATURE (TA)-"C

Fig.8 - Typical Offset Voltage Characteristic vs
Ambient Temperature

Fig.9 - Typical Static Input Voltage Characteristic for
Darlington Pair (Q3 and Q4) vs
Emitter Current

7-8

CA3018, CA3018A
~

COLLECTOR-lO-EMITTER VOLTS (VCE':3

'"

~
0:

1f.
z

~Z
..J

~ 1.75

"'~ 1.50

Fig.10 - Typical Static Input Voltage Characteristic for
Darlington Pair (Q3 and Q4) vs
Ambient Temperature.

>

ffi

:: 1.25

illI
o

~

~ 0.75
-75

-50

o

-25

AMBIENT TEMPERATURE (TA)-"C

TYP.ICAL DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR
COLLECTOR-TO-EMITTER VOLTS (VCE)'3
SOURCE RESISTANCE OHMS (RS)·500
AMBIENT TEMPERATURE ITA!'25"C
20

~

I

15

'"

"'z
15

,

SOURCE RESISTANCE OHMS (RS)·IOOO
AMBIENT TEMPERATURE (TA)'25"C
20

...",1."

~\p

i'"

.{~

~o.;s

'""'"
ii:
'"

'"
"'"~
'"z
(g

~~

Ii-~~

10

5

~

./

~

.J!!..F~

8

8 0.1

0.01

/

/V

1,'}'fY

r--:::

J

COLLECTOR-TO-EMITTER VOLTS (VCE)'3

'I
-- ~~

15

~~~

10

5~

I

~oy

....

(,

",,1/

-

~~

r

../'

V"

/

J9- V

8

8 0.1

0.01

I

COLLECTOR MILLIAMPERES (IC)

COLLECTOR MILLIAMPERES (Ic)

Fig.11(b) - Noise Figure vs Collector Current, RS = 1 KO.
Fig. 11 (a) - Noise Figure vs Collector Current,
RS 500 O.

100 COLLECTOR-TO-EMITTER VOLTS (VCE)'3
6 FREQUENCY (f)'lkHz
4 AMBIENT TEMPERATURE (TA)- 25"C

=

"'
'".
'"

30 COLLECTOR-lO-EMITTER VOLTS (VCE)~3
SOURCE RESISTANCE OHMS (RS)'IOOOO
AMBIENT TEMPERATURE (TAI'25"C
25

'"
T

0:

'"'"
1f.
0:

~

0

20

'"
0:

"~

/

15

'"

t-...

1

0:
0

z

I/hoe

/

~

.........

,
I
B

•
4

,

10

I

}

hie "3.5 Kll
hre"'1.88xIO-4 at ImA
hoe =15.6,umho

....

4

:J

''""

II
I II

hl e '1I0

N

/

"''"i5
z

'-

10B ---6

I

....

,-

/

I........

..-

/
.~:
",~,.

.....

~

/

01 ".
0.01

2

4

6 B

0.1

2

4

6 B

I

2

4

6 B

COLLECTOR MILLIAMPERES (IC)

o
0.01

4

6

a

0.1

2

6

Fig. 12 • Forward Current-Transfer Ratio (h fe ), ShortCircuit Input Impedance (hie)' Open-Circuit
Output Impedance (hoe)' ana Open-Circuit
Reverse Voltage- Transfer Ratio (h re )
vs Collector Current

8

COLLECTOR MILLIAMPERES (Ic)

Fig.ll(c) - Noise Figure vs Collector Current,
RS 10 KO.

=

7-9

10

CA3018, CA3018A
TYPICAL DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR

~~~~'l-~~~~f~A~~~M\t:)~~,~PUT,

COMMON-EMITTER CIRCUIT, BASE INPUT,
AMBIENT TEMPERATURE ITA)=25'C
COLLECTOR-TO-EMITTER VOLTSIVCE)=3
COLLECTOR MILLlAMPERESUC)"

2i

4

~~

30

'J!

l;lx

COLLECTOR-TO-EMITTER VOLTSIVCE)=3
S CCLLECTCR MILLIAMPERES lIe)-1

'"

VIe

~~

r---

t:!:1§

-::&

~I

1'\

z-

"'.0

weJ!

~UJ'

0:"
0-0-

~O-lO

~~
~

0.1

2

•

6

a

2

•

6

a

I
10
FREQUENCY (I)-MHz

2

0-11.
:oW
11. 0
z'"
-:0

4

6

a

4

::3

:i •

~

~li:

6'"II:
0

,./

0.
0.,1

4

6 B I

4

6 8 10
FREQUENCY I 1)- MHz

/'
.....4

-

bre

""'"

0-

~~

~~

1/

II

~j-o.5

I

2
I

10.0

gl

I

0-:0

a

0.

o::l
~i

boa

j

6

Ore IS SMALL AT FREQUENCIES
LESS THAN 50.0. MHz

::&
w-

ZZ

8~

•

COMMCN-EMITTER CIRCUIT, BASE INPUT,
AMBIENT TEMPERATUREITA)=25'C
CCLLECTOR-TO-EMITTER VOLTS IVCE)-3
COLLECTOR MILLIAMPERES II ).1

0-3
0:ow 3
00
0- W

468

I
10.
FREQUENCY (1)- MHz

Fig.14 - Input Admittance (Y ie)

6

!!i
~l

f.468

0.1

COLLECTOR-TC-EMITTER VOLTS IVCE)=3
COLLECTCR MILLIAMPERES II )= I

5

./ /

L. V

0.
4

2

100

~':::~'l-~~~~~~Af~'liUI'iAr="2~Fic'NPUT,

'"0x

/

/0;.

I

Fig, J3 - Forward Transfer Admittance (Y fe)

-::&

/

2

'"

V

............

-2C

Zz
8~

'\

r-- .!t.

'

o~

4

.. .!!
0- 3
:ow
00

0:

0

b,.

O'd

........

g ;;l,20
0::&
zl
8_ 10

:i l;l

,

5

...... :J

-I

~~

,/

~~-1

~2i

goo

OJ

a:

2

4

68'00

68'0

4

68'00

FREQUENCY(f )-MHz

Fig, I!! - Output Admittance (Y oe)

Fig, J6 - Reverse Transfer Admittance (Y re )

eCLLEeTCR-TO-EMITTER VOLTS IVeE)-3
AMBIENT TEMPERATURE (TA)-e- c

4

678910.

CCLLECTCR MILLIAMPERES lIe)

Fig, J7 - Typical Gain-Bandwidth Product (f T ) vs
Collectcr Current

7-10

4

CA3039

mHARRIS

Diode Array

August 1991

Features

Description

• Six Matched Diodes on a Common Substrate

The CA3039 consists of six ultra-fast, low capacitance
diodes on a common monolithic substrate. Integrated
circuit construction assures excellent static and dynamic
matching of the diodes, making the array extremely useful
for a wide variety of applications in communication and
switching systems.

• Excellent Reverse Recovery Time ••••••• 1 ns Typical
• Matched Monolithic Construction - VF Matched
Within SmV
• Low Diode Capacitance - CD
VR = -2V

= O.6SpF Typical

at

Five of the diodes are independently accessible, the sixth
shares a common terminal with the substrate.

Applications
• Ultra-Fast Low-Capacitance Matched Diodes for
Applications in Communications and Switching
Systems
• Balanced Modulators or Demodulators
• Ring Modulators

For applications such as balanced modulators or ring
modulators where capacitive balance is Important, the
substrate should be returned to a DC potential which is
significantly more negative (with respect to the active
diodes) than the peak signal applied.
The CA3039 is available in a 12-lead TO-5 style can
package and in a 14-lead Small Outline package (M suffix).

• High Speed Diode Gates
• Analog Switches

Schematic

Pinouts
CA3039M
14 LEAD SMALL OUTLINE
TOP VIEW

rlh
~
@
~o @
@--"--.@
t

Os

SUBSTRATE
AND CASE
NC

NC
FIGURE 1. SCHEMATIC DIAGRAM FOR CA3039

CA3039
12 LEAD TO-5 STYLE CAN
TOP VIEW

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @) Harris Corporation 1991

7-11

File Number

343.1

CA3039
ABSOLUTE MAXIMUM RA TltoiGS at T A

= 25 °C
Peak Inverse Voltage, PIV for: 01- 05' ..

5V

°6 .....

0.5 V

Dissipation:
Anyone diode unit. . . . . • • . . . . .

100

mW

Total for device. • . . . • • . • . • . .

600

mW

Peak Diode-to-Substrate Voltage, Vm
for 01-05 (term. 1,4,5,8 or 12 to term. 10) +20, -1 V

For TA > 55 0 C ...... derate linearly 5.7 mW/oC

25

rnA

Operating. . . . . . . . . . . . . . . . .. - 55 to + 125 °C

Peak Recurrent Forward Current, If . . . •. 100

rnA

+ 1500 C

Peak Forward Surge Current, If (surge) .•. 100

rnA

OC Forward Current, IF . • . • . • . • . . • .•

Temperature Range:
Storage . . . . . . . . . . . . . . . . . .. - 65 to

LEAD TEMPERATURE (During Soldering)
At distance 1/16 ± 1/32 inch (1.59 ± O.79mm)
••••••••••.••.••.••••.•••.••••.•.•.. + 265

from case for 10 seconds max.

ELECTRICAL CHARACTERISTICS, at TA

= 25

0

0c

C

Characteristics apply for each cliocle unit, unless otherwise specifiecl.

LIMITS
CHARACTERISTICS

SYMBOLS

SPECIAL TEST CONDITIONS

CHARACTERISTIC
CURVES

MIN.

TYP.

MAX.

-

0.69
0.78
0.80
0.90

V
V
V
V

2

-

0.65
0.73
0.76
0.81

5

7

-

V

-

IR=-10j.LA

20

-

-

V

-

VF

IF=50j.LA
1 rnA
3 rnA
10 rnA

DC Reverse Breakdown Voltage

V(BR)R

IR=-IOj.LA

DC Reverse Breakdown Voltage
Between any Diode Unit and Substrate

V(BR)R

DC Forward Voltage Drop

UNITS

-

FIG.

DC Reverse (Leakage) Current

IR

VR = -4V

-

0.016

100

nA

3

DC Reverse (Leakage) Current
Between any Diode Unit and Substrate

IR

VR = -10 V

-

0.022

100

nA

4

IF = 1 rnA

-

0.5

5

mV

2

IF = 1 rnA

-

1

-

j.LV/oC

5

6 VF
-6T

IF = 1 rnA

-

-1.9

-

mViDC

6

DC Forward Voltage Drop for
Anode-ta-Substrate Diode (OS)

VF

IF = 1 rnA

-

0.65

-

V

-

Reverse Recovery Time

trr

IF = 10 rnA, IR = 10 rnA

.-

1

-

ns

-

Diode Resistance

RD

f = 1 kHz, IF" 1 rnA

25

30

45

n

7

Diode Capacitance

CD

VR =-2 V, IF =0

-

0.65

-

pF

8

VOl =+4 V, IF =0

-

3.2

-

PF

9

Magnitude of Diode Offset Voltage
(Difference in DC Forward Voltage
Drops of any Two Diode Units)

I

Temperature Coefficient of VF l - VF21
Temperature Coefficient of Forward Drop

Diode-ta-Substrate Capacitance

! VFl - VF2!
61VFl - VF21
6T

COl

7-12

CA3039

~l

AMBIENT TEMPERATURE ITA)'25"C

I

O.B

.1

"-

~

"'
!:i

g

~"I'O
f°l' ~

0.7

..
0:

;0

~

0

I

~"G

5

3
,I

1

~,,~

~Ol~ l~lS!rr'-l..°I

- -4

QOI

6 601

4

6 8 I

DC FORWARD MILLIAMPERES (IF)

~

"'~
0
:>

a

::i
..J

::l

t;;

t;;

0

w

g

0

c 0.4

•4

t:!

,.

0.18

lJl
0:

4

r:;

2

--

•

4

/
0.9

2 0 .8
~ 0.7

o

II:

-- r-r-------- - -

-50

-25

o

25

50

75

;

0.6

~
g

0.5
0.4
-75

125

100

-50

o

-25

Fig. 3 . DC reverse (leakage) current (diodes 1,2,3,4,5)
vs temperature

2

0:

2

~

..

'2

z

2

w

/

10

"'ww

FREQUENCY (t) =1 kHz

/

/

V

4

tlz

/

~

"'

i 1~:t===i===~=t~~==r===~t=ti===-l~===i=-l-~~

0.1

"'0:w
>
w

4

0:

g

125

100

AMBIENT TEMPERATURE ITA)'25"C

4

,."-

75

Fig. 6 • DC forward voltage drop (any diode) vs
temperature

1(10. DC REVERSE VOLTAGE IVR)'-IOV

4

50

25

AMBIENT TEMPERATURE (TA )_·C

AMBIENT TEMPERATURE (TA)-·C

~

125

100

Fig. 5 • Diode offset voltage (any diode) vs temperature

./

2

0.001
-75

75

50

"'

a: 0.01
u
•

a

25

~

•

w

o

-25

AMBIENT TEMPERATURE (TA)- °C

/

2

z
z

1:-.t.H
-50

/

4

(l

0.1

0.3
-75

0

II

•

0:

1:1-

DC FORWARD CURRENT (.IF) -lrnA

I.

"'w

It

0.7

~
~ 0.5

Q

I

2

::E 0.6

4V

2

Ii:

.

DC REVERSE VOLTAGE IVR)'

:>

"'
it
0

2

Fig. 2 • DC forward voltage drop (any diode) and diode
offset voltage vs DC forward current
10.

"'

,.

ri:;I

.,.Ii.

~

-=-

4

0.6

05

~

:>

-.jO~

V
..............

0:

u

L~'Y~

....... V

0

---

6

2

./

0.01
4

-75

2-1--' -

i-""

2

0.001

-50

-25

---r--

15

o

25

50

75

100

125

0.01

AMBIENT TEMPERATURE (TA)-OC

4

6

+-j-----601

4

6

a

I

4

6

DC FORWARD MILLIAMPERES I~F)

Fig. 7 • Diode resistance (any diode) vs DC
forward current

Fig. 4 - DC reverse (leakage) current between diodes
(1,2,3,4,5) and substrate vs temperature

7-13

e 10

CA3039
TYPICAL CHARACTERISTICS
AMBIENT TEMPERATURE (TA)=25"C
DC FORWARD CURRENT (rF) =0
6

AMBIENT TEMPERATURE (TA)-2S"C
DC FORWARD CURRENT (J:F)=O

6

~

I

:€
"'uz

;!

4

3

u

~

:J

2

"'o
Q
Q

o

1 2 3

4

DC REVERSE VOLTS (VR) ACROSS DIODE

o
I
2 3 4
DC REVERSE VOLTS (VR) BETWEEN TERMINALS 1,4, 5,8.0R 12
AND SUBSTRATE (TERMINAL 10)

Fig. 8 - Diode capacitance (diodes 7,2,3,4,5) vs
reverse voltage

Fig. 9 - Diode-to-substrate capacitance vs
reverse voltage

7-14

CA3045
CA3046

mHARRIS

General Purpose N-P-N
Transistor Arrays

August 1991

Features

Description

• Two Matched Transistors: VBE Matched ±SmV;
Input Offset Current 2J.lA Max at IC 1mA

=

• 5 General Purpose Monolithic Transistors
• Operation From DC to 120MHz
• Wide Operating Current Range
• Low Noise Figure ••••••••••••• 3.2dB Typical at 1KHz
• Full Military Temperature Range ••• -55 0 C to +125 0 C

Applications
• Three Isolated Transistors and One Differentially
Connected Transistor Pair for Low-Power Applica·
tions at Frequencies from DC through the VHF Range
• Custom Designed Differential Amplifiers
• Temperature compensated amplifiers

The CA3045 and CA3046 each consist of five general
purpose silicon n-p-n transistors on a common monolithic
substrate. Two of the transistors are internally connected to
form a differentially-connected pair.
The transistors of the CA3045 and CA3046 are well suited
to a wide variety of applications in low power systems in the
DC through VHF range. They may be used as discrete
transistors in conventional circuits. However, in addition,
they provide the very significant inherent integrated circuit
advantages of close electrical and thermal matching.
The CA3045 is supplied in a 14-lead dual-in-line hermetic
(welded-seal) ceramic package and the CA3045F in a 14lead dual-in-line hermetic (frit-seal) ceramic package.
The CA3046 is electrically identical to the CA3045 but is
supplied in a 14-lead dual-in-line plastic package (no
suffix) and in 14-lead Small Outline package (M suffix).

Packaging Information

• See Application Note, ICAN-5296 "Application of the
CA3018 Integrated-Circuit Transistor Array" for
Suggested Applications

Pinout

PACKAGE

SUFFIX CA3045 CA3046
,/

14-Lead Dual-In-Line Plastic

None

14-Lead Dual-In-Line Ceramic

None

,/

14-Lead Dual-In-Line Fril-Seal
Ceramic

F

,/

Chip

H

,/

14-Lead Small Outline

M

,/

Schematic Diagram
CA3045,CA3046
14 PIN PACKAGES
TOP VIEW

SUBSTRATE
DIFF.
PAIR

SUBSTRATE

FIGURE 1.

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

7-15

File Number

341.1

CA3045, CA3046
ABSOLUTE MAXIMUM RATINGS AT TA =25°C

CA3045
Each
Transistor

CA3046, CA3045F
Total
Package

Each
Transistor

Power Dissipation:
TA up to 55°C ....................... .

300

mW

750

mW/oC

Derate at 6.67

TA> 55°C ......................... .
TA up to 75°C

Total
Package

300

.......•................

mW

750

mW/oC

Derate at 8

TA> 75 0 C ............ : ............ ..
Coliector·to·Emitter Voltage, VCEO' ......... .

15

15

V

Coliector·to·Base Voltage, VCBO ............ .

70

20

V

Coliector·to·Substrate Voltage, Vcia * ........ .

20

20

V

Emitter·to·Base Voltage, VEBO ............. .

5

5

V

50

mA

Collector Current
Temperature Range:
Operating ........................ , ... .
Storage .............................. .
Lead Temperature (During Soldering):
At distance 1/16 ±1/32" (1.59 ±0.79 mm)
from case for 10 seconds max. . ........... .

50

* The

collector of each transistor of the CA3045 and
CA3046 is isolated from the substrate by an integral
diode. The substrate (terminal 13) must b~ connected

-55 to +125
-65 to +150

-55 to +125
-65 to +150

+265

+265

to the most nel1ative point in the external circuit to

maintain isolation between transistors and to provide
for normal transistor action.

ELECTRICA'L CHARACTERISTICS, at TA = 25°C
Characteristics apply for eoch transistor in the CA3045 and CA3046 as·specified.
LIMITS
CHARACTERISTICS

SYMBOLS

Type CA3045
Type CA3046

SPECIAL TEST CON DlTIONS
MIN.

TYP.

UNITS
MAX.

CHARAC·
TERISTIC
CURVES
FIG.

STATIC CHARACTERISTICS
Coliector·to·Base Breakdown Voltage
Collector·to·Ernitter Breakdown Voltage

V(BR1CBO

Ie = 101lA, IE = 0

20

60

V

VIRR1r.En

IC = I rnA, IR = 0

15

24

V

Collector·to·Substrate Breakdown Voltage

V(8R1CIO

IC = 101lA, ICI = 0

20

60

V

Ernitter·to·Base Breakdown Voltage

V(BR1EBO

IE = IOIIA, IC = 0

5

7

V

ICBO

VCB = 10 V, IE = 0

0.002

40

nA

2

Coliector·Cutoff Current

Coliector·Cutoff Current

ICED

VCE =IOV, IB=O

See curve

0.5

pA

3

Static Forward Current·Transfer Ratio
(Static Beta) (Note 1)

hFE

\ IC " 10 rnA
VCE " 3 V) IC " I rnA
tc " 10 J.lA

Input Offset Current for Matched Pair
QI and 02' 11101 - 11 02 1 (Note 1)
Base·to·Ernitter Voltage (Note 1)

VCE " 3 V, IC " I rnA

40

100
100
54
0.3

4
2

pA

5

V

6

VCE " 3 V{IE" I rnA
IE" 10 rnA

0.715
0.800

VCE

3 V, IC "I rnA

0.45

5

mV

6,8

VCE " 3 V, IC " I rnA

0.45

5

mV

6,8

t.VBE
~

VCE "3 V, IC " I rnA

-1.9

mVJlC

7

Vr.F~

IB = I rnA, Ie = 10 rnA

0.23

V

VCE =3V,IC=lrnA

1.1

pvJlc

VBE

Magnitude of Input Offset Voltage for Differ·
ential Pair IVBE I - vBE21 (Note 1)

=

Magnitude of Input Offset Voltage for Isolated

Transislors IVsrr. - VSE4 l

IVSE4 - VSES

vSE5 -

vs~ I(Note 1)

Temperature Coelficient of
Base·to·Emitter Voltage
Coliector·to·Emitter Saturation Voltage
Temperature Coefficient:
Magnitude of Input·Offset Voltage

It. vIOl

t.T

7-16

8

CA3045, CA3046
ELECTRICAL CHARACTERISTICS (Cont'd.)
DYNAMIC CHARACTERISTICS
Low·Frequency Noise Figure

NF

f = I kHz, VCE = 3 V, IC" 100}IA
Source Resislance = I kD

3.25

l
I

110

dB

9(b)

Low·Frequency, Small·Signal
Equivalent·Circuit Characlerisllcs:
Forward Current· Transfer Ratio

hfe

Short·Circuit Input Impedance

lire

Open·Circuit Output Impedance

hoe

Open·Circuit Reverse
Voltage. Transfer Ratio

f = I kHz, VCE = 3 V, IC " I rnA

hre

Admittance Characteristics:
Yfe
Vie

Output Admittance

Yoe

Reverse Transler Admittance

Y,.

Gain·Bandwidth Product

f = I MHz, VCE = 3 V, IC = I rnA

!

10

31·)1.5

11

0.3+jO.04

12

0.001 tjO.03

13
14

See curve
550

MHz

VEB = 3 V, IE = 0

0.6

pF

CCB

VCB = 3 V, IC = 0

0.58

pF

CCI

VCS = 3 V, IC = 0

2.8

pF

VCE =3V, IC =3mA

Emitter·to·Base Capacitance

fT
CEB

Collector·to·Base Capacitance
Collector·to·Substrate Capacitance

kD
}JJIlho

LBx10· 4

I

Forward Transfer Admittance
Input Admittance

3.5
15.6

300

15

NOTES:
1. Actual forcing current is via the emitter for this test

§a:

STA TIC CHARACTERISTICS
10 2 8

6

EMITTER CURRENT (IE) ,,0

10 38
6

4

':1
I

•
2

t:!

I.
6
4

u

...
...
"u""...0
"u

10'

g

10.2

Z

0:
0:

~
0~"Z

.,.

10-3

•

I-

4

10 8
6

'"'"::>

o"'~L

-<:

6

R-"

4

a

~~/

2

0""7/

115 1

g •

v

6

..............
/

//

4

6
u

V

6

4

2
10"4

2
10-3

25

50

75

100

125

.///

2
10" •

6
4

o

r::-?/

I.

!5
I-

~

'/.,

~

4

2

u
"-

'"

~

....'"
.,.0"";/

2

ti

d"l"/'//
./V/

2

2

::t

-

"'"V

4

:!

u

/

R-""lV/

...u 4•6
0

"8

",0

6

6

r

o,q,"///

•

•

«

,,:>'"

2

0:

10 2

.,..+
~v"" ,0.,

4

al

/,

2

//

6

"0

4

/.

2
10



001

6 B I

4

0.01

EMITTER MILLIAMPERES (IE)

08 COLLECTOR-lO-EMITTER VOLTS(VCE)::3
AMBIENT TEMPERATURE (TA)::25 C1 C

/

g

3

/

~

~

~

0

"'

:;
-'
iE

!:i
o

;;; O.B

ffi

'"'"

0.4
O. I

2

4

I

I

.../y

0.7

lI-

Ie
Ie
0

/

O.S

~UT OFFSET VOLTAGE

6 B 10

0.9

I-

iE

'"I
m

4

8 I

:ff'

>

2

l-

..ill

6

Fig.S - Typical input offset current for matchea
frons istor pair Q ,Q2 vs collector current.

'"~

V"'"

0.6

i!i
I-

4

COLLECTOR-lO-EMITTER VOLTS (VCE) ·3

~V

'"~

a 0.1

./

0.7

CD

~

6

COLLECTOR MILLIAMPERES (Ici

Fig.4 - Typical static forwara current-transfer ratio ana
beta ratio for transistors Q, ana Q2 vs emitter current.

W

.....

)--.-

Z

H

V

/

0.1
8

Ie
0
I-

V
60f----7I"'---I-t-++--t--I-t-H--+-+-+Ho.8
SOV
4

./

4

iE

CD

0.01

./

<.>

~ rof----l--+~V-++--+--f_+-H--~-+-+-+_I

;'":

8
6

~
0:

~

hFEI

V

I

'"::I!

~ ~ 8of==!=""I::=..J-I-+-:"./4--I--I-+f--If.----t-l-l--lO.9
~
V

1'!

2

'"'"0:

I-

!§6

4

<>H

I"~

~ 0.6

.,..
I-

I

::>

~

L&J

~

0.5

CD

2

6 BO.I

4

2

6 8 I

4

0.4

0
6 810

~

~

_

0.

~

~

~

~

~

AMBIENT TEMPERATURE (TAI-'C

EMITTER MILLIAMPERES(IE I

Fig.6 - Typical static base-to-emitter voltage characteristic ana input offset voltage for aifferential pair ana
pairea isolatea trans is tors vs emitter current.

Fig.7 - Typical base-to-emitter voltage characteristic
vs ambient temperature for each transistor.

COLLECTCR-TC-EMITTER VOLTS (VCEI'3

<>

COLLECTOR-TC-EMITTER VOLTS (YcEI'3
SOURCE RESISTANCE OHMS (RS)'500
AMBIENT TEMPERATURE (TAl'2S'C

4

~
.,

EMITTER

MILLIAMPERES (lEl· IO

20

...>?-"",

!:i

g

:;

!ll

·2

I

..J

::I!

I=i

~

15

'"0:
~

'"0
Ie
Ie

~~~

10

...,

I- o.~o

S

0.1

::>

0.25

°

-7~

S

-~O

-a

0

2~

~O

7~

10.0

~
,,-0:;:;

~~

::>

0,75

0#'7

o'l~

~ --..;:::

,/

/

/V

",

...........

-

.JQ....~"...

12~

0.01

AMBIENT TEMPERATURE (TAI-'C

F ig.8 - Typical input offset voltage characteristics for
aifferential pair ana pairea isolatea transistors
vs ambient temperature.

• 0.1

•

I

COLLECTOR MILLIAMPERES (lei

Fig.9(a) - Typical noise figure vs collector current.
7-18

CA3045, CA3046
DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR

J

COLLECTOR-TO-EMITTER VOLTS IVCE)-3
SOURCE RESISTANCE OHMS IRS)-IOOO
AMBIENT TEMPERATURE (TA}=25°C

20

'"'"=>
'"
'"'"0z

V

~o))
...

+,/
T 201---I---I--+-l-l---o,~~'--+--l-h'1

m

(.

'll

I

30 COLLECTOR-TO-EMITTER VOLTS IVCE)-3
SOURCE RESISTANCE OHMS IRS)-IOOOO
I ....
AMBIENT TEMPERATURE (TA)" 25°C
V
25r----~--~--~~----+_---+~~?-~

,;:,"'~

15

~~~'"
o.U
z'"
-::l

"""
.........

COLLECTOR-TO-EMITTER VOLTS IVCE)-3
COLLECTOR MiLLIAMPERES IIC)-I

...."':J
i;d
-:&

z-

'\

~tt;~~'f~~U"Jf~Af~'I,~UIi..:.r."~"i.c'NPUT.

'"0x

~J

I

.-

Fig.1I - Typical forward transfer admittance
vs frequency.

COLLECTOR-TO-EMITTER VOLTSIVCE)-3
6 COLLECTOR MILLIAMPERES IIc)-1

~ I 4

"

--

~e

tr"''''-20
4
4
6 •
6 •
2
0.1
I
COLLECTOR MILLIAMPERES (IC)

2

~~~~~~-~~~~f~A~I~~~''';':t.~~"~PUT.

'"

-

a

~~

Fig.IO . Typical normalized forward current-transfer
ratio, short-circuit input impedance, open-circuit
output impedance, and open-circuit reverse voltage-transfer ratio vs collector current.

~~

r-.....

20

51
hf e

......

._--

'If.
30

lix
g~

,-

0.01

,

B 0.1

;:!:§

V'

01

-......---~

40

J!
~~

I/h oe
I

~

0

~V

COMMON-EMITTER CIRCUIT. BASE INPUT.
AMBIENT TEMPERATURE ITA)=25"C
COLLECTOR-TO-EMITTER VOL TSIVCE)- 3
COLLECTOR MILLIAMPERESlIc)-1

~

N

V__

~

Fig.9(c} - Typical noise figure vs collector current.

II

hre=I.SSXIO-4 ot ImA
hoe =15.6I'mho

....

4

'":J

-110

hie: 3.5 Kn

/

,

COLLECTOR MILLIAMPERES IIc)

I I I

I

h,.

...V

001

Fig.9(b} - Typical noise figure vs col/ector current.

'"t-'"
'"
'"'"

~,,'17

Q

5~~~--~,-+
~7~~,--~~~~-+~

COLLECTOR MILLIAMPERES II C)

100 COLLECTOR-TO EMITTER VOLTS IVCE)-3
6 FRECUENCY (f) =I kHz
4 AMBIENT TEMPERATURE (TA)= 25°C

/ l/

"'~,'ff'/

/

468

I

2468

10

FREQUENCYIf)-MHz

4

6

a

100

Fig.13 - Typical output admittance vs frequency.

7-19

CA3045, CA3046
DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR
~~~~~~-wm~A~'~~~\r,,:I~~~·g'PUT.

COLLECTOR-TO-EMITTER VOLTS (VCEI'3
AMBIENT TEMPERATURE ITAI'25" C

COLLECTOR-TO-EMITTER VOLTS (VcEI-3
COLLECTOR MILLIAMPERES (I I-I

::

9re IS SMALL AT FREQUENCIES
LESS THAN 500 MHz

6 8 10

2

::
::

6 8 100

o

~REQUENCY(f )-MHz

Fig.14 - Typical reverse transfer admittance vs frequency.

3

4

7

8

9

10

COLLECTOR MILLIAMPERES IICI

Fig.IS - Typical gain-bandwidth product vs
collector current.

7-20

CA3081
CA3082

mHARRIS

General-Purpose High-Current N-P-N
Transistor Arrays

August 1991

Features

Description

• CA3081 - Common-Emitter Array

CA3081 and CA3082 consist of seven high-current (to
100mA) silicon n-p-n transistors on a common monolithic
substrate. The CA3081 is connected in a common-emitter
configuraticn and the CA3082 is connected in a commoncollector configuration.

• CA3082 - Common-Collector Array
• Directly Drive 7-Segment Incandescent Displays and
Light-Emitting-Diode (LED) Display
• 7 Transistors Permit a Wide Range of Applications in
Either a Common-Emitter (CA3081) or CommonCollector (CA3082) Configuration
• High IC •••••••••••••••••••••••••••••••• 1OOmA Max
• Low VCE Sat (at SOmA) •••••••••••••••••••• O.4V Typ

Applications
• Drivers for
~ Incandescent Display Devices
~ LED Displays
~ Relay Control
~ Thyristor Firing

The CA3081 and CA3082 are capable of directly driving
seven-segment displays, and light-emitting diode (LED)
displays. These types are also well-suited for a variety of
other drive applications, including relay control and thyristor
firing.
The CA3081 and CA3082 are supplied in a 16-lead Small
Outline package (M suffix), in a 16-lead dual-in-line plastic
package (no suffix), and in a 16-lead dual-in-line frit-seal
ceramic package (F suffix), which include a separate
substrate connection for maximum flexibility in circuit
design. Both types are also available in chip form.

Functional Diagrams
CA3081
COMMON-EMITTER CONFIGURATION

CA3082
COMMON-COLLECTOR CONFIGURATION

SUBSTRATE

SUBSTRATE

FIGURE 1. FUNCTIONAL DIAGRAMS OF TYPES CA3081 AND CA3082

CAUTION; These devices are sensitive to electrostatic discharge. Proper I.e. handling procedures should be followed.
Copyright @) HarriS Corporation 1991

7-21

File Number

480.1

CA3081, CA3082
MAXIMUM RATINGS, Absolute-Maximum Values at TA = 25°C
Power Dissipation:

mW
mW

Anyone transistor _..................•................. '. . . .
500
Total package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
750
Above 550 C ........................................ Derate linearly 6.67

mWtDC

Ambient Temperature Range:
Operating ................................................ -55 to +125
Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : . -65 to + 150
Lead Temperature (During Soldering):
At distance 1/16" ±1/32" (1.59 mm ±0_79 mm)
from case for 10 seconds max. . •••..•.•... _.......... _•.... _
The following ratings apply for each transistor in the device:

265

Collector-to-Emitter Voltage (V CEO) ........................... .

16

V

Collector-to-Base Voltage (V CBO) .............................. .

20

V

Collector-to-Substrate Voltage (V CIO) ~ ......................... .

20

V

Emitter-to-Base Voltage (V EBO ) ............................... .

5

V

Collector Current (I

cl ................ -...................... .

Base Current (I B) ........................................... .

• The collector of each transistor of the CA3081 and CA3082 is
isolated from the substrate by an integral diode. The substrate must
be connected to a voltage"which is more'negative than any collector
voltage in order to maintain isolation between transistors and

100

mA

20

mA

provide normal transistor action. To avoid undesired coupling
between transistors, the substrate terminal (5) should be maintained
at either DC or signal (AC) ground. A suitable bypass capacitor can
be used to establish a signal ground.

ELECTRICAL CHARACTERISTICS at TA = 25°C
For Equipment Design
LIMITS

TEST CONDITIONS

CHARACTERISTIC

Collector-to-Base Breakdown Voltage

Typ.
Char.
Curve
Fig. No.

SYMBOL

V(BR)CBO

Collector-to-Substrate Breakdown Voltage V(BR)CIO

IC = 500 MA, IE = 0
ICI

= 500 !lA, Ie = a

UNITS
Min.

Typ.

Max.

-

20

60

-

V

20

60

V

24
6.9

-

Collector-to-Emitter Breakdown Voltage

V(BR)CEO

IC= 1 mA,IB=O

-

16

Emitter-to-Base Breakdown Voltage

V(BR)EBO

IC= 500MA

-

5

DC Forward-Current Transfer Ratio

hFE

VCE=0.5V,lc,:,30mA

-

30

68

VCE = 0.8 V, IC = 50 mA

40

70

-

IC = 30 mA, IB = 1 mA

3

-

0.87

1.2

IC= 30mA,IB = 1 mA

-

0.5

4

-

0.27

IC = 50 mA, IB = 5 mA

0.4

0.7

0.4

0.8

-

10

MA

1

MA

Base-to-Emitter Saturation Voltage

VBE sat

V
V

V

Collector-to-Emitter Saturation Voltage:
CA3081, CA3082
CA3081

VCE sat

CA3082

IC = 50 mA, IB = 5 mA

4

-

Collector-Cutoff-Current

ICEO

VCE = 10 V, IB = 0

Collector-Cutoff Current

ICBO

VCB = 10 V, IE = 0

7-22

V

CA3081, CA3082
TYPICAL STATIC CHARACTERISTICS FOR EACH TRANSISTOR OF TYPES.CA3081 AND CA3082
100

~z

90

0:
....

BO

...

....
z'"

l ?rfc,\<{..~

"'0:-...

",~".~.;'I'
~"'~~

o:~

::Jo 70 I--

,

u....
0'"

0:0:

"
:z
~

60

u
0

50

1.0 SET DC FORWARO-CURRENT TRANSFER RATIO

COLLECTOR-TO-EMITTEj VaLl' rCEI'3

f--

;;:;

........ 1--'

~V

z

-

l:~O.8

a~
'-'
00

'0>

..'"

U)

0.7

~

---

B I

6 8 10

2

COLLECTOR MILLIAMPERES (I C I

•

O.B

0:

"
~-

ffi~O.6

/

'"$~ 0.4
0:>

1:?
u

'"-'-'
0

0

V

~

~
4

6

8

z

V

I

0

...
ti_o.8
"

II II

0:

"'0
a: •

..
"'

.... u
!:::2:0.6

J

....
'-'
~g

a:

•

6

Irl
-'
-'

0.2

0

u

2

~

~

2
• 100

Fig. 4-VCEsat vs. IC at TA = 250 C

"'~~"V
TYPICA.4--

I-~

Vp

1/

If

V

4
6
B 10
2
COLLECTOR MILLIAMPERES (Ic)

Fig. 5-VCEsat vs. IC at TA

TYPICAL READ-OUT DRIVER APPLICATIONS

4

6

•

= 700 C

--rI
L

OV~

LIGHT-EMITTING

I SEGMENT OF
INCANDESCENT DISPLAY
(RCA-DR2000 SERIES

DIODE (LEDI

RCA-40736R

OR EOUIVALENT)

FROM
DECODER

100

V V

0.4

1:?

a

10

/

",,,,

:.

V

COLLECTOR MILLIAMPERES (Ie)

lL

;::

./

1"'U'" ./

1-

0.2

u

1.2 SET DC FORWARD-CURRENT TRANSFER RATIO (hrE' 10
AMBIENT TEMPERATURE (TAl =70·C

II

z

0

~~

4

Fig. 3-VBEsat vs. IC

SET DC FORWARO·CURRENT TRANSFER RATIO (hF'E)= 10
AMBIENT TEMPERATURE ITA'=2S-C

.... '"

V

4
6
2
10
COLLECTOR MILLIAMPERES Uel

Fig. 2-hFE vs. IC

i;i

~

.........

0.6
6

/

15'::

IQ

4

V

0:

r-

40
0.1

IhrEI=1O - -

Q

~V
V

I

(TA)~25·C

....... 0,9
"
~~

..........

o·C

~

~ vi--'VV
".;

AMBIENT TEMPERATURE

1/1 CA30BI
(COMMON EMITTER I

-THE RESISTANCE FOR R IS DETERMINED BY THE RELATIONSHIP

Vp -VeE -VF(LEOJ

R'

I (LEDI

R=O FOR Vp=VBEfVF(LEOl

Fig_6-Schematic diagram showing one transistor of
the CA3081 driving one segment of an incandescent display_

WHERE: Vp~ ~L~~~~LSE

VF =~~r:'Af~Rd'~~Tt~{
DIODE

Fig.l-Schematic diagram showing one transistor of
the CA3082 driving a light-emitting diode
(LED).

7-23

100

(II

CA3083

HARRIS

General-Purpose High-Current N-P-N
Transistor Array

August 1991

Features

Description

• High IC •••••••••••••••••••••••••••••••• 100mA Max

The CA3083 Is a versatile array of five high-current (to
100mA) n-p-n transistors on a common monolithic
"Substrate. In addition, two of these transistors (Ql and 02)
are matched at low currents (i.e. 1 mAl for applications in
which offset parameters are of special importance.

• Low V CEsat (at SOmA) • • • • • • • • • • • • • • • • • • •• O.7V Max
• Matched Pair (01 and 02)
VIO (VBE Matched) •••••••••••••••••••••• :!:SmV Max
110 (at lmA) ••••••••••••••••••••••••••••• 2.SIlA Max
• S Independent Transistors Plus Separate Substrate
Connection

Applications
• Signal Processing and Switching Systems Operating
from DC to VHF

Independent connections for each transistor plus a
separate terminal for ·-the substrate permit maximum
flexibility In circuit design. The CA3083 is supplied in a
16-lead dual-in-line frit-seal ceramic package (F suffix), a
16-lead Small Outline package (M suffix), and a 16-lead
dual-in-Iine plastic package (no suffix). The CA3083 is also
available in chip form.

• Lamp and Relay Driver
• Differential Amplifier
• Temperature-Compensated Amplifier
• Thyristor Firing
~

See Application Note, ICAN-S296 "Application of the
CA3018 Circuit Transistor Array" for Suggested
Applications

Functional Diagram

"SUBSTRATE

FIGURE 1.

CAUTION: These devicea,are subject to electrostatic discharge. Pl"Oper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

7-24

File Number

481.1

CA3083
MAXIMUM RATINGS, Absolute-Maximum Values at T A = 250 C
Power Dissipation:
Anyone transistor _ _ _ _ _ _ _ _ ___ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ __ _ _ __ __ _ _ _ _ _ _
500
Total package _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
750
Above 55 0 C ________________________________________ Derate linearly 6_67

mW
mW
mWflC

Ambient Temperature Range:
Operating ________________________________________________ -55 to +125
Storage ___________________________________________________ -65 to +150
Lead Temperature (During Soldering):
At distance 1/16" ±1/32" (1.59 mm ±0_79 mm)
265

from case for 10 seconds max.

The following ratings apply for each transistor in the device:
Collector-to-Emitter Voltage (V CEO) - - - - - - - - - - - - - - - - - - - - - - - - - - - -

15

Collector-to-Base Voltage (V CBO) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

20

V

Collector-to-Substrate Voltage (V CIO )-- - - - - - - - - - - - - - - - - - - - - - - - - __

20

V

Emitter-to-Base Voltage IV EBO) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

5

Collector Current (lC) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Base Current (lB) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

100
20

V

V
mA
mA

II The collector of each transistor of the CA3083 is isolated from the substrate by an integral diode. The substrate
must b:! connected to a voltage which is more negative than any collector voltage in order to maintain isolation
between transistors and provide normal transistor action. To avoid undesired coupling between transistors, the
substrate terminal (51 should be maintained at either OC or signal (AC~ ground. A suitable bypass capacitor can
be used to establish a signal ground.

ELECTRICAL CHARACTERISTICS at TA = 250 C
For Equipment Design
TEST CONDITIONS
CHARACTERISTICS

SYMBOL

.

LIMITS

Typ_
Char_
Min_
Curve
Fig_ No_

Typ_

Max_

UNITS

For Each Transistor:
Collector-to-Base
Breakdown Voltage

V(BR)CBO

IC= 100llA, IE = 0

-

20

60

-

V

Col lector-to-Em itter
Breakdown Voltage

V(BR)CEO

IC= lmA,IB = 0

-

15

24

-

V

Collector-to-Substrate
Breakdown Voltage

V(BR)CIO

-

20

60

-

V

5

6_9

-

V

Emitter-to-Base

ICI = lOOIlA,lB = 0,
IE = 0

V(BR)EBO

IE = 500llA, IC = 0

Collector-Cutoff-Current

ICEO

VCE = 10V, IB = 0

Collector-Cutoff-Current

ICBO

VCB = 10V,I E = 0

DC Forward-Current
Transfer Ratio (Note 1)

hFE

VCE = 3V

Breakdown Voltage

IC= 10mA
IC= SOmA

2

Base-to-Emitter Voltage

V BE

VCE = 3V,IC= 10mA

3

Collector-to-Emitter
Saturation Voltage

VCE,at

IC = 50mA, IB ~ 5mA

4,5

Gain-Bandwidth
Product

fT

VCE = 3 V
IC= 10 rnA

-

-

40

76

-

40

75

-

0_65

0_74 0_85

V

0.40 0_70

V

10

IlA

1

IlA

-

450

7

-

1.2

5

mV

8

-

0_7

2_5

IlA

-

MHz

For Transistors 01 and 02 (As a Differential Amplifier!:
Absolute Input Offset
Voltage
Absolute Input Offset
Current

Iviol
VCE = 3V, IC = lmA

11101

NOTES:
1. Actual forcing current is via the emitter for this test

7-25

~
a:
a:


0:
j:!

f.~~".
~~'&'

0.5
468,
468,0
COLLECTOR MilLIAMPERES (Ie)

I SET DC FORWARD-CURRENT TRANSFER RATIO IhFE)'IO
AMBIENT TEMPERATURE (TA)'25'C

~~

0.6

III

z

Ii0:

0.7

ii

Fig.2- hFE vs Ie

52

II ~~~7
!,~~\l~

!:i

50 :;....-0.1

O.B

g

t'

--

VV~

L\

~t::-~

u
0

"';c.'-

"'

!.,

~ ,;' .... ~ V

~

0:

..-- -.....

~

v ,...

II II

0

I

"'
I:

<

I

1

>

!5
ti0:

~

JV

0:

ii

~ /

~~:+.'

1.2 SET DC FORWARD·CURRENTTRA~SFER RATIO IhFEI' 10
AMBIENT TEMPERATURE ITA I- 70D C

II

.."'b
u

0.2

'"0

L

~

oJ
oJ

u

/

0.6

0.4

a:
~

~

II

O.B

r- "'~~

"'III

->

•

0.9

III

~

V

0

>
z O.B

52

~"
a:

0.7

_f...--

r""'"

V

I,.-V

'"
l-

I-

i

6"'

0.6

III

0.5

~

..

/

V

2
6
10
COLLECTOR MILLIAMPERES lIe I

I SET DC FORWARD-CURRENT TRANSfER RATIO I hfE I : 10'
AMBIENT TEMPERATURE (TAl: 2SD C

Ii
a:

I-""

,."P\C~L I-~

or--

6
8 10
COLLECTOR MILLIAMPERES (Ici

-g

V

1

L

4
6
8 10
COLLECTOR MILLIAMPERES (leI

7-26

• • IDC

4

6

• IDC

CA3083
TYPICAL STATIC CHARACTERISTICS FOR DIFFERENTIAL AMPLIFIER
>

E
J

"

E
"'

.!:i'"
."'

..

6 COLLECTOR-TO- EMITTER VOLT~,IVCE I' 3 V
AMBIENT TEMPERATURE (TA)z 25°C

J.

/

4

0

>

on

3

,!.
::>
"-

2

/

tt0

/

I

~~~~i~io~~~~~~~i~~EER I~O~~~~~gE I- 3 v

4

Z

"'::> •
0:
0:

V

."'
9. •
.."'
..g 'V
u

~

I

.;"

6

"-

;!;

4

::>
oJ

CD

~

-

/'V

::>

~/

;!;

.."'3
.g

•
6

J

5

V

CD

0
0.1

6

8

I

2

COLLECTOR MILLIAMPERES (Ie)

•

0·1

10

•

4

• •

I

•

COLLECTOR MILLIAMPERES IICI

•

6

•

10

Fig.8- ',0 vs Ie (transistors 01 and Q2 as a differential
amplifier).

Fig.l- V I 0 vs Ie (transistors 01 and 02 as a differential
amplifier).

~

a:



'"a:~

'"z"

,0.,
~
00"Z /

",'"

"
......
~
u

2
a:
0 10- 2

~

0

u

B
6
4

2
10" B

g

aa:

/: V/

~Ij/

~

/"/

~f7

4)

2-

0,,"7/

=
-

CJ

4-

3

...,......-/ /

,,0,"'~7

6
4

10-1
B
6

12

/:
//

2

10- 28

6
4

6

4~7

2
10-4

o

-!i0"
~

4

0

",0
",r:..
r:..0'Y//

6
4

'/.,
'!7"

U>

.

-!i

g(~V/

:::>

I-

4

:Y'" 2
'"a: 10 6B
'"
"'z" 2
"...z 18

o'"///

0

2
Z 10-1
8

B
6

-0

~.

IB
6
4

:$=

102

~r:..'?J.

2

/

2

//

B
6
4

=

BASE CURRENT (Ie I ~O

10 38
6
4

/

2
10- 3

25

50

75

100

125

0

25

50

75

AMBIENT TEMPERATURE ITA)-·C

AMBIENT TEMPERATURE (TA )_·C

Fig.3- 'CEO vs TA ·

Fig.2-'CBO vs TA ·

7-29

100

15

CA3086

=

ELECTRICAL CHARACTERISTICS at TA 2So C
Typical Values Intended Only for Design Guidance
TEST CONDITIONS

CHARACTERISTICS

Typ.
Chara·
teristics
Curves
Fig. No.

SYMBOL

TYPICAL
VALUES

UNITS

IC= 10mA

4

10(1

IC = 10 /lA

4

54

IE = lmA

5

0.715

V

IE = 10mA

5

0.800

V

DC Forward·Current
Transfer Ratio

hFE

Base·to-Emitter Voltage

VBE

VBE Temperature Coefficient

Ll VBE/LlT

VCE = 3V.IC= lmA

6

Collector-to-Emitter
Saturation Voltage

VCEsat

IB = lmA, IC= 10mA

-

0.23

V

Noise Figure (low frequency)

NF

-

3.25

dB

VCE = 3V

VCE = 3V

f= lkHz,V CE = 3V,
IC= 100j.lA, RS= lk n

-1.9

mVtDC

Low-Frequency, Small-Signal
Equivalent-Circuit Characteristics:
Forward Current-Transfer Ratio

hfe

Short-Circuit Input Impedance

hie

7

100

-

7

3.5

kn

hoe

7

15.6

j.lmho

h re

7

Forward Transfer Admittance

Yfe

8

31 - jl.5

mmho

Input Admittance

Yie

9

0.3 + jO.04

mmho

Output Admittance

Yoe

10

0.001 + jO.03

mmho

Reverse Transfer Admittance

Yre

11

Open-Circuit Output Impedance
Open-Circuit Reverse-Voltage
Transfer Ratio

f = 1kHz, VCE = 3V, IC = lmA

1.8 X 10-4

-

Admittance Characteristics:

f= lMHz,V CE = 3V,IC= lmA

See Curve

-

Gain-Bandwidth Product

fT

VCE = 3V, IC = 3mA

Emitter-to-Base Capacitance

CEBO

VEB = 3V, IE = 0

-

0.6

pF

Collector-to-Base Capacitance

CCBO

VCB = 3V,IC= 0

-

0.58

pF

Collector-to-Substrate Capacitance

CCIO

VCI = 3V,IC= 0

-

2.8

pF

7-30

12

550

MHz

CA3086
TYPICAL STATIC CHARACTERISTICS FOR EACH TRANSISTOR

120 COLLECTOR-lO-EMITTER VOLTS(VCE)=3

0.8 COLLECTOR -TO-EMITTER VOLTSCVCE'.3
AMBIENT TEMPERATURE (TA)- 2S·C -

AMBIENT TEMPERATURE (TA"25"C

'"~
~
'"'"

l-

liD

~

100

I-

~ ~ 90

va

;!'"
v

"

~

S
a
>

...or

0.6

,/"

V'"

I-

V

~I

1/

70

60

0.7

CD

on

l-

80

a:

I?

W
2:

/

gj=

./

,/"

/

z_

~~

i'-

a

';"

k,/

lJl

V

50
0,01

2

•

0.5

'"

ID

6 S0.1
4
6 SI
2
2
EMITTER MILLIAMPERES (IE'

•

0.4
01

6 S 10

2

4

6 801

COLLECTOR - TO- BASE VOLTSIVea) =3

0.9

II:

0.7

~

I-

~ 0.6
I
a
';
w 0.5
~
ID

0.4
75

2

4

6 SI

EMITTER MILlIAMPERES(I.E)

-50

-25

o

25

50

75

AMBIENT TEMPERATURE (TA) _·C

7-31

100

125

2

4

6 SID

CA3086
CCMMON-EMITTER CIRCUIT. BASE INPUT
AMBIENT TEMPERATURE (TAl- 2S"C
COLLECTOR-TO-EMITTER VOLTS(VCEI-3
COLLECTOR MILlIAMPEREslIcl"

ICC

• ~~~~~~~:i~~:,~~:TTER VCLTsIVCE"3

4 AMBIENT TEMPERATURE (TAl- 25°C

I
UI

2r--

0:

'"....

..'"'"

10.

-

••

0:

If

h,.'

r--...

....

rs..

4

0

~

2

.

N

-

I

'z" ••
0:
0

4

'"

/'"

2

I II

I

i"o~

30
"';!
u-,

I--

Z

8!

..

.~-

"'u
IL",

r-..;>"rt.

Zo«
..
0:",

"'

20

I"
--

10
O

r--

.... 0
0"

~

~~ -10

3'0

2

4

••

4

0.1
6 e I
CCLLECTCR MILLIAMPERES IICI

4

6

8 10

0.1

2

4

68,

.,

UI

00

S

b,.

i;d

;;; 2: 4

ul
z-

j

~E

6

.. u

I

a

L.468

46B

4

I
10
FREQUENCY (f)- MHz

4

::>0
....'
"
"

./ V

0

~

0«
0:;:

;-

ZUI

-::>

S

=>'"
00
zZ

/

2

1~

~J
u-

(ftie

0 ..

x

.. =1
-,.
I

Z-

7

u=>'" 3
Ou
Zz

••

Ul•

..'"

0

boe

3

/

1/

I

./

0
4

6

e

I
4 6 8'0
FREQUENCY ( f l - MHz

Fig. 10- Voe

VS

---

4

f.

~~~m-~~I~~f~A~~~~I'~:I~~~"~PUT
COLLECTCR-TO-EMITTER VOLTS (VCEI'3
COLLECTCR MILLIAMPERES II 1"

r~

are

~~

'"

IS SMALL AT FREQUENCIES
LESS THAN SOO MHz

-

0

~i

br•

I~-o

'"

u-

ffi~

ffii~ -I
iii"
0:'"
....
u
~~-I.S
0:0

!l!z

","
0:

-2
6

B

10
FREQUENCY(f I-MHz

6

8

o

100

3

4

7

7-32

10.

9

COLLECTOR MILLIAMPERES

IIel

V
goo

/

0.1

100

I
I

2

Fig.9- Vie vs f.

~:J'

2

0

-~~

0.1

6 B,OO

COLLECTOR-TO-EMITTER VOlTS (VCEI'3
COLLECTOR MILLIAMPERES (lei' I

CCLLECTCR-TC-EMITTER VCLTSlvCEI'3

'"

"

FREQUENCY (f)-MHz

1~~~71:~~ ~~~~~AT~~'EUIrAr.~~~c'NPUT

~~~~~-~~~~f~A~I~~~\t~~~g"~PUT

u ....
......
=>'"

V

468,0

Fig.8- Vfe vs f.

6 CCLLECTOR MILLIAMPERES IIcl"

"'"

t-.......

~ct-20
2

Fig.7- Normalized hfe- hie' hoe' h re vSIC '

zx

'\
~

0:",

0.1 , /

I-- - -

........

•

0:",

--

r---.

Z-'

~i

II

7

--f-

III.

gX

gl
0_

/

0.0.1

4

..,:g

I~O'
I

~

'":::i

I

ICC
}
hie"3.5kn
hre a '.88 X 'O-4 at ImA
hoeal5.6l'1-mho

••

100

((I

HARRIS

CA3096,CA3096A
CA3096C
N-P-N/P-N-P Transistor Arrays

August 1991

Applications

CA3096A,CA309~CA3096C

• Five-Independent Transistors
~ Three N-P-N and
• Two P-N-P

Essential Differences
CHARACTERISTIC

• Differential Amplifiers

35

35

24

-40

-24

Min.
n-p-n

45

45

30

p-n-p

-40

-40

-24

V(BR)CBO (V)

hFE@lrnA

• Lamp and Relay Drivers
• Thyristor Firing Circuits

• Operational Amplifiers

ICBo(nA)

Description
The CA3096C, CA3096, and CA3096A are general
purpose high-voltage silicon transistor arrays. Each array
consists of five independent transistors (two p-n-p and
three n-p-n types) on a common substrate, which has a
separate connection. Independent connections for each
transistor permit maximum flexibility in circuit design.

ICEo(nA)

150-500

150-500

100-670

20-200

20-200

15-200

p-n-p

40-250

40-250

30-300

Max.
n-p-n

40

100

100

p-n-p

-40

-100

-100

Max.
n-p-n

100

1000

1000

p-n-p

-100

-1000

-1000

Max.
n-p-n

VCE(SAT) (V)
IVIOi(rnV)

Types CA3096A, CA3096, and CA3096C are identical,
except that the CA3096A specifications include parameter
matching and greater stringency in ICBO, ICEO, and
VCE(SAT). The CA3096C is a relaxed version of the
CA3096.
. The CA3096C, CA3096, and CA3096A are supplied in
l6-lead dual-in-line plastic packages (E-suffix), and in
16- lead Small Outline packages (M suffix). The CA3096 is
also available in chip form (H suffix).
CA3096,CA3096A,CA3096C
16 PIN PACKAGES
TOP VIEW

n-p-n
p-n-p
hFE@100j1A

• Temperature-Compensated Amplifiers

Pinout

CA3096C

-40

• Level Shifters
• Timers

CA3096

p-n-p

• DC Amplifiers
• Sense Amplifiers

CA3096A

V(BR)CEO (V) Min.
n-p-n

0.5

0.7

0.7

Max.
n-p-n

5

-

-

p-n-p

5

11101(pA) Max.
n-p-n

0.6

p-n-p

0.25

-

-

-

Schematic Diagram

SUBSTRATE

~ SUBSTRATE

FIGURE 1.

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

7-33

File Number

595.1

CA309aCA3096A, CA3096C
MAXIMUM RATINGS. Absolute-Maximum Values:

COLLECTOR-TO-EMITTER VOLTAGE. V CEO :
CA3096A ,CA3096 , , . . . ,
CA3096C
, • . , , . . . •
COLLECTOR-TO-BASE VOLTAGE, V CBO :
CA3096A ,CA3096 . , , . , ,
CA3096C
. , , , . . . , .
COLLECTOR-TO-SUBSTRATE VOLTAGE, VCIO:
CA3096A • CA3096 . . . . • • .
CA3096C
. • . . , . . , . .
EMITTER-TO-SUBSTRATE VOLTAGE. VEIO:
CA3096A • CA3096 . . • , .
• . . • . . . .
CA3096C
EMITTER-TO-BASE VOLTAGE. V EBO :
CA3096A ,CA3096 . . . . .
CA3096C
. . • . . • . .
COLLECTOR CURRENT. IC (All Types)
POWER DISSIPA110N. Po:
Up to T A = 55 C:
Device (Total) . . , . . .

Each Transistor.

.

.

.

.

EACH

EACH

N-P-N

P-N-P

35
24

-40
-24

V
V

45
30

-40
-24

V
V

45
30

-40

6
6
50

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

V
V

-40
-24
-10

V
V
rnA

rnW
rnW
rnW/oC
-55 to +125°C
-65 to +1500 C

Storage . . . . . . . . . .
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16± 1/32 inch (1.59 ±0.79 rnrn)

from case for 10 5 max.

-24

750
200
6.67

.

Above T A = 55°C derate linearly at
AMBIENT-TEMPERATURE RANGE. T A :

Operating.

V
V

.

265°C

STATIC ELECTRICAL CHARACTERISTICS at TA = 25°C
For Equipment Design
.
LIMITS

TEST
CHARACTERISTIC CONDITIONS

Min_ Typ.

CA3096C

CA3096

CA3096A

Max. Min. Typ.

UNITS

Max Min. Typ.

Max.

For Each n-p-n Transistor
ICBO

VCB- 1OV,
IE = a

-

0.001

40

-

0.001

100

-

0.001

100

nA

ICEO

VCE= 10V,
IB = a

-

0.006

100

-

0.006

1000

-

0.006 1000

nA

V(BR)CEO IC=lmA,
IB =0

35

50

-

35

50

-

24

35

-

V

V(BR)CBO IC= lO IlA,
IE = a

45

100

-

45

100

-

30

80

-

V

V(BR)CIO ICI = lallA,
IB=IE=O

45

100

-

45

100

-

30

80

-

V

V(BR)EBO IE= lO IlA,
IC = a

6

8

-

6

8

-

6

8

-

V

IZ = lallA

6

7.9

9.B

6

7.9

9.B

6

7.9

9.B

V

-

0.24

0.5

-

0.24

0.7

0.24

0.7

V

0.7B

0.6

0.69

0.78

0.6

500 150

390

500

100

390

670

1.9

-

-

1.9

-

Vz

VCE(SAT) IC=10mA,
IB=l rnA
VBE(Nofe l)IC= 1 rnA,

0.6

0.69

hFE(Nofe l)lVCE = 5 V

150

390

IlIVRl'/lITI IC=lmA,
(Note 1) VCE= 5V

-

1.9

-

-

7-34

-

0.69 0.78

V

mVtC

CA309~CA3096A,

CA3096C

STATIC ELECTRICAL CHARACTERISTICS at T A = 25°C (Cont'd)
For Equipment Design
LIMITS

CHARACTEST
TERISTIC CONDITIONS

Min_ Typ_

CA3096C

CA3096

CA3096A

Max_ Min. Typ.

Max Min. Typ.

UNITS
Max.

For Eact, p-n-p Transistor
ICBO

VCB=-10V,
IE = 0

-

-O.OOE

-40

-

-0.06 ..:100

-

-0.06 -100

nA

ICEO

Vce- 1OV,
IB= 0

-

-0.12

-100

-

-0.12 -1000

-

-0.12 -100e

nA

V(BRICEO IC=-100,uA.
IB= 0

-40

-75

-

-40

-75

-

-24

-30

-

V

V(BR)CBO IC=-10,uA,
IE = 0

-40

-80

-

-40

-80

-

-24

-60

-

V

V(BR)EBO IE = -10,uA,
IC = 0

-40

-100

-

-40

-100

-

-24

-80

-

V

V(BR)EIO lEI = 10,uA,
IB=IC=O

-40

-100

-

-40

-100

-

-24

-80

VCE(SAT) IC=-lmA,
I B =-100,uA

-

-0.16

-0.4

-

-0.16

-0.4

-

-0.6

-0.7

0.5

-0.6

VBE
(Note 1)

IC=-100,uA. -0.5
VCE=-5V

-0.7 -0.5

-

V

-0.16

-0.4

V

-0.6

-0.7

V

IC= -100,uA,
VCE=-5V

40

85

250

40

85

250

30

85

300

IC=-l mA,
VCE=-5V

20

47

200

20

47

200

15

47

200

-

2.2

-

2.2

-

-

2.2

-

hFE
(Note 1)

It-VBE It-TI IC= -100,uA,
(Note 1) VCE=-5V

-

mV/oC

ICBO

Collector-Cutoff Current

Vz

ICEO

Collector-Cutoff Current

VCE(SAT) Collector-to-Emitter Saturation
Voltage

V(BR)CEO Collector-to-Emitter Breakdown
Voltage

Emitter-to-Base Zener Voltage

Base-to-Emitter Voltage
DC Forward-Current Transfer
Ratio

V(B R)CBO Collector-to-Base Breakdown
Voltage
V(BR)CIO Collector-to-Substrate Breakdown Voltage

~

a:
a:

<

\t-VBE/t-T\ Magnitude of Temperature
Coefficient: (for each transistor)

V(BR)EBO Emitter-to·Base Breakdown
Voltage
NOTES:
1. Actual forcing current is via the emitier for this test.

7-35

CA309~CA3096A,CA3096C

STATIC ELECTRICAL CHARACTERISTICS at TA = 25°C (CA3096A Only)
For Equipment Design
LIMITS

TEST
CONDITIONS

CHARACTERISTIC

UNITS

CA3096A
Min. Typ. Max.

For Transistors 01 and 02 (as a Differential Amplifier)
Absolute Input Offset Voltage,

IVIOI

Absolute Input Offset Current,

11101

Absolute Input Offset Voltage
Temperature Coefficient,

-

0.3

-

VCE=5V,IC=lmA

5

mV

0.07 0.6

p.A

lilVIOI

--xr

-

1.1
0.15

-

p.vfc

For Transistors 04 and 05 (As a Differential Amplifier)
Absolute Input Offset Voltage,

IVIOI

-

Absolute Input Offset Current,

11101

-

Absolute Input Offset Voltage
Temperature Coefficient,

.

VCE = -5V,IC=-100p.A
lilVIOI RS= 0
~

-

5

mV

2 250

nA

0.54

-

p.vfc

. '0,

...I'

4

• ,
I

;§'

,,
,

I

~

~

,

1/

C

II

I

~vz1

4

a

~IO-I,

H

4j

,

•

4

t I
III

,

10-2

7

7.'
ZENER VOLTAGE CVzl-v

0.'

•

~

•

_

_

0

~

~

00

~

TEMPEAATURE-·C

Fig. 1 - Base-to-emitter zener characteristic

Fig. 2 - Collectorcut·offcurrent (IcEd as a
function of temperature fn-p-nJ.

(n·p-nJ_

10

III

500

~
~

.t..L.J.J

~E.p.tI.~+25.C

~400

300V~v
V

IV

-

zoo ...... I--::

I

I

r---1'

-40·C

'00

~

g

-15

-50

-25

25

50

15

000

TEMPERATURE-·C

Fig. 3 - Collector cut'Off current (I CBOJ as a
function of temperature (n-p-n).

0

,

4

.,

,

4

.. , . ..

0.1
I
COLLECTOR CURRENT fIC l-II'IA

'0

Fig. 4 - Transistor (n-p·nJ h FE as a function of

collector current.

7-36

CA309~

CA3096A, CA3096C

DYNAMIC
ELECTRICAL CHARACTERISTICS at T A = 25°C
Typical Values Intended Only for Design Guidance
CHARACTERISTICS

TEST CONDITIONS

TYPICAL
UNITS
VALUES

For Each n-p-n Transistor
f = 1 kHz, VCE = 5 V,
IC = 1 mA, Rs= 1 kS1

Noise Figure (low frequency). NF

2.2

dB

10

kS1

80

kS1

gfe

7.5

mmho

Yfe bfe

-j13

Low-Frequency, Input Resistance, Ri

f= 1.0 kHz. VCE = 5 V,
IC= 1 mA

Low-Frequency Output Resistance, Ro
Admittance Characteristics:
Forward Transfer Admittance,

-

gie

Input Admittance,

2.2

f= 1 MHz, VCE=5V,
IC=lmA

-

Vie

j3.1
0.76

goe
Yoe -boe

Output Admittance,

mmho

bie
mmho

j2.4
VCE=5V,IC=1.0mA

280

VCE = 5 V,IC= 5mA

335

Emitter-to-Base Capacitance, CEB

VEB = 3 V

0.75

pF

Collector-to-Base Capacitance, CCB

VCB = 3 V

0.46

pF

Collector-to-Substrate Capacitance, CCI

VCI = 3 V

3.2

pF

3

dB

Gain-Bandwidth Product,

fT

MHz

For Each p-n-p Transistor
Noise Figure (lowfrequencyl. NF

f = 1 kHz,
IC = 100llA, RS = 1 kS1

Low-Frequency Input Resistance, Ri

f=l kHz, VCE= 5 V,

Low-Frequency Output Resistance, Ro

IC= 100llA

Gain·Bandwidth Product, fT

VCE = 5 V, Ie = 100llA

Emitter-to-Base Capacitance, CEB

VEB = -3 V

Collector-to -Base Capacitance, CCB
Base-to-Substrate Capacitance, CBI

27

kS1

680

kS1

6.8

MHz

0.85

pF

VCB = -3 V

2.25

pF

VBI = 3 V

3.05

pF

r-Qg OOLt.EcioR-TO-EMITTER VOLTAGE (YCEI-5V

08

M_

07

--

V
I-

0'
0'
0

001

. ..

0

4

..

01
I
COLLECTOR CURRENT IIcl-mA

0

., .

10

TEMPERATURE--c

Fig. 5 - VBE (n-p-n) as a function of collector

Fig. 6- VSE (n-p-n) asa function of tempera-

current.

ture.

7-37

CA309~CA3096A,CA3096C

4

0.'

& II

2

..

...

6.

•

'0

COL.LECTOR CURRENT IICI-mA

i

10:

-'0

-"

lector current.

i

,

50

/'

..

I
l!

"\

V

I'Z"

0""

"

'00

'0

1"0

'0

. .,

,

001

TEMPERATUAE-~

\
,\

....

20

0

,

i&

~~

. .,

., .

0.1
I
COLl.ECTOR CURRENT Ire I-rnA

10

Fig. 10 - Transistor (p-n-p) h FE as a function
of col/ector current.

Fig. 9 - Collector cut-off current 11CBO) as a
function of temperature (p-n-p).

I ..

.OV

........

-----

ffi 40
§
~ '0

ii '0,

a

80

........

~ 70p cto~_,o-EMITTER 'tt~ "
60 COLLE:
%
~ ,0
"k

,

..

100

75

TEMPERATURE -'"C

110

~ IOO~

-0 90

~

----- -

'0

Fig. 8 - Collector cut-off current 11 CEO) as a
function of temperature (p-n-p).

Fig. 7 - V CE(SA T) (n-p-n) as a function of co/-

~

.

..

8

'00

'E 0'
I

r"

04

~

~
g

03

~

~
~

"

"
16

~

1/

~
~

0

!1

81;:~ ~ ~.~"

.-~'1'~,

001

0 I
I
COLLECTOR CURRENT lIe l-mA

I

,

.. 'SOl

..

61,

,

.. G'IO

Fig. 16 - Noise figure as a function of frequen~
cy for n-p-n transistors.

RSOUAC[·II(O

,.~~~ I
"I-~I

--

~

12r-

~f\r-fff,-,
s

J2"A

-~

I

,

.. 15

-

r--

7or~4

•
aDl

-_.-

~

I'(~

•

4~

,

tOr

..

... .. ,
,

,

61,

o

",,"r-F-jIO"'"

0.01

2

..

'110.

2

.. iii I

FREQUENCY{"-lOtz

RSOUACE-IMQ----

I

."(,,

:1\.

0
aDl

~

! /
~

-

--

,

'K>

0

,

"

6

I

to

2

iii

a

10

COLLECTOR CURRENT Ilel-mA

Fig. 19 - Noise figure as a function of frequency for n-p-n transistors.

Fig, 20 - Gain-bandwidth product as a function
of collector current (n-p-n) .

•0

1000a FREQUENCY If )_/ kHz

"•.or--...

... r--..

..

COLLECTOR .1"0. SUBSTRATE
CAPACITANCE ICCI)

"j'-.....

'0

-

I-

lOr--.

0

«

:l

fAEQUENCl'UJ-KHr

..

~

a:

:/

100

-... .. - -.
, ..
,

----

/'

1:200

........

'01

",/

~

~).

'R~

&sao

i

t'

100.....

.. 6

COl.LECTOR -TO- EMITTER VOLTAGE (VC~ l ' 5v

- 300

sp, ~...

2

n-p-n transistors.
400

Z4r-~'1p
~ ~.,.
.o~t-N

12

.. iii III)

Fig. 78 - Noise as a function of frequency for

2ap\'4~±t~ RSOURCE-'OO KA
~

Z

fREQUENCYIfl-KHt

Fig. 17 - Noise figure as a function of frequencv for n-p-n transistors.

16

.. ,

,

FREQUENCVCf}-kHt

Fig. 15 - Magnitude of input offset voltage
IvIOl as a function of collector
current for p-n-p transistor Q4- QS

"_I

Z

-- -

- f--!-"'="-

-~

I
I

,

4

. , . , . , . , . ..

,

001

{('/'"....1...J

~~rn~>r
~
:.r. .

V

I'-... 1--1-

0

~

121-~~

V

1"-

0'

01

14

ASOURCE·~OI1

,1

~

IEMITTER-TO-BASE
CAPACITANCE CCEBI

~CTOA-TO'8ASE
I

• •

I I

CAPACITANCE ICcal

r

r

I

0.01

BIAS VOLTAGE-V

. ,.

01
I
COLLECTOR CURRENT Ilcl-mA

. ..

Fig. 22 - Input resistance as a function of

Fig. 21 - Capacitance as a function of bias
voltage (n-p-n).

collector current.

7-39

10

CA309~CA~?96A,CA3096C

2:

FREQUENCY (fist hHz

4

H

~(~~~,. I

.0

!~
~~

~~

20---

~~

10---

~~

0

~e

I

co,JrcU.

' E
E
E

-"

~~

~~

cc
~~

...

~~

'~-+--+-+11---~-+~++--1-~~-H
I

oI

001

4

I
COLLECTOR CURRENT (ICI-mA

6 B,O

..

,

'20
I

'f,

100... A

I~.

,

• 10

t- .....
100

FREQUENCVItl-MH,

Fig. 24 - Forward transconductance as a

Fig. 23 - Output resistance as a function of
collector current.

function of frequency.

~ t s.f---+------j--1-1-+----+----h

~:

E E

EE

II

II

~!.~--+_--~-t-r~~+,

'112

~~3~--~--~--1-1-+_-:
~~

~tl

e e2.5

,!!.

I

Ol- c!~

z~

8~

I

~~
~~

~~

~~

LL

§ gO.5

LL

zz

. ..

,eptj

ff lv

~~ V
~

,

0
10
FREQUENCY (tI-MH.

Fig. 25 - Input admittance as a function of
frequency.

,~

.:

,..,./:-"" ...t.

~§

iH~
3~2~--~--~~+1-~~~--~~

1

,,~

;'i ;'i1.5

UL

'0

IOOJ •

~. ..

r- _.

-

-10

;;

J'I'

.,

,

~V

10
FREQUENCY en-UHI

. ..

100

Fig. 26 - Output admittance as a function of
frequency.

t'°I"I'I',oon

30

RSOURCE; I k.n

1111

~o«~JJ I

20~rn.&~
1-1~"~..,
t~~.
10

~'~"

10

'".

t-~
,

0
0.01

....

...II , ... , ..
0.1

l-

t-....
I

10

FREQUENCV Ifl- KH.

bo

001

Fig. 27 - Noise figure as a function of frequen·
cy {p,n·p},
40

Fig.

8

':--10--

0

:-... t-

COLLECTOR-TO-EMITTER VOLTAGE (VCE): 5V

-

~

1'\
lli

I'-

g

~

I'--

la,..A

2
"68'0 2
"88'0
FREQUENCY!rI-kHt

2

"&8,(\1'"

28 - Noise figure as a function of frequen4

~7-

.. ..

~~

20--

"680.

cy {p·n·p}.

"SOURCE = 10 kn

3O~~L1JJ

2

i~

6

- - --

-

t,

-

•

I I

f['--l
\

~

r-"'~f'.

t --- r-r-

I '"

5

~

r-

0012468012468102468102468U)O
FREQUENCY!f) - kH,

Fig. 29 - Noise figure as a function of frequency {p·n·p},

01

2

1

i

"6
8 10
2
COLLECTOR CURRENT (IC I-rnA

4,.

e

I

Fig. 30 - Gain-bandwidth product as a function
of collector current (p-n-p).

7-40

CA309~CA3096A,CA3096C

OUTPUT

NOTE:
FI OR F2 < 10 KHz

BIAS VOLTAGE-V

Fig. 31 - Capacitance as a function of bias

Fig. 32 - Frequency comparator using

voltage {p-n-p}_

CA3096

0,

120 V AC

JOOp.F
'2 V

Fig_ 33 - Line-operated level switch using CA3096A

or CA3096
+6V

9

•
7

t

-

,.....

CENTER FREQUENCY 1 kHz

/

6

"

/

20Kn

".

".

~
~

•
~ ,
s
g

4

'--

/

2

-20

/

V

SOMa

·,0
'2-1."0

o
'."2

10
'1-'2>0

FREQUENCY DEVIATION (.o.f)-kHz

5 foF

20
TIME DELAY CHANGES % 7"10
FOR SUPPLY VOLTAGE CHANGE OF ± 10"1.

Fig. 35 - One-minute timer using CA3096A
and a MOS/FET_

Fig. 34 - Frequency comparator charac-

teristics.
v+

VT':!:

IKO

r~6RL

EO

IF IO:lmA

~

r\

AND RL"It<.n
VT::!:36mV

,

~

EODDe,

Fig. 36 - CA3096A

small-signal zero-voltage detector having noise immunity.

7-41

CA309aCA3096A,CA3096C
I5"

LAMP G E 21580

70

OR EQUIVALENT

60
m

i

,0

z

iiw

:l
~
g

'.'

40

30

10
4

"10

2

4 ' 'tOO

I:

4 ' '1000

FREOU£NCY(fl-IIHz

SUBSTRATE I

-=Fig. 38 - Gain4requency characteristics.

Fig. 37 - Ten-second timer operated form 1.5-volt

supply using CA3096

Features:
1. Can be operated with either dual
supply or single supply.
2. Wide·input common·mode range
+5 Vto -5 V.
3. Low bias current: < 1 /lAo

,...

51 KG

,...

51"11

Fig. 39 - cascade of differential amplifiers using CA3096A

CA3096H
The photographs and dimensions represent a chip
when it is part of the wafer. When the wafer is cut
into chips, rhe cleavage angles are 57· instead of
90· with respect to the face of the chip. Therefore,
the isolated chip is actually 7 mils (0. 17 mm)
larger in both dimensions.

Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Grid graduations are in mils f1 0- 3 inch}.

7-42

CA3127

(lJHARRIS

High-Frequency N-P-N
Transistor Array

August 1991

Features

Description

• Gain-Bandwidth Product (fT) •.•••••••••••••

> 1 G Hz

• Power Gain •••••••••••••••••• 30dB (Typ) at 100MHz
• Noise Figure •••••••••••••••• 3.5dB (Typ) at 100MHz
• Five Independent Transistors on a Common
Substrate

Applications
• VHF Amplifiers

The CA3127* consists of five general-purpose silicon
n-p-n transistors on a common monolithic substrate. Each
of the completely isolated transistors exhibits low llf noise
and a value of fr in excess of I GHz, making the CA3127
useful from DC to 500MHz. Access is provided to each of
the terminals for the individual transistors and a separate
substrate connection has been provided for maximum
application flexibility. The monolithic construction of the
CA3127 provides close electrical and thermal matching of
the five transistors.

o VHF Mixers

The CA3127 is supplied in the 16-lead Small Outline
package (M suffix), 16-lead dual-in-Iine plastic package
(E suffix), 16-lead dual-in-line frit-seal ceramic package
(F suffix), and is also available in clip form (H suffix). it
operates over the full military temperature range of -550 C to
+1250C.

o IF Converter

• Formerly RCA Oov. No. TA6206.

• Multifunction Combinations - RF/Mixer/Oscillator
o

Sense Amplifiers

o

Synchronous Detectors

o IF Amplifiers

• Synthesizers
• Cascade Amplifiers

Schematic Diagram

MAXIMUM RATINGS, Absolute-Maximum Values:
POWER DISSIPATION, Po:
Anyone transistor ................................ 85 mW
Tolal Package:
ForTA up to 75 0 C ............................... 425mW
For TA > 750 C .............. Derale Linearly at 6.67 mW/oC
AMBIENT TEMPERATURE RANGE:
Operating ............................. -55 0 Cto+125 0 C
Storage ............................... -650 Cto+1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for
10 seconds max..................................... +2650 C
The following ratings apply for each transistor in the device:
COLLECTOR-TO-EMITTERVOLTAGE, VCEO ............ 15 V
COLLECTOR-TO-BASEVOLTAGE,VCBO ............... 20V
COLLECTOR-TO-SUBSTAATEVOLTAGE,VCIOt ........ 20V
COLLECTOR CURRENT, IC ............................ 20 rnA

SUBSTRATE

FIGURE I.

t The colleclor of each transistor of the CA3127 is isolated from the substrate by an integral diode. The substrate (lerminaI5) must be connected to the most
negative pOint in the external circuit to maintain isolation between transistors and to provide for normal transistor action.
CAUTION: These devices are sensitive 10 elecrlrostalic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

7-43

File Number

662.1

CA3727
STATIC ELECTRICAL CHARACTERISTICS at TA = 250 C
CHARACTERISTICS

LIMITS

TEST CONDITIONS

UNITS

Min. Typ. Max.
For Each Transistor:
Coliector·to·Base
Breakdown Voltane

IC= lO IlA,IE=O

20

32

-

V

Collector·to·Emitter
Breakdown Voltage

IC= 1 mA,IB=O

15

24

-

V

Collector·to·Substrate
Breakdown Voltage

ICl = lOIlA,lB = O,IE = 0

20

SO

-

V

Emitter·to·Base
Breakdown Voltage·

IE = lOIlA,lC = 0

4

5.7

-

V

Collector-Cutoff-Current

VCE = 10 V, IB = 0

-

-

0.5

IlA

Collector-Cutoff-Current

VCB = 10 V, IE = 0

40

nA

DC Forward-Current
Transfer Ratio

VCE = S V

-

-

IC= SmA

35

88

IC= 1 mA

40

90

-

35

85

-

IC= 0.1 mA

Base-to-Emitter Voltage

VCE =SV

Ic-5mA

0.71 0.81 0.91

IC=l mA

0.S6 0.76 0.86

IC=O.l mA

O.SO 0.70 0_80

V

Collector-to-Emitter
Saturation Voltage

IC = 10 mA,lB = 1 mA

-

Magnitude of Difference
in VBE

01 & 02 Matched

-

0.5

5

mV

Magnitude of Difference
in IB

VCE = 6 V, IC = 1 mA

-

0.2

3

IlA

0.26 0.50

V

·When used as 8 zener for reference voltage, the device must not be subjected to more than 0.1 millijoule of energy from any possible capacitance
or electrostatic discharge in order to prevent degradation of the junction. Maximum operating zener current should be less than 10 mAo

DYNAMIC CHARACTERISTICS at T A = 25°C
CHARACTERISTICS

TEST CONDITIONS

LIMITS
Min. Typ. Max.

UNITS

1.15

-

GHz

VCB = 6 V, f = 1 MHz

-

See

-

pF

Collector-to-Substrate
Capacitance

VCI = 6 V, f = 1 MHz

-

Fig.

-

pF

Emitter-to-Base
Capacitance

VBE = 4 V, f = 1 MHz

-

5

-

pF

Voltage Gain

VCE = 6 V, f = 10 MHz
RL = 1 kn, IC = 1 mA

-

28

-

dB

Power Gain

Cascode Configuration
f= 100 MHz, V+= 12 V

27

30

-

dB

-

dB
kn

IIF Noise Figure

f= 100 kHz, RS= 500n,IC= 1 mA

Gain-Bandwidth Product

VCE = 6 V, IC = 5 mA

Collector-to-Base
Capacitance

1.8

Noise Figure

IC=l mA

-

3.5

Input Resistance

Common-Emitter

-

400
4.6
3.7
2

-

24

-

Output Resistance

Configuration

Input Capacitance

VCE =.6 V
IC=l mA

-

f= 200 MHz

-

Output Capacitance
Magnitude of forward
Transadmittance

7-44

dB

n
pF
pF
mmho

CA3127

AMBIENT TEMPERATURE ITAloZ:'-C
COLLECTOR-TO-EMITTER VOLTAGE IVCt'o6V
30 RSOURCE. :lOon

J¢t

1

,J~

"'-

",/

20

V

'0

"

0

,...1-"

,

'0,

~
......... ~
~
,
,
,

..

20~-4---r-+~~-+--~~~++---r~

"

//

V

F"

,

,

~

..........

100\li'il

00'

4

Fig. 2 - 1If noise figure as a function of collector
current at R SOURCE = 500 n.

' 8 01

4

6

8

I

COLLECTOR CURRENT (ICI-mA

COLLECTOR CURRENT tlcl-rnA

Fig. 3 - 1If noise figure as a function of collector
current at RSQURCE = I kn.

,
I

o.t-----

~ 08 r~
~

g
n1
~

~

O.G

__ .LLUURE ".!.."=-

--

~

; n,-

-

0.'

...,1::::1-"

'l~-c.

f.-- r--

-l-

~

~I-

-I-

,

0.'

1-1-

AMBIEN

.

,

. ..

,

COlLECTOR CURRENTlltl-fIIA

Fig_ 4 - Gain-bandwidth product as a function of
collector current.

Fig. 5 - Base-to-emitter voltage as a function of
collector current_

CiipacilanC1llpFI

..,.

CCB

Tfilmilito.

CCE

To,,1 Pkll.

T01~1

..,.

C

GV

Voltag_

0015

-

.V

GV

0360 008'

''''
'.35

0190 0.225 0270 03'"

0610 008'

12'

0 ' " 0095 0115 0.140

03 .. 0090

0170 0225 0.2EG 0130

0200 0215 0240 0360
O.

0040

::c
cr:

cc,

0190 0090 0'25 0.365

02

U)

..,.

EB

'40

Fig. 6(b) - Typical capacitance values at f = I MHz.
Three terminal measurement. Guard
all terminals except those under test.
Fig. 6ra} - Capacitance as a function of bias
voltage for Q;z.

lS

..

~L~ CURRE~T 11.cJ.,,~
_I

'0

m

''''~

i
s 20
~

~

~

!/

I

.'",

"
,
'0

I
I
o AMBIEHT TEMPERATURE ITAlle-C

-5

. ..

"-

"

'"

..

.\.
'\."\

:\

~~~E!::;!~~~~L~~~ :LTAGE '''tEloIiV

,

,

FOR TEST CIRCUfT SU FIG. 20

FREOUENCY Ifl-MHI

"-

li?,;)o...

'0

'00

,

.

'"~ 1000

FREQuENCYIlI-hlHI

Fig. 8 - Voltage gain as a function of frequency
at RL ~ I kn.

Fig. 1 - Voltage gain as a function of frequancy

atRL -lOOn.

7-45

cr:

et

CA3127

-;. 100

~~~'i~o~~~:::iT~EERt~~;~tVcEl06V

f 901--1--+-

I

...... 1'-..

1'0

i5

-.

i=';

~ TO,~--l---J.-+--I-I--+----l---l---l--l

., .

•

V

T

•

~

i

5

.
:------

V

/

./

/'"
. / Vo"

.,

0
100

'10

•

7

a 91000

FREQUENCY ItI-IliHI

COLLECTOR CURRENT (lei-iliA

Fig. 9 - DC forward-current transfer ratio
function of collector current.

V

Y

i~'
- ./'

LO~--l---J.-+--I-I--I---l---l---l--l
Ig ~~--l---+-+--~--~--l--+-+4
0.'

AMBIENT TEMPERA'TURI: IT,,'o15·C
COLLECTOR-TO-EMITTER VOLTAGE I\tE'o6V
• COLLEtTOA CURRENTlIClol1IIA

Fig. 10 - Input admittance IY ,,) as a function of

as a

frequency.

.:

~
I

13 AMBIENT TEMPERATURE !TA'-2S-C
12 COLLECTOR-TO-EMITTER VOLTAGE
IVCEI- IV
1.1 COLLfCTOR CURRENTIIC"'IIIA

.0
i~

-It-+-+-H--I

t

I

I

I I
II

~

s oef----I--+---Ji'--f-H-++-I' E
~

e

i

~

O.6

&~

//

1//

0.5

5

~

M

i
~

Si

::~t?
o.lt"""-.U

• '1000

'00
FREQUENCY IfI-MHI:

COLLECTOR CURRENT {,Icl-IIIA

Fig. 11 - Input admittance (Y 1,) as a function of

COLLECTOR CURRENT(Icl-IIIA

COLLECTOR CURRENTIIC'-IfiA

Fig. 13 - Output admittance IY22)as a function of

i

t-...

E

Ii
~-

I :0

!

-

100

"

-40

N2I

"

t-- j....1'o.1

'0

10

~
~

::I~

t......

~:
~

Fig. 14 - Forward transadmittance 1Y21) as a
function of collector current.

collector current.
AMBIENT TEMPERATURE ITAloZS·C
COLLECTOR-TO-EMITTER VOLTAGE IVcElo6V
COLLECTOR CURRENT \ Ie 101lllA

~

Fig. 12 - Output admittance IY22) as a function of
frequency.

collector current.

-so

"

~~

il g

It

-60~m
-10 ~

-eo!

t-

. ..

-OOl

,

I.,~
1 7 . '1000

FREOU£NC'I' (f1-IliHI
COLLECTOR CURRENT ItcHIIIA

Fig. 15 - Forward transadmittance (Y21) as a
function offrequency.

Fig. 16 - Reverse transadmittance IY 12) as B
function of collector curren t.

7-46

CA3127

y+

7 "1000

100
FREQUENCY (f)-MHz

Fig. 18 - Voltage--gain test circuit using current---

Fig. 17 - Reverse transadmittance (Y 12) as a
function of frequency.

<-.-r...........--J

D'

This circuit was chosen because it convenientlv
represents a close approximation in performance to
a properly unilateralized single transistor of this
type. The use of 03 in a current-mirror configuration facilitates simplified biasing. The use of the
cascade circuit in no way implies that the tran.
sistors cannot be used individually.

1
!l60n

1
, 1

=1

100D

I

~

J

I

~

mirror biasing for 02-

I
-"2

itE.F.JOHNSON No 160-104-1
OR EQUIVALENT

Fig. 19:'" 100-MHz power-gain and nois,..figure test circuit.

a...I RId50 1021-P1
100-MH. G...~DI'

Fig. 20 - Blocle diagrams of poWtlr-gain and noise-figure telt set·ups.

7-47

CA3141

mHARRIS

High-Voltage Diode Array
For Commercial, Industrial & Military Applications

August 1991

Features

Description

• Matched Monolithic Construction - VF for Each Diode
Pair Matched to Within O.SSmV (Typ) at IF 1mA

The CA3141 E High Voltage Diode Array Consists 'of ten
general purpose high. reverse breakdown diodes. Six
diodes are internally connected to form three common
cathode diode pairs, and the remaining four diodes are
internally connected to form two common anode diode
pairs. Integrated circuit construction assures excellent
static and dynamic matching of the diodes, making the
CA3141 extremely useful for a wide variety of applications
in communications and switching systems.

=

• Low Diode Capacitance - O.3pF (Typ) at VR = 2V
• High Dio'de-to-Substrate Breakdown Voltage ••• 30V
(Min)
• Low Reverse (Leakage) Current •••••••• 1 ~OnA (Max)

Applications
• Balanced Modulators of Demodulators

The CA3141 is supplied in the 16-lead dual-in-line plastic
. package (E suffix), and in chip form (H suffix).

• Analog Switches
• High-Voltage Diode Gates
• Current Ratio Detectors

Pinout

MAXIMUM RATINGS, Absolute-Maximum Values:
CA3141
16 PIN PLASTIC DIP
TOP VIEW

PEAK INVERSE VOLTAGE (PIV) ••.•.••.••••.•..•..•••..... 30V
PEAK DIODE-TO-SUBSTRATE VOLTAGE ••••.••.•••..••.• 30V
PEAK FORWARD SURGE CURRENT [IF (SURGE») .••••• 100mA
DC FORWARD CURRENT (IF) •••.••••.••..••.••.••.•••• 25mA
DISSIPATION:
Anyone diode unit ••••••.••••••••.••••••••.••.•.••• 50mW
Total Package:
Up to 550C ••.•••.•.•.••.•.....••.•••••.••••••.. 650mW
For TA > 550C ••.••.•••.••••• Derate linearly at6.67mW/OC
AMBIENT TEMPERATURE RANGE:
Operating .••.•••.•••.••.••..•..•.•.••. -550 Cto+1250 C
Storage ......•.••..••..•.••.••••••..•. -650C to + 1500C
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79mm) from case for
1Os max ...••.•.••..•..••..••...•••••...••..•..• +265 0 C

FIGURE 1.

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.e. handling procedures should be followed,
Copyright © Harris Corporation 1991

7-48

File Number

906.1

CA3141
ELECTRICAL CHARACTERISTICS at T A = 25°C
LIMITS _ _

TEST

CHARACTERISTIC

CONDITIONS
IF (Anode I

DC Forward Voltage Drop, V F

100llA
1 mA
10mA

UNIT

Min.

Typ.

Max.

-

0.7
0.78
0.93

0.9
1
1.2

V

DC Reverse Breakdown
Voltage, V(BRIR

IF = -10 IlA

30

50

-

V

DC Breakdown Voltage Between
Any Diode and Substrate,

101 = lOIlA

30

50

-

V

DC Reverse (Leakagel Current,1 R

VF=-20V

-

-

100

nA

DC Reverse (Leakagel Current
Between Any Diode and
Substrate, 101

VOl = 20 V

-

-

100

nA

Magnitude of Diode Offset
Voltage Between Diode Pairs

VOl = 20 V
IFA=lmA

-

0.55

-

mV

Temperature Coefficient of
Forward Voltage Drop,

IF = 1 mA

-

-1.5

-

mVtC

IF=2mA,IR=2mA

-

50

-

V(BRIDI

D.VF/6.T
Reverse Recovery Ti me, trr

See Fig. 5

Diode Capacitance, CD

ns
pF

Diode Anode·to-Substrate
Capacitance, COAl

See Fig. 6

pF

Diode Cathode-to-Substrate
Capacitance, CDCI

See Fig. 7

pF

Magnitude of Cathode-to-Anode
Current Ratio, IIFC/IFAI

>
I
~

I IBIEr TEMPERTuRE
I
08

i

I

~

0

06

~

~

~ 04

1

0.9

0.96

-

(TA'-2,·C

I

I

,

~

'"ow

!

IFA = 1 mA, VDS= 10V

!

PI

:

i

0

l'i~

~ 0.2

is
0
2

0.1

i

4 68

2468

10

2

468

2

10 2

466

2

4 66

FORWORD CURRENT (IF)- ~A

AMBIENT TEMPERATURE (TA1-OC

Fig. 2 - DC forward voltage drop vs.
forward current.

Fig. 3 - DC forward voltage drop vs.

ambient temperature.

7-49

CA3141

;)

=e

~ 2
~
'"
~

':;.

....

I

~-~-~~~~-4~f7.+-+-+~~~·~··

I

~ 0 Bl-*-"-,-+-':+--I-·..j~+--I--+-+--'I..:..j-I~FJ

i

>

~

I-r--;.:- . ,,,., .,. ". ,.. , ., ,~
.. -'-"'~R-'-

IVFI-VF21.I VF3-VF41·IV..-VF.1
IVF,VFal·IV..-V,ol

0

~

1.2 AMBIENT TEMPERATURE (TAl "2Soc!::.·

AMBIENT TEMPERATURE (TAI'"2S D C

25

15

I
1/

0.5

,

a
2 4 68

10

4 .0

10 2

,

4 .0

103

,

4 .0

104

2

4 68

a

MAGNITUDE OF ANODE CURRENT (:tFAI-,.A

10

15

20

CATHODE-lO-ANOOE DC REVERSE VOLTAGE (VR1-V

Fig. 5 - Diode capacitance vs. cathode-toanode reverse voltage.

Fig. 4 - Diode offset voltage vs. magnitude of

anode current.

AMBIENT TEMPERATURE(TA )_2S D C: ......•. ::::

8'"
a

is

o

2

5

10

15

20

ANODE-TO-SUBSTRATE DC REVERSE VOLTAGE eVRI-V

CATHODE - TO- SUBSTRATE DC REVERSE VOLTAGE (VRI-V

Fig. 6 - Diode anode-to--substrate capacitance
VI. reverse voltage.

F.ig. 7 - Diode cathode·to-substrate capacitance vs.
cathode·to-substrate DC reverse voltage.
10'~1=

'I-

~lo4iF

~ ,~
~ :~
,
6F
= :~

(

V /

=>

u 10'

/-\

III

~IO

oJ

g

0.124686.1246812468102468

F
:F
2f-

I

!I=

0.1

'I-100

FORWARD (ANODE)CURRENT U:FI-mA

/

DIODE-TO-SUBSTRATE
LEAKAGE CURRENT

ZIO'

~

-so

I-

l!

o

/
/

DIODE REVERSE
(LEAKAGE) CURRENT

50

100

150

AMBIENT TEMPERATURE (TAl-DC

Fig. 9 - DC leakage current vs. ambient

Fig. 8 - Forward (cathode) current vs. forward

temperature.

(anode) current

7-50

m

CA3146,CA3146A
CA3183,CA3183A

HARRIS

High-Voltage Transistor Arrays

August 1991

Features

Description

• Matched General-Purpose Transistors

The CA3146A, CA3146, CA3183A, and CA3183* are
general-purpose high-voltage silicon n-p-n transistor
arrays on a common monolithic substrate.

• VBE Matched ±5mV Max
• Operation from DC to 120MHz (CA3146, A)
• Low-Noise Figure: 3.2dB Typ at 1 kHz (CA3146, A)
• High IC: 75mA Max (CA3183, A)

Applications
• General Use in Signal Processing Systems in DC
Through VHF Range
• Custom Designed Differential Amplifiers
• Temperature Compensated Amplifiers
o Lamp and Relay Drivers (CA3183, A)

• Thyristor Firing (CA3183, A)

Pinouts
CA3146, A
14 PIN PACKAGES
TOP VIEW

CA31B3, A
16 PIN PACKAGES
TOP VIEW

Types CA3146A and CA3146 consist of five transistors
with two of the transistors connected to form a
differentially-connected
pair.
These
types
are
recommended for low-power applications in the DC
through VHF range. Both types are supplied in 14-lead
dual-in-line plastic (E suffix) and l4-lead small outline
(M suffix) packages and operate over the ambient
temperature range of -40 0 C to +85 0 C. (CA3146A and
CA3146 are high-voltage versions of the popular
predecessor type CA3046.)
Types CA3183A and CA3183 consist of five high-current
transistors with independent connections for each
transistor. In addition two of these transistors (01 and 02)
are matched at low-current (i.e. 1 mAl for applications
where offset parameters are of special importance. A
special substrate terminal is also included for greater
flexibility in circuit design. Both types are supplied in
16-lead dual-in-line plastic (E suffix) and l6-lead small
outline (M suffix) packages and operate over the ambient
temperature range of -400 C to +850 C. (CA3183A and
CA3l83 are high-voltage versions of the popular
predecessor type CA3083.)
The types with an "A" suffix are premium versions of their
non-"A" counterparts and feature tighter control of
breakdown voltages making them more suitable for higher
voltage applications.
For detailed application information, see companion
Application Note, ICAN-5296 "Application of the CA3018
Integrated Circuit Transistor Array."
*Formerly Developmental Types Nos.

CA3146A CA3146

PT·
TYPE

MAX.
mW

IC
MAX.
mA

VCEO
MAX.
V

TA6084
TA6181

VCBO
MAX.
V

VCEsat.
at10mA
TYP.
V

hFE
atl mA,
&VCE=5V
TYP.

CA3183A CA3183
-

TA6094
TA6163

DIFF.PAIRAT1mA
VIO
MAX.
mV

110
MAX.

TARanga
(OPERATING)

~A

°c

VALUES APPLY FOR EACH TRANSISTOR
CA3146A

300

50

40

50

0.33

100

±5

2

-40- +85

CA3146

300

50

30

40

0.33

100

±5

2

-40-+85

CA3183A

500

75

40

50

0.16

75

±5

2.5

-40-+85

CA3183

500

75

30

40

0.16

75

±5

2.5

-40- +85

• Caution on Tolal Package Power Dissipation: The maximum lotal package dissipation rating for the CA3146 and CA31 83 Series circuits is 750 mW at
temperatures up to +550 C, then derate linearly at 6.67mW/oC.

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @) Harris Corporation 1991

7-51

File Number

532.1

CA3146, CA3146A, CA3183, CA3183A
MAXIMUM RATINGS, Absolute-Maximum Values at TA = 250 C
POWER DISSIPATION:
Anyone transistor CA3146A,CA3146 ••..••...•.•••.•••.•••.••••••.•..•..••••••••••••••••••.•••••••.••••••••••••••.•••••••••••••••.•••••• 300mW
CA3183A,CA3183 •••••••••••••••••••••••••••••••••••••.••••••••••••••••••••••••••••••••••.•••••••.••.••••••••••••••.• 500mW
Total package Up to 550 C (CA3146A, CA3146, CA3183A, CA3183) •••••••••••••••••••.••.•.•••.••••••••.••••.••••.••.••.••.•••••••••••.• 750 mW
Above to 550 C (CA3146A, CA3146, CA3183A, CA3183) ••••••.••••.••••••••••••••••••••••••.••••••..••.•• Derate linearly 6.67 mWfOC
AMBIENT TEMPERATURE RANGE:
Operating CA3146A, CA3146, CA3183A, CA3183 .••••••••••••.•••••••••.•••••••••..••••••.••••.••••••••••••••.••••••••••••••• -4010 +850 C
Storage(alilypes) .•••.••.•••••••••••.••••••.••••••••••••.••••.••••••••••••••..••••••.•••••••••••••••••.••••••••••• -6510+15OOC
The following ratings apply for each transistor In the device:
COLLECTOR-TO-EMITTER VOLTAGE (VCEO):
CA3146A,CA3183A •.•••••••••••••••••••••••••••••.•••••••••••••••.••.•••••..••••••.••••.••••.••.•••••.••••..•••.•••••••• 40V
CA3146,CA3183 ••••.••••••••..••••••••.••••••.••••..••••.•••.•••••.•••••••••••.••••.•••••.•••.••••••.•.••••.•.••••.•••••• 30V
COLLECTOR-TO-BASE VOLTAGE (VCBO):
CA3146A, CA3183A •.•.••••••••••••.••••••••••••.•.••••.••.••••••.••.••••••.•..••.•.••••.••••.••.•••••.•••••••••.•••••••• 50V
CA3146,CA3183 •.•••••••••••••••.•.••••••••••••.•••••••••.••••.•.••.••••.••••••..•••••••••••••••••••••••••••••.••.••••.• 40V
COLLECTOR-TO-SUBSTRATE VOLTAGE (VCIO):CA3146A, CA3183A •••••••••.••••.••••••.•.••••••••••.••••••••..••••••••••••••.•.•••••••••.•••••••.••••••.••••••••••••••• 50V
CA3146,CA3183 ••••••..••••••••.••.••••••••••••••.•.••..••••••••.••••.•••••••.••••.••••.••••.•••••••••••••••••••.••••••• 40V
EMITIER-TO-BASE VOLTAGE (VEBO) all types •••••••••••.•.••.•••••••••••••••.•••••••••••.•.•••••••.••••••••••••••••.••••••••••• 5 V
COLLECTOR CURRENT CA3146A, CA3146 ••••••••••••••••••.••••••.•••••••••••••••••••••••••••••••.••••.•••.•.••••.••••••••••.•••••••.••••••••• 50 rnA
CA3183 ••••••••••••••••••••••••••••.••••••••••••••••••••••••••.••••••••••••••••.••••••••••••.•••..••.•••.•••••.••••.•. 75 rnA
BASE CURRENT (IB) - CA3183A, CA3183 ••••••••••••••••••.•••••••••.••••••••••••••••••••.•.•••••••.••••••••••••••••••••••••• 20 rnA
• The collector of each transistor Is isolated from the substrate by an integral diode. The substrate must be connected to a voltage which is more negative than any
collector vollage in order to maintain isolation between transistor action. To avoid undesired coupling between transistors. the substrate terminal should be maintained
at eKher DC or signal (AC) ground. A suHable bypass capacilar can be used to establish a signal ground.

SUBSTRATE

CA3146A. CA3146

CA3163A. CA3163

Figure 1 - Schematic diagrams of high-voltage arrays.

COMPARISON OF RELATED PREDECESSOR TYPE WITH TYPES IN THIS DATA BULLETIN
DATA
FILENO.

CA3046
CA3146A
CA3146

CA3083
CA3183A
CA3183

341

VeEO
MIN.

15
40
30

481

15
40
30

VeBO
MIN.

20
50
40

20
50
40

veE sat.
TYP.V

VBE
TYP.V

le=10mA

IC=l mA

0.23
0.33
0.33

0.715
0.730
0.730

le=50mA

le=10mA

0.4
1.7

0.74
0.75
0.75

1.7

7-52

Ie
MAX. rnA

CeB
TYP.pF

Cel
TYP.pF

CEB
TYP.pF

50
50
50

0.58
0.37
0.37

2.8
2.2
2.2

0.6
0.7

100
75
75

-

-

-

0.7

CA3146, CA3146A, CA3183, CA3183A
STATIC ELECTRICAL CHARACTERISTICS - CA3146 Series

CHARACTERISTICS

TEST CONDITIONS
Typ.
Char.
TA = 250 C
Curve
Fig.No.

SYMBOL

LIMITS
CA3146A

CA3146
UNITS

Min.

Typ.

Max.

Min.

Typ.

Max.

For Each Transistor:
Collector-ta-Base

VIBR)CBO

Breakdown Voltage

IC = 10ILA,IE = a

-

50

72

-

40

72

-

V

IC= lmA,IB =0

-

40

56

-

30

56

-

V

-

50

72

-

40

72

-

V

-

5

7

-

5

7

-

V

COllector-ta-Emitter

Breakdown Voltage

VIBR)CEO

Collector-ta-Substrate

ICI = lalLA, Ie = a

VIBR)CIO

Breakdown Voltage

IE =0

Emitter-ta-Sase

IE = lalLA, IC = a

VleR)EeO

Breakdown Voltage

se.

COllector-Cutoff Current

ICEO

VCE = 10V,Ie = a

2

-

Collector-Cutoff Current

Iceo

Vce = 10V, IE = a

3

-

4

-

85

-

4

30

100

4

-

90

-

IIC=10mA

DC Forward-Current

VCE=5V I IC=l mA

hFE

Transfer Ratio

IIC= lOILA
Base-ta-Emitter Voltage

0.002

5

-

100

-

curve

5

0.002

100

ILA
nA

85

-

30

100

-

90

-

0.63

0.73

0.83

V

0.33

-

V

1.46

-

VeE

VCE=3V,lc=lmA

5

0.63

0.73

0.83

VCE,.,

IC = lamA, Ie = 1 mA

6

-

0.33

-

-

8

-

1.46

-

-

8,9

-

-

4.4

10,11

-

0.48

-

-

-

12

Collector-ta-Emitter
Saturation Voltage

curve

..

,

-

For transistorsQ3 and Q4 (Darlington Configeration):
Base-ta-Emitter

V

VeE

CE

103'004)
Magnitude of Base-to-

Emitter Temperature
Coefficient

16:~E I

=5V liE = 10mA
IIE=lmA

VCE = 5V, IE = 1 mA

1.32

1.32

V

-

4.4

5

-

0.48

1.9

-

-

1.9

-

mV/oC

-

1.1

-

-

1.1

-

ILV/oC

-

0.3

2

-

0.3

2

ILA

-

-

mV/oC

For transistors 01 and Q2 (AS a Differential Amplifier):

Magnitude of Input

Offset Voltage

IVlol

VCE = 5V, IE = 1 mA

1:~eEI

IE = lmA

5

mV

IVBEl = VeE21
Magnitude of Base-to-

Emitter Temperature
Coefficient
Magnitude of VIC

...

IVeE 1 . VeE2) Temp·

erature Coefficient

;,~.

Input Offset

Current

11101.11021

)

VCE = 5V,
1:;01

CA3146AE
and
CA3146E

VCE = 5V,

110

ICl = IC2 = 1 mA

VCE = 5V,
ICl = IC2 = 1 mA

only

7-53

CA3146, CA3146A, CA3183, CA3183A
DYNAMIC ELECTRICAL CHARACTERISTICS - CA3146 Series
SYM·
BDL

CHARACTERISTICS

TEST CONDITIONS
Typ.
Cha ••
TA = 25~C

CA3146A

CA3146

UNITS

Curve

Typ.

Fig.No. Min.

Max.

Typ.

Min.

Max.

f'" 1kHz, VeE = 5V.

NF

Low Frequency Noise Figure

Ie;:: looP.A, Source
resistance = 1 kn

14

3.25

16

100

3.25

dB

Low-Frequency, Small-5ignal

Equivalent-Circuit
Characteristics:
Foward·Current Transfer

h,.

Ratio

100

I = 1kHz. VCE = 5V,

Short-Circuit Input

Ic=lmA

16

2.7

3.5

Open-Circuit Output
Impedance

hoe

16

15.6

15.6

Open-Circuit Reverse_

hr.

16

1.8xl0·4

1.8xl0·4

hie

Impedance

Voltage Transfer Ratio

Admittance Characteristics:
Foward Transfer Admittance

17

31·;1.5

31,;1.5

1= lMHz, VCE = 5V,

18

0.35+;0.04

0.3+;0.04

Voe
Vre

Ic""mA

19

O.OOl+jO.03

Gain-Bandwidth Product

'T

VCE = 5V,IC = 3mA

21

Emitter-ta-Base Capacitance

CEB

VEB = 5V. IE = 0

22

Collector·to--Base Capacitance

CCB

VCB = 5V, IC = 0

Collector-to-Substrate
Capacitance

CCI

VCI

V'e
Vie

Input Admittance

Output Admittance

Reverse Transfer Admittance

mmho
mmho

0.001+;0.03

mmho

See curve

mmho

500

MHz

0.70

0.70

pF

22

0.37

0.37

pF

22

2.2

2.2

pF

20

=5V. IC = 0

kU

IJmho

See curve

300

500

300

STATIC ELECTRICAL CHARACTERISTICS - CA3183 Series
LIMITS

TEST CONDITIONS
CHARACTERISTICS SYMBOL

Typ.
Char

TA=250 C

CA3183

CA3183A

UNITS

Curve
Fig. No. Min.

Typ.

Max.

Min.

Typ.

Max.

For Each Transistor:
COllector-to-Base
Breakdown Voltage

VIBRICBO

Collector-to-Emitter
Breakdown Voltage

VIBRICEO

-

50

-

-

40

-

-

V

le"'1 mAo 'B=O

-

40

-

-

30

-

-

V

-

50

-

-

40

-

-

V

ICI=I00}.lA,IB=O.

Collector-to-Substrate
Breakdown Voltage

'C=loo}.lA,IE=o

VtBRIC'O

Emitter-to-Base

'E =0

VtBRIEBO

IE = 500}.lA, IC = 0

-

5

-

-

5

-

-

Collector-Cutoff Current

ICEO

VCE = 10V,Ie =0

23

-

-

10

-

10

}.IA

Collector-Cutoff Current

ICBO

VCB

-

-

-

-

1

}.IA

-

40

-

-

Breakdown Voltage

DC Forward-Current
Transfer Ratio
Base-to-Emitter Voltage

hFE

10V, 'E = 0

24
25.26

40

1

40

-

-

0.65

0.75

0.85

V

-

1.7

3.0

V

5

-

0.47

5

mV

2.5

-

0.78

2.5

IJA

VCE - 5V. IC - 50mA

-

40

-

VBE

VCE = 3V, IC

lOrnA

27

0.65

0.75

0.85

·VCEsat

IC = 50mA, IB = 5mA

28

-

1.7

3.0

29

-

0.47

30

-

0.78

Collector-to-Emitter
Saturation Voltage

c

VCE= 3 V, IC = lOrnA

c

V

-

For Transistors a1 and a2 (As a Differential Amplifier):
Absolute Input Offset
Voltage

1VIOl
VCE = 3V, IC = lmA

Absolute Input Offset
Current
•

1'101

A maximum dissipation of 5 transistors x 150mW

=

750mW is possible for a particular application.

7-54

CA3146, CA3146A, CA3183, CA3183A
TYPICAL STATIC CHARACTERISTICS CURVES 10

10":

BASttuRR[NTllal'Q

CA3146 SERIES

[MITTER CURllENT II 1·0

~ 110 CCUD:TOft-Tl)-DUTTER YOLTAG( IV~"V

".

~

....'DlTf[MPt:III,NREtT,,'.It5"C

,.,.>t---t----t-'~'/
//

"

AM8J[IIY TEIU'£R""UAEITAI-"t

.. "01
I
COLLECTCfIctMR£NTCleI-_"

AWIUENTJEMP[RAJUREITAJ-'C

Fig. 3 - I CBO vs. TA for any transistor• •"

Fig. 2 - ICED vs. TA for any transistor.

Fig. 4 - hFE vs. I C for any transistor. '

,
.... BIENT TtMPEIIArUREITA'--C

COLLECTOfICl.llRENTllc:'-1IIA

Fig. 6 - VCE sat vs. lefor a~y"'"
transistor.

Fig. 5- VBEvs. TAforanyt;;;;ritor.

Fig. 10 - VIO vs. TA for a Tand a2.

f

w "r--t-+lH-t----1b!4-+t---t-t+H'

~

~o~~~--~~-+-4~H-~-+4H1,.

6

f

/'

~

Ill:

11

<

~

e

r
o

, ;;

-~-/-

I~~T OFFSET VOLTAGE-\'lBt\ ~
IIII I I II

I

2

" 6 'QI

2

• • 8,

2

S
4

&

'10

001

tMITTER IAI.IAIoII'£A[SII,[1

I

" . '01

Z

"Ii' I

COLUCTOf' MILL,I"MPERU

Fig. 11- VBEand VIO vs. lEfor aT and a2.

3GHz

The CA3227 and CA3246* consist of five general purpose
silicon n-p-n transistors on a common monolithic
substrate. Each of the transistors exhibits a value of tr in
excess of 3GHz, making them useful from DC to 1.5GHz.
The monolithic construction of these devices provides close
electrical and thermal matching of the five transistors.

• Five Transistors on a Common Substrate

Applications
• VHF Amplifiers
• VHF Mixers
• Multifunction Combinations-RF/Mixer/Oscillator
• IF Converter

The CA3227 is supplied in a l6-lead Small Outline
package (M suffix) and in 16-lead dual-in-line plastic
package (E suffix). The CA3246 is supplied in a 14-lead
Small Outline package (M suffix) and in a 14-lead dual-inline plastic package (E suffix).

• IF Amplifiers
• Sense Amplifiers

'Formerly RCA Oeve!opmenl Nos. TA10854 and TA10855. re.pecllvely.

• Synthesizers
• Synchronous Detectors
• Cascade Amplifiers

Schematic Diagrams

FIGURE 1. SCHEMATIC DIAGRAM OF CA3227

MAXIMUM RATINGS, 'Absolute-Maximum Values at TA = 250 0
POWER DISSIPATION, Po:
Anyone transistor ................................. 85mW
TolBI Package:
ForTAupt0750C ................................ 425mW
ForTA> 750 C ••••••••••••••• Derate Unearlyat 8.67mWJOC
AMBIENT TEMPERATURE RANGE:
Operating .............................. -550 Cto+125OC
Siorage ................................ -6SOC to +1500c
LEAD TEMPERATURE (DURING SOWERINGj:
At dlslance 1/16 ± 1/32 In. (1.59 ± 0.79 mm) from case for
10 seconds max...................................... +265OC
The following ratings apply for each transistor In the device:
COLLECTOR-TO-EMITTER VOLTAGE, VCEO ............... 8V
COLLECTOR-To-BASEVOLTAGE, VCBO ••••••••••••••••• 12V.
COLLECTOR-TO-SUBSTRATE VOLTAGE, VCIO§ .......... 2OV
COLLECTOR CURRENT,IC •••••••.•••...••••••••••••••• 20mA

FIGURE 2. SCHEMATIC DIAGRAM OF CA3246

§ The coIleclor of each lranslslor of Ihe.e devlees Is Isolaled from Ihe subslrate by an Inlegral diode. The subslrale (lerminal 5/CA3227E and lermlnal 131
CA3246E) must be connecled 10 Ihe most negative polnlln !he exlernat elreuilla malnlain Isolallon belwesn IransIsIora and 10 provide for normallranslstor

acIIon.
CAUTION: These davie.. are sensllve to eleclroslelle discharge. Proper I.C. handling procodur.. should be followed.
Copyrighl @ Harris Corporation 1891

7-58

File Number

1345.1

CA3227, CA3246
STATIC ELECTRICAL CHARACTERISTICS at TA=2So C
CHARACTERISTIC

I

Min.

LIMITS
Typ.

IC=10pA,IE=0

12

20

-

V

IC=l mA, IB=O

8

10

-

V

20

-

-

V

10
1
100

pA

SYMBOL

TEST CONDITIONS

V(BR)CBO
V(BR)CEO

I

I

Max.

UNITS

For Each Transistor:
Collector-to-Base
Breakdown Voltage
Collector-to-Emitter
Breakdown Voltage
Collector-to-Substrate
Breakdown Voltage
Emitter-Cutolf-Current·
Collector-Cutoff-Current
Collector-Cutoff-Current
DC Forward-Current
Transfer Ratio
Base-Io-Emitter Voltage
Collector-to-Emitter
Saturation Voltage
Base-to-Emltter
Saturation Voltage

V(BR)CIO
lEBO
ICEO
ICBO

IC1=10pA,IB=0,
IE=O
VEB=4.5 V, IC=O
VCE=5 V, IB=O
VCB-a V, IE-O
IC-l0 mA

-

pA
nA

hFE

VCE=6V

IC=l mA
IC-O.l mA

40

-

150

-

VBE

VCE=6V

IC=l mA

0.62

0.71

0.82

V

110
150

VCE(sat)

IC=10 mA, IB=l mA

-

0.13

0.50

V

VBE(sat)

'IC=10 rnA, IB=l rnA

0.74

-

0.94

V

·On small-geometry. high-frequency transistors, it is very good practice neverto take the Emiller Base Junction into reverse breakdown. To
do so may permanently degrade the hFE. Hence. the useof lEBO ratherthan V(BR)EBO. These devices are also susceptible to damage by
electrostatic discharge and transients in the circuits in which they are used. Moreover, CMOS handling procedures should be employed.

en

~

rx:

g
--Q)-...,.-"4'- -l,

,
I

I

I
I

Figure 12 shows the typical waveforms generated during
this mode of operation, and Figure 13 gives the family of
time delay curves with variations in R1 and Cr.

T
FIGURE 14. REPEAT CYCLE TIMER
(ASTABLE OPERATIONAL)

Repeat Cycle Timer (Astable Operation)
Figure 14 shows the CA555 connected as a repeat cycle
timer. In this mode of operation, the total period is a function
of both R1 and R2.

T= 0.693{R1 +2R2)CT=t1 +t2
where t1 = 0.693 (R1 = R2) CT
and t2 = 0.693 (R2) CT
the duty cycle is:
t2
R2

Typical waveforms generated during this mode of operation
are shown in Figure 15. Figure 16 give the family of curves
of free running frequency with variations in the value of (R1
+ 2R2) and CT.

8-7

CA555, CA555C, LM555C

~

.v

I

1

O!-_U

I~

I

I

f-I

U

1\

\

I
I

I
I

I
I

I
I

f...J

..J

..J

1\

1\

\

3.3V -

II \
1.7Y

- .-"

0

Top Trace: Output voltage 12V/div. and
0.6 ms/div.l
Bottom Trace: Capacitor voltage (1 VI
div. and 0.6 ms/div.l

2 46B

10- 1

FIGURE 15. TYPICAL WAVEFORMS FOR REPEAT CYCLE
TIMER

2468

I

2468

2468

10
10 2
FREQUENCY-Hz

2468

10 3

2: 4681

10'"

10'

FIGURE 16. FREE RUNNING FREQUENCY OF REPEAT
CYCLE TIMER WITH VARIATION IN
CAPACITANCE AND RESISTANCE

8-8

CA1391
CA1394

mHARRIS

TV Horizontal Processors

August 1991

Features

Description

• CA1391E - Positive Horizontal Sawtooth Input

The Harris CA1391E and CA1394E are monolithic
integrated circuits designed for use In the low-level
horizontal section of monochrome or color television
receivers. Functions include a phase detector, an oscillator,
a regulator, and a pre-driver.

• CA1394E - Negative Horizontal Sawtooth Input
• Internal Shunt Regulator
• Linear Balanced Phase Detector
• Preset Hold Control Capability
• Pull-In • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• ±300Hz (Typ.)

The CA 1391 E and CA 1394E are electrically equivalent and
pin compatible with industry types 1391 and 1394 in similar
packages.
These types are supplied in an 8-lead dual-in-line plastic
(Mini-DIP) package, and operate over an ambient
temperature range of 0 to +85 0 C.

• Low Thermal Frequency Drift
• Small Static Phase Error
• Variable Output Duty Cycle
• Adjustable DC Loop Gain

Pinout

Functional Block Diagram

CA1391E, CA1394E
(PLASTIC MINI-DIP)
TOP VIEW

PHASE
DETECTOR
OUTPUT

OSCILlATOR
TIMING

OUTOs ~~'SPACE
GND 2

S~~3
HORIZ 4

IN

7

~~NG

8V+
5

OUT

PHASE
DETECT

HORIZONTAL
SAWTOOTH
INPUT

FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE CA1391 E, CA 1394E

CAUTION: These devices are sensitive
Copyright @ Harris Corporation 1991

to

electrostatic discharge. Proper I.C. handling procedures should be followed.

8-9

File Number

981.1

CA 1391, CA 1394

v'

•

RI.
I.ll

PHASEDETECTOR

REGULATOR

RI.
200

C~~----------~----~---i~------~

92CM-26340

Fig.2 - Schematic diagram of CA 1391 E, CA 1394E.

8-10

CA1391, CA1394

+6V
+25V

6200

IW

2000

IOn

•

I

14110

1500

53
43011

150

6800

10011

Q'F
'_F

5'
I.: 11.11

1.65

57

'"

1500

•
•

I

.6

92CM-28749

Fig.3 - DC test circuit.

+
4KR
lOW

I!SOV

2.4 kR

]

O.lI'~O.J~

390
kR

3.9
kR

1.2 kR

l.S

20V p-p
51'S

\J
60 V p-p
lOps

92CM- 28750R2

Fig.4 - Typical C'ircuit application.

8-11

Specifications CA 1391, CA 1394
Absolute Maximum Ratings TA = 250 C. Unless Otherwise Specified.
DC Supply Current ••••.••••••.•.•••••••.••••.•.•••••••.••••..•••.••.••••••••••••••••..••• 40mA
DC Output Voltage .••••.••...••..••••••••.•••••••.••••••.•••••••.•••.••••••.••••••.•••••••• 40V
DC Output Current •.••.••••••••.••..•...••••.••••••••••••••.••••..•.•••..•.•.•..•••.•.•.• 30mA
Sync Input Voltage •.•••.•••••••..••.••••••••••••.•••••••.••••.••.•••.•••••.•••.•••.•••.• 5Vp_p
Sawtooth Input Voltage ••.••.•••••••.••..••••••.•••••••••••••••••.•••••••••.•••••••••..•. 5Vp_p
Device Dissipation:
UptoTA=250 C ••••.••.••••••••••••..••••••••••••••••••••••••••••••••••••••••••••.•• 625mW
Above TA = 250C Derate Linearly .•.•••.•••.••••••••..••••••••••••.••.•••••••.••••••.• 5mW/OC
Ambient Temperature Range:
Operating •......•....•....••••.•••••••••.••••••••..••••.•••••••.••••••.•••••••••• 0 Ie +850C
Storage •..•..••.•••..••.••••.••••••.•.••••.••••.•••••••••..••••••.••.••.••••.• -65 to +1500C
Lead Temperature (During Soldering):
At Distance 1/16 ±1/32 in. (1.59 ± O.79mm) from Case for 10 Seconds Max••••••••••••••••. +2600 C
Thermal Resistance. • • • • . • • • . • • . • • • • • . • • • • • • • • . • • . • . • • • • • • • • • • • • • • • • • . • • • • • • • . • • . • • • •• 2000 C/W

ELECTRICAL CHARACTERISTICS at TA = 25°C (See Fig.3)
CHARACTERISTIC
Supply Voltage

Free·R unning
Frequency
Output Leakage
Output 5aturation
Phase Detector Bias
. Phase Detector Leak
Phase Detector Low

Phase Detector High
Phase Detector Balance
5ync Diode
5tatic Phase Error
Oscillator Pull·in Range
Oscillator Hold-in Range

TEST CONDITIONS

Min.

51,5S,56- 2
52,53, S4, S7, 58 = 1
8
Measure term. 6 to Gnd
51,5S,S6= 2
S2, 53, 54, S7, S8 = 1
14734
Counter to term. 1
S2, 53, 56, 58 - 1
51, S4, 5S, 57 = 2
Measure term. 1 to 2S V
52, 53, 5S, 56, 58 = 1
51,54,57 = 2
Measure term. 1 to Gnd
52, 5S, 56, 58 - 1
51,53,54,57 = 2
Measu re term. 3 to G nd
5S, 58 = 1
-2
51,52,53,54,56,57 = 2
Measu re term. S to +4 V
Sl,5S,58-1
52, 53, 54, 56, S7 = 2
-O.SS"
Measure term. S to +4 V
51,SS,56,58= 1
52, 53, 54, S7 = 2
+O.SS"
Measure term. 5 to +4 V
-100
VDET2 + VDET3
Sl, 52, S3, 54, 56, 57 = 1
0.3
55,58 = 2

-

5ee Fig.4

-

" Polarity reversed in the CA 1391.

8-12

LIMITS
Typ.

Max.

-

9

V

-

16734

Hz

10

-

mV

60

-

mV

1.9

-

V

-

+2

mV

-

-

V

-

-

V

-

+100

mV

1.2

V

O.S
±300
±900

-

-

UNITS

f.1S

Hz
Hz

CA 1391, CA 1394
The phase detector is isolated from the
remainder of the circuit by R31, Z2, 015
and 016. The phase detector consists of
the comparator 022 and 023, and the gated
current source 018. Negative·going sync
pulses at terminal 3 turn off 017, and the
current division between 022 and 023 is
then determined by the phase relationship
of the sync and the sawtooth waveform at
terminal 4, which is derived from the hori·
zontal flyback pulse. If there is no phase
difference between the sync and sawtooth,
equal currents flow in the collectors of 022
and 023 during each half of the sync pulse
period. The current in 022 is turned around
by current mirror 020 and 021 so that there
is no net output current at terminal 5 for
balanced conditons. When a phase offset
occurs, current flows either in or out of
terminal 5. I n circuit applications, this ter·
minal is connected to terminal 7 through an
external low·pass filter, thereby controlling
the oscillator.
Shunt regulation for the circuit is obtained
by using a VBE and zener multiplier. Resistors R 13 and R 14 multiply the VBE of
011, and the ratio of R15 and R16 multiplies the voltage of the zener diode Zl.

CIRCUIT OPERATION
(See schematic diagram, Fig.2)
The CA 1391 and CA 1394 contain the ascii·
lator, phase detector, and predriver sections
necessary for the television horizontal ascii·
lator and AFC loop.
The oscillator is an RC type with terminal 7
used to control the timing. If it is assumed
that Q7 is initially off, then an external
capacitor connected from terminal 7 to
ground charges through an external resistance
connected between terminals 6 and 7. As
soon as the voltage at terminal 7 exceeds the
potential set at the base of 08 by resistors
R 11 and R 12, 07 turns on, and 06 supplies
base current to 05 and 010. Transistor 05
discharges the capacitor through R4 until
the base bias of 07 falls below that of 08,
at which time, 07 turns off, and the cycle
repeats.
The sawtooth generated at the base of 04
appears across R 3 and turn off 03 whenever
the sawtooth voltage rises to a value that
exceeds the bias set at terminal 8. By ad·
justing the potential at terminal 8, the duty
cycle at the pre·drive output (terminal 1)
may be changed.

~

5
..... u

«

;=
U)

:::: :::1 iii

:

:j~ :!U

::: iii! i !
.: :::: ! ii!
::,: ::'; I l.
i!"

Uli

:

I111

:

:

i

>H

Hi: iii: :;1:
:i:: ;:,; :
iii; lillli!
-3 )0

!

:

i

:
I

:

I

tn

: I!!

In

:lk
i:::1i:i

",:H

iHiiliii

-2')0
-I
II
lO
300
400
OSCILLATOR FREE-RUNNING FREQUENCY OEVIATION
IN Hz FROM 3.579545 MHz
92C$-25000

Fig. 5-Static phase error.

8-25

CA3126

Thermal Considerations
The circuit of the 'CA3126 is thermally compensated to
achieve the optimal operating characteristics over the normal
operating temperature range of TV receivers. Figs. 6 and 7
show the oscillator- and chroma-output amplitudes and phases
as a function of temperature (Terminals 8 and 15). respectively.

~

~
>

~

'"

+

g
I-

..J

j!:: :::'

g

70

... '"

:ro

-10

~

'"o

G

-J5 (,)

AMBIENT TEMPERATURE (TA)-"C

AMBIENT TEMPERATURE (TA)-"C
92CS-25002

92CS-25001

Fig. 6-Amplitude and phase variations of oscillator
output vs. temperature.

Fig. 7-Amplitude and phase variations of chroma
output vs. temperature.

1l1:ROMA INPUT =0 v p _ p

I

y

>-N

o:r 100

z'"

~~
"'~~

.

z..,
z'"
Zo
'!'IL
",N

i; :

"0:

",r

:

11'i:

! ,
;;:' !

!

I::; 1':

o:z
IL-

i':

~~

:

~o

I

;

co'

:

Iii;
-1501Hi
-50

c(

~

0:

1-10
.0

-l

I

o

o

.6()

o

0-

..J

I

-;0

"S

~..J

,'Ip!

'"

I-

0:1L

iU:!;

0

...~

-50.0:

1;!i;lli!

0

I

I-

~+

60:

0:

~..J

ffio

I~

!("'.~

I:': :,:i

..J

...'"-"

ttl 3

....

o:~

~,

o

o

0'"

....

>

l!I
IL

IL

IL

o

IL

z
o
~

~+

o

o

I

..J

,S!

N

CHROMA INPUT =0.25 Vp_ p
3.56-MHz CW SIGNAL

"'"~

z

CHROMA INPUT' 0.25 Vp _p • 3.56-MHz CW SIGNAL 15

'"3

Both the oscillator- and chroma-output amplitudes and phases
are measured relative to the chroma-input phase. The performance of the oscillator free-running frequency as a function
of temperature is shown in Fig. 8. All the temperature plots are
characteristic of the test circuit with the indicated component
types and values given in Fig. 3.

lil

::

ill
i
111

-25

,
;

,
,

!ili
ii,: i'li

,

Hi::)
tli; illl

7!
25
AM61ENT TEMPERATURE (TA)-"C

1'0

115

92CS-25003

Fig. 8- Variation of oscillator free-running frequency vs. temperature.

8-26

CA3189

EDHARRIS

FM IF System

August 1991

Features

Description

• Includes IF Amplifier, Quadrature Detector, AF
Preamplifier, and Specific Circuits for AGC, AFC,
Tuning Meter, Deviation-Noise Muting, and ON
Channel Detector

The Harris CA3189E* is a monolithic intergrated circuit that
provides all the functions of a comprehensive FM-IF sys'
tern. Figure 1 shows a block diagram of the CA3189E,
which includes a three-stage FM-IF amplifier/limiter config'
uration with level detectors for each stage, a doubly-bal'
anced quadrature FM detector and an audio amplifier that
features the optional use of a muting (squelch) circuit.

• For FM IF Amplifier Applications in High-Fidelity,
Automotive, and Communications Receivers
• Exceptional Limiting Sensitivity. • • • • • •• 121lV (Typ.)
@-3d8 Point
• Low Distortion ••••••••••••••••••••••••• 0.1 % (Typ.)
(with Double-Tuned Coil)
• Single-Coil Tuning Capability
• Improved S + N/N Ratio
• Externally Programmable Recovered Audio Level

The CA3189E Is Ideal for high-fidelity operation. Distortion
In a CA3189E FM-IF System is primarily a function of the
phase linearity characteristic of the outboard detector coli.

• Provides Specific Signal for Control of Interchannel
Muting (Squelch)
• Provides Specific Signal for Direct Drive of a Tuning
Meter
• On Channel Step for Search Control
• Provides Programmable AGC Voltage for RF
Amplifier
• Provides a Specific Circuit for Flexible Audio
Output
• Internal Supply-Voltage Regulators

The advanced circuit design of the IF system includes
desirable deluxe features such as programmable delayed
AGC for the RF tuner, an AFC drive circuit, and an output
signal to drive a tuning meter and/or provide stereo
switching logic. In addition, internal power-supply
regulators maintain a nearly constant current drain over the
voltage supply range of +8.5 to +16 Volts.

The CA3189E has ail the features of the CA3089E plus
additions. See CA3189E features compared to the
CA3089E in Table 1.
The CA3189E utilizes the 16-lead dual-in-line plastic
package and can operate over the ambient temperature
range of -400 C to +850 C.
"Formerly Developmental Type No. TA10038.

• Externally Programmable "On" Channel Step
Width, and Deviation at Which Muting Occurs

Pinout

Absolute Maximum Raglngs TA = 25 0 C
CA3189E (PLASTIC DIP)
TOP VIEW

DC Supply Voltage
(Between Terms. 11 and 4) •••••••••••••.•••••••••••••••• 16V
(Between Terms. 11 and 14) ••••••.•.•••••.•••••••.••••• 16V
DC Current (Out ofTerm. 15) ••••••••••••••••••••••••••••• 2mA
Device Dissipation:
UptoTA=850 C ••••••••••••••.••••••••••••••••••• 640mW
Above TA = 850 C •••••••••••••••• Derate Linearly at 9.9mWfOC
Ambient Temperature Range
Operating ••••••••••••••••••••••••••••••••••• -40 to +850 C
Storage ••••••••••••.•••••••••.•••••••.••••• -65 to +1500 C
Lead Temperature (During Soldering):
At Distance Not Less Than 1/32 Inch (0.79mm)
from Case for 1 Os Max•••••••••••••••••••••••••••••• +2650 C

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed,

Copyright @ Harris Corporation 1991

8-27

File Number

1046.1

Specifications CA3189
ELECTRICAL CHARACTERISTICS. at T A = 250 C. V+ = 12 Volts
LIMITS

TEST CONDITIONS
CHARAC·
TERISTIC

UNITS
Circuit
or
Min. Typ. Max.
Fig. No.

SYMBOL

Static (DCI Characteristics
Quiescent Circuit
Current

111

20

31

DC Voltages:
Terminal 1 (I F Input)

V1

1.2

1.9 2.4

V

1.2

1.9 2.4

V

40

mA

Terminal 2 (AC
Return to Input)

V2

Terminal 3 (DC
Bias to Input)

V3

1.2

1.9 2.4

V

Terminal 15
(RF AGC)

V 15

7.5

9.5

11

V

Terminal 10 (DC
Reference)

VlO

5

5.6

6

V

-

12

25

fJ V

45

55

-

dB

3,4

No signal input.
Non muted

Dynamic Characteristics
Input Limiting Volt·
age (-3 dB point)
AM Rejection
(Term. 6)
Recovered AF
Voltage (Term. 6)
Total Harmonic
Distortion:*
Single Tuned (Term.
6)
Double Tuned
(Term. 6)

VI (lim)
AMR
VO(AF)

THO

VIN =
.0.1 V

S+ N/N

Deviation Mute
Frequency

fDEV.

3,4
fa = 10.7
MHz,

fmod' =
400 Hz,

Deviation
±75 kHz

THO

Signal plus Noise to
Noise Ratio
(Term. 6)

R F AGC Threshold

VIN =
0.1 V.
AM Mod.
=30%

fmod. =0

V 16

On Channel Step
V 12

VIN=
0.1 V

325

>

fDEV.
±40 kHz

mV

3

-

0.5

4

-

0.1

-

%

3,4

65

72

-

dB

1

%

3,6,7

-

±40

-

kHz

3,4

-

1.25

-

V

3

-

0

-

V

<

fDEV.
±40 kHz

500 650

-

5.6

-

*THD characteristics are essentially a function of the phase characteristics of the network connected
between terminals 8, 9, and 10.

8-28

CA3189
AL.L AESISTANCE VAlues ARE IN OHMS
• L TUNES WITH 100 flF lei AT 107 MHI

aD;; Ti5lTOKO ND KACS K586HIII OR
EQUIVALENT.)

OK

~~kA:OE:-rly-~~~J
RF AMP!.

TO STER(O
THRESHOLD

LOGIC CIRCUITS

U
ON CHANNEL
INDICATOR

4"
Fig. I - Block diagram of the CA31B9E.

~
:5

..... 0

«0::

00
WCJ

0..

en 0.....

«
«

:z

L£VEl DETECTOR III METER CIRCUIT

Fig. 2 - Schematic diagram of the CA3189E (cont'd on next page).

8-29

CA3189
TABLE I - CA3189E Features Compared to CA3089E
FEATURES

CA3189E

CA3089E

Low Limiting Sensitivity (1 2IJ.V typ,)

Yes

Yes

Low Distortion

Yes

Yes

Single-coil Tuning Capability ,

Yes

Yes

Programmable Audio Level

Yes

No
Yes

SIN Mute

Yes

Deviation Mute

Yes

No

Flexible AFC ,

Yes

Yes

Yes

No

Yes

No

Yes

No

Yes

No

Programmable AGC Threshold and Voltage
Typical S + NIN

> 70 dB

Meter Drive Voltage Depressed at Very'
Low Signal Levels
On-Channel Step Control Voltage

DEVIATION MUTE DETECTOR
AND AFt ANI'Ll.

Fig, 2 - Schematic diagram of the CA3189E Ccont'd from previous page),

8-30

CA3189
V+~12V

DC VOLTAGE SUPPLY V+oI2V
AMBIENT TEMPERATURE (TA}o+ZS-C
TEST CIRCUIT - SEE FIG. 3

~ o SEE
~
ili

"

RECOVERED AUDIO FROM FULL
OUTPUT (LEFT CO-ORDINATE)

-I0f-::==Ij~=:j:==t----jl---j'o
j~
t§!i -20
B ~
g
ffi!;t
6 g
ffi..J -30
ma:

..o.
>0

.)-<§)--,:,+_AUOIO
OUTPUT

§~

a:8- 40
~

~

-50
-60
10

100
Ik
INPUT SIGNAL - " I I

10k

lOOk

Fig. 5 - Muting action, tuner AGe, and tuning
meter output as a function of input
signal voltage.

S~P~P~LY~I~V~+I~"~2~V::llllli~
(TA)~25·C·

AMBIENT TEMPERATURE

ALL RESISTANCE VALUES ARE IN OHMS
*L TUNES WITH 100pF (C) AT 10.7 MHz
QaIUNLOAOEO}:lE75 (TOKO No KACS K58SHM OR EQUIVALENT)

200 DC
SEEPOWER
TEST CIRCUIT, FIG 3

"i~
~

5 kll

15

.

**C;O.OI J£F FOR 50 J£s OEEMPHASIS (EUROPE)
=0.015J£F FOR 751£5 DEEMPHASIS (USA)

,..A

"~ 100

::;

" '0

~

Fig. 3 - Test circuit for CA3189E using a singletuned detector coil.

-'0
-100
-150
100

50
-'0
CHANGE IN FREOUENCY (6t)-kHz

100

150

Fig. 6 - AFC characteristics (current at Term. 7
as a function of change in frequency).
DC SUPPLY VOLTAGE (V+)-12V
AMBIENT TEMPERATURE (TA)=25°C

V+=12V

120
100

60
60

5K

~§)--+.AUDID

c**

1

40

OUTPUT
20

o

10
15
20
LOAD RESISTANCE(BETWEEN TERM 7 AND TERM.IO)-kQ

470

25

Fig. 7 - Deviation mute threshold as a function
of load resistance (between Term. 7
and Term_ 10).

a -

-

-10, /"

~IGNA~E~IATION' ±j5kH~

/

==

ALL RESISTANCE VALUES ARE IN OHMS
itT: PRI.- Qo(UNLOAOED)S7S(TUNES WITH 100 pF (CI) 20t OF 34e ON

-20

7/32" OIA. FORM
SEC.-Qo(UNLOAOEDIS75 (TUNES WITH 100pF(C2) 20t OF34e ON
7/32" orA FORM
kQ(PER CENT OF CRITICAL COUPLING) a 70%
(ADJUSTED FOR COIL VOLTAGE Vc );150 mV

-30

~

-40

ABOVE VALUES PERMIT PROPER OPERATION OF MUTE (SQUELCH) CIRCUIT
nE" TYPE SLUGS, SPACING 4mm
**CoO.OI,..F FOR 501£5 OEEMPHASlS (EUROPE)
-O.OI5J£F FOR 75 JlS OEEMPHASIS (USA)

-'0
60

\\ '\
\

\"\.
,

"

-70

Fig. 4 - Test circuit for CA3189E using u doub/etuned detector coil.

~~II~~i ~~~~EDED

BY
FILTER AND GAIN STAGE
_ _ _ CA31B9E PRECEDED BY
2 FILTER AND GAIN STAGES

'

'''':'''

I

I
~NOISE

A

--

"-

-60
10

~

4

10

SIGNAL LEVEL-,..V

Fig. 8 - Typical limiting and noise characteristics.

8-31

CA3189

1.8 II.

3.311.

390

1

10nF

+12V

3.311

AFT

12.
IO.7~

~~~~R

IflF

AUDIO

22.

2.211.

470

10

of

Al.l RESISTANCE VALUES ARE IN OHMS

CF: CERAMIC FILTERS, TOKO CSFE OR EQUIVALENT
*L TUNES WITH 100 pF eel AT 10.7 MHz
00 IUNLOADED);175 (TOKO No. KAtS 1<586 HM
OR EQUIVALENT!

RF AGe .

ov
92CL-29958RI

Fig. 9 - Complete FM IF system for high-quality receivers.

8-32

CA3194

mlHARRIS

Single Chip PAL
Luminance/Chroma Processor

August 1991

Features

Description

• All PAL Luminance and Chrominance Processing
Circuitry on a Single Chip in a 24-Lead Plastic
Package

The Harris CA3194E* is a sillcon monolithic Integrated
circuit designed to perform all of the signal processing
functions for both the chroma and luminance signals of PAL
color television receivers.

• Phase-Locked Subcarrier Regeneration Utilizing
Sample-and-Hold
• DC Controls for Brightness, Contrast, and ColorSaturation Functions
• Input for Average Beam-Current Limiting
• Contrast Control Having Excellent Tracking of Luma
and Chroma Channels
• Low-Impedance RGB Outputs with Excellent
Tracking for Direct Coupling to Video Driver
Circuitry

This circuit performs all the functions needed between the
video detector and the video RGB output stages. DC
contrast, brightness. and saturation controls and average
beam limiting functions are included. The RGB buffer
stages are capable of delivering SmA of current into the
video output stages.
The CA3194E is supplied in the 24-lead dual-in-line
plastic package.
ill

Formerly RCA Dev. No. TA10313.

Pinout
TERMINAL VOLTAGE AND CURRENT RATINGS

CA3194E (PLASTIC DIP)
TOP VIEW

VOLTAGE*-V
TERMINAL
BRIGHTNESS COMTROI.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

PICTURE COMTROL

WMA INPUT

ACC FILTER

APe FILTER

PEAK BEAM LEVEL.:
R OUTPUT
G OUTPUT
B OUTPUT

CURRENT-mA

MIN.

MAX.

liN

-

-

-

-

13
8
5

0
10

30

0
0
0
0

-

0
0
0
0
0
0
0
0

Note

-

Note
Note

8
8
13
13
12
5
5
13
13
13

0

0
0
0
0
0
0
0
0
0

Note

5
Note

8
5
12

-

--

0.1

-

----

lOUT

-0.5
--

0.7
10

--

1.5
1.5
10
10
10

-----

NOTE: The maximum should not exceed the VCC voltage. Voltage with
respect to Terminal 1 for VCC (Terminal 12) of 12V ±10,*,.

CAUTION: These device. are .ensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

8-33

File Number

1270.1

CA3194

Circuit Description

(See Figures 1 and 6)

The chroma signal is externally separated from the video
signal by means of a bandpass or high-pass filter and
applied to pin 4. The burst is separated In the first chroma
stage and applied to ;the synchronous detector which
procldes Information to sample-and-hold circuits for APC
(phase-locked loop), ACC (automatic chroma gain control)
and identification and killing. The 4.43-MHz crystal
oscillator is phase-locked to the burst and provides 0 0 and
900 (via an external phase shifter) carriers to the chroma
demodulators. The burst and chroma amplitued at the
output of the first chroma amplifier Is kept constant by the
automatic gain control.

The second chroma stage provides saturation control (pin
3) which tracks the contrast control In the luminance
channel. This stage is also used for color killing.
A buffer stage drivers the external PAL delay line. The
separated U and V signals are applied to pins 14 and 15,
respectively, and demodulated. A standard G-V matrix Is
included on the chip.
The luminance signal passes through the sub carrier trap
and through the luminance delay line and enters the chip at
pin 20. Contrast and brightness control is provided before
the luminance signal is combined with the color difference
signals in the V matrix. Average and peak beam limiting
circuits are controlled from pins 24 and 19.

CHROMA
INPUT

VCO
OUTPUT

CHROMA
OUT

~~~~:::;-~~~~~~~~~=====~-!--(13
~::!!~~~====-------i..(16

SANDCASTLE
B OUTPUT

1---+---+-~------+..('7 G OUTPUT
VR-Y
INPUT

1---+---+-+-~-----+..(18 R OUTPUT

f-@vcc
:

r,"\

GROUND

~(SUBSTRATE)
______________ .J

PICTURE
CONTROL

AVER.
BEAM INFO.

8RIGHTNESS
CONTROL

Fig. 1 - Block diagram.

8-34

PEAK
BEAM LEVEL

92CL-32909RZ

Specifications CA3194
Absolute Maximum Ratings
DC Supply Voltage and Current:
Pin 12 Vollage Range .••••••••••••.••••••••••••••••.•••••••••••••••••••••..•••••••••••••••••••••••••••.•••••••••• 11 Min. to 13 Max. V
Pin 12 Current Range ......................................................................................... 44 (Typ.) to 60 Max. mA
Device Dissipation:
UptoTA= 250C ........................................................................................................... 825mW
Above TA = 250C ....................................................................................... Derate Linearly @ 8.7mW/oC
OJC Max. = 1150 C/W. TJ Max. = 150°C
Ambient Temperature Range:
Operating ............................................................................................................-40 to +850C
Storage ............................................................................................................ -65 to +1500C
Lead Temperature (During Soldering):
AtDislance 1/16 ±1/32 in. (1.59 ± 0.79mm) from Case for 10 Seconds Max................................................'...... +2650 C

Electrical Characteristics TA = 250C. VCC = 12V. Vs = 2.85V. Vc = 2.85V. VAB = VpB = VCC. VB adiusted for V18 = 6.3V. Cx adiusted
for FOSC = 4.43361875MHz. SandcasUe: VBG = 8.0V. VBLANK = 3.5V-Burst Gate centered on Burst. These
conditions exist except as otherwise noted. See Figure 5 for test circuil.

CHARACTERISTIC

TEST CONDITIONS

TYPICAL
VALUE

UNITS

LUMINANCE SECTION

Input Impedance-Term. 20
Luminance Channel Input Voltage
Bandwidth of Luminance Channel
Brightness Control Range-Term. 23
Output Black Level:
Range
Offset
Contrast Control Range-Term. 22

Luminance Gain Control Range
RGB Output Swing

Luma Input Slgnal=30% Sync
Luma Input Signal: 0.5 Vp_p (30% Sync) modulated CW
Adj. modulation frequency for -3 dB at color outputs
For control characteristics. See Fig. A .
Luma Input Signal: 0.5 Vp _p (30% Sync)
VB 0-5 V
Measured at Pin 18 tilack level. See Fig. A.
Luminance input: 0.5 Vp _p (30% Sync). for control
characteristics. See Fig. B.
Luminance Input: 0.5 Vp _p (30% Sync).
VC=0.5 - 5 V measure Pin 18 black level
to maximum white. level. See Fig. C.
Luminance Input: 0.5 Vp_p (30% Sync). VC=5 V.
read black level to peak white. See Fig. D.

6
5
0.5

kn
pF
VD- D

8

MHz

0-3.5

Vdc

5.9 - 9.7
0.6 Max.

Vdc

0-5

Vdc

32

dB

4

Vp_p

4.5
5
220
100
+6--20

kn
pF
mVp_p
mVp_p

10'

mVp_p

±5

%

0-5

Vdc

2.5

Vp_p

-_---"-(!

--""BLANK 2VTOSV

I

PEDESTAL

--- 0

I

v

I
I
I____

5.1 M

92CS-33098

J

Fig. 2 - Sandcastle/nput waveform.
KI LLER THRESHOLD LEVEL CONTROl
92C8-3451.

Fig. 3 - Killer-threshold level control.
~--------I

2

I

CHRJ=::I~~~PUT:

I
,.F

SK
27K

I
I

I
SATURATION
CONTROL

VCC

,
,

,
,
I

NOMINAL VALUES USED
IN NTSC SYSTEM

300

SIGNAL N-P-N
92CS-34517

Fig. 4 - External overload detector.

8-39

CA3194
BEAM
LIMIT
(VAB) INFO

(VB)

C~~~RAST

BRIGHTN.

OUTPUTS
I

R
IK

15K

SAND
CASTLE
INPUT

\

G

B

RC

15K

220n

IK

LUMA

IN~+
24

161'

23

22

20

8RIGHT- CONNESS
TRAST

AV.
BEAM
LIMIT

19

18

PEAK
BEAM
LIMIT

ROUT

17

16

GOUT

15
VR_ Y

BOUT

14
VB_ Y

13

CA~~~~

CA3194E

CHROMA

CHROMA
OUT

GND

CHROMA
INPUT

SAT.

ACC

ACC

APC

VCO
OUT

APC

B+

6

IN~
3n3

2K2

t
lOp

2K2

c.

39011
DELAY LINE
AMPLITUDE ">'"--~

l

r ,

5%
R.

1O %

3
DL 700

DL I II L4
PHASE IL ~IIOJLHI 47P

IOn

II'

41'71 22nr 0.11'1 12OP

47nr

SAT.
(Vs)

+

330

43011/5%

4

'

NOTE I TRIM C. FOR ZERO PHASE
TRIM R. FOR QUAD PHASE

if:

92CM-'528,3R2

4.43361875 MHz

Fig. 5 - Test circuit.
\YABI

BEAM
LIMIT
INFO

(VB)
(VC)
BRIGHTN. CONTRAST

OUTPUTS
I

R

SAND
CASTLE
INPUT

G

10K
2200
LUMA

IK

+ __+-__I-_--'

IN~r+'-t_ _
161'

24
AV.
BEAM
LIMIT

23
22
BRIGHT- CONNESS
TRAST

20

19

18

PEAK
BEAM
LIMIT

ROUT

17
GOUT

16

15

BOUT

CA3194E

CHROMA

GND

CHROMA
OUT

SAT.

CHROMA
INPUT

Veo
ACC

1~1-~_-+----4----4

ACC

APC

APC

6

303
2Kl

330

5%
R.

3.3,.
O.IJLl 12OPlIO%
lOp

Co

39011

r

DL
11L4
PHASE I
IIOJLHI47P

L

PAL DL 50

~

IOn

Fig. 6 - Application circuit for PAL M.

8-40.

14

13

II HARRIS

CA3217
Single Chip TV
Chroma/Luminance Processor

August 1991

Features

Description

• All Chroma Processing and Demodulating Circuitry
on a Single Chip in a 28-Lead Plastic Package

The Harris CA3217E· is a monolithic silicon integrated
circuit. It contains all the required circuit functions between
the video detector and the picture tube RGB driver stages of
a color television receiver. The CA3217E decodes the
chromlnance signals and then produces three different
color signals that are internally combined with the
luminance to develop the RGB signals. The picture
saturation, hue and brightness DC controls are externally
adjustable by the viewers. The AFPC, ACC, Dynamic flesh
control, Beam limiting and Gate black level (Brightness)
control are servo loops used to stabilize the RGB output
and reduce frequent manual adjustment The automatic
beam limiter circuit reduces picture contrast and brightness
to prevent excessive drive output at the picture tube.

• Phase-Locked Subcarrier Regeneration Utilizing
Sample-and-Hold Techniques
• Supplementary ACC with Overload Detector to Prevent Over Saturation of the Picture Tube
• Linear DC Controls for Chroma Gain and Tint
• Dynamic "Flesh Correction" - Corrects Purple and
Green Flesh Colors without Affecting Primary
Colors
• Balanced Chroma Demodulators with Low Output
Impedance for Direct Coupling
• Internal RF Filtering
• Requires Few External Components

The CA3217E is supplied in a 28-lead dual-in-line plastic
package.

• Automatic Beam Limiter

• Formerly RCA Dev. Type No. TAl 0806.

• Chroma Luminance Tracking Picture Control

Pinout

Absolute Maximum Ratings
CA3217E (PLASTIC DIP)
TOP VIEW

CHROMA

our

CHROMA CONTROL

1

~

~

CHRO~ iNPUT ~

O\IERLOAD FU..TER ~

ACe. KILLER ALTER•

-[ 5

6

SANDCASTLE PULSE

~

GND~
-[ 9
APe ALTER•
:;
OSCIllATOR IN

aoo

OSCIllATOR IN ,IIQO
OSCIUATOR OUT

28 BEAM UMlTER

~

WMINANCE

~ PICTURE CONTROL
~ LOW PASS ALTER

?1
ORlGtfT CONTROL
r.;:;
23 Vee

~

BLUE

~ RED

10
11

18 I CARRIER IN

g

TINT CONfROL 14

CAUTION: These devices are sensilive
Copyright @ Harris Corporation 1991

~

::;

-,0

3.3 v
I MaXimum Linear Output
R
G
B

Angle

1.0
93°
1.2
2°
0.3
258°
900 kHz
Primary control in the +1 half-plane
Two levels
40 dB
Black level clamped on 3 V to 5 V level
On picture and brightness controls
5 MHz min
Blanking
Burst gate
5 V
~

3.7 V

~

:::)

..... 0

 •.••••••• 18V
Control Input Voltage Range, All Inpuls •••.••••••..•• VEE 10 VCC
Signal Input Voltage Range, Channel 1-5 •••••••••.•.••.•• 3Vp-p
Amplifier Output Current •.••.•.••.•.••.•.••••••..•.•.••• 30mA
DC LED Sink Current •••.•••••••••.••••••..••.•••••••••• 30mA

Performance Data

Device Dissipation:
UptoTA=550 C ••••••••.••.••••••••••••.••••.•••• 630mW
Above TA = 55 0 C. • • • • • • • . • • . •• Derate linearly at 6.67mWfOC
Operating Temperature Range ..•••••.•••••••• -400 C to +850 C
Storage Temperature Range .•.•••••••••••••• -650 C to +1500 C
Lead Temperature (During Soldering) at Distance 1/16 ± 1/32 in.
(1.59 ± 0.79 mm) from case for 10sec max.••••••••••••• +265 0 C

TA = +250 C, Nominal Data for (VCC - VEE) = 12V

CHARACTERISTICS

SYMBOL

TYPICAL VALUES

UNITS

10to18

VDC

20

mA

Power Supply Voltage VCC - VEE
Power Supply Current VCC - VEE = 12V
SWITCH
Open Loop Gain

AOl

Programmable Gain, FB Adjustment Range
Power Bandwidth
Un~yGain

Bandwidth,lkO, 7pFCompensation

-

AMPLIFIER
35

dB

-0.8AOl

dB

10

MHz

25

MHz

Inserlion loss

-0.8

-

dB

Signal Feedthrough, 5MHz

-66

-

dB

10.

kO

ZOUT

-

5

0

Maximum Input Voltage

VI(max)

3

2.5

Vp-p

Maximum Output Voltage, Clipped

VO(max)

Input Impedance
Output Impedance

ZIN

-

7

Vp-p

Reference Bias Output Voltage (V8 - VEE)

-

5

VDC

Differential Gain

-

1

%

Differential Phase

-

1

Degree

-

dB

Off Isolation, Channel to Channel, ZIN = 750

-66

-

lCC Switch Turn On/Off Time Delay
Maximum lED Sink Current
Typical Output Source Current
Channel Control Switch A, B, C

EN Threshold

CAUTION: Connecl the VEE power supply voltage before or during the VCC turn-on.

8-52

0.5

~s

30

mA

-

16

rnA

6

-

V

Specifications CA3256
Electrical Specifications

TA = +25 0 C, vec = +12, VLED = +12, VEE = GND, Pin 4 = GND, Feedback Switch Closed,
VHIGH = 9V, VLOW = 3V (See Figure 3) Unless Otherwise Specified.
CHANNEL SWITCH CONTROL

INPUTS
CH1 CH2 CH3 CH4 CH5

B

C

ENABLE

PIN
15

PIN
17

PIN
1

PIN
3

PIN
13

PIN
16

PIN
18

PIN
7

PIN
6

TEST
PIN
#

MIN

TYP

MAX

UNITS

Supply Current,lcC
VLED=OV

OV

OV

OV

OV

OV

3V

3V

3V

3V

14

10

16

22

mA

Dual Supply Current
VS=±5V

OV

OV

OV

OV

OV

OV

OV

OV

5V

14/5

10

20

26

mA

Amplifier Output,
Open Loop
V8(OL)' VLED = OV

OV

OV

OV

OV

OV

3V

3V

3V

3V

9

6

8.5

10

V

Amplifier Output,
Closed Loop, VLED = OV

OV

OV

OV

OV

OV

3V

3V

3V

3V

9

4.8

5.1

5.4

V

lOUT MAX. (Source)
Open Loop

OV

OV

OV

OV

OV

3V

3V

3V

3V

9
Note 1

-

-70

-25

mA

lOUT MAX. (Sink)
Open Loop

OV

OV

OV

OV

OV

3V

3V

3V

3V

9
Note 2

10

16

-

mA

Input Leakage
Channel 1-5

3V

3V

3V

3V

3V

3V

3V

3V

3V

1,3,
15,17

-15

5

+15

nA

Channel Control Input
A, B, e, Enable Leakage

OV

OV

OV

OV

OV

Measure at 3V, 9Veach;
Enable and Channel
Switching Control Inputs

6,7,
16,18

-20

10

+20

nA

LEDOff,VOFF

OV

OV

OV

OV

OV

Select Channel 0-5

2,10,
11,12

11.97

11.99

-

V

LED On, VON

OV

OV

OV

OV

OV

Select Channel 0-5

2,10,
11,12

-

0.1

0.3

V

0.8

1.1

1.4

kO

CHARACTERISTICS

Switch Resistance, RDS

±1 OO~A Input Each Switch,
Channel 1-4 + 5

A

Select
Channel 1-4

9V

9V

-

-

3.6

5

%

Amplifier Output Offset
Vo Feedback Switch
Closed VSUP = ±5V

OV

OV

OV

OV

OV

OV

OV

OV

+5V

9

-100

45

+100

mV

Closed Loop Unity Gain

3V

OV

OV

OV

OV

3V

3V

3V

9V

9

-0.5

-0.1

+0.5

dB

Calculation: (Max RDS - Min RDS)/Min RDS

RDSMatch

NOTES:
1. VOUT
2. VOUT

= +3V.
= +7V.

8-53

CA3256

-SVYEE

YCC+SVTO+I2V

AMPLIFIER
TO CABLE
OUTPUT

75A

~t5A

lED INDICATOR CHANNa.. 1

)K~~____~~~~~____~~~____~YLED

lED INDICATOR CHANNa.. 2

20F5
INPUTS
SHOWN

lED INDICATOR CHANNa.. 3

lED INDICATOR CHANNa.. 4

WHERE AMPUAER GAIN:

CHANNa.. 5

O'!}:~-+ >-l

Ay =

ENABLE
CHANNa..
1-4

4

6

~+

L

Rf + lKJ X 0.9

10K

Le_ FOR Ay= 1.8
Rf= 9kA

FIGURE 2(a)_ TYPICAL APPLICATION BIAS CIRCUIT DIRECT-COUPLED OUTPUT WITH VEE

8-54

= -SV

CA3256
VEE
TO GND
O.Ij4F

lOOK

VCC
+ 12TO+ 18V

lOOK

V OUT2

lOOK

2.2 j4F
CHANNELl ~~
INPUT
75A

.t

LED INDICATOR CHANNEL I
~rt---------{12!}i~------~~----~

LED INDICATOR CHANNEL 2

20F5
INPUTS
SHOWN

LED INDICATOR CHANNEL 3
~~--------~'IO~e-----~~-----i

LED INDICATOR CHANNel 4

~~------~2·~G-----~~----~

Tn
2.2 j4F

CHANNEL 5
INPUTI
OUTPUT

~

WHERE AMPUFIER GAIN:

AV~

75A

ENABLE
CHANNEL

4

1·4
4.7K =GND

r,

L

+

Rf+ IKJ

FOR THIS CIRCUIT:
VCC= + 12V
A= 1.1 X
BW= IBMHz(SINEWAVE)
VOUT= IVpp
Rf=IK

FIGURE 2(b). TYPICAL APPLICATION BIAS CIRCUIT AC-COUPLED INPUT WITH VEE = GND

Waveform Display (Figure 2b) Pulse Performance = 20ns t,for 0 to 2V Pulse

Vee =+12V. Rf =1kO. eeOMP =6pF. Pin 9 at VEE(GND).
VOUT

8-55

Xo.a

10K

~

::>

-,0

~:n~
~CI
tng
«
z

«

CA3256

10K·

VEE

o---'VII'v--O Vee
OFF SET
ADJ.

VCC

BW(MHz)

+5
+7

20

+ 12

28

10K

14

r---

I
I
I
I

VOUT = 2Vpp
510A
154
VEE
VLED
1.2K

LED

IN 2>---t---{ 7Jf-+-It---t~~~----...:.---....
11

IN 3>---_-<

LED

1.2K

LED

1.2K

LED

1.2K

10

IN4>---~~r-~~~~~~~~~----__t
LCC

ENABLE
AND
CHAN 1-4
SELECT

IN

2

5>---~~' ~+===~-I--4-1:EJ:J~---.J

6 ENABLE

4
-=-GND

• Adjust offset larVOC at pin 9 equa/to zero volls with no AC signal and one channel "ON"·. Oymanic
clamping may be accomplished by error current feedback to pin 8.

FIGURE 2(c). TYPICAL APPLICATION BIAS CIRCUIT DC-COUPLED INPUT AND OUTPUT.
THE Vp-p OUTPUT CAPABILITY IS FIXED BY THE VCC AND VEE RANGE AND
IS APPROXIMATELY +3.6V, -2.SV (CLIPPED) FOR VCC
+SV, VEE
SV.
THE LOW P.S. FUNCTIONAL RANGE FOR 2Vp-p OUTPUT IS VCC = +4V,
VEE -4V; BW", 10MHz.

=

=

=

"'Cr~~":T ~~ :"~
.

._ + ••..L.c.+. _.,

-

+1

o

-1
10

o

1 palDIVISION
PHOTO 1. WAVEFORM DISPLAY (FIGURE 2c) GATED OUTPUT FOR VCC = +12V
ENABLE = HIGH, CONTROL B = C = LOW, CONTROL A = 10V PULSE.
THE BURST OUTPUT IS DELAYED - 400n5 at tON, tOFF'

8-56

CA3256

z

z

o

o

iii

iii

:;:
C

:;:
C

>
II!

>
II!

o

o

10/lo/DIVISION

10/lo/DIVISION

PHOTO 2. STANDARD NTS COLOR BAR

PHOTO 3. UNIFORM STEP SIGNAL WITH 3.5BMHz
MODULATION. CIRCUIT CONDITIONS,
VCC = +5V, VEE = -5V, ICC'" 25mA.

PHOTOS 2 & 3. WAVEFORM DISPLAY (FIGURE 2c) OF DC COUPLED PERFORMANCE CHARACTERISTIC.

Test Circuit
FEEDBACK
SWITCH

CONTROL INPUTS (CHANNEL SELECT)

FIGURE 3. CA3256 TEST CIRCUIT

8-57

CA3256
Test Circuits

(Continued)

~I~B-:~~. ~~\\'Kt ~;3L~~~~EQUENCY
AMBIENT TEMPERATURE (TA)

~

25°C

7 pF

0

....,

"

-2

~ -4

;;

" -6
-8
-10
4682468

0.01

0.1

2468

1

2468

10

100

FREQUENCY (t) • MHz

FIGURE 4(a). GAIN-BANDWIDTH CHARACTERISTICS OF
FIGURE 2b WITH COMPENSATION
CAPACITOR, CCOMP, AND Rf, SEE FIGURE
4b AND FIGURE 6(1).

31

t-29

\

FIGURE 4(b). TEST CIRCUIT.

VOUT - 200 mV(pp), AT LOW
FREQUENCY 0 dB REF.
GAIN WITHOUT FEEDBACK ~30 dB
AMBIENT TEMPERATURE (TAl ~ 25°C

NO FEEDBACK

27

!g

z
;;

"

25

23

21

19
4 • B

4682468

0.01

0.1

1

10

2

4 B B

100

FREQUENCY (t) • MHz

FIGURE 5(a). OPEN LOOP GAIN-BANDWIDTH
CHARACTERISTIC OF FIGURE 2b WITH
NO FEEDBACK, SEE FIGURE 5b AND
FIGURE 6(5).

8-58

FIGURE 5(b). TEST CIRCUIT.

CA3256

Test Circuits

(Conllnued)
A = 1.1X
BW= 18MHz
VOUT= 1 Vpp

7pF

AOL= 30X

T f---0-

BW = 250kHz

~::;;:o~o~

200m

75,n.
9l)---"""'IIr-~--O VOUT '

V

pp

f50,n.

75,n.

(5)

(1)

2pF

A= 2X
BW= 15MHz
VOUT= 2Vpp

1}-__1--II---.1I----o VOUT
75,n.

7pF

A= 3.6X
BW= 6MHz
VOUT= 200mVpp

I J=: eg

11-0 VOUT

(NOTE: 470,n.ADDED TO INCREASE SOURCE
DRIVE CURRENT)
(2)

(6)

6pF

2pF

1 t:

cg

11---0 VOUT

9

280,n.

A = 1.1X
BW = 4OMHz(1.2 X GAIN PEAK AT 25 MHz)
VOUT= 200m Vpp
(3)

I

:~VOUT2
~

•_ _ _ _

75,n.

V0UT1

75,n.

I 6

(7)

~

OFFSET ADJ.
(SETS DC OUT LEVEL)

+

200K

....._ . . :

RS
VOUT1

~

~

-=-

2X

A= 1.1X
BW= 15MHz
VOUT = 200mVpp

A= 1.1X
BW= 28MHz
VOUT= 2Vpp

26 MHz(UNITY GAIN)
400mVpp

10<

/

ADJ.
VDC = 5V

I

F

A = 1.1X
BW= 2BMHz

VOUT
= 2Vpp

1oo,n.

NOTE: ADD RS TO REDUCE HIGH· FREQUENCY SlEWING

(4)

(S)

FIGURE 6. OTHER TABULATED RESULTS FOR VARIATIONS OF LOAD AND FEEDBACK FOR CIRCUIT, FIGURE 2b;
VCC +12V.

=

8-59

CA3256
Application of High Speed CMOS
Analog Switches
CMOS analog switches are available in a wide variety of
forms, and have been known and used for some time. There
are a number of advantages to using the CMOS transmission gate as a switch:
• Ideal suitability to series cascade arrangements.
• Simple muitiple parallel input switching arrangements.
• No bipolar junctions and, hence, no offset.
• Very low power consumption.
• Wide signal-swing capability.
• Fast multiplexing and video switching in high-speed
CMOS.
• Wide bandwidth in high-speed CMOS.
• Low RON channel resistance in high-speed CMOS.
• Bidirectional signal handling.

An Integrated Video-Switch Amplifier
Commonly, integrated video-switch amplifiers have been
fabricated in the bipolar technology using differential
amplifiers in a current-switching mode. In this form, two
differential pairs are needed for-two input-signal sources.
The handling of multiple sources is very much more
complex. The advantages of the CMOS video-switch
amplifier have already been noted. While the bipolar video
switch has high output drive and switching speed as
advantages, the price is high in voltage offset and current
drain. The integrated device solution that is offered here is in
the use of the BiMOS technology, where both the CMOS
and bipolar processes complement each other to provide
CMOS -switching with bipolar amplifiers. The BiMOS
process allows several CMOS switches to be coupled to a
bipolar drive-amplifier in the same process to exploit the
best of two technologies.
Other advantages are gained when the BiMOS process is
used for an IC video-switch amplifier design. The BiMOS
process calls for a p-substrate and, therefore, isolated
n-epitaxial boats can be built for both nand p channel
parts. The boats provide for better Isolation of the nand p
channels. The nand p wells in a transmission-gate cell can
be switched between source and rail; therefore, they have a
smaller body effect on both nand p devices, which results
In better gain linearity. Where desired, oxide capacitors are
available for bipolar amplifier compensation.

CA3256 Video-Switch Amplifier
The block diagram of Figure 1 shows the functional
diagram of the CA3256, which consists of five MOS
channels, each comprising a three-element T-switch. The
output of the five switches is made common and fed into the
input of a bipolar buffer amplifier. The T-switch, together
with the input impedance of the buffer, is typically 10kO,
and has an insertion loss of approximately O.8dB. The
T-switch was designed to handle up to 3Vpp input
signal with low distortion. The T-switches of the CA3256
conform to a break-before-make format; hence, shorting to
ground is eliminated.
The amplifier is programmable for gain and, typically, can
provide a gain of 1 times into a 750 load or a gain of 5 times
into a lkO load. The maximum output signal swing with
linearity is greater than 5Vpp for (VCC - VEE) greater than
or equal to 12 volts, while the maximum output current is
approximately 20mA. The amplifier has base-current
compensation to reduce offset and a temperature
compensated 5-volt zener referenced bias. Other features
Include LED-selector indicators for channels 1 through 4.
The fifth channel is independently selectable for use as a
separate input or output in parallel with any on channel, and
may be used as a monitor, or for pass-through, signal
summing, or parallel distribution.
In the application, the user has the option to specify -5 volts
VEE for the switch and a ground reference for the amplifier
input and output. Alternatively, the CA3256 may be used
with a single + 12 volt supply. The logic select for channels
1 through 4 is controlled by the A, B and Inhibit lines with
-ground to VCC logic switching. The logic threshold is
approximately VCC/2 independent of the -VEE voltage
level. DC coupling may also be used at the output (when
VEE is returned to a -5 volt supply). For the circuit of Figure
2(b). AC coupling is used at the output and input. The
switching bias arrangement shown provides for stable bias
across each switch when in the off position to minimize
transients when the input is switched.
Any combination of switch input circuits can be configured
with mUltiple, parallel, line-drive outputs. The video-switch
amplifier circuit of Figure 7 illustrates how the CA3256 may
be configured in pairs to provide an 8-to-l video-switch
amplifier using a 3-bit address to select the input. It is also
possible to use the fifth channel input to tie signals to a
common bus line for distribution from the selected amplifier;
however, distributed capacitance loading will result In
reduced bandwidth. The 4 plus 1 combination of inputsignal switching provides for a wide assortment of videoswitch circuit configurations.

8-60

CA3256
While the SiMOS process does provide some compromises
for both the switch and the amplifier, the combined system
is capable of the performance needed in most high-quality,
switching applications. As an integrated system, many of
the problems in pc-board layout are simplified, and there is
is a reduction in component count. In its simplest form, with
+12 and -5 volt supplies, the CA3256 may be DC connected at the input and output; the LED indicators need not
be connected. A DC level translator resolves the channel
switch control at the -VEE voltage level. Under these conditions, the circuit may be as simple as the one in Figure 7.

Summary
While each video-switch amplifier is designed for a speCific
application and, to that end, Is tailored as far as .performance to a given set of specifications, the circuit-designer's
goal is generally the same in every case: to make the best
possible switch for the lowest cost. In this respect, the
CA3256 IC switch and amplifier discussed provide an
excellent choice for a cost-effective high-performance
video-switch amplifier, by taking advantage of the
complementary features of both high-speed CMOS and
bipolar integrated circuits.

A>----.---------fAAi1------~N~01i1
B >--9>-+---------1 B1
C1
C1

CH
1 -4

r::

V
INa
V IN4

CH5

INH1
1

TRUTH TABLE

2
Vour
a

VCC

4

GND

5

VEE

- -

-5V

CA3256

No2

A2
B2
C2

-

+12V

CH

Cl

A

B

1

0

0

0

2

0

0

1

3

0

1

0

4

0

1

1

5

1

0

0

6

1

0

1

7

1

1

0

8

1

1

1

INH2

~{
5-8

NC

V IN5

1

V IN6 2
V IN7

~

=>

a

-,0

-~----,,..-:j~-~

SYNC

U

NOTES
*PIN 21 HIGH WHEN PIN 20
**15 HIGH lOR OPEN}
PIN! HIGH INHIBITS CLOCK

CRYSTAL .-.-~---'
3Z TIMES
HORIZ
503,496 t----1---+--+-~~~~~

I
I

I

I

1.36

..I

m.

____~~~~~~ __ ruI
I

1--0.,94... ---l

I

~~~~~~il ______r-~~_;_:-

CATHODE BLANKING
PIN 7
FRAME S'tNC

ION

r-

II

At~~R~5ATE FIELDS)

~

I

I

I

:

I

I I I
I
-L..Jl.JL.I"-- U-

u

~ ~ 2,.,5

i

___,__

92CM-38697

(NOT TO SCALE)

Fig. 3 - Sync generator timing - 625/50 Hz.

8-66

CD22402
STATIC ELECTRICAL CHARACTERISTICS

CHARACTERISTIC

Quiescent Device
Current

100

Output Voltage
Low-Level

VOL

High-Level

VOH

Threshold Voltage
(N-Channel)
(P-Channel)
Noise Immunity
(Any Input)

VTHN
VTHP
VNL
VNH

TEST
CONOITIONS
Vo
VOO
(VI
(VI
5
10
15
5
10
5
10

10 = 10JlA
lo=-10JlA
5
10
5
10
0.5
5

Output SINK Current
(N-Channel)

IoN

r---s0.5
r--w-

Output SOURCE Current
(P-Channel)

loP

4.5

Input Current
(Each Input)

10

ro-

5

~
0

10

I,

-

LIMITS
+25°C

-55°C

UNITS

+125°C

Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.

-

-

4.99
9.99

-

-

-

-

4.99
9.99

-

1.7
-1.7

-

1
-1
1.5
3
1.5
3
80
960
200
2400
80
960
200
2400

-

1.5
3
1.4
2.9
100
1200
248
3000
200
1200
248
3000

-

-

-

-

-

0.5
1.5
3

0.75
2
4

0.01
0.01

-

-

-

-

-

-

-

1
2.5
5
0.01
0.01

-

-

4.95
9.95

-

-

...,.

-

1.5 2.6
1.3
-1.5 -2.6 -1.3
1.4
2.25 4.5
2.9
2.25 1.5
3
4.5
160
56
1920 672 140
400
4800 1680 56
160
1920
672
400
140 1680
4800

-

10

-

-

-

-

-

mA

0.05
0.05

-

-

V

pA

-

pA

DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25° C and CL = 15 pF
Typical Temperature Coefficient lor All Values 01 VOO = O.3%I"C
TEST
CONOITIONS
VOO (VI

MIN.

TYP.

MAX.

tPLH
tPHL

5
10

-

40
20

80
40

hLH
hHL
C,

5
10

-

-

45
30
5

90
60

CHARACTERISTIC
Output State
Propagation Delay Time
(50% to 50%)
Low-ta-High Level
High-ta-Low Level
Transition Time
(10% to 90%)
Low-to-High
High-to-Low
Input Capacity (Per Input)

8-67

LIMITS

-

UNITS

-

ns

pF

CD22402

MIXED SYNC.

COM ~~S ITE >-------1
VIDEO
'-_-.-_...J
INPUT
VERTICAL S.:.YN:,:C~_ _ _ _+-_____lf-_____---1
(OPTIONAL)
)

RCA
CD22402 4

HORIZONTAL DRIVE

II

HORIZONTAL CLAMP

13

MIXED PROCESSING BLANKING

14

HORIZONTAL PROCESSING BLANKING

10

6
0

u
'"g~

2

MIXED BEAM (CATHODE) BLANKING

22

zO

VERTICAL DRIVE

OJ
C>

24
16

FROM POWER
LINE FOR
LI NE-LOCK
OPERATION

SHORT VERTICAL DRIVE

MIXED SYNC

15

FRAME

17

VERTICAL PROCESSING BLANKING OUTPUT

18

OPERATION SWITCH FOR 525-lINE OR
62S-L1NE RASTER

3,12

SYNC OUTPUT (ODD FIELD)

92CL-3B693

Fig. 4 -. Typical application in a TV camera.

8-68

HA-2546

mHARRIS

Wide band Two Quadrant
Analog Multiplier

August 1991

Features

Description

o High Speed Voltage Output •••••••••.•.•••• 300V/IIS

The HA-2546 is a monolithic, high speed, two quadrant,
analog multiplier constructed in the Harris Dielectrically
Isolated High Frequency Process. The high frequency per·
formance of the HA-2546 rivals the best analog multipliers
currently available including hybrids.

o Low Multiplication Error ••••••••••.••••••••••• 1.6%

• Input Bias Currents ••••••••••••••••••••.•••••• 1.211A
• Signal Input Feedthrough .••••••••••••••••••• -52dB
• Wide Signal Bandwidth ••.•••••••••••••••••• 30MHz
• Wide Control Bandwidth •••••••••••••••••••• 17MHz
• Gain Flatness to 5 MHz ••••••••••••.•.•••••• O.10dB

Applications
o Military Avionics
o Missile Guidance Systems
o

Medical Imaging Displays

o

Video Mixers

o

Sonar AGC Processors

• Radar Signal Conditioning
• Voltage Controlled Amplifier
o Vector Generator

Pinout

The HA-2546 has a voltage output with a 30MHz signal
bandwidth, 300V/lls slew rate and a 17MHz control input
bandwidth. High bandwidth and slew rate make this part an
ideal component for use in video systems. The suitability for
precision video applications is demonstrated further by the
0.1dB gain flatness to 5MHz, 1.6% multiplication error,
-52dB feedthrough and differential inputs with 1.211A bias
currents. The HA-2546 also has low differential gain (0.1 %)
and phase (0.1 0 ) errors.
The HA-2546 is well suited for AGC circuits as well as
mixer applications for sonar, radar, and medical imaging
equipment. The voltage output of the HA-2546 Simplifies
many designs by eliminating the current-to-voltage conversion stage required for current output multipliers.
The HA-2546-9 has guaranteed operatIon from -40 0 C
to +850 C. The HA-2546-5 has guaranteed operation
from OOC to +75 0 C. The HA-2546 Is available In a 16 pin
Ceramic DIP. For MIL-STD-883 compliant product and
LCC packages consult the HA-2546/883 datasheet.

Simplified Schematic

~

HA1-2546 (CERAMIC DIP)
TOP VIEW

+v

:5

-,0

; a

13

....-r:
~-

-3
-6

..A
OpF

~=ot
N'ooJ
CL=
10K

lOOK

1M

5Op~~

10M

OJ
:!!.

10
5

e.

<
C!l

;>;

0

ff!

1 1

a

5

~
c:

~
w

-

-5
-10

Ii:

45 ~
90 w
135~
1
100M

aail:

lOOK

10K

FREQUENCY (Hz)

1M

c:

"-

ff!

e-

o Ii:

"

10M

~
w
135~

45
90

1805:
100M

FREQUENCY (Hz)

Vy FEEDTHROUGH vs FREQUENCY
Vx = OV RL = 1 K, Vy 200mVrms

Vx FEEDTHROUGH vs FREQUENCY
RL = 1 K, Vx+ = 200mVrms, Vy = OV,

=

-10
-20

-30

iii' -40

:!!.

z

;;:
C!l

-

-50

-60
-70

....

-80
-90

10K

lOOK

1M

~

'"

iii'

0
-10
-20

v~ =1 _I J.ovJc

-

:!!. -30
-40

-50

10M

1"---

-

v, =1-1~·SVdi'

10K

100M

lOOK

VARIOUS Vy FREQUENCY RESPONSES
RL = lK, CL = 50pF, Vy = 200mVrms

iii'
:!!.

z

;;:
C!l

VXI=

12-~~dC

Vx= 1.0Vdc
vx'=

~.\;\,dC

-12
-15

10K

1M

10M

100M

L"..oo'
I.,,;"

VARIOUS Vx FREQUENCY RESPONSES
Vx+ = 200mVrms, RL = 1K. Vx- = -lVdc

-

15

-

iii'

:!!.
Z

;;:

1/
./

10M

10 f-- _vy5
-VY0
-5

r-

C!l -10
-15 f-20

LI II
lOOK

1M

I

FREQUENCY (Hz)

FREQUENCY (Hz)

9
6
3
0
-3
-6
-9

-

rx I -lt~c

100M

10K

SVdc
2Vdc

-Vy- O.SVdc

lOOK

~Y,i 1V~C
1M
FREQUENCY (Hz)

FREQUENCY (Hz)

8-73

10M

100M

HA-2546
Typical Performance Curves (Continued) Vs = ±15V, TA = +25 0 C, See test circuit for multiplier configuration
NOISE CHARACTERISTICS
Vx=OV,Vy=OV

Vy OFFSET AND BIAS CURRENT vs TEMPERATURE
14

3OCO~rTnmm-~~mr-rTnnm~~nmr-rTnwm

20c01--1-+~m-~~Hm~-H+mi-~~~-+++H*H
20c0~+++H~~+H~~rHH#m-~Htffi*-t~~

12
10

_ 2400 I\-l-+ttHlIIf-+tttfffft-l-tltlfl~-HH-HItfIt-+++!ffHt
~ 2200 1-\\+++HIIIH-++I-IIIH--+-Jl+HIlII-+-H~'-++HiitH
~ 2000 l-\H-ttHlIIf-+ttt

<"

8

I-

6

~

ffi 4
a:

;;

.s lOCO HH-ttHm-~~
lOCO i-J~+-HlIIII--I-+++

~

1-1-:~~~~:tjtttl-l!!!l~-H+mIH--HI-I+IIIIII---+-++HIIII

:;

OCO 1-+4-H11ffil--+-+++ilirll-+lH+HfH-lH-HflIlll--+-+rHIIH

- t--.

~

a:

a II

1400
w 1200
~ locol--++\H~-+;;+mIH-~HtHm-lrtHflIllf--r+hmm

o

~FFSET ClURRENl

-2

~ OCO 1--+++HIII--+;;+mIH-~HtHm-lrtHflIllf--rttmm

-4

4OO1--1-+~~~+H~~tttlli*-t-++Hffir-rHHHm

-55

-25

o

10

50

75

100

125

lOOK

10K

100
lK
FREQUENCY (Hz)

25

TEMPERATURE (DC)

~tttlOOtfnm~~~~~~1
1

BIAS CURRENT

OFFSET VOLTAGE vs TEMPERATURE

Vx OFFSET AND BIAS CURRENTvs TEMPERATURE
3

10

8
6

lw

- --

-

4 I-Vy
2

~

:;

0

~

-2

tu

~

Vx

'-

~ ·4 f--VZ
u.

0

........ ,......,..,
-

-6

-8

2

r----. r--,"",
o

OFFSICURRr

-1

-55
-10

-55

-25

o

25
50
TEMPERATURE (OC)

75

100

BIAS CURRENT

-25

o

25

50

75

8'---~----r---r---~--~---r----'

120

J I Jv-

100

±l

125

Vy CMRR vs FREQUENCY
VYcm = 200mVrms

OUTPUT VOLTAGE SWING vs TEMPERATURE

>6~~~--~-+--~--+-~

100

TEMPERATURE (DC)

125

.,80

__~

IX

:2.60
~ 40

~

.... (!l

~~

VX= 2V

20

~

i'"

o

~;;:: 4-t---+--It---t---+--It---t----I

-10

OC/l

~~
D.:;

~ 2-t---t--+--t--t--+--t-~

100

~~55~----~25~--~O----2~5--~50~--~7~5~~1~OO~--J125
TEMPERATURE (DC)

8-74

lK

10K

lOOK
1M
FREQUENCY (Hz)

10M

100M

HA-2546
Typical Performance Curves (Continued) Vs = ±15V, TA = +250 C, See test circuit for multiplier configuration
Vx COMMON MODE REJECTION RATIO vs FREQUENCY
Vx = 200mVrms
120
100
1ij'

:!!.

a:
a:

::;
U

VY

80
80
40

PSRR vs FREQUENCY

Vy=Vx=ov

OV

100 c -

........

Vy - 2V -"""

-

+PSSR

-

1ij'80

:!!.60
~ 40
~ 20

r-

20
0

PSSR

o

100

lK

10K

lOOK
1M
FREQUENCY (Hz)

10M

100M

100

SUPPLY CURRENT vs TEMPERATURE

lK

10K

lOOK
1M
FREQUENCY (Hz)

10M

100M

SIGNAL/CONTROL CMRR vs TEMPERATURE

25

100
• ICC
90

CtNTROL
+ ICC
llGNAL

60

15
·55

·25

0255075

100

50

125

·55

·25

TEMPERATURE (DC)

PSRR

va TEMPERATURE

0

25
50
TEMPERATURE (DC)

75

100

125

MULTIPLICATION ERROR vs Vx

100

4
+PSRR

I
80

.lpSRR
1ij'

80

:!!.

a:
a:

en
/l.

40

I'"

20

0

o
·55

·25

0

25
50
TEMPERATURE (DC)

75

100

125

8-75

I

0.0

.... ~

~

~ .....

I
0.2

--

0.4

0.6 0.8 1.0
1.2 1.4
VOLTAGE APPLIED TO Vx

~ ....
1.6

i"oo~'"
1.8

2.0

HA-2546
Typical Performance Curves (Continued) Vs = ±15V, TA = +250 C, See test circuit for multiplier configuration
MULTIPLICATION ERROR vs TEMPERATURE
Vy=5V,VX=2V

WORST CASE MULTIPLICATION ERROR vs TEMPERATURE
2.0
1.9
1.8
1.7
1.6
i 1.5
~1A

0.5

t

0.4

I!:

0

~UJ ~:~
1.1

I!:

~ 1.0

9

ffi

0.3

Z

~ ~::

!;;c
tl

~ 0.7

./

0.2

:J

e.

~ ~:~

./

::;

:> 0.1

:E 0.4
0.3
0.2
0.1
0.0

/

::;;

·55

·25

0

25

50

75

100

0.0
-55

125

-25

25

0

TEMPERATURE (DC)

50

75

100

125

TEMPERATURE (DC)

GAIN VARIATION vs FREQUENCY
RL = 1 K, Vx = 2Vdc, Vy = 200mVrms

SCALE FACTOR vs TEMPERATURE
2.010

,

0.6
0.4
ICL= 50pF

,

iii" 0.2
~

z

:;;:

0

2.008
2.006

I
I

I!:

§

CL= OpF

I

C!I

tI:

I I

lOOK

10K

1M
FREQUENCY (Hz)

10M

1.998

13en

100M

2.002
2.000

~

-0.2

---

2.004

1.996

--

~

1.994
1.992
1.990
·55

OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
fo = 10kHz, Vx = 2Vdc, THO < 0.1%
7.0

I-V~-W5

::;
0

>

4.0

1/

....

:>

...."-

:>
0

~

"-

,

3.0

I,;
2.0
1.0
0.0
10

V"

Vs=t B

100

125

SLEW RATE vs TEMPERATURE

~Y CHANNEL

400

IF-

w 5.0

~

25
50
75
0
TEMPERATURE (DC)

500

Js'2 ~I~~

I

6.0

-25

-;;~

:::'300
w

Vs=t 10

-

!;;:
I!:

~

200

en

Vx CHANNEL
100

II

II

0

,

- 60

100

lK
10K
LOAD RESISTANCE (.n.)

lOOK

8-76

·40

- 20

0
20
40
60
TEMPERATURE (DC)

80

100

120

HA-2546
Typical Performance Curves (ContinuedlVs = ±

15V, TA = 25 0 C, See test circuit for multiplier configuration

RISE TIME vs TEMPERATURE
24

SUPPLY CURRENT vs SUPPLY VOLTAGE
28

I I I

22

26

:<:

Vx CHANNEL

18

22

c
;;;14

!zw 18

~

a 14

+Icc

I
II

520

'iiJ 16

~ 16

12

~ 10

~ 12

Vy CHANNEL

8

8:

10

6

1il

8
6

4

2

4

o

20

-60

~

24

20

c:

I I
-ICC

-40

-20

02040

60

80

100

2

120

4

6
8
10
12
14
SUPPLY VOLTAGE (-I: V)

TEMPERATURE (DC)

16

18

20

Applications Information
Theory of Operation
The HA-2546 is a two quadrant multiplier with one differential signal channel, Vy+ and Vy_, one differential control
channel, VX+ and VX-, and one differential input, Vz+
and VZ-, to complete the feedback of the output amplifier.
Figure 1 shows a detailed functional block diagram of the
HA-2546. The differential voltages of channels Vx and Vy
are converted to differential currents. These currents are
then multiplied in a circuit similar to a Gilbert Cell multiplier,
producing a differential current product. The differential
voltage of Vz is converted to a differential current which
sums with the product currents. The differential "product!
sum" currents are converted to a Single-ended current then
converted to a voltage output by a transimpedance amplifier.

The open loop transfer equation for the HA-2546 is:
VOUT=Af(vxvVX-)(VY+-VY-J SF

L

(VZ+-VZ-~,where

J

A = Output Amplifier Open loop Gain
SF = Scale Factor
VX, Vy, Vz = Differential Inputs
The scale factor Is used to maintain the output of the multiplier within the normal operating range of ±5V. The scale factor
can be defined by the user by way of an optional
external resistor, REXT, and the Gain Adjust pins, Gain
Adjust A (GA AI, Gain Adjust a (GA aI, and Gain Adjust C
(GA CJ. The scale factor Is determined as follows:
SF = 2, when GA a is shorted to GA C

+V 0-----1
- V

SF,., 1.2* REXT, when REXT is connected
between GA A and GA C (REXT is in kOI

0-----1

VYIOA
VYIOB

SF,., 1.2* (REXT + 1.667kOJ, when REXT
is connected to GA a and GA C (REXT Is in knl

Vy
VOUT

Vz

GAA

GAB
GAC

The scale factor can be adjusted from 2 to 5. It should be
noted that any adjustments to the scale factor will affect the.
AC performance of the control channel, VX. The normal
Input operating range of Vx is equal to the scale factor
voltage.
The typical multiplier configuration is shown in Figure 2. The
ideal transfer function for this configuration is:
VOUT= {

FIGURE 1.

(VX+-VX-J(VY+-VY-J +VZ2
,when(Vx+-Vx_J~O
o

8-77

,when (Vx+-Vx-J <0

HA-2546
Applications Information

(Continued)

The Vx- pin is usually connected to ground so that when
Vx+ Is negative there is no signal at the output, I.e. two
quadrant operation. If the Vx input Is a negative going signal
the Vx+ pin maybe grounded and the Vx- pin used as the
input.
The Vy_ terminal is usually grounded allowing Vy+
to swing :1:5 volts. The Vz+ terminal is usually connected
directly to VOUT to complete the feedback loop of the
output amplifier while VZ- Is grounded. The scale factor is
normally set to 2 by connecting GA B to GA C. Therefore
the transfer function becomes:
Vour=

(Vx+)(Vy-)
2

The multiplication error Is trimmed to be minimum at full
scale, Vx '" 2V and Vy '" 5V. When Vy '" 5V, the worst case
multiplication error occurs when Vx "" 0.65V. See Typical
Performance Curves.

Operation At Reduced Supply Voltages
The HA-2546 will operate over a range of supply voltages,
:1:8 to :1:15 volts. Use of supply voltages below :1:12 volts will
cause degradation of electrical parameters.
Offset Adjustment
The signal channel offset voltage may be nulled by using a
20K potentiometer between VYIO Adjust pins A and Band
connecting the wiper to -VS. Reducing the signal channel
offset voltage will reduce Vx AC feedthrough and improve
the multiplication error. Output offset voltage can also be
nulled by connecting VZ- to the wiper of a potentiometer
which Is tied between +V and -V.
Capacitive Drive Capability
When driving capacitive loads >20pF a 50n resistor should
be connected between VOUT and VZ-, using VZ- as the
output (see Figure 2). This will prevent the multiplier from
going unstable due to the pole created by the load capacitor
and reduce gain peaking at higher frequencies.

Die Characteristics
Transistor Count ..•...........•.......•..•..•.•.... 87
Die Dimensions •.......••........ 79.9x119.7x19mils
(2030 x 3040 x 480J.lm)
Substrate Potentlal* ....•.....•..••...........•..•.• VProcess ....•..•.......•.••.• High Frequency, Bipolar, 01
Passivation. . . • • . . • . • . • • . • . . • • • • • • • . • . • . . • . . . .• Nitride
Thermal Constants (OC/W)
HA1-2546...........................

aja

ajc

76

17

• The substl'ate maybe left floating (Insulating Die Mount) or it may be on a
conductor al V- potential.

FIGURE 2.

8-78

mt HARRIS

HA-2547
Wide band Two Quadrant
Analog Multiplier

August 1991

Features

Description

• Low Multiplication Error •.•••••.•••••••••••••• 1.6%

The HA-2547 is a monolithic, high speed, two quadrant,
analog multiplier constructed in Harris' Dielectrically
Isolated High Frequency Process. The high frequency
performance of the HA-2547 rivals the best analog multipli'
ers currently available including hybrids.

• Input Bias Currents ••.••••.••••••••••.•••••••• 1.2(JA
• Signal Input Feedthrough @ SMHz ••••••••••• -SOdB
• Wide Signal Bandwidth ••••.•••••.•••.•••.• 100MHz
• Wide Control Bandwidth •••••••••.•••••••••• 22M Hz

Applications
• Military Avionics
• Missile Guidance Systems

The single-ended current output of the HA-2547 has a
100MHz signal bandwidth (RL = 500) and a 22MHz
control input bandwidth. High bandwidth and low distortion
make this part an ideal component in video systems. The
suitability for precision video applications is demonstrated
further by low multiplication error (1.6%), low feedthrough
(-50dB), and differential inputs with low bias currents
(1.2(JA). The HA-2547 is also well suited for mixer circuits
as well as AGC applications for sonar, radar, and medical
imaging equipment
The current output of the HA-2547 allows it to achieve
higher bandwidths than voltage output multipliers. An
internal feedback resistor is provided to give an accurate
current-to-voltage conversion and is trimmed to give a full
scale output voltage of ±5 volts. The HA-2547 is not limited
to multiplication applications only; frequency doubling and
power detection are also possible.

• Medical Imaging Displays
• Video Mixers
• Sonar AGC Processors
• Radar Signal Conditioning

The HA-2547-9 has guaranteed operation from -400 C to
+85 0 C, while the HA-2547-5 has guaranteed operation
from OOC to +750C. The HA-2547 is available in a 16 pin
Ceramic DIP. For MIL-STD-883 compliant product and
LCC packages consult the HA-2547/883 datasheet.

• Voltage Controlled Amplifier
• Vector Generator

Pinout

Schematic

HAl-2547 (CERAMIC DIP)
TOP VIEW
GAA
GAC
GAB

vy+

vx+
vx -

vy-

+v

-v
lOUT

RZ
NC

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed,
Copyright @ Harris Corporation 1991

8-79

File Number

2862

Specifications HA-2547
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- Terminals ..................... 35V
Differential Input Voltage ••••.••••••••••••••.••••••••••••••• SV
Output Current •••••••••.••.••..•.•••••••••.•..••.•••••• 3mA
Maximum Junction Temperature ••••••••••••••••••••••• +1750C

HA-2547-9 .•••••••••••••.•••••••••••.•• -400C ~TA~ +850C
HA-2547-5 •••••••••••••••••••••••••••••.• OOC~TA~+750C
Stomge Temperature Range ••••.•••••••• -85°C S TA :S +150o C

Electrical Specifications +V = +15V, -V = -15V, RZ (Pin 10) Grounded, Unless Otherwise Specified
HA-2547-5

HA-2547-9
PARAMETER

TEMP

MIN

I

TYP

MAX

1.S
3.0
0.003
0.7
0.03
6
14

3
7

I

MIN

TYP

MAX

UNITS

-

1.6
3.0
0.003
0.7
0.03
6
14

3
7

%FS
%FS
%JOC
%
%
mV
mV
JlVJOC

MULTIPLIER PERFORMANCE
Multiplication Error (Note 2)
Multiplication Error Drift
Scale Factor Error
THD+N (Note 3)
Output Offset Voltage (Note 4)
Average Offset Voltage Drift

+250 C
Full
Full
Full
+250 C
+25 0 C
Full
Full

-

-

5

-

15
20

-

-

-

5
-

15
20

-

SIGNAL INPUT, Vy
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Differential Resistance
Small Signal Bandwidth (-ad B) (Notes 5, 10)
Feedthrough (Note 13)
Differential Input Range
Common Mode Range
CMRR (Note 6)

+250 C
Full
Full
+250 C
Full
+250 C
Full
+250C
+250 C
+250 C
+250 C
+250 C
Full

-

-

4
8
35
7
10
0.7
1.0
720
100
-50

10
20

15
15
2
3

±5

-

60

±g
78

-

-

5
3

-

-

-

±5
-

4
8
35
7
10
0.7
1.0
720
100
-50

-

60

±9
78

-

5
3

10
20

mV
mV
JlVJOC

15
15
2
3

)IA
)IA
)IA
)IA

-

kO
MHz
dB
Volts
Volis
dB

-

-

Vy TRANSIENT RESPONSE
Rise Time (Note 15)
Propagation Delay

+250 C
+250C

-

ns
ns

CONTROL INPUT, Vx
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Differential Resistance
Small Signal Bandwidth (-3dB) (Notes 5, 10)
Feedthrough (Note 14)
Input Range (Note 1 2)
Common Mode Range
CMMR (Note 7)

+250 C
Full
Full
+250 C
Full
+250 C
Full
+250C
+250 C
+250 C
"Full
+250 C
+250 C

-

+2
-

-

+2
-

1
2
12
1.2
1.8
0.3
0.4
360
22
-40

2
20

-

-

±g
75

-

2
5
2
3

-

1
2
12
1.2
1.8
0.3
0.4
360
22
-40

2
20

mV
mV
JlVJOC

2
5
2
3

)IA
)IA
)IA
)IA

-

-

±9
75

-

kO
MHz
dB
Volts
Volis
dB

15
25

-

ns
ns

±6.25
2
4

-

Volls
mA
MO

-

dB
mA

-

-

Vx TRANSIENT RESPONSE
Rise Time (Note 16)
Propagation Delay

-

15
25

-

-

Full
+250C
+25 0 C

-

±6.25
2
4

-

-

Full
Full

58

63
20

-

58

29

+250 C
+250 C

-

OUTPUT CHARACTERISTICS
Full Scale Output Voltage (Note 8)
Full Scale Output Current (Note 11)
Output Resistance

-

-

POWER SUPPLY
PSRR (Note 9)
ICC

-

8-80

-

63
20

29

HA-2547
NOTES:
1. Absolute maximum ratings are limiting values. applied individually.

beyond which the servicabilily of the circuit may be impaired. Functional
operation under any of these conditions is not necessarily implied

9. Vs = ±12V to ±lSV. Vy = SV. Vx = 2V.
10. Guaranteed by sample test and not 100% tested.
11. Output current tolerance is ±20%.

2. Error is percent of full scale, 1% = 50mV.
3. 10 = 10kHz. Vy = Wrms. Vx = 2V.

12. Scale Faclor = 2. See Applications Information.

4. Vx = OV. Vy = OV.

13. fa

5. RL = son.

14. 10 = SMHz. Vy = O. Vx+ = 200mVrms. Vx- = -O.SV. Relative to lull

6. Vy

= 0 to ±5V. Vx = 2V.

= 5MHz, Vx = 0, Vy = 200mVrms. Relative to full scale output.

scale output

= ±SV. Vx = 2V. RL = son.

7. Vx = 0 to 2V. Vy = 5V.

15. Vy

e. Vy = ±5. Vx = 2.5V.

16. Vx = 0 to 2V. Vy = 5V. RL = son.

Test Circuits
AC AND TRANSIENT RESPONSE TEST CIRCUIT

(J)
l-

S

Vx TRANSIENT RESPONSE
Vertical Scale: Top: lV/Div Bottom: SOmV/Div
Horizontal Scale: SOns/Div

Vy TRANSIENT RESPONSE
Vertical Scale: Top: SV/Div Bottom: 100mV/Div
Horizontal Scale: 20ns/Div

-,0

<1:0:

00
W(!J

D..O

(J)-,

" B
±!
(!l
z

~

VOUT

~ 6
w
~

S
~

...
~:::>

o

~0.

6

~
S

r----Vx

2

~

4

-

!---

I
1ii-2
~
~
r---II.

o

2

-6

o

-55

-25

o

25
50
75
TEMPERATURE (DC)

100

-10

125

-55

Vy OFFSET/BIAS CURRENT vs TEMPERATURE

o

-25

25
50
TEMPERATURE (DC)

75

100

125

Vx OFFSET/BIAS CURRENT vs TEMPERATURE
2_0

15

--

10
1.0
:(

BIAS CURRENT

:( 5

5

~

...

iii

-

w

!zW

0

0:
0:

OFFSET CURRENT

0

BIL CURJENT

~

I
OFFSET CURRENT

0:
0:

~ -5

:::>
t.l

-1.0
-10
-15

-55

-25

02550

75

100

-2.0
-55

125

TEMPERATURE (DC)

o

-25

75
25
50
TEMPERATURE (DC)

100

125

:!?

:5

SIGNAL/CONTROL CMRR vs TEMPERATURE

..... 0


m

1.97
1.96
15
-55

-25

0

25
50
75
TEMPERATURE (DC)

100

1.95
-55

125

-25

02550
75
TEMPERATURE (DC)

100

125

MULTIPLICATON ERROR vs TEMPERATURE
WORST CASE MULTIPLICATION ERROR vs TEMPERATURE

Vx

1.8 "T"--y----r--"""T---,r--,----r----,

!a:

1.6 -1---1---1---+--4--_1____+-___1
ERROR

!5

0

a:
a:
W
z

I yo

a: 1.4 +---+---+---+---I---I---::::o.-FI!"""--I

ffi

~

V

"

0

~

U

~

1.2-1---1---I---+~~--_I_-~-___I

:J

I-

",'"

5::>

~

~~

0-

::iE

1.0 -I---boo"""'--I---+--4--_I_-~-___I

-'"

0.8--=55::----2~5::--0~--:2=5:------:!50:--=75::-----:17oo::-~125

1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
-55

= 2V,

Vy

= 5V

./

.......
..,,-

......

""

1000"""
-25

25
75
0
50
TEMPERATURE (DC)

100

125

TEMPERATURE (DC)

MULTIPLICATION ERROR vs Vx

Die Characteristics

Vy = +5V and -5V
2.0
1.8

a:

!fa:
~§"
Ow
fi~

1.2
1.0

UW 0.8
it~

5::>
::iE

,,

1.6

~

1.4

0.6

i'IIIIIII .....
N

~

,
I

'1

:--...

Vy- +5
Vy

=-5V"

~ ii:!!!!!r.

Transistor Count ..................................• 75
Die Dimensions .................. 79.9x119.7x19mils
(2030 x 3040 x 480/lm)
Substrate Potential" ..........•..•.................. VProcess ..................... High Frequency, Bipolar, DI
Passivation .................................... Nitride
Thermal Constants (OC/W)
Sja
Sjc
HA1 -2547..................
76
17.3

*

0.4
0.2
0.0
0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

Vx VOLTAGE (VOLTS)

8-84

The substrate maybe left floating (Insulating Cie Mount) or it may be on a
conductor at V- potential.

HA-2547
Applications Information

A typical multiplier configuration is shown in Figure 2. The
ideal transfer function for this configuration is shown below,
illustrating two quadrant operation:

Theory of Operation
The HA-2547 is a current output, two quadrant multiplier
with one differential signal channel, Vy+ and Vy_, and one
differential control channel, VX+ and VX-. Figure 1 shows a
detailed functional block diagram of the HA-2547. The
differential voltages of channels Vx and Vy are converted to
differential currents. These differential currents are then
multiplied in a circuit similar to a Gilbert Cell multiplier,
producing a differential current product. The differential
product currents are then converted to a single-ended
output current which is typically 2mA, ±20% at full scale
IYx = 2V , Vy = ±5V). A trimmed internal scaling resistor,
RZ, is designed to convert the output current to an accurate
voltage by grounding RZ (pin 10). RZ is trimmed such that
at full scale output current the voltage drop across RZ will
be ±5.0 volts.

(VX+ - VX-)(Vy+ - Vy)
VOUT=

2

,when (VX+ - VX-) ~ 0

o

,when (VX+ - VX-) < 0

The VX- pin is usually connected to ground so that when
VX+ is negative there is no signal at the output, i.e. two
quadrant operation. If the Vx input is a negative going signal
the VX+ pin maybe grounded and the VX- pin used as the
input. The Vy_ terminal is usually grounded allowing Vy+ to
swing ±5 volts. RZ is normally used as a feedback resistor
for an external op amp to provide an accurate currentto-voltage conversion. The scale factor is normally set to 2
by connecting GA B to GA C. Therefore, the transfer function becomes:
VOUT=

+Vo----I

!-------oVREF

-V 0 - - - - 1

The multiplication error is trimmed to be minimum at full
scale, Vx = 2V and Vy = ±5V. When Vy = ±5V, the worst
case multiplication error occurs when Vx "" 0.8V (Refer to
typical performance curves).

VYlOA
VYlOB

Vy
lOUT

GAA

GAB
GAC

The transfer equation for the HA-2547 is:
lOUT

=

VOUT =

(VX+ - VX-)(Vy+ - Vy_),

RZ

SF

0

where

RZ

SF = Scale Factor
RZ = 2.5kV (Internal)
VX, Vy = Differential Inputs
The scale factor is used to maintain the output of the
multiplier within the normal operating range of ±5V. The
scale factor can be defined by the user by way of an
optional external resistor, REXT, and the Gain Adjust pins:
Gain Adjust A (GA A), Gain Adjust B (GA B), and Gain Adjust C (GA C). The scale factor is determined as follows:
SF = 2, when GA B is shorted to GA C
SF '" (1.2)(REXT), when REXT is connected between
GA A and GA C (REXT is in kO)
SF '" (1.2)(REXT + 1.667kO), when REXT is connected to
GA Band GA C (REXT is in kO).
The scale factor can be adjusted from 2 to 5. It should be
noted that any adjustments to the scale factor will affect the
AC performance of the control channel, VX. The normal
input operating range of Vx is equal to the scale factor
value.

FIGURE 2_

Operation At Various Supply Voltages
The HA-2547 will operate over a range of supply voltages,
±8 to ±15volts. Use of supply voltages below ±12 volts will
cause degradation of electrical parameters.
Offset Adjustment
The signal channel offset voltage may be nulled by using a
20K potentiometer between VYIO Adjust pins A and Band
connecting the wiper to -VS. Reducing the signal channel
offset voltage will reduce Vx AC feedthrough and improve
the multiplication error. Output offset voltage can also be
nulled by connecting VZ- to the wiper of a potentiometer
which is tied between +V and -V.

8-85

HA-2556

mHARRIS
PRELIMINARY

Wideband Four Quadrant
Voltage Output Analog Multiplier

August 1991

Features

Description

• High Speed Voltage Output •••••••.••••••.• 350V"~s

The HA-2556 is a monolithic, high speed, four quadrant,
analog multiplier constructed in the Harris Dielectrically
Isolated High Frequency Process. The high frequency per·
formance of the HA-2556 rivals the best analog multipliers
currently available including hybrids.

• Low Multiplication. Error •.•••••••••••••••.•••• 1.5%
• Input Bias Currents .••••••••••••••••••••••••••.

5~A

• Y Input Feedthrough ..•.•••••.••.••••••..•.• -GOdB
• Wide X and Y Channel Bandwidth ••••••••••. 30MHz
• Gain Flatness to 10 MHz ..••••.••••.•••••.•• 0.10dB

Applications
• Military Avionics
• Missile Guidance Systems
• Medical Imaging Displays
• Video Mixers

The HA-2556 has a voltage output X and Y channel band·
width of 30M Hz, and a 350V/~s slew rate. High bandwidth
and slew rate make this part an ideal component for use in
video systems. The suitability for precision video applications
is demonstrated further by the 0.1 dB gain flatness to 1OM Hz,
1.5% multiplication error, -60dB feedthrough and
differential inputs with 5~A bias currents. The HA-2556 also
has low differential gain (0.1%) and phase (0.1 0 ) errors.
The HA-255G is well suited for AGC circuits as well as
mixer applications for sonar, radar, and medical Imaging
equipment. The voltage output of the HA-2556 simplifies
many designs by eliminating the current-lo-voltage conver·
sion stage required for current output multipliers.

• Sonar AGC Processors
• Radar Signal Conditioning
• Voltage Controlled Amplifier
• Vector Generator

Pinout

The HA-2556-9 has guaranteed operation from -40 0 C
to +850 C. The HA-2556-5 has guaranteed operation
from OOC 10 +700 C. The HA-2556 is available in a 16 pin
Ceramic DIP. For MIL-STD-883 compliant product and
LCC packages consult the HA-2556/883 datasheet.

Simplified Schematic

HA1-2556 (CERAMIC DIP)
TOP VIEW

+V

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
c"opyright @l Harris Corporation 1991

8-86

File Number

2477.1

Specifications HA-2556
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- Terminals .••...••••.••.•..••.• 35V
Differential Input Voltage ................................... BV
Output Current ....................................... :l:60mA
Maximum Junction Temperature ....................... +175 0 C

HA-2556-9 ............................. -400 C TA +850 C
HA-2556-5 ............................... ooc.:s TA.:s HOOC
Storage Temperature Range ............. -650C.:s TA.:s +150oC

:s :s

Electrical Specifications V+ = 15V, V- = -15V, RL = 1 K, CL = 50pF, Unless Otherwise Specified
HA-2556-9
PARAMETER

TEMP

MIN

+250 C
Full
Full

HA-2556-5

TYP

MAX

-

1.5

3

-

3.0

6

-

0.003

-

MIN

TYP

MAX

UNITS

-

1.5

3

%

3.0

6

%

0.003

-

%/oC

MULTIPLIER PERFORMANCE
Multiplication Error (Note 2)

Multiplication Error Drift
Differential Gain (Note 3,10)

+250 C

-

0.1

0.2

-

0.1

0.2

%

Differential Phase (Note 3,1 0)

+250 C

-

0.1

0.3

-

0.1

0.3

Deg.

0.1

0.2

0.2

dB

-

-

0.1

5

5

-

260

-

-

260

0.03

-

-

0.03

-

Gain Flatness (Note 6,1 0)
+250 C

-

Scale Factor

+250 C

1% Vector Bandwidth Error

+250 C

THD+ N (Note 4)

+250 C

-

DCto10MHz

V
kHz
%

Voltage Noise (Note 12)
fo=10Hz

+250 C

400

150

-

-

+25 0 C

-

400

fo=100Hz

-

150

-

fo=1kHz

+250 C

-

75

-

-

75

-

nV/..jHz

-

3

10

-

3

10

mV

8

20

-

8

20

mV

45

-

-

45

-

~VfOC

5

10

-

5

10

~
~

<0::
00

~

D..o

nV/y'HZ
nV/..jHz

SIGNAL INPUT, VX, Vy, Vz
Input Offset Voltage

+250 C

-

Full
Average Offset Voltage Drift

Full

Input Bias Current

+250 C

Input Offset Current

+250 C

Differential Input Resistance

+250 C

Small Signal Bandwidth (-3d B)

+250 C

Full Power Bandwidth (Note 5)

+250 C

Y Input Feedthrough (Note 11)

-

Full

Full

10

15

0.5

1

1.0

1.5

720

-

10

15

0.5

1

1.0

1.5

~

720

-

kO

9.5

-

-

-80

-

dB

-

:1:5

-

-

:1:9

Valls

78

-

60

78

-

350

-

-

350

11

-

-

+250 C

-

-60

-

Differential Input Range

+250 C

:1:5

-

Common Mode Range

+250 C

-

:1:9

Full

60

Slew Rate (Note 7)

+250 C

Rise Time (Note 8)

+250 C

Overshoot (Note 8)

+250 C

-

Propagation Delay

+250 C

-

25

Settling Time (Note 7) 0.1 %

+250 C

-

200

CMRR (Note 6)

-

30
9.5

30

MHz
MHz

V

dB

VX, Vy TRANSIENT RESPONSE

8-87

17

11

-

V/~s

ns

25

-

ns

200

-

ns

17

%

~

5

.... 0

w(!J

en ....

<
<

:z

Specifications HA-2556
Electrical Specifications (Continued) v+ = 15V, v-

= -15V, RL = 1K, CL = 50pF, Unless Otherwise Specified
HA-2556-9

PARAMETER

TEMP

MIN

TYP

HA-2556-5
MAX

MIN

-

-

TYP

MAX

UNITS

Vz TRANSIENT RESPONSE
Slew Rate (Note 7)

+250 C

Rise Time (Note 8)

+250 C

Overshoot (Note 8)

+250 C

Propagation Delay

+250 C

SetUing Time (Note 7) 0.1 %

+250 C

-

350
11

17

-

-

25

-

200

-

-

350

11
17
25

-

200

-

±6.05

±20

±45

-

-

VIps
ns
%

ns

-

ns

-

Volts

OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 13)

Full

-

±6.05

Output Current

Full

±20

±45

+250 C

-

1

PSRR (Note 9)

Full

-

63

-

Supply Current

Full

-

16

20

Output Resistance

-

1

-

-

mA

n

POWER SUPPLY

-

63

-

dB

16

20

mA

NOTES:

1. Absolute maximum ratings are limiting values, applied indivIdually.
beyond which the .ervicability of the circuit may be Impaired. Functional
operation under any of these conditions is not necessarily implied.
2. Error Is percent of full scala, 1%

3. fo

::::I

7. VOUT

~

0 10 ±SV.

e. VOUT = 0 to ± l00mV.
9. Vs = ±12V to ±ISV.

50mV.

10. Guaranteed by characterization and not 100% tested.

= 4.43MHz. Vy = 300mVp·p. 0 to 1Vdc off.e~ Vx = 5V.

4. fo = 1 DkHz, Vy = lVrms, Vx = SV.

'1. fo = SMHz.

5. Full Power Bandwidth calculated by equation:

'2. VX=Vy=O.

FPBW =

~. Vpeak = 5V.

'3. Vx

= S.SV, Vy = ±S.5

2nVpeak

6. VIN = D to ±ID.

Functional Block Diagram

~---------------l

I vx+

~
+

VX_

-

1JSF

OUT

•

I
I
I

x

I
I
:

v

HA-2556

_-:;'~I

x

I

z

+

VZ+

I

I1 _Vy_
VZ- I
______________ _
The transfer equation for the HA-2556 is:
(vx+ - Vx-) (VY+ - Vy_) SF (vz+ - VZ-),
where SF Scale Factor 5V
VX, VY, VZ Differential Inputs.

=
=

=
=

8-88

HA-2557

tmHARRIS
PRELIMINARY

Wideband Four Quadrant
Current Output Analog Multiplier

August 1991

Features

Description

• Low Multiplication Error ...................... 1.50/0

The HA-2557 is a monolithic, high speed, four quadrant,
analog multiplier constructed in Harris' Dielectrically
Isolated High Frequency Process. The high frequency
performance of the HA-2557 rivals the best analog multipliers currently available including hybrids.

• Input Bias Currents ............................ 51lA
• Y Input Feedthrough @ 5MHz ••••••.••••••••• -GOdB
• Wide X and Y Channel Bandwidth ••••••••.• 100MHz

Applications
• Military Avionics
• Missile Guidance Systems
• Medical Imaging Displays

The current output of the HA-2557 allows it to achieve
higher bandwidths than voltage output multipliers. Full
scale output current is trimmed to 1.6mA. An Internal
2500n feedback resistor is also provided to accurately'
convert the current, if desired, to a full scale output voltage
of ±4V. The HA-2557 Is not limited to multiplication
applications only; frequency doubling and power detection
are also possible.

• Video Mixers
• Sonar AGe Processors
• Radar Signal Conditioning
• Voltage Controlled Amplifier

The HA-2557-9 has guaranteed operation from -400 C to
+85 0 C, while the HA-2557-5 has guaranteed operation
from OOC to +700 C. The HA-2557 is available in a 16 pin
Ceramic DIP. For MIL-STD-883 compliant product and
LCC packages consult the HA-2557/883 datasheet.

o Vector Generator

Pinout

The single-ended current output of the HA-2557 has a
1OOMHz signal bandwidth (RL = 50n). High bandwidth and
low distortion make this part an ideal component in video
systems. The suitability for precision video applications is
demonstrated further by low multiplication error (1.5%), low
feedthrough (-60dS), and differential inputs with low bias
currents (5IlA). The HA-2557 is also well suited for mixer
circuits as well as AGC applications for sonar, radar, and
medical imaging equipment.

Schematic

HA1-2557 (CERAMIC DIP)
TOP VIEW

CAUTION; These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

8-89

File Number

2478.2

Specifications HA-2557
Absolute Maximum Ratings (Note 1)

Operating Temperature Range

Voltage Between V+ and V- Terminals •••••••••••••.••••••• 35V
Differential Input Voltage •••••••••••••••••..•••••••.••••.••• 6V
Output Current ••••.•••.•••••.•••.•••••••.•••••••••••••• 3mA
Maximum Junction Temperature ..•••..•••.•..••••••••• +1750C

HA-2557-9 ••.••••.•.•••••.•••••••••••.• -4(lOC ~ TA ~ +85 0C
HA-2557-5 ••.•.••.•.•••.•.•••••..•....... (lOC:o; TA ~ +70oC
Storage Temperature Range •••••••.••.•• -65°C :0; TA:S +150 oC

Electrical Specifications +V = +15V, -V = -15V, Unless Otherwise Specified
HA-2557-9
PARAMETER

TEMP

I

MIN

HA-2557-5

TYP

MAX

1.5
3.0
0.003
10
0.03
6
14

3
6

15
20

-

-

4

10
20

MIN

TYP

MAX

UNITS

1.5
3.0
0.003
10
0.03
6
14

3
6

%FS
%FS

-

%JOC

MULTIPLIER PERFORMANCE
+260 C
Full
Full
+25 0C
+25 0C
+250C
Full
Full

-

Input Offset Current

+250 C
Full
Full
+250C
Full
+250 C

Diflerentiallnput Resistance
Small Signal Bandwidth (-3dB) (Note 5)
Y Input Feedthrough (Note 8)
Diflerentiallnput Range
Common Mode Range

+250C
+250C
+25 0C
+25 0C
+250 C

±4
-

Full

60

+250 C
+25 0C

-

Multiplication Error (Note 2)
Multiplication Error Drift
Scale Factor
THD+N (Note 3)
Output Offset Voltage (Note 4)
Average OffsetVoltage Drift

-

-

-

15
20

kV-O
%
mV
mV

-

-

4

10

8
35
5
10
0.5
1.0
720

20

mV
mV

-

"VJOC

10
15
1
1.5

IIA
IIA
IIA
IIA

"VJOC

VX,Vy,VZ
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current

Full

CMRR (Note 6)

8
35
5
10
0.5
1.0
720

-

-

-

10
15
1
1.5

-

-

-

100
-60

-

-

-

-

±4

±9
78

-

60

5

-

-

-

±9
78

-

kO
MHz
dB
Volts
Volts
dB

5
3

-

ns
ns

4
1.6

-

Volts

-

MO

100
-60

-

VX, Vy TRANSIENT RESPONSE (Note 5)
Rise Time
Propagation Delay

-

-

3

-

-

4
1.6
2500
1.5

-

-

2500
1.5

63
18

20

-

63
18

OUTPUT CHARACTERISTICS
Full Scale Output Compliance Voltage
Full Scale Output Current

~?50C

Internal Feedback Resistor (RZ)
Output Resistance

+:<:50C
+250C

-

Full
Full

-

rull

-

mA

0

POWER SUPPLY
PSRR (Note 7)
ICC

-

NOTES:
1. Absolute maximum ratings are limiting values, applied individually.
beyond which the servicability of the circuit may be impaired. Functional
operation under any of these conditions Is not necessarily implied.

2. Error Is percent of full scale, 1% =- 50mV.

3. 10 = 10kHz, Vy = 1Vrms, Vx = 4V.

= OV, Vy = OV.
= 500.
VCM = 010 ±9V.

4. Vx

5. Rl
6.

7. Vs

8. fo

8-90

1::1

±12V to ±15V.

= 5MHz. Relative to full scale output.

20

dB
mA

HA-2557
Test Circuits
AC AND TRANSIENT RESPONSE TEST CIRCUIT

Vy TRANSIENT RESPONSE
Vertical Scale: Top 5V/Div Bottom: 100mV/Div
Horizontal Scale: 20ns/Div

en
l-

S

-,0

«D:

00
we.!)

c..
en o
......

«

z

«

8-91

ICL8013

HARRIS
SEMICONDUCTOR

Four Quadrant
Analog Multiplier

GENERAL DESCRIPTION

FEATURES

The ICL8013 is a four quadrant analog multiplier whose
output is proportional to the algebraic product of two input
signals. Feedback around an internal op-amp provides level
shifting and can be used to generate division and square
root functions. A simple arrangement of potentiometers may
be used to trim gain accuracy, offset voltage and feedthrough performance. The high accuracy, wide bandwidth,
and increased versatility of the ICL8013 make it ideal for all
multiplier applications in control and instrumentation systems. Applications include RMS measuring equipment, frequency doublers, balanced modulators and demodulators,
function generators, and voltage controlled amplifiers.

• Accuracy of ± 0.5% ("An Version)
• Full ± 10V Input Voltage Range
• 1MHz Bandwidth
• Uses Standard ± 15V Supplies
• Built-in Op Amp Provides Level Shifting, Division and
Square Root Functions

ORDERING INFORMATION
Part
Number

Multiplication
Error

Temperature
Range

Package

ICL80l3AM TX
ICL80l3BM TX
ICL80l3CM TX
ICL80l3AC TX
ICL80l3BC TX
ICL80l3CCTX

±0.5% }
±l%
MAX
±2%

- 55'C to + l25'C
- 55'C to + l25'C
- 55'C to + l25'C
O'Cto +70'C
O'Cto +70'C
O'Cto +70'C

10-LEAD
TO-l00

±5% }
±l% MAX
±2%

ZIN

XIN

Xos

VOLTAGE TO CURRENT
CONVERTER AND
SIGNAL COMPRESSION

Yos

OUTPUT

VYIN

TOP VIEW

(oullin. dwg TO·1DOI
0325-2

Figure 2: Pin
Configuration

ZIN

0325-1

Figure 1: Functional Diagram (Multiplexer)

HARRIS SEMICONDUCTOR'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE
CONDITION OF SALE. THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOT£:: All typical values have been characterized but are not tested.

8-92

File Number

2863

ICL8013
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 1BV
Power Dissipation (Note 1) ..................... 500mW
Input Voltages
(XIN. YIN. ZIN. XOS. YOS. ZOS) ............... VSUPPLY

Operating Temperature Range:
ICLB013XC ........................... O'Cto +70'C
ICLB013XM ....................... -55'Cto + 125'C
Storage Temperature Range .......... -65'C to + 150'C
Lead Temperature (Soldering. 10sec) ............. 300'C

NOTE 1: Derale al 6.8mWI"C for operalion al ambienl lemperalure above 7S'C.

NOTE: Stresses above those listed under "Abso/ute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(Unless otherwise specified T A = 25'C. VSUPPLY= ± 15V. Gain and Offset

Potentiometers Externally Trimmed)
Parameter

Test Conditions

ICL8013A
Min

Multiplier Function
Multiplication Error

Typ
XY

ICL8013B

Max Min

-10

-10

SINE WAVE
ADJUST
SINE WAVE
OUT

NC

TRIANGLE
OUT

C~~~{
FREQUENCY
ADJUST

CURRENT
SOURCE
#2

--' (.)
:;!; a:
(.) (3
w (!)
D-

O
en --'
«
z

2 SINEt'lAVE
ADJUST
4

«

\rORGND
TIMING
CAPACIT'()R
SQUARE WAVE
OUT

V-orGND
11

FM
BIAS

FMSWEEP
INPUT

0326-2

Figure 2: Pin Configuration
(Outline dwg JD)
0326-1

Figure 1: Functional Diagram

HARRIS SEMICONDUCTOR'S SOLE AND EXCLUSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE
CONDITION OF SALE. THE WARRANTY SHALL BE EXCLUSIVE AND SHALL BE IN LIEU OF ALL OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORV, INCLUDING THE IMPLIED

WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: All typical values have been characterized but are not tested.

8-101

File Number

2864

ICL8038
ABSOLUTE MAXIMUM RATINGS
Supply Voltage rJ- to v+) ...•....•..•..........•. 36V
Power Dissipation(l) ........................... 750mW
Input Voltage (any pin) ..•.................... V- to V+
Input Current (Pins 4 and 5) ...................... 25mA
Output Sink Current (Pins 3 and 9) ......•......... 25mA

Storage Temperature Range .......... -65·Cto + 150"C
Operating Temperature Range:
8038AM, 8038BM ................. - 55·C to + 125·C
8038AC, 8038BC, 8038CC ........•...•. O·C to + 70·C
Lead Temperature (Soldering, 10sec) ............. 300·C
NOTE: Stresses above those listed under "Absolute Maximum RaUngs" may cause permanent damage to the device. These are stress ratings only and functional

operation of the device at these or any other conditions above those indicated in the operational secUons of the Specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
NOTE 1: Derale ceramic package aI12.5mW/·C for ambienllemperalures above 10000C.

ELECTRICAL CHARACTERISTICS

rJSUPPLY= ±10Vor +20V, TA=25·C, RL =10kO, Test Circuit Unless

Otherwise Specified)
Symbol

Min
VSUPPLY
V+
V+,VISUPPLY

8038BC(BM)

B03BCC

General Characteristics

Typ

Max

Min

Typ

803BAC(AM)

Max

Min

Typ

Units

Max

Supply Voltage Operating Range
Single Supply

+10

+30

+10

30

+10

30

V

Dual Supplies

±5

±15

±5

±15

±5

±15

V

Supply Current rJSUPPLy= ± 10V)(2)
8038AM, 8038BM
8038AC, 8038BC, 8038CC

12

20

12

15

12

15

mA

12

20

12

20

mA

Frequency Characteristics (all waveforms)
f max

Maximum Frequency of Oscillation

fsweep

Sweep Frequency of FM Input

100

Sweep FM Range(3)

I!>.fI I!>. T

100

100
10

10

35:1

35:1

35:1

FM Linearity 10:1 Ratio

0.5

0.2

0.2

Frequency Drift With Temperature(S)
8038 AC, BC, CC O·C to 70"C

250

180

120

kHz

%
ppmrC

8038 AM, BM, - 55'C to 125'C

t.fl I!>.V

kHz

10

350

Frequency Drift With Supply Voltage
(Over Supply Voltage Range)

0.05

250

0.05

%IV

0.05

Output Characteristics
IOLK

Square-Wave
Leakage Current rJg = 30V)

VSAT

Saturation Voltage (lSINK = 2mA)

0.2

tr

Rise Time (RL = 4.7kO)

180

tf
I!>.D

Typical Duty Cycle Adjust (Note 6)

VTRIANGLE

Triangle/Sawtooth/Ramp
Amplitude (RTRI = 100kO)

1

Fall Time (RL = 4.7kO)

ZOUT

THD

0.2

0.30

0.2

180

40
2

1

0.4

180

0.30

98

%

0.33

XVSUPPLY

0.05

%

Output Impedance (lOUT=5mA)

200

200

200

0

0.22
2.0

THD Adjusted (Use Figure 6)

1.5

NOTES: 2.
3.
4.
5.

0.2
5

0.30

ns
98

0.05

THD (Rs = 1MO)(4)

0.33

2

V

0.1

0.2

0.33

2

p.A
ns

40

40
98

0.4

Linearity
Sine-Wave
Amplitude (RSINE = 100kO)

VSINE
THD

1

0.5

0.22
1.5

0.2
3

1.0

RA and RB currents not included.
VSUPPLy=20V: RA and RB=10kU, f"10kHz nominal; can be extended 1000 10 1. See Figures 78 and 7b.
82kU connected between pins 11 and 12, Triangle Duty Cycle sel al 50%. (Use RA and Re.)
Figure 3, pins 7 and 8 connected, VSUPPLY= ±10V. See Typical Curves for T.C. va VSUPPLY.
6. Nollested, typical value for design purposes only.

NOTE: All typicsJ vaIu6S have been charscttKized but BJ'6 not testsd.

8-102

0.22
1.0
0.8

1.5

XVSUPPLY
"10

"10

ICL8038
TEST CONDITIONS
Parameter

Measure

RA

RB

RL

Cl

SWI

Supply Current

10k!!

10k!!

10k!!

3.3nF

Closed

Sweep FM Range(l)

10k!!

10k!!

10k!!

3.3nF

Open

Frequency Drift with Temperature

10k!!

10k!!

10k!!

3.3nF

Closed

Frequency at Pin 3

Frequency Drift with Supply Voltage(2)

10k!!

10k!!

10k!!

3.3nF

Closed

Frequency at Pin 9

10k!!

10k!!

10k!!

3.3nF

Closed

Pk-Pk output at Pin 2

10k!!

10k!!

10k!!

3.3nF

Closed

Pk-Pk output at Pin 3

10k!!

10k!!

3.3nF

Closed

Current into Pin 9

Output Amplitude:
(Note 4)

I Sine
I Triangle

Leakage Current (011)(3)

Current into Pin 6
Frequency at Pin 9

Saturation Voltage (on)(3)

10k!!

10k!!

3.3nF

Closed

Output (low) at Pin 9

Rise and Fall Times (Note 5)

10k!!

10k!!

4.7k!!

3.3nF

Closed

Waveform at Pin 9

50k!!

-1.6k!!

10k!!

3.3nF

Closed

Waveform at Pin 9

Duty Cycle Adjust:
(Note 5)

I MAX
I MIN

-25k!!

50k!!

10k!!

3.3nF

Closed

Waveform at Pin 9

Triangle Waveform Linearity

10k!!

10k!!

10k!!

3.3nF

Closed

Waveform at Pin 3

Total Harmonic Distortion

10k!!

10k!!

10kn

3.3nF

Closed

Waveform at Pin 2

NOTES: I. The hi and 10 frequencies can be oblained by connecling pin 8 10 pin 7 (fi1il and Ihen connecting pin 8 to pin 6 (f/o). Otherwise apply Sweep Vollage al
pin B (% VSUPPlY +2V)s:VSWEEps:VSUPPlY where VSUPPlY is Ihe lotal supply vollage.ln Figure 7b. pin 8 should vary between 5.3V and 10V wtlh
respect 10 ground.
2. IOVS:V+S:30V, or ±5Vs:VSUPPlyS:±15V.
3. Oscilialion can be hailed by forcing pin 10 10 + 5 volls or - 5 valls.
4. Oulput Amplilude is lesled under slatic conditions by forcing pin 10 to 5.0V then 10 -5.0V.
5. Notlesled; for design purposes only.

Triangle Waveform Linearity. The percentage deviation
from the best-fit straight line on the rising and falling triangle
waveform.
Total Harmonic Distortion. The total harmonic distortion
at the sine-wave output.

DEFINITION OF TERMS:
Supply Voltage (VSUPPLY). The total supply voltage from
V+ toVSupply Current. The supply current required from the power supply to operate the device, excluding load currents and
the currents through RA and RB.
Frequency Range. The frequency range at the square
wave output through which circuit operation is guaranteed.
Sweep FM Range. The ratio of maximum frequency to minimum frequency which can be obtained by applying a sweep
voltage to pin 8. For correct operation, the sweep voltage
should be within the range

r----<..----<_ _ _....._ _... +10V

~

:5

-,0

 5mA), transistor betas and saturation voltages will
contribute increasingly larger errors. Optimum performance
will, therefore, be obtained with charging currents of 10p.A
to 1mAo If pins 7 and 8 are shorted together, the magnitude
of the charging current due to RA can be calculated from:

y+

J.
7

SELECTING RA. RB and C

The waveform generator can be operated either from a
single power-supply (10 to 30 Volts) or a dual power-supply
(± 5 to ± 15 Volts). With a single power-supply the average
levels of the triangle and sine-wave are at exactly one-half
of the supply voltage, while the square-wave alternates between V+ and ground. A split power supply has the advantage that all waveforms move symmetrically about ground.
The square-wave output is not committed. A load resistor
can be connected to a different power-supply, as long as
the applied voltage remains within the breakdown capability
of the waveform generator (30V). In this way, the squarewave output can be made TTL compatible (load resistor
connected to + 5 Volts) while the waveform generator itself
is powered from a much higher voltage.

10k

l00kO
lOOk/I

10k
V_orQND

0326-19

Figure 6: Connection to Achieve
Minimum Sine-Wave Distortion

NOTE: AU typical vsJues have be6n characterized but are not tested.

8-108

ICL8038

~--~------~------~--~~v+

SW~I!P
VOLTAGE

. . - - -......- - - _ -......--oy+
RL

• R.
r>-7

5

4

8

Ra
4

8t-~IlIt

RL

5

8

81-~nn

R

3_"1/\,

ICL8038

ICLB038

T
FM
L-~lrO______~11______~1~2_2~~~

~~10~____~11r-____~lr2~2~~

·81k

81k
~------+-------~----~y-orGND

L-------+-------~----__oy-orOND

0326-20

0326-21

Figure 7: Connections for Frequency Modulation (a) and Sweep (b)

FREQUENCY MODULATION AND
SWEEPING

y+

RI

RA

The frequency of the waveform generator is a direct function of the DC voltage at terminal 8 (measured from V+). By
altering this voltage, frequency modulation is performed.
For small deviations (e.g. ± 10%) the modulating signal can
be applied directly to pin 8, merely providing DC decoupling
with a capacitor as shown in Figure 7a. An external resistor
between pins 7 and 8 is not necessary, but it can be used to
increase input impedance from about 8kO (pins 7 and 8
connected together), to about (R+8kO).
For larger FM deviations or for frequency sweeping, the
modulating signal is applied between the positive supply
voltage and pin 8 (Figure 7b). In this way the entire bias for
the current sources is created by the modulating signal, and
a very large (e.g. 1000:1) sweep range is created (f=O at
Vsweep=O). Care must be taken, however, to regulate the
supply voltage; in this configuration the charge current is no
longer a function of the supply voltage (yet the trigger
thresholds still are) and thus the frequency becomes dependent on the supply voltage. The potential on Pin 8 may
be swept down from V+ by (Va VSUPPLy-2V).

5

7 4

8 2~PUTUDE

-,iffh.

ICL8038

0

4.7k

'1

10

f!?

::;

'---

C

L-____________

--,0
c:(a:

00

":"
~--------~~--~y_

0326-22

Figure 8: Sine Wave Output Buffer Amplifiers
trol Pin 8 exceed the voltage at the top of RA and Rs by a
few hundred millivolts. The Circuit of Figure 10 achieves this
by using a diode to lower the effective supply voltage on the
ICl8038. The large resistor on pin 5 helps reduce duty cycle
variations with sweep.
The linearity of input sweep voltage versus output frequency can be significantly improved by using an op amp as
shown in Figure '11.

APPLICATIONS
The sine wave output has a relatively high output impedance (1 kO Typ). The circuit of Figure 8 provides buffering,
gain and amplitude adjustment. A simple op amp follower
could also be used.
With a dual supply voltage the external capacitor on Pin
10 can be shorted to ground to halt the ICl8038 oscillation.
Figure 9 shows a FET switch, diode ANDed with an input
strobe signal to allow the output to always start on the same
slope.
To obtain a 1000:1 Sweep Range on the ICl8038 the
voltage across external resistors RA and Rs must decrease
to nearly zero. This requires that the highest voltage on con-

USE IN PHASE-LOCKED LOOPS
Its high frequency stability makes the ICl8038 an ideal
building block for a phase-locked loop as shown in Figure
12. In this application the remaining functional blocks, the

NOTE: AU typical values have been characterized but am not lestBd.

8-107

wCI

g,g
c:(

:z
c:(

ICL8038
1N457

r-------~----------------~---o~w
CYCLE

11k

R_

Ik

1511

4.7k

•

•

I

INt14
10

11

2

10k

.I1Il.

ICL8038

FREQUENCY

INIl4
..............1-<>8TAOBE

10111e
OFF

C

'V\,

V~::::~;:::

-1$V

DISTORTION
lGOIc
-IDY

ON

0326-23

Figure 9: Strobe-Tone Burst Generator

0326-24

Figure 10: Variable Audio Oscillator,
20Hz to 20kHz

HIGH
FREQUENCY
SYMMETRY

lN753A

l00k0

(8.2V)

4.7kfl

lkO

lMIi
LOW
FREQUENCY
SYMMETRY

9

lkO

---I.

'>-......'VIJ'v.......

SINE-WAVE
OUTPUT

ICLS038
FUNCTION GENERATOR

11

10

"'"

3

12

IOkO
OFFSET

l00k1l

3,1IOOpF

SINE-WAVE
DISTORTION

~----~----~------~----------~--------------"""~-15V
0326-25

Figure 11: Linear Voltage Controlled Oscillator
phase-detector and the amplifier, can be formed by a number of available IC's (e.g. MC4344, NE562, HA2800,
HA2820)
In order to match these building blocks to each other, two
steps must be taken. First, two different supply voltages are
used and the square wave output is returned to the supply
of the phase detector. This assures that the VCO input voltage will not exceed the capabilities of the phase detector. If
a smaller VCO signal is required, a simple resistive voltage
divider is connected between pin 9 of the waveform generator and the VCO input of the phase-detector.

Second, the DC output level of the amplifier must be
made compatible to the DC level required at the FM input of
the waveform generator (pin 8, O.8V+). The simplest solu. tion here is to provide a voltage divider to V+ (Rt, R2 as
shown) if the amplifier has a lower output level, or to ground
if its level is higher. The divider can be made part of the lowpass filter.
This application not only provides for a free-running frequency with very low temperature drift, but it also has the
unique feature of producing a large reconstituted sinewave
signal with a frequency identical 10 that at the input.
For further information, see Harris Application Note A013,
"Everything You Always Wanted 10 Know Aboul The
ICl8038."

NOTE: All typical values havs been characterized but 818 not tested.

8-108

ICL8038
r-------~~--------._--------~-----oV++

TRIANGLE
OUT
V+~----~----~~--------

"Iv

__--,
SQUARE
WAVE
OUT t
fll
SWEEP
INPUT

INPUT

SINE WAVE
OUT

rvv

ICL8038

SINE WAVE
ADJ.

8
10
SINE
WAVE
ADJ.

TilliNG
CAP.

~--------------~------------------~----~---------6---------6----_oV7GND

0326-26

Figure 12: Waveform Generator Used as Stable veo in a Phase-Locked Loop

CURRENT SOURCES

Ra
50

COMPARATOR

800

FUP·FLOP

SINE-CONVERTER

0326-27

Figure 13: Detailed Schematic

NOTE: AD typical values have been charactorized but 8m not tosted.

8-109

ICL8048/ICL8049
Logl Antilog Amplifier
GENERAL DESCRIPTION
The 8048 is a monolithic logarithmic amplifier capable of
handling six decades of current input, or three decades of
voltage input. It is fully temperature compensated and is
nominally designed to provide 1 volt of output for each decade change of input. For increased flexibility, the scale factor, reference current and offset voltage are externally adjustable,
The 8049 is the antilogarithmic counterpart of the 8048; it
nominally generates one decade of output voltage for each
1 volt change at the input.

FEATURES
• Yz% Full Scale Accuracy
• Temperature Compensated for O"C to + 70'C
Operation
• Scale Factor 1V/Decade, Adjustable
• 120dB Dynamic Current Range (8048)
• 60dB Dynamic Voltage Range (8048 & 8049)
• Dual JFET-Input Op-Amps

ORDERING INFORMATION
Part Number

Error (25'C)

Temperature Range

Package

ICL8048BCJE
ICL8048CCJE

30mV
60mV

O'Cto +70'C
O'Cto +70'C

16 Pin CERDIP
16 Pin CERDIP

ICL8049BCJE
ICL8049CCJE

10mV
25mV

O'Cto +70'C
O'Cto +70'C

16 Pin CERDIP
16 Pin CERDIP

r-__~________~~~INP~
14

toUT

,.

GAIN

Your
IS
GAIN

0313-1

(ICL8048)
0313-2

(ICL8049)
Figure 1: Functional Diagram

GROUND

liN

A11NPUT

I

,

NO CONNECTION ,

GAIN 2

,

VIN
GROUND

NO CONNECTION

IREF 3

4

13 AZ OfFSET NULL

Al OFFSET NULL 4

A2 OFFSET NULL

A, OFFSET NULL •

11 A2 OFFSET NULL

A, OFFSET NULL 5

'2 A20FFSETNULL

A1 OFFSET NULL

A, OUTPUT
NO CONNECTION

,

•

t4

.

10

vVOUT

A,OUTPUT 7
NO CONNECTION 8

NO CONNECTION

0313-3

0313-4

Figure 2: Pin Configurations (Outline Dwg JE)

HARRIS SEMICONDUCTOR'S SOLE AND EXCWSIVE WARRANTY OBLIGATION WITH RESPECT TO THIS PRODUCT SHALL BE THAT STATED IN THE WARRANTY ARTICLE OF THE
CONDITION OF SALE. THE WARRANTY SHALL BE EXCLUSive AND SHALL Be IN UEU OF ALL OTHER WARRANTIES, EXPRESS, IMPUED OR STATUTORY, INCLUDING THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR USE.
NOTE: AN typicsJ vs/ues have been chatactstizfld but 818 not tested.

8-110

File Number

2865

ICL8048/ICL8049
ABSOLUTE MAXIMUM RATINGS (ICL8048)
Operating Temperature Range ............ O'C to + 70'C
Output Short Circuit Duration .................. Indefinite
Storage Temperature Range .......... -65'C to + 150'C
Lead Temperature (Soldering, 1Osee) ............. 300'C

Supply Voltage ................................. ± 18V
liN (Input Current) ................................ 2mA
IREF (Reference Current) ......................... 2mA
Voltage between Offset Null and V+ ............. ±0.5V
Power Dissipation ............................. 750mW

NOTE: Stresses above those lis/ed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended pen"ods may aHect device reliabllily.

ELECTRICAL CHARACTERISTICS (ICL8048)

Vs= ±15V, TA=25'C, IREF=1mA, scale factor adjusted

for 1V I decade unless otherwise specified.
Parameter

8048BC

Test Conditions
Min

Dynamic Range
liN (1nA - 1mA)
VIN (10mV - 10V)

Typ

8048CC
Max

120
60

RIN=10kn

Min

Typ

Units
Max

120
60

dB
dB

Error, % of Full Scale

TA=25'C, IIN= 1nA to 1mA

.20

0.5

.25

1.0

%

Error, % of Full Scale

TA=O'Cto +70'C,
IIN=1nAt01mA

.60

1.25

.80

2.5

%

Error, Absolute Value

TA=25'C, IIN=1nA to 1mA

12

30

14

60

mV

Error, Absolute Value

TA=O'Cto +70'C
IIN=1nA to 1mA

36

75

50

150

mV

Temperature Coefficient of VOUT

IIN= 1nA to 1mA

0.8

0.8

Power Supply Rejection Ratio

Referred to Output

2.5

2.5

Offset Voltage (A1 & A2)

Before Nulling

15

Wideband Noise

At Output, for liN = 100,uA

Output Voltage Swing

25

15

mVIV
50

mV

250

""V(RMS)

RL =10kn

±12

±14

±12

±14

V

RL =2kn

±10

±13

±10

±13

Power Consumption
Supply Current

NOTE: AU typk;al values have bsen charactsrized but BF8 not tested.

8-111

250

mVI'C

V

150

200

150

200

mW

5

6.7

5

6.7

mA

ICL8048/ICL8049
TYPICAL PERFORMANCE CHARACTERISTICS
SMALL SIGNAL BANDWIDTH AS A
FUNCTION OF INPUT CURRENT

TRANSFER FUNCTION FOR
CURRENT INPUTS

TRANSFER FUNCTION FOR
VOLTAGE INPUTS

•• I'I::......,""T-..,...,-......,,......-......

lOOk
IREF -!rnA

i
t'"

~
~

.
.,

~,.

~
cz

0

-2

-3t--++-H---f""",,-I-I

~
"

0

-.

in

::l

-&!---+--I-+-jf--+-l----""!

0313-5

!.,
w

150

~
g

125

10-"

'"0

100

'",.ffi

,.;c"
,.c

200

10-1

I
10-1 10-'1

10-1

1000

'34
100

10-5 10-" 10-3

INPUT CURRENT (AMPS)

o

IOmY

CI

10_

0313-9

NOTE: An typical valu6s hBY9 been characf9tized but sre not 1fJsted.

8-112

~'

~

I

g

IN

.~'1v

-

....

........

-t-

- - --

,0 I
ImY

'Omv

1000IV

!!o.,
IV

tOY

INPUT VOLTAGE

INPUT VOLTAGE

0313-8

10

I

III I I
IV

~

OUT

CAS. lDUlI

w

8048 CC IZt·CI

l00mV

,VOLTAGEGAIN.~.~

z

1!itic '25"CI

I

0313-7

_cc"rCI07O"CI

.IoU BC I,O"J ••

5

10-3

SMALL SIGNAL VOLTAGE GAIN AS A
FUNCTION OF INPUT VOLTAGE FOR
RS=10kO

10011

III I r
III I I

_BCI25'CI

25

o

"~

_CC,25'CI

50

-111 I"'N •

I

8048 8C COOC to 1CtC)

10-'

10-'1

0313-6

I I

75

10-1

INPUT CURRENT lAMPS)

MAXIMUM ERROR VOLTAGE AT
THE OUTPUT AS A FUNCTION OF
INPUT VOLTAGE

8048 cc cere to 70"Ct

I

-- f-.

/

100

INPUT CURRENT tAMPS)

I I

1/

10

10. 10 10· t 10.1 10. 7 ,0. 6 10'

MAXIMUM ERROR VOLTAGE AT
THE OUTPUT AS A FUNCTION OF
INPUT CURRENT

10- ~

a

-.L",---I-:,....a-.:-~..J..~L,-..J..,...J

175

I

10

~-V

c

INPUT VOLTAGE

200

10k

~z

w

-I

1--

0313-10

ICL8048/ICL8049
ABSOLUTE MAXIMUM RATINGS (ICL8049)
Supply Voltage .... . . . . . . . . . . . . . . . • . . . • . . . . . . . .. ± 18V
VIN (Input Voltage) ........•..................... ± 15V
IREF (Reference Current) ......................... 2mA
Voltage between Offset Null and V+ ............. ±0.5V
Power Dissipation ........................•.... 750mW

Operating Temperature Range ............ O'C to + 70'C
Output Short Circuit Duration .................. Indefinite
Storage Temperature Range .......... -65'C to + 150'C
Lead Temperature (Soldering, 10sec) ......•...... 300'C

NOTE: Stresses above those/isted under ''Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional

operation of the devies at these or any other conditions above those indicated in the operational sections of the specifications is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (ICL8049)

Vs= ±15V, TA=25'C,IREF=1mA, scale factor adjusted

for 1 decade (out) per volt (in), unless otherwise specified.
Parameter

8049BC

Test Conditions
Min

8049CC

Typ

Max

Min

Units

Typ

Max

Dynamic Range (VOUT)

VOUT= 10mV to 10V

Error, Absolute Value

TA=25'C,OV,,;VIN,,;2V

3

15

60
5

25

mV

Error, Absolute Value

TA=O'Cto +70'C,
OV,,;VIN,,;3V

20

75

30

150

mV

Temperature Coefficient, Referred to VIN

VIN=3V

0.38

0.55

mVI'C

Power Supply Rejection Ratio

Referred to Input, for
VN=OV

2.0

2.0

p.VIV

60

Offset Voltage (A1 & A2)

Before Nulling

15

Wideband Noise

Referred to Input, for
VIN=OV

26

Output Voltage Swing

RL =10kO

±12

±14

RL =2kO

±10

±13

Power Consumption
Supply Current

25

dB

15

50

mV

26

p.V(RMS)

±12

±14

V

±10

±13

V

150

200

150

200

mW

5

6.7

5

6.7

mA

~

TYPICAL PERFORMANCE CHARACTERISTICS

::;

--,0

MAXIMUM ERROR VOLTAGE REFERRED
TO THE INPUT AS A FUNCTION OF VIN
10 r-"T""-'-"""--'-"--"'-""""'"

TRANSFER FUNCTION
(VOUT AS A FUNCTION OF VIN)

10i=1q~;:::1\++=q

«a:

UU
we)

g;g
«
:z
«

.OOIL-~-L~_~~~-1~
~

~

~

~

0

M

d

d

M

INPUT VOLTAGE IVI

INPUT VOLTAGE

0313-11

'v,
0313-12

NOTE: All typical values have been characterized bul are not tested.

8-113

ICL8048/ICL8049
TYPICAL PERFORMANCE CHARACTERISTICS
SMALL SIGNAL BANDWIDTH AS A
FUNCTION OF INPUT VOLTAGE
10M

!

="E~ .,,;,1

SMALL SIGNAL VOLTAGE GAIN AS A
FUNCTION OF INPUT VOLTAGE
-100

'REF· • rnA.

,--

-23

~ 'Mr--t~~~~~~--+-~
~

Z

~
~

-r--- -:---= -:

...

i

'Ok

1----

-

.. -

"- t\.

-=--=
_

-0

'k o

,-

-0.0
INPUT VOLTAGE (VI

,

-

-

--

-

"-

--'\

---

--

-- f-

._f-

-- - f.- - f.- ---

~~

o
INPUT VOLTAGE (VI

0313-13

0313-14

Resistor R2 is external and should be a low T.C. type; it
should have a nominal value of 1kO to provide 1 voltldecade, and must have an adjustment range of ± 20% to allow
for production variations in the absolute value of R1.

ICL8048 DETAILED DESCRIPTION
The ICL8048 relies for its operation on the well-known
exponential relationship between the collector current and
the base-emitter voltage of a transistor:
IC=IS[eqVSE/kL11
(1)
For base-emitter voltages greater than 100mV, Eq. (1)
becomes

ICL8048 OFFSET AND SCALE FACTOR
ADJUSTMENT
A log amp, unlike an op-amp, cannot be offset adjusted
by simply grounding the input. This is because the log of
zero approaches minus infinity; reducing the input current to
zero starves 01 of collector current and opens the feedback
loop around A1. Instead, it is necessary to zero the offset
voltage of A1 and A2 separately, and then to adjust the
scale factor. Referring to Figure 3, this is done as follows:
1)
Temporarily connect a 10kO resistor (Ro) between
pins 2 and 7. With no input voltage, adjust R4 until
the output of A1 (pin 7) is zero. Remove Ro.
Note that for a current input, this adjustment is not
necessary since the offset voltage of A1 does not
cause any error for current-source inputs.
2)
Set IIN=IREF= 1mA. Adjust R5 such that the output
of A2 (pin 10) is zero.
3)
Set IIN=1ILA, IREF=1mA. Adjust R2 for VOUT=3
volts (for a 1 voltl decade scale factor) or 6 volts (for
a 2 voltldecade scale factor).
Step #3 determines the scale factor. Setting liN = 1/LA
optimizes the scale factor adjustment over a fairly wide dynamic range, from 1mA to 1nA. Clearly, if the 8048 is to be
used for inputs which only span the range 100ILA to 1mA, it
would be better to set liN = 100ILA in Step #3. Similarly,
adjustment for other scale factors would require different liN
and VOUT values.

IC = IseQVsE/kT
(2)
From Eq. (2), it can be shown that for two identical transistors operating at different collector currents, the VSE difference (AVSE) is given by:
[IC1]
kT
(3)
AVSE= -2.303X-log10
q
IC2
Referring to Figure 3, it is clear that the potential at the
collector of 02 is equal to the AVSE between 01 and 02.
The output voltage is AVSE multiplied by the gain of A2:

VOUT= -2.303 (R1:2R2) (k;) log10

"-

-'0

-'OOk 11<--+-+- - -- ._- -.

~

(Continued)

L~:F]

(4)

The expression 2.303 x kT has a numerical value of 59mV
q
at 25°C; thus in order to generate 1 voltldecade at the output, the ratio (R1 + R2)/R2 is chosen to be 16.9. For this
scale factor to hold constant as a function of temperature,
the (R1 + R2)/R2 term must have a 1/T characteristic to
compensate for kT/q.
In the ICL8048 this is achieved by making R1 a thin film
resistor, deposited on the monolithic chip. It has a nominal
value of 15.9kO at 25°C, and its temperature coefficient is
carefully designed to provide the necessary compensation.

NOTE: AN typical values have been chsracteriztJd but are not tesl6d.

8-114

ICL8048/ICL8049
~ v+

~ v+
>_VR
_EFf\J(V+\r15_V_)- 0

!

IREF

16

RS

2k.D.

2
10

7

VOUT

Rl

GROUND
C1

150pF
I..

Ro

_~

GAIN 15

AI OUTPUT
I
I
I
I
__ .aI

"

10k.D.

{

15.9k.D.

680.0. (LOW T.C.)
I k.D.

0313-15

Figure 3: ICL8048 Offset and Scale Factor Adjustment
For voltage references equation 7 becomes

ICL8049 DETAILED DESCRIPTION
The ICL8049 relies on the same logarithmic properties of
the transistor as the ICL8048. The input voltage forces a
specific aVBE between 01 and 02 (Figure 4). This VBE difference is converted into a difference of collector currents
by the transistor pair. The equation governing the behavior
of the transistor pair is derived from (2) on the previous
page and is as follows:

AOUT
[
-A2
qVIN]
VOUT=VREFX AREF exp (At+ A2("""i(f

ICL8049 OFFSET AND SCALE FACTOR
ADJUSTMENT
As with the log amplifier, the antilog amplifier requires
three adjustments. The first step is to null out the offset
voltage of A2' This is accomplished by reverse biasing the
base-emitter of 02' A2 then operates as a unity gain buffer
with a grounded input. The second step forces VIN = 0; the
output is adjusted for VOUT = 10V. This step essentially "anchors" one point on the transfer function. The third step
applies a specific input and adjusts the output to the correct
voltage. This sets the scale factor. Aeferring to Figure 4, the
exact procedure for 1 decade/volt is as follows:
1)
Connectthe input(pin # 16)10 + 15V. This reverse
biases the base-emitter of 02' Adjust A7 for
VOUT=OV. Disconnect the input from + 15V.
2)
Connect the input to Ground. Adjust A4 for
VOUT= 10V. Disconnect the input from Ground.
3)
Connect the input to a precise 2V supply and adjust
A2 for VOUT= 100mV.
The procedure outlined above optimizes the performance
over a 3 decade range at the output (i.e., VOUT from 10mV
to 10V). For a more limited range of output voltages, for
example 1V to 1OV, it would be better to usB' a precise 1 volt
supply and adjust for VOUT= tV. For other scale factors
and/or starting pOints, different values for A2 and AREF will
be needed, but the same basic procedure applies.

Ic.
[qaVBE]
-=-=exp
-IC2
kT
When numerical values for q/kT are put into this equation, it is found that a a VBE of 59mV (at 25'C) is required to
change the collector current ratio by a factor of ten. But for
ease of application, it is desirable that a 1 volt change at the
input generate a tenfold change at the output. The required
input attenuation is achieved by the network comprising At
and A2. In order that scale factors other than one decade
per volt may be selected, A2 is external to the chip. It
should have a value of 1kO, adjustable ± 20%, for one decade per volt. At is a thin film resistor deposited on the
monolithic chip; its temperature characteristics are chosen
to compensate the temperature dependence of equation 5,
as explained on the previous page.
The overall transfer function is as follows:
lOUT
[ - A2
qVIN ]
IREF =exp (At + A2) X"""i(f

(6)

Substituting VOUT=IOUTxAOUT gives:
-A2
qVIN]
VOUT= AOUT IREF exp [ (At + A2) X"""i(f

(8)

(7)

NOTE: All typical values have been characteriz9d but lU6 not ft1Stsd.

8-115

!!?
:5

--,0



~

~

10

""""

.1

I"- r-.

0

.01 ~_....L....L..I--lI_-L_..J....~
0

~
~I'\

r'\
"" ~
,
~

-

-2

~
~

10-10 10-1 10-1 10-7 10-1 10-5 10-4 10-3

INPUT VOLTAGE (V)

INPUT CURRENT lAMPS)

0313-17
0313-18

Figure 5

Figure 6

33k.n

0.1 pf
RREF

YREF
(+15Y)

33k.n

4

RS
2k.n

-+

'REF

5

+-oV+

16

RIN
YIN

10

-+

'iN

YOUT

!::
'"
:::J

-,0

GAIN

Al OUTPUT

7

C1
150pf

 TIMEBASE INPUT/OUTPUT
o---{]
o---{::J

21 (RC 2) OUTPUT
28 (RC 256) OUTPUT

[}--~~~~-oVOD

11.

11.

• TIMEBASE PERIOD = 1.0RC;
I SEC. = lMn X I,F

0360-3

NOTE: OUTPUTS + 2' AND + 28 ARE INVERTERS AND HAVE ACTIVE PULLUPS.

Figure 3: Test Circuit

TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

l00Mr--'-.--.--r-r-~-'--'

260

J

240

•

22

120

J'I'

100

// ; /

80
60
40

20

••

....

/

a: 140

5

/
10M

L A"'"

"--1

! 18•
S 160
~

V

TA--20°C

200

a

RECOMMENDED RANGE OF TIMING COMPONENT
VALUES FOR ACCURATE TIMING

{//

".,...

1 V

LA-"'"

1M

......-

~

lOOk

TA =+7!rC

u;

1 1

a:

w

"z
i

I

~

RESET MODE

~

ei

a:
II!

TA· +2S·C

I
10

SUPPLY VOLTAGE

10k

lkf-~=~~

1
12

14

16

tv.
TIMING CAPACITOR, C ("F)

0360-4

DIMENSIONS IN INCHES AND MILLIMETERS

0360-5

TIMEBASE FREE RUNNING FREQUENCY
AS A FUNCTION OF RAND C

MINIMUM TRIGGER PULSE WIDTH AS A
FUNCTION OF TRIGGER AMPLITUDE
1800
1400
1300

TA -

+25"C

.. 1200
;

b

1100
1000

~:

!l700
~600

ffi

VDD·18V

500

~400

t"tr

~: 100

o
•

S
,\

vor=f I" I
1

;.~

-

.......

234587891.
TRIGGER AMPLITUDE (VOLTS)

0360-7

TIME BASE FREQUENCV (Hz)

0360-6

NOTE; All typical vaiuflS have been charact8tfzed but IU8 not tssted.

8-122

ICM7242
TYPICAL PERFORMANCE CHARACTERISTICS
MINIMUM RESET PULSE WIDTH AS A
FUNCTION OF RESET AMPLITUDE
1500
1400
1300
1200

I

I

70 0

~

BOO

ti
ffl
a:

500

~
~

TA -2S0C

I

1100
:;: 1000
::; 900

3E
~

+10.0

I
I

"2

,

800

./
/l

I ,
'Vee = lBV

400
300
200
100

o

I

2

3

"

,

,

+3

+1

-25

...0

I

-8.0

--..::= " , -

~

......
-"'-- -,
~-:::: ~;:-

~
0360-9

I I I I

f
ffi

~

~

,

TAo -+25"'C

==
I

RCCONNECTED
rOGROUND I

--

-f--

1M

C

;;
Q

I

~'00K

r-- 10K

o

I
+50

,~

81012'4"'820

=~

ifi
51

I
+25

'>\;

~--

-8.0

> 10M

C=O.lpF

I

---

100M

sv..; Vee..; 15V

o

~

MAXIMUM DIVIDER FREQUENCY VS. SUPPLY VOLTAGE

~=,

-4
-5

~

-2.0

---

1DOkn .01,..F - -

0360-8

C=O,lp~""

--

......... lL.
~

fa
N

C
.OO1,..F----lOOoF--.1,..F
,Dcn,..F____
IOkIl .01,..F -- ... -_.

SUPPLY VOLTAGE IV)

R-l~Sl~
___

+2

I

D~

0.0

2

I
I

+4

R

101en
lMII
lkll
100kn

S678910

+5

-3

+2.

I

-10.0

NORMALIZED FREQUENCY STABILITY IN THE ASTABLE
MODE AS A FUNCTION OF TEMPERATURE

-1

~

>

[

RESET AMPLITUDE (VOLTS)

-2

+I.0

:i

~

TA • +25·C
0

+4.0

ifi
51f

ve~ -2V

....

~

c

voe -sv

o

~

(Continued)
NORMALIZED FREQUENCY STABILITY IN THE ASTABLE
MODE AS A FUNCTION OF SUPPLY VOLTAGE

2

--- -4

8

8

10

-

12 14

16 18

~

SUPPLY VOLTAGE (V)

0360-"

+75

TEMPERATURE (OC)

0360-,0

DISCHARGE OUTPUT CURRENT AS A
FUNCTION OF DISCHARGE OUTPUT VOLTAGE

OUTPUT SATURATION CURRENT AS A
FUNCTION OF OUTPUT SATURATION VOLTAGE

1

.!Z
a:
a:

:::>
u

.'"
z

iii

III

~

~

Q

0.1.7--'--'-'--'-'L''-;:',:-'---'-~-:--'---'--'--'---'~
.01
0.1
10
OUTPUT SATURATION VOLTAGE (V)

elSCHARGE SATURATION VOLTAGE (V)

0360-'3

0360-12

NOTE: All typical values havs beoo characterizBd but are not IBsIf1d..

8-123

ICM7242
transistor turns on, discharging the timing capacitor C, and
all the flip-flops in the counter chain change states. Thus,
the outputs on terminals 2 and 3 change from high to low
states. After 128 negative timebase edges, the +28 output
returns to the high state.
To use the 8-bit counter without the timebase, terminal 7
(RC) should be connected to ground and the outputs taken
from terminals 2 and 3.

OPERATING CONSIDERATIONS
Shorting the RC terminal or output terminals to VDD may
exceed dissipation ratings and/or maximum DC current limits (especially at high supply voltages).·
There is a limitation of 50pF maximum loading on the TB
I/O terminal if the timebase is being used to drive the counter section. If higher value loading is used, the counter sections may miscount.
For greatest accuracy, use timing component values
shown in the graph under typical performancecharacteristics. For highest frequency operation it will be desirable to
use very low values for the capacitor; accuracy will decrease for oscillator frequencies in excess of 200KHz.
The timing capacitor should be connected between the
RC pin and the positive supply rail, VDD, as shown in Figure
3. When system power is turned off, any charge remaining
on the capacitor will be discharged to ground through a
large internal diode between the RC node and Vss. Do NOT
reference the timing capacitor to ground, since there is no
high-current path in this direction to safely discharge the
capacitor when power is turned off. The discharge current
from such a configuration could potentially damage the device.
When driving the counter section from an external clock,
the optimum drive waveform is a square wave with an amplitude equal to supply voltage. If the clock is a very slow
ramp triangular, sine wave, etc., it will be necessary to
"square up" the waveform; this can be done by using two
CMOS inverters in series, operating from the same supply
voltage as the ICM7242.
The ICM7242 is a non-programmable timer whose principal applications will be very low frequency oscillators and
long range timers; it makes a much better low frequency
oscillator/timer than a 555 or ICM7555, because of the onchip 8-bit counter. Also, devices can be cascaded to produce extremely low frequency Signals.
Because outputs will not be AND'd, output inverters are
used instead of open drain N-channel transistors, and the
external resistors used for the 2242 will not be required for
the ICM7242. The ICM7242 will, however, plug into a socket
for the 2242 having these resistors.
The timing diagram for the ICM7242 is shown in Figure 4.
Assuming that the device is in the RESET mode, which occurs on powerup or after a positive signal on the RESET
terminal (if TRIGGER is low), a positive edge on the trigger
input signal will initiate normal operation. The discharge

.1l..-

_

'"

-os: 'A(V+)

0360-15

Figure 5: Using the ICM7242 as a
Ripple Counter (Divider)
The ICM7242 may be used for a very low frequency
square wave reference. For this application the timing·components are more convenient than those that would be required by a 555 timer. For very low frequencies, devices
may be cascaded (see Figure 6).

0360-16

Figure 6: Low Frequency Reference (Oscillator)
For monostable operation the + 28 output is connected
to the RESET terminal. A positive edge on TRIGGER initiates the cycle (NOTE: TRIGGER overrides RESEn.
The ICM7242 is superior in all respects to the 2242 except for initial accuracy and oscillator stability. This is primarily due to the fact that high value p-resistors have been
used on the ICM7242 to provide the comparator timing
pOints.

TRIGGER INPUT

(TERMINAL I)

Tn"111111111

LnnruL-fl.J -

'lMEIASE OUTPUT
(JEAUIHALI)

OUTPUT

+

2 OUTPUT (T£AMINAL 2)

+

1281256 OUTPUT

(TERMINAL 3) {ASTABLE
OR "FREE RUN" MODE)
~

1

-~~(V+)

JUUt

It

!--'280C---l

TRIGGER

1211258 OUTPUT

(TERMINAL 3) (UONOSTABLE
OR "ONE SHOT' MODE)

0360-14

Figure 4: Timing Diagrams of
Output Waveforms for the ICM7242_
(Compare with Figure 8)

-.

~

TERMINAL I

TB OUTPUT

__rnTTTf1Jl='t TERMINAL.

OUTPUT

~tTEAMINAL3

0360-17

Figure 7: Monostable Operation

NOTE: All typical values havs been charscl8rized but 8I'B not Issted.

8-124

ICM7242
By selection of Rand C, a wide variety of sequence timing can be realized. A typical flow chart for a machine tool
controller could be as follows:

COMPARING THE ICM7242 WITH THE
2242
ICM7242

2242

a. Operating Voltage
2-16V
4-15V
b. Operating Temp.
-25'Cto +85'C O'Cto +70'C
Range
c. Supply Current
O.7mAMax.
7mAMax.
VDD=5V
d. Pullup Resistors
No
Yes
TB Output
+2 Output
No
Yes
+256 Output
No
Yes
e. Toggle Rate
3.0MHz
O.5MHz
f. Resistor to Inhibit
Oscillator
No
Yes
g. Resistor in Series
with Reset for
Monostable Operation
No
Yes
h. Capacitor TB
Terminal for
No
Sometimes
HF Operation

leM 7240

leM 7242

~r-t~I------rl-t~I----~-----'r-~~
WAIT
5 SEC.

ENABLE
10 SEC.

WAIT
5 SEC.

COUNT
TO 185

ENABLE
55EC.

0360-18

Figure 8
By cascading devices, use of low cost CMOS AND/OR
gates and appropriate RC delays between stages, numerous sequential control variations can be obtained. Typical
applications include injection molding machine controllers,
phonograph record production machines, automatic sequencers (no metal contacts or moving parts), milling machine controllers, process timers, automatic lubrication systems, etc.

SEQUENCE TIMING
0Process Control
0Machlne Automation

OElectro-Pneumatlc Drivers
OMultl-Operatlon (Serial or Parallel Controlling)

~
~

... 0

Sa:
00
We!)

en o
...


~

'0.3

=

1-'~r-t--1-i

-0.2 \--~......

i

'0.1

+-+--hHI--I

1-+-~b:lH-i"""'~7+·-l

R
z

1.0F
l00mF

~~

~

......
,RF I - P,
~~ ...... "'

.GOpF

0.1

1

10

100

" '"
10k lOOk

1/ V
r/ V

...

r/ V

tOp'

'p' tOO

\

Ik

V

10ltF

'n'
.,

I'\.

I'

..

:: 100nF

...... ....... ...... ,'If...... .......

'pF

.M

10M

ns

"

.,
V l..7
17 17 17
.....,!o>( V V V
v'~ V 17 17
17
~
V
l"- I V ~@
17 i7

~~

/1/1/

t

pi

t.

,.1

lOG

t

.0

,OG

1

••

"'

1M

II'\a

....

•

•

TIMIE DILAY

FREQUENCY (Hz)

0363-13

0363-14

0363-15

POWER SUPPLY CONSIDERATIONS

APPLICATION NOTES

Although the supply current consumed by the ICM7555/6
devices is very low, the total system supply can be high
unless the timing components are high impedance. Therefore, use high values for R and low values for C in Figures 4
and 5.

GENERAL
The ICM7555/6 devices are, in most instances, direct replacements for the NE/SE 555/6 devices. However, it is
possible to effect economies in the extemal component
count using the ICM7555/6. Because the bipolar 555/6 devices produce large crowbar currents in the output driver, it
is necessary to decouple the power supply lines with a good
capaCitor close to the device. The 7555/6 devices produce
no such transients. See Figure 3.

OUTPUT DRIVE CAPABILITY
The output driver consists of a CMOS inverter capable of
driving most logic families including CMOS and TTl. As
such, if driving CMOS, the output swing at all supply voltages will equal the supply voltage. At a supply voltage of 4.5
volts or more the ICM7555/6 will drive at least 2 standard
TTL loads.

500
T"

'm'
ri 1ao~F
:: '0,.'
5 h,'

f"... ......... f"...
f"... I""'-.. ...... l......

IOpF

T..... JS·C

10mF

~
", ~(~.+~R,)

I""'-.. ....... ......

~tTr-t-!rl-i--+-+-+-l

TIME DELAY IN THE MONOSTABLE
MODE AS A FUNCTION OF RA AND C

I
I

T .25'C

,oomF

1\-J.-r-'---jH........-+-+-+-l

(Continued)

ASTABLE OPERATION

-zs-c

The circuit can be connected to trigger itself and free run
as a multivibrator, see Figure 4. The output swings from rail
to rail, and is a true 50% duty cycle square wave. (Trip
pOints and output swings are symmetrical). Less than a 1%
frequency variation is observed, over a voltage range of + 5
to +15V.
1.44
f=RC

~

V·
\.)':555155
ElHE 55
•

200

400
TillE·,..

The timer can also be connected as shown in Rgure 4b. In
this circuit, the frequency is:
f = 1.44/(RA + 2Rs)C
The duty cycle is controlled by the values of RA and Rs, by
the equation:
D = Rs/(RA + 2Rs)

100

0363-16

MONOSTABLE OPERATION

Figure 3: Supply Current Transient
Compared with a Standard Bipolar 555
During an Output Transition

In this mode of operation, the timer functions as a oneshot. Initially the external capacitor (C) is held discharged by
a transistor inside the timer. Upon application of a negative
TRIGGER pulse to pin 2, the internal flip flop is set which
releases the short circuit across the external capacitor and
drives the OUTPUT high. The voltage across the capacitor
now increases exponentially with a time constant t=RAC.
When the voltage across the capacitor equals % V +, the
comparator resets the flip flop, which in turn discharges the
capaCitor rapidly and also drives the OUTPtJT to its low
state. TRIGGER must return to a high state before the OUTPUT can return to a low state.
toutput = -In (113) RAC = 1.1 RAC

The ICM7555/6 produces supply current spikes of only
2 - 3mA instead of 300 - 400mA and supply decoupling is
normally not necessary. Secondly, in most instances, the
CONTROL VOLTAGE decoupling capaCitors are not required since the input impedance of the CMOS comparators
on chip are very high. Thus, for many applications 2 capacitors can be saved using an ICM7555, and 3 capaCitors with
an ICM7556.

NOTE: AU typical values have been characterizBd but am not tssted.

8-131

ICM7555/ICM7556
CONTROL VOLTAGE
V+
10k

~~~~~-o~~~
OUTPUT o--t--+'~"""~
CONTROL
VOLTAGE

The CONTROL VOLTAGE terminal permits the two trip
voltages for the THRESHOLD and TRIGGER internal comparators to be controlled. This provides the possibility of
oscillation frequency modulation in the astable mode or
even inhibition of oscillation, depending on the applied voltage.·ln the monostable mode, delay times can be changed
by varying the applied voltage to the CONTROL VOLTAGE
pin.

RESET

0363-17

Figure 48: Astable Operation

The RESET terminal is designed to have essentially the
same trip voltage as the standard bipolar 555/6, i.e. 0.6 to
0.7 volts. At all supply voltages it represents an extremely
high input impedance. The mode of operation of the RESET
. function is, however, much improved over the standard bipolar 555/6 in that it controls only the internal flip flop,
which in turn controls. simultaneously the state of the OUTPUT and DISCHARGE pins. This avoids the multiple threshold problems sometimes encountered with slow falling edges in the bipolar devices.

OUTPUT

V+

v+

t

= 1.1RC

0363-22

Figure 4b:

0363-18

. Figure 5: Monostable Operation

y.

THRESHOLD

o

I

n

CONTROL
VOLTAGE

OUTPUT

....D
R

~

0363-.19

l00kfl ± 20% Typical

Figure 6: Equivalent Circuit

NOTE: All typical va/uss haWl been chsrBct6riz6d but IU6 not tBsted.

8-132

ICM7 555/ICM7 556
TRUTH TABLE
Threshold
Voltage

Trigger
Voltage

RESET

Output

Discharge
Switch

DON'T CARE

DON'T CARE

LOW

LOW

ON

>%(V+)

>y.(V+)

HIGH

LOW

ON

<%(V+)

>y.(V+)

HIGH

STABLE

STABLE

DON'T CARE



-r.!! .,

-2.'

0

2.'

INPUT SIGNAL (VI,I-Y

Fig. 4 -

Typical ON resistance as B function of
input signal voltage at V DD -= - V58

Fig.

<2

7.5V.

9-4

5- Tvpical ON resistance as a

fUffliPon of
input signal voltage at TA ... 25 C.

CD22100

RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected
so that operation is always within the following ranges:
LIMITS

CHARACTERISTIC
Supply·Voltage Range (For T A =
Full Package·Temperature Range)

*

MIN.

MAX.

3

18

UNITS

V

INPUT VOLTAGE [VIII-V

,

STROBE
160~---_

·00

Fig. 7 - Typical switch ON transfer characteristics ( 1 of 16 switches)•

.---,--,----,.---,0, "

*'~
,---+-,-t----.-+--..---+-014

"

*'~

TO OTHER CECODER
GATES/LATCHES

l!~:
. .

.---+-,-+--,-+--,.--+-0'0
"

DETAIL. OF LATCHES

*'~

,

:

I

Q

?;

2

i

1.5

.0----_

NETWORK

f\-

C.o04pF

I I ;--11---,

I I III I

!'
.!..

DETAIL OF TRANSMISSION OATES

PROTECTED
*C05'MOS
'N'UTS BT
PROTECTION

I

> 25 LOAD CAPACITANCE ICLI'15pF

~

·ss

p'pH++-++I-H

INPUT SIGNAL VOL.TAGE I Vis)- 5 v
SINE WAVEII 77VRMS)
DATA-IN VOLTAGE (VOATA_INlo+5V

6

.

*4~

ANSIENT TEMPERATURE ITA)·25·C
SUPPLY VOLTAGE: "00"+5. 'lss'-SV

I!!

VLI

LOAD RESISTANCE
(RLI-INn

fll

RM'

Vo,1

I

SW

I~t--~~~-+++t-t-~i

~ o.,I---I--+-+-l++-+-l++-+-+-I~"1""i""'rl

·00

2
102

4 6 8

2

4 6 8

2

4 6 8

2

4 68

103
104
lOS
INPUT SIGNAL FREQUENY lIi,I-IIHz

10&
!UCS~30268

Fig. 8 - Typical switch ON frequency response
characteristics.

·ss
·ss
Fig, 6- Schematic diagram.

TRUTH TABLE
Select

Address
A

B

C

D

0

0
0

0

0

1

0

0

0

1

0
0

0
0
0
0
0
0

1

1

0

0
0

1

1
1

0

1

1

1

1

1

Select

Address
A

B

C

D

X1Yl

0

0

0

1

X1Y3

X2Yl

1

0

0

1

X2Y3

~~BoH-+++I-++H++'>i"f++++ttt-+-H-H

X3Yl

0

1

0
0

1

X3Y3

§

1

X4Y3

u.1o

1

1

X1Y4

1
1

1

X2Y4

1

1

X3Y4

1

1

1

X4Y4

X4Yl

1

1

X1Y2

0

X2Y2
X3Y2

1
0

0
0

X4Y2

1

9-5

'o!-+-t-tJI:P-I4+tH-tttl-t-tttt-t-t-tt1
012468,2468,02468102246810324&8104
INPUT SIGNAL FREQUENCY "ill - . Hz 9ZCS-502eT

Fig. 9 - Typical crosstalk between switches as a
function of signal frequency.

CD22100
STATIC ELECTRICAL CHARACTERISTICS
LIMITS at Indicated Temperature ( CI
CONDITIONS
Values at -55,+25,+125,apply to D,F,H pkg
CHARAC·
Values at -40,+25,+85,apply to E pkg
TERISTIC
--40

VIN VDD -55
(VI (VI

+85 +125

+25
Typ.

Min.

I

• AMBIENT TENPERATURE(TA)_25-C

Units

Max.

CROSSPOINTS

-

Quiescent
Device Current,lDD
Max.
ON Resist·

Any Switch

ance

VIS=
Oto VDD

RON Max.

AON Resist·
ance,
ARON

Between
any two
switches

OFF Switcb
Leakage
All switches
Current
OFF
ILMax.

-

0.08

-

65

96

25

-

10

-

-

-

5

-

±lOOO

-

±1

±100·

-

-

1.5
3
4

3.5
7

-

-

11

-

-

20

5
10
20

150 150
300 300
600 600

20

100

100

3000 3000

5

475

500

725

10

135

145

205 230

100
70

110

15

155
110

175
125

5

-

-

-

-

10
12

-

-

15

-

-

5
10

5
10

15

-

-

12

0,18

18

-

5

1.5

10
15

3
4

5
10
15

3.5
7
11

-

75

800

-

-

-

±lOO

-

0.04
0.04
0.04

5
10

jJ.A

20
100

225

600

85

180

75

135

8

01 2 4 68.

2;

418 10 2:

SWITCHING

n

48810z 2 4 68KJ'2 4 68 104
FREQUENCY H. )-kHI
UCS-302e8

Fig. 10 - Typical dynamic power dissipation as a
function of switching frequency_

n

16

to
14
13

I'tt

nA

10

CONTROLS

92CS-30269

Input Low
Voltage
VIL Max.

OFF switch
IL <0.2IlA

Input High
Voltage,
VIH Min.

ON switch
see RON
characteristic

Input
Current,
liN Max.

Any control

-

0,18

18

±0.1

±0.1

I

-

Fig. 11 - Quiescent currBnt tBst circuit.

V

Voo
Voo

-

±1

±1

±10-5

±0.1

jJ.A

~

Vss

I.

16

NOTE
MEASURE INPUTS
SEQUENTIALLY TO
80TH Voo AND Yss
CONNECT ALL UNUSED
INPUTS TO EITHER
Voo OR VSS

14

13
12

• Determined by minimum feasible leakage measurement for automatic testing.

tt
10

DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C
CONDITIONS

CHARACTERISTIC
tiS:
kHz

LIMITS

I I
RL
kn

UNITS

Visel VDD
(VI
(VI

Fig. 12 - Input current test circuit.

Min. Typ. Max.

CROSSPOINTS
Propagation Delay Time, (Switch ON)
Signal Input to Output, tpHL' tpLH

-\10
CL

15

I

1
5
1
Sine wave input
Vos
20 log - Vis

Sine. Wave Response, (Distortion)

1

Feedthrough
(All Switches OFF)
·Peak·to~peak

1.6

-

60
30
20

ns

-

30
15
10

-

40

-

MHz

-

15

= 50pF;t" tf = 20ns

I

Frequency Response,
(Any Switch ON)

11~ \1~

I
I

1
1

I
I

I

10

I

I.

= -3 dB
5
5

"I-t-t-....,

I 10
I 10

Sine wave input

-

0.5

-

-80
.

V DD

-

%

11

10
~
,I..:...._ _.:.'r-'IC':L CL

dB
NOTE
CLOSE SWITCH S AFTER
APPLYING Veo

92CS-30271

Fig. 13 - Dynamic power dissipation test circuit.

voltage symmetrical about -2-'

9-6

CD22100
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 25 c C
CONDITIONS
CHARACTERISTIC

lis
kHz

RL
kn

-

1

LIMITS
UNITS

Vis-I VDD
(V) (V)

Min. Typ. Max.

CROSSPOINTS (CONT'D)
Frequency for Signal Crosstalk
Attenuation of 40 dB
Attenuation of 110 dB

10

I 10

-

1.5
0.1

-

-

18
30
0.4

-

Sine wave input

MHz
kHz
vss

Capacitance,
Xn to Ground
Yn to Ground
Feedthrough

-

-

-

-

-

5·15
5-15
-

-

-

pF

Fig. 14 - OFF switch input or output leakage
current test circuit.
ON

See
Fig.

CONTROLS
Propagation Delay Time:
Strobe to Output, tpZH
(Switch Turn·ON to High Level)

RL=lkn,
CL=50pF,
tr,tf= 20 ns

18

5
10
15

Data·ln to Output, tpZH
(Turn·On to High Level)

19

5
10
15

Address to Output, tpZH
(Turn·ON to High Levell

20

5
10
15

18

5
10
15

Data·ln to Output, tpZL
(Turn·ON to Low Level)

19

5
10
15

Address to Output, tpHZ
(Turn·OFF)

5
20 10
15

Propagation Delay Time:
Strobe to Output, tpHZ
(Switch Turn·OFF)

Minimum Setup Time,
Data·ln to Strobe, Address, tsu
Minimum Hold Time,
Data-In to Strobe, Address, tH
Maximum Switching Frequency, f",
RL =lkn,cL=50pF
t" tf = 20 ns

5
10
15
5
10
15
5
10
15

-

-

-

-

-

165 330
85 170
70 140

-

210 20
110 220
100 200

-

-

-

-

0.6
1.6
2.5

Control Crosstal k,
Data·ln, Address, or Strobe to Output

10 110
Square wave input
t r, tf = 20 ns

10

-

Input Capacitance, CIN

Any Control Input

--

-

Minimum Strobe Pulse Width, tw

5
10

15

110 220
40 80
25 50
350 700
135 270
90 180

-

10··Y·0'"

300 600
125 250
80 160

-

v;.~v~
sw- ANY CROSSPOINT
STROBE· DATA-IN -Voo

ns

92CS- 30273

Fig. 15 - Propagation delay time test circuit and
waveforms (signal input to signal output,
switch ON).
CONTROLS

ns

··A~

435 870
210 1420
160 320
95 190
25 50
15 30
180 360
110 220
35 70
1.2
3.2
5
-

-

300 600
120 240
90 180
75

5

=
~
sw -ANY CROSSPOINT

ns

ns

rI
r
---1r lL-..J
L-J

VOO CONTROL 0

V..

50mv-,
0-1"--1'--1--f....-50mV92CIoI-30277

MHz

Fig.

16...... Test circuit and waveforms for crosstalk
(control input to signal output).

ns

-

mV
(peak)

7.5

pF
sw- ANY CROSSPOINT

• Peak-ta-peak voltage symmetrical about VOO-

92C9-502.78

Fig. 17 ...... 'Test circuit for crosstalk between switch
circuits in the same package.

2

9-7

CD22100

STRoeE
DATA-IN

v"
50pF

Voo
V"

SW • ANY CROSSPOINT

Fig. 18 - Propagation delay time test circuit and waveforms (strobe to signal
output, switch Turn-ON or Turn-OFF).

Voo

DATA IN

VIS

~
SW

~

VOl

I lin

VIS _

SW

-

50pF

vo0g;:.
50%

DATA IN
0

tpZL

VOl

1-""'F

-=-

SWe ANY CROSSPOINT
STROBE-VOO

liln

voo-£o
..
VOl

0---

92CM-30275

Fig. 19 - Propagation delay time test circuit and waveforms (data-in to signal output,
switch Turn-ON to high or low leve/).

Voo --:c-tr>l

AODRESS_O

ADDRESS_'

VI.L& V
OO2
""~

ADDRESS

Voo

DATA -IN

"nQ!50~

0-

Voo

SWeANY CROSSPOINT

Vas 2

STROBE- VOO

0

Fig. 20 - Propagation delay time test circuit and waveforms (address to signal output,
switch Turn-On or Turn-OFF).

Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as indicated. Gri~ graduations are in mils (1()-3 inch}.

9-8

CD22101
CD22102

mHARRIS

CMOS 4 x 4 x 2 Crosspoint Switch
With Control Memory

August 1991

Features

Description

• LowONResistance •••••••••• 75VTyp.atVoo=12V

CD22101 and CD22102 crosspoint switches consist of 4 x
4 x 2 arrays of crosspoint (transmission gates) 4-line to 16line decoders and 16 latch circuits. Anyone of the sixteen
crosspoint pairs can be selected by applying the appropriate four-line address, and any number of crosspoints can
be ON simultaneously. Corresponding crosspoints in each
array are turned on and off simultaneously, also.

• "Built-In" Latched Inputs
• Large Analog Signal Capability •••••••••••• ±VOO/2
• Switch Bandwidth •••••.•••••••••••••••••••• 10MHz
• Matched Switch Characteristics ARON = SO Typ. at
VOO = 12V
• High Linearity - 0.25% Oistortion (Typ.) at f = 1kHz,
VIN = 5Vp-p, Voo - VSS = 10V, and Rl = 1kO
• Standard CMOS Noise Immunity

Applications

In the C0221 01, the selected crosspoint pair can be turned
on of off by applying a logical ONE or ZERO, respectively,
to the data input, and applying a ONE to the strobe input.
When the device is "powered up", the states of the 16
switches are indeterminate. Therefore, all switched must be
turned off by putting the strobe high, data-in low, and then
addressing all switches in succession.
The selected pair of crosspoints in the CD22102 is turned
on by applying a logical ONE to the Ka (set) input while a
logical ZERO is on the Kb inut, and turned off by applying a
logical ONE to the Kb (reset) input while a logical ZERO is
on the Ka input. In this respect, the control latches of the
C022102 are similar to SET/RESET flip-flops. They differ,
however, in that the simultaneous application of ONE's to
the Ka and Kb inputs turns off (resets) all crosspoints. All
crosspoints in both devices must be turned off as VOO Is
applied.

• Telephone Systems
• PBX

• Studio Audio Switching
• Multisystem Bus Interconnect

The C022101 and C022102 types are supplied in 24 lead
Hermetic dual-In-line ceramic packages (0 and F suffixes),
24 lead dual-in-line plastic packages (E suffix).

Functional Diagram

Pinouts
CD22101
24 PIN CERAMIC/PLASTIC DIP
TOP VIEW

CD22102
24 PIN CERAMIC/PLASTIC DIP
TOP VIEW

CONTROL
,...A-..

IN (OUT)

:::;;;

~

o
oW

....I

} OUT (IN)

X2

Bla:

Y2
X4

DECODER
LATCH

16

c

X.

!il

X3
Y'

} OUT (IN)

Y3
XI

Ka

-.._ _ _ _.r- Kb

CAUTION: These devices are sensitive to electrostatic discharge. Proper
Copyrighl © Harris Corporalion 1991

XI
~

IN (OUT)

DATA
STROBE

I.e. handling procedures should
9-9

be followed.

FlleNumber

2871

W
I-

Specifications CD2210 1, CD22102
MAXIMUM RATINGS,Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE,IVDDI
--1).510 +20 V
(Voltages referenced to VSS Terminal)
INPUT VOLTAGE RANGE, ALL INPUTS _
-0.5 10 VDD +0.5 V
±10mA
DC INPUT CURRENT, ANY ONE INPUT·_
POWER DISSIPATION PER PACKAGE IPDI:
• . . . . _ • •.
500mW
For TA "-401o +60 oC (PACKAGE TYPE E)
For TA = +ti0 10 +850C (PACKAGE TYPE E)
_
Derate Linearly at 12 mW/oC to 200 mW
....•... _
500mW
For TA = -55 10 +1000C (PACKAGE TYPES D,F)
Derate Linearly at 12 mWfJC to 200 mW
For TA =+100 10 +1250 C (PACKAGE TYPES 0, FI
DEVICE DISSIPATION PER OUTPu'T TRANSISTOR
100mW
FOR TA = FULL PACKAGE-TEMPERATURE RANGE (All Package Types)
OPERATING-TEMPERATURE RANGE ITA):
-55
10
+1250 C
.PACKAGE TYPES 0, F, H
-40 1o +850C
PACKAGE TYPE E • . • • . • • .
-651o +1500C
STORAGE TEMPERATURE RANGE ITstgl
LEAD TEMPERATURE lOURING SOLDERING):
At distance 1/16 ±1/32 inch (1.59±O.79 mm) from case fpr 10s max .

• Maximum current through transmission gates (switches) = 25 mAo

RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges:
LIMITS

CHARACTERISTIC
Supply-Voltage Range (For TA - Full PackageTemperature Range)

Min.

Max.

3

18

UNITS

V

[~~I02
'Kb

21 VI

Ka'

SIGNAI..$
OUT (INI

.

16 Y3

A

23

*

•

I

*
C

2

17 V4

ADDRESS

0
E

C

°0
E

R
S

I.

e

~:

::']SIGNALS
OUT UN)

9 Y3'

*INPUTS
PROTECTED
BY COSJMOS
PROTECTION
NETWORK

---

8 V4'

"

•
X·

7

3'

SIGNALS IN (OUTI

Fig.

t - Functional block diagram.

9-10

CD22101, CD22102

,--.....,.--.....,.---.--0:: (:..)
~';...----'00

.~

~
.~

~
3>------

DETAIL OF TRANSMISSION CATES

·~~f~~E~glE",'"-B
q - .~
",wm

•

'ss

Fig. 2 - Logic diagram.

DECODER TRUTH TABLE
Address
A
B
0
0
1
0
0
1
1
1
0
0
0
1
0
1
1
1

Select
C
0
0
0
0
1
1
1
1

D
0
0
0
0
0
0
0
0

Address
B
A
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1

XIVl & Xl'Vl'
X2Vl & X2'Vl'
X3Vl & XiVl'
X4Vl & X4'Vl'
Xl Y2 & xl'vi
X2Y2 & xivi
X3Y2 & xivi
X4 V2 & x4'vi

Select
C
0
0
0
0

,
1
1
1

D
1
1
1
1
1
1
1
1

X1V3 & x,'vi
X2V3 & X2'V3'
X3V3&x3'V:/
X4V3 & X4'vi
Xl V4 & Xl'V4'
X2V4 & X2'V4'
X3V4 & X3'V4'
X4V4 & X4'V4'

CONTROL TRUTH TABLE FOR C022101
Function

Addre..

Switch On

A
1

Switch 011

1

1

1

No Change

X

X

X

B
1

C
1

Strobe

Data

1

1

1

1

0

X

0

X

D
1

Select
15 (X4V4)&
15' (X4'V4')
15 (X4V4)&
15' (X4'V4')
X X X,X

1 • High Level; O. Low Lev.l; X - Don't Car.
CONTROL TRUTH TABLE FOR CD22102
Function

Switch On

Address
A
B
1
1

C
1

KI

Kb

Seloct

D
1

1

0

Switch Off

1

1

1

1

0

1

All Switches
011#
No Chlngo

X

X

X

X

1

,

15 (X4V4)&
15' (X4'V4')
15 (X4V4) &
15' (X4'V4')
All

X

X

X

X

0

0

XXX X

1 - High Levll; 0 • Low Level; X • Don't c. ...
# In the event that K. and Kb .r. changed from leve', 1,1 to 0,0 Kb should not be allowed to 90 to 0 before KI •
otherwise a switch which was off will inadvertentlv be turned on.

9-11

CD22101, CD22102

STATIC ELECTRICAL CHARACTERISTICS
LIMITS at Indicated Temperature ( CI
CONDITIONS
Values at -55,+25,+125,apply to D,F ,H pkg
CHARAC·
TERISTIC
Values at -40,+25,+85,apply to E pkg
VIS VDD -55
(VI (VI

-40

+85 +125

+25
Typ.

Min.

'"-':

IVI

,"

Units

Max.

CROSSPOINTS
Quiescent
Device Cur·
rent, 100
Max.

ciN Resist·
ance

-

0.04
0.04
0.04
0.08

500
145

725 800 205 230 -

85

600
180

20

5
10
20
100

5
10
20
100

5
10

475
135

5
1'0
15

150
300
600
3000

150
300
600
3000

225

5
10

IlA

20
100

,
INPUT SIGNAL(V" I-V

Any Switch

-

RON Max.

VIS =
Oto VD D

-

12

100

110

155 175

-

75

135

15

70

75

110 125

-

65

95

5
10

-

-

-

-

-

25

Between
any two
switches

-

-

ll.ON Resist·
ance,
ll.RON

-

-

-

-

8
5

n

-

-

0,18

18

tlOOO

-

tl

tl00·

nA

-

5
10
15

1.5
3
4

-

-

-

-

5
10
15

3.5
7
11

3.5
7
11

OFF Leak·
All switches
age Current
OFF
IL Max.

-

12

-

15

-

10

Fig. 3 - Typical ON resistance as a function of
input signal voltage at V DO =

-vss=

n

2.5V.

,

ISUPPl(

"

.TAGE

.+"

I'-'V

h' ,

CONTROLS
Input Low
Voltage
VIL Max.

OFF switch
IL <0.2IlA;

Input High
Voltage,
VIH Min.

ON switch
see RON
characteristic

Input
Current,
liN Max.

Any control

-

-

0,18 18

to.l

to.l

±1

±1

-

tl0-5

1.5
3
4

INPUT SIGNAL.(VI,J-V

Fig. 4 -

V

±0.1

92CS-!U630

Typical ON resistance as B function of
input signal voltage at V DO = - VS8·

5V.

'''''I SUPPLY V----'l.f\/V-_._-..---i

33kn~----'

1

-

-

CDZZ202E

CQ22203E

O.001~

~F

PARAMETER
SYMBOL MIN. TYP. ,.-rAX. UNITS
TONE TIME:
for detection
40
ms
tON
for rejection
20
ms
tON
PAUSE TIME:
for detection
40
ms
tOFF
for rejection
20
ms
tOFF
25
DETECT TIME
46
ms
to
RELEASE TIME
35
50
ms
tR
DATA SETUP
TIME
7
tsu
Jis
DATA HOLD
4.2
TIME
5
ms
tH
DV CLEAR TIME
- 160 250
ns
tel
CLRDV pulse
width
tpw
200 ns
ED Detect Time
7
22
ms
tED
ED Release Time
2
18
ms
tEA
OUTPUT ENABLE
TIME
- 200 300 ns
Cl=50 pF.
Rl = 1 kO
OUTPUT DISABLE TIME
ns
150 200
Cl=35 pF.
Rl = 500 0
OUTPUT RISE
- 200 300
ns
TIME
Cl=50 pF
OUTPUT FALL
TIME
160 250
ns
Cl=50 pF

92C5-42796

-

Fig. 5 - Filter for use in extreme high frequency input noise

environment.

Noise will also be reduced by placing a grounded trace
around XIN and XOUT pins on the circuit board layout
when using a crystal. It is important to note that XOUT is not
intended to drive an additional device. XIN may be driven
externally; in this case. leave XOUT floating.

9-27

-

-

::;;:

o

u

w

-'
w

I-

CD22202~CD22203E
GUARD TIME
Whenever the DTMF receiver is continually monitoring a
voice channel containing distorted or musical voices or
tones, additional guard time may be added in order to
prevent false decoding. This may be done In software by
verifying that both ED and DV are present simultaneously
for about 55 ms. An appropriate guard time should be

selected to balance the fastest expected dialing speed
agalnstthe rejection of distorted or musical voices ortones
(most autodialers operate In the 65 to 75 ms range although
a few generate 50 ms tones). A hardware guard-timecircuit
Is shown below. RS and R4 should keep the voice amplitude
as low as practical, while R2 and R5 adjust detection speed.

+5V

R2
=240K

(55 Ms._)

0'

02--r----------------;

HEX 1B2a
EN
,N'633
VOO

IN4,48

EO
C2
0"5

Vss

04

'6

08--~----------,

4

'5
'4
C022203E
6
'3
'2
5

XEN
ANALOG 'N

9

"

,0

R5
t.8M
R6
'OOK

R4
33 K

-r--------------,

t7

R3
=390K

C ROV

OV
AT8

~IN1ld
CJ
~~

XOUT
Vss

3.58
MHz

C,
4700pF
08 04 02 01
HEX OATA OUT

ENABLE
'NPUT
1/3 CD74HC04

OV
OUT

92CM-42797

(BUFFERS OPT'ONAL I

Fig. 7 - CD22203 DTMF receiver with guard time circuit to
provide exceptional talk-off performance.

OPERATING AND HANDLING CONSIDERATIONS

1.

2.

Handling
All inputs and outputs of RCA CMOS devices have a
network for electrostatic protection during handling.
Recommended handling practices for CMOS devices
are described in ICAN-6525. "Guide to Better Handling
and Operation of CMOS Integrated Circuits."
Operating
Operating Voltage
During operation near the maximum supply voltage
limit, care should be taken to avoid or suppress power
supply turn-on and turn-off transients, power supply
ripple, or ground noise; any of these conditions must
not cause Voo - Vss to exceed the absolute maximum
rating.

9-28

Input Signals
To prevent damage to the Input protection circuit, input
signals should never be greater than Voo nor less than
Vss. Input currents must not exceed 20 mA even when
the power supply is off.
Unused Inputs
A connection must be provided at every input terminal.
All unused input terminals must be connected to either
Voo or Vss, whichever is appropriate.
Output Short Circuits
Shorting of outputs to Voo or Vss may damage CMOS
devices by exceeding the maximum device dissipation.

CD22204

mHARRIS

5V Low-Power Subscriber
DTMF Receiver

August 1991

Features

Description

• No Front-End Band Splitting Filters Required

The CD22204 complete dual-tone multiple-frequency
(DTMF) receiver detects a selectable group of 12 or 16 stand·
ard digits. No front-end pre-filtering is needed. The only
extemally-required components are an inexpensive
3.579545MHz TV "colorbursf' crystal (for frequency reference) and a bias resistor. Extremely high system density is
possible through the use of the Alternate Time Base (ATB)
output of a crystal-connected CD22204 receiver to drive the
time bases of up to 10 additional receivers. This is a monolithic integrated circuit fabricated with low-power, complementary-symmetry CMOS processing. It only requires a single
power supply and is packaged in either a 14 pin dual-in-line
plastic package (E suffix) or a 24 pin plastic SOIC (M suffix).

• Single Low-Tolerance 5V Supply
• Three-State Outputs for Microprocessor-Based
Systems
• Detects all 16 Standard DTMF Digits
• Uses Inexpensive 3.579545MHz Crystal
• Excellent Speech Immunity
• Output in 4-Bit Hexadecimal Code
• Excellent Latch-Up Immunity

The CD22204 employs state-of-the-art "switched-capacitor" filter technology, resulting in approximately 40 poles of
filtering and digital circuitry on the same CMOS chip. The
analog input is preprocessed by 60Hz reject and bandsplitting filters and then zero-cross detected to provide AGC.
Eight bandpass filters detect the individual tones. Digital precessing Is used to measure the tone and pause durations and
provides the correctly coded and timed digital outputs. The
outputs interface directly to standard CMOS circuitry and are
tri-state enabled to facilitate bus-oriented architectures.

Pinouts

Functional Diagram

CD22204E
14 PIN PLASTIC DIP
TOP VIEW

CD22204M
24 PIN SOIC
TOP VIEW

~!

l!':

~

04
08

~

ov

7

LDW 8A'
FILTERS

~~

01

100 kQ

33kn

I
....1-1500pF

IL ______
VSS
_

*

OPTIONAL
HIGH FREQUENCY
NOISE FILTER
(le·3.9kHz)

9ZCS-42801

Digit

08

04

02

01

1
2
3
4
5

0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0

0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0

0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

6

7
8
9
0

Fig. 2 - Analog In.

The C022204E is designed to accept sinusoidal input
waveforms, but will operate satisfactorily with any input
that has the correct fundamental frequency with harmonies
that are at least 20 dB below the fundamental.

*
#

A
B
C
0

CRYSTAL OSCILLATOR
The C022204 contains an on-board inverter with sufficient
gain to provide oscillation when connected to a low-cost
television "color-burst" (3.579545-MHz) crystal :The crystal
oscillator Is enabled by tying XEN high. The crystal is
connected between XI Nand XOUT. A 1-Megohm resistor is
also connected between these pins in this mode. ATB Is a
clock-frequency output. Other C022204 devices may use
the same frequency reference bytying their ATB plnstothe
ATB output of a crystal-connected device. XIN and XEN of
the auxiliary devices must then be tied high and low,
respectively. Up to ten devices may be run from a single
crystal-connected C022204 as shown below.
3.579545MHz

bv
OV signals a detection by going high after a valid tone pair is
sensed and decoded at the output pins 01, 02, 04, 08. OV
remains high until a valid pause occurs.
N/CPIN
This pin has no internal connection and should be left
floating.
OTMF OIALING MATRIX

VDD

ATB

ColO
Col 1
Col 2
Col 3
1209 Hz 1336 Hz 1477 Hz 1633 Hz

6

CD22204

Row 0
697Hz
Row 1
770 Hz
Row2
852 Hz
Row 3
941 Hz

"
x I N CONNECTED TO VDD
10
CD22204

"

6

XEN

UP TO 10 DEVICES
92C$- 39005RI

Fig. 3 - Crystal oscillator.

m m [!J
III m rn
m m iii
I!I rn m

~

[!]
@]
@]

Note:
Column 3 is for special applications and is not normally
used In telephone dialing.

9-32

CD22204
TIMING WAVEFORMS

DIGITAL INPUTS AND OUTPUTS
All digital inputs and outputs of the DTMF receiver are
represented by the schematic below. Only the "analog in"
pin is different, and is described above. Care must be
exercised not to exceed the voltage or current ratings on
these pins as listed in the "maximum ratings" section.
voo

01.02
04,08--+-...J

DV--+--...J

CLRDV--+---+---------.J

DIGITAL
INPUT

*

ED

92CS-42795

• NOTE: EARLY DETECT OUTPUT IS AVAILABLE ONLY ON THE CD22203

92CS·389S6RI

Fig. 4 - Digital inputs and outputs.

Fig. 6 - Timing waveforms.

INPUT FILTER
PARAMETER

The CD22204 will tolerate total input noise of a maximum
of 12 dB below the lowest-amplitude tone. For most
telephone applications, the combination of the
high-frequency attenuation of the telephone line and
internal band-limiting make special circuitry at the input to
these receivers unnecessary. However, noise near the 56
kHz internal sampling frequency will be aliased (folded
back) into the audio spectrum, so if excessive noise is
present above 28 kHz, the simple RC filter shown below may
be used to band-limit the incoming signal. The cut-off
frequency is 3.9 kHz.

NOISY

AN~~OG

270 kn

SIGNA L >--'l.N\v--+-__.--j

0.0015

CD22204

33knL..---...J

~F

I

92CS-42800

Fig. 5 - Filter for use in extreme high frequency input
noise environment.

Noise will also be reduced by placing a grounded trace
around XIN and XOUT pins on the circuit board layout
when using a crystal. It is important to note that XOUT is not
intended to drive an additional device. XIN may be driven
externally; in this case, leave XOUT floating.

9-33

Tone Time:
for detection
for rejection
Pause Time:
for detection
for rejection
Detect Time
Release Time
Data Setup Time
Data Hold Time
DV Clear Time
CLRDV pulse
width
ED Detect Time
ED Release
Time
Output Enable
Time CL=50pF
RL=1KQ
Output Disable
Time CL=35pF
RL=500Q
Output Rise
Time CL=50pF
Output Fall Time
CL=50pF

SYMBOL MIN.
tON
tON

40

tOFF
tOFF
to
tA
tsu
tH
tCL

40

-

25
35
7

4.2

-

TYP. MAX. UNITS

-

20

-

20
46
50

160

5.0
250

-

-

-

ms
ms
ms
ms
ms
ms
JlS
ms
ns

tpw
tED

200
7

-

22

ns
ms

tEA

2

-

18

ms

-

-

200

-

-

150

200

ns

-

-

200

300

ns

-

-

160

250

ns

300

ns

:;;;

o

fd
-'

W
I-

CD22301

mHARRIS

Telecommunications ICs

August 1991

Pinout

Features

CD22301E
18 PIN PLASTIC DIP
TOP VIEW

• Automatic Line Buildout
• Supply Voltage ••••••••.••••••••••••••••••••••• S.lV
• Buffered Output
ALBO GROUND

1

Applications

ALBO 1 OUTPUT

2

ALBO BIAS

• Bipolar Carrier System •••••••••••••• Tl 1.S44Mbits/s

ALBO 2 OUTPUT

3

OSC BIAS

• Ternary Carrier System. • • • • • • • • • •• T148 2.37Mbits/s

4

LC TANK INPUT

5

vee

+

7

TIMING PULSE INPUT

PREAMP OUTPUT·

8

OUTPUT PULSE 1

ALBO 3 OUTPUT
PREAMP INPUT

Description

+

PREAMP INPUT •

The C022301 monolithic PCM repeater circuit is designed
for Tl carrier systems operating with a bipolar pulse train
ofl.544Mbits/s. It can also be used In the T148 carrier sys·
tem operating with a temary pulse train of 2.37Mbits/s. The
circuit operates from a 5.1 V ±5% externally regulated supply.

SUBSTRATE

PREAMP OUTPUT

CLOCK LIMITER OUTPUT

OUTPUT PULSE 2

The C022301 provides active circuitry to perform all func·
tions of signal equalization and amplification, automatic line
buildout (ALBO), threshold detection, clock extraction, pulse
timing and buffered output formation.
The C022301 is supplied in an 18 lead dual-in-line plastic
package (E suffix).

Typical 1.544MHz T1 Repeater System

~'lP
PHASE
SHIFT
NETWORK

3·83K

82K

Vee
FIGURE 1.
CAUTION: These devtces are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

9-34

File Number

1368.1

CD22301
MAXIMUM RATINGS, Absolute Maximum Values:
At ambient temperature (T.) = 25°C
DCSUPPLy .........•...•.•.••.•......•..•........••.•....•••.....•..•..•.•..•..•.•...••••..•••....•.......•..••.••...••.••. 10V
DC CURRENT (Into Pin 9 or 10) .................................•..•.....••........•..•......•...•...•......•...............25 mA
PEAK CURRENT (Into Pin 9 or 10) .........•...........••.....•..•....•...........•..•.•..........•.............•...•...•.. 100 mA
INPUT SURGE VOLTAGE (Between Pins 5 and 6, t = 10 ms) .................................................................... 50 V
OUTPUT SURGE VOLTAGE (Between Pins 10 and 11, t = 1 ms) ................................................................ 50 V
POWER DISSIPATION PER PACKAGE (Po)
ForT. = -40 to +60·C ................................................................................................... 500 mW
ForT. = +60·C to +85·C .................................................................. Derate linearly at 12 mW/·C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
ForT. = Full Package-Temperature Range ............................................................................... 100 mW
OPERATING TEMPERATURE RANGE (T.) .•..••.•..•...•..•...•.•..•................•...•.••.•...••..•.•....•...•..•• -40 to +8S·C
STORAGE TEMPERATURE (T...) .................................................................................... -65 to +150·C
LEAD TEMPERATURE (DURING SOLDERING)
At distance 1116 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max ...................................................... +265·C

ALBO GND

ALBO BIAS

I

17
IK

15K

loon

loon

50K

FROM ALBO

I-~t---+--vv\'-l!--..n@ 1.105 MHz

92CS- 34930

Fig. 7 - Test circuit for threshold voltage measurement.

Fig. 6 - Test circuit for impedance measurement.

9-36

Specifications CD22301
DYNAMIC ELECTRICAL CHARACTERISTICS
TA = 25°C, Vcc = 5.1 V ± 5%
LIMITS
CHARACTERISTIC

UNITS
FIG.

NOTE

MIN.

TYP.

MAX.

Preamplifier Input Imedance

Z'n

8

20

-

-

Preamplifier Output Impedance

Zeut

8

-

-

2

kO

Ao

8

47

50

-

dB

Preamplifier Gain @ 2.37 MHz

kO

AVo"

8

1

-50

0

50

mV

Z'n(CL)

6

2

10

ZALBo(off)

6

3

20

-

kO

ALBa Off Impedance
ALBa On Impedance

ZALBO(on)

6

4

-

-

10

0

VTH(D)

7

5,8

0.62

0.7

0.78

V

CLOCK Threshold Voltage

VTH(CL)

7

6,8

0.92

1.1

1.28

V

ALBa Threshold

VTH(AL)

7

7,8

1.4

1.5

1.6

V

44

47

49

%

Preamplifier Output Offset Voltage
Clock Limiter Input Impedance

DATA Threshold Voltage

VTH(D) as % of VTH(AL)
VTH(CL) as % of VTH(AL)

kO

66

73

80

%

VOL

5

9

0.65

0.8

0.95

V

AVoL

5

9

-0.15

0

0.15

V

t,

5,9

9, 10

-

40

ns

Output Pulse Fall Time

tt

5,9

9,10

-

-

40

ns

Output Pulse Width

tw

5,9

9, 10

290

324

340

ns

Pulse Width Differential

Atw

5,9

9,10

-10

0

10

ns

Clock Drive Current

ICL

-

2

-

mA

Buffer Gate Voltage (low)
Differential Buffer Gate Voltage
Output Pulse Rise Time

Notes:
1. No signal input. Measure voltage between pins 7 and
8.
2. Measure clock limiter input impedance at pin 15.
3. Adjust potentiometer for 0 volts. Measure ALBa off
impedances from pins 2, 3 and 4 to pin 1.
4. Increase potentiometer until voltage at pin 17 = 2 Vdc.
Measure ALBa on impedances from pins 2,3 and 4 to
pin 1.
5. Adjust potentiometer for AV = 0 volts. Then slowly
increase AV in the positive direction until pulses are
observed at the DATA terminal.

~:r.:

",I

6.

Continue increasing AV until the DC level at the clock
terminal drops to 4 volts.
Continue increasing AV until the ALBa terminal rises
to 1 volt.
8. Turn potentiometer in the opposite direction and
measure negative threshold voltages by repeating
tests outlined in notes 5, 6 and 7.
9. Set e'n = 2.75 mV(rms) at f = 1.185 MHz. Adjust
frequency until maximum amplitude Is obtained at pin
15. Observe output pulses at pins 10 and 11.
10. Adjust Input signal amplitude until pulses just appear
in outputs. Increase input amplitude by three dB.
7.

4
5

-l-

kn
~---------+~~

Fig. 8 - Preamplifier gain and Impedance measurement circuit.

9-37

:;;

o

o

w
-'
w

I-

CD22354A
CD22357A

mHARRIS

CMOS Single-Chip,
Full-Feature PCM CODEC

December 1990

Features

Description

• Meets or Exceeds All AT&T 03/04 SpeCifications and
CCITT Recommendations
• Complete COOEC and Filtering Systems: No
External Components for Sample-and-Hold and
Auto-Zero Functions. Receive Output Filter with
SIN XIX Correction and Additional 8kHz Suppression
• Variable Data Clocks - From 64kHz •••••••••• 2.1 MHz
• Receiver Includes Power-Up Click Filter
• TTL or CMOS-Compatible Logic
o ESO Protection on All Inputs and Outputs

The CD22354A and CD22357A are monolithic silicon gate,
double-poly CMOS integrated circuits containing the
band-limiting filters and the companding ND and D/A
conversion circuits that conform to the AT&T D3/D4
specifications and
CCITT recommendations. The
CD22354A provides the AT&T ,,-law and the CD22357A
provides the cCln A-law companding characteristic.

Applications
•
•
•
•
•
•
•
•
•
•
•

PABX
Central Office Switching Systems
Accurate AID and DIA Conversions
Digital Telephones
Cellular Telephone Switching Systems
Voice Scramblers - Oescramblers
T1 Conference Bridges
Voice Storage and Retrieval Systems
Sound Based Security Systems
Computerized Voice Analysis
Mobile.Radio Telephone Systems
o Microwave Telephone Networks
• Fiber-Optic Telephone Networks

Pinouts

The primary applications for the CD22354A and
CD22357A are in telephone systems. These circuits
perform the analog and digital conversions between the
subscriber loop and the PCM highway in a digital switching
system. The functional block diagram is shown below.
With the flexible features, including synchronous and
asynchronous operations and variable data rates, the
CD22354A and CD22357A are ideally suited for PABX,
central office switching system, digital telephones as well
as other applications that require accurate AID and D/A
conversions and minimal conversion time.
The CD22354A and CD22357A are supplied In 16-lead
dual-in-line plastic packages (E suffix).

Functional Block Diagram

TOP VIEW

FULL-FEATURE PCM CODEC
VFX H
VFX1-

G"x

VFX I VFXI+

TS x
FS x
BeLKRI
CLKSEl

BCLKX

t:t:r=;~lADX

MpCD~ ---...
8 _ _ _ _.r-

BCU-~~-_

DR

y+

y.

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1990

9-38

File Number

1682.1

Specifications CD22354A/CD22357A
Absolute Maximum Ratings
DC Supply-Voltage, (V+) .......................... -0.5 to + 7V
DC Supply-Voliage, (V-) ........................... +0.5 to -7V
DC Input Diode Current,
11K (VI < V- -0.5V or VI> V+ +0.5V) ..................... ±20mA
DC Output Diode Current,
10K (VI < V- -0.5VorVO > V+ +0.5V) ................... ±20mA
DC Drain Curren~ Per Output
10 (V- -0.5V < Vo < V+ +0.5V) ......................... ±25mA
DC Supply/Ground Current ............................ ±50mA
Power Dissipation Per Package (Po):
ForTA=-400Cto+600 C .•..•.......•..•.......•.• 500mW
For TA = +600 C to +850 C •..•...•. Derate Linearly @ 8mW/oC
t0300mW

Operating-Temperature Range (TN ............ -400 C to +80 0 C
Storage Temperature (TSTG) ................. -65 0 C to +150 0 C
Lead Temperature (During Soldering):
At Distance 1/16± 1/32 in. (1.59 ± 0.79mm)
from Case for 1Os Max.............................. +265 0 C
Unit Insert into a PC Board (Min. Thickness 1/16 in. 1.59mm)
with Solder Contacting Lead Tips Only ...•..•..•.•..• +300 0 C

Pin Function and Description
PIN NO.

SYMBOL

1

V-

DESCRIPTION

2

GND

Analog and digital ground. All signals referenced to this pin.

3

VFRO

Analog output of RECEIVE FILTER

4

V+

Positive power supply, V+ = +5V ± 5%

5

FSR

Receive Frame Sync Pulse which enables BCLKR to shift PCM data into DR'
FSR is an 8kHz PULSE TRAIN.

S

DR

Receive Data Input. PCM data is shifted into DR following the FSR leading edge.

7

BCLKR/CLKSEL

The Bit Clock, which shifts data into DR after the Frame sync leading edge, may vary from
64kHz to 2.048MHz. Alternatively, the leading edge may be a logic input which selects
either 1.536MHz or 1.544MHz or 2.048MHz for Master Clock in synchronous mode and BCLKX is
used for both transmit and receive directions.

8

MCLKR/PDN

Receive Master Clock. Must be 1.536MHz or 1.544MHz or 2.048MHz. May be asynchronous with
MCLKX but should be synchronous with MCLKX for best performance. When this pin Is continuously
connected low, MCLKX is selected for all internal timing. When this pin is continuously connected high,
the device is power down.

9

MCLKX

Transmit Master Clock. Must be 1.536MHz or 1.544MHz or 2.048MHz. May be asynchronous
with MCLKR.

10

BCLKX

The Bit Clock which shifts out the PCM Data on OX. May vary from 64kHz to 2.048MHz but must be
synchronous with MCLKX.

11

Ox

The TRI-STATE PCM Data Output which is enabled by FSX.

:;;;

12

FSX

Transmit Frame Sync Pulse input which enables BCLKX to shift out the data on OX. FSX is an 8kHz
PULSE TRAIN.

-'

Negative power supply, V- = -5V ± 5%

TSX

Open drain output which pulses low during the encoder time slot.

14

GSX

Transmit gain adjust

15

VFXI-

Inverting input of the transmit input amplifier

16

VFXI+

Non-Inverting input of the transmit input amplifier

13

9-39

oC,)
w

W
I-

CD22354A/CD22357A
Functional Description
Power-Up
When power is first applied, the Power-On reset circuitry
initializes the CODEC and places It In a Power-Down mode.
When the CODEC returns to an active state from the
Power-Down mode, the receive output Is muted briefly to
minimize tum-on "click".
To power up the device, there are two modes available.
1. A logical zero at pin 8 will power up the device, provided
FSX or FSR pulses are present.
2. Alternatively, a clock (MClKR) must be applied to pin 8
and FSX or FSR pulses must be present
•
Power-Down
Two power-down modes are available.
1. A logical 1 at pin 8, after approximately 0.5ms, will power
down the device.
2. Alternatively, hold both FSX and FSR continuously low,
the device will power down approximately 0.5ms after the
last FSX or FSR pulse.
Synchronous Operation
The same master clock and bit-clock should be used for the
receive and transmit sections. MClKX (pIn 9) Is used to
provide the master clock for the transmit section. The
receive section will use the same master clock if the
MClKR/PDN (pin 8) Is grounded (synchronous operation),
or at V+ (power-down mode). Pin 8 may be clocked only if a
clock Is provided at Pin 7 as in asynchronous operation.
The BClKX (pin 10) is used to provide the bit clock to the
transmit section. In synchronous operation, this bit clock is
used for the receive section if MClKR/PDN (pin 8) Is
grounded. BClKR/ClKSEl (pin 7) Is then used to select the
proper internal frequency division for 1.544MHz, 1.536MHz
or 2.048MHz operation. See Table below for 1.544MHz
operation. The device automatically compensates for the
193rd clock pulse each frame.
Each FSX pulse begins the encoding cycle and the PCM
data from the previous encode cycle is shifted out of the
enabled DX output on the leading edge of the BClKX. After
8 bit-clock periods, the tristate DX output is retumed to a
high impedance state. With a FSR pulse PCM data is latched
via the DR input onthe negative edge of the BClKX.
FSX and FSR must be synchronous with MClKX. F~r
1.544MHz
operation,
the
device
automatically
compensates for 193rd clock pulse each frame.
CLOCKING OPTIONS
MASTER CLOCK
FREQUENCY SELECTED
BCLKR/CLKSEL

CD22354A

CD22357A

Clocked

1.536MHzor
1.544MHz

2.048MHz

0

2.048MHz

1.536MHzor
1.544MHz

1(or open clrcuR)

1.536MHzor
1.544MHz

2.048MHz

Asynchronous Operation
For asynchronous operation separate transmit and receive
clocks may be applied.

For CD22357A, the MClKX and MClKR must be 2.048MHz
and for CD22354A must be 1.536MHz or 1.544MHz. These
clocks may not be synchronous. However, for best transmission performance it Is recommended that MClKX and
MClKR should be synchronous.
For 1.544MHz operation the device automatically
compensates for the 193rd clock pulse each frame. FSX
must be synchronous with MClKX and BClKX. FSR must
be synchronous with BClKR. BClKR must be clocked if
MClKR is to be clocked.
Short-Frame Sync Mode
When the power is first applied, the power initialization
circuitry places the CODEC in a short-frame sync mode. In
this mode both frame sync pulses must be 1 bit-clock period
long, with timing relationship shown in Figure 1.
With FSX high during falling edge of the BClKx. the next
rising edge of BClKX enables the DX tristate output buffer,
which will output the sign bit The following rising seven
edges clock out the remaining seven bits, and the next
falling edge disables the DX output.
With FSR high during the falling edge of the BClKR (BClKX
in synchronous mode), the next falling edge latches In the
sign bit. The following seven edges latch In the seven
remaining bits.
Long-Frame Sync Mode
In this. mode of operation, both the frame sync pulses must
be three or more bit-clock periods long with timing
relationship shown in Figure 2.
Based on the transmit frame sync FSX, the CODEC will
sense whether short-or long-frame sync pulses are being
used.
For 64kHz operation the frame sync pulse must be kept low
for a minimum of 160ns.
The DX tristate output buffer is enabled with the rising edge
of FSX or the rising edge of the BClKX, whichever comes
later and the first bit clocked out Is the sign bit The following
seven rising edges of the BClKX clock out the remaining
seven bits. The
output Is disabled by the next falling edge
of the BClKX following the 8th rising edge or by FSR going
low whichever comes later.
A rising edge on the receive frame sync, FSR, will cause the
PCM data at DR to be latched in on the next falling edge of
the BClKR. The remaining seven bits are latched on the
successive seven falling edges of the bit-clock (BClKX In
synchronous mode).
Transmit Section
The transmit section consists of a galn-ad]ustable Input
op-amp, an anti-aliasing filter, a low-pass filter, a high-pass
filter and a compressing ND converter. The input op-amp
drives a RC active anti-aliasing filter. this filter eliminates the
need for any off-chip filtering as it provides 3D-dB
attenuation (minimum) at the sampling frequency. From this
filter the signal enters a 5th order low-pass filter clocked at
128kHz, followed by a 3rd order high-pass filter clock at
32kHz. The output of the high-pass filter directly drives the
encoder capacitor ladder at an 8kHz sampling rate. A
precision voltage reference Is trimmed In manufacturing to
provide an input overload of nominally 2.5-V peak. Transmit
frame sync pulse FSX controls the process. The 8-blt PCM
data Is clocked out at DX by the BClKX.
BClKX can be varied from 64kHz to 2.1 MHz.

9-40

Ox

CD22354A/CD22357A
Receive Section
The receive section consists of an expanding D/A converter
and a low-pass filter which fulfills both the AT&T D3/D4
specifications and CCITI recommendations. PCM data
enters the receive section at DR upon the occurrence of
FSR, Receive Frame sync pulse. BClKR. Receive Data
Clock, shich can range from 64kHz to 2.1 MHz, clocks the
8-bit PCM data into the receive data register. AD/A
conversion is performed on the 8-bit PCM data and the

corresponding analog signal is held on the D/A capacitor
ladder. This signal Is transferred to a switched capacitor
low-pass filter clock at 128kHz to smooth the sample-and
hold signal as well as to compensate for the SIN X/X
distortion.
The filter is then followed by a second order Sallen and Key
active filter capable of driving a 600-0 load to a level 7.2
dBm.

MeLK R
MCLK X

BCLK X

BClK R

FIGURE 1. SHORT FRAME-SYNC TIMING

MCLKR
MCLK X

::;;:

o
ow

BCLK X

-'
w

I-

BeLK R

DR

FIGURE 2. LONG FRAME-SYNC TIMING

9-41

Specifications CD22354A/CD22357A
Static Electrical Characteristics

At TA = 25 0 C
LIMITS

CHARACTERISTIC

TEST CONDITIONS

MIN.

TYP

MAX.

UNITS

Positive Power Supply

V+

4.75

5

5.25

V

Negative Power Supply

V-

-4.75

-5

-5.25

V

Power Dissipation (Operating)

POPR

V+=5V

75

90

mW

Power Dissipation (Standby)

PSTBY

V-=-5V

-

9

15

mW

Static Electrical Characteristics At TA = OOC to 700 C; V+ = 5V, V- = -5V ±5%
LIMITS
CHARACTERISTIC

MIN.

TYP.

MAX.

UNITS

10

-

-

5

-

MO

All Logic and Analog Inputs
VI=OVorV+

-10

-

10

pA

VIL

IIL=±10pAmax.

-

-

0.8

V

High Level Input Voltage

VIH

IIH = ±10~Amax.

2

-

-

V

Low Level Output Voltage

'VOL

IOL=3.2mA

-

0.4

V

High Level Output Voltage

VOH

IOH=1.0mA

2.4

-

-

V

Analog Input Resistance

RINA

Input Capacitance

CIN

Input Leakage Current, Digital

II

Low Level Input Voltage

Open State Output Current

IOZ

Input Leakage Current, Analog

II

GND 10K, CL < 50pF

-0.15

-40 to -50dBmO
-50 to -55dBmO
Transmit Input Amplifier Gain,
Open Loop

AOL

Transmit Input Amplifier Gain,

ACL

Unity
Transmit Gain, Absolute

GXA

Receive Gain, Absolute

GRA

-

-

+3to-40dBmO

RL~

RL~

1MOatGSX

6000, CL:s. 500pF

-0.15

-

±0.4

dB

±1.2

dB

±0.2

dB

±0.4

dB

±1.2

dB

-

dB

0.01

dB

0.15

dB

0.15

dB

Noise Characteristics
LIMITS
TEST CONDITIONS

MIN.

TYP.

MAX.

UNITS

NX

VFXI-=GND

-

12

15

dBrncO

-74

-67

dBmOp

NR

PCM Code Equivalent

-

7

11

dBrncO

-83

-79

dBmOp

VFXI+=OV
V+ = 5V + (1 OOmV RMS)
f=Ot050kHz

40

-

-

dBc

VFXI-=OV
V- = -5V + (1 OOmV RMS)
f=Ot050kHz

40

-

-

dBc

-

-

dBc

CHARACTERISTIC
Transmit Noise

VFXI+=GND
Receive Noise

to Zero Volts
V+ Power Supply Rejection
Transmit

PSRR

V- Power Supply Rejection
Transmit

PSRR

V+ Power Supply Rejection
Receive

PSRR

V- Power Supply Rejection
Receive

PSRR

PCM Code = All 1 Code
V+ = 5V + (1 OOmV RMS)
f=Ot04kHz

40

=4to25kHz

40

= 25 to 50kHz

36

PCM Code = All 1 Code
V- = -5V + (1 OOmV RMS)
f=Ot04kHz

40

=4to25kHz

40

-

-

=25to50kHz

36

-

-

-

-80

-70

dB

-76

-70

dB

Cross Talk Transmit to Receive

CTXR

VFXI- = OdBmO @ 1020Hz

Cross Talk Receive to Transmit

CTRX

DR = OdBmO @ 1020Hz,
VFXI-=OV

9-44

-

dB
dB

dBc
dB
dB

Specifications CD22354A/CD22357A
Timing Specifications
LIMITS
CHARACTERISTIC
Frequency of Master Clocks

TEST CONDITIONS

MIN.

TYP.

l/tpM

Depends on the'Device Used
and the BCLKR/CLKSEL Pin
MCLKX and MCLKR

-

1.536
1.544
2.048

MAX.

-

UNITS
MHz
MHz
MHz

-

-

50

MCLKX and MCLKR

-

-

50

ns

First Bit Clock after the
Leading Edge of FSX

100

-

-

ns

Width of Master Clock High

tWMH

MCLKX and MCLKR

160

Width of Master Clock Low

twML

MCLKX and MCLKR

160

Rise TIme of Master Clock

tRM

MCLKX and MCLKR

Fall Time of Master Clock

tFM'

Set-up TIme from BCLKX High
(and FSX In Long Frame Sync
Mode) to MCLKX Falling Edge

tSBFM

Period of Bit Clock

ns
ns
ns

tpB

485

488

15,725

ns

Width of Bit Clock High

tWBH

V'H=2.2V

160

-

ns

Width of Bit Clock Low

tWBL

V'L=0.6V

160

-

-

ns

Rise Time of Bit Clock

tRB

tpB=488ns

-

-

50

ns

Fall Time of Bit Clock

tFB

tpB=488ns

-

50

ns

Holding TIme from Bit Clock
Low to Frame Sync

tHBF

Long Frame Only

0

-

-

ns

Holding Time from Bit Clock
High to Frame Sync

tHOLD

Short Frame Only

0

-

-

ns

Set-up Time from Frame Sync
to Bit Clock Low

tSFB

Long Frame Only

80

-

-

ns

DelayTimefrom BCLKX High

tDBD

Load = 150pF plus 2
LSTILLoads

0

-

180

ns

Delay Time to TSX Low

tXDP

Load = 150pF plus 2
LSTILLoads

-

-

140

ns

Delay Time from BCLKXLowto
Data Output Disabled

tDZC

50

-

165

ns

Delay Time to Valid Data from
FSX or BCLKX, Whichever
Comes Later

tDZF

20

-

165

ns

Set-up TIme from DR Valid to
BCLKR/XLow

tSDB

50

-

-

ns

Hold Time from BCLKR/X Low to
DR Invalid

tHBD

50

-

-

ns

Set-up Time from FSX/R to
BCLKx/RLow

tSF

Short Frame Sync Pulse (lor 2
Bit Clock PerIods Long) (Note 1)

50

-

-

ns

Hold TIme from BCLKX/R Low

tHF

Short Frame Sync Pulse (lor 2
Bit Clock Periods Long) (Note 1)

100

-

-

ns

Hold Time from 3rd PerIod of
Bit Clock Low to Frame Sync
(FSxorFSR)

tHBFJ

Long Frame Sync Pulse (from 3
to 8 Bit Clock Periods Long)

100

-

-

ns

Minimum Width of the Frame
Sync Pulse (Low Level)

tWFL

64K Bits Operating Mode

160

-

-

ns

to Data Valid

to FSX/R Low

CL = OpFto 150pF

NOTE: 1. For short frame sync liming, FSX and FSR must go high while their respective bR clocks are high.

9-45

.,

o
==

o

w
....
w

I-

CD22M3493

mHARRIS

12 x 8 x 1 BiMOS-E
Crosspoint Switch

August 1991

Features

Description

• 96 Analog Switches

The Harris CD22M3493 is an array of 96 analog switches
capable of handling signals from DC to. video. Because ef
the switch structure, input signals may swing threugh the
tetal supply veltage range, VDD to. VSS. Each ef the 96
switches may be addressed via the ADDRESS input to. the 7
to 96 line decoder. The state ef the addressed switch is
established by the signal to. the DATA input. A lew er zero.
input will epen the switch, while a high legic leveler a ene
will result In clesure ef the addressed switch when the
STROBE Input gees high from Its nermally lew state. Any
number er cembinatien ef cennectiens may be active at ene
time. Each cennectien, hewever, must be made er breken
Individually in the manner previeusly described. All switches
may be reset by taking the RESET input from a zero. state to. a
ene state and then retuming it to. its nermal lew state.

• Low RON
• Guaranteed RON Matching
• Analog Signal Input Voltage Equal To The Supply
Voltage
• Wide Operating Voltage: 4V To 16V
• Parallel Input Addressing
• High Latch Up Current: SOmA Minimum
• Very Low Crosstalk
• Pin And Functionally Compatible With The Following
Types: SGS M3493, SGS M093, SSI 78A093A, and
Mitel MT8812

Applications
• PBX Systems
• Instrumentation
o Analog And Digital Multiplexers
• Video Switching Networks

The CD22M3493 is effered beth In Plastic DIP ('E' suffix)
and In PLCC ('0' suffix). The device is eperatienal ever the
entire Industrial temperature range (-40 eC to. +85e C) in
beth packages.

Pinouts
CD22M3493E (PLASTIC DIP)
TOP VIEW

CD22M3493Q (PLCC)
TOP VIEW

Iii
!zl ~ ~ ~ ~

Y3

0(

c
c ~ !;(
C ;:: ~

~ >

RESET
AX3

NC

NC

NC

X6

xo

NC

X7

Xl

X6

X6

X2

X7

X9

X3

Xl0

X4

AXO

NC

X5

NC

NC
NC

NC
NC

s:

~

~
Ii;

~

r.n ;!:
~

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

9-46

0
~ ~ ~ ~ z

File Number

2491.1

CD22M3493
Block Diagram
STROBE

DATA

RESET

AXO
AXl
AX2
AX3
AYO
AYl
AY2

96

l2X8
SWITCH
ARRAY

xo-

Xll

Pin Descriptions

SYMBOL

40 PIN
PLASTIC DIP

44 PIN
PLCC

DESCRIPTION

POWER SUPPLIES
VDD

40

44

Positive Supply

VSS

20

22

Negative Supply

AXO-AX3

5,22,23,
&4

5,24,25,
&4

X Address Lines. These pins select one of the 12 rows of switches. See the
Truth Table for the valid addresses.

AYO-AY2

24,25,
&2

26,27,
&2

Y Address Lines. These pins select one of the 8 columns of switches. See
the Truth Table for the valid addresses.

DATA

38

42

DATA Input determines the state of the addressed switch. A high or one will close the
switch. A low or zero will open the switch.

STROBE

18

20

STROBE Input enables the action defined by the DATA and ADDRESS Inputs. A low or
zero results in no action. The ADDRESS Input must be stable before the STROBE Input
goes to the active high level. The DATA Input must be stable on the failing edge of the
STROBE.

RESET

3

3

MASTER RESET. A high or one on this line opens all switches.

ADDRESS

CONTROL

::;;

INPUTS/OUTPUTS

o(,)

XO-X5
I/O
X6-Xll

33-28
8-13

9-14

YO-Y7
I/O

35,37,39,
1,21,19,
17& 15

40,41,43,
1,23,21,
19& 18

37-32

Analog or Digital Inputs/Outputs. These pins are the rows XO - X11.

w

-'
w

I-

Analog or Digital Inputs/Outputs. These pins are the columns YO - Y7.

9-47

Specifications CD22M3493
Absolute Maximum Ratings
DC Supply Voltage (Voo):
(Voltages Referenced to Vss) •••.•••••••.••.•••••• -0.5to+17V
DC Input Diode Current, liN •••••••••••••••••••••••••••• ±2omA
(For VI < VSS -0.5V or VI > VOO +0.5V)
OC Output Olode Current, 10K ••.••••••••••••••••••••.• ±20mA
(For Vo < VSS -0.5V or Vo > VOO +0.5V)
DC Transmission Gate Current .••••••••••.•••.••••••..• :l:25mA
Power Oissipation Per Package (Po):
For TA = -40 to +85 0 C •••••••••.•••••••••••.••••••••• 500mW
(Package Type E, 40 Pin Plastic DIP)
ForTA = -40 to +850 C •••••••••••••••••••.••••••••••• 600mW
(Package Type Q, 44 Pin PLCC)

Operating Temperature Range (TA):
Package Type E and Q •••••.• , .••••.•.•••••••••••• -40 to 850 C
Storage Temperature Range (TSTG) ••.•••.••••.•• -85 to 1500 C
Lead Temperature (During Soldering) For 10 sec max:
Ata distance 1/16 ± 1/32In.(1.59:1: 0.79mm) ••••••••••• +2650 C
From case for 10 sec max
'Printed-circuit board mount 57mm x 57mm minimum area x
1.6mm thick GIO epoxy glass or equivalent

Recommended Operating Conditions
For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges:
LIMITS
CHARACTERISTIC
Supply Voltage Range (ForTA = Full Package Temperature Range) VSS=OV
VOO
DC Input or Output Voltage VI or Vo
Digital Input Voltage

MIN

MAX

UNITS

4

16

V

Vss
Vss

VOO
VOO

V
V

Dynamic Electrical Characteristics (TA = -400 C to 850 C) Vss = OV, Voo = 14V, Unless Otherwise Specified
CHARACTERISTIC

CONTROLS CONDITIONS

MIN

TYP

MAX

UNITS

Voo=5V

Logic Inputs = VOO

-

mA

Logic Inputs = VOO

-

-

2

VOO=16V

5

mA

High-Level Input
Voltage, VIH

2A

-

-

V

Low-Level Input
Voltage, VIL

-

-

0.8

V

Input Leakage Current,
liN

-

-

:1:10'

JlA

Supply Current, 100

CHARACTERISTIC

MIN

TYP

MAX

UNITS

VOO=5V

-

40

70

n

ON Resistance
RON

TA=250 C,
VIN=Vool2
VX - VY = 0.25V

CROSSPOINTS CONOITIONS

VOO=14V

-

22

45

VOO=5V

80

n
n

VOO=14V

-

-

ON Resistance
RON

TA = -400 C to 850 C
VIN=Vool2
VX - VY = 0.25V

-

55

n

VOO=14V

-

4

10

n

VOO=14V

-

-

10

n

-

-

:1:10'

JlA

Difference In ON
Resistance between
any two switches,
A. RON

TA=250 C,
VIN=VOO/2
VX - VY = 0.25V

Oifference in ON
Resistance between
any two switches,
A. RON

TA = -400 C to 850 C
VIN=VOO/2
VX - VY = 0.25V

OFF Leakage Current,
IL

Ivx-vyl=14V

9-48

CD22M3494
Dynamic Electrical Characteristics (Continued)
(TA = +250 C), VSS = OV, VEE = OV, VDD = 14V, CL = 50pF, Unless Otherwise Specified
CHARACTERISTIC

CROSSPOINTS CONDITIONS

Switch I/O Capacitance

VIN = VDD/2, I = 1 MHz

Switch Feedthrough Capacitance

VIN = VDD/2, I = 1 MHz

Propagation DelayTime (switch ON)
Signal Input to Output
tpHLortpLH

MIN

TYP

MAX

UNITS

-

-

20

pF

0.3

-

pF

-

30

100

na

Frequency Response Channel ON
1= 20109 ryxNY) = -3dB

CL = 3pF, RL = 750, VIN = 2VP-P

-

50

-

MHz

Total Harmonic
THO

VIN = 2VP-P, 1= 1kHz

-

0.D1

-

%

Feedthrough Channel OFF
Feedthrough =
2010g ryXNY) = FDT

VIN = 2VP-P, 1= 1 kHz

-

-95

-

dB

Frequency lor Signal Crosstalk,lCT

40dB, VIN = 2VP-P, RL = 750

-

10

-

MHz

5

-

kHz

-

75

-

mVPK

MIN

TYP

MAX

UNITS

-

5

-

pF

Attenuation of:

110dB,VIN=2VP-P,RL=1kIl10pF

Control Crosstalk
DATA-Input, ADDRESS,
or STROBE to Output

Control Input = 3VP-P
Square Wave, tr = If = 10ns
RIN = 1K,ROUT= 10K 1110pF

Dynamic Electrical Characteristics
(TA = +250 C), VSS = OV, VEE = OV, VDD = 14V, RL = 1 K 1150pF, Unlesa Otherwise Specilied
CHARACTERISTIC

CONTROLS CONDITIONS

Digital Input Capacitance

CIN

Propagation DelayTime
STROBE to Output
(Switch turn-ON)
(Switch turn-OFF)

tpSN
tPSF

-

50
50

100
100

na
na

DATA-in to Output
(Turn-ON to high level)
(Turn-ON to low level)

tpZH
tpZL

-

-

60
70

100
100

ns
ns

ADDRESS 10 Output
(Tum-ON to high level)
(Turn-OFF to low level)

tpAN
tpAF

-

70
70

-

ns
ns

Set-upTime
CS 10 STROBE
DATA-in to STROBE
ADDRESS 10 STROBE

tcs
tDS
tAS

10
10
10

-

-

ns
ns
ns

tCH

10
10
20
10

-

-

Hold Time
STROBE to CS
ADDRESS to CS
STROBE to DATA-in
STROBE to ADDRESS
DATA-lntoCS

VIN = 5V, 1= 1 MHz

tDH
tAH

PulseWidlh
STROBE
RESET

\sPW
tRPW

RESETTurn OFFlo
Output Delay

tpHZ

9-49

-

-

ns
ns

20

-

20
20

-

-

ns
ns

-

70

100

ns

-

-

CD22M3493
Timing Diagram

\V 50%

ADDRESS

\1/50%

JI\ .

STROBE

1\

tAS _ t s p w _ tAH

1

\1--

r

f
50%

DATA

tDS

l"-

tpSN--tpSF ---tDH

I"-

\/50%

\ / 50%

1\

1\
I--tRPW--

RESET

_

--

tPAF·

lpZL

•

_lpZH

tpAN

TRUTH TABLE X AXIS

-K
--

~tpHZ

K

10%

TRUTH TABLE V AXIS

AX3

AX2

AX1

AXO

0

0

0

0
0
0
0

0
0
0
1
1
1

0
1
1
0

0
1
0
1

1
.0
0
0

1
0
0
1

0
1
1
1
1

1

0
1

0
0
1
1

0
1
0
1

1
1
1
1
1
1
1

_
90%

X ADDRESS

0
0
0
1

1\50%

9O'l&

SWITCH
OUTPUT

--

\

V 50%

1

0
1

V ADDRESS
SEE·
NOTE

0
1
0
1
0
1

(1)
(1)

(1)
(1)

SEE
NOTE

X SWITCH

AV2

AV1

AVO

XO
XI
X2
X3
X4
X5
No Connect

0

0

0
0
0

0
1
1

0
1

1
1

0
0

0

1
1

1

0

Y5
Y6

1

1

Y7

No Connect
X6
X7

NOTE: (1)

V SWITCH
YO
VI
Y2
Y3
Y4

0
1
1

When X switch addresses are in these states. no change in

status will occur in switches between any X and Y points.

X8
X9
Xl0
XII
No Connect
No Connect

To make a connection (close switch) between any two points, specify an "X" address, a "Y" address, set "Data" high, and
switch "Strobe" from low to high to break a connection, follow this same procedure with "Data" low.
Example:

X ADDRESS

To connect switch X3 to switch Y4:
To connect switch X6 to switch Y7:
To break connection from X3 to Y4:

9~50

YADDRESS

DATA

AX3

AX2

AX1

AXO

AV2

AVI

AVO

1
1
0

0
1
0

0
0
0

1

1

0
1

0
1

1
1
1

0
1
0

0
1
0

CD22M3494

mHARRIS

16 x 8 x 1 BiMOS-E
Crosspoint Switch

August 1991

Features

Description

• 128 Analog Switches

The Harris CD22M3494 is an array of 128 analog switches
capable of handling signals from DC to video. Because of
the switch structure, input signals may swing through the
total supply voltage range, VDD to VSS. Each of the 128
switches may be addressed via the ADD RESS input to the 7
to 128 line decoder. The state of the addressed switch is
established by the signal to the DATA input. A low or zero
Input will open the switch, while a high logic level or a one
will result In closure of the addressed switch when the
STROBE input goes high from its normally low state. Any
number or combination of connections may be active at one
time. Each connection, however, must be made or broken
Individually in the manner previously described. All switches
may be reset by taking the RESET input from a zero state to a
one state and then retuming it to its normal low state.

• Low RON
• Guaranteed RON Matching
• Analog Signal Input Voltage Equal to the Supply
Voltage
• Wide Operating Voltage: 4V to 14V
• Parallel Input Addressing
• High Latch Up Current: SOmA Minimum
• Very Low Crosstalk
• Pin And Functionally Compatible with the Following
Types: SGS M3494 and Mitel MT8816

CS allows crosspoint array to be cascaded for matrix
expansion.

Applications

The CD22M3494 Is offered both in Plastic DIP ('E' suffix)
and in PLCC ('Q' suffix). The device is operational over the
entire Industrial temperature range (-40 0 C to +850 C) In
both packages.

• PBX Systems
• Instrumentation
• Analog And Digital Multiplexers
• Video Switching Networks

Pinouts
CD22M3494E
(PLASTIC DIP)
TOP VIEW

CD22M3494MQ (PLCC)
(MITEL PIN COMPATIBLE)
TOP VIEW

~~~i~~~~~

CD22M3494SQ (PLCC)
(SGS PIN COMPATIBLE)
TOP VIEW

>B

0

z

0

~ ~

~

of

<

~

!c0

>

jl

::;;;
0
NC·

NCO

0

W

--'
Xl

Xl
X2

X3

X3

X5

Xl.

Xl.

I:

~

::l

0

a:

~

"'"'

>

;!

0
~ ~ ~ ~ z

Ii;

CAUTIONI: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be follll'lYe VOO +0.5V)
DC Output Diode Current, 10K •••••••••••••••••••.••••• :l:20mA
(For Vo < VSS -o.5V or Vo > VOO +0.5V)
DC Transmission Gate Current ••••••••••.••••.••••••••• :l:25mA
Power Dissipation Per Package (Po):
ForTA=-40to+60oC ••••••••••••.••••.••••••••••••• 500mW
(Package Type E, 40 Pin Plastic DIP)
ForTA = +600 C to + 850 C Derate Lineary •• 12mWjOC to 200mW

Recommended Operating

ForTA = -40 to +850 C ••••••.•••••••••••.•••••••••••• 600mW
(Package Type Q, 44 Pin PLCC)
Operating Temperature Range (TA):
Package Type E and Q •••••••••••••••••••••••••••• -40 to 850 C
Storage Temperature Range (TSTG) •••••••••••••. -65 to 1500 C
Lead Temperature (During Soldering) For 10 sec max:
At a distance 1/16:1: 1/32 in. (1.59:1: 0.79mm) ••••••••.•• +2650C
From case for 10 sec max
·Printed-circuit board mount 57mm x 57mm minimum area x
1.6mm thick GIO epoxy glass or equivalent.

Condltlons~

For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges:
LIMITS
CHARACTERISTIC
Supply Voltage Range (ForTA = Full Package Temperature Range) VSS=OV,
VEE=OV,VOO
DC Input or Output Voltage VI or Vo
Digital Input Voltage

MIN

MAX

UNITS

4

14

V

VEE
Vss

VOO
VOO

V
V

Dynamic Electrical Characteristics (TA = -4ooC to +850 C) VSS = VEE = OV, Unless Otherwise Specified
CHARACTERISTIC925

MIN

TYP

MAX

VOO=5V

Logic Inputs = VOO

-

2

rnA

VOO= 16V

Logic Inputs = VOO

-

-

5

rnA

High-Level Input
Voltage, VIH

2.4

-

-

V

Low-Level Input
Voltage, VIL

-

-

O.B

V

Input Leakage Current,
liN

-

-

:1:10·

I1A

MIN

TYP

MAX

UNITS

-

40

75

n

38

65

50

90

n
n

45

80

n

Supply Current,loO

CHARACTERISTIC

CONTROLS CONDITIONS

CROSSPOINTS CONDITIONS

ON Resistance
RON

VSS= VEE = OV
TA=+250C,
VIN=VOO/2
VX-VY= 0.2V

ON Resistance
RON

TA = -400 C to +850C
VIN=VOO/2
VX-VY=0.2V
VSS=VEE=OV

VOO=10V

VOO=12V

-

VOD = 12V
VOO=10V

UNITS

Difference In ON
Resistance between
any two switches,
ARON

TA=+250 C,
VIN=Vool2
VX-VY= 0.2V
VSS=VEE=OV

VOO= 12V

-

6

10

n

Difference in ON
Resistance betwsen
any two switches.
ARON

TA = -400C to +850 C
VIN=VOO/2
VX-VY=0.2V
VSSorVOO=OV

VOO=12V

-

-

10

n

Input Leakage Current,lL
(Digital Pins)

VIN (Digital) = Vss orVOO,
TA = -40°C to +850C

-

-

:1:100
:1:3

nA
rnA

TA=+250C

·At +250 C UmR is ±l00nA

9-53

Specifications CD22M3494
Dynamic Electrical Characteristics (Continued)
(TA = +2SOC), vSS = OV, vEE = OV, VOO = 14V, CL = 50pF, Unless Otherwise Specilled
CHARACTERISTIC

CROSSPOINTS CONDITIONS

Switch I/O Capacitance

VIN = V0012, I = 1 MHz

Switch Feedthrough Capacllance

VIN = V0012, I = 1 MHz

Propagation Delay Time (switch ON)
Signalinputto Output
tpHLor tpLH

MIN

TYP

MAX

UNITS

-

-

20

pF

0.3

-

pF

-

30

100

ns

Frequency Response Channel ON
1= 20109 ryxNY) = -3dB

CL = 3pF, RL = 750, VIN = 2VP-P

-

50

-

MHz

Total Harmonic
THO

VIN = 2VP-P, 1= 1kHz

-

0,01

-

%

Feedthrough Channel OFF
Feedthrough =
20109 ryxNY) = FOT

VIN = 2VP-P, I = 1kHz

-

-95

-

dB

Frequency lor Signal Crosstalk,ICT

40dB, VIN = 2VP-P, RL = 750

Attenuation of:

1.1 OdB, VIN = 2VP-P, RL = 1 k 1110pF

Control Crosstalk
DATA-Input, ADDRESS,
or STROBE to Output

Control Input = 3VP-P
Square Wave, tr = If = 10ns
RIN = 1K, ROUT = 10K 1110pF

-

10
5

-

MHz
kHz

75

-

mVPK

MIN

TYP

MAX

UNITS

-

5

-

pF

-

Dynamic Electrical Characteristics
(TA = +250 C), VSS = OV, VEE = OV, VOD = 14V, RL = 1 K 1150pF, Unless Otherwise Specified
CHARACTERISTIC

CONTROLS CONDITIONS

Digital Input Capacitance

CIN

Propagation Delay Time
STROBE to Output
(Switch tum-ON)
(Switch turn-OFF)

tpSN
tpSF

-

50
50

100
100

ns
ns

DATA-In to Output
(Tum-ON to high level)
(Tum-ON to low level)

tpZH
tpZL

-

60
70

100
100

ns
ns

ADDRESS to Output
(Tum-ON to high level)
(Tum-OFF to low level)

tpAN
tpAF

-

70
70

-

-

ns
ns

Set-upTime
CS to STROBE
DATA-In to STROBE
ADDRESS to STROBE

tcs
tDS
tAS

10
10
10

-

ns
ns
ns

tCH

10
10
20
10

Hold Time
STROBEtoCS
ADDRESS to CS
STROBE to DATA-In
STROBE to ADDRESS
DATA-In to CS

VIN =5V,I= 1MHz

tOH
tAH

-

-

-

-

-

20

ns
ns

-

Pulse Width
STROBE
RESET

tspw
tRPW

20
20

-

-

-

ns
ns

RESETTum OFF to
Output Delay

tpHZ

-

70

100

ns

9-54

Specifications CD22M3494
Timing Diagram
50'1&

-

e---

'CSCS

JI

1

e---

1\

:-

_Y5O'l&

~

I t\ 50'1&

-

50'1&

I--'ws-

'AS-

ADDRESS

'CH

'AS

11\

f-- 'SPW1L5O'I&

STROBE

-V

DATA

'AH

C- 1\
'os t:=-

1\

f-'PSN'PSF-

I--'DH-

f---..

\V 50'1&

50'1&

1\

~."~~
1/50'1&

RESET

-

-

tpAF

-'PZL

I---'PHZ-

9O'If>

9O'If>

~K

SWITCH
OUTPUT

-

~K

10'l1>

-

-'PZH
'PAN

TRUTH TABLE X AXIS

TRUTH TABLE V AXIS
X ADDRESS

AX3

AX2

AX1

AXO

0

0

0

0

0

0
0
0
0

0
0

0
1
1
0
0
1
1
0
0
1
1

0

,

0

1
1

,
,
,
1

0
0

1
1

0
0
1

1
1

1
1

,

,

50'1&

0
0
1
1

V ADDRESS
SEE
NOTE

X SWITCH

AV2

AV1

AVO

SEE
NOTE

V SWITCH

0

,

XO

x,

0
0

0
0

0
1

VO
Vl

0
1
0
1

X2
X3
X4
X5
X12
X13
X6
X7
X8
X9

1
1
0
0
1
1

0
1
0
1

0
1
0
1
0
1

0
0
1
1
1
1

Y2
Y3
Y4
Y5
V6

0
1
0
1

X10
(1)
(1)

0
1

:::;;;

o

Y7

frl
.....I
W

t-

X1'
X14
X15

To,make a connection (close switch) between any two points, specify an "X" address, a "Y" address, set "Data" high, and
switch "Strobe" from low to high to"break a connection, follow this same procedure with "Data" low.
Example:

V ADDRESS

X ADDRESS
DATA

AX3

AX2

AX'

AXO

AV2

AV1

AVO

1
1
0

0
1
0

0
0
0

1
0
1

1
0
1

1
1
1

0
1
0

0
1
0

To connect switch X3 to switch Y4:
To connect switch X6 to switch Y7:
To break connection from X3 to Y4:

9-55

CD22M3494

Voltage and Resistance
RON vs. VIN
-SSoC, +2So C and +8So C
VEE = -SV, VSS = OV, VOO = SV
@

70

r
II'
,
-~

60

C;
w

50

+85o C

U

40

~
f3a:

30

z

z

0

/

I
I

+ 250 C

""'100.

",,-

........

i-"""'"

--

I

I
-55 0 C

20

It.

ioo""'"

~

V

100"

10
0

-8

-6

-4

-2
V,N

9-56

0

+2

(VOLTS)

+4

+6

+8

CD22859

mHARRIS

Monolithic Silicon
COS/MaS Dual-Tone Multifrequency Tone Generator

August 1991

Features

Description

• Mute Drivers On-Chip

The CD22859 is a CMOS dual-tone multifrequency (DTMF)
tone generator for use in dual-tone telephone dialing systems. The device can easily be Interfaced to a standard
pushbutton telephone keyboard, to provide enabling operation directly with the telephone lines.

• Device Power can Either be Regulated DC or
Telephone Loop Current
• Use of an Inexpensive 3.579545MHz TV Crystal
Provides High Accuracy and Stability for all
Frequencies

Applications
• For Use In Dual-tone Telephone Dialing Systems

Pinout
CD22859 TYPES
16 PIN CERAMIC SIDEBRAZED
16 PIN PLASTIC DIP
TOP VIEW

VOUT
TX

CD

C1

R1

C2

R2

C3

R3

Vss

R4

OSC1

RX

OSC2

C4

CAUTION: These devices are sensitive to electrostatic discharge. Proper
Copyright @ Harris Corporation 199'

The CD22859 generates standard DTMF sinuslodal dialing
tones from an on-chip reference crystal oscillator. The reference oscillator uses an inexpensive 3.579545MHz color
TV crystal to create highly stable and accurate tones. The
sinusiidal tones are digitally synthesized by a stair-step approximation.
One of four low-frequency band row tones and one of four
high-frequency band column tones are selected by driving
one of the four row inputs and one of the four column inputs
low. Simultaneous selection of more than one row input
and/or more than one column input will inhibit tone generation, or generate a single-tone sinusoid. These operating
modes are described in the functional truth table.
Control logic is included to allow easy interface to standard
K500-types telephones. Two CMOS outputs Tx, Rx capable of driving external p-n-p receiver and transmitter muting transistors are provided. A low input to the CD pin, inhibits tone generation, turns off the reference oscillator and
causes Tx and Rx outputs to logic '0'. During tone generation mode, CD = 1 and Tx, Rx = logic 1.
All row, column and CD inputs are provided with pull-up resistors to allow the use of SPST switch matrixes.
The CD22859 types are supplied in a 16 lead hermetic
dual-in-Iine sidebrazed ceramic package (D suffix) and a
16 lead dual-in-Iine plastic package (E suffix).

I.e. handling procedures should
9-57

be followed.

File Number

1257_1

Specifications CD22859
Absolute MaxImum Ratings
DC Supply Voltage Range (VDD - VSS) •••...••..•• -0.5V to +12V
Input Voltage Range ••..•.••••.•.•••••••••• -0.5V to VDD +0.5V
Power Dissipation, Po:
TA = -400 C to +600 C .•••••••••••...••.•.••••••.•••• 500mW
TA = +600 C to +85 0 C •. Derate Linearly at 1.2mWfOC to 200mW

Power Dissipation Per Output. • • . • • • • . . • • . . • . • • • • • . • .• 100mW
Operating Temperature Range ••.•.••.••••.••• -40 0 C to +85 0 C
Lead Temperature During Soldering: Distance 1/16 in. :!: 1/32 in.
(1.59mm :!: 0.79mm) from case for lOs max •...•.•••••• +2650 C

Dynamic Electrical CharacteristIcs TA = -250 C to +60 0 C All Voltages Referenced to VSS = OV
LIMITS
MIN

MAX

UNITS

Tone Gneration Mode with Valid Input (Note 1)

2.5

10

V

Non-Tone Generation (Note 2)

1.7

10

V

-

2.7

rnA

13

rnA

100

pA

CHARACTERISTICS

Voo

DC SUPPLY VOLTAGE

OPERATING CURRENT
Tone Generation Mode
Outputs Unloaded)

3.7V

No Keydown Mode

3.7V

9.3V

Input Pull-Up Current

3V-l0V

Input Low Voltage (VIL) Maximum

3V-l0V

Input Low Voltage (VI H) Minimum

3V-l0V

-

VDD

Vo

MIN

MAX

UNITS

yo; Dual-Tone Output

3.7-9.3

700

mVrms

3.7-9.3

-

350

Vo (Cu; Single-Tone Output, Column (Note 3)

300

-

mVrms

Vo (RL); Single-Tone Output, Row (Note 4)

3.7-9.3

260

-

mVrms

Distortion (Note 5)

3.9-9.3

Rise and Fall Time (Dual-Tone Out) (Note 6)

3.9-9.3

Pre-Emphasis (Note 7)

3.9-9.3

9.3V

Static ElectrIcal CharacterIstIcs TA

200 .

pA

400

pA

0.2VDD

V

0.8VDD

V

= -250 C to +600 C
LIMITS

CHARACTERISTICS
TONE OUTPUTS (RL = 82)

-

-

10

%

-

5

ms

(Nom.-l%)

(Nom.+l%)

Hz

MUTE OUTPUT CURRENT

-

1.7

1.2

-0.5

IOH (Source)

10

9.5

-3.4

IOL(Sink)

10

2.5

-

1.7

1.2

-0.5

IOH (Source)

10

9.5

-3.4

-

IOL(Sink)

10

2.5

-

10

TransmiHer

Receiver

10

rnA
rnA
pA

rnA
rnA
pA

NOTES;

1. All logiC and counters functional.

6. Tone rise time Is defined as the time for each of the 2 DTMF frequencies to
attain 90% of full amplitude, measured from the time when a row and column signal are driven low.

2. Mute switches remain open.
3. Two or more row inputs low. and ona column input low.
4. Two or more column inputs low, and one row input low.

7. Pre-emphasis Is the ratio of thl1 high-group level to the low-group level.

5, Distortion is defined as: The ralio of all extraneous frequency components generated in the voiceband O.5kHz. to the power of the dual-tone
signal, measure across RL'

8. Refer

=

(V12+V22D •.. +Vn~
VL2+VH2

where Vl. V2 ..•• Vn are extraneous frequency components in the
voiceband a.5kHz to 3kHz, VL is the low-band frequency tone, and VH is
the high-band frequency tone.

9-58

to Figure 1. for standard OTMF frequencies.

CD22859
COLI

COL 2

COL 3

COL 4

ROW I

697(699.1)

ROW 2

8000

170 (7662\

ROW:3

Cl~~8

852(8474)

941 (948 0)

ROW4

)209
(12159)

1336
(13317\

1477
(14719)

r

1633 of-(16450)

NOMINAL
OUTPUT
FREQUENCY

92CS- 32956

Fig. 1 - Bell and nominal output frequencies (in
parenthesis) for 3.579545·MHz crystal.

DTMF Generator Functional Truth Table
Inputs
Number of
Number of
Column Inputs
Row Inputs
Keyboard Mode
Activated
Activated
"Low"
Low
X
X
X
No key de0
0
pressed

Normal Dialing
One Key Depressed (See
Note 1)
Two or More
Keys In
Same Row
(See Note 2)

Tone

"0"

None

"1"

None

"1"
"1"

0
1

"1"

2,3, or 4

Dual Tone
Ra,C1
None
Dual Tone

OSC
RX
Running
No "0"

"0"

"0"

"0"

No

TX

Yes

"1"

"1"

No

"0"

"0"

Ra,Cb

Yes

"1"

"1"

Single Row
Tone
Ra

Yes

"1"

"1"

:;;
0
(.)
w
..J

W
I-

Two or More
Keys In Same
Column
Two or More
Keys In Different Rows
& Columns

CD

"1"

0
1,2,3, or 4
1

Outputs

2,3, or 4

"1"

"1"

2,3 or 4

Single Column Yes
Tone
Cb

"1"

"1"

None

Yes

"1"

"1"

None

Yes

"1"

"1"

Where:
X = Do Not Care
Ra,Cb refers to Tone Output frequencies corresponding to Row 1, Row 2, Row 3,
Row 4, Column 1, Column 2, Column 3, Column 4
a = 1,2,3,4 b = 1,2,3,4 a= b, or a,.b
1. Corresponds to normal dual-tone operation.
2. Corresponds to single-tone generation mode.

9-59

CD22859
VDD

C2 4 }----+-t-l--l

C3

COL
SENCE

S}-----<~+__l

C4

9}-----~~

CD

I S } - - - - -.....--4

ROW INH

ROW

VDD

ENABLE

R2 13}----<~+_+~ SENSE

R3 1 2 } - - - -. .+~

R4 I I } - - - - -......~

RX

1--"1-------(,0

C~~i~Ol

OSCI7}-------I---,

TX

i-------{2

OSC
VSS

OOC2 8 } - - - - - - - l

-------@
Fig. 2 -Touch-tone generator.

r

lIT
VOD
+
RX

t-+---ITx

KEYPAD

I

2 3

4

S 6

CSCI

csc 2
'bUT

L2

R3

NETWORK
I
_ _ _ _ _ _ _ _ _ _ _ _ ....J

04

Fig. 3 - Interface with standard K500 telephone network.

9-60

7 8

9

CD74HC22106
CD74HCT22106

mHARRIS

QMOS 8 x 8 x 1 Crosspoint
Switch with Memory Control

August 1991

Type Features

Description

• 64 Analog Switches in an 8 x 8 x 1 Array

The CD74HC2210S and CD74HCT221 OS are digitally controlled analog switches which utilize silicon-gate CMOS
technology. The CD74HC2210S types feature CMOS input-voltage-level compatibility and the CD74HCT2210S
feature LSTIL input-voltage-level compatibility.

• On-Chip Line Decoder and Control Latches
• Automatic Power-Up Reset by Using a 0.1 JlF
Capacitor at the MR Pin
• RON Resistanced 9S0 @ VCC

=4.SV

• 2V to 10V Operation
• 4.SV to S.SV Operation
o

Analog Signal Capability: VCC2

Family Features
o

Wide Operating Temp. Range ••••• -40 0 C to +8S o C

• CD74HC Types:

The Master Reset has an internal pull-up resistor and is normally used with a 0.1JlF capacitor. During power-up all
switches are automatically reset. The crosspoint switches
will reset with MR = 0 even if CE is high. A S-bit address
through a S-line-to-S4-line decoder selects the transmission gate which can be turned on by applying a logical ONE
to the DATA input and logical ZERO to the STROBE. Similarly, any transmission gate can be turned OFF by applying
a logical ZERO to the DATA' Input while strobing the
STROBE with a logical ZERO.

~

2V to 10V Operation

The CE pin allows the crosspoint array to be cascaded for
matrix expansion in both the X and Y directions.

~

High Noise Immunity: NIL = 300/0, NIH = 30% of
VCC; @ VCC SV and 10V

The CD74HC and CD74HCT devices are supplied In the 28
lead dual-in-Iine plastic packages (E suffix).

=

o CD74HCT Types:
~

4.SV to S.SV Operation

~

Direct LSTTL Input Logic Compatibility:
VIL O.8V Max, VIH 2V Min

~

CMOS Input Compatibility:
I, < 1JlA @ VOL, VOH

=

=

Pinout
CD74HC22106,CD74HCT22106
28 PIN PLASTIC DIP
TOP VIEW
A4
A3
A2

Al

AO

Xl
X3
X5

X7

Vee
YO
Yl
Y2
Y3

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

Copyright

©

Harris Corporation 1991

9-S1

File Number

1719.1

Specifications CD 74HC221 06, CD 74HCT221 06
Absolute Maximum Ratings

Operating Temperature Range (TA)

DC Supply-Voltage (VCC):
Voltage Reference to GND •••••••••••••••••••••• -0.5V to + 11 V
DC Input Diode Current:
11K (For VI < -0.5 orVI > VCC +0.5V ••••••••••••••••••• :!:20mA
DC Output Diode Current:
10K (For Vo < -0.5 or Vo > VCC +0.5V •••••••••••••••• :!:20mA
DC Transmission Gate Current ••••••••••.••••••••••••.• :!:25mA
Power DiSSipation per Package (Po):
ForTA =-400C to +600C (Package Type E) .•••••••••• 500mW
For TA = -600 C to +850 C (Package Type E) • •• Derate Llnerity at
12mWI"C to 200mW

Package Type E ••••••••••••••••••••••.•••••• -400 C to +850C
Storage Temperature (During Soldering) for lOs Max
At distance 1/16 in.:!: 1/32 in. (1.59mm:!: 0.79mm) for Case for
lOs Max •••••.••••••••••••••••••••••••••••••••••••• +2650 C

Recommended Operating Conditions: For Maximum Reliability. Nominal Operating Conditions Should be Selected so that
Operation is Always Within the Following Ranges:
LIMITS
CHARACTERISTICS

MIN

Supply Voltage Range (ForTA = Full Package Temperature Range) VCC:
CD74HC22106
CD74HCT22106
DC Input of Output Voltage VI. Vo

MAX

UNITS

2

10

V

4.5

5.5

V

0

VCC

V

120 _ AMBIENT TEMPEjATURE ITA I' 25'C

itO
Vcc"4.5V

SU!

Cl70f---

1z

--

I

!60~
tj
z

~

50_ ---- ---

40

1

~ 3~1

~

---

~r

. 20i

~

---

--

.t

100

'TEJPERATURE

- AtoAS\EN"\1'A, 1s\Z.::s-.05· C _

1I

_.~.;s...-.. _t3I!t-C

I-

---........
-...........

------- -.....

~

90

~

8

.~

10

~ 60

on

~ 50

?
~

i

10----

on

01

~

~

(, vccL
-)

/

40
30

\

___

VCC'4.5V

Vee "9V

-----

20
10

INPUT VOLTAGE (VIN)-V

o

FIGURE 1. TYPICAL "ON" RESISTANCE AS A FUNCTION OF
INPUT SIGNALYOLTAGE

4
6
8
INPUT SIGNAL I Vts)-V

10

FIGURE 2. TYPICAL "ON" RESISTANCE AS A FUNCTION OF
INPUT SIGNAL VOLTAGE

9-62

Specifications CD 74HC221 06, CD 74HCT221 06
Static Electrical Characteristics
CD74HC22106
TEST
CONDITIONS
VI
V

CHARACTERISTICS
High-Level Input Voltage
VIH

Low-Level Input Voltage
VIL

+250 C

VCC
V

MIN

2

1.5

4.5

3.15

9

-

CDHCT22106
-400C to
+850 C

TYP MAX MIN

-

-

6.3

-

-

10

-

-

2
4.5
9

TEST
CONDITIONS
VI
V

MAX

1.5
3.5
6.3

-

-

VCC
V
4.5
to
5.5

-400C to
+85 0 C

+25 0 C
MIN

TYP MAX MIN

MAX

UNITS

2

-

-

2

-

V

-

-

0.8

-

0.8

V

1.35

2.7

-

2.7

-

±0.1

-

±1

Any
Voltage
Between
VCC&
GND

5.5

-

-

±0.1

-

±1

pA

0.5
1.35

0.5

4.5
tei
5.5

Input Leakage Current
(Any Control)
IL

GND

Quiescent Device
CurrentiCC
(withMR=1)

VCC
or
GND

10

-

-

5

-

50

VCC
or
GND

5.5

-

-

2

-

20

pA

All

10

-

-

0.1

-

1

-

5.5

-

-

0.1

-

1

pA

2

-

875

-

4.5

-

64

95

-

120

n

-

4.5

-

58

85

-

110

n

-

VCC

4.5

-

-

-

n

to

-

25

-

VCC

or

Off Leakage Current
IL
(with MR = 1)

~witches
OFF

liOn" Resistance

VCC
to
GND

RON

4.5
9

-

700

64

95

45

70

-

-

58

85

40

60

-

-

9

-

VCC

-

-

to

4.5

VCC/2

4.5

"On" Resistance
Between Any Two
Channels aRON

470

-

GND

9

-

25

-

23

-

-

120
90

110

80

GND

:;:
MON" ATTENUATION

V~~-4~

."

Vss~

iD

-4.5 V
YIS=2Vp-P
RS=RL:600{l

:2..4Q

TA~25'C

\

.,
.,

·10

I

."

...

~

~ON·

o
(,,)

VDD~4.5V

VSS'-4.5Y
YIS"2Vp-p
AS:RL=15{l
TA : 25°C

W

-I

rt . .

II

ATTENUATION

H -++H-++I+I++tIt++t-tt+t+tt-HttHIA.,

I

Z

I

1

0

.5O

~~

.GO ~-+-I+++-l+!++--f++H-++I++++tt-+-HH·12

o~~

~

~

.~

1-1-++H-t-I-Ht-H~I-+-+Bo~.~'~~+t+l-1-++~
~7
~~

"'H-+++t-+-+t+t·-++t+t-+'ftt(,f(,Q~H-+ttt-++t-H·8 ~

." 1-+-++tt--HI+It-++tlt-7f-/++tt--HI+It-+++H.'
.100H-ttfl-++Ht+-vt9t--f-ttft-Hc+tH-t+H
'DO

'K

10K

FREQUENCY - 1Hz)

100K

~

I

~

S
~

",:¥H+H--l
." H-++l+-+++++-t-t-Mt-i
I
o~t:i
... H-+ttt-+++++-+-t-Mt-i-r-j-HII'~c",,;:i4-H--H-ItI-l

1!

." H-++fH-++tt-+-+HH

l'

:;::
10

1M
10M
92.(S-39210

!

~-+-I+++-l+!+-t-Jf++H-++I++++tt-+-H-IH ·10 ~

S -so H-+++t-+-+Ht-++t+t--I--I-hI+-H4+l-7I...,.-Hl-S 5
5

l!:!

100

,K

10K

11~.~I
III
100K

FREQUENCY - (HI)

1M

~
Z

10M
92CS-39271

FIGURE 4. TYPICAL "ON" SWITCH ATTENUATION AND
"OFP' SWITCH FEED THROUGH AS A
FUNCTION OF FREQUENCY

FIGURE 3. TYPICAL "ON" RESISTANCE AND CROSSTALK
AS A FUNCTION OF FREQUENCY

9-63

Specifications CD 74HC221 06, CD 74HCT221 06
Switching Characteristics
LIMITS
' -400 C to +8So C

+2So C

CHARACTERISTICS

TEST
CONDITIONS

HC
VSS

VCC

MIN

HCT
MAX

MIN

HCT

He

MAX

MIN

MAX

MIN

MAX

UNITS

-

ns

135

ns

CONTROLS
Propagation Delay Time
Strobe to Output
(Switch Turn-On to
High Lavel) tpZH
Data-In to Output
(Turn-On to High Level)
tpZH
Address to Output
(Turn-On to High Level)
tpZH
Propagation Delay Times
Strobe to Output)
tpHZ
Data-In to Output
(Turn-On to Low Level)
tpZL
Address to Output
(Turn-Off)
tpHZ

Minimum Set-Up Time
(Data-In to Strobe
Address)tsu

Minimum Hold Time
(Data-In 10 Strobe
Address)IH

Minimum Strobe Pulse
Width

tw
Maximum Switching
Frequency
Fo
Input (Control)
Capacitance CI

RL=10kO
CL=50pF
tr,tf= 6ns

-

370

-

-

-

385

110

-

120

-

125

-

-

70

-

255

-

0

2

0

4.5

0

9

0

2

0

4.5

,-

75

0

9

50

0

2

0

4.5

-

0

9

-

65

0

2

0

4.5

0

9

0

2

0

4.5

85

50

-

--

-

-

-

-

-

150

-

-

40

20

-

-

65
240

-

85

380

-

-

110

-

120

--

-

400
135

-

-

90
240

0

9

-

0

2

-

420

0

4.5

-

140

0

9

-

95

0

2

35

0

4.5

20

0

9

15

0

2

85

0

4.5

25

0

9

20

0

2

200

0

4.5

45

0

9

25

0

2

0.7

0

4.5

3.0

0

9

7

-

-

-

-

10

75

-

-

9-64

-

150

~

55

-

400

-

85

125
75
420
155
100
255

-

-

95

135

-

ns
ns
ns
ns
ns
ns
ns
ns

170

ns

-

ns

-

ns

95

ns

-

ns

55

-

440

-

-

ns

155

-

170

ns

-

-

85

100

20

-

20

-

15

-

-

-

-

90

-

25

-

25

-

-

20

-

-

-

210

-

55

-

-

30

-

-

0.6

55

-

-

2.8

-

2.8

-

-

6.5

-

10

-

10

25

65

-

2.6

-

-

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz

-

MHz

10

pF

Specifications CD74HC22106, CD74HCT22106
Analog Channel Characteristics
LIMITS
-400C to +B5 0 C

+25 0 C

CHARACTERISTICS

TEST
CONDITIONS

Propagation Delaylime, tpHL

RL=lOkn

Signal Input to Output, tPLH

CL=50pF
tr,!i=6ns

Switch Frequency
Response @ -3dB

Crosstalk Between Any Two
Channels

RS=RL=600n

-

Total Harmonic Distortion
tHD

Control to Switch
Feed-Thru Noise
(DATA IN, Strobe,Address)

VSS VCC
0

2

0

4.5

-

9

2Vp-p

-2.25 2.25

2Vp-p

-4.5

4.5

MIN

HC

HCT

MAX

MIN

MAX

MIN

30

20

15

-

-

-

33

20

-

Typical
5

Typical
5

-

6

6

-

Typical
-110

-

MAX MIN

MAX UNITS

-

-

ns

22

ns

-

ns

-

-

-

MHz

-

-

MHz

-

-

-

dB

-

-

MHz

-

-

MHz
%

22
17

RS=RL=600n
f=lkHz

2Vp-p

-2.25 2.25

Typical
-110

f=lMHz

2Vp-p

-2.25 2.25

-53

-53

-55

-55

-

Typical
7

Typical
7

-

8

8

-

-

Typical
0.05

Typical
0.05

-

0.05

-

-

0.05

-

-

-

-

-

-

-

-

%

-

-

mV

-

mV

2Vp-p
Switch "OFP'
-40dB Feed Through
Frequency

HCT

HC
VIS

RS=RL=600n

2Vp-p
2Vp-p

-4.5

4.5

-2.25 2.25
-4.5

4.45

dB
dB

RL=lOkn

4Vp-p

-2.25 2.25

f = 1kHz Sinewave

8Vp-p

-4.5

RL=600n

4Vp-p

-2.25 2.25

0.25

0.25

f = 1 kHz Sinewave

7Vp-p

-4.5

4.5

0.12

0.12
Typical
35

-

-

-

-

-

-

-

-

pF

-

-

-

pF

4.5

RL=lOkn

5

0

5

Typical
35

tr,!i=6ns

10

0

20

65

65
Typical
48
44

Capacitance, Co
XntoGND

f=lMHz

-

0

10

Typical
48

YntoGND

f=lMHz

-

0

10

44

%
%

::;;;

o

frl
-'

W
I-

9-65

CD74HC22106, CD74HCT22106

Truth Table
AS

A4

A3

A2

A1

AO

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
00
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

SWITCH SELECT

Xo
Xl
X2
Xa
X4
X5
X6
X7
Xo
Xl
X2
Xa
X4
X5
X6
X7
Xo
Xl
X2
Xa
X4
X5
X6
X7
Xo
Xl
X2
Xa
X4
X5
X6
X7

Yo
Yo
Yo
Yo
Yo
Yo
Yo
Yo
Yl
Yl
Yl
Yl
Yl
Yl
Yl
Yl
Y2
Y2
Y2
Y2
Y2
Y2
Y2
Y2
Ya
Ya
Ya
Ya
Ya
Ya
Ya
Ya

AS

A4

A3

A2

A1

AO

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

SWITCH SELECT

Xo
Xl
X2
Xa
X4
X5
X6
X7
Xo
Xl
X2
Xa
X4
X5
X6
X7
Xo
Xl
X2
Xa
X4
X5
X6
X7
Xo
Xl
X2
Xa
X4
X5
X6
X7

Y4
Y4
Y4
Y4
Y4
Y4
Y4
Y4
Y5
Y5
Y5
Y5
Y5
Y5
Y5
Y5
Y6
Y6
Y6
Y6
Y6
Y6
Y6
Ys
Y7
Y7
Y7
Y7
Y7
Y7
Y7
Y7

r-----~------~----~------~------~----~------~--__o~

r--+--~--4---~-4--~---+--~--4---~-4--~---r--~--t-oY2

r--+--~--1---~~--~---+--~--1---~~--~---r--~--t-0. Y3

x4

FIGURE 5. FUNCTIONAL DIAGRAM

9-66

x.

CD74HC22106, CD74HCT22106
Test Circuits and Waveforms

DATA-IN

~ ----I

50pF

SW' ANY CROSSPOINT

t.

IPZH

"--=f1O~

=

92CM - 39264

AGURE 6. PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS (STROBE TO
SIGNAL OUTPUT, SWITCH TURN-ON OR TURN-OFF)

DATA IN

STROBE =VOO

FIGURE 7. PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS (DATA-IN TO
SIGNAL OUTPUT, SWITCH TURN-ON TO HIGH OR LOW LEVEL)

::iE

o

oW

....I

W
I-

ADDRESS"!

AOORESS·O

VOO ---t,~,1
ADDRESS

VOO
DATA-IN

Vas I

0-

voo---b...1

SW ... ANY CROSSPOINT

Vas 2

STROBE: Voe

0

FIGURE 8. PROPAGATION DELAY TIME TEST CIRCUIT AND WAVEFORMS (ADDRESS
SIGNAL OUTPUT, SWITCH TURN-ON OR TURN-OFF)

9-67

92CM-30276

CD 74HC22 706, CD 74HCT22 706
Test Circuits and Waveforms

(Continued)

'5 V

'5 V
HC or CMOS
Output

Vcc

Control
Inpul

:n

HC
22106

Analog

Analog Output
0-5 V

Input

0-"

#HC Logic lor CMOS Inputs
HCT Logic for TTL Inpuls

VS5

GND

FIGURE 9_ TYPICAL SINGLE-SUPPLY CONNECTION FOR HC22106
'5 V

'5 V
CD4000AlB
CMOS Bipolar
Output

5V
' OV
-5 V

VCC

Control
Input

..:R::

HC22106

Analog Output
-510+5 V

Analog

Input
-510 +5 V

-5 V

V55

-5 V

FIGURE 10. TYPICAL DUAL-SUPPLY CONNECTION FOR HC22106

+10 V

"10 V

'. V
1 KO

Control

Signal

Vcc
Control
Input

:>----1

HC
22106
*For CMOS Input Levels Use He03 Logic Type
For ITt Input Levels Use HCT03 Logic Type

Analog Output
0-10 V

Analog
Inpul
0-10 V
VS5

GND

FIGURE 11. USE OF HC/HCT03 WHEN CONTROL SIGNAL IS OV - 5V AND ANALOG SIGNAL IS OV - 10V

'. V

'5V

TTL Type
Output

Control
Input

VCC

HCT

22106

Analog Output
0-5 V

Analog
Inpul
0-5 V

Vss
GND

FIGURE 12. TYPICAL SINGLE-SUPPLY CONNECTION FOR HCT22106 WITH TTL INPUT

9-68

HC-5502A

mHARRIS

SLiC
Subsciber Line Interface Circuit

August 1991

Features

Description

• Monolithic Integrated Device

The Harris SLiC incorporates many of the BORSHT
function on a single IC chip. This includes DC battery
feed, a ring relay driver, supervisory and hybrid functions.
This device Is designed to maintain transmission performance in the presence of externally induced longitudinal cUrrents. Using the unique Harris dielectric isolation process,
the SLiC can operate directly with a wide range of station
battery voltages.

• 01 High Voltage Process
• Compatible With Worldwide PBX Performance
Requirements
• Controlled "Supply of Battery Feed Current for Short
Loops (30mA)
• Internal Ring Relay Driver
• Low Power Consumption During Standby
• Switch Hook, Ground Key and Ring Trip Detection
Functions
• Selective Denial of Power to Subscriber Loops

Applications
• Solid State Line Interface Circuit for Analog and
Digital PBX Systems

The SLiC also provides selective denial of power. If the PBX
system becomes overloaded during an emergency, the
SLiC will provide system protection by denying power to
selected subscriber loops.
The Harris SLiC is ideally suited for the design of new
digital PBX systems, by eliminating bulky hybrid
transformers.
SLiC Is available In either a 24 pin Dual-in-Line Plastic or
Ceramic package, and a 28 pin PLCC package.

• Direct Inward Dial (DID) Trunks
• Voice Messaging PBX's

Pinouts
HC-5502A
(CERAMIC/PLASTIC DIP).
TOP VIEW

HC4P5502A
(PLCC)
TOP VIEW

TIP

TX

RING

AG

Vs+

C4

Cl*

RX

C3

+IN

DG

-IN

RS

OUT

RD

C2

TF

Rc
Po

RF
VB_

GKD

BG

SHD

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

9-69

File Number

2868

HC-5502A

Schematic
21

22

Rev

C4

20

IB

19

OUT

VOLTAGE 8. CURRENT
BIAS NETWORK

GND SHORTS
CURRENT LIMITING

'B1

RS

C3

HC-5502A SUC FUNCTIONAL SCHEMATIC.

Die Characteristics
Transistor Count •..•.•....•....................... 181
Diode Count ...............•........•.......•...... 27
Die Dimensions ............................. 169 x 112
Substrate Potential ....................... Unconnected
Process .................................... Bipolar-DI
Thermal Constants (OCIW)
Bja
Bjc
Ceramic DIP
51
16
Plastic DIP
52
24

9-70

iiii

Specifications HC-5502A
Absolute Maximum Ratings (Note 1)

Recommended Operating Conditions

Maximum Continuous Supply Voltages (VB-)..... -60 to +0.5 V
(VB+) .... -0.5to+15V
(VB+ - VB-) .•.•••.. 75V
Relay Drive Voltage (VRD) ••....•..••.••..•...•••. -0.5 to +15V
Storage Temperature Range ......•.......••. -650 C to +15COC
Junction Temperature .•..•......•.••.....•...•.••.•.. +1750 C

Relay Driver Voltage (VRD) ...•.•.•..•....•......•.. +5 to +12V
Pos~ive Supply Voltage (VB+) ..•...•..•........••. 10.8 to 13.2V
Negative SupplyVoltage(VB-) •....•••.•............ -42 to -58V
Minimum High Level Logic Input Voltage .•........•....... 2.4V
Maximum Low Level Logic Input Voltage .•..•.....•....... 0.6V
Loop Resistance (RLl ..•.•...•..•.....•...•. 200 to 1200 Ohms
Operating Temperature Range
HC-5502A-5,-7 ..•..•.........•............•. OOC to +750 C
HC-5502A-9 .•.. . . . . . . . . . • . . . • . . . . . . . . . .. -40OC to +850C

Electrical Specifications VB- '= -48V, VB+ = +12V, AG = BG = DG = OV, Unless Otherwise Noted,
Typical Parameters +250 C. Min-Max Parameters are Over Operating Temperature Range.

MIN

TYP

MAX

UNITS

On Hook Power Dissipation

PARAMETER
ILong=O

CONDITIONS

-

135

174

mW

Off Hook Power Dissipation

RUNE = 600 Ohms,lLong = 0

-

450

580

mW

Off Hook IB+

RUNE = 600 Ohms, ILong = 0 @ -400 C

-

5.0

mA

Off Hook IB+

RUNE = 600 Ohms,lLong = 0 @ +25OC

-

-

4.3

mA

Off Hook IB-

RUNE = 600 Ohms, ILong = 0

-

-

38

mA

Off Hook Loop Current

RUNE = 1200 Ohms,lLong = 0

-

21

Off Hook Loop Current

RUNE = 1200 Ohms, VBTA=250 C

17.5

-

-

Off Hook Loop Current

RUNE = 200 Ohms, ILong = 0

25.5

30

34.5

mA

-

mA

=-42V,ILong =0

mA
mA

Fault Currents
TIPtoGround

-

14

RING to Ground

-

47

TIPtoRING
Ring Relay Drive VOL

IOL=62mA

-

Ring Relay Driver Off Leakage

VRD= +12V, RC = 1 = HIGH, TA = 250 C

-

TIP and RING to Ground

Ring Rrip Detection Period

RUNE = 600 Ohms, TA = +250 C

-

Switch Hook Detection Threshold

SHD=VOL

10

SHD=VOH

-

GKo=VOL

20

Ground Key Detection Threshold
Loop Current During Power Denial

-

Dial Pulse Distortion

0

Receive Input Impedance

-

GKo=VOH

Transmit Output Impedance
Two Wire Return Loss

mA
mA

47

-

0.2

0.5

V

-

100

flA

2

3

Ring Cycles

-

-

mA

5

mA

-

mA

±2

10

-

mA

mA

-

5

ms

:5

90

-

kOhms

o

5

20

Ohms

(Return Loss Referenced to 600n +2.16IlF)"

-

SRLLO
ERL
SRLHI
Longitudinal Balance

30

-

15.5
24
31

-

dB
dB
dB

1V Peak-Peak 200Hz - 3400Hz
00C~TA~750C

2 Wire Off Hook

58

65

2Wire On Hook

60

63

4 Wire Off Hook

50

58

-

-

Low Frequency Longitudinal Balance

R.EA Method, COC STA ~ 750 C

NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the servlcealblily of the
circuit may be impaired. Functional operability under any of these conditions is not necessarily implied.

9-71

-

dB
dB
dB

23

dBmC

-67

dBmOp

o

w

-'

I:!:!

Specifications HC-;5502A
Electrical Specifications

(Continued)

PARAMETERS
Insertion Loss
2 Wire - 4 Wire
4 Wire - 2 Wire
Frequency Response

CONDITIONS
@lkHz,OdBm Input Level

. 200 - 3400Hz Referenced to Absolute
Loss at 1kHz and OdBm Signal Level
00C~TA'$.75OC

Idle Channel Noise
2 Wire - 4 Wire

OOC :~;;TA ~ 750 C

4 Wire - 2 Wire
Absolute Delay
2 Wire - 4 Wire
4 Wire - 2 Wire
Trans Hybrid Loss
Overload Level
2 Wire - 4 Wire
4 Wire - 2 Wire
Level Linearity
2 Wire - 4 Wire

4 Wire - 2 Wire

Power Supply Rejection Ratio
VB+t02 Wire
VB+ to Transmit
VB-t02Wire
VB- to Transmit
VB+t02Wire

VB+ to Transmit
VB-to 2 Wire
VB- to Transmit
Logic Input Current (RS, Re, Po)
Logic Inputs
LogiC '0' VII
Logic'l'VIH
Logic Outputs
Logic '0' VOL
Logic'l'VOH

MIN

TYP

MAX

UNITS

-

±0.05

±D.05

±0.2
±0.2
±0.05

dB
dB
dB

-

1
-89
1
~89

5
-85
5
-85

dBrnC
dBmOp
dBrnC
dBmOp

-

-

2
2

36

40

-

I's
I's
dB

-

Vpeak
Vpeak

±0.05
±0.1
±0.3
±0.05
±0.1
±0.3

dB
dB
dB
dB
dB
dB

-

dB
dB
dB
dB

-

dB
dB
dB
dB

±100

IlA

0.8
5.5

Volts
Volts

OOC~TA ~750C

Balance Network Set Up for 600 Ohm
Termination at 1kHz
QOC~TA~75OC

1.75
1.75
at lkHz,QOC ~TA ~750C
+3to-4OdBm
-40 to -50dBm
-50 to -55dBm
+3to-40dBm
-40to-50dBm
-50to-55dBm

-"00C~TA~750C
30 - 60Hz, RUNE = BOOO

15
15
15
15

2oo-16kHz
RLINE=600{}

30

OV5VIN55V

-

30
30
30

2.0

-

ILOAD BOOIlA
ILOAD801lA

±0.02

--

-

2.7

0.1
5.0

0.5
5.5

Volts
Volts

MIN

TYP

MAX

UNITS

-

-mV

Uncommitted Op Amp Specifications
PARAMETER

CONDITIONS

-

Input Offset Voltage
Input Offset Current
Input Bias Current
Differential Input Resistance
Output Voltage Swing
Output Resistance

RL=10K
AVCL=l

-

Small Signal GBW

9-72

±5
±10
20
1
±5
10
1

-

-

nA
nA
MO
Vpeak
{}

MHz

Pin Assignments HC-5502A
28PIN
PLCC

24 PIN
DIP

SYMBOL

2

1

TIP

DESCRIPTION

An analog input connected to the TIP (more positive) side of the subscriber loop through a 1500
feed resistor and a ring relay. Functions with the Ring terminal to receive voice signals from
the telephone and for Loop Monitoring Purposes.

3

2

RING

An analog input connec1ed to the RING (more negative) side of the subscriber loop through a
1500 feed resistor. Functions with the Tip terminal to receive voice signals from the telephone
and for loop monitoring purposes.

4

3

VB+

Positive Voltage Source - Most positive supply. VB+ is typically 12 volts with an operational
range of 1 0.8 to 13.2 volts.

5

4

Cl

Capacitor #1 - Optional Capacitor used to improve power supply rejec1ion. This pin should
be left open if unused.

6

5

C3

Capacitor #3 - An external capacitor to be connected between this terminal and analog ground.
Required for proper operation of the loop current limiting function, and for filtering VBsupply. Typical value is 0.3~F, 30V.

7

6

DG

Digital Ground - To be connec1ed to zero potential and serves as a reference for all digital
inputs and outputs on the SLiC.

9

7

RS

Ring Synchronization Input - A TIL - compatible clock input. The clock is arranged such that
a positive transition occurs on the negative going zero crossing of the ring voltage source,
ensuring that the ring relay is activated and deac1ivated when the instantaneous ring voltage
is near zero. If synchronization is not required, tie to +5V.

10

8

AD

Relay Driver - A low active open collector logic output. When enabled, the external ring relay
is energized.

11

9

TF

Tip Feed - A low inpedance analog output connec1ed to the TIP terminal through a 1500 feed
resistor. Func1ions with the RF terminal to provide loop current, feed voice signals to the
telephone set, and sink longitudinal current.

12

10

RF

Ring Feed - A low impedance analog output connec1ed to the RING terminal through a 1500 feed
resistor. Func1ions with the TF terminal to provide loop current, feed voice sin gals to the
telephone set, and sink longitudinal currents.

13

11

VB-

Negative Voltage Source - Most negative supply. VB- is typically -48 volts with an operational
range of -42 to -58 volts. Frequently referred to as "battery".

14

12

BG

Battery Ground - To be connected to zero potential. All loop current and some quiescent current
flows into this ground terminal.

16

13

SHD

Switch Hook Detec1ion - A low active LS TIL - compatible ligic output. This output is enabled
for loop currents exceeding 1OmA and disabled for loop currents less than 5mA.

17

14

GKo

Ground Key Detection - A low active LS TIL - compatible logic output. This output is enabled
if the DC current into the ring lead exceeds the DC current out of the tip lead by more than
20mA, and disabled if this current difference is less than 10mA.

18

15

Po

Power Denial - A low active TIL - Compatible logic input. When enabled theJ!!llitch hook detect (SHD)
and ground key detect (GKD) are not necessarily valid, and the relay driver, (RD) output is disabled.

19

16

RC

Ring Command - A low ac1ive TIL - Compatible logic input. When enabled, the relay driver (Ao)
output goes low on the nel!llising edge of the ring sync (RS) input, as long al!.!!!!> SLiC is not
in the power denial state (PO = 0) or the subecriber is not already off- hook (SHD = 0).

20

17

C2

21
23
24
25

18
19
20
21

OUT
-IN

Capacitor #2 - An extemal capacitor to be connec1ed between this terminal and digital ground.
Prevents false ground key indications from occuring durring ring trip detection. Typical value
is 0.15~F, 10V. This capacitor is ont used if ground key function is not required.
The analog output of the spare operational amplifier.
The inverting analog input of the spare operational amplifier.
The non-inverting analog input of the spare operational amplifier.
Receive Input, Four Wire Side - A high inpedance analog input which is internally biased.
Capacitive coupling to this input is required. AC signals appearing at this input differentially
drive the Tip feed and Ring feed amplifiers, which in turn drive tip and ring through
300 Ohms of feed resistance on each side of the line.

26

22

C4

Capacitor #4 - An extemal capaCitor to be connec1ed between this terminal and analog
ground. This capacitor prevents false ground key indication and false ring trip detec1ion
from occurring when longitudinal currents are induced onto the subscriber loop from near
proximity power lines and other noise sources. This capacitor is also required for the proper
operation of ring trip detection. Typical value is 0.5~F, to 1.0~F, 20V. This capicitor should
be non polarized.

27

23

AG

Analog Ground - To be connected to zero potential and serves as a reference for the transmit
output (TX) and receive input (RX) terminals.

28

24

TX

Transmit Output, Four Wire Side - A low impedance analog output which represents the
differential voltage across Tip and Ring. Transhybrid balancing must be preformed (using
the SLiC microcircuit's spare op amp) beyond this output to completely implement two to four
wire conversion. This output is unbalanced and referenced to analog ground. Since the DC level
of this output varies with loop current, capacitive coupling to the next stage is essential.
No Internal Connec1ion.

1,8,15,22

+IN
RX

NC

NOTE: All grounds (AG, BG, & DG) must be applied before VB+ or VB -. Failure to do so may result in premature failure of the part. If a user wishes to run
separate grounds off a line card. the AG must be applied first.

9-73

HC-5502A
Applications Diagram
TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC

Flr~~RI

SWITCHING

CODEC

NETWORK

""
TYPICAL COMPONET VALUES
C1 =
C2 =
C3 =
C4 =

C5 = 0.5"F, 20V
C6 C7 0.5"F (10% Match Required) (Note 2), 20V
. C8 = O.01"F, 100V
C9 = 0.01 "F, 20V, ±20%

0.5"F (Note 1)
0.15"F, 10V
0.3"F,30V
0.5"V to 1.0"F, ±10%, 20V (Should be non polarized)

=

=

=

=

R1 -+ R3 100kO (0.1% Match Required, 1% absolute value), ZB 0 for 6000 Terminations (Note 2)
RB1
RB2 RB3 RB4 1500 (0.1 % Match Required, 1% absolute value)
RS = 1kO, Cs = 0.1 IIF, 200V typically, depending on VRing and line length.
Z1
150V to 200V transient protector. PTC used as ring ballast.

=

=

=

=

=

NOTE 1: C1 is an optional capacitor used to improve +12V supply rejection. This pin must be left open if unused.
NOTE 2:

To obtain the specified transhybrid loss it is necessary forthe three legs of the balance network, C6-R1 and R2 and C7-ZB-R3,
.to match in impedance to within 0.3%. Thus, if C6 and C7 and 1IIF each, a 20% match is adequate. It should be noted that the
transmit output to C6 see's a -10.5 to -21 volt step when the loop is closed and that too large a value for C6 may produce an
excessively long transient at the op amp output to the PCM Filter/CODEC.
A 0.5"F and 100kO gives a time constant of 50msec. The uncommitted op amp output is internally clamped to stay within
±5.5V and also has current IimHing protection.

NOTE 3:

Secondary protection diode bridge recommended is MDA 220 or equivalent.
ADDITIONAL INFORMATION IS CONTAINEDIN APPLICATION NOTE 549, ''THE HC-550X TELEPHONE SLlCs"
BY GEOFF PHILLIPS

Overvoltage Protection and
Longitudinal Current Protection

TABLE 1

The SLiC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
High voltage surge conditions are as specified in Table 1.
The SLiC will withstand longitudinal currents up to a maximum or 30mA RMS, 1SmA RMA per leg, without any performance degradation.
'

TEST
CONDITION

PEFORMANCE
(MAXI

UNITS

Longitudinal
Surge

10"sRise/
1000"s/Fail

±1 000 (Plastic)
±500 (CeramiC)

V Peak
V Peak

Metallic Surge

1O"s Rise/
1000" Fall

±1 000 (PlastiC)
±500 (CeramiC)

V Peak
V Peak

T/GND
R/GND

10"sRise/
1000"sFall

±1 000 (Plastic)
±500 (Ceramic)

V Peak
V Peak

11

Cycles

PARAMETER

50/60Hz
Current
T/GND
R/GND

9-74

700Vrms
Limiledto
10Arms

m

HC-5502B

HARRIS

SLIC
Subscriber Line Interface Circuit

August 1991

Features

Description

•
•
•
•
•

The Harris SUC incorporates many of the BORSHT
function on a single IC chip. This includes DC battery feed,
a ring relay driver, supervisory and hybrid functions. This
device is designed to maintain transmission performance in
the presence of externally induced longitudinal currents.
Using the unique Harris dielectric isolation process, the
SUC can operate directly with a wide range of station
battery voltages.

Pin For Pin Replacement For The HC-5502A
Capable of +12V or +5V (VB+) Operation
Monolithic Integrated Device
01 High Voltage Process
Compatible With Worldwide PBX Performance
Requirements
Controlled Supply of Battery Feed Current for
Short Loops (30mA)
Internal Ring Relay Driver
Low Power Consumption During Standby
Switch Hook, Ground Key and Ring Trip Detection
Functions
Selective Denial of Power to Subscriber Loops

•
•
•
•
•

The SUC also provides selective denial of power. If the PBX
system becomes overloaded during an emergency, the
SUC will provide system protection by denying power to
selected subscriber loops.
The Harris SUC is ideally suited for the design of new
digital PBX systems, by eliminating bulky hybrid
transformers.

Applications

The SUC Is available in either a 24 pin Dual-in-Line Plastic
or Ceramic package, a 28 pin PLCC package and a 24 pin
SOIC package.

Solid State Line Interface Circuit for Analog and
Digital PBX Systems
o Direct Inward Dial (DID) Trunks
o Voice Messaging PBX's
o

Pinouts

Functional Diagram

HC1-5502B (24 PIN CERAMIC DIP)
HC3-5502B (24 PIN PLASTIC DIP)
HC9P5502B (SOIC)
TOP VIEW

TRANSMIT
OUTPUT

::;;:

o
ow

-'
w

IRINGQ----'V""'"-+-.::;:.::O-fl..J
POWER DENIAL

HC4P5502B (PLCC)
TOP VIEW

;:!

PO

1

·1

AX RECEIVE

1 _ _ _ _s~ MICROCIRCUIT _ _ _

1

INPUT

.J

~nruNG-rt+_-JL
HC4PSS04DLC (PLCC)
TOP VIEW

___<

RING
VOLTAGE
V

a-

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.e. handling procedures should be followed.

Copyright @ Harris Corporation 1991

9-95

File Number

2443.1

HC-5504DLC

Schematic
21

22

11

RX

c.

Et

"

Z3

•

GND

GND

•

~ ~~ ~
GNO

V.+

20

"

OUT

VOLTAGE & CURRENT
BIAS NETWORK

C3

TX

Z4

HC-5504DLC SLIC FUNCTIONAL SCHEMATIC

9-96

RS

HC-5504DLC
Schematic

(Continued)

....----------1
LOGIC BIAS

HC-5504DLC LOGIC GATE SCHEMATIC

Die Characteristics
Transistor Count ..............•..•............•... 185
Diode Count ..•.....•.........•.................... 36
Die Dimensions .•.....•.......•.••...... 137 x 102 mils
Substrate Potential ...••..•......••......... Connected
Process .••••...•.•...•...•..•...•.......... Blpolar-DI
Thermal Constants (OC/W)
9ja
9jc
52
15
Ceramic DIP
Plastic DIP
52
22
PLCC
67
29
SOIC
76
24

9-97

C2

Specifications HC-5504DLC
Absolute Maximum Ratings

Recommended Operating Conditions

(Note 1)

Maximum Continuous Supply Voltages

(VB-)..... -60 to +0.5 V
(VB+) •••• -0.5to+15V
(VB+ - VB-) •••••. +75V
Relay Drive Voltage (VRD) ••••...•••..•••.••.••••. -0.5 to +15V
Storage Temperature Range ••..••••..•••.••.•• -650C to 1500 C
Juncllon Temperature Ceramic .•••••..••..•.•.•...••.• +1750 C
Junction Temperature Plastic •.•••••..•••.••.•••..•••. +1500 C

Electrical Specifications

Relay Driver Voltage (VRD) •••••••••.••••...•••.•.•• +5 to +12V
Positive Supply Voltage (VB +) . • • . • •. 4. 75to 5.25 or 10.8 to 13.2V
Negative SupplyVoltage(VB-) ..•.••••.••••.•••.•••• -42 to -58V
High Level Logic Input Voltage •••••.•.••••••••••••••••••• 2.4V
Low Level Logic Input Voltage .•••••••••••..••.••••••••••• 0.6V
Loop Resistance (RLl •••••••..•••.••••.••.•• 200 to 1200 Ohms
Operating Temperature Range
HC-5504DLC-5
•.•.••.•..•••••••• '••.•.•..• OOC to + 750 C
HC-5504DLC-Q •••.••••••••••••.••.••.••• -400 C to +850 C

Unless Otherwise Specified, VB- = -48V, VB+ = +12V and +5V, AG = BG = DG = OV,
Typical Parameters TA = +25 0 C. Min-Max Parameters are Over Operating Temperature Range.

PARAMETER

CONDITIONS

On Hook Power Dissipation

ILong*=O,VB+ =+12V

Off Hook Power Dissipation

RL = 600 Ohms,ILong* = 0, VB+ = +12V

MIN

TYP

MAX

-

170

235

mW

425

550

mW

-

6.0

mA

5.3

mA

41

mA

rnA

mA

Off HooklB+

RL = 600 Ohms,ILong* = 0, TA = -40 o C

-

OffHooklB+

RL = 600 Ohms,ILong* = 0, TA = +250 C

-

Off Hook IB-

RL = 600 Ohms,ILong* = 0

-

35

Off Hook Loop Current

RL = 1200 Ohms,ILong* = 0

-

21

Off Hook Loop Current

RL = 1200 Ohms, VB- = -42V,ILong* = 0

17.5

-

-

36

41

48

UNITS

mA

TA=+250 C
Off Hook Loop Current

RL = 200 Ohms,ILong* = 0

Fault Currents

-

TIP to Ground

-

RING to Ground
TIP to RING
TIP and RING to Ground

-

14

-

mA

55

-

0.2

0.5

V

-

100

pA

55
41

mA
mA
mA

Ring Relay Drive VOL

IOL-62mA

Ring Relay Driver Off Leakage

VRD = +12V,RC -1 - HIGH, TA- +25 0 C

Ring Trip Detection Period

RL=6000hms

-

2

3

Ring Cycles

Switch Hook Detection Threshold

SHD=VOL

18

-

mA

SHD=VOH

-

-

12

mA

GKD=VOL

20

rnA

-

-

GKD=VOH

-

10

-

RL=2000hms

-

±2

-

mA

-

Ground Key Detection Threshold

Loop Current During Power Denial
Dial Pulse Distortion

5

rns

-

110

-

kOhms

10

20

Ohms

-

15.5

-

dB

ERL
SRLHI

-

31

0

Receive Input Impedance

(Note 2)

Transmit Output Impedance

(Note 2)

Two Wire Return Loss

(Referenced to 6000 +2.16~F), (Note 2)

SRLLO

Longitudinal Balance
2 Wire Off Hook

4 Wire Off Hook

-

dB
dB

1 VRMS 200Hz - 3400Hz, (Note 2)
IEEE Method

2 Wire On Hook

Low Frequency Longitudinal Balance

24

OOC ~TA!> +750 C
R.EA Method, (Note 2), RL= 600
00C~TAS+750C

58

65

80

63

50

58

-

-

* ILong = Longitudinal Current
NOTE: 1. Absolute maximum ratings are limiting values. applied Individually. beyond which the serviceability of the
circuit may be Impaired. Functional operability under any of these conditions Is not necessarily implied.

9-98

-

dB

23

dBmC

-67

dBmOp

dB

dB

Specifications HC-5504DLC
Electrical Specifications (Continued)
PARAMETERS
Insertion Loss

CONDITIONS

2 Wire - 4 Wire, 4 Wire - 2 Wire
Frequency Response

MIN

TYP

MAX

UNITS

±0.05

±0.2

dB

±0.02

±0.05

dB

at 1kHz, OdBm Input Level, Referenced 600n

200 - 3400Hz Referenced to Absolute

-

Loss at 1kHz and OdBm Signal Level (Note 2)
Idle Channel Noise

(Note 2)

-

2 Wire - 4 Wire, 4 Wire - 2 Wire

Absolute Delay

5

dBmC

-85

dBmOp

(Note 2)

2 Wire - 4 Wire, 4 Wire - 2 Wire
Trans Hybrid Loss

1
-89

Balance Network Set Up for 600n

-

-

2

ps

36

40

-

dB

-

-

Vpeak

-

±0.05

dB

±0.1

dB

±0.3

dB

Termination at 1kHz
Overload Level
2 Wire - 4 Wire, 4 Wire - 2 Wire
Level Linearity
2 Wire - 4 Wire, 4 Wire - 2 Wire

1.5

VB+=+5V

1.75

VB+=+12V
at 1 kHz, (Note 2)

-

+3to-40dBm

-

-40to-50dBm
-50 to -55d Bm
Power Supply Rejection Ratio
VB+ to 2 Wire

Vpeak

-

(Note 2)
30 - 60Hz, RL = 600n

15

VB+ to Transmit

15

VB-to 2 Wire

15

VB- to Transmit

15

VB+ to 2 Wire

200-16kHz

30

VB+ to Transmit

RL=600n

30

-

VB-to 2 Wire

30

VB- to Transmit

30

-

-

Logic '0' VIL
Logic 'I' VIH

Logic Input Current (RS, RC, PO)

OV< VIN<+5V

-

-

dB
dB
dB
dB
dB
dB
dB
dB

-

±100

pA

-

-

0.8

Volls

2.0

-

5.5

Volls

-

0.1

0.5

Volls

Logic Inputs

Logic Outputs

:;;

Logic '0' VOL

ILOAD 800pA, VB+ = +12V, +5V

Logic'1'VOH

ILOAD 80pA, VB+ = +12V

2.7

5.0

5.5

Volls

ILOAD 40pA, VB+ = +5V

2.7

-

5.0

Volls

MIN

TYP

MAX

UNITS

-

±5

-

mV

±10

-

nA

20

-

1

-

Mn

Uncommitted Op Amp Specifications
PARAMETER

CONDITIONS

Input Offset Voltage
Input Offset Current
Input Bias Current
Differential Input Resistance

(Note 2)

Output Voltage Swing

RL = 10K, VB+ = +12V

Output Resistance

AVCL = 1 (Note 2)

-

Small Signal GBW

(Note 2)

-

RL = 10K, VB+ = +5V

NOTE:

2. These parameters are controlled by design or process parameters and are not directly tested. These
parameters are characterised upon initial design release, upon design changes which would affect Ihesa
characteristics, and al intervals to assure product quality and specification compliance.

9-99

±5
±3
10
1

-

nA

Vpeak
Vpeak
n
MHz

o
oW

-I

W
I-

Pin Assignments HC-5504DLC
2BPIN
PLCC

24 PIN
DIP

SYMBOL

DESCRIPTION

2

1

TIP

3

2

RING

4

3

RFS

5

6

4
5

VB+
C3

7

6

DG

9

7

RS

10

8

R6

11

9

TF

12

10

RF

13

11

VB-

14

12

BG

16
17

13
14

SHD
GKD

18

15

PO

19

16

RC

20

17

C2

21
23
24
25

18
19
20
21

OlIT
-IN
+IN
RX

26

22

C4

27

23

AG

28

24

TX

An analog input connected to the TIP (more positive) side 01 the subscriber loop through a 1500
feed resistor and a ring relay contact. Functions with the Ring terminal to receive voice signals from
the telephone and for loop monitoring purposes.
An analog input connected to the RING (more negative) side of the subscriber loop through a
1500 feed resistor and a ring relay contact. Functions with the Tip terminal to receive voice signals
from the telephone and for loop monitoring purposes.
Senses ring side of loop for ground key and ring trip detection. During ringing, the ring signal
is inserted into the line at this node and RF is isolated from RFS via a relay.
Positive Vollage Source - Most positive supply. VB+ is typically 12 volts or 5 volts.
Capacitor #3 - An external capacitor to be connected between this terminal and analog ground.
Required for proper operation of the loop current limiting function, and for filtering VB-.
Typical value is 0.311F, 30V.
Digital Ground - To be connected to zero potential and serves as a reference for all digital
inputs and outputs on the SLIC microcircuit.
Ring Synchronization Input - A TTL - compatible clock Input. The clock should be arranged such
that a positive pulse transition occurs on the zero crossing of the ring vollage source, as it
appears at the RFS terminal. For Tip side injected systems,the RS pulse should occur on the
negative going zero crossing and for Ring injected systems, on the positive going zero crossing.
This ensures that the ring relay activates and deactivates when the instantaneous ring voltage
is near zero. If synchronization is not required, the pin should be tied to +5V.
Relay Driver - A low active open collector logic output. When enabled, the external ring relay
is energized.
Tip Feed - A low impedance analog output connected to the TIP terminal through a 1500 feed
resistor. Functions with the RF terminal to provide loop current, feed voice signals to the
telephone set, and sink longitudinal current.
Ring Feed - A low impedance analog output connected to the RING terminallhrough a 1500 feed
resistor. Functions with the TF terminal to provide loop current, feed voice signals to the
telephone set, and sink longitudinal current.
Negative Vollage Source - Most negative supply. VB- is typically -48 volls wRh an operational
range of -42 to -58 volts. Frequently referred to as "battery".
Battery Ground - To be connected to zero potential. All loop current and some quiescent current
flows into this ground terminal.
Switch Hook Detection - A low active LS TTL - compatible logic output.
Ground Key Detection - A low active LS TTL - compatible logic output. This output is enabled
if the DC current into the ring lead exceeds the DC current out of the tip lead and disabled
if this current difference Is below an internally set threshold.
Power Denial - A low active TTL - Compatible logic Input. When enabled, the switch hook detect
(SHD) and ground key detect (GKD) are not necessarily valid, and the relay driver (RD)
output Is disabled.
Ring Command - A low active TTL - Compatible logic Input. When enabled, the relay driver (AD)
output goes low on the ne~high level of the ring sync (RS) input, as long as ~L1C Is not
in the power denial state (PO = 0) or the subscriber is not already off- hook (SHD = 0).
Capacitor #2 - An external capacitor to be connected between this terminal and digital ground.
Prevents false ground key indications from occuring during ring trip detection. Typical value
Is 0.1511F, 10V. This capacitor Is not used if ground key function is not required and (Pin 17)
may be left open or connected to digital ground.
The analog output of the spare operational amplifier. The output vollage swing is typically ±5V.
The Inverting analog Input of the spare operational amplifier.
The non-inverting analog input of the spare operational amplifier.
Receive Input, Four Wire Side - A high impedance analog input which is internally biased:
Capacitive coupling to this input is required. AC signals appearing at this input differentially
drive the Tip feed and Ring feed terminals, which in turn drive tip and ring through
300 Ohms of feed resistance on each side of the line.
Capacitor #4 - An external capacitor to be connected between this terminal and analog
ground. This capacitor prevents false ground key indication and false ring trip detection
from occurring when longitudinal currents are induced onto the subscriber loop from near
by power lines and other noise sources. This capacitor is also required for the proper
operation of ring trip detection. Typical value is 0.511F,to 1.0llF, 20V. This capacitor should
be non polarized.
Analog Ground - To be connected to zero potential and serves as a reference for the transmit
output [fX) and receive Input (RX) terminals.
Transmit Output, Four Wire Side - A low impedance analog output which represents the
differential voltage across Tip and Ring. Transhybrld balancing must be performed (using
the SLiC microcircuit's spare op amp) beyond this output to completely implement two to four
wire conversion. This output is unbalanced and referenced to analog ground. Since the DC level
of this output varies with loop current, capacitive coupling to the next stage Is essential.
No Internal Connection.

1,8,15,22

NC

NOTE: All grounds (AG. BG. & OG) must be applied before Ve+ or VB-' Failure
separate grounds off a line card, the AG must be applied first.

to do so may result In premature failure of the part. If a usef wishes to run

9-100

HC-5504DLC
Applications Diagram 1
TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC

BALANCE NETWORK

.XI;2~,____~=-__~~CI'c~

TIP
slIe
HC-5504DLC

TXf"'------>H
20

{ .'N

OPAMP

-IN«';:.'--'-+---i-,

SUBSCRIBER
lOOP

OUT

I"~'-----t~===t_1

cz 1n

CJ 5

C2

TYPICAL COMPONENT VALUES
C2
C3
C4
CS

=
=
=
=

0.15pF, 10V
0.3pF, 30V
O.SpF to 1.0I1F, 10%, 20V (Should be non polarized)
O.SI1F, 20V

C6 = C7 = 0.511F (10% Match Required) (Note 2)
C8 = O.OlI1F, 100V
C9 = O.OlI1F, 20V, ±20%

Rl = R2 = R3 = lOOk (0.1% Match Required, 1% absolute value) ZB = 0 for 6000 Terminations (Note 2)
RBl = RB2 = RB3 = RB4 = 1500 (0.1% Match Required,l% absolute value)
RSl = RS2 =lkO, typically.
CSl = CS2 = O.lI1F, 200V typically, depending on VRING and line length.
Zl = 150V to 200V transient protection.
PTC used as ring generator ballast.
NOTE1:

Secondary protection diode bridge recommended is a 2A, 200V type.

NOTE 2: To obtain the specified transhybrid loss it is necessary for the three legs of the balance network, C6-Rl and R2 and C7-ZB-R3,
to match in Impedance to within 0.3%. Thus, if C6 and C7 and ll1F each, a 20% match is adequate. It should be noted that the
transmit outpulto C6 see's a -22V step when the loop is closed. Too large a value for C6 may produce an excessively long tran·
sient at the op amp output to the PCM Filter/CODEC.
A 0.5pF and 100kO gives a time constant of SOmsec. The uncommitted op amp output is internally clamped to stay within
±5.5V and also has current limiting protection.
ADDITIONAL INFORMATION IS CONTAINED IN APPLICATION NOTE 549, "THE HC-5S0X TELEPHONE SLlCs"
BY GEOFF PHILLIPS

Overvoltage Protection and
Longitudinal Current Protection

TABLE 1

The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
High voltage surge conditions are as specified in Table 1.
The SLiC will withstand longitudinal currents up to a
maximum or 30mA RMS, lSmA RMS per leg, without any
performance degradation.

TEST
CONDITION

PEFORMANCE
(MAX)

UNITS

Longitudinal

10l1sRise/

±1 000 (Plastic)

V Peak

Surge

100011s/Fall

±500 (Ceramic)

V Peak

Metallic Surge

10l1sRise/

±1 000 (Plastic)

V Peak

100011 Fall

±500 (Ceramic)

V Peak

T/GND

1OI1S Rise/

±1 000 (Plastic)

V Peak

R/GND

1000118 Fall

±500 (Ceramic)

V Peak

Cycles

PARAMETER

50/60Hz
Current

---

9-101

T/GND

700VRMS

11

R/GND

limited to
10ARMS

(Plastic)

He-550gB

mtHARRIS

Subscriber Line Interface Circuit - SLIC

August 1991

Features

Description

• 01 Monolithic High Voltage Process

The HC-5509B telephone Subscriber Line Interface Circuit
integrates most of the BORSCHT functions on a monolithic
IC. The device is manufactured in a Dielectric Isolation (01)
process and is designed for use as a high voltage interface
between the traditional telephone subscriber pair (Tip and
Ring) and the low voltage filtering and coding/decoding func·
tions of the line card. Together with a secondary protection
diode bridge and ''feed'' resistors, the device will withstand
1000V lightning induced surges, in plastic packages. The
SLiC also maintains specified transmission performance in
the presence of externally induced longitudinal currents. The
BORSCHT functions that the SLiC provides are:
• Battery Feed with Subscriber Loop Current Limiting
• Overvoltage Protection
• Ring Relay Driver
• Supervisory Signaling Functions
• Hybrid Functions (with External Op-Amp)
• Test (or Battery Reversal) Relay Driver

• Compatible with Worldwide PBX and CO
Performance Requirements
• Controlled Supply of Battery Feed Current With
Programmable Current Limit
• Operates with 5 Volt Positive Supply (VB+)
• Internal Ring Relay Driver and a Utility Relay Driver
• High Impedance Mode for Subscriber Loop
• High Temperature Alarm Output
• Low Power Consumption During Standby Functions
• Switch Hook, Ground Key, and Ring Trip Detection
• Selective Power Denial to Subscriber
• Voice Path Active During Power Denial
• On Chip Op-Amp for 2 Wire Impedance Matching

Applications
• Solid State Line Interface Circuit for PBX or Central
Office Systems, Digital Loop Carrier Systems
• Hotel/Motel Switching Systems

In addition, the SLiC provides selective denial of power to
subscriber loops, a programmable subscriber loop current
limit from 20 to 60mA, a thermal shutdown with an alarm
output and line fault protection. Switch hook detection, ring
trip detection and ground key detection functions are also
incorporated in the SLiC device.
The HC-5509B SLiC is available in a 28 pin Dual-in-Line
Ceramic or Plastic package, a 44 pin Plastic Leaded Chip
Carrier, or in a 28 Pin SOIC. It is ideally suited for line card
designs in PBX and CO systems, replacing traditional
transformer solutions.

• Direct Inward Dialing (DID) Trunks
• Voice Messaging PBX's
• High Voltage 2W/4W, 4W/2W Hybrid

Pinouts
HC1-5509B, HC3-5509B,
& HC9P5509B
TOP VIEW

HC4P5509B
TOP VIEW

~~o~~~g~ ~~~

TRUTH TABLE

GKD

PR
PRI

ALM

VTX

ILMT

C2

OUT 1
·IN 1
TIP

RFS

F1

FO

Action

0

0

Normal Loop Feed

0

1

1

0

Power Down Latch
RESET

1

0

Power on RESET

1

1

Loop Power
Denial Active

-RDActive

NiC

TFI

Fl

TF2

FO

VFe

RS

RD

SHD

DG

GKD

PH

TST

PRI

NiC
NiC

VTX

NiC

NiC

C2

ALM

NiC
16 19 2021 22 232425 26 27 28

RING

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright © Harris Corporation 1991

9-102

File Number

2799.1

HC-55098
Functional Diagram
R

L - - - - I sw
TSD

L---------------~GK

DIP OR sOle

9-103

He-5509B
Functional Diagram
R

9-104

HC-5509B
Logic Diagram

TO BIAS

NETWORK

I
I
I _____________ JI
::;:

o

o

~

W
I-

Die Characteristics
Transistor Count .................................. 224
Diode Count •...............••....•••.............. 28
Die Dimensions ......................... 174x120mils
Substrate Potential ............... .. .. . . . ... Connected
Process ......•..........•...• " ........•... Bipolar-DI
Thermal Constants (OC/W)
Sja
Sjc
Ceramic DIP
48
12
Plastic DIP
51
21
PLCC
47
17
SOIC
72
22

9-105

Specifications HC-5509B
Absolute Maximum Ratings (Note 1)

Recommended Operating Conditions

Relay Drivers ................................... -0.5V to +15V
Maximum Supply Voltages (VB+) .•..•.•...••....• -0.5Vto +7V
(VB+)-(VB-) ................. +75V
Storage Temperature Range ...••.•... , •....• -650C to +1500 C
Junction Temperature Ceramic •.•.•...••...••••......• +175 0 C
Junction Temperature Plastic ......................... +150 0 C

Relay Drivers .................................... +5Vto+12V
Positive Power Supply (VB+) .........•..•.•.•..•....• +5V ±5%
Negative Power Supply (VB-) ......•.•..•....••... -42V to -58V
loop Resistance (Rl) ........................ 2000 to 17500'
Operating Temperature Range
HC-5509B-5 ................................ OOC to +750 C
HC-5509B-9 ............................ , -400C to +850 C

*Note: May 8e Extended to 1900n With Application Circuit.

Electrical Specifications Unless Otherwise Slated. Typical Parameters are at TA = +25 0 C. Min-Max Parameters are over Operating

=

Temperature Range. VB- -48V. VB+
6000 2 wire terminating impedance.

= +5V. AG = DG = BG =OV. All AC. Parameters are specified at

A.C. TransmisSion Parameters
PARAMETER

MIN

TYP

MAX

-

100

-

K

20

0

+1.5

-

-

Vpk

SRLLO

26

35

-

dB

ERL

30

40

dB

SRLHI

30

40

-

dB

RX Input Impedance

CONDITIONS
300Hz to 3.4kHz (Note 2)

-

TX Output Impedance
4W Input Overload level

300Hz to 3.4kHz
RL = 12000.6000 Reference

2W Return Loss

Matched for 6000 (Note 2)

2W Longitudinal to Metallic Balance

Per ANSI/IEEE STD 455-1976 (Note 2)

Off Hook

300Hz to 3400Hz

58

63

UNITS

dB

4W Longitudinal Balance
Off Hook

300Hz to 3400Hz (Note 2)

50

55

Low Frequency longitudinal Balance

R.EA. Test Circuit

-

Longitudinal Current Capability

IUNE =.040A TA = +250 C (Note 2)

-

Insertion Loss

OdBm at 1kHz. Referenced 6000

2W/4W

-

4W/2W

-

IUNE = .040A TA = +250 C (Note 2)

4W/4W
Frequency Response

300Hz to 3400Hz (Note 2)
Referenced to Absolute
Level at 1kHz. OdBm Referenced 600

level Linearity

Referenced to -1 OdBm (Note 2)

2Wt04Wand4Wt02W

-

-

+3to-4OdBm
-40 to -50dBm
-50 to -55dBm

dB

-

±.12

dB

±0.02

±0.05

dB

.

dB

±0.3

dB

1

ps

1

ps

-

-

1.5

ps

40

-

dB

-

-

-52

dB

-

5

dBmc

-85

dBmp

-

15

dBm

-

4W/4W

300Hz to 3400Hz

Transhybrid Loss. THL

(Note 2) See Figure 1

C-Message

-

Psophometric

-

3kHz Rat

-

9-106

dB

±0.2

-

-

2Wand4W

±0.2

±0.05

dB

300Hz to 3400Hz

(Note 2)

±0.05

±0.1

300Hz to 3400Hz

Idle Channel Noise

dBmc
mArms

±0.05

4W/2W

Reference level OdBm at 6000

23
30

-

2W/4W

300Hz to 3400Hz (Note 2)

-

-

-

(Note 2)

2W/4W. 4W/2W. 4W/4W

dB
dBmp

-

Absolute Delay

Tolal Harmonic Distortion

-67

Specifications HC-5509B
Electrical Specifications Unless Otherwise Stated, Typical Parameters are at TA = +250 C, Min-Max Parameters are over
Operating Temperature Range. VB- =-48V, VB+ = +5V, AG = DG = BG = OV.AII A.C. Parameters are
specified at 6000 2 wire terminating impedance.

A.C. Transmission Parameters (Continued)
PARAMETERS

CONDITIONS

Power Supply Rejection Ratio

(Note 2)

VB+t02W

30Hz to 200Hz, RL = 6000

MIN

TYP

MAX

UNITS

-

dB

20

29

VB+t04W

20

29

VB-t02W

20

29

VB-t04W

20

29

30

-

dB
dB
dB

VB+t04W

30

-

VB-t02W

20

25

VB-to4W

20

25

-

Ring Sync Pulse Width

50

-

500

~s

MIN

TYP

MAX

UNITS

Limit Range

20

40

60

rnA

Accuracy

10

-

-

%

-

:1:3

:1:5

rnA

30

-

rnA

TIP and RING to Ground

-

Switch Hook Detection Threshold
Ground Key Detection Threshold

VB+t02W

200Hz to 16kHz

dB
dB
dB
dB

D.C. Parameters
PARAMETERS

CONDITIONS

Loop Current Programming

Loop Current During Power Denial

RL=2000

Fault Currents
TIP to Ground

rnA

90

-

-

12

15

rnA

-

TBD

-

rnA

140

-

160

°C

-

TBD

-

rnA

Ring Trip Detection Period

-

100

150

ms

Dial Pulse Distortion

-

0.1

0.5

ms

-

0.2

0.5

V

:1:10

:1:100

~A

RING to Ground

Thermal ALAR M Output

Safe Operating Die Temperature Exceeded

Ring Trip Detection Threshold

VRING = 105VRMS, 'RING = 20Hz

Relay Driver Outputs

rnA

10L (PR) - 60mA,IOL (RD) - 30mA

On Voltage VOL
Off Leakage Current

60

VOH = 13.2V

o
(.)
w

-'
W

I-

TIL/CMOS Logic Inputs
(Fa, F1, RS, TEST, PRI)
Logic 'a' VIL

-

V

2.0

-

0.8

Logic '1' VIH

5.5

V

-

-

:1:100

~A

V

Input Current
(Fa, F1, RS, TEST, PRI)

:;;

OV~VIN~5V

LogiC Outputs

-

0.1

0.5

2.7

-

-

V

-

200

-

mW

VB+ = +5.25V, VB- = -58V, RLOOP = co

-

VB+ = +5.25V, VB- = -58V, RLOOP = co

-6

-

Logic 'a' VOL

ILOAD = 800~A

Logic'1'VOH

ILOAD=40~A

Power Dissipation
On Hook

Relay Drivers Off

IB+
IB-

9-107

6

rnA

-

rnA

Specifications He-5509B
Electrical Specifications Unless Otherwise Stated, Typical Parameters are at TA = +250 C, Min-Max Parameters are over
Operating Temperature Range. VB- = -48V, VB+ = +5V, AG = DG = BG = OV. All A.C. Parameters are
specified at 6000 2 wire terminating impedance.

Uncommited Op Amp Parameters
MIN

TYP

MAX

UNITS

Input Offset Voltage

PARAMETER

CONDITIONS

-

±5

-

mV

Input Offset Current

-

±10

-

nA

1

-

MO

Differential Input Resistance

(Note 2)

Output Voltage Swing

RL=10K

Small Signal GBW

(Note 2)

-

±3
1

Vp_p
MHz

NOTES:
1. Absolute maximum ratings are limiting values, applied Individually,
beyond which the serviceability of the circuit may be impaired. FUnctional
operability under any of these conditions is not necessarily implied.

2. These parameters are controlled by design or process parameters and
are not directly tested. These parameters are characterised upon initial
design release, upon design changes which would affect these
characteristics, and at intervals to assure product quality and specification
compliance.

Pin Descriptions
DIP

PLCC

SYMBOL

1

2

AG

DESCRIPTION
Analog Ground - To be connected to zero potential. Serves as a reference for the transmit output
and receive input terminals.

2

3

VB+

3

4

Cl

Positive Voltage Source - Most Positive Supply.
Capacitor #C1 - An external capacitor to be connected between this terminal and analog ground.
Required for proper operation of the loop current limiting function.

4

B

F1

Function Address #1 - A TIL and CMOS compatible input used with FO function address line to
externally select logic functions. The three selectable functions are mutually exclusive. See Truth
Table on pagel. F1 should be toggled high after power is applied.

5

9

FO

Function Address #0 - A TIL and CMOS compatible input used with F1 function address line to
externally select logic functions. The three selectable functions are mutually exclusive. See Truth
Table on page 1.

e

10

RS

Ring Synchronization Input - A TIL - compatible clock input. The clock is arranged such that a
positive pulse (50 - 500~s) occurs on the zero crossing of the ring voltage source, as it appears at
the RFS terminal. For Tip side injected systems, the RS pulse should occur on the negative going
zero crossing and for Ring injected systems, on the positive going zero crossing. This ensures
that the ring delay activates and deactivates when the instantaneous ring voltage is near zero. If
synchronization is not required, the pin should be tied to +5.

7

11

SHD

Switch Hook Detection - An active low LS TIL compatible logic output. A line supervisory output.

8

12

GKo

Ground Key Detection - An active low LS TTL compatible logic output. A line supervisory output.

9

13

TST

A TTL logiC Input. A low on this pin will set a latch and keep the SLIC in a power down mode until
the proper Fl , FO state Is set and will keep ALM low. See Truth Table on page 1.

10

17

m:r

11

18

ILMT

Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions using a
resistive voltage divider.

A LS TIL compatible active low output which responds to the thermal detector circuit when a safe
operating die temperature has been exceeded. When TST is forced low by an external control
signal, ALM is latched low until the proper Fl, FO state and TST input is brought high. The ALM
can be tied directly to the TST pin to power down the part when a thermal fault is detected and then
reset with FO, Fl. See Truth Table on page 1. It is possible to ignore transient thermal overload
conditions in the SLIC by delaying the response to the TST pin from the ALM. Care must be
exercised In attempting this as continued thermal overstress may reduced component life.

12

19

OUTI

The analog output of the spare operational amplifier.

13

20

-INI

The inverting analog input of the spare operational amplifier.

14

22

TIP

An analog Input connected to the TIP (more positive) side of the subscriber loop through a feed
resistor and ring relay contact. Functions with the RING terminal to receive voice signals from the
telephone and for loop monitoring purpose.

9-108

HC-55098
Pin Descriptions

(Conllnued)
DESCRIPTION

DIP

PLCC

SYMBOL

15

24

RING

An analog input connected to the RING (more negative) side of the subscriber loop through a feed
resistor. Functions with the TIP terminal to receive voice signals from the telephone and for loop
monitoring purposes.

16

25

RFS

Ring Feed Sense - Senses RING side of the loop for Ground Key Detection. During Ring injected
ringing the ring signal at this node is isolated from RF via the ring relay. For Tip injected ringing,
the RF and RFS pins must be shorted .

17

27

VRX

. Receive Input, Four Wire Side - A high impedance analog input. A.C. signals appearing at this input
drive the Tip Feed and Ring Feed amplifiers differentially.

18

31

C2

Capacitor #2 - An external capacitor to be connected between this terminal and ground. It prevents
fatse ring trip detection from occurring when longitudinal currents are induced onto the subscriber
loop from power lines and other noise sources. This capacitor should be nonpolarized.

19

32

VTX

Transmit Output, Four Wire Side - A low impedance analog output which represents the differential
voltage across TIP and RING Transhybrid balancing must be performed beyond this output to completely implement two to four wire conversion. This output is referenced to analog ground. Since
the D.C. level of this output varies with loop current, capacitive coupling to the next stage is necessary.

20

33

PRI

A TIL compatible Input used to control PRo PRI active High = PR active low.

21

34

PFi

An active low open collector output. Can be used to drive a Polarity Reversal Relay.

22

35

DG

Digital Ground - To be connected to zero potential. Serves as a reference for all digital inputs and
outputs on the SLIC.

23

36

iID

Ring Relay Driver - An active low open collector output. Used to drive a relay that switches ringing
signals onto the 2 wire line.

24

37

VFB

Feedback signal from the tip feed amplifier. To be used In conjunction with transmit output signal
and the spare op-amp to accommodate 2W line impedance matching.

25

38

TF2

Tip Feed - A low impedance analog output connected to the TIP terminal through a feed resistor.
Functions with the RF terminal to provide loop curren~ and to feed voice signals to the telephone
set and to sink longitudinal currents. Must be tied to TF1.

NA

39

TF1

Tie directly to TF2 in the PLCC application.

26

41

RF1

Ring Feed - A low impedance analog output connected to the RING terminal through a feed resistor.
Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and
to sink longitudinal currents. Tie directly to RF2.

NA

42

RF2

Tie directly to RF1 in the PLCC application.

27

43

VB-

The battery voltage source. The most negative supply.

28

44

BG

Battery Ground - To be connected to zero potential. All loop current and some quiescent current
flows into this ground terminal.

5,6,7,

NC

No internal connection.

1,21,
26,23,
30,28,
29,40,
14,15,
16
NOTE: All grounds (AG. BG. DG) must be applied before ,VB+ or VB-. Failure to do so may result In premature failure of the part. If a user wishes to
run separate grounds off a line card, the AG must be applied first.

9-109

HC-5509B

Applications Diagram 1
TYPICAL LINE CIRCUIT APPLICATION WITH THE HC-5509B

FO
RD

Pii

ILlMrr

TIP

VRX+

TF1"

VFB

TF2u

VTX
RF2....

-INI

RF1'"
CS2
OUT1
-

-----+-..:....::=--'---4-1

- - - TOHYBIRD
BALANCE
NETWORK

RING 0 - -.....

J:'"\

ZI PTC

YJ L . . . + - - - - - - +
TYPICAL COMPONENT VALUES

C1
C2
C3
C4
C5

= 0.511F,30V
= 0.5I1F-1.OIlF ±10%, 20V (Should be nonpolarized)

RB1 '" RB2 = RB3 = RB4 = 500 (1% absolute, matching
requirements covered In a Tech Brief)

= 0.0111F, 100V ±20%
= 0.0111F,100V ±20%
= 0.Q1 IIF, 100V ±20%

RS1 = RS2 '" 1kO typically

=

CS1 CS2
length.

=

Z1 150V to 200V transient protector. PTC used as ring generator
ballast.

CAC = 0.511F, 20V
KZo '" 60K, (Zo '" 6000, K '" Scaling Factor = 1 00)
RL1, RL2; Current Limit Setting Resistors

• Secondary protection diode bridge recommended is 3A. 200V
type.

RL1 + RL2 > 90kO
III MIT = (0.6) (RL 1 + RL2)/(200 x RL2), RL1 typically 100kO
KRF = 201<, RF = 2(RB2

+ RB4), K '" Scaling Factor '"

=0.111F, 200V typically, depending on VRing and line

•• TF1, TF2 and RF1, RF2 are on PLCC only and should be
connected together as shown.

100)

NOTE: He-550gB Applications Diagram shows Ring injected ringing configuration. A Balanced or Tip injected configuration may also be used.

Overvoltage Protection
Longitudinal Current Protection

TABLE 2.

The SLiC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and.
power line crosses.
High voltage surge conditions are as specified In Table 2.
The SLiC will withstand longitudinal currents up to a
maximum of 30mArms, 15mArms per leg, without any
performance degradation.

TEST
CONDITION

PEFORMANCE
(MAX)

UNITS

Longitudinal
Surge

1OilS Rlsel
1000lls/Fail

±1 000 (Plastic)
±500 (Ceramic)

Vp_p
Vp_p

Metallic Surge

1OilS Risel

±1 000 (Plastic)

Vp_p

1000llS Fall

±500 (Ceramie)

Vp_p

10llsRIsel
1000llS Fall

±1 000 (Plastic)
±500 (Ceramic)

Vp_p
Vp_p

11
(Plastic)

Cycles

PARAMETER

T/GND
R/GND
50/60Hz
Current
T/GND
R/GND

9-110

700Vrms
Limited to
10Arms

HC-5524

;:;)HARRIS

Subscriber Line Interface Circuit - SLiC

August 1991

Features

Description

• 01 Monolithic High Voltage Process

The HC-5524 telephone Subscriber Line Interface Circuit
integrates most of the.BORSCHT functions on a monolithic
IC. The device is manufactured in a Dielectric Isolation (01)
process and is designed for use as a 24V interface between
the traditional telephone subscriber pair (Tip and Ring) and
the low voltage filtering and coding/decoding functions of the
line card. Together with a secondary protection diode bridge,
the device will withstand 500V induced surges, in plastic
packages. The SLiC also maintains specified transmission
performance in the presence of externally induced longitudinal currents. The BORSCHT functions that the SLiC provides
are:
• Battery Feed with Subscriber Loop Current Limiting
• Overvoltage Protection
• Ring Relay Driver
• Supervisory Signaling Functions

• Compatible with Worldwide PBX and DLC
Performance Requirements
• Controlled Supply of Battery Feed Current With
Programmable Current Limit
• Operates with 5 Volt Positive Supply (VB+)
• Internal Ring Relay Driver and a Utility Relay Driver
• High Impedance Mode for Subscriber Loop
• High Temperature Alarm Output
• Low Power Consumption During Standby Functions
• Switch Hook, Ground Key, and Ring Trip Detection
• Selective Power Denial to Subscriber

• Hybrid Functions (with External Op-Amp)
• Test (or Battery Reversal) Relay Driver

• Voice Path Active During Power Denial
• On Chip Op-Amp for 2 Wire Impedance Matching

In addition, the SLIC provides selective denial of power to
subscriber loops, a programmable subscriber loop current
limit from 20 to 60mA, a thermal shutdown with an alarm
output and line fault protection. Switch hook detection, ring
trip detection and ground key detection functions are also
incorporated in the SLiC device.

Applications
• Solid State Line Interface Circuit for PBX or Digital
Loop Carrier Systems
• Hotel/Motel Switching Systems

The HC-5524 SLiC is available in a 28 pin Dual-in-Line Ceramic or Plastic package, a 44 pin Plastic Leaded Chip Carrier, or In a 28 Pin SOIC. It is ideally suited for line card
designs in PBX and DLC systems, replacing traditional
transformer solutions.

• Direct Inward Dialing (DID) Trunks
• Voice Messaging PBX's
• 2W/4W, 4W/2W Hybrid

Pinouts
HCl-5524, HC3-5524,
& HC9P5524

HC4P5524

:;;

TOP VIEW

o
(.)

TOP VIEW

....
w

W
I-

TFI
TF2

N/C

FI

VF8

TRUTH TABLE

ALM
ILMT
OUT I

-INI

Fl

FO

Action

0

0

Normal Loop Feed

0

1

RDActive

1

0

RS

RD

SHD

DG

PR

Power Down Latch

RESET

PAl

N/C
N/C

VTX
C2

N/C

N/C

ALM

1

0

Power on RESET

1

1

Loop Power
Denial Active

N/C

18 19 20 21 22 232425262728

TIP

CAUTION: These devices ate sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

9-111

File Number

2798.1

HC-5524
Functional Diagram

DIP OR SOIC

9-112

HC-55;22~4~_________________________
" gram
Func tl"onal 0 la

PLCC

9-113

HC-5524
Logic Diagram

TO BIAS
NETWORK

I
I
I_ _ _ _ _ _ _ _ _ _ _ _ _ _ I1

Die Characteristics
Transistor Count ..........•.............•......... 224
Diode Count ......................................• 28
Die Dimensions .....•......•............ 174 x 120 mils
Substrate Potential ...........•............. Connected
Process ....•............................... Bipolar-DI
Thermal Constants (OC/W)
aja
ajc
Ceramic DIP
48
12
Plastic DIP
51
21
PlCC
47
17
SOIC
72
22

9-114

Specifications HC-5524
Absolute Maximum Ratings (Note 1)

Recommended Operating Conditions

Relay Drivers •.•.•.....•••..•....•.......•...... -0.5V to +15V
Maximum Supply Voltages (VB+) ..•.•............ -0.5Vto +7V
(VB+)-(VB-) .............•... +40V
Storage Temperature Range ....•.•........•. -650 C to +150 0 C
Junction Temperature Ceramic ...•....•...•..••....... +175 0 C
Junction Temperature Plastic ....•........•...•....... +150 0 C

Relay Drivers •....•...•...•.•...•.•...•......•... +5Vto +12V
Positive Power Supply (VB+) .....••••..••..••.••...•. +5V ±5%
Negative Power Supply (VB-) •..•.....•........... -20V to -2BV
Operating Temperature Range
HC-5524-5 ..............•................... 00C to +750 C
HC-5524-9 .......................•....... -40 0 C to +85 0 C

= +250 C, VB+ = +5V, VB- = -24V, AG =
DG = BG = OV. Min-Max Parameters are Over Operating Positive and Negative Ballery Voltages and Over
the Industrial Temperature Range. All Parameters are Specified at 600n 2-Wire Terminating Impedance.

Electrical Specifications Unless Otherwise Slated, Typical Parameters are at TA

A.C. Transmission Parameters
PARAMETER
RX Input Impedance

CONDITIONS
300Hz to 3.4kHz (Note 2)

TX Output Impedance

MIN

TYP

MAX

-

100

-

UNITS

K

-

20

n

+1.0

-

-

Vpk

26
30
30

35
40
40

-

dB
dB
dB

63

-

dB

4W Input Overload Level

300Hz to 3.4kHz, 600n Reference

2W Return Loss
SRLLO
ERL
SRLHI'

Matched for 600n (Note 2)

2W Longitudinal to Metallic Balance
Off Hook
4W Longitudinal Balance
Off Hook

Per ANSI/IEEE STD 455-1976 (Note 2)
300Hz to 3400Hz

58

300Hz to 3400Hz (Note 2)

50

55

-

dB

Low Frequency Longitudinal Balance

R.E.A. Test Circuit

-

-80

-67

dBmp

-

10

23

dBrnc

-

40

mArms

-

±0.05

±0.2

dB

±0.05

±0.2

dB

-

±0.2

dB

±0.02

±0.06

dB

dB

ILINE = 40mA TA = +25 0C (Note 2)
Longitudinal Current Capability

ILINE = 40mA TA = +250 C (Note 2)

Insertion Loss
2W/4W

-1.5BdBm @ 1kHz, Referenced 600n

4W/2W

OdBm @ 1kHz, Referenced 600n

4W/4W

-1.5BdBm @ 1kHz, Referenced 600n

Frequency Response

300Hz to 3400Hz (Note 2)
Referenced to Absolute
Level at1 kHz, OdBm Referenced 600

Level Linearity

Referenced to -1 Od Bm (Note 2)

2W to 4W and 4W to 2W

+3to-40dBm

-

-

±0.08

-40 to -50dBm

-

-

±0.12

dB

-50 to -55dBm

-

-

±0.3

dB

Absolute Delay

(Note 2)

2W/4W

300Hz to 3400Hz

4W/2W

300Hz to 3400Hz

4W/4W

300Hz to 3400Hz

Total Harmonic Distortion

Reference Level OdBm at 600n

-

1

~s

-

-

1

~s

0.95

1.5

~s

-

-

-50

dB

-

-

5

dBrnc

Psophometric

-85

dBmp

3kHz Flat

-

-

16

dBrn

2W/4W, 4W/2W, 4W/4W

300Hz to 3400Hz (Note 2)

Idle Channel Noise

(Note 2)

2Wand4W

Open Loop Voltage (VTIP - VRING)

-

C-Message

VB+

= +5V, VB- =-24V

9-115

15.8

V

Specifications HC-5524
Electrical Specifications Unless Otherwise Slaled, Typical Paramelers are al TA = +2S0C, VB+ = +SV, VB- = -24V, AG =
DG = BG = OV. Min-Max Paramelers are Over Operaling Positive and Negative Battery Voltages and
Over lhe Industrial Temperature Range. All Parameters are Specnied at 600n 2-Wire Terminating Imped-

ance.

A.C. TransmIssIon Parameters (Continued)
PARAMETERS

CONDITIONS

Power Supply Rejection Ratio

(Note 2)

VB+t02W

30Hz to 200Hz, RL = 600n

MIN

TYP

MAX

UNITS

20

40

VB+l04W

20

40

VB-t02W

20

40

VB-to4W

20

SO

-

30

40

-

VB+l04W

20

28

VB-102W

20

50

-

VB-l04W

20

SO

-

dB

Ring Sync Pulse Width

SO

-

SOO

~s

MIN

TYP

MAX

UNITS

Limit Range

20

40

60

mA

Accuracy

10

-

-

%

±4

±7

rnA

30

200Hz 1016kHz

VB+l02W

dB
dB
dB
dB
dB
dB
dB

D.C. Parameters
PARAMETERS

CONDITIONS

Loop Current Programming

Loop Current During Power Denial

RL=200n

Fault Currents

-

120

-

rnA

RING to Ground
TIP and RING to Ground

-

lS0

-

rnA

TIP to Ground

Switch Hook Detection Threshold
Ground Key Detection Threshold
Thermal ALM Output

Sale Operating Die Temperature Exceeded

Ring Trip Deteclion Threshold

VRING = 1OSVRMS, IRING - 20Hz

Ring Trip Detection Period
Dial Pulse Distortion
Relay Driver Outputs

rnA

-

12

lS

rnA

TBD

-

rnA

140

-

160

oC

-

TBD

-

rnA

100

lS0

ms

0.1

O.S

ms

10L (PR) = 60mA,IOL (RD) = 30mA

-

0.2

O.S

V

-

±10

±100

~

Logic '0' VIL

-

V

2.0

-

O.B

Logic'l'VIH

S.S

V

-

-

±100

~

V

On Voltage VOL

Off Leakage Current

VOH=13.2V

TILJCMOS Logic Inputs
(FO, Fl, RS, TST, PRI)

Input Current
(FO, Fl, RS, TST, PRI)

OV,$,VIN!>SV

Logic Outputs
Logic '0' VOL

ILOAD=800~

Logic '1' VOH

ILOAD=40~A

Power DiSSipation
On Hook

Relay Drivers Off

IB+

VB+ = +S.2SV, VB- = -28V, RLOOP =

00

IB-

VB+ = +S.2SV, VB- = -28V, RLOOP =

00

IB+

VB+ = +SV, VB- = -24V, RLOOP = 600n

IB-

VB+ = +SV, VB- = -24V, RLOOP = 600n

9-116

-

0.1

O.S

2.7

-

-

V

-

60

-

mW

-

-

4

rnA

-4

-

-

rnA

-

3

6

rnA

-28

-24

-

rnA

Specifications HC-5524
Electrical Specifications Unless Otherwise Stated, Typical Parametsrs are at TA = +250 C, VB+ = +5V, VB- = -24V, AG =
DG = BG = OV. Min-Max Parameters are Over Operating Positive and Negative Battery Voltages and
Over the Industrial Temperature Range. All Parameters are Specified at 600n 2-Wire Terminating
Impedance.

Uncommlted Op Amp Parameters
MIN

TYP

MAX

UNITS

Input Offset Voltage

CONDITIONS

-

±5

-

mV

Input Offset Current

-

±10

-

nA

(Note 2)

-

1

-

Mn

Output Voltage Swing

RL=10K

-

±3

-

Vp_p

Small Signal GBW

(Note 2)

-

1

-

MHz

PARAMETER

Differenliallnput Resistance

NOTES:

1. Absolute maximum ratings are limiting values, applied Individually.
beyond which the serviceability of tho circuit may be impaired. Functional

2. These parameters are controlled by design or process parameters and are

operability under any of thase conditions is nol necessarily implied.

not directly tosted. These parameters are characterized upon Initial
design release, upon deSign changes which would affect these
characteristics, and at intervals to assure product quality and specification
compliance.

Pin Descriptions
DIP

PLCC

SYMBOL

1

2

AG

DESCRIPTION
Analog Ground - To be connected to zero potential. Serves as a reference for the transmit output
and receive input terminals.
Positive Voltage Source - Most Posilive Supply.

2

3

VB+

3

4

C1

Capacitor #C1 - An external capacitor to be connected between this terminal and analog ground.
Required for proper operation of the loop current limiting function.

4

8

F1

Funclion Address #1 - A TIL and CMOS compatible Input used with FO function address line to
extsrnally select logiC functions. The three selectable functions are mutually exclusive. See Truth
Table on page1. F1 should be toggled high after power is applied.

5

9

FO

Function Address #0 - A TIL and CMOS compatible input used with F1 function address line to
extemally select logic functions. The three selectable functions are mutually exclusive. See Truth
Table on page 1.

6

10

RS

Ring Synchronizalion Input - A TIL - compatible clock input The clock is arranged such that a
positive pulse (50 - 500(ls) occurs on the zero crossing of the ring voltage source, as it appears at
the RFS terminal. For Tip side injected systems, the RS pulse should occur on the negative going
zero crossing and for Ring injected systems, on the positive going zero crossing. This ensures
that the ring delay activates and deactivates when the instantaneous ring voltage is near zero. 11
synchronization Is not required, the pin should be tied to +5.

7

11

SHD

8

12

GKD

Switch Hook Detection - An active low LS TIL compatible logic output A line supervisory output
Ground Key Detsction - An active low LS TIL compatible logic output A line supervisory output

9

13

TST

A TIL logic input A low on this pin will set a latch and keep the SUC in a power down mode until
the proper F1, FO state is set and will keep ALM low. See Truth Table on page 1.

10

17

ALM

A LS TIL compatible active low output which responds to the thermal detector circuit when a safe
operating die temperature has been exceeded. When TST is forced low by an external control
signal, ALM is latched low until the proper F1, FO state and TST input Is brought high. The ALM
can be tied directly to the TST pin to power down the part when a thermal fault is deteclsd and then
reset with FO, F1. See Truth Table on page 1. 11 is possible to Ignore transient thermal ove~oad
conditions in the SLiC by delaying the response to the TST pin from the ALM. Care must be
exercised in attempting this as continued thermal overstress may reduce component life.

11

18

ILMT

Loop Current Umit - Voltage on this pin sets the short loop current limiting conditions using a
resistive voltage divider.

12

19

OUT1

The analog output of the spare operational amplifier.

13

20

-IN1

The inverting analog input of the spare operational amplifier.

14

22

TIP

An analog input connected to the TIP (more positive) side of the subscriber loop through a feed
resistor and ring relay contact. Functions with the RING tsrminal to receive voice signals from the
telephone and for loop monitoring purposes.

9-117

HC-5524
Pin Descriptions

(Continued)

DIP

PLCC

SYMBOL

15

24

RING

An analog Input connected to the RING (more negative) side of the subscriber loop through a feed
resistor. Functions with the TIP terminal to receive voice signals from the telephone and for loop
monitoring purposes.

16

25

RFS

Ring Feed Sense - Senses RING side of the loop for Ground Key Detection. During Ring injected
ringing the ring signal at this node is isolated from RF via the ring relay. For Tip Injected ringing,
the RF and RFS pins must be shorted.

17

27

VRX

Receive Inpu\, Four Wire Side - A high Impedance analog Input. A.C. signals appearing at this Input
drive the Tip Feed and Ring Feed amplifiers differentially.

18

31

C2

Capacitor #2 - An external capacitor to be connected between this terminal and ground. It prevents
false ring trip detection from occurring when longitudinal currents are induced onto the subscriber
loop from power lines and other noise sources. This capaCitor should be nonpolarlzed.

19

32

VTX

Transmit Output, Four Wire Side - A low impedance analog output which represents the differential
voltage across TIP and RING Transhybrid balancing must be performed beyond this output to completely Implemenltwo to four wire conversion. This output is referenced to analog ground. Since
the D.C. level of this output varies with loop curren\, capacitive coupling to the next stage is necessary.

20

33

PRI

A TIL compatible input used to control PRo PRI active High = PR active low.

21

34

PR

An active low open collector output. Can be used to drive a Polarity Reversal Relay.

22

35

DG

Digital Ground - To be connected to zero potential. Serves as a reference for all digital Inputs and
outputs on the SLiC.

23

36

RD

Ring Relay Driver - An active low open collector output. Used to drive a relay that switches ringing
signals onto the 2 wire line.

24

37

VFB*

Feedback input to the tip feed amplifier may be used In conjunction with transmit output signal
and the spare op-amp 10 accommodate 2W line impedance matching. (This Is not used in the typical
applications circuit on page 8.)

25

38

TF2

Tip Feed - A low impedance analog output connected 10 the TIP terminal through a feed resistor.
Functions with the RF terminal to provide loop curren\, and to feed voice signals to the telephone
set and 10 sink longitudinal currents. Must be tied to TF1.

NA

39

TF1

Tie directly 10 TF2 in the PLCC application.

26

41

RF1

Ring Feed - A low Impedance analog output connected to the RING terminal through a feed resistor.
Functions with the TF terminal to provide loop current, feed voice signals 10 the telephone set, and
to sink longitudinal currents. Tie directly to RF2.

NA

42

RF2

Tie direcHy 10 RF1 In the PLCC application.

27

43

VB-

The battery voltage source. The most negative supply.

28

44

BG

Battery Ground - To be connected to zero potential. All loop current and some quiescent current
flows Into this ground terminal.

5,6,7,

NC

No Internal connection.

DESCRIPTION

1,21,
26,23,
30,28,
29,40,
14,15,
16
NOTE: All grounds (AG. BG. OG) must be applied before VB+ or VB-. Failure to do so may result In premature failure of the part. If a user wishes to

run separate grounds off a line card, the AG must be applied first.
• Although not used In the typical applications circuit. VFB may be used In matching complex 2-wlre impedances.

9-118

HC-5524

Applications Diagram 1
TYPICAL LINE CIRCUIT APPLICATION WITH THE HC-5524
+5V

Fa
RD

TIP

PR

IUMIT

TIP

VAX+

TF1 u

VFB

Tf2u

VTX
RF2 u

·IN1

AF1 u

oun
TO HYBIRD
BALANCE
NETWORK

-----+-.:...::=--'--4-1

RING 0 - -....

-~

TYPICAL COMPONENT

=

=

=

==

RBl
RB2
500 (1 % absolute, matching requirements cov·
ered in a Tech Briel)
RSl = RS2 = lkO typically
CSl = CS2 = O.lI1F, 200V typically, depending on VRing and line
length.
Zl = 150V to 200V transient protector. PTC used as ring generator
ballast.

=

• Secondary protection diode bridge recommended is 3A, 200V
type.

RL 1+RL2 > 90kO
ILiMIT = (.6) (RL1+RL2)/(RL2X200), RL1 typically.l00kO
KRF

VALUE~ 5V

=

Cl = 0.511F,20V
C2 = 0.5I1F-1.oIlF ±10%, 50V (Should be non polarized)
C3 = 0.01 JiF, 50V ±20%
C4 = O.OlI1F, SOV ±20%
C5 = O.OlI1F, 50V ±20%
CAC = 0.511F, 20V
KZo 50K, (Zo 6000, K Scaling Factor 100)
RL 1, RL2; Current Limit Setting Resistors

•• TF1, TF2 and RF1, RF2 are on PLCC only and should be
connected together as shown.

= 20K, RF = 2(RB1+RB2), K = Scaling Factor = 100)

NOTE: HC-5524 Applications Diagram shows Ring injected ringing configuration. A Balanced or Tip injected configuration may also be used,

::;:

Overvoltage Protection
Longitudinal Current Protection

o

ow

TABLE 2.

-'
w

The SliC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.
High voltage surge conditions are as specified in Table 2.
The SliC will withstand longitudinal currents up to a
maximum of 40mArms, 20mArms per leg, without any
performance degradation.
NOTE: OVBrvoltage. Surge Condition Limits, listed In Table 2, may be
increased with use of additional secondary protection to Tip & Ring.

9-119

PARAMETER

TEST
CONDITION

PEFORMANCE
(MAX)

t-

UNITS

lOllS Risel

±500 (Plastic)

10001ls/Fall

±250 (Ceramic)

lOllsRlsel
lOOOIiS Fall

±500 (Plastic)
±250 (Ceramic)

Vp_p

T/GND

lOllS Risel

R/GND

lOOOIiS Fall

±500 (Plastic)
±250 (Ceramic)

Vp_p
Vp_p

11
(Plastic)

Cycles

Longitudinal
Surge
Metallic Surge

SO/60Hz
Current
T/GND
R/GND

350Vrms
Limited to
10Arms

Vp_p
Vp_p

Vp_p

I)

HC-5560

HARRIS

PCM Transcoder

August 1991

Features

Description

• Single 5V Supply ••••••••••••••••••••••• 10mA Typ.

The HC-5560 digital line transcoder provides encoding and
decoding of pseudo ternary line code substitution schemes.
Unlike other industry standard transcoders, the HC-5560
provides four worldwide compatible mode selectable code
substitution schemes, including HDB3 (High Density Bipolar
3), B6ZS, B8ZS (Bipolar with 6 or 8 zero Substitution) and
AMI (Altemate Mark Inversion).

• Mode Selectable Coding Including:
~ AMI (Tl, T1C)
~
~

B8ZS (Tl)
HDB3 (PCM30)

• North American and European Compatibility

The HC-5560 Is fabricated in CMOS and operates from a
single 5V supply. All inputs and outputs are TIL compatible.
The HC-5560 is available in 20 pin dualHn-line plastic pack·
ages over the commercial temperature range, OOC to +7OOC.

• Simultaneous Encoding and Decoding
• Asynchronous Operation
• Loop Back Control

Application Note ,*573, "The HC-5560 Digital Line
Transcoder," by D.J. Donovan is available.

• Transmission Error Detection
• Alarm Indication Signal
• Replaces MJ1440, MJ147l and TCM2201
Transcoders

Applications
• North American and European PCM Transmission
Lines where Pseudo Ternary, Line ,Code Substitution
Schemes are Desired
• Any Equipment that Interfaces Tl, Tl C, T2 or PCM30
Lines Including Multiplexers, Channel Service Units,
(CSUs) Echo Cancellors, Digital Cross-Connects
(DSXs), T1 Compressors, etc.

Functional Diagram

Pinout
HC-5560

TOP VIEW
MODE
SELECT

FORCEAIS

1

MODE SELECT 1

2

OUTPUT ENABLE

NRZ DATA IN

3

RESET

CLKENC

4

OUTl

MODE SELECT 2

5

OUT2

NRZ DATA OUT

6

'BIN

CLKDEC

7

LOOP TEST ENABLE

RESET AlS

8

AIN

,0-----....------........
.0---.....---1--------.

HRZ DATA I. ~~.r-L-_..s...,

CLOCK
(ENCODER)

iiiiPii"f
ffiiti

-,._ _ _-..r-

~+--++---+-+--...()OUTZ

LOOP TEST
ENABLE
MRZ DATA

OUT

AIN

CLOCK
~S

>-+-+----()CLOCK

~-~~---+-+--~onl

·,No-----...J

ERROR

OLOO.o--------t-+-+I...._ _
(OEOODER)
~o------~

CAUTION: These device. are .ensaive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

9-120

ERROR
~

.....- - - _ O A I .

File Number

2887

HC-5560

FuncvonalDescripvon
The HC-5560 TRANSCODER can be divided into six sections:
transmission (coding), reception (decoding), error detection,
all ones detection, testing functions, and output controls.
The transmitter codes a non-return to zero (NRZ) binary
unipolar input signal (NRZ Data In) into two binary unipolar
return to zero (RZ) output signals (Out 1, Out 2). These output
signals represent the NRZ data stream modified according to
the selected encoding scheme (i.e., AMI, B8ZS, B6ZS, HDB3)
and are extemally mixed together (usually via a transistor or
transformer network) to create a temary bipolar signal for driving
transmission lines.

The receiver accepts as its input the ternary data from the
transmission line that has been externally split into two binary
unipolar return to zero signals (Ain and Bin). These signals are
decoded, according to the rules of the selected line code into
one binary unipolar NRZ output signal (NRZ Data Out).
The encoder and decoder sections of the chip perform
independently (excluding loopback condition) and may
operate simultaneously.
The Error output signal is active high for one cycle of ClK DEC
upon the detection of any bipolarviolation in the received Ain
and Bin signals that is not part of the selected line coding
scheme. The bipolar violation is not removed, however, and
shows up as a pulse in the NRZ Data Out signal. In addition,
the Error output signal monitors the received Ain and Bin
signals for a string of zeros that violates the maximum consecutive zeros allowed for the selected line coding scheme

(i.e., 15 for AMI, 8 for B8ZS, 6 for B6ZS, and 4 for HDB3). In
the event that an excessive amount of zeros is detected, the
Error output signal will be active high for one cycle of ClK
DEC during the zero that exceeds the maximum number. In
the case that a high level should simultaneously appear on
both received input signals Ain and Bin a logical one is
assumed and appears on the NRZ Data Out stream with the
Error output active.
An input signal received at inputs Ain and Bin that consists of
all ones (or marks) is detected and signaled by a high level at
the Alarm Indication Signal (AIS) output This is also known as
Blue Code. The AIS output is setto a high level when less than
three zeros are received during one period of Reset AIS
immediately followed by another period of Reset AIS containing
less than three zeros. The AIS output is reset to a low level
upon the first period of Reset AIS containing 3 or more
zeros.
A logic high level on lTE enables a loopback condition where
Out 1 is intemally connected to Ain and Out 2 is intemally connected to Bin (this disables inputs Ain and Bin to external
signals). In this condition, NRZ Data In appears at NRZ Data
Out (delayed by the amount of clock cycles it takes to encode
and decode the selected line code). A decode clock must be
supplied for this operation.
The output controls are Output Enable and Force AIS. These
pins allow normal operation, force Out 1 and Out 2 to zero,
or force Out 1 and Out 2 to output all ones (AIS condition).

:;;

o

ow

-'

W
I-

9-121

HC-5560

Pin Assignments
PIN
NO.

2,5

FUNCTION

DESCRIPTION

Force AIS

Pin 19 must be at logic '0' to enable this pin. A logic '1' on this pin forces Out 1 and Out 2 to all
ones. A logic 'a' on this pin allows normal operation.

Mode Select 1,
Mode Select 2

MS1

MS2

0
0

()

1
1

0

1
1

func.tions.as
AMI
BBZS
B6ZS
HDB3

3

NRZ Data In

4

ClK ENC

6

NRZ Data Out

7

ClK DEC

B,9

Reset AIS, AIS

10

VSS

Ground reference.

11

Error

A logic '1' indicates that a violation of the line coding scheme has been decoded.

12

Clock

"OR" function of Ain and Bin for clock regeneration when pin 14 is at 10gic'O', "OR"function
of Out 1 and Out 2 when pin 14 is at logic '1'.

13,15

Input data to be encoded into ternary form. The data is clocked by the negative going edge
of ClK ENC.
Clock encoder, clock for encoding data at NRZ Data In.
Decoded data from ternary inputs Ain and Bin.
Clock decoder, clock for decoding ternary data on inputs Ain and Bin.
logic '0' on Reset AIS resets a decoded zero counter and either resets AIS output to zero
provided 3 or more zeros have been decoded in the preceding ~ period or sets AIS
to '1' if less than 3 zeros have been decoded in the preceding two Reset AIS periods. A
period of Reset AIS is defined from the bitfollowing trul,bit during which ResetAIS makes a
high to low transition to the·bit during which Reset AIS makes the next high to low
transition.

Inputs representing the recieved PCM signal. Ain=' 1, represents a positive going '1' and
Bin='l' represents a negative going '1'. Ain and Bin are sampled by the positive going edge
of ClK DEC. Ain and Bin may be interchanged.

14

lTE

loop Test Enable, this pin selects between normal and loop back operation. A logic '0'
selects normal operation where encode and decode are independent and asynchronous. A
logic '1' selects a loop back condition where Out 1 is internally connected to Ain and Out2 is
internally connected to Bin. A decode clock must be supplied.

16,17

Out 1, Out 2

Outputs representing the ternary encoded NRZ Data In signal for line transmission. Outl and
Out 2 are in return to zero form and are clocked out on the positive going edge of ClK ENC.
The length of Out 1 and Out 2 is set by the length of the positive clock pulse.

18

Reset

A logic '0' on this pin resets all internal registers to zero. A logic '1' allows normal operation
of all internal registers.

19

Output Enable

A logic '1' on this pin forces outputs Out 1 and Out 2 to zero. A logic '0' allows normal
'operation.

20

VDD

Power to chip.

9-122

Specifications HC-5560
Static Electrical Specifications Unless Otherwise Specified. Typical parameters at +250 C.
Min-Max parameters are over operating temperature range. Vee = +5V.
SYMBOL

SPECIFICATION
Quiescent Device Current

MIN

100

10

Out 1, Out 2 low (Sink) Current

UNITS
uA
rnA

lOll

3.2

rnA

IOL2

2

rnA

IOH

2

rnA

= 0.4V)
low (Sink) Current

All Other Outputs

(VOL

MAX
100

Operating Device Current

(VOL

TYP

= 0.8V)

All outputs High (Source) Current

= 4.0V)

(VOH

Input Low Current

IlL

10

uA

Input High Current

IIH

10

uA

Input Low Voltage

VIL

0.8

V

Input High Voltage

VIH

Input Capacitance

CIN

V

2.4
8

pF

Dynamic Electrical Specifications Unless otherwise Specified. Typical parameters at +250 C.
Min-Max parameters are over operating temperature range. Vee = +5V.
SYMBOL

SPECIFICATION
CLK ENC. CLK DEC Input Frequency

lei

CLK ENC. CLK DEC Rise Time (1.544 MHz)

trel

Fall Time

Rise Time 12.048 MHz)

tIel
trel

Fall Time

tfcl

Rise Time (6.3212 MHz)
Fall Time

trel
tfcl

Rise Time (8.448 MHz)

trel

Fall Time

tIel

NRZ-Data In to CLK ENC Data Setup Time
Data Hold Time

AIN. 81N to CLK DEC Data Setup Time
Data Hold Time

CLK ENC to Out 1. Out 2
Out 1. Out 2 Pulse Width (CLK ENC Duty Cycle

MIN

TYP

10
10
10
10
10
10
5
5

MAX

UNITS

FIG.

8.5

MHz

60
60
40
40
30
30
10
10

ns
ns
ns
ns
ns
ns
ns
ns

1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2

ts
tH

20
20

ns
ns

1
1

ts
tH

15

ns
ns

2
2

ns

1

ns
ns
ns
ns

1
1
1
1

5

too

23

tw
tw
tw
tw

324
224
79
58

80

= 50%)

=
=

lei
1.544 MHz
lei 2.048 MHz
lei = 6.3212 MHz
lei 8.448 MHz

=

CLK DEC to NRZ-Data Out.

ns

2

ts2

35

25

ns

3

th2

20

ns

3

ts2

0

ns

3

too

54

---

Setup Time

elK DEC to Reset AIS

- - - = '0'

Hold Time of Reset AIS

---

Setup Time Reset AIS

= '1' to CLK DEC

---

Reset AIS to AIS output

eLK DEC to Error output

9-123

tpd5

42

ns

3

tpd4

62

ns

3

::iE

o
ow

--'

W
I-

HC-5560
Line Code Descriptions
AMI, Alternate Mark Inversion, is used primarily in North
American Tl (1.544 MHz) and Tl C (3.152 MHz) carriers.
Zeros are coded as the absence of a pulse and one's are
coded alternately as positive or negative pulses. This type of
coding reduces the average voltage level to zero to eliminate
DC spectral components, thereby eliminating DC wander. To
simplify timing recovery, logic l's are encoded with 50% duty
cycle pulses.

1. If the immediate preceding pulse is of (-) polarity, then
code each group of 8 zeros as 000-+ O+-.
2. If the immediate preceding pulse is of (+) polarity then
code each group of 8 zeros as 000+- 0-+.
e.g.
PCM Code

r--- 8 - - ,
1 010 0 0 0 0 000 1 1 0
000-+0+-

e.g.

B8ZS (-)

PCM Code 0 0 0 1 0 1 1 1 0 1 0 0 0 0 0 1
AMI Code

000+-0-+

B8ZS (+)
To facilitate timing maintenance at regenerative repeaters
along a transmission path, a minimum pulse density of logic
l's is required. Using AMI, there is a possibility of long
strings of zeros and the required density may not always
exist, leading to timing jitter and therefore higher error
rates.
A method for insuring minimum logic 1 density by substituting
bipolar code in place of strings of O's is called BNZS or
Bipolarwith N Zero Substitution. B6ZS is used commonly in
North American T2 (6.3212MHz) carriers. For every string of
6 zeros, bipolar code is substituted according to the following
rule;
If the immediate preceding pulse is of (-) polarity,
then code each group of 6 zeros as 0 -+ O+-, and if
the immediate preceding pulse is of(+) polarity, code
each group of 6 zeros as O+- 0-+. One can see the
consecutive logic 1 pulses of the same polarity violate
the AMI coding scheme.
e.g.
PCM Code

V

Another coding scheme is HDB3, high density bipolar3 used
primarily in Europe for 2.048 MHz and 8.448 MHz carriers.
This code is similar to 8NZS in that it substitutes bipolar code
for 4 consecutive zeros according to the following rule;
1. Ifthe polarity of the immediate preceding pulse is (-) and
there have been an odd (even) number of logic 1 pulses
since the last substitution, each group of 4 consecutive
zeros is coded as 000-(+00+).
2. Ifthe polarity ofthe immediate preceding pulse is (+) then
the substitution is 000+(-00-) for odd (even) number of
logic 1 pulses since the last substitution.
e.g.

1""4~

,--6---,
PCM Code

000101110000001

=Violation

00-

000+

~
V

+ 0 0+

HDB3 (-)

0+-0- +

B6ZS (+)

r-4,

0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 1
000

~
v

=Violation

The BNZS coding schemes, in addition to eliminating DC
wander, minimize timing jitter and allow a line error monitoring capability.

0-+0+-

B6ZS (-)

V

HDB3 (+)

V

V

B8ZS is used commonly in North American T1 (1.544 MHz)
and T1 C (3,152 MHz) carriers. For every string of 8 zeros,
bipolar code is substituted according to the following
rules;

9-124

=Violation

The 3 in HDB3 refers to the coding format that precludes
strings of zeros greater than 3. Note that violations are
produced only in the fourth bit location of the' substitution
code and that successive substitutions produce alternate
polarity violations.

HC-5560
Application Diagram

FROM CODEC OR
TRANSCODER

OUT'

II

ENCODER
ENCODER CLOCK

0--....--1

ClK ENe

OUT 2

FORCE AIS

MS ,

LTE

MS 2 t - - - . . . , o

CONTROL

RESET

CLOCK

0 - -....-1 OUTPUT

RESET AIS

ENABLE

1--....-0
1--....-0

}

~

"T2'T1C'

PCM 30

LINE OUTPUT

MODE SELECT
LOGIC INPUTS
CLOCK RECOVERY

ALARM CLOCK

A I S I - - ' - - o ALARM
ERROR

LIN~II

INP~

~---I

AIN

1--"'-0

}

ERROR

ERROR
MONITORS

NRZ Data
DECODER

Outt--_.--O TO CODEC OR TRANSCODER

HC-5560

Die Characteristics
Transistor Count ................................. 4322
Die Dimensions. . . • . . . . . . . . . . • • . . . • • . . . • • . .. 119 x 133
Substrate Potential .......•....•...••....•...•.••... +V
Process ....•.....••.•••...•.....•.....•.• SAJI CMOS
Thermal Constants (OC/W)
Oja
Ojc
Plastic DIP, HC-5560
67
25

9-125

MS'

MS2

o
o

o

,

o

SELECTS
AMI
B82S
B6ZS
HDB3

HC-5560
Timing Waveforms
~------~Cl------~~

ClK ENC

-------.1

ts

I::

r---------------r---r.--

,

...L.

NRZ Data In

too [1--___---,
Out 1, Out 2

L

----------------------....Ji

t-

tw----l

FIGURE 1. TRANSMITTER (CODER) TIMING WAVEFORMS

AIN. BIN

\

. elOCK

L

f

ttDD

f

NRZ Data Out

\

FIGURE 2. RECEIVER (DECODER) TIMING WAVEFORMS

~'------r

ClK DEC - - - - - -

J~~ll--I-

RESET AIS

t~d1
AISOUTPUT

I

t--

rd~
ERROR OUTPUT_ _ _ _. . J x , r - - - - - - -

FIGURE 3. RESET AIS INPUT, AIS OUTPUT, ERROR OUTPUT

9-126

HC-5560

ClK DEC
ResetAIS

u

u

u

U

L

NRZ Data Out
AIS
FIGURE4.
Two consecutive periods of Reset AIS, each containing less than three zeros, sets AIS to a logic '1' and
remains in a logic '" state until a period of Reset AIS contains three or more zeros.

ClK DEC
ResmAIS

lJr----------,ur----------'Ur----------'U~----------~Ur----------~L_

NRZ Data Out
AIS
FIGURES.
Zeros which occur during a high to low transition of ResetAIS are counted with the zeros that occured before
the high to low transition.

NRZ Data IN
ClK ENC

n

OUT 1

n

I

AMI

n

fI

OUT2

n

OUT 1

n

n

HDB3
OUT2

n

tsLrsL-.

Isl
Q

Isl

:;;;
0

u

w

-'

I

n

OUT 1

I
I

B6ZS

I
I

OUT2

i

W
l-

n

n

f5L--.lS1
~

rLJsl

I

h

OUT 1

I
I

B8ZS
OUT2

n
n

~

n

ISl

!--3\1, cycles-':
I

~51h cycles

-----.J

FIGURE 6. ENCODE TIMING AND DELAY
Data is clocked on the negative edge of ClK ENC and appears on Out 1, and Out2. Out 1 and Out2 are
interchangable. Bipolar violations and all other pulses inserted by the line coding scheme to encode
strings of zeros are labled with an "S".

9-127

r

HC-5560

ClK DEC
I

AMI

Ain
Bin

NRZ Data Out

~,

n~

__________________________________

~------~~-------------------------------I

HDB3

Ain
Bin

NRZ Data Out
B6ZS

r-----~~------------------------

Ain
Bin

NRZ Data Out

~~---------------------------

T---------~-----,

1

BSZS

Ain
Bin

NRZ Data Out

__-=~--~h~------~~~------~~~------~~~----~
rl--------7---~--~.~--------------------

14 cycles ----*

I

I

....-- 6 cycles ~
k------ 8 cycles

I

~

!

FIGURE 7. DECODE TIMING AND DELAY

Data that appears on Ain and Bin is clocked by the positive edge of ClK DEC. decoded and zeros
are inserted for all valid line code substitutions. The data then appears in non-return to zero form at output
NRZ Data Out. Ain and Bin are interchangable.

elK DEC
AIN
BIN
NRZ DATA

OUT
ERROR

__________________________

~!l~

____

~r__l~

FIGURE S.
The ERROR signal indicates bipolar violations that are not part of a valid substitution.

9-128

______

HC-55536

mlHARRIS

Continuous Variable
Slope Delta Demodulator {CVSD}

August 1991

Features

Description

• All Digital

The HC-55536 is a CMOS integrated circuit used to convert serial NRZ digital data to an analog (voice) signal. Conversion is by delta demodulation, using the Contrinuously
Variable Slope (CVSD) method of demodulation.

• Requires Fewer External Parts
• Low Power Drain: 1.SmW from Single 3V-7V Supply
• Time Constants Determined by Clock Frequency;
No Calibration or Drift Problems; Automatic Offset
Adjustment
• Filter Reset by Digital Control
• Automatic Overload Recovery
• Automatic "Quiet" Pattern Generation

Applications
• Voice Decoder for Digital Systems and Speech
Syntheses

While signals are compatible with other CVSD circuits, the
internal design is unique. The anaiog loop filters have been
repiaced by digital filters which use very low power and require no external timing components. This digital approach
allows inclusion of many desirable features, which otherwise would be difficult to implement. The device is usable
from 9Kbits/sec to above 64Kbits/sec, and may be easily
configured with the HC-55536 CVSD for a complete transmit/receive voice channel.
The HC-55536 is available in a 14 pin Ceramic DIP package.

• Voice Main
• Audio Manipulations; Delay Lines, Echo Generation/
Suppression, Special Effects, etc.
• Pager/Satellites

Pinout
HC-55536 (CERAMIC DIP)
TOP VIEW

Functional Diagram
(13)

FORCE

ZERo

SYLLABIC

DIGITAL
FILTER

DIGITAL
MODULATOR

+1

4.0msec

SIGNAL
EATIMATE
DIGITAL FILTER

10 BIT
DAC

1.0msec

AOUT
(3)

6

CLOCK
(9)

CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.

Copyright @ Harris Corporation 1991

9-129

VDD
(1)

DIGITAL GND
(8)

File Number

2888

Specifications HC-55536
Absolute Maximum Ratings
Voltage at Any Pin: ................... GNO -O.3Vto VOO +O.3V
Maximum Voo Voltage ....•.........•...•...•.••..•...• +7.0V
Minimum Voo Voltage ..................•...•..•...•..• +3.0V
Operating VOO Range •.•.••..•....•..••.•••.•• +3.0Vto +7.0V
Junction Temperature. . . . . • . . . . . . . . . • . . . . . . . . . • . . • • . .. 1750 C

Electrical Specifications

Operating Temperature Ranges
HC-55536-5 ..••..•.•••...•.•.•....•........ OOC to +750C
HC-55536-9 ......•.•.••..••............. -400C to +850 C
Storage Temperature Range .•............... -650 C to +1500C

Unless Otherwise Specified: VOO = +5.0V; Bit Range = 16K Bits/sec; typical parameters are at
+250 C. Min-Max parameters are over operating temperature.

PARAMETER
Clock Sampling Rate
Clock Outy Cycle
Supply Voltage
Supply Current
Logic "1" Input, VIH
Logic "0" Input, VIL
Audio Output Voltage
Audio Output Impedance
Syllabic Filter Time Constant
L.P. Signal estimate Filter Time Conatant
Step Size Ratio
Resolution
Minimum Step Size
Signal/Noise Ratio
QUieting Pattern Amplitude
Clamping Threshold

MIN

TYP

MAX

UNIT

NOTE

9

16

64
70
+7.0
1.5

Kbps

(1)

30
+3.0
0.3
4.5

3.5

0.5
150
4.0
1.0
24
0.1
0.2
25
10
0.75

1.5
1.2

%

V
mA
V
V
Vrms
ms
ms
dB

(2)
(2)
(3)
(4)
(5)
(5)
(6)

%

(7)

%

(8)

dB
mV p_p
F. S.

111 )

HI

(9)

NOTES:

1. There is one N RZ data bit per clock period. Clock must be
phased with digital data such that a positive clock transition

6, Step size compression ratio of the syllabic filter Is defined as
the ratio of the filter output, with an equal 1 -0 bit densitY
input to the filter, to its minimum output,

occurs in the middle of each received data bit. Clock may be
run at greater than 64Kbps or less than 9Kbps.

2. Logic inputs are CMOS compatible at supply voltage and are
diode protected. Digital data Input Is N RZ at clock rate
and changes with negative clock transitions.
3. This output Includes a OC bias of VOO/2; therefore, an AC
coupling capacitor Is required unless the output filter also
Includes this bias.
4. Presents approximately 150Kn In series with recovered
audio voltage. Zero-signal reference is VOO/2.

7. Minimum quantization voltage level expressed as a percentage
of supply voltage.
8. Tha minimum step size between levels Is twice the resolution.
9. The"quleting" pattern or Idle-channel audio output steps at
Yz the bit rate, changing state on negative clock transitions.
10. The recovered signal will be clamped, and the computation
will be Inhibited, when the recovered slngal reaches, threequarters of full-scale value, and will 'unclamp when it falls
below this value (positive or negative).

5. Note that filter time cinstants are Inversely proportional
to clock rate. Both filters approximate single pole responses.

9-130

HC-55536

SIGNAL LEVEL
OUTPUTD

•

-ODB

FIG. 1. Illustrates the frequency response of the HC-55536
for varying input levels. To prevent slope overload (slew
rate limiting) do not exceed the OdB boundary. The frequency response is directly proportional to the sampling
rate. The output levels were measured after filtering.

'DB IN • I.2DV
Vaa -+5V

..oOBIN

~

..DB

~DBIN

-1208

-12DBIN

-1808

-1BDOIN

-2408

-2409 IN

-3009

-300BIN

-3609

-3SD9IN

100

200

~ r-....

"" t\
"

...

300

FREOUENCV

.1

J(

BOO

'000

2000

3000

SAMPLl~: ~~!E IKb/lj

FIGURE 1 - TRANSFER FUNCTION FOR CVSD AT 16Kbps

Die Characteristics
Transistor Count ................................. 1790
Die Dimensions ..................•......•..... 154 x 93
Substrate Potential ................................. +V
Process .................................. SAJI CMOS
Thermal Constants (OCIW)
Sja
Sjc
Ceramic DIP, HC-55536
75
15

:;;

o
oW

....I

W
J-

9-131

HC-55536
Pin Description
PIN NO.
14-LEADDIP

SYMBOL

1

VDD

Positive supply voltage.

2

N.C.

No internal connection is made to this pin.

3

Audio Out

DESCRIP110N

Recovered audio out. Presents approximately 150KS1 source
with DC offset of VDD/2 should be externally AC couples.

4

N.C.

5

N.C.

No internal connection Is made to this pin.
No internal connection is made to this pin.

6,7

N.C.

No internal connection Is made to these pins.

8

Digital GND.

9

Clock

Logic Ground.
Sampling rote clock must be synchronized with the digital input
data such that the data is valid at the positive clock transition.

10

No internal connection is made to this pin.

N.C.

11

N.C.

12

Digitalin

No internal connection is made to this pin.

13

FZ

14

N.C.

Input for the received serial NRZ digital data.
Active low logic input. Activating this input resets the internal logic
and forces the recovered audio output into the "quieting" condition.
No internal connection is made to this pin.

NOTE: No active input should be left in a "floating condition".

Timing Waveforms
SAMPLING CLOCK:

..

II

II
II

II

II

DIGITAL IN:

~------~~11~~~
U 0 __~~1
!1 1

_1--II

II
II
II

II

IDS
IDS: DATA SET UP TIME 100ns TYPICAL
FIGURE 2 - CVSD TIMING DIAGRAM

9-132

HC-55564

mHARRIS

Continuously Variable
Slope Delta-Modulator {CVSD}

August 1991

Features

Description

• All Digital
• Requires Few External Parts
• Low Power Drain: 1.SmW Typical From Single
3.0V-7V Supply
• Time Constants Determined by Clock Frequency;
No Calibration or Drift Problems: Automatic Offset
Adjustment
• Half Duplex Operation Under Digital Control
• Filter Reset Under Digital Control
• Automatic Overload Recovery
• Automatic "Quiet" Pattern Generation
• AGC Control Signal Available

The HC-55564 is a half duplex modulator/demodulator
CMOS intergrated circuit used to convert voice signals into
serial NRZ digital data and to reconvert that data into voice.
The conversion is by delta-modulation, using the Continuously Variable Slope (CVSD) method of modulation/
de-modulation.
While the signals are compatible with other CVSD circuits,
the internal design is unique. The analog loop filters have
been replaced by very low power digital filters which require
no external timing components. This approach allows
inclusion of many desirable features which would be
difficult to implement using other approaches.

Applications
•
•
•
•

Voice Transmission Over Data Channels (Modems)
Voice/Data Multiplexing (Pair Gain)
Voice Encryption/Scrambling
Voicemail
o Audio Manipulations: Delay Lines,
Time Compression, Echo Generation/Suppression,
Special Effects, etc.
• Pagers/Satellites
• Data Aquisition Systems
• Voice I/O for Digital Systems and Speech Synthesis
Requiring Small Size, Low Weight, and Ease of
Reprogrammability

Pinout

The fundamental advantages of delta-modulation, along
with its simplicity and serial data format, provide an efficient
(low data rate/low memory requirements) method for voice
digitization.
The HC-55564 is usable from 9K bits/sec to above
64Kbps. The unit is available in a 14 pin Ceramic DIP, in
commercial OOC to +75 0 C and industrial-400C to +B5 0 C,
temperature ranges. See the Harris Military databook for a
Mil-Std-BB3C compliant CVSD. Application Notes 607 and
576 are available.

Functional Diagram
HC-55564
TOP VIEW

(9'

CLOCK

181

DIG. GilD

::;;
0

(,,)

w
w

........
(14)

DIGITAL OUT

FIGURE 1.
CAUTION: These devices are sensitive to electrostatic discharge. Proper I.C. handling procedures should be followed.
Copyright @ Harris Corporation 1991

9-133

File Number

2889

HC-55564
Pin Description
PIN #
14-PIN
DIP

DESCRIPTION

SYMBOL

1

VDD

2

AnalogGND

3

AOUT

Audio Out recovered from 10 bit DAC. May be used as side tone at the transmitter. Presents
approximately 150 kilohm source with D.C. offset of VDDI2. Within ±2dB of Audio Input. Should be
externally AC coupled.

4

AGe

Automatic Gain Control output. A logic low level will appear at this output when the recovered signal
excursion reaches one-half of full scale value. In each half cycle full scale is VDD/2. The mark-space
ratio is proportional to the average signal level.

5

AaN

Audio Input Ie comparator. Should be externally AC coupled. Presents approximately 280 kilohms
in series with VDD/2.

6,7

NC

No internal connection Is made to these pins.

8

DigitalGND

9

Clock

10

EiiCodeI
Decode

11

APT

12

Digitalin

13

FZ

14

Digital Out

Positive Supply Voltage. Voltage range is +3.0Vto +7.0V.
Analog Ground connection to D/A ladders and comparaler.

Logic ground. OV reference for all logic inputs and outputs.
Sampling rate clock. In the decode mode, must be synchronized with the digital input data such
that the data is valid at the positive clock transition. In the encode mode,the digital data is clocked out
on the negative going clock transition. The clock rate equals the data rate.
A single CVSD can provide half-duplex operation .. The encode or decode function Is selected by the
logic level applied to this input. A low level selects the encode mode, a high level the decode mode.
Alternate Plain Text Input. Activating this input caused a digital quieting pattern to be transmitted,
however; internally the CVSD is still functional and a signal Is still available at the AOUT port.
Active low.
Input for the received dlgHal NRZ data.
Force Zero input. Activating this Input resets the internal logic and forces the digital output and the
recovered audio output inle the "quieting" condition. An alternating 1-0 pallern appears at the digital
output at 'h the clock rate. When this is decoded by a receive CVSD, a 10mVp-p Inaudible signal
appears at audio output. Active low.
Outpulforlransmilled digital NRZ data.

NOTE: No active input should be left in a ''floating condition."

9-134

Specifications HC-55564
Absolute Maximum Ratings
Voltage at Any Pin •.•••••••••.••••••.• GND -0.3V to VDD +0.3V
Maximum VDO Voltage •••••••••••••••••••••••••.••••••• +7.0V
Minimum VDD Voltage •••.••..••••.•.•••••.••••.••.•••• +3.0V
Operating VDD •••••••••••••••.••••.•••••••.••• +3.0V to +7.0V
Junction Temperature •••••••••.••••.••••••••••••••••• +1750 C

Electrical Specifications

SYMBOL.

Operating Temperature Ranges
HC-55564-5, -7 •••••••••••••••••••••••••••••• OOC to +750 C
HC-55564-9 •••.••••.••••••••••••••••••••• -400 C to +850 C
HC-55564-2 •••••••••••••••••..•.••.••••• -550 C to +1250 C
Storage Temperature •.••••••••••••••••.••••• -650 C to +150oC

Unless Otherwise Specified, typical parameters are at +250 C, min-max are over operating tempera'
ture ranges. VDD +5.0V; Sampling Rate 16Kbps, AG DG OV, AIN 1.2Vrms.

PARAMETER

=

MIN

=

TYP

=

MAX

UNITS

=

=

CONDITIONS

ClK

Sampling Rate

9

16

64

Kbps

IDD

Supply Current

-

0.3

1.5

mA

VIH

logic '1 ' Input

3.5

-

-

V

Note 2

Vil

logic '0' Input

-

1.5

V

Note 2

-

V

Note 3

0.4

V

Note 3

30

-

Audio tnput Voltage

-

0.5

1.2

Vrms

AC Coupled. Note 4

Audio Output Voltage

-

0.5

1.2

Vrms

AC Coupled. Note 5

280

-

kO

Note 6

kO

Note 6
No load. Audio In to Audio Out

VOH

logic '1' Output

4.0

VOL

logic '0' Output

-

Clock Duty Cycle
AIN
AOUT
ZIN

Note 1

Audio Input Impedance

70

%

ZOUT

Audio Output Impedance

AE-D

Transfer Gain

-2.0

-

+2.0

dB

AE

Encode Gain

-

0.34

-

dB

AD

Decode Gain

-

dB
mS

Note 7

mS

Note 7
Note 8

!sF

Syllabic Filter Time Constant

!sE

Signal Estimate Filler
Time Constant

1.0

Resolution

-

Minimum Step Size
VQP

Quieting Pattem Amplitude

-

VATH

AGC Threshold

VCTH

Clamping Threshold

150

1.23
4.0

0.1

-

%

0.2

-

%

10

-

mVp-p

-

0.5

-

F.S.

Note 11

-

0.75

-

F.S.

Note 12

Note 9

Fz =OV or ART =OV; or
AIN

9-135

=OV. Note 10, 13

HC-55564
NOTES:

7. Note that filtar time constants ars Inversely proportional to clock rate.
Both filters approximate single pole responses.

1. There is one NRZ (Non-Return Zero) data bit clock pe·riod. Data is
clocked out on the negative clock edge. Data is clocked Inlo the CVSD
on the pOsitive gOing edga (see Figure 2). crock may be run alless than
9Kbps and greater than 64Kbps.
2. logic inputs are CMOS compatible at supply voltage and Bre diode
lected. Digital data input is NRZ at clock rate.
.

8. Minimum quantization voltage leval expressed as a percentage of supply

voltage.

pro~

3. Logic outputs are CMOS compatible at supply voltage and will withstand
shorl-circuits to Voe or ground. Digital data output is NRZ and changes
with negative clock transitions. Each output will drive one lS TTL load.
4. Recommended voice input range for best voice performance. Should be
externally AC coupled.

5, May be used for side-tone In encode mode. Should be externally AC
coupled. Varle. wfth audio Inpullevel by ±dB.
6. Presents series Impedance with audio signal. Zero signal reference is
approximately VOOf2.

9. The minimum step size between levels is twice the resolution.
10. The "quietlng" paUsrn or Idle-channel audio output steps at one-half the
bit rate, changing slate on negative clock transitions.
11. A logic "0'· will appear at the AGe output pin when the recovered signal
reaches one-half of full-scale value (positive or negative), i.e. at VOOJ2
±25% ofVOO'
12. The recovered signal will be clamped, and the computation will be Inhibited, when the r&covered Signal reaches three-quarters of full-scale value, and will unclamp when it falls below this value (positive or negative).
13. Typical encoding threshold for quieting pattern generation Is 6.5mVrms
at 1 kHz input signal. 16kHz clock. The threshold varies inversly with input frequency and proportionally with clock frequency.

Timing Waveforms
SAMPLING CLOCK:

II

DEC/ENC

L~'----------------------------------------~n.

::tl

DIGITAL NRZ IN:

_II.

!-iHi-___~j,1
II
II
tl
II

DIGITAL NRZ OUT: 'OS

!l

'OS: DATA SET UP TIME. lOOns TYPICAL

FIGURE 2. CVSD TIMING DIAGRAM

Die Characteristics
Transistor Count ................................ 1896
Die Dimensions ..................... : ........ 154 x 93
Substrate Potential ................................ +V
Process. . • • . . . . . . . • . . . • • • • . . . . . . . . . . • . . .. SAJI CMOS
6ja
6jc
Thermal Constants (OC/W)
Ceramic DIP
75
15

9-136

HC-55564
Interface Circuit for HC-55564 CVSD
AUDIO SOURCE
HC·55564

HC-5512/12A/12D'

INPUT
LEVEL ADJUST
RA. RB. CA
OPTIONAL

CA

~

RB 5

VFX I +

PWRO+

VFX I -

VFxO

GSx

VFRI

AUDIO OUT

AGC
AIN

0.1"
AOUT

DOUT
OIN

Fz

VFRO
PWRI
1 VOD

CLKO
PDN

+5V

VCC

-5V

11
VBB
GNOO
GNDA ClK

14
Il

13

APT 11
10

flo

ITO OATA IIFI
IFROM DATA IIFI

I

EXTERNAL
CONTROL

0.1"
8 DIGITAL
GND
"::'

O.l,,~~.1,,15

"HC·5512D ALSO AVAILABLE IN
LCC FOR TOTAL SURFACE MOUNT
APPLICATION SOLUTION
""RD 100KO to IMO

CLK. GEN.
FIGURE 3.

CVSD Hookup for Evaluation
The circuit in Figure 3 is sufficient to evaluate the voice
quality of the CVSD, since when encoding the feedback signal at the audio output pin is the reconstructed audio input
signal. CVSD design considerations are as follows:
1) Care should be taken In layout to maintain isolation between analog and digital signal paths for proper noise
consideration.
2) Power supply decoupling Is necessary as close to the
device as possible. A 0.1 flf should be sufficient.
3) Ground, then power, must be present before any input
sIgnals are applied to the CVSD. Failure to observe this
may cause a latchup condition which may be destructive. Latchup may be removed by cycling the power offl
on. A power-up reset circuit may be used that strobes
Force Zero (Pin 13) during power-up as follows:

4) Analog (signal) ground (Pin 2) should be externally tied
to Pin 8 and power ground. It is recommended that the
AIN and AOUT ground returns connect only to Pin 2.
5) Digital inputs and outputs are compatible with standard
CMOS logic using the same supply voltage. All unused
logic inputs must be tied to the appropriate logic level for
desired operatIon. TTL outputs will require 1K Ohm pullup resistors. Pins 4 and 14 will each drive CMOS logic
or one low power TTL input.
6) Since the AudIo Out pins are internally DC biased to
VDO/2, AC coupling is required. In general, a value of
0.1 flf is sufficient for AC coupling of the CVSO audio
pins to a filter circuit.
7) The AGC output may be externally integrated to drive an
AGC pre-amp, or it could drive an LEO indIcator through
a buffer to indicate proper speaking volume.

9-137

HC-55564
Figures 4, 5, and 6 illustrate the typical frequency response
of the HC-55564 for varying input levels and for varying
sampling rates. To prevent slope overload (slew limiting),
the OdS boundry should not be exceeded. The frequency
response is directly proportional to the sampling clock rate.

SIGNAL LEVEL
@AOUT

OdB
-6dB

I""

The flat bandwidth at OdS doubles for every 16kHz Increase
in sampling rate. The output levels were measured in the
encode mode, without filtering, from AIN to AOUT, at VDD =
+5V. OdS = 1.2Vrms.

!-~

~

-12dB
-18d8

-10

"-

" !\.

-24d8

d8
~o

~

-30dB
-36d8

100

-20

-40

10000
INPUT FREQUENCY @ AIN 1Hz,

1000

FIGURE 4. 16Kbps
SIGNAL LEVEL
@AOUT

--......

OdB
-6d8

-10

......,."""

~

-12d8

-20

-18dB
dB
-24dB

~o

-30d8
-40

-36dB

100

10000
INPUT FREQUENCY @ AIN 1Hz,

1000

FIGURE 5. 32Kbps
SIGNAL LEVEL
@AOUT

--

,0dB
-6d8

t........

-10

-12d8
-20
-18d8
d8
-24d8

-30

-30d8
-40

-36dB

100

lDOD

10000
INPUT FREQUENCY @ AIN IHzl

FIGURE 6. 64Kbps

9-138

HC-55564
The following typical performance distortion graphs were
realized with the test configuration of Figure 7. The measurement vehicle for Total Harmonic ~istortion (THO) was an
HP-339A distortion measurement set, and for 2nd and 3rd

harmonic distortion, an HP-3582A spectrum analyzer. All
measurement conditions were at VOO = +5V, and 2nd and
3rd harmonic distortion measurements were C-message filtered. OdB = 1.2Vrms.

•JJ

ADUT I-'J'--_--I

fUNCTiON
GENERATOR

1 VDD

11m
1J IT

DECI 10
ENC 8

~

HPJ582A
SPECTRUM
ANALYZER
OR HPJJ9A
DISTORTiON
ANALYZER

C·MESSAGE
filTER

DGND 2
AGND

+5V

FIGURE 7. TEST AND MEASUREMENT CIRCUIT

-.

0

-30"
INPUT FREQ=tKHI
........... 16KHz

THO

-,0
-,0

r::::::::

-.-,.

--

32KHz

64KHI

0

-s

-16

INPUT SIGNAL LEVEL dB

-10%

-1%

o

FIGURE 8. CVSD SIGNAL LEVEL VS. TOTAL HARMONIC DISTORTION

CVSD SIGNAL TO 2ND AND 3RD HARMONIC DISTORTION C·MESSAGE WEIGHTED

CVSD INPUT LEVEL VERSUS 2ND AND 3RD HARMONIC DISTORTION CMESSAGE WEIGHTED

-. o

INPUT FREQUENCY
lKHl

-,0

-

'6KHZ CLOCK

dB -3 0

-.
-.-,.

VIN=D.5VRMS
16KHZ CLOCK

'RO

-

~

0

'NO

-5O~0------.,JDD'::0------""''':DD':"O------'...JOOO

0

-17

-II

-3.B

+3.0

A)

INPUT LEVEL(dB)

A)

-.

CVSD INPUT LEVEL VERSUS 2ND AND 3RO HARMONIC DISTORTION C·MESSAGE WEIGHTED

-. o

-,
-,
'B

INPUT FREQUENCY

~

0

.. -......:::::
-.-,.

'B

0

-17

-II

-3.B

.,

+3.D

....

-2

-40

'"-...........

-50
-Z4
C)

-17

-II

-

dB

'.0 -;7

'RO

-18

3R0

1000

2000

-

-'
W

~
.......
JOOO

4000

INPUT FREQUENCYI'H.Z)

CVSD SIGNAL TO 2ND AND 3RD HARMONIC DISTORTION C-MESSAGE WEIGHTED

64KHZ CLOCK

-,o~ --..

............... ~

-. o~

CiSO INPUT LEVEL VERSUS 2ND AND 3RD HARMONIC DISTORTION C·MESSAGE WEIGHTED

-,

·6

+3.0

INPUT LEVEL(d8)

V1N =O.5VRMS
64KHZ CLOCK

0,
o

-.,
-.0
0
o

C)

~

-

.0

'RO

1000

2000

- --:::

3000

4000
'NPUT fREOUEHCY(Hz)

FIGURE 10A, B, C. CVSD INPUT FREQUENCY vs.
2ND AND 3RD HARMONIC DISTORTION

FIGURE 9A, B, C. CVSD INPUT LEVEL vs.
2ND AND 3RD HARMONIC DISTORTION

9-139

:;;

o
ow

D)

-10 INPUT FREQUENCY

'B

0

INPUT LEVEL(dB)

D)

•

-. '--=
-.
0

0

-2

VIN=G.SVRMS
32KHZ CLOCK

0'
0

,.~

~

0

-,
-, o~

1KHz
32KHZ CLOCK

0

INPUT fREDUENCY(Hz)

CVSO SIGHAL TO 2ND AND JRD HARMONIC DISTORTION CMESSAGE WEIGHTED

I-

HARRIS QUALITY AND RELIABILITY
PAGE
INTRODUCTION ...........................................•.........•...........•...•.......•.. 10-3
THE ROLE OF THE QUALITY ORGANIZATION ..........................................•........ 10-3
THE IMPROVEMENT PROCESS ........................•.........................•....•.•...•... 10-3
DESIGNING FOR MANUFACTURABILITY •....................................................... 10-5
HARRIS SEMICONDUCTOR STANDARD PROCESSING FLOWS .................................. . 10-6
CONTROLLING AND IMPROVING THE MANUFACTURING PROCESS - SPC/DOX ...........•...... 10-8
AVERAGE OUTGOING QUALITY (AOQ) ..•...............•....................................... 10-9
Training ...................................•...................•....•...............•...•..... 10-9
Incoming Materials .........................•...........................•........•.........•... 10-10
MANUFACTURING SCIENCE - CAM, JIT .•...............•....................................... 10-11
Computer Aided Manufacturing (CAM) ...•...............•....................................... 10-11
Just In Time (JIT) .............•........•....................................................... 10-11
MEASUREMENT ...•............•......................................•..........••....•••...•. 10-12
Analytical Services Laboratory .........................................•.................•...... 10-12
Calibration Laboratory ...•............................................•..........•..........••. 10-12
Failure Analysis Laboratory .................................................................... . 10-13
RELIABILITY ......•...........•........................•....................................... 10-13
Reliability Assessment and Enhancement ...•..................................................... 10-13
Qualifications ................•................................................................ 10-13
In-Line Reliability Monitors ..................•....................................•............. 10-13
PRODUCT/PACKAGE RELIABILITY MONITORS ................................................. . 10-13
PFAST ACTION REQUEST FORM ................•............................................... 10-14
RELIABILITY FUNDAMENTALS .........................................•......................•. 10-15
Failure Rate Primer .....•....••.........•..............•.........................•..........•.. 10-15
Failure Rate Calculations .........•.............................•......•.....................••• 10-16
Acceleration Factors .....•.........................................•.........•............•.... 10-16
Activation Energy .•......•............•.•......•..•.•.•..........•............................. 10-16
Qualification Procedures .........•.............•....................•...•............•......... 10-18

10-1

c>

~5

>- ....m

::::;:;!;

« ....

:::lw

00::

Harris Quality & Reliability
Introduction
Success in the integrated circuit industry means more
than simply meeting or exceeding the demands of
today's market. It also includes anticipating and
accepting the challenges of the future. It results from
a process of continuing improvement and evolution,
with perfection as the constant goal.

procedures through auditing, sampling, consulting,
and managing Quality Improvement projects.

To support specific market requirements, or to ensure
conformance to military or customer speCifications,
the Quality organization still performs many of the
conventional quality functions (e.g., group testing for
Harris Semiconductor's commitment to supply only military products or wafer lot acceptance). But, true to
top value integrated circuits has made quality im- the philosophy that quality is everyone's job, much of
provement a mandate for every person in our work the traditional on-line measurement and control of
force - from circuit designer to manufacturing opera- quality characteristics is where it belongs - with the
tor, from hourly employee to corporate executive. people who make the produc!. The Quality organizaPrice is no longer the only determinant in marketplace tion is there to provide leadership and assistance in
competition. Quality, reliability, and performance en- . the deployment of quality techniques, and to monitor
joy significantly increased importance as measures of progress.
value in integrated circuits.

The Improvement Process

Quality in integrated circuits cannot be added on or
considered after the fact. It begins with the development of capable process technology and product
design. It continues in manufacturing, through effective controls at each process or step. It culminates in
the delivery of products which meet or exceed the
expectations of the customer.

1

STAGE IV

I

PRODUCT II
OPTIMIZATION

IMPACTON
PRO DUCT
QU AUTY

STAGE III
PROCESS
OPTIMIZATION

The Role of The Quality Organization

STAGE II

The emphasis on building quality into the design and
manufacturing processes of a product has resulted in
a significant refocus of the role of the Quality organization. In addition to faCilitating the development of
SPC and DOX programs and working with manufacturing to establish control charts, Quality professionals are involved in the measurement of equipment
capability, standardization of inspection equipment
and processes, procedures for chemical controls,
analysis of inspection data and feedback to the manufacturing areas, coordination of efforts for process
and product improvement, optimization of environmental or raw materials quality, and the development
of quality improvement programs with vendors.
At critical manufacturing operations, process and
product quality is analyzed through random statistical
sampling and product monitors. The Quality organization's role is changing from pOlicing quality to
leadership and coordination of quality programs or

PROCESS
CONTROL
STAGE I
PRODUCT
SCREENING
SOPHISTICATION OF
QUALITY TECHNOLOGY

FIGURE 1. STAGES OF STAnSTICAL QUALITY TECHNOLOGY

Harris Semiconductor's quality methodology is evolving through the stages shown in Figure 1. In 1981 we
embarked on a program to move beyond Stage I, and
we are currently in the transition from Stage II to Stage
III, as more and more of our people become involved
in quality activities. The traditional "quality" tasks of
screening, inspection, and testing are being replaced
by more effective and efficient methods, pulling new
tools into the hands of all employees. Table 1 illustrates how our quality systems are changing to meet
today's needs.

10-3

TABLE 1. TYPICAL ON-LINE MANUFACTURING/QUAUTY FUNCTIONS

WaferFab

Assembly

Test

Probe

MANUFACTURING
CONTROLS

FUNCTION

AREA

X

• JAN Self-Audit
• Environmental
- Room!Hood Particulates
- Temperature/Humidity
- Water Quality
• Product
- Juncllon Depth
- Sheet Resistivities
- Defect Density
- Critical Dimensions
- Visual Inspection
- Lot Acceptance
• Process
- Film Thickness
- Implant Dosages
- Capacitance Voltage Changes
- Conformance to Specification
• Equipment
- Repeatability
- Profiles
- Calibration
- Preventive Maintenance

X
X
X
X
X
X
X

JAN SeR-Audit
Temperature/Humidity
ESD Controls
Temperature Test Calibration
Test System Calibration
Test Procedures
Control Unit Compliance
Lot Acceptance Conformance
GroupALotAcceptance

•
•
•
•
•

JAN SeR-Audit
Wafer Repeat Correlation
Visual Requirements
Documentation
Process Performance

X
X
X

X
X
X
X

X
X
X
X

X

X
X

X
X
X
X

X

• JAN SeR-Audit
• Environmental
- Room/Hood Particulates
- Temperature/Humidity
- Water Quality
• Product
- Documentation Check
- Dice Inspection
- Wire Bond Pull Strength/Controls
- Die Sear Controls
- Pre-Seal Visual
- Fine/Gross Leak
- PINDTest
- Lead Finish Visuals, Thickness
- Die Shear
- Solderability
• Process
- Operator Quality Performance
- Saw Controls
- Die Attach Temperatures
- Seal Parameters
- Seal Temperature Profile
- Sta-Bake Profile
- Temp Cycle Chamber Temperature
- ESD Protection
- Plating Bath Controls
- Mold Parameters
•
•
•
•
•
•
•
•
•

QA/QC MONITOR
AUDIT

X
X

X
X
X

X
X
X
X
X

X
X
X
X
X
X

X
X
X

X

X
X
X

X
X
X
X
X
X
X
X
X
X

X

X
X
X
X

X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X

10-4

X
X
X

TABLE 1. TYPICAL ON-LINE MANUFACTURING/QUALITY FUNCTIONS (CONTINUED)

AREA
Burn-In

Brand

QCllnspection

MANUFACTURING
CONTROLS

FUNCTION

QA/QC MONITOR
AUDIT

X

•
•
•
•

JAN Self-Audit
Functionality Board Check
Oven Temperature Controls
Procedural Conformance

X
X

•
•
•
•
•

JAN Self-Audit
ESD Controls
Brand Permanency
Temperature/Humidity
Procedural Conformance

X
X
X

X
X
X
X
X
X
X
X
X

• JAN Self-Audit
• Group B Conformance
• Group C and 0 Conformance

Designing For Manufacturability
Assuring quality and reliability in integrated circuits
begins with good product and process design. This
has always been a strength in Harris Semiconductor's
quality approach. We have a very long lineage of high
reliability, high performance products that have resulted from our commitment to design excellence. All
Harris products are designed to meet the stringent
quality and reliability requirements of the most demanding end equipment applications, from military
and space to industrial and telecommunications. The
application of new tools and methods has allowed us
to continuously upgrade the design process.
Each new design is evaluated throughout the development cycle to validate the capability of the new
product to meet the end market performance, quality,
and reliability objectives.
The validation process has four major components:
1. Design simulation/optimization
2. Layout verification
3. Product demonstration
4. Reliability assessment.
Harris designers have an extensive set of very powerful
Computer-Aided Design (CAD) tools to create and
optimize product designs (see Table 2).

TABLE 2. APPROACH AND IMPACT OF STATISTICAL
QUALITY TECHNOLOGY
STAGE
I

Product
Screening

"

Process

III

IV

APPROACH

IMPACT

• Stress and Test
• Defective Prediction

• Limited Quality
• Costly
• After-The-Fact

• Statistical Process
Control
• Just-In-Time
Manufacturing

• Identifies Variability
• Reduces Costs
• RealTime

Process
Optimization

• Design of Experiments
• Process Simulation

• Minimizes Variability
• Before-The-Fact

Product
Optimization

• Design for Producibility
• Product Simulation

• Insensitive to Variability
• Designed-In Quality
• Optimal Results

Control

Special Testing
Harris Semiconductor offers several standard screen
flows to support a customer's need for additional testing and reliability assurance. These flows include
environmental stress testing, burn-in, and electrical
testing at temperatures other than +25 0 C. The flows
shown on pages 9-6 and 9-7 indicate the Harris
standard screening processes. In addition, Harris can
supply products tested to customer specifications
both for electrical requirements and for non-standard
environmental stress screening. Consult your field
sales representative for details.

10-5

Harris Semiconductor Standard Processing Flows
SMD

883
JANCLASSB
LASER
TRIMMING
AT BOTH
PACKAGE AND
WAFER LEVELS

PROBE/DICE
PREPARATION

HIGH/ROOM
TEMP
PROBE TEST

VISUAL
INSPECTION
PER
MIL-STD-883
METHOD 2010
CONDITION B
WITHOC
MONITOR

ASSEMBLY (1)

o

DIE ATTACH
CONTROL

WIRE BOND
CONTROL

'*

OPERATION
QAMONITOR
LEAD FRAME CLEAN

YES

DIE AND FRAME ATIACH
CONTROL

YES

OADIEATIACH
CONTROL (SPC)

2-HOUR

'*

WIRE BOND
PRE-SEAL
WASH IN
LAMINAR
FLOW

PRE-SEAL
VISUAL
INSPECTION
IN CLASS 100
LAMINAR
FLOW

'*

OA WIRE BOND
CONTROL

PRE-SEAL CLEAN
PRE-SEAL INSPECT

'*

OA PRE-SEAL INSPECT

YES
PER
MIL-STD-883
METHOD 2010
CONDITIONB
YES
YES

CERDIP SEALING

YES

SEAL CONTROL

YES

TEMPERATURE CYCLE

YES

CENTRIFUGE

YES

TIN-PLATING

'*

PARTICLE
IMPACT NOISE
DETECTION
(PIND)
AS
REQUIRED

YES
2-HOUR

OA TIN-PLATING
INSPECT

YES
YES

FINE LEAK TEST

YES

GROSS LEAK TEST

YES

PINDTEST

b

FRAME REMOVAL

AS
APPLICABLE
YES

LOAD SHIPPING TUBES

YES

OA FINALINSPECT

YES

OA DOCUMENTATION
INSPECT

YES

'*
'*

(1) Example for a Cerdip Package Part

10-6

Harris Semiconductor Standard Processing Flows
(Continued)

SMD

883
JAN CLASS B

TEST(2)
0

*
AC/DC SINGLE
INSERTION TEST
ICAPABILITY;
HIGH/LOW TEMP

OPERATION
QAMONITOR
ELECTRICAL TEST SORTING
OPERATION
SERIALIZE

YES

IF
APPLICABLE

BURN-IN
'--

QUALITY
CONFORMANCE ' - GROUPS A, B, C, IANDDAS
REQUIRED

~

PRE BURN-IN ELECTRICAL
TEST
BURN-IN(3)

POST BURN-IN TEST

-*
DELTAS PER
SLASH SHEET
REQUIREMENT
IF APPLICABLE

IN-HOUSE
MASS
SPEC
CAPABILITY

I-

f-

ALTERNATE GROUP A

COMPUTERIZED
LOT
TRACEABILITY c - MONITORING
SYSTEM

160-HOUR@
+125 0 C,OR
PER
SLASH SHEET
YES
YES

APPLY BURN-IN PDA
(AS APPLICABLE)

YES

SOLDERDIP

YES

FINE LEAK TEST

YES

GROSS LEAK TEST

YES

BRAND

YES

EXTERNAL VISUAL
'-

YES

t--*

QUALITY
CONFORMANCE
INSPECTION

FINAL DATA REVIEW

YES
GROUPA,B,
C,D

YES

c>-

z>«=;
>>-lll
--I «
«--I
:::>w

oil:

PACKAGE & SHIP
OR STOCK

(2) -550C TO +125 0 C
(3) Burn-In test temperatures can be increased and time reduced per regression tables in Mil-Std-SS3, Method 1015.

10-7

TABLE 3. SUMMARIZING CONTROL APPLICATIONS
FAB
• Diffusion

-

Junction Depth
Sheet Resistivities
Oxide Thickness
Implant Dose Calibration
Uniformity

• Measurement Equipment
- Critical Dimension
- Film Thickness
- 4 Point Probe
- Ellipsometer

• Photo Resist
- Critical Dimension
- Resist Thickness
- Etch Rates

• Thin Film
- Film Thickness
- Uniformity
- Refractive Index
- Film Composition

ASSEMBLY
• Pre-Seal
- Ole Prep Visuals
- Yields
- Die Attach Heater Block
- DieShear
- Wire Pull
- Saw Blade Wear
- Pre-Cap Visuals

• Post-Seal
• Measurement
- Internal Package Moisture
- XRF
- Radiation Counter
- Tin Plate Thicknass
- PI NO Defect Rate
- Thermocouples
- SolderThlckness
- GM-Force Measurement
- LeakTesls
- Module Rm. Solder Pot Temp.
- Seal
- Temperature Cycle
TEST
-

- Monitor Failures
- Lead Strengthening Quality
- After Burn-In PDA

HandlersITest Systems
Defect Pareto Charts
Lot % Defective
ESD Failures par Month
OTHER

• IQC
- Vendor Performance
- Material Criteria
- Quality Levels

• Environment
- Water Quality
- Clean Room Control

• IQC MeasuremenVAnalysis
- XRF
-ADE
- 4 Point Probe
- Chemical Analysis Equipment

Controlling and Improving the
Manufacturing Process - SPC/DOX
Statistical process control (SPC) is the basis for quality
control and improvement at Harris Semiconductor.
Harris manufacturing people use over 1,000 Shewhart
control charts to determine the normal variabilities in
processes, materials, and products. Critical process
variables are measured and control limits are plotted on
the control charts. Appropriate action is taken if the
charts show that a variable is outside the process control limits or indicates a trend toward the limit These
same control charts are powerful tools for use in reducing variations in processing, materials, and products.
Table 3 lists some typical manufacturing applications
of control charts at Harris Semiconductor.

defects to the levels expected by today's buyers. In addition, screening and inspection have an associated
expense, which raises product cost.
Harris engineers are, instead, using DeSign of Experiments (DOX), a scientifically diSCiplined mechanism for
evaluating and implementing improvements in product
processes, materials, equipment, and facilities. These
improvements are aimed at reducing the number of defects by studying the key variables controlling the process, and optimizing the procedures or design to yield
the best result This approach is a more timeTABLE 4. HARRIS I.C. DESIGN TOOLS
PRODUCTS
DESIGN STEP

But SPC is only part of the solution. Processes which
operate in statistical control are not always capable of
meeting engineering requirements. The conventional
way of dealing with this in the semiconductor industry
has been to implement 100% screening or inspection
steps to remove defects, but these techniques are insufficient to meet today's demands for the highest reliability and perfect quality performance.
Harris still uses screening and inspection to "grade"
products and to satisfy specific customer requirements
for bum-in, multiple temperature test insertions,
environmental screening, and visual inspection as value-added testing options. However, inspection and
screening are limited in their ability to reduce product

ANALOG
Slice

Silos
Proteous
Socrates

Parametric
Simulation

Slice
MonlsCarlo

Slice

Schematic
Capture

Note 1

Daisy
SDA-Mass Comp

Functional
Checking

Note 1

SDA-LVS

Rules
Checking

Calma-DRC

Harris Dash

ParasHic
Extraction

Note 1

SDA-LVS

NOTE 1. Tools are In Development.

10-8

DIGITAL

Functional
Simulation

consuming method of achieving quality perfection,
but a beUer product results from the efforts, and the
basic causes of product nonconformance can be
eliminated.
SPC, DOX, and design for manufacturability, coupled
with our 100% test flows, combine in a product assurance program that delivers the quality and reliability
performance demanded for today and for the future.

The focus on this quality parameter has resulted in a
continuous improvement over the past three years.
AOQ has improved from 1,000 PPM to less than 100
PPM, and the goal for 1989 is to continue improvement toward a goal of a PPM.

Average Outgoing Quality (AOQ)
Average Outgoing Quality is a yardstick for our
success in quality manufacturing. The average outgoing electrical defective is determined by randomly
sampling units from each lot and is measured in parts
per million (PPM). The current procedures and
sampling plans outlined in MIL-STD-883 and MILM-38510 are used by our quality inspectors.

Training
The basis of a successful transition from conventional
quality programs to more effective, total involvement
is training. Extensive training of personnel involved in
product manufacturing began in 1984 at Harris, with
a comprehensive development program in statistical
methods. Using the resources of the University of
Tennessee, private consultants, and internally developed programs, training of over 2,000 engineers,
supervisors, and operators/technicians has been
completed.
Nearly 1,000 operators, 100 supervisors, and more
than 800 engineers have been trained in SPC
methods, providing them with tools to improve the
overall level of uniformity of Harris products. Almost
300 engineers have received training in DOX
methods: learning to evaluate changes in process operations, set up new processes, select or accept new
equipment, evaluate materials, select vendors, compare two or more pieces of equipment, and compare
two or more process techniques.

300
200

100

04-~.--r--~-'---.--r-~--'-~.--r--'
Q1

FY88

FY87

FY88

FIGURE 2. DEFECTIVE PARTS PER MILLION

Over the past four years, Harris has also deployed a
comprehensive training program for hourly operators
and supervisors in job requirements and functional
skills. All hourly manufacturing employees partiCipate
(see Table 5).

TABLE 5. SUMMARY OF TRAINING PROGRAMS
COURSE

AUDIENCE

LENGTH

TOPICS COVERED

SPC

Manufacturing Operators

8 Hours

Basic Philosophy, Statistical Calculations
Graphing Techniques, Pareto Charts, Control Charts

SPC

Manufacturing Supervisors

21 Hours

Basic Philosophy, Statistical Calculations
Graphing Techniques, Pareto Charts, Control Charts,
Testing for Inspector Agreement, Cause & Effect Diagrams,
1 & 2 Sample Methods

SPC

Engineers and Managers

48 Hours

Basic Philosophy, Graphical Methods, Control Charts,
Rational Subgrouping, Variance Components, 1 & 2
Sample Methods, Pareto Charts, Cause & Effect Diagrams

DOX
(Design of
Experiments)

Engineers and Managers

88 Hours

Factorial Designs, Fractional Factorial Designs,
Blocking DeSigns, Variance Components,
Computer Usage, Normal Probability Plolting

RSM
(Response Surface
Methods)

Engineers and Managers

40 Hours

Steepest Ascent, Central Composite Designs,
Box-Behnken Designs, Computer Usage,
Contour Plolting, Second Order Response Surfaces

Continuous
Improvement
Methods

Manufacturing Supervisors

12 Hours

Basic Philosophy, Pareto Analysis,lmaglneering,
Run Charts, Cause & Effect Diagrams, Histograms,
Ideas of Control Charts

SPCThe Essentials

Department-Level
WorkGroups

20 Hours

Basic Philosophy, of Continous Improvement,lmagineering
Pareto Charts, Cause & Effect Diagrams, Flow Charts,
Graphical Display, Control Charts, Ideas of experiment

10-9

c>-

2:1-

~~

I-£D

::::;=S

«
.....
~w

ocr:

Incoming Materials
With statistical procedures in place to improve quality
in the manufacturing operation, the impact of Silicon,
chemicals, gases, and other materials used in
processing the product has become more measurable. Q\,Iality and consistency are important; it is logical
to feed the manufacturing line with materials
manufactured by vendors using equivalent statistical
controls.
In order to ensure optimum quality of materials purchased from vendors, Harris initiated and coordinated
an aggressive program to link key suppliers to our
manufacturing operations. This network is formed by
certifying strategic vendors who meet the highest

quality standards while demonstrating a commitment
to the use of statistical controls in their manufacturing
operations.
SPC seminars, development of open working relationships, understanding of manufacturing needs and
vendor capabilities, and continual improvement programs are all part of the certification process. Certified
suppliers have passed stringent quality and SPC
audits, while continuing to supply material with 100%
conformance to Harris requirements.
In addition to the certification process, Harris has
worked to promote improved quality in the performance of all our qualified vendors, who must meet
rigorous incoming inspection criteria (see Table 6).

TABLE 6. INCOMING QUALITY CONTROL MATERIAL QUALITY CONFORMANCE
MATERIAL
Silicon

INCOMING INSPECTIONS

• Equipment Capability Control Charts
- Oxygen
- Resistivity
• Control Charts Related to
- Enhanced Gettering
- Total Thickness Variation
- Total Indicated Reading
- Psrticulates
• Certificate of AnalysiS for all Critical Parameters

• Resistivity
• Crystal Orientation

• Dimensions
•
•
•
•
•
•
•
Chemicals/Photoresistsl
Gases

VENDOR DATA REQUIREMENTS

Edge Conditions
Taper
Thickness
Total Thickness Variation
Backside Criteria
Oxygen
Carbon

• Certificate of AnalysiS on ali Critical Parameters
• Control Charts
- Assay
- Contaminants
- Water
- Selected Parameters

• Chemicals
- Assay
- Major Contaminants
• Molding Compounds
- Spiral Flow
- Thermal Characteristics
• Gases
-Impurities

• Control Charts
- Assay
- Contaminants
• Control Charts on
- Photospeed
- Thickness
- UV Absorbance
- Filterability
- Water
- Contaminants

• Photoresists
- Viscosity
- Film Thickness
- Solids
- Pinholes

Thin Film Materials

• Assay
• Selected Contaminants

• Control Charts
- Assay
- Contaminants
- Dimensional Characteristics
• Certificate of Analysis for all Critical Parameters

Assembly Materials

•
•
•
•
•
•
•
•
•
•
•

• Certificate of Analysis
• Process Control Charts on Outgoing Product
Checks and In-Line Process Controls

Visuallnspectlon
Physical Dimension Checks
Lead Integrity
Glass ComposHlon
Bondabllity
Intermetalllc Layer Adhesion
Ionic Contaminants
Thermal Characteristics
Lead Coplanarity
Plating Thickness
Hermeticity

10-10

Manufacturing Science - CAM, JIT
In addition to SPC and DOX as key tools to control the
product and processes, Harris is deploying other
management mechanisms in the factory. On first
examination, these tools appear to be directed more
at schedules and capacity. However, they have a significant impact on quality results.
Computer Aided Manufacturing (CAM)
CAM is a computer based inventory and productivity
management tool which allows personnel to quickly
identify production line problems and take corrective
action. In addition, CAM improves scheduling and
allows Harris to more quickly respond to changing
customer requirements and aids in managing work in
process (WIP) and inventories.
The use of CAM has resulted in significant improvements in many areas. Better wafer lot tracking has
facilitated a number of process improvements by correlating yields to process variables. In several places
CAM has greatly improved capacity utilization
through better planning and scheduling. Queues have
been reduced and cycle times have been shortened
- in some cases by as much as a factor of 2.
The most dramatic benefit has been the reduction of
WIP inventory levels, in one area by 500%. This results in fewer lots in the area and a resulting quality
improvement. In wafer fab, defect rates are lower because wafers spend less time in production areas
awaiting processing. Lower inventory also improves
morale and brings a more orderly flow to the area.
CAM facilitates all of these advantages.

3 STEPPERS
3PE'S

PRE INSPECT

/

/

DEV

Just In Time (JITI
A key adjunct to the CAM activity is Just In Time (JIT)
material management. This is more than an inventory
reduction technique: in many cases it involves
reorganization of facilities and people. The essential
concept is to fcrm work units that are responsible for
dOing the whole job rather than bits of it. An employee
has control over equipment, maintenance, cleanliness, scheduling, material, quality, and improvements.
In one Harris example, a photoresist flow consisting
of several steps was previously organized in the classical departmentalized way. The inspection and etch
areas were in different serial locations from the deposition and alignment areas. Work piled up at the
slowest operation (inspection), and quality problems
detected there were decoupled from the areas producing them by 20 to 30 feet and at least one day.
Rework rates were very high; scrap was
unacceptable.
When the area was reorganized into GT (group technology) cells (a basic concept of JIT), the inspection
and alignment areas were physically coupled and
people were organized into teams. The whole job (finished, defect-free wafers) was assigned to the GT cell
(see Figure 3). Rework rates decreased 70%, scrap
rates decreased 45%, and probe yields increased by
50%. This is only one of hundreds of examples of how
JIT has improved our factory performance.
The JIT program/system works. This cultural change
is vital and the benefits derived are impressive.

9PE'S

V
V
V

COAT

V
V
V

Q>

Zt-

~;J
t-c :m
(

COAT

..J c:(..J

:::>w

aD:

BEFORE

AFTER
FIGURE 3. GROUP TECHNOLOGY CELL

10-11

Measurement
Analytical Services Laboratory
Harris facilities, engineering, manufacturing, and product
assurance are supported by the Analytical Services
Laboratory. Organized into chemical or microbeam analysis
methodology, staff and instrumentation from both labs
cooperate in fully integrated approaches necessary to
complete analytical studies. The capabilities of each area
are shown below.
SPECTROSCOPIC METHODS: Colorimetry,
Optical
Emission, Ultraviolet Visible, Fourier Transform-Infrared,
Flame Atomic Absorption, Furnace Organic Carbon
Analyzer, Mass Spectrometer.
CHROMATOGRAPHIC METHODS: Gas Chromatography,
Ion Chromatography.
THERMAL METHODS: Differential Scanning Colorimetry,
Thermogravimetric Analysis, Thermomechanical Analysis.
PHYSICAL
Rheometry.

METHODS:

Profilometry,

Microhardness,

CHEMICAL METHODS: Volumetric, Gravimetric, Specific
Ion Electrodes.
ELECTRON MICROSCOPE: Transmission Electron Microscopy, Scanning Electron Microscope.
X-RAY METHODS: Energy Dispersive X-ray Analysis
(SEM), Wavelength Dispersive X-ray Analysis (SEM),
X-ray Fluorescence Spectrometry, X-ray Diffraction
Spectrometry.
SURFACE ANALYSIS METHODS: Scanning Auger Microprobe, Electron Spectroscope/Chemical Analysis, Secondary Ion Mass Spectrometry, Ion Scattering Spectrometry,
Ion Microprobe.
The department also maintains ongoing working
arrangements with commercial, university, and equipment
manufacturers' technical service laboratories, and can
obtain any materials analysis in cases where Instrumental
capabilities are not available in our own facility.
Calibration Laboratory
Another important resource in the product assurance
system is Harris Semiconductor's Calibration Lab. This area
is responsible for calibrating the electronic, electrical,
electro/mechanical, and optical equipment used in both the
production and engineering areas. The accuracy of
Instruments used at Harris in calibration Is traceable to the
National Bureau of Standards. The lab maintains a system
which conforms to the current revision of MIL-STD-45662,
"Calibration System Requirements."
Each Instrument requiring calibration Is assigned a
calibration interval based upon stability, purpose, and
degree of use. The equipment is labeled with an
identification tag on which is specified both the date of the
last calibration and of the next required calibration. The
Calibration Lab reports on a regular basis to each user

department. Equipment out of calibration is taken out of
service until calibration is performed. The Quality
organization performs periodic audits to assure proper
control in the using areas. Statistical procedures are used
where applicable in the calibration process.

Field Return Product Analysis System
The purpose of this system is to enable Harris' Field Sales
and Quality operations to properly route, track and respond
to our customers' needs as they relate to product analysis.
The Product Failure Analysis Solution Team (PFASn
consists of the group of people who must act together
to provide timely, accurate and meaningful results to
customers on units returned for analysis. This team includes
the salesman or applications engineer who gets the parts
from the customer, the PFAST controller who coordinates
the response, the Product or Test Engineering people who
obtain characterization and/or test data, the analysts
who failure analyze the units, and the people who provide
the ultimate corrective action. It is the coordinated effort of
this team, through the system described in this document
that will drive the Customer responsiveness and continuous
Improvement that will keep Harris on the forefront of the
semiconductor business.
The system and procedures define the processing of
product being returned by the customer for analysis
performed by Product Engineering, ReliabilHy Failure
Analysis and/or Quality Engineering. This system is
designed for processing "sample" returns, not entire lot
returns or lot replacements.
The philosophy is that each site analyzes its own product.
This applies the local expertise to the solutions and helps
toward the goal of quick turn time.
Goals: quick, accurate response, uniform deliverable
(consistent quality) from each site, traceability.
The PFAST system Is summarized in the following steps:
1) Customer calls the sales rep about the unit(s) to return.
2) Fill out PFAST Action Request - see the PFAST form in
this section. This form is all that Is required to process a
Field Return of samples for failure analysis. This form
contains essential information necessary to.perform root
cause analysis. (See copy of page 10-14).
3) The unHs must be packaged in a manner that prevents
physical damage and prevents ESD. Send the units and
PFAST form to the appropriate PFAST controller. This
location can be determined at the field sales office or rep
using "look-up" tables In the PFAST document.
4) The PFAST controller will log the units and route them to
ATE testing for data log.
5) Test results will be reviewed and compared to customer
complaint and a decision will be made to route the fallure
to the appropriate analytical group.

10-12

6) The customer will be contacted with the ATE test results
and interim findings on the analysis. This may relieve a
line down situation or provide a rapid disposition of
material. The customer contact is valuable in analytical
process to insure root cause is found.
7) A report will be written and sent directly to the customer
with copies to sales, rep, responsible Individuals with
corrective actions and to the PFAST controller so that
the records will capture the closure of the cycle.
8) Each report will contain a feedback form (stamped and
preaddressed) so that the PFAST team can assess their
performance based on the customers assessment of
quality and cycle time.
9) The PFAST team objectives are to have a report In the
customers hands in 28 days, or 14 days based on
agreements. Interim results are given realtime.
Failure Analysis Laboratory
The Failure Analysis Laboratory's capabilities encompass
the isolation and identification of all failure modes/failure
mechanisms, preparing comprehensive technical reports,
and assigning appropriate corrective actions. Research vital
to understanding the basic physics of the failure is also
undertaken.
Failure analysis is a method of enhancing product reliability
and determining corrective action. It is the final and crucial
step used to isolate potential reliability problems that may
have occurred during reliability stressing. Accurate analysis
results are imperative to assess effective corrective actions.
To ensure the Integrity of the analysis, correlation of the
failure mechanism to the initial electrical failure Is essential.
A general failure analysis procedure has been established
in accordance with the current revision of MIL-STD-883,
Section 5003. The analysis procedure was designed on the
premise that each step should provide information on the
failure without destroying information to be obtained from
subsequent steps. The exact steps for an analysis are
determined as the situation dictates. (See Figures 4 and 5).
Records are maintained by laboratory personnel and
contain data, the failure analyst's notes, and the formal
Product Analysis Report.

Reliability
Reliability Assessment and Enhancement
At Harris Semiconductor, reliability is built into every product by emphasizing quality throughout manufacturing. This
starts by ensuring the excellence of the design, layout, and
manufacturing process. The quality of the raw materials and
workmanship is monitored using statistical process control
(SPC) to preserve the reliability of the product. The primary
and ultimate goal of these efforts is to provide full performance to the product specification throughout its useful life.
Product reliability is maintained through the following
sources: Qualifications, In-Line Reliability Monitors, Failure
Analysis.

Qualifications
Qualifications at Harris de-emphasize the sole dependence
on production product which Is only available late in the
development cycle. The focus is primarily on the use of test
vehicles to establish design ground rules for the product
and the process that will eliminate any wearout
mechanisms during the useful life of the product. However,
to comply with the military requirements concerning reliability, product qualifications are performed. (See Figure 6).
In-line Reliability Monitors
In-line reliability monitors provide immediate feedback to
manufacturing regarding the quality of workmanship,
quality of raw materials, and the ultimate reliability
implications. The rudimentary implementation of this
monitoring is the "First Line of Defense," which is a pass/
fail acceptance procedure based on control charts and
trend analysis. The second level of monitoring is referred to
as the "Early Warning System" and incorporates wafer level
reliability concepts for extensive diagnostic and
characterization capabilities of various components that
may impact the device reliability or stability. The quick
feedback from these schemes allows more accurate
correlation to process steps and corrective actions.

Product/Package Reliability Monitors
Reliability of finished product is monitored extensively
under a program called Matrix I, II, III monitor. All major
technologies are monitored.
Matrix I - Has a higher sampling size and rate per week and
uses short duration test, usually less than 48 hours to assess day to day, week to week reliability. High volume types
are prevalent in this data. Stresses - Operating Life, Static
Life and HAST. TA = +125 0 C to +2000 C
Matrix II - Longer duration test, much like requalification.
The sample sizes are reduced in number and frequency,
yet meet or exceed the JEDEC Standard 29. Stresses
Operating Life, Storage, THB, Autoclave, Temp Cycle, and
Thermal Shock.
Matrix III - Package specific test. Tests Solderability, Lead
Fatigue,
Physical
Dimensions,
Brand
Adhesion,
Flammability, Bond Pull, Constant Acceleration, and
Hermeticity.
Data from these Monitor Stress Test provides the following
information:
• Routine reliability monitoring of products by die
technology and package styles.
• Data base for determining FIT Rates and Failures Mode
trends used drive Continuous Improvement.
• Major source of reliability data for customers.
• Customers have used this data to qualify Harris
products.

10-13

m~6BBt§

Requost #
Customer Analysis #

PFAST ACTION REQUEST
Date:

ORIGINATOR

CUSTOMER

No.
TYPE/PART No.

LoCATION/PHONE

LOCATION

DEVICE

PURCHASE ORDER

No.

SAMPLES RETURNED

No.

QUANTITY RECEIVED

THE COMPLETENESS AND TIMELY RESPONSE OF THE EVALUATION IS DIRECTLY RELATED TO THE COMPLETENESS
OF THE DATA PROVIDED. PLEASE PROVIDE AlL PERTINENT DATA. ATTACH ADDmONAL SHEETS IF NECESSARY.

DETAIlS OF REJECT

TYPE OF PROBLEM
1. 0

(Where .1ppropriare serialize uaits aad specify for each)
TEsT CONDmONS RELATING TO FAILURE

INCOMING INSPECTION
SAMPLE INSPECTION
0100% ScREEN
No. TEsTED
No. OF REJECTS
ARE RESULTS REPRESENTATIVE OF PREVIOUS LOTS?
DYES
NO
BRIEF DESCRIPTION OF EVALUATION
AND RESULTS ATTACHED
2. 0 IN PROCESSiMANUFACTURING FAILURE
BOARD CHECKOUT
SYSTEM CHECKOUT
FAILED ON TURN-ON
FAILED AFTER
HOURS OPERATION
WAS UNIT RETESTED UNDER INCOMING INSPECTION
CONDmoNS?
YES
NO
BRIEF DESCRIPTION OF HOW FAILURE WAS ISOLATED
TO COMPONENT ATTACHED
3 . 0 FIELD FAILURE
FAILED AfTER
HOURS OPERATION
EsTIMATED FAILURE RATE _ _% PER 1000 HOURS

o

--

o
o
o

--

o

o

o
o
o

0

TEsTER USED (MFGR/MODEL)
TEsT TEMPERATURE
TEsTnME:
CONTINUOUS TEsT
ONE SHOT (T = _ _ SEC)

o
o

DESCRIPTION OF ANY OBSERVED CONDmON TO
WHICH FAILURE APPEARS SENsmVE:

o

1. 0

DC FAILURES
OPENS 0 SHORTS 0 LEAKAGE 0 STRESS
POWER DRAIN 0 INPUT LEVEL 0 OUTPUT LEVEL
UsT OF FORCING CONDmONS AND MEASURED
RESULTS FOR EACH PIN IS ATTACHED
POWER SUPPLY SEQUENCING ATTACHED
2 . 0 AC FAILURES
UsT FAILING CHARACTERISTICS

--

o

o

o

--

END USER
AMBIENT TEMPERATURE

MIN.

-- C

LocATION

MAx.

--

C

ADDRESS OF FAiUNG LOCATION (IF APPUCABLE)

C

REI.. HUMIDITY
%
END USER FAILURE CORRESPONDENCE ATTACHED

o

ACITON

o
o
o
o

REQUESTED

BY

ATTACHED:

o LIST OF POWER SUPPLY AND DRIVER LEVELS
(Include pictures of waveforms).
o UsT OF OUTPUT LEVELS AND LOADING CONDmONS
o INPUT AND OUTPUT nMING DtAGRAMS
o DESCRIPTION OF PATTERNS USED

CUSTOMER

SPECIFIC ACTION REQUESTED
IMPACT OF FAILED UNITS ON CUSTOMER'S SITUATION:

---

(If not standard patterns, give very complete
description including address sequence).
3 . 0 PROM PROGRAMMING FAILURES
ADDRESS OF FAILURES
PROGRAMMER USED (MFG/MoDE1lREV. No.)

CUSTOMER CONTACTS wrm SPECIFIC KNOWLEDGE OF REIECTS
NAME
PosmON

PHONE

4.0 PHYSICAI.lAssEMBLY RELATED FAILURES
SEE COMMENTS BELOW 0 SEE ATTACHED

o

Additional Comments:

10-14

Reliability Fundamentals
Reliability, by its nature, is a mixture of engineering and
probability statistics. This combination has derived a
vocabulary of terms essential for describing the reliability of
a device or system. Since reliability involves a measurement
of time, it is necessary to accelerate the failures which may
occur. This, then, introduces terms like "activation

energy" and "acceleration factor," which are needed to
relate results of stressing to normal operating conditions
(see Table 7). Also, to assess product reliability requires
failures. Therefore, only a statistical sample can be used to
determine the model of the failure distribution for the entire
population of product.

TABLE 7. FAILURE RATE PRIMER
GLOSSARY OF TERMS
UNITS/DESCRIPTION

TERMS/DEFINITION
FAILURE RATE A.

FIT - Failure In Time

For Semiconductors, usually expressed In FITs.

1 AT - 1 failure in 109 device hours.
Equivalent to 0.0001 %/1 000 hours
FITs =
# Failures
xl09 xm

Represents useful life failure rate (which Implies a constant
failure rate).
FITs are not applicable for infant mortality or wearoul failure
rate expressions.

# Devices x # hours stress x AF

MTTF - Mean Tome To Failure

Mean Tome is measured usually in hours or years.

m- Factor to establish Confidence Interval
109 - Establishes in terms of ATs
AF - Acceleration Factor at temperature for a given failure
mechanism

For semiconductors, MTIF is the average or mean life expectancy
ofadevice.

If an exponential distribution is assumed then the mean time to
fail of the population will be when 63% of the parta have failed.

1 Year = 8760 hours
When working with a constant failure rate the MTIF can be
calculated by taking the reciprocal of the failure rate.
MTIF = I/A. (exponential model)
Example: =10 ATs at +550 C
The MTIF is: MTIF = IIA. = 0.1 x 109 hours
=IOOMhours

CONFIDENCE INTERVAL (C. I.)

Example:

Establishes a Confidence Interval for failure rate predictions.
Usually the upper limit is most significant in expressing failure
rates.

"10 FITs @ a 95% C.I. @ 55o C" means only that you are 95%
certain the the FITs <10 al +550 C use conditions.

10-15

Failure Rate Calculations
Reliability data for products may be composed of
several different failure mechanisms and requires
careful combining of diverse failure rates into one
comprehensive failure rate. Calculating the failure rate
is further complicated because failure mechanisms
are thermally accelerated at varying rates and thereby
have differing accelerating factors. Additionally, this
data is usually obtained a variety of life tests at unique
stress temperatures. The equation below accounts for
these considerations and then inserts a statistical factor to obtain the confidence interval for the failure rate.
FIT =

xM

B=

# of distinct possible failure mechanisms

K=

# of life tests being combined

Xi =

# of failures for a given failure mechanism
1= 1, 2, ... B

TDGj =

Total
device hours
of
(unaccelerated) for Life Testj

test

time

In the failure rate calculation, Acceleration Factors (AFij)
are used to derate the failure rate from thermally accelerated Life Test conditions to a failure rate indicative of
use temperatures. Though no standards exist, a temperature of +SsoC has been popular and allows some
comparison of product failure rates. All Harris
Semiconductor Reliability Reports will derate to +SsoC
at both the 60% and 9S% confidence intervals.
Acceleration Factors
The Acceleration Factors (AF) are determined from the
Arrhenius Equation. This equation is used to describe
physiochemical reaction rates and is an appropriate
model for expressing the thermal acceleration of
semiconductor failure mechanisms.
EXP [

AF =

Acceleration Factor

Ea =

Thermal Activation Energy in eV from Table 8

K=

AFij=

Acceleration factor for appropriate failure
mechanism i = 1, 2, ... K

M=

Statistical factor for calculating the upper
confidence limit (M is a function of the total
number of failures and an estimate of the
standard deviation of the failure rates)

Ea ( 1
K
Tuse

AF=

Boltzmann's Constant (8.62 x 1o-S eVJOK)

Both Tuse and Tstress (in degrees Kelvin) include the
internal temperature rise of the device and therefore
represent the junction temperature. With the use of the
Arrhenius Equation, the thermal Activation Energy (Ea)
term is a major influence on the result This term is
usually empirically derived and can vary widely.

FIGURE 4. NON-DESTRUCTIVE

FIGURE 5. DESTRUCTIVE

10-16

Activation Energy
To determine the Activation Energy (Ea) of a
mechanism (see Table 8) you must run at least two
(preferably more) tests at different stresses (temperature anQ/or voltage). The stresses will provide the time
to failure (Tt) for the populations which will allow the
simultaneous solution for the Activation Energy by
putting the experimental results into the following
equations.
In

(tf1)

=C +

Ea

+

Ea

= Ea/k(1 /T1-1 /T2)

= K* ((In(tf1) -

In(tf2»/(1/Ti - 1/T2»

The Activation Energy may be estimated by graphical
analysis plots. Plotting In time and In temperature then
provides a convenient nomogram that solves (estimates) the Activation Energy.
Table 9 is a summary of military generic groups by
process descriptions.

KT1
C

In(tf1) - In(tf2)

Ea
KT2

Then, by subtracting the two equations, the Activation
Energy becomes the only variable, as shown.
TABLE 8.

All Harris Reliability Reports from qualifications and
Group C1 (all high temperature operating life tests)
will provide the data on all factors necessary to calculate and verify the reported failure rate (in FITs) using
the methods outlined in this primer.

FAILURE MECHANISM

FAILURE
MECHANISM

ACTIVATION
ENERGY

SCREENING AND
TESTING METHODOLOGY

Oxide Defects

O.3-0.SeV

High temperature operating lile (HTOl) and
voltage stress. Defect density test vehicles.

Statistical Process Control of oxide parameters,
defect density control, and voltage stress testing.

Silicon
Defects (Bulk)

O.3-0.SeV

HTOl & voltage stress screens.

Vendor Statistical Quality Control programs, and
Statistical Process Control on thermal processes.

Highly accelerated stress tesing (HAST)

Passivation dopant control, hermetic seal control,
improved mold compounds, and product handling.

Temperature CYCling, temperature and
mechanical shock, and environmental
stressing.

Vendor Statistical Quality Control programs,
Statistcal Process Control of assembly processes
proper handling methods.

Test vehicle characterizations at highly
elevated temperatures.

Design ground rules, wafer process statistical
process steps, photoresist, metals and
passivation

Corrosion

O.45eV

Assembly
Defects

O.S-O.7eV

Electromigration
- AI Line
- Contact

O.SeV
O.geV

CONTROL METHODOLOGY

Mask Defectsl
Photoresist
Defects

O.7eV

Mask FAB comparator, print checks, defect
density monitor in FAB, voltage stress test
andHTOL.

Clean room control, clean mask, pellicles
Statistical Process Control or photoresistletch processes.

Contamination

1.0eV

C-V stress at oxidelinlerconnect, wafer
FAB device stress test (EWS) and HTOL.

Statistical Process Control of C-V data, oxidel
Interconnect cleans, high Integrity glassivation
and clean assembly processes.

Charge
Injection

1.3eV

HTOl & oxide characterization.

Design ground rules, wafer level Statistical
Process Control and critical dimensions for
oxides.

10-17

Qualification Procedures
New products are reliably introduced to market by the
proper use of design techniques and strict adherence
to process layout ground rules. Each design is
reviewed from its conception through early production to ensure compliance to minimum failure rate
standards. Ongoing monitoring of reliability performance is accomplished through compliance to 883C
and standard Quality Conformance Inspection as
defined in Method 5005.
New process/product qualifications have two major
requirements imposed. First is a check to verify the
proper use of process methodology, design techTABLE 9.

niques, and layout ground rules. Second is a series of
stress tests designed to accelerate failure mechanisms and demonstrate the reliability of integrated circuits.
From the earliest stages of a new product's life, the
design phase, through layout, and in every step of the
manufacturing process, reliability is an integral part of
every Harris Semiconductor product. This kind of attention to detail "from the ground up" is the reason
why our customers can expect the highest quality for
any application.

HIGH TEMPERATURE OPERAT!NG- UFE TEST SUMMARY

GROUPC
GENERIC
GROUP

HOURS
@1250C

FAILURE
RATE FITs
@550C60%CI

QUANTITY

QUANTITY
FAILURE

D-49-3

Op. AmplHiers

Std. Linear, DI w/NiCr resistors

3482

8

3,215,708

62

D-49-4

Op. AmplHiers

Std. Linear, DI w/NiCr resistors

324

1

429,945

17

D-53

High Voltage
Op. Amplifiers

High voltage 01

315

0

284,943

20

0-58

OataAcquisition

High beta high frequency, 01, NiCr

1022

5

1,868,349

100

0

403,960

5

0

183,222

10

GROUP NAME

PROCESS DESCRIPTION

F-l03

Telecommunications

SAJIIVA

199

F-81-3

AID Converters

SAJIIVA

201

F-81-4

NO Converters

SAJIIVA

217

1

328,000

12

'F-82

Switches & Mux

01 AI Gate & Si Gate MOS

121

0

82,836

23

F-99-3

Active Rlters

SAJIIVA

196

1

184,262

24

F-99-4

Active Rlters

SAJIIVA

407

1

470,324

9

G-85

Op.Amplifiers

Std. Linear, MOS, & High
Frequency JFET

532

1

535,728

11

G-86

Comparators

Combination, Std. Linear & MOS

G-94-3

Switches & Mux

DI AI & SI Gate Linear CMOS

154

0

153,400

25

4351

41

7,443,054'

103

G-94-4

Switches & Mux

01 AI & 51 Gale Linear CMOS

C-41-4

CMOS RAMs

SAJICMOS

906

0

889,816

20

2418

19

2,247,526-

31

C-41-5

CMOS RAMs

SAJICMOS

1104

C-42-4

CMOS PROMs &
HPALs

SAJICMOS

2645

10

1,105,094

53

28

4,074,728

61

0.105-4

Microprocessor and
Peripherals

SAJICMOS

3638

12

4,099,002

17

NOTE: All Infant mortality failures (up to 168 hours or equivalent) have been removed from products sampled.

10-18

RELIABILITY FOCUS

FLOW - PRODUCT DEVELOPMENT

I

PRODUCT DEFINITION REVIEW

I

• Assumes Process Development Required

I

CONCEPT REVIEW

I

• Evaluate Reliability Risks Factors
• Attain CommilmenlforTestVehicle (T.V.) Development

I

DESIGN REVIEW PART 1

l-

• Review Test Vehicle Development and Stress Test Plan
• Review Package Requirements
• Review Latent Failure Mechanism Historyfor Design Sensitivity and Elimination
• Review Ground Rules for Design and Elimination of Wearout Mechanisms
• Review Process Characterization, Statistical Control & Capability which are Design
Considerations

I

DESIGN REVIEW PART2

I..

• Review Test Vehicle Stress Results
• Review Device Modeling & Simulations
• Review Process Variability & Producibility
• Define Wafer Reliability MonitorVehicles, Application of Early Warning System

I

LAYOUT REVIEW PART 1

~

• Verify Wearout Mechanisms are Eliminated by Design & Process Control
(Test Vehicle + SPC)
• Evaluate Design of Chip to Package Risk Factors
• Review Ground Rule Checks (DRCs)
• Establish Reliability Tes~ Stress and Failure Analysis Capabilities. Project Failure Rate
Based on T.V. Data.

I

LAYOUT REVIEW 2

I

• Review Burn-In Diagrams for Production and Qualification
• Review Overall Qualification Plan & Begin Balance of Life Test

I

EVALUATION REVIEW

I

• Review Product Characterization to Data Shee~ ESD, Latch-up & DPA Results &
Define Corrective Actions
• Review of Life Test Data & Failure Mechanisms. Define Corrective Actions
• Utilize Statistical Design of Experiments (DOX) if Required to Adjust Process or Design
• Define Necessary Changes to Eliminate Any Systematic Failure Mechanism

• If Mature Process - Grant Generic Release

I
--I

NEW PRODUCT TRANSFER

MANUFACTURE

I
I-

• Qualification Requirements Complete and Presented. Meet FIT Rate Requirements
• Review Infant Mortality (I.M.) Burn-in Results. If Greater Than 1% at 1250 C
Determine I.M. Burn-in Requirements
• Reliabilliy Monitors:
• Real Time Early Warning Wafer Level Reliability control
• Real Time Reliability Control of Burn-in PDA with Control Charts
• Add-On Life Testing: - Mil Sid Group C & 0
- Industrial/Commercial Life Testing
• Trend Analysis of Reliability Performance Used to Develop Product Improvements
• Special Studies

I
-I

SHIPMENT

CONTINUOUS IMPROVEMENT

I

• High Quality and Reliability Products to Harris Customers

I-

• Failure Analysis - Determine Assignable Cause of Failure
• Closed Loop Corrective Action Process
• Continuous Improvement Objectives in Product Reliability & Quality

FIGURE 6. NEW PROCESS PRODUCT DEVELOPMENT AND LIFE CYCLE

10-19

APPUCATDON NOTIE ABSTRACTS

AN#

TITLE

ABSTRACTS

509

A Simple Comparator
Using The HA-2620

Performance characteristics, application schematics, output parameter control
methods.

514

The HA-2400 PRAM
Four Channel
Operational Amplifier

HA-2400 PRogrammable Analog Microcircuit description, frequency compensation,
applications (analog multiplexer, non-inverting programmable gain amplifier, inverting
programmable gain amplifier, programmable attenuator, programmable adder-subtractor,
phase selector, phase detector, synchronous rectifier, balanced modulator, integrator,
ramp generator, track and hold, sample and hold, sine wave oscillator, multivibrator, active
filter, programmable power supply, comparator, multiplying D/A converter).

515

Operational Amplifier
Stability: Input Capacitance Considerations

Input capacitance and stability, capacitive feedback compensation, guidelines for
compensation requirements.

517

Applications of a Monolithic Sample and Hold/
Gated Op Amp

General Sample and Hold Information and fourteen specific applications, including
filtered Sample & Hold DAC de-glitcher, Integrate-Hold-Reset, gated op amp, etc.

519

Operational Amplifiers
Noise Prediction.

Noise model and equations, procedure for computing total output noise, example,
broadband noise measurement, spot noise prediction techniques, typical spot noise
curves, popcorn noise discussion.

525

HA-5190/5195 Fast
Settling Operational
Amplifier

Internal schematic, prototyping considerations, frequency compensation, performance
enhancement methods, applications.

526

HA-5190/5195 Video
Applications

Video applications, video response tests, SIN ratio measurements, power supply
requirements temperature considerations, design hints, prototyping tips, RF AGC
amplifier, DC gain controlled video amplifier.

538

Monolithic Sample/Hold
Combines Speed and
Precision

Description and electrical specifications for the HA-5320 Sample/Hold Amplifiers,
explanation of errors sources, and HA-5320 applications.

540

HA-5170 Precision Low
Noise J-FET Input
Operational Amplifier

Internal design and technology, J-FET noise discussion, trimming of offset voltage,
single op amp Instrumentation Amplifier, sine wave oscillator, high Impedance
transducer interface, current source/sink and current sense circuits.

541

Using HA-2539/2540
Very High Slew-Rate
Wideband Operational
Amplifiers

Prototyping considerations, output short circuit protection, offset voltage adjustment,
frequency compensation, composite amplifier scheme, DC error reduction, boosting
output current, increasing output signal swing, cascade amplifier, video gain block,
high frequency oscillator, wideband signal splitter.

544

Micropower Op Amp
Family, HA-514X,

Operation, noise performance, applications (remote sensor loop transmitter, charge
pool power supply, low power microphone preamplifier, AGC with squelch control,
Wein bridge oscillator, bar code scanner, monostable multivibrator).

11-1

Application Note Abstracts

(Continued)

ABSTRACTS

AN#

TITLE

546

A Method of Calculating
HA-2625 Gain Bandwidth Product vs.
Temperature

A method of calculating Gain Bandwidth product performance versus temperature for
the HA-2625 Op Amp.

548

A Designer's Guide for
the HA-5033
Video Buffer

Operation, video performance, video parameter specifications, Y parameters, applications (flash converter pre-driver, coaxial line driver, video gain block, high speed
sample and hold, audio drivers, crystal oscillator).

549

The HC-550X Telephone
Subscriber Line Interface
Circuit

Complete description of device functionality and applications of SLiC.

550

Using the HA-2541

Prototyping guidelines, thermal considerations and heat sinking, performance enhancements, applications (Wein bridge oscillator, high power gain stage, video stage with
clamp, multiplexer/demultiplexer, disk drive write amplifier, gain programmable amp,
composite amp).

551

Recommended Test
Procedures for
Operational Amplifiers

Operational amplifier test procedures for offset voltage, bias current, offset current,
power supply rejection ratio, common mode rejection ratio, output voitage swing,
output current, open loop gain, slew rate, full power bandwidth, transient response,
settling time, GBP, phase margin, noise voltage and current, and channel seperation.

552

Using the HA-2542

Prototyping guidelines, thermal considerations and heat sinking, performance enhancements, applications (multi-channel security system, unbalanced coaxial driver, flash
converter driver, programmable power supply, bridge load driver, high current stage,
differential line driver, DC motor speed control).

553

Using the HA-5147/
5137/5127

Construction and operation, low noise design applications (instrumentation amplifier
bridge sensor, multiplexer, precision threshold detector, audio driver, NAB amplifier,
multivibrator, programmable gain stage, log amp, professional mixer).

554

Low Noise Family
HA-51 01/51 02/51 04/
5112/5114

Low noise design, operation, applications (Electronic scales, programmable attentuator,
Baxandal circuit, RIAA amplifier, NAB preamplifier, microphone amplifier, standard and
simple biquads, professional mixer.

556

Thermal SafeOperating-Areas for
High Current Op Amps

Thermal management equations and curves Indicating areas of VOUT and lOUT safe
operation. Also, the effects of packaging and heat sinking are examined.

558

Using the HV1205 AC to
DC Converter

Explains the basic theory of operation of the HV-1205. Presents a discussion of
external components required for operation, PC board layout recommendations and
safety considerations

571

Using Ring Sync with
HC-5502A and HC5504
SLiCs

Describes use of the SLiCs Ring Synchronization pin and why you should us it.

573

The HC-5560 Digital
Line Transcoder

Full functional and applications description of HC-5560 transcoder and line codes.

574

Understanding PCM
Coding

The process of converting analog voice signals into Time Division Multiplexed (TDM)
Pulse Code Modulated (PCM) format is described and illustrated.

607

Delta Modulation for
Voice Transmission

Introduction to delta modulation coding techniques, 4 general applications, including
digital transmission encryption, voice scrambling and audio delay. Also CVSD evaluation guidelines.

11-2

Application Note Abstracts

(Continued)

ABSTRACTS

AN#

TITLE

9006

HV-2405E Operation from Full Bridge

A brief discussion of function of the source resistor (R1) and the benefits of using a
bridge rectifier to reduce the power dissipation in R 1. Presents several points to be
kept in mind when implementing the full bridge (i.e. safety aspects, filtering of output so
device will reset for the next cycle and circuit operation verification with test equipment).

9101

High Current Off Line
Power Supply

Explains the basic theory of operation of the HV-1205/2405E and show how to increase the maximum output current from 50mA to greater than 250mA. A detailed description of the circuit operation, to achieve the higher currents, is presented along with
suggestions for external component selection.

A007

Using the 8048/8049
Monolithic Log-AntiLog Amplifier

Describes in detail the operation of the 8048 logarithmetic amplifier, and its counterpart, the 8049 anti-log amp.

A013

Everything You Always This note includes 17 of the most asked questions regarding the use of the 8038.
Wanted to Know About
the 8038

A027

Power Supply Design
Using the ICL8211
and ICL8212

Explains the operation of the ICL8211/12 and describes various power supply configurations. Included are positive and negative voltage regulators, constant current
source, programmable current source, current limiting, voltage crowbarring, power
supply window detector, etc.

A040

A Precision Four
Quadrant MultiplierThe 8013

Describes, i~ detail, the operation of the 8013 analog multiplier. Included are multiplication, division, and square root applications.

A051

Principles and
Applications of the
ICL7660 CMOS
Voltage Converter

Describes internal operation of the ICL7660. Includes a wide range of possible
applications.

A053

The ICL7650 - A
New Era in GlitchFree Chopper
Stabilizer Amplifiers

A brief discussion of the internal operation of the ICL7650, followed by an extensive
applications section including amplifiers, comparators, log-amps, pre-amps, etc.

ICAN5290

General Purpose
Op Amps

Discusses various uses of op amps

ICAN5296

CA3018

Transistor Array

ICAN5337

CA3028

RF amplifiers in the HF and VHF ranges.

ICAN5380

FM IF Amplifiers

Discusses differential amplifier configurations.

ICAN5766

CA3020

Multipurpose wideband power amplifiers

ICAN6048

CA3094

Programmable power switch/amplifier.

ICAN60n

CA3094

OTA with power capability.

ICAN6157

CA3085

Monolithic voltage regulators.

ICAN6182

CA3059

Zero-voltage switches.

ICAN6247

CA3126

Chroma processing IC using sample and hold circuit techniques.

11-3

Application Note Abstracts
AN#

TITLE

(Continued)

ABSTRACTS

ICAN6257

CA3089

FM IF Subsystem.

ICAN6386

CA3130

Understanding BiMOS op amps.

ICAN6459

CA3130

Why and how to use the BIMOS op amp.

ICAN6472

CA3126

A chrominance demodulator IC with dynamic flesh correction.

ICAN6525

IC Handling

Guide to IC handling.

ICAN6668

CA3080

High performance OTA.

ICAN6669

CA3240

BiMOS op amp mates directly to system sensors.

ICAN6732

Noise Measurement

Measurement of burst noise and "popcorn" noise in ICs.

ICAN6818

CA3280

OTA simplifies complex analog designs.

ICAN6915

CA1524

Pulse-width modulators.

ICAN6998

Telecom

Telephony in Digital Evolution.

ICAN7037

Telecom

Logarithmic units of measure in telecommunications.

ICAN7127

CA3420

BiMOS amplifier circumvents low voltage limitations.

ICAN7174

CA1524

Pulse-width modulator in an electronic scale.

ICAN7175

CA3217

Integrated NTSC chrominance/luminance processor

ICAN7304

SCR Protection

Discusses SCR Protection Circuits for ICs.

ICAN8636

Video Devices

Discusses advanced video speed switches, multiplexers, crosspoints and buffer
amplifiers.

ICAN8707

CA3450

Single chip video line driver-high speed op amp.

ICAN8742

CD22402

Sync Generator

ICAN8811

CA5470

BiMOS-E process enhances quad op amp.

ICE-402

Operating
Considerations

Discusses operating considerations for solid state devices.

Harris Analog Spice Macro-Models available upon request.

11-4

PACKAGING AND ORDERING INFORMATION
PAGE
SOIC PACKAGING INFORMATION .............................................................. 12-2
CAlCD-TVPE PACKAGING & ORDERING INFORMATION .........•............................... 12-5
PACKAGE OUTLINES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . • . • . •• • . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-6
HAlHC/HFAlHV-TVPE PACKAGING & ORDERING INFORMATION ...................•............ 12-16
PACKAGE OUTLINES. . . . . . . . . . . . . . . . . . . . . . . . • . . . • .• . • . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-17
HVlICL/ICM-TYPE PACKAGING & ORDERING INFORMATION .................................... 12-22
PACKAGE OUTLINES ............•....•..•.......•.............................................. 12-23

o

.

zO
 Quality Assurance Step

Package Outlines
Dual-In-Line Welded-Seal Ceramic Package
(D) SUFFIX
16-LEAD DUAL-IN-LINE WELDED-SEAL CERAMIC PACKAGE
INCHES
MIN.

MAX.

MIN.

MAX.

A

0.120

0.160

3.05

4.06

Al

0.020

0.065

0.51

1.65

B

0.014

0.020

0.356

0.508

Bl

0.050

0.065

1.27

1.65

C

0.008

0.012

0.204

0.304

0

0.745

0.840

18.93

21.33

E

0.300

0.325

7.62

8.25

El

0.240

0.260

6.10

6.60

Q' GEl
BOTTObyJl. r
c1

-~---:) -1..

~
-""'' '---;-'

!

INDEX AREA
1

2

3

I

N

F'l F'l F'l

MILLIMETERS

SYMBOL

tf
"
r

NOTES

1

el

O.IOOTP

2.54TP

2

eA

0.300TP

7.62TP

2,3

L

0.125

0.150

3.18

3.81

L2

0.000

0.030

0.000

0.76

a

0°

15°

0°

15°

N

16

16

Nl

0

0

4
5
6

Ql

0.050

0.085

1.27

2.15

S

0.065

0.090

1.66

2.28

NOTES:
Refer to Rules for Dimensioning (JEDEC Publication No. 95) for Axial Lead
Product Ouillne•.

1. When this device Is supplied solder-dipped, the maximum lead thickness
(narrow portion) will not exceed 0.013",

2. Lead. wHhin 0.005" (0.1 2mm) radius of True Poollion (TP) at gauge plane
with maximum material condition and unit installed.
3. eA applies in zone l2 when unit installed.

4. a. applies to spread leads prior to installation.
5. N Is the maximum quantity of lead positions.
6. N 1 Is the quantity of allowable missing leads.

12-6

Dual-In-Line Plastic Packages

(E) SUFFIX (JEDEC MS-001-AB)
8 LEAD DUAL-IN-LiNE PLASTIC PACKAGE
INCHES
SYMBOL

MAX.

MIN.

A

0.210

INCHES

0.115

0.195

2.93

4.95

0.39

0.558

A

MIN.

0.210

B

0.014

0.022

0.356

0.045

0.070

1.15

1.77

C

0.008

0.Q15

0.204

0.381

0.430

8.84

10.92

0

0.348
0.005

E

0.300

0.325

7.62

8.25

5

El

0.240

0.280

6.10

7.11

6.7

0.13

a

0.100BSC

2.54BSC

aA

0.300BSC

7.62BSC
10.92

0.430
0.115

0.160

2.93

8

4.06

INCHES

A

9

Al

0.015

A2

0.115

0.195

2.93

4.95
0.558

0.195

2.93

4.95

B

0.014

0.022

0.356

0.558

Bl

0.045

0.070

1.15

1.77

C

0.008

0.Q15

0.204

0.381

0.795

0

0.725

01

0.005

20.19

E

0.300

0.325

7.62

8.25

El

0.240

0.280

6.10

7.11

0.13

3

MAX.

MIN.

MIN.

0.210

MAX.

NOTES

5.33

9

0.39

9

B

0.014

0.022

0.356

Bl

0.045

0.070

1.15

1.77

C

0.008

0.Q15

0.204

0.381

0.840

21.33

4

0

0.745

01

0.005

5

E

0.300

0.325

7.62

8.25

5

6.7

El

0.240

0.280

6.10

7.11

6.7

18.93
0.13

0.100BSC

2.54BSC

8

a

0.100BSC

2.54BSC

0.300BSC

7.62 BSC

9

aA

0.300 BSC

7.62BSC

10

aB

L

10.92

0.115

N

0.160
14

2.93

4.06
14

9

L

11

N

NOTES:
1. Refer to JEOEC Publication No. 95 JEOEC Registered and Standard Outlines
for Solid State Products, for rules and general information concerning registered and standard outlines, in Seclion 2.2.

2. Protrusions (flash) on the base plane surface shall not exceed 0.010"
(0.25mm).

3. The dimension shown is for full leads. "Half" leads are optional at lead
positions

1.N.

N

.!::

2

2

+1.

4. Dimension 0 does not include mold flash or protrusions. Mold flash or protru"
sians shall not exceed 0.010" (0.25mm)
5. E Is the dimension to the outSide of the leads and is measured with the leads
perpendicular to the base plane (zero lead spread~
6. Dimension E1 dOBS not include mold flash or protrusions.
7. Package body and leads shall be symmetrical around center line shown in

end view.

10.92

0.430
0.115

0.160
16

4
12

a

0.430

3

12

aA
aB

9

MILLIMETERS

9

0.115

9
10

(E) SUFFIX (JEDEC MS-001-AA)
16 LEAD DUAL-IN-LiNE PLASTIC PACKAGE

5.33

A2

8

11

8

SYMBOL

0.39

4
12

NOTES

0.Q15

3

01

MAX.

Al

18.42

9

Bl

MILLIMETERS

MAX.

9

A2

L

MIN.

NOTES

5.33

0.015

N

SYMBOL

MAX.

Al

a8

(E) SUFFIX (JEDEC MS-001-AC)
14 LEAD DUAL-IN-LiNE PLASTIC PACKAGE

MILLIMETERS
MIN.

2.93

4.06
16

8
9
10
9
11

8. Lead spacing e shall be non-cumulative and shall be measured at the lead
tip. This measurement shall be made before insertion into gauges, boards or
sockers.
9. This is a basic installed dimension. Measurement shall be made with the device installed in tl"-e seating plane gauge (JEDEC Oullins No. GS-a, seating
plane gauge). Leads shall be'" true posHion within 0.01 0" (O.2Smm) diameter for dimension eA.
10. e8 is the dimension to the outside of the leads and is measured at the lead
tips before the device ;s installed. Negative lead spread is not permitted.
11. N Is the maximum number of lead positions.
12. Dimension 01 altheloftend of the package must equal dimonsion 01 altho
right end of the package within 0.030" (0.76mm).
13. Painted or rounded lead tips are preferred to ease insertion.
14. For automatic insertion, any raised irregularity on the top surface (step, mesa,
etc.) shall be symmetrical about the lateral and longHudlnai package
centerlines.

12-7

Dual-In-Line Plastic Packages

(Continued)

(E) SUFFIX (JEDEC M5-001-AD)
18 LEAD DUAL-IN-LiNE PLASTIC PACKAGE
INCHES
MIN.

MAX.

MIN.

MAX.

A

-

0.210

-

5.33

9

A1

0.Q15

-

0.39

-

9

A2

0.115

0.195

2.93

4.95

B

0.014

0.022

0.356

0.558

B1

0.045

0.010

1.15

1.11

C

0.008

0.015

0.204

0.381

INCHES

NOTES

3

0

0.845

0.925

21.41

23.49

4

01

0.005

-

0.13

-

12

E

0.300

0.325

1.62

8.25

5

E1

0.240

0.280

6.10

1.11

6,1

e

0.100B8C

2.54BSC

eA

0.3OOB8C

1.62B8C

eB

-

L

0.115

0.430

N
(E) SUFFIX (JEDEC M5-001-AF)
24 LEAD DUAL-IN-LiNE PLASTIC PACKAGE

MILLIMETERS

SYMBOL

0.160

-

8
9

10.92

2.93

18

4.06
18

10

9
11

(E) SUFFIX (JEDEC MS-011-AA)
24 LEAD DUAL-IN-LiNE PLASTIC PACKAGE

MILLIMETERS

INCHES

MILLIMETERS

SYMBOL

MIN.

MAX.

MIN.

MAX.

NOTES

SYMBOL

MIN.

MAX.

MIN.

MAX.

NOTES

A

-

0.210

5.33

9

A

9

A1

0.D15

0.39

9

A1

0.015

-

-

6.35

-

-

0.250

-

-

0.39

-

9

A2

0.115

0.195

2.93

4.95

A2

0.125

0.195

3.18

4.95
0.558

B

0.014

0.022

0.356

0.558

B1

0.045

0.010

1.15

1.11

C

0.008

0.D15

0.204

0.381

0

1.125

1.215

01

0.005

-

28.6
0.13

32.3

E

0.300

0.325

1.62

8.25

E1

0.240

0.280

6.10

1.11

-

3

B

0.014

0.022

0.356

B1

0.030

0.010

0.11

1.11

C

0.008

0.D15

0.204

0.381

29.3

32.1

4

0

1.150

1.290

12

01

0.005

-

0.13

-

5

E

0.600

0.625

15.24

15.81

5

6,1

E1

0.485

0.580

12.32

14.13

6,1

9

0.100B6C

2.54B6C

8

e

0.100B8C

2.54B8C

eA

0.300B8C

1.62 B8C

9

eA

0.600B8C

15.24B8C

eB

-

10

9B

-

L

0.115

9

L

0.115

11

N

N

0.430

-

0.160

2.93

24

10.92
4.06
24

NOTES:

1. Refer to JEDEC Publication No. 95 JEOEC Registered and Standard Outlines
for Solid State Products, for rules and general information concerning registered and standard outlines, In Section 2.2.
2. Protrusions (Hash) on the base plane surface shall not exceed 0.010"
(025mm).
3. The dimension shown is for full leads. "Half" leads are optional at lead
positions

1,N,

3

~ ~ +1.

2 2
4. Dimension 0 does not include mold flash or protrusions. Mold flash or pro-

0.100
0.200
24

-

11.18

2.93

5.08
24

4
12

8
9
10

9
11

B. Lead spacing e shall be non-cumulative and shall be measured at the lead
tip. This measurement shall be made before insertion into gauges, boards or
sockets.
9. This is a basic Installed dimension. Measurement shall be made with the de·
vice Installed In the seating plane gauge (JEDEC Oulline No. GS-3), seating
plane gauge). Leads shall be In !rue posnion within 0.Q10" (025mm)diam..

ter for dimension eA.
10. ee is the dimension to the outside of the leads and Is measured at the lead
tips before the device is installed. Negative lead spread is not permitted.
11. N Is the maximum number of lead positions.
12. Dimension 01 altha left end of the package must equal dimension 01 attha
right end of the package wnhin 0.030" (O.76mm).

trusion. shall not exceed 0.Q1 0" (O.25mm)

5. E is the dimension to the outside of the leads and is measured with the leads
perpendicular to the b..e plane (zero lead spread).

13. Pointed or rounded lead tips are preferred to ease insertion.
14. For automatic insertion, any raised irregularity on the lop surface (stap, mesa,

6. Dimension £1 does not Include mold flash or protrusions.
7. Package body and leads shall be symmetrical around center line shown in
end view.

12-8

etc.)

shall be symmetrical about the lateral and longnudinal package

centarlines.

1ttm'fflt7-----:-r
I
JL
T?l--'""'r
.Brrrl
EJ111
jlt;[

Dual-In-line Plastic Packages

(Continued)

1"-- _ .. ---

0

-.----j

BASE PLANE

_______ \

i..J. '

I

SEATING PLANE ,

~

'NOEXA~EA
C

~~.

01

.--1

-

I

0,

7~ ~ ;. - -~
N_;: V'EW
J

INCHES
MAX.

MIN.

A

(E) SUFFIX (JEDEC MS-011-AC)
40 LEAD DUAL-IN-LiNE PLASTIC PACKAGE
INCHES

MILLIMETERS
MIN.

0.250

MAX.

NOTES

SYMBOL

6.35

9

A

9

A1

0.015

0.39

~

E

(E) SUFFIX (JEDEC MS-011-AB)
28 LEAD DUAL-IN-LiNE PLASTIC PACKAGE

SYMBOL

A

, , -r-:I-

MIN.

MAX.

MILLIMETERS
MIN.

MAX.

0.250

6.35

A1

0.015

A2

0.125

0.195

3.18

4.95

A2

0.125

0.195

3.16

4.95

B

0.014

0.022

0.356

0.558

B

0.014

0.022

0.356

0.558

B1

0.030

0.070

0.77

1.77

e

0.006

0.015

0.204

0.381

2.095

B1

0.030

0.070

0.77

1.77

C

0.008

0.015

0.204

0.361

D

1.360

1.565

D1

0.005

35.1

39.7

0.13

3
4

D

1.980

12

D1

0.005

0.39

NOTES
9
9

50.3

53.2

0.13

3
4
12

E

0.600

0.625

15.24

15.87

5

E

0.600

0.625

15.24

15.87

5

E1

00465

0.580

12.32

14.73

6,7

E1

00485

0.580

12.32

14.73

6,7

a

0.100BSC

2.54BSe

8

a

0.100 BSe

2.54BSe

aA

0.600BSe

15.24BSe

9

aA

0.600BSe

15.24 BSC

10

aB

0.700

aB
L
N

0.200

0.115

17.78
2.93

28

5.06
28

9

L

11

N

NOTES:
1. Refer 10 JEDEC Publicalion No. 95 JEDEC Registered and Standard Outlines for Solid State Products. for rules and general Information concerning

registered and standard oullines. in Section 2.2.
2. Protrusions (flash) on the base plane surface shall not exceed 0.010"
(025mm).
3. The dimension shown is for full leads. "Half" leads are optional at lead

positions
1.N. ~ ~ +1.
2 2
4. Dimension 0 does not include mold flash or protrusions. Mold flash or protruSions shall not exceed 0.010" (O.25mm)

5. E is the dimension to the outside of the leads and is measured with the leads
perpendicular to the base plane (zero lead spread).
6. Dimension E1 does not include mold flash or protrusions.
7. Package body and leads shall be symmetrical around cenler line shown In
end view.

0.700
0.115

0.200
40

17.78
2.93

5.08
40

8
9
10
9
11

8. Lead spacing e shall be non-cumulative and shall be measured at the lead
tip. This measurement shall be made before insertion into gauges, boards
or sockets.
9. This is a basic installed dimension. Measurement shall be made with the
device installed in the seating plane gauge (JEDEC Oulline No. GS-3),
seating plane gauge). Leads shall be in true position within 0.010 ..
(O.25mm) diameter for dimension eA.
10. eB isthe dimension to the outside of the leads and is measured al the lead
tips before the device is installed. NegativB lead spread is nol permitted.
11. N is the maximum number of lead positions.
12. Dimension D 1 at the left Bnd of the package must equal dimension 01 at
thB right end of the package within 0.030" (0.76mm).
13. POinted or rounded lead tips are preferred to ease insertion.
14. For automatic insertion, any raised irregularity on the top surface (step,
mesa, etc.) shall be symmetrical about the lateral and longiludinal package
centerlines.

12-9

Dual-In-Line Frit-Seal Ceramic Packages
(F) SUFFIX (JEDEC MO-001-AB)
14 LEAD DUAL-IN-L1NE FRIT-SEAL CERAMIC PACKAGE
INCHES
MIN.

MAX.

MIN.

MAX.

A

0.155

0.200

3.94

5.08

Al

0.020

0.050

0.508

1.27

B

0.014

0.020

0.356

0.508

Bl

0.050

0.065

1.27

1.65

c

0.008

0.012

0.204

0.304

D

0.745

0.770

18.93

E

0.300

0.325

7.62

8.25

El

0.265

0.285

6.73

7.24

el

INCHES
MIN.

MAX.

MAX.

19.55

0.100TP

2.54TP

2

0.300TP

7.62TP

2,3

L

0.125

0.150

3.18

3.81

L2

0.000

0.030

0.00

0.76

a

00

4

N

14

14

Nl

o

o

5
6

01

0.040

0.075

1.02

1.90

s

0.065

0.090

1.66

2.28

INCHES

MILLIMETERS
MIN.

NOTES

(F) SUFFIX
18 LEAD DUAL-IN-L1NE FRIT-SEAL CERAMIC PACKAGE

(F) SUFFIX (JEDEC MO-001-AC)
16 LEAD DUAL-IN-L1NE FRIT-SEAL CERAMIC PACKAGE

" SYMBOL

MILLIMETERS

SYMBOL

NOTES

MILLIMETERS

SYMBOL

MIN.

MAX.

MIN.

MAX.

0.155

0.200

3.94

5.08

NOTES

A

'0.155

0.200

3.94

5.08

A

Al

0.020

0.050

0.051

1.27

A1

0.020

0.050

0.508

1.27

B

0.014

0.020

0.356

0.508

B

0.014

0.020

0.356

0.508

Bl

0.035

0.065

0.89

1.65

Bl

0.035

0.065

0.89

1.65

C

0.008

0.012

0.204

0.304

C

0.008

0.012

0.204

0.304

D

0.745

0.785

18.93

19.93

D

0.845

0.885

21.47

22.47

E

0.300

0.325

7.62

8.25

El

0.240

0.260

6.10

6.60

El

0.265

0.285

6.73

7.24

el

0.1 00 TP

2.54TVP

2

eA

0.300TP

7.62TVP

2,3

el
eA
L

0.100TP
0.3OOTP
0.125

0.150

2.54TP

2

7.62TP

2,3

3.18

L

0.125

0.150

3.16

3.81

a

00

150

00

N

18

18

4

Nl

0

0

5

S

L2

0.000

'0.030

0.00

-0.76

a

00

150

00

150

N

16

16

'0

Nl
01

,0.040

S

0.Q15

I

1

0
0.075

1.02

0.060

0.39

0.Q15

0.060

0.39

6
1.90

I

1.52

NOTES:
Refer to Rules for Dimensioning (JEDEC Publication No. -95) for Axial lead

Product Outlines.
1. When this device is supplied solder-dipped, the maximum lead thickness
(narrow portion) will nol exceed 0,013" (0.33mm).
2. leads wnhln 0,005" (O.12mm) radius of True posnlon (TP) al gauge plane
with maximum material condition and unit installed.

3. sA applies in zone L2 when unit installed.

4. a applies to spread leads prior to installation.
5. N Is the maximum quantity of lead positions.
6. N1 is the quantity of allowable missing leads.

12-10

3.81
150

I

4

5
6
1.52

Dual-In-Line Frit-Seal Ceramic

-~"' ~'I ," .
L --II- 4 it

SEATING PLANE

==J

O:tLf ';'" ~ ~ ~
INDEX AREA

c

81

~2

BOTTOM

_ "'-""-}-

ffif
EJTT11

f

A

B

t

'I

E

VIEW

bl bl bl bl

NOTES:

Refer to Rules for Dimensioning (JEDEC Publication No. 95) for Axial Lead
Product Outlines.
1. When this device is supplied solder-dipped, the maximum lead thickness
(narrow portion) will not exceed 0.013" (O.33mm).

(F) SUFFIX
24 LEAD DUAL-IN-LINE FAIT-SEAL CERAMIC
INCHES

MILLIMETERS

SYMBOL

MIN.

MAX.

MIN.

MAX.

A

0.120

0.250

3.10

6.30

3. eA applied in zone L2 when unit is installed.

Al

0.020

0.070

0.51

1.77

4. Applies to spread leads prior to installation.

B

0.016

0.020

0.407

0.508

5. N is the maximum quantity of lead positions.

Bl

0.028

0.070

0.72

1.77

6. N1 is the quantity of allowable missing leads.

C

0.008

0.012

0.204

0.304

0

1.200

1.290

30.48

El

0.515

0.580

13.09

2. Leads within 0.005" (O.127mm) radius of True Position (TP) at gauge
plane with maximum material condition.

12-11

NOTES

1

32.76
14.73

el

0.1 00 TP

2.54 TP

2

eA

0.600TP

15.24TP

2,3

5.00

L

0.100

0.200

2.54

L2

0.000

0.030

0.00

0.76

a

0°

15°

00

15°

N

24

24

Nl

0

0

4
5
6

01

0.040

0.075

1.02

1.90

S

0.040

0.100

1.02

2.54

Small-Outline (SO) Packages

(M) SUFAX (JEDEC MS-012AB) (Notes 1, 2, 3, 8, 9)
14 LEAD DUAL-IN-LiNE SURFACE MOUNT PLASTIC PACKAGE
INCHES

MILLIMETERS

SYMBOL

MIN.

MAX.

MIN.

MAX.

A

0.0532

0.0688

1.35

1.75

A1

0.0040

0.0098

0.10

0.25

B

0.0138

0.0192

0.35

0.49

C

0.0075

0.0098

0.19

0.25

D

0.3367

0.3444

8.55

8.75

4

E

0.1497

0.1574

3.80

4.00

4

e

0.050BSC

NOTES

1.27BSC

H

0.2284

0.2440

5.80

6.20

h

0.0099

0.0196

0.25

0.50

5

L

0.Q16

0.40

1.27

6

N
ex;

,0.050
1·4
80

00

14

7
80

00

(M) SUFFIX (JEDEC MS-012AC) (Notes 1, 2, 3, 8, 9)
16 LEAD DUAL-IN-LINE SURFACE MOUNT PLASTIC PACKAGE
INCHES

MILLIMETERS

SYMBOL

MIN.

MAX.

MIN.

MAX.

A

0.0532

0.0688

1.35

1.75

A1

0.0040

0.0098

0.10

0.25

B

0.0138

0.0192

0.35

0.49

NOTES:

1. Refer 10 applicable symbol lisl.
2. Dimensioning and tolerancing per ANSI Y14.SM-1982.
3. Dimension "0" does not include mold flash, protrusions or gate burrs.

Mold flash, protrusions and gate burrs shall not exceed O.15mm (.006"
per side.
4. Dimension OlE" does not include interJead flash or protrusions. Intsrlead
flash and protrusions shall not exceed .25mm (O.010',) per side.

NOTES

C

0.0075

0.0098

0.19

0.25

D

0.3859

0.3937

9.80

10.00

4

E

0.1497

0.1574

3.80

4.00

4

e

0.050BSC

1.27BSC

5. The chamfer on the body Is optional. If It is not present, a visual index

H

0.2284

0.2440

5.80

6.20

feature must be located within the crosshatched area.
6. OIL" is the length of terminal for soldering to a substrate.

h

0.0099

0.0196

0.25

0.50

5

L

0.Q16

0.050

0.40

1.27

6

80

00

7. "N" is the number of terminal positions.

N

8. Terminal numbers are shown for reference only.

ex;

9. Controlling dimension: Millimeter.

(M) SUFAX (JEDEC MS-012AA) (Notes 1, 2, 3, 8, 9)
8 LEAD DUAL-IN-UNE SURFACE-MOUNT PLASTIC PACKAGE
INCHES
MIN.

MAX.

MIN.

MAX.

A

0.0532

0.0688

1.35

A1

0.0040

0.0098

B

0.0138

0.0192

16

INCHES
NOTES

7
80

(M) SUFFIX (JEDEC MS-013AA) (Notes 1, 2, 3, 8, 9)
16 LEAD DUAL-IN-LINE SURFACE MOUNT PLASTIC PACKAGE

MILLIMETERS

SYMBOL

16

00

MILLIMETERS

SYMBOL

MIN.

MAX.

MIN.

MAX.

1.75

A

0.0926

0.1043

2.35

2.65

0.10

0.25

A1

0.0040

0.0118

0.10

0.30

0.35

0.49

B

0.0138

0.0192

0.35

0.49

NOTES

C

0.0075

0.0098

0.19

0.25

C

0.0091

0.0125

0.23

0.32

D

0.1890

0.1968

4.80

5.00

4

D

0.3977

0.4133

10.10

10.50

4

E

0.1497

0.1574

3.80

4.00

4

E

0.2914

0.2992

7.40

7.60

4

e

0.050BSC

1.27BSC

H

0.2284

0.2440

5.80

6.20

h

0.0099

0.0196

0.25

0.50

L

0.Q16

0.050

0.40

1.27

80

00

N
ex;

8

00

8

e

0.050BSC

1.27 BSC

H

0.394

0.419

10.00

10.65

5

h

0.010

0.029

0.25

0.75

5

6

L

0.Q16

0.050

0.40

1.27

6

80

00

16

N

7

ex;

80

12-12

00

16

7
80

Plastic Chip Carrier
0.042 (1.07)

-h~""'-

.050 (1.27) TP

r

,

E3

0.020 (0.51) MAX
3 PLCS

0.026 (0.66)
0.032 (0.81)

0.013 (0.33)

----IO.021 (0.53)

~I'

DIMENSIONS IN PARENTHESES

0.080(1.52)
MIN.

ARE MILLIMETER EQUIVALENTS

OF THE BASIC INCH DIMENSIONS

0.025 (0.84)

~

VIEW "A" TYP.

(0) SUFFIX (JEDEC MO-047AC)
44 LEAD SOUARE SURFACE-MOUNT PLASTIC PACKAGE
MILLIMETERS

INCHES
SYMBOL

MIN.

MAX.

MIN.

MAX.

A

0.165

0.180

4.20

4.57

NOTES

Al

0.090

0.120

2.29

3.04

D

0.685

0.695

17.40

17.65

Dl

0.650

0.656

16.510

16.662

2

D2

0.590

0.630

14.99

16.00

1

D3

0.500 REF

12.70BSC

E

0.685

0.695

17.40

17.65

El

0.650

0.656

16.510

16.662

2

E2

0.590

0.630

14.99

16.00

1

E3

0.500 REF

12.70BSC

N

44

44

NOTES:

1. To be determined at seating plane.
2. Dimensions D 1 and E1 do nol include mold protrusions.
Allowable mold protrusion is 0.254mm/0.010 inch.
3. "N" is the number of terminal posilions.
4. Controlling dimensions: Inch
5. All leads at sealing plana to be coplanar within 0.004 inch.

12-13

3

Quad-In-Line Plastic Packages
(0) SUFFIX, 16 LEAD

RECOMMENDED MOUNTING
HOLE DIMENSIONS AND SPACING

.

.785 (19.93)
, . 7 4 5 18.93

I

L~_-_$_$_~~~
~~~~~{~: ~:~ : JT:t(:.:~)
1
li;~1 ! ~--$--$~~ .
1254

15678

oo
.

~
' -$-$-$-

15081
,

!
J

060(1'90)

1~

.050
(1.27)
.020 ,51

.015

.39

! }--

IA~I I~~~I

15.081
.200
TYP.

MIN.

TYP.

.300
17.621

-.l

'

- - - - - - - - - - - - TOP VIEW
TERMINAL NO,I

1

-e-$-'-$-$.lOoL 030 I,76I OIA,
~~12541
T'yP' .
liN ci~~81~E~OAROI

.200(5.08)
.155 3.94

JL~ ~;JI:~~)
,020 (,508)
.014 .356

TYP.

.008-.013
1.204-.3301

92CS -17S33R2

NOTES:

I. Body width is measured 0.040" (1.02mm) from top surface.
2. Seating plane defined as the junction of the angle with the narrow portion
oflhe'tead.

TO-5 Style Package
(S) SUFFIX
8 LEAD TO-5 STYLE WITH DUAL-IN-L1NE FORMED LEADS
(DILCAN)

ffi1

.33!1-·37O
39
18."-9.
OIA.
.30!l-.33!1
17.7!1- 8.!!O1
OIA.

( O,,-.O!lO -,
.39-1.271

L

,

.

,

IS!!
i4.701 MAX.
.070-."0
(1.78- 3.all

a LEADS
.200 (!I.OaIOIA.
PIN CI RC LE

-FH:,.j-H:::+

.100t.010
(2.54t·254)
(3 SPACES)

All dimensions given in

.300±.010
( 7.62 1.254)
NON CUMULATIVE

Inches
(mUlimelersl

12-14

TO-5 Style Packages

(Continued)

IT) SUFFIX IJEDEC MO-002-AL)
8 LEAD TO-S STYLE PACKAGE
INCHES
SYMBOL

MIN.

a

MILLIMETERS
MIN.

MAX.

0.200TP

MAX.

Al

0.010

0.050

0.26

1.27

A2

0.165

0.185

4.20

4.69

0.016

0.019

0.407

0.482

0.125

0.160

3.18

4.06

0.016

0.021

0.407

0.482

0.335

0.370

8.51

9.39

0.305

0.335

7.75

8.50

0.020

0.040

0.51

1.01

0.028

0.034

0.712

0.863

cpBI
cpB2
cpO
cpDl
Fl

NOTES

5.88TP

2
2

k

0.029

0.045

0.74

1.14

L1

0.000

0.050

0.00

1.27

L2

0.250

0.500

6.4

12.7

2

L3

0.500

0.562

12.7

14.27

2

3
2

Q

IT) SUFFIX IJEDEC MO-006-AF)
10 LEAD TO-5 STYLE PACKAGE

a

8

5

3

4

MILLIMETERS

MAX.

MIN.

8
3

IT) SUFFIX IJEDEC MO-006-AG)
12 LEAD TO-5 STYLE PACKAGE

INCHES
SYMBOL

N

Nl

MIN.

0.230TP

MAX.

MILLIMETERS

INCHES
NOTES

SYMBOL

MIN.

a

5.84TP

MAX.

MIN.

0.230TP

Al

o

0

o

0

Al

o

0

o

0

A2

0.165

0.185

4.19

4.70

A2

0.165

0.185

4.19

4.70

cpB
cpBl
cpB2
cpO
cpOl

0.016

0.019

0.407

0.482

0.Q19

0.407

0.482

0

o

0

o

0

o

0

0.016

0.021

0.407

0.533

0.016

0.021

0.407

0.533

0.335

0.370

8.51

9.39

0.335

0.370

8.51

9.39

0.305

0.335

7.75

8.50

cpB
cpBl
cpB2
cpO
cpOl

0.016

o

0.305

0.335

7.75

8.50

0.020

0.040

0.51

1.01

Fl

0.020

0.040

0.51

1.01

0.028

0.034

0.712

0.863

0.028

0.034

0.712

0.863

Fl

2

2

NOTES

2

2

k

0.029

0.045

0.74

1.14

3

k

0.029

0.045

0.74

1.14

3

Ll

0.000

0.050

0.00

1.27

2

Ll

0.000

0.050

0.00

1.27

2

L2

0.250

0.500

6.4

12.7

2

L2

0.250

0.500

6.4

12.7

2

L3

0.500

0.562

12.7

14.27

2

l3

0.500

0.562

12.7

14.27

2

Q

300 TP

300 TP

5

N

12

12

4

Nl

Q

N

10

10

Nl
NOTES:

Refer to Rules for Dimensioning (JEDEC Publication No. 95) for Axial Lead
Product Oullines.

1. Leads at gauge plana within 0.007" (O.178mm) radius of True Position
(TP) at maximum material condition.

2.

MAX.

5.84TP

~B

applies between L I and L2.

~B2

3. Measure from Max. cpO.

4. Nl is the quantity of allowable missing leads.

applies between L2 and 0.500"
(12.70mm) from sealing plane. Diameter is uncontrolled in l1 and beyond
0.500" (12.70mm).

5. N Is tha maximum quantity of lead positions.

12-15

5
4

HA/HC/HFA/HV*-Type
Packaging & Ordering Information

HARRIS PRODUCT CODE EXAMPLE

H
PREFIX:
H: Harris

T

A

7

-r-

-r-

5147

5

PART NUMBER

TEMPERATURE:
FAMILY: - - - - - - '
A: Analog
C: Communications

J

2: -550 Cto+1250 C
4: -250 C to +85 0 C
5: ooC to + 75 0 C

7: Dash-7 High Reliability Commercial
Product OoC to + 75 0 C, includes 96
hour Burn-In

PACKAGE:
1: Dual-In-Llne Ceramic
2: MetalCan
3: Dual-In-Llne Plastic
4P: Plastic Leaded Chip Carrier
7: Mini-DIP, Ceramic
9P: Small Outline
0: Chip Form

-8: -550 C to +1250 C Harris Class B
equivalent for use in military &
flight systems not manufactured
to full Mil-Std-883 specifications
9: -400 C to +850 C
/883: Full compliance to Mil-Std-S83

These products are available fully screened to Mil-Std-SS3C.
Contact a Harris Sales Office for a copy of the /883 data sheet.

·Ordering Information for HV-1205 and HV-2405E only

12-16

Package Outlines
1- .300 CERAMIC DUAL-IN-L1NE
; - E ---,

PKG

CODE
1-

LEAD
COUNT
8
SSI

DIM
A

--

.200

DIM
A1

DIM
B

DIM
B1

DIM
C

DIM
D

DIM
E

DIM
E1

DIM

DIM
L

DIM
L1

DIM
5

DIM
51

DIM
Q

.140
.160

,016
.023

.050
.065

.008
.015

.375
.395

.245
.265

.290
.310

.100

a

.125
.150

.150

--

.005

.015
.060

00
-15
0

.016
.023

.050 .008 .753 .265 .290 .100 .125 .150
- -.005
-.065
-.015 -.785 -.285 -.310 esc -.180 - - -.098
-

.015
.060

-

.015
.060

00
150

.015
.060

0
-15
0

.015
.060

0
-15
0

.005 .015
-.300
-.100 -.125 -.150
.320 esc .180
- -.098 - - -.060

00
150

e

esc

--

.055

1-

14
MSI

- -.140
-.200
.170

1-

14
LSI

-.200
-.140
-.050 -.008
.170 .023 .065 .015

-

.753
.785

-

16"
MSI

-.200
-.140
.170

.016
.023

.050"
.065"

.008
-.015

.753
.785

.265 .290 .100
-.285
-.310 esc

16"
LSI

-.200
-.140
.170

.016
.023

.050"
.065

-.008
-.753 -.285 -.300 .100 -.125 -.150
.015 .785 .305 .320 esc .180
- -.080

1-

18
LSI

- -.140 -.016 .050"
-.200
-.008 -.882
.170 .023 .065" .015 .915

1-

20
LSI

-.200

11-

,016

.140
.170

.016
.023

.285
.305

.285
.305

.300
.320

-

.100

-

esc

-

.125
.180

-.150
- -.098

.125
.180

-.150
-

-.940
-.285 -.300 -.100
.970 .305 .320 esc

.125
.180

*End leads are half leads where B remains the same and 81 is

0.035
0.045

.050"
.065"

.008
.015

-

"Solder dip finish add +0.003 inches

.150

-

-

--

.080

-.080

--

.005

-

-

.005

-

-

.005

-

-

.005

-

-

DIM

00
150

0

0

0
-.015
.060 150
0

1- .600 CERAMIC DUAL-IN-L1NE

~___________ D__________S_1~~I~~
I

o

.

zO
et!il:

eJ-

PKG

CODE
11-

LEAD
COUNT

DIM
A

DIM
A1

DIM
B

DIM
B1

DIM
C

DIM
D

DIM
E

DIM
E1

DIM

24
LSI

--

.150
.180

.016
.023

.050
.065

.008
-.015

1.24
-1.27

.515
.535

.595
.615

.100

28
LSI

.180 .016 .050 .008
-.225
-.190
-.023 -.065 -.015

1.44
1.47

.515
.535

.595
.615

.100

.225

e

esc

DIM
L1

DIM
5

DIM
S1

DIM

DIM

Q

a.

.125
.180

.150

--

.005

.015
.060

-

-

.098

--

00
150

.125 .150
- .005 .015 00
esc -.180 - - -.098 - - -.080 -150

*Solder dip finish add +0.003 Inches

12-17

DIM
L

zeJ
z
eJ
-

eta:
~w

0

0

eta:
c..O

l2=J

.300 SIDEBRAZE DUAL-IN-LiNE

PKG
CODE

LEAD
COUNT

DIM
A

1-

8
LSI
14
LSI

1-

L::J

DIM
A1

DIM
B

DIM
B1

DIM
C

DIM
D

DIM
E

DIM
E1

DIM

e

DIM
L

DIM
L1

DIM
5

DIM
51

.101
.150

.016
.023

.040
.060

.008
.015

.380

.280
.300

.290
.310

.100
Bse

.125
180

.150

AOO

.015
.060

.055

.101
.150

.016
.023

.040
.060

.008
.015

.736
.758

.260
.300

.290
.310

.100
Bse

.125
.160

.150

.015
.060

.098

.005
.005

.300 PLASTIC DUAL-IN-LiNE

PKG
CODE

LEAD
COUNT

DIM
A1

DIM
B

DIM
B1

DIM
C

DIM
D

DIM
E

DIM
E1

DIM

DIM
L

DIM
5

DIM
Q

DIM

e

3-

8

.125
.140

.016
.023

.050
.070

.006
.015

.370
.390

.245
.265

.290
.310

.090
.110

.110
.150

.030
.050

.020
.040

00
150

3-

14

.125
.140

.016
.023

.050
.070

.008
.015

.750
.770

.245
.265

.290
.310

.090
.110

.110
.150

.030
.050

.020
.040

00
150

3-

16"

.125
.140

.016
.023

.050
.070

.008
.015

.750
.770

.245
.265

.290
.310

.090
.110

.110
.150

.025
.035

.020
:040

00
150

3-

18

.125
.140

.016
.023

.050
.070

.008
.015

.900
.920

.245
.265

.290·
.310

.090
.110

.110
.150

.040
.060

.020
.040

00
150

3-

20

.130
.145

.016
.023

.050
.070

.008
.015

1.030
1.050

.250
.270

.290
.310

.090
.110

.110
.150

.060
.060

.020

.040

00
150

*End leads are half leads where B remains the same and 81 is
**Solder dip finish add +0.003 inches

12-18

0.035
0.045

DIM
Q

(l

~

0600 PLASTIC DUAL-IN-L1NE

I

I

I

0

~~jt
JL J!!l U-,JSiLO, -rr~,~~a~
_U U U U U UOSU

UU e

U

.j

"SI

PKG
CODE

LEAD
COUNT

DIM
A1

DIM
8

DIM
81

DIM
C

DIM
D

DIM
E

DIM
E1

DIM

DIM
L

DIM

DIM

e

5

Q

a

3-

24

.145
.155

.016
.023

.050
.070

.008
.015

1.24
1.26

.540
.560

.290
.610

.090
.110

.110
.150

.045
.095

.020
.040

0°
15°

3-

28

.145
.155

.016

.050
.070

.008
.015

1.54

.540
.560

.590
.610

.090

.110

.110

.150

.110
.160

.020
.040

15°

.023

1.57

DIM

00

·Solder dip finish add +0.003 inches

~ TO-99 METAL CAN

f"b
L-

i---J

-

,

Q

aDo
a,

t

=i4i

* 08

0-

e

t

,

0-

L

0

KJ[ll

PKG
CODE

LEAD
COUNT

DIM
A

DIM
$8

DIM
$D

DIM

2-

8
TO-99

.165
.185

.016
.018

.345
.190
.365 . .210

e

o .
zO

DIM
F

DIM
K

DIM
K1

DIM
L

DIM
Q

~z~

.020
.040

.028

.028
.040

.505
.550

.015
.040

~
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:06:25 17:11:23-08:00
Modify Date                     : 2017:06:25 18:25:40-07:00
Metadata Date                   : 2017:06:25 18:25:40-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:e3cc34b7-ecd0-8f4e-a419-0ccc03555744
Instance ID                     : uuid:b597edbc-9f39-3d41-b1e0-a133ee9d929a
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 1234

EXIF Metadata provided by EXIF.tools