1991_Motorola_Memory_Device_Data 1991 Motorola Memory Device Data

User Manual: 1991_Motorola_Memory_Device_Data
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Selector Guide and Cross Reference
CMOS Dynamic RAMs •
DRAM Modules •
General MOS Static RAMs •
CMOS Fast Static RAMs

II

CMOS Fast Static RAM Modules •
Application Specific MOS Static RAMs •
Military Products •
Reliability Information •
Applications Information •
Mechanical Data
MOTOROLA MEMORY DATA

m

DATA CLASSIFICATION
Product Preview
This heading on a data sheet indicates that the device is in the formative
stages or in design (under development). The disclaimer at the bottom of
the first page reads: "This document contains information on a product
under development. Motorola reserves the right to change or discontinue
this product without notice."

Advance Information
This heading on a data sheet indicates that the device is in sampling,
preproduction, or first production stages. The disclaimer at the bottom of
the first page reads: "This document contains information on a new product.
Specifications and information herein are subject to change without notice."

Fully Released
A fully released data sheet contains neither a classification heading nor a
disclaimer at the bottom of the first page. This document contains information on a product in full production. Guaranteed limits will not be changed
without written notice to your local Motorola Semiconductor Sales Office.

BurstRAM, DSPRAM, ParityRAM, and QuickRAM are trademarks of Motorola, Inc.
SPARe is a trademark of Sun Microsystems.

MOTOROLA
MEMORIES
Prepared by
Technical Information Center

Motorola has developed a broad range of reliable memories for virtually any digital
data processing system application. Complete specifications for the individual circuits
are provided in the form of data sheets. In addition, a selector guide is included to
simplify the task of choosing the best combination of circuits for optimum system
architecture.
New Motorola memories are being introduced continually. For the latest
releases, and additional technical information or pricing, contact your nearest
authorized Motorola distributor or Motorola sales office.

Motorola reserves the right to make changes without further notice to any products herein to improve reiiability,
function or design. Motorola does not assume any liability arising out of the application or use of any product
or circuit described harein; neither does it convey any license under its patent rights nor the righta of others.
Motorola products are not designed, intended, or authorized for use as componenta in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application
in which the failure of tha Motorola product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer
shall indemnify and hold Motorola and its officers, employees, subaidiaries, affiliates, and distributors harmless
againat aU claims, costa, damages, and expanses, and reaaonabla attomav f_ arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and
are
registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity!Affirmative Action Employer.

®

Printed in U.S.A.

DL113!D, Rev 7
©MOTOROLA INC., 1991
Previous Edition © 1990
"All Rights Reserved"

MOTOROLA MEMORY DATA
iv

TABLE OF CONTENTS
ALPHANUMERIC INDEX . ........................................................ ix

CHAPTER 1
Selector Guide ................................................................................ 1-2
Cross Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-20

CHAPTER 2 - CMOS DYNAMIC RAMs
MCM54100A
MCM54100A-C
MCM54101A
MCM54102A
MCM54170B
MCM54190B
MCM54260B
MCM54280B
MCM54400A
MCM54400A-C
MCM54402A
MCM54410A
MCM54800A
MCM54900A
MCM511000A
MCM511000B
MCM511001A
MCM511002A
MCM514256A
MCM514256B
MCM514258A

4M x 1, 60170/80 ns .................................................... 2-3
4M x 1,70/80 ns, Industrial Temp Range (- 40 to + 85 C) ...................... 2-22
4M x 1, 60/70/80 ns, Nibble Mode ........................................ 2-41
4M x 1, 60170180 ns, Static Column ... ;................................... 2-60
256K x 16,70/80/100 ns, Fast Page Mode -1 CAS,2 Write Enables ............. 2-82
256K x 18,70/80/100 ns, Fast Page Mode -1 CAS, 2 Write Enables ............. 2-84
256K x 16, 70/80/100 ns, Fast Page Mode - 2 CAS, 1 Write Enable .............. 2-86
256K x 18, 70/801100 ns, Fast Page Mode - 2 CAS, 1 Write Enable .............. 2-88
1M x 4, 60/70/80 ns, Fast Page Mode ..................................... 2-90
1M x 4, 70/80 ns, Fast Page Mode ....................................... 2-111
1M x 4, 60170180 ns, Static Column Mode ................................. 2-131
1M x 4, 60/70/80 ns, Write Per Bit ....................................... 2-154
512K x 8, 70/801100 ns, Page Mode ...................................... 2-175
512K x 9,70/80/100 ns, Fast Page Mode .................................. 2-195
1M x 1, 70/80/100 ns, Page Mode ....................................... 2-197
1M x 1, 60/80 ns, Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-212
1M x 1, 70/80/100 ns, Nibble Mode ...................................... 2-227
1M x 1, 70/80/100 ns, Static Column ..................................... 2-242
256K x 4, 70/80/100 ns, 'Page Mode ..................................... 2-257
256K x 4, 60/80 ns, Page Mode ......................................... 2-272
256K x 4, 70/80/100 ns, Static Column . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-287

CHAPTER 3 - DRAM MODULES
MCM32100
MCM32130
MCM32200
MCM32230
MCM32256
MCM32512
MCM36100
MCM36200
MCM36256
MCM36512
MCM40100
MCM40200
MCM40256
MCM40512
MCM81000
MCM81430
MCM84000

1M x 32, 80/100 ns .................................................. '" 3-3
1M x 32,70/80/100 ns, Low Height Version of MCM32100 ..................... 3-15
2M x 32, 80/100 ns .................................................... 3-27
2M x 32, 70/80/100 ns, Low Height Version of MCM32200 ..................... 3-39
256K x 32, 70/801100 ns ................................................ 3-51
512K x 32, 70/80/100 ns ......................... " ..................... 3-63
1M x 36, 80/100 ns ............. ; ...................................... 3-75
2M x 36, 80/100 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-87
256K x 36, 70/80/100 ns ................................................ 3-99
512K x 36,70/80/100 ns ............................................... 3-111
1M x 40,70/80/100 ns, Same as MCM36100, for Error Correction Applications .... 3-123
2M x 40,70/80/100 ns, Same as MCM36200, for Error Correction Applications .... 3-135
256K x 40,70/80/100 ns, Same as MCM36256, for Error Correction Applications .. 3-147
512K x 40,70/80/100 ns, Same as MCM36512, for Error Correction Applications .. 3-159
1M x 8, 70/80/100 ns ................................................. 3-171
1M x 8,60170/80/100 ns, 2 Chip Derivative of MCM81000S ................... 3-183
4M x 8,80/100 ns .................................................... 3-195

MOTOROLA MEMORY DATA
v

TABLE OF CONTENTS (Continued)
MCM84000A
MCM84256
MCM91 000
MCM91430
MCM94000
MCM94000A
MCM94256
MCM94256A

4M x 8, 60/70/80/100 ns .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
256K x 8 Bit, 70/80/100ns .................................... : .......•.
1M x 9, 70/80/100 ns •................................................
1M x 9, 70/80/100 ns, 3 Chip Derivative of MCM91000S ......................
4M x 9, 80/100 ns ..... . . . . . • • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4M x 9,60170/80/100 ns .....•..........•.............•................
256K x 9, 70/80/100 ns ........................... _. . . . . . . . . . . . . . . . . . . .
256K x 9, 70/80/100 ns ................................................

3-207
3-219
3-231
3-243
3-255
3-267
3-279
3-291

CHAPTER 4 - GENERAL MOS STATIC RAMs
MCM2018A
MCM60L256A-C
MCM60L256A-V

2K x 8, 35/45/55 ns . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
32K x 8, 100 ns, Industrial Temp Range (- 40 to + 85°C), Low Power .............. 4-8
32K x 8,100 ns, Extended Temp Range (- 40 to + 105°C), LOw Power ............ 4-16

CHAPTER 5 - CMOS FAST STATIC RAMs
MCM6205
MCM6205C
MCM6206
MCM6206C
MCM6207
MCM6207C
MCM62L07
MCM6208
MCM6208C
MCM62L08
MCM6209
MCM6209C
MCM6226
MCM6226A
MCM6229
MCM6229A
MCM6246
MCM6249
MCM6264
MCM6264C
MCM6265
MCM6265C
MCM6268
MCM6270
MCM6287
MCM6288
MCM6288B
MCM6288C
MCM6290
MCM6290C
MCM6706
MCM6706A
MCM6708

32Kx9,15/17/20/25135ns ............................................... 5-3
32K x 9,15/17/20/25135 ns ..•..•......................................... 5-9
32K x 8, 15/17/20/25135 ns .............................................. 5-15
32K x 8,15/17/20/25/35 ns .............................................. 5-21
256K x 1, 15120125 ns . . . . . . . . . . . . . . . • . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . 5-27
256K x 1, 15120125 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-33
256K x 1, 20125135 ns, Low Current Standby Mode ..... . . . . . . . . . . . . . . . . . . . . .. 5-39
64K x 4,15/20125 ns ............................•...................... 5-45
64K x 4,15/20125 ns ................................•.................. 5-51
64K x 4, 20/25135 ns, Low Current Standby Mode ............................ 5-57
64K x 4,15120125 ns ................................................... 5-63
64K x 4,15120125 ns .............•..................................... 5-69
128K x 8, 25130 ns .................................................... 5-75
128K x 8, 20/25130 ns .....•..•............•............................ 5-82
256K x 4, 25130 ns .•..............•................................... 5-89
256K x 4, 20/25130 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-95
512K x 8, 25130/35 ns ................................................. 5-102
1M x 4, 25130/35 ns .................................... , ............. 5-108
8K x 8, 15/20/25/35'ns ................................................ 5-114
8K x 8, 12115120125/35 ns .............................................. 5-120
8K x 9, 15120/25/35 ns ................................................ 5-126
8K x 9,12115/20/25135 ns .......................•...................... 5-132
4K x 4,20/25/35/45/55 ns .............................................. 5-138
4K x 4,20/25135 ns, Output Enable ...................................... 5-144
64K x 1, 12115120/25/35 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-150
16K x 4,12115 ns .................................................... 5-156
16K x 4,20125135 ns ............................................•..... 5-162
16K x 4, 12115/20/25/35n8 ..................•.......................... 5-168
16K x 4,12115 ns ....•............................................... 5-174
16K x 4,10/12115/20125135 ns, Output Enable .............................. 5-180
32K x 8,10/12 ns, BiCMOS .•................•......................... 5-186
32K x 8, 8110112 ns, BiCMOS ...........•.............................. 5-192
64K x 4,10/12 ns, BiCMOS ............................................ 5-198

MOTOROLA MEMORY DATA
vi

TABLE OF CONTENTS (Continued)
MCM6708A
MCM6726
MCM6727
MCM6728
MCM6729
MCM62820
MCM62820A
MCM67282

64K x 4, 8110/12 ns, BiCMOS . . . . . . . . . . . . . . . . • . . . . . . . • . . . . • . . . . . . . . . . . . .
128K x 8,10/12 ns, BiCMOS ......•...•.•........•.....................
1M x 1,10/12 ns, BiCMOS .••...........................•..............
256K x 4,10/12 ns, BiCMOS ......•.........•...........•..............
256K x 4,10/12 ns, BiCMOS ............•..............................
8K x 20, 23/30 ns, Latched Address . . . . . . . . . . . . . . . . • . . • . . . . • . . . . . . . . . . . . .
8K x 20,17/23 ns, Latched Address ..•........•...••......•.•............
256K x 4, 10112 ns, BiCMOS •....•....•••......•.......................

5-204
5-210
5-215
5-220
5-225
5-230
5-236
5-242

CHAPTER 6 - CMOS FAST STATIC RAM MODULES
MCM3264
MCM8256
MCM32257
MCM36232

64K x 32, 20/25135 ns . . . • . . • • • • • • . • • • . . . . . . . . . . . • . . • . • . • . . . . . • . . . . . . . . .. 6-3
256K x 8, 20/25/35 ns ...•.••.•.•.•...•.•...••...•....•.....•........... 6-10
256K x 32, 20/25 ns .•.••.•••..•••••.•.•...••.•...•....•.••............ 6-17
2 x 32K x 36, 15/20 ns .............•....•..........•....•.............. 6-24

CHAPTER 7 - APPLICATION SPECIFIC MOS STATIC RAMs
MCM4180
MCM6293
MCM6294
MCM6295
MCM56824
MCM56824A
MCM62110
MCM62157
MCM62350
MCM62351
MCM62486
MCM62486A
MCM62940
MCM62940A
MCM62950
MCM62950A
MCM62960
MCM62960A
MCM62963
MCM62963A
MCM62973
MCM62973A
MCM62974
MCM62974A
MCM62975
MCM62975A
MCM62980
MCM62981
MCM62982
MCM62983
MCM62990

4K x 4,18120122125 ns, Cache Tag ..................•...................... 7-3
16K x 4, 20/25 ns, Synchronous, Output Registers ...................•....... 7-13
16K x 4, 20/25 ns, Synchronous, OUtput Registers, Output Enable ............... 7-23
16K x 4, 25/30 ns, Synchronous, Output Enable ........••...•............... 7-32
8K x 24, 25/30/35 ns, DSPRAM •.•..•..•.•........•...................... 7-41
8K x 24, 20/25/35 ns, DSPRAM •.••.•.......•.•.....•....•.••............ 7-49
32K x 9, 15/17/20 ns, Synchronous, Dual 110, Parity Checker ...•.•.•........... 7-56
16K x16, 15117/24 ns, Spare Cache, Synchronous .......•................... 7-68
4K x 4, 18/20/22125 ns, Cache Tag, Programmable Match Level .•.....•......... 7-71
4K x 4, 18120122125 ns, Cache Tag ..••......•....•......•.•............... 7-81
32K x 9,14119/24 ns, 486 Processor Cache Synchronous BurstRAM ............. 7-91
32K x 9,14119/24 ns, 486 Processor Cache Synchronous BurstRAM ............ 7-100
32K x 9,14119/24 ns, 68040 Cache Synchronous BurstRAM .••••............. 7-110
32K x 9, 14119/24 ns, 68040 Cache Synchronous BurstRAM .................. 7-118
32K x 9, 20/25 ns, RISC-CISC Cache, Synchronous .....•.....•............. 7-127
32K x 9, 15/20/25 ns, RISC-CISC Cache, Synchronous .••................... 7-133
32K x 9,17/20/24 ns, Synchronous ............•..•...•...•.............. 7-140
32K x 9,15117/24 ns, Synchronous ...............•.••................... 7-146
4K x 10,30 ns, Synchronous, Output Registers ...............•...........•. 7-153
4K x 10, 30 ns, Synchronous, Output Registers ...•.....••.................. 7-158
4K x 12, 18/20 ns, Synchronous, Output Registers ..........•.•...•...•...•. 7-163
4K x 12, 18/20 ns, Synchronous, OUtput Registers .•...........•..........•. 7-168
4K x 12, 18120 ns, Synchronous, Output Registers, Output Enable •............. 7-173
4K x12, 18120 ns, Synchronous, Output Registers, Output Enable .............. 7-177
4K x 12,25/30 ns, Synchronous, OUtput Registers ....••....•............... 7-181
4K x 12,25/30 ns, Synchronous, Output Registers •..••.....•............... 7-186
64K x 4,15/20 ns, Synchronous 1 Stage Pipeline .•.•.•..........•.......... 7-191
64K x 4, 15/20 ns, ParityRAM, Synchronous 1 Stage Pipeline .......•.......... 7-197
64K x 4,12115 ns, Synchronous, 2 Stage Pipeline ........................... 7-203
64K x 4,12115 ns, ParityRAM, Synch., Output Registers 1 Stage Pipeline ........ 7-208
16K x 16, 17/20/25 ns, Latched Address .••...........•........•.......... 7-213

MOTOROLA MEMORY DATA
vii

TABLE OF CONTENTS (Continued)
MCM62990A
MCM62995
MCM62995A
MCM62996
MCM101510
MCM101514

16K x 16, 121t5l20/25 ns, Latched Address ................................
16K x 16, 17/20125 ns, Asynchronous, Latched Address .....................
16K x 16, 12115120125 ns, Asynchronous, Latched Address ...................
16K x 16, 12115/20/25 ns .......................•......................
1M x 1, 10/12 ns .....................................................
1M x 1, 10/12 ns ..........•..•.....................................' ..

7-219
7-226
7-237
7-249
7-254
7-260

CHAPTER 8 - MILITARY PRODUCTS . ...................................................... 8-3
CHAPTER 9 - RELIABILITY INFORMATION ................................................ 9-2
CHAPTER 10 - APPLICATIONS INFORMATION
DRAMs
AN986

Page, Nibble, and Static Column Modes: High-Speed, Serial-Access Options on
1M-Bit + DRAMS .....................•............•.................. 10-2
DRAM Refresh Modes ................................................. 10-6
1 Meg to 4 Meg DRAM Upgrading ........................................ 10-8
Battery Backup of SeHRefreshing Dynamic Random Access Memory. . . . . . . . . . .. 10-10

AN987
AN1124
AN1202
FSRAMs
AN971
Avoiding Bus Contention Problems in Fast Access RAM Designs . . . . . . . . . . . . . ..
AN973
Avoiding Data Errors with Fast Stat.ic RAMs. . . . . . . . . . . .. . . . . . . . . . . . . . . . . . ..
AN984
25 MHz Logical Cache for an MC68020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
SPECIAL APPLICATION STATIC RAMs
.
AR256
Motorola's Radical System SRAM Design Speeds System 40% ................
AR258
High Frequency System Operation Using Synchronous SRAMS . . . . . . . . . . . . . . ..
AR260
Enhancing System Performance Using Synchronous SRAMs '" . . . . . . . . . . . . . ..
AR270
Designing a Cache for a Fast Processor ..................................

10-14
10-18
10-21
10-35
10-38
10-45
10-49

CHAPTER 11 - MECHANICAL DATA
Package Dimensions .......... '....•............•..••...•...................................... , 11-3
Tape and Reel Data for Surface Mount Devices .................................................... 11-24

MOTOROLA MEMORY DATA
viii

ALPHANUMER~INDEX
Device Number

Organization

Comments

Address Access
leyel.Tlme

Page

MCM60L256A-C

32Kx8

lOOns

MCM60L256A-V

32Kx8

lOOns

MCM2018A

2Kx8

35145155 ns

4-3

MCM3264

64Kx32

2OI2513Ons

6-3

Industrial tamp range (-<10 to ..a5° C), Low power

4-8

EXlended lamp range (-<10 to +105° C), Low power

4-16

MCM4180

4Kx4

18120125 ns

MCM6205

32Kx9

15117120/25135 ns

Cache Tag

7-3

MCM6205C

32Kx9

15117120/25135 ns

5-9

MCM6206

32Kx8

15117120/25135 ns

5-15

MCM6206C

32Kx8

15117120/25135 ns

5-21

MCM6207

256Kx 1

15120125 ns

5-27

5-3

5-33

MCM6207C

256Kx 1

10112 ns

MCM62L07

256Kx 1

20125135 ns

MCM6208

64Kx4

1~2O/25ns

5-45

MCM6208C

64Kx4

15,2O,25ns

5-51

MCM62L08

64Kx4

20125135ns

MCM6209

64Kx4

15120125 ns

MCM6209C

64Kx4

15,2O,25ns

MCM62L09

64Kx4

20125135 ns

Low Current Slandby Mode

Low Current Slandby Mode

5-39

5-57
5-63
5-69

Low Current Slandby Mode

5-57

MCM6226

128Kx 8

25130ns

5-75

MCM6226A

128Kx8

20125130 ns

5-82

MCM6229

256Kx 4

25130ns

5-89

MCM6229A

256Kx4

20125130ns

5-95

MCM6246

512Kx8

25130135 ns

5-102

MCM6249

lMx4

25130135 ns

5-108

MCM6264

8Kx8

15120125135 ns

5-114

MCM6264C

8Kx8

12115120/25135 ns

5-120

MCM6265

8Kx9

15120125 ns

5-126

MCM6265C

8Kx9

12115120125135 ns

5-132

MCM6268

4Kx4

20125135145155 ns

5-138

MCM6269

4Kx4

25135ns

Fast Chip Select

5-138

MCM6270

4Kx4

20125135 ns

Output Enable

5-144

MCM6287

64Kx 1

12115120/25135 ns

5-150

MCM6288

16Kx4

12115 ns

5-156

MCM6288B

16Kx4

20125135 ns

5-162

MCM6288C

16Kx4

12115120/25135 ns

MCM6290

16Kx4

12115 ns

Output Enable

5-174

MCM6290B

16Kx4

2OI25135ns

Output Enable

5-156

MCM6290C

16Kx4

10112115120125135ns

Output Enable

5-180

MCM6293

16Kx4

2OI25ns

Synchronous, Output Regis1ers

7-13

MCM6294

16Kx4

2OI25ns

Synchronous, Output RegiSlars, Output Enable

7-23

MCM6295

16Kx4

25135 ns

Synchronous, Output Enable

7-32

MCM6706

32Kx8

10112n8

BiCMOS

5-186

5-168

MOTOROLA MEMORY DATA

ix

ALPHANUMERIC INDEX (Continued)
Device Number

Organization

AddreeaAcceu
/CycleTime

Comments

Page

MCM6706A

32Kx8

8/12ns

BiCMOS

5-192

MCM6708

64Kx4

10112ns

BiCMOS

5-198

MCM6708A

84Kx4

10112ns

BiCMOS

5-204

MCM6709

84Kx4

10112ns

BiCMOS, Output Enable

5-198

MCM6709A

84Kx4

12115ns

BiCMOS, Ou1put Enable

5-204

MCM6728

256Kx4

10112 ns

BiCMOS

5-210

MCM6727

lMxl

10112ns

BiCMOS

5-215

MCM6728

256Kx4

10112ns

BiCMOS

5-220

MCM6729

256Kx4

10112ns

BiCMOS

5-225

MCM8256

256Kx8

2OI25I3On&

MCM32100

lMx32

6OI100ns

Fast page mode cycle lime = 40/45/55 ns

3-3

MCM32130

lMx32

70l60I100 ns

Low height version of MCM32100

3-15

MCM32200

2Mx32

8OI100ns

Fast page mode cycle time =40145155 ns

3-27

MCM32230

2Mx32

701601100ns

Low height version of MCM32200

3-39

MCM32256

256Kx32

70l60I100 ns

Fast page mode cycle time .. 40145155 ns

3-51

MCM32257

256Kx32

2OI25ns

MCM32512

512Kx32

70l60I100 ns

Fast page mode cycle time .. 40145155 ns

3-63

MCM36100

lMx36

8OI100ns

Fast page mode cycle time = 40145/55 ns

3·75

MCM36200

2Mx36

801100ns

Fast page mode cycle time =40145/55 ns

MCM36232

2x32Kx36

15120ns

MCM36256

256Kx36

70l60I100 ns

Fast page mode cycle time .. 40145/55 ns

3-99

MCM36512

512Kx36

701601100 ns

Fast page mode cycle time .. 40145155 ns

3·111

6·10

6-17

3-87
6·24

MCM40100

lMx40

70l60I100 ns

Same as MCM36100, for error correction applications

3-123

MCM40200

2Mx4O

70l60I100 ns

Same as MCM36200, for error correction applications

3-135

MCM40256

256Kx4O

701601100ns

Same as MCM36256, for error correction applications

3-147

MCM40512

512Kx4O

701601100 ns

Same as MCM36512, for error correction applications

3-159

MCM54100A

4Mxl

6OI7018Ons

Fast page mode cyele time .. 40145155 ns

2-3

MCM54100A·C

4Mxl

70180ns

Industrial temp range (-400 to +85"C)

2·22

MCM54101A

4Mxl

6OI7018Ons

Nibble mode cycle time = 40140140 ns

2-41

MCM54102A

4Mxl

6OI7OI8Ons

Sialic column mode cycle time .. 35140145 ns

2-80

MCM54170B

256Kx 16

70l60I100 ns

Fast page mode - 1 CAS, 2 Write Enables

2-82

MCMSL4170B

256Kx 16

70l60I100 ns

Battery Backup

2-82

MCMSV4170B

256Kx 16

70l60I100 ns

Self Relrash

2-82

MCM54190B

256Kx 18

70l60I100 ns

Fast page mode - 1 CAS, 2 Write Enables

2-84

MCMSL4190B

256Kx 18

70l60I100 ns

Battery Backup

2-84

MCMSV4190B

256Kx 18

701601100 ns

S81f Relrash

2-84

MCM54260B

256Kx 16

701601100 ns

Fast page mode - 2 CAS, 1 Write Enables

2-86

MCMSL4260B

256Kx 16

70l60I100 ns

Battery Backup

2-86

MCM5V4260B

256Kx 16

701601100 ns

SaIl Refresh

2-86

MCM54280B

256Kx 18

701601100 ns

Fast page mode - 2 CAS, 1 Write Enables

2-88

MCM5L4280B

256Kx 18

70180/100 ns

Battery Backup

2-88

MCMSV4280B

256Kx 18

70l60I100 ns

Self Relrash

2-88

MOTOROLA MEMORY DATA

x

ALPHANUMERIC INDEX (Continued)
Device Number

Organization

Addr... Access
ICycienme

Comments

Page

MCM54400A

1Mx4

6OnO/80ns

Fast page mode cycle time = 40/45155 ns

2-90

MCM544OOA-C

1Mx4

70180ns

Industrial temp range (--4O"C to +85"C)

2-111

MCM54402A

1Mx4

6OnO/80 ns

Static column mode cycle time = 35140145 ns

2-131

MCM54410A

1Mx4

6O/70/80ns

Fast page mode cycle time = 45/45/50 ns, Write Per Bit

2-154

MCM54800A

512Kx8

70180/100 ns

Fast page mode cycle time = 45150/60 ns

2-175

MCMSL4800A

512Kx8

70180/100 ns

Battery Backup

2-175

MCMSV4800A

512Kx8

701801100 ns

Self Refresh

2-175

MCM54900A

512Kx9

70180/100 ns

Fast page mode

2-195

MCMSL4800A

512Kx9

70180/100 ns

Battery Backup

2-195

MCMSV4900A

512Kx9

70180/100 ns

Self Refresh

2-195

MCM56824

8Kx24

25130/35 ns

DSPRAM

7-41

MCM56824A

8Kx24

20125135 ns

DSPRAM

7-49

MCM62110

32Kx9

15117120 ns

Synchronous, Dual 110, Parity Checker

7-56

MCM62157

16Kx16

15117124 ns

Sparc Cache, Synchronous

7-66

MCM62350

4Kx4

18/20/25ns

Cache Tag, Programmable Match Level

7-71

MCM62351

4Kx4

18/20/25ns

Cache Tag, Programmable Match Level

7-81

MCM62486

32Kx9

14119124 ns

486 Processor Cache Synchronous BurstRAM

7-91

MCM62486A

32Kx9

14119124 ns

486 Processor Cache Synchronous BurstRAM

7-100

MCM62820

8Kx2O

23/30ns

Latched Address

5-230

MCM62820A

8Kx2O

17/23ns

Latched Address

5-238

MCM62940

32Kx9

14119124 ns

68040 Cache Synchronous BurstRAM

7-110

MCM62940A

32Kx9

14119124 ns

68040 Cache Synchronous BurstRAM

7-118

MCM62950

32Kx9

20125ns

RISC-CISC Cache, Synchronous

7-127

MCM62950A

32Kx9

15120/25 ns

RISC-CISC Cache, Synchronous

7-133

MCM62960

32Kx9

17/20124n8

Synchronous, Output Registers

7-140

MCM62960A

32Kx9

15117124 ns

Synchronous, Output Registers

7-146

MCM62963

4Kx 10

30ns

Synchronous, Output Registers

7-153

MCM62963A

4Kx 10

30ns

Synchronous, Output Registers

7-158

MCM62973

4Kx 12

18/2Ons

Synchronous, Output Registers

7-163

MCM62973A

4Kx 12

18/2Ons

Synchronous, Output Registers

7-168

MCM62974

4Kx 12

18/20 ns

Synchronous, Output Registers, Output Enable

7-173

MCM62974A

4Kx 12

18/2Ons

Synchronous, Output Registers, Output Enable

7-177

MCM62975

4Kx 12

25130ns

Synchronous, Output Enable

7-181

MCM62975A

4Kx 12

25130 ns

Synchronous, Output Enable

7-186

MCM62980

64Kx4

15120ns

Synchronous 1 Slage Pipeline

7-191

MCM62981

4x64Kx 1

15120ns

Parity RAM, Synchronous 1 Slage Pipeline

7-197

MCM62982

64Kx4

12115 ns

Synchronous, Output Registers, 2 Stage Pipeline

7-203

MCM62983

4x64Kx 1

12115 ns

Parity RAM, Synch., Output Registers 2 Stage Pipeline

7-208

MCM62990

16Kx 16

17/2O/25ns

Latched Address, Asynchronous

7-213

MCM62990A

16Kx 16

1512O/25ns

Latched Address, Asynchronous

7-219

MCM62995

16Kx16

17/2O/25ns

Latched Address, Asynchronous

7-226

MCM62995A

16Kx16

12115120 ns

Latched Address, Asynchronous

7-237

MOTOROLA MEMORY DATA

xi

ALPHANUMERIC INDEX (Continued)
Device Number

Organization

Address Acceas
ICycleTime

Comments

Page

MCM62996

16Kx 16

12115120125 ns

MCM672S2

256Kx 4

10112 ns

BiCMOS

5-242

7-249

MCMS1000

lMxS

70180/100 ns

Fast page mode cycle time = 40145/55 ns

3-171

MCMSL1000

lMxS

701801100 ns

Fast page mode with low power battery backup

3-171

MCMS1000A

lMxS

701801100 ns

Low cost derivative of MCMS1000

-

MCMSll000A

lMxS

70180/100 ns

low cost derivative of MCMSll000

MCMS100l

lMxS

70180/100 ns

Nibble mode cycle time = 35/35140 ns

MCMS1002

lMxS

70180/100 ns

Static column mode cycle time = 40145155 ns

-

MCMS1430

lMxS

60170/S011 00 ns

Two chip derivative of MCMS1000S

3-1S3

MCMSL1430

lMxS

60170/80/100 ns

Two chip derivative of MCMSll000S

3-1S3

MCMS4000

4MxS

SOIl 00 ns

Fast page mode cycle time = 50/60 ns

MCMS4000A

4MxS

60170180/100 ns

3-195
3-207

MCMSL4000

4MxS

SOIl 00 ns

Fast page mode with low power battery backup

3-195

MCM84256

256KxS

701S0/100 ns

Fast page mode cycle time = 40/45155 ns

3-219

MCMSl4256

256KxS

701S0/100 ns

Fast page mode cycle time = 40/45155 ns, low power

3-219

MCM91000

lMx9

701S0/100 ns

Fast page mode cycle time = 40/45/55 ns

3-231

MCM9L1000

lMx9

701S0/100 ns

Fast page mode cycle time = 40/45155 ns, low power

3-231

MCM91000A

lMx9

70180/100 ns'

low cost derivative of MCM91000

-

MCM9L1000A

lMx9

70180/100 ns

Low cost derivative of MCM9L 1000

-

MCM91001

lMx9.

70180/100 ns

Nibble mode cycle time = 35/35140 ns

MCM91002

lMx9

701S0/100 ns

Static column mode cycle time = 40145155 ns

MCM91430

lMx9

701S0/100 ns

Three chip derivative of MCM91000S

3-243

MCM9L1430

lMx9

701S0/100 ns

Three chip derivative of MCM9L 1OOOS

3-243

MCM84000

4Mx9

S0I100ns

Fast page mode cycle time = 50/60 ns

3-255

MCMSL4000

4Mx9

S0I100ns

Fast page mode cycle time = 50/60 ns, low power

3-255

MCM94000A

4Mx9

60170180/100 ns

low height 4Mx9 using MCM54100AN DRAM

3.267

MCM9l4000A

4Mx9

60170180/100 ns

Low height 4Mx9 using MCM54100AN DRAM, .Iow power

3-267

MCM94256

256K x 9

701S01100 ns

Fast page mode cycle time = 40/45/55 ns

3-279

MCM9L4256

256Kx 9

70/80/100 ns

Fast page mode cycle time'= 40/45155 ns, low power

3-279

MCM94256A

256K x 9

70180/100 ns

Fast page mode cycle time = 40145155 ns

3-291

MCM9L4256A

256Kx 9

701S01100 ns

Fast page mode cycle dme = 40/45155 ns, low power

3-291

MCM101510

lMxl

10112 ns

ECl

7-254

MCM101514

lMxl

10112 ns

ECL

7-260

MCM511000A

lMxl

701S0/100 ns

Fast page mode cycle time = 40/45/55 ns

2-197

MCM51l1000A

lMxl

701801100 ns

Fast page mode with low power battery backup

2-197

MCM51.1000B

lMxl

60ns

Fast page mode cycle time = 40 ns

2-212

MCM511001A

lMxl

701S0/100 ns

Nibble mode cycle time = 35/35140 ns

2-227

MCM511002A

1Mx1

70/80/100 ns

Static column mode cycle time = 4<1'45155 ns

2-242

MCM514256A

256Kx 4

70180/100 ns

Fast page mode cycle time = 40145/55 ns

2-257

MCM51L4256A

256Kx 4

70/801100 ns

Fast page mode with low power battery backup

2-257

MCM514256B

256Kx 4

60ns

Fast page mode cycle time = 40 ns

2-272

MCM51 L4256B

256Kx 4

60ns

Fast page mode with low power battery backup

2-272

MCM514258A

256K x 4

70/801100 ns

Static column mode cycle time = 40145155 ns

2-287

MOTOROLA MEMORY DATA
xii

-

Selector Guide and Cross Reference

MOTOROLA MEMORY DATA
1-1

SELECTOR GUIDE

DYNAMIC RAMs
erg
Motorola

PackagelnformatJon

Pari Number

lMxl

256Kx4

350-1111 SOJ
(Pins)

Addreaa
A_

Current

(na Max)

(mAMax)

Op

300-1111 DIP
(Plna)

11JO-11111ZIP
(Plna)

3CJO.M11 SOJ
(Plna)

MCM511000A-70

18

20

20126

70

80

MCMSll0ooA-80

18

20

20126

SO

70

MCMSll000A-l0

18

20

20126

100

60

MCMSll000A-C70

18

20

20126

70

85

MCMSll000A-C80

18

20

20126

SO

75

MCMSll000A-Cl0

18

20

20126

100

65

MCMSl L l000A-70

18

20

20126

70

SO

MCMS1L1000A-80

18

20

20126

SO

70

MCMS1Ll000A-l0

18

20

20126

100

60

MCM51Ll000A-C70

18

20

20126

70

85

MCM51Ll000A-C80

.18

20

20126

SO

75

MCMS1Ll000A-C10

18

20

20126

100

65

MCMSll0oo~

20

20126

60

90

MCMS1L1000~

20

20126

60

90
SO

MCM511oo1A-70

18

20

20126

70

MCM511OO1A-80

18

20

20126

SO

70

MCMSllOOlA-10

18

20

20126

100

60

MCMSlloo2A-70

18

20

20126

70

80

MCMSll002A-80

18

20

20126

SO

70

60

MCMSll002A-l0

18

20

20126

100

MCMS14256A-70

20

20

20126

70

80

MCMSl4256A-80

20

20

20126

SO

70

MCMSl4256A-l0

20

20

20126

100

60

MCMS14256A-C70

20

20

20126

70

85

MCMS14256A-C80

20

20

20126

SO

75

MCMS14256A-Cl0

20

20

20126

100

65

MCMSl L4256A-70

20

20

20126

70

SO

MCMS1L4256A-80

20

20

20126

SO

70

MCM51L4256A-l0

20

20

20126

100

60

MCMS1L4256A-C70

20

20

20126

70

85

MCMStL4256A-CSO

20

20

20126

SO

75

MCMSl L4256A-Cl0

20

20

20126

100

65

MCM514256~

20

20126

60

90

MCM51L4256~

20

20126

60

90

20

20126

70

SO

MCMSl4258A-70

20

MOTOROLA MEMORY DATA

1-2

Low
P-

Ind
Tamp

·
·
·

·
·
·
· ·
· ·
· ·
·

·

·
·

··
··
·
· ·
· ·
·

SELECTOR GUIDE

DYNAMIC RAMs (Continued)
Org

Peckegelnformetlon

Motorola

Perl Number
3QO.UII DIP
(Plna)

100....11 ZIP
(Pine)

3QO.UII 80.1
(Plna)

350....1180.1
(Plna)

Add.....
Accesa

Op
Current

(naUax)

(mAUax)

256Kx4

MCM514258A-80

20

20

20126

80

70

(Cont.)

MCM514258A-l0

20

20

20126

100

60

4Mxl

MCM54100A-60

20

70

100

MCM54100A-80

20

20126

MCM54100A-L.->L.-l<..~.

D(DATAOUT) VOH- - - - - - - H I G H Z _ _ _ _ _ _-<1
VQL-

VALID DATA

EARLY WRITE CYCLE
~---------------------tRC----------------------~

~--------------tRAS--------------~

~---tRCD

ADDRESSES VVIH IL-

iii VIHVIL - ~~.::.t....::.t...:.I...:.I...lL-:\L..,;~i:.-_I-_+-_ _ _ _--';~"-rl£....l.'--l.I~-lIi.~~~.::.t...:.I...~

.1

D(DATAIN)

D(DATAOUT)

t~1
tDH=1 ' "
~II~= X;-'1I

o(DATA OUT)

VOH-

_ _ _ _ _ _ _ _ _ _ _1-<1

VOL-

MOTOROLA MEMORY DATA
2-9

VALID DATA

MCM54100A-MCM5L4100A

FAST PAGE MODE EARLY WRITE CYCLE

•
WVIH-

VIL- ~~~~~~~____~~~~~~~-+~~~~~~

D(DATAIN)

__~~~~~~~~

VIHVIL -

..L..."-'......'-"~-Y "'-________~

D (DATA OUT) VOH - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HIGH Z ______________________________
VOL-

FAST PAGE MODE READ-WRITE CYCLE

ADDRESSES VIH VIL-

D (DATA IN) VIH VIL-

D(DATAOUT) VOH VOL -

MOTOROLA MEMORY DATA
2-10

MCM54100A-MCM5L4100A

RAS ONLY REFRESH CYCLE
(Wand Al0 are Don't Care)

~------------------tRC------------------------~

D(DATAOUT) VOH- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HIGHZ _ _ _ _ _ _ _ _ _ _ _ _ _ __
VOL -

CAS BEFORE RAS REFRESH CYCLE
(AD to Al0 are Don't Care)

~----------------tRC--------------~

CAS

VIHVIL- ___~

Iii VIHVIL -

D (DATA OUT)

--'"-"'--"--¥-""""-.:./

~~~=__________---Jllf---------------

MOTOROLA MEMORY DATA
2-11

HIGHZ - - - - - - - - - - - -

•

MCM54100A-MCM5L4100A

HIDDEN REFRESH CYCLE (READ)

ADDRESSES VVIH IL-

iN VIHVIL - -"--"--"-+-"--"-",

D (DATA OUT) VOHVOL-

----------+--<1

HIDDEN REFRESH CYCLE (EARLY WRITE)

ADDRESSES VVIH IL -

iN VIHVIL - "--l>"-->~~~-:¥'-"-+--H---....=f'-loL...:./

D(DATA IN) VIH VIL -,......'-"'-".......-><--><-.>1' l ' ' - - - - - - - - ' . - "'-"-->L.-><--><--"-""-'''-''--'',-,,-,,--''--,,--''--''-,,D(DATAOUT) VOH - _ _ _ _ _ _ _ _ _ _ _ _ HIGHZ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
VOL -

MOTOROLA MEMORY DATA
2-12

MCM54100A-MCM5L4100A

•

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

READ CYCLE

Q(OATAOUT) VOVOH-- ----++--L

EARLY WRITE CYCLE

Q(DATA OUT) VQHVOL- ----++-------+--++- HIGHZ - - - - 1 H - - t - - - - - -

D(DATA IN) VIHVIL - ~...loL...lL....lL...*'".lo£_:.L....;IL_l~~~ ""L.,--_--:--:--_ _

;if "r.....lo<~-lL.,.,..r'f_...v...-"--"'-....."'-....

REAO-WRITE CYCLE

H- - - - - t + Q(DATAOUT) VOVQL-

'cwo

'WP

D(DATAIN) ~II~= ~~X~XX~XX~X~XX~X't""""7'rXX~XX""""-:X~XX~X)fVALIDD~XX

'D:U~

MOTOROLA MEMORY DATA
2-13

MCM64100A-MCM5L4100A

•

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the RAM. During an extended inactive
state (greater than 16 milliseconds or 128 milliseconds in case
of low power device, with the device powered up), a wakeup
sequence of eight active cycles is necessary to ensure proper
operation.
ADDRESSING THE RAM
The eleven address pins on the device are time multiplexed
at the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate II-bit address fields. A total of twenty-two address bits,
eleven rows and eleven columns, will decode one of the
4,194,304 bit locations in the device. RAS active transition is
followed by CAS actiVE;! transition (active = VIL, tRC!Lminimum) for all read or write cycles. The delay between RAS and
CAS active transitions, referred to as the multiplex window,
gives a system designer flexibility in setting up the external addresses into the RAM.
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the 4M RAM:
RAS only refresh cycle, CAS before RAS refresh cycle,
and page mode.
READ CYCLE
The DRAM may be read with four different cycles: "normal"
random read cycle, page mode read cycle, read-write cycle,
and page mode read-write cycle. The normal read cycle is outlined here, while the other cycles are discussed in separate
sections.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (IN) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent olthe address multiplex
window; however, CAS must be active before or attRCD maximum to guarantee valid data out (0) attRAC (access time from
RAS active transition). If the tRCD maximum is exceeded,
read access time is determined by the CAS clock active transi- .
tion (tGAQ),.
_
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. IN must remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data at that bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitry for the next active
cycle. 0 is valid, but not latched, as long as the CAS clock is
active. When the CAS clock transitions to inactive, the output
will switch to High Z (three-state).

WRITE CYCLE
The user can write to the DRAM with any offour cycles: early
write, late write, page mode early write, and page mode readwrite. Early and late write modes are discussed here, while
page mode write operations are covered elsewhere.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of IN to active
(VIU, Early and late write modes are distinguished by the active transition of IN, with respect to CAS. Minimum active time
tRAS and tCAS, and precharge time tRP apply to write mode,
as in the read mode.
An early write cycle is characterized by IN active transition at
minimum time tWQS...before CAS active transition. Data in (D)
is referenced to CAS in an early write cycle. RAS and CAS
clocks must stay active for tRWL and tCWL' respectively, after
the start of the early write operation to complete the cycle.
remains in three-state condition throughout an early write
cycle because IN active transition precedes or coincides with
CAS active transition, keeping data-out buffers disabled. This
feature can be utilized on systems with a common I/O bus, provided all writes are performed with early write cycles, to prevent bus contention.
A late write cycle occurs when IN active transition is made
after CAS active transition. IN active transition could be
delayed for almost 10 microseconds after CAS active transition, (tRCD + tCWD + tRWL + 2IT):5 tRAS, if other timing minimums (tRCD, tRWL, and IT) are maintained. 0 is referenced to
IN active transition in a late write cycle. Output buffers are enabled by CAS active transition but 0 may be indeterminatesee note 15 of ac operating conditions table. RAS and CAS
must remain active for tRWL and tCWL' respectively, after IN
active transition to complete the write cycle.

o

READ-WRITE CYCLE
A read-write cycle performs a read and then a write at the
same address, during thjl same cycle. This cycle is basically a
late write cycle, as discussed in the WRITE CYCLE section,
except IN must remain high for tCWD minimum after the CAS
active transition, to guarantee valid 0 before writing the bit.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
2048 column locations on a selected row of the 4M dynamic
RAM. Read access time in page mode (tCAC) is typically half
the regular RAS clock access time, tRAC' Page mode operation consists of keeping RAS active while toggling CAS between VIH and ~The row is latched by RAS active transition, while each CAS active transition allows selection of a new
column location on the row.
A page mode cycle is initiated by a normal read, write, or
read-write cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to
inactive for minimum of tcp, while RAS remains low (VIL). The
second CAS active transition while RAS is low initiates the first
page mode cycle (tpc ortpRWC). Either a read, write, or readwrite operation can be performed in a page mode cycle, subject to the same conditions as in normal operation (previously
described). These operations can be intermixed in consecutive page mode cycles and performed in any order. The maximum number of consecutive page mode cycles is limited by
tRASP' Page mode operation is ended when RAS transitions
to inactive, coincident with or following CAS inactive transition.

MOTOROLA MEMORY DATA
2-14

MCM54100AeMCM6L4100A

REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically
refreshed (recharged) to maintain the correct bit state. Bits in
the MCM541 OOA require refresh every 16 milliseconds, while
refresh time for the MCMSL41 OOA is 128 milliseconds.
This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 1S.6
microseconds for the MCM54100A, and 124.8 microseconds
for the MCMSL41 OOA. Burst refresh, a refresh of all 1024 rows
consecutively, must be performed every 16 milliseconds on
the MCM541 OOA and 128 milliseconds on the MCMSL41 OOA.
A normal read, write, or read-write operation to the RAM will
refresh all the bits (4096) associated with the particular row decoded. Three other methods of refresh, RA5-only refresh,
CAS before RAS refresh, and hidden refresh are available
on this device for greater system flexibility.
RA5-0nly Refresh
RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(VIH) throughoutthe cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.
CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order activates an internal refresh
counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh
cycle. The output buffer remains at the same state it was in duringthe previous cycle (hidden refresh). Vii must be inactive for
timetWRP before and timetWRH after RAS active transition to
prevent switching the device into test mode.

Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). Vii is subject to the same conditions
with respect to RAS active transition (to prevent test mode
entry) as in CAS before RAS refresh.
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter ofthis device can be tested with
a CAS before RAS refresh counter test. This test is performed with a read-write operation. During the test, the internal
refresh counter generates the row address, while the external
address supplies the column address. The entire array is refreshed after 1024 cycles, as indicated by the check data written in each row. See CAS before RAS refresh counter test
cycle timing diagram.
The test can be performed after a minimum of 8 CAS before
RAS initialization cycles. Test procedure:
1.
Write "O"s into all memory cells with normal write mode.
2.
Select a column address, read "0" out and write "1" into
the cell by performing the CAS before RAS refresh
counter test, read·wrlte cycle. Repeat this operation
1024 times.
3.
Read the "1 "s which were written in step 2 in normal read
mode.
4.
Using the same starting column address as in step 2,
read "1" out and write "0" into the cell by performing the
CAS before RAS refresh counter test, read,wrlte
cycle. Repeat this operation 1024 times.
S.
Read "O"s which were written in step 4 in normal read
mode.
6.
Repeat steps 1 to S using complement data.

CAS BEFORE RAS
REFRESH CYCLE

MEMORY CYCLE

I'

f\

1\

CAS BEFORE RAS
REFRESH CYCLE

/
Q -HIGHZ

/

\.

VALID DATA·OUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA
2-15

'--

)-

•

MCM54100A-MCM6L4100A

•

TEST MODE
The internal organization of this device (512K x 8) allows it
to be tested as.if it were a 512K x 1 DRAM. Nineteen of the
twenty two addresses are used when operating the device in
test mode. Row address AO, and column addresses AO and
A 10 are ignored by the device in test mode. A test mode cycle
reads and/or writes data to a bit in each of eight 512K blocks
(BD-B7) in parallel. External data out is determined by the in-

ternal test mode logic of the device. See the following truth
table and test mode block diagram.
W, CAS before RAS timing puts the device in "Test Mode"
as shown in the test mode timing diagram. A CAS before RAS
or a RAS only refresh cycle puts the device back into normal
mode. Refresh is performed in test mode by using a W, CAS
before RAS refresh cycle which uses intemal refresh address
'
counter.

TEST MODE TRUTH TABLE
D

BO

B1

B2

B3

B4

B5

B6

B7

a

a

a

a

a

a

a

0

0

1

1

1

1

1

1

1

1

1

1

1

-

Q

Any Other

0

TEST MODE
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ±1 0%, T A =0 to 70°C, Unless Otherwise Noted)
READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbol
Parameter

54100A-60
5L4100A-60

54100A·70
5L4100A-70

54100A-80
5L4100A-80

Std.

Alt.

Min

Max

Min

Max

Min

Max

Random Read or Write Cycle Time

tRELREL

tRC

115

135

tCELCEL

tpc

50

-

155

Fast Page Mode Cycle Time

-

-

Access Time from RAS

tRELQV

tRAC

Access Time from CAS

teELQV

tCAC

Access Time from Column Address

tAVQV

tM

Access Time from Precharge ~

teEHQV

tePA

-

RAS Pulse Width

tRELREH

tRAS

RAS Pulse Width (Fast Page Mode)

tRELREH

RAS Hold Time

teELREH

CAS Hold Time

50

45

-

65

10k

tRASP

65

tRSH

25

tRELCEH

teSH

65

CAS Precharge to RAS Hold Time

tCEHREH

tRHCP

CAS Pulse Width

tCELCEH

teAS

55

Un"
ns

45

75

10k

85

10k

ns

200k

75

200k

85

200k

ns

25

50

-

ns

85

45

-

25

45

-

25

10k

25

10k

25

10k

ns

25
35

75

-

75
25
40

-

5

ns

-

65

Notes

85

ns

6,7

25

ns

6,8

45

ns

6,9

50

ns

6

-

ns
ns

Column Address to RAS Lead Time
40
ns
35
45
tAVREH
tRAL
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL'
2. An initial pause of 2001's is required after power-up followed by 8 RAS cycles bsfore propsr device opsration is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition bstween VIH and VIL (or bstween VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which propsr opsration over the full temperature
range (O°C ,;; TA';; 70°C) is ensured.
6. Measured with a current load equivalent to 2 TIL (- 200 1lA, + 4 mAl loads and 100 pF with the data output trip points set at VOH - 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD';; tRCD (max).
8. Assumes that tRCD " tRCD (max).
9. Assumes that IRAD " IRAD (max).

MOTOROLA MEMORY DATA
2-,18

MCM64100A-MCM6L4100A

WRITE, CAS BEFORE RAS REFRESH CYCLE (TEST MODE ENTRY)
(D and AD-AI 0 are Don't Care)

~----------------tRC ----------------~

Vi

V1H V1L -

-'-~y~'--loI~+

_____+~~~...::.t....::.t...::.I....:.L...,;~~'-..:>I:...::.t....::.t...::.I....:.L...,;"'--l~'-l.

Q(OATAOUT) VOH - - - - - - - - - - - HIGHZ - - - - - - - - - - - - VOL - - - - - - " [

MOTOROLA MEMORY DATA

2-17

II

MCM54100A-MCM5L4100A

•

TEST MODE - READ CYCLE

_

V1H _ --""""-

RAS

14---------

V1L -

ADDRESSES VIH V1L -

W V1H VIL - '-'................"'-''';-'........L.....l........'-'~

V

Q (DATA OUT) OL-

VOH-

TEST MODE - EARLY WRITE CYCLE
~------------tRC-------------~

_
V1H _
RAS

---:L

~--------t

RAS---------.! .1:-------:'-

V1L -

~---t

RCD - - - - r o I - - - - t R S H - - - - + i

ADDRESSES V IH V 1L -

14--+--+- tCWL-----+i
~---tWCH

V

W

IH'\""'H--+---tWp---~.(
VIL-~~~~~~~~~~~~-t_------~~~~~~~~~~~~~
I+-+--I-- t R W L - - - - - - I

D(DATAIN) V1H V1L -

xxxxx~
tDS

VALID DATA

I-- I-- t DH

;JXXXXXXXXXXXX)

VOH _
Q (DATA OUT)

--------------

HIGHZ - - - - - - - - - - - - - - - - - -

VOL -

MOTOROLA MEMORY DATA
2-18

MCM54100A-MCM5L4100A

TEST MODE - FAST PAGE MODE READ CYCLE
~-----------------------tRASP------------------------~
VIH----~

RAS

1+---- t PC----~

V1L -

ADDRESSES

Vi

-+--<1

Q (DATA OUT) VOH - _ _ _ _ _ _ _ _

VOL -

TEST MODE - FAST PAGE MODE EARLY WRITE CYCLE

_ V 1H RAS
V1L -

_ V 1H CAS
V 1L -

ADDRESSES VIH V 1L -

Vi

V1H -

VIL-~~~~~~~4-~--~~~~~~+--~~~~~~~+--~~~~~~~~~

V1H Q(DATAIN)
VIL

"...."-"",,",,",,

- ~-"-"",,,--,,-;y

VOH
Q(DATAOUT)

VOL -

J,,-----,.

~r::-7~

J:--___-{.. "'''"'''''' J:--___--,i

rr".,....,'Ir"7""''''''-,,:'~

1='--=;';;":""__ "--'''''-->'-'' "1=-"'::';';;;';"::":'....:r "-'<......:.~ "1=-"'::';';;""""~ "-"-''--'''--'''''--''--''--''-

HIGHZ - - - - - - - - - - - - - - - - - - - -

MOTOROLA MEMORY DATA
2-19

MCM64100A-MCM6L4100A

TEST MODE BLOCK DIAGRAM

•

ADDRESSES

~
Vee

~ 512KBLOCK
I~A
BO

~r

I

;-R
R

512K BLOCK
B1

512K:i0eK

~

TEST MODE

l~
l-a

I

!~

Ih

ADiS-

:=- H
::H

NORMAL

512K:iOCK

512K:.iOCK

TEST MODE

I

-H
'-R
ADDRESSES
BO A1 OR,A10e,~
B1 A1 OR,~AOe
B2 A1 OR,~~
R A1OC,AOC
B3 A1Q!l,
B4 A1QBR,A10e, AOC

Ii>

D·

I

DOUT

it-I
r--

r-

512K:OCK

~

512K:iOCK

I:

,......,
I-

TEST MODE

y

H

1_

512K BLOCK
B7
H

~HH

I

B5 A1Q!l, ~ AOC

B6 A1Q!l, ~ AOC
B7 A10R, A10e, AOe

MOTOROLA MEMORY DATA
2-20

NORMAL

~

MCM54100A-MCM5L4100A

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory Prefix

T

' ' ·T. '. . 11 T
x xx xx

Part Number

.."'"'...., ,.. -,.,.. -, ,.,,-....)
Speed (60 =60 ns, 70 =70 ns, 80

=80 ns)

Package (N = 300-mil SOJ, Z = 100-mil Plastic ZIP)

Full Part Numbers-

MCM54100AN60
MCM54100AN70
MCM54100AN80

MCM54100AN60R2
MCM54100AN70R2
MCM54100AN80R2

MCM5L4100AN60
MCM5L4100AN70
MCM5L4100AN80

MCM5L4100AN60R2 MCM5L4100AZ60
MCM5L4100AN70R2 MCM5L4100AZ70
MCM5L4100AN80R2 MCM5L4100AZSO

MOTOROLA MEMORY DATA
2-21

MCM54100AZ60
MCM54100AZ70
MCM54100AZ80

•

MOTOROLA

-

III

SEMICONDUCTOR

TECHNICAL DATA

MCM54100A-C
Advance Information
4M x 1 CMOS Dynamic RAM
Page Mode
NPACKAGE
3OD-MILSOJ
CASE 822

The MCM54100A-C is a 0.711 CMOS high-speed, dynamic random access memory.
It is organized as 4,194,304 one-bit words and fabricated with CMOS silicon-gate
process technology. Advanced circuit desigl) and fine line processing provide high
performance, improved reliability, and low cost.
The MCM54100A-C requires only 11 address lines; row and column address inputs are multiplexed. The device is packaged in a standard 300-mil and a 100-mil
zig-zag in-line package (ZIP).
•
•
•
•
•
•
•
•
•

Three-State Data Output
Fast Page Mode
Test Mode
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh: MCM54100A-C =16 ms
Fast Access Time (tRAC)
MCM54100A-C70 = 70 ns (Max)
MCM54100A-C80 = 80 ns (Max)
• Low Active Power Dissipation:
MCM54100A-C70 = 550 mW (Max)
MCM54100A-C80 = 468 mW (Max)

ZPACKAGE
PLASTIC
ZIG-ZAG IN-LINE
CASE 836

,

PIN NAMES
AQ-A 10 . . . . . . . . . .. Address Input
D ................... Data Input
Q .................. Data Output
Vii ............ ReadiWrite Enable
RAS . . . . . . .. Row Address Strobe
CAS. . . .. Column Address Strobe
VCC ........ Power Supply (+ 5 V)
VSS.·.· ................ Ground
NC .. . . . . . . . . . . .. No Connection

• Low Standby Power Dissipation:
MCM54100A-C = 11 mW (Max, TTL Levels)
MCM54100A-C = 5.5 mW (Max, CMOS Levels)

PIN ASSIGNMENT
100-MILZIP

Tr-

300- AND 350-MIL SOJ
0[1

iii[ 2

26
25

Q

VSS
Q

RAS[3

24

CAS

NC[ 4

23

NC

Al0 [ 5

22

A9 ••

A9

D
RAS
NC
AO

AO [ 9

18

AS

Ad 10

17

A7

A2 [ 11

16

A6

A3[ 12

15

AS

VCC[ 13

14

A4

A2
VCC

AS

2

.. ..•• CAS
.. W
z. ..
..
3

4

VSS

5

6

8

9

.. ..l!!.
.. l1.
11

12

13

l5.

.. ..
16

17

Al0

NC
AI

A3
A4

l~ A6
19

A7 •• 20

~.!.!.. A8

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA

2-22

MCM54100A-C

BLOCK DIAGRAM

W--------<:1"""-""
1----<.....---+1
___I

D

CAS-----.~----OL

Q

COLUMN
DECODER

AO
AI
A2
A3
A4
AS
A6
A7

AJJ
A9

AIO

-"""'---v'LiJjiijiilli~~~

RAS-------t

VCC

Vss

ABSOLUTE MAXIMUM RATING (See Note)
Rating
Power Supply Voltage
Voltage Relative to V SS for Any Pin Except V CC
Data Out Current

Symbol

Value

Un"
V

VCC

-I to +7

Yin. Vout

-I to +7

V

lout

50

mA

Power Dissipation

PD

700

mW

Operating Temperature Range

TA

-40to+85

°C

Storage Temperature Range

Tstg

-55to
+150

°C

NOTE: Permanent deVice damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

MOTOROLA MEMORY DATA

2-23

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however.
it Is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit.

II

MCM54100A-C

•

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%, T A =- 40 to 85°e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

-

6.5

V

1

Logic Low Voltage, All Inputs

VIL

-1.0

-

0.8

V

1

Min

Max

Unit

Notes

mA

2,3

DC CHARACTERISTICS
Characteristic

Symbol

VCC-Power Supply Current
MCM54100A-C-70, tRC = 130 ns
MCM54100A-C-80, tRC = 150 ns

ICCI

VCC Power Supply Current (Standby) (RAS = CAS = VIH)

ICC2

VCC Power Supply Current During RAS Only Refresh Cycles (CAS = VIH)
MCM54100A-C-70, tRC = 130 ns
MCM54100A-C-80, tRC = 150 ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle (RAS
MCM54100A-C-70, tpc = 45 ns
MCM541 00A-C-80, tpc = 50 ns
VCC Power Supply Current (Standby) (RAS = CAS

= VIH -

= VILJ

ICC4

MCM54 t OOA-C

0.2 V)

ICC5

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM54100A-C-70, tRC = 130 ns
MCM541 00A-C-80, tRC = 150 ns

ICC6

-

100
85

-

60
50

2.0

mA
mA

2,3

rnA

2,3

100
85

-

100
85

1.0

mA

rnA

2

Ilkg(l)

-10

10

~A

Ilka(O)

-10

10

~

Output High Voltage (lOH = - 5 mAl

VOH

2.4

Output Low Voltage (IOL = 4.2 mAl

VOL

-

0.4

V

Symbol

Max

Unit

Notes

Cin

5

pF

5

Input Leakage Current (0 V " Vin " 6.5 V)
Output Leakage Current (CAS = VIH,

a V " Vout " 5.5 V)

-

V

CAPACITANCE (f = 1.0 MHz, TA = 25°C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

AO-Al0, D

Ri'S,m,W

7

Q
pF
7
110 CapaCitance (CAS = VIH to Disable Output)
Cout
NOTES.
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
3. Column address can be changed once or less while RAS = VIL and CAS = VIH.
4. tRAS (max) = 1 ~ is only applied to refresh of battery-back up. tRAS (max) = 1a ~ Is applied to functional operating.
5. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = lat/tN.

MOTOROLA MEMORY DATA

2-24

5

MCM54100A-C

AC OPERATING CONDITIONS AND CHARACTERISTICS
= 5.0 V ± 10%, TA =- 40 to + 85°C, Unless Otherwise Noted)

(Vee
READ, WRITE,

AND READ-WRITE CYCLES (See Notes 1,2,3, and 4)
541DOA-C70

54100A-C80

Symbol
Std.

Alt.

Min

Random Read or Write Cycle Time

Parameter

tRELREL

tRC

130

Max

Read-Write Cycle Time

tRELREL

tRWC

155

Fast Page Mode Cycle Time

tCELCEL

tpc

45

-

Fast Page Mode Read-Write Cycle Time

tCELCEL

tPRWC

70

-

Access Time from RAS

tRELQV

tRAC

-

70

Access Time from CAS

tcELQV

tCAC

20

Access Time from Column Address

tAVQV

tAA

-

Access Time from Precharge CAS

tCEHQV

tCPA

CAS to Output in Low-Z

tCELQX

tCLl

Output Buffer and Turn·Off Delay

tCEHQZ

Transition Time (Rise and Fall)

Min

Unit

Notes

150

-

ns

5

175

ns

5

75

-

-

80

50

Max

ns
ns
ns

6,7

20

ns

6,8

35

-

40

ns

6,9

40

-

45

ns

6

-

ns

6

20

a
a

-

tOFF

a
a

20

ns

10

3

50

3

50

ns

-

ns

IT

IT

RAS Precharge Time

tREHREL

tRP

50

RAS Pulse Width

tRELREH

tRAS

70

10,000

80

10,000

ns

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

70

200,000

80

200,000

ns

RAS Hold Time

tCELREH

tRSH

20

CAS Hold Time

tRELCEH

tCSH

70

CAS Precharge to RAS Hold Time

tcEHREH

tRHCP

40

CAS Pulse Width

tcELCEH

tCAS

20

10,000

20

10,000

ns

RAS to CAS Delay Time

tRELCEL

tRCD

20

50

20

60

ns

11

tRELAV

tRAD

15

35

15

40

ns

12

CAS to RAS Precharge Time

tcEHREL

tCRP

5

-

CAS Precharge Time

tCEHCEL

tcp

10

Row Address Setup Time

tAVREL

tASR

a

Row Address Hold Time

tRELAX

tRAH

10

RAS to Column Address Delay Time

-

-

-

60

20

-

ns

80

-

ns

45

-

ns

10

-

a

-

10

-

5

ns
ns
ns
ns
(continued)

NOTES:
1. VIH min and VIL max are reference levels for measuring timing of ~ Signals. Transition times are measured between VIH and VIL'
2. An initial pause of 200 flS is required after power·up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VI H) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range (O°C ,;; TA ,;; 70°C) is assured.
6. Measured with a current load equivalentto 2 TTL (- 200 flA, + 4 rnA) loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD ,;; tRCD (max).
8. Assumes that tRCD ;, tRCD (max).
9. Assumes that tRAD ;, tRAD (max).
10. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output vottage levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by tcAC'
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
2-25

MCM54100A-C

•

READ, WRITE, AND READ-WRITE CYCLES (Continued)
Symbol
Parameter

54100A-C70

54100A-CBO

Std.

Alt.

Min

Max

Min

Max

Unit

tAVCEL

tASC

0

-

0

ns

Column Address Hold Time

tCELAX

leAH

t5

-

-

15

-

ns

Column Address to RAS Lead Time

tAVREH

tRAL

35

-

40

ns

Read Command Setup Time

twHCEL

tRCS

0

0

Read Command Hold Time Referenced to CAS

leEHWX

tRCH

0

-

-

0

-

ns

13

Read Command Hold Time Referenced to RAS

tREHWX

tRRH

0

-

0

ns

13

Write Command Hold Time Referenced to CAS

leELWH

twCH

15

-

15

-

Column Address Setup Time

Notes

ns

ns

Write Command Pulse Width

twLWH

twP

15

-

15

-

ns

Write Command to RAS Lead Time

twLREH

tRWL

20

-

20

-

ns

Write Command to CAS Lead Time

twLCEH

20

-

20

-

ns

Data in Setup Time

tDVCEL

leWL
tDS

0

0

14

tCELDX

tDH

15

-

ns

Data in Hold Time

-

ns

14

Refresh Period

tRVRV

tRFSH

-

Write Command Setup Time

twLCEL

twcs

0

CAS to Wrne Delay

tCELWL

tCWD

20

RAS to Write Delay

tRELWL

tRWD

70

Column Address to Write Delay Time

tAVWL

tAWD

tCEHWL

tCPWD

MCM54100A

CAS Precharge to Write Delay Time (Page
Mode)

15

ms
16

-

16

0

-

ns

15

20

ns

15

80

-

ns

15

35

-

45

-

ns

15

40

-

45

-

ns

15

CAS Setup Time for CAS Before RAS Refresh

tRELCEL

tCSR

5

-

5

tRELCEH

tCHR

15

-

15

-

ns

CAS Hold Time for CAS Before RAS Refresh
RAS Precharge to CAS Active Time

tREHCEL

tRPC

'0

-

0

-

ns

CAS Precharge Time for CAS Before RAS
Counter Time

leEHCEL

lePT

40

-

40

-

ns

Write Command Setup Time (Test Mode)

twLREL

twTS

10

-

ns

tRELWH

twTH

10

-

10

Write Command Hold Time (Test Mode)

10

Wrne to RAS Precharge Time (CAS Before RAS
Refresh)

twHREL

twRP

10

-

10

-

ns

ns

ns

Write to RAS Hold Time (CAS Before RAS
10
10
ns
tRELWL
twRH
Refresh)
NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in early write cycles and to Wleading edge in read-write cycles.
15. twcs, tRWD, 'CWD, tAWD, and 'CPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; ~ twcs ~ twcs (min). the cycle Is an earty write cycle and the data out pin will remain open circuit (high impedance) throughout
the entire cycle; if leWD ~ tCWD (min), tRWD " tRWD (min), tAWD "tAWD (min), and tCPWD " tCPWD (min) (page mode), the cycle is
a read-write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied, the condition
of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
2-26

MCM54100A-C

•

READ CYCLE

ADDRESSES VVIH -

IL-

Iii VIHVIL - ......"-'''-'~...................................''---'{

o(DATA OUT) VOH- - - - - - - -

VOL-

EARLY WRITE CYCLE
~---------------------tRC---------------------~

~-------------tRAS------------~

1------ tRCD

Iii VIHVIL - -"-->L.."""-..loL.....loL.....lL..:loL...:loL...y"---_I-__-t-_____--'p"-;>......,.'-"'->L..........>L.-"--"--><-......~

·1
to~

towj

D(OATAIN) ~:~=X'....,...X."....,.XX,...,....X...,.,....,XX......,...X..,......,.XM-VA-LlOOA-:rA--"jN(XXXXXXXXXXXXXX
o(DATA OUT)

H
VO
VOL-- - - - - - - - - - - - - - HIGHZ - - - - - - - - - - - - - - - - MOTOROLA MEMORY DATA
2-Z1

MCM54100A·C

READ.WRITE CYCLE
~----------------------tRWC----------------------~

~---------------tMS--------------~

~-----tRCD

tASR
ADDRESSES VVIH Il -

iii

VIH-

VI,l - ..t....-"--"-.>L.:--"--"-"

tOFF
D(DATAOUT) VOH- - - - - - - - - - - HIGHZ
VOl -

--------IHI

FAST PAGE MODE READ CYCLE

'iii

VIHVIl -

V
D(DATAOUT)

OHVOl-

..t......lL.....lL.....lL...!"--"-"

'

------------KIX

MOTOROLA MEMORY DATA
2-28

VALID DATA

MCM54100A-C

FAST PAGE MODE EARLY WRITE CYCLE

W VIHVIL-

D(DATA IN)

~~~~~~~----r-~-+~~~~~~~~~~~--~~~~~~~~

VIHVIL -

-'-"'--'''--'..............~ " -________~

D(DATAOUn VOH - - - - - - - - - - - - - - - - - - H I G H Z - - - - - - - - - - - - - - - VOL -

FAST PAGE MODE READ·WRITE CYCLE

ADDRESSES VIH VIL -

D(DATA IN) VIH VIL -

MOTOROLA MEMORY DATA

2-29

•

MCM54100A-C

RAS ONLY REFRESH CYCLE

rN and Al0 are Don't care)

~------------------tRC------------------------~

- - - - - - - - - - - - - - HIGHZ - - - - - - - - - - - - - -

CAS BEFORE RAS REFRESH CYCLE
(AD to Al0 are Don't Care)

~----------tRC--------~

o(DATA OUT)

~~~= -------.;lfl>------------

MOTOROLA MEMORY DATA
2-30

HIGHZ - - - - - - - - - - -

MCM54100A-C

HIDDEN REFRESH CYCLE (READ)

ADDRESSES VVIH IL-

Vi

VIHVIL -

D(DATAOUT)

VQHVOL -

->1....................,...-"-..........,

---------+-<1

HIDDEN REFRESH CYCLE (EARLY WRITE)

ADDRESSES VV IH IL -

Vi

VIHVIL - ~L..::.'--l..'--loi~~.....lI..-=f--H----=f;..lL.,~

D(DATAOUT) VOH - - - - - - - - - - - - - HIGHZ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
VOL -

MOTOROLA MEMORY DATA

2-31

•

MCM54100A-C

..

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

ADDRESSES VIH VIL -

.L-"--'.......,......,7-7''--'''--''-->L-->L.-'''-....>L...~ 1''----;'""7-----'1 "-"--'''''''''"-i'L..;-''7-"f'--'''--''-->L-->L.....>i....

READ CYCLE

Q(DATAOUT) VOH- - - - - t + - - VOL-

EARLY WRITE CYCLE

H
Q(DATA OUT) VO
VO -- ----+f---------II-----+-+-- HIGH Z ----+-f-+-----L

D(DATAIN) VIHVIL -

..j4.-"'--"'--"--l'-,-"--"--"--"--"--"--'"

~--r-tOFF

READ-WRITE CYCLE

Q(DATA OUT) VOH- ----+t-VOL-

tewD

D(DATA IN)

twp

~II~=\-"--'X"""""""XX"""""""'XX~X~XX""""""'X'""""""""XX""""""XX--"'-X""""""XX~x'tVAUiD~~XX"""""""'XX~XX-,.:--rX
tD:~.~H

MOTOROLA MEMORY DATA

2-32

MCM54100A-C

DEVICE INITIALIZATION

WRITE CYCLE

On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the RAM. During an extended inactive
state (greater than 16 milliseconds with the device powered
up), a wakeup sequence of eight active cycles is necessary to
ensure proper operation.

The user can write to the DRAM with any offourcycles: early
write, late write, page mode early write, and page mode readwrite. Early and late write modes are discussed here, while
page mode write operations are covered elsewhere.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of IN to active
(V,Ll. Early and late write modes are distinguished by the active transition of IN, with respect to CAS. Minimum active time
tRAS and tCAS, and precharge time tRP apply to write mode,
as in the read mode.
An early write cycle is characterized by IN active transition at
minimum time twcs before CAS active transition. Data in (D)
is referenced to CAS in an early write cycle. RAS and CAS
clocks must stay active for tRWL and tCWL' respectively, after
the start of the early write operation to complete the cycle.
remains in three-state condition throughout an early write
cycle because IN active transition precedes or coincides with
CAS active transition, keeping data-out buffers disabled. This
feature can be utilized on systems with a common 1/0 bus, provided all writes are performed with early write cycles, to prevent bus contention.
A late write cycle occurs when IN active transition is made
after CAS active transition. IN active transition could be
delayed for almost 10 microseconds aiter CAS active transition, (tRCD + tCWD + tRWL + 2fT)"; tRAS, if other timing minimums (tRCD, tRWL, and tTl are maintained. 0 is referenced to
IN active transition in a late write cycle. Output buffers are enabled by CAS active transition but may be indeterminate see note 15 of ac operating conditions table. RAS and CAS
must remain active for tRWL and tCWL, respectively, aiter IN
active transition to complete the write cycle.

ADDRESSING THE RAM
The eleven address pins on the device are time multiplexed
at the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 11-bit address fields. A total of twenty-two address bits,
eleven rows and eleven columns, will decode one of the
4,194,304 bit locations in the device. RAS active transition is
followed by CAS active transition (active = V'L, tRQQ..!llinimum) for all read or write cycles. The delay between RAS and
CAS active transitions, referred to as the multiplex window,
gives a system designer flexibility in setting up the external addresses into the RAM.
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the ex1ernal CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the 4M RAM:
RAS only refresh cycle, CAS before RAS refresh cycle,
and page mode.

a

a

READ CYCLE

READ-WRITE CYCLE

The DRAM may be read with four different cycles: "normal"
random read cycle, page mode read cycle, read-write cycle,
and page mode read-write cycle. The normal read cycle is outlined here, while the other cycles are discussed in separate
sections.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (IN) input level must be high
(V,H), tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex
window; however, CAS must be active before or altRCD maximum to guarantee valid data out (a) at tRAC (access time from
RAS active transition). If the tRCD maximum is exceeded,
read access time is determined by the CAS clock active transi_
tion (tG.8Ql..
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. IN must remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data althat bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitry for the next active
cycle.
is valid, but not latched, as long as the CAS clock is
active. When the CAS clock transitions to inactive, the output
will switch to High Z (three-state).

A read-write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically a
late write cycle, as discussed in the WRITE CYCLE section,
except IN must remain high for tCWD minimum aiter the CAS
active transition, to guarantee valid before writing the bit.

a

PAGE MODE CYCLES
Page mode allows fast successive data operations at all
2048 column locations on a selected row of the 4M dynamic
RAM. Read access time in page mode (tCAel is typically half
the regular RAS clock access time, tRAC. Page mode operation consists of keeping RAS active while toggling CAS between V,H and V,L. The row is latched by RAS active transition, while each CAS active transition allows selection of a new
column location on the row.
A page mode cycle is initiated by a normal read, write, or
read-write cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to
inactive for minimum oftCP, while RAS remains low (V,L). The
second CAS active transition while RAS is low initiates the first
page mode cycle (tpc ortpRWel. Either a read, write, or readwrite operation can be performed in a page mode cycle, subject to the same conditions as in normal operation (previously
described). These operations can be intermixed in consecutive page mode cycles and performed in any order. The maximum number of consecutive page mode cycles is limited by
tRASp. Page mode operation is ended when RAS transitions
to inactive, coincident with or following CAS inactive transition.

a

MOTOROLA MEMORY DATA
2-33

•

MCM64100A-C

•

REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically
refreshed (recharged) to maintain the correct bit state. Bits in
the MCM54100A-C require refresh every 16 milliseconds.
This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM541 OOA. Burst refresh, a refresh of
all 1024 rows consecutively, must be performed every 16 milliseconds on the MCM541 OOA.
A normal read, write, or read-write operation to the RAM will
refresh all the bits (4096) associated with the particular row decoded. Three other methods of refresh, RAS-Only refresh,
CAS before RAS refresh, and hidden refresh are available
on this device for greater system flexibility.

Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle. while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). Wis subject to the same conditions
with respect to RAS active transition (to prevent test mode
cycle) as in CAS before RAS refresh.
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CAS before RAS refresh counter test. This test is performed with a read-write operation. During the test, the internal
refresh counter generates the row address, while the external
address supplies the column address. The entire array is refreshed after 1024 cycles, as indicated by the check data written in each row. See CAS before RAS refresh counter test
cycle timing diagram.
The test can be performed after a minimum of 8 CAS before
RAS initialization cycles. Test procedure:
1.
Write "O"s into all memory cells with normal write mode.
2.
Select a column address, read "0" out and write "1" into
the cell by performing the CAS before RAS refresh
counter test, read-write cycle. Repeat this operation
1024 times.
3.
Read the "1"s which were written in step 2 in normal read
mode.
4.
Using the same starting column address as in step 2,
read "1" out and write "0" into the cell by performing the
CAS before RAS refresh counter test, read·wrlte
cycle. Repeat this operation 1024 times.
5.
Read "O's which were written in step 4 in normal read
mode.
6.
Repeat steps 1 to 5 using complement data.

RAS-Only Refresh
RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(VI H) throughoutlhe cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.
CAS Before fiE Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order activates an internal refresh
counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh
cycle. The output buffer remainsatthe same state it was in during the previous cycle (hidden refresh). Wmust be inactive for
time twRP before and time twRH after RAS active transition to
prevent switching the device into a test mode cycle.

CASBEFORE~

REFRESH CYCLE

MEMORY CYCLE

I'

r'

r-...

CAS BEFORE RAS
REFRESH CYCLE

/
a

-HIGHZ

"

VALID DATA·OUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA
2-34

-

)-

MCM64100A-C

TEST MODE
The internal organization of this device (512K x 8) allows it
to be tested as if It were a 512K x 1 DRAM. Nineteen of the
twenty-two addresses are used when operating the device in
test mode. Row address AO, and column addresses AO and
A 10 are ignored by the device in test mode. A test mode cycle
reads andlor writes data to a bit in each of eight 512K blocks
(So-B7) in parallel. Extemal data out is determined by the in-

ternal test mode logic of the device. See following truth table
and test mode block diagram.
iii, CAS before RAS timing puts the device in ''Test Mode"
as shown in the test mode timing diagram. A CAS before RAS
or a RAS only refresh cycle puts the device back into normal
mode. Refresh is performed in test mode by using a W, CAS
before RAS refresh cycle which uses internal refresh address
counter.

TEST MODE TRUTH TABLE
D

BO

B1

B2

B3

B4

B5

B6

B7

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

-

Q

Any Other

0

TEST MODE
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA
40 to + 85°C, Unless Otherwise Noted)
Z

-

READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2, 3, and 4)
54100A-C70

Symbol

Parameter

54100A-C80

SteI.

AH.

Min

Max

Min

Max

UnH

Notes

Random Read or Write Cycle Time

tRELREL

tRC

135

155

5

teELCEL

tpc

50

-

ns

Fast Page Mode Cycle Time

-

Access Time from RAS

tRELQV

tRAC

85

ns

6,7

Access Time from CAS

tCELQV

tCAC

25

ns

6,8

Access Time from Column Address

tAVQV

tM

45

ns

6,9

Access Time from Precharge CAS

teEHQV

50

ns

6

RAS Pulse Width

tRELREH

tePA
tRAS

-

55

ns

45

-

75

10 k

85

10k

ns

75
25
40

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

75

200k

85

200 k

ns

RAS Hold Time

teELREH

tRSH

25

25

CAS Hold Time

tRELCEH

tCSH

75

85

teEHREH

tRHCP

45

50

-

ns

CAS Precharge to RAS Hold Time

-

CAS Pulse Width

teELCEH
tAVREH

tCAS
tRAL

25

10k

25

10k

ns

-

-

ns
ns

Column Address to RAS Lead lime
40
45
ns
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL'
2. An initial pause of 200 I1S is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all Input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specificalions for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range (O°C S TA S 70'C) is ensured.
6. Measured with a current load equivalent to 2 TTL (- 200 I1A, + 4 mAl loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD S tRCD (max).
8. Assumes that tRCD ~ tRCD (max).
9. Assumes that tRAD 2: tRAD (max).

MOTOROLA MEMORY DATA
2-35

•

MCM54100A·C

•

,

W, CAS BEFORE RAS REFRESH CYCLE (TEST MODE ENTRY)
(D and AG-A10 are Don" Care)

~--------------- tRC----------------~

tRAS ------------t

J,,--""";';;--"'-

J>--tO_FF_ _ _ _ _ _ _ _ __
HIGHZ --...;...--~----

TEST MODE - READ CYCLE

_

V1H -

RAS V

--~

1+--------

IL-

ADDRESSES VIH V1L -

Vi V1H V1L -L...l~~L....lo~~:.....lL~~~

1+----If-t OF,F

Q (DATA OUT)

~--------- tRAC ---------j;~'j...----~-~
V
OL- - - - - - - - HIGHZ - - - - - - - - - { I
VALID DATA
VOH-

MOTOROLA MEMORY DATA
2-36

1':

MCM54100A-C

TEST MODE - EARLY WRITE CYCLE
~----------------------tRC------------------------~

_
V1H _
RAS V
IL -

---~ ~---------------t RAS--------------~

~---

J,-------::L

t RCD ----"*'o----tRSH - - - - i O o I

ADDRESSES VIH V1L -

I-+--t-- tCWL-----i
"""7':"'"'7'r7':"'"~~~~~'"
i""1----tWCH
iN IH 'l.i""f-/--j--- twp - - - - + i / .
VIL-~~~~~~~~~~~-r-t-------~~~~~~~~~~~~~
I+--t---+--t RWL------.j
V

D(DATAIN)

::~ =.XXXXXXXX>N
VALIDDATA]()O(XXXXXXXXXX)
~-J ~~tDH~
VOH _

Q(DATAOUT)

-------------

HIGHZ

VOL -

TEST MODE - FAST PAGE MODE READ CYCLE

V1H - - - - . .
RAS

~------------ tRASP

V1L -

-------------0001

1 + - - - - tpc - - - - + I

ADDRESSES

iN V1H VIL-~~~*:J

Q (DATAOUT)V OH VOL -

--------t-L...:>L...:>L...:~4-+---"'~::.L~~D.(..::.L~

Q (DATA IN) VIH VIL -

~~loL....l~ 'F:-...;;.;.;;.;.;.;;..'--'r "'~-"-'" .,.......:;;.;;;.;.;;.;.,..;~ "'-....loL..~'"

V
Q(DATAOUT) OH-_ _ _ _ _ _ _ _ _ _ _ _ __

HIGHZ

VOL -

MOTOROLA MEMORY DATA
2-38

1'-"";';';---'__ "--'''-''......~~-''-~

MCM54100A-C

•

TEST MODE BLOCK DIAGRAM

ADDRESSES

."!
Vee

~ 512KBLOCK
I~A
BO

OO-r

I

r-

rJ

TEST MODE

~ 512KBLOeK
I~B
B1
I

~ 512KBLOeK
t~e
B2
I

AD~
I

~
~
NORMAL

t-...-.

D

~ 512KBLOeK
B3

1_D

I

DOUT

~

512KBLOCK
B4

~
E

I

TEST MODE

.--r-

'--

~ 512K:kOeKr

~

t--

- ~ 512KBLOCK
I~G
B6
I

ADDR ESSES
BO
B1
B2
B3

B4

B5
B6
B7

A1 OR, A10e, AQQ
A1 OR,~AOe
A1 OR,~AOe
R A10e,AOe
A1QB,
A1QB,A10e, AOe
A1QB, ~ AOe
A1QB, A1QQ, AOe
A10R, A10e, AOe

TEST MODE

y

512KBLOCK
B7

~

Hii
~L------II
1

H

I,H

NORMAL

I

ADDRESSES

MOTOROLA MEMORY DATA
2-39

MCM54100A-C

.'

ORDERING INFORMATION
(Order by Fu" Part Number)

Motorola Memory Prefix ____T_M_C_M_ _ _T54--l100A
Part Number

Full Part Numbers

-

MCM54100ANC70
MCM54100ANCBO

MCM54100ANC70R2
MCM54100ANCBOR2

MOTOROLA MEMORY DATA
2-40

MCM54100AZ70
MCM54100AZBO

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

L--M_C_M5_4_10_1A---li.

Advance Information
4M x 1 CMOS Dynamic RAM

4"

Nibble Mode
The MCM54101A is a 0.711 CMOS high-speed, dynamic random access memory. It
is organized as 4,194,304 one-bit words and fabricated with CMOS silicon-gate process technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low cost. The fast nibble mode feature allows
high-speed serial access of up to 4 bits of data.
The MCM541 01 A requires only 11 address lines; row and column address inputs
are multiplexed. The device is packaged in a standard 300-mil and small outline
package, and a 100-mil zig-zag in-line package (ZIP).

N PACKAGE
300-MILSOJ
CASE 822

ZPACKAGE
PLASTIC
ZIG-ZAG IN-LINE
CASE 836

•
•
•
•
•
•
•
•
•

Three-State Data Output
Nibble Mode
Test Mode
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh: MCM54101A = 16 ms
Fast Access Time (tRAC):
MCM541 01 A-60 = 60 ns (Max)
MCM54101 A-70 = 70 ns (Max)
MCM54101 A-80 = 80 ns (Max)
• Low Active Power Dissipation:
MCM54101 A-60 660 mW (Max)
MCM54101 A-70 = 550 mW (Max)
MCM54101 A-80 = 468 mW (Max)
• Low Standby Power Dissipation:
MCM54101A = 11 mW (Max, TTL Levels)
MCM54101A = 5.5 mW (Max, CMOS Levels)

PIN NAMES
AO-Al0 ......... Address Input
D " " " " " , , " , , . Datalnput
Q " " " " " " " " DataOutput
W .......... ReadlWrite Enable
RAS . . . . .. Row Address Strobe
CS " " . , , " " " " ChipSelect
VCC ...... Power Supply (+ 5 V)
VSS ......... " ....... Ground
NC ............ NoConnection

=

PIN ASSIGNMENT
100-MILZIP
~-

300-MILSOJ
D[ 1

26

iN

[2

25

RAS [ 3

24

NC [4

23

Al0 [5

22

PVSS
PO
PCAS
PNC
PA9

A9 ••

==

D

..

RAS
NC
AO

AO

9

18

Al

10

17

A2

11

16

A3

12

15

VCC

13

14

PA8
PA7
PA6
PA5
PA4

3

0

A2
VCC

AS

.2. CAS
4
VSS

5

7

6

== iN
8

.. ==
.. ==
.. H
9

10

11

12

13

15.

16

.. 18"=.

17

19
A7 •• 20

Al0
NC
Al

A3
A4
A6

,---=-=.AB

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
2-41

MCM&4101A

BLOCK DIAGRAM

W
CAS

DATA IN
BUFFER

D

DATA,OUT
BUFFER

a

COLUMN
DECODER

AO
AI

A2
A3
A4
AS
A6
A7
AS
A9
AIO

RAS

VCC
Vss

ABSOLUTE MAXIMUM RATING (See Note)
Rating
Power Supply Voltage

Symbol

Value

Unit
V

VCC

-I to +7

Vin. Vout

-1 to +7

V

Data Out Current

lout

50

mA

Vottage Relative to VSS for Any Pin Except VCC
Power DisSipation

Po

700

mW

Operating Temperature Range

TA

o to +70

Storage Temperature Range

Tstg

-55to
+150

'c
'c

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded, Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

MOTOROLA MEMORY DATA

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however. it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high-impedance
circuit.

MCM54101A

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, T A = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

logic High Voltage, All Inputs

VIH

2.4

-

6.5

V

1

logic low Voltage, All Inputs

Vil

-1.0

-

0.8

V

1

Min

Max

Unit

Notes

mA

2,3

DC CHARACTERISTICS
Characteristic

Symbol

VCC Power Supply Currenl
MCM54101A-60, tRC = 110 ns
MCM54101A-70, tRC = 130 ns
MCM54101A-80, tRC = 150 ns

ICCI

VCC Power Supply Current (Standby) (RAS=CAS=VIH)

ICC2

VCC Power Supply Current During RAS Only Refresh Cycles (CAS=VIH)
MCM54101A-60, tRC = 110 ns
MCM54101A-70, tRC = 130 ns
MCM541 01 A-80, tRC = 150 ns

ICC3

VCC Power Supply Current During Nibble Mode Cycle (RAS = VILl
MCM541 01 A-60, tNC = 40 ns
MCM54101A-70, tNC =40 ns
MCM541 01 A-80, tNC = 40 ns

ICC4

VCC Power Supply Current (Standby) (RAS=CAS=VCC-0.2 V)

ICC5

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM54101A-60, tRC = 110 ns
MCM54101A-70, tRC = 130 ns
MCM54101 A-80, tRC = 150 ns

ICC6

Input leakage Current (0 V ,; Vin :;; 6.5 V)
Output leakage Current (CAS = VIH, 0 V " Vout :;; 5.5 V)

-

-

-

120
100
85
2.0

mA
mA

2,3

mA

2,3

120
100
85
50
50
50
1.0

mA
mA

-

2

-

120
100
85

Ilkg(l)

-10

10

Ilkg(O)

-10

10

Output High Voltage (IOH = - 5 mAl

VOH

2.4

-

V

Output low Voltage (IOl = 4.2 mAl

VOL

-

0.4

V

Symbol

Max

Unit

Notes

Cin

5

pF

4

-

!lA
!lA

CAPACITANCE (f = 1.0 MHz, TA = 25'C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

AO-Al0, D
RAS,CAS,W

7

Output Capacitance (CAS = VIH to Disable Output)
pF
4
7
Q
Cout
NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
3. Column address can be changed once or less while RAS = Vil and CAS = VIH.
4. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = IllVllV.

MOTOROLA MEMORY DATA
2-43

•

MCM54101A

•

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA = 0 to 70o e, Unless Otherwise Noted)

READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2 3 and 4)
Symbol
Parameter

54100A-60
Max

54100A-70
Min

Std.

Alt.

Min

Random Read or Write Cycle lime

tRELREL

tRC

110

-

130

Read-Write Cycle lime

tRELREL

tRWC

135

155

Nibble Mode Cycle lime

tCEHCEH

tNC

40

-

Nibble Mode Read-Write Cycle Time

tCELCEL

tNRWC

Access Time from RAS

tRELQV

tRAC

Access lime from CAS

teELQV

Max

40

-

54100A-80
Min

Unit

Notes

150

-

ns

5

175

ns

5

Max

65

-

65

-

65

-

-

60

-

70

-

80

ns

6,7

20

20

ns

6,8

30

35

-

20

-

-

40

ns

6,9

20

-

20

-

20

ns

6

40

ns
ns

Access Time from Column Address

tAVQV

teAC
tAA

Nibble Mode Access lime

teELQV

tNCAC

-

CAS to Output in Low-Z

tCELQX

teLZ

0

-

0

-

0

-

ns

6

Output Buffer and Turn-Off Delay

tCEHQZ

tOFF

0

20

0

20

0

20

ns' '.

10

Transition lime (Rise and Fall)

IT

tT

3

50

3

50

3

50

ns

RAS Precharge Time

tREHREL

tRP

40

-

50

-

60

-

ns

RAS Pulse Width

tRELREH

tRAS

60

10k

70

10k

80

10k

ns

RAS Hold lime

tCELREH

tRSH

20

-

20

-

20

-

ns

CAS Hold lime

tRELCEH

teSH

60

-

70

-

80

-

ns

CAS Pulse Width

tCELCEH

teAS

20

10 k

20

10 k

20

10 k.

ns

RAS to CAS Delay lime

tRELCEL

tRCD

20

40

20

50

20

60

ns

11

RAS to Column Address Delay lime

tRELAV

tRAD

15

30

15

35

15

40

ns

12

CAS to RAS Precharge lime

teEHREL

tCRP

5

-

5

tcp

10

10

-

10

-

0

0

-

10

-

-

ns

tCEHCEl

-

5

CAS Precharge Time

10

-

ns

Row Address Setup Time

tAVREL

tASR

0

Row Address Hold lime

tRELAX

tRAH

10

ns
ns

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 IlS is required after power-up followed by 8 RAS cycles belore proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VI H) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range (O°C ,; TA ,; 70°C) is ensured.
6. Measured with a current load equivalentto.2 TTL (- 200 lIA, + 4 mAl loads and 100 pFwith the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD'; tRCD (max).
8. Assumes that tRCD " tRCD (max).
9. Assumes that tRAD ;;, tRAD (max).
'"
1O. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC'
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) Is specified as a reference point only; if tRAD is
greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
2-44

MCM54101A

READ, WRITE, AND READ-WRITE CYCLES (Continued)
Symbol
Parametar

541 01 A-60

541 01 A-70

541 01 A-60

Std.

Alt.

Min

Max

Min

Max

Min

tAVCEL

tASC

0

0

-

0

Column Address Hold Time

!cELAX

tCAH

15

15

Column Address to RAS Lead Time

tAVREH

tRAL

30

-

-

0

-

0

0

-

0
15

Column Address Setup Time

Read Command Setup Time

twHCEL

tRCS

0

Read Command Hold Time
Referenced to CAS

tCEHWX

tRCH

0

Read Command Hold Time
Referenced to !'lAS

tREHWX

tRRH

0

Write Command'Hold Time
Referenced to CAS

tCELWH

twCH

10

Write Command Pulse Width

twLWH

twP

10

Write Command to RAS Lead Time

twLREH

tRWL

20

Write Command to CAS Lead Time

twLCEH

!cWL

20

Data in Setup Time

tDVCEL

tDS

Data in Hold Time

!cELDX

Refresh Period

tRVRV

35

15
20
20

0

-

tDH

15

15

tRFSH

-

16

0

-

Write Command Setup Time

twLCEL

twcs

0

CAS to Write Delay

!cELWL

tCWD

20

-

RAS to Write Delay

tRELWL

tRWD

60

-

70

Column Address to Write Delay Time

tAVWL

tAWD

30

35

CAS Setup Time for CAS Before RAS
Refresh

tRELCEL

!cSR

5

CAS Hold Time for CAS Before RAS

tRELCEH

tCHR

15

RAS Precharge to CAS Active Time

tREHCEL

tRPC

0

-

CAS Precharge Time for CAS Before
RAS Counter Test

tCEHCEL

!cPT

30

-

40

Refresh

0
20

5
15
0

Max

Unit

Note.

-

ns

15

-

ns

40

-

ns

-

ns

0

ns

13

-

0

-

ns

13

-

15

-

ns

16

-

15

-

ns

20

-

ns

20

ns

0

-

ns

14

15

-

ns

14

-

16

ms

0

-

ns

15

ns

15

ns

15

45

-

ns

15

5

-

ns

15

-

ns

0

-

ns

40

-

ns

20
80

(continued)
NOTES:
13. Either tRRH or tRCH must be staisfied for a read cycle.
14. These two parameters are referenced to CAS leading edge in early write cycles and to iN leading edge in read-write cycles.
15. twcs, tRWD, tCWD. tAWD, and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if twcs ;, twcs (min). the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout
the entire cycle; ~ tCWD ;, tCWD (min), tRWD ;, tRWD (min), tAWD ;, tAWD (min), and !cPWD ;, tCPWD (min) (page mode), the cycle Is
a read-write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied, the condnion
of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA

2-46

•

MCM54101A

•

READ, WRITE, AND READ-WRITE CYCLES (Continued)
'Parameter
Nibble Mode Pulse Width
Nibble Mode CAS Precharge Time
Nibble Mode RAS Hold Time
Nibble Mode CAS to Write Delay Time

Symbol

54101A-60

Std.

All.

Min

tCELCEH

INCAS

20

tcEHCEL

INcp

10

tCELREH

tNRSH

20

tcELWL

tNCWD'

20

-

Nibble Mode Write Command to RAS
Lead Time

twLREH

tNRWL

20

Nibble Mode Write Command to CAS
Lead Time

twLCEH

tNCWL

20

Write Command Setup Time (Test
Mode)

tWLREL

twTs

10

Wr~e

Command Hold Time (Test
Mode)

tRELWH

twTH

Write to RAS Precharge Time (CAS
Before RAS Refresh)

twHREL

Write to RAS Hold Time (CAS Before

tRELWL

RAS Refresh)

Max

54101A·70

Min

20

-

20

-

20
10
20
20

541 01 A-80
Min

Max

ns

20
20

-

ns
ns

ns

10
20
20

10

10

10

-

10

-

10

-

10

10

twRP

10

-

twRH

10

.-

10

MOTOROLA MEMORY DATA

Un"

-

20

-

-

2-48

Max

10

ns
ns
ns
ns

ns
ns

Nolee

MCM64101A

•

READ CYCLE

ADDRESSES VVIH IL-

iii VIHVIL - '-''-''-'~'''''''''''''''''''''-'':......l{

o(DATA OUT)

VQH-

VOL-

------

EARLY WRITE CYCLE

~-----------tRC-------------------~

1 - - - - - - - - - - tRAS ----'-'-----------1
RAS VIH- ----~
VIL-

~-----~
1----tRCD

tASR
ADDRESSES VVIH IL-

iii VIHVIL - ..::.I...~~::.i....::.i....~~"'--l"-=ll:""---1_-+-----......:l~'-T':...lL~...lL.->L--"--><--"-"""""'-""""

tD~
D(DATAIN)

~II~ -......,X,.....X,......X.,.....X..,...X...,...X....,..X""'7'I:X...."X~M

o (DATA OUT) VOH VOL-

3<--><--><--"--"--'"

Q (DATA OUT) VOH-

- - - - - - - - - HIGHZ _________1--(1

VALID DATA

VOL-

NIBBLE MODE READ CYCLE
tRAS --------------------~

xxxxxxx

VI
MOTOROLA MEMORY DATA

MCM54101A

••

NIBBLE MODE EARLY WRITE CYCLE

iii

VIHVIL_ ~~~~~~~~+-~~~~=-++~~~~~

D(DATA IN)

VIHVIL -

Q (DATA OUT) VO H-

J......~"--''-"'~-Y ""f-,,....,....-""'1

------------------------------

VOL-

NIBBLE MODE READ-WRITE CYCLE

ADDRESSES VIH VIL-

iii

D (DATA IN)

VIHVIL-

VIHVIL-

MOTOROLA MEMORY DATA
2-49

__~~~~~__~~~~~~~

MCM64101A

..

RAS ONLY REFRESH CYCLE

rN and A1D are Don't Care)
~----------tRC-------------~

CAS VIH -

"'"7I:-:t-+t-----------------......:..::.:±;;.~..,.....,----

VIL-

H- - - - - - - - - - - - - - Q (DATA OUT) VO
Vm-

~~Z - - - - - - - - - - - - - -

CAS BEFORE RAS REFRESH CYCLE
(AD to A1D are Don't Care)

14--------- tRC --------+1

WVIHVIL -

Q (DATA OUT)

~~7\7r~~r----~~~""~~~~~~~~~~~~~~
-"-->L-,,"-¥-~.:.t

~~:= -----_1-----------

MOTOROLA MEMORY DATA
2-60

HIGHZ - - - - - - - - - - -

MCM54101A

HIDDEN REFRESH CYCLE (READ)

VVIH -

ADDRESSES

Il-

_VIH-~~"7r7r7r~r-~~--------~7r7r~r-----~~"~~~~~~""7

W Vil -

Q (DATA OUT)

VOH-

VQl-

~..lL.....lL...*-lL....l~
------------------~_I

Vil - L...:.I.~"""'~...l4~~

,,'--_ _ _ _---'T " .......~...l4~~...lL......lL....lL...loL...,;lL....l""'_.lL...l.L...l.'__lo<~

VOH - ----------------------- HIGH Z - - - - - - - - - - - - - - - - - - - -___________
VOl-

MOTOROLA MEMORY DATA
2-51

•

MCM64101A

..

CAS BEFORE RAS REFRESH COUNTE.R TEST CYCLE

READ CYCLE
Q (DATA OUT) YOHYOL -

----t+---

EARLY WRITE CYCLE
Q (DATA OUT) YOHVQL-

D(DATAIN)

----t+-------+---t+- HIGtiZ ----H+------

VIHVIL - .......................t';-"-'''-'......................... ....;--_--;-;-_ _..Il

-:";+...............................

" .................

READ-WRITE CYCLE
Q(DATAOUT) VOHYOL-

----t+-

tewD
D(DATAIN)

.

~II~= K"""""X"""""XX""""'XX""""'X""""XX""""XX"-"-X"""""XX""""'X""""'XX"""""'X'>GUO DATAWXXXXXXX
tD:~~H.

MOTOBOLA MEMORY DATA
2-52

MCM54101A

tRP to precharge the internal device circuitryforthe next active
cycle. Q is valid, but not latched, as long as the CAS clock is
active. When the CAS clock transitions to inactive, the output
will switch to High Z (three-state).

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the RAM. During an extended inactive
state (greater than 16 milliseconds or 128 milliseconds in case
of low power device, with the device powered up), a wakeup
sequence of eight active cycles is necessary to ensure proper
operation.

WRITE CYCLE
The user can write tothe DRAM with any offour cycles: early
write, late write, nibble mode early write, and nibble mode
read-write. Early and late write modes are discussed here,
while nibble mode write operations are covered in another section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
(VIU. Early and late write modes are distinguished by the active transition of W, with respect to CAS. Minimum active time
tRAS and tCAS, and precharge time tRP apply to write mode,
as in the read mode.
An early write cycle is characterized by Wactive transition at
minimum time tWQS...before CAS active transition. Data in (D)
is referenced to CAS in an early write cycle. RAS and CAS
clocks must stay active for tRWL and tCWL' respectively, after
the start of the early write operation to complete the cycle.
Q remains in three-state condition throughout an early write
cycle because Wactive transition precedes or coincides with
CAS active transition, keeping data-out buffers disabled. This
feature can be utilized on systems with a common I/O bus, provided all writes are performed with early write cycles, to prevent bus contention.
A late write cycle occurs when Wactive transition is made
after CAS active transition. W active transition could be
delayed for almost 10 microseconds after CAS active transition, (tRCD + tCWD + tRWL + 2IT) $ tRAS, if other timing minimums (tRCD, tRWL, and IT) are maintained. 0 is referenced to
Wactive transition in a late write cycle. Output buffers are enabled by CAS active transition but Q may be indeterminatesee note 15 of ac operating conditions table. RAS and CAS
must remain active for tRWL and tCW!,.., respectively, after W
active transition to complete the write cycle.

ADDRESSING THE RAM
The eleven address pins on the device are time multiplexed
at the beginning of a mempry cycle by two clocks, row address
strobe (RA$) and column address strobe (CAS), into two separate 11-bit address fields. A total of twenty-two address bits,
eleven rows and eleven columns, will decode one of the
4,194,304 bit locations in the device. RAS active transition is
followed by CAS active transition (active = VIL, tRQlLminimum) for all read or write cycles. The delay between RAS and
CAS active transitions, referred to as the multiplex window,
gives a system designer flexibility in setting up the ex1ernal addresses into the RAM.
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the ex1ernal CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the 4M RAM:
RAS only refresh cycle, CAS before RAS refresh cycle,
and nibble mode. All three are discussed in separate sections that follow.
READ CYCLE
The DRAM may be read with four different cycles: "normal"
random read cycle, nibble mode read cycle, read-write cycle,
and nibble mode read-write cycle. The normal read cycle is
outlined here, while the other cycles are discussed in separate
sections.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (W) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent olthe address multiplex
window; however, CAS must be active before or at tRCD maximum to guarantee valid data out (Q) attRAC (access time from
RAS active transition). If the tRCD maximum is exceeded,
read access time is determined by the CAS clock active transition (tCACl.
_
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. Wmust remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data at that bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of

READ-WRITE CYCLE
A read-write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically a
late write cycle, as discussed in the .WRITE CYCLE section,
except Wmust remain high for tCWD minimum after the CAS
active transition, to guarantee valid Q before writing the bit.
NIBBLE MODE CYCLES
Nibble mode allows fast successive serial data operations
at two, three, orfour bits olthe 4M dynamic RAM. Read access
time in nibble mode (tNCAC) is considerably faster than the
regular RAS clock access time, tRAC. Nibble mode operation
consists of keeping RAS active while toggling CAS between
~and ~he address of the first nibble bij is latched by
RAS and CAS active transitions. Each subsequent CAS active transition increments the row and column addresses internally to access the next bit in binary fashion. After the fourth bit
is accessed, the nibble pattern repeats itself (0,0) (0,1) (1,0)
(1,1) (0,0) (0,1) (1 ,0) (1,1) .... TheA1 0 address determines the
starting point of the 4-bit nibble, with row address A10 the least
significant of the (column, row) ordered pair. External addresses are ignored after the first nibble bit is selected.

MOTOROLA MEMORY DATA
2-53

•

MCM54101A

A nibble mode cycle is initiated by a normal read, write, or
read-write cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to
inactive for minimum of tNCP, while RAS remains low (VILl.
The second CAS active transition while RAS is low initiates the
first nibble mode cycle (tNC ortNRWC). Either a read, write, or
read-write operation can be performed in a nibble mode cycle,
subject to the same conditions as in normal operation (previously described). These operations can be intermixed in
consecutive nibble mode cycles and performed in any order.
The maximum number of consecutive nibble mode cycles is
limited by tRAS' Nibble mode operation ends when RAS transitions to inactive, coincident with or following a CAS inactive
transition.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically
refreshed (recharged) to maintain the correct bit state. Bits in
the MCM541 01 A require refresh every 16 milliseconds.
This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM541 01 A. Burst refresh, a refresh of
all 1024 rows consecutively, must be performed every 16 milliseconds on the MCM541 01 A.
A normal read, write, or read-write operation to the RAM will
refresh all the bits (4096) associated with the particular row decoded. Three other methods of refresh, RAS-only refresh,
CAS before RAS refresh, and hidden refresh are available
on this device for greater system flexibility.
RAS-Only Refresh
RAS-only refresh consists of RAS transition to active,latching the row address to be refreshed, while CAS remains high
(VI H) throughout the cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.
CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order activates an internal refresh
counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh
cycle.

The output buffer remains at the same state it was in during
the previous cycle (hidden refresh). IN must be inactive for
time tWRP before and time !wRH after RAS active transition to
prevent switching the device into test mode.
Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive tRP and
back to active, starts the hidden refresh. This is essentially the
execution of a CAS before RAS refresh from a cycle in progress (see Figure 1). IN is subject to the same conditions with
respect to RAS active transition (to prevent test mode) as in
CAS before RAS refresh.
.
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter ofthis device can be tested with
a CAS before RAS refresh counter test. This test is performed with a read-write operation. During the test, the internal
refresh counter generates the row address, while the external
address supplies the column address. The entire array is refreshed after 1024 cycles, as indicated by the check data written in each row. See CAS before RAS refresh counter test
cycle timing diagram.
The test can be performed after a minimum of 8 CAS before
RAS initialization cycles. Test procedure:
.
1.
Write "O"s into all memory cells with normal write mode.
2.
Select a column address, read "0" out and write "1" into
the cell by performing the CAS before RAS refresh
counter test, read-write cycle. Repeat this operation
1024 times.
3.
Read the "1"s which were written in step 2 in normal read
mode,
4.
Using the same starting column a,ddress as in step 2,
read "1" out and write "0" into the cell by performing the
CAS before RAS refresh counter test," read-write
cycle. Repeat this operation 1024 times.
5.
Read "O"s which were written in step 4 in normal read
mode.
6.
Repeat steps 1 to 5 using complement data.

CAS BEFORE RAS
REFRESH CYCLE

Q -HIGH

Z-+---<

VALID DATA'()UT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA

2-54

CAS BEFORE RAS
REFRESH CYCLE

MCM54101A

TEST MODE

ternal test mode logic of the device. See the following truth
table and test mode block diagram.
IN, CAS before RAS timing puts the device in "Test Mode"
as shown in the test mode timing diagram. A CAS before RAS
or a RAS only refresh cycle puts the device back into normal
mode. Refresh is performed in test mode by using a W, CAS
before RAS refresh cycle which uses internal refresh address
counter.

The internal organization of this device (512K x 8) allows it
to be tested as if it were a 512K x 1 DRAM. Nineteen of the
twenty-two addresses are used when operating the device in
test mode. Row address Al0, and column addresses AO and
Al0 are ignored by the device in test mode. A test mode cycle
reads and/or writes data to a bit in each of eight 512K blocks
(BO-B7) in parallel. External data out is determined by the in-

TEST MODE TRUTH TABLE

0

BO

Bl

B2

B3

B4

B5

B6

B7

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

-

Q

Any Other

0

TEST MODE
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V CC = 5.0 V ±1 0%, T A = 0 to 70°C, Unless Otherwise Noted)
READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2, 3, and 4)
54101A~

Symbol

541 01 A-70

541 01 A-80

Std.

Alt.

Min

Max

Min

Max

Min

Random Read or Write Cycle Time

tRELREL

tRC

115

135

-

155

-

ns

5

Access Time from RAS

tRELQV

tRAC

-

-

-

85

ns

6,7

Access Time from CAS

teELQV

teAC

-

25

-

25

ns

6,8

tAA

-

35

-

40

-

25

tAVQV

45

ns

6,9

RAS Pulse Width

tRELREH

tRAS

65

10k

75

10k

10 k

ns

Parameter

Access Time from Column Address

65

-

75

85

RAS Hold Time

teELREH

tRSH

25

-

25

-

25

CAS Hold Time

tRELCEH

teSH

65

-

75

-

85

CAS Pulse Width

tCELCEH

teAS

25

10k

25

10k

25

Max

10k

Unit

Notes

ns
ns
ns

Column Address to RAS Lead Time
ns
40
45
35
tRAL
tAVREH
NOTES.
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 lIS is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range (O°C S TA S 70°C) is ensured.
6. Measured with a current load equivalent to 2 TIL (- 200 1lA, + 4 mAl loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD S tRCD (max).
8. Assumes that tRCD 2: tRCD (max).
9. Assumes that tRAD 2: tRAD (max).

MOTOROLA MEMORY DATA

2-56

•

MCM54101A

•

WRITE, CAS BEFORE RAS REFRESH CYCLE (TEST MODE ENTRY)
(0 and AD-Al0 are Don't Care)

14----------

IRC

---------~

CAS VIH -

VIL -

W

VIH -

VIL -~~~~~~~----------~~~~~~~~~~~~~~~~~~~~
Q (DATA OUT) VOH -

VOL

~_____________________ HIGH Z ______________________

------"1

MOTOROLA MEMORY DATA
2-56

MCM54101A

•

TEST MODE - READ CYCLE

_
VIH _
RAS
VIL -

--~

14---------

ADDRESSES VIH VIL -

W VIH VIL - '--'''-'''-''''""''''';-'''--'''--'''-'''-'''-'',

t
---------<1

-....:."'_"=--:.-:::.:l-toFF

'r - ' 1 - - - - - - - RAC --------j;:::::;:'i,...-___

v
Q (DATA OUT)

OL- - - - - - - - HIGHZ
VOH-

VALID DATA

TEST MODE - EARLY WRITE CYCLE
14-------------tRC-------------~

V IH -

RAS

--~

1---------tRAS---------*i

.J,:-------:i.

VIL 1 - - - - t RCD ----*"~-

ADDRESSES V IH V IL 14--t--t--- tCWL-----

W

1----tWCH

VIH -

~~~~-+---twP----~'

VIL-~~~~~~~~~~--r__r------------_1~~~~~~~~~"-'~
14--+----11--- t RWL-----~

D (DATA IN)

V IH VIL -

xxxxx~
t DS

VALID DATA

~

I------

~xxxxxxxxxx>

t DH

VOH Q(DATAOUn

HIGHZ - - - - - - - - - - - - - - - - - VOL -

MOTOROLA MEMORY DATA
2-67

MCM54101A

•

TEST MODE BLOCK DIAGRAM

ADDRESSES

~

~IA1_
512KBLOCK
BO

VCC

A

~r

I

~

TEST MODE

r-~ 512KBLOCK
:iBB
Bl
I

-......,

~_
~ 512KB2BLOCK Ic
C

ADi£-

H
~
I

512K :-OCK

ID

r0

~

DOUT

NORMAL

H

512K:OCKr

TEST MODE

r--

r-

.......

'--

ADDRESSES
BO Al OR, A1OC, A!Kt
B1 A1 OR, 81Ql!, AOC
B2 A1 OR, 81Ql!, AQQ
B3 A10R Al0C,AOC
B4812B. A1OC,AQQ
B5 A10R 81Ql!, AOC
B6 A10R 81Ql!, AQQ.
B7 Al0R, A1OC, AOC

~ 512K:OCK ~

~

f-

I:

~ 512KBLOCK
'B6'
r

TEST MODE

Y

H

II
r

512KBLOCK
B7
H

NORMAL

~

itt'-Hi!
---------lJ
ADDRESSES

MOTOROLA MEMORY DATA
2-68

1

MCM54101A

II

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory Prefix
Part Number

T

T11
x

XX XX

T

"'.... _IR'-T........', ..... _,
Speed (60 = 60 ns, 70 • 70 ns, 80 = 80 ns)
Package (N - 300-mil SOJ, Z - 100-mil Plastic ZIP)

Full Part Numbers- MCM54101AN60
MCM54101 AN70
MCM54101 AN80

MCM54101AN60R2
MCM54101 AN10R2
MCM54101 AN80R2

MOTOROLA MEMORY DATA
2-68

MCM54101AZ60
MCM54101AZ70
MCM54101AZ80

MOTOROLA

-

•

SEMICONDUCTOR

TECHNICAL DATA

MCM54102A

Advance Information
4M

x 1 CMOS Dynamic RAM

Static Column

NPACKAGE
300-MILSOJ
CASE 822

The MCM54102A is a 0.711 CMOS high-speed, dynamic random access
memory. It is organized as 4,194,304 one-bit words and fabricated with
CMOS silicon-gate process technology. Advanced circuit design and fine line
processing provide high performance, improved reliability, and low cost. The
static column mode feature allows Column data to be accessed upon the
column address transition when RAS and CS are held low, similar to static
RAM operation.
The MCM54102A requires only 11 address lines; row and column
address inputs are multiplexed. The device is packaged in standard 300-mil
J-Iead small outline package and a 100-mil zig-zag in-line package (ZIP).
Three-State Data Output
Static Column Mode
Test Mode
TIL-Compatible Inputs and Outputs
RAS Only Refresh
CS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh: MCM54102A = 16 ms
Fast Access Time (tRAC):
MCM54102A-60 = 60 ns (Max)
MCM54102A-70 = 70 ns (Max)
MCM54102A-80 = 80 ns (Max)
• Low Active Power Dissipation:
MCM54102A-60 = 660 mW (Max)
MCM54102A-70 = 550 mW (Max)
MCM54102A-80 = 468 mW (Max)
• Low Standby Power Dissipation:
MCM541 02A = 11 mW (Max, TIL Levels)
MCM541 02A = 5.5 mW (Max, CMOS Levels)

ZPACKAGE
PLASTIC
ZIG-ZAG IN-LINE
CASE 836
' "

•
•
•
•
•
•
•
•
•

PIN NAMES

ACl-A10 ......... Address Inpul
D ................. Data Inpul
Q ................ Data Ou1put
W .......... ReadlWrite Enable
RAS . . . . .. Row Address Strobe
CS ............... Chip Select
VCC ...... Power Supply (+ 5 V)
VSS .................. Ground
NC ............ No Connection

PIN ASSIGNMENT
100-MILZIP
~-

300-MILSOJ
o

1

"iii 2
RAS 3

26

PVSS

25pa
24

pes

NC4

23PNC

Al0 5

22

PAS
PAS
PA7
PA6

AO

9

18

AI

10

17

A2

11

16

A3

12

VCC

13

15 P A5
14 PA4

ThiS document contains Information on a new product Specifications and information herein are subject to change Without notice

MOTOROLA MEMORY DATA
2-60

AS ~~ ~2~ es
a

--

0

==

RAS

==

5

7

4

: : = Vss
6

--

"iii

8

== Al0
9
NC == 10
NC
11
AO == 12
13 -- AI
A2 ==
11 A3
15~
VCC
16
::: '"
A4
17
A5 : :
ll!. A6
19
A7
20

~A8

MCM54102A

BLOCK DIAGRAM

D

Q

COLUMN
DECODER

AO
AI
A2
A3
A4
AS
A6
A7
AS
AS

AIO ----...---,/1

L-"lI.=t'"'-I.J,.I.I-J-n-TlII

RAS------.j

Vee

Vss

ABSOLUTE MAXIMUM RATING (See Nole)
RaUng

Power Supply Voltage

Symbol

Value

Unit

V

VCC

-I to +7

Vin. Vout

-I to +7

V

Data Out Current

lout

50

mA

Power Dissipation

Po

700

mW

Operating Temperature Range

TA

o to +70

·C

Voltage Relative to VSS for Any Pin Except VCC

·C
-55to+15O
Tsta
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommendad voltages for extended
periods of time could affect device reliability.
Storage Temperature Range

MOTOROLA MEMORY DATA

2.:e1

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however.
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuil.

MCM54102A

•

DC OPERATING CONDITIONS ANDCHARACTERlsncs
(Vee m 5.0 V ±10%, TA - 0 to 700 e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDmONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

lYP

Max

Unit

Nolea

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0
6.5

V

1

0.8

V

1

Max

Unit

Notea

mA

2,3

Logic High Voltage, All Inputs

VIH

2.4

Logic Low Voltage, All Inputs

VII

-1.0

-

Symbol

Min

DC CHARACTERISTICS
CharacterlaUc
VCC Power Supply Current
MCM54102A·60, tRC 110 ns
MCM54102A·70, tRC = 130 ns
MCM54102A-80, tRC ~ 150 ns

ICCI

VCC Power Supply Current (Standby) (~ = CS - VIH)

ICC2

VCC Power Supply Current During RAS Only Refresh Cycles (CS = VIH)
MCM54102A-60, tRC = 110 ns
MCM54102A-70, tRC = 130 ns
MCM54102A-80, tRC -150 ns

ICC3

VCC Power Supply Current During Static Column Mode Cycle (~ MCM54;02A-60, tsc 35 ns
MCM54102A-70, tsc - 40 ns
MCM54102A-80, tsc = 45 ns

ICC4

=

=

CS - VII)

-

120
100
85
2.0

mA
mA

2,3

mA

2,3

120
100
85
85
75
65

VCC Power Supply Current (Standby) (~ = CS = VCc-O.2 V)

ICC5

VCC Power Supply Current During CS Before ~ Refresh Cycle
MCM54102A-60, tRC 110 ns
MCM54102A-70, tRC .130 ns
MCM54102A-80, tRC -150 ns

ICC6

Input Leakage Current (0 V :S Vin :S 6.5 V)

Ilka(l)

-10

10

Output Leakage Current (CS = VIH, 0 V:S Vout:S 5.5 V)

IlkalO)

-10

10

Output High Voltage (IOH = - 5 mAl

VOH

2.4

Output Low Voltage (lot = 4.2 mAl

VOL

-

0.4

V

Symbol

Max

Unit

Notes

Cin

5

pF

4

=

1.0

mA
mA

2

120
100

85

-

JIA
JIA
V

CAPACITANCE (f -1.0 MHz, TA = 25°C, VCC - 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

AO-Al0,D
RAS,CS,iN

7

pF
4
Q
Output Capacitance (CS = VIH to Disable Output)
7
Cout
NOTES.
1. All voltage referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
3. Column address can be changed once or less while RAS VIL and CS = VIH.
4. Capacitance measured wtth a Boonton Metar or effective cepacttance calculated from the equation: C • IAlltN.

=

MOTOROLA MEMORY DATA
2-82

MCM54102A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = a to 70oe, Unless Otherwise Noted)

READ. WRITE. AND READ-WRITE CYCLES (See Notes 1 2, 3, and 4)
Symbol
Parametar

54102A-60

54102A-70

Std.

Alt.

Min

Max

Min

Random Read or Write Cycle
Time

tRELREL

tRC

110

130

Read-Write Cycle Time

-

155

tRELREL

tRWC

135

Static Column Mode Cycle Time

tAVAV

tsc

35

Static Column Mode Read-Write
Cycle Time

tAVAV

tSRWC

60

Access Time from RAS

tRELQV

tRAC

tcELQV

tCAC

-

60

Access Time from CS
Access Time from Column Address

tAVQV

tAA

-

30

Access Time from Last Write

twLQV

tALW

-

55

20

Max

54102A-80
Min

Max

Unit

Notea

-

150

-

ns

5

-

175

-

ns

5

40

45

ns

70

-

80

-

-

70

-

20
35

65

ns

80

ns

6,7

20

ns

6,8

40

ns

6,9

75

ns

6,10

CS to Output in Low-Z

tCELQX

tcLZ

0

-

0

-

0

-

ns

6

Output Buffer and Tum-Off Delay

tcEHQZ

toFF

0

20

0

20

0

20

ns

11

Data Out Hold from Address
Change

tAXQX

tAOH

5

-

5

-

5

-

ns

Data Out Enable from Wrtte

twHQV

tow

-

20

-

20

twHQX

twOH

0

-

0

-

-

Data Out Hold from Write

IT

IT

3

50

3

RAS Precharge Time

tREHREL

tRP

40

-

RAS Pulse Width

tRELREH

tRAS

60

RAS Pulse Width (Static Column
Mode)

tRELREH

tRASC

RAS Hold Time

tCELREH
tRELCEH
tcELCEH

Transition Time (Rise and Fall)

cs Hold Time
CS Pulse Width

20

ns

0

-

ns

50

3

50

ns

50

-

60

-

ns

10k

70

10k

80

10k

ns

60

200k

70

200k

80

200k

ns

tRSH

20

80

-

ns

70

-

20

60

-

20

tcSH
tcs

20

10k

20

10k

20

10k

ns

200k

20

200 k

20

200k

ns

ns

CS Pulse Width (Static Column
Mode)

tcELCEH

tcsc

20

RAS to CS Delay Time

tRELCEL

tRCD

20

40

20

50

20

60

ns

12

RAS to Column Address Delay
Time

tRELAV

tRAD

15

30

15

35

15

40

ns

13

!cEHREL

!cRP

5

-

5

-

5

-

ns

CS to RAS Precharge Time

(continued)
NOTES:
1. VIH min and VIL max are reference levels for meaSuring timing of input signals. Transition times are measured between VIH and VIL'
2. An initial pause of 200 jlS is required aiter power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specnication applies for all input signals. In addition to meeting the transition rate specnication, all input Signals must
transition between VIH and VIL (or between VIL and VIH) In a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range (O°C ,; TA ,; 70°C) is ensured.
6. Measured wtth a current load equivalent to 2 TTL (- 200 IIA, + 4 mAl loads and 100 pF wtth the data output trip points set at VOH = 2.0
V and VOL = 0.8 V.
7. Assumes that tRCD ,; tRCD (max).
8. Assumes thatlRCD ~ tRCD (max).
9. Assumes that tRAD ~ tRAD (max).
10. Assumes that tLWAD ~ ILWAD (max).
11. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
12. Operation wtthin the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specnied tRCD (max) limit, then access time Is confrolled exclusively by tcAC'
13. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specnied tRAD (max), then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
2-63

•

MCM54102A

III

READ, WRITE, AND READ·WRITE CYCLES (Continued)
Symbol
Parameler
CS Precharge Time (Static
Column Mode)

54102A-60

54102A·70

54102A-80

SId.

All.

Min

Max

Min

Max

Min

Max

Unll

tCEHCEl

!cP

10

-

10

-

10

ns

0

-

10

-

ns

0

ns

90

-

40

-

ns

5

-

ns

.-

Row Address Setup Time

tAVREL

tASR

0

-

0

Row Address Hold Time

tRELAX

tRAH

10

10

Column Address Setup Time

tAVCEL

tASC

0

Column Address Hold Time

tCELAX

!cAH

15

Column Address Hold Time
Referenced to RAS
(Read Cycle)

tRELAX

tAR

70

-

Column Address to RAS Lead
Time

tAVREH

tRAL

30

Column Address Hold Time
Reference to RAS High

tREHAX

tAH

5

Write Command to CS Lead Time

0
15
80

15

Nola.

ns

ns
ns

twLCEH

!cWL

20

-

20

-

20

-

ns

Last Write to Column Address
Delay Time

twLAV

tLWAD

20

25

20

30

20

35

ns

Last Write to Column Address
Hold Time

twLAX

tAHLW

55

-

65

75

twHCEL

tRCS

0

-

0

Read Command Hold Time
Referenced to CS

tCEHWX

tRCH

0

0

0-

ns

16

Read Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

-

-

ns

Read Command Setup Time

-

0

-

ns

16

Write Command Hold Time
Referenced to CS

!cELWH

twCH

10

-

15

15

-

ns

Write Command Pulse Width

twLWH

twP

10

-

15

15

twHWL

twl

10

-

10

Write Command to RAS Lead
Time

twLREH

tRWL

20

-

20

Data in Setup Time

tDVCEL

tDS

0

Data in Hold Time

!cELDX

tDH

15

15

Refresh Period

tRVRV

tRFSH

-

-

-

ns

Write Command Inactive Time

-

16

ms

-

ns

18

20

ns

18

80

-

ns

18

40

-

ns

18

16

35
5

0

0

-

Write Command Setup Time

twLCEL

twcs

0

-

0

CS to Write Delay

!cELWL

!cWO

20

20

RAS to Write Delay

tRELWL

tRWD

60

Column Address to Write Delay
Time

tAVWL

tAWD

30

-

70
35

16

-

0

10
20
0
15

0

14

15

ns

ns
ns
ns

17

ns

17

(continued)
NOTES:
14. tAH must be met for a read cycle.
15. Operation within the tLWAD (max) limHensures thallALWcan be met.tLWAD (max) is specified as a reference point only; iftLWAD is greater
than the specified tLWAD (max) limit, then access time is controlled exclusively by tAA.
16. EHher tRRH or tRCH must be satisfied for a read cycle.
17. These parameters are referenced to CS leading edge in early write cycles and to Wleading edge in read-write cycles.
18. twcs, tRWD, !cWO, tAWD, and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if twcs ., twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout
the entire cycle; ntCWD ., tCWD (min), tRWD ., tRWD (min), tAWD ., tAWD (min), and !cPWD ., !cPWD (min) (page mode), the cycle is
a read-write cycle and the data out will contain data read from the selected cell. If neither oi these sets of conditions is satisfied, the condHion
of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
2-64

MCM54102A

READ, WRITE, AND READ-WRITE CYCLES (Concluded)
Symbol
Parameter

54102A-60

54102A·70

54102A-60

Std.

Alt.

Min

Max

Min

Max

Min

Max

UnH

CS Setup Time for CS Before
RAS Refresh

tRELCEL

!cSR

5

-

5

-

5

-

ns

CS Hold Time for CS Before
RAS Refresh

tRELCEH

!cHR

15

15

-

15

-

ns

RAS Precharge to CS Active
Time

tREHCEL

tRPC

0

0

-

ns

!cEHCEL

!cPT

30

40

-

ns

Write Command Setup Time
(Test Mode)

twLREL

twTs

10

10

-

0

CS Precharge Time for CS
Before RAS Counter Test

-

10

-

ns

Wrtte Command Hold Time
(Test Mode)

tRELWH

twTH

10

-

10

-

10

-

ns

Write to RAS Precharge Time
(CS Before RAS Refresh)

twHREL

twRP

10

-

10

10

-

ns

Wrtte to RAS Hold Time
(CS Before RAS Refresh)

tRELWL

twRH

10

-

10

-

10

-

ns

40

MOTOROLA MEMORY DATA
2-66

Notes

•

MCM54102A

..

READ CYCLE
~------------------------tRC----------------------~

1-0--------------- tRAS --------------""1

i"'1------ tRP ----""I

~------------------tCSH----------4_~--_r~

ADDRESSES VIH vIL-

~~------------_4--~ i"'1---------~--~-----""1 ~---------

W VIHVIL - t.....:>.'--"~~....::.L...u.....u....:.J....::i-.Y

Q (DATA OUT) VOH - ___________ HIGH Z --------1---{1
VOL-

VALID DATA OUT

EARLY WRITE CYCLE
~---------------------tRC------------------------~

--------------- tRAS---------------""I

WVIH-

...,.---+-+--------t'-'.....................-""-"--"-.. . . .,.,............

VIL - ...........................-""-""........,.,..................,.......

Q(DATAOUT) VOH- _ _ _ _ _ _ _ _ _ _ _ _ HIGHZ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
VOL -

MOTOROLA MEMORY DATA

MCM54102A

READ-WRITE CYCLE
t~c-----------~

tRAS

---------;~

iii VIHVIL - -'-~~~...:.t..~:.I....JI

Q(DATAOUT)

VQH-

VOL-

- - - - - HIGHZ----KI

STATIC COLUMN MODE READ CYCLE
~----------- ~C--------

tsc-~--

COLUMN
ADDRESS 1

COWMN
ADDRESS 2

iii VIHVIL - ~:....lL",",","+"""-"'-lI..->~

Q(DATAOUT)

VQH-

VOL-

VALID
DATA OUT

- - - - - HIGHZ-----{I

VALID DATA OUT

MOTOROLA MEMORY DATA
2-67

•

MCM54102A

..

STATIC COLUMN MODE ,EARLY WRITE CYCLE (A)

tASR
ADDRESSES VIH VIL -

Q(DATAOUT) VOH- _ _ _ _ _ _ _ _ _ _ _ _ HIGHZ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
VOL-

STATIC COLUMN MODE EARLY WRITE CYCLE (8)

tASR
ADDRESSES VIH VIL-

Q(DATAOUT)

VoH- _ _ _ _- - - - - - - -

HIGHZ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

VOL-

MOTOROLA MEMORY DATA
2-68

MCM54102A

STATIC COLUMN MODE READ-WRITE CYCLE

--"""""-

~--------------------- tMSC----------------~~ ~__~__~

ADDRESSES VVIH-

IL -

Q (DATA OUT) VVOH -

- - - - - HIGH Z - - - - - - t ( j

OL-

r--

READ·WRITE--*'>---

MOTOROLA MEMORY DATA
2-89

•

MCM54102A

•

STATIC COLUMN MODE READIWRrrE MIXED CYCLE

D(DATA IN) VVIH IL-

OH
Q(DATAOUT) V -

VOL -

--------+1-'..

~

HIGHZ--....,....--.(I
_ _..1::~~=..,.-tALW

-I-

EARLYWRITE

MOTOROLA MEMORY DATA

2·70

"..:;L..~'-"'-~ ~...;;;.;,;.;.;..;;..;;.;....,.--

READ-----<·~I...· - - READ-WRITE----I

MCM54102A

RAS ONLY REFRESH CYCLE
(Wand A10 are Don't Care)

~-------------------tRC------------------------~

Q(DATAOUn VOHVOL-

- - - - - - - - - - - - - - HIGHZ - - - - - - - - - - - - - -

CS BEFORE RAS REFRESH CYCLE
(AO to A10 are Don't Care)

~----------------tRC--------------~
~-------t~--------~

~----~

Jr----~

iii VIHVIL -

-"-"-"-1'--"--'"

Q (DATA oun VVOH OL- _ _ _ _ _

~

MOTOROLA MEMORY DATA
2-71

•

MCM54102A

...

HIDDEN REFRESH CYCLE (READ)

ADDRESSES VVIH IL -

iii VIHVIL - -"--"--"-"1-"--'11....-;,;'

Q(DATAOUT) VOHVOL-

----------1--<1
HIDDEN REFRESH CYCLE (EARLY WRITE)

cs VIHVIL -

ADDRESSES VVIH IL -

iii VIHVIL - '-lo~:...lI~~~~~_+-+_ _ _~~.::J

D(DATA IN) VIH VIL - /....::.I.~....:>I..~.::.I-~;;' 11"------......;. ,,~~....:>I.....:.t..~~~.:>I_.lL....~:.I....:"_l.:......:.~:...lI;..
Q (DATA OUT) VOH - _ _ _ _ _ _ _ _ _ _ _ _ HIGHZ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
VOL -

MOTOROLA MEMORY DATA

2-72

MCM54102A

•

CS BEFORE RAS REFRESH COUNTER TEST CYCLE

READ CYCLE
ADDRESSES VVIH -

IL - ......"--'......,'-"~--"--"-.......-"-"'--'''--''~

Q(DATAOUT) VOH VOL-

~_.,....,.._ _ _ _ _--:--:-_:-:---II

"-'"--'>1.-"-

----++---

EARLY WRITE CYCLE
ADDRESSES VVIH -

IL - -'-.................................-"-..................................................~

Q(DATAOUT) VOHVOL -

o(DATA IN)

----H--------+---H--

VIH -

.......+-"-""--,,,,--,,,_,,--,,-

VIL - -"'-......-"-""--~"'-"-'''--'''--'''--'''--''"'''''''"-J -'I:..-.....,....,.-_ _;:r "--lL.~,......
READ-WRITE CYCLE
ADDRESSES VVIH -

IL - ......"'-'''--'''-''i-r'--''--''--''--''-''"-''--''-''' ~-..,....,.---:----'r

o(DATA IN)

VIHVIL - ~~.:.t--"-:""';~"--l.,-",~~~-"-""--"'_~ ~_ _ _....,

MOTOROLA MEMORY DATA

2-73

v....,...........-"-""--"'-'''--'''-'''''-''-

MCM54102A

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the RAM. During an extended inactive
state (greater than 16 milliseconds with the device powered
up), a wakeup sequence of eight active cycles is necessary to
ensure proper operation.

WRITE CYCLE
The user can write to the DRAM with any offourcycles: early
write, late write, static column mode early write, and static column mode read-write. Early and late write modes are discussed here, while static column mode write operations are
covered in another section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of Wto active
(VIL). Early and late write modes are distinguished by the active transition of W, with respect to CS leading edge. Minimum
active time tRAS and tcs, and precharge time tRP apply to
write mode, as in the read mode.
An early write cycle is characterized by Wactive transition at
minimum time twcs before CS active transition. Column address set up and hold times (tASC, tCAH) , and data in (D) set
up and hold times (tD.fu..tDH) are referenced to CS in an early
write cycle. RAS and CS clocks must stay active for tRWL and
tCWL' respectively, after the start of the early write operation to
complete the cycle.
o remains in three-state condition throughout an early write
cycle because Wactive transition precedes or coincides with
CS active transition, keeping data-out buffers disabled. This
feature can be utilized on systems with a common I/O bus, provided all writes are performed with early write cycles, to prevent bus contention.
A late write cycle occurs when Wactive transition is made
after CS active transition. Wactive transition could be delayed
for almost 10 microseconds after CS active tranSition, (tRCD +
leWD + tRWL + 2tT) ::; tRAS, if other timing minimums (tRCD,
tRWL, and IT) are maintained. Column address and 0 timing
parameters are referenced to Wactive transition in a late write
cycle. Output buffers are enabled by CS active transition but 0
may be indeterminate-see note 18 of ac operating conditions
table. Parameters tRWL and tCWL also apply to late write
cycles.

ADDRESSING THE RAM
The eleven address pins on the device are time multiplexed
at the beginning of a memory cycle by the row address strobe
(RAS) clock, into two separate 11-bit address fields. A total of
twenty-two address bits, eleven rows and eleven columns, will
decode one of the 4,194,304 bit locations in the device. RAS
active transition latches the row address field. Column addresses are not latched, hence the "static column" designation of this device. Chip select (CS) active transition (active =
VIL, tRCD minimum) follows RAS on all read, write, or readwrite cycles and is independent of column address. The static
column feature allows greater flexibility in setting up the external column addresses into the RAM.
There are three other variations in addressing the 4M RAM:
RAS only refresh cycle. CS before RAS refresh cycle. and
Static Column mode. All three are discussed in separate
sections that follow.
READ CYCLE
The DRAM may be read with four different cycles: "normal"
random read cycle, static column mode read cycle, read-write
cycle, and static column mode read-write cycle. The normal
read cycle is outlined here, while the other cycles are discussed in separate sections.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS active transition latching the desired
row. The write (W) input level must be high (VIH), tRCS (minimum) before the CS active transition, to enable read mode. A
valid column address can be provided at any time (tRAD minimum), independent of the CS active transition.
Both the RAS and CS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent olthe address multiplex
window. However, CS must be active and column address
must be valid by tRCD and tRAD maximums, respectively, to
guarantee valid data out (0) at tRAC (access time from RAS
active transition). If either tRCD or tRAD maximum is exceeded, read access time is determined by the CS clock active
transition (tcAd and/or valid column address (tAA)'
The RAS and CS clocks must remain active for a minimum
time of tRAS and tcs respectively, to complete the read cycle.
The column address must remain valid for~H after RAS inactive transition to complete the read cycle. W must remain high
throughout the cycle, and for time tRRH or tRCH after RAS or
CS inactive transition, respectively, to maintain the data althat
bit location. Once RAS transitions to inactive, it must remain
inactive for a minimum time of tRP to precharge the internal
device circuitry for the next active cycle. 0 is valid, but not
latched, as long as the CS clock is active. When the CS clock
transitions to inactive, the output will switch to High Z (threestate).

READ-WRITE CYCLE
A read-write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically a
late write cycle, as discussed in the WRITE CYCLE section,
except Wmust remain high for tCWD and/or tAWD minimum,
to guarantee valid 0 before writing the bit.
STATIC COLUMN MODE CYCLES
Static column mode refers to multiple successive data operations performed at any or all 2048 column locations on the selected row of the 4M dynamic RAM during one RAS cycle.
Read access time of multiple operations (tAA or tCAC) is considerably faster than the regular RAS clock access time t8AQ:
Multiple operations can be performed simply by keeping RAS
active. CS may be toggled between active and inactive states
at any time within the RAS cycle.
Once the timing requirements for the initial read, write, or
read-write cycle are met and RAS remains low, the device is
ready for the next operation. Operations can be intermixed in
any order, at any column address, subject to normal operating
conditions previously described. Every write operation must
be clocked with either CS or W, as indicated in static column
mode early write cycle timing diagrams A and B. Column address and 0 timing parameters are referenced to the signal
clocking the write operation.

MOTOROLA MEMORY DATA
2-74

MCM54102A

CS must be toggled inactive (tcp) to perform a"read operation after an early write operation (to tum output on), as indIcated in static column mode readlwrlte mixed cycle timing
diagram. The maximum number of consecutive operations is
limited to tRASC. The cycle ends when RAS transitions to inactive.

The output buffer remains at the same state it was in during
the previous cycle (hidden refresh). Vii must be inactive for
timetwRP before and time twRH after RAS active transition to
prevent switching the device into test mode.

REFRESH CYCLES
The dynamic RAM design is based on capaCitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically
refreshed (recharged) to maintain the correct bit state. Bits in
the MCM541 02A require refresh every 16 milliseconds.
"
This is accomplished by cycling through the 1024 rowaddresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM54102A. Burst refresh, a refresh of
all 1024 rows consecutively, must be performed every 16 milliseconds on the MCM54102A.
A normal read, write, or read-write operation to the RAM will
refresh all the bijs (4096) associated with the particular row decoded. Three other methods of refresh, RA8-0nly refresh,
CS before RAS refresh, and hidden refresh are available on
this device for greater system flexibility.
RAS-Only Refresh
RAS-only refresh consists ofRAS transition to active,latching the row address to be refreshed, while CS remains high
(VIH) throughout the cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.
CS Before RAS Refresh
CS before RAS refresh is enabled by bringing CS active before RAS. This clock order activates an internal refresh counterthat generates the row address to be refreshed. External address lines are ignored during the automatic refresh cycle.

MEMORY CYCLE

Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintainingvalid dataatthe output pin. Holding CS active the end of
a read or write cycle, while RAS cycles inactive for tRP and
back to active, starts the hidden refresh. This is essentially the
execution of a CS before RAS refresh from a cycle in progress
(see Figure 1). Vii is subject to the same conditions with respect to RAS active transition (to prevent test mode cycle) as
in CS before RAS refresh.
CS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CS before RAS refresh counter test. This test is performed
with a read-write operation. During the test, the internal refresh
counter generates the row address, while the external address
supplies the column address. The entire array is refreshed after 1024 cycles, as indicated by the check data written in each
row. See CS before RAS refresh counter test cycle timing
diagram.
The test can be performed after a minimum of 8 CS before
RAS initialization cycles. Test procedure:
1.
Write ·O"s into all memory cells with normal write mode.
2.
Select a column address, read "0" out and write "1" into
the cell by performing the CS before RAS refresh
counter test, read-write cycle. Repeat this operation
1024 times.
3.
Read the "l"s which were written in step 2 in normal read
mode.
4.
Using the same starting column address as in step 2,
read "1" out and write "0" into the cell by performing the
CS before RAS refresh counter test, read-write
cycle. Repeat this operation 1024 times.
5.
Read ''0'' which were written in step 4 in normal read
mode.
6.
Repeat steps 1 to 5 using complement data.

CS BEFORE RAS

REFRESH CYCLE

r

CS BEFORE RAS

REFRESH CYCLE

r'
/

Q

-HIGHZ

/
\.

VALID DATA OUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA
2-75

-

-

•

MCM54102A

..

TEST MODE

internal test mode logic of the device. See fqllowing truth table
and test mode block diagram.
W, before RAS timing puts the device in "Test Mode",
as shown in the test mode timing diagram. A "CS before
RAS" refresh cycle or a "RAS only" refresh cycle puts the device back in normal mode. Refresh is performed in test mode
by using a "W, CS before RAS" refresh cycle which uses the
internal refresh address counter.

The internal organization of this device (512 x 8) allows it to
be tested as if it were a 512K x 1 DRAM. Nineteen of the
twenty-two addresses are used when operating the device in
test mode. Row address A 10, and column addresses AO and
A 10 are ignored by the device in test mode. A test mode cycle
reads and/or writes data to a bit in each of eight 512K blocks
(B0-87) in parallel. External data out is determined by the

es

TEST MODE TRUTH TABLE

D

eo

B1

B2

B3

B4

B5

B6

B7

Q

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

-

1

Any Other

0

TEST MODE
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, T A = 0 to 70 c e, Unless Otherwise Noted)
READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2. 3, and 4)
Symbol
Parameter
Random Read or Write Cycle
lime
Static Column Mode Cycle lime

54102A-60

Std.

Alt.

Min

tRELREL

tRC

115

40

tAVAV

tsc

Access lime from RAS

tRELOV

tRAC

Access lime from CS

leELOV

leAC

tAVOV

tAA

Access lime from Column
Address
RAS Pulse Width
RAS Pulse Width (Static Column
Mode)

-

Max

-

54102A-70
Min
135
45

35

-

65
25

Max

-

Unit

Notes

155

-

ns

5

50

-

ns

85

ns

25

ns

6,8

45

ns

6,9

40

-

75
25

Max

tRELREH

tRAS

65

10k

75

10k

85

10 k

ns

.tRELREH

tRASC

65

200k

75

200k

85

200k

ns

85

-

10k

25

10k

ns

200k

25

200k

ns

RAS Hold lime

leELREH

tRSH

25

-

25

CS Hold lime

tRELCEH

leSH

65

-

75

-

CS Pulse Width

leELCEH

les

25

10k

25

CS Pulse Width (Static Column

leELCEH

lesc

25

200k

25

Mode)

54102A-60
Min

-

-

25

-

6,7

ns
ns

Column Address to RAS Lead
35
40
45
ns
tAVREH
tRAL
lime
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 J1S is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification. all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (O°C S TA S
70°C) is ensured.
6. Measured with a current load equivalent to 2 TTL (- 200!iA, + 4 mAl loads and 100 pF with the data output trip points set at VOH = 2.0
V and VOL = 0.8 V.
7. Assumes that tRCD s tRCD (max).
8. Assumes thattRCD 2: tRCD (max).
9. Assumes thattRAD 2: tRAD (max).

MOTOROLA MEMORY DATA

2-76

MCM54102A

'II, CS BEFORE RAS REFRESH CYCLE (TEST MODE ENTRY)
(0 and AO-A10 are Don't Care)
~--------tRC--------~
------i-.j

tRAS

VQH-

Q (DATA OUT) V

OL-

J..:------:L

J_

tOFF
- _ _ _ _ _ _ _ _ __

HIGHZ - - - - - - - - - -

TEST MODE - READ CYCLE
~------------- tRC-----------~
i--------tRAS
~--- tRP --.-..,
--:!l
1~------,.

--------1

RAS VIHVIL-

~---------t~H-----4-~-4-~

tRAL----.J

COLUMN
ADDRESS

ADDRESSES VVIH IL-

-~~~------~~ ~----~S-~--~ ~-----

iii VIHVIL - L....l'--lo"-"'-T'-"......-""'--"-~...,
~------tMc;--t--;~~
Q (DATA OUT)

VQH-

VOL-

- - - - - - HIGHZ

----......,--{I

MOTOROLA MEMORY DATA

2-77

__________~
VALID DATA OUT

•

MCM54102A

•

TEST MODE - EARLY WRITE CYCLE
~----------------------IRC----------------------~

---------------~,--------------~

WVIHVIt - '-".......--"--"--"-.¥-.¥...,;"-".......-"--"-1"-.......,H-----------'p'--"'.......................-"-....."--'''--''<....>

~~

'....., ~~-XXXXXXXXXXXXX ...."':1xxxxxxxxxxxxxx
Q(DATAOUT) VQH- _ _ _ _ _ _ _ _ _ _ _ _ _ HIGHZ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
VOL -

TEST MODE - STATIC COLUMN MODE READ CYCLE
~-------------------I~----------~----~

tsc---*-COLUMN
ADDRESS 1

COLUMN
ADDRESS 2

WVIHVIL-L...,.lj:....¥.~~~~.:.....:¥~

Q(DATAOUT)

VQHVQL-

VALID
DATAOUT

- - - - - HIGHZ----{I

VALID DATA OUT

MOTOROLA MEMORY DATA

2-78

MCM54102A

TEST MODE - STATIC COLUMN MODE EARLY WRITE CYCLE (A)

tASR
ADDRESSES VV IH IL-

D(DATA IN)

~IH
IL -......,........"-"'......l.4--'L-"'""->J fo-----'r

Q(DATAOUn VOH- - - - - - - - - - - - - HIGHZ - - - . , . - - - - - - - - - - - - - - -

VQL-

TEST MODE - STATIC COLUMN MODE EARLY WRITE CYCLE (8)

tASR
ADDRESSES VVIH IL -

D(DATA IN)

~IH

IL -~'-"'~~~...::..I.."'::'/ J I - - - - - ' I

Q(DATAOUn VOH- - - - - - - - - - - - - HIGHZ - - - - - - - - - - - - - - - VOL-

MOTOROLA MEMORY DATA
2-79

•

MCM&4102A

..

TEST MODE BLOCK DIAGRAM

ADDRESSES
~

~ 512KBLOCK lAIA
BO

r-

VCC

~~

I

R:l

TEST MODE

1B
512K LOCK IB

t-

512K:iOCK lc
Ie

H

r-J

~

ADDRESSES
0----

~
~
NORMAL

I

10

~ 512K:.i0CK

10
DOUT

H

512K:!-OCKr

I

TEST MODE

;-r-

'--

~

'-- H

ADDRESSES
BO Al OR, A1OC, AllC
Bl Al OR'I:AOC
B2 Al OR,
AllC
R 1 ,AOC
~~ A1OC, AOC

t-

H512K:iOCKr

IG

512KBLOCK ]G
B6
I

TESTMODE

q

I

1H
512KBLOCK [_
B7
H

iil t

B5~~,AllC

~~mt.~

MOTOROLA MEMORY DATA
2-80

NORMAL

'--J

MCM54102A

ORDERING INFORMATION
(Order by Full Part Number)

T....I~

Motorola Memory Prefix _ _ _
Part Number

J 11
x

XX XX

T

"'__ I"'_T.... _, . . . _...~
Speed (60 = 60 ns, 70 = 70 ns, 80 = 80 ns)

-

Package (N = aOD-mii SOJ, Z • 100-mil Plastic ZIP)

Full Part Numbers- MCM54102AN60
MCM54102AN70
MCM54102ANBO
MCM54102AN10

MCM54102AN60R2
MCM54102AN70R2
MCM54102AN80R2
MCM541 02AN1 OR2

MCM54102AZ60
MCM54102AZ70
MCM54102AZ80
MCM54102AZ10

MOTOROLA MEMORY DATA
2-81

•

MOTOROLA

-

•

SEMICONDUCTOR

TECHNICAL DATA

Product Preview
256K x 16 CMOS Dynamic RAM
Fast Page Mode - 1 CAS, 2 Write Enables
The MCM54170B is a 0.611 CMOS high-speed, dynamic random access memory. It
is organized as 262,144 sixteen-bit words and fabricated with CMOS silicon-gate process technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low cost.
The MCM54170B requires only 10 address lines; row and column address inputs
are multiplexed. The device is packaged in a standard 400-mil SOJ plastic package,
a 100-mil zig-zag in-line package (ZIP), and a 400-mil thin-small-ou!line-package
(TSOP).
•
•
•
•
•
•
•
•

•

•

•
•
•

Three-State Data Output
Fast Page Mode
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
Self Refresh (MCM5V4170B only)
1024 Cycle Refresh:
MCM54170B = 16 ms
MCM5L4170B and MCM5V4170B = 128 ms
Fast Access Time (tRAC)
MCM54170B-70, MCM5L4170B-70, and MCM5V4170B-70 = 70 ns (Max)
MCM54170B-80, MCM5L4170B-80, and MCM5V4170B-80 = 80 ns (Max)
MCM54170B-l0, MCM5L4170B-l0, and MCM5V4170B-l0 = 100 ns (Max)
Low Active Power Dissipation:
MCM54170B-70, MCM5L4170B-70, and MCM5V4170B-70 = 385 mW (Max)
MCM54170B-80, MCM5L4170B-80, and MCM5V4170B-80 = 330 mW (Max)
MCM54170B-l0, MCM5L4170B-l0, and MCM5V4170B-l0 = 303 mW (Max)
Low Standby Power Dissipation:
MCM54170B, MCM5L4170B, and MCM5V4170B = 5.5 mW (Max, TTL Levels)
Battery Backup Power Dissipation:
MCM5L4170B = 1.7 mW (Max, battery backup mode, tRC =125/1s)
Self Refresh Power Dissipation:
MCM5V4170B = 1.1 mW (Max, self refresh mode)

This document contains Information on a new product. Specifications and information herein are subject to Change without notice.

MOTOROLA MEMORY DATA

MCM54170B
MCM5L4170B
MCM5V4170B

MCM54170B-MCM5L4170B-MCM5V4170B

PIN ASSIGNMENTS - MCM54170B

DQ8

l.

..

001 0 3
Vss 5

Vee

1

40

Vss

oao

2

39

0015

001

3

38

0014

0Q2

4

37

0013

DQ3

5

VCC 11
DQ3

VCC

6

36P 0012
35P Vss

DQ4

7

34p 0011

005

8

DQ6

9

007

10

NC

11

P0010
32P DQ9
31 PDQ8
lOP NC
33

IW

12

29 p

UW

13

RAS

14

ABR

15

MJ

16

Al

17

A2

18

PCAS
27P G
26P ABR
25 PA7
24 PA6
23P AS

A3

19

22p A4

VCC

20

21

NC

28

PVss

256K X 16 DRAM
4O-Pln 4OO·mll SOJ

..

..

001 3 7
001 5 9

..

001

DQ4

..
13

DQ9

VCC 1

.1

0011

000 2

44P VSS
43P 0015

.~

0012

001 3

42

P0014

~

0014

002 4

41

P0013

DQ3

40P 0012

.~

.

~~

VSS

J~

000

.. Jt
15
..
17 J~
..
J'1

.. :9.
.. ~
UW 23
..
25 Ji
A9R ..
27 .~
Al ..
29 ~
A3 ..
30
31 ..
VsS ..
006 19

NC 21

..
35
..

AS 33

A7

..
..

G 37

NC 39

0Q2

Vee
DQ5

5

39

DQ4 7

38

0011

DQ5 8

37

0010

36

DQ9

007 10

DQ6

35

DQ8

NC I 13
IW I 14

32

UW 1 15

9

007

IW
RAS
MJ
A2

VCC

32

A4

J1

AS

~~ ABR
J~ CAS
~ NC

256K X 16 DRAM
4O-Pln 475-mll ZIP

30

NC
NC
CAS

RAS 1 16

29

G

A9R I 17

28[J

ABR
A7

18

27

A1

19

26

AS

A2 120

25

AS

A3 1 21

24

A4

VCC 122

23

Vss

256K X 16 DRAM
4OI44-Pln 400-mll TSOP

VCC ....... Power Supply (+ 5 V)
VSS ................... Ground
NC . . . . . . . . . . . . . . No Connection
G . . . . . . . . . . . . . . .. Output Enable

MOTOROLA MEMORY DATA
2-83

31

MJ

PIN NAMES

AG-A7, ABR, A9R .. Address Input
DOO-DQ15 .•.• Data InpuVOutput
LW, UW .•..... ReadlWrite Enable
RAS ........ Row Address Strobe
CAS . . . .. Column Address Strobe

Vss

VCC 6

•

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

II

Product Preview
256K x 18 CMOS Dynamic RAM
Fast Page Mode - 1 CAS, 2 Write Enables
The MCM54190B is a 0.6).1 CMOS high-speed, dynamic random access memory. It
is organized as 262,144 eighteen-bit words and fabricated with CMOS silicon-gate
process technology. Advanced circuit design and fine line processing provide high
performance, improved reliability, and low cost.
The MCM54190B requires only 10 address lines; row and column address inputs
are multiplexed. The device is packaged in a standard 400-mil SOJ plastic package,
a 100-mil zig-zag in-line package (ZIP), and a 400-mil thln-small-outline-package
(TSOP).
•
•
•
•
•
•
•
•

•

•

•
•
•

Three-State Data Output
Fast Page Mode
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
Self Refresh (MCM5V4190B only)
1024 Cycle Refresh:
MCM54190B = 16 ms
MCM5L4190B and MCM5V4190B = 128 ms
Fast Access lime (tRAC)
MCM54190B -70, MCM5L4190B -70, and MCM5V4190B -70 = 70 ns (Max)
MCM54190B - 80, MCM5L4190B - 80, and MCM5V4190B - 80 = 80 ns (Max)
MCM54190B-l0, MCM5L4190B-l0, and MCM5V4190B-l0 = 100 ns (Max)
Low Active Power Dissipation:
MCM54190B -70, MCM5L4190B -70, and MCM5V4190B -70 = 385 mW (Max)
MCM54190B - 80, MCM5L4190B - 80, and MCM5V4190B - 80 = 330 mW (Max)
MCM54190B-l0, MCM5L4190B-l0, and MCM5V4190B-l0 = 303 mW (Max)
Low Standby Power Dissipation:
MCM54190B, MCM5L4190B, and MCM5V4190B = 5.5 mW (Max, TTL Levels)
Battery Backup Power Dissipation:
MCM5L4190B = 1.7 mW (Max, battery backup mode, tRC =125J.lS)
Self Refresh Power Dissipation:
MCM5V4190B = 1.1 mW (Max, self refresh mode)

This document contains information on a new produd. Spec/flcations and Information herein are subject to change without notice.

MOTOROLA MEMORY DATA
2-84

MCM54190B
MCM5L4190B
MCM5V4190B

MCM54190B-MCM5L4190B-MCM5V4190B

PIN ASSIGNMENTS - MCM54190B

0010 1

.~

0011

VCC

.i

0013

0015 7

.~

0014

.~

D02

0017 9

0016

0012

Vcc

1

DQO

2

DO 1

3

DO2

4

DO3

5

40P VSS
P0017
38 P0016
37 P0015
36 P0014

Vcc

6

35

004

7

34

0013

003 15

DO5

8

33

0012

004 17

DO6

9

32

0011

006 19

DO7

10

31

0010

001111

11

30

D09

IW

12

29

NC

uw

13

28

CAS

RAS

14

27

ABR

15

26

PG
PABR

AD

16

25

A7

39

h VSS

VSS 5

..

VCC
DOl

11
13

VSS

~~

000

~i

002

~~

VCC

J~

OOS

44

VSS

000

43

0017

001

42

0016

41

0015

4

000

40

0014

Vee

39

VSS

DQ4 7

38

0013

005

37

0012

D06

36

0011

007 10

35

0010

:~

007

~

IW

:i

RAS

ooBI

13

ABR 25

32

0Q9

AO

14

31

NC

27

:~

IW

28

A2.

OOB

21

UW 23

Al

I>J 29
VSS

31

Al

17

24

A6

AS 33

A2.

18

23

AS

A7 35

I>J

19

22

A4

VCC

20

21

VSS

256K X 18 DRAM
40-Pln 400-mil SOJ

10

1

G

37

NC 39

30

VCC

32

A4

UW

15

30

CAS

RAS

16

29

G

A9R

17

28

A8R

AO

18

27

A7

Al

19

26

A6

AS

,iii

A6

36

ABR

A2.

20

25

,iI~

CAS

I>J

21

24

A4

~!J.

009

VCC

22

23

Vss

256K X 18 DRAM
4O·Pin 475·mll ZIP

256K X 18 DRAM
40/44-Pln 400-mll TSOP

PIN NAMES
AD-A7, ABR, A9R .. Address Input
DoD-Do17 .... Data Input/Output
LW, UW ....... ReadIWrite Enable
RAS . . . . . . .. Row Address Strobe
CAS. . . .. Column Address Strobe

VCC ....... Power Supply (+ 5 V)
VSS ................... Ground
NC .. .. .. .. .. .... No Connection
G................ Output Enable

MOTOROLA MEMORY DATA
2-86

•

MOTOROLA

-

SEMICONDUCTOR

..

TECHNICAL DATA

Product Preview
256K x 16 CMOS Dynamic RAM
Fast Page Mode - 2 CAS, 1 Write Enable
The MCM54260B is a 0.6J.l CMOS high-speed, dynamic random access memory. It
is organized as 262,144 sixteen-bit words and fabricated with CMOS silicon-gate process technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low cost.
The MCM54260B requires only 9 address lines; row and column address inputs
are multiplexed. The device is packaged in a standard 400-mil SOJ plastic package,
a 100-mil zig-zag in-line package (ZIP), and a 400-mil thin-small-outline-package
(TSOP).
•
•
•
•
•
•
•
•

•

•

•
•
•

Three-State Data Output
Fast Page Mode
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
Self Refresh (MCM5V4260B only)
512 Cycle Refresh:
MCM54260B = 8 ms
MCM5L4260B and MCM5V4260B = 64 ms
Fast Access Time (tRAC)
MCM54260B -70, MCM5L4260B -70, and MCM5V4260B -70 = 70 ns (Max)
MCM54260B - 80, MCM5L4260B - 80, and MCM5V4260B - 80 = 80 ns (Max)
MCM54260B-10, MCM5L4260B-10, and MCM5V4260B-10 = 100 ns (Max)
Low Active Power Dissipation:
MCM54260B -70, MCM5L4260B -70, and MCM5V4260B -70 = 550 mW (Max)
MCM54260B - 80, MCM5L4260B - 80, and MCM5V4260B - 80 = 468 mW (Max)
MCM54260B -10, MCM5L4260B -1 0, and MCM5V4260B -1 0 = 413 mW (Max)
Low Standby Power Dissipation:
MCM54260B, MCM5L4260B, and MCM5V4260B = 5.5 mW (Max, TTL Levels)
Battery Backup Power Dissipation:
MCM5L4260B = 1.7 mW (Max, battery backup mode, tRC =125 J.lS)
Self Refresh Power Dissipation:
MCM5V4260B = 1.1 mW (Max, self refresh mode)

this document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
2-86

MCM54260B
MCM5L4260B
MCM5V4260B

MCM54260B-MCM5L4260B-MCM5V4260B

PIN ASSIGNMENTS - MCM54260B

D08 1

..

D010 3
VCC

VSS

DOO

D015

D01

D014

D013 7

DQ2

D013

D015 9

D03

D012

VCC

VCC

VSS

D01

VSS 5

11
13

DQ4

D011

D03 15

DOS

D010

DQ4 17

D06

D09

DQ6 19

D07

D08

NC 21

NC

NC

NC

LCAS

W

UCAS

UW 23

.~
10

VSS

D011

DOO [ 2

43

DOtS

D012

D01

r3

42

D014

D014

D02 [ 4

41

D013

D03

5

40

DQ12

VCC

6

39

VSS

DQ4

7

38

D011

DOS

8

37

D010

D06

9

36

D09

D07

10

35

D08

NC

13

32 ~ NC

NC

14

31 ~ LCAS

15

30 ~ UCAS

RAS

16

29

NC

17

28

AO

18

27
26

VSS

~~

DOO

~i

D02

~~

VCC

JIJ.

DOS

~~

DQ7

~~

NC
RAS

27

~~

AO

28

A2

30

VCC

NC

A8

A3

AO

A7

VSS

A1

A6

AS

33

A2

AS

A7

35

DE

37

LCAS

39

256K X 16 DRAM
40-Pin 400-mU SOJ

.~

44

~i

A1

VCC

.i

VCC [ 1

25

G

A4

DQ9

NC

RAS

A3

.~

29
31

32

A4

W

Ji

A6

A1

19

36

A8

A2

20

25

JIJ.

UCAS

A3

21

24

:~

NC

VCC

22

23

256K X 16 DRAM
40-Pin 475-mil ZIP

VCC .......... Power Supply (+ 5 V)
VSS ... : ................... Ground
NC .. .. . . . . . . . . . . . .. No Connection

G ................... Output Enable

MOTOROLA MEMORY DATA
2..f!l

~ A8

PA7
PA6
PAS
~ A4
~ VSS

256K X 16 DRAM
40/44-Pin 400-mU TSOP

PIN NAMES
AD-AS ............... Address Input
DQD-DQ15 . . . . . .. Data Input/Output
W .............. ReadlWrite Enable
RAS .. . . . . . . . .. Row Address Strobe
LCAS,UCAS . Column Address Strobe

PG

•

MOTOROLA

-

D

SEMICONDUCTOR

TECHNICAL DATA

Product Preview
256K x 18 CMOS Dynamic RAM
Fast Page Mode - 2 CAS, 1 Write Enable
The MCM54280B is a 0.611 CMOS high-speed, dynamic random access memory. It
is organized as 262,144 eighteen-bit words and fabricated with CMOS silicon-gate
process technology. Advanced circuit design and fine line processing provide high
performance, improved reliability, and low cost.
The MCM54280B requires only 9 address lines; row and column address inputs
are multiplexed. The device is packaged in a standard 400-mil SOJ plastic package,
a 100-mil zig-zag in-line package (ZIP), and a 400-mil thin-small-outline-package
(TSOP).
•
•
•
•
•
•
•
•

•

•

•
•
•

Three-State Data Output
Fast Page Mode
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
Self Refresh (MCMSV4280B only)
S12 Cycle Refresh:
MCMS4280B = 8 ms
MCMSL4280B and MCMSV4280B = 64 ms
Fast Access TIme (tRAC)
MCMS4280B -70, MCMSL4280B -70, and MCMSV4280B -70 = 70 ns (Max)
MCMS4280B - 80, MCMSL4280B - 80, and MCMSV4280B - 80 = 80 ns (Max)
MCMS4280B-l0, MCMSL4280B -10, and MCMSV4280B-l0 = 100 ns (Max)
Low Active Power Dissipation:
MCMS4280B -70, MCMSL4280B -70, and MCMSV4280B -70 = SSO mW (Max)
MCMS4280B - 80, MCMSL4280B - 80, and MCMSV4280B - 80 = 468 mW (Max)
MCMS4280B-l0, MCMSL4280B-l0, and MCMSV4280B-l0 =413 mW (Max)
Low Standby Power Dissipation:
MCMS4280B, MCMSL4280B, and MCMSV4280B = S.S mW (Max, TTL Levels)
Battery Backup Power Dissipation:
MCMSL4280B = 1.7 mW (Max, battery backup mode, tRC =12S 115)
Self Refresh Power Dissipation:
MCMSV4280B = 1.1 mW (Max, self refresh mode)

This document contaIns information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
2-88

MCM54280B
MCM5L4280B
MCM5V4280B

MCM54280B-MCM5L4280B-MCM5V4280B

PIN ASSIGNMENTS -- MCM54280B

0010 1

4O~
~

.~

0011

VCC 1

44

VSS

Vss 5

.i

0013

DOO

43

0017

.~

001

3

42

0016

0015 7

0014

.~

002 4

41

0015

0017

0016

10

VSS

003

40

0014

VCC

39

VSS

DQ4 7

38

0013

0012

VCC

1

000

2

39

001

3

38~ 0016

002

4

37

~

0015

~

0014

VCC

VSS
0017

11

DQ3

5

36

VCC

6

35

VSS

001

13

J~

DOO

DQ4

7

34

0013

003 15

Ji

002

005

8

33

0012

004 17

~~

VCC

006

9

32

0011

006 19

J~

005

007

DOB 21

:0..

007
NC
RAS

10

31

0010

DQB[ 11

30

DQ9

12

29

LCAS

NC

iii

23

:~

NC

25

:i

Al

27

iii

13

28

UCAS

RAS

14

27

G

NC

15

26

AS

AO

16

25

A7

Al

17

24

A6

AS 33

A2

18

23

AS

A7 35

A3[ 19

22

A4

37

21

VSS

vCC r

20

256K X 18 DRAM
40-Pin 400-mil SOJ

A3 29
VSS

G

DOS 9

36

0011

007 10

35

DOlO

DQ9

13
NC

14

LCAS

iii

15

UCAS

RAS

16

G

NC

17

A8

AO

18

,}i A6

Al

19

26

A6

38

AS

A2

20

25

AS

.~

OCAS

A3

21

24

A4

jQ.

DQ9

VCC

22

23

Vss

:~

AO

28

A2

30

Vee

31

LCAS 39

0012

005

32

A4

256K X 18 DRAM
40-Pin 475-mil ZIP

256K X 18 DRAM
40/44-Pin 400-mll TSOP

PIN NAMES

AO--AB . . . . . . . . . . . . . .. Address Input
OOD--0017 ....... Data InpuVOu1put
W ............... ReadlWrite Enable
RAS . . . . . . . . . .. Row Address Strobe
LCAS, UCAS Column Address Strobe

VCC ........ Power Supply (+ 5 V)
VSS ...................... Ground
NC . . . . . . . . . . . . . . .. No Connection
G .................. Ou1put Enable

MOTOROLA MEMORY DATA
2-89

A7

•

MOTOROLA

-

•

SEMICONDUCTOR

TECHNICAL DATA

MCM54400A
MCM5L4400A

Advance Information
1M x 4 CMOS Dynamic RAM
Fast Page Mode
The MCM54400A is a 0.711 CMOS high-speed, dynamic random access memory. It
is organized as 1,048,576 four-bit words and fabricated with CMOS silicon-gate process technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low cost.
The MCM54400A requires only 10 address lines; row and column address inputs
are multiplexed. The device is packaged in a standard 300 J-Iead small outline package, and a 100-mil zig-zag in-line package (ZIP).

NPACKAGE

30D-MILSOJ
CASE 822

ZPACKAGE
PLASTIC
ZIG-ZAG IN-LINE
CASE 836

Three-State Data Output
Fast Page Mode
Test Mode
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh: MCM54400A = 16 ms
MCM5L4400A = 128 ms
• Fast Access Time (tRAC)
MCM54400A-60 and MCM5L4400A-60 = 60 ns (Max)
MCM54400A-70 and MCM5L4400A-70 = 70 ns (Max)
MCM54400A-80 and MCM5L4400A-80 = 80 ns (Max)
• Low Active Power Dissipation:
MCM54400A-60 and MCM5L4400A-60 = 660 mW (Max)
MCM54400A-70 and MCM5L4400A-70 = 550 mW (Max)
MCM54400A-80 and MCM5L4400A-80 = 468 mW (Max)
• Low Standby Power Dissipation:
MCM54400A and MCM5L4400A = 11 mW (Max, TTL Levels)
MCM54400A = 5.5 mW (Max, CMOS Levels)
MCM5L4400A = 1.1 mW (Max, CMOS Levels)

•
•
•
•
•
•
•
•

PIN NAMES

AO-AS ............... Address Input
DOO-D03 ....... Data InpuVOutput
G .................. Output Enable
W . . . . .. . .. . .. .. ReadlWrite Enable
RAS ........... Row Address Strobe
CAS ........ Column Address Strobe
VCC .......... Power Supply (+ 5 V)
VSS ...................... Ground

PIN ASSIGNMENT
100-MILZIP

_r"jr300-MILSOJ

DOO

1

26

VSS
D03

2

25

3

24

D02

RAS( 4

23

DCAS

A9( 5

22

~G

AO ( 9

18 PA8

I

17 PA7

D01

-W

A1

10

A21 11

16

A3 [ 12

15

VCC ( 13

~ A6

~ A5

14 PA4

G • • •2.
CAS
3
D02
4
D03
5
VSS
6
DOO
7
D01
8
W
9
RAS
l~ A9
11
AO
12
A1
13

..
.. ..
.. ..
..

.. ..

A2

.. l'l
.. ..

VCC l5. 16
17
A5

ll!-

19
A7 •• 20

2-90

A4
A6

~...!!..A8

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA

A3

MCM~A·MCM5~A

BLOCK DIAGRAM

w--------....qr--...,
C A S - - - - -....

I---+-G

AO
A1
A2
A3
A4
A5
A6

A7
AS
A9

R A S - - - - -....

ABSOLUTE MAXIMUM RATING (See Note)
Rating
Power Supply Voltage

Symbol

Value

Unit
V

VCC

-1 to +7

Vin. Vout

-1 to +7

V

Data Out Current

lout

50

mA

Voltage Relative to VSS for Any Pin Except VCC
Power Dissipation

PD

700

mW

Operating Temperature Range

TA

o to +70

Storage Temperature Range

Tsta

-55to+150

°c
°c

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

MOTOROLA MEMORY DATA
2-91

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however. it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high-impedance
circuit.

•

MCM~A·MCM5~A

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.0

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

-

S.5

V

1

Logic Low Voltage, All Inputs

VIL

-1.0

-

0.8

V

1

Min

Max

Unit

Notes

rnA

2,3

DC CHARACTERISTICS
Characteristic

Symbol

VCC Power Supply Current
MCM54400A·SO and MCM5L4400A-SO, tRC = lIOns
MCM54400A-70 and MCM5L4400A-70, tRC = 130 ns
MCM54400A-80 and MCM5L4400A-80, tRC = 150 ns

ICC 1

VCC Power Supply Current (Standby) (RAS=CAS=VIH)

ICC2

VCC Power Supply Current During RAS Only Refresh Cycles (CAS = VI H)
MCM54400A-SO and MCM5L4400A-SO, tRC = 110 ns
MCM54400A·70 and MCM5L4400A-70, tRC = 130 ns
MCM54400A-80 and MCM5L4400A-80, tRC = 150 ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle (RAS = VIL)
MCM54400A·SO and MCM5L4400A-SO, tpc = 45 ns
MCM54400A·70 and MCM5L4400A-70, tpc = 45 ns
MCM54400A·80 and MCM5L4400A-80, tpc = 50 ns

ICC4

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V)

ICC5

-

120
100
85

-

120
100
85

-

2.0

-

70
70

-

60

-

rnA
rnA

2,3

rnA

2,3

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM54400A-SO and MCM5L4400A-SO, tRC = 110 ns
MCM54400A-70 and MCM5L4400A-70, tRC = 130 ns
MCM54400A-80 and MCM5L4400A-80, tRC = 150 ns

ICCS

VCC Power Supply Current, Battery Backup Mode-MCM5L4~0~ Only
(tRC = 125 jJ.S; CAS = CAS Before RAS Cycling or 0.2 V; G, W = VCC - 0.2 V;
AC-A9 = VCC - 0.2 V or 0.2 V; DOC-D03 = VCC - 0.2 V or 0.2 V or OPEN;
tRAS = Min to 1flS)

ICC7

-

Input Leakage Current (0 V " Vin " S.5 V)

Ilkalll

Output Leakage Current (CAS = VIH, 0 V" Vout" 5.5 V)

IlkalO)

Output High Voltage (IOH = - 5 rnA)

VOH

2.4

-

V

Output Low Voltage (lOL = 4.2 rnA)

VOL

-

0.4

V

Symbol

Max

Unit

Notes

Cin

5

pF

5

pF

5

MCM54400A
MCM5L4400A

CAPACITANCE (f = 1.0 MHz, TA = 25°C, VCC

1.0
200

rnA

IIA
rnA

2

300

IIA

2,4

-10

10

-10

10

IIA
IIA

120
100
85

= 5 V, Periodically Sampled Rather Than 100% Tested)

Parameter
Input Capacitance

AO-A9

G, RAS, CAS, W
1/0 Capacitance (CAS = VIH to Disable Output)

DOC-D03

7

CliO

7

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
3. Column address can be changed once or less while RAS = VIL and CAS = VIH.
4. tRAS (max) = 1 fls is only applied to refresh of battery-back up. tRAS (max) = 10 fls is applied to functional operating.
5. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = IfWIN

MOTOROLA MEMORY DATA
2-92

MCM~A·MCM5~A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70 o e, Unless Otherwise Noted)
READ, WRITE, AND READ-WRITE CYCLES (See Notes I, 2, 3, and 4)
Symbol
Parameter

Std

All

54400A-60
5L4400A-60

544OOA-70
5L4400A-70

54400A-80
5L4400A-BO

Min

Min

Min

Max

Random Read or Write Cycle Time

tRELREL

tRC

110

Read-Write Cycle Time

tRELREL

165

Fast Page Mode Cycle Time

tCELCEL

tRWC
tpc

Fast Page Mode Read-Write Cycle
Time

tCELCEL

tpRWC

95

-

Access Time from RAS

tRELQV

tRAC

-

60

Access Time from CAS

tcELQV

-

30

45

20

Max

Max

Unit

Notes

130

-

150

-

ns

5

185

-

205

ns

5

45

-

50

100

-

105

-

-

70

-

80

ns

6,7

20

20

ns

6,8

35

-

40

ns

6,9

40

-

45

ns

6

ns
ns

Access Time from Column Address

tAVQV

tcAC
tAA

Access Time from Precharge CAS

tcEHQV

tCPA

-

40

-

CAS to Output in Low-Z

tCELQX

tCLl

0

-

0

-

0

-

ns

6

Output Buffer and Turn-Off Delay

tcEHQZ

tOFF

0

20

0

20

0

20

ns

10

Transition Time (Rise and Fall)

IT

IT

3

50

3

50

3

50

ns

RAS Precharge Time

tREHREL

tRP

40

-

50

-

60

-

ns

RAS Pulse Width

tRELREH

tRAS

60

10 k

70

10k

80

10k

ns

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

60

200k

70

200k

80

200k

ns

RAS Hold Time

tcELREH

tRSH

20

-

20

20

-

ns

CAS Hold Time

tRELCEH

tCSH

60

70

80

-

ns

CAS Precharge to RAS Hold Time

tcEHREH

tRHCP

40

-

-

-

ns

CAS Pulse Width

tCELCEH

tCAS

20

10 k

20

10 k

20

10 k

ns

RAS to CAS Delay Time

tRELCEL

tRCD

20

40

20

50

20

60

ns

11

tRELAV

tRAD

15

30

15

35

15

40

ns

12

CAS to RAS Precharge Time

tCEHREL

tCRP

5

-

5

-

ns

tcEHCEL

tcp

10

-

5

CAS Precharge Time

10

-

10

-

ns

RAS to Column Address Delay Time

40

-

45

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 j.lS is required aiter power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate spec~ication, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range (O'C ,;; TA';; 70'C) is assured.
6. Measured with a current load equivalent to 2 TTL (- 200~, + 4 rnA) loads and 100 pF with the data output trip points set at VOH - 2.0 V
and VOL - 0.8 V.
7. Assumes that tRCD ,;; tRCD (max).
8. Assumes that tRCD ~ tRCD (max).
9. Assumes that tRAD ~ tRAD (max).
10. tOFF (max) andfor tGZ (max) define the time at which the output achieves the open circuit condition and is not referenced to output voltage
levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC'
.
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
2-93

•

MCM~A·MCM5~A

•

READ, WRITE, AND READ-WRITE CYCLES (Continued)
Symbol
Parameter

544OOA-60
SL4400A-60

544OOA-70
SL4400A-70

544OOA-60
SL4400A-60

Min

Min

Max

Unit

0

-

ns

10

20

-

20

-

ns

0

-

ns

14

15

-

ns

14

-

16
128

ms

-

ns

15

ns

15

ns

15

Std

Alt

Min

Row Address Setup Time

tAVREL

IASR

0

Row Address Hold Time

IRELAX

IRAH

10

Column Address Setup Time

tAVCEL

IASC

0

Column Address Hold Time

ICELAX

Column Address 10 RAS Lead Time

tAVREH

!cAH
IRAL

30

Read Command Setup Time

twHCEL

tRCS

0

Read Command Hold Time
Referenced 10 CAS

!cEHWX

tRCH

0

Read Command Hold Time
Referenced to RAS

IREHWX

tRRH

0

Write Command Hold Time
Referenced to CAS .

!cELWH

twCH

10

Write Command Pulse Width

twLWH

Write Command to RAS Lead Time

twLREH

twP
tRWL

20

Write Command to CAS Lead Time

twLCEH
tDVCEL

tCWL

20

tDS

0

!cELDX
tRVRV

tDH

15

tRFSH

-

Data in Setup Time
Data in Hold Time
Refresh Period

MCM54400A
MCM5L4400A

15

10

Max

16
128

0
10
0
15
35
0
0
0
15
15
20
20
0
15

-

Write Command Setup Time

twLCEL

-

tCELWL

twcs
tCWD

0

CAS to Write Delay

50

-

RAS to Write Delay

tRELWL

tRWD

90

-

50
100

Column Address to Write Delay Time

IAVWL

tAWD

60

-

65

CAS Precharge 10 WrHe Delay Time
(Page Mode)

!cEHWL

!cPWD

70

70

CAS Setup Time for CAS Before RAS
Refresh

tRELCEL

!cSR

5

CAS Hold Time for CAS Before RAS
Refresh

tRELCEH

tCHR

15

RAS Precharge to CAS Active Time

tREHCEL

tRPC

0

CAS Precharge Time for CAS Before
RAS Counter Time

!cEHCEL

tCPT

30

-

RAS Hold Time Referenced to G

'GLREH

tROH

G Access Time

'GLOV

tGA

G to Data Delay

'GLHDX

'GD
tGZ

Outp~ Buffer Turn-()ff

fromG

Delay Time

tGHOZ

10

-

20

0

5
15
0
40
10

-

Max

16
128

20

20

-

20

-

0

20

0

20

0
15
40
0
0
0
15
15

0
50
110
70
75
5
15
0
40
10

-

Notes

ns
ns
ns
ns
ns
ns

13

ns

13

ns
ns
ns

ns

15

ns

15

ns
ns
ns
ns
ns

20

ns

20

-

ns

0

20

ns

10
(contInued)

NOTES:
13. Either IRRH or tRCH must be satisfied for a read cycle.
_
14. These parameters are referenced to CAS leading edge in early write cycles and to W leading edge in late write or read-write cycles.
15. twcs, tRWD, !cWD, tAWD, and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; Htwcs ~ twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high Impedance) throughout
the entire cycle; if !cWD ~ !cWD (min), tRWD ~ tRWD (min), tAWD " tAWD (min), and !cPWD ~ !cPWD (min) (page mode), the cycle is
a read-write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied, the condition
of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
2-94

MCM~A·MCM5~A

READ, WRITE, AND READ-WRITE CYCLES (Continued)
Symbol
Parameter

54400A-60
5L4400A-60

54400A-70
5L4400A-70

54400A-BO
5L4400A-BO

Std

Alt

Min

Max

Min

Max

Min

Max

Unit

twLGL
tWLREL

tGH

20

-

20

20

10

10

10

Write Command Hold Time (Test
Mode)

tRELWH

twTH

10

10

-

10

-

ns

Write to RAS Precharge Time (CAS
Before RAS Refresh)

tWHREL

twRP

10

10

-

ns

tRELWL

twRH

10

-

10

Wr"e to RAS Hold Time (CAS Before
RAS Refresh)

-

-

ns

twTS

-

10

-

ns

G Command Hold Time
Write Command Setup Time (Test
Mode)

MOTOROLA MEMORY DATA

2-96

10

ns

Notes

•

MCM~A·MCM5~A

•

READ CYCLE

CAS V1H V1L -

ADDRESSES VIH VIL

-:L...l"-"'--'J

~_-;--J"

wVIH-"""">7r7~~~~---r----------+--r~~~~~~~~",
VIL - .....,'--''--''--''--''~f-'''--"'

G V1H VIL-~~~~~~~~~~~~~~~~_ _4--L4L~~~~~~~~~~~~~~

DQO-DQ3 VOH - - - - - - VOL -

EARLY WRITE CYCLE

ADDRESSES VIH V1L -

VIH -

W

..,.-.,.-,........,,......,......,.......,....,.,....,,.

V1L - ~~~~~~~~~~-+--+--~~~~~~~~~~~~~~~~~~~~

G V1H V1L -

DOO-DQ3

V1H

-

HIGHZ - - - - - - -

MOTOROLA MEMORY DATA
2-96

MCM~A·MCM5~A

G CONTROLLED WRITE CYCLE
IRC --------------;_

__ v 1H - - - - - \ _

~-------IRAS--------------;-I
..J<:-------~

RAS V
IL ~------ICSH

-------t

--"*1---- IRSH ---+---~

__ V1H CAS V
IL -

~---ICAS---~

ADDRESSES VIH V1L -

_ VIH - '"''"''"'r7'r7'~,.._,.:,.._,.:.....,.,.....,.,.....,.,.....,.,.....,.,__.I...
W
VIL-~~~~~~~~~~~~~~~-----~~~~~~~~~~~~~~~~

_ V1H G

~~~~~~~~~~---~+--~~~~~~~~~~~~~~~~~~~

VIL - ...>L..-"-..>L-"'--'''--''L.....l.<'-'''~ 14----<0+_

READ-WRITE CYCLE

ADDRESSES VIH V1L -

G

V 1H -

"A"~~+~~~~~~~;.-"

VIL -

-"-.J<.....J<....+""-""-""-""-""-"'-"'-~>L...::I=--II-.....J

DOO-DQ3 VIH NOH VIL NOL -

-----------I---{IX

MOTOROLA MEMORY DATA
2-97

•

MCM~A·MCM5~A

•

FAST PAGE MODE READ CYCLE
_
V1H - - - - = t RAS V
IL -

1 4 - - - - - - - - - - - - - t RASP - - - - - - - - - - - - - - - - t

_
V1H CAS V
IL -

W

13

V1H V1L -

V1H V1L -

-<1

DOO-DQ3 VOH - _ _ _ _ _ _ _ _ _
VOL -

FAST PAGE MODE EARLY WRITE CYCLE

ADDRESSES V1H V1L -

_ V1H W
V1L -

~~~r-1'~""""

........:.. . >L.........-"->L....l'-"l'\1~=:;f::~~'-"'~_j;=:;f:fwr~I~.><...:1'H;::::;l:fw~~<.....l<:.....>L...><..->

DOO-DQ3 V1H V1L - ~....lL..~-"-:.J' "1I--~~-"f"

'I£...;>L....l'-Y

""l=-";;;';";';';;';'~ "--l,,-\ll'r....:>I ""l=-"';;';';;;"';;';-"f" \L...lL...,;~L...O~-.l/..~

MOTOROLA MEMORY DATA
2-88

MCM~A·MCM5~A

•

FAST PAGE MODE READ-WRITE CYCLE

ADDRESSES

VIH VIL -

iN

G

VIH VIL -

VIH VIL -

VALID
DATA OUT

VALID
DATA IN

VALID
DATA OUT

MOTOROLA MEMORY DATA
2-99

VALID
DATA OUT

VALID
DATA IN

MCM~A·MCM5~A

RAS ONLY REFRESH CYCLE
(Wand 0 are Don'l Care)

~-------------------- tRC--------------------~
~-----------tRAS----------~~
__ V1H RAS

------"'-

CAS

.......,""""'''"""'1<"'':ir:--++---------------------:jh""'''''"-r--------

V1L -

__ V 1H V
IL -

r
ADDRESSE'-"'~

tAS~

CAS BEFORE RAS REFRESH CYCLE
(0 and AG-A9 are Don'l Care)

_ V1H W
VIL-~.....l£..*~Y

DO(H)03 VOH VOL -

-----5=

- - tOFF

HIGHZ

MOTOROLA MEMORY DATA
2-100

MCM~A·MCM5~A

HIDDEN REFRESH CYCLE (READ)

ADDRESSES V
IH V 1L

000-003

VOH VOL -

-----------<1
HIDDEN REFRESH CYCLE (EARLY WRITE)

_
V1H RAS V _

IL

_VIH
CAS
V 1L -

ADDRESSES VIH -V 1L

_ V
W

IH - .. . ",. . ",. . ",. . ,.,. . ,."-}\

VIL - -lo<'--"'--"'-"'-"-"-=f+-+-----'l:;....><.-J

G

~:: =<---i"--"''--'''-''--I'--------+-'''-'''-'''-'''~-><--''--''-~''-'"''-'''-'''-><--''--''-~.......,~
DQO-OQ3 VOH VOL------"f

~----------

HIGHZ - - - - - - - - - - -

MOTOROLA MEMORY DATA
2-106

MCM~A·MCM5~A

TEST MODE-READ CYCLE
(G=Low)
~-----------tRC---------------------;~
~------------- t RAS ---------------;~

~----- t C S H - - - - - - - .

_

V1H -

CAS V

IL -

ADDRESSES V IH -

VIL - -'--'''--'1.....>1

"'-_-;--J

iii V1H VIL -

'-''--''--''--''--''--'f--'~

000-003 VOH -

- - - - - - HIGH Z

VALID DATA OUT

VOL -

TEST MODE-EARLY WRITE CYCLE
~---------------------tRC---------------------~

~------------_t RAS ------------~

-------~

1---------~

~----- tCSH - - - - - - - - - - .

ADDRESSESV IH VIL -

.. I

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
tDsll-- tDH]
DQo-OO3 V IH VIL -

1
---------i

VALID
DATA IN

1\

, , ' - - - - - - - - - HIGHZ

MOTOROLA MEMORY DATA
2-107

•

MCM~A·MCM5~A

TEST MODE-FAST PAGE MODE READ CYCLE

D

(G=Low)

VIH---~

RAS

~-----------------------tRASP------------------------~

1 4 - - - - t PC - - - - I

V1L -

Q (DATA OUn VOH

- - - -_ _ _ _ _+_<

VOL -

TEST MODE-FAST PAGE MODE EARLY WRITE CYCLE

ADDRESSESVIH V1L -

WV1H -

DOO-DQ3

VIL -

--",,"--"--"-",,--""-->"4Hf;===:;+:"t;~'--><.~1;==*1M~-"-~~;::::;f="T~"'--'''''''''-''-''''''''''''

VIH -

....,.....,......,.......,......,.

V1L - ~..::L..:.I-:>I....;;,t

.,1,,.----"'"- ,,--,,-,,-.,.
"l''----_"f"

"-'''--''~

..1:------,... "'...",-.,.-". .J,,------,01- '"""""-"-""""""7<"""""'",,-,,"l=----'<

"-:.L-~y

MOTOROLA MEMORY DATA
2-108

,'------''I"

"~-",,"...::.I.....lL..::L.~:.t....:

MCM~A·MCM5~A

TEST MODE BLOCK DIAGRAM

lEI

AOC
AOC

VCC
NORMAL
512KBLOCK
BO

A

512K BLOCK
B1

li

A

~

B
TEST

d

NORMAL
AOC

9

AOC
AOC

VCC
NORMAL
512K BLOCK
B2

C

C

TEST

D
512KBLOCK
TEST

0

B3

TEST
NORMAL
AOC

d

~

9

AOC
AOC

VCC
NORMAL
512KBLOCK
B4

TEST

512K BLOCK
B5

E

TEST

F

AOC

d

~

9

AOC
AOC

Vcc
512KBLOCK
B6

d

G

G

~

H

TEST

512KBLOCK
B7

H

AOC

MOTOROLA MEMORY DATA
2-109

9

MCM~A·MCM5~A

ORDERING INFORMATION

D

-r- 11

(Order by Full Part Number)

T-,~

Motorola Memory Prefix _ _ _
Part Number

x

XX XX

T

,_ ...... ,"'.,... ""'..........,

.

Speed (60 = SO ns, 70 = 70 ns, 80 = 80 ns)
Package (N = 300-mil SOJ, Z = , OO-mil Plastic ZIP)

Full Part Numbers- MCM54400AN60
MCM54400AN70
MCM54400AN80
MCM5L4400AN60
MCM5L4400AN70
MCM5L4400AN80

MCM54400AN60R2
MCM54400AN70R2
MCM54400AN80R2

MCM54400AZSO
MCM54400AZ70
MCMS4400AZ80

MCM5L4400ANSOR2
MCMSL4400AN70R2
MCMSL4400AN80R2

MCMSL4400AZ60
MCMSL4400AZ70
MCMSL4400AZSO

MOTOROLA MEMORY DATA
2-110

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

L...--MC_M_5_4_40_0A_-_c---,l.

Advance Information

1M x 4 CMOS Dynamic RAM

."

Fast Page Mode
Operating Temperature - 40°C to + 85°C
The MCM54400A is a 0.7jJ. CMOS high-speed, dynamic random access memory. It
is organized as 1,048,576 four-bit words and fabricated with CMOS silicon-gate process technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low cost.
The MCM54400A requires only 10 address lines; row and column address inputs
are multiplexed. The device is packaged in standard 300-mil small outline J-Iead
(SOJ) and 100-mil zig-zag in-line (ZIP) package.
Three-State Data Output
Fast Page Mode
Test Mode
TIL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh: MCM54400A = 16 ms
Fast Access Time (tRAC)
MCM54400A-C70 = 70 ns (Max)
MCM54400A-C80 = 80 ns (Max)
• Low Active Power Dissipation:
MCM54400A-C70 = 550 mW (Max)
MCM54400A-C80 = 468 mW (Max)
• Low Standby Power Dissipation:
MCM54400A = 11 mW (Max, TIL Levels)
MCM54400A = 5.5 mW (Max, CMOS Levels)

ZPACKAGE
PLASTIC
ZIG-ZAG IN-LINE
CASE 836

,

•
•
•
•
•
•
•
•
•

NPACKAGE
300-MILSOJ
CASE 822

PIN NAMES

Ao-A9 ............... Address Inputs
DOO-D03 ......... Data InpuVOutput
G . . . . . . . . . . . . . . . . . . .. Output Enable
W ................. ReadlWrite Input
RAS ............ Row Address Strobe
CAS ......... Column Address Strobe
VCC ........... Power Supply (+ 5 V)
VSS ........................ Ground

PIN ASSIGNMENT
100-MIL ZIP

_'"lrG .-

300-MILSOJ

D02
26

VSS

25

DQ3

24

DQ2

D01

23

CAS

RAS

22

G

RAS

4

A9

18

A8

17

A7

VCC

A2

11

16

DA6
DA5

A5

12

15

13

14 PA4

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
2-111

A2

10

A3

D03
DOO

7

W

A1

VCC

_2_ CAS

VSS

AO
AO

3

5

DQO

D01

W

.-

11

l~ A9
12

13

15_

11.
16

17

ll!.

19
A7 _. 20

A1
A3

A4
A6

~.-=.=.A9

MCM54400A-C

•

BLOCK DIAGRAM

w________-q---.....
.....--+-<3

CAS,------.j

AO
A1
A2

A3
A4
AS
A6

A7
AS
A9

RAS,------i

ABSOLUTE MAXIMUM RATING (See Note)
Rating
Power Supply Voltage

Symbol

Value

Unit
V

VCC

-1 to +7

Vin, Vout

-1 to +7

V

Data Out Current

lout

50

mA

Power Dissipation

Po

700

mW

Operating Temperature Range

TA

-40to+S5

·C

Voltage Relative to VSS for Any Pin Except VCC

·C
-55to +150
Tsta
NOTE: Permanent device damage may occur nABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended vo~ages for extended
periods of time could affect device reliability.
Storage Temperature Range

MOTOROLA MEMORY DATA
2·112

This device contains circuitry to protectthe
inputs against damage dueto high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high-Impedance
circuit.

MCM54400A-C

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = - 40 to 85°e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.0

V

1

VSS

0

Logic High Voltage, All Inputs

VIH

2.4

-

0

S.5

0
V

1

Logic Low Voltage, All Inputs

VIL

-1.0

-

0.8

V

1

Symbol

Min

Max

Unit

Notes

mA

2,3

DC CHARACTERISTICS
Characteristic
VCC Power Supply Current
MCM54400A-C70, tRC = 130 ns
MCM54400A-C80, tRC = 150 ns

ICC1

VCC Power Supply Current (Standby) (RAS=CAS=VIH)

ICC2

VCC Power Supply Current During RAS Only Refresh Cycles (CAS=VIH)
MCM54400A-C70, tRC = 130 ns
MCM54400A-C80, tRC = 150 ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle (RAS = VILl
MCM54400A-C70, tpc = 45 ns
MCM54400A-C80, tpc = 50 ns

ICC4

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V)

-

100
85

-

70
SO

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM54400A-C70, tRC = 130 ns
MCM54400A-C80, tRC = 150 ns
Input Leakage Current (0 V ,;; Yin ,;; S.5 V)

-

ICC5
ICCS

-

Ilkg(l)

Output Leakage Current (CAS = VIH, 0 V,;; Vout';; 5.5 V)

Iikol01
VOH
VOL

Output High Voltage (IOH = - 5 mAl
Output Low Voltage (IOL = 4.2 mAl

2.0

-

-

MCM54400A-C

100
85

-10
-10

1.0

mA
mA

2,3

mA

2,3

mA
mA

100
85
10
10

2

2.4

-

I'A
I'A
V

-

0.4

V

Symbol

Max

Unit

Notes

Cin

5

pF

5

CAPACITANCE (f= 1.0 MHz, TA = 25°C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

AO-A9

G, RAS, CAS, W

7

110 Capacitance (CAS = VIH to Disable Output)
7
DQO-DQ3
pF
5
CliO
NOTES.
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
3. Column address can be changed once or less while RAS = VIL and CAS = VIH.
4. tRAS (max) = 1 I's is only applied to refresh of battery-back up. tRAS (max) = 10 I'S is applied to functional operating.
5. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = lal/IN.

MOTOROLA MEMORY DATA
2-113

•

MCM54400A-C

•

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA = - 40 to 85°e, Unless Otherwise Noted)

READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbol
Parameter

Std

MCM54400A-C70
Alt

Min

Max

-

105

ns

SO

ns

-

20

-

-

70

20

ns

6, S

35

-

40

ns

6,9

tpc

45

tCELQV

tCAC

Access TIme from Column Address

tAVQV

tAA

5

-

tCELCEL

Access TIme from CAS

5

ns

100

Fast Page Mode Cycle TIme

tRAC

ns

-

1S5

tpRWC

Notes

50

130

tRWC

tRELQV

Unit

-

tRC

tRELREL
tCELCEL

Max

205

tRELREL

Read-Write Cycle TIme
Fast Page Mode Read-Write Cycle TIme

Min

-

Random Read or Write Cycle TIme

Access TIme from RAS

MCM54400A-CBO
150

ns
6,7

Access TIme from Precharge CAS

tCEHQV

40

-

45

ns

6

teELQX

tePA
tCLZ

-

CAS to Output in Low-Z

0

-

0

-

ns

6

Output Buffer and Turn-Off Delay

teEHQZ

'oFF

0

20

0

20

ns

10

IT

IT

3

50

3

50

ns

Transition TIme (Rise and Fall)
RAS Precharge TIme

tREHREL

tRP

50

-

60

-

ns

RAS Pulse Width

tRELREH

tRAS

70

10,000

SO

10,000

ns

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

70

200,000

SO

200,000

ns

RASHoldTIme

tCELREH

tRSH

20

-

20

-

ns

CAS Hold TIme

tRELCEH

tCSH

70

-

SO

CAS Precharge to RAS Hold TIme

tCEHREH

tRHCP

40

-

45

CAS Pulse Width

teELCEH

tCAS

20

10,000

20

10,000

ns

RAS to CAS Delay TIme

tRELCEL

tRCD

20

50

20

60

ns

11

tRELAV

tRAD

15

35

15

40

ns

12

CAS to RAS Precharge TIme

teEHREL

tCRP

5

-

5

-

ns

CAS Precharge Time

teEHCEL

tcp

10

Row Address Setup TIme

tAVREL

tASR

0

-

Row Address Hold TIme

tRELAX

tRAH

10

-

Column Address Setup TIme

tAVCEL

tASC

0

Column Address Hold TIme

teELAX

teAH

Column Address to RAS Lead TIme

tAVREH

Read Command Setup TIme

!WHCEl

RAS to Column Address Delay TIme

-

ns
ns

0

-

10

-

ns

0

-

ns

10

15

-

15

tRAL

35

-

40

-

tRCS

0

-

0

-

ns
ns

ns
ns
ns

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL'
2. An initial pause 01 200 IlS is required aiter power-up followed by S RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range (- 40°C,; TA'; S5°C) is assured.
6. Measured with a current load equivalent to 2 TTL (-200 ItA, + 4 mAl loads and 100 pF with the dataoutputtrip points set at VOH = 2.0 V
and VOL = O.S V.
7. Assumes that tRCD ,; tRCD (max).
S. Assumes that tRCD ~ tRCD (max).
9. Assumes that tRAD ~ tRAD (max).
10. 'oFF (max) andforlGZ (max) define the time at which the output achieves the open circuit condition and is not referenced to output voltage
levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC'
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
2-114

MCM54400A-C

READ, WRITE, AND READ-WRITE CYCLES (Continued)
Symbol

Parameler

Sid

MCM54400A-C70
All

Min

Read Command Hold TIme Referenced to CAS

!cEHWX

tRCH

Read Command Hold TIme Referenced to RAS

tREHWX

tRRH

a
a

Write Command Hold TIme Referenced to CAS

!cELWH

twCH

15

Write Command Pulse Width

twLWH

15

Write Command to RAS Lead TIme

tWLREH

twP
tRWL

Write Command to CAS Lead TIme

twLCEH

Data in Setup TIme

tDVCEL

Data in Hold TIme

!cELDX
tRVRV

CAS to Write Delay

MCM54400A-c80

Max

Min

-

a
a
15

-

20

-

20

!cWL
tDS

20

-

20

a

-

a

tDH

15

15

tRFSH

-

-

twLCEL
tCELWL

twcs
tCWD

50

RAS to Write Delay

tRELWL

tRWD

Column Address to Write Delay TIme

tAVWL

CAS Precharge to Write Delay TIme (Page Mode)

Refresh Period

MCM54400A-C

16

15

-

Unil

Noles

-

ns

13

ns

13

-

ns

16

ms
ns

15

ns

15

ns

15

ns

15

ns

15

Max

ns
ns
ns
ns

14

ns

14

100

-

110

tAWD

65

-

70

tCEHWL

!cPWD

70

75

CAS Setup TIme for CAS Before RAS Refresh

tRELCEL

tCSR

5

-

CAS Hold TIme for CAS Before RAS Refresh

tRELCEH

-

15

tREHCEL

!cHR
tRPC

15

RAS Precharge to CAS Active TIme

a

-

a

CAS Precharge TIme for CAS Before RAS Counter
TEST

tCEHCEL

!cPT

40

-

40

-

10

-

10

-

ns

-

20

-

20

ns

-

ns

20

ns

-

ns

Write Command Setup TIme

a

RAS Hold TIme Referenced to G

tGLREH

tROH

G Access TIme

tGLQV

iGA

G to Data Delay

tGLHDX

20

Output Buffer Tum-Off Delay TIme from G

iGHOZ

iGD
tGZ

G Command Hold TIme

twLGL

tGH

20

a

-

a
50

5

20

20

a

-

20

Write Command Setup TIme (Test Mode)

twLREL

twTs

10

-

10

Write Command Hold TIme (Test Mode)

tRELWH

twTH

10

10

Write to RAS Precharge TIme (CAS Before RAS
Refresh)

twHREL

twRP

10

-

10

ns
ns
ns
ns

10

ns
ns
ns

Write to RAS Hold TIme (CAS Before RAS Refresh)
ns
10
10
tRELWL
twRH
NOTES.
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in early write cycles and to iii leading edge in late write or read-write cycles.
15. tWCS. tRWD. tCWD. tAWD. and !cPWD are not restrictive operating parameters. They are included In the data sheet as electrical characteristics only; if twcs" twcs (min). the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout
the entire cycle; If !cWO" tCWD (min). tRWD "tRWD (min). tAWD "tAWD (min). and tCPWD "!cPWD (min) (page mode). the cycle is
a read-wrRe cycle and the data out will contain data read from the selected cell. Hneither of these sets of conditions is satisfied. the condition
of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
2-115

•

MCM54400A-C

•

READ CYCLE
I RC
I RAS

RAS VIH V IL -

ICSH
IRSH
I CAS

CAS V IH V1L -

lRAL

ADDRESSES V IH VIL -

W V1H V 1L -

\

G

V1H V1L -

DOQ-D03 VOH VOL -

EARLY WRITE CYCLE
~---------------------IRC----------------------~

V1H RAS

~-------------IRAS------------~

V 1L -

V 1H CAS

V 1L -

ADDRESSES VIH V 1L -

W

G

V 1H V1L V1H V 1L -

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
~ I- I.-IDH-~
IDS

V1H DQQ-D03
V 1L -

----------1.

VALID D A T A I N ] f - - - - - - - - - HIGHZ - - - - - - -

MOTOROLA MEMORY DATA
2-116

MCM54400A-C

G CONTROLLED WRITE CYCLE
~----------------------tRC------------------------~
~--------------tMS--------------~

__ V1H RAS
V1L -

---~

Jc-------:i

~-----------tCSH -------------.,~
- - - -....0 - - - - - - - -

tRSH

---+---1

~-----tCAS-------.,~

__ V 1H CAS V
IL -

j4j------\------ t RAL

-------+----.j

ADDRESSES VIH V1L -

_ VIH W

"""'''''''''''''''''''''''''''''r-l'"""""""",.....",.....",....."......"......,,-1

_ V1H -

?/

tAS~

CAS BEFORE RAS REFRESH CYCLE
(G and AO-A9 are Don't Care)

__ V1H CAS
V 1L -

DQO-DQ3 VOH VOL -

____~i=tOFF
__

HIGHZ

MOTOROLA MEMORY DATA
2-120

MCM54400A-C

•

HIDDEN REFRESH CYCLE (READ)

ADDRESSES VIH VIL -

VIH -

G

VIL -

DClO-DQ3 VOH -

VOL -

HIDDEN REFRESH CYCLE (EARLY WRITE)
~------------IRC----------~~-------------IRC------------~

_
VIH - - - - . L ~--- I RAS - - - - . j
RAS V _
IL

J,...-----,:l ""1-----1 RAS----.j J:-----L

1 * - - - ICRP - - - - . I

_V IH CAS V
IL -

ADDRESSES VIH VIL -

AD~

WCS;1

~r:

,Mru

- i l W:,t

=XXXXX~~~'-----r,.\X~X7'<"'""'l"
:11: =L.;~L...l..~~+_ _ _ _ _-=F-~~~...J.i....:.l...::¥.-~~~t.....::.I.~...:.l...::¥.-::.t..,;.I.L....:~~

DOC-D03 VOH - - - - - - - - - - - HIGHZ - - - - - - - - - - VOL - - - - - " " "

MOTOROLA MEMORY DATA

2-126

MCM54400A-C

TEST MODE-READ CYCLE
(G=Low)
~--------------------tRC--------------------~

I+--------------t RAS --------------1
--------~

~--------~
~----------tCSH----------~

ADDRESSES VIH V1L - ................~ --......~T=-

WV1H V1L -

DQO-DQ3

VOH VOL -

~~~~~~~~~+_--~----------------------~~7\7\7\~~~~"

L...::.~~~~+::.L-'J

----------- HIGHZ

-----+---{I

VALID DATA OUT

TEST MODE-EARLY WRITE CYCLE
~--------------------tRC--------------------~
~------------tMS------------~
---------1
~----------~

ADDRESSES VIH V1L -

~--r_r_-t~L----------~.1

xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
tDsll.-tDH]

DQO-DQ3 VIH V1L -

1

--------~i

VALID

~ATAIN

1\

, f - - - - - - - - HIGHZ - - - - - - - -

MOTOROLA MEMORY DATA
2-127

•

MCM54400A-C

TEST MODE-FAST PAGE MODE READ CYCLE
(G =Low)
V1H -·--...".,.
RAS

~-------------------tMSP------------------------~

1 + - - - - t PC -------I

V1L -

Q (DATA OUT) VOH -

VOL -

--------+-<1

TEST MODE-FAST PAGE MODE EARLY WRITE CYCLE

_V 1H CAS V
IL -

WV1H VIL -

~~~ot....:>I.~='-i;:==:::;f:fw;~i-:>I.""'ti;:=::::;~~~~-=It"j;:::::;1F't:.-;;~~~~

MOTOROLA MEMORY DATA

2-128

MCM54400A-C

TEST MODE BLOCK DIAGRAM

Vee

Aoe
NORMAL
512KBLoeK
BO

A

A

TEST

B

TEST

512KBLoeK
B1

B

d

~
~

Aoe
Aoe
Vee

Aoe
NORMAL
512KBLOCK
B2

e

C
D

TEST

512KBLoeK
B3

j'j

TEST
NORMAL

d

~
~

Aoe
Aoe
Vee

Aoe
512KBLOCK
B4

TEST

512KBLOCK
B5

d

E

E

F
TEST
NORMAL

~
~

AOC
AOC
AOC

VCC
NORMAL
512KBLOCK
B6

G

G

~
~

H

TEST

512KBLOCK
B7

d

Fi

AOC

MOTOROLA MEMORY DATA
2-129

•

MCM54400A-C

..

ORDERING INFORMATION
(Order by Full Part Number)
OOAn

T_C_M_J---l

Motorola Memory Prefix _ _ _ _ _
Part Number

-

111

Shipping Method (R2 = Tape & Reel, Blank = Rails)
Speed (70 = 70 ns, 80 = 80 ns)
Temperature Range (C = - 40 to 85°C)
Package (N = 300-mil SOJ, Z = 100-mil Plastic ZIP)

Full Part Numbers- MCM54400ANJ70
MCM54400ANJ80

MCM54400ANJ70R2
MCM54400ANJ80R2

MOTOROLA MEMORY DATA
2-130

MCM54400AZ70
MCM54400AZ80

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM54402A

Advance Information
1M x 4 CMOS Dynamic RAM
Static Column

NPACKAGE
3DO-MILSOJ
CASE 822

The MCM54402A is a 0.7~ CMOS high-speed, dynamic random access
memory. It is organized as 1,048,576 four-bit words and fabricated with
CMOS silicon-gate process technology. Advanced circuit design and fine line
processing provide high performance, improved reliability, and low cost. The
static column mode feature allows column data to be accessed upon the
column address transition when RAS and CS are held low, similar to static
RAM operation.
The MCM54402A requires only 10 address lines; row and column
address inputs are multiplexed. The device is packaged in a standard 300-mil
J-Iead small outline package, and a 100-mil zig-zag in-line package (ZIP).
Three-State Data Output
Static Column Mode
Test Mode
TIL-Compatible Inputs and Outputs
RAS Only Refresh
CS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh: MCM54402A = 16 ms
Fast Access Time (tRAC):
MCM54402A-60 = 60 ns (Max)
MCM54402A-70 = 70 ns (Max)
MCM54402A-80 = 80 ns (Max)
• Low Active Power Dissipation:
MCM54402A-60 = 660 mW (Max)
MCM54402A-70 = 550 mW (Max)
MCM54402A-80 = 468 mW (Max)
• Low Standby Power Dissipation:
MCM54402A = 11 mW (Max, TTL Levels)
MCM54402A = 5.5 mW (Max, CMOS Levels)

ZPACKAGE
PLASTIC
ZIG-ZAG IN-LINE
CASE 836
' "

•
•
•
•
•
•
•
•
•

PIN NAMES
AO--A9 . . . . . . . . .. Address Input
DOO--DQ3 ......... Data Input
G .............. Output Enable
iii ............ ReadIWrite Input
RAS . . . . .. Row Address Strobe
CS ............... Chip Select
Vce ...... Power Supply (+ 5 V)
VSS .................. Ground

PIN ASSIGNMENT
100-MILZIP

-,,--..G
2

3OG-MILSOJ

==

3
OClOll

26

pvss

DOl 12

25

003

WI3

24

DQ2

RASI4

23

A9 5

22

CS
G

18

A9

AI

10

17

A7

A2

11

16

A6

A3

12

15

AS

Vee

13

14 ~A4

This document contains information on a new product. SpeCIfications and Information herein are subject to change wlthout notice.

MOTOROLA MEMORY DATA
2-131

CS
003

VSS

OClO
OQl

8

RAS
AD

AD

==

A2

11

12
13

Vee 15=
A5
A7

11
16

17
19

W

!~ A9
AI
A3
A4

!~ A6
20

~A8

•

MCM54402A

BLOCK DIAGRAM
IlQ(}-OO3

w---------L..lWI~,.>'-l,-+-J

MOTOROLA MEMORY DATA
2-141

II

MCM54402A

STATIC COLUMN MODE READIWRITE MIXED CYCLE

fII
ADDRESSES VIH
VIL

=

- VIHG VIL - l...:.t.~lL..lo~.lWt..:>L..lL..~~.lWt..:>L..lL..lI...l.,,*~_+-_ _+-_ _-j-J

VALID
DATA OUT

MOTOROLA MEMORY DATA
2·142

MCM54402A

RAS ONLY REFRESH CYCLE
(Wand G are Don'l Care)

tAC
RAS

CS

VIH-

-----'31...

----------~

i"'1------tAAS--------i

VIL -

VIHVIL -

·
XXX~ AD~~SSXXXXXXXXXXXXXXXXXXXXXXX
tASA

I~

CS BEFORE RAS REFRESH CYCLE
(G and AO-A9 are Don'l Care)

cs

tAP

J.~------:ll

VIHVIL- _ _- - I

W VIHVIL -

-"--"---"-~..::.t.....:;"

~a3~~:= ___________.~)~---------------------

MOTOROLA MEMORY DATA
2-143

HIGHZ

•

MCM54402A

..

HIDDEN REFRESH CYCLE (READ)

14-----tRC
1 4 - - - - IRAS'------

1 4 - - - - tRAS----+i

RAS VIHVIL -

tcHR
_

~

-

tCRP-

VIH-

CS VIL-

_ VIH -

7\i'\'7\ri~r-r+----+~m:~--.h~7rI':"'7':"'l'r1l'"7\""7I~'r1I'"""""'r7<""'K"7<:~

W VIL -

..>W"'-l/....lL...lL.:>i

DOO-DQ3 VOH -

----'---_~

VOL-

-""'V

'",.",--------------'f

HIDDEN REFRESH CYCLE (EARLY WRITE)

1 4 - - - - - tRC

----~. .- - - - -

14----tR~------

AAS VIHVIL -

VIH -

CS

VIL -

v -

ADDRESSES VIH

IL -

_ VIH W VIL -

~""""'''''''''':'"'7T'""n-7\

.:.t..,;1L..¥...lL.l.W.I...l.L...l.L*1f-1_ _ _--'~

MOTOROLA MEMORY DATA

2-144

tRC------+1

~---tAAS---~

MCM54402A

E

CS BEFORE RAS REFRESH COUNTER TEST CYCLE
tRAS

tcSR*---+I

READ CYCLE
ADDRESSES VIHVIL -

~----- tRSH----;-:-~

Jr----i I..f - - - - - tcs---~ J--+r-----

1_-++-----

tRAL-----H-----+I

COLUMN ADDRESS

L:>I.~>Wo:~I4-¥~>Wo:....l£..>Wo:~ ~--:--,-_ _ _ _ _ _ _ _ _--,-;---;--;-.J

'I.....l£..lL..lI....l£..~....l£..lL..lI:....lL.lL..lI~ " } - - - - : - - , - - - - - - - - - - ' I "'7-'''-''-~'-'J..-''-'t.....>L..........

iii VIHVIL -

LV. "--"LV

G VIHVIL -

...L.-'''-''-''-'''-'''-''--''-''-''-''-''-''-''-'''-'':-''-......."'''I''--t--'

tDH
DOQ-DQ3 VIHiVoH VILNOL -

- - - - - HIGHZ - - - - - - i 1
VALID
DATA OUT

MOTOROLA MEMORY DATA
2-145

MCM54402A

•

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the RAM. During an extended inactive
state (greater than 16 milliseconds with the device powered
up), a wakeup sequence of eight active cycles is necessary to
ensure proper operation.
ADDRESSING THE RAM
The ten address pins on the device are time multiplexed at
the beginning of a memory cycle by the row address strobe
(RAS) clock, into two separate 1O-bit address fields. A total of
twenty address bits, ten rows and ten columns, will decode
one of the 1,048,576 bit locations in the device. RAS active
transition latches the row address field. Column addresses are
not latched, hence the "static column" deSignation of this device. Chip select (CS) active transition (active = VIL, tRCD
minimum) follows RAS on all read, write, or read-write cycles
and is independent of column address. The static column feature allows greater flexibility in setting up the external column
addresses into the RAM.
There are three other variations in addressing the 1M x 4
RAM: RAS only refresh cycle, CS before RAS refresh
cycle, and Static Column mode. All three are discussed in
separate sections that follow.
READ CYCLE
The DRAM may be read with four different cycles: "normal"
random read cycle, static column mode read cycle, read-write
cycle, and static column mode read-write cycle. The normal
read cycle is outlined here, while the other cycles are discussed in separate sections.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS active transition latching the desired
row. The write (W) input level must be high (VI H), tRCS (minimum) before the CS active transition, to enable read mode. A
valid column address can be provided at any time (tRAD minimum), independent of the CS active transition.
Both the RAS and CS clocks trigger a sequence of events
which are controlled by several delayed internal Clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex
window. Both CS and output enable (G) control read access
time; CS and G must be active (and column address must be
valid) by tRCD maximum, and tRAc-taA minimum, respectively, to guarantee valid data out (0) at tRAC (access time
from RAS active transition).lfthe tRCD maximum is exceeded
and/or G active transition does not occur in time, read access
time is determined by either the CS or G clock active transition
(leAC or 'GA)·
The RAS and CS clocks must remain active for a minimum
time of tRAS and tcs respectively, to complete the read cycle.
The column address must remain valid for !AH after RAS
inactive transition to complete the read cycle. W must remain
high throughout the cycle, and for time tRRH or tRCH after
RAS or CS inactive transition, respectively, to maintain the
data at that bit location. Once RAS transitions to inactive, it
must remain inactive for a minimum time of tRP to precharge
the internal device circuitry for the next active cycle. 0 is valid,
but not latched, as long as the CS and G clocks are active.
When either the CS or G clock transitions to inactive, the

output will switch to High Z (three-state) tOFF or taz after the
inactive transition.
WRITE CYCLE
The user can write to the DRAM with anyoffourcycles: early
write, late write, static column mode early write, and static column mode read-write. Early and late write modes are discussed here, while static column mode write operations are
covered in another section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of Wto active
(VILl. Early and late write modes are distinguished by the active transition of W, with respect to CS leading edge. Minimum
active time tRAS and tcs, and precharge time tRP apply to
write mode, as in the read mode.
An early write cycle is characterized by Wactive transition at
minimum time !wCS before CS active transition. Column address set up and hold times (tASC, tCAH), and data in (D) set
up and hold times (tD.£...tDH) are referenced to CS in an early
write cycle. RAS and CS clocks must stay active fortRWL and
tCWL' respectively, after the start of the early write operation to
complete the cycle.
o remains in three-state condition throughout an early write
cycle because Wactive transition precedes or coincides with
CS active transition, keeping data-out buffers and G disabled.
A late write cycle (referred to as G-controlled write) occurs
when Wactive transition is made after CS active transition. W
active transition could be delayed for almost 10 microseconds
after CS active transition, (tRCD + leWD + tRWL + 2tr) S
tRAS, if other timing minimums (tRCD, tRWL, and tTl are
maintained. Column address and 0 timing parameters are referenced to Wactive transition in a late write cycle. Output buffers are enabled by cg active transition but 0 may be indeterminate-see note 18 of ac operating conditions table.
Parameters tRWL and tCWL also apply to late write cycles.
READ-WRITE CYCLE
A read-write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically a
late write cycle, as discussed in the WRITE CYCLE section,
except Wmust remain high for leWD and/or tAWD minimum,
to guarantee valid 0 before writing the bit.
STATIC COLUMN MODE CYCLES
Static column mode refers to multiple successive data operations performed at any or aliI 024 column locations on the selected row of the 1M x 4 dynamic RAM during one RAS cycle.
Read access time of multiple operations (tAA or tCAC) is considerably faster than the regular RAS clock access time tllAC.:.
Multiple operations can be performed simply by keeping RAS
active. CS may be toggled between active and inactive states
at any time within the RAS cycle.
Once the timing requirements for the initial read, write, or
read-write cycle are met and RAS remains low, the device is
ready for the next operation. Operations can be intermixed in
any order, at any column address, subject to normal operating
conditions previously described. Every write operation must
be clocked with either CS or W, as indicated in static column
mode early write cycle timing diagrams A and B. Column address and 0 timing parameters are referenced to the signal
clocking the write operation. CS must be toggled inactive (lep)
to perform a read operation after an early write operation (to
turn output on), as indicated in static column mode readl
write mixed cycle timing diagram. The maximum number of
consecutive operations is limited to tRASC. The cycle ends
when RAS transitions to inactive.

MOTOROLA MEMORY DATA
2-146

MCM54402A

Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CS active the end of
a read or write cycle, while RAS cycles inactive for tRP and
back to active, starts the hidden refresh. This is essentially the
execution of a CS before RAS refresh from a cycle in progress
(see Figure 1). Wis subject to the same conditions with respect to RAS active transition (to prevent test mode) as in CS
before RAS refresh.

REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically
refreshed (recharged) to maintain the correct bit state. Bits in
the MCM54402A require refresh every 16 milliseconds.
This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM54402A. Burst refresh, a refresh of
aliI 024 rows consecutively, must be performed every 16 milliseconds on the MCM54402A.
A normal read, write, or read-write operation to the RAM will
refresh all the bits (4096) associated with the particular row decoded. Three other methods of refresh, RA5-only refresh,
CS before RAS refresh, and hidden refresh are available on
this device for greater system flexibility.

es BEFORE RAS REFRESH COUNTER TEST

RA5-0nly Refresh
RAS-only refresh consists of RAS transition to active,latching the row address to be refreshed, while CS remains high
(VIH) throughoulthe cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.
CS Before RAS Refresh
CS before RAS refresh is enabled by bringing CS active before RAS. This clock order activates an internal refresh counterthat generates the row address to be refreShed. External address lines are ignored during the automatic refreSh cycle.
The output buffer remains at the same state it was in during
the previous cycle (hidden refresh). Wmust be inactive for·
timetWRP before and timetWRH after RAS active transition to
prevent switching the device into test mode.

The internal refresh counter of this device can be tested with
a CS before RAS refresh counter test. This test is performed
with a read-write operation. During the test, the internal refresh
counter generates the row address, while the external address
supplies the column address. The entire array is refreshed after 1024 cycles, as indicated by the check data written in each
row. See CS before RAS refresh counter test cycle timing
diagram.
The test can be performed after a minimum of 8 CS before
RAS initialization cycles. Test procedure:
1.
Write "O"s into all memory cells with normal write mode.
2.
Select a column address, read "0' out and write "I" into
the cell by performing the CS before RAS refresh
counter test, read-write cycle. Repeat this operation
1024 times.
3.
Read the "1"s which were written in step 2 in normal read
mode.
4.
Using the same starting column address as in step 2,
read "I" out and write "0" into the cell by performing the
es before RAS refresh counter test, read-write
cycle. Repeat this operation 1024 times.
5.
Read "0" which were written in step 4 in normal read
mode.
6.
Repeat steps 1 to 5 using complement data.

CS BEFORE RAS

REFRESH CYCLE

Q -HIGHZ-+--~

VALID DATA OUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA
2-147

CS BEFORE RAS

REFRESH CYCLE

•

MCM54402A

•

TEST MODE

out is determined by the internal test mode logic of the device.
See the following truth table and test mode block diagram.
W, CS before, RAS timing puts the device in "Test Mode",
as shown in the test mode timing diagram. A "CS before
RAS" refresh cycle or a "Rn only" refresh cycle puts the device back in normal mode. Refresh.is performed in test mode
by using a "W, CS before RAS" refresh cycle which uses the
internal refresh address counter.

The internal organization ofthis device (512 x 8) allows ilia
be tested as, if it were a 512K x 4· DRAM. Nineteen of the
twel'1ty addresses are used when operating the device in test
mode. Column address AO ,is ignored by the device in test
mode. A test mode cycle reads and/or writes data to a bit in
each of eight 512K blockS (eo-e7) in parallel. i;:l!Iernal data

TEST MODE TRUTH TABlE
D

BO,Bl

B2,B3

B4,B5

B6,B7

0

0

0

0

0

1

1

1

1

1

1

.1

-

Q

Any Other

0

TEST MODE
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ±1 0%, T A"" 0 to 70°C, Unless Otherwise Noted)
READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbol
Parameter
Random Read or Write Cycle
Time
Static Column Mode Cycle Time
Access Time from RAS
Access Time from CS
Access Time from Column
Address

54402A-60

54402A-70

Std.

All.

Min

Max

Min

tRELREL

tRC

115

-

135

40

-

45

-

-

65

-

75

25

-

25

35

-

40

tAVAV

tsc

tRELQV

tRAC

tcELQV

tcAC

tAVQV

tAA

-

Max

54402A-60
Min

Max

Unit

Notes

155

-

ns

5

50

-

ns

85

ns

25

ns

6,8

45

ns

6,9

-

RAS Pulse Width

tRELREH

tRAS

65

10k

75

10 k

85

10k

ns

RAS Pulse Width (Static Column
Mode)

tRELREH

tRASC

65

200k

75

200k

85

200k

ns

-

25

-

25

75

-

85

-

ns

RAS Hold Time

tcELREH

tRSH

25

CS Hold Time

tRELCEH

tcSH

65

CS Pulse Width

tCELCEH

tcs

25

10k

25

10 k

25

10k

ns

CS Pulse Width (Static Column
Mode)

tcELCEH

tcsc

25

200k

25

200 k

25

200k

ns

Column Address to RAS Lead
Time

tAVREH

tRAL

35

40

-

45

-

ns

-

6,7

ns

NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 I1S is required aiter power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specnication applies for all input signals. In addition to meeting the transition rate specnication, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specification for tRC (mi~) is used only to indicate cycle time at which proper operation over the full temperature range (0 °C ,; TA';
70°C) is ensured.
6. Measured with a current load equivalent to 2 TIL (- 200 1iA, + 4 mAl loads and 100 pF with the data output trip points set at VOH = 2.0
V and VOL = 0.8 V.
7. Assumes that tRCD'; tRCD (max).
8. Assumes that tRCD ~ tRCD (max).
9. Assumes that 'RAD " tRAD (max).

MOTOROLA MEMORY DATA
2-148

MCM54402A

w, CS BEFORE RAS REFRESH CYCLE (TEST MODE ENTRY)
(G and AO-A9 are Don't Care)

~---------------tRC----------------~

tRAS -----------10;
.Jt:--....;.;;--~

3_

tO FF
_ _ _ _ _ __
HIGHZ - - - - - - - - - -

TEST MODE - READ CYCLE
~------------------tRC--------------------~

1+------------- tRAS-----------+I
RAS VIH -

------.l

Jt------'lI.

VIL-

tCSH

ADDRESSES VvIH IL-

_ VIH - '""''''''"'''''''-i-l''''+I----t----------+'--+"""*'"'''~7r1~7r1~'7rK"
W VIL _ ......,............,..........,,-....,

G VIHVIL- ~~~~~~~~~~~~~_r--~~~~~~~~~~~~~~~

DOO-OO3 VOH -

_ _ _ __

VOL -

MOTOROLA MEMORY DATA
2-149

•

MCM54402A

•

TEST MODE - EARLY WRITE CYCLE
~------------------tRC--------------------~
~-----------

IRAs -------------1

RAS VIH,- - - - - i
VIL-

tRP-----+I

1Jr---';';;"---,L
'--_ _

ADDRESSES VVIH IL-

G

JI~ =?XiX!YX/XiXXXXX'IX'IXlJX:/XXXXXXXX'lJX'IXIXIXiXIX/x

E"

tDs-ll-tDH3

DClO-l)Q3 VIH - - - - - - - - . . . . .
VALID DATA IN
. . . . . - - - - - - - HIGH Z - - - - - - VIL- -

TEST MODE - STATIC COLUMN MODE READ CYCLE
~~-------------------tAASC ------------------~

tsc
VIHADDRESSES VIL -

_ VIHW VIL -

DClO-l)Q3 VOH VOL -

COLUMN
ADDRESS 1

-----1-1+----

COLUMN
ADDRESS 2

~"-"--lWI...lL.~

HIGH Z - - - H i

MOTOROLA MEMORY DATA

2-160

tRAL----~

COLUMN
ADDRESSN

MCM54402A

TEST MODE - STATIC COLUMN MODE EARLY WRITE CYCLE (A)

v ADDRESSES

JI~ -

TEST MODE - STATIC COLUMN MODE EARLY WRITE CYCLE (8)

ADDRESSES VIHVIL -

- VIH - - - - - - - " ' "
W VIL-

MOTOROLA MEMORY DATA
2-151

•

MCM54402A

•

TEST MODE BLOCK DIAGRAM

Aoc

d

Vee

NORMAL

~~

1

d

Vee

NORMAL

~~

--""---1
d

Vee

NORMAL

~~

1
MOTOROLA MEMORY DATA

2-152

MCM54402A

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory Prefix

T

J 11

54402A

X XX XX

T

Part Number _ _ _ _ _ _

,........... ,,,._ ........... "".,
Speed (60 = 60 ns, 70 = 70 ns, 80 = 80 ns)
Package (N = 300-mil SOJ, Z = 100-mil Plastic ZIP)

Full Part Numbers- MCM54402AN60
MCM54402AN70
MCM54402AN80
MCM54402AN10

MCM54402AN60R2
MCM54402AN70R2
MCM54402AN80R2
MCM54402AN10R2

MOTOROLA MEMORY DATA

2-153

MCM54402AZ60
MCM54402AZ70
MCM54402AZ80
MCM54402AZ10

•

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM54410A

IIEJI

Advance Information
1M x 4 CMOS Dynamic RAM

NPACKAGE
300-MILSOJ

Write Per Bit Mode
The MCM54410A is a 0.711 CMOS high-speed, dynamic random access memory. It is
organized as 1,048,576 four-bit words and fabricated with CMOS silicon-gate process
technology. Advanced circuit design and fine line processing provide high performance,
improved reliability, and low cost.
The MCM54410A requires only 10 address lines; row and column address inputs are
multiplexed. The device is packaged in a standard 300-mil J-Iead small outline package,
and a 100-mil zig-zag in-line package (ZIP).
• Three-State Data Output
• Write Per Bit Mode
• Fast Page Capability
• Test Mode
• TTL-Compatible Inputs and Outputs
• RAS Only Refresh
• CAS Before RAS Refresh
• Hidden Refresh
• 1024 Cycle Refresh: MCM54410A = 16 ms
300-MILSOJ
• Fast Access Time (tRAe):
MCM54410A-60 = 60 ns (Max)
WO/DOO [ 1
26 P VSS
MCM54410A-70 = 70 ns (Max)
MCM54410A-80 = 80 ns (Max)
W1/D01 2
25 PW3ID03
• Low Active Power Dissipation:
WBIWE 3
24 PW2ID02
MCM54410A-60 = 660 mW (Max)
RAS[ 4
23 P CAS
MCM54410A-70 = 550 mW (Max)
MCM54410A-80 = 468 mW (Max)
A9 [ 5
22
• Low Standby Power Dissipation:
MCM54410A = 11 mW (Max, TTL Levels)
MCM54410A = 5.5 mW (Max, CMOS Levels)
A8
AO
18

pG

A1

10

17

A2

11

16 pA6

A7

A3

12

15 PAS

Vcc

13

14

PM

CASE 822

ZPACKAGE
PLASTIC
ZIG-ZAG IN-LINE

CASE 836

PIN ASSIGNMENT
100-MILZIP

_"""1rG ""
3 "2" CAS
W2ID02
4
W3ID03
VSS
WO/DOO
W1/D01
WBIWE
RAS
10
A9
11
AO
12
A1
13
A2
!~ A3
vcc 15" 16
M
17
AS
lit A6
19
A7
~O" A8
~~

PIN NAMES
AO-A9 ............................................. Address Input
WO/DQO-W3/DQ3 ..................... Write Select/Data Input Output
Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Data Output
W ............................................. ReadlWrite Enable
RAS ......................................... Row Address Strobe
CS .................................................. Chip Select
VCC ......................................... Power Supply (+ 5 V)
VSS ..................................................... Ground
NC ............................................... No Connection

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA

2-154

MCM54410A

•

BLOCK DIAGRAM
WBIWE

WO/DOQ-W3/D03

----------<1"-,

DATA IN
BUFFER

CAS------i

......----I--G

AO
A1
A2
A3
A4

A5
A6

A7
AS
A9

RAS;------!

ABSOLUTE MAXIMUM RATING (See Note)
Rating
Power Supply Voltage

Symbol

Value

Unit

VCC

-1 to +7

V

Vin, Vout

-1 to +7

V

Data Out Current

lout

50

rnA

Power Dissipation

Po

700

mW

Operating Temperature Range

TA

o to +70

'c

Tstg

-55to
+150

'C

Voltage Relative to VSS for Any Pin Except VCC

Storage Temperature Range

This device contains circuitry to protectthe
inputs against damage due to high static voltages or electric fields; however, ~ is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high-impedance
circuit.

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
WRITE-PER-BIT MODE

The write-per-bit mode allows selective masking of a write
operation on a particular set of device DOs for a given cycle.
The write-per-bit function is enabled by holding the WB/WE
signal "Low" at the falling edge of RAS for the minimum hold
time. Masked DOs are selected by holding Data in (Di) "Low"
on the falling edge of RAS for the minimum hold time. Data is
then written into the device only on the unmasked DOs, which
occurs on the falling edge of either WB/WE (late write) or CAS
(early write). Any combination of DOs can be selectively

masked for each write cycle. The truth table for the write-perbit function is shown in the following table:
At the Failing Edge of RAS
CAS

WBIWE

oal

Function

H
H
H
H

H
H
L
L

H
L
H
L

Write Enabled
Write Enabled
Write Enabled
Write Masked

MOTOROLA MEMORY DATA
2-155

MCM54410A

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

-

6.5

V

1

Logic Low Voltage, All Inputs

VIL

-1.0

-

0.8

V

1

Min

Max

Unit

Notes

mA

2,3

DC CHARACTERISTICS
Characteristic

Symbol

VCC Power Supply Current
MCM5441 OA-60, tRC = liOns
MCM54410A-70, tRC = 130 ns
MCM54410A-80, tRC = 150 ns

ICCl

VCC Power Supply Current (Standby) (RAS=CAS=VIH)

-

120
100
85

ICC2

-

2.0

VCC Power Supply Current During RAS Only Refresh Cycles (CAS=VIH)
MCM54410A-60, tRC = 110 ns
MCM54410A-70, tRC = 130 ns
MCM5441 OA-80, tRC = 150 ns

ICC3

-

120
100
85

VCC Power Supply Current During Fast Page Mode Cycle {RAS ='VIU
MCM54410A-60, tpc - 45 ns
MCM54410A-70, tpc = 45 ns
MCM5441 OA-80, tpc = 50 ns

ICC4

-

70
70
60

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V)

ICC5

-

1.0

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM54410A-60, tRC = 110 ns
MCM54410A-70, tRC = 130 ns
MCM54410A-80, tRC = 150 ns

ICC6

-

-

120
100
85

Input Leakage Current (O V " Yin :;; 6.5 V)

Ilkalll

-10

10

Output Leakage Current (CAS = VIH, 0 V " Vout S 5.5 V)

IlkalO)

-10

10

I1A
I1A

Output High Voltage (I0H = - 5 mAl

VOH

2.4

-

V

Output Low Voltage (1m = 4.2 rnA)

VOL

-

0.4

V

Symbol

Max

Unit

Notes

Cin

5

pF

4

pF

4

-

mA

rnA

2,3

mA

2,3

mA
2

mA

CAPACITANCE (f = 1.0 MHz, TA = 25°C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter
Input CapaCitance

AO-A9

G, RAS, CAS, WBiWE
WO/DOO-W3ID03

I/O CapaCitance (CAS = VIH to Disable Output)

7
CliO

7

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
3. Column address can be changed once or less while RAS = VIL and CAS = VIH.
4. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I.:l.VtlV.

MOTOROLA MEMORY DATA

2-156

MCM54410A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70°C, Unless Otherwise Noted)
READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbol
Parameter

Std

54410A-60
Alt

Min

Max

-

Random Read or Write Cycle lime

tRElREl

tRC

110

Read-Write Cycle Time

tRElREl

tRWC

165

Fast Page Mode Cycle lime

tCELCEl

tpc

45

Fast Page Mode Read-Write Cycle
lime

tCELCEl

tpRWC

100

Access lime from RAS

tRElQV

tRAC

Access Time from CAS

tCElQV

tcAC

Access lime from Column Address

tAVQV

IAA

Access lime from Precharge CAS

tcEHQV

tCPA

-

CAS to Output in low-Z

tcElQX

tClZ

0

-

Output Buffer and Turn-Off Delay

tCEHQZ

tOFF

0

20

Transition Time (Rise and Fall)

-

-

54410A-70
Min
130
185
45
100

60
20
30
40

-

Max

-

70

54410A-80
Min

Max

Unit

Notes

150

-

ns

5

205

-

ns

5

50

-

ns

105

-

ns

-

80

ns

6,7

20

ns

6,8

40

ns

6,9

40

-

45

ns

6

0

-

0

-

ns

6

0

20

0

20

ns

10

-

20
35

IT

IT

3

50

3

50

3

50

ns

RAS Precharge lime

tREHREl

tRP

40

-

50

-

60

-

ns

RAS Pulse Width

tRElREH

tRAS

60

10k

70

10k

80

10 k

ns

RAS Pulse Width (Fast Page Mode)

tRElREH

tRASP

60

200 k

70

200k

80

200k

ns

RASHoldlime

tcElREH

tRSH

20

-

20

-

20

CAS Hold lime

tRElCEH

tcSH

60

CAS Precharge to RAS Hold Time

tCEHREH

tRHCP

40

CAS Pulse Width

tCElCEH

tCAS

20

10 k

20

10k

20

10k

ns

RAS to CAS Delay lime

tRElCEl

tRCD

20

40

20

50

20

60

ns

11

tRELAV

tRAD

15

30

15

35

15

40

ns

12

CAS to RAS Precharge lime

tCEHREl

tCRP

5

-

5

-

ns

tCEHCEl

tcp

10

-

5

CAS Precharge lime

10

-

10

-

ns

RAS to Column Address Delay lime

-

70
40

-

80
45

-

ns
ns
ns

(conllnued)
NOTES:
1. VIH min and Vil max are reference levels for measuring timing of input signals. Transition times are measured between VIH and Vil'
2. An initial pause of 200 liS is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and Vil (or between Vil and VI H) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range (O°C :s; TA :s; 70°C) is ensured.
6. Measured with a current load equivalent to 2 TTL (- 200 llA, + 4 mAl loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes thatlRCD:S; tRCD (max).
8. Assumes that tRCD ;, tRCD (max).
9. Assumes thattRAD;' tRAD (max).
10. tOFF (max) andlor tGZ (max) define the time at which the output achieves the open circuit condition and is not referenced to output voltage
levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by tcAC'
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA

2-157

•

MCM64410A

•

READ, WRITE, AND READ-WRITE CYCLES (Continued)
Symbol

54410A-60

54410A-70

54410A-80

Sid

All

Min

Max

Min

Max

Min

Row Address Setup lime

tAVREL

tASR

0

0

0
10

0

-

15

-

15

35

-

15

Parameter
Row Address Hold lime

tRELAX

tRAH

10

Column Address Setup lime

tAVCEL

tASC

0

Column Address Hold lime

tCELAX

tCAH

15

Column Address to RAS Leed lime

tAVREH

tRAL

30

Read Command Setup lime

twHCEL

tRCS

0

Reed Command Hold Time
Referenced to CAS

!cEHWX

tRCH

0

Reed Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

-

Write Command Hold lime
Referenced to CAS

tCELWH

twCH

10

-

10

0
0
0

Write Command Pulse Width

twLWH

twP

10

-

15

Write Command to RAS Lead lime

twLREH

tRWL

20

20

Write Command to CAS Lead lime

twLCEH

tCWL

20

Data in Setup lime

tDVCEL

tDS

0

Data in Hold lime

!cELDX

tDH

15

-

15

-

Refresh Period

tRVRV

tRFSH

-

16

-

16

0

-

20
0

Write Command Setup lime

tWLCEL

twcs

0

CAS to Write Delay

!cELWL

!cWD

50

-

50

RAS to Write Delay

tRELWL

tRWD

90

-

100

-

65

5
15

40

-

10

-

Column Address to Write Delay lime

tAVWL

tAWD

60

CAS Precharge to Write Delay lime
(Page Mode)

!cEHWL

tCPWD

70

CAS Setup Time for CAS Before RAS
Refresh

tRELCEL

!cSR

5

CAS Hold lime for CAS Before RAS
Refresh

tRELCEH

!cHR

15

RAS Precharge to CAS Active lime

tREHCEL

tRPC

0

-

CAS Precharge lime for CAS Before
RAS Counter Test

tCEHCEL

tCPT

30

-

RAS Hold lime Referenced to G

-

'GLREH

tROH

10

G Access lime

'GLOV

'GA

-

G to Data Delay

'GLHDX

'GD

Output Buffer Tum-Off Delay lime
fromG

tGHOZ

'GZ

70

0

Max

Unil
ns

0

-

15

-

ns

0
40
0
0

ns
ns
ns
ns
ns
ns

13

ns

13

15

-

ns

20

-

ns

20

ns

15

-

-

16

ms

0

-

ns

50

-

ns

15

ns

15

ns

15

ns

15

ns

40

-

0

110
70
75
5
15
0

ns

14

ns

14

ns
ns

10

-

ns

-

20

ns

20

-

20

-

ns

0

20

0

20

ns

-

20

-

0

20

15

ns

20

20

Noles

10
(continued)

NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leeding edge in early write cycles and to W leading edge in late write or read-write cycles.
15. twcs, tRWD, tCWD' tAWD, and !cPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if twcs ~ twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout
the entire cycle; if tCWD ~ !cWD (min), tRWD ~ tRWD (min), tAWD ~ tAWD (min), and !cPWD ~ tCPWD (min) (page mode), the cycle is
a reed-write cycle and the data out will contain data read from the selected cell. ~ neither of these sets of conditions is satisfied, the condition
of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
2-158

MCM54410A

READ, WRITE, AND READ-WRITE CYCLES (Continued)
Symbol
Parameter

5441DA-7D

5441DA-6D
Alt

Min

twLGL

tGH

20

-

20

Write Command Setup TIme (Test
Mode)

twLREL

twTS

10

10

Write Command Hold TIme (Test
Mode)

tRELWH

twTH

10

-

10

Write to RAS Precharge Time (CAS
Before RAS Refresh)

tWHREL

twRP

10

-

10

Write to RAS Hold TIme (CAS Before
RAS Refresh)

tRELWL

tWRH

10

-

10

Write Per Bit Setup TIme

twBVREL

tWBS

a

Write Per Bit Hold TIme

tRELWBV

twBH

10

-

10

-

10

-

a

-

a

-

10

-

10

G Command Hold TIme

Write Per Bit Selection Setup TIme

twOVREL

twos

a

Write Per Bit Selection Hold TI me

tRELWOV

twOH

10

Max

Min

MOTOROLA MEMORY DATA

2-159

a

Max

5441DA-8D

Std

Min

-

20

-

Max

Unit
ns

10

-

10

-

ns

10

-

10

a

ns

ns
ns

-

ns

-

ns

ns

ns

Notes

MCM54410A

..

READ CYCLE

ADDRESSES VIH V'L-~~r....:.t

W~E V'H-\7\7\7~~~~~~+---~r---------~-------+--~-*"~?r~~~~~
V IL -.......,"'--l"--'~'--loI~~~

G V,H V'L-~~~~~~~~~~~~~~~__-+~~~~~~~~~~~~~~

WO/DQO- VOH W3IDQ3 VOL -

EARLY WRITE CYCLE

ADDRESSES V IH V,L -

WO/DQO- VIH W3IDQ3 V ,L -

MOTOROLA MEMORY DATA
2-1~

MCM54410A

G CONTROLLED WRITE CYCLE

III

~---------------------tRC----------------------~
~--------------tRAS------------~~

------~

t~H

~----------~

----~.-------tRSH----+---~

__ V1H CAS V
IL -

14_-----

tCAS ----~.-j

ADDRESSES VIH V1L -

WOIDOO- V1H -

W3ID03 VILREAD-WRITE CYCLE
~----------------------------tRWC----------------~--------~~

~----------------------tR~ ------------------------~

tCSH--------------------~

..r----"('

t RSH --------------+....,
-"-------------------1 r---~-----

tc~

G V1H VIL -

......-"-""-+""-"'-"'-~""-""-""-f_"'--"'f_-_r_--'

V1L WOIDo(}-

W3ID03
VOHVoL-

HIGHZ

MOTOROLA MEMORY DATA
2-161

MCM54410A

..

FAST PAGE MODE READ CYCLE
_ V1H - --~
RAS V
IL -

1 + - - - - - - - - - - - - - 1RASP

------------_

1+----1 PC 4 - -..

_ _ V1H WB/WE V
IL -

....lL.-"-...o.I....*~

-<1

WO/DOO- VO H - _ _ _ _ _ _ _ _ _
W3/D03 VOL -

FAST PAGE MODE EARLY WRITE CYCLE
_
V1H RAS V
IL -

V 1H CAS V1L -

ADDRESSES V IH V1L -

_ _ V1H WBIWE
V 1L -

MqrOROLA MEMORY DATA
2-162

MCM54410A

•

FAST PAGE MODE READ-WRITE CYCLE

RAS

VIHVIL -

CAS

VIH-

ADDRESSES VIHVIL -

WOIDODW3IDQ3

VALID
DATA IN

VALID
DATA IN

MOTOROLA MEMORY DATA
2·163

VALID
DATA IN

MCM54410A

..

RAS ONLY REFRESH CYCLE
(WBIWE and G are Don't Care)

~-------------------tRC------------------~
~------------tRAS-----------4~

RAS 1H1L -- -----o::L
CAS 1H1L -tRAH
AS::1
ADDRESSES ~:: =XXXXXAD~~~SSXXXXXXXXXXXXXXXXXXr---V

V

k

V

V

t

CAS BEFORE RAS REFRESH CYCLE
(G and AD-A9 are Don't Care)

1*-------------------

t

RC ----------------------.1

1+_----------- t RAS - - - - - - - - - - - - - Je-----....L

14-------

WO/DOC- VOH W3/DQ3 VOL-

tCHR ------+I

______1i=t OFF

HIGHZ --------------

_

MOTOROLA MEMORY DATA

2-164

MCM54410A

HIDDEN REFRESH CYCLE (READ)

~---------------tRC--------------~·-----------tRC----------~
~-------

tRAS - - - - I

j,,-----------,L ~--

tRAS

---~

ADDRESSES VI1HL -V

____
WBIWE IL -

VIH-~~~~~~~~-4-----------~~~~------~~~7\7\7\~~~~\7~
V

VOLOH --

WOIDQO· V
W3IDQ3

'-.:l'-"'--"-"-r"-->J

VALID DATA OUT

-------------------{I

HIDDEN REFRESH CYCLE (EARLY WRITE)
~-----------tRC------------~~-----------tRC-------~

_ V1H- - - - : i [4---- tRAS
RAS 1L -

----~ ~----,i

[4----t RAS-----i

..1<-------:>1.

V

~--

1H CAS V
IL -

_

V

tCRP

---~

ADDRESSES 1H ADD
ADDRESS
1VL tWC~· I-- ---1t W~
WBrNE ~:: =XXXXX~~~""----±\X~"-""-XX"""""'X"""""'XX"""'X"'""XX,..-,.rx"7'C""7X~X>
V

G

r

,AII'U

~:: =I-::¥....:.L....:"--"t...:::.~~'*.::L..~:Jt--+--------L.¥-;~~~~.:::.L.:::.L~

WO/DOO· VOHWS/DOS VOL-

WO/DClO- VIHW3fDOS VILREAD-WRITE CYCLE

MOTOROLA MEMORY DATA
2-166

MCM54410A

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the RAM. During an extended inactive
state (greater than 16 milliseconds with the device powered
up), a wakeup sequence of eight active cycles is necessary to
ensure proper operation.
ADDRESSING THE RAM
The ten address pins on the device are time multiplexed at
the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 10-bit address fields. A total of twenty address bits, ten
rows and ten columns, will decode one of the 1,048,576 bit locations in the device. RAS active transition is followed by CAS
active transition (active = VIL, tRQQ3linimum) for all read or
write cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system designer flexibility in setting up the external addresses into the
RAM.
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the 1Mx4
RAM: RAS only refresh cycle, CAS before RAS refresh
cycle, and page mode. All three are discussed in separate
sections that follow.
READ CYCLE
The DRAM may be read with four different cycles: "normal"
random read cycle, page mode read cycle, read-write cycle,
and page mode read-write cycle. The normal read cycle is outlined here, while the other cycles are discussed in separate
sections.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (WBIWE) input level must be
high (VIH), tRCS (minimum) before the CAS active transition,
to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex
window. Both CAS and output enable (G) control read access
time: CAS must be active before or at tRCD maximum and G
must be active tRAC-IGA (both minimum) after RAS active
transition to guarantee valid data out (0) attRAC (access time
from RAS active transition). If the tRCD maximum is exceeded
and/or G active transition does not occur in time, read access
time is determined by either the CAS or G clock active transition (tCML.0r tGAL
The RAS and CAS clocks must remain active for a minimum
time 0!..!BAS...and tCAS respectively, to complete the read
cycle. WBIWE must remain high throughout the cycle, and for
time tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data at that bit location. Once RAS
transitions to inactive, it must remain inactive for a minimum

time of tRP to precharge the internal device circuitry for the
next active cycle. 0 is valid, but not latched, as long as the CAS
and G clocks are active. When either the CAS or G clock transitions to inactive, the output will switch to High Z (three-state)
tOFF or tGZ after the inactive transition.
WRITE CYCLE
The user can write to the DRAM with any of four cycles: early
write, late write, page mode early write, and page mode readwrite. Early and late write modes are discussed here, while
page mode write operations are covered in another section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of WBIWE to active (VILl. Early and late write modes are distinguished by the
active transition of WBIWE, with respect to CAS. Minimum active time tRAS and tCAS, and precharge time tRP apply to
write mode, as in the read mode.
An early write cycle is characterized by WB/WE active transition at minimum time tw~efore CAS active transition.
Data in (D) is referenced to CAS in an early write cycle. RAS
and CAS clocks must stay active for tRWL and tCWL' respectively, after the start of the early write operation to complete the
cycle.
remains in three-state condition throughout an early write
cycle because WB/WE active transition precedes or coincides
with CAS active transition, keeping data-out buffers and G disabled.
A late write cycle (referred to as G-controlled write) occurs
when WB/WE active transition is made after CAS active transition. WBIWE active transition could be delayed for almost 10
microseconds after CAS active transition, (tRCD + tCWD +
tRWL + 2IT) s; tRAS, if other timing minimums (tRCD, tRWL,
and IT) are maintained. D is referenced to WB/WE active transition in a late write cycle. Output buffers are enabled by CAS
active transition but outputs are switched off by G inactive transition, which is required to write to the device. 0 may be indeterminate-see note 15 of ac operating conditions table. RAS
and CAS must remain active fortRWL and tcWL, respectively,
after WB/WE active transition to complete the write cycle. G
must remain inactive for tGH afterWB/WE active transition to
complete the write cycle.
READ-WRITE CYCLE
A read-write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically a
late write cycle, as discussed in the WRITE CYCLE section,
except WBIWE must remain high for tCWD minimum after the
CAS active transition, to guarantee valid 0 before writing the
bit.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
1024 column locations on a selected row of the 1M x 4 dynamic RAM. Read access time in page mode (tCAC) is typically
half the regular RAS clock access time, tRAC' Page mode operation consists of keeping RAS active while toggling CAS between VIH and ~The row is latched by RAS active transition, while each CAS active transition allows selection of a new
column location on the row.
A page mode cycle is initiated by a normal read, write, or
read-write cycle, as described in prior sections. Once the
timing requirements for the first cycle are met, CAS transitions
to inactive for minimum tcp, while RAS remains low (VIL)' The
second CAS active transition while RAS is low initiates the first
page mode cycle (tpc or tPRWC). Either a read, write, or

a

MOTOROLA MEMORY DATA
2-167

•

MCM64410A

•

read-write operation can be performed in a page mode cycle,
subject to the same conditions as in normal operation
(previously described). These operations can be intermixed in
consecutive page mode cycles and performed in any order.
The maximum number of consecutive page mode cycles is
limited by tRASP' Page mode operation is ended when RAS
transitions to inactive, coincident with or following CAS
inactive transition.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically
refreshed (recharged) to maintain the correct bit state. Bits in
the MCM54410A require refresh every 16 milliseconds.
This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM5441 OA. Burst refresh, a refresh of
all 1024 rows consecutively, must be performed every 16 milliseconds on the MCM5441 OA.
A normal read, write, or read-write operation to the RAM will
refresh all the bits associated with the particular row decoded.
Three other methods of refresh, RAS-only refresh, CAS before RAS refresh, and hidden refresh are available on this
device for greater system flexibility.

during the previous cycle (hidden refresh). WBfWE must be
ina~tive fortime tWRP before and time !wRH after RAS active
transition to prevent switching the device into test mode.
Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). WBfWE is subject to the same conditions with respect to RAS active transition (to prevent test
mode cycle) as in CAS before RAS refresh.
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CAS before RAS refresh counter test. This test is performed with a read-write operation. Duringthe test, the internal
refresh counter generates the row address, while the external
address supplies the column address. The entire array is refreshed after 1024 cycles, as indicated by the check data written in each row. See CAS before RAS refresh counter test
cycle timing diagram.
The test can be performed after a minimum of eight CAS before RAS initialization cycles. Test procedure:
1.
Write "O"s into all memory cells with normal write mode.
2.
Select a column address, read "0" out and write "1" into
the cell by performing the CAS before RAS refresh
counter test, read-write cycle. Repeat this operation
1024 times.
3.
Read the "1 "s which were written in step 2 in normal read
mode.
4.
Using the same starting column address as in step 2,
read "1" out and write "0" into the cell by performing the
CAS before RAS refresh counter test, read-write
cycle. Repeat this operation 1024 times.
5.
Read "O"s which were written in step 4 in normal read
mode.
6.
Repeat steps 1 to 5 using complement data.

RAS-Only Re,fresh
RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(VIH) throughoutthe cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.
CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order activates an internal refresh
counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh
cycle. The output buffer remains at the same state it was In

CAS BEFORE RAS
REFRESH CYCLE

MEMORY CYCLE

.--------..

"
WO/DOO-W3IOO3 -

HIGHZ

/

r'r\

VALID DATA OUT

\

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA

2-168

CAS BEFORE RAS
REFRESH CYCLE

)--

MCM54410A

TEST MODE
The internal organization of this device (512K x 8) allows it
to be tested as if it were a 512K x 4 DRAM. Nineteen of the
twenty addresses are used when operating the device in test
mode. Column address AO is ignored by the device in test
mode. A test mode cycle reads and/or writes data to a bit in
each of eight 512K blocks (SD-S7) in parallel. External data
out is determined by the internal test mode logiC of the device.

See the following truth table and test mode block diagram .
Vii, CAS before RAS timing puts the device in "Test Mode"
as shown in the test mode timing diagram. A CAS before RAS
or a RAS only refresh cycle puts the device back into normal
mode. Refresh is performed in test mode by using a Vii, CAS
before RAS refresh cycle which uses internal refresh address
counter.

TEST MODE TRUTH TABLE
D

BO, B1

a

a

1

1

-

I B2, B3 I B4, B5 1 B6, B7

I

o1

I

a1

Any Other

Q
1
1

0
1

I

a

TEST MODE
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, T A = 0 to 70°C, Unless Otherwise Noted)
READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2, 3, and 4)
54410A~0

Symbol
Parameter

54410A-70

54410A-80

Std

All

Min

Max

Min

Max

Min

Random Read or Write Cycle Time

tRELREL

tRC

115

-

135

-

155

Max

Fast Page Mode Cycle lime

tCELCEL

tpc

50

-

50

-

55

-

Access lime from RAS

tRELQV

tRAC

-

65

-

75

-

85

ns

6,7

Access lime from CAS

tCELQV

tcAC

-

25

-

25

25

ns

6,8

Access lime from Column Address

tAVQV

tAA

-

35

-

40

Access lime from Precharge CAS

tCEHQV

tCPA

-

45

-

RAS Pulse Width

tRELREH

tRAS

65

10k

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

65

RAS Hold lime

tcELREH

tRSH

25

ns

6,9

45

50

ns

6

75

10 k

85

10k

ns

200k

75

200k

85

200k

ns

-

25

-

25

-

75

-

85

-

tRELCEH

tCSH

CAS

tcEHREH

tRHCP

45

-

45

-

50

-

tcELCEH
tAVREH

tCAS
tRAL

25

10k

25

10k

25

10k

45

-

Column Address to RAS Lead lime

35

5

ns

45

65

CAS Pulse Width

Notes

ns

-

CAS Hold lime
Precharge to RAS Hold lime

Unit

-

40

-

ns
ns
ns
ns
ns

NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 2001's is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements tr = 5.0 ns.
5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range (O'C :;; TA :;; 70°C) is ensured.
6. Measured with acurrentload equivalentto 2 TIL (-200!1A, + 4 mAl loads and 100 pFwith the dataoutputtrip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes thattRCD :;;tRCD (max).
8. Assumes thattRCD " tRCD (max).
9. Assumes thattRAD "tRAD (max).

MOTOROLA MEMORY
2-169

DATA

•

MCM54410A

WRITE, CAS BEFORE RAS REFRESH CYCLE (TEST MODE ENTRY)

II

(0 and AO-A9 are Don't Care)

i---------IRC

----------1

RAS V1H V1L -

CAS

VIH - ,,""~..-:2:-----::i
V1L -

iii V1H V1L -~~~~~~~-----~~~~~~~~~~~~~~~~~~
Q(OATAOUT) VOH - - - - - - - - - - - HIGHZ - - - - - - - - - - VOL - - - - - - "

MOTOROLA MEMORY DATA
.2-170

MCM54410A

TEST MODE-READ CYCLE
(e; = Low)
~---------------------IRC--------------------~~

i+--------------RAS

RAS V1H V1L -

--------1

--------~

~--------_1

~------tCSH------_I

_
V1H CAS V
IL -

ADDRESSES VIH V IL -

.<.....l""-",--""

"-_-,-~

WBIWE VIH VIL -

WO/DOO- VOH W3/D03 VOL -

~'--lo'--lo"--l<"--l<~;......11-,:>/

- - - - - - HIGHZ

----+---<1

VALID DATA OUT

TEST MODE-EARLY WRITE CYCLE
J4------------IRC-----------~

~-------------I RAS -----------~

-------,:!I..

j,------""'--

ADDRESSES VIH V IL -

WaNiE VIH VIL -

G VIH

-

V IL -

II

.1

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
IDS

WO/DOO- VIH W3ID03 V1L _

1--1--

IDH

VALID
DATA IN

Mc/JrOROLA MEMORY DATA
2-171

•

MCM54410A

•

TEST MODE-FAST PAGE MODE READ CYCLE
~----------------------IMSP------------------------~

/4------ 1RHCP -----~

1+------ 1PC -t----~

WBIWE V1H VIl - .....................ll;-..,

WOIOClO- VOH - _ _ _ _ _ _ _ _-<1

W31DQ3 VOl TEST MODE-FAST PAGE MODE EARLY WRITE CYCLE

ADDRESSESVIH V1l -

MOTOROLA MEMORY DATA

\

\

2-,172

MCM54410A

TEST MODE BLOCK DIAGRAM

AOC
AOC

VCC
NORMAL
512KBLOCK
BO

A

A

TEST

B
TEST

512KBLOCK
B1

B

d
~

9

AOC
AOC
AOC

Vee
512K BLOCK
B2

C

C
0

TEST

512KBLoeK
B3

Ii
TEST
NORMAL
Aoe

d
~

9

AOC
Aoe

Vee
NORMAL
512K BLOCK
B4

TEST

512KBLOCK
B5

E

E
F

NORMAL
Aoe

d
~

9

Aoe
Aoe

Vee
NORMAL
512KBLoeK
B6

G

G
H

TEST

512KBLOCK
B7

Fi

Aoe

MOTOROLA MEMORY DATA
2-173

d
~

9

•

MCM64410A

..

ORDERING INFORMATION
(Order by Full Part Number)

III T

MCM 54410A X XX XX

Motorola Memory Prefix

T

Part Number - - - - - - - - - '

"_"-("'._'-.•~'-'.'J
Speed (60 = 60 ns, 70 = 70 ns, 80 = 80 ns)
Package (N = 300-mil SOJ, Z = 100-mil Plastic ZIP

Full Part Numbers- MCM54410AN60
MCM54410AN70
MCM54410AN80

MCM54410AN60R2
MCM54410AN70R2
MCM54410AN80R2

MOTOROLA MEMORY DATA
2-174

MCM54410AZ60
MCM54410AZ70
MCM54410AZ80

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM54800A
MCM5L4800A
MCM5V4800A

Advance Information
512K x 8 CMOS Dynamic RAM
Page Mode

J PACKAGE
400MILSOJ

The MCM54800A is a 0.7~ CMOS high-speed, dynamic random access memory. It
is organized as 524,288 eight-bit words and fabricated with CMOS silicon-gate process
technology. Advanced circuit design and fine line processing provide high performance,
improved reliability, and low cost.
The MCM54800A requires only 10 address lines; row and column address inputs
are multiplexed. The device is packaged in a standard 400-mil-wide J-Iead small outline package, and a 100-mil zig-zag in-line package (ZIP).
•
•
•
•
•
•
•
•

•

•

•

•
•

Three-State Data Output
Fast Page Mode
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
Self Refresh (MCM5V4800A only)
1024 Cycle Refresh:
MCM54800A = 16 ms
MCM5L4800A and MCM5V4800A = 128 ms
Fast Access lime (tRAC)
MCM54800A-70, MCM5L4800A-70, and
MCM5V4800A-70 = 70 ns (Max)
MCM54800A-80, MCM5L4800A-80, and
MCM5V4800A-80 = 80 ns (Max)
MCM54800A-l 0, MCM5L4800A-l0, and
MCM5V4800A-l0 = 100 ns (Max)
Low Active Power Dissipation:
MCM54800A-70, MCM5L4800A-70, and
MCM5V4800A-70 = 578 mW (Max)
MCM54800A-80, MCM5L4800A-80, and
MCM5V4800A-80 = 495 mW (Max)
MCM54800A-l0, MCM5L4800A-l0, and
MCM5V4800A-l0 = 440 mW (Max)
Low Standby Power Dissipation:
MCM54800A, MCM5L4800A, and MCM5V4800A = 11 mW
(Max, TTL Levels)
MCM54800A = 5.5 mW (Max, CMOS Levels)
MCM5L4800A and MCM5V4800A = 1.1 mW (Max, CMOS Levels)
Battery Backup Power Dissipation:
MCM5L4800A = 1.7 mW (Max, Battery Backup Mode, tRC = 125 ~s)
Self Refresh Power Dissipation:
MCM5V4800A = 1.1 mW (Max, Self Refresh Mode)

CASE 810

Z PACKAGE
PLASTIC
ZIG-ZAG IN-LINE
CASETBD

PIN ASSIGNMENT
400-MILSOJ

100-MILZIP

VCC
DOD

DO?

DOl

D06

D02

DOS

D03

D04

NC

W
RAS

VSS

CAS

G
Ne

A9R

AB

AD

A7
A6

G

VCC

DOS
DO?
VSS

Vee

DOD

lD
11

D02

12
13

NC
RAS

14
15
16
17

A4

AD

VSS

A2

18
19
20
21

Vce
A4

PIN NAMES

This document contams informatIOn on a new product. Specifications and Information herein are subject to change Without notice.

MOTOROLA MEMORY DATA
2-175

D03

W
A9R
Al
A3
VSS

24
25
26
27

A8

DOl

22
23

A6

AO-AS, A9R .......... Address Inputs
RAS ............ Row Address Strobe
CAS ......... Column Address Strobe
W........................ Write Input
G . . . . . . . . . . . . . . . . . . .. Output Enable
DOO-DO? ......... Data InpuVOutput
VCC ........... Power Supply (+ 5 V)
VSS ........................ Ground
NC ...................... No Connect

CAS

D06

AS
A3

2

DQ4

28

AS
A7
NC

MCM&4800A-MCM5L4800A-MCM5V4800A

•

BLOCK DIAGRAM
DOo-D07

IN

CAS

t---IH-G

AD
AI
A2
A3
A4
A5
A6
A7
AS

COLUMN
DECODER
SENSE AMP
1/0 GATING

A9R
RAS

/
_VCC
_VSS

/

/
ABSOLUTE MAXIMUM RATING (See Note)
Rating

Power Supply Voltage
Voltage Relative to VSS for Any Pin Except VCC

Symbol

Value

VCC

-I to +7

V

Vin, Vout

-I to +7

V

Unit

Data Out Current

lout

50

rnA

Power Dissipation

Po

600

mW

Operating Temperature Range

TA

Ot070

°c
°c

Storage Temperature Range
-55to+150
Tsto
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

MOTOROLA MEMORY DATA

2-176

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any vottage higher than maximum rated voltages to this high-impedance
circu~.

MCM54800A-MCM5L4800A-MCM5V4800A

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, T A = 0 to 70 o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

Supply Voltage (Operating Voltage Range)

0

0

VSS

0

Logic High Voltage, All Inputs

VIH

2.4

-

S.5

V

1

Logic Low Voltage, All Inputs Except DOO-D07

VIL

-1.0'

-

O.B

V

1

Logic Low Voltage, DOO-D07

VIL

- OS'

-

O.B

V

1

Symbol

Min

Max

Unit

Notes

mA

2,3

mA
mA

2,3

mA

2,3

'- 2.5 V at pulse width" 20 ns
"- 2.0 V at pulse width" 20 ns

DC CHARACTERISTICS
Characteristic
VCC Power Supply Current
MCM54BOOA-70, MCM5L4BOOA-70, and MCM5V4800A-70, tRC = 130 ns
MCM54BOOA-BO, MCM5L4BOOA-BO, and MCM5V4800A-BO, tRC =150 ns
MCM54BOOA-l0, MCM5L4BOOA-l0, and MCM5V4800A-l0, tRC =lBO ns

ICCl

VCC Power Supply Current (Standby) (RAS = CAS = VI H)

ICC2

VCC Power Supply Current During RAS Only Refresh Cycles (CAS =VIH)
MCM54BOOA-70, MCM5L4BOOA-70, and MCM5V4800A-70, tRC =130 ns
MCM54BOOA-BO, MCM5L4BOOA-BO, and MCM5V4800A-BO, tRC = 150 ns
MCM54BOOA-l0, MCM5L4800A-l0, and MCM5V4800A-l0, tRC = lBO ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle (RAS =VIU
MCM54BOOA-70, MCM5L4BOOA-70, and MCM5V4800A-70, tpc = 45 ns
MCM54BOOA-BO, MCM5L4BOOA-BO, and MCM5V4800A-BO. tpc =50 ns
MCM54B00A-l0, MCM5L4BOOA-l0, and MCM5V4800A-l0, tpc = SO ns

ICC4

MCM54BOOA
VCC Power Supply Current (Standby) (RAS =CAS =VCC - 0.2 V)
MCM5L4800A and MCM5V4BOOA

ICC5

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM54B00A-70, MCM5L4BOOA-70, and MCM5V4800A-70, tRC = 130 ns
MCM54BOOA-BO, MCM5L4BOOA-BO, and MCM5V4800A-BO, tRC =150 ns
MCM54B00A-l0, MCM5L4BOOA-l0, and MCM5V4800A-l0, tRC = lBO ns

ICCS

VCC Power Supply Current, Battery Backup Mode-MCM5L4800A Only
(tRC =125 IJ.S~RAS =llJ.S; CAS =CAS Before RAS Cycle or 0.2 V;
AO-AB, A9R, W, D =VCC - 0.2 V or 0.2 V)
VC~wer

-

-

105
90
BO
2
105
90
BO
75
S5
SO
1.0
200

mA

I1A
mA

2

2,4

-

-

105
90
BO

ICC7

-

300

I1A

ICCB

-

200

I1A

Input Leakage Current (0 V" Vin" 7.0 V)

Ilkalil

-10

10

Output Leakage Current (0 V,; Vout'; 7.0 V, Output Disable)

-10

10

I1A
I1A

Output High Voltage (IOH

IlkalOl
VOH

2.4

-

V

Output Low Voltage (1m

VOL

-

0.4

V

Symbol

Max

Unit

Notes

Cin

5

pF

5

Supply Current, Self Re.!.e~ Mode-MCM5V4BOOA Only
(RAS =CAS =VIL; AO-AB, A9R, W, G =VCC - 0.2 V or 0.2 V;
DOO-D07 = VCC - 0.2 V, 0.2 V, or Open)

=- 5 mAl
= 4.2 mAl

CAPACITANCE (f = 1.0 MHz, TA = 25°C, VCC = 5 V, periodically sampled, not 100% tested)
Parameter
AD-AB,A9R

Input Capacitance

RAS, CAS, W, G

7

7
pF
5
Input/Output CapaCitance (CAS = VIH to Disable Output)
DOD-D07
Coul
NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading. Maximum currents are at the specified cycle time (min) with the output open.
3. Column address can be changed once or less while RAS = VIL and CAS = VIH.
4. tRAS (max) = 1 I1s is only applied to refresh of battery-back up. tRAS (max) = 10 IJ.S is applied to functional operating.
5. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = lat/aV.

MOTOROLA MEMORY DATA
2-177

•

MCM54800A-MCM5L4800A-MCM5V4800A

II

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70 o e, Unless Otherwise Noted)
READ, WRITE, AND READ-MODIFY-WRITE CYCLES (See Notes 1,2,3, and 4)

Parameter

MCM54800A-70
MCM5L4800A-70
MCM5V4800A-70

Symbol
Std

Alt

Min

Max

MCM54800A-80
MCM5L4800A-80
MCM5V4800A-80
Min

Max

MCM54800A-l0
MCM5L4800A-l0
MCM5V4800A-l0
Min

Unit

Notes

-

ns

5

ns

5

Max

Random Read or Write Cycle Time

tRELREL

tRC

130

-

150

-

180

Read·Modify-Write Cycle Time

tRELREL

tRWC

185

-

205

-

245

Page Mode Cycle Time

tCELCEL

tpc

45

-

50

-

60

Page Mode Read-Modify-Write Cycle
Time

tCELCEL

tpRWC

100

-

105

-

125

Access Time from RAS

tRELQV

tRAC

-

70

-

80

ns

6,8,9

tCELQV

!cAC

-

20

-

20

25

ns

6,8

Access Time from Column Address

tAVQV

tAA

35

40

50

ns

6,9

Access Time from CA,S Precharge

tCEHQV

45

-

100

Acc!'ss Time from CAS

55

ns

6

CAS to Output in' Low-Z

-

0

-

ns

6

Output Buffer Turn-Off Delay

7

Transition Time (Rise and Fall)

ns
ns

tCPA

-

40

-

tCELQX

tCLZ

0

-

0

tCEHQZ

tOFF

0

20

0

20

0

20

ns

tT

IT

3

50

3

50

3

50

ns

-

ns

RAS Precharge Time

tREHREL

tRP

50

-

60

RAS Pulse Width

tRELREH

tRAS

70

10,000

80

10,000

100

10,000

ns

RAS Pulse Width (Page Mode)

tRELREH

tRASP

70

100,000

80

100,000

100

100,000

ns

RAS Hold Time

tCELREH

tRSH

20

-

20

CAS Hold Time

tRELCEH

tCSH

70

-

80

CAS Pulse Width

tCELCEH

tCAS

20

10,000

20

10,000

25

10,000

RAS to CAS Delay Time

tRELCEL

tRCD

20

50

20

60

25

75

ns

8

tRELAV

tRAD

15

35

15

40

20

50

ns

9

CAS to RAS Precharge Time

tCEHREL

tCRP

5

-

5

10

tCEHCEL

tcp

10

-

10

10

-

ns

CAS Precharge Time (Page Mode
Only)

-

RAS Hold Time From CAS Precharge
(Page Mode Only)

tCEHREH

tRHCP

40

-

45

-

55

-

ns

Row Address Setup Time

tAVREL

tASR

0

-

0

tRAH

10

Column Address Setup Time

tAVCEL

tASC

0

-

Column Address Hold Time

tCELAX

tCAH

15

-

15

20

Column Address Hold Time
Referenced to RAS

tRELAX

tAR

55

-

60

-

75

-

ns

tRELAX

-

0

Row Address Hold Time

Column Address to RAS Lead Time

tAVREH

tRAl

35

-

40

-

50

-

ns

RAS to Column Address Delay Time

10
0

-

-

70

25
100

15
0

-

ns
ns
ns

ns

ns
ns
ns
ns

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 100 Jls is required after power·up followed by 8 RAS only refresh cycles or 8 CAS before RAS refresh cycles, before proper
device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VI H) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range (0 ,,; T A"; 70°C) is assured.
6. Measured with a current load equivalent to 2 TTL (- 200 JlA, + 4 rnA) loads and 100 pF with the data output trip pOints set at VOH = 2.0 V
and VOL = 0.8 V.
7. tOFF (max) and tGZ (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage
levels.
8. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by !cAC.
9. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
2-178

MCM54800A-MCM5L4800A-MCM5V4800A

READ, WRITE, AND READ·MODIFY·WRITE CYCLES (Continued)

Parameter

MCM54800A·70
MCM5L4800A·70
MCM5V4800A·70

Symbol

MCM54800A·80
MCM5L4800A-IIO
MCM5V4800A·80

MCM54800A·10
MCM5L4800A·10
MCM5V4800A·10

Unit

Notes

SId

All

Min

Max

Min

Max

Min

Max

Read Command Setup Time

tWHCEL

tRCS

0

-

0

0

tCEHWX

tRCH

0

-

0

Read Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

-

0

-

0

Write Command Hold Time

leELWH

twCH

15

-

20

tRELWH

twCR

55

-

15

Write Command Hold Time
Referenced to CAS

60

-

75

15

-

20

20

25

-

ns

Read Command Hold Time

-

20

-

25

-

ns

-

0

ns

11

20

-

ns

11

75

-

ns

-

16
128

ms

Write Command Pulse Width

twLWH

twP

15

Write Command to RAS Lead Time

twLREH

tRWL

20

Write Command to CAS Lead Time

twLCEH

20

Data in Setup Time

tDVCEL

leWL
tDS

Data in Hold Time

tCELDX

tDH

Data in Hold Time Referenced to RAS

tRELDX

Refresh Period
MCM54800A
MCM5L4800A and MCM5V4800A

tRVRV

-

15

-

15

tDHR

55

60

tRFSH

-

16
128

-

0

0

-

16
128

0

ns

10

ns

10

ns
ns
ns
ns

Write Command Setup Time

twLCEL

twcs

0

-

0

-

ns

12

leELWL

50

50

-

60

ns

12

RAS to Write Delay

tRELWL

leWD
tRWD

-

0

CAS to Write Delay

100

-

110

135

ns

12

Column Address to Write Delay

tAVWL

tAWD

65

70

ns

12

CAS Precharge to Write Delay

tCEHWL

lePWD

70

-

-

90

ns

12

CAS Setup Time for CAS Before RAS
Cycle

tRELCEL

leSR

5

-

5

CAS Hold Time for CAS Before RAS
Cycle

tRELCEH

tCHR

15

-

15

RAS Precharge to CAS Active Time

tREHCEL

tRPC

0

-

0

CAS Precharge Time (CAS Before
RAS Counter Test)

tCEHCEL

tCPT

40

40

-

50

RAS Hold Time Referenced to G

-

-

10

-

20

-

-

20

-

25

ns

20

-

25

-

ns

0

20

0

25

ns

IGLREH

tROH

10

G Access Time

tGLQV

tGA

-

G to Data Delay

IGLHDX

tGD

20

-

Output Buffer Turn-Off Delay Time
from

IGHQZ

IGz

0

20

a

20

75

-

G Command Hold Time

-

85
5
20
0

-

ns
ns
ns
ns
ns
6
7

20
20
25
ns
tGH
twLGL
Output Disable Setup Time
0
ns
0
0
tGLCEL
tGDS
NOTES:
10. Either tRRH or tRCH must be satisfied for a read cycle.
11. These parameters are referenced to CAS leading edge in early write cycles and to Wleading edge in late write or read-write cycles.
12. twCS. tRWD. leWD. lePWD. and tAWD are not restrictive operating parameters. They are included in thedatasheetas electrical characteristics only. If twcs 2: twcs (min). the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout
the entire cycle.lftCWD 2:leWD (min). lePWD 2:tCPWD (min). tRWD2:tRWD (min). andtAWD 2:tAWD (min). the cycle is aread-modify-write
cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied. the condition of the data
out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
2·179

•

MCM54800A-MCM5L4800A-MCM5V4800A

..

SELF REFRESH CYCLE

Parameter

MCM54800A-70
MCM5L4800A-70
MCM5V4800A-70

Symbol

MCM54800A-80
MCM5L4800A-80
MCM5V4800A-80

MCM54800A-10
MCM5L4800A-10
MCM5V4800A-10

Unit

SId

Alt

Min

RAS Pulse Width (CAS Before RAS
Self Refresh, MCM5V4800A Only)

tRELREHS

tRASS

100

-

100

-

100

-

!IS

RAS Prechange Time (CAS Before
RAS Self Refresh, MCM5V4800A
Only)

tREHRELS

tRPS

130

-

150

-

180

-

ns

CAS Hold Time (CAS Before RAS
Self Refresh, MCM5V4800A Only)

tREHCEH

tcHS

-50

-

~O

-

-70

-

ns

Max

Min

MOTOROLA MEMORY DATA
2-180

Max

Min

Max

Notes

MCM54800A-MCM5L4800A-MCM5V4800A

READ CYCLE
~--------------------tRC--------------------~

/4------------- t AAS -------------t

RAS

V1H -

;.------t AA ------*I

V1L -

--+-----------1
__+-----+-t ASH ---+----.j

~--------- t CSH

CAS

v1H -

.J,:----++------"""*""'"""

",o---+t CAS -------..j ,--'--'--=10--------

V1L -

AO-A8

V1H V1L -

A9R

v1H V1L -

Vi

V1H V1L -

G

V1H V1L -

OOO-OQ7 VOH VOL -

OPEN

MOTOROLA MEMORY DATA
2-181

•

MCM54800A-MCM5L4800A-MCM5V4800A

•

EARLY WRITE CYCLE

RAS

V1H -

1--------tRC --------+1
1 + - - - - - tRAS - - ' - - - - - + I
_ _ _~ i+---tAR - - - + I

V1L -

CAS

V1H V1L -

DQI}-DQ7

V1H -

V1L -

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX)
I~DS:l~HR~
(XXXxxxxxn DA~XXXXXXXXXXXXXXXXX

MOTOROLA MEMORY DATA

2-182

MCM54800A-MCM5L4800A-MCM5V4800A

W

G

OQO-DQ7

V1H V1L V1H V1L V1H VIL -

MOTOROLA MEMORY DATA
2-183

MCM64800A·MCM6L4800",·MCM6V4800A~

READ·MODIFY·WRITE CYCLE

D

~---------------------------tRWC------------------------~

AO-A8

A9R

G v1H vlL - _ _ _..-_ _ _ _ _ _...,..._~-+--.J

i"'1.0--------D~Q7 VIH NOH VIL IVoL -

t

RAC

+------101

-----------+---.~"--l<~--lL..::L~_+-_~::.......--lL..::L...:.I..-+!-+-_.....:z~~:..-..:.'--'o£..:l"+-lf---':t:...lt.....:.~"--l<--lL--lL..:>I..

DOC-D07 VIH -

VIL -

-->L-><.->L..-"-';;' .....' - -_ _--=T

"'---"'--"-J ""'--_---:T '<.-"---"->1 ........_ _~ "-"-''-''''--''-''--''--><

MOTOROLA MEMORY DATA
2-186

MCM54800A-MCM5L4800A-MCM5V4800A

•

FAST PAGE MODE READ·MODIFY·WRITE CYCLE

Ao-Ml

VIH Vll -

A9A

VIH Vll -

Vi

VIH VIl-

a

VIH Vll -

DATA OUT

DATA IN

DATA OUT

DATA IN

MOTOROLA MEMORY DATA

2-187

DATA OUT

DATA IN

MCM54800A-MCM5L4800A-MCM5V4800A

III

RAS ONLY REFRESH CYCLE

~-------------------tRC------------------~
~--------- t RAS ----------~

RAS IH - - - - - - - : : i
CAS IH -

__ V

VIL -

__ V

~"""'"'<:"":l!:__-H_----------------------_t:"'~.__----

V IL - "-"'-"''''---''

tAs::i

r

AD-A8,A9R ~II: =XXXMAD~~~SS)1
~~~~~~~~~~~A7

DOD-DO?

)>------------ HIGH Z

VOH VOL- _ _ _ _..J.

CAS BEFORE RAS SELF REFRESH CYCLE (MCM5V4800A ONLY)
~-----------t RAS<>-----------~O>I

DOD-DO?

)>------------ HIGH Z

VOH VOL- _ _ _ _..J.

MOTOROLA MEMORY DATA

2-188

MCM54800A-MCM5L4800A-MCM5V4800A

HIDDEN REFRESH CYCLE (READ)

~---------------tRC--------------~.----------tRC------~

RAS

V 1H -

'""~---

t RAS - - - - - . , ..ic------"3lfoo---- t RAS ------I jc----"'-.
\ 1 4 - - tAR -

---"'-.

CAS
V1L -

AO-AS

A9R

V 1H V1L -

V1H V 1L -

W

V 1H V1L -

G

J~XXxxXXXxxXXXXXXXX
I

I

V1H V 1L -

VOH -

DATA OUT

DOD-DO?
VOL -

MOTOROLA MEMORY DATA
2-189

•

MCM~A·MCM5~A·MCM~~A

•

HIDDEN REFRESH CYCLE (WRITE)
1 4 - - - - - t A C - - - - - - t o - - - - - - -t A C - - - - - t

AG-A8 V1H V 1L

ABA

~A~A
A~

~:: =

~

ADD1AESS

tAAH

~~~XX"""""'7M.XXXX~X~XX<"""'7t'""X'7<"'""l'<"XX"""""""'XXXXXX.,......,......~XX~X....,....XXXXX~~XX"""l<-:-X

Itw~*t~1\l

•:::=~ ~XXXXXXXXXXXXXXXXX)(
G

DQG-DQ7

~:: =L--"--"-~......""-"'-"'-9'----I----I-----------'p'_i':.....<-->L-"-->L-->L--"-...lL-......""-~

I

D(DATAIN)

tD~

tDH}z

~: =XXXX'x'XXXXM-VA-UDDAT-A

I;:

IDHR

~XX~X7r7lXX~X'7r7X~XX~X~XX~X"1r7X

--

Q(DATAOU1) VOH - - - - - - - - - - - - - HIGHZ - - - - - - - - - - - - - - - VOL -

MOTOROLA MEMORY DATA
2-202

MCM511000AeMCM51L1000A

READ-WRITE CYCLE

_VIHRAS
VIL

CAS VIHVIL -

ADDRESSES VIH VIL -

Q(DATAOUT) VOH - - - - - VOL -

FAST PAGE MODE READ CYCLE
_____~

~~-------------------tRASP-------------------

RAS VIHVIL -

_VIHCAS
VIL

ADDRESSES VIH VIL -

_ VIHW
VIL

Q (DATA OUT)

V -

OH _
VOL

--------------------KJX
"'-.::.:..:::..:-.:;r

MOTOROLA MEMORY DATA
2-203

lEI

MCM511000A-MCM51L1000A

..

FAST PAGE MODE EARLY WRITE CYCLE

VIH ADDRESSES
VIL

WVIHVIL -

D (DATA IN) VIH VIL -

'--''--'''--'''--'''-'''-'''-+---I---II--+"''-"'''--I---+----i..........,'--I---I--~'--'''-'''-''--''................- '

-'-~~"-lL...l.'-:./ ~----~

Q(DATAOUT) VOH - - - - - - - - - - - - - - - - - H I G H Z - - - - - - - - - - - - - - - VOL -

FAST PAGE MODE READ-WRITE CYCLE

v -

ADDRESSES IH _
VIL

D(DATA IN)

v -

IH_
VIL

--"-"'-"'"""",,-.lL.-"--"--"--:-"-~,

v -

Q(DATAOUT) OH _
VOL

MOTOROLA MEMORY DATA
2-204

MCM511000A· MCM51 L1000A

RAS ONLY REFRESH CYCLE
(Wand A9 are Don't Care)

~-------------------tRC------------------------~

AOTOAB VIHVIL

Q(DATAOUT) VOH
VOL

=----------------

HIGH Z

CAS BEFORE RAS REFRESH CYCLE
(Wand AO 10 A9 are Don'l Care)

~------------------tRC ----------------------~
~------------tMS------------~

~-+_t-tCSR
~------

Q (DATA OUT) VOH VOL - - - - - - " 1

tCHR

------~

>------------

HIGH Z

MOTOROLA MEMORY DATA
2-206

r-------------

•

MCM511000A-MCM51 L1000A

•

HIDDEN REFRESH CYCLE (READ)

ADDRESSES VIH Vll-

Vi VIH~....lL.....lL..-¥-.lL...lL...;"

Vil -

---------+-<1

Q (DATA OUT) VOH VOl-

HIDDEN REFRESH CYCLE (EARLY WRITE)

ADDRESSES VIH Vil -

W VIHVil - '--"'-"'-"'-1'-"-"--"-"f--!-+----T'......'-"'-"-""'-"-......-"--"-......"'-""-.............'-"'--"..........

Q(DATAOUT) VOH
VOL

=------------

HIGHZ - - - - - - - - - - - - - - - -

MOTOROLA MEMORY DATA
2-206

MCM511000A-MCM51L1000A

•

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

READ CYCLE
Q(DATAOUT) VOH -_ -------VOL
W

VIHVIL -

:....>:~~~.:.I_.lL....:~~'__loI:~

EARLY WRITE CYCLE

Q(DATAOUT) VOH -_ -------------+---1+- HIGHZ ----11-+-+-----VOL

READ-WRITE CYCLE

Q(DATA OUT) VOH -_ - - - - - - HIGH Z----t--I-++-<-->+--><--"--"--"--"-'1"---+---;--------'1-''-;''--'''--'''-'''-''-''-''-''-''....................

I

D(DATA IN)

tD~

tDH~

~

~I~ =XXXXYXXXXM-VA-UDDA-JA-"":llroo<'--><'""""",,--"---"---"---"---"--",

Q (DATA OUT)

V -

OH _
VOL

--------------------<1

MOTOROLA MEMORY DATA
2-219

•

MCM511oooB-MCM51L1000B

III

RAS ONLY REFRESH CYCLE
(Wand AS are Don't Care)

~------------------tRC------------------------~

Q(DATAOUT) VOH - - - - - - - - - - - - - - - HIGHZ - - - - - - - - - - - - - VOL -

CAS BEFORE RAS REFRESH CYCLE
(Wand AD to A9 are Don't Care)

1-------------------tRc
~------------ t RAS - - - - - - - - - . . 1

~-I_+-tCSR

1------- tCHR - - - - - i

Q (DATA OUT) VOH VOL - - - - - " " ' 1

>------------ HIGH Z

MOTOROLA MEMORY DATA
2-220

MCM511000B.MCM51L1000B

HIDDEN REFRESH CYCLE (READ)

ADDRESSES VIH VIL -

W VIH~~...l£...+~>L...:Y

VIL

---------+-<1

Q(DATAOUT) VOH VOL -

HIDDEN REFRESH CYCLE (EARLY WRITE)

ADDRESSES VIH VIL -

Q(DATAOUT) VOH

=------------

HIGHZ - - - - - - - - - - - - - - - -

VOL

MOTOROLA MEMORY DATA
2-221

lEI

MCM511000B-MCM51L1000B

..

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

READ CYCLE
VOH - _ _ _ _ _ _ _ __
Q(DATAOUT)
_
VOL

iii VIHVIL -

'--"'--"'--"'--"'--"'--"--"--"--"....::.t.~

EARLY WRITE CYCLE

VOH- _ _ _ _ _ _ _ _ _ _ _ _ _~--~-

_ _ _ _-+~~-------

Q (DATA OUT)

HIGH Z
VOL

READ-WRITE CYCLE

Q (DATA OUT) VOH
VOL

=-------

HIGH Z

----r-----i+<1

leWD

o(DATA IN)

VIH
VIL

IWp

=><~X~XX""1":""7'XXt"'"?<'""X~XX--":-,X~XX.."......,,XX"""""'X~XX""1":""7'X§VAUiDA~TA~XXX~X~X-,.::-rX
IDS

MOTOROLA MEMORY DATA

2-222

IDH

MCM511000B- MCM51 L1000B

DEVICE INITIALIZATION

WRITE CYCLE

On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the RAM. During an extended inactive
state (greater than 8 milliseconds with the device powered up),
a wake up sequence of eight active cycles is necessary to ensure proper operation.

The ten address pins on the device are time multiplexed at
the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 1O-bit address fields. A total of twenty address bits, ten
rows and ten columns, will decode one of the 1,048,576 bit locations in the device. RAS active transition is followed by CAS
active transition (active = VIL, tRCJLI!linimum) for all read or
write cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system designer flexibility in setting up the external addresses into the
RAM.
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are two other variations ·in addressing the 1M RAM:
RAS only refresh cycle and CAS before RAS refresh cycle.
Both are discussed in separate sections that follow.

The user can write to the DRAM with any offour cycles: early
write, late write, page mode early write, and page mode readwrite. Early and late write modes are discussed here, while
page mode write operations are covered in another section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of IN to active
(VIL). Early and late write modes are distinguished by the active transition of IN, with respect to CAS. Minimum active time
tRAS and tCAS, and precharge time tRP apply to write mode,
as in the read mode.
An early write cycle is characterized by IN active transition at
minimum time twcs.Pefore CAS active transition. Data in (D)
is referenced to CAS in an early write cycle. RAS and CAS
clocks must stay active fortRWL and tCWL' respectively, after
the start of the early write operation to complete the cycle.
Q remains High Z throughout an early write cycle because
IN active transition precedes or coincides with CAS active
transition, keeping data-out buffers disabled. This feature can
be utilized on systems with a common I/O bus, provided all
writes are performed with early write cycles, to prevent bus
contention.
A late write cycle occurs when IN active transition is made
after CAS active transition. Vii active transition could be
delayed for almost 10 microseconds after CAS active transition, (tRCD + tCWD tRWL + 2tT) ., tRAS, if other timing minimums (tRCD, tRWL, and tTl are maintained. 0 is referenced to
Vii active transition in a late write cycle. Output buffers are enabled by CAS active transition but 0 may be indeterminatesee note 16 of AC operating conditions table. RAS and CAS
must remain active for tRWL and tCWL' respectively, after Vii
active transition to complete the write cycle.

READ CYCLE

READ-WRITE CYCLE

The DRAM may be read with four different cycles: "normal"
random read cycle, page mode read cycle, read-write cycle,
and page mode read-write cycle. The normal read cycle is outlined here, while the other cycles are discussed in separate
sections.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (IN) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex
window. However, CAS must be active before or allRCD maximum to guarantee valid data out (0) at tRAC (access time from
RAS active transition). If the tRCD maximum is exceeded,
read access time is determined by the CAS clock active transi_
tion (teAd.
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. IN must remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data at that bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitryforthe next active
cycle. 0 is valid, but not latched, as long as the CAS clock is
active. When the CAS clock transitions to inactive, the output
will switch to High Z.

A read-write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically a
late write cycle, as discussed in the WRITE CYCLE section,
except Vii must remain high for tCWD minimum after the CAS
active transition, to guarantee valid Q before writing the bit.

ADDRESSING THE RAM

+

PAGE MODE CYCLES
Page mode allows fast successive data operations at all
2048 column locations on a selected row of the 1M dynamic
RAM. Read access time in page mode (tCAC) is typically half
the regular RAS clock access time, tRAC. Page mode operation consists of keeping RAS active while toggling CAS between VIH and.'{tLThe row is latched by RAS active transition, while each CAS active transition allows selection of a new
column location on the row.
A page mode cycle is initiated by a normal read, write, or
read-write cycle, as described in prior sections. Once the
timing requirements for the first cycle are met, CAS transitions
to inactive for minimum of tcp, while RAS remains low (VIU.
The second CAS active transition while RAS is low initiates the
first page mode cycle (tpc or tPRWC). Either a read, write, or
read-write operation can be performed in a page mode cycle,
subject to the same conditions as in normal operation
(previously described). These operations can be intermixed in
consecutive page mode cycles and performed in any order.
The maximum number of consecutive page mode cycles is
limited by tRASp. Page mode operation is ended when RAS
transitions to inactive, coincident with or following CAS
inactive transition.

MOTOROLA MEMORY DATA
2-223

•

MCM611000B-MCM61 L1000B

•

REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge degrades with
time and temperature, thus each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in
the MCM511 OOOB require refresh every 8 milliseconds while
refresh time for the MCM51 L1OOOB is 64 milliseconds ..
Refresh is accomplished by cycling through the 512 rowaddresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM511 OOOB and 124.8 microseconds
for the MCM51 L1000B. Burst refresh, a refresh of all512 rows
consecutively, must be performed every 8 milliseconds on the
MCM511000B and 64 milliseconds on the MCM51Ll000B.
A normal read, write, or read-write operation to the RAM will
refresh all the bits (2048) associated with the particular row decoded. Three other mehtods of refresh, RAS-only refresh,
CAS before RAS refresh, and Hidden refresh are available
on this device for greater system flexibility.

Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1).
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CAS before RAS refresh counter test. This test is performed with a read-write operation. During the test, the internal
refresh counter generates the row address, while the external
address supplies the column address. The entire array is refreshed after 512 cycles, as indicated by the check data written
in each row. See CAS before RAS refresh counter test
cycle timing diagram.
The test can be performed after a minimum of eight CAS
before RAS initialization cycles. Test procedure:
1. Write "O"s into all memory cells with normal write mode.
2. Select a column address, read "0" out and write "1" into the
cell by performing the CAS before RAS refresh counter
test, read-write cycle. Repeat this operation 512 times.
3. Read the "1 "s which were written in step 2 in normal read
mode.
4. Using the same starting column address as in step 2, read
"I" out and write "0" into the cell by performing the CAS before RAS refresh counter test, read-write cycle. Repeat
this operation 512 times.
5. Read "O"s which were written in step 4 in normal read mode.
6. Repeat steps 1 to 5 using complement data.

RAS-Only Refresh
RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(VIH) throughout the cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.
CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order actives an internal refresh counter that generates the row address to be refreshed. External
address lines are ignored during the automatic refresh cycle.
The output buffer remains at the same state it was in during the
previous cycle (hidden refresh).
Hidden Refresh

MEMORY CYCLE

-

\

Q

-

HIGHZ

I

\

CAS BEFORE RAS
REFRESH CYCLE

CAS BEFORE RAS
REFRESH CYCLE

I'

VALID DATA OUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA
2-224

)-~

MCM611000B-MCM61L1000B

TEST MODE
Internal organization of this device (256Kx4) allows it to be
tested as if it were a 256Kx1 DRAM. Only nine of the ten addresses (AO-AS) are used in test mode; A9 is internally disabled. A test mode write cycle writes data, D (data in), to a bit in
each of the four 256Kx1 blocks (80-83), in parallel. A test
mode cycle reads a bit in each of the four blocks. If data is the
same in all four bits, Q (data out) is the same as the data in
each bit. If data is not the same in all four bits, Q is high Z. See
truth table and test mode block diagram.
Test mode can be used in any timing cycle. including page

mode cycles. The test mode function is enabled by holding the
"IF" pin on "super voltage" for the specified period (trES.
tTEHR. trEHe; see TEST MODE CYCLE).
"Super voltage" = Vee + 4.5 V
where
4.5 V < Vee < ;5.5 V and maximum voltage = 10.5 V.
A9 is ignored in test mode. In normal operation, the "TF" pin
must either be connected to Vil. or left open.

Test Mode Truth Table
0
0
1

BO
0
1

-

I

I

B1
0
1

I

I

B2
0
1

Any Other

I

I

B3
0
1

Q

0
1
High-Z

TEST MODE BLOCK DIAGRAM

VIH VIL

TF VIH(TF) VIL(TF) -

TEST MODE BLOCK DIAGRAM

(AS)

TF
Q

NORMAL

o
TFo-l-I"'"1_~-.J

MOTOROLA MEMORY DATA
2-225

•

MCM511000B-MCM51L1000B

ORDERING INFORMATION
(Order by Full Part Number)

111 T

MCM 511000Bor51Ll000BX X XX XX

Motorola Memory Prefix

T

I

Part Number _ _ _ _ _ _ _---1,

Shipping Method (R2 = Tape & Reel, Blank =, Rails)
Speed (60 = 60 ns, 80 = 80 ns)
Temperature (Blank = 0 to 70°C)
Package (J = 300 mil SOJ, Z = Plastic ZIP)

Commercial Temperature Range 0 to 70°C
Full Part Number

MCM511000BJ60

MCM511000BJ60R2

MCM511000BZ60

MCM511000BJ80

MCM511000BJ80R2

MCM511000BZ80

MCM51Ll000BJ60

MCM51Ll000BJ60R2 MCM51Ll000BZ60

MCM51 L1 000BJ80

MCM51 L 1000BJ80R2 MCM51 L 1OOOBlBO

MOTOROLA MEMORY DATA

2-226

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM511001A

1 M x 1 CMOS Dynamic RAM
Nibble Mode
. P PACKAGE
. -300 MIL PLASTIC
CASE7U1A

The MCM511001A is a 1.0" CMOS high-speed, dynamic random access memory. It is
organized as 1,048,576 one-bit words and fabricated with CMOS silicon-gate process
technology. Advanced circuit design and fine line processing provide high performance,
improved reliability, and low cost. The fast nibble mode feature allows high-speed serial
access of up to 4 bits of data.
The MCM511001A requires only 10 address lines; row and column address inputs are
multiplexed. The device is packaged in a standard 300-mil dual-in-line plastic package
(DIP), a 300-mil SOJ plastic package, and a l00-mil zig-zag in-line plastic package (ZIP).
•
•
•
•
•
•
•
•
•
•
•

•

•

~

JPACKAGE
300 MIL SOJ
CASE 822

~-

Three-State Data Output
Common 110 with Early Write
Fast Nibble Mode
Test Mode
TTL-Compatible Inputs and Output
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
512 Cycle, 8 ms Refresh
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access TIme (tRAC): MCM511001A-70=70 ns (Maximum)
MCM511001A-80=80 ns (Maximum)
MCM511001A-10=100 ns (Maximum)
low Active Power Dissipation: MCM511001A-70=440 mW (Maximum)
MCM511001A-80=385 mW (Maximum)
MCM511001A-l0=330 mW (Maximum)
low Standby Power Dissipation: 11 mW (Maximum, TTL levels)
5.5 mW (Maximum, CMOS Levels)

ZPACKAGE
- . PLASTIC
ZIG-ZAG IN-LINE
CASE 836

PIN NAMES
AO-A9 . . . . • . . . . . . Address Input
o . . . . . . . . . . . . . . . . Data Input
Q • • . . • . • . • . . . . . . Data Output
W. . . . . . . . . . . Read/Write Enable
RAS . . . . . . . . Row Address Strobe
~ . . . . . . Column Address Strobe
VCC . . . . . . . . . . . . Power (+5V)
VSS . . . . . . . . . • . . . . . . Ground
TF. . . . . . . . . . Test Function Enable
NC . . . . . . . . . . . . . No Connection

ZIG-ZAG IN-LINE

r"""'I
SMALL OUTLINE
DUAL-IN-L1NE
0

PIN
ASSIGNMENT

W

I.

I

26

W
im

2

25

n

3

24

m

0

18 pVSS
17 pn

VSS

16 pCAS

TF

4

23 PNC

TF

15

A9

NC

5

22 PAD

AD

14

A8

AI

13 A7

m

AD ='=1 2
3 :== CAS
n ==14
5 1== Vss
D ==16
7 :== Vi
HAl ==1 8
D 1== TF
NC ==1
II!!. NC
ill-AD ==112
A2 H:== AI

A2

12 PA6

AD

A3

11 PA5

AI

VCC

10 PA4

18 PA8
10

A2

11

16 PA6

A3

12

15 PA5

VCC

13

MOTOROLA MEMORY DATA
2-227

17 PA7

14 PA4

IJi

151 VCC ==116

A3

A5 g:== A4
A7

IJ~ A6

I!!. I

--120

~A8

MCM511001A

..

BLOCK DIAGRAM

AD
A1
A2
A3

A4
A5
A6
A7

A8
A9

ABSOLUTE MAXIMUM RATINGS

(See Notel

Symbol

Valua

Unit

VCC

-1 to +7

V

Vin, Vout

-1 to +7

V

Vin(TFI

-1 to +10.5

V

Deta Out Current

lout

50

mA

Power Dissipation

PD

600

mW

TA

Oto+70

·C

Tstg

-55 to +150

·C

Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin Except VCC
Teet Function Input Voltage

Opereting Ternpereture Range
Storege Temperature Range

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
excesdad. Functional operation should be restrictad to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

MOTOROLA MEMORY DATA

2-228

This device oonteins circuitry to protect the
inputs ageinst damage due to high etatic
voltagee or electric fielda; however, It is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high-imped-

ance circuit.

MCM511001A

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ±10%, TA=O to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

-

6.5

V

1

-

0.8

V

1

10.6

V

1

Unit

Notes

mA

2

LogiC High Voltage, All Inputs

VIH

2.4

Logic Low Voltage, All Inputs

VIL

-1.0

VIH (TF)

VCC+4.6

Test Function Input High Voltage

DC CHARACTERISTICS
Symbol

Characteristic
VCC Power Supply Currant
MCM611OO1A-70, tRC=13O ns
MCM611OO1A-80, tRC = 150 ns
MCM511oo1A-l0, tRC=l80 ns

ICCl

VCC Power Supply Currant (Standby) (~=CAS=VIH)

ICC2

VCC Power Supply Currant During ~ only Refrash Cycles (~=VIH)
MCM611OO1A-70, tRC = 130 ns
MCM511OO1A-80, tRC= 150 ns
MCM511OO1A-l0, tRC=l80 ns

ICC3

VCC Power Supply Currant During Nibble Mode Cycle ~=VIL)
MCM611oo1A-70, tNC=35 ns
MCM511OO1A-80, tNC=36 ns
MCM511OO1A-l0, tNC=4O ns

ICC4

VCC Power Supply Currant (Standby) ~=~=VCC-0.2 V)

ICC5

VCC Power Supply Currant During ~ Befora ~ Refresh Cycle
MCM511OO1A-70, tRC=13O ns
MCM511oo1A-80, tRC = 150 ns
MCM511oo1A-l0, tRC = 180 ns

ICC6

Input Leakage Currant (Except TF) (0 VSVins6.6 V)

Min

-

-

-

Max
80
70

60
2.0

mA
mA

2

mA

2

80
70

60
60
50
40
1.0

mA
mA

2

-

80
70

Ilka(l)

-10

10

Input Leakage Currant (TF) (0 VSVin(TF)SVCC+0.6 V)

Ilko(l)

-10

10

Output Leakage Currant (~=VIH' 0 VSVouts5.6 V)

Ilkg(O)

-10

10

FA
FA
FA

Test Function Input Currant (VCC+4.6 VSVin(TF)s10.5 V)

lin(TF)

-

1

mA

Output High VoItsge "OH = - 5 mAl

VOH

2.4

-

V

Output Low Voltage "OL = 4.2 mAl

VOL

-

0.4

V

Symbol

Max

Unit

Notes

Cin

5

pF

3

7

pF

3

7

pF

3

60

CAPACITANCE (f=l 0 MHz TA=25°C VCC=5 V Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

AD-M, D
~,~,W,TF

Output Capecitance (~= VIH to Disable Output)

Q

Cout

NOTES:
1. All voltages referanced to VSS'
2. Currant is a function of cycle rata and output loading; maximum currant is measured at the fastast cycle rata with the output open.
3. Capacitance measurad with a Boonton Metar or effective capacitance calculated from the equation: C = l.. Early and late write modes are distinguished by the active
transition of iiii, with respect to CAS. Minimum active times
tRAS and tCAS, and precharge time tRP apply to write mode,
as in the read mode.
An early write cycle is characterized by iiii active transition
at minimum time ~ before CAS active transition. Date in
(D) is referenced to CAS in an early write cycle. RAS and CAS
clocks must stay active for tRWL and tCWL, respectively,
after the start of the early write operation to complete the
Cycle.
a remains in three-state condition throughout an early write
cycle because iiii active transition precedes or coincides with
CAS active transition, keeping data-out buffers disabled. This
feature can be utilized on systems with a common 1/0 bus,
provided all writes are performed with early write cycles, to
prevent bus contention.
A late write cycle occurs when iiii active transition is made
after CAS active transition. iiii active transition could be delayed for almost 10 microseconds after CAS active transition,
(tRCD +tCWD + tRWL + 2ty) ""tRAS, if other timing minimums (tRCD, tRWL and ty) are mainteined. 0 is referenced
to iiii active transition in a late write cycle. Output buffers are
enabled by CAS active transition but may be indeterminatesee note 16 of AC operating conditions table. RAS and CAS
must remain active for tRWL and tCWL, respectively, after iiii
active transition to complete the write cycle.

a

READ CYCLE
The DRAM may be read with four different cycles: "normal"
random read cycle, nibble mode read cycle, read-write cycle,
and nibble mode read-write cycle. The normal read cycle is
outlined here, while the other cycles are discussed in separate
sections.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (iiii) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to
enable read mode.
Both the RAS and ~ clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
intemal clocks are linked in such a manner that the read access
time of the device is independent of the address multiplex
window. However, CAS must be active before or at tRCD
maximum to guarantee valid data out (a) at tRAC (access time
from RAS active transition). If the tRCD maximum is exceeded,
read access time is determined by the CAS clock active transition (tCACI.
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. iiii must remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data at that bit location. Once RAS
transitions to inactive, it must remain inactive for a minimum

READ-WRITE CYCLE
A read-write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically
a late write cycle, as discussed in the WRITE CYCLE section,
except iiii must remain high for tCWD minimum after the CAS
active transition, to guarantee valid before writing the bit.

a

NIBBLE MODE CYCLES
Nibble mode allows fast successive serial data operations
at two, three, or four bits of the 1M dynamic RAM. Read
access time in nibble mode ItN CAC) is considerably faster than
the regular RAS clock access time tRAC. Nibble mode operation consists of keeping RAS active while toggling CAS between VIH and VIL. The address ofthe first nibble bit is latched
by RAS and CAS active transitions. Each subsequent CAS
active transition increments the row and column addresses
internally to access the next bit in binary fashion. After the
fourth bit is accessed, the nibble pattern repeats itself: (0,0)
(0,1) (1,0) (1,11 (0,0) (0,11 (1,01 (1,1) .... The Al0 address
determines the starting point of the 4-bit nibble, with row
address A 10 the least significant of the (column, row) ordered

MOTOROLA MEMORY DATA

2-238

MCM511001A

pair. External addresses are ignored after the first nibble bit is
selected.
A nibble mode cycle is initiated by a normal read, write, or
read-write cycle, as described in prior sections. Once the timing
requirements for the first cycle are met, CAS transitions to
inactive for minimum of tNCP, while RAS remains low (VIL).
The second CAS active transition while RAS is low initiates
the first nibble mode cycle (tNC or tNRMW). Either a read,
write, or read-write operation can be performed in a nibble
mode cycle, subject to the same conditions as in normal operation (previously described). These operations can be intermixed in consecutive nibble mode cycles and performed in
any order. The maximum number of consecutive nibble mode
cycles is limited by tRAS. Nibble mode operation ends when
RAS transitions to inactive, coincident with or following a CAS
inactive transition.

CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order activates an internal refresh
counter that generates the row address to be refreshed. Extemal address lines are ignored during the automatic refresh
cycle. The output buffer remains at the same state it was in
during the previous cycle (hidden refresh).
Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid date at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and beck to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1).
CAS BEFORE RAS REFRESH COUNTER TEST

REFRESH CYCLES

The internal refresh counter of this device can be tested
with a CAS before RAS refresh counter test. This test is
~rformed with a read-write operation. During the test, the
Internal refresh counter generetes the row address, while the
external address supplies the column address. The entire array
is refreshed after 512 cycles, as indicated by the check date
written in each row. See CAS before RAS refresh counter
test cycle timing diagram.
The test can be performed after a minimum of eight CAS
before RAS initialization cycles. Test procedure:

The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge degrades with
time and temperature, thus each bit must be periodically refreshed (recharged) to maintein the correct bit state. Bits in
the MCM511001A require refresh every 8 milliseconds.
Refresh is accomplished by cycling through the 512 row
addresses in sequence within the specified refresh time. All
the bits on a row are refreshed simultaneously when the row
is addressed. Distributed refresh implies a row refresh every
15.6 microseconds for the MCM511001A. Burst refresh, a refresh of all 512 rows consecutively, must be performed every
8 milliseconds.
A normal read, write, or read-write operation to the RAM
will refresh all the bits (2048) associated with the particular
row decoded. Three other methods of refresh, RAS-only refresh, CAS before RAS refresh, and hidden refresh are
available on this device for greater system flexibility.

1.
2.

3.
4.

RAS-Only Refresh
RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(VIH) throughout the cycle. An extemal counter is employed
to ensure all rows are refreshed within the specified limit.

5.
6.

Write "O"s into all memory cells with normal write mode.
Select a column address, read "0" out and write "1" into
the cell by performing the CAS before RAS refresh
counter teet, reed-write cycle. Repeat this operation
512 times.
Read the "1 "s which were written in step 2 in normal read
mode.
Using the same starting column address as in step 2, read
"1" out and write "0" into the cell by performing the CAS
before RAS refresh counter test, read-write cycle.
Repeat this operation 512 times.
Read "O"s which were written in step 4 in normal read
mode.
Repeat steps 1 to 5 using complement data.

CAS BEFORE HE
REFRESH CYCLE

MEMORY CYCLE

Q -

HIGH Z -+--~

VAUD DATA·OUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA
2-239

MCM511001A

..

TEST MODE
Internal organization of this device I256K x 4) allows It to be
tested I I if it were a 256K x 1 DRAM. Only nine of the ten
edd_ (AO-AS) are ueed in teet mode; AS is internally
disabled. A teet mode write cyde writee dete. D (dete in). to
a bit in eech of the four 256K x 1 bIockI (80-83). in perallel.
A teet mode reed cycle reeds a bit in eech of the four b1ockl.
If dete is the lime in all four bits. Q (data out) is the IIrna a.
the data in 88ch bit. If dete is not the lime In all four bits. Q
is high Z. See .truth table and block diagram.

Test mode can be ueed in any timing cycle except nibble
mode cycles. The teet mode function is enabled by holding
the "TF" pin on "super voltage" for the speciflld period (trES.
trEHR. trEHC; _ TEST MODE CYCLE).
"Super voltage" =VCC + 4.5 V
where
4.5 V'"

DOC-DQ3 VOH VOL -

EARLY WRITE CYCLE

MOTOROLA MEMORY DATA
2-262

MCM514256A-MCM51L4256A

G CONTROLLED LATE WRITE CYCLE
~----------------------tRC ----------------------~~
~--------------tR~------------~~

v -

ADDRESSES IH
VIL -

READ·WRITE CYCLE
~----------------------------tRMW--------------------------~~
~----------------------

t RAS

~----------------~~---tCSH--------------------~

----~----+------------tRSH--------------+-~

~~-r--------~~~ ~~~---------tCAS ----------------~ r----~-----

ADDRESSES VIH VIL -

G VIHVIL -

~-"--"-+""''''''''''''''''-''''-''''-''''-i"-''-''f---+---J

DOa-D03VIHIVOH - ---------------------+---{I
VILIVOL -

MOTOROLA MEMORY DATA
2-263

•

MCM514256Ae MCM51 L4256A

•

FAST PAGE MODE READ CYCLE

v -

ADDRESSES IH
VIL -

iN VIHVIL -

DOD-D03 VOH -

-"--"'--"--",.-""

_ _ _ _ _ _ _ _ _-<

VOL -

FAST PAGE MODE EARLY WRITE CYCLE

ADDRESSES VIH VIL -

MOTOROLA MEMORY DATA
2-264

MCM514256A. MCM51 L4256A

FAST PAGE MODE READ-WRITE CYCLE

ADDRESSES

VIH Vil -

W

VIH Vil -

G VIH
Vil

DOQ-D03 VU.jlVOH VUlVOl -

------Hl'x'X1
VALID
DATA OUT

VALID
DATA OUT

VALID
DATA IN

MOTOROLA MEMORY DATA
2-265

VALID
DATA OUT

VALID
DATA IN

MCM514256A-MCM51L4256A

RAS ONLY 'REFRESH CYCLE
(iii and G are Don't Care)

II

~-------------------tRC------------------~
~-----------

CAS

tRAS

----------~

VIHVIL - ......'--'"'-"

r
~I~ =XXXMAD~~~SS:XXXXXXXXXXXXXXXXXXXX,-IAS~

ADDRESSES

_ __

CAS BEFORE RAS REFRESH CYCLE

(W, G, and AD-A8 are Don't Care)

----------------------.
tRAS ------------

~------------------tRC
~------------

I4-_H-

tCSR

1+------

tCHR

-----~ i""1----

Jr-------~

DOO-D03 VOH
VOL -------""1 >---------------------- HIGH

Z

MOTOROLA MEMORY DATA
2-266

MCM514256A-MCM51L4256A

HIDDEN REFRESH CYCLE (READ)

VIH RAS

CAS

VIH VIL -

ADDRESSES VIHVIL -

W

G

VIH VIL VIH VIL -

DOG-DQ3 VOH -

----------<1

VOL -

HIDDEN REFRESH CYCLE (EARLY WRITE)

ADDRESSES VIH VIL -

W VIHVIL -

~~~--.lL--.lL--.lL-=F+-+

_ _ _~~~.::.I....::.I....::.I....::.I....::.I....::.I.....\.L....::.I....::.I...:.L:.L:.L::.L..::.L..::.L..lL.lL.lL.lL.

MOTOROLA MEMORY DATA

2-2ff1

•

MCM514266A-MCM51L4256A

•

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

AAS VIH-

------~~r------------------lAAS------------------~J~~--~

VIL -

J.-------.I

1+----------1 RSH ----------.\
I CAS
,.....!~~-------

ADDRESSES VIH VIL -

READ CYCLE

v

~OO OH

-

- - - - - - - - - - - - HIGH Z

-----+---++__-{!

VOL -

EARLY WRITE CYCLE
_ VIHW
VIL - .J...;.1.L.-'''-l.L..l.L..lt.....::.t.....::.~~~.....:4+-++__________--"~~.....:~.,:::.L.:::.{..:::.L:::.L~::.L~
VIH -

___________

~OO VILREAD-WRITE CYCLE

_ VIHG

VlfilVOH -

___________ HIGH Z ___________~

DQO-OQ3

VILNOL -

MOTOROLA MEMORY DATA

2-268

MCM514256A-MCM51L4256A

a

cycle.
is valid, but not latched, as long as the CAS and G
clocks are active. When either the CAS or G clock transitions
to inactive, the output will switch to High Z, tOFF or tGZ after
the inactive transition.

DEVICE INITIALIZATION

On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the RAM. During an extended inactive
state (greater than 8 milliseconds with the device powered up),
a wake up sequence of eight active cycles is necessary to
ensure proper operation.
ADDRESSING THE RAM

The nine address pins on the device are time multiplexed at
the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 9-bit address fields. A total of eighteen address bits, nine
rows and nine columns, will decode one of the 262,144 bit locations in the device. RAS active transition is followed by CAS
active transition (active = VIL, tRGJl.!:.I1inimum) for all read or
write cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system designer flexibility in setting up the external addresses into the
RAM.
The external CAS signal is ignored until an internal RAS signal is available. This gate feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are two other variations in addressing the 256Kx4
RAM: RAS only refresh cycle and CAS before RAS refresh
cycle. Both are discussed in separate sections that follow.
READ CYCLE
The DRAM may be read with four different cycles: normal
random read cycle, page mode read cycle, read-write cycle,
and page mode read-write cycle. The normal read cycle is outlined here, while the other cycles are discussed in separate
sections.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (IN) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read
access time of the device is independent of the address multiplex window. Both CAS and output enable (G) control read
access time: CAS must be active before or at tRCD maximum
and G must be active tRAC-tGA (both minimum) after RAS
active transition to guarantee valid data out (a) at tRAC
(access time from RAS active transition). If the tRCD maximum is exceeded and/or G active transition does not occur in
time, read access time is determined by either the CAS or G
clock active transition (tCAC or tGA)'
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. IN must remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data at that bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitry forthe next active

WRITE CYCLE
The DRAM may be written with any of four cycles: early
write, late write, page mode early write, and page mode readwrite. Early and late write modes are discussed here, while
page mode write operations are covered in another section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of IN to active
(VIL). Early and late write modes are distinguished by the
active transition of IN, with respect to CAS. Minimum active
time tRAS and tCAS, and precharge time tRP apply to write
mode, as in the read mode.
An early write cycle is characterized by IN active transition at
minimum time ~before CAS active transition. Data In (D)
is referenced to CAS in an early write cycle. RAS and CAS
clocks must stay activefortRWL and tCWL' respectively, after
the start of the early write operation to complete the cycle.
remains High Z throughout an early write cycle because
IN active transition precedes or coincides with CAS active
transition, keeping data out buffers disabled, effectively disablingG.
A late write cycle (referred to as G controlled write) occurs
when IN active transition is made after CAS active transition.
IN active transition could be delayed for almost 10 microseconds after CAS active transition, (tRCD + tCWD + tRWL + tTl
"tRAS, if timing minimums (tRCD, tRWL, and tTl are maintained. D is referenced to IN active transition in a late write
cycle. Output buffers are enabled by CAS active transition but
may be indeterminate-see note 15 of AC operating conditions table. Parameters tRWL and tCWL also apply to late write
cycles.

a

a

READ-WRITE CYCLE

A read-write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically a
late write cycle, as discussed in the WRITE CYCLE section,
except IN must remain high for tCWD minimum after the CAS
active transition, to guarantee valid before writing the bit.

a

PAGE MODE CYCLES

Page mode allows fast successive data operations at all512
column locations on a selected row of the 256Kx4 dynamic
RAM. Read access time in page mode (tCAC) is typically half
the regular RAS clock access time, tRAC' Page mode operation consists of keeping RAS active while toggling CAS between VIH and ~The row is latched by RAS active transition, while each CAS active transition allows selection of a new
column location on the row.
A page mode cycle is initiated by a normal read, write, or
read-write cycle, as described in prior sections. Once the
timing requirements for the first cycle are met, CAS transitions
to inactive for minimum tcp, while RAS remains low (VIL). The
second CAS active transition while RAS is low initiates the first
page mode cycle (tpc or tpRWC). Either a read, write, or
read-write operation can be performed in a page mode cycle,
subject to the same conditions as in normal operation
(previously described). These operations can be intermixed in
consecutive page mode cycles and performed in any order.
The maximum number of consecutive page mode cycles is
limited by tRASP' Page mode operation is ended when RAS

MOTOROLA MEMORY DATA
2-269

MCM514256A- MCM51 L4256A

III

transitions to inactive, coincident with or following CAS
inactive transition.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge degrades with
time and temperature, thus each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in the
MCM514256A require refresh every 8 milliseconds while refresh time for the MCM51 L4256A is 64 milliseconds ..
Refresh is accomplished by cycling through the 512 row
addresses in sequence within the specified refresh time. All
the bits on a row are refreshed simultaneously when the row is
addressed. Distributed refresh implies a row refresh every
15.6 microseconds forthe MCM514256A and 124.8 microseconds forthe MCM51 L4256A. Burst refresh, a refresh of all512
rows consecutively, must be performed every 8 milliseconds
on the MCM514256A and 64 milliseconds on the
MCM51 L4256A.
A normal read, write, or read-write operation to the RAM will
refresh all the bits (2048) associated with the particular row decoded. Three other mehtods of refresh, RAS-only refresh,
CAS before RAS refresh, and Hidden refresh are available
on this device for greater system flexibility.
RAS-Only Refresh
RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(VIH) throughout the cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.
CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order actives an internal refresh counter that generates the row address to be refreshed. External
address lines are ignored during the automatic refresh cycle.
The output buffer remains at the same state it was in during the
previous cycle (hidden refresh).

MEMORY CYCLE

1\

HIGHZ

Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1).
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CAS before RAS refresh counter test. This test is performed with a read-write operation. During the test, the internal
refresh counter generates the row address, while the external
address supplies the column address. The entire array is
refreshed after 512 cycles, as indicated by the check data written in each row. See CAS before RAS refresh counter test
cycle timing diagram.
The test can be performed after a minimum of eight CAS
before RAS initialization cycles. Test procedure:
1. Write "O"s into all memory cells with normal write mode.
2. Select a column address, read "0" out and write "1" into the
cell by performing the CAS before RAS refresh counter
test, read-write cycle. Repeat this operation 512 times.
3. Read the "1"s which were written in step 2 in normal read
mode.
4. Using the same starting column address as in step 2, read
"1" out and write "0" into the cell by performing the CAS
before RAS refresh counter test, read-write cycle.
Repeat this operation 512 times.
5. Read "O"s which were written in step 4 in normal read mode.
6. Repeat steps 1 to 5 using complement data.

CAS BEFORE RAS
REFRESH CYCLE

/"

\

DQO-DQ3 -

Hidden Refresh

/

\

CAS BEFORE RAS
REFRESH CYCLE

/"

VALID DATA OUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA
2-270

>-~

MCM514256A-MCM51L4256A

ORDERING INFORMATION
(Order by Full Pari Number)

111 T

MCM 514256A or 51 L4256A X X XX XX

Motorola Memory Prefix

T

I

Part Number _ _ _ _ _ _ _--'.

.,,'..., --I"· '''' " ...... "'"
Speed (70 = 70 ns, 80 = 80 ns, 10 = 100 ns)
Temperature (Blank = 0 to 70'C,
C = -40 to 85'C)
Package (P = 300 mil Plastic DIP,
J =300 mil SOJ, Z =Plastic ZIP)

Commercial Temperature Range 0 to 70'C
Full Part Numbers- MCM514256AP70
MCM514256AP80
MCM514256AP10
MCM51L4256AP70
MCM51 L4256AP80
MCM51L4256API0

MCM514256AJ70
MCM514256AJ80
MCM514256AJ10

MCM514256AJ70R2
MCM514256AJ80R2
MCM514256AJ10R2

MCM514256AZ70
MCM514256AZ80
MCM514256AZ10

MCM51L4256AJ70
MCM51 L4256AJ80
MCM51L4256AJ10

MCM51L4256AJ70R2
MCM51 L4256AJ80R2
MCM51 L4256AJI OR2

MCM51 L4256AZ70
MCM51 L4256AZ80
MCM51L4256AZI0

Industrial Temperature Range -40 to +85'C
MCM514256APC70
MCM514256APC80
MCM514256APC10

MCM514256AJC70
MCM514256AJC80
MCM514256AJC10

MCM514256AJC70R2
MCM514256AJC80R2
MCM514256AJC10R2

MCM514256AZC70
MCM514256AZC80
MCM514256AZC10

MCM51 L4256APC70 MCM51 L426AJC70
MCM51 L4256APC80 MCM51 L426AJC80
MCM51L4256APC10 MCM51L426AJC10

MCM51L426AJC70R2
MCM51 L426AJC80R2
MCM51L426AJC10R2

MCM51L4256AZC70
MCM51 L4256AZC80
MCM51L4256AZC10

NOTE: Low Power Industrial Temperature SOJ device part numbers are one character shorter than corresponding
PDIP or ZIP part numbers.

MOTOROLA MEMORY DATA
2-271

•

MOTOROLA

-

II

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM514256B
MCM51 L4256B

256K X 4 CMOS Dynamic RAM
Page Mode
The MCM514256B is a 0.8jL CMOS high-speed. dynamic random access memory. It is
organized as 262.144 four-bit words and fabricated whh CMOS silicon-gate process
technology. Advanced circuit design and fine line processing provide high performance.
improved reliability. and low cost.
The MCM514256B requires only nine address lines; row and column address inputs are
multiplexed. The device is packaged in a 300-mil SOJ plastic package. and a 1OO-mil zigzag in-line package (ZIP).
• Three-State Data Output
• Fast Page Mode
• TTL-Compatible Inputs and Output
• RAS" Only Refresh
• CAS Before RAS Refresh
• Hidden Refresh
• 512 Cycle Refresh:
MCM514256B.8 ms
MCM51 L4256B - 64 ms
• Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
• Fast Access lime (tRAC):
MCM514256B-60 and MCM51 L4256B-60 - 60 ns (Max)
MCM514256B-80 and MCM51L4256B-80 = 80 ns (Max)
• Low Active Power Dissipation:
MCM514256B-60 and MCM51 L4256B-60 = 495 mW (Max)
MCM514256B-80 and MCM51 L4256B-80 = 385 mW (Max)
• Low Standby Power Dissipation:
MCM514256B and MCM51L4256B = 11 mW (Max). TTL Levels
MCM514256B. 5.5 mW (Max). CMOS Levels
MCM51 L4256B = 1.1 mW (Max). CMOS Levels

JPACKAGE

300·MILSOJ
CASE 822

,

ZMCKAG'

PLASTIC
ZIG·ZAG IN·LlNE
CASE 836

~
~

PIN NAMES
AO-A8 . . . . . . . . . . . . .. Address Input
DOO-OQ3 . . . . . . .. Data InputlOutput
(3 .................. Output Enable
W ............... ReadlWrite Input
RAS .......... Row Address Strobe
IDi§ ....... Column Address Strobe
Vce ......... Power Supply (+ 5 V)
Vss .................... Ground
NC .........•...... No Connection

PIN ASSIGNMENT
ZlG·ZAG IN·LINE

r;-r-

SMALL OUTLINE

ll: ••
002

..

Vss

==

OQO I 1

26

Vss

001

2

25

003

Vi

3

24

002

001

RAS

4

23

CAS
G

m

NC

5

22

AO

AO

9

18

AS

A2

A1

10

17

A7

Vee

A2

11

16

A3

12

15

Vee

13

14

aAS
aM
aM

This document contain. information on a ~ product Specification. and information herein are subject to change without notioe.

MOTOROLA MEMORY DATA

2-272

AS

3

2

==

4

5
6

7
8
9

1°.

.. ==
.. 11,

11

12

13

15.

.. ..l~
16

17

19
A7 •• 20

CAS
003

DQO

Vi
NC
A1
A3

M
AS

_..!.!..AS

MCM514256BeMCM51L4256B

E

BLOCK DIAGRAM

w--------~cr-"

'CA§------.t

AO
AI
A2
A3
A4
A5
A6
A7

AS

RAS------4OI

ABSOLUTE MAXIMUM RATING (See Note)
Rating
Power Supply Voltage

Symbol

Value

Unit
V

VCC

-1 to +7

Vin, Vout

-1 to +7

V

Data Out Current

lout

50

mA

Voltage Relatiw to Vss for Any Pin Except VCC
Power Dissipation

Po

600

mW

Operating Temperature Range

TA

Oto +70

·C

Storage Temperature Range

Tstg

-55 to +150

·C

This devioe oontains circuitry to protect the
inputs against damage due to high static voltages or electric fields; howewr, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high-impedance
circuit.

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA = Oto 70·e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

Supply Voltage (Operating Voltage Range)

Vee

Logic High Voltage, All Inputs
Logic Low Voltage, All Inputs

VSS
VIH
VIL

MOTOROLA MEMORY DATA
2-273

Min
4.5

Typ
5.0

0

0

2.4
-1.0

-

Max

Unit

Notes

5.5
0

V

1

6.5
O.B

V
V

1
1

MCM5142568- MCM51 L42568

•

DC CHARACTERISTICS
Symbol

Characterl8tlc
VCC Power SuKs'ttrUmlllt
OandMCM51l4256B-60,tRC= 110ns
MCM5142
MCM514256B-60 and MCM51L4256B-60, tRC = 150 ns

ICCl

VCC Power Suct.r CUmlllt~tan~~mi§=CAS:VIH)
MCM5142
and MC lL4

ICC2

m

Min

-

..ax

Unit

Noles

mA

3

90
70

mA
2

VCC Power suEt~mIIlt During
~ Rafresh Cycles (~VIH)
O,tRc=110ns
MCM5142
andMCM51L4256
MCM514256B-60 and MCM51L4256B-60, tRC" 150 ns

ICC3

VCC Power SuEt~mIIlt During Fast P~ Mode Cl8'e (RAS" - VILl
MCM5142
and MCM51L4256
,!PC =
ns
MCM5142568-60 and MCM51l42568-60,!pC" 45 ns

ICC4

VCC Power suger. CUmlllt (Standby) (RAS=~=VCc-O.2 V)
MCM5142
MCM51l4256B-

ICC5

VCC Power sUI'~mIIlt DUrin~ eAS Before roiS Rafresh Cycle
MCM5142
andMCM5 l4256B-60,lRc-110ns
MCM514256B-60and MCM51L42568-60,IRC = 150 ns

ICC6

Vcc..f.ower Supply Current, Battery Backup Mode.JIRC = 125 lIS, IRAs = 1 lIS,
CAS=CASBefore RAS Cycle orO.2 V, AO-Aa, W, 0= VCC-0.2 VorO.2V)
MCM51 L4256B-

ICC5

-

300

Input Leakage Current (0 V s Vin S 6.5 V)

Ilkg(l)

-10

10

Output Leakage CUmlllt (CAS = VIH, 0 V S Vout S 5.5 V, Output Disable)

Ilkg(O)

-10

10

Output High Voltage (ICH .. -5 rnA)

VOH

2.4

Output Low Voltage (IOL .. 4.2 rnA)

VOL

mA

3

mA

3,4

90
70

60
50
1.0

200

mA

IIA
mA

3

IIA

3

90
70

-

IIA
IIA
V

-

0.4

V

Symbol

Max

Unit

Notas

Cin

5

pF

4

pF

4

CAPAQTANCE (I = 1.0 MHz, TA" 25"C, VCC" 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

AO-A8
~,m,~,w

000-003

I/O Capacitance (CAS = VIH to Disable Output)

7
Cout

7

NOTES:
1. All,voItages referenced to Vss.
2. Current Is a function of cycle nllll and output loading; maximum CUmlllt is measured at the fastest cycle ralll with the output open.
3. Measured with one address transition per page mode cycle.
4.

Capaci1anoe measured with a Boonton Melllr or effective capaci1ance celculated from the equation: C = IAI/AV.

MOTOROLA MEMORY DATA
2-274

MCM514256B-MCM51L4256B

E

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC

=5.0 V ± 10%, TA =0 to 70·C, Unless Otherwise Noted)

READ, WRITE, AND READ-WRITE CYCLES (See Notes I, 2, 3, and 4)
MCM514256B-60
MCM51 L4256B-60

Symbol
Paramater

MCM514256B-80
MCM51L4256B-80

Std

Alt

Min

Max

Min

Max

Units

Random Read or Write Cycle Time

tRELREL

tRC

110

-

150

ns

5

Read-Write Cycle Time

tRELREL

tRMW

165

-

205

ns

5

Fast Page Mode Cycle Time

tCELCEL

tpc

40

Fast Page Mode Read-Write Cycle Time

tCELCEL

tpRMW

95

-

100

Access Time from ~

tRELQV

tRAC

-

-

60

80

ns

6,7

Access Time from CAS

tCELQV

teAC

20

20

ns

6,8

30

40

ns

6,9

35

-

45

ns

6

45

Notes

ns
ns

Access Time from Column Address

IAVQV

IAA

-

Access Time from CAS Precharge

teEHQV

tePA

-

CAS to Output in Low-Z

tCELQX

tell

0

-

0

-

ns

6

Output Buffer and Tum-Olf Delay

teEHQZ

toFF

0

20

0

20

ns

10

Transition Time (Rise and Fall)

IT

IT

3

50

3

50

ns

RAS Precharge Time

tREHREL

tRP

40

-

60

-

ns

RAS Pulse Width

tRELREH

tRAS

60

10,000

80

10,000

ns

RAS Pulse Width (Fast Page Mode)

tRELREH

IRASP

60

100,000

80

100,000

ns

RAS Hold Time

tCELREH

tRSH

20

-

20

ns

RAS Hold Time from CAS Precharge (Page

tCELREH

IRHCP

35

-

40

-

CAS Hold Time

tRELCEH

teSH

60

-

80

-

ns

CAS Pulse Width

tCELCEH

tCAS

20

10,000

20

10,000

ns

RAS to CAS Delay Time

tRELCEL

tRCD

20

40

20

60

ns

11

RAS to Column Address Delay Time

tRELAV

tRAD

15

30

15

40

ns

12

CAS to ~ Precharge Time

tCEHREL

teRP

5

-

5

tCEHCEL

tep

10

-

10

Row Address Setup Time

tAVREL

IASR

0

-

0

Row Address Hold Time

tRELAX

tRAH

10

-

10

-

ns

CAS Precharge Time

Mode Cycle Only)

"

ns

ns
ns
ns
(conDnued)

NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 I1S is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specifications for tRC (min) and IRMW (min) are used only to indicate cycle time at which proper operation over the full temperature
range (OOC S TA S 70·C) is assured.
6. Measured with a current load equivalent to 2 TTL (- 200 IJA, + 4 mAl loads and 100 pF with the data output trip points set at VOH = 2.0
V and VOL = 0.8 V.
7. Assumes that tRCD S tRCD (max).
8. Assumes that tRCD ~ tRCD (max).
9. Assumes that tRAD ~ tRAD (max).
10. toFF (max) andlor IGz (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage
levels.
11. Operation within the tRCD (max) limit ensures thatlRAC (max) can be met. tRCD (max) is specified as a reference point only; ij tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by teAC.
12. Operation within the IRAD (max) limit ensures that tRAC (max) can be mel. tRAD (max) is specified as a reference point only; if tRAD is
greater than the speWied tRAD (max) limit, then access time is controlled exclusively by IAA.

MOTOROLA MEMORY DATA
2-275

MCM514256B-MCM51L4256B

II

READ, WRITE, AND READ-WRITE CYCLES (Continued)
MCM514256B-60
MCM51 LA256B-60

Symbol

MCM514256B-80
MCM51 LA256B-80

Std

All

Min

Max

Min

Max

Unit

Column Address SebJp lime

IAVCEL

tASC

0

-

0

ns

Column Address Hold Tillie

leELAX

leAH

15

IAR

50

-

60

Parameter

Column Address Hold lime Relerenced to

'AAS

'RELAX

40
0

-

ns

0

13

0

-

ns

0

-

ns

13

twCH

10

-

15

-

ns

twCR

45

-

60

-

ns

-

15
20

-

ns

20
0

-

ns

14

15

-

ns

14

8
64

ms

Column Address to RAS Lead lime

tAVREH

tRAL

30

Read Command SebJp lime

'WHCEL

'Rcs

0

Read Command Hold lime

leEHWX

'RCH

0

Read Command Hold lime Relerenced to

tREHWX

tRRH

leELWH
tRELWH

'RAS
Write Command Hold lime Relerenced to

CAS
Write Command Hold lime Referenced to

'AAS
Write Command Pulse Width

twLWH

twP

10

Write Command to RAS Lead lime

twLREH

tRWL

20

Write Command to ~ Lead lime

twLCEH

leWL

20

Data in SebJp lime

tDVCEL

tDS

0

Data in Hold lime

leE LOX

tDH

15

Data in Hold lime Relerenced to 'AAS

'RELDX

IDHR

50

tRVRV

tRFSH

-

Refresh Period

MCM514256B
MCM51LA256B

Notes

-

15

-

60

8
64

-

-

ns
ns
ns

ns
ns

ns

Write Command SebJp lime

twlCEL

twcs

0

-

ns

15

leELWL

leWD

50

-

0

CAS to Write Delay

50

-

ns

15

'RAS to Write Delay

tRELWL

tRWD

90

-

110

-

ns

15

Column Address to Write Delay lime

tAVWL

tAWD

60

70

-

ns

15

CAS Precharge to Write Delay

leEHWL

lePWD

65

-

70

-

ns

15

~ SebJp lime for ~ Before 'AAS

tRELCEL

leSR

5

-

5

-

ns

tRELCEH

leHR

15

15

tREHCEL

tRPC

0

~ Precharge lime for ~ Before RAS
Counter Test

leEHCEL

tCPT

30

-

40

-

ns

'RAS Precharge to ~ Active lime

-

Refresh
CAS, Hold lime for CAS Before RAS
Refresh

0

ns
ns

RAS Hold lime Relerenced to G

IGLREH

'ROH

10

-

10

-

ns'

GAccessTlllle

IGLOV

IGA

-

.20

-

20

ns

Ci to Data Delay

IGLHDX

IGD

20

-

20

-

ns

Output Buffer Tum-Off Delay lime from G"

IGHOZ

IGz

0

20

0

20

ns

G Command Hold lime

twLGL

IGH

20

-

20

-

ns

Output Disable Setup lime

IGHCEL

tGS

0

-

0

-

ns

10

NOTES:
13. Either 'RRH or 'RCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in ea~y write cycles and to IN leading eclge in delayed write or read-write cycles.
15. twcs, tRWD, leWD, lePWD, and IAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if twcs 2: twcs (min), the cycle is an ea~y write cycle and the data out pin will remain open circuit (high impedance) throughout
the entire cycle; if leWD 2: leWD (min), tRWD 2: 'RWD (min), lePWD 2: lePWD (min), and tAWD 2: tAWD (min), the cycle is a read-write
cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied, the condition of the data
out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
2-276

MCM514256B-MCM51L4256B

READ CYCLE

ADDRESSES VIH VII. - ........................ _____,.-T

W VIHVII. -.L..l~~~~"*~~

II VIHVII.

-~~~~~~~~~~~~~~~--+~~~~~~~~~~~~~~.

DQG-003 VOHVOL -

EARLY WRITE CYCLE

ADDRESSES VIH VIL -

~3

VIH VIL -

.L..J~~ .,..;.=~#

---------<1

1"-----4

MOTOROLA MEMORY DATA

2-XT7

•

MCM514256B-MCM51L4256B

..

G CONTROLLED LATE WRITE CYCLE
~---------------------tRC----------------------~
~-------------t~------------~~

READ-WRITE CYCLE

~---------------------------tRMW--------------------------~
_____________________
~

~-----

t~

tAR

-----.j
t~

____________________

__

~

----~
--r_----------t~--------------~~
~_+4_------~~__ ~~_+------ t~
r---~-----

~ VIH-

VIL -:- ...................+"-''''-'.......'--''.......'--'''~--'f----+--.J

VIHNOH D~

-+-__-<1

___________________

VLNOL -

MOTOROLA MEMORY DATA
2-278

MCM514256B. MCM51 L4256B

FAST PAGE MODE READ CYCLE

W VIHVL-

...lC......lL...lL..~..,

G VIHVL-

DOO-DQ3 VOH -

...lC.....lC......lL.~..lL..~~~~~~~~~~~~~__~~~~~~~~~__~~....lL.~..lL..~¥

--------....:..---<1

VOL -

FAST PAGE MODE EARLY WRITE CYCLE

VIH-

CAS

VIL -

ADDRESSES VIH VIL -

W VIHVIL -~~~~~~~--~--~~~~~~~--~~~~~~~R-r---~~~~~~~~

MOTOROLA MEMORY DATA

2-279

•

MCM514256B-MCM51L4256B

•

FAST PAGE MODE READ-WRITE CYCLE

lIAS

CAS

VIH VL -

VIH-

ADDRESSES VIH-

VII. -

DOO-DQ3 VIHiVOH- ------t-(l)(11
VuJVOL -

VAUD

VAUD

DATA OUT

DATA OUT

MOTOROLA MEMORY DATA
2-280

VALID
DATA OUT

VALID
DATA IN

MCM514256B-MCM51 L4256B

RU ONLY REFRESH CYCLE
(W and ~ are Don't Care)
~

VIH ~

-----------::t.

__________________

t~

__________________

~

~----------t~----------~

J.:-----------"L

VIL tAPe

m V1H VIL -

ADDRESSES

L...lo'-lj~

~~

·r

~: =XXXXXAD~~s)
s tRAS. Htiming minimums (tRCD. tRWL. and tTl are maintained. D is referenced to W active transition in a late write
cycle. Output buffers are enabled by CAS active transition but
a may be indeterminate-5ee note 15 of AC operating conditions table. Parameters tRWL and tCWL also apply to late write
cycles.

a

The DRAM may be read with four different cycles: normal
random read cycle. page mode read cycle. read-write cycle.
and page mode read-write cycle. The normal read cycle is outlined here. while the other cycles are discussed in separate
sections.
The normal read cycle begins as described in ADDRESSING THE RAM. with ~ and CAS active transitions latching
the desired bit location. The write (W) input level must be high
(VIH).tRCS (minimum)beforethe CASactivetransition. to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read
access time ofthe device is independent of the address multiplex window. Both CAS and output enable (G) control read
access time: ~ must be active before or at tRCD maximum
and G must be active tRAC-tGA (both minimum) after RAS
active transition to~rantee valid data out (a) at tRAC
(access time from RAS active transition). If the tRCD maximum is exceeded and/or ~ active transition does not occur in
time. read access time is determined by either the CAS or G
clock active transition (tCAC or tGA).
The RASand CAS clocks must remain aclive for a minimum
time of tRAS and teAS respectively. to complete the read
cycle. Wmust remain high throughout the cycle. and for time
tRRH or tRCH after RAS or CAS inactive transition. respectively. to maintain the dataatthat bit location. Once RAS transitions to inactive. it must remain inactive for a minimum time of
tRP to prechargethe Internal device circuitryforthe next active

READ-WRITE CYCLE
A read-write cycle performs a read and then a write at the
same address. during the same cycle. This cycle is basically a
late write cycle. as discussed in the WRITE CYCLE section.
except Wmust remain high for tCWD minimum after the CAS
active transition. to guarantee valid a before writing the bit.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all 512
column locations on a selected row of the 256Kx4 dynamic
RAM. Read access time in page mode (tCAC) is typically half
the regular RAS clock access time. tRAC. Page mode operation consists of keeping ~ active while toggling CAS between VIH and YR.:..The row is latched by RAS active transition. while each CAS active transition allows selection of a new
column location on the row.
A page mode cycle is initiated by a normal read. write. or
read-write cycle. as described in prior sections. Once the
timing requirements forthe first cycle are met. ~ transitions
to inactive for minimum tcP. while RAS remains low (VIU. The
second ~ active transition while ~ is low initiates the first
page mode cycle (tpc or tPRWC). Either a read. write. or
read-write operation can be performed in a page mode cycle.
subject to the same conditions as in normal operation
(previously described). These operations can be intermixed in
consecutive page mode cycles and performed in any order.
The maximum number of consecutive page mode cycles is
limited by tRASP. Page mode operation is ended when RAS

MOTOROLA MEMORY DATA

2-284

MCM514256B-MCM51L4256B

transitions to inactive, coincident with or following ~
inactive trans~ion.

Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1).

REFRESH CYCLES
ThedynamicRAMdesignisbasedoncapacitorchargestorage for each bit in the array. This charge degrades with time
and temperature, thus each b~ must be periodically refreshed
(recharged) to maintain the correct b~ state. Bits in the
MCM514256B require refresh every 8 milliseconds while refresh time for the MCM51 L4256B is 64 milliseconds..
Refresh is accomplished by cycling through the 512 row
addresses in sequence w~hin the specified refresh time. All
the b~s on a row are refreshed simukaneously when the row is
addressed. Distributed refresh implies a row refresh every
15.6 microseconds forthe MCM514256B and 124.8 microseconds for the MCM51 L4256B. Burst refresh, a refresh of all512
rows consecutively, must be performed every 8 milliseconds
on the MCM514256B and 64 milliseconds on the
MCM51 L4256B.
A normal read, write, or read-wr~e operation to the RAM will
refresh all the bits (2048) associated w~h the particular row decoded. Three other methods of refresh, RAS-only refresh,
CAS before liB refresh, and Hidden refresh are available
on this device for greater system flexibility.

eA! BEFORE ~ REFRESH COUNTER TEST
The internal refresh counterofthis device can be tested with
a ~ before RAS refresh counter test. This test is performed with a read-write operation. During the test, the internal
refresh counter generates the row address, while the external
address supplies the column address. The entire array is
refreshed after 512 cycles, as indicated by the check data written in each row. See c:AS before RAS refresh counter test
cycle timing diagram.
Thetestcanbeperformedafteraminimumofeight~be

fore RAS initialization cycles. Test procedure:
1. Write "O"s into all memory cells with normal write mode.
2. Select a column address, read ''0" out and write "1" into the
cell by performing the c:AS before RAS refresh counter
test, read-write cycle. Repeat this operation 512 times.
3. Read the ·'1"s which were written in step 2 in normal read
mode.
4. Using the same starting column address as in step 2, read
"1" out and write "0" into the cell by performing the CAS
before RAS refresh counter test, read-write cycle.
Repeat this operation 512 times.
5. Read "O"s which were written in step 4 in normal read mode.
6. Repeat steps 1 to 5 using complement data.

RAS-Only Refresh
RAS-only refresh consists of RAS transition to active,latching the row address to be refreshed, while CAS remains high
(VIH) throughout the cycle. An external counter is employed to
ensure all rows are refreshed w~hin the specnied limit.
CAS Before RAS Refresh
~ before RAS refresh is enabled by bringing CAS active
before RAS. This clock order actives an internal refresh counter that generates the row address to be refreshed. External
address lines are ignored during the automatic refresh cycle.
The output buffer remains at the same state it was in during the
previous cycle (hidden refresh).

CAS BEfORE RAS
REFRESH CYCLE

MEMORY CYCLE

-

"
DQO-DQ3 -

HIGHZ

I

\

CAS BEFORE RAS
REFRESH CYCLE

I'~

1\

VALID DATA OUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA

2-286

)-+-

•

MCM514256B- MCM51 L4256B

FJI

ORDERING INFORMATION
(Order by Full Part Number)

111 T

MCM 514256B or 51 U256B X X

T....

Motorola Memory Prefix _ _ _

I

Part Number _ _ _ _ _ _ _...1.

xx xx

-

_,RO- _ . _

....

Speed (60 =60 nl, ao =80 nl)

Temperature (Blank - 0 to 7O"C)
Package (J - 300-mH SOJ, Z =Plastic ZIP)

Commercial TemperalUre Range 0 III 7O"C
Fu" Part Numbers-

MCM514256BJ60
MCM514256BJao

MCM514256BJ60R2
MCM514256BJaoR2

MCM514256BZ80
MCM514256BZ80

MCM51L4256BJ60
MCM51L4256BJao

MCM51L4256BJ60R2
MCM51L4256BJ80R2

MCM51L4256BZ60
MCM51L4256BZao

MOTOROLA MEMORY DATA

2-286

""'1

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM514258A

256K X 4 CMOS Dynamic RAM
Static Column
The MCM514258A is a 1.0" CMOS high-speed, dynamic random access memory. It is
organized as 262,144 four-bit words and fabricated with CMOS silicon-gate process technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low coat.
The MCM514258A requires only nine address lines; row and column address inputs are
multiplexed. The device is packaged in a standard 300-mll dual-in-line plastic package
(DIPI, a 300-mil SOJ plastic package, and a 100-mil zig-zag in-line plastic package (ZIPI.

~PPACKAGE
~~ ~ "~MIL
U

JPACKAGE
300 MILSOJ
CASE 822

,

~MCKAG'

• Three-State Data Output
• Static Column Mode
• TTL-Compatible Inputs and Output
• iiAS Only Refresh
• CS Before RAS Refresh

~'~~LASTIC

ZIG-ZAG IN-LINE
CASE 836

• Hidden Refresh
•
•
•

•

•

PLASTIC

CASE738A

512 Cycle, 8 ms Refresh
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access TIme (tRACI:
MCM514258A-70=70 ns (MaxI
MCM514258A-80=80 ns (MaxI
MCM514258A-10=100 ns (Maxi
Low Active Power Dissipation:
MCM514258A-70=440 mW (MaxI
MCM514258A-80=385 mW (MaxI
MCM514258A-10=330 mW (MaxI
Low Standby Power Dissipation:
11 mW (MaxI, TTL Levels
5.5 mW (MaxI, CMOS Levels

PIN NAMES
AG-AB • . . . • • . . . • • Address Input
DQO-DQ3 • . • • . . . Data Input/Output
'1i . . • . . . . . • . . . . • Output Enable
Read/Write Input
~ . • • • . • • • Row Address Strobe
CS • . . . . • • . . • • • • . . Chip Select
VCC • • . . . . . . . . . • Power (+5 VI
VSS • • . • . • • . . . • . . • . . Ground
NC • . • • • • . . • • • • • No Connection

w. . . . . . . . . . . .

ZIG-ZAG IN-LINE

il
SMALL OUTLINE
DUAL-IN-L1NE

PIN
ASSIGNMENT

~Vss
~DU3
24 ~002
23 ~cs
22 ~il

000

1

26

001

2

25

0001 1.

20

0011 2

19

DQ3

WI 3
liAS I 4

18

DQ2

1m

4

17"

CS

NC

5

Nci 5

111

II

Aol 6

15

A8

AI

7

14

A7

Aol 9

A2

8

13

A6

All 10

17 PA7

A3

9

12

A5

A21 11

16 PA6

VCC

10

11 pA4

Vss

W3

A31 12

15 PA5

VCe! 13

14~A4

MOTOROLA MEMORY DATA
2-287

18 PA8

ij"T""
==1

:1= cs

3
002 ==1 4
51==
VSS ==16
7 :==
001 ==16
91==
==1

m

003
DOD
_
W

I!~ NC
111
AD ==112
1== Al
A2 HI
I!~ A3
151
VCC ==116
171== A4
A5 ==1 8
19:!= A6
A7 ==120
1== A8

...........

MCM514258A

•

BLOCK DIAGRAM
i-----------------or-~

AO
AI
A2
A3
A4
A5
A6
A7
A8

RAS-----~

ABSOLUTE MAXIMUM RATINGS (Sea Note)
Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin Except VCC
Date Out Current

Symbol

Valua

Unit

VCC

-1 to +7

V

Vln. Vout

-1 to +7

V

lout

60
600

mA

Power Dissipation

PD

Opalllting TempallltUre Range

TA

Storage Temperature Range

Tata

Oto +70
-56 to +160

mW
·C
·C

NOTE: Pannanant dllVlC8 damage may occur if ABSOLUTE MAXIMUM RATINGS are
excaaded. Functional operation should be reSlrictad to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of tima could affect device reliability.

MOTOROLA MEMORY DATA
2-288

This devIoe contains circuitry to protect the
Inputs againBl damage due to high static
voltages or alactric fields; however. it is advised that normal precautions be taken to
avoid application of any voltage higher then
maximum rated voltagas to this high-Impedance circuit.

MCM514258A

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vcc = 5.0 V ±10%, TA=O to 7O"C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Param_r

Symbol

Min

Typ

Max

Unit

N_

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

-

6.5

V

1

0.8

V

1

Unit

N_

mA

2

Supply Voltage (Operating Voltage Range)

Logic High Voltage, All Inputs

VIH

2.4

Logic Low Voltage, All Inputs

VIL

-1.0

DC CHARACTERlmCS
Chanu:tarlatlc

Symbol

Min

Max

Vee Power Supply Cunant
MCM51Gi11A-70, tHC= 130 lIS
MCM51425J1A.81, tHc = 150 lIS
MCM51Gi11A-l0, tHC= 180 lIS

ICCI

VCC Power Supply Cunant (Standby) ~=CS=VIHI

ICC2

VCC Power Supply Cutrant During ~ only Refresh Cycles (CS=VIH)
MCM51421i11A-70, tHc = 130 lIS
MCM51425J1A.81, tHc = 150 lIS
MCM5142511A-l0, tHc = 180 lIS

ICca

Vee Power Supply Cunant During S1aIic Column Mode Cycle 11iAS="fS=VILI
MCM51421i11A-70, tsC=4O lIS
MCM5142!il1A-80, tsc=45 ns
MCM5142511A-l0, tsc = 50 lIS

ICC4

Vee Power SupplY Cutrant (Standbyl (~=CS=VCC-O.2 VI

ICC6

Vee Power Supply Cunant During "fS Befont JIA§" Refresh Cycle
MCM5142!il1A-70, tHc = 130 lIS
MCM51425J1A.81, tHc = 150 lIS
MCM5142!il1A-l0, tHC = 180 lIS

ICC6

Input I..eIIIcaga Cunant (0 V sVin sS.5 VI

Ilkg(ll

-10

10

Output I..eIIIcaga Cunant ~=VIH' 0 VSVouts5.5 VI

Ilkg(OI

-10

10

VOH

2.4

Output High Voltage

(1oH =

- 5 mAl

Output Low Voltage (lOL =4.2 mAl

-

70
80
2.0

mA
mA

2

mA

2,4

80

70
80
80
50

40
1.0

mA
mA

2

80

70
80

-

,.A
,.A
V

0.4

V

Symbol

Max

Unit

N_

Cln

5

pF
pF

Cout

7
7

3
3
3

VOL

CAPACrrANCE (f= 1.0 MHz. TA =25°C, VCC=5 V,

80

Periodically Sampled Rather Than 100% Tested)

Para_r
Input CapaciIanca

AO-AS

'G, RU, "fS, W
Output CapaciIanca ~ = VIH to DieabIe Output)

OCIO-OQ3

pF

NOTES:
1. All vohagaa refanInced to VSS.
2. Cutrant is a function of cycle rata and output loading; maximum current is measured at the fastaat cycle rata with the output opan.
3. Capacitance..-nd with a Boonton Meter or effectiw capacitance calculated from the equation: C = IAt/AV.
4. Meesuted with OIlS ........ transition par static column mode cycle.

MOTOROLA MEMORY DATA
2-289

•

MCM514258A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ± 10%, TA=O to 70o C, Unless OtherwiSe Noted)
READ WRITE, AND READ-WRITE CYCLES (See Notes 1 2 3 and 4)
MCM61Gi11A-70 MCM&lGi11A-80 MCM61Gi11A-l0

Svmbol

Parameter

Standard Altarnata

Min

Max

Min

tRC

130

150

tRMW

185

Max

110

-

-

80

tAVAV

tSRMW

100

-

Access Time from ~

tRELQV

tRAC

-

70

Access Time from ~

tCELQV

tCAC

Access Time from Column Address

tAVQV

tM

Access Time from Last Write

twLQV

tALW

-

CS to Output in Low-Z

tCELQX

tCLZ

0

-

Output Buffer and Tum-Off Oslay

tCEHQZ

toFF

0

20

Output Data Hold Time from Column Address

tAXQX

tAOH

5

Output Data Enable Time from Write

twHQV

tow

-

20

-

20

tr

tr

3

50

3

50

tREHREL

tRP

50

-

60

tRELREH

tRAS

70

10,000

tRELREH

tRASC

70

100,000

Random Read or Write Cycle Time

tRELREL

Read-Write Cycle Time

tRELREL
tAVAV

tsc

40

Static Column Mode Cycle Time
Static Column Mode Read-Write Cycle Time

Transition Time (Rise and Fall)

FiAS Precharge Time
FiAS Pulse Width
FiAS Pulse Width (Static

Column Mode)

25
35

65

-

205
46

-

25

40
75

0

-

0

20

Max

180

-

ns

6

ns

5

100

ns

6,7

30

ns

6,8

50

ns

6,9

96

ns

6,10
11

246

55
135

-

30

ns
ns

6

-

ns

-

30

ns

3

50

ns

-

70

-

ns

80

10,000

100

10,000

80

100,000

100

100,000

ns
ns
ns

5

-

tCELREH

tRSH

25

-

25

-

30

tRELCEH

tcSH

70

-

80

-

100

-

CS Pulse Width

tcELCEH

tcs

25

10,000

25

10,000

30

10,000

tcELCEH

tcsc

25

100,000

25

100,000

30

100,000

tRELCEL

CS Pulse Width (Static Column Mode)
FiAS to CS Oslay Time
FiAS to Column Addrass Delay Time
CS to ~ Precharge Time

tRCD

20

46

20

55

25

70

tRELAV

tRAD

15

35

15

40

20

50

tCEHREL

tCRP

5

CS Precharge Time
CS Precharge Time (Static Column

tCEHCEL

tCPN

10

tCEHCEL

tcp

10

Row Address Setup Time

tAVREL

tASR

0

Row Address Hold Time

tRELAX

tRAH

10

Column Address Setup Time

tAVCEL

tASC

0

Column Address Hold Time

tCELAX

tcAH

15

Write Address Hold Time Referenced to ~

tRELAX

tAWR

55

Column Address Hold Time Referenced to

tRELAX

tAR

85

tAVREH

tRAL

35

FiAS
Column Address to ~ Lead Time

-

-

ns

0

CS to fiAS Hold Time

Mode)

ns

0

FiAS to CS Hold Time

-

Unit Not..

Min

5
10
10
0
10

-

5
15
10
0
15

0

-

0

15

-

20

60
96

40

-

75
115
50

-

-

6

ns

ns
ns
·ns
ns
ns
ns
ns

12
13

ns
ns
ns

ns
ns
ns

ns

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition timee are measured between VIH and VIL.
2. An initial pause of 200 ps is required atter power-up followed by 8 FiAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements tr = 5.0 ns.
5. Tha specifications for tRC (min) and tRMW (min) are used only to indicate cycle time at which proper operation over the full temperature
range (OOC sTA s700C) is essured.
6. Measured with a current load equivalent to 2 TTL (- 200 pA, + 4 mAl loads and 100 pF with the data output trip points set at
VOH =2.0 V and VOL =0.8 V.
7. Assumes that tRCDstRCD (max).
8. Assumes that tRCD ",tRCD (max).
9. Assumes that tRAD",tRAD (max).
10. Assumes that tLWADstLWAD (max).
11. toFF (max) andlor tGZ define the time at which the output achieves the open circuit condition and i. not referenced to output voltage
levels.
12. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by tcAC.
13. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) i. specified as a reference point only; if tRAD is
greater than the specified tRAD (max), then access time is controlled exclusively by tM.

MOTOROLA MEMORY DATA
2-290

MCM514258A

READ. WRITE.-AND READ-WRITE CYCLES IContinuedl
Symbol
MCM&1421i8A-70 MCM61421i8A-80 MCM61421i8A-10
Param_
Unit No_
Max
Min
Max
Min
Max
Standard Alternate Min
Column Addrea Hold Time Referenced to
10
10
10
ns
14
tAH
tREHAX

JIA!

Last Write to Column Address Delay Time
Last Write to Column Addrea Hold Time
Reed Command Setup Time Referenced to
~

Read Command Hold Time Referenced to ~
Reed Command Hold Tima Referenced to

JIA!
Write Command Hold Time IOutput Data
Olssblel
Write Command Hold Time Referencad to

JIA!
Write Command Pulsa Width
Write Inactive Time
Write Command to RA! Lead Time
Write Command to ~ Lead Time
Oats In Setup Time
Oats In Hold TIma
Data In Hold Tome Referenced to JIA!
Refreeh Period
Write Command Setup TunelOutput Data
Diaablel
~ to Write Delay IRW Cyclel
JIA! to Write Delay IRW CVclaI
Column Addrea to Write Delay Time
~ Setup Time for ~ Before JIA! Refreeh
~ Hold Time for ~ Bafora JIA! Refreeh
JIA! Pracharge to ~ Activa TIma
~ Pracharge Time for ~ Bafora JIA!
Countar Teat
RA! Hold TIma Referencad to t;
t; Accass Tune
t; to Data Delay
Output Buffar Tum-off Delay Time from t;
t; Command Hold Time

ZO

30

ZO

35

25

65

-

75

-

95

0

-

0

tRCH
tRRH

0

0

tcEHWH

twCH

15

IRELWH

twCR

65

twLWH
twHWL
twLREH
twLCEH
tOVCEL
tcELOX
tRELOX
tRVRV

twP

15

twl
tRWL

10

-

twLAV
twLAX
twHCEL

tLWAO
tAHLW
tRCS

tcEHWX
IREHWX

twLCEL

tcwL
tos
tDH
toHR
IRFSH
twcs

0

ZO
ZO
0
15
65

0
65
100

tCELWL
tRELWL
tAVWL
tCELREL
tRELCEH
tREHCEL
tCEHCEL

tcwD
IRWD
t/lWO

tcPT

0
40

tGLREH
tGLQV

tROH

10

IGHDX
tGHOZ
twLGL

tcSR
tcHR
IRpc

IGA
tGO

IGZ
tGH

65
10
30

8

-

-

25

ZO
0
ZO

ZO

-

0
15
60
15
10

ZO
20
0
16
60

0
65
110
70
10
30
0
40
10'

-

-

8

-

-

-

26

ZO
0
20

20

-

0
0
0

ZO
75

ZO
10
25
25
0
ZO
75

0
65
136
86
10
30
0
50

46

-

ns
ns
ns

15

no

16

-

ns

16

-

no

17

-

no

-

no

8

-

-

-

ns

no

no
no

18

no

18

ns
me

ns

17

ns
ns
n.
ns
n8

17

no
ns

25

ns
ns

26

-

no

0

25

26

-

ns
na

20

-

17
17

II

NOTES:
14. tAH must be met for a reed cycle.
15. Oparation within the tLWAD lmaxllimit enBUras that tALW lmaxl can be met. tLWAD lmaxl is apecIfied as a rafaren08 point only; if ILWAO
Is graatar than the apeciflsd tLWAD lmax) limit. than 8CC888 time Is controlled exctuslvely by tAA'
16. EIther IRRH or IRCH must be aatIafied for a reed evele.
17. twCH. twCS. IRWD. tcwO. and t/lWD are not raatrictIve operating paremetars. Thay are included in the data sheat 88 electrical
characterlatica only; if twcs~twcs Iminl and twCH~twCH Imlnl. the cycle is an aer/y write cycle and the data out pin will remain
open circuit Ihigh irnpadanoal throughout the entire cycle; if tcwo~tcwD Iminl. tRWD~tRWD Imlnl. and t/lWD~t/lWD (mini. the
cycle is a reed-write evele and the data out will contain data read from the selected cell. if neither of theee eata of conditions is satlalied.
the condition of the data out (at accass timel is indatarrninata.
IS. Theea paramataIB are referenoad to ~ leedlng edge In random write evel.. and to W leading edge In late write or reed-write evel...

MOTOROLA MEMORY DATA

2-291

•

MCM514258A

•

READ CYCLE

VIH -

-----i.

RAS
VIL -

VIH-

ADDRESSES

VOH000·003

-----VOL -

EARLY WRITE CYCLE
(G,18 Don't Carel

i+-------\ftAS-------.i
VIH -

------1.14----

iiJJ

VIH - 'W"'"1l'"'"O""" ..r-::::"":,,...

ADDRESSES

VIL - ~~r...JI.,..:=::;:;::.~
VIH - ,""f"'7f"'7~f"'7~r-,.t"""

Vi
VIL - L..lo'-''-'L..lo'-'L..loy.''_lI~=--+-_+--------------oI~''-lI:.....lj~~...¥-

VIH000-003
VIL -

---------<1

VALID DATA IN
1)---------HI6H Z - - - - - - - ...-----~

MOTOROLA MEMORY DATA
2-292

MCM514258A

G CONTROLLED LATE WRITE CYCLE

•
W

ii

VIH - "r?r?:""7I:""X"""7t""'7r"'lr':1t""l"'r?:""'lI:~~
VIL -

~~'-lo:...lL.~:lL..:IoL..:ll...j/,~~'¥";IoL..:lY4_ _ _.......;'f-lIt....lI~....lIL..~~"--l'-"'''''''''''''''''''''''~''--l'-''....II

VIH - ~~~~-r-~~""'7'I:*----++-""*,"""l'r~~'t""'lI~""'lI:""7t""'7r":or"'l"'t'"7I'""'lI:""7t""~~,,

READ-WRITE CYCLE

~-------------------------~MW------------------------~
~---------------------~M----------------------~
VIHRAS
VIL-

~==~;===~~====~~~SH~~~~------------~

""'---...
~CD

IRSH--------------+....

~-------------tcs-------------~~

VIH-

CS
vIL.....- - - - - - - - - - - - - - - - - tRAL----------------++I
VIHADDRESSES

COLUMN ADDRESS
VIL~----_r-----~~-----------~

14--------

~WDI-------.....,
~------+_----_r- tR~I---------------__.!

VIH-

W
VILVIH-

ii
VIL-

VIHNDHDQO-OQ3

- - - - - HIGH z

----t--"\I

VILNOL-

MOTOROLA MEMORY DATA
2-293

MCM514258A

•

STATIC COLUMN MODE READ CYCLE

ADORESSES

Vi

Ii

VOH-

OOO.lJ03

-----

STATIC COLUMN MODE EARLY WRITE CYCLE (AI

(ii Is Don"t Care)

VIH-

RAS
Vll-

VIH-

ADDRESSES
Vll-

VIH-

CS
Vll-

VIH-

Vi
VIL -

VIH-

000-003
VIL -

MOTOROLA MEMORY DATA
2-294

MCM514258A

STATIC COWMN MODE EARLY WRITE CYCLE IB)
10 Is Don't Care'
VIHRAS
VIl-

'IHADDRESSES
VIl-

VIH-

CS
'Il-

'IH-

i

Vn.-

YJHNDHDDO-D113
VaJYDL -

STATIC COLUMN MODE READ-WRITE CYCLE
/4-------------tRASC----------~

'IHRAS

tSRMW
VII-

COLUMN
ADDRESS

ADDRESSES
VIl-

COlUMN
ADDRESS
tRAl

Vut-

l:!
Vll-

'IH-

i

Vll-

I!"

'IHVIl-

VIHiVoH-

~

VllNOl-

------------~~;~

;

--....~I~..---REAO.WRITE ----'.-tl
MOTOROLA MEMORY DATA
2-295

MCM514258A

..

STATIC COLUMN MODE READ/WRITE MIXED CYCLE
VIH-

liA!
VIlVIH-

Ci
VIL-

VIHADDRESSES
VIL VIH-

if
VIl-

6"

VIHVIL -

000-003

VIHiVOHVILiVOL -

VAUD
DATA OllT

RAS ONLY REFRESH CYCLE
cW and i'I are Don't Carel

~-------------------~C--------------------~~
VIH-

liA!

Ci
VIlVIHADDRESSES
VIL -

CS BEFORE RAS REFRESH CYCLE
IW, i'I, and AO to A8 are Don't Carel
~--------------~c----------------~
.&-----~ t4----~S----__+t

i-----"""-

tcPN-f---I~

Ci

VIHVIL- _ __

VOH------;..

000-003 VOL- _ _ _ _ _...:IrD------------~Z-----------MOTOROLA MEMORY DATA
2-296

MCM514258A

HIDDEN REFRESH CYCLE (READI
i+-_ _ _ _ _ _ t R c - - - - - - _ I + - - - - - - t R c - - - - - - - + t
i+-----tRAS------'l"i

,J.---i.

I""1-----tRAS----+i

.r--""",-

VIH-

ADDRESSES
VIL -

VOHDIl0-DQ3

----HIGH Z

----<1

VALID DATA OUT

VOL -

HIDDEN REFRESH CYCLE (EARLY WRITE)
Iii Ie Don't Carel
-----~~~------tRc------~

m

VIH - - - " : I I . -

.J,:--.....,:l. footl-----IftAS------l-t .II:---s..

VIL-

VIH-

ADDRESSES
VIL -

MOTOROLA MEMORY DATA
2-'JJ11

•

MCM514258A

•

CS BEFORE RAS REFRESH COUNTER TEST CYCLE
j4------------IRAS----------+j
_

VIH- - - - " " " ' L

RAS

~Il-

..10:----.1..
1+------IRSH-------1~

+1-----

.Jo,---......,oL foof__--- ICS ----~ ...1......

j4---H-----IRAl----++_~

BUD CYCLE

VIH - 7r~~r7I~'"""A'~~~r'7I:"'7\. J.:--~i....-----..,C""Ol"'UM"'N"...---....l..-I-....:...-I--.L. JO~"""'''''
ADDRESSES Vil -

W-"-l""-l<[.",lij'-X._l'...lC...~"-l""-l<[.",lij'..JI l=-_-:-1r-____..::A:::OO:::R:;: ES:: ,S---'l'""T-T"":'~

...............L.

VIH- "A'~~~'I""'7'.....,.r'7I:""7t'"A'"~~~.....t-+---------__t+_+--~Irl~

if Vil _ ................................."'-......,....."-".............~

~----IROH--+H~

VIH - ~""'Ir""A'~"X""1r"K"'"lIt""""l~,......,.~....,......,......,......,..L-ft-.,....,...

ii

Vil -

~-l'.~.JoL...lC....¥_"-l~'-lo~~_l'.~..lC....ltr+~~F--I_ _ _ _...........,.i_¥:....l(r~.JoL...lC....¥-~

VOH000·003 VOl- - - - - - - - -

VIH - ""7t''''""7t"";'''''t"""l'I~'''""7t"";''''~~
ADDRESSES

Jo.....---:'::=::----:!I. A""T~7t"";""~""*'7t""~~~A'"~~

Vil - ..:L~~IL..lo~~~~~~-» "l'--'""""'l'::::=::::....-.... " ............................-><.-'!-............................................'-o.;

WVIHVil - ...¥.-"-JI.-".....l(......l(......l(._l'.....lL..~...JL....JL..JoL."'""_++------""""'4::.lO:....lC.....lC.._l'_~~.JoL....JL....x.....x.....x..

-<1

000-003 VIH - - - - - - H I G H Z- -_ _ _
Vll-,o..--:-;----.......r

READ-WRITE CYCLE

II

ii VIHVil -

.:..lI.............-".....l(.~..K...~.¥-.loL..l"-l"-"~~....liot.....K.!""""-+_

MOTOROLA MEMORY DATA
2-298

MCM514258A

When either the CS or G clock transitions to inactive, the
output will switch to High Z, toFF or tGZ after inactive
transition.

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required
for the intemal substrate generator to establish the correct
bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clockl to initialize all
dynamic nodes within the RAM. During an extended inactive
state (greater than 8 milliseconds with the device powered upl,
a wake up sequence of eight active cycles is necessary to
assure proper operation.

WRITE CYCLE
The DRAM may be written with any of four cycles: early
write, late write and "static column mode" early write, and
read-write. Early and late write modes are discussad here, while
static column mode write operations are covered in another
section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
(VIL levell. Early and late write modes are distinguished by the
active transition of W with respect to CS leading edge. Minimum active time tRAS and tcs, and precharge time tRP apply
to write mode, as in the read mode.
.An early write cycle is characterized by W active transition
at minimum time twcs before CS active transition. Column
address set up and hold times ItASC, tCAHl, and data in (DI
set up and hold times (tDS, !ru:I1 are referenced to CS in an
early write cycle. RAS and CS clocks must stay active for
tRWL and tCWL, respectively, after the start of the early write
operation to complete the cycle.
remains High Z throughout an early write cycle because
W active transition precedes or coincides with CS active transition, keeping data-out buffers disabled effectively disabling

ADDRESSING THE RAM
The nine address pins on the device are time multiplexed at
the beginning of a memory cycle by the row address strobe
(RASI clock, into two seperate 9-bit address fields. A total of
eighteen address bits, nine rows and nine columns, will decode
one of the 262,144 bit locations in the device. RAS active
transition latches the row address field. Column addresses are
not latched, hence the "static column" designation of this
device. Chip select (CSI active transition (active=VIL tRCD
minimuml follows RAS on all read, write, or read-write cycles,
and is independent of column address. The static column
feature allows greater flexibility in setting up the external external column addresses into the RAM.
There are two other variations in addressing the 256K x 4
RAM: RAS only refresh cycle and CS before RAS refresh
cycle. Both are discussad in seperate sections that follow.

o

G.

A late write cycle (referred to as G controlled writel occurs
when W active transition is made after CS active transition.
W active transition could be delayed for almost 10 microseconds after CS active transition, (tRAD + tASC + tRWL +
2tpitRAS, if other timing minimums (tASC, tRWL, and tTl
are maintained. Column address and D timing perameters are
referenced to W active transition in a late write cycle. Output
buffers are enabled by CS active transition but 0 may be
indeterminate-see note 17 of AC operating conditions tebla.
Parameters tRWL and tCWL also apply to late write cycles.

READ CYCLE
The DRAM may be read with four different cycles: random
read cycle, read-write cycle, and "static column mode" read,
and read-write. The random read cycle is outlined here, while
the other cycles are discussad in seperate sections.
The random read cycle begins as described in ADDRESSING THE RAM, with RAS active transition latching the dasired row. The write (WI input level must be high (VIHI, tRCS
(minimuml before the CS active transition, to enable read
mode. A valid column address can be provided at any time
(tRAD mlnlmuml, independent of the CS active transition.
Both the RAS and CS clocks trigger a sequence of events
which are controlled by several delayed intemal clocks. The
internal clocks are linked in such a manner that the read access
time of the device is independent of the address multiplex
window. Both CS and output enable (GI control read access
time: CS and G must be active land column address must be
valid I by tRCD maximum, and tRAC-tGA minimum, respectively, to guarantee valid date out (01 at tRAC (access time
from RAS active transitionl. If either tRCD maximum is exceeded or G active transition does not occur in time, read
access time is determined by the CS andlor G clock active
transition (tCAC tGAI.
The RAS and CS clocks must remain active for a minimum
time of tRAS and tcs, respectively, to complete the read cycle.
The column address must remain valid for tAH after RAS
inactive transition to complete the read cycle. W must remain
high throughout the cycle, and for time tRRH or tRCH after
RAS or CS inactive transition, respectively, to maintein the
data at that bit location. Once RAS transitions to inactive, it
must remain inactive for a minimum time of tRP to precharge
the internal device circuitry for the next active cycle. 0 is valid,
but not latched, as long as the CS and G clocks are active.

READ-WRITE CYCLE
A read-writa cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically
a late write cycle, as discussad in the WRITE CYCLE saction,
except W must remain high for tCWD and/or tAWD minimum,
to guarantee valid 0 before writing the bit.
STATIC COLUMN MODE CYCLES
Static column mode refers to multiple successive data operations performed et any or all 512 column locations on the
selected row of the 256 x 4 dynamic RAM during one RAS
cycle. Read access time of multiple operations (tM or tCAcl
is considerably faster than the regular RAS clock access time
tRAC. Multiple operations can be performed simply by keeping
RAS active. CS may be toggled between active and inactive
states at any time within the RAS cycle.
Once the timing requirements for the initial read, write, or
read-write cycle are met and RAS remains low, the device is
ready for the next operation. Operations can be intermixed in
any order, at any column address, subject to normal operating
conditions previousty described. Every write operation must
be clocked with either CS or W, as indicated in static column

MOTOROLA MEMORY DATA
2-299

MCM514258A

•

mode eerly write cycle timing diagrams A and B. Column
address and [) timing parameters are referenced to the signal
clocking the write operation. CS must be toggled inactive (tCPI
to perform a read operation after an early write operation (to
tum output onl, as indicated in static column mode reed!
write mixed cycle timing diagram. The maximum number of
consecutive operations is limited by tRASC. The cycle ends
when RAS transitions to inactive.

that generates the row address to be refreshed. External address lines are ignored during the automatic refresh cycle. The
output buffer remains at the same state it was in during the
previous cycle (hidden refresh).
Hidden Refraeh
Hidden refresh allows refresh cycles to occur while mainteining
valid date st the output pin. Holding CS active at the end of
a read or write cycle, while RAS cycles inactive for tRP and
back to active, starts the hidden refresh. This is essentially the
execution of a CS before RAS refresh from a cycle in progress
(_ Figure 11.

REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge degrades with
time and temperature, thus each bit must be periodically ra- '
freehed (recharged I to maintein the correct bit state. Bits in
the MCM514268A require refresh every 8 milliseconds.
Refresh is accomplished by cycling through the 512 row
addresses in sequence within the specified refresh time. All
the bits on a row are refreshed simulteneously when the row
is addressed. Distributed refresh implies a row refresh every
15.6 microseconds for the MCM514268A. Burst refresh, a refresh of all 512 rows consecutively, must be performed every
8 milliseconds on the MCM514268A.
A normal read, write, or read-write operation to the RAM
will refresh all the bits (20481 associated with the particular
row decoded. Threa other methods of refresh, RAS only
refresh, CS before RAS refr..h, and hidden refresh are
available on this device for greeter system flexibility.

CS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested
with a CS before RAS refraeh counter teet. This test is
performed with a read-write operation. During the test, the
internal refresh counter generates the row address, while the
extemal address supplies the column address. The entire array
is refreshed after 512 test cycles, as indicated by the check
dsta written in each row. Sea CS before RAS refraeh
counter teet cycle timing diagram.
The test can be performed after a minimum of eight CS
before RAS initialization cycles. Test procedure:
1.
2.

RAS-Only Refresh
RAS-only refresh consists of RAS transition to active, latching
the row address to be refreshed, while CS remains high NIH)
throughout the cycle. An extemel counter is employed to
ensure all rows are refreshed within the specified limit.

3.

CS Before RAS Refraeh

5.

CS before RAS refresh is enabled by bringing CS active before
RAS. This clock order activates an internal refresh counter

6.

4.

Write "O"s into all memory cells with normal write mode.
Select a column address, read "0" out and write "1" into
the cell by performing the CS before RAS refresh
counter teet, reed-write cycle. Repeat this operation
512 times.
Read the "l"s which were written in step 2 in normal read
mode.
Using the same column address as in step 2, read "1"
out and write "0" into the cell by performing the CS
before RAS refraeh counter t ..t, read-write cycle.
Repeat this operation 512 times.
Read "O"s which ware written at in step 4 in normal read
mode.
Repeat steps 1 to 5 using complement dsta.

m

CSBEFORE
REFRESH CYCLE

Q -

HIGH Z -+--~

VALID DATA.lJUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA
2-300

MCM514258A

ORDERING INFORMATION
IOrder by Full Part Number)

MCM

Motorola Memory Prefix
Part Number

T

1
T
T
T
x

XX

XX

S _ _ _ _ (R2-T............. -...,
Speed (70=70 ns, 80=80 ns, 10= 100 ns)
Package (P=Plastic DIP, J=Plastic SO
with J leads, Z = Plastic ZIP)

Full Part Numbars-MCM514258AP70
MCM514257APSO
MCM514258AP10

MCM514258AJ70
MCM514258AJ80
MCM514258AJ10

MCM514258AJ70R2
MCM514258AJ80R2
MCM514258AJ10R2

MOTOROLA MEMORY DATA
2-301

MCM514258AZ70
MCM514258AZ80
MCM514258AZ10

•

•

MOTOROLA MEMORY DATA·

2-3112

DRAM Modules . .

MOTOROLA MEMORY DATA
3-1

•

MOTOROLA MEMORY DATA

3-2

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM32100
MCM32L100

1M x 32 Bit Dynamic Random
Access Memory Module
The MCM32100S is a 32M, dynamic random access memory (DRAM) module
organized as 1,048,576 x 32 bits. The module is a 72-lead single-in-line memory
module (SIMM) consisting of eight MCM514400 DRAMs housed in standard 350-miiwide SOJ packages mounted on a substrate along with a 0.22 I1F (min) decoupling
capacitor mounted under each DRAM. The MCM514400 is a CMOS high speed, dynamic random access memory organized as 1,048,576 four-bit words and fabricated
with CMOS silicon-gate process technology.
•
•
•
•
•
•
•
•
•
•
•
•
•

Three-State Data Output
Early-WrHe Common 1/0 Capability
Fast Page Mode Capability
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh:
MCM32100S = 16 ms (Max)
MCM32L 1OOS = 128 ms (Max)
Consists of Eight 1M x 4 DRAMs and Eight 0.22 I1F (Min) Decoupling CapacHors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access TIme (tRAC):
MCM32100S-80 = 80 ns (Max)
MCM321OOS-10 = 100 ns (Max)
Low Active Power Dissipation:
MCM32100S-80 = 4.62 W (Max)
MCM32100S-10 = 3.96 W (Max)
Low Standby Power Dissipation:
TTL Levels = 88 mW (Max)
CMOS Levels = 44 mW (Max, MCM32100S)
CMOS Levels = 18 mW (Max, MCM32Ll00S)

PINOUT
Pin
1

D
D
D
D
36
37

PIN NAMES

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

VSS

13

AI

25

DQ22

37

NC

49

DOS

61

0013

2

000

14

A2

26

007

36

NC

50

0024

62

0030

3

0016

15

A3

27

D023

39

Vss

51

D09

63

0014

4

001

16

A4

28

A7

40

CASO

52

0025

64

0Q31

5

0017 - 17

AS

29

NC

41

CAS2

53

0010

65

0015

6

002

18

A6

30

Vee

42

CAS3

54

0026

66

NC

7

0018

19

NC

31

AS

43

CASI

55

0011

67

POI

8

003

20

DQ4

32

A9

44

RASO

56

0027

68

P02

9

0019

21

0020

33

NC

45

NC

57

0012

69

PD3

10

Vee

22

DOS

34

RAS2

46

NC

58

0028

70

PD4

11

NC

23

0021

35

NC

47

W

59

VCC

71

NC

12

AO

24

D06

36

NC

46

NC

60

D029

72

VSS

MOTOROLA MEMORY DATA
3-3

AO--A9 ................ Address Inputs
DQO--0Q31 ......... Data Input/Output
CASQ-CAS3 ... Column Address Strobe
PD1-PD4 ..•......... Presence Detect
RASO, RAS2 ••...• Row Address Strobe
'Ii ................... ReadlWrite Input
VCC ................... Power (+ 5 V)
VSS ........................ Ground
NC .................... No Connection
All power supply and ground pins must be
connected for proper operation of the device.

MCM32100-MCM32L100

BLOCK DIAGRAM

..

A~A9

1/01
1/02
1/03
V04

000
001
002
003

A~A9

V01
1102
1/03
1/04

DQ4
DQ5
006
007

A~

1/01
1/02
1/03
1/04

DQ6
009
0010
0011

A~A9

V01
V02
1/03
1/04

0012
0013
0014
0015

A~A9

1/01
V02
V03
V04

0016
0017
0018
0019

~A9

V01
V02
V03
V04

0020
0021
0022
0023
0024

A~A9

V01
V02
V03
V04

A~A9

V01
V02
V03
V04

0028
0029
0030
0031

CAS
RAS

r OE
r OE
rOE
r OE

iN

CAS
RAS

iN

CAS
RAS

iN

CAS
RAS

iN

CAS
RAS

r OE
rOE
rOE
rOE

iN

CAS
RAS

iN

CAS
RAS

iN

CAS
RAS

iN

I

iN

0026
0027

I

~

•

UD-U7

--------------T
......-----.......,~.

UD-U7

Vee
VSS

DQ25

I

0.2211F (MIN)

PRESENCE DETECT PIN OUT

Pin Name

70na

SOns

100ns

PD1
PD2
PD3
PD4

VSS
VSS
VSS

VSS
VSS

NC

VSS

VSS
VSS
VSS
VSS

NC

MOTOROLA MEMORY DATA
3-4

MCM321oo- MCM32L100

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Un"

VCC

-I to+ 7

V

Yin, Vout

-1 to+7

V
mA

Power Supply Voltage
Voltage Relative to VSS
(For Any Pin Except VCC)
Data Output Current per DO Pin

lout

50

Power Dissipation

Po

4.8

W

Operating Temperature Range

TA

Oto+70

·C

Storage Temperature Range

Tstg

-25to+125

·C

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to these high impedence circuits.

NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Vee =5.0 V ± 10%, TA =0 to 70·e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameler
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notee

VCC

4.5

5.0

5.5

V

I

VSS

0

0

0

VIH

2.4

V

1

VIL

-

6.5

-1.0

0.8

V

I

Min

Max

Un"

Notee

mA

2

Logic High Voltage, All Inputs
Logic Low Voltage, All Inputs

RECOMMENDED OPERATING CONDITIONS
Characteristic

Symbol

VCC Power Supply Current
MCM321 00-80, tRC = 150 ns
MCM321 00-1 0, tRC = 180 ns

ICCI

VCC Power Supply Current (Standby) (RAS = CAS = VIH)

ICC2

VCC Power Supply Current During RAS only Refresh Cycles
MCM32100-BO,tRC = 150 ns
MCM32100-IO,tRC = 180 ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle
MCM32100-80,tpC = 50 ns
MCM321 00-1 0, tpc = 60 ns

ICC4

VCC Power Supply Current (Standby) (RAS =CAS =VCC - 0.2 V)

MCM32100
MCM32Ll00

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM32100-80, tRC =150 ns
MCM32100-IO,tRC = 180 ns

ICC6

=

~ P~ Supply Current Battery Back~ Mode (tRC = 1251'S; tRAS IlLS;
CAS CAS before RAS Cycling or 0.2V; W, DO, Ao--A9 = VCC-O.2V or 0.2V)

=

ICC5

-

840
720
16

mA
mA

2

mA

2,3

840
720
560
480
8
3.2

mA
mA

2

mA

2,4

840

720

ICC7

-

4

Input Leakage Current (VSS S Vln S VCC)

Ilkg(l)

-80

+80

Output Leakage Current (CAS at logic I, Vss SVoutS VCC)

Ilkg(O)

-10

10

Output High Voltage (IOH =- 5 mAl

VOH

2.4

-

V

Output Low Voltage (IOL =4.2 mAl

VOL

-

0.4

V

MCM32L100 only

IIA
IIA

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loeding'-!!!!!L..lL.:"-lI:~"-lI:JF

CAS

ADDRESSES

W

toFF ,..1--+1
DO VOH (DATA OUT) VOL _

---------t-f

VALID DATA

HIDDEN REFRESH CYCLE (WRITE)
----+i~----tAAS

RAS

VIH

-

VIL

-

VIH CAS
VIL

-

VIL

-

VIH

-

VIL

-

ADDRESSES

W

DO
(DATA IN)

VIH VIL

-

MOTOROLA MEMORY DATA
3-11

MCM32100- MCM32L100

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
tRAS --------1~
1 + - - tRSH

4

RAS

•

VIH VIL -

CAS

VIH VIL -

VIH ADDRESSES
VIL READ CYCLE

DO VOH (DATA OUT)

VOL tRCS

W

VIH VIL -

WRITE CYCLE

W

VIH VIL -

DO
(DATA IN)

VIH VIL -

MOTOROLA MEMORY DATA
3-12

MCM32100- MCM32L100

DEVICE INITIALIZATION

mum (tCAS) period for the CAS clock. The RAS clock must

stay inactive for the minimum (tRP) time. The former is for the

On power-up an initial pause of 200 microseconds is required forthe internal substate generator pump to establish the
correct bias voltage. This Is to be followed by a minimum of
eight active cycles olthe row address strobe (clock) to initialize
the various dynamic nodes internal to the module. During an
extended inactive state of the device (greater than 4 milliseconds with device powered up), the wake up sequence (8 active
cycles) will be necessary to assure proper device operation.

completion of the cycle in progress, and the latter Is for the device internal circuitry to be precharged for the next active cycle.
Data out is not latched and is valid as long as the CAS clock
is active; the output will switch to the three-state mode when
the CAS clock goes inactive. To perform a read cycle, the write
(W) input must be held at the VIH level from the time the CAS
clock makes its active transition (tRCS) to the time when ittransitions into the inactive (tRCH) mode.

ADDRESSING THE RAM

WRITE CYCLE

The ten address bus pins on the device are time multiplexed
with two separate 1O-bit address fields that are strobed at the
beginning of the memory cycle by two clocks (active negative)
called the row address strobe (RAS) and the column address
strobe (CAS). A total of twenty address bHs will decode one of
the 1,048,576 word locations in the device. The column address strobe follows the row address strobe by a specified
minimum and maxium time called tRCD, which is the row to
column strobe delay. This time interval is also referred to as the
multiplex window which gives flexibilHy to a system designer
to set up the external addresses into the RAM. These conditions have to be met for normal read or write cycles. This initial
portion of the cycle accomplishes the normal addressing of the
device. These are, however, two other variations in addressing
the module, one is called the RAS only refresh cycle (described later) where a 9-bit row address field is presented on
the input pins and latched by the RAS clock. The most significant bH on Row Address A9 is not required for refresh. The other variation, which is called page mode, allows the user to
column access all words within a selected row. (See PAGEMODE CYCLES section.)

A write cycle is similar to a read cycle except that the write
(W) clock must go active (VIL level) at or before the CAS clock
goes active at a minimum twcs time. If the above condition is
met, then the cycle in progress is referred to as an early write
cycle. In an early write cycle, the write clock and the data in are
referenced to the active transition of the CAS clock edge.
There are two important parameters wHh respect to the write
cycle: the column strobe to write lead time (tCWL) and the row
strobe to write lead time (tRwLl. These define the minimum
time that RAS and CAS clocks need to be active after the write
operation has started (W clock at V,L level).

READ CYCLE
A read cycle is referred to as a normal read cycle to differentiate it from a page mode read cycle, which is covered in a later
section.
The memory read cycle begins with the row addresses valid
and the RAS clock transitioning from V,H to the VIL level. The
CAS clock must also make a transHion from V,H to the VIL level
at the specified tRCD timing limits when the column addresses
are latched. Both the RAS and CAS clocks trigger a sequence
of events which are controlled by several delayed Intemal
clocks. Also, these clocks are linked in such a manner that the
access time of the device is independent of the address multiplex window. The only stipulation is thatthe CAS clock must be
active before or at the tRc~imum specification for an access (data valid) from the RAS clock edge to be guaranteed
(tRAC)' If the tRCJ1!11aximum condition is not met, the access
(tcAC) from the CAS clock active transition will determine read
access time. The extemal CAS signal is ignored until an internal RAS signal is available. This gating feature on the CAS
clock will allow the external CAS signal to become active as
soon as the row address hold time (tRAH) specification has
been met and defines the tRCD minimum specification. The
time difference between tRCD minimum and tRCD maximum
can be used to absorb skew delays in switching the address
bus from the row to column addresses and in generating the
CAS clock.
Once the clocks have become active, they must stay active
for the minimum (tRAS) period for the RAS clock and the mini-

PAGE-MODE CYCLES

Page mode operation allows fast successive data operations at all 1024 column locations on a selected row. Page access (tCAC) is typically half the regular RAS clock access
(tRAC) on the Motorola 1M dynamic RAM. Page mode operation consists of holding the RAS clock active while cycling the
CAS clock to access the column locations determined by the
1O-bit column address field.
The page cycle is always initiated with a row address being
provided and latched by the RASclock, followed by the column
address and CAS clock. From the timing illustrated, the initial
cycle is a normal read or write cycle, that has been previously
described, followed by the shorter CAS cycles (tpC)' The CAS
cycle time (tpC) consists of the CAS clock active time (tCAS),
and CAS clock precharge time (tcp) and two transitions. In
practice, any combination of read and write cycles can be performed to suit a particular application.
REFRESH CYCLES

The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Therefore, to retain the correct information, the module needs to be refreshed at least
once every 16 milliseconds. This is accomplished by sequentially cycling through the 1024 row address locations every 16
milliseconds (i.e., at least one row every 15.6 microseconds).
A normal read or write operation to the module will also refresh
all the words associated with the particular row(s) decoded.
RA8-0nly Refresh

In this refresh method, the system must perform a
RAS-only cycle on 1024 row addresses every 16 milliseconds.
The row addresses are latched in wHh the RAS clock, and the
associated internal row locations are refreshed. As the
heading implies, the CAS clock is not required and must be
inactive or at a V,H level.

MOTOROLA MEMORY DATA
3-13

•

MCM321oo-MCM32L100

CAS Before RAS Refrltsh

•

test is performed with read and write operations. During this
test, the internal refresh counter generates the row address,
while the external address input supplies the column address.
The entire array is refreshed after 1024 test cycles, as indicated by the check data written in each row. See CAS before
RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:

This refresh cycle is initiated when RAS falls, after CAS has
been low (by tCSR)' This activates the internal refresh counter
which generates the row address to be refreshed. Externally
applied addresses are ignored during the automatic refresh
cycle. If the output buffer was off before the automatic refresh
cycle, the output will stay in the high impedance state. If the
output was enabled by CAS in the previous cycle, the data out
will be maintained during the automatic refresh cycle as long
as CAS is held active (hidden refresh).
HIC\den Refresh

1. Write "O"s into all memory cells (normal write mode).
2. Select a column address, and read "0" out of the cell by
performing CAS before RAS refresh counter test, read
cycle. Repeat this operation 1024 times.
3. Select a column address, and write "1" into the cell by
performing CAS before RAS refresh counter test, write
cycle. Repeat this operation 1024 times.
4. Read "1 "s (normal read mode), which were written at step
3.
5. Repeat steps 1 to 4 using complement data.

The hidden refresh method allows refresh cycles to be performed while maintaining valid data at the output pin. Hidden
refresh is performed by holding CAS at VIL and taking RAS
high and after a specified precharge period (tRP), executing a
CAS before RAS refresh cycle. (See Figure 1.)
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of the device can be tested with
a CAS before RAS refresh counter test. This refresh counter

REFRESH

_+I4-_REFRESH

CYCLE

DO -

HIGH·Z

CYCLE

VALID DATA-OUT

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory

prefiX~

32100

32L100

XX

T L
L

°1 r

Part N u m b e r - - - - - - - - - - - - '

Full Part Numbers -

x

Speed (80=80ns, 10=loons)
Package (S = SIMM, SG = Gold Pad SIMM,
SM = Low Height SIMM,
SHG = Gold P"ad Low Height SIMM)

MCM32100S80
MCM321OOSI0

MCM32100SG80
MCM32100SG10

MCM32100SH80
MCM321 OOSHI 0

MCM32100SHG80
MCM321 OOSHGI 0

MCM32L100S80
MCM32L 1OOSI 0

MCM32L100SG80
MCM32Ll00SG10

MCM32L1OOSH80
MCM32LlOOSHI0

MCM32L100SHG80
MCM32Ll00SHG10

NOTE: Contact your Motorola representative for further information on the Gold Pad SIMM packages.

MOTOROLA MEMORY DATA
3-14

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM32130
MCM32L130

1M x 32 Bit Dynamic Random
Access Memory Module
The MCM32130S is a 32M, dynamic random access memory (DRAM) module
organized as 1,048,576 x 32 bits. The module is a 72-lead single-in-line memory
module (SIMM) consisting of eight MCM54400AN DRAMs housed in standard
300-mil-wide SOJ packages mounted on a substrate along with a 0.22 IlF (min) decoupling capacitor mounted under each DRAM. The MCM54400AN is a CMOS high
speed, dynamic random access memory organized as 1,048,576 four-bit words and
fabricated with CMOS silicon-gate process technology.
• Three-State Data Output
• Early-Write Common 1/0 Capability
• Fast Page Mode Capability
• TTL-Compatible Inputs and Outputs
• RAS Only Refresh
• CAS Before RAS Refresh
• Hidden Refresh
• 1024 Cycle Refresh: MCM32130S = 16 ms (Max)
MCM32L130S = 128 ms (Max)
• Consists of Eight 1M x 4 DRAMs and Eight 0.22 IlF (Min) Decoupling Capacitors
• Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
• Fast Access Time (tRAe): MCM32130S-70 = 70 ns (Max)
MCM32130S-80 = 80 ns (Max)
MCM32130S-10 = 100 ns (Max)
• Low Active Power Dissipation: MCM32130S-70 = 4.40 W (Max)
MCM32130S-80 = 3.74 W (Max)
MCM32130S-10 = 3.30 W (Max)
• Low Standby Power Dissipation: TTL Levels = 88 mW (Max)
CMOS Levels = 44 mW (Max, MCM32130S)
CMOS Levels = 8.8 mW (Max, MCM32L130S)

,0:;-"0

36
37

I

~ .'-------'

72

PINOUT
Pin Name

8

=.
~= 0

PIN NAMES

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

1

Vss

13

Al

25

0022

37

NC

49

DOS

61

0013

2

000

14

A2

26

0Q7

38

NC

50

0024

62

0030

3

0016

15

A3

27

0023

39

Vss

51

009

63

0014

4

001

16

A4

28

A7

40

CASO

52

0025

64

0031

5

0017

17

A5

29

NC

41

CAS2

53

0010

65

0015

6

002

lS

A6

30

VCC

42

CAS3

54

0026

65

NC

7

0018

19

NC

31

AS

43

CASl

55

DOn

67

POl

8

003

20

0Q4

32

A9

44

RASO

56

0027

68

P02

9

0019

21

0020

33

NC

45

NC

57

0012

69

P03

10

VCC

22

005

34

RAS2

46

NC

58

0028

70

P04

11

NC

23

0021

35

NC

47

W

59

VCC

71

NC

12

AO

24

DOS

36

NC

48

NC

60

0029

72

VSS

MOTOROLA MEMORY DATA
3-15

AQ-A9 ................ Address Inputs
DOQ-D031 ......... Data InpuVOutput
CASO-CAS3 ... Column Address Strobe
PD1-PD4 ............ Presence Detect
RASa, RAS2 ...... Row Address Strobe
W................... ReadlWrite Input
VCC ................... Power (+ 5 V)
VSS ........................ Ground
NC .................... No Connection
All power supply and ground pins must be
connected for proper operation of the device.

•

MCM3213O-MCM32L130

BLOCK DIAGRAM

W

VOl
V02
V03
Ao-A9 V04

W

VOl
V02
V03
Ao-A9 V04

CAS
RAS

•

~DE
CAS
RAS

~

DE

Ao-A9

~

Ao-A9

V04

W

VOl
V02
V03
Ao-A9 V04

0016
0017
0018
0019

VOl
V02
1/03

0020
0021
0Q22
0Q23

1/03

CAS
RAS

~

DE

W

Ao-A9

W

Ao-A9

V04

0024
0025
0026
0027

W

VOl
V02
V03
Ao-A9 V04

DQ26
0Q29
0Q30
0031

V02
V03

CAS
RAS

~DE

V04
VOl

CAS
RAS

~DE

0010
0011

1104

W

RAS

~

DOS

D09

0012
0013
0014
0015

CAS

DE

DQ6
007

VOl
1/02

CAS
RAS

DE

DQ4

DOS

VOl
V02
1/03

CAS
RAS

~DE .w

000
001
0Q2
003

I

W

I

Ao-A9
VCC

..

I O.22I1F (MIN)
Vss ---'-------------T
__-----.....

PRESENCE DETECT PIN OUT
Pin Name

70ns

BOns

100ns

POl
P02
P03
P04

VSS
VSS
VSS

VSS
VSS

NC

VSS

VSS
VSS
Vss
Vss

NC

MOTOROLA MEMORY DATA
3-16

UO-U7
Uo-U7

MCM32130· MCM32L130

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

Vee

-1 to+ 7

V

Yin, Vout

-1 to+ 7

V
mA

Power Supply Voltage
Voltage Relative to VSS
(For Any Pin Except Vee)
Data Output Current per DO Pin

'out

50

Power Dissipation

Po

6.0

W

Operating Temperature Range

TA

oto + 70

°e

TSla

-25to+125

°C

Storage Temperature Range

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to these high impedence circuits.

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70 oe, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

a

Logic High Voltage, All Inputs

V,H

2.4

-

6.5

V

1

Logic Low Voltage, All Inputs

V,L

-1.0

-

O.B

V

1

Max

Unit

Notes

BOO
6BO
600

mA

2,3

RECOMMENDED OPERATING CONDITIONS
Characteristic
VCC Power Supply Current

VCC Power Supply Current (Standby) (RAS

MCM32130-70, tRC
MCM32130-BO, tRC
MCM32130-10, tRC

= 130 ns
= 150 ns
= lBO ns

= CAS = V, H)

= 130 ns
= 150 ns
= lBO ns
MCM32130-70, tpc = 45 ns
VCC Power Supply Current
During Fast Page Mode Cycle
MCM32130-80, tpc = 50 ns
MCM32130-1 0, tpc = 60 ns
VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V) MCM32130
VCC Power Supply Current
During RAS only Refresh Cycles

MCM32130-70, tRC
MCM32130-BO, tRC
MCM32130-10, tRC

Symbol

Min

ICC 1

-

ICC2

-

ICC3

-

-

ICC4

= 130 ns
= 150 ns
= 180 ns
~ Power Supply Current Battery Back'!e Mode (tRC = 1251'S; tRAS = 1~s;
CAS = CAS before RAS Cycling or 0.2V; W, DO, AO-A9 = VCC-O.2V or 0.2V)
MCM32130-70, tRC
MCM32130-80, tRC
MCM32130-10, tRC

ICC6

Output Leakage Current (CAS at Logic I, VSS'; Vout'; VCC)

= - 5 mAl
Output Low Voltage (IOL = 4.2 mAl
Output High Voltage (lOH

-

mA
mA

2,3

560
480
440

mA

2,3

8
1.6

mA

BOO
680
600

mA

2

mA

2,4

ICC7

-

2.4

l'k9(1)

-80

+ 80

~

l'kg(O)

-10

10

~

VOH

2.4

-

V

VOL

-

0.4

V

MCM32L 130 only
Input Leakage Current (VSS'; Vin'; VCC)

-

ICC5

MCM32L130
VCC Power Supply Current
During CAS Before RAS Refresh Cycle

-

16
BOO
6BO
600

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and outputloading~imum current is measured at the fastest cycle rate with the output open.
3. Column Address can be changed once or less while RAS = V,L and CAS = V,H.
4. tRAS (MAX) = 1~s is only applied to refresh of battery backup. tRAS (MAX) = 1O~s is applied to functional operating.

MOTOROLA MEMORY DATA
3-17

•

MCM3213O.MCM32L130

CAPACITANCE (f = 1.0 MHz, TA = 25°C,

Vee = 5 V, Periodically Sampled Rather Than 100% Tested)

Characteristic

..

Symbol

Min

Max

Unit

Notes

Input Capacitance (AO-AS)

Cll

-

50

pF

1

Input Capacitance (W)

CI2

-

66

pF

1

Input Capacitance (RASO, RAS2)

CI3

38

pF

1

Input Capacitance (CASO-CAS3)

CI4

24

pF

1

I/O Capacitance (00D-0031)

COO

-

17

pF

1

NOTE: 1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 I!.. t II!.. V.

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee 5.0 V ± 10%, TA 0 to 70 oe, Unless Otherwise Noted)

=

=

READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)
32130.70
32LI30·70

Symbol
Parameter

32130-10
32LI30.10

Std

Ait

Min

Min

Max

Min

Random Read or Write Cycle Time

tRELREL

tRC

130

-

150

-

180

Fast Page Mode Cycle Time

tCELCEL

tpc

45

-

50

-

Access lime from RAS

tRELOV

tRAC

Access lime from CAS

teELOV

Access lime from Column Address

tAVOV

teAC
tAA

Access lime from Precharge CAS

lCEHOV

CAS to Output in Low-Z

teELOX

tePA
tCLZ

Output Buffer and Turn-Off Delay

teEHOZ

tOFF

Transition Time (Rise and Fall)

-

Max

32130-80
32LI30.80

70
20
35
40

0

-

0

20

-

Unit

Notes

ns

5

60

-

SO

-

100

ns

6,7

20

-

25

ns

6,S

50

ns

6,9

55

ns

6

0

-

ns

6

0

20

ns

10

40
45

0

-

0

20

Max

ns

IT

IT

3

50

3

50

3

50

ns

RAS Precharge Time

tREHREL

tRP

50

-

60

-

70

-

ns

RAS Pulse Width

tRELREH

tRAS

70

10k

80

10k

100

10 k

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

70

200k

SO

200 k

100

200k

ns

RAS Hold Time

teELREH

tRSH

20

-

20

25

ns

100

-

55

-

CAS Hold Time

tRELCEH

tCSH

70

-

SO

-

CAS Precharge to RAS Hold Time

teEHREH

tRHCP

40

-

45

-

CAS Pulse Width

tCELCEH

tCAS

20

10k

20

RAS to CAS Delay Time

tRELCEL

tRCO

20

50

RAS to Column Address Delay Time

tRELAV

tRAO

15

35

CAS to RAS Precharge Time

tCEHREL

tCRP

5

CAS Precharge lime

tcEHCEL

tcp

10

ns

ns
ns

10k

25

10k

ns

20

60

25

75

ns

11

15

40

20

50

ns

12

-

5

-

10

10

-

10

-

ns

-

ns

contmuec
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 lIS is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
trans~ion between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range(O·C,; TA'; 70·C) is
assured.
6. Measured with a current load equivalent to 2 TTL (- 200 !lA, + 4 mAl loads and 100 pF with the data outputtrip points set at VOH = 2.0 V and
VOL = O.SV.
7. Assumes that tRCO ,; tRCO (max).
8. Assumes that tRCO ~ tRCO (max).
9. Assumes that tRAO ;" tRAO (max).
10. !oFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operationw~inthetRCO (max) limit ensures thallRAC (max) can be met.tRCO (max) is specified asa reference point only; iflRCO is greater
than the specified tRCO (max) limit, then access time is controlled exclusively to teAC'
12. Operation within the tRAO (max) limit ensures thattRAC (max) can be met. tRAO (max) is specified as a reference point only; iflRAO is greater
than the specified tRAO (max), then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
3-18

MCM32130-MCM32L130

READ AND WRITE CYCLES (Continued)
32130-70
32l130-7D

Symbol
Parameter

Max

32130-80
32l130-00
Min

Max

32130-10
32l130-10
Min

Sid

All

Min

Row Address Setup Time

IAVREl

IASR

0

-

0

-

0

Max

Unll

Noles

Row Address Hold Time

IRELAX

IRAH

10

-

10

-

15

-

Column Address Selup Time

IAVCEL

IASC

0

-

0

0

-

ns

Column Address Hold Time

tcELAX

tcAH

15

-

15

-

20

ns

Column Address 10 RAS Lead Time

IAVREH

tRAl

35

-

40

-

50

-

Read Command Selup Time

twHCEl

IRCS

0

-

0

0

-

ns

Read Command Hold Time
Referenced to CAS

ICEHWX

IRCH

0

0

-

0

-

ns

13

Read Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

0

-

0

-

ns

13

Write Command Hold Time
Referenced to CAS

tcElWH

twCH

15

15

20

-

ns

20

-

ns

20

-

25

-

ns

25

-

ns

ns
ns

ns

Write Command Pulse Width

twLWH

twP

15

Write Command to RAS lead Time

twLREH

tRWL

20

-

Write Command to CAS Lead Time

twLCEH

20

-

20

-

Data in Setup Time

tOVCEL

tcWL
tos

0

-

0

14

tOH

15

15

-

20

-

ns

tcELOX

-

0

Data in Hold Time

ns

14

tRVRV

tRFSH

-

16
128

ms

Write Command Setup Time

twLCEL

0

-

ns

CAS Setup Time for CAS Before RAS
Refresh

5

-

ns

15

-

16
128

-

16
128

twcs

0

0

tRELCEL

tCSR

5

5

-

CAS Hold Time for CAS Before RAS
Refresh

tRELCEH

tcHR

15

15

-

20

-

ns

0

-

0

-

ns

50

-

ns

10

-

ns

10

-

ns

Refresh Period

MCM32130
MCM32L130

-

-

RAS Precharge to CAS Active Time

tREHCEL

tRPC

0

-

CAS Precharge Time for CAS Before
RAS Counter Time

tCEHCEL

tCPT

40

-

40

Write to RAS Precharge Time (CAS
Before RAS Refresh)

twHREL

twRP

10

10

Write to RAS Hold Time (CAS Before
RAS Refresh)

IRELWL

twRH

10

-

10

-

15

NOTES:
13. Either IRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in random write cycles.
15. twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs;;' twcs (min), the cycle
is an earty write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. II this condition is not satisifed,
the condttion of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA

3-19

•

MCM3213O- MCM32L130

READ CYCLE

•
ADDRESSES VIH VIL -CL.....l"--"~ "---r-~

iii V1H V1L -t...::.t....:>t....:>t....:>t....:>y~~

DO

VOH -

- - - - - - HIGHZ - - - - + - - - { I

VALID DATA OUT

vOL -

EARLY WRITE CYCLE

RAS

CAS

V 1H -

V1L -

V 1H -

V1L -

ADDRESSES VIH V1L -

VIH -

iii

.......,.......,.......,.......,.....,.-,.-,.-"

V1L - ~~~~~~~~~f--+--+--~~~~~~~~~~~~~~~~~~~~

MOTOROLA MEMORY DATA
3-20

MCM32130·MCM32L130

FAST PAGE MODE READ CYCLE
_

RAS

V1H - --~

1 4 - - - - - - - - - - - - - tRASP - - - - - - - - - - - - - - 1

V1L 14-----t PC -+---~

"~"'a

DO VOH- - - - - - - - - - { I
vOL -

FAST PAGE MODE EARLY WRITE CYCLE

ADDRESSES VIH V 1L -

V1H - .....,......,.......,.......,...." J,,....-..,.,.,.,.:-:-~

DO
V1L -

....lL...JoL....lL...:.I-V

J<"""":........,.....,.

J:-....,.".,..",....~ x-->..-I"~ J:-.....,.",.,..",.~ ~,......,..............,.....,....,...~

""'--~"";';"-4" "--'oL.....lo~ ~....;.;..-4" "'-''"II''......., "1'----4" "-""--l"--l.~"-lL...JL.~.

MOTOROLA MEMORY DATA
3-21

MCM32130-MCM32L130

RAS ONLY REFRESH CYCLE

(W Is Don't Care)
~-------------------tRC------------------~
1+------

•

__ VIH----...,....-~
V
IL -

tRAS

---------.1

RAS

CAS

_

V1H - ~~~M.,__-H----------------_±,...,......,......,r_-----

r
ADDRESSE<'->J'

tASR~

CAS BEFORE RAS REFRESH CYCLE
(AO-A9 Is Don't Care)

CAS
_

V1H -

V1L -

_ V1H W
VIL-~~*~Y

HIGHZ - - - - - - - - - - - - - -

MOTOROLA MEMORY DATA
3-22

MCM32130-MCM32L130

HIDDEN REFRESH CYCLE (READ)

•
ADDRESSES VIH -

V1L -

iii

V1H -

~~~~~~~-+---r----------~~~~--------~~~~~~~~~7r7r~~

VIL -

--"'--"'--"-",.,..~

DO VOH VOL -

------------------{J

HIDDEN REFRESH CYCLE (EARLY WRITE)

ADDRESSES VIH -

V1L _ V1H W
V IL -

....,......,......,.,.....,.,.....,,~

-"-"-"-"-"~-=F-+--+-------~~..T

DO VIHV1L - £....lL..l.£...l<'-Y

MOTOROLA MEMORY DATA

3-23

MCM32130-MCM32L130

CAS BEFORE RiS REFRESH COUNTER TEST CYCLE

--~i.

•

" " o - - - - - - - - - - - I R A S - - - - - - - - - - " ' i .lI:----oL

Jc----.1

I+------IRSH ------001
i4-----ICAS
r-'---':I,........---

ADDRESSES VVIH ILREAD CYCLE

MOTOROLA MEMORY DATA
3-24

MCM32130-MCM32L130

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the module. During an extended inactive
state (greater than 16 milliseconds with the device powered
up), a wake up sequence of eight active cycles is necessary to
ensure proper operation.

ADDRESSING THE RAM
The ten address pins on the device are time multiplexed at
the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 10-bit address fields. A total of twenty address bits, ten
rows and ten columns, will decode one of the 1,048,576 word
locations in the device. RAS active transition is followed by
CAS active transition (active = VIL,.!BQp minimum) for all read
or write cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system designer flexibility in setting up the external addresses into the
RAM.
The external CAS Signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the module:
RAS only refresh cycle, CAS before RAS refresh cycle,
and page mode. All three are discussed in separate sections
that follow.
READ CYCLE

The DRAM may be read with either a "normal" random read
cycle or a page mode read cycle. The normal read cycle is outlined here, while the page mode cycle is discussed in a separate section.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (W) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The internal clocks are linked in such a manner that the read access
time of the device is independent of the address multiplex window. CAS controls read access time: CAS must be active before or at tRCD maximum to guarantee valid data out (DO) at
tRAC (access time from RAS active tranSition). If the tRCD
maximum is exceeded, read access time is determined by the
CAS clock active transition (tCAC)'
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. Wmust remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data althat bitlocation. Once RAS transitions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitry for the next active
cycle. DO is valid, but not latched, as long as the CAS clock is
active. When the CAS clock transitions to inactive, the output

will switch to High Z (three-state) toFF after the inactive transition.
WRITE CYCLE

The user can write to the DRAM with either an early write or a
page mode early write cycle. Early write mode is discussed
here, while page mode write operations are covered in a separate section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
(Vul. Early write mode is distinguished by the active transition
of W, with respect to CAS. Minimum active time tRAS and
tCAS, and precharge time tRP apply to write mode, as in the
read mode.
An early write cycle is characterized by Wactive transition at
minimum time twcs before CAS active transition. Data in
(DO) is referenced to CAS in an early write cycle. RAS and
CAS clocks must stay active for tRWL and tCWL' respectively,
after the start of the early write operation to complete the cycle.

PAGE MODE CYCLES
Page mode allows fast successive data operations at all
1024 column locations on a selected row of the module. Read
access time in page mode (tCAc) is typically half the regular
RAS clock access time, tRAC' Page mode operation consists
of keeping RAS active while toggling CAS between VIH and
~The row is latched by RAS active transition, while each
CAS active transition allows selection of a new column location
on the row.
A page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for
minimum tcp, while RAS remains low (VIL). The second CAS
active transition while RAS is low initiates the first page mode
cycle (tpc). Either a read or write operation can be performed
in a page mode cycle, subject to the same conditions as in normal operation (previously described). These operations can
be intermixed in consecutive page mode cycles and performed
in any order. The maximum number of consecutive page mode
cycles is limited by tRASP' Page mode operation is ended
when RAS transitions to inactive, coincident with or following
CAS inactive transition.

REFRESH CYCLES
The dynamic RAM design is based on capacitor charge storage for each bit in the array. This charge will tend to degrade
with time and temperature. Each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in the
MCM32130 require refresh every 16 milliseconds, while refresh time for the MCM32L 130 is 128 milliseconds.
This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds forthe MCM32130, and 124.8 microseconds for
the MCM32L 130. Burst refresh, a refresh of all 1024 rows consecutively, must be performed every 16 milliseconds on the
MCM32130 and 128 milliseconds on the MCM32L 130.
A normal read or wriie operation to the RAM will refresh all
the bits associated with the particular row decoded. Three other methods of refresh, RAS-only refresh, CAS before RAS
refresh, and hidden refresh are available on this device for
greater system flexibility.

MOTOROLA MEMORY DATA
3-25

III

MCM32130-MCM32L130

..

RAS·Only Refresh
RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(V IH) throughout the cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.

CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of the device can be tested with
a CAS before RAS refresh counter test. This refresh counter
test is performed with read and write operations. During this
test, the internal refresh counter generates the row address,
while the external address input supplies the column address .
The entire array is refreshed after 1024 test cycles, as indicated by the check data written in each row. See CAS before
RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:

CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order actives an internal refresh counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh cycle. The
output buffer remains at the same state it was in during the previous cycle (hidden refresh). IN must be inactive for time tWRP
before and time !wRH after RAS active transition to prevent
switching the device into a test mode cycle.
Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). IN is subject to the same conditions
with respect to RAS active transition (to prevent test mode
cycle) as in CAS belore RAS refresh.

1. Write "O"s into all memory cells (normal write mode).
2. Select a column address, and read "0" out of the cell by
performing CAS before RAS refresh counter test, read
cycle. Repeat this operation 1024 times.
3. Select a column address, and write "1" into the cell by
performing CAS before RAS refresh counter test, write
cycle. Repeat this operation 1024 times.
4. Read "1 "s (normal read mode), which were written at step
3.
5. Repeat steps 1 to 4 using complement data.

REFRESH
CYCLE

DO -

HIGH·Z

-+

REFRESH
CYCLE

VALID DATA'()UT

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory

prefiX~

32130 or 32L130

I

Part N u m b e r - - - - - - - - _ - - - - I
Full Part Numbers -

x

xx

T T_
~

MCM32100SH70
MCM32100SH80
MCM321 OOSHl

a

MCM32L 100SH70
MCM32L100SH80
MCM32L1OOSHl

a

Speed (70 = 70ns, 80 = 8Ons, 10 = lOOns)
Package (SH = SIMM, SHG = Gold Pad SIMM)

MCM32100SHG70
MCM32100SHG80
MCM32100SHG10
MCM32L100SHG70
MCM32L100SHG80
MCM32L1OOSHGl

MOTOROLA MEMORY DATA

a

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM32200
MCM32L200

2M x 32 Bit Dynamic Random
Access Memory Module
The MCM32200S is a 64M, dynamic random access memory (DRAM) module
organized as 2,097,152 x 32 bits. The module is a 72-lead double sided single-in-line
memory module (SIMM) consisting of sixteen MCM514400 DRAMs housed in standard 350-mil-wide SOJ packages mounted on a substrate along with a 0.22 I1F (min)
decoupling capacitor mounted under each DRAM. The MCM514400 is a CMOS high
speed, dynamic random access memory organized as 1,048,576 four-bit words and
fabricated with CMOS silicon-gate process technology.
• Three-State Data Output
• Early-Write Common I/O Capability
• Fast Page Mode Capability
• TTL-Compatible Inputs and Outputs
• RAS Only Refresh
• CAS Before RAS Refresh
• Hidden Refresh
• 1024 Cycle Refresh:
MCM32200S = 16 ms (Max)
MCM32L200S = 128 ms (Max)
• Consists of Sixteen 1M x 4 DRAMs and Sixteen 0.22 I1F (Min)
Decoupling Capacitors
• Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
• Fast Access Time (tRAC):
MCM32200S-80 = 80 ns (Max)
MCM32200S-10 = 100 ns (Max)
• Low Active Power Dissipation:
MCM32200S-80 = 4.71 W (Max)
MCM32200S-10 = 4.05 W (Max)
• Low Standby Power Dissipation:
TTL Levels = 176 mW (Max)
CMOS Levels = 88 mW (Max, MCM32200S)
CMOS Levels = 36 mW (Max, MCM32L200S)

1

=
=
=
2l
§=
=
~
=
=
2l
§=
§

2l
2l

36

§
§=

0

D
D
D
D

37

D
D
D
72

PINOUT
Pin

Name

Pin

Name

Pin

Name

Pin

Name

1

VSS
OQO

13

Al

25

0022

37

NC

2

14

A2

26

007

38

NC

3

0016

15

A3

27

0023

39

VSS

4

001

16

A4

28

A7

40

CASO

5

0017

17

AS

29

Ne

41

CAS2

6

002

18

AS

30

VCC

42

7

0018

19

NC

31

A8

43

8

003

20

DQ4

32

A9

9

0019

21

0020

33

RAS3

10

VCC

22

005

34

11

NC

23

0021

12

AO

24

DOS

Pin

Name

Pin

Name

49

008

61

0013

50

0024

62

0030

51

0Q9

63

0014

52

0025

64

0031

53

0010

65

0015

CAS3

54

0026

66

NC

CASI

55

0011

67

POI

44

RASO

56

0027

68

P02

45

RASl

57

0012

69

P03

RAS2

46

NC

58

OQ28

70

P04

35

NC

47

W

59

VCC

71

NC

36

NC

48

NC

60

0029

72

VSS

MOTOROLA MEMORY DATA
3-Xl

PIN NAMES
AO-A9 ................ Address Inputs
000-0031 ......... Data InpuVOulput
CASO-CAS3 ... Column Address Strobe
PD1-PD4 ............ Presence Detect
RASO-RAS3 ...... Row Address Strobe
W................... ReadlWrite Input
VCC ................... Power (+ 5 V)
VSS ........................ Ground
NC .................... No Connection
All power supply and ground pins must be
connected for proper operation of the device.

•

MCM32200. MCM32l.2OO

BLOCK DIAGRAM
00(H)03
CAS
RAS

~OE

II

W

ACH.9

1/01
1/02
V03
V04 AG-AfJ

;:::

CAS
RAS

W

OE-....L

004-007

CAS
RAS

~OE

VOl
1/02
1/03
1104

W

AO....AfJ

I

I

1/01
1/02
1/03
1104

1101
1/02
1/03
1/04 AG-AfJ

~

-"

CAS
RAS

W

I

I

OE~

00!HJ011

AO-A9

1/01
1/02
1/03
1/04

W

AO-A9

1/01
1/02
1/03
V04

I

I

CAS
RAS

~OE

W

~

1

AO-A9

W

AO-A9

1/01
1/02
1103
1/04

I

I

W

"
~

-

OE~
CAS
RAS

W

I

I

0016-0019
1101
1102
1/03
1104

OE~

I

1101
1/02
1/03
1104 AO-A9

CAS
RAS

W

OE-....L

002(H)023

CAS
RAS

~OE

W

1101
1/02
1/03
1/04 AO-AfJ

I

CAS
RAS

~OE

CAS
RAS

00120015

CAS
RAS

~OE

1101
1/02
1/03
1/04 AO-A9

~

-

1/01
1/02
1103
1104 AO-A9

"

"

CAS
RAS

W

I

I

OE~

0024-0027

AO-A9

1/01
1/02
1/03
1/04

W

ACH.9

1/01
1/02
1/03
1/04

1

I

CAS
RAS

~OE

W

W

AO-A9
Vee

CAS
RAS

W

0026-0031

CAS
RAS

~OE

1101
1102
1103
1/04 AO-A9

~

;:::

1/01
1/02
1/03
V04 AO-A9

-"

W

I

I

- - - - - - - - - - - - - - - : 1 : - - - - - - -....

UO-U15

0.22 ~F (MIN)

VSS

---------------T
. . . . . ------.. .~.

UO-U15

PRESENCE DETECT PIN OUT

Pin Name

70ns

SOns

100ns

PDl
PD2
PD3

Ne
Ne

Ne
Ne
Ne

Ne
Ne

PD4

VSS

Ne

VSS

MOTOROLA MEMORY DATA
3-28

OE~
CAS
RAS

VSS
VSS

OE~

RAS3

MCM32200-MCM32L200

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-I to+ 7

V

Yin, Vout

-I to+ 7

V
mA

Power Supply Voltage
Voltage Relative to VSS
(For Any Pin Except VCC)
Data Output Current per DQ Pin

lout

50

Power Dissipation

Po

6.42

W

Operating Temperature Range

TA

Oto+ 70

·C

Storage Temperature Range

Tstg

-25to+125

·C

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to these high-impedance circuHs.

NOTE: Permanemdevice damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages lor extended periods of
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
"

Parameter
Supply Voltage (Operating Voltage Range)

Logic High Voltage, All Inputs
Logic Low Voltage, All Inputs

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

I

VSS

0

0

0

VIH

2.4

-

6.5

V

I

VIL

-1.0

-

O.B

V

I

Max

Unit

Notes

mA

2

RECOMMENDED OPERATING CONDITIONS
Characteristic

Symbol

VCC Power Supply Current
MCM32200-BO, tRC =150 ns
MCM32200-10, tRC =IBO ns

ICCI

VCC Power Supply Current (Standby) (RAS =CAS =VIH)

ICC2

VCC Power Supply Current During RAS only Refresh Cycles
MCM32200-B0, tRC = ISO ns
MCM32200-10, tRC =IBO ns

ICC3

VCC Power Supply Currant During Fast Page Mode Cycle
MCM32200-80, tpc = 50 ns
MCM32200-10, tpc =60 ns

ICC4

VCC Power Supply Current (Standby) (RAS =CAS =VCC - 0.2 V

Min

-

856
736

-

856
736

-

576
496

32

mA
mA

2

mA

2,3

ICC5

-

-

16
6.4

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM32200-BO, tRC = ISO ns
MCM32200-10, tRC = IBO ns

ICC6

-

856
736

~

Power Supply Current Battery Backl!e Mode (tRC =1251'S; tRAS = IllS;
CAS =CAS before RAS Cycling or 0.2V; W, DQ, AO-A9 = VCC-{).2V or O.2V)
MCM32L200 only

ICC7

-

B.O

Input Leakage Current (VSS';; Vin';; Vccl

Ilkg(l)

-160

160

Output Leakage Currem (CAS at Logic I, VSS:;; Vout:;; VCC)

Ilkg(O)

-20

20

ItA
ItA

VOH

2.4

-

V

-

0.4

MCM32100
MCM32L200

Output High Voltage (IOH =- 5 mAl
Output Low Voltage (IOL =4.2 mAl

mA
mA

2

mA

2,4

V
VOL
NOTES:
I. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum current Is measured at the fastest cycle rate with the output open.
3. Column Address can be changed once or less while RAS =VIL and CAS =VIH.
4. tRAS (MAX) = II'S is only applied to refresh of battery backup. tRAS (MAX) = lOllS is applied to functional operating.

MOTOROLA MEMORY DATA
3-29

•

MCM32200-MCM32l2OO

CAPACITANCE (I = 1.0 MHz, T A = 25°C, Vee = 5 V, Periodically Sampled Rather Than 100% Tested)
Characteristic

•

Symbol

Input Capacitance (Ao-A9)

Cll

Input Capacitance rN)

CI2

Input Capacitance (RASo-RAS2)

CI3

Input Capacitance (CASO-CAS3)

CI4

I/O Capacitance (000-0031)

COO

Min

Max

Unit

Notas

-

90

pF

1

122

pF.

1

38

pF

1

38

pF

1

24

pF

1

NOTE:
1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 L\. tiL\. V.

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Vee

=5.0 V ± 10%, TA =0 to 70oe, Unless Otherwise Noted)

READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)
MCM32200-80

Symbol
Parameter
Random Read or Write Cycie TIme

Standard
tRELREL

MCM3220D-l0

Alternate

Min

Max

Min

Max

Unit

Notes

tRC

150

5

60

-

ns

50

-

180

80

-

100

ns

6,7

20

-

25

ns

6,8

40

-

50

ns

6,9

45

-

55

ns

6

Page Mode Cycle TIme

teELCEL

tpc

Access Time from RAS

tRELOV

tRAC

ns

tAVOV

tAA

Access Time from Precharge CAS

teEHOV

tCPA

-

CAS to Output in Low-Z

teELOX

tCLZ

0

-

0

-

ns

6

Output Buffer and Tum-Off Delay

tCEHOZ

toFF

0

20

0

20

ns

10

Access Time from CAS
Access Time from Column Address

Transition Time (Rise and Fall)

tCELOV

teAC

IT

IT

3

50

3

50

ns

RAS Precharge Time

tREHREL

tRP

60

-

70

-

ns

RAS Pulse Width

tRELREH

tRAS

80

10,000

100

10,000

ns

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

80

100,000

100

100,000

ns

RASHoldTIme

teELREH

tRSH

25

25

tRELCEH

teSH

80

100

-

ns

CAS Hold Time

-

CAS Pulse Width

tCELCEH

teAS

20

10,000

25

10,000

ns

RAS to CAS Delay Time

tRELCEL

tRCO

20

60

25

75

ns

11

tRAO

15

40

20

50

ns

12

RAS to Column Address Delay TIme

tRELAV

ns

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 j!S is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input Signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VI H) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specification fortRC (min) is used only to indicate cycle time atwhich proper operation overthe full temperature range (O°C:;; TA:;; 70°C) is
assured.
6. Measured with a current load equivalentto 2 TTL (- 200 1lA, + 4 mAl loads and 100 pF with the data outputtrip points set at VOH = 2.0 V and
VOL = 0.8 V.
7. Assumes that tRCO:;; tRCO (max).
8. Assumes that tRCO " tRCO (max).
9. Assumes that tRAO " tRAO (max).
10. toFF (max) defines the time at which the output achieves the open circuit condijion and is not referenced to output voltage levels.
11. Operation within thetRCo (max) limit ensures thattRAC (max) can be met. tRCO (max) is specified as a reference point only; iltRCO is greater
than the specified tRCO (max) limij, then access time is controlled exclusively to teAC'
12. Operation within the tRAO (max) limij ensures tihattRAC (max) can be met. tRAO (max) is specified as a reference point only; iltRAO is greater
than the specified tRAO (max), then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA

3-30

MCM32200-MCM32L200

READ AND WRITE CYCLES (Continued)
Symbol

MCM32200-80

MCM32200-10

Parameter

Standard

Alternate

Min

Max

Min

Max

Unit

CAS to RAS Precharge TIme

tcEHREL

tCRP

5

10

-

ns

CAS Precharge TIme (Page Mode Cyle Only)

tCEHCEL

tcp

10

10

-

ns

tASR

0

a

tRAH

a

-

ns

10

-

Row Address Setup TIme

tAVREL

Row Address Hold TIme

tRELAX

Column Address Setup TIme

15

Notea

•

ns
ns

tAVCEL

tASC

a

Column Address Hold TIme

tcELAX

tCAH

15

-

20

-

ns

Column Address Hold TIme Referenced
toRAS

tRELAX

tAR

60

-

75

-

ns

Column Address to RAS Lead TIme

tAVREH

tRAL

40

-

50

-

ns

Read Command Setup TIme

twHCEL

tRCS

0

-

0

-

ns

Read Command Hold TIme Referenced
to CAS

tcEHWX

tRCH

0

-

a

-

ns

13

Read Command Hold TIme Referenced
toRAS

tREHWX

tRRH

0

-

a

-

ns

13

Write Command Hold TIme Referenced
to CAS

tcELWH

twCH

15

-

20

-

ns

Write Command Hold TIme Referenced
toRAS

tRELWH

twCR

60

-

75

-

ns

Write Command Pulse Width

tWLWH

twP

15

tcWL

20

25

tos

0

-

0

-

ns

tRWL

-

20

20

ns

14

-

20

-

ns

14

Write Command to RAS Lead TIme
Write Command to CAS Lead TIme
Data in Setup TIme

twLREH
twLCEH
tOVCEL

Data in Hold TIme

25

ns
ns

tCELOX

tOH

15

Data in Hold TIme Referenced to RAS

tRELOX

tOHR

60

-

75

-

ns

Refresh Period

tRVRV

tRFSH

-

16
128

-

-

16
128

ms

MCM32200
MCM32L200

-

Write Command Setup TIme

twLCEL

twcs

a

CAS Setup TIme for CAS Before RAS Refresh

tRELCEL

tCSR

10

CAS Hold TIme for CAS Before RAS Refresh

tRELCEH

tcHR

30

CAS Precharge to CAS Active TIme

tREHCEL

tRPC

a

-

CAS Precharge TIme for CAS Before RAS
Counter Test

tCEHCEL

tcPT

40

-

a

-

ns

10

-

ns

30

-

ns

-

ns

a
50

15

ns

CAS Precharge TIme
10
15
ns
tCPN
tCEHCEL
NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in random write cycles.
15. twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs ~ twcs (min), the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is not
satisifed, the condition of the data out (at access time) is indeterminate.
16. To avoid bus contention and potential damage to the module, RASa and RAS1 may not be active low simultaneously. Similarly, RAS2 and
RAS3 may not be simultaneously active low.

MOTOROLA MEMORY DATA
3·31

MCM32200-MCM32L200

READ CYCLE

RAS

•

VIHVIL -

CAS

VIHVIL -

ADDRESSES

VIHVIL -

iii

VIH VIL -

VOHDO
(DATA OUT)
VOL -

MOTOROLA MEMORY DATA

MCM32200-MCM32L200

FAST PAGE MODE READ CYCLE
______~~.-------------tRASP--------------~
RAS

VIH VIL -

VIH CAS
VIL -

ADDRESSES

VIH VIL -

Vi

VIH VIL -

VOH 00
(DATA OUT) VOL _

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

RAS

VIH VIL -

VIH CAS
VIL -

ADDRESSES

VIH VIL -

Vi

VIH VIL -

DO
(DATA IN)

VIH VIL -

MOTOROLA MEMORY DATA

MCM32200-MCM32L200

RR ONLY REFRESH CYCLE
(Wand A9 are Don't Care)

..

I~·-------------~C--------------~

RAS

VIH VIL

CAS

------.ill..·..-------- tRAS - - - - -...llr---''''''-~

-

VIH -

ADDRESSES

DO
(DATA OUT)

VOHVOL _ - - - - - - - - - - - - - - - - - - - HIGH·Z

~ BEFORE RR REFRESH CYCLE

(AO to A9 are Don't Cere)

E

-tRAS~tRC-1.-~·'~

tRPC

-

tcHR

DO

-.lr)-->----------

VOH _ _ _ _ _

(DATA OUT) VOL -

_ _ _ _..11

HIGH·Z - - - - - - - - - - - - - - -

MOTOROLA MEMORY DATA

MCM32200-MCM32L200

HIDDEN REFRESH CYCLE (READ)

RAS

CAS

VIH -

VIH VIL -

ADDRESSES
VIL -

W

VIH

-

VIL -

VOH DO
(DATA OUT)
VOL -

HIDDEN REFRESH CYCLE (WRITE)
- - - -..... 1 4 - - - tRAS
RAS

VIH VIL -

VIH CAS

VIL -

ADDRESSES
VIL

W

DO
(DATA IN)

-

VIH VIL -

VIH VIL

-

•

tDHR

•

MOTOROLA MEMORY DATA

MCM32200-MCM32L200

CAS BEFORE RlS REFRESH COUNTER TEST CYCLE
IRAS ---------II~
140-- IRSH

III
VIHADDRESSES
VIL READ CYCLE
VOH DO
(DATA OUT)
VOL -

W

VIH VIL -

WRITE CYCLE

W

VIH VIL -

DO
(DATA IN)

VIH -

T"'7<"..,.....,.....,.....,......,....,....."....,.....,....,....,..~Jr-------,lIr"7I.....,....,....,.....,....,.....,.....,.....,....,.....,....,

VIL _ ........-"-''-''-"''-'''-''-''-''-''-''-'L->L.¥ _ _ _ _ _ _ _;;r ,,-"-'........-"-''-''-......'-''-'''-'''-''

MOTOROLA MEMORY DATA

MCM32200-MCM32L200

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substate generator pump to establish the
correct bias voltage. This is to be followed by a minimum of
eight active cycles olthe row address strobe (clock) to initialize
the various dynamic nodes internal to the modllie. During an
extended inactive state of the device (greater than 4 milliseconds with device powered up), the wakeup sequence (8 active
cycles) will be necessary to assure proper device operation.

mum (tCAS) period for the CAS Clock. The RAS clock must
stay inactive for the minimum (tRP) time. The former is for the
completion of the cycle in progress, and the latter is for the device internal circuitry to be precharged for the next active cycle.
Data out is not latched and is valid as long as the CAS clock
is active; the output will switch to the three-state mode when
the CAS clock goes inactive. To perform a read cycle, the write
(W) input must be held at the VIH level from the time the CAS
clock makes its active transition (tRCS) to the time when ittransitions into the inactive (tRCH) mode.

ADDRESSING THE RAM

WRITE CYCLE

The ten address bus pins on the device are time multiplexed
with two separate 10-bit address fields that are strobed at the
beginning olthe memory cycle by two clocks (active negative)
called the row address strobe (RAS) and the column address
strobe (CAS). A total of twenty address bits will decode one of
the 2,097,152 word locations in the device. The column address strobe follows the row address strobe by a specified
minimum and maxium time called tRCD, which is the row to
column strobe delay. This time interval is also referred to as the
multiplex window which gives flexibility to a system designer
to set up the external addresses into the RAM. These conditions have to be met for normal read or write cycles. This initial
portion of the cycle accomplishes the normal addressing of the
device. These are, however, two other variations in addressing
the module, one is called the RAS only refresh cycle (described later) where a 9-bit row address field is presented on
the input pins and latched by the RAS clock. The most significant bit on Row Address A9 is not required for refresh. The other variation, which is called page mode, allows the user to
column access all words within a selected row. (See PAGEMODE CYCLES section.)

A write cycle is similar to a read cycle except that the write
(W) clock must go active (VIL level) at or before the CAS clock
goes active at a minimum twcs time. If the above condition is
met, then the cycle in progress is referred to as an early write
cycle. In an early write cycle, the write clock and the data in are
referenced to the active transition of the CAS clock edge.
There are two important parameters with respect to the write
cycle: the column strobe to write lead time (tCWL) and the row
strobe to write lead time (tRWL). These define the minimum
time that RAS and CAS clocks need to be active after the write
operation has started (W clock at VIL level).
PAGE-MODE CYCLES
Page mode operation allows fast successive data operations at all 1024 column locations on a selected row. Page access (tCAC) is typically half the regular RAS clock access
(tRAe) on the Motorola 1M dynamic RAM. Page mode operation consists of holding the RAS clock active while cycling the
CAS clock to access the column locations determined by the
1O-bit column address field.
The page cycle is always initiated with a row address being
provided and latched by the RAS clock, followed by the column
address and CAS clock. From the timing illustrated, the initial
cycle is a normal read or write cycle, that has been previously
described, followed by the shorter CAS cycles (tpC). The CAS
cycle time .(tPC) consists of the CAS clock active time (tCAS),
and CAS clock precharge time (tcp) and two transitions. In
practice, any combination of read and write cycles can be performed to suit a particular application.

READ CYCLE
A read cycle is referred to as a normal read cycle to differentiate it from a page mode read cycle, which is covered in a later
section.
The memory read cycle begins with the row addresses valid
and the RAS clock transitioning from VIH to the VIL level. The
CAS clock must also make a transition from VIH to the VIL level
at the specified tRCD timing limits when the column addresses
are latched. Both the RAS and CAS clocks trigger a sequence
of events which are controlled by several delayed internal
clocks. Also, these clocks are linked in such a manner that the
access time of the device is independent of the address multiplex window. The only stipulation is that the CAS clock must be
active before or at the tRC~imum specification for an access (data valid) from the RAS clock edge to be guaranteed
(tRAC)' If the tRCJl.!:Ilaximum condition is not met, the access
(tCAC) from the CAS clock active transition will determine read
access time. The external CAS signal is ignored until an internal RAS signal is available. This gating feature on the CAS
clock will allow the external CAS signal to become active as
soon as the row address hold time (tRAH) specification has
been met and defines the tRCD minimum specification. The
time difference between tRCD minimum and tRCD maximum
can be used to absorb skew delays in switching the address
bus from the row to column addresses and in generating the
CAS clock.
Once the clocks have become active, they must stay active
for the minimum (tRAS) period for the RAS clock and the mini-

REFRESH CYCLES
The dynamic RAM design is based on capaCitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Therefore, to retain the correct information, the module needs to be refreshed at least
once every 16 milliseconds. This is accomplished by sequentially cycling through the 1024 row address locations every 16
milliseconds (I.e., at least one row every 15.6 microseconds).
A normal read or write operation to the module will also refresh
all the words associated with the particular row(s) decoded.
RAS-only Refresh
In this refresh method, the system must perform a
RAS-only cycle on 1024 row addresses every 16 milliseconds.
The row addresses are latched in with the RAS clock, and the
associated internal row locations are refreshed. As the
heading implies, the CAS clock is not required and must be
inactive or at a VIH level.

MOTOROLA MEMORY DATA

3-37

•

MCM32200-MCM32L200

test is performed with read and write operations_ During this
test, the internal refresh counter generates the row address,
while the external address input supplies the column address.
The entire array is refreshed after .1024 test cycles, as indicated by the check data written in each row. See CAS before
RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:

CAS Before RAS Refresh

•

This refresh cycle is initiated when RAS falls, after CAS has
been low (by tCSR)' This activates ihe internal refresh counter
which generates the row address to be refreshed. Externally
applied addresses are ignored during the automatic refresh
cycle. If the output buffer was off before the automatic refresh
cycle, the output will stay in the high-impedance state. If the
output was enabled by CAS in the previous cycle, the data out
will be maintained during the automatic refresh cycle as long
as CAS is held active (hidden refresh).
.
Hidden Refresh

1. Write "0"5 into all memory cells (normal write mode).
2. Select a column address, and read "0" out of the cell by
performing CAS before RAS refresh counter test, read
cycle. Repeat this operation 1024 times.
3. Select a column address, and write "1" into the cell by
performing CAS before RAS refresh counter test, write
cycle. Repeat this operation 1024 times.
4_ Read "1 "s (normal read mode), which were written at step
3.
5. Repeat steps 1 to 4 using complement data.

The hidden refresh method allows refresh cycles to be performed while maintaining valid data at the output pin. Hidden
refresh is performed by holding CAS at VIL and taking RAS
hig~and after a specified precharge period (tRP), executing a
CAS before RAS refresh cycle. (See Figure 1.)
CAS BEFORE RAS REFRESH COUNTER TEST
The intemal refresh counter of the device can be tested with
a CAS before RAS refresh counter test. This refresh counter

REFRESH
CYCLE

DO -

HIGH-Z

-+14----, REFRESH
. CYCLE

VALID DATA-OUT

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory

prefiX~

32200 or 32L200

I

Part N u m b e r - - - - - - - - - - . . . . . . I

Full Part Numbers -

x

xx

T L
L

Speed(BO=BOns,10=100ns)

Package (S = SIMM, SG = Gold Pad SIMM,
SH = Low Height SIMM,
SHG = Gold P"ad Low Height SIMM)

MCM32200SBO
MCM32200S10

MCM32200SGBO
MCM32200SG10

MCM32200SHBO
MCM32200SH10

MCM32200SHGBO
MCM32200SHG10

MCM32L200SBO
MCM32L200S10

MCM32L200SGBO
MCM32L200SG10

MCM32L200SHBO
MCM32L200SH10

MCM32L200SHGBO
MCM32L200SHG10

NOTE: Contact your Motorola representative for further information on the Gold Pad SIMM packages.

MOTOROLA MEMORY DATA

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM32230
MCM32L230
2M x 32 Bit Dynamic Random
Access Memory Module
The MCM32230S is a 64M, dynamic random access memory (DRAM) module
organized as 2,097,152 x 32 bits. The module is a 72-lead double sided single-in-line
memory module (SIMM) consisting of sixteen MCM54400AN DRAMs housed in standard 300-mil-wide SOJ packages mounted on a substrate along with a 0.22 J.lF (min)
decoupling capacitor mounted under each DRAM. The MCM54400AN is a CMOS
high speed, dynamic random access memory organized as 1,048,576 four-bit words
and fabricated with CMOS silicon-gate process technology.
•
•
•
•
•
•
•
•
•
•
•
•
•

Three-State Data Output
Early-Write Common 1/0 Capability
Fast Page Mode Capability
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh: MCM32230S = 16 ms (Max)
MCM32L230S = 128 ms (Max)
Consists of Sixteen 1M x 4 DRAMs and Sixteen 0.22 J.lF (Min)
Decoupling Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access lime (tRAC): MCM32230S-70 = 70 ns (Max)
MCM32230S-80 = 80 ns (Max)
MCM32230S-10 = 100 ns (Max)
Low Active Power Dissipation: MCM32230S-70 = 4.49 W (Max)
MCM32230S-80 = 3.83 W (Max)
MCM32230S-10 = 3.39 W (Max)
Low Standby Power Dissipation: TTL Levels = 176 mW (Max)
CMOS Levels = 88 mW (Max, MCM32230S)
CMOS Levels = 18 mW (Max, MCM32L230S)

1

=

o

36
37

72

~

ell 0
PIN NAMES

PINOUT
Name

Pin

Name

PIn

Name

Pin

Name

Pin

Name

Pin

Name

1

VSS

13

Al

25

0022

37

NC

49

DOS

61

0013

2

000

14

A2

26

007

38

NC

50

0024

62

0030

3

0016

15

A3

27

0023

39

VSS

51

0Q9

63

0014

4

001

16

A4

28

A7

40

CASO

52

0025

64

0031

5

0017

17

AS

29

NC

41

CAS2

53

DOlO

65

0015

6

002

18

A6

30

VCC

42

CAS3

54

0026

66

NC

7

0018

19

NC

31

A8

43

CAS1

55

0011

67

P01

8

003

20

004

32

A9

44

RASO

56

0027

68

P02

9

0019

21

0020

33

RAS3

45

RAS1

57

0012

69

P03

10

VCC

22

005

34

RAS2

46

NC

58

0028

70

PD4

11

NC

23

0021

35

NC

47

W

59

VCC

71

NC

12

AO

24

006

36

NC

48

NC

60

0029

72

VSS

Pin

MOTOROLA MEMORY DATA
3-39

A(}--A9' ................ Address Inputs
DQ(}--DQ31 ......... Data InpuVOutput
CASo-GAS3 ... Column Address Strobe
PD1-PD4 ............ Presence Detect
RASO-RAS3 ...... Row Address Strobe
IN ................... ReadlWrlte Input
VCC ................... Power (+ 5 V)
VSS ........................ Ground
NC .................... No Connection
All power supply and ground pins must be
connected for proper operation of the device.

•

MCM32230-MCM32L230

BLOCK DIAGRAM
DQ(Hl03
CAS
RAS

•

~OE

W

1/01
V02
1/03
Ao-A9 1/04

CAS
AAS

W

OE

D04-D07

CAS
RAS

~OE

1/01
V02
1/03
V04 .A(}-A9

W

Ao-A9

I

I

1/01
V02
1/03
V04

VOl
V02
V03
V04 A(}-A9

.....
.....

'--J....

CAS
RAS

W

I

I

OE~

008-0011

CAS
AAS

~OE

W

ArrA9

1/01
V02
V03
1/04 A(}-A9

::::

VOl
1/02
V03

W

.....
~

I
Ao-A9

1/01
V02
1/03
1/04

W

ArrA9

1/01
V02
1/03
V04

I

I

W

W

I

I

VOl
1/02
V03
V04 ArrA9

~

W

VOl
V02
V03
V04 A(}-AS

~

.....
.....

OE~
CAS
RAS

002rr0023

CAS
RAS

OE~
CAS
AAS

I

ool6-,.ea19

~OE

W

1/01
V02
1/03
V04 A(}-A9

ArrA9 V04

I

CAS
RAS

~OE

CAS
RAS

0012-0015

CAS
AAS

rOE

VOl
1/02
1/03
V04

OE~
CAS
RAS

W

I

I

OE~

0024-0027
CAS
RAS

~OE

W

ArrA9

W

1/01
1/02
1/03
1/04 ArrA9

-

.....

CAS
RAS

W

0028-0031
1/01
V02
V03

CAS
AAS

~OE

1/01
1/02
V03
1/04

W

ArrA9 V04

I

VOl
V02
V03
1/04 ArrA9

......

I

CAS
RAS

W

I

I

ArrA9
Vcc

---------------1..-------...
0.22 J!F (MIN)
VSS ---------------T
....-------t.~

UD-U15
U(}-U15

PRESENCE DETECT PIN OUT
Pin Name

70ns

BOns

lOOns

POl
P02
P03
P04

NC
NC

NC
NC

VSS

NC
NC
NC

NC

VSS

MOTOROLA MEMORY DATA

OE~

VSS
VSS

OE~

RAS3

MCM32230- MCM32L230

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-1 to+ 7

V

Yin, Vout

-1 to+ 7

V
rnA

Power Supply Voltage
Voltage Relative to VSS
(For Any Pin Except Vccl
Data Output Current per DO Pin

lout

50

Power Dissipation

PD

6.12

W

Operating Temperature Range

TA

o to + 70

°C

TstQ

-25to + 125

°C

Storage Temperature Range

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to these high impedence circuits.

NOTE: Permanent device damage may oceu"f ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70 o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Supply Voltage (Operating Voltage Range)

Logic High Voltage, All Inputs

VIH

2.4

-

6.5

V

1

Logic Low Voltage, All Inputs

VIL

-1.0

-

O.B

V

1

Symbol

Min

Max

Unit

Notes

ICC 1

-

rnA

2,3

-

B16
696
616

ICC2

-

32

RECOMMENDED OPERATING CONDITIONS
Characteristic
VCC Power Supply Current

VCC Power Supply Current (Standby) (RAS
VCC Power Supply Current
During RAS only Refresh Cycles

VCC Power Supply Current
During Fast Page Mode Cycle
VCC Power Supply Current (Standby) (RAS
VCC Power Supply Current
During CAS Before RAS Refresh Cycle

MCM32230·70, tRC
MCM32230-BO, tRC
MCM32230-10, tRC

= CAS = VIH)
MCM32230-70, tRC
MCM32230-BO, tRC
MCM32230-1 0, tRC

= 130 ns
= 150 ns
= 1BO ns

ICC3

MCM32230-BO, tpc
MCM32230-BO, tpc
MCM32230-1 0, tpc

= 45 ns
=50 ns
= 60 ns

ICC4

= CAS = VCC -

0.2 V) MCM32230
MCM32L230

MCM32230-70, tRC
MCM32230-BO, tRC
MCM32230-1 0, tRC

~ Power Supply Current Battery Back'!e Mode (tRC

CAS

= 130 ns
= 150 ns
= lBO ns

= 130 ns
= 150 ns
= 1BO ns

= 1251lS; tRAS = 1~s;

= CAS before RAS Cycling or 0.2V; W, DO, AO-A9 = VCC-{).2V or 0.2V)

mA
rnA

2,3

2,3

-

B16
696
616

-

mA

-

576
496
456

ICC5

-

16
3.2

mA

ICC6

-

B16
696
616

rnA

2

rnA

2,4

-

-

ICC7

-

2.4

Input Leakage Current (VSS'; Vin ,; VCC)

Ilkg(l)

-160

160

~

Output Leakage Current (CAS at Logic 1, VSS'; Vout'; VCC)

Ilkg(O)

-20

20

~

VOH

2.4

-

V

VOL

-

0.4

V

MCM32L230 only

=- 5 mAl
Output Low Voltage (IOL = 4.2 rnA)

Output High Voltage (IOH

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading~imum current is measured at the fastest cycle rate with the output open.
3. Column Address can be changed once or less while RAS =VIL and CAS =VIH.
4. tRAS (MAX) = IllS is only applied to refresh of battery backup. tRAS (MAX) = lOllS is applied to functional operating.

MOTOROLA MEMORY DATA
3-41

MCM32230- MCM32l23O

CAPACITANCE (I = 1.0 MHz, TA = 25°e, Vee = 5 V, Periodically Sampled Rather Than 100% Tested)
Symbol

Min

Max

Unit

Notes

Input Capacitance (AO-AS)

Cll

-

SO

pF

1

Input Capacitance (W)

CI2

-

122

pF

1

Input Capacitance (RASQ--RAS2)

CI3

-

38

pF

1

Input Capacitance (CASQ--CAS3)

CI4

38

pF

1

110 Capacitance (DOQ--D031)

COO

-

24

pF

1

Characteristic

..

NOTE: 1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 .l. t / .l. V.

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70 o e, Unless Otherwise Noted)
READ AND WRITE CYCLES (See Notes I, 2, 3, and 4)
32230-70
32L23Q-70

Symbol
Parameter

32230-80
32L230-80

32230-10
32L23Q-l0
Unit

Notes

150

-

180

-

ns

5

45

-

50

60

70
20
35

tCPA

-

-

-

ns

-

-

tCELOX

tCLZ

tCEHOZ

Std

Alt

Min

Random Read or Write Cycle Time

tRELREL

tRC

130

Fast Page Mode Cycle Time

tCELCEL

tpc

Access Time from RAS

tRELQV

tRAC

Access Time from CAS

tcELOV

tCAC

Access Time from Column Address

tAVOV

tAA

Access Time from Precharge CAS

tCEHOV

CAS to Output in Low-Z
Output Buffer and Turn-Off Delay

Max

Min

Max

Min

Max

-

100

ns

6,7

20

25

ns

6,8

-

40

-

50

ns

6,S

40

-

45

55

6

0

-

a

-

-

a

20

0

20

10

80

a

-

ns
ns .

0

20

ns

6

IT

'oFF
tT

3

50

3

50

3

50

ns

RAS Precharge Time

tREHREL

tRP

50

-

60

-

70

-

ns

RAS Pulse Width

tRELREH

tRAS

70

10k

80

10 k

100

10 k

ns

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

70

200k

80

200k

100

200 k

ns

RAS Hold Time

tcELREH

tRSH

20

-

20

-

25

-

ns

CAS Hold Time

tRELCEH

tCSH

70

80

-

100

-

ns

CAS Precharge to RAS Hold Time

tCEHREH

tRHCP

40

-

45

-

55

-

ns

CAS Pulse Width

tCELCEH

tCAS

20

10k

20

10 k

25

10 k

ns

RAS to CAS Delay Time

tRELCEL

tRCD

20

50

20

60

25

75

ns

11

RAS to Column Address Delay Time

tRELAV

tRAD

15

35

15

40

20

50

ns

12

CAS to RAS Precharge Time

tCEHREL

-

5

-

10

-

ns

tCEHCEL

tCRP
tcp

5

CAS Precharge Time

10

-

10

-

10

-

ns

Transition Time (Rise and Fall)

contlnueo
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL'
2. An initial pause of 200 I1S is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VI H) in a monotonic manner.
4. AC measurements tT = 5.0 ns.
5. The specification for tRC (min) are used only to indicate cycle time at which proper operation overthe full temperature range (O°C" TA" 70°C)
is assured.
6. Measured with a current load equivalentto 2 TTL (- 200~, + 4 rnA) loads and 100 pF with the data outputtrip points set at VOH = 2.0 V and
VOL = 0.8 V.
7. Assumes that tRCD" tRCD (max).
8. Assumes that tRCD ;, tRCD (max).
S. Assumes that tRAD ;, tRAD (max).
10. 'oFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operation within the tRCD (max) limit ensures thattRAC (max) can be met. tRCD (max) is spec~ied asa reference point only; iftRCD is greater
than the specified tRCD (max) limit, then access time is controlled exclusively to tCAC'
12. Operation within the tRAD (max) limit ensures thattRAC (max) can be met. tRAD (max) is specified as a reference point only; iftRAD is greater
than the specified tRAD (max), then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
3-42

MCM32230-MCM32L230

READ AND WRITE CYCLES

(Continued)

32230-70
32L230-70

Symbol
Parameter

Std

Alt

Min

Row Address Setup Time

tAVREl

tASR

0

Max

3223o-BO
32L230-80
Min

-

0

Row Address Hold Time

tRELAX

tRAH

10

-

10

Column Address Setup Time

tAVCEl

tASC

0

-

0

Column Address Hold Time

leELAX

leAH

15

-

Column Address to RAS lead Time

tAVREH

tRAL

35

-

Read Command Setup Time

twHCEl

tRCS

0

Read Command Hold Time
Referenced to CAS

leEHWX

tRCH

0

Read Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

Write Command Hold Time
Referenced to CAS

tCElWH

twCH

15

-

Max

-

32230-10
32L230-1 0
Min
0
15

Max

-

Unit

Notes

ns
ns

15

-

20

-

40

-

50

-

ns

0

-

0

-

ns

0

-

0

-

ns

13

0

-

0

ns

13

Write Command Pulse Width

twLWH

twp

15

-

Write Command to RAS Lead Time

twlREH

tRWL

20

-

20

Write Command to CAS Lead Time

twlCEH

tCWl

20

-

-

20

Data in Setup Time

tOVCEl

tos

0

Data in Hold Time

tCELOX

tOH

tRVRV

Write Command Setup Time

15
15

0

ns
ns

25

-

-

25

-

ns

20
20

ns
ns
ns

0

-

0

-

ns

14

t5

-

15

-

20

-

ns

14

tRFSH

-

16
128

-

16
128

ms

-

16
128

twlCEl

twcs

0

-

0

CAS Setup Time for CAS Before RAS
Refresh

tRELCEL

tCSR

5

-

CAS Hold Time for CAS Before RAS"
Refresh

tRELCEH

tCHR

15

Refresh Period

MCM32230
MCM32L230

0

-

ns

5

-

5

-

ns

-

15

-

20

RAS Precharge to CAS Active Time

tREHCEl

tRPC

0

CAS Precharge Time for CAS Before
RAS Counter Time

tCEHCEl

tCPT

40

-

40

-

50

-

Write to RAS Precharge Time (CAS
Before RAS Refresh)

twHREL

tWRP

10

-

10

-

10

-

ns

Write to RAS Hold Time (CAS Before
RAS Refresh)

tRElWL

twRH

10

-

10

-

10

-

ns

0

0

15

ns
ns
ns

NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in random write cycles.
15. twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs;, twcs (min), the cycle
is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is not satisifed,
the condition of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA

•

MCM32230-MCM32L230

READ CYCLE

RAS VIH -

VIL -

•
ADDRESSES VIH VIL --.......,"--"~ "1I:-_~:r

w VIH-""~~~r7~~~~-----r-------------------+--~~~~~~~~~~~
VIL - ......~.....,.'--"'-""--'if--"~

DO VOH -

- - - - - - - - - - HIGH

z _____-+______.(1

VALID DATA OUT

VOL -

EARLY WRITE CYCLE

VIH RAS

VIL -

VIH CAS

VIL -

ADDRESSES VIH V IL -

W

VIH -

VIL

-

~~~~~~~~~~-+----4---~~~~~~~~~~~~~~~~~~~~

MOTOROLA MEMORY DATA

MCM32230-MCM32L230

FAST PAGE MODE READ CYCLE
_
V1H - --~
RAS
V1L -

1 - - - - - - - - - - - - - tRASP - - - - - - - - - - - - - - 1
t - - - - tpc -+---~

_
V1H CAS V
IL -

DQ VOH VOL -

----------{I

FAST PAGE MODE EARLY WRITE CYCLE
_
V1H RAS V

IL -

ADDRESSES VIH V1L -

_ VIH W

VIL -

DO

""""""""""~

4-..lJ'-"--"--"--'''--'''4Hi;::==:;f:1;;~'-''~j;:==:;f:fWc;;::'"I!,.><-~'ti;=::::;f:Tw~'''''''''-''-''-~

VIH - ~-="""~"" -J.,.....-=:-;;:-~ ~"'""'" .Jo-""':':7.-:::-~ ~..-\"<-7\ .Jo--:-::::-:::-~ ~"''''''''':''''A"'"A"'A""

MOTOROLA MEMORY DATA

MCM32230-MCM32L230

RAS ONLY REFRESH CYCLE

(iN Is Don't care)
~-------------------tRC------------------~
~-----

•

tm - - - - - - - . j

__ V1H - ,,"'''''n:---H-----------------:t:~;r:r_-----

CAS

V
IL -

r
ADDRESSES~:: =XXXXXAD~~~Ss)OI'

tASR~

.

CAS BEFORE RAS REFRESH CYCLE
(AD-A9ls Don't care)

VIH-~~~~~~------i~~~~~~~~~~~"'''''''''''''''~~~~

Vi

oa

VIL -

VOH VOL -

--"_-><;-"-~

-____--"IJ=t

OFF

HIGHZ

MOTOROLA MEMORY DATA

MCM32230-MCM32L230

HIDDEN REFRESH CYCLE (READ)

CAS

•

V1L -

ADDRESSES V IH V1L -

W V1H VIL -

00 VOH VOL -

--"'-"'-"'-"..,.-"~

------------------~

HIDDEN REFRESH CYCLE (EARLY WRITE)

_
V 1H RAS V _
IL

_VIH CAS V
IL -

ADDRESSES VIH V1L _ VIH W
VIL -

.-,."''''.....,......,.:-"''1\
->I._>L-->L.-"--"-..><.,.;'ft-l______----'+-'<-J

00 V1H VIL - ~'__"l.....l<'....Y "1<-______________- T 'IL-~~"_l'__"l.....l<~_>L-->L.....:.L_"_-"-~.JI-~~>L....l"__lt......:>.

MOTOROLA MEMORY DATA
3-47

MCM32230-MCM32L230

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

----~~~~-----------------t~------------------~~~----~.

•

14----------tRSH - - - - - - - - - - . . j

Jc-----"l i4--------tCAS

ADDRESSES VIH VILREAD CYCLE

MOTOROLA MEMORY DATA

,.-)-....!.:L...-----

MCM32230-MCM32L230

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the module. During an extended inactive
state (greater than 16 milliseconds with the device powered
up), a wake up sequence of eight active cycles is necessary to
ensure proper operation.
ADDRESSING THE RAM
The ten address pins on the device are time multiplexed at
the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 1O-bit address fields. A total of twenty address bits, ten
rows and ten columns, will decode one of the 1,048,576 word
locations in the device. RAS active transition is followed by
CAS active transition (active = VIL,.!Bm minimum) for all read
orwrite cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system designer flexibility in setting up the external addresses into the
RAM.
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the module:
RAS only refresh cycle, CAS before RAS refresh cycle,
and page mode. All three are discussed in separate sections
that follow.
READ CYCLE
The DRAM may be read with either a "normal" random read
cycle or a page mode read cycle. The normal read cycle is outlined here, while the page mode cycle is discussed in a separate section.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (iN) input level must be high
(VI H), tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The internal clocks are linked in such a manner that the read access
time of the device is independent of the address multiplex window. CAS controls read access time: CAS must be active before or at tRCD maximum to guarantee valid data out (DO) at
tRAC (access time from RAS active transition). If the tRCD
maximum is exceeded, read access time is determined by the
CAS clock active transition (tCAC)'
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. Wmust remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data althat bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitry for the next active
cycle. DO is valid, but not latched, as long as the CAS clock is
active. When the CAS clock transitions to inactive, the output

will switch to High Z (three-state) tOFF after the inactive transition.
WRITE CYCLE
The user can write to the DRAM with either an early write or a
page mode early write cycle. Early write mode is discussed
here, while page mode write operations are covered in a separate section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of Wto active
(Vul. Early write mode is distinguished by the active transition
of W, with respect to CAS. Minimum active time tRAS and
tCAS, and precharge time tRP apply to write mode, as in the
read mode.
An early write cycle is characterized by Wactive transition at
minimum time twcs before CAS active transition. Data in
(DO) is referenced to CAS in an early write cycle. RAS and
CAS clocks must stay active for tRWL and tCWL, respectively,
after the start of the early write operation to complete the cycle.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
1024 column locations on a selected row of the module. Read
access time in page mode (!cAC) is typically half the regular
RAS clock access time, tRAC. Page mode operation consists
of keeping RAS active while toggling CAS between VIH and
~ The row is latched by RAS active transition, while each
CAS active transition allows selection of a new column location
on the row.
A page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for
minimum tcp, while RAS remains low (VIL)' The second CAS
active transition while RAS is low initiates the first page mode
cycle (tPC)' Either a read or write operation can be performed
in a page mode cycle, subject to the same conditions as in normal operation (previously described). These operations can
be intermixed in consecutive page mode cycles and performed
in any order. The maximum number of consecutive page mode
cycles is limited by tRASP' Page mode operation is ended
when RAS transitions to inactive, coincident with or following
CAS inactive transition.
REFRESH CYCLES
The dynamic RAM design Is based on capacitor charge storage for each bit in the array. This charge will tend to degrade
with time and temperature. Each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in the
MCM32230 require refresh every 16 milliseconds, while refresh time for the MCM32L230 is 128 milliseconds.
This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds forthe MCM32230, and 124.8 microseconds for
the MCM32L230. Burst refresh, a refresh of aliI 024 rows consecutively, must be performed every 16 milliseconds on the
MCM32230 and 128 milliseconds on the MCM32L230.
A normal read or write operation to the RAM will refresh all
the bits associated with the particular row decodes. Three other methods of refresh, RAS-only refresh, CAS before RAS
refresh, and hidden refresh are available on this device for
greater system flexibility.

MOTOROLA MEMORY DATA

•

MCM32230-MCM32L230

•

RA5-0nly Refresh

CAS BEFORE RAS REFRESH COUNTER TEST

RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(VIH) throughoutthe cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.

The internal refresh counter of the device can be tested with
a CAS before RAS refresh counter test. This refresh counter
test is performed with read and write operations. During this
test, the internal refresh counter generates the row address,
while the external address input supplies the column address.
The entire array is refreshed after 1024 test cycles, as indicated by the check data written in each row. See CAS before
RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:

CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order actives an internal refresh counterthat generates the row address to be refreshed. External address lines are ignored during the automatic refresh cycle. The
output buffer remains atthe same state it was in during the previous cycle (hidden refresh). Vii must be inactive for time twRP
before and time tWRH after RAS active transition to prevent
switching the device into a test mode cycle.

1. Write "O"s into all memory cells (normal write mode).
2. Select a column address, and read "0" out of the cell by
performing CAS before RAS refresh counter test, read
cycle. Repeat this operation 1024 times.
3. Select a column address, and write "1" into the cell by
performing CAS before RAS refresh counter test, write
cycle. Repeat this operation 1024 times.
4. Read "I "s (normal read mode), which were written at step

Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). Vii is subject to the same conditions
with respect to RAS active transition (to prevent test mode
cycle) as in CAS before RAS refresh.

3.
5. Repeat steps 1 to 4 using complement data.

REFRESH
CYCLE

MEMORY - .
CYCLE

DQ -

HIGH-Z

REFRESH
CYCLE

VALID DATA-OUT

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory

prefix~

32230 or 32L230

I

Part N u m b e r - - - - - - - - - - - - - l
Full Part Numbers-

TT
x

xx

-

1>0· ""'.'"

MCM32230SH70
MCM32230SH80
MCM32230SH10

MCM32230SHG70
MCM32230SHG80
MCM32230SHG10

MCM32L230SH70
MCM32L230SH80
MCM32L230SH10

MCM32L230SHG70
MCM32L230SHG80
MCM32L230SHG10

MOTOROLA MEMORY DATA
3-50

"'~. '". '"""'I

Package (SH = SIMM, SHG = Gold Pad SIMM)

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM32256
MCM32L256

256K X 32 Bit Dynamic Random
Access Memory Module
The MCM32256S is a 8M, dynamic random access memory (DRAM) module organized as 262,144 x 32 bits. The module is a 72-lead single-in-line memory module
(SIMM) consisting of eight MCM514256A DRAMs housed in 20/26 J-Iead small outline packages (SOJ) mounted on a substrate along with a 0.22 ItF (min) decoupling
capacitor mounted under each DRAM. The MCM514256A is a 1.0 It CMOS high
speed, dynamic random access memory organized as 262,144 four-bit words and
fabricated with CMOS silicon-gate process technology.
• Three-State Data Output
• Early-Write Common I/O Capability
• Fast Page Mode Capability
• TIL-Compatible Inputs and Outputs
• RAS Only Refresh
• CAS Before RAS Refresh
• Hidden Refresh
• 512 Cycle Refresh:
MCM32256 = 8 ms (Max)
MCM32L256 = 64 ms (Max)
• Consists of Eight 256K x 4 DRAMs and Eight 0.22 ItF (Min) Decoupling Capacitors
• Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
• Fast Access Time (tRAC):
MCM32256S-70 = 70 ns (Max)
MCM32256S-80 = 80 ns (Max)
MCM32256S-10 = 100 ns (Max)
• Low Active Power Dissipation:
MCM32256S-70 = 3.6 W (Max)
MCM32256S-80 = 3.1 W (Max)
MCM32256S-10 = 2.7 W (Max)
• Low Standby Power Dissipation:
TIL Levels = 88 mW (Max)
CMOS Levels = MCM32256S 44 mW (Max)
MCM32L256S = 8.8 mW (Max)

0
00
0
0
i50000

'8

=

=
§!
=
§!

o

=
~
=
§!
=
8=
8=
=
§!
=

36

37

~

§!

=
=
=

8

8

72

PIN NAMES

PINOUT
Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

1

VSS

13

AI

25

0022

37

NC

49

DQ8

61

0013

2

OQO

14

A2

26

DOl

38

NC

50

0024

62

0030

3

0016

15

A3

27

0023

39

VSS

51

0Q9

63

0014

4

001

16

A4

28

A7

40

CASO

52

0025

64

0031

5

0017

17

A5

29

NC

41

CAS2

53

0010

65

0015

Pin

6

002

18

A6

30

VCC

42

CAS3

54

0026

66

NC

7

0018

19

NC

31

AS

43

CASI

55

0011

67

POl

8

003

20

004

32

NC

44

RASO

56

0027

68

P02

9

0019

21

0020

33

NC

45

NC

57

0012

69

P03

10

VCC

22

005

34

RAS2

46

NC

58

0028

70

P04

11

NC

23

0021

35

NC

47

W

59

VCC

71

NC

12

AO

24

006

36

NC

48

NC

60

0029

72

VSS

MOTOROLA MEMORY DATA
3-51

A(}->A8 ................ Address Inputs
DOa-D031 ......... Data InpuVOutput
CASO-CAS3 ... Column Address Strobe
PD1-PD4 ............ Presence Detect
!lASO, RAS2 ...... Row Address Strobe
W ................... Read/Write Input
VCC ................... Power (+ 5 V)
VSS .................•...... Ground
NC .................... No Connection
All power supply and ground pins must be
connected for proper operation of the device.

•

MCM32256·MCM32L256

BLOCK DIAGRAM

An-AS

1101
1102
1103
1104

000
001
D02
D03

An-AS

1101
1102
V03
1104

DQ4
DOS
DOB
D07

An-AS

1101
1102
V03
1104

DOB
DOO
DOlO
0011

1101
1102

CAS
RAS

~OE

•

Vi

CAS
RAS

~OE

Vi

CAS
RAS

~OE

Vi

AO-AS

1104

0012
0013
0014
0015

An-AS

VOl
V02
V03
V04

0016
0017
0018
0019

Ao-A8

1101
1102
1103
1104

0020
0021
0022
0023

Ao-AB

VOl
1102
1103
V04

0Q24
D025
D026
0027

Vi

Ao-AS

1101
1102
1103
1104

0028
0029
0030
0031

I

I

CAS
RAS

~OE

1103

Vi

CAS
RAS

Vi

rOE
CAS
RAS

~OE

Vi

CAS
RAS

Vi

rOE
CAS
RAS

~OE
Vi
Ao-AS
VCC
VSS

:t

0.2211F (MIN)

..

--------------T+---------I.~

PRESENCE DETECT PIN OUT

Pin Name

70n8

BOna

lOOns

POl
P02
P03
P04

VSS

VSS

VSS

NC

NC

NC

VSS

NC

NC

VSS

VSS
VSS

MOTOROLA MEMORY DATA
3-52

UD-U7
UD-U7

MCM32256-MCM32L256

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-lto+ 7

V

Vin, Vout

-lto+7

V
mA

Power Supply Voltage
Voltage Relative to VSS
(For Any Pin Except VCC)
Data Output Current per DO Pin

lout

50

Power Dissipation

Po

4.8

W

Operating Temperature Range

TA

oto + 70

°C

Storage Temperature Range

Ts!g

-25to+125

°C

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to these high impedence circuits.

NOTE: Permanent device damage may occurH ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, T A = 0 to 70·C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

Logic Low Voltage, All Inputs

VIL

-1.0

-

6.5

V

1

0.8

V

1

Min

Max

Unit

Notes

-

640
560
480

mA

2

16

rnA

640
560
480

mA

2

-

480
400
320

mA

2,3

8
1.6

mA

-

-

640
560
480

mA

-

2.4

RECOMMENDED OPERATING CONDITIONS
Symbol

Characteristic
VCC Power Supply Current

MCM32256-70,tRC = 130 ns
MCM32256-80, tRC = 150 ns
MCM32256-10,tRC = 180 ns

ICCl

VCC Power Supply Current (Standby) (RAS = CAS = VIH)

ICC2

VCC Power Supply Current
During RAS only Refresh Cycles

MCM32256-70,tRC = 130 ns
MCM32256-80, tRC = 150 ns
MCM32256-1 0, tRC = 180 ns

ICC3

MCM32256-70, tpc = 40 ns
MCM32256-80, tpc = 45 ns
MCM32256-1 0, tpc = 55 ns

ICC4

VCC Power Supply Current
During Fast Page Mode Cycle

-

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V) MCM32256
MCM32L256

ICC5

VCC Power Supply Current
During CAS Before RAS Refresh Cycle

ICC6

MCM32256-70, tRC = 130 ns
MCM32256-80, tRC = 150 ns
MCM32256-10, tRC = 180 ns

VCC Power Supply Current Battery Backup Mode (tRC = 1251'S; CAS = CAS
before RAS Cycling or 0.2V; W, DQ, AO-A8 = VCC-O.2V or 0.2V) tRAS = 11's
MCM32L256 only

ICC7

Input Leakage Current (VSS ,; Vin ,; VCC)

Ilkg(l)

-80

+80

Ilkg(O)

-10

+10

Output High Voltage (IOH = - 5 mAl

VOH

2.4

-

V

Output Low Voltage (IOL = 4.2 mAl

VOL

-

0.4

V

Output Leakage Current (CAS at Logic 1, VSS'; Vout'; VCC)

mA

I1A
I1A

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
3. Measured with one address transition per page mode cycle.

MOTOROLA MEMORY DATA
3-53

2

MCM32256·MCM32L256

CAPACITANCE (f = 1.0 MHz, TA = 25°e, Vee = 5 V, Periodically Sampled Rather Than 100% Tested)
Characteristic

Symbol

Input Capacitance (AO-A8)

..

Cll

Input Capacitance (W)

CI2

Input Capacitance (RASa, RAS2)

CI3

Input Capacitance (CASO-CAS3)

CI4

i/O CapacHance (000-0031)

COO

Min

Max

Unit

-

50

pF

t

66

pF

1

38

pF

1

24

pF

1

17

pF

1

Notes

NOTE:
1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 A t I A V.

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70 oe, Unless Otherwise Noted)
READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)
MCM32256·70

MCM32256-80

MCM32256-10

Alternate

Min

Max

Min

Max

Min

Max

Unit

Notes

-

150

180

-

ns

5

45

-

55

-

ns

100

ns

6,7

25

ns

6,8

50

ns

6,9
6

Symbol
Parameter

Standard

Random Read or Write Cycle lime

tRELREL

tRC

130

Page Mode Cycle lime

tCELCEL

tpc

40

Access lime from RAS

tRELOV

tRAC

-

70

-

80

Access lime from CAS

tCELOV

tCAC

-

20

-

20

Access lime from Column Address

tAVOV

tAA

-

35

-

40

-

Access lime from Precharge CAS

teEHOV

tePA

-

35

-

40

50

ns

CAS to Output in Low-Z

tCELOX

teLZ

a

-

a

a

-

ns

6

Output Buffer and Turn-Off Delay

-

-

teEHOZ

toFF

a

20

a

20

a

20

ns

10

Transition lime (Rise and Fall)

IT

IT

3

50

3

50

3

50

ns

RAS Precharge lime

tREHREL

tRP

50

-

60

-

70

-

ns

RAS Pulse Width

tRELREH

tRAS

70

10,000

80

10,000

100

10,000

ns

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

70

100,000

80

100,000

100

100,000

ns

tRSH

20

teSH

100

-

ns

80

-

25

70

-

20

teELCEH

tCAS

20

10,000

20

10,000

25

10,000

ns

tRELCEL

tRCD

20

50

20

60

25

75

ns

11

tRELAV

tRAD

15

35

15

40

20

50

,ns

12
(continued)

RAS Hold lime
CAS Hold Time

CAS Pulse Width
RAS to CAS Delay lime
RAS to Column Address Delay lime

tCELREH
tRELCEH

ns

NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 lIS is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VI H) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specnication for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (O°C " TA"
70°C) is assured.
6. Measured with a current load equivalent to 2 TTL (- 200 f.IA, + 4 mAl loads and 100 pF with the data output trip points set at VOH = 2.0 V and
VOL =O.BV.
7. Assumes that.tRCD" tRCD (max).
8. Assumes that tRCD " tRCD (max).
9. Assumes that tRAD " tRAD (max).
10. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voHage levels.
II. Operation within the tRCD (max) limit ensures thattRAC (max) can be met. tRCD (max) is specified as a reference point only; ntRCD is greater
than the specnied tRCD (max) limit, then access time is controlled exclusively to teAC'
12. OperationwithinthetRAD (max) limitensuresthattRAC (max) can be met. tRAD (max) is specified as a reference point only; iftRAD is greater
than the specified tRAD (max), then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
3-54

MCM32256-MCM32L256

READ AND WRITE CYCLES (Continued)
MCM32256-70

MCM32256-80

MCM32256-10

Standard

Alternate

Min

Min

Max

Min

Max

Unit

CAS to RAS Precharge Time

tcEHREl

tcRP

5

-

5

10

tcEHCEl

tcP

10

-

10

10

-

ns

CAS Precharge Time (Page Mode
CyleOnly)

-

tAVREl

tASR

0

ns

15

Symbol
Parameter

Max

Row Address Hold Time

tRElAX

tRAH

10

Column Address Setup Time

tAVCEl

IASC

0

Column Address Hold Time

tCElAX

tcAH

15

-

Column Address Hold Time
Referenced to RAS

tRElAX

tAR

55

-

60

Row Address Setup Time

0

.-

0

-

-

15

-

ns

0

-

0

-

ns

Column Address to RAS lead Time

tAVREH

tRAl

35

-

40

Read Command Setup Time

twHCEl

tRCS

0

-

0

Read Command Hold Time
Referenced to CAS

tcEHWX

tRCH

0

-

Read Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

Write Command Hold Time
Referenced to CAS

tcElWH

twCH

Write Command Hold Time
Referenced to RAS

tRElWH

twCR

Write Command Pulse Width

twlWH

50

0

-

0

15

-

55

-

twP

15

tRWl

20
20

0

ns

13

-

0

-

ns

13

15

-

20

-

ns

60

-

75

-

ns

-

20

-

ns

twLCEH

tCWl

tOVCEl

tos

0

-

15

15
20
20
0

tcElOX

tOH

15

Data in Hold Time Referenced to
RAS

tRELOX

tOHR

55

-

60

Refresh Period

tRVRV

tRFSH

-

8
64

-

Write Command Setup Time

twLCEl

twcs

0

CAS Setup Time for CAS Before

tRELCEl

tcSR

10

-

CAS Hold Time for CAS Before RAS
Refresh

tRELCEH

tcHR

30

CAS Precharge to CAS Active Time

tREHCEL

tRPC

0

CAS Precharge Time for CAS
Before RAS Counter Test

tCEHCEL

tCPT

40

MCM32256
MCM32L256

RASRefresh

ns

ns

Data in Setup Time
Data in Hold Time

•

ns

-

Write Command to CAS Lead Time

twLREH

75

-

-

Write Command to RAS lead Time

ns

10

20

Notes

0

25
25
0
20
75

-

8
64

-

0
10

-

-

30

-

-

0

-

0

40

-

50

-

-

ns

ns
ns
ns

14

ns

14

ns

-

8
64

ms

0

-

ns

10
30

-

ns

-

15

ns

ns
ns

CAS Precharge Time
15
ns
10
10
tCEHCEl
tcPN
NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in random write cycles.
15. twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs ~ twcs (min), the
cycle Is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. "this condition is not
satisifed, the condition of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA

MCM32266-MCM32L256

READ CYCLE

•

RAS

VIHVIL -

CAS

VIHVIL -

ADDRESSES

VIHVIL -

W

VIHVIL -

Doo-DQ31 VOH(DATA OUT)
VOL -

MOTOROLA MEMORY DATA
3-56

MCM32256·MCM32L256

FAST PAGE MODE READ CYCLE
_ _ _~II4-------- t R A S P - - - - - - - - . t
RAS

V'H-

V,L -

V,H -

•

---fr--tt---~n

CAS

V,L -

ADDRESSES

V'H-

V,L -

DOQ-DQ3t VOH(DATAOUl] VOL _

L.:JLJ/~~~~

---------LX
tcLZ-~t+--

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

RAS

V,H V,L -

V,H CAS

V,L -

ADDRESSES

V,H V,L -

iN

DOO-D03t
(DATA IN)

V,H V,L -

V,H V,L -

MOTOROLA MEMORY DATA
3-57

MCM32256-MCM32L256

RAS ONLY REFRESH CYCLE
(Wand A8 are Don't Care)

•

RAS

VIH

-

VIL

-

1....
. - - - - - - - tRC--------.t
1....
. - - - - - tRAS - - " ' ' ' - - - - - . 1
-----,I
ir------.i

VIH -

CAS

AO-A7

DQO-DQ31 VOH (DATA OUT) VOL _ - - - - - - - - - - HIGH-Z

CE BEFORE RA"S REFRESH CYCLE
(Wand AO to A8 are Don't Care)

1-------

tRAS---:-.t~.-- tRP ~

(
tRPC

tRC-----~~

tCHR

MOTOROLA MEMORY DATA

3-58

MCM32256-MCM32l.256

HIDDEN REFRESH CYCLE (READ)

RAS

VIH -

•

VIL -

VIH CAS
VIL -

ADDRESSES
VIL -

W

VIH

-

VIL -

DQ()-DQ31 VOH (DATA OUT)
VOL -

HIDDEN REFRESH CYCLE (WRITE)
- - - - - + 1 1 4 - - - tRAS

RAS

VIH

-

VIL

-

VIH

-

VIL

-

VIL

-

VIH

-

VIL

-

CAS

ADDRESSES

iN

DQO-DQ31
(DATA IN)

VIH VIL

4

..

toHR

MOTOROLA MEMORY DATA
3-59

MCM32256-MCM32L266

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
tRAS ---'------I~

,

--

ADDRESSES

VIH VIL -

READ CYCLE
DClO-D031 VOH (DATA OUT)
VOL -

MOTOROLA MEMORY DATA
3-60

MCM32256-MCM32U56

stay inactive for the minimum (tRP) time. The former is for the
completion of the cycle in progress, and the latter is for the device internal circuitry to be precharged for the next active cycle.
Data out is not latched and is valid as long as the CAS clock
is active; the output will switch to the three-state mode when
the CAS clock goes inactive. To perform a read cycle, the write
(W) input must be held at the VIH level from the time the CAS
clock makes its active transition (tRCS) to the time when it transitions into the inactive (tRCH) mode.

DEVICE INITIALIZATION

On power-up an initial pause of 200 microseconds is required for the internal substate generator pump to establish the
correct bias voltage. This is to be followed by a minimum of
eight active cycles of the row address strobe (clock) to initialize
the various dynamic nodes internal to the module. During an
extended inactive state of the module (greater than 4 milliseconds with device powered up), the wake up sequence (8 active
cycles) will be necessary to assure proper device operation.

WRITE CYCLE
ADDRESSING THE RAM

A write cycle is similar to a read cycle except that the write
(W) clock must go active (VIL level) at or before the CAS clock
goes active at a minimum twcs time. If the above condition is
met, then the cycle in progress is referred to as an early write
cycle. In an early write cycle, the write clock and the data in are
referenced to the active transition of the CAS clock edge.
There are two important parameters with respect to the write
cycle: the column strobe to write lead time (tCWL) and the row
strobe to write lead time (tRWU. These define the minimum
time that RAS and CAS clocks need to be active after the write
operation has started (W clock at VIL level).

The nine address bus pins on the device are time multiplexed with two separate 9-bit address fields that are strobed
althe beginning of the memory cycle by two clocks (active negative) called the row address strobe (RAS) and the column address strobe (CAS). A total of eighteen address bits will decode
one of the 262,144 word locations in the device. The column
address strobe follows the row address strobe by a specified
minimum and maxium time called tRCD, which is the row to
column strobe delay. This time interval is also referred to as the
multiplex window which gives flexibility to a system deSigner
to set up the external addresses into the RAM. These conditions have to be met for normal read or write cycles. This initial
portion of the cycle accomplishes the normal addressing of the
device. These are, however, other variations in addressing the
module: the refresh modes (RAS only refresh, CAS before
RAS refresh, hidden refresh), and another mode called page
mode which allows the user to column access all words within
a selected row. The refresh mode and page mode operations
are described in more detail in later sections.

PAGE-MODE CYCLES

Page mode operation allows fast successive data operations at all 512 column locations on a selected row. Page access (teAC) is typically half the regular RAS clock access
(tRAC) on the Motorola 1M dynamic RAM. Page mode operation consists of holding the RAS clock active while cycling the
CAS clock to access the column locations determined by the
1O-bit column address field.
The page cycle is always initiated with a row address being
provided and latched by the RAS clock, followed by the column
address and CAS clock. From the timing illustrated, the initial
cycle is a normal read or write cycle, that has been previously
described, followed by the shorter CAS cycles (tpC). The CAS
cycle time (tpC) consists of the CAS clock active time (teAS),
and CAS clock precharge time (tep) and two transitions. In
practice, any combination of read and write cycles can be performed to suit a particular application.

READ CYCLE

A read cycle is referred to as a normal read cycle to differentiate it from a page mode read cycle, which is covered in a later
section.
The memory read cycle begins with the row addresses valid
and the RAS clock transitioning from VIH to the VIL level. The
CAS clock must also make a transition from VIH to the VIL level
althe specified tRCD timing limits when the column addresses
are latched. Both the RAS and CAS clocks trigger a sequence
of events which are controlled by several delayed internal
clocks. Also, these clocks are linked in such a manner that the
access time of the device is independent of the address multiplex window. The only stipulation is that the CAS cloc~ must be
active before or at the tRC~ximum specification for an access (data valid) from the RAS clock edge to be guaranteed
(tRAC). If the tRQQ!!Iaximum condition is not met, the access
(tCAC) from the CAS clock active transition will determine read
access time. The external CAS Signal is ignored until an internal RAS signal is available. This gating feature on the CAS
clock will allow the external CAS signal to become active as
soon as the row address hold time (tRAH) specification has
been met and defines the tRCD minimum specification. The
time difference between tRCD minimum and tRCD maximum
can be used to absorb skew delays in switching the address
bus from the row to column addresses and in generating the
CAS clock.
Once the clocks have become active, they must stay active
for the minimum (tRAS) period for the RAS clock and the minimum (tCAS) period for the CAS clock. The RAS clock must

REFRESH CYCLES

The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Therefore, to retain the correct information, the module needs to be refreshed at least
once every 8 milliseconds. This is accomplished by sequentiallycycling through the 512 row address locations every 8 milliseconds (i.e., at least one row every 15.6 microseconds). A
normal read or write operation to the module will also refresh
all the words associated with the particular row(s) decoded.
RA5-0nly Refresh
In this refresh method, the system must perform a
RAS-only cycle on 512 row addresses every 8 milliseconds.
The row addresses are latched in with the RAS clock, and the
associated internal row locations are refreshed. As the
heading implies, the CAS clock is not required and must be
inactive or at a VIH level.

MOTOROLA MEMORY DATA

3-61

•

MCM322&6-MCM32L266

CAS Before RAS Refresh

test is performed with read and write operations. During this
test, the internal refresh counter generates the row address,
while the external address input supplies the column address.
The entire array is refreshed after 512 test cycles, as indicated
by the check data written in each row. See CAS before RAS
refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:

This refresh cycle is initiated when RAS falls, after CAS has
been low (by tCSR)' This activates the internal refresh counter
which generates the row address to be refreshed. Externally
applied addresses are ignored during the automatic refresh
cycle. If the output buffer was off before the automatic refresh
cycle, the output will stay in the high impedance state. If the
output was enabled by CAS in the previous cycle, the data out
will be maintained during the automatic refresh cycle as long
as CAS is held active (hidden refresh).
Hidden Refresh

1. Write "O"s into all memory cells (normal write mode).
2. Select a column address, and read "0" out of the cell by
performing 'CAS before RAS refresh counter test, read
cycle. Repeat this operation 512 times.
3. Select a column address, and write "1" into the cell by
performing CAS before RAS refresh counter test, write
cycle. Repeat this operation 512 times.
4. Read "1 "s (normal read mode), which were written at step
3.
5. Repeat steps 1 to 4 using complement data.

The hidden refresh method allows refresh cycles to be performed While maintaining valid data at the output pin. Hidden
refresh is performed by holding CAS at VIL and taking RAS
high and after a specified precharge period (tRP), executing a
CAS before RAS refresh cycle. (See Figure 1.)

CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of the device can be tested with
a CAS before RAS refresh counter test. This refresh counter

REFRESH

_ . .1+_ REFRESH

CYCLE

DQ0-0Q31 -

HIGH·Z

CYCLE

VALID DATA.QUT

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory

prefiX~

32256 or 32L256

I

Part N u m b e r - - - - -_ _ _ _---'
Full Part Numbers -

x

xx

T T_
~

Speed (70 = 70 ns, 80 a 80 ns, 10 = 100 ns)
Package (S = SIMM, SG = Gold Pad SIMM)

MCM32256S70
MCM32256S80
MCM32256S10

MCM32256SG70
MCM32258SG80
MCM32256SGI0

MCM32l256S70
MCM32l256S80
MCM32l256S10

MCM32l256SG70
MCM32l258SG80
MCM32l256SG10

MOTOROLA MEMORY DATA

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM32512
MCM32L512

512K X 32 Bit Dynamic Random
Access Memory Module
The MCM32512S is an 16M. dynamic random access memory (DRAM) module
organized as 524.288 x 32 bits. The module is a 72-lead double-sided single-in-line
memory module (SIMM) consisting of sixteen MCM514256A DRAMs housed in 20/26
J-Iead small outline packages (SOJ) mounted on a substrate along with a 0.22 ItF
(min) decoupling capaCitor mounted under each DRAM. The MCM514256A is a 1.0 It
CMOS high speed. dynamic random access memory organized as 262.144 four-bit
words and fabricated with CMOS silicon-gate process technology.
• Three-State Data Output
• Early-Write Common 110 Capability
• Fast Page Mode Capability
• TTL-Compatible Inputs and Outputs
• RAS Only Refresh
• CAS Before RAS Refresh
• Hidden Refresh
• 512 Cycle Refresh:
MCM32512 = 8 ms (Max)
MCM32L512 = 64 ms (Max)
• ConSists of Sixteen 256K x 4 DRAMs and Sixteen 0.22 ItF (Min) Decoupling
Capacitors
• Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
• Fast Access lime (tRAC):
MCM32512S-70 = 70 ns (Max)
MCM32512S-80 = 80 ns (Max)
MCM32512S-10 = 100 ns (Max)
• Low Active Power Dissipation:
MCM32512S-70 - 3.608 W (Max)
MCM32512S-80 = 3.168 W (Max)
MCM32512S-10 = 2.728 W (Max)
• Low Standby Power Dissipation:
TTL Levels = 176 mW (Max)
CMOS Levels = 88 mW (Max)
18 mW (Max. MCM32L512)

o0
I 00
i
0
0
0

'E!!
8

~
~
~

§

36
37

72

=
~

~!oOo

PINOUT
Pin
1

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Vss

13

Al

25

0Q22

37

NC

49

DQ8

61

0013

2

DQO

14

A2.

26

D07

38

NC

50

0024

62

0030

3

0016

15

A3

27

0023

39

VSS

51

D09

63

0014

4

DOl

16

A4

28

A7

40

CASO

52

0025

64

0031

5

0017

17

AS

29

NC

41

CAS2

53

0010

65

0015

6

D02

18

A6

30

Vee

42

CAS3

54

0026

66

NC

7

0018

19

NC

31

AS

43

CASl

55

0011

67

POl

8

003

20

0Q4

32

NC

44

RASa

56

0Q27

68

P02

9

D019

21

0020

33

RAS3

45

RASl

57

0012

69

PD3

10

VCC

22

DOS

34

RAS2

46

NC

58

0028

70

PD4

11

NC

23

0021

35

NC

47

W

59

Vec

71

NC

12

AO

24

DQ6

36

NC

48

NC

60

DQ29

72

Vss

MOTOROLA MEMORY DATA

3-63

PIN NAMES
AD-AS ................ Address Inputs
QQQ;:DQ31 ......... Data Input/Output
CASO-CAS3 ... Column Address Strobe
PD1-PD4 . . . . . . . • . • .. Presence Detect
RASD-RAS3 ...... Row Address Strobe
W................... ReadlWrite Input
VCC ................... Power (+ 5 V)
VSS ........................ Ground
NC .................... No Connection
All power supply and ground pins must be
connected for proper operation of the device.

MCM32512·MCM32L612

BLOCK DIAGRAM

AfJ-A8

1101
V02
V03
1/04

W

AO-AB

1/01
1/02
1/03
1/04

I

I

CAS

•

RAS

~OE

W

1101
1102
1103
1104 AO-A8

CAS

RAS

W

DQ4-D07

CAS
RAS

~OE

OO~DQ3

-

1101
1/02
1103

,...
'"

OE~
CAS
RAS

W

V04 AO-AB

I

I

OE~

DOB-DOll

AfJ-A8

1/01
1/02
1103
1104

W

AfJ-A8

VOl
1102
V03
1/04

I

I

CAS
RAS

~OE

W

'"

CAS
RAS

W

0012-0015

CAS
RAS

~OE

1101
1/02
1103
1/04 AO-A8

,...

1/01
1/02
1/03
1/04 AO-AB

OE~
CAS
RAS

W

I

I

OE~

0018-0019
1/01
1/02
1/03

CAS
RAS

~OE

W

AO-AB

V04

W

AO-AB

1101
1102
1103
1/04

I

I

~

CAS
RAS

W

V04 AO-AB
DQ2O-D023

CAS
RAS

~OE

1101
1102
1103

,...

-,..

1/01
1102
1103

,...

OE~
CAS
RAS

W

V04 AO-AB

I

I

OE~

D02~27

AfJ-A8

1/01
1102
1/03
1104

W

AO-AB

1101
1102
1/03
1104

1

I

CAS
RAS

~OE

W

W

AfJ-A8
Vcc

W

1101
1102
1103

,...

W

I

J

---------------l
......- - - - - -.......

UO-U15
... UO-U15

----------------A9

CAS
RAS

rOlE

I CAS
RAS

iii

Ar>-A9

iii

iii

I CAS

m

Ar>-A9

OiE

iii

iii
iii

A()-A9

Ar>-A9

CAS

RAS

r

iii

A()-A9

CAS
RAS

W

Di~~

Ar>-A9

"

"

DQ22;:PCl25

002a
DQ27;:PQ30

1101
1102
1103
1104

-DQ31;:PQ34

1101
1/02
1103
1104

"
"
0035

I CAS
RAS

W

Ar>-A9

iii

~~in

Dnld

1101
1102
1/03
1104

Dout Ar>-A9

l-l DinDOUl

Di~~

Dout

OIE~
CAS

I

RAS

CAS
RAS
Ar>-A9

VOl
V02
1/03
1/04 A()-A9

~

--

1101
1102
1103
1104

iii

1/01
1/02
1103
1/04 A()-A9

"

Di~~

RAS
A()-A9

VOl
V02
1103
1104

OIE~

iii

CAS

l-l Doul
Din
Ar>-A9

001 il;:DQ21

1101
1/02
1/03
1104

A()-A9

VOl
1/02
V03
V04 Ar>-A9

"
,..

A()-A9

CAS

OiE

"

"

1101
1/02
1103
1104

RAS

rOlE

~

1101
1102
V03
1/04

CAS

m

~Din

OO13;;1lO16

Dout

CAS

I RAS

D;Q;8

Di~~

A()-A9

CAS
RAS

r
rOlE

-

0017

W

1101
1102
V03
1104

;:.

Ar>-A9

RAS

iii

VOl
1102
1103
1104

VOl
1102
1103
1104

CAS

rOlE

"
fXl.1;pQ7

DnuII

RAS
rOlE

1103
1104

A()-A9

CAS

1101
1102
1103
V04

"

1102

RAS

Ar>-A9

OIE~

iii

CAS
RAS

iii

OIE~

W

CAS
RAS

I

CAS
RAS

OIE~

iii

CAS
RAS

iii

OIE~

W

~I
RAS

W

l'iAS
O/E~

CAS
Ar>-A9

CAS

RAS
Ar>-A9

A()-A9

iii

O/E~

W

CAS
RAS

I

iii

Ar>-A9

Vee

II

~

UO-U23

O.22J!F (MIN)

VSS - - - - - - - - - - - - -.....
- .....-----------I~~ Ull-U23

PRESENCE DETECT PIN OUT

Pin Name

70ns

80ns

lOOns

POl
P02
P03
P04

Ne
Ne
VSS
NC

Ne
Ne
Ne
Vss

Ne
Ne
VSS
VSS

MOTOROLA MEMORY DATA

MCM36200-MCM36L200

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-lto+ 7

V

Vin' Vout

-1 to+ 7

V
mA

Power Supply Voltage
Voltage Relative to Vs~
(For Any Pin Except cc)
Data Output Current per DQ Pin

lout

50

Power Dissipation

Po

8.66

W

Operating Temperature Range

TA

oto + 70

'c

Tst~

-2510 + 125

'c

Storage Temperature Range

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to these high impedence circuits .

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Vee = 5.0 V ± 10%, T A = 0 to 70 o e,

Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

-

6.5

V

1

Logic Low Voltage, All Inputs

VIL

-1.0

-

0.8

V

1

Min

Max

Unit

Notes

mA

2

RECOMMENDED OPERATING CONDITIONS
Characteristic

Symbol

VCC Power Supply Current
MCM36200-80, tRC =150 ns
MCM36200-10, tRC =180 ns
VCC Power Supply Current (Standby) (RAS =CAS

ICCI

=V, H)

ICC2

VCC Power Supply Current During RAS only Refresh Cycles
MCM36200-80, tRC =150 ns
MCM36200-10, tRC =180 ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle
MCM36200-80, tpc =45 ns
MCM36200-10, tpc =55 ns

ICC4

VCC Power Supply Current (Standby) (RAS =CAS =VCC - 0.2 V) MCM36200
MCM36L200

ICC5

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM36200-80, tRC =150 ns
MCM36200-1 0, tRC =180 ns

ICC6

VCC Power Supply Current Battery Backup Mode (tRC =1251lS; tRAS = IllS;
CAS =CAS Before RAS Cycling or 0.2V; W, DO, AQ-A9 =VCC -0.2V or 0.2v)

ICC7

-

-

1144
984
48

mA
mA

2

mA

2,3

-

1144
984

-

784
664

-

24
8

-

-

1144
984

-

10.4

l'kg(l)

-'240

240

l'kg(O)

-20

20

JJA
JJA

Output High Voltage (IOH =- 5 mAl

VOH

2.4

-

V

Output Low Voltage (IOL =4.2 mAl

VOL

-

0.4

V

-

MCM36L200 only
Input Leakage Current (VSS:;; Vin:;; VCC)
Output Leakage Current (CAS at Logic 1, VSS S Vout:;; VCC)

-

mA
mA

mA

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
3. Measured with one address transition per page mode cycle.

MOTOROLA MEMORY DATA

3-89

2

•

MCM36200-MCM36L200

RECOMMENDED OPERATING CONDITIONS
Characteristic

..

Min

Max

Unit

130

pF

1

178

pF

1

CI3

-

52

pF

1

CI4

-

52

pF

1

-

24

pF

1

1/0 Capacitance (008, 0017, 0026, 0035)
34
pF
C002
NOTE: 1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 Iltlll V.

1

Symbol

Input Capacitance (Ao-A9)

Cll

Input CapaCitance (W)

Cl2

Input Capacitance (RASo-RAS2)
Input Capacitance (CASQ-CAS3)

1/0 Capacitance (000-007, 009-0016, 0018-0025, 0027-0034)

COOl

Notes

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vce =5.0 V ± 10%, TA = 0 to 70 oe, Unless Otherwise Noted)
READ AND WRITE CYCLES (See Notes 1, 2,3, and 4)
Symbol
Parameter

Standard

MCM362GO-aO

MCM36200-10

Alternate

Min

Max

Min

Max

Unit

Notes

180

ns

5

60

-

ns

tRELREL

tRC

150

Page Mode Cycle Time

tCELCEL

tpc

50

-

Access Time from RAS

tRELOV

tRAC

-

80

-

100

ns

6,7

Access Time from CAS

tCELOV

tCAC

-

20

-

25

ns

6,8

Access Time from Column Address

tAVOV

tAA

40

ns

6,9

tCEHOV

tePA

-

50

Access Time from Precharge CAS

-

55

ns

6

CAS to Output in Low-Z

teELOX

tcLZ

-

ns

6

teEHOZ

toFF

20

a
a

-

Output Buffer and Turn-Off Delay

a
a

20

ns

10

IT

IT

3

50

3

50

ns

-

ns

Random Read or Write Cycle Time

Transition Time (Rise and Fall)

45

-

RAS Precharge Time

tREHREL

tRP

60

RAS Pulse Width

tRELREH

tRAS

80

10,000

100

10,000

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

80

100,000

100

100,000

ns

RAS Hold Time

tCELREH

tRSH

25

25

tRELCEH

teSH

80

100

-

ns

CAS Hold Time

-

tCAS

20

10,000

25

10,000

ns

tRCO

20

60

25

75

ns

11

tRAO

15

40

20

50

ns

12
(continued)

CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time

teELCEH
tRELCEL
tRELAV

70

ns

ns

NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 IlS is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specification fortRC (min) is used only to Indicate cycle time at which proper operation over the full temperature range (O°C STA" 70°C) is
assured.
.
6. Measured with a current load equivalent to 2 TIL (- 200 !lA, + 4 mAl loads and 100 pF with the data outpultrip points set at VOH = 2.0 V and
VOL = 0.8 V.
7. Assumes thattRCO" tRCO (max).
8. Assumes that tRCO 2: tRCO (max).
9. Assumes that tRAO 2: tRAO (max).
10. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11 . Operation within the tRCO (max) limit ensures thattRAC (max) can be met. tRCO (max) is specified as a reference point only; iflRCO is greater
than the specified tRCO (max) limit, then access time is controlled exclusively to teAC'
.
12. Operation within the tRAO (max) limit ensures thattRAC (max) can be met. tRAO (max) is specified as a reference point only; ntRAO is greater
than the specified tRAO (max), then access time Is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
3-90

MCM36200-MCM36l2OO

READ AND WRITE CYCLES (Continued)
Symbol

MCM36200

MCM36L200

Parameter

Standard

Alternate

Min

Max

Min

CAS to RAS Precharge TIme

tcEHREL

tcRP

5

10

CAS Precharge TIme (Page Mode Cyle Only)

tcEHCEL

tcp

10

tAVREL

tASR

0

tRAH

10

tASC

0

tcAH

15

-

tAR

60

Row Address Setup TIme
Row Address Hold TIme

tRELAX

Column Address Setup TIme

tAVCEL

Column Address Hold TIme

tcELAX

Column Address Hold TIme Referenced
toRAS

tRELAX

Max

Unit
ns

10

-

ns

0

ns

20

-

-

75

-

ns
ns

ns

13
13

15
0

ns
ns

tAVREH

tRAL

40

-

50

Read Command Setup TIme

twHCEL

tRCS

0

0

Read Command Hold TIme Referenced
to CAS

tCEHWX

tRCH

0

-

0

-

Read Command Hold TIme Referenced
toRAS

tREHWX

tRRH

0

-

0

-

ns

Write Command Hold TIme Referenced
to CAS

tcELWH

twCH

15

-

20

-

ns

Write Command Hold TIme Referenced
toRAS

tRELWH

twCR

60

-

75

-

ns

20

-

ns

25

75

-

-

16
128

ms

0

-

ns

Write Command Pulse Width

twLWH

twp

15

Write Command to RAS Lead TIme

twLREH

tRWL

20

Write Command to CAS Lead TIme

twLCEH

tCWL

20

Data in Setup TIme

tDVCEL

tDS

0

tDH

15

-

tcELDX

Data in Hold TIme Referenced to RAS

tRELDX

tDHR

60

Refresh Period

tRVRV

tRFSH

-

16
128

tWLCEL

twcs

0

MCM36200
MCM36L200

CAS Setup TIme for CAS Before RAS Refresh

tRELCEL

tcSR

10

CAS Hold TIme for CAS Before RAS Refresh

tRELCEH

tcHR

30

CAS Precharge to CAS Active TIme

tREHCEl

tRPC

0

-

CAS Precharge TIme for CAS Before RAS
Counter Test

tcEHCEl

tCPT

40

-

Write Command Setup TIme

-

25
0
20

10
30
0
50

-

--

ns

Column Address to RAS Lead TIme

Data in Hold TIme

Notes

-

ns

ns
ns
ns

14

ns

14

ns

15

ns
ns
ns
ns

CAS Precharge TIme
10
15
ns
tCEHCEl
tcPN
NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in random write cycles.
15. twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs" twcs (min), the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition Is not
satisifed, the condition of the data out (at access time) is indeterminate.
16. To avoid bus contention and potential damage to the module, RASO and RASI may not be active low simultaneously. Similarly, RAS2 and
RAS3 may not be simultaneously active low.

MOTOROLA MEMORY DATA
3-91

MCM36200-MCM36L200

READ CYCLE

•

RAS

VIH Vll-

CAS

VIHVil -

ADDRESSES

VIHVil -

W

VIHVll-

VOHDQ
(DATA OUT)
VOL -

MOTOROLA MEMORY DATA

MCM36200-MCM36L200

FAST PAGE MODE READ CYCLE

___.... ""1------- t R A S P - - - - - - - - + I
RAS

VIHVIL -

•

VIH - --Ir--I+---....;;,t;;.,.
CAS

VIL -

ADDRESSES

VIHVIL -

DO VOH-

(DATA OUT)

VOL -

---------1
tcLZ

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

RAS

VIH VIL -

VIH -

CAS
VIL -

ADDRESSES

VIH VIL -

W

DO

(DATA IN)

VIH VIL -

VIH VIL -

MOTOROLA MEMORY DATA

MCM36200-MCM36L200

RE ONLY REFRESH CYCLE
(Wand A9 are Don't Care)

,....
--------

RAS

tRC-------~

1~..
.-----tMS~~----. .1

Ir--"'-~

VIH - - - - - - , \
VIL tcRP

VIH - --+--11+--------------+-~,.._-

CAS

ADDRESSES

DO vOH (DATA OUT) VOL _ - - - - - - - - - - HIGH-Z

MOTOROLA MEMORY DATA

MCM36200-MCM36L200

HIDDEN REFRESH CYCLE (READ)

RAS

VIH -

..

- - - - - + 1 1 4 - - - tRAS--'

•

VIL -

VIH CAS
VIL -

ADDRESSES
VIL -

iN

VIH

-

VIL -

DO VOH (DATA OUT}
VOL-

VALID DATA

HIDDEN REFRESH CYCLE (WRITE)
- - - -.... 1 4 - - - tRAS
RAS

VIH VIL

-

VIH CAS
VIL

-

VIL

-

ADDRESSES

iN

VIH VIL

DQ
(DATA IN)

-

VIH VIL

-

..

..

tDHR

MOTOROLA MEMORY DATA
3-95

MCM36200-MCM36L200

~ BEFORE RA'S REFRESH COUNTER TEST CYCLE
IRAS - - - - - - - I - . j
1 + - - IRSH ---I~

•
ADDRESSES

VIHVIL -

READ CYCLE
DO VOH (DATAOUl)
VOL. -

MOTOROLA MEMORY DATA

MCM36200-MCM36L200

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substate generator pump to establish the
correct bias voltage. This is to be followed by a minimum of
eight active cycles olthe row address strobe (clock) to initialize
the various dynamic nodes internal to the module. During an
extended inactive state of the module (greater than 4 milliseconds with device powered up), the wake up sequence (8 active
cycles) will be necessary to assure proper device operation.

mum (tCAS) period for the CAS clock. The RAS clock must
stay inactive for the minimum (tRP) lime. The former is for the
completion of the cycle in progress, and the latter is for the device internal circuitry to be precharged for the next active cycle.
Data out is not latched and is valid as long as the CAS clock
is active; the output will switch to the three-state mode when
the CAS clock goes inactive. To perform a read cycle, the write
(W) input must be held at the VIH level from the time the CAS
clock makes its active transition (tRCS) to the time when ittransitions into the inactive (tRCH) mode.

ADDRESSING THE RAM

WRITE CYCLE

The ten address bus pins on the device are time multiplexed
with two separate 1O-bit address fields that are strobed at the
beginning of the memory cycle by two clocks (active negative)
called the row address strobe (RAS) and the column address
strobe (CAS). A total of twenty address bits will decode one of
the 2,097,152 word locations in the module. The column address strobe follows the row address strobe by a specified
minimum and maxium time called tRCD, which is the row to
column strobe delay. This time interval is also referred to as the
multiplex window which gives flexibility to a system designer
to set up the external addresses into the RAM. These conditions have to be met for normal read or write cycles. This initial
portion of the cycle accomplishes the normal addressing of the
device. These are, however, two other variations in addressing
the module, one is called the RAS only refresh cycle (described later) where a 9-bit row address field is presented on
the input pins and latched by the RAS clock. The most significant bit on Row Address A9 is not required for refresh. The other variation, which is called page mode, allows the user to
column access all words within a selected row. (See PAGEMODE CYCLES section).

A write cycle is similar to a read cycle except that the write
(W) clock must go active (V IL level) at or before the CAS clock
goes active at a minimum twcs time. If the above condition is
met, then the cycle in progress is referred to as an early write
cycle. In an early write cycle, the write clock and the data in are
referenced to the active transition of the CAS clock edge.
There are two important parameters with respect to the write
cycle: the column strobe to write lead time (tCWL) and the row
strobe to write lead time (tRWLJ. These define the minimum
time that RAS and CAS clocks need to be active after the write
operation has started (W clock at VIL level).

PAGE·MODE CYCLES
Page mode operation allows fast successive data operations at all 1024 column locations on a selected row. Page access (!cAC) is typically half the regular RAS clock access
(tRAC) on the Motorola 1M dynamic RAM. Page mode operation consists of holding the RAS clock active while cycling the
CAS clock to access the column locations determined by the
1O-bit column address field.
The page cycle is always initiated with a row address being
provided and latched by the RAS clock, followed by the column
address and CAS clock. From the timing illustrated, the initial
cycle is a normal read or write cycle, that has been previously
described, followed by the shorter CAS cycles (tpc). The CAS
cycle time (tpC) consists of the CAS clock active time (tCAS),
and CAS clock precharge time (tcp) and two transitions. In
practice, any combination of read and write cycles can be performed to suit a particular application.

READ CYCLE

A read cycle is referred to as a normal read cycle to differentiate it from a page mode read cycle, which is covered in a later
section.
The memory read cycle begins with the row addresses valid
and the RAS clock transitioning from VIH to the VIL level. The
CAS clock must also make a transition from VIH to the VIL level
at the specified tRCD timing limits when the column addresses
are latched. Both the RAS and CAS clocks trigger a sequence
of events which are controlled by several delayed internal
clocks. Also, these clocks are linked in such a manner that the
access time of the device is independent of the address mUltiplex window. The only stipulation is that the CAS clock must be
active before or at the tRC~ximum specification for an access (data valid) from the RAS clock edge to be guaranteed
(tRAC). If the tRQ!2!!Iaximum condition is not met, the access
(tCAC) from the CAS clock active transition will determine read
access time. The external CAS signal is ignored until an internal RAS Signal is available. This gating feature on the CAS
clock will allow the external CAS signal to become active as
soon as the row address hold time (tRAH) specification has
been met and defines the tRCD minimum specification. The
time difference between tRCD minimum and tRCD maximum
can be used to absorb skew delays in switching the address
bus from the row to column addresses and in generating the
CAS clock.
Once the clocks have become active, they must stay active
for the minimum (tRAS) period for the RAS clock and the mini-

REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Therefore, to retain the correct information, the module needs to be refreshed at least
once every 16 milliseconds. This is accomplished by sequentially cycling through the 1024 row address locations every 16
,milliseconds (i.e., at least one row every 15.6 microseconds).
A normal read or write operation to the module will also refresh
all the words associated with the particular row(s) decoded.

RAS-Only Refresh
In this refresh method, the system must perform a
RAS-only cycle on 1024 row addresses every 16 milliseconds.
The row addresses are latched in with the RAS clock, and the
associated internal row locations are refreshed. As the
heading implies, the CAS clock is not required and must be
inactive or at a VIH level.

MOTOROLA MEMORY DATA
3-97

•

MCM36200-MCM36L200

CAS Before RAS Refresh

II

test is performed with read and write operations. During this
test, the internal refresh counter generates the row address,
while the external address input supplies the column address.
The entire array is refreshed after 1024 test cycles, as indicated by the check data written in each row. See CAS before
RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:

This refresh cycle is initiated when RAS falls, after CAS has
been low (by tCSR)' This activates the internal refresh counter
which generates the row address to be refreshed. Externally
applied addresses are ignored during the automatic refresh
cycle. "the output buffer was off before the automatic refresh
cycle, the output will stay in the high impedance state. " the
output was enabled by CAS in the previous cycle, the data out
will be maintained during the automatic refresh cycle as long
as CAS is held active (hidden refresh).
Hidden Refresh

1. Write "O"s into all memory cells (normal write mode).
2. Select a column address, and read "0" out of the cell by
performing CAS before RAS refresh counter test, read
cycle. Repeat this operation 1024 times.
3. Select a column address, and write "I" into the cell by
performing CAS before RAS refresh counter test, write
cycle. Repeat this operation 1024 times.
4. Read "1"s (normal read mode), which were written at step
3.
5. Repeat steps 1 to 4 using complement data.

The hidden refresh method allows refresh cycles to be performed while maintaining valid data at the output pin. Hidden
refresh is performed by holding CAS at VIL and taking RAS
high and after a specified precharge period (tRP), executing a
CAS before RAS refresh cycle. (See Figure t.)
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of the device can be tested with
a CAS before RAS refresh counter test. This refresh counter

MEMORY
CYCLE

DO -

REFRESH _ ....._REFRESH
CYCLE
CYCLE

~

HIGH-Z

VALID DATA-OUT

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)
MCM
Motorola Memory prefix--=:r-

36200 or 36L200

I

Part N u m b e r - - - - - - - - - - - - I

TT
x

Full Part Numbers - MCM36200S80
MCM36200S10
MCM36l200S80
MCM36L200S10

xx

Package (S =SIMM, SG =Gold Pad SIMM)

MCM36200SG80
MCM36200SG10
MCM36l200SG80
MCM36l200SG10

MOTOROL6. MEMORY DATA
3-98

_',"."~.".H'~'

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM36256
256K X 36 Bit Dynamic Random
Access Memory Module
The MCM36256S is a 9M, dynamic random access memory (DRAM) module organized as 262,144 x 36 bits. The module is a 72-lead single-in-line memory module
(SIMM) consisting of eight MCM514256A DRAMs housed in 20/26 J-Iead small outline packages (SOJ) and four CMOS 256K x 1 DRAMs housed in 18-lead PLCC
packages, mounted on a substrate along with a 0.22 f.lF (min) decoupling capacitor
mounted under each DRAM. The MCM514256A is a 1.0 f.l CMOS high speed, dynamic random access memory organized as 262,144 four-bit words and fabricated
with CMOS Silicon-gate process technology.
• Three-State Data Output
• Early-Write Common 110 Capability
• Fast Page Mode Capability
• TTL-Compatible Inputs and Outputs
• RAS Only Refresh
• CAS Before RAS Refresh
• Hidden Refresh
• 512 Cycle Refresh:
MCM36256 = 8 ms (Max)
• Consists of Eight 256K x 4 DRAMs, Four 256K x 1 DRAMs, and Twelve 0.22 f.lF
(Min) Decoupling Capacitors
• Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
• Fast Access Time (tRAC):
MCM36256S-70 = 70 ns (Max)
MCM36256S-80 = 80 ns (Max)
MCM36256S-10 = 100 ns (Max)
• Low Active Power Dissipation:
MCM36256S-70 = 5.17 W (Max)
MCM36256S-80 = 4.51 W (Max)
MCM36256S-10 = 3.85 W (Max)
• Low Standby Power Dissipation:
TTL Levels = 132 mW (Max)
CMOS Levels = 66 mW (Max)

•
PIN NAMES

PINOUT
Pin Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

13

AI

25

0024

37

0017

49

DQ9

61

0014

2

VSS
000

14

A2

26

007

38

0035

50

0027

62

0033

3

0018

15

A3

27

0025

39

51

0010

63

0015

4

001

16

A4

28

A7

40

VSS
CASO

52

0Q28

64

0034

5

0019

17

AS

29

NC

41

CAS2

53

0011

65

0016

6

002

18

A6

30

42

CAS3

54

0029

66

NC

7

0020

19

NC

31

VCC
A8

43

CASI

55

0012

67

POI

8

003

20

004

32

NC

44

RASO

56

0030

68

P02

9

0021

21

0022

33

NC

45

NC

57

0013

69

P03

10

VCC

22

005

34

RAS2

46

NC

58

0031

70

P04

11

NC

23

0023

35

0026

47

W

59

VCC

71

NC

12

AO

24

006

36

DQ8

48

NC

60

0032

72

VSS

1

MOTOROLA MEMORY DATA
3-99

AO-AS ................ Address Inputs
000-0035 . . . . . . . .. Data Input/Output
CASO-<:AS3 . .. Column Address Strobe
P01-P04 ........... Presence Detect
RASO, RAS2 ...... Row Address Strobe
W .................. ReadlWrite Input
VCC ................... Power (+ 5 V)
VSS ......................... Ground
NC ................... No Connection
All power supply and ground pins must be
connected for proper operation of the device.

MCM36256

BLOCK DIAGRAM
1/01
1/02

CAS
RAS

~O/E

•

I/OS

iii

AO-AS

I CAS
RAS

AO-AS

V04

iii

AO-AS

°out

ICAS
RAS

ICAS
RAS

1/04

iii

AO-AS

VOl
1/02
V03
V04

001S
0014
0015
0016

AO-AS

~

0017

iii

1/01
V02

001S
0019
0020
0021

VOS

iii

AO-AS

rOlE

ICAS
RAS

iii

AO-AS

1/04

iii

AO-AS

OO::J--l

0026

0027
0028
0029
OOSO

1/01
1102
I/OS

iii

AO-AS

1/04
1/01
V02

iii

AO-AS

I/OS
1104

iii

AO-AS

Qm

I

W
AO-AS
VCC
VSS

0022
0023
0024
0025

I/OS

CAS
RAS

~O/E

1/04
1/01
1/02

CAS
RAS

3

0Q9
0010
0011
0012

AO-AS

CAS
RAS

rOlE

OOS

I/OS

iii

CAS
RAS

~O/E

Oi~J--1

1/01
1/02

CAS
RAS

rOlE

0Q4
005
0Q6
007

I/OS

iii

CAS
RAS

rOlE

1/04
1/01
1/02

CAS
RAS

rOlE

000
001
002
OOS

OOSI
0032
003S
0034
0Q35

~

•

UO-Ull

------------T
___---------...

UO-Ull

I

0.221'F (MIN)

PRESENCE DETECT PIN OUT
Pin Name

70ns

80ns

100n8

POI
PD2
PD3
PD4

VSS

VSS

VSS

NC

NC

NC

VSS

NC

NC

VSS

VSS
VSS

MOTOROLA MEMORY DATA
3-100

MCM36256

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage

Symbol

Value

Unit

VCC

-1 to+ 7

V

Relative to VS~
(For Any Pin Except CC)

Vin, Vout

-1 to+ 7

V

Data Output Current per DQ Pin

lout

50

mA

Power Dissipation

PD

7.05

W

Operating Temperature Range

TA

Oto+70

Storage Temperature Range

Tsta

-2510+125

°c
°c

Vo~age

This device contains circuitry 10
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken 10
avoid applicatian of any vottage
higher than maximum rated voltages
to these high impedence circuits.

NOTE: Permanent device damage may occur ~ ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliabiltty.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Valtage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

-

6.5

V

1

O.B

v

1

Min

Max

Unit

Notes

mA

2

Logic High Voltage, All Inputs

VIH

2.4

Logic Low Vo~ge, All Inputs

VIL

-1.0

RECOMMENDED OPERATING CONDITIONS
Characteristic

Symbal

VCC Power Supply Current
MCM36256-70, tRC =130 ns
MCM36256-BO, tRC =150 ns
MCM36256-10, tRC =180 ns

ICCI

VCC Power Supply Current (Standby) (RAS =CAS = VI H)

ICC2

VCC Power Supply Current During RAS only Refresh Cycles
MCM36256-70, tRC = 130 os
MCM36256-80, tRC =150 ns
MCM36256-10, tRC =180 ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle
MCM36256-70, tpc =40 ns
MCM36256-80, tpc = 45 ns
MCM36256-10, tpc =55 ns

ICC4

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V)

ICC5

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM36256-70, tRC =130 ns
MCM36256-80, tRC =150 ns
MCM36256-10, tRC = 180 ns

ICC6

-

940
820
700
24

-

940
820
700

-

680
560
460

-

12

mA
mA

2

mA

2,3

rnA
rnA

940
820
700

Input Leakage Current (VSS " Yin " VCC)

Ilkg(l)

-120

120

Output Leakage Current (CAS at Logic 1, VSS';; Vout" VCC)

Ilkg(O)

-10

+10

IlA
IlA

Output High Voltage (IOH = - 5 mAl

VOH

2.4

-

V

Output Low Voltage (IOL = 4.2 mAl

VOL

-

0.4

V

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum current Is measured at the fastest cycle rate with the output open.
3. Measured with one address transition per page mode cycle.

MOTOROLA MEMORY DATA
3-101

2

•

MCM36256

CAPACITANCE (f =1.0 MHz, TA =25°e, Vee =5 V, Periodically Sampled Rather Than 100% Tested)
Symbol

Min

Max

Unit

Notas

Input Capacnance (AO-AS)

CI1

-

75

pF

1

Input Capacitance (W)

CI2

-

94

pF

1

Input Capacitance (RASa, RAS2)

CI3

-

52

pF

1

pF

1

COOl

-

31
17

pF

1

C002

-

22

pF

1

Characteristic

..

Input Capacitance (CASQ-CAS3)

CI4

I/O Capacnance (000-007, 009-0016, 0018-0025, 0027-0034)
I/O Capacnance (008, 0017, 0026, 0035)

NOTE: 1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 

VIH - --",-,.-...,......,.....". J.,..--.".,,..----::L "':--7I~"""'7\ ..r"7.:':-:::-~ _7M~,,"""'" -Jo,...-~:::_:01-

DO

MOTOROLA MEMORY DATA
3-129

".....".......,.......".....".....,......,.-.,,-

MCM40100-MCM40L100

RAS ONLY REFRESH CYCLE
(W Is Don'l Care)

~------------------- tRC------------------~

•

1 4 - - - - - - t RAS ----------~
__ V1H V
IL -

RAS

-------::i.

__ V1H - ~~~riI:__-H----------------,,~~r_----

CAS

r

V1L - ....................,

tASR~

ADDRESSES:: =XXXXXAD~~~SS)O/

DQ

VOH -

- - - - - - HIGHZ

VALID DATA OUT

VOL -

EARLY WRITE CYCLE

V1H RAS

V1L -

V1H CAS

V 1L -

ADDRESSES VIH V1L -

iii

VIH -

~"""""""7\

V1L -

~~~~~~~~~f--+--+--~~~~~~~~~~~~~~~~~~~~

MOTOROLA MEMORY DATA

3-140

MCM40200-MCM40L200

FAST PAGE MODE READ CYCLE
_
V1H - --~
RAS
V1L -

1 + - - - - - - - - - - - - - tRASP

---------------1~

to----t PC

-+--~

_
V1H CAS V

IL -

DO VOH - _ _ _ _ _ _ _ _ _-(1
VOL -

FAST PAGE MODE EARLY WRITE CYCLE
_
V1H RAS V

IL -

ADDRESSES VIH V1L -

DO

VIH - .....,.....,......,.........,....."" -J,,--..,.,.,.,.,,,..--.l..

~,.......,......,. ~...,.",c:=-~

VIL - ->L->L....ll.....lL...~ ,,~;......;~--r-

"-.,;>L....:>t....Y

Jr""l..,\7......".

.J,---,-,:-:-:::-~ ~,......,.......,......,.,.....,.....,......,.....

..,.....;;.;.;;.~--r- "-l'"l\l'~ ~~"';""..:If" "-:IL..-"~L..Joj~....lL.~

MOTOROLA MEMORY DATA
3-141

MCM40200-MCM40L200

RAS ONLY REFRESH CYCLE
(Vi Is Don't Care)

~-------------------tRC------------------~

•

~---------

t RAS ----------~

__ VIH V
IL -

RAS

------~

CAS

.....-:><"-"l,...-,n:----I-+------------------------,....-------"""*""',......,,..----------

__ VIH V
IL - .<......>'-"'-'"

r
ADDRESSES~:: =XXXMAD~~~SS:xxXXXXXXXXXXXXXXXXXX'--___
tAS~

CAS BEFORE RAS REFRESH CYCLE
(AO-A9 is Don't Care)

CAS

__ V1H V
IL -

_ V1H W

VIL-~~*~Y

HIGHZ

MOTOROLA MEMORY DATA
3-142

MCM40200-MCM40L200

HIDDEN REFRESH CYCLE (READ)

CAS

•

V1L -

ADDRESSES V IH V1L -

Vi

V1H -

~~~~~~~-+---r----------~~~~---------i~~~~~~~7r?r?r~~

V IL -

--"--"--"--".,..,...-"

DQ VOH -

-------------------<1

VOL -

HIDDEN REFRESH CYCLE (EARLY WRITE)

__ V1H RAS V IL

__ VIH CAS V
IL -

ADDRESSES VIH V1L _ VIH W
V IL -

.~,.....,.,....,.,...."-.,.,-,,.

.....lo<-><-01

MOTOROLA MEMORY DATA
3-143

MCM40200-MCM40L200

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

---~

•

f o o o - - - - - - - - - - - t R A S - - - - - - - - - . - j ...i<,....-----.J
~-----tRSH ----~

.J.:----,i. J-----tCAS

ADDRESSES YylH IlREAD CYCLE

HIGH z ---+--+-+----<1

MOTOROLA MEMORY DATA
3-144

r....l.,:I,----

MCM40200- MCM40L200

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the module. During an extended inactive
state (greater than 16 milliseconds with the device powered
up), a wake up sequence of eight active cycles is necessary to
ensure proper operation.
ADDRESSING THE RAM
The ten address pins on the device are time multiplexed at
the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 1O-bit address fields. A total of twenty address bits, ten
rows and ten columns, will decode one of the 1,048,576 word
locations in the device. RAS active transition is followed by
CAS active transition (active =VIL,.!Bc.D minimum)for all read
or write cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system designer flexibility in setting up the external addresses into the
RAM.
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the module:
RAS only refresh cycle, CAS before RAS refresh cycle,
and page mode. All three are discussed in separate sections
that follow.
READ CYCLE
The DRAM may be read with either a "normal" random read
cycle or a page mode read cycle. The normal read cycle is outlined here, while the page mode cycle is discussed in a separate section.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (W) input level must be high
(VIH). tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The internal clocks are linked in such a manner that the read access
time of the device is independent of the address multiplex window. CAS controls read access time: CAS must be active before or at tRCD maximum to guarantee valid data out (DO) at
tRAC (access time from RAS active transition). If the tRCD
maximum is exceeded, read access time is determined by the
CAS clock active transition (tCAC)'
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. Wmust remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data at that bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitry for the next active
cycle. DO is valid, but not latched, as long as the CAS clock is
active. When the CAS clock transitions to inactive, the output

will switch to High Z (three-state) tOFF after the inactive transition.
WRITE CYCLE
The user can write to the DRAM with either an early write or a
page mode early write cycle. Early write mode is discussed
here, while page mode write operations are covered in a separate section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
(V!.!.} Early write mode is distinguished by the active transition
of W, with respect to CAS. Minimum active time tRAS and
tCAS, and precharge time tRP apply to write mode, as in the
read mode.
An early write cycle is characterized by Wactive transition at
minimum time twcs before CAS active transition. Data in
(DO) is referenced to CAS in an early write cycle. RAS and
CAS clocks must stay active for tRWL and tCWL' respectively,
after the start of the early write operation to complete the cycle.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
1024 column locations on a selected row of the module. Read
access time in page mode (tcAd is typically half the regular
RAS clock access time, tRAC' Page mode operation consists
of keeping RAS active while toggling CAS between VIH and
~The row is latched by RAS active transition, while each
CAS active transition allows selection of a new column location
on the row.
A page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for
minimum tcp, while RAS remains low (VILl. The second CAS
active transition while RAS is low initiates the first page mode
cycle (tpC)' Either a read or write operation can be performed
in a page mode cycle, subject to the same conditions as in normal operation (previously described). These operations can
be intermixed in consecutive page mode cycles and performed
in any order. The maximum number of consecutive page mode
cycles is limited by tRASP' Page mode operation is ended
when RAS transitions to inactive, coinCident with or following
CAS inactive transition.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge storage for each bit in the array. This charge will tend to degrade
with time and temperature. Each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in the
MCM40200 require refresh every 16 milliseconds, while refresh time for the MCM40L200 is 128 milliseconds.
This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM40200, and 124.8 microseconds for
the MCM40L200. Burst refresh, a refresh of all 1024 rows consecutively. must be performed every 16 milliseconds on the
MCM40200 and 128 milliseconds on the MCM40L200.
A normal read or write operation to the RAM will refresh all
the bits associated with the particular row decoded. Three other methods of refresh, RAS-only refresh, CAS before RAS
refresh, and hidden refresh are available on this device for
greater system flexibility.

MOTQROLA MEMORY DATA
3-146

•

MCM40200-MCM40L200

•

RAS-Only Refresh

CAS BEFORE RAS REFRESH COUNTER TEST

RAS-only refresh consists of RAS transition to active,latching the row address to be refreshed, while CAS remains high
(VI H) throughoutthe cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.

The internal refresh counter of the device can be tested with
a CAS before RAS refresh counter test. This refresh counter
test is performed with read and write operations. During this
test, the internal refresh counter generates the row address,
while the external address Input supplies ttie column address.
The entire array is refreshed after 1024 test cycles, as indicated by the check data written in each row. See CAS before
RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:

CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order actives an internal refresh counterthat generaies the row address to be refreshed. Extemal address lines are ignored during the automatic refresh cycle. The
output buffer remains at the same state it was in during the previous cycle (hidden refresh). Wmust be inactive for time twRP
before and time twRH after RAS active transition to prevent
switching the device into a test mode cycle.

1. Write "O"s into all memory cells (normal write mode).
2. Select a column address, and read "a" out of the cell by
performing CAS before RAS refresh counter test, read
cycle. Repeat this operation 1024 times.
3. Select a column address, and write "I" into the cell by
performing CAS before RAS refresh counter test, write
cycle. Repeat this operation 1024 times.
4. Read "1"s (normal read mode), which were written at step
3.
5. Repeat steps 1 to 4 using complement data.

Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). Wis subject to the same conditions
with respect to RAS active transition (to prevent test mode
cycle) as in CAS before RAS refresh.

REFRESH
CYCLE

DQO-OQ31,ECCo-ECC7 -

HIGH·Z

VALID DATA'()UT

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)
MCM
Motorola Memory p r e f i x - I

40200 or 40L2oo

I

PartNumber---------~

TT
x

xx

-,,,,. "'"'" .

.om, " . ",""

Package (S = SIMM, SG = Gold Pad SIMM)

Full Part Numbers - MCM40200S70
MCM40200S80
MCM40200S10
MCM40L200S70
MCM40L200S80
MCM40L200S10

MCM40200SG70
MCM40200SG80
MCM40200SG10
MCM40L200SG70
MCM40L200SG80
MCM40L200SG10

MOTOAOLA MEMORY DATA

3-146

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

256K X 40 Bit Dynamic Random Access
Memory Module

MCM40256
MCM40L256

for Error Correction Applications
The MCM40256S and MCM40L256S are 10M, dynamic random access memory
(DRAM) modules organized as 262,144 x 40 bits. The module is a 72-lead
single-in-line memory module (SIMM) consisting of ten MCM514256A DRAMs
housed in 20/26 J-Iead small outline packages (SOJ), mounted on a substrate along
with a 0.22 I1F (min) decoupling capacitor mounted under each DRAM. The
MCM514256A is a 1.011 CMOS high speed, dynamic random access memory
organized as 262,144 four-bit words and fabricated with CMOS silicon-gate process
technology.
• Three-State Data Output
• Early-Write Common I/O Capability
• Fast Page Mode Capability
• TTL-Compatible Inputs and Outputs
• RAS Only Refresh
• CAS Before RAS Refresh
• Hidden Refresh
• 512 Cycle Refresh:
MCM40256 = 8 ms (Max)
MCM40L256 = 64 ms (Max)
• Consists of Ten 256K x 4 DRAMs, and Ten 0.22 I1F (Min) Decoupling Capacitors
• Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
• Fast Access Time (tRAC): MCM40256S-70 = 70 ns (Max)
MCM40256S-80 = 80 ns (Max
MCM40256S-10 = 100 ns (Max)
• Low Active Power Dissipation: MCM40256S-70 = 4.40 W (Max)
MCM40256S-80 = 3.85 W (Max)
MCM40200S-10 = 3.30 W (Max)
• Low Standby Power Dissipation:
TTL Levels = 110 mW (Max)
CMOS Levels (MCM40256) = 55 mW (Max)
(MCM40L256) = 11 mW (Max)

PINOUT
Pin

1~0

~O
~O

iO

10
36~0
37~0

10
~O

~O

72

10
~

0 ••••

PIN NAMES

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

1

VSS

13

Al

25

0022

37

ECC3

49

DQ8

61

0013

2

OQO

14

A2

26

007

38

ECC4

50

0Q24

62

0020

3

0016

15

A3

27

0023

39

VSS

51

0Q9

63

0014

4

001

16

A4

28

A7

40

CASO

52

0025

64

0031

5

0017

17

AS

29

ECCO

41

CAS2

53

0010

65

0015

6

002

lS

A6

30

VCC

42

CAS3

54

0026

66

ECC6

7

001S

19

NC

31

AS

43

CASl

55

0011

67

POl

8

003

20

004

32

NC

44

RASO

56

0027

66

P02
P03

9

0019

21

0020

33

NC

45

NC

57

0012

69

10

VCC

22

DOS

34

RAS2

46

ECC5

58

0028

70

P04

11

NC

23

0021

35

ECCl

47

W

59

VCC

71

ECC7

12

AO

24

006

36

ECC2

48

CD

60

0029

72

VSS

MOTOROLA MEMORY DATA
3-147

AO-AB ................ Address Inputs
000-0031 ......... Data InpuYOutput
ECCo-ECC7 .. Error Correction Data I/O
CASO-CAS3 ... Column Address Strobe
PD1-PD4 .......... " Presence Detect
RASa, RAS2 ...... Row Address Strobe
Vii .. .. .. . .. .. . .. .. ... ReadlWrite Input
CD . . . . . . . . . . .. Configuration Detection
VCC ................... Power (+ 5 V)
VSS ........................ Ground
NC .................... No Connection
All power supply and ground pins must be
connected for proper operation of the device.

•

MCM40256-MCM40l256

256K x 40 BLOCK DIAGRAM

AO-Ail

1/01
1/02
1/03
1/04

000
001
002
003

0Q4
005
006

AO-A8

1/01
1/02
1/03
1/04

DOB
0Q9

AD-Ail

VOl
1/02
1/03
1104

AD-A8

VOl
1/02
V03
1/04

0012
0013
0014
0015

AD-A8

1/01
1/02
1/03
V04

0016
0017
001B
0019

AD-As

1/01
1/02
1/03
1/04

0020
0021
0022
0023

AD-Ail

1/01
1/02
1/03
1/04

0024
0025
0026
0027

AD-A8

1/01
1/02
1/03
V04

0028
0029
0030
0031

1/01

ECCO

AD-Ail

1/02
1/03
1/04

ECCl
ECC2
ECGS

AD-AS

1/01
1/02
1/03
1/04

ECC4
ECC5
ECC6
ECC7

CAS
RAS

rOE
rOE
rOE
rOE
rOE

•

iN

CAS
RAS

iN

CAS
RAS

iN

CAS
RAS

iN

CAS
RAS

iN

CAS
RAS

~OE

iN

CAS
RAS

~OE

iN

CAS
RAS

~OE

iN

CAS
RAS

~OE

iN

CAS
RAS

~OE
W

iN

D07

0010
0011

J

J

AD-Ail

VCC---------------I-------.~

UD-U9

0.221lF (MIN)

T~-----__I~.

V S S - - - - - - - - - - - - - -.....

Presence Detect Pin Out
Pin Name

70ns

SOns

100ns

POl
P02
P03
P04

VSS

VSS

NC

VSS

Vrfe
VSS
VSS

CD

Vr>,r>,

Vr>,r>,

VSS

NC

VSS

NC
NC

MOTOROLA MEMORY DATA
3-148

UD-U9

MCM40266-MCM40L256

ABSOLUTE MAXIMUM RATINGS (See Note)
Symbol

Value

Unit

VCC

-1 to+ 7

V

Yin, Vout

-1 to+ 7

V
mA

Rating
Power Supply Voltage
Voltage Relative to VSS
(For Any Pin Except VCC)
Data Output Current per DQ Pin

lout

50

Power Dissipation

Po

6.0

W

Operating Temperature Range

TA

o to + 70

'C

Storage Temperature Range

TSIll

-25to+125

'c

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, il is advised thai
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to these high-impedance circutts.

NOTE: Permanent device damage may occur HABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliabiltty.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%, TA =0 to 70·C, Unless Otherwise Noted)
RECOMMENDED OPERAnNG CONDInONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

lYP

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

-

6.5

V

1

O.B

v

1

Min

Max

Unit

Notes

-

BOO
700

mA

2

-

800
700
600

Logic High Voltage, All Inputs

VIH

2.4

Logic Low Voltage, All Inputs

VIL

-1.0

RECOMMENDED OPERATING CONDITIONS
Characteristic
VCC Power Supply Current

Symbol
MCM40256-70, tRC = 130 ns
MCM40256-80, tRC = 150 ns
MCM40256-10, tRC = lBO ns

ICCI

VCC Power Supply Current (Standby) (RAS = CAS = VIH)

ICC2

VCC Power Supply Current
During RAS only Refresh Cycles

MCM40256-70, tRC = 130 ns
MCM40256-BO, tRC = 150 ns
MCM40256-10, IRC = 180 ns

ICC3

MCM40256-70, tpc = 40 ns
MCM40256-BO, tpc = 45 ns
MCM40256-10,tpC = 55 ns

ICC4

VCC Power Supply Current
During Fast Page Mode Cycle

ICC5

VCC Power Supply Current
During CAS Before FiAS Refresh Cycle

ICC6

MCM40256-70, tRC = 130 ns
MCM40256-BO,tRC = 150 ns
MCM40256-10,tRC = lBO ns

20

mA
mA

2

600
500
400

mA

2,3

10
2

mA

-

-

BOO
700
600

mA

-

3.0

-

VCC Power Supply Current (Stsndby) (RAS = CAS = VCC - 0.2 V) MCM40256
MCM40L256

600

mA

VCC Power Supply Current B,!!!ery Backup Mode (tRC = 1251'S; CAS = CAS
before RAS Cycling or 0.2V; W, DO, AO-AB = VCC-C.2V or 0.2V) tRAS = 1J!S
MCM4OL256 only

ICC7

Input Leakage Current (VSS,;; Vin';; VCC)

Ilkg(l)

-100

100

Ilkg(O)

-10

+10

IlA
IlA

Output High Voltage (IOH = - 5 mAl

VOH

2.4

-

V

Output Low Voltage (IOL = 4.2 mAl

VOL

-

0.4

V

Output Leakage Current (CAS at Logic I, VSS';; Vout';; VCC)

2

NOTES:
1.
All voltages referenced to VSS.
2.
Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
Measured with one address transition per page mode cycle.
3.

MOTOROLA MEMORY DATA
3-149

MCM40256- MCM40L256

CAPACITANCE (f = 1 .0 MHz, T A = 25°C,

Vee = 5 V, Periodically Sampled Rather Than 100% Tested)
Symbol

Min

Max

Unit

Notas

Input Capacitance (AO-AS)

Cll

-

60

pF

1

Input Capacitance (W)

CI2

-

SO

pF

1

Input Capacitance (RASO, RAS2)

CI3

-

45

pF

1

Input Capacitance (CASQ--CAS3)

CI4

-

31

pF

1

17

pF

1

17

pF

1

Characteristic

•

I/O Capacitance (000-0031)

COOl

1/0 Capacijance (ECCo-ECC7)

C002

NOTE: 1.

Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 tJ. t I tJ. V.

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vce = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)

Symbol
Parameter
Random Read or Write Cycle Time

Standard

MCM40256-70

MCM40256-80

MCM40256-10

Alternate

Min

Min

Max

Min

Max

Unit

Notes

-

150

-

180

-

ns

5

Max

tRELREL

tRC

130

Page Mode Cycle Time

tCELCEL

tpc

40

-

45

-

55

-

ns

Access Time from RAS

tRELOV

tRAC

70

80

100

ns

25

ns

6, S

50

ns

6,9
6

Access Time from CAS

teELOV

teAC

Access Time from Column Address

tAVOV

tAA

Access Time from Precharge CAS

teEHOV

tePA

-

35

-

40

-

50

ns

CAS to Output in Low-Z

tCELOX

tCLZ

0

-

0

-

0

-

ns

6

Output Buffer and Tum-Off Delay

teEHOZ

toFF

0

20

0

20

0

20

ns

10

Transition Time (Rise and Fall)

20
35

20
40

6,7

tT

IT

3

50

3

50

3

50

ns

RAS Precharge Time

tREHREL

tRP

50

-

60

-

70

-

ns

RAS Pulse Width

tRELREH

tRAS

70

10,000

80

10,000

100

10,000

ns

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

70

100,000

80

100,000

100

100,000

ns

RAS Hold Time

tCELREH

tRSH

20

-

20

-

25

-

ns

teSH

70

-

80

-

100

-

ns

tCAS

20

10,000

20

10,000

25

10,000

tRCO

20

50

20

60

25

75

ns

11

tRAD

15

35

15

40

20

50

ns

12

CAS Hold Time
CAS Pulse Width
RAS to CAS Delay Time
RAS to Column Address Delay Time

tRELCEH
tCELCEH
tRELCEL
tRELAV

ns

(continued)
NOTES:
1.
VIH min and VIL max are reference levels for measuring timing of l!!ru!! signals. Transition times are measured between VIH and VIL.
2.
An initial pause of 2001's is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3.
The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VI H) in a monotonic manner.
4.
AC measurements tT = 5.0 ns.
5.
The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (O°C S TAS
70°C) is assured.
6.
Measured with a currentload equivalentto 2 TIL (-200 1lA, +4 mAl loads and 100 pF with the dataoutputtrip points set atVOH =2.0 Vand
VOL =O.S V.
7.
Assumes that tRCO S tRCD (max).
S.
Assumes that tRCD ;, tRCO (max).
9.
Assumes that tRAD ;, tRAD (max).
10. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11.
Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by teAC.
12.
Operation within the tRAO (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max), then access time is controlled exclusively by tAA.

MOTOROLA MEMORY DATA
3-150

MCM40256·MCM40L256

READ AND WRITE CYCLES (Continued)
MCM40256-70

MCM40256-80

MCM40256-10

Standard

Symbot
Alternate

Min

Max

Min

Min

CAS to RAS Precharge Time

tcEHREL

tCRP

5

5

-

10

-

ns

CAS Precharge Time (Page Mode
Cyle Only)

tcEHCEL

tcp

10

-

10

-

10

-

ns

tAVREL

tASR

0

tRAH

-

0

10

10

tASC

0

-

0

-

15

-

60

-

Parameter

Row Address Setup Time
Row Address Hold Time
Column Address Setup Time

tRELAX
tAVCEL

Column Address Hold Time

tcELAX

tcAH

t5

Column Address Hold Time
Referenced to RAS

tRELAX

tAR

55

-

ns

20

-

ns

ns

ns

13
13

75

ns

-

0

-

ns

15

-

15

-

20

-

ns

55

-

60

-

75

-

ns

twp

15

-

ns

20

25

-

ns

tCWL

20

-

20

25

tos

0

ns

14

tOH

15

15

-

20

-

ns

14

tRELOX

tOHR

55

-

0

-

ns

0

-

20

tRWL

-

15

20

60

-

75

-

ns

tRVRV

tRFSH

-

8
64

8

8
64

ms

Read Command Hold Time
Referenced to CAS

tcEHWX

tRCH

0

Read Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

Write Command Hold Time
Referenced to CAS

tcELWH

twCH

Write Command Hold Time
Referenced to RAS

tRELWH

twCR

Write Command Pulse Width

twLWH
twLREH
twLCEH
tOVCEL
tCELOX

MCM40256
MCM40L256

ns

0

0

0

Refresh Period

ns

-

-

40

-

RAS

-

0

-

0

Data in Hold Time Referenced to

-

-

0

-

64

-

ns

Write Command Setup Time

twLCEL

twcs

0

-

0

CAS Setup Time for CAS Before

tRELCEL

tCSR

10

-

10

-

10

-

ns

CAS Hold Time for CAS Belore RAS tRELCEH

tCHR

30

-

30

-

30

-

ns

CAS Precharge to CAS Active Time

tREHCEL

tRPC

0

-

0

-

ns

tCEHCEL

tcPT

40

-

0

CAS Precharge Time for CAS
Before RAS Counter Test

40

-

50

-

ns

RAS Refresh

•

0
15

0

35

tRCS

Data in Hold Time

Notes

-

tRAL

twHCEL

Data in Setup Time

Unit

50

tAVREH

Read Command Setup Time

Write Command to CAS Leed Time

Max

-

Column Address to RAS Lead Time

Write Command to RAS Lead Time

Max

Refresh

-

-

0

ns

15

CAS Precharge Time
10
ns
10
15
tcEHCEL
tcPN
NOTES:
13.
Either tRRH or tRCH must be satisfied lor a read cycle.
14. These parameters are referenced to CAS leading edge in random write cycles.
15. twcs is not a restnctiveoperating parameter. II is included in the data sheet as an electrical characteristic only; fftwCS ~ twcs (min), the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is not
satisffed, the condition of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
3-151

MCM40266-MCM40L256

READ CYCLE

•

RAS

VIHVIL -

CAS

VIHVIL -

ADDRESSES VIHVIL -

iN

VIHVIL -

VOHDO
(DATA OUT)
VOL -

MOTOROLA MEMORY DATA
3-162

MCM40256- MCM40L256

FAST PAGE MODE READ CYCLE
_ _ _""\I " " . . - - - - - - -

RAS

tRASP-------+I

VIH-

..

VIL -

VIH -

---lr--++---~h

CAS
VIL -

ADDRESSES

VIHVIL -

DO VOH(DATA OUT) VOL -

-----------1
tcLZ--.tI4-

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

RAS

VIH VIL -

VIH -

CAS
VIL -

ADDRESSES

VIH VIL -

W

VIH VIL -

DO

(DATAlN)

VIH VIL -

MOTOROLA MEMORY DATA
3-153

MCM40256-MCM40L256

~ ONLY REFRESH CYCLE
~ and A8 are Don't Care)

1....
. . - - - - - - - tRC--------+I
--'-'~--...IIr_--"'--_.j

RAS

VIH

- ---""\I 1...... . - - - - - tRAS

VIL

'-

VIH

-

CAS

ADDRESSES

DO VOH (DATA OUT)
- - - - - - - - - - HIGH-Z-----------

VOL -

~ BEFORE RAS REFRESH CYCLE

(Wand AO to A8are DOn't Care)

14------ t R C - - - - - - + t
RAS

VIH VIL -

CAS
VIL -

DO VOH (DATA OUT)

----,l~--'_______

HIGH-Z _ _ _ _ _ _ __

VOL -

MOTOROLA MEMORY DATA
3-154

MCM40256-MCM40L256

HIDDEN REFRESH CYCLE (READ)

-----.114---

V,H -

tRAS--'

•

-ofr--+I------.

V,L -

ADDRESSES

DO VOH (DATA OUT)
VOL -

--------I--i

VALID DATA

HIDDEN REFRESH CYCLE (WRITE)
- - - - - + 1 1 4 - - - tRAS
RAS

V,H V,L

-

V,H

-

V,L

-

V,L

-

CAS

ADDRESSES

W

V,H V,L

DO
(DATA IN)

-

V,H V,L

-

..

•

tDHR

MOTOROLA MEMORY DATA
3-156

MCM40256·MCM40L256

~

BEFORE RAS REFRESH COUNTER TEST CYCLE
tRAS --------t~

~

RAS

•

VIH VIL -

VIH CAS
VIL -

VIH ADDRESSES
VIL READ CYCLE
DO VOH (DATA OUT)
VOL -

W

VIH VIL -

WRITE CYCLE

W

VIH VIL -

DO
(DATA IN)

VIH VIL -

MOTOROLA MEMORY DATA
3-156

MCM40256-MCM40L256

DEVICE INITIALIZATION

On power-up an initial pause of 200 microseconds is required for the internal substate generator pump to establish the
correct bias voltage. This is to be followed by a minimum of
eight active cycles olthe row address strobe (clock) to initialize
the various dynamic nodes internal to the module. During an
extended inactive state of the module (greater than 4 milliseconds with device powered up), the wakeup sequence (8 active
cycles) will be necessary to assure proper device operation.

stay inactive for the minimum (tRP) time. The former is for the
completion of the cycle in progress, and the latter is for the device internal circuitry to be precharged for the next active cycle.
Data out is not latched and is valid as long as the CAS clock
is active; the output will switch to the three-state mode when
the CAS clock goes inactive. To perform a read cycle, the write
(iii) input must be held at the VIH level from the time the CAS
clock makes its active transition (tRCS) to the time when ittransitions into the inactive (tRCH) mode.
WRITE CYCLE

ADDRESSING THE RAM

The nine address bus pins on the device are time multiplexed with two separate 9-bit address fields that are strobed
atthe beginning of the memory cycle by two clocks (active negative) called the row address strobe (RAS) and the column address strobe (CAS). A total of eighteen address bits will decode
one of the 262,144 word locations in the device. The column
address strobe follows the row address strobe by a specified
minimum and maximum time called tRCD, which is the row to
column strobe delay. This time interval is also referred to as the
multiplex window which gives flexibility to a system designer
to set up the external addresses into the RAM. These conditions have to be met for normal read or write cycles. This initial
portion of the cycle accomplishes the normal addressing of the
device. These are, however, other variations in addressing the
module: the refresh modes (RAS only refresh, CAS before
RAS refresh, hidden refresh), and another mode called page
mode which allows the user to column access all words within
a selected row. The refresh mode and page mode operations
are described in more detail in later sections.
READ CYCLE

A read cycle is referred to as a normal read cycle to differentiate it from a page mode read cycle, which is covered in a later
section.
The memory read cycle begins with the row addresses valid
and the RAS clock transitioning from VIH to the VIL level. The
CAS clock must also make a transition from VIH to the VIL level
atthe specified tRCD timing limits when the column addresses
are latched. Both the RAS and CAS clocks trigger a sequence
of events which are controlled by several delayed internal
clocks. Also, these clocks are linked in such a manner that the
access time of the device is independent of the address multiplex window. The only stipulation is that the CAS clock must be
active before or at the tRc~ximum specification for an access (data valid) from the RAS clock edge to be guaranteed
(tRAC). If the tRQQ.!!laximum condition is not met, the access
(tCAC) from the CAS clock active transition will determine read
access time. The external CAS Signal is ignored until an internal RAS signal is available. This gating feature on the CAS
clock will allow the external CAS signal to become active as
soon as the row address hold time (tRAH) specification has
been met and defines the tRCD minimum specification. The
time difference between tRCD minimum and tRCD maximum
can be used to absorb skew delays in switching the address
bus from the row to column addresses and in generating the
CAS clock.
Once the clocks have become active, they must stay active
for the minimum (tRAS) period for the RAS clock and the minimum (tCAS) period for the CAS clock. The RAS clock must

A write cycle is similar to a read cycle except that the write
(W) clock must go active (VIL level) at or before the CAS clock
goes active at a minimum twcs time. I! the above condition is
met, then the cycle in progress is referred to as an early write
cycle. In an early write cycle, the write clock and the data in are
referenced to the active transition of the CAS clock edge.
There are two important parameters with respect to the write
cycle: the column strobe to write lead time (tcwLl and the row
strobe to write lead time (tRWL). These define the minimum
time that RAS and CAS clocks need to be active after the write
operation has started (W clock at VIL level).
PAGE-MODE CYCLES

Page mode operation allows fast successive data operations at all 512 column locations on a selected row. Page access (tCAC) is typically hal! the regular RAS clock access
(tRAC) on the Motorola 1M dynamic RAM. Page mode operation consists of holding the RAS clock active while cycling the
CAS clock to access the column locations determined by the
1O-bit column address field.
The page cycle is always initiated with a row address being
provided and latched by the RAS clock, followed by the column
address and CAS clock. From the timing illustrated, the initial
cycle is a normal read or write cycle, that has been previously
described, followed by the shorter CAS cycles (tpC). The CAS
cycle time (tpC) consists of the CAS clock active time (tCAS),
and CAS clock precharge time (tcp) and two transitions. In
practice, any combination of read and write cycles can be performed to suit a particular application.
REFRESH CYCLES

The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Therefore, to retain the correct information, the module needs to be refreshed at least
once every 8 milliseconds. This is accomplished by sequentially cycling through the 512 row address locations every 8 milliseconds (I.e., at least one row every 15.6 microseconds). A
normal read or write operation to the module will also refresh
all the words associated with the particular row(s) decoded.
RAS-Only Refresh

In this refresh method, the system must perform a
RAS-only cycle on 512 row addresses every 8 milliseconds.
The row addresses are latched in with the RAS clock, and the
associated internal row locations are refreshed. As the
heading implies, the CAS clock is not required and must be
inactive or at a VIH level.

MOTOROLA MEMORY DATA
3-157

•

MCM40256-MCM40L256

CAS Before RAS Refresh

..

test is performed with read and wrne operations. During this
test, the internal refresh counter generates the row address,
while the external address input supplies the column address.
The entire array is refreshed after 512 test cycles, as indicated
by the check data written in each row. See CAS before RAS
refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:

This refresh cycle is initiated when. RAS falls, after CAS has
been low (by leSR). This activates the internal refresh counter
which generates the row address to be refreshed. Externally
applied .addresses are ignored during the automatic refresh
cycle. If the output buffer was off before the automatic refresh
cycle, the output will stay in the high-impedance state. If the
output was enabled by CAS in the previous cycle, the data out
will be maintained during the automatic refresh cycle as long
as CAS is held active (hidden refresh).
Hidden Refresh

1. Write "0"5 into all memory cells (normal write mode).
2. Select a column address, and read "0" out of the cell by
performing CAS before RAS refresh counter test, read
cycle. Repeat this operation 512 times.
3. Select a column address, and write "1" into the cell by
performing CAS before RAS refresh counter test, write
cycle. Repeat this operation 512 times.
4. Read "1 "5 (normal read mode), which were written at step
3.
5. Repeat steps 1 to 4 using complement data.

The hidden refresh method allows refresh cycles to be performed while maintaining valid data at the output pin. Hidden
refresh is performed by holding CAS at ViL and taking RAS
high and after a specified precharge period (tRP), executing a
CAS before RAS refresh cycle. (See Figure 1.)

CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of the device can be tested with
a CAS before RAS refresh counter test. This refresh counter

REFRESH
CYCLE

DO -

HIGH-Z

VALID DATA-OUT

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory

prefiX~

40256 or 40L256

I

Part N u m b e r - - - - - - - - - - - - '

x

xx

T T_
L-

Full Part Numbers - MCM40256S70
MCM40256S80
MCM40256S10
MCM40L256S70
MCM40L256S80
MCM40L256S10

Package (S = SIMM, SG = Gold Pad SIMM)

MCM40256SG70
MCM40256SG80
MCM40256SG10
MCM40L256SG70
MCM40L256SG80
MCM40L256SG10

MOTOROLA MEMORY DATA
3-158

Speed (70 = 70 ns, 80 = 80 ns, 10 =100 os)

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

512K X 40 Bit Dynamic Random Access
Memory Module

MCM40512
MCM40L512

for Error Correction Applications

•

The MCM40512S and MCM40l512S are 20M, dynamic random access
memory (DRAM) modules organized as 524,288 x 40 bits. The module is a
double-sided 72-lead single-in-line memory module (SIMM) consisting of
twenty MCM514256A DRAMs housed in 20/26 J-Iead small outline packages
(SOJ), mounted on a substrate along with a 0.2211F (min) decoupling capacitor
mounted under each DRAM. The MCM514256A is a 1.011 CMOS high speed,
dynamic random access memory organized as 262,144 four-bit words and
fabricated with CMOS silicon-gate process technology.
• Three-State Data Output
• Early-Write Common 1/0 Capability
• Fast Page Mode Capability
• TTL-Compatible Inputs and Outputs
• RAS Only Refresh
• CAS Before RAS Refresh
• Hidden Refresh
• 1024 Cycle Refresh:
MCM40512 = 8 ms (Max)
MCM40L512 = 164 ms (Max)
• Consists of Twenty 256K x 4 DRAMs, and Twenty 0.2211F (Min) Decoupling Capacitors
• Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
MCM40512S-70 = 70 ns (Max)
• Fast Access Time (tRAC):
MCM40512S-80 = 80 ns (Max)
MCM40512S-10 =100 ns (Max)
• low Active Power Dissipation: MCM40512S-70 = 4.51 W (Max)
MCM40512S-80 = 3.96 W (Max)
MCM40512S-10 = 3.41 W (Max)
• low Standby Power Dissipation:
TTL levels =220 mW (Max)
CMOS Levels (MCM40512) = 110 mW (Max)
(MCM40L512) = 22 mW (Max)
PIN NAMES

PINOUT
Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

Pin

Name

1

Vss

13

Al

25

0022

37

ECC3

49

008

61

0013

2

000

14

A2

26

007

38

ECC4

50

DQ24

62

0020

3

0016

15

A3

27

0023

39

Vss

51

D09

63

0014

4

001

16

A4

28

A7

40

CASO

52

0025

64

0031

5

0017

17

A5

29

ECCO

41

CAS2

53

0010

65

0015

6

002

18

A6

30

VCC

42

CAS3

54

0026

66

ECC6

7

0018

19

NC

31

A8

43

CASl

55

0011

67

POl

8

003

20

DQ4

32

A9

44

RASO

56

0027

68

PD2

9

0019

21

0020

33

RAS3

45

RASl

57

0012

69

PD3

10

VCC

22

005

34

RAS2

46

ECGS

58

0028

70

PD4

11

NC

23

0021

35

ECCl

47

W

59

VCC

71

ECC7

12

AO

24

D06

36

ECC2

48

CD

60

0029

72

Vss

MOTOROLA MEMORY DATA
3-159

AO-A9 ................ Address Inputs
DQO-DQ3l ......... Data InpuVOutput
ECCO-ECC7 .. Error Correction Data 110
CASO-CAS3 ... Column Address Strobe
PD1-PD4 ............ Presence Detect
RASG-RAS2 ...... Row Address Strobe
W................... ReadlWrite Input
CD . . . . . . . . . . .. Configuration Detection
VCC ................... Power (+ 5 V)
VSS ........................ Ground
NC .................... No Connection
All power supply and ground pins must be
connected lor proper operation 01 the device.

MCM40612-MCM40L512
t;

512K x 40 BLOCK DIAGRAM
OQ(}-D03

CAS

liAS

~OE

•

iN

iN

iN

1/03
AG-AB 1/04

iN

1101
1102
1103
AG-AB 1104

CAS
RAS
AG-AB

iN

VOl
V02
V03
1/04
008-0011

AG-AB

iN

VOl
1102
V03
1104

AG-AB

iN

CAS
RAS

~OE

iN

RAS
AG-AB

iN

iN

iN

iN

1101
1102
1103
AG-A8 1/04

VOl

iN

1/02
1103
AG-AB 1104

iN

VOl
V02
V03
AG-AB V04

iN

1101
1/02
1/03
1/04

CAS
RAS
AG-AB

1/01
1102
1/03

V04

iN

RAS
AG-AB

iN

AG-AB

OE~

iN

VOl
. V02
1/03
1/04

OE~
CAS
RAS

1102
1/03

V04

OE~
CAS

VOl

ECCG-ECC3

OE~

CAS
RAS
AG-AB

OE~

iN

ECC4-ECC7

CAS
RAS

iN

AG-AB

OQ26-DQ31

CAS

rOE

1104

1101
1102
1103
AG-AB 1/04

1102
1103
AG-AB 1104

liAS

rOE

AG-A8 1104

OE~
CAS
RAS

0024-0027

CAS
RAS

~OE

V03

VOl

CAS
RAS

~OE

1/03
oo2G-DQ23

CAS
RAS

~OE

1/01
1/02

OE~
CAS

0016-0019

VOl
1102

OE~
CAS
RAS

1/01

V02
V03
V04

OE~
CAS
RAS

0012-0015

CAS
RAS

~5E

1/02
1/03
V04

VOl
V02
V03
AG-AB 1104
1101
1102

CAS
RAS

~OE

VOl

OQ4-OO7

CAS
RAS

~OE

VOl
V02
V03
AG-AB V04

1

VOl
V02
V03
1/04

CAS
RAS
AG-AB

iN

I

I

I

AG-AB

Vcc

OE~

..

UG-U19
O.221'F (MIN)
VSS------------T
.......- - - - - - - - - -...... UG-U19

I

Presence Detect Pin Out
Pin Name

70ns

80ns

100ns

POl
P02
P03
P04

NC
VSS
VSS
NC

NC
VSS
NC
VSS

Ne
VSS
VSS
VSS

CD

VSS

VSS

VSS

MOTOROLA MEMORY DATA
3-160

MCM40512-MCM40L512

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-1 to+ 7

V

Vin, Vout

-1 to+ 7

V
mA

Power Supply Voltage
Voltage Relative to V SS
(For Any Pin Except VCC)
Data Output Current per DO Pin

lout

50

Power Dissipation

Po

6.15

W

Operating Temperature Range

TA

Oto + 70

Tsta

-25to + 125

°c
°c

Storage Temperature Range

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to these high-impedance circuits.

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time
could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70 o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

-

6.5

V

1

Logic Low Voltage, All Inputs

VIL

-1.0

-

0.8

V

1

Min

RECOMMENDED OPERATING CONDITIONS
Characteristic
VCC Power Supply Current

VCC Power Supply Current (Standby) (RAS

Symbol
MCM40512-70, tRC
MCM40512-80, tRC
MCM40512-10, tRC

= 130 ns
= 150 ns
= 180 ns

= CAS = VIH)

ICC2

= 130 ns
= 150 ns
= 180 ns
VCC Power Supply Current
MCM40512-70, tpc = 40 ns
During Fast Page Mode Cycle
MCM40512-80, tpc = 45 ns
MCM40512-1 0, tpc = 55 ns
VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V) MCM40512
VCC Power Supply Current
During RAS only Refresh Cycles

ICCI

MCM40512-70, tRC
MCM40512-80, tRC
MCM40512-10, tRC

ICC3

= 130 ns
= 150 ns
= 180 ns
VCC Power Supply Current ~ttery Backup Mode (tRC = 1251's; CAS = CAS
before RAS Cycling or 0.2V; W, DO, AO - A8 = VCC - 0.2V or 0.2V) tRAS = II's
MCM40512-70, tRC
MCM40512-80, tRC
MCM40512-10, tRC

ICC4

ICC5

ICC6

Output Leakage Current (CAS at Logic 1, VSS'; Vout'; Vccl

Notes

mA

2

40

mA

-

820
720
620

mA

2

-

-

mA

2,3

-

620
520
420

-

20
4

mA

-

mA

-

820
720
620

-

6.0

-

-

mA

ICC7

MCM40L512 only
Input Leakage Current (VSS'; Vin'; Vccl

Unit

820
720
620

-

MCM40L512
V CC Power Supply Current
During CAS Before RAS Refresh Cycle

Max

-

Ilkg(l)

-200

200

I'A

Ilkg(O)

-20

20

I'A

VOH

2.4

-

V

VOL

-

0.4

V

=- 5 mAl
Output Low Voltage (IOL = 4.2 mAl
Output High Voltage (lOH

NOTES:
1. All voltages referenced to V SS.
2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
3. Measured with one address transition per page mode cycle.

MOTOROLA MEMORY DATA
3-161

2

..

MCM40612- MCM40L512

CAPACITANCE (f = 1.0 MHz, T A = 25°C,

Vee = 5 V, Periodically Sampled Rather Than 100% Tested)

Characteristic

•

Symbol

Min

Max

Unit

Input Capacitance (AD-A8)

Cll

-

110

pF

1

Input Capacitance (W)

CI2

150

pF

1

Input Capacitance (RASO-RAS3)

CI3

45

pF

1

Input Capacitance (CASo-GAS3)

CI4

-

45

pF

1

24

pF

1

24

pF

1

110 Capacitance (000-0031)

COOl

110 Capacijance (ECCO-ECC7)

CD02

Notes

NOTE: 1. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 1 <1 t I <1 V.

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)
MCM40512-70

MCM40512-80

MCM40512-10

Standard

Altemate

Min

Max

Min

Min

Max

Unit

Notes

Random Read or Write Cycle Time

tRELREL

tRC

130

-

150

-

180

ns

5

Page Mode Cycle lime

tCELCEL

tpc

40

-

45

-

55

-

Access lime from RAS

tRELOV

tRAC

ns

25

ns

6,8

Access lime from Column Address

tAVOV

tAA

-

35

50

ns

6,9

Access lime from Precharge CAS

tCEHOV

tCPA

-

35

40

-

100

tCAC

-

80

tCELOV

-

70

Access lime from CAS

50

ns

6

CAS to Output in Low-Z

teELOX

teLZ

a

-

0

-

a

-

ns

.6

Output Buffer and Turn-Off Delay

tCEHOZ

toFF

a

20

a

20

a

20

ns

10

IT

tT

3

50

3

50

3

50

ns

tREHREL

tRP

50

-

60

-

70

10,000

80

10,000

100

10,000

ns

100,000

80

100,000

Symbol
Parameter

Transition lime (Rise and Fall)
RAS Precharge lime

20

Max

20
40

-

ns

ns

RAS Pulse Width

tRELREH

tRAS

70

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

70

100

100,000

ns

tRSH

20

-

20

-

25

ns

-

80

-

100

-

RAS Hold lime

tCELREH

6,7

CAS Hold Time

tRELCEH

teSH

70

CAS Pulse Width

tCELCEH

teAS

20

10,000

20

10,000

25

10,000

ns

RAS to CAS Delay lime

tRELCEL

tRCD

20

50

20

60

25

75

ns

11

RAS to Column Address Delay lime

tRELAV

tRAD

15

35

15

40

20

50.

ns

12

ns

NOTES:
(continued)
1.
VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2.
An initial pause of 200 I'S is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3.
The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4.
AC measurements IT = 5.0 ns.
5.
The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (O°C,; TA';
70'C) is assured.
6.
Measured with acurrent load equivalentto 2 TTL (-200 I'A, + 4 mAl loads and 100 pFwith the data outputtrip points setatVOH = 2.0 V and
VOL=0.8 V.
7.
Assumes that tRCD ,; tRCD (max).
8.
Assumes that tRCD ~ tRCD (max).
9.
Assumes that tRAD ;;, tRAD (max).
10.
tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11.
Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively to tCAC' .
12.
Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max), then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA

3-162

MCM40612-MCM40L512

READ AND WRITE CYCLES (Continued)
MCM40512·70

MCM40512·80

MCM40512·10

Standard

Symbol
Alternate

Min

Min

Max

Min

Max

Unit

CAS to RAS Precharge TIme

tCEHREL

tcRP

5

-

5

10

tCEHCEL

tcP

10

-

10

10

-

ns

CAS Precharge Time (Page Mode
Cyle Only)

-

-

0

-

0

-

ns

10

-

t5

-

ns

0

0

-

ns

20

-

ns

75

-

ns
ns

Parameter

Row Address Setup TIme

tAVREL

tASR

0

Row Address Hold TIme

tRELAX

tRAH

10

Column Address Setup TIme

tAVCEL

tASC

0

Column Address Hold TIme

tcELAX

tCAH

15

Column Address Hold TIme
Referenced to RAS

tRELAX

tAR

Column Address to RAS Lead TIme

tAVREH

Read Command Setup TIme

twHCEL

Max

Notes

•

ns

55

-

60

-

tRAL

35

-

40

-

50

-

tRCS

0

-

0

0

-

ns

-

0

-

0

-

ns

13
13

15

Read Command Hold TIme
Referenced to CAS

tCEHWX

tRCH

0

Read Command Hold TIme
Referenced to RAS

tREHWX

tRRH

0

-

0

-

0

-

ns

Write Command Hold TIme
Referenced 10 CAS

tCELWH

twCH

15

-

15

-

20

-

ns

Write Command Hold TIme
Referenced 10 RAS

tRELWH

twCR

55

-

60

-

75

-

ns

Wrile Command Pulse Width

twLWH

twP

15

-

15

-

20

-

ns

Write Command to RAS Lead TIme

twLREH

tRWL

20

20

-

25

Write Command to CAS Lead TIme

twLCEH

ICWL

20

-

20

-

25

-

ns

Data in Setup TIme

IDVCEL

tDS

0

-

0

-

0

-

ns

14

Dala in Hold TIme

tCELDX

IDH

15

-

15

-

20

-

ns

14

Data in Hold TIme Referenced to
RAS

tRELDX

IDHR

55

-

60

-

75

-

ns

Refresh Period

tRVRV

tRFSH

-

8
64

-

8
64

8
64

ms

-

MCM40512
MCM40L512

-

-

ns

Write Command Setup TIme

twLCEL

twcs

0

-

0

-

ns

tRELCEL

tcSR

10

-

0

CAS Setup TIme for CAS Before
RAS Refresh

10

-

10

-

ns

CAS Hold TIme for CAS Before RAS
Refresh

tRELCEH

tCHR

30

-

30

-

30

-

ns

CAS Precharge to CAS Active TIme

tREHCEL

tRPC

0

-

0

-

0

-

ns

-

40

-

50

-

ns

-

10

-

15

-

ns

CAS Precharge TIme for CAS
Before RAS Counter Test

tcEHCEL

tcPT

40

CAS Precharge TIme

tcEHCEL

tCPN

10

15

NOTES:
13.
Either tRRH or tRCH must be satisfied for a read cycle.
14.
These parameters are referenced to CAS leading edge in random write cycles.
15.
twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs ;>:twcs (min), the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughoullhe entire cycle. If this condition is not
satisifed, the condition of the data out (at access time) is indeterminate.
16. To avoid bus contention and potential damage to the module, RASO and RAS1 may notbe active low simultaneously. Similarly, RAS2 and
RAS3 may not be simu~aneously active low.

MOTOROLA MEMORY DATA
3-163

MCM40612-MCM40L512

READ CYCLE

•

RAS

VIHVIL -

CAS

VIHVIL -

ADDRESSES

VIHVIL -

W

VIH VIL -

VOHDO
(DATA OUT)
VOL -

MOTOROLA MEMORY DATA
3-164

MCM40612- MCM40L512

FAST PAGE MODE READ CYCLE
_ _ _..,. ........- - - - - - tRASP-------~
RAS

VIH VIL -

•

VIH CAS
VIL -

ADDRESSES

VIH VIL -

iii

VIH VIL -

DO VOH (DATA OUT)
VOL -

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

RAS

VIH VIL -

VIH CAS
VIL -

ADDRESSES

VIH VIL -

W

VIH VIL -

DO
(DATA IN)

VIH VIL -

MOTOROLA MEMORY DATA
3-166

MCM40612·MCM40L512

RAS ONLY REFRESH CYCLE
(Wand AS are Don't Care)

•

1....__----- t R C - - - - - - - + f
1.....1 - - - - - tRAS - - ' - ' ' ' - - - -...1

RAS

VIH

- --~

~--~

VIL -

VIH CAS

ADDRESSES

DO VOH (DATA OUT)
- - - - - - - - - HIGH·Z---------VOL -

CAS BEFORE RAS REFRESH CYCLE
(Wand AD to AS are Don't Care)

14------ t R C - - - - -. .
RAS

VIH vlL -

CAS
VIL -

DO VOH (DATAOUn
VOL -

-----J~
_ _
)--

HIGH·Z - - - - - - - -

MOTOROLA MEMORY DATA
3-166

MCM40612. MCM40L512

HIDDEN REFRESH CYCLE (READ)

----..,1+-- tRAS--'

VIH -

•

--ir--++----...,.

CAS

ADDRESSES

DO VOH (DATA OUT) VOL _

VALID DATA

--------t--i

HIDDEN REFRESH CYCLE (WRITE)
----~ ...- - tRAS

RAS

VIH VIL

-

VIH CAS
VIL

-

VIL

-

ADDRESSES

iN

DO
(DATA IN)

VIH VIL -

VIH VIL

-

..

..

tDHR

MOTOROLA MEMORY DATA
3-167

MCM40612·MCM40L512

~ BEFORE RAS REFRESH COUNTER TEST CYCLE

•

..

RAS

IRAS ------~
'RSH

VIH VIL -

VIH CAS

VIL -

ADDRESSES

VIH VIL -

READ CYCLE
DO VOH (DATA OUT)
VOL -

iii

VIH VIL -

WRITE CYCLE

iii

VIH VIL -

DO
(DATA IN)

VIH VIL -

MOTOROLA MEMORY DATA
3-168

MCM40512·MCM40L512

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substate generator pump to establish the
correct bias voltage. This is to be followed by a minimum of
eight active cycles of the row address strobe (clock) to initialize
the various dynamic nodes internal to the module. During an
extended inactive state of the module (greater than 4 milliseconds with device powered up), the wakeup sequence (8 active
cycles) will be necessary to assure proper device operation.

stay inactive for the minimum (tRP) time. The fonmer is for the
completion of the cycle in progress, and the latter is for the device internal circuitry to be precharged for the next active cycle.
Data out is not latched and is valid as long as the CAS clock
is active; the output will switch to the three-state mode when
the CAS clock goes inactive. To perform a read cycle, the write
(W) input must be held at the VIH level from the time the CAS
clock makes its active transition (tRCS) to the time when ittransitions into the inactive (tRCH) mode.
WRITE CYCLE

ADDRESSING THE RAM
The nine address bus pins on the device are time multiplexed with two separate 9-bit address fields that are strobed
althe beginning of the memory cycle by two clocks (active negative) called the row address strobe (RAS) and the column address strobe (CAS). A total of eighteen address bits will decode
one of the 524,288 word locations in the device. The column
address strobe follows the row address strobe by a specified
minimum and maximum time called tRCD, which is the row to
column strobe delay. This time interval is also referred to as the
multiplex window which gives flexibility to a system designer
to set up the external addresses into the RAM. These conditions have to be met for normal read or write cycles. This initial
portion of the cycle accomplishes the normal addreSSing of the
device. These are, however, other variations in addressing the
module: the refresh modes (RAS only refresh, CAS before
RAS refresh, hidden refresh), and another mode called page
mode which allows the user to column access all words within
a selected row. The refresh mode and page mode operations
are described in more detail in later sections.
READ CYCLE
A read cycle is referred to as a normal read cycle to differentiate it from a page mode read cycle, which is covered in a later
section.
The memory read cycle begins with the row addresses valid
and the RAS clock transitioning from VIH to the VIL level. The
CAS clock must also make a transition from V IH to the VIL level
at the specified tRCD timing limits when the column addresses
are latched. Both the RAS and CAS clocks trigger a sequence
of events which are controlled by several delayed internal
clocks. Also, these clocks are linked in such a manner that the
access time of the device is independent of the address multiplex window. The only stipulation is that the CAS clock must be
active before or at the tRCD maximum specification for an access (data valid) from the RAS clock edge to be guaranteed
(tRAC)' If the tRQll!11aximum condition is not met, the access
(tCAC) from the CAS clock active transition will determine read
access time. The external CAS Signal is ignored until an internal RAS signal is available. This gating feature on the CAS
clock will allow the external CAS signal to become active as
soon as the row address hold time (tRAH) specification has
been met and defines the tRCD minimum specification. The
time difference between tRCD minimum and tRCD maximum
can be used to absorb skew delays in switching the address
bus from the row to column addresses and in generating the
CAS clock.
Once the clocks have become active, they must stay active
for the minimum (tRAS) period for the RAS clock and the minimum (tCAS) period for the CAS clock. The RAS clock must

A write cycle is similar to a read cycle except that the write
(W) clock must go active (VIL level) at or before the CAS clock
goes active at a minimum twcs time. If the above condition is
met, then the cycle in progress is referred to as an early write
cycle. In an early write cycle, the write clock and the data in are
referenced to the active transition of the CAS clock edge.
There are two important parameters with respect to the write
cycle: the column strobe to write lead time (tCWL) and the row
strobe to write lead time (tRWL). These define the minimum
time that RAS and CAS clocks need to be active after the write
operation has started (W clock at VIL level).
PAGE-MODE CYCLES
Page mode operation allows fast successive data operations at all 512 column locations on a selected row. Page access (tCAC) is typically half the regular RAS clock access
(tRAC) on the Motorola 1 M dynamic RAM. Page mode operation consists of holding the RAS clock active while cycling the
CAS clock to access the column locations determined by the
1O-bit column address field.
The page cycle is always initiated with a row address being
provided and latched by the RAS clock, followed by the column
address and CAS clock. From the timing illustrated, the initial
cycle is a normal read or write cycle, that has been previously
described, followed by the shorter CAS cycles (tPC)' The CAS
cycle time (tpC) consists of the CAS clock active time (tCAS),
and CAS clock precharge time (tcp) and two tranSitions. In
practice, any combination of read and write cycles can be performed to suit a particular application.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Therefore, to retain the correct information, the module needs to be refreshed at least
once every 8 milliseconds. This is accomplished by sequentially cycling through the 512 row address locations every 8 milliseconds (Le., at least one row every 15.6 microseconds). A
normal read or write operation to the module will also refresh
all the words associated with the particular row(s} decoded.
RAS-Only Refresh
In this refresh method, the system must perform a
RAS-only cycle on 512 row addresses every 8 milliseconds.
The row addresses are latched in with the RAS clock, and the
associated internal row locations are refreshed. As the
heading implies, the CAS clock is not required and must be
inactive or at a VIH level.

MOTOROLA MEMORY DATA

3-169

•

MCM40612·MCM401.512

CAS Before RAS Refresh

..

test is performed with read and write operations. During this
test, the internal refresh counter generates the row address,
while the external address input supplies the column address.
The entire array is refreshed after 512 test cycles, as indicated
by the check data written in each row. See CAS before RAS
refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:

This refresh cycle is initiated when RAS falls, after CAS has
been low (by tCSR). This activates the internal refresh counter
which generates the row address to be refreshed. Externally
applied addresses are ignored during the automatic refresh
cycle. If the output buffer was off before the automatic refresh
cycle, the output will stay in the high-impedance state. If the
output was enabled by CAS in the previous cycle, the data out
will be maintained during the automatic refresh cycle as long
as CAS is held active (hidden refresh).
Hidden Refresh

1. Write "O"s into all memory cells (normal write mode).
2. Select a column address, and read "0" out of the cell by
performing CAS before RAS refresh counter test, reed
cycle. Repeat this operation 512 times.
3. Select a column address, and write "I" into the cell by
performing CAS before RAS refresh counter test, write
cycle. Repeat this operation 512 times.
4. Read "1"s (normal read mode), which were written at step
3.
5. Repeat steps 1 to 4 using complement data.

The hidden refresh method allows refresh cycles to be performed while maintaining valid data at the output pin. Hidden
refresh is performed by holding CAS at VIL and taking RAS
high and after a specified precharge period (tRP), executing a
CAS before RAS refresh cycle. (See Figure 1.)
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of the device can be tested with
a CAS before RAS refresh counter test. This refresh counter

REFRESH
CYCLE

DO -

HIGH·Z

-++4- REFRESH
CYCLE

VALID DATA·OUT

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory

prefiX~

40512 or 40L512

I

Part N u m b e r - - - - - - - - - - - - I

x

XX

T T_

Speed(70=70ns,BO=BOns,10=100ns)

~ Pac~e

Full Part Numbers - MCM40512S70
MCM40512SBO
MCM40512S10
MCM40L512S70
MCM40L512SBO
MCM40L512S10

MCM40512SG70
MCM40512SGBO
MCM40512SG10
MCM40L512SG70
MCM40L512SGBO
MCM40L512SG10

MOTOROLA MEMORY DATA

3-170

(S = SIMM, SG = Gold Pad SIMM)

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - -

TECHNICAL DATA

MCM81 000

1Mx8 Bit Dynamic Random

MCM8L1000

Access Module

•

The MCM81000 and MCM8Ll000 are 8M dynamic random access memory
(DRAM) modules organized as 1,048,576 x 8 bits. The modules are 30-lead
single-in-line memory modules (SIMM) or 30-pin single-in-line packages (SIP)
consisting of eight MCM511000A DRAMs housed in a 20/26 J-Iead small outline
package (SOJ) and mounted on a substrate along with a 0.22 IlF (min) decoupling capacitor mounted under each DRAM. The MCM511000A is a 1.011
CMOS high speed, dynamic random access memory organized as 1,048,576
one-bit words and fabricated with CMOS Silicon-gate process technology.
•
•
•
•
•
•
•
•

•
•
•

•

•

•
•
•

Three-State Data Output
Early-Write Common 1/0 Capability
Fast Page Mode Capability
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
512 Cycle Refresh:
MCM81 000 = 8 ms (Max)
MCM8L 1000 = 64 ms (Max)
Consists of Eight 1M DRAMs and Eight 0.221lF (Min) Decoupling Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access Time (tRAC)
MCM81 000-70 = 70 ns (Max)
MCM81 000-80 = 80 ns (Max)
MCM81 000-1 0 = 100 ns (Max)
Low Active Power Dissipation:
MCM81 000-70 = 3.6 W (Max)
MCM81 000-80 = 3.1 W (Max)
MCM81000-10 = 2.7 W (Max)
Low Standby Power Dissipation:
TTL Levels = 88 mW (Max)
CMOS Levels (MCM81 000) = 45 mW (Max)
(MCM8L1000) = 9 mW (Max)
CAS Control for Eight Common 1/0 Lines
Available in Edge Connector (MCM81 OOOS) or Two-Layer PCB Edge Connector
(MCM81000AS)
Available in Pin Connector (MCM81 OOOL) or Double-Sided Low Height Pin
Connector (MCM81000LH)

S, AS PACKAGE

SIMMMODULE
CASE 839

30-PIN
SINGLE-IN-LiNE PACKAGE
(TOP VIEW, MCM81000S/81000AS)

-.Jo
VCC (I)
CAS (2)
DQO (3)
AD (4)
At (5)
DOl (6)
A2 (7)
AS

(8)

Vss (9)
002 (10)
A4 (II)
AS (12)
DQ3 (13)
AS (14
A7 (15
DQ4 (16)
AS (17)
AS (18)
NC (19)
DQ§ (20)
W (21 )
Vss (22)
006(23)
NC (24)
DQ7(25)

!~I

.ll!«26)

RAS (27)
NC (28)
NC (29)
Vee (30)

PIN NAMES
AD-A9 ..................... Address Inputs
DOD-DO? ... . . . . . . . . . . .. Data InpuVOutput
CAS ............... Column Address Strobe
RAS .................. Row Address Strobe
W ....................... ReadlWrite Input
VCC ........................ Power (+5 V)
VSS .............................. Ground
NC ........................ No Connection

MOTOROLA MEMORY DATA

3-171

0

MCM81ooo-MCM8L1000

FUNCTIONAL BLOCK DIAGRAM

DOO

I
r-"\
~ ~

•

roo- ' -

r-+- i--

-

oJ

D

DQ4

I

RAS

roo-

~

CAS

rI-

I-- CAS
f-W

W

r-

-HDOl

I

:i\
.....
~~r--

~

-

DOS

I

ti\:

ACl-A9
RAS

~

CAS

~I-

Vi

~

r-r-

~

I

~
..... ~
~-

..... 1--

-

DOS

I

ACJ-A9
RAS

~

CAS

..... 1-

Vi

~

r-I-

~
~

I

~
..... ~
~..... r--

ACl-A9

D07

I

~

ACJ-A9
RAS

-

oj

ACJ-A9
RAS

-II--

oj

D

D

f- CAS
f-Vi

-II---D03

RAS

-II--

oj

D

oj

D
ACl-AS

f- CAS
I--Vi

-II---DQ2

RAS

-II--

oJ

D

oj

D

~ ACl-AS

ACl-A9

~

-

~r-

CAS

~ r-r-

-W

~~

~

D

oj

ACl-AS

RAS

I-- CAS
r-W

-II-

RAS
CAS

Vi
VCC
VSS

MOTOROLA MEMORY DATA
3-172

MCM81000-MCM8L1000

ABSOLUTE MAXIMUM RATING (See Note)
Rating

Symbol

Value

VCC

-1 to +7

V

Vin, Vout

-1 to +7

V
mA

Power Supply Voltage
Voltage Relative to VSS for Any Pin Except VCC

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit.

Unit

Data Out Current per DO Pin

lout

50

Power Dissipation

Po

4.8

W

Operating Temperature Range

TA

Oto+70

'c

Storage Temperature Range
-25 to +125
'c
Tsto
NOTE: Permanent deVIce damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higherthan recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70'e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0
6.5

V

1

0.8

V

1

Max

Unit

Notes

mA

2

Logic High Voltage, All Inputs

VIH

2.4

Logic Low Voltage, All Inpuls

Vil

-1.0

-

Symbol

Min

DC CHARACTERISTICS
Characteristic
VCC Power Supply Current
MCM81000-70, tRC = 130 ns
MCM81 000-80, tRC = 150 ns
MCM81 000-1 0, tRC = 180 ns

ICCI

-

VCC Power Supply Current (Standby) (RAS=CAS=VIH)

ICC2

V CC Power Supply Current During RAS Only Refresh Cycles
MCM81 000-70, tRC = 130 ns
MCM81 000-80, tRC = 150 ns
MCM81 000-10, tRC = 180 ns

Ice3

VCC Power Supply Current During Fast Page Mode Cycle
MCM81 000-70, tpc = 40 ns
MCM81 000-80, tpc = 45 ns
MCM81 000-10, tpc = 55 ns

ICC4

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V)

MCM81 000
MCM8L1000

-

ICC5

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM81 000-70, tRC = 130 ns
MCM81 000-80, tRC = 150 ns
MCM81 000-1 0, tRC = 180 ns

ICC6

VCC Power Supply Current, Baltery Backup Mode-MCM8L1000 and
MCM8L1OOOA Only
(tRAC =J..2511S; tRAS = 1 11S; CAS = CAS Before RAS Cycle or 0.2 V;
AD-A9, W, DO = VCC-{).2 V or 0.2 V)

ICC7

-

640
560
480
16

mA
mA

2

mA

2

640
560
480
480
400
320
8
1.6

mA
mA

640
560
480
2.4

mA

Input Leakage Current (0 VSS'; Vin S VCC)

11kg(1)

-ao

80

I1A

Output Leakage Current (CAS at Logic 1, VSS S Vout ,; VCC)

Ilka{O)

-20

20

I1A

Output High Voltage (IOH = -5 mAl

VOH

2.4

-

V

Output Low Voltage (IOl = 4.2 mAl

Val

0.4

V

-

CAPACITANCE (f = 1.0 MHz, TA = 25'C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

AD-A9, W, CAS, RAS

InpullOutput Capacitance

DOD-D07

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and oulputloading; maximum current is measured at the fastest cycle rate with the output open.
3. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I/;.\I/N.

MOTOROLA MEMORY DATA

3-173

2

•

MCM81ooo.MCM8L1000

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA = 0 to 70o e, Unless Otherwise Noted)

READ AND WRITE CYCLES (See Notes 1, 2 3, and 4)

•

MCM81000-70

MCM81000-a0

MCM81000-10

Standard

Alternate

Min

Max

Min

Max

Min

Max

Random Read or Write Cycle Time

tRELREL

tRC

130

-

150

teELCEL

tpc

40

-

45

Access Time from RAS

tRELOV'

tRAC

-

70

.-

-

180

Page Mode Cycle Time
Access Time from CAS

tCELQV

teAC

-

20

20

Access Time from Column Address

tAVOV

tAA

35

-

40

Access Time from Precharge CAS

tCEHOV

tCPA

-

-

35

-

40

Parameter

Symbol

-

-

-

Notes

-

ns

5

100

ns

6,7

25

ns

6,8

50

ns

6,9

50

ns

6

-

ns

6
10

ns

CAS to Output in Low-Z

teELOX

teLZ

0

Output Buffer and Turn-Off Delay

tCEHOZ

tOFF

0

20

0

20

0

20

ns

IT

IT

3

50

3

50

3

50

ns

Transition Time (Rise and Fall)

0

80

55

Unit

0

RAS Precharge Time

tREHREL

tRP

50

-

60

70

-

ns

RAS Pulse Width

tRELREH

tRAS

70

10,000

80

10,000

100

10,000

ns

RAS Pulse Width (Fast Page
Mode)

tRELREH

tRASP

70

100,000

80

100,000

100

100,000

ns

25

-

RAS Hold Time

tCELREH

tRSH

20

teSH

70

80

-

100

-

ns

tRELCEH

-

20

CAS Hold Time
CAS Pulse Width

tCELCEH

teAS

20

10,000

20

10,000

25

10,000

ns

RAS to CAS Delay Time

tRELCEL

tRCD

20

50

20

60

25

75

ns

11

tRELAV

tRAD

15

35

15

40

20

50

ns

12

CAS to RAS Precharge Time

tCEHREL

teRP

5

-

5

teEHCEL

tep

10

-

10

-

10

-

ns

CAS Precharge lime (Page Mode
Cycle Only)

RAS to Column Address Delay
Time

Row Address Setup Time

tAVREL

tASR

0

Row Address Hold lime

tRELAX

tRAH

10

Column Address Setup lime

tAVCEL

tASC

0

Column Address Hold Time

tCELAX

teAH

15

Column Address Hold Time
Referenced to RAS

tRELAX

tAR

55

-

Column Address to RAS Lead
lime

tAVREH

tRAL

35

-

5

60

-

75

40

-

50

0
10
0
15

0
15
0
20

ns

ns
ns
ns
ns
ns
ns
ns

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 I1S is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specifications for tRC (min) and tRWC (min) are usad only to indicate cycle time at which proper operation over the full temperature
range (O°C :;; TA :;; 70°C) is assured.
6. Measured with a current load equivalent to 2 TTL (-200 ~, +4 rnA) loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD:;; tRCD (max).
8. Assumes that tRCD ~ tRCD (max).
9. Assumes that tRAD ~ tRAD (max).
10. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specnled as a reference point only; if tRAD is
greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA.

MOTOROLA MEMORY DATA
3-174

MCM81ooo- MCM8L1000

READ AND WRITE CYCLES (Continued)
Symbol
Parameter

Standard

MCM81 000-80

MCM81 000-1 0

Alternate

MCM81 000-70
Min

Max

Min

Max

Min

Max

Unit

Notes

Read Command Setup Time

twHCEL

tRCS

0

tRCH

0

0

0

-

ns

IcEHWX

-

0

Read Command Hold Time
Referenced to CAS

-

0

ns

13

Read Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

-

0

-

0

-

ns

13

Write Command Hold Time
Referenced to CAS

IcELWH

twCH

15

-

15

-

20

-

ns

Write Command Hold Time
Referenced to RAS

tRELWH

twCR

55

-

60

-

75

-

ns

15

Write Command Pulse Width

twLWH

twP

15

ns

tRWL

20

20

-

-

twLREH

-

20

Write Command to RAS Lead Time

25

ns

Write Command to CAS Lead Time

twLCEH

tCWL

20

-

20

-

25

Data in Setup Time

tOVCEL

tos

0

-

0

-

0

Data in Hold Time

tCELOX

tOH

15

-

15

-

20

Data in Hold Time Referenced to
RAS

tRELOX

tOHR

55

-

60

-

75

-

Refresh Period

tRVRV

tRFSH

-

8

-

8
64

ms

MCM81 000
MCM8Ll000

8
64

-

-

64

Write Command Setup Time

twLCEL

twcs

0

CAS Setup Time for CAS Before
RASRefresh

tRELCEL

tCSR

10

-

10

-

CAS Hold Time for CAS Before
RAS Refresh

tRELCEH

tCHR

30

-

30

CAS Precharge to CAS Active
Time

tREHCEL

tRPC

0

-

CAS Precharge Time for CAS
Before RAS Counter Test

IcEHCEL

tCPT

40

-

ns
ns

14,15

ns

14,15

ns

0

-

ns

10

-

ns

-

30

-

ns

0

-

0

-

ns

40

-

50

-

ns

0

-

-

-

15,16

CAS Precharge Time
10
10
15
ns
tcEHCEL
tcPN
NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in random write cycles.
15. Early write only (twcs 2: twcs (min)).
16. twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs 2: twcs (min), the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is
not satisfied, the condition of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
3-175

•

MCM81000- MCM8L1000

READ CYCLE

•
ADDRESSES VIHVIL -

W VIHVIL - t......:!."--'''--'~4-.>4-.>4-.>'-'''-''''-'(.

DOO-DO? VOH - _ _ _ _ _ __

(DATA OUT) VOL -

EARLY WRITE CYCLE
~-----------tRC-----------~

~-------tRAS -------~

1 4 - - - - tRCD ----0\+--

CAS VIHVIL -

ADDRESSES VIHVIL -

DOD-DO?
(DATA IN)

MOTOROLA MEMORY DATA
3-176

Jc---""-----:i.

MCM81ooo. MCM8L1000

FAST PAGE MODE READ CYCLE

iii

VIHVIL-

VOHDOD-D07
(DATA OUT) VOL -

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

iii

VIHVIL-

~~~~~~~~--r--r-+~~--;--f--~~~-r~--~~~~~~~~

DOD-D07 V IH (DATA IN) VIL -

J-~~~~~;v l''-----------:,

MOTOROLA MEMORY DATA
3-1n

MCM81ooo. MCM8L1000

RAS ONLY REFRESH CYCLE
(Wand AS are Don'l Care)
~------------------tRC------------------------~

..

DOD-DO? VOH- - - - - - - - - - - - - - - HIGHZ
(DATA OUT) VOL -

CAS BEFORE RAS REFRESH CYCLE
(Wand AD to A9 are Don't care)
~----------------tRC--------------~

..IC""-------:~---------

CAS VIHVIL- ___- - J

tRAS-----------i ...il:------:i.

tCHR

-------:L!>-__________

DOo-OO? VOH(DATA OUT) VOL - _ _ _ _ __

HIGHZ - - - - - - - - - - -

MOTOROLA MEMORY DATA
3-178

MCM81000-MCM8L1000

HIDDEN REFRESH CYCLE (READ)

•
ADDRESSES VV IH IL -

W VIHVIL -

DCO-DO? VOH(DATAOUTI VOL _

....lL....lL...:L+~~..:Y

----------+-<1

HIDDEN REFRESH CYCLE (WRITE)

ADDRESSES VV IH IL -

iN

VIHVIL- ~~~~~~~~-~r-----~~~~~~~~~~~~~~~~~~~

DOD-DO? VIH -

~",,*"""""" Jc-------~L "'~~~~~~~-,.,:'"''"''"''"''"''"''"'"

(DATA IN) VIL -

--"'-"'-"-"--"-"->1 1'-_ _ _ _ _--'1

MOTOROLA MEMORY DATA
3-179

MCM81OOO-MCM8L1000

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

•
I

ADDRESSES VIH VIL -

-'-''''--'......,L....l.~'-'''-''...lL~~~~ 1'~--r-,------.;i1 ,,~~~~~-?'-""-;>L....;"'--'......,'-

READ CYCLE
DQO-DQ7 VOH (DATA OUT) VOL - - - - - - - - -

iN VIHVIL -

.<....;'"-'.......'-"--"'-"'-"--"'-......~",

WRITE CYCLE

iN

VIH-'VIL -

DQO-DQ7 VIH(DATA IN) VIL -

MOTOROLA MEMORY DATA

3-180

MCM81000-MCM8L1000

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the RAM. During an extended inactive
state (greater than 16 milliseconds with the device powered
up), a wake up sequence of eight active cycles is necessary to
ensure proper operation.
ADDRESSING THE RAM
The eleven address pins on the module are time multiplexed
at the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 1O-bit address fields. A total of twenty address bits, ten
rows and ten columns, will decode one of the 1,048,576 byte
locations in the module. RAS active transition is followed by
CAS active transition (active = V'L, tBQD minimum) for all read
or write cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system
designer flexibility in setting up the external addresses into the
RAM.
_
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are two other variations in addressing the 1M RAM:
RAS only refresh cycle, and CAS before RAS refresh
cycle. Both are discussed in separate sections that follow.
READ CYCLE
The DRAM may be read with either the "normal" random
read cycle or the page mode read cycle. The normal read cycle
is outlined here, while the page mode is discussed in a separate section.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired byte location. The write (Vii) input level must be
high (VIH), tRCS (minimum) before the CAS active transition,
to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex
window. However, CAS must be active before or at tRCD maximum to guarantee valid data out (DO) at tRAC (access time
from RAS active tranSition). II the tRCD maximum is exceeded, read access time is determined by the CAS clock active
transition (tCAC)'
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. Vii must remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data at that bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitry for the next active
cycle. Data out (DO) is valid, but not latched, as long as the

CAS clock is active. When the CAS clock transitions to inactive, the output will switch to High Z.
WRITE CYCLE
The user can write to the module with either of two cycles:
early write or page mode early write. Early write mode is discussed here, while the page mode write operation is covered
in another section.
A write cycle begins as described in ADDRES~ING THE
RAM. Write mode is enabled by the transition of W to active
(VIL)' Minimum active time tRAS and tCAS, and precharge
time tRP apply to write mode, as in the r~d mode.
An early write cycle is characterized by W active transition at
minimum time twcs before CAS active transition~ta in
(DO) is referenced to CAS in an early write cycle. RAS and
CAS clocks must stay active for tRWL and tCWL, respectively,
after the start olthe early write operation to complete the cycle.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
2048 column locations on a selected row of the 1M dynamic
RAM. Read access time in page mode (tCAC) is typically hall
the regular RAS clock access time, tRAC' Page mode operation consists of keeping RAS active while toggling CAS between VIH and ~The row is latched by RAS active transition, while each CAS active transition allows selection of a new
column location on the row.
A page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for
minimum of tcp, while RAS remains low (VIU, The second
CAS active transition while RAS is low initiates the first page
mode cycle (tpC)' Either a read or write operation can be performed in a page mode cycle, subject to the same conditions
as in normal operation (previously described). These operations can be intermixed in consecutive page mode cycles and
performed in any order. The maximum number of consecutive
page mode cycles is limited by tRASP. Page mode operation
is ended when RAS transitions to inactive, coincident with or
following CAS inactive transition.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge degrades with
time and temperature, thus each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bytes in
the MCM81 000 require refresh every 8 milliseconds, while refresh time for the MCM8L1000 is 64 milliseconds.
Refresh is accomplished by cycling through the 512 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM81000, and 124.8 microseconds
for the MCM8L1000. Burst refresh, a refresh of all 512 rows
consecutively, must be performed every 8 milliseconds on the
MCM81 000 and 64 milliseconds on the MCM8L1000.
A normal read, write, or read-write operation to the RAM will
refresh all the bytes associated with the particular row decoded. Three other methods of refresh, RAS-only refresh,
CAS before RAS refresh, and hidden refresh are available
on this device for greater system flexibility.

MOTOROLA MEMORY DATA
3-181

•

MCM81ooo. MCM8L1000

RAS-only Refresh
RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(VI H) throughout the cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.

•

CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order actives an internal refresh counterthatgenerates the row address to be refreshed. External address lines are ignored during the automatic refresh cycle. The
output buffer remains at the same state it was in during the previous cycle (hidden refresh).
Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). Wis subject to the same conditions
with respect to RAS active transition (to prevent test mode
cycle) as in CAS before RAS refresh.

CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CAS before RAS refresh counter test. This refresh counter test is performed with read and write operations. During this
test, the Internal refresh counter generates the row address,
while the external address supplies the column address. The
entire array is refreshed after 512 test cycles, as indicated by
the check data written in each row. See CAS before RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as follows:
1. Write "O"s into all memory cells with normal write mode.
2. Select a column address, and read "0" out of the cell by
performing CAS before RAS refresh counter test,
read cycle. Repeat this operation 512 times.
3. Select a column address and write "1" into the cell by
performing the CAS before RAS refresh counter test,
write cycle. Repeat this operation 512 times.
4. Read "1"5 (normal read mode), which were written at
step3.
5. Repeat steps 1 to 4 using complement data.

REFRESH CYCLE

OQO-OQ7 -HIGH z-t----{

REFRESH CYCLE

VALID DATA·OUT

Figure 1. Hidden Refresh Cycle

r"

ORDERING INFORMATION
(Order by Full Part Number)

Motorola Memory Prefix
Part Number

1M
_ _ _M_C_
_ _8_10_0....

Speed (70 -70 ns, 80 - 80 ns, 10 - 100 ns
Package (L - SIP, LH - Low Height SIP, S - 4-Layer SIMM,
AS - 2-Layer SIMM)

Full Part Numbers- MCM81000AS70
MCM81000AS80
MCM81000AS10
MCM8L1000AS70
MCM8L1OOOASBO
MCM8L1 OOOASI 0

MCM81000S70
MCM81000S80
MCM81000SI0

MCM81000L70
MCM81000L80
MCM81OOOLI0

MCM81000LH70
MCM81000LH80
MCM81OOOLHI0

MCM8L1000S70
MCM8L1000S80
MCM8L1 OOOSI 0

MCM8L1000L70
MCM8L1000L80
MCM8L1OOOL 10

MCM8L1000LH70
MCM8L1000LH80
MCMBL1OOOLHI 0

MOTOROLA MEMORY DATA
3-182

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM81430
MCM8L1430

Advance Information
1Mx8 Bit Dynamic Random
Access Module
The MCM81430 and MCM8L1430 are 8M dynamic random access memory
(DRAM) modules organized as 1,048,576 x 8 bits. The modules are 30-lead
single-in-line memory modules (SIMM) consisting of two MCM54400AN DRAMs
housed in a 20/26 J-Iead small outline package (SOJ) and mounted on a substrate along with a 0.22 IiF (min) decoupling capacitor mounted adjacent to each
DRAM. The MCM54400AN is a CMOS high speed, dynamic random access
memory organized as 1,048,576 four-bit words and fabricated with CMOS
silicon-gate process technology.
•
•
•
•
•
•
•
•

•
•
•

•

•

•
•

Three-State Data Output
Early-Write Common 110 Capability
Fast Page Mode Capability
TIL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh:
MCM81430 = 16 ms (Max)
MCM8L1430 = 128 ms (Max)
ConSists of Two 4M DRAMs and Two 0.221iF (Min) Decoupling Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access Time (tRAC)
MCM81430-60 = 60 ns (Max)
MCM81430-70 = 70 ns (Max)
MCM8143()"80 = 80 ns (Max)
MCM81430-10 = 100 ns (Max)
Low Active Power Dissipation:
MCM81430-60 = 1.32 W (Max)
MCM81430-70 = 1.10 W (Max)
MCM81430-80 = 0.94 W (Max)
MCM81430-10 = 0.83 W (Max)
Low Standby Power Dissipation:
TIL Levels = 22 mW (Max)
CMOS Levels (MCM81430) = 11 mW (Max)
(MCM8Ll430) = 2.2 mW (Max)
CAS Control for Eight Common 110 Lines
Available in Edge Connector (MCM81430S)

•
SPACKAGE
SIMMMODULE
CASE 839A

30-PIN
SINGLE-IN-LINE PACKAGE
(TOP VIEW, MCM81430S18L1430S)

0
vee (1)
CAS (2)
DQO (3)
AO (4)
Al (5)
DOl (6)
A2 (7)
A3 (8)
Vss (9)
D02 (10)
A4 (11)
A5 (12)
D03 (13)
AS (14)
A7 (15)
D04 (16)
AS (17)
A9 (18)
NC (19)
o~ (20)
W (21)
Vss (22)
oQ6 (23)
NC (24)
oQ7 (25)
NC (26)
RAS (27)
NC (28)
NC (29)
Vee (30)

PIN NAMES

0

D
D
0

0

AO....A9 ..................... Address Inputs
DQ()....DQ7 ............... Data InpuVOutput
CAS ....•.......... Column Address Strobe
RAS .................. Row Address Strobe
W ....................... ReadIWrile Input
VCC ........................ Power (+5 V)
VSS ..•........................... Ground
NC ........................ No Connection

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA

3-183

MCM8143O-MCM8L1430

FUNCTIONAL BLOCK DIAGRAM

DOll-003

~

I

--

DO
AQ-AS

RAS

CAS

r--

iN

;-

b~

D04--DQ7

~

IV"

DO

AQ-AS

RAS
CAS

iN

Hf-<

Ao-A9
VCC
VSS

ABSOLUTE MAXIMUM RATING (See Note)
Rating
Power Supply Voltage

Symbol

Value

Unit
V

VCC

-t to +7

Vin. Vout

-1 to +7

V

Data Out Current per DQ Pin

lout

50

mA

Power Dissipation

PD

1.4

W

Operating Temperature Range

TA

o to +70

·C

Voltage Relative to VSS for Any Pin Except VCC

·C
Storage Temperature Range
-25 to +125
Tsta
NOTE: Permanent deVIce damage may occur If ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

MOTOROLA MEMORY DATA
3-184

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however.
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit.

MCM81430-MCM8L1430

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

-

S.5

V

1

Logic Low Voltage, All Inpuls

VIL

-1.0

-

O.B

V

1

Symbol

Min

Max

Unit

Notes

mA

2

DC CHARACTERISTICS
Characteristic
VCC Power Supply Current
MCMBI430-S0, tRC = 110 ns
MCMBI430-70, tRC = 130 ns
MCMBI430-BO, tRC = 150 ns
MCMBI430-10, tRC = lBO ns

ICC 1

VCO Power Supply Current (Standby) (RAS;'CAS=VIH)

ICC2

Vcq Power Supply Current During RAS Only Refresh Cycles
iMCMBI430-S0, tRC = 110 ns
iMCMBI430-70, tRC = 130 ns
MCM81430-80, tRC = 150 ns
: MCM81430-10, tRC = lBO ns

ICC3

vct Power Supply Current During Fast Page Mode Cycle
MCM81430-S0, tpc = 45 ns
MCM81430-70, tpc = 45 ns
MCM81430-80, tpc = 50 ns
MCM81430-10, tpc = 60 ns

ICC4

-

240
200
170
150

-

4

-

240
200
170
150

-

140
140
120
110

-

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V)

MCM81430
MCM8Ll430

-

Iccs

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM81430-S0, tRC = 110 ns
MCMB1430-70, tRC = 130 ns
MCM81430-80, tRC = 150 ns
MCM81430-10, tRC = 180 ns

ICCS

VCC Power Supply Current, Batte~ck~ode-MCM81430 Only
(tRAC =J.25 J1S; tRAS = 1 liS; CAS = CAS Before RAS Cycle or 0.2 V;
AD-A9, W, DO = VCc;-{l.2 V or 0.2 V)

ICC7

2
0.4

mA
mA

2

mA

2,3

rnA
rnA

2

2,4

240
200
170
150

-

O.S

rnA

llA
llA

Input Leakage Current (0 VSS S Vin S VCC)

Ilkg(l)

-20

20

Output Leakage Current (CAS at Logic 1, VSS S Vout S VCC)

Ilka(O)

-10

10

Output High Voltage (IOH = -5 mAl

VOH

2.4

Output Low Voltage (IOl = 4.2 mAl

VOL

-

0.4

V

Symbol

Max

Unit

Cln

24

pF

5

CliO

17

pF

5

-

V

CAPACITANCE (f = 1.0 MHz, TA = 25°C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

AD-A9, W, CAS, RAS

InpuVOutput Capacitance

DOD-D07

Notes

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
3. Column address can be changed once or less while RAS = VIL and CAS = VIH.
4. tRAS (max) = lJ1S is only applied to refresh of battery backup. tRAS (max) = lOllS is applied to functional operating.
5. Capacitance measured with a Boonton Meter or effective capaCitance calculated from the equation: C = IdVtN.

MOTOROLA MEMORY DATA
3-185

MCM81430-MCM8L1430

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70 0 e, Unless Otherwise Noted)

READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)

•

Parameter

Symbol

8143D-l 0

81430-60
8LI430-S0

81430-70
8LI430-70

81430-80
8L143D-80

8L1430-10

Unit

Notes

-

ns

5

-

100

ns

6,7

-

25

ns

6,8

-

50

ns

6,9

45

-

55

ns

6

0

-

0

-

ns

6

0

20

0

20

ns

10

Sid

Aft

Min

Max

Min

Max

Min

Max

Min

Max

Random Read or Write Cycle Time

tRELREL

tRC

110
45

45

50

-

180

tpc

-

150

tCELCEL

-

130

Fast Page Mode Cycle Time

60

Access Time from RAS

tRELQV

tRAC

-

60

-

70

-

80

Access Time from CAS

tCELQV

teAC

-

20

-

20

-

20

Access Time from Column Address

tAVQV

tAA

30

-

40

tCEHQV

tCPA

40

-

35

Access Time from Precharge CAS

-

40

-

CAS to Output in Low-Z

tCELQX

tell

0

-

0

-

Output Buffer and Turn-Off Delay

tCEHQZ

tOFF

0

20

0

20

ns

IT

tT

3

50

3

50

3

50

3

50

ns

RAS Precharge Time

tREHREL

tRP

40

-

50

-

60

-

70

-

ns

RAS Pulse Width

tRELREH

tRAS

60

10k

70

10 k

80

10k

100

10k

ns

RAS Pulse Width (Fast Page
Mode)

tRELREH

tRASP

60

200k

70

200k

80

200k

100

200k

ns

20

-

25

80

-

100

ns
ns

Transition Time (Rise and Fall)

RAS Hold Time

tCELREH

tRSH

20

-

20

CAS Hold Time

tRELCEH

tCSH

60

-

70

CAS Precharge to RAS Hold Time

teEHREH

tRHCP

40

-

40

-

45

-

55

-

CAS Pulse Width

tCELCEH

teAS

20

10 k

20

10 k

20

10k

25

10 k

RAS to CAS Delay Time

tRELCEL

tRCD

20

40

20

50

20

60

25

75

ns

11

RAS 10 Column Address Delay
Time

tRELAV

IRAD

.15

30

15

35

15

40

20

50

ns

12

CAS to RAS Precharge Time

teEHREL

teRP

5

-

5

-

5

-

10

-

ns

CAS Precharge Time

tCEHCEL

tcp

10

-

10

-

10

-

10

ns

Row Address Setup Time

tAVREL

tASR

0

-

0

0

-

0

Row Address Hold Time

tRELAX

tRAH

10

10

10

-

15

-

ns

Column Address Selup Time

tAVCEL

IASC

0

0

-

0

teAH

15

15

-

15

Column Address 10 RAS Lead
Time

tAVREH

tRAL

30

35

-

40

50

-

ns

teELAX

-

0

Column Address Hold Time

-

-

-

Read Command Setup Time

!wHCEl

tRCS

0

-

0

-

0

-

0

-

ns
(continued)

20

ns
ns

ns

ns
ns

NOTES:
1. V,H min and V,L max are reference levels for measuring timing of input Signals. Transition times are measured between VIH and VIL'
2. An inilial pause of 200 ~ is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between V,H and VII': (or between VIL and V, H) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specification for IRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (O°C ,; TA ,;
70'C) is assured.
6. Measured with a current load equivalentto 2 TTL (-200 11A. +4 mAl loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD ,; tRCD (max).
8. Assumes that tRCD " tRCD (max).
9. Assumes that tRAD " tRAD (max).
10. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by teAC.
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max) limit, then access time is controlled exclusively by tM'

MOTOROLA MEMORY DATA
3-186

MCM8143O-MCM8L1430

READ AND WRITE CYCLES (Continued)

Parameter

Symbol

81430-60
8L1430-60

81430-70
8L1430-70

81430-80
8L1430-80

81430-10
8L1430-10

Min

Min

Min

Unit

Notes

ns

13

ns

13

25

-

0

-

ns

14

20

-

ns

14

-

16
128

ms

0

ns

15

ns

15

ns

15

ns

15

ns

15

10

-

10

-

ns

Std

Alt

Min

Read Command Hold Time
Referenced to CAS

tcEHWX

tRCH

0

-

0

-

0

-

0

Read Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

0

-

0

tCELWH

twCH

10

15

-

15

Write Command Pulse Width

twLWH

twP
tRWL

15

20

20

-

20

-

0

Write Command Hold Time
Referenced to CAS

-

10

Max

Max

15

Write Command to RAS Lead Time

twLREH

Write Command to CAS Lead Time

twLCEH

-

20

-

20

tDVCEL

tcWL
tDS

20

Data in Setup TIme

0

0

tcELDX

tDH

15

tRVRV

tRFSH

-

-

0

Data in Hold Time

-

Write Command Setup Time

twLCEL

twcs

0

CAS to Write Delay

tcELWL

50

RAS to Write Delay

tRELWL

tcWD
tRWD

-

90

-

100

Column Address to Write Delay
Time

tAVWL

tAWD

60

65

CAS Precharge to Write Delay
Time (Page Mode)

tcEHWL

tcPWD

70

CAS Setup Time for CAS Before
RAS Refresh

tRELCEL

tcSR

5

CAS Hold Time for CAS Before
RAS Refresh

tRELCEH

tCHR

15

RAS Precharge to CAS Active
Time

tREHCEL

tRPC

0

CAS Precharge Time for CAS
Before RAS Counter Time

tcEHCEL

tCPT

30

-

Write Command Setup Time (Test
Mode)

twLREL

tWTS

10

Write Command Hold Time (Test
Mode)

tRELWH

twTH

10

Write to RAS Precharge Time
(CAS Before RAS Refresh)

tWHREL

twRP

10

Write to RAS Hold Time (CAS
Before RAS Refresh)

tRELWL

twRH

10

Refresh Period

MCM81430
MCM8LI430

16
128

15

-

16
128

0

-

50

-

15

0
50
110
70

5

-

15

-

15

0

0

40

-

40

-

10

-

10

10

-

10

-

10

-

10

10

-

10

70

75
5

Max

16
128

-

20
20
25

60
135
85
90
5
20
0
50
10
10

Max

ns
ns
ns
ns

ns
ns
ns
ns
ns
ns
ns

NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in early write cycles.
15. twcs is not a restrictive operating parameters. It is included in the data sheet as an electrical characteristic only; if twcs " twcs (min).
the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition
is not satisfied. the condition of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA

3-187

•

MCM8143O-MCM8L1430

READ CYCLE

RAS

•

v1H V1L -

CAS

V1H V1L -

ADDRESSES VIH V1L -

W

DO

V1H V 1L -

VOH -

HIGHZ

VOL -

EARLY WRITE CYCLE

RAS

V1H V1L -

V1H CAS

V1L -

ADDRESSES VIH VIL - ~"-"r.....Y ~="F::or

W

DO

V1H V1L -

V1H -

HIGHZ - - - - - -

V1L -

MOTOROLA MEMORY DATA
3-188

MCM81430-MCM8L1430

FAST PAGE MODE READ CYCLE
_ V1H - --~
RAS V
IL -

14-------------

tRASP

-------------+1

i4----tpc

+--0.1

_ VIH - -r;--r;--r;--i--;r:%---+-+------+r-t-:lE-_r_--~,r_+r_i__.:l!:'"__r_-----_+t,~~

w

VIL - ...:L~.:.t-+:>J

DO VOH- - - - - - - - - - - { I
VOL -

FAST PAGE MODE EARLY WRITE CYCLE

V1H CAS V
IL -

ADDRESSESVIH -

V1L -

_ VIH W

VIL -

"''''''''''''':-7\
'-->I.~-"-'.........--"-,-1;==l~~"--"'-~"j;:::::;~~'-\T"---><-.,..~:::;'1=t;~"'-"'->L.-"-"'-

VIH - -.,.,.-",...."-.,.,....,,. ..J<--,=,,--:i. ..-.,.-.,,-...
DO

..I~~,,---L

VIL - --lL~....lL.:,t.....:>J "1I:...-';;;";;:":';;":'---':f" "~:....lo<:....Y ..,...,';;;";;:":';;":'...,;:f" "-'><-\\_'" .'------'Of" "'-"--"--"-_"'--'''--'''-

MOTOROLA MEMORY DATA
3-189

MCM81430-MCM8L1430

RA§ ONLY REFRESH CYCLE

(VI Is Don't Care)
~------------------'RC------------------~

•

14---------- 'RAS --------~

CAS

. . . . ------

V1H - ......,.....,........-::I.,---I-+---------------~-.

V1L -~'--lo,j'....:>l'

r
ADDRESSES:: =XXXMAD~~SSjO<'-"-><..................~+-+-

___-"I';.,.....J

DO VIH-

V1L -

-"__"__"_-" ,,'--_ _ _ _ _ _---'>r "-.......,;"-'~'_"__"__"__"_.>L_.......,;"-''_''_''__''__''__''_.>L_~

MOTOROLA MEMORY DATA
3-191

..

MCM81430-MCM8L1430

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
- - - i . i-'o-----------IRAS - - - - - - - - - - + /

•

Jc----~

14------IRSH ----~
Jc----1I4-----ICAS
r--!.:::l~---

ADDRESSES YylH ILREAD CYCLE

VALID DATA OUT

MOTOROLA MEMORY DATA
3-192

MCM81430-MCM8L1430

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the module. During an extended inactive state (greater than 16 milliseconds with the device powered up), a wake up sequence of eight active cycles is necessary to ensure proper operation.
ADDRESSING THE RAM
The ten address pins on the device are time multiplexed at
the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 1O-bit address fields. A total of twenty address bits, ten
rows and ten columns, will decode one of the 1,048,576 byte
locations in the device. RAS active transition is followed by
CAS active transition (active = VIL, tBm minimum) for all read
or write cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system
designer flexibility in setting up the external addresses into the
RAM.
_
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the module:
RAS only refresh cycle, CAS before RAS refresh cycle,
and page mode. All three are discussed in separate sections
that follow.
READ CYCLE
The DRAM may be read with either a "normal" random read
cycle or a page mode read cycle. The normal read cycle is outlined here, while the page mode cycle is discussed in a separate section.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (W) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex
window. CAS controls read access time: CAS must be active
before or at tRCD maximum to guarantee valid data out (OQ)
at tRAC (access time from RAS active transition). If the tRCO
maximum is exceeded, read access time is determined by the
CAS clock active transition (tCAe).
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. Wmust remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data althat bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitry for the next active
cycle. DQ is valid, but not latched, as long as the CAS clock is
active. When the CAS clock transitions to inactive, the output

will switch to High Z (three-state) !oFF after·the inactive transition.
WRITE CYCLE
The user can write to the DRAM with either an early write or
page mode early write cycle. Early write mode is discussed
here, while page mode write operations are covered in a separate section.
A write cycle begins as described in ADDRES~ING THE
RAM. Write mode is enabled by the transition of W to active
(Vul. Early write mode is distinguished by the active transition
of W, with respect to CAS. Minimum active time tRAS and
tCAS, and precharge time tRP apply to write mode, as in the
read mode.
An early write cycle is characterized by Wactive transition at
minimum time twcs before CAS active transition. Data in
(DQ) is referenced to CAS in an early write cycle. RAS and
CAS clocks must stay active fortRWL and tcWL, respectively,
after the start of the early write operation to complete the cycle.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
1024 column locations on a selected row of the module. Read
access time in page mode (tCAC) is typically half the regular
RAS clock access time, tRAC' Page mode operation consists
of keeping RAS active while toggling CAS between VIH and
~The row is latched by RAS active transition, while each
CAS active transition allows selection of a new column location on the row.
A page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for
minimum tcp, while RAS remains low (VIL). The second CAS
active transition while RAS is low initiates the first page mode
cycle (tpC)' Either a read or write operation can be performed
in a page mode cycle, subject to the same conditions as in normal operation (previously described). These operations can
be intermixed in consecutive page mode cycles and performed in any order. The maximum number of consecutive
page mode cycles is limited by tRASP' Page mode operation
is ended when RAS transitions to inactive, coincident with or
following CAS inactive transition.
REFRESH CYCLES
The dynamic RAM design is based on capaCitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically
refreshed (recharged) to maintain the correct bit state. Bits in
the MCM81430 require refresh every 16 milliseconds, while
refresh time for the MCM8L1430 is 128 milliseconds.
This is accomplished by cycling through the 1024 rowaddresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM81430, and 124.8 microseconds
for the MCM8L1430. Burst refresh, a refresh of aliI 024 rows
consecutively, must be performed every 16 milliseconds on
the MCM81430 and 128 milliseconds on the MCM8L1430.
A normal read or write operation to the RAM will refresh all
the bits associated with the particular row decoded. Three other methods of refresh, RAS-only refresh, CAS before RAS
refresh, and hidden refresh are available on this device for
greater system flexibility.

MOTOROLA MEMORY DATA
3-193

MCM81430-MCM8L1430

•

RA5-0nly Refresh
RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(VIH) throughoulthe cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.
CAS Before RAS Refresh
CAS before RAS refresh is el)abled by bringing CAS active
before RAS.This clock order actives an internal refresh counterthatgenerates the row address to be refreshed. External address lines are ignored during the automatic refresh cycle. The
output buffer remains althe same state it was in during the previous cycle (hidden refresh). Wmust be inactive for time twRP
before and time twRH after RAS active transition to prevent
switching the device into a test mode cycle.
Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). Wis subject to the same conditions
with respect to RAS active transition (to prevent test mode
cycle) as in CAS before RAS refresh.

MEMORY CYCLE

CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CAS before RAS refresh counter test. This refresh counter test is performed with read and write operations. During this
test, the internal refresh counter generates the row address,
while the external address supplies the column address. The
entire array is refreshed after 1024 test cycles, as indicated by
the check data written in each row. See CAS before RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as follows:
1. Write "O"s into all memory cells with normal write mode.
2. Select a column address, and read "0" out of the cell by
performing CAS before RAS refresh counter test,
read cycle. Repeat this operation 512 times.
3. Select a column address and write "1" into the cell by
performing the CAS before RAS refresh counter test,
write cycle. Repeat this operation 512 times.
4. Read "1"s (normal read mode), which were written at
step 3.
5. Repeat steps 1 to 4 using complement data.

REFRESH CYCLE

r

\

REFRESH CYCLE

r'
f--

/
/

DQ -HIGHZ

VALID DATA-OUT

j

\f--

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory Prefix

~
Speed (60 = 60 ns, 70 = 70 ns,
80 80 ns, 10 100 ns)

Part Number

=

Package (S = SIMM)

Full Part Numbers- MCMB1430S60
MCMBl430S70
MCMB1430SBO
MCMBl430S10

MCM8L1430S60
MCMBL1430S70
MCMBL1430SBO
MCMBL1430S1 0

MOTOROLA MEMORY DATA
3-194

=

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - -

TECHNICAL DATA

MCM84000
MCM8L4000

4Mx8 Bit Dynamic Random
Access Memory Module
The MCM84000S is a 32M, dynamic random access memory (DRAM) module
organized as 4,194,304 x 8 bits. The module is a 30-lead single-in-line memory
module (SIMM) consisting of eight MCM54100A DRAMs housed in 20/26 J-Iead
small outline packages (SOJ) mounted on a substrate along with a 0.22 IlF (min)
decoupling capacitor mounted under each DRAM. The MCM54100A is a CMOS
high speed, dynamic random access memory organized as 4,194,304 one-bit
words and fabricated with CMOS silicon-gate process technology.
•
•
•
•
•
•
•
•

•
•
•

•

•

•
•

Three-State Data Output
Early-Write Common 1/0 Capability
Fast Page Mode Capability
TIL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh:
MCM84000 = 16 ms
MCM8L4000 = 128 ms
Consists of Eight 4M x 1 DRAMs and Eight 0.22 IlF (Min) Decoupling Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access Time (tRAC)
MCM84000S-80 = 80 ns (Max)
MCM84000S-10 = 100 ns (Max)
Low Active Power Dissipation:
MCM84000S-80 and MCM8L4000S-80 = 4.4 W (Max)
MCM84000S-10 and MCM8L4000S-10 = 3.75 W (Max)
Low Standby Power Dissipation:
TIL Levels = 88 mW (Max)
CMOS Levels (MCM84000) = 45 mW (Max)
(MCM8L4000) = 18 mW (Max)
CAS Control for Eight Common I/O Lines
Available in Edge Connector (MCM84000S) or Low Height Pin Connector
(MCM84000LH)

•

SPACKAGE
SIMMMODULE

CASE 839B

30-PIN
SINGLE IN· LINE PACKAGE
(TOP VIEW, MCM84000S/8L4000S)
~

~~ !~l~oO
DQO (3)

AO (4)

Al

(5)

DOl (6)
A2 (7)

0

DO

~~(!~!

A4 (II)
AS (12)

DQ3 (13)

AS (14)

:~lll!~OO

~(20)

w (21)

:~I~!§OO

NC
RAS
NC
Ne
Vee

(26)
(27)
(2B)
(29)
(30) ~

:5

=!

0

PIN NAMES
AO-A 10 .................... Address Inputs
DOD-DO? ............... Data InpuVOutput
CAS ............... Column Address Strobe
RAS .................. Row Address Strobe
iN ........................ ReadiWrite Input
VCC ........................ Power (+5 V)
VSS .............................. Ground
NC ......................... No Connection

MOTOROLA MEMORY DATA
3-195

MCM84000-MCM8L4000

FUNCTIONAL BLOCK DIAGRAM

..

DOO

1

oJ

D

~

DQ4

1
---'\.

AO-Al0

r-~ RAS
r-f-f- f-

DOl

r-fr- -f-

~ CAS

iN

~

r-H-

1

ti\:
~

~

..... r- r ....... - f-

D

~

1

oJ

D05

1

ti\:

AO-Al0
~

RAS

~

....... r- r -

CAS
~

-f-

~

....... f-

[II'
I--

1

D06

1

t;;::

AO-Al0
RAS

~

I-- CAS
r - iN

....... f-

~

...... f-

AO-Al0

~
~

~

RAS
CAS

-r-

~

D

oJ

AO-Al0
RAS

I-- GAS
r-iN
...:..j.~

oJ

D

oJ

I-- iN

HID03

D
AO-Al0

rlr--

oJ

D

RAS

rir--

I-- iN

t;;::

oJ

I-- CAS
l--iN

~ID02

D
AO-Al0

DO?

1

AO-Al0
RAS

~

I-- CAS
I-- iN

...... f~ -f-

.~~

~
~

0

oJ

AO-Al0
RAS

I-- CAS
l--iN

~r--

RAS
CAS

iN
VCC

Vss

MOTOROLA MEMORY DATA
3-196

MCM84000-MCM8L4000

ABSOLUTE MAXIMUM RATING (See Note)
Rating

Symbol

Value

Unit

VCC

-1 to +7

V

Vin, Vout

-1 to +7

V

lout

50

mA

Power Supply Voltage
Voltage Relative to V SS for Any Pin Except V CC
Data Out Current per DO Pin
Power Dissipation

Po

4.B

W

Operating Temperature Range

TA

o to +70

°c

Storage Temperature Range

T~tn

-25 to +125

°c

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit.

NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA = 0 to 70 o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

-

Logic High Voltage, All Inputs

VIH

2.4

6.5

V

1

Logic Low Voltage, All Inputs

VIL

-1.0

-

O.B

V

1

Symbol

Min

Max

Unit

Notes

mA

2

DC CHARACTERISTICS
Characteristic
VCC Power Supply Current
MCM64000-80, tRC = 150 ns
MCM84000-10, tRC = 180 ns

ICCl

VCC Power Supply Current (Standby) (RAS=CAS=VIH)

ICC2

VCC Power Supply Current During RAS Only Refresh Cycles
MCM84000-80, tRC = 150 ns
MCM84000-10, tRC = 180 ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle
MCM84000-BO, tpc = 45 ns
MCM84000-1 0, tpc = 55 ns

ICC4

MCM84000
MCM8L4000

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V)

-

-

ICC5

V CC Power Supply Current During CAS Before RAS Refresh Cycle
MCM84000-80, tRC = 150 ns
MCM84000-10, tRC = 180 ns

ICC6

VCC Power Supply Current, Battery Backup Mode-MCM8L4QQO Only
(tRC = 12511S; CAS = CAS Before RAS Cycling or 0.2 V; W = VCC-D.2 V;
DQ = VCC-D.2 V, 0.2 V or Open; AO-Al0 - VCC-D.2 V or 0.2 V)
tRAS = Min to 1 I1s

ICC7

800
680
16

mA
mA

2

mA

2,3

800
680

-

480
400

-

800
680

8
3.2

mA
mA

2

2,4

-

4.0

mA

!1A
!1A

Input Leakage Current (VSS" Vin "VCC)

Ilkotn

~O

80

Output Leakage Current (CAS at LogiC 1, VSS" Vout" VCe!

IlkolO)

-20

20

Output High Voltage (lOH = -5 mAl

VOH

2.4

Output Low Voltage (IOL = 4.2 mAl

VOL

-

0.4

V
V

CAPACITANCE (f = 1.0 MHz, TA = 25°C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter

Symbol

Input Capacitance

AO-Al0, W, CAS, RAS
DQO....D07

InpuVOutput Capacnance

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
3. Measured with one address transition per page mode cycle.
4. tRAS (max) = 1 !1S is only applied to refresh of battery backup. tRAS (max) = 10 !1S is applied to functional operating.
5. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I~V~V.

MOTOROLA MEMORY DATA
3-197

•

MCM84000-MCM8L4000

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 700 e, Unless Otherwise Noted)

..

READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)
Parameter

MCM84000-80

MCM8400D-l0

Altemate

Min

Max

Min

Max

-

180

-

60

Symbol
Standard

Random Read or Write Cycle TIme

tRELREL

tRC

150

Page Mode Cycle TIme

leELCEL

tpc

50

Access TIme from RAS

tRELQV

tRAC

Access TIme from CAS

tCELQV

leAC

Access TIme from Column Address

tAVQV

tAA

Access TIme from Precharge CAS

tCEHQV

tCPA

-

CAS to Output in Low-Z

leELQX

tCLZ

Output Buffer and Turn·Off Delay

tCEHQZ

tOFF

Transition TIme (Rise and Fall)

Unit

Notes

-

ns

5

100

ns

6,7

25

ns

6,8

50

ns

6,9

55

ns

6

ns

45

-

0

-

0

-

ns

6

0

20

0

20

ns

10

80
20
40

IT

IT

3

50

3

50

ns

RAS Precharge TIme

tREHREL

tRP

60

-

70

-

ns

RAS Pulse Width

tRELREH

tRAS

80

10,000

100

10,000

ns

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

80

200,000

100

200,000

ns

RASHoldTIme

tCELREH

tRSH

20

-

25

ns

CAS Hold TIme

tRELCEH

leSH

80

-

100

-

CAS Pulse Width

tCELCEH

leAS

20

10,000

25

10,000

ns

RAS to CAS Delay TIme

tRELCEL

tRCD

20

60

25

75

ns

11

RAS to Column Address Delay TIme

tRELAV

tRAD

15

40

20

50

ns

12

CAS to RAS Precharge TIme

leEHREL

tCRP

5

leP

10

Row Address Setup TIme

tAVREL

tASR

0

-

0

-

ns

tCEHCEL

-

10

CAS Precharge TIme

10

Row Address Hold TIme

tRELAX

tRAH

10

tAVCEL

tASC

0

-

15

Column Address Setup TIme
Column Address Hold TIme

tCELAX

leAH

15

-

Column Address Hold TIme Referenced to RAS

tRELAX

tAR

60

Column Address to RAS Lead TIme

tAVREH

tRAL

40

-

-

ns

ns
ns
ns
ns

20

-

75

-

ns

50

-

ns

0

ns

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL'
2. An initial pause of 200 liS is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VI H) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (O°C ,; TA';
70·C) is assured.
6. Measured with a current load equivalent to 2 TIL (-200 IIA, +4 mAl loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD" tRCD (max).
8. Assumes that tRCD ~ tRCD (max).
9. Assumes that tRAD 2: tRAD (max).
10. tOFF (max) defiries the'time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11.. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC'
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specffied as a reference point only; HtRAD is
greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
3-198

MCM84000-MCM8L4000

READ AND WRITE CYCLES (Continued)
MCM84CJCIO.8O

MCM84000-10

Altemate

Min

Min

Max

0

-

Symbol

Parameter

Standard

Read Command Setup lime

twHCEL

tRCS

0

Read Command Hold lime Referenced to CAS

leEHWX

tRCH

0

Read Command Hold lime Referenced to RAS

tREHWX

tRRH

0

Write Command Hold lime Referenced to CAS

leELWH

twCH

15

Write Command Hold lime Referenced to RAS

tRELWH

twCR

60

Write Command Pulse Width

twLWH

twP

15

Write Command to RAS Lead lime

twLREH

tAWL

20

Write Command to CAS Lead lime

twLCEH

tCWL

20

Data in Setup lime

tOVCEL

tos

0

Data in Hold lime

leELOX

tOH

15

Data In Hold lime Referenced to RAS

tAELOX

tOHA

60

tRVAV

tAFSH

-

Refresh Period

MCM84000
MCM8L4000

Write Command Setup lime

twLCEL

twcs

0

CAS Setup lima for CAS Before RAS Aefresh

tAELCEL

leSA

5

CAS Hold lime for CAS Before AAS Aefresh
CAS Precharge to CAS Active lime

tRELCEH

leHA

15

tAEHCEL

tAPC

0

Max

16
128

-

0
0
20
75
20
25
25
0
20
75

0
10
20
0

Unit

Notea

ns
ns

13

ns

13

ns
ns
ns
ns
ns
ns

14,15

ns

14,15

ns

16
128

ms

-

ns

15,16

ns
ns
ns

CAS Precharge lime for CAS Before RAS Counter Test tcEHCEL
50
ns
40
tCPT
NOTES:
13. Either tAAH or tACH must be satisfied for a read cycle.
14. lihese parameters are referenced to CAS leading edge In random write cycles.
15. Early write only (twcs ~ twcs (min)).
16. twcs Is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs ~ twcs (min), the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is
not satisfied, the condition of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
3-199

MCM84000-MCM8L4000

READ CYCLE

•
ADDRESSES VIHVIL -

W VIHVIL - ......,'--''--'''"'7''--''................'--'''--''~

DO VOH- _ _ _ _ _ __
(DATA OUT) VOL -

EARLY WRITE CYCLE
~-------------tRC-----------~

RAS VIHVIL -

--"L

~---------tMS-------~

J,,--------------,,L

1+---- tRCD ------t---

ADDRESSES VIHVIL -

W VIH-

I-"'-.. . . .'-""'-><..,;f;:=4=::j::i;;;;:::==+=~->L..........,"-"'-"-""'--'''-'''-''-...><.....>.

VIL - -"'-........

tD~

(DATA

~~ ~:: =>L.->L....OI

DO VOH(DATA OUT) VOL _

-----------1--<1

HIDDEN REFRESH CYCLE (WRITE)

ADDRESSES VV IH -

IL -

W VIHVIL- ~~~~~~~~--~r-----~~~~~~~~~~~~~~~~~~~

DO VIH (DATA IN) V IL -

-rr~"7':"'*~~'" Jr--------:lll'l~~_;<:~"7':"'"7':"7<:""~~~7'r"':~~0;_'7r_,,:_

-l<-->L.--"--'f--"--"-'y

l''-------------'r ,,'--"--"---"---"--"--"--"--"-""'-"'-"'--'''-'''--'''--'''-'''-

1*----tDHR----~

MOTOROLA MEMORY DATA
3-203

MCM84000-MCM8L4000

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

~---------------tMS------------------~~

•

RAS

CAS

VIHVIL -

VIHVIL -

ADDRESSES

VIHVIL -

READ CYCLE
DO VOH- - - - - - - - HIGHZ
(DATA OUT) VOL-

W

------1+<1

VIHVIL -

WRITE CYCLE

W

DO
(DATA IN)

VIH-

f
~II~ =-,~--

~

-

0

oJ

005

1

~

AO-Al0

1
~

>-,-

~

--

~
~
-

1

J\

~

>-t~

AO-Al0

-,-

:!C
-

0

~

~

tt-

I-- CAS
I-- Vi

Vi

~

0

oJ

006

RAS

HI-

1

~

AO-Al0

0

~

~

AO-Al0

RAS
CAS

>-t-

r--

CAS

-t-

I-- Vi

Vi

0

~

oJ

oj

Ao-Al0

RAS

oj

RAS

HI-

0---11DQ3

RAS

CAS

0---11002

oJ

~-H-

0---11001

0
Ao-Al0

007

1

Ao-A1O
RAS

~

CAS

>-t>-- t-

Vi

~~

~
~

0

oj

AO-Al0
RAS

I-- CAS

-

Vi

0---11-

RAS
CAS

Vi
VCC
VSS

MOTOROLA MEMORY DATA
3-208

MCM~A·MCM8~A

ABSOLUTE MAXIMUM RATING (See Note)
Rating
Power Supply Voltage

Symbol

Value

Unit

VCC

-1 to +7

V

Vin, Vout

-1 to +7

V

Data Out Current per DO Pin

lout

50

mA

Power Dissipation

PD

5.6

W

Operating Temperature Range

TA

o to +70

°C

Voltage Relative to VSS for Any Pin Except VCC

This device contains circuitry to pratect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit.

Storage Temperature Range
-25 to +125
°C
Tsta
NOTE: Permanent device damage mayoccunf ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higherthan recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ±10%, TA =0 to 70 D e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

-

6.5

V

1

Logic Low Voltage, All Inputs

VIL

-1.0

-

O.B

V

1

Max

Unit

Notes

mA

2

DC CHARACTERISTICS
Characteristic

Symbol

VCC Power Supply Current
MCMB4000A-60, tRC = liOns
MCMB4000A-70, tRC = 130 ns
MCM84000A-80, tRC = 150 ns
MCM84000A-l0, tRC = 180 ns
VCC Power Supply Current (Standby) (RAS

ICCI

--

= CAS = VIH)

ICC2

VCC Power Supply Current During RAS Only Refresh Cycles
MCM84000A-60, tRC = 110 ns
MCM84000A-70, tRC = 130 ns
MCM84000A-80, tRC = 150 ns
MCM84000A-l0, tRC = 180 ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle
MCM84000A-60, tpc = liOns
MCM84000A-70, tpc = 45 ns
MCM84000A-80, tpc = 50 ns
MCM84000A-l0, tpc = 60 ns

ICC4

VCC Power Supply Current (Standby) (RAS

Min

= CAS = VCC -

--

0.2 V)

MCM84000A
MCM8L4000A

ICC5

V CC Power Supply Current During CAS Before RAS Refresh Cycle
MCM84000A-60, tRC = liOns
MCM84000A-70, tRC = 130 ns
MCM84000A-80, tRC = 150 ns
MCM84000A-l0, tRC = 180 ns

ICC6

VCC Power Supply Current, Battery Backup Mode--MCM8L4~OA Only
(tRC = 125 JlS; CAS = CAS Before RAS Cycling or 0.2 V; W = VCC - 0.2 V;
DO = VCC - 0.2 V, 0.2 V or Open; AO-Al0 = VCC - 0.2 V or 0.2 V)
tRAS = Min to 1 ItS

ICC7

960
BOO
680
600
16

mA
mA

2

mA

2,3

960
800
680
600

-

-

480
480
400
360

-

8
1.6

-

--

960
800
680
600

-

mA
mA

2

2.4

mA

2,4

ItA
ItA

Input Leakage Current (VSS" Vin" VCC)

IlkoCll

--80

80

Output Leakage Current (CAS at Logic I, VSS" Vin "VCC)

Ilka(OI

-20

20

Output High Voltage (IOH

=-5 mAl
= 4.2 mAl

VOH

2.4

-

V

Output Low Voltage (lOl

VOL

-

0.4

V

MOTOROLA MEMORY DATA

3-209

•

MCM~A·MCM8~A

CAPACITANCE (f = 1.0 MHz, TA =2SoC, VCC = S V, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

•

AQ-Al0,W,CAS,RAS

Symbol

Max

Unit

Notes

Cin

SO

pF

S

InpuVOutput Capacitance
DQQ-OQ7
22
pF
S
CliO
NOTES:
1. All vollages referenced to VSS .
2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
3. Measured with one address transition per page mode cycle.
4. tRAS (max) = 1 IlS is only applied to refresh of battery backup. tRAS (max) = lOllS is applied to functional operating.
S. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I!J.V!J.V.

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70o e, Unless Otherwise Noted)
READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)

Parameter

Symbol

840ooA-60
8L4000A-60

84000A-70
8L4000A-70

840ooA-80
8L4000A-80

84OO0A-l0
BL4000A-l0

Unit

Notes

ns

S

60

-

-

100

ns

6,7

-

25

ns

6,8

SO

ns

6,9
6

Std

Alt

Min

Max

Min

Max

Min

Max

Min

Max

Random Read or Write Cycle
Time

tRELREL

tRC

110

-

130

-

150

-

180

80
20

45

-

45

60

-

70

30
40

-

35

tCPA

-

40

-

teLZ

0

-

0

-

0

-

toFF

0

20

0

20

0

20

Fast Page Mode Cycle Time

teELCEL

tpc

Access Time from RAS

tRELQV

tRAC

Access Time from CAS

tCELQV

teAC

tAVQV

tM

Access Time from Precharge CAS

teEHQV

CAS to Output in Low-Z

teELQX

Output Buffer and Tum-Off Delay

teEHQZ

Access Time from Column
Address

Transition Time (Rise and Fall)

20

20

SO

40
45

ns

55

ns

0

-

ns

6

0

20

ns

10

IT

IT

3

SO

3

SO

3

SO

3

SO

ns

RAS Precharge Time

tREHREL

tRP

40

-

SO

-

60

-

70

-

ns

RAS Pulse Width

tRELREH

tRAS

60

10k

70

10k

80

10k

100

10k

ns

RAS Pulse Width (Fast Page
Mode)

tRELREH

tRASP

60

200k

70

200k

80

200k

100

200k

ns
ns

ns

RAS Hold Time

tCELREH

tRSH

20

-

20

-

20

-

25

CAS Hold Time

tRELCEH

tCSH

60

-

70

-

80

-

100

CAS

tCEHREH

tRHCP

40

-

40

-

45

-

S5

-

Precharge to RAS Hold

Time
CAS Pulse Width

tCELCEH

teAS

20

10k

20

10k

20

10k

2S

10 k

RAS to CAS Delay Time

tRELCEL

tRCD

20

40

20

50

20

60

25

75

ns
ns

ns
11
(conllnued)

NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL'
2. An initial pause of 200 IlS is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input Signals must
transition between VIH and VIL (or between VIL and VI H) in a monotonic manner.
4. AC measurements IT = S.O ns.
S. The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (O°C ,;; TA';;
70°C) is assured.
6. Measured with a current load equivalentto 2 TTL (-200~, +4 rnA) loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD';; tRCD (max).
8. Assumes that tRCD 2: tRCD (max).
9. Assumes that tRAD 2: tRAD (max).
10. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC'

MOTOROLA MEMORY DATA

3-210

MCM~A·MCM8~A

READ AND WRITE CYCLES (Continued)
Parameter

Symbol

84000A-60
8L4000A-60

84OOOA-70
8L4000A-70

84OOOA-80
8L4000A-80

84OO0A-l0
8L4000A-l0

Unit Notes

Std

Alt

Min

Max

Min

Max

Min

Max

Min

Max

tRELAV

tRAO

15

30

15

35

15

40

20

50

ns

CAS to RAS Precharge Time

tCEHREL

leRP

5

-

10

-

ns

lep

10

10

-

5

tCEHCEL

-

5

CAS Precharge Time

10

-

10

ns

Row Address Setup Time

tAVREL

tASR

0

-

0

-

0

-

0

Row Address Hold Time

tRELAX

tRAH

10

-

10

-

10

-

-

15

Column Address Setup Time

tAVCEL

tASC

0

-

0

-

0

-

0

Column Address Hold Time

leELAX

leAH

15

-

15

-

15

-

20

Column Address to RAS Lead
Time

tAVREH

tRAL

30

-

35

-

40

-

50

-

RAS to Column Address Delay
Time

Read Command Setup Time

twHCEL

tRCS

0

-

0

-

0

Read Command Hold Time
Referenced to CAS

tCEHWX

tRCH

0

-

0

-

0

Read Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

-

0

-

0

Write Command Hold Time
Referenced to CAS

tCELWH

twCH

10

15

-

15

-

12

•

ns
ns
ns
ns

0

-

0

-

ns

13

0

-

ns

13

ns
ns

Write Command Pulse Width

twLWH

twp

10

-

15

-

15

-

20

-

ns

Write Command to RAS Lead
Time

twLREH

tRWL

20

-

20

-

20

-

25

-

ns

Write Command to CAS Lead
Time

twLCEH

tCWL

20

-

20

-

20

-

25

-

ns

-

0

-

ns

14

20

ns

14

-

16
128

ms

Data in Setup Time

tOVCEL

tos

0

Data in Hold Time

leELOX

tOH

15

tRVRV

tRFSH

Write Command Setup Time

tWLCEL

CAS Setup Time for CAS Before
RAS Refresh

0

-

0

15

-

15

16
128

-

-

-

16
128

twcs

0

tRELCEL

leSR

5

CAS Hold Time for CAS Before
RAS Refresh

tRELCEH

leHR

15

-

RAS Precharge to CAS Active
Time

tREHCEL

tRPC

0

-

0

CAS Precharge Time for CAS
Before RAS Counter Time

tCEHCEL

tCPT

30

Write Command Setup Time (Test
Mode)

twLREL

twrs

10

Write Command Hold Time (Test
Mode)

tRELWH

twTH

10

Write to RAS Precharge Time
(CAS Before RAS Refresh)

twHREL

twRP

10

-

Refresh Period

MCM84000A
MCM8L4000A

-

40

-

10

-

16
128

20

-

ns

0

-

0

-

ns

5

-

5

-

ns

15

-

20

-

ns

0

-

0

ns

40

-

50

-

10

10

10

-

10

-

10

-

10

-

10

-

0
5
15

-

10

15

ns
ns
ns
ns

Write to RAS Hold Time (CAS
10
10
10
10
ns
tRELWL
tWRH
Before RAS Refresh)
NOTES:
12. Operation within the tRAO (max) limit ensures thattRAC (max) can be met. tRAO (max) is specified as a reference point only; if tRAO is
greater than the specified tRAO (max) limit, then access time is controlled exclusively by tAA.
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in early write cycles.
15. twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs 2: twcs (min), the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is
not satisfied, the condition of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
3-211

MCM~A·MCM8~A

READ CYCLE
~----------------------tRC----------------------~
~--------------tAAS --------------~

..t---------ci-

II
I

ADDRESSES VIHVIL -

W VIHVIL -

DQ (DATA OUT) VOH VOL -

:....'l'-l.'-l.y.~~~~~~

- - - - - - - - - - - - HIGH

z -------------<1

VALID DATA

EARLY WRITE CYCLE
~-----------------------tAC----------------------~

~--------------tRAS

~---

-------------_

..t--------..,.

tACD -----__I"i4-----

ADDRESSES VIH VIL -

W VIHVIL - ...;,t.~~~...::.J.....::.J.....::.J.....::.J....::L+_--_+---1-------""'--'''_;_>'--'''--'''-'''-'''-'''-''-''-''-''-''-''

.1

tDH~",

tD~

DO (DATA IN)

~:~ =>L....l>L....l~~'....Y

DO (DATA OUT) VOH VOL-

-----------KIX

"'--'=-=~

FAST PAGE MODE EARLY WRITE CYCLE

ADDRESSES VIH VIL-

iN VIHVIL-

~>L....l>L....l>L....l>L....l>L....l~~---r__r-~~~__+--+~~~~-+__r-~~>L....l>L....l>L....l>L....l>L....l~~

DO (DATA IN) VIH VIL - -k--"--"-........................" -~~________~

MOTOROLA MEMORY DATA
3-213

MCM~A·MCM8~A

RAS ONLY REFRESH CYCLE
(Wand A10 are Don't Care)
~------------------tRC------------------------~

•
AOTOA9 VtHVIL -

DQ(DATAOUn VOH - - - - - - - - - - - - - - - - HIGHZ _ _ _ _ _ _ _ _ _ _ _ _ _ __
VOL -

CAS BEFORE RAS REFRESH CYCLE
(AD to A10 are Don't Care)

14-----------------t RC

---------------.J

~--------tMS--------~

RAS VIHVIL -

iii

VIH-

VIL -

DQ(DATAOUT)

-:.t.-.::.i.-",,--¥-.:.L..:J

~~~ =------"11-----------

MOTOROLA MEMORY DATA
3-214

HIGHZ - - - - - - - - - - -

MCM~A·MCM8~A

HIDDEN REFRESH CYCLE (READ)

ADDRESSES VVIH IL-

W VIHVIL -

DQ(DATAOUT) VOH VOL -

-",-",,",,--",--¥--",--",-J

-----------+-<1

HIDDEN REFRESH CYCLE (EARLY WRITE)

ADDRESSES VVIH IL -

DQ(DATAIN)

V1HVIL -

MOTOROLA MEMORY DATA
3-215

MCM~A·MCM8~A

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

~---------------IRAS------------------~ ~~~
~-----

tRSH

------<~

--'I""---lL

~----tCAS - - - - - + (

HADDRESSES VVIIL-

~~~~~~~~~~~~

~____~____~

~~~~~~~~~~~

READ CYCLE

DO (DATA OUT) VOHVOL- --------++----- HIGH z ---------++<1

EARLY WRITE CYCLE

W

VIHVIL -

DO (DATA IN) ::~=

f
(XXXXXXXXXXX

tDS
tDH3<
VALIDDATAXXXXXXXXXXX)

MOTOROLA MEMORY DATA

3-216

MCM~A·MCM8~A

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the module. During an extended inactive state (greater than 16 milliseconds with the device powered up), a wake up sequence of eight active cycles is necessary to ensure proper operation.
ADDRESSING THE RAM
The eleven address pins on the device are time multiplexed
althe beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 11-bit address fields. A total of twenty two address bits,
eleven rows and eleven columns, will decode one of the
4,194,304 word locations in the device. RAS active transition
is followed by CAS active transition (active = VIL, t~mini
mum) for all read or write cycles. The delay between RAS and
CAS active transitions, referred to as the multiplex window,
gives a system designer flexibility in setting up the external addresses into the RAM.
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the module:
RAS only refresh cycle, CAS before RAS refresh cycle,
and page mode.
READ CYCLE
The DRAM may be read with either a "normal" random read
cycle or a page mode read cycle. The normal read cycle is outlined here, while the other cycles are discussed in separate
sections.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the deSired bit location. The write (W) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time olthe device is independent of the address multiplex
window; however, CAS must be active before or altRCD maximum to guarantee valid data out (DO) at tRAC (access time
from RAS active transition). If the tRCD maximum is exceeded, read access time is determined by the CAS clock active
transition (tCAC)'
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. Wmust remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data althat bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitry for the next active
cycle. DO is valid, but not latched, as long as the CAS clock is

active. When the CAS clock transitions to inactive, the output
will switch to High Z (three-state).
WRITE CYCLE
The user can write to the DRAM with either an early write or
page mode early write cycle. Early write mode is discussed
here, while page mode write operation is covered elsewhere .
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
(V
Early write mode is distinguished by the active transition
of W, with respect to CAS. Minimum active time tRAS and
tCAS, and precharge time tRP apply to write mode, as in the
read mode.
An early write cycle is characterized by Wactive transition at
minimum time twcs before CAS active transition. Data in
(DO) is referenced to CAS in an early write cycle. RAS and
CAS clocks must stay active for tRWL and tCWL' respectively,
after the start olthe early write operation to complete the cycle.

uJ..

PAGE MODE CYCLES
Page mode allows fast successive data operations at all
2048 column locations on a selected row of the module. Read
access time in page mode (tCAC) is typically half the regular
RAS clock access time, tRAC' Page mode operation consists
of keeping RAS active while toggling CAS between VIH and
~ The row is latched by RAS active transition, while each
CAS active transition allows selection of a new column location on the row.
A page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for
minimum of tcp, while RAS remains low (VIL). The second
CAS active transition while RAS is low initiates the first page
mode cycle (tpC). Either a read or write operation can be performed in a page mode cycle, subject to the same conditions
as in normal operation (previously described). These operations can be intermixed inconsecutive page mode cycles and
performed in any order. The maximum number of consecutive
page mode cycles is limited by tRASP' Page mode operation
is ended when RAS transitions to inactive, coincident with or
following CAS inactive transition.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically
refreshed (recharged) to maintain the correct bit state. Bits in
the MCM84000A require refresh every 16 milliseconds, while
refresh time for the MCM8L4000A is 128 milliseconds.
This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM84000A, and 124.8 microseconds
for the MCM8L4000A. Burst refresh, a refresh of alii 024 rows
consecutively, must be performed every 16 milliseconds on
the MCM84000A and 128 milliseconds on the MCM8L4000A.
A normal read or write operation to the RAM will refresh all
the bits (4096) associated with the particular row decoded.
Three other methods of refresh, RAS-only refresh, CAS before RAS refresh, and hidden refresh are available on this
device for greater system flexibility.

MOTOROLA MEMORY DATA
3-217

..

MCM~A·MCM8~A

respect to RAS active transition (to prevent test mode cycle)
as in CAS before RAS refresh.

RAS-Only Refresh
RAS-only refresh consists of RAS transition to active,latching the row address to be refreshed, while CAS remains high
(VIH) throughoutthe cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.

•

CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CAS before RAS refresh counter test. This test is performed with a read-write operation. During the test, the internal
refresh counter generates the row address, while the external
address supplies the column address. The entire array is refreshed after 1024 cycles, as indicated by the check data written in each row. See CAS before RAS refresh counter test
cycle timing diagram.
The test can be performed aiter a minimum of 8 CAS before
RAS initialization cycles. Test procedure:
1. Write "O"s into all memory cells (normal write mode).
2. Select a column address, and read "0" out olthe cell by performing CAS before RAS refresh counter test, read
cycle. Repeat this operation 1024 times.
3. Select a column address, and write "I" into the cell by performing CAS before RAS refresh counter test, write
cycle. Repeat this operation 1024 times.
4. Read "1"s (normal read mode), which were written at step
3.
5. Repeat steps 1 to 4 using complement data.

CAS Before RAS Refresh

CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order actives an internal refresh
counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh
cycle.
The output buffer remains at the same state it was in during
the previous cycle (hidden refresh). W must be inactive for
time tWRP before and time !wRH aiter RAS active transition to
prevent switching the device into a test mode cycle.
Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active the end
of a read or write cycle, while RAS cycles inactive for tRP and
back to active, starts the hidden refresh. This is essentially the
execution of a CAS before RAS refresh from a cycle in progress (see Figure 1). Wis subject to the same conditions with

r

\

CAS BEFORE RAS
REFRESH CYCLE

CAS BEFORE RAS
REFRESH CYCLE

MEMORY CYCLE

I'
/

/

DQ -HIGHZ

\J

VALID DATA·OUT

\.

-

Figure 1. Hidden Refresh Cycle
ORDERING INFORMATION

(Order by Full Part Number)
MCM 84000A or 8L4000A

Motorola Memory Prefix
Part Number

~

I

11 "''
x

XX

'oo.

oo~, "-"",," -""''' - '00""

Package (AS

Full Part Numbers-MCM84000AS60
MCM84000AS70
MCM84000AS80
MCM84000AS10
MCM8L4000AS60
MCM8L4000AS70
MCM8L4000AS80
MCM8L4000AS10

=SIMM, L =SIP, LH =Low Height SIP)

MCM64000L60
MCM84000L70
MCM84000180
MCM84000L10

MCM84030LH60
MCM84030LH70
MCM84030LH80
MCM84030LH10

MCM8L4000L60
MCM8L4000L70
MCM8L4000L80
MCM8L4000L10

MCM8L4030LH60
MCM8L4030LH70
MCM8L4030LH80
MCM8L4030LH10

MOTOROLA MEMORY DATA

3-218

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM84256
MCM8L4256

256Kx8 Bit Dynamic Random
Access Memory Module
The MCMB4256 is a 2M, dynamic random access memory (DRAM) module
organized as 262,144 x B bits. The module is a 30-lead single-in-line memory
module (SIMM) consisting of two MCM514256A DRAMs housed in 20/26
J-Iead small outline package (SOJ) and mounted on a substrate along with a
0.221!F (min) decoupling capacitor mounted adjacent to each DRAM. The
MCM514256A is a 1.011 CMOS high speed, dynamic random access memory
organized as 262,144 four-bit words and fabricated with CMOS silicon-gate
process technology.
•
•
•
•
•
•
•
•

•
•
•

•

•

•
•

Three-State Data Output
Early-Write Common 1/0 Capability
Fast Page Mode Capability
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
512 Cycle Refresh:
MCM84256 = B ms (Max)
MCMBL4256 = 64 ms (Max)
Consists of Two 256Kx4 DRAMs and Two 0.22 IlF (Min) Decoupling Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access Time (tRAC):
MCMB4256-70 = 70 ns (Max)
MCMB4256-BO = BO ns (Max)
MCMB4256-10 = 100 ns (Max)
Low Active Power Dissipation:
MCMB4256-70 = 0.9 W (Max)
MCMB4256-BO = O.B W (Max)
MCMB4256-10 = 0.7 W (Max)
Low Standby Power Dissipation:
TTL Levels = 22 mW (Max)
CMOS Levels (MCMB4256) = 11 mW (Max)
(MCMBL4256) = 2.2 mW (Max)
CAS Control for Eight Common 1/0 Lines
Available in Edge Connector

III

SPACKAGE
SIMMMODULE
CASE 839A

30-PIN
SINGLE IN-LINE PACKAGE
(TOP VIEW, MCM84256S/8L4256S)

,---J()

~ m~ DO
AO (4)

~

D~: !~! ~

~ fa! ~

Vss (9)
OD2 (10)
A4 (11)
A5 (12)
DQ3 (13)
A6 (14)
A7 (15)
DQ4 (16)
A6 (17)

=g [:~!

Vss (22)
DQ6 (23)
Ne (24)
DQ7 (25)

D
0

W (21) :J
~(20)

;!

~~[~

NC (28)
NC (29)

Vcc (30)

o

PIN NAMES
AO-A8 ...................... Address Inputs
DOO-D07 ............... Data InpuVOutput
CAS ............... Column Address Strobe
RAS .................. Row Address Strobe
W ........................ ReadlWrite Input
VCC ........................ Power (+5 V)
VSS·.··· ......................... Ground
NC ......................... No Connection

MOTOROLA MEMORY DATA
3-219

MCM84256- MCM8L4256

FUNCTIONAL BLOCK DIAGRAM
DOC-D03

DQO-D03

~

---v

..

AO-A8
RAS
CAS

-

iN

:--

b~

DQ4--D07

~

RAS
CAS

W

D04--D07
AO-AB
RAS
CAS

W

Hf-

AO-A8
VCC
VSS

ABSOLUTE MAXIMUM RATING (See Note)
Rating
Power Supply Voltage

Symbol

Value

Unit

V

VCC

-1 to +7

Vin'VoU!

-1 to +7

V

Data Out Current per DO Pin

lout

50

mA

Power Dissipation

PD

1.2

W

Operating Temperature Range

TA

Oto +70

°c

Voltage Relative to VSS for Any Pin Except VCC

Storage Temperature Range
-25 to +125
°C
T.tn
NOTE: Permanent device damage mayoccunt ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

MOTOROLA MEMORY DATA
3-220

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit.

MCM84256-MCM8L4256

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 10 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

Logic Low Voltage, All Inputs

VIL

-1.0

-

6.5

V

1

0.8

V

1

Min

Max

Unit

Notes

mA

2

DC CHARACTERISTICS
Characteristic

Symbol

VCC Power Supply Current
MCM84256-70, tRC = 130 ns
MCM84256-80, tRC = 150 ns
MCM84256-10, tRC = 180 ns

ICCI

VCC Power Supply Current (Standby) (RAS=CAS=VIH)
VCC Power Supply Current During RAS Only Refresh Cycles
MCM84256-70, tRC = 130 ns
MCM84256-80, tRC = 150 ns
MCM84256-10, tRC = 180 ns
VCC Power Supply Current During Fast Page Mode Cycle
MCM84256-70, tpc = 40 ns
MCM84256-80, tpc = 45 ns
MCM84256-10, tpc = 55 ns

ICC4

-

160
140
120

ICC2

-

4

ICC3

-

160
140
120

-

120
100
80

-

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V)

MCM84256
MCM8L4256

ICC5

2
400

mA
rnA

2

mA

2,3

rnA

ItA

VCC Power Supply Current During CAS Before fU(S Refresh CyCle
MCM84256-70, tRC = 130 ns
MCM84256-80, tRC = 150 ns
MCM84256-10, tRC = 180 ns

ICC6

rnA

2

VCC Power Supply Current, Battery Backup Mode-MCM8L4256 Only
(tRC = 12511S; CAS = CAS Before fU(S Cycling or 0.2 V; W= VCC -0.2V;
DO = VCC-0.2 V or Open; AO-A8 = VCC-0.2 or 0.2 V) tRAS = min to IllS

ICC7

-

0.6

mA

2,4

Input Leakage Current (VSS'; Yin ,; VCC)

likalll

Output Leakage Current (CAS at Logic I, VSS'; Vout'; vccl

IlkatO)

-20

20

-10

10

ItA
ItA

Output High Voltage (lOH = -5 mAl

VOH

2.4

Output Low Voltage (lOL = 4.2 mAl

VOL

-

0.4

V

Symbol

Max

Unit

Notes

Cin

24

pF

5

-

160
140
120

-

V

CAPACITANCE (f = 1.0 MHz, TA = 25°C VCC = 5 V Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

AO-A8, W, CAS, RAS

InpuVOutput Capacitance
pF
17
DQO-D07
5
CliO
NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
3. Measured with one address transition per page mode cycle.
4. tRAS (max) = 1 I1S is only applied to refresh of battery backup. tRAS (max) = lOllS is applied to functional operating.
5. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = II!o.VI!o.V.

MOTOROLA MEMORY DATA
3-221

..

MCM84256·MCM8L4256

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70o e, Unless Otherwise Noted)

READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)

..

Symbol

MCM84256-70

MCM84256-80

MCM84256-10

Standard

Alternate

Min

Min

Min

Random Read or Write Cycle Time

tRELREL

tRC

130

-

150

-

180

Page Mode Cycle Time

tCELCEL

tpc

40

45

Access Time from RAS

tRELOV

tRAC

70

-

-

55

-

-

80

-

100

ns

Access Time from CAS

tCELOV

tCAC

-

20

-

20

-

25

ns

6,8

Access Time from Column Address

tAVOV

tAA

-

35

-

40

-

50

ns

6,9

Access Time from Precharge CAS

teEHOV

tCPA

-

35

-

40

-

50

ns

6

CAS to Output in Low-Z

tCELOX

teLZ

0

-

0

-

0

-

ns

6

Output Buffer and Tum-Off Delay

tCEHOZ

tOFF

0

20

0

20

0

20

ns

10

Parameter

Transition Time (Rise and Fall)

Max

Max

Unit

Notea

-

ns

5

-

ns

Max

6,7

IT

IT

3

50

3

50

3

50

ns

RAS Precharge Time

tREHREL

tRP

50

-

60

-

70

-

ns

RAS Pulse Width

tRELREH

tRAS

70

10,000

80

10,000

100

10,000

ns

RAS Pulse Width (Fast Page
Mode)

tRELREH

tRASP

70

100,000

80

100,000

100

100,000

ns

RAS Hold Time

tCELREH

tRSH

20

tRELCEH

teSH

70

-

20

CAS Hold Time

80

-

100

CAS Pulse Width

teELCEH

tCAS

20

10,000

20

10,000

25

10,000

ns

RAS to CAS Delay Time

tRELCEL

tRCD

20

50

20

60

25

75

ns

11

tRELAV

tRAD

15

35

15

40

20

50

ns

12

CAS to RAS Precharge Time

teEHREL

teRP

5

-

5

-

10

-

ns

CAS Precharge Time (Page Mode
Cycle Only)

tCEHCEL

tep

10

-

10

-

10

-

ns

RAS to Column Address Delay
Time

25

-

ns
ns

Row Address Setup Time

tAVREL

tASR

0

-

0

-

0

-

ns

Row Address Hold Time

tRELAX

tRAH

10

10

-

15

tAVCEL

tASC

0

0

0

Column Address Hold Time

teELAX

tCAH

15

Column Address Hold Time
Referenced to RAS

tRELAX

tAR

55

Column Address to RAS Lead
Time

tAVREH

tRAL

35

-

-

ns

Column Address Setup Time

-

15
60
40

20
75
50

ns
ns
ns
ns

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An Initial pause of 200 ~ is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all Input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specification lor tRC (min) is used only to Indicate cycle time at which proper operation over the full temperature range (O°C ,; TA ,;
70°C) is assured.
6. Measured with a current load equivalent to 2 TTL (-200 iJA, +4 rnA) loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = O.B V.
7. Assumes that tRCD ,; tRCD (max).
8. Assumes that tRCD;" tRCD (max).
9. Assumes that tRAD 2: tRAD (max).
10. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; " tRCD is
greater than the specified tRCD (max) limit, then access lime is controlled exclusively by tCAC'
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max) limit, then access time Is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
3-222

MCM84256·MCM8L4256

READ AND WRITE CYCLES (Continued)
MCM84256-70

MCM84256-80

MCM84256-10

Alternate

Min

Max

Min

Max

Min

Max

0

-

0

-

0
0

-

ns

Symbol
Parameter

Standard

Read Command Setup Time

tWHCEL

tRCS

0

Read Command Hold Time
Referenced to CAS

tCEHWX

tRCH

0

-

0

Read Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

-

0

Write Command Hold Time
Referenced to CAS

tcELWH

twCH

15

-

15

Write Command Hold Time
Referenced to RAS

tRELWH

twCR

55

-

60

Write Command Pulse Width

ns

13

-

ns

75

-

ns

15

-

20
25

20

-

0

-

0

15

20
75

-

ns

20

-

8
64

ms

twP

15

twLREH

tRWL

20

Write Command to CAS Lead Time

twLCEH

tcWL

20

Data in Setup Time

tOVCEL

tos

0

Data in Hold Time

tCELOX

tOH

15

-

Data in Hold Time Referenced to
RAS

tRELOX

tOHR

55

-

60

-

Refresh Period

tRVRV

tRFSH

-

8
64

8
64

Write Command Setup Time

twLCEL

twcs

0

-

0

-

CAS Setup Time for CAS Before

tRELCEL

tcSR

10

-

10

-

10

CAS Hold Time for CAS Before
RAS Refresh

tRELCEH

tcHR

30

30

tREHCEL

tRPC

0

0

-

30

CAS Precharge to CAS Active
Time
CAS Precharge Time for CAS
Before RAS Counter Test

tcEHCEL

tCPT

40

-

40

-

RAS Refresh

13

20

twLWH

-

25

0

-

ns
ns
ns

14,15

ns

14,15

ns

ns

15,16

ns

0

-

ns

50

-

ns

-

Notes

ns

-

Write Command to RAS Lead Time

MCM84256
MCM8L4256

Unit

ns

CAS Precharge Time
10
15
ns
10
tcEHCEl
tcPN
NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in random write cycles.
15. Early write only (twcs ;, twcs (min)).
16. twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs;' twcs (min), the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is
not satisfied, the condition of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA

3-223

III

MCM84256-MCM8L4256

READ CYCLE
~----------------------tRC----------------------~
~---------------tMS--------------~

•

f 4 - - - - - - - - tCSH ---------------1
f 4 - - - - tRCDI------I---

tASR
ADDRESSES VIHVIL -

'Ii VIHVIL -'--'-i£....li£....l"-i'''--l''--l''--l''--l''--l~
t OFF-+I------i~

DO VOH - ____________ HIGH z ------------<1
(DATA OUT) VOL -

VALID DATA

EARLY WRITE CYCLE
/4----------------------tRC----------------------~

/ 4 - - - - - - - - tRAS -------------+/

~---

tRCD ------;-----tRSH -----i~

CAS VIHVIL -

ADDRESSES VIH VIL -

MOTOROLA MEMORY DATA
3-224

jr------:t.

MCM84256-MCM8L4256

FAST PAGE MODE READ CYCLE

\ 4 - - - - - - - - - - - - t RASP - - - - - - - - - - 1

..
ADDRESSES V IH Vll-

iN

VIHVll-

DO VOH(DATA OUT) VOl-

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

RAS

CAS

iN

VIHVll-

VIHVll-

VIHVll-

~~~~~~~~_~_~~~~_~-+~~~~-+__~~~~~~~~~~

DO VIH(DATA IN) Vil -

-'-""-""-""-r-""-"

1''----------1

MOTOROLA MEMORY DATA
3-225

MCM84256-MCM8L4256

RAS ONLY REFRESH CYCLE
(Wand AS are Don't Care)
~-----------tRC------------~

•
DO VOH (DATAOUT) VOL _ - - - - - - - - - - - - - - HIGHZ

CAS BEFORE RAS REFRESH CYCLE
(iN and AO to A8 are Don't Care)

14---------tRC ---------t
1"'"------,~-----tRAS-----~L1--.....;..--~

tOFF -I00I-_

--------:lI...!>-__________

DO VOH(DATA OUT) VOL - _ _ _ _ _---'"

HIGHZ - - - - - - - - - - -

MOTOROLA MEMORY DATA
3-226

MCM84266-MCM8L4256

HIDDEN REFRESH CYCLE (READ)

•
ADDRESSES VV IH IL -

Vi VIHVIL - ....><.-"--"-+..............",

DQ VOH(DATA OUT) VOL -

---------_+_-<1

HIDDEN REFRESH CYCLE (WRITE)

ADDRESSES VV IH IL -

iN VIHVIL- ~~~~~~~~-4~---~~~~~~~~~~~~~~~~~

DO VIH -

-";:-"'7<"'"7'r"~Ir'l"<"""7\

J r - - - - - - " l ~..._"""',.....,'<""7,....,.,.....,,:_"'7'<_..:-,.;-,.;"7f:"....,......,........,.......,.....

(DATAlN) V IL - -''-''''-''-.....If-................, 1''---------''1""" "'-""~__>L........_"_..............""_.lL...,;"'--'......,.......'__"f....>j'_lL...
~---tDHR----.-j

MOTOROLA MEMORY DATA
3-227

MCM84256-MCM8L4256

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

~--------------tMS------------------~

•

ADDRESSES VIH VIL - .L....;"-'''--'L....>'--'''--''....lL-->L-''--''--''''-->J' 1''-----;--;----'1 "-'''-'''--''-7"'-;-''~....lL-->L-''--''-...>L...
READ CYCLE

VOH_
(DATA OUT)DO VOL
-------- HIGH Z -------i'-t-{I

W

VIHVIL -

WRITE CYCLE
W

VIHVIL -

ftDS
tDH)(
(DATA IN) ~II: ='-loj...................................~'''-'''->t...lo~~
14----tDHR------t

MOTOROLA MEMORY DATA

3-239

MCM91000-MCM9L1000

~ BEFORE US REFRESH

COUNTER TEST CYCLE

•
ADDRESSES VH -

VL - .t...,;1L..l"'-lo'-loj~...Jol.~~~;w...;~l"-_--,_ _ _.;,r "...¥.~~~~I'-l"'-lo'-loj~~

READ CYCLE
000-007 VOH(DATAOUT) VOL - - - - - - - - -

W VHVL - .t...JoL...\r....::t....loL..JoL.~~loL...loL...\t-:V

WRITE CYCLE

W

VHVL-

000-007 VIH(DATA IN) VL -

MOTOROLA MEMORY DATA
3-240

MCM91000- MCM9L1000

CAS clock is active. When the ~ clock transitions to inactive, the output will switch to High Z.

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required forthe internal substrate generator to establish the correct bias vohage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the RAM. During an extended inactive
state (greater than 8 milliseconds with the device powered up),
a wake up sequence of eight active cycles is necessary to ensure proper operation.

WRITE CYCLE
The user can write to the module with either of two cycles:
early write or page mode early write. Early write mode is discussed here, while the page mode write operation is covered in
another section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
(VIU. Minimum active time tRAS and tCAS, and precharge
time tRP apply to write mode, as in the r~ad mode.
An early write cycle is characterized by W active transition at
minimum time twcs before CAS active transition. Data in
(DO) is referenced to CAS in an early write cycle. RAS and
CAS clocks must stay active fortRWL and tCWL, respectively,
after the start of the early write operation to complete the cycle.

ADDRESSING THE RAM
The ten address pins on the module are time multiplexed at
the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 10-bit address fields. A total of twenty address bits, ten
rows and ten columns, will decode one of the 1,048,576 word
locations in the module. AAS active transition is followed by
~ active transition (active- VIL, tRCD minimum)for all read
or write cycles. The delay between RAS and CAS activetransitions, referred to as the multiplex window, gives a system designer flexibility in setting up the external addresses into the
RAM.
The externalCAS signal is ignored until an internalAAS signal is available. This "gate" feature on the external CAS clock
enables the internal ~ line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The muhiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are two other variations in addressing the 1M RAM:
RAS only refresh cycle, and CAS before RAS refresh
cycle. Both are discussed in separate sections that follow.

PAGE MODE CYCLES
Page mode allows fast successive data operations at all
2048 column locations on a selected row of the 1M dynamic
RAM. Read access time in page mode (tCAC) is typically half
the regular RAS clock access time, tRAC. Page mode operation consists of keeping RAS active while toggling ~ between VIH and ~The row is latched by RAS active transition, while each CAS active transition allows selection of a new
column location on the row.
A page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing requirements forthe first cycle are met, ~ transitions to inactive for
minimum of tcp, while RAS remains low (VIL). The second
~ active transition while AAS is low initiates the first page
mode cycle (tpC). Either a read or write operation can be performed in a page mode cycle, subject to the same conditions
as in normal operation (previously described). These operations can be intermixed in consecutive page mode cycles and
performed in any order. The maximum number of consecutive
page mode cycles is limited bytRASP. Page mode operation is
ended when AAS transitions to inactive, coincident with or following ~ inactive transition.

READ CYCLE
The DRAM may be read with either the "normal" random
read cycle or the page mode read cycle. The normal read cycle
is outlined here, while the page mode is discussed in a separate section.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired word location. The write (W) input level must be
high (VIH), tRCS (minimum) before the CAS active transition,
to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The internal clocks are linked in such a manner that the read access
time ofthe device is independent ofthe address muhiplex window. However, ~ must be active before or at tRCD maximum to guarantee valid data out (DO) at tRAC (access time
from RAS active transition). Hthe tRCD maximum is exceeded, read access time is determined by the CAS clock active
transition (!CAC).
The AAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. W must remain high throughout the cycle, and for time
tRRH or tRCH after AAS or ~ inactive transition, respe~
tively, to maintain the data althat bit location. Once ~ tranSItions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitryforthe next active
cycle. Data out (DO) is valid, but not latched, as long as the

REFRESH CYCLES
The dynamic RAM design is based on capacitor charge storage for each bit in the array. This charge degrades with time
and temperature, thus each bit must be periodically refreshed
(recharged) to maintain the correct bit state. Words in the
MCM91 000 require refresh every 8 milliseconds, while refresh
time for the MCM9L 1000 is 64 milliseconds.
Refresh is accomplished by cycling through the 512 rowaddresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM91000, and 124.8 microseconds
for the MCM9L1000. Burst refresh, a refresh of all 512 rows
consecutively, must be performed every 8 milliseconds on the
MCM91 000 and 64 milliseconds on the MCM9L1000.
A normal read, write, or read-write operation to the RAM will
refresh all the words associated with the particular row decoded. Three other methods of refresh, n-s-only refresh,
CAS before RAS refresh, and hidden refresh are available
on this device for greater system flexibility.

MOTOROLA MEMORY DATA
3-241

•

MCM91000-MCM9L1000

~Only Refresh
~-only refresh consists of~ transition to active,latch-

ing the row address to be refreshed, while CAS remains high
(VIH)throughoulthe cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.

•

CAS Before ~ Refresh
CAS before ~ refresh is enabled by bringing CAS active
before~. This clock order actives an internal refresh counterthat generates the row address to be refreshed. External address lines are ignored during the automatic refresh cycle. The
output buffer remains althesame state it was in during the previous cycle (hidden refresh).
Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding ~ active at the
end of a read or write cycle, while ~ cycles inactive fortRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before ~ refresh from a cycle in
progress (see Figure 1).
eA! BEFORE ~ REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CAS before RlS refresh counter test. This refresh count-

MEMORY CYClE

ertest is performed with read and write operations. During this
test, the internal refresh counter generates the row address,
while the external address supplies the column address. The
entire array is refreshed after 512 test cycles, as indicated by
the check data written in each row. See CAS before AAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as follows:
1. Write ·O"s into all memory cells (normal write mode).
2. Select a column address, and read ·0" out of the cell by
performing CAS before RlS refresh counter test,
read cycle. Repeat this operation 512 limes.
3. Select a column address and write "I" into the cell by
performing CAS before RiS refresh counter test,
write cycle. Repeat this operation 512 times.
4. Read "l"s (normal read mode), which were written at
step 3.
5. Repeat steps Ito 4 using complement data.

REFRESH CYClE

REFRESH CYCLE

VALlO DATA-OUT

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)

Motorola Memory Prefix

1__9_1000--,!,""
___M_CM_
Speed (70 = 70 ns, 80 = 80 ns, 10 = 100 ns

Part Number

Package (L = SIP, LH = Low Height SIP, S = 4-Layer SIMM,
AS =2-Layer SIMM, SG =Gold Pad SIMM)
Full Part Numbers- MCM91000AS70
MCM91000AS80
MCM91000AS10
MCM9Ll000AS70
MCM9L1000ASBO
MCM9L1OOOASI 0

MCM91000s70
MCM91000SB0
MCM91000s10

MCM91000SG70
MCM91000SGBO
MCM91000SG10

MCM91000L70
MCM91000L80
MCM91OOOL10

MCM9L1000s70
MCM9Ll000S80
MCM9L1000s10

MCM9L l000SG70
MCM9L l000SG80
MCM9L1OOOSGI 0

MCM9Ll000L70 MCM9L l000LH70
MCM9L l000LBO MCM9L l000LH80
MCM9LlOOOLI0 MCM9Ll000LH10

MOTOROLA MEMORY DATA

3-242

MCM91000LH70
MCM91000LH80
MCM91000LH10

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

Advance Information

MCM91430
MCM9L1430

1Mx9 Bit Dynamic Random
Access Memory Module

•

The MCM91430 and MCM9L1430 are 9M dynamic random access memory
(DRAM) modules organized as 1,048,576 x 9 bits. The modules are 30-lead
single-in-line memory modules (SIMM) consisting of two MCM54400AN and one
MCM511000A DRAMs housed in a 20/26 J-Iead small outline package (SOJ)
and mounted on a substrate along with a 0.22 IlF (min) decoupling capacitor
mounted adjacent to each DRAM. The MCM54400AN is a CMOS high speed,
dynamic random access memory organized as 1,048,576 four-bit words and
fabricated with CMOS silicon-gate process technology.
•
•
•
•
•
•
•
•

•
•
•

•

•

•
•
•

Three-State Data Output
Early-Write Common I/O Capability
Fast Page Mode Capability
TIL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh:
MCM91430 = 16 ms (Max)
MCM9L1430 = 128 ms (Max)
Consists of Two 4M and One 1M DRAMs and Three 0.22 IlF (Min) Decoupling
Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access TIme (tRAC):
MCM91430-70 =70 ns (Max)
MCM91430-80 =80 ns (Max)
MCM91430-10 = 100 ns (Max)
Low Active Power Dissipation:
MCM91430-70 = 1.54 W (Max)
MCM91430-80 = 1.32 W (Max)
MCM91430-10 = 1.16 W (Max)
Low Standby Power Dissipation:
TIL Levels = 33 mW (Max)
CMOS Levels (MCM91430) = 16.5 mW (Max)
(MCM9L1430) = 3.3 mW (Max)
CAS Control for Eight Common I/O Lines
CAS Control for Separate I/O Pair
Available in Edge Connector (MCM91430S)
PIN NAMES

5 PACKAGE
slMMMODULE
CAsE839A

3D-PIN
SINGLE IN-LINE PACKAGE
(TOP VIEW, MCM91430SI9L1430S)

Vee
CAS
000
AO
A1
DQ1
A2
AS
Vss
0Q2
A4
AS
DQ3
AS
A7
DQ4

AS
AS
HC

(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)

~[~l

Vss
DQ6
HC
DQ7

(22)
(23)
(24)
(25)

~(26)

AO-A9 ..................... Address Inputs
DOO-D07 ............... Data Input/Output
D8 ............................. Data Input
08 . . . . . . . . . . . . . . . . . . . . . . . . . .. Data Output
CAS ............... Column Address Strobe
RAS .................. Row Address Strobe
W ....................... ReadlWrite Input
CAS8 .............. Column Address Strobe
VCC ........................ Power (+5 V)
VSS .............................. Ground
NC ........................ No Connection

...!!Mi (27)

CASS (28)
08 (29)
Vee (30)

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
3-243

0

0
'0
0
0

0

Ei

0

MCM9143O. MCM9L1430

FUNCTIONAL BLOCK DIAGRAM

.--::>

DQO--D03 - - - - - - - - - - - 1 DO

•

AO-A9

1-----1 RAS
-

CAS

-

D04-D07

W

~j

--+--1-+--1

CAS -----I~......,H

W-----If--4>---1
AO-A9

--+--T""""""1L

08
RAS==~==~
D8
CAS8

-------I

D

1---1 CAS

~
vcc

AD-A9

J

o tRAS

t-

Wr--

------'b1

VSS------------~

ABSOLUTE MAXIMUM RATING (See Note)
Rating
Power Supply Voltage

Symbol

Value

Unit

VCC

-1 to +7

V

Vin, Vout

-1 to +7

V

Data Out Current per DQ Pin

lout

50

mA

Power Dissipation

PD

2.0

W

Operating Temperature Range

TA

oto +70

'c

Voltage Relative to VSS for Any Pin Except VCC

Storage Temperature Range
T sto
-25 to +125
'C
NOTE: Permanent deVice damage may occur If ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

MOTOROLA MEMORY DATA
3-244

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit.

MCM91430-MCM9L1430

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ±1 0%, TA =0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

UnH

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

V

1

Vil

-1.0

-

6.5

Logic Low Voltage, All Inputs

0.8

V

1

Symbol

Min

Max

Unit

Noles

mA

-

2

280
240
210

DC CHARACTERISTICS
Characteristic
VCC Power Supply Current
MCM91430-70, tRC = 130 ns
MCM91430-80, tRC = 150 ns
MCM91430-10, tRC = 180 ns

ICCI

VCC Power Supply Current (Standby) (RAS = CAS = V, H)

ICC2

VCC Power Supply Current During RAS Only Refresh Cycles
MCM91430-70, tRC = 130 ns
MCM91430-80, tRC = 150 ns
MCM91430-1 0, tRC = 180 ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle
MCM91430-70, tpc = 45 ns
MCM91430-80, tpc = 50 ns
MCM91430-10, tpc = 60 ns

ICC4

-

280
240
210

-

200
170
150

-

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V)

MCM91430
MCM9L1430

-

ICC5

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM91430-70, tRC = 130 ns
MCM91430-80, tRC = 150 ns
MCM91430-10, tRC = 180 ns

ICC6

VCC Power Supply Current, Batte~ck~od&-MCM9L 1430 Only
(tRAC =..1.25118; tRAS = 1 118; CAS = CAS Before RAS Cycle or 0.2 V;
AQ-A9, W, DO = VCc-O.2 V or 0.2 V)

6

3
0.6

mA

2

mA

2,3

mA
mA

2

0.9

mA

2,4

-30

30

~

-10

10

~

VOH

2.4

V

VOl

-

0.4

V

Symbol

Max

UnH

Notes

Cin

25

pF

5

17

pF

5

-

-

280
240
210

ICC7

-

Input Leakage Current (VSS S Vin" VCC)

Ilko{/)

Output Leakage Current (CAS at Logic I, VSS " Vout S VCC)
Output High VOltaQe (IOH = -5 mAl

Ilkg/OJ

Output Low Voltage (IOL = 4.2 mAl

mA

CAPACITANCE (f = 1.0 MHz TA = 25°C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter
AQ-A9, W, CAS, RAS

Input Capacitance

08, CAS8
Input/Output Capacitance

DQo-D07

CliO

17

pF

5

08

Cout

17

pF

5

Output Capacitance (CAS = VIH to Disable Output)

NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
3. Column address can be changed once or less while RAS = VIL and CAS = VIH.
4. tRAS (max) = 1 Ils is only applied to refresh of battery backup. tRAS (max) = 10 118 is applied to functional operating.
5. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = 11J.t//},v.

MOTOROLA MEMORY DATA

3-245

•

MCM91430-MCM9L1430

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70o e, Unless Otherwise Noted)

READ AND WRITE CYCLES (See Notes t, 2, 3, and 4)

Parameter

II

MCM91430-70
MCM9L 1430-70

Symbol
Standard

Alternate

Min

Max

-

Random Read or Write Cycle Time

tRELREL

tRC

130

Page Mode Cycle lime

tcELCEL

tpc

45

Access Time from RAS

tRELQV

tRAC

-

70

Access Time from CAS

tCELQV

tCAC

-

20

Access Time from Column Address

tAVQV

tAA

-

Access Time from Precharge CAS

tCEHQV

tCPA

CAS to Output in Low-Z

tCELQX

tCLl

Output Buffer and Turn-Off Delay

tCEHQZ

IT

Transition Time (Rise and Fall)

MCM91430-80
MCM9L1430-80

MCM91430-10
MCM9L1430-10

Min

Max

Min

Max

150

-

180

50

-

60

-

-

80

Unit

Notes

ns

5

ns

-

100

ns

6,7

20

-

25

ns

6,8

35

-

40

-

50

ns

6,9

-

40

-

45

-

55

ns

6

-

-

ns

6

toFF

a
a

20

ns

10

tT

3

50

ns

-

ns

-

20

a
a

20

a
a

50

3

50

3

RAS Precharge Time

tREHREL

tRP

50

-

60

RAS Pulse Width

tRELREH

tRAS

70

10,000

80

10,000

100

10,000

ns

RAS Pulse Width (Fast Page
Mode)

tRELREH

tRASP

70

100,000

80

100,000

100

100,000

ns

-

-

70

RAS Hold Time

tcELREH

tRSH

20

CAS Hold lime

tRELCEH

tCSH

70

-

80

CAS Precharge to RAS Hold lime

tcEHREH

tRHCP

40

-

45

-

CAS Pulse Width

tCELCEH

tCAS

20

10,000

20

10,000

25

10,000

RAS to CAS Delay lime

tRELCEL

tRCD

20

50

20

60

25

75

ns

11

tRELAV

tRAD

15

35

15

40

20

Sa

ns

12

CAS to RAS Precharge Time

tCEHREL

tCRP

5

-

5

CAS Precharge Time (Page Mode
CycleOnly)

tCEHCEL

tcp

10

-

10

RAS to Column Address Delay
Time

Row Address Setup Time

tAVREL

tASR

a

Row Address Hold Time

tRELAX

tRAH

10

Column Address Setup Time

tAVCEL

tASC

a

Column Address Hold lime

tCELAX

tCAH

15

-

Column Address Hold lime
Referenced to RAS

tRELAX

tAR

55

-

20

25

-

ns

100

-

ns

55

-

ns

a

-

a

-

10

-

15

-

a

a

15

-

20

60

-

75

-

-

5
10

ns

ns
ns
ns
ns
ns
ns
ns

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 ~ is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate speCification, all input signals must
transition between VIH and VIL (or between VIL and VI H) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range
(O°C ,; T A ,; 70°C) is assured.
6. Measured with a current load equivalenllo 2 TTL (-200 IlA, +4 mAl loads and 100 pF with the data outputtrip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD s tRCD (max).
8. Assumes that tRCD "tRCD (max).
9. Assumes that tRAD " tRAD (max).
10. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC'
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max) limit, then access time is controlled exclusively by tM'

MOTOROLA MEMORY DATA
3-246

MCM91430-MCM9L1430

READ AND WRITE CYCLES (Continued)
Symbol
Parameter

MCM9143D-70
MCM9LI43D·70

MCM9143D-BD
MCM9L1430-80

Standard

Alternate

Min

Max

Min

tAVREH

tRAL

35

-

40

MCM9143D-l0
MCM9LI43D-l0

Unit

Max

Min

Max

50

-

ns

Notes

Read Command Setup Time

twHCEL

tRCS

0

-

0

-

0

-

ns

Read Command Hold Time
Referenced to CAS

tCEHWX

tRCH

0

0

-

0

-

ns

13

Read Command Hold Time
Referenced to RAS

tREHWX

tRRH

0

0

-

0

-

ns

13

Write Command Hold Time
Referenced to CAS

tCELWH

twCH

15

15

-

20

-

ns

Write Command Hold Time
Referenced to RAS

tRELWH

twCR

55

60

75

ns

20

-

0

-

0

15

-

20

Column Address to RAS Lead
Time

Write Command Pulse Width

twLWH

twP

15

Write Command to RAS Lead Time

twLREH

tRWL

20

Write Command to CAS Lead Time

twLCEH

tcWL

20

Data in Setup Time

tOVCEL

tos

0

Data In Hold Time

tcELOX

tOH

15

-

Data in Hold Time Referenced to
RAS

tRELOX

tOHR

55

-

60

-

75

-

Refresh Period

tRVRV

tRFSH

-

16
128

-

16
128

-

16
128

ms

MCM91430
MCM9L1430

15
20

20
25
25

ns
ns
ns
ns

14,15

ns

14,15

ns

Write Command Setup Time

twLCEL

twcs

0

-

0

0

-

ns

tRELCEL

tCSR

5

5

-

5

-

ns

CAS Hold Time for CAS Before
RAS Refresh

tRELCEH

tcHR

15

15

-

20

-

ns

CAS Precharge to CAS Active
Time

tREHCEL

tRPC

0

0

-

0

-

ns

CAS Precharge Time for CAS

tcEHCEL

tCPT

40

-

-

CAS Setup Time for CAS Before
RAS Refresh

40

-

50

-

ns

Before RAS Counter Test

15,16

CAS Precharge Time
10
15
ns
10
tCPN
tcEHCEL
NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in random write cycles.
15. Early write only (twcs "twcs (min)).
16. twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs" twcs (min), the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is
not satisfied, the condition of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
3-247

•

MCM91430-MCM9L1430

READ CYCLE
tRC
tRAS

..

RAS vIHVILtCSH
tRCD

tASR
ADDRESSES VIHVIL -

IN VIHVIL tOFF
DQ(DATAOUT) VOHVOL -

HIGHZ

VAUDDATA

EARLY WRITE CYCLE

tRC
tRAS
RAS VIHVIL tRCD

ADDRESSES VIH VIL -

IN VIHVIL -

-"'-"'->r-'''--'.......'-'''-''-+--+--I-------''f-''-+-''--''--''--''--''-'''-''--'''--'''--''-

tD~

DQ(DATAIN)

tDH}z

~:: =....,.;-"7«Xx~y""X'X~XX""'XM-VA-LlDDA1:-A
~
tDHR
-

MOTOROLA MEMORY DATA
3-248

XXXXXXXXXXXXX>

MCM91430- MCM9L1430

FAST PAGE MODE READ CYCLE

•

ADDRESSES VIH VIL -

W VIHVIL -

DQ (DATA OUT) VOH-

.L-;"-',,-->~""""'-'"

------------HIX

VOL-

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

ADDRESSES VIH VIL -

W VIHVIL-~~~~~~~~--~~~~~~--r__r~~~~_r~r_~~~~~~~~~

MOTOROLA MEMORY DATA

3-249

MCM91430. MCM9L1430

RAS ONLY REFRESH CYCLE
Wand A9 are Don't Care
~------------------tRC------------------------~

14---------------tRAS---------------i

RAS VIH -

•

Jr------"L

-----..,,,L

VIL-

OQ (OATA OUT) VOH VOL -

- - - - - - - - - - - - - - - HIGHZ - - - - - - - - - - - - -

CAS BEFORE RAS REFRESH CYCLE
(AO to A9 are Don't Care)
~----------------tRC--------------~

~----------tRAS-------·

1---------~

~--------_"L

CAS VIHVIL - ____----I
tOFF-+---~

DQ(OATAOUT) VOHVOL -

HIGHZ - - - - - - - - - -

---------......:l[""

MOTOROLA MEMORY DATA
3-250

MCM91430-MCM9L1430

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

~--------------t~s------------------~ ~~~

ADDRESSES VIH VIL -

•
~~"--lo.....:.L....l."--l<:......lo<~~~..lI.....u l''------;-.,..----Jr ,,~~..lI..*'*_*_~~~"--l....

READ CYCLE
DO VOH(DATA OUT) VOL _ - - - - - - - - HIGHZ

W

VIHVIL - ......,.............,.'-"'-""'....>l.-"--"'-"""-..loL...,

WRITE CYCLE

W

DO
(DATA IN)

VIHVIL- -"'-"""-..loL..~~"--lo.....:.~~~~~_ _~~_ _ _~~"--l~~~~-""'~..lI..~

f

tDS

~~~ =<~XX~X'1r7":"XX~XX~X~XX"7r?X

tDH=j

VALID DATA

MOTOROLA MEMORY DATA

3-251

](XXXXXXXXXXX)

MCM9143O-MCM9L1430

DEVICE INITIALIZATION

..

On power-up an initial pause of 200 microseconds is required forthe internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the module. During an extended inactive state (greater than 8 milliseconds with the device powered
up), a wake up sequence of eight active cycles is necessary to
ensure proper operation.
ADDRESSING THE RAM
The ten address pins on the device are time multiplexed at
the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate 10-bit address fields. A total of twenty address bits, ten
rows and ten columns, will decode one of the 1,048,576 word
locations in the device. RAS active transition is followed by
CAS active transition (active = VIL, tBCD minimum) for all read
or write cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system
designer flexibility in setting up the external addresses into the
RAM.
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the module:
RAS only refresh cycle, CAS before RAS refresh cycle,
and page mode. All three are discussed in separate sections
that follow.
READ CYCLE
The DRAM may be read with either a "normal" random read
cycle or a page mode read cycle. The normal read cycle is outlined here, while the page mode cycle is discussed in a separate section.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (W) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex
window. CAS controls read access time: CAS must be active
before or at tRCD maximum to guarantee valid data out (DQ)
at tRAC (access time from RAS active transition). If the tRCD
maximum is exceeded, read access time is determined by the
CAS clock active transition (tCAC)'
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cycle. W must remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data althat bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitryforthe next active
cycle. DQ is valid, but not latched, as long as the CAS clock is
active. When the CAS clock transitions to inactive, the output

will swtlch to High Z (three-state) tOFF after the inactive transition.
WRITE CYCLE
The user can write to the DRAM with either an early write or
page mode early write cycle. Early write mode is discussed
here, while page mode write operations are covered in a separate section .
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
(VuJ Early write mode is distinguished by the active transition
of W, with respect to CAS. Minimum active time tRAS and
tCAS, and precharge time tRP apply to write mode, as in the
read mode.
An early write cycle is characterized by Wactive transition at
minimum time twcs before CAS active transition. Data in
(DQ) is referenced to CAS in an early write cycle. RAS and
CAS clocks must stay active for tRWL and tCWL, respectively,
after the start of the early write operation to complete the cycle.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
1024 column locations on a selected row of the module. Read
access time in page mode (tCAC) is typically half the regular
RAS clock access time, tRAC' Page mode operation consists
of keeping RAS active while toggling CAS between VIH and
~ The row is latched by RAS active transition, while each
CAS active transition allows selection of a new column location on the row.
A page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for
minimum tcp, while RAS remains low (VIL). The second CAS
active transition while RAS is low initiates the first page mode
cycle (tPC)' Either a read or write operation can be performed
in a page mode cycle, subject to the same conditions as in normal operation (previously described). These operations can
be intermixed in consecutive page mode cycles and performed in any order. The maximum number of consecutive
page mode cycles is limited by tRASP' Page mode operation
is ended when RAS transitions to inactive, coincident with or
following CAS inactive transition.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically
refreshed (recharged) to maintain the correct bit state. Bits in
the MCM91430 require refresh every 16 milliseconds, while
refresh time for the MCM9L1430 is 128 milliseconds.
This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is
addressed. Distributed refresh implies a row refresh every
15.6 microseconds for the MCM91430, and 124.8 microseconds for the MCM9L 1430. Burst refresh, a refresh of all 1024
rows consecutively, must be performed every 16 milliseconds
on the MCM91430 and 128 milliseconds on the MCM9L1430.
A normal read or write operation to the RAM will refresh all
the bits associated with the particular row decoded. Three other methods of refresh, RAS-only refresh, CAS before RAS
refresh, and hidden refresh are available on this device for
greater system flexibility.

MOTOROLA MEMORY DATA

3-252

MCM91430-MCM9L1430

RA5-0nly Refresh
RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(VIH) throughoullhe cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.
CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order actives an internal refresh counterthat generates the row address to be refreshed. External address lines are ignored during the automatic refresh cycle. The
output buffer remains at the same state it was in during the previous cycle (hidden refresh). IN must be inactivefortimetwRP
before and time !wRH after RAS active transition to prevent
switching the device into a test mode cycle.
Hidden Refresh
Hidden refresh aliows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles Inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). IN is subject to the same conditions

MEMORY CYCLE

DO -HIGH Z-t----{

with respect to RAS active transition (to prevent test mode
cycle) as in CAS before RAS refresh.
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CAS before RAS refresh counter test. This refresh
counter test is performed with read and write operations. During this test, the internal refresh counter generates the row
address, while the external address supplies the column
address. The entire array is refreshed after 512 test cycles, as
indicated by the check data written in each row. See CAS
before RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:
1. Write "O"s into ali memory celis (normal write mode).
2. Select a column address, and read "0" out of the celi by
performing CAS before RAS refresh counter test,
read cycle. Repeat this operation 512 times.
3. Select a column address and write "1" into the celi by
performing CAS before RAS refresh counter test,
write cycle. Repeat this operation 512 times.
4. Read "1"s (normal read mode), which were written at
step 3.
5. Repeat steps 1 to 4 using complement data.

REFRESH CYCLE

VAliD DATA·OUT

Figure 1. Hidden Refresh Cycle

MOTOROLA MEMORY DATA
3-253

REFRESH CYCLE

•

MCM91430-MCM9L1430

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory Prefix

~

Speed (70 = ns, 80 = 80 ns,
10 =100 ns)

Part Number

Package (S = SIMM)

Full Part Numbers-MCM91430S70
MCM91430sao
MCM91430S10

MCM9L1430570
MCM9L1430S80
MCM9L1430S10

MOTOROLA MEMORY DATA
3-254

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM94000
MCM9L4000

4Mx9 Bit Dynamic Random
Access Memory Module
The MCM94000S is a 36M, dynamic random access memory (DRAM) module
organized as 4,194,304 x 9 bits. The module is a 30-lead single-in-line memory
module (SIMM) consisting of nine MCM54100A DRAMs housed in a 20/26 J-Iead
small outline packages (SOJ) mounted on a substrate along with a 0.22 !iF (min)
decoupling capacitor mounted under each DRAM. The MCM54100A is a CMOS
high speed, dynamic random access memory organized as 4,194,304 one-bit
words and fabricated with CMOS silicon-gate process technology.
•
•
•
•
•
•
•
•

•
•
•

•

•

•
•
•

Three-State Data Output
Early-Write Common 1/0 Capability
Fast Page Mode Capability
TIL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
1024 Cycle Refresh:
MCM94000 = 16 ms
MCM9L4000 = 128 ms
Consists of Nine 4M x 1 DRAMs and Nine 0.22 !iF (Min) Decoupling Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access Time (tRAC)
MCM94000S-80 = 80 ns (Max)
MCM94000S-10 = 100 ns (Max)
Low Active Power Dissipation:
MCM94000S-80 and MCM9L4000S-80 = 4.95 W (Max)
MCM94000S-10 and MCM9L4000S-10 =4.21 W (Max)
Low Standby Power Dissipation:
TIL Levels = 99 mW (Max)
CMOS Levels (MCM94000) = 50 mW (Max)
(MCM9L4000) = 20 mW (Max)
CAS Control for Eight Common 1/0 Lines
CAS Control for Separate 1/0 Pair
Available in Edge Connector (MCM94000S) or Low Height Pin Connector
(MCM94000LH)

•

SPACKAGE
SIMMMODULE
CASE839B

aD-PIN
SINGLE IN-LINE PACKAGE
(TOP VIEW, MCM94000S/9L4000S)

0
D~: !~l ~D 0
0
00
0
c~H~S9 0
Vcc

CAS
DQO

(1)
(2)
(3)

,.---J§I"0

AO (4)

A2(7))
A3 (8) ~

Vss (9)

DQ2
A4 (10)
(11)
AS (12)

~~D

DQ3
AS (13)
(14)
A7 (15)
DQ4
(16)
AS (17)

A9 (18)

AtO(t9)
D~
(20)

W (21)

VSS(22)
006
(23)
NC (24)
DQ7 (25)
Jl! (26)

DB (29)
Vee (30)

P 0

PIN NAMES
AD-Al0 .................... Address Inputs
000-007 ............... Data Input/Output
08 ............................. Data Input
08 ........................... Data Output
CAS ............... Column Address Strobe
RAS .................. Row Address Strobe
W ........................ ReadiWrite Input
CAS8 .............. Column Address Strobe
VCC ........................ Power (+5 V)
VSS .............................. Ground
NC ......................... No Connection

MOTOROLA MEMORY DATA
3-256

MCM94000-MCM9L4000

FUNCTIONAL BLOCK DIAGRAM

..

DQO

1

~

rr- l- l - I-

001

~

D

~
~ l-

004

1
,..--

I-- Vi

~
~

D

~

r-~

RAS

t-- CAS

r-H-

1

oJ

AIl-Al0

-f--

1

oJ

005

1

RAS

........

I-- CAS
t-- Vi

,,"""-

~ Ao-Al0
~

l- I-

. . . . r--

~
~

oJ

D06

l

1

::f\
........

I-- CM
I-- Vi

""""-

........ f - -

D

~
~ l-

........ 1- I-

~
-

Ao-Al0

D

oj

AIl-Al0
RAS
CAS

Vi

-tI-

oJ

007

I
........
,,"""-

I-- CM
Vi

-

oj

liAS

r--H-

~ RAS

~ AO-Al0
~ RAS

D

AIl-Al0

I-- CAS
I-- Vi

~IDQ3

RAS

f-n-..

Ao-Al0

D

oJ

I-- CM
I--Vi

HIDQ2

D

AO-Al0

I-r- ......

liAS

-

Vi

~r1
D8

D

~
~

-~

oj

Ao-Al0
CAS

b~OrD

AO-Al0
RAS

CAS

Vi

~I--

VCC

Vss

MOTOROLA MEMORY DATA
3-266

as

MCM94000-MCM9L4000

ABSOLUTE MAXIMUM RATING (See Note)
Rating

Symbol

Value

Unit

VCC

-1 to +7

V

Power Supply Voltage
Voltage Relative to VSS for Any Pin Except VCC

Yin, Vout

-1 to +7

V

Data Out Current per DO Pin

lout

50

mA

Power Dissipation

PD

5.4

W

Operating Temperature Range

TA

oto +70

°C

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit.

Storage Temperature Range
-25 to +125
°C
Tsta
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA = 0 to 70 o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

-

6.5

V

1

Logic Low Voltage, All Inputs

VIL

-1.0

-

O.S

V

1

Max

Unit

Notes

mA

2

DC CHARACTERISTICS
Characteristic

Symbol

VCC Power Supply Current
MCM94000-S0, tRC = 150 ns
MCM94000-1 0, tRC = ISO ns

ICCI

VCC Power Supply Current (Standby) (RAS=CAS=VIH)

ICC2

VCC Power Supply Current During RAS Only Refresh Cycles
MCM94000-S0, tRC = 150 ns
MCM94000-1 0, tRC = ISO ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle
MCM94000-S0, tpc = 45 ns
MCM94000-1 0, tpc = 55 ns

ICC4

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V)

MCM94000
MCM9L4000

Min

--

ICC5

VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM94000-S0, tRC = 150 ns
MCM94000-1 0, tRC = ISO ns

ICC6

VCC Power Supply Current, Battery Backup Mode-MCM9L4~0 Only
(tRC = 125 ~s; CAS = CAS Before RAS Cycling or 0.2 V; W = VCC - 0.2 V;
DO = VCC-0.2 V, 0.2 V or Open; AO-Al0 = VCC -0.2 VorO.2 V)
tRAS = Min to 1 ~s

ICC7

900
765
IS

mA

2

mA

2

900

-

765

-

540
450

-

9
3.6

-

900

-

mA

mA
mA

2

765
4.5

mA

Input Leakage Current (VSS'; Vin'; Vccl

Ilkall\

-90

90

~

Output Leakage Current (CAS at Logic 1, VSS'; V out '; VCC)

Ilka(O)

-20

20

Output High Voltage (IOH = -5 mAl

VOH

2.4

-

~
V

Output Low Voltage (lOL = 4.2 mAl

VOL

-

0.4

V

Symbol

Max

Unit

Cin

60

pF

3

7

pF

3

CAPACITANCE (f = 1 0 MHz TA = 25°C VCC = 5 V Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

AO-Al0, W, CAS, RAS
DS, CASS

InpuVOutput Capacitance

Notes

DOG-D07

CliO

15

pF

3

OS

Cout

10

pF

3

Output Capacitance (CAS = VIH to Disable Output)

NOTES:
1. All voltages referenced to VSS'
2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
3. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = II!.VI!.V.

MOTOROLA MEMORY DATA
3-257

MCM94000-MCM9L4000

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70°C, Unless Otherwise Noted)

READ AND WRITE CYCLES (See Notes 1, 2, 3 and 4)

•

MCM941JOO.8O

MCM94000-10

Standard

Alternate

Min

Max

Min

Max

Random Read or Write Cycle Time

tRELREL

tRC

150

-

180

Page Mode Cycle Time

tCELCEL

tpc

50

-

60

Access Time from RAS

tRELQV

tRAC

tCELQV

teAC

Access Time from Column Address

tAVQV

tAA

-

80

Access Time from CAS

40

Access Time from Precharge CAS

teEHQV

tCPA

-

45

CAS to Output in Low-Z

tCELQX

tell

0

Output Buffer and Turn-Off Delay

teEHQZ
t,-

tOFF

0

20

Transition Time (Rise and Fall)

t,-

3

50

RAS Precharge Time

tREHREL

tRP

60

-

70

RAS Pulse Width

tRELREH

tRAS

80

10,000

100

10,000

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

80

200,000

100

200,000

RAS Hold Time

tCELREH

tRSH

20

25

CAS Hold Time

tRELCEH

teSH

80

-

CAS Pulse Width

teELCEH

tCAS

20

10,000

RAS to CAS Delay Time

tRELCEL

tRCD

20

tRELAV

tRAD

CAS to RAS Precharge Time

teEHREL

CAS Precharge Time

teEHCEL

Row Address Setup Time

Parameter

Symbol

20

-

Unit

Notes

-

ns

5

-

ns

-

100

ns

6,7

25

ns

6,8

-

50

ns

6,9

55

ns

6

-

ns

6

0

20

ns

10

3

50

ns

0

-

ns
ns
ns

-

ns

tOO

-

ns

25

10,000

ns

SO

25

75

ns

11

15

40

20

50

ns

12

tCRP

5

-

ns

to

-

10

tcp

10

-

ns

tAVREL

tASR

0

-

0

-

ns

Row Address Hold Time

tRELAX

tRAH

10

-

t5

-

ns

Column Address Setup Time

tAVCEL

tASC

0

-

0

ns

Column Address Hold Time

tCELAX

tCAH

15

20

Column Address Hold Time Referenced to RAS

tRELAX

tAR

SO

75

Column Address to RAS Lead Time

tAVREH

tRAL

40

-

-

50

-

ns

RAS to Column Address Delay Time

ns
ns

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 ~ is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input Signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. AC measurements t,- = 5.0 ns.
5. The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (O°C ,;; TA';;
70°C) is assured.
S. Measured with a current load equivalent to 2 TTL (-200 JlA, +4 rnA) loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD';; tRCD (max).
8, Assumes that tRCD " tRCD (max),
9. Assumes that tRAD " tRoAD (max),
10. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11, Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is
greater than the specified tRCD (max) lim~, then access time is controlled exclusively by tCAC'
12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is
greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA'

MOTOROLA MEMORY DATA
3-258

MCM94000-MCM9L4000

READ AND WRITE CYCLES (Continued)
Symbol
Parameter

MCM94000-80

MCM9400D-l0

Min

Min

Max

a
a
a

-

ns
ns

13

-

ns

13

20

-

ns

75

-

ns

20

-

ns

25

-

ns
ns

14,15

20

-

ns

14,15

75

-

ns

-

16
128

ms

Standard

Alternate

Read Command Setup Time

tWHCEL

tRCS

Read Command Hold Time Referenced to CAS

tCEHWX

tRCH

Read Command Hold Time Referenced to RAS

tREHWX

tRRH

a
a
a

Write Command Hold Time Referenced to CAS

tCELWH

twCH

15

Write Command Hold Time Referenced to RAS

tRELWH

twCR

60

Write Command Pulse Width

twLWH

twP

15

Write Command to RAS Lead Time

tWLREH

tRWL

20

-

Write Command to CAS Lead Time

tWLCEH

tCWL

20

-

25

Data in Setup Time

tDVCEL

tDS

a

a

Data in Hold Time

tCELOX

tOH

15

Data in Hold Time Referenced 10 RAS

IRELOX

tOHR

60

-

tRVRV

tRFSH

16
128

Refresh Period

MCM94000
MCM9L4000

-

Write Command Setup Time

tWLCEL

twcs

a

CAS Setup Time for CAS Before RAS Refresh

tRELCEL

tCSR

5

CAS Hold Time for CAS Before RAS Refresh

tRELCEH

tCHR

15

CAS Precharge to CAS Active Time

tREHCEL

tRPC

a

Max

-

-

Unit

ns

-

a

-

ns

-

10

-

ns

-

ns

20

a

Notes

15,16

ns

CAS Precharge Time for CAS Before RAS Counter Test tcEHCEL
40
50
ns
tCPT
NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are referenced to CAS leading edge in random write cycles.
15. Early write only (twcs " twcs (min)).
16. twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs "twcs (min), the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is
not satisfied, the condition of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
3-259

•

MCM94000. MCM9L4000

READ CYCLE

..
ADDRESSES VIHVIL -

iii

VIHVIL - L...)."--'''--'~''--'''--'''--'''--'''--'~

DO VOH- _ _ _ _ _ __

(DATA OUD VOL -

EARLY WRITE CYCLE
~-----------tRC-----------~

~-------tRAS -------~

1+---- tRCD ----1+---

ADDRESSES VIHVIL -

MOTOROLA MEMORY DATA
3-260

MCM94000-MCM9L4000

FAST PAGE MODE READ CYCLE
~--------------------tR~P----------------~

RAS

CAS

Vi

VIHVIL -

•

VIHVIL -

VIHVIL -

DO VQH(DATA OUT) VOL-

..J-.:.t-.:.t-.:.t-~.:.t-;"

-----------KIX

""",,--,=-='--'T

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

RAS

CAS

Vi

VIHVIL-

VIHVIL-

VIHVIL- ~~~~~~~~_~_~~~~_~~~~~~~_~~~~~~~~~~

DO VIH(DATAlN) VIL -

-L-.....................~........ ,

"'--------'r

MOTOROLA MEMORY DATA
3-261

MCM94000-MCM9L4000

RAS ONLY REFRESH CYCLE
(Wand A10 are Don't Care)
~------------------IRC------------------------~

14---------------IRAS---------------.(
RAS

D

CAS

VIH-

Jr-----,

VIL-

VIHVIL-

AO TO A9

VIHVIL -

DO VOH(DATA OUT) VOL-

HIGHZ

CAS BEFORE RAS REFRESH CYCLE
(AO to A10 are Don't Care)
i-----------------IRC

---------------1

~----------tAAS------~~

~--------~

~--------~

CAS VIHVIL- _ _- J

DO VOH(DATA OUT) VOL - _ _ _ _ _--''1

HIGHZ - - - - - - - - - - -

MOTOROLA MEMORY DATA
3-262

MCM94000-MCM9L4000

HIDDEN REFRESH CYCLE (READ)

RAS VIHVIL -

•

ADDRESSES VV IH IL -

Vi VIHVIL -

DO VOH(DATA OUT) VOL _

..::.t...::J..~~IL...lL..::ll

---------+-~'-

1+---- tDHR----~

MOTOROLA MEMORY DATA
3-283

MCM94000-MCM9L4000

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE

~--------------tRAS------------------~

•

RAS

CAS

ADDRESSES

~~~

VIHVIL VIHVIL VIHVIL-

READ CYCLE
DO VOH(DATA OUT) VOL - - - - - - - - - HIGHZ

W

-----++<1

VIHVIL -

WRITE CYCLE

W VIHVIL- ~~~~~~~~~~~~_ _ _~_ _ _~~~~~~~~~~~
t=tDS
DQ
(DATA IN)

~:: =<....:p:-__

+ __-!______----'''--''-;>'--'''--'''--'''-'''--''-''-''-''-''->L......

DO (DATA IN)

=

~I

tD~

tDH~1

~:~ -";-"KX"""XXl""""A"X"ArXXl""""A"X"7':"""'7'Xxn:-O-V-ALID-DATA-j<\"'XX"X~XX\"""7'C"X"XA7'XX\"""7'C"X"XA7'XX\"""7'C"X~X

MOTOROLA MEMORY DATA

3-272

MCM~A·MCM9~A

FAST PAGE MODE READ CYCLE

•
W VIHVIL -

OQ(OATAOUT) VQHVOL-

-'-"'-"'-"'-;"'--"'--"

------------1-{IX

FAST PAGE MODE EARLY WRITE CYCLE

W VIHVIL-

~~~~~~~~_~-~~~~-~_+~~~~_+-~~~~~~~~~~

OQ(OATAIN) VIHVIL - -'-"'-''''-''......,.'--'''~ ~ _ _ _ _...T

MOTOROLA MEMORY DATA
3-273

MCM~A·MCM9~A

RAS ONLY REFRESH CYCLE
(Wand A10 are Don't Care)
~-------------------tRC------------------------~
14---------------tRAS--------------~

•

RAS VIH -

----"L

J...--------"L

VIL -

AOTOA9 VIHVIL -

DQ(DATAOUT) VOH - - - - - - - - - - - - - - - HIGHZ
VOL -

CAS BEFORE RAS REFRESH CYCLE
(AD to A10 are Don't Care)

14----------------tRC --------------~
14-------tRAS ---------.I

CAS VIH VIL -

___---J

iii VIHVIL -

......."""""'....:.i..-¥-..:.I...J

--.l.~'--_ _ _ _ _ _ _ __

tOFF -+1...
DO (DATA OUT) VOH VOL -

_ _ _ _ _--"1

~

HIGHZ - - - - - - - - - -

MOTOROLA MEMORY DATA

3-274

MCM~A·MCM9~A

HIDDEN REFRESH CYCLE (READ)

III
W VIHVIL -

DQ (DATA OUn VOH VOL -

-"--"--"-+-"--"-.>1

----------+-<1

HIDDEN REFRESH CYCLE (EARLY WRITE)

ADDRESSES VVIH IL -

MOTOROLA MEMORY DATA
3-275

MCM~A·MCM9~A

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
~-------------tR~------------~

~~~

1 - - - - tRSH -------1-1

•

~---tc~ - - - - . - j

READ CYCLE

OO(DATAOUT) VOV H-- ----H---- HIGHZ _ _ _ _-++<1
OL

EARLY WRITE CYCLE

Vi

VIHVIL -

00

(DATA IN) ~:~= (XXXXXXXXXXX

f

tDS

DH

MOTOROLA MEMORY DATA
3-276

3<

t
VALIDDATAXXXXXXXXXXX)

MCM~A·MCM9~A

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight
active cycles of the row address strobe (clock) to initialize all
dynamic nodes within the module. During an extended inactive state (greater than 16 milliseconds with the device powered up), a wake up sequence of eight active cycles is necessary to ensure proper operation.
ADDRESSING THE RAM
The eleven address pins on the device are time multiplexed
at the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two separate ll-bit address fields. A total of twenty two address bits,
eleven rows and eleven columns, will decode one of the
4,194,304 word locations in the device. RAS active transition
is followed by CAS active transition (active = VIL, tR.QlLminimum) for all read or write cycles. The delay between RAS and
CAS active transitions, referred to as the multiplex window,
gives a system designer flexibility in setting up the external addresses into the RAM.
The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the module:
RAS only refresh cycle, CAS before RAS refresh cycle,
and page mode.
READ CYCLE
The DRAM may be read with either a "normal" random read
cycle or a page mode read cycle. The normal read cycle is outlined here, while the other cycles are discussed in separate
sections.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (IN) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time olthe device is independent of the address multiplex
window; however, CAS must be active before or at tRCD maximum to guarantee valid data out (DQ) at tRAC (access time
from RAS active transition). If the tRCD maximum is exceeded, read access time is determined by the CAS clock active
transition (tCAel.
The RAS and CAS clocks must remain active for a minimum
time of tRAS and tCAS respectively, to complete the read
cy:cle. IN must remain high throughout the cycle, and for time
tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data althat bitiocation. Once RAS transitions to Inactive, it must remain inactive for a minimum time of
tRP to precharge the internal device circuitryforthe next active
cycle. DQ is valid, but not latched, as long as the CAS clock is

active. When the CAS clock transitions to inactive, the output
will switch to High Z (three-state).
WRITE CYCLE
The user can write to the DRAM with either an early write or
page mode early write cycle. Early write mode is discussed
here, while page mode write operation is covered elsewhere.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of IN to active
(VI,U' Early write mode is distinguished by the active transition
of W, with respect to CAS. Minimum active time tRAS and
tCAS, and precharge time tRP apply to write mode, as in the
read mode.
An early write cycle is characterized by IN active transition at
minimum time twcs before CAS active transition. Data in
(DQ) is referenced to CAS in an early write cycle. RAS and
CAS clocks must stay active for tRWL and tCWL' respectively,
after the start of the early write operation to complete the cycle.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
2048 column locations on a selected row of the module. Read
access time in page mode (tCAC) is typically half the regular
RAS clock access time, tRAC' Page modl:j operation consists
of keeping RAS active while toggling CAS between VIH and
~The row is latched by RAS active transition, while each
CAS active transition allows selection of a new column location on the row.
A page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for
minimum of tcp, while RAS remains low (VIL). The second
CAS active transition while RAS is low initiates the first page
mode cycle (tpC)' Either a read or write operation,can be performed in a page mode cycle, subject to the same conditions
as in normal operation (previously described). These operations can be intermixed inconsecutive page mode cycles and
performed in any order. The maximum number of consecutive
page mode cycles is limited by tRASP' Page mode operation
is ended when RAS transitions to inactive, coincident with or
following CAS inactive transition.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically
refreshed (recharged) to maintain the correct bit state. Bits in
the MCM94000A require refresh every 16 milliseconds, while
refresh time for the MCM9L4000A is 128 milliseconds.
This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the
bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6
microseconds for the MCM94000A, and 124.8 microseconds
for the MCM9L4000A. Burst refresh, a refresh of all 1024 rows
consecutively, must be performed every 16 milliseconds on
the MCM94000A and 128 milliseconds on the MCM9L4000A.
A normal read or write operation to the RAM will refresh all
the bits associated with the particular row decoded. Three
other methods of refresh, RAS-only refresh, CAS before
RAS refresh, and hidden refresh are available on this device
for greater system flexibility.

MOTOROLA MEMORY DATA

•

MCM~A·MCM9~A

RAS-Only Refresh

respect to RAS active transition (to prevent test mode cycle)
as in CAS before RAS refresh.

RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high
(VIH) throughoutthe cycle. An external counter is employed to
ensure all rows are refreshed within the specified limit.

•

CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CAS before RAS refresh counter test. This test is performed with a read-write operation. During the test, the internal
refresh counter generates the row address, while the external
address supplies the column address. The entire array is refreshed after 1024 cycles, as indicated by the check data written in each row. See CAS before RAS refresh counter test
cycle timing diagram.
The test can be performed after a minimum of 8 CAS before
RAS initialization cycles. Test procedure:
1. Write "O"s into all memory cells (normal write mode).
2. Select a column address, and read "0" out olthe cell by performing CAS before RAS refresh counter test, read
cycle. Repeat this operation 1024 times.
3. Select a column address, and write "1" into the cell by performing CAS before RAS refresh counter test, write
cycle. Repeat this operation 1024 times.
4. Read "1 "s (normal read mode), which were written at step
3.
5. Repeat steps 1 to 4 using complement data.

CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order actives an internal refresh
counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh
cycle.
The output buffer remains at the same state it was in during
the previous cycle (hidden refresh). W must be inactive for
time twRP before and time tWRH after RAS active transition to
prevent switching the device into a test mode cycle.
Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active the end
of a read or write cycle, while RAS cycles inactive for tRP and
back to active, starts the hidden refresh. This is essentially the
execution of a CAS before RAS refresh from a cycle in progress (see Figure 1). Wis subject to the same conditions with

CAS BEFORE RAS
REFRESH CYCLE

MEMORY CYCLE

DQ -HIGH Z-+---{

CAS BEFORE RAS
REFRESH CYCLE

VALID DATA·OUT

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION

(Order by Full Part Number)
MCM 94OO0A or 9L4000A
Motorola Memory Prefix
Part Number

--.T
I

11 '-' -ro~.
x

XX

'00

'" -

"'~." -" "'" - "'~,

Package (AS = SIMM, L = SIP, LH = Low Height SIP)

Full Part Numbers-MCM94000AS60
MCM94000AS70
MCM94000AS80
MCM94000AS10
MCM9L4000AS60
MCM9L4000AS70
MCM9L4000AS80
MCM9L4000AS10

MCM94000L60
MCM94000L70
MCM94000LBO
MCM94000L10

MCM94030LH60
MCM94030LH70
MCM94030LH80
MCM94030LH10

MCM9L4000L60
MCM9L4000L70
MCM9L4000L80
MCM9L4000L10

MCM9L4030LH60
MCM9L4030LH70
MCM9L4030LH80
MCM9L4030LH10

MOTOROLA MEMORY DATA
3-278

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM94256

256K X 9 Bit Dynamic Random
Access Memory Module
The MCM94256S is a 2.25M bit, dynamic random access memory (DRAM)
module organized as 262,144 x 9 bits. The module is a 30-lead single-in-line
memory module (SIMM) consisting of two MCM514256A DRAMs housed in
20/26 J-Iead small outline packages (SOJ) and one CMOS 256K x 1 DRAM
housed in an 18-lead PLCC package, mounted on a substrate along with a
0.22/1F (min) decoupling capacitor mounted adjacent to each DRAM. The
MCM514256A is a 1.0/1 CMOS high speed, dynamic random access memory
organized as 262,144 four-bit words and fabricated with CMOS silicon-gate
process technology.
•
•
•
•
•
•
•
•
•
•
•

•

•

•

•

Three-State Data Output
Early-Write Common 1/0 Capability
Fast Page Mode Capability
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
512 Cycle Refresh:
MCM94256 = 8 ms (Max)
Consists of Two 256K x 4 DRAMs, One 256K x 1 DRAM, and
Three 0.22/1F (Min) Decoupling Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access Time (tRAC):
MCM94256S-70 = 70 ns (Max)
MCM94256S-80 = 80 ns (Max)
MCM94256S-10 = 100 ns (Max)
Low Active Power Dissipation:
MCM94256S-70 = 1.32 W (Max)
MCM94256S-80 = 1.16 W (Max)
MCM94256S-10 = 1.05 W (Max)
Low Standby Power Dissipation:
TTL Levels = 33 mW (Max)
CMOS Levels = 16.5 mW (Max)
CAS Control for Eight Common 1/0 Lines
CAS Control for Separate 1/0 Pair

~
::
CASE 839A

3D-PIN
SINGLE IN-LINE PACKAGE
(TOP VIEW, MCM94256)

'!cc
CAS
OQO
AO
A1
OQ1
A2
A3
VSS
OQ2
A4
A5
OQ3
AS
A7
OQ4
A8
NC
NC
OQ5

Iii

VSS
DQ6
NC

007

as

AAS
CASS
OS
VCC

(1)
(21
(3)
(4)
(5)
(S)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(1S)
(17)
(18)
(191
(20)
(21)
(221
(23)
(24)
(251
(26)
(27)
(2S)
(29)
(30)

0

'-----"-'

PIN NAMES
AD-A8 ..................... Address Inputs
DOD-D07 ... . . . . . . . . . . .. Data Input/Output
D8 . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Data Input
08 . . . . . . . . . . . . . . . . . . . . . . . . . .. Data Output
CAS ............... Column Address Strobe
CAS8 .............. Column Address Strobe
RAS .................. Row Address Strobe
Vii ....................... ReadlWrite Input
VCC ........................ Power (+5 VI

~~S.::::::::::::::::::::::: ·N~·6~~~~~~~~

MOTOROLA MEMORY DATA
3-279

MCM94266

FUNCTIONAL BLOCK DIAGRAM

00~D03--------------~DD~0~--l
A~A8

RAS

•

CAS

W

004-007--+-1-1-1

00

CAS --+--1---1---1
W------1~~
A~A8 ___--r--,--,

VCC---------------~

VSS------------------~

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

UnH

VCC

-1 to +7

V

Yin. Vout

-1 to +7

V

Data Out Current per DQ Pin

lout

50

mA

Power DisSipation

Po

1.8

W

Operating Temperature Range

TA

Oto+70

Tstg

-25 to +125

°c
°c

Power Supply Voltage
Voltage Relative to VSS for Any Pin Except VCC

Storage Temperature Range

NOTE. Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended voltages for extended periods of time could affect
device reliability.

MOTOROLA MEMORY DATA

3-280

MCM94256

DC OPERATING CONDITIONS AND CHARACTERISTICS
=5.0 V ± 10%, TA =0 to 70°C, Unless Otherwise Noted)

(Vee

RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

Typ

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

-

6.5

V

1

0.8

V

1

Min

Max

Unit

Notes

mA

2

logic High Voltage, All Inputs

VIH

2.4

logic low Voltage, All Inputs

Vil

-1.0

DC CHARACTERISTICS
Characteristic

Symbol

VCC Power Supply Current
MCM94256-70, tRC =130 ns
MCM94256-80, tRC =150 ns
MCM94256-10, tRC = 180 ns

ICCI

VCC Power Supply Current (Standby) (RAS =CAS =VIH)

ICC2

VCC Power Supply Current During RAS only Relresh Cycle
MCM94256-70, tRC =130 ns
MCM94256-80, tRC =150 ns
MCM94256-10, tRC =180 ns

ICC3

VCC Power Supply Current During Fast Page Mode Cycle
MCM94256-70, tpc =40 ns
MCM94256-80, tpc =45 ns
MCM94256-1 0, tpc =55 ns

ICC4

VCC Power Supply Current (Standby) (RAS =CAS = VCC - 0.2 V)

ICC5

VCC Power Supply Current During CAS Belore RAS Relresh Cycle
MCM94256-70, tRC = 130 ns
MCM94256-80, tRC =150 ns
MCM94256-10, tRC =180 ns

ICC6

-

225
195
165

-

225
195
165

-

160
135
110

-

225
195
165

6

3

mA
mA

2

mA

2,4

mA
mA

2

Input leakage Current (VSS" Vin" VCC)

Ilkg(l)

-30

30

Output leakage Current (CAS at logic I, VSS S Vin S VCC)

Ilkg(O)

-10

10

!lA
!lA

=-5 mAl

VOH

2.4

-

V

Output low Voltage (IOl =4.2 mAl

VOL

-

0.4

V

Symbol

Max

Unit

Notes

Cin

30

pF

3

pF

3

Output High Voltage (IOH

CAPACITANCE (I =1.0 MHz, TA =25°C, VCC =5 V, Pe~odically Sampled RalherThan 100% Tesled)
Parameter
Input Capacitance

AO-AS, W, CAS, RAS
DS,CASS

InpuVOutput Capacitance

DQO-007

r-17

CliO

17

17
pF
Output Capacitance
OS
3
Cout
NOTES:
1. All voltages referenced to VSS.
2. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
3. Capacitance measured with a Boonton Meter or effective capacitance calculated lrom the equation: C = II1VI1V.
4. Measured with one address transition per page mode cycle.

MOTOROLA MEMORY DATA
3-2B1

•

MCM94256

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vec = 5.0 V ± 10%, TA = 0 to 70 o e, Unless Otherwise Noted
READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)
MCM94256-70

MCM94256-80

MCM94256-10

Alternate

Min

Min

Symbol
Parameter

II

Random Read or Write Cycle TIme

Standard

Max

Max

Min

Max

Unit

Notes

-

150

-

180

-

ns

5

45

-

55

-

ns

tRELREL

tRC

130

Page Mode Cycle TIme

tCELCEL

tpc

40

Access TIme from RAS

tRELQV

tRAC

-

100

ns

6,7

tcAC

20

-

80

tCELQV

-

70

Access TIme from CAS

20

-

25

ns

6,8

Access TIme from Column Address

tAVQV

tAA

-

35

-

40

-

50

ns

6,9

Access TIme from Precharge CAS

tCEHQV

tCPA

-

35

-

40

-

50

ns

6

CAS to Output in Low-Z

tCELQX

tCLl

a
a

-

a
a

-

0

-

ns

6

20

a

20

ns

10

Output Buffer and Turn-Off Delay
Transition TIme (Rise and FaU)

tCEHQZ

!oFF

20

IT

tT

3

50

3

50

3

50

ns

RAS Precharge TIme

tREHREL

tRP

50

-

60

-

70

-

ns

RAS Pulse Width

tRELREH

tRAS

70

10,000

80

10,000

100

10,000

ns

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

70

100,000

80

100,000

100

100,000

ns

RASHoldTIme

tCELREH

tRSH

20

-

20

25
100

-

ns

80

-

CAS Hold TIme

tRELCEH

tcSH

70

CAS Pulse Width

tCELCEH

tCAS

20

10,000

20

10,000

25

10,000

ns

RAS to CAS Delay Time

tRELCEL

tRCD

20

50

20

60

25

75

ns

11

tRELAV

tRAD

15

35

15

40

20

50

ns

12

CAS to RAS Precharge TIme

tCEHREL

tCRP

5

-

5

tcp

10

-

10

10

-

ns

tcEHCEL

-

10

CAS Precharge TIme
(Page Mode Cycle Only)

a

-

a

-

ns

10

15

75

-

ns

60

-

40

-

50

-

ns

RAS to Column Address Delay Time

Row Address Setup TIme

tAVREL

tASR

a

Row Address Hold TIme

tRELAX

tRAH

10

Column Address Setup Time

tAVCEL

tASC

a

Column Address Hold TIme

tCELAX

tCAH

15

Column Address Hold TIme Referenced
toRAS

tRELAX

tAR

55

-

Column Address to RAS Lead TIme

tAVREH

tRAL

35

-

a
15

a
20

ns

ns

ns
ns
ns

(continued)
NOTES:
1. V,H min and V,L max are reference levels for measuring timing of input signals. Transition times are measured between V,H and V,L'
2. An initial pause of 200 lLs is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between V,H and V,L (or between V,L and V, H) in a monotonic manner.
4. AC measurements IT = 5.0 ns.
5. The specification for tRC (min) is only to indicate cycle time at which proper operation over the full temperature range (O'C $ TA $ 70'C) is
assured.
6. Measured with a current load equivalent to 2 TTL (-200 !LA, +4 mAl loads and 100 pF with the data output trip pOints set at VOH = 2.0 V and
VOL =0.8 V.
7. Assumes that tRCD $ tRCD (max).
8. Assumes that tRCD ~ tRCD (max).
9. Assumes that tRAD ~ tRAD (max).
10. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operation within the tRCD (max) limit ensures thattRAC (max) can be met. tRCD (max) is specified as a reference point only; iftRCD is greater
than the specified tRCD (max) limit, then access time is controlled exclusively by tcAC'
12. Operation within the tRAD (max) IimitensuresthattRAC (max) can be met. tRAD (max) is specified as a reference point only; iftRAD is greater
than the specified tRAD (max), then access time is controlled by tAA'

MOTOROLA MEMORY DATA
3-282

MCM94256

READ AND WRITE CYCLES (Continued)
MCM94256-70

MCM94256-80

MCM94256-10

Standard

Alternate

Min

Max

Min

Max

Min

Max

Unit

Read Command Setup Time

twHCEl

tRCS

0

-

0

0

tcEHWX

tRCH

0

-

0

-

ns

Read Command Hold Time Referenced
to CAS

-

ns

13

Read Command Hold Time Referenced
toRAS

tREHWX

tRRH

0

-

0

-

0

ns

13

Write Command Hold Time Referenced
to CAS

tcELWH

twCH

15

-

15

-

20

-

Write Command Hold Time Reference
toRAS

tRElWH

twCR

55

-

60

-

75

-

ns

Write Command Pulse Width

twLWH

twP

15

15

-

20

-

ns

20

25

-

ns

25

-

ns

0

Symbol
Parameter

0

Notes

ns

Write Command to RAS Leed Time

tWlREH

tRWL

20

Write Command to CAS lead Time

tWlCEH

tCWl

20

-

Data in Setup Time

tOVCEl

tos

0

-

0

-

ns

14

Data in Hold Time

tcELOX

tOH

15

-

15

-

20

-

ns

14

Data in Hold Time Referenced to RAS

tRELOX

tOHR

55

-

60

-

75

-

ns

Refresh Period

tRVRV

tRFSH

-

8

-

8

-

8

ms

Write Command Setup Time

twLCEl

twcs

0

-

0

-

0

-

10

-

10

-

ns

-

30

-

30

-

ns

-

0

-

ns

50

20

ns

15

CAS Setup Time for CAS Before RAS
Refresh

tRELCEL

tCSR

10

CAS Hold Time for CAS Before RAS
Refresh

tRELCEH

tcHR

30

CAS Precharge 10 CAS Active Time

tREHCEL

tRPC

0

-

0

CAS Precharge Time for CAS Before
RAS Counter Test

tCEHCEL

tCPT

40

-

40

CAS Precharge Time

ICEHCEL

tcPN

10

-

10

-

15

tcELCELP

tpcp

45

-

45

-

55

-

ns

Fast Page Mode Cycle Time

ns

16

Output Buffer and Turn-Off Delay

tcEHOZP

toFFP

0

25

0

25

0

25

ns

10,16

-

-

-

ns

Access Time from Precharge CAS
45
45
6,16
50
ns
tcPAP
tcEHOVP
NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are reference to CAS leading edge in random write cycles.
15. twcs is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if twcs ;, twcs (min), the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is not
satisfied, the condition of the data out (at access time) is indeterminate.
16. This parameter applies to the parity bit only.

MOTOROLA MEMORY DATA
3-283

•

MCM94266

READ CYCLE

~

•

VIHVIL -

CAS

VIHVIL -

ADDRESSES

VIHVIL -

iN

VIHVIL -

DO VOH(DATA OUT)
VOL-

EARLY WRITE CYCLE

RAS VIH- _ _ _- , 1 1 4 - - - - - - tRAS

IRc ---------+j
-----+1111--....:..::.---.1

VIL -

iN VIHVIL -

L,j[,..lL..liL.Y..~t...:;L~~f--+_I-_ _I-~t...:;L~I..:;,L~~'J.::J.~..t..:::.I..~

DO VIH- ..........,...,....,....,..:.,......,.......~.....;
(DATA IN) VIL _

Ir.....;...--'-~...J

J,,..,...."!f:'"1.....,......,,..,....,,,...,....,.....,,...,,...,.,...,.........,....,

L,j[,~IUI:~IUI:~:lU.l..::>f·1L-_--.:.____p..::u..:lU.u..::~.t.::J.:u..:lU.WL~..t..:::.I..~

1 + - - - - tDHR

---~

MOTOROLA MEMORY DATA

3-284

MCM94256

FAST PAGE MODE READ CYCLE

ADDRESSES

•

VIH-

iN

DO VOH(DATA OUT) VOL _

----------C

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

RAS VIH- ---~
VIL -

CAS VIH -

I'---------~---___:___:___:-_'I

--+--1+-----.1....

VIL-

VIHADDRESSES
VIL -

iN

VIHVIL -

L.:l/.....lL..'IWL~IWL...lqi...----1H--+'~-+-+--4-'-~-+-+-1-.IL~~WL..lL...l.

DQ VIH -

..."....,....,,,.....,..,..:-,,....,.,.,. Ir--"""'"=----.I

(DATA IN) VIL _

....,.""'-'......,.......,.......,.001 1'-_":;';';;'-'--'1

MOTOROLA MEMORY DATA
3-285

MCM94266

RAS ONLY REFRESH CYCLE
(Wand A8 are Don't Care)

•

RAS

VIH -

..

IRC
IRAS

VIL -

VIH CAS
VIL -

VIH -

AO-Ml
VIL -

DO VOH (DATA OUT)
VOL -

HIGH·Z

CAS BEFORE RAS REFRESH CYCLE
(W And AO to A8 are Don't Care)

J+------J+---RAS

IRC------+1

IRAS---~

Lr--""';"'--{

VIH vlL tcHR

CAS

VIH VIL -

DO VOH (DATA OUT)
vOL -

HIGH·Z

MOTOROLA MEMORY DATA
3-288

MCM94256

HIDDEN REFRESH CYCLE (READ)

RAS

VIH VIL

-

•

VIH CAS
VIL -

ADDRESSES

VIH
VIL -

W

VIH

-

VIL

-

DO VOH (DATA OUT)
VOL -

HIDDEN REFRESH CYCLE (WRITE)

ADDRESSES

W

VIHVIL -

DO
(DATA IN)

1...JJ.~"-lL~"-lL-9'---it-----lf~~UL~UL~UL~UL~l...:JI..~l...:JI..~

VIH - ---+-:-=--~ .It-------i.~7':"?'''"A"'l~_rr~'"7:"7rJ'''..,.....,~_rr~

+-_--.1 "-____...J

VIL _ _ _ _

"-"-.>L...l'-"--"-'''-''-''-'''--'''-''--''-''-''--''-'''-''....lL..l

1+---- tDHR---+I

MOTOROLA MEMORY DATA
3-287

MCM94256

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
lRAS

-------~

1 + - - - IRSH

•

CAS
VIL -

ADDRESSES

VIH VIL -

READ CYCLE
DO VOH (DATAOUn
VOL -

Vi

VIH VIL -

WRITE CYCLE

Vi

VIH VIL -

DO
(DATA IN)

VIH VIL -

MOTOROLA MEMORY DATA
3-288

MCM94256

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This is to be followed by a minimum of eight
active cycles of the row address strobe (RAS) to initialize all
dynamic nodes within the module. During an extended inactive state (greater than 8 milliseconds with the device powered
up), a wake up sequence of eight active cycles is necessary to
assure proper operation.
ADDRESSING THE RAM
The nine address pins on the device are time multiplexed
at the beginning of the memory cycle by two clocks row address strobe (RAS) and column address strobe (CAS), into
two separate 9-bit address fields. A total of eighteen address
bits, nine rows and nine columns, will decode one of the
262,144 word locations in the device. RAS active transition is
followed by CAS active transijion (active = VIL, tRCD minimum) for all read or write cycles. The delay between RAS and
CAS active transitions, referred to as the multiplex window,
gives a system designer flexibility in setting up the external addresses into the RAM.
The external CAS Signal is ignored until an internal RAS
Signal is available. This gate feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are two other variations in addressing the module:
RAS only refresh cycle and CAS before RAS refresh
cycle. Both are discussed in separate sections that follow.
READ CYCLE
The DRAM may be read with either a normal random read
cycle or a page mode read cycle. The normal read cycle is outlined here, while the page mode cycle is discussed in a separate section.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (W) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to
enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex window. CAS controls read access time: CAS must be
active before or at tRCD maximum to guarantee valid data out
(DO) at tRAC (access time from RAS active transition). If the
tRCD maximum is exceeded, read access time is determined
by the CAS clock active transition (tCAC)'
The RAS and CAS clocks must remain active for a
minimum time fo tRAS and tCAS, respectively, to complete
the read cycle. Wmust remain high throughout the cycle, and
for time tRRH or tRCH after RAS or CAS inactive transijion,
respectively, to maintain the data at that bit location. Once

RAS transitions to inactive, it must remain inactive for a
minimum time of tRP to precharge the internal device circuitry
for the next active cycle. DO is valid, but notlatched, as long as
the CAS clock is active. When the CAS clock transitions it
inactive, the output will switch to High Z, tOFF after inactive
transition.
WRITE CYCLE
The DRAM may be written with either an early write or page
mode early write cycle. Early write mode is discussed here,
while the page mode write operation is covered in another
section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of Wto active
(VILl. Early write mode is distinguished by the active transition
of W, with respect to CAS. Minimum active time tRAS and
tCAS, and precharge time tRP apply to write mode, as in the
read mode.
An early write cycle is characterized by Wactive transition
at minimum time twcs before CAS active transition. Data In
(DO) is referenced to CAS in an early write cycle. RAS and
CAS clocks must stay active for tRWL and tCWL'
respectively, after the start of the early write operation to
complete the cycle.
PAGE-MODE CYCLES
Page mode allows fast successive data operations at all
512 column locations on a selected row of the module. Read
access time in page mode (tCAC) is typically half the regular
RAS clock access time, tRAC. Page mode operation consists
of keeping RAS active while toggling CAS between VIH and
VIL' The row is latched by RAS active transition, while each
CAS active transition allows selection of a new column location on the row.
The page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for
minimum tcp, while RAS remains low (VIL)' The second CAS
active transition while RAS is low initiates the first page mode
cycle (tpC). Either a read or write operation can be performed
in a page mode cycle, subject tothe same conditions as in normal operation (previously described). These operations can
be intermixed in consecutive page mode cycles and performed in any order. The maximum number of consecutive
page mode cycles is limited by tRASP' Page mode operation
is ended when RAS transitions to inactive, coincident with or
following CAS inactive transition.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge degrades with
time and temperature, thus each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in the
MCM94256 require refresh every 8 milliseconds, while refresh time for the MCM9L4256 is 64 milliseconds.
Refresh is accomplished by cycling through the 512 row
addresses in sequence within the specified refresh time. All
the bits on a row are refreshed simultaneously when the row is

MOTOROLA MEMORY DATA
3-289

•

MCM94256

II

addressed. Distributed refresh implies a row refresh every
15.6 microseconds for the MCM94256, and 124.8 microseconds for the MCM9L4256. Burst refresh, a refresh of all 512
rows consecutively, must be performed every 8 milliseconds
on the MCM94256 and 64 milliseconds on the MCM9L4256.
A normal read or write operation to the RAM will refresh all
the bits associated with the particular row decoded. Three other methods of refresh, RAS only refresh, CAS before RAS
refresh, and Hidden refresh are available on this device for
greater system flexibility.

end of a read or write cycle, while RAS cycles inactive for tRP
and back to active,starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1).

CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested
with a CAS before RAS refresh counter test. This refresh
counter test is performed with read and write operations. During this test, the internal refresh counter generates the rowaddress, while the external address input supplies the column
address. The entire array is refreshed after 512 test cycles, as
indicated by the check data written in each row. See CAS before RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:

RA5-0nly Refresh
RAS-only refresh consists of RAS transition to active,
latching the row address to be refreshed, while CAS remains
high (VIH) throughout the cycle. An external counter is
employed to ensure all rows are refreshed within the specified
limit.

1. Write "O"s into all memory cells (normal write mode).

CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order activates an internal refresh
counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh
cycle. The olitput buffer remains at the same state it was in
during the previous cycle (hidden refresh).

2. Select a column address, and read "0" out of the cell by
performing CAS before RAS refresh counter test, read
cycle. Repeat this operation 512 times.

3. Select a column address, and write "1" into the cell by performing CAS and RAS refresh counter test, write cycle.
Repeat this operation 512 times.
4. Read "1 "s (normal read mode), which were written at step
3.

Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the

5. Repeat steps 1 to 4 using complement data.

MEMORY CYCLE

REFRESH CYCLE

DQ- HIGH-Z

REFRESH CYCLE

VALID DATA-OUT

Figure 1. Hidden Refresh Cycle
ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory

prefiX~

Tt t
94256

Part Number - - - - - - - - - - - - '

l'--________

Full Part Number - MCM94256S70
MCM94256S80
MCM94256S10

MOTOROLA MEMORY DATA

3-290

Speed (70

= 70 ns, 80 = 80 ns, 10 = 100 ns)

Package (S = SIMM)

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM94256A

256K X 9 Bit Dynamic Random
Access Memory Module
The MCM94256AS is a 2.25M bit, dynamic random access memory
(DRAM) module organized as 262,144 x 9 bits. The module is a 30-lead
single-in-line memory module (SIMM) consisting of two MCM514256A
DRAMs housed in 20/26 J-Iead small outline packages (SOJ) and one
MCM5110004 1M x 1 DRAM, mounted on a substrate along with a 0.221!F
(min) decoupling capacitor mounted adjacent to each DRAM. The
MCM514256A is a 1.01! CMOS high speed, dynamic random access memory
organized as 262,144 four-bit words and fabricated with CMOS silicon-gate
process technology.
•
•
•
•
•
•
•
•
•
•
•

•

•

•
•

Three-State Data Output
Early-Write Common I/O Capability
Fast Page Mode Capability
TTL-Compatible Inputs and Outputs
RAS Only Refresh
CAS Before RAS Refresh
Hidden Refresh
512 Cycle Refresh:
MCM94256A = 8 ms (Max)
Consists of Two 256K x 4 DRAMs, One 1M x 1 DRAM, and
Three 0.221!F (Min) Decoupling Capacitors
Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection
Fast Access Time (tRAC):
MCM94256AS-70 = 70 ns (Max)
MCM94256AS-80 = 80 ns (Max)
MCM94256AS-10 = 100 ns (Max)
Low Active Power Dissipation:
MCM94256AS-70 = 1.32 W (Max)
MCM94256AS-80 = 1.16 W (Max)
MCM94256AS-10 = 0.99 W (Max)
Low Standby Power Dissipation:
TTL Levels = 33 mW (Max)
CMOS Levels = 16.5 mW (Max)
CAS Control for Eight Common I/O Lines
CAS Control for Separate I/O Pair

•

SPACKAGE
SIMMMODULE
CASE 839A

3D-PIN
SINGLE IN-LINE PACKAGE
(TOP VIEW, MCM94256)

~

CAS
DQO
AO

(1)
(2)
(3)
(4)

Al

(5)

DQl
A2
A3
VSS
DQ2
A4
AS
DQ3
A6
A7

(6)

(7)
(B)
(9)
(10)
(11)
(12)
(13)
(14)
(15)

DQ4

(16)

AB
NC
NC
DQ5

(17)
(IB)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(2B)
(29)
(30) L-_----'

W

VSS
DQ6
NC
DQ7
QB

RAS
CASB
DB

VCC

PIN NAMES

AO-A8 ..................... Address Inputs
DQO--D07 ............... Data InpuVOu1put
D8 . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Data Input
08 . . . . . . . . . . . . . . . . . . . . . . . . . .. Data Output
CAS ............... Column Address Strobe
CAS8 .............. Column Address Strobe
RAS .................. Row Address Strobe
W ....................... ReadlWrite Input
VCC ........................ Power (+5 V)
VSS .............................. Ground
NC ........................ No Connection

MOTOROLA MEMORY DATA
3-291

MCM94256A

FUNCTIONAL BLOCK DIAGRAM
DO~D03--------------~DO
A~A8

RAS

•

CAS

W

DQ4-D07--~~~~

DO
AO-A8
RAS

CAS --+-~---I~

CAS

W-------1H~
A~A8 ______,__,__,

RAS:==~=~
08
D8

CAS8 --------~

VCC----------------~

VSS------------------~

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage
Vo~age

Relative to VSS for Any Pin Except VCC

Data Out Current per DO Pin

Symbol

Value

Unit

VCC

-1 to +7

V

Yin. Vout

-1 to +7

V

'out

50

rnA

Power Dissipation

PD

1.8

W

Operating Temperature Range

TA

Oto+70

Tstg

-25 to +125

°c
°c

Storage Temperature Range

NOTE: Permanent deVice damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended vo~ages for extended periods of time could affect
device reliability.

MOTOROLA MEMORY DATA

3-292

MCM94256A

DC OPERAnNG CONDInONS AND CHARACTERI5nCS
(Vee =5.0 V ± 10%, TA =0 to 70 0 e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Symbol

Min

TYP

Max

Unit

Notes

VCC

4.5

5.0

5.5

V

1

VSS

0

0

0

Logic High Voltage, All Inputs

VIH

2.4

-

6.5

V

1

Logic Low Voltage, All Inputs

VIL

-1.0

-

0.8

V

1

Min

Max

Unit

Notes

rnA

2

DC CHARACTERISTICS
Characteristic

Symbol

VCC Power Supply Current
MCM94256A-70, tRC = 130 ns
MCM94256A-80, tRC = 150 ns
MCM94256A-1 0, tRC = 1BO ns

ICC1

VCC Power Supply Current (Standby) (RAS = CAS = VIH)

ICC2

VCC Power Supply Current During RAS only Refresh Cycle
MC¥94256A-70, tRC = 130 ns
MCM94256A-BO. tRC = 150 ns
MCM94256A-10, tRC = 1BO ns

ICC3

VOC Power Supply Current During Fast Page Mode Cycle
MCM94256A-70, tpc =,40 ns
MCM94256A-BO, tpc = 45 ns
MCM94256A-1 0, tpc = 55 ns

ICC4

VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V)
VCC Power supp~ drrent During CAS Before RAS Refresh Cycle
MCM94256A-70, tRC = 130 ns
MCM94256A-BO, tRC = 150 ns
MCM94256A-10,'RC = 1BO ns

-

240
210
180

-

6

-

240
210
1BO

-

1BO
150
120

ICC5

-

3

ICC6

-

-

240
210
1BO

mA
mA

2

mA

2,3

mA
mA

2

Input Leakage Current (VSS '" Vin '" VCC)

Ilkg(l)

-30

30

~

Output Leakage Current (CAS at Logic 1, VSS" Vin" VCC)

ilkg(O)

-10

10

~

VOH

2.4

-

V

VOL

-

0.4

V

Symbol

Max

Unit

Notes

Cin

31

pF

4

pF

4

Output High Voltage (IOH = -5 mAl
Output Low Voltage (IOL = 4.2 mAl

CAPACITANCE (f = 1.0 MHz. TA = 25°C. VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

AO-AB, W, CAS, RAS
DB,CASB

Input/Output Capacitance

DQO--D07

0,10

-

17
17

Output Capacitance
OB
17
pF
4
Cout
NOTES:
1. All voltages referenced to VSS.
2. Ourrent is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open.
3. Measured with one address transition per page mode cycle.
4. Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = lal/aV.

MOTOROLA MEMORY DATA

3-293

MCM94256A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70 o e, Unless Otherwise Noted
READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbot

•

Parameter

MCM94256A-70

MCM94256A-80 MCM94256A-l0

Standard

Alternate

Min

Max

Min

Min

Max

Unit

Notes

Random Read or Write Cycle Time

tRELREL

tRC

130

150

-

180

-

ns

5

Page Mode Cycle Time

teELCEL

tpc

40

-

Max

45

-

55

-

ns

Access Time from RAS

tRELQV

tRAC

ns

6,7

20

25

ns

6,8

Access Time from Column Address

tAVQV

tAA

-

35

-

40

-

100

tCAC

-

80

tCELQV

-

70

Access Time from CAS

50

ns

6,9

Access Time from Precharge CAS

teEHQV

tCPA

-

35

-

40

-

50

ns

6

CAS to Output in Low-Z

tCELQX

tCLZ

0

-

0

-

0

-

ns

6

Output Buffer and Turn-Off Delay

tCEHQZ

tOFF

0

20

0

20

0

20

ns

10

ns

20

tT

t-r

3

50

3

50

3

50

RAS Precharge Time

tREHREL

tRP

50

-

60

-

70

-

ns

RAS Pulse Widt~

tRELREH

tRAS

70

10,000

80

10,000

100

10,000

ns

RAS Pulse Width (Fast Page Mode)

tRELREH

tRASP

70

100,000

80

100,000

RAS Hold Time

tCELREH

tRSH

20

CAS Hold Time

tRELCEH

tCSH

70

CAS Pulse Width

teELCEH

teAS

20

10,000

20

10,000

50

20
15

Transition Time (Rise and Fall)

-

20
80

100

100,000

ns

-

25

ns

-

100

-

25

10,000

ns

60

25

75

ns

11

40

20

50

ns

12

ns

RAS to CAS Delay Time

tRELCEL

tRCD

20

RAS to Column Address Delay Time

tRELAV

tRAD

15

35

CAS to RAS Precharge Time

teEHREL

teRP

5

-

5

-

10

-

ns

CAS Precharge Time
(Page Mode Cycle Only)

tCEHCEL

tcp

10

-

10

-

10

-

ns

Row Address Setup Time

tAVREL

tASR

0

-

0

-

ns

-

-

0

10

15

-

ns

0

Row Address Hold Time

tRELAX

tRAH

10

Column Address Setup Time

tAVCEL

tASC

0

Column Address Hold Time

tCELAX

teAH

15

-

Column Address Hold Time Referenced
toRAS

tRELAX

tAR

55

Column Address to RAS Lead Time

tAVREH

tRAL

36

0

-

ns

15

-

20

-

60

-

75

-

ns

-

40

-

50

-

ns

ns

(continued)
NOTES:
1. VIH min and VIL max are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
2. An initial pause of 200 J.ls is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate speCification, all input signals must
transition between VIH and VIL (or between VIL and VI H) in a monotonic manner.
4. AC measurements t-r = 5.0 ns.
5. The specification fortRC (min) is used only to indicate cycle time atwhich proper operation overthefull temperature range (O'C ~T A ~70'C) is
assured.
6. Measured with a current load equivalent to 2 TTL (-200 1lA, +4 mAl loads and 100 pF with the data output trip points set at VOH = 2.0 V and
VOL = 0.8 V.
7. Assumes that tRCD ~ tRCD (max).
8. Assumes that tRCD ;!; tRCD (max).
9. Assumes that tRAD ;!; tRAD (max).
10. toFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voHage levels.
11. Operation within thetRCD (max) limn ensures thattRAC (max) can be met. tRCD (max) is specified as a reference point only; iftRCD is greater
than the specified tRCD (max) limit, then access time is controlled exclusively by teAC'
12. Operation within the tRAD (max) limit ensures thattRAC (max) can be met. tRAD (max) is specified as a reference point only; iftRAD is greater
than the specified tRAD (max), then access time is controlled by tAA'

MOTOROLA MEMORY DATA

3-294

MCM94256A

READ AND WRITE CYCLES (Continued)
Symbol

MCM94256A-70 MCM94256A-80 MCM94256A-10

Standard

Alternate

Min

Max

Min

Max

Min

Max

Unit

Read Command Setup Time

twHCEl

tRCS

0

0

-

0

tCEHWX

tRCH

0

0

-

0

-

ns

Read Command Hold Time Referenced
to CAS

-

ns

13

Read Command Hold Time Referenced
toRAS

tREHWX

tRRH

0

-

0

-

0

-

ns

13

Write Command Hold Time Referenced
to CAS

tCELWH

twCH

15

15

-

ns

tRELWH

twCR

55

75

-

ns

Write Command Pulse Width

twLWH

twP

15

-

15

20

tRWl

-

20
20

-

25

0

0

15

-

20

-

ns

20

-

20

Write Command Hold Time Reference
to RAS

-

-

75

-

ns

Parameter

Write Command to RAS lead Time

tWLREH

60

25

ns
ns

Write Command to CAS lead Time

twLCEH

tcWL

20

Data in Setup Time

tDVCEL

tDS

0

Data in Hold Time

tcELDX

tDH

15

-

Data in Hold Time Referenced to RAS

tRELDX

tDHR

55

-

60

tRVRV

tRFSH

-

8

-

8

-

8

ms

twLCEL

twcs

0

-

0

-

0

-

ns

-

10

-

10

-

ns

30

-

30

-

ns

-

0

-

ns

50

Refresh Period
Write Command Setup Time
CAS Setup Time for CAS Before RAS
Refresh

tRELCEL

tcSR

10

CAS Hold Time for CAS Before RAS
Refresh

tRELCEH

tcHR

30

-

CAS Precharge to CAS Active Time

tREHCEL

tRPC

0

-

0

tCPT

40

-

40

CAS Precharge Time for CAS Before
RAS Counter Test

tcEHCEL

-

Notes

ns

14.15

ns

14.15

15.16

ns

15
ns
CAS Precharge Time
10
10
tcEHCEL
tcPN
NOTES:
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. These parameters are reference to CAS leading edge in random write cycles.
15. Early write only (twcs ~ twcs (min)).
16. twcs is not a restrictive operating parameter. It is Included in the data sheet as an electrical characteristic only; if twcs ~ twcs (min). the
cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is not
satisfied. the condition of the data out (at access time) is indeterminate.

MOTOROLA MEMORY DATA
3-296

•

MCM94256A

READ CYCLE
IRC

RAS

lRAS

VIHVIL-

a

CAS

VIHVIL -

ADDRESSES

VIHVIL-

VIH-

Vi
VIL-

DQ VOH(DATA OUT)
VOL-

EARLY WRITE CYCLE

CAS VIH- --~-++------.h
VIL-

Vi

VIHVIL -

L.:.L...lL..l"-lL..li.;lWL.~WL.f-+---iI---I-~t..:::.I...~~IL1!~i.:.L~t.:::L~

DO VIH- """'..,....,~.,..:.,,"""'"',....,.~ ~~....:....:.~~I
(DATA IN) VIL _

J...,........,..."...,......,,...,....,,....,,...,....,,....,,...,....,.....,..........,

~~lL..lj~lL..lj:....IL.~1..,;;/ ..._ _ _ _~ '\L""""'-"'-"'-"""...............-"->L..,ljWL..loL..lWJ..~

MOTOROLA MEMORY DATA
3-296

MCM94256A

FAST PAGE MODE READ CYCLE
RAS

V'H-

V,L -

ADDRESSES

---"'\I
I}-------------------fl

•

V'H-

V,L -

iii

DO VOH(DATA OUT) VOl-

FAST PAGE MODE WRITE CYCLE (EARLY WRITE)

ADDRESSES

V'H-

V,L -

W V'HV,L -

DO V,H -

~~~-,M~"'7\

.....................-"';-'......."""-!'---I-I--+'--'+-+-+-......."+--+-+-1-"-""'-'.......'->l.......

~~'Mt"-tM~'7l

r--=-::::----li

(DATA IN) V,L _ .............,.......-"r'L.:LJI ~_"""'::..:.....---'I

MOTOROLA MEMORY DATA
3-297

MCM94256A

RAS ONLY REFRESH CYCLE
(Wand A8 are Don't Care)

•

RAS

VIH -

....

tRC
tRAS

VIL -

VIH CAS
VIL -

VIH M-A8
VIL -

----'

DQ VOH (DATA OUT)
VOL -

HIGH·Z

CAS BEFORE RAS REFRESH CYCLE
(W And AO to A8 are Don't Care)
~------------

RAS

tRC------------~

VIH VIL tCHR
vlH -

CAS
VIL -

DO vOH (DATA OUT)
VOL -

HIGH·Z

MOTOROLA MEMORY DATA
3-298

MCM94256A

HIDDEN REFRESH CYCLE (READ)

RAS

VIH Vil -

•

VIH CAS
Vil -

ADDRESSES
Vil -

W

VIH

-

Vil -

DO VOH (DATA OUT)
VOL -

HIDDEN REFRESH CYCLE (WRITE)

VIH -

--Ir--+I-----""

CAS

ADDRESSES

W

VIH Vil -

DO
(DATA IN)

L..:>L-"-"-"T"-"'-"WL.t--t+---""I-'L...l.L....>L...>L...lt..::i..-"-'''-''-'L..''--'''-''-..IL...lt..::i..-''-''-''~

VIH - ---+-"~____.Jr-------,I
Vil -

J<",,"""""""""""""""""""""""""""'!r'>'-'

- - - I - - - f "-------1 "'-"-'>L..,lj'-"-.......'-lL.........'-"-"'-"'-"-"'-"'-"-"'-"'-"
1+----

tDHR---~

MOTOROLA MEMORY DATA

3-299

MCM94266A

CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
tRAS
RAS

-------~

1 + - - - tRSH

VIHVIL -

•

VIHCAS
VIL -

ADDRESSES

VIHVIL -

READ CYCLE
DO VOH (DATA OUT)
VOL -

Vi

VIH VIL -

WRITE CYCLE

Vi

VIH VIL -

DO
(DATA IN)

VIH - ~~~~~~In':~In':""7I.~r-------i. ~""7<:"?"""","'"","'A7
VIL _

L.J.L..lL-l"-""..lL-l"-""..lL.:.\L..lL,..lI..;.\L..lL..JI1L-_ _ _ _ _.T "'-"-.lL-lo'-"-~UL.~L.J.L~

MOTOROLA MEMORY DATA

3-300

MCM94256A

DEVICE INITIALIZATION
On power-up an initial pause of 200 microseconds is required forthe internal substrate generator to establish the correct bias voltage. This is to be followed by a minimum of eight
active cycles of the row address strobe (RAS) to initialize all
dynamic nodes within the module. During an extended inactive state (greater than 8 milliseconds with the device powered
up), a wake up sequence of eight active cycles is necessary to
assure proper operation.

RAS transitions to inactive, it must remain inactive for a
minimum time of tRP to precharge the internal device circuitry
forthe next active cycle. DQ is valid, but not latched, as long as
the CAS clock is active. When the CAS clock transitions it
inactive, the output will switch to High Z, tOFF after inactive
transition.
WRITE CYCLE
The DRAM may be written with either an early write or page
mode early write cycle. Early write mode is discussed here,
while the page mode write operation is covered in another
section.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of Wto active
(VIL). Early write mode is distinguished by the active transition
of W, with respect to CAS. Minimum active time tRAS and
tCAS, and precharge time tRP apply to write mode, as in the
read mode.
An early write cycle is characterized by Wactive transition
at minimum time twcs before CAS active transition. Data In
(DQ) is referenced to CAS in an early write cycle. RAS and
CAS clocks must stay active for tRWL and tCWL'
respectively, after the start of the early write operation to
complete the cycle.

ADDRESSING THE RAM
The nine address pins on the device are time multiplexed
at the beginning of the memory cycle by two clocks row address strobe (RAS) and column address strobe (CAS), into
two separate 9-bit address fields. A total of eighteen address
bits, nine rows and nine columns, will decode one of the
262,144 word locations in the device. RAS active transition is
followed by CAS active transition (active = VIL, tRCD minimum) for all read or write cycles. The delay between RAS and
CAS active transitions, referred to as the multiplex window,
gives a system designer flexibility in setting up the external addresses into the RAM.
The external CAS signal is ignored until an internal RAS
signal is available. This gate feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are two other variations in addressing the module:
RAS only refresh cycle and CAS before RAS refresh
cycle. Both are discussed in separate sections that follow.

PAGE-MODE CYCLES
Page mode allows fast successive data operations at all
512 column locations on a selected row of the module. Read
access time in page mode (tCAC) is typically half the regular
RAS clock access time, tRAC. Page mode operation conSists
of keeping RAS active while toggling CAS between VIH and
VIL. The row is latched by RAS active transition, while each
CAS active transition allows selection of a new column location on the row.
The page mode cycle is initiated by a normal read or write
cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for
minimum tcp, while RAS remains low (VII). The second CAS
active transition while RAS is low initiates the first page mode
cycle (tPC). Either a read or write operation can be performed
in a page mode cycle, subject to the same conditions as in normal operation (previously described). These operations can
be intermixed in consecutive page mode cycles and performed in any order. The maximum number of consecutive
page mode cycles is limited by tRASP. Page mode operation
is ended when RAS transitions to inactive, coincident with or
following CAS inactive transition.

READ CYCLE
The DRAM may be read with either a normal random read
cycle or a page mode read cycle. The normal read cycle is outlined here, while the page mode cycle is discussed in a separate section.
The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (W) input level must be high
(VIH), tRCS (minimum) before the CAS active transition, to
enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
which are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex window. CAS controls read access time: CAS must be
active before or attRCD maximum to guarantee valid data out
(DQ) at tRAC (access time from RAS active transition). If the
tRCD maximum is exceeded, read access time is determined
by the CAS clock active transition (tCAC).
The RAS and CAS clocks must remain active for a
minimum time fo tRAS and teAS, respectively, to complete
the read cycle. Wmust remain high throughout the cycle, and
for time tRRH or tRCH after RAS or CAS inactive transition,
respectively, to maintain the data at that bit location. Once

REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge degrades with
time and temperature, thus each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in the
MCM94256A require refresh every 8 milliseconds.
Refresh is accomplished by cycling through the 512 row
addresses in sequence within the specified refresh time. All
the bits on a row are refreshed simultaneously when the row is
addressed. Distributed refresh implies a row refresh every

MOTOROLA MEMORY DATA

3-301

MCM94256A

•

15.6 microseconds for the MCM94256A. Burst refresh, a refresh of all 512 rows consecutively, must be performed every 8
milliseconds.
A normal read or write operation to the RAM will refresh all
the bits associated with the particular row decoded. Three other methods of refresh, RAS only refresh, CAS before RAS
refresh, and Hidden refresh are available on this device for
greater system flexibility.

end of a read or write cycle, while RAS cycles inactive for tRP
and back to active,starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1).
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested
with a CAS before RAS refresh counter test. This refresh
counter test is performed with read and write operations. During this test, the internal refresh counter generates the rowaddress, while the external address input supplies the column
address. The entire array is refreshed after 512 test cycles, as
indicated by the check data written in each row. See CAS before RAS refresh counter test cycle timing diagram.
The test can be performed only after a minimum of 8 CAS
before RAS initialization cycles. The test procedure is as
follows:

RAS-Only Refresh
RAS-only refresh consists of RAS transition to active,
latching the row address to be refreshed, while CAS remains
high (VIH) throughout the cycle. An external counter is
employed to ensure all rows are refreshed within the specified
limit.
CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order activates an internal refresh
counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh
cycle. The output buffer remains at the same state it was in
during the previous cycle (hidden refresh).

1. Write "O"s into all memory cells (normal write mode).
2. Select a column address, and read "0" out of the cell by
performing CAS before RAS refresh counter test, read
cycle. Repeat this operation 512 times.
3. Select a column address, and write "1" into the cell by performing CAS and RAS refresh counter test, write cycle.
Repeat this operation 512 times.
4. Read "1 "s (normal read mode), which were written at step
3.

Hidden Refresh
Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the

5. Repeat steps 1 to 4 using complement data.

MEMORY CYCLE

oQ-

REFRESH CYCLE

VALID oATA.Q\JT

HIGH·Z

Figure 1. Hidden Refresh Cycle

ORDERING INFORMATION
(Order by Full Part Number)

Full Part Number - MCM94256AS70
MCM94256AS80
MCM94256AS10

MOTOROLA MEMORY DATA
3-302

REFRESH CYCLE

General MOS Static RAMs •

MOTOROLA MEMORY DATA
4-1

•

MOTOROLA MEMORY DATA
4-2

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM2018A

Fast 16K Bit Static RAM
The MCM2018A is a 16,384 bit static random access memory organized as 2048
words by 8 bits, fabricated using Motorola's high-performance silicon-gate MOS
(HMOS) technology. It uses an innovative design approach which combines the
ease-of-use features of fully static operation (no external clocks or timing strobes
required) with the reduced standby power dissipation associated with clocked
memories. To the user this means low standby power dissipation without the need
for address setup and hold times, nor reduced data rates due to cycle times that
are longer than access times. Perfect for cache and sub-100 ns buffer memory systems, this high spead static RAM is intended for applications that damand superior
performance and reliability.
Chip enable (E) controls the power-down feature. It is not a clock but rather a
chip control that affects power consumption. In less than a cycle time after E goes
high, the part automatically reduces its power requirements and remains in this
low-power standby mode as long as E remains high. This feature provides significant system-level power savings.
The MCM2018A is in a 24-pin dual-in-line 300 mil wide package with the industry standard JEDEC approved pinout.
Single + 5 V Operetion, ± 10%
Fully Static: No Clock or Timing Strobe Required
Fast Access Time: MCM2018A-35=35 ns (Maximum)
MCM2018A-45=45 ns (Maximum)
Power Supply Current: 135 rnA Maximum (Active)
20 rnA Maximum (Standby)
Three-State Output
BLOCK DIAGRAM

•
•
•
•
•

4
3

A4
A5
A6
A7

23
22

AS
A9

DQ2
003
004
005
006
007

E

G
iii

•

MEMORY MATRIX
128x128

•
••

10
11
13
14
15

AD

Al

A2

A3

16
17

18
20
21

MOTOROLA MEMORY DATA
4-3

PIN ASSIGNMENT
A7

VCC

A6

AS

A5

A9

A4

iii

A3

G

A2

AID

Al

E

AD

007

DOD

006

001

D05

DQ2

DQ4

Vss

D03

PIN NAMES

AD-AID . . . . . . . . . . . . . • . . Address Input
DOO-DQ7 •••.••••••• Oats Input/Output
Vii. . . . . . . . . . . . . . . . . . . Writs Enable
G . . . . . . . . . . . . . . . . .. Output Enable
E . . . . . . . . . . . . . . . . . . . . Chip Enable
VCC . . . . . • • . . . • . • +5 V Power Supply
VSS . • . • . • • • . • • • . • . • . . . . Ground

19

AID

DOD
001

ROW
DECODER

PIN 24=VCC
PIN 12=VSS

•

PLASTIC
CASE 724

•

MCM2018A

MODE SELECTION
Mode

E

G

W

VCC Currant

DO

Standby

H

X

X

ISB

High Z

Read

L

L

H

ICC

0

Write Cycle

L

X

L

ICC

D

This device contains circuitry to protect the
inputs against damage due to high stetic
voltages or electric fields; however, it is advised that normal precautions ba taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit.

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage

•

Voltage on Any Pin With Respect to VSS

Symbol

Value

Unit

VCC

-0.5 to +7.0

V

Yin, Vout

-0.5 to +7.0

V

lout

±2O

rnA

PD

1.1

Watt

Tbias

-10to +80

°c

DC Output Current
Power Dissipation
Temperature Under Bias
Operating Temperature Range

TA
T stg

Storage Temperature Range

o to

+70

-65 to +150

°c
°c

NOTE: Permanent davice damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extanded periods 01 time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee=5.0 V ± 10%, TA=O to 70o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)

Input Voltage

Symbol

Min

Typ

Max

Unit

VCC

4.5

5.0

5.5

V

VSS

0

0

0

V

VIH

2.0

3.0

6.0

V

VIL

-0.5*

0

0.8

V

*The device will withstand undershoots to the - 2.5 volt level with a maximum pulse width 01 50 ns. This is periodically sampled rather then
100% tested.

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Current IVCC=5.5 V, Vin=GND to VCC)

Ilkg{/)

-1.0

1.0

p.A

Output Leakage Current (E=VIH or G=VIH, VI/O=GND to VCC)

Ilkg(O)

-1.0

1.0

p.A

ICC

-

135

mA

Parameter

Operating Power Supply Current (E=VIL, 11/0=0 rnA)
Standby Power Supply Current (E=VIH)

ISB

-

20

rnA

Output Low Voltage (tOL = 8.0 rnA)

VOL

-

0.4

V

Output High Voltage (/OH = -4.0 rnA)

VOH

2.4

-

V

Symbol

Typ

Max

Unit

Cin

3
5

5
7

pF

CliO

5

7

pF

CAPACITANCE (1= 1.0 MHz, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance

All Inputs Except E and DO
E

1/0 Capacitance

DO

MOTOROLA MEMORY DATA
4-4

MCM2018A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5 V ± 10%, TA=O to

+ 70o C,

Input Pulse Levels . . . . . . . . . . . . . . • . . • • . . . 0 and 3.0 V
Input Rise and Fall Times . . • . . . . . . . . . . • . . • . • . . . 5 n.

READ CYCLE (See Note

Unless Otherwise Noted)

Input and Output Timing Measurement Reference Levels. .. 1.5 V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

1)

MCM201BA-3& MCM201BA-4&

Symbol

Units Notes

Psrameter
Standard Altarnate

Min

Max

Min

Max

Address Valid to Address Valid (Read Cycle TIme)

tAVAV

tRC

35

-

46

-

ns

Address Valid to Output Valid (Address Access Time)

tAVOV

tAC

-

35

46

ns

Chip Enable Low to Chip Enable High (Reed Cycle TIme)

tELEH

tRC

35

-

46

-

ns

Chip Enable Low to Output Valid (Chip Enable Access TIme)

tELOV

tACS

35

-

46

ns

Output Enable Low to Output Valid (Output Enable Access TIme)

IGLOV

toE

-

20

-

20

ns

Chip Enable Low to Output Invalid (Chip Enable to Output Active)

tELOX

teLZ

5

-

5

-

ns

2

20

0

20

n.

2

Chip Enable High to OutpUt High Z (Chip Disable to Output
Disable)

teHOZ

teHZ

0

Output Enable Low to Output Invalid (Output Enable to Output
Active)

tGLOX

toLZ

0

-

0

-

ns

2

Output Enable High to Output High Z (Output Disable to Output
Disable)

IGHOZ

toHZ

0

20

0

20

ns

2

tAXOX

toH

5

tELICCH

tpu

0

-

0

-

ns

Address invelid to Output Invalid (Output Hold Time)
Chip Enable Low to Power Up

5

-

ns

-

Chip Enable High to Power Down
20
20
ns
tPD
tEHICCL
NOTES:
1. Transition time specification applies for all input signals. In addition to meeting the transition rata specification, all input signal. must transition
between VIL and VIH (or between VIH and VIL) in a monotonic manner.
2. Transition is measured ±200 mV from the steady state output voltage with the output loading specified in Figure 1.
3. In read cycle 2, all addresses are velid prior to or coincident with chip enable (E) transition low.

tAVAV

Ii
Jr'\.

A (ADDRESS)

~
tAVQV

tsHOZ

!---IGLQV-

)

~ (OUTPUT ENABLE)

Q IDATA

j

1\
tSLQ](

oun

kxxx~v

tAXQ](
OUTPUT DATA VALID

@

READ CYCLE 2 (VV=VIH, G=Vll; See Note 3 Above)

14------- t E L E H - - - - - - - - + - i
EICHIP ENABLE)

tELQ]( --114----+1
Q (DATA OUT)

OUTPUT DATA VALID
tELICCH -+_---1~

VCC SUPPLY
CURRENT

-------+,------------~
ICC
ISS

MOTOROLA MEMORY DATA
4-5

•

MCM2018A

WRITE CYCLE

(See Notes

1 and 2)
Symbol

•

MCM2018A-35 MCM2018A4i
Units Notes

Parameter

Standard Altarnete

Min

Max

Min

-

45

0

Address Valid to Address Valid (Write Cycle Time)

tAVAV

twc

35

Chip Enable Low to Write High (Chip Enable to End of Write)

tELWH

tEW

30

Address Valid to Chip Enable Low (Address Setup to Chip Enable)

tAVEL

tAS

0

Max

-

40

ns
ns

Address Valid to Write Low (Address Setup to Write)

tA,VWL

tAS

0

Address Valid to Write High

tAVWH

tAW

30

Write Low to Write High (Write Pulse Width)

twLWH

twP

30

Write High to Address Don't Care (Address Hold After End of Write)

lWHAX

twR

0

-

4

twHOX

twLZ

0

-

0

-

ns

Write High to Output Oon't Care (Output Active After End of Write)

ns

5

Write Low to Output High Z (Write Enable to Output Disable)

twLOZ

twHZ

0

20

0

20

ns

5

Date Valid to Write High (Data Setup to End of Write)

tDVWH

tDS

15

Write High to Data Don't Care (Date Hold After End of Write)

lWHDX

tDH

0

-

Output Enable High to Output High Z

tGHOZ

tOHZ

0

20

0
40

35
0

0

-

0

20

20

ns
ns
ns

3

ns

ns

3

ns

3,5

ns

NOTES:
1. Write enable (W) must be high during all address transitions.
2. If the chip enable (E) low transition occurs simultanaously with the write enable (W) trensition, the output remains in a high impadance
atete.
3. Both chip enable (E) and write enable (iN! must be active (low) to write data into the memory. Either signal can terminate the write cycle
by going high. Data in setup and hold timing should be referencad to the rising edge of the signal that terminates the write.
4. twHAX is measured from the earlier of, chip enable (E) or write enable (W) going high to the end of write evele.
5. Output enable (G) can be either low or high during a write cycle. If chip enable (E) and G are both low during this period then the data
input/output (001 pins are in the output stste. Under these conditions input signals of opposite phase to the outputs must not be applied.

WRITE CYCLE 1 {Vii

Controlled)

!+----------AVAV

------------.J

A (ADDRESS)

...-

~--------IElWH ---------.j~---

r(CHIP ENABLE)
)4------twlWH ------I~

W\WRITE ENABlEI

~ (OUTPUT ENABLE)

14--+- IWlQZ
IWHQ)(
Q

(DATA

oun

HIGH IMPEDANCE

IQVWH --~~--t-twHDX
DATA IN VAUD

D (DATA IN)

MOTOROLA MEMORY DATA

MCM2018A

WRITE CYCLE 2

fe Controlledl

J+----------IAVAV------------.J
A (ADDRESS!

--------l£LwH--------...·~----i*twHAX

IAVEl-t~~....

EICIRP ENABLE)
...-----twLWH-----~
WIWRITE ENABLE!

i+-----I----IAVWH--------.....

11 /OUTPUT ENABLE!

14--t--twLoz
Hl6H IMPEDANCE

Q IDATA OUT) ""':=';;;;;';=;;:"'0{

toYWH--.......--*-twHDx
D /OATA IN)

DATA IN VAUD

5V

480

Q------.

30 pf

= ONCLUDING

255

SCOPE AND JIG)

Figura 1. Output Load

ORDERING INFORMATION

(Order by Full Part Number)

T. .

CM

Motorola Memory PrefiX _ _ _ _ _ _
Psrt Number

T

r r ' - - - - - - - s p e e d (35=36 ns. 46=46 nsl

-------------......1

'---------- Package (N=3O().mil Plasticl

Full Part Numbers-MCM2018AN36
MCM2018AN46

MOTOROLA MEMORY DATA

4-7

•

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

IMCM60L256A-C I

Advance Information

32K X 8 Bit CMOS Static Random
Access Memory
Extended Temperature Range: - 40 to 86°C

4

The MCM60L256A-C is a 262,144 bit low-power static random access memory organized as 32,768 words of 8 bits, fabricated using silicon-gate CMOS technology. Static
design eliminates the need for external clocks or timing strobes, while CMOS circuitry
reduces power consumption and provides greater reliability. The operating current is
5 mA/MHz (typ) and the cycle time is 100 ns. For long cycle times (> 100 ns), the automatic power down (APD) circuitry will temporarily shut down various power consuming
circuits, theraby reducing the active power consumption.
Chip enable (E) controls the power-down feature. It is not a clock but rather a chip
control that affects power consumption. When E is a logic high, the part is placed in low
power standby mode. The maximum standby current is 2 pA (TA = 25°C). Chip enable
also controls the date retention mode. Another control feature, output enable (G) allows
access to the mamory contants as fast as 50 ns. Thus the MCM60L.256A-C is suitable for
usa in various microprocessor application systems where high speed, low power, and
battery backup ara required.
The MCM60L.256A-C is offered in a 2S pin, 600 mil plastic dual-in-line package and a
330 mil gull-wing SO package.

a"SOG

1

CASE 'J&1H

PIN ASSIGNMENT

Single 5 V Supply, ± 10%
• 32K x 8 Organization
• Fully Static - No Clock or Timing Strobes Necessary
• Low Power Dissipation-27.5 mW/MHz (Typical Active)
• Output Enable and Chip Enable Inputs for More System Design Flexibility and Low
Power Stendby Mode
• Battery Backup capability (Maximum Standby Current=2 pA @ 25°C)
• Data Ratention Supply Voltage = 2.0 V to 5.5 V
• All Inputs and Outputs Are TTL Compatible
• Three Stata Outputs
• Fast Access Time: MCM60L.256A-Cl0= 100 ns (Max)
•

BLOCK DIAGRAM

A14

1.

28

Vee

A12

2

27

i

A7 I 3

28

A13

A8 I 4

25

A8

A5 I 5

24

A8

A4 I 8

23

All

11

A3 I 7

22

A2 I 8

21

AID

Al I 8
AD I 10

20

I

18

D07

DOD I 11

18

D08

DOl 112

17

D05

DD2 I 13

18

D04

Vss I

15

D03

14

A5
A8
A7 ----.A--_--'
A8
A8
AI1 ---...c...._--,
A12 - - - ' .....- - ,

MEMORY ARRAY
1512 ROWS AND
512 COI.UIIIISl

-Vee

-Vss

PIN NAMES

AO-AI4 . . . . . . . . . . . . . . Add_
W .. .. .. .. .. .. .. WrIte Enable
'E. . . . . . . . . . . . . . . • Chip Enable
'G .. .. .. .. .. .. • Output Enable
~DQ7 ....... DMaI~/Output

vcc ......... + 5 V P..-r Supply
vss ................ Ground

A13
A14

DOD
D07

-H--I-I >=-1

i
a---dL..-l

ThIs cIc>c:u"*It containo inIormInIon on 8

now product. SpacIIicationo 8nd information _

8 ..

subject to chengo without notice.

MOTOROLA MEMORY DATA

4-8

MCM60L256A-C

TRUTH TABLE

E

G

iN

H

X
H
L
X

X

L

L
L

H

H
L

Supply Current

Mode
Not Selected
OutpUt Disabled
Read
Write

ISB
ICC
ICC
ICC

I/O Pin
High Z
High Z
Dout
Din

This device contains circuitry to protect the
inputs against damage due to high static
voltages or alactrlc fields; however, It is adviaad that normal precautions be tsken to
avoid application of any voltsge hlghsr than
maximum rated voltsges to this hlghimpedance circuit.

X=don't care

ABSOLUTE MAXIMUM RATINGS (See Notel
Rating
Symbol
Power Supply Voltage
Voltage to Any Pin with Respect to VSS
Power Dissipation ITA = 25°CI

Value

Unit

VCC

-0.3 to +7.0

V

Yin, Vout

-0.5 to VCC+0.5

V

Po

1.0
0.6

W

PDIP
SOG

•

Oparating Temperature

-40 to +85
°c
TA
·C
-65 to +150
Tato
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS ara
exceeded. Functional operation should be raatrictad to RECOMMENDED
OPERATING CONDITIONS. Exposura to higher than racommandad voltsgaa for
extended periods of time could affect device reliabHity.
Storage Temparature

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%, TA= -40 to 85oe, Unless Otherwise Notedl
RECOMMENDED OPERATING CONDITIONS
Param_

Symbol

Min

Typ

Max

Unit

Supply Voltage (Oparating Voltsge Range)

VCC

4.6

5.0

6.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

Input Low Vo!tsga

VIL

-0.3*

-

0.8

V

*VIL (mini = -0.3 V de; VIL (mini = -3.0 V ac (pulsa width ;,;50 nsl

DC CHARACTERISTICS
Symbol

Min

Typ

Max

Unit

Input Leakage Currant (All Inputs, Yin = 0 to VCCI

Parameter

Ilkgm

<0.01

±1.0

p.A

Output Leakage Currant (E=VIH or G=VIH or W=VIL, Vout=O to VCC)
Operating Curram (Read Cyclel
(E=VIL, W=VIH, Other Input=VIHIVIL, 10ut=0 mAl
tAVQV=1 pS
tAVQV=loo ns

Ilkll(OI

-

<0.01

±1.0

(E=0.2 V, iiii=VCC-0.2 V, Other Input=VCC-0.2 V/0.2 V,
lout=O mAl
tAVQV=1 pS
tAVQV= 100 ns

ICCAZ

ICCAI

-

10

16
70

6

8
60

-

Output Low Vo!tsga HOL =4.0 mAl

VOL

-

Output High Voltage HOH = - 1.0 mAl

VOH

2.4

-

Symbol
Cin

Standby Currant (E=VIHI

ISBI

Stsndby Currant (El!:VCC-0.2 V, VCC=2.0 to 5.5 VI

ISB2
(TA=25'CI

p.A

mA

-

3.0

mA

2

100
2

p.A

0.4

V

-

V

Min

Max

Unit

-

10

pF

10

pF

Typical values ara referenced to TA=25°C and VCC=5.0 V

CAPACITANCE (f=1 MHz TA=25°C Periodically Sampled Rather Than 100% Tastedl
Characteriatlc
Input Capacitance (Vin = 0 VI
110 Capacitsnce (VIIO=O VI

All Inputs Except DO
DQ

MOTOROLA MEMORY DATA
4-9

CliO

MCM60L256A-C

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ±10%, TA= -40 to 86°C, Unless Othelwise Noted)
Input Pulae LewIs . • . . . . . . . • • . • . . . . . . . . 0.6 V, 2.4 V
Input Rlae/Fall Time • • • • . • • . • • . • • • • • • • • • • • . • . 5 n.
Input Timing Measurement Reference LewIs. . . . . . . . . . 1.5 V

Output Tuning Measurement Reference LewIs . . . . . 0.8 and 2.2 V
Output load. . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1

READ CYCLE ISee Nota 1)
Param_

•

Symbol

Read Cycle Time
Address Access Time
"EAccessTuna

AIt
Symbol

tAVAV
tAVav
tELQV
tGLQV
tAXOX

~Accessnme

OutpUt Hold from Address Change
Chip Enable to Output Low-Z
OutpUt Enable to OutpUt Low-Z
Chip Ensble to Output Hlgh-Z
Output Enable to Output HIgh-Z

tRC
tM
tAC

teLOX
tGLOX
tEHOZ

toE
toH
tcLZ
toLZ
tCHZ

tGHOZ

toHZ

Min

Mill<

Unit

Not..

100

ns

-

100
100
50

10
10
5
0
0

-

-

35

n.
n.
n.
n8
ns
ns
ns

35

ns

-

2.3
2.3
2,3
2,3

NOTES:
1. W Ie high at all times for read cycles.
2. All hlgh-Z and Iow-Z parameters are considered in a high or low impedance atate when tha output has made a 100 mV transition from tha
previoua ataady atate voltage.

3. Thasa paramatars are parlodlcally sampled and not 100% testad.

READ CYCLE

...

IAVQV

E(CHIP ENABLEI

\.
II

_IEHOZ_

I£LQV

1-~HOZ-

ii (OUTPUT ENABLEI
_IGLQV
Q (DATA

oun

IAXQX-.-.

HIGH·Z

XXX.X.
........ IGLQX .-.
k---I£LQX_

5.0 V

TEST POINT <>-~"1--+"'-+

100 pF*

*Includes jig capacitance.

2.4 k

lN914B
OR EQUIV.

-=-

Figure 1. AC Test Load

MOTOROLA MEMORY DATA
4-10

OATA VALID

~

MCM60L256A-C

WRITE CYCLE 1 AND 2 (See Note 1)
P....m_.

Symbol

AIt
Symbol

Min

Max

Unit

Notes

n8

-

Addreaa Setup Tima

tAVWL/tAVEL

twe
tAS

100

Addreaa Valid to End of Writa

tAVWH/tAVEH

tAW

80

Writa Pulse Width

twLWH
tOVWH/tOVEH

twp

80

tow

36

toH
twHZ

0

-

0

26

twLZ

10

Writa Cycle Time

tAVAV

Data Valid to End of Writa
Data Hold Tima
Writa Low to Output in High-Z

twHOX/tEHOX

Writa High to Output Low.z

twLoz
twHox

Writa R8COV8IY Tima
Chip Enable to End of Writa

twHAX/tEHAX
tELWH/tELEH

0

twR

0

tcw

80

-

n8

ns
lIB
lIB
lIB
lIB
lIB
lIB
lIB

2

3,4
3,4

5

-

NOTES:
1. Outputs are in high impedance stata if 1.; is high during Writa Cycle.
2. A writa occurs during the overlap (twp) of a low 'E and a low W. If Wgoaa low prior to 'E low than outputs wiD remain in a high impedance

stata.
3. All high-Z and Iow-Z paramaters are considared in a high 0' low impedance stata when the outputs have made a 100 mV trenaltion from
the p<8Vious steady stata voltage.
4. These parame\8nlare periodically sampled and not 100% tested.
5. twR is _red from the earlier of E or W going high to the end of writa cycle.

WRITE CYCLE 1 IW CONTROLLED)
.---------IAVAV--------+I

A IADORESS)
~----------------~VWH------------_+4--.~

~~-r~~,~~-------~n---------.~r~~~~_r~~

E (ClIP EIIAIII.E)
1+----IWlWH-------+I

, !WRITE ENABLE)

o IOATA IN)

Q IDATA

DATA VALID

-<

HIGH-Z

OUT) ___......:H:;:;IGH;;;;,:.Z_ _

MOTOROLA MEMORY DATA
4-11

•

MCM60L256A-C

WRITE CYCLE 2

(E Controlled)
tAVAV

~
I\.

A IADDRESS)'

J~

j+--tAVEL

tEHAX-

tElEH
tAVEH

I ICHIP ENABlE)

jf'WLWH

•

WIWRITE ENABLE)

\~~'J~

nIOATA OUT)

///////
HIGH IMPEDANCE

HIGH IMPEDANCE

E-

.1

IEHDX

.J.

DATA VALID

D !DATA INI

DATA RETENTION CHARACTERISTICS ITA - -40 to 86°CI
Parametar

Symbol

Min

VDR

2.0

ICCDR

-

VCC for Data Retention (E~VCC-O.2 VI
Dete Retention Currant (E~VCC-O.2 VI

VCC=3.0V
VCC=5.6V

Chip Disable to Data Retention Time

-

tCDR

0

tree

tAVAV*

Operation Recovery TIme

Typ

-

Max
5.5

Unit

50
100

pA

-

V

n8
ns

*tAVAV= Read Cycle TIme

DATA RETENTION MODE

....,.--------1--YCC

DATA RETENTION MODE
VDR~2.0

---t-~--------

Y

,_ /lzzf·:~,-____I_~Y": :DR:" -0_'2_V

___

~;,.-~\\\\\

NOTE: If the VIH of E is 2.4 V in operation, IS81 current flows during the period thet the VCC voltage is decreasing from 4.6 V to 2.4 V.

MOTOROLA MEMORY DATA
4-12

MCM60L256A-C

1.5

~
_

~

1.4
1.3

~w
'"~

1.2

1!i
:c

1.0

§?

1.5
TA = 25°C

/"

1.1

i

0.9

1

0.8

~

O. 7

4

--

4.5

V

./'"

o:
_

~

1.2

'"
~

§?

1. 1

~

i

1.0
0.9

~

U.8

w

..... /'"
V

0.7

7.5

5.5
6.5
VCC, SUPPLY VOLTAGE IYOLTS)

TA=25°C
1.4
1.3

Figure 1. Input High Voltage versuB Supply Voltage

4

/'

1/

/'"

4.5

f-'"

.....- ----

6.5
5.5
Vcc. SUPPLY VOLTAGE IYOLTSI

7.5

Figure 2. Input Low Voltage versus Supply Voltage

1.6

!

lA

:E

II:

C

!!;

....

1.2

=

1.0

~

II:

u

'"
!c
IE

.

-

-

0.8

r--- r--

15

c
oi:
u
E

0.6
0.4
-60

-40

-20

40
60
80
20
TA. AMBIENT TEMPERATURE lOCI

100

120

Figure 3. Operating Current versus Ambient
Temperature

100
is

!!lc

I
15

1

...I...=

-

...z

'"~

'"N

10

1

O. 1

...

.!!.'

o

-60

-40

-20

20
40
60
80
TA. AMBIENT TEMPERATURE lOCI

100

120

Figure 4. IS81 Standby Current versus Ambient
Temperature

0.0 1
-60 -40 -20

20
40
60
80
TA. AMIllfNT TEMPERATURE 1°C)

100

120 140

Figure 6. IS82 Standby Current versus Ambient
Temperature

MOTOROLA MEMORY DATA
4-13

MCM60L266A-C

.. 1.4
1.8

1•8

4

~

IIi

5

;..
CD

1.2

2

1.0

0

.".

0.8
0.8

•

o

o

I

o.8

.a

0.2

i

~I-'"
.".

C 0.2

~

8

i--"" I--"""

i.,....-' V

0.4

V

4

10

OA

......

i--"'

1-

o

o

12

~

.L- ~

V

4

I. fREQUENCY IMHzI

8
8
I. fREQUENCY IMHzl

10

12

Figure 7. Operating Current wraue Frequency !Write)

Figure 8. Low Power Operating Current wraue
Frequency (Reed)

1.8

I::

TA=25oe

Ii 1.0
& 0.8
>-

!

J

-

./"

,/""

0.8

Vi-""

. / '"""

0.4
0.2

o
2

2.5

3.5

4

5.5

4.5

Vee. SUPPLY VUlTAGE IVOLTSl

Figure 8. Low Power IS82 Standby Current wraue
SUpply Voltege

F

1.5

-11.4

8

1.3

I

I 1.4
I 1.2

1.2

11.

1

1

""-

-

1.0

0.9

J

O.8
O.7
4.5

:;l

!

1.0

I-I-- I-J

;

I--

0.8

--- -

O.8

4.75

5

5.25

~

-H

-~

-W

0

W

~

"

"

100

lW

TA. AMIIlENT TEllPERATIIAE I"el

Vee. SUPPLY VOLTAGE tYOlTSl

Figure 10. Acc_ Time V81'8US Ambient Temperature

Figure •• Ac_ Time veraue Supply Voltege

MOTOROLA MEMORY DATA
4-14

MCM60L256A-C

ORDERING INFORMATION

11

(Order by Full Pert Number)
MCM

Motorola Memory Prefix

~

T
III2Ii8A

Part Number - - - - - - - - - '

X

X

XX

XX

T

_

....... '02-T.... _ _- _

Speed (10= 100 118)

Operating Temperatura Range
IC = Industrial Range, "-40 to EOC)

'--------Package IP=Plastic DIP, F=GuiI-Wing SO)
Full Part Number- MCM60l.256APC10
MCM60L266AFC10
MCM60L266AFC10R2

MOTOROLA MEMORY DATA
4-15

•

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

IMCM60L256A-V I

Advance Information

32K X 8 Bit CMOS Static Random
Access Memory
Extended Temperature Range: -40 to 105°C

•

The MCM60I:l56A-V is a 262,144 bit low-power static random access memory organized as 32,768 words of 8 bits, fabricated using allicon-gate CMOS technology. Static
design eliminates the need for extemal clocks or timing atrobes, while CMOS circuitry
reducea power conaumption and provides greater reliability. The operating current is
5 mA/MHz (typ) and the cycle time is 100 ns. For long cycle times (>100 ns), the automatic power down (APD) circuitry will temporarily shut down various power consuming
circuits, thereby reducing the active power consumption.
Chip enable (E) controls the power-down feature. It is not a clock but rather a chip
control that affects power consumption. When E is a logic high, the part is placed in low
power standby mode. The maximum standby current is 2 pA (TA =25°C). Chip enable
also controls the date retention mode. Another control feature, output enable {ii) allows
access to the memory contents as fast as 50 ns. Thus the MCM60I:l56A-V Is suitable for
use in various microprocessor application systams where high speed, low power, and
battery backup are required.
The MCM60I:l56A-V is offered in a 28 pin, 600 mil plastic dual-in-line package and a
330 mil gull-wing SO package.
Single 5 V Supply, ± 10%
• 32K x 8 Organization
• Fully Ststic - No Clock or Timing Strobes Necessary
• Low Power Dissipation-27.5 mW/MHz (Typical Active)
• Output Enable and Chip Enable Inputs for More System Dasign Flexibility and
Power Stendby Mode
• Battery Backup Capability (Maximum Stendby Current =2 pA @ 25°C)
• Date Retention Supply Voltage =2.0 V to 5.5 V
• All Inputs and Outputs Are TTL Compatible
• Three Stete Outputs
• Fast Access Time: MCM50I:l56A-V10 = 100 ns (Max)

PIN ASSIGNMENT

Vee

A12

i
A13

A7

•

AS

A8

AS

AI

A4

Low

A3
A2
Al

BLOCK DIAGRAM
A5

A14

r-----...,

AD

007

DUO

D08

001

QQ5

DD2

004

Vss

AS

L--_ _-I

003

A7
A8
AS

All

MEMORY ARRAY
(512 ROWS AND
512 eOLUMNs)

-Vee
PIN NAMES

-Vss

AG-A14 • • • . • • • • • • • • • • AdcIraoe

W. . . . . . . . . . . . . .

Write Enable

r. . . . . . . . . . . . . . . .Chip Enable

AI2

~ • . . • • • . . • • . • • Output Enable
000-0Q7 ••..••. Data Input/Output
VCC •..•••.•• +5 V Power Supply
VSS ••.•••••••.••••• Ground

AI3
AI4
DOD
007

i
&---<1.....-/
This document contal.. Informotlon on • new product. Specilicatlona and informotlon _

.... aubjoct to change without notice.

MOTOROLA MEMORY DATA
4-16

MCM60L256A-V

TRUTH TABLE
E

11

W

Mode

Supply Current

1/0 Pin

H

X

X

Not Selected

ISB

HighZ

L

H

H

Output Disabled

ICC

HighZ

L

L

H

Reed

ICC

Dout

L

X

L

Write

ICC

Ojn

This device conteins circuitry to protect the
inpute against damage due to high etatic
voItagee or electric fields; h0W8Y8r, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltagee to this highimpsdance circuit.

X=dcn't care
ABSOLUTE MAXIMUM RATINGS (See Note)
Symbol

Value

Unit

VCC

-0.3 to +7.0

V

Vln, Vout

-0.5 to VCC+0.5

V

Po

1.0
0.6

W

Operating Temperature

TA

-40 to +105

DC

Storage Temperature

Tato

-65 to +150

DC

Retina
Power Supply Voltage
Voltaga to Any Pin with Reepact to VSS

Power Diesipetion (TA =25DC)

PDIP
SOG

•

NOTE: Permanant device dsrnege may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional oparation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended pariods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ±10%, TA= -40 to I05DC, Unless Otharwisa Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Oparating Voltage Range)

Param_

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

VCC+0.3

V

Input Low Voltage

VIL

-0.3*

0.8

V

Symbol

Min

-

*VIL (min) = - 0.3 V de; VIL (min) = - 3.0 V 8C (pulse width ,,50 ns)
DC CHARACTERISTICS
Parametar

Typ

Max

Unit

<0.01

±1.0

,.A

<0.01

±1.0

Output Low Voltage IIOL =4.0 mAl

VOL

-

0.4

V

Output High Voltage IIOH = -1.0 mAl

VOH

2.4

-

-

V

Symbol

Min

Max

Unit

10

pF

10

pF

Input Leakage Current (A1llnpute, Vln=O to VCC)

Ilkg(1)

Output Leekege Current (E=VIH or 'G=VIH or W=VIL, Vout=O to Vce)

IlkI(O)

Opareting Current (Reed Cycle)
fE=VIL, W=VIH, Other Input=VIHIVIL, lout=O mAl

ICCAI
tAVQV=1 psi
tAVOV=I00 ns

JE=0.2 V, W=VCC-0.2 V, Other Input=VCC-0.2 V/0.2 V,
lout=OmA)
tAVOV=1 psi
tAVQV= 100 ns

ICCA2

Standby Current (E = VIH)

ISBI

Standby Current (E:':VCC-0.2 V, VCC=2.0 to 5.5 V)

ISB2
(TA=25DC)

,.A
mA

10

5

2
-

15
70
8

60
3.0

mA

100
2

,.A

Typical values are referenced to TA=25DC and VCC=5.0 V
CAPACITANCE (f= 1 MHz TA =25DC Periodically Sampled Rather Than 100% Teeted)
Characterlatlc
Input Capacitance (Vin = 0 VI

All InpulS Except DQ

110 Capacitanca (VIIO=O V)

DO

MOTOROLA MEMORY DATA
4-17

ein
CliO

-

MCM60L266A-V

AC OPERATING CONDITIONS AND CHARACTERISTICS
IVCC=5.0 V ±10'l6, TA= -40 to 105°C, Unless OtherwIse Noted)
Input Pulle LewIs ••.••••.•.••.•.••..•. 0.8 V, 2.4 V
Input RIIe/FaU TIme • • • • • • • • • • • • • • • • • • • • • • • • • 6 ns
Input TimIng Measurement Reference LewIs. • . • . • • • • • 1.& V

OU1pUt Timing Mealurament Reference LewIs. . • • .0.8 and 2.2 V
Output Load. • • • • • • • . • • • • • • • • • • • • • • • • See F"lgUre 1

-

READ CYCLE (See Note II

......
R8IId Cycle Tome

•

Symbol

AIt
Symbol

tAVAV
tAVQV

!ftC
tM

IlAcceaTIIIIII

tELQV

tAC

~AcceaTime
Output Hold from Add-. Change

tGLQV
tAXQX

toE
toH

Chip Enable to Output Low-Z

tELQX

!eLZ

Output Enable to OU1pUt Low-Z

tGLQX

toLZ

Chip Enable to Output HIgIt-Z

tEHQZ
tGHQZ

!eHZ
toHZ

AddIeu Accea Time

Output Enable to OU1pUt HIgh-Z

Min

Max

100

-

-

100

Unit

N_

ns

-

"-

ne

100

III

50

III

-

III

0

3&

III

0

3&

III

10
10
6

III

III

-

2,3
2,3
2,3
2,3

NOTES:
1. W Is high at aN timaa for read cyctes.
2. AU hlglt-Z and Iow-Z parameters are conaldelad In a high or low Impedance _
previous -ely voltage.
3. Thaaa parametars are periodically aampIed and not 100% taatad.

when tha 0U1pUt haa made a 100 mV tranIItIon from tha

READ CYCLE
----------IAVAV

~

- - - - - - - - -....

AIAIIIIIIESSI _ _ _ _ _ __
""------IAVOV------I·~'

E(CHIP EIIAIIlEI

14---- ta.OV----+i

6 (OUTPUT ENABlEI
_IGLQV---.j
Q (DATA

---+--+----(1

DUn _ _..;.H;;.;IG;;.H.;;.Z

IGLOX

'ELOX-

5.0 Y

TESTPOI/IT--.............................
100 pF*

*Includes jig capacitance.

2.4 k

.".

,.,48

OR EQUIV.

.".

Figure 1. AC Test Loed

MOTOROLA MEMORY DATA
4-18

MCM60L256A-V

WRITE CYCLE 1 AND 2 (See Nota 1)
Ait

Min

Max

Unit

tAVAV

!Wc

100

-

ns

Addrass Setup Tims

tAVWL/tAVEL

tAS

0

Addrass Valid to End of Write

tAVWH/tAVEH

tAW

80

IWLWH

!WP

80

-

ns

OelS Valid to End of Write

tOVWH/tOVEH

tow

35

-

ns

OelS Hold Tims

Symbol

Parameter
Write Cycle Time

Write Pulse Wodth

Symbol

-

ns

-

-

ns

-

!WHOx/tEHOX

tOH

0

-

ns

Write Low to Output In High-Z

lWLaz

twHZ

0

30

ns

Write High to Output Low-Z

!WHax

twLZ

10

twHAX/tEHAX

twR

0

-

tELWH/tELEH

tew

80

-

Write Recovery Tims
Chip Enable to End of Write

N_

2

-

ns

3,4
3,4
5

ns

-

ns

NOTES:
1. Outputs are in high impsdanca 81818 if iI is high during Write Cycle.
2. A wrile occurs during the overlap Itwp' of a low 'E and a low W. If Wgoes low prior to E low then outputs will remain In a high impsdance
81818.
3. All high-Z and Iow-Z paremetara are considerad in a high or low impedance 81818 when the outputs have mada a 100 mV trensition from
the previous stasdy 81818 voltage.
4. These paremstare are periodically sernpled and not 100% taetsd.
5. twR is measured from the earlier of E or W going high to the end of write cycle.

WRITE CYCLE 1

ew CONTROLLED)

A (ADDRESSI

f ICHI' ENABLEI

IV IWRITE ENABUI

o (DATA IN'

o !DATA DUn

---==---<

MOTOROLA MEMORY DATA
4-19

•

MCM60L256A-V

WRITE CYCLE 2

(E Controlled)
tAYAY

~

A IADDRESS)

J~

f4---tAYEL

tEHAX-

tELEH
tAYEH

"

[ICHIP ENABLE)
twLWH

iii IWllITE ENABLE)

II

\\\\\\\\ \\~

o(DATA DUT)

///////
HIGH IMPEDANCE

HIGH IMPEDANCE

.1

,l:=:.tDYEH

I

oillATA IN)

DATA RETENTION CHARACTERISTICS ITA = -40 to t05°C)
Param_
VCC for Data Ratantion I'E2:VCC-0.2 VI
Data Retention Currant Il2: VCC - 0.2 VI

tEHDX

I

DATAYAUD

Symbol

MIn

Typ

Max

UnIt

VDR

2.0

-

6.6
60
tOO

p.A

ICCDR

-

Chip Disable to Data Ratantion TIme

tcDR

0

-

Operation Recovery TIme

tree

tAVAV*

-

VCC=3.0V
VCC=5.5V

-

V

ns
ne

*tAVAV=Read Cycle Time

DATA RETENTION MODE

~

vt""I----

~~,

,. . . zzzzT. \

...,..

DATA RETENTIOII MODE

~

~:

! . . . - .."

1\\\\\

/ ..

NOTE: If the VIH of ( is 2.4 V in operation, ISBt currant flows during the period thet the VCC voltage is declM8ing from 4.5 V to 2.4 V.

MOTOROLA MEMORY DATA
4-20

MCM60L256A-V

1.5

1.5

I: :
II

~

1.2

1.0

I---

..-/

/

.....
..,/'

1
1.

~ 0.9

1

TA=25°C

v

4.5

1.2

~

!:i

1. 1

~

1.0

!i!

~ 0.9
j 0.8

0.8
0.7
4

_

I

!i

~

TA=25°C
1.4
1.3

0.7
4

7.5

5.5
8
8.5
VCe. SUPPLY VOLTAGE (VOLTSI

Figura 1. Input High Voltage versus Supply Voltage

..,/'

I-"'"

~

~

/'

/

4.5

5.5
6.5
VCC. SUPPLY VOLTAGE (vOLTSI

7.5

Figure 2. Input Low VGltage versus Supply Voltage

6

4

2

-

-

0

8

0.4

-60

-40

-20

I--

o 20 40 80 60
TA< AMBIENT TEMPERATURE lOCI

--

100

120

Figure 3. Operating Current versus Ambient
Temperature

10
2r-~---r--~--r-~---r--~--r--1

0.1

OL-~

-60

__-L__

-40

-20

~

__

L-~

20

__- L__

40

60

~

60

__

0.01
-60 -40 -20

L-~

100

120

TA. AMBIENT TEMPERATURE lOCI

20

40

60

60

100

120 140

TA. AMBIENT TEMPERATURE lOCI

Figure 5. ISB2 Standby Current versus Ambient
Temperatura

Figure 4. ISB1 Standby Current versus Ambient
Temperature

MOTOROLA MEMORY DATA
4-21

•

MCM60l.256A-V

1.6

1.8
5

;
I!!i

1.2

I

1.0

is

::::I

II

1.4

'"~

i...
u

Iii

"...-'

0.8

u

...-'

,.. V

0.8

OA

II:
II:

"

~

0.6

!i

OA

.......-

--

...-'

I-"

1-

~ 0.2

~

~

•

0.8

!C
II:

-

1.2
1.0

::::I

u

,. ...-'r-"

0.2

lA

4

o
o

12

10

4

I. FREQUENCY tMHz}

Figure •• Low Power Operetlng Current versus
Frequency (Read)

8
6
I. FREQUENCY tMHz!

12

10

Figure 7. Operetlng Current versus Frequency (Write)

1.8

I: :
I!

0.8

~

OA

j

0.2

TA=25°C

L

1.0

0.8

",....

/

_f--

..--

",....

V

o
2

3

2.5

3.5
4
4.5
VCC. SUPPLY VOLTAGE IVIII.TSI

5.&

Figure 8. Low Power ISB2 Standby Current versus
Supply Voltage

I:

I.

I

I

1.8

1.5

!

I
)

...

!

1.2

1_
1.
1.0

-

0.9
0.8

O.7
4.5

lA

1.2

!a

1.0

)

O.

I

5.5

i-""'"

~

8

O.6
5.25

4.75

--- -- -V

-60

-40

-20

20

40

60

80

-

100

120

TA. AMBIENT TEIIPEIIATURE ("CI

VCC. SUPPlY VIII.TA6E IVOlTS)

Figure 9. Ace... Time versus Supply Voltage

Figure 10. Ace... Time versus Ambient Temperature

MOTOROLA MEMORY DATA
4-22

MCM60L256A-V

ORDERING INFORMATION
(Order by Full Pert Number)

MCM

Motorola Memory

PrefiX~

T 1T
8OI.2Ii8A

X

X

XX

XX

T _ _ '''.T.............. ....

Pan Number - - - - - - - - - - - '

Speed (10 =100 1'181

Operating Temperature Ranga
(V=Extended Range, -40 to 1I16°CI

l..-------Packaga (P=Plaatic DIP, F=Gull-Wing SOl

Full Pan Number-MCMeOL256APV10
MCM80L256AFV10
MCMeOL256AFV10R2

MOTOROLA MEMORY DATA
4-23

•

•

MOTOROLA MEMORY DATA
4-24

CMOS Fast Static RAMs

MOTOROLA MEMORY DATA
5-1

II

•

MOTOROLA MEMORY DATA

5-2

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM6205
32K X 9 Bit Fast Static RAM
The MCM6205 is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is available in plastic dual-in-line and plastic small-ouUine J-Ieaded packages.
• Single 5 V ±1 0% Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• Fast Access Times: 15,17,20,25 and 35 ns
• Equal Address and Chip Enable Access Times
• Output Enable (G) Feature for Increased System Flexibility and to Eliminate
Bus Contention Problems
• Low Power Operation: 140 -170 rnA Maximum ac
• Fully TIL-Compatible - Three-State Output

BLOCK DIAGRAM

MEMORY MATRIX

PPACKAGE
3OO-MIL PLASTIC
CASE853-G1

JPACKAGE
300-MILSOJ
CASE857-G2

PIN ASSIGNMENT

NC

VCC

NC

A14

AS

E2

A7

iii

A6

A13

A5

A9

A4

Al0

.256 ROWS x

A3

All

121h'9 COLUMNS

A2

G

COLUMN 1/0

Al

A12

AO

ET

000

DQ8

DOl

007

002

DQ6

DQ3

DQ5

VSS

DQ4

COLUMN DECODER

PIN NAMES

ET--.--""'
E2

Ao-A14 .............. Address Input
DQO-D06 ...... Data Input I Ou1put

iii
G'----.:lL-J

iii ..................... Write Enable
G ................... Output Enable

8, E2 •...•.•.•........

Chip Enable
NC .................. No Connection
VCC .. • . .. • . .. Power Supply (+ 5 V)
VSS ........•.............. Ground

MOTOROLA MEMORY DATA

MCM6206

This device contains circu~ry to protect the inputs against damage due
to high static voltages or electric
fields; however, ~ is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.

TRUTH TABLE (X = Don't Care)
E1

E2

G

W

Mode

Vee Current

Output

Cycle

H

X

X

X

Not Selected

ISBI,ISB2

High-Z

X

L

X

X

Not Selected

ISBI,ISB2

High-Z

L

H

H

H

Output Disabled

ICCA

High-Z

-

L

H

L

H

Read

ICCA

Dout

Read Cycle

L

H

X

L

Write

ICCA

High-Z

Write Cycle

This CMOS memory circuit has
been designed to meet the dc and
ac specifications shown in the
tables, aiter thermal equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse air flow
of at least 500 linear feet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

Unit

VCC

- 0.5 to + 7.0 V

V

Yin, Vout

-0.5toVCC
+0.5

V

Output Current

lout

±20

mA

Power Dissipation

PD

1.0

W

Tbias

-10to+85

°C

TA

Oto +70

°C

Power Supply Voltage
Vottage Relative to VSS For Any Pin
ExceptVcc

•

Temperature Under Bias (TA = 25°C)
Operating Temperature

-55to+ 125
Storage Temperature-Plastic
°C
Tsla
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC + 0.3*

V

-0.5**

-

0.8

V

Parameter

Input Low Voltage
Vil
vlH (max) = vcc + U.;:I v oc; vlH (max) - vcc + 2.u v ac (PU se WlOIn ,; ~O ns)
**VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width,; 20 ns)

DC CHARACTERISTICS
Min

Max

Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC)

Parameter

Symbol
Ilka(l\

-

±1

Output Leakage Current (EI = VIH or G = VIH, Vout = 0 to VCC)

IlkalO}

-

±1

IlA
IlA

Output High Voltage (lOH = - 4.0 mAl

VOH

2.4

Output Low Voltage (1m = 8.0 mAl

VOL

-

-

V
V

0.4

POWER SUPPLY CURRENTS
Parameter
AC Active Supply Current (lout = 0 mA, VCC = Max, f = fmax)
AC Standby Current (EI

= VIH or E2 = VIL or VCC = Max, f = fmax)

Standby Current (EI ;, VCC - 0.2 V or E2,; VSS + 0.2 V,
Yin ';VSS + Q.2 V, or ;,VCC-0.2V)

Symbol

-15

·17

·20

·25

·35

Unit

ICCA

170

160

155

145

140

mA

ISBI

50

45

45

40

40

mA

ISB2

20

20

20

20

20

rnA

MOTOROLA MEMORY DATA
5-4

MCM6205

CAPACITANCE (I = 1 MHz, dV = 3 V, TA = 25'C, Periodically sampled rather than 100% tested)
Symbol

Max

Unit

Address and Data Input Capacitance

Characteristic

Cin

6

pF

Control Pin Input Capacitance (El, E2, G, W)

Cin

8

pF

Output Capacitance

Cout

8

pF

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10%, TA = 0 to + 70'e, Unless Otherwise Noted)
Input Timing Measurement Reference Level .••••.•• 1.5 V
Input Pulse Levels ............................ 0 to 3 V
Input Rise/Fall Time .............................. 5 ns

Output Timing Measurement Reference Level. . . . . .. 1.5 V
Output Load .•........ Figure lA Unless Otherwise Noted

READ CYCLE (See Notes 1 and 2)
Symbol
Parameter

-15

-20

-17

-25

-35

Std

Alt

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Read Cycfe lime

tAVAV

tRC

15

17

-

20

-

25

-

35

-

ns

Address Access lime

tAVOV

tAA

35

ns

Enable Access lime

tELOV

tACS

35

ns

Output Enable Access lime

IGLOV

toE

-

-

15

ns

Output Hold from Address
Change

tAXOX

toH

4

15

-

15

8

17

-

-

17

-

9

-

10

-

12

-

4

4

-

4

-

4

4

-

4
0

-

0

20

25
25

-

3

4

Enable Low to Output Active

IELOX

tCLZ

4

Output Enable Low to Output
Active

IGLOX

toLZ

0

-

Enable High to Output High-Z

tEHOZ

tcHZ

0

8

0

8

0

9

0

10

0

11

ns

5,6,7

Output Enable High to Output
High-Z

IGHOZ

toHZ

0

7

0

8

0

8

0

10

0

11

ns

5,6,7

-

0

-

0

-

0

-

0

-

ns

25

-

35

ns

Power Up lime

tELICCH

tpu

0

Power Down lime

IEHICCL

tpo

-

0

-

20

Unit Notes

4

-

15

17

0

-

20

-

4

ns
ns

5,6,7

ns

5,6,7

NOTES:
1. Wis high lor read cycle.
2. E1 and E2 are represented by E in this data sheet. E2 is 01 opposite polarity to E.
3. All timings are referenced lrom the last valid address to the lirst transitioning address.
4. Addresses valid prior to or coincident wRh E going low.
5. At any given voltage and temperature, tEHOZ max < tELOX min, and IGHOZ max < 'GLOX min, both lor a given device and lrom device 10 device.
6. Transition is measured ± 500 mV lrom steady-state voltage wRh load 01 Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E1 = VIL, E2 = VIH, G = VIL)'

MOTOROLA MEMORY DATA

5-6

II

MCM6205

READ CYCLE 1 (See Note 8)

•

tAVAV
A(ADDRESS)
tAXOXo (DATA OUT)

DATA VALID

PREVIOUS DATA VALID
tAVOV - - - - - - - -__ 1

READ CYCLE 2

•
A(ADDRESS)

•

(See Note 4)

tAVAV

\I
1\

•

E (CHIP ENABLE)

tELOV

\.

G(OUTPUT ENABLE

•
I!...tEHaz-

j.tELOX"

-tGHaz-

I\t GLOX "

11
tGLOV-

~(

O(DATAOUT)
tELICCH

ICC

VCC
SUPPLY CURRENT I SB

tAVOV

1--+

-----------

DATA VALID

~

~tELICCL-

•

V

\

~

AC TEST LOADS
+5V
OUTPUT

~\L----Zo.sonii-

4800

o

RL=SOO

2550

5pF
(INCLUDING
SCOPE AND JIG)

VL=1.5V

Figure 1A

Figure 1B

TIMING PARAMETER ABBREVIATIONS

I II

txxxx
signal name from which interval is defined
transition direction for first signal
signal name to which interval is defined
transition direction for second signal

I

The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X • transition to invalid or don~ care
Z = transition to off (high impedance)

TIMING LIMITS

The table of timing values shows e~her a minimum or a maximum
limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a
minimum since the system must supply at least that much time (even
though most devices do not require il). On the other hand, responses
from the memory are specified from the device point of view. Thus, the
access time is shown as a maximum since the device output will be
valid no later than that time.

MOTOROLA MEMORY DATA

MCM6206

WRITE CYCLE (W Controlled) (See Notes 1, 2, and 3)
Symbol
Parameter

-15

-20

-17

-25

-35

Sid

All

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

twe

15

17

4

Address Valid to End of
Write

tAVWH

tAW

12

15

Write Pulse Width

twLWH,
twLEH

twp

12

14

15

-

20

Write Pulse Width, High
(Output Enable devices)

twLWH,
twLEH

twp

10

11

-

12

-

15

-

ns

0

-

35

tAS

-

25

tAVWL

-

20

Address Setup Time

-

Data Valid to End of Write

tOVWH

tow

7

-

8

-

8

0

-

0

-

0

0

0

-

ns

tDH

-

12

twHOX

-

10

Data Hold Time
Write Low to Output HighZ

twLOZ

twz

0

7

0

8

0

8

0

10

0

11

ns

6,7,8

Write High to Output Active

twHOX

tow

4

4

6,7,8

0

-

ns

0

-

4

twR

-

4

twHAX

-

4

Write Recovery Time

-

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

20

4

25

-

ns

20

-

35

15

-

25

14

-

0
14

0

0

0

0
20

0

0
30
30
20

ns
ns
ns
ns

5

ns

ns

WRITE CYCLE (E Controlled) (See Notes 1 and 2)
Symbol
Parameter

-17

-15

-20

-35

-25

Std

All

Min

Max

Write Cycle Time

tAVAV

twe

15

Address Setup Time

tAVEL

tAS

0

Address Valid to End of

tAVEH

tAW

12

-

Enable to End of Write

tELEH,
tELWH

tew

10

-

11

-

12

-

15

-

25

-

ns

Data Valid to End of Write

tOVEH

tow

7

-

8

0

-

0

Write Recovery Time

teHAX

twR

0

0

-

0

-

-

ns

0

-

11

tOH

-

10

tEHOX

-

8

Data Hold Time

17

0

0

0

0

ns
ns

Wrne

0
0

0
0

NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. Ef and E2 are represented by E in this data sheet. E2 is of opposite polarny to E.
3. I! G goes low coincident with or after Wgoes low, the output will remain in a high-impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. I! G ~ VIH, the output will remain in a high-impedance state.
6. At any given voltage and temperature, twLQZ max < twHQX min, both for a given device and from device to device.
7. Transition is measured ± SOO mV from steady-state voltage with load of Figure 1B.
8. This parameter is sampled and not 100% tested.
9. I! E goes low coincident with or after Wgoes low, the output will remain in a high-impedance state.
1O.I! E goes high coincident with or before Wgoes high, Ihe output will remain in a high-impedance state.

MOTOROLA MEMORY DATA
5-7

ns
ns

9,10

•

MCM6206

WRITE CYCLE 1 (See Notes 1 , 2, and 3)
tAVAV
A(ADDRESS)

1~.~==========~~t~~VW;H~============::.;;~I---tWHAA
E(CHIP ENABLE)

-------1----"'"'

i + - - - - - tWLWH _ _ _ _ _ 1
tWLEH

,---------

W (WRITE ENABLE)
t DVWH
D(DATA IN)

--

- f o o - -.......- tWHDX

DATA VALID

HIGHZ

Q(DATAOUn - - - - - - - {

WRITE CYCLE 2 (See Notes 1 and 2)

.

tAVAV

"

A(ADDRESS)

\

tAVEH

E (CHIP ENABLE)
-tAVEL-\
~tELEH

tEHAA ...

tELWH

W (WRITE ENABLE)

D(DATAIN)

xxxxxxxxxxxxxxxxxf

tDVEH - DATA VALID

tEHDX

=-mxXX

HIGH-Z
Q(DATAOUn - - - - - - - - - - - - - - - - - - - - - - - - - - - , - - - -

ORDERING INFORMATION (Order by Full Part Number)
MCM

Motorola Memory Prefix
Part Number

6205

-==r- T

TL=:
X

XX

XX

Shipping Method (R2 = Tape & Reel, Blank = Rails)
Speed (15 = 15 ns, 17 = 17 ns, 20 =20 ns,
25 = 25 ns, 35 = 35 ns)

Package (NP or BNP = 300-mil Plastic DIP,
NJ or BNJ = 300-mil SOJ)
Full Part Numbers---MCM6205NP15
MCM6205NP17
MCM6205NP20
MCM6205NP25
MCM6205BNP35

MCM6205NJ15
MCM6205NJ17
MCM6205NJ20
MCM6205NJ25
MCM6205BNJ35

MOTOROLA MEMORY DATA

MCM6205NJ15R2
MCM6205NJ17R2
MCM6205NJ20R2
MCM6205NJ25R2
MCM6205BNJ35R2

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6205C

Advance Information
32K x 9 Bit Fast Static RAM
The MCM6205C is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is available in plastic dual-in-line and plastic small-outline J-Ieaded packages.
• Single 5 V ±1 0% Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• Fast Access Times: 15, 17, 20, 25 and 35 ns
• Equal Address and Chip Enable Access Times
• Output Enable (G) Feature for Increased System Flexibility and to Eliminate
Bus Contention Problems
• Low Power Operation: 140-170 mA Maximum ac
• Fully TTL Compatible - Three State Output

BLOCK DIAGRAM

VCC
VSS
MEMORY MATRIX
256 ROWS x
128 x 9 COLUMNS

COLUMN 1/0

PPACKAGE
300 MIL PLASTIC
CASE 853-01

~JPACKAGE

300MILSOJ
CASE 857-02

PIN ASSIGNMENT
NC

VCC

NC

A14

A8

E2

A?

W

A6

A13

A5

A9

A4

Al0

A3

All

A2

G

AI

A12

AO

ET

Doo

D08

DOl

DO?

D02

DQ6

D03

DOS

VSS

D04

COLUMN DECODER
PIN NAMES

8 _ _--."

AI

A2

A5

A8 A12 A13 A14

E2

W

G--a-/

AD-A 14 ............... Address Input
DOD-D08 .... Data InpuVData Output
W ..................... Write Enable
G ................... Output Enable
ET, E2 ................. Chip Enable
NC .................. No Connection
VCC .......... Power Supply (+ S V)
VSS ....................... Ground

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
5-9

iii

MCM6205C

This device contains clrcuttry to protect the inputs against damage due
to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.

TRUTH TABLE (X = don't care)
E1

E2

G

W

Mode

VCCCurrent

Output

H

X

X

X

Not Selected

ISB1,ISB2

High-Z

-

X

L

X

X

Not Selected

ISB1,ISB2

High-Z

-

L

H

H

H

Output Disabled

ICCA

High-Z

-

L

H

L

H

Read

ICCA

Read Cycle

L

H

X

L

Write

ICCA

Dout
High-Z

Cycle

This CMOS memory circutt has
been designed to meet the de and
ac specifications shown in the
tables, after thermal eqUilibrium has
been established. The circuit Is in a
test socket or mounted on a printed
circuit board and transverse air flow
of at least 500 linear feet per minute
is maintained.

Write Cycle

ABSOLUTE MAXIMUM RATINGS
Reting
Power Supply Voltage
Voltage Relative to VSS For Any Pin
ExceptVcc
Output Current
Power Dissipation

Symbol

Value

VCC

-0.5to + 7.0 V

Unit
V

Yin' Vout

-0.5toVCC
+0.5

V

lout
Po

±20

rnA

1.0

W

Temperature Under Bias

-10to+65
'C
Tbias
Operating Temperature
Oto +70
'C
TA
Storage Temperature-Plastic
Tsto
-55to+ 125
'C
NOTE. Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee

=5.0 V ± 10%, TA =0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC + 0.3'
0.6

V

Input Low Voltage
VIL
• VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse WIdth S 20 ns)
"VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width S 20 ns)

-0.5*'"

V

DC CHARACTERISTICS
Min

Max

Unit

±1

IlkalOl

-

IIA
IIA

Output High Valtage (lOH = - 4.0 rnA)

VOH

2.4

Output Low Voltage (1m = 6.0 rnA)

VOl

-

Parameter

Symbol

Input Leakage Current (All Inputs, Vin = 0 to Vcc)

Ilka(l)

Output Leakage Current (El = VIH or G = VIH, Vout = 0 to VCC)

±1

-

V

0.4

V

POWER SUPPLY CURRENTS
Parameter

Unit

Symbol

-15

-17

-20

-25

-35

AC Active Supply Current (lout = 0 rnA, VCC = Max, f = fmax)

ICCA

170

160

155

145

140

rnA

AC Standby Current (El = VIH, or E2 = VIL, VCC = MAX, f = fmax)

ISBI

50

45

45

40

40

rnA

CMOS Standby Current (Vce = Max, f = 0 MHz, El ;;, Vce - 0.2 V or
E2SVSS+ 0.2 V, VinSVSS + 0.2 V, or ;'Vee -0.2 V)

ISB2

20

20

20

20

20

rnA

MOTOROLA MEMORY DATA
5-10

MCM6206C

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically sampled rather than 100% tested)
Symbol

Max

Unit

Cin

6

pF

Control Pin Input Capacitance (El, E2, G, W)

Cin

8

pF

Output Capacitance

Cout

8

pF

Characteristic
Address and Data Input Capacitance

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vec = 5.0 V ± 10%, T A = 0 to + 70 oe, Unless Otherwise Noted)
Input Timing Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall Time ..................................... 5 ns

Output Timing Measurement Reference Level ............. 1.5 V
Output Load . . . . . . . . . . . . . . . .. Figure 1A Unless Otherwise Noted

READ CYCLE (See Notes 1 and 2)
Symbol
Parameters

-15

-20

-17

-25

-35

Std.

Alt.

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle lime

tAVAV

tRC

15

-

17

-

20

-

25

-

35

-

ns

3

Address Access Time

tAVOV

tAA

17

-

20

35

ns

17

-

20

9

10

4

-

4

Enable Access Time

tELOV

tACS

Output Enable Access lime

'GLOV

toE

-

Output Hold from Address
Change

tAXOX

toH

4

-

15
15
8

-

-

25

-

-

25

ns

12

-

35

-

15

ns

4

-

ns

4

Enable Low to Output Active

tELOX

tcLZ

4

-

4

-

4

-

4

-

4

-

ns

5,6,7

Enable High to Output High-Z

tEHOZ

tcHZ

0

8

0

8

0

9

0

10

0

11

ns

5,6,7

Output Enable Low to Output
Active

tGLOX

tOLZ

0

-

0

-

0

-

0

-

0

-

ns

5,6,7

Output Enable High to Output
High-Z

'GHOZ

toHZ

0

7

0

8

0

8

0

10

0

11

ns

5,6,7

Power Up Time

tELICCH

tpu

0

-

0

-

0

0

-

ns

17

-

-

tEHICCL

-

-

Power Down Time

25

-

35

-

15

0

-

ns
W is high for read cycle.
ET and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
All timings are referenced from the last valid address to the first transitioning address.
Addresses valid prior to or coincident with E going low.
At any given voltage and temperature, tEHOZ max is less than tELOX (min), and 'GHOZ (max) is less than tGLOX (min), both for a
given device and from device to device.
6. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (ET = VIL, E2 = VIH, G = VIL)'
tpD

NOTES: 1.
2.
3.
4.
5.

MOTOROLA MEMORY DATA

5-11

20

4

•

MCM6206C

t:

READ CYCLE 1 (See Note 8)

~J

IAVAV

A(ADDRESS) _ _ _ _

" '_ _ __

-1-AA-aK----.~I---------------

Q (DATA OUT)

PREVIOUS DATA VALID

DATA VALID

1------- IAVQV

READ CYCLE 2 (See Note 4)
IAVAV

•

\V

A(ADDRESS)

1[\

,

E(CHIP ENABLE)

IELQV

V
I!--IEHQZ"

,-telQX -

G(OUTPUT ENABLE)

I
HIGHZ

Q (DATA OUT)

J(XXX) (

IAVQV

,

!--IGHOZ"

IGlQV
-lGlQX -

V

DATA VALID

HIGHZ

I

I---

SUPPlYCURR~~ICC -------------,------------------1
IELICCH -

L

ISB----------'.

AC TEST LOADS

+5V 4800

Zo=500

Q

~

255 0

SpF
(INCLUDING
SCOPE AND JIG)

:-

Figure 1A

IEHICCl

Figure 18

MOTOROLA MEMORY DATA
6-12

TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the extemal
system point of view. Thus. address setup time is
shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand.
responses from the memory are specified from
the device point of view. Thus. the access time is
shown as a maximum since the device never provides data later than that time.

MCM6206C

WRITE CYCLE 1

0N Controlled, See Notes 1, 2, and 3)
Symbol

Parameters

-15

-20

-17

-25

-35

Std.

Alt.

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Units

Notes

Write Cycle Time

tAVAV

twc

15

17

-

20

4

0

0

-

a

0

Address Valid to End of
Write

tAVWH

tAW

12

-

14

-

15

-

20

-

30

-

ns

tAS

-

35

tAVWL

-

25

Address Setup Time

-

Write Pulse Width

tWLWH,
twLEH

twp

12

-

14

-

15

-

20

-

30

-

ns

Write Pulse Width,
GHigh

twLWH,
twLEH

twP

10

-

11

-

12

-

15

-

20

-

ns

Data Valid to End of
Write

tDVWH

tow

7

8

8

10

12

ns

0

ns
ns

5

Data Hold Time

twHDX

tDH

0

-

0

-

0

-

0

-

0

-

Write Low to Output
High-Z

twLQZ

twz

0

7

0

8

a

8

a

10

0

11

ns

6,7,8

Write High to Output
Active

twHQX

tow

4

-

4

-

4

-

4

4

6,7,8

twHAX

twR

0

-

0

-

0

-

0

0

-

ns

Write Recovery Time

-

WRITE CYCLE 2

ns

ns

(E Controlled, See Notes 1 and 2)
Symbol

Parameters

-15

-17

-20

~5

-25

Std.

Alt.

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

twc

15

17

4

Address Valid to End of
Write

tAVEH

tAW

12

-

ns

0

-

35

tAS

Enable to End of Write

tELEH,
tELWH

lew

10

tow

7

Data Hold Time

tEHDX

-

ns

tDVEH

-

25

Data Valid to End of
Write

-

25

tAVEL

-

20

Address Setup Time

-

0
14
11
8

0
15
12

8

0
20
15
10

0

25

11

ns
ns
9,10

ns

ns
0
0
0
0
0
tDH
ns
0
0
a
0
0
tEHAX
.twR.
NOTES: 1. A write occurs during the overlap of E low and W low.
2. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. If G goes low coincident with or after Wgoes low, the output will remain in a high impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. If G;, VIH, the output will remain in a high impedance state.
6. At any given voltage and temperature, twLQZ max is less than twHQX min, both for a given device and from device to device.
7. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
8. This parameter is sampled and not 100% tested.
9. If E goes low coincident with or after Wgoes low, the output will remain in a high impedance state.
10. If E goes high coincident with or before Wgoes high, the output will remain in a high impedance state.
Write Recovery Time

MOTOROLA MEMORY DATA
5-13

II

MCM6206C

WRITE CYCLE 1 (iN Controlled, See Notes 1, 2 and 3)
IAVAV

----------001

A (ADDRESS)

\4-------

IAVWH -----_>I4---oo!_ twHAX

E(CHIP ENABLE)
---t----~I+----

twLWH
twLEH

----t::::::::::!:!.----

W(WRITE ENABLE)
IDVWH
D(DATA IN)

•

--t-*""

DATA VALID

HIGHZ

o(DATA OUT) --...;.;.;='----(

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
~-------- ~~v----------t

A(ADDRESS)
IAVEH

---------1

E(CHIP ENABLE) ----------+----------------~

r---+-----

W(WRITE ENABLE)

D(DATAIN)

o (DATA OUT) _ _ _ _ _ _ _ _ _ _ _ _ _ _

-"H~IG::..:.H.::.Z

_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

ORDERING INFORMATION (Order by Full Part Number)

MCM

Motorola Memory Prefix
Part Number

~

T TL2
6205C

X

XX

XX

Shipping Method (R2 = Tape & Reel, Blank = Rails)
Speed (15 = 15 ns, 17 = 17 ns, 20 = 20 ns,
25 = 25 ns, 35 = 35 ns)

Package (P = 300 mil Plastic DIP, J = 300 mil SOJ)
Full Part Numbers-MCM6205CP15
MCM6205CP17
MCM6205CP20
MCM620SCP25
MCM6205CP35

MCM6205CJ15
MCM6205CJ17
MCM6205CJ20
MCM6205CJ25
MCM6205CJ35

MOTOROLA MEMORY DATA
5-14

MCM6205CJ15R2
MCM6205CJ17R2
MCM6205CJ20R2
MCM6205CJ25R2
MCM6205CJ35R2

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - -

TECHNICAL DATA

MCM6206
32K

X

8 Bit Fast Static RAM

The MCM6206 is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout. and is available in plastic dual-in-line and plastic small-outline J-Ieaded packages.
• Single 5 V ±1 0% Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• Fast Access Times: 15, 17,20, 25 and 35 ns
• Equal Address and Chip Enable Access Times
• Output Enable (<3) Feature for Increased System Flexibility and to Eliminate
Bus Contention Problems.
• Low Power Operation: 135 -165 rnA Maximum ac
• Fully TTL-Compatible - Three-State Output

~~,

30D-MIL PLASTIC
CASE 7108-01

~PACKAGE

3DO-MILSOJ
CASE 8108-03

PIN ASSIGNMENT
A14

VCC

A12

Iii

AO--D-r---,

A7

A13

A6

AS

A3--I>--I

AS

A9

A4

All

BLOCK DIAGRAM

A4--{~-I

A6--I"2--I

>.;
.!

~~"

....

ROW" :,'
A7 _ _D-IDECODER ~'.

000 -.--'''-' .,--,

D07

A3

G

A2

Ala

Al

E

Aa

007

Doa

006

001

DOS

002

DQ4

VSS

003

COLUMN 110

-=-'-+-I>-H

COLUMN DECODER

Al

A2

PIN NAMES

AS Ala A12 A13 A14

MOTOROLA MEMORY DATA
5-15

AO-A14 ... " ..... , ... Address Input
DOO-DO? ... Data Input/Data Output
Iii ., .... , ...... , ....... WriteEnable
G ................... Output Enable
E ..................... Chip Enable
NC .................. No Connection
Vce .... .. .... Power Supply (+ 5 V)
VSS ... , ... , ....... ,., ..... Ground

MCM6206

TRUTH TABLE (X = don't care)
E

G

W

Mode

Vee Current

Output

H

X

X

Not Selected

ISBt,ISB2

High-Z

-

L

H

H

Output Disabled

ICCA

High-Z

-

L

L

H

Read

ICCA

L

X

L

Write

ICCA

Dout
High-Z

Write Cycle

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
lields; however, it is advised that
normal precautions be taken to
avoid application 01 any voltage
higher than maximum rated voltages to this high-impedance circuit.

Cycle

Read Cycle

ABSOLUTE MAXIMUM RATINGS
Ratlng
Power Supply Vottage
Voltage Relative to VSS For Any Pin
Except VCC
Output Current (per I/O)
Power Dissipation
Temperature Under Bias

Symbol

Value

Unit

VCC

- 0.5 to + 7.0 V

V

Yin, Vout

-0.5toVCC
+0.5

V

lout
PD

±20

mA

1.0

W

Tbias

-10to+85

°c

This CMOS memory circuit has
been designed to meet the dc and
ac specilications shown in the
tables, after thermal equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse air Ilow
01 at least 500 linear leet per minute
is maintained.

Operating Temperature

o to + 70
°c
TA
Storage Temperature-Plastic
-55to+ 125
°C
Tsta
NOTE. Permanent device damage may occur II ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages lor extended
periods 01 time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

-0.5"

-

VCC + 0.3'
0.8

V

Parameter

Input Low Voltage
VIL
'vIH (m~x) = VCC + 0.3 V dC; vlH (max) ~ VCC + 2.0 V ac (pulse Width'; 20 ns)
"VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse Width,; 20 ns)

V

DC CHARACTERISTICS
Parameter
Output Leakage Current (E

Max

Unit

±1

jJA

IlkalO)

-

±1

jJA

VOH

2.4

-

V

VOL

-

0.4

V

Ilka(l)

= VIH or G = VIH, Vout = 0 to VCC)

Output High Voltage (IOH = - 4.0 rnA)
Output Low Voltage (l0L

Min

Symbol

Input Leakage Current (All Inputs, Vin = 0 to Vccl

= 8.0 mAl

POWER SUPPLY CURRENTS
Parameter
AC Active Supply Current (lout = 0 rnA, VCC

= Max, I =Imax)
AC Standby Current (E = VIH, VCC = Max, I = Imax)
CMOS Standby Current (VCC = Max, I = 0 MHz,

Symbol

·15

·17

·20

·25

·35

Unit

ICCA

165

155

150

140

135

rnA

ISBI

50

45

45

40

40

mA

ISB2

20

20

20

20

20

rnA

Vin'; VSS + 0.2 V, or :2 VCC - 0.2 V)

MOTOROLA MEMORY DATA
5-16

MCM6206

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically sampled rather than 100% tested)
Symbol

Max

Un"

Address and Data Input Capacitance

Characteristic

Cin

6

pF

Control Pin Input Capacitance (E, G, W)

Cin

8

pF

Cout

8

pF

Output Capacitance

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10%, T A = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level ........ 1.5 V
Input Pulse Levels .......•.•.................. 0 to 3 V
Input Rise/Fall Time ...................•...•..•... 5 ns
READ

Output Timing Measurement Reference Level. . . . . .. 1.5 V
Output Load .......... Figure lA Unless Otherwise Noted

CYCLE (See Note 1)
-17

-15

Symbol
Parameter

Min

Max

Min

Max

Unit

Notes

-

20

-

25

-

35

ns

2

-

17

-

20

-

25

35

ns

-

17

-

20

35

ns

10

-

25

9

-

-

-

12

-

15

ns

4

-

4

-

ns

4

-

4

-

Min

Max

Min

Read Cycle TIme

tAVAV

tRC

15

-

17

Address Access TIme

tAVOV

tM

-

15

Enable Access TIme

tELOV

tACS

Output Enable Access TIme

tGLOV

toE

-

tOH

4

Output Hold from Address
Change

tAXOX

Enable Low to Output Active

tELOX

tcLZ

Enable High to Output High-Z

tEHOZ

tcHZ

Output Enable Low to Output
Active

IGLOX

Output Enable High to Output
High-Z

IGHOZ

4

toLZ

a
a

toHZ

8

-

4

4

-

a
a

a

7

-

Power Up Time

tELICCH

tpu

a

Power Down TIme

tEHICCL

tpD

-

8

15

-35

-25

Max

Alt

15

-20
Min

Std

Max

-

4

4

-

a
a

a

8

a

a

-

-

8

17

-

ns

4,5,6

11

ns

4,5,6

-

a
a

11

ns

4,5,6

a

10

a

8

ns

4,5,6

-

a
a

8

9

3

10

a

-

a

-

a

-

ns

-

20

-

25

-

35

ns

NOTES:
1. Vii is high for read cycle.
2. All timings are referenced from the last valid address to the first transitioning address.
3. Addresses valid prior to or coincident w~h E going low.
4. At any given voltage and temperature, tEHOZ max < tELOX min, and IGHOZ max < tGLOX min, both for a given device and from device to device.
5. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected E =VIL and G =VIL.

MOTOROLA MEMORY DATA
5-17

•

MCM6206

READ CYCLE 1 (See Note 7)
tAVAV
A(ADDRESS)
tAJ(OX-

o(DATA OUT)

PREVIOUS DATA VALID

DATA VALID

~----- tAVOV ---------l~1

READ CYCLE 2

•

(See Note 3)

tAVAV

V

A(ADDRESS)

•

1\

tElOV

~

E (CHIP ENABLE)

•

If

.-tEHOZ-.-tGHOZ--

.tELOX"
.tGlOX"

G(OUTPUT ENABLE

I

\
tGlOVO(DATAOUT)

ICC
VCC
SUPPLY CURRENT I SB

------

tEllCCH

-

,XXYXX:• <

DATA VALID

tAVOV

V

-

tELICCl-

\

<-

AC TEST LOADS
+5V
4B00

OUTPUT
ZO=50 0

o
Rl=500

5pF
(INCLUDING
SCOPE AND JIG)

2550

Figure1A

Figure 1B

TIMING PARAMETER ABBREVIATIONS
t X X X X

signal name from which interval is defined
transttion direction for first signal
signal name to which interval is defined
transition direction for seoond signal

t

III

TIMING UMITS
The table of timing values shows either a minimum or a maximum
limn for each parameter. Input requirements are specified from the extemal system point of view. Thus, address setup time is shown as a
minimum since the system must supply at least that much time (even
though most devices do not require ttl. On the other hand, responses
from the memory are specffied from the device point of view. Thus, the
access time is shown as a maximum since the device output will be
valid no later than that time.

The transttion definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transttion to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)

MOTOROLA MEMORY DATA
5-18

MCM6206

WRITE CYCLE 1

(Vi Controlled) (See Notes 1 and 2)
-15

Symbol
Parameter

-17

-20

-35

-25

Std

Alt

Min

Max

Min

Max

Min

Max

Min

Max

Min

Write Cycle lime

tAVAV

twe

15

17

20

-

35

-

ns

tAVWL

tAS

0

0

-

0

-

ns

20
20

30

-

ns

15

-

30

14

-

25

Address Setup lime

-

-

20

-

ns

Max

Unit Notas

Address Valid to End of Write

tAVWH

tAW

12

Write Pulse Width

twLWH,
twLEH

twP

12

-

Wr~e

Pulse Width, High
(Output Enable devices)

twLWH,
twLEH

twP

10

-

11

-

12

-

15

Data Valid to End of Write

tOVWH

tow

7

-

12

0

0

0

-

0

-

ns

0

-

10

tOH

-

8

twHOX

-

8

Data Hold lime
Low to Output High-Z

twLOZ

twz

0

7

0

8

0

8

0

10

0

11

ns

5,6,7

Write High to Output Active

twHox

tow

4

4

-

ns

5,6,7

0

-

4

twR

-

4

twHAX

-

4

Write Recovery lime

-

W~e

0
14

0

0
15

0

0

0

3

ns

4

ns

ns

WRITE CYCLE 2 (E Controlled) (See Note 1)

-15

Symbol
Parameter

-17

Sid

All

Min

Max

Min

Write Cycle lime

tAVAV

twe

15

-

17

Address Setup lime

tAVEL

tAS

0

-

0

-

14

-

8

Address Valid to End of Write

tAVEH

tAW

12

Enable to End of Write

tELEH,
tELWH

tew

10

Data Valid to End of W~e

tOVEH

tow

7

Data Hold lime

tEHOX

tOH

0

Write Recovery lime

leHAX

twR

0

11

0
0

-20

-35

-25

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

-

20

-

25

35

3

15

-

25

-

ns

20

-

-

10

-

ns

0

0

-

0

-

11

0

0

-

ns

0
15
12
8

0

0

0
25

NOTES:
1. A write occurs during the overlap of E low and iN low.
2. If G goes low coincident with or aiter iN goes low, the output will remain in a high-impedance state.
3. All timings are referenced from the last valid address to the first lransRioning address.
4. If G ~ VIH, the output will remain in a high-impedance state.
5. At any given voltage and temperature, tWLOZ max < lwHOX min, both for a given device and from device to device.
6. Trans~ion is measured ± SOO mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. If E goes low coincident with or after iN goes low, the output will remain in a high-impedance state.
9. If Egoes high coincident wRh or before iN goes high, the output will remain in a high-impedance state.

MOTOROLA MEMORY DATA
5-19

ns
ns
ns

ns

8,9

MCM6206

WRITE CYCLE 1 (See Notes 1 and 2)

__~I---------

tAVAV ----------;.~I

r--------

A(ADDRESS)

1~.~==========~t~AMYWMH~============::~~I--tw~
E (CHIP ENABLE)

W(WRITE ENABLE)
t DYWH - 1 - - - - 1 - tWHDX

o(DATA IN)

•

DATA VALID

HIGHZ

Q(DATAOUn - - - - - - - {

WRITE CYCLE 2 (See Note 1)

•

tAVAV

V

A(ADDRESS)

1\

•

tAVEH

E (CHIP ENABLE)
-tAVEL-1\
I - - - t E L E H _ .tEHAX"
tELWH

W(WRITE ENABLE)

D(DATAIN)

xxxxxxxxxxxxxxxxxf

tDVEHDATA VALID

tEHDX

=-mxxXX

Q(DATAOun _ _ _ _ _ _ _ _ _ _ _ _--:..H;;.;IG;;.;H-;;.;Z_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

ORDERING INFORMATION (Order by Full Part Number)

---=---- T TL-=:
MCM

Motorola Memory Prefix
Part Number

6206

X

XX

XX

Shipping Method (R2 = Tape & Reel, Blank = Rails)

Speed (15 = 15 ns, 17 = 17 ns, 20
25 = 25 ns, 35 = 35 ns)
Package (NP or BNP = 300-mil Plastic DIP,
NJ or BNJ = 300-mil SOJ)

Full Part Numbers--MCM6206NP15
MCM6206NP17
MCM6206NP20
MCM6206NP25
MCM6206BNP35

MCM6206NJ15
MCM6206NJ17
MCM6206NJ20
MCM6206NJ25
MCM6206BNJ35

MOTOROLA MEMORY DATA

5-20

MCM6206NJ15R2
MCM6206NJ17R2
MCM6206NJ20R2
MCM6206NJ25R2
MCM6206BNJ35R2

=20 ns,

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6206C
Advance Information
32K x 8 Bit Fast Static RAM
The MCM6206C is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is available in plastic dual-in-line and plastic small-outline J-Ieaded packages.
• Single 5 V ±1 0% Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• Fast Access Times: 15, 17,20, 25 and 35 ns
• Equal Address and Chip Enable Access Times
• Output Enable (G) Feature for Increased System Flexibility and to Eliminate
Bus Contention Problems
• Low Power Operation: 135-165 rnA Maximum ac
• Fully TTL Compatible - Three State Output

~,

300 MIL PLASTIC
CASE 7108-01

~JPACKAGE

3OOMILSOJ
CASE 81011-03

PIN ASSIGNMENT
A14

BLOCK DIAGRAM
AO

VCC

A3--I~"'"

VSS

A4--"~---1

A6--"~---1

MEMORY MATRIX
256 ROWS x
128 x 8 COLUMNS

ROW

A7 _ _"~---1DECODER
A8--I>-.....
A9--I>-.....
All --"~---1

VCC

A12

W

A7

A13

A6

A8

A5

A9

A4

All

A3

G

A2

Al0

Al

E

AO

D07

000

D06

001

D05

002

DQ4

VSS

003

COLUMN 1/0
COLUMN DECODER

E---'

Al

A2

PIN NAMES

AS Al0 A12 A13 A14

W
G-_ _1

Ao-A 14 .............. Address Input
000--007 .... Data Input/Data Output
W .................... WrHe Enable
G .................... Output Enable
E ...................... Chip Enable
VCC .......... Power Supply (+ 5 V)
Vss ....................... Ground

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
5-21

•

MCM6206C

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
fields; however, h is advised thet
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuh.

TRUTH TABLE (X = don't care)

E

G

W

Mode

VCCCurrent

Output

Cycle

H

X

X

Not Selected

ISB1,ISB2

High-Z

L

H

H

Output Disabled

ICCA

High-Z

-

L

L

H

Read

ICCA

L

X

L

Write

ICCA

Dout
High-Z

Write Cycle

Read Cycle

This CMOS memory circuit has
been designed to meet the dc and
ac specilications shown in the
tables, after thermal equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse air flow
01 at least 500 linear leet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS
Retlng
Power Supply Voltage
Voltage Relative to VSS For Any Pin
ExceptVCC
Output Current
Power Dissipation

•

Temperature Under Bias

Symbol

Value

Unit

VCC

-0.5to+7.0V

V

Yin, Vout

-0.5toVce
+0.5

V

lout
Po

±20

rnA

1.0

W

Tbias

-10to + 85

·C

·C
o to + 70
TA
·C
Storage Temperatur-"Iastic
-55to + 125
Tsta
NOTE. Permanent devIce damage may occur II ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages lor extended
periods 01 time could affect device reliability.
Operating Temperature

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA = 0 to 70o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC + 0.3'

V

0.8

V

Parameter

Input Low Voltage
Vll
'VIH (max) = VCC + 0.3 V dc; VIH (max) = Vce + 2.0 V ac (pulse WIdth S 20 ns)
"VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width s 20 ns)

-0.5"·

Unit

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Yin = 0 to Vec)

Ilkalll

±1

Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC)

Ilka(Ol

-

!iA
!iA

Parameter

Output High Voltage (IOH = - 4.0 mAl

-

2.4

VOH
VOL

Output Low Voltage (IOL = 8.0 mAl

±1

-

V

0.4

V

POWER SUPPLY CURRENTS
Symbol

-15

-17

-20

-25

-35

Unit

AC Active Supply Current (lout = 0 rnA, Vec = Max, 1= Imax)

ICCA

165

155

150

140

135

mA

AC Standby Current (E = V'H, VCC = MAX, I = Imax)

ISBI

50

45

45

40

40

rnA

CMOS Standby Current (Vce = Max, 1=0 MHz, E;, Vee - 0.2V
VinSVSS+0.2V,or ;'VCC-0.2V)

ISB2

20

20

20

20

20

mA

Parameter

MOTOROLA MEMORY DATA

5-22

MCM6206C

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25°C, Periodically sampled rather than 100% tested)
Symbol

Max

Un"

Address and Data Input Capacitance

Characteristic

Cin

6

pF

Control Pin Input Capacitance (E, G, W)

Cin

8

pF

Cout

8

pF

Output Capacita"ce

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%, TA =0 to + 700 e, Unless Otherwise Noted)
Input Toming Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. a to 3.0 V
Input Rise/FailTome ..................................... 5 ns

Output Timing Measuremem Reference Level ....•........ 1.5 V
Output Load ......... . . . . . . .. Figure 1A Unless Otherwise Noted

READ CYCLE (See Note 1)
Symbol
Parameter

-15

-17

-25

-20

-35

Std.

Alt

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notea

Read Cycle Time

tAVAV

tRC

15

-

17

-

20

-

25

-

35

-

ns

2

Address Access Tome

tAVOV

tAA

15

-

17

35

ns

15

-

17

35

ns

8

15

ns

-

4

Enable Access Tome

tELOV

tACS

Output Enable Access Tome

tGLOV

Output Hold from Address
Change

tAXOX

toE
tOH

4

9

-

-

10

-

12

-

-

4

-

4

-

ns

4,5,6

4

-

4

-

4

-

ns

4,5,6

9

10

ns

4,5,6

-

a
a

11

-

a
a

-

ns

4,5,6

a

10

a

11

ns

4,5,6

a

-

a

25

-

-

ns

-

35

ns

20
20

4

tELOX

tcLZ

4

-

4

Enable High to Output High-Z

tEHOZ

tcHZ

8

Output Enable Low to Output
Active

'GLOX

toLZ

a
a

-

a
a

-

a
a

Output Enable High to Output
High-Z

'GHOZ

toHZ

a

7

a

8

a

8

-

a

-

a

-

-

-

17

Power Up Tome

tELiCCH

tpu

a

Power Down Tome

tEHiCCL

tPD

-

15

25

i

Enable Low to Output Active

8

25

20

3

NOTES: 1. Wis high for read cycle.
2. All timings are referenced from the last valid address to the first transitioning address.
3. Addresses valid prior to or coincidem with E going low.
4. At any given vottage and temperature, tEHOZ max is less than tELOX (min), and tGHOZ (max) Is less than 'GLOX (min), both for a
given device and from device to device.
5. TransHion is measured ±sao mV from steady-state vottage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E =VIL, G =VIU.

MOTOROLA MEMORY DATA

5-23

•

MCM6206C

t____

READ CYCLE 1 (See Note 7)

A (ADDRESS)

AVAV
_FI+----t

~-tAA--Q-X-------.~I--------------------------~

Q(DATAOUT)

PREVIOUS DATA VAliD

DATA VALID

/4------------ tAVQV

READ CYCLE 2 (See Note 3)
tAVAV

~

W

A(ADDRESS)

J~
teLQV

\

E(CHIP ENABLE)

!\

J +tEHQZ--

\1-- teLQXG(OUTPUT ENABLE)

/

!\
-IGHOZ--

IGLQVHIGHZ

Q(DATAOUT)

I--IGLQX -

J-1
D01--.tC>tl
D02--1H+I>tl

PIN NAMES

D03it1Hi1jL_-----1

AO-A 15 .............. Address Input
DOo-DQ3 . .. Data Input/Data Output

W ..................... Write Enable
E ...................... Chip Enable
NC .................. No Connection
VCC .......... Power Supply (+ 5 V)
VSS ....................... Ground

E----'-.....

w

MOTOROLA MEMORY DATA

•

MCM6208

TRUTH TABLE (X = don't care)
E

W

Mode

VCcCurrent

Output

H

X

Not Selected

ISB1,ISB2

High-Z

-

L

H

Read

ICCA

Dout

Read Cycle

L

L

Write

ICCA

High-Z

Write Cycle

This device contains circuitry to protect the inpU1s against damage due
to high static voltages or electric
lields; however, it is advised that
normal precautions be taken to
avoid application 01 any voltage
higher than maximum rated voltages to this high-impedance circuit.

Cycle

This CMOS memory circuit has
been designed to meet the de and
ac specilications shown in the
tables, after thermal equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse airllow
01 at least 500 linear leet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

Unit

VCC

- 0.510 + 7.0 V

V

Vin, Vout

-0.5toVCC
+0.5

V

Output Current (Per I/O)

lout

±30

mA

Power Dissipation

PD

1.0

W

Tbias

-10to + 85

°c

TA

Oto + 70

°c

Power Supply Voltage
Voltage Relative to V SS For Any Pin
ExceptVcc

Temperature Under Bias (TA _ 25°C)

•

Operating Temperature
Storage Temperature-Plastic

-55to+ 125
°C
Tsto
NOTE: Permanent device damage may occur II ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages lor extended
periods 01 time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%, TA =0 to 70° C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC +0.3"

V

VIL

-0.5'

-

0.8

V

.

Input Low Voltage

VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width" 20 ns)
"VIH (max) = VCC + 0.3 V de; VIH (max) = VCC + 2.0 V ac (pulse width" 20 ns)

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC)

Parameter

IlkoCll

-

±1.0

Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC)

Ilkg(O)

-

±1.0

ISB2

-

IIA
IIA

20

rnA

Standby Current (E ~ VCC - 0.2 V, "VSS + 0.2 V, or ~ VCC - 0.2 V
VCC = Max, I = 0 MHz)
Output low Voltage (lOl = 8.0 mAl

VOL

-

0.4

V

Output High Voltage (IOH = - 4.0 mAl

VOH

2.4

-

V

POWER SUPPLY CURRENTS
Parameter
AC Active Supply Current (lout = 0 mA, VCC = Max, I =1 max)
AC Standby Current (E = VIH, VCC = MAX, 1= I max)

Symbol

-15

-20

-25

Unit

ICCA

155

145

135

mA

ISBI

50

45

40

mA

MOTOROLA MEMORY DATA
5-46

MCM6208

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25° C, Periodically sampled rather than 100% tested)
Symbol

Max

Unit

Address and Data Input Capacitance

Characteristic

Cin

6

pF

Control Pin Input Capacitance (E,G,W)

Cin

6

pF

Output Capacitance

Cout

8

pF

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5 V ± 10%, TA = 0 to + 70o e, Unless Otherwise Noted)
Input Timing Measurement Reference Level ........ 1.5 V
Input Pulse Levels ..........•.........•.•..... 0 to 3 V
Input Rise/Fall Time .........•....•...••.......... 5 ns

Output Timing Measurement Reference Level. . . . . .. 1.5 V
Output Load .......... Figure lA Unless Otherwise Noted

-15

Symbol

-25

-20

Std

Alt

Min

Max

Min

Max

Min

Read Cycle Time

tAVAV

tRC

15

-

20

-

25

-

ns

Address Access Time

tAVQV

tM

-

15

20

25

ns

20

-

25

ns

10

-

12

ns
ns

Parameter

Enable Access Time

tELQV

tACS

-

15

-

Output Enable Access Time

toLQV

toE

-

8

Output Hold from Address Change

tAXQX

toH

4

Enable Low to Output Active

tELQX

tell

4

-

-

Output Enable Low to Output Active

toLQX

toll

0

Enable High to Output High-Z

tEHQZ

teHZ

0

Output Enable High to Output High·Z

tGHQZ

toHZ

Power Up Time

IELICCH

Power Down Time

tEHICCL

Max

4

-

-

0

-

0

-

8

0

9

0

10

0

7

0

8

0

tpu

0

-

0

-

tpo

-

15

-

20

4

4

Unit Notes
3
4

ns

5,6,7

ns

5,6,7

ns

5,6,7

10

ns

5,6,7

0

-

ns

-

25

ns

4

NOTES:
1. Wis high for read cycle.
2. For devices with multiple chip enables, ET and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with Egoing low.
S. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < IGLQX min, both for a given device and from device to device.
6. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected. E S VIL and G S VIL.

MOTOROLA MEMORY

547

DATA

•

MCM6208

READ CYCLE 1 (See Note 8)
tAVAV
A(ADDRESS)
---- tAXOX-

o (DATA OUT)

DATA VALID

PREVIOUS DATA VALID
t AVOV

----------;.~I

READ CYCLE 2 (See Notes 2 and 4)

A(ADDRESS)

r\.

/

tELOV

~

•

,/

tAVAV

~

V

•

~tEHOZ""

1\

E(CHIP ENABLE)

i+tELOX-

~XXXXXr\.

O(DATAOUT)

tAVOV
tELICCH i-o

VCC

ICC

----------

SUPPLY CURRENT I S8

DATA VALID

•

/

-

~

tELICCL-

\
"""

AC TEST LOADS

OUTPUT

~¥----ZO=50Q~_

480Q

o

RL=SOQ
255

5pF
(INCLUDING
SCOPE AND JIG)

Q

VL = 1.5 V

Figure 18

Figure 1A
TIMING PARAMETER ABBREVIATIONS
t X X X X

signal name from which interval is defined
transition direction for first signal
signal name to which interval is defined
transition direction for second signal

I

III

The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)

TIMING LIMITS
The table of timing values shows either a minimum or a maximum
limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a
minimum since the system must supply at least that much time (even
though most devices do not require it). On the other hand, responses
from the memory are specified from the device point of view. Thus, the
access time is shown as a maximum since the device output will be
valid no later than that time.

MOTOROLA MEMORY DATA

MCM6208

WRITE CYCLE 1 (WControlled) (See Notes 1 2 and 3)
-20

-15

Symbol
Parameter

-25

SId

Alt

Min

Max

Min

Max

Min

Max

Write Cycle lime

tAVAV

twe

15

20

25

Address Setup Time

tAVWl

tAS

a

Un"
ns

Notes

Address Valid to End of Write

tAVWH

tAW

12

-

15

-

20

-

Write Pulse Width

twLWH,

twp

12

-

15

-

20

-

ns

Write Pulse Width, High
(Output Enable devices)

tWlWH,
twlEH

twp

10

-

12

-

15

-

ns

Data Valid to End of Write

tOVWH

tow

7

tOH

0

a

-

Write Low to Output High-Z

twlOZ

twz

a

7

0

8

a
a

-

ns

twHOX

-

10

Data Hold lime

10

ns

6,7,8

Write High to Output Active

twHQX

tow

4

-

4

-

4

-

ns

6,7,8

Write Recovery lime

twHAX

twR

a

-

a

-

a

-

ns

0

0

4

ns
ns

twlEH

8

5

ns

WRITE CYCLE 2 (E Controlled) (See Notes 1 2 and 3)
Symbol
Parameter
Write Cycle lime

-25

-20

-15

SId

Alt

Min

Max

Min

Max

Min

Max

Unit

Noles

tAVAV

twe

15

-

20

-

25

-

ns

4

-

a

-

a

-

ns

15

20

ns

12

-

15

-

Address Setup lime

tAVEl

tAS

a

Address Valid to End of Write

tAVEH

tAW

12

Enable to End of Write

tElEH,
tElWH

lew

10

Data Valid to End of Write

tOVEH

tow

7

-

10

ns

toH

0

0

-

-

tEHOX

-

8

Data Hold lime

0

Write Recovery lime

tEHAX

twR

a

-

a

-

a

-

ns

ns

ns

NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. For devices with multiple chip enables, Ef and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. For Output Enable devices, if G goes low coincident with or after Wgoes low, the output will remain in a high-impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. For Output Enable devices, if G" VIH, the output will remain in a high-impedance state.
6. At any given voltage and temperature, twLQG max < twHQX min, both for a given device and from device to device.
7. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
8. This parameter is sampled and not 100% tested.
9. If E goes low coincident with or after Wgoes low, the output will remain in a high-impedance state.
10.1f E goes high coincident with or before Wgoes high, the output will remain in a high-impedance state.

MOTOROLA MEMORY DATA

5-49

9,10

II

MCM6208

WRITE CYCLE 1 (§lee Nole 2)
tAVAV
A(ADDRESS)

1~======:-tt;A:;;;VW;;;H;-:::=======:::;;;~I-

----1--""'

E (CHIP ENABLE)

----1-----,.

~_______ tw~H

______~·~1

tWLEH

tWHAX

r---------

iii (WRITE ENABLE)
t DVWH

o(DATA IN)

•

-1----,-

t WHDX

DATA VALID

HIGHZ

Q(DATAOUn - - - - - - - {

WRITE CYCLE 2 (See Nole 2)

•

tAVAV
A(ADDRESS)

Il
\

\
tAVEH

E (CHIP ENABLE)

j

-tAVEL-

_ t E L E H _ -tEHAXtELWH

V

W (WRITE ENABLE)

xxxxxxxxxxxXxxxm~D_AT_AV_ALlD_-,*>OOo-1
001--.-1-1>+1
PIN NAMES

002---1'*1>+1

AD-A 15 ............... Address Input
00D-003 . . .. Data InpuVOata Output
W ..................... Wr~e Enable
VSS ....................... Ground
E ...................... Chip Enable
NC .................. No Connection
VCC ........... Power Supply (+ 5 V)

0031tiItl1jL_~

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA

5-51

•

MCM6208C

TRUTH TABLE
E

W

Mode

VCCCurrent

Output

H

X

Not Selected

ISB1,ISB2

High-Z

-

L

H

Read

ICCA

Read Cycle

L

L

Write

ICCA

Dout
High-Z

This device contains circuitry to protect the inputs against damage due
to high static vottages or electric
lields; however, it is advised that
normal precautions be taken to
avoid application 01 any voltage
higher than maximum rated vottages to this high-impedance circuit.

Cycle

Write Cycle

This CMOS memory circuit has
been designed to meet the dc and
ac specifications shown in the
tables, afterthermai equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse air flow
01 at least 500 linear leet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS
Rating
Power Supply Vottage
Voltage Relative to VSS For Any Pin
ExceptVcc
Output Current
Power Dissipation
Temperature Under Bias (TA _ 25°C)

•

Symbol

Value

VCC

-0.5to + 7.0 V

Unit
V

Yin, Vout

-0.5toVCC
+0.5

V

lout
Po

±20

mA

1.0

W

Tbias

-10to+85

°c

Operating Temperature

o to +70
°c
TA
Storage Temperature - Plastic
-55to+125
°c
Tsto
NOTE. Permanent device damage may occur II ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended vottages lor extended
periods 01 time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70oe, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Vottage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Vottage

VIH

2.2

-

VCC + 0.3··

V

-OS

-

0.8

V

Parameter

.

Input Low Voltage
VIL
VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse Width S 20 ns)
··VIH (max) =VCC + 0.3 V dc; VIH (max) =VCC + 2.0 V ac (pulse width S 20 ns)

DC CHARACTERISTICS
Parameter

Symbol

Min

Max

Unit

±t.O
±1.0

IlA
IlA

20

mA

0.4

V

-

V

Output Low Vottage (IOL = 8.0 mAl

VOL

-

Output High Vottage (IOH = - 4.0 mAl

VOH

2.4

Input Leakage Current (All Inputs, Yin = 0 to VCC)

Ilka(\)

Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC)

Ilka(O)

Standby Current (E ~ VCC - 0.2 YO, Yin S VSS + 0.2 V
or ~ VCC - 0.2 V, VCC = MAX, I = 0 MHz)

ISB2

POWER SUPPLY CURRENTS
Unit

Symbol

-15

-20

-25

AC Active Supply Current (lout = 0 mA, VCC = Max, I = Imax)

ICCA

155

145

135

mA

AC Standby Current (E = VIH, VCC = MAX, 1= Imax)

ISB1

50

45

40

mA

Parameter

MOTOROLA MEMORY DATA

MCM6208C

CAPACITANCE (f =1 MHz, dV

=3 V, TA =25'C, Periodically sampled rather than 100% tested)

Characteristic

Symbol

Max

Unit

Address and Data Input Capacitance

Cin

6

pF

Control Pin Input Capacitance (E,G,Wl

Cin

6

pF

8

pF

Output Capacitance

Cout
'For devices with multiple chip enables, El and E2 are represented by E in this data sheet. E2 is of oppcsHe polarity to E

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, T A = 0 to +70oe, Unless Otherwise Noted)
Input TIming Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall TIme ..................................... 5 ns

Output TIming Measurement Reference Level ............. 1.5 V
Output Load . . . . . . . . . . . . . . . .. Figure 1A Unless Otherwise Noted

READ CYCLE (See Notes 1 and 2)

-20

-15

Symbol
Parameter

-25

Std.

All.

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle TIme

tAVAV

tRC

15

-

20

25

-

ns

3

Address Access TIme

tAVOV

tAA

-

15

25

ns

Enable Access TIme

tELOV

tACS

-

15

25

ns

Output Enable Access TIme

tGLOV

toE

-

8

-

-

12

ns

4

-

10

-

4

-

4

-

ns

20
20

4

Output Hold from Address Change

tAXOX

tOH

Enable Low to Output Active

tELOX

tCLZ

4

-

4

-

4

-

ns

5,6,7

Enable High to Output High-Z

tEHOZ

tCHZ

0

8

0

9

0

10

ns

5,6,7

Output Enable Low to Output Active

tGLOX

toLz

0

-

0

-

0

-

ns

5,6,7

Output Enable High to Output High-Z

IGHOZ

tOHZ

0

7

0

8

0

10

ns

5,6,7

tELICCH

tpu

0

-

0

-

0

-

ns

Power UpTIme

-

Power Down TIme

-

-

ns
15
20
25
tpc.
tEHICCL
W is high for read cycle.
For devices wilh multiple chip enables, E1 and E2 are represented by E in this data sheet. E2 Is of opposite polarity to E.
All timings are referenced from the last valid address to the first transitioning address.
Addresses valid prior to or coincident with E going low.
At any given voltage and temperature, tEHOZ max is less than tELOX (min), and tGHOZ (max) is less than IGLOX (min), both for a
given device and from device to device.
6. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E = VIL, E2 = VIH, G = VILl.

NOTES: 1.
2.
3.
4.
5.

MOTOROLA MEMORY DATA
5-63

•

MCM6208C

t:

A (ADDRESS)

------~

Q(DATAOUT)

READ CYCLE 1 (See Note 8)

~J

tAVAV

)1\

~tA:AX~OX~====~·~I~------------~------------~

PREVIOUS DATA VALID

~------

DATA VALID

1--------

tAVQV

READ CYCLE 2 (See Notes 2 and 4)
tAVAV

•

\V
I!\

A(ADDRESS)

\V
I~
tELQV

V

\

E(CHIP ENABLE)

/
r--tEHOZ'"

-tELOX -

KXXXX~\

HIGHZ

Q(DATAOUT)

f

tAVQV

tELICCH -

SUPPLY

CURR~~

ICC

-------------

DATA VALID

I.-

\
/

HIGHZ

tEHICCL

IS8------'

AC TEST LOADS

+5V

Zo=50Cl
Q

~

255 Cl

Figure 1A

480Cl

5 pF
(INCLUDING
SCOPE AND JIG)

TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external
system point of view. Thus, address setup time is
shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand,
responses from the memory are specified from
the device point of view. Thus, the access time is
shown as a maximum since the device never provides data later than that time.

Figure 18

MOTOROLA MEMORY DATA

MCM6208C

WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)
-15

Symbol
Parameter

Std.

Alt.

Min

Write Cycle Time

tAVAV

twc

15

Address Setup Time

tAVWL

tAS

0

-20

Max

-25

Min

Max

Min

Max

Unit

Notes

20

-

25

-

ns

4

0

0
20

15

-

20

-

ns

15

-

12

-

15

-

ns

8

-

10

-

ns

0

-

0

-

ns

Address Valid to End of Write

tAVWH

tAW

12

Write Pulse Width

twLWH,
twLEH

twp

12

-

Write Pulse Width, G High

twLWH,
twLEH

twp

10

-

Oata Valid to End of Write

tOVWH

tow

7

Oata Hold Time

twHOX

tOH

0

-

Write Low to Output High·Z

twLOZ

twz

0

7

0

8

0

10

ns

6,7,8

Write High to Output Active

twHOX

tow

4

-

4

4

-

ns

6,7,8

Write Recovery Time

twHAX

twR

0

-

0

-

0

-

ns

ns
ns
5

WRITE CYCLE 2 (E: Controlled, See Notes 1, 2, and 3)

Write Cycle Time

-20

-15

Symbol
Parameter

-25

Std.

Alt.

Min

Max

Min

Max

Min

Max

Unit

Notes

tAVAV

twc

15

-

20

-

25

-

ns

4

-

20

-

ns

-

10

-

ns

-

0

-

ns

Address Setup Time

tAVEL

tAS

0

Address Valid to End of Write

tAVEH

tAW

12

-

15

Enable to End of Write

tELEH,
tELWH

lew

10

-

12

Oata Valid to End of Write

tOVEH

tow

7

-

8

Oata Hold Time

tEHOX

tOH

0

-

0

0

0
15

ns
ns

9,10

0
ns
0
0
tEHAX
twR
NOTES: 1. A write occurs during the overlap of E low and W low.
2. For devices with multiple chip enables, Ef and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. For Output Enable devices, if G goes low coincident with or after Wgoes low, the output will remain in a high impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. For Output Enable devices, if G" VIH, the output will remain in a high impedance state.
6. At any given voltage and temperature, twLOZ max is less than twHOX min, both for a given device and from device to device.
7. Transition is measured ± 500 mV from steady·state voltage with load of Figure 1B.
8. This parameter is sampled and not 100% tested.
9. If E goes low coincident with or aiter Wgoes low, the output will remain in a high impedance state.
10. If E goes high coincident with or before Wgoes high, the output will remain in a high impedance state.
Write Recovery Time

MOTOROLA MEMORY DATA
5-55

•

MCM6208C

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
tAVAV

--------..j

A (ADDRESS)

14-------

tAVWH -----_1*----1o!- twHAX

E(CHIP ENABLE)

Vi (WRITE ENABLE)
tDVWH
D (DATA IN)

•

--I--t-

DATA VALID

HIGHZ

Q (DATA OUT) --....;..;;.='----{

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
tAVAV - - - - - - - - - - - . \
A (ADDRESS)
tAVEH - - - - - - - - - - . ,

r---+-------

E(CHIP ENABLE) ---------+----------------~

----.-jo----+- tEHAX
Vi (WRITE ENABLE)

D(DATAIN)

Q(DATAOUT) _ _ _ _ _ _ _ _ _ _ _ _ _ _--"H""IG::.:.H.::.Z_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

ORDERING INFORMATION (Order by Full Part Number)
MCM
6208C X XX
XX
Motorola Memory Prefix

~

Part Number
Package (P

T TL2

Shipping Method (R2 = Tape & Reel, Blank = Rails)
Speed (15 = 15 ns, 20

=20 ns, 25 =25 ns)

=300 mil Plastic DIP, J =300 mil SOJ)

Full Part Numbers-MCM6208CP15
MCM6208CP20
MCM6208CP25

MCM6208CJ15
MCM6208CJ20
MCM6208CJ25

MOTOROLA MEMORY DATA

MCM6208CJ15R2
MCM6208CJ20R2
MCM6208CJ25R2

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - -

TECHNICAL DATA

64K

X

MCM62L08
MCM62L09

4 Bit Static RAMs

The MCM62L08 and MCM62L09 are 262,144 bit static random access memory
devices organized as 65,536 words of 4 bits fabricated using high-performance
silicon-gate CMOS technology. Static design eliminates the need for external clocks
or timing strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
The MCM62L08 and MCM62L09 draw low current in stand-by mode which makes
_
them ideal for applications with low poweiJlattery backup.
The MCM62L09 has both chip enable (El and output enable (Gl inputs, allowing
greater system flexibility. Either input, when high, will force the outputs to the high
impedance.
The MCM62L08 is available in a 300-mil, 24-lead plastic dual-in-line package and a
24-lead 300-mil plastic SOJ package, both with the JEDEC standard pinout.
The MCM62L09 is available in a 300-mil, 28-lead plastic dual-in-line package and a
28-lead 300-mil plastic SOJ package, both with the JEDEC standard pinout.
• Single 5.0 V ±1 0% Power Supply
• Fully Statio-No Clock or Timing Strobes Necessary
• Fast Access Time: 20/25/35 ns
• Fully TIL-Compatible--Three-State Data Output
• Low Power Operation: 100 ~A Maximum CMOS Standby 120/120/110 mA
Maximum Active ac
• High Board Density SOJ Package Available

MCM62LOB

~+.:!~,

300-MIL PLASTIC

CASE 724A

_._-'..0<::::::1

J PACKAGE
300-MILSOJ
CASEB10A

28riJJiJ'~ 2'
1

PPACKAGE
30D-MIL PLASTIC
CASE 710B

J PACKAGE
30D-MILSOJ

CASE BlOB

PIN ASSIGNMENT
MCM62L08

AD
AI

VCC
A15

A2

A14

VCC

A3

A13

Vss

A4

A12

AS

All

MEMORY MATRIX
256 ROWS x
256 x 4 COLUMNS

ROW
DECODER

24'

AID
A7

DOD

A8

001

A9

002

E
VSS

003

W

COLUMN 1/0
MCM62L09

NC

(MCM62D9 ONLy)

W=~~~rt-------------------------~-j
G
PIN NAMES

AO-A 15 ................. Address Input
DQO-DQ3 ........... Data InpuVOutput
Iii . . . . . . . . . . . . . . . . . . . . . .. Write Enable
G(MCM6209) ........... Output Enable

E . . . . . . . . . . . . . . . . . . . . . . .. Chip Enable
NC .................... No Connection
VCC ............. + 5.0 V Power Supply
VSS ......................... Ground

MOTOROLA MEMORY DATA

VCC

AD

A15

AI

A14

A2

A13

A3

AI2

A4

All

AS

AID

A6

NC

A7

NC

AS

000

A9

DOl

E
G

002

VSS

003

W

..

MCM62L08-MCM62L09

MCM62L08 TRUTH TABLE

E

W

Mode

VCCCurrent

Output

Cycle

H

X
H

Not Selected
Read
Write

ISB1,ISB2
ICCA
ICCA

High-Z
Dout
High-Z

Read Cycle
Write Cycle

Cycle

L
L

L

-

MCM62L09 TRUTH TABLE
E

G

W

Mode

VCC Current

1/0 Pin

H

X
H

X
H
H
L

Not Selected
Output Disabled
Read
Write

ISB1,ISB2
ICCA
ICCA
ICCA

High-Z
High-Z

L
L
L

L
X

This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric lields; however, it Is advised that normal precautions be taken to
avoid application 01 any voltage higher than
maximum rated voltages to this highimpedance circuit.

-

Read Cycle
Write Cycle

Dout
High-Z

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-0.5to+7.0

V

Yin, Vout

- 0.5 to VCC+ 0.5

V

Output Current (per 1/0)

lout

±20

mA

Power Dissipation (TA = 25°C)

PD

1.0

W

Temperature Under Bias

Tbias

-10to+85

°C

Operating Temperature

TA

o to +70

°C

Power Supply Voltage

•

Voltage Relative to V55 lor Any
Pin Except VCC

Storage Temperature

-55 to +125
°C
T.tn
NOTE: Permanent deVice damage may occur II ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages lor extended periods 01 time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS

(Vee = 5.0 V ± 10%, T A = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

Input Low Voltage

VIL

-OS

-

0.8

V

Parameter

·VIL (min) = - 0.5 V dc; VIL (min) = - 3.0 V ac (pulse width,; 20 ns)
DC CHARACTERISTICS
Parameter

Symbol

= 0 to V CC)
Output Leakage Current (E = VIH, Vout = Oto VCC), or G = VIH
AC Supply Current (lout = 0 mA, I =I max , VCC = Max)
Input Leakage Current (All Inputs, Yin

IJ!Ig(IL
IlkolO)
(tAVAV
(tAVAV
(tAVAV

= 20 ns)
= 25 ns)
= 35 ns)

ICCA

= VIH, I =I max, VCC = Max)

ISBI

CMOS Standby Current (E 2: VCC - 0.2 V, all other pins Vin 2: VCC - 0.2 V or
Vin ';VSS + 0.2 V, I = 0 MHz)

ISB2

TTL Standby Current (E

Output Low Voltage (lOL

= 8.0 mAl
= - 4.0 mAl

Output High Voltage (IOH

Min

-

Max
± 1.0

Unit
I'A

± 1.0

j1A

120
120
110

mA

20

mA

100

j1A

0.4

V

-

V

Symbol

Max

Unit

Cin

6

pF

CliO

8

pF

VOL

-

VOH

2.4

CAPACITANCE (I = 1.0 MHz, dV ~ 3.0 V, T A = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
input Capacitance
I/O CapaCitance

MOTOROLA MEMORY DATA
5-58

MCM62L08·MCM62L09

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee

=5 V ±1 0%, T A =0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level .. . . . . .. 1.5 V
Input Pulse Levels ........................... 0 to 3.0 V
Input Rise/Fall Time ............................. 5.0 ns

Output Timing Measurement Reference Level. . . . . .. 1.5 V
Output Load .......... Figure 1A Unless Otherwise Noted

READ CYCLE (See Note 1)
MCM62L08-20
MCM62L09-20

Symbol

MCM62L08-25
MCM62L09-25

MCM62L08-35
MCM62L09-35

Standard

Alternate

Min

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

tRC

20

-

25

35

-

ns

2

Address Access Time

tAVOV

tAA

-

20

25

ns

Enable Access Time

tElOV

tACS

20

-

25

-

35

-

-

-

35

ns

Output Hold from Address Change

tAJ(OX

toH

5

-

5

-

5

-

ns

Parameter

Max

3

Output Enable Access Time

MCM62l09

tGlOV

10

-

12

-

15

ns

MCM62L09

IGLOX

toE
t[2

-

Output Enable low to
Output Active

0

-

0

-

0

-

ns

4,5,6

Output Enable High to
Output High-Z

MCM62L09

tGHOZ

tHZ

0

8

0

10

0

15

ns

4,5,6

Enable low to Output Active

tElOX

t[2

5

-

5

-

5

-

ns

4,5,6

Enable High to Output High-Z

tEHOZ

tHZ

0

8

0

10

0

15

ns

4,5,6

Power Up Time
0
ns
0
0
tpu
tELICCH
Power Down Time
20
25
ns
35
tpD
tEHIGGL
NOTES: 1. W IS high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transitioning address.
3. Addresses valid prior to or coincident with E going low.
4. At any given voltage and temperature, tEHOZ max is less than tELOX min, and tGHOZ max is less than tGlOX min, both for a
given device and from device to device.
5. Transition is measured 500 mV from steady-state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected E=Vll and G=Vll (MCM62l09 only).

-

€

A (ADDRESS)

----

-

READ CYCLE 1 (See Note 7)
tAVAV

d

Av

t

,

XX~

o(DATA OUT)

DATA VALID

~W-1
OOI-..H>-I1
PIN NAMES

AQ-AI5 .............. Address Input
00Q-003 ...... Oata Input / Output
W ..................... Write Enable
G ................... Output Enable
E ..................... Chip Enable
NC .................. No Connection
Vce .. .. .. .... Power Supply (+ 5 V)
VSS ....................... Ground

W
G

MOTOROLA MEMORY DATA
5-63

II

MCM6209

TRUTH TABLE
E

G

W

Mode

VCC Current

Output

Cycle

H

X

X

1I!6t Selected

ISB1,ISB2

High-Z

-

L

H

H

Output Disabled

ICCA

High-Z

-

L

L

H

Read

ICCA

Dout

Read Cycle

L

L

L

Write

ICCA

High-Z

Write Cycle

This device contains circuitl)' to protect the inputs against damage due
to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.
This CMOS memol)' circuit has
been designed to meet the dc and
ac specifications shown in the
tables, after thermal equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse air flow
of at least 500 linear feet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

VCC

- 0.5 to + 7.0 V

V

Yin, Vout

-0.5toVCC
+0.5

V

Output Current (Per 1/0)

lout

±30

rnA

Power Dissipation

PD

1.0

W

Temperature Under Bias

Tbias

-10to+85

'c

Operating Temperature

TA

o to + 70

'c

Power Supply Voltage Relative to V

ss

Voltage Relative to VSS For Any Pin
ExceptVcc

•

Unit

Storage Temperatur&-Plastic

-55to+ 125
'c
Tsta
NOTE: Permanent device damage may occuflf ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, T A = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input H·igh Voltage

VIH

2.2

VCC + 0.3"

V

Input Low Voltage

VIL

-OS

-

0.8

V

Parameter

• VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width,;; 20 ns)
"VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width,;; 20 ns)

DC CHARACTERISTICS
Parameter

Standby Current (E;, VCC - 0.2 V, Vin·';; VSS + 0.2 V,
or ;,VCC-0.2V VCC = MAX, f = 0 MHz)
Output Low Voltage (IOL = 8.0 rnA)
Output High Voltage (IOH

=-

Min

Max

Unit

-

±1.0

~

±1.0
20

~
rnA

VOL

-

0.4

V

VOH

2.4

-

V

Symbol

= 0 to VCC)
Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC)
Input Leakage Current (All Inputs, Yin

4.0 rnA)

Ilka(l)
Ilka(OI
ISB2

POWER SUPPLY CURRENTS
Parameter
AC Active Supply Current (lout = 0 rnA, VCC
AC Standby Current (E

= VIH, VCC

= Max, f = fmax)

=Max, ,= 'max)

Symbol

-15

-20

-25

Unit

ICCA

155

145

135

rnA

ISBI

50

45

40

rnA

MOTOROLA MEMORY DATA

MCM6209

CAPACITANCE (f =1 MHz, dV =3 V, TA = 25"C Periodically sampled rather than 100% tested)
Symbol

Max

Unit

Address and Data Input Capacitance

Cin

6

pF

Control Pin Input Capacitance (E,G,W)

Cin

6

pF

Output Capacitance

Cout

8

pF

Characteristic

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ±10%, TA = 0 to +70 o e, Unless Otherwise Noted)

Input Timing Measurement Reference Level ........ 1.5 V
Input Pulse Levels ............................ 0 to 3 V
Input Rise/Fall Time .............................. 5 ns

Output Timing Measurement Reference Level. . . . . .. 1.5 V
Output Load .......... Figure 1A Unless Otherwise Noted

READ CYCLE
Symbol
Parameter

-20

-15

-25

SId

Ait

Min

Max

Min

Max

Min

Max

Read Cycle Time

tAVAV

tRC

15

20

-

25

-

ns

Address Access Time

tAVOV

tAA

15

-

20

ns

tELQV

lACS

15

-

20

-

25

Enable Access Time

25

ns

Output Enable Access Time

lGLOV

toE

-

8

10

-

12

ns

Output Hold from Address Change

IAXOX

toH

4

4

-

4

IELQX

tCLZ

4

4

-

4

Output Enable Low to Output Active

lGLOX

toLZ

0

0

-

0

-

ns

Enable Low to Output Active

-

-

Enable High to Output High-Z

tEHOZ

tcHZ

0

8

0

9

0

Output Enable High to Output High-Z

lGHOZ

toHZ

0

7

0

8

Power Up Time

tELICCH

tpu

0

0

Power Down Time

tEHICCL

tpo

-

15

-

Unit Notes

3
4

ns

5,6,7

ns

5,6,7

10

ns

5,6,7

0

10

ns

5,6,7

-

0

-

ns

20

-

25

ns

NOTES:
1. Wis high for read cycle.
2. For devices with multiple chip enables, Ef and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with Egoing low.
5. At any given voltage and temperature, tEHOZ max < tELOX min, and tGHOZ max < tGLOX min, both for a given device and from device to
device.
6. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected. E ,; VIL and G ,; VIL.

MOTOROLA MEMORY DATA

MCM6209

READ CYCLE 1 (See Note 8)
tAVAV
A(ADDRESS)
tAXQXQ(DATAOUn

PREVIOUS DATA VALID

DATA VALID

READ CYCLE 2 (See Notes 2 and 4)

•
A(ADDRESS)

•

tAVAV

V

~

E(CHIP ENABLE)

,•

•

tELQV

I!.-I EHQZ...-tGHQZ-

'4-tELQX.tGLQX--

G(OUTPUT ENABLE)

II

\.
tGLQV-

ifX'IYYX.. if

Q(DATAOUn

-V

tELICCH

VCC
SUPPLY CURRENT

ICC

DATA VALID

•

tAVQV

-----------

I SB

-

tELICCL-

'\

AC TEST LOADS
+5V
OUTPUT

480

D-HI,L-------/...L~
..r:

Q

la=50 Q

Q

RL=50Q
255

5pF
(INCLUDING
SCOPE AND JIG)

Q

VL=1.5V

Figure 1A

Figure 18

TIMING PARAMETER ABBREVIATIONS

txxxx
signal name from which interval is defined
transition direction for first signal
signal name to which interval is defined
transition direction for second Signal

I

III

The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)

TIMING LIMITS
The table of timing values shows either a minimum or a maximum
limitfor each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a
minimum since the system must supply at least that much time (even
though most devices do not require it). On the other hand, responses
from the memory are specified from the device point of view. Thus, the
access time is shown as a maximum since the device output will be
valid no later than that time.

MOTOROLA MEMORY DATA
5-66

MCM6209

WRITE CYCLE 1 (W Controlled) (See Notes I, 2, and 3)
-15

Symbol
Parameter

-25

-,20

Std

All

Min

Max

Min

Max

Min

Write Cycle Time

IAVAV

Iwe

15

20

IAVWL

lAS

0

-

25

Address Setup Time

-

-

10

0

0

Max Unit Notes

-

ns

-

ns

0
0

10

ns

6,7,8

ns

6,7,8

0

-

0

Address Valid to End of Write

IAVWH

lAW

12

Write Pulse Width

twLWH,
twLEH

twp

12

Write Pulse Width, High
(Output Enable devices)

twLWH,
twLEH

twp

10

Data Valid to End of Write

IOVWH

tow

7

Data Hold Time

twHOX

toH

0

-

Write Low to Output High-Z

twLOZ

twz

0

7

0

8

4
0

-

Min

Max

Min

Max

20

-

25

0

-

0

15

-

20

-

-

10

Write High to Output Active

twHQX

tow

4

Write Recovery Time

twHAX

twA

0

Max

15
15
12
8

20
20
15

4

4

ns
ns

I

ns

I

ns

5

ns

ns

WRITE CYCLE 2 (E Controlled) (See Notes 1 2 and 3)
Sid

All

Min

Write Cycle Time

Parameter

IAVAV

15

Address Setup Time

IAVEL

twe
lAS

0

Address Valid to End of Write

IAVEH

lAW

12

Enable to End of Write

IELEH'
tELWH

lew

10

Data Valid to End of Write

IOVEH

lOW

7

Data Hold Time

IEHOX

toH

0

Write Recovery Time

teHAX

twR

0

-

12

8
0
0

15

0
0

-

Unll Noles
ns
ns
ns
ns
ns
ns

NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. For devices with multiple chip enables, E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. For Output Enable devices, if G goes low coincident with or after Wgoes low, the output will remain in a high-impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. For Output Enable devices, if G ~ VIH, the output will remain in a high-impedance stale.
6. At any given voltage and temperature, twLQG max < twHQX min, both for a given device and from device to device.
7. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
8. This parameter is sampled and not 100% tested.
9. If E goes low coincident with or after Wgoes low, the output will remain in a high-impedance state.
10.1f E goes high coincident with or before Wgoes high, the output will remain in a high-impedance state.

MOTOROLA MEMORY DATA

4

ns
9,10

MCM6209

WRITE CYCLE 1 (See Note 2)
I AVAV
A (ADDRESS)

I~.~::::::::::~I~~;~;H~::::::::::::::.~~--IW~
E (CHIP ENABLE)
~

_ _ _ _ IWLWH _ _ _ _....

------~--------~

IWLEH

W (WRITE ENABLE)
IDVWH

o(DATA IN)

r------------------

- 1 - - - 1 - IWHDX

DATA VALID

HIGHZ

Q(DATAOUT)

WRITE CYCLE 2 (See Note 2)

.

I AVAV

1/

A(ADDRESS)

i\
IAVEH

E (CHIP ENABLE)
-IAVEL-r\

I-----

t ELEH
tELWH

tEHAX·

W (WRITE ENABLE)

\7\1;

D(DATAIN)

XXXXXXXXXXXXXXXXJX\i

I

I-

DVEH

DATA VALID

I

~~

~XX

Q(DA~OUT)------------------------~H~IG~H.~Z--------------------------------

ORDERING INFORMATION (Order by Full Part Number)
MCM
6209
X XX
XX

Motorola Memory Prefix
Part Number

---==r-- T

TL-=:

Shipping Method (R2 = Tape & Reel, Blank = Rails)
Speed (15 = 15 ns, 20 = 20 ns, 25 = 25 ns)

Package (P = 300-mil Plastic DIP, J = 300-mil SOJ)
Full Part Numbers-MCM6209P15
MCM6209J15
MCM6209J15R2
MCM6209P20
MCM6209J20
MCM6209J20R2
MCM6209P25
MCM6209J25
MCM6209J25R2

MOTOROLA MEMORY DATA

MOTOROLA

• SEMICONDUCTOR
TECHNICAL DATA

MCM6209C

Advance Information
64K x 4 Bit Fast Static RAM
With Output Enable
The MCM6209C is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is available in plastic dual-in-line and plastic small-outline J-Ieaded packages.
•
•
•
•
•

Single 5 V ±1 0% Power Supply
Fully Static - No Clock or Timing Strobes Necessary
Fast Access Times: 15, 20, and 25 ns
Equal Address and Chip Enable Access Times
Output Enable (G) Feature for Increased System Flexibility and to Eliminate
Bus Contention Problem

• Low Power Operation: 135 -155 rnA Maximum ac
• Fully TTL Compatible - Three -State Output

BLOCK DIAGRAM

~

PPACKAGE
300 MIL PLASTIC
CASE 710B

~PACKAGE

300 MILSOJ
CASE 810B

PIN ASSIGNMENTS
NC

VCC

AO

A15

A1

A14

A2

A13

A3

A12

-VCC

A4

A11

-VSS

A5

A10

A6

NC

A7

NC

MEMORY MATRIX
256 ROWS x
256 x 4 COLUMNS

AS

DOO

A9

D01

E
G

D02
D03

Vi

VSS

DOO.
D01

PIN NAMES

D02-TTl, __"-'

AQ-A 15 .............. Address Input
DOO-D03 .... Data Input/Data Output
Vi .................... Write Enable
G .................... Output Enable
E ...................... Chip Enable
NC ................. No Connection
VCC .......... Power Supply (+ 5 V)
VSS ....................... Ground

D03

E~--'

Vi
G

ThIS document contams information on a product under development. Motorola reserves the nght to change or dIscontinue thIS product without notice.

MOTOROLA MEMORY DATA
5-69

MCM6209C

TRUTH TABLE (X = don't care)
E

G

W

Mode

VCC Current

Output

Cycle

H

'X

L

H

X

Not Selected

ISB1,ISB2

High-Z

H

Output Disabled

ICCA

High-Z

-

L
L

L

H

Read

ICCA

X

L

Write

ICCA

Dout
High-Z

Write Cycle

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated vohages to this high-impedance circuit.

Read Cycle

This CMOS memory circuit has
been designed to meet the dc and
ac specifications shown in the
tables, after thermal equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse air flow
of at least 500 linear feet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Power Supply Voltage
Voltage Relative to VSS For Any Pin
ExceptVcc
Output Current
Power Dissipation
Temperature Under Bias (TA = 25'C)
Operating Temperature

Value

Unit

VCC

-0.5to+ 7.0V

V

Yin' Vout

- 0.5 to VCC + 0.5

V

lout
Po

±20

rnA

1.0

W

Tbias
TA

-10to+85

'c

Oto + 70

'c

Storage Temperature - Plastic

-55to+ 125
'C
Tslo
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70 oe, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH
VII

2.2

-

VCC +0.3"

V

0.8

V

Input Low Voltage

-OS

• VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width $ 20 ns)
"VIH (max) =VCC + 0.3 V dc; VIH (max) =VCC + 2.0 V ac (pulse width $ 20 ns)

DC CHARACTERISTICS
Parameter
Output Leakage Current (E

Max

Unit

-

±1.0
±1.0

J.IA
J.IA

-

20

rnA

VOL

-

0.4

V

VOH

2.4

-

V

IlkaCll

=VIH or G =VIH, VOu! =0 to VCC)

IlkarOl
ISB2

Standby Current (E ~ VCC - 0.2 V', Vin;; VSS + 0.2 V,
or~ VCC-0.2 V, VCC = MAX, f =0 mHz)
Oulput Low Voltage (IOL =8.0 rnA)
Output High Voltage (IOH

Min

Symbol

Input Leakage Current (All Inputs, Vin =a to VCC)

=-4.0 rnA)

POWER SUPPLY CURRENTS
Parameter
AC Active Supply Current (lout =0 rnA, VCC =Max, f =fmax)
AC Standby Current (E

=VIH, VCC =MAX, f =fmax)

Symbol

-15

-20

-25

Unit

ICCA

155

145

135

rnA

ISBI

50

45

40

rnA

MOTOROLA MEMORY DATA

5-70

MCM6209C

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25 C, Periodically sampled rather than 100% tested)
Q

Symbol

Max

Unit

Address and Data Input Capacitance

Cin

6

pF

Control Pin Input Capacitance (E,G,W)

Cin

6

pF

Characteristic

Output Capacitance

8
Cout
'For devices with multiple chip enables, El and E2 are represented by E in this data shee\. E2 is of opposite polarity to E

pF

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, T A = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall Time ..................................... 5 ns

Output Timing Measurement Reference Level ............. 1.5 V
Output Load ................. Figure 1A Unless Otherwise Noted

READ CYCLE (See Notes 1 and 2)
Symbol
Parameter

-15

-25

-20

Std.

All.

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

tRC

15

-

20

-

25

-

ns

3

Address Access Time

tAVOV

tAA

-

15

-

20

-

25

ns

15

-

20

ns

10

-

25

8

12

ns

Enable Access Time

tELOV

tACS

Output Enable Access Time

tGLOV

toE

-

Output Hold from Address Change

tAXOX

toH

4

-

4

-

4

-

ns

5,6,7

Enable Low to Output Active'

tELOX

teLZ

4

-

4

-

4

-

ns

5,6,7

Enable High to Output High-Z

tEHOZ

tCHZ

0

8

0

9

0

10

ns

5,6,7

Output Enable Low to Output Active

'GLOX

toLZ

0

-

0

-

0

-

ns

5,6,7

Output Enable High to Output Hlgh-Z

'GHOZ

toHZ
tpu

0

7

0

8

0

10

ns

5,6,7

0

-

0

-

0

-

ns

Power Up Time

tELICCH

-

-

4

15
20
25
ns
tpD
tEHICCL
W is high for read cycle.
For devices with multiple chip enables, Ef and E2 are represented by E in this data shee\. E2 is of opposite polarity to E.
All timings are referenced from the last valid address to the first transitioning address.
Addresses valid prior to or coincident with E going low.
At any given voltage and temperature, tEHOZ max is less than tELOX (min), and 'GHOZ (max) is less than tGLOX (min), both for a
given device and from device to device.
6. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E = VIL, E2 = VIH, G = VIU.

Power Down Time
NOTES: 1.
2.
3.
4.
5.

MOTOROLA MEMORY DATA
5-71

MCM6209C

t:

A (ADDRESS)

------~

Q(DATAOUT)

READ CYCLE 1 (See Note 8)

~

~J

)1\

~tAA~Q;X~====~.~!------------~------------~

PREVIOUS DATA VALID

------

DATA VALID

14------------ tAVQV

READ CYCLE 2 (See Notes 2 and 4)
tAVAV

V
\.

A (ADDRESS)

\V

I\.

tELQV

\

E(CHIP ENABLE)

1/
J

I\.

,I-- tELOX /

1\

G(OUTPUT ENABLE)

!--IGHOz--

IGLQVHIGHZ

Q(DATAOUT)

!--tEHOZ--

If

I-IGLOX -

XXXX)K

tAVQV

HIGHZ

DATAVAUD

I--

SUPPLYCURR~~ -------------r-----------------------------=1L
teLlCCH ICC
ISB ___________..J.

AC TEST LOADS

nMING LIMITS
The table of timing values shows either a mini-

+5V480n

lo= son
Q

~

255 n

5pF
(INCLUDING
SCOPE AND JIG)

....
Figure 1A

tEHICCL

mum or a maximum limit for each parameter. Input requirements are specified from the external
system point of view. Thus, address setup time is
shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand,
responses from the memory are specified from
the device point of view. Thus, the access time is
shown as a maximum since the device never provides data later than that time.

Figure 18

MOTOROLA MEMORY DATA
5-72

MCM6209C

WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 3)
Symbol
Parameter

-15

-20

Std.

Alt.

Min

Max

Min

Write Cycle Time

tAVAV

twc

15

-

20

Address Setup Time

tAVWL

tAS

a

-

a

Address Valid to End 01 Write

tAVWH

tAW

12

Write Pulse Width

twLWH,
twLEH

twP

12

15

Write Pulse Width,
GHigh

twLWH,
tWLEH

twP

10

Data Valid to End 01 Write

tDVWH

tow

7

Data Hold Time

twHDX

tOH

-

Write Low to Output High-Z

tWLQZ

twz

a
a

7

a
a

Write High to Output Active

twHOX

tow

4

-

Write Recovery Time

twHAX

twR

a

-

15
12

8

-25

Max

Min

Max

Unit

Notes

-

25

ns

4

-

-

a

-

ns

20

-

ns

20

-

ns

15

-

ns

10

-

ns

10

5

8

a
a

ns

6,7,8

4

-

4

-

ns

6,7,8

a

-

a

-

ns

ns

WRITE CYCLE 2 (E Controlled See Notes 1, 2, and 3)
Symbol
Parameter

-20

-15

-25

Std.

Alt.

Min

Max

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

twc

15

20

25

-

ns

4

Address Setup Time

tAVEL

tAS

a

-

a

ns

Address Valid to End 01 Write

tAVEH

tAW

12

-

15

20

-

Enable to End of Write

tELEH,
tELWH

lew

10

-

-

12

-

15

-

ns

Data Valid to End of Write

tOVEH

tow

7

-

8

-

10

ns

tEHOX

tDH

a
a

-

a
a

-

-

Data Hold Time

a
a

-

ns

Write Recovery Time

a

-

ns
9,10

ns
tFHAX
tWR
NOTES: 1. A write occurs during the overlap 01 E low and W low.
2. For devices with multiple chip enables, E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. For Output Enable devices, il G goes low coincident with or after Wgoes low, the output will remain in a high impedance state.
4. All timings are referenced from the last valid address to the lirst transitioning address.
5. For Output Enable devices, ilG ~ VIH;the output will remain in a high impedance state.
6. At any given voltage and temperature, twLOZ max is less than tWHOX min, both for a given device and from device to device.
7. Transition is measured ± 500 mV from steady-state voltage with load 01 Figure lB.
8. This parameter is sampled and not 100% tested.
9. II E goes low coincident with or after Wgoes low, the output will remain in a high impedance state.
10. If E goes high coincident with or before Wgoes high, the output will remain in a high impedance state.

MOTOROLA MEMORY DATA
5-73

MCM6209C

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
tAVAV

---------t

A(ADDRESS)

t--------

tAVWH ------+ot---IIoj- twHAX

E(CHIP ENABLE)

Vi (WRITE ENABLE)
tOVWH

o(DATA IN)

---.I--+-

DATA VALID

HIGHZ

Q (DATA OUT) --..:.::.::::.:..:---(

WRITE CYCLE 1 (I: Controlled, See Notes 1 and 2)
tAVAV - - - - - - - - - - 1
A(ADDRESS)
tAVEH

----------*1

E(CHIP ENABLE) ----------~----------------~

r---+-------

---oo+----+- tEHAX
Vi (WRITE ENABLE)

o(DATA IN)
Q(OATAOUT) _ _ _ _ _ _ _ _ _ _ _ _ _ _....:.:H"'IG:.:.,HZ"--_ _ _ _ _ _ _ _ _ _ _ _ _ __

ORDERING INFORMATION (Order by Full Part Number)
MCM
Motorola Memory Prefix
Part Number

~

T T1-=:
6209C

X

XX

XX

Shipping Method (R2 = Tape & Reel, Blank = Rails)
Speed (15 = 15 ns, 20 = 20 ns, 25 = 25 ns)

Package (P = 300 mil Plastic DIP, J = 300 mil SOJ)
Full Part Numbers- MCM6209CP15
MCM6209CP20
MCM6209CP25

MCM6209CJ15
MCM6209CJ20
MCM6209CJ25

MOTOROLA MEMORY DATA
5-74

MCM6209CJ15R2
MCM6209CJ20R2
MCM6209CJ25R2

MOTOROLA

• SEMICONDUCTOR
TECHNICAL DATA

MCM6226

128K X 8 Bit Static Random
Access Memory
The MCM6226 is a 1,048,576 bit static random-access memory organized as
131,072 words of 8 bits, fabricated using high-performance silicon-gate CMOS
technology. Static design eliminates the need for external clocks or timing strobes
while CMOS circuitry reduces power consumption and provides for greater reliability.
The MCM6226 is equipped with both chip enable (E1 and E2) and output enable
(<3) pins, allowing for greater system flexibility and eliminating bus contention
problems.
The MCM6226 is available in a 400-mil, 32-lead surface-mount SOJ package.
• Single 5 V ± 10% Power Supply
• Fast Access lime: 25/30 ns
• Equal Address and Chip Enable Access lime
• All Inputs and Outputs are TTL Compatible
• Three State Outputs
• Low Power Operation: 170/165 rnA Maximum, Active ac
BLOCK DIAGRAM

AS----I

A4---t
A7---t
A6---t

AS---t
Al0---t

ROW
DECODER

•
•
•

MEMORY MATRIX
. S12AOWSx

2048 COLUMNS

AS---t

,

WJPACKAGE

400-MILSOJ
CASE867A

'I'
PIN ASSIGNMENT

Ne

Vee

AO

A16

Al

E2

A2

W

AS

A15

A4

A14

AS

A13

AS

A12

A7

G

AS

All

AS

E1

Al0

007

oao

DQ6

001

DOS

002

DQ4

VSS

DQ3

AS---t
Al---t
PIN NAMES

DOO--..-t

eOLUMNYO

••
•
007-.....+-1

E1
E2

w-+--+
G---- vDC; vlL (min) -

-.w vAC (pulse wIDtn,,",u ns); vlH (max) = vcc + "' vAC (PU se WlDt

Unit

""uns).

DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter

Symbol

Min

Max

Unit

±1

IlA
IlA

Input Leakage Current (All Inputs, Yin = 0 to VCC)

Ilkg(l)

Output Leakage Current (E' = VIH, Vout = 0 to VCC)

Ilkg(O)

-

AC Active Supply Current (lout = 0 mA, VCC = max)
MCM6226A-20: tAVAV = 20 ns
MCM6226A-25: tAVAV = 25 ns
MCM6226A-30: tAVAV = 30 ns

ICCA

-

AC Standby Current (VCC = max, E'= VIH, I = Imax)

ISBI

-

20

mA

CMOS Standby Current (E':1: VCC - 0.2 V,
Yin "VSS + 0.2 Vor:1: VCC-0.2 V, VCC = max, I

ISB2

-

15

mA

VOL

-

0.4

V

VOH

2.4

-

V

= 0 MHz)

Output Low Voltage (IOL = + 8.0 mAl
Output High Voltage (lOH

=-

4.0 mAl

'El and E2 are represented by E In thiS data sheet. E2 IS 01 oPPOsite polanty to El'

MOTOROLA MEMORY DATA
5-83

±1

mA
155
135
115

MCM6226A

CAPACITANCE (f -- 1 a MHz dV -- 3 a v TA -- 25°C Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance

Symbol

Max

Max

Unit

All Inputs Except Clocks and DO
E2,G,W

Cin
Cck

4
5

6
8

pF

DO

CliO

5

8

pF

E1,

110 Capacitance

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, T A = 0 to + 70 o e, Unless Otherwise Noted)
Input Pulse Levels. . . . . . . .. . . . . . . . .. . . . . . . . .. 0 to 3.0 V
Input Rise/Fall Time .............................. 2 ns
Input Timing Measurement Reference Level ........ 1.5 V

Output Timing Measurement Reference Level ....... 1.5 V
Output Load ............................ See Figure 1a

READ CYCLE TIMING (See Notes 1, 2 and 9)
Symbol
Parameter

MCM6226A·20

MCM6226A·25

MCM6226A-30

Standard

Alternate

Min

Max

Min

Max

Min

Unit

Notes

Read Cycle Time

tAVAV

tRC

20

-

25

-

30

-

ns

3

Address Access Time

tAVOV

tAA

-

20

-

25

30

ns

30

ns

15

ns

-

ns

-

ns

4,5,6

12

ns

4,5,6

10

a
a
a

12

ns

4,5,6

-

0

-

ns

25

-

30

ns

Enable Access Time

tELOV

tACS

-

20

-

25

Output Enable Access Time

'GLOV

tOE

-

10

-

12

-

Output Hold from Address Change

tAXOX

toH

5

-

5

-

5

Enable Low to Output Active

tELOX

tLZ

5

5

-

5

tLZ

-

Enable High to Output High-Z

tEHOZ

Output Enable High to Output High-Z

'GHOZ

tHZ

Power Up Time

tELICCH

tpu

a
a
a
a

Power Down Time

tEHICCL

tpD

-

Output Enable Low to Output Active

'GLOX

tHZ

-

a
a
a
a

20

-

9
9

10

Max

ns

8

4,5,6

NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention
conditions during read and write cycles.
3. All timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHOZ (max) is less than tELOX (min), and tGHOZ (max) is less than 'GLOX (min), both for a given
device and from device to device.
5. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1b.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E":;; VIL, G:;; VILl.
a. Addresses valid prior to or coincident with E going low.
9.
and E2 are represented by E in this data sheet. E2 is of opposite polarity to

E1

E1.

READ CYCLE 1 (See Notes 1, 2, 7, and 9)

.1

tAVAV

t

A (ADDRESS)

-'

~tAXOX

o(DATA OUT)

PREVIOUS DATA VALID

ixxxx>g(

tAVOV

MOTOROLA MEMORY DATA

DATA VALID

MCM6226A

READ CYCLE 2 (See Notes 8 and 9)
_I

tAVAV
A (ADDRESS)

fc---

*

tELQV

E(CHIP ENABLE)

r---

tELQX-

{

G(OUTPUT ENABLE)
~IGLQX--

HIGH-Z
Q (DATA OUT)

-------+

ICC

--- --

IGLQV-

'YXXX

~

tEHQZ

f-----.

IGHQZ

DATA VALID

tAVQV
tELICCH

Ie- tEHICCL

-t=
J

SUPPLY CURRENT ISB _ _ _ _ _ _ _ _

WRITE CYCLE 1 (W Controlled, See Notes 1, 2, 7 and 8)
Symbol
Parameter

Standard

MCM6226A·20

MCM6226A·25

Alternate

Min

-

25
0

Write Cycle Time

tAVAV

twe

20

Address Setup Time

tAVWL

tAS

0

Max

Min

Max

MCM6226A·30
Min

Max

Unit

Notes

-

30

-

ns

3

0

-

ns

20

-

25

-

ns

20

-

25

-

ns

Address Valid to End of Write

tAVWH

tAW

t5

Write Pulse Width

twLWH

twP

15

-

Data Valid to End of Write

toVWH

tow

10

-

12

-

15

-

ns

Data Hold Time

twHoX

toH

0

-

0

-

0

-

ns

Write Low to Data High-Z

twLOZ

twz

0

9

0

10

0

12

ns

4,5,6

Write High to Output Active

twHOX

tow

5

5

4,5,6

tWR

0

-

ns

twHAX

-

5

Write Recovery Time

-

0

0

ns

NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivITies to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1b.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, twLOZ (max) is less than twHOX (min) both for a given device and from device to device.
7. E;" and E2 are represented by E in this data sheet. E2 is of opposite polarity to E;".
8. If G goes low coincident with or after Wgoes low, the output will remain in a high-impedance state.

MOTOROLA MEMORY DATA

MCM6226A

WRITE CYCLE 1 (W Controlled, S~ Notes I, 2, 7 and 8)
tAVAV

----------+1

A(ADDRESS)
tAVWH - - - - - - - - - I o t + - - . J

twHAX

E(CHIP ENABLE)

1+------- tWLwH ------~

----t!:!.----

twLEH

iii (WRITE ENABLE)
1+----

tDVWH----~_+!

o(DATA IN)

DATA VALID

HIGH·Z

HIGH·Z

Q(DATAOUT)

AC TEST LOADS

TIMING LIMITS
+5V

4800
OUTPUl

OUTPUT~
Zo=500

ll"-'~D

2SSn

VL=1.5V
(a)

i=

5pF
(INCLUDING
SCOPE AND JIG)

~
(b)

figure 1

MOTOROLA MEMORY DATA

The table of timing values shows either
a minimum or a maximum limn for each
parameter. Input requirements are speci·
fiedfrom the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that much time (even though most
devices do not require tt). On the other
hand, responses from the memory are
specified from the module point of view.
Thus, the access time is shown as a maxi·
mum since the module never provides
data later than that time.

MCM6226A

I',

WRITE CYCLE 2 (E Controlled, See Notes 1, 2, 6 and 7)
Symbol
Parameter
Write Cycle Time

MCM6226A-20

Standard

Alternate

Min

tAVAV

twc

20

Max

tAVEL

tAS

0

Address Valid to End of Write

tAVEH

tAW

15

lew

15

-

tELEH

Min

-

Address Setup Time

Enable to End of Wrile

MCM6226A-25

MCM6226A-30

Max

Min

Max

Unit

Notes
3

25

-

30

-

ns

0

-

0

-

ns

20

-

25

-

ns

20

-

25

-

ns

20

-

ns

25

-

ns

Enable to End of Write

IELWH

ICW

15

Write Pulse Width

twLEH

twp

15

-

20

-

25

Data Valid to End of Write

tDVEH

tow

8

-

10

-

12

Data Hold Time

tEHOX

tOH

0

0

Write Recovery Time

tEHAX

twR

0

-

-

0

0
0

4,5

ns
ns
ns

NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and wrne cycles.
3. All timings are referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after Wgoes low, the output will remain in a high-impedance state.
5. If E goes high coincident with or before Wgoes high, the output will remain in a high-impedance state.
6. ELand E2 are represented by E in th~ data sheet. E2 is of opposite polarity to E1.
7. If G goes low coincident with or after W goes low, the output will remain in a high-impedance state.

WRITE CYCLE 2 (E Controlled, See Notes 1, 2, 6 and 7)
'AVAV
A (ADDRESS)
tAVEH
-

'ELEH-

E(CHIP ENABLE)
'AVEL

tELWH

tEHAX

W(WRITE ENABLE)
'OVEH-

o(DATA IN)

xxxxxxxxxxxxxxxxxxxxxxXXXXXXEOATA VALID

*Xi:£Xm

--I'~tEHOX

Q(OATAOUT)

HIGH-Z

MOTOROLA MEMORY DATA

Il
II

II

MCM6226A

ORDERING INFORMATION
(Order by Full Part Number)

TT
xx

Motorola Memory Prefix
Part Number

xx

1..-_ _ _ _ _ _

"'.... -"".,.. ....,.... Speed (20 • 20 ns. 25 • 25 ns. 30 - 30 ns)
Package (W =4OO-mil. J

Full Part Numbers - MCM6226AWJ2O
MCM6226AWJ25
MCM6226AWJ30

MOTOROLA MEMORY DATA

=SOJ)

.

MOTOROLA

.SEMICONDUCTOR . . . . . . . . . . . . . . . . . . . . . . . . . ...
TECHNICAL DATA

MCM6229

256K X 4 Bit Static Random
Access Memory
The MCM6229 is a 1.048.576 bit static random-access memory organized as
262.144 words of 4 bits. fabricated using high-performance silicon-gate CMOS
technology. Static design eliminates the need for external clocks or timing strobes
while CMOS circuitry reduces power consumption and provides for greater reliability.
The MCM6229 is equipped with both chip enable (E) and output enable (G) pins.
allowing for greater system flexibility and eliminating bus contention problems. Either
input. when high. will force the outputs to high impedance.
The MCM6229 is available in a 400-mil. 28-lead surface-mount SOJ package.
•

Single 5 V ± 10% Power Supply

•

Fast Access Time: 25/30 ns

•

Equal Address and Chip Enable Access Times

•

All Inputs and Outputs are TIL-Compatible

•

Three-State Outputs

•

WJ PACKAGE
400-MILSOJ
CASE 810-03

PIN ASSIGNMENT

AD

Low Power Operation. 170/165 mA Maximum. Active ac

BLOCK DIAGRAM

A3

1.

AI

2

A2

3

D Vcc
~ A17
26 ~ A16
25 D A15
24 D A14
28

27

A3

4

A4

5

AS

6

23

A6

7

22

A12

A7

8

21

All
NC

~

A13

A4

AS

9

20

A7

A9

10

19

DC3

Al0

11

18

002

A6

•

A5

Al0

•

.MEMORY MATRIX·
Sl2 flOWS X.,:
2048 COlUMNS

E
G
VSS

12

17

001

13

16

000

14

15

W

A9

A8
PIN NAMES

AI
~A17

............... Address Inputs
W ....................... Write Enable
Q ..................... Output Enable
E ....................... Chip Enable
DOD-D03 ........ Data Inputs/Outputs
NC . . . . . . . . . . . . . . . . . . . . .. No Connect
VCC ............. + 5 V Power Supply
VSS ........................ Ground

000

003

W===~~~------------~--4
G

MOTOROLA MEMORY DATA

5-89

MCM6229

MCM6229 TRUTH TABLE
E

H

G

W

H

X

L

H

L
L

110 Pin

X

Not Selected

High-Z

H

Output Disabled

High-Z

-

L

H

Reed

Dout

Read

ICCA

X

L

Write

Din

Write

ICCA

=High, L - Low, X -

This device contains circunry to
protect the inputs against damage
due to high static voltages or electric
lields; however, it is advised that
norrnai precautions be taken to
avoid application 01 any voltage
higher than maximum rated voltages
to these high-impedance circuits.

Current

Mode

Cycle

IISB1,ISB2
ICCA

Don t Care

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-0.5t07.0

V

Yin, Vout

-0.5 to VCC +0.5

V

Output Current (per 1/0)

lout

±20

mA

Power Dissipation (TA = 25·C)

Po

1.1

W

Temperature Under Bias

Tbias

-10to+85

·C

Operating Temperature

TA

Oto + 70

·C

Power Supply Voltage Relative to VSS
Vo~age

ss lor Any Pin

Relative to V
ExceptVcc

This CMOS memory circuit has
been designed to meellhe dc and ac
specilications shown In the tables,
aiter thermal equilibrium has been
established. The circuit is in a test
sacket or mounted on a printed
circuit board and transverse air Ilow
01 at least 500 linear leet per minute
is maintained.

·C
Storage Temperature
-55 to + 150
Tsto
NOTE: Permanent device damage may occur Ii ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended vo~ages lor extended periods 01
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to + 70o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.5

V

Input High Voltage

VIH

2.2

VCC+ 0.3

V

Parameter

.

0.8
-OS
VIL
VIL (min) = -' ...,.

=30 ns, 35 = 35 ns)

•

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6249

Product Preview
1M x 4 Bit Static Random
Access Memory

•

The MCM6249 is a 4,194,304 bit static random access memory organized as
1,048,576 words of 4 bits, fabricated using high-performance silicon-gate CMOS
technology. Static design eliminates the need for external clocks or timing strobes,
while CMOS circuitry reduces power consumption and provides for greater reliability.
The MCM6249 is equipped with chip enable (EO) and output enable (<3) pins,
allowing for greater system flexibility and eliminating bus contention problems. Either
input, when high, will force the outputs into high impedance.
The MCM6249 is available in a 400-mil, 32-lead surface-mount SOJ package.
• Single 5 V ± 10% Power Supply
• Fast Access Time: 25/30/35 ns
• Equal Address and Chip Enable Access Time
• All Inputs and Outputs are TTL Compatible
• Three-State Outputs
• Power Operation: 160/155/150 rnA Maximum, Active ac

,

WJPACKAGE
400-MILSOJ
CASE 857A-01

I.

PIN ASSIGNMENT

Ad

32 AI

AS! 2

31

AO

A9 ! 3

30

AS

A17! 4

29

A4

A61 5

28

AI9

6

27

G

0001 7

26

003

I8
Vss I 9

25

VSS

24

vcc

All

Dod 10

23

002

AIO

wi II

22

A2

BLOCK DIAGRAM

'EI
A13

VCC

AI2

A9
A8
A7

ROW
DECODER

•
•
•

MEMORY MATRIX
1024 ROWS x
4096 COLUMNS

A6

AI31 12

21

AlB

AlB I 13

20

AI5

AIO I 14

19

AI4

All

15

18~ A3

AI2

16

17P N/C

A5

A4
PIN NAMES
AD-A 19 ............... Address Inputs
IN ....................... Wrije Enable
G ........ .. .. .. .. .. ... Output Enable
E ....................... Chip Enable
DOD-D03 .......... Data InpuVOulput
NC .. . . . . . . . .. . . .. . .. . . .. No Connect
Vee ............. + 5 V Power Supply
VSS ........................ Ground

DOC

•
••
003

WI-=~~~----

G-

__________-+______~

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
5-108

MCM6249

MCM6249 TRUTH TABLE

X

Mode

Cycle

G

H

X

X

Not Selected

High-Z

-

IISB1,ISB2

L

H

H

Output Disabled

High-Z

-

ICCA

L

L

H

Read

Dout

Read

ICCA

L

X

L

Write

High-Z

Write

ICCA

W

1/0 Pin

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to these high impedance circuits.

Current

E

= DontCare

This CMOS memory circuit has
been designed to meet the de and ac
specifications shown in the tables,
after thermal equilibrium has been
established. The circuit is in a test
socket or mounted on a printed
circuit board and transverse air flow
of at least 500 linear feet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

- 0.5 to 7.0

V

Yin, Vout

- 0.5 to VCC + 0.5

V

Output Current (per 1/0)

lout

± 20

mA

Power Dissipation (TA = 25'C)

Po

1.0

W

Tbias

-10to+85

'C

TA

oto + 70

'C

Power Supply Voltage Relative to VSS
Voltage Relative to VSS for Any Pin
Except VCC

Temperature Under Bias
Operating Temperature
Storage Temperature -

Plastic

-55to+150
'c
Tsto
NOTE: Permanent device damage may aceu"f ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vce = 5.0 V ± 10%, T A = 0 to + 70 oe, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage

.

Input Low Voltage

Symbol

Min

Typ

Max

Unit

VCC

4.5

5.0

5.5

V

VIH

2.2

-

VCC+ 0.3

V

VIL

-OS

-

0.8

V

Symbol

Min

Typ

Max

Unit

-

-

±1.0

-

-

±1.0

JlA
JlA

150

160

mA

140

150

VIL (min) = - 0.5 V dc, VIL (min) = - 2.0 V ac (pulse width" 20 ns).

DC CHARACTERISTICS AND AC CURRENTS
Parameter
Input Leakage Current (All Inputs, Yin = 0 to Vccl

Ilkg(l)

Output Leakage Current (E = VIH, Vout = 0 to Vccl

Ilkg(O)

AC Active Supply Current (lout = 0 mAl
(VCC=max)

MCM6249-25: tAVAV = 25 ns

ICC

MCM6249-30: tAVAV = 30 ns
MCM6249-35: tAVAV = 35 ns

AC Standby Current (VCC = max)

(E: = VIH, No other restrictions on other inputs)

MCM6249-25: tAVAV = 25 ns

ISBI

MCM6249-30: tAVAV = 30 ns
MCM6249-35: tAVAV = 35 ns

CMOS Standby Current (E ;'VCC-0.2 V, Vin" VSS + 0.2 Vor;, VCC-0.2 V)

ISB2

-

130

140

-

50
40

50

-

35

40

-

10

15

60

mA

mA

(VCC = max, f = 0 MHz)
Output Low Voltage (lOL = + 8.0 mAl
Output High Voltage (lOH = - 4.0 mAl

VOL

-

-

0.4

V

VOH

2.4

-

-

V

MOTOROLA MEMORY DATA
5-109

MCM6249

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25'C, Periodically Sampled Rather Than 100% Tested)
Symbol

Typ

Max

Unit

4
5

6
8

pF

E,G,W

Cin
Cck

DO

CliO

5

8

pF

. Characteristic
(All Inputs Except E and DO)

Input Capacitance
Input/Output Capacitance

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to + 70 o e, Unless Otherwise Noted)
Input Pulse Levels ........................... 0 to 3.0 V
Input Rise/Fall Time .............................. 2 ns
Input Timing Measurement Reference Level ........ 1.5 V

Output Timing Measurement Reference Level ....... 1.5 V
Output Load ............................. See Figure 1

READ CYCLE TIMING (See Note 1)
Symbol

MCM6249-25

MCM6249-30

Standard

Alternate

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

tRC

25

-

30

-

35

-

ns

2,3

Address Access Time

tAVOV

tAA

25

30

ns

tELOV

tACS

25

35

ns

12

-

13

-

35

Enable Access Time

-

14

ns

5

5

0

-

ns

0

-

Parametar

Output Enable Access Time

IGLOV

toE

-

Output Hold from Address Change

tAXOX

toH

5
5

30

MCM6249-35

tELOX

tLZ

Output Enable Low to Output Active

tGLOX

tLZ

0

-

Enable High to Output High-Z

tEHOZ

tHZ

0

12

0

14

0

Output Enable High to Output High-Z

IGHOZ

tHZ

0

12

0

14

tELICCH

tpu

0

-

0

-

Enable Low to Output Active

Power Up Time

-

5

-

8

ns

4,5,6

ns

4,5,6

16

ns

4,5,6

0

16

ns

4,5,6

0

-

ns

5

-

Power Down Time
25
30
35
ns
tpD
tEHICCL
NOTES:
1. Wis high for read c;ycle.
2. Productsensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention
conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHOZ max < tELOX min, and IGHOZ max < tGHOX min, both for a given device and from device to
device.
' .
.
5. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E ~ VIL, G ~ VILl.
8. Addresses valid prior to or coincident with E going low.
READ CYCLE 1 (See Note 7 Above)

~-----------------~V~--------------------~~

E

*=======

A(ADORESS)========

:-tAXQX- - - - - - '

QIDATA OUT)

PREVIOUS DATA VALID

DATA VALID

------~------------~I~~~yl

~Ic~-------~VQV---------.I

MOTOROLA MEMORY DATA
5-110

MCM6249

READ CYCLE 2 (See Note)
J

tAVAV

l.

A (ADDRESS)
~ tELQV

-;f

E(CHIP ENABLE)
-

tELQX-

G(OUTPUT ENABLE)
lGLOV... lGLQX ....
HIGH-Z

Q(DATAOUT)

r

tAVQV

---fo

------------

Xl'll:

tEHQZ

tGHQZ

DATA VALID
-tEHICCl

tELICCH

SUPPLY CURRENT ICC
ISB _ _ _ _ _ _ _ _---'l!

II

NOTE: Addresses valid prior to or coincident with E going low.

AC TEST LOADS

TIMING LIMITS
+5V

OUTPUT

~'r'_'---Zo-=-50-Q-~-(~"

480
Q

---<1-----+
5 pF
(INCLUDING
SCOPE AND JIG)

255

=
Figure 1A

Figure 18

MOTOROLA MEMORY DATA

5-111

The table of timing values shows either
a minimum or a maximum limit for each
parameter. Input requirements are specified from the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that much time (even though most
devices do not require it). On the other
hand, responses from the memory are
specified from the device point of view.
Thus, the access time is shown as a maximum since the device never provides data
later than that time.

MCM6249

WRITE CYCLE 1 (W Controlled, See Notes 1,2, and 7)
Symbol
Parameter

MCM6249-25

MCM6249-30

MCM6249-35

Standard

Alternate

Min

Max

Min

Max

Min

Unit

Notes

tAVAV

twc

25

30

35

-

ns

3

0

14

-

ns

-

ns

Address Setup Time

tAVWL

tAS

0

Address Valid to End of Write

tAVWH

tAW

20

twP

20

-

13

-

-

0

-

0

Write Cycle Time

Write Pulse Width

twLWH

Data Valid to End of Write

•

tOVWH

tow

12

Data Hold Time

tWHOX

tOH

0

Wrije Low to Data High-Z

0
25
25

Max

30
30

ns
ns
ns

twLOZ

twz

0

12

0

14

0

16

ns

4,5,6

Wirte High to Output Active

twHOX

tow

5

5

4,5,6

twR

0

-

ns

tWHAX

-

5

Write Recovery Time

-

0

0

ns

NOTES:
1. A write occurs during the overlap of E low and Iii low.
2. Productsensitivities to noise require proper grounding and decoupling of power supplies as well as minimization orelimination of bus contention
conditions during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured + 500 mV from steady-state voltage with load of Figure 1.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLOZ < twHOX min both for a given device and from device to device.
7. If G goes low coincident with or after Iii goes low, the output will remain in a high impedance state.

WRITE CYCLE 1 (W Controlled, See Notes 1, 2, and 7)
tAVAV
A (ADDRESS) ________

JI~

----------.1

__________________________________________

_JII~------

tAVWH ---------!~--!* twHAX

E(CHIP ENABLE)
~------twLWH-----~

twLEH

--------~:!...-------

W(WRITE ENABLE)

1+---- tDVWH---~--l""
DATA VALID

HIGH·Z

Q (DATA OUT)--------!.~::....------<

MOTOROLA MEMORY DATA
5-112

MCM6249

WRITE CYCLE 2 (I: Controlled, See Notes 1, 2, and 6)
MCM&249-25

MCM&2249-30

MCM&2249-35

Standard

Symbol
Alternate

MIn

Max

MIn

Max

MIn

Max

UnIt

Notes

Write Cycle Time

tAVAV

twc

25

30

-

35

3

tAVEL

tAS

0

0

-

0

-

ns

Address Setup Time
Address Valid to End of Write

tAVEH

tAW

20

25

-

ns

tELEH

tcp

20

30

-

ns

Enable to End of Write

tELWH

tcw

20

25

-

30

Enable Pulse Width

-

30

-

ns

Write Pulse Width

twLEH

twp

20

-

25

-

30

-

ns

tow

12

-

13

-

14

-

ns

tOH

0

-

0

-

0

-

ns

-

0

-

0

-

Parameter

Data Valid to End of Write

tOVEH

Data Hold Time

tEHOX

Write Recovery Time

tEHAX

25

ns

4,5

ns
twR
NOTES:
1. A write occurs during the overlap of E low and Vii low.
2. Productsensitivities to noise require proper grounding and decoupling of powersupplies as well as minimization or elimination of bus contention
conditions during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. If E goes low coincident wijh or aiter Vii goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before Vii goes high, the output will remain in a high impedance condition.
6. If G g09S low coincident wijh or aiter Vii goes low, the output will remain in a high impedance state.
0

WRITE CYCLE 2 (I: Controlled, See Notes 1, 2, and 6)
tAVAV
A (AOORESS)
tAVEH

14--

tELEH-

E(CHIP ENABLE)
tAVEL

!ELWH

tEHAX

W(WRITE ENABLE)
tOVEH-

o(OATAIN)

xxxxxxxxxxxxxxxxxxxxxxxXXXXXt

OATA VAllO

~XXXX

---I '~ !EHOX

Q(OATAOUT) _ _ _ _ _ _ _ _ _ _ _ _ _ _-.:.:H"'IG.,.H.....
Z _ _ _ _ _ _ _ _ _ _ _ _ _ __

ORDERING INFORMATION
(Order by Full Part Number)
MCM

"~•• "------=r

TTTT
6249

XX

xx

XX

Part N u m b e r - - - - - - -....

"'.......... ,'" -

T. . . . - . " ". . . . . .

Speed (25 = 25 ns, 30 = 30 ns, 35 = 35 ns)

Package (W = 400 mil, J = SOJ)
Full Part Numbers -

MCM6249WJ25
MCM6249WJ30
MCM6249WJ35

MOTOROLA MEMORY DATA
5-113

II

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL
DATA

------------MCM6264

8K X 8 Bit Fast Static RAM

•

The MCM6264 is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is available in plastic dual-in-line and plastic small-oulline J-Ieaded packages.
• Single 5 V ±1 0% Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• Fast Access TImes: 15, 20, 25 and 35 ns
• Equal Address and Chip Enable Access Times
• Output Enable (<3) Feature for Increased System Flexibility and to Eliminate
Bus Contention Problems
• Low Power Operation: 110 -140 mA Maximum ac
• Fully TTL-Compatible - Three-State Output

~,

300·MIL PLASTIC
CASE 710B-01

~'PACKAGE

3OO·MILSOJ
CASE 810B·03

PIN ASSIGNMENT

NC

BLOCK DIAGRAM

A3

E2

AS

AS

Vce

AS

A9

VSS

A4

All

A4

A7

ROW
DECODER

W

A7

A2

AS

VCC

A12

MEMORY MATRIX
2S6ROWSx
'32 x aOOi.UMN$

AS
A9-,-,.....-,

A1--1...c--.

A3

G

A2

Al0

Al

8

AO

007

000

DOS

001

DOS

002

004

VSS

003

COLUMN 1/0
COLUMN DECODER

AO

Al

AS Al0 A12

MOTOROLA MEMORY DATA

5·114

PIN NAMES
AO-A12 .............. Address Input
000-007 ". Data InpuVData Output
W " .. ,.,.,.'"'''''''' Write Enable
G ' .. " " " , .. , .. ,',. Output Enable
8, E2 ................. Chip Enable
NC ............... , .. No Connection
VCC ..... , .... Power Supply (+ S V)
VSS ................ ' .... " Ground

MCM6264

TRUTH TABLE (X = don't care)
E1

E2

H

X

X

L

L

H

L

H

L

H

W

Mode

VCC Current

Output

X

X

Not Selected

ISB1,ISB2

High-Z

-

X

X

Not Selected

ISB1,ISB2

High-Z

-

H

H

Output Disabled

ICCA

High-Z

-

L

H

Read

ICCA

Dout

Read Cycle

X

L

Write

ICCA

High-Z

Write Cycle

G

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
lields; however, it is advised that
normal precautions be taken to
avoid application 01 any voltage
higher than maximum rated voltages to this high-impedance circuil.

Cycle

This CMOS memory circuit has
been designed to meet the dc and
ac specifications shown in the
tables, after thermal equilibrium has
been established. The circutt is in a
test socket or mounted on a printed
circuit board and transverse air flow
of at least 500 linear leet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS
Rating

Unit

Symbol

Value

VCC

- 0.5 to + 7.0 V

V

Yin, Vout

-0.5toVCC
+0.5

V

Output Current (per VOl

lout

±30

rnA

Power Dissipation

Po

1.0

W

Temperature Under Bias

Tbias

-10to+85

'c

Operating Temperature

TA

oto +70

'C

Power Supply Voltage Relative to VSS
Voltage Relative to VSS For Any Pin
ExceptVcc

Storage Temperature-Plastic

-55to+ 125
'c
Tsta
NOTE: Permanent devIce damage may occur II ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages lor extended
periods 01 time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%, TA =0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC + 0.3"

V

- OS"

-

0.8

V

Parameter

Input Low Voltage

Vil
"VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse WIdth S 20 ns)
"VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width S 20 ns)

DC CHARACTERISTICS
Parameter

Symbol

=0 to VCC)
Output leakage Current (E =VIH or G =VIH, Vout =0 to VCC)
Output Low Voltage (IOl =8.0 rnA)
Output High Voltage (IOH =- 4.0 rnA)
Input leakage Current (All inputs, Yin

Min

-

IlkaCil
Ilkg(OL

Max

Unit

±1
±1

IIA
IIA

VOL

-

0.4

V

VOH

2.4

-

V

POWER SUPPLY CURRENTS
Parameter
AC Active Supply Current (lout =0 rnA, VCC

=Max, I =Imax)
AC Standby Current (E =VIH or E2 =VIL, VCC =Max, I =Imax)

Standby Current (El ;, VCC - 0.2 V or E2 S VSS + 0.2 V,
Yin SVSS +0.2 V, or ;'VCC -0.2V)

Symbol

-15

-20

-25

-35

Unit

ICCA

140

130

120

110

rnA

ISBI

40

35

30

30

rnA

ISB2

20

20

20

20

rnA

MOTOROLA MEMORY DATA

5-115

MCM6264

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25'C, Periodically sampled rather than 100% tested)
Symbol

Max

Unit

Address and Data Input Capacitance

Cin

6

pF

Control Pin Input Capacitance (E, E2 G", W)

Cin

6

pF

Cout

7

pF

Characteristic

Output CapaCitance

AC OPERATING CONDITIONS AND CHARACTERISTICS
,(Vee = 5 V ± 10%, TA = 0 to + 70 o e, Unless Otherwise Noted)

Input liming Measurement Reference Level ...... .. 1.5 V
Input Pulse Levels ............................ 0 to 3 V
Input Rise/Fall lime .............................. 5 ns

Output liming Measurement Reference Level. . . . . .. 1.5 V
Output Load .......... Figure lA Unless Otherwise Noted

READ CYCLE (See Notes 1 and 2)

•

-20

-15

Symbol
Parameter

Min

Max

Unit

Notes

-

35

ns

3

25

-

35

ns

25

-

35

ns

10

-

12

ns

4

ns
ns

5,B,7

0

-

ns

5,6,7

Ait

Min

Max

Min

Max

Min

Read Cycle Time

IAVAV

tRC

15

-

20

25

Address Access Time

tAVQV

tAA

'15

Enable Access Time

tELQV

tACS

-

8

-

-

15

-35

-25

Std

20
20

Max

4

Output Enable Access Time

lGLQV

toE

-

Output Hold from Address Change

tAXQX

toH

4

-

4

Enable Low to Output Active

tELQX

ICLZ

4

-

4

-

4

Output Enable Low to Output Active

tGLQX

toLZ

0

-

0

-

0

-

Enable High to Output High-Z

tEHOZ

tcHZ

0

8

0

9

0

10

0

11

ns

5,6,7

Output Enable High to Output High-Z

lGHQZ

toHZ

0

7

0

8

0

9

0

10

ns

5,B,7

Power Up Time

tELICCH

tpu

0

0

-

0

-

0

-

ns

Power Down Time

tEHICCL

tpo

-

-

35

ns

15

-

20

-

11

25

4
4

-

NOTES:
1. Wis high for read cycle,
2, El and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low,
5. At any given voltage and temperature, tEHOZ max < tELOX min, and 'GHOZ max < tGLOX min, both for a given device and from device to
device.
6, Transition is measured ± 500 mV from steady-state voitage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8, Device is continuously selected (El = VIL, E2 = VIH, G = VILl.

MOTOROLA MEMORY DATA
5-116

MCM6264

READ CYCLE 1 (See Note 8)

..

tAVAV

A (ADDRESS)
- - tAXOX-

o(DATA OUT)

PREVIOUS DATA VALID

..

tAVQV

.
A (ADDRESS)

DATA VALID

----------1

READ CYCLE 2

(See Note 4)

tAVAV

\V

V
~

~

•
1\

E (CHIP ENABLE)

•

tELOV

II.... tEHOZ.... tGHOZ-

!+tELOX'"
..tGLOX'"

G (OUTPUT ENABLE)

1\
IGLOV--

KX>O--I

A5--~~_I

VCC

AI2

MEMORY MATRIX
25SROWSx
32 x 8 COLUMNS

A8 ----1Iz.--1

A3

G

A2

AIO

AI

8

AO

D07

DOO

DOS

A9 ----1Iz.--1

DOl

D05

AI--~~_I

D02

DQ4

VSS

D03

COLUMN VO
PIN NAMES

COLUMN DECODER

8-~'----"'"

E2

AO

AI

AS AIO AI2

W

G----.

MOTOROLA MEMORY DATA

5-122

MCM6264C

t:

READ CYCLE 1 (See Note 8)

l~J____

tAVAV

A (ADDRESS) _ _ _ _

-t-AX-Q-X----.-,--------------~

Q (DATA OUT)

PREVIOUS DATA VALID

DATA VALID

1 + - - - - - - - tAVQV

READ CYCLE 2 (See Note 4)
tAVAV

V
/\

A (ADDRESS)

\
/

II

tELQV

V

\

E(CHIP ENABLE)

1\

/f.-tEHQZ"

\~ tELQX-

G(OUTPUT ENABLE)

V

1\

/

HIGHZ

Q(DATAOUn

KXXXX)(

tAVQV

"",,"U,,:'Ii ':

,

f.-lGHOZ"

lGLQV!--tGLQX -

DATA VALID

I--

HIGHZ

/

-------------p------------------=t
tELICCH - -

AC TEST LOADS

~

+5V

ZOo 50Q
Q

255 Q

Figure 1A

480Q

5pF
(INCLUDING
SCOPE AND JIG)

TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external
system point of view. Thus, address setup time is
shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand,
responses from the memory are specified from
the device point of view. Thus, the access time is
shown as a maximum since the device never provides data later than that time.

Figure 18

MOTOROLA MEMORY DATA
5-123

tEHICCL

MCM6264C

WRITE CYCLE 1

(Iii Controlled. See Notes 1. 2. and 3)
Symbol

Parameter

•

-12

Std.

All.

Min

Write Cycle TIme

tAVAV

twc

12

Address Setup TIme

tAVWL

tAS

a

Address Valid to End of Write

tAVWH

tAW

Write Pulse Width

twLWH.
twLEH

twP

Write Pulse Width.
GHigh

twLWH.
tWLEH

Data Valid to End of Write
Data Hold TIme

-15

-20

-35

-25

Min

Max

Min

Unit

Notes

15

-

20

-

25

-

35

-

ns

4

a

-

a

-

15

17

ns

-

12

15

-

17

-

20

10

-

-

ns

12

-

a

10

-

20

-

ns

twP

8

-

10

-

12

-

15

-

17

-

ns

tDVWH

tDW

6

-

8

-

10

-

12

0

0

-

-

a

twLOZ

twz

a

6

a

7

8

a
a

-

Write Low to Output High-Z

a
a

-

ns

tDH

-

7

twHDX

10

0

12

ns

6.7.8

Write High to Output Active

twHOX

tow

4

4

-

4

-

4

-

ns

6.7.8

twl-lAX

twR

a

-

4

Write Recovery TIme

-

a

-

0

-

a

-

ns

Max

Min

Max

WRITE CYCLE 2

Max

a

a

Max

Min

Max

Min

Max

5

ns

(E Controlled. See Notes 1 and 2)
Symbol

Parameter

·12

·15

·20

·25

·35

Std.

Alt.

Min

Max

Min

Max

Min

Max

Min

Unit

Notes

Write Cycle TIme

tAVAV

twc

12

15

-

35

-

ns

4

tAS

a

a

tAW

12

12

15

20

25

ns

Enable to End of Write

tELEH.
tELWH

tcw

10

-

10

-

12

-

15

-

25

-

ns

tAVEH

-

a

Address Valid to End of Write

-

25

tAVEL

-

20

Address Setup TIme

-

Data Valid to End of Write

tDVEH

tDW

7

-

-

10

-

15

-

ns

tEHDX

tDH

a
a

-

-

8

Data Hold TIme

0

-

0

-

a
a

-

ns

-

a

7

a
a

a

-

ns

9.10

ns
a
a
tEI-iAX
twR
NOTES: 1. A write occurs during the overlap of E low and W low.
2 Ef and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. If G goes low coincident with or after Iii goes low. the output will remain in a high impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. If G" VIH. the output will remain in a high impedance state.
6. At any given voltage and temperature. twLOZ max is less than tWHOX min. both for a given device and from device to device.
7. Transition is measured ±sao mV from steady-state voltage with load of Figure 1B.
8. This parameter is sampled and not 100% tested.
9. If E goes low coincident with or after Iii goes low. the output will remain in a high impedance state.
10. If E goes high coincident wijh or before Iii goes high. the output will remain in a high impedance state.
Write Recovery TIme

MOTOROLA MEMORY DATA
5-124

MCM&264C

WRITE CYCLE 1 (W Controlled, See Notes 1, 2 and 3)
tAVAV

--------~

A (ADDRESS)

1 4 - - - - - - - tAVWH - - - - - - - < . - + / - tWHAX

E(CHIP ENABLE)

__-+_____,

1-01----

twLWH
twLEH

iN (WRITE ENABLE)
tDVWH
D (DATA IN)

----0\+--1-

DATA VALID

HIGHZ

Q (DATA OUT) ----"';;;.;.;.;;'-----{

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
tAVAV

---------~~

A (ADDRESS)
tAVEH --------~

E(CHIP ENABLE)

----------+----------------__

r---+-------

--_01+--_0+- tEHAX

iN (WRITE ENABLE)

D (DATA IN)

Q (DATA OUT) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-"H~IG::::H.:..:Z=___ _ _ _ _ _ _ _ _ _ _ _ _ _ __

ORDERING INFORMATION (Order by Full Part Number)
MCM
Motorola Memory Prefix
Part Number

~

T TL=:
6264C

X

XX

XX

Shipping Method (R2 = Tape & Reel, Blank = Rails)
Speed (12 = 12 ns, 15 = 15 ns, 20 = 20 ns,
25 = 25 ns, 35 = 35 ns)

Package (P = 300 mil Plastic DIP, J = 300 mil SOJ)
Full Part Numbers-MCM6264CP12
MCM6264CP15
MCM6264CP20
MCM6264CP25
MCM6264CP35

MCM6264CJ12
MCM6264CJ15
MCM6264CJ20
MCM6264CJ25
MCM6264CJ35

MOTOROLA MEMORY DATA
5-125

MCM6264CJ12R2
MCM6264CJ15R2
MCM6264CJ20R2
MCM6264CJ25R2
MCM6264CJ35R2

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM6265
8K X 9 Bit Fast Static RAM

•

~,

The MCM6265 is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing strobes. while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout. and is available in plastic dual-in-line and plastic small-outline J-Ieaded packages.
• Single 5 V ±IO% Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• Fast Access Times: 15.20. 25 and 35 ns
• Equal Address and Chip Enable Access TImes
• Output Enable (G) Feature for Increased System Flexibility and to Eliminate
Bus Contention Problems
• Low Power Operation: 110-140 mA Maximum ac
• Fully TIL-Compatible - Three-State Output

300-MIL PLASTIC
CASE 710B-Ol

~PACKAGE

300-MILSOJ
CASE 8108-03

PIN ASSIGNMENT

,:
BLOCK DIAGRAM

A2--fr.:-r-i

',;'

VCC

A3--I2-::l

vis

A4--{~---1

AS -----t2--;

ROW
A 7 - - i 2 - l DECODER

MEMORY MATRIX
256 ROWS. x
.,3ax9COtUMNS

A9 -----tI2--I

AS

VCC

A7

W

A6

E2

AS

A9

A4

Al0

A3

All

A2

G

AI

A12

AO

8
DOS

000
Al0--i2-l
All--i2-l

COLUMN I/O

001

007

002

DOS

003

005

VSS

DQ4

COLUMN DECODER
PIN NAMES

E2

AO

AI

A6

AS A12

MOTOROLA MEMORY DATA
5-126

AO-A 12 .............. Address Input
DOO-DOS ... Data InpuVData Output
W ..................... Write Enable
G ................... OUlput Enable
8. E2 ................. Chip Enable
VCC .. .. .. . . .. Power Supply (+ 5 V)
VSS ....................... Ground

MCM6266

TRUTH TABLE (X = don't care)
El

E2

G

W

Mode

VCCCurrent

Output

Cycle

H

X

X

X

Not Selected

IS81,IS82

High-Z

-

X

L

X

X

Not Selected

IS81,IS82

High-Z

L

H

H

H

Output Disabled

ICCA

High-Z

L

H

L

H

Read

ICCA

Dout

Read Cycle

L

H

X

L

Write

ICCA

High-Z

Write Cycle

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
lields; however, it is advised that
normal precautions be taken to
avoid application 01 any voltage
higher than maximum rated voltages to this high-impedance circuit.
This CMOS memory circuit has
been designed to meet the dc and
ac specilications shown in the
tables, after thermal equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse air Ilow
01 at least SOO linear leet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS
Rating

Symbol

Value

Unit

VCC

-0.5 to + 7.0 V

V

Yin, VOU!

-0.510 VCC
+0.5

V

Oulput Current

lout

±20

rnA

Power Dissipation

Po

1.0

W

Temperature Under Bias

Tbias

-1010+85

°C

Operating Temperature

TA

Oto +70

°C

Power Supply Voltage
Voltage Relative to VSS For Any Pin
ExceptVCC

-55to+ 125
Storage Temperature - Plastic
°C
Tslo
NOTE. Permanent device damage may occur II ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages lor extended
periods 01 time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70 c e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC + 0.3'

V

-0.5"

-

0.8

V

Parameter

Input Low Voltage
VIL
·vIH (max) vcc + U.;i vac; IH (max) - vcc + ".u v ac IPU se wlatn" "u ns}
"VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 Vac (pulse width" 20 ns)

DC CHARACTERISTICS
Parameter

Min

Symbol

= 0 to VCC)
Oulput Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC)
Output Low Voltage (lOL = 8.0 rnA)
Input Leakage Current (All Inputs, Yin

-

IlkaCil
IlkalO)

Output High Voltage (IOH = - 4.0 rnA)

Max

Unit

±1
±1

I-IA
I-IA

VOL

-

0.4

V

VOl-!

2.4

-

V

POWER SUPPLY CURRENTS
Symbol

-15

-20

·25

·35

Unit

AC Active Supply Current (lout = 0 rnA, VCC = Max, 1= Imax)

ICCA

140

130

100

110

rnA

AC Standby Current (El = VIH or E2 = VIL, VCC = Max, I = Imax)

IS81

40

35

30

30

rnA

IS82

20

20

20

20

rnA

Parameter

Standby Current (El 2: VCC - 0.2 V or E2" VSS + 0.2 V,
Yin "VSS + 0.2 V, or "VCC-0.2 V)

MOTOROLA MEMORY DATA
5-127

MCM6266

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25"C, Periodically sampled rather than 100% tested)
Symbol

M8l1

Unit

Address and Data Input Capacitance

Cin

6

pF

Control Pin Input Capacitance (El, E2, G, W)

Cin

6

pF

Output Capacitance

Cout

7

pF

Characteristic

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10%, TA = 0 to + 70 oe, Unless Otherwise Noted)
Input liming Measurement Reference Level ........ 1.5 V
Input Pulse Levels ............................ 0 to 3 V
Input Rise/Falilime .............................. 5 ns

Output liming Measurement Reference Level. . . . . .. 1.5 V
Output Load .......... Figure lA Unless Otherwi~e Noted

READ CYCLE (See Notes 1 and 2)
-12

Symbol
Parameter

-15

-25

Std

All

Min

Max

Min

Read Cycle lime

tAVAV

tRC

15

20

-

25

Address Access lime

tAVOV

tAA

tELOV

tACS

15

-

20

Enable Access lime

-

8

-

15

Max

Min

-35
Min

Max

Unit

Notes

-

35

nil

3

25

ns

35

ns

10

-

12

-

35

20

-

12

ns

-

4

-

ns
ns

5,6,7

ns

5,6,7

Output Enable Access lime

tGLOV

toE

-

Output Hold from Address Change

tAXOX

toH

4

-

4

tELOX

tcLZ

4

-

4

Enable Low to Output Active

4

4

Output Enable Low to Output Active

'GLOX

toLZ

0

-

0

-

Enable High to Output High-Z

tEHOZ

tCHZ

0

8

0

Output Enable High to Output High-Z

'GHOZ

toHZ

0

7

Power Up lime

tELICCH

tpu

0

Power Down lime

tEHICCL

tpD

-

Max

25

4

4

0

-

0

-

9

0

10

0

11

ns

5,6,7

0

8

0

10

0

10

ns

5,6,7

-

0

-

0

-

0

-

ns

15

-

20

-

25

35

ns

-

NOTES:
1. Wis high for read cycle.
2. Ef and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. All timings are referenced from the last valid address to the firsttransitioning address.
4. Addresses valid prior to or coincident with E going low.
5. At any given voltage and temperature, tEHQZ max < tELQX min, and 'GHQZ max < tGLQX min, both for a given device and from device to
device.
6. TransHion is measured ± 500 mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (Ef = VIL, E2 = VIH, G = VIL)'

MOTOROLA MEMORY DATA
5-128

MCM6265

READ CYCLE 1 (See Note 8)
lAVAV
A (ADDRESS)
lAXQXQ(DATAOUT)

PREVIOUS DATA VALID

DATA VALID
lAVQV

----------<... 1

READ CYCLE 2 (See Note 4)

•

lAVAV

A(ADDRESS)

•
1\

E (CHIP ENABLE)

•

lElQV

~
_lEHOZ .....

_lGHQZ .....

j.-lElQX+
_lGlQX+

G (OUTPUT ENABLE)

1\
lGlQV-

~Xx:;:xx

Q(DATAOUT)
lELICCH ~

VCC
SUPPLY CURRENT

DATA VALID

1\

•

lAVQV

---------- /
I SB

ICC

-

--

IELICCl-

\ '-

AC TEST LOADS
480

OUTPUT

n

ZO=50n
Q

255

n

5pF
(INCLUDING
SCOPE AND JIG)

VL=I.5V

Figure 1A

Figure 18

TIMING PARAMETER ABBREVIATIONS

signal name from which interval is defined
transition direction for first signal
signal name to which interval is defined
transition direction for second signal

I

t X X X X
I

I I

The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)

TIMING LIMITS

The table of timing values shows either a minimum or a maximum
limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a
minimum since the system must supply at least that much time (even
though most devices do not require it). On the other hand, responses
from the memory are specified from the device point of view. Thus, the
access time is shown as a maximum since the device output will be
valid no later than that time.

MOTOROLA MEMORY DATA
5-129

MCM6265

WRITE CYCLE

(W Controlled) (See Notes I, 2, and 3)
Symbol
Parameter

III

-15

-20

Std

Alt

Min

Max

Min

Write Cycle Time

tAVAV

twe

15

20

Address Setup Time

tAVWL

tAS

0

-35

-25

Max

Min

Max

Min

Max

Unit

Notes

35

-

ns

4

-

ns

20

-

ns

Address Valid to End of Write

tAVWH

tAW

12

Write Pulse Width

twLWH,
tWLEH

twp

12

-

Write Pulse Width, High
(Output Enable devices)

twLWH,
twLEH

twp

10

-

12

Data Valid to End of Write

tOVWH

tow

7

-

8

-

12

tOH

0

-

0

0

-

0

-

ns

twHOX

-

10

Data Hold Time
Write Low to Output High-Z

tWLQZ

twz

0

7

0

8

0

10

0

12

ns

6,7,8

Write High to Output Active

twHOX

tow

4

4

4

6,7,8

twR

0

-

ns

twHAX

-

4

Write Recovery Time

-

0
15
15

-

25

-

17

-

15

-

17

0
17

0
20

-

0

Min

Max

Min
25

-

35

0

0
25

15

-

0

0

ns
ns
5

ns

ns

WRITE CYCLE (E Controlled) (See Notes 1 and 2)
Symbol
Parameter

-15

-20

Max

-25

-35

Std

Alt

Min

Write Cycle Time

tAVAV

twe

15

-

20

Address Setup Time

tAVEL

tAS

0

-

0

Address Valid to End of Write

tAVEH

tAW

12

tELEH,
tELWH

lew

10

-

15

Enable to End of Write

12

-

Data Valid to End of Write

tOVEH

tow

7

-

8

-

10

-

15

Data Hold Time

tEHOX

tOH

0

0

-

tEHAX

twR

0

-

0

Write Recovery Time

-

0

-

0

20

Max

Max

Unit

Notes

-

ns

4

-

ns

0
0

-

ns

Min

25

NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. E1 and E2 are represented by E in this data sheet. E2 is of oppos~e polarity to E.
3. If G goes low coincident with or after Wgoes low, the output will remain in a high-impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. If G" V'H, the output will remain in a high-impedance state.
6. At any given voltage and temperature, twLQZ max < twHQX min, both for a given device and from device to device.
7. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
8. This parameter is sampled and not 100% tested.
9. If E goes low coincident with or after Wgoes low, the output will remain in a high-impedance state.
1O.lf E goes high coincident with or before Wgoes high, the output will remain in a high-impedance state.

MOTOROLA MEMORY DATA
5-130

ns
ns
ns

ns

9,10

MCM6266

WRITE CYCLE 1 (See Notes 1 , 2, and 3)

•

tAVAV
A (ADDRESS)

1 - - - - - - - - tAVWH

--------14-<..1-

tWHAX

E (CHIP ENABLE)

iii (WRITE ENABLE)
tOVWH - 1 - - - - 1 ' - tWHOX

o(DATA IN)

DATA VALID

HIGHZ

Q(OATAOUT) - - - - - - - {

II

WRITE CYCLE 2 (See Notes 1 and 2)

•

•

1AVAV

A (ADDRESS)
tAVEH

E (CHIP ENABLE)
-tAVEL-1\
I + - - t E L E H _ .tEHAX+
lELWH

Vi

I

(WRITE ENABLE)

o(DATA IN)

xxxxxxxxxxxxxxxxxf

lOVEHDATA VALID

==mxxx
IEHOX

HIGH-Z
Q(OATAOUT) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

ORDERING INFORMATION (Order by Full Part Number)

-=-- T TL-=:
MCM

Motorola Memory Prefix
Part Number

6265

X

XX

XX

Shipping Method (R2 = Tape & Reel, Blank = Rails)
Speed (15 = 15 ns, 20 = 20 ns, 25 = 25 ns)

Package (P = 300-mil Plastic DIP, NJ = 300-mil SOJ)
Full Part Numbers-MCM6265P15
MCM6265P20
MCM6265P25

MCM6265NJ15
MCM6265NJ20
MCM6265NJ25

MOTOROLA MEMORY DATA
5-131

MCM6265NJ15R2
MCM6265NJ20R2
MCM6265NJ25R2

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM6265C

Advance Information
8K x 9 Bit Fast Static RAM

•

The MCM6265C is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is available in plastic dual-in-line and plastic small-outline J-Ieaded packages.
• Single 5 V ±1 0% Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• Fast Access Times: 12, 15, 20, 25, and 35 ns
• Equal Address and Chip Enable Access Times
• Output Enable (G) Feature for Increased System Flexibility and to Eliminate
Bus Contention Problems
• Low Power Operation: 110 -150 mA Maximum ac
• Fully TTL Compatible - Three State Output
BLOCK DIAGRAM
A2
VCC

A3

VSS
A4--~..o--1

-

Tl

DQ3~.J..ll-' .....--'--'

g(MCM6268) }
S(MCM6269)

MOTOROLA MEMORY DATA
5-138

AO-A 11 ............... Address Inputs
W ...................... Write Enable
E (MCM6268) . . . . . . . . . . .. Chip Enable
5 (MCM6269) ...........•. Chip Select
DQO-OQ3 ... . . . .. Data Inputs/Outputs
VCC .............. + 5 V Power Supply
VSS ......................... Ground

MCM6268-MCM6269

TRUTH TABLE
VCC Current
(MCM6268)

ElS

Vi

Mode

H

X

Not Selected

L

H

Read

L

L

Write

VCC Current
(MCM6269)

I/O Pin

ISB1,ISB2

ICC

High-Z

ICC

ICC

Dout

Read Cycle

ICC

ICC

Din

Write Cycle

Cycle

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application 01 any voltage
higherthan maximum rated voltages
to this high-impedance circuit.

-

ABSOLUTE MAXIMUM RATINGS (See NOle)
Rating

Symbol

Value

VCC

- 0.5 to 7.0

V

Vin, Vout

- 0.5 to VCC + 0.5

V

lout

± 20

rnA

PD

1.0

W

Temperature Under Bias

Tbias

-10to+B5

°c

Operating Temperature

TA

Oto+ 70

°c

Power Supply Voltage
Voltage Relative to V~
For Any Pin Excep CC
Output Current (per I/O)
Power Dissipation (TA

= 25°C)

Unit

•

Storage Temperature

-55to+125
°c
Tsta
NOTE: Permanent devIce damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods 01
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%, TA = 0 to 70 o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.0

VCC +0.3

V

VIL

-0.5·

O.B

V

.

Input Low Voltage

-

VIL (mIn) = - 0.5 V dc; VIL (mIn) = - 3.0 V ac (pulse wIdth,; 20 ns)

DC CHARACTERISTICS
Parameter

=0 to VCe)
Output Leakage Current (E or S =VIH, Vout =0 to VCC)
AC Supply Current (lout =0 rnA)

Symbol

Input Leakage Current (All Inputs, Yin

Ilka(l)
Ilka(O)
MCM6268/69-20, 25, 35

ICC

MCM6268-45, 55

=VIH, No Restrictions on Other Inputs) (MCM626B)

ISB1

CMOS Standby Current (E;, VCC - 0.2 V, No Restrictions on Other Inputs)

ISB2

TTL Standby Current (E

MCM6268-20, 25, 35

Output Low Voltage (IOL

=B.O rnA)
=- 4.0 rnA)

CAPACITANCE (I

IlA
IlA

110

rnA

-

BO

-

20

-

15

rnA
rnA

2
15

VOL

-

0.4

V

VOH

2.4

-

V

=1.0 MHz, dV =3.0 V, T A =25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic

Input Capacitance

Unit

± 1.0
± 1.0

ISB

Output High Voltage (IOH

Max

-

-

MCM6268-45, 55
(s;'VCC-o.2V, Vin,;Q.2 V, or ;,Vcc-o.2V) (MCM6269)

Min

Symbol
All Inputs Except E, S

Cin

E,g
I/O Capacitance

CliO

MOTOROLA MEMORY DATA
5-139

Min

-

-

Typ

Max

Unit

4

pF

5

6
7

5

7

pF

MCM6268·MCM6269

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Reference Level ........................... 1.5 V
Input Pulse Levels. . . . . . . .. . .. .. . . . . . . . . . . . .. 0 to 3.0 V
Input Rise/Fall Time .............................. 5 ns

Output Reference Level .......................... 1.5 V
Output Load .......... Figure 1A Unless Otherwise Noted

READ CYCLE (See Note 1)
MCM6268P20 MCM6268P25 MCM6268P35
MCM6268P45 MCM6268P55
MCM6269P20 MCM6269P25 MCM6269P35
Standard Alternate Min
Max
Min
Max
Min
Max Unit
Max
Min
Max
Min
20
25
45
55
ns
35
tAVAV
tRC
20
25
45
50
ns
35
tAVOV
tAA
45
ns
20
25
35
55
tELOV
tACS
Symbol

Parameter
Read Cycle Time
Address Access Time
Enable Access Time
(MCM6268)
Select Access Time
10
12
15
ns
tSLQV
tACS
(MCM6269)
5
5
5
Output Hold from Address
5
ns
5
tAXOX
toH
Change
Enable Low to Output
10
10
5
5
5
ns
tLZ
tELOX
Active
Select Low to Output
5
ns
5
5
tLZ
tSLQX
Active (MCM6269)
Enable High to Output
20
ns
a
a
10
a
15
0
15
0
8
tHZ
tEHOZ
High-Z
Select High to Output
ns
a
8
a
10
0
15
tHZ
tSHOZ
High-Z (MCM6269)
Power Up Time
0
0
ns
a
0
0
tpu
tELICCH
(MCM6268)
Power Down Time
20
20
30
45
55
ns
tpD
tEHICCL
(MCM6268)
NOTES:
1. Wis high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transitioning address.
3. At any given voltage and temperature, tEHOZ (or tSHOl) max, is less than tELOX (or tsLOX) min, both for a given device and from device to
device.
4. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. Device is continuously selected (E or S = ~Ll. _
7. Addresses valid prior to or coincident with Ear S going low.

-

•

-

-

-

-

Notes
2

-

3,4,5

-

READ CYCLE 1 (See Note 6 Above)

A (ADDRESS) ______

~------------------ ~VQV--------------------~J
~r--~"~

__________________________________

-tAXQX
Q(DATAOUT)

A

JI~

_ _ _ ___

.1

*x> v oc; Vil (min) - - ~.U v ac (pUlse wlotn ,; ~u ns)
""VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width';; 20 ns)

DC CHARACTERISTICS
Parameter

Symbol

= 0 to VCC)
Output leakage Current (E = VIH or G = VIH, Vout = 0 to VCC)
CMOS Standby Current (VCC = Max, f = 0 MHz, E" VCC - 0.2V"
Input leakage Current (All Inputs, Yin

Max

Unit

Ilko(l)

Min

-

±1.0

IlkQ(O)

-

±1.0

I!A
I!A
I!A

-

Yin ';;VSS + 0.2 V, or "VCC -0.2 V)

15

ISB2

= 8.0 mAl
Output High Voltage (IOH =- 4.0 mAl
Output low Voltage (IOl

VOL

-

0.4

V

VOH

2.4

-

V

POWER SUPPLY CURRENTS
Parameter
AC Active Supply Current (lout = 0 mA, VCC

= Max, f = fmax)
AC Standby Current (E = VIH, VCC = MAX, f =f max)

Symbol

·12

·15

·20

·25

·35

Unit

ICCA

150

140

130

120

110

mA

ISB1

45

40

35

30

30

mA

"For deVices with muiliple chip enables of opposite polanty,Ef" VCC - 0.2 V or E2,;; VSS + 0.2 V

MOTOROLA MEMORY DATA
5-151

MCM62B7

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25·C, Periodically sampled rather than 100% tested)
Characteristic

Symbol

Max·

Unit

Address and Data Input Capacitance

Cin

6

pF

Control Pin Input Capacitance (E,W)

Cin

6

pF

Cout

7

pF

Output Capacitance

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee ~ 5 V ± 10 %, T A - 0 to + 70·e, Unless Otherwise Noted)
Input liming Measurement Reference Level ........ 1.5 V
Input Pulse Levels ............................ 0 to 3 V
Input Rise/Falllime .............................. 5 ns
-12

Symbol

•

Parameter

Output liming Measurement Reference Level. . . . . .. 1.5 V
Output Load •......... Figure lA Unless Otherwise Noted

-20

-15

Std

All

Min

Max

Min

Read Cycle TIme

IAVAV

tRC

12

15

Address Access TIme

IAVOV

tM

-

12

Enable Access TIme

tELOV

lACS

-

Output Hold from Address Change

tAXOX

toH

4

-35

-25

Min

Max

Min

Max

Min

Max

-

20

25

-

35

-

ns

15

20

35

ns

15

-

25

12

-

-

-

-

4

-

4

4

Max

20

25

-

Unit Notes

35

ns
ns

2
3

Enable Low to Output Active

tELQX

ICLZ

4

-

4

-

4

-

4

-

4

-

ns

4,5,6

Enable High to Output High-Z

tEHQZ

tcHZ

0

6

0

8

0

9

0

10

0

15

ns

4,5,6

Power Up TIme

tELICCH

IpU

0

0

-

0

-

0

-

0

-

ns

Power Down TIme

tEHICCL

IpO

-

-

.35

ns

12

-

15

-

20

-

25

NOTES:
1. is high for read cycle.
2. All timings are referenced from the last valid eddress to the firsl transitioning address.
3. Addresses valid prior to or coincident with E going low.
4. At any given voltage and temperature, tEHQZ max < tELQX min for a given device and from device to device.
5. TransUion is measured ± 500 mV from steady-state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected E s VIL'

MOTOROLA MEMORY DATA
5-152

4

-

MCM6287

READ CYCLE 1 (See Note 7)
tAVAV
A(ADDRESS)
tAJ(QXQ(DATAOUT)

PREVIOUS DATA VALID

DATA VALID
tAVQV - - - - - - - -___ 1

READ CYCLE 2 (See Notes 2 and 4)

.
A(ADDRESS)

,

tAVAV

V
1\

•

•

tELQV

~tEHQZ--

t\

E (CHIP ENABLE)

f.-t ELQX'"

~X'IXiX~

Q(DATAOUT)

-

tELICCH

VCC

ICC

SUPPLY CURRENT

I SB

-------

DATA VALID

•

tAVQV

-

tELICCL-

/

\

~

AC TEST LOADS
OUTPUT

480

~¥-------1:L~
lo=50Q

Q

Q

RL=50Q

5pF
(INCLUDING
SCOPE AND JIG)

255Q

VL=I.73V

Figure 1A

Figure 18

TIMING PARAMETER ABBREVIATIONS

t X X X X

signal name from which Interval is defined
transition direction for first signal
signal name to which interval is defined
transition direction for second signal

I

III

The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)

TIMING LIMITS

The table of timing values shows either a minimum or a maximum
limitfor each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a
minimum since the system must supply at least that much time (even
though most devices do not require it). On the other hand, responses
from the memory are specified from the device point of view. Thus, the
access time is shown as a maximum since the device output will be
valid no later than that time.

MOTOROLA MEMORY DATA
5-153

MCM6287

WRITE CYCLE 1 (W Controlled) (See Notes I, 2 and 3)
Symbol
Parameter

-12

-15

-20

-25

Std

AH

Min

Max

Min

Max

Min

Max

Min

Write Cycle Time

'AVAV

twe

12
0

12

-

25

lAS

-

20

tAVWL

-

15

Address Setup Time
Address Valid to End of Write

tAVWH

tAW

10

Write Pulse Width

twLWH,
twLEH

twp

10

0
12

0
15
15

0
20
20

-35

Max Min Max Unit Notas

-

35
0
25
25

-

ns

-

ns

2

ns
ns

Data Valid to End of Write

tOVWH

tow

6

-

8

0

-

0

0

0

-

ns

0

-

15

tOH

-

10

twHOX

-

7

Data Hold Time
Write Low to Output High-Z

twLoz

twz

0

6

0

7

0

8

0

10

0

15

ns

3,4,5

Write High to Output Active

twHax

tow

4

4

-

ns

3,4,5

0

-

4

twR

-

4

twHAX

-

4

WrHe Recovery Time

-

0

0

0

0

ns

ns

WRITE CYCLE 2 (E Controlled) (See Notes 1 2 and 3)

•

Symbol

-12

-20

-15

Sid

All

Min

Max

Min

Max

Min

Writa Cycle Time

tAVAV

!we

12

15

-

20

Address Setup Time

tAVEL

tAS

0

-

0

-

0

12

-

Parameter

Address Valid to End of Write

tAVEH

tAW

10

Enable to End of Write

tELEH,
IELWH

lew

8

Data Valid to End of Write

toVEH

tow

6

Data Hold Time

tEHOX

toH

0

10
7

0

-35

-25
Min

Max

-

25

35

-

0

15

-

20

12

-

15

-

8

-

10

-

15

0

Max

0

Min

0
25
25

0

Max

-

WrHe Recovery Time
0
0
0
0
0
tEHAX
twR
NOTES:
1. A write occurs during the overiap of E low and Vii low.
2. All timings are referenced from the last valid address to the first transitioning address.
3. At any given voltage and temperature, twLOZ max < twHOX min, both for a given device and from device to device.
4. Transition is measured ± 500 mV from steady-state voltage wHh load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. If E goes low coincident wHh or aHer Vii goes low, the output will remain in a high-impedance state.
7. If E goes high coincident with or before Vii goes high, the output will remain in'a high-impedance state.

MOTOROLA MEMORY DATA
5-154

Unll Notes
ns

2

ns
ns
ns
ns
ns
ns

6,7

MCM6287

WRITE CYCLE 1 (See Nole 2)

.

tAVAV
A(ADDRESS)

1...·1-------- tAVWH - - - - - - -•• 1'..... -

tWHAX

E(CHIP ENABLE)

----1----"'"
Vi (WRITE ENABLE)

~-____

tWLWH _ _ _ _ _~'~1
tWLEH

r---------

I-o--~f---

o(DATA IN)

t WHDX

DATA VALID

HIGHZ

Q(DATAOUT) - - - - - - - {

•

WRITE CYCLE 2 (See Nole 2)

•

tAVAV

'I
\

A(ADDRESS)

•

tAVEH

E(CHIP ENABLE)

/
-tAVEL-1\
I - t E L E H _ - tEHAX~
tELWH

Vi (WRITE ENABLE)

V

D\1r
o(DATA IN)

t

DVEH

--

XXXXXXXXXXXXXXXXM.._DA_JA_VA_LlD_ _

t

~~

~XX

Q(DATAOUT) _ _ _ _ _ _ _ _ _ _ _ _.....;.H;;,:IG;;,,;H•.::.Z_ _ _ _ _ _ _ _ _ _ _ _ _ _ __

ORDERING INFORMATION (Order by Full Part Number)
MCM

Motorola Memory Prefix
Part Number

6287

-===r- T

T1.-=:
X

XX

XX

Shipping Method (R2 =Tape & Reel, Blank =Rails)
Speed (12 = 12 ns, 15 = 15 ns, 20 = 20 ns)

Package (P = 300·mil Plastic DIP, J = 300-mil SOJ)
Full Part Numbers-MCM6287P12
MCM6287P15
MCM6287P20
MCM6287BP25
MCM6287BP35

MCM6287J12
MCM6287J15
MCM6287J20
MCM6287BJ25
MCM6287BJ35

MOTOROLA MEMORY DATA
5-155

MCM6287J12R2
MCM6287J15R2
MCM6287J20R2
MCM6287BJ25R2
MCM6287BJ35R2

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM6288
16K x 4 Bit Fast Static RAM
The MCM6288 is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is available in plastic dual-in-line and plastic small-outline J-Ieaded packages.
• Single 5 V ± 10% Power Supply
• Fully Static - No Clock or liming Strobes Necessary
• Fast Access limes: 12 and 15 ns
• Equal Address and Chip Enable Access limes
• Low Power Operation: 140 - 150 mA Maximum ac
• Fully TTL-Compatible - Three-State Output

BLOCK DIAGRAM

---:'-VCC

Al ----,......::::1

-VSS

MEMORY MATRIX

-

PPACKAGE
3OO-MIL PDIP
CASE736A

PIN ASSIGNMENT
AO

VCC

Al

A13
A12

A3

All

A4

Al0

AS

A9

A6

DOO

A7

001

AS

D02

E

D03

Vi

VSS

128 ROWS x
lli!8 x 4 COLI:JMN$'

PIN NAMES
Ao-A13 ..........•... Address Input
DOo-DQ3 ... Data Input/Data Output
iN ..................... Write Enable
E ..................... Chip Enable
NC .................. No Connection
VCC .......... Power Supply (+ S V)
VSS ....................... Ground

COLUMN 1/0
COLUMN DECODER

A2

A3

A4

AS

A6

A7

AS

MOTOROLA MEMORY DATA
5-166

MCM6288

TRUTH
E
H
L
L

TABLE
Mode
Not Selected
Read
Write

W
X
H
L

Output
High-Z
Dout
High-Z

VCCCurrent
ISB1,ISB2
ICCA
ICCA

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
lields; however, it is advised that
normal precautions be taken to
avoid application 01 any voltage
higher than maximum rated voltages to this high-impedance circuit.

Cycle

Read Cycle
Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-0.5 to + 7.0 V

V

Yin, Vout

-0.5toVCC
+ 0.5

V

lout
PD

±30

mA

1.0

Temperature Under Bias

Tbias

-10to+85

W
DC

Operating Temperature

TA

o to + 70

DC

Power Supply Voltage
Voltage Relative to VSS For Any Pin
ExceptVCC
Output Current (per I/O)
Power Dissipation

This CMOS memory circuit has
been designed to meet the dc and
ac specilications shown in the
tables, alter thermal equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse air Ilow
01 at least SOO linear leet per minute
is maintained.

DC
Storage Temperature-PlastiC
-55to+ 125
Tsta
NOTE: Perrnanent device damage may occur II ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods 01 time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70° e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Supply Voltage (Operating Voltage Range)

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC + 0.3··

V

--{)S

-

0.8

V

Input Low Voltage
VIL
• VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse Width ~ 20 ns)
··VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ~ 20 ns)

Unit

DC CHARACTERISTICS
Min

Max

Unit

Input Leakage Current (All Inputs, Yin = 0 to VCC)

Parameter

Symbol
Ilka(l)

-

±1.0

Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCC)

IlkalO)

-

±1.0

ISB2

-

IIA
IIA

20

mA

Standby Current (E ~ VCC - 0.2 V, VCC = MAX, I = OMHz, Yin ~ VSS
+ 0.2 V, or~VCC-0.2 V)
Output Low Voltage (IOL = 8.0 rnA)

VOL

-

0.4

V

Output High Voltage (IoH = -4.0 mAl

VOH

2.4

-

V

POWER SUPPLY CURRENTS
Symbol

-12

-15

Unit

AC Active Supply Current (lout = 0 mA, VCC = Max, I = Imax)

ICCA

150

140

mA

AC Standby Current (E = VIH, VCC = MAX, I = Imax)

ISBI

45

40

mA

Parameter

MOTOROLA MEMORY DATA
5-157

MCM6288

CAPACITANCE (f = 1 MHz, dV = 3 V, TA = 25'C, Periodically sampled rather than 100% tested)
Symbol

Max

Unit

Address and Data Input Capacitance

Cin

6

pF

Control Pin Input Capacitance (E,G,w)

Cin

6

pF

Output Capacitance

Cout

7

pF

Characteristic

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10%, TA = 0 to + 70'e, Unless Otherwise Noted)
Input Timing Measurement Reference Level ........ 1.5 V
Input Pulse Levels ............................ 0 to 3 V
Input Rise/Fall Time .............................. 5 ns

Output Timing Measurement Reference Level. . . . . .. 1.5 V
Output Load .......... Figure 1A Unless Otherwise Noted

-12

Symbol

•

Parameter

-15

SId

All

Min

Max

Min

Read Cycle Time

tAVAV

tRC

12

-

15

Address Access Time

tAVOV

tM

12
6

-

Max Unit Noles

-

ns

15

ns

15

ns

8

ns

3

Enable Access Time

tELOV

tACS

Output Enable Access Time

lGLOV

toE

-

Output Hold from Address Change

tAXOX

toH

4

-

4

-

ns

Enable Low to Output Active

tELOX

tCLZ

4

4

-

ns

5,6,7

Output Enable Low to Output Active

lGLOX

toLZ

0

-

0

-

ns

5,6,7

12

4

Enable High to Output High-Z

tEHOZ

tCHZ

0

6

0

8

ns

5,6,7

Output Enable High to Output High-Z

lGHOZ

0

6

0

7

ns

5,6,7

Power Up Time

tELICCH

toHZ
tpu

0

-

0

-

ns

Power Down Time

tEHICCL

tpo

-

12

15

ns

-

NOTES:
1. Wis high for read cycle.
2. For devices with multiple chip enables, Ef and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low.
5. At any given voltage and temperature, tEHOZ max < tELOX min, and 'GHOZ max < tGLQX min, both for a given device and from device to
device.
6. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected. E S VIL and G S VIL'

MOTOROLA MEMORY DATA
5-158

MCM6288

READ CYCLE 1 (See Note 8)
tAVAV
A(ADDRESS)
tAXOX-

o (DATA OUT)

PREVIOUS DATA VALID

DATA VAliD

READ CYCLE 2 (See Notes 2 and 4)

•
A(ADDRESS)

tAVAV

/

\

•
1\

E(CHIP ENABLE

•

tELOV

~tEHQZ--

I-tELQX1

~'XXXXX K

O(DATAOUT)

VCC

ICC

------tELICCH

I-

DATA VAliD

•

tAVOV

II

SUPPLY CURRENT I SB

-

~

tELlCCL_

\

~

AC TEST LOADS
+5V

OUTPUT

4800

~'f-~Zo-=500-fi_

o

RL=500
2550

5pF
(INCLUDING
SCOPE AND JIG)

VL = 1.5V

Figure lB

Figure lA
TIMING PARAMETER ABBREVIATIONS

II

I

t X X X X

signal name from which interval is defined
transition direction for first Signal
signal name to which interval is defined
transition direction for second signal

I

The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don't care
Z = transition to off (high impedance)

TIMING UMITS
The table of timing values shows e~her a minimum or a maximum
limit for each parameter. Input requirements are specified from the extemal system point of view. Thus, address setup time is shown as a
minimum since the system must supply at least that much time (even
though most devices do not require it). On the other hand, responses
from the memory are specified from the device point of view. Thus, the
access time is shown as a maximum since the device output will be
valid no later than that time.

MOTOROLA MEMORY DATA
5-158

MCM6288

WRITE CYCLE 1 (WControlled) (See Notes t 2 and 3)

-12

Symbol
Parameter

•

Std

Alt

Min

WrHe Cycle lime

tAVAV

twe

12

Address Setup lime

tAVWL

tAS

0

-15

Max

Min

Max

Unit

Notes

15

-

ns

4

0

-

ns

12

-

ns

12

-

ns

10

-

ns

-

ns

0

Address Valid to End of Write

tAVWH

tAW

10

Write Pulse Width

twLWH,
twLEH

twp

10

-

Write Pulse Width, High
(Output Enable devices)

twLWH,
twLEH

twp

8

-

Data Valid to End of Write

tOVWH

tow

6

Data Hold lime

twHOX

tOH

0

6

0

7

7

5

ns

Write Low to Output High-Z

twLQZ

twz

0

ns

6,7,8

Write High to Output Active

tWHQX

tow

4

-

4

-

ns

6,7,8

Write Recovery lime

twHAX

twR

0

-

0

-

ns

WRITE CYCLE 2 (E Controlled) (See Notes 1 2 and 3)
Symbol

-12

-15

Std

Alt

Min

Write Cycle lime

tAVAV

twe

12

-

15

Address Setup Time

tAVEL

tAS

0

-

0

Parameter

Max

Min

Max

Unit

Notes

-

ns

4

ns

Address Valid to End of Write

tAVEH

tAW

10

-

ns

tELEH,
tELWH

lew

8

-

12

Enable to End of Write

10

-

ns

Data Valid to End of Write

tOVEH

tow

6

-

7

tEHOX

tOH

0

0

Write Recovery lime

tEHAX

twR

0

-

-

ns

Data Hold lime

0

-

ns

ns

NOTES:
1_ A wrHe occurs during the overlap of E low and IN low.
2. For devices with multiple chip enables, E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. For Output Enable devices, if G goes low coincident with or after IN goes low, the output will remain in a high-impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. For Output Enable devices, if G" VIH, the output will remain in a high-impedance state.
6. At any given voltage and temperature, tWLQG max < twHQX min, both for a given device and from device to device.
7. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
8. This parameter is sampled and not 100% tested.
9. If Egoes low coincident with or after IN goes low, the output will remain in a high-impedance state.
10.1f E goes high coincident with or before IN goes high, the output will remain in a high-impedance state.

MOTOROLA MEMORY DATA
5-160

9,10

MCM6288

WRITE CYCLE 1 (See Note 2)
tAVAV
A(ADDRESS)

1~=============lt~W~W;H~============~~~I-tWHAA
E(CHIP ENABLE)

----t-----,.

...- - - - - tWLWH _ _ _ _ _ _ 1
tWLEH
~---------

Vi (WRITE ENABLE)
t DVWH - 1 4 - - - - + l r t WHDX

o(DATA IN)

DATA VALID

HIGHZ

Q(DATAOUT)

II
WRITE CYCLE 2 (See Note 2)

•

tAVAV
A(ADDRESS)

1\

•

tAVEH

E(CHIP ENABLE)

J

-tAVEL-

I-----

Vi (WRITE ENABLE)

D(DATAIN)

t ELEH _
tELWH

xxxxxxxxxxxxxxxxxf

.. tEHAA--

V

tDVEHDATA VALID

=---mxxxx
tEHDX

HIGH-Z

Q(DATAOUT)

ORDERING INFORMATION (Order by Full Part Number)
MCM
Motorola Memory Prefix
Part Number

~

T T-c.=:
6288

X

XX

XX

Shipping Method (R2 =Tape & Reel, Blank = Rails)
Speed (12 = 12 ns, 15 = 15 ns)

Package (P = 300-mil Plastic DIP, J = 300-mil SOJ)
Full Part Numbers-MCM6288P12
MCM6288P15

MOTOROLA MEMORY DATA
5-161

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6288B
MCM6290B

16Kx4 Bit Static RAMs

II

The MCM6288B and MCM6290B are 65,536 bit static random access memories
organized as 16,384 words of 4 bits, fabricated using Motorola's high-performance
silicon-gate CMOS technology. Static design eliminates the need for external clocks
or timing strobes, while CMOS circuitry reduces power consumption for greater
reliability.
The chip enable (i:) pin is not a clock. In less than a cycle time after E goes
high, the part enters a low-power standby mode, remaining in that state until E goes
low again. This feature reduces system power requirements without degrading access time performance.
The MCM6290B has both chip enable (E) and output enable (G) inputs, allowing
greater system flexibility. Either input, when high, will force the outputs to high
impedance.
• Single 5 V ±1 0% Power Supply
• Fast Access Time (Maximum)
MCM6290B
(xx=88 or 90)
Address
Chip Enable
Output Enable
MCM62xxB-20
20 ns
20 ns
10 ns
MCM62xxB-25
25 ns
25 ns
12 ns
MCM62xxB-35
35 ns
15 ns
35 ns
• Equal Address and Chip Enable Access Time
• Output Enable (<3) Feature for Increased System Flexibility and to Eliminate
Bus Contention Problems (MCM6290B)
• Low Power Operation: 120 mA Maximum, Active AC
• Fully TTL Compatible-Three-State Data Output

MC~

2~VV~UU
1

M~CM6290B
,'
r (' r

1

MCM6~

1

PIN ASSIGNMENT
MCM6288B
AO[ 1.

VCC

M

VSS

A6

MEMORY MATRIX
256 ROWS x
64x4COLUMS

A11
A12

JPACKAGE
300 MILSOJ
CASE 810A

24~

A2

ROW
DECODER

r

PPACKAGE
300 MIL PLASTIC
CASE 724

24

A:3

A5

PPACKAGE
PLASTIC
CASE736A

22P VCC

A1[ 2

21p A13

A2[ 3

20p A12

A3 [ 4

19P A11

M [ 5

1ap A10

A5 [ 6

17

A6 [ 7

16

DQO

A7[ a

15

D01

AB[ 9

14

DQ2

E[ 10

13

003

VSS[ 11

12

W

A9

A13

DOO

MCM6290B

COLUMN 1/0

001

AO

1·

002

A1

2

23P A13

A2

3

22p A12

A3

D03

E~~~~

W

(MCM6209B ONLy) G -~""'----'

PIN NAMES
AO-A 13 .............. Address Input
DOD-D03 .... Data InpuVData Output
IN ..................... Write Enable
G (MCM6290B) ....... Output Enable

E. . . . . . . . . . . . . . . . . . . . . . Chip Enable
NC .................. No Connection
VCC· .. " ...... Power Supply (+5 V)
VSS .. ·· .... · .............. Ground

MOTOROLA MEMORY DATA
5-162

24P VCC

4

21 P A11

M[ 5

20P A10

A5 [ 6

19P A9

A6 [ 7

18

A7[ 8

17 DOO

AB[ 9

16

E[
G[

10

15 002

11

14

D03

Vss [ 12

13

W

NC

D01

MCM6288B- MCM6290B

MCM6288B TRUTH TABLE
E

W

Mode

VCC Current

Output

H
L
L

X

Not Selected
Read
Write

IS81,IS82
ICCA
ICCA

High-Z

H
L

Cycle

Read Cycle
Write Cycle

Dout
High-Z

MCM6290B TRUTH TABLE
E

G

W

Mode

VCC Current

I/O Pin

Cycle

H
L
L
L

X

X

H
L

H
H
L

Not Selected
Output Disabled
Read
Write

IS81,IS82
ICCA
ICCA
ICCA

High-Z
High-Z

-

X

Dout
Din

This device contains circuitry to protect
the inputs against damage due to high static
voltages or electric lields; however, it is advised that normal precautions be taken to
avoid application 01 any voltage higher than
maximum rated voltages to this high-impedance circuit.

Read Cycle
Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

VCC

-0.5 to +7.0 V

V

Vin, V out

-0.5 to VCC +0.5

V

Output Current (per I/O)

lout

i20

mA

Power DiSSipation (TA = 25'C)

PD

1.0

W

Tbias

-10 to +85

'C

TA

oto +70

'c

Power Supply Voltage
Voltage Relative to VSS For Any Pin
ExceptVCC)

Temperature Under Bias
Operating Temperature

Unit

Storage Temperature
-55 to +125
'C
Tsto
NOTE. Permanent device damage may oceu,,1 ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages lor extended
periods 01 time could affect device relability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSs=O V)
Symbol

Min

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.5

V

Input High Voltage

VIH

2.2

VCC+0.3

V

VIL

-0.5·

0.8

V

Parameter

Input Low Voltage
'vIL (min) -0." v oc; vlL (min)

-2.0 v ac (Pu se Wlot :5 0 ns)

DC CHARACTERISTICS
Symbol

Min

Max

Input Leakage Current (All Inputs, Vin=O to Vccl

Parameter

Ilkc(l)

-

il

(.IA

Output Leakage Current (E = VIH, Vout = 0 to VCC)

Ilkg(O)

-

il

(.IA

ICCA

-

120
120
110

mA

AC Active Supply Current (lout = 0 mA, VCC = Max, I = Imax)

tAVAV = 20 ns
tAVAV = 25 ns
tAVAV = 35 ns

Unit

AC Standby Current (E = VIH, Vce = Max, f = Imax)

ISBI

-

40

mA

CMOS Standby Current (VCC = Max, f = 0 MHz, E" VCC - 0.2 V, Yin :5 VSS + 0.2 V or
"VCC- 0.2 V)

IS82

-

15

rnA

Output Low Voltage (IOL=8.0 rnA)

VOL

-

0.4

V

Output High Voltage (IOH=-4.0 mAl

VoH

2.4

-

V

Symbol

Max

Unit

Cin

6

pF

CAPACITANCE (I = 1.0 MHz, dV = 3.0 V, TA = 25'C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance

All Inputs Except E

E
1/0 Capacitance

7
CliO

MOTOROLA MEMORY DATA
5-163

7

pF

MCM6288B-MCM6290B

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA = 0 to +70 oe, Unless Otherwise Noted)
Input Timing Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall Time ..................................... 5 ns

Output Timing Measurement Reference Level ............. 1.5 V
Output Load .. . . . . . . . . . . . . . .. Figure 1A Unless Otherwise Noted

READ CYCLE (See Note 1)
MCM6288B-20 MCM6288B-25 MCM6288B-35
MCM6290B-20 MCM6290B-25 MCM6290B-35

Symbol

Parameter

Standard Alternate

Max

20

-

25

20

-

Read Cycle Time

tAVAV

tRC

Address Access Time

tAVOV

tAA

Enable Access Time

tELOV

tACS

-

Output Hold from Address Change

tAXOX

toE

4

20

-

Min

4

Max

Units Notes

Min

Max

-

35

ns

-

-

25

35

ns

35

ns

-

ns

25

-

MCM6290B

IGLOV

toE

-

10

-

Output Enable Low to Output Active MCM6290B

IGLOX

tLZ

0

-

0

-

Output Enable High to Output High-Z
MCM6290B

tGHOZ

tHZ

0

8

0

10

Output Enable Access Time

•

Min

12

4

-

2
3

15

ns

0

-

ns

4,5,6

0

15

ns

4,5,6

Enable Low to Output Active

tELOX

tLZ

4

-

4

-

4

-

ns

4,5,6

Enable High to Output High-Z

tEHOZ

tHZ

0

8

0

10

0

15

ns

4,5,6

tELICCH

tpu

0

-

0

-

0

-

ns

Power Up Time

-

-

-

Power Down Time
ns
20
25
35
tpD
tEHICCL
NOTES. 1. W IS high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transitioning address.
3. Addresses valid prior to or coincident with Egoing low.
4. At any given voltage and temperature, tEHOZ max is less than tELOX min, and IGHOZ max is less than tGLOX min, both for a given
device and from device to device.
5. Transition is measured ±SOO mV from steady-state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
'
7. Device Is continuously selected (E = VII) and G = VIL (MCM6290B only).

t:

READ CYCLE 1 (See Note 7 Above)

A(ADDRESS)

------~

~I

¥

tAVAV

~tAX;;a;x-=====~·~I~------------~--------------

Q{DATAOUT)

PREVIOUS DATA VALID

~------

DATA VALID

14------------- tAVQV
A(ADDRESS)

E (CHIP ENABLE)

,

READ CYCLE 2 (See Note 3 Above)
tAVAV

,

/

i\

J .... tEHQZ ...

,I+- tELQX
G(OUTPUT ENABLE
(MCM6290B ONLY)

~

tELQV

-

/

1\

/
.... IGHOZ ...

IGLQV-IGLQX -

Q(DATAOUT)

J(XXX)K

f

DATA VALID

tAvav
\.- tEHICCL

tELICCH VCC ICC
SUPPLY CURRENT
ISB------'

-------------

MOTOROLA MEMORY DATA

5-164

MCM6288B-MCM6290B

WRITE CYCLE 1 (W Controlled, See Notes 1 and 6)
MCM6288B-20 MCM6288B-25 MCM6288B-35
MCM6290B-20 MCM6290B-25 MCM6290B-35

Symbol

Parameter

Standard

Alternate

Min

Max

Min

Max

Min

Write Cycle Time

tAVAV

twc

20

-

25

tAVWL

tAS

a

-

a

-

35

Address Setup Time
Address Valid to End of Write

tAVWH

tAW

15

-

20

Write Pulse Width

tWLWH

twp

15

20

Data Valid to End of Write

tOVWH

tow

10

Data Hold Time

twHOX

tOH

Write Low to Output High-Z

twLQZ

twz

a
a

8

10

a
a

30

-

30

-

ns

15

-

n.

a
a

-

n.

15

ns

a

10

Units Notes

Max
ns

2

ns
ns

3,4,
5,6

4
4
4
ns 3,4,5
tow
twHQX
Write Recovery Time
ns
a
a
a
twHAX
twR
NOTES: 1. A wnte occurs dunng the overlap of E low and W low.
2. All write cycle timing is referenced from the last valid address 10 the first transitioning address.
3. Transition is measured ±500 mV from steady-state voltage with load of Figure 1B.
4. Parameter is sampled and not 100% tested.
5. At any given vo.!!age and temperature, twLQZ max...!,s less than tWHQX min both for a given device and from device to device.
6. MCM6290B, if G goes low coincident with or after W goes low, the output will remain in a high impedance state.
Write High to Output Active

tAVAV

---------001

A (ADDRESS)

1+-------

tAVWH

- - - - - ¥ f - - - - r - twHAX

E(CHIP ENABLE)

W(WRITE ENABLE)

---+-----"'"'\

; + - - - - tWLWH

tDVWH --'14--+1D (DATA IN}

DATA VALID

HIGHZ

a (DATA OUT) ----:..::.:::..:..:'----{

AC TEST LOADS
+5V

480

480

a-...-----.

a-.e------....
30 pF (INCLUDING
SCOPE AND JIG)

255

5 pF (INCLUDING
SCOPE AND JIG)

255

Figure 1A

Figure 18

MOTOROLA MEMORY DATA
5-166

•

MCM6288B-MCM6290B

WRITE CYCLE 2 (E Controlled, See Notes 1 and 5)

•

MCM6288B-20 MCM6288B-25 MCM6288B-35
MCM6290B-20 MCM6290B-25 MCM6290B-35

Symbol

Parameter

Standard

Alternate

Min

Write Cycle Time

tAVAV

twc

20

-

25

Address Setup Time

tAVEL

tAS

0

-

0

Address Valid to End of Write

tAVEH

tAW

15

-

Enable to End of Write

tELEH

tcw

15

-

Enable to End of Write

tELWH

tcw

15

Write Pulse Width

twLEH

twp

Data Valid to End of Write

tOVEH

tow

Data Hold Time

tEHOX

tOH

Max

Min

Max

Min

Units Notes

Max

35

-

ns

0

-

ns

30

-

ns

30

-

ns

3,4

30

-

ns

3,4

30

-

ns

15

-

ns

Write Recovery Time
0
0
0
tEHAX
twR
NOTES. 1. A write occurs dUring the overlap of E low and W low.
2. All write cycle timing is referenced from the last valid address to the first transitioning address.
3. If E goes low coincident with or alter Iii goes low, the output will remain in a high impedance condition .
4. If Egoes high coincident with or before Iii goes high, the output will remain in a high impedance condition.
5. MCM6290B, if G goes low coincident with or after Iii goes low, the output will remain in a high impedance state.

ns

20

-

20

-

20

15

-

20

-

10

-

10

-

0

-

0

-

0

2

ns

tAVAV - - - - - - - - - - . . . . . . ;
A (ADDRESS)

tAVEH - - - - - - - - . . . . ;

E(CHIP ENABLE)

-----1-1---* tEHAX2
iii (WRITE ENABLE)

D(DATA IN)

Q(DATAOUT) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...!H.!!:IG~H!..:Z=___ _ _ _ _ _ _ _ _ _ _ _ _ _ __

TIMING PARAMETER ABBREVIATIONS

"".

~,

t

TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply
at least that much time (even though most devices do not require it). On the other hand, responses from the memory are
specified from the device point of view. Thus, the access time
is shown as a maximum since the device never provides data
later than that time.

XXXX

I

from . direction
. . . ''''''''''
"'"....
transition
for first
signal
signal name to which interval is defined
transition direction for second signal
The transition definitions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X = transition to invalid or don1 care
Z = transition to off (high impedance)

III

MOTOROLA MEMORY DATA

6-166

MCM6288B-MCM6290B

ORDERING INFORMATION
(Order by Full Part Number)

I

62XXB.
Motorola Memory Prefix
Part Number

X

L

XX

XX
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns)

-----------'.

, - - - - - - - Package (P = Plastic DIP, J = Plastic SOJ

Full Part Numbers- MCM6288BP20
MCM6288BP25
MCM6288BP35

MCM6290BP20
MCM6290BP25
MCM6290BP35

MCM6290BJ20
MCM6290BJ25
MCM6290BJ35

MCM6290BJ20R2
MCM6290BJ25R2
MCM6290BJ35R2

..

MOTOROLA MEMORY DATA
5-167

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6288C
16K X 4 Bit Static RAM
The MCM6288C is a 65,536 bit static random access memory organized as 16,384
words of 4 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS
circuitry reduces power consumption for greater reliability.

Single 5 V ± 10% Power Supply
Low Power Operation: 120 mA Maximum, Active ac
Fully Static - No Clock or Timing Strobes Necessary
Fast Access Times: 12, IS, 20, 25, 35 ns
Two Chip Controls: E for Automatic Power Down
G for Fast Access to Data and Elimination of Bus Contention
Problems
• Fully TTL Compatible -Three-State Data Output
•
•
•
•
•

--

-

PPACKAGE
300 MIL PLASTIC
CASE736B

PIN ASSIGNMENT
AO

I.

22P Vee

AI

2

21p AI3

AI

A2

3

20P AI2

All

A3

4

19P All

A4

5

lap AIO

A5

6

17P AfJ

AS

7

ISP DQO

A7

a

15p DOl

AS

9

14P D02

BLOCK DIAGRAM

Vee

AI2
AI3
A3

Vss
MEMORY ARRAY
256 ROWS x
64 x 4 COLUMNS

A4
AS

E 10

AS
DOO

VSS

II

lap DOa
12P Vi

COLUMN 1/0

DOl
D02
PIN NAMES

D03

AO - A13 ............. Address Input
DOO - D03 ... Data InpuVData Output
Write Enable
E ...................... Chip Enable
NC ................. No Connection
VCC .......... Power Supply (+ 5 V)
VSS ....................... Ground

W ....................

E
Vi

MOTOROLA MEMORY DATA
5-168

MCM6288C

TRUTH

TABLE

E

W

Mode

Vee Current

110 Pin

H
L
L

X
H
L

Not Selected
Read
Write

ISBI,ISB2
ICCA
ICCA

High-Z
Dout
High-Z

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

- 0.5 to + 7.0 V

V

Vin, Vout

-0.5 to VCC
+0.5

V

Output Current

lout

±20

rnA

Power Dissipation

Po

1.0

W

Tbias

-IOto+85

°C

TA

a to +70

°C

Power Supply Voltage
Voltage Relative to VSS For Any Pin
Except VCC

Temperature Under Bias (TA

= 25°C)

Operating Temperature
Storage Temperature -

This CMOS memory circuit has
been designed to meet the dc and
ac specifications shown in the
tables, afterthermal equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse air flow
of at least 500 linear feet per minute
is maintained.

..

Plastic

-55to+ 125
°C
Tsto
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERAT·
ING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

VCC+0.3"

V

Input Low Voltage

VIL

-OS

-

0.8

V

'VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width" 20 ns)
"VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width" 20 ns)

DC CHARACTERISTICS
Parameter

Standby Current (E" VCC - 0.2 V', Vin" VSS + 0.2 V,
or" VCC -0.2 V, VCC = MAX, f = 0 MHz)
Output Low Voltage (IOL

Min

Max

Unit

Ilko(J)

-

±I.O

IlkQ(O)

-

±I.O

vA
vA

ISB2

-

10

rnA

VOL

-

0.4

V

VOH

2.4

-

V

Symbol

= 0 to VCe)
Output Leakage Current (E = VIH or G = VIH, Vout = 0 to VCe)
Input Leakage Current (All Inputs, Yin

= 8.0 rnA)
=- 4.0 mAl

Output High Voltage (IOH

POWER SUPPLY CURRENTS
Symbol

-12'

-15'

-20'

-25'

-35'

AC Supply Current (lout = 0 rnA)

Parameter

ICCA

120

120

110

110

110

rnA

Standby Current (TIL Levels, VCC = Max)

ISBI

45

40

35

30

30

rnA

, All values represent maximum values

MOTOROLA MEMORY DATA
5-169

Units

MCM6288C

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol

Max

Unit

Address and Data Input Capacitance

Cin

6

pF

Output Capacitance

Cout

7

pF

Characteristic

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to +70oe, Unless Otherwise Noted)
Input Timing Measurement Reference Level ............... 1.5 V
Inpul Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall Time ..................................... 5 ns

Output Timing Measurement Reference Level ............. 1.5 V
Output Load .,. . . . . . . . . . . . . .. Figure 1A Unless Otherwise Noted

READ CYCLE (See Notes 1 and 2)
Symbol
Parameter

-12

-15

-25

-20

-35

Std.

Alt.

Min

Max

Min

Max

Min

Max

Min

Max

Min

Unit

Notes

Read Cycle Time

tAVAV

tRC

12

-

15

-

20

25

-

35

-

ns

3

Address Access Time

tAVOV

tAA

-

12

-

15

20

-

25

35

ns

20

-

-

15

-

-

Max

25

-

35

ns

15

ns

Enable Access Time

IELOV

tACS

tGLOV

tOE

-

12

Output Enable Access Time

6

-

Output Hold from Address
Change

tAXOX

tOH

4

-

4

Enable Low to Output Active

tELOX

tcLZ

4

-

4

-

4

-

4

-

4

-

Enable High to Output High-Z

tEHOZ

tcHZ

0

6

0

8

0

8

0

10

0

15

Output Enable Low to Output
Active

tGLOX

tOLZ

0

-

0

-

0

-

0

-

0

Output Enable High to Output
High-Z

IGHOZ

10HZ

0

6

0

7

0

8

0

10

Power Up Time

tELICCH

tpu

0

-

0

-

0

-

0

-

Power Down Time

tEHICCL

tpD

-

12

-

15

8

4

-

NOTES: 1.
2.
3.
4.
5.

10

20

4

-

12

25

4

ns

5,6,7

ns

5,6,7

ns

5,6,7

-

ns

5,6,7

0

15

ns

5,6,7

0

-

ns

35

ns

4

-

W IS high for read cycle.
For devices with multiple chip enables, E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
All timings are referenced from the last valid address to the first transitioning address.
Addresses valid prior to or coincident with E going low.
At any given voltage and temperature, tEHOZ max is less than tELOX (min), and IGHOZ (max) is less than IGLOX (min), both for a
given device and from device to device.
6. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected (E = VIL, E2 = VIH, G = VIL).

MOTOROLA MEMORY DATA

5-170

MCM6288C

t:

A (ADDRESS)

------~
Q(DATAOUT)

READ CYCLE 1 (See Note 8)

~J

tAVAV

)1\

~t~AA~Q;X-=====~.~I~------------~--------------J

PREVIOUS DATA VALID

f+.--------

~------

DATA VALID
tAVQV

READ CYCLE 2 (See Notes 2 and 4)
tAVAV

\I

A (ADDRESS)

tELQV

V

\

E(CHIP ENABLE)

1\

t

II

/r--tEHQZ ....

~tELQX -

K.XXXX)(

HIGHZ

Q(DATAOUT)

DATA VALID

\

HIGHZ

J

~tEHICCL

tAVQV

SUPPLYCURR~~Y -------------f------------------:1
tELICCH -

ICC

L

' S B .

AC TEST LOADS

Zo=

q

+5V 480n

50n
Q

255 n

Figure 1A

5pF
(INCLUDING
SCOPE AND JIG)

TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external
system point of view. Thus, address setup time is
shown as a minimum since the system must supply at leastthat much time (even though most devices do not require it). On the other hand,
responses from the memory are specified from
the device point of view. Thus, the access time Is
shown as a maximum since the device never provides data later than that time.

Figure 18

MOTOROLA MEMORY DATA
5-171

MCM6288C

WRITE CYCLE 1 (IN Controlled See Notes 1 2 and 3)
-12

Symbol
Parameter

-15

-25

-20

-35

Max

Min

Max

Unit Notes

Std.

All.

Min

Max

Min

Max

Min

Max

Min

Write Cycle lime

tAVAV

twc

12

-

15

-

20

25

-

35

-

ns

Address Setup lime

tAVWL

tAS

0

0

0

-

0

0

ns

15

3

Address Valid to End of Write

tAVWH

tAW

10

-

12

-

20

30

-

Write Pulse Width

twLWH,
twLEH

twP

10

-

12

-

15

-

-

20

-

30

-

ns

Write Pulse Width,
GHigh

twLWH,
tWLEH

twP

8

-

10

-

12

-

15

-

25

-

ns

Data Valid to End of Write

tOVWH

tow

6

-

7

-

10

-

ns

tOH

0

-

0

0

-

0

-

15

twHOX

-

8

Data Hold lime

0

-

ns

Write Low to Output High-Z

twLOZ

twz

0

6

0

7

0

8

0

10

0

15

ns

4,5,6

Write High to Output Active

twHOX

tow

4

-

4

-

4

-

4

-

4

ns

4,5,6

Write Recovery Time

twHAX

twR

0

-

0

-

0

-

0

-

0

-

Max

Min

Max

Min

Max

Min

Max

25

-

35

0

0
25

-

ns

5

ns

WRITE CYCLE 2 (E' Controlled, See Notes 1, 2, and 3)
-12

Symbol
Parametar

-15

-25

-20

Std.

Alt.

Min

Max

Min

Write Cycle lime

tAVAV

twc

12

15

-

20

Address Setup lime

tAVEL

tAS

0

-

0

0

-

-35

Address Valid to End of Write

tAVEH

tAW

8

-

12

15

-

20

-

Enable to End of Write

tELEH,
tELWH

tcw

8

-

-

10

-

12

-

15

-

25

Data Valid to End of Write

tOVEH

tow

6

-

7

8

-

10

15

tOH

0

0

-

0

-

-

tEHOX

-

-

Data Hold lime

0

-

0

-

-

Unit Notes
ns

3

ns
ns
ns

7,8

ns
ns

0
0
0
0
ns
0
tEHAX
twR
NOTES: 1. A write occurs dUring the overlap of E low and W low.
2. For devices with multiple chip enables, Ef and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. All timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, twLOZ max is less than twHOX min, both for a given device and from device to device.
5. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. If E goes low coincident with or after IN goes low, the output will remain in a high impedance state.
8. If E goes high coincident with or before IN goes high, the output will remain in a high Impedance state.
Write Recovery lime

MOTOROLA MEMORY DATA
5-172

MCM6288C

WRITE CYCLE 1 (IN Controlled, See Notes 1 and 2)
--------~

tAVAV
A (ADDRESS)

1+-------

tAVWH

- - - - - - * ' > - - - . j - twHAX

E(CHIP ENABLE)

iii (WRITE ENABLE)
tOVWH -_014-.....D (DATA IN)

DATA VALID

HIGHZ

Q (DATA OUT) --...;.::;:;;,.:.::'----{

II

WRITE CYCLE 1 (E Controlled, See Notes 1 and 2)
tAVAV

--------,------1

A (ADDRESS)

------+---------__

tAVEH - - - - - - - -.....

E(CHIP ENABLE)

r--~-----

tELEH
~---- tAVEL - - - - . , . - - - tELWH
tWLEH

---"""---r-

tEHAX

- - - - - - - + 1 ,..-_ _ _ _ _ __

iii (WRITE ENN;LE)

D (DATA IN)

Q(O~AOUD---------------------------~H~IG~H~Z-----------------------------ORDERING INFORMATION
(Order by Full Part Number)
~
Motorola Memory Prefix
Part Number

_ _MCM-JI

I

x

XX

II

XX

I

....'" - ' ' ' ' . '''" "" ',", OM' .....,
Speed (12 = 12 ns, 15 = 15 ns, 20 = 20 ns,
35 = 35 ns)
Package (P =Plastic DIP, J = Plastic SOJ

Full Part Numbers: MCM6288CP12
MCM6288CP15
MCM6288CP20
MCM6288CP25
MCM6288CP35

MOTOROLA MEMORY DATA
5-173

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - -

TECHNICAL DATA

MCM6290
16K x 4 Fast Static RAM

•

~

The MCM6290 is fabricated using Motorola's high-performance silicon-gate
CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for
greater reliability.
This device meets JEDEC standards for functionality and pinout, and is available in plastic dual-in-line and plastic small-outline J-Ieaded packages.
• Single 5 V ±1 0% Power Supply
• Fully Static - No Clock or TIming Strobes Necessary
• Fast Access Times: 12 and 15 ns
• Equal Address and Chip Enable Access Times
• Output Enable (<3) Feature for Increased Svstem Flexibility and to Eliminate
Bus Contention Problems.
• Low Power Operation: 140 -150 mA Maximum ac
• Fully TTL-Compatible - Three-State Output

PPACKAGE
3OQ-MILSOJ
CASE 724A

.-.'

JPACKAGE
300-MIL SOJ
CASE 810A

PIN ASSIGNMENT

,
BLOCK DIAGRAM

'l,

AO

VCC

AI

AI3

A2

A12

AO

--I':::-r---,

AI

--1::>--1

A9

---f:>--l

A5

A9

AIO --l~--l

AS

NC

AII--l~--l

A7

DOO

AI2 --l~-I

AS

DOl

E

D02

.

·.r,

AI3 --l~-I

-~~_---J

All
AIO

A4

13

D03

W

VSS
DOO
DOl
PIN NAMES

A2

A3

A4

A5

A6

A7

AS

~H:::::==========~

1
w 3-

MOTOROLA MEMORY DATA
5-174

AO-AI3 .............. Address Input
DOD-D03 ... Data InpuVData Output
W ..................... Write Enable
13 ................... Output Enable
E ..................... Chip Enable
NC .................. No Connection
VCC .......... Power Supply (+ 5 V)
VSS ....................... Ground

MCM6290

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
lields; however, It is advised that
normal precautions be taken to
avoid application 01 any voltage
higher than maximum rated voltages to this high-impedance circuit.

TRUTH TABLE
E

G

W

Mode

Vee Current

I/O Pin

H
l
l
l

X
H
L
X

X
H
H
L

Not Selected
Output Disabled
Read
Write

ISB1,ISB2
ICCA
ICCA
ICCA

High-Z
High-Z
Dout
Din

This CMOS memory circuit has
been designed to meet the dc and
ac specilications shown in the
tables, after thermal equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse air flow
01 at least 500 linear leet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

VCC

- 0.5 to + 7.0 V

V

Yin, Vout

-0.5 to VCC
+0.5

V

Output Current (per I/O)

lout

±20

rnA

Power Dissipation

Po

1.0

Tbias

-1010+85

W
·C

Power Supply Voltage
Voltage Relative to VSS For Any Pin
ExceptVcc

Temperature Under Bias (TA = 25·C)

Unit

·C
Oto+ 70
TA
·C
Storage Temperature-Plastic
-55to+125
Tsta
NOTE: Permanent device damage may occur HABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages lor extended
periods 01 time could affect device reliability.
Operating Temperature

II

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, T A = 0 to 70oe, Unless Otherwise Noted)
RECOMMENDED OPERATING CONOmONS
Symbol

Min

lYP

Max

Unit

Supply Voltage (Operating Voltage Range)

Paramater

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC + 0.3**

V

-OS

-

O.B

V

Input Low Voltage
Vil
* Vil (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse Width S 20 ns)
**VIH (max) =VCC + 0.3 V dc; VIH (max) =VCC + 2.0 V ac (pulse width s 20 ns)

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input leakage Current (All Inputs, Yin =0 to VCC)

Ilka(l)

-

±1.0

Output Leakage Current (E =VIH or G =VIH, Vout =0 to VCC)

IlkalO)

-

±1.0

;.tA
;.tA

ISB2

-

20

rnA

Parameter

Standby Current (E ~ VCC - 0.2 V*, Yin S VSS + 0.2 V, or ~ VCC - 0.2
V, VCC =max, I =0 MHz)
Output low Voltage (IOl =B.O rnA)

VOL

-

0.4

V

Output High Voltage (IOH =- 4.0 rnA)

VOH

2.4

-

V

Symbol

-12

-15

Unit

ICCA

150

140

rnA

ISBI

45

40

rnA

POWER SUPPLY CURRENTS
Parameter
AC Active Supply Current (lout =0 rnA, VCC =Max, I
AC Standby Current (E

=I max)

=VIH, VCC =MAX, I =Imax)

MOTOROLA MEMORY DATA

5-175

MCM6290

CAPACITANCE (f =1 MHz, dV =3 V, TA =25' C, Periodically sampled rather than 100 % tested)
Symbol

Max

Unit

Address and Data Input Capacitance

Characteristic

Cin

6

pF

Control Pin Input Capacitance (E,G,W)

Cin

6

pF

Output Capacitance

Cout

7

pF

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5 V ± 10 %, TA = 0 to + 70' e, Unless Otherwise Noted)
Input Timing Measurement Reference Level .. . . . . .. 1.5 V
Input Pulse Levels ............................ 0 to 3 V
Input Rise/Fall TIme .............................. 5 ns

Output Timing Measurement Reference Level. . . . . .. 1.5 V
Output Load .......... Figure 1A Unless Otherwise Noted

Symbol

•

Parameter

-12

-15

Std

Alt

Min

Max

Min

Max

Unit

Notes

Read Cycle lime

tAVAV

tRC

12

-

15

-

ns

3

Address Access lime

tAVQV

tM

12

15

ns

Enable Access lime

tELQV

tACS

Output Enable Access lime

IGLQV

toE

-

Output Hold from Address Change

tAXQX

tOH

4

Enable Low to Output Active

tELQX

tcLZ

4

Output Enable Low to Output Active

IGLOX

toLZ

0

-

Enable High to Output High-Z

tEHOZ

tCHZ

0

Output Enable High to Output High-Z

IGHQZ

Power Up Time

tELICCH

toHZ
tpu

Power Down lime

tEHICCL

tpD

-

12

-

15

ns

6

-

8

ns
ns

0

-

6

0

8

. ns

5,6,7

0

6

0

7

ns

5,6,7

0

-

0

-

ns

-

12

-

15

.ns

4
4

4

ns

5,6,7

ns

5,6,7

NOTES:
1. Wis high for read cycle.
2. For devices with multiple chip enables, Ef and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. All timings are referenced from the last valid address to the first transitioning address.
4. Addresses valid prior to or coincident with E going low.
5. At any given voltage and temperature, tEHQZ max < tELQX min, and tGHQZ max < tGLQX min, both for a given device and from device
to device.
6. Transition is measured ± 500 mV from steady-state voltage wijh load of Figure 1B.
7. This parameter is sampled and not 100% tested.
8. Device is continuously selected. E" VIL and G" VIL'

MOTOROLA MEMORY DATA

5-176

MCM6290

READ CYCLE 1 (See Note 8)

..

tAVAV
A(ADDRESS)
tAXOX-

o(DATA OUT)

DATA VALID

PREVIOUS DATA VALID
tAVOV - - - - - - - - - - <..~I

READ CYCLE 2 (See Notes 2 and 4)

•
A(ADDRESS)

J

tAVAV

i

II

•
E(CHIP ENABLE)
G(OUTPUT ENABLE)

..

tELOV

1\

v..-tEHOZ-

!+tELOX....
-tGLOX ....

1/

II

--tGHOZ-

1\

tGLOV-

KXXXXXK
..

O(DATAOUT)

ICC
VCC
SUPPLY CURRENT I SB

tELICCH

--------

DATA VALID

tAVOV

I-

II

-

~

tELICCL-

\

'-

AC TEST LOADS

OUTPUT

....r::: la=son
-'D-fv---------,)I~

480

n

o

RL=son
255

n

5pF
(INCLUDING
SCOPE AND JIG)

vL = 1.5V

Figure 1A

Figure 18

TIMING PARAMETER ABBREVIATIONS

IXXXX
signal name from which interval is defined
transition direction for first signal
signal name to which interval is defined
transition direction for second signal

I

III

The transition defin~ions used in this data sheet are:
H = transition to high
L = transition to low
V = transition to valid
X= transition to invalid or don't care
Z = transition to off (high impedance)

TIMING LIMITS

The table of timing values shows either a minimum or a maximum
limitfor each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a
minimum since the system must supply at least that much time (even
though most devices do not require it). On the other hand, responses
from the memory are specified from the device point of view. Thus, the
access time is shown as a maximum since the device output will be
valid no later than that time.

MOTOROLA MEMORY DATA

5-177

MCM6290

WRITE CYCLE 1 (W Controlled) (See Notes 1 2 and 3)
Symbol

-12

-15

SId

All

Min

Max

Min

Max

Write Cycle lime

tAVAV

twc

12

15

tAVWL

tAS

0

-

ns

Address Setup lime

-

-

ns

7

ns

6,7,8

-

ns

6,7,8

Paramater

Address Valid to End of Write

tAVWH

tAW

10

Write Pulse Width

twLWH,
twLEH

twP

10

Write Pulse Width, High
(Outpu1 Enable devices)

twLWH,
twLEH

twP

8

Data Valid to End of Write

tOVWH

tow

6

twHOX

tOH

0

Data Hold lime
Write Low to Output High-Z

twLQZ

twz

0

Write High to Output Active

twHQX

tow

4

Write Recovery lime

twHAX

twR

0

6

-

0
12
12
10
7
0
0

4
0

Unit Notes
4

ns
ns
ns
5

ns
ns

ns

WRITE CYCLE 2 (E Controlled) (See Notes 1 2 and 3)
-12

Symbol
Parameter
Write Cycle lime

-15

SId

All

Min

Max

Min

Max

tAVAV

twC3.3

12

-

15

-

ns

-

ns

-

ns

Address Setup lime

tAVEL

tAS

0

Address Valid to End of Write

tAVEH

tAW

10

Enable to End of Write

tELEH,
tELWH.

lew

8

Data Valid to End of Write

tOVEH

tow

6

Data Hold lime

tEHOX

toH

0

Write Recovery lime

tEHAX

twR

0

-

0
12
10
7

0
0

Unit Notes

ns
ns

ns
ns

NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. For devices with muRiple chip enables, E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E.
3. For Output Enable devices, if G goes low coincident wnh or after Wgoes low, the output will remain in a high-impedance state.
4. All timings are referenced from the last valid address to the first transitioning address.
5. For Output Enable devices, if G ~ VIH, the output will remain in a high-impedance state.
6. At any given voltage and temperature, twLOO max < twHQX min, both for a given device and from device to device.
7. Transition is measured ± 500 mV from steady-state voltage wtth load of Figure 1B.
8. This parameter is sampled and not 100% tested.
9. If E goes low coincident with or aiter Wgoes low, the output will remain in a high-Impedance state.
10. If E goes high coincident with or before Wgoes high, the output will remain in a high-impedance state.

MOTOROLA MEMORY DATA
5-178

4

9,10

MCM6290

WRITE CYCLE 1 (See Note 2)
tAVAV
A(ADDRESS)

1-------- tAVWH -------··1-- tWHAX
E(CHIP ENABLE)
W(WRITE ENABLE)
t OVWH - 1 - - - - - 1 - - tWHOX

o(DATA IN)

DATA VALID

HIGHZ

Q(OATAOUT)

II

WRITE CYCLE 2 (See Note 2)

•

•

tAVAV

I

A(ADDRESS)

I[

~

•

tAVEH

E(CHIP ENABLE)

J

-tAVEL-

_tELEH_
~tEHAX"
tELWH

V

W(WRITE ENABLE)

o(DATA IN)

xxxxxxxxxxxxxxxxxf

tOVEHDATA VALID

tEHDX

==mxxXX

HIGH-Z
Q(OMAOUT) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

ORDERING INFORMATION (Order by Full Part Number)

-==r- T
MCM

Motorola Memory Prefix
Part Number

6290

T-c2
X

XX

XX

Shipping Method (R2 = Tape & Reel, Blank = Rails)
Speed (12 = 12 ns, 15 = 15 ns)

Package (P = 300-mil Plastic DIP, J = 300-mil SOJ)
Full Part Numbers-MCM6290P12
MCM6290J12
MCM6290J12R2
MCM6290P15
MCM6290J15
MCM6290J15R2

MOTOROLA MEMORY DATA
5-179

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6290C
16K x 4 Bit Static RAM
With Output Enable
The MCM6290C (with OE) is a 65,536 bit static random access memory organized as
16,384 words of 4 bits, fabricated using Motorola's high-performance silicon-gate CMOS
technology. Static design eliminates the need for external clocks or timing strobes, while
CMOS circuitry reduces power consumption for greater reliability.
The chip enable (E) pin is not a clock. In less than a cycle time after E goes high, the
part enters a low-power standby mode, remaining in that state until E goes low again.
This feature reduces system power requirements without degrading access time
performance.
The MCM6290C has both chip enable (E) and output enable (G) inputs, allowing
greater system flexibility. Either input, when high, will force the outputs to high impedance.

•

•
•
•
•
•

Single 5 V ±1 0% Power Supply
Low Power Operation: 120 mA Maximum, Active ac
Fully Static - No Clock or Timing Strobes Necessary
Fast Access Times: 10, 12, 15, 20, 25, 35 ns
Two Chip Controls: E for Automatic Power Down
G for Fast Access to Data and Elimination of Bus Contention
Problems
• Fully TTL Compatible - Three-State Data Output

~.,
.~:;U:~CPLASTIC
CASE 724A

,

JPACKAGE

300MILSOJ

CASE 810A

PIN ASSIGNMENTS
AO[ 1-

24

Al

23 A13

A2

22

A12

21

All

A4

20

Al0

AS

19

A9

18

Ne

A3

BLOCK DIAGRAM
Al

----~ ~-r--~--,

AS

All -------;

Vee
Vss

A12 ----~
A13 -------;
A3 ----~

MEMORY ARRAY
25SROWSx
64 x 4 COLUMNS

A4 -------;

Vee

4

7

17 OQO

A7
AS

9

16 DOl

E 10

15 OQ2

a-

II

14 OQ3

Vss [

12

13

Vi

AS ----~

AS

DQO

-~~~===!=l====;::::::=====L. . . .

----...-t

DOl--_-H
OQ2--.....-H

D03

PIN NAMES
AO-A13 .............. Address Input
DOQ-D03 .... Data InpuVData Output
W .................... Write Enable
G .................... Output Enable
E ...................... Chip Enable
NC ................. No Connection
VCC .......... Power Supply (+ 5 V)
VSS ....................... Ground

_-+-+-H

Vi
G---.......---'

MOTOROLA MEMORY DATA
5-180

MCM6290C

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
lields; however, it is advised that
normal precautions be taken to
avoid application 01 any voltage
higher than maximum rated volt·
ages to this high-impedance circuit.

TRUTH TABLE
E

G

W

Mode

VCC Current

110 Pin

H
L
L
L

X
H
L
X

X
H
H
L

Not Selected
Output Disabled
Read
Write

ISB1,ISB2
ICCA
ICCA
ICCA

High-Z
High-Z
Dout
Din

This CMOS memory circuit has
been designed to meet the dc and
ac specifications shown in the
tables, alter thermal equilibrium has
been established. The circuit is in a
test socket or mounted on a printed
circuit board and transverse air Ilow
of at least 500 linear feet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Power Supply Voltage
Voltage Relative to VSS For Any Pin
ExceptVcc
Output Current
Power DisSipation
Temperature Under Bias (TA = 25°C)
Operating Temperature
Storage Temperature -

Symbol

Value

Unit

VCC

- 0.5 to + 7.0 V

V

Yin, VOU!

-0.5 to VCC
+0.5

V

lout
PD

±20

mA

1.0

W

Tbias
TA

-1010+85

°C

oto + 70

°C

Plastic

-55to+125
°C
Tsta
NOTE: Permanent device damage may occur il ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages lor extended
periods 01 time could affect device reliability.

II

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70o e, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

V,H

2.2

VCC+0.3"

V

Input Low Voltage

V,L

-OS

-

0.8

V

• V,L (min) = - 0.5 V de; V,L (min) = - 2.0 Vac (pulse width" 20 ns)
"V,H (max) = VCC + 0.3 V de; V,H (max) = VCC + 2.0 V ac (pulse width,;; 20 ns)

DC CHARACTERISTICS
Parameter

Max

-

±1.0

-

"A

±1.0

IlA

-

10

mA

VOL

-

0.4

V

VOH

2.4

-

V

I,ka(l)
l'kaIO)
ISB2

Standby Current (E;;, VCC - 0.2 V', Vin "VSS + 0.2 V,
or;;'VCC-0.2 V, VCC =MAX, I =0 MHZ)
Output Low Voltage (IOL =8.0 mAl
Output High Voltage (IOH

Min

Symbol

=0 to VCC)
Output Leakage Current (E =V,H or G =VIH, VOU! =0 to VCC)
Input Leakage Current (All Inputs, Yin

=- 4.0 mAl

Unit

POWER SUPPLY CURRENTS
Parameter

Symbol

-10' -12' -IS' -20' -25' -35'

Units

AC Supply Current (lout = 0 mAl

ICCA

120

120

120

110

110

110

mA

Standby Current (TIL Levels, Vec = Max)

ISBI

50

45

40

35

30

30

mA

, All values represent maxImum values

MOTOROLA MEMORY DATA
5-181

MCM6290C

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic

Symbol

Max

Unit

Cin

6

pF

Cout

7

pF

Address and Data Input Capacitance
Output Capacitance

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to + 70 o e, Unless Otherwise Noted)
Output Timing Measurement Reference Level ............. 1.5 V
Output Load ................. Figure 1A Unless Otherwise Noted

Input Timing Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. to 3.0 V
Input Rise/Fall Time ..................................... 5 ns

a

READ CYCLE (See Notes 1 and 2)
Symbol
Parameters

•

-10

-12

Std.

Alt.

Min

Read Cycle Time

tAVAV

tRC

10

-

12

Address Access Time

tAVQV

tAA

-

10

Max

Min

-15

Max

Min

-

15

-

20

-

25

-

12

-

20

-

25

12

-

-

25

8

-

20

6

-

-

10

-

12

-

Enable Access Time

tELQV

tACS
toE

-

10

tGLQV

5

Output Hold from Address
Change

tAXQX

tOH

4

-

4

-

4

-

4

Enable Low to Output
Active

tELQX

tCLZ

4

-

4

-

4

-

Enable High to Output
High-Z

tEHQZ

tCHZ

a

5

a

6

a

Output Enable Low to
Output Active

tGLQX

toLZ

a

-

a

-

Output Enable High to
Output High-Z

tGHQZ

toHZ

a

5

a

tELICCH

tpu

a

-

a

15
15

4

4

-

4

-

8

a

8

a

a

-

a

-

6

a

7

a

-

a

-

a

35

Max

Unit

Notes

-

ns

3

35

ns

35

ns

15

ns

4

4

-

10

a

15

ns

5,6,7

a

-

a

-

ns

5,6,7

8

a

10

a

15

ns

5,6,7

-

a

-

a

-

ns

4

-

ns

5,6,7

ns

5,6,7

10
12
15
20
25
35
ns
tEHICCL tpD
W is high for read cycle.
For devices with multiple chip enables, E1 and E2 are represented by E in this data sheet. E2 is of oPPOsite polarity to E.
All timings are referenced from the last valid address to the first transitioning address.
Addresses valid prior to or coincident with E going low.
At any given voltage and temperature, tEHQZ max is less than tELQX (min), and tGHQZ (max) is less than tGLQX (min), both for a
given device and from device to device.
Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
This parameter is sampled and not 100% tested.
Device is continuously selected (E = VIL, E2 = VIH, G = VIL).

Power Down Time

6.
7.
8.

Min

Min

Output Enable Access
Time

NOTES: 1.
2.
3.
4.
5.

Max

Max

-

Power Up Time

-35

-25

-20

Min

Max

MOTOROLA MEMORY DATA
5-182

MCM6290C

t:

A (ADDRESS)

------o(DATA OUT)

READ CYCLE 1 (See Note 8)

~J

tAVAV

)1\

tt~~~~====:;.f!------------~--------------

PREVIOUS DATA VALID

~-----

DATA VALID

14------- tAVOV

READ CYCLE 2 (See Notes 2 and 4)
tAVAV

\V

A (ADDRESS)

•

If\.

tELOV

V

\

E(CHIP ENABLE)

1\

l!--tEHOZ"

\1-- tEL~G(OUTPUT ENABLE)

V

~

I
~tGHOZ"

tGLOV!--tGLOX -

HIGHZ

o (DATA OUT)

:--------twLWH ------~ r-------iii (WRITE ENABLE)

D (DATA IN)

Q(DATAOUT)

DATA VALID

HIGH-Z

---=:.:..---<

AC TEST LOADS

q

+5V 480Q

Q

255 Q

Figure 1A

5 pF
(INCLUDING
SCOPE AND JIG)

Figure 18

MOTOROLA MEMORY DATA
5-189

MCM6706

WRITE CYCLE 2 (S Controlled, See Notes 1 and 2)
MCM6706-10

MCM6706-12

Alternate

Min

Max

Min

-

12

Symbol
Parameter

Standard

Write Cycle Time

tAVAV

!wc

10

Address Setup Time

tAVSL

tAS

0

-

Unit

Notes

ns

3

0

-

ns

Address Valid to End of Write

tAVSH

tAW

9

-

10

-

ns

Chip Select to End of Write

tSLWH,
tSLSH

tcw

8

-

9

-

ns

Oata Valid to End of Write

tOVSH

tow

5

-

6

tSHOX

tOH

0

0

tWR

0.5

-

-

ns

Oata Hold Time
Write Recovery Time

II

Max

0.5

4,5

ns
ns

tSHAX
NOTES:
1. A write occurs during the overlap of S low and Wlow.
2. Productsensitivites to noise require proper grounding and decoupling of power supplies as well as minimization orelimination of bus contention
conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If S goes low coincident with or after Wgoes low, the output will remain in a high-impedance condition.
5. If S goes high coincident with or before Wgoes high, the output will remain in a high-impedance condition.

~------------------- ~VAV----------------------~

A (ADDRESS)

S (CHIP SELECn

-----+l----.rW(WRITE ENABLE)

o (DATA IN)

HIGH·Z

Q (DATA OUT)

TIMING LIMITS
The table oftiming values shows either
a minimum or a maximum limit for each
parameter. Input requirements are specified from the external system point of
view. Thus, address setup time is shown
as a minimum since the system must
supply at least that much time (even
though most devices do not require it).
On the other hand, responses from the
memory are specified from the device
point of view. Thus, the access time is
shown as a maximum since the device
never provides data later than that time.

MOTOROLA MEMORY DATA

5-190

tSHAX

MCM6706

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix
Part Number

T

x XX XX

I

I

1 - Shipping Method (R2 = Tape and Reel, Blank = Rails)

~ Speed(10=10ns,12=12ns)
Package (J = 300-mil SOJ)

Full Part Number -

MCM6706Jl0
MCM6706J12

MCM6706Jl0R2
MCM6706J12R2

MOTOROLA MEMORY DATA

5-191

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

Product Preview

MCM6706A

32K x 8 Bit Static Random
Access Memory
The MCM6706A is a 262,144 bit static random access memory organized as 32,768
words of 8 bits, fabricated using high performance silicon-gate BiCMOS technology.
Static design eliminates the need for external clocks or timing strobes.
Output enable (<3) is a special control feature that provides increased system flexibility and eliminates bus contention problems.
The MCM6706A is available in a 300 mil, 28 lead surface-mount SOJ package.
•
•
•
•
•

•

Single 5.0 V ±1 0% Power Supply
Fully Static - No Clock or Timing Strobes Necessary
All Inputs and Outputs are TTL Compatible
Three State Outputs
Fast Access Times: MCM6706A - 8 ns
MCM6706A - IOns
MCM6706A - 12 ns

28'
1

J PACKAGE

300 MILSOJ
CASE 810B

A14

VCC

W

BLOCK DIAGRAM

MEMORY MATRIX
(2S6ROWS
128x8 COLUMNS)

A?

A13

A6

AS

AS

A9

A4

All

A3

G

A2

Al0

AI

E

AO

DO?

000

DOS

001

DOS

DQ2

004

VSS

003

PIN NAMES

COLUMN VO

AD-A 14 .. .. .. .. .. .. .. .. ... Address
Write Enable
E ...................... Chip Enable
G ................... Output Enable
DOD-DO? ........ Data InputlOutput
VCC ........... +5.0 V Power Supply
VSS ....................... Ground

W ....................

w=~~~

G

____________-;====~~

This document contains information on a new product Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
5-192

MCM6706A

TRUTH TABLE

E

G

W

Mode

1/0 Pin

H
L
L
L

X
H
L
X

X
H
H
L

Not Selected
Read
Read
Write

High-Z
High-Z
Dout
Din

This device contains circuitry to protect
the inputs against damage due to high
static voltages or electric fields; however,
it is advised that normal precautions be
taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit.

Cycle

-

-

Read Cycle
Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-0.5 to +7.0

V

Yin, Vout

-0.5 to VCC+0.5

V

Output Current

lout

±30

mA

Power Dissipation

Po

2.0

W

Temperature Under Bias

Tbias

-10 to +85

·C

Operating Temperature

TA

o to +70

·C

Power Supply Voltage
Voltage Relative to VSS for Any
Pin Except VCC

This BiCMOS memory circuit has been
designed to meet the dc and ac specifications shown in the tables, after thermal
equilibrium has been established. The
circuit is in a test socket or mounted on
a printed circuit board and transverse air
flow of at least 500 linear feet per minute
is maintained.

II

·C
-55 to +125
Tstg
NOTE: Permanent device damage may occunf ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
Storage Temperature - Plastic

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, T A = 0 to lO·C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3·

V

-1

-

0.8

V

Parameter

Input Low Voltage

VIL
·VIH (max) = VCC +0.3 V dc; VIH (max) = +2.0 V ac (pulse width" 2.0 ns) for I ,,20 mA.
··VIL (min) = -1 V dc@ 30 mA; VIL (min) = -2.0 V ac (pulse width" 2.0 ns).
DC CHARACTERISTICS
Parameter

Max

Unit

±1.0

IlA

Ilkg(O)

-

±1.0

IlA

ICCA

-

185
175
175

mA

0.4

V

-

V

Ilkg(l)

tAVAV = 8 ns
MCM6706A-10: tAVAV = 10 ns
MCM6706A-12:tAVAV = 12 ns

Output Low Voltage (IOL =8.0 mAl
Output High Voltage (IOH

Min

Symbol

=0 to VCe)
Output Leakage Current (E = VIH, Vout = 0 to VCC)
AC Supply Current (lout =0 mAl
MCM6706A -8:
Input Leakage Current (All Inputs, Yin

=-4.0 mAl

VOL

-

VOH

2.4

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25·C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Address Input Capacitance
Control Pin Input Capacitance (E, G, W)

110 Capacitance

MOTOROLA MEMORY DATA
5-193

Symbol

Max

Unit

Cin

6

pF

Cin

8

pF

CliO

8

pF

MCM6706A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA = 0 to 70oe, Unless Otherwise Noted)
Input Timing Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall Time ..................................... 3 ns

Output Timing Measurement Reference Level ............. 1.5 V
Output Load ... . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .. See Figure 1A

READ CYCLE (See Notes 1 and 2)
Symbol
Parameter

II

MCM6706A-8

MCM6706A-10

MCM6706A-12

Standard

Altarnata

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

tRC

8

-

10

-

12

-

ns

3

Address Access Time

tAVOV

tAA

8

-

12

ns

tELOV

tACS

10

-

12

ns

Output Enable Access time

tGLOV

toE

4

-

10

Chip Enable Access Time

-

5

-

7

ns

Output Hold from Address Change

tAXOX

tOH

4

-

4

4

tELOX

tLZ

4

-

4

0

-

ns

Chip Enable Low to Output Active

-

ns

4,5,6

4

0

5

0

6

ns

4,5,6

8

Chip Enable High to Output High-Z

tEHOZ

tHZ

0

Output Enable Low to Output Active

tGLOX

tLZ

0

-

0

-

0

-

ns

4,5,6

Output Enable High to Output High-Z

tGHOZ

tHZ

0

4

0

5

0

6

ns

4,5,6

NOTES:
1. Wis high for read cycle.
2. Productsensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention
conditions during read and write cycles.
3. All read cycle timing is referencad from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHOZ max < tELOX min, and tGHOZ max < tGHOX min, both for a given device and from device to
device.
5. Transition is measured SOO mV from steady-state vo~age with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VII)'
8. Addresses valid prior to or coincident with 1: going low.

READ CYCLE 1 (See Note 7 Above)
tAVAV -------~
A (ADDRESS)

,.-----

tAJ(OX
Q (DATA Oun

PREVIOUS DATA VALID

DATA VALID

READ CYCLE 2 (See Note 8 Above)
tAVAV
A (ADDRESS)

E(CHIP ENABLE)

G(OUTPUT ENABLE)

t

V
r\

1

tElQV

-f.
I

tElOX

\

talQV-

-I
I

talQ"
Q(DATAOUn

~XXXXJ
tAVQV

MOTOROLA MEMORY DATA
5-194

DATA VALID

'EHQZ

taHOZ

MCM6706A

WRITE CYCLE 1 (W Controlled See Notes 1 and 2)
Symbol
Parameter
Write Cycle Time

MCM6706A-8

MCM6706A-10

MCM6706A-12

Min

Max

Min

-

10

12

-

9

-

9

-

Standard

Alternate

Min

Max

tAVAV

twc

8
0

0

Max

Unit

Notes

ns

3

0

-

10

-

ns

9

-

ns

-

ns

Address Setup Time

ns

tAVWL

tAS

Address Valid to End of Write

tAVWH

tAW

8

Write Pulse Width
G High, GLow

tWLWH,
tWLEH

twp

8

Data Valid to End of Write

tDVWH

tow

4

-

5

-

6

Data Hold Time

twHDX

tDH

0

-

0

-

0

Write Low to Data High-Z

tWLOZ

twz

0

4

0

5

0

6

ns

4,5,6

Write High to Output Active

tWHOX

tow

4

4

-

4

-

ns

4,5,6

Write Recovery Time

twHAX

tWR

0

-

0

-

0

-

ns

ns

NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention
conditions during read and write cycles.
3. Ali write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 500 mV from steady-state voltage with load of Figure 1B.
5. Parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLOZ max is < tWHOX min both for a given device and from device to device.
~---------------------tAVAV--------------------~

A (ADDRESS)
i+-------------------tAvwH------------------+joo---i_r_ tWHAX

r.------

E(CHIP ENABLE)
tWLEH

_ _ _+-_ _ _ _ _-,. ""';------tWLWH-----~

r--------

W(WRITE ENABLE)
twHDX
D (DATA IN)

DATA VALID

HIGH-Z

Q (DATA OUT) ---~:..::....---<

AC TEST LOADS

~

+5V 480n

Q

255 n

Figure 1A

5 pF
(INCLUDING
SCOPE AND JIG)

Figure 18

MOTOROLA MEMORY DATA
5-195

MCM6706A

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
Symbol
Parameter
Write Cycle Time

..

MCM6706A-8

Standard

Alternate

Min

tAVAV

!wc

8

MCM6706A-l0

Max

Min

-

10

MCM6706A-12
Unit

Notes

ns

3

0

-

-

10

-

ns

9

-

ns
ns

Max

Min

-

12

Max

Address Setup Time

tAVSL

tAS

0

Address Valid to End of Write

tAVEH

tAW

8

-

9

Chip Enable to End of Write

tELWH,
tELEH

lew

6

-

7

Data Valid to End of Write

tOVEH

tow

4

-

5

-

6

-

Oata Hold Time

tEHOX

tOH

0

-

0

-

0

-

ns

Write Recovery Time

tEHAX

tWR

0

-

0

-

0

-

ns

0

ns

4,5

NOTES.
1. A write occurs during the overlap of E low and Wlow.
2. Product sensitivites to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention
conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after Wgoes low, the output will remain in a high impedance condition .
5. If E goes high coincident with or before Wgoes high, the output will remain in a high impedance condition.

) + - - - - - - - - - - - IAVAV - - - - - - - - - - - - - 1
A (ADDRESS)

E(CHIP ENABLE)
---j4---r-

tEHAX

W(WRITE ENABLE)

--+f--r-

o(DATA IN)

HIGH·Z

Q (DATA OUT)

TIMING LIMITS
The table of timing values shows either
a minimum or a maximum limit for each
parameter. Input requirements are specified from the external system point of
view. Thus, address setup time is shown
as a minimum since the system must
supply at least that much time (even
though most devices do not require it).
On the other hand, responses from the
memory are specified from the device
paint of view. Thus, the access time is
shown as a maximum since the device
never provides data later than that time.

MOTOROLA MEMORY DATA

5-196

tEHDX

MCM6706A

ORDERING INFORMATION
(Order by Full Part Number)

T
. - . Mom., '''''

.

§Zl!liA

X

xx

I I I

XX

I

Part Number - - - - - - - - - - - - - '

,,,"...-

'" -' " "'" RoO, .~. - ROo,

Speed (8 = 8 ns, 10 = 10 ns)
Package (J = 300 mil SOJ)

Full Part Number -

MCM6706AJ8
MCM6706AJ10
MCM6706AJ12

MCM6706AJ8R2
MCM6706AJ10R2
MCM6706AJ12R2

•

MOTOROLA MEMORY DATA
5-197

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6708
MCM6709

Advanced Information
64K x 4 Bit Static RAM

--

MCM6708

The MCM670S and the MCM6709 are 262,144 bit static random access
memories organized as 65,536 words of 4 bits, fabricated using high-performance
silicon-gate BICMOS technology. Static design eliminates the need for external
clocks or timing strobes.
Output enable, (G), a special control feature of the MCM6709, provides increased
system flexibility and eliminates bus contention problems.
The MCM670S is available in a 300-mil, 24-lead plastic surface-mount SOJ
package. The MCM6709 is available in a 300-mil, 2S-lead plastic surface-mount SOJ
package.
• Single 5 V ± 10% Power Supply
• Fully Static - No Clock or Timing Strobes Necessary
• All Inputs and Outputs are TTL-Compatible
• Three-State Outputs
• Fast Access Times:
MCM670S - 10 ns
MCM6709 - 10 ns
MCM670S - 12 ns
MCM6709 - 12 ns
BLOCK DIAGRAM

A----t
A----1

•

A----t
A---I
A----1

ROW
DECODER

MEMORY MATRIX
256 ROWS x 256 x 4
COLUMNS

•

A---I

•

A----I

~.P

JPACKAGE
300-MILSOJ
CASE 810A

MCM6709

~JPACKAGE

~

300-MILSOJ
CASE 810B

PIN ASSIGNMENT

AO

VCC

Al

A15

A2
AS

A13

A14

A4

A12

A5

All

A6

Al0

A7

DQO

A6

DOl

A9

D02

S

D03

VSS

W

A----t
DQO--.....-I

COLUMN I/O

:•
DQ3--.-H

!====~L-~----------------~--~
(MCM67090NLy)

\-------'
PIN NAMES

~o-A15

............ Address Inputs
G . . . . . . . . . . . . . . . . . .. Output Enable
DQO-D03 ........ Data Input/Output
VSS ...................... Ground

W ................... Write Enable

S ...................... Chip Select

Vgc ...........
N

+ 5 VPower Supply

. . . . . . . . . . . . . . . . . .. No Connect

All power supply and ground pins must be connected for proper operation of the device.
This document contains information on a

new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
5-198

NC

VCC

AO

A15

Al

A14

A2

A13

AS

A12

A4

All

A5

Al0

A6

NC

A7

NC

A6

DQO

A9

DOl

S

DQ2

G

D03

Vss

W

MCM67OS·MCM6709

TRUTH TABLE
S

G

W

Mode

I/O Pin

Cycle

H

X

X

Not Selected

High-Z

L

H

H

Read

High-Z

-

L

L

H

Read

Dout

Read Cycle

L

X

L

Write

Din

Write Cycle

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to this high-impedance circuit.

X = Dont Care
ABSOLUTE MAXIMUM RATINGS (See Note)
Rallng

Symbol

Power Supply Voltage
Voltage Relative to VSS
(For Any Pin Except Vcel
Output Current (per I/O)
Power Dissipation
Temperature Under Bias
Operating Temperature
Storage Temperature -

Value

Unit

VCC

-0.5to 7.0

V

Yin, Vout

- 0.5 to VCC + 0.5

V

lout

± 30

mA

Po

2.0

W

Tbias

-10 to + 85

°C

'Oto+70

°C.

TA
Plastic

This BICMOS memory circuit has
been designed to meet the dc and ac
specifications shown in the tables,
aiter thermal equilibrium has been
established. The circuit is in a test
socket or mounted on a printed
circuit board and transverse air flow
of at least 500 linear feet per minute
is maintained.

•

-55to+125

°C
Tstg
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(V ce = 5.0 V ± 10%, TA = 0 to + 70 o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC + 0.3*

V

- OS'

-

O.S

V

Parameter

.

Input Low Voltage

VIL
VIH (max) = VCC + 0.3 V dc, VIH (max) = VCC + 2 V ac (pulse width:;; 2 ns) or I :;; 30 mAo
"VIL (min) = - 0.5 V dc; VIL (min) = - 2 V ac (pulse width:;; 2 ns) or I :;; 30 mAo

Unit

DC CHARACTERISTICS
Parameter

= 0 to VCC)
Output Leakage Current (S = VIH, Vout = 0 to VCC)
AC Supply Current (lout = 0 mAl

Symbol

Input Leakage Current (All Inputs, Yin

= + 8.0 mAl
Output High Voltage (lOH = - 4.0 mAl
Output Low Voltage (IOL

CAPACITANCE (f

Ilkg(O)

-

ICC

Ilkg(l)

MCM670S-10/MCM6709-10:tAVAV = 10 ns
MCM6708-121MCM6709-12: tAVAV = 12 ns

Min

Max

Unit

±1

I'A

±1

I'A

-

mA

-

175
165

VOL

-

0.4

V

VOH

2.4

-

V

= 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic

Address Input Capacitance
Control Pin Input Capacitance (S, G. W)
InpuVOutput Capacitance

MOTOROLA MEMORY DATA
5-199

Symbol

Max

Unit

Cin

5

pF

Cin

6

pF

CliO

6

pF

MCM6708·MCM6709

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee 5.0 V ± 10%, TA 0 to + 70 oe, Unless Otherwise Noted)

=

=

Input Timing Measurement Reference Level ........ 1.5 V
Input Pulse Levels. . . . . . . . . . . .. . . . . . . . . . . . . .. 0 to 3.0 V
Input Rise/Fall Time .............................. 3 ns

Output Timing Measurement Reference Level ....... 1.5 V
Output Load ............................ See Figure 1A

READ CYCLE TIMING (See Notes 1 and 2)
Symbol

Parameter

•

MCM6708-10
MCM6709-10

MCM6706-12
MCM6709-12

Standard

Altemate

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

tRC

10

-

12

-

ns

3

Address Access Time

tAVQV

tAA

-

10

-

12

ns

Chip Select Access Time

tSLQV

tACS

-

10

-

12

ns

Output Enable Access Time

tGLQV

toE

-

6

-

7

ns

Output Hold from Address Change

tAXQX

tOH

3

3

tSLQX

tLZ

0

Output Enable Low to Output Active

tGLQX

tLZ

0

0

-

ns

Chip Select Low to Output Active

-

tHZ

0

5

0

0

5

0

Chip Select High to Output High-Z

tSHQZ

Output Enable High to Output High-Z

0

ns

4,5,6

ns

4,5,6

6

ns

4,5,6

6

ns

4,5,6
tHZ
'GHQZ
NOTES:
1. Wis high for read cycle.
2. Productsensitivijies to noise require proper grounding and decoupling of powersupplies as well as minimization or elimination of bus contention
condijions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given vo~age and temperature, tSHQZ max is less thantSLQX min, and'GHQZ max is less than 'GHQX min, both for agiven device and
from device to device.
5. Transition is measured 500 mV from steady-state voltage wijh load of Figure lB.
6. This parameter is sampled and not 100% tested.

READ CYCLE 1 (See Note)
tAVAV --------~
A(ADDRESS)

r------

------~I'~----------------------------~I
tAXQ'v----;~

______

Q(DATAOUT)

~"""""...".."....,..."""""...".."""""

PREVIOUS DATA VALID
~-----------JI

NOTE: Device is continuously selected (8 = VIL, G = VII).

MOTOROLA MEMORY DATA

5-200

DATA VALID

MCM6708-MCM6709

READ CYCLE 2 (See Note)
tAVAV

-*

A (ADDRESS)

~ tSLQV

J'~

S (CHIP SELECT)

I+-G(OUTPUT ENABLE)

ISLQX-

1

'T\
IGLQV!+-IGLQX--

Q(DATAOUn

~

tSHOZ

tGHOZ

DATAVALtD

tAVQV

•

NOTE: Addresses valid prior to or coincident with S going low.

AC TEST LOADS

OUTPUT

TIMING LIMITS
The table of timing values shows either
a minimum or a maximum limit for each
parameter. Input requirements are specified from the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that much time (even though most
devices do not require it). On the other
hand, responses from the memory are
specified from the module point of view.
Thus, the access time is shown as a maximum since the module never provides
data laler than that time.

~Y_~-Zo-=5-0-n----'1l
Figure 1A

+5V
480

Q-p------+

255

5 pF
(INCLUDING
SCOPE AND JIG)

Figure 1B

MOTOROLA MEMORY DATA
~201

MCM6708-MCM6709

WRITE CYCLE 1 (iN Controlled, See Notes 1 and 2)
MCM6708-1D
MCM67D9-1D

Symbol
Parameter

Standard

Write Cycle lime

•

tAVAV

MCM6708-12
MCM67D9·12

Alternate

Min

Max

Min

Unit

Notes

twc

10

-

12

-

ns

3

a

-

ns

-

ns

6

ns

4,5,6

-

ns

4,5,6

Address Setup lime

tAVWL

tAS

a

Address Valid to End of Write

tAVWH

tAW

9
8

Write Pulse Width

twLWH
twLSH

twP

Data Valid to End of Write

tOVWH

tow

5

Data Hold lime

twHOX

tOH

Write Low to Data High-Z

tWLQZ

twz

Write High to Output Active

tWHQX

tow

a
a
a

Write Recovery lime

twHAX

twR

0.5

-

10
9

6

-

a
a
a

-

0.5

5

Max

ns
ns

ns

ns

NOTES:
1. A write occurs during the overlap of S low and W low.
2. Productsensitivities to noise require propar grounding and decoupling of power supplies as well as minimization or elimination of bus contention
conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. Transition is measured 500 mV from steady-state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, twLQZ max is less than twHQX min both for a given device and from device to device.

WRITE CYCLE 1
tAVAV
A (ADDRESS)

----------+1

,...---

______jl'~----------------------------------JI
tAVWH --------+l~""* twHAX

S (CHIP SELECn
~------twLWH-----~

twLSH ----~:!----

W(WRITE ENABLE)
~--- tDVWH----+t-"'*

DATA VALID

HIGH-Z

Q (DATA QUn _ _ _--!.H""IG"'H""-Z'--_ __

MOTOROLA MEMORY DATA

6-202

MCM6708·MCM6709

WRITE CYCLE 2 (8 Controlled, See Notes 1 and 2)
Symbol

MCM6708-10
MCM6709·10

MCM6708-12
MCM6709-12

S1andard

Alternate

Min

Max

Min

Max

Unit

Notes

WrHe Cycle Time

tAVAV

twc

10

12

ns

3

Address Setup Time

tAVSL

tAS

0

9

-

Parameter

Address Valid to End of Write

tAVSH

tAW

9

Chip Select to End of Write

tSLSH
tSLWH

lew

8

-

Oata Valid to End of Write

tOVSH

tow

5

-

6

-

ns

tOH

0

-

0

-

ns

twR

0.5

-

0.5

-

ns

Oata Hold Time

tSHOX

Write Recovery Time

tSHAX

0
10

ns
ns
ns

4,5

NOTES:
1. A write occurs during the overlap of S low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. All wrHe cycle timing is referenced from the last valid address to the first transitioning address.
4. If S goes low coincident with or after Wgoes low, the output will remain in a high-impedance condition.
5. If S goes high coincident with or before Wgoes high, the output will remain in a high-impedance condition.

WRITE CYCLE 2
tAVAV
A(AOORESS)
IAVSH

4

'SLSH

S (CHIP SELECn
tsLWH

'AVSL

'SHAX

W(WRITE ENABLE)

_t:::=

tOVSH

-""'""'mxxxxx

o(OATA IN)"X"'XXX~X~X"'X"'XX~X"7rX"'X"'XX""X~X"7rX"'X"'XX""XX""A?XCO"-JAIl-ALI-O

----.J .~tsHOX

Q(OATAOUn _ _ _ _ _ _ _ _ _ _ _ _ _ _. . . wH""IG.. ,H.;.,Z_ _ _ _ _ _ _ _ _ _ _ _ _ __

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory

6708

prefiX~

Part Number
Package (J = Plastic SOJ)

T1
x

xx

xx

T

............. '''--"'., ,.". """'
Speed (10 = 10 ns, 12 = 12 ns)

---------1

Full Part Numbers - MCM6708J10
MCM6708J12

MCM6708Jl0R2
MCM6708J12R2

MCM6709Jl0
MCM6709J12

MCM6709Jl0R2
MCM6709J12R2

MOTOROLA MEMORY DATA
5-203

II

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM6708A
MCM6709A

Product Preview
64K x 4 Bit Static RAM

MCM6708A

The MCM6708A and the MCM6709A are 262,144 bit static random access
memories organized as 65,536 words of 4 bits, fabricated using high-performance
silicon-gate SICMOS technology. Static design eliminates the need for external .
clocks or timing strobes.
Output enable, (G), a special control feature of the MCM6709A, provides
increased system flexibility and eliminates bus contention problems.
The MCM6708A is available in a 300 mil, 24 lead plastic surface-mount SOJ
package. The MCM6709A is available in a 300 mil, 28 lead plastic surface-mount
SOJ package.

•

•
•
•
•
•

4fi
MCM67D9A

~JPACKAGE
~
PIN ASSIGNMENT
MCM6708A
AO

A---I

•

A-----1
A---I

A----i

ROW
DECODER

•

A-----1

MEMORY MATRIX
256 ROWS x 256 x 4
COLUMNS

12

A2

3

22

A3

4

21

A4

5

AS

23

~ VCC
~ A15

~ A14
~ A13
20 D A12

~

6

19

As[ 7

18

Ad 8

17 D DOO

A8 [ 9

16

DOl

A9 [ 10

15

D02

11

14

D03

VSS [ 12

13

W

A-----I

~

All
Al0

MCM67D9A

000--""';

••
•
D03--.-H

~====~~~-----------------+--~
(MCM6709AONLY)

1-------'

PIN NAMES
~O-A 15

24

Al

E[

•

A---I

J PACKAGE
300MILSOJ
CASE 810A

3OOMILSOJ
CASE 81 DB

Single 5 V ± 10% Power Supply
Fully Static - No Clock or Timing Strobes Necessary
All Inputs and Outputs are TTL Compatible
Three State Outputs
Fast Access Times:
MCM6708A - 8 ns
MCM6709A - 8 ns
MCM6708A - 10 ns
MCM6709A - 10 ns
MCM6708A - 12 ns
MCM6709A - 12 ns
BLOCK DIAGRAM

A-----i

i

... . . . . . . . .. Address Inputs
G . . . . . . . . . . . . . . . . . .. Output Enable
DOO-D03 ........ Data InpuVOutput
VSS ...................... Ground

W ................... Write Enable

E ...................... Chip Select
VCC ............ +5 V Power Supply
NC ................... No Connect

All power supply and ground pins must be connected for proper operation of the device.
This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA

5-204

NC

1-

28

AO

2

27

Al

3

D VCC
~ A1S
26 ~ A14

A2

4

25

D A13

A3 [ 5

24

D A12

~

A4[ 6

23

AS [ 7

22

Al0

A6 [ 8

21

NC

Ad 9

20

NC

A8 [ 10

19

DOO

A9 [ 11

18

DOl

E r 12
G 13

17

D02

16

D03

14

15

VSS

All

~ W

MCM6708A-MCM6709A

TRUTH TABLE

E

G

W

Mode

1/0 Pin

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to this high impedence circuit.

Cycle

H

X

X

Not Selected

High-Z

-

L

H

H

Read

High-Z

-

L

L

H

Read

Dout

Read Cycle

L

X

L

Write

Din

Write Cycle

X = Don't Care
This BICMOS memory circuit has
been designed to meet the dc and ac
specifications shown in the tables,
after thermal equilibrium has been
established. The circuit is in a test
socket or mounted on a printed
circuit board and transverse air flow
of at least 500 linear feet per minute
is maintained.

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-0.5to 7.0

V

Yin, Vout

- 0.5 to VCC + 0.5

V

Output Current (per 110)

lout

± 30

mA

Power Dissipation

Po

2.0

W

Tbias

-10to+85

°C

TA

oto + 70

°C

Tst9

-55to + 125

°C

Power Supply Voltage
Voltage Relative to VSS
(For Any Pin Except VCe)

Temperature Under Bias
Operating Temperature
Storage Temperature -

Plastic

II

. NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, T A = 0 to + 70 oe, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC + 0.3'

V

Input Low Voltage

VIL

-0.5"

-

0.8

V

,

VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width" 2 ns) for I" 20 mA.
"VIL (min) = - 1 V dc @ 30 mA; VIL (min) = - 2 V ac (pulse width" 2 ns).
DC CHARACTERISTICS
Parameter

Symbol

= 0 to VCC)
Output Leakage Current (E = VIH, Vout = 0 to VCC)
AC Supply Current (lout = 0 mAl
MCM6708-10/MCM6709-8:
Input Leakage Current (All Inputs, Yin

tAVAV
MCM6708-1 0/MCM6709-1 0: tAVAV
MCM6708-121MCM6709-12: tAVAV

Output Low Voltage (lOL = + 8.0 mAl
Output High Voltage (IOH

=-

4.0 mAl

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA

Ilkg(l)
Ilkg(O)

= 8 ns
= IOns
= 12 ns

ICC

Min

Max

Unit

-

±1

JlA
JlA

-

VOL

-

VOH

2.4

±1
185
175
165

mA

0.4

V

-

V

= 25°C, Periodically Sampled Rather Than 100% Tested)

Characteristic

Symbol

Max

Address Input Capacitance

Cin

6

pF

Control Pin Input Capacitance (E, G. W)

Cin

8

pF

Input/Output Capacitance

CliO

8

pF

MOTOROLA MEMORY DATA
5-205

Unit

MCM6708A-MCM6709A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee

=5.0 V ± 10%, TA =0 to + 70°C, Unless Otherwise Noted)

Input TIming Measurement Reference Level ........ 1.5 V
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 3.0 V
Input Rise/Fall TIme .............................. 3 ns

Output TIming Measurement Reference Level . . . . . .. 1.5 V
Output Load ............................ See Figure 1A

READ CYCLE TIMING (See Notes 1 and 2)
Symbol

MCM6708A·l0
MCM6709A·l0

MCM6708A·12
MCM6709A·12

Standard

Alternate

MIn

Max

MIn

Max

Min

Max

UnIt

Notes

Read Cycle Time

tAVAV

tRC

8

-

10

-

12

-

ns

3

Address Access Time

tAVOV

tAA

8

ns

tACS

12

ns

toE

-

4

-

12

tELOV

-

10

Chip Enable Access Time

-

7

ns

tAXOX

tOH

4

4

tELOX
'GLOX

tLZ

0

0

0

-

ns

4

-

4

tLZ

-

Chip Enable High to Output High-Z

tEHOZ

tHZ

0

4

0

5

0

Output Enable High to Output
High-Z

'GHOZ

tHZ

0

4

0

5

0

Parameter

Output Enable Access Time

II

MCM6708A-8
MCM6709A-8

'GLOV

Output Hold from Address Change
Chip Enable Low to Output Active
Output Enable Low to Output Active

8

4

10
5

4

ns

4,5,6

ns

4,5,6

6

ns

4,5,6

6

ns

4,5,6

NOTES:
1. Wis high for read cycle.
2. Productsensijivities to noise require proper grounding and decoupling of powersupplies as well as minimization orelimination ofbuscontention
conditions during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHOZ max is less than tELOX min, and 'GHOZ max is less than 'GHOX min, both for a given device and
from device to device.
'
5. Transition Is measured 500 mV from steady-state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.

READ CYCLE 1 (See Note)
tAVAV
A(ADDRESS) ______

JI'~

---------+/

____________________________

Q(DATAOUT)

J"~

__________

DATA VALID

-------4-----------J"~~~~~~~

NOTE: Device is continuously selected (e = VIL, G = VIU,

MOTOROLA MEMORY DATA

5-206

MCM6708A-MCM6709A

READ CYCLE 2 (See Note)
tAVAV
A (ADDRESS)
-

tELOV

l-

E(CHIP ENABLE)

.~

+ - tELOX-

G(OUTPUT ENABLE)

{

t
tGLOV!+-lGLOX......

o(DATA OUT)

..

I

rxx'tl:

tEHOZ

tGHOZ

DATAVAUD

tAVOV

NOTE: Addresses valid prior to or coincident with E going low.

II

AC TEST LOADS

OUTPUT

TIMING LIMITS
The table of timing values shows either
a minimum or a maximum limit for each
parameter. Input requirements are specified from the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that much time (even though most
devices do not require it). On the other
hand, responses from the memory are
specified from the module point of view.
Thus, the access time is shown as a maximum since the module never provides
data later than that time.

D-Oy'--___--1~=>---].
I
lo=50Q -?
{
Figure 1A

+5V

480

0---1----+
255

==

5pF
(INCLUDING
SCOPE AND JIG)

Figure 18

MOTOROLA MEMORY DATA

5-207

MCM6708A-MCM6709A

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
MCM6708A-8
MCM6709A-8

MCM6708A-10
MCM6709A-10

Alternate

Min

Max

Min

Max

Min

Max

Unit

Notes

twc

8

-

10

-

12

3

9

-

ns

ns

Symbol
Parameter

Standard

Write Cycle Time

•

tAVAV

Address Setup Time

tAVWL

tAS

0

Address Valid to End of Write

tAVWH

tAW

8

0
9

MCM6708A-12
MCM6709A-12

0
10

ns
ns

Write Pulse Width
G High, GLow.

tWLWH
twLEH

twp

8

Data Valid to End of Write

tOVWH

tow

4

-

tOH

0

0

-

6

twHOX

-

5

Data Hold Time

0

-

ns

Write Low to Data High-Z

twLQZ

twz

0

4

0

5

0

6

ns

4,5,6

Wrije High to Output Active

twHQX

tow

4

4

-

4

4,5,6

twHAX

tWR

0

0

-

0

-

ns

Wrije Recovery Time

-

9

ns

ns

NOTES:
1. A wrije occurs during the overlap of E low and Wlow.
2. Productsensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention
conditions during read and write cycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. Transition is measured 500 mV from steady-state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. At any given voltage and temperature, tWLQZ max is less than twHQX min both for a given device and from device to device.

WRITE CYCLE 1

---""\
A (ADDRESS)

1 + - - - - - - - - - - - tAVAV

----------+1

_ _ _oJ

tAVWH .-------_14--+1- twHAX

E(CHIP ENABLE)
1+-------twLWH-----~

twLEH ---I~

___

W(WRITE ENABLE)

1+---- tDVWH----+l-""*
D(DATAIN)L..l.I...lL,.;IL..l£..lL,.;IL..l£..lL,.;IL..l£~lL...lI~lL...lI~lL...lI~ '--_ _ _ _DA_:t:_AV_A_Ll_D_-..,.---JI\L..:~~~

HIGH-Z

Q (DATA OUT) _ _ _--"H"'IG""H-....
Z_ _ __

MOTOROLA MEMORY DATA
5-208

MCM6708A·MCM6709A

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
Symbol
Parameter

MCM670BA-8
MCM6709A-8

MCM6708A-l0
MCM6709A-l0

MCM6708A-12
MCM6709A-12

Standard

Altarnate

Min

Max

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

twc

8

10

-

ns

3

tAVEl

tAS

0

-

12

Address Setup Time

-

0

-

ns

10

-

ns

9

-

ns

-

6

-

ns

Address Valid to End of Write

tAVEH

tAW

8

Chip Enable 10 End of Write

tElEH
tElWH

lew

6

Data Valid to End of Write

tOVEH

tow

4

tOH

0

Data Hold Time

tEHOX

0
9
7

-

5
0

0

4,5

ns

Write Recovery Time
ns
0
0
0
tEHAX
twR
NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. Productsensilivities to noise require proper grounding and decoupling of power supplies as well as minimization orelimination of bus contention
conditions during read and write eycles.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after Wgoes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before Wgoes high, the output will remain in a high impedance condition.

WRITE CYCLE 2
IAVAV
A(ADDRESS)

•

IAVEH

•

tELEH

E(CHIP ENABLE)
tAVEL

tELWH

tEHAX

W(WRITE ENABLE)

_t==

tOVEH

o(DATA IN)"""'XX"""'X"""X"""'X""""XX"""'X"""X"""'X""""XX"""X."...,X,.....,.XX,...,..X..,...X,.....,X.....,.,XXX....,....,,~-DAt-AV-ALI-D-""'"'*XXXXXXX

----1' ~tEHDX
Q(DATAOUT)_ _ _ _ _ _ _ _ _ _ _ _ _ _-"H""IG"'H--"-Z_ _ _ _ _ _ _ _ _ _ _ _ _ __

ORDERING INFORMATION

(Order by Full Part Number)
MCM

Motorola Memory

prefiX~

6708A
6709A

T TT
x

xx

xx

,"-""""",._"..,_.,.",
Speed (8=8ns, 10=10ns,12 = 12ns)

Part N u m b e r - - - - - - - - - - - '
Package (J = Plastic SOJ) - - - - - - - - - '

Full Part Numbers: MCM6708AJ8
MCM6708AJ10
MCM6708AJ12

MCM6708AJ8R2
MCM6708AJ10R2
MCM6708AJ12R2

MCM6709AJ8
MCM6709AJ10
MCM6709AJ12

MCM6709AJ8R2
MCM6709AJ10R2
MCM6709AJ12R2

MOTOROLA MEMORY DATA
5-209

II

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6726

Product Preview
128K x 8 Bit Fast Static Random
Access Memory
The MCM6726 is a 1,048,576 bit static random access memory organized as
131,072 x 8 bits. This device is fabricated using high-performance silicon-gate
BiCMOS technology. Static design eliminates the need for external clocks or timing
strobes.
Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems.
This device meets JEDEC standards for functionality and revolutionary pinout, and is
available in a 400-mil plastic small-outline J-Ieaded package.

•

•
•
•
•
•
•

Single 5 V ±10% Power Supply
Fully Static - No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TIL-Compatible
Three-State Outputs
Fast Access Times: 10, 12 ns
Center Power and 1/0 Pins for Reduced Noise

BLOCK DIAGRAM

Vee
Vss

·•

MEMORY
MATRIX
512 ROWS x 256 x 8
COLUMNS

. ,WJ PACKAGE
400-MILSOJ
CASE857A

PIN ASSIGNMENT

A 1·

32

PA

A

2

31

A

3

30

PA
PA

A

4

29

PA

E

5

28

DOD

6

001

7

Vee

8

Vss

9

002

10

PG
27 P007
26 P006
25 PVss
24 PVee
23 P005

11

22

P004

W

12

21

A

A

13

20

A

A

14

19

A

A

15

18

A

A

16

17

A

003

PIN NAMES
• eOLUMNl/O

AO-A 16 ............... Address Input
E .. .. .. .. .. .. .. .. .. .... Chip Enable
W ..................... Write Enable
G ................... Output Enable
DOa-D07 . . . . . . . .. Data InpuVOutput
VCC ............ + 5 V Power Supply
VSS ....................... Ground

W===~~r-----------+--------'.
G

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
5-210

MCM6726

TRUTH TABLE (X = Don't Care)
E

G

W

Mode

VCCCurrent

Output

Cycle

H

X

X

Not Selected

ISBI,ISB2

High-Z

L

H

H

Output Disabled

ICCA

High-Z

-

L

L

H

Read

ICCA

L

X

L

Write

ICCA

Dout
High-Z

Read Cycle
Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VCC

-0_510+7.0

V

Yin, Vout

- 0.5 to VCC + 0.5

V

Output Current

lout

±30

mA

Power Dissipation

Po

1.2

W

Tbias

-IOto+85

°c

TA

o to +70

°c

Power Supply Vonage
Voltage Relative to VSS lor Any Pin Except
VCC

Temperature Under Bias (TA = 25"C)
Operating Temperature

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric lields; however, it is advised
that normal precautions be taken to avoid
application 01 any vottage higher than maximum rated voltages to these high-impedance circuits.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications shown in the tables, aiter thermal equilibrium has been established. The circuit is in
a test socket or mounted on a printed circuit
board and transverse air Ilow 01 at least SOD
linear leet per minute is maintained.

Storage Temperature-Plastic

-55to+125
°c
Tsta
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to the OPERATING CONDITIONS. Exposure to higher than recommended voltages lor extended periods 01
time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, T A = 0 to +70 o e, Unless Otherwise Noted)
Parameter

Symbol

Typ

Min

Max

Unit

5.0

4.5

5.5

Input High Voltage
Input Low Voltage

VCC
VIH
VIL

-

2.2
-0.5"

V
V

Input Leakage Current (All Inputs, Yin = 0 to Vccl

Ilkg(l)

-

VCC+ 0.3•
0.8
±I.O

Output Leakage Current (E = VIH, Vout = 0 to VCC)
Output Low Voltage (lOL = + 8.0 mAl

Ilka(O)
VOL

-

±I.O
0.4

Supply Voltage (Operating Voltage Range)

-

Output High Voltage (1m =- 4.0 mAl
VOH
'VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse WIdth ~ 20 ns) lor I S 20.0 mAo
"VIL (min) = - 0.5 V dc; VIL (min) = - 2.0 V ac (pulse width S 20 ns) lor I S 20.0 mA.

-

-

2.4

V

!LA
!LA
V
V

DC CHARACTERISTICS
Symbol

-10

-12

AC Active Supply Current (lout = 0 mAl (VCC = max, I = Imax)
Active Quiescent Current (E = VIL, VCC = max, I = 0 MHz)

ICCA
ICC2

175
100

165
100

AC Standby Current (E = VIH, VCC = max, I = Imax)
CMOS Standby Current
C = max, I = 0 MHz, E ~ VCC - 0.2 V,
Yin ~VSS + 0.2 V, or~ CC-0.2 V)

ISBI

35

30

Unit
mA
mA
mA

ISB2

12

12

mA

Parameter

('W

CAPACITANCE (I = 1 0 MHz dV = 3 0 V TA = 25°C Periodically Sampled Rather Than 100% Tested)
Symbol
Parameter
Address and Data Input Capacitance
Cin
Control Pin Input Capacitance
Cin
Output CapaCitance
Cnut

MOTOROLA MEMORY DATA

5-211

Typ

-

Max
6

-

6
8

-

Unit
pF
pF
pF

•

MCM6726

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to +70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall TIme ..................................... 2 ns

Output TIming Measurement Reference Level ............. 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. See Figure 1A

READ CYCLE TIMING (See Notes 1 and 2)
Symbol

Parameter

..

Standard

-12

-10

Alternate

Min

Max

Min

-

12

Units

Max

Read Cycle TIme

tAVAV

tRC

10

-

ns

Address Access TIme

tAVOV

tAA

-

10

-

12

ns

10

-

12

ns

5

6

ns

Notes
3

Enable Access TIme

tELOV

tACS

Output Enable Access TIme

tGLOV

toE

-

Output Hold from Address Change

tAXOX

toH

3

-

3

-

ns

Enable Low to Output Active

tELOX

teLZ

3

-

3

-

ns

4,5,6

Output Enable Low to Output Active

tGLOX

toLZ

0

-

0

-

ns

4,5,6

Enable High to Output High-Z

tEHOZ

tCHZ

0

5

0

6

ns

4,5,6

Output Enable High to Output High-Z
ns
4,5,6
0
5
0
6
tOHZ
'GHOZ
..
NOTES: 1. W IS high for read cycle .
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All read cycle timings are referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHOZ max < tELOX min, and tGHOZ max < tGHOX min, both for a given
device and from device to device.
5. Transition is measured ± 200 mV from steady-state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = VIL, G = VIU.
8. Addresses valid prior to or coincident with E going low.

READ CYCLE 1 (See Note 7)

t------------

A (ADDRESS)

~

)j\

ttAX;;OX~====~.~I~------------~------------~

-------Q(DATAOUT)

~I

tAVAV

PREVIOUS DATA VALID

~------

DATA VALID

1 4 - - - - - - - tAVQV

READ CYCLE 2 (See Note 8)
tAVAV
A (ADDRESS)

E (CHIP ENABLE)

\!
},
tELQV

\

tEHQZ"

"

+--tELQX -

G(OUTPUT ENABLE)

'I

tGLQV..... 'GLOX Q(DATAOUT)

!XXX)QK

tAVQV

MOTOROLA MEMORY DATA
5-212

{.~
DATA VALID

\

/

MCM6726

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
Symbol

Parameter

·10

Standard

Alternate

Min

Write Cycle lime

tAVAV

twc

10

Address Setup Time

tAVWL

tAS

0

·12
Max

Units

Min

Max

12

-

ns

0

ns

7

-

8

-

ns

-

ns

Notes

Address Valid to End of Write

tAVWH

tAW

6

Write Pulse Width

twLWH
twLEH

twp
twp

7

-

Write Pulse Width, G High

tWLWH
tWLEH

twp
twp

6

-

7

Oata Valid to End of Write

tOVWH

tow

5

-

ns

twHOX

tOH

0

-

6

Oata Hold lime

0

-

ns

Write Low to Oata High-Z

twLQZ

twz

0

5

0

6

ns

4,5,6

Write High to Output Active

twHQX

tow

4

-

4

-

ns

4,5,6

ns

0
ns
0
twHAX
twR
A write occurs during the overlap of E low and W low.
For common 1/0 applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
All write cycle timings are referenced from the last valid address to the first transitioning address.
Transition is measured ± 200 mV from steady-state voltage with load of Figure 1B.
This parameter is sampled and not 100% tested.
At any given voltage and temperature, tWLQZ max <: tWHQX min both for a given device and from device to device.

Wrtte Recovery lime
NOTES: 1.
2.
3.
4.
5.
6.

3

WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
Symbol

Parameter

·12

·10

Standard

Alternate

Min

Write Cycle lime

tAvAV

twc

10

Address Setup lime

tAVEL

tAS

0

Address Valid to End of Write

tAVEH

tAW

7

Enable to End of Write

tELEH

tcw

7

Enable to End of Write

tELWH

tcw

7

Oata Valid to End of Write

tOVEH

tow

5

Oata Hold lime

tEHOX

Max

3.
4.
S.

-

-

Notes

-

ns

3

-

ns

-

ns

-

ns

4,5

ns

4,5

-

ns

Max

12
0
8
8
8
6

ns
0
0
tOH
ns
0
0
tEHAX
tWR
A write occurs dunng the overlap of E low and W low.
For common 1/0 applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
All write cycle timings are referenced from the last valid address to the first transitioning address.
If E goes low coincident with or after IN goes low, the output will remain in a high impedance condition.
If E goes high coincident with or before IN goes high, the output will remain in a high impedance condition.

Write Recovery lime
NOTES: 1.
2.

-

-

Units

Min

AC TEST LOADS

q

TIMING LIMITS

+5V 480n

OUTPUT----Q,..."r
_ _ _ _-r~

~

ZOo

son ::1-

Figure 1A

f

RL =

son

Q

255 n

5pF
(INCLUDING
SCOPE AND JIG)

Figure 18

MOTOROLA MEMORY DATA
5-213

The table of timing values shows either
a minimum or a maximum limit for each parameter. Input requirements are specified
from the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that much time (even though most
devices do not require it). On the other
hand, responses from the memory are
specified from the device point of view.
Thus, the access time is shown as a maximum since the device never provides data
later than that time.

MCM6726

WRITE CYCLE 1
IAVAV --------~
A (ADDRESS)

14--------

IAVWH - - - - - -....f--~ IWHAX

,----:..------

E(CHIP ENABLE)

Vi (WRITE ENABLE)
IOVWH --1*--tD(DATAIN)

•

DATA VALID

HIGHZ

Q (DATA OUT) _ _.....;.H",IG;;;.H",Z_ __

WRITE CYCLE 2

IAVAV

-----------'i

A (ADORESS)

1 - - - - - - - - IAVEH - - - - - - - - - 1
IELEH - - - + /

E(CHIP ENABLE)

r---+----

/ + - - - - - IAVEL - - - -....f - - - IELWH ---014------01- IEHAX

Vi (WRITE ENABLE)
toVEH -~-~
D (DATA IN)

DATA VALID

Q(OATAOUT) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~HI~GH~Z=____ _ _ _ _ _ _ _ _ _ _ _ _ _ __

ORDERING INFORMATION
(Order by Full Part Number)
Motorola Memory Prefix

MCM

§Z26

I

I

Part Number ,,-_-'-_ _ _ _ _ _ _ _..J.

xx XX
~I

W.!

Shipping Method (R2 = Tape and Reel, Blank = Rails)
Speed (10

.

=10 ns, 12 =12 ns)

Package (WJ = 400-mil SOJ)

Full Part Number -

MCM6726WJ10
MCM6726WJ10R2

MCM6726WJ12
MCM6726WJ12R2

MOTOROLA MEMORY DATA
5-214

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - -

TECHNICAL DATA

Product Preview
1M x 1 Bit Fast Static Random

MCM6727

Access Memory
The MCM6727 is a 1,048,576 bit static random access memory organized as
1,048,576 x 1 bits. This device is fabricated using high-performance silicon-gate
SiCMOS technology. Static design eliminates the need for external clocks or timing
strobes.
This device meets JEDEC standards for functionality and revolutionary pinout, and is
available in a 400-mil plastic small-outline J-Ieaded package.
•
•
•
•
•
•

Single 5 V ±10% Power Supply
Fully Static - No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TTL Compatible
Three State Outputs
Fast Access Times: 10, 12 ns
Center Power and 1/0 Pins for Reduced Noise

WJPACKAGE
400-MILSOJ

CASE 810

PIN ASSIGNMENT

BLOCK DIAGRAM

A[ 1 •
Ar 2

27P A

A[ 3

26P A

A[ 4

25P A

A

5

24P A

Er
A

Vee
Vss

A-----.~.

A

2SP A

6

23P A

Vee
Vss

7

22

8

21

Vss
Vee

D

9

20

Q

W

10

19

A

A

11

18

A

A

12

17

A

A

A

13

16

A

A

A

14

15

A

A
A
A

MEMORY
MATRIX
512 ROWS x2048
COLUMNS

A-'-A12

AO-A12 ..... Address Inputs
LE ............ Latch Enable
W..... "' . . . . .. Write Enable
gf, E2 .......... Chip Enable
G ............ Output Enable
DOO-DQ19 Data Input/Output
Vec .... + 5 V Power Supply
VSS ................ Ground
NC ...... "' .. No Connection

ROW
DECODERS

E1. E2
LE

For proper operation of the device,
all VSS pins must be connected to
grouM.

~~~----~----------~H
0019~~----+-~--------~~~

This document contains information on a project under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
5-230

MCM62820

TRUTH TABLE
E1

E2

G

W

LE

Mode

Supply Current

1/0 Status

H

X

X

X

X

Not Selected

ISB

High-Z

X

L

X

X

X

Not Selected

ISB

High-Z

L

H

H

H

X

Output Disabled

ICC

High-Z

L

H

L

H

H

Read with Transparent Inputs

ICC

Data Out

L

H

L

H

L

Read with Latched Inputs

ICC

Data Out

L

H

X

L

H

Write with Transparent Inputs

ICC

Data In

L

H

X

L

L

Write with Latched Inputs

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
fields; however it is advised that normal precautions be taken to avoid
application of any voltage higher
than maximum rated voltages to this
high-impedance circuit.
This CMOS memory circuit has
been designed to meetthe de and ac
specifications shown in the tables.
after thermal equilibrium has been
established. The circuit is assumed
to be in a test socket or mounted on
a printed circuit board with at least
300 LFPM of transverse air flow being maintained.

Data In
ICC
NOTE. X means don t care. Inputs AO-AI2. El. E2 are latched or transparent depending upon the
state of latch enable (LE).
ABSOLUTE MAXIMUM RATINGS (Va Itages re erenced to V'88=0 V)
Rating·
Symbol
Power Supply Voltage

Value

Unit

VCC

-0.5to + 7.0

V

Voltage Relative to VSS

Yin. Vout

- 0.5 to VCC + 0.5

V

Output Current (per 1/0)

lout

±20

mA

Power Dissipation (TA = 70°C. VCC = 5 V.
tAVAV = 23 ns)

PD

2.5

W

Temperature Under Bias

Tbias

-10to+85

°c

Operating Temperature

TA

Oto+ 70

°c

Storage Temperature

II

-55to+125

°c
Tstg
NOTE. Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended voltages for extended periods of time could affect
device reliability.

DC OPERATING CONDmONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%. T A =0 to + 70o e. Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (VoItages re ferenced t o V'SS.= 0 V)
Symbol

Min

Typ

Max

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

3.0

VCC + 0.3

V

Input Low Voltage

VIL

-0.5'

0.0

0.8

V

Max

Unit

±1.0

~

Parameter

Unit

'VIL (min) = - 3.0 V ac (pulse width"; 20 ns)
DC CHARACTERISTICS
Parameter

Symbol

Input Leakage Current (All Inputs. Yin = 0 to VCC)

Ilkg(l)

Output Leakage Current (G = VIH. El = VIH. E2 = VIL. Vout = 0 to VCC)

Ilkg(O)

AC Supply Current (G = VIH. El = VIL. E2 = VIH. All Inputs = VIL = 0.0 V and VIH:<: 3.0.
lout =0 mAl
Cycle Time :<: 23 ns
Cycle Time :<: 30 ns

ICCA

Min

-

± 1.0

~
mA

Standby Current (El = VIH. E2 = VIL. All Inputs = VIL or VIH)

ISBt

CMOS Standby Current (El :<: VCC - 0.2 V. E2"; 0.2 V. All Inputs :<: VCC - 0.2 V or"; 0.2 V)

ISB2

--

Output Low Voltage (IOL = + 8.0 mAl

VOL

-

0.4

V

Output High Voltage (IOH = - 4.0 mAl

VOH

2.4

-

V

240
185
15.0

mA

10.0

mA

CAPACITANCE (f = 1 0 MHz dV = 3 0 V T A = 25°C Periodically Sampled Rather Than 100% Tested)
Characteristic
Input CapaCitance

All Pins Except DOO-OO19

InpuVOutput Capacitance

DOO-D019

MOTOROLA MEMORY DATA
5-231

Symbol

Typ

Max

Unit

Cin

4

6

pF

CliO

6

8

pF

MCM62820

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to 70o e, Unless Otherwise Noted)
Input TIming Measurement Reference Level ................ 1.5 V
Input Pulse Levels ................................... 0 to 3.0 V
Input Rise/Fall TIme .. . .. . .. .. . .. .. . .. .. .. .. . .. . . .. . .. ... 3 ns

Output Measurement Reference Level ..•................. 1.5 V
Output Load ..... ;...... See Figure I A Unless Otherwise Noted

.READ CYCLE TIMING (See Notes I , 2, 3)
Symbol

•

MCM62820-23

MCM62820-30

Standard

Alternate

Min

Max

Min

Max

Unit

Read Cycle TIme

tAVAV

tRC

23

-

30

-

ns

Address Access TIme

30

ns

30

ns

-

ns

12

ns
ns

4,5

ns

5

ns

5

Parameter

tAVQV

tAA

Chip Enable to Output Valid

tEILQV
tE2HQV

tACI

-

23

-

25

-

30

-

Latch Enable High to Output Valid

tLEHQV

Output Enable to Output Valid

IGLQV

toE

Output Active from Chip Enable

tEILQX
tE2HQX

leLZ

2

Output Active from Output Enable

tGLQX

toLZ

2

Output Active from Latch Enable High

tLEHQX

Output Hold from Address Change

tAXQX

JJ
JJ

Setup TImes For:

EI
E2

Hold TImes for:

EI
E2

Chip Enable High to Output High-Z

23

10

-

2

-

tOH

3

-

3

tAVLEL
tEtVLEL
tE2VLEL

tAS
les
les

4

-

4

-

tLELAX
tLELEIX
tLELE2X

tAH

3

-

3

tCHZ

0

tEIHQZ
tE2LQZ

~~

9

Latch Enable High to Output High-Z
9
0
tLEHQZ
tcHZ
Output Enable to Output High-Z
0
8
tGHQZ
toHZ
NOTES.
_
.
I. A read cycle is defined by W high.
2. All read cycle timings are referenced from the last v.llli.d address to the first transitioning address.
3. &!dresses must be valid prior to or coincid.l!!.t with EI goilKl.low or E2 going high.
4. EI in the timing diagrams represents both EI and E2 with l':1 asserted low and E2 asserted high.
5. Transition is measured ± 500 mV from steady-state voltage w~h load of Figure I B. This parameter
is sampled and not 100% tested. At any given voltage and temperature. tEl ~Z max is less than
tlJJ-.P&~~~ ~~§1~~~~i~~~~~~~~E2HQX min and tGHQZ max is less an IGLQX min for a
6. ~ese inputs are latched and must meet the required setup and hold times for ALL latch enable
(LE) low transitions.
READ CYCLE

2
2
2

Notes

4

ns
ns

4,6

-

ns

4,6

0

10

ns

4,5

0

10

ns

5

0

10

ns

5

A (ADDRESS)

1 4 - - - - - tLEHQZ ----+--1
LE (LATCH ENABLE)

E1(CHIP ENABLE)

G(OUTPUT ENABLE)

Q (DATA OUT)

MOTOROLA MEMORY DATA

5-232

MCM62820

WRITE CYCLE TIMING Write Enable Initiated (See Note 1)
Symbol
Parameter

Write Cycle Time

MCM62820-23

Standard

Alternate

Min

tAVAV

twc

23

Max

-

MCM6282~O

Min

Max

Unit

30

-

ns

-

ns

Notes

Address Setup Time

tAVWL

tAS

0

Address Valid to End of Write

tAVWH

tAW

20

Write Pulse Width

tWLWH

twp

15

-

18

-

ns

3

Write Enable to Chip Enable Disable

twLE1H
twLE2L

tcw

15

-

18

-

ns

4

Chip Enable to End of Write

tE1LWH
tE2HWH

tcw

15

-

18

-

ns

3,4,5

Data Valid to End of WrHe

-

ns

0
25

tDVWH

tow

7

twHDX

tDH

0

-

10

Data Hold Time
Write Recovery Time

twHAX

twR

0

-

0

tAVLEL
tEtVLEL
tE2VLEL

tAS
tcs
tcs

4

-

-

4

tWHLEH

tLEH

-2

tLELAX
tLELE1X
tLELE2X

tAH
tCH
tcH

3

-

twLOZ

twHZ

0

9

Setup Times for:

-A
El
E2

LE Hold to End of Write
Hold Times for:

-A
El
E2

Write Low to Output High-Z

Write High to Output Low-Z
2
twHOX
twLZ
NOTES.
_
_
1. A write cycle starts at th~atest lliInsition of El low, W low, or E2 high. A write cycle ends at the
earliest transition of an El high W high, or E2 low.
2. WIi!e must be hi\lh for all address transitiQrls.
3.
If W \loes low coincident with or prior to El low or E2 high the outputs will remain in a
!!igh-Impedance state.
__
4.
El in the timing diagrams represents both El and E2 with Et asserted low and E2 asserted high.
5. These inputs are latched and must meet the required setup and hold times for ALL latch enable
(LEllow transitions.
6.
DUring this time the output pins may be in the output state. Signals of opposite phase must not be
applied to the outputs at this time.
7. Transition is measured 500 mV from steady-state voltage with load of Figure 1B. This parameter
is sampled and not 100% tested. At any given voltage and temperature, tEl HOZ max is less than
tEl LOX Il)in, tE2LOZ max .is less than tE2HOX min and 'GHOX max is less tnan 'GLOX min for a
given cevlce andlrom device to device.

±

WRITE ENABLE INITIATED WRITE CYCLE

A (ADDRESS)

LE (LATCH ENABLE)

IT (CHIP ENABLE)
Vi (WRITE ENABLE)
D (DATA IN)

Q(DATAOUT)

1------ tWLElf<------t

MOTOROLA MEMORY DATA
5-233

2

ns

ns

6

ns

2

-

ns

4,5

-2

-

ns

3

-

ns

4,5

0

10

ns

7

2

-

ns

7

0

..

MCM62820

WRITE CYCLE TIMING, Chip Enable Initiated (See Notes 1 and 2)
Symbol

MCM62820-30

Alternate

Min

Min

Max

Unit

tAVAV

!wc

23

-

30

ns

Address Setup Time

tAVE1L
IAVE2H

tAS

0

-

0

Address Valid to End of Write

~VE1H
AVE2L

tAW

20

-

25

Data Valid to End of Write

tDVE1H
tDVE2L

tDW

7

-

10

Chip Enable to End of Write

lE1LE1H
E2HE2L

tcw

15

18

ns

3

Data Hold Time

tE1HDX
tE2LDX

tDH

0

0

-

ns

4

Write Recovery Time

tE1HAX
tE2LAX

tWR

0

0

-

ns

LE Hold to End of Write

tE1HLEH
tE2LLEH

tE1HLEH
tE2LLEH

-2

-2

-

ns

tAVLEL
tE1VLEL
tE2VLEL

tAS
ICS
tcs

4

-

-

4

-

ns

5

3

-

ns

5

Write Cycle Time

..

MCM62820-23

Standard

Parameter

Setup Times for:

2,
El
E2

Max

3
tLELAX
tAH
tLELE1X
tcH
tCH
tLELE2X
NOTES:
_
_
1. A write cycle starts at thJ!Jatest 1!:§nsition of El low, W low, or E2 high. A write cycle ends at the
!!Wliest transition of an El high, W high, or£.2 low.
_
2. Elln the timing diagrams represents bollLEl and E2 with El asserted low and E2 asserted high.
3. If W Qoes low coincident with or prior to El low or E2 high the outputs will remain in a
high-Impedance state.
4. During this time the output pins may be in the output state. Signals of opposite phase must not be
applied to the outputs at this time.
5. These inputs are latched and must meet the required setup and hold times for ALL latch enable
(LE) low transitions.
Hold Times for:

2,
El
E2

CHIP ENABLE INITIATED WRITE CYCLE

A (ADDRESS)

LE (LATCH ENABLE)

E1 (CHIP ENABLE)

W(WRITE ENABLE)

o(DATA IN)
HIGH-Z

Q(DATAOUT)

MOTOROLA MEMORY DATA
5-234

Notes

ns
ns
ns

MCM62820

+5V

+5V

4800

4800

DO

DO

2550

2550

30g"
gN lUDING
COPE AND JIG)

l.-

:',= 5~F

g ClUDING
COPE AND JIG)

--=

0:-

-Vee
r-

-F-

E2

'---

DATA (19:0)

I.

"

Ef

A

lE ADDRESS (12:0)
~
W
MCM62820

DATA (19:0)

INSTRUCTION CACHE
(8K xSO)

W
1ICM62820
G FI--

13

DATA CACHE
(8K xSO)

60

-~

I

L..-

'---

'---

IRD

DATA (31:0)
DATAP(3:0)

TAG (19:0)
TAG P(2:0)
TAG V
ORO I--

R3000 PROCESSOR

IWR
IClK

~

~

~

ADDRESS lOW (12:0)

II

f--

ADDRESS (12:0) lE

G

r---

E2

Ef

DWR I - DClK r - -

Figure 2. R3000 Application Example with 64K Byte
Segregated InstructloniData Cache Using
Six Motorola MCM62820 Latched SRAMs

ORDERING INFORMATION
(Order by Full Part Number)
MCM

MotorolaMemOryprefixJ

TTL==
T
62820

x

xx

Part Number _ _ _

Full Part Numbers - MCM62820FN23

MCM62820FN30

MOTOROLA MEMORY DATA
6-235

Speed (23 = 23 ns, 30 = 30 ns)
Package (FN = PLCC)

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM62820A
Product Preview

8K x 20 Bit Fast Static RAM
The MCM62820A is a 163,840 bit static random access memory organized as 8,192
words of 20 bits, fabricated using Motorola's high-performance silicon-gate CMOS
technology. The device integrates an 8K x 20 SRAM core with address and chip enable
input latches, multiple chip enable inputs, and an output enable input.
FNPACKAGE
The availability of output enable (G) and multiple chip enable (n and E2) inputs
PLASTIC
CASE 778
provide for greater system flexibility when multiple devices are used. With either chip
enable input negated, the device will enter standby mode, useful in low power
applications. All address (AO-A12) and chip enable (n, E2) inputs propagate through
PIN ASSIGNMENT
level-sensitive on-chip latching controlled by LE. This feature alleviates the need for
external address and chip enable latching. This device was designed specifically to
operate as cache memory with the R3000 RISC Microprocessor (see
~~~~~~9~<~~~~
Figure 2), but it will also be very adaptable wherever wide and fast
8 7 6 5 4 3 2 1 52 51 50 49 46 4746
SRAMs are needed.
VSS
The MCM62820A will be available in a 52-pin plastic-leaded
45
DO~
chip carrier. Multiple power and ground pins have been
44
001 10
utilized to minimize effects induced by output noise.
43
Vss 11

•

•
•
•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Fast Access and Cycle Times: 17/23 ns Max
Fully Static Read and Write Operations
Equal Address and Chip Enable Access Times
On Chip Address and Chip Enable Latches
Active High and Active Low Chip Enable Inputs
Output Enable Controlled Three-State Outputs
High Board Density PLCC Package
Low Power Standby Mode
Fully TTL-Compatible

002
003
DQ4
DQ5
006

12
13
14
15
16
17
18
19

009

2~1

42
41

40

0018
VSS
0017
0016
0015
0014
0013
0012

39
38
37
38 VSS
35 0011
0010
22 23 24 25 26 27 28 29 30 31 32 3334

9 ~ ~ !;;: ~ 9 :!Lll w111
IC!l

BLOCK DIAGRAM

VSS
0019

1;1:

~

9

AD-A12
PIN NAMES

AO-A12 ...... Address Inputs
LE .. . . . . . . . . .. Latch Enable
W ............. Write Enable
8, E2 ......... Chip Enable
G . . . . . . . . . . .. Output Enable
DOO-D019 Data Input/Output
VCC .... + 5 V Power Supply
VSS ............... Ground
NC .......... No Connection

E1. E2
LE

For proper operation of the device,
all VSS pins must be connected to
ground.

DOD ---:;---1--------+-1
0019

--"'----+-_-----li--l

This document contains information on a project under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
5-236

MCM62820A

TRUTH TABLE
E1

E2

G

W

LE

Mode

Supply Current

110 Status

H

X

X

X

X

Not Selected

ISB

High-Z
Hlgh-Z

X

L

X

X

X

Not Selected

ISB

L

H

H

H

X

Output Disabled

ICC

High-Z

L

H

L

H

H

Read with Transparent Inputs

ICC

Data Out

L

H

L

H

L

Read with Latched Inputs

ICC

Data Out

L

H

X

L

H

Write with Transparent Inputs

ICC

Data In

L

H

X

L

L

Write with Latched Inputs

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
fields; however it is advised that normal precautions be taken to avoid
application of any voltage higher
than maximum' rated voltages to this
high-impedance circuit.
This CMOS memory circuit has
been designed to meet the dc and ae
specifications shown in the tables,
after thermal equilibrium has been
established. The circuit is assumed
to be in a test socket or mounted on
a printed circuit board with at least
300 LFPM of transverse air flow being maintained.

Data In
ICC
NOTE: X means don't care. Inputs AO-A 12, E1 , E2 are latched or transparent depending upon the state of
latch enable (LE).
ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = a V)
Rating

Symbol

Value

Unit

VCC

-O.Sto + 7.0

V

Voltage Relative to VSS

Yin, Vout

-0.5 to VCC + 0.5

V

Output Current (per 110)

lout

±20

mA

Power Dissipation (TA = 70°C, VCC = 5 V,
tAVAV = 23 ns)

PD

2.5

W

Temperature Under Bias

Tbias

-10to+8S

°c

Operating Temperature

TA

a to +70

°c

Power Supply Vottage

Storage Temperature

II

-55to+ 125

°c
Tstg
NOTE: Permanent deVIce damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to +70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = a V)
Symbol

Min

TYP

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

3.0

V

Input Low Voltage

VIL

-0.5'

0.0

VCC+0.3
0.8

Parameter

V

'VIL (min) = - 3.0 V ac (pulse width:::; 20 ns)
DC CHARACTERISTICS
Parameter

Symbol

Min

Max

Unit

"kg(')

-

± 1.0

Output Leakage Current (G = VIH, E1 = VIH, E2 = VIL, Vout = 0 to VCC)

l'kg(O)

-

± 1.0

flA
flA

AC Supply Current (G = V'H, El = V'L, E2 = V'H, All Inputs = V,L = 0.0 V and VIH;:: 3.0,
'out = a mAl
Cycle Time;::17 ns
Cycle Tim~3 ns

ICCA

-

-

280
240

-

15.0

mA

10.0

mA

0.4

V

Input Leakage Current (All Inputs, Yin =

a to VCe>

mA

Standby Current (El = V,H or E2 = V'L, All Inputs = VIL or V, H)

ISBl

CMOS Standby Current (E1 ;:: VCC - 0.2 V, E2:::; 0.2 V, All Inputs ;:: VCC - 0.2 V or:::; 0.2 V)

ISB2

Output Low Voltage (lOL = + 8.0 mAl

VOL

-

Output High Voltage (IOH = - 4.0 mAl

VOH

2.4

-

V

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol

TYP

Max

Unit

All Pins Except DOO-D019

Cin

4

6

pF

DOO-D019

CliO

6

8

pF

Characteristic
Input Capacitance .
InpullOutput Capacitance

MOTOROLA MEMORY DATA

5-237

MCM62820A

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Vee = 5.0 V ± 10%, TA = 0 to 70o e, Unless Otherwise Noted)
Input Timing Measurement Reference Level .........•..... 1.5 V
Input Pulse Levels. . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . .. 0 to 3.0 V
Input Rise/Faillime ......................•.............. 3 ns

Output Measurement Reference Level .. . • . . . . . . . . . . . . . . .. 1.5 V
Output Load . . . . . . . . . . . .. See Figure 1A Unless Otherwise Noted

READ CYCLE TIMING (See Notes 1, 2, 3)

Symbol
Parameter
Read Cycle Time

MCM62820A-23

Altamata

Min

Max

Min

Max

Unit

tAVAV

tRC

17

-

23

ns

-

23

ns

23

ns

25

-

ns

10

ns
ns

4,5

ns

5

ns

5

4

-

ns

4,6

-

ns

4,6

ns

4,5

tAVQV

tAA

Chip Enable to Output Valid

:E1LQV
E2HQV

tACI

-

Latch Enable High to Output Valid

ILEHQV

-

Address Access Time

•

MCM62820A-17

Standard

17

17
17

-

-

Output Enable to Output Valid

toLQV

toE

Output Active from Chip Enable

tE1LQX
tE2HQX

tCLl

2

Output Active from Output Enable

toLQX

toll

2

Output Active from Latch Enable High

tLEHQX

Output Hold from Address Change

tAXQX

toH

3

..A

tAVLEL
tE1VLEL
tE2VLEL

tAS
tcs
Its

3

-

..A

tLELAX
lLELE1X
LELE2X

tAH

2

-

3

~E1HQZ

tCHZ

0

9

0

Setup Times For:

El
E2

Hold Times for:

El
E2

Chip Enable High to Output High·Z

2

~~

6

2
2
2

3

9

Notea

4

ns

E2LQZ

0
9
ns
0
9
5
tLEHQZ
tcHZ
Output Enable to Output High-Z
ns
0
6
0
8
5
tOHZ
toHQZ
NOTES.
1. A read cycle Is defined by Iii high.
2. All read cycle timings are referenced from the last valid address to the first transitlonlng address.
3. Addresses must be valid prior to or coincident with E1 going low or E2 going high.
4. E1 in the timing diagrams represents both E1 and E2 wnh E1 asserted low and E2 asserted high.
5. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B. This parameter Is sampled and not 100% tested. At any
given voltage and temperature, tEl HQZ max is less than tEl LQX min, tE2LQZ max is less than tE2HQX min and toHQZ max Is less than
tGLQX min for a given device and from device to device.
6. These inputs are latched and must meet the required setup and hold times for ALL latch enable (LE) low transitions.
Latch Enable High to Output High-Z

READ CYCLE

LE (LATCH ENABLE)

Ei1CHIP ENABLE)

G"jOUTPUT ENABLE)

Q(DATAOUT)

MOTOROLA MEMORY DATA
5-238

MCM62820A

WRITE CYCLE TIMING , Write Enable Initiated (See Note I)
Symbol
Parameter
Write Cycle Time

MCM62820A-17

Standard

Alternate

Min

Max

tAVAV

twc

17

-

MCM62820A-23
Min
23

Max

Unit

-

ns

Address Setup Time

tAVWL

tAS

0

-

0

-

ns

Address Valid to End of Write

tAVWH

tAW

13

20

-

ns

Notes
2

Write Pulse Width

twLWH

twp

13

-

IS

-

ns

3

Write Enable to Chip Enable Disable

tWLEIH
tWLE2L

tcw

13

-

IS

-

ns

4

Chip Enable to End of Write

tEILWH
tE2HWH

tcw

13

-

IS

-

ns

3,4,5

Data Valid to End of Write

tDVWH

tDW

6

-

7

-

ns

Data Hold Time

twHDX

tDH

0

0

-

ns

6

Write Recovery Time

twHAX

twR

0

0

-

ns

2

tAVLEL
tEIVLEL
tE2VLEL

tAS
tcs
tcs

3

-

4

-

ns

4,5

twHLEH

tLEH

-2

-

-2

-

ns

tLELAX
tLELEIX
tLELE2X

tAH

2

-

3

-

ns

Setup Times for:

-A
EI
E2

LE Hold to End of Write
Hold Times for:

A
E1
E2

%~

4,5

Write Low to Output High Z
ns
7
9
a
9
0
twLQZ
twHZ
Write High to Output Low Z
2
2
ns
7
twHOX
twLZ
NOTES.
I. A write cycle starts althe latesltransition ofE1low, iN low, or E2 high. A write cycle ends althe earliesltransition of an E1 high iNhigh, or E2
low.
2. Write must be high for all address transitions.
3. If iN goes low coincident with or prior to E1low or E2 high the outputs will remain in a high-impedance state.
4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
5. These inputs are latched and must meet the required setup and hold times for ALL latch enable (LE) low transitions.
6. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.
7. Transition is measured ± 500 mV from steady-state voltage with load of Figure I B. This parameter is sampled and not I 00% tested. At any
given voltage and temperature, tEl HOZ max is less than tEl LOX min, tE2LOZ max is less than tE2HOX min and tGHOX max is less than
'GLOX min for a given device and from device to device.

-

WRITE ENABLE INITIATED WRITE CYCLE

A (ADDRESS)

LE (LATCH ENABLE)

E1{CHIP ENABLE)

iii (WRITE ENABLE)

o(DATA IN)
Q{DATAOUT)

tWLE1H-----~

MOTOROLA MEMORY DATA

5-239

•

MCM62820A

.

WRITE CYCLE TIMING Chip Enable Initiated (See Notes 1 and 2)
Symbol,

MCM62820A-23

Alternate

Min

Min

Max

Unit

tAVAV

twc

17

-

23

-

ns

Address Setup Time

tAVEIL
tAVE2H'

tAS

0

-

0

ns

Address Valid to End of Write

~VEIH
AVE2L

tAW

13

-

20

-

Data Valid to End of Write

tOVEIH
tOVE2L

tow

,6

-

7

-

ns

Chip Enable to End of Write

tEl LEI H
tE2HE2L

tcw

13

-

15

-

ns

3

Data Hold TIme

tEIHOX
tE2LOX

tOH

0

-

0

-

ns

4

Write Recovery TIme

tEIHAX
tE2LAX

twR

0

-

0

ns

LE Hold to End of Write

tEIHLEH
tE2LLEH

tEIHLEH
tE2LLEH

-2

-

-2

~

tAVLEL
tEIVLEL
tE2VLEL

tAS
tcs
tcs

3

-

4

ns

EI
E2

-

5

Ef
E2

ILELAX
tLELEIX
tLELE2X

tAH
tCH
tcH

2

-

3

-

ns

5

Write Cycle TIme

--

MCM62820A-17

Standard

'Parameter

Setup Times for:

Hold Times for:

Max

Notes

ns

ns

NOTES.
1. A write cycle starts atthe latesttransition of Eflow. Wlow. or E2 high. A write cycle ends atthe earliesttransition of an Ef high. Whigh. or E2
low.
2, Ef in the timing diagrams represents both Ef and E2 with Ef asserted low and E2 asserted high,
3. If Wgoes low coincident w~h or prior to Eflow or E2 high the outputs will remain in a high-impedance state.
4. During this time the I/O pins may be in the output state. Signals of opposite phase must not be applied to the I/Os at this time.
5, These inputs are latched and must meet the required setup and hold times for ALL latch enable (LE) low transitions,

CHIP ENABLE INITIATED WRITE CYCLE

A(ADDRESS)

LE (LATCH ENABLE)

TI (CHIP ENABLE)

W(WRITE ENABLE)

o(DATA IN)
Q(DATAOUT)

HIGH-Z

MOTOROLA MEMORY DATA

5-240

MCM62820A

AC TEST LOADS
+5V

+5V

4800
DQ~~----+

2550

'-___-+

DQ~----"

30pF
(INCLUDING
SCOPE AND JIG)

2550

'-___-+

5pF
(INCLUDING
SCOPE AND JIG)

=

=
Figure 1A

Figure 1B

-

-Vee

- r-

.

A

-

E2

DATA (19:0)

-=

rv--

G

INSTRUCTION CACHE
(SKx6O)

~

I

'-'---

DATA (19:0)

ADDRESS (12:0) LE
MCM62820A

~

~~

DATA (31:0)
DATA P (3:0)

TAG (19:0)
TAGP(2:0)
TAG V
ORO

R3000 PROCESSOR

IWR
ICLK

Vi
G =-

DATA CACHE
(SK x 60)

60

•

IRD

-

E2

E1

r

13

ADDRESS LOW (12:0)

'---

C

"

E1
.IL
LE ADDRESS (12:0)
W
MCM62820A

DWR
DCLK

-

Figure 2. R3000 Application Example with 64K Byte
Segregated Instruction/Data Cache Using
Sixl.totorola MCM62820A Latched SRAMs

ORDERING INFORMATION
(Order by Full Part Number)

MCM
Motorola Memory p r e f i x J
Part Number

T1I

62820A

x

Full Part Numbers - MCM62820AFN23

XX

MCM62820AFN30

MOTOROLA MEMORY DATA
5-241

_,,,",, ~ "." ~I
Package (FN=PLCC)

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

Product Preview

MCM67282

256K x 4 Bit Fast Static Random
Access Memory
The MCM67282 is a 1,048,576 bit static random access memory organized as
262,144 x 4 bits. This device is fabricated using high-performance silicon-gate
BiCMOS technology. Static design eliminates the need for external clocks or timing
strobes.
This device meets JEDEC standards for functionality and revolutionary pinout, and is
available in a 400-mil plastic small-outline J-Ieaded package.

•

•
•
•
•
•
•

Single 5 V ±10% Power Supply
Fully Static - No Clock or Timing Strobes Necessary
All Inputs and Outputs Are TIL-Compatible
Three-State Outputs
Fast Access Times: 10, 12 ns
Center Power and I/O Pins for Reduced Noise

PIN ASSIGNMENT

BLOCK DIAGRAM

Vee
Vss

------..~--,

A-----.~__,

.

A
A
A

MEMORY
MATRIX
512ROWSx512x4
COLUMNS

A

-'

AO-A17

-

0

r- - iii
r- -E

I--

~~
02

-'\

~

brf

05

Ot--Ol

0

0-Q2

AD-A17
I"-

-

0

~

AD-A17

-

0

-

-~

..... rI--

01--

-

0

:)

AO-A17

-

~~

Or--- as

AO-A17

iii

~r07

Q3

'- 0

-"

iii

I"-

-

~

AO-A17

iii

..... - E

-E

-II-

-IIiii
E1

as

..... _E

t-1H
03

O~

- - iii
..... _E

06

r- ~ iii
r- -E

AO-A17

iii

-E

b~
01

ot-- Q4

-

Ei-

Vee
VSS
AD-A17

PDQ -NC
POl

-

°NC = No Connect,

MOTOROLA MEMORY DATA
6-11

-

O~ 07

MCM8256

MCM8256 TRUTH TABLE
Ex
H

W
X

Mode
Not Selected

VCC Current

L

H

Read

ICCA

Input
High-Z
Hlgh-Z

L

L

Write

ICCA

Din

ISB1,ISB2

Dout
High-Z

The devices on this module contain
circuitry to protect the inputs against
damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid
application of any voltage higher than
maximum rated voltages to these high
impedance circuits.
These CMOS memory circuits have
been designed to meet the dc and ac
specifications shown in the tables, after
thermal equilibrium has been established. The module is in a test socket or
mounted on a printed circuit board and
transverse air flow of at least 500 linear
feet per minute is maintained.

Cycle

Output
High-Z

Read Cycle
Write Cycle

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating
Power Supply Voltage

Symbol

Value

VCC

-0.5to +7.0

Unit
V
V

Voltage Relative to VSS

Yin, Vout

Output Current (per VOl

lout

- 0.5 to VCC + 0.5
±30

rnA

Power Dissipation (TA = 70'C, VCC = 5 V,
TAVAV = 20 ns)
Temperature Under Bias

Po

8

W

-10to+85
'c
Tbias
Operating Temperature
o to +70
TA
'c
Storage Temperature
-25 to +125
'c
Tsto
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Vee = 5.0 V ±10%, T A = 0 to +70 o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter
Supply Voltage (Operating Voltage Range)

Symbol
VCC

Min
4.5

Typ
5.0

Max
5.5

Unit
V

Input High Voltage

VIH

2.2

3.0

VCC +0.3"

V

Input Low Voltage

Vil

-OS"

0.0

0.8

V

Symbol

Min

Typ

Ilkg(l)

-

-

Max
±8

Unit
j.tA

-

±8

I·)

,. ( )

'vlH max = VCC + 0.3V dc' VIH max = VCC + 2 V ac (pulse wlatn $20 ns)
""Vll min) = -3.0 V ac (pulse Width $20 ns)

DC CHARACTERISTICS
Parameter
Input leakage Current (All Inputs, Yin = 0 to VCC)
Output leakage Current (El and E2 = VIH, Vout = 0 to VCC)

Ilkg(O)

AC Active Supply Current (lout = 0 rnA, Cycles limes;, tAVAV min)
MCM8256-15: tAVAV = 15 ns
MCM8256-20: tAVAV = 20 ns

ICCA

AC Stantlby Current (El and E2 = VIH, Cycles limes;, tAVAV min)
MCM8256-15: tAVAV = 15 ns
MCM8256-20: tAVAV = 20 ns

ISBI

CMOS Standby Current (f= 0 MHz, E;,VCC-0.2 V, Yin ';VSS + 0.2 Vor;,VCC
-0.2 V)

ISB2

Output low Voltage (IOl = + 8.0

mAl

Output High Voltage (IOH = - 4.0 rnA)

.

-

j.tA

rnA
720
640

1200
1120

-

300
260

400
360

-

32

160

rnA

VOL

-

V

2.4

-

0.4

VOH

-

V

Symbol

Ttp

Max

Unit

Cin

32
20
6

48
28
7

pF

CliO

8

9

pF

rnA

NOTE: Good decouphng of the local power supply should always be used.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25'C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input CapaCitance

Wand Address

ET-E2

00-07
InpuVOutput Capacitance

00-07

MOTOROLA MEMORY DATA

6-12

MCM8256

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±10%, TA = 0 to +70 oe, Unless Otherwise Noted)

Input Timing Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall Time ..................................... 5 ns

Output Timing Reference Level .......................... 1.5 V
Output Load ............. See Figure 1A Unless Otherwise Noted

READ CYCLE TIMING (See Notes 1 and 2)
Symbol
Parameter

MCM8256·15

MCM8256-20

Min

Max

Min

tRC

15

-

20

-

ns

tAA

15

-

20

ns

Standard

Alternate

Read Cycle Time

tAVAV

Address Access Time

tAVQV

Max

Unit

Notes
3

Enable Access Time

tELQV

tACS

-

15

-

20

ns

Output Hold from Address Change

tAXQX

toH

4

-

4

ns

Enable Low to Output Active

tELQX

tcu

4

-

4

-

ns

4,5,6

Enable High to Output High-Z

tEHQZ

tCHZ

0

8

0

9

ns

4,5,6

tELICCH

tpu

0

-

0

-

ns

Power Up Time

Power Down Time
15
20
ns
tpD
tEHICCL
NOTES:
1. Wis high for read cycle.
2. ET-E2 are represented by E in these timing specifications, any combination of E.s may be asserted.
3. All read cycle timing is referenced from the last valid address to the first transitioning address.
4. At any given voltage and temperature, tEHQZ max is less than tELQX min both for a given device and from device to device.
5. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
6. This .parameter is sampled and not 100% tested.

TIMING LIMITS

AC TEST LOADS

'""'"1 ~. ~

ff

+5V480n

Q

~

255 n

VL=1.5V

Figure lA

5 pF
(INCLUDING
SCOPE AND JIG)

Figure 18

MOTOROLA MEMORY DATA
6-13

The table of timing values shows either a minimum or a maximum limit for
each parameter. Input requirements are
specified from the extemal system point
of view. Thus, address setup time is
shown as a minimum since the system
must supply at least that much time
(even though most devices do not require it). On the other hand, responses
from the memory are specified from the
module point of view. Thus, the access
time is shown as a maximum since the
module never provides data later than
that time.

II

MCM8256

READ CYCLE 1 (See Note)

t:

~J
l'--__
_

tAVAV

A (ADDRESS) _ _ _ _

Q(DATA OUn

-tAVQX---------'

PREVIOUS DATA VALID

DATA VALID

14-------

tAVQV

NOTE: Oevice is continuously selected (E = VIU,

READ CYCLE 2 (See Note)

•

tAVAV
A (ADDRESS)

/
\
tELQV

EX (NIBBLE ENABLE)

\

V
/l'--tEHOZ'"
-tELQX -

)(XXXtK

Q(DATAOUT)
tAVQV

DATA VALID

I--

\
/

SUPPLYCURR~~9 -------------f-----------------=jL
teLiCCH --ICC
ISB _ _ _ _ _ _ _ _ _...J.

NOTE: Addresses valid prior to or coincident with E going low.

MOTOROLA MEMORY DATA
6-14

teHICCL

MCM8256

WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
Symbol
Parameter

MCM8256-15

Standard Alternate

Min

Max

MCM8256-20
Min

Max

Unit

Write Cycle lime

tAVAV

twc

15

-

20

-

ns

Address Setup lime

tAVWL

tAS

0

-

0

ns
ns
ns

Address Valid to End of Write

tAVWH

tAW

12

-

15

-

Write Pulse Width

twLWH,
tWLEH

twP

12

-

15

-

Data Valid to End of Write

tDVWH

tow

7

-

ns

twHDX

tDH

0

-

8

Data Hold lime

0

-

ns

Notes
3

Write Low to Data High-Z

tWLOZ

twz

0

7

0

8

ns

4,5,6

Write High to Output Active

twHOX

tow

4

-

4

ns

4,5,6

Write Recovery lime

twHAX

twR

0

-

-

0

-

ns

NOTES:
1. A write occurs during the overlap of E low and Wlow.
2. E1-E2 are represented by E in these timing specifications, any combination of Exs may be asserted.
3. All write cycle timing is referenced from the last valid address to the first transitioning address.
4. Transition Is measured ± SOO mV from steady-state voltage with load of Figure 1B.
5. This parameter is sampled and not 100"10 tested.
6. At any given voitage and temperature, twLOZ max is less than twHox min both for a given device and from device to device.

WRITE CYCLE 1

tAVAV - - - - - - - - . ;
A (ADDRESS)

14--------

lAVWH ------"....--001- twHAX

Ex (NIBBLE ENABLE)

W(WRITE ENABLE)

---t-----, 1----- twLWH
tOVWH

D(DATA IN)

---1--+1-

DATA VALID

HIGHZ

Q (DATA OUT) ---"':::..:..:'----{

MOTOROLA MEMORY DATA
6-15

•

MCM8256

WRITE CYCLE 2 (E" Controlled, See Notes 1 and 2)
MCM8256-15

MCM8256-20

Standard

Alternate

Min

Min

Max

Write Cycle Time

tAVAV

twc

15

-

20

tAVEL

tAS

0

0

Address Valid to End of Write

tAVEH

tAW

12

-

15

-

ns

Address Setup Time
Enable to End of Write

tELEH

tcw

10

-

12

-

ns

Enable to End of Write

tELWH

lew

10

-

12

ns

Data Valid to End of Write

tDVEH

tow

7

-

8

-

Data Hold Time

tEHDX

tDH

0

-

0

-

ns

Write Recovery Time

tEHAX

twR

0

-

0

-

ns

Symbol
Parameter

Max

Unit

Notes
3

ns
ns
4,5

ns

NOTES:
1. A wr~e occurs during the overlap of E low and Wlow.
2. E1-E2 are represented by E in these timing specifications, any combination of Exs may be asserted.
3. All write cycle timing is referenced from the last valid address to the flrsttransitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high-impedance condition.
5. If E goes high coincident with or before Wgoes high, the output will remain in a high-impedance condition.

WRITE CYCLE 2

•

tAVAV - - - - - - - - - - - . j
A(ADDRESS)
tAVEH - - - - - - - - - . j

Ex (NIBBLE ENABLE)
; . . - - - - tAVEL

------ro--- tELWH
tELEH ----<-14--* tEHAX

iii (WRITE ENABLE)
toVEH -~-I-

o(DATA IN)
Q(D~AOU~

DATA VALID

______________________________

~H~IG~H~Z~

________________________________

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix
Part Number

T
Full Part Numbers- MCM8256Z1s

Speed (IS = 15 ns, 20 = 20 ns)
Package (Z = ZIP Module)
MCM82s6Z20

MOTOROLA MEMORY DATA
6-16

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM32257
PIN ASSIGNMENT
64 LEAD ZIG-ZAG IN-LINE PACKAGE
TOP VIEW

Product Preview
256K x 32 Bit Static Random
Access Memory Module

Vss

PDO
000

The MCM32257 is an 8M bit static random access memory module organized as
262,144 words of 32 bits. The module is a 64-lead zig-zag in-line package (ZIP)
consisting of eight MCM6229 fast static RAMs packaged in 28 J-Iead small outline
package (SOJ) and mounted on a printed circuit board along with eight decoupling
capacitors.
The MCM6228 is a high-performance CMOS fast static RAM organized as 262,144
words of 4 bits, fabricated using high-performance silicon-gate CMOS technology. Static
design eliminates the need for external clocks or timing strobes, while CMOS circuitry
reduces power consumption and provides for greater reliability.
The MCM32257 is equipped with output enable (G) and four separate byte enable
(El-E4) inputs, allowing for greater system flexibility. The G input, when high, will force
the outputs to high impedance. Ex high will do the same for byte x.
PDO and PDl are reserved for density identification. PDO and PDl are connected to
ground. These pins can be used to identify the density of the memory module.
• Single 5 V ± 10% Power Supply
• Fast Access Time: 20/25 ns
• Three-State Outputs
• Fully TTL Compatible
• JEDEC Standard Pin Out
• Power Operation: 1200/1120 mA Maximum, Active ac
• High Board Density ZIP Package
• Byte Operation: Four Separate Chip Enables, One for each byte (eight bits)
• High Quality Four-Layer FR4 PWB with Separate Internal Power and Ground Planes
• Incorporates Motorola's State-of-the-Art Fast Static RAMs

AO-A 17 ............................. Address Inputs
Write Enable
G .................................. Output Enable
Ef-81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Byte Enables
000-0031 ...................... Data Input/Output
VCC ............................ + 5 V Power Supply
VSS ....................................... Ground
PDO-PDI ......................... Package Density
NC .................................... No Connect

W ....................................

POI

DOl

DOS

002

009
DOlO

003

DOlI

Vee
AI

AO

A3

A2

AS

A4

D04
D05
DOS
007

W
A7

E1
§
A9

VSS
0016

DOI7

0012
0013
DAI4
0015
VSS
AS

E2
E4
AS

G
D024
D025

DOIS

0026

DOI9

0027
AIO

All

PIN NAMES

4

AI3
AI5

AI2

AI6
0020

Vee
AI7

0021

0028

0022

D029
0030

0023
Vss

AI4

0031

For proper operation of the device, VSS must be connected to
ground.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
6-17

•

MCM32257

FUNCTIONAL BLOCK DIAGRAM

000-003

4

"v

4

0016-0019

0OD-003

"

AO-A17

v

w

-G

~G

07

4

~r-1

E34

000-D03

v

•

E

iii

iii
G

>--

.~.r-j

b~

000-003

4

0024-0027 -

AO-A17

v

4
0012-00 15

"

0OD-003
AO-A17

E

E

iii

iii
G

~G

-

AO-A17

E
~G

0Q6-D01 1 -

~r-1
0OD-003

0020-0023

AO-A17

4

AO-A17

E

E

w

-

DQO-003

>---

. ~r-j

b~

&1-

0OD-003

4

0026-0031

AO-A17

DQO-DQ3
AO-A17

E

E

iii

iii
G

~G

>---

-If-

Hf-

iiiG-

-

Vcc Vss AO-A1 7 -

PDQ-POl ~

MOTOROLA MEMORY DATA
6-18

MCM32257

MCM32257 TRUTH TABLE
Ex

G

W

Mode

VCCCurrent

Output

H

X

X

Not Selected

ISBl orl SB2

High-Z

l

H

H

Read

ICCA

High-Z

l

l

H

Read

ICCA

Dout

Read Cycle

l

X

l

Write

ICCA

Din

Write Cycle

This devices on this module contain
circuitry to protect the inputs against
damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid
application of any voltage higher than
maximum rated voltages to these high
impedance circuits.

Cycle

-

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = 0 V)
Rating

Symbol

Power Supply Voltage

Value

VCC

-0.5 to 7.0

V

Vcca

-0.5to VCC

V

Voltage Relative to VSS

Yin, Vout

- 0.5 to VCC + 0.5

V

Output Current (per I/O)

lout

±30

rnA

Po

8

W

Temperature Under Bias

Tbias

-10to+85

°c

Operating Temperature

TA

o to + 70

°C

Output Power Supply Voltage

Power Dissipation (TA
tKHKH = 20 ns)

= 70°C, VCC = 5 V,

These CMOS memory circuits have been
designed to meet the dc and ac
specifications shown in the tables, after
thermal equilibrium has been established.
The module is in a test socket or mounted
on a printed circuit board and transverse air
flow of at least 500 linear feet per minute is
maintained.

Unit

Storage Temperatrue

-25to+ 125
°C
Tsta
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

•

DC OPERATING CONDITIONS AND CHARACTERISTICS
(V CC = Vcca = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

3.0

VCC+
0.3"

V

Input low Voltage
'vIH (max) =vcc + U.~ vac; vlH (max) = vcc + 2vac (pUlse wlatn" 2U ns)
""Vll (min) = - 3.0 V ac (pulse width'; 20 ns)

Vil

- OS"

0.0

0.8

V

Parameter

Symbol

Min

Typ

Max

Unit

= 0 to VCC)
Output leakage Current (G, Ex = VIH, Vout = 0 to Vcca)
AC Active Supply Current (G, Ex = Vll, lout = 0 rnA,) MCM32257-20 tAVAV = 20 ns
Cycle time" tAVAV min)
MCM32257-25 tAVAV = 25 ns
MCM32257-20 tAVAV = 20 ns
AC Standby Current (Ex = VIH,
MCM32257-25 tAVAV = 25 ns
Cycle time" tAVAV min)

Ilkg(l)

±8

~A

DC CHARACTERISTICS
Input leakage Current (All Inputs, Yin

Ilkg(O)

-

-

±8

~A

1120
960

rnA

ICCA20
ICCA25

-

-

ISBI

-

360
320

rnA

CMOS Standby Current (Ex" VCC - 0.2 V, All Inputs "VCC - 0.2 V or" 0.2 V)

ISB2

-

120

rnA

Output low Voltage (IOl = + 8.0 rnA)

VOL

-

-

0.4

V

Output High Voltage (IOH = - 4.0 rnA)
NU I t:: ~ooa aecoup Ing 0 tne oca power supp y s oUia a ways oe usea.

VOH

2.4

-

-

V

MOTOROLA MEMORY DATA
6-19

MCM32251

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance

(all pins except 000-0031 and

~~

El-E4
Input/Output CapaCitance (000-0031)

Symbol

Typ

Max

Unit

Cin

32
10

48
14

pF

Cout

8

9

pF

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%, TA =0 to + 70 oe, Unless Otherwise Noted)
Input liming Measurement Reference Level ................ 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input RiseJFalilime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 ns

OutputTiming Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load ............ See Figure 1A Unless Otherwise Noted

READ CYCLE TIMING (See Notes 1 and 7)
MCM32257-20

MCM32257-25

Alt.

Min

Max

Min

Max

Unit

Notes

20

-

25

-

ns

2

25

ns

Symbol
Parameter

•

Std.

Read Cycle lime

tAVAV

tRC

Address Access lime

tAVOV

tAA

Enable Access lime

tELOV

tACS

Output Enable Access lime

'GLOV

toE

-

Output Hold from Address Change

tAXOX

toH

5

Enable Low to Output Active

tELOX

tCLZ

5

Output Enable to Output Active

'GLOX

toLZ

0

-

Enable High to Output High-Z

tEHQZ

tCHZ

0

tGHOZ
tELICCH

Output Enable High to Output High-Z
Power Up lime

20
20

-

25

ns

10

ns

5

-

ns

5

ns

3,4,5

0

-

ns

3,4,5

8

0

10

ns

3,4,5

toHZ

0

8

0

10

ns

3,4,5

tpu

0

-

0

-

ns

9

-

Power Oown lime
20
25
ns
tpo
tEHICCL
NOTES.
1. Wis high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transitioning address.
3. At any given voltage and temperature, tEHOZ max is less thantELOX min, and 'GHOZ max is less than 'GHOX min, both for a given device and
from device to device.
4. Transition is measured ± 500 mV from steady-state voltage with load Of Figure 1B.
5. This parameter is sampled and not 100% tested.
6. Oevice is continuously selected (1: =VIL, G = VIL).
7. 8-E4 are represented by E in these timing specifications, any combination of Exs may be asserted.

READ CYCLE 1 (See Note 6 Above)
\ + - - - - - - - - - - I A V A V - - - - - - - - - - - - +Jl
A(ADDRESS)

~

fro..

______'I~____________--I------------------JI~-----

tAJ(OX---+i

D_A_JA_~_AL_ID_ _ _ _ __

Q(DATAOUT)_ _ _ _-+_P_R_EV_IO_U_S_D_Al_A_VA_L_ID--J.to-

E2

iN

T

r

Vee
Vee
Vss

E2

iN

>----Jf--

Hf-ET
G1

I- E1
I- 13

.--J

VSS-

i--'

t--

(i2-

t--

I---

E2-

I---

AQ-A14

PDO---l-'
PD1PD2-

MOTOROLA MEMORY DATA
6-25

III

MCM36232

MCM36232 TRUTH TABLE
E1

E2

G1

G2

Wx

Mode

Vee Current

Output

H

L

X

X

X

Not Selected

ISBI or ISB2

High-Z

-

L

L

H

X

H

Read Bank 1

ICCA,ISBI

High-Z

-

L

L

L

X

H

Read Bank 1

ICCA,ISBI

Dout

Read Cycle

L

L

X

X

L

Write Bank 1

ICCA,ISBI

Din

Write Cycle

H

H

X

H

H

Read Bank 2

ISB1,ICCA

High-Z

H

H

X

L

H

Read Bank 2

ISB1,ICCA

Dout

Read Cycle

H

H

X

X

L

Write Bank 2

ISB1,ICCA

Din

Write Cycle

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = 0 V)
Rating

Symbol

Power Supply Voltage

Unit
V

VCC

- 0.5 to 7.0

Vcca

-0.5to VCC

V

Voltage Relative to V 55

Yin, Vout

- 0.5 to VCC + 0.5

V

Output Current (per 110)

lout

±30

rnA

Power Dissipation (TA = 70°C, VCC = 5 V)

PD

5

W

Temperature Under Bias

Tbias

-10to+85

°C

Operating Temperature

TA

o to + 70

°C

Output Power Supply Voltage

•

Value

Cycle

-

This devices on this module contain
circuitry to protect the inputs against
damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid
application of any voltage higher than
maximum rated voltages to these high
impedance circuits.

Storage Temperature
-2Sto + 125
°C
Tsta
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

These CMOS memory circuits have been
designed to meet the dc and ac
specifications shown in the tables, after
thermal equilibrium has been established.
The module is in a test socket or mounted
on a printed circuit board and transverse air
flow of at least 500 linear feet per minute is
maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%, TA = 0 to + 70 o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

Parameter

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

3.0

VCC+
0.3·

V

Input Low Voltage

VIL

-0.5"

0.0

0.8

V

Symbol

Min

Typ

Max

Unit

±8

~

·VIH (max) =VCC + 0.3 Vdc; VIH (max) =VCC + 2Vac (pulse wldth:5 20 ns)
"VIL (min) = - 3.0 V ac (pulse width:5 20 ns)

DC CHARACTERISTICS
Parameter

= 0 to VCC)
Output Leakage Current (G, Ex = VIH, Vout = 0 to Vcca)
AC Active Supply Current (G, Ex = VIL, lout = 0 rnA,
Input Leakage Current (All Inputs, Yin

Cycle times" tAVAV min,
only one Bank is enabled)
AC Standby Current (El = VIH, E2
Cycle time" tAVAV min)

= VIL,

Ilkg(l)
IlkalO)

-

MCM36232-15 = 15 ns
MCM36232-20 = 20 ns

ICCA15
ICCA20

-

MCM36232-15 = 15 ns
MCM36232-20 = 20 ns

ISBI

-

-

CMOS Standby Current (Ex" VCC - 0.2 V, All Inputs "VCC - 0.2 V or:5 0.2 V)

ISB2

Output Low Voltage (IOL = + 8.0 rnA)

VOL

-

VOH

2.4

Output High Voltage (IOH

=-

4.0 rnA)

NOTE: Good decoupling of the local power supply should always be used.

MOTOROLA MEMORY DATA
6-26

-

-

±8

~

880
800

rnA

300
260

400
360

rnA

100

160

rnA

-

0.4

V

-

-

V

MCM36232

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Input CapaCitance

ET,

Symbol

Typ

Max

Unit

Cin

32
14
24

48
16
32

pF

CliO

14

16

pF

Address
Wl-W4
E2, Gl, G2

InpuVOutput Capacitance (DQO-DQ35)

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Vee = 5.0 V ± 10%, TA =0 to + 70 oe, Unless Otherwise Noted)
Input Timing Measurement Reference level ................ 1.5 V
Input Pulse levels .................................. a to 3.0 V
Input Rise/Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 ns

OutputTiming Reference level. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output load ............ See Figure 1A Unless Otherwise Noted

READ CYCLE TIMING (See Notes 1 and 7)
Symbol
Parameter

MCM36232Z15 MCM36232Z20

Std.

Alt.

Min

Unit

Notes

Read Cycle Time

tAVAV

tRC

15

-

20

-

ns

2

Address Access Time

tAVQV

tAA

-

15

-

20

ns

20

ns

10

ns

4

-

ns

4

Enable Access Time

tElQV

tACS

Output Enable Access Time

tGlQV

toE

-

Output Hold from Address
Change

tAXQX

toH

4

tCLZ

Enable low to Output Active

tElQX

Output Enable to Output Active

tGlQX

toLZ

Enable High to Output High-Z

tEHQZ

tcHZ

Output Enable High to Output
High-Z

IGHQZ

tOHZ

Power Up Time

tElICCH

Power Down Time

tEHICCl

4

Max

Min

-

15

8

-

Max

-

ns

3.4,5

-

ns

3.4,5

8

a
a

9

ns

3,4,5

7

0

8

ns

3.4,5

-

a

-

ns

15

-

20

ns

a
a
a

-

tpu

a

tpD

-

..

NOTES.
1. Wis high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transitloning address.
3. At any given voltage and temperature, tEHQZ max is less than tElQX min, and tGHQZ max is less
than IGHQX min, both for a given device and from device to device.
4. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B.
5. This parameter is sampled and not 100% tested.
S. ~vice is continuously sele£led (E = V'l, G = V,l).
_
7. El-E2 are represented by E in these timing specifications; only one of the Exs may be asserted ..

READ CYCLE 1 (See Note 6 Above)

J

IAVAV

i

A (ADDRESS)

.I

I+-- IAXQX
Q(DATAOUT)

PREVIOUS DATA VALID
IAVQV

l>-----+
5pF
(INCLUDING
SCOPE AND JIG)

255

Figure1A

Figure 18

MOTOROLA MEMORY DATA
6-28

The table of timing values shows either
a minimum or a maximum limit for each
parameter. Input requirements are specified from the external system point of view.
Thus, address setup time is shown as a
minimum since the system must supply at
least that much time (even though most
devices do not require it). On the other
hand, responses from the memory are
specified from the module point of view.
Thus, the access time is shown as a maximum since the module never provides
data later than that time.

MCM36232

WRITE CYCLE 1 (W Controlled, See Notes 1 and 6)
Symbot
Parameter

MCM36232Z15 MCM36232Z20

Std.

Alt.

Min

Max

Write Cycle Time

tAVAV

twc

15

20

Address Setup Time

tAVWL

tAS

a

Address Valid to End of Write

tAVWH

tAW

12

-

Min

Max

Unit

Notes

ns

2

15

-

15

-

ns

-

ns

-

ns

8

ns

3,4,5

4

-

ns

3,4,5

a

-

ns

a

Write Pulse Width

twLWH,
WLEH

twP

12

Write Pulse Width, G High

twLWH,
WLEH

twP

10

-

12

Data Valid to End of Write

tDVWH

tow

7

-

8

Data Hold Time

tWHDX

tDH

-

Write Low to Data High-Z

twLOZ

twz

a
a

Write High to Output Active

tWHOX

tow

4

Write Recovery Time

twHAX

twR

a

-

a
a

7

ns
ns

ns

NOTES:
1. A write occurs during the overlap of E low and Vii low.
2. All write cycle timing is referenced from the last valid address to the first transitioning address.
3. Transition is measured ± 500 mV from steady-state vo~age with load of Figure 1B.
4. This parameter is sampled and not 100% tested.
5. At any given voltage and temperature, twLOZ max is less than tWHOX min both for a given
device and from device to device.
6. E1-E2 are presented by E in these timing specifications; any combination of Exs may be
asserted. G is a don't care when Vii is low.

II

~---------- ~~V---------~
A (ADDRESS) _ _ _oJ
tAVWH

- - - - - - - - 1 + -.........

EX (BYTE ENABLE)
\ + - - - - - - - tWLWH - - - - - - + \

Vi (WRITE ENABLE)

1+---- tDVWH----+l-""*
DATA VALID

HIGH·Z

Q (DATA QUT),----'-"'''''-'''''-----{

MOTOROLA MEMORY DATA
6-29

twHAX

MCM36232

WRITE CYCLE 2 (E Controlled, See Notes 1 and 5)
Symbol
Parameter

MCM36232Z15 MCM36232Z20

Std.

Alt.

Min

Max

Min

Max

Unit

Notes

Write Cycle 11me

tAVAV

twc

15

20

-

ns

2

Address Setup 11me

tAVEL

tAS

0

0

-

ns

Address Valid to End of Write

tAVEH

tAW

12

15

tELEH
tELWH

tcw

10

-

ns

Enable to End of Write

-

Data Valid to End of Wr~e

tOVEH

tow

7

-

8

tEHOX

tOH

0

0

Write Recovery 11me

tEHAX

twR

0

-

-

ns

Data Hold 11me ,

12

0

3,4,5

ns

ns
ns

NOTES:
1. A write occurs during the overlap of E low and iN low.
2. All write cycle timing is referenced from the last valid address to the first transitioning address.
3. If E goes low coincident with or after Wgoes low. the output will remain in a high-impedance
condition.
4. If E goes high coincident with or before iN goes high, the output will remain In a high-impedence
condition.
5. E1 and E2 are represented by E in these timing specifications; any combination of Exs maY be
asserted. G is a don't care when iN is low.

..

tAVAV
A (AODRESS)
tAVEH

Ex (BYTE ENABLE)

Vi (WRITE ENABLE)

o(DATA IN)
HIGH-Z

Q(DATAOUT)

ORDERING INFORMATION
(Order by Full Part Number)

MCM
Motorola Memory p r e f i x J
Part Number

36232

x

xx

T1T

Full Part Numbers - MCM36232Z15

_,"-"~."-"oo'

MCM36232Z20

MOTOROLA MEMORY DATA

Package (Z = ZIP Module)

Application Specific MOS Static RAMs •

MOTOROLA MEMORY DATA
7-1

•

MOTOROLA MEMORY DATA
7-2

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM4180

4K X 4 Bit Cache Address Tag
Comparator
The MCM4180 is a 16,384 bit cache address tag comparator organized as 4096
tags of 4 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology. The device integrates a 4K x 4 SRAM core with an on-board comparator for
efficient implementation of a cache memory.
The device has a CLR pin for flash clear of the RAM, useful for system initialization.
The MCM4180 compares RAM contents with current input data. The result is either an active high MATCH level for a cache hit, or an active low level for a cache
miss.
The MCM4180 is available in 22 lead plastic DIP and 24 lead SOJ packages.
• Single 5 V ± 10% Power Supply
•

Fast Address to MATCH Time:

18/20/22/25 ns max

•
•

Fast Data to MATCH TIME:
Fast Read of Tag RAM Contents:

20/22/25/30 ns max

•

Flash Clear of the Tag RAM (CLR Pin)

•

Pin and Function Comaptible with MK41 H80

_ _G,
PLASTIC
CASE 736A

~

10/10/10/12 ns max

JPACKAGE
300 MIL SOJ
CASE 810A

PIN ASSIGNMENT
DUAL-IN-LINE

BLOCK DIAGRAM

A4

VCC

AS

A3

A6

A2
At

AO-A6

. MEMORY
MAmlX
128 ROWS
x 128 COLUMNS

A8

AO

A9

CLR

AtO

D03

Alt

D02

G
W

w

DOt
DOO
MATCH

VSS
SMALL OUTLINE

DOO-D03------~----~

A4

PIN NAMES

AD--A 11 ............... Address Inputs
IN ...................... Write Enable
G ..................... Output Enable
CLR ................ Flash Clear Input
MATCH .......... MATCH (Hit) Output
DOD--D03 ........... Data Input/Output
VCC .............. + 5 V Power Supply
VSS ......................... Ground
NC ................... No Connection

MOTOROLA MEMORY DATA
7-3

1.

24

J

VCC
A3

AS

2

23

A6

3

221 A2

A7

4

2~ ] AI

A8

S

20

A9

6

19

NC

NC

7

18

CLR

Al0

8

17

D03

All

9

16

D02
DOl

G

AO

10

15

W 11

14

DOO

12

13

MATCH

VSS

•

MCM4180

TRUTH TABLE
W

G

H
L

CLR

DQG-DQ3

MATCH

Mode

H

H

X

H

Compare Din

Valid

Compare

Din

Assert

H

L

Write

H

Dout

Assert

Read

X

X

L

High-Z

Assert

Clear

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to these high impedence circuits.

X = Don t Care
ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS
Rating

Value

Unit

VCC

-0.5to + 7.0

V

Vin, Vout

- 0.5 to VCC + 0.5

V

lout

±40
±20

mA

Power Supply Voltage
Voltage Relative to VSS for Any Pin
ExceptVcc
Output Current

= 0 V)

Symbol

MATCH Output
1/0 Pins, per 110

Power Dissipation (TA = 25°C)

PD

1.0

W

Operating Temperature

TA

a to + 70

°C

Tstg

-55to+ 125

°C

Storage Temperature
Temperature Under Bias

-10to+85
°C
Tbias
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

•

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Vce = 5.0 V ± 10%, TA = 0 to + 70 oe, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Referenced to VSS = 0 V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

Input Low Voltage

VIL

-as

-

0.8

V

Min

Max

Unit

-

± 1.0
± 1.0

IIA
IIA

ICCA

-

140'

mA

VOL

-

0.4

V

VOH

2.4

-

V

Parameter

, VIL (min) -

- 0.5 V dc, VIL (min) - - 2.0 V ac (pulse Width" 20 ns).

DC CHARACTERISTICS
Symbol

Parameter
Input Leakage Current (All Inputs Yin

=a to VCC)

Output Leakage Current, Except MATCH Output (G
AC Supply Current (lout

Ilkg(l)

= VIH, Vout =a to Vccl

=a mA, All Inputs = VIL or VIH, Cycle Time" tAVAV min)

Output Low Voltage (1/0 Pins: 10L = 8.0 mA, MATCH Output: 10L = 12.0 mAl
Output High Voltage (1/0 Pins: 10H

=-

4.0 mA, MATCH Output: 10H

=-

10.0 mAl

..

Ilkg(O)

"
'ICC active current for the clear cycle exceeds this specification.
However, this IS a transient phenomenon and Will not affect the power dissipation of
the device. Good decoupling of the local power supply should always be used.

CAPACITANCE (f

= 1.0 MHz, dV = 3.0 V, T A = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic

Input Capacitance

1/0 Capacitance
MATCH Output Capacitance

MOTOROLA MEMORY DATA

7-4

Symbol

Typ

Max

Cin

4

5

pF

Cout

5

7

pF

Cmatch

6

7

pF

Unit

MCM4180

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5 V ± 10%, TA =0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level ........ 1.5 V
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 3.0 V
Input RiselFall Times ............................. 5 ns

Output Timing Measurement Reference Level ....... 1.5 V
Output Load (1/0 Pins) ................... See Figure 1a
Output Load (MATCH Output) .............. See Figure 1c

READ CYCLE (See Note 1)
Symbol
Parameter

MCM41BO-18 MCM41BO-20 MCM41BO-22 MCM41BO-25

Standerd Altemate

Read Cycle Time

tRC

tAVAV

Max

Min

Max

Min

Max

Min

20

-

22

-

25

-

30

-

ns

-

22

-

25

-

30

ns

12

ns

0

0

ns

Address Access Time

tAVOV

tAA

-

20

G Access Time

IGLOV

tOEA

-

11

Output Hold from Address Change

tAXOX

tOH

0

12

12

Min

Max

Unit

Notes

G Low to Output Active

IGLOX

'eEL

3

-

3

-

5

-

5

-

ns

2

G High to Output High-Z

IGHOZ'

'eEZ

-

7

-

8

-

8

-

10

ns

2

G Low to MATCH Assert

IGLMX

tcH

0

8

0

10

0

10

0

12

ns

0

NOTES:
1. CLR = VIH, W= VIH continuously during read cycles.
2. Transition is measured ± 500 mV from steady state voltage wtth load of Figure 1b. This parameter is sampled and not 100% tested.

READ CYCLE
(G CONTROLLED)

(ADDRESS CONTROLLED)

~ ...

tAVAV
A (ADDRESS)
tAVQV

G(OUTPUT ENABLE) •

t

lAVAV

IGLQ
Q(DATAOUl)

DATA VALID

-

HIGH-Z
IGLM

(ASSERTED)

MATCH

AC TEST LOADS
+5V

+5V

+5V

481

481

305

Q - p - - - -...

Q - p - - - -...
30pF
(INCLUDING
SCOPE AND JIG)

255

MATCH-p----...
5pF
(INCLUDING
SCOPE AND JIG)

255

-=-

-=-

Figure la

Figure lb

MOTOROLA MEMORY DATA
7-5

50 pF
(INCLUDING
SCOPE AND JIG)

130

Figure Ie

•

MCM4180

COMPARE CYCLE (See Note 1)
Symbol
Characteristic
Compare Cycle Time

MCM4180·18 MCM4180-20 MCM4180·22 MCM4180·25

Standard Alternata
tAVAV

Ie

Min

Max

Min

Max

Min

Max

Unit

20

-

22

-

25

-

30

-

ns

18

20

-

25

ns

15

-

18

ns

10

-

22

10

-

10

-

12

ns

Min

Max

Address Valid to MATCH Valid

tAVMV

tACA

G High to MATCH Valid

taHMV

taCA

Oata Valid to MATCH Valid

tOVMV

tOCA

-

MATCH Hold from Glow

tG'LMX

leH

0

10

0

10

0

10

0

12

ns

MATCH Hold from Address
Change

tAXMX

tACH

5

-

5

-

5

-

5

-

ns

MATCH Hold from Oata Invalid

tOXMX

tOCH

3

-

3

-

3

It.z

3

-

3

5

-

5

-

ns

talQX

-

3

G low to Output Active

-

8

-

8

-

8

-

10

G High to Output High-Z

15

15

ns

Notes

2

ns

2
tHZ
tGHQZ
NOTES:
1. A compare cycle is performed when ClR. W. and G are all high.
2. Transition is measured ± SOO mV from steady state voltage with load of Figure 1b. This parameter is sampled and not 100% tested.

COMPARE CYCLE
(ADDRESS CONTROLLED)

..

(G CONTROLLED)

- r___>c

A (ADDRESS)

-!=tAVMV
G(OUTPUT
ENABLE)

D(DATAIN)

IGHQ
Q (DATA OUT)

MATCH

-------+_ HIGH,Z - - - 4 - MATCH VALID

MOTOROLA MEMORY DATA
7-6

MCM4180

WRITE CYCLE (See Note 1)
Symbol
Characteristic

MCM4180·18

MCM418D-20

Standard

Alternate

Min

Max

Min

Wrile Cycle Time

IAVAV

twc

20

-

22

Wrile Pulse Width

twLWH

twEW

12

-

Address Selup 10 Beginning of
Wrile

IAVWL

tAS

0

-

Address Valid to End of Write

tAVWH

tAW

16

tos

10

twHOX

tOH

0

-

0

twLOZ

1HZ

0

8

twHAX

tWAH

0

-

Oala Valid 10 End of Write
Oala Hold from Wrile End
Wrile Low to Outpul High-Z
Address Hold from Wrile End

tOVWH

Wrile Low to MATCH Assert

twLMX

twCH

Wrile High 10 MATCH Valid

tWHMV

twCA

-

Wrile High 10 Oulput Active

twHOX

tLZ

3

Max

MCM4180·22

MCM418D-25

Min

Max

Min

-

25

-

30

14

-

18

-

20

0

-

0

-

16

-

18

10

-

10

-

0
0

Max

Unit

-

ns

-

ns

0

-

20

-

ns

-

12

-

ns

0

-

0

-

ns

8

0

9

0

10

ns

-

0

-

0

-

ns

Notes

ns

20

0

15

0

15

0

15

ns

20

-

20

-

22

-

25

ns

-

3

-

5

-

5

-

ns

2

2

NOTES:

1. A wrile occurs during Ihe overlap of Wlow and CLR high.
2. Transition is measured ± 500 mV from steady state voltage with load of Figure 1b. This parameter is sampled and not 100% tesled.

WRITE CYCLE
(FROM A READ CYCLE)

(FROM A COMPARE CYCLE)

•

A (ADDRESS)

G(OUTPUT
ENABLE)

W(WRITE
ENABLE)

D (DATA IN)

Q(DATAOUT)

MATCH

(ASSERTED)

MOTOROLA MEMORY DATA
7-7

MCM4180

CLEAR CYCLE (See Note 1)
MCM4180-18 MCM4180-20 MCM4180-22 MCM4180-25

Symbol
Characteristic

Min

Max

Min

Max

Min

Max

Min

Max

Unh

Notas

-

70

-

70

-

70

-

70

ns

2

teLP

20

2

tex
tex
tcx
tex

0

-

ns

0

-

30

0

-

25

tCLAX
teLGX
teLDX
tCLWX

-

22

0

Ci:R Low to MATCH Assert

teLMX

tMH

0

15

0

15

0

15

0

18

ns

CLR Low to Output High-Z

teLQZ

tcz

-

15

-

15

-

15

-

18

ns

Slandard Alternata

CLR Low to Inputs Recognized A
(Clear Cycle Time)
G

W
0

CLR Pulse Width
CLR Low to Inputs Don't Care

A

G
0

W

tCLAV
teLGV
tCLWV
teLDV

teR
tCR
tCR
tCR

teLCH

ns

3

NOTES:
1. The address, data, W, and G inputs are a don't care during a clear cycle.
2. The clear cycle is initiated at the falling edge of CLR.
3. Transnion is measured ± 500 mV from steady-state voltage with load of Figure 1b. This parameter is sampled and not 100% tested.

CLEAR CYCLE
(FROM A READ CYCLE)

(FROM ACOMPARE CYCLE)

r-tcLAX~

•

A(ADDRESS) _ - - : - ,___
' -..Jl"""'XX""""X""""'X""""X""""'X>

~ 0.8
>

~.;:0.6 V

V

V

"

~

./

::::>

....

c..> 1.0
~

1""

it
iil

........

~

..........

r-.......

.;: 0.9

g

4.0

4.5
5.0
5.5
Vcc, SUPPLY VOLTAGE (VOLTS)

~

6.0

Figure 2. Active Supply Current versus Supply Voltage

",

-10 0
25
50
70
90
TA, AMBIENT TEMPERATURE (0e)

.........
130

Figure 3. Active Supply Current versus Temperature

1.1

./
/'

"

./

........

./

r--......

./

..........

./

..... ......

./

r--..... .....

./

V

20

..........

22

24
26
lAVAV, CYCLE TIME (ns)

28

/'

1.0
50

30

Figure 4. Active Supply Current versus Cycle TIme

100

150
200
TA, AMBIENT TEMPERATURE (OC)

250

300

Figure 5. Address to MATCH Access TIme versus
MATCH AC Test Load Capacitance of Figure 1c

.;'

"' "-

./

,/

I'

"'

V
V

I'....
r--......

","

.........
0.8
4.0

/'

"

.......... r-.

V

L

0.7
4.5
5.0
5.5
Vcc, SUPPLY VOLTAGE (VOLTS)

~

6.0

Figure 6. Address to MATCH Access Time versus
Supply Voltage

0255070
TA, AMBIENT TEMPERATURE (OC)

150

Figure 7. Address to MATCH Access Time versus
Temperature

MOTOROLA MEMORY DATA
7-9

•

MCM4180

~1.3

~

f§ 1.2
~

w
::;

>=

./

" "-

/

1.1

"'-

!i3
~:> 1.0
~

'"

...........
1-_

- 0.9

4.0

4.5
5.0
5.5
VGG. SUPPLY VOLTAGE (VOLTS)

-

,.

V

/'

V

V

./

./
0.7

6.0

-so

lSO

0255070
TA. AMBIENT TEMPERATURE (oG)

Figure 8. Data to MATCH Access Time
versus Supply Voltage

Figure 9. Data to MATCH Access Time
versus Temperature

I\..

V

"-

./

./

" -r--....

II

0.8
4.0

'"

../

-

./'
I-"~

i--"
/'

4.5
5.0
5.5
VGG. SUPPLY VOLTAGE (VOLTS)

0.8

6.0

Figure 10. Output Enable to MATCH Access Time
versus Supply Voltage

V'
-SO

150

0255070
TA, AMBIENT TEMPERATURE (oG)

Figure 11. Output Enable to MATCH Access Time
versus Temperature

./'

I"-..

~

......

r.......

,.

.......... I--..

"r-. r-4.5
5.0
5.5
VGG. SUPPLY VOLTAGE (VOLTS)

/'

/'

V

V

V

..... 1-"
./~
6.0

0255070
TA, AMBIENT TEMPERATURE (oG)

Figure 13. Write Pulse Width versus Temperature

Figure 12. Write Pulse Width versus Supply Voltage

MOTOROLA MEMORY DATA
7-10

lSO

MCM4180

6

~

~ 1.4

..........

~

..........

r·

I'....

..........

l5

.........

o

...... ~

r---....

~::::;

0.8

s:

0.6

4.5
5.0
5.5
Vee, SUPPLY VOLTAGE (VOLTS)

V

i--'

w

!:j

6

v

!
~

~ 1.0

~

V

-'

:>

4.5
5.0
5.5
Vee, SUPPLY VOLTAGE (VOLTS)

0.8

6.0

4.0

4.5
5.0
5.5
Vee, SUPPLY VOLTAGE (VOLTS)

6.0

Figure 17. Input Low Voltage versus Supply Voltage

60

60

_54 ~

"\
§.48
>-

54

~

w

"\

42

II:

gs 36
<>
~ 30
24

'\..
I\..

~ 24

"- .........

~ 18
12

C!.

~

1.4

./

'[48

'\.

gs36
<>
~ 30

1.0

-

,,/

~

Figure 16. Input High Voltage versus Supply Voltage

o

........ "

~

;;;;

0.8
4.0

ai42
II:

..... /

>

........-

"

I,..ooo~ I-""'""

w

..... V"

;;;;
::f.
:>

1.2

~

,,/'

~
:J:
'3
a..

150

Figure 15. Data Setup Time versus Temperature

/'

§; 1.0

r--

0255070
TA, AMBIENT TEMPERATURE ("C)

Figure 14. Data Setup Time versus Supply Voltage

Cl

..........
~

6.0

6 1.2
~

lL

~

o

!

.".....

2

1.0

zw

......... i'oo"

.".....

1.8

......

~

"'-

2.2 2.6
3.0 3.4 3.8
VOU!' OUTPUT VOLTAGE (VOLTS)

C!.

.Q

r- r-4.2

4.6

5.0

Figure 18. Output Source Current versus
Output Voltage

18
12
6

o0.0/ '

/'

/'

/'

0.2

V

V

/'

/'

0.4
0.6
Vou!. OUTPUT VOLTAGE (VOLTS)

0.8

Figure 19. Output Sink Current versus
Output Voltage

MOTOROLA MEMORY DATA
7-11

1.0

..

MCM4180

ORDERING INFORMATION
(Order by Full Part Number)

MCM
Motorola Memory prefix---=rPart Number

x

T

xx

T

XX

~

~

Shipping Method (R2 =Tape & Reel, Blank =Rails)
Speed (18 = 18 ns, 20 = 20 ns, 22 = 22 ns, 25 = 25 ns)

' - - - - - - - - - Package (P = Plastic DIP, J = Plastic SOJ)
Full Part Numbers -

MCM4180P18
MCM4180J18
MCM418OJ18R2

MCM4180P20
MCM418OJ20
MCM418OJ20R2

MCM4180P22
MCM418OJ22
MCM4180J22R2

•

MOTOROLA MEMORY DATA
7-12

MCM4180P25
MCM418OJ25
MCM418OJ25R2

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - MCM6293
16K x 4 Bit Synchronous Static RAM

TECHNICAL DATA

with Output Registers
The MCM6293 is a 65,536 bit synchronous static random access memory
organized as 16,384 words of 4 bits, fabricated using Motorola's second-generation
high-performance silicon-gate CMOS (HCMOS III) technology. The device integrates
input registers, high speed SRAM, and high-drive capability output registers onto a
single monolithic circuit for reduced parts count implementation of cache data RAM
and writeable control store applications. It is well suited for telecommunications
switches and test equipment.
Synchronous design allows precise cycle control with the use of an external clock
(K), while CMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
The address (Ao-A13), data (00-03), write (Vii), and chip enable (E) inputs are all
clock (K) controlled,positive-edge-triggered, noninverting registers.
The MCM6293 provides output register operation. At the rising edge of K, the RAM
data from the previous K high cycle is presented. This function is well suited to fully
pipelined applications.
Write operations are internally self-timed and initiated by the rising edge of the K
input. This feature eliminates complex off-chip write pulse generation and provides
increased flexibility for incoming signals.
The MCM6293 is available in a 300-mil, 28-pin plastic DIP as well as a 300-mil,
28-pin plastic SOJ package.
• Single 5 V ± 10% Power Supply
• Fast Cycle Times: 20/25 ns Max
• Fast Clock (K) Access Times: 10 ns Max
• Address, Data Input, E, and Vii Registers On-Chip
• Output Registers for Fully Pipelined Applications
•
•
•
•
•

High Output Drive Capability
Internally Self-Timed Write Pulse Generation
Separate Data Input and Data Output Pins
High Board Density SOJ Package Available
Typical Applications: General-Purpose Buffer Storage, Writeable Control Store,
Data Cache, or Cache Tag

BLOCK DIAGRAM

~

PPACKAGE
300 MIL PLASTIC
CASE 710A

.->

NJPACKAGE
300MILSOJ
CASE 810B

PIN ASSIGNMENT

A5

Vee
A4

AS
A7

A3

AS

A2

Afl

A1

A10

AO

A11

03

A12

02

A13

03

DO

02

D1

01

E

QO

K

W
VSSO'

VSS

'For proper operation of the device, both
VSS and Vssa must be connected to
ground.

QO
01
02
03

I

'------t--J I
VSSO--.c. - - .J

MOTOROLA MEMORY DATA
7-13

PIN NAMES

AD-A 13 ............... Address Inputs
W ....................... Write Enable
E ....................... Chip Enable
00-03 ................... Data Inputs
aQ-Q3 ....... . . . . . . . . .. Data Outputs
K ........................ Clock Input
VCC .............. + 5V Power Supply
VSS ........................ Ground
Vssa . . . . . . . ... Output Buffer Ground

•

MCM6293

TRUTH TABLE
E

W

Operation

Q~3

L

L

Write

HighZ

L

H

Read

Dout

X

HighZ
Not Selected
..
..
NOTE: The values of E and Ware vahd Inputs for the setup and hold times relative to the K rising
edge.
H

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = VSSQ = 0 V)
Rating

Symbol

Value

Unit

VCC

-0.5to + 7.0

V

Yin. Vout

- 0.5 to VCC + 0.5

V

Output Current (per 1/0)

lout

± 20

rnA

Power Dissipation (TA = 25°C)

PD

1.0

W

Temperature Under Bias

Tbias

-10to+85

°c

Operating Temperature

TA

oto + 70

°c

Power Supply Voltage
Volt!ige Relative to VSsNSSQ for Any
Pin Except VCC

Storage Temperature

-55to+ 125
°c
Tsta
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

This device contains circuitry to
protect the inputs against damage
due to high static voltages or electric
fields; however. it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to this high impedence circuit.
This is a synchronous device. All
synchronous inputs must meet the
specified setup and hold times with
stable logic levels for ALL rising
edges of clock (K) while the device is
selected.
This device contains circuitry that
will ensure the output devices are in
High Z at power up. Care should be
taken by the user to ensure that all
clocks are atVIL orVIH during power
up to prevent spurious read cycles
from occurring.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ± 10%. T A = 0 to 70 oe. Unless Otherwise Noted)

•

RECOMMENDED OPERATING CONDITIONS (Voltages referenced to vss = vSSQ = 0 V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

VIL

-OS

-

0.8

V

Parameter

.

Input Low Voltage

VIL (min) = - 0.5 V dc; VIL (min) = - 3.0 V ac (pulse width,;; 20 ns)

DC CHARACTERISTICS
Parameter

Symbol

=0 to VCe>
Output Leakage Current (E =VIH. Vout =0 to VCC. Outputs must be high-Z)
AC Supply Current (E =VIL. lout =0 rnA. All Inputs =VIH or VIL.
Input Leakage Current (All Inputs. Yin

Min

Max

Unit

Ilkg(l)

-

±1.0

I'A

Ilkg(O)

-

±1.0

I1A

ICCA

-

140

rnA

ISBI

-

55

rnA

VOL

-

0.4

V

VOH

2.4

-

V

Symbol

Typ

Max

Unit

Cin

4

6

pF

Cout

7

10

pF

Cycle Time", tKHKH min)
Standby Current (E

=VIH; Other Inputs =VIH" 3.0 V or VIL S 0.4 V; lout =0 rnA.

Cycle Time" tKHKH min)
Output Low Voltage (lOl

=12.0 rnA)
=- 10.0 mAl

Output High Voltage (IOH

CAPACITANCE (f =1.0 Mhz. dV = 3.0 V. TA =25°C. Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance
Output Capacitance

MOTOROLA MEMORY DATA
7-14

MCM6293

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vce = 5.0 V ± 10%, TA = 0 to + 70 o e, Unless Otherwise Noted)
Input Timing Measurement Reference Level ........ 1.5 V
Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 3.0 V
Input Rise/Fall Time .............................. 5 ns

Output Timing Measurement Reference Level ....... 1.5 V
Output Load ...... See Figure 1A Unless Otherwise Noted

READ CYCLE (See Note 1)
Parameter

Read Cycle Time

MCM6293-20

MCM6293-25

Symbol

Min

Min

-

25

-

ns

2

-

10

ns

3

Max

tKHKH

20

Clock Access Time

tKHOV

-

10

Output Active from Clock High

Max

Unit

Notes

tKLOX

0

-

0

-

ns

4

Clock High to 0 High Z (E = VIH)

tKLOZ

-

10

-

10

ns

4

Clock Low Pulse Width

tKLKH

5

5

-

ns

5

-

ns

5

-

ns

5

3

-

ns

5

Clock High Pulse Width
Setup Times for:

E
A

W
Hold Times for:

E

A

W

tKHKL

5

tEVKH
tAVKH
twHKH

5

-

tKHEX
tKHAX
tKHWX

3

-

NOTES:

A read is defined by Whigh and E low for the setup and hold times.
All read cycle timing is referenced from K.
Valid data from K high will be the data stored at the address of the last valid read cycle.
Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled not 100% tested. At any given
voltage and temperature, tKHOZ max is less than tKHOX min for a given device.
5. Tihis is a synchronous device. All synchronous inputs must meellhe specified setup and hold times with stable logic levels for ALL rising edges
of clock (K) while the device is selected.
1.
2.
3.
4.

AC TEST LOADS
+5V

+5V
305n

305ll

0 ......- - - -..
130n

0 ......_ - - -..
130 pF
(INCLUDING
SCOPE AND JIG)

5 pF
(INCLUDING
SCOPE AND JIG)

130n

=

=

Figure 1A

Figure1B

MOTOROLA MEMORY DATA
7-15

•

MCM6293

READ CYCLE 1 (See Note 1)

K(CLOCK)

'E (CHIP ENABLE)

A (AODRESS)

Vi (WRITE ENABLE)

o(DATA OUT)

•

On-3

READ CYCLE 2 (See Note 1)

K(CLOCK)

'E (CHIP ENABLE)

A (AODRESS)

Vi (WRITE ENABLE)

o(DATA OUT)
NOTES:
1. The outputs an _ 3 and an _ 2 are derived from two previous read cycles where iN • VIH and E = VIL for those cycles.

MOTOROLA MEMORY DATA
7-16

MCM6293

WRITE CYCLE (W Controlled See Note 1)
MCM6293-20

MCM6293-25

Symbol

Min

Min

Max

Unit

Write Cycle Time

tKHKH

20

-

25

-

ns

2

Clock High to Output High Z (W = VIU

tKLOZ

-

10

-

10

ns

3

Parametar

Max

Notes

Setup Times for:

E
A
W
0

tEVKH
tAVKH
twLKH
IDVKH

5

-

5

-

ns

4

Hold Times for:

E
A
W
0

IKHEX
tKHAX
tKHWX
tKHDX

3

-

3

-

ns

4

NOTES:

1. A write is performed when Wand E are both low for the specified setup and hold times.
2. All write cycle timing is referenced from K.
3. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled not 100% tested. At any given
voltage and temperature, tKHOZ max is less than tKHOX min for a given device.
4. This is a synchronous device. All synchronous inputs must meetthe specified setup and hold times with stable logic levels for ALL rising edges
of clock (K) while the device is selected.

WRITE CYCLE
1 + - - - - - tKHKH - - - - + I
K(CLOCK)

_ _ _ _...J

•

E(CHIP ENABLE)

A (ADDRESS)

W(WRITE ENABLE)

o(DATA IN)

o(DATA OUT)

On-2

On-l

MOTOROLA MEMORY DATA
7-17

1 - - - - - HIGH-Z - - - - -

MCM6293

0w 1.40

0w 1.20

...
!::!

~

c(

:::E
a:
0

1.20

:::E

!Z
w

1.00 -

~

VCC=5V
TA=25°C

a:
a:

::>

<.> 0.80
~

CL.
CL.

::>

en 0.60
w

~

~

0.40

V

c(

.? 0.20

V
10

L

V

a: 1.15

V

0

zw 1.10

a:
a:

::>

<.> 1.05
~

CL.
CL.

./

::>

en 1.00

30

40

0.95

80.90
-75-50

70

60

50

,/"

V

L

V
./

w

~

20

VCC=5V

~

I-

t, FREQUENCY (MHz)

-25

0

25

50

75

100

125

150

TA, AMBIENT TEMPERATURE (OC)

Figure 2. Active Supply Current versus Frequency

Figure 3. Active Supply Current versus Temperature

1.03
I

11.00
~

0.97

/

!Z

~

0.94

i

0.91

G

•

1/

VCC=5V

/

;'!:
en

/

~ 0.88

en

/

0.85

V
10

20

30

40

50

60

70

t, FREQUENCY (MHz)

Figure 4. Standby Current versus Frequency

30

120

\
\

<"

§. 25

I-

zw

a: 20
a:

::>

<.>

/

:I:

!2 15
::>

50

10

:I:

5'

o

/

\

o

0.5

1.0

1.5

2.0

2.5

/

V

\
\

:I:
I-

/

3.0

3.5

4.0

4.5

o

/

o

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

YOU!' OUTPUT VOLTAGE (VOLTS)

YOU!' OUTPUT VOLTAGE (VOLTS)

Figure 5. Output Source CUrrent versus Output Voltage

Figure 6. Output Sink Current versus Output Voltage

MOTOROLA MEMORY DATA
7-18

MCM6293

C 1.3

1.4

~

C

w

!:>!

:;;! 1.3

VGG~5V

:::;;

II:

0

;;;. 1.2
w

:::;;

>=
w

<3
>

u

'"US

1.1

,./

1.0

V

II:

~ 0.9
::c

V

V

./

::: 1.2

/

VGG~5V

~

,./"

!:!;l 1.1

>=

~

1.0

§ 0.9

/

./

,./

/

V

u

i5 O.B
2

}!'

O.B
-75

0.7

-50

-25
25
50
75
100
TA, AMBIENT TEMPERATURE (oG)

125

150

Figure 7. Read Cycle TIme versus Temperature

-75

-25
a 25 50 75 100
TA, AMBIENT TEMPERATURE (oG)

125

150

Figure 8. Clock Access Time versus Temperature

APPLICATIONS INFORMATION
The Motorola family of synchronous SRAMs is designed to provide a performance and parts count advantage in applications such
as writeable control stores, memory mapping, and cache memory. The on-board input registers eliminate the need for external latch
chips in systems where addresses and data are not on the bus long enough to satisfy standard SRAM setup and hold times.
Registers on the output port provide extended hold times independent of address or other device input changes to better meet
system access requirements. The clock (K) input controls the operation of the input registers and output registers, and provides
a direct means of synchronizing the SRAM to a system clock.
The MCM6293 offers registered output operation. On the rising edge of the clock (K) signal, the output data for the previous cycle
is latched until the next rising clock edge.
Figure 9 shows a typical system configuration using four MCM6293 chips. The system addresses are tied to the MCM6293s in
parallel, while system data is distributed among the four input data ports of 4 bits each. Output data is tied to a separate output data
bus to exploit the separate I/O configuration of the MCM6293. The clock (K) signal is a logical derivation of the system clock.
Figure 10 shows typical bus timing for the configuration of Figure 9. The system bus supplies address, data, and control signals,
while accepting data from the memory on rising clock edges. In some applications, the clock (K) signal may need to be a delayed
system clock to allow adequate address and data setup times.

MOTOROLA MEMORY DATA
7-19

•

MCM6293

SYSTEM
ADDRESSES

14

It 14

SYSTEM
CLOCK

14

AG-A13
~K

**-

-

E
MCM6293

W

SYSTEM
DATA IN

16

OUTPUT
DATA BUS

16

*From read/write controller.

**r

DQ-D3

4

L....., K

*_

E

,

4

E

MCM6293

MCM6293

W

*-

W

00-03

r

00-03

4
00-03

AQ-AI3

AG-A13
L....., K

4
QQ-Q3

MOTOROLA MEMORY DATA

--**---

K

E
MCM6293

W
00-03

QD-03

QD-03

4

4

Figure 9. Typical Configuration for a 16-Blt Bus

•

AQ-AI3

4

4

7-2lJ

It 14

14

s:
s:

o
SYSTEM-GENERATED
SIGNALS
SYSTEM CLOCK

0

I

20

I

40

I

60

I

60

I

100

I

120

I

160

I

200

I

240

Ir------'L

ADDRESS

CONTROL

WRITE DATA

s::

~JJ
o

-.I

~

MCM6293 CONTROL
AND OUTPUT SIGNALS
K(CLOCK)

>
s::
m

s::
oJJ
-<
o

W (WRITE ENABLE)

»~

E (CHIP ENABLE)

On+ 5

QO-Q3 (DATA OUT)

120

160

NOTES:
1. The syslem supplies address, data, and control information and accepts data from memory on the rising edge of the system clock.
2. The memory clock is delayed IOns (for this example) to allow input information to propagate to the memory chips.

Figure 10. Pipeline System Timing

200

~

MCM6293

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory

prefiX~

Part Number

TT
x

xx

XX

T

'"""","""'~""'"

"HI. , ... - ".,,'

Speed (20 = 20 ns, 25 = 25 ns)

' - - - - - - - - Package (P = Plastic DIP, NJ = Plastic SOJ)
Full Part Numbers -

MCM6293P20
MCM6293P25

MCM6293NJ20
MCM6293NJ25

MCM6293NJ20R2
MCM6293NJ25R2

•

MOTOROLA MEMORY DATA
7-'12.

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6294

16K x 4 Bit Synchronous Static RAM
with Output Registers and Output Enable
The MCM6294 is a 66,536 bit synchronous static random access memory organized as
16,384 words of 4 bits, fabricated using Motorola's second-generation high-performance
silicon-gate CMOS (HCMOS 1111 technology. The device integrates input registers, high
speed SRAM, and high-drive capability output registers onto a single monolithic circuit for
reduced parts count implementation of cache dete RAM and writeable control store applications. Synchronous design allows precise cycla control with the use of an external clock
(KI, while CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability. It is well suited for telecommunications switches and test
equipmant.
The address (AO-A131, dets (00-031, and write (WI inputs are all clock (KI controlled,
positive-edge-triggered, noninverting registers.
The MCM6294 provides output registsr operation. At the rising edge of K, the RAM
dets from the previous K high cvcIa is presented. This function is well suited to fully pipelined applications.
The output enable fGI provides asynchronous bus control for common I/O or bank
switch applications.
Write operations are intsrnally self-timed and initiated by the rising edge of the K input.
This feature eliminates complex off-chip writs pulse generation and provides increased
flexibility for incoming signals.
The MCM6294 is available in a 300-mil, 28-pin plastic DIP as well as a 300-mil, 28-pin
plastic SOJ package.
•
•
•
•
•
•
•
•
•
•
•

Single 6 V ± 10,*, Power Supply
Fast Cycle Times: 20/26 ns Max
Fast Clock (KI Access TImes: 10 ns Max
Address, Oats Input, and W Registsrs On-Chip
Output Enable for Asynchronous Bus Control
Output Registers for Fully Pipelined Applications
High Output Drive Capability
Intsrnally Self-TImed Write Pulse Genaration
Separate Oats Input and Oats Output Pins
High Board Density SOJ Package Available
Typical Applicationa: General-Purpose Buffer Storage, Writsable Control Store, Oats
Cache, or Cache Tag

300 MIL PLASTIC
CASE710A

~ACKAGE
3OOMILSOJ
CASE810B

PIN ASSIGNMENT
A5 I 1.

28

A6 I 2

27

A4

A7 I 3

26

A3

A8 I 4

25

A2

A9

5

24

Al

AID

8

23

AD

All

7

22

03

A12

8

21

02

A13

9

20

03

DO

10

19

02

01

11

18

Ql

12

17

DO

13

16 IV

G

Vss 14

15

Vee

Vsso*

*For proper operation of the
device, both VSS and Vssa
must be connectad to ground.

BLOCK DIAGRAM

PIN NAMES
AO-A 13 . . . • . . . . . Address Inputs
W. . . . . . . . . . . . . Write Enable
G . . . . . . . . . . .. OUlput Enable
00-03 . . . . . . . . . . . Data Inputs
QO-Q3 . • . • . . • • • • Data Oulputs
K . . . . . . . . . . . . . • Clock Input
VCC . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . Ground
Vssa . . . . . Output Buffer Ground

MOTOROLA MEMORY DATA
7-23

•

MCM6294

TRUTH TABLE

1I

W

Operation

00-03

X

L

Write

HighZ
Dout
HighZ

L

H

Read

H

H

Output Disable

NOTE: The value W is a valid input for the setup and hold timea relative to the K rising
adge. Tha value "G is an aaynchronous input.

ABSOLUTE MAXIMUM RATINGS (Voltages referencad to Vss=Vssa=O VI
RatIng

Symbol

Valua

Unit

VCC

-0.5 to +7.0

V

Yin, Vout

-0.5 to VCC+0.6

V

Output Currant (par 1/01

lout

±2O

mA

Power DIssipation ITA = 26·CI

Po

1.0

W

Tbias

-10to +86

·C

Power Supply Voltage
Voltage Relative to VsslVssa for Any
Pin Except VCC

Tempereture Under Bias
Operating Tempereture

TA

Storege Tempereture

Tata

oto

+70

-56 to + 126

This device contains circuitry to protect the
inputs ageinst damage due to high static
voltagea or electric fields; howevar, it is advlaad that normal pracautlons be taken to
avoid applicatlcn of any voItsge higher then
maximum rated voltagea to this hlghimpedance circuit.
This is a synchronous device. All synchronous Inputs must meat the speciflad satup
and hold times with stable logic levels for
ALL rising adges of clock IKI whlla the device is selected.
This device contains circuitry that will ensure the output devices are in High Z at
power up. Care should be taken by the user
to ensure that all clocks are at VIL or VIH
during power up to prevant spurious read
cycles from occurring.

·C
·C

NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are
exceadad. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voItsgea for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ± 10%, TA=O to 700C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS IVoltages referencad to Vss=Vssa=O VI

•

Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Rangel

Psram_

VCC

4.5

5.0

5.6

V

Input High Voltage

VIH

2.2

VCC+0.3

V

Input Low Voltage

VIL

-0.5*

-

0.8

V

Symbol

Min

Max

Unit

±1.0

pA

*VIL (mini = -0.6 V dc; VIL Iminl = -3.0 V ac (pulse width :520 nsl

DC CHARACTERISTICS
Psramater
Input Leakage Current (All Inputs, Vin=O to VCCI

Illcglll

Output Leakage Current fG=VIH, Vout=O to VCC, Outputs must be hlgh-ZI

IlkalOI

AC Supply Current (~= VIL, lout = 0 mA, Cycle

nme = .tKHKH mini

ICCA

-

±1.0

pA

140

mA

Output Low Voltage (lOL = 12.0 mAl

VOL

-

0.4

V

Output High Voltage (lOH = -10.0 mAl

VOH

2.4

-

V

Symbol

Typ

Max

Unit

Cin
Cout

4

6

pF

7

10

pF

CAPACITANCE If= 1.0 MHz, dV=3.0 V, TA = 25·C, Periodically Sampled Rather Than· 100% Testadl
Characteristic
Input Capacitance
Output Capacitance

MOTOROLA MEMORY DATA

7-24

MCM6294

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0V ±10%, TA=Oto +70o C, Unless Otherwise Notedl
Output TIming Measurement Reference Level . • . • . • • •. 1.5 V
Output Load . . . . . . . . . • See Figure lA Unless Otherwiee Noted

Input TIming Measurement Reference Level . . • . . . . . . • 1.5 V
Input Pulse Levels . . • . . . • . • • . . . . . . . . . . . . .0 to 3.0 V
Input Rise/Fall Time • . • . . . • . . . . . • . . . . . . . . • • • • 5 ns

READ CYCLE (See Note 1)
Parameter

Symbol

MCM8294-211

MCM6Z84-2Ii

Min

Max

Min

Unit

Notaa

Max

Read Cycle Tima

tKHKH

20

-

25

-

ns

2

Clock Access Tnna

tKHQV

-

10

-

10

ns

Output Active from Clock High

tKHQX

Clock Low Pulse Width

tKLKH

0
5

3
4

Clock High Pulse Width
Setup TImes for:

A

W
Hold TImes for:

A

W

tKHKL

5

-

tAVKH
IWHKH

5

-

5

-

tKHAX
tKHWX

3

-

3

10

-

~ High to Q High Z

tGHOZ

-

~ Low to Q Active

tGLQX

0

~ Low to Q Valid

IGLQV

-

0

-

5
5

10

ns
n.

ns
lIS

5

-

lIS

5
4,6
4,6

10

ns

0

-

ns

-

10

lIS

NOTES:
1. A read is defined bV W high for the setup and hold times.
2. All read cycle timing i. referenced from K or from~.
3. Valid data from K high will be the data atored at the address of the leat valid read evele.
4. Transition is measured ± 500 mV from steady·state voltage with load of Figure 1B. This parameter is aamplad not 100% testad.
5. This is a synchronous device. All synchronous inputs must meat the spacified setup and hold times with stable logic levals for ALL rising
adges of clock (K) while the device i. sslectad.
6. At any given voltage and temperature, tGHOZ max i. less than IGLQX min for a given device.

AC TEST LOADS

+5V

+5V

305

305

----+

Q -.....

Q -....- - - - - -

130

130 pF
(INCLUDING
SCOPE AND JIG)

130

=~ 5 pF
(INCLUDING
SCOPE AND JIG)

Figure 1A

Figure 1B

MOTOROLA MEMORY DATA
7-25

•

MCM6294

READ CYCLE 1 (See Note 1)

K (CLOCK)

...----tKHKH----....
Ii (OUTPUT ENABLE)

A (ADDRESS)

W(WRITE ENABLE)

Q IQATA OUT)

0,,-3

~]--0"---2--1----READ CYCLE 2 (See Note 1)

K (CLOCK)

•

...----iKHKH----....
Ii (OUTPUT ENABLE)

A (ADDRESS)

W\WRITE ENABLE)

Q IQATA OUT)

0,,-3

0,,-2

tK~l-----O"---I----

NOTE:
1. The outputs On-3 and On-2 are derived from two previous read cycles, where W=VIH for those cycles.

MOTOROLA MEMORY DATA
7-26

MCM6294

WRITE CYCLE IVii Controlled, See Note 1)

Symbol

Paramater

Write Cycle Time

tKHKH

Clock High to Output High Z IW = VIL.
11 High to a High Z
Setup Times for:

tKHOZ
tGHOZ
A

W
0
Hold Times for:

A

W
0

MCMII284-2O

MCMII284-ZII

Min

Max

Min

-

25

20

-

10
10

tAVKH
twLKH
tDVKH

5

-

tKHAX
lKHWX
tKHDX

3

-

-

Max

Unit

Not..

-

ns

10

ns

2
3

10

ns

4

5

-

ns

6

3

-

ns

5

NOTES:
1. A write i. perfonned when W is low for the speclfled setup and hold times.

2.

All write cycle timing Is referenced from K or from 11.

3. Traneitfon Is measured ±600 mV from ateady-state voltage with load of Figura lB. At any given voltage and temperature, tKHOZ max Is
lea then tKHOX min for a given device.
4. 11 becomes • don't cere eignal for aucceaaive writes after the tim write cycle.
5. This Is a synchronou8 devlca. AU synchronous Inputs must meet the specified setup and hold times with stable logic levels for ALL rising
edgas of clock 110 while the device Is aeiected.
WRITE CYCLE 1

ISEPARATE I/O MODE)

ICOMMOI I/O MODEl
'----IKHKH----I~

K (CLOCK.

..

ii (OUTPUT ENABlE.

A (ADDRESS.

W(WRITE ENABLEI

D (DATA IN.

~rtsHnz

Q (DATA

.::::::r.

our.

------HI6H.Z - - - - - -

MOTOROLA MEMORY DATA
7-Xl

MCM6294

1.40

S

:Ii!
lE

1.20

I

0::

Ii
!iii

..

t--

1.00

VCC=5 V
TA=25°C

~

0::

:::>

~
"iii

0.80
0.60

~

...t;

0.40

V

~

g

0.20

1/

/

V

/

i

........-

1.05

i

.,

1.00

~_

0.95

/""

10

20
30
40
f. FREOUENCY !MHzI

50

60

20

0.90
-75

70

-50

-25

25
50
75
TA. AMBIENT TEMPERATURE (OCI

~

10

jfj

..•

80

\

o

1.0

1=
:::>

40

~

20

L

150

1.5
2.0
2.5
3.0
3.5
Vaut. OUTPUT VOLTAGE (VOLTSI

4.0

~

o
o

4.5

Figure 4. Output Source Current versus Output Voltage

V

/

V

V

<>

\

0.5

/

60

....:::>9

1\

<>
:i:
.E'

o

125

100

1....
0::

15

100

120

:::>

:z:
:z:

V

V

Figure 3. Active Supply Current versus Temperature

\
\

25

Ie

V

V

c5

G

•

VCC=5 V
1.10

!
g

30

ii

1.15

....

Figure 2. Active Supply Current versus Frequency

1

1.20

I

~

0.2

0.4

0.6
O.B
1.0
1.2
VlHlt. OUTPUT VOLTAGE (VOLTSI

1.4

1.6

1.8

Figure 6. Output Sink Current versus Output Voltage

1.3

VCC=5V

I

1. 1

<>

1.0

j

O.9

~
~

O.8
-75 -50

V
V
./"'"
-25

/""

1

V

/'

Igj

g
;

V

1.0

V
/'

.. 0.9

e;
p

25
50
75
100
TA. AMBIENT TEMPERATURE (OCI

125

Figure 6. Reed Cycle Time versus Tempereture

lL

V

0.8

O. 7
-75

150

V

VCC=5V

"2
1. 1

-50

-25

25
50
75
100
TAo AMBIENT TEMPERATURE (OCI

125

Figure 7. Clock Access Time versus Temperature

MOTOROLA MEMORY DATA
7-28

150

MCM6294

1.20

!II

1.15

5

1.10

VCC=5V

co

~
II

iii
~

6

J

1.05

/

1.00

V
/"

0.86
0.80
-75

. . . .V

V

-50

-25

TA. AMBIENT TEMPERATURE lOCI
Rgura 8. Output Enable nme versus Temperatura

ORDERING INFORMATION
(Order by Full Pert Number)

MCM

Motorola Memory Prefix

T

TIT T
1284

X

XX

XX

Part Numbar'-------------'-

_ ' _ ( R 2 . T _ ..... B..k-..

~1

Speed (20=20 ns, 25=25 ns)
Package (P = Plastic DIP, NJ=300 mil SOJ)

Full Part Numbars-MCM6294P20
MCM6294P25

MCM6294NJ2O
MCM6294NJ25

MOTOROLA MEMORY DATA

7-29

MCM6294NJ2OR2
MCM6294NJ25R2

•

MCM6294

APPUCATIONS INFORMATION

rising edge of the clock (K) signal, the output data for the
previous cycle is latched until the next rising clock edge.
Figure 9 shows a typical system configuration using four
MCM6294 chips. The system addrassas are tied to the
MCM6294e in parallel, while system data is distributed among
the four input dete ports of 4 bits each. Output dete is tied to
a separate output data bus to exploit the separate 1/0 configuration of the MCM6294. The clock (K) signal is a logical
derivation of the system clock.
Figure 10 shows typical bus timing for the configuration of
Figure 9. The system bus supplies address, data, and control
signals, while accepting data from the memory on rising clock
edges. In some applications, the clock (K) signal may need to
be a delayed system clock to allow adequate address and date
setup times.

The Motorola family of synchronous SRAMs is designed to
provide a performance and parts count advantage in applicetions such as writeable control stores, memory mapping,
and cache memory. The on-board input registers eliminate the
need for extemallatch chips in systems where addrassas and
data are not on the bus long enough to satisfy standerd SRAM
setup and hold times. Registers on the output port provide
extended hold times indepandent of address or other device
input changes to better meet system access requirements. The
clock (K) input controls the operation of the input registers
and output registers, and provides a direct means of synchronizing the SRAM to a system clock.
The MCIIII6294 offers registered output operation. On the

SYSTEM
ADDRESSES

/14
)'''14

VI4

, Vl4

~4

AD-A13

AD-AI3

AD-A13

AD-A\3

SYSTEM
CLOCK

~

L..,K

K

*- 6

•

*- 6

*-w
r'

.~
SYSTEM
DATA
IN
OUTPUT
DATA
BUS

r-

00-03

rt"

V
00-03

4

MCM6294

MCM6294

*_w

*_w

*-w

00-03

*- 6

*-6
MCM6294

MCM6294

~K

4K

r

00-03

00-03

V
00-03

' 4

00-03

'

4

00-03

16
..,16

4

~~

, 4

*From read/write controller.

Figure 9. Typical Configuration for a ttl-Bit Bua

MOTOROLA MEMORY DATA
7-30

V4

s::(')
s::

SYSTEM-GEIWTED
SlSIAlS
SYSTEM

0

CLoCK~

20

I

40

I

80

I

80

1DO

I

120

160

200

240

I I ----'L

I

I

i--

ADDRESS

CONTROL

WRITE DATA

s:::

@
::u

o

~

>
s:::

MCM62S4 CONTROL
AID OUTPUT SIGIALS
K (CLOCKI

m

s:::

- - - -.....-WRITECYCLE--t-READCYCLE

o

~
o

»~

R

R

R---+---

W

WIWRITE ENABLE)
G1000PUT ENABLEI

00-03 IDATA OUT)

(

120

160

NOTES:
1. The system supplies address, data, and control information and accepts data from memory on the rising edge of the system clock.
2. The memory clock is dalayed 10 ns (for this example) to aHow input infonnation to propagate to the memory chips.

Figure 10. Pipeline System 11mlng

I

200

I

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM6295

16K x 4 Bit Synchronous Static RAM
with Transparent Outputs and Output Enable
The MCM6295 is a 65,536 bit synchronous static random access memory organized as
16,384 words of 4 bits, fabricated using Motorola's second-generation high-performance
silicon-gate CMOS (HCMOS 1111 technology. The device integrates input registars, high
speed SRAM, and high-drive capability output latching onto a single monolithic circuit for
reduced parts count implementation of cache data RAM and writeable control store applications. The MCM6295 is well suited for applications involving the MC68030, MC68040,
and AMD29K microprocessors. It is ideal for burst mode or pipelined bus applications.
Synchronous design allows preciss cycle control with theuss of an extemal clock (K),
while CMOS circuitry reduces the overall power consumption of the integrated functions
for greater reliability.
The address (Ao-A13), data (00-03), and write (W) inputs are all clock (K) controlled,
positive-edge-triggered, noninverting registers.
The MCM6295 provides transparent output operation when K is low for access of RAM
data within the same cycle (output data is latched when K is high).
The output enable fG) provides asynchronous bus control for common I/O or bank
switch applications.
Write operations are internally self-timed and initiated by the rising edge of the K input.
This feature eliminates complex off-chip write pulss generation and provides increassd
flexibility for incoming signals.
The MCM6296 is available in a 300-mil, 2S-pin plastic DIP as well as a 300-mil, 28-pin
plastic SOJ package.
•

•

..

•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Fast Access and Cycle Times: 25/30 ns Max
Address, Data Input, and W Registers On-Chip
Transparent Output Latch for Access Within the Same Cycle
Output Enable for Asynchronous Bus Control
High Output Drive Capability
Intemally Self-Timed Write Pulss Generation
Separate Data Input and Date Output Pins
High Board Density SOJ Package Available
Typical Applications: General-Purpose Buffer Storage, Writeable Control Store, Data
cache, or cache Tag

~

300 MIL PLASTIC
CASE710A

~PACKAGE
3OOMILSOJ
CASE 8108

PIN ASSIGNMENT
A5

1.

28

Vee

A6

2

27

A4

A7

3

26

A3

A8

4

25

A2

AI

A9

5

24

AID

6

23

AD

All

7

22

03

A12

8

21

02

A13

9

20

03

DO I 10

19

02

01 111

18

01

12

17

00

KI 13

16

W

Vss I 14

15

VSSO*

ii I

*For

proper operation of the
device, both VSS and VSSQ
must be connected to ground.

BLOCK DIAGRAM

PIN NAMES
A()'A 13 ••.•••••• Address Inputs
00
01
02

03

MOTOROLA MEMORY DATA
7-32

Vii. • . . . . . . . . . . . Write Enable

G . . . . . . . . . . ..

Output Enable
00-03 . . . . . . . . . . . Oata Inputs
OO-Q3 . • . . • • • . • • Oata Outputs
K • • • . • • • • • • • • • • Clock Input
Vee . . . • . • . +5 V Power Supply
VSS • . • • • . . . • . . • • . Ground
VSSQ . . . . • Output Buffer Ground

MCM6295

TRUTH TABLE

c;

W

Operation

QO-Q3

X

L

Write"

HighZ

L

H

Read

H

H

Output Disabled

Daut
High Z

NOTE: The value W is a valid input far tha aetup and hold times relative to the K rising
edge. The value "G is an asynchronous input.
ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = Vssa =0 V)
Rating

Symbol

Value

VCC

-0.5 to +7.0

V

Yin, Vaut

-0.6 to VCC+0.5

V

Output Currant (per 110)

'out

±2O

mA

Power Dissipation (TA = 25'C)

PD

1.0

W

Tbias

-10to +85

·C

Power Supply Voltage
Voltage Relative to VsslVssa for Any
Pin Except VCC

Temperature Under Bias
Operating Temperature

TA

Storage Temperature

Tstg

oto

Unit

+70

This device contains circuitry to protect tha
inputs against damage due to high static
voltages or electric fields; hawever, it is advised that normal pracautiana be taken to
avoid application of any voltage higher than
maximum rated voltages to this highimpedance circuit.
This is a synchronous device. All synchronous inputs must meat the specifllld aetup
and hold times with stable logic levera far
ALL rising edges of clack (K) while the device is eeIectad.
This device contains circuitry that will ensure the output devices are In High Z at
power up. Care should be taken by the u.r
to ensure that all clacks are at V,L or V,H
during power up to prevent spurlcua reed
cycles from occurring.

·C

-66 to +125

·C

NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

± 10%, TA=O to 70°C, Unless Otherwise Noted)

(VCC=5.0 V

RECOMMENDED OPERATING CONDITIONS (Voltages referenced to Vss=Vssa=O V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

Param_

VCC

4.6

6.0

5.6

V

Input High Voltage

V,H

2.2

Input Low Voltage

V,L

-0.5*

-

VCC + 0.3

V

0.8

V

*V,L (min) = -0.5 V de; V,L (min) = -3.0 V ac (pulse width ,;20 ns)

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Vin=O to VCC)

Parametar

"kg(/)

-

±1.0

p.A

Output Leakage Currant ("S=V,H, Vout=O to VCC, Outputs must be in high-Z)

l'ka(O)

AC Supply Currant ~=VIL- lout=O mA, Cycle Time .. tKHKH min)

-

±1.0

p.A

-

140

mA

Output Low Voltage (lOL = 12.0 mAl

'CCA
VOL

-

0.4

V

Output High Voltage (lOH = - 10.0 mAl

VOH

2.4

-

V

Symbol

Typ

Max

Unit

Cin

4

6

pF

Cout

7

10

pF

CAPACITANCE (f= 1.0 MHz, dV =3.0 V, TA =25°C, Periodically Sampled Rather Than 100% Tested)
Charactaristlc
Input Capacitance
Output Capacitanca

MOTOROLA MEMORY DATA
7-33

•

MCM6295

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ±10%, TA=O to +70o C, Unless Otherwise Noted)
Input Timing Measurement Reference Level • . • . • . • . •• 1.5 V
Input Pulse l.eI(els . . . . . . • . • • . • . . . .' • • . • . . .0 to 3.0 V
Input Rise/FalfTime • . . . . . . . • . . . • . • . . . . . . . . . . 5 ns

Output Timing Measurement Reference Level • . • • • . • • . 1.5 V
Output Load • . . • . . . . . . See F"lIJure lA Unless Otherwise Noted

READ CYCLE (See Nota 1)
Symbol

Parametar

MCM829&-30

Max

Min

Unit

Max

Notas

Read Cycle Time

tKHKH

25

-

30

-

ns

2

Clock Access TII1l8

tKHOV

-

25

-

30

ns

4,6

13

ns

5,6

ns

3,6

Data Valid from Clock Low

tKLOV

-

10

-

Output Hold from Clock Low

tKLOX

0

-

0

Clock Low Pulse Width

tKLKH

5
5

-

tAVKH
twHKH

5

-

5
5
5

tKHAX
tKHWX

3

-

3

-

tGHOZ

-

10

0

-

-

tGLOX
tGLOV

-

10

Clock High Pulse Width

tKHKL

Setup Times for:

A

W
Hold Times for:

A

W
G High to 0 High Z
G Low to 0 Active
G Low to 0 Valid

•

MCM828&-2&
Min

-

0

-

ns
ns
ns

7

ns

7

13

ns

8

-

ns

8

13

ns

NOTES:
1. A read Is defined by W high for the setup and hold timas.
2. All reed cycle timing is referenced from K or from G.
3. Transition is measured ±500 mV from stsedy-state voltage with load of Figure lB. This parameter is sampled not 100% tasted.
4. For Read Cycle 1 timing, clock high pulse width < (tKHOV - tKLOV).
5. For Read Cycle 2 timing, clock high pulse width ;;" (tKHOV - tKLOV)'
6. K must be at a low level for outputs to transition.
7. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising
edges of clock (K) while the device is selected.
8. At any given voltage and tamparature, tGHOZ max is less than tGLOX min, both for a given device and from device to device.

AC TEST LOADS

+5V

+5Y

305

305

Q--~--------~

Q - -....--------~

='= 130 pF

130

5 pF
(INCLUDING
SCOPE AND JIG)

130

(INCLUDING
SCOPE AND JIGI

Figure 1A

Figure 1B

MOTOROLA MEMORY DATA
7-34

MCM6296

READ CYCLE 1 (See Note 1)

A (ADDRESS)

w

QO-Q3 - - - PREVIOUS HIGH

Z----

0,,+1

READ CYCLE 2 (See Note 2)

A (ADDRESS)

OO-Q3 - - - - - PREVIOUS HIGH Z

-------1

NOTES:
1. For Read Cycle 1 timing, clock high pulse width 

5

~

1.00

....

O.BO

II:
II:
::0

r----

VCC=5 V
TA=25°C

en

0.60

~

!i1

0.40

/

C
....

E

V

V
i/

!:;

II:
::0

0.20

/'

1.20

I

1.15

~

1.10

!

1.05

/

~

ill 1.00

§
3D

20

40

50

60

0.90
-75 -50

70

-25

f. FREOUENCY (MHz)

Figure 2. Active Supply Current versus Frequency

3D

i...
z

Ii!

...~

.

/

....

15

\

<>

:i:
!?

1.0

1.5

2.0

2.5

....
~
::0

40

3.0

3.5

4.0

~

20

/

V

o
o

4.5

0.2

0.4

1.3

..~

1.2

I

1.1

ij

r.

:5

'":i:
,.
~

/

VCC=5 V

5

1.0
0.9
O.B

-75 -50

0.8

1.0

1.2

1.4

1.6

1.8

1.3

1.4

<>

0.6

Figure 5. Output Sink Current versus Output Voltage

S

II:

/

VOU!. OUTPUT VOLTAGE (VOLTS)

Figure 4. Output Source Current versus Output Voltage

~

150

V

VOU'. OUTPUT VOLTAGE (vOLTSI

:i
:IE

125

/

<>

\

0.5

100

/

60

9

\

10

::0

o
o

60

II:
::0

....

:r:

25
75
50
TA. AMBIENT TEMPERATURE laC)

100

i...

::0

~

V

120

\

20
Il!
II:

./'"

Figure 3. Active Supply Current versus Tempereture

\

25

./'"

V
./

0.95

~
10

\

VCC=5 V

~

~

!!;

//
V
~
-25

/"

I

VCC=5 V
1.1

~

1.0

1S

0.9

..e

./

.",-

1.2

V
./

L

V

V

d

J

75
100
25
50
TA. AMBIENT TEMPERATURE laC)

125

0.8
0.7
-75

150

-50

-25

25

50

75

100

125

TA. AMBIENT TEMPERATURE laC)

Figure 8. Read Cvcle Time versuB Temperature

Figure 7. Clock Access Time versus Temperature

MOTOROLA MEMORY DATA
7-37

150

. .

MCM6296

1.20

m

1.15

I

1.10

c

i

Vee=5Y

l-

i

1.05

~

1.00

~

0.95

6

......../'

.........

.....V

V

11
0.90
-75

-50

-25

25

50

75

100

125

150

TA. AMBIENT TEMPERATURE ("e)

Figure 8. Output Enable Time versus Temperature

ORDERING INFORMATION
(Order by Full Part Numberl

MCM

Motorola Memory Prefix

•

T

J 1TT
6296

X

XX

XX

Part Numbar - - - - - - - - - - - '

8" _ _ _

'02-,." ..........-...,

Speed (25=25 08. 30=30 n8)
Package (P=300 mil Plastic DIP, NJ =300 mil SOJ)

Full Part Numbers-MCM6295P25
MCM6295P30

MCM6295NJ25
MCM6295NJ30

MOTOROLA MEMORY DATA
7-38

MCM6295NJ25R2
MCM6295NJ30R2

MCM6296

APPLICATIONS INFORMATION

be set up on the system bus prior to the next rising clock edge.
On the rising edge of the clock (K) signal, the output data for
the previous cycle is latched until the next falling clock edge.
When the clock (K) signal is low, the output is allowed to
transition relative to the most recent rising clock (K) edge.
Figure 9 shows a typical system configuration using four
MCM6295 chips. The system addresses are tied to the
MCM6295s in parallel, while system data is distributed among
the four input data ports of 4 bits each. Output data is tied to
a separate output data bus to exploit the separate 110 configuration of the MCM6296. The clock (K) signal is a logical
derivation of the system clock.
Figure 10 shows typical bus timing for the configuration of
Figure 9. The system bus supplies address, data, and control
signals, while accepting data from the memory on rising clock
edges. In some applications, the clock (K) signal may need to
be a delayed system clock to allow adequate address and data
setup times.

The Motorola family of synchronous SRAMs is designed to
provide a performance and parts count advantage in applications such as writeable control stores, memory mapping,
and cache memory. The on-board input registers eliminate the
need for external latch chips in systems where addresses and
data are not on the bus long enough to satisfy standard SRAM
setup and hold times. Latches on the output port provide
extended hold times independent of address or other device
input changes to better meet system access requirements. The
clock (K) input controls the operation of the input registers
and output latches, and provides a direct means of synchronizing the SRAM to a system clock.
The MCM6295 offers transparent output operation, which
allows output data access within the same tKHKH cycle. This
feature lends itself well to applications requiring RAM data to

SYSTEM
ADDRESSES

, /14
)"14

11"14

,."'14

~4

AO-A13

AO-A13

AO-A13

AO-A13

SYSTEM
CLOCK

~K

*-i;

*-«
*-Iii

r-

I'

~

4

IN
OUTPUT
DATA
BUS

00-03

, ,,16
.... 16

4

*-«
MCM6295

-_Iii

*-Iii

....... OO-D3

....... K

*-«
MCM6295

MCM6295

SYSTEM
DATA

~K

_K

*_Iii

....... DO-D3

00-03
00-03

/4

,,~

....... 00-03

00-03

,,~

*From read/write controller.
Agure 9. Typical Configuration for a 16-Bit Bus

MOTOROLA MEMORY DATA
7-39

MCM6295

,. 4

OD-Q3

V4

•

I
SYsnM-GEIERATEO
SIGIALS
SYSTEM

0

CLOCK~

20

I

40

I

60

I

80

3:
n
3:
100

120

I I I

160

I

200

I

240

---'L

~I

ADDRESS

CONTROL

WRITE DATA

3:

§
JJ

0

~

~

MCM8295 COITROL
AID OUTPUT SlG.ALS
K (CLOCK)

3:
m
3:
0

WRITE CYCLE

-1--

READ CYCLE

~--+----W

R

R~I--~----

JJ

-<

0

,..

~

IV (WRITE ENABLE)

G(OUTPUT ENABLE)
00-03 (DATA OUT)

V'I
BO

Dn+5

lV,
120

160

NOTES:

1. The system supplies address, data, and control information and accepts data from memory on the rising edge of the system clock.
2. The memory clock is delayed 10 ns (for this example) to allow input information to propagata to the memory chips.

Figura 10. Nonpipalina System Timing

240

m

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - -

TECHNICAL DATA

MCM56824

Product Preview
DSPRAMTM
8Kx24 Bit Fast Static RAM
The MCM56824 is a 196,608 bit static random access memory organized as
8,192 words of 24 bits, fabricated using Motorola's high-performance silicon-gate
CMOS technology. The device integrates an 8Kx24 SRAM core with muHiple chip
enable inputs, output enable, and an extemally controlled single address pin multiplexer. These functions allow for direct connection to the Motorola DSP56001 Digital
Signal Processor and provide a very efficient means for implementation of a reduced parts count system requiring no additional interface logic.
The availability of multiple chip enable (ET and E2) and output enable (G)
inputs provides for greater system flexibility when multiple devices are used.
With either chip enable input unasserted, the device will enter standby mode,
useful in low-power applications. A single on-chip multiplexer selects A12 or
XIV as the highest order address input depending upon the state of the viS
control input. This feature allows one physical static RAM component to
efficiently store program and vector or scalar operands by dynamically repartitioning the RAM array. Typicel applications will logically map vector operands into upper memory with scalar operands being stored in lower memory.
By connecting DSP56001 address A15 to the VECTOR/SCALAR (V~ ~~.
control pin, such partitioning can occur with no additional compo~ Thill.
allows efficient utilization of the RAM resource irrespeC!il(8 of ~""dtype..
See application diagrams at the end of this docl!nu,/'ltJor additlofl81
•..
information.
". '..
.: '(
.. ..' ' ,
IJ04
Multiple power and ground pins haw'l;Ieen:utllilacffo minil\'ltia'~
DQ5
induced by output noise.
".... " ":
'.
. ,;;'
; . ,:' ..... .
'006
The MCM56824 is available fn; a52/)ln p~le~ 9hip-c'ar!ie~ (P~CC).
007
DQ8
• Single 5 V ±1 00/0 Power Supply
. '.' ... ",
',., '..,
Vss
• Fast Access and Cycle limes: 25/35 ns MaX
DOS
• Fully Static Read and Write Operations
0010
• Equal Address and Chip Enable Access limes
• Single Bit On-Chip Address Multiplexer
• Active High and Active Low Chip Enable Inputs
• Output Enable Controlled Three State Outputs
• High Board Density PLCC Package
• Low Power Standby Mode
• Fully TTL Compatible

FNPACKAGE
52-LEAD PLCC

CASE 778

PIN ASSIGNMENT

,~~.~I~I~~:l3~ c~ ~n ~
8
9

7 '6 5 4 3 2 1 52 51 50 49 48 47
46
45

•

44
43

'10
11
12
13
14
15
16

42
41

0023
0022
0021

Vss

0020
0019
40 0018
39 0017
38 0016
37 0015
17
36 Vss
18
35 0014
19
0013
20 21 22 23 24 25 26 27 28 29 30 31 32

J4

;::

g

~

:i!!<

~ Ie:>

8ll!1i:U ~I~

> >

~ ~

g

PIN NAMES

AO-A 11 ............. Addrsss Inputs
A 12, XiV

...•.•.. Multiplexed Addrsss
viS ...... Addrsss Multiplexer Control
W ................... Writs Enable

"ET, E2 .. . . . . . . . . . . . . .. Chip Enable
G . . . . . . . . . . . . . . . . .. Output Enable
~23

........ Oats InputlOutput

VCC •.......... +5 V Power Supply
VSS .......•...........••. Ground

NC .. . .. .. .. . .. .. ... No Connection
For properoperation of the device, all Vss
pins must be connected to ground.

DSPRAM is a lrademark of Motorola, Inc.
This document contains infarmadon on a ptOduct under development MoIllrOla reserves the rightID change or discontinue this ptOduct without notice.

MOTOROLA MEMORY DATA
7-41

•

MCM56824

BLOCK DIAGRAM

viS

xN
A12

Vee

NJ

Vss

••
•

••
•

ROW
DECODER

AS
A1D

MEMORY ARRAY
512 ROWS X
384 COLUMNS

All

•••
DOD

•••

t1PUT
DATA
CONTROL

D023

E1

COLUMN 110

••
•

COLUMN DECODER

E2

•••

W

G

(LSB)

..

(MSB)

TRUTH TABLE
El

E2

~

W

VIS

Mode

Supply Current

H

X

X

X

X

Not Selected

ISB

High-Z

X

L

X

X

X

Not Selected

ISB

High-Z

L

H

H

H

X

Output Disable

ICC

High-Z

L

H

L

H

H

Read Using xiV

ICC

Data Out

L

H

L

H

L

Read Using A12

ICC

Data Out

L

H

X

L

H

Write Using xiV

ICC

Data In

L

H

X

L

L

Write Using A12

ICC

Data In

110 Status

NOTE: X = don't care.

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)
Rating
Power Supply Voltage
Voltage Relative to Vss

Symbol

Value

Unit

VCC

-C.5to +7.0

V

Vin, VOU! -C.5 to VCC + 0.5

V

Output Current (per 110)

lout

±20

mA

Power Dissipation (TA =70DC, VCC =5 V,
IAVAV =50 nsl
Temperature Under Bias

Po

1.75

W

Tbias

-10 to +85

DC

Operating Temperature

TA

o to +70

DC

Storage Temperature

Tstg

-65 to +125

DC

NOTE: Permanent deVIce damage may occur If ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

MOTOROLA MEMORY DATA
7-42

This device contains circuitry to protect against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit
This CMOS memory circuit has been
designed to meet the de and ac specifications shown in the tables, after thermal equilibrium has been established.
The circuit is assumed to be in a test
socket or mounted on a printed circuit
board with at teast 300 LFPM of transverse air flow being maintained.

MCM56824

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to +700 e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to Vss = 0 V)
Parameter
Supply Voltage (Operating Voltage Range)

Symbol
VCC

Min
4.5

Typ

5.0

Max
5.5

Unit
V

Input High Voltage

VIH

2.2

3.0

VCC..o·3

V

Input Low Voltage

VIL

~.5·

0.0

0.8

V

Symbol

Min

·VIL(mln) = ~.O V ac (pulse width S20 ns)

DC CHARACTERISTICS
Parameter

Max

Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC)

IIkg(i)

-

±1.0

II-'

Output Leakage Current (G - VIH, El - VIH, E2 - VIL Vout- 0 to VCC)

Ilkg(O)

-

±1.0

AC Supply Current (~ = VIH, ET = VIL, E2 = VIH, lout = 0 mA,
MCM56824-25 Cycle Tune: ~25 ns
All Other Inputs ~ VIL = 0.0 V and VIH ~ 3.0 V)
MCM56824-35 Cycle Tune: ~35 ns

ICCA

Standby Current (ET = VIH, E2 = VIL, AlllnpUls = VIL or VIH)

ISBl

250
180

ISB2

-

OulputLow Voltage (IOL = +8.0 mAl
Oulput High Voltage (IOH = -4.0 mAl

CMOS Standby Current (El

~ VC~.2

V, E2 S 0.2 V, All Inputs ~ VCC~.2 V or S 0.2 V)

II-'
mA

15

mA

10

mA

VOL

-

0.4

V

VOH

2.4

-

V

Symbol

Typical

Max

Unit

Cin

4

6

pF

CI/o

6

8

pF

CAPAaTANCE (I = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

All Pins Except DCIO-0023

InputlOulpUt Capacitance

000-0023

AC TEST LOADS

480ll
00 ...- - - -....
5 pf (INCLUDING
SCOPE AND JIG)

255ll

FIGURE1A

FIGURE1B

MOTOROLA MEMORY DATA
7-43

•

MCM56824

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ±1 0%. TA = 0 to +70"C, Unless Otherwise Noted)
Output liming Reference Level ....... '. . . . . . . . . . . . . . .. 1.5 V
Output Load ........... See Figure lA Unless Otherwise Noted

Input liming Measurement Reference Level .............. 1.5 V
Input Pulse Levels ............................ " 0 10 3.0 V
Input Rise/Fall lime .................................. 3 ns

READ CYCLE TIMING (See Notes I, 2, 3)
Symbol
Parameter

•

MCM56824-25

Standard

Alternale

Read Cycle lime

IAVAV

Address Access lime

IAvav

MUX Control Valid to Output Valid

tvsvav

IAA

Chip Enable to Output Valid

telLaV
tE2HaV

tACl
tAC2

MCS6824-3S
Unit

Min

Max

Min

Max

tRC

25

-

35

-

ns

tM

-

25

3S

ns

25

-

3S

ns

25

-

35

ns

Output Enable to Output Valid

IGLav

toE

-

Output Active from Chip Enable

tel LaX
tE2Hax

teLZ

2

Nota.

4

10

-

15

ns

0

ns

4,5

0

-

ns

5

5

-

ns

Output Active from Output Enable

IGLax

toLz

0

-

Output Hold from Address Change

tAXax

toH

5

-

Output Hold from MUX Control Change

tvsxax

tvsOH

5

-

5

-

ns

Chip Enable 10 Output High Z

tE1HaZ
tE2LaZ

teHZ

0

15

0

15

ns

4,5

Output Enable High to Output High Z
0
15
0
15
ns
5
IGHOZ
toHZ
NOTES:
1. A read cycle is defined by iii high.
2. All read cycle timings are referenced from the last valid address or vector/scalar transition to the first address or vector/scalar transition.
3. Addresses valid prior to or coincident with ~ going low or E2 going high.
4. ET in the timing diagrams represents both ET and E2 with ET asserted low and E2 asserted high .
5. Transition is measured ±SOO mV from steady-state voltage with load of Figure 1B. This parameter is samplad and not 100% tested. At any
given voltage and temperature, tE 1HaZ max is less than tEl Lax min, tE2LaZ max is less than tE2HaX min, and tGHaZ max is less than
IGLax min for a given device and from device 10 device.

READ CYCLE

A(ADDRESS)

viS (MUX CONTROL)

~

tAVAV

-I

IAvav

=t'--------------:-----------'t
.1

hfSvav

tvsxax

E1 (CHIP ENABLE)
'E1HaZ

'EILav
~ (OUTPUT ENABlE)

Q(DATAOUT)

HIGH-Z

DATA VALID

MOTOROLA MEMORY DATA
7-44

HIGH-Z

MCM56824

WRITE CYCLE TIMING, WRITE ENABLE INITIATED (See Note 1)
Symbol
Parameter

MCM56824·25

MC56824-35

Max

Min

Unit

Max

Notes

Standard

Alternate

Min

Write Cycle Time

tAVAV

twc

25

-

35

IAVWL

tAS

0

-

0

-

ns

Address Setup Time

tvSVWL

tvss

0

0

-

ns

30

-

ns

30

-

ns
ns

3

ns

3,4
3,4

ns

IAVWH

tAW

20

MUX Control Valid to End of Write

tVSVWH

tvsw

20

-

Write Pulse Width

twLWH

twP

15

-

20

Write Enable to Chip Enable Disable

twLE1H
1WLE2L

tow

,15

-

20

-

Chip Enable to End of Write

tE1LWH
tE2HWH

tow

15

-

20

-

ns
ns

0

-

MUX Control Setup Time
Address Vaiid to End of Write

2

Date Valid to End of Write

toVWH

tow

10

-

15

Date Hold Time

twHDX

tDH

0

0

Write Recovery Time

twHAX

twR

0

MUX Control Recowry Time

twHVSX

tvSR

0

Write High to Output Low Z

twHOX

twLZ

5

-

5

-

ns

6

Write Low to Output High Z

twLOZ

twHZ

0

15

0

15

ns

6

0

ns

5

ns

2

ns

NOTES:
1. A write cycle star1S at the latest transition of 1:1 low, Wlow, or E2 high. A write cycle ends at the earliest transition of 1:1 high, Whigh, or E2
low.
2, Write must be high for all address and viS transitions.
3. If Wgoes low coincident with or prior to 1:1 low or E2 high the outputs will remain in a high-impedance state.
4. 'E'f in the timing diagrams represents both 'E'f and E2 wnh 'E'f asserted low and E2 asserted high.
5. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.
6. Transition is measured ±SOO mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tEl HOZ max is less than lEI LOX min, 1E2LOZ max is less than tE2HOX min, and taHOZ max is less than
taLOX min for a giwn device and from device to device.

WE INITATED WRITE CYCLE

~

~---------------------~v~------------------~----~

A(AODRESS)

" " - - - - _ _

_

~---------------~VWH--------------~·~I··----- ~HAX

viS (MUX CONTROL)

~

twHVSX~

-,.../
tvSVWH
tE1LWH

\

'Ei (CHIP ENABLE)

-tvsVWL
W(WRITE ENABLE)

i--

tAVWL

tWLWH

I

't-

toVWH -- --

twHox

hxxxxx»
~

o(DATA IN)
Q(DATAOUT)

r

VALlO DATA IN

~

HIGH-Z

i "'""

(~XX)

MOTOROLA MEMORY DATA
7-46

1------1

H~:LE1H

\

....

I

4XXX~

•

MCM56824

WRITE CYCLE nMlNG, CHIP ENABLE INITIATED (See Note 1)
Symbol

Param_
Write Cycle Tune

MCM56824-25
Max

Min

Max

-

35

-

ns

0

-

ns

2

0

-

ns

2

30

-

ns

2

ns

2

ns

2,3

ns

2

ns

2,4

ns

2

ns

2

twc

25

'As

0

tVSVE1L
"'SVE2H

"'SS

0

'AVE1H
'AVE2L

lAw

20

MUX Control Valid to End of Write

"'SVE1H
tVSVE2L

tvsw

20

Chip Enable to End of Write

tE1LE1H
tE2HE2L

tcw

15

Data Valid to End of Write

tOVE1H
'OVE2L

tow

10

Data Hold lime

tE1HOX
tE2LOX

tOH

0

Write Recovery lime

1E1HAX
tE2LAX

twR

0

tE1HVSX
tE2LVSX

"'SR

0

Address Valid to End of Write

MUX Control Recovery lime

Note.

IIln

'AVAV

MUX Control Setup lime

Unit

A1terna..

'AVE1L
'AVE2H

Address Setup lime

MC56824-35

Standard

30
20
15
0
0
0

NOTES:
1. A write cycle starts at the latest transition of ET low, Wlow, or E2 high. A write cycle ends at the earliest transition of Ef high, Whigh, or E2
low.
2. 'ET in the timing diagrams represents both 'ET and E2 with Ef asserted low and E2 asserted high.
3. If Wgoes low coincident with or prior to ET low or E2 high the outputs will remain in a high-impedance state.
4. During this time the output pins may be in the output stale. Signals of opposite phase must not be applied to the outputs at this time .

•

E1 OR E2INITIATED WRITE CYCLE
~""I-----------IAVAV
A(ADDRESS)

-------'~

--------=4---tOf

;1.:-=--=--=--te-1-HAX-;j~----

....::::::::::::::::::.:::.:::.-=--=--=--t-AVE-1H---------.:-------------...

V~ (MUX CoNTROL)

1 - - - - - tvsVE1H -----1- te1HVSX

E1 (CHIP ENABlE)

- - - - - t - t - - - , j . - - - 1E1LE1H ---11----,...-----tvsVE1L

Vi (WRITE ENABLE)

D(DATA IN)

Q(D~Aoun

DATA VALID

__________________

~H~IG~H~~~

_ _ _ _ _ _ _ _ _ _ _ _ ___

MOTOROLA MEMORY DATA
7-46

MCM&6824

MCM56824 DSPRAM Multiplexed Vector/Scalar Address Maps
MCU56824

DSP56001

AO-A11 1 - - - - - - - 1 AO-A11
A12
RAMA12
Xf(

viS 1-----1

4KX24
"X" OPERANDS

--------

8KX24
")("OPERANDS

PROGRAM

MEMORY
HIGH
4KX24
"'("OPERANDS

i- _ _ _ _ _ _ _

-------PROGRAM

PROGRAM

MEMORY

MEMORY

LOW

MCM56824 8Kx24 DSPRAM Used In TYpical Application

DSP56001
DO-l)23

AG-A11
A12
A15
Xl{

..

...
"

.

b

MCM56824
00-023

AO-A11
A12 {MEMORY
viS MANAGEMENT
xfj PINS

WE

\Wi

MOTOROLA MEMORY DATA

7-47

•

MCM56824

ORDERING INFORMATION

T r ¥,

(Order by Full Part Number)

T...

Motorola Memory Prefix _ _ _
Part Number

_

Speed (25 =25 ns, 35 =35 ns)

L.
_______

Full Part Numbers: MCM56824FN25

II

MOTOROLA MEMORY DATA
7~

Package (FN = PLCC)

MCM56824FN35

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM56824A
Product Preview
DSPRAMTM
8Kx24 Bit Fast Static RAM
The MCM56824A is a 196,608 bit static random access memory organized as
8,192 words of 24 bits, fabricated using Motorola's high-performance silicon-gate
CMOS technology. The device integrates an 8Kx24 SRAM core with multiple chip
enable inputs, output enable, and an externally controlled single address pin multiplexer. These functions allow for direct connection to the Motorola DSP56001 Digital
Signal Processor and provide a very efficient means for implementation of a reduced parts count system requiring no additional interface logic.
The availability of multiple chip enable (E1" and E2) and output enable (G)
inputs provides for greater system flexibility when multiple devices are used.
With either chip enable input unasserted, the device will enter standby mode,
useful in low-power applications. A single on-chip multiplexer selects A12 or
XIV as the highest order address input depending upon the state of the
control Input. This feature allows one physical static RAM component to
oao
efficiently store program and vector or scalar operands by dynamically reDOl
partitioning the RAM array. Typical applications will logically map vector operD02
ands into upper memory with scalar operands being stored in lower memory.
Vss
By connecting DSP56001 address A15 to the VECTOR/SCALAR (ViS) MUX
D03
control pin, such partitioning can occur with no additional components. This
DQ4
allows efficient utilization of the RAM resource irrespective of operand type.
DOS
See application diagrams at the end of this document for additional
D06
information.
D07
Multiple power and ground pins have been utilized to minimize effects
DOS
induced by output noise.
Vss
The MCM56824A is available in a 52 pin plastic leaded chip-carrier (PLCC).
0Q9
0010
• Single 5 V ±1 0% Power Supply

Vis

•
•
•
•
•
•
•
•
•

Fast Access and Cycle limes: 20125135 ns Max
Fully Static Read and Write Operations
Equal Address and Chip Enable Access limes
Single Bit On-Chip Address Multiplexer
Active High and Active Low Chip Enable Inputs
Output Enable Controlled Three State Outputs
High Board Density PLCC Package
Low Power Standby Mode
Fully TTL Compatible

FNPACKAGE
52-LEAD PLCC
CASE 778

PIN ASSIGNMENT

~ ~ ~ I~ '~ ~ ~ll :c ~ :.! ~ ~
7 6 5 4 3 2 1 52 51 50 49 48 47
•
46
45

D023
D022
D021

Vss
D020
D019
D018
D017
D016
D015

Vss
D014
D013

PIN NAMES

AO--Al1 ............. Address Inputs
A 12, XIY ........ Multiplexed Address
viS ...... Address Multiplexer Conlrol

W ................... Write Enable
1:1, E2 . . . . . . . . . . . . . . . . Chip Enable
13 ................ " Output Enable
~Q23 ..•..... Data InpullOutput
VCC ........... +5 V Power Supply
VSS ...................... Ground
NC . . . . . . . . . . . . . . . .. No Connection

Forproperoperationoflhedevice, a1IVSS
pins must be connected 10 ground.

DSPRAM is a trademark of Motorola, Inc.
This document contains information on a product under development. Motorola reserves the right to chenge or discontinue this product without notice.

MOTOROLA MEMORY DATA
7-49

•

MCM66824A

BLOCK DIAGRAM

vS
'IN
A12

vee

III

Vss

••
•

••

ROW
DECODER

M

•

Al0

MEMORY ARRAY
512 ROWS X
384 COLUMNS

All

•••
DOD

••

tlPUT
DATA

•

CONTROl.

D023

n

••

COLUMN 110

•

COLUMN DECODER

E2

•••

W
~

AS
(LSB)
(MSB)

•

TRUTH TABLE

E2
X

(f

W

vi§

Mode

Supply Current

IIOStatu8

H

X

X

X

NotSelecled

ISB

High-Z

X

l

X

X

X

Not Selectad

ISB

High-Z

l

H

H

H

X

Output Disable

ICC

High-Z

l

H

l

H

H

Read Using XiV

ICC

Data Out

l

H

l

H

l

Read Using A12

ICC

Data Out

l

H

X

l

H

Wri1e Using XiV

ICC

Data In

l

H

X

l

l

WriteUsingA12

ICC

Data In

Ei

NOTE: X=Cbn't care.

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS=O V)
Rating

Symbol

Value

Unit
V

VCC

-(l.5 to +7.0

Voltage Relative to Vss

Vin, Vout

-(l.5 to VCC+0.5

V

Output Current (per I/O)

lout

±20

mA

Power Dissipation (TA=7O"C, VCC=5 V,
'AVAv=50 ns)
Temperature Under Bias

Po

1.75

W

Tblas

-10 to +85

·C

TA

Oto +70

·C

Power Supply Voltage

Operating Temperature

Storage Temperature
-55 to +125
Tstg
·C
NOTE: PermanentdeY1C8demage mayoccunf ABSOLUTE MAXIMUM RATINGS are exeeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time coutd alfect device reliability.

MOTOROLA MEMORY DATA
7-60

This device contains circuitry to protect against demage due to high static
voltagos or electric fields; however, it is
advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to
this high-impedance circuit
This CMOS memory circuit has been
designed to meet the de and ac specifications shown in the tables, after thermal equilibrium has been estabtished.
The circuit Is assumed to be in a test
socket or mounted on a printed circuit
board with at least 300 LFPM of transverse air flow being maintained.

MCM56824A

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee - 5.0 V±10%, TA = Oto +70oe, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to Vss=O V)
Parameter
Supply Voltage (Operating Voltage Range)

Symbol
VCC

Min
4.5

Typ
5.0

Max
5.5

Unit
V

Input High Voltage

VIH

2.2

3.0

VCC-Hl·3

V

Input Low Voltage

VIL

~.5·

0.0

0.8

V

'VIL(m,n) - -3.0 V ac (pulse WIdth S20 ns)

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Current (All Inputs. Yin = 0 to VCC)

Ilkg(i)

-

±1.0

IIA

Output Leakage Current (C! =VIH, ET =VIH. E2 = VIL. Vout =0 to VCC)

Ilkg(O)

-

±1.0

AC Supply Current (G = VIH. El = VIL. E2 =VIH, lout =0 mA,
MCM56824A·20 Cycle Time: ~20 ns
All Other Inputs ~ VIL = 0.0 V and VIH ~ 3.0 V)
MCM56824A·25 Cycle Time: ~25 ns
MCM56824A-35 Cycle Time: ~35 ns

ICCA

Parameter

Standby Current (El

=VIH, E2 =VIL. All Inputs = VIL or VIH)

VOL

-

VOH

2.4

ISBl

Output Low Voltage (IoL =+8.0 mAl

=-4.0 mAl

280
250
180

-

15B2

Output High Voltage (IOH

-

CMOS Standby Current (ET ~ VCC~.2 V, E2 s 0.2 V. All Inputs ~ VC~.2 V or S 0.2 V)

IIA
mA

15

rnA

10

rnA

0.4

V

-

V

CAPACITANCE (I = 1 0 MHz dV = 3 0 V TA = 25°C Periodically Sampled Rather Than 100% Tested)
Parameter
Input Capacitance

Symbol

Typical

Max

Unit

All Pins Except DQO...OQ23

Cin

4

6

pF

DOO-DQ23

ClIO

6

8

pF

InputlOutput Capacitance

AC TEST LOADS
+5V
480n

00-.----.-..

OUlPUT---q..~----"lRt.= 50 n

~ Zo= 50n

l

5 Df (INCLUDING
SCOPE AND JIG)

255n

FIGURE1A

FIGURE 18

MOTOROLA MEMORY DATA
7·51

•

MCM56824A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V±lO%, TA - Oto +70·C, Unless Otherwise Noted)
Input liming Measurement Reference Lewl . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels • . . . . . • . . . . . . . . . • • . . . . • . • • . . .. 0 to 3.0 V
Input Rise/FaD lime .................................. 3 ns

Output liming Reference Level ....................... 1.5 V
Output Load ...•......• See Figure lA Unless OthlltWise Noted

READ CYCLE llMING (See Notes 1, 2, 3)
Symbol
Parameter

•

MCM56824A-20

Standard Alternate

Read Cycle Time

'AVAV

IRC

Address Access Time

IAVOV

Min
20

Output Enable to Output Valid

IGLOV

toE

-

OutpUI Actiw from Chip Enable

tE1LQX
tE2HQX

tell

2

MUX Control Valid 10 Output Valid

tvSVOV

IAA
IAA

Chip Enable to Output Valid

tE1LOV
IE2HOV

'ACI
IAC2

Max

MCM56824A-25
Min

Min

Max

35

-

-

25

-

20

-

25

-

25

20
20

8

-

25
10

Output Active from Output Enable

IGLQX

toll

0

-

0

Output Hold from Address Change

tAXQX

toH

4

5

Output Hold from MUX Control
Change

tVSXQX

tvSOH

4

-

5

-

Chip Enable to Output High Z

tE1HQZ
tE2LQZ

teHZ

0

10

0

15

2

MC58824A-35

Max

-

Unit

Notes

ns

35

ns

35

ns

35

ns

4

15

ns

ns

4,5

ns

5

5

-

0

15

ns

0
0
5

ns
ns
4,5

Output Enable High to Output High Z
15
0
8
0
15
0
ns
5
IGHQZ
toHZ
NOTES:
1. A read cycle is defined by Whigh.
2. All read cycle timings are re1erencecf from the last valid address or vector/scalar transition to the first address or vector/scalar transnion.
3. Addresses valid prior to or coincident with ET going low or E2 going high.
4. ET in the timing diagrams represents both 'ET and E2 with 'ET asserted low and E2 asserted high.
5. Transition is measured:l:5OO mV from steady-state voltage with load of Figure 1B. This parameter is samplad and not 100% tested. AI any
given voltage and temperature, IE 1HQZ max is less than lEI LQX min, tE2LQZ max is less than tE2HQX min, and IGHQZ max is less than
IGLQX min for a given device and from device to device.
READ CYCLE

~---------------------~VAV

A(ADDRESS)

~

....._ _ _ __

.-

Vi§(MUXCONTROL)

~

~VQV ------·~I

X----------....:.----------l

tAXQX

-+---:'::-.001-1- -

r ----..:....--

~
-~--tvSVQV ----+1.1

- - - ' ...

'

I::

tvSXQX

E1 (CHIP ENABLE)
1E1HaZ

....------ 'E1LQV --------.{

-a (OUTPUT ENABLE)
l:i (DATA OUT)

HIGH·Z

DATA VALID

MOTOROLA MEMORY DATA

7-62

HIGH-Z

MCM56824A

WRITE CYCLE TIMING (Write Enable Initiated, See Note 1)
Symbol
Parameler

MCMS6824A·20

Standard Alternate

MCMS6824A·25

MC56824A-35

Min

Max

Min

Max

Min

20

-

25

-

35

Max

Write Enable to Chip Enable Disable

twLE1H
twLE2L

tcw

15

Chip Enable to End of Write

tE1LWH
tE2HWH

tcw

15

Data Valid to End of Write

tDVWH

tow

8

Data Hold Time

twHDX

tDH

0

Write Recovery TlIlle

twHAX

twR

0

MUX Control Recovery Time

twHVSX

tvSR

0

-

Write High to Output Low Z

twHOX

t.wLz

4

-

5

-

5

-

Write Low to Output High Z

twLOZ

twHZ

0

15

0

15

0

15

Write Cycle Time

IAVAV

Address Setup Time

tAVWL

tAS

0

-

0

-

0

tvSVWL

tvss

0

0

0

15

-

15

-

10

15

0

-

MUX Conlrol Setup Time

twc

tAVWH

tAW

15

MUX Conlrol Valid to End of Write

tvsVWH

tvsw

15

Write Pulse Width

twLWH

t.wP

15

Address Valid to End of Write

20
20
15

0
0

30
30
20
20
20

0
0
0

Unit

Notes

ns

ns

6

ns

6

ns

2

ns
ns
ns
ns

3

ns

3,4

ns

3,4

ns
ns

5

ns

2

ns

NOTES:
1. A write cycle starts attha latest transition of E'f low, Wlow, or E2 high. A write cycle ends at the earliest transition ofE'f high, W high, or E2
low.
2. Write must be high for all address transitions.
3. If W goes low coincident with or prior to E'f low or E2 high tha outputs will remain in a high-impedance state.
4. E'f in the timing diagrams represents both E'f and E2 with E'f asserted low and E2 asserted high.
5. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.
6. Transition is measured ±500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tE 1HOZ max is less than tEl LOX min, tE2LOZ max is less than tE2HOX min, and IGHOZ max is less than
IGLOX min for a given device and from device to device.

WE INITATED WRITE CYCLE

~14----------- "AVAV

A(ADDRESS)

viS (MUX CONTROL)

---------------1--..

~"':==============--t"-WlH--:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.-:.:.~I-...

--------=:-tw-HAJ(---=i-----

~~

twHVSX~

_Jr\.
tvsVWH

!f (CHP ENABLE)

tE1LWH

~

J

i-tvsVWL

twLWH

~[-

W(WRITE ENABLE)
--tAVWL -

toVWH D(DATA tI)

o (DATA OUT)

r-

- W-

twHDX

hxxxxxx>

H~:'--=1xxxJ

MOTOROLA MEMORY DATA
7·53

-

VALID DATA IN

MCM56824A

WRITE CYCLE nMING (Chip Enable Initiated, See Note 1)
Symbol
Parameter

MCM56824A-20

Standard Alternate

Min

Max

MCM56824A-25
Min

IAVAV

twc

20

IAVElL
tAVE2H

tAS

0

-

tvSVE1L
tvSVE2H

tvss

0

-

0

tAVE1H
IAVE2L

tsw

15

-

20

MUX Control Valid to End 01 Write

tvSVE1H
tvSVE2L

tvsw

15

Chip Enable to End 01 Write

1E1LE1H
1E2HE2L

tcw

12

Data Valid to End of Write

tDVE1H
tDVE2L

tow

8

Data Hold lime

tE1HDX
tE2LDX

tDH

0

Write ReooVGfy lime

1E1HAX
1E2LAX

twA

0

1E1HVSX
1E2LVSX

tvSR

0

-

Write Cycle lime
Address Setup lime
MUX Control Setup lime
Address Valid to End 01 Write

MUX Control Recovery lime

25

0

20

15
10
0
0
0

MC56824A-35

Max

Min

Max

-

35

-

0
0
30
30
20
15
0
0
0

Unit

No...

ns
ns

2

ns

2

ns

2

ns

2

ns

2,3

ns

2

ns

2,4

ns

2

ns

2

NOTES:
1. A write cycle starts altha latest transition 01J:T low, Wlow, or E2 high. A write cycle ends at the earliesltransition olET high, Whigh, or E2
low.
2. Ef in the timing diagrams represents both Ef and E2 with ET asserted low and E2 asserted high.
3. II Wgoes low coincident with or prior to J:T low or E2 high the outpUts will remain in a high-impedance state.
4. During this time the output pins may be in the output state. Sig~als 01 opposite phase must not be applied to the outputs at this time .

•

E1 OR E2INlnATED WRITE CYCLE
1---------AVAV -------~------i
A(AODRESS)

--------- ~~==========~--IA~--l-H~~~~~~~~~~~~:·+I-·~--~-=-~-l-~--

----------

VIS (MUX CONTROl)
1 - - - - - tvs~lH --------g~~~IG~ ~ ~
7 6 5 4 3 2 1 52 51 50 49 4647
46
8
45
9
10
44
11
43
12
42
13
41
14
40
15
39
16
38
17
37
18
36
19
35
20
34
21 222324 25262728 29 30 31 3233

~ ~ ~

!< l\! !2 $:>g~

~ ~

::(

NC
D07
DQ6
Vee
VSSO

DOS

DQ4
D03
DQ2
VSSO
Vce
DOl
DOO

~

PIN NAMES
AD-A13 .......•...... Address Inputs
K ............................ Clock
WO, WI ................ Write Enable
G .. .. .. .. .. .. .. .. .... Output Enable
SE, SE ................. Chip Selects
DOD-DOI5 ........ Data Input/Output
Vce ............. + 5 V Power Supply
VCCO' ... Output Buffer Power Supply
VSS ........................ Ground
VSSO ................ Output Ground
NC .................. No Connection
All power supply and ground pins must be
connected for proper operation of the device. Vce ~ VCCO at all times including
power up.

CY7C157 Is a part number for a Cypress FSRAM.
SPARe is a trademark of SPARe International.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
7-66

MCM62157

BLOCK DIAGRAM
DQO-007 OOS-0015

G

K

SE
SE
AO-A13

LATCH

we

Wl---a

TRUTH TABLE (See Notes)
SE

SE

WO

W1

G

K

Input/Output

Operation

L

X

X

X

X

L-H

High-Z

Deselected

X

H

X

X

X

L-H

High-Z

Deselected

H

L

X

X

H

L-H

High-Z

Selected

H

L

H

H

H

H-L

High-Z

Read Cycle

H

L

H

H

L

H-L

Data Out

Read Cycle

H

L

H

L

H

H-L

High-Z

Write Upper Byte

H

L

L

H

H

H-L

High-Z

Wrile Lower Byte

H

L

L

L

H

H-L

High-Z

Write Both Bytes

H

L

L

X

L

H-L

Low-Z

Undefined

H

L

X

L

L

H-L

Low-Z

Undefined

NOTES:
1. All address and chip select inputs must meet set-up and hold times for all low to high
transitions of clock (K). Write WO and WI inputs must meet set-up and hold times for
all high to low transitions of clock (K).
2. During a Write cycle, Gmust be high before the input data required setup time and held
high throughout the data hold time.

MOTOROLA MEMORY DATA
7-07

•

MCM62157

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = Vsso = 0 V)
Rating

Symbol

Power Supply Voltage

Value

-0.5 to + 7.0
VCC
Yin, Vout -0.5 to VCC+ 0.5

Voltage Relative to VssNsso for Any
Pin Except VCC and VCCO

This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields;
however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated
voltages to this high impedance circu~.
This CMOS memory circu~ has been
designed to meet the de and ac specifications shown in the tables, aiter thermal equilibrium has been established.

Unit
V
V

Output Current (per I/O)

lout

±20

Power Dissipation (TA = 70'C)

Po

2.0

mA
W

Temperature Under Bias

Tbias

-10to+85

°c

Operating Temperature

TA

o to + 70

°c

Storage Temperature
-55to+ 125
°c
Tsta
NOTE: Permanent deVice damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
=Vcca = 5.0 V ± 10%, TA =0 to +70°C, Unless Otherwise Noted)

(VCC

RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = VSSO = 0 V)
Parameter

Symbol

Typ

Min

Max

Unit

VCC

5.0

4.5

5.5

V

VCCO

5.0
3.3

4.5
3.0

5.5
3.6

V

Input High Voltage

VIH

3.0

2.2

VCC+0.3

V

Input Low Voltage

VIL

0.0

-0.5-

0.8

V

Symbol

Typ

Min

Max

Unit

-

±1.0

~

Ilka{Ol

-

± 1.0

~

ICCA15
ICCA17
ICCA24

310
300
290

Standby Current (SE =VIH or SE =VIL, All Inputs =VIL and VIH
Cycle lime> tKHKH min)
,

ISBI

-

-

70

mA

CMOS Standby Current (SE" VCC - 0.2 V, SE" 0.2 V,
All Inputs "VCC - 0.2 V or" 0.2 V, Cycle lime> tKHKH min)

ISB2

-

40

mA

Supply Voltage (Operating Voltage Range)
Output Buffer Supply Voltage (5.0 V TTL Compatible)
(3.3 V 50 n Compatible)

-VIL(mln) = - 3.0 V ac (pulse width" 20 ns)

•

DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Yin

=0 to VCC)

Ilka(l)

=VIH, Vout = 0 to VCC)
AC Supply Current (G =VIH, lout =0 rnA VIH, All Inputs =VIL
VIL =0 V and VIH, Cycle lime" tKHKH min)

Output Leakage Current (G

or VIH

Output Low Voltage (IOL =+ 8.0 mAl
Output High Voltage (IOH

VOL

=- 4.0 rnA)

VOH

-

mA
360

-

0.4

V

2.4

-

V

NOTE: Good decoupling of the local power supply should always be used.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol

Typ

Max

Unit

Input Capacitance (All Pins Except 000-008)

Parameter

Cin

4

6

pF

Inpul/Output Capacitance (000--008)

Cout

8

10

pF

MOTOROLA MEMORY DATA

7-68

MCM62157

AC OPERATING CONDITIONS AND CHARACTERISTICS
(V CC = 5.0 V ± 10%, VCCQ = 3.3 V or 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall Time ..................................... 3 ns

Output Timing Reference Level .......................... 1.5 V
Output Load ............. See Figure I A Unless Otherwise Noted

READIWRITE CYCLE TIMING (See Notes I and 2)
MCM62157-15

MCM62157-17

MCM62157-24

Standard

Alternate

Min

Min

Min

Clock Control:
Cycle Time
Clock High Pulse Width
Clock Low Pulse Width

tKHKH
tKHKL
tKLKH

tCHCH
tCH
tCL

20
8
8

-

20
8
8

Read Cycles:
Clock Access Time
Output Enable to Output Valid

tKHOV
tGLOV

15

-

-

Symbol
Parameter

Max

Max

Max

Unit

Notes

ns

tcHOV

-

-

-

6

Output Buffer Control:
Clock High to Output Low-Z
Clock High to Output Change
Clock High to 0 High-Z
Output Enable to Output Active
Output Disable to 0 High-Z

tKHOXI
tKHOX2
tKHOZ
tGLOX
tGHOZ

Register Setup Times:
Address
Data
Write Enables
Chip Selects

tAVKH
tDVKL
twvKL
tsVKH

tAVCH
tDVCL
twLCL

2
3
2
2

-

2
3
2
2

Register Hold Times:
Address
Data
Write Enables
Chip Selects

tKHAX
tKLDX
tKLWX
tKHSX

tcHAX
tcLDX
tcLWH

3
2
3
3

-

3
2
3
3

tcHOX
3
5

0

-

-

3
5

10
-

0

-

7

-

-

-

-

30
12
12

-

17
7

-

24
9

-

3
5

-

10

-

ns

-

0

-

8

-

2
3
2
2

-

-

3
2
3
3

-

ns

3

ns

4

ns

4

-

12

9

-

-

-

NOTES:
I. A read cycle is defrined by WO and WI high for the set-up and hold times. A write cycle is defined by WO or WI low for the set-up and hold
times.
2. All read and write cycle timings are referenced from K or G.
3. Transition is measured ± 500 mV from steady-state voltage with load of Figure I B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tKHOZ max is less than tKLOXI min for a given device and from device to device.
4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for all rising (or
falling in the case of WO and WI) edges of clock (K) when device is selected. To select or deselect the device, both chip selects must be valid
at the riSing edge of K. Timings for SE and SE are similar.

q

AC TEST LOADS

+5V

DO

255 Q

480Q

q

+5V 480Q

DO
85pF
(INCLUDING
SCOPE AND JIG)

255 Q

Figure lA

5 pF
(INCLUDING
SCOPE AND JIG)

Figure 18

MOTOROLA MEMORY DATA
7-69

•

MCM62157

READIWRITE CYCLES

K

(ADDRESS)

(DATA OUT) - - - - - - (

•

tDVKl
D(E)

(DATA IN)
READ

WRITE

ORDERING INFORMATION
(Order by Full Part Number)

W.5Z
Motorola Memory Prefix
Part Number

I

Full Part Numbers- MCM62157FN15

i f'

Speed (15 = 15 ns, 17 = 17 ns, 24 = 24 ns)
Package (FN = PLCC)

MCM62157FN17

MCM62157FN24

MOTOROLA MEMORY DATA
7-70

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62350
4Kx4 Bit Cache Address Tag
Comparator
with System Status Bit Functions
The MCM62350 is a 16,384 bit cache address tag comparator organized as 4096 tags
of 4 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology.
The device integrates a 4Kx4 SRAM core, an on-board comparator, and special pin
functions for tag valid and system status bit applications. These functions allow easy
interface to the MC68020 and MC68030 microprocessors, or any other environment
where efficient implementation of external cache memory is required. The MC62350 is
available in 24 lead plastiC DIP and SOJ packages.
The device has a reset (A) pin for flash clear of the RAM within two minimum cycles.
This function is useful for system initialization. Individual bits within a tag field can be set
or cleared via the BSET and BClR control input pins for valid bit updates.
The MCM62350 has two configurable comparator modes. The comparator can be
configured as standard XNOR (exclusive NOR) for address tag comparison, or AOI
(AND-OR-Invert) for determining whether specific bits in the 4-bit word are set (for
system status bit applications). In addition, the MATCH output can be programmed as
true high or true low for potential logic delay savings. The configuration of these modes
is accomplished by performing a write cycle with the R pin held low.
.
•
•
•
•
•
•
•
•

Single 5 V ±10% Power Supply
20/22/25 ns max
Fast Address to MATCH 'Time;
10/10112 ns max ..
Fast Data to MATCH 'Time;
Fast Read of Tag RAM Contents; 22125/30 oS,max
Flash Clear of the Tag RAM
Programmable Active Output Level of MATCH
Bit Manipulation of Tags via '§SEf and BClR Writes"
Configurable Comparator Mockis:
XNOR Mode for Address Tag Comparison
AOI Mode for System Valid Bit Comparison

~~~G'

300 MIL PLASTIC
CASE 724

JPACKAGE
3OOMILSOJ
CASE 810A

PIN ASSIGNMENT
A4

VCC

AS

A3

A6

A2

A7

A1

AS

AO

A9

R

A10

Vss

A11

D03

S
iii

D02
D01

BelR

DOO

BSET

MATCH

BLOCK DIAGRAM
AO-A6 ---'7'-1

R----<'---_ _>C

tAVAV
A (ADDRESS)

S (CHIP SELECT)

--------------------~------~r--tsLOX

BSET (BIT SET)
tBSLMX

BCiJi (BIT CLEAR)

tBCLQX-~:::jf:t----I------1--tBCLMX
Q(DATAOUT)--- HIGH-Z - - i - I (

- - HIGH-Z

MATCH

(ASSERTED)

MOTOROLA MEMORY DATA
7-74

MCM62350

COMPARE CYCLE (See Notes 1 and 2)
Symbol
Characteristic

Standard

62350-18
Alternate

Min

Max

20

-

Compare·Cycle lime

tAVAV

Ie

Address Valid to MATCH Valid

tAVMV

tACA

BClR High to MATCH Valid

tBCHMV

tBCCA

BSET High to MATCH Valid

tBSHMV

tBSCA

-

Data Valid to MATCH Valid

tDVMV

tDCA

-

18
15
15
10

S low to MATCH Valid

tSlMV

tCSCA

-

12

MATCH Hold from Address
Change

tAXMX

tACH

5

-

MATCH Hold from Data
Change

tDXMX

tDCH

2

-

0

10

S High to MATCH Assert

tSHMX

leH

BClR High to Output High-Z

tBCHQZ

tBCZ

BSET High to Output High-Z

tBSHQZ

tBSZ

-

7
7

62350-20
Min

Max

22

-

-

Min
30

25

22

15

-

15

-

15

-

15

-

10

-

10

-

12

-

15

-

3
0

-

62350-25

Max

-

20

-

5

62350-22
Min

3

-

10

0

8

-

8

-

9

5

Max

Unit Notes

-

ns

25

ns

18

ns

3

18

ns

3

12

ns

18

ns

3

-

10

0

12

ns

9

-

10

ns

4

10

ns

4

5

ns
ns

NOTES:
1. R =VIH, W=VIH continuously during compare cycles.
2. MATCH assertion is always shown high for distinction between asserted and valid.
3. For brevity in signal names, BC is used to represent BClR transitions, while BS is used to represent BSET transitions.
4. Transition is measured ±500 mV from steady state voltage with load of Figure 1b. This parameter is sampled and not 100% tested.

COMPARE CYCLE

(5 CONTROllED)

(ADDRESS CONTROllED)

1 - - - - - tAVAV
A (ADDRESS)
tAVMV

5 (CHIP SELECT)

---+I

(5 = Vll)
------------------+-----~
'sHMrl--I

BSET (BIT SET)

BClR (BIT CLEAR)

D (DATA IN)

-------K

DATA VALID

Q(DATAOUT)

----

\4--*- tDVMV
HIGH-Z ---+-----f--

M~CH-----------~~---4~

(ASSERTED)

MOTOROLA MEMORY DATA
7-75

•

MCM62350

STANDARD WRITE CYCLE (See Notes 1 and 2)
Symbol
Characteristic

62350-18
Max

Standard

Alternate

Write Cycle Time
Write Pulse Width

tAVAV
twLWHItSLSH
twLSHItSLWH

twc
twp
twp

Address Setup to Beginning of
Write

tAvwLftAVSL

tAS

0

tAVWHItAVSH

14
10
0

Address Valid to End of Write
Data Valid to End of Write
Data Hold from Write End
Write Low to Output High-Z
Address Hold from Write End
Write Low to MATCH Assert
BSETIBCLR Setup to
Beginning of Write

toVWHilOVSH
twHOXItSHOX

tAW
tow
tOH

twLOZ
twHAXItSHAX
tWLMX
tBSHWLItBSHSL
tBCHWLItBCHSL

twz
twR
twCH
tBSS
tBCS

BSET/BCLR Hold Time from
Write Start

twLBSXItSLBSX
twLBCXItSLBCX

tBSH
tBCH

Min
20
14

-

-

8

0
0
-1

-

10

-

62350-20
Max

Min
22
16

-

-

0
16
10
0

-

8

62350-22
Max

Min
25
18

0
18
10
0

-

-

-

0
0
-1

-

0
0
-1

-

10

-

10

15

15

-

-

62350-25
Max

Min
30
20

-

0

-

-

Unit Notes
ns
ns
ns

9

-

-

0
0
-1

-

ns
ns
ns
ns
ns
ns
ns

10

-

ns

20
12
0

15

-

-

10
15

3,4
4

Write High to MATCH Valid
18
20
22
25
ns
4
twHMV
twCA
Write High to Output Active
3,4
5
5
ns
3
3
tow
twHDX
NOTES:
1. A standard write occurs during the overlap of Vi and S low and BSET and BCLR high. The R pin is high continuously during a write cycle.
2. MATCH assertion is always shown high for distinction between asserted and valid.
3. Transition is measured ±SOO mV from steady state voltage with load of Figure 1b. This parameter is sampled and not 100% tested.
4. Both the MATCH output and 00-03 are shown as valid in the Vi controlled cycle below to convey their timing relative to Vi. In reality, only
one of either MATCH or 00-03 can be valid at one time, as determined by BSET and BCLR inputs.

-

-

-

-

STANDARD WRITE CYCLE

..

(iii CONTROllED)

(8 CONTROllED)

1 4 - - - - - tAVAV - - - - - + I

1+-----

tAVAV

----~

A(ADDRESS)

1+----

tAVWH

---+1---1+
-+---1

1 - - - - twlSH

S (CHIP SELECT)

"iii (WRITE ENABLE)

BSET (BIT SET)

BClR (BIT CLEAR)

D(DATA IN)

-----+--{
twlQZ

Q(DATAOUT)

- - - - - - - - HIGH·Z - - - - - -

----.,.---'
twLMX
(ASSERTED)

MATCH

MOTOROLA MEMORY DATA
7-76

MCM62350

BSET/BCLR WRITE CYCLE (See Notes 1 and 2)
Symbol
Characteristic
Write Cycle Time
Write Pulse Width

62350-18

62350-20

Standard

Alternate

Min

Max

Min

tAVAV

twc

20
14

-

twlWf+'tSlSH
twlSHItSlWH

-

22
16

0

-

14
0

-

Address Setup to Beginning of
Write

tAVWt!tAVSl

twP
twP
tAS

Address Valid to End of Write
Data Setup to Beginning of
Write

tAVWH/tAVSH

tAW

tDVWlltDVSl

tDS

Data Hold from Write End
Address Hold from Write End

twHDXItSHDX

tDH

twHAXItSHAX

tWR

W Low to MATCH Assert
BSET/BClR Setup to
Beginning of Write

twlMX
tBSlWt!tBSlSl
tBClWlItBClSl

tWCH

BSET/BClR Hold Time from
Write Start

twlBSX/tSlBSX
twlBCxttSlBCX

tBSH
tBCH

tBSS
tBCS

0
0

15

Max

62350-22

62350-25
Unit Notes

Min

Max

Min

Max

-

25
18

-

30
20

-

ns

0

-

0

-

0

-

ns

16

-

0

-

18
-1

-

20
-1

-

ns
ns

0
0

-

0
0

-

-

0
0

-

ns
ns

15

0
-1

15

-

ns
ns

10

-

ns

15

0
-1

-

0
-1

-

0
-1

10

-

10

-

10

-

ns

3

3

-

Write High to MATCH Valid
22
ns
18
20
25
twHMV
twCA
NOTES.
1. A BSETIBClR write occurs during the overlap of iN and S low and BSET or BClR low. The R pin is high continuously during a write cycle.
BSET and BClR write cycles can be iN controlled or S controlled. Only two of four possible cycles are shown here for brevity.
2. MATCH assertion is always shown high for distinction between asserted and valid.
3. Data output buffer must be in high-Z prior to start of either BSET or BClR write cycles. Note that for iN controlled cycles, the user must
avoid excessive setup time of BSET/BClR to avoid bus contention. Data musl be set up for tDVWt!tDVSl time to ensure the data integrity
of non-modified bits during BSET/BClR write cycles. In the event that invalid data is presented for non-modified bits during the BSET/BClR
write, note that is is not possible to recover the original data state by simply presenting valid data before the end of write.

BSET WRITE CYCLE

BCLR WRITE CYCLE

rn CONTROllED)

(8 CONTROllED)

; - - - - - - tAVAV - - - - + \
A (ADDRESS)

1----

tAVWH ---/-01---1; - - - - twlSH -+---.1

8 (CHiP SELECn

W(WRITE ENABLE)

BSET (BIT SET)

BClR (BIT CLEAR)

o(DATA iN)
Q(DATAOUT)

-----1---

- - - - - - - - HIGH-Z - - - - - - -

MATCH

(ASSERTED)

MOTOROLA MEMORY DATA
7-77

•

MCM62350

CLEAR CYCLE (See Notes 1 and 2)
Symbol
Characteristic

62350-18
Altemate

tRLAV
tRlSV
tRlBSV
tRlBCV
tRlDV

leR
leR
tCR
tCR
tCR

R Pulse Width

tRlRH

lelP

20

Read Setup to R low

twHRl

tRS

5

Write Hold from R High

tRHWl

twH

0

-

tRLAX
tRlSX
tRlBSX
tRlBCX
tRlDX

lex
lex
lex
lex
lex

0

-

R Low to MATCH Assert

tRlMX

tMH

0

R low to Output High-Z

tRlQZ

lez

-

R low to Inputs Recognized A
(Clear Cycle Time)
S
BSET
BClR
D

R low to Inputs Don't Care

A

S
BSET
BClR
D

Min

Max
70

Standard

-

-

62350-20
Min

-

22

Min

-

25

0

-

0

-

15

0

15

-

5

62350-22

Max
70

-

6235Q.25

Max
70

-

0

-

0

-

15

0

15

-

5

Min

-

30

Max
70

-

Unit Notes
ns

ns

0

-

0

-

ns

15

0

18

ns

15

-

18

ns

5

ns
ns

3
3
4

5

NOTES:
1. The address, BSET, and BClR inputs are don't cares during a clear cycle.
2. MATCH assertion is always shown high for distinction between asserted and valid.
3. The clear cycle is initiated at the falling edge ofR. The twHRl and tRHWl parameters must be satisfied to prevent an undesired configuration
cycle.
4. "Inputs· for this parameter refers to all inputs except W.
5. Transition is measured ±500 mV from steady state voltage with load of Figure 1b. This parameter is sampled and not 100% tested.

CLEAR CYCLE
(FROM COMPARE CYCLE)

(FROM READ CYCLE)
A (ADDRESS)

•

tRLAX-+--~

S (CHIP SELECT)

1 - - - - - tRLAV - - - - . I

tRLAX
tRLSX

R(RESET)

W(WRITE ENABLE)

tRLBSX
BSET (BIT SET)

BCLR (BIT CLEAR)

tRLBCX

1-----

tRLDV

tRLDX-t--~

D(DATAIN)

MATCH

(ASSERTED)

t - - - - t - tRLQZ
Q(DATAOUT)

} I - - - - - HIGH·Z - - - -

- - - - - - - HIGH·Z - - - - - - -

MOTOROLA MEMORY DATA
7-78

MCM62360

CONFIGURATION CYCLE (See Notes 1 and 2)
Symbol
Characteristic

62350-18

62350-20

Max

-

10

-

-

0

-

-

ns

10

-

12

-

ns

-

0

-

0

-

ns

5

-

5
18

-

-

5

-

5
20

5
5

-

-

-

ns
ns

-

5
5
20

-

25

-

ns

tSR

18

-

20

-

20

25

-

ns

tcss

5

5

-

0

-

5
0

ns

0

5
0

-

twss
tHZ

-

-

-

ns
ns

Max

Configuration Control Pulse S
Width
R

tSLSH
tRLRH

tsp
tsp

-

Oata Setup to End of
Configuration Cycle

S
R
W

tOVSH
tOVRH
tOVWH

10

-

Oata Hold from End of
Configuration Cycle

S
R
W

tSHOX
tRHOX
tWHOX

tOH
tOH
tOH
tcp

0

tSLWH
tSLRH

tws
tsws
tscs

R Setup to End of
Configuration

tRLWH

R Setup to SLow
S Setup to Beginning of Write

tRLSL
tSHWL

tRHRL
tWLRL

Unit Notes

Max

Min
20

R High Pulse Width

62350-25
Min
25

Alternate

Write Setup to R Low
S Setup to End of
Configuration

62350-22
Min
22

Standard

Min
18

Max

tos
tos
tos

-

-

-

-

3

4

3

10
5
S High to Output High-Z
9
9
9
tSHOZ
10
ns
5
W Low to Output High-Z
9
9
9
tHZ
twLOZ
NOTES:
1. A configuration cycle is performed during the overlap of W low, R low, and S low. Address, 002, 003, BSET, and BCLR inputs are don't
cares during configuration cycles.
2. To ensure proper configuration of the device during power up, chip select must be equal to or greater than VIH.
3. A valid configuration can be performed with S asserted prior to Rand W low transitions. Be aware, however, that array data may be altered
under this condition.
4. Note that terminating the cycle with R while leaving Wand S asserted may cause array data to be altered.
5. Transition is measured ±500 mV from steady state voltage with load of Figure 1b. This parameter is sampled and not 100% tested.

-

CONFIGURATION CYCLE
(ARRAY UNPROTECTED)

(ARRAY PROTECTED)

S (CHIP SELECT)

R(RESET)

W(WRITE ENABLE)

D (DATA IN)-+--{

Q (DATA OUT)

)1------

HIGH-Z - - - - - -

MOTOROLA MEMORY DATA
7-79

•

MCM62350

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory Prefix

T

J 11 T
62350

X XX XX

Part Number - - - - - - - - - - - - '

"" ........'" ,.. -,.,.. -.

OM' - ..."

Speed (18 = 18 ns, 20 = 20 ns, 22 = 22 ns, 25 = 25 ns)
Package (P = 300 mil Plastic DIP, J = 300 mil SOJ)

Full Part Numbers -

MCM62350P18
MCM6235OJ18
MCM62350J18R2

MCM62350P20
MCM62350J20
MCM62350J20R2

MCM62350P22
MCM62350J22
MCM62350J22R2

..

MOTOROLA MEMORY DATA

7-80

MCM62350P25
MCM62350J25
MCM62350J25R2

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - -

TECHNICAL DATA

MCM62351

4Kx4 Bit Cache Address Tag
Comparator
with System Status Bit Functions
The MCM62351 is a 16,384 bit cache address tag comparator organized as 4096 tags .
of 4 bits, fabricated using Motorola's high-performance silicon-gate CMOS technology.
The device integrates a 4Kx4 SRAM core, an on-board comparator, and special pin
functions for tag valid and system status bit applications. These functions allow easy
interface to the MC68020 and MC68030 microprocessors, or any other environment
where efficient implementation of external cache memory is required.
The device has a reset (R) pin for flash clear of the RAM, which is useful for system
initialization. Individual bits within a tag can be set or cleared via the BSET and BClR
control input pins for valid bit updates.
The MCM62351 has two configurable comparator modes. The comparator can be
configured as standard XNOR (exclusive NOR) for address tag comparison, or AOI
(AND-OR-Invert) for determining whether specific bits in the 4-bit word are set (for
system status applications). The configuration of the comparator is accomplished by
performing a write cycle with the R pin held low. The MATCH output is open drain, allowing efficient combination of multiple MATCH outputs using a wired-OR connection.
•
•
•
•
•
•
•
•

Single 5 V ±10% Power Supply
20/22125 ns max
Fast Address to MATCH Time;
1011 0/12 ns max
Fast Data to MATCH Time;
Fast Read of Tag RAM Contents; 22/25/30 ns max
Flash Clear of the Tag RAM
Open Drain MATCH Output
Bit Manipulation of Tags via imEIT and BCiJi Writes
Configurable Comparator Modes:
XNOR Mode for Address Tag Comparison .
AOI Mode for System Valid Bit Comparison
• High Board Density SOJ Package Available

---

300 MIL PLASTIC
CASE 724

JPACKAGE
300MILSOJ
CASE 810A

PIN ASSIGNMENT

M[

1.

AS [ 2

AS [ 3

PVCC
PA3
22 pA2

24

23

A7 [ 4

21

P A1

AS [ 5

20

A9 [ 6

19

PAO
Pil

A10 [ 7

18

VSS

A11 [ 8

17

DC3

S[
W[

9

16

DQ2

10

15

BCLR [ 11

14

P DC1
poao

BSEf[ 12

13

P MATCH

BLOCK DIAGRAM
AO·AS --...k.t'-l

i l - -........ j

1--------_--1

PIN NAMES

MEMORY
MATRIX
128 ROWS
x128 COLUMNS

MATCH
DQO·DQ3
COLUMN
1/0
COLUMN
DECODER

W

5
BSET
BCLR

A7·A11

5

MOTOROLA MEMORY DATA
7-81

AO-A 11 ..•.•.•....... Address Inputs
W ..................... Write Enable
S ....................... Chip Select
BClR .•........ Bit Clear Control Input
BSET ........... Bit Set Control Input
R ........... Reset (Flash Clear) Input
MATCH ......... MATCH (Hit) Output
DQO-DQ3 . . . . . . . .. Data Input/Output
VCC ............. +5 V Power Supply
VSS ........................ Ground

•

MCM62351

SIGNAL DESCRIPTIONS
bits within the tag can be cleared using the appropriate mask,
as indicated in the bit clear truth table. The BelR input can
also be used to initiate a read cycle (note that at least one olthe
BSET/BelR signals must be asserted to trigger a read cycle).

AO-A11 - ADDRESS INPUTS
The address lines are used for indexing into the tag RAM
portion of the chip.
DQO-DQ3 - DATA INPUT/OUTPUT
The data lines are used as inpullor compare, write, and configuration cycles, and as output for read cycles.

R-

RESET (FLASH CLEAR) INPUT

The reset control signal is used to initiate a clear cycle or a
configuration cycle.

BSET - BIT SET CONTROL INPUT
This control signal is used for ORing data into the tag RAM
during BSET write cycles. Independent bits within the tag can
be set using the appropriate mask, as indicated in the bit set
truth table. The BSET input can also be used to initiate a read
cycle.
BCLR - BIT CLEAR CONTROL INPUT
This control signal is used for ANDing the complement of
data into the tag RAM during BeLR write cycles. Independent

S-

CHIP SELECT
This control signal is used to chip select the device.

W- WRITE ENABLE
The write enable signal is used to initiate wrije cycles.
MATCH - MATCH (Hln OUTPUT
This output signal is used to indicate a match of DaD-D03
inputs with the contents olthe tag RAM addressed by AD-A 11.

FUNCTIONAL TRUTH TABLE

•

S

W

aCLR

aSET

R

L
L
L
L
L
L
X
L
H

H
H
H
L
L
L
H
L
X

H
L
X
H
L
H
X
X
X

H
X
L
H
H
L
X
X
X

H
H
H
H
H
H
L
L
H

DQO-OO3

MATCH
Valid
Assert
Assert
Assert
Assert
Assert
Assert
Assert
Assert

Compare Din
Read Dout
Read Dout
Write Din
Bit Clear Mask
Bit Set Mask
High-Z
Config Din'
High-Z

Cycle
Compare
Read
Read
Write
BCLRWrite
BSETWrtte
Clear (Reset)
Configuration
Deselect

'DOl, 002, and 003 are don't cares during a configuralion cycle .

COMPARATOR TRUTH TABLE
Type

DQO

DQl

DQ2

DQ3

RAMQO

RAMQ1

RAMQ2

RAMQ3

MATCH

XNOR
XNOR
AOI
AOI
AOI

00
00
00
L
H

01
01
01
01
01

02
02
02
02
02

03
03
03
03
03

00
00

01
01
01
01
01

02
02
02
02
02

03
03
03
03
03

1
0
1
1
0

QO

X
L

BIT CLEAR TRUTH TABLE (See Note)
Data
In

Initial
Stored Data

Final
Stored Data

0
0

0

0

1

1

1
1

0

0
0

1

BIT SET TRUTH TABLE (See Note)
Data
In

Initial
Stored Data

Final
Stored Data

Bit
Unchanged

0
0

0
1

0
1

Bit
Unchanged

Bit Cleared
to "Zero"

1
1

0
1

1
1

Bit Set
to "One"

..

NOTE: These tables reflect the behaVior of slOgle bit positions. The
four bits in the tag can all be set or cleared in tandem, or bits
within the tag can be independently set or cleared with the appropriate mask.

AOI COMPARATOR LOGIC DIAGRAM

CONFIGURATION TABLE
DQO

Comperator
Type

L
H

XNOR
AOI

L=Low
H = High
0= False
1 = True
X = Don't Care

MEMORY
ARRAY

001 003

MOTOROLA MEMORY DATA
7-82

MCM62351

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS
Rating

Symbol

Power Supply Voltage
Voltage Relative to VSS for Any Pin
ExceptVcc
Output Current

= 0 V)

Value

Unit

VCC

-0.5 to +7.0

V

VinNout

-0.5 to VCC +0.5

V

lout

±40
±20

mA

MATCH Output
110 Pins, Per 1/0

Power Dissipation (TA = 25°C)

PD

1.0

W

Operating Temperature

TA

oto +70

°c

Storage Temperature

Tstg

-55 to +125

°c

Temperature Under Bias

Tbias

-10to +85

'c

This device contains circuitry to protect
the inputs against damage due to high static
voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high-impedance circui!.
The power supply (VCC) should be
stable for at least 100 J!S before operating
the device. During this interval, the part will
internally configure itself for XNOR compares. In addition, the memory array of
RAM bits will be cleared.

NOTE: Permanent deVice damage may occur If ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V ±1 0%, TA = 0 to 70'C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Referenced to VSS

= 0 V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC +0.3

V

Input Low Voltage

VIL

-OS

-

0.8

V

Parameter

VIL min = -0.5 V dc; VIL min = -3.0 V ac (pulse width :>20 ns)
DC CHARACTERISTICS
Characteristic

Symbol

Min

Max

Unit

Ilkg(l)

-

±1.0

J!A
J!A
J!A

= 0 to VCC)
Output Leakage Current (S = VIH, Vout = 0 to VCC)

Ilkg(O)

MATCH Output Leakage Current (MATCH Asserted)

Ilkg(M)

Input Leakage Current (All Inputs Vin

AC Supply Current (All Inputs = VIL or VIH, lout

-

±1.0
±2.0

140'
mA
= 0 mA, Cycle lime 2: tAVAV min)
ICCA
0.4
V
Output Low Voltage (110 Pins: 10L = 8.0 mA, MATCH Output: 10L = 25.0 mAl
VOL
2.4
Output High Voltage (110 Pins: IOH = 4.0 mAl
V
VOH
..
..
ICC active current for the clear cycle exceeds this speCification. However, this IS a transient phenomenon and Will not affect the power diSSipation

.

of the device. Good decoupling of the local power supply should always be used.
CAPACITANCE (f = 1 0 MHz dV = 3 0 V T A

= 25°C

Periodically Sampled Rather Than 100% Tested)

Characteristic

Symbol

Typ

Max

Input Capacitance

Cin

4

5

pF

110 Capacitance

Cout

5

7

pF

Cmatch

6

7

pF

q

MATCH Output Capacitance

AC TEST LOADS

+5V

Q

255

q

Unit

+5V

481
Q

30 pF
(INCLUDING
SCOPE AND JIG)

Figure 18

255

481
MATCH
5pF
(INCLUDING
SCOPE AND JIG)

Figure 1b

MOTOROLA MEMORY DATA
7-83

+¥

184

---150PF
(INCLUDING
-= SCOPE AND JIG)

I

Figure 1c

•

MCM62361

AC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ±10%, TA =0 to 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall Time ..................................... 5 ns

Output Timing Measurement Reference Level ............. 1.5 V
Output Load (VO Pins) .......................... See Figure 1a
Output Load (MATCH Output) ................... See Figure 1c

READ CYCLES (See Note 1)
Symbol

Characteristic

62351-18

Standard

Alternate

Min

Max

-

62351-20

Min

62351-22

62351-25

Max

Min

Max

-

25

-

30

-

22

-

25

-

30

ns

15

ns

30

ns

2

30

ns

2

-

ns
ns

3

ns

3

Read Cycle Time

tAVAV

tRC

20

Address Access Time

tAVQV

tAA

20

Select Access Time

tSLQV

tACS

-

10

-

BCLR Access Time

tBCLQV

tABC

-

20

-

22

BSET Access Time

tBSLQV

tABS

-

20

-

22

Output Hold from Address
Change

tAXQX

toH

0

-

0

Select Low to Output Active

tSLQX

tCSL

5

-

5

-

5

-

5

BSET/BCLR Low to Output
Active

tBSLQXItBCLQX

tLZ

7

-

7

-

10

-

10

-

22

Unit Notes

Min

Max

11

-

-

12
25
25

-

0

0

ns

tSHQZ

tcsz

-

8

-

10

ns

3

tHZ

7

-

8

-

9

tBSHQZItBCHQZ

-

7

BSET/BCLR High to Output
High-Z

9

-

10

ns

3

BSET/BCLR Low to MATCH
Assert

tBSLMXItBCLMX

tcH

0

15

0

15

0

15

0

18

ns

S High to Output High-Z

NOTES:

1.

•

R= VIH, W= VIH continuously during read cycles. One of either BSET or BCLR pins must be asserted lowto activate the outputs. The MATCH

output becomes asserted when either the BSET or BCLR pin transitions low.
2. For brevity in signal names, BC is used to represent BCLR transitions, while BS is used to represent BSET transitions .
3. Transition is measured ±SOO mV from steady state vo~age with load of Figure 1b. This parameter is sampled and not 100% tested.

READ CYCLE

(s CONTROLLED)

(ADDRESS CONTROLLED)

=x>---_ _>C

tAVAV
A (ADDRESS)

S (CHIP SELECT)

----------~----_+------_r-tBSLOX+o---!

tSLOX

BSET (BIT SET)
tBSlMX
BClR (BIT CLEAR)
tBClQX -t---t~
tSClMX
Q(DATAOUT)--- HIGH-Z

--+-1{

- - HIGH-Z

MATCH

MOTOROLA MEMORY DATA

7-84

MCM62351

COMPARE CYCLE (See Note 1)
Symbol
Characteristic

Standard

62351-18

Alternate

Compare Cycle TIme

tAVAV

Ie

Address Valid to MATCH Valid

tAVMV

tACA

BClR High to MATCH Valid

tBCHMV

tBCCA

BSET High to MATCH Valid

tBSHMV

tBSCA

Data Valid to MATCH Valid

tOVMV

tOCA

Min

Max

20

-

-

18

-

62351-20

Min
22

-

62351-22

62351-25

Max

Unit Notes

Min

Max

Min

-

25

-

30

-

ns

20

-

22

-

25

ns

15

-

Max

S Low to MATCH Valid

tSlMV

tCSCA

12

-

12

-

15

-

18

ns

MATCH Hold from Address
Change

tAXMX

tACH

5

-

5

-

5

-

5

-

ns

MATCH Hold from Data
Change

tOXMX

tOCH

2

-

3

-

3

-

3

-

ns

15
15
10

15
15
10

15
10

18

ns

2

18

ns

2

12

ns

S High to MATCH Assert

tSHMX

tCH

a

10

0

10

a

10

a

12

ns

BClR High to Output High-Z

tBCHQZ

tBCZ

7

-

10

ns

3

tBSZ

-

9

tSSHOZ

-

8

BSET High to Output High-Z

-

9

-

10

ns

3

7

8

NOTES:
1. R = VIH, W= VIH continuously during compare cycles.
2. For brevity in signal names, BC is used to represent BClR transitions, while BS is used to represent BSET transitions.
3. Transition is measured ±sao mV from steady state voltage with load of Figure 1b. This parameter is sampled and not 100% tested.

COMPARE CYCLE
(8 CONTROllED)

(ADDRESS CONTROllED)

1 - - - - tAVAV
A (ADDRESS)
tAVMV --...-,~

8 (CHIP SELECn

(8 = Vll)
----------~------+-----4__
tsHMrl---I~

BSET (BIT SEn

BClR (BIT CLEAR)

o(DATA IN) -------1{

DATA VALID

1--+1-- tOVMV
Q(DATAOUT)

- - - - HIGH-Z

---+----+-

M~CH----------__+---~~

VALID

MOTOROLA MEMORY DATA
7-65

MCM62351

STANDARD WRITE CYCLE (See Note 1)
Symbol
Characteristic

Stsl1dard

62351·18
Alternate

Min

Write Cycle Time

tAVAV

Write Pulse Width

twLwHltSLSH
tWLSH/tSLWH

twc
twp
twp

20

Address Setup to Beginning of
Write

tAVWLItAVSL

tAS

0

14

Max

-

-

62351·20
Min

Max

16

-

0
16

22

62351·22
Max

Min
18

-

-

0

62351·25
Min Max

Unit Notes

20

-

-

0

-

ns

18

-

20

-

12

0

-

0

-

ns

10

25

30

ns
ns

Address Valid to End of Write

tAVWH/tAVSH

tAW

14

Data Valid to End of Write

tDVWHItDVSH

tDW

10

-

10

Data Hold from Write End

twHDx/tSHDX

tDH

0

0

twLQZ

twz

-

-

-

8

-

8

-

9

-

10

ns

twHAX/tSHAX

tWR

0

-

0

-

0

-

0

-

ns

15

ns

Write Low to Output High-Z
Address Hold from Write End

tWLMX

tWCH

0

15

0

15

0

BSET/BCLR Setup to
Beginning of Write

tBSHWLItBSHSL
tBCHWl/tBCHSL

tBSS
tBCS

-1

-

-1

-

-1

BSET/BCLR Hold Time from
Write Start

twLBSXItSLBSX
twLBCx/tSlBCX

tBSH
tBCH

10

-

10

-

10

-

Write High to MATCH Valid

twHMV

twCA

-

18

-

20

-

22

Write High to Output Active

tWHOX

tow

3

Write Low to MATCH Assert

-

3

-

5

15

-

0
-1
10

5

-

ns
ns
2,3
3

ns
ns

25

ns

3

-

ns

2,3

NOTES:
1. A standard write occurs during the overlap of Wand S low and BSET and BCLR high. The R pin is high continuously during a write cycle.
2. Transition is measured ±SOO mV from steady state voltage with load of Figure 1b. This parameter is sampled and not 100% tested.
3. Both the MATCH output and 00-03 are shown as valid in the W controlled cycle below to convey their timing relative to W. In reality, only
one of either MATCH or OO--Q3 can be valid at one time, as determined by BSET and BClR inputs.

STANDARD WRITE CYCLE

(W CONT tlOllED)
\ - - - - tAVAV

•

(S CONTROllED)

----+\

A (ADDRESS)

\ - - - twlSH

S (CHIP SELECT)

--1--+\

W(WRITE ENABLE)

BSET (BIT SET)

BClR (BIT CLEAR)

D(DATAIN)

twlQZ~--I
- - - - - - - - HIGH-Z - - - - - -

Q(DATAOUT)
twlMX

(ASSERTED)

MATCH

MOTOROLA MEMORY DATA

7-86

MCM62361

BSET/BClR WRITE CYCLE (See Note 1)
Symbol

Characteristic

62351-18

Standard

Alternate

Min

Write Cycle TIme

tAVAV

twc

20

Write Pulse Width

tWLWH/tSLSH
twLSHItSLWH

twp
twp

14

-

Address Setup to Beginning of
Write

tAVWLItAVSL

tAS

0

Address Valid to End of Write

tAvwt¥tAVSH

tAW

Data Setup to Beginning of
Write

tDVWLItDVSL

tDS

Data Hold from Write End

twHDXItSHDX

tDH

Address Hold from Write End

twHAXItSHAX

twR

W Low to MATCH Assert

Max

62351-20
Min

62351-22

62351-25
30

-

ns

-

ns
ns

-

ns

-

ns

-

25

16

-

0

-

0

14

-

16

-

20

-

0

-

18

0

-1

-

-1

0

-

0

0

0

-

0

-

0

-

18

0

-

-

UnH Notes

Max

Min

22

Max

Min

Max

20
0

0

ns

ns

twLMX

twCH

0

15

0

15

0

15

0

15

ns

BSET/BCLR Setup to
Beginning of Write

!aSLWLItBSLSL
tBCLWLftBCLSL

tBSS
tBCS

-1

-1

-

-1

-

-1

twLBsxlIslBSX
twlBCx/tSlBCX

tBSH
tBCH

10

10

-

10

-

10

-

ns

BSETIBCLR Hold TIme from
Write Start

-

-

-

-

2

2

ns

-

Write High to MATCH Valid
18
20
22
25
ns
twHMV
twCA
NOTES:
1. A BSETIBCLR write occurs during the ove~ap of Wand S low and BSET or BCLR low. The R pin is high continuously during a write cycle.
BSET and BClR write cycles can be W controlled or S controlled. Only two of four possible cycles are shown here for brevity.
2. Data output buffer must be in high-Z prior to start of enher BSET or BCLR write cycles. Note that for W controlled cycles, the user must
avoid excessive setup time of BSET/BClR to avoid bus contention. Data must be set up for tDVWlItDVSL time to ensure the data integrity
of non-modified bits during BSET/BCLR write cycles. In the eventthat invalid data Is presented for non-modified bits during the BSET/BCLR
write, note that is is not possible to recover the original data state by simply presenting valid data before the end of write.
BClR WRITE CYCLE
(5 CONTROLLED)

BSET WRITE CYCLE
(iN CONTROLLED)

1------

i----tAVAV

tAVAV - - - - . . ,

A (ADDRESS)

1 + - - - - tAVWH --~I--~I
\ 4 - - - twLSH -+-~

5 (CHIP SELECT)

iN (WRITE ENABLE)

BSET (BIT SET)

BCLR (BIT CLEAR)

D(DATA IN)

Q (DATA OUT)

-----/--

- - - - - - - HIGH·Z - - - - - - -

(ASSERTED)

MATCH

MOTOROLA MEMORY DATA

un

•

MCM62361

CLEAR CYCLE (See Nole 1)
Symbol
Characteristic

62351-18

Standard

Alternate

IRLAV
IRISV
IRlBSV
IRlBCV
IRlDV

teR
ICR
teR
ICR
teR

R Pulse Widlh

IRlRH

IClP

20

Read Selup 10 R low

twHRl

IRS

5

Wrile Hold from R High

IRHWl

twH

0

IRLAX
IRISX
IRlBSX
IRlBCX
IRlDX

0

0

-

R low 10 Inpuls Recognized A
(Clear Cycle lime)
S
BSET
BClR
D

R low 10 Inpuls Don't Care

A

R low 10 MATCH Assert

tRlMX

tex
tex
tex
tex
tex
IMH

R Low 10 Outpul High-Z

IRlQZ

tez

S
BSET
BClR
D

62351-20

Min

Max

Min

-

70

-

-

22

Min

Max

70

-

70

0

-

15

0

15

-

-

5
0

62351-22

Max

62351-25
Min

-

Max

Unit Notes

70

0

-

15

0

15

0

18

ns

15

-

15

-

18

ns

25
5
0

30
5
0
0

-

ns

ns
ns

2

ns

2

ns

3

4

NOTES:
1. The address, BSET, and BClR inpuls are don'I cares during a clear cycle.
2. The clear cycle is initialed althe falling edge ofR. The twHRl and IRHWl paramelers must be salisfied 10 prevenl an undesired configuralion
cycle.
3. "Inputs" for this parameler refers 10 all inputs excepl W.
4. Transilion is measured ±500 mV from steady slate voltage with load of Figure lb. This parameler is sampled and noll00% tested.

CLEAR CYCLE
(FROM READ CYCLE)

(FROM COMPARE OR WRITE CYCLE)

A(ADDRESS)

•

S (CHIP SELECT)

IRLAX
IRLSX

1----

IRLAV ---~

~---

tRLDV - - - - + I

l'i (RESET)

W(WRITE ENABLE)

BSET (BIT SET)

BCLR (BIT CLEAR)

tRLBSX

IRLBCX
IRLDX-+----l~

o(DATA IN)

__....::..::I.=-_-J!
IRLMX
MATCH

MATCH

VALID

I---+/-- tRLOZ
Q (DATA OUT)

) 1 - - - - - HIGH·Z - - - -

- - - - - - - HIGH·Z - - - - - -

MOTOROLA MEMORY DATA
7-88

MCM62361

CONFIGURATION CYCLE (See Notes t and 2)
Symbol
Characteristic

62351-18

Standard

Alternate

Configuration Control Pulse S
Width
R

tSLSH
tRLRH

tsp
tsp

Data Setup to End of
Configuration Cycle

tOVSH
tOVRH
tOVWH

tos
tos
tos

10

-

tOH
tOH
tOH
tcp

0

R High Pulse Width

tSHOX
tRHOX
twHOX
tRHRL

5

Write Setup to R Low
S Setup to End of
Configuration

twLRL
tSLWH
tSLRH

tws
tsws
tscs

R Setup to End of
Configuration

tRLWH

S

R
W

Data Hold from End of
Configuration Cycle

S

R
W

62351-20

62351-22

-

Min
20

10

-

10

-

-

0

-

0

-

5
5
20

tsR

18

-

20

5
0

-

5

-

0

-

5

5
18

-

9

-

-

9

R Setup to SLow
S Setup to Beginning of Write

tRLSL

tess

tSHWL

S High to Output High-Z

tSHOZ

W Low to Output High-Z

twLOZ

twss
tHZ
tHZ

Min
18

Max

Min
20

Max

9
9

-

5
20
20
5
0

-

-

Max

62351-25

Min
25

Max

Unit Notes
ns

12

-

-

0

-

ns

-

5

-

ns

9
9

5
25
25
5
0

-

3

ns

ns
ns

4

ns
ns
ns

3

10

ns

10

ns

5
5

NOTES:
1. A configuration cycle is performed during the overlap of W low, R low, and S low. Address, 001, 002, 003, BSET, and BeLR inputs are
don't cares during configuration cycles.
2. To ensure proper configuration of the device during power up, chip select must be equal to or greater than VIH.
3. A valid configuration can be performed with S asserted prior to R and W low transitions. Be aware, however, that array data may be altered
under this condition.
4. Note that terminating the cycle with R while leaving Wand S asserted may cause array data to be altered.
5. Transition is measured ±SOO mV from steady state voltage with load of Figure lb. This parameter is sampled and not 100% tested.

CONFIGURATION CYCLE
(ARRAY UNPROTECTED)

(ARRAY PROTECTED)

S (CHIP SELECl]

R(RESEl]

twLRL

W(WRITE ENABLE)

D(DATA INjl--i---<

Q(DATAOUT)

)1----

MOTOROLA MEMORY DATA

7-89

HIGH-Z - - -

•

MCM62351

ORDERING INFORMATION
(Order by Full Part Number)
MCM
Motorola Memory Prefix _ _ _ _ _ _ _T......

r 11
62351

X

xx xx

T

Part Number _ _ _ _ _ _ _ _ _ _
.J

--,,,. _. "" ..... --,
Speed (18 = 18 ns, 20 = 20 ns, 22 = 22 ns, 25 = 25 ns)
Package (P = 300 mil Plastic DIP, J = 300 mil SOJ)

Full Part Numbers -

MCM62351 P18
MCM62351J18
MCM62351J18R2

MCM62351 P20
MCM62351J20
MCM62351J20R2

MCM62351 P22
MCM62351J22
MCM62351 J22R2

•

MOTOROLA MEMORY DATA
7-90

MCM62351 P25
MCM62351J25
MCM62351 J25R2

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - - MCM62486
32K X 9 Bit BurstRAMTM
Synchronous Static RAM

TECHNICAL DATA

With Burst Counter and Self-Timed Write
The MCM62486 is a 294,912 bit synchronous static random access memory
designed to provide a burstable, high-performance, secondary cache for the
i486 microprocessor. It is organized as 32,768 words of 9 bits, fabricated with
Motorola's high-performance silicon-gate CMOS technology. The device
integrates input registers, a 2-bit counter, high speed SRAM, and high drive
capability outputs onto a single monolithic circuit for reduced parts count
implementation of cache data RAM applications. Synchronous design allows
precise cycle control with the use of an external clock (K). CMOS circuitry
reduces the overall power consumption of the integrated functions for greater
reliability.
Addresses (AO-A14), data inputs (DO-D8), and all control signals except
output enable (G) are clock (K) controlled through positive-edge-triggered
noninverting registers.
Bursts can be initiated with either address status processor (ADSP) or
address status cache controller (ADSC) input pins. Subsequent burst
addresses can be generated internally by the MCM62486 (burst sequence
im~ates that of the i486) and controlled by the burst address advance (ADII)
input pin. The following pages provide more detailed information on bUrs'!
controls.
Write cycles are internally self-timed and are initiated by the rising
edge of the clock (K) input. This feature eliminates complex off-chip
write pulse generation and provides increased flexlbility for incoming
signals.
The MCM62486 will be available. In a 44-pin .plastic.leaded chip.
carrier (PLCC). Multiple power and ground pins have been utilized 'to
minimize effects induced by output noise, Separate power and ground
pins have been employed for DOO-D08 to allow user-controlled
output levels of 5 volts or 3.3 volts.

FNPACKAGE
44-LEAD PLCC
CASE7n

PIN ASSIGNMENT

2 1 44 43 42 41 40 39

All

38

A12

37

A13

A51 10

36

A14

AS

11

35

VSS

vS~ 12
000 13

34

007

33

006

DOlI 14

32

VSSQ 15
vccd 16

31

VSSO
VCCQ

30

005

22 23 24 25 26 27 28 29

004

4

3

AS

A4

002

• Single 5 V ± 10% Power Supply
• Choice of 5 V or 3.3 V ± 10% Power Supplies for Output
Level Compatibility
• Fast Access limes: 14/19/24 ns Max and Cycle limes: 20/25/30 ns Min
• Internal Input Registers (AddreSS, Data, Control)
• Internally Self-limed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three-State Outputs
• Common Data Inputs and Data Outputs
• High Output Drive Capability: 85 pF per 1/0
• High Board Density PLCC Package
• Fully TTL-Compatible
• Active High and Low Chip Select Inputs for Easy Depth Expansion

BurstRAM is a trademark of Motorola, Inc.
i486 is a trademark of Intel Corp.

MOTOROLA MEMORY DATA
7-91

5

A2

•

9

17 18 19 20 21

PIN NAMES
AD-A 14 ............... Address Inputs
K ............................. Clock
W....................... Write Enable
G .-'-'.,.................. Output Enable
§Q21 ................... Chip Selects
ADV .......... Burst Address Advance
ADSP, ADSC ......... Address Status
DOD-DOS .......... Data InpuVOutput
VCC ............. + 5 V Power Supply
VCCO ..... Output Buffer Power Supply
VSS ........................ Ground
VSSO ........... Output Buffer Ground
All power supply and ground pins must be
connected for proper operation of the device.
VCC 2: VCCO at all times including power up.

•

MCM62486

BLOCK DIAGRAM (See Note)

K ------------~------------1_~

32Kx9

MEMORY
ARRAY
ADSC -----C~
ADSP

---...--c':J

AO-A14 ---+----I~

15

w----a
SO

-------1

Sf - - - - - - - - < 0

WRITE
REGISTER

ENABLE
REGISTER

G

DQO-~ ~---~--------------------------------------------------~~------~

•

NOTE: All registers are positive-edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the
next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of Wand ADSC) is
performed using the new external address. When ADSC is sampled low (and ADSP is sampled high), any ongoing burst
is interrupted and a read or write (dependent on W) is performed using the new external address. Chip selects (SO, Sl)
are sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst
cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high,
the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of
a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE.

BURST SEQUENCE TABLE (See Note)
External Address

Al4-A2

A1

AO

1st Burst Address

Al4-A2

A1

AO

2nd Burst Address

Al4-A2

A1

AO

3rd Burst Address

Al4-A2

A1

AO

NOTE: The burst wraps around to its initial state upon
completion.

MOTOROLA MEMORY DATA
7-92

MCM62486

SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3, and 4)
S

ADSP

ADSC

ADV

W

K

Address Used

Operation

F

L

X

X

X

L-H

NIA

Deselected

F

X

L

X

X

L-H

NlA

Deselected

T

L

X

X

X

L-H

External Address

Read Cycle, Begin Burst

T

H

L

X

L

L-H

External Address

Write Cycle, Begin Burst

T

H

L

X

H

L-H

External Address

Read Cycle, Begin Burst

X

H

H

L

L

L-H

Next Address

Write Cycle, Continue Burst

X

H

H

L

H

L-H

Next Address

Read Cycle, Continue Burst

X

H

H

H

L

L-H

Current Address

Write Cycle, Suspend Burst

L-H
X
H
H
H
H
Current Address
NOTES.
1. X means Don't Care.
2. All inputs except G must meet setup and hold times for the low-to-high transition of clock (K).
3. S represents SO and ST. T implies ST =L and SO =H; F implies ST =H or SO =l.
4. Wait states are inserted by suspending burst.

Read Cycle, Suspend Burst

ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation

G

110 Status

Read

L

Data Out (DOG-DOa)

Read

H

High-Z

Write

X

High-Z - Data In (DOO-DOa)

Deselected

X

High-Z

NOTES:
1. X means Don't Care.
2. For a write operation following a read operation, G must be high before the input
data required setup time and held high through the input data hold time.

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = 0 V)
Rating
Power Supply Voltage
Output Power Supply Voltage

Symbol

Value

Unit

VCC

-O.Sto 7.0

V
V

VCCO

-0.5toVcC

Voltage Relative to VSS

Vin, Vout

- 0.5 to VCC + 0.5

V

Output Current (per 1/0)

lout

±20

mA

Power Dissipation (TA =70·C, VCC =5 V,
tKHKH =20 ns)

PD

1.0

W

Temperature Under Bias

Tbias

-10to+a5

·C

Operating Temperature

TA

o to + 70

·C

Storage Temperature

·C
-55to+ 125
Tsta
NOTE: Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recommended voltages for extended periods of
time could affect device reliability.

MOTOROLA MEMORY DATA
7-93

This device contains circuitry to
protect the inputs against damage
due to high static voitages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated voltages
to this high-impedance circuit.
This CMOS memory circuit has
been deSigned to meetthe dc and ac
specifications shown in the tables,
after thermal equilibrium has been
established.

•

MCM62486

(Vee

DC OPERATING CONDITIONS AND CHARACTERISTICS
V ceQ =5.0 V or 3.3 V ± 10%. TA =0 to + lOoe. Unless Otherwise Noted)

=5.0 V ± 10%.

RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter
Supply Voltage (Operating Voltage Range)
Output Buffer Supply Voltage
(5.0 V TTL Compatible)
(3.3 V 50 n Compatible)

Symbol

Min

Typ

Max

VCC

4.5

5.0

5.5

Unit
V
V

VCCO
4.5
3.0

5.0
3.3

5.5
3.6

Input High Voltage

V,H

2.2

3.0

VCC+ 0.3

V

Input Low Voltage

V,L

-0.5"

0.0

0.8

V

" V,L (min) = -

3.0 V ae (pulse width,; 20 ns)

DC CHARACTERISTICS
Parameter

Symbol

= 0 to VCC)
Output Leakage Current (G, SI = V'H, SO = V'L, Vout = 0 to VCCO)
AC Supply Current (G. SI, = V,H. SO = VIL.
All Inputs = V,L = 0.0 V and VIH ;, 3.0 V, 'out = 0 mA,
Input Leakage Current (All Inputs. Yin

Min

Max

Unit

Ilkg(l)

-

±1.0

I'A

Ilkg(O)

-

± 1.0

!1A

ICCA

-

180

mA

ISBI

-

40

mA

ISB2

-

30

mA

VOL

-

0.4

V

VOH

2.4

-

V

Cycle Time;, tKHKH min)
Standby Current (SI

..

= V,H. SO = VIL. All Inputs = VIL and V,H. Cycle Time;, tKHKH min)

CMOS Standby Current (SI ;, VCC - 0.2 V. SO,; 0.2 V, All Inputs ;, VCC - 0.2 V or,; 0.2 V.
Cycle Time;, tKHKH min)
Output Low Voltage (IOL

= + 8.0 mAl
=- 4.0 mAl

Output High Voltage (lOH

NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible i486 bus cycles.

CAPACITANCE (f = 1.0 MHz. dV = 3.0 V, TA

=25°C. Periodically Sampled Rather Than 100% Tested)

Characteristic

Symbol

TyP

Max

Unit

Input Capacitance (All Pins Except 000-008)

Cin

2

3

pF

Input/Output Capacitance (000-008)

CliO

7

8

pF

MOTOROLA MEMORY DATA
7-94

MCM62486

AC OPERATING CONDITIONS AND CHARACTERISTICS
(V CC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input liming Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. a to 3.0 V
Input RiselFalilime ..................................... 3 ns

Output liming Reference Level ......................... 1.5 V
Output Load . . . . . . . . . . .. See Figure 1A Unless Otherwise Noted

READIWRITE CYCLE TIMING (See Notes 1, 2, and 3)
Symbol
Parameter

Standard

MCM62486-14

MCM62486-19

Alternate

Min

Max

Min

Min

Max

Unit

20

-

25

-

30

-

ns

-

14

-

19

-

24

ns

6

-

7

-

8

ns

Cycle lime

tKHKH

tevc

Clock Access lime

tKHOV

teo

Output Enable to Outpuf Valid

Max

MCM62486-24
Notes

4

'GLOV

toE

Clock High to Output Active

If1
s::

w

m

s::

0

:tJ

-<
0

SO

(81 ="lLl

»~
ADV

G

DATA IN

It~

DATA OUT

~XX~-X~X~}-r-------------------------------------------

BURST READ

-+-

SINGLE WRITE

---I-*'Icc----------

I

BURST WRITE

~c

EXTENDEDBURSTWRIT~

MCM62486

COMBINATION READIWRITE CYCLE

K

ADDRESS

w

DATA IN

DATA OUT

I-- READ--+l-II+--- WRITE - - - -..1-----

BURST READ

APPLICATION EXAMPLE
DATA BUS

r==:>

DATA
ADDRESS BUS
ADDRESS

)1

CLOCK

V15

i486

L

ADDR
ClK

K
CACHE
CONTROL lOGIC

r

~
DATA

/DDR
ADSC

W

MCM62486

ADSP

f

ADS
CONTROL

128K BYTE BURSTABLE, SECONDARY CACHE USING
4 MCM62486FN24s WITH A 33 MHz i486

MOTOROLA MEMORY DATA

7-98

36

~ --

GADV

I

/

-----~

MCM62486

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory

prefiX~

r rt

Part Number - - - - - - - - - - - - '

Full Part Number - MCM62486FN14

_("""~."""~."""~l

' - - - - - - - - - Package (FN = PLCC)
MCM62486FN19

MCM62486FN24

•

MOTOROLA MEMORY DATA
7-99

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62486A
32K X 9 Bit BurstRAMTM
Synchronous Static RAM
With Burst Counter and Self-Timed Write
The MCM62486A is a 294,912 bit synchronous static random access memory
designed to provide a burstable, high-performance, secondary cache for the
i486 microprocessor. It is organized as 32,768 words of 9 bits, fabricated with
FNPACKAGE
44-LEAD PLCC
Motorola's high-performance silicon-gate CMOS technology. The device
CASem
integrates input registers, a 2-bit counter, high speed SRAM, and high drive
capability outputs onto a single monolithic circuit for reduced parts count
implementation of cache data RAM applications. Synchronous design allows
PIN ASSIGNMENT
precise cycle control with the use of an external clock (K). CMOS circuitry
reduces the overall power consumption of the integrated functions for greater
::;:
reliability.
Addresses (Ao-A14), data inputs (Do-D8), and all control signals except
5 4 3 2 1 44 43 4241
A2 7
output enable (G) are clock (K) controlled through positive-edge-triggered
noninverting registers.
A3 8
Bursts can be initiated with either address status processor (ADSP) or
A4
address status cache controller (ADSC) input pins. Subsequent burst
AS 10
addresses can be generated internally by the MCM62486 (burst sequence
A6 11
imitates that of the i486) and controlled by the burst address advance (ADV)
12
input pin. The following pages provide more detailed information on burst
controls.
13
Write cycles are internally self-timed and are initiated by the rising
14
edge of the clock (K) input. This feature eliminates complex off-chip
15
write pulse generation and provides increased flexibility for incoming
16
signals.
002 17 18 19 20 21 22 23 24 25 26 27
The MCM62486A will be available in a 44-pin plastic leaded chip
carrier (PLCC). Multiple power and ground pins have been utilized to
§ ~ ~ I:;: ~ ~ Ie!) Ii! I;;;
minimize effects induced by output noise. Separate power and ground
>
pins have been employed for DOo-D08 to allow user-controlled
output levels of 5 volts or 3.3 volts.

~I~I~I~ '" ~!< ~ ~

C>

::;:

•

•

A11
A12
A13
A14

VSS
007
D06
31

Vssa
Vcca

30

D05

28 29

DQ4

g~

• Single 5 V ± 10% Power Supply
• Choice of 5 V or 3.3 V ± 10% Power Supplies for Output
Level Compatibility
• Fast Access limes: 14/19/24 ns Max and Cycle limes: 20/25/30 ns Min
• Internal Input Registers (Address, Data, Control)
• Internally Self-limed Write Cycle
• ADSP, ADSC, and ADV Burst Control Pins
• Asynchronous Output Enable Controlled Three-State Outputs
• Common Data Inputs and Data Outputs
• High Output Drive Capability: 85 pF per 1/0
• High Board Density PLCC Package
• Fully TTL-Compatible
• Active High and Low Chip Select Inputs for Easy Depth Expansion

BurstRAM is a trademark of Motorola, Inc.
i486 is a trademark of Intel Corp.

MOTOROLA MEMORY DATA
7-100

>

PIN NAMES
Ao-A 14 ....•.......... Address Inputs
K ............................. Clock
Vii ....................... Write Enable
G ..................... Output Enable
§Q.§1 ................... Chip Selects
ADV ........•. Burst Address Advance
ADSP, ADSC ......... Address Status
DQO-DOS .......... Data InpuVOutput
VCC ............. + 5 V Power Supply
VCCQ ..... Output Buffer Power Supply
VSS ........................ Ground
VSSQ ........... Output Buffer Ground
All power supply and ground pins must be
connected for proper operation of the device.
VCC ~ VCCQ at all times including power up.

MCM62486A

BLOCK DIAGRAM (See Note)

INTERNAL
ADDRESS

K

-----------1------------.-4

15

r------,
32Kx9

MEMORY
ARRAY
ADSC ---~~
ADSP --.~':J

Al-AO
AO-A14 --+------I~

A2-AI4

15

w------a
so
Sf

ENABLE
REGISTER

------------1
3:

w

m

3:
0
:lJ

-<
0

SI
(SO='lJH)

»~
ADV

G

DATA OUT

I+--

SINGLE READ

-I-

BURST READ

NOTE: 01 (A2) represents the first output data from the base address A2; 02(A2) represents the next output data in the burst sequence with A2 as the base address.

I

-I

I

I

3!:
3!:

WRITE CYCLES

C')

I

K

ADSP

ADSC

:s::
~

ADDRESS

0

:D

";"

&1

~I
:s::
m
:s::

0

:D

-<

w
SO
(81 =v)U

0

~

>

ADV

G

DATA IN

l~tGHQZ
DATA OUT

-}-

~XX""---\'7X'\TX
+ - BURST READ

-+-

SINGLE WRITE

---1_'1'\_.-----------

BURST WRITE

-\-

EXTENDED BURST WRIT~

MCM62486A

COMBINATION READIWRITE CYCLE

APPLICATION EXAMPLE
DATA BUS

"-

~

DATA
ADDRESS BUS
ADDRESS

y

V

CLOCK

i486

L

ADDR
ClK

K
CACHE
CONTROL lOGIC

15

V V36

~ r-r r-- r-/DDR
ADSC

Vi

DATA

MCM62486

G
ADV

I

ADSP

f

ADS
CONTROL

128K BYTE BURSTABLE, SECONDARY CACHE USING
4 MCM62486FN24s WITH A 33 MHz i486

MOTOROLA MEMORY DATA
7-107

•

MCM62486A

Derating Curves
ICCA vs Cycle Time

ICCAvsVCC

1.10

1.60

,

1.05
1.00

1.20

"

ICCA 095
(Norm) .

ICCA

.........

0.90
0.85

0.40

~

~

~

~

~

80

$

/
./

V

80

5

4

CYCLE TIME (ns)

VCC(V)

KHQV vs Temperature

KHQVvsVCC

1.05

1.00

~

IKHOV 095
(Nann) .

•

,/

0.90

~

1.80

--

.",.. ~

1.80
1.~

IKHOV

V

(Norm)

1.20

\
\

"

1.00
0.80

0.85
-10

10

./

./

0.60

0.20
~

/"

1.00

(Nann) 0.80

--... -

~

0.80
g

/

1.40

20
30
~
50
TEMPERATURE ('C)

80

70

80

Change In Output Rise/Fail Times vs
Output Capacitance

-I--- r--.....

....

5

VCC (V)

KHQV vs Output Capacitance

o.~

1.04

o.~

air. all

~

(nsIV) 0.10

V
.,/

0.00

""

V

V

1.03

1.02

tKHOV
(Nann)

,. V

1.01
1.00

-{l.10

...--- ~

0.99
20

40

60
80 100 120 140 180
OUTPUT CAPACITANCE (pF. lumped)

180

200

20

Derating curves are based on component typical values.

MOTOROLA MEMORY DATA
7-108

40

V

~

, ..,V

V

60
80 100 120 140 180
OUTPUT CAPACITANCE (pF. lumped)

/

180

200

MCM62486A

ORDERING INFORMATION
(Order by Full Part Number)

T_2-,~

Motorola Mem_o_ry_p_re_fi_x_ _M_C_I_M__
Part Number

-

f.

_T_x_x______ Speed (14 = 14 ns, 19 = 19 ns, 24 = 24 ns)

-

Package (FN = PLCC)

Full Part Number - MCM62486AFN14 MCM62486AFN19 MCM62466FN24

•

MOTOROLA MEMORY DATA
7-109

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62940
32K X 9 Bit BurstRAMTM
Synchronous Static RAM
With Burst Counter and Self-Timed Write

..

The MCM62940 is a 294,912 bit synchronous static random access
memory designed to provide a burstable, high-performance, secondary
cache for the MC68040 microprocessor. It is organized as 32,768 words of 9
bits, fabricated using Motorola'S high-performance silicon-gate CMOS
technology. The device integrates input registers, a 2-bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for
reduced parts count implementation of cache data RAM applications.
Synchronous design allows precise cycle control with the use of an external
clock (K). CMOS circu~ry reduces the overall power consumption of the
integrated functions for greater reliability.
A2
Addresses (AO-AI4), data inputs (00-08), and all control signals,
A3
except output enable (<3), are clock (I<) controlled through
A4
positive-edge-triggered non inverting registers.
ASI
Bursts can be in~iated with either transfer start processor (TSP) or
transfer start cache controller (TSC) input pins. Subsequent burst
M
addresses are generated internally by the MCM62940 (burst sequ8;ride "'
Vss
imitates that of the MC68040) and controlled by the burst addreSs '
000
advance (BAA) input pin. The following pages provide more detailed
' , 001, I
information on burst controls.
"
", ", ' Vssq
Write cycles are internally self-~imEld allj:l are inHlated by the 'rismg 'il~e' Vcco
of the clock (I<) input. This featUre e/illlinates complex off.:chip write pulse
generation and provides increased flexibil~y ior'ln,col'iling signall!. : , '
DQ2
The MCM62940 is packaged iii a 44-pin pi8siIC!eaded chip carrter"
(PLCC). Multiple power and ground pins have been 'utilized to '
minimize effects induced by output noise. Separate power and ground
pins have been employed for 000-008 to allow user-controlled
output levels of 5 volts or 3.3 volts.
•
•
•
•
•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Compatibility
Fast Access limes: 14/19/24 ns Max and Cycle Times: 20/25/30 ns Min
Internal Input Registers (Address, Data, Control)
Internally Self-limed Write Cycle
TSP, TSC, and BAA Burst Control Pins
Asynchronous Output Enable Controlled Three-State Outputs
Common Data Inputs and Data Outputs
High Output Drive Capability: 85 pF per I/O
High Board Density PLCC Package
Fully TTL-Compatible
Active High and Low Chip Select Inputs for Easy Depth Expansion

FN PACKAGE
44-LEAD PLCC
CASEm

PIN ASSIGNMENT
;;[

~lil~l~ ~ ~ ~ ~ ~
-=

5 4 3

7
8
9
10

-===
2
44 43
1

•

<:>

;;[

-=

42 41

40 39

38
37
36
35
34
33
32
31

11
12
13
14
15
16

All
A12
A13
A14

Vss
007
DOS

VsSQ
Vcco

30

DOS

17 18 19 20 21 22 23 24 25 26 27 28 29

DQ4

§

~

8

> >

I~

8

>

~

IC!>

Iil I;;;

g >~

PIN NAMES

AO-A14 " " " " " " ' " Address Inputs
K ............................. Clock
W... ,." ......... , .. , ... Write Enable
G ..... .. .. .. .. .. .. .... Output Enable
SO, §T , ......... " .. , .. , Chip Selects
BAA .. ,....... Burst Address Advance
TSP, TSC .. , .... , ...... Transfer Start
DOD-DOB .. ,., .. ,.. Data Input/Output
VCC .... , .... , ... +5VPowerSupply
VCCO ' . . .. Output Buffer Power Supply
VSS ........................ Ground
VSSO ' .. , ...... , Output Buffer Ground
All power supply and ground pins must be
connected for proper operation of the device.
VCC;' VCCO at all times including power up.

BurstRAM is a trademark of Motorola, Inc.

MOTOROLA MEMORY DATA
7-110

MCM62940

BLOCK DIAGRAM (See Note)
BURST LOGIC

BAA------------------------~
K---------.----------~~

02
INTERNAL
ADDRESS
AI'
011-____
""""...

BINARY
COUNTER

15

00

AO'

r-~--+_-----.----~LOAD

01
AI
EXTERNAL
AI4-AO -t-_A_DD_R_ESS
__~

DO

32Kx9
MEMORY
ARRAY

AO
AI4-A2

ADDRESS
REGISTERS

15

WRITE
REGISTER

iii

so

ENABLE
REGISTER

51
G
DQG-DQ8

9

NOTE: All registers are positive-edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next burst.When
TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed using the new external
address. When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W)
Is performed using the next external address. Chip selects (SO, $f) are sampled only when a new base address is loaded. After the first
cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is advanced prior to the
operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wa" state into the burst sequence accesses.
Upon completion of a burst, the address will wrap around to Its initial state. See BURST SEQUENCE GRAPH.

BURST SEQUENCE GRAPH (See Note)

(O'O~
AI', AO' =

t

0,1

'-1,0..,.....)
NOTE: The external two values for Aland AO
provide the starting point for the burst
sequence graph. The burst logic advances
Aland AO as shown above.

MOTOROLA MEMORY DATA

7·111

•

MCM62940

SYNCHRONOUS TRUTH TABLE (See Notes 1 2 3 , and 4)
S

TSP

TSC

BAA

W

K

Address

Operation

F

L

X

X

X

L-H

N/A

Deselected

F

X

L

X

X

L-H

N/A

Deselected

T

L

X

X

X

L-H

External Address

Read Cycle, Begin Burst

T

H

L

X

L

L-H

External Address

Wr~e

T

H

L

X

H

L-H

External Address

Read Cycle, Begin Burst

X

H

H

L

L

L-H

Next Address

Write Cycle, Continue Burst

X

H

H

L

H

L-H

Next Address

Read Cycle, Continue Burst

X

H

H

H

L

L-H

Current Address

Wr~e

X

H

H

H

H

L-H

Current Address

Read Cycle, Suspend Burst

Cycle, Begin Burst

Cycle, Suspend Burst

NOTES:
I. X means Don't Care.
2. All inputs except G must meet setup and hold times for the low-to-high transition of clock (K).
3. S represents SO and 51. T implies SO = Hand $1 = L; F implies SO = Lor $1 = H.
4. Wait states are inserted by suspending burst.

ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

•

Operation

G

I/O Status

Read

L

Data Out (DOO-D08)

Read

H

High-Z

Write

X

High-Z - Data In (DOD-D08)

Deselected

X

High-Z

NOTES:
I. X means Don't Care.
2. For a write operation following a read operation, G must be high before the input data required
setup time and held high throughout the input data hold time.

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = 0 V)
Rating

Symbol

Power Supply Voltage

Value

Unit

Vce

-0.5to 7.0

V

VCCO

-0.5 to VCC

V

Voltage Relative to VSS

Vin, Vout

-0.5 to VCC + 0.5

V

Output Current (per I/O)

lout

±20

rnA

Po

1.0

W

Temperature Under Bias

Tbias

-10to+85

°C

Operating Temperature

TA

Oto+ 70

°C

Tsta

-55to+ 125

°C

Output Power Supply Voltage

Power Dissipation (TA = 70°C, VCC
tKHKH = 20 ns)

Storage Temperature

= 5 V,

NOTE: Permanent device damage may occur IT ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended voltages for extended periods of time could affect
device reliability.

MOTOROLA MEMORY DATA
7-112

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higherthan maximum rated voltages
to this high-impedance circuit.
This CMOS memory circuit has
been designed to meet the dc and ac
specifications shown in the tables,
after thermal equilibrium has been
established.

MCM62940

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = 0 to + ?O°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter
Supply Voltage (Operating Voltage Range)
Output Buffer Supply Voltage
(5.0 V TTL Compatible)
(3.3 V 50 (l Compatible

Symbol

Min

l'fp

Max

Unit

VCC

4.5

5.0

5.5

V

4.5
3.0

5.0
3.3

5.5
3.6

V

VCCO

Input High Voltage

VIH

2.2

3.0

VCC+0.3

V

Input Low Voltage

VIL

-0.5'

0.0

0.8

V

, VIL (min) = - 3.0 V ae (pulse width ,; 20 ns)

DC CHARACTERISnCS
Parameter

Symbol

Input Leakage Current (All Inputs, Vin = 0 to Vcc)

=VIH, SO =VIL, Vout =0 to VCCO)
AC Supply Current (G, Sl =VIH, SO =VIL,
MCM62940-14: tKHKH =20 ns
All Inputs =VIL =0.0 V and VIH " 3.0 V, lout =0 rnA,
MCM62940-t9: tKHKH =25 ns
Cycle lime" tKHKH min)
MCM62940-24: tKHKH =30 ns
Standby Current (Sl =VIH. SO =VIL. All Inputs =VIL and VIH, Cycle lime" tKHKH min)
Output Leakage Current (G, St

CMOS Standby Current (Sl "Vee - 0.2 V. SO,; 0.2 V, All Inputs "Vee - 0.2 V or" 0.2 V.
Cycle Time" tKHKH min)
Output Low Voltage (IOL

Min

-

Ilkg(l)

=+ 8.0 mAl
=- 4.0 mAl

Output High Voltage (10H

-

Ilkg(O)
ICCA

Max

Unit

± t.O

IlA
IlA

±1.0
t80
t75
170

mA

-

40

mA

30

mA

VOL

-

0.4

V

VOH

2.4

-

V

ISBl
ISB2

NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible MC68040 bus
cycles.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance (All Pins Except DQO-DQ8)
Input/Output Capacitance (DOO-D08)

MOTOROLA MEMORY DATA
7-113

Symbol

l'fp

Max

Cin

2

3

pF

CvO

7

8

pF

Unit

•

MCM62940

AC Ol'ERATING CONDITIONS AND CHARACTERISTICS
(VCC

= 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input liming Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. a to 3.0 V
Input Rise/Falilime ..................................... 3 ns

Output liming Reference Level ......................... 1.5 V
Output Load ............ See Figure 1A Unless Otherwise Noted

READIWRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM6294D-14

MCM62940-19

MCM62940-24

Standard

Symbol
Alternata

Min

Min

Min

Cycle lime

tKHKH

teyC

20

-

25

-

30

-

ns

Parameter

Max

Max

Unit

Notes

Clock Access lime

tKHOV

teD

-

14

-

24

ns

tGLOV

toE

-

6

-

19

Output Enable to Output Valid

7

-

8

ns

Clock High to Output Active

tKHOXl

tDCl

8

-

8

-

ns

tKHOX2

tDC2

5

-

5

-

8

Clock High to Output Change

5

-

ns

Output Enable to Output Active

tGLOX

tOLZ

a

-

a

-

a

-

ns

Output Disable to 0 High-Z

'GHOZ

toHZ

-

7

-

9

ns

5

tcz

8

-

8

-

8

-

8

ns

5

tCH

8

-

9

-

11

-

ns

Clock High to 0 High-Z

•

Max

tKHOZ

4

Clock High Pulse Width

tKHKL

Clock Low Pulse Width

tKLKH

tCL

8

-

11

-

ns

Address
Address Status
Data In
Write
Address Advance
Chip Select

tAVKH
'TSVKH
tDVKH
tWVKH
tBAVKH
tSOVKH
tS1VKH

tAS
tss
tDS
tws

3

-

9

Setup limes:

3

-

3

-

ns

6

Hold limes:

Address
Address Status
Data In
Write
Address Advance
Chip Select

tKHAX
tKHTSX
tKHDX
tKHWX
tKHBAX
tKHSOX
tKHS1X

tAH
tSH
tDH
twH

2

-

2

-

2

-

ns

6

NOTES:
1. A read cycle is defined by Whigh or TSP low for the setup and hold times. A write cycle is defined by Wlow and TSP high for the setup and
hold times.
2. All read and write cycle timings are referenced from K or G.
3. G is a don't care when W is sampled low.
4. Maximum access times are guaranteed for all possible MC68040 external bus cycles.
5. Transition is measured ± 500 mV from steady-state voltage wtth load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tKHOZ max is less than IKHQXl min for a given device and from device 10 device.
6. This is a synchronous device. All addresses must meet the spec~ied setup and hold times for ALL rising edges of clock (K) whenever TSP
or TSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K
when the chip Is selected.Chip select must be true (sf low and SO high) at each riSing edge of clock for the device (when TSP or TSC is low)
to remain enabled. limings for Sf and SO are similar.

AC TEST LOADS
+5V

+5V

4800.

4800.

00--<_----+
2550.

00--<_----+
2550.

85pF
(INCLUDING
SCOPE AND JIG)

Figure 1A

5 pF
(INCLUDING
SCOPE AND JIG)

Figure 18

MOTOROLA MEMORY DATA
7-114

MCM62940

READ CYCLE

K

Sf ...,...,.....,..."...,....,."",,1
(SO = VIH) Di.~t:::.L~~L+-~~t:::.L~QL~_--'.~t:::.L~QL~QL~~.D.I.~t:::.L~rY

•
READ ----+oIOlc-------- BURSTREAD------_~I

NOTE: 01 (A2) represents the firstoulputfrom the external address A2; 02(A2) represents the next oulputdata in the burst sequence
with A2 as the base address.

MOTOROLA MEMORY DATA
7-116

MCM62940

WRITECVCLE

K

TSP

TSC

ADDRESS

W

SO

(81 =Vn)

•

BAA

DATA IN

~

SINGLE
WRITE

+

BURST WRITE

NOTE:G=VIH

MOTOROLA MEMORY DATA
7-116

---------.!-I

MCM62940

APPLICATION EXAMPLE

-r.

DATA BUS

"

DATA
ADDRESS BUS
ADDRESS
CLOCK

MC68040

L

ADDR
BCLK

K

.c:: -

r -

KADDR

DATA

G

CACHE
CONTROL
LOGIC

TSC

MCM62940

W
BAA

TSP

I
fS
CONTROL

128K Byte Burstable. Secondary Cache
Using Four MCM62940FN24s with a 33 MHz MC68040

•
Full Part Number -

MCM62940FN14

MCM62940FN19

MOTOROLA MEMORY DATA
7-117

MCM62940FN24

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL
DATA

------------MCM62940A

Product Preview
32K x 9 Bit BurstRAMTM
Synchronous Static RAM
With Burst Counter and Self-Timed Write

..

The,MCM62940A is a 294,912 bit synchronous static random access
memory designed to provide a burstable, high-performance, secondary
cache for the MC68040 microprocessor. It is organized as 32,768 words of 9
bits, fabricated using Motorola's high-performance Silicon-gate CMOS
technology. The device integrates input registers, a 2-bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for
reduced parts count implementation of cache data RAM applications.
Synchronous design allows precise cycle control with the use of an external
clock (K). CMOS circuitry reduces the overall power consumption of the
integrated functions for greater reliability.
Addresses (Ao--A14), data inputs (Do--D8), and all control signals,
except output enable (G), are clock (I<) controlled through
positive-edge-triggered noninverting registers.
Bursts can be initiated with either transfer start processor (fSP) or
transfer start cache controller (TSC) input pins. Subsequent burst
addresses are generated internally by the MCM62940A (burst sequence
imitates that of the MC68040) and controlled by the burst address
advance (BAA) input pin. The following pages provide more detailed
information on burst controls.
Write cycles are internally self-timed and are initiated by the rising edge
of the clock (K) input. This feature eliminates complex off-chip write pulse
generation and provides increased flexibility for incoming signals.
The MCM62940A is packaged in a 44-pin plastic-leaded chip carrier
(PLCC). Multiple power and ground pins have been utilized to
minimize effects induced by output noise. Separate power and ground
pins have been employed for DOO-DQ8 to allow user-controlled
output levels of 5 volts or 3.3 volts.
•
•
•
•
•
•
•
•
•
•
•
•

FNPACKAGE
44-LEAD PLCC
CASEm

PIN ASSIGNMENT

::;:

~lil~l~ ~ ~ ~ ~ ~

A2

5 4 3 2 1 44 43 42 41 40 3S

AS

38

•

7
8
A4[ 9
AS

A6

Vss
DOO
DOl

Vssa
Vcce
0Q2

Single 5 V ± 10% Power Supply
Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Compatibility
Fast Access Times: 14/19/24 ns Max and Cycle Times: 20/25/30 ns Min
Internal Input Registers (Address, Data, Control)
Intern~elf-Timed Write Cycle
TSP, TSC, and BAA Burst Control Pins
Asynchronous Output Enable Controlled Three-State Outputs
Common Data Inputs and Data Outputs
High Output Drive Capability: 85 pF per I/O
High Board Density PLCC Package
Fully TTL-Compatible
Active High and Low Chip Select Inputs for Easy Depth Expansion

10
11
12
13
14
15
16

35

Vss
007
006

17 18 19 20 21 22 23 24 25 26 27 28 29

DQ4

a

g8

13:

8

gj

e.g:»>

IC>

Iil liij ~

Vssa
Vcce
D05

i

>

PIN NAMES
AD--A 14 ............... Address Inputs
K ............................. Clock
Vii ....................... Wr~e Enable
G ..................... Output Enable
SO, Sf .................. Chip Selects
BAA .......... Burst Address Advance
TSP, 'fSC .............. Transfer Start
DQO--OQ8 .......... Data Input/Output
VCC ............. + 5 V Power Supply
VCCQ ....• Output Buffer Power Supply
VSS ........................ Ground
VSSQ .....•..... Output Buffer Ground
All power supply and ground pins must be
connected for proper operation of the device.
VCC;" VCCQ at all times including power up.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA

3
3E

All
A12
A13
A14

34
33
32
31
30

BurstRAM is a trademark of Motorola, Inc.

7-118

<>

::;:

MCM62940A

BLOCK DIAGRAM (See Note)
BURST LOGIC
BAA--------------------------~

02

K--------~----------~~
BINARY
COUNTER

Al'

01

INTERNAL
ADDRESS

!----,r"'7".......
15

QO

AO'

}-~--~----~~--~LOAD

D1
A1
EXTERNAL
A14-AO +.:;:A:;::DD~R::.:ES:::.:S~_I

DO

32Kx 9
MEMORY
ARRAY

AO

A14-A2

ADDRESS
REGISTERS

15

WRITE
REGISTER

w
so
Sf

ENABLE
REGISTER

G
DOO-DQ8

9

NOTE: All registers are positive-edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next burst. When
TSP is sampled low, any ongoing burst is interrupted and a read (independent of Wand TSC) is performed using the new external
address. When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W)
is performed using the next external address. Chip selects (SO, Sf) are sampled only when a new base address is loaded. After the first
cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is advanced prior to the
operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses.
Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE GRAPH.

BURST SEQUENCE GRAPH (See Note)

(o,o~
A1',AO'=

~1'0.J1

NOTE: The external two values for A1 and AO
provide the starting point for the burst
sequence graph. The burst logic advances
A1 and AO as shown above.

MOTOROLA MEMORY DATA
7-119

•

MCM62940A

SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, 3, and 4)
S

TSP

TSC

BAA

W

K

Address

Operation

F

L

X

X

X

L-H

NIA

Deselected

F

X

L

X

X

L-H

NIA

Deselected

T

L

X

X

X

L-H

External Address

Read Cycle, Begin Burst

T

H

L

X

L

L-H

External Address

Write Cycle, Begin Burst

T

H

L

X

H

L-H

External Address

Read Cycle, Begin Burst

X

H

H

,L

L

L-H

Next Address

Write Cycle, Continue Burst
Read Cycle, Continue Burst

X

H

H

L

H

L-H

Next Address

X

H

H

H

L

L-H

Current Address

Write Cycle, Suspend Burst

X

H

H

H

H

L-H

Current Address

Read Cycle, Suspend Burst

NOTES:
1. X means Don't Care.
2. All inputs except G must meet setup and hold times for the low-to-high transition of clock (K).
3. S represents SO and Sf. T implies SO = H and Sf = L; F Implies SO = L or Sf = H.
4. Walt states are inserted by suspending burst.

ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

•

Operation

G

VOStatus

Read

L

Data Out (D~Q8)

Read

H

High-Z

Write

X

High-Z - Data In (000-008)

Deselected

X

High-Z

NOTES:
1. X means Don't Care.
2. For a write operation following a read operation, G must be high before the input data required
setup time and held high throughout the input data hold time.

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = 0 V)
Rating
Power Supply Voltage

Symbol

Value

Unit

VCC

-0.5 to 7.0

V

VCCO

-0.5toVCC

V

Voltage Relative to VSS

Vin, Vout

-0.5 to VCC +0.5

V

Output Current (per 1/0)

lout

±20

mA

Power Dissipation (TA = 70·C, VCC = 5 V,
tKHKH = 20 ns)

Po

1.0

W

Temperalure Under Bias

Tbias

-10to+85

·C

Operating Temperature

TA

Oto + 70

·C

Output Power Supply Voltage

Storage Temperature

·C
-55to+125
TSI9
NOTE: Permanent deVice damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended voltages for extended periods of time could affect
device reliability.

MOTOROLA MEMORY DATA
7-120

This device contains circuitry to protect the Inputs against damage due
to high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid
application of any voltage higher
than maximum rated voltages to this
high-impedance circuit.
This CMOS memory circuit has
been designed to meet the de and ac
specifications shown in the tables,
after thermal equilibrium has been
established.

MCM62940A

DC OPERATING CONDITIONS AND CHARACTERISTICS
± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

(V CC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V

RECOMMENDED OPERATING CONDITIONS (Voltages referenced to Vss = 0 V)
Parameter
Supply Voltage (Operating Voltage Range)
Output Buffer Supply Voltage
(5.0 V TIL Compatible)
(3.3 V 50 n Compatible

Symbol

Min

Typ

Max

Unit

VCC

4.5

5.0

5.5

V

4.5
3.0

5.0
3.3

5.5
3.6

VCCO

V

Input High Voltage

VIH

2.2

3.0

VCC + 0.3

V

Input Low Voltage
" VIL (min) = - 3.0 V ac (pulse Width s 20 ns)

VIL

-0.5"

0.0

0.8

V

DC CHARACTERISTICS
Parameter

Symbol

Min

Max

Unit

±1.0

I'A

40

mA

30

mA

0.4

V

Standby Current (81 =VIH, SO =VIL, All Inputs =VIL and VIH, Cycle TIme ~ tKHKH min)

ISBl

CMOS Standby Current (81 ~ VCC - 0.2 V, SO S 0.2 V, All Inputs ~ VCC - 0.2 V or S 0.2 V,
Cycle Time" tKHKH min)

ISB2

-

Output Low Voltage (IOL =+ 8.0 mAl

VOL

-

Input Leakage Current (Ail Inputs, Yin =0 to Vccl

Ilkg(l)

Output Leakage Current (G, Sl = VIH, SO =VIL, Vout =0 to VCCO)

Ilkg(O)

AC Supply Current (G, Sl =VIH, SO =VIL,
All Inputs =VIL =0 V and VIH ~ 3.0 V, lout =0 mA,
Cycle TIme ~ tKHKH min)

ICCA

MCM62940A-14:tKHKH =20 ns
MCM62940A-19: tKHKH =25 ns
MCM62940A-24: tKHKH =30 ns

± 1.0

I'A

180
175
170

mA

-

2.4
V
Output High Voltage (IOH =- 4.0 mAl
VOH
..
NOTE: Good decoupilng olthe local power supply should always be used. DC charactenstlcs are guaranteed for all possible MC68040 bus cycles .

CAPACITANCE (f =1.0 MHz, dV =3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol

Typ

Max

Unit

Input Capacitance (All Pins Except DOD-D08)

Characteristic

Cin

2

3

pF

Input/Output Capacitance (OOD-D08)

CliO

7

8

pF

MOTOROLA MEMORY DATA
7-121

MCM62940A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, Vcca = 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input TIming Measurement Reference level ............... 1.5 V
Input Pulse levels .................................. 0 to 3.0 V
Input Rise/Fall TIme ..................................... 3 ns

Output TIming Reference level ......................... 1.5 V
Output load . . . . . . . . . . .. See Figure 1A Unless Otherwise Noted

READIWRITE CYCLE TIMING (See Notes 1, 2, and 3)
Symbol
Parameter

MCM62940A-19

MCM62940A-24

AHernate

Min

Max

Min

Max

Min

Max

Unit

Cycle TIme

tKHKH

tCYC

20

-

25

-

30

-

ns

Clock Access'TIme

tKHOV

te~

-

19

-

24

ns

IGlOV

toE

-

14

Output Enable to Output Valid

6

-

7

-

8

ns

Clock High to Output Active

tKHOX1

tOC1

7

-

7

-

7

-

ns

-

5

-

ns

Notes

4

Clock High to Output Change

tKHOX2

tDC2

5

Output Enable to Output Active

tGlOX

toLZ

0

-

5
0

-

0

-

ns

toHZ

-

7

-

8

9

ns

5

tcz

-

8

-

8

-

8

ns

5

teH

8

-

9

-

11

ns

ns

6

ns

6

Output Disable to 0 High-Z

IGHOZ

Clock High to 0 High-Z

•

MCM62940A-14

Standard

tKHOZ

Clock High Pulse Width

tKHKl

Clock low Pulse Width

tKlKH

tel

8

-

9

-

11

Setup TImes:

Address
Address Status
Data In
Write
Address Advance
Chip Select

tAVKH
trSVKH
tDVKH
tWVKH
tBAVKH
tSOVKH
tSWKH

tAS
tss
tDS
tws

3

-

3

-

3

-

Hold TImes:

Address
Address Status
Data In
Write
Address Advance
Chip Select

tKHAX
tKHTSX
tKHDX
tKHWX
IKHBAX
tKHSOX
tKHS1X

tAH
tSH
tOH
twH

2

-

2

-

2

-

ns

NOTES:
1. A read cycle is defined by Whigh or TSP low for the setup and hold times. A write cycle is defined by Wlow and TSP high for the setup and
hold times.
2. All read and write cycle timings are referenced from K or G.
3. G is a don't care when Wis sampled low.
4. Maximum access times are guaranteed for all possible MC68040 external bus cycles.
5. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, IKHOZ max is less than tKHOX1 min for a given device and from device to device.
6. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of clock (K) whenever TSP
or TSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL riSing edges of K
when the chip is selected. Chip select must be true (Sf low and SO high) at each rising edge of clock for the device (when TSP or TSC is low)
to remain enabled. TImings for Sf and SO are similar.

AC TEST LOADS
+5V

+5V

480 g
DQ

DO

255 g

255 g

85pF
gNCLUDING
COPE AND JIG)

: ~ 5pF
gNCLUDING
COPE AND JIG)

~
Figure 18

-=

Figure lA

MOTOROLA MEMORY DATA
7-122

MCM62940A

READ CYCLE

K

ADDRESS 1..jJ,~~~~fI\..-+...J'I"-~~~~:>I

Sf .......,.....,...,....,....,.""'1
(SO • VIH) L..>I.-"-'~""-"'-"t"--t-Lf"'o-"-'~",,-,,'-"-"""'---L-"-''-:''-"''''t>'-''-'''''''''-''-'''->L-''-'''-'''--''-''-''-'''''''':..:.f

•
READ

---~/ooII"~----- BURSTREAD-------c~~1

NOTE: 01 (A2) represents the first outputfrom the external address A2; 02(A2) represents the next output data in the burst sequence
with A2 as the base address.

MOTOROLA MEMORY DATA
7-123

MCM62940A

WRITE CYCLE
K

ADDRESS ~~~L>L;:,c."

iii

•

+

SINGLE
WRITE
NOTE:G=VIH

BURST WRITE

-----------;.~I

APPLICATION EXAMPLE
DATA BUS

"

DATA

.

-V

ADDRESS BUS
ADDRESS
CLOCK

MC68040

L--..

ADDR
BCLK

K

~ f--I-- I--

r

K ADDR

DATA

G

CACHE
CONTROL
LOGIC

_
MCM62940A
TSC

iii
BAA

I
'fS
CONTROL

128K Byte Burstable. Secondary Cache
Using Four MCM62940AFN24S with a 33 MHz MC68040

MOTOROLA MEMORY DATA
7-124

TSP

MCM62940A

Derating Curves
ICCA vs Cycle Time

ICCAvsVCC

1.10

1.60

,

1.05
1.00

1.20

~

ICCA
(Norm) 0.95

0.90
0.85

"

........

1.00
ICCA
(Norm) 0.60

-

I"-- '-

0.40
0.20

20

25

30

35
40
45
CYCLE TIME (ns)

V

50

55

./

V

5

60

VCC(V)

KHQV vs Temperature

KHQVvsVCC

1.05

1.00

.",. ~

IKHOV095
(Norm) .

0.85
-10

1.60

-

~

1.60
1.40
tKHOV
(Norm)

/

.,/

0.90

~

1\

\

1.20

"-- - r---

1.00
0.60
10

20
30
40
50
TEMPERATURE ('C)

/'

i/

/'

0.60

0.80
15

/

1.40

60

70

60

r----

5
VCC(V)

Change In Output Rlsa/Fall Times vs
Output Capacitance

KHQV VB Output Capacitance

0.30

1.04

0.20
Alr,AI!

..".

(nsN) 0.10

,,/
0.00

'/

/'

V

1.03
1.02
tKHOV
(Norm)

~

.". ~

/

1.01
1.00
~

0.99

-11.10
20

40

60
60 100 120 140 160
OUTPUT CAPACITANCE (pF, lumped)

160

20

200

40

"",.. V
60

60

l/
100

V

I'

120

140

160

OUTPUT CAPACITANCE (pF, lumped)

Derating curves are based on component typical values.

MOTOROLA MEMORY DATA
7-125

v

180

200

•

MCM62940A

Full Part Number -

MCM62940AFN14 MCM62940AFN19 MCM62940AFN24

•

MOTOROLA MEMORY DATA
7-126

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62950

32K X 9 Bit Synchronous
Static RAM
The MCM62950 is a 294,9j 2 bit synchronous static random access
memory organized as 32,768 words of 9 bits, fabricated using
Motorola's high-performance silicon-gate CMOS technology. The
device integrates input registers, high-speed SRAM, and high drive
capability outputs onto a single monolithic circuit for reduced parts
count implementation of cache data RAM applications. Synchronous
design allows precise cycle control with the use of an external clock
(K). Asynchronous controls consist of asynchronous write enable
(AW) and output enable (G). CMOS circuitry reduces the overall
power consumption of the integrated functions for g. eater reliability.
Addresses (AD-AI4) and control signals, except output enable (G)
and asynchronous write enable (AW), are sampled through
positive-edge-triggered non inverting registers. Data outputs are
asynchronously controlled by G.
Write cycles are differentiated from read cycles by the state of the
synchronous write enable pin (SW) at the rising edge of K. Write
cycles are completed only if AW is asserted within the specified setup'
time to the following rising edge of K. Write cycles may be aborted by .
negating the AW signal prior to the low-going edge of K. Oata for the
write may be delayed until the latter half of the write cYQle.
The MCM62950 is packaged in a 44-pin plastiC-I9a\lliid chip
carrier (PLCC). Multiple power and ground pins have been utilized
to minimize effects induced by OutpUt noise. Separate 'Power and
ground pins have been employed ·for DOD-DOS 10' allOw
user-controlled output levels of 5 volts or 3.3 \Il)1ts;
•
•
•
•
•
•
•
•
•
•
•

FN PACKAGE
44-lEAD PlCC
CASE 777
PIN ASSIGNMENT

6

A2
A3

5 4 3

2 1 44 43 4241 40

•

39
38

All
A12

37

A13

A5

10

36

A14

A6

If

VSs

12

35
34

Vss
007

000

13

33

D06

001

14

32

VSSO

31

VCCO
DOS

A4

", VSSO

:15 .

.VCcQ 16
DQ2,

Single 5 V ± 10% Power Supply
Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Cornpatibility
Fast Access Times: 20/25 ns Max and Cycle Times: 20/25 ns Min
Internal Input Registers (Address, Control)
Late Write Abort Feature
Output Enable Controlled Three-State Outputs
Common Data Inputs and Data Outputs
High Output Drive Capability: 85 pF per 1/0
High Board Density PLCC Package
Fully TTL-Compatible
Active High and Low Chip Select Inputs for Easy Depth Expansion

30

17 18 19 20 21 22 23 24 25 26 27
28 29

004

PIN NAMES
AD-A 14 ............... Address Inputs
K ............................. Clock
SW ............... Synchronous Write
AW .............. Asynchronous Write
G ..................... Output Enable
SO, Sf .................. Chip Selects
DQD-DQ8 .......... Data Input/Output
VCC ............. + 5 V Power Supply
VCCQ ..... Output Buffer Power Supply
VSS ........................ Ground
VSSQ ........... Output Buffer Ground
All power supply and ground pins must be
connected for proper operation of the device.
VCC " VCCQ at all times including power up.

MOTOROLA MEMORY DATA

7-1Zl

•

MCM62950

BLOCK DIAGRAM

K--------1---,
15
AO-A14 - -....~

32Kx9
MEMORY ARRAY

5W---I~

~----~======~_L----~
so
Sf
G------------------------------~
D~~~--------------~~----------------------------~~------~

SYNCHRONOUS TRUTH TABLE (See Notes I, 2, 3, and 4)

..

S

SW

AW

G

K

Operation

I/OSlalus

F

X

X

X

L-H

Deselected

High-Z

T

L

X

X

L-H

Write

High-Z

(T)

(L)

L

X

L

Write

Data-In

(T)

(L)

H

X

L

Aborted Write (No Action)

High-Z

T

H

X

-

L-H

Read Initiated

-

(T)

(H)

X

H

X

Read

High-Z

(T)

(H)

X

L

X

Read

Data Out

NOTES.
1. X means Don't Care.
2. SO, Sf, and Wmust meet setup and hold times for the low-to-high transition of clock (K).
3. 5 represents SO and 51. T implies Sf = L and SO = H; F implies Sf = H or SO = L.
4. W= (L) implies W= L for the last clock transition from low to high. Similarly for 5 = (T).

MOTOROLA MEMORY DATA
7-128

MCM62960

-

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to Vss - 0 V)
Rating
Power Supply Voltage
Output Power Supply Voltage

Symbol

Value

Unit

VCC

-0.5to 7.0

V
V

VCCO

-0.5toVCC

Voltage Relative to VSS

Yin, Vout

-0.5to VCC + 0.5

V

Output Current (per 1/0)

lout

±20

rnA

PD

1.0

W

Power Dissipation (TA = 70°C, VCC
tKHKH = 20 ns)

= 5 V,

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid
application of any voltage higher
than maximum rated voltages to this
high-impedance circuit.

This CMOS memory circuit has
been designed to meet the dc and ac
specifications shown in the tables,
after thermal equilibrium has been
Storage Temperature
-55to+125
°C
Tsta
NOTE: Permanent deVice damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. established.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended voltages for extended periods of time could affect
device reliability.
Temperature Under Bias

Tbias

-10to+85

°c

Operating Temperature

TA

o to + 70

°C

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC

= VCCQ = 5.0 V ± 10%, T A = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter
Supply Voltage (Operating Voltage Range)
Output Buffer Supply Voltage
(5.0 V TTL Compatible)
(3.3 V 50 Cl Compatible)

Symbol

Min

Typ

Max

Unit

VCC

4.5

5.0

5.5

V

4.5
3.0

5.0
3.3

5.5
3.6

V

VCCO

Input High Voltage

VIH

2.2

3.0

VCc+0.3

V

.

VIL

-OS

0.0

0.8

V

Input Low Voltage
VIL (min) = - 3.0 Vac (pulse Width ~ 20 ns)

DC CHARACTERISTICS
Parameter

Symbol

= 0 to VCC)
Output Leakage Current (G, SI = VIH, SO = VIL, Vout = 0 to VCCO)
AC Supply Current (G, SO = VIH, SI = VIL, All Inputs = VIL = 0.0 V and VIH ~ 3.0 V, lout = 0
rnA, Cycle Time ~ tKHKH min)
MCM62950-20: tKHKH = 20 ns
MCM62950-25: tKHKH = 25 ns

Ilkg(l)

Input Leakage Current (All Inputs, Yin

Min

Max

Unit

-

± 1.0

I1A

Ilkg(O)
ICCA

-

± 1.0

I1A
rnA

-

195
185

-

40

rnA

ISB2

30

rnA

Output Low Voltage (lOL = + 8.0 rnA)

VOL

0.1

0.4

V

Output High Voltage (IOH - - 4.0 rnA)

VOH

2.4

-

V

Unit

Standby Current (SI

= VIH, SO = VIL, All Inputs = VIL and VIH)

ISBI

CMOS Standby Current (SI ~ VCC - 0.2 V, SO ~ 0.2 V, All Inputs ;, VCC - 0.2 V or ~ 0.2 V,
Cycle Time ~ tKHKH min)

NOTE: Good decouphng of the local power supply should always be used.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T A = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol

Typ

Max

Input Capacitance (All Pins Except DOO-D08)

Cin

2

3

pF

Input/Output Capacitance (DOo-D08)

CUO

7

8

pF

Characteristic

MOTOROLA MEMORY DATA
7-129

MCM62950

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC '" VCCQ '" 5.0 V ± 10%, TA '" 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall Time ..................................... 3 ns

Output Timing Reference Level .................. 1.5 V
Output Load ..... See Figure 1A Unless Otherwise Noted

REAOIWRITE CYCLE TIMING (See Notes 1, 2 and 3)

Parameter

•

MCM62950-20

MCM6295D-25

Min

Min

Symbol

Clock Control:
Cycle Time
Clock High Pulse Width
Clock Low Pulse Width

tKHKH
tKHKL
tKLKH

Read Access Times:
Clock Access Time
Output Enable to Output Valid

tKHQV
tGLQV

Max

Max

Unit

Noles

ns

Aborted Write Cycles:
Clock Low to Asynchronous Write High
Clock High to Asynchronous Write Invalid

tKLAWH
tKHAWX

Write Cycles:
Asynchronous Write Low to Clock High
Clock High to Asynchronous Write Invalid
Data-In Valid to Clock High (Transparent Data)
Clock High to Data Invalid (Transparent Data)
Output Buffer Control:
Clock High to Output Low-Z aiter Write
Clock High to Output Change
Output Enable to Output Active
Output Disable to Q High-Z
Clock High to Q High-Z

20
8
8

-

-

25
11
11

-

ns

-

-

20
8

-

25
9

-

0

-

0

2

-

tAWLKH
tKHAWX
tDVKH
tKHDX

6

-

6

-

2

tKHQXl
tKHQX2
IGLQX
tGHQZ
tKHQZ

7

-

7

8
8

-

2

6
2

5
0

-

ns

2

-

6

-

2

-

-

5
0

ns

ns

-

9
8

4
4

Register Setup Times for:

Address
Synchronous Write
Chip Select

tAVKH
tWVKH
tSOVKH
tStVKH

3

-

3

-

ns

5

Register Hold Times for:

Address
Synchronous Write
Chip Select

tKHAX
tKHWX
tKHSOX
tKHS1X

2

-

2

-

ns

5

NOTES:
1. A read cycle is defined by SW high for the setup and hold times. A write cycle is defined by SW low for the setup and hold times.
2. All read and write cycle timings are referenced from K or G.
3. G is a don't care when SW is sampled low.
4. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tGHQZ max is less than IGLQX min for a given device and from device to device.
5. This is a synchronous device. All address inputs must meet the specified setup and hold times with stable logic levels for ALL rising
edges of clock (K) when the device is selected. All synchronous inputs must meetthe specified setup and hold times with stable logic levels
for ALL rising edges of clock (K) when the device is selected. Timings for Sf and SO are similar.

AC TEST LOADS
+5V

+5V

480

480

Q

DO
255

Q

Q

DO
255

==85~F
~ LUDING

Q

OPE AND JIG)

-==

= 5pF
gNCLUDING
COPE AND JIG)
-'-

MOTOROLA MEMORY DATA
1-130

MCM62950

READ CYCLE

•

READ-WRITE-READ CYCLE

READ

WRITE

READ

MOTOROLA MEMORY DATA
7-131

ABORTED
WRITE

MCM62960

Full Part Number - MCM62950FN20

MCM62950FN25

•

MOTOROLA MEMORY DATA
7-132

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62950A

Product Preview
32K x 9 Bit Synchronous
Static RAM
The MCM62950A is a 294,912 bit synchronous static random
access memory organized as 32,768 words of 9 bits, fabricated using
Motorola's high-performance silicon-gate CMOS technology. The
device integrates input registers, high-speed SRAM, and high drive
capability outputs onto a single monolithic circuit for reduced parts
count implementation of cache data RAM applications. Synchronous
design allows precise cycle control with the use of an external clock
(K). Asynchronous controls consist of asynchronous write enable
(AW) and output enable (G). CMOS circuitry reduces the overall
power consumption of the integrated functions for greater reliability.
Addresses (AO-A14) and control signals, except output enable (G)
and asynchronous write enable (AW), are sampled through
positive-edge-triggered noninverting registers. Data outputs are
asynchronously controlled by G.
Write cycles are differentiated from read cycles by the state of the
synchronous write enable pin (SW) at the rising edge of K. Write
cycles are completed only if AW is asserted within the specified setup
time to the following rising edge of K. Write cycles may be aborted by
negating the AW signal prior to the low going edge of K. Data for the
write may be delayed until the latter half of the write cycle.
The MCM62950A is packaged in a 44-pin plastic-leaded chip
carrier (PLCC). Multiple power and ground pins have been utilized
to minimize effects induced by output noise. Separate power and
ground pins have been employed for DOO-D08 to allow
user-controlled output levels of 5 volts or 3.3 volts.
•
•
•
•
•
•
•
•
•
•
•

FN PACKAGE
44·LEAD PLCC
CASEm

PIN ASSIGNMENT

6

k2.

5 4 3

2 1 44

•

A3

43 42 41 40 39

A11

38

A12

37

A13

A4
A5

10

36

A14

A6

11

VSS
DQO

12
13

35
34

VSS
DQ7

33

DQ6

DQ1

14

32

VSSQ

VSSQ

15

VCCQ

16

31
30

VCCQ
DQ5

DQ2

Single 5 V ± 10% Power Supply
Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Compatibility
Fast Access Times: 15/20/25 ns Max and Cycle Times: 15/20/25 ns Min
Internal Input Registers (Address, Control)
Late Write Abort Feature
Output Enable Controlled Three·State Outputs
Common Data Inputs and Data Outputs
High Output Drive Capability: 85 pF per 1/0
High Board Density PLCC Package
Fully TIL Compatible
Active High and Low Chip Select Inputs for Easy Depth Expansion

1718 19 20 21 22 23 24 25 26 27 28 29

Q
......

~ I~ I~

g

u~»

>

DQ4

~ I~ ~ 1Ci) 0
g
oC/)
>

PIN NAMES
AD-A 14 ............... Address Inputs
K ............................. Clock
SW ............... Synchronous Write
AW .............. Asynchronous Write
G ..................... Output Enable
SO, Sf .................. Chip Selects
DQO-DQ8 .......... Data InpuVOutput
VCC ............. + 5 V P9wer Supply
VCCQ ..... Output Buffer Power Supply
VSS ........................ Ground
VSSQ ........... Output Buffer Ground
All power supply and ground pins must be
connected for proper operation of the device.
VCC ? VCCQ at all times including power up.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
7-133

•

MCM62950A

BLOCK DIAGRAM
K----------~------.
15

AG-A14 _ _....

32Kx9
MEMORY ARRAY

~

9

sw ----....~

~----~======~~----~
so
51

13------------------------'

..

D~~~-------~~---------------~

~----~

SYNCHRONOUS TRUTH TABLE (See Notes 1 2, 3, and 4)

•

s

SW

AW

G

K

Operation

1/0 Status

F

X

X

X

L-H

Deselected

High-Z

T

L

X

X

L-H

Write

High-Z

(T)

(L)

L

X

L

Write

Data-In

(T)

. (L)

H

X

L

Aborted Write (No Action)

Hlgh-Z

T

H

X

-

L-H

Read Initiated

-

(T)

(H)

X

H

X

Read

High-Z

(T)
(H)
X
X
Read
L
NOTES.
1. X means Don~ Care.
2. SO, Sf, and Wmust meet setup and hold times for the low-ta-high trans~ion of clock (I<).
3. S represents SO and S1. T Implies Sf ~ L and SO s H; F Implies Sf = H or SO = L.
4. W= (L) implies W= L for the last clock transition from low to high. Similarly for S = (T).

MOTOROLA MEMORY DATA

7-134

Data Out

MCM62950A

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to Vss
Rating

0 V)

Value

Unit

VCC

-0.5to 7.0

V
V

Power Supply Voltage
Output Power Supply Voltage

~

Symbol

VCCO

-0.5toVCC

Voltage Relative to VSS

Yin, Vout

- 0.5 to VCC + 0.5

V

Output Current (per I/O)

lout

±20

rnA

Power Dissipation (TA ~ 70°C, VCC ~ 5 V,
tKHKH ~ 15 ns)

PD

1.0

W

Temperature Under Bias

Tbias

-10to+85

°c

Operating Temperature

TA

o to + 70

°c

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid
application of any voltage higher
than maximum rated vo~ages to this
high-impedance circuit.
This CMOS memory circuit has
been designed to meet the dc and ac
specifications shown in the tables,
after thermal equilibrium has been

Storage Temperature
-55to+125
°c
Tsta
NOTE. Permanent device damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded. established.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended voltages for extended periods of time could affect
device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC

=Vcca =5.0 V ± 10%, TA =0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS ~ 0 V)
Parameter

Symbol

Min

Typ

Max

Unit

VCC

4.5

5.0

5.5

V

4.5
3.0

5.0
3.3

5.5
3.6

Supply Voltage (Operating Voltage Range)
Output Buffer Supply Voltage
(5.0 V TTL Compatible)
(3.3 V 50 (l Compatible)

V

VCCO

Input High Voltage

VIH

2.2

3.0

VCC+ 0.3

V

Input Low Voltage

VIL

-0.5"

0.0

0.8

V

" VIL (min) - - 3.0 Vac (pulse width,,; 20 ns)

DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Yin ~ 0 to VCC)
Output Leakage Current (G, S1

= VIH, SO ~ VIL, Vout ~ a to VCCO)

AC Supply Current (G, SO ~ VIH, S1 ~ VIL,
All Inputs = VIL = 0.0 V and VIH;' 3.0 V, lout
Cycle Time;, tKHKH min)

= 0 rnA,

Standby Current (S1 ~ VIH, SO ~ VIL, All Inputs

= VIL and VI H)

tKHKH

= 15 ns

Symbol

Min

Max

Unit

Ilkg(l)

-

±1.0

Ilkg(O)

-

± 1.0

I!A
I!A

ICCA

-

195

rnA

-

40

rnA

30

rnA

ISB1

CMOS Standby Current (S1 ;, VCC - 0.2 V, SO,,; 0.2 V, All Inputs ;, VCC - 0.2 V or" 0.2 V,
Cycle Time;, tKHKH min)

ISB2

Output Low Voltage (lOL ~ + 8.0 rnA)

VOL

0.1

0.4

V

VOH

2.4

-

V

Output High Voltage (IOH

= - 4.0 rnA)

NOTE: Good dacouphng of the local power supply should always be used.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Input Capacitance (All Pins Except DOD-D08)
Input/Output Capacitance (DOO-DOB)

MOTOROLA MEMORY DATA
7-136

Symbol

Typ

Max

Unit

Cin

2

3

pF

CI/O

7

8

pF

•

MCM62950A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC

= Vcca = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input liming Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Falilime ..................................... 3 ns

Outpulliming Reference Level .................. 1.5 V
Output Load ..... See Figure 1A Unless Otherwise Noted

READIWRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM62950A-1
5
Parameter

•

Symbol

Clock Control:
Cycle lime
Clock High Pulse Width
Clock Low Pulse Width

tKHKH
tKHKL
tKLKH

Read Access limes:
Clock Access lime
Output Enable to Output Valid

tKHOV
tGLOV

Aborted Write Cycles:
Clock Low to Asynchronous Write High
Clock High to Asynchronous Write Invalid

tKLAWH
tKHAWX

Write Cycles:
Asynchronous Write Low to Clock High
Clock High to Asynchronous Write Invalid
Data-In Valid to Clock High (Transparent Data)
Clock High to Data Invalid (Transparent Data)
Output Buller Control:
Clock High to Output Low-Z after Write
Clock High to Output Change
Output Enable to Output Active
Output Disable to 0 High-Z
Clock High to 0 High-Z

Min
15

6
6

Max

Max

Min

Max

20
8
8

-

25
11
11

-

15

6

-

20
8

-

25
9

0

-

0

-

0

-

6
2
6
2

-

6
2
6
2

-

-

8
5
0

-

8
5
0

-

tAWLKH
tKHAWX
tDVKH
tKHDX

6
2
6
2

tKHOXl
tKHOX2
tGLOX
'GHOZ
IKHOZ

8
5
0

7
8

Register Setup limes for:

Address
Synchronous Write
Chip Select

tAVKH
twvKH
tSOVKH
tS1VKH

3

-

Register Hold limes for:

Address
Synchronous Write
Chip Select

tKHAX
tKHWX
tKHSOX
tKHS1X

2

-

-

-

2

ns

ns

8
8

-

3

-

3

-

ns

5

2

-

2

-

ns

5

4
4

9
8

NOTES:
1. A read cycle is defined by SW high for the setup and hold times. A write cycle is defined by SW low for the setup and hold times.
2. All read and write cycle timings are referenced from K or G.
3. G is a don't care when SW is sampled low.
4. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At
any given voltage and temperature, 'GHOZ max is less than 'GLOX min for a given device and from device to device.
5. This is a synchronous device. All address inputs must meet the specified setup and hold times with stable logic levels for ALL rising
edges of clock (K) when the device is selected. All synchronous inputs must meet the specified setup and hold times with stable logic
levels for ALL rising edges of clock (K) when the device is selected. limlngs for Sf and SO are similar.

AC TEST LOADS
+5V

+5V

480(1

00----_---...
255 (1

DO - - - - _ - - -...

255(1

85pF
(INCLUDING
SCOPE AND JIG)

MOTOROLA MEMORY DATA

7-.136

Notes

ns

ns

-

-

Unit

ns

2

2

-

Min

MCM62950A·2
5

-

-

MCM62950A·2
0

MCM62950A

READ CYCLE

•

READ·WRITE·READ CYCLE

READ

WRITE

READ

MOTOROLA MEMORY DATA
7-137

ABORTED
WRITE

MCM62950A

Derating Curves
fCCA vs Cycle Time

ICCAvsVCC

1.10

1,60

1,05

1.40

\

1,00

1.20

" ----

ICCA 095
(Norm) ,

1.00
ICCA
(Norm) 0,80

I" ~

0,90

0,85

0,40
0,20

20

25

30

35

40

45

50

55

/'
./
5

60

CYCLE TIME (ns)

VCC(V)

KHQV vs Temperature

KHQVvsVCC

1,05

1.00

V

lKHOV 095
(Norm) ,

•

0,85
-10

-

,...- ~

1,80
1.60

1,40
tKHOV
(Norm)

V

/

0,80

.,..

"

1,20

\
\

"

1.00
0,80
10

20

30

40

./

./

0,80

0,80
15

V

V

50

60

70

80

TEMPERATURE ('C)

Change in Output Rise/Fall Times vs
Output Capacitance

- -------5

VCC (V)

KHQV vs Output Capacitance

0,30

1,04

0,20
.l.tr,.l.tf
(ns/V) 0,10

~

.... V

0,00

40

60

V

1,03
1.02
tKHOV
(Norm)

V

1,01
1.00

.

-0,10
20

/

V

V

.... ,,/'
80

100

120

/

0,99
140

160

180

200

20

-~

OUTPUT CAPACITANCE (pF, lumped)

40

~
80

.",
80

V

100

I

V'

120

140

160

OUTPUT CAPACITANCE (pF, lumped)

Deraling curves are based on component typical values,

MOTOROLA MEMORY DATA
7-138

/

180

200

MCM62950A

Full Part Number - MCM62950AFN15

MCM62950AFN20

MCM62950AFN25

•

MOTOROLA MEMORY DATA
7-139

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62960
32K X 9 Bit Synchronous
Static RAM
The MCM62960 is a 294,912 bH synchronous static random access
memory designed to provide a high-performance, cache for the SPARCTM
Family of microprocessors. It is organized as 32,768 words of 9 bits,
fabricated using Motorola's high-performance silicon-gate CMOS
technology. The device integrates input registers, high-speed SRAM, and
high drive capabilHy outputs onto a single monolHhic circuH for reduced
parts count implementation of cache data RAM applications.
Synchronous design allows precise cycle control wHh the use of an
external clock (K). CMOS circuHry reduces the overall power consumption
of the integrated functions for greater reliabilHy.
Output enable (~) is an asynchronous control input. Addresses
(Ao-AI4) and chip select inputs (SO, 'ST) are sampled through
positive-edge-triggered, non inverting registers on the rising edge of the
clock input (K). Write enable (R) and data-in are sampled on the following
edge of K through negative-edge-triggered, non inverting registers.
The MCM62960 is packaged in a 44-pin plastic leaded chip carrier
(PLCC). Multiple power and ground pins have been utilized to
minimize effects induced by output noise. Separate power and ground
pins have baan employed for OOO-DQ8to allow user-controlled
output lavels of 5 volts or 3.3 volts.

•

•
•
•
•
•
•
•
•
•
•
•

FNPACKAGE
44-lEAD PLCC
CASEro

PIN ASSIGNMENT

cSl~~~~~~~~~
.....
A2
A3

7
8

6 5 4 3 2 1 44 43 42 41
40 39
•
38

A4

9

3J

AS

19..

:IE

A14

M '11

35

VSS

VSS1 'Ill,

,000'
DOl

A11
A12
A13

34

007

13

33

DQ6

'14 "

32

VSSQ

Vsso

Single 5 V ± 10% Power Supply
: .', ,
" ','
,
15
31 Vcco
Choice of 5 V or 3.3 V ± 100/0 Power Supplla& for Output LIWtII COntpatiI/ufty-Vcco ,16
30 DQ5
Fast Access Times: 17120124118 Max ard Cycle llr11lJS( 2Of25I3(j ns MIn".-· 'Dp2 17 18 19 20 21 22 23 24 25 26 27 28 21 004
Internal Input Registers (Address, Control,.Data)
~ ~ I~ 8 ~ Ie> ~ I;;;
~
Internally Self-Timed WrHe C y c l e '
Q
>
>
>
Output Enable Controlled Three-State oUtputs
Common Data Inputs and Data Outputs
PIN NAMES
High Output Drive Capability: 85 pF per I/O
AO-A 14 . , ... ,. .... ,. . Address Inputs
High Board DensHy PLCC Package
K ..... ,. .. ,. ............... Clock
Fully TTL Compatible
Vi ... ,. .... ,. .. ,..,.. Wrila Enable
Active High and Low Chip Select Inputs for Easy Depth Expansion
~ ,. ,. ,. ..... , ..... ,. Output Enable
SO. S1 ,. ........... ,.. Chip Selects
DQO-OQ8 . . . . . . . .. Data InputJOutput
VCC ............ +5 V Power Supply
Vcca .... Output Buffer Power Supply
Vss .. ,. . ,. ,. ............ ,. Ground
Vssa .,..,,. ..... ,.. Output Ground
NC ...... ,. ..... ,. . .. No Connection

a

8

All power supply and ground pins must be
conneclad for proper operation of the device.

VCC ~ Vcca at all times including power up.
No Connection pins should be left open.
SPARC is a Irademark of Sun Corp,

MOTOROLA MEMORY DATA
7-140 '

MCM62960

BLOCK DIAGRAM
K ______________~----_,

15

32Kx9

AO-A14 - - - -......-t

MEMORY AARAY

W------+I
9

so
Sl

~------------------+---+q-~

1---------11---1

•

TRUTH TABLE (Saa Notas 1 2, 3, and 4)
S

W

~

InputlOutput

Operation

F

X

X

High-Z

Deselacl8d

T

H

L

Data Out

Read Cycle

T

H

H

High-Z

Read Cycle

H
WriteDala In
WriteCycJe
T
L
NOTES.
1. X means Don't Care.
2. All addrassandchip selactlnputs mustmaetsatupand hold times lor ALL Iow-to-high transitions olclock
(K). Winput must meat setup and hold times lor ALL high-to-Iow lransitions 01 clock (K).
3. S represents SO and
T implies
L and SO = H; F imp6es !if = H or SO = L
4. During a write cycle, ~ must be high before Ihe input data required setup time and held high Ihroughoul
the data hold time.

m-.

m- -

MOTOROLA MEMORY DATA
7-141

MCM62960

ABSOLUTE MAXIMUM RATINGS (Vokages referenced to VSS = 0 V)
Symbol

Rating
Power Supply Voltage

Value

Unit

VCC

-0.510 7.0

V

VCCQ

-0.5toVCC

V

Voltage Retative 10 Vss

Yin. Vout

- 0.5 10 VCC + 0.5

V

Output Current (per VOl

lout

±2O

mA

Power DISSipation (TA =70"0. VCC =5 V.
tKHKH = 20 ns)

Po

1.0

W

Output·Power Supply Voltage

This devioe contains circuitry 10 proteet the inputs against damage due
to high static wltages or electric
fields;however. ills advised that normal preoeutions be taken to awid
application of any wltage higher
·than maximum rated wltages 10 this
high-impedanoe circuit.
This CMOS memory circuit has
been designed to meet the dcand ac

Temperature Under Bias

Tbias

Operating Temperature
Storage Temperature

-1010+85

°c

TA

010+70

°c

Tstg

-5510+125

°c

specifications shown in the tables.
after thermal equilibrium has been
established.

NOTE: Permanent d9YIoe damage may occur HABSOLUTE MAXIMUM RATINGS are exoeeded.
Functional operation should be restricted 10 RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended wltages for extended periods of time could affect
device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC

=Vcca =5.0 V ± 10%. TA =0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (Vokages referenced to VSS - 0 V)
Parameter
Supply Voltage (Operating Voltage Range)

..

Output Buller Supply Voltage
(5.0 V TTL Compatible)
(3.3 V 50 g Compatible)

Symbol

Min

Typ

Max

Unit

VCC

4.5

5.0

5.5

V

4.5
3.0

5.0
3.3

5.5
3.6

V

Vcca

Input High Voltage

VIH

2.2

3.0

VCC+0.3

V

Input Low Voltage

VIL

-0.5"

0.0

0.8

V

" VIL (min) = - 3.0 Vac (pulse width ,;; 20 ns)

DC CHARACTERISTICS
Parameter

Symbol

Input Leakage Current (All Inputs. Yin =0 to Vce)

Ilkg(l)

Output Leakage Current (~. 51

Ilkg(O)

=VIH. SO =VIL. Vout =0 to Vcca)
AC Supply Current (~. SO = VIH. 51 =VIL.
MCM62960-17: tKHKH = 20 ns
MCM62960-20: tKHKH =25 ns
All Inputs =VIL - 0.0 V and VIH ~ 3.0 V. lout =0 mAo

ICCA

Min

-

Max

Unit

±1.0

IIA

±1.0

IIA

180
175

mA

Cycle Time ~ tKHKH min)

-

40

mA

30

rnA

VOL

-

0.4

V

VOH

2.4

-

V

Standby Current (m- = VIH. SO =VIL. All Inputs =VIL and VIH. Cycle Time ~ tKHKH min)

ISBl

CMOS Standby Current (m- ~ VCC - 0.2 V. SO ,;; 0.2 V. All Inputs ~ VCC - 0.2 V or';; 0.2 V.
Cycle Time ~ tKHKH min)

ISB2

Output Low Voltage (IOL =+ 8.0 mAl
Output High Voltage (IOH - - 4.0 mAl
NOTE. Good decoupllng of the local power supply should always be used.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA - 25°C Periodically Sampled Rather Than 100% Tested)
Symbol

Typ

Max

Unit

Input Capacitance (All Pins Except DQO-D08)

Characlerlatlc

Cin

2

3

pF

InputlOutput Capacitanoe (DQ0-D08)

ClIO

7

8

pF

MOTOROLA MEMORY DATA
7-142

MCM62960

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = VCCQ = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level .............. 1.5 V
Input Pulse Levels .............................. 0 to 3.0 V
Input Rise/Fall Time . .. .. . .. .. . .. .. . . . .. . . . . . .. .. . . .. 3 ns

Output Timing Reference Level. . . . . .. . .. . . . .. . .. .. ... 1.5 V
Output Load .......... See Figure 1A Unless Otherwise Noled

READlWRITE CYCLE llMING (See Notes 1, 2, and 3)
Symbol

Peremeler

MCM62960-17

MCM6296D-20

MCM6296D-24

Min

Min

Min

Max

Max

IKHKH
tKHKL
tKLKH

Read Cycles:
Clock Access Time
Output Enable to Output Valid

tKHOV
toLOV

Output Buffer Control:
Clock High to Output Low-Z
Clock High to Output Change
Clock High to 0 High-Z
Output Enable to Output Active
Output Disable to 0 High-Z

tKHOXl
tKHOX2
IKHOZ
IGLOX
tGHOZ

-

7

-

Address
Data
Write Enable
Chip Select

tAVKH
tDVKL
tWVKL
tsoVKH
ts1VKH

2
3
2
2
2

-

-

-

2
3
2
2
2

-

2
3
2
2

Address
Data
Write Enable
Chip Select

tKHAX
tKLDX
tKLWX
tKHSOX
IKHSIX

3

-

3

-

3

-

3
3
3

RegisterJlatch Setup Times:

Registerllatch Hold Times:

8
8

-

-

25
10
10

-

-

17
7

-

20

8
5

-

8
5

20

8
-

0

-

-

2
3
3
3

8

8
-

0

8

-

2

-

Max

Unit

Not••

ns

Clock Control:
Cycle Time
Clock High Pulse Width
Clock Low Pulse Width

-

30
12
12

-

-

24
9

8
5

-

ns

ns

0
-

8

3

9

-

ns

4

-

ns

4

-

2

-

2
3
3
3

NOTES:
1. A read cycle is definad by 'II high for the setup and hold times. A write cycle is defined by 'II low for the setup and hold times.
2. An read and write cycle timings are referenced from K or G.
3. Transition is measurad ± 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tesled. At any
given voltage and temperature, tKHOZ max is less than IKHOXI min for a given device and from device to device.
4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising (or
falling in the case of'll and Data In) edges of clock (K) when the device is selecled. To select or deselect the device. both chip selects must be
valid at the rising edge of K. Timings for ~ and SO are similar.

AC TEST LOADS
+5V

+5V

480
DQ--1~----+

256

~

DO

:=~~UDING

--1~----+

256

'--_ _--+ SCOPE AND JIG)

1..-_ _--+

~'-UDING

SCOPE AND JIG)

=
Figure1B

Figure1A

MOTOROLA MEMORY DATA

7-143

•

MCM62960

READ - WRITE CYCLE

..

READ

WRITE

ORDERING INFORMATION

(Order by Full Pan Number)

Fu" Part Number - MCM62960FN17

MCM62960FN20

MCM62960FN24

MOTOROLA MEMORY DATA
7-144

MCM62960

Derating Curves
ICCA vs Cycle Time

ICCAvSVCC

1.10

1.60

,

1.05
1.00

1.20

l'\

ICCA 095
(Norm) .

"' ----

1.00
ICCA
(Nann) 0.80

r-...

0.90
0.85

0.40
0.20

20

25

30

35
40
45
CYCLE TIME (ns)

V

50

55

/'

/'

./

0.60

~

0.80
15

./

1.40

/

V

5

60

VCC(V)

KHQV vs Temperature

KHQVvsVCC

1.05

1.80

1.00

",,- ~

tKHQV 095
(Norm) .

J

V

0.90

---

~

"""'"

tKHQV
(Norm)

'('

1.60

II

1.40

1\

\

" ----- ..

1.20

"""

1.00
0.80

0.85
-10

10

20
30
40
50
TEMPERATURE ('C)

60

70

r----

5
VCC(V)

80

Change In Output RIse/Fail Times vs
Output Capacitance

KHQV vs Output Capacitance

0.30

1.04

0.20

.,V

I!.tr,l!.\j
(nsIV) 0.10

/

,. /

0.00

V

/

1.03
1.02
tKHQV
(Norm)

V

/

1.01
1.00

~~

0.99

-0.10
20

40

60

80

100

120

140

160

180

20

200

40

60

",.,
80

l/

100

It'

'I"

120

140

160

OUTPUT CAPACITANCE (pF, lumped)

OUTPUT CAPACITANCE (pF, lumped)
Derating curves are based on component typical values.

MOTOROLA MEMORY DATA
7-145

I

180

200

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62960A

Product Preview
32K x 9 Bit Synchronous
Static RAM
The MCM62960A is a 294,912 bit synchronous static random access
memory designed to provide a high-performance, cache for the SPARCTM
Family of microprocessors. It is organized as 32,768 words of 9 bits,
fabricated using Motorola's high-performance silicon-gate CMOS
technology. The device integrates input registers, high-speed SRAM, and
high drive capability outputs onto a single monolithic circuit for reduced
parts count implementation of cache data RAM applications.
Synchronous design allows precise cycle control with the use of an
external clock (K). CMOS circuitry reduces the overall power consumption
of the integrated functions for greater reliability.
Output enable (<3) is an asynchronous control input. Addresses
(AD-A14) and chip select inputs (SO, S1) are sampled through
positive-edge-triggered, non inverting registers on the rising edge of the
clock input (K). Write enable (W) and data-in are sampled on the following
edge of K through negative-edge-triggered, noninverting registers.
The MCM62960A is packaged in a 44-pin plastic-leaded chip carrier
(PLCC). Multiple power and ground pins have been utilized to
minimize effects induced by output noise. Separate power and ground
pins have been employed for DOD-D08 to allow user-controlled
output levels of 5 volts or 3.3 volts.

•

FNPACKAGE
44-LEAD PLCC
CASE 777

PIN ASSIGNMENT

A2

4 3 2 1 44 43 42 41 40 39

All

A3

38

A12

37

A4
AS

10

36

A13
A14

A6

11

35

Vss

Vss

12

34

007

000

13

001

14

33
32

VSSQ

VsSQ

15

31

VCCO

VCCO

16

30

DQ5

17 18 19 20 21 22 23 24 25 26 27 28 29

DQ4

Single 5 V ± 10% Power Supply
Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Compatibility OQ2
Fast Access Times: 15/17/24 ns Max and Cycle Times: 20/25/30 ns Min
Internal Input Registers (Address, Control, Data)
Internally Self -Timed Write Cycle
Output Enable Controlled Three-State Outputs
Common Data Inputs and Data Outputs
High Output Drive Capability: 85 pF per 1/0
High Board Density PLCC Package
• Fully TIL-Compatible
• Active High and Low Chip Select Inputs for Easy Depth Expansion

•
•
•
•
•
•
•
•

•

DQ6

PIN NAMES

AO-A 14 ............... Address Inputs
K ............................. Clock
W....................... Write Enable
G . . . . . . . . . . . . . . . . . . . .. Output Enable
SO, 51 .................. Chip Selects
DOO-DOS .......... Data Input/Output
VCC ............. + 5 V Power Supply
VCCO ..... Output Buffer Power Supply
VSS ............ , ... :....... Ground
VSSQ ................. Output Ground
NC .................... No Connection
Ali power supply and ground pins must be
connected for proper operation of the device.
VCC ~ VCCO at ali times including power up.
No Connection pins should be left open.

SPARC is a trademark of Sun Corp.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product wijhout notice.

MOTOROLA MEMORY DATA
7-146

MCM62960A

BLOCK DIAGRAM
K ________________

AO-A14

~----_.

15

-------t

32Kx9
MEMORY ARRAY

W------I~

so
81

G------------------------+----+-q

D~OO--~-------------------------~

TRUTH TABLE (See Notes 1 2 3 and 4)

s

W

G

Input/Output

Operation

F

X

X

High-Z

Deselected

T

H

L

Data Out

Read Cycle

T

H

H

High-Z

Read Cycle

T

L

H

Write Data In

Write Cycle

NOTES:
1. X means Don't Care.
2. All address and chip select inputs must meet setup and hold times for ALL low-to-high transitions of clock
(K). Winput must meet setup and hold times for ALL high-to-Iow transitions of clock (K).
3. S represents SO and Sf. T implies Sf = L and SO = H; F implies Sf = H or SO = L.
4. During a write cycle, Gmust be high before the input data required setup time and held high throughout
the data hold time.

MOTOROLA MEMORY DATA
7-147

MCM62960A

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to Vss = 0 V)
Rating
Power Supply Voltage
Output Power Supply Voltage

Symbol

Value

Unit

VCC

-0.5 to 7.0

V
V

VCCO

-0.5toVCC

Voltage Relative to VSS

Vin' Vout

- 0.5 to VCC + 0.5

V

Output Current (per VOl

lout

±20

mA

Power Dissipation (TA = 70°C, VCC = 5 V,
tKHKH = 20 ns)

Po

1.0

W

Tbias

-10to+85

°c

Temperature Under Bias
Operating Temperature

TA

oto + 70

°c

Storage Temperature

Tstg

-55to+125

°c

This device contains circuitry to protect the inputs against damage due
to high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid
application of any voltage higher
than maximum rated voltages to this
high-impedance circu~.
This CMOS memory circuit has
been designed to meet the dc and ac
specifications shown in the tables,
after thermal equilibrium has been
established.

NOTE: Permanent devIce damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended voltages for extended periods of time could affect
device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS
± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

(VCC = Vcca = 5.0 V

RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)
Parameter
Supply Voltage (Operating Voltage Range)

•

Output Buffer Supply Voltage
(5.0 V TTL Compatible)
(3.3 V 50 Q Compatible)

Symbol

Min

Typ

Max

Unit

VCC

4.5

5.0

5.5

V

4.5
3.0

5.0
3.3

5.5
3.6

V

VCCO

Input High Voltage

VIH

2.2

3.0

VCC +0.3

V

Input Low Voltage
" VIL (mIn) = - 3.0 Vac (pulse wIdth,;; 20 ns)

VIL

-0.5"

0.0

0.8

V

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Yin = 0 to VCC)

Parameter

Ilkg(l)

-

± 1.0

jlA

Output Leakage Current (G, SI = VIH, SO = VIL, Vout = 0 to VCCO)

Ilkg(O)

-

±1.0

jlA

ICCA

-

175

mA

-

40

mA

30

mA

VOL

-

0.4

V

VOH

2.4

-

V

AC Supply Current (G, SO = VIH, SI = VIL,
All Inputs = VIL = 0.0 V and VIH ,,3.0 V, lout =.0 mA,)

tKHKH = 20 ns

Standby Current (SI = VIH, SO = VIL, All Inputs = VIL and VIH, Cycle Time" tKHKH min)

ISBI

CMOS Standby Current (SI "VCC - 0.2 V, SO,;; 0.2 V, All Inputs "VCC - 0.2 V or,;; 0.2 V,
Cycle Time" tKHKH min)

ISB2

Output Low Voltage (lOL = + 8.0 rnA)
Output High Voltage (lOH = - 4.0 rnA)
NOTE. Good decoupltng of the local power supply should always be used.

CAPACITANCE (I = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol

Typ

Max

Unit

Input Capacitance (All Pins Except 000-008)

Cin

2

3

pF

Input/Output Capacitance (000-008)

CliO

7

8

pF

Characteristic

MOTOROLA MEMORY DATA
7-148

MCM62960A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = Vcca = 5.0 V ± 10%, T A = 0 to + 70°C, Unless Otherwise Noted)

Input TIming Measurement Reference Level ................ 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 ns

Output TIming Reference Level. . . . . . . . . . . . . . . . . . . . . . . . .. 1.5 V
Output Load ............ See Figure lA Unless Otherwise Noted

READIWRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM62960A-15
Parameter

Symbol

Clock Control:
Cycle TIme
Clock High Pulse Width
Clock Low Pulse Width

tKHKH
tKHKL
tKLKH

Read Cycles:
Clock Access TIme
Output Enable to Output Valid

tKHQV
IGLQV

Output Buffer Control:
Clock High to Output Low-Z
Clock High to Output Change
Clock High to Q High-Z
Output Enable to Output Active
Output Disable to Q High-Z

tKHQXl
tKHQX2
tKHQZ
tGLQX
tGHQZ

Register/Latch Setup TImes:

Register/Latch Hold TImes:

Min

Max

MCM62960A-17
Min

Max

MCM62960A-24
Min

Max

Unit

Notes

ns

Address
Data
Write Enable
Chip Select
Address
Data
Write Enable
Chip Select

-

20
8
8

-

25
10
10

-

15

-

6

-

7

-

5

0
-

tAVKH
tDVKL
twVKL
tSOVKH
tSWKH

2
3
2
2

tKHAX
tKLDX
tKLWX
tKHSOX
tKHS1X

3
2
3
3
3

8

-

2

-

-

17
7

-

24
9

-

7

5

5

-

0

-

ns

7

-

7

-

-

2
3
2
2
2

-

3
2
3
3
3

-

-

30
12
12

-

-

-

-

8

-

7

2
3
2
2
2

-

-

-

8

-

0

-

ns

-

3

9

-

ns

4

ns

4

-

-

3
2
3
3
3

-

-

NOTES:
1. A read cycle is defined by W high for the setup and hold times. A write cycle is defined by W low for the setup and hold times.
2. All read and write cycle timings are referenced from K or G.
3. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device.
4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL riSing (or
falling in the case ofW and Data In) edges of clock (K) when the device is selected. To select or deselect the device, both chip selects must be
valid at the rising edge of K. TImings for Sf and SO are similar.

AC TEST LOADS
+5V

+5V

480

480

Q

DQ--

1 44 43 42 41 40

I'8I8I'Y8B

the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
7-173

•

MCM62974

TRUTH TABLE

H
Read
Dout
ICCA
NOTE: The value W Ia a valid Input for the aatup and hold times relative to the K rlalng
edge.

ABSOWTE MAXIMUM RATINGS (VoItagaa referanced to VSS~VSSo=O V)

RMlng
PIMMI' Supply Voltage

Voltage RaIatIva to VSSIVSSO for Arrv
Pin Except VCC
Output Currant (par 110)

Symbol

Value

VCC
Vln, Vout

-0.6to +7.0

V

-0.5 to VCC+0.5

V

lout

±:lO

mA

Power Diaaipation (TA =26"C)

Tarnpareture Under Blae

Unit

Po

1.0

W

Tbias

-10to +85

"C

oto +70
"C
TA
-65 to +125
"C
Tsta
NOTE: Permanent davioa damage may occur If ABSOLUTE MAXIMUM RATINGS are
axoaedad. Functional operation should be restricted to RECOMMENDED
OPERATING CONDmONS. Exposure to higher than recommended voltagaa for
extended period. of lima could affect device reliability.
Operating TempanltUre
Storage Temperature

This device contains circuitry to protect the
inputs against damage due to high static
voItagaa or aIactrIc fieIda; howavar, It is adviIad that normal precautlona be takan to
avoid application of any voltage higher than
maximum retad voItagaa to this highimpadanoa circuit.
Thla Is a aynchronoua davioa. All aynchron01/8 Inputa must meat the apacIfied aatup
and hold timaa with stable logic IevaIa for
ALL rising adgaa of clock (K) while the devioa is aeIectad.
This davloa contains circuitry that will' enaure the output devicae are In High Z at
power up. Care should be takan by the uaar
to ansure that atl clocks are at VIL or VIH
during power up to prevent spurious read
evelaa from occurring.
Thla CMOS memory circuit haa bean designed to meat tha de and ac apacificatlons
shown In the tablea, after thermal aquHibrium has bean aatabIishad. The circuit is in
taat aockat or mountad on a printed circuit
board and trall8V8l'll8 air flow of at Ieaat 600
linear feat par minuta Ia maintained.

8

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = 5.0 V

± 10%, TA=O to 7Oo e, Unless Otherwise Notedl

RECOMMENDED OPERATING CONDmONS (VoItagaa refarenoad to VSS=VSSO=O VI
I'Ioram_
Symbol
Min

II

Typ

Max

Unit

Supply Voltage 10parating Voltage Range)

VCC

4.5

6.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

Input Low Voltage

VIL

-0.5*

-

0.8

V

Symbol

Min

-

Max
±1.0
±1.0

-

Unit
p.A
p.A
mA

180
170
0.4

*VIL (minl- -3.0 V ac (pulaa width :s:lO nsl

DC CHARACTERISTICS

I'Ioramater
Input Leakage Current (Allinputa, V)n=0 to VCC)
Output Leakage Currant fG=VIH, Vout=O to VCC, Outputs muat be high-ZI
AC Supply Currant ~-VIL' AN Inputa=VIL or VIH, 10ut=0 mA, Cycle
rnne2:tKHKH min)
MCM62974-18: tKHKH = 18 ns
MCM62974-:lO: tKHKH =:lO ns
Output Low Voltage UOL = 12.7 mAl
OUlput High Voltage UOH = -1.8 mAl

Ilkam
Ilkg(OI
ICCA

-

2.8

-

V
V

Symbol

Typ

Cin
Cout

3
5

Max
4
7

Unit
pF
pF

VOL
VOH

CAPACITANCE (1= 1.0 MHz, dV = 3.0 V, TA =25"C, Periodically Sampled Rather Than 100% Taatadl

Chara_rIHIc
Input Capacitanoa
Output Capacitanoa

MOTOROLA MEMORY DATA
7-174

MCM62974

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V ±10%, TA=O to

+ 7O"C,

Unless Otherwise Noted)

Output Timing Measurement Reference Level • • • • . • • . • 1.5 V
Output Load • • . . . . . • • . See Figure lA Unless Otherwiae Noted

Input Timing M.....rement Reference Lewt • . • • . . • • • . 1.5 V
Input Pulaa LaveIa • • • • • . . • • • • • • • • • • . • • • • .0 to 3.0 V
Input Rise/Fal Time . . . . . . . . • . • . . . . • . • . • . • . . . 5 lIS

READ/WRITE CYCLE
Symbol

Parameter

MCM62lI74-18

MCM1121174-211

Min

Min

Read Cycle THn8

tKHKH

18

Write Cycle Time

tKHKH

18

Max

-

Clock High Access THn8

tKHQV

~ Low to Output Valid

tGLQV

-

Output Active from Clock High

tKHQ)(

0

Output Active from ~ Low

tGLQ)(

0

Clock Low Pulaa Width

tKLKH

Clock High Pulsa Width

tKHKL

5
5

-

tAVKH
tOVKH
twvKH

4

-

tKHAX
tKHOX
tKHWX

2

Clock High to Output High 2 (W=VIL)

tKHQ2

G High to Output High 2

tGHQ2

Setup THn8S for:

A

0

Vi
Hold Times for:

A

0

Vi

10
10

Max

-

20
20

0
0

Unit

Not..

ns

1,3
2,3

10

no
no

3,4

10

ns

3

-

no
lIS

ns

4

-

n8

1,2,5

-

2

-

no

1,2,5

0

10

0

10

ns

3,6

0

10

0

10

ns

3,6,7

5
6

lIS

NOTES:
1. A reed is defined by Vi high for the opecified letup and hold times.
2. A write is defined by W low for the specified aatup and hold times.
3. All reed and write cycle timing is referenced from K or from ~.
4. Valid data from K high will be the data stored at the address of the last valid read cycle.
5. This is a synchronous davIca. All synchronous Inputs must mast the specified aatup and hold times with stable logic levels for ALL rising
edgea of clock (K) while the device is aslacted.
6. Transition Is maaoured ±600 mVfrom steedy-stats voltage with load of F"'IIure lB. This paramatsr isaamplad and not 100% tasted. At any
given voltage and temperature, tKHQ2 max is leas then tKHQ)( min and tGHQ2 max Is less than tGLQ)( min for a given davIca.
7. ~ becomes a don't care signal for successive wrhes after the first write cycle.

AC TEST LOADS

+5V

+5V

330

330

D-_-----t

0 -.......- - - - .

ONCUJIIING

5pf
(INClUDING

SCOPE AND JIG)

SCOPE AND JIG)

85 pf

330

330

Rgure 18

Rgure1A

MOTOROLA MEMORY DATA
7-175

•

MCM62974

READ CYCLE

K (CLOCK)
~

_ _I I

G(OUTPUT ENABLE)

A (ADDRESS)

i

!WRITE ENABLE)

o (DATA Dun

1

-J-:, ~ ~-~ -x. .
IGLOV

tKHnV

tG HOZ
- - - - - O ' - _ - 2 - - --

_-_-o._-_-_-_

WRITE CYCLE

(SEPARATE I/O MODE)

..

(COMMOI YO MODE)

K (CLOCKI

IT (OUTPUT ENABLE)

A (ADDRESS)

W(WRITE ENABLE)

o (DATA IN)
~rIGHQZ

o IDATA DUTI

~

0.-1

HIGH·Z - - - - - - -

ORDERING INFORMATION
(Order by Full Part Number)

T-'CM

Motorola Memory PrefiX _ _ _ _ _

T1

Part N u m b e r - - - - - - - - - - - - - - - l

TL..______ Speed (18=18 ns, 20=20 ns)

L
_________

Full Part Numbers-MCM62974FN18

MCM62974FN2O

MOTOROLA MEMORY DATA
7-176

Package (FN=PLCC)

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - MCM62974A
Product Preview

TECHNICAL DATA

4K X 12 Bit Synchronous Static
with Output Registers and Output Enable

RAM

The MCM62974A is a 49,152 bit synchronous static random access memory organized
as 4096 words of 12 bits, fabricated using Motorola's second-generation high-~rformance
silicon-gate CMOS (HCMOS III) technologv. The device integrates input registers, high
speed SRAM, and high-drive capability output registers onto a single monolithic circuit for
reduced parts count implementation of cache data RAM, writeable control store applications, and other applications that utilize long words.
Synchronous design allows precise cycle control with the use of an external clock (K),
while CMOS circuitry reduces the overall power consumption of the integrated functions
for greater reliability.
The address (AO-All), data (00-011), and write (W) inputs are all clock
(K) controlled, poaitive-edge-triggered. noninverting registers.
The MCM62974A provides output register operation. At the rising edge
of clock (K), the RAM data from the previous clock (K) high cvcle is
07
presented.
06
The output enable (G) provides asynchronous bus control for common
05
1/0 or bank switch applications.
Write operations are internallv self-timed and initiated bV the rising edge
of the clock (K) input. This feature eliminates complex off-chip write pulse
generation and provides increased flexibility for incoming signals.
•
•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supplv
Fast Cycle TImes: 18/20 ns Max
Fast Clock (K) Access Times: 10/10 ns Max
Address, Data Input, and W Registers On-Chip
Output Enable for Asynchronous Bus Control
Output Registers for Fully Pipelined Applications
High Output Drive Capebility
Internally Self-Timed Write Pulse Generation
Seperate Data Input and Data Output Pins

FN PACKAGE
44-LEAD PLCC
CASE 777

PIN ASSIGNMENT

44 43 42 41

AO
011
010

04

10

03

11

VSSO

02

12

Q9

Q9

01

13

07

DO

14

06

A7

15

05

A6

16

04

A9

17

OJ
18 19 20 21 22 23 24 25 26 27 28

BLOCK DIAGRAM
AD-All

PIN NAMES

Vee
VSS

AO-A 11. . . . . . . . . Address Inputs

'Ii. . . . . . . . . . . . . Write Ensble

VSSQ

00-011

~ .. .. .. .. .. .. OutpUt Enable
QQ

00-011 . . . . . . . . • . Data Inputs
00-011 . . . . . . . . . Data Outputs
K . • • • • . . . . • • . . • Clock Input
VCC . . • • . • . + 5 V Power Supply
VSS ••..•••••..••• Ground
VSSO •..•• OutpUt Buffer Ground

For proper operation of the device Vss
all

ROW
COL

and both VSSO leads must be connectad to ground.

AS. A4. A3. A2. AI. AD. A6
A7. All. AID. A9. AB
MSB

LSB

This document contains information on 8 product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA MEMORY DATA
7-177

•

MCM62974A

TRUTH TABLE

I

~ I

Operation

Current

Write

HighZ

Read

Dout

ICeA

NOTE: The value W Is a valid input for the eetup and hold times relative to the K rising

edge.

ABSOWTE MAXIMUM RATINGS (voltages referenced to VSS =VSSO=O V)
Rating

Symbol

Power Supply Voltage

Velue

Unit

VCC

-0.6to +7.0

V

Vln, Vout

-0.5 to VCC+0.5

V

Output Current (per 110)

lout

±ZO

mA

Power DissIpation ITA = 26DC)

Po

1.0

W

Tbias

-10to +85

DC

Voltage Relativa to VSSIVSSO for Any
Pin Except VCC

Temperatura Under Bias
Operating Temperatura

TA

Storage Temperatura

Tata

o to

+70

-65 to +125

DC
DC

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS ara
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposura to higher then recommended voltages for
extended periods of time could affect device reliability.

This device containa circuitly to pro1llCt the
inputs against demage due to high static
voItagee or elactrlc fields; howevar, It is advieed that normal precautlone be taken to
avoid application of any voltage higher then
maximum rated voltages to this hlghimpedance circuit.
This is a synchronous device. All synchronous inputs must meat the specified eetup
and hold times with atable logic IevaIs for
ALL rising edges of clock (K) while the de-

vice Is selected.
This device containe circuitly that will ensura the output devices ara In High Z at
power up. Cara should be taken by the uear
to eneura that all clocks ara at VIL or VIH
during power up to prevent spurious read
cycles from occurring.
This CMOS memory circuit has been designed to meat the de and ac specifications
shown in the tables, after thermal equilibrium has been established. TIta circuit is in
a tast socket or mounted on a printed circuit
board and traneV8188 air flow of at least 500
linear feat per mlnuta is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ±10%, TA=O to 7OD e, Unless Otherwise Noted)

•

RECOMMENDED OPERATING CONDmONS (Voltages referanced to vss=vsso=o V)
Symbol

Min

Typ

Max

Unit

Supply Voltage (Operating Voltaga Range)

VCC

4.5

5.0

5.5

V

Input High Voltage

VIH

2.2

-

VCC+0.3

V

Input Low Voltage

VIL

-0.5*

-

0.8

V

Param_

*VIL (min) = -3.0 V ac (pulse width :sZO ne)

DC CHARACTERISTICS
Symbol

Min

Max

Unit

Input Leakage Currant (All Inputs, Vln=O to VCC)

likalll

-

±1.0

pi.

Output Leaksge Currant tG=VIH, Vout=O to VCC, Outputs must be high-Z)

Ilka(O)

-

±1.0

Parameter

AC Supply CUIrsnt I~=VIL. Alllnputs=VIL or VIH, 10ut=0 mA, Cycle
rnne~tKHKH min)
MCM62974A-18: tKHKH = 18 ne
MCM62974A-ZO: tKHKH =ZO ne

ICCA

pi.
mA

Output Low Voltage (lOL = 12.7 mAl

VOL

-

0.4

V

Output High Voltage (lOH =

VOH

2.8

-

V

Symbol

Typ

Max

Unit

Cin

3

4

pF

Cout

6

7

pF

- 1.8 mAl

180
170

CAPACITANCE (f= 1.0 MHz, dV=3.0 V, TA = 26DC, Pariodlcelly Sampled Rather Than 100% Tasted)
Ch.ractaristlc
Input Capacitance
Output Capacitance

MOTOROLA MEMORY DATA
7-178

MCM62974A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC=5.0 V

± 10%, TA=O to +7O"C, Unl_ Otherwise Noted)

Input Timing Mea...11IIYI8Ilt Reference LewI • . • . • • . • • . 1.5 V
Input Pulea LewIs • . • • • • . • • . • . • • • • . • • • . • .0 to 3.0 V
Input Risel Fall Time • • . • • • • • • • • • • . • . • . • • . • • • • 5 lIS

Output riming Measurement Refanlnce Level • • • • • • • • • 1.6 V
Output Load. • . • • • . . . •See Figure lA Unless Otherwise Noted

READ/WRITE CYCLE
Param_

Symbol

MCM8i2II74A-18

MCMI2I74A-211

Min

Max

Min

Read Cycle Time

tKHKH

18

-

20

Write Cycle Time

tKHKH

18

-

20

Clock High ACC8118 Time

IKHOV

-

10

~ Low to Output Valid

IGLOV

-

10

Output Active from Clock High

IKHOX

0

Output Active from ~ Low

IGLOX

0

tKLKH

6
5

Clock Low Pulea Width
Clock High Pulea WIdth
Setup Times for:

tAVKH
tDVKH
twvKH

4

-

IKHAX
tKHDX
tKHWX

2

-

IKHKL
A

0

W
Hold Times for:

A

0

W

0
0

5
5
4

2

Unit

Max

-

Notea

ns

1,3

ns

2,3

10

ns

3,4

10

ns

3

-

n.

-

1,2,5

ns
ns
ns
ns

1,2,5

ns

Clock High to Output High Z (W = VILI

IKHOZ

0

10

0

10

~ High to Output High Z

tGHOZ

0

10

0

10

ns
ns

3,8
3,6,7

NOTES:
1. A rescI is defined by W high for ths specified setup and hold times.
2. A wrIta is daflned by W low for the apecifoed setup and hold limes.
3. AN rescI and wrha cycle timing is referenced from K or from ~.
4. Valid data from K high will be the data atored at the address of the last valid read cycle.
5. This is a synchronous device. All synchronous inputs must mset the specified setup and hoidtimes willi atable logic levels for ALL rising
adgea of clock (KI while the device is selectad.
6. Trensition Is measured :I: 500 mV from steady-_ voltage with load of Figure 1B. This paramatar is sampled and not 100% 1881ad. At any
given voltage and temperature, tKHOZ max Is lees than IKHOX min and IGHOZ max is lees than IGLOX min for a given device.
7. ~ becomas a don't care algnal for succeesive wrItas after the first wrIta cycle.

AC TEST LOADS

+5V

+5V

330

330

Q------..

Q -....- - - - .

85 pf

330

5pf

330

IINClUDING
SCOPE AND JIGI

"NClUDING
SCOPE AND JIGI

FlgurelA

Figure lB

MOTOROLA MEMORY DATA
7-179

•

MCM62974A

READ CYCLE

K (ClOCKI

ii (OUTPUT ENABLEI

A (ADDRESSI

iii (WRITE

ENABLEI
LQV

IGHOZ jlGLOX
Q (DATA Dun

On - 2

rHIGH-Z

~

~--------------~

~--~

WRITE CYCLE
(UPMATE 110 MODEl

ICOMMOI I/O MODEl

K {CLOCKI

•

G(OUTPUT ENABLEI

A {AODRESSI

Vi (WRITE ENABLEI

o {DATA INI

~tGHOZ
a IOATA Dun

HIGHZ - - - - - - -

On-- 2

ORDERING INFORMATION
(Order by Full Part Number)

MCM

Motorola Memory Prefix

T

T 1T
62974A

X

XX

Speed (18= 18 ns, 20=20 nsl
Package (FN = PLCCI

Part Number - - - - - - - - - - - - - - - '
Full Part Numbers-MCM62974AFNI8

MCM62974AFN20

MOTOROLA MEMORY DATA
7-180

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL
DATA

-------------MCM62975

Product Preview

4K X 12 Bit Synchronous Static RAM
whh Transparent Outputs and Output Enable
The MCM62975 is a 49,152 bit synchronous static random access mamory organized as
4096 words of 12 bits, fabricated using Motorola's secon
Output Leakage Current (G

=VIH)

AC Supply Current (G =VIH,
All Inputs =V,L = 0.0 V and V,H ~ 3.0 V,
lout = 0 mA, Cycle TImes ~ tKHKH min)
Output Low Voltage (IOL =+ 8.0 rnA)
Output High Voltage (lOH

Min

l'kg(O)

-

ICCA

-

VOL

-

VOH

2.4

Ilkg(l)

=- 4.0 mAl

1YP

-

Max

UnH

±1.0

j.lA

±1.0

j.lA

150

170

mA

-

0.4

V

-

V

CAPACITANCE (I = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol

lYP

Max

Unit

Input Capacitance (All Pins Except OOO-OQ3)

Cin

4

6

pF

Input/Output Capacitance (000-003)

CvO

8

10

pF

Parameter

CAPACITIVE LOAD EQUIVALENT RESISTANCE

i.CxdVldt

Y[+Cl
"'"-1 F' t"' J~'
i.cx(dVout\'85Xl0-12x(~\
.SOmA
dt )
4.25 x 10 4 )
85 pF load is equivalent to a 50 Q tennination

MOTOROLA MEMORY DATA
7-206

i.Y..'!' .SOmA
R

50

•

MCM62982

AC OPERAnNG CONDITIONS AND CHARACTERI8nCS
(VCC=5.0V± 10%. Vcca=5.0Vor3.3 V± 10%. TA =Oto+70·C. Unless Otherwise Noted)
Input liming Measurement Reference Level .....•.......... 1.5 V
Input Pulse Levels .•..•...•..•..•...•......•.••.••.• 0 to 3.0 V
Input RiseJFalllime . . • . . • . • . . . . . • . . . . . . . . • . . . • . . . . . . . • .• 3 ns

Output Timing Reference Level. . . . . . . . • . • . • . . . . . . . . . • • . •. 1.5 V
Output Load ......•.•... See Figure 1A Unless Otherwise Noted

READ AND WRITE CYCLE nMlNG (See Note 1)
MCM62982-12 MCM62982-15
Parameter

Symbol

Cycle limes:
Clock High to Clock High

tKHKH

Access Times:
Clock High to Output Valid
Output Enable Low Output Valid

IKHOV
'GLOV

Aborted Write Cycles:
Clock Low to Asynchronous Write Strobe High
Clock High to Asynchronous Write Strobe Invalid
Output Buller Control:
Output Enable High to Output Hlgh-Z
Output Enable Low to Output Low-Z
Reads:
Clock High to Output Low-Z after Write
Clock High to Output Invalid
Wrnes:
Clock High to Output Hlgh-Z after Read

Max

12

8
6

tKLAWH
IKHAWX

-2

'GHQZ
tGLOX

0
0

tKHOXI
IKHOX2

4
5

-

IKHQZ

3

8

0

-

Min

Max

15

-

-2

10
6

Unit

Note.

ns
ns
2.
2
ns

0

-

ns

Clock:
Clock High Time
Clock Low Time

•

Min

Setup limes:
Address Valid to Clock High
Synchronous Write Enable Valid to Clock High
Writes:
Date In Valid to Clock High
Asynchronous Write Strobe Low to Clock High
Hold limes:
Clock High to Address Invalid
Clock High to Synchronous Write Enable Invalid
Writes:
Clock High to Date In Invalid
Clock High to Asynchronous Write Strobe High

IKHKL
tKLKH

3
8

tAVKH
tSWVKH

3
3

tDVKH
tAWLKH

5
5

IKHAX
tKHSWX

2
2

IKHDX
IKHAWH'

.0
2

6

-

2
2
4
5

-

3

10

4
8

3
3
6
6
2
2
0
2

3
3

6

-

3
3
ns

ns

ns

NOTES:
1. This is a synchronous device. All synchronous inputs must meel the specified setup and hold limes wnh stable logic levels for ALL rising
edges of ctock (K).
2. Into rated load of 85 pF equivalent resisllve load (see Figure 1).
3. Transition is measured ±500 mVlrom steady-stete vonage wnh output load of Figure 1B. This parameter is sampled and noll 00% tested. At
any given voltege and temperature, tKHQZ is less than tKHOXI and 'GHOZ is less than 'GLOX for a given device.

MOTOROLA MEMORY DATA
7-206

MCM62982

READ AND WRITE CYCLES

K

ADDRESS

Q

--

taLQV;----i

DATAIN - - - - - - - - - - - - - - - - - - - - {
READ

READIWRITE

ABORTED
WRITE

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory
Part Number

prefiX~

J

x

xx

T

xx

~

~

1...--------

Full Part Numbers - MCM62982J12
MCM62982J15

Shipping Method (R2 = Tape & Reel, Blank = Rails)
Speed (12 = 12 ns, 15= 15 ns)
Package (J = 30D-mil SOJ)

MCM62982J12R2
MCM62982J15R2

MOTOROLA MEMORY DATA
7-2f17

•

-

MOTOROLA

SEMICONDUCTOR - - -_ _ _ _ _ _ _ _ _ __

TECHNICAL DATA

MCM62983

Advance Information

64K x 4 Bit Fast Synchronous
ParityRAMTM with Output Registers

•

The MCM62983 is a 262,144 bit synchronous static random access memory
organized as 65,536 words of 4 bits, fabricated using Motorola's high-performance
silicon-gate CMOS technology. The device integrates a 64K x 4 SRAM core with
advanced peripheral circuitry consisting of positive edge triggered registers on
address and synchronous write enable inputs. Asynchronous controls include
asynchronous write strobes and output enable (<3). This device has increased
output drive capability supported by multiple power pins. Four asynchronous write
strobes (AWD-AW3) are provided to allow each bit position to be written
individually, thereby simplifying the task of supporting byte parity. This x 4
organized SRAM is ideally suited for parity on 32-bit words. The device is
functionally similar to the MCM62982 with the only difference being the individual
bH write capablilty.
Write cycles are differentiated from read cycles by the state of the synchronous
write enable pin (SW) at the rising edge of clock (K). Write cycles are completed
only if the appropriate asynchronous write strobe (AWx) is asserted within the
specified setup time of the following rising edge of clock (K). Write cycles may be
aborted by ensuring each AWx is negated by the time the clock transitions to the
low state.
Read cycle output register operation occurs on the rising edge of clock (K) and
provides data from the previous clock (K) high in a two-cycle pipeline operation.
Additional power supply pins have been utilized and placed on the package for
maximum performance. In addition one set of power pins is electrically isolated
from the other set and supplies power only to the output buffers. This allows
connecting the output buffers to 3.3 V instead of 5.0 V if desired. If 3.3 V output
levels are chosen, the output buffer impedance in the "high" state is approximately
equal to the impedance in the "low" state which allows simple yet effective
transmission line terminations to be achieved.
The MCM62983 will be available initially in a 32-pin 300-mil plastic SOJ followed
by a 300-mil32-pin plastic DIP.
•
•
•
•
•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Buffers
Fast Access and Cycle TImes: 12/15 ns Max
Fully Synchronous Operation, Single Clock Control
Clock Timed Writes with Asynchronous Late Write Abort
Each Bit Position Individually Writeable for Simple Parity Support
Registered Address Inputs
Output Registers for Fully Pipelined Applications
Common Data Inputs and Data Outputs
Output Enable Controlled Three-State Outputs
High Output Drive Capability: 85 pFIOutput at Rated Access TIme
High Board Density PSOJ Package

J PACKAGE
PLASTIC
CASE 857

PIN ASSIGNMENT

K[ I .
AO [ 2

32 D Vcc
AI5
31

Ad 3

30

AI4

A2[

4

29

AI3

A3 [ 5

28

AI2

A4[

6

27

All

A5 [ 7

26

AIO

A6[

8

25

vCCO

Ad 9

24

VSSO

A8[
A9[

10

23

DOO

II

22

DOl

svd 12

21

D02

13

20

D03

vss[ 14

19

AW3

NC [ 15

18

AW2

17

AWl

(i[

AWO

16

PIN NAMES
............. Address Inputs
AWG-AW3 . Asynchronous Write Strobes
SW ........ Synchronous Write Enable
K ............................. Clock
G ..................... Output Enable
DOG-D03 .......... Data Input/Output
VCC ............. + 5 V Power Supply
VCCO ..... Output Buffer Power Supply
VSSO ........... Output Buffer Ground
VSS ........................ Ground
NC . . . . . . . . . . . . . . . . . . . . .. No Connect
AG-A~

All power supply and ground pins must be
connected for proper operation of the device.
VCC" VCCO at all times including power up.
ParityRAM is a trademark of Motorola Inc.
This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA

7-208

MCM62983

BLOCK DIAGRAM
;--

~
ADDRESS
(AD-A15)

~

ffi
a:

16

f-Ts-

T

r

t

;--

a:
w

'"a:w

I--

OUTPUT
BUFFER

'"a:w

'4
....4

r-CONTROL

T

K

!i2

WRITE AMPLIFIER

------+
255 n ~
: =5pF

00-._----+
2550

n

DO

85 pF
(iNCLUDING
SCOPE AND JIG)

(INCLUDING
SCOPE AND JIG)

MOTOROLA MEMORY DATA

7-209

•

MCM62983

DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = 0 to +70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (V0 Itages re erencedt0 VSS= V'SSO= OV)
Symbol
Parameter
Supply Voltage (Operating Voltage Range)

VCC

Output Buffer Supply Voltage
(5.0 V TTl Compatible)
(3.3 V 50 n Compatible)

Min

lYP

Max

Unit

4.5

5.0

5.5

V

4.5
3.0

5.0
3.3

5.5
3.6
VCC+0.3
0.8

V

VCCO"

Input High VoHage

VIH

2.2

3.0

Input Low Voltage
"VCCO must be ~ VCC at all times, Including power up.
""Vll (min) = - 3.0 V ac (pulse width ~ 20 ns)

Vil

-0.5""

0.0

V
V

DC CHARACTERISTICS
Symbol

Min

Typ

Max

Unit

Input leakage Current (All Inputs, Yin = a to VCC)

Ilkg(l)

-

±1.0

Output leakage Current (G = VI H)

Ilkg(O)

-

±1.0

J.1A
J.1A

AC Supply Current (G = VIH,
All Inputs = Vil = 0.0 V and VIH ~ 3.0 V,
lout = 0 rnA, Cycle limes ~ tKHKH min)

ICCA

150

170

rnA

Parameter

-

Output Low Voltage (IOl = + 8.0 rnA)

VOL

-

Output High Voltage (IOH = - 4.0 mAl

VOH

2.4

-

0.4

V

-

-

V

Unit

CAPACITANCE (I = 1 a MHz dV = 3 a v TA = 25°C Periodically Sampled Rather Than 100% Tested)
Parameter

•

Symbol

1YP

Max

Input Capacitance (All Pins Except 000 - 003)

Cin

4

6

pF

InpuVOutput CapaCitance (DQO - 003)

CvO

8

10

pF

CAPACITIVE LOAD EQUIVALENT RESISTANCE
I=CxdV/cit

X
out~

4V

-l

4.25ns

+F1-I
VoU!

"="

85pF

,,,,:,"

(~\I) .SOmA

i=CX(dVout\=S5xtO-12 x
cit )
4.25x10

85 pF load is equivalent to a 50 a termination

MOTOROLA MEMORY DATA
7-210

i=Y.
R

_.i. -SOmA
50

MCM62983

AC OPERATING CONDmONS AND CHARACTERISTICS

(Vee

=5.0 V ± 10%, VeeQ = 5.0 V or 3.3 V ± 10%, TA = 0 to +70·e, Unless Otherwise Noted)

Input Timing Measurement Reference Level ........•....... 1.5 V
Input Pulse Levels .......................•.......... 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 ns

Output Timing Reference Level. . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5 V
Output Load ............ See Figure lA Unless Otherwise Noted

READ AND WRITE CYCLE TIMING (See Note 1)
MCM62983-12 MCM62983-15
Parameter

Symbol

Cycle Times:
Clock High to Clock High

tKHKH

Access Times:
Clock High to Output Valid
Output Enable Low Output Valid

tKHOV
taLOV

Aborted Write Cycles:
Clock Low to Asynchronous Write Strobe High
Clock High to Asynchronous Write Strobe Invalid
Output Buffer Control:
Ou1put Enable High to Output High-Z
Ou1put Enable Low to Output Low-Z
Reads:
Clock High to Output Low-Z after Write
Clock High to Ou1put Invalid
Writes:
Clock High to Output High-Z after Read

Min
12

tKLAWxH
tKHAWxX

-2

taHOZ
taLOX

0
0

tKHOXl
IKHOX2
tKHOZ

Max

8
6

0

-

Min

Max

15

-

-2

10
6

Unit

Notas

ns
ns
2
2
ns

0

-

ns

Clock:
Clock High Time
Clock Low Time
Setup Times:
Address Valid to Clock High
Synchronous Write Enable Valid to Clock High
Writes:
Data In Valid to Clock High
Asynchronous Write Strobe Low 10 Clock High
Hold Times:
Clock High to Address Invalid
Clock High to Synchronous Write Enable Invalid
Writes:
Clock High to Data In Invalid
Clock High to Asynchronous Write Strobe High

6

2
2

4
5

4
5

-

3

8

3

10

tKHKL
tKLKH

3
8

tAVKH
tSWVKH

3
3

tDVKH
tAWxLKH

5
5

tKHAX
tKHSWX

2
2

tKHDX
tKHAWxH

0
2

-

4
8
3
3

6
6
2
2
0
2

3
3

6

-

-

3

3
ns

ns

ns

NOTES:
1. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising
edges of clock (I<).
2. Into rated load of 85 pF equivalent resistive load (see Figure 1).
3. Transition is measured ± SOO mV from steady-state voltage with output load of Figure 1B. This parameter is sampled and not 100% tesled. At
any given voltage and temperature, tKHOZ is less than tKHOXl and taHOZ is less than taLOX for a given device.

MOTOROLA MEMORY DATA
7-211

•

MCM62983

READ AND WRITE CYCLES

K

ADDRESS

Q

•

DATAIN - - - - - - - - - - - - - - - - - - - - {
READ

READIWRITE

ABORTED
WRITE

ORDERING INFORMATION
(Order by Full Part Number)
MCM

Motorola Memory
Part Number

prefiX~

x

T

xx

T

XX

~

~

Shipping Method (R2 = Tape & Reel, Blank = Rails)
Speed (12 = 12 ns, 15 = 15 ns)

' - - - - - - - - - Package (J = 300-mil SOJ)
Full Part Number- MCM62983J12
MCM62983J15

MCM62983J12R2
MCM62983J15R2

MOTOROLA MEMORY DATA
7-212

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62990

Advance Information
16K x 16 Bit Fast Synchronous
Static RAM
The MCM62990 is a 262,144 bit synchronous static random access memory
organized as 16,384 words of 16 bits, fabricated using Motorola's
high-performance Silicon-gate CMOS technology. The device integrates a 16K x 16
FNPACKAGE
SRAM core with advanced peripheral circuitry. Inputs to the device fall into two
PLASTIC
categories: synchronous and asynchronous. All synchronous inputs pass through
CASEna
positive-edge-triggered registers controlled by a single clock input (K). The
synchronous inputs include all addresses, the two chip enables (SE and SE), and
the synchronous write enable (SW).
Asynchronous inputs include the asynchronous byte write strobes
PIN ASSIGNMENT
(AWL and AWH), output enable (G), data (DOo-D015), data latch
enable (OL), and the clock (K). Input data can be asynchronously
~ ~lml~l~ ~~I~ ~ I~ ~ ~ ~
latched by OL to provide simplified data-in timings during write cycles.
7 6 5 4 3 2 1 52 51 50 49 48 4746
Address and write control are registered orH:hip which greatly
NC
DQ8 8
simplifies write cycles. Dual write strobes (AWL and AWH) are
DQ9 9
45 D07
provided to allow individually writeable bytes. AWL controls
44 DQ8
VCCO 10
DOo-D07, the lower bits while AWH controls 008-0015, the
43 VCCO
VSSO 11
upper bits. In addition, the AWs allow late write cycles to be aborted
,DOlO, 12'
42 VSSO
if they are "false" during the low period of the clock. Dual chip
enables (SE and SE) are provided allowing address decoding to be.0011 ,\3
41 DOS
accomplished on-Chip when the device is used in a dual bank mode:
, '[J(112
14'
40 D04
An input data latch is provided. When data latch enable (OL) is
39 D03
0013 'is
high the data latches are in the transparent state. When OL is low
38 D02
VSSO' i6
the data latches are in the latched state. This data inPut latch
'VCCO 17
37 VSSO
simplifies write cycles by guaranteeing ilata hold tIme in a simple
DQf4 18
fashion.
36~ VCCO
Additional power supply pins have been utilized and placed on the "
0015 19
35 ~ DOl
package for maximum performance. In addillon one set of power
NC 2021 22 23 24 25 26 27 28 29 30 31 32 3334 ~ DOO
pins is electrically isolated from the other two and supplies power
only to the output buffers. This allows connecting the output buffers
to 3.3 V instead of 5.0 V if desired. If 3.3 V output levels are chosen,
the output buffer impedance in the "high" state is approximately
equal to the impedance in the "low" state which allows simple yet
effective transmission line terminations to be achieved.
PIN NAMES
The MCM62990 will be available in a 52-pin plastic leaded Chip
carrier (PLCC).
AQ-AI3,.,.,., ... ,.,., Address Inputs
Typical applications for this device are cache memory and tag
K , ..... ".,.,.,., ........ Clock Input
RAMs, memory in systems which are pipelined and systems which
DL , .. ,."., .. , .. ,. DataLatchEnable
SW .,., .. ,. Synchronous Write Enable
require wide data bus widths and reduced parts count.

•

•
•
•
•
•
•
•
•
•
•

Single 5 V ± 10% Power Supply
Choice of 5 V or 3.3 V Power Supplies for Output Buffers
Fast Access and Cycle Times: 17/20/25 ns Max
Byte Writeable via Dual Write Strobes with Abort Write Capability
Separate Data Input Latch for Simplified Write Cycles
Clock Controlled Registered Address, Write Control, and Dual Chip Enables
Common Data Inputs and Data Outputs
Output Enable Controlled Three-State Outputs
High Output Drive Capability: 85 pF/Output at Rated Access Time
High Board Density 52-Lead PLCC Package

AWL .. , Lower Byte Async Write Strobe
AWH ", Upper Byte Async Write Strobe
SE ...... ,.,. Synchronous Chip Enable
§E ,.,., .. , .. Synchronous Chip Enable
G """" Asynchronous Output Enable
DOD-DOtS ,.,.",., Data Input/Output
VCC " " " ' " ' ' ' ' +SVPowerSupply
VCCO ., . , , Output Buffer Power Supply
VSSO ., .. , .. , .. , Output Buffer Ground
VSS., ... '.,., .. "., ........ , Ground
NC .,., ..... ,." .. ,.,., .. NoConnect
All power supply and ground pins must be
connected for proper operation of the device.
VCC<:Vccoatalltimes including power up.

This document contains information on a new product, Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
7-213

•

MCM62990

BLOCK DIAGRAM
DQO-OQ15
ADDRESS
(Ao-AI3)

MEMORY ARRAY
16Kx 16
128 ROWS
128 COLUMNS

14

SE

16
16

WRITE AMPLIFIER

SE

16

SW
K

G

TRUTH TABLE (See Notes)
SEa

•

Supply
Current

Status

Deselected Cycle

ISB

High-Z

Read Cycle

ICC

Hlgh-Z

L

Read Cycle

ICC

Data Out

SW

AWL

AWH

DL

G

Mode

X
X
X

X
X
X

X
H

I/O

F

X

T

H

T

H

X
X
X

T

L

L

L

H

X

Write Cycle All Bits
Transparent Data In

ICC

High-Z

T

L

H

H

X

Aborted Write Cycle

ICC

High-Z

T

L

L

H

H

X
X

Write Cycle Lower 8 Bits
Transparent Data In

ICC

High-Z

T

L

H

L

L

X

Write Cycle U&per 8 Bits
Latched ata In

ICC

High-Z

NOTES.
1. X means don't care. True (T) is SE = 1 and SE = O.
2. Registered inputs (addresses, SW, SE, and SE) satisfy the specified setup and hold times about
the rising edge of clock (K). Data-in satisfies the specified setup and hold times for DL.
3. A transparent write cycle is defined by DL high during the write cycle.
4. A latched write cycle is defined by DL transitioning low during the write cycle and satisfying the
specified setup and hold times.

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS = VSSQ = 0 V)
Rating

Symbol

Value

Unit

VCC

-0.5to 7.0 V

V

Vin, Vout

- 0.5 to Vee + 0.5

V

Output Current (per I/O)

lout

±20

mA

Power Dissipation (TA = 70°C)

Po

2.0

W

Temperature Under Bias

Tbias

-10to+85

°c

Operating Temperature

TA

Oto+70

°c

Power Supply Voltage
Vottage Relative to VssNSSQ tor Any Pin Except
VCCandVCCQ

Storage Temperature

-55to+125
Tstg
°c
NOTE. Permanent deVice damage may occur If ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS.
Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.

MOTOROLA MEMORY DATA
7-214

DL

This device contains circuitry to protect the inputs against damage due
to high static voltages or electrical
fields; however, it is advised that
normal precautions be taken to
avoid application of any voltage
higher than maximum rated vottages
to this high-impedance circuit.
This CMOS memory circuit has
been designed to meetthe dc and ac
specHications shown in the tables,
after thermal equilibrium has been
established.
This device contains circuitry that
will ensure the output devices are in
High Z at power up.

MCM62990

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee =5.0 V ± 10%, Veca =5.0 V or 3.3 V ± 10%, TA =0 to +70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voijages referenced to VSS = VSSO = 0 V)
Parameter
Supply Voltage (Operating Voltage Range)
Output Buffer Supply Voltage
(5.0 V TTL Compatible)
(3.3 V 50 Q Compatible)

Symbol

Min

Typ

Max

Unit

VCC

4.5

5.0

5.5

V

4.5
3.0

5.0
3.3

5.5
3.6

V

VCCO"

Input High Voltage

VIH

2.2

3.0

VCC +0.3

V

.

VIL

-0.5"

0.0

0.8

V

Input Low Voijage

VCCO must be ~ VCC at all times, including power up.
"VIL (min) = - 3.0 V ac (pulse width ~ 20 ns)

DC CHARACTERISTICS
Parameter

Min

Typ

-

310
290
280

360
360
360

50

80

mA

VOL

-

V

2.4

-

0.4

VOH

-

V

Symbol

Input Leakage Current (All Inputs, Vin =0 to VCC)

Ilkg(l)

Output Leakage Current (G =VIH)

Ilkg(O)

AC Supply Current (G =VIH, All Inputs =VIL or VIH, VIL =0.0 V and VIH ~ 3.0 V,
lout = 0 mAo Cycle Time?! tKHKH min)
MCM6299Q-17: tKHKH =17 ns
MCM6299Q-20: tKHKH =20 ns
MCM6299Q-25: tKHKH = 25 ns

ICCA

Standby Current (E =VIH, E =VIL, All Inputs =VIL or VIH,
VIL =0.0 V and VIH ~ 3.0 V, lout =0 mA, Cycle Time ~ tKHKH min)

ISB

Output Low Voltage (lOL =+ 8.0 mAl
Output High Voltage (IOH

=- 4.0 mAl

Max

Unit

±1.0

J.lA
J.lA

±1.0

rnA

CAPACITANCE (f =1.0 MHz, dV =3.0 V, TA =25°C, Periodically Sampled Rather Than 100% Tested)
Symbol

Typ

Max

Unit

Input Capacitance (All Pins Except DQO-0015)

Cin

4

6

pF

InpuVOutput Capacitance (00Q-DOI5)

CliO

8

10

pF

Parameter

CAPACITIVE LOAD EQUIVALENT RESISTANCE

+Pr-l
i. CxdV/dt

Voutr~v
1...14.25ns-1

Voul

S5pF

=

i.CX(dVout\.85Xl0-12X(~\
.SOmA
dt j
4.25xl0 Ij
S5 pF load is equivalent to a 50 II termination

MOTOROLA MEMORY DATA

7-215

i.Y • .!. .SOmA
R 50

•

MCM62990

AC OPERATING CONDITIONS AND "CHARACTERISTICS
(VCC = 5.0V ± 10%, Vcca = 5.0 V or 3.3 V ± 10%, TA = 0 to +70°C, Unless Otherwise Noted)
Output liming Reference Level ........................... 1.5 V
Output Load ............ See Figure 1A Unless Otherwise Noted

Input liming Measurement Reference Level ................ 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input Rise/Falilime . . .. .. .. . . . . . . . .. . . . .. .. . . . . .. .. . . . .. 3 ns
READ AND WRITE CYCLE TIMING (See Notes 1 and 2)

MCM6299D-17
Parameter
Cycle limes
Clock High to Clock High
Access limes
Clock High to Outpul Valid
Output Enable Low to Output Valid
Aborted Write Cycles
Clock Low to Asynchronous Write Strobes
{AWL, AWHl!:!i9h
Clock High to AWx Invalid
Output Buffer Control
Asynchronous Output Enable (G) High to
_ Output High Z
G Low to Output Low Z
Reads:
Clock (K) High to Output Low Z After
Deselect or Write
Data Out Hold After Clock High
Writes:
K High to Output High Z After Read

•

Clock
Clock High lime
Clock Low lime
Setup lime
Address Valid to Clock High
Synchronous Write (SW) Valid to Clock High
Synchronous Enables (SE, SE) Valid to Clock
High
Writes:
Data-In Valid to CLock High
AWL, AWH Low to Clock High
Data Latch:
Data-In Valid to DL Low
Hold limes
Clock High to Address Invalid
Clock High to SW Invalid
Clock High to SE, SE Invalid
Writes:
Clock High to Data-In Invalid
Clock High to AWL, AWH High
Clock High to DL High
Data Latch:
DL Low to Data-In Invalid
DL High to Clock High

Min

Max

Unit

25

-

ns

6

-

20
8

-

25
10

0

-

0

-

0

tKHKH

17

-

tKHOV
'GLOV

-

17

tKLAWxH

2

tGHOZ

2

MCM6299D-25

-

Min

tKHAWxL

MCM6299Q.2Q

20

Symbol

Max

Min

-

2

Max

-

Notes

ns
3
3
ns

2

-

2

10

4

ns

6

2

8

2

-

2

-

4

8

-

8

-

4

tKHOX2

5

-

5

-

5

-

tKHOZ

3

10

3

10

3

12

tGLOX

2

tKHOXl

8

4
10

--

-

3
3
3

-

6
6

--

7
7

-

2

-

2

-

tKHKL
tKLKH

4
8

-

tAVKH
tSWVKH
tSEVKH

3
3
3

--

-

3
3
3

tDVKH
tAWxLKH

6
6

-

tDVDLL

2

-

tKHAX
tKHSWX
tKHSEX

3

tKHDX
tKHAWxH
tKHDLH

2
2
2

--

tDLLDX
tDLHKH

2

-

6

2

3

4
10

-

2

3
3
2
2
2
2

6

-

--

2
3

-

2
2
2

--

-

2
7

-

-

-

3

-

4

ns

ns
5
5
5
1,5
5
2,5
ns
5
5
5
1,5

5
2,5
2,5
2,5

NOTES:
1. A transparent write cycle is defined by DL high during the write cycle.
2. A latched write cycle is defined by DL transitioning low during the write cycle and satisfying the specified hold time for the rising edge of clock
(K).

3. Into rated load of 85 pF equivalent resistive load (see Figure lA).
4. Transition is measured ± 500 mV frOm steady-state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested. At
any given voltage and temperature, tKHOZ is less than tKHOX and 'GHOZ is less than tGLOX for a given device.
5. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL riSing
edges of clock (K) or falling edges of data latch enable (DL).

MOTOROLA MEMORY DATA
7-216

MCM62990

READ CYCLES

K

ADDRESS

'I '--4--1'1 "-l,-",,-lW!.:L:!I..Y

DATA OUT

READ - UNLATCHED WRITE - READ CYCLES

1----

•

tKHKH---~

K

ADDRESS

DL

DATA IN

DATA OUT

MOTOROLA MEMORY DATA
7-217

MCM62990

WRITE CYCLES

tKHKH
K

ADDRESS

SW

AWL,AWH

DL

DATA IN

DATA OUT

G
ABORTED
WRITE

LATCHED
WRITE

•

UNLATCHED
WRITE

AC TEST LOADS
+5V

+5V

4800

4800

DO-1~---+

2550

-+

L -_ _ _

DO

----_----+

2550

85pF
(INCLUDING
SCOPE AND JIG)

'--___-+

=

=

Figure 1A

Figure 18

ORDERING INFORMATION
(Order by Full Part Number)

Full Part Number - MCM62990FN17 MCM62990FN20 MCM62990FN25)

MOTOROLA MEMORY DATA
7-218

5pF
(INCLUDING
SCOPE AND JIG)

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62990A
Product Preview
16K x 16 Bit Fast Synchronous
Static RAM
The MCM62990A is a 262,144 bit synchronous static random access memory organized as
16,384 words of 16 bits, fabricated using Motorola's high-performance silicon-gate CMOS
technology. The device integrates a 16K x 16 SRAM core with advanced peripheral circuitry.
Inputs to the device fall into two categories: synchronous and asynchronous. All synchronous
FNPACKAGE
PLASTIC
inputs pass through positive-edge-triggered registers controlled by a single clock input (K). The
CASEm
synchronous inputs include all addresses, the two chip enables (SE and SE), and the synchronous write enable (SW).
Asynchronous inputs include the asynchronous byte write strobes (AWL and
AWH), output enable (<3), data (000-0015), data latch enable (OL), and the clock
PIN ASSIGNMENT
(K). Input data can be asynchronously latched by OL to provide simplified data-in
timings during write cycles.
Address and write control are registered on-chip which greatly simplifies write
cycles. Dual write strobes (AWL and AWH) are provided to allow individually
6 5 4 3 2 ~52515049484748 NC
OOB
writeable bytes. AWL controls 000-007, the lower bits, while AWH controls
45 007
0Q9
008-0015, the upper bits. In addition, the AWs allow late write cycles to be
44 DOS
aborted if they are ''false" during the low period of the clock. Dual chip enables Vcca 10
(SE and SE) are provided allowing address decoding to be accomplished
VSSQ 11
43 VCCO
on-Chip when the device is used in a dual bank mode.
42 VSSO
0010 12
An input data latch is provided. When data latch enable (OL) is high the data 0011 13
41 DOS
latches are in the transparent state. When OL is low the data latches are in the
40 DQ4
latched state. This data input latch simplifies write cycles by guaranteeing data 0012 14
39 0Q3
hold time in a simple fashion.
0013 15
3S 002
Additional power supply pins have been utilized and placed on the package
Vssa 16
for maximum performance. In addition one set of power pins Is electrically iso- Vcca 17
37 VSSO
lated from the other two and supplies power only to the output buffers. This
0014 IS
36 Vcca
allows connecting the output buffers to 3.3 V instead of 5.0 V if desired. If 3.3 V
0015 19
35 001
output levels are chosen, the output buffer impedance in the "high" state is approximately equal to the impedance in the "low" state which allows simple yet
NC 2021 22 23 24 25 26 27 28 29 30 31 32 3334
effective transmission line terminations to be achieved.
The MCM62990A will be available in a 52-pin plastic leaded chip carrier
(PLCC).
Typical applications for this device are cache memory and tag RAMs,
memory in systems which are pipelined and systems which require wide data
bus widths and reduced parts count.
PIN NAMES
• Single 5 V ± 10% Power Supply
AQ-AI3 ............... Address Inputs
• Choice of 5 V or 3.3 V Power Supplies for Output Buffers
K ........................ Clock Input
• Fast Access Times: 12115/20/25 ns Max
DL ................ Data Latch Enable
SW ........ Synchronous Wrtte Enable
• Byte Writeable via Dual Write Strobes with Abort Write Capability
AWL ... Lower Byte Async Write Strobe
• Separate Data Input Latch for Simplified Write Cycles
AWH ... Upper Byte Async Write Strobe
• Clock Controlled Registered Address, Write Control, and Dual Chip Enables
SE .......... Synchronous Chip Enable
§.E .......... Synchronous Chip Enable
• Common Data Inputs and Data Outputs
G ........ Asynchronous Output Enable
• Output Enable Controlled Three-State Outputs
DOQ-D01S ......... Data InpuVOutput
• High Output Drive CapabilitY: 85 pFIOutput at Rated Access Time
VCC ................ S V Power Supply
VCCO .... , Output Buffer Power Supply
• High Board Density 52-Lead PLCC Package
VSSO ........... Output Buffer Ground
VSS ......................... Ground
NC .. . . . . . . . . . . . . . . . . . . .. No Connect
All power supply and ground pins must be
connected for proper operation olthe device.
VCC '" VCCO at all times including power up.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA MEMORY DATA
7-219

MCM62990A

BLOCK DIAGRAM

DQO-OQ15
16

16

SE

SE

16

LATCH

SW
K

G

DL

TRUTH TABLE (See Notes)
SEs

F
T

AWH

DL

G
X
H

X
H
H

X
X
X

X
X
X

X
X
X

L

L

L

H

L
X

T

L

H

H

T

L

L

H

X
H

X
X

T

L

H

L

L

X

T
T

..

SW AWL

Deselected Cycle
Read Cycle
Read Cycle
Write Cycle All Bits
Transparent Data In

Supply
Current

I/O
Status

19B
ICC

High-Z
High-Z

ICC
ICC

Data Out
High-Z

Aborted Write Cycle

ICC

High-Z

Write Cycle Lower 8 Bits
Transparent Data In

ICC

High-Z

Write Cycle Upper
8 Bits Latched Data In

ICC

High-Z

NOTES:
1. True (T) is SE = 1 and SE = O.
2. Registered inputs (Addresses. SW. SE. and SE) satisfy the specified setup and hold
times aboutthe rising edge of clock (K). Data-in satisfies the specified setup and hold
times for DL.
3. A transparent write cycle is defined by DL high during the write cycle.
4. A latched write cycle is defined by DL transitioning low during the write cycle and satisfying the specified setup and hold times.

MOTOROLA MEMORY DATA

7-220

MCM62990A

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = VSSO = 0 V)
Rating

Symbol

Value

Unit

VCC

-0.5 to + 7.0

V

Yin. Vout

-0.5to
VCC+0.5

V

Output Current (per I/O)

lout

±20

mA

Power Dissipation (TA = 70·C)

Po

2.0

W

Temperature Under Bias

Tbias

-10to+85

·C

Operating Temperature

TA

Oto + 70

·C

Power Supply Voltage
Voltage Relative to VssNsso for Any
Pin Except VCC and VCCO

·C
-55to+ 125
Tsta
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
Storage Temperature

This device contains circuitry to protect the inputs against damage due to
high static voltages or electric fields;
however. it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated
voltages to this high-impedance circuil.
This CMOS memory circuit has been
designed to meet the dc and ac specifications shown in the tables. after thermal equilibrium has been established.
This device contains circuitry that will
ensure the output devices are in High-Z
at power up.

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = Veca = 5.0 V ±10%. TA = 0 to +70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS

=Vsso =0 V)
Symbol

Typ

Min

Max

Unit

Supply Voltage (Operating Voltage Range)

VCC"

5.0

4.5

5.5

V

Output Buffer Supply Voltage (5.0 V TTL Compatible)
(3.3 V 50 Q Compatible)

VCCO

5.0
3.3

4.5
3.0

5.5
3.6

V

Parameter

Input High Voltage

VIH

3.0

2.2

VCC+0.3

V

Input Low Voltage

VIL

0.0

-OS

0.8

V

Symbol

Typ

Min

Max

Unit

Ilkolil

-

-

± 1.0

IlA
IlA

• VIL(min} = - 3.0 V ac (pulse width,; 20 ns)
"VCC must be ~ Vcca at all times, including power up.
DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, Yin
Output Leakage Current (G

=0 to VCC)

=VIH)

AC Supply Current (G =VIH, lout =0 mAo All Inputs =VIL or VIH.
VIL =0.0 V and VIH ~ 3.0 V, Cycle lime ~ tKHKH min)

Standby Current (E =VIH. E =VIL. lout =0 mAo All Inputs
VIL =0.0 V and VIH ~ 3.0 V. Cycle lime ~ tKHKH min)
Output Low Voltage (lOL

=VIL and VIH

=+ 8.0 mA)
=- 4.0 mA)

=1 0 MHz

310
300
290
280

ISB

50

-

-

-

0.4

V

2.4

-

V

Symbol

Typ

Max

Unit

Cin

4

6

pF

Cout

8

10

pF

,
VOL

Output High Voltage (IOH
CAPACITANCE (f

IlkolOI
ICCA12
ICCA15
ICCA20
ICCA25

VOH

dV =3 0 V, T A

=25·C

± 1.0

mA

360
70

mA

Periodically Sampled Rather Than 100% Tested)

Parameter
Input Capacitance (All Pins Except DOC-DOI5)
Input/Output Capacitance (DOO-DOI5)

MOTOROLA MEMORY DATA
7-221

..

MCM62990A

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC - 5.0 V ±100/0, Vcca = 3.3 Vor 5.0 V ±100/0, TA

=0 to '+70·C, Unless Otherwise Noted)

Output liming Reference Level .......................... 1.5 V
Output Load ............. See Figure 1A Unless Otherwise Noted

Input liming Measurement Reference Level ............... 1.5 V
Input Pulse Levels .................................. 0 to 3.0 V
Input RiselFalllime ..................................... 3 ns

READ CYCLE TIMING (See Notes 2 and 3)
Parameter
Cycle limes
Clock High to Clock High
Access limes
Clock High to Output Valid
Output Enable Low to Output Valid
Aborted Write Cycles
Clock Low to Asynchronous Write
Strobes (AWL, AWH) High
Clock High to AWx Invalid
Output Buffer Control
Asynchronous Output Enable (G) High to
Output High Z
G Low to Output Low Z
Reads:
Clock (K) High to Output Low Z After Deselect or Write
Data Out Hold After Clock High
Writes:
K High to Output High Z After Read

•

Clock
Clock High lime
Clock Low lime
Setup limes
Address Valid to Ciock High
Synchronous Write (SW) Valid to Clock
High
Synchronous Enables (SE, SE) Valid to
Clock High
Writes:
Data-In Valid to Clock High
AWL, AWH Low to Clock High
Data Latch:
Data-In Valid to DL Low
Hold limes
Clock High to Address Invalid
Clock High to SW Invalid
Clock High to SE, BE Invalid
Writes:
Clock High to Data-In Invalid
Clock High to AWL, AWH High
Clock High to DL High
Data Latch:
DL Low to Data-In Invalid
DL High to Clock High

MCM62990A-12
Symbol

MCM62990A-15

MCM62990A-20

MCM62990A-25
Unit

Notas

Min

Max

Min

Max

Min

Max

Min

Max

15

-

15

-

20

-

25

-

12
5

-

15

-

0

0

-

25
10

0

-

20
8

tKLAWxH

-

It------------------------------

DATA OUT _ _ _

G----~!---------------------------------LATCHED
WRITE

UNLATCHED
WRITE

ABORTED
WRITE

ORDERING INFORMATION
(Order by Full Part Number)

Motorola Memory Prefix

A

62U1!A,

TFLN._X_IX__

Part Number - - - - - - - - - - '

Speed (12 =12 ns, 15 = 15 ns, 20
25 = 25 ns)
Package (FN = PLCC)

Full Part Numbers- MCM62990AFN12 MCM62990AFN15 MCM62990AFN20 MCM62990AFN25

MOTOROLA MEMORY DATA
7-226

=20 ns

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

MCM62995

Advance Information
16K x 16 Bit Asynchronous/Latched
Address Fast Static RAM

•

The MCM62995 is a 262,144 bit latched address static random access memory
organized as 16,384 words of 16 bits, fabricated using Motorola's
FNPACKAGE
high-performance silicon-gate CMOS technology. The device integrates a 16K x 16
PLASTIC
CASEna
SRAM core with advanced peripheral circuitry consisting of address and data input
latches, active high and active low chip enables, separate upper and lower byte
write strobes, and a fast output enable. This device has increased output drive
capability supported by multiple power pins. In addition, the output levels can be
PIN ASSIGNMENT
either 3.3 V or 5 V TTL compatible by choice of the appropriate output bus power
supply.
Address, data in, and chip enable latches are provided. When
latch enable (LE for address and Chip enables and DL for data in) is
7 6 5 4 3 2 ~ 52 51 50 49 48 47 46
high the address, data in, and chip enable latches are in the
DOS
transparent state. If latch enable (LE, DL) is tied high the device
0Q9
45
can be used as an asynchronous SRAM. When latch enable (LE,
44
DL) is low the address, data in, and chip enable latches are in the
VCCQ 10
43
latched state. This input latch simplifies read and write cycles by
VSSO 11
guaranteeing address and data in hold time in a simple fashion.
0010 ··I~
42
Dual write strobes (BWL and BWH) are provided to allow
':·.tipll
41
individually writeable bytes. BWL controls DOO-D07, the lower
',0012 14
40
bits. While BWH controls D08-DOI5, the upper bits...,:
'i \. .,,,<
, " ::,. <
39
Additional power supply pins have been utilized and'Pliiced on.ttte
OPl~~.s '
38
package for maximum performance. In addition. the OUtPut buffer ",' , 'YSsa:" ~
power pins are electrically isolated from,the OthSr,Nvoand supPlY, '~",,, 4' ',~t20 1]',
37
power only to the output buffer!>. 'This allows eorinectil1!l the QiJtP\

'lX'IXI

A (ADDRESS)

E
(CHIP ENABLE)
tETQX....,...--~

Q (DATA OUT)

G
(OUTPUT ENABLE)

\XxXX)

(WRITEENABL~

YXXXY

LATCH~~~1m

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

WRIT~~~~~E~

MOTOROLA MEMORY DATA

7-241

•

MCM62995A

ASYNCHRONOUS WRITE CYCLE TIMING (See Notes 1, 2, 3, 4, and 5)
MCM62995A·12
Parameter
Write Cycle Times

Symbol
tAVAV

MCM62995A·15

MCM62995A·2Q

MCM62995A·25

Min

Max

Min

Max

Min

Max

Min

Max

15

-

15

-

20

-

25

-

-

15
15
15
15

-

20
5

Setup Times:
Address Valid to End of Write
Address Valid to E, E "False"
Address Valid to WLow
Address Valid to E, E "True"
Data Valid to WHigh
Data Valid to E or E "False"
Byte Write Low to WHigh
Byte Write High to WLow (Abort)
Byte Write Low to E, E "False"

tAVWH
tAVEF
tAVWL
tAVET
tDVWH
tDVEF
tBWxLWH
tBWxHWL
tBWxLEF

10
10

Hold Times:
WHigh to Address Invalid
E, E "False" to Address Invalid
WHigh to Data Invalid
E, E "False" to Data Invalid
WHigh to Byte Write Invalid
E, E "False" to Byte Write Invalid

tWHAX
tEFAX
twHDX
tEFDX
tWHBWxX
tEFBWxX

a
a
a
a
2
2

-

Write Pulse Width:
Write Pulse Width
Write Pulse Width
Enable to End of Write
Enable to End of Write

twLWH
twLEF
tETWH
tETEF

12
12
12
12

-

Output Buffer Control:
WHigh to Output Valid
WHigh to Output Active
WHigh to Output High-Z

twHOV
twHOX
twLOZ

12
5

a
a

4
4
4

a
4

a

-

-

-

-

-

-

9

13
13

a
a
6
6
6

a
6

a
a
a
a
2
2
13
13
13
13
18
5

a

9

Unit
ns

Notes

6

ns
15
15

a
a
8
8
8

a
8

a
a
a
a
2
2

a

-

-

-

9

20
20

a
a

10
10
10

a

10

a
a
a
a
2
2
20
20
20
20
25
5

a

-

-

-

2
ns

-

-

10

ns

9
8
8,9
ns
10
7,10

NOTES:
1. LE and DL are equal to VIH for all asynchronous cycles.
2. A write occurs during the overlap of ET, Wlow and BWx low. An aborted write occurs when BWx remains at VIH while Wis low.
3. Write must be equal to VIH for all address transitions.
4. ET is defined by E going low coincident with or after E goes high, or E going high coincident with or after E goes low.
5. EF is defined by E going high or E gOing low.
6. All write cycle timing is referenced from the last valid address to the first transitioning address.
7. If G goes low coincident with or after Wgoes low, the output will remain in a high impedance state.
8. If E and E goes true coincident with or after Wgoes low the output will remain in a high impedance state.
9. If E or E goes false coincident with or before Wgoes high the output will remain in a high impedance state.
10. Transition is measured ± 500 mV from steady-state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, twLOZ is less than tWHOX for a given device.

MOTOROLA MEMORY DATA

7·242

MCM62995A

ASYNCHRONOUS WRITE CYCLE
lE
(LATCH ENABLE)

A(ADDRESS)

E
(CHIP ENABLE)

Vi
(WRITE ENABLE)

BWx(BYTE
WRITE ENABLE)

DATA-IN

Dl(DATA
LATCH ENABLE)

Q (DATA OUT)

G
(OUTPUT ENABLE)

~~

__~r-\~___________________

MOTOROLA MEMORY DATA
7-243

•

MCM62995A

LATCHED READ CYCLE TIMING (See Notes 1. 2. 3. and 4)
MCM62995A-12
Parameter
Read Cycle TImes

•

Symbol
tAVAV

MCM62995A-15

MCM62995A-20

Min

Max

Min

Max

Min

15

-

15

-

20

Max

-

MCM62995A-25
Min

Max

25

-

Access TImes:
Address Valid to Output Valid
E. E "True" to Output Valid
LE High to Output Valid
Output Enable Low to Output Valid

tAVOV
tETOV
tLEHOV
IGLOV

-

12
12
12
5

-

15
15
15
6

-

20
20
20
8

-

Setup TImes:
Address Valid to LE Low
E. E "Valid"to LE Low
Address Valid to LE High
E. E "Valid" to LE High

tAVLEL
tEVLEL
tAVLEH
tEVLEH

2
2
0
0

2
2
0
0

-

-

2
2
0
0

tLELAX
tLELEX

3
3

3
3

-

Output Hold:
Address Invalid to Output Invalid
LE High to Output Invalid

tAXOX
tLEHOXl

4
4

Latch Enable High Pulse Width

tLEHLEL

5

Output Buffer Control:
E. E ''True" to Output Active
G Low to Output Active
LE High to Output Active
E. E "False" to Output High-Z
LE High to Output High-Z
G High to Output High-Z

tETOX
IGLOX
tLEHOX2
tEFOZ
tLEHOZ
tGliOZ

2
2
2
2
2
2

-

2
2
0
0

Hold TImes:
LE Low to Address Invalid
LE Low to E. E 'Invalid"

-

4
4

5
2
2
2
2
2
2

9
9
5

-

-

-

9
9
7

3
3
4
4

5
2
2
2
2
2
2

10
10
8

-

-

-

Unn

Notas

ns

5

ns
25
25
25
10

5
6
ns

3
3
4
4

5
2
2
2
2
2
2

-

-

6
6

ns

6

ns

ns
ns

7

10
10
10

NOTES:
1. Write Enable is squalto VIH for all read cycles.
2. All read cycle timing is referenced from the last valid address to the firsttransitioning address .
3. ET is defined by E going low coincident with or after E goes high. or E going high coincident with or after E goes low.
4. EF is defined by E going high or E going low.
5. Addresses valid prior to or coincident with E going low and E going high
6. All latched inputs must meet the specified setup and hold times with stable logic levels for ALL falling edges of latch enable (LE) and data
latch enable (OL).
7. Transition is measured ± 500 mV from steady-state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature. tEFOZ is less than tETOX and tLEHOZ is less than tLEHOX2 and tGHOZ is less than tGLOX for a
given device.

MOTOROLA MEMORY DATA
7-244

MCM62995A

LATCHED READ CYCLES
LE
(LATCH ENABLE)

A (ADDRESS)

E
(CHIP ENABLE)
tLEHOZ -joot----t~

o (DATA OUT)

G

(OUTPUT ENABLE)

W
(WRITE ENABLE)
DL(DATA
LATCH ENABLE)
BWx(BYTE
WRITE ENABLE)

'tlJ
'gjl:1:~'(!;1~ ~

w

7 6 5 4 3 2 1 52 51 50 49 48 47
NC
007
006

8

9
10
11
12
13
14
15
16
17
18
19

Vcca
VSSQ

DOS

0Q4
0Q3
0Q2
VSSO
VCCO
001

oao

PIN NAMES
AD-A 13 .............. Address Inputs
W ..................... Write Enable
BWl .......... Byte Write Strobe low
BWH .......... Byte Write Strobe High
E ............ Active High Chip Enable
E ............ Active low Chip Enable
IT '" . . . . . . . . . . . . . . . .. Oulput Enable
OOD-OOt5 ........ OatalnpuliOutput
VCC ............. + 5 V Power Supply
VCCO .... Output Buffer Power Supply
VSS ........................ Ground
VSSO .......... Output Buffer Ground
NC .................. No Connection
All power supply and ground pins must be
connected for proper operation of the de·
vice. VCC ~ VCCO at all times including
power up.

E---'-'

E-"",--_j

This document contains Information on a product under development. Motorola reserves the right to change or dlsoontinue this product without notice.

MOTOROLA MEMORY DATA
7-249

•

MCM62996

TRUTH TABLE (See Notes)
E

W

F
T
T

X
H

X
X

X
X

H

X

X

T
T

L
L

L
H

L
H

T
T

L
L

L
H

H
L

BWl BWH

G

Mode

Supply
Current

110
Status

X
H
L

Deselected Cycle
Read Cycle

ISB

High-Z

ICC

High-Z
Data Out

X

Write Cycle All Bits
Aborted Write Cycle

ICC
ICC

Read Cycle

X
X
X

ICC

High-Z
High-Z

Write Cycle Lower 8 Bits
Write Cycle Upper 8 Bits

High-Z
ICC
High-Z
ICC
..
NOTE: True (T) IS E = 1 and E = O. E, E, end addresses satisfy the specified setup and hold
times for the falling edge of LE. Data-in satisfies the specified setup and hold times
for falling edge of DL.

This device contains circuHry to protect the inputs against damage due to
high static voHages or electric fields;
however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated
voHages to this high-impedance circuit.
This CMOS memory circuit has been
designed to meet the dc and ac specHicati9ns shown in the tables, after thermal equilibrium has been established.
This device contains circuitry that will
ensure the output devices are in High-Z
at power up.

ABSOLUTE MAXIMUM RATINGS (VoHages Referenced to VSS = VSSO = 0 V)
Rating
Power Supply VoHage

Symbol

VoHage Relative to VssNsSQ for Any
Pin Except VCC and VCCO
Output Current (per 110)

Value
-0.5to+ 7.0

Unit
V

-0.5to
VCC +0.5

V

lout
Po

±20
2.0

mA

Tbias
TA

-10.to + 85
Oto + 70

VCC
Yin, Vout

Power Dissipation (TA = 70·C)
Temperature Under Bias
Operating Temperature
Storage Temperature

W
·C
·C

·C
-55to+125
TRln
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliabilHy.

•

DC OPERATING CONDITIONS AND CHARACTERISTICS
(Vee = Veea = 5.0 V±10%, TA = Oto +70 o e, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = VSSO = 0 V)
Parameter
Supply Voltage (Operating Voltage Range)
Output Buffer Supply Voltage (5.0 V TTL Compatible)
(3.3 V 50 Q Compatible)

Symbol

Typ

Min

Max

Unit

VCC·

5.0
5.0
3.3

4.5
4.5
3.0

5.5
5.5
3.6

V
V

VCCO

Input High Voltage

VIH

Input Low Voltage

VIL

3.0
0.0

2.2
-0.5·

VCC+0.3
0.8

V
V

·VIL(min) = - 3.0 V ac (pulse width S20 ns)
DC CHARACTERISTICS
Symbol

Typ

Min

Max

Unit

Input Leakage Current (All Inputs, Yin =0 to VCC)
Output Leakage Current (G =VIH)

Parameter

Ilkolil
Ilkg(O)

-

±LO
±LO

IIA
IIA

AC Supply Current (G =VIL, lout =0 mA, All Inputs =VIL or VIH,
Cycle Time ~ tAVAV min)
VIL =0 V and VIH 2:3.0 V

ICCA12
ICCA15
ICCA20
ICCA25

310
300
290
280

Standby Current (E =VIL, E =VIH, lout =0 mA, All Inputs =VIL and VIH
VIL =0 V and VIH 2: 3.0 V
Cycle Time ~ tAVAV min)

ISB

50

Output Low VoHage (IOL = + 8.0 mAl

VOL
VOH

-

-

Output High Voltage (IOH

=- 4.0 mAl

mA

360
70

mA

0.4

V

2.4

-

V

Typ
4

Max

Unit

6
10

pF

CAPACITANCE (f = 1 0 MHz dV =3 0 V TA =25·C Periodically Sampled Rather Than 100% Tested)
Symbol

Parameter
Input Capacitance (All Pins Except 000--0015)
Input/Output CapaCitance (000-0015)

Cin
Cnul

MOTOROLA MEMORY DATA

7-250

8

pF

MCM62996

AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC - 5.0 V ±10%. Vcca = 3.3 Vor 5.0 V ±10%. TA = 0 to +70·C. Unless Otherwise Noted)
Input TIming Measurement Reference Level ............... 1.5 V
Input Pulse Levels .............•.•....•............. 0 to 3.0 V
Input Rise/Fall TIme ..................................... 3 ns

Output TIming Reference Level .......................... t.5 V
Output Load . . . . . . . . . . . . .. See Figure 1 Unless Otherwise Noted

READ CYCLE TIMING (See Notes 1. 2. 3. and 4)
Parameter
Read Cycle TImes

Symbol
tAVAV

MCM62996-12

MCM62996-15

MCM62996-20

MCM62996-25

Min

Max

Min

Max

Min

Max

Min

Max

15

-

15

-

20

-

25

-

Access TImes:
Address Valid to Output Valid
E. E "True" to Output Valid
Output Enable Low to Output Valid

tAVQV
tETQV
IaLQV

-

Output Hold from Address Change

tAXQX

4

Output Buffer Control:
E. E "True" to Output Active
GLow to Output Active
E. E "False" to Output High·Z
G High to Output High·Z

tETQX
IaLQX
tEFQZ
IaHOZ

2
2
2

2

12
12
5

-

4

2
2

2
2

9
5

-

15
15
6

-

9
6

-

4

2
0
0
0

20
20
8

-

9
9

-

4

2
2
2

2

Unit

Noles

ns

4

ns

5

25
25
10

-

ns
ns

6

-

10
10

-

Power UpTIme
ns
0
0
0
0
tETICCH
NOTES:
1. Write Enable is equal to VIH for all read cycles.
2. ET is defined by E going low coincident with or after E goes high. or E going high coincident with or after E goes low.
3. EF is defined by E going high or E going low.
4. All read cycle timing is referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E going low or E going high.
6. Transition is measured ±500 mV from steady-state vo~age with output load of Figure 1B. This parametar is sampled and not 100% tested.
At any given voltage and temperature. tEFQZ is less than tETQX and IaHQZ is less than tGLQZ for a given device.

READ CYCLE

A(ADDRESS)

E(CHIP ENABLE)

Q (DATA OUT)

G(OUTPUT
ENABLE)

(WRITE

'
MOTOROLA MEMORY DATA
7-251

..

MCM62996

WRITE CYCLE TIMING (See Notes 1, 2, 3, and 4)
Parameter
Write Cycle Times

•

Symbol
tAVAV

MCM62996-12

MCM62996-15

MCM62996-20

MCM62996-25

Min

Max

Min

Max

Min

Max

Min

Max

15

-

15

-

20

-

25

-

-

0
0
0
0
2
2

-

0
0
0
0
2
2

13
13
13
13

-

18

Setup Times:
Address Valid to End of Write
Address Valid to End of Write
Address Valid to Vii Low
Address Valid to E, E "True"
Data Valid to Vii High
Data Valid to E or E "False"
Byte Write Low to Vii High
Byte Write High to Vii Low (Abort)
Byte Write Low to E, E "False"

tAVWH
tAVEF
tAVWL
tAVET
tDVWH
tDVEF
tBWxLWH
tBWxHWL
tBWxLEF

10
10
0
0
4
6
6
0
6

Hold Times:
Vii High to Address Invalid
E, E "False" to Address Invalid
Vii High to Data Invalid
E, E "False" to Data Invalid
Vii High to Byte Write Invalid
E, E "False" to Byte Write Invalid

twHAX
tEFAX
twHDX
tEFDX
twHBWxX
tEFBWxX

0
0
0
0
2
2

Write Pulse Width:
Write Pulse Width
Write Pulse Width
Enable to End of Write
Enable to End of Write

twLWH
twLEF
tETWH
tETEF

12
12
12
12

Output Buffer Control:
Vii High to Output Valid
Vii High to Output Active
Vii Low to Output High-Z

twHOV
twHOX
twLOZ

12
5
0

-

9

13
13
0
0
6
6
6
0
6

5
0

-

-

9

15
15
0
0
8
8
8
0
8

15
15
15
15
20

5
0

-

-

9

20
20
0
0
10
10
10
0
10
0
0
0
0
2
2
20
20
20
20
25

5
0

-

10

Unit

Notes

ns

5

ns

ns

ns
8
7
7,8
ns

9
6,9

NOTES:
1. A write occurs during the overlap of ET, Vii low and BWx low. An aborted write occurs when BWx remains at VIH while Vii is low.
2. Write must be equal to VIH for all address transitions.
3. ET is defined by E going low coincident with or after E goes high, or E going high coincident with or after E goes low.
4. EF is defined by E going high or E going low.
5. All write cycle timing is referenced from the last valid address to the first transitioning address.
6. If G goes low coincident with or after Vii goes low, the output will remain in a high-impedance state.
7. If E and E goes true coincident with or after Vii goes low the output will remain in a high-impedance state.
8. If E or E goes false coincident with or before Vii goes high the output will remain in a high-impedance state.
9. Transition is measured ± 500 mV from steady-state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, twLOZ is less than twHOX for a given device.

MOTOROLA MEMORY DATA
7-252

MCM62996

WRITE CYCLE

A(ADDRESS)

E
(CHIP ENABLE)

W
(WRITE ENABLE) -'--'~"--'''->_ _ _- - I

BWx(BYTE
WRITE ENABLE)

DATA-IN

Q(DATAOUn - - - - - - - - - - - - - - - - - {

AC TEST LOADS

+5V

DO

~

255 Q

+5V

480Q

DO
85pF
(INCLUDING
SCOPE AND JIG)

~

255 Q

Figure 1A

480Q

5pF
(INCLUDING
SCOPE AND JIG)

Figure 18

ORDERING INFORMATION
(Order by Full Part Number)

Motorola Memory Prefix

_ __
MCM....JI

mB§1

' .

.EN

I

XX

L--

~

Part Number

Full Part Numbers- MCM62996FN12

MCM62996FN15

MCM62996FN20 MCM62996FN25

MOTOROLA MEMORY DATA
7-253

Speed (12 = 12 nS,15 = 15 ns, 20 = 20 ns
25=25ns)
Package (FN = PLCC)

•

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL
DATA

------------MCM101510

Product Preview
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Memories with ECl 1/0
ECl 101 K levels (ECl 100K @ - 5.2 V) Are Required
The MCM101510 is a 1,048,576 bit static random access memory organized as
1,048,576 x 1 bits. This device is fabricated using high performance Silicon-gate
BiCMOS technology. Static design eliminates the need for eX1ernal clocks or timing
strobes. This device operates with a supply voltage of - 5.2 V ± 5% yet the input and
output voltage levels are temperature compensated lOOK ECl compatible.
This device meets JEDEC standards for functionality and revolutionary pinout, and is
available in a 28 lead flatpack.

• Fast Access Times: 10, 12 ns

CASE

TBD

PIN ASSIGNMENT

BLOCK DIAGRAM

A

A
A

A

•

A

5

Vee
VEE

A
A

A

A

••

•

Q

MEMORY
MATRIX
1024 ROWS)( 1024
COLUMNS

W

A

A
A
A
A
0 ---{>-;---~rr--~----~COL~U~MN~OO~--------~C>-Q

PIN NAMES
AD-A19 •....•......•.• Address Input
~ ....................... Chip Select
W ..................... Write Enable
o ....................... Data Input
Q ..................... Data Output
VEE ........... - 5.2 V Power Supply

VCC ....................... Ground

W-----C : :;: ~ ":;:
..

50 ..

-------lj~

Figure 3b. Static Column Mode Cycle Minimum Timing

MOTOROLA MEMORY DATA
10-5

MOTOROLA

-

SEMICONDUCTOR

APPLICATION NOTE

AN987

DRAM Refresh Modes

•

DRAMs offer the lowest cost per bit of any memory, and
for that reason are enormously popular in a wide range of
applications. This low cost per bit is achieved with a very simple
bit cell design, among other things, but rooted in this simplicity
are some inherent drawbacks. One major limitation is the need
to refresh each memory bit at regular intervals. This note
discusses what refresh is, the reasons refresh is required for
DRAM operation, .and the various types of refresh available
on the Motorola 1M x 1 and 256K x 4. DRAMs. Specific commentsrefertothe 1M x 186-ns DRAM. Refer to specific device
data sheets for analogous information on other devices.
The heart of any memory device is the bit cell. A 1M DRAM
has 1,048,576 of these cells in the memory array. Each cell
holds a single bit of information in the form of a high or low
voltage, where high voltage = a binary "1" and low voltage = a
binary "0". The DRAM bit cell consists of one transistor and
one capacitor. The transistor acts as a switch, regulating when
the capacitor will charge and discharge, while the capacitor
stores a high or low voltage charge.
All capacitors leak over time, slowly losing the charge stored
in them, regardless of how carefully they are constructed.
Junction and dielectric leakage are two capacitor discharge
paths that are characteristic of the DRAM bit cell, and both
are affected by temperature. The capacitor In the bit cell can
hold a small charge, on the order of 35-125 fF (fF = 1 x 10- 15
farads). As this charge dissipates through leakage paths, the
small difference between a "1" and a "0" diminishes. If nothing
is done to restore the charge on the capacitor to its initial
value, the sensing circuitry on the DRAM will eventually be
unable to datect a charge difference and will read the cell as
a "0".
Thus, all the capacitors in the memory array must be periodically recharged, or refreshed. Refresh is accomplished by
accessing each row in the array, one row at a time. When a
row is accessed, it is turned on, and voltage is applied to the
row, recharging each capacitor on the row to its initial value.
Specified refresh time o.n the 1M x 1 DRAM is 8 milliseconds;
every row must be recharged every 8 milliseconds. This is a
vast improvement over refresh times required for earlier generations of DRAMs. The 16K x 1 DRAM required refresh every
2 milliseconds, the 256K x 1 DRAM requires a refresh every 4
milliseconds. Longer refresh times mean more time available
for access to memory, and less time required to refresh the
device.
Design and operation of the DRAM allow only one row to
be refreshed at a time; 512 refresh cycles are required to refresh
the entire 1M x 1 memory array. The array is actually 1024
rows by 1024 columns, but it operates electrically like two half
arraya of 512 rows by 1024 columns. During refresh, every row
is treated as if it runs through both halves of the array, refreshing 2048 column locations (bit cells) per row. This design
results in fewer refresh cycles required to recharge the entire
array, since only 512 rows need to be accessed, rather than
1024.

Refresh can be performed in eithar a single burst of 512
consecutive refresh cycles (one cycle per row) every 8 milliseconds, or distributed over time, one refresh cycle every 15
microseconds (8 milliseconds per 512 rows=15.6 microseconds per row) on avarage, or some combination of these two
extremes. As long as every row is refreshed within 8 milliseconds, the actual method used is best determined by syatam
use of the DRAM. The burst takas 84 microseconds to complete (165 nanoseconds per row x 512 rows for 85 nanoseconc!s
per device). During this burst refresh time, no memory operations can be performed on the device. Distributed refresh
disables memory access for 165 nanoseconds every 15
microseconds.
The 1M x 1 DRAM can be refreshed in three waya: RAS
only refresh, CAS before RAS refresh, and hidden refresh. In
addition, any normal read or write refreshes all 2048 bit cells
on the row accessed. Regardless of the refresh method used,
the time required to refresh one row is the random read or
write (RAS) cycle time (tRc). When operating tha device in
page, nibble, or static column mode, only the row being accessed is refreshed. The device must be in normal random
mode to utilize any of these specific refresh methods.
RAS only refresh requires external row counters, to ensure
all rows are refreshed within the specified time, and externallysupplied row addresses. CAS before RAS relies on internal
row counters and internally generates the address of the next
row to be refreshed. Hidden refresh is a variation on CAS
before RAS refresh that holds vl!lid data at the output while
refresh is occurring. Whenever the device is in a refresh cycle,
neither a read nor a write operation can be performed. Hidden
refresh allows the device to be read ahead of refresh, then
holds the valid data at the output while refresh cycles are in
progress. It appears that the refresh is hidden among data
cycles because valid data is maintained at the output.
RAS only refresh is performed by supplying row addresses
AO-AS and completing a RAS cycle (tRC); switching RAS
from inactive (high) to active (low), holding RAS low (tRAS),
then switching back to high, and holding RAS high (tRP). A9
is ignored during RAS only refresh, since this address normally
determines which half of the array is to be accessed. CAS
must be held high through this RAS cycle, hence the name
RAS only refresh. An external row counter is required for this
refresh method. See Figure 1.
CAS before RAS refresh is performed by switching CAS
from high to low while RAS is high, then switching RAS low
(tCSR). This revarsal of the usual clock order activates an
internal row counter that generates addresses to be refreshed;
external addresses are ignored in this cycle. CAS must be held
low (tCHR) after liAS' transitions to low. After that time it can
either be held low or switched to high. See Figure 2. The CAS
before RAS refresh counter test, specified on all DRAM data
sheets that offer this typa of refresh, is used to check for
proper operation of the internal row counters and correct address generation.

MOTOROLA MEMORY DATA
10-6

DRAM REFRESH MODES (AN987)

method of refresh allows refresh cycles to be mixed within
read and write cycles. During the refresh cycle, a write operation cannot be perfonned. See Figure 3.
Refresh is an integral and necessary part of DRAM operation. Substantial improvement has been made in increasing
the time between refresh cycles, but as long as the bit cell
design utilizes a capacitor, periodic recharging will be required.
Threa methods of refresh are available on the 1M x 1 DRAM:
RAS only, CAS before RAS, and hidden refresh. The Motorola
1M x 1 and 256K x 4 will work in virtually all systems as a result
of flexibility provided by this assortment of refresh methods.

Hidden refresh is a CAS before RAS refresh that has been
initiated during a read or write operation. At the end of a
typical read cycle, CAS would be switched to high before RAS,
turning off the output. In a hidden refresh cycle, RAS is
switched to high, concluding the RAS cycle (tRC), while CAS
is held low. RAS is held high (tRP), then switched low, beginning another RAS cycle. As long es CAS is held low, data
is valid at the output, resulting in a long read cycle. Since data
can be read while the device is being refreshed, the refresh
operation(s) appears to be hidden by the read cycle. The same
refresh can be performed attar a write cycle is Initiated. This

~14-:.-=-_-=-=-_-=-=-_-_IftAS=_-t_RC-=-:=-=,--.j.-JF-IRP---:-:l~l

H-

HAS
l-

H-

eAl
l-

:=00<_.::AD:::~::::::::SS::""J

AD-AS

Figure 1. RAS Only Refresh Cycle

H-

HAS

lH-

eAl

lH

n IOATA DUn

)

l-

HIGH Z

Figure 2. CAS Before RAS Refresh Cycle

MEMORY
liAS

REfRESH

CYClE~

H- ~

CYCLE~

REFRESH
CYCLE

L-

m

H
l-

H-

n IDATA DUTI
l-

I
\.

VALID DATA OUT

tRC

IRc

Figure 3. Hidden Refresh Cycle

tRC

} r-

II

/

MOTOROLA MEMORY DATA
10-7

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN1124

1 Meg to 4 Meg DRAM Upgrading
Prepared by: Paul Oats
4 Meg DRAM Product Engineering
Austin, Texas

mode. Figure 1 shows the CAS-Before-RAS Refresh timing for
the 4 Meg DRAM, and Figure 2 shows the test mode entry timing. The test mode is exited by performing either a RAS-Only
Refresh cycle or a CAS-Before-RAS Refresh cycle. Test mode
on the 1 Meg DRAM is entered through use of a "supervoltage"
on a separate test function pin, and is therefore completely unlike the 4 Meg test mode entry.

INTRODUCTION
Standards set through JEDEC and EIAJ allow upward compatibility from the 1 Meg to 4 Meg DRAM by using the same pinoutlor SOJ and ZIP packages. Such standards are setto ensure
a stable DRAM supply when higher density memories are introduced. This eliminates the need for expensive redesigns of systems that can utilize the new memories.
Although the common pinout between the 1 Meg and 4 Meg
DRAM requires little, if any, relayoutofthe PCB, caution must be
exercised when upgrading because of potential incompatibilities with refresh and power up. Both of these involve differences
in test mode entry between the 1 Meg and 4 Meg DRAM.

POWER UP
Another potential incompatibility between the 1 Meg and
4 Meg DRAM occurs during the power up, and this must be addressed when upgrading. Both devices require a pause of
200 IJ.S after power up, followed by 8 RAS cycles before proper
device operation is guaranteed. The pause allows the internal
substrate generator to establish the correct bias voltage. The 8
RAS cycles initialize all dynamic nodes within the RAM.
To prevent the 4 Meg DRAM from entering the test mode, the
8 RAS cycles should be RAS-Only Refresh cycles or CASBefore-RAS Refresh cycles. If these refresh modes are not
used, the device could power up in the test mode, which can only
be exited by performing a RAS-Only Refresh cycle or a CASBefore-RAS Refresh cycle.

REFRESH
The dynamic memory cell is based on capacitor charge storage for each bit in the array. This charge will dissipate over time,
so the entire array must be periodically refreshed to maintain the
correct bit state. This is accomplished by cycling through all the
rows of the array within a specified refresh time.
The 4 Meg DRAM has 1024 rows instead of the 1 Meg's 512
rows. Since the refresh period of the 4 Meg is twice that of the
1 Meg DRAM, the equivalent wait state olthe 4 Meg is the same
as that of the 1 Meg. This is summarized in Table 1.
As with the 1 Meg DRAM, the 4 Meg DRAM can be refreshed
through a variety of ways:.any read or write cycle, a RAS-Only
Refresh, a CAS-Before-RAS Refresh, or a Hidden Refresh. A
potential incompatibility between the 1 Meg and 4 Meg DRAM
exists with the use of the CAS-Before-RAS Refresh.
On the 1 Meg DRAM, the Wpin is specified as a don't care
during the CAS-Before-RAS Refresh. But on the 4 Meg DRAM,
the W pin must be high (disabled) for time twRP before RAS
goes low and held high for time tWRH after the transition. This
will prevent the device from entering the JEDEC standard test

SUMMARY
Upgrading a system from a 1 Meg DRAM to a 4 Meg DRAM is
easily accomplished if a few precautions are taken. The CASBefore-RAS Refresh mode on the 4 Meg DRAM requires that W
be high during the RAS low transition. If Wis a don't care, as on
the 1 Meg DRAM, the test mode could inadvertently be entered.
Caution with the 4 Meg DRAM mustaiso be exercised during the
power up. The 8 initialization cycles should be either RAS-Only
Refresh cycles or CAS-Before-RAS Refresh cycles, so that the
device 'comes up in its normal operating mode and not in the test
mode.

Table 1. Comparison of Refresh Requirements for the 4 Meg and 1 Meg DRAM
(TImes Shown are for Devices with 70 ns Random Access Timas)
1 Meg

4 Meg
Normal Power

Low Power

Normal Power

Number of Rows

1024

1024

512

Low Power
512

Number of Bits per Row

4096

4096

2048

2048

Refresh Period (tRFSH)

16ms

128ms

8ms

64ms

Distributed Refresh Period

15.61's

124.811S

15.61's

124.811S

Burst Refresh Period

16ms

128ms

8ms

64ms

lime to Refresh 1 Row (tRC>

130ns

130ns

130 ns

130ns

Cumulative lime to Refresh the Entire Array

133.1I's

133.1 I1S

66.611S

66.61's

Refresh lime/Operating lime

0.833%

0.104%

0.833%

0.104%

MOTOROLA MEMORY DATA

10-8

1 Meg to 4 Meg DRAM Upgrading (AN1124)

~------------------tRC----------------------~
~------------t

RAS ------------~

__ VIH -

RAS V

IL -

HIGHZ

Figure 1. CAS-Before-RAS Refresh Timing for the 4 Meg DRAM
(Addresses and G are Don't Care)

~----------------~----------

tRAS

tRC

------------------~

---------4~

r---------~

CAS VIH

r---------~

- -r-,.....-:~:__--_1

V IL -

W VIH VIL -~~~~~~~----------~~~~~~~~~~~~~~~~~~~~
DATA OUT VOH -

________________________ HIGH Z _______________________

VOL-----"'I

Figure 2. Test Mode Entry Timing for the 4 Meg DRAM

MOTOROLA MEMORY DATA
10-9

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN1202

Battery Backup of Self Refreshing Dynamic
Random Access Memory
Prepared by: Paul A. Oats, 4Meg DRAM Products, Motorola Microprocessor and Memory Technologies Group
John P. Hansen, M68000 Products, Motorola Microprocessor and Memory Technology Group
Paul J. Polansky, formerly of Motorola High-End Microprocessor Division, currently in Motorola
Austin Intellectual Property Department

INTRODUCTION
In today's information dependent society, the need for maintaining the integrity of data and program status during a power
outage is becoming increasingly important. Even though data
flies may be stored frequently during a session, in the event of a
power failure, any changes since the last save would be lost,
and the program would have to initialize, reloading the required
data. In applications where the loss of data would be costly in
terms of dollars and time spent re-entering data, the use of battery backup circuits in conjunction with robust software can ensure that a power failure would be at most an annoying delay,
requiring no user intervention upon the restoration of power.

SELF REFRESHING DYNAMIC RANDOM
ACCESS MEMORY
In the past, the best protection of volatile random access
memory (RAM) data against a power loss was provided through
the use of static RAMs (SRAMs) in the memory array because
of the ease of interfacing with the rest of the system. SRAMs require none of the complex cycle and power consuming refresh
circuitry associated with dynamic RAMs (DRAMs), because of
their direct addressing and static cell. This has now changed
with the introduction of Motorola's newest very low power
512Kx8 DRAM, the MCM5V4800A. Use of self refreshing
DRAMs allows battery backup of an increased memory size for
a comparable dollar cost.

In addition to the usual methods of DRAM refresh (any read
or write cycle, a RAS-Only Refresh, a CAS-Before-RAS Refresh, or a Hidden Refresh), the MCM5V4800A also incorporates a self refresh operation, previously only found on pseudo
static RAMs (PSRAMs). This self refresh feature removes the
need to have the DRAM control circuitry on the battery backup
node, and is expected to be a standard feature on future generations of DRAMs.
The self refresh operation is entered just as a normal CASBefore-RAS refresh, but CAS and RAS are held low for a period
greater than tRASS min (>1 00 ~), as shown in Figure 1. After
this time, the DRAMs internal timer starts, and a new row is refreshed approximately every 130 ~. When the refresh pulse is
generated by the internal timer, the ICC current may peak to 120
rnA, but the current ICCS during the self refresh is guaranteed to
be a maximum of 200 !lA, as shown in Figure 2.
The MCM5V4800A CMOS processing makes it particularly
well suited for use in battery backup systems because of the inherent advantages of CMOS technology: superior noise immunity, faster switching speeds, low standby power dissipation,
and a wide operating range.
For battery backup applications, chief among these advantages is the low standby power dissipation. Due to the series
connection of P and N channel devices in CMOS designs, current is only drawn during switching. Thus, when the DRAM is in
the self refresh mode, the only current drawn is due to surface,
junction, and channel leakage and the operation of the internal
refresh timer.

t---------tRASS-----.-!

CAS VIH -

V1L -

OQO-DQ7 VOH )>-------------OPEN-------------VOL- _ _ _ _.....J.

B

NOTE: Din, W, G, AO...A8, A9R = "H" or "L"

Figure 1. CA5-Before-RAS Refresh Cycle for the MCM5V4800A

MOTOROLA MEMORY DATA
10-10

"H"or"L"

BATTERY BACKUP OF SELF REFRESHING DRAM (AN1202)

..

SELF REFRESH PERIOD

100 1J.S-150 IJ.S

120mAIJI

r

PEAK

CURREONT
REFRESH

REFRESH

Figure 2. Power Supply Current of the MCM5V4800A During Self Refresh
Pull-down resistors should be placed on the CAS and RAS
pins to ensure that the DRAM stays in the self refresh mode
during the battery backup period. All other pins (addresses,
data inputs/outputs, output enable, and write enable) should
use pull-ups or pull-downs so that they do not float, creating
undesirable current paths that would shorten battery life and
possibly destroy data. [The use of pull-up and pull-down resistors to terminate each transmission line in the memory's bus
is a wise practice with many inherent advantages. This topic
is discussed in more detail in Motorola Application Notes
AN971 and AN973. Although these notes specifically address
Fast Static RAM applications, the principals can generally be
applied to all volatile memories.]

BATTERY BACKUP CIRCUIT
The battery backup circuit is one of the key components of
the system. Its function is to supply power to the memory array,
processor, and power failure detection circuit during a power
failure. This is usually accomplished through the use of the
trickle charge circuit illustrated in Figure 3, although numerous
variations on this circuit exist. System interconnects are not
shown in order to clarify the power connections.
In this circuit, diode D1 isolates the battery El from all but
the system's RAM array, processor, and power failure detection circuit when the DC power supply has failed. The processor and power failure detection circuit must also have the battery backup in order to detect when the main power is restored
and to keep track of whether the system is in the battery backup mode or normal operating mode. When the DC power supply is active, diode D2 and current limiting resistor R1 allow a
small amount of current to be diverted into recharging the battery. If a non-rechargeable battery is used, resistor R1 can be
eliminated. In order to prevent the battery from discharging
during a scheduled power shutdown, a switch should be in series with the battery so that the backup circuit is disconnected
when the system is deliberately powered off after all critical
data has been written to some less volatile storage medium
(e.g., floppy disk, hard disk, tape).

BATTERY BACK-UP SYSTEM REQUIREMENTS
It is desirable after the occurrence of a power failure to be
able to recover after power is restored and resume operation
as if only a delay had occurred. This process is called fault recovery. Figure 3 shows the DC power bus for a system utilizing
a low power processor, such as Motorola's MC68300-family
of processors.
Note that besides the memory array, the processor and
power failure detection circuit are also on the battery backup
node. The MC68300-family is capable of low power standby
necessary for battery backup operation. Having a low power
processor greatly simplifies the circuitry and software required
for fault recovery, in that the processor itself can now store
internal registers and keep track of the power state, without the
need of external control logic comprising a finite state
machine.

VCC

1

I
DC
POWER
SUPPLY

I

MEMORY
CONTROL
CIRCUITS

Vss

1

POWER FAILURE DETECTION CIRCUIT
The function of the power failure detection circuit is to monitor the AC power source. If the main power fails, this circuit
generates an ACFAIL interrupt signal to the processor, which
will store its internal status and put the memory in the self

BACKUP CIRCUIT
; "'01"'BATTERY
..........................................
..
,
,
,
,
,
,
,
,,,
,
Rl
~
,,
,
,
,
,
,
V(BATT) :
,
,,
,
,
,
,
,
,
El
,
,
,,
,

vcc (RAM)

02

,

T

I

J
MPU

RANDOM
ACCESS
MEMORY
ARRAY

POWER
FAILURE
DETECTION
CIRCUIT
/

1

Figure 3. DC Power Bus for Complete System Showing the Process, Memory Array, and Power
Failure Detection Circuit on the Battery Backup Node

MOTOROLA MEMORY DATA
10-11

I

•

BAlTERY BACKUP OF SELF REFRESHING DRAM (AN1202)

SOFTWARE CONSIDERATIONS

refresh mode_ Because of the urgency necessitated in the
event of a power failure, the signal issued to the processor in
such an event is a non-maskable interrupt (NMI) olthe highest
priority_
Just as with the battery backup circuit, a wide variety of circuits exist for power failure detection_ A simple power failure
detection circuit is shown in Figure 4. It is recommended that
the signal from the power supply into the power failure detection circuit be drawn from a separate winding of the transformer than that going to VCC. This will avoid possible interference with the voltage regulation of the system.
In this circuit, the zener diode provides the reference level
to the Schmitt trigger inverter which fires if the AC power drops
below acertain threshold. Resistor Rl and the zener reference
voltage V(REF) should be chosen so thatthere is enough margin to the minimum system operating voltage for the power fail
code to complete processing before the power loss propagates through the DC power supply, and VCC falls below the
system operating voltage. This margin must be greater than
the execution time of the power fail code, which is on the order
of 151!s for the code illustrated in the following section. Concerns about this propagation delay can be dispelled through
the use of an uninterruptable power supplies (UPS), which can
provide system power for a short time. An R-C network may
also be included in parallel with the zener diode to prevent system shutdown if the AC power source goes down for only a few
cycles. The trigger will then only fire if the power fails for more
than a time constant. The hysteresis of the Schmitt trigger supplies additional margin.
Since the power failure detection circuit must continue to
function during a power failure, its components need to have
an operating range from the backup battery voltage to the normal system operating voltage and should also be of low power
to minimize battery drain. Motorola's high performance
Schmitt trigger inverter, the MC74HC9014 fulfills these
requirements. If a high-to-Iow transition is required for the processor to begin the battery backup sequence, then a noninverting Schmitt trigger should be used, such as the
MC74HC9015.

The system's operating software must include code to
accomplish the fault recovery process. From the standpoint of
the processor it is essential to save enough information to be
able to return to the same point in program execution when
power is restored. With the advent of components with low
power standby modes, not only can essential data be saved,
but also all variables and parameters may be recovered on
return to normal operation.
Upon receipt of the ACFAIL signal from the power failure
detection circuit, the processor will prepare the system for the
battery backup operation. A low power processor from the
MC68300-family will store its registers internally, send the
memory array into the self refresh mode, and make note that
the system is now in the standby mode. Additional power can
be saved by disabling circuitry that will be unused during the
backup operation, such as the periodic interrupt timer, voltage
controlled oscillator (VCO), and phase-locked loop (PLL).
Upon restoration of power, the ACFAIL signal is reset and
the processor begins the fault recovery process. After the internal status of the processor is restored and the power to the
external logic (especially the memory control circuits) reaches
an operational level, the memory array can then return to the
normal operating state. It is prudent to perform a refresh of the
memory array as a part of the fault recovery process in order
to assure that no refresh parameters are violated.
As system complexity grows (for example when an operating system is being used) more complex measures must be
taken to ensure proper fault recovery than if all software is written in assembly language. When the ACFAIL is detected, the
operating system must shut down active processes and close
files in an orderly fashion for full recovery after power is restored. In a likewise fashion, systems which implement some
functions of operating systems like multitasking and scheduling, or access files on permanent storage devices, must close
those processes or files to ensure proper recovery after the
fault is repaired. The shutdown software must also keep a record of the status of the processes and files before the fault so

VCC(RAM)

VCC

~

DC
POWER
SUPPLY

DC FROM
SEPARATE WINDING
THANVCC

BATIERY
BACK-UP
CIRCUIT

~

74HC90t4
Rt

V(REF)

.....

'"

friV

AC FAIL

ALL GROUNDS ARE
SYSTEMS V5S

Figure 4_ A Simple Power Failure Detection Circuit
(Note that the Schmitt trigger is also powered by the backup battery when· the main power Is down_)

MOTOROLA MEMORY DATA
10-12

BATTERY BACKUP OF SELF REFRESHING DRAM (AN1202)

they can be reopened on recovery. Consideration of the software or firmware necessary for such tasks is beyond the
scope of this paper, but the user must nonetheless take them
into account.
MOVEM.L

AO-A7, DO-D7, FAILREGS

MOVE.W
MOVE.L
MOVE.L
RESET
STOP

SR,FAILSR
USP,AO
AO, FAILUSP

The code to perform a simple fault recovery for the
MC68xxx-family of processors follows. On reception of a power failure interrupt, the processor should execute, at a minimum, code similar to the following:
Save regular registers and supervisor
stack pointer. Note that the number of
registers may vary depending on the
type of processor being used.
Save status register.
Get user stack pointer
and now save it.
Reset all system peripherals.
The CPU is now waiting to be reset
for the duration of the power failure.

When the AC fault disappears, the fault recovery routine should contain code at the end of the routine similar to the following:
TAS

BEQ
MOVE.L
MOVE.L
MOVE.W
MOVEM.L
RTE

JMP

FAILSAVE

JMP
FAILUSP,AO
AO, usp

FAILSR,SR
FAILREGS,AO-A7,DO-D7

CLR . W F AILSAVE

Get value of state register and clear it through
an indivisible read-modify-write cycle, while
setting the Z bit of the CCR.
Skip if OK.
Load user stack pointer
and put in register.
Reload status register.
Reloading the registers causes the CPU to
reload the stack frame that was saved on the
power fail interrupt; program execution
continues as if no fault occurred.
Clear semaphore in state register and continue
power up code.

It should be noted that the above code is generic to the
MC68xxx-family, and the number of internal status registers
may vary. A low power processor from the MC68300-family
can greatly simplify this code and shorten execution time,
since it can store the status registers internally and initiate a
low power stop.

all variables and parameters may be recovered and the system returned to normal operation.
For a system to accomplish a fault recovery, additional circuitry is required beyond that of a system with no backup. A
battery backup circuit switches between the main power and
the battery; a power failure detection circuit senses a power
loss and initiates the interruptto the processor to send the system into the standby mode. The power failure detection circuit
and processor must also be powered by the backup battery
during a fault.
A wide variety of circuits exist for these additional requirements, and this paper has touched on only a few. As battery
backup systems become more common, vendors are responding by including many of these requirements in their systems. For example, the VME bus specification defines an implementation of power failure detection. In the event that the
power supply used in an application does not include the circuitry for battery backup operation, the required components
can be obtained through Motorola.

SUMMARY
When critical data is being stored in a volatile RAM array,
it is important to retain that data in the event of a power failure
by having the RAM powered by a backup battery. It is also desirable after the occurrence of a power failure to be able to recover after power is restored through the process of fault
recovery. From the standpoint of the processor it is essential
to save enough information to be able to return to the same
point in program execution when power is restored. With the
advent of self refreshing DRAMs and processors with low
power standby, not only can essential data be saved, but also

MOTOROLA MEMORY DATA
10-13

MOTOROLA

-

SEMICONDUCTOR

APPLICATION NOTE

AN971

Avoiding Bus Contention in Fast Access
RAM Designs
INTRODUCTION

REV1

SWITCHING FROM A READ TO WRITE MODE
With E low (device selected), on the falling edge of IN (write
asserted) the RAM output driver begins to turn off (highimpedance state). Depending on the input and output logic
levels, if sufficient time is not allowed for the output to fully
turn off before an input driver turns on, bus contention will
occur (see Figure 2a).
Figure 2a shows an example of a RAM trying to drive a bus
line low while an input driver is trying to drive the line high.
If the situation were reversed (RAM output high and the input
driver low), bus contention would still exist.
Of course the obvious way to avoid this type of bus contention is to make sure that the input buffer is not enabled
until the write low to output high-impedance (twLOZ) time is
satisfied (see Figure 2b). This specification is usually given on
most manufacturers' data sheets.
Another method to eliminate bus contention would be to
use E to deselect the RAM before asserting IN (low). This
allows the RAM output extra time to go into high-impedance
state before the input driver is enabled. E and IN are later
asserted low to begin a write cycle (see Figure 2c).

When designing a bus oriented system, the possibility of
bus contention must be taken into consideration. Bus contention occurs when two or more devices try to output opposite
logic levels on the same common bus line.
This application note points out common causes of bus
contention when designing with fast static random access
memories and describes ways to eliminate or reduce
contention.

WHAT CAUSES BUS CONTENTION?
The most common form of bus contention occurs when
one device has not completely turned off (output in a highimpedance state) before another device is tumed on (output
active). Basically, contention is a timing overlap problem that
results in large, transient current spikes. These large current
spikes not only generate system noise, but can also affect the
long tarm reliability of the devices on the bus (see Figure 1).

BUS CONTENTION AND FAST STATIC RAMs
SWITCHING FROM A WRITE TO A READ MODE
With E set low (device selected), on the rising edge of IN
(write terminated) the address or data-in changes before the
device has had a chance to tarminate the write mode. If this
should occur, and depending on the input and output logic
levels, a bus contention situation could exist (see Figure 3).
To avoid address changing type bus contantion requires that
the address not change till the writa recovery specification
(twHAX) is satisfied. To avoid bus contention caused by data
changing requires that the data-in remains stable for the duration of the data hold specification (twHDX). Most of

Since memory devices are primarily used in bus oriented
systems, care must be taken to avoid bus contention in memory designs. Fast static RAMs with common I/O data lines (or
any high frequency device with common I/O pins) are the
most likely candidates to encounter bus contention. This is
due to the tight timing requirements that are needed to achieve
high-speed operation. If timing control is not well maintained,
bus contention will occur. The most common form of bus
contention for memories occurs when switching from a read
mode to a write mode or vice versa.

1 OF 4 DATA BUS LINES
D1/Ol

RAM WITH
COMMON DATA
I/O

D2/02
D3/03

04/04

a

IHI

TO INTERNAL
CIRCUITRY

if III
Figure 1. Common 110

BUB

Contention

MOTOROLA MEMORY DATA
1()'14

AVOIDING BUS CONTENTION . .. (AN971)

L ______________________
EH

ADDRESS
H

RA:
t-twLOZ-l fll
OUTPUT L _ _ _ _ _ _ _ _-'r__

WL

_ _ _;;;fll~_~1

INPUT
DRIVER

RAM H
OUTPUT L

BUS
LINE

'----

INPUT H
DRIVER L

I--

BUS CONTENTlON....j

-....!~::::::~C~~:)

BUS

FIgure 2a. Input Driver Enebled Prior to Disabling
RAM Output

Figure 3&. Data Setup Time Violation

! H

EH

L
H
WL

ADDRESS H - - - - - - - - - - - - - - - - -

RAM H
OUTPUT L
INPUT H
DRIVER L
BUS H
LINE L

W
______-=fll______

H

L

~r__

RAM H
OUTPUT L

----~~
- N O CONTENTION-

-1=""=j
< ---1
(Zl

INPUT H
DRIVER L

VALID

BUS

Figura 2b. Input Drivar Disabled Prior to Enabling
RAM Output

X,.....:.--INVALID

§W4

BUS CONTENTION

Figure 3b. Data Hold Time Violation

EH
L

_ H

WH

EL

L

H
WL

(Zl

RAM H
OUTPUT L
INPUT H
DRIVER L
BUS H
LINE L

Figure 2c. Using

RAM H
OUTPUT L

fll

E to Avoid

:.

fll

I+I£HDX~

''---

Bus Contention
Figure 3c. Using

Motorola's fast static RAMs specify write recovery and data
hold times of 0 ns. However, it is always a good practice to
allow seme margin to take care of possible race conditions.
Both of these types of contention could alse be avoided by
taking E high prior to taking IN high. This will give the RAM
output driver time to go to a high-impedance state before IN
goes high. In this case E is used to terminate the write cycle
instead of IN (see Figure 3c1.

E to Avoid Bus Contention

OTHER WAYS TO ELIMINATE BUS CONTENTION
If the RAM has an output enable pin (GI, synchronizing
schemes can be incorporated to help eliminate bus conteAtion.
Taking G high will ensure that even when the RAM is in a read
mode the output will be in a high-impedance state. This will
allow the input driver to be enabled longer.

MOTOROLA MEMORY DATA
10-15

AVOIDING BUS CONTENTION . .. (AN971)

r-------- -----,
I

TO
INTERNAL
CIRCUITRY

I

I
I
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ADDRESS

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MCM6164

RIWI-----.:;:.!....------.H

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MC6S000
Figure 48. Using

G to Avoid

Figure 4b. Timing Diagram of the MC68000

Bus Contention

Most advanced microprocessors, such as the MC68000 and
MC68020, have asynchronous bus control signals that take
advantage of fast memory devices with output enable pins.
Figure 4 shows one way to avoid bus contention using a
Motorola MC68000 interlaced to a Motorola 46-ns MCM6164.
A more obvious way to eliminate bus contention is to use
slow memory devices. Slow memories have loose timing requirements that allow devices to fully turn off before another
device turns on. Of course this defeats the whole purpose of
fast static memory devices.
Another obvious way to eliminate bus contention is to use
memory devices that have separate data I/O pins. In this way
the R/W signal from the microprocessor can control a buffer
device to eliminate bus contention (see Figure 5). However,
the industry is demanding RAM with common I/O because
these devices cost less and save system real estate.
Common I/O devices reduce package size since fewer pins
are needed. Smaller packages result in less PCB space re'
quirement. Common I/O devices also eliminate the need for

an extra buffer with its associated expense and space requirement. In general fast static RAMs configured greater than a
XI will have common data I/O pins.
Another popular way to reduce bus contention is to put a
current limiting series resistor on each bus line (see Figure 6).
The series resistor does not eliminate bus contention, but it
helps reduce the large transient currants associated with bus
contention. However, series resistors increase access time as
well as increasing component count. The added access time
depends on the total bus capacitance (including the capacitance of the devices on the bus) and the total bus resistance.
The added delay should be added on to the point at which
bus contention ceases. The following formulas can be used
to determine the added access delay.
R C I Vin(initiaJ) - Vin(finaJ)
tHL = L· L· n VILlmax) _ Vln(finaJ)
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01

02

02

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RAM

03 ~------'
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Figure 5. Seperate I/O Buffer

Figure 6. Using Series Terminating Resistors

MOTOROLA MEMORY DATA
10-16

AVOIDING BUS CONTENTION . .. (AN971)

Generally the value of the resistor should be around 100
ohms. The larger the resistor the less the transient current
generated, but the greater the delay. Using a 150-ohm resistor
will limit the current flow to less than 20 milliamperes while
adding approximately 3 nanoseconds extra access time. However, note that even with series resistors bus contention duty
cycle must be minimized to reduce EMI and bus ringing.
Although it is very important to reduce bus contention,
CMOS memories can tolerate more bus noise generated by
bus contention than can bipolar memories, due to the excellent
noise immunity advantege of CMOS ovar bipolar technology.
However, even when using CMOS memories, large destructive
transient currents generated by bus contention can still occur.

CONCLUSION
Bus contention must be taken into consideration in most
bus-oriented system design. The occurrence of bus contention
generates large transient currents that produce system noise
and could also affect the system's long term reliability.
Fast random access memories with common data 1/ 0 pins
are very susceptible to bus contention due to tight timing
requirements. Although it is almost impossible to totally eliminate bus contention, it must be the goal of the system designer
to minimize bus contention.

MOTOROLA MEMORY DATA
10-17

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN973

Avoiding Data Errors with Fast Static RAMs
Microprocessors are now capable of 20-25 MHz. This places
a great demand on SRAMs to supply super-fast access times.
Todey's sub-loa-nanosecond SRAMs in production are rapidly
moving to sub-50 nanoseconds as yesterday's prototypes ramp
into production, and sub-25 nanoseconds is just on the horizon. This need for high-speed SRAMs is amplified by the
fact that setup, hold times, and cycle edge accuracies do not
usually improve at the same rate as the clock frequency. There
is help on the way in terms of application specifiC SRAMs that
put on chip some of the "glue" features that eliminate gate
delays caused by decoders, drivers, or clock signals; but for
now, the main burden will fall upon SRAM designers to make
up for the "lost time" in the shorter cycles. Some of the tools
of the SRAM designer are improved processes, tighter design
rules, and improved circuit techniques such as address transition detection. When you combine all of these features into
a high performance SRAM, you no longer have the bistable
flip-flop of yesterday but a highly tuned circuit that is more
closely related to a DRAM. This is where the system designer
can help. Although SRAM designers are doing everything
possible to make the devices stable and noise immune, there
is no substitute for a good solid system layout and design.
The following discussion gives system designers some insight
into potential trouble areas from a component engineering
viewpoint.

Since an unterminated bus looks almost entirely like a capacitive load, the larger the resistor value the slower the rate
at which data can be presented to the receiving device. This
is due to' the time it takes to charge and discharge this capacitive line through the termination resistor. If a small value
resistor is used, the charging/discharging time delay can be
minimized (t = Re). However, the smaller the resistor the
greater the power consumption through the resistor. Also, if
the resistor value is too small, its value will approach that of
the source resistance of the transmitting device, which could
lead to a degradation of noise margin to the receiving devices.
A resistor value between 1 kilohm and 10 kilohms is usually
adequate. The actual value should be optimized through experimentation (see Figure 1).

Vcc
AD

RX

MC68020

MEMORY
BOARD

A1

• •
• •
AN

RX

CHARACTERISTICS OF HIGH-SPEED BUSES

II

When dete is transmitted over long distances, the line on
which the data travels has to be considered a transmission
line. A long distance is relative to the rate at which data is
being toggled. Address and data buses associated with highthroughput microprocessors (e.g .• M68000 family) must also
be thought of as transmission lines, since it is not uncommon
for these processors to run bus cycles of 4O-nanosecond periods or less.
Other features of high-end microprocessor buses are that
they tend to operate in harsh, noisy-type environments, and
most of these buses are ul'lterminated. A high-impedance,
unterminated bus line acts just like an antenna. It not only
radiates EMI, it can also receive EMI, This can result in bus
ringing, crosstalk, and various other noise associated problems. The more transmission lines a bus has, the more antennas to pick up and radiate noise. Of course, the best way
to reduce this EMI is to ensure that the bus is properly terminated into a low-impedance load. This low-impedance load
could be in the form of a pull-up or pull-down resistor tied to
each bus line. Ideally, the termination resistor should be equal
to the characteristic impedance of the bus line. A transmission
line terminated into its own characteristic impedance has the
best incident wave switching as well as the least amount of
reflection.

Figure 1. Microprocessor Address Bus with Pull-Up
Reaistors

HIGH SPEED SRAM DESIGN TECHNIQUES
In order to speed up access times of high-speed RAMs,
many new design techniques have surfaced. One of the most
innovative techniques to emerge is known as address transition
detection (ATD) circuitry. Since row address access times are
typically slower than column address access times, this circuitry originally used the row addresses to trigger a clocking
sequence that restored bit lines, shorted data lines, equalized
sense amplifiers, and threestated the output as the output
buffers were equalized. This meant that many of the internal
transistions could be completed by the time that the signals
were decoded and propagated through the device seeking the
proper cell and outputting data. This then made row and column access times much more equal and eliminated one of the
speed bottlenecks. This scheme also has the added advantage
of reducing power consumption because the static bit line
loads can be reduced in size by utilizing a parallel equalization
that is also generated at the ATD initiation and used to pull
up the bit line 0 before selection of the new word line. Since

MOTOROLA MEMORY DATA
10-18

AVOIDING DATA ERRORS . .. (AN973)

START EQUALIZATION
OF TOP OF CHIP

EQUALIZE BIT LINES

TURNS WORD OFF

START EQUALIZATION
OF BOTTOM OF CHIP

EQUALIZE SENSE AMP

EQUALIZE DATA LINES

TURNS OUTPUT OFF

TURNS SENSE AMP OFF

Figure 2. Address Trensition Detection Timing Chain
its inception, ATD has been expanded and is now activated
by all addresses and chip select pins instead of just row addresses. A typical timing chain, as shown in Figure 2, applies
to Motorola's MCM6164 8K x 8 SRAM and exemplifies the
clock sequence dependency.
ATD has been shown to be very effective as a performance
enhancer and will remain a valuable tool for designers, but it
can be seen that we now essentially have a clock-activated
part. What happens if addresses are floated or oscillate at a
frequency greater than the ATD response7 What happens if
addresses are skewed, thereby getting successive ATD initiations7 There is also the case of signals being gated from
numerous sources, in which the address may start in one
direction and then reverse several times before it finally seeks
a valid high or low level. Circuit designers believe that these
potential problems have been resolved over the last few years
as testing techniques and circuit simulations have wrung out
the Infinite number of application variations. However, there
is a simple, foolproof way that system designers can eliminate
any potential for this type of a problem. Deselect the device
during address transitions (see Figure 3).
Since new design techniques have made chip select access
times equal to address access times, system designers can
take advantage of this and improve reliabilty of their system
by increasing overall immunity to a noisy environment. This
can cover a host of potential board-induced problems from
oscillating multiplexer or driver units, to spurious address
glitches put out by MPUs.

Another design improvement is related to rise and fall times
on the output levels, known by circuit designers as dil dt. This
is the inductance associated with the changing current as loads
are charging and discharging. This inductance is coupled back
to the device, and through connections and bus resistance
can cause the power supply or ground to change drastically.
This is pushed to the limits as output drivers become more.
powerful, and is especially aggravated by multiple I/O devices
like byte-wide SRAMs which may have all eight data lines
switch from all Os to all 1s or vice versa. These spurious noise
spikes '
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MOTOROLA MEMORY DATA
10-31

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MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - _
AR256/D

MOTOROLA'S
RADICAL SRAM
DESIGN SPEEDS
SYSTEMS 40%

E

ngineers at Motorola Inc.'s MOS Memory Products Division are taking a radically different approach from the current asynchronous architecture for static random-access memories. They are developing
a synchronous architecture the company claims
will improve system throughput by as much as
40% and will reduce system component count by
as much as 50%.
The keys to the Austin, Texas, division's new
architecture are: replacing the traditional selfclocked address-trsnsition-detection circuitry,
found in conventional asynchronous SRAMs, with a
a
synchronous clocked architecture, and adding critical input and output latches on-clrip. The combination of these features eliminates as much as 8 to
10 ns of interconnection delay on input and on
output, says William Martino, the division's design
manager for specialized memories. It also eliminates circuitry often required to make asynchronous devices appear synchronous in high-perforby EIsrntII'd C. Cole
mance cache-memory systems, which depend
heavily on the synchronization of critical timing
r-------------------------...., parameters. Also incorporated on the
CLOCK
chip are drive transistors capable of
driving buses with capacitive loads
of up to 130 pF without additional
external circuitry. Motorola designers also enlarged the geometries to
increase the inherent drive capability
ADDRESS
of the devices.
The new architecture has been in25-n,
25-111
25..,
25-..
corporated into four initial products
18 K-BY-4-BIT
18 K-BY-4'BIT
18 K-BY-4-BIT
16 K-BY-4-BIT
SRAM
SRAM
SRAM
SRAM
that are members of a new family of
16-Kbit-by-4-bit SRAMs with cycle
times ranging from 25 to 35 ns and
Ito PORT
access times in the 10 to 35 ns range.
This equals that of comparably sized
asynchronous SRAMs fabricated with
the same 1.5-J&IIl double-metal CMOS
process [Electronics, Aug. 7, 1986,
p.81], says Frank Miller, synchronous SRAM project leader at the division. But Miller emphasizes that the
elimination of as much as 20 ns of
interconnection delay can almost
double system-level performance.
Motorola expects to offer samples of the four clocked synchronous SRAM parts within about a
month and plans to be in volume
production by the end of the fourth
quarter. Two of the devices, the
MCM6292 and 6295, incorporate
t.AIYIICHROIIOUIL Using asynchronous SRAMs, designers of high-performance synchro- level-sensitive transparent latches,

Key to higher throughput is
synchronous clocked architecture and
on-chip I/O latches; the combination
cuts interconnection delay by up to 20 ns

nous systems must Incorporate latches on the Inputs and outputs, adding' 5 to 20 ns of delay.
Raprin1ed from EIBcttonIcs, July 23, 1987, Issue. Copyright @1987, McGraw-HRI, Inc. All rights reserved_

MOTOROLA MEMORY DATA

10-35

RADICAL SRAM DESIGN ... (AR256)

whereas the MCM6293 and 6294 use positive- says Martino. As a result, most speed improveedge-triggered latches. Also the 6294 and 6295 ments have come by pushing the speed of the
each have an output enable pin that allows memory chips themselves. But, as processors
the user asynchronous control of the output speed up, mem6ries with sufficiently low access
bufters, allowing the parts to be used in com- times are getting harder and harder to produce
mon I/O at the board level. All the devices fea- inexpensively, Martino says. Current 25-tIh'l5-ns
ture an active ac power dissipation of 600 mW asynchronous SRAMs are barely adequate, he
says. And newer processors will require a sysand an active dc power of only 100 mW.
The advantages of Motorola's new family of tem throughput of no more than 35 to 40 ns. For
synchronous SRAMs outweigh the advantages of such throughputs, SRAMs must be pushed to beasynchronous devices, Martino says. In asyn- low 10 ns, only achievable now with bipolar and
chronous devices, great reliance is placed on ad- bicMOS circuits, but at much higher power.
dreas-transition detection, a self-cloeking scheme "However, even if parts are pusheddowu to 1 ns
that uses the address-signal transition, or edge, and under, there is still that 10 ns on the input
as a reference to synchronizing all operations on and another 10 ns on the output to deal with,"
the chip to that signal. Martino says that asyn- says Martino.
The most important element in Motorola's new
chronous SRAMs are widely used because they
allow and recognize address changes at any SRAM architecture (see fig .. 2) is the incorporation
time. As a result, no external global clock is of the external input and output latches necesnecessary to access data, making them easy to sary for synchronous operation on board. This
use. Also, compared with dynamic RAMS, asyn- design considerably simplifies system design and
chronous SRAMS take much less external circuit- reduces interconnection delay. "By pulling all of
ry, says Miller. Because they are free-running, that glue logic on board, it is no longer necessary
the addresses can be changed whenever needed, to drive a large bus to 'ITL levels," says Martino.
and they are very easy to control.
"It is now done on-clrip, reducing the 10-ns delay
Although they are easy to use, asynchronous dowu to picosecond levels. This allows the use
SRAMs must be surrounded by considerable ex- of a 25-ns part for a 25-t0-30-ns bus, rather than
ternal logic (see fig. 1) in many applications in using more expensive, power-hungry 10- and 15high-performance processor systems such as ns parts for the same chore."
writable control stores, data caches, and cacheThe Motorola architecture uses addresS-input
tag memories [Electronics, June 11, 1987, p.78] latches to hold the addresses so that the procthat require synchronous operation. The extra essor does not have to hold the addresses valid
circuitry imposes a considerable performance for the entire cycle. A similar function is served
penalty, and that can be a problem in cache by the data latches on the input. The latches
applications in particular, says Martino, where on the output, however, serve a dual function.
the speed of memory typically must be at least First, they provide a longer setup and hold
an order of magnitude faster than main memory. time over which the data is valid on the bus,
Also, for a cache to work properly, critical tim- necessary in most processing systems. With a
ing relationships must be preserved
so that a variety of simultaneous
operations can be coordinated, such
as searching the tag store, getting
data out of cache, and replacing
proper entries in the cache. The
added delay of the external logic
can make it difficult to preserve
these relationships.
25-no
25-ns
2!k1s
16 K-BY-4-BIT
16 K-BY-4-BIT
16 K-BY-4-BIT
When system speeds were in the
CLOCKED
CLOCKED
CLOCKED
200-ns range, Miller says, the addiSRAM
SRAM
SRAM
tionallO-to-20-ns penalty of this externallogic could be tolerated. "But
with proeeasor speeds improving so
OATAIN
dramatically, now pushing below
DATA IN
100 ns toward 50 ns, this is a penalOUTl'UT
OUTPUT
OUTPUT
OUTPUT
ty that is critical, especially since
PORT
PORT
PORT
PORT
the speed of the external logic has
not kept pace with the improvements in speed at the chip level."
Depending on the type of register involved and the proeeas used,
the delay time, even with high-performance logic families, can be re- 2.SYNCHRONOUL By incorporating latches and drivers on-chip. Motorola's synchronous
dueed to no more than 7 to 10 ns, SRAM reduces chip count by more than 50% and reduces interconnection delay.

-

MOTOROLA MEMORY DATA
10-36

RADICAL SRAM DESIGN ••. (AR256)

standard SRAM at minimum cycle time, that time
is about 5 ns without any external latching. This
is not enough time for most systems, which require the data to be on the bus for at least 15 to
20 ns, for the processor to receive the valid data.
The other function of the latches is to provide
the extra drive needed to drive the buses with
capacitive loads of up to 180 pF.

The designers of the new SRAMs have
eliminated the address-detection-transition
circuitry; now they use on-chip clock input
for a synchronous clocking scheme
Also incorporated on-chip to support the synchronous operation of the latches is a clock input
that controls when the latches are transparent
and when they are brought into play. Usually
this clock input is a derivative of the system
clock; that is, the latches are controlled by the
edge of the system clock.
The Motorola designers have eliminated the
address-detection-transition circuitry in the new
SRAMs. Instead, they use the on-chip clock input
to incorporate a synchronous clocking scheme in
which the necessary address, data, chip-select,
and write-enable information previously brought
on board the chip by the address-detection-transition circuitry is now accessed at the beginning of
the cycle in reference to the external clock,
rather than to the address edge as in the asynchronous scheme. The technique, says Martino,
is similar to how a DRAM brings in its addresses

with setup and hold times in relation to a readaccess or column-access signal input. "Since this
device employs a clock with a high-going edge at
the beginning of each cycle, it is no longer necessary
to detect address- transitions," he
says. "The system will tell the chip when to
supply the necessary information by providing
the clock at the appropriste time."
To eliminate the external drive circuitry, the
inherent drive capability of the devices was increased fourfold, says Miller. So Motorola designers enlarged the geometries used to fabricate the pull-up and pull-down transistors, typically on the order of 1,500 I'm wide, compared
with 4()()' to 600-porn widths on the standard 3O-pF
devices, and as small as 6 I'm in the memory
array and 80 porn in the peripheral circuitry.
Moreover, to achieve higher speed in spite of the
higher drive currents, n-channel devices, which
are only output devices, were used rather than
the slower p-channel devices. Furthermore, these
output devices were speeded up by incorporating
a separate ground-supply pin for the output drivers. "This allowed us to burn more current in
the output drivers without corrupting the operation of the rest of the circuit," Miller says.
Although this required a substantial increase
in the area devoted to the drive circuitry, the
chip size, 146 by 404 mils, is not substantially
larger than comparable 64-Kbit asynchronous
SRAMs. The extra area required for the larger
drivers and for the internal clocking circuitry is
offset by the area eliminated by removal of the
address-transition-detection circuitry required on
0
asynchronous parts, Martino says.

INGENIOUS SRAM DESIGN WAS DONE IN REMARKABLY SHORT TIME
FDr. m......., device of such complexity

and ingenious design, Motorola's new
clocked synchronous static random-access-memory design was completed in a
remarkably short time-only 12 months.
Moreover, most of the work was done
by a four-person design team: William
Martino, design manager for specialized
memories; Frank Miller, synchronous
SRAM project leader; chip designer
Scott Remington; and layout engineer
Richard Southerland.
One reason for the fast turnaround
was that the array and much of the
peripheral circuitry is identical to what
was used in the company's family of
asynchronous 64-Kbit SRAMs, says
Miller. "All we had to do was strip off
those portions of the circuit relating to
the asynchronous operation and replace
them with new synchronous elements."
The team drew from two sources for
the features incorporated into the synchronous design-including their cumula-

tive design experience. Miller has seven
years' experience in memory design.
Remington, an eight-year Motorola veteran, worked on the company's 64-Kbit and
1- Mbit DRAMs. Southerland, a five- year
Texas Instruments veteran, worked on

most of Motorola's asynchronous SRAMs
in his two years with the company.
The other source was extensive input
from Motorola's customers. "We spent
several months defining a variety of
special-application memory devices,
from dual-port SRAMs and video
DRAMs to content-addressable memories," says Miller. "But when we started
taking these designs around to customers for input, we found they were most
. concerned with ways to make standard
parts work, better. For designers of
high-performance systems using cache
architectures, one of the largest common denominators was complaints that
they had to surround the asynchronous
parts with a variety of glue logic to
operate appropriately in a synchronous
environment.
''The key is listening to the customers, finding out what their specific comIXPIRTS. Miller, Southerland, and Remington, plaints are, and coming up with parts
that satisfy those needs."
from left, are old hands al memory design.

MOTOROLA MEMORY DATA
10-37

II

/

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - - - AR258
HIGH FREQUENCY SYSTEM OPERATION
USING SYNCHRONOUS SRAMs
Frank Miller
Scott Remington
Richard Crisp
Senior Memory Designers
Motorola Inc.
3501 Ed Bluestein Blvd.
Austin, TX 78721
INTRODUCTION
The market for semiconductor memory products suitable
for today's high speed cache applications is changing dramatically as the demand for higher performanca super mini,
ASIC, and microprocessor based computers rapidly increa_.
1'his development has put heavy pressura on MOS memory
suppliers for faster and faster stetic RAMs to support shorter
and shorter procassor cycle times. To utilize their full system
performanca, fast SRAMs requira precise system control, long
address hold times, and have tight write pulse requirements.
They provide short data valid time, cause common 1/0 data
contention, and offer low drive capability. Todays high performance procassors themeelves have similar 1/0 requirements. Therefore system designers have many concerns when
designing a fast memory subsystem. They must use'additional
logic (latches, drivers, pulse generators, etc.1 to allow the
memory subsystem to interact efficiently with the procassor
et the fastest system cycle times.
A solution to get the memory and the processor to work
well together et fast cycle and access times lies not only in
faster components, but in minimizing the need for external
glue logic and its associated delays. The Synchronous Static
RAM is defined as having on chip latches for all its inputs and
outputs, added drive cepability, and a self timed write cycle
all under the control of the syStem clock. This aliminates the
need for most extemal logic chips and allows the memory to
run at higher system speeds than standard SRAMs with comparable access times.
This papar outlines the basic architecture of a Synchronous
SRAM that Motorola plans to introduce in the first half of
1988. We will highlight its advanteges over standerd SRAMs
in high frequency computer system oparetion. This is followed
by an application example for a MC68030 ceche subsystem.

ARCHITECTURE AND OPERATION
ARCHITECTURE
A block diagram of the 16K x 4 Synchronous SRAM is
shown In Figure 1. This diagram shows all inputs, outputs,
and control signals (iN, S, and KI to the part; add~ (AOA131, data in (00-031, data out (00-031, clock (KI, chip select
(SI, and write enable (iNl. All inputs, outputs, write enable,
and chip select are latched by the clock.
The latches are ona of two types, either positive adge triggered or transparent. The positive edge triggered latches are

latched by the rising edge of clock (KI. The transparent latches
are frozen when the clock is in the high state and open when
it is in the low state. Our parts feature two of the possible
combinations of input and output latches. The first part, the
MCM6292, features edge triggered latches on the inputs and
transparent latches on the outputs. Our second part, the
MCM6293, has edge triggered latches on both inputs and
outputs, to aid in pipelining data.
, The output buffers on all of our parts are capable of driving
130 pF loads. The output buffers were designed to drive this
load because in 80me systems the latches that they replace
would be required to drive a comparable size load. Due to the
size of load thet the output buffers must drive, and the speed
at which the part operates, we have added an extra ground
pin (VSSQ). This pin is the ground connection for all of our
output drivers, and allows us to drive our outputs harder and
also gives us noise immunity on the ground bus.
For systems that require a common I/O configuration we
expect to offer the MCM6295 and the MCM6294, which are
the MCM6292 and the MCM6293 with an asynchronous output
enable ((3) option. These parts, the MCM6294 and the
MCM6295, replace the chip select (S) buffer with an asynchronous output enable ((3) buffer.

OPERATION
The operation of these parts is much the same as a standard
16K x 4 SRAM except for the fact that the inputs and outputs
are latched and the cycle begins with the low to high transition
of the clock. The following examples will concentrate on a
read and write cycle for both the MCM6292 and the MCM6293.
The MCM6294 and MCM6295 read and write cycles are the
same as the MCM6292 and the MCM6293 except that the
outputs can be put into a high impedance state at any time
by using output enable (G).
During a read, see Figure 2, all inputs are latched into the
part at the rising edge of the clock (K) in both the MCM6292
and the MCM6293. For the MCM6292, when clock goes high,
the outputs become latched and are held in that state until
the clock falls low. Since the output latches are transparent,
during clock low time, there are two possible access times,
tKHQV and tKLQV. These access times are dependent upon
the high pulse width of the clock. If the high pulse width is
less than the access time of the memory array the longer
tKHQV spec is the clock access time. However if the clock
high pulse is longer then the memory array access time, the
clock access time becomes tKLQV. For the MCM6293 the

Copyright ©E1ectronIc Conventions, Inc. Reprinted with permission, from MIDCON 1987, Professional Program Papers, Session #22/4.

MOTOROLA MEMORY DATA
10-38

HIGH FREQUENCY SYSTEM ... (AR258)

-voo
-vss

MEMORY MATRIX
128 ROWSx
512 COWMNS

00
COLUMN I/O

Q1

02

03
K

[8J-TlIANSPARENT OR EDGE TRIGGERED LATCH

D

-POSITIVE EDGE TRIGGERED LATCH

Figure 1. Synchronous SRAM Block Diagram
outputs transitio;'l only when the clock switches from low to
high. The output data that is latched during the low to high
transition of the clock is the data from the previous read cycle.
For the write cycle, see Figure 3, all Inputs are handled in
the same manner as in the read. Since both write enable and
the input data are sampled on the rising edge of the clock the
write becomes self timed. This eliminates the need for complex
off chip write pulse generating circuitry. The outputs are put
in a high impedance state tKLOZ after the clock falls low for
the MCM6292. In the MCM6293 the output buffers will not
go into a high impedance state until the low to high transition
of the clock at the beginning of the next cycle. The MCM6294
and the MCM6295 allow the user to put the output buffers
into a high impedance state asynchronously by using the output enable input. This allows the user to put the output buffers
into a high impedance state earlier in the cycle, which eases
the data contention problem when the part is used in a common
110 system configuration.

SYSTEM ADVANTAGES (SRAM vs SSRAM)
SYSTEM DESCRIPTION AND TIMING
Figure 7 shows two examples of a 16K x 32 bit memory using
standard parts. The systems shown require eighteen parts
each ten latches and eight 16K x 4 SRAMs, to implement the
sam~ function as eight synchronous SRAMs and no glue logic.
The functional equivalent of a MCM6292 is the standard
16K x 4 SRAM with edge triggered latches on the inputs and
transparent latches on the outputs, as shown at the top of
Figure 7. The parts used in this example are six 'F374 octal
D-type flip flops, four 'F373 octal transparent latches, and eight
6288 16K x 4 SRAMs. The predicted timing diagram for the
system is shown in Figure 4. This timing diagram compares
the predicted system access with that of the MCM6292. In the
timing diagrams an approximate skew of 5 ns was added to
the address timing to allow for some propagation delay from
the MPU or CPU. For the purpose of comparison, three timing

MOTOROLA MEMORY DATA
10-39

III

HIGH FREQUENCY SYSTEM ... (AR258)

MCMIZI2 TRAISPAJU:IT OUTPUT LATCHES

MCMI212 TRAlSPAJU:1T OUTPUT LATCHES

MCMIZI3 EDGE TRIGGERED OUTPUT LATCHES

'~\
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_-

&...'---

MCMI213 EDGE TRIGGERED OUTPUT LATCHES

Q (a)

NOTE: Both MCM6292 and MCM6293 are available with an
aaynchronous G option.

Figure 2. Reed Cycle Comparison

K

00-Q3

-C_tKHOV_'-:-:--:-:-L_'--3l0I~;""_..!Q.!!(•.:..!I)L_3_)-I-----

NOTE: Both MCM6292 and MCM6293 are available with an
asynchronous G option.

Figure 3. Write Cycle Comparison
STANDARD SRAM WITH EDGE TRIGGERED LATCHES 01 IIPUTS AID TRAISPAREIT LATCHES 01 OUTPUTS
(tAVOV" 50 II, tcvc .. Z& U/

HOLD
~------18M------~~~

A

AT

(a+2)

KI
AI
OO-OJ

K2

Ol(0-3)

Ol (a)

Ol (a-2)

=

MCMI212 SYICHROIOUS SUM ItAvov 3& "" teTC" 2& III

III

12 111-----I00I1+-

3111
AT

A

K
Ol (0·3) Ol (a-2)

Ol (81
NOTE: AT -Address generation and transition time.

Figura 4. Standerd SRAM VB MCM6292 Timing Diagram

MOTOROLA MEMORY DATA
lQ.40

HIGH FREQUENCY SYSTEM ... (AR258)

parameters were calculated, tCYC (cycle time), tAVOV (address valid to data out valid tima), and tKOV (address clock
valid to data out valid time). The equations used to calculate
each of the timing paramaters for the standard SRAMs are as
follows:
tcyc=Ta+ Tb- Tc
tKov=Ta+Tb+Td
tAVOV= skew + setup + Ta+ Tb+ Td
The equivalent timing parameters for the MCM6292 can be
detarmined as follows:
tCyc=Tb
tKOV=Tb
tAVOV = skew + setup + Tb .
The equivalent circuit for the MCM6293, as shown at the
bottom of Figure 7, is a 16Kx4 SRAM with positive edge
triggered latches on both inputs and outputs. For this example
the parts used are, eight 62B8 16K x 4 SRAMs and ten 'F374
octal D-type flip flops. The timing diagrams for this example
are shown in Figure 5. The equations for calculating the timing
paramatera are as follows:
Standard SRAMs:
tcyc=Ta+Tb-Tc

SYSTEM COMPARISONS
The timing parameters for the 25 ns 16K x 4 synchronous
SRAMs and the equivalent circuits using 25 ns SRAMs are in
Table 1. Also in Table 1 are timing parameters for other systams
using progressively faster and more expensive SRAMs. From
this table it can be datarmined that if either tAVOV or tKOV
were the most important timing constraints a much faster
SRAM would be needed to match the performance of the
synchronous SRAM. For the performance of the system built
with standard parts to match the performance of the 25 ns
MCM6292, it would be necessary to use a 10 ns SRAM. Similarly, if the system used 25 ns MCM6293s the equivalent system made from standard parts would require 15 ns SRAMs.
Another important advantage of the synchronous parts over
standard parts is the board level chip count; 18 parts are necessary when using standard SRAMs while only 8 parts are
needed for the synchronous SRAM implementation. This is
critical when board space is an important factor. Also, the fact
that data and write enable·are sampled on the rising edge of
the clock, eliminates the need for complex write pulse generating circuitry. Finally, in order to gat the high speed performance out of standard SRAMs, it requires precise timing
and phase control of two clock signals (K1 and K2), while in
the synchronous part only one clock (K) is needed.

tKov=Ta+Tb+Td+Te

APPLICATION: MC68030 CACHE SUBSYSTEM

tAVOV= skew + setup + Ta+ Tb+ Td+ Te
MCM6293:

The Synchronous SRAM combined with the Motorola
MC68030 microprocessor illustrates the potential of this advanced memory architecture. The high frequency performance
of microprocessors like the MC68030 can be impaired by having

tCYC=Tb
tKov=Tb+Te
tAVOV = skew + setup + Tb + Te

STAlBARD SHAll WITH EDGE TRIGGERED LATCHES 01 Ii!PUTS AID OUTPUTS
ItAYDY= 54 no. 'eYe = 25 ..I

2 ..
~------16

~-------16

.. --------~

..--------~~!

K1 _ _ _ _"'1

~-----~~~------~~~~--_ _ _~~~I_ _ _ _ _~------~~------

~----------~~}------------{~)-------K2

OLIO-31

:::::x______

.....;;;OL~I;:...-...;2;:.I_ _ _ _ _ _ __
.ca1213 SYICHRONOUS SRAM (tAYDY = 45

OL lal
II,

'eYe = 26 III

/

Ie
25 .. (Tbl
.',.
10 .. 11.1= .....____-::-":":"_ _ __
K==:::;;~=====~~~~..!!!...!!!!.
JX
OL la-II
=--=x
OL loJ

OL 10-31 _ _ _ _ _....;;;OL;..:I.:...-...:2::.1_ _ _ _ _

NOTE: AT -Address generation and transition time.

Figure 6. Standard SRAM VB MCM6293 Timing Diagram

MOTOROLA MEMORY DATA
1041

m

HIGH FREQUENCY SYSTEM ... (AR258)

MCM6295
PROCESSOR
AOORESS BUS

SYSTEM Cl:K - - - - - - " - - - - - -.....
Figure 6. MC&8030 Burst Reed Addressing
to wait for slow memory to respond. For this example we will
use a 16K by 32-bit cache system running at frequencies of
up to 33-1/3 MHz. This does not mean that you can purchase
MC68030 processors today at this speed, only that our 25 ns
SSRAM will support this processor up to that speed. The
MC68030 timings used for this example are extrapolated from
the current 16.67 and 20 MHz specifications that exist today
and are not intended to be the official specifications.
We will exploit the processor's burst read cycle which supports burst filling of its on-chip instruction and data caches,
adding to the overall system performance. The on-chip caches

are organized with a block size of four long words, so that
there is only one tag for the four long words in a block. Since
locality of reference is present to some degree in most programs, filling of all four entries when a single entry misses can
be advantageous, especially if the time spent filling the additional entries is minimal. When the caches are burst-filled,
data can be latched by the processor in as little as one clock
for each 32 bita. 1
The timing diagram shown in Figure 8 shows a burst read
cycle (four 32-bit words read) in a 3-1-1-1 clock cycle configuration. The first word is read in 3 clock cycles and the remaining three words are read in ona clock cycle each. The
burst read cycle begins with a cache burst request (CBREQ)
from tha processor followed by a cache burst acknowledge
(CBACK) from the memory controller. This means the processor is requesting a burst cycle and the accessed memory
can comply. During the burst cycle the processor supplies the
starting address in the normal synchronous fashion and holds
it valid until all four long worda are read. It does not provide
the next three addresses required to complete the burst fill,
so they must be generated off chip. For this example we used
a 'F191 counter whose control Signals, Pl and CE, are generated in a cache controller. The clock input, CP (ClK), is the
opposite phese of tha system clock. The SSRAM operates
with the same inverted system clock (ClK) and receives its
addresses from two sources; A2.-A 13 are supplied from the
processor's address bus, and AO-A 1 are supplied from the
'F191 countar to allow nibble counting as shown in Figure 6.

STAlDAD SHAM WITH ED&E TIUGGERED lATCHES O. I.PUTS AID
TRAISPAREIT lATCHES 01 OUTPUTS

32
6288
W------+,-It--~~

374

!-----+I (2) 11---.-1
AO-A 13 --+--..11

SHAM

I -___--.,£-___ OL

25 .. Ace

32

(8)

14

14

16Kx4

AL (0-13)

Kl------'

STA.DARD SRAM WITH ED&E TRIGGERED lATCHES 01 IIPUTS AID OUTPUTS

32
8288
w----+f--,~--+I

! _ _ _-.,--t
AD-AI3

374

-_::::2:::::~~
14

18Kx4

SRAM

I -______+---."OL

(2) 11--,-\.1 25 .. Ace

32

(8)

Kl-----'

Figure 7. Standard SRAM Implementations

MOTOROLA MEMORY DATA
1tl-42

%
C)

:::z::
ClK

."

::D
m

p

CBiiEii

c:
m
2:

Q

CiiACK

en

STERM

~m

~'A'
\

s:

AS
~

~

ADDR

j;;

~

~

):
~

i

CTR. "eE"

m

~
:D
-<
a
~

>

CTR. ''Pi''

AD~::~

- ......

t

AD

¥

X

AD+l

AD+2

~

AD+3

'fIfJJ.

t

AD

SSRAM,
CTR. CLOCK

DATA

~

0 IADI

M

0 lAD + 11

MI

ClK
NOTES: 'A'-(minimum clock periodll2

CTR.=counter ('F1911

Figure 8, MC68030 Burst Fill Timing

I

0 IAD+21

'fJ.

0 IAD+31

)

HIGH FREQUENCY SYSTEM ••. (AR258)

Table 1. Timing Comparisons Batwaan SSRAMe and SRAMe

Timings

26n.

26 ns

20ns

16ns

10 n.

SSRAM

SRAM

SRAM

SRAM

SRAM

Trans.
Output

Edge Trig.
Output

Trans.
Output

EdgaTrig.
Output

EdgaTrig.
Output

Trans.
Output

EdgaTrig.
Output

Trans.
Output

Trans.
Output

EdgaTrig.
Output

tcvc

25na

25na

25na

25n8

ZOna

ZOna

15 n8

15 na

10 n.

10na

tAVQV

35na

46na

50na

54na

46na

49na

4On8

44na

35 n.

39na

tKQV

25na

35na

43na

43na

38na

38na

33 ns

33na

28 ns

28na

SUMMARY
The timing begins with the request, the acknowledgment
and the generation of the first address. This address is used
to access one of the four long words. Two low order address
signals from this address must also be loaded into the counter.
At the beginning of the cycle the parallel load signal for the
counter is enabled, the address is then loaded in and the PL
signal can be disabled. The counter will provide the memory
this first address a propagation delay later and then increment
it on successive clock edges to supply the memory with the
remaining three needed addresses. After receiving all four 32bit words the processor is free to continue.
A similar system built using stendard MCM62.88 116K x 41
type SRAMswouid require the usa of off-chip input and output
latches ('F373 or 'F374 typal in addition to the counter. It
would require four chips to parform the latching function for
32-bit data in, and four chips to latch the 32-bit date out, for
a total of eight additional 20 pin packages added to the memory
PC board. This stendard SRAM cache system would also
require additional logic in the cache controller to support the
write pulse, associated writa enable and data in timing for
writa cycles, and the generation of a second clock (LE or CPl
to separately control the input and output latches. To attain
the cache system speed of 33-1 /3 MHz would require a SRAM
access time of approximataly one bin faster than the SSRAM.
In addition the external glue logic would have to be faster than
what is currently offered in the 74F serlas logic.

There are many applications for high-speed Synchronous
Static RAMs. The integration of latches, self timed writes, bus
drive capability, and clock control greedy simplifies system
level implementation and ease of usa. These features will allow
SSRAMs to continue to support higher frequency system operation. Depending on the application, Synchronous Static
RAMs can provide up to a 10 to 15 ns improvement in system
access time over SRAMs that spec the same chip speeds.
They save precious board space by reducing the chip count,
and simplify controller design for latch control and write cycles.
ACKNOWlEDGMENTS
The authors would like to thank Brian Branson and Bill
Martino for thair inputa and comments that helped complete
this paper. And special thenks to Richard Crisp for his MC6IKI3O
cache system timing analysis.
REFERENCES
1. Motorola Semiconductor Technical Data: "Technical
Summary: Second Generation 32-Bit Enhanced Microprocessor", 1986.
2. Motorola Semiconductor Technical Data: "Fast and LS
TTL Data", 1986.
Motorola Inc. cen provide the usual promotional and technical literature associated with the Synchronous Static RAM
family.

MOTOROLA MEMORY DATA
1().44

MOTOROLA

-

SEMICONDUCTOR
AR2601D

ENHANCING SYSTEM PERFORMANCE
USING SYNCHRONOUS SRAMs
Curt Wyman
Robert King
Motorola Inc.
3&01 Ed Bluestein Blvd.
Austin. TX 78721
INTRODUCTION TO SYNCHRONOUS
SRAM ARCHITECTURE
Fast static RAMs (FSRAMsl are commanding a lot of attention from todaYs high performance system designers who
frequently find that the speed of their system is limited by the
performance of FSRAMs on the market. As 32-bit microprocessor-based systems become faster and more prevalent, the
demand for sub 25 ns FSRAMs will grow even more.
FSRAMs are the driving force bahind semiconductor technology today: they have the smallest circuit features-as low
as 0.8 micron from some manufacturers-and use special processes like double-level matal and SIMaS. The Fast SRAM
has come a long way from its slower ancestolS like the 1K x 4
Model 2114. The ease of use and dependable performance
that resulted from the asynchronous performance of SRAMs
have been replaced by the raw speed which is pacing todays
demand; however, FSRAMs are still expected to meet the
basic SRAM specifications for pure asynchronous performance. This dichotomy has caused problems as chip designers
come up with more innovative ways to speed up their circuits.
Address transition-detection circuitry, for example, caused a
number of problems when first introduced in 2K x 8 FSRAMs
under certain system conditions. With such advanced technology being used and the cost of manufacturing these chips
so high, Motorola has developed an alternative to a high-tech
15 ns access SRAM that uses conventional technology.
Motorola's newest SRAMs are the first to fully embrace the
primary purpose of Fast SRAMs. They totally abandon the
previous definition of asynchronous SRAMs. They have the
raquirement of a clock signal, and are, therefore, Synchronous
SRAMs. They have separate pins for input and output data,
and do not specify standby power.
Motorola offers four different 65,536-bit Synchronous
SRAM family members organized as 16Kx4: Modals
MCM6292, MCM6293, MCM6294, and MCM6295. The technology used for their implementation is the fast, low powerconsuming, and noise-immune HCMOS III, which uses a silicon gate for its fabrication. One of the main advantages to
using these devices is that they can be designed into system
cache-memory or writeable control-Btore applications with
fewer interfacing glue-type parts than the standard SRAM
memory. Among the reasons for this are the integrated input
and output latches that are capable of driving loads up to 130
pF. Due to the increased operating speed of the device and
the additional output-buffer loads, an extra ground pin has
been placed on the chip.
Four different devices have been specified so that all combinations of the output-latching and output-enable features
are in the offering. The MCM6292 comes equipped with latches
that are edge triggered on the inputs but transparent on the
outputs. To support systems with pipelined data, the
MCM6293 is offered with edge-triggered latches on both the

inputs and outputs. The MCM6295 and MCM6294 are outputenable versions of the two basic parts. All of the Synchronous
SRAMs come with separate data-in and data-out pins; however, some systems specify a more conventional common
1/0 mode, and the asynchronous output-enable control (31
which replaced the S signal on these parts can be helpful in
such a case.
In many designs using SRAMs, there is actually extra time
during the cycle that is being wasted. In more critical applications, the Synchronous SRAM offers an alternative to the
conventional SRAM. An external clock input (KI can be used
to precisely control the cycle by directing the operation of the
on-chip latches.
The designer of small personal computer systems can use
the Synchronous SRAM in a number of storage areas. One
of the primary applications, cache memory, is high-speed
memory that resides batween the central processing unit (CPU)
and the main memory of the system. Accesses to this fast
cache typically require 60 ns versus the 200 ns needed to
perform an access to main memory. One way the cache is
used is to store dsta or instructions from main memory that
are frequently called for by an application. As an example of
this, higher-Iavellanguagas often use repetitive loops: by storing the data necessary for these repeated operations and instructions in the cache, accesses to the main memory can be
avoided.
A typical system is illustrated in Figure 1. It is configured
as a cache memory residing batween the CPU and the system
bus. The system bus links the main memory and 1/0 devices
to the CPU by way of the cache.

SYSTEM BUS

II
Figure 1. A primary synchronous SRAM application Is
high-speed cache memory residing between the CPU
and the main memory of a personal computer system.
Accesses to the cache typically require 60 ns, whereas
main memory takes 200 ns.

Reprinted with permission from ECN, Chilton Compeny, October 1987.

MOTOROLA MEMORY DATA
10-45

ENHANCING SYSTEM PERFORMANCE ..• (AR260)

2. In this illustration, there are four MCM6292 synchronous
SRAM devices configured to operate on a 16-bit data bus.
Each memory has four data inputs and four data outputs to
allow the transfer to data. The address bus consists of 14
address bits, AO-A 13. These 14 bits are required to decode
and access the 66,536 memory locations of each device. The
memory matrix is configured as 128 rows by 512 columns. The
system clock is connected to the (K) input of each memory
and used to latch all inputs, outputs, write enable, and chip
select.
In Figure 3, there are two different read-cycle timings being
represented for the MCM6292 (transparent output latches).
Both are examples of systems that use the rising edge of (K)
to latch all inputs to the memory device. The states of the
outputs are then held until the clock makes its transition to
the low state. With this Synchronous SRAM, however, it is
possible to have different memory access times, depending
upon the condition of the clock (K). If the clock pulse is high
for less than the 25 ns access time of the memory device, the
total access time is rated at tKHQV or 25 ns (Read Cycle 1).
On the other hand, if the high portion of the clock cycle lasts
longer then 25 ns, the total access time becomes tKLQV (10
ns maximum) plus the length of the clock high (Read Cycle

In operation, there is one set of locations in which data is
stored and another set of locations containing a cache tag for
each word in the cache. The cache tag identifies the main
memory location with which the data is associated. A comparison is made between the cache tags, which are located
in the cache memory, and the address, which is generated by
the microprocessor at the beginning of a cycle. If a cache tag
and the address match, there is no access made to main
memory, but instead the read or write cycle is executed on
the corresponding byte of data stored in the cache. When the
address does not find a match, a miss occurs, and new locations must be read into the cache from main memory.
A cache miss is the result of a mismatch between the cache
tag and the desired address to be accessed by the CPU. When
this occurs, the system logic is allowed to perform a retry of
the previous access. The appropriate address is accessed from
main memory. Following an update of the cache, the data is
then available for processing.
The cache hit rate is the actual percentage of accesses made
to the cache in which the requested address is resident. In
order to keep the hit rate as high as possible, a variety of
software routines are used. The function of these routines is
to keep the cache as full as possible with the most frequently
used data. In so doing, the cache hit, rate for both the data
and instruction caches wiD be maximized, increasing overall
information throughput.
The Harvard architecture, an efficient method used in many
current day applications, is characteristic of a configuration
which supports parallelism throughout a system. Synchronous
SRAMs can be organized as relatively small external caches
connected to the data buses and instruction paths located
between the CPU and main memory. This will allow simultaneous instruction execution and data prefetches. The external cache demonstrates another system speed enhancament capability of these devices.

2).
Figure 4 has baen included to show the timing of a write
cycle. The timing of a write operation is similar to that of the
previously discussed read cycle. One point to consider is that
to generate a write pulse, there is no requirement for complex
external interfacing chips. This is accomplished through the
seIf-timin'g mechanism which samples both the write enable
and input data when (K) rises. A high-impedance state is
entered when the clock raturns low.

MPU AND MEMORY SPEED CONSIDERATIONS
, AT A SYSTEM LEVEL
One consideration worth mentioning is that many memories
are not able to keep up with very high-speed MPU control
devices. This hes been a problem with DRAM technology for
a number of years. MPUs operating at clock speeds of over
20 MHz are common in both business and engineering systems

ADDRESSING CONSIDERATIONS FOR
READ/WRITE CYCLES
To batter understand the Synchronous SRAM's addressing
capabilities in regard to read and write cycles, refer to Figure
SYSTEM
ADDRESSES

, /14
,/14

,/14

SYSTEM
ClDCK

AO-A13

'-- K

AO-A13
-K

MCM6292

II

T4
SYSTEM
DATA IN

II&.

OUTPUT
DATA BUS

, /16

DO-D3

4

4

00-03

~

AO-AI3

AO-AI3
'-- K

MCM6292

MCM6292

-

; - - DD-D3

DO-D3

lot

/14

14

'-- K

MCM6292

~

00-03

/

14

4

00-03

~

4

/ 4

DO-D3
00-03

/4

Figure 2. An array of synchronous SRAMs Is configured for a 16-blt data bus. Each MCM6292 has four data inputs,
four data outputs, and fourteen address lines.

MOTOROLA MEMORY DATA
10-46

ENHANCING SYSTEM PERFORMANCE . .. (AR260)

READ CYCLE 1 (See Note 1)

tKHKL --_14--- tKLKH

A (ADDRESSI

w

00-03 - - - - - PREVIOUS HIGH Z

READ CYCLE 2 (See Note 2)

A )ADDRESSI

_____~_~_-_-_~_I.~~:-t-KL-W-----tK-L~---~~-~~~:1~
~

00-03 _ _ _ _ _ _ _ PREVIOUS HIGH Z

0"

)--

NOTES:
1. For Read Cycle 1 timing, clock high pulse width < (tKHQV - tKLQVI.
2. For Read Cycle 2 timing, clock high pulse width .. (tKHQV - tKlQVI.

Figure 3. If the system's clock high. tKHKL. is shorter than the MCM6292's 2!i ns access time. than tha total access
time will be 2!i ns. However. if tKHKL is longer than 2!i ns. total access time is increased.

MOTOROLA MEMORY DATA
1().47

ENHANCING SYSTEM PERFORMANCE .•• (AR260)

IKHKl---tlofooI--1KlKH
K

ISVKH --+ol--+l_ _+--IKHSX
ISVKH - ...- - - I.....t---t- IKHSX

ii

A (ADDRESSI

00-03

Vi
IKlOZ

-+__

~~

---JJt-------

00-03 _ _ _ _ _ _ _
o"_-_l_ _ _ _ _

HIGH Z - - - - - - -

Figure 4. In a write cycle, the 8elf-timing mechanism of the MCM6292 samples both the write enable and the input
data when the clock 8ignal, K, rises.

WHAT'S TO COME FROM
SYNCHRONOUS SRAMs

m

Very high cache hit rates can be attained from a relatively
small cache store. The high-rate efficiency is primarily due to
the fact that the cache is located external to the CPU rather
then actually being an on-chip cache, as is the case with some
high-performance microprocessors.
In addition to the popular high-speed cache-memory applications, Synchronous SRAMs are also ideal for writeable control store environments. Data can be downloaded into a
SynChronous SRAM array, and the information can be accessed at very high speeds-much faster than from a DRAM
array.
Memories are taking on new roles. Because of this, they
are being used in a wide variety of application areas and operating to support functions previously not possible. Future
Synchronous SRAM devices will be even more complex and
some will very likely contain higher degrees of intelligence.
Many will be designed with special system functions in mind.
Higher-speed operation working from lower voltage sources
is just one example. There will be enhancements allowing the
designer more flexibility and enabling him to reach supercomputer performance.
Current-day static memories support numerous applications. The synchronous SRAMs discussed above will be offered in 3OO-mil, 2B-lead CERDIP and 400-mil, 2B-lead plastic
SOJ packages. These configurations satisfy the requirements
of most systems presently. As chip integration and sophistication continue to advance, the packaging technology will also
need to advance to promote future innovations within the
industry.
For more information on MCM6292-series synchronous
SRAMs, contact Memory Marketing at Motorola, Inc., MOS
Memory Products Div., P.O. Boxeooo, Austin, TX78762. (512)

in use today; therefore, 25 ns Synchronous SRAMs are ideal
to operate with zero wait states.
Wait states are implemented with slower SRAMs and most
DRAMs to freeze the state of the microprocessor address and
data bus for a clock cycle. As long as the signal controlling
wait states is assertad, more wait-state periods will be generated. The microprocessor resumes operetion when the waitstate signal is negated.
The alternative to implementing a wait state to halt the
microprocessor for a slow memory device is to use the much
faster Synchronous SRAM. Its timing parameters can be more
exactly controlled, making the system operate more efficiently.
Faster data throughput plus an improvement in overall system
performance make the Synchronous SRAM cache a very costaffective solution in a microprocessor-based system.
When performing read and write operations in a personal
computer system, the timing relationship between a highspeed microprocessor's system clock and a typical Synchronous SRAM's cycle time constraints is very critical. These operations could be as simple as inputting console information
for CRT display outputs or as complex as supporting multitasking environments or concurrent execution of operations.
High-performance microprocessor systems with operating
frequencies of 20-25 MHz are a realistic timing example being
offered today. For microprocessors capable of operating at
these speeds, a 25 ns Synchronous SRAM is ideally suited.
These devices not only provide precise clocked timing control,
but also will support applications requiring system clocks running at over 30 MHz. This can be accomplished without incurring any degradation of the processor by inserting wait
states.

928-6700.

MOTOROLA MEMORY DATA
10-48

MOTOROLA

-

SEMICONDUCTOR
AR270/D

DESIGN APPLICATIONS

DESIGNING
A CACHE
FORA FAST
PROCESSOR

o wring the best performance from the new
breed of superfast microprocessors, system designers frequently tum to external
caches. Direct mapped and set-associative
caches offer advantages, compand with
fully associative caches. In designing an address-tag-and-comparator system for a direct-mapped or set-associative cache, engineers must consider issues such as the
speed of the hit, the address-bus loading, and the datablock size (see "What ~ the Cache?'7.
Issues relating to the specific high-speed microprocessor also crop up. For instance, a system built around the
MC68030 microprocessor must support two-cycle reads
and writes related to the address-tag-comparatortiming.
Designers must also resolve questions of whether or not
and how to support a burst mode. To support this mode,
they must decide on address-tag and cache-data-RAM
requirements unique to the mode, such as automatically
incrementing addresses for the address tags and the
cache-data RAM. They must also consider the data setup
and hold timing requirements at the processor.

CACHE TAG RAMs

COMPARATOR CHIPS
HELP CREATE
A HIGH-SPEED CACHE
FOR THE MC68030

RICHARD CRISP, BRIAN BRANS(lII, AND RIl'I HANSON
Motorola MOS Memory Products Div.,
3501 Ed Bluestein Blvd.,
Austin, TX 78762; (512) 928-6141.

Matching the speed of the MC68030 microprocessor,
the cache-tag comparators in the MCM4180, MCM62350,
and MCM62351, organized to handle 4 kwords by 4 bits,
compare data in the cache RAM with an external 4-bitwide data field. The comparison results appear on the
devices' Match pins. Each of the cache-tag devices is bulk
clearable and has read and write functions. Of all the
cache-system configurations possible with this MCM
family of RAMS, for a 32-bit-by-16-kword system, a block
of four MCM4180s as tag valid-bits comparators and
four MCM62350s provide the fastest hardware arrangement,least bus loading, and lowest cost (Fig. 1).
The MCM4180 includes an Exclusive-Nor (XNOR)
comparator, which matches each bit position with the
stored data for a true result. This type of comparator
requires that every bit position match the stored data for
the result to be true.
The MCM62350 and MCM62351 supply a user-configurable comparator offering the conventional XNOR
mode and an And-Or-Invert (AOI) mode. Unlike the
XNOR mode, the AOI comparator treats zeros in any bit
position as don't-care bits during the compare operation.
The AOI option is extremely useful for comparing status
bits often stored with each address tag. The status bits
can represent validating entry bits, which allow storing
multiple data entries with each address-tag entry (block
size = n), as well as individual so-called dirty bits needed
for copy-back caching schemes.
The MCM62350and MCM62351 RAMs also feature bitset and bit-clear write cycles, which allow individual bits
to be unconditionally set or cleared through a mask.
Thus, any combination of the four bits in any particular
location can be set or cleared without having to read the
RAM, modify the data, and write it back as in a conventional SRAM. This feature is useful with the AOI com-

Reprinted with permission lrom ElectroniC Deoign © 1988 VNU Busln... Publications Inc. (Vol. 36 No. 23) October 13, 1988.

MOTOROLA MEMORY DATA
10-49

DESIGNING A CACHE . .. (AR270)

1,1"iHI'liualiHLililt:~'

CACHE SYSTEMS
parator for storing status bits. Also,
both the MCM62350 and the
MCM62351 have ground pins positioned to achieve minimum self-inductance in both DIP and small-outline J-type packages.
The MCM62350 differs from the
MCM62351 in that it offers a userconfigurable Match-output active
level. The MCM62351 has an active
high open-drain Match output. WireORed connections of separate Match
pins allow the comparison width to
expand efficiently.
The design of external caches for
the MC68030 involves two major timing problem areas-in the addl'ess-

W

ith a cache, when a
proeessor executes a

new task, it fetches

from the system's
main dynamic memory.the first
instruction and corresponding
data, plus the instruetionsand
data for aeveral subseqnent 0perations at adjacent memory addresses_
The cache's SRAM memory
fetches the inBtruetiona and data
from the adjacent main-memory
addresses because they have a
high probability of being used in
the operations that follow. Most
programs eontain loops, and if the
cache is 1arge enough, the needed
information will be present in the
fast cache, shortening the average memory-access time.
That's a cache hit. If the cache
doesn't eontain the information, a
miss oeeurs. In this case, the main
memory again responds, and the
cache receives updated inBtrIJctions and data.
A cache controller circuit sequences the necessary functional
steps. For normal program 0peration, the system doesn't direetly
address the cache. The cache subsystem stores both the information and its corresponding mainmemory address. The controller
compares the stored address in
the cache, called the address tag,

tag-comparator and in the data
cache. Since the synchronous bus
protocol makes it possible to use
short bus cycles and supports burstmode accessing, the prudent designer will also choose to use it for external cache interfacing to the MC68030

(see "A Synchronous Bus Protocol'?
The primary challenge with timing
the address-tag comparator is to
avoid wait states when the processor
runs at a high frequency. Generally,
only a hit in any given bus cycle
should assert the Synchronous Termination Handshake (lSTERM) signal. The first order of business, then,

WHAT'S THE CACHE;!
widI the address the processor
provides to determine whether
the cache contains the requested
data.
Cache types are usually delineated bytlleirplaeementpoliey, or
mappiDa- a1Jorithm, which determines where new information is
stored in the cache. Most caches
are either
content
addressable or direetly mapped,

associativelY

random-accessIble ty)tes.
Whereas ill astraightRAK, the
processor dirtietIy accesMrthe information, in a content-addresaable memory a match with a
stored address of the information's original main-memory location causa the eontents-addressable portion of the cache to respond with a pointer (see the jig-

ure, 0J1P0IIite. left). ,The pointer,
or address, then specifies the data's location in a random-accessmemory portion of the caehe system. This fully associative memory cache copies the-mformation in
any main-memory location into
any location in the caehe.
A directly mapped cache, on the
other hand, uses random-access
memories to store both an address
tag and the information's image
(see the figure, opposite, rigkt).
The low-order bits of the address
from the processor provide an index into the address-tag-store

MOTOROLA MEMORY DATA
10-50

is how to generate ISTERM.
To avoid a wait state, the MC68030
asserts the worst-case Address
Strobe (I AS) signal at the same time
that the ISTERM signal is activated.
As a result, cache designs for this
processor cannot generally use the
I AS to signal the cache that a bus
cycle is starting.
Nevertheless, the address-tag
comparison must be qualified based
on valid addresses that I AS announces. Fortunately, a signal called
External Cycle Start (/ECS) is valid
slightly earlier than the addresses.
Whenever the processor needs an instruction or data, it therefore asserts

DESIGNING A CACHE ... (AR270)

iI141!HI"'A4ui,jiiti$j

CACHE SYSTEMS
lEGS during the clock's high phase
when the new addresses appear.
Should the processor find what it
needs in its internal caches, it would
not assert I AS and an external bus
cycle would not run. If ISTERM activates when no bus cycle runs, the
processor ignores it.
The timing diagram of the synchronous bus shows that after addresses are valid, ISTERM must be
activated within just a half clock period minus the clock-rise time to
avoid wait states. Operating at 25
MHz, that leaves only 15 ns to check
for a cache hit and assert ISTERM if
wait states are to be avoided.

The circuit must furnish an extra
gate for the results of the tag comparator to be ANDed with a qualifier-a latched lEGS signaL A 74F64
AOI gate can AND the Match signals from the tag comparators to this
qualifier. Unfortunately, this gate
adds a 5.5-ns delay to the circuit. Consequently, the tag comparators must
perform their comparison in 9.5 ns.
Since TTL-compatible tag compa,rators aren't that fast, this technique
isn't feasible. Two options remain:
Always assert ISTERM after lEGS,
and if the cache misses assert
IBERR and IHALT retry, or insert a
wait state. With retries, at 25 MHz,

the tag comparator has 35 ns to perform its function and generate
ISTERM. At 33 MHz, it has just 28
ns. For the wait-state option, 34.5 ns
is available to generate ISTERM after the addresses are valid.
Retries, however, can run into
trouble. After requesting a retry,
the processor must disable the cache
to prevent a system deadlock condition when the bus cycle reruns. Also,
before the bus cycle can rerun, a twoclock-cycle delay occurs. As a result,
the penalty incurred when the external cache misses might be greater
than it would be if the processor asserted ISTERM only on a cache hit.

MlfllllbII

Procenor

Procel1Or

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bill
bill
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MOTOROLA MEMORY DATA
10-51

-

•

DESIGNING A CACHE •.. (AR270)

1"4i jijl',JQ4I!R,'iUiltl

CACHE SYSTEMS
Therefore a no-wait-state cache with
a low hit mte can perform worse
than a cache with a wait state.
A secondary difficulty with tag
compardtors in MC6l«l:!O cache designs is supporting hurst-mode accesses. The address-tag-compardtor
timing is clearly a limiting factor in
the design of external caches for the
Me(illO:IO. Because the hurst-mode
cycles furnish only a first address
for the four desired long words, the
circuit must provide autoincrementing addressing to the address-tag
comparator and the cache-data
RAMs. This requirement, coupled
with the fact that hurstlransferscan
occur in single clock cycles, implies
that incrementing the addresses into
the address-tag compardtor will not
be fa.'1t enough to support one-cycle
bursting.
Organizing the cache with a block
si?,c of four is a viable one-cycle

hursting solution. Storing a valid bit
for each long word per tag, then, requires only checking the valid hit on
the fly during the bursting portion of
the burst-mode transfer.
This approach can exploit the fast
timing of the compare port in an
MCM62350 or MCM62.%1 to store
the valid bits. It also allows the AOI
compardtor option for the valid-bit
comparisons to operate effectively
(Fig. 2).

A PAL POINTER
The open- 1• =-i1

1+1 ....

J78PL

<1>1

1... 1 +0.25(0.010) @lITI A®I B®I

DETAILB

DIM
A
B

C
D
E

F
G
H
J
K
L

N

P
R
S
U
V
W

X
Y

MILUMETERS
MIN
MAX
107.70 108.20
12.70
9.14
0.37
0.63
1.14
1.40
1.02
1.40
1.27 BSC
2.54 BSC
0.20
0.35
3.81
3.05
100.20 100.46
1.14
1.40
1.40
1.14
3.43
4.19
2.54
46.99 REF
6.35BSC
16.00
3.81
5.26
-

-

-

INCHES
MAX
MIN
4.240 4.260
0.500
0.360
0.015 0.025
0.045 0.055
0.040 0.055
0.050BSC
0.100BSC
0.008 0.014
0.120 0.150
3.945 3.955
0.045 0.055
0.045 0.055
0.135 0.165
- 0.100
1.850 REF
0.250 BSC
0.630
- 0.150
Q.208
-

H

VIEWZ-Z

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M.1982.
2. CONTROLLING DIMENSION: INCH.

II

MOTOROLA MEMORY DATA
11-23

MOTOROLA

-

SEMICONDUCTOR

TECHNICAL DATA

Embossed Tape and Reel
Embossed Tape and Reel is used to facilitate automatic pick and place equipment
feed requirements. The tape is used as the shipping container for various products and
requires a minimum of handling. The antistatic/conductive tape provides a secure cavity for the product when sealed with the "peel-back" cover tape.
• 13-lnch Reel
• Used For Automatic Pick and Place Feed Systems
• Minimizes Product Handling
• EIA-481
• SOJ: 24, 20/26, 24/26, 28, 32
• SOIC: 28, 32
• PLCC: 44, 52
Ordering Information
Use the standard device title and add the required suffix R2. Note the minimum lot
size is one full reel for each line item, and orders are required to be in increments of
the single reel quantity.

~oooooooo~

· DO· .
l]LJlJ11Dr[J
DIRECTION OF FEED

Minimum
Lot
Size

Tape and
Reel
Suffix

1000

1000

R2

13"

1000

1000

R2

24

13"

1000

1000

R2

300

24

13"

1000

1000

R2

28

300

24

13"

1000

1000

R2

28

400

24

13"

1000

1000

R2

32

300

32

13"

1000

1000

R2

32

400

32

13"

1000

1000

R2

28

350

24

13"

1000

1000

R2

32

450

32

13"

1000

1000

R2

44

650/656

32

13"

500

500

R2

52

7501756

32

13"

450

450

R2

Package

Lead
Count

Package
Width
(mils)

Tape
Width
(mm)

Reel
Siza

SOJ

24

300

24

13"

20/26

300

24

20/26

350

24126

SOIC (Gull Wing)
PLCC

Devlcas

Per
Reel

•
MOTOROLA MEMORY DATA
11-24

Tape and Reel
Data for
MOSMemory
Surface Mount
Devices
PACKAGES

SOJ:

24,20/26,24/26,28,32
28,32

SOIC:
PLCC: 44,52

TAPE AND REEL DATA

CARRIER TAPE SPECIFICATIONS

Dl

~~I).~O~f~~~NTS

..

FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND BO

AND LARGER

USER DIRECTION OF FEED

'TOP COVER
TAPE THICKNESS (11)
0.10mm
(0.004") MAX.

RMIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS "R"
WITHOUT DAMAGE

EMBOSSMENT

TYPICAL
COMPONENT CAVITY
CENTERLINE

I

--'1--L

TYPICAL
~ COMPONENT
CENTERLINE

lmm
(0.039') MAX

CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mrnllCO mm NONACCUMULATIVE OVER 250 mm

DIMENSIONS
Tape

Size

B1 Max

0

01

E

F

K

P

Po

P2

RMln

IMax

W

24mm

19.4mm
(0.764")

1.5+0.1 mm
-0.0
(0.059+0.004"
-0.0)

2.0mm
Min
(0.079")

1.75
±D.l mm
(0.069
±D.004")

11.5
±D.l mm
(0.453
±D.C04")

4.0mm
(0.157")

12.0-16.0
±D.l0mm
(0.472-0.630
±D.C04')

4.0
±D.lmm
(0.156
±D.004")

2.0
±D.05mm
(0.079
±D.002")

50mm
(1.9681

0.400mm
(0.0161

24
±D.2mm
(0.945
±D.C08")

32mm

23.0mm
(0.9061

1.5+0.1 mm
-0.0
(0.059+0.004"
-0.0)

2.0mm
Min
(0.079")

1.75
±D.l mm
(0.069
±D.004")

14.2
±D.l mm
(0.559
±D.C04")

10.0mm
(0.394'1

16.0-24.0
±D.l0 mm
(0.630-0.945
±D.C04")

4.0
±D.l mm
(0.156
±D.C041

2.0
±D.05mm
(0.079
±D.C02')

50mm
(1.968")

0.500mm
(0.020')

32
±D.3mm
(1.26
±D.0121

Metric Dimensions Govern-English are in parentheses for reference only.
NOTE 1: AQ, Bo, and Ko are determined by compnent size. The clearance between the components and the cavity must be within 0.05 mm
min to 0.50 mm max. The component cannot rotate more than 10' within the determined cavity

MOTOROLA MEMORY DATA
11·25

II

TAPE AND REEL DATA

REEL DIMENSIONS
Metric Dimensions Govern-English are In Parentheses for Reference only.

--I

r?:-II~I'5mmMIN
,

f-tMAX

13.0 mm iO.2 mm
(0.512" iO.OO6j

~
"..........
2O'2mmMIN~_
0'7951~_ J
(0.06j

A

~
I

f

SOmmMIN
(1.969j

~

' ...... _""
FULL RADIUS

--ll--G
Size
24mm
32mm

A Max
330mm
(12.992")

G
24.400 mm, +2.0 mm, -0.0
(0.961", +0.079", -0.00)

tMax
30.4 mm
(1.197")

330mm
(12.992")

32.4 mm, +2.0 mm, -0.0
(1.276", +0.079", -0.00)

38.4 mm
(1.51")

TAPE ENDS

r

0

00001 00000

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TRAILER
NO COMPONENTS - _ ."'..~- COMPONENTSI--••"'..- soo mm MIN
(19.7" MIN)

•

DIRECTION OF FEED

m
MOTOROLA MEMORY DATA
11-26

0000000

-')
I
I

r

-,r -,

I
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I
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LEADER
NO COMPONENTS
soo mm MIN
(19.7" MIN)

I

-----I

Sele~or Guide and Cross Reference

CMOS Dynamic RAMs •
DRAM Modules •
General MOS Static RAMs •
CMOS Fast Static RAMs

II

CMOS Fast Static RAM Modules •
Application Specific MOS Static RAMs •
Military Products •
Reliability Information •

II
Mechanical Data III

Applications Information

MOTOROLA MEMORY DATA

Selector Guide and Cross Reference

•

CMOS Dynamic RAMs

. . DRAM Modules
•

General MOS Static RAMs

•

CMOS Fast Static RAMs

III

CMOS Fast Static RAM Modules

•

Application Specific MOS Static RAMs

•

Military Products

. . Reliability Information

m

Applicationslnformation

m

Mechanical Data
MOTOROLA MEMORY DATA
1ATX16685·10 PRINTED IN USA 3/92 CUSTOM PRINTING CMTR6693 15,000 MemMOS YHAAAA
1991_Motorola_Memory_Device_Data 1991 Motorola Memory Device Data

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