1992_Fujitsu_Telecommunications_Products_Data_Book 1992 Fujitsu Telecommunications Products Data Book
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Telecotlltllunications
Products
1992 Data Book
1992
.0
FU'ITSU
Prescalers
Phase-Locked Loops (PLLs)
Single-Chip PLLs/Prescalers
Single-Chip VCOs/Prescalers
Piezoelectric Devices
Cordless Telephone Integrated Circuits
Telephone Integrated Circuits
D
EI
m
10
iii
0
III
Coders/Decoders (CODECs)
m
Quality and Reliability
iii
Ordering Information
mJ
Sales Information
iD
Appendix: Design Information
[fJ
cO
FUJITSU
Telecommunication Products
1992
Data Book
Fujitsu limited
Tokyo. Japan
Fujitsu Microelectronics. Inc.
Son Jose. California. U.S.A.
Fujitsu Mikroelektronik GmbH
Frankfurt. F.R. Germany
Fujitsu Microelectronics Asia PTE Limited
Singapore
© 1991 Fujitsu MicroeieC1ronics, Inc., San Jose, Califomla
All Rights Reserved.
Circuit diagrams using Fujitsu products are included to iIIustrale typical semiconductor applications. Information sufficient for
construction purposes may not be shown.
The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu
MlcroeleC1ronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any Uc:ense under the copyrights, palent rights or trademarks
claimed and owned by Fujitsu Umited, its subsidiaries, or Fujitsu Microeleotronics, Inc.
Fujitsu MlcroeleC1ronics, Inc. reserves the right to change products or specifications without notice.
No part of this pubrlCBtion may be copied or reproduced in any form or by any means, or transferred to any third party without prior
written consent of Fujitsu Microelectronics, Inc.
This document is pubUshed by the PubUcations Department, Inlegraled Circuits Division, Fujitsu MIcroeleC1ronics, Inc.,
3545 North First Street, San Jose, Califomia, U.S.A. 95134-1804; U.S.A.
Printed in the U.S.A.
Edition 1.0
PREFACE
This data book contains the latest product information for Fujitsu's line of Telecommunications Products. This
year's edition includes Piezoelectric Devices and IC Compandors, as well as sustaining products from the previous edition. Please note thatthe contents ofthis edition have been reorganized to betlercategorize products
for your ease of use.
In addition to the collection of data sheets, you will find valuable information on ordering and expanded packaging descriptions, both in the Order Information section. One appendix, Design Information, is included as a
guideline for selecting and designing Fujitsu prescalers and phase-locked loops for VH F and UHF frequency
synthesis.
If you are interested in obtaining other Fujitsu product information, see the publication listing on the following
pages for titles and brief descriptions of other Fujitsu product literature. To obtain a copy of any of the documents, contact one of our sales offices.
iii
Telecommunications Data Book
FUJITSU PRODUCT PUBLICATIONS
The following is a list of the product publications available from Fujitsu Microelectronics, Inc. Call your nearest FMI Sales
Office or Sales Representative to order any document(s) you need. (See the Sales Information section for phone numbers.)
STANDARD PRODUCTS
Dynamic RAM Products Data Book
Contains product data sheets for NMOS and CMOS DRAMs,
including 1M and 4M devices, and MOS application-specific
RAMs.
Static RAM Products Data Book
Contains product data sheets for high-speed CMOS and
BiCMOS SRAMs, low-power CMOS SRAMs and applicationspecific SRAMs.
ECl RAM Products Data Book
Contains product data sheets for ECl and TTL bipolar ECl
RAMs, BiCMOS ECl RAMs, and application-specffic RAMS
including seH-timed RAMs (STRAMs).
Programmable Memory Products Data
Book
Contains product data sheets for programmable ROMs (including
registered and wide-temperature range PROMs); CMOS maskprogrammable ROMS, OTP ROMs, erasable PROMs, and
EEPROMs; NMOS erasable PROMs and non-volatile RAMs.
Memory Card Products Data Book
Contains product data sheets and programming information for
58-pin JEIDA and PCMCIA standard memory cards and connectors and for 38-pin memory cards.
Power Transistor Products Data Book
Contains product data sheets for RETs, Darlington arrays, and
FETs.
Linear Products Data Book
Contains product data sheets for audio products, power supply
controls, motor drivers, disk drivers, and converters (AID, D/A,
AID-D/A, and FN), and other linear products.
Linear Products Selector Guide
Presents an overview of linear products.
Telecommunication Products Data Book
Contains product data sheets for prescalers and VCOS, Plls,
single-chip Plls and Prescalers, CODECs, telephone ICs, and
cellular telephone ICs, cordless telephone ICs, and piezoelectric
devices.
Telecommunication Devices Selector Guide Presents an overview of telecommunication products and piezoelectric devices.
Interface and Logic Products Selector
Guide
Presents an overview of logic and interface devices.
CMOS 4-b~ Microcontrollers Data Book,
Contains product information, including the development tool for
the MB8850 and MB88200 families of 4-b~ microcontrollers.
Vol. I
CMOS 4-b~ Microcontrollers Data Book,
Vol. II
Contains product information, including the development tool for
the MB88500 family of 4-M microcontrollers.
CMOS 4-b~ Microcontrollers Selector
Guide
Presents an overview of the MB88500 (high end), MB8850 (midrange), and MB88200 (low end) families of 4-b~ microcontrollers.
Master Product Guide
Presents an overview of the entire range of products offered by
the Integrated Circu~ Division: Standard and ASIC products.
Iv
Telecommunications Data Book
FUJITSU PRODUCT PUBLICATIONS (Continued)
ASIC PRODUCTS
CMOS Channeled Gate Arrays Data Book
and Design Evaluation Guide
Contains product information for UHB Series High Drive CMOS
Gate Arrays and CG10 Series High Drive CMOS Gate Arrays.
CMOS Channelless Gate Arrays Data
Book and Design Evaluation Guide
Contains product information for AU Series CMOS Series Gate
Arrays and CG21 Series CMOS Gate Arrays.
ASIC Products Selector Guide
Presents an overview of CMOS, BiCMOS, ECl, and GaAs gate
arrays and CMOS standard cell products.
BiCMOS Gate Arrays Data Book and
Design Evaluation Guide
Contains product information for BC Series BiCMOS Gate
Arrays and BC-H Series BiCMOS Gate Arrays.
ECl Gate Arrays Data Book and Design
Evaluation Guide
Contains product information for ET Series ECl Gate Arrays,
H Series ECl Gate Arrays, UHra-High Performance ECl Gate
Arrays, and VH Series ECl Gate Arrays.
ASIC SOFTWARE
The ASIC GalieryTM (catalog)
Discusses the trend in ASICs: migration from using gates as
primitives to using lSI and even VlSI macros as design elements.
The ASIC Design Environment (catalog)
Provides an overview of the third-party tools that work in concert
with Fujitsu's proprietary tools, ViewCADTM, BankCADTM, and
FAME. Also included are product profiles explaining how the
third-party tools fit within the design framework.
ViewCAD User's Guide
Provides a basic understanding of Fujitsu's proprietary CAD/CAE
system, ViewCAD. This book provides information necessary to
design, test, simulate, and analyze circuits using Fujitsu's unit cell
libraries for AU, UHB, CG10, CG21, and CG31 CMOS technologies.
ViewCAD Installation Guide
Explains how to install Fujitsu's proprietary CAD/CAE system,
ViewCAD.
CMOS ASIC Reference Manual for
Valid
Provides a basic understanding of the Valid System on the Sun
platform as it interfaces with Fujitsu programs to build circuits
using Fujitsu's unit cell libraries for AU and UHB CMOS technologies.
FAME User's Guide
Provides a basic understanding of the Fujitsu ASIC Management
Environment (FAME) software as it interfaces with third-party
tools (Sun or PC) to build circuits using Fujitsu's unit cell libraries.
FAME Reference Manual
Provides installation and directory information for the Fujitsu
ASIC Management Environment (FAME) software, which uses
third-party tools (Sun or PC) to build circuits using Fujitsu's unit
cell libraries.
Synopsys User's Guide
Provides a basic understanding of the Synopsys® system as it
interfaces with Fujitsu programs to build circuits using Fujitsu's
unit cell libraries.
v
FUJITSU PRODUCT PUBLICATIONS (Continued)
ASIC SOFTWARE (Continued)
Verilog-XL User's Guide
Provides a basic understanding of the Verilog-XL® system as it
interfaces with Fujitsu programs to build circuits using Fujitsu's
unit cell libraries.
Future Publlcal/ons
For Memory Ptoducts:
Hybrid Products (1992)
Presents Fujitsu's hybrid products and discusses thick- and thin-film
capabilities.
For ASIC Software:
ASIC Design Environment
Data Book (1992)
Provides detailed information about the ASIC Design Methodology
at Fujitsu. It contains an overview of the third-party tools that work
in concert with Fujitsu's proprietary tools, ViewCAD, BankCAD, and
FAME. Also included are product profiles explaining how the thirdparty tools fit within the design framework.
Synopsys® is a registered trademark of Synopsys, Inc.
Verilog-XL® is a regis1Bred trademark of Cadence Design Sys1Bms, Inc.
ViewCAOTM and BankCAOTM are trademarks of Fujitsu Umited.
ASIC GaHeryTM is a trademark of Fujitsu Microelectronics, Inc.
vi
Contents and Alphanumeric Product List
Fujitsu's Telecommunication Products
Introduction
......................................................... vii
Section 1- Prescalers MB467
MB501/L
503
504/L
MB501LV
MB504LV
MB501SL
MB505-16
MB506
MB507
MB508
MB509
MB510
MB511
At a Glance ........................................ 1-1
200 MHz Low Power High Frequency Prescaler ................... 1-3
1.0/1.1 GHz Two Modulus Prescaler .......... " ................ 1-11
200 MHz Two Modulus Prescaler .............................. 1-11
520 MHz Two Modulus Prescaler ....•......................... 1-11
1.1 GHz Low Voltage/Low Power Two Modulus Prescaler ........... 1-23
520 GHz Low VoltagelLow Power Two Modulus Prescaler ........... 1-23
1.1 GHz Super Low Power Two Modulus Prescaler ................ 1-33
1.6 GHz Ultra-high Frequency Prescaler ........................ 1-43
2.4 GHz Ultra-high Frequency Prescaler ........................ 1-47
1.6 GHz Two Modulus Prescaler ............................... 1-51
2.3 GHz Two Modulus Prescaler ............................... 1-59
1.1 GHz Two Modulus Prescaler with Stand-by Mode .............. 1-67
2.7 GHz Two Modulus Prescaler ............. " ................ 1-75
1.0 GHz High-speed Prescaler ................................ 1-83
Section 2 - Phase-Locked Loops (PLLs) MB87001A
MB87006A
MB87014A
MB87076
MB87086A
MB87087
MB87090
Section 3 - Single-Chip PLLs/Prescalers MB1501
1501H
1501L
MB1502
MB1503
MB1504
1504H
1504L
MB1505
MB1507
At a Glance ....................... 2-1
13 MHz CMOS Serial Input PLL Frequency Synthesizer ............. 2-3
17 MHz CMOS Serial Input PLL Frequency Synthesizer ............ 2-15
CMOS Serial Input PLL Frequency Synthesizer
with 180 MHz Prescaler ..................................... 2-27
13 MHz CMOS Serial Input PLL Frequency Synthesizer
With Power Down Mode ..................................... 2-37
15 MHz CMOS Serial Input PLL Frequency Synthesizer ............ 2-51
17 MHz CMOS Serial Input PLL Frequency Synthesizer ............ 2-61
13 MHz CMOS Serial Input PLL Frequency
Synthesizer with Constant Current Output Charge Pump ............ 2-73
At a Glance ....................... 3-1
Serial Input PLL Frequency Synthesizer with 1.1 GHz Prescaler ....... 3-3
Low Power Serial Input PLL Synthesizer with 1.1 GHz Prescaler ..... 3-21
Serial Input PLL Frequency Synthesizer with 1.1 GHz Prescaler ...... 3-35
Serial Input PLL Frequency Synthesizer with 520 MHz Prescaler ..... 3-49
Serial Input PLL Frequency Synthesizer with 600 MHz Prescaler ..... 3-67
Low Power Serial Input PLL Frequency Synthesizer with 2.0 GHz
Prescaler ................................................. 3-79
vii
Contents and Alphanumeric Product List (Continued)
MB1508
MB1509
MB1511
MB1512
MB1513
MB1518
MB1519
Serial Input PLL Frequency Synthesizer with 2.5 GHz Prescaler ...... 3-91
Dual Serial Input PLL Frequency Synthesizer with 400 MHz Prescaler 3-101
Low Power and Low Voltage Serial Input PLL Frequency
Synthesizer with 1.1 GHz Prescaler ........................... 3-115
Low Power Serial Input PLL Frequency Synthesizer with 1.1 GHz
Prescaler ................................................ 3-127
Serial Input PLL Frequency Synthesizer with 1.1 GHz Prescaler ..... 3-139
Serial Input PLL Frequency Synthesizer with 2.5 GHz Prescaler ..... 3-153
Dual Serial Input PLL Frequency Synthesizer with
600 MHz Prescaler ........................................ 3-161
Section 4 - Single-Chip VCOs/Prescalers MB551
At a Glance ........................ 4-1
1 GHz Dual Modulus Prescaler with VCO Circuit ................... 4-3
At a Glance ................................ 5-1
SAW-Bandpass Filter Devices ................................. 5-3
Piezoelectric Devices (0100) with VCO ......................... 5-17
Piezoelectric Devices (0300) with VCO ......................... 5-25
Piezoelectric Devices (0001) with VCO ......................... 5-35
Piezoelectric Devices (0101) with VCO ......................... 5-39
Section 5 - Piezoelectric Devices F5CBSeries
M2Series
M2 Series
M3 Series
M3 Series
At a Glance ............. 6-1
Modem with Internal Voice-Band Filters .......................... 6-3
CMOS 1200 bps Minimum Shift Keying Modem ................... 6-25
Section 6 - Cordless Telephone Integrated Circuits MB86460A
MB87002
At a Glance ...................... 7-1
Compandor IC .............................................. 7-3
CompandorlC ............................................. 7-15
Telephone AmplifierfTone Ringer .............................. 7-19
Telecommunication Circuit ................................... 7-31
Subscriber Line Interlace IC .................................. 7-47
Dual Tone Multifrequency Pulse Dialer .......................... 7-57
Section 7 - Telephone Integrated Circuits MB3120
MB3121
MB4513
MB4518
MB4752A
MB87007A
87008A
MB87009
MB87017B
MB87029
MB87057
Dual Tone Multifrequency Pulse Dialer .......................... 7-83
Dual Tone Multifrequency Receiver ............................ 7-111
Dual Tone Multifrequency Pulse Dialer ......................... 7-123
Dual Tone Multifrequency Receiver ............................ 7-149
At a Glance ......................... 8-1
and A-law Single-chip CODEC with Filters ................... 8-3
Section 8 - Coders/Decoders (CODECs) MB6021A
6022A
viii
~-Iaw
Contents and Alphanumeric Product List (Continued)
Section 9 - Quality and Reliability -
At a Glance . ...............................
9-1
Quality Control at Fujitsu ................................................... 9-3
Quality Control Processes at Fujitsu .......................................... 9--4
At a Glance .............................. 10-1
IC Packages, Inserted Types .............................................. 10-3
IC Packages, Surface Mounted Types ....................................... 10-4
Part Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Section 10 - Ordering Information -
At a Glance .................................. 11-1
Fujitsu Worldwide Locations
Fujitsu Limited (Japan) ................................................ 11-3
Fujitsu Microelectronics, Inc. (U.S.A.) ..................................... 11-4
Fujitsu Electronic Devices Europe: ....................................... 11-6
Fujitsu Mikroelektronik GmbH (West Germany)
Fujitsu Microelectronics, Limited. (U.K.)
Fujitsu Microelectronics, Italia S.R.l. (Italy)
Fujitsu Microelectronics, Ireland, Ltd. (Ireland)
Fujitsu Microelectronics Asia PTE Ltd. (Singapore) .......................... 11-8
Integrated Circuits Corporate Headquarters - Worldwide ......................... 11-9
FMI Sales Offices for North and South America ............................... 11-10
FMI Representatives - USA .............................................. 11-11
FMI Representatives - Canada ............................................ 11-14
FMI Representatives - Mexico ............................................ 11-14
FMI Representatives - Puerto Rico ........................................ 11-14
FMI Distributors - USA .................................................. 11-15
FMI Distributors-Canada ............................................... 11-17
FMG, FML, FMIL Sales Offices for Europe ................................... 11-18
FMG, FML, FMIL Distributors - Europe .................................... 11-19
FMAP Sales Offices for Asia, Australia and Oceania ........................... 11-20
FMAP Representatives - Asia and Australia ................................. 11-21
FMAP Distributors - Asia ................................................ 11-21
Section 11 - Sales Information -
Section 12 - Appendix - Design Information
Application Note: Prescalers and PLLs ....................................... 12-1
ix
Contents and Alphanumeric Product List
Telecommunications Products
Alphanumeric List of Fujitsu Part Numbers
Device
Page
Device
Page
F5 Series ..............•..... 5-3
M81508 .................... 3-91
M2 Series (0100) ............. 5-17
M81509 ................... 3-101
M2 Series (0300) ............. 5-25
M81511 ...•............... 3-115
M3 Series (0001) ............. 5-35
M81512 ................... 3-127
M3 Series (0101) ............. 5-39
M81513 ..............•.... 3-139
MB467 ...............•...... 1-3
M81518 •.•...•....••...... 3-153
MBS01 ..................... 1-11
M81519 ................... 3-163
MBS01L •............•...... 1-11
MB3120 ..................... 7-3
MBS01LV ..........•........ 1-23
MBS01SL ...............•... 1-33
MBS03 ••................... 1-11
MBS04 ..................... 1-11
MBS04L ...........•........ 1-11
MBS06 ..................... 1-47
MBS07 •.................... 1-51
MBS08 ..................... 1-59
MBS09 ...•................. 1-67
MBS10 ....•................ 1-75
MBS11 ...................... 1-63
MBS51 ................•....• 4-3
MB3121 ....•............... 7-15
MB4513 .................... 7-19
MB4518 .................... 7-31
MB4752A . . . . . . . . . . . . . . . . . .. 7-47
MB6021A .................... 8-3
M86022A • . . . . . . . . . . . . . . . • . .. 8-3
MB86460A . . . . . . . . . . . . . . . . . .. 6-3
MB87001A ...•............... 2-3
MB87002 ................... 6-25
MB87006A ....•............. 2-15
MB87007A .................. 7-57
M81501 ..................... 3-3
MB87008A .................. 7-57
M81501H .................... 3-3
MB87009 ................... 7-63
M81501L .................... 3-3
MB87014A .................. 2-27
M81502 .................... 3-21
MB870178 ................. 7-111
M81503 .....•.............. 3-35
MB87029 .................. 7-123
M81504 .................... 3-49
MB87057 .................. 7-149
M81504H ................•.. 3-49
MB87076 ................... 2-37
M81504L ................•.. 3-49
MB87086A . . . . . . . . . . . . . . . . .. 2-51
M81505 ..•...•............. 3-67
MB87087 .........•......... 2-61
M81507 .................... 3-79
MB87090 ................... 2-73
11
- - - - - - - - - - - - - - - - - Introduction
I
I
Page
lllle
xi"
Fujitsu's Telecommunication Producls
xi
Introduction
xii
Te!ecommunicatjons Data Book
Fujitsu's Telecommunication Products
Introduction
Fujitsu manufactures a wide range of integrated circuits that
includes linear products, microprocessors,
telecommunications circuits, ASICs, high-speed ECl logic,
power components (consisting of both discrete transistors
and transistor arrays), and both static and dynamic RAMs.
The telecommunication product line offers devices for use in
a wide range of applicatIOns. These telecommunication
products are manufactured to meet the hiQh standard of
quality and reliability that is found in all FUJitsu products.
Prescalers
Fujitsu offers a wide range of prescaler devices capable of
satisfying the technical requirements of today's applications.
Features such as the 200 MHz to 2.7 GHz frequency range,
low power consumption, and a multitude of divide ratios are
some of the advantages of Fujitsu's prescaler family.
Phase-locked loops (Plls)
The Fujitsu family of PlLs offers a wide range of operating
frequencies with low supply currents and voltages to meet
deSign needs. The serial input capability of these devices is
an outstanding feature of Fujitsu's Plls.
Single-Chip PLLslPrescaiers
Fujitsu is one of only a few semiconductor manufacturers to
offer single-chip PlUPrescaler devices. Fujitsu is the only
manufacturer with a BiCMOS version that combines high
speed and low power consumption in a single Chip. With the
increasing emphasis on board space reduction (to improve
cost), reliability, and overall product size, these single-chip
devices provide solutions for designers.
Single-Chip VCOs/Prescalers
Fujitsu is the only semiconductor manufacturer with a
single-chip VCO/Prescaler family of products. With the
increasing emphasis on overall product size reduction and
added on-chip functionality, this new family of devices
provides the needed design solution.
.
Continued on next page
xm
Fujitsu's Telecommunication Devices
Piezoelectric Devices
Fujitsu's lithium tantalate peizoelectric bandpass SAW filters
provide sharp roll-off characteristics and excellent stability
over temperature in a tiny 5 mm x 5 mm surface mount
package. Standard frequencies are available for AMPS,
NTACS, NMT, and ETACS transmit and receive frequencies.
This family of devices also includes a series of voltage
controlled oscillators.
Cordless Telephone Integrated Circuits
Fujitsu's family of cordless telephone ICs offers low power
consumption, ideal for applicatIOn of this type. This family of
products consists of minimum-shift keying modems for data
transfer applications.
Telephone Integrated Circuits
Fujitsu offers a complete family of telephone ICs as an
application-specific product line. These devices are capable
of performing advanced telephone functions such as SLlC,
speech transmission/reception, DTMF, on-hook dialing, last
number repeat, tone amplification, and companding
functions.
Coder/Decoders (CODECs)
The Fujitsu family of CODECs oonsists of the MB6020
series. All devices conform to CCITT and AT&T
specifications.
xlv
Section 1
Prescalers - At a Glance
Page
DevIce
llu:lmum
Frequency
1-3
MB467
1-11
MB501
Divide
Supply
Icc
Vee
Ratio
200 MHz
6mA
5V
1.0GHz
30mA
5V
10120
64165,
Package
Optlona
B1lin
Plastic
DIP,FPT
81lin
Plastic
DIP, FPT
B-pin
Plastic
DIP,FPT
81lin
Plastic
DIP,FPT
1281129
SOIL
1.IGHz
10mA
5V
64/65,
1281129
503
200 MHz
BmA
5V
16117,
32/33
504
520 MHz
10mA
5V
32/33,
64165,
5O4l
520 MHz
SmA
5V
MB501LV
1.1 GHz
12mA
3V
32/33,
64165
64165,
1281129
504LV
520 MHz
6mA
3V
1-33
MB501SL
1.1 GHz
SmA
5V
1-43
MB505-16
1.6GHz
9mA
5V
1281256
B-pin
Plastic
DIP,FPT
1-47
MB506
2.4GHz
lBmA
5V
6411281256
B-pin
Plastic
DIP,FPT
1-51
MB507
1.6GHz
lBmA
5V
1281129,
256/257
B-pin
Plastic
DIP,FPT
1-59
MB508
2.3GHz
24mA
5V
1281130,
256/258,
5121514
B-pin
Plastic
DIP,FPT
1-57
MB509
1.1 GHz
1'.6mA
5V
64165,
8-pin
Plastic
DIP,FPT
1-23
32/33,
64165
64165,
1281129
1281129
1-75
MB510
2.7GHz
10mA
5V
1281144,
256/272
B-pin
Plastic
FPT
l-as
MB511
1.0GHz
23mA
5V
1,2,B
&-pin
Plastic
DIP,FPT
1-1
III
Prescale!S
01
1-2
Telecommunjcations Data Book
00
October 1989
Edition 2.0
FUJITSU
DATA SHEET
MB467
LOW POWER PRESCALER
10
200MHz, LOW POWER PRESCALER
The Fujitsu MB467 is a prescaler, which is used in Phase Locked Loop (PLL) frequency
synthesizer. The MB467 will divide by 10 when SW pin is high (Vee level) and by 20 when SW
pin is low (open or 1/2Vee level). The output is an open coIlectoroutputto drive TTL or CMOS
logic circuit.
o Operating Frequency: 200MH z max.
o
Low Power Cornsumption: 30mW typo
o
Low Level Input Voltage: V,,.;;,l50mV......
o
Wide Operation Temperature: T.:-{lO·C to +85·C
PLASTIC PACKAGE
DIP-08P-M01
o
Power Supply Voltage: Vee=+5V±10%
o
Interface
Input: Capacitor coupling due to internal biased input
Output: Open collector output
o
Plastic B-pin Standard Dual-ln-line' Package: (Suffix:--P)
o
Plastic 8-pin Standard Flat Package: (Suffix: -PF)
PLASTIC PACKAGE
FPT-08P-M01
PIN ASSIGNMENT
IN
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
v",
Symbol
Value
Unit
sw
Supply Voltage
Vee
-0.5 to +7.0
V
OUT
Input Voltage
V,.
-0.5 to Vee
V
Output Current
I.
010+5
mA
Junction Temperature
Tj
+125
OC
Storage Temperature
TsrG
-55 to +150
·C
Nole: ·It should be open.
NOTE:
Permanent device damage may occur if the above Absolute Maximum
Ratl~. are exceeded. Functional operation should be restricted to the
conatiOns as detailed in !he operational sections 01 this data sheet Exposure to
absolute maximum rating conditions lor extended periods may affect device
reliability.
~:.~;or:u~~~r:~~ ~=
:a !:6t~,::~:.
However. it Is advised that normal precautions be taken to
avoid application 01 any voltage higher than maxilrum rated
vonages to this high Inpedanoe circul.
Copyrlgh,O'989 Ill' FUJrrsu LIMITED
1-3
MB467
D
BLOCK DIAGRAM
IN
I-----~Hc
IN
'-----J
AS 01------.
SW 0 - - - - - - - - - 1
CH o---':=~
~H---o OUTPUT
Output
Buffer
SW
Divide Ratio
H
1/10
L
1120
Open
1120
PIN DESCRIPTION
Pin Number
1-4
Function
Symbol
1
IN
Input
2
Vee
DC Supply Voltage Input
3
SW
Divide Ratio Control Input (See Divide Ratio Table)
4
OUT
Output
5
GND
Ground
6
CH
Check Input For Outgoing Test. It should be open.
7
NC
Non Connection
8
IN
Complementary Input
MB467
10
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unll
Min
Typ
5.0
Power Supply Voltage
Vee
4.5
Ambient Temperature
T.
-30
Load Capacitance
CL
Max
5.5
V
+85
·C
7
pF
ELECTRICAL CHARACTERISTICS
-
.
(Vcc-+5V+1D% TA-3D to +85°C)
Value
Parameler
Symbol
Conditions
Unll
Min
Power Supply Current
"lee
High-level Output Voltage
VOH
Low-lewl Output Voltage
VOL
Input Frequency
f'N
Input Signal Amplitude for IN
VIN
Vee-5.0V,
T =25·C
With 2kn pull-up
resistor to Vee
With 2kn pull-up
resistor to Vee
VI N: 150mV.....
sine wave
Typ
Max
6
10
4.0
mA
V
0.4
V
10
200
MH,
150
2000
mV....
1-5
MB467
D
TIMING CHART
o
IN
5
10
15
20
25
I I I I I I I I I I I I I I I I I I I I I I I I I I I
OUT(SW="H")
--.J
OUT(SW="Li
~
TEST CIRICUIT
.---..--...- ..------0 Vcc=+5.0V±100/0
Sampling scope input point
for output waveform
Vee
I
Sampling scope prober point
for input waveform
2
OUT
8
C2
5
GND
C,: 1000p F
c2: 1000p F
C3 :O.1I'F
CL : 7pF (including scope and jig capacitance)
RL : 2Kn
Note: Input frequency has a influence of input signal amplitude, input signal slew rate, and input coupling capacitor value.
The MB467 can operate down to DC when large value of above parameters are selected.
The MB467 starts self-oscillation unless signal is input
When a double drive, please connect either of input pins to GND by a 39 kohms pull down resistor. The oscillation is prevented
easily.
When a single drive, please connect a pull down resistor to unused pin.
1-6
MB467
TYPICAL CHARACTERISTICS CURVE
INPUT SIGNAL AMPLITUDE vs INPUT FREQUENCY
1000
800
"~
2
--....
5
-
1'--....
10
20
50
100
200
500
1000
2000
Input Frequency [MHz!
APPLICATION EXAMPLE
Antenna
1-7
III
MB467
PACKAGE DIMENSIONS
8-LEAD PLASTIC DUAL-IN-LINE PACKAGE
(CASE No.: DIP-4IP-M01)
.370~:81~
INDEX
.244±.010
(6.20±0.25)
.300(7.62)
TYP
~::;:=;==;=r=?I~
.039~Jl12
II
(0.99~g30)
1·060~g12
(1.52~8·30)
.035~:m
.172(4.36) MAX
.118(3.00) MIN
.100(2.54)
TYP
© 19BB FUJITSU LIMITED DOB006S-2C
1-8
.018±.003
(0.46 ± 0.06)
Dimensions in
inches (millimeters)
MB467
III
PACKAGE DIMENSIONS
SUffix: -PF
8-LEAD PLASTIC FLAT PACKAGE
(CASE NO.: FPT-08P-M01)
1
·307±.016
(7.8~±0.40)
INDEX
if
.209±.012
(5.30± 0.30)
~::;:;:::;!;=Y,~~
.050(1.27)
TYP
~,~
.......---f .020±.008
(0.50±0.20)
l.OD6~:gg~(0.15~g:g~)
.018±.004
III ,OD5(0.13)@
(0.45±0.10·
.150(3.81)
r --- -- ---- - -- - -,
t Details of "A" part I
,
REF
"A"
,
.008(0,20):
.020(0.50):
,007(0.18) :
MAX
I
'
.027(0,68) :
MAX
LI ___________ ____ JI
© 1988 fUJITSU LIMITED FOB002S-3C
Dimensions in
inches (millimeters)
1-9
MB467
III
1-10
00
April 1990
Edition 6.0
FUJITSU
DATA SHEET
MB5011501 LI50315041504L
TWO MODULUS PRESCALERS
TWO MODULUS PRESCALERS
The Fujitsu MB 501/503/504 are two modulus prescalers, which are used in
Phase Locked Loop (PLL) frequency synthesizer and will divide the input fre·
quency by the modulus of 64/65 or 1281129, 16/17 or 32/33, and 32/33 or
64165 respectively. MB 501 LIMB 504L is the low·power version of MB 5011
MB 504; it will perform exactly the same function as MB 5011MB 504 but with
much lower power dissipation.
The output is 1.6 V peak to peak on ECL level.
• High Operating Frequency, Low Power Operation.
PLASTIC PACKAGE
DIP·OSP·MOt
1.0 GHzat150mWtyp. (MB501)
1.1
GHz at 50 mW typo (MB 501 L)
200 MHz at 40 mW typo (MB 503)
520 MHz at 50 mW typo (MB 504)
520 MHz at 25 mW typo (MB 504L)
•
Pulse Swallow Function
•
Wide Operation Temperature
T A ~ _40°C to +85°C
•
Stable Output Amplitude
V OUT
•
Complete PLL synthesizer circuit with the Fujitsu MB 87001 A, PLL synthesizer
~
PLASTIC PACKAGE
FPT·OSP·MOt
1.6 Vp.p
PIN ASSIGNMENT
IC
• Plastic 8·pin Standard Dual·ln·Line Package or space saving Flat Package
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Value
Rating
Unit
Supply Voltage
Vee
-0.5 to +7.0
V
I nput Voltage
V IN
-0.5 to Vee
V
Output Current
Va
10
mA
Ambient Temperature
TA
-40 to +85
°c
Storage Temperature
T STG
-55 to + 125
°c
IN
Vee
sw
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.
1-11
MB501
MB501L
MB503
MB504
MB504L
01
Fig. 1 - BLOCK DIAGRAMS
II) MB 5011501 L
OUT
MB 501/
MB 501L
sw
Me
H
H
1/64
H
L
1/65
L
H
1/128
L
L
1/129
Divide Ratio
Note: SW: H = Vee. L = open
Me: H = 2.0 V to Vee.
L= GND to 0.8 V
IN
IN
OUT
MB503
SW
Me
Divide Ratio
H
H
1/16
H
L
1/17
L
H
1/32
L
L
1/33
Note: SW: H = Vee. L = open
Me : H = 2.0 V to Vee.
L= GND to 0.8 V
<:1 MB 5041MB 504L
IN
IN
OUT
MB 5041
MB 504L
SW
Me
Divide Ratio
H
H
1/32
H
L
1/33
L
H
1/64
L
L
1/65
Note: SW: H = Vee. L
2 open
Me: H=2.0VtoV ee •
L = GND to 0.8 V
1-12
MB501
MB501L
MB503
MB504
MB504L
11
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Supply Voltage
Vee
Output Current
10
Ambient Temperature
TA
Load Capacitance
CL
Unit
Min
Typ
Max
4.5
5.0
5.5
1.2
-40
V
mA
+85
°c
12
pF
PIN DESCRIPTION
Pin Number
Symbol
1
IN
2
Vee
DC Supply Voltage
3
SW
Divide Ratio Control Input (See Divide Ratio Table)
4
OUT
Output
5
GND
Ground
6
MC
Modulus Control Input (See Divide Ratio Table)
7
NC
Non Connection
8
iN
Complementary Input
Function
Input
1-13
MB501
MB501L
MB503
MB504
MB504L
ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Value
Symbol
Parameter
Conditions
Unit
Min
Power Supply Current
Typ
Max
MBSOl
30
42'
mA
MBS01L
10
14'
mA
8
12'
mA
MBS03
Icc
I/O pins are
open
MB504
10
14'
mA
MBS04L
S
7"
mA
Output Amplitude
1.0
Va
MBSOl
10
MBS01L
Input Frequency
MBS03
fiN
MBS04
Input Signal Amplitude
for IN
With input
coupling
capacitor
1000pF
MHz
10
1100
MHz
10
200
MHz
10
S20
MHz
MBS04L
10
S20
MHz
-4
S.S
dBm
MBS01L
-4
S.S
dBm
-12
10
dBm
MBS04
-12
10
dBm
MBS04L
-12
10
dBm
MBS03
VIN
V IHM
Low Level Input Voltage for MC
V ILM
2.0
V'HS**
Low Level Input Voltage for SW
VILS
High Level Input Current for MC
IIHM
V IH = 2.0V
IILM
V IL =0.8V
Low Level Input Current for MC
V
0.8
High Level Input Voltage for SW
Vee-0.1
Vee
Vee+0.1
Open
V
V
V
0.4
-0.2
mA
mA
MBSOl
18
28
ns
MBS01L
16
26
ns
MBS03
38
46
ns
MBS04
20
30
ns
MBS04L
18
28
ns
NOTE: • Vee = SV, TA = 2SoC
•• Design Guarantee
1-14
1000
MBSOl
High Level Input Voltage for MC
MoCiulus Set-up Time
MCto OUT
Vp_p
1.6
tSET
MB501
MB501L
MB503
MB504
MB504L
11
MB501/MB501L TIMING CHART (2 MODULUS)
Example: Divide ratio = 64/65
IN
64
65
A
"
IlJl- --JUlll- -M ----- IlJl- --MJ1fl- --M
:
:
•
I
I
I
I
I
•
•
I
I
I
I
I
I
I
•
OUT
•
I
·
J·
:
32
32
..
.'
.'
r
-------
1.
.
32
,,
I
33
,
,,
,
L
MC
.
~
tsET
:
-----:
IsET •
Note: When divide ratio of 65 is selected, positive pulse is applied by one 10 33.
The typical sel up time is 18 ns (MBS01), 16 ns (MBSOI L) from Ihe MC signal input 10 the liming of change of prescaler
divide ratio.
1-15
MB501
MB501L
MB503
MB504
MB504L
01
MB503 TIMING CHART (2 MODULUS)
Example: Divide ratio = 16117
IN
17
"
"
M---JlJ1J1--M -----M---MJ1fl---M
:
•
:
•
I
I
:
•
I
I
•
•
•
•
I
I
•
I
I
•
I
j
OUT
16
8
8
-- .- .---.. .. '
.......
r
-------
1
8
J
-.
.-
9
--
MC
I
I
'"'--IeET
I
Note: When divide ratio of 17 is selected, positive pulse is applied by one to 9.
The typical set up time is 38 ns from the MC signal input to the timing of change of prescaler divide ratio.
1-16
L
MB501
MB501L
MB503
MB504
MB504L
MB504/MB504LV TIMING CHART (2 MODULUS)
Example: Divide ratio = 32133
32
r---------~A~
IN
33
~--------~A~----------~
JlJl---JLfUl---M -----JlJl---JlJlM ---M
:
:
I
:
'
I
I
I
I
,
I
I
I
I
I
I
I
I
I
I
I
j
OUT
________~
16
f -- -- --- 1~__16_~, .
,.
16_--.-J
J--_ _
,,
17
L
MC
I
I
I
~
I
IsET
Note: When divide ratio of 33 is selected, positive pulse is applied by one to 17.
The typical set up time is 20 ns (MB504), 18 ns (MB504L) from the MC signal input to the timing of change of prescaler
divide ratio.
1-17
MB501
MB501L
MB503
MB504
MB504L
III
Fig. 2 - TEST CIRCUIT
r--~----~------O Vee =
+ s.O V ± 10%
Sampling scope input point
for input waveform
Sampling scope prober point
for output waveform
Vee
P.G.
C==rJ-T---I
OUT~--.--~---{J
IN
MC
GND
Me input
C, : 1000pF
C2 : 1000pF
C3: O.l/lF
C L : 12pF (including scope and jig capacitance)
R~:2Kn
TYPICAL CHARACTERISTICS CURVES
Fig. 3 - INPUT SIGNAL AMPLITUDE
;;
.s.
INPUT FREQUENCY
1000
MBSOl
.s
Vee = S.OV
TA =2S'C
w
o
::J
I-
800
:::;
Q.
:;;
«
..J
«
600
Z
Cl
iii
I-
400
::J
Q.
~
:;;
::J
;;;
200
l"-..
Z
~
0
10
..........
r'--
20
so
-'
100
200
INPur FREQUENCY (MHz)
1-18
SOO
1000
2000
MBS01
MBS01L
MBS03
MBS04
MBS04L
III
TYPICAL CHARACTERISTICS CURVES (continued)
Fig. 4 - INPUT SIGNAL AMPLITUDE vs. INPUT FREQUENCY
1000
:;
E
w
0
::>
::;
Vee! 5.0V
TA = 25°C
MB50l L
800
I0..
::E
600
«
I-
::>
0..
~
::E
::>
~
z
400
200
~
o
10
20
50
100
200
INPUT FREQUENCY (MHz)
500
1000
2000
Fig. 5 - INPUT SIGNAL AMLITUDE vs. INPUT FREQUENCY
1000
:;
E
MB50~
Vee = 5.0V
TA = 25°C
800
w
0
::>
I-
::;
600
0..
::E
«
I-
::>
400
0..
~
::E
::>
~
200
z
~
0
r--r-10
20
50
100
200
INPUT FREQUENCY (MHz)
500
Fig. 6 - INPUT SIGNAL AMPLITUDE vs. INPUT FREQUENCY
1000
:;
E
w
0
MB50l
Vee = 5.0V
TA=25°C
800
::>
I::; 600
0..
::E
«
I-
::> 400
0..
~
::E
::> 200
~
z
~
o
r--..r-10
20
50
100
200
INPUT FREQUENCY (MHz)
....-~
500
1000
1-19
ill
MB501
MB501L
MB503
MB504
MB504L
TYPICAL CHARACTERISTICS CURVES (continued)
Fig. 7 - INPUT SIGNAL AMPLITUDE vs. INPUT FREQUENCY
:>
E
w
§
I-
1000
MB50~L
Vee = 5.0V
TA =25°C
800
:::;
D.
::0
«
..J
600
«
z
<.?
in
400
I-
:::>
D.
~
::0
:::>
::0
200
~
o
Z
10
20
50
100
200
500
1000
INPUT FREQUENCY (MHz)
Fig. 8 - TYPICAL APPLICATION EXAMPLE
Vsx (Max. B VI
10Kn
12Kn
9
OUTPUT
MB 87001 A
12Kn
l00Kn
ClockQ-----..---DamQ---~-+_----
33Kn
LEo-~~+__+--------~
XI
: 12.B MHz X'tal
Vee: 5V±10%
Vsx : BV Max.
e 1. C2: depends on crystal oscillator
~~:o---~--------------------'
10Kn
An example of application of MB501/501 L/503/504/504L with PLL Synthesizer IC MB87oo1 '"
1-20
MB501
MB501L
MB503
MB504
MB504L
PACKAGE DIMENSIONS
8-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-08P-M01)
INDEX
.244±.010
(6.20±0.25)
.300(7.62)
TYP
1Jr::::i=i=:::r=;==::r;r=;:Y~
039~g12
I
I.
(0.99~g~0)
1·060~g12
(152~g30)
035~:81~
.172(4.36) MAX
.020(0.51) .118(3.00) MIN
MIN
.100(2.54)
TYP
.. 1988 FUJITSU LIMITED 0
>
E 1000
E1000
w
.
Vee= 3.0V
TA = 2S'C
MB501 LV
o
:J
f-
~
in 400
..
f:J
f:J
z
200
200
::;;
::;;
:J
f--
:J
~
600
l!l
l!l
in 400
~
Vee = 3.0V
TA=25°C
..
«
z
«
Z
MBS04LV
o
~
::;;
z
Z
w
:::; 800
800
:::;
::;;
~ 600
..
Fig. 4 - INPUT SIGNAL AMPLITUDE
vs. INPUT FREQUENCY
Ii.
o
10
20
50
100
200
500
INPUT FREQUENCY (MHz)
1000 2000
~
Z
~
I0
10
20
50
100
200
500
1000
INPUT FREQUENCY (MHz)
1-29
MB501LV
MB504LV
01
Fig. 5 - TYPICAL APPLICATION EXAMPLE
Vsx (Max. 8 V)
OUTPUT
MB 87001 A
CIOCk~==~=+==='-J
Data C
LE
XI
12.8 MHz X'tal
Vee
+2.7V to +4.5V
8V Max.
Vsx
C1,C2
~:'~~----~r---------------------------------------~
10KO
1-30
depends on crystal oscillator
MB501LV
MB504LV
PACKAGE DIMENSIONS
8-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-08P-M01)
.370
tg1~
INDEX
.244±.010
(6.20±0.25)
.300(762)
TYP
~=;:::;::=:::r:;:=;:Y~
039~g12 I I
(099~g30)
.1060~g12
(1.52~g·30)
.1 72(4.36) MAX
.118(3.00) MIN
.100(2.54)
.D18±.003
TYP
(0.46±0.08)
© 1988 FUJITSU LIMITED D08006-2C
Dimensions in
inches (millimeters)
1-31
MB501LV
MB504LV
01
PACKAGE DIMENSIONS (Continued)
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-08P-M01)
.089(2.25) MAX
(SEATED HEIGHT)
.002(0.05) MIN
(STAND OFF)
INDEX
if
""',..---t .020±.008
(0.50±0.20)
1-.006~:gg~(0 15~g:g~)
.050(1.27)
TYP
''A''
,
.020{0.50):
,007(0.18) :
MAX
I
I
.027(0.68) :
,L _______________
MAX
JI
@
1-32
1988 FUJITSU LIMITED F08002S·3C
Dimensions in
inches (milDmeters)
May 1990
Edition 3.0
FUJITSU
DATA SHEET
11
MB501SL
SUPER LOW POWER TWO MODULUS PRESCALER
SUPER LOW POWER TWO MODULUS PRESCALER
The Fujitsu MB501SL is a super low power version of MB501 two modulus prescaler used in
Phase Locked Loop (P LL) frequency synthesizer and divides the input frequency by the
modulus of 64/65 or 128/129. respectively. The MB501SL achieves extremely small stay
capacitance of internal element, realized through the use of Fujitsu Advanced Process
Technology. As the results, high speed operation is achieved with low power supply cunrent
of 5 mA typ., about a half cunrent value of MB501 L.
PLASTIC PACKAGE
DIP-08P-M01
•
High Frequency Operation
fmax = 1.1 GH z max. (V'N = -14bBm)
•
Pulse Swallow Function:
64165, 128/129
•
Low Power Supply Current:
5.0mA typo
•
Stable Output Amplitude:
Vo =1.6Vp-p typo
•
Complete PLL synthesizer circuit with the Fujitsu MB87001A, PLL synthesizer IC
•
Plastic 8-pin Dual-In-Line Package
PLASTIC PACKAGE
FPT-08P-M01
Plastic 8-pin Mini Flat Package
•
Built-in Termination Resistor
Stable output amplitude is obtained up to output load capacitance of 8 pF.
PLASTIC PACKAGE
FPT-08P-M02
PIN ASSIGNMENT
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Symbol
Value
Unit
Power Supply Voltage
Vee
-0.5 to +7.0
V
Input Voltage
V,N
-0.5 to Vee
V
10
10
mA
TSTG
-55 to +125
DC
Output Current
Storage Temperature
NOTE:
Permanent device damage may occur if the above Absolute Maximum
Ratin\Js are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
=--;ue~~hr9~~~~ ~= ~re ~::ric,:~:~
However. it • advised thai normaf precautions be taken to
avoid appIicaUon of anyvollage hlgherthan maximum rated
voltages to this high irJ1)8dance circuit.
Copyright .. ,990 by FUJITSU LIMITED
1-33
MB501SL
III
Fig. 1 - MB501 SL BLOCK DIAGRAM
l:>+-oOUT
MB501SL
SW
MC
H
H
Divide Ratio
1164
H
L
1/65
L
H
11128
L
L
11129
Note: SW: H = Vee. L = open
MC: H = 2.0V to Vee.
L = GND to O.SV
PIN DESCRIPTION
1-34
Description
Pin Number
Symbol
1
IN
Input
2
Vee
Power Supply. +5V
3
SW
Divide Ratio Control Input (See Divide Ratio Table)
4
OUT
Output
5
GND
Ground
6
MC
Modulus Control Input (See Divide Ratio Table)
7
NC
Non Connection
8
m
Complementary Input
MB501SL
10
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
Typ
Max
Power Supply Voltage
Vee
4.5
5.0
5.5
V
Operating Temperature
T.
-40
-
+85
"C
Load Capacitance
CL
-
-
8
pF
ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Value
Parameter
Symbol
Power Supply Current
lee
Output Amplitude
Vo
Condition
-
Unit
Min
Typ
Max
-
5.0
7.0
mA
1.0
1.6
-
Vp.p
Built-in a termination
resistor.
Load capacitance = SpF
Input Frequency
fin
With input coupling
capacitor l000pF
10
-
1100
MHz
Input Signal Amplitude
V'N
-
-14
-
0
dBm
High Level Input Voltage for MC
V1HM
-
2.0
-
-
V
Low Level Input Voltage for MC
VILM
-
-
-
0.8
V
V1HS•
-
Vee-O. 1
Vee
Vee + 0.1
V
Low Level Input Voltage for SW
VIU>
-
High Level Input Current for MC
IIHM
V'H = 2.0V
-
-
0.4
rnA
Low Level Input Current for MC
I'LM
V'L=0.8V
-{).2
-
-
rnA
Modulus Set-up Time MC to Output
!sET
-
-
16
26
ns
High Level Input Voltage for SW
OPEN
V
Note: • Design Guarantee
1-35
MB501SL
III
Fig. 2 -TEST CIRCUIT
Vee = +5.0V ±10%
Sampling scope input point
for input wawform
I
~B-t---iC'
Sampling scope prober point
for output waveform
Vee
OUT~----~-------o
IN
P.G.1..-
GND
MCinput
C, : l000pF
C.: l000pF
C3 :O.IIlF
CL : 8pF(including scope and jig capacitance)
TWO MODULUS OPERATING TIMING CHART
Example. Divide Ratio of 64/65
IN
64
65
r~----------'~'--------~,
r~--------~~'--------~'
JUl-.11.fl1l--Jlf1:----:fUl---n
n n no-oM
..IUYUL
•
I
j
OUT
MC
32
I
32
.... -_ ..... --_...
I
I
I
I
•
[.---'---1
•
I
32
",,"
"
33
.... "
~I_.~. . I.
~:
I teET'
L
.... -
.
~:
•
!sET •
Notes:
When divide ratio of 129 is selected, positiw pulse is added by one to 65.
The typical set up time(lsEr) is 16 ns from MC signal input to the timing of change of prescaler divide retio.
1-36
MB501SL
III
TYPICAL CHARACTERISTICS CURVES
Fig. 3 - INPUT SIGNAL AMPLITUDE VS. INPUT FREQUENCY
T. = 25°C
Vee = 4.5V
Vee = 5.0V
Vee = 5.5V
DATASHEET SPEC
1.0
0.8
1.2
1.4
INPUT FREQUENCY f'N(GHz)
Fig. 4 -INPUT SIGNAL AMPLITUDE VS. INPUT FREQUENCY
Vee = 5.0V
E
~
10
c
0
-tw
:::>
T. =-40°C
T.=25"C
T. = 85°C
5
Q..
:;;
«
«
z
~
DATASHEET SPEC
-10
Cl
iii
I-
:::>
Q..
~
-20
:;;
:::>
:;;
Z
~
-30
0.8
1.0
1.2
1.4
INPUT FREQUENCY f'N(GHz)
1-37
MB501SL
ill
Fig. 5 - POWER SUPPLY CURRENT VS. POWER SUPPLY VOLTAGE
-~
"
....z
6.0
W
II:
II:
::::>
o
~
5.0
II.
II.
::::>
en
II:
~
4.0
--------4.5
~
.-- ~
5.0
POWER SUPPLY VOLTAGE Vee (V)
5.5
Fig. 6 - POWER SUPPLY CURRENT VS. TEMPERATURE
<"
]
6.0
....z
W
II:
II:
::::>
0
~
5.0
II.
II.
::::>
en
V
II:
w
~
4.0
-20
~
~
~
o
20
40
TEMPERATURE T.(OC)
--60
I-
80
Fig. 7 -INPUT SIGNAL VS. INPUT FREQUENCY
E
0
~
II.
::;;
DATASHEET SPEC
-<
...J -10
-<
z(!l
iii
....::::>
II.
~
-20
::;;
::::>
::;;
Z
~
-30
-r-------10
1-38
100
INPUT FREQUENCY (MHz)
~
I
1000
J
MB501SL
Fig. 8-TYPICAL APPLICATION EXAMPLE
Vsx(Max.BV)
16 15 14 13 12 11 10 9
OUTPUT
MB87001A
Clock
0 - - - -_ _- . - . 1
Data o - - - _ - - + - - - - - l
LE~~--t__r--------~
Vee
Vsx
12.8MHz x·taI
5V± 10%
BV Max.
C,. C.
depends on crystal osillator
XI
----------------.-.I
Locko-_ _ _
Det.
10kn
1-39
MB501SL
PACKAGE DIMENSIONS
8-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-08P-M01)
.370~:g1~
INDEX
.244±.010
(6.20±0.25)
.300(7.62)
TYP
~:::;::::;:::::=;:::::?I~
.039~6112
J060~g12
II
(0.25±0.05)
(1.52~g30)
(0.99~g30)
.035~:g1i
.172(4.36) MAX
.118(3.00) MIN
.100(2.54)
TYP
"'988 FUJITSU LIMITED 1J08OO6S.2C
1-40
II
.0181..003
(0.46 t 0.08)
Dimensions in
inch.. (mJimol...)
MB501SL
PACKAGE DIMENSIONS (Continued)
10
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-OSP-M01)
.089(2.25) MAX
(SEATED HEIGHT)
-1 r
.307±.016
(7.8~±0.40)
INDEX
cf
.209±.012
(5.30±0.30)
.050(1.27)
..
TYP
J
J I
_. i
.018±.004
1(0.45±010
$ ¢.005(0.13)@i)
.268 ~gbg(680 ~ g~g)
R
1.
1. 020 ±.008
(0.50±0.20)
006+.002(015+0.05)
.
-.001· -0.02
lS.~.:!llli
REF
··A"
,
.020(0.50):
.007(0.18) :
MAX
'
.027(0.68) :
_______________
MAX
J'
Dimensions in
..1988 FUJITSU LIMITED F08OO2S·3C
incheo(rriUi.......)
1-41
III
MB501SL
PACKAGE DIMENSIONS (Continued)
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-OSP-M02)
.199~86g
0
·061 ±.008 (SEATED HEIGHT)
(1.55±0.20)
(g~65"±g~0) (STAND
OFF)
1
.191±.012
(5.00±0.30)
1-1
-
1.020±.008
(0.50±0.20)
.008+.002
(0.20±0.05)
UA·'
.016(0.40)
~
.008(0.20)
.150(3.81)
.007(0.18)
MAX.026(0.65)
MAX
_. ___________ J
REF
Dimensions in
01988 FUJITSU LIMITED F08OO4S-2C
1-42
Inches (millimeters)
cO
FUJITSU
June 1991
DATA SHEET
MBSOS-16
Ultra High Frequency Prescaler
ULTRA HIGH FREQUENCY PRESCALER
The Fujitsu MB505 is a high frequency prescaler used in Phase Locked Loop
(PLL) frequency synthesizer and will divide the input frequency by the
modulus of 12B or 256. The output level is 1.6V peak to peak on ECL level.
Its ultra high frequency operation provides wide application range, such as
Direct Broadcasting Satellite System, CATV system, UHF Transceiver, etc.
•
High Frequency Operation
1.6GHz max.
•
Low Power Dissipation
45 mW typo
PLASTIC PACKAGE
DIP'()8P·MOl
• Wide Operation Temperatu re
-40·C to +B5·C
• Stable Output Amplitude
V OUT = 1.6 Vp •P
• Complete PLL synthesizer circuit with the Fujitsu MB B1006A, PLL synthe·
sizer IC
PLASTIC PACKAGE
FPT'()8P-MOl
• Plastic B·pin Standard Dual·ln·Line Package or Flat Package
PIN ASSIGNMENT
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Symbol
Value
Unit
Supply Voltage
Vee
-0.5 to +1.0
V
Input Voltage
VIN
-0.5 to Vee
V
Output Current
10
10
mA
Storage Temperature
TSTG
-55 to +125
'c
Raging
IN
Vee
sw
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
OUT
ThiS device contains ClfcVltry to protect the
inputs against dar:nage due to high static voitages or electric fields. However, it is adVisee
that normal precautions be taken to aVOid
application of any voltage higher than maxImum rated voltages to this high impedance
circuit.
1-43
MBSOS-16
Fig. 1 - MB 505 BLOCK DIAGRAM
Output
Buff.r
""--~
OUT
SW
Divide Ratio
H
1/128
L
1/256
Nota: SW: H = Vee. L
==
open
PIN DESCRIPTION
1-44
Pin Number
Symbol
1
IN
2
Vee
Power Supply Voltage
3
SW
Divide Ratio Control Input Selecting divide ratio (See Divide Ratio Table)
4
OUT
Output
5
GND
Ground
6
NC
No Connection
7
NC
No Connection
8
iN
Complementary Input
Function
Input
MB505-16
III
RECOMMENDED OPERATING CONDITIONS
Value
Unit
Symbol
Parameter
Supply Voltage
Vee
Output Current
10
Ambient Temperature
TA
Load Capacitance
CL
Min
Typ
Max
4.5
5.0
5.5
V
mA
1.2
-40
+85
°c
12
pF
ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Value
Parameter
Symbol
Conditions
Unit
Min
Supply Current
lee
Output Amplitude
Vo
Input Frequency
fiN
Input Signal Amplitude
1.0
with input coupling
capacitor 1000 pF
Typ
Max
9
mA
1.6
VD' D
100
1600
MHz
V IN
0.15
1.2
VD' D
High Level Input Voltage for SW
VIHS
Vee- O.1
Vee- 0.1
V
Low Level Input Voltage for SW
V ILS
Vee
Open
V
Fig. 2 - INPUT SIGNAL AMPLITUDE vs. INPUT FREQUENCY
-"1-
>0. 1000
i
Vee
g
= 5.0V
TA=25'C
w
800
f-
:::;
Q.
~
SOO
..J
<{
Z
t:I
iii
400
f-
...1!;::>
200
:::;;
::>
;;l
z
~
0
V
100
200
500
1000
2000
INPUT FREQUENCY (MHz)
1-45
..
MB505-16
PACKAGE DIMENSIONS
(Suffix: -PI (Suffix: -PF)
I·LEAD PLASTIC DUAL-IN-LiNE PACKAGE
ICASE No.: DIP·oaP·M01'
(j
' '.MAX
'300".~,m
,Dl0dJ02
to.2S~D.05t
'
172'4.36IMAX
.03e::.o°12
~~g~
D' .....1II1o... 'n
,rocn"lmiU'IIItI\tfll i
~~UJ!TSu
\,,'rJI'TECl987 008oo65::1e
8-LEAD PLASTIC FlAT PACKAGE
ICASE No. : FPT·oap·M011
.00210.051
~
~
cJ .
----.
INDEX
--
;
-,,-,-'-050,' 27'
~
.. 307,.016
I 17'8!.'"
.209'.012
15.30tO.2SI"
--1.
-.OlBdX)4
--.1
--10.45:0.10'
QI'UJITSU LIMIT£D 1.7 FOIlIOO2S 2e
1-46
~.oo'"
m
.288::::
t6.80:g:~gJ
------1 .070!.OOS
l~tO.5:!.O.2)
V,ew"A"
H.oos(O.21
tIr2
: i'
:
.02010.51
.0071018)
---w:x-
i
'.~~~.6B1
; .oos:::~
--- 10.15-:::'
Dirn,MtOns ,1'1
IfIcheiimil .. me....1
00
February 1990
Edition 3.0
FUJITSU
DATA SHEET
MB506
UL TRA HIGH FREQUENCY PRESCALER
ULTRA HIGH FREQUENCY PRESCALER
The Fujitsu MB506 is a high frequency prescaler used in Phase Locked Loop
(PLL) frequency synthesizer and will divide the input frequency by the
modulus of 64, 128 or 256. The output level is 1.6V peak to peak on ECL
level.
Its ultra high frequency operation provides wide application range, such as
Direct Broadcasting Satellite System, CATV system, UHF Transceiver, etc.
PLASTIC PACKAGE
DIP·OSP-MOl
•
High Frequency Operation
2.4GHz max.
•
Power Dissipation
90 mW typo
• Wide Operation Temperature
_40°C to +85°C
• Stable Output Amplitude
V OUT = 1.6 Vp. p
•
Complete PLL synthesizer circuit with the Fujitsu MB 87006A, PLL syn·
thesizer IC
•
Plastic 8·pirrStandard Dual·ln-Line Package or Flat Package
PLASTIC PACKAGE
PFT-OSP-MOl
PIN ASSIGNMENT
ABSOLUTE MAXIMUM RATINGS ISee NOTE)
Rating
Symbol
Value
Unit
Supply Voltage
Vee
-0.5 to +7.0
V
Input Voltage
V IN
-0.5 to Vee
V
Output Current
10
10
mA
Storage Temperature
TSTG
-55 to +125
·C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
IN
iiii
Vee
NC
SW1
SW2
OUT
GND
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.
1-47
MBS06
D
Fig. 1 - MB 506 BLOCK DIAGRAM
Output
Buffer
C
C
Q
Q
C
Q
C
OUT
Q
SWI
SW2
Divide Ratio
H
H
L
H
H
L
L
L
1/64
1/128
1/128
1/256
Note: H = Vee. L = open
PIN DESCRIPTION
Pin Number
1-48
Symbol
Function
1
IN
Input
2
Vee
Power Supply Voltage
3
SWl
Divide Ratio Control Input Selecting divide ratio (See Divide Ratio Table)
4
OUT
Output
5
GND
Ground
6
SW2
Divide Ratio Control Input Selecting Divide Ratio (See Divide Ratio Table)
7
NC
No Connection
B
iN
Complementary Input
MB50S
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Supply Voltage
Vcc
Output Current
10
Ambient Temperature
TA
Load Capacitance
CL
Unit
Min
Typ
Max
4.5
5.0
5.5
V
1.2
mA
-40
+85
·C
12
pF
ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Value
Parameter
Symbol
Conditions
Unit
Min
Supply Current
Icc
Output Amplitude
Vo
Input Frequency
1.0
with input
coupling
capacitor
1000 pF
fiN
Input Signal Amplitude
Typ
Max
18
mA
1.6
V p.p
T A =-40·C
to 85·C
100
2200
TA = -40·C
to 60·C
100
2400
MHz
fiN = 100 MHz to 1.3 GHz
-16
5.5
fiN = 1.3 MHz to 2.4 GHz
-4
5.5
V IN
High Level Input Voltage for SW
V IH ;
Low Level Input Voltage for SW
V ILS
dBm
Vcc-0.1
Vcc
Open
V cc +O.l
V
V
Note: 'Design Guarantee
Fig. 2 - INPUT SIGNAL AMPLITUDE vs. INPUT FREQUENCY
-",
>0.
.s
1000
Vcc= S.OV
TA=2SoC
BOO
600
400
200
,
0
100
200
500
1000
2000
INPUT FREQUENCY (MHz)
SOOO
1-49
..
..
MB506
PACKAGE DIMENSIONS
8-LEAD PLASTIC DUAL-IN·UNE PACKAGE
(CASE No.: DIP..Q8P.M01)
8-LEAD PLASTIC FLAT PACJAGE
(CASE No.: FPT-DSP-M01)
.250+·g~
r(6.35~:~)1
---1
~
c/
'!1"'' ','
_J
INDEX
..1
I
wtl
I
.301*.016
(7.81-0.4\
-:0;".""
~-----JtO.4S±O.101
TYP
.039~~'2
~I~~:~!o",
~l
-""
1
JI------
~J~
V',w"A"
.00810.2)
+ 0'6
.268_:008
.0201.008
11O."0.21
I::';~O'"
.02010.51
I
I-o-l~
MAX
I ·OO6:~r
to.'S_O,02)
.11Bj3.0IMIN
IO.99~2J
c
1987 FUJITSU LIMITED 008006S-2C
1-50
Dimensions In
inches (rrillimeters)
Dimensions in
.. 1987 FUJITSU LIMITED F08OO2S·2C
inches (millimeters)
cP
April 1990
Edition 4.0
FUJITSU
DATA SHEET
MB507
1.6 GHz TWO MODULUS PRESCALER
1.6 GHz TWO MODULUS PRESCALER
The Fujitsu MB507 is a 1.6 GHz two modulus prescaler used in Phase Locked
Loop (PLL) frequency synthesizer and will divide the input frequency modulus
of 12S/129 or 256/257.
The output level is 1.6 V peak to peak on ECL level.
•
High Frequency Operation:
1.6 GHz max.
•
Power Dissipation:
90 mWtyp.
PLASTIC PACKAGE
DIP-08p·M01
• Pulse Swallow Function
• Wide Operation Temperature:
-40°C to +S5°C
• Stable Output Amplitude:
V OUT = 1.6 Vp . p
• Complete PLL synthesizer circuit with the Fujitsu MB87001A. PLL syn·
thesizer IC
PLASTIC PACKAGE
FPT·08P-M01
• Package
Standard S·pin Dual·ln·Line Package
Standard S·pin Flat Package
PIN ASSIGNMENT
(Suffix: ·P)
(Suffix: -PF)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Symbol
Value
Unit
IN
Vee
Supply Voltage
Vee
-0.5 to +7.0
V
Input Voltage
VIN
-0.5 to Vee
V
Output Current
10
10
mA
Storage Temperature
TSTG
-55 to +125
°c
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
sw
This device contains circuitry to protect the
inputs against damage due to high static volt·
ages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high impedance
circuit.
1-51
..
MB507
Fig. 1 - MB507 BLOCK DIAGRAM
)0-+--0 OUT
MB 507
SW
MC
H
H
1/128
H
L
1/129
L
H
1/256
L
L
1/257
Divide Ratio
Note: SW: H = Vee. L = opon
MC: H = 2.0 V to Vee. L ~ GND to 0.8 V
PIN DESCRIPTION
Pin Number
1-52
Symbol
Function
1
IN
Input
2
Vee
DC Supply Voltage
3
SW
Divide Ratio Control Input Selecting Divide Ratio (See Divide Ratio Table)
4
OUT
Output
5
GND
Ground
6
MC
Modulus Control Input (See Divide Ratio Table)
7
NC
Non Connection
8
IN
Complementary Input
MB507
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Unit
Symbol
Supply Voltage
Vee
Output Current
10
Ambient Temperature
TA
Load Capacitance
CL
Min
Typ
Max
4.5
5.0
5.5
V
mA
1.2
-40
+85
°c
12
pF
ELECTRICAL CHARACTERISTICS
(Recommended Oparating Conditions unless otherwise noted)
Value
Parameter
Symbol
Conditiol)s
Unit
Min
Supply Current
lee
Output Amplitude
Vo
Input Frequency
fiN
Input Signal Amplitude
1.0
With input coupling
capacitor 1000pF
Typ
Max
18
mA
1.6
V p•p
100
1600
MHz
V IN
-4
10
dBm
High Level Input Voltage for Me
Input
V IHM
2.0
Low Level Input Voltage for MC
Input
V ILM
High Level Input Voltage for SW
Input
V IHS•
Low Level Input Voltage for SW
Input
V ILS
High Level Input Current for MC
Input
IIHM
V IH =2.0V
Low Level Input Current for MC
Input
IILM
V IL = 0.8V
Modulus Set-up Time MC to OUT
tSET
1.6 GHz Operation
Note: • Design Guarantee
Vee-0.1
V
Vee
0.8
V
Vee +O· 1
V
OPEN
V
0.4
-0.2
mA
mA
18
28
ns
1-53
..
..
MB507
Fig. 2 - TEST CIRCUIT
r----1~----_._------__{)
Vee
=
+ 5.0 V
±
10%
Sampling scope input point
for input waveform
sw
Vee
P.G.
c:=:::rr-r---/
Sampling scope prober point
for output waveform
OUT~--.--_._-----{)
IN
MC GND
Me input
C, 1000pF
C2 ; 1000pF
C3 ; O.lI'F
C L : 12pF (including scope and jig capacitance)
R L ; 2Kn
TIMING CHART (2 MODULUS)
Example: Divide ratio
= 128/129
129
128
IN
rul-JUillnJl-- -Jlfl
J
64
64
I
1.
JlJ1illlM
64
65
L
OUT
MC----------------------------~
,.--~'
: IsET :
: IsET
Note: When divide of 129 is selected, positive pulse is applied by one to 65.
The typical set up time is 18 ns from the MC signal input to the timing of change of prescaler divide ratio.
1-54
MB507
D
Fig. 3 - INPUT SIGNAL AMPLITUDE vs. INPUT FREQUENCY
"r
11.
>
E
700
w
0
::J
I-
600
0..
500
«
..J
«
z
400
:::;
:;
Vee
~
5.0V
TA~25°C
Cl
iii 300
I::J
0..
~
:;
::J
~
200
100
Z
~
j'....
10
20
j.....50
100 200
500 1 000 2000
INPUT FREQUENCY. (MHz)
Fig. 4 - TYPICAL APPLICATION EXAMPLE
Vsx (Max. 8 VI
10Kn
12Kn
OUTPUT
M887001A
12Kn
0.047~F
~
10Kn
Damo---·----~~--~
C)ock;O---..--+------J
LE:o-~~--+-------~
MB 507
LOCki=
XI
Vee
Vsx
, 12.8MHz X'tal
,5 V ± 10%
: 8V Max.
C" C2: depends on crystal oscillator
Det.
10Kn
1-55
..
MB507
PACKAGE DIMENSIONS
(Suffix: P)
8-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DlP-08P-M01)
370~:81~
INDEX
.244±.010
(6.20±0.25)
.300(7.62)
TYP
U;=:;=;:::::::;:::::;::::::;::::r::?I~
.039
~J>12
I
I
(0.99~g30)
1·060~J>12
(1.52~g30)
.035~81~
.1 72(4.36) MAX
.118(3.00) MIN
.100(2.54)
.018±.003
TYP
(0.46 ± 0.08)
.. 1988 FUJITSU LIMITED 1Xl8OO6S-2C
1-56
DirT'lElnsions In
inches (mnftmeters)
MB507
D
PACKAGE DIMENSIONS (Continued)
(Suffix: PF)
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT·08P·M01)
.089(2.25) MAX
(SEATED HEIGHT)
INDEX
cf
.050(1.27)
TYP
r---------------,
: Details of "A" part
"A"
I
.008(0.20):
,
I
.020(0.50):
.007(0.18) :
MAX
'
.027(0.68) :
MAX
J
L _______________
J
I
CD 1988 FUJITSU LIMITED
F08002S~3C
Dimensions in
inches (millimeters)
1-57
..
MB507
1-58
00
April 1990
Edition 3.0
FUJITSU
DATA SHEET
MB50B
2.3GHz TWO MODULUS PRESCALER
2.3 GHz TWO MODULUS PRESCALER
The Fujitsu MB508 is a 2.3 GHz two modulus prescaler used in Phase Locked
Loop (PLL) frequency synthesizer and divides the input frequency by a
modulus of 128/130, 256/258 or 512/514. The output level is 1.6V peak to
peak ECL level. Its ultra high frequency operation provides wide application,
such as Direct Broadcasting Satellite System, CATV system, UHF Transceiver,
etc.
~
~
2.3 GHz max. (V IN
•
High Frequency Operation:
f
•
Input Signal Amplitude:
V,N
~
100mV p •p (fiN
~
PLASTIC PACKAGE
DIP·08P·MOl
-4d8m min.)
100 MHz to 1.8 GHz)
• Pulse Swallow Function:
128/130, 256/258, 512/514
• Power Dissipation:
120 mWtyp.
PLASTIC PACKAGE
FPHl8p·MOl
• Wide Operation Temperature: -40DC to +85DC
• Stable Output Amplitude:
VOUT
~
1.6V p. p typo
• Complete PLL synthesizer circuit with the Fujitsu MB87001A, PLL synthe·
sizer system block IC
PIN ASSIGNMENT
• Standard Plastic 8·pin Dual·lh·Line Package or Flat Package
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
IN
Symbol
Value
Unit
Vee
Power Supply Voltage
Vee
-0.5 to +7.0
V
SW1
Input Voltage
V,N
-0.5 to Vee
V
OUT
Output Current
10
10
mA
Operating Temperature
TA
-40 to +85
DC
TSTG
-5"5 to +125
DC
Storage Temperature
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static volt·
ages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.
1-59
..
..
MB508
Fig. 1 .- MB508 BLOCK DIAGRAM
IN
iN ~::;;JD---J
N---r)o--f--o
SW1
SW2
MC
H
H
H
1/128
H
H
L
1/130
H
L
H
1/256
L
H
H
1/256
H
L
L
1/258
L
H
L
1/258
L
L
H
1/512
L
L
L
1/614
Divide Ratio
Note: SW: HaVee. L=Open
MC: H=2.0V to Vee. L=GND to 0.8V
PIN DESCRIPTION
1-60
Pin Number
Symbol
1
IN
Descriptions
Input
Power Supply. +5V
2
Vee
3
SWl
Divide Ratio Control Input (See Divide Ratio Table)
4
OUT
Output
5
GND
Ground
6
MC
Modulus Control Input (See Divide Ratio Table)
7
SW2
Divide Ratio Control Input (See Divide Ratio Table)
8
IN
Complementary Input
OUT
MB50S
D
RECOMMENDED OPERATING CONDITIONS
Values
Parameter
Symbol
Power Supply Voltage
Vee
Output Current
10
Operating Temperature
TA
Load Capacitance
CL
Unit
Min
Typ
Max
4.5
5.0
5.5
V
1.2
mA
-40
ELECTRICAL CHARACTERISTICS
+85
·C
12
pF
(Recommended Operating Conditions unless otherwise noted)
Values
Parameter
Symbol
Condition
Unit
Min
Typ
Max
Power Supply Current
lee
Output Amplitude
Va
I nput Frequency
fiN
With input coupling
capacitor 1000pF
100
2300
MHz
V INA
fiN = 1800MHz to
2300MHz
-4
5.5
dBm
V INB
fiN = 100MHz to
1800MHz
-16
10
dBm
1.0
24
mA
1.6
V p •p
Input Signal Amplitude
High Level Input Voltage for MC
V IHM
Low Level Input Voltage for MC
V ILM
High Level Input Voltage for SW
V IHS
Low Level I nput Voltage for SW
V ILS
High Level Input Current for MC
IIHM
V IH = 2.0V
Low Level Input Current for MC
IILM
V IL = 0.8V
High Level Input Current for SW
IIHS
V IH = Vee
Modulus Set-up Time MC to
Output at 2.3GHz Operation
tSET
Note: 'Design Guarantee
2.0
.
Vee-0.1
V
Vee
0.8
V
Vee+0.1
V
OPEN
V
0.4
-0.2
mA
mA
18
250
p.A
28
ns
1-61
MBS08
1m
Fig. 2 - TEST CIRCUIT
Vee
~
+5.0V±10%
Sampling scope input point
for input waveform
P.G.
S
/
°l
C1
Vee
I
IN
500
Sampling scope prober point
for output waveform
OUT
iN
RL
MC
C2
GND
MC input
Cl: 1000pF
C2: l000pF
C3: O.II'F
C L : 12pF (Including scope and jig capacitance)
CR: 2kSl
TIMING CHART (2 MODULUS)
Example: Divide ratio
~ 128/130
130
128
IN
nn····J1JU1····nn ....... Jill····J1JUU1··JlJ1
~
:
J
64
:
~
~
:
_"..Jf ........... ·1..
64
t--_
64
66
L
OUT
MC----------------------------~
---+,-L
r'--~--
L-,
,~
!sET ,
: tSET :
Note: When divide ratio of 130 is selected, positive pulse is applied by two to 66.
The typical set up time is 18 ns from the MC signal input to the timing of change of prescaler divide ratio.
1-62
MBSOS
Fig. 3 - INPUT SIGNAL AMPLITUDE vs. INPUT FREQUENCY
Ii.
fi
700
E
600
Vee
~ 5.0V
TA~25°C
>
"
"C
.E
c.
500
E
..«
400
§,
in
:;
300
Co
.::
E
200
~
100
"E
';:
r-.....
10
-
20
V
50
100 200
500 1000 2300 5000
Input Frequency (MHz),
Fig. 4 - TYPICAL APPLICATION EXAMPLE
Vsx (Max_ 8 V)
10Kn
12Kn
OUTPUT
M687001A
12Kn
10Kn
Data
LE
o----,-+----J
c:
...""
'"
XI
: 12.8 MHz X'tal
Vee
Vsx
: 5V ± 10%
: 8V Max.
C" C2: depends on crystal oscillator
1-63
..
..
MB508
PACKAGE DIMENSIONS
(Suffix: -P)
8-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-08P-M01)
.370:+::m
INDEX
.244±.010
(6.20±0.25)
~==;:::;:::::::;::;::::;:'J~
.039:+:J>12
II
(0.99:+:g. 30)
.1060:+:J>12
(1.52:+:g. 30)
.035:+::81~
.172(4.36) MAX
.118(3.00) MIN
.100(2.54)
TYP
co 1988 FUJITSU UM\lEO IJ08OO6..2C
1-64
.018±.003
(0.46±0.08)
Dimensions In
inches (millimeters)
MB50S
D
PACKAGE DIMENSIONS (Continued)
(Suffix: ·PF)
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-
::;
Z
:E
-30
12
1.0
1A
1.6
INPUT FREQUENCn. (GHz)
Fig. 4 - WAVEFORM OF STAND BY MODE
«
Power Off
»
«
Power On
»
,,:
PS pin Input
Signal
~
.,
,,:
OUT pin
Output signal
(Prescaler
output)
~
11 111 f\~
\ \
, ,
\ ~ ;' ;' ~ ;' ;' ~ ~ ;' , I
\ 1\1 \Ir 1\1r \Ir 1\1r 1\1r \Ir
,
~
SOns/Diy.
Note:
About 50 ns of set up time is required both power on/off.
1-71
MB509
D
Fig. 5 - TYPICAL APPLICATION EXAMPLE
Microcomputer
PS Signal
LE Data Clock
16
15
14
13
12
11
10
9
MB87076
3
4
LPF
Voo
Prescaler
MB509
OUTPUT
1-72
MB509
PACKAGE DIMENSIONS
a-LEAD PLASTIC DUAL IN-LINE PACKAGE
37o~gl~
(Case No.: DIP-8P-MOI)
INDEX
.244±.OI0
(6.20±O.25)
.300(7.621
TYP
~:::;:::;:::::::r=?I~
.039~gI2
II
(O.99~g30)
I·060~gI2
11.52~g30)
035~:gl~
.172(4.36) MAX
.118(3.00) MIN
.100(2.54)
TYP
© 1988 FUJITSU LIMITED D08006S-2C
.OI8±.003
(O.46±O.08)
Dimensions in
inches tmillimeters)
1-73
..
MB509
PACKAGE DIMENSIONS continued
8-LEAD PLASTIC FLAT PACKAGE
(Case No.: FPT-8P-MOI)
INDEX
cf
....._ - - 1 .020±.008
1.
.050(1.27)
TYP
(0.50±0.20)
.006:!:
:gg~(0.15 :!:gg~)
••p;.
,
.020(0.50):
.007(0.18) :
MAX
I
'
.027(0.68) :
JI
IL _______________
MAX
© 1918 FUJITSU LIMITED FDI002S-3C
1-74
Dimensions in
inches (millimeters)
00
April 1990
Edition 3.0
FUJITSU
DATA SHEET
MB51 0
2.7 GHz TWO MODULUS PRESCALER
2.7 GHz TWO MODULUS PRESCALER
The Fujitsu MB510 is a ultra high speed two modulus prescaler which enables
pulse swallow function. The MB510 is used in Phase Locked Loop (PLL)
frequency synthesizer and divides the input frequency by the modulus of
128/144 or 256/272, respectively.
The MB510 achieves extremely small stray capacitance of internal element,
realized through the use of Fujitsu Advanced Process Technology. As the
results, ultra high speed is achieved with low power supply current of 10 mA
typo
•
High Frequency Operati on:
2.7GHz max.
•
Power Dissipation:
50 mWtyp.
•
Pulse Swallow Function:
•
128/144,256/272
_40 0 C to +85 0 C
Wide Operation Temperature:
VOUT
• Stable Output Amplitude:
=
1.6 Vp . p typo
PLASTIC PACKAGE
FPT·08p·MOl
• Built·in a Termination Resistor
•
Complete PLL synthesizer circuit with the Fujitsu MB87001A, PLL syn·
thesizer IC
•
Package
Standard 8·pin Flat Package
PIN ASSIGNMENT
(Suffix: ·PF)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Symbol
Value
IN
Unit
Vee
Supply Voltage
Vee
-0.5 to +7.0
V
Input Voltage
V IN
-0.5 to Vee
V
10
mA
-55 to +125
°c
Output Current
10
Storage Temperature
TSTG
SW
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
OUT
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum fated voltages to this high impedance
circuit.
1-75
..
MB510
Fig. 1 - MB510 BLOCK DIAGRAM
SW
MC
Divide Ratio
H
H
1/128
H
L
1/144
L
H
1/256
L
L
11272
Note: SW: H = Vee. L = open
MC: H = 2.0 V to Vee. L
= GND to 0.8 V
PIN DESCRIPTION
Pin Number
1
1-76
Symbol
Function
IN
Input
DC Supply Voltage
2
Vee
3
SW
Divide Ratio Control Input (See Divide Ratio Table)
4
OUT
Output
5
GND
Ground
6
MC
Modulus Control Input (See Divide Ratio Table)
7
NC
Non Connection
8
IN
Complementary Input
MB510
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Supply Voltage
Vee
Output Current
10
Ambient Temperature
TA
Load Capacitance
CL
Unit
Min
Typ
Max
4.5
5.0
5.5
V
1.2
mA
-40
+B5
°c
B
pF
ELECTRICAL CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Value
Parameter
Symbol
Unit
Condition
Min
Typ
10.0
Max
15.0
Supply Current
lee
Output Amplitude
Vo
Built·in a termination
resistor.
Load capacitance = BpF
1.0
Input Frequency
fiN
With input coupling
capacitor 1000pF
10
2700
fiN = 10 to 2200 MHz
-10
10
Input Signal Amplitude
V IN
fiN = 2200 to 2700 MHz
-4
10
V p•p
MHz
dBm
High Level Input Voltage for MC
Input
V IHM
Low Level Input Voltage for MC
Input
V ILM
High Level Input Voltage for SW
Input
V IHS'
Low Level Input Voltage for SW
Input
V ILS
High Level Input Current for MC
Input
IIHM
V IH = 2.0V
Low Level Input Current for Me
Input
IILM
V IL = O.BV
Modulus Set·up Time MC to OUT
tSET
Note: 'Design Guarantee
1.6
mA
V
2.0
Vee-0.1
Vee
O.B
V
Vee +O·1
V
OPEN
V
0.4
-0.2
mA
mA
16
26
ns
1-77
..
MB510
Fig. 2 - TEST CIRCUIT
,.--.,0-----...,..-------0
vee
= + 5.0 V
± 10%
Sampling scope input point
for input waveform
Vee
P.G.
C=::n--r--I
Sampling scope prober point
for output waveform
OUT~----...,..---_o
IN
son
MC GND
Me
input
C, : 1000pF
C2: 1000pF
C3 : O.l/t F
C L : 8pF
1-78
(including scope and jig capacitance)
MB510
Fig. 3 -INPUT SIGNAL AMPLIFITUDE vs. INPUT FREQUENCY
..
li>
.s
.I..
I
Vcc=5.0V_
TA - 25"C
800
w
c 600
...::;
:;)
Q.
500
::;;
«
.J
«
z
"...iii
:;)
Q.
400
300
200
!:
::;; 100
:;)
::;;
Z
:E
I
r--....
10
./
20
50
100
200
V
500 1000 2000
INPUT FREQUENCY (MHz)
TWO MODULUS TIMING CHART
Example. Divide Ratio of 1281144
128
144
A
IN
.nn---JlfUl- -:M ----- J1..fl- --JU1.M ---Jlfl
I
j
OUT
M
r -"'-----1
I
64
64
--.--- ---
.....
L
.. . --- --- --80
64
Io-.---":;";"-'~
I
i
I
• to... •
....----..
I
!sET
I
Note: When divide ratio of 144 is selected, positive pulse is applied by 16 to 80.
The typical set up time is 16 ns from the Me signal input to the timing of change of prescaler divide ratio.
1-79
..
..
MB510
Fig. 4 - TYPICAL APPLICATION EXAMPLE
OUTPUT
MB 87001 A
0.047"F
~
Vee
Clock O---'---1~-
Data
o---~-+_---....J
LE
XI
Vee
Vsx
: 12.8 MHz X'tal
: 5V ± 10%
: 8V Max.
C1. C 2 : depends on crystal oscillator
LOCk~_
Det.
10Kn
1-80
M8510
10
PACKAGE DIMENSIONS
(Suffix: -PF)
8-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-08P-M01)
.089(2.25) MAX
(SEATED HEIGHT)
.002(0.05) MIN
d~-t-,-(S..,.TAND OFF)
INDEX
cf
.050(127)
TYP
,
.020(0.50):
.007(0.18) I
MAX
I
~
.. 1988 FUJITSU LIMITED F080Q2S·3C
:
.027(0.68) :
___ ___ __~~~____ J
Dimensions in
inchas (millimeters)
1-81
MB510
D
1-82
cO
January 1990
Edition 2.0
FUJITSU
DATA SHEET
MB511
1GHz HIGH SPEED PRESCALER
HIGH SPEED PRESCALER
The Fujitsu MB511 is a 1GHz high speed prescalerdesigned for use in PLL
(Phase Locked Loop) frequency synthesizer application.
The MB511 consumes low power 23mA at 5V up to 1GHz input frequency
due to adoption of Fujitsu advanced bipolar process.
The MB511 will divide by 1,2, or 8, respectively and very sensitivity (-20dBm
min.). So, the MB511 is well suited for electronically tuned TV and CATV
applications.
•
•
•
Wide operating frequency range:
fin = 50 to 1000MHz (V in =
-20dBm)
Maximum operating frequency
depends upon a divide ratio
111: 250MHz max.
(Buffer through)
1/2: 500MHz max.
lIB: 1000MHz max.
Low supply current: 23m A @5V
•
High input sensitivity: -20dBm min
• Stable output amplitude:
800mVp-p (C L :<:;: 5pF)
•
Wide temperature range:
T A = -40 to +85D C
•
Plastic a·pin dual·in·line package
(Suffix: ·P)
.PLASTIC PACKAGE
FPT·08p·MOl
PIN ASSIGNMENT
Plastic a·pin flat package
(Suffix: ·PF)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Symbol
PLASTIC PACKAGE
DIP·08p·MOl
0
IN
Value
Unit
Power Supply Voltage
Vee
-0.5 to 7.0
V
Input Voltage
V 1N
-0.5 to V ee +O.5
V
Outp,,' Current
Va
10
mA
Storage Temperature
TSTG
-55 to 125
DC
Vee
8
iN
51
2
TOP VIEW
NC
3
6
52
OUT
4
5
GND
This device contains circuitry to protect the
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
inputs against damage due to high static volt·
ages or electric fields. However. it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi·
mum rated voltages to this high impedance
circuit.
1-83
MB511
D
Fig_ 1 - MB511 BLOCK DIAGRAM
IN
OUT
510---\
Divide
Ratio
Controller
520---\
FUNCTION TABLE
H=Vcc
L = OPEN
1-84
Sl
S2
Divide Ratio
Operating Frequency
L
L
Not use
-
L
H
1
250 MHz
H
L
2
500 MHz
H
H
8
1000 MHz
MB511
D
PIN DESCRIPTIONS
Pin No.
Symbol
1/0
Descriptions
1
IN
I
2
Vee
-
Power supply voltage input.
3
NC
-
No connection.
4
OUT
0
Output. Termination resistor is necessary due to emitter follower output.
5
GND
-
Ground.
6
S2
I
Divide ratio control input.
7
Sl
I
Divide ratio control input.
8
iN
I
Complementary input.
Input. The connection with VCO should be an AC connection.
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Unit
Symbol
Min
Typ
Max
5.0
5.5
V
+85
·C
5
pF
Power Supply Voltage
Vee
4.5
Operating Temperature
TA
-40
Load Capacitance
CL
Note
Termination resistor 500.0
1-85
..
MB511
ELECTRICAL CHARACTERISTICS
Value
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Current
lee
15
23
32
mA
Except termination
output current.
Output Amplitude
Va
0.4
0.8
1.2
V p •p
500n termination,
C L = 5pF max.
1/1
fl
50
250
MHz
1/2
f2
50
500
MHz
1/8
f3
50
1000
MHz
Input Frequency
V iH
High Level Input Voltage
+10
-20
V in
Input Signal Amplitude
Vee-0.7
Vee
dBm
Vee+0.5
Min value is measured
with coupling capaci·
tor of 1000pF.
50n
V
51,52
Low Level Input Voltage
High Level I nput Current
OPEN
V iL
51,52
40
liH
V
160
p.A
Vee = 5V
Fig. 2 - TEST CIRCUIT
, - -.....- - . . . - - - - -.....- - 0
P.G·
Vee
L
= 5V±10%
Sampling scope prober point
1000pF
for output waveform
IN
1
50n
500n
MB511
.----iiN
GND
I
1-86
Vee
1000PF
5pF
(including scope and jig capacitance)
MB511
III
TYPICAL CHARACTERISTICS CURVES
Fig. 3 - INPUT SENSITIVITY CURVE
(1/8 DIVIDE RATIO) POWER
SUPPLY VOLTAGE DEPENDENCY
Fig. 4 - INPUT SENSITIVITY CURVE
11/2 DIVIDE RATIO) POWER
SUPPLY VOLTAGE DEPENDENCY
INPUT FREQUENCY fin IMHz)
INPUT FREQUENCY fin 1M Hz)
Fig. 5 - INPUT SENSITIVITY CURVE
(1/1 DIVIDE RATIO) POWER
SUPPL Y VOLTAGE DEPENDENCY
Fig. 6 - POWER SUPPLY CURRENT
vs. POWER SUPPLY VOLTAGE
!zw
28.ot-TA
~ 25lC
IX:
IX:
a>1
.J-
26.0
~2
~
24.0
~
.22.0
~
~
V
¢:Typ 123.Omt
4.5
INPUT FREQUENCY fin IMHz)
~
5.0
5.5
POWER SUPPLY VOLTAGE Vee IV)
1-87
..
MB511
TYPICAL CHARACTERISTICS CURVES (continued)
Fig. 7 - INPUT SENSITIVITY CURVE
(1/8 DIVIDE RATIO)
TEMPERATURE DEPENDENCY
Fig. 8 - INPUT SENSITIVITY CURVE
(1/2 DIVIDE RATIO)
TEMPERATURE DEPENDENCY
INPUT FREQUENCY fin (MHz)
INPUT FREQUENCY fin (MHz)
Fig. 9 - INPUT SENSITIVITY CURVE
(1/1 DIVIDE RATIO)
TEMPERATURE DEPENDENCY
Fig. 10 - POWER SUPPLY CURRENT
VS. TEMPERATURE
!z
...J
w
~E
(!Jig
28.0
II:
II:
iij-
:::l
~ >~ -lclH--HH-
U:;c 26.0
~~
~~
~E -2CII+-+--I---l--
:::;;i
~ ~ -3011+~~ft-~I:±!l:~0f7tt-lr-tlittt--t--t-tl
~.s
~
------ -......
24.0
w
1-88
"
"-
¢= TYP (23mA)
~
1
Q.
22.0
-40
INPUT FREQUENCY fin (MHz)
Vee = 5.0V
0
40
TEMPERATURE TA 1°C)
80
MB511
PACKAGE DIMENSIONS
8-LEAD PLASTIC DUAL IN-LINE PACKAGE
370~g1~
(Case No. : DIP-8P-MOI)
INDEX
.244±.010
16.20±0.25)
.300(7.62)
TYP
~:;:::;::=;:::;::::;:y~
039~J'12
II
10.99~g·30)
1.060~J'1 2
(1.52~g·30)
.035~g1~
1089~g~g)
.17214.36) MAX
.1 18(3.00) MIN
.100(2.54)
TYP
© 1988 FUJITSU LIMITED D08006S-2C
.018±.003
(0.46±0.OB)
Dimensions in
inches (millimeters)
1-89
..
..
MB511
PACKAGE DIMENSIONS (continued)
a-LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT-8P-MOI)
.250~:~g
1
·30a.016
17.8~±0.401
INDEX
cf
.209±.012
15.30±0.301
'9!i=i!i=n=i!i=l~ I
----~
J
.050(1.271
.018±.004
10.45±0.10. ~.OO510.131
TYP
.15~~~
REF
."A••
.
~
...
,
.02010.501:
.00710.181 :
MAX
'
a .004(0.101
I
.02710.681
:
I __ _____________
MAX
L
JI
© 1981 FUJITSU LllmO FOIO02S-3C
1-90
Dimensions in
inches (millimeters)
Section 2
lEI
Phase-Locked Loops (PLLs) - At a Glance
Maximum
Frequency
Supply
Programmable
Counter
Swallow
Counter
Reference
Counter
4.5 V5.5V
Binary
16-1023
Binary
0-127
Binary
8--2048
3.5mA
3.0 V6.0 V
Binary
16-1023
Binary
0-127
Binary
8-16383
8.0mA
typo
4.5 V5.5V
Binary
5-1023
Binary
0-63
5~5535
Binary
8-16383
Page
Device
2~
MB87001A
13 MHz
2.0mA
typo
2-15
MB87006A
10 MHz
2...,27
MB87014A'
40 MHz
Ice
Vee
2~7
MB87076
15MHz
3.0mA
2.7 V5.5 V
Binary
16-2047
Binary
0-127
2-51
MB87086A
95 MHz
8.0mA
4.5 V5.5V
Binary
5-1023
None
Binary
Binary
~5535
2~1
MB87087
10MHz
2.5mA
typo
at3.0V
3.5mA
typo
at 5.0 V
3.0 V6.0V
Binary
5-1023
Binary
0-127
Binary
5-16383
2-73
MB87090
15MHz
4.0mA
typo
at 5.0 V
3.0mA
typo
at3.0V
2.7 V5.5V
Binary
16-1023
Binary
0-127
Binary
8--2048
13 MHz
NOTES: All devices are available in 16-pin plastic DIP and FPT packages.
'Also has on-chip 180 MHz dual modulus (+ 64165) prescaier.
2-1
Pbastt-Locked Loops (PLLs!
2-2
TBlscoromunjcations Data Book
cO
November 1990
Edition 7.0
FUJITSU
DATA SHEET
MB87001A
CMOSPLLFREQUENCYSYNTHESeER
CMOS SERIAL INPUT PHASE-LOCKED-LOOP (PLL)
FREQUENCY SYNTHESIZER
The Fujitsu MB87oo1A, fabrical'3d in CMOS technology, is a serial input PLL frequency
synthesizer.
The MB87oo1 A contains an inverter for oscillator, a programmable reference divider, a divide
factor of programmable reference civider control circuit, a phase detector, a charge pump, a
17-bit shift register, a 17-bit latch, a programmable divider (a binary 7-bit swallow counter, a
binary H)·bit programmable counter), and a control generator for an external dual modulus
prescaler.
PLASTIC PACKAGE
Dlp·16p·M04
When supplemented with a loop filter and VCO, the MB87001 A contains the necessary circuit
to make up PLL frequency synthesizer. Typically, a dual modulus prescaler such as the
MBSOl L can be added, allowing input frequency operation up to 1.1 GHz.
•
11128,1/256, 1/S12, 1/1024,
Single power supply voltage:
Voo = 2.7V to S.SV
112048)
•
•
Wide temperature range:
T. = -40 to 8So(;
•
13MHz typical input capability
@SV (fin input)
•
On-chip inverter for oscillator
•
8 divide factors for programmable
reference divider are selected by 51,
S. and 53 input (lIB, 1116, 1/64,
Programmable 17-bit divider with
input amplifl9r consisting of:
Binary 7-bit swallow counter
Binary 10-bit programmable counter
PLASTIC PACKAGE
FPT·16p·M06
• Two types of phase detector output:
On-chip charge pump ou1put
Output for external charge pump
•
PIN ASSIGNMENT
Easy interface to Fujitsu dual
modulus prescaler
ABSOLUTE MAXIMUM RATINGS (see NOTE)
(Vss = OV)
VDD
Rating
Symbol
Value
Unit
Clock
Power Supply Voltege
Voo
V.. -O.S to Vss +7.0
V
Data
Input Voltage
V,.
V.. -O.S to VDD +o.S
V
LE
Output Voltage
VOIIr
Vss -O.S to Voo +0.5
V
fin
Output Current
10IIr
±10
rnA
M
Open-drain Output
VooP
Vss-O.S to Voo +3.0
V
LD
T.
-40 to ..as
0(;
D.
TSTG
-65 to +150
0(;
PD
300
mW
Operating Temperature
Storage Temperature
Power Dissipation
NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet EXPQsure to absolute
maximum rating conditions for extended periods may affect device reliability.
This doYIco contain. cln:ull}' to protect
InpiAI
aganst
_the
_
._
,
t , , _ thai nornaIpnIOIWI_ be ...... to . 8II1II_ of any IIOItagII higher than maxinllm _
10 thil
Irrpadanca clraJit.
~duetohlghSfatk:""-Of
Copyright ©1990 by FWITSU LIMITED
2-3
MB87001A
Fig. 1 - MB87001 A BLOCK DIAGRAM
voo0--Clock
0--Ll.
2
17-bit Shift Register
I
I
I
I
DataG)
I
I
:==rr11111===1111J]]]]]==:
I
I
I ......IW''---I
I
I
I Crystal
IL _Oscillator
I
_ _ _ _ .J
I
17-bit Latch
I
~0 1·1 '''- ~ ,... I
AMP
-0 vss
r------------------------,I
1
I
I
II
Divide Factor 01
Programmable
Relerence Divider
Control Circuit
I
:==r111111===1II1]]]]]]==:
Programmable Divider
Binary 7-bit
Swallow Counter
II-bit
Binary 10-bit
Programmable Counter
Programmable
Relerence Divider
Ip
2-4
}+-----------------------1
LD
7
Do
8 ~------------~
Charge Pump
Ir
MB87001A
PIN DESCRIPTION
Description
Pin No.
Symbol
VO
1
VDD
-
2
Clock
I
Clock signal input for 17·bit shift register.
Each rising edge ollhe clock shifts one bit 01 the data into the shift register.
3
Data
I
Serial data input for 17·bit shift register.
The data is used for setting the divide factor of programmable divider.
4
LE
I
Load enable input.
When this pin is high level (high active), the dala stored in the 17·bit shift register is transferred to
17-bitlatch.
5
fin
I
Input for programmable divider from VCO or prescaler output.
This input involves bias circuit and amplifier. The connection with external dual modulus prescaler
should be an AC connection.
6
M
0
Control output lor external dual modulus prescaler.
The connection to the prescaier should be DC connection. This output level is synchronized with failing edge of fin input signal (pin #5).
Pulse Swallow Function:
MB501L
M = High: Preset modulus factor 64 or 128
M = Low: Preset modulus factor 65 or 129
7
LD
0
Output of phase detector.
It is high level when fr and fp are equal, and then the loop is locked. Otherwise it outputs negative
pulse signal.
0
Three-slate charge pump output 01 the phase detector.
The mode of Do is changed by the combination 01 programmable reference divider output frequency
fr and programmable divider output frequency fp as listed below:
fr>lp:
Drive mode (Do = High level)
High-impedance mode
fr= fp:
frfp:
Low
Low
High-Impedance
Ir= fp:
Low
High
High-Impedance
frP
and OSCOUT
4>P
m~.
1.0
J.IA
2.0
mA
Power Supply Current-'
100
Max. Operating Frequency of
Programmable Reference Divider
fmaxd
13
20
MHz
Max. Operating Frequency of
Programmable Divider
fmaxp
10
20
MHz
Note: -1: fin = S.OMHz, 12.8MHz Crystal is connected between OSC,. and oseOUT.
Inputs are connected to ground except for fin and OSC,•. Outputs are open.
2-10
0.50
MB87001A
ELECTRICAL CHARACTERISTICS (continued)
(VDO = 5.0V, Vss = OV, TA = -40 to 85°C)
Value
Parameler
Symbol
Condition
Unit
Min
High-/ewllnput Voltage
Low-level Input Voltage
V,H
Low-level Input Current
Max
3.5
Except fin
andOSC,.
V,L
fin
Vfin
OSC,.
V"""
Except fin
andOSC,.
I'H
VIM
=
Voo
1.0
I,L
VIM
= Vss
-1.0
fin
Ifin
VIN
= Vss to Voo
±SO
OSC,.
I"""
V,. = Vss to VDD
±SO
VOH
10H= OJIA
VOL
I
2-13
MB87001A
PACKAGE DIMENSIONS (Continued)
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)
.08912.25) MAX
ISEATED HEIGHT)
1--400+ 010110 15-+ 025 )
,
-008
-020h
·307±.016
117.80±0.40)
.209±.012
15.30,'0.30)
:",: __ IJ
.05011.27)
TYP
~~$1".00510.'3) (M'I
!-D-;taii;~-':-B-:'-p~;t-:
: ¥ . 0 0 6 10.,5) :
,,
.00410.10)
I- .. 35018.89)
REF
MAX
.02710.68)
I
2-14
,,,
,
:
.00810.20) I I
r
I
.00710.18)
I
: \I
~ ______ _~A_X_____ I
.. 1990 FUJITSU LIMITED FI8015S-2C
'~
--
I
I
I
.008(0.20) :
.007(0.18)
I
I
_'
MAX:
.027 (0.68)
I
I
IL ______________
MAX
I
Dimensions In
Inches (millimet8f'l)
00
November 1990
Edition 6.0
FUJITSU
DATA SHEET
MB87006A
CMOSPLLFREQUENCYSYNTHES~ER
CMOS SERIAL INPUT PHASE-LOCKED-LOOP (PLL)
FREQUENCY SYNTHESIZER
The Fujitsu MB87006A. fabricated in CMOS technology. is a serial input phase locked loop
(PLL) frequency synthesizer.
The MB87006A contains an inverter for oscillator. programmable reference divider (binary
14-bit programmable reference counter). 14-bit shift register. 14-bit latch, phase detector,
charge pump, 17-bit shift register, 17-bit latch, programmable divider (binary 7-bit swallow
counter, binary 10-bit programmable counter) and control generator for dual modulus
prescaler.
When supplemented with a loop filter and VCO. the MB8700SA contains the necessary
circuit to make up a PLL frequency synthesizer. Typically. a dual modulus prescaler such as
the MB501 L can be added, allowing input frequency operation up to 1.1 GHz.
•
Wide range power supply voltage:
Vee = 3.0 to 6.0 V
•
Wide temperature range:
TA=-40to85°C
•
17 MHz typical input capability
at 5 V (fin input)
•
Programmable divider with input
ampUfl9r consisting of:
-Binary 7-bit swallow counter
-Binary 1O-bit programmable counter
•
Programmable reference divider with
input amplifier consisting of binary
14-bit programmable reference counter
•
•
PLASTIC PACKAGE
DIP·16P·M04
•
On-chip inwrter for oscillator
Divide factor of programmable divider
and programmable reference divider
are set by serial data input. (The last
data bit is control bit.)
•
Two types of phase detector output:
-On-chip charge pump output
-Output for external charge pump
•
Easy interface with Fujitsu presca/ers
•
16-pin standard dual-in-line package
(Suffix:-P)
16-pin standard fiat package
(Suffix:-PF)
PLASTIC PACKAGE
FPT·16p·M06
PIN ASSIGNMENT
asc,.
ABSOLUTE MAXIMUM RATINGS (see NOTE)
OSCOUT
tv
Voo
Do
Vss
LD
fin
NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
This devlca contains cfrculry to protecI the Inputs against
damage due to high static voltages or Eriectrlc fields. However.
it is adviaed that normal precautions be taken to avoid
application of any voltage higher than rnaxirrum rated
voltages to this high I~ance c'ooK.
Copyright © 1990 by FUJITSU LIMITED
2-15
MB87006A
Fig. 1 - MB87006A BLOCK DIAGRAM
r----------,I
I
14-1>il Shift Register
r;:::====::! r _ - - - - - , I
i.p.,..,..,....,..,...,..,.....,..,..,..,....J
I
1
I
I
OscRlator
I
I
1
~kiiliffimJJ1
r-------,
I
Crystal
I
esc..
14-bil Latch
I
I
rI
I
I
II
I
I
Programmable
Reference Divider
I
Binary 14-bil
Reference Counter
I
L. _ _ _ _ _ _ _ _ _ _ .J
_.J
Ir--~~~~r_--~~~--~
r-------,
I
Register I
Control
I
I
I
~~~~
II~----~~~~~~---------I
I
I
.JI
I
1._________ ____________
2-16
MB87006A
PIN DESCRIPTION
Input pin for crystal oscillator.
Input to the inverting amplifier that forms part of the oscillator.
This pin receives the oscillator signal as AC coupled when an external oscillator is used. For large
amplitude signals (standard CMOS levels) DC coupling may also be used.
OSCI.
2
OSCOUT
0
Output pin for crystal oscillator.
Output of the inverting amplifier. This pin should be open when an external oscillator is used.
3
fv
0
Monitor output of the phase detector.
This pin is tied to the programmable divider output.
4
Voo
5
Do
Power supply voltage input.
0
Three-state charge pump output of phase detector.
The mode of Do is changed by the combination of programmable reference divider output frequency
fr, and programmable divider output frequency fv as listed below:
fr>fv:
Drive mode (Do = High level)
fr= fv:
High impedance
fr fv:
fr= fv:
Ir A)
fvco
N
Output frequency of external voltage controlled oscillator (VCO)
Preset divide factor of binary 10-bit programmable counter (5 to 1023)
Preset modulus factor of external dual modulus prescaler
(e.g. 64 in 64165 mode, 128 in 128/129 mode of an MBS01 L prescaler)
Preset divide factor of binary 7-bit programmable counter (0 to 127, A <: N)
M
A
fose
: Output frequency of external oscillator
R
: Preset divide factor of binary 14-bit programmable reference counter (5 to 16383)
DIVIDE FACTOR OF PROGRAMMABLE REFERENCE DIVIDER
Serial data consists of 14-bit data, which is used for selling divide factor of programmable reference counter, and 1-bit control data. In this case,
control bit is set high level.
The data format is shown below.
Control
Register
LSB
MSB
Data
14-bit
Shift Register
Clock
14-bit Latch
Programmable
Reference
Divider
Binary 14-bit Reference Counter
I
BINARY 14-BIT REFERENCE COUNTER DATA INPUT
CD
Divide
Factor
0
1
5
1
0
6
1
1
1
7
1
1
1
16383
@
@
(jj)
@
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
@
® ® 0
@
® 0
® ®
Note: Divide factor less than 5 is prohibited.
Divide factor: 5 to 16383
2-19
MB87006A
DIVIDE FACTOR OF PROGRAMMABLE DIVIDER
Serial data consists of l7-bit data, which is used for setting divide factor of programmable divider, and l-bit control data. In this case, control bit is
set low level. The data(Dto O. 101
M I
:D~taii;- ~f-·7e:·-;';t-:
:~00610"51:I
"A"
,
~
I> 1990 FUJITSU LIMITED Fl6015S·2C
2-26
I
I
I
,
I
I
I
:
.008 (0.20) :
.00BIO.2011
.OO710.1BI :
I
~
I
MAX
:
I
I
I
.027(0.68):
____ __ ~_Al'_____
1"
.007(0.18) :
MAX
I
:
:L
I
.027(0.68) :
___
~
MAX!
___ __
:- __ :-_
Dimensions in
Inches (millimeters)
cP
FUJITSU
June 1991
DATA SHEET
MB87014A
CMOS PLL Frequency SynthesizerlPrescaler
The Fuj~su MB87014A, fabricated in advanced CMOS technology, is a serial input
phase locked loop (Pll) frequency synthesizer with an on-chip 180 MHz dual
modulus prescaler.
The MB87014A contains dual modulus prescaler, inverter for oscillator, programmable reference divider, control circu~, phase detectors, charge pump, programmable divider (binary 6-bit swallow counter and binary 1 O-b~ programmable
counter).
The MB87014A contains the necessary circuit to make up a Pll frequency
synthesizer that operates at a speed up to 180 MHz.
•
Single power supply voltage:
Voo = 4.5 V to 5.5 V
•
Wide temperature range:
TA = -30 to 60 DC
•
•
180 MHz input capability at 5 V (fin input)
On-chip inverter for oscillator
•
Programmable divider with input amplffier consisting of:
Binary 6-bit swallow counter
Binary 10-bit programmable counter
•
Programmable reference divider with input amplifier consisting of binary 16-b~
programmable reference counter
•
Divide factor of programmable divider and programmable reference divider are
set by serial data input. (The last data bit IS a control bit.)
•
Three types of phase detector outputs:
- On-chlp charge pump output for active lPF
- On-chip charge pump output for passive lPF
- Output for external charge pump
•
16-pin standard dual-in-Iine package (Suffix: -P)
16-pin standard flat package (Suffix: -PF)
•
Pulse swallow function
fvco= [(N x M) + Alx (Fose +R) IN >A)
fvco
:Output frequency of external voltage controlled oseillator (VCO)
N
:Preset divide lactorol binary 1O-bit programmable counter (5 to 1023)
M
:Preset modulus factor of internal dual modulus presealer (64/65)
A
:Preset divide factor of binary 6-bit swallow counter (0 to 63)
fose
:Output frequency of the external oscillator
R
Preset divide factor 01 binary 16-bit programmable reference counter
(5 to 65535)
Plastic Package
DIP-16P-M04
Plastic Package
FPT·16P-M02
Pin Assignment
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Power Supply Voltage
Voo
cj>R
cj>V
Iv
Voo
Ratings
Vss -{l.3 to Vss +7.0
NC
ff
Unit
DOP
DOA
V
Vss
LE
Input Voltage
V IN
Output Voltage
VOUT
Vss -{l.3 to Voo +0.3
V
Output Current
lOUT
±10
mA
Operating Ambient
Temperature
TA
-30 to +80
DC
Storage Temperature
TSTG
--40 to +125
DC
Power Dissipation
Po
300
mW
Vss -{l.3 to Voo +0.5
Note: Permanent device damage may occur il absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operation sections of this data sheet. Exposure to absolute maximum rating conditions lor extended periods may afl9ct devioe reliability.
©
OSCIN
OSCOUT
LD
Data
fiN
Clock
This device contains circuitry to protect the InpUII against
damage due to high ataIic voltages or eleclrlc fields. HOIW8V8r••
Is ad_1haI normal p!8C8UIionB be _
to avcid application
of My voltage higher than maximum rated voIageI to this high
""""anooclrcuh.
1991 by FUJITSU LIMITED and Fujhsu M_ronlcs. Inc.
2-27
MB87014A
MB87014A BLOCK DIAGRAM
I
CRYSTAL
OSCILLATOR
I
I
PROGRAMMABLE REFERENCE DIVIDER •
I
BINARY lEI-BIT
PROGRAMMABLE REFERENCE
COUNTER (R)
2-28
BINARY 6-BIT
(A)
BINARY 10-BIT
SWAllOW
COUNTER
PROGRAMMABLE
COUNTER
(N)
I
MB87014A
PIN DESCRIPTION
osc,.
Input pin for crystal oscillator.
Input to the inverting amplifier that forms part 01 the oscillator. This pin receives the oscillator signal as
AC
when an external oscillator is used, but lor large amplitude signals (standard CMOS levalso be used.
2
OSCotrr
0
Output pin for crystal oscillator.
Output 01 the inverting amplifier. This pin should be left open when an external oscillator is used.
3
Iv
0
Monitor pin for the phase detector input.
This pin is tied to the programmable divider output.
Dop
0
Output pin lor low pass lilter (Passive type).
The mode 01 DOP is changed by the combination 01 programmable reference divider output lrequency
f., and programmable divider output lrequency Iv as listed below:
I. > Iv:
Drive mode (Dop = High level)
High-impedance
1.= Iv:
Iv:
Sink mode (Dop = Low level)
4
5
input
,,<
6
Vss
7
LD
8
,.,
9
Clock
Clock signal input lor shift registers.
Each rising edge 01 the clock makes one bit 01 the data shift into the shift registers.
10
Data
Serial data input lor shift registers.
The last bit of the data is the conlrOl bit The control data determines which latch is ectivated.
11
LE
12
Do..
13
14
NC
15
16
,R
'V
Ground.
0
Output 01 phase detector.
It is high level when I. and fv are coherent, and when the loop is locked. Otherwise it outputs negative
I
Frequency input to an internal prescaler from VCO.
The connection with VCO should be AC connection.
Load enable input.
When this pin is high, the data from shift register is latched into programmable relerence divider or
programmable divider depending upon a control bit setting.
0
Output pin lor low pass filter (Active type).
The mode 01 DCA is changed by the combination 01 programmable relerence divider output frequency
I., and programmable divider output lrequency Iv as listed below:
Sink mode (DCA = Low level)
I. > Iv:
High-impedance
I.=fv:
I. Iv:
I. = Iv:
High level
High level
I. fp:
fr = fp:
Do = H level
Do = High-impedance level
fr fp:
f,=fp :
f, ct.:
2-40
,R
Low
Low
High
'V
Low
High-impedance
High-impedance
MB87076
FUNCTIONAL DESCRIPTION
SERIAL DATA INPUT FOR PROGRAMMABLE DIVIDER
Binary serial data is input to Data pin. Each rising edge of clock shifts one bit of the data into the shift registers and control register. Input data
consists of IS-bit data and I-bit of control bit data. In this case, control bit is set at low level. S, to Sr is used for setting the divide ratio of 7-bit
swallow counter and S. to S" is used for setting the divide ratio of 11 bit programmable counter.
The data format is shown below.
Control bit
r--
7-bit swallow counter
-----1-""1··-------
-I
II-bit programmable counter
7-bit Swallow Counter Data Input
Divide
factor A
S,
S.
S.
S3
50
S,
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
127
1
1
1
1
1
1
1
.
Note:
S7
.
.
.
Divide factor: 0 to 127
11-blt Programmable Divider Data Input
Divide
factor N
S"
S"
S,.
SIS
S"
S'3
S,.
S"
SIC
S.
S.
5
0
0
0
0
0
0
0
0
1
0
1
6
0
0
0
0
0
0
0
1
1
0
.
.
0
.
1
1
1
1
1
1
1
1
.
2047
Nole:
1
1
1
.
.
.
.
Divide factor less than 5 is prohibited.
Divide factor: 5 to 2047
2-41
MB87076
FUNCTIONAL DESCRIPTION (Continued)
SERIAL DATA INPUT FOR PROGRAMMABLE REFERENCE DIVIDER
Binary serial data is input to Data pin. Each rising edge of clock shifts one bit of the data into the shift registers and control register. Input data
consists of 14-bit data and I-bit of control bit data. In this case, control bit is set at high level.
The data format is shown below.
Control bit
14-bit Programmable Reference Counter
14-bit Programmable Divider Data Input
S"
S'3
S12
S"
S,.
S,
S.
S,
S.
S5
S,
S3
S2
S,
8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
9
0
0
.
0
.
0
0
0
.
0
.
0
0
0
1
.
0
0
.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Divide factor R
16383
Note:
Divide factor less than 8 is prohibited.
Divide factor: 8 to 16383
Fig. 2 - SERIAL DATA INPUT TIMING
- - - -
Data
~ Control bit
(S2)
(Control bit)
----~
Clock
LE
t,
• Input data of programmable reference divider.
2-42
(S,)
Is
1
MB87076
Fig. 3 - PHASE DETECTOR WAVEFORM
fp
Do
____n~lLJl_n~
--.J
n
u
1:0:
HIGH IMPEDANCE
n
.pR
.p
(N-CHAN~
OPEN DRAIN
OUTPUT)
U
UI
HIGH IMPEDANCE
f,
LD
Nole:
LD is set at High level when f, .. f,. (Unclock condition)
LD is set at Low level when f, = f,. (Lock condition)
2-43
MB87076
POWER DOWN OPERATION DESCRIPTION
The MB87076 has power down function which selects operation mode or power down mode depending on PS input signal level.
When PS is set at low level, power down mode is selected. During power down mode, internal dividers stop operation. Thus, very low power
supply consumption is achieved and LC pin is set at Low level.
Then the PS level goes High with the frequency of VCO as almost the same value as that under the condition of phase lock, the following sequence is taken.
1) Programmable divider starts operation
fp is output with some delay
3) Programmable reference divider starts operation when it receives fp.
4) f, is output
5) LC is forced to set at High level (Normal operation mode is selected)
2)
When the f, outputs immediately after the fp outputs, and goes into the phase detector,the phase lock condition is obtained just after the first clock.
When PS is set at Low level again. internal dividers stop operation. Then internal condition is reset.
Fig. 4 - POWER DOWN MODE
PS~
_JL ___SL___~
J----
LC
--
I
POWERDOWNMODE--~·~I~·-------- OPERATION MODE
I
2-44
I
---------l..-tl••I
POWER DOWN MODE
MB87076
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Unit
Symbol
Min
Typ
Max
5.0
5.5
V
Power Supply Voltage
V""
2.7
Input Voltage
V'N
V..
Voo
V
Output Temperature
T.
--40
+85
'C
ELECTRICAL CHARACTERISTICS
(V••
=OV. Voo =3.0V. T. =--40 to 8S·C)
Value
Parameter
Symbol
Unit
Condition
Min
High-level Input Voltage
Typ
Max
2.1
V'H
Except fin
andOSC'N
Low-level Input Voltage
V
V'L
fin
0.9
V".
0.5
Vp•p
Amplitude in AC coupling,
sine wave
Input Sensitivity
OSC,.
High-level Input Current
V ••
Sine
0.5
I'H
V'N = V DD
t.O
I'L
V,. = V..
-1.0
fin
IIIN
V'N = V.. to VDD
±30
OSC'N
IXIN
V'N = V .. to Voo
±30
VOH
10H= OIIA
VOL
10L= 01lA
Except fin
andOSC'N
Low-level Input Current
IIA
IIA
Input Current
High-level Output Voltage
2.95
Exceplq,P
and OSCOUT
Low-level Output Voltage
V
0.05
2-45
MB87076
ELECTRICAL CHARACTERISTICS (Continued)
(V..
EI
=OV. v•• =3.0V. T. =-40 to as"c)
Value
Parameter
Symbol
Unit
Condition
Min
Low-level Output Voltage
cpP
High-level Output Voltage
VO!.v
10L=0.8mA
VOHX
IOH = 0jJA
Typ
Max
0.80
2.50
OSCOUT
Low-level Output Voltage
V
VOU(
High-level Output Current
V
IOH
0.50
IO!. = OflA
VOH = 2.0V
-0.5
ExceptcpP
andOSCoUT
rnA
Low-level Output Current
loe
VOL = O.BV
N-channelopen drain Cut 011 Current
10FF
Vo= Voo +3.0V
1.0
JJA
loOOP
Operation mode
2.50
rnA
loDl'S
Power down mode
0.5
Power Supply Current .,
Max. Operation Frequency of Programmable
Reference Divider
fmalld
BO
10
JJA
20
MHz
Max. Operation Frequency of Programmable
Divider
Note: *1
2-46
fm.xp
10
20
fin = B.OMHz, 11.5MHz Crystal is conneceted between OSC IN and OSCOUT. PS is set at high level, all other inputs are set at low
level. Outputs are open.
MB87076
ELECTRICAL CHARACTERISTICS (Continued)
(V..
=OV, V =5.0V, T. =-40 to 85 C)
D
DD
Value
Symbol
Parameter
Unit
Condition
Min
High·levellnput Voltage
Typ
Max
3.5
V,H
Except lin
and OSC 'N
Low·level Input Voltage
V
1.5
V"
lin
OSC'N
High·levellnput Current
0.8
Vipp
Input Sensitivity
Amplitude in AC coupling,
Vp_p
sine wave
Sine
1.0
Van
I'H
V1N = Voo
1.0
I,c
V,N = Vss
-1.0
"IN
V,N = V.. to Voo
±50
Except fin
andOSC 'N
Low-level Input Current
lin
IIA
IIA
Input Current
OSC 'N
High-level Output Voltage
IXIN
V,N = Vss to VDD
V""
10H = 01lA
VOL
10L= 01lA
±50
4.95
ExceptcpP
and OSC OUT
Low·level Output Voltage
V
0.05
2-47
MB87076
ELECTRICAL CHARACTERISTICS (Continued)
(V..
=OV, V =5.0V, T. =-40 to a5°C)
DD
Value
Parameter
Symbol
Unit
Condition
Min
Low-level Output Voltage
opP
Typ
Max
VOLV
IOL= lrnA
VOM•
'0• = 01lA
VOU(
101.= 01lA
'0•
VOH = 4.0V
-1.0
Low-level Output Current
101.
VOl = O.SV
1.0
N-channel open drain Cut 011 Current
10FF
Vo = VDD +3.0V
1.0
IlA
looop
Operation mode
3.0
mA
loops
Power down mode
High-level Output Voltage
0.50
4.50
V
OSCour
Low-level Output Voltage
High-level Output Current
ExceptopP
andOSCour
V
0.50
mA
Power Supply Current .,
Max. Operation Frequency of Programmable
Reference Divider
fmaxd
100
15
IlA
25
MHz
Max. Operation Frequency of Programmable
Divider
Note: .1
2-48
fmup
10
25
lin = S.OMHz, 11.5MHz Crystal is conneceted between OSC,. and OSCOUT. PS is set at high level, all other inputs are set at low
level. Outputs are open.
MB87076
PACKAGE DIMENSIONS
lIi·LEAD PLASTIC DUAL IN·L1NE PACKAGE
(CASE No.: DIP·16P·M04)
\
q
,-----"..,..;_"'_""_-_""-.==0"
15' MAX
300(7.62)
TYP
i
- -D"''''''.118(3.00) MIN
.05~)
MAX
., 1988 FWITSU LIMITED DI6033S-2C
TYP
.018±.003
(0.46±0.08)
.020(0.51) MIN
Dimensions in
inches (millimeters)
2-49
MB87076
PACKAGE DIMENSIONS (Continued)
Hi·LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT·16P·M02)
089(2 25) MAX
(SEATED HEIGHT)
-''"h
1-400+ 010(10 15+ 025 )
i
-000
!
.268 ~ :g6~(6.80 ~g;g)
.209±.012
(5.30±0.30)
1Im==iii=;:;=;:;=;:;=;:;:=;:;:==nY___.. 1_
TYP
U J.
307±.016
(7 80±0 40)
INDEX
if '
.050(1.27)
.002(0.05) MIN
l(STAND OFF)
JLo~$I .
(0.45±0.10)
.
j
005(0.13
- ===t
i
~
'M:I
).
r--- -I
"A"
.020±.008
(0.50±0.20)
006+. 002 (0 15+ 0 .05 )
.
-.001' -0.02
-------~I
Details of "A" part
:
.008(0.20) :
,
,
I
I
I
.020(0.50) :
.007(0.18)
MAX
I
.027(0.68) I
~ ________ lI!IiI!<____
to 1988 FUJITSU LIMITED F1600SS-4C
2·50
J
Oimenslons In
Inches (millimeters)
OJ
FUJITSU
June 1991
DATA SHEET
MB87086A
CMOS PLL Frequency SynthesizerlPrescaler
The Fujitsu MB87086A, fabricated in advanced CMOS technology, is a serial input
phase locked loop (PLL) frequency synthesizer. The MB87086A contains an
inverterforoscillator, programmable reference divider (binary 16-bit programmable
reference counter), programmable divider (binary 10-bit programmable counter),
phase detector, charge pump.
The MB87086A contains the necessary circuit to make up a PLL frequency
synthesizer that operates at a speed up to 95 MHz.
•
Single power supply vo~age:
•
Wide temperature range:
•
On-chip inverter for oscillator
•
Divide factor of programmable divider and programmable reference divider are
set by serial data input. (The last data bit is a control bit).
•
Three types of phase detector outputs:
-On-chip charge pump output for active LPF
-On-chip charge pump output for passive LPF
-Output for external charge pump
•
16-pin standard dual-in-line package (Suffix: -P)
16-pin standard flat package (Suffix: -PF)
•
95 MHz input capability at 5 V (fin input)
•
fin, Clock, Data input circuits involve schmitt circuit
•
The divide factor is selected according to the following equation:
fvco = N xfosc + R
fvco
:Output frequency of external vo~age controlled oscillator (VCO)
N
:Preset divide factor of programmable divider (5 to 1023)
M
:Preset modulus factor of internal dual modulus prescaler (64165)
!9sc
:Output frequency of the external oscillator
R
Preset divide factor of binary programmable reference divider
(5 to 65535)
Voo = 4.5 V to 5.5 V
Plastic Package
DIP-16P-M04
Plastic Package
FPT-16P-M06
ABSOLUTE MAXIMUM RATINGS
Pin Assignment
OSCIN
~R
OSCouT
~V
Iv
Voo
Parameter
Power Supply Vo~age
Symbol
Voo
Input Voltage
V IN
Output Voltage
VOUT
Output Current
lOUT
Operating Ambient
Temperature
Ratings
Vss -0.3 to Vss +7.0
Vss -0.3 to Voo +0.3
Vss -0.3 to Voo +0.3
Unit
V
V
V
±10
mA
TA
-30 to +80
·C
Storage Temperature
TSTG
--40 to +125
·C
Power Dissipation
Po
300
mW
Note: Permanent device damage may occur if absolute maximum ratings
are exceeded. Functional operation should be restricted to the conditions as detailed in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
©
NC
I,
DoP
DOA
Vss
LE
LD
Data
IIA
Clock
This device contains circuitry to protect the Inputs against
damage due 10 high atatk: voJlages or electric fields. However. II
Is advtsed that normal precautions be taken to avoid application
of any voltage higher than maximum rated YOhages to this h'Oh
ifl1)8dance circuit.
1991 by FUJITSU LIMITED and FuJ1>u MicroelectroniCS. Inc.
2-51
MB87086A
MB87086A BLOCK DIAGRAM
r----'
I
I
OSC,.
X'taI OSC.
I >---+-1-1
I
I
;0-'1-'1""'"
Programmable Reference Divider
16-bit Programmable Reference Counter
I ~--------------------~I
L ____________________ J
r----------
I
---,
Programmable Reference Divider
I
IO-bit Programmable Counter
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ JI
IL _~--------------------~I
L - - - - - - - { 3 fv
2-52
MB87086A
PIN DESCRIPTION
Pin No.
Symbol
va
1
OSC,.
I
Input pin far crystal oscillator.
Input to the inverting amplifier thatlorms pari of the osciUator. This pin l'8CIIives the osciRator signal as
AC coupled when an extemal oscillator is used, bulfor large amplitude signals (standard CMOS levels) DC coupling may also be used.
2
OSCOUT
0
Output pin lor crystal oscillator.
Output of the inverting amplifier. This pin should be connected to open when an external oscinalDr is
used.
3
fv
0
Monitor pin for the phase de\9clor input.
This pin is tied 10 the programmable divider output.
4
VDD
5
Do.
-
Deacrlpdon
Power supply voltage input.
0
Output pin lor low pass fiker (Passive type).
The mode of DOP is changed by the combination of programmable reference divider output frequency
fro and programmable divider output frequency fv as listed below:
fr > Iv:
Drive mode (DOP - High level)
High-impedance
fr= Iv:
Sink mode (Do. = Low level)
fr < Iv:
6
V..
-
Ground.
7
LD
0
Output of phase detector.
II is high level when fr and fvare coherent, and when the loop is locked. Otherwise it outputs low pulse
signal.
8
fin
I
Frequency input to programmable divider from
(This input has an internal feed back resistor.)
9
Clock
I
Clock signal input lor shill registers.
Each rising edge of the clock makes one bit of the data shift into the shill registers.
10
Data
I
Serial data input lor shill registers.
The last bit of the data is the control bit. The control data determines which latch is activated.
11
LE
I
Load enable input.
When this pin is high level, the data stored in the shill registers is transferred 10 16-bitlatch, or 10-bit
latch depending on the control bit selling.
veo or prescaler output.
12
DCA
0
Output pin far low pass filter (Active type).
The mode of DCA is changed by the combination of programmable reference divider output frequency
fr, and programmable divider output frequency fv as listed below:
Drive mode (DoA - Low level)
fr>fv:
High-impedance
fr=fv:
frd.:
Sink mode (DoA = High level)
13
fr
0
Monitor pin lor the phase detector input.
This pin is tied to the programmable reference divider output.
14
NC
-
No connection.
15
16
+V
0
0
Output pins for low pass filter (diHerentiai filler type).
Outputs lor extemal charge pump are changed by the combination of programmable reference divider output frequency fr, and programmable divider outputlrequency fv as listed below.
+R
+V
fr>fv:
fr= fv:
fr < Iv:
High level
High level
Low level
+R
Low level
High level
High level
2-53
MB87086A
FUNCTIONAL DESCRIPTIONS
DIVIDE FACTOR OF PROGRAMMABLE REFERENCE DIVIDER
Binary code serial data is input to data pin. Each rising edge of clock makes one b~ of the data shift into the shift registers and control register. Input data consists of IS-bit or 10-bit data and l-bit of control bit data. The 16-b~ data is used for setting the divide factor
of pnlgrammable reference divider. The lO-bit data is used for setting the divide factor of programmable divider.
The last bit of \he data stored in control register is a control b~. Control data determines which latch is activated. When this bit is at
high level, 16-bit latch is selected; when this is at low level, 10-bit latch is selected.
The data format is shown below.
Last Input Bit
Programmable
Reference Divider
Programmable
Divider
1+------- Divide Factor of Programmble Reference
Divider Setting Bits
When LE is high level and control bit is high level, the data stored in IS-bit shiflregister is transferred to IS-bit latch. When LE is high level and
control bit is at low level, the data stored in 10-bit shift register is transferred to 10-bitlatch.
~""""'""'I"'..r..'T""""'r-"""'""'I"'..r..'T""""'r-"""'""'I"'..r..'T""~r-...,.....,...r..""''''''6_bit
Shift
.........I_...L._..I..._I-....I_...L._..I..._I-....I_...L._..I..._I---'-.....-..L..-.lRegister
Data
Clock
LE
2-54
MB87086A
BINARY 1D-BIT PROGRAMMABLE DIVIDER DATA INPUT
(10)
(9)
(8)
(7)
(6)
0
0
0
0
0
0
0
0
1
1
1
1
1
(1)
Divide
Factor
0
1
5
1
0
6
1
1
1023
(5)
(4)
(3)
(2)
0
0
0
1
0
0
0
1
1
1
1
Nole: Divide factor less than 5 is prohibited.
Divide factor N: 5to 1023
BINARY 16-BIT PROGRAMMABLE REFERENCE DIVIDER DATA INPUT
@ @) @ @ @ @ @)
® ® CD ® 0 0 ® ® 0
Divide
Factor
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
5
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
65535
Note: Divide factor less than 5 is prohibited.
Divide factor R: 5 to 65535
SERIAL DATA INPUT TIMING
Data
Clock
-
LE
,
Notes:
12
........
' .....
' --"';i---lnJ-'
b~
'f
~:
,,
15---, ,
0
Data input for programmable reference divider.
()
Data input for programmable divider.
Data
Serial data inpUf is used for selling divide factor of programmable reference divider or programmable divider.
Data is input from MSB and last bit data is control bit.
Control bil is set at high level when divide factor of programmable reference divider is set. Control bit is set at low level when divide
factor of programmable divider is set.
Clock Clock input for 1O-bit shift register, 1S-bit shift register and control register. Data is input into internal shift registers by rising edge of
the clock.
LE Load enable input:
When LE is high level, the data stored in shift registers is transferred to 16-bitlatch, or 10-bitlatch depending on the control bit
selling.
2-55
MB87086A
PHASE DETECTOR OUTPUT WAVEFORM
fr
~
Iv
~
1...--,
,,
Dop
--1,
,
DOA
---,
,
.R
l
.V
LD
2-56
Ln
,
,
,, ,
r-----u
'
"
,
LJ
,
n
,
nJ
U
,,,
,
l
¢I HIGH IMPEDANCE
nJ U
¢I HIGH IMPEDANCE
MB87086A
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Unit
Symbol
Min
Typ
Max
5.0
5.5
V
Power Supply Voltage
Voo
4.5
Input Voltage
V'N
Vss
Voo
V
Operating Temperature
T.
-30
+60
"C
ELECTRICAL CHARACTERISTICS
(V••
= OV, Voo = 5V, T. = -30 to 60"C)
Value
Parameter
Symbol
Unit
Condition
Min
High-level Input Voltage
Low-level Input Voltage
Except fin
andOSCIN
lin
High-level Input Current
Low-level Input Current
Except lin
andOSC'N
Max
3.5
V'H
V
VIL
1.5
V!pp
Input Sensitivity
OSC'N
Typ
Vsin
1.0
Amplitude in AC coupling,
Sine wave
Vp.p
1.0
I'H
VIH
= Voo
1.0
I'L
Vll
= Vss
-1.0
IIA
lin
lfin
V'N = Vss to Voo
±50
OSC'N
lose
V'N = Vss to Voo
±50
VOH
10H = 01lA
VOL
10L= 01lA
10H
VOH= 4.6V
-1.0
Low-level Output Current
10L
VOL = O.4V
1.0
Power Dissipation"
100
IIA
Input Current
High-level Output Voltage
Except
OSCOUT
Low-level Output Voltage
High-level Output Current
Maximum Operating>'
Frequency
Notes:
Except
OSCOUT
4.95
V
0.05
rnA
8.0
mA
REF Section
Imaxd
40
60
MHz
PD Section
Imaxp
95
130
MHz
*1: fin 100MHz, 22MHz cystal is connected between OSC'N and OSCOUT pins.
Inputs are grounded except lin and OSC ... Outputs are open.
*2 REF Section: Maximum operating frequency 01 programmable relerence divider.
PD Section: Maximum operating lrequency or programmable divider.
2-57
MB87086A
PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M04)
.300(7.62)
TYP
.050(1.27)
MAX
01998 FUJITSU LIMITED 016033S-2C
2-58
TYP
~~1::::::
::
.f-
.018±.003
(0.46±0.08)
.020(0.51) MIN
Dimensions in
inches (millimeters)
MB87086A
PACKAGE DIMENSIONS (Continued)
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)
.089(2.25) MAX
'--4001010(10151025)
~"'~~
:
3071 016
1(780;
040)
INDEX
cf
"8"
.209.+ .012
(5.3010.30)
:---; __ -_1_
J
~~$I.005(0.13) iMll
050(1.27)
TYP
(0.45 ± O. 10)
26S+gbg (680
':gig)
I
I
---t (0 50 +0.20)
--I- .020 +.008
-l006
~ggf
(0 15
~ gg~)
"A"
.-- .350(8.89). REF
DImension< In
01990 FUJITSU LIMITED F16015S-2C
inches (mHlinatefs)
2-59
MB87086A
2-60
OJ
January 1991
Edition 3.0
FUJITSU
DATA SHEET
MB87087
CMOSPLLFREQUENCYSYNTHES~ER
CMOS SERIAL INPUT PHASE-LOCKED-LOOP (PLL)
FREQUENCY SYNTHESIZER
The Fujitsu MB87087, fabricated in CMOS technology, is a serial input phase locked loop
(PLL) frequency synthesizer.
The MB87087 contains an inverter for oscillator, programmable reference divider (binary
14·bit programmable reference counter), 14-bit shift register, 14-bit latch, phase detector,
charge pump, 17-bit shift register, 17-bitlatch, programmable divider (binary 7-bit swallow
counter, binary 10-bit programmable counter) and control generator for dual modulus
prescaler.
When supplemented with a loop filter and vee, the MB87087 contains the necessary circuit
to make up a PLL frequency synthesizer. Typically, a dual modulus prescaler such as the
MB501 L can be added, allowing input frequency operation up to 1.1 GHz.
•
Wide range power supply voltage:
Vce = 3.0 to 6.0 V
•
Wide tamperature range:
TA=-40to85'C
•
•
17 MHz typical input capability
at 5 V (fin input)
Programmable divider with input
amplifier consisting of:
-Binary 7-b~ swallow counter
-Binary 10-bit programmable counter
•
Programmable reference divider with
input amplifier consisting of binary
14-b~ programmable reference counter
•
•
PLASTIC PACKAGE
DIP-16P-M04
On-ilhip inverter for oscillator
Divide factor of programmable civider
and programmable reference divider
are set by serial data input (The last
data bit is control bit.)
•
Two types of phase detector output:
-QI-ilhip charge pump output
-Output for external charge pump
•
•
Easy interface with Fujitsu prescalers
PLASTIC PACKAGE
FPT-16P-M06
16-pin standard dual-in-line package
(MB87087P)
IS-pin standard flat package
(MB87087PF)
PIN ASSIGNMENT
esC..
ABSOLUTE MAXIMUM RATINGS (see NOTE)
OSCOUT
Iv
voo
Do
v••
LD
fin
NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
This device contains circuitry to protect the inputs againtt
damage dueto high staticYOlages orekK:tric ftekis. However,
I: is advised thai nDlmal precautions be taken to avoid
appIk:alion of any voCtage t'tlgher than rnaxifTlJm ratad
votIages 10 this high irJ1)8dance circuit.
Copyrighl ©1991 by FUJITSU LIMITED
2-61
MB87087
MB87087 BLOCK DIAGRAM
r----------i
I
14-bit Shift Register
I
r.:====:::! .-----.... II
'TT~I"T'TTT"I"'T'T',..,....J
OSCI'
OSCour
I
I
I
IL _ _ _ _ _ _ .JI
I
II
Programmable
Reference Divider
Binary 14-bit
Reference Counter
I
L _ _ _ _ _ _ _ _ _ _ ..J
I~~~~r_~~~--~~~
r------,
I
I
2-62
Control Register
I
I
I~--~~~~~r_--------~ II
I
I
I
I
IL _ _ _ _ _ _ _ _
I
I
I
_ _ _ _ _ _ _ _ _ _ _ _ ..1I
MB87087
PIN DESCRIPTION
PinNa.
SymbOl
1
OSC,.
<110
I
···.··i
.
.....
Description
Input pin for crystal oscillator.
Input to the inverting amplifier that forms part of the oscillator.
This pin receives the oscillator signal as AC coupled when an external oscillator is used. For large
amplitude signals (standard CMOS levels) DC coupling may also be used.
2
OSCOUT
0
3
fv
0
Output pin for crystal oscillator.
Output of the inverting amplifier. This pin should be open when an external oscillator is used.
Monitor output of the phase detector.
This pin is tied to the programmable divider output.
4
5
VOD
Do
-
Power supply voltage input.
0
Three-state charge pump output of phase detector.
The mode of Do is changed by the combination of programmable reference divider output frequency
fr, and programmable divider output frequency fv as listed below:
fr > fv:
Drive mode (Do = High level)
fro fv:
High impedance
fr < fv:
Sink mode (Do = Low level)
6
Vss
-
Ground.
7
lD
0
Output of phase detector.
It is high level when fr and fv are equal, and when the loop is locked.
Otherwise it outputs negative pulse signal.
8
fin
I
Clock input for programmable divider.
This input contains internal bias circuit and amplifier. The connection with an external dual-modulus
prescaler should be an AC connection.
9
Clock
I
Clock signal input for 17-bit shih register and 14-bit shih register.
Each rising edge of the clock shifts one bit of the data into the shih registers
10
Data
I
Serial data input for programmable divider and programmable reference divider.
The last bit of the data is the control bit. Control bit determines which latch is activated. The data
stored in the shih register is transferred to the 14-bitlatch when the bit is high, and to 17-bit latch when
low.
11
lE
I
Load enable input with internal pull up resistor.
When this pin is high (active high), the data stored in shift registeris transferred to 14-bitlatch or 17-bit
latch depending on the control bit data.
12
M
0
Control output for an external dual modulus prescaler.
The connection to the prescaler should be DC connection. This output level is synchronized with failing edge of input signal fin (pin #8).
Pulse swallow function:
e.g. MB501 L: M = High: Preset modulus factor 64 or 128
M = low: Preset modulus factor 65 to 129
2-63
MB87087
PIN DESCRIPTION
13
Ir
14
NC
o
Monitor output 01 phase detector input
This pin is tied to the programmable divider output
No connection.
o
o
15
16
(Continued)
OuIPUI for external charge pump.
The mode ol.R and +V is changed by the combination 01 programmable reference divider output
frequency fr and programmable divider output lrequency Iv as listed below.
fr > Iv:
fr= Iv:
frdv:
•R
.V
Low-level
High-level
High-level
High-level
High-level
Low-level
FUNCTIONAL DESCRIPTION
SERIAL DATA INPUT TIMING
Data
.(S14)
~~~~
Controlbll
(S2)
(Control bit)
(Sl)
----~
Clock - - - - '
LE
tl
.I I.
13
lft"
Is
• Data for programmable reference divider.
Notes:
Data: Serial data input is used for setting divide lactor 01 programmable reference divider and programmable divider. Data is input lrom
MSB, and laSI bit data is a control bit
Control blt is set high when divide factor 01 programmable reference divider is set. Control bit is set low level when divide lactor of
programmable divider is set.
Clock: Data is inpul to internal shift registers by rising edge of the clock.
LE: Load enable input:
When LE is high, the data stored in shift registar is transferred to l4-bit latch, or 17-billalch depending on the control bit setting.
2-64
MB87087
PULSE SWALLOW FUNCTION
fyco = [ (N x M) + A 1xfose + R (N > A)
fyeo
: Output frequency of external voltage controlled oscillator (VCO)
N
Preset divide factor of binary 1D-bit programmable counter (5 to 1023)
M
Preset modulus factor of extemal dual modulus prescaler
(e.g. 64 in 64165 mode, 128 in 128/129 mode of an MB501L presealer)
Preset divide factor of binary 7-bit programmable counter (0 to 127, A < N)
A
fose
R
Output frequency of external oscillator
: Preset divide factor of binary 14-bit programmable referenre counter (5 to 16383)
DIVIDE FACTOR OF PROGRAMMABLE REFERENCE DIVIDER
Serial data consists of 14-bit data, which is used for setting divide factor of programmable reference counter, and l-bit control data. In this case,
control bit is set high level.
The data format is shown below.
LSB
MSB
Data
l4-bit
Shift Register
Clock
l4-bit Latch
Programmable
Reference
Divider
Binary l4-bit Reference Counter
BINARY 14-BIT REFERENCE COUNTER DATA INPUT
Divide
Factor
@
@
@
@
0
0
0
0
0
0
0
0
0
0
0
1
0
1
5
0
0
0
0
0
0
0
0
0
0
0
1
1
0
6
0
0
0
0
0
0
0
0
0
0
0
1
1
1
7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16383
® ® 0
® ®
@
65165)prescaler
SW = H (64/65): Bit 7 to shift registerQ) should be zero.
BINARY 1D-BIT PROGRAMMABLE COUNTER DATA INPUT
@
@
@
@
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
..
@
@)
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
Divide
Factor
N
5
6
7
1
1
1
1
1
1023
@ @
Note: D,v,de factor less than 5 is prohibited.
Divide lactor N : 5 to 1023
2-66
® ®
I
I
I
MB87087
PHASE DETECTOR OUTPUT WAVEFORM
Iv
DeY
n
~RU
U
~V
LOU
I
U
¢
U
High Impedance
U
U
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage
Input Voltage
Operating Temperature
Vee
V,.
3.0
6.0
V
Vss
Vee
V
--40
"C
2-67
MB87087
ELECTRICAL CHARACTERISTICS
(VDD
High-Iewllnput Voltage
Low-level Input Voltage
Except fin
andOSC,.
V
VooxO.3
Vil
fin
Vfin
OSC,.
Vosc
Amplitude in AC
coupling, sine wave
0.5
Vp_p
0.5
I'H
VIN =
Veo
1.0
I'L
VIN
=
Vss
-1.0
fin
Ifin
VIN
= Vss to Veo
±30
IIA
OSC,.
lose
VIN
=
Vss to Voe
±30
IIA
ILE
VIN
= Vss
-40
IIA
Except fin
andOSC,.
Low-level Input Current
Input Current
VooXO.7
V'H
Input Sensitivity
High-level Input Current
=3.0V, Vss =OV, TA = -40 to 85°C)
LE
IIA
VOH
10H = 01lA
VOL
10L= 01lA
10H
VOH= 2.6V
-{l.5
10L
VOL = 0.4V
0.5
IOHM
VOH= 2.6V
-{l.7
Low-level Output Current
10'"
VOL = 0.4V
1.5
Power Supply Current. t
100
High-level Output Voltage
Except
OSCOUT
Low-level Output Voltage
High-level Output Current
V
Except M
and OSCOUT
Low-level Output Current
High-level Output Current
2.95
0.05
mA
M
2.5
mA
Maximum Operating Frequency of
Programmable Reference Divider
fmaxd
10
20
MHz
Maximum Operating Frequency of
Programmable Divider
fmaxp
10
20
MHz
Notes:
2-68
mA
*1: fin = 8.0MHz 11.5MHz Crystal is connected between OSC .. and OSCOUT.
Inputs are grounded except fin and OSC,•. Output are open.
MB87087
ELECTRICAL CHARACTERISTICS (Continued)
=5.0V
V,H
High·level Input Voltage
Vss =OV TA =-40 to 85°C)
D
VODxO.7
Except fin
low-level Input Voltage
andOSC'N
V
VIL
fin
Vfin
OSC'N
Vosc
Input Sensitivity
High·level Input Current
VooxO.3
Amplitude in AC
coupling, sine wave
0.5
Vp. p
0.5
IIH
VIN
= Voo
1.0
III
V,N = Vss
-1.0
fin
Ifin
VIN
VOD
±50
fIA
OSC'N
lose
V,N = Vss to Voo
±50
fIA
lE
ILE
VIN
-SO
fIA
Except
OSCOUT
VOH
10H = 0fIA
VOL
10L= OfIA
10.
VOH= 4.SV
-1.0
10L
VOL = 0.4V
1.0
IOHM
VOH = 4.SV
-1.5
Low-level Output Current
IOLM
VOL = 0.4V
3.0
Power Supply Current.'
100
Maximum Operating Frequency 01
Programmable Reference Divider
Imaxd
Maximum Operating Frequency 01
Programmable Divider
fmaxp
low-level Input Current
Input Current
High·level Output Voltage
Except fin
andOSC 'N
low-level Output Voltage
High-level Output Current
Except M
andOSCoUT
low-level Output Current
High-level Output Current
fIA
= Vss to
= Vss
4.95
V
0.05
mA
M
Note:
mA
3.5
mA
10
25
MHz
17
25
MHz
.1. fin = 8.0MHz, 11.5MHz Crystal is connected between OSC'Nand OSCOUT.
Inputs are grounded except lin and OSC,N. Outputs are open.
2-69
MB87087
TYPICAL CHARACTERISTICS CURVE
Input Sensitivity VS. Input Frequency (fin Section)
Voo = 5V. T. = 25·C
500
200
100
50
Input Sensitivity
Vlin (mV...)
20
"
J
~
../
10
5
2
5
10
20
Input Frequency fin (MHz)
2-70
50
100
MB87087
PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M04)
.-----z~;;;;:;;;?§;::::=t 15· MAX
.30017.62)
TYP
.05011.27)
--MAX-;--I
ill '988 FUJITSU LIMITED 0'60339-2(;
TYP
10.46±0.08)
.02010.51) MIN
Dimensions In
inches (millimetel'8)
2-71
MB87087
PACKAGE DIMENSIONS (Continued)
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M06)
.OS9(2.25) MAX
(SEATED HEIGHT)
r400: g~g(10 15~g~g~
i
I
_
!
307± 016
(7 SO±040)
.209±.012
J
(5.30±0.30)
1/;F;F;;=;;==rF"iT'i;r!=;;ll- I
\") - -
TVP
~~~1~.005(0.'3) ""'I
"A"
,,
.00S(0.20) I
.007 (0. 18) I
.004(0.10)
MAX
- .350(8.S9) REF
~
II> 1990 FUJITSU LIMITED FI8015S-2C
2-72
:
.027 (0.68)
:
_______M!'_X_____ I
Dirransions in
Inches (milHmeters)
OJ
April 1991
Edition 4.0
FUJITSU
DATA SHEET
MB87090
CMOS PLL FREQUENCY SYNTHESIZER
CMOS SERIAL INPUT PHASE·LOCKED·LOOP (PLL)
FREQUENCY SYNTHESIZER WITH CONSTANT
CURRENT OUTPUT CHARGE PUMP
The Fujitsu MBB7090, fabricated in CMOS technology, is a serial input PLL frequency
synthesizer with constant current output charge pump.
The MB87090 contains an inverter for oscillator, programmable reference divider, divide factor
of programmable reference divider control circuit, phase detector, constant current output
charge pump, 17·bi! shift register, 17-bit latch, programmable divider (binary 7-bit swallow
counter, binary I Q.bi! programmable counter), and a control generator for an extemal dual
modulus prescaler.
When supplemented with a loop filter and VCO, the MBB7090 contains the necessary circuit
to make up a PLL frequency synthesizer.
Unique to this device is a constant current output charge pump. This allows improved
modulation characteristics, tracking and noise performance compared to earlier devices.
•
PLASTIC PACKAGE
Dlp·16p·M04
Constant current output charge pump. Magnitude of current controlled by extemal
resistor: 0 to 4 mAo
•
13MHz input capability @5V (fin input)
•
Single power supply voltage: Voo
•
Wide temperature range: T. = -40 to 85"C
•
•
On-chip inverter for oscillator
Eight divide fectors for programmable reference divider are selected by external input
S" &.!, and Sa (1/8,1/16,1/64,1/128,1/256,11512,1/1024,112048)
•
Programmable 17-bit divider with input amplifier consisting of:
Binary 7-bit swallow counter
Binary I Q.bit programmable counter
•
Easy interface to Fujitsu dual modulus prescalers.
•
16·pin standard dual·in-line package (Suffix: ·P)
16-pin standard flat package (Suffix: ·PF)
= 2.7V to 5.5V
PLASTIC PACKAGE
FPT·16p·M06
PIN ASSIGNMENT
v..
osc.
ABSOLUTE MAXIMUM RATINGS (See NOTE)
(V.. =OV)
OSCCUT
Rating
Symbof
Value
Unit
Power Supply Voltage
Voo
V.s -0.5 to V.s +7.0
V
s,
V,N
V.s -0.5 to Voo +0.5
V
S,
S,
Input Voltage
VOIJT
Vss -0.5 to Voo +0.5
V
Output Current
lOUT
±IO
mA
Operating Temperature
T.
-40 to +85
"C
Output Voltage
Storage Temperature
Power Dissipation
NOTE:
TSTG
Po
~5
to +150
300
RC
"C
mW
Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
This device contains circuitry to protect the inputs against
damage due to high staticvollages or electric fields. However.
it is advised thaI normal precautions be taken to avoid
application of any voltage higher than maximum rated
VOltages to this high irrpedance circuit.
Copydgh' ©.99. by FUJITSU LIMITED
2-73
MB87090
Fig. 1 - MB87090 BLOCK DIAGRAM
--@v.s
VDD0: 17-BIT SHIFT REGISTER
asc,.
Clock
7-BIT
SHIFT REGISTER
Data
10-BIT
SHIFT REGISTER
..__--IJ" rJ"_IfJ"_lf"""
____T
l IT
_i ITITI
_l j_ J"_,r""'
__ .
,
_~
, 17-BIT LATCH
LE
:'., Ir-------"HH
0--...._
AMP
7-BITLATCH
10-BITLATCH
I
.~ ~{11 1111 ~ ~ ~ J] J11J 1111""""
CRYSTAL
, OSCILLATOR
,
DIVIDE FACTOR
OF PROGRAMMABLE
REFERENCE DIVIDER
CONTROL CIRCUIT
S.
S2
S,
ll-BIT
PROGRAMMABLE
REFERENCE
DIVIDER
f.
LD
7
Do
8
10 f.
PHASE
DETECTOR
9 RC
2-74
MB87090
PIN DESCRIPTION
PinNa.
Symbol
110
1
Vee
-
Power supply voltage input.
2
Clock
I
Clock signal input for 17-bit shift register.
Each rising edge of the clock shifts one bit of the data into the shift register.
3
Data
I
Serial data input for 17-bit shift register.
This data is used for setting the divide factor of programmable divider.
4
LE
I
Load enable input.
When this pin is high level (high active), the data stored in the 17-bit shift register is transferred to the
17-bit latch.
5
fin
I
Input for programmable divider from VCO or prescaler output.
This input involves bias circuit and amplifier. The connection with external dual modulus prescaler
should be an AC connection.
6
M
0
Control output for external dual modulus prescaler.
The connection to the prescaler should be DC connection. This output level is synchronized with failing edge of fin input signal (pin #5).
Pulse Swallow Function:
MBSOl L M = High: Preset modulus factor 64 or 128
M = Low: Preset modulus factor 65 or 129
7
LD
0
Output of phase detector.
It is high level when f, and fpare equal, and then the loop is locked. Otherwise it outputs negative pulse
signal.
8
Do
0
Three-state charge pump output of the phase detector.
The mode of Do is changed by the combination of programmable reference divider output frequency
f, and programmable divider output frequency fp as listed below:
f, > fpc Drive mode
(Do High level)
f, = fpc High-impedance mode
f. < fpc Sink mode
(Do Low level)
Descripllon
=
=
9
RC
I
10
f.
0
This pin is tied to programmable reference divider output.
11
12
13
S.
So
S3
I
I
I
Control input for programmable reference divider. The combination of these inputs provides divide
factor to programmable reference divider. See following page.
14
OSCOUT
0
Pin for crystal oscillator.
Output of the inverting amplifier. This pin should be open when an external oscillator is used.
15
OSC,.
I
Pin for crystal oscillator.
Inputto the inverting amplifier thatforms part olthe oscillator. This pin receives the oscillator signal as
AC coupled when an external oscillator is used.
For large amplitude signals (standard CMOS levels) DC coupling may also be used.
16
Vss
-
Ground
The value of external resistor connected to this pin determines the magnitude 01 the current delivered
by the charge pump. See graph on page 10.
2-75
MB87090
FUNCTIONAL DESCRIPTION
DIVIDE FACTOR OF PROGRAMMABLE REFERENCE DIVIDER
Divide factor of programmable reference divider is set depending on input dignal S, to S,.
~
1
-8
S,
0
1
0
1
0
1
0
1
S,
0
0
1
1
0
0
1
1
S,
0
0
0
0
1
1
1
1
1
1
1
---16
64
128
1
-256
1
1
1
--- -512
1024
2048
DIVIDE FACTOR OF PROGRAMMABLE DIVIDER
Serial data of binary code is input to Data pin. These data are loaded into the 17-bit shift register from MSB. When load enable signal LE is high,
the data stored in the 17-bit shift register is transferred to the 17-bit latch.
The data
0
to
0
set a divide factor olthe binary 7-bit swallow counter and data
G>
to
@
set a divide factor of binary 1O-bit programmable
counter. In other words, serial data is equivalent to the divide factor of programmable divider.
Fig. 2 - BLOCK DIAGRAM OF PROGRAMMABLE DIVIDER
LSB
MSB
17-BIT
SHIFT
REGISTER'
Data
Clock
17-BIT
LATCH
LE
.
---------r•
Binary 7-bit Swallow Counter
2-76
Binary 10-bit Programmable Counter
PROGRAMMABLE
DIVIDER
I
I
MB87090
Binary 7-bit Swallow Counter Data Input
0
® ®
G)
®
A)
Iveo
Output frequency of external voltage controlled oscillator (VeO)
N
Preset divide factor of binary 100bit programmable counter (5 to 1023)
M
Preset modulus factor of external dual modulus prescaler (e.g. 64 in 64/65 mode, 128 in 128/129 mode of an MB501L pre scaler)
A
Preset divide factor of binary 7-bit swallow counter (0 to 127)
fose
OUtput frequency of the external oscillator
R
Preset divide factor of programmable reference divider (8, 16, 64, 128, 256, 512, 1024,2048)
2-77
MB87090
CONSTANT CURRENT OUTPUT CHARGE PUMP
The MB87090 adopts constant current output charge pump. The output current of charge pump is controlled by an extemal resistor shown in
Fig. 3.
Fig. 3 - EXTERNAL RESISTOR CONNECTION EXAMPLE
10
7
-101.
LPF
RC
Do
8
9
10H
RRC
TIMING CHART
Data
___
~
Clock
LE
Clock: Clock signal input for the 17-bit shift register.
Each rising edge of the clock shifts one bit of data into the shift register.
Data : Serial data for the 17-bit shift register is input.
LE
: Load enable input.
When LE is high (high active), the data stored in the 17-bit shift register is' transferred to the 17-bit latch.
The 17-bit data is used for setting a divide factor of the programmable divider.
2-78
S,=LSB
MB87090
PHASE DETECTOR OUTPUT WAVEFORM
f'~
-
n n n
-
~
fp
-
i.....-
--.n
n
WLJ
u
U
U
Do
I
I
¢:I High
Impedance
RECOMMENDED OPERATING CONDITIONS
(Vss = OV)
Value
Parameter
Unit
Symbol
Min
Typ
Max
Power Supply Voltage
Voo
2.7
-
5.5
V
Input Voltage
V,N
Vss
-
Voo
V
Operating Temperature
TA
--40
-
+85
'C
2-79
MB87090
ELECTRICAL CHARACTERISTICS
(VDD = 3.0V, Vss = OV, TA = -40 to 85°C)
Value
Parameter
Unit
Condition
Symbol
Min
High-level Input Voltage
V,N
Except f,.
Low-level Input Voltage
andOSC,.
t..
V"
V",.
Input Sensitivity
OSC,.
High-level Input Current
Low-level Input Current
Exceptfm
andOSCIN
V...
Typ
Max
-
2.1
-
-
-
-
-
0.9
0.8
-
-
1.0
-
-
Amplitude in AC
coupling, sine wave
V
Vp.p
liN
VIN
VOO
-
1.0
-
hL
V,. = Vss
-
-1.0
-
=
flA
Input Current
fin
lfin
VIN
to Voo
-
±30
-
flA
Input Current
OSC,.
lose
V,. = Vss to Veo
-
±30
-
flA
Except
VON
ION = OflA
2.95
-
-
VOL
10L=
OflA
-
-
0.05
VOHX
ION =
OflA
2.50
-
-
VOLX
10L= OflA
-
-
0.50
ION
VON= 2.0V
-0.5
-
-
10L
VOL = 1.0V
0.5
-
-
IOHD
VON = 2.0V
-1.0
-3.0
-
Low-level Output Current
10LD
VOL= 1.0V
1.0
3.0
-
Power Supply Current·'
100
-
-
2.0
4.0
mA
fmaxd
-
13
20
-
MHz
fmop
-
10
20
-
MHz
High-level Output Voltage
Low-level Output Voltage
OSCOUT
High-level Output Voltage
= Vss
V
OSCour
Low-level Output Voltage
High-level Output Current
Low-level Output Current
Except Do
V
mA
and OSCour
High-level Output Current
Do·'
mA
Max. Operating Frequency of
Programmable Aeference Divider
Max. Operating Frequency of
Programmable Divider
Notes:
2-80
-1: AC pin extemal resistor ARC = SkU.
-2 to. = 5.0MHz, 12.8MHz Crystal is colVlected between OSC,.and OSCour.
AC pin extemal resistor A"" = 5kQ.
Inputs are connected to ground exoepl for f,. and OSC,•. Outputs are open.
MB87090
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 5.0V, Vss
= OV, TA = -40 to 85°C)
Value
Parameter
Symbol
Max
3.5
-
-
and OSC'N
V,L
-
-
-
1.5
t..
V~p
1.0
-
-
1.5
-
-
Input Sensitivity
OSC,.
Low-level Input Current
Typ
-
Except fi.
High-level Input Current
Min
V,H
High·level Input Voltage
Low-level Input Voltage
Unit
Condition
Except fin
and OSC'N
Amplitude in AC
coupling, sine wave
Vain
V
Vp.p
I'H
VLN
= Voo
-
1.0
-
k
VLN
= Vss
-
-1.0
-
pA
Input Current
fi•
IH"
VLN
.::
Vss to Voo
-
±50
-
pA
Input Current
OSC'N
lose
VIN
= Vss to Voo
-
±50
-
pA
Except
VOH
10H = OpA
4.95
-
-
VOL
10L= OpA
-
-
0.05
VOHX
10H = OpA
4.50
-
VOLX
10L= OpA
-
-
0.50
10H
VOH = 4.0V
-1.0
-
-
10L
VOL= 1.0V
1.0
-
-
iOHO
VOH= 4.0V
-2.0
-5.0
-
Low-level Output Current
IOLD
VOL= 1.0V
2.0
5.0
-
Power Supply Current-2
100
-
-
3.0
6.0
mA
fmaxd
-
15
25
-
MHz
fmaxp
-
13
25
-
MHz
High-level Output Voltage
Low-level Output Voltage
OSCOUT
High-level Output Voltage
V
-
OSCOUT
Low-level Output Voltage
High-level Output Current
Low-level Output Current
High-level Output Current
Except Do
and OSCOUT
Do·'
V
mA
mA
Max. Operating Frequency of
Programmable Reference Divider
Max. Operating Frequency of
Programmable Divider
Note:
§.
~
:;:
i=
iii
z
100
I::l
0..
!5
'"
2.0
50 ~5
3V
::l
0.5
I::l
0..
I::l
0.2
0
10
5
;::
1.0
a:
a:
~/
....
20
IZ
LU
"3V
5
10
50
20
5
100
INPUT FREQUENCY (MHz)
::l
~
0..
0..
::l
I. = 5.0MHz
«
§.
RRC = 5.0kQ
6
4
3
./
2
7
50
100 200
5001000
OSC,. = 12.8MHz
RRC = 5.0kQ
Voo = 5.0V
6
o
/
246
SUPPLY VOLTAGE (V)
15
5
~
3
a:
~
o
n.
4
~
0..
1il
~
I¢.00S(0.13) M·I
:D-;taii; ~f-'-:-B-:'-p~~t-:
' y . 0 0 6 1 0 . 1S ) ,
,, ,i
, :
II II!II,
I
.00810.20) I
:
.00710.18)
I
MAX
1
.027(O.6!:!)
I
~ ______ .M.A.X____
@1990FUJITSUlIMITEDF16015S-2C
2-84
~
.I
,i
.008(0.20) :
,
AClm
4r--r,;.0;n04
o,.1n;0)Cl
.3S018.89) REF -
,
,
"A"
I
.007(0.18) :
MAX
I
.027(0.68) :
L____ ____~~~ __ j
Dimensions in
inches (millimeters)
Sectien 3
Single-Chip PLLs/Prescalers - At a Glance
Page DevIce
Maximum
Frequency
Divide
Ratio
Supply
Icc
Vee
Programmabie
Counter
3-3
MBI501 1.1 GHz
1501H
1501L
64165 or
1281129
15mA
2.7 V 10 Binary
16102047
5.5V
Binary
010127
Binary
810 16383
16-pin Plastic
FPT
3-21
MBI502 1.1 GHz
64165 or
1281129
8mA
5.0 V
(typ)
Binary
16102047
Binary
010127
Binary
81016383
IS-pin Plastic
FPT
3-35 MBI503 1.1 GHz
1281129
8mA
5.0 V
(typ)
Binary
16102047
Binary
010127
Binary
8to 16383
IS-pin Plastic
FPT
3-49 MBI504 520 MHz
1504H
1504L
32133 or
64/65
10mA
2.7 V 10 Binary
16102047
5.5V
Binary
010127
Binary
810 16383
IS-pin Plastic
FPT
3-67 MBI505 600 MHz
32133 or
64/65
6mA
5.0 V
(typ.)
Binary
16102047
Binary
01063
Binary
8to 16383
IS-pin Plastic
FPT
3-79 MBI507 2.0GHz
1281129 or
2561257
18mA
5.0 V
(typ)
Binary
16102047
Binary
010255
Binary
810 16383
IS-pin Plastic
FPT
3-91
2561272 or
5121528
16mA
5.0 V
(typ)
Binary
32104095
Binary
01031
Binary
2O-pin Plastic
256,512,
FPT
1024,2048
3-101 MBI509· 400 MHz
32133 or
64165
8mA
3.0 V
(typ)
Binary
16102047
Binary
010127
2O-pin Plastic
Binary
512 or 1024 FPT
3-115 MB1511
1.1 GHz
64165 or
1281129
7mA
2.7VIo Binary
5.5 V
16102047
Binary
010127
Binary
8to 16383
2O-pin Plastic
FPT
3-127 MB1512 1.1 GHz
64165 or
8mA
5.0 V
(typ)
Binary
16102047
Binary
010127
Binary
810 16383
2O-pin Plastic
FPT
MBI508 2.5GHz
1281129
3-139 MB1513 1.1 GHz
128129
8mA
5.0 V
Binary
16102047
Binary
010127
Binary
810 16383
2O-pin Plastic
FPT
3-153 MB1518 2.5 GHz
5121528
16mA
5.0 V
(typ)
Binary
3210511
Binary
01031
512
IS-pin Plastic
FPT
Binary
010127
512,1024
2O-pin Plastic
FPT
3-163 MB1519· 600 MHz
64165
lImA
2.7 V 10 Binary
5.5 V
16102047
II)
Swallow Reference Package
Optlona
Counter Counter
·Dual PLUPrescaier
3-1
Siaqlt-Cbiq PLue"scaltrs
III
3-2
TelecqmmUlgtjoas Data Book
Qj
November 1990
Edition 5.0
FUJITSU
DATA SHEET
niB 15011AfB1501HIAfB1501L
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 1.1 GHz PRESCALER
The Fujitsu MB1501lMB1501HIMB1501L, utilizing BI-CMOS technology, is a
single chip serial input PLL frequency synthesizer with pulse-swallow function.
The MB1501 series contain a 1.1 GHz two modulus prescaler that can select either
64/65 or 12BI129 divide ratio; control signal generator; 16-bit shift register; 15-bit
latch; programmable reference divider (binary 14-bit programmable reference
counter); l-bit switch counter; phase comparator with phase inverse function;
charge pump; crystal oscillator; 19-bit shift register; 1B-bit latch; programmable
divider (binary 7-bit swallow counter and binary ll-bit programmable counter).
The MB1501 operates on a low supply vottage (3Vtyp) and consumes low power
(45mWat 1.1 GHz).
PLASTIC PACKAGE
DIP·16p·M04
MB1501 Product Line
Vp
Voltage
MB1501
BV max
MB1501H 10V max
MB1501L BV max
Voop
Vottage
Lock up
time
B.5V max Middle speed
10.0V max Hioh speed
B.5V max Low speed
Do
Ou~ut
Wi h
Middle
Low
Hioh
High-level LOW-level
Output
Output
Current
Current
Middle
Middle
Hioh
Low
Low
HiQh
• High operating frequency: f'NMAX=l.lGHz (V'NM'N=0.20Vp.p)
• On-chip prescaler
• Low power supply voltage: 2.7V to 5.5V (3.0V typ)
• Low power supply consumption: 45mW (3.0V, 1.1 GHz operation)
• Serial input lB-bit programmable divider consisting of:
o Binary 7-bit swallow counter (Divide ratio: 0 to 127)
o Binary l1-bit programmable counter (Divide ratio: 16 to 2047)
• Serial input 15-bit programmable reference divider consisting of:
o Binary 14-bit programmable reference counter (Divide ratio: B to 163B3)
o l-bit switch counter (SW) Sets divide ratio of prescaler
• 2types of phase detector output
o On-chip charge pump (Bipolar type)
o Output for external charge pump
• Wide operating temperature: T.=-40·C to +B5·C
PLASTIC PACKAGE
FPT·16p·M06
PIN ASSIGNMENT
OSC'N
OSCOUT
Vp
0R
0P
fp
Vee
Do
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
Symbol
Vee
VPH
Vp,VPI.
Vo,,",
Power Supply Voltage
Output Voltage
Open-drain Output
Output Current
Storage Temperature
NOTE:
Copyr~ht"
VOOPH
VoopVoop
lOUT
TSTG
Condition
MB1501H
MB1501/1501L
MB1501H
MB150111501L
GND
Value
Unit
-0.5 to +7.0
Vee to 12.0
Vee to 10.0
-0.5 to Vee +0.5
-0.5 to 11.0
-0.5 to 9.0
±10
-55 to +125
V
LD
fin
LE
Data
Clock
V
V
V
mA
·C
This device contains circuitry to protect the Inputs against
damage due to high static vertag86 or eleclric fields. However, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum
rated voltages to this high Impedance circuit.
Permanent device damage may occur if the above Absolute Maximum
Ratln~s are exoeeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect devioe
reliability.
1990 by FUJITSU L... ITED
3-3
MB1501
MB1501H
MB1501L
MB1501IMB1501H/MB1501L BLOCK DIAGRAM
Vee0--
r------------,
I
16-Bit Shift Register
I
16-Bit Shift Register
I
GND0--
I
:J1Unllllilln=:
I
I
LE
I
I
I
I
I
I
15-Bn Latch
l1r------------rr-~i---~~~~~ I
15-Bn Latch
13
f,
12
FC
]IllIIl1Illl[:
asc,.
asc
I
I
I
Programmable
Reference Divider
LD
I
I
0R
Binary 14-Bn
Reference Counter
0P
OUT
r-----------------,
I
I
19-Bit Shift Register
+-1--11.....
19-Bit Shift Register
I
I
I
:=OJ]lIr[OJlllrOJ=:
I
18-Bit Latch
v.
Charge
Pump
Do
I
I
I II
:=m]II[m11IrrrJ1~~_'--__
I
l1-BitLatch
I
Programmable Divider
,--.---r14
I
I
I
~~~~--~~--~~----~I
3-4
f.
MB1501
MB1501H
MB1501L
PIN DESCRIPTIONS
Pin No.
Pin Name
I/O
1
2
OSC,.
OSCOUT
0
Oscillator input.
Oscillator output.
A crystal is placed between OSC,. and OSCOUT•
3
Vp
-
Power supply input for charge pump.
4
Vee
-
Power supply vottage input.
5
Do
0
Charge pump output.
Phase characteristic can be inversed depending upon FC input.
6
GND
-
Ground.
7
LD
0
Phase comparator output.
This pin outputs high when the phase is locked. While the phase difference of f, and fp exists,
the output level goes low.
8
fin
I
Prescaler input.
The connection with an external VCO should be an AC connection.
9
Clock
I
Clock input for 19·bit shift register and 16·bit shift register.
Each rising edge of the clock shifts one bit of data into the shift registers.
10
Data
I
Serial data of binary code input.
The last bit of the data is a control bit. The last data bit specifies which latch is activated.
When the last bit is high level and LE is high-level, data is transferred to 15-bit latch.
When the last bit is low level and LE is high level, data is transferred to 18-bit latch.
11
LE
I
Load enable input (with internal pull up resistor).
When LE is high level (or open), data stored in the shift register is transferred to latch depending on the control data.
12
FC
0
Phase selecting input of phase comparator (with internal pull up resistor)_ When FC is low
level, charge pump and phase detector characteristics can be inversed.
13
f,
0
Monitor pin of phase comparator input.
It is the same as programmable reference divider output.
14
Ip
0
Monitor pin of phase comparator input.
It is the same as programmable divider output.
15
16
0P
0R
0
0
Outputs for external charge pump.
Phase characteristics can be inversed depending on FC input.
I
Descriptions
0P pin is an N-channel open-drain output.
3-5
MB1501
MB1501H
MB1501L
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is input using Data pin, Clock pin and LE pin, The lS-bft programmable reference divider and 18-bft programmable
divider are controlled respectively.
On rising edge of the clock shifts one bit of the data into the internal shift registers.
When load enable (LE) is high level (or open), data stored in shift resisters is transferred to 1S-bft latch or 18-bft latch depending upon
the control bit level.
Control data "W ; Data is transferred into 1S-bit latch.
Control data "L" ; Data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, IS-bit latch and 14-bit reference counter. 5erial16-bit data format is
shown below.
---------t•• Data input
First data input
Last data input
@
14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide
ratio
R
5
S
5
5
5
5
5
5
S
5
S
S
S
5
14
13
12
11
10
9
8
7
6
S
4
3
2
1
8
0
0
0
0
0
0
0
0
0
0
1
0
0
0
9
0
0
0
0
0
0
0
0
0
0
1
0
0
1
•
..
1
1
1
. ...........
16383
1
1
1
1
1
1
1
1
1
1
Divide ratio less than 8 is prohibited.
Divide ratio R: 8 to 16383
SW: Divide ratio of prescaler setting bit.
SW="H": 64
5W="L": 128
5. to 5,,: Divide ratio of programmable reference counter selling bits (8 to 16383)
C: Control bit (Control bit is set to high.)
3-6
1
MB1501
MB1501H
MB1501L
FUNCTIONAL DESCRIPTIONS
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and ll-bit programmable counter.
Serial 19-bit data format is shown below.
!
• Data input
Last data input
!
r
MSB.!
SISISISISISIS
1
2
3
456
7
Ic
SISls
s l 12
sls
s l 15
s l 16
sls
s
10 l 11
13 l 14
17 l 18
8
9
Ie- Divide ratio of swallow counter
setting bits
@)
First data input
Control bit
LSB
7-BIT SWALLOW COUNTER DIVIDE RATIO
Divide ratio of programmable counter
setting bits
@)
ll-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide
ratio
A
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
6
5
4
3
2
1
Divide
ratio
N
S
7
18
17
16
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
16
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
17
0
0
0
. . .
0
0
0
1
0
0
0
•
.... ..
1
1
1
1
1
1
1
1
1
1
•
127
.......
1
1
Divide ratio A : 0 to 127
1
1
1
1
1
•
2047
1
1
•
Divide ratio less than 16 is prohibited.
Divide ratio N : 16 to 2047
s. to S.. : Divide ratio of programmable counter setting bits (16 to 2047)
S, to S, : Divide ratio of swallow counter setting bits (0 to 127)
C: Control bit (Control bit is set to low.)
Dara is input from MSB data.
3-7
MB1501
MB1501H
MB1501L
SERIAL DATA INPUT TIMING
Data
SI8=MSB
'(SW)
S17
S10
S9
SI=LSB
(SI4)
(S8)
(S7)
(SI)
Clock
X
C: Control bit
(C:Control bit)
r-n___ .... -1nL.JnL - -
.... _
LE
t,-I--+O""
On the rising edge of the clock sh~ts one bit of the data into the shift registers.
Parenthsis data is used for setting the divide ratio of the programmable reference divider.
PHASE CHARACTERISTICS
VCO CHARACTERISTICS
FC pin (pin 12) is provided to inverse the phase comparator
characteristics. The characteristics of internal charge pump output
(Do), phase detector outputs ("R, "P) can be inversed depending
upon FC input data. Outputs are shown below.
FC=H (or open)
FC=L
Do
0R
0P
Do
lOR
lOP
f,>f,
H
L
L
L
H
Z
f,
£1
Cl
to
MB~501
'[ 7.0
>
MB1501H
::>
9- 1.0
::>
0
'5
0
a;
a;
>
.!!!
>
Q)
3:
1;
.3
.2'
:r:
MB1501L
'5
MB1501L
~
MB1501
MB1501H
Q)
\
Cl
I
5
\
>
10L
I
~ 2.0
~ 8.0
vs.
6.0
0.0
0
-1
-2
-3
-4
High-level Output CurrentloH (rnA)
-5
0
10
Low-level Output Current
20
10L
(rnA)
3-11
MB1501
MB1501H
MB1501L
Do PIN OUTPUT WAVEFORM AT LOCK CONDITION
Output Waveform
(
lV/div
tL-__"~
100nsldiv
MB1501
,
I
I
MB1501H
I
r
MB1501L
....... V'
I
/-
3-12
J
MB1501
MB1501H
MB1501L
PHASE CHARACTERISTICS
(~f VS.
Do OUTPUT ENERGY)
150
~
100
l ~~
50
~
I
c:
I:!:!-
~
0
>-
e>
Q)
100
80
60
c
40
20
~
~: /
"
~.
~'
V'~O
20
60
80
UJ
-50
-100 I--
-150
~-
MB1501HI
- - - MB1501
- - - MB1501L I
/
.......... ....
V ""
,,'
_....
,."
._-
Timellf (ns)
VP10k
.
D
f t : Oscilloscope
a
10k
Vcc= Vp=3.0V ]
[ f'Nsfosc=12MHz
f.=fp=46.9kHz
3-13
MB1501
MB1501H
MB1501L
INPUT SENSITIVITY
Input Sensitivity vs. Input Frequency (Supply Voltage Dependence)
I
+10
E
°~
aJ
:!?.
-; -10
I
Guaran188dArea
Operating
Vcc-4.o-s.sv
1--I..........
'[ -40
.E
-
J" ~
~ io"
.r-
Vcc-2.7-4.0V
.--
,.,
:~ -20
'i,l
lii -30
C/)
I-\..
Vcc=S.SV
----
~
~\
~
V rc=2.7V
Vee=4.SV
-50
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Input Frequency fin (GHz)
B-f
000PF
P.G
8
SOQ
14
6
Input Sensitivity vs. Input Frequency (Temperature Dependence)
I
+10
o
-; -10
~
Guarantood
Operating Area
Vcc-4.0-5.5V
Vcc·2.7-4.0V
I
-~ ~
........ ~
I
I - - r- T'=1 00C
~
,.,
,'">
~
~
1
-20
c1l -30
~
T.=+2SOC
I
T.=+8SOC
::::::::;;0 i"""
'[ -40
.E
-50
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Input Frequency fin (GHz)
<> Vee =3.0V
B-f
000PF
P.G
SOQ
3-14
8
14
6
1.8
1.9
MB1501
MB1501H
MB1501L
INPUT IMPEDANCE
lOMHz
100M Hz
200MHz
500MHz
TEST CIRCUIT
Do Pin Output Current (loH, 10l) Measurement
Vee
Vp
asc,.
D o - loL
MB1501
-loH
3-15
MB1501
MB1501H
MB1501L
Lock up Time Measurement
Oscilloscope (10MQ, 10pF)
LPF Circu~
lkQ
4kQ
o--J#.TWo.
lkQ
10~F
Vcc=3V, Vp =8V
[ fvco=Low unlock condition
fvco=High unlock condition
-
Step to Lock condition (533MHz)
Step to Lock condition (518MHz)
1
Phase Characteristics Measurement
10kQ
OSCin
------10kQ
fin
fp
Vcc=3V, Vp =3V
[ Af=fr-fp
Energy (En)=V2t
3-16
-------------
Oscilloscope
(10MQ, 10pF)
1
MB1501
MB1501H
MB1501L
TYPICAL APPLICATION EXAMPLE
. - - - - - - , OUTPUT
Charge Pump Selection
(Internal or external)
12kn
FROM
CONTROLLER
12kn
0R
16
~}
FC
0P
15
14
13
11
12
47kQ
LE
10
MB1501
2
OSC,•
3
OSCOUT
456
V,
Vee
Do
7
GND
8
LD
1000pF
Vee(3V)
LOCK DET.
C" C. : Depends on crystal oscillator
LE,FC: With internal pull up resistor
0P
: Open drain output
3-17
MB1501
MB1501H
MB1501L
PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-16P-M04)
\
.----'/J=-;;;-g;---:;;:-=:?;~-:4 15' MAX
I
.300(7.62)
TYP
l_~~
.010±.002
(0.25±0.05)
E50(1.27)
MAX
© 1988 FUJITSU LIMITED D16033S-2C
3-18
.020(0.511 MIN
Dimensions in
inche;s (millimeters)
MB1501
MB1501H
MB1501L
PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(Case No.: FPT-16P-M06)
I~' g;,g,,,
"'8l}"
307± 016
(7 80± 0 401
.209±.012
(5.30±0.30)
,_.",/
U
"8"
1Ini=iF;:;=;;=;:~9=;;Y __l
:")
l
".00510.13)
U1
268~g6~1680~g:~)
i
1.020±.008
===t10.50±0.20)
- - --.
~~$I
TYP
.00210.05) MIN
-1ISTAND OFF)
!
INDEX
.05011.27)
089(225) MAX
ISEATED HEIGHT)
~006~:gg~10 15~gg~)
10\)1
:D-;taii;~f-';B-;'-p~rt-:
"A"
II
II
II
,
,,
II ,II'
:
.00810.20) I I
.00710.18) , :
1; ~'"';-,'
L,,=::-r,.0,",0;;;4"(0-.
-.- .35018.89) REF -
MAX
:
~
'Cl1990 FUJITSU LIMITED F16015S-2C
il Hq""'i
I
.008(0.20) :
I
.00710.18) :
MAX
I
.027(0.68) :
.02710.68): :,
I
______ !"!.A_X_____ I L. ________~~~ __
Dimensions in
J
inches (millimeters)
3-19
MB1501
MB1501H
MB1501L
3-20
00
FUJITSU
June 1991
DATA SHEET
MB1502
Serial Input PLL Frequency Synthesizer
The Fujitsu MB1502 fabricated in Bi-CMOS technology, is a single chip serial input
PLL synthesizer with pUlse-swallow function.
The MB1502 contains the following: analog switch to speed up lock uptime, control
signal generator, 16-bit shift register, 15-bit latch, programmable reference divider
(binary 14-bit programmable reference counter), l-bi! switch counter, phase
comparator with phase conversion function, charge pump, crystal oscillator, 19-bit
shift register, la-bit latch, programmable divider (binary 7-bit swallow counter and
binary ll-bit programmable counter) and a 1.1 GHztwo modulus prescalerthat can
select either a 64165 or 128/129 divide ratio.
Plastic Package
DIP·16p·M04
It operates supply voltage of 5 V typo and achieves very low power supply current of
8 mA typo realized through the use of Fujitsu Advanced Process Technology.
•
High operatin9 frequency: fIN MAX = 1.1 GHz (VIN MAX = -10 dBm)
•
Pulse swallow function: 64/65 or 128/129
•
Low supply current: Icc = a mA typo
•
Serial input 18-bit programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary ll-bit programmable counter: 16 to 2047
•
Serial input 15-bit programmable reference divider consisting of:
- Binary 14-bit programmable reference counter: 8 to 16383
- l-bit switch counter (SW) sets divide ratio of prescaler
•
On-chip analog switch achieves fast lock up time
•
Two types of phase detector output:
- On-chip charge pump (Bipolar type)
- Output for external charge pump
•
Wide operating temperature: -40 °C to +85 °C
•
16-pin Plastic DIP Package (Suffix:-PI
16-pin Plastic Flat Package (Suffix: -PF)
Plastic Package
FPT·16p·M06
Pin Assignment
OSC IN
0
fj>R
OSCOUT
fj>P
Vp
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Symbol
Ratings
Unit
BISW
Do
TOP VIEW
FC
Vce
-0.5 to +7.0
V
GND
Vp
Vccto 10.0
V
LD
Data
-0.5 to Vcc +0.5
V
fiN
Clock
Output Voltage
VOUT
Open-drain Voltage
Voop
-0.5 to 0.8
LE
V
Output Current
lOUT
±10
mA
Storage Temperature
TSTG
-55 to +125
°C
Note: Permanent device damage may occur if absolute maximum ratings
are exceeded. Functional operation should be restricted to the conditions as detailed in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
©
fOUT
Vcc
This devloa con1alns clraJkry to pIOIeCt tho Inpu1S against
damage due to high static voIIagea or eleclrk:: fields. Hcr.vever, h
is advised that normal precaulions be taken to avoid application
or any vottage higher than maxinJm rated volages to this high
~noacJroult.
1991 by FUJITSU LIMITED and Fu"," Mlcroel"'ronlcs.lnc.
3-21
MB1502
MB1502 BLOCK DIAGRAM
.-------------,
I
I
I
l6-BIT SHIFT REGISTER
l6-BIT SHIFT REGISTER
I
I
I
I
~JrnIOJH1J===~
I
l5-BIT LATCH
I
~~-------------,I
l5-BIT LATCH
I
~--------------~I
rIL.JrnIOJfOI===-'II
PROGRAMMABLE REFERENCE
DIVIDER
I
BINARY l4-BIT
REFERENCE COUNTER
L_..-_-_-_-_-_-_-_-_-_-_.L..I_.J
Do
5~---------++---------------------~r-r--r----------~
~--------------------------~----------------~--~ll
r------------,
I
19-BIT SHIFT REGISTER
I
I
I
I
19-BIT SHIFT REGISTER
I
~IrnIOJfOJrnI~
I
I
fiN
8
PRESCALER
la-BIT LATCH
7-BIT LATCH 11'"'1-1-B-IT-L-A-TC-H"1
I
!
~JmJmr.flmlI_~---,
PROGRAMMABLE DIVIDER
I
I
I
I
L_~_~_~_~_~_~~~rT~~~
3-22
I
I
LE
MB1502
PIN DESCRIPTION
Pin No.
Pin Name
110
Description
1
2
OSC,.
OSCour
I
0
Oscillator input.
Oscillator output.
A crystal is placed between OSC,. and OSCOUT '
3
Vp
-
Power supply input for charge pump and analog switch.
4
Vee
-
Power supply voltage input.
5
Do
0
Charge pump output.
The characteristics of charge pump are reversed depending upon Fe input.
6
GND
-
Ground.
7
LD
0
8
f,.
I
9
Clock
I
Phase comparator output.
Normally this pin outputs high level. While the phase difference of f, and fp exists. this
pin outputs low level.
Prescaler input.
The connection with an external VCO should be AC connection.
Clock input for 19-bit shift register and lG-bit shift reaister.
Each rising edge of the clock shifts one bit of data into the shih register,
10
Data
I
Binary serial data input.
The last bit of the data is a control bit which specified destination of shift registers.
When this bit is high level and LE is high level. the data stored in shift register is transferred to IS-bit latch. When this bit is low level and LE is high level, the data is transferred to IS-bit latch.
11
LE
I
Load enable input (with internal pull up resistor).
When LE is high or open. the data stored in shift register is transferred into latch depending upon the control bit. At the time. internal charge pump output to be connected
to BISW pin because internal analog switch becomes ON state.
12
FC
I
Phase select inlJUt of phase comparator (with internal pull up resistor).
When FC is low level. the characteristics of charge pump. phase comparator is reversed.
FC input signal is also used to control f... pin (test pin) output level. f, or fp.
13
BISW
0
Analog switch output.
Usually BISW pin is set high-impedance state. When internal analog swnch is ON (LE
pin is high level). this pin outputs internal charge pump state.
14
loUT
0
Monitor pin of phase comparator input.
f"" pin outputs either programmable reference divider output (f,) or programmable divider output (fp) depending upon FC pin input level.
FC=H: It is the same as f, output level.
FC=L: It is the same as fp output level.
15
16
~~
0
0
Outputs for external charge pump.
The characteristics are reversed according to FC input.
0P pin is N-channel open drain output.
3-23
MB1502
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable
reference divider and 18-btt programmable divider. respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open,
stored data is transferred into latch depending upon the control bit.
Control data "H" data is transferred into 15-bit latch.
Control data "L" data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register. 15-bit latch and 14-bit reference counter. Serial 16-bit data format is
shown below.
r--
-----I
Divide ratio of programmable reference counter setting btt
14·BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide
Ratio
R
S
S
S
S
S
S
S
S
S
S
S
S
S
S
14
13
12
11
10
9
8
7
6
5
4
3
2
I
8
0
0
0
0
0
0
0
0
0
0
I
0
0
0
9
0
0
0
0
0
0
0
0
0
0
I
0
0
1
•
•
•
•
•
.......
•
•
•
16383
1
1
1
1
1
I
1
1
1
1
1
1
I
I
NOTES: Divide ratio less than 8 is prohibited.
Divide ratio: 8 to 16383
SW:This bit selects divide ratio of prescaler.
SW=H :64
SW=L :128
Sl to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets as high level).
Data is input from MSB side.
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register. 18-bit latch. 7-bit swallow counter and ll-bit programmable counter.
Serial19-bit data format is shown on the following page
3-24
MB1502
-I-
Divide ratio of swallow
counter
setting bit
Divide ratio of programmable
counter
setting bit
7-BIT SWALLOW COUNTER DIVIDE RATIO
Divide
Ratio
S
S
S
S
S
S
S
A
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
127
1
1
1
1
1
1
1
. .......
NOTE: Divide ratio: 0 to 127
11·BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide
Ratio
S
S
S
S
S
S
S
S
S
S
S
N
18
17
16
15
14
13
12
11
10
9
8
16
0
0
0
0
0
0
1
0
0
0
1
17
0
0
0
0
0
0
1
0
0
0
1
2047
1
1
1
1
1
1
1
1
1
1
1
. ...........
NOTES: Divide ratio less than 16 is prohibited.
Divide ratio: 16 to 2047
S 1 to S7: Swallow counter divide ratio setting bit. (O to 127)
S8 to S18: Programmable counter divide ratio setting bit. (16 to 2047)
C: Control bit (sets as low level).
Data is input from MSB side.
PULSE SWALLOW FUNCTION
Ivco= [(PxN)+A] xlosc+R
fvco: Output frequency of external voltage controlled oscillator (VCO)
N: Preset divide ratio of binary II-bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (f.
H
L
L
(f,)
L
H
Z
(fp)
I,d.
L
H
Z
(f,)
H
L
L
(fp)
f,:f.
Z
L
Z
(f,)
Z
L
Z
(fp)
Do
Nota:
FC=L
Z=(High impedance)
Depending upon VCO characteristics, FC pin should be set accordingly:
When VCO characteristics are like
FC should be sel High or open circuit;
When VCO characteristics are like@, FC should be set Low.
CD,
3-26
VCO INPUT VOLTAGE -
MB1502
t
LOU
00···-4-·······~···
1,>1.
t
t
z
t
L
U
U U L
···u·····-U----v···l.I,d.
1,=1.
I,d.
I,d,
NOTES: Phase dfflerence detection range: -2n to +2n
Spike appearance dep'ends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When 1,>lp or I,d., spike might not appear depending upon charge pump characteristics.
ANALOG SWITCH
ON/OFF of analog switch is controlled by lE input signal. When the analog switch is ON, internal charge pump output (Do) is
connected to BISW pin. When the analog switch is OFF, BISW pin is set to high-impedance state.
lE-H (Changing the divide ratio 01 internal prescaler) : Analog switch=ON
LEal (Normal operating mode)
: Analog switch=OFF
lPF time constant is decreased in order to insert a analog switch between LPFI and LPF2 when channel of PLL is changing.
Thus, lock up time is decreased, that is, fast lock up time is achieved.
------------------.0
I
0
CHARGE PUMP
,
..
_-_ ....... _-_ ...... _-,
I
, BISW
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Unit
Symbol
Min
Typ
Max
Vee
4.5
5.0
5.5
V
Vp
Vee
V,
8.0
V
V,
GNO
Power Supply Voltage
Input Voltage
Operating Temperature
T.
-40
Vee
V
85
·C
3-27
MB1502
ELECTRICAL CHARACTERISTICS
(Vcc=4.5 to 5.5V, TA=-40 to +85°C, unless otherwise noticed.)
Parameter
Symbol
Power Supply Current
Condition
Value
Min
Unit
Typ
Max
S.O
12.0
mA
1100
MHz
20
MHz
6
dBm
Icc
Note 1
fin
fm
Note 2
OSC,.
lose
1m
VI;"
-10
OSC,.
Vase
0.5
Vpp
Except Ii"
andOSC,.
V,"
VccxO.7
V
Data
Clock
I,"
1.0
j1A
I'L
-1.0
j1A
OSC,.
lose
±50
j1A
LE,FC
I...
-60
j1A
10
Operating Frequency
Input Sensitivity
High-level Input VoHage
Low-level Input Voltage
High-level Input Current
Low-level Input Current
12
VccxO.3
V'L
V
Input Current
High-level Output Current
Low-level Output Current
Except Do
and OSCOUT
Vo.
Vcc=5V
4.4
V
VOL
0.4
V
1.1
j1A
N-channel Open Drain
Cutoff Current
Do,0P
IoFF
Except Do
and OSCOUT
10 "
-1.0
mA
Output Current
IOL
1.0
mA
Analog Switch On Resistor
RON
Vp=Vcc to SV
Voop=GND to 8V
25
NOTE 1: f =1.1GHz, OSC,~=12MHz, V<;c=5V. Inputs are grounded and outputs are open.
NOTE 2: lc coupling. Minimum operating frequency is measured when a capacitor 1000pF is connected.
3-28
n
MB1502
TYPICAL CHARACTERISTICS CURVES
INPUT SENSITIVITY CHARACTERISTICS
asc,. Input Sensitivity vs. Input Frequency
fin Input Sensitivity vs. Input Frequency
Vcc=5.0V
Vcc=5.0V. T.=25 DC
20
+5
10
o
Input
Sensitivity
V",
o
-5
Input
Sensititity -101-+-+-Httttit--t+HtHtt......,H--I
Vosc
(dBm) -10
-15
(dBm) -20
1-+-+-Httttit--t+~Htt......,H--I
H"""'I-+-+-t-I-+--:fo's-q.-H
5
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.31.4 1.5
Input Frequency fin (GHz)
10
50 100
Input Frequency OSC,. (MHz)
I-c= P.G
P.G
9 10 11 12 13 14 15 16
Oscilloscope
Oscilloscope
3-29
MB1502
INPUT IMPEDANCE CHARACTERISTICS
20MHz
lOOMHz
200MHz
lOOOMHz
~-t---500MHz
3-30
MB1502
TYPICAL APPLICATION EXAMPLE
r-----, OUTPUT
Charge Pump
Selection
(Internal or
external)
12k
FROM
CONTROLLER
12k
0R
16
0P
15
LE
14
13
12
Data
11
10
6
7
47k
MB1502
2
OSC,.
4
3
OSCom V.
5
Vee
GND
8
LD
1000p
6V
Vcd5V)
5V
LOCKDET
V•• V.x
C,. C.
LE.FC
0P
8V max.
Depends on crystal oscillator
With internal pull up resistor
Open drain output
3-31
MB1502
PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No, : DIP-16P-M04)
15'MAX
-~u::::::::
~QI1P)
MAX
I--+-~~--'- --tt~-;;-;-;~
© 1988 FUI1TSU LIMITED D16033S-2C
3-32
,02010.51) MIN
Dimensions in
inches (millimeters)
MB1502
16-LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT-16P-M06)
h
089(22S1 MAX
(SEATED HEIGHTI
1--400+ 010(10 15+ 025
I
- 008
-020
I
.002(0.OSI MIN
l(STAND OFF)
_
307± 016
1(780±0401
.209±.012
(S.30±0.301
i.. )
TYP
-=l_J
l
U
.268~g6~(6.80~g:~gl
I
II-==t-j
JLOI8t.004r.~~===~
(O~$I ~.00S(0.131 iMll
.020±.008
(0.SO±0.201
-11- .006 ~gg~ (0. 15 ~ 8:g~1
If·
--------- ----,
Details of "S" part :
··A··
0 06 (0.ISI:
,
.004(0.101
.350(8.891 REF
,
.008(0.201 :
.007(0.181 '
MAX
.027(0.681 I
~--- -- - -~~-----:
© 1990 FUI1TSU LIMITED F16015S-2C
~i
.008(0.201 :
.007(0.18)
!
MAX
:
.027(0.681 :
MAX
L _____________
J'
Dimensions in
inches (millimeters)
3-33
MB1502
3-34
cP
FUJITSU
September 1991
DATA SHEET
MB1503
Serial Input PLL Frequency Synthesizer
The Fujitsu MB1503 is a serial input phase-locked loop (PLL)frequency synthesizer
with a pulse-swallow function. A stand-by mode is provided to limit power
consumption during intermittent operation.
The MBI503 is configured with a 1.1 GHz dual-modulus prescaler with a 128/129
divide ratio, control signal generator, 16-bit shift register, IS-bit latch, programmable reference divider (binary 14-bit programmable reference counter), 1-bit
switch counter, phase comparator with phase conversion function, charge pump,
crystal oscillator, 19-bit shift register, IS-bit latch, programmable divider (binary
7-bit swallow counter and binary ll-bit programmable counter), analog switches,
and intermittent operation control circuit that selects the operating or stand-by mode
depending on the power-save control input state (PS).
FPT·1SP·M06
The MB1503 operates from a single +5 V supply. FUjitsu's advanced technology
achieves an Icc of 8 mA, typical. The stand-by mode current consumption is just
100 IJA.
•
High operating frequency: fiN = 1.1 GHz (VIN = -1 0 dBm)
•
Pulse-swallow function: hil;lh-speed dual-modulus prescaler with 128/129
diVide ratio
•
Low supply current: Icc = 8 mA typo at 5 V
•
Power-saving stand-by mode: 100 IJA
•
Serial input, 18-bit programmable reference divider consisting of:
Binary 7-bit swallow counter: 0 to 127
Binary II-bit programmable counter: 0 to 2,047
•
Serial input, 15-bit programmable reference divider consisting of binary 15-bit
programmable reference counter: 8 to 16,383 I-bit switch counter sets
prescaler divide ratio
•
On-chip analog switch for fast lock-up
•
On-chip charge pump
•
Wide operating temperature range: -40 to +85 °C
•
Plastic IS-pin dual in line package (Suffix: -PI
Plastic IS-pin small outline package (Suffix: -PF)
DIP·16P·M04
Symbol
PS
OSCIN
OSCOUT
Value
fR
fp
Vp
ABSOLUTE MAXIMUM RATINGS
Parameter
Pin Assignment
Vcc
Unit
BiSW
Do
FC
LE
Vcc
-0.5 to 7.0
V
GND
Vp
Vcc:S; Vp:S; 10.0
V
LD
Data
Output Voltage
VOUT
-0.5 to Vee +D.5
V
fiN
Clock
Output Current
lOUT
±10
mA
Storage Temperature
TSTG
-55 to +125
°C
Supply Voltage
Note:
©
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
_,he
lbl8 dovlco oontaIno clreultryto
InpulS agak10I
damage duo to high I1aIIc voIag.. or _ric field •• _
••
Is _,hat normal pr8CIW1ions be _n to avcId appIIcatfon
=~~~1han maximum ratod
YO"- tolhls high
1991 by FUJITSU LIMITED and FullSU MJclOlllOClfonics. Inc.
3·35
MB1503
BLOCK DIAGRAM
l
1~ PS
OSC 'N
1'"--------.,
I l6-bit shift register I
1
I
Oscillator
~_
-t
l6-bit shift register!
I--
L________ . I
PSl
J:F=
S
W
JIntermi~ent l
Phase char-l
~, acteristics
changi~g cirJ
CUlt
H
I--
Charge
pump
From phase
comparator
J> fp or fR < fp, spike might not appear depending on the charge pump characteristics.
4. LD is low when the phase difference is two or more. LD is high when the phase difference is two or less
for three or more cycles (when fosel • = 12.8 MHz, tw = 625 to 1,250 ns).
Analog switch
The LE signal turns the analog swnch on or off. When the analog swnch is turned on, the charge pump output (Do) is output through
the BiSW pin. When n is turned off, the BiSW pin is in the high-impedance state.
When LE - high (when the divide ratio of the internal divider is changed): Analog switch = on
When LE - low (normal operating mode): Analog switch = off
The LPF time constant can be decreased by inserting an analog swnch between LPFI and LPF2. This decreases the lock-up time
when the PLL channel is changed.
------------,
I
3-42
MB1503
RECOMMENDED OPERATING CONDITIONS
Supply voltage
v
Vp
Input vottage
V,
Operating temperature
v
GND
-40
+85
Notes: To protect against damage by electrostatic discharge, note the following handling precautions:
-
Store and transport devices in conductive containers.
-
Use properly grounded workstations, tools, and equipment.
-
Protect ieads of the device using conductive sheet when handling PC boards on which devic/ils are mounted.
Turn off power before inserting or removing this device from a socket
3-43
MB1503
ELECTRICAL CHARACTERISTICS
0
Supply current
lee
8.0
Stand-by current
IPS
100
Operating frequency
Input sens~iv~y
High-level input voltage
Low-level input voltage
High-level input current
Low-level output vo~age
With f," = 1.1 GHz, OSC," =
12 MHz, Vee =5.0 V. The
PS pin isgrounded, remaining inputs are at Vee' and
outputs are open
1100
MHz
AC coupling. The minimum
operating frequency
is
measured with a 100·pF
capacitor connected
20
MHz
6
dBm
OSC,"
fose
f,"
V,,"
-10
OSC,"
Vose
0.5
Vp-p
Vee x 0.7
V
Except fIN and
OSC,"
Data, Clock,
LE
OSC'N
Except Do and
OSCOUT
High-impedance
Cut off current
Do
Output current
Except Do and
OSCOUT
Analog sw~ch ON resistance
3-44
IlA
f,"
FC
High·level output
With f," = 1.1 GHz, OSC," =
12 MHz, Vee = 5.0 V. Inputs
are Vee and outputs are
open
f,"
Low-level input current
Input current
10
mA
12.0
V,"
12
Vee X 0.3
V'l
V
I'N
1.0
IlA
I'l
-1.0
IlA
IFe
-60
IlA
lose
±50
IlA
VON
4.4
V
VOL
0.4
V
IOFF
1.1
IlA
ION
-1.0
mA
10l
1.0
mA
RON
25
n
Vee = 5 V
Voo = GNDto 8 V
Vee:S;Vp:S;8 V
MB1503
TEST CIRCUIT
(FOR MEASURING PRESCALER INPUT SENSITIVITY)
0.1/1
P G
~r-PL-L_r-L7fi-..r::::I:::t:::;7fi----,
50n
1-
8 7 6 5 4 3 2
1
Vee = 5 V
9 1011 1213141516
3-45
MB1503
APPLICATION EXAMPLE
I
I
I
I
LPF
J VCO I
I
I
Output
] From
controller
Ii.
PS
16
lip
15
BiSwlFC
13
14
12
LE
I
Data
Clock
11
10
9
6
7
8
lIT
MB1513
1
OS~N
-uX'tal
j; C,
Vp , Vpx
C" C2
3-46
4
3
2
0SC0ur Vp
J:.
5
Vee
6V
5V
LT J
C.
0.111
J:.
Maximum 8 V
Depend on the crystal parameters
Do !ND ILD
47K
f'N
II
1JJO P
; 47K
11~
MB1503
PACKAGE DIMENSIONS
16·LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT·16P·M06)
.089(2.2S)MAX
(MOUNTING HEIGHT)
.OO2(0.05)MIN
(STAND OFF HEIGHT)
~1
INDEX
d
050(1.27~ 1
.
TYP
"S"
I.
"A"
'016(0.40)lllr
==ro=::( ---+-
~t:~:*--'I
.350(8.89) REF _
II
II
I,
I
I
,
.008(0.20)11
.008(0.20) 1
I,
.0070.18)
MAX"
.027(0.68)
I"
-+I----t-"M""'AXv-'"-'
©1991 FUJITSU LIMITED F16015S-2C
T'" I
r-D~~;~~~-lr-D~~;~~~-l
.007(0.18)'
MAX'
.
.
027(0.68)
MAX
"
---------~~---------~Dimensions in
inches (millimeters)
3-47
MB1503
16·LEAD PLASTIC DUAL IN·LlNE PACKAGE
(CASE No.: DIP·16P·M04)
r·
.244±.010
20
A:;:=i=;:::::;:::::;:::::;:::::;:::::;:::::;:::::;:::::;:::::;:::::;:=;::::;:::;:Y
INDEX-2
©1991 FUJITSU LIMITED D1S033S-2C
3·48
(S.
.300(7.S2)
TYP
25
)
Dimensions in
inches (millimeters)
00
October 1990
Edition 4.0
FUJITSU
DATA SHEET
AlB 15041A1B1504HIAIB1504L
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 520MHz PRESCALER
The Fujitsu MBI504/MBI504H/MBI504L, utilizing BI-CMOS lechnology, is a single chip
serial input PLL frequency synthesizer with pulse·swallow function.
The MBI504 series contain a 520MHz two modulus prescaler that can select either 32133 or
64165 divide ratio; control signal generator; 16·bit shift register; 15-bit latch; programmable
reference divider (binary 14-bit programmable reference counter); I-bit switch counter;
phase comparator with phase inverse function; charge pump; crystal oscillator; 19-bit shift
register; 18-bit latch; programmable divider (binary 7·bit swallow counter and binary II-bit
programmable counter).
The MBI504 operates on a low supply voltage (3V typ) and consumes low power (30mW at
520MHz).
PLASTIC PACKAGE
DIP-16P-M04
MB1504 Product Line
DoOutput
Width
High·level
low·level
Output Current
Output Current
VpVoItage
VCOP Voltage
MBt504
8Vmax
S.SV max
Middle speed
Middle
Middle
MBt504H
10V max
10.0V max
High speed
low
High
low
MBt504l
8Vmax
8.SV max
low speed
High
low
High
Lock up time
•
High operating frequency: f'N .Ax=520MHz (V'N .,N=0.20V p•p )
•
•
On-chip prescaler
Low power supply voltage: 2.7V to 5.5V (3.0V typ)
Middle
PLASTIC PACKAGE
FPT-16P-M06
•
Low power supply consumption: 30mW (3.0V, 520MHz operation)
•
Serial input 18-bit programmable divider consisting of:
o Binary 7-bit swallow counter (Divide ratio: 0 to 127)
o Binary II·bit programmable counter (Divide ratio: 16 to 2047)
•
Serial input 15·bit programmable reference divider consisting of:
o Binary 14·bit programmable reference counter (Divide ratio: 8 to 16383)
o I-bit switch counter (SW) Sets divide ratio of prescaler
•
2types of phase detector output
o On-chip charge pump (Bipolar type)
o Output for external charge pump
•
Wide operating temperature: TA=-40·C to +85·C
PIN ASSIGNMENT
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
Symbol
Power Supply Voltage
VOH
Vp Vo,
Output Voltage
VOUT
Open-drain Output
V
V'IOOH
V
Value
Condition
-{l.5 to +7.0
Vee
MBI504H
MBI504/1504L
MB1504H
MB1504/1504L
Unit
V
V to 12.0
Vee to 10.0
V
-{l.5 to Vee +0.5
V
-{l.5 to 11.0
-{l.5 to 9.0
V
Output Current
lOUT
+10
mA
Storage Temperature
TSTG
-55 to +125
·C
NOTE:
This device contains circu~ry 10 proted the inputs against
damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken 10
avoid application of any vohage higher than maximum
rated vohages to this high impedance cirCllil
Permanent device damage may occur if the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections ot this data sheet. Exposure to
absolute maximum rating conditions tor extended periods may affect device
reliability.
Ccpyr~hl"'990 by FUJITSU LIMITED
3-49
MB1504
MB1504H
MB1504L
MB1504/MB1504H/MB1504L BLOCK DIAGRAM
vcc
0-
r------------,
I
I
..----+1___
GND0-
I
I
16-Bit Shift Register
I
16-Bit Shift Register
:JJIillilllilII[:
I
I
15-Bit Latch
I
LE
11
r-----------------~13
I
r-______________~~~-t~____~1~5-~B:it~L:at:c~h____.J I
..-----------------i12
]IDIilllill[:
I
I
I
OSC,.
1
J--t-t---!-i"
FC
LD
I
I
Programmable
Reference Divider
Binary 14-Bit
Reference Counter
r-----------------,
19-Bit Shift Register
I
I
I
t-t--I-I___
II
19-Bit Shift Register
:=rrlJI II[O]JIIIUr:
I
ll-Bit Latch
Do
I
18-Bit Latch
I
Charge
Pump
I
_
I,
:=[ilJllf[[ilJllf[[[:__'--_,
---.----.(14
I
3-50
Programmable Divider
I
I
I
I
fp
MB1504
MB1504H
MB1504L
PIN DESCRIPTIONS
Pin No.
Pin Name
1i0
Descriptions
1
2
esC,.
OSC OUT
0
Oscillator input.
Oscillator output.
A crystal is placed between OSC,. and OSCour.
3
Vp
-
Power supply input for charge pump.
4
Vee
-
Power supply voltage input.
5
Do
0
Charge pump output.
Phase characteristic can be inversed depending upon FC input.
6
GND
-
Ground.
7
LD
0
Phase comparator output.
This pin outputs high when the phase is locked. While the phase difference of f, and fp exists. the output
level goes low.
8
f,.
I
Prescaler input.
The connection with an external VCO should be an AC connection.
9
Clock
I
Clock input for 19-bit shift register and 16-bit shift register.
Each rising edge of the clock shifts one bit of data into the shift registers.
10
Data
I
Serial data of binary code input.
The last bit of the data is a control bit. The last data bit specifies which latch is activated.
When the last bit is high level and LE is high-level, data is transferred to 15-bit latch.
When the last bit is low level and LE is high level, data is transferred to 18-bitlatch.
11
LE
I
Load enable input (with internal pull up resistor).
When LE is high level (or open), data stored in the shift register is transferred to latch depending on the
control data.
12
FC
0
Phase selecting input of phase comparator (with internal pull up resistor). When Fe is low level,
charge pump and phase detector characteristics can be inversed.
13
f,
0
Monitor pin of phase comparator input.
It is the same as programmable reference divider output.
14
fp
0
Monitor pin of phase comparator input.
It is the same as programmable divider output.
15
16
I2IP
I2IR
0
0
I
Outputs for external charge pump.
Phase characteristics can be inversed depending on FC input.
I2IP pin is an N-channel open-drain output.
3-51
MB1504
MB1504H
MB1504L
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is input using Data pin. Clock pin and LE pin. The tS-bit programmable reference divider and 18-bit programmable divider are
controlled respectively.
On rising edge of the clock shifts one bit of the data into the internal shift registers.
IJI
When load enable (LE) is high level (or open). data stored in shift resisters is transferred to IS-bit latch or 18-bitlatch depending upon the control bit
level.
Control data "H" ; Data is transferred into IS-bit latch.
Control data "L"; Data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of IS-bit shift register. IS-bit latch and 14-bit reference counter. Seriaf 16-bit data format is shown below.
- - - - - - - -...... Data input
First data input
Last data input
14---- Divide ratio of programmable reference counter setting bits ----to!
@ 14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide
ratio
R
S
S
S
S
S
S
S
S
S
S
S
S
S
S
14
13
12
11
10
9
8
7
6
S
4
3
2
1
8
0
0
a
a
0
0
0
0
0
0
1
0
0
0
9
a
0
0
0
0
0
0
0
a
0
1
0
0
1
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
. . . . . . . . . . . . . . .
Divide ratio less than 8 is prohibited.
Divide ratio R: 8 to 16383
SW: Divid~W~~HC!.~ P3~SCafer setting bit.
SW="L": 64
S, to S,.: Divide ratio of programmable reference counter setting bits (8 to 16383)
C: Control bit (Control bit is set to high.)
3-52
MB1504
MB1504H
MB1504L
FUNCTIONAL DESCRIPTIONS
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bitlatch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown below.
- - - - - - - - - -... Data input
@) 7-BIT SWALLOW COUNTER DIVIDE RATIO
@)ll-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide
ratio
A
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
6
5
4
3
2
1
Divide
ratio
N
S
7
18
17
16
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
16
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
17
0
0
0
0
0
0
1
0
0
0
1
127
1
1
1
1
1
1
1
2047
1
1
1
1
1
1
1
1
1
1
1
. ....... . ...........
Divide ratio A : 0 to 127
Divide ratio less than 16 is prohibited.
Divide ratio N : 16 to 2047
S. to St.:
Divide ratio of programmable counter setting bits (16 to 2047)
S, to S7 :
Divide ratio of swallow counter setting bits (0 to 127)
C: Control bit (Control bit is set to low.)
Dara is input from MSB data.
3-53
MB1504
MB1504H
MB1504L
SERIAL DATA INPUT TIMING
Data
518=M5B
517
'(5W)
(514)
510
(SS)
59
51 =L5B
($7)
(51)
X
C: Control bit
(C: Control bit)
Clock
LE
On the rising edge of the clock shifts one bit of the data into the shift registers.
Parenthsis data IS used for setting the divide ratio of the programmable reference divider.
PHASE CHARACTERISTICS
VCO CHARACTERISTICS
FC pin (pin 12) is provided to inverse the phase comparator characteristics.
The characteristics of internal charge pump output (Do), phase detector
outputs (..R, ..P) can be inversed depending upon FC input data. Outputs are
shown below.
FC=H (or open)
Nole:
FC=L
Do
..R
.. P
Do
lOR
lOP
fr>fp
H
L
L
L
H
Z
f,
:;
~ 7.0
I
MB15~
I
2.0
0
I
MB1504
MBl504H
>
"
\
15
IOL
~
\
N'"
vs.
Cl
g
MBl504L
15
>
5
MB1504H
S-
a
a;
~
1.0
~
~
.2>
~
--'
.c:
:r
6.0
o
-1
-2
-3
-4
High-level Output Current 10H (rnA)
-5
0.0
o
10
Low-level Output Current 10 , (rnA)
20
3-57
MB1504
MB1504H
MB1504L
Do PIN OUTPUT WAVEFORM AT LOCK CONDITION
Output Wavefonn
(
1V/div
lL.___".
l00nsldiv
MBl504
II
II
'r
MBl504H
v
MBl504L
IT
-.~J
3-58
J
MB1504
MB1504H
MB1504L
PHASE CHARACTERISTICS (M VS. Do OUTPUT ENERGY)
150
~
100
l ~~
...
50
~
I
C
!!:!.
>-
~
0
~
100
80
60
40
c
w
v;
~
~
"
~.
~
V~40
20
~~ V
60
80
-50
-100
I--
~--
MB1504HI
- - MB1504
---MBI504L!
-150
/
V
,
,,- "
~.
/
~
"
.-t-
TimeAf (ns)
v
DO~
1
Oscilloscope
1
;:, -,,Vcc=Vp=3.0V
]
[ f'Nsfosc=12MHz
f,=fp=46.9kHz
3-59
MB1504
MB1504H
MB1504l
INPUT SENSITIVITY
Input Sensitivity vs. Input Frequency (Supply Voltage Dependence)
10
0
J
5a.
~
Vee=2.7V-4.0V
...... ......
-10
c:
c1l
Vee 4.0-S.SV
I.
>
·f
:~
~ ~\
Guaranteed
Operating Area
E
m
:!l.
-20
£
-30
_-
~'
E:Ar-
....... V
~'1.
f1.V
V
Vee=2.7V
....... ...-~ V K·VCC=4.0V
..I .........
VcrS.5V
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
Input Frequency fin (GHz)
Input Sensitivity vs. Input Frequency (Temperature Dependence)
10
E
m
:!l.
J
0
?;o
-10
Vcc-4.O-S.SV
I
>
's:
-20
a.
£
-30
-
\
~
0.3
;:-
0.4
I
.'" <~ ~
)
/
........ T.=+8SD C
~
0.5
0.6
0.7
O.B
0.9
Input Frequency fin (GHz)
3-60
I
~ TA =2S DC
I ;
T.=-40 DC
c:
5
I
~
"'
Vcc=2.7V-4.0V
:~
c1l
~
Guaranteed
Operating Area
1.0
1.1
1.2
MB1504
MB1504H
MB1504L
INPUT IMPEDANCE
III
TEST CIRCUIT
Do Pin Output Current (loH, IOL) Measurement
Vee
V.
Do-
10l
MBl504
-loH
3-61
MB1504
MB1504H
MB1504L
Lock up Time Measurement
Oscilloscope (10Mn, 10pF)
LPFCircuit
Vcc=3V. Vp =8V
[ Ivco=Low unlock condition _
Ivco=High unlock condition _
Step to Lock condition (533MHz)
Step to Lock condition (518MHz)
1
Phase Characteristics Measurement
OSCin
Oscilloscope
(10Mn. 10pF)
fin
fp
Vcc=3V. Vp=3V
[ Af=fr-fp
Energy (En)=1f2t
3-62
MB1504
MB1504H
MB1504L
TYPICAL APPLICATION EXAMPLE
r----..,
OUTPUT
Charge Pump Selection
(Internal or external)
12kn
FROM
CONTROLLER
12kO
~}
FC
16
15
13
14
12
LE
11
47kn
Data
10
MB1504
2345678
OSC OUT
OSC'N
V.
Vee
Do
GND
LD
1000pF ~_ _
Vcc"'(i-3V)
X'taI
6V
100kn
3V
33kO
LOCKDET,
v., V.x
C"C.
LE,FC
"p
8Vmax.
Depends on aystal oscillator
With internal pull up resistor
Open drain output
3-63
MB1504
MB1504H
MB1504L
PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-16P-M04)
_==~:=:r15' MAX
II
- - --u
-n
:!l~0!.L27) I
MAX
--t
I
© 1988 FUJITSU LIMITED D16D33S-2C
3-64
--1~O-;-;;--:-;:-,,"
172(4 36) MAX
118(3 00) MIN
.020(0.51) MIN
Dimensions in
inches (millimeters)
MB1504
MB1504H
MB1504L
PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT-16P-M06)
089(2 251
___..400
MA~__
_
1
1
.307' .016
1(7 80t 040)
.209
t
.012
I
(5.30 • 0.30)
1!m=iF;;==n==T~l=;;lI_ I _
050(127)
TYP
Jl.018 •.
004=-,-,=-=-=~I
(0.4~(j)1 ¢005(0.13)
M
"A"
.004(0.10)
.350(8.89) REF
---.j
MAX
( 027(068)
L _______~A_X____
c 1990
_
FUJITSU LIMITED F16015S-2C
3-65
MB1504
MB1504H
MB1504L
lID
3-66
cO
March 1990
Edition 1.0
FUJITSU
DATA SHEET
MB1505
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
~~~~
I
LOW POWER SERIAL INPUT PLL
SYNTHESIZER WITH 600MHz PRESCALER
~~~
-
<.)
z
W
:::J
@
ex:
u..
I-
:::J
c..
FC=H or open
Note:
I-
FC=L
:::J
Do
0R
0P
foul
Do
0R
0P
f~1
f,>f.
H
L
L
(f,)
L
H
Z
(f.)
I,d.
L
H
Z
(f,)
H
L
L
(f.)
f,=f.
Z
L
Z
(f,)
z
L
z
(f.)
a
8>
Z=(High impedance)
Depending upon VCO characteristics, FC pin should be set accordingly:
When VCO characteristics are like
FC should be set High or open circuit;
When VCO characteristics are like
FC should be set Low.
1.
I
I
I
Z
f,=I.
I,d.
I,d.
I,d.
NOTES: Phase difference detection range: -21t to +21t
Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When 1,>1. or I,d., spike might not appear depending upon charge pump characteristics.
ANALOG SWITCH
ON/OFF 01 analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (00 ) to be
connected to BISW pin. When the analog switch is OFF, BISW pin is set to high-impedance state.
LE=H (Changing the divide ratio 01 internal prescaler) : Analog switch=ON
LE=L (Normal operating mode)
: Analog switch=OFF
LPF time constant is decreased in order to insert a analog switch between LPFI and LPF2 when channel of PLL is changing.
Thus, lock up time is decreased, that is, fast lock up time is achieved
.................................... Do
~
I
CHARGE PUMP
III--~A-.ft'r--fl
~
I
LPF-1
II
I~------~
LPF-2
I
I
Vco
I
L. .. _ _ _ _ _ _ _ _ _ . . . . . . .,
----I
,
ANALOG SW
I
(CONTROL SIGNAL LE)
I
(j)BISW
i
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - .. .1
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Unit
Symbol
Min
Typ
Max
Vee
4.5
5.0
5.5
V
Vp
Vee
V.
8.0
V
Input Voltage
V,
GNO
Vee
V
Operating Temperature
T.
-40
85
·C
Power Supply Voltage
3-73
MB1505
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Power Supply Current
Operating Frequency
low-level Input Voltage
High-level Input Current
low-level Input Current
Value
Min
Typ
Max
mA
6.0
Note 1
I"
fin
Note 2
OSC,.
lose
1;0
VI"
-4
OSC,.
Vesc
0.5
Vpp
Except Ii,
and OSC,.
V'H
VccxO.7
V
Data
Clock
I'H
1.0
!LA
I'L
-1.0
!LA
OSC'N
lose
±50
!LA
lE,FC
ILE
-60
!LA
10
600
MHz
20
MHz
6
dBm
12
VccXO.3
V'L
Input Current
High-level Output Current
low-level Output Current
N-channel Open Drain
Cutoff Current
Output Current
Analog Switch On Resistor
Except Do
and OSCOUT
Do,0P
Except Do
and OSCOUT
VOH
Vcc=5V
0.4
VOL
10FF
V
V
4.4
Vp=Vcc to BV
VOOP=GND to BV
1.1
V
!LA
10H
-1.0
mA
10L
1.0
mA
RON
25
NOTE 1: f'n=600MHz, OSC'Nz12MHz, Vcc=5V. Inputs are grounded and outputs are open.
NOTE 2: AC coupling. Minimum operating frequency is measured when a capacitor 1000pF is connected.
3-74
Unit
Icc
Input Sensitivity
High-level Input Voltage
Condition
n
MB1505
TEST CIRCUIT
V._6V
OM
1000.F
PoG~
50°1
I
5
4
3
2
MB1505
L..--------oOscilioscope
3-75
MB1505
TYPICAL APPLICATION EXAMPLE
r------, OUTPUT
Charge Pump
Selection
(Internal or
external)
12k
FROM
CONTROLLER
12k
0R
16
0P
15
LE
14
13
12
47k
Data
11
10
6
7
47k
MB1505
2
OSC,.
4
3
OSCOUT Vp
5
Vee
Do
GND
8
LD
X'tal
6V
5V
LOCK DET
Vp, Vpx : 8V max.
C" C2 : Depends on crystal oscillator
LE,FC : With internal pull up resistor
0P
: Open drain output
3-76
MB1505
PACKAGE DIMENSIONS
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. ; DIP-16P-M04)
r
INDEX· 1
.30017.62)
TYP
,
INDEX-2
10.25 ± 0.05)
1
.17214.36) MAX
.118(300) MIN
I
02010.51) MIN
Dimensions in
(C) 1988 FUJITSU LlM1TED D16033S-2C
inches (millimeters)
3-71
MB1505
16-LEAD PLASTIC FLAT PACKAGE
(Case No.: FPT-16P-M02)
_400+ 010110 IS+ 025 1
-OOB
-020l
•
~I-!
·30J±.016
1(7.BO±0.401
INDEX
209±.01·2
(5.30t 0.301
Cf
il;;=;Fn==n=;;r=;;=;;==;#.
.OS011271
TYP
..!
I
JLO..!ll.!c!l~I".00SI0.131 iIJ
10.45±0.101
r,
.OB912.251 MAX
;!SEATED HeIGHTI
I~.
~~:t~g56~~~
~
I.
!
26B+'~.'6.
0 .40 )
-.OOB 16.BO+
-0.20
i
I
----+ 020± .OOB
Ii ---t(0.50l 020)
-lI- .006 + .002(0 15 + 0.05 1
-.001
-0.02
i -O;tall; of :-:;'~;rt'--:
"A"
,'"
o
.00410.101
.008(0.20):
-=1 :
- ""'1 i
.020(0.501,
.007(0. I BI '
MAX
.027(06BI '
MAl(
DImensions
(C) 1988 FUJITSU LIMITED F16005HC
3-78
In
inches (millimeters)
cO
March 1991
Edition 3.0
FUJITSU
DATA SHEET
MB1507
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 2.0GHz PRESCALER
ID
The Fujitsu MB 1507 is a single chip serial inpul PLL frequency synthesizer designed for BS
tuner and cellular telephone applications.
It contains a 2.0 GHz dual modulus prescaler which enables pulse swallow function. and an
analog switch to speed up lock up time.
It operates supply voltage of 5.0V typo and dissipates 18mA typo of current realized through
the use of Fujitsu's unique U·ESBIC Bi-CMOS technology.
•
High operating frequency: fiN MAX=2.0GHz (V'N MlN=-4dBm)
•
Pulse swallow function: 1281129 or 256/257
•
Low supply current: lee=18mA typo
•
Serial input 19-bit programmable divider consisting of:
o Binary 8-bit swallow counter: 0 to 255
o Binary II-bit programmable counter: 16 to 2047
•
Serial input 15-bit programmable reference divider consisting of:
o Binary 14-bit programmable reference counter: 8 to 16383
o l-bit switch counter (SW) sets divide ration of prescaler
•
On-chip analog switch achieves fast lock up time
PLASTIC PACKAGE
FPT·16p·M06
• Two types of phase detector output
o
o
PIN ASSIGNMENT
On·chip charge pump (Bipolar type)
Output for external charge pump
•
Wide operating temperature: -40'0 to +85DC
•
16-pin Plastic Flat Package (Suffix: -PF)
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
Power Supply Voltage
Symbol
Value
Unit
Vee
-0.5 to +7.0
V
Vp
Vee to 10.0
V
V
Output Voltage
VOIIT
-0.5 to Vee +0.5
Open-drain Voltage
Voop
-0.5 to 8.0
V
Output Current
lOUT
+10
Storage Temperature
TSTG
-55 to +125
mA
DC
NOTE:
Permanent deVice damage may occur If the above Absolute Maximum
Ratln\ls are exceeded. Functional operation should be restricted to the
condilJons as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability .
This device contains circuHry to protect the inputs against
damage due to high static voltages or electric fields. However.lt Is advised that normal precautions be taken 10
avoid application of any voltage higher than maximum
rated vohages to this high irf1)edance circuit
Copyright.. 1991 FUJITSU LIMITED
3-79
MB1507
MB1507 BLOCK DIAGRAM
r------------,
I
I
I
16-BIT SHIFT REGISTER
16-BIT SHIFT REGISTER
I
I
I
~ImnnH:u===~
I
15-BIT LATCH
I
~~----------~I
I
15-BIT LATCH
I
~~----------~I
rLlmIOlun===-'
II
I
PROGRAMMABLE REFERENCE
DIVIDER
BINARY 14-BIT
I REFERENCE COUNTER
I L..-________--IU
L _ _ _ _ _ _ _ _ _ _ _ _ -'
Do
5~--------_4+_----------------------~+-~----------~
t--------------------------4----------------~--~11
fiN
3-80
8
PRESCALERt--4------'-'-T-'-""-'=:..:::.::=...:"-'-'::,
LE
MB1507
PIN DESCRIPTION
PinNa.
Pin Name
110
Description
OSC"
I
OSCOUT
0
Oscillator input.
Oscillator output.
A crystal is placed between OSC,. and OSCOUT•
3
Vp
-
Power supply input for charge pump and analog switch.
4
Vee
-
I
2
Power supply voltage input.
Charge pump output
5
Do
0
6
GND
-
Ground.
7
LD
0
Phase comparator output.
Normally the output level is high level. While the phase difference of I, and fp exists, the output becomes low level.
8
f,.
I
Prescaler input.
The connection with VCO should be AC connection.
9
Clock
I
Clock input for 20-bit shift register and IS-bit shift register.
Each rising edge of the clock shifts one bit of data into shift registers
10
Data
I
Binary serial data input.
The last bit of the data is a control bit which specified destination of shift registers. When this bit is
high level and LE is high level, the data stored in shift register is transferred to 15-bit latch. When
this bit is low level and LE is high level, the data is transferred to 19-bit latch.
II
LE
I
12
FC
I
Phase select input of phase comparator (with pull up resistor).
When FC is low level. the characteristics of charge pump. phase comparator are reversed.
FC pin input signal controls f~1 pin (test pin) output level. f, or fp.
13
BISW
0
Analog switch output
Usually BISW pin is set at high-impedance state. When internal analog switch in ON (LE pin is set
at high level). this pin outputs internal charge pump output.
fOOT
0
Monitor pin 01 phase comparator input.
I... pin outputs programmable reference divider output (f,) or programmable divider output (fp) depending upon FC pin input level.
FC=H: It is the same as f, output level.
FC=L: It is the same as Ip output level.
15
"p
16
"R
0
0
14
The characteristics of charge pump are reversed depending upon FC input.
Load enable input (with pull up resistor).
When LE is high or open. the data stored in shift register is transferred into latch depending upon
the control bit. At the time. internal charge pump output to be connected to BISW pin because internal analog switch becomes ON state.
Outputs lor external charge pump.
The characteristics are reversed according to FC input.
"p pin is N-channel open drain output.
3-81
MB1507
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achiewd by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable reference divider
and 19-bit programmable divider, respectiwly.
Binary serial data is input to Data pin.
Each rising edge of the clock shifts one bit of serial data into the internal shill registars and when load enable pin is high level or
open, stored data is transferred into latch depending upon the control bit
Control data "H" data is transferred into 15-bit latch.
Control data "L" data is transferred into HI-bit latch.
THE DIVIDE RATIO SETTING
fvco=[(MxN)+A]xfosc+R
'vco: Output frequency 01 external voltage controlled oscillator (VCO)
M:
Preset modulus 01 external dual modulus prescaler (128 or 256)
N:
Preset divide ratio 01 binary ll-bit programmable counter (16 to 2047)
A:
Preset divide ratio 01 binary 8-bit swallow counter (OsAS255, Afp
VCO INPUT VOLTAGE Note:
Z=(High impedance)
Depending upon VCO polarity, FC pin should be set accordingly:
FC should be set High or open circuit;
When VCO polarity are like
When VCO polarity are like
FC should be set Low.
CD '
®'
3-84
MB1507
PHASE DETECTOR OUTPUT WAVEFORM (FC=High)
f
LOU
Do ••••
~ •••••••• ~ •••
Z
f
f
u
u
f
u
L
L
... -u-..... L...t ... L..r ... Lfr1. or I,-d•• spike might not appear depending upon charge pump characteristics.
ANALOG SWITCH
ON/OFF 01 analog switch is controlled by LE input signal. When the analog switch is ON. internal charge pump output (Do) is connected to BISW pin.
When the analog switch is OFF, BI-SW pin is set to high-impedance state.
LE
Analog Switch
H(Changing the divide ratio 01 internal prescaler)
ON
L(Normal operating mode)
OFF
When an analog switch is inserted between LPI and LP2, laster lock up time is achieved to reduce LPF time constant during PLL channel switching.
------------------~Do
I
CHARGE PUMP
I
~
't'
I_ _LP_F_-_
1
1 __I
I
.
I
LPF-2
I
I
1
Vco
I
1. ... __ .. _ ...... _ ............... .,
I- ,I_ANALOG
_....,._SW
_...I1 '"
"" BISW
(CONTROL SIGNAL LE)
I
;
-... -... ----------------------------~
3-85
MB1507
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
Typ
Max
Vex;
4.5
5.0
5.5
V
Vp
Vee
-
8.0
V
Input Voltage
V,
GND
-
Vee
V
Operating TemparalUre
T.
--40
-
85
DC
Power Supply Voltage
HANDLING PRECAUTIONS
• This dellice should be lransportad and stored in anti-static containers.
• This is a statio-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are prope~y grounded. Cover
workbenches with grounded conductive mats.
• Always IUm the power supply off before inserting or remolling the device from its socket.
• Protect leads with a conductive sheet when handling or lransporting PC boards with devices.
3-86
MB1507
ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Power Supply Current
Oparating Frequency
""
OSC,.
I..
Condition
Value
Min
Typ
Max
Unit
Icc
Note 1
-
lB.O
25.0
mA
I..
Note 2
10
-
2000
MHz
lose
-
-
12
20
MHz
Vin
son
-4
-
6
dBm
V"""
-
0.5
-
V••
V,"
VccXO.7
-
V
V'L
-
-
I,"
I'L
110
Input Sensitivity
OSCIH
High-level Input Voltage
Low-level Input Voltage
High-level Input Current
Low-level Input Current
Except I,.
anclose,.
Data
Clock
OSC,.
lose
LE,FC
I...
Input Current
High-level Output Current
Low-level Output Current
High Impedence
CutoH Current
Output Current
Analog Switch On Resistance
Except Do
anclOSCour
Do,"P
Except Do
and OSCour
VO"
-
-
-
-
1.0
-
~
-
-
-1.0
-
~
-
+so
-
~
-
-60
-
~
4.4
-
-
V
-
-
0.4
V
-
-
1.1
~
VccxO.3
V
Vcc=5V
VOL
IOFF
V.=Vcc toBV
Voo.=GND to BV
IOH
-
-1.0
-
-
mA
IOL
-
1.0
-
-
mA
Ro.
-
-
25
-
n
NOTE 1: 1..=2.OGHz, losc=12MHz X'tal Vcc=5V. Inputs are grounded and outputs are open.
NOTE 2: AC coupling. Minimum operating lrequency is measured with a capacitor l000.F.
3-87
MB1507
TEST CIRCUIT Prescaler In ut Sensitivit
Vp=6V
""I
l000,.F
'~~
son
8
7
6
S
7fT
4
3
7fT
2
MBl507
' - - - - - - - - - 0 Oscilloscope
3-88
MB1507
TYPICAL APPLICATION EXAMPLE
V px(6V)
OUTPUT
Charge Pump
Selection
(Internal or
external)
12k
12k
16
}
"p
"R
15
IIJ
FROM
CONTROLLER
FC
14
13
12
LE
11
47k
Data
10
MBl507
234
asC,.
OSC OUT
Vp
5
Vee
X'taI
6
Do
7
GND
B
LD
1000p
6V
Vcc(5V)
5V
LOCK
DETECTOR
10k
Vp, V.x
C"C,
LE,FC
"p
BVmax.
Depends on crystal oscillator
With pull up resistor
Open drain output
3-89
MB1507
PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(Oase No. : FPT-16P-M06)
.089(2.25) MAX
IMOUNTING HEIGHT)
.05011.27)
TYP
11·018±.004
10.45±0.10)1$1;>.00510.13) 1/!1)
··A··
I
,-------------1
; Details of "A" part I
r--------- ----,
1r
Details of "B" part
.OO6(0.15)
,,
.008(0.20) :
© 1990 FUJITSU LIMITED F16DI5S-2C
3-90
.008(0.20) I
.OO:~~18)
I
:
~-----~~!~~~~--:
I
~!
I
, .00410.10)
!
L ___
~
.007(0.18) :
MAX
I
.02710.68) :
MAX___ Ji
______
Dimensions in
inches (millimeters)
cO
April 1991
Edition 2.0
FUJITSU
DATA SHEET
MB150B
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
ON CHIP 2.5GHz PRESCALER
III
The Fujitsu MBI508 on chip 2.5 GHz dual modulus prescaler is a serial input PLL (Phase
Locked Loop) frequency synthesizer with pulse swallow function. It is well suited for BS tuner,
CATV system, and TV tuner applications.
It operates supply voltage of 5.0V typo and dissipates 16mA typo of current realized through the
use of Fujitsu's unique U-ESBIC Bi-CMOS technology.
PLASTIC PACKAGE
FPT-20P-M01
= 4.5 to 5.5V
•
Power supply voltage: Vee
•
High operating frequency: ft,
•
2.5GHz dual modulus prescaler: P = 256/272, 512/528
•
Low power supply current: Icc = 16mA typo
•
Programmable reference divider consisting of:
Binary 2-bit programmable reference counter (R = 256, 512, 1024, 2048)
•
Programmable divider consisting of:
Binary 5-bit swallow counter (A = 0 to 31)
Binary 12-bit programmable counter (N = 32 to 4095)
= 2.5GHz (V. =-4dBm)
PIN ASSIGNMENT
•
•
FC
20
LD
LE
2
19
fOUT
Data
3
18
VCC2
Clock
4
17
fi,
Wide operating temperature: T. = -40 to +85"C
Plastic 2O-pin flat package (Suffix: -P F)
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Power Supply Voltage
Vee
-0.5 to 7.0
V
Output Voltage
Vo
0.5 to Vee +0.5
V
Output Current
10
±10
rnA
TSTO
-55 to +125
Vcc.
5
OSC,.
6
TOP 16
VIEW
15
OSCOUT
7
14
BCl
GND
8
13
BC2
D••
9
12
BC3
10
11
BC4
0 ..
Storage Temperature
NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
GND2
;:
This device oontains ci'cuitry to prated the inputs against
damage dUBIO high slatlcvt*ages orelactrlc fields. However.
l is advised that I'IOfmal precautions be taken to avoid
appIica1ion 01 any voltage higher than maxifftlm rated
voltages to this hlgn ilJ1)8dance circuit.
Copyr;gh' ©1991 by FUJITSU LIMITED
3-91
MB1508
MB1508 BLOCK DIAGRAM
LD
toUT
VCC2
L
FC
3-92
Data
t.
17
Clock
GND2
~
Veel
BC1
BC2
BC3
BC4
9
10
DOt
002
15
OSC",
OSC""
r
GND1
MB1508
--
PIN DESCRIPTIONS
.!~~l~\E
II
i> .•..•.••••
/>
Phase select input pin 01 the phase detector. This pin involves an internal pull up resistor.
When Ihis pin is low, characteristics 01 Ihe charge pump and phase detector can be reversed. Thi.
input also selects lOUT pin output level, eilher Ir or fp. See Functional Description section,
Phase Detector Characteristics.
1
FC
I
2
LE
I
Load enable input pin. This pin involves a schmitt trigger circuit.
When this pin is high. Ihe data stored in Ihe shift register is transferred into Ihe latch.
3
Data
I
Serial data of binary code input pin. This pin involves a schmitt trigger circuit.
4
Clock
I
Clock input pin of the 24-bit shift register. This pin involves a schmitt trigger circuit.
Each riSing edge of the clock shifts one bit of data into lila shift regisier.
5
Vcc,
-
6
7
OSC,.
OSCOUT
I
0
S
GNDl
-
PLL ground pin.
9
10
Do,
0
0
Charge pump output pins.
Phase characteristics can be reversed depending upon FC pin input level.
11
12
13
14
BC4
BC3
BC2
BCl
0
0
0
Band switching output pins. (Open-coliector output)
Output is controlled by a band bit data, individually.
BCX-bit=H : BCX output transistor is ON.
BCX-bit=L: BCX output transistor is OFF.
(X=l to 4)
15
Tn
I
Complementary input pin at f,". Please connect to GND through a capacitor.
16
GND2
-
Prescaler ground pin.
17
fin
I
Prescaler input pin,
This signal is AC coupled.
18
Vcc,
-
Prescaler power supply voltage input pin.
19
foUT
0
Monitor pin of the phase detector input.
fouT pin outputs either at the programmable reference divider output frequency fr or programmable
divider output frequency fp depending upon the FC pin input level.
0.,.
PLL power supply voltage input pin.
Oscillator input pin.
Oscillator output pin.
A crystal is connected between OSC,. pin and OSCOUT pin.
FC pin
20
LD
0
fout output signal
H
fr
L
fp
Phase detector output pin.
Normally this pin outputs high. While Ihe phase difference between fr and fp exists, this pin outputs
low.
3-93
MB1508
FUNCTIONAL DESCRIPTIONS
DIVIDE RATIO SETTING
Divide ratio can be set using the following equation:
fvco ~ {(P x N)
+ (16 x
An x fose + R
fvco: Output frequency of an external voltage controlled oscillator (VCO)
P:
Preset divide ratio of an internal dual modulus prescaler (256 or 512)
N:
Preset divide ratio of binary 12-bit programmable counter (32 to 4095)
A:
Preset divide ratio of binary 5-bit swallow counter (0 to 31)
fose: Reference oscillator frequency
R:
Preset divide ratio of reference counter (256,512,1024,2048)
SERIAL DATA INPUT
Each rising edge of the clock shifts one bit of data into the shift register.
When the loao enable is high, the data stored in the shift register is-transferred to the latch.
The data format of 24 bits is shown below.
r
A
1
I-
- - - . . . Data Input Flow
MSB,
LSB
A
2
A
3
A
4
N
1
A
5
Divide ratio of swallow
counter setting bit
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
10
N
11
N
12
S
W
.. ,
"I-
R
R
1
2
B
C
4
B
C
2
B
C
3
J
I
I
Divide ratio of programmable
counter setting bit
Band switch
setting bit
Divide ratio of prescaler setting bit
Divide ratio of reference counter settin g bit
5-bit swallow counter divide ratio (A 1 to A5)
Divide ratio
A
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
1
0
0
0
0
1
2
0
0
0
1
0
1
1
1
N
10
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
0
:
:
:
31
1
1
12-bit programmable counter divide ralio (NI to N12)
3-94
Divide ratio
N
12
N
11
32
0
0
0
0
0
0
1
0
0
0
0
33
0
0
0
0
0
0
1
0
0
0
0
1
34
0
0
0
0
0
0
1
0
0
0
1
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
1
:
:
:
4095
1
I
B
C
1
I
MB1508
FUNCTIONAL DESCRIPTIONS
Reference counter divide ratio (Rl to R2)
Divide ratio
R
R
2
R
1
256
0
0
512
0
1
1024
1
0
2048
1
1
Prescaler divide ratio (SW)
When divide ratio of prescaler setting bit is high. divide ratio 01 2561272 is selected.
When divide ratio of prescaler setting bit is low. divide ratio 01 5121528 is selected.
Band Switch Setting (BCl to BC4)
When band switch setting bit is high. output is ON.
When band switch setting bit is low. output is OFF.
SERIAL DATA INPUT TIMING
t •• 12. b. 14. Is ~ If'S
Data
Clock
BCl
(MSB)
---~W:N12 - - - 3 2 At
(LSB)
.. :
.
...._--------
-
--
---fuJl..JUl..fULrL
I
I
I
I
I
I
I
LE
------~------.~.-----
I
I
!..,12 ....
I
I
I
I
""""';---;--,
b~
I
I
I
I
I
ts ----.:..-
Note: Each rising edge of the clock shifts one bit of data into the shift register.
When LE is high, the data stored in the shift register is transferred into the latch.
3-95
MB1508
PHASE DETECTOR CHARACTERISTICS
FC pin selects the phase 01 the phase detector. Phase characteristics (charge pump output) can be reversed depending upon the FC pin.
input level. Monitor pin (lout) output level is selected by the FC pin input level as well.
FC = L
FC = H (or open)
001,0..
Ir> fp
H
Ir = fp
Z
Ir< fp
L
001,0..
lout
lout
L
Outputs programmable
reference divider output
lrequency Ir.
Outputs programmable
divider output
frequency Ip.
Z
H
Note:
Z:
VCO POLARITY
High-impedance
Depending upon the VCO polarity, FC pin should be set accordingly.
When VCO polarity is like 1,
FC should be set high or open.
When VCO polarity is like 2,
FC should be set low .
VCOOutput
Frequency
VCO Input Voltage -
PHASE DETECTOR WAVEFORM
Ir~
L
Ip
u u u L
(FC =H)
001,0..
Jf-------_Ir---- -J:-----Ll----LJ --L -J-------_Ir---- -11-----Jt----.J"t---LH
f
I
I
Z- -
I
(FC =L)
001. D02
Z- -
I
fr > fp
Note:
fr=lp
Ir.{?
Vee
-0.5 to 7.0
Vp
Vee to 10.0
Output Voltage
VOUT
-0.5 to Vee +0.5
V
Output Current
lOUT
±10
mA
Storage Temperature
TSTG
--55 to +125
°C
V
Power Supply Voltage
NOTE:
GND
Permanent device damage may occur ilthe above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections 01 this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
3
TOP
VIEW
Ir
6
15
Ip
LD,
7
14
L02
Vp,
13
VP2
Do,
12
002
11
BS2
BS,
10
This device contains circuitry to protect the Inputs against
damage due to high static vohages or electric fields. However,
it is advised that normal precautions be taken to avold
application of any voltage higher than maximum rated
voltages to this high impedance circuit.
Copyright ©t99t by FUJITSU LIMITED
3-101
MB1509
MB1509 BLOCK DIAGRAM
r--
J
(8
I
I
I
I
I
r-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Charge
Pump
r----...l
i~
- +__________~1~
Charge
Pump
lp
I
I
I
I
I
I
I
I
Phase
Detector
~~~it~r
~
r----.J
""'""___
)
-1
6e~:~~r
--+
I
selector
iT
Tr
I
"rr-"
t-=~~I-tt==I=====
--
ITRANSMIT
I
SECTION
rr--
r--t:RECEPTION
SECTION
.
Binary
11·bit
Programmable
-
Counter
-'--
Reference
Counter
(512.
~O-b;t
latch
Binary
11·bil
Program-
mable
Counter
20-bit
I->
latch
1024)
r-
Binary
7-bit
Swallow
Counter
...
r-'--
5~
Binary
7-bi!
Swallow
Counter
...
Latch
Selec-
tor
'--I
r--
L.e.
f4---
*_____
Prescaler
~
~
.J
•
Prescaler~
-
23-bit shift
register
....
T
Crystal
Oscillator
I
I
IL ____
3-102
.
-r--
CNT
11
Circuit
Schmitt
Circuit
18
19
Schmitt
I
I
L----I------.J
17
Schmitt
Circuit
T
MB1509
BLOCK DESCRIPTIONS
TRANSMIT/RECEPTION BLOCK
• 20-bn latch
• Programmable divider consisting of:
Binary 7-bn swallow counter (Divide ratio: 0 to 127)
Binary l1-bn programmable counter (Divide ratio: 16 to 2047)
• Phase detector with phase polarity change function
• 400MHz dual modulus prescaler (Divide ratio: 32/33, 64/65)
• Charge pump
COMMON BLOCK
• 23-bn shift register
• Programmable divider consisting of:
Reference counter (Divide ratio: 512,1024)
(Divide frequency = 25kHz, 12.5kHz (Crystal oscillator frequency = 12.8MHz)
• Crystal oscillator
• fp monnor output selector
• Latch selector
• Schmnt circuits
• Analog switches
3-103
MB1509
PIN DESCRIPTIONS
-
Ground.
I
0
Oscillator input pin.
Oscillator output pin.
A crystal is connected between OSC'N pin and OSCOUT pin.
1
GND
3
2
OSC'N
OSCOUT
4
fin1
I
Prescaler input pin of transmit section.
The connection with VCO should be AC connection.
5
Vee1
-
Power supply voltage input pin of transmit section.
When power is OFF, latched data of transmit section is cancelled.
6
fr
0
Monitor pin for programmable reference divider output.
7
LD1
0
Lock detect signal output pin of transmit section.
Condition
H
Unlock
L
8
VPI
-
Power supply voltage input for charge pump and analog switch of transmit section.
9
DOl
0
Charge pump output pin of transmit section.
Phase characteristics of the phase detector can be reversed depending upon FC-bit setting.
10
BS1
0
Analog switch output pin of transmit section.
Usually this pin is high-impedance state. During SW is ON (LE
nected to this pin.
=high), charge
pump output is con-
Analog switch output pin of reception section.
Usually this pin is high-impedance state. During SW is ON (LE
nected to this pin.
=high), charge
pump output is con-
11
BS2
0
12
002
0
Charge pump output pin of reception section.
Phase characteristics of the phase detector can be reversed depending upon FC-bit setting.
13
VP2
-
Power supply voltage input for charge pump and analog switch of reception section.
14
LD2
0
Lock detect signal output pin of reception section.
Condition
15
3-104
LD pin output level
Lock
fp
0
LD pin output level
Lock
H
Unlock
L
Monitor pin for programmable divider output.
This pin outputs divided frequency of transmit section or reception section depending upon FP bit
setting.
FP bit
Output
H
Transmit section (fp1)
L
Reception section (fp2)
MB1509
PIN DESCRIPTIONS (Continued)
16
VCC2
17
Power supply voltage input pin for reception section, programmable reference divider, shift register,
and crystal oscillator.
When power is OFF, latched data of reception section and reference counter is cancelled.
Prescaler input pin of reception section.
The connection with VCO should be AC connection.
18
LE
Load enable input pin. This pin involves a schmitt trigger circuit.
When this pin is high, the data stored in the shift register is transferred into the latch depending on a
control data.
At this moment, charge pump output signal is output from BS pin since internal analog swith becomes ON.
19
Data
Serial data input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
The stored data in the shift register is transferred to either transmit section or reception section depending upon a control data.
20
Clock
Control bit data
The destination of data
H
Latch of transmit section
L
Latch of reception section
Clock input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
Each rising edge of the clodk shifls one bit of data into the shift register.
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
Ivco = {(M
x N) + A} x lose +
R (A < N)
fveo: Output frequency of external voltage controlled oscillator (VCO)
M:
Preset divide ratio 01 dual modulus prescaler (32 or 64)
N:
Preset divide ratio 01 binary 11-bit programmable counter (16 to 2047)
A:
Preset divide ratio 01 binary 7-bit swallow counter (O~ A ~ 127)
lose: Reference oscillator Irequency
R:
Preset divide ratio of reference counter (512 or 1024)
3-105
MB1509
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data is input using three pins: Data pin, Clock pin, and LE pin. Programmable divider 01 transmit section and programmable divider 01
reception section are controlled individually.
Serial data 01 binary data is input into Data pin.
Each rising edge 01 the clock shifts one bit of serial data into the shift register. When load enable signal is high, the data stored in the9ister is
shift register is transferred to either the latch of the transmit section or the latch 01 the reception section, dapending upon the control bit data setting.
Control data
Destination of serial data
H
Latch of transmit section
L
Latch 01 reception section
SHIFT REGISTER CONFIGURATION
Control bit
! Lr
1
2
3
C
R
F
N
E
P
T
F
Nl to NIl
Al toA7
FC
PRE
FP
REF
CNT
,59
DataFlow_
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P
F
A
A
A
A
A
A
A
N
N
N
N
N
N
N
N
N
N
N
R
C
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
4
E
: Divide ratio olthe programmable counter setting bit (16 to 2047)
: Divide ratio 01 the swallow counter setting bit (O to 127)
: Phase control bit 01 the phase detector
: Divide ratio 01 the prescaler setting bit (32/33 or 64/65)
: Output of the programmable divider control bit (Ipl or fp2)
: Divide ratio of the reference counter setting bit (512 to 1024)
: Control bit
SERIAL DATA INPUT TIMING
ot" b, b, 4, Is" 11'5
Data
NIl
=MS9v;;----R;;::;;V
___ ~-__
.::::.:.J\
~
,
Clock
C:Controlbit
-fufl--lWl. Il-fl-_____
LE
~
~'-_~
I
:
:..
12";
t
3
~
I
+-;.- :.....•
I
fL
t4 --.:
I
:
t5~
I
Each rising edge of the clock shifts one bit of data into the shift register.
3-106
•
22
23
MB1509
BINARY 11-BIT PROGRAMMABLE COUNTER DATA SETTING
N
7
N
6
N
5
N
4
N
3
N
2
N
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
Divide
Ratio
(N)
N
tl
N
10
N
N
9
8
16
0
0
0
17
0
0
0
2047
1
1
1
Nole: Divide ratio less than 16 is prohibited.
Divide ratio (N) range = 16 to 2047
BINARY 7-BIT SWALLOW COUNTER DATA SETTING
Divide
Ratio
(A)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
127
1
1
1
I
1
1
1
Note: Divide ratio (A) range = 0 to 127
PRE : DIVIDE RATIO (P) OF THE PRESCALER SETTING BIT
H = 32/33
L = 64165
REF : DIVIDE RATIO (R) OF THE REFERENCE COUNTER SETTING BIT
H = 512 (fr = 25.0 kHz)
L = 1024 (fr = 12.5 kHz)
FP
: OUTPUT OF THE PROGRAMMABLE DIVIDER SETTING BIT
H = fp pin (15 pin) outputs programmable divider output frequency (fpl) of transmit section.
L = fp pin (15 pin) outputs programmable divider output frequency (fp2) of reception section.
FC
: PHASE CONTROL BIT OF THE PHASE DETECTOR
Output of charge pump is selected by FC pin.
FC= H
FC = L
fr >fp
H
L
fr=fp
Z
Z
fr < fp
L
H
VCO Polarity
(j)
®
Nole: Z = High-impedance
Depending upon the
veo polarity. Fe bit should be set.
VCOOutput
Frequency
VCO Input Voltage -
3-107
MB1509
PHASE DETECTOR OUTPUT WAVEFORM
Ir
Ip
~
(FC bit = High)
Do - - -
~- - -
Nole:
~r-
Z---9-------'1- ---trL------Jr-------',------J,_ -
(FC bit = Low)
Do - - -
, ,
tw
tw
LD
____________
, ,
,
, ,
~
~- - - z --
H
-d-------'1- ----9-------Jr------J,_ -----J1_-
• Phase difference detection range = -21< to +2"
• LD output becomes low when phase difference is tw or more.
LD output becomes high when phase difference less than tw is reperated 3 times or more.
(e. g. tw = 625 to 1250 ns. foscin = 12.8 MHz)
• Spike apperance depends on the charge pump characteristics. The spike is output to diminish the dead band.
• When Ir > Ip or Ir < fp. spike might not generate depending upon the VCO characteristics.
3-108
MB1509
ANALOG SWITCH
ONiOFF of the analog switch is controlled by the combination of the control data and LE signal. When the analog switch is ON, BS1, BS2 pin
output the charge pump output (001,002). When analog switch is OFF, BS pin is set to high impedance.
Control data = H
Divide ratio of transmit section is set
LE
=H
LE
=L
Control data = L
Divide ratio of reception section is set
LE
=H
LE
=L
Analog switch of transmit section
ON
OFF
OFF
OFF
Analog switch of reception section
OFF
OFF
ON
OFF
ID
When an analog switch is inserted between LP1 and LP2, faster lock up time is achieved to reduce LPF time constant during PLL
channel switching.
----------------~
I
I
I
CHARGE PUMP
~
:Hr-~b,7---I:
L
LPF-1
:1--------fp
H
L
L
(f,)
L
H
Z
(fp)
f,f.
t
t
u
u u
----u-;:- ---- -L-t ---
f,=f.
I
f,f. or f,fp
H
L
L
(f,)
L
H
Z
(fp)
f,d p
L
H
Z
(f,)
H
L
L
(fp)
f,=fp
Z
L
Z
(f,)
Z
L
Z
(fp)
Z=(High impedance)
Depending upon VCO characteristics. FC pin should be set accordingly:
When veo characteristics are like(j). FC should be set High or open circuit;
FC should be set Low.
When VCO characteristics are like
®.
3-132
VCO INPUT VOLTAGE -
MB1512
f,
---.f
t
t
u
lOU
MH
Do - - - - - '
1
t
u u
----u:------L-.j - - I
~--------r-- z
f,>f.
t
f,-f.
I
f,d.
L
L
I
~---"1-
f,d.
f,d.
NOTES: Phase difference detection range: -21t to +21t
Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When f,>f. or f,d., spike might not appear depending upon charge pump characteristics.
ANALOG SWITCH
ON/OFF of analog switch is controlled by lE input signal. When the analog switch is ON, internal charge pump output (Do) to be
connected to BISW pin. When the analog switch is OFF, BISW pin is set to high-impedance state.
lE=H (Changing the divide ratio of internal prescaler) : Analog switch=ON
lE=l (Normal operating mode)
: Analog switch=OFF
lPF time constant is decreased in order to insert a analog switch between LPF1 and LPF2 when channel of PLL is changing.
Thus, lock up time is decreased, that is, fast lock up time is achieved.
------------------,0
•
0
CHARGE PUMP
\.-_
...
__ ...... __ ..... -,
, BISW
.
(CONTROL SIGNAllE)
:
--------------------------------~
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Min
Typ
Max
Vee
4.5
5.0
5.5
V
V.
Vee
V.
8.0
V
Input Voltage
V,
GNO
Vee
V
Operating Temperature
T.
-40
85
°C
Power Supply Voltage
3-133
MB1512
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Power Supply Current
Condition
Value
Min
Typ
Max
Unit
mA
100
Note 1
8.0
I..
I..
Note 2
OSC,.
lose
1m
VI,.
-10
OSC,.
Vosc
0.5
V,...
Except fin
andOSC,.
V'H
VccxO.7
V
Data
Clock
I'H
1.0
f1A
III
-1.0
f1A
OSC,.
lose
±SO
f1A
LE,FC
IlE
-60
f1A
10
1100
MHz
20
MHz
6
dBm
Operating Frequency
III
Input Sensitiv~y
High-level Input Vonage
Low-level Input Voltage
High-level Input Current
Low-level Input Current
Input Current
High-level Output Current
LOW-level Output Current
Except Do
and OSCOUT
12
VccxO.3
V'L
VOH
Vcc=5V
V
V
4.4
VOL
0.4
V
1.1
f1A
N-channel Open Drain
Cutoff Current
Do,0P
10FF
Except Do
and OSCOUT
IoH
-1.0
mA
Output Current
10L
1.0
mA
Analog Switch On Resisior
RON
Vcc'f.V~8V
25
NOTE 1: I· = 1.1 GHz, OSC",= 12MHz, Vr.c=5V. Inputs are grounded and outputs are open.
NOTE 2: t.C coupling. Minimum operating Irequency is measured when a capacitor 1000pF is connected.
3-134
Q
MB1512
TEST CIRCUIT
Vp=6V
1000pF
PeG:=Itr-'
1
500
109 8
7
6
5
4
321
111213
14
15
16
17
181920
L--------.5 to +7.0
V
Vp
Vee So Vp So 10.0
V
VOUT
4>.5 to Vee +0.5
V
Output Current
loUT
±10
mA
Storage Temperature
TSTG
-65 to +125
°C
©
Pin Assignment
OSCIN
PS
NC
NC
OSCDUT
IA
Vp
fp
vee
Output VoHage
Note:
FPT-20P-M03
Permanent device damage may occur il absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as deteiled in the operation sections 01 this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Do
GND
BiSW
FC
LE
LD
Data
NC
NC
lin
CK
Thla device contains c1rcuHrv to protect the InpuIB against
damage due to high static YOJIages or electric fields. However, It
II acM&ed that normal precautions be taken to avoid application
01 tII1'f voltage high.. than maximum rated wIag.. to Ihl. high
I~noe circuh.
'99' by FUJITSU LIMITED and Fujitsu Microelectronics. Inc.
3-139
MB1513
BLOCK DIAGRAM
ooc.J'>------,i
. .~Sl
l
Oscillator
flS:-bllshiftre-;;';-l
I
-
4
OSCoUTCi'j')o-------1
jl 16-bhhift register I
..
>:n:[]:II:O:I1:~
1
15-bit latch
1
15-bit latch
I
I
>:n:[]:I1:o:n:<
1 Programmable 1
I reference divider I
t---+-H--i+ojJ, Binary 14-bit IsH-l,eferenoe counte'l
W.rr--
L ________ J
PSl
'---++---otJJ lntermit,tent 1'1-+---+--1....,1-1-....
From charge
operatIon
r-+t---;Icontrol circuitr
~~pu~m~p~---t_+1-------_t--_r-_t_i------~
Do ~
I - - - - - - - - - j I - - - - - - t - - - - - - 1 J Schmitt
..
, trigger
From
GND ~phase
comparator
JLJo-_-(,~i'
LE
..------------,
1
1
19-bit shift register
+
I
19-bit shift register
~:I1:[]:II:[]:U:[]:II:<
4
PSl
SW
I
=ier
output
J Prescaler
fiN \(i8}-_-I
1-
'--......_ ....IPsl
MC
1
I
Ill-bit latch I
I
~:n:[]:II:O:II:[]:I1:<
Programmable divider
I
i
I
I II
I
1 1
J
I
,
I
Binary 7-bj,t lBinary ll-bitlH -_---'
swallow
programma-I,
counter
ble counterJ I
L--tt...:ti---
J
'---------1
3-140
1
la-bit latch
7-bitlatch
Control circuit
I
J
l-bit
control
latch
Schmitt
ger
,~ Data
'-----t~"
~'r' Clock
MB1513
PIN DESCRIPTION
.r\'.··.·· . . •••.. l1li .• • •.
1
OSC'N
2
NC
3
OSCOUT
I
Programmable reference divider input
Oscillator input
An external crystal is connected to this pin
0
Oscillator output
An external crystal is connected to this pin
No
Power supply input for charge pump and analog switch
4
Vp
5
Vee
-
Power supply
6
Do
0
Charge pump output
The phase of charge pump is reversed depending on FC input
7
GND
8
LD
0
Ground
Phase comparator output
The output level is high when LD is locked. The output level is low when LD is unlocked
9
NC
-
No ~.".c,,"v.
10
f'N
I
Prescaler input
An external VCO should be AC-coupled to this pin
11
Clock
I
Clock input for 19-bit and 16-bit shift registers
One bit of data is shifted into the registers on the rising edge of the clock
Schmitt trigger circuit is involved
12
NC
-
No "v .... c,,"v ..
13
Data
I
Binary serial data input
The last bit of the data is a control bit
When the control bit is high, data is transmitted to the 15-bit latch
When the control bit is low, data is transmitted to the 18-bit latch
Schmitt trigger circuit is involved
14
LE
I
Load enable signal input
When LE is high, the contents of the shift register are transferred to a latch, depending on the
control bit in the serial data. At the same time, an internal analog switch turns on and the
output of the internal charge pump is connected to the BiSW pin
Schmitt trigger circuit is involved
15
FC
I
Phase select input of phase comparator (with internal pull-up resistor)
When FC is low, the characteristics of charge pump and phase comparator are reversed
FC input signal is also used to control the foul pin (test pin) of fR or fp
16
BiSW
0
17
fp
0
18
fR
il
19
NC
-
20
PS
I
Analog switch output
Usually, BiSW is in the high-impedance state. When the switch is on (LE is high), the charge
pump is connected to the BiSW pin
""
,~u,d
counter output monitor pin
' counter output monitor pin
No "v." .c""v..
Power save signal input
Set low when the system is operating (Never use pin 20 as it is opened)
PS = High : Operation mode
PS = Low : Stand-by mode
3-141
MB1513
FUNCTION DESCRIPTIONS
Pulse swallow function
The divide ratio can be calculated using the following equation:
fvco - [(M x N) + Al x fose + R (A < N)
fvco : Output frequency of external vottage controlled oscillator (VCO)
N
: Preset divide ratio of binary 11-bit programmable counter (16 to 2.047)
A
: Preset divide ratio of binary 7-bit swallow counter (0 S A S 127)
fose : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 144>it programmable reference counter (8 to 16.383)
M : Preset divide ratio of prescaler (128)
Serial data Input
Serial data is input using the Data. Clock. and LE pins. Serial data controls the 15-bit programmable reference divider and 18-bit
programmable divider separately.
Binary serial data is input to the Data pin.
One bit of data is shifted into the internal shift registers on the rising edge of the clock. When the load enable pin is high or open.
stored data is latched. depending on the control as follows:
Control data
(a)
Destination of serial data
H
15 bit latch
L
18 bit latch
Programmable reference divider ratio
The programmable reference divider consists of a 15-bit latch and a 14-bit reference counter. The 16-bit serial data format is
shown below:
- - - . . Direction of data shift
Divide ratio setting bit for programmable reference counter
3-142
MB1513
14-bit programmable reference counter divide ratio
8
o
o
o
o
o
o
o
o
o
o
o
o
9
o
o
o
o
o
o
o
o
o
o
o
o
o
•
16383
(Divide ratio
Notes:
(b)
=
8 to 16,383)
1. Divide ratios less than 8 are prohibited.
2. SW: This bit selects the divide ratio of the prescaler
SW Low: 128 or 129
(SW must be always be low.)
3. S1 to S14: These bits select the divide ratio of the programmable reference counter (8 to 16,383).
4. C: Control bit: Set high.
5. Input data MSB first.
Programmable divider divide ratio
The programmable divider consists of a 19-bit shift register, an 18-bit latch, a 7-bit swallow counter, and an II-bit
programmable counter. The 19-bit serial data format is shown below:
- - -...~ Direction of data shift
Divide ratio setting bit for
swallow counter
Divide ratio setting bit for programmable counter
3-143
MB1513
•
7-bit swallow counter divide ratio
o
III
•
o
o
o
o
o
o
o
o
o
o
o
o
II-bit programmable counter divide ratio
0
127
16
o
o
o
o
0
o
o
o
o
17
o
o
0
o
o
o
o
o
o
2047
(Divide ratio = 0 to 127)
Notes: 1.
2.
3.
4.
5.
(Divide ratio = 16 to 2.047)
Divide ratios less than 16 are prohibited for ll-bit programmable counter.
SI to S7: These bits select the divide ratio of swallow counter (0 to 127).
S8 to S18: These bits select the divide ratio of programmable counter (16 to 2.047).
C: Control bit: (Set low)
Input data MSB first.
Serial data input timing
•
t,
t,
(~
(~
1~s): Data setup time
t, (~ 1~s): Data hold time
1~s): LE setup time to the rising edge of last clock
Data
~
(SW) (*1)'
Clock
(SI4)
__
~
,
(S8)
,
__
(S7)
LSB
(SI)
(C: Control bit)
JLlJL--J1lJL--1LILI
LE
t, (<> l~s) : Clock pulse width
t, (~I~s): LE pulse width
~--~--~ C: Control bit
,
I
, ,
t1 --:--;-
t, -:
I
•
t3
"
I
~
I
,
-._-...,......: t4
t5
.......;--+--
*1: Bits enclosed in parentheses are used when the divide ratio of the programmable reference divider is selected.
Note:
3-144
o
One bit of data is shifted into the shift register on the rising edge of the clock.
MB1513
Intermittent operation
Intermittent operation limits power consumption by shutting down or starting the internal circuits according to its necessity. If device
operation resumes uncontrolled, the error signal output from the phase comparator may exceed the limit due to an undefined phase
relationship between the reference frequency (f.) and the comparison frequency (fp) and frequency lock is lost.
To prevent this, an intermittent operation control circuit is provided to decrease the variation in the locking frequency by forcibly
correcting phase of both frequencies to limitthe error signal output. This is done by the PS control circuit. If PS is set high, the circuit
enters the operating mode. If PS is set low, operation stops and the device enters the stand-by mode. Each mode is explained below:
•
Operating mode (PS = High)
All circuits are operating, and PLL operation is normal.
•
Stand-by mode (PS = Low)
Circuits that do not affect operation are powered-down to save power.
The current in the power save state is typically 100 j.lA.
At this time, the levels of Do and LD are the same as when the PLL is locked.
Since Do is placed in the high-impedance state and the input vo~age of the vo~age-controlled oscillator (VCO) is set to the
vo~age in the operating mode (when locked) by the time constant of the low-pass filter, the frequency output from the VCO (fvco)
is kept at the locking frequency.
The operating and stand-by modes alternate repeatedly. This intermittent operation limits the error signal by forcibly correcting the
phase of the reference and comparison frequencies to limit power consumption.
The device must be set in the stand-by mode (PS = low) when it is powered up.
Relationship between
Fe input and phase characteristics
The FC pin controls the phase characteristics of the phase comparator. The internal charge pump output level (Do) is reversed
depending on the FC pin input level. The relationship between the FC input level and Do is shown below:
L
H
01: High impedance
When designing a synthesizer, the FC pin setting depends on the VCO characteristics.
*: When the VCO characteristics are similar to
CD, set FC high or open.
*: When the VCO characteristics are similar to
VCO
output
frequency
®, set FC low.
VCO input voltage _
3-145
MB1513
Phase comparator output waveform (Fe =High)
fp
~----------------~~
LD
Do - - - -
_lr _.
Z .-
Vc -----Jr------_lr -------'r ---
~- - - - -'r ---fR = fp
fR < fp
fR = fp
fR = fp
fR = fp
Notes: 1. Phase difference detection range: -21t to +21t
2. Spike appearance depends on the charge pump characteristics. The spike is output to diminish dead
band.
3. When fR > fp or fR < fp, spike might not appear, depending on the charge pump characteristics.
4. LD is low when the phase difference is two or more. LD is high when the phase difference is two or less
for three or more continuous cycles (when foselN = 12.8 MHz, tw = 625 to 1,250 ns).
Analog switch
The LE signal turns the analog switch on or off. When the analog switch is turned on, the charge pump output (Do) is output through
the BiSW pin. When it is turned off, the BiSW pin is in the high-impedance state.
When LE = high (when the divide ratio of the internal divider is changed): Analog switch _ on
When LE = low (normal operating mode): Analog switch = off
The LPF time constant can be decreased by inserting an analog switch between LPF1 and LPF2. This decreases the lock-up time
when the PLL channel is changed.
------------,I
___ J~~~I~~~~El. ________
3-146
I
J
MB1513
RECOMMENDED OPERATING CONDITIONS
Supply voltage
Vp
Input vokage
V,
Operating temperature
Vcc:S; Vp:S; 8.0
GND
v
v
-40
Notes: To protect against damage by electrostatic discharge, note the following handling precautions:
-
Store and transport devices in conductive containers.
Use properly grounded workstations, tools, and equipment.
Turn off power before inserting or removing this device from a socket.
-
When handling PC boards on which devices are mounted, protect leads of the device using conductive sheet.
3-147
MB1513
ELECTRICAL CHARACTERISTICS
-
_.~~mUl
mA
With f'N = 1.1 GHz, OSC'N =
12MHz, V ec =5.0V. Inputs
are at Vce and outputs are
open
-
~A
With f'N = 1.1 GHz, OSC'N =
12 MHz, Vee = 5.0 V. The
PS pin is grounded, remaining inputs are at V ceo and
outputs are open
-
1100
MHz
AC coupling. The minimum
operating
frequency
is
measured with a 100-pF
capacitor connected
-
12
20
MHz
VflN
-10
-
6
dBm
Vose
0.5
-
-
Vp-p
V'H
Vee X 0.7
-
-
V
VIL
-
-
Vee X 0.3
V
I'H
-
1.0
-
~A
III
-
-1.0
-
~A
FC
IFe
-
-60
-
~A
OSC,.
lose
-
±50
-
I!A
VOH
4.4
-
-
V
VOL
-
-
0.4
V
Supply current
Icc
-
8.0
Stand-by current
IPS
-
100
f'N
f'N
10
OSC'N
f08c
f'N
OSC'N
Operating frequency
Input sensitivity
High-level input voltage
Low-level input voltage
Except f,. and
OSC,.
High-level input current
Data Clock LE
Low-level input current
Input current
High-level output voltage
Low-level output vo~age
Except Do and
OSCOUT
High-impedance
Cut off current
Do
IOFF
-
-
1.1
~A
Except Do and
OSCOUT
10H
-1.0
-
-
mA
Output current
10l
1.0
-
-
mA
-
25
-
Q
Analog switch ON resistance
3-148
RON
Vee = 5 V
Voo = GND to 8 V
Vee '5, Vp '5, 8 V
MB1513
TEST CIRCUIT
(FOR MEASURING PRESCALER INPUT SENSITIVITY)
Vp =6V
0.1 11
P G
==r;j"",-PL-L_I-L7Ji-...r::::jt:t::::;-7Ji------'
5001.
10 8 7 6 5 4 3
1
Voo = 5 V
11 13 14 15 1718 1920
3-149
MB1513
APPLICATION EXAMPLE
I
LPF
I
I
vco
Output
I
1
Fro.
controller
IfR Ifp
PS
20
19
18
LE
BiSwlFC
15
16
17
I
I
Data
Clock
14
13
12
11
7
8
9
10
MB1513
1
2
3
OSC'N
HOI-X'tal
Xc,
Vp, Vpx
C,' C.
3-150
4
5
oSCorr VP
6V
6
Vcc
Do lGND
5V
LI J
;t c. ;t.
0.1 1l
Maximum 8 V
Depend on the crystal parameters
ILD
~i
1JJo P
:
11
47K
47K
7l r
MB1513
PACKAGE DIMENSIONS
20·LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P·M03)
.049~:gg:
...-;*---l----:-,..,---- (MOUNTING HEIGHT)
(1.25~:ro)
~ nn:ff~ nn~ 1 . 1
I
INDEX
cI
I
252±.OOB
(6.4o±O.20)
*.173±.004
(4.4o±O.10)
~;::n:::;;::;;:::;;::;;r;;:::;?I ~
"A"
-.,'
-
.213(5.40) NOM
'0
.0256±.0047
(0.22~:Jg)
(0.65±o.12)
.230(5.B5)
REF
*:This dimension does not include resin protruction.
©1991 FUJITSU LIMITED F20012S-2C
Dimensions in
inches (millimeters)
3-151
MB1513
3-152
cO
May 1991
Edition 1.0
FUJITSU
DATA SHEET
MB1518
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
SERIAL INPUT Pll FREQUENCY SYNTHESIZER
ON CHIP 2.5GHz PRESCAlER
The Fujitsu MB151S on chip 2.5 GHz dual modulus prescaler is a serial input PLL (Phase
Locked Loop) frequency synthesizer with pulse swallow function. It is well suited for BS tuner,
CATV system applications.
It operates supply voltage of 5.0V typo and dissipates 16mA typo of current realized through the
use of Fujitsu's unique U-ESBIC Bi-CMOS technology.
PLASTIC PACKAGE
FPT·16p·M06
•
Power supply voltage: Vee = 4.5 to S.SV
•
High operating frequency: f.
•
2.5GHz dual modulus prescaler: P = 512/528
•
Low power supply current: Icc = 16mA typo
•
Programmable reference divider: R
•
Programmable divider consisting of:
Binary 5-bit swallow counter (A = 0 to 31 )
Binary 9-bit programmable counter (N = 32 to 511)
•
Wide operating temperature: T. = -40 to +85"C
•
Plastic 16-pin flat package (Suffix: -PF)
= 2.5GHz (V," = -4dBm)
PIN ASSIGNMENT
= 512
16
LD
Data
2
15
fouT
Clock
3
14
VCC2
4
13
f,.
GND2
LE
VCC1
ABSOLUTE MAXIMUM RATINGS (see NOTE)
OSCOUT
6
11
t;;
GNDI
7
10
Fe
0.5 to Vee +0.5
V
001
8
9
002
±10
mA
Vee
-{l.5 to 7.0
Output Voltage
Vo
Output Current
10
TSTG
-{is to +125
NOTE:
5
12
V
Power Supply Voltage
Storage Temperature
TOP
VIEW
asc,.
Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
it Is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated
voltages to this high impedance circuit.
Copyr;ght ©1991 by FUJITSU LIMITED
3-153
MB1518
MB1518 BLOCK DIAGRAM
LD
I.
loUT
13
GND2
!
i;
11
FC
Do.
10
9
fOUT
FC ' - - - r - r - - - - - '
Crystal
Oscillator
0)
LE
3-154
0
Data
0
Clock
d;
Vee,
5
OSC.
OSC""
r
GND1
8
Dot
MB1518
PIN DESCRIPTIONS
LE
Load enable input pin. This pin involves a schmitt trigger circuit.
When this pin is high, the data stored in the shift register is transferred into the latch.
2
Data
Serial data of binary code input pin. This pin involves a schmitt trigger circuit.
3
Clock
Clock input pin of the 14-bit shift register. This pin involves a schmitt trigger circuit.
On rising edge of the clock shifts one bit of the data into the shift register.
4
VCC1
PLL power supply voltage input pin.
5
6
OSCIN
OSCOUT
Oscillator input pin.
Oscillator output pin.
A crystal is connected between OSCIN pin and OSCou, pin.
7
GND1
8
9
0 01
002
10
FC
11
tn
Complementary input pin of f•. Please connect to GND through a capacitor.
12
GND2
Prescaler ground pin.
13
1m
Prescaler input pin,
This signal is input with AC coupled.
14
VeC2
Prescaler power supply voltage input pin.
15
fOUT
I
0
PLL ground pin.
0
0
Charge pump output pins.
Phase characteristics can be reversed depending upon FC pin input level.
Phase select input pin of the phase detector. This pin involves an internal pull up resistor.
When this pin is low, characteristics of the charge pump and phase detector can be reversed. This
input also selects fouT pin output level, either fr or fp. Please see on page 6.
0
Monitor pin of the phase detector input.
fOUT pin outputs either of the programmable reference divider output frequency fr or programmable
divider output frequency Ip depending upon the FC pin input level.
FC pin
16
LD
III
o
fout output signal
H
fr
L
fp
Phase detector output pin.
Normally this pin outputs high. While the phase difference between Ir and fp exists, this pin outputs
low.
3-155
MB1518
FUNCTIONAL DESCRIPTIONS
DIVIDE RATIO SETTING
Divide ratio can be set using the following equation:
fvco = {(P x N) + (16 x
An x fose + R
fvco: Output frequency of an external voUage controlled oscillator (VeO)
P:
Preset divide ratio of an internal dual modulus prescaler (512)
N:
Preset divide ratio of binary 9-bit programmable counter (32 to 511)
A:
Preset divide ratio of binary 5-btt swallow counter (0 to 31)
fose: Reference oscillator frequency
R:
Preset divide ratio of reference counter (512)
SERIAL DATA INPUT
On rising edge of the clock shifts one bit of the data into the shift register.
When the load enable is high, the data stored in the shift register is transferred to the latch.
14 bit of serial data formit is shown below.
IT~~i :I : I : I " I : I : I ." I : I : I ~ rr I
------I...
I
I'
-I'
Divide ratio of swallow
counter setting bit
Data Input Flow
"I
Divide ratio of programmable
counter setting bit
5-bit swallow counter divide ratio (A 1 to AS)
Divide ratio
A
A
5
4
A
3
A
A
2
1
0
0
0
0
0
0
1
0
0
0
0
1
2
0
0
0
1
0
1
1
N
7
N
6
N
N
N
5
4
3
N
2
N
1
0
:
:
:
:
31
1
1
1
A
:
9-bit programmable counter divide ratio (Nl to N9)
N
9
N
8
32
0
0
0
1
0
0
0
0
33
0
0
0
1
0
0
0
0
1
34
0
0
0
1
0
0
0
1
0
1
1
1
1
1
1
Divide ratio
3-156
:
:
:
:
511
1
1
1
:
:
MB1518
SERIAL DATA INPUT TIMING
Data
Clock
LE
N9
(MSB)
---II: ---3(AI
--.
A5
:,
---
(LSB)
_--------
.....
~.JUl.1l-fl,
------!-:_..,--- - -";--";',-;....,
;.."'-:
. tt:
,
rL
,
, '
--, + - - t - -,
Ia~
~t.a~
, ,
, ,
is
.....:-.!.-
Note: On rising edge 01 the clock shilts one bit 01 the data into the shilt register.
When LE is high, the data stored the shift register is translerred into the latch.
3-157
MB1518
PHASE DETECTOR CHARACTERISTICS
FC pin selects the phase of the phase detector. Phase characteristics (chage pump output) can be reversed depending upon the FC pin
input level. Monitor pin (lout) output level is selected by the FC pin input level as well.
FC = H (or open)
0.,,0..
fr>fp
H
fr= fp
Z
fr< fp
L
FC=L
0.,,0..
lout
lout
L
Outputs programmable
reference divider output
frequency fro
Outputs programmable
divider output
frequency fp.
Z
H
Note:
Z:
VCO POLARITY
High-impedance
Depending upon the
cordingly.
veo polarity, FC pin should be set ac-
When VCO polarity is like 1,
FC should be set high or open.
When VCO polarity is like 2,
FC should be set low.
VCOOutput
Frequency
VCO Input Voltage _
PHASE DETECTOR WAVEFORM
fr~
L
fp
u u u
(FC=H)
001,0",
(FC=L)
Dot , 002
' I .
Jf-------Ir ---- Lk -----U----L-1---L,
-,J--------Ir --- -'l-----0----Sl---L,
H
z- -
-z- -
fr>fp
Note:
fr=fp
,
'
fr
Power supply voltage input pin for reception section, programmable reference divider, shift register,
and crystal oscillator.
When power is OFF, latched data of reception section and reference counter is cancelled.
17
fin.
Prescaler input pin of reception section.
The connection with VCO should be AC conneciton.
18
LE
Load enable input pin. This pin involves a schmitt bigger circuit.
When this pin is high, the data stored in the shift register is transferred into the latch depending on a
control data.
Atlhis moment, charge pump output signal Is outputlrom BS pin since intemal analog swRh becomes ON.
19
Data
Serial data input pin of 23-bit shift register. This pin involves a schmitt bigger circuit.
The stored data in the shift register is transferred to either transmit section or reception section depending upon a control data.
20
Clock
Control bit data
The destination of data
H
Latch of transmit section
L
Latch of reception section
Clock input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
On rising edge of the clock shifts one bit of data into the shift register.
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
f¥CO - {(M x N) + Al x fooc + R
(A < N)
f¥CO: Output frequency of external voRage controlled ocillator (VCO)
M:
Preset divide ratio of dual modulus prescaler (64)
N:
Preset divide ratio of binary ll-b~ programmable counter (16 to 2047)
A:
Preset divide ratio of binary 7-bit swallow counter (OS A S 127)
fose: Reference oscillator frequency
R:
Preset divide ratio of reference counter (512 or 1024)
3-167
MB1519
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data is input using three pins, Data pin, Clock pin, and LE pin. Programmable divider 01 transmit section and programmable divider 01
reception section are controlled individually.
Serial data 01 binary data is input into Data pin.
On rising edge 01 clock shilts one bit of serial data into the shift register. When load enable signal is high, the data stored in the shift register is
transferred to either the latch of transmit section or the latch of reception section depending upon the control bit data setting.
Control data
Destination of serial data
H
Latch of transmit section
L
Latch of reception section
SHIFT REGISTER CONFIGURATION
Control bit
!
1
2
r
DataFlow_
~S
3
4
s
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
C
R
F
0
F
A
A
A
A
A
A
A
N
N
N
N
N
N
N
N
N
N
N
N
E
P
M
C
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
T
F
Nl to NIl
AI toA7
FC
DMY
FP
REF
CNT
Y
: Divide ratio olthe programmable counter setting bit (16 to 2047)
: Divide ratio of the swallow counter setting bit (0 to 127)
: Phase control bit 01 the phase detector
: Dummy bit (sets to low)
: Output of the programmable divider control bit (Ipl or fp2)
: Divide ratio of the reference counter setting bit (512 to 1024)
: Control bit
SERIAL DATA INPUT TIMING
• t" 12, 13, t" t5 ~ 'I'S
Data
Clock
C:Controlbit
.. ~--R;~
~. __ ::=J\
NIl =MSSV;;;;---
~_
,
,
--illJl--JLl.Jl---fl-fl-,
LE
- - - - -....-
rL
11
..
,--
.....
•
I
.... 12--r
I t1'
'
I
13"":'-"'I
I
•
....
t.... '
I
I
:
:
t5 ...............
, ,
On rising edge of the clock shifts one bit of the data into the shift register.
3-168
22
MB1519
BINARY 11-BIT PROGRAMMABLE COUNTER DATA SETTING
Divide
Ratio
(N)
N
11
N
10
N
N
9
8
N
7
N
6
N
5
N
N
4
3
N
2
N
1
16
0
0
0
0
0
17
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
2047
1
1
1
1
1
1
1
1
1
1
1
Note: Divide ratio less than 16 is prohibited.
Divide ratio (N) range = 16 to 2047
BINARY 7-BIT SWALLOW COUNTER DATA SETTING
Divide
Ratio
(A)
A
7
A
6
A
5
A
A
4
3
0
0
0
1
0
0
127
1
1
1
A
2
A
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Note: Divide ratio (A) range = 0 to 127
DMY : DUMMY BIT INPUT
This bit is set to low in operation.
REF : DIVIDE RATIO (R) OF THE REFERENCE COUNTER SETTING BIT
H = 512 (Ir = 25.0 kHz)
L = 1024 (Ir = 12.5 kHz)
FP
: OUTPUT OF THE PROGRAMMABLE DIVIDER SETTING BIT
H = Ip pin (15 pin) outputs programmable divider output frequency (fp1) 01 transmit section.
L = fp pin (15 pin) outputs programmable divider output Irequency (fp2) 01 reception section.
FC
PHASE CONTROL BIT OF THE PHASE DETECTOR
Output of charge pump is selected by FC pin.
FC= H
FC = L
Ir >Ip
H
L
fr=fp
Z
Z
fr fp or fr < !p, spike might not generate depending. up the veo characteristics.
3-170
MB1519
ANALOG SWITCH
ONIOFF of the analog switch is controlled by the combination of the control data and LE signal. When the analog switch is ON, BSt, BS2 pin
output the charge pump output (Dol, 0(2). When analog switch is OFF, BS pin is set to high impedance.
Control data = H
Divide ratio of transmit section is set
Control data = L
Divide ratio of reception section is set
LE = H
LE = L
LE = H
LE = L
Analog switch of transmit section
ON
OFF
OFF
OFF
Analog switch of reception section
OFF
OFF
ON
OFF
lID
When a analog switch is inserted between LPt and LP2, faster lock up time is achieved to reduce LPFtime constant during PLLchannel switching.
----------------, Do
1
CHARGE PUMP
L. _ _ _ _ _ _ _ _ _ _ _ _ _ .,
,
, BISW
(CONTROL SIGNALE)
,
_______________________________ J
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage
HANDLING PRECAUTIONS
• This device should be transported and stored in anti-static containers.
• This is a static-sensitive device; take proper anti-ESD precautions. Ensure that personnel and equipment are properly grounded. Cover workbenches with grounded conductive mats.
o
Always tum the power supply off before inserting or removing the device from its socket.
• Protect leads with a conductive sheet when handling or transporting PC boards with devices.
3-171
MB1519
ELECTRICAL CHARACTERISTICS
lee,
Reception section is active.
5.5
1=
Transmit/reception section
are active.
11.0
mA
Power Supply Current.
lin
10
fin
600
MHz
Operating Frequency..
OSC'N
lose
lin
Vlin
Input Sensitivity
High-level Input Voltage
Low-level Input Voltage
High-level Input Cunrent
Except lin
andOSC'N
12.8
20
Vee = 2.7 to 4.0V, 50Q
~
0
Vee = 4.0 to 5.5V, 50Q
-4
2
dBm
VeexO.7+0.4
V'H
V
VeexO.3--{).4
VIL
Data,
Clock
LE
I'H
1.0
I,L
-1.0
FC
IFe
-60
OSCIN
lose
±50
Low-level Input Current
Input Current
High-level Output Voltage
Low-level Output Voltage
High-impedance Cutoff
Current
Except Do
and OSCOUT
Do,
-_ _-<
GND
son!
P.Gi"
l000pF
son
fp
'---+--------0
Oscilloscope
3-173
MB1519
APPLICATION EXAMPLE
Output
VCO
Lock Detector
MB1519
Output
VCO
Note: V." V..
C1,C2
Clock, Data, LE
X'taI
3-174
:BVmax.
: depends on the crystal oscillator.
: involve the schmitt circuit.
When input pins are open, please insert the pull down/up resistor individually to prevent the oscillation.
: 12.BMHz
MB1519
PACKAGE DIMENSIONS
20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-20P-M02)
,~~~f ':. :!":'::]Jgi~',t _ _.,,_'~"M"
I 1050:+:J>12
11.034:+:J>12
(0.86 :+:g30)
.010±.002
10.25±0.05)
11.27 :+:g.30)
W.17214.36) MAX
-f-l.118(3.00) MIN
.050(1.27)
MAX
@19B8FUJITSULIMITEDD20003S-3C
.10012.54)
TYP
II
.018±.003
10.46±0.08)
.020(0.51) MIN
Dimensions in
Inches (millimeters)
3-175
MB1519
PACKAGE DIMENSIONS (Continued)
20-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-20P-M01)
.08912.25) MAX
ISEATED HEIGHT)
II
.05011.27)
TYP
.018±.004
10.45±0.10)i$i ~.00510.13) @
I
r------------.,
I
, II
4=
:
:
'
"
.00410.10)
-.450111.43) REF-
.. 1990 FUJITSU LIMITED F20003S-5C
3-176
Details of "A" part
I
I
I
,
.008(0.20):
I
:
I
I
.02010.50) :
.00710.18) :
MAX
:
I
,02710.68) I
MAX
I _______________
I...
JI
Dimensions In
inches (millimeters)
- - - - - - - - - - - - - - - - - - Section 4
Sin~le-Ch~ VCOs/Prescalers
- At a Glance
Page
Device
Maximum
Frequency
Divide
Rallo
128 or 129
Supply
4-3
MB551
1 GHz
NOTE:
The MB551 is available in an 8-pin Plaslic FPT package.
Icc
Vee
16 rnA (lyp) 5 V (Iyp)
III
4-1
Single-Chjp Presca!,rsNCOs
4-2
Telecommunications Data 80qk
OJ
FUJITSU
June 1991
DATA SHEET
MB551
1 GHz Dual Modulus Prescaler
The Fujitsu MB551 is a dual modulus prescaler w~h low supply current and a veo
(voltage controlled oscillator). It is used in a frequency synthesizer in the 1 GHz
region.
The MB551 contains a Colpitts oscillator w~h a grounded base capac~or. an
open-collector output buffer amplifier. a prescaler interface circuit. and a dual
modulus prescaler that can select divide ratios of 128 or 129.
The VCO oscillator section can be constructed with external components such as a
capacitor. dieletric oscillator (resonator). and variable capac~or.
The on-chip VCO and prescaler are connected on internal control circuit. Thus. the
influence caused by carrier to noise by deviation of prescaler input load is
suppressed.
The MB551 operates on a supply voltage of 5 V typical and has a 16 mA supply
current typical.
• Oscillator frequency: 1 GHz max.
• Low supply current: lee = 16 mA
typo
• Oscillator output voltage: 0 dBm
typo
• Stable oscillator output
• Carrier to noise ratio:
70 dB typo (At = 50 kHz.
BW-15kHz
65 dB typo (Af = 25 kHz.
BW = 15kHz
• Supply voltage dependence:
±200 kHzN typo
• Pulse swallow method: Divide
ratio of 128 or 129
• Load regulation: ±2 MHz
VSWR=2typ.
• Frequency stability: 35 ppmf'C
(Referenced to 25·C)
• Prescaler output contains
termination circuit: VI = 1.6 Vp-p
typo
Symbol
Ivco
Ratings
-0.5 to +7.0
GND
Unit
Vee
E
V
MC
C
OUT
B
Supply Voltage
Vcc
Oscillator Transistor
Base. Emitter Input Voltage
Va
Ve
DC voltage is not input from
o
InBut Voltage for MC and
T (3. 4 pins)
VPt
-0.5 to Vee +0.5
Input Voltage for fvco and C
(1. 6 pins)
VP2
Vee:!: VP2 < +7.0
V
Input Current
Ip
±10
mA
Storage Temperature
TSTG
--55 to +125
·C
outside.
V
Note: Permanent device damage may occur if absolute maximum ratings
are exceeded. Functional operation should be restricted to the conditions as detailed in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
©
Pin Assignment
• Plastic 8-pin flat package:
Suffix-PF
ABSOLUTE MAXIMUM RATINGS
Parameter
Plastic Package
FPT-OSP-M01
• Signal to noise ratio: 45 dB typo
(BW = 0.3 to 3 kHz. 3 kHz Dev.
1 kHz tone)
Pin assignment to be determined
Thill device contains clrcuhry to protect the Inputs agaInat
volIages or oJoc:trIc field .. _ . k
10 ad_thai normal prec:auIIonB be - . .. avoid application
of.., wltago higher than maximum _ volIages Iothlo high
damogo duo .. high _
~clrcull.
1991 by FUJITSU LIMITED and Fujllsu MlcroolecilOnlcs. Inc.
4-3
MB551
Figure 1. MB551 Equivalent ClrcuH
DXQ
F3
..
C
Bias
Circuit
PIN DESCRIPTIONS
4-4
Pin No.
Symbol
110
Description
1
fvco
0
Voltage controlled oscillator output
2
Vee
-
Supply voltage input, +5V
3
MC
I
Modulus control input
4
OUT
0
Prescaler output
5
B
-
Oscillator transistor base pin
6
C
-
Oscillator transistor collector pin
7
E
-
Oscillator transistor emitter pin
8
GND
-
Ground
H
MB551
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Min
lYP
Max
UnH
Vee
4.5
5.0
5.5
V
Supply Voltage
External Variable Capackor Control Voltage
VT
1.5
4.5
V
Operating Temperature
T"
-40
+85
°C
Presealer Output load
CL
8
pF
Max
UnH
VCO ELECTRICAL CHARACTERISTICS1,2
Value
Parameter
Symbol
CondHlon
Min
lYP
Oscillator Frequency
fosc
Oscillator output
POUT
-To be supplied-
0
dBm
Carrier to Noise Ratio
CIN
Af=25kHz, BW=15kHz
65
dB
SIN
BW - 0.3 - 3kHz, 3kHz Dev.
Tone 1kHz
45
dB
-10
dB
35
ppmJOC
±100
kHzIV
Signal to Noise Ratio
-TBD-
900
MHz
Fundamental to
1st Harmonic Ratio
SP-1
Frequency Stabilky
Af,
TA=-40-85°C
Referenced to 25°C
Supply Deviation
Afv
Vee - 5V ±100/0
Conversion Gain
Afosc
Control range: 1.5 - 4.5V
4.3
MHzIV
load Regulation
AfswR
VSWR - 2.0 All phase
Referenced to 50 0
±2
MHz
Not.. : 'These values depend on external components.
2"fhese values are measured under the test circuit shown in Figure 2.
4-5
MB551
PRESCALER ELECTRICAL CHARACTERISTICS
Value
Parameter
Symbol
Condition
Min
Max
'l\'p
Supply Current
Icc
Output Amplitude
VOUT
Internal termination
resistor is used.
Load capacitor is
less than 8 pF.
1.0
16.0
mA
1.6
Vp-p
Input Frequency
lin
Minimum value is
measured with input
coupling capacitor
1000 pF.
10
900
MHz
Input Signal Amplitude
Vin
-4
6
dBm
High-level Input Voltage
lorMC
VIH
2.0
Low-level Input Vokage
10rMC
VIL
0.8
V
High-level Input
Current lor MC
IIH
0.4
mA
Low-level Input
Current for MC
IlL
Modulus Setup Time
tseT
V
mA
-0.2
16
26
DUAL MODULUS FUNCTION
128
---.. .,.
5lJl- fLflJl. flJl
.
A.
r~--~
IN
I
J. ~
OUT
M
,.'
•
129
. . . ---,
JU1:
. -illlJlJl-flJl
A.
r~---
•
. ; . 6~,- ---:!-F -- -- --- --~~..,-.
__ : 1,-__----___
___
~J __ _
64
_..::6;;:..4._
••-.••
,- -'
"
."
..- -,. .,. ...
!sET
•
I
!sET
Notas: lWhen Me is high, divide ratio of 128 is selected.
2When Me is low, divide ratio of 129 is selected.
(V/H = 2.0 V min., Vu. = O.S V max.)
awhen divide ratio of 129 is selected, positive pulse is added by 1 to 65.
'The typical setup time is 16 ns from the Me signal input to the timing of change of prescaler divide ratio.
4-6
Unit
I
L
ns
MB551
Figure 2. Test Circuit Example-!
I II!
2pF
1500MHZ§
82nH
ISVl64
c::::Jt-......
l----11--~O
51 pF
4pF
1 pF
2pF
7
8
22nH
3pF
6
J
5
MBSSl
3900
2
51pF
J J
VT
O.OlI1F
4
3
.20pF
fOUT
OutputD-1
r -....-
(500)
56nH
.....-oM
J J J
0.01
High-impedance prober
(Sampling scope)
IJ.F
20pF 51 pF
J; 0.011J.F
Note.: Variable capacitor
Chip condenser
Chip coil
Dielectric Oscillator
ISVl64 (NEC)
UMK316C, UMK212C, UCN103C Series (Taiyo Yuden)
LQN2A Series (Murata)
DRR060UE (Murata)
4-7
MB551
Figure 3. Test Circuit Example-II
I
1500MHZ§
..
1.5pF
II!.
3pF
ISV164
82nH
O VT
CJI--I....-l...---51 pF
0.01 pF
J 1
4pF
2pF
3pF
5
MB551
390Q
22nH
2
51pF
J
~20
pF
fOUT
Oulput Q---1
(50Q)
............-
56nH
Va; (+5V) 0-....-
---+--...
.....
20 pF J; 20 PFJ;
Nol..: Variable capacitor
Chip condenser
Chip coil
Dielectric Oscil/aler
4-8
4
3
......-oM
J J 1 0.01~F
High-impedance prober
(Sampling scope)
20pF 51 pF
J;0.01 ~
ISVl64 (NEC)
UMK316C, UMK212C, UCN103C Series (Taiyo Yuden)
LQN2A Series (Murata)
DRR060UE (Murata)
MB551
Fig. 4 - RECOMMENDED PRINT CIRCUIT BOARD PATTERN
(Parts list)
Cl
:lpF
(Taiyo Yuden UMK212C)
C15
: O.OII'F
C2
: 2pF
(Taiyo Yuden UCN103C)
C16
: O.OII'F
(Film condenser)
C3
: 3pF
(Taiyo Yuden UMK212C)
C17
: O.OII'F
(Film condenser)
C4
:4pF
(Taiyo Yuden UMK212C)
C5
: 2pF
(Taiyo Yuden UMK212C)
Rl
: 3900
(Rohm MCR25)
(Film condenser)
C6
: 20pF (Taiyo Yuden UMK316C)
C7
: 51pF (Taiyo Yuden UMK212C)
C8
: 20pF (Taiyo Yuden UMK316C)
C9
: 20pF (Taiyo Yuden UMK316C)
Ll
: 22nH
(Murata LON2A)
Cl0
: 51pF (Taiyo Yuden UMK212C)
L2
: 56nH
(Murata LON2A)
Cll
: 20pF (Taiyo Yuden UMK316C)
L3
: 82nH
(Murata LON2A)
C12
: 51pF (Taiyo Yuden UMK212C)
VD
: ISV164 (NEC)
C13
: 20pF (Taiyo Yuden UMK316C)
C14
: 51pF (Taiyo Yuden UMK212C)
Dielectric oscillator: (Murata DRR060 Serise, 1.5GHz)
4-9
MB551
TYPICAL CHARACTERISTICS CURVES
Fig. 5 - Supply CUrrent va. Supply Voltage
;(
jE
20.0
TA_25'C
I-
zw
II:
II:
=>
0
>
...J
-~
~
I-
Typ-l6mA
0..
0..
=>
en 15.0
4.5
5.0
5.5
SUPPLY VOlTAGE Vr;c (V)
Fig. 6 - Oscillator Waveform (Span = 50kHz)
-101-+--1-----1-+-1+1-1--1-4--1-----1
FREQUENCY
4-10
MB551
(TEST CIRCUIT - I, RECOMMENDED PRINTED CIRCUIT BOARD USED)
Fig. 7 - Conversion Gain
865
v
~
V
/
/
V
l:J.
fooc. 4.2MHzJV
L
Vee = 5.0V
1.0
2.0
3.0
4.0
5.0
T. = 25'C
VARIABLE CAPACITOR CONTROL VOLTAGE VT (V)
Fig. 8 - Supply Voltage Dependence
N 856.50
:I:
~
j
>o
z
856.25
~
w
5~
u.
~fOlC'+430MHzJV
856.00
~
~
855.75
~
V'
~
855.50
VT = 2.5V
4.5
5.0
5.5
T. = 25'C
SUPPLY VOLTAGE Vee (V)
4-11
MB551
(TEST CIRCUIT - I, RECOMMENDED PRINTED CIRCUIT BOARD USED)
Fig. 9 - ClN, SIN vs. Variable capacitor Control Voltage
iii'
:!a-
80
"'-
~
..
~
SIN
CIN(6 5OI
I-
..
:::;
0-
::E
0
0(
..J
0(
z(!!
-10
iii
I-
::::>
0-
~
-20
::E
::::>
::E -30
Z
:i
1.4
INPUT FREQUENCY Fin (GHz)
Fig. 12- Prescaler Input Sensitivity Curve (Temperature Dependence)
1.B
(Vee = 5V»
E
~
+20
5
w
c +10
::::>
:::;
I0-
::E
0
0(
..J
0(
z
(!!
-10
iii
I-
::::>
0~
-20
::E
::>
::E -30
Z
:i
0.6
1.0
1.4
INPUT FREQUENCY Fin (GHz)
1.B
4-13
MB551
(TEST CIRCUIT - II)
Fig. 13 - Conversion Gain
...
860
:I:
~
j
..
>
0
z
w
:::l
fa
845
II:
f2
~
(5
/
,/
830
/
h_·7.5MHlJV
II:
LL
~
V
/
V
/
Vee = S.OV
T. = 25°C
1.0
2.0
3.0
4.0
5.0
VARIABLE CAPACITOR CONTROL VOLTAGE VT (V)
Fig. 14 - CIN, SIN vs. Variable capacHorControl VoHage
m
:2-
m
:2-
80
50
~
0
~w
z~
f2
70
60
...
--SIN
~---
-
1----
~
-
~
~
clNcA 2510Hz
40
W
~
~
50
Vee = S.OV
T. = 25°C
1.0
2.0
3.0
4.0
5.0
VARIABLE CAPACITOR CONTROL VOLTAGE VT (V)
4-14
f2
.....
~
II:
~
II:
~
MB551
Figure 15. Application Example
2pF
~vn'500
MHz
VH
4pF
J
3901<0 Vee (5 V)
..
MB551
3
2
20pF
5
6
7
LD
8
Do
laca
Iraq.
<>-i
20
p~
Ivoc
Vee
4
M
tOUT
Vee
(5 V)
Vee (5V)
1000pF
J?01 IlJh20 pF
lock-
Clock
Det.
101<0
Data
lE
47 Kn47 Kn 47Kn
Nole:
C1 and C2 depend on crystal oscillator.
4-15
MB551
PACKAGE DIMENSIONS
8-LEAD PLASTIC FLAT PACKAGE
(Case No.: FPT-8P-M01)
.088
25 MAX
"iR~:IR-I-'I---r!
.307 • .018
(1.80'0A0)
.2Il9 ••012
(5.3000.30)
III
DoIaIIs '" "A" part
"A"
:--"
, ,
~
, ,
o
4-16
.D04(O.lO)
.03)
(0.50)
JJ07 .1
MAX
.rtB
.
MAX
Section 5
Piezoelectric Devices - At a Glance
Frequency
Package
Page
Device
Description
Range
Option
5-3
F5CBSeries
SAW-Bandpass Filter
700-1000 MHz
&-pin
I
lCC
5-17
M2Series
VCO(D100)
4-,'30 MHz
14-pin
DIP
5-25
M2Series
VCO(D300)
4-,'30 MHz
16-pin
SIP
5-35
M3Series
VCO(DOO1)
50-300 MHz
16-pin
DIP
5-39
M3Series
VCO(D10l)
50-300 MHz
14-pin
DIP
5-1
Pjezoelectric Devjces
5-2
Telecommunications Data Book
cP
FUJITSU
October 1991
DATA SHEET
F5CBSeries
Piezoelectric Filters
SAW-BPF, 700 MHz to 1000 MHz
The F5 series are wide bandpass filters for use in the 700 MHz to 1000 MHz range.
The F5 series uses a single I~hium tantalate piezoelectric crystal (UTa03) that has a
high electromechanical coupling coefficient. The UTa03 also provides wide
bandwidths and exceptional stabil~y. Fujitsu's exclusive mounting technique makes
the F5 series very compact and surface mountable. The F5 is su~able for use in
handheld phones.
•
Considerably smaller and lighter than the ceramic filter (volume and weight
are reduced by 1130)
•
Surface mount package (SMT)
•
Wide variety of bandwidths
•
low insertion loss
•
High power rating: 0.2 W guaranteed
•
a-pad ceramic package (lCC)
(Bottom View)
®
®
0
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Symbol
Ratings
Unit
°C
T.
-30 to 70
Storage Temperature
Tsm
--40 to 100
°C
Maximum Input level
PIN
200
mW
700 to 1000
MHz
Frequency Range
RECOMMENDED OPERATING CONDITIONS
Parameter
Operating Temperature
Ratings
-30 to 70
Note: Permanent device damage may occur if absolute maximum ratings are
exceeded. Functional operation should be restricted to the conditions
as detailed in the operation sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
©
®
Pin No.
Pin Name
1
GND
Description
2
IN
3
GND
Ground Pin
4
GND
Ground Pin
5
GND
Ground Pin
6
7
OUT
Output Pin
GND
Ground Pin
8
GND
Ground Pin
Ground Pin
Input Pin
This device contains Circuitry to protect the inputs against damage
due to high static voltages or electric fields. However. It is advised that
normaf precautions be taken to avoid appHcatlon of any voltage higher
than maximum raled voltages to thls high IlT1)8dance circuit.
1991 by FWITSU LIMITED
5-3
F5CB Series
STANDARD FREQUENCIES
Number
Model
System
Use·
Center Freauency
(MHz
Bandwidth
(MHz)
1
FSCB-836MSO-G201
AMPS/EAMPS
Tx
836.S
25
2
FSCB-881 MSO-G201
AMPS/EAMPS
Rx
881.S
2S
3
FSCB-888MSO-G201
ETACS
Tx
888.S
33
4
FSCB-933MSO-G202
ETACS
Rx
933.S
33
S
FSCB-902MSO-G201
NMT
Tx
902.S
25
6
FSCB-947MSO-G201
NMT
Rx
947.S
25
7
FSCB-911 MSO-G201
NTACS
Tx
911.S
27
8
FSCB-8S6MSO-G201
*Tx = Transmitter; Rx = Receiver
NTACS
Rx
8S6.S
27
TEST CIRCUIT
®
®
Each value is changed according 10 specHicalion
5-4
F5CB Series
ELECTRICAL CHARACTERISTICS - EXAMPLES
Example 1. AMPS Specification (Tx)
Pan Number FSCB-836M50-G201
Ta = -30 to 70°C
Rating
Item
Insertion Loss
Symbol
IL
In-band Ripple
Typical
Maximum
Unit
-
3.5
dB
1.0
4.2
1.5
20
25
-
dB
869 to 894 MHz
20
25
-
dB
894 to 3000 MHz
15
20
-
dB
824 to 849 MHz
-
1.7
2.0
824 to 849 MHz
DC to 800 MHz
Absolute
Out-of-band
Attenuation
In-band VSWR
Matching Constants
Minimum
Condition
824 to 849 MHz
dB
C1
7
-
pF
l1
9
nH
C2
6
l2
11
-
pF
nF
Example 2. AMPS Specification (Rx)
Pan Number FSCB-881MSQ-G201
Ta = -30 to 70°C
Rating
Item
Insertion Loss
Symbol
Minimum
Maximum
Unit
-
4.5
dB
-
1.5
dB
dB
Typical
-
DC to 824 MHz
20
824 to 849 MHz
917 to 939 MHz
20
18
947 to 1049 MHz
30
-
1049 to 3000 MHz
15
-
-
869 to 894 MHz
-
1.8
2.0
C1
6
-
l1
7
~
7
~
9
In-band Ripple
Absolute
Out-of-band
Attenuation
In-band VSWR
Matching Constants
Condition
824 to 849 MHz
IL
869 to 894 MHz
-
-
dB
dB
dB
dB
pF
nH
pF
nF
Continued on next page
5-5
F5CB Series
ELECTRICAL CHARACTERISTICS - EXAMPLES (Continued)
Example 3. ETACS Specification (Tx)
Pan Number F5CB-888M50-G201
Rating
Item
Insertion loss
Minimum
Typical
Maximum
Unit
872 to 900 MHz
-
4.5
5.0
dB
900 to 905 MHz
-
5.5
6.5
dB
872 to 905 MHz
-
-
2.5
dB
DC to 847 MHz
20
25
dB
847 to 860 MHz
8
12
-
917 to 920 MHz
10
13
-
dB
920 to 922 MHz
13
15
dB
922 to 950 MHz
20
23
962 to 995 MHz
30
33
995 to 3000 MHz
15
20
-
872 to 905 MHz
-
2.0
2.5
C1
7
II
7
-
Symbol
IL
In-band Ripple
Absolute
Out-of-band
Attenuation
In-band VSWR
Matching Constants
Condition
C2
6
l2
9
dB
dB
dB
dB
pF
nH
pF
nF
Continued on next page
5-6
F5CB Series
ELECTRICAL CHARACTERISTICS - EXAMPLES (Continued)
Example 4. ETACS Specification (Ax)
Pan Number FSCB-933M50-G201
Rating
Item
Insertion Loss
Symbol
IL
In-band Ripple
Absolute
Out-of-band
Attenuation
In-band VSWR
Matching Constants
Condition
Minimum
Typical
Maximum
Unit
917 to 947 MHz
-
4.5
5.0
dB
947 to 950 MHz
5.5
6.5
dB
917t0950MHz
-
1.0
2.5
dB
DC to 872 MHz
20
25
dB
872 to 900 MHz
15
18
900 to 902 MHz
13
15
-
902 to 905 MHz
8
13
-
dB
962 to 965 MHz
10
15
dB
965 to 970 MHz
15
18
970 to 995 MHz
20
25
1005 to 1040 MHz
30
33
1040 to 3000 MHz
15
20
-
917 to 950 MHz
-
20
2.5
dB
dB
dB
dB
-
C,
6
L,
6
pF
~
7
-
pF
L2
8
-
nF
-
nH
Example 5. NMT Specification (Tx)
Pan Number FSCB-902M5O-G201
Rating
Item
Insertion Loss
Symbol
Minimum
Typical
Maximum
Unit
890 to 915 MHz
-
4.0
4.5
dB
890 to 915 MHz
-
1.3
2.0
dB
DC to 850 MHz
20
25
dB
850 to 870 MHz
15
22
-
935 to 960 MHz
20
28
1012 to 1058 MHz
30
33
1058 to 3000 MHz
15
20
-
890 to 915 MHz
-
1.5
2.0
C,
5
L,
6
-
IL
In-band Ripple
Absolute
Out-of-band
Attenuation
In-band VSWR
Matching Constants
Condition
~
6
~
9
-
-
dB
dB
dB
dB
pF
nH
pF
nF
Continued on next page
5-7
F5CB Series
ELECTRICAL CHARACTERISTICS - EXAMPLES (Continued)
Example 6. NMT Specification (Rxl
Pan Number F5CB-947M50-G201
Rating
Item
Insertion loss
Symbol
Condition
Minimum
lYplcal
Maximum
IL
935 to 960 MHz
-
4.0
4.5
dB
935 to 960 MHz
-
1.3
2.0
dB
-
dB
In-band Ripple
Absolute
Out-of-band
Attenuation
In-band VSWR
Matching Constants
Unit
OCto 890 MHz
20
25
890 to 915 MHz
18
22
980 to 1005 MHz
18
30
1012 to 1058 MHz
28
32
1089 to 1115 MHz
30
32
-
dB
1115 to 3000 MHz
15
20
-
dB
-
1.5
2.0
-
6
nH
7
-
9
-
nF
935 to 960 MHz
C,
-
L,
-
6
dB
dB
-
dB
pF
C:!
-
L2
-
-
Symbol
Condition
Minimum
Typical
Maximum
Unit
IL
898-925 MHz
4.0
4.5
dB
898-925 MHz
-
1.5
2.0
dB
DC-815 MHz
25
27
-
dB
815-870 MHz
22
25
dB
Out-of-Band
1008-1100 MHz
30
33
Attenuation
1100-3000 MHz
15
20
-
-
1.8
2.0
-
6
-
7
-
10
pF
Example 7. NTACS Specification (Txl
Pan Number F5CB-911M5D-G201
Specification
Parameter
Insertion loss
In-band Ripple
Absolute
In-band VSWR
Matching Constants
898-925 MHz
C,
-
L,
-
C:!
L2
-
-
5
-
dB
dB
pF
nH
pF
nH
Continued on next page
5-8
F5CB Series
ELECTRICAL CHARACTERISTICS - EXAMPLES (Continued)
Example 8. NTACS Specification (Rx)
Part Number F5CB-856M50-G201
Ta = -30 to 70·C
Specification
Symbol
Condition
Minimum
Typical
Maximum
Unit
Il
843-870 MHz
-
4.0
4.5
dB
843-870 MHz
-
1.5
2.0
dB
OC-814 MHz
22
25
-
dB
Absolute
898-935 MHz
22
25
-
dB
Out-of-Band
935-11 00 MHz
30
33
-
dB
Attenuation
1100-3000 MHz
15
20
-
dB
843-870 MHz
-
1.8
2.0
-
-
7
-
pF
-
8
nH
-
-
7
-
Parameter
Insertion Loss
In-band Ripple
In-band VSWR
C,
Matching Constants
L,
C:!
L2
9
pF
nH
5-9
F5CB Series
Below is an example of the AMPS-Tx filter input and output characteristics with compensating l&C components.
Input with Land C In 50 n environment
CH1S11
1 UFS
AMPSTX
2: 51.7890
F5CB-836M50-G201
4.2305 0 793.05 pF
log MAG
CH1 1i21
5d3J
849.000 000 MHz
50.4220
·20.3670
Cor
Del
Y- I-...
824.000 000 MHz
2: -3.5565 dB
849 MHz
2
Cor
Del
!\
{
Hid
Hid
1:-3.6053 dB
REFOdB
I
".,
If!,
J
l~
"'-
I
\.1
\
'V
1\
I \
~
CENTER
835.000 000 MHz
SPAN 200.000 000 MHz
CENTER
Output with Land C In 50 n environment
CH1S22
1 UFS
AMPSTX
2: 22.7460
F5CB-836M50-G201
Del
log MAG
-4.4521 n 43.383 pF
5 dBl
824.000 000 MHz
76.0860
2.88050
Cor
1 : -3.6053 dB
REFOdB
!31- -...
24.00\> 000 ¥HZ
2:-3.5565 dB
849 MHz_
2
Cor
Del
1\
I
Hid
Hid
I
".,
~f'
,
I~
J
I
"'-
V
'V
\
1\
I \
\
CENTER
5-10
835.000 000 MHz
I'
SPAN 200.000 000 MHz
835.000 000 MHz
SPAN 200.000 000 MHz
CENTER
835.000 000 MHz
r
SPAN 200.000 000 MHz
F5CB Series
PART NUMBER DESIGNATION
Designation Example
F5CB
-000000
-Gooo-o
------'
)-
o
1.0
2.0
3.0
4.0
5.0
Control Voltage (V)
Oscillation Frequency: H
0.5
..---. ..---A
0.4
l
0.3
I!l.
0.2
ii
0.1
~
0
"
~.1
tij
i
----
.----- -----
----
18.432 MHz
)--
)/
~.5 0
1.0
2.0
3.0
4.0
5.0
Control Voltage (V)
5-29
M2 Series (0300)
STANDARD CHARACTERISTICS
1C. Control Voltage and Oscillation Frequency Changes
Pan Number: M2SCo24M576-D300
Oscillation Frequency' L
0.5
0.4
l
t
ii
0.3
0.2
0.1
I -O~
.g
-0.2
J!
-0.3
o
-0.4
'0
.----':>-
y-
~
-0.5 0
---' ~
v-'
16.384 MHz
--' >--
;>-
1.0
2.0
4.0
3.0
5.0
Control Vottage (V)
Oscillation Frequency' M
0.5
0.4
l
0.3
'"cto
..c:
0.2
0.1
0
CD
u
is'
c
CD
I"
5
'iI
'ii
0
.--'
.....---"-
-0.1
22.579 MHz
..-< \--
-0.2
-0.3
-0.4
-0.5
.-< \ -
~
~
o
~
y
2.0
1.0
3.0
4.0
5.0
Control Vottage (V)
Oscillation Frequency: H
0.5
0.4
l
'"fa
CD
ii
is'
Ii
6-
0.3
0.2
0.1
0
------"y
-0.1
-0.2
J!!
-0.3 ) -0.4
~
-0.5
,--
24.576 MHz
o
,..---'
1.0
2.0
3.0
Control Vottage (V)
5-30
l--
..-1.\--
~
c
.g
..-'
.-J.
~;r-
4.0
5.0
M2 Series (0300)
2. Oscillation Spectrum
Part Number: M2SC-18M432-D300
Example of 103 = 18.432 MHz
REF-IOOdBm
AlTIOdB
MKR
IOdBI
184334 MHz
-IO.OdBm
SPAN
200kHz
\
RBW
3kHz
I
II
VBW
3kHz
-
SWP 100 ms
\
\
~l
d
~,UJ .•
I
SPAN 200 kHz
""'I"'"'"
CENTER 18.434 MHz
RBW= 3 kHz
SPAN = 200 kHz
RBW=300Hz
SPAN = 20kHz
3. Frequency Switch Oscillation Startup Characteristics
The characteristics in the circuit below were measured with Vcc = 5.0 V and VFC = 5.0 V.
Condition: Vcc=5.0V
VIN = 5.0 V
Fo
PG
M2SC-18M432-D300
Fl
~
Oscilloscope
5-31
M2 Series (0300)
4. Frequency and Switching Oscillation Stanup Characteristics
A. Condition: SlOp ~ 12.288 MHz
Stop ~ 12.288 MHz
2 Vlav
2J.1SIdiv
10J,1S
B. Condition: Stop ~ 16.934 MHz
Stop ~ 16.934 MHz
2 Vldiv
2J.1SIdiv
llJ,1S
C. Condition: Stop ~ 18.432 MHz
Stop ~ 18.432 MHz
2V1dv
2J.1SIdiv
10J,1S
5-32
M2 Series (0300)
PART NUMBERING SYSTEM
(Part Number Example)
M2SC-DDDDDD
(i)
(i)
®
-0
DOD
®
Frequency designation: Designates the highest frequency of the combined nominal frequency types in six alphanumeric
characters. M indicates the decimal point in MHz.
Serial numbers of the series:
Standard for the M2 series (0300): 0300
MARKING
Part Number
Indication
Company Symbol
Lot Indication
DIMENSIONS
8.0 max. (0.315)
-0-
43.0 max. (1.693)
0.4(0.016)
1 (0.039.:...)*-t-(.i.;~)
16
(0.630)
Units: mm (in.)
5-33
M2 Series (D300)
5-34
00
FUJITSU
October 1990
DATA SHEET
M3 Series (D001)
Piezoelectric Device
(Voltage Controlled Oscillator)
The M3 series voltage controlled oscillators (VCO) operate in the frequency range of
50 to 300 MHz. The M3 series VCOs use a single LiTa03 (I~hium tantalate)
piezoelectric crystal with a high electromechanical coupling coefficient and a SAW
resonator that has an original configuration. The M3 series VCOs oscillate directly in
the VHF band up to 300 MHz. and have a wide variable frequency width and high
temperature stabil~y.
•
Direct oscillation at high frequencies: 50 to 300 MHz
•
Wide variable frequency width: 800 ppmN minimum (0.5 to 4.5 V)
•
Superb temperature characteristics: Within ±200 ppm (0 to 60°C)
•
High-precision oscillation frequency, ready for use without adjustment
•
High reliability due to hermetically sealed package
•
High carrier noise ratio: -90 dB or less (12.5 kHz detuning, 8 kHz band)
•
Compact size: Compatible w~h 16-pin DIP IC packages
•
Frequency offset by built-in offset terminal
•
Three types of standard frequencies available
Metal Case
DIP-16
(Bottom View)
Symbol
Ratings
Unit
Vee
-0.5 to 7.0
V
Input Control Voltage
VIN2
-0.5 to 7.0
V
T.
Storage Temperature
TSTG
Control Polarity
Ot060
°C
-40 to 85
°C
50 to 300
MHz
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Ratings
Description
7
VINI
GND
8
VOUT
9
Vee
Offset Terminal
Grounding Terminal
Oscillation Output
Tenninal
Power Supply
Terminal
16
VIN2
Control Voltage
Input Terminal
Unit
Power Supply Vottage
Vee
5.0
V
Input Control Voltage
VIN2
0.5 to 4.5
V
Operating Temperature
T.
Ot060
°C
Note: Permanent device damage may occur ff absolute maximum ratings are
exceeded. Functional operation should be restricted to the conditions
as detailed in the operation sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
©
09
Terminal No. Terminal Name
1
Positive Polarity
Oscillation Frequency Range
B
0
16
Power Supply Voltage
Operating Temperature
0
0
ABSOLUTE MAXIMUM RATINGS
Parameter
7
1
0
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
fields. However, it is adllised that normal precautions
be taken to avoid application of any voltage higher
Ihan maximum rated voltages to Ihis high impedance
circuit.
1990 by FUJITSU LlMITEO
5-35
M3 Series (D001)
STANDARD FREQUENCIES
Frequency
Part Number
Application
74.25 MHz
Professional HDTV
M3DA-74M250-DOO1
97.2 MHz
Transmission Standard HDTV
M3DA-97M200-DOO1
115.52 MHz
Broad-band ISDN
M3DA-155M52-DOOl
ELECTRICAL CHARACTERISTICS
Ratings
Minimum
"lYplcal
MaxImum
Unit
VIN2 = 2.5 V
-500
-
+500
ppm
V IN2 -O.5 V
VIN2 = 4.5 V
800
-
-
ppmN
f.
~f(Ta)
VIN2=2.5 V
-200
-
+200
ppm
25°C reference,
Ta=Oto60OC
POUT
V IN2 = 2.5 V
0
5
7
dBm
50
Output Level Stabil~y
~P(VF)
VIN2 =0.5 V
VIN2=4.5V
-2
-
+2
dB
V 1N2 -2.5V
reference
Output Level Temperature
Stabil"y
~P
VIN2=2.5V
-2
-
+2
dB
25·C reference,
Ta - 0 to 60·e
-
-
30
rnA
V 1N2 = 2.5 V
-50
-
+50
ppm
Item
Symbol
Oscillation Frequency Deviation
~f.
(fH-fd
Variable Width of Oscillation
Frequency
Temperature Stability of
Oscillation Frequency
Output Level
Current Consumption
(Tal
lee
Oscillation Frequency Power
Supply Vottage Fluctuation
~f (Vccl
Condition
STANDARD CHARACTERISTICS
The examples below show characteristics of the M3 VCO devices at 155.52 MHz.
Example 1. Frequency Variable Characteristics
+0.3
r------------------------------------,
+0.2
~
G>
'iii
a:
+0.1
G>
C>
c:
::J
-0.1
0
~
c:
a~
u..
-0.2
+0.3
o
2
3
4
Control Vottage (V)
5-36
5
6
Remarks
f. reference
n termination
Vee =5 V reference,±5%
M3 Series (D001)
STANDARD CHARACTERISTICS (Continued)
Example 2. Temperature Characteristics
+250
r-------------------------------------------------------,
+200
E
Co
+150
.
a:
.
+100
OJ
.r;
-50
.s.
tii
D>
C
+50
0
0
(j -100
.
-150
£
-200
c
::>
e
'5<
.
U
Uoooooo
:::0-
8~
1~:
@o
~
I
(
--
1jIO.5 (0.020)
@-
(Rear)
q
(Side)
~
00000
7.62±0.5
(0.300 ± 0.020)
~
~
---0
~
1~I ~
-I[
8
o
•
+1
0
+1
&t.!
0
q
II
0
+1
.....
- " ' - - +1'"
0
~
&d
e-
o
...0+1
Units: mm (in.)
5-38
cP
FUJITSU
October 1990
DATA SHEET
M3 Series (D101)
Piezoelectric Device
Modulator, 50 MHz to 300 MHz
These piezoelectric modulators feature direct oscillators (50 MHz to 300 MHz). The
piezoelectric modulator uses a lithium tantalate piezoelectric single crystal (uTa03)
wkh a high electromechanical coupling coefficient. The piezoelectric modulator
employs an exclusive SAW resonator. The piezoelectric modulator can be used in
direct modulation applications needing high modulation sensitivky and a high
signal-to-noise ratio in the VHF band (up to 300 MHz).
•
High frequency direct modulation:
50 to 300 MHz
•
High modulation sensitivky:
800 ppmN min. (0.5 to 4.5 V)
•
Excellent modulation distortion ratio: 40 dB max. (1 kHz to 1.75 kHz dev.)
•
Excellent signal noise ratio:
•
Excellent temperature characteristic: ±200 ppm max. (-20 to 70°)
•
Highly reliable hermetically sealed package
•
Compatible with 14-pin DIP Ie packages
~t:>~~
~~\~
~~
Matelcasa
DIP-14
-50 dB max.
(Bottom View)
01
40
70
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Ratings
Unit
Power Supply Vo~age
Vee
-0.5 to 7.0
V
ML Pin Input Voltage
VML
-0.5 to 10
V
MM Pin Input Vo~ge
VMM
-0.5 to 7.0
V
ML Pin Modulation Polarity
Positive
MM Pin Modulation Polarky
Storage Temperature
To
-20 to +85
TSTG
-40 to +100
°e
ML
Description
Control Voltage
Input Terminal
4
MM
Modulation Input
7
GND
°e
RECOMMENDED OPERATING CONDITIONS
Paramater
80
~ermlnal No. Termine! Name
1
Negative
Operating Temperature
014
Symbol
RatIngs
Unit
Power Supply Vo~age
Vee
4.75 to 5.25
V
ML Pin Input Vo~age
VML
2.5
V
Operating Temperature
To
-20 to 70
°e
Note: Permanent device damage may occur if absolute maximum ratings are
exceeded. Functional operation should be restricted to the condkions
as detailed in the operation sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliabilky.
8
VOUT
14
Vee
Grounding Terminal
Oscillation Output
Terminal
Power Supply
Terminal
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
fields. However, it is advised that normal precautions
be taken to avoid application 01 any voltage higher
than maximum ratad voltages to this high impedance
circuit
© 1990bJFUJITSULlMrTED
5-39
M3 Series (D101)
STANDARD FREQUENCY
Standard Frequency
Application
Part Number
145.0 MHz
Mobile Phone
M3DA-145MOO-D101
ELECTRICAL CHARACTERISTICS
(Vee =5 0 V)
Ratings
Min.
Typ.
Max.
Unit
6.f.
VIAL = 2.5 V
-300
-
+300
ppm
(fH-fd
V UL = 0.5 V
VIAL =4.5 V
SOO
-
-
ppmN
fo
6.f (Ta)
VUL = 2.5 V
-200
-
+200
ppm
25°C reference,
Ta - -20 to 70°C
POUT
VUL = 2.5 V
-5
-3
-1
dBm
50 n termination
Output Level Stability
6.P (VF)
VUL = 0.5 V
VuL =4.5 V
-2
-
+2
dB
VUL=2.5V
reference
Output Level Temperature
Stability
6.P (Tal
VuL =2.5 V
-2
-
+2
dB
25°C reference,
Ta - -20 to 70°C
-
-
10
rnA
-50
-
+50
ppm
1.75 kHz DEV
-
-
-40
dB
3.5 kHz DEV
-
-
-40
dB
5.0 kHz DEV
-
-
-40
dB
1.75 kHz DEV
-
-
-50
dB
hem
Symbol
Oscillation Frequency Deviation
Variable Width of Oscillation
Frequency
Temperature Stability of
Oscillation Frequency
Output Level
Current Consumption
lee
Oscillation Frequency Power
Supply Vo~age Fluctuation
6.f (Vcc)
Modulation
Distortion
(1 KHz tone)
Modulation
Characteristic
Signal to
Noise Ratio
Modulator
Input Impedanc
Condition
VUL =2.5 V
10
Remarks
fo reference
±5%at Vee =5
V
reference
15 kHz LPF
300 to 3 kHz
Kn
PART NUMBERING SYSTEM
Designation Example
M3DA-000000 - DODO
CD
5-40
®
CD
Frequency Designation:
The standard frequency is designated in six alphanumeric characters. M is used to
designate the decimal point in MHz. Refer to STANDARD FREQUENCY.
Example: 145.0 MHz device is designated as 145MOO.
®
Serial Number:
The serial number is assigned from 101 to 199 (with 101 as the standard).
M3 Series (D101)
PACKAGE MARKING
(Bottom View)
Fujitsu logo
Part Number
\
~r.J...
-F
/
SV-145M
0 101
0
~
t
:/
lolnumber
Index
PACKAGE DIMENSIONS
Units: mm (in.)
152 (0 598)
I
I
@1
I-
4~~
7@
i
"t
-.:r
13.1max.
(0.51 6)
7.6
9
@14
8@,
)
1
208 max. (0.819)
18.3 (0.720)
.
I
I
1
r~r===;t::==:::::;:;:=l~__ (0.197)
5.0
6.3
(0.248)
~
5-41
M3 Series (0101)
SAW MODULATOR CHARACTERISTICS
M30A-145MQO-0101
Hem
Characteristics
Rating
Output Frequency
145.0 MHz
144.997 MHz
Current Consumption
lOrnA or less (w~h buffer)
7.3 rnA
Output Level
-3 dBm ±2dB
-2.00dBm
Spurious Response Ratio
Frequency
Stabil~
Higher harmonic < 4 dB at 2 fo (290 MHz)
-7.3 dB
Power Supply
Fluctuation
W~hin ±50 ppm for 5 V ±0.25 V
+6.00 ppm
-5.80 ppm
AFC-F-F
Characteristic
±550 ppm or more for 2.5 V ±1 V
-789 ppm
+1016 ppm
Temperature
Characteristic
W~hin
+66 ppm
+41 ppm
AFC Voltage Versus Output
Frequency Characteristics
Modulation
Input Level
±300 ppm for -35 to +85
At 25 ±SoC, the AFC vokage for the output frequency
of 145 MHz is Vc = 2.5 V +0.3 V
At -20 +85°C, the AFC vokage for the output
frequency of 145 MHz is Vc = 2.5 V +0.3 V
Signal Noise
Characteristic
-28 dBm ±3 dB (600 W)
1 KHz +3.5 kHz OEV*
-20°C
+85°C
-26.1 dB
15kHz LPF
-46 dB
-49 dB
-48 dB
15kHz LPF
< ±1 dB120 Hz to 5 kHz ±5 kHz OEV*
-55 dB
< -50 dB ±1. 75 kHz OEV"
Test Circuit
Vee
Modulation
Analyzer
HP8901B
8
14
OUT
Audio Analyzer
HP8903B
5-42
vc= 2.5 V
2.476 V
2.459 V
• Adjust the control voltage for an oscillation frequency of 145 MHz for the modulation characteristic.
Vc
vc=2.5V
2.501 V
-35 dB or less 1 kHz (±1.75 kHz OEV)*
Modulation
Oistortion Ratio -30 dB or less 1 kHz (±3.5 kHz OEV)*
-20 dB or less 1 kHz (±5.0 kHz OEV)*
Modulation
Modulation
Characteristic Characteristic
Remarks
300103 kHz
M3 Series (0101)
M30A-145MOO-D101 MODULATION FREQUENCY CHARACTERISTICS
/
N
/
~~-------------;----/T---------------------~
~~-------------4---/+-----------------------~
I
I
~
r
_________ ~ __~~/J__________________________-;
~---------o--~~--------------------------~
z
~============~~======================~
~==============~§========================~
~==========~~==================~
~------m-------+--------------------------~
"0
•
••
~===~c:~~~=t==~====================~
I-------~- " + - o - I - C ) l - - - - - - - - - - - - - - - I
5-43
M3 Series (D1 01)
SAW MODULATOR CHARACTERISTIC DATA
M3DA·145MOO-D101
No. ES-380
0
,
-1
+- -
-2
--3
-4 Output Level
(dBm)
-5
-6
-7
0 . 6 1 - - - - - - - - - - - - - - - - - - - - - - - - - 1 -8
0.5
,
--+-,
+--+--
0.4
+--+--
0.3
,
,
0.2
Oscillation
Frequency
Variation
(%)
,
0.1
,
,
+--+--
01--------;:1<:::..-----------------1145.00 MHz
,
-0.1
+--+--
,
,
+ - - ... - . - ... - -
-0.3
..........
,
,
,
+--+--
V-F Characteristic
,
+ - - + - - + - - + - ...
,
-0.2
Control Voltage, Vc (V)
5-44
,
+--+--
M3 Series (0101)
SAW MODULATOR CHARACTERISTIC DATA (Continued)
M3DA·145M()()"D101
No. ES-38 0
,
2
Output Level
Fluctuation
(dB)
- - + - -
0
-1
-2
500
400
300
200
Oscillation
Frequency
Variation
(ppm)
100
:-0
0
-100
-200
-300
-400
-500
-40
Frequency
Variation
(ppm)
100
80
60
40
20
-30
+20
-10
o
10
20
30
40
,
,
+--
+-- +--
50
60
,
70
80
90
Temperature (OC)
Temperature Characteristic
0
-20
-40
-60
-80
-100 4 .7
5-45
M3 Series (0101)
5-46
Section 6
Cordless Telephone Integrated Circuits -
I Page
Device
Description
At a Glance
Package
Options
MB86460A
Modem with Internal Voice-Band FUters
48-pin
Plastic
FPT
MB87002
CMOS 1200 bps MSK Modem
16-pin
Plastic
DIP, FPT
6-1
Cordless Te!ephooelateqrated Circuits
6-2
Telecommunications Data Book
00
May 1991
Edition 1.0
FUJITSU
DATA SHEET
MB86460A
MODEM WITH INTERNAL VOICE-BAND FIL TERS
CMOS MODEM CIRCUIT WITH INTERNAL VOICE-BAND
FILTERS FOR CORDLESS TELEPHONES
The MB86460 MSK (Minimum Shift Keying) modem IC contains a 1200-band MSK
modem and voice-band filters.
The voice-band filter consists of transmit and receive bandpass filters,
pre-emphasislde-emphasis, and splatter filters arranged in an SCF configuration. In
addition, a limiter circuit is included.
The MB86460 operates at low voltage (3.0 to 5.5 V) and is suitable for cordless
telephone applications.
•
•
•
•
On-chip voice-band filters and 1200-band MSK modem
Low supply voltage requirements (3.0 to 5.5 V)
Wide operating temperature range (T. = -20 D C to 700C)
Standby function for low power consumption
•
•
•
•
•
•
•
•
•
MSK frame detection
Frame synchronization selectable
Full-duplex MSK modem
Transmit/receive muting
Externally adjustable receive and transmit gain
Externally adjustable limiter level
CarrierNnterference detection circuit
The on-chip oscillator operates with 3.6864 or 3.456 MHz crystal (selectable).
The on-chip serial interface reduces the number of signailines
• CMOS 1/0 interface
PLASTIC PACKAGE
(FPT·48P·M02)
PIN ASSIGNMENT
(TOP VIEW)
This device oontains circuitry 10 protect the inputs against damage
due to high static voltages or eJedric fields. However. It Is advised
that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to this high irJ1)8dance circuit.
Copyr~ht"1991 by FUJITSU LIMITED
6-3
MB86460A
PIN DESCRIPTION
Power
supply
pins
Input pins
5
AF,••
7
112 Voo,.
10
DEM,
21
DET,.
23
Input to the 112 Voo generator. A 1 IJ.F bypass capacttor is usually connected from
this pin to analog ground (pin 41)
Reference voltage input to the tone detector. Wnh this pin open. the reference vottage
level is 1/100 VDD.
Input for pattern check mode selection
When TEST is low, an internal pattern is loaded into the shift register on the rising edge
of DCK. When TEST is high. data at DIN is loaded into the shift register ans data in the
shift register is shifted out to DO"T on the rising edge of DCK. This pin is pulled by up a
A high on the SEND line enables data
6-4
MB86460A
A 0.1 !LF capacitor is connected
4
AF'.2
Output of input transmit amplifier. The transmit input gain is adjusted with external
registors connected to this pin and pin 5 (AF,.,).
6
112 VDDoUT
Output of the 112 Voo reference. Internal circuit operation is referenced to the voltage on
this pin.
11
DEM2
Output of receive input amplifier. The receive input amplifier gain is adjusted with
external resistors connected to this pin and pin 10 (DEM,).
20
COUT
Output of tone detector. An external 0.1 !LF capacitor is connected from this pin to
ground complete the internal primary lPF configuration.
22
DETouT
Tone detector output. DETOUT is high when the input to the tone detector (rms value)
exceeds the reference voltage.
25
DOUT
Patter~k setting output
When TEST is high, the rising edge of DCK triggers output of the pattern.
30
FDouT
Frame detection circuit output. FDOUT goes high when a signal matching the frame
synchronization pattern is output from RD after a reset.
iii
Output pins
6-5
I
~
to
r0O
o
"c5>
As
G)
.CMPani. EMPour .I. SarrR'.1. SAM"'.
:rJ
l>
i:
t---06MOO
C, R,
fc-.31< lc';;;-20K
fe.l0K
~~~'====~:I~M~~U_~~
SENOF
•
____,
To..
r-----O 112VOo...
1I2VDDI,~
esc..
1::1
osCour
L-J
b'
0.1
ce.
~!
:~~~
RAM~t'; R1D I RAMPour
R.
DTMF and tone signals
i'F
i:
OJ
i
!
MB86460A
CIRCUIT FUNCTIONS
The MB86460 consists of the transmit fitters, receive fitters, MSK modulator, MSK demodulator, digital circuits, and tone detector.
1. Transmit filters
The input amplnier AMP1 controls the gain of the transmitted VF signal. Gain is adjusted with external resistors R1 and R2. The
input signal is then band-limited to 3.7 kHz or less by the transmit filter LPF1. The signal is then output at CMP 'N to an external
compressor. We recommend forming an RC filter using extemal resistor RI, and external capacitor CI.
The compressor output signal is input to filter HPF2 at CMPOUT for 6 dB/octave pre-emphasis. The pre-emphasis filter can be
bypassed externally.
The pre-emphasis filter output is brought out at EMPOUT to the external summing network 01 summing amplnier AMP2, where the
signal is summed with the MSK modulating signal. The Signal then enters the limiter. The limiter level can be adjusted externally at
the LIM pin.
The output of the limiter is then band-limited to 3 kHz by splatter fitter LPF2 and output at the MOD pin. the transmitted VF signal can
be muted externally.
2. Receive filters
Input amplifier AMP3 controls the gain of the received VF signal. Gain is adjusted by external resistors R3 and R4. The input signal is
then band-limited to 0.23 kHz to 3.4 kHz by receive filters LPF4 and HPF3. The signal then enters fitter LPF5, where the 6 dB/octave
pre-emphasis is removed. The de-emphasis filter can be bypassed externally.
The output of the de-emphasis fitter is brought out to the EXP,N pin to an external expander. The expander output is then input to
summing amplifier AMP4, where the signal is summed with tone, DTMF, or other signal. The signal is then output at RAMPOUT. The
receive VF signal can be muted externally.
3. MSK modulator
In the MSK modulator, a 1200-Hz (data 1) or 1800-Hz (data 0) sine-wave signal is generated for data input to pin SO in
synchronization with transmit clock SCK. The MSK modulator signal then passes through pin SOUT and enters summing amplifier
AMP2, where the signal is summed with the transmit VF signal.
4. MSK demodulator
The received MSK signal passes through receive input amplnier AMP3. The signal then enters BPFl , where frequencies other than
1200 and 1800 Hz are eliminated. The signal passes through waveform-shaping circuit 1 and is AID converted. The signal then
enters the delay detector, where data is regenerated. The noise components in the regenerated data are fittered out by LPF3 and
then the signal enters waveform-shaping 2, where AID conversion is done again.
The digital phase-locked loop (DPLL) circuit recovers receive clock RCK from the regenerated data signal and outputs the
regenerated data at the RD pin.
The MB86460 has a buitt-in frame-detection function for reducing microprocessor load. When the regenerated data output from pin
RD matches the frame synchronization pattern, FDOUT goes high. The frame synchronization pattern can be set externally.
5. Digital circuits
The digital circuits consist of the timing generator and serial interface. The timing generator generates basic clocks for the MSK
modulator and demodulator, transmit f!Hers, and receive filters, and consists 01 a 3.6864-MHz crystal and an on-chip oscillator and
divider circuits.
The signal interface is used to set the standby mode, the bypass mode, and the frame synchronization pattern, and to enable or and
disable the tra.!!.smitlreceive mute function. These operations are microprocessor-controllable through serial signal lines D,N, DCK,
DSTB, and FIM.
6. Tone detector
The tone detector is used for interference or carrier detection during demodulation. The tone detectorfull-wave-rectnies the output of
the receive LPF or demodulator BPF, smoothes the signal, and compares it with the reference to check for interference or carrier
presence.
6-7
MB86460A
FUNCTION DESCRIPTIONS
1. Timing chart for the 1200-bps MSK modem
1. Modulation
RST
..J
SEND
SCK
o
SD
SO
2. Demodulation
RST
J
o
o
o
o
DEM1
RD
RCK
3. Frame detection
FCL
RST
.
:;"'~I---- Frame synchronization pattern (selectable) - - - -..
IO;.:~ Receive data -
RD
.
L
o•
•
RCK
FDoUT _ ....._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1
6-8
L
MB86460A
2. Limiter
Voo
VOO
-0.25>V,
-0.25
1 - - = - - - - - - - - - + - . . . . . . : : = - - - - - - - - - 1 LIM pin is open.
"2
"2
VDO
VDO
"2 - 0.25 !> V,!> "2 + 0.25
V,
I - - = - - - - - - " - - - - + - - V O - O - - - - - - - - l Von = 5.0 V
\'00
"2
+ 0.25 < V,
VUM> v,
2
+ 0.25
VUM
V,
VUM!> V,!> V,- VUM
LIM pin = VLI.
r-----------------~--------------~
Voo- VUM
Voo- VUM < V,
3. Microprocessor interface (mode selection)
The serial interface selects the standby mode and mute mode.
CD Data input timing (TEST is high, FiM is low)
DCK
015: MSB
DIN
DO: LSB
DSTB
The serial pattern is valid.
6-9
MB86460A
FUNCTION DESCRIPTIONS
@ Data setting
On reset, 015 to 03, 01, and DO are sella 0, and 02 is selto 1.
6-10
MB86460A
• Standby mode
(02,01, DO)
L-~_...l---I
Transmit
system
Mode selection (Mn): n indicates values
in binary notation for 02 (MSB) to DO (LSB).
Voice-band
filters
Receive
system
MSK
MODEM
Others
Note: During reset, mode M4 is set.
o ....
Active
X .... Powered down
6-11
MB86460A
FUNCTION DESCRIPTIONS
• Mute mode
(04.03)
1.--_-./ Receive mute selection
Active
Muted
SW1
Used
Bypassed
SW3
• Pre-emphasistde-emphasis bypass mode
(06.05)
1.--_-./ Oe-emphasis bypass selection
• Compander bypass mode
(07)
6-12
MB86460A
• Tone detector mode
(08)
>--.....-\ Postfilter 3
Tone
detector
a
o
LPF4
Receive filters
• Crystal oscillator mode
(09)
Note: The internal dividing ratio depends on the frequency of the crystal.
• Test mode
(015 to 010)
Digital test selection
Normal
Test
Analog test selection
Normal
Test
don'teare
For expansion
Note: In no-test (normal operation) mode, set 012 and 013 to O.
6-13
MB86460A
FUNCTION DESCRIPTIONS
4. Setting the frame synchronization pattern
The frame synchronization pattern is set via the serial interface pins. (16 bits)
For strobe, use DSTB and set FiM to high.
--
-
Data input timing (TEST is high, F/M is high)
DCK
D15: MSB
DIN
DO: LSB
DSTB
The pattern is loaded internally.
6-14
MB86460A
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Supply voltage
Voo
Voo
GND-O.3
7
V
Input voHage
Y,N
All input pins
GND-O.3
VDo+O.3
V
Output voltage
VOIJT
All output pins
GND-O.3
VDo+O.3
V
Output current
loUT
All output pins
-10
10
mA
Storage temperature
T",
-40
125
·C
NOTE: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Supply voltage
Vo.
Vo.
Input voHage
Y,N
All input pins
Analog output load resistance
RL
All analog output pins
Analog output load capacitance
CL
All analog output pins
OSC pin load capacitance
Coec
OSC,N, OSCOUT
Operating temperature
T.
•
3.0 •
5.0
0
5.5
V
VDO
V
50
kn
30
pF
20
30
50
pF
-20
25
70
·C
The MB86460A operates down to 2.7 V, but electrical characteristics are not guaranteed from 2.7 V to 3.0 V.
6-15
MB86460A
ELECTRICAL CHARACTERISTICS
1. Transmit characteristics
VDD = 3.0 to 5.5 V, T. = -20 to 70°C
Transmn gain 1
Transmn mute
D
TM1lTE
AF.N.-MOD
Input: -27 dBV, 1 kHz
R.=R.,R,=R7
With pre-emphasis.
7.0
AF.N.-MOD
Input: -27 dBV, 1 kHz
R.=R•• R,=R7
With pre-emphasis.
Compander bypassed.
Transmit muted.
45
dB
40
dB
9.0
11.0
dB
Transmn
signal-to-noise
ratio
TSIN
AF.N.-MOD
Input: -27 dBV. 1 kHz
R.=R•• R,=R7
With pre-emphasis.
Compander bypassed.
Band: 50 Hz to 20 kHz
Receive gain
RG..N.
DEM.-RAMPOUT
Input: -26 dBV. 1 kHz
R3 = R•• Ra = R••
With de-emphasis.
-1.0
DEM.-RAMPo1lT
Input: -18 dBV. 1 kHz
R3 = R•• R. = R••
With de-emphasis.
Compander bypassed.
Receive muted.
45
dB
40
dB
Receive mute
6-16
TGAIN.
RM1lTE
0.0
1.0
dB
Receive
signal-to-noise
ratio
RSJN
DEM.-RAMPo1lT
Input: -18 dBV. 1 kHz
R3 = R4, R. = R••
With de-emphasis.
Compander bypassed.
Band: 50 Hz to 20 kHz
Transmn gain 2
TGAlN2
AF.N.-EMPOUT
Input: -27 dBV, 1 kHz
R. =R.
With pre-emphasis.
-1.0
0.0
1.0
dB
Transmn gain 3
TGAlN3
EMPour-MOD
Input: -27 dBV. 1 kHz
R,= R7
8.0
9.0
10.0
dB
Transmn frequency
characteristics
TF•
AF.N.-MOD
Input: -27 dBV
R. = R•• R, = R7
With pre-emphasis.
Shown in Figure 1.
MB86460A
Veo = 3.0 to 5.5 V. TA = -20 to 70°C
Receive frequency
characteristics
RFA
DEM,-RAMPOUT
Input: -26 dBV
R,=R•• Rs=R7
With de-emphasis.
Demodulator
BPFgain
BGA,.
DEM,-CC,
Input: -18 dBV.
1.5 kHz
R3= R.
Demodulator
LPF gain
lGA'N
CC,-CC3
Input: -18 dBV.
300 Hz
In test mode
Shown in Figure 2.
-1.5
0
1.5
-6.0
dB
dB
-30.0
Demodulator
BPF frequency
characteristics
BF•
DEM,-CC,
R3=R,
-3.5
-1.0
-3.5
dB
-30.0
Demodulator
LPF frequency
characteristics
LF•
CC,-CC3
Input: -18 dBV.
In test mode
3dB
Reduced
800
Hz
6-17
iii
MB86460A
ELECTRICAL CHARACTERISTICS
• 2. DC characteristics
Vee = 3.0 to 5.5 V, T. = -20 to 70°C
Supply current
Analog input resistance 2
kg
DET'N
RAIN2B
RAIN3A
Analog input resistance 3
Operating
Analog output load
resistance
RL
AF'N2, CMP'N, EMPouT,
SOUT, SAMPoUT, MOD,
DEM2, lIMouT, EXP'N,
RAMPouT
Analog output load
capacitance 1
CL1
AF'N2, CMP'N, EMPouT,
SOUT, SAMPoUT, MOD,
DEM2, lIMouT, EXP'N,
RAMPoUT
CL2
COUT
6-18
450
900
10
20
40
90
180
360
kQ
LIMN
RA1N3B
load
225
Between this pin
and 1/2 Vee
kQ
50
100
0.1
pF
!iF
MB86460A
Voo = 3.0 to 5.5 V, T. _ -20 to 70 ·C
Analog output
voHage range
AF,..., CMP,., EMPOUT,
SAMPouT, MOD,
OEM., EXP,., RAMPolIT,
LlMoUT
Modulator output
voHage
SOUT
Limiter high voHage
Limiter low voHage
Tone detection level
VOU!
Vou.
VDET
4
SAMPou,...LlM OUT
4
V
LIM pin = VUM
1I2Voo+O.S 112Voo+l.0 112Voo+l.2
x (ll2Voo- X (ll2Voo- x (ll2VooVUM)
VUM)
VUM)
V
The LIM pin
is open.
112Voo
-o.06Voo
V
LIM pin = VUM
1l2Voo-l.2 1l2Voo-l.0 1I2Voo-D.S
x (ll2Voo- x (1/2Voo- x (ll2VooVUM)
VUM)
VUM)
SAMPou,...LlMouT
DET,.
~Voo
..LVoo
R,=R.
pin is
open.
DET,.pin
= VOT
..L Voo
125
112Voo
-o.osVoo
..LVoo
100
112Voo
-o.04Voo
..LVoo
SO
1/12.Sx
1110x
l/8x
(lI2Vo.,...VOT) (lI2V_VOT) (1/2V_VOT)
V
V....
V....
6-19
D
MB86460A
ELECTRICAL CHARACTERISTICS
3. AC characteristics
Voo = 3.0 to 5.5 V, T. =-20 to 70·C
Digital input rise time
t.
RST, SEND, SO,
D'N, DCK, DSTB,
100
ns
100
ns
T'EsT FiM
RST, SEND, SO,
Digital input fall time
t.
D'N, DCK, DSTB,
T'EsT FiM
6-20
MB86460A
Von - 3.0 to 5.5 V,
T. = -20 to 70°C
6-21
MB86460A
TIMING CHART
CD MSK modem timing
RST VIH
VIL
SENOVIH
VIL
_+--+_____
SCK VOH
VOL
SO
VIH
VIL
_+-....._______11
SoUT
OEM,
OEM.
RO
VOH
-+_______-"
VOL _ _
RCK VOH
VOL
VOH
FOOUT VOL
® Serial interface timing
OIN
VIH
VIL
OCK VIH
VIL
OSTB VIH
VIL
TEST VIH
VIL
F/M VIH
VIL
OOUTVOH
VOL
6-22
(01)
X
(00)
MB86460A
TRANSMIT RECEIVE CHARACTERISTICS
Figure 1 Transmit frequency characteristics
-15.0
(JooHZ)~ (3500Hz)
-10.0
. / ~HZ)
-5.0
6dBlOCT
0.0
b
5.0
Attenuation
(dB)
10.0
15.0
20.0
~
~ ~HZ)
12dBlOCT
\
~
-'3dB
(3000Hz)
\ 36dBlOCT
~' /
V
./
11.5dB (300Hz)
~dB(100HZ)
25.0
30.0
0.1
0.2
0.4
0.8 1.0
Frequency (kHz)
2.0
4.0
\
\
\
\
\
8.010.0
Figure 2 Receive frequency characteristics
-15.0
-10.0
-5.0
(2ooH~OHZ
-12?V
/oCT
V
(360Hz)
'" ~
-12dBlOCT~~
-7dB
C400HZ~
-4dB (300Hz)
0.0
6dB/oCT
~
5.0
Attenuation
(dB)
~
8~~
10.6dB
(3800Hz)
(2250Hz
10.0
12.5d!3\
3000Hz)
15.0
\
20.0
\
25.0
30.0
0.1
~BIOCT
0.2
0.4
0.8 1.0
Frequency (kHz)
2.0
4.0
\
8.010.0
6-23
MB86460A
DIMENSIONS
48-LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT-48-M02)
.677±.016
(17.20±0.40) S Q - ;
.472+. 012
-.004SQ_
.106(2.70) MAX
(MOUNTING HEIGHT)
.002(0.05) MIN
112.00:+:8:r8)
24
LEAD No.
i
.0315(0.80)
TYP
Q~
I
I
! .012±002
.
~ 1LhI()()6(616)@i
! (0.30±0.0~-'-"'-=--J
"A"
.....roti.;;n;;::;;G:;:;nn;;;nn;;n:;:;nn~6n:;··~·:d"
·U I I
1.006(0.15)
.071± .012
(1.80±0.30)
002
005
JL006+·
.
- .0004(015+
. - 0·01 )
r---------------I
:i
i
:
:
:
Details of "A" part
~~
----t
.
i
i
.024(0.60) I
.006(0.15)
MAX
.020(0.50)
C_________I'::1.~X
6-24
1
I
i
Dimensions in
inches (millimeters)
cO
November 1990
Edition 3.0
FUJITSU
DATA SHEET
MB87002
1200 BPS MSK MODEM
1200 BPS MSK (Minimum Shift Keying) MODEM
The MB87002 is a 1200-bps CMOS minimum shift keying (MSK) single-<:hip
modem for multichannel access (MCA) and radio communication application.
Hs operation at low supply voltages and low power consumption is especially
su~able for portable application.
•
Data rate: 120o-bps
•
Low power consumption (20 mW with 5 V power supply)
•
Low supply voHage operation: 3.0 to 5.5 V (5 V typical)
•
On-<:hip crystal oscillator: 3.6864 MHz
PLASTIC PACKAGE
(DIP-16P·M03)
•
Switched-<:apacitor filter (SCF)
•
Selectable timing regenerator pull-in characteristic (within 15 b~s for
high-speed, and within 25 bits for low-speed operation)
•
Low external component count
•
TTL compatible inputs and outputs
•
PLASTIC PACKAGE
(FPT-16P·M03)
PIN ASSIGNMENT
(TOP VIEW)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
RlTC
CLOCK
Input Voltage
V,N
All input pins
Voo +0.3
V
OSC1
SEND
OSC2
RESET
DATAOUT
Output Voltage
VOUT
All output pins
Output Current
lOUT
All output pins
Storage Temperature
NOTE:
TSTG
-10
-55
Voo +0.3
V
10
mA
125
DC
Permanent device damage may occur if the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
cond~ions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Voo
DATAIN
MSKOUT
BPFIN
GND
BPFOUT
DPLLC
TEST
112 Voo
~ov:,':'I,~~'.=1ry1O Pro:"":~'C.~
ever, it is advised that n=:acautlons be taken to
awid app)ica1lDn of any voltage higher than maximum
rated voltages 10 this high ilf1)8dance circuil.
CapyrlghtC 1990 by FUJITSU LIMITED
6-25
MB87002
PIN DESCRIPTIONS
RlTC
6-26
Transmit-receive clock output control. When pulled high, the 1.2 kHz transmit clock is
output from the CLOCK pin and DATAOUT becomes low. When pulled low, the 1.2 kHz
receive clock is output from the CLOCK pin.
o
2
CLOCK
10
TEST
Test function control signal input. In the normal mode, this pin is pulled high or left open.
In the test mode, it is pulled low. In the test mode, the BPF IN pin directly accepts
Waveform Shaping I and receive LPF input signals, and the DATA IN pin directly accepts
Waveform Shaping II input signals. In this mode, the delay detection circuit signal is
output from BPFOUT and the receive LPF signal is output from MSKOUT.
11
DPLLC
DPLL pull-in time control signal input. When pulled low, high~peed operation is
selected. When pulled high, low-speed operation is selected.
Transmit-receive clock output pin. When RITC pin is pulled high, 1.2 kHz transmit clock
is output. When RITC pin is pulled low, the 1.2 kHz receive clock is output.
MB87002
MB87002 BLOCK DIAGRAM
DATAIN
MSKOUT
SEND
RlTC
OSCI
OSC2
CLOCK
RESET
TEST
BPFIN
BPFOUT
DATAOUT
D
DPLLC
VDD
1/2
VDD
GND
6-27
MB87002
FUNCTIONAL DESCRIPTION
The timing generating section generates the clock signals required by the modulator and demodulator. The basic clock is generated
by an internal oscillator and external crystal (3.6864 MHz).
Modulator uses a programmable DAC with a 6 bn resistor string. The MSKOUT output is 1200 Hz for input 1 and 1800 Hz for input 0
synchronized with transmit clock. Before the transmit signal is output. a fixed level of 112 Veo is output by pulling the SEND pin low.
The demodulator is composed of a band-pass filter (BPF). a delay detection circuit. a Iow-pass filter (LPF). and a digital
phase-locked loop (DPLL). The BPF removes noise components from the 1.200 Hz and 1.800 Hz receive signals from the BPFIN
pin and consists of a 1Oth-order Chebyshev switched-capacitorfitter (SCF). The delay detection circuit. after conversion olthe BPF
output from analog to digital in the waveform shaping circuit. regenerates data by delay detection. The noise components in the
regenerated data are removed by the LPF. The LPF is a third-order Butterworth fitter and removes noise components of 800 Hz or
higher. The DPLL extracts the receive clock from the regenerated data. The regenerated data is output from the DATAOUT pin
synchronized with the receive clock. The DPLL has a tendency to degrade the bit error rate when the pull-in time is shortened. This
IC allows users to choose between two pull-in times. When the DPLLC pin is pulled low. the high-speed mode is selected. When
pulled high. the low-speed mode is selected.
The on-chip 112 Voo circuit supplies the reference voltage required by BPF. LPF. and waveform shaping circuits and reduces
external circuitry and component count.
NOTE: Devices consisting of mixed analog and diQital signal processing circuits are usually difficult to test. The MB87002
incorporates a test circuit which simplHies independent testing of the BPF, delay detection circuit. LPF and DPLL.
RECOMMENDED OPERATING CONDITIONS
mI
Input Voltage
6-28
V,N
All input pins
0
Voo
OSCI Pin Load Capacitance
Cose,
OSCI
25
50
OSC2 Pin Load Capacitance
Case.
OSC2
25
50
Analog Output Load Resistance
RMO
MSKOUT
10
Analog Output Load Capacitance
ClIO
MSKOUT
Temperature
T.
-10
kQ
30
pF
70
·C
MB87002
ELECTRICAL CHARACTERISTICS
DC characteristics (V DO = 4.5 - 5.5 V)
...
··:.ZL{. ··········i~~~:{ ·)F:Lii
······i~~~~~~(······
. > . i ) .•..:...\:........ .:. ·.~~';;'~'T~. .....i
......:.:......
v~iii.i.·· .
MIn
Typ .
....
.
-
T. - 25·C
.. :
Max
·······~~~i
100
Voo
-
4
8
mA
Digital Input Low Voltage
VIL
RESET, SEND.
DATAIN. DPLLC,
RfTC, TEST
0
-
0.8
V
Digital Input High Voltage
V,"
RESET, SEND,
DATAIN, DPLLC,
RITC, TEST
2.2
-
Voo
V
Digital Input Low Current
III
SEND, DATAIN,
DPLLC, RITC
V," = GND
-10
-
0
!'II
Digital Input High Current
I'H
RESET, SEND,
DATAIN, DPLLC,
RfTC, TEST
V'N = Voo
0
-
10
!'II
Power Supply Current
f-----
Pull-up Resistance
RpLU
RESET, TEST
25
50
100
kn
Digital Output Low Vottage
VOL
DATAOUT, CLOCK
10l= 2.0 mA
0
-
0.4
V
Digital Output High Voltage
VOH
DATAOUT, CLOCK
10H= 1.0 mA
2.4
-
Voo
V
OSC,.
OSC1,OSC2
-
3.6864
-
MHz
Analog Input Resistance 1
RAIN'
BPFIN
Analog Input Vottage 1
VAIN1
BPFIN
Oscillator Frequency
Analog Output Vokage 1
Receive BPF Absolute Gain
AoUT1
ABS,
Receive BPF Frequency
Characteristics
F,
Receive LPF Cutoff Frequency
Fo
Receive LPF Absolute Gain
ABS,
Input pin-l 12 Voo
50
100
200
kn
0.5
-
2.5
Vf4'
Operation
0.8
1.0
1.2
Vf4'
Offset vokage
in operation
1/2 Voo
-0.3
112 Voo
1/2 Voo
+0.3
V
RESET = Low
1/2 Voo
-0.3
1/2 Voo
1/2 Voo
+0.3
V
-
Input frequency
1500 Hz
-1.0
0
1.0
dB
-
-40.0
-3.5
-1.0
-3.5
-
-
0-300
900-1200
1200-1800
1800-2100
-
-
-30.0
dB
dB
dB
dB
dB
-
800
-
Hz
-
-6.0
-
dB
MSKOUT
-
Hz
Hz
Hz
Hz
3000-5000 Hz
Reference
frequency
1500 Hz
3 dB down
o Hz <
Input frequency
~ 300 Hz
-
-
-
-
6-29
MB87002
DC characteristics (VDD = 3.0 - 4.5 V)
Dignal Input Low Voltage
VIL
RESET. SEND.
DATAIN. DPLLC.
RlTC. TEST
0
0.6
V
Dig Hal Input High Vottage
V,.
RESET. SEND.
DATAIN.DPLLC.
RfrC. TEST
2.2
VDO
V
Digital Input Low Current
I'L
SEND. DATAIN.
DPLLC. RlTC
V'N- GND
-10
0
IIA
Digital Input High Current
I,.
RESET. SEND.
DATAIN. DPLLC.
TEST
V'N = Veo
0
10
IIA
MSKOUT
112 Veo
-0.3
112 VDD
+0.3
V
AoUT1
Offset vottage
in operation
112 Voo
Analog Output Vottage 1
RESET = Low
1/2 Voo
-0.3
112 Voo
112 VDD
+0.3
V
Input frequency
1500Hz
-2.0
0
2.0
dB
-30.0
dB
dB
dB
dB
dB
mI
Receive BPF Absolute Gain
Receive BPF Frequency
Characteristics
Receive LPF Absolute Gain
6-30
ABS,
F,
ABS.
0-300 Hz
900-1200 Hz
1200-1800 Hz
1800-2100 Hz
3000-5000 Hz
Reference
frequency
1500 Hz
OHz<
Input frequency
S300 Hz
-3.5
-1.0
-3.5
-25.0
-6.0
dB
MB87002
AC characteristics (VDD
Pull-in Bit Number
=3.0 - 5.5 V)
N
Demodulator Delay Time
15
DATAOUT
1900
2317
bit
Receive Clock High Width
twHC2
CLOCK
417
496
!lS
Receive Clock Low Width
twLC2
CLOCK
417
496
!lS
6-31
MB87002
TYPICAL CONNECTION EXAMPLE
Reset
Transmit enable
To microcomputer
output port
Transmit data (Serial)
TransmitlReceive switching
TransmitlReceive clock
To microcomputer [
input port
Receive data
(Serial)
Rrrc
Voo
CLOCK
------i
OSCl
SEND
OSC2
RESET
MB87002
BPFOUT
Transm~ MSK signal ......
MSKOUT
Receive MSK signal
BPFIN
GND
6-32
DATAIN
DPLLC
TEST
1/2 Voo
High speed mode
MB87002
BPF FREQUENCY CHARACTERISTICS
~'~
48.0
42.0
-
l40dB
36.0
30.0
Attenuation
(dB)
1
24.0
1m
30dB
18.0
12.0
~
6.0
1 dB
0.0
-6.0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Frequency (kHz)
6-33
MB87002
TIMING CHART
Modulator timing chan (TEST pin
H
RESET
L
=High or Open)
t..u.
l::J
H
L
SEND
L
H
RlTC
L
•
,
tdACH
CLOCK
(1.2 kHz)
H
:
,
twHCt
'
,
,
tWLCl
~
,I t.SCL .:,
.
,
,
---
, tssc,
tSDC I
L
,
tsoc : 1t.oc
H
DATAIN
L
.
;.......:
,, ' ,,
'
,
>k><:>,><>,:><>::.,,<:,>:;>::,<><>,:::>:>:]
: 1.,.1-'[>~~>:I
~~'''''~''''' "",,;,,·"\t'\\\;··\':·\{'::f\{~;\\\';··.\\'\\\t\\·';,./" ,,'\\',/.\',""'\ \\\'\\l~
"
I
,
,
I
,,\1".
0
I'>';~>I
_'.",'\"{'~
WRM
H
H
MSKOUT 1/2 Voo
L
~~;~:+,-------+,~,
,,
H
DATAOUT
L
NOTE: 1. SEND pin is pulled high after Iow-ta-high trans~ion of the RESET pin.
2.
3.
4.
5.
6-34
DATAIN signal is read at the rising edge of the CLOCK.
When SEND pin changes from low to high, the CLOCK pin is pulled high once. Then 1.2 kHz clock is output.
When RlTC pin is pulled high, DATAOUT pin outputs low.
When power is first applied, RESET pin must be sat to low to reset all circuits before use.
MB87002
Demodulator timing chan (TEST pin
H
RESET
L
=High or Open)
twlR
1::1
H
SEND
L
H
RfTC
L
tdRS
N-pattern or more
BPF IN 1/2 Voo
o
o
o ,,1
,
0
0
o
~
H
DATAOUT
L
;;~,;;;:;;f:;:;;;::'::;;';;;;;;;:;:;;;';;;;f>;;;::>;~;:;;;:,11
, ,
~~j1~o
oG'loF<>«
I)
. :." .,'..,'.
"
CLOCK H
(1.2 kHz) L
~,'UnUnUnL!»-'
«n
n r({ n n-;~o~t!htR n n
U U U U J)J U U U U U U U U L
:
,
,
i-:
,,
:,
;
n
n
tdRM
,,
MSKOUT 1/2 Voo :
zjJ'I-.- - - - - - - - - - - - - - - - - - - - - - - -
NOTE: 1. DATAOUT is output synchronized with the rising edge of the CLOCK.
2. When demodulator section is used, SEND pin must be set to high or low, When SEND pin is set to low, MSKOUT is
fixed to 1/2 Voo.
3. When power is first applied, RESET pin must be set to low to reset all circuits before use.
6-35
MB87002
Clock output timing chart
H
RlTC
L
, ,
, ,
,......, tdRCl
, ,
, ,
.......
,
CLOCK
H
tdTC6
----------------~----------------------~-------------Transmit clock (1.2 kHz)
Transmit clock (1.2 kHz)
Receive clock (1.2 kHz)
L
o
o
r----~-
DATA IN
XCLOCK
Modulator
circuit
MSKOUT
= BPFIN
1.2 kHz
1.8 kHz
1.2 kHz
1.8 kHz
BPFOUT
RCLOCK
'-______--II
6-36
DATAOUT
Demodulator
circuit
MB87002
PACKAGE DIMENSIONS
Plastic DIP,16 pins
(DIP-16P-M03)
.050 IL~_n
MAX
© 1988 FUJITSU LIMITED D160305-3C-1
Un~s:
mm (inches)
6-37
MB87002
Plastic SOP, 16 pins
122(3.10) MAX
(SEATED HEIGHT)
(FPT-16P-M03)
.002(0.05) MIN
J
~r-U
(STAND OFF)
I
.362±.012
(9.20±0.30)
INDEX
cf
4
I
'--f-
n
.020±.00B
(0.50±0.20)
002 (0 15+ 0 .05 )
--H- .006+.
-.001· -0.02
.050(1.27)
TYP
r------------,
.-p...
I
1
1
1
1
:
~
© 1989 FUJITSU LIMITED F16008S-3C-1
6-38
Details of ''A'' part
I
1
.008(0.20)
:
.024(0.60)
.007(0.18)
MAX
.027(0.68)
~!'~
_______
1
____ J
Units: mm (inches)
Section 7
Telephone Integrated Circuits -
At a Glance
Page
Device
DeacrlplIon
7-3
MB3120
Compandor IC
7-15
MB3121
Compandor IC
7-19
MB4513
Telephone AmplifierlTone Ringer
7-31
MB4518
7-47
Package
Optlona
Hi-pin
17-pin
28-pin
Plastic
Plastic
Plastic
FPT
ZIP
FPT
48-pin
Plastic
DIP, FPT
Telecommunication Circuit
28-pin
Plastic
DIP, FPT
MB4752A
Subscriber Une Interface IC
28-pad
Ceramic
LCC
7-57
MB87007A
MB87008A
Dual Tone Multilrequency Pulse Dialer
III-pin
24-pin
Plastic
Plastic
DIP
FPT
7-a3
MB87009
Dual Tone Multifrequency Pulse Dialer
2O-pin
Plastic
FPT
7-111
MB87017B
Dual Tone Multifrequency Receiver
III-pin
24-pin
Plastic
Plastic
DIP
FPT
7-123
MB87029
Dual Tone Multilraquency Pulse Dialer
22-pin
24-pin
Plastic
Plastic
DIP
FPT
7-149
MB87057
Dual Tone Multifrequency Receiver
III-pin
24-pin
Plastic
Plastic
DIP
FPT
III
7-1
Telephone Integrated Cjrcujrs
D
7-2
Telecommunications Data Book
OJ
April 1990
Edition 2.0
FUJITSU
DATA SHEET
MB3120
COMPANDOR IC
COMPANDOR IC
The Fujitsu MB3120 is a compandor IC to expand dynamic range at transmis·
sion/reception systems and to improve the tone quality by means of restricting
noise.
Two functions are loaded on one IC, the one is the compressor which has the
2/1 ratio of input/output ratio by logarithm, and the expandor which has the
1/2 ratio of input/output ratio by logarithm.
PLASTIC PACKAGE
FPT·16p·M04
The MB3120 is encapsulated in a small package. This enables high density
mounting.
The M.B3120 is well suitable for a mobile radio system like as cellular radio,
MCA and handy telephone set.
•
Wide power supply voltage range
(3.2V to 10.0V)
•
Inhibit function with compres·
sion/expantion ratio of one
•
Low power supply current
•
Equipped with mute function
which cut off the output signal
•
On·chip both compressor and
expandor
•
16'pin Flat Package
17'pin Zig·zag In·line Package
•
Wide dynamic range
•
Less external elements
PLASTIC PACKAGE
Zlp·17P·M01
PIN ASSIGNMENT
(TOP VIEW)
Vee
Inv In-C
Rect In-E
NFB-C
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Out·C
Reet
Rating
Symbol
Value
Unit
"G In·E
In~C
Rect Cap·E
D.G In-e
Out·E
Reet Cap·C
Power Supply Voltage
Vec
12
V
Mute Control Voltage
V MUTE
5"
V
Inhibit Control Voltage
V 1NH
5"
V
Power Dissipation
Po
560
mW
Operating Temperature
TA
-20 to +75
°c
Storage Temperature
T STG
-55 to +125
°c
Mute In-E
INH
Mute In-e
ByPass
GND
(FPT·16P-M02)
ZIP·17P-MOI Pin A .. ignmont
Please Sea Page 12
": This value takes Vcc when Vee is less than 5V.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this. data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.
7-3
MB3120
MB3120 BLOCK DIAGRAM
------------------------------,
COMPRESSOR
OUTPUT
COMPRESSOR :
SECTION
I
I
I
I
COMPRESSOR
INPUT
+
C4
20kn
VARIABLE GAIN
CONTROL CIRCUIT
10kn
C3
IfJI
EXPANDOR
SECTION
FULL WAVE
RECTIFIER
EXPANDOR OUTPUT
40kn
10kn
VARIABLE GAIN
CONTROL CIRCUIT
EXPANDOR
INPUT
COMMON
MUTE
I
I
:
8
~-------------------------------l
GND
I
I
I
I
_J
INHIBIT
MUTE FOR
EXPANDOR
FPT'16~
~ZIP'17
7-4
MB3120
BLOCK DESCRIPTIONS
C,
C, determines the low cut off frequency of compressor section.
fc
1
= --21fR" C,
R is on chip feed back resistor (10k.l1 typ.)
C:z. Ca. Cg
Input coupling condenser
C3 • C7
Smooth capacitor of full wave rectifier. Atack time and recovery time are determined by
~
and C7 •
Time constant T c can be calculated.
Tc (ms)
=,
10 x C3 (J.lF)
Output coupling condenser
Coupling condenser for internal feed back of compressor section.
Ripple filter condenser
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Typ
Min
Power Supply Voltage
Vcc
Operating Temperature
TA
Max
3.2
10
V
-20
75
·C
ELECTRICAL CHARACTERISTICS
(Vee =8V. TA = 25°C,f= 1kHz.RL = 10k.\1l
Value
Parameter
Symbol
Condition
Min
Power Supply Current
I
I
Icc
Typ
3.0
I
I
Unit
Max
4.5
mA
Compressor
Input Resistance
Input Reference Level
Output Level"
R1Nc
14
20
V 1N = -6dBm
-10.5
-9.0
-7.5
dBm
Voco
V 1N =-6dBm.
T A = -20 to 75·C*2
-2.5
0
2.5
dB
V oc ,
V 1N = -20dB
-10.5
-10.0
-9.5
dB
V OC2
V 1N =-40dB
-20.7
-20.0
-19.3
dB
V 1N = -60dS
-31.5
-30.0
-29.0
dB
V 1N =-60dB.
T A = -20 to 75·C'2
-4.0
3.0
dB
VOC3
V OC4
V 1N = -BOdB
0
-40.0
k.l1
dB
7-5
MB3120
ELECTRICAL CHARACTERISTICS (continued)
Parameter
Value
Symbol
Condition
Min
I
Typ
I
Unit
Max
Expandor
Input Resistance
Input Reference Level
Output Level*1
4.7
R'NE
6.7
kn
V ,N = -9dBm
-1.5
0
1.5
dBm
V OEO
V ,N = -9dBm,
T A = -20 to 75°C'2
-2.5
0
2.5
dB
V OE1
V ,N = -10dB
-20.5
-20.0
-19.5
dB
V OE2
V ,N = -20dB
-40.7
-40.0
-39.3
dB
V ,N =-30dB
-61.0
-60.0
-58.5
dB
V OE3
V,N =-30dB,
TA = -20 t075°C*2
-3.0
4.5
dB
V OE4
V ,N = -40dB
0
-80.0
dB
Compandor
1.11
Total Harmonic Distortion
THD
Vo =OdBm
Output Noise Voltage
VON
BW = 100Hz t05kHz
Voltage Gain
Av
V ,N = -6dBm
Gain Deviation 1
AAv1
V ,N --6dBm,
T A = -20 to 75°C*2
Gain Deviation 2
AAv2
f = 200Hz to 5kHz,
Vo,=OdBm
Voltage Gain at Inhibit
AVINH
V ,N = -6dBm,
V,N,NH = O.4V
Compressor Mute
Attenuation *3
VOCMUTE
V ,N =-6dBm,
V,NCMUTE = 2.7V
-50
dBm
Expandor Mute
Attenuation *3
VOEMUTE
V ,N = -9dBm,
V,NEMUTE = 2.7V
-70
dBm
High-level Control Voltage
for Mute and Inhibit Pins*3
V ,H
Low-level Control Voltage
for Mute and Inhibit Pins*3
V ,L
0.5
2.0
%
-80.0
dBm
6.0
7.5
dB
-3.0
0
3.0
dB
-0.5
0
0.5
dB
6.0
7.5
dB
4.5
4.5
2.7
V
0.4
Notes:
"1 Measured at input reference level of OdB.
*2 Gain deviation with temperature when output level of 25°C is specified as OdB.
*3 As for Zip-17 pin, both compressor and expandor circuit enter mute function depending on 8 pin input.
7-6
V
MB3120
TYPICAL CONNECTION EXAMPLE
FPT·16
4.7"F
COMPRESSOR INPUT
0
- +
0
16
2
15
-0 Vee
- +
1
I
3
14
4
13
5
12
6
11~0-- MUTE FOR EXPANDOR
4.7"F
2.~F
+
~o---7
MUTE FOR COM PRESSOR
+
2.2"F
.+
4.7"F
...
EXPANDOR INPUT
I
4.7"F
1OI'F
...
r-.
+
22"F
4.7"F
COMPRESSOR OUTPUT
1
10"F
- +
EXPANDOR OUTPUT
+
10 ---<)'---0--
INHIBIT
22"F
8
9
+
,
ZIP·17
4.71'F
COMPRESSOR INPUT
0
1
+
COMPRESSOR OUTPUT
0
+
22"F
2
4.71'F
3
4.71'F
+ 10"F
4
+
5
MUTE FOR CO MPRESSOR
+"~C>--7
2.21'F
6
+
.......0 - -
8
9
10
INHIBiT
4.71'F
EXPANDOR OUTPUT
0
EXPANDOR INPUT
0
Vee
*;
~
+
' - - - 0 " --C>--
+
11
.......
0-
12
13
+
15
+
10l'F
16
17
MUTE ·FOR EXPANDOR
2.21'F
14
4.71'F
COMMON MUTE"
221'F
+
Both the mute of Compressor and Expandor can be controlled by this terminal.
7-7
MB3120
OUTPUT TRANSITION RESPONSE CHARACTERISTICS
Condition:
Vee" 8V, f • 1kHz, RL
1;11
10kn. Mute OFF.INH OFF, Typ. connection
COMPRESSOR
(V: O.2V/div. X: 5msec/divl
VIN • -l8dBm - -6dBm (Va· -15dBm - -9dBml
V 1N = -6dBm - -18dBm (Va = -9dBm - -15dBml
EXPANDOR
(V: O.5V/div. X: 5msec/divl
VIN --15dBm--9dBm (Va = -12dBm- OdBml
VIN = -9dBm-+-15dBm (Va
=OdBm ... -12dBml
COMPANDOR
(V: O.5V/div. X: 5m.ec/divl
VIN· -18dBm--6dBm (Vo· -12dBm-OdBml
VIN = -6dBm ... -18dBm (Va
=OdBm ... -12dBml
III
7-8
MB3120
TYPICAL CHARACTERISTICS CURVES
Fig. 1 - INPUT VOLTAGE vs. OUTPUT LEVEL
f'" 1kHz
Fig. 2 - INPUT VOLTAGE vs. OUTPUT LEVEL
(INHIBIT COND.)
f"" 1kHz
Mute OFF
INH ON
Mute OFF
INH OFF
Rg = soon
RL'" 10kn
Rg =6000
RL = 10kn
TYP. CONNECTION
TYP. CONNECTION
INPUT LEVEL V,N ldBm)
INPUT LEVEL
-100
-80
-60
-100
-80
-60
3.SV
.
e
e
:!!
-40 ~
Vee '" 8V·~_~~~~~::-r
...J
Vee '"
W
-60
~
EXPANDOR
>
~
3.5V~~~I:;;OH;:Z:;t=O=3=0=kH=Z"""'icoMPRESSOR
~
~
-60
8V
-80
;=
-80
5
-100
Fig. 4 - MAX. OUTPUT LEVEL VS.
SUPPLY VOLTAGE (COMPANDOR)
f".1kHz
..
LPF: 100kHz
Mute OFF
INH OFF
----- R L • 600n
Rg =600.0
- - R L -10ka
THO = 1%
Mute OFF
-7
-12
-8
-14
:!!
0
.. e..
e
1
:!!
:!!
0
0
-16
-9
W
0
0
0
w
0
o 4
>
>
>
...J
...J
...J
...J
w
w
1rI-
>
w
-18~
-10
w
-1
>
W
...J
...J
...J
u:
u:
u:w
~ -11
a:
.
a:
I-
-22 ~
-3 ~
:0
1r
~ -12
-2
I-
l-
INH OFF
Rg=600n
1
i
>
w
~
:0
o
-100
Fig. 3 - INPUT REFERENCE LEVEL
vs. VOLTAGE SUPPLY
e
~
I:0
I:0
~
3
...J
I:0
o
1r
SUPPLY VOLTAGE Vee IV)
~3
2
I
:
,,
4
10
12
~
~
SUPPLY VOLTAGE Vee IV)
I
7-9
MB3120
TYPICAL CHARACTERISTICS CURVES (continued)
Fig. 5 - FREQUENCY vs. VOLTAGE GAIN
(COMPANDOR)
Vee = 8V
MUTE OFF
INH OFF
Rg =600.0
RL = 10k.o
TYP. CONNECTION
iii
:!!
0.5
0
-0.5
-
VIN = OdBm
0.5
0
-
-20dBm
0.5
-
-40dBm
>
<0: -0.5
z
0
<
t!l -0.5
w
t!l
<0:
0.5
0
>
-1.0
':i0
Vo i. OdB when f = 1kHz.
-2.0
--
50
II
---
-50dBm
500
100
5k
1k
10k
~
50k
FREQUENCY f (Hz)
Fig. 6 - INPUT REFERENCE LEVEL
VS. TEMPERATURE
-7
E
co
~
Fig. 7 - OUTPUT LEVEL vs. TOTAL HARMONIC
DISTORTION (COMPRESSOR)
2
-8
E
co
-9
>
~
u
...J
w
>
w
...J
10
w
0
0
>
20
COMPRESSOR:
(VIN = -6dBm)
-10
Ii
w
a:
I- -11
:::l
0.
~
-12
-40
Vo~
0
-20
0
20
Vee = 3.5V
w
>
w
-1
Vee = 8V
Mute OFF
INH OFF
Rg = 600.0
RL = 10k.o
TYP. CONNECTION
5
...J
f= 1kHz
LPF: 100kHz
Rg = 600.0
MUTE OFF
INH OFF
..J
Ii
w
a:
-2 I:::l
0.
~
0
I
l-
0.5
~
-3
40
TEMP. T. (OC)
60
80
0.1
0.05
0.05 0.1
0.5
OUTPUT LEVEL Vo (Vrm.)
7-10
5
MB3120
TYPICAL CHARACTERISTICS CURVES (continued)
Fig. 8 - OUTPUT LEVEL .s. TOTAL HARMONIC
DISTORTION (EXPANDOR)
20
10
5
f = 1kHz
LPF: 100kHi
Rg = 600n
MUTE OFF
INH OFF
Fig. 9 - OUTPUT LEVEL .s. TOTAL HARMONIC
DISTORTION (COMPANDOR)
Vee = 3.5V Vee = 8V
20
10
RL=
10kn
RL=
600n
RL=
10kn
5
f= 1kHz
LPF: 100kHz
Rg =600n
MUTE OFF
INH OFF
Vee = 3.5V Vee = BV
RL =
600n
~
~
o
o
J:
I-
~ 0.5
0.5
0.1
0.1
0.05
0.05
0.05 0.1
5
0.5
0.05
OUTPUT LEVEL Vo (Vrms)
Fig. 10 - OUTPUT LEVEL .s. TOTAL HARMONIC
DISTORTION (EXPANDOR INHIBIT COND.)
20
10
5
~
o
J:
f = 1kHz
LPF: 100kHz
Rg = 600n
MUTE OFF
INH ON
0.1
0.5
1.0
5.0
OUTPUT LEVEL Vo (Vrms)
Fig. 11 - OUTPUT LEVEL .s. TOTAL HARMONIC
DISTORTION (COMPRESSOR INHIBIT COND.)
20
Vee = 3.5V Vee = BV
10
RL =
10kn
f = 1kHz
LPF: 100kHz
Rg = 600n
MUTE OFF
Vee= 3.5V
5
RL =
600n
~
o
J:
1
I-
I-
0.5
0.5
0.1
0.1
0.05
0.05
0.05
0.1
0.5
OUTPUT LEVEL Vo (Vrms)
5
0.05 0.1
0.5
1
5
OUTPUT LEVEL Vo (Vrms)
7-11
MB3120
TYPICAL CHARACTERISTICS CURVES (continued)
Fig. 12 - FREQUENCY vs. TOTAL HARMONIC
DISTORTION (COMPANDOR)
Fig. 13 - EXAPNDOR MUTE ATTENUATION
20
Vee = BV
Vo=OdBm
MUTE OFF
INH OFF
LPF: 100kHz
o
E -20
"'"
-;;'-40
o
>
VIN = -29dBm
-60
VIN = -9dBm
-80
0.05
VIN
-100 0
100
500
lk
5k
10k
2
50k
Fig. 14 - COMPRESSOR MUTE ATTENUATION
20
o
E -20
VIN = -6dBm
VIN =-46dBm
'""
~-40
o
>
Vee = BV
INH OFF
Rg = 600n
RL = lOkI"!
TYP.
CONNECTION
VIN =-BdBm
-60
-80
-100 0
VIN = -46dBm
1
=-29dBm
MUTE CONTROL VOLTAGE VIN (V)
FREQUENCY f (Hz)
2
MUTE CONTROL VOLTAGE VIN (V)
7-12
Vee = BV
INH OFF
Rg = 600n
RL = 10kn
TYP.
CONNECTION
VIN =-9dBm
3
3
MB3120
PACKAGE DIMENSIONS
16-LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT-16P-M04)
083(2 10) MAX
(SEATED HEIGHT)
0(0) MIN
+
.252±.016
.050(1.27)
TYP
r---------,
I
:
''A''
Details of "A" part
.008(0.20)
I
I
4
0[004(0
.350(8.89)
REF
I
I
1~; [
I
I
I
I
I
I
I
,
I
.020(0.50)
I
.007(0.18):
I
MAX
I
I
.027(0.68)
I
I __________
MAX
L
..JI
:
Dimensions In
C 1988 FUJITSU LIMITED D16012S-3C
inches (miI'maters)
7-13
MB3120
PACKAGE DIMENSIONS (Continued)
(TOP VIEW)
Inv In·C
]1
-13
Out·C -,
aG In-C
]5
Mute In-C
]7
GND
]9
2[
,-
17-LEAD PLASTIC ZIG-ZAG IN-LINE PACKAGE
(CASE No.: ZIP-17P-M01)
NFB-C
4l_ Reet In-C
.112±.01C
,-
6L Reet Cap-c
s[
I
1
Mute-In
.236±.OtD
(S.OO:tO.25)
10r BvPass
INH J11
12[ Mute In-E
Out-E ]13
(2.85±O.25J
~~rnvnnrnv~~~
J033)
.310±.013
14[ Reet Cap-E
.094t2.40) MIN
.oG In-E -J15
Vee -J17
---'-
16[ Reet In-E
.020±.OO3
(D.SO±O.OS)
LEAD NO.G\
(ZIP-17P-M01)
r
,100(2.54) TYP
(ROW SPACE)
~
(BOTTOM VIEW)
.. 1988 FUJITSU UM)TED Z17001S-3C
7-14
Dfl'T8nsions In
Inch.. (rrln_l
cO
FUJITSU
July 1991
DATA SHEET
MB3121
Compandor IC
The Fujitsu MB3121 is a highly functional compandor IC with on-chip support
circuitry that includes a microphone amplifier, input amplifier, and a splatter filter
amplifier. It also features low operating voltage and low power consumption.
The MB3121 is designed to improve the sound quality in transceiver systems by
increasing the dynamic range of the voice signal and suppressing noise. This
device incorporates a signal compression circuit having an inpulloutput compression ratio of 112*1og (110) and an expandor circuit with an input/output expansion
ratio of 2"log (110).
The MB3121 is the ideal choice for application in portable/mobile equipment such
as car phones and cordless telephones.
•
Low voltage operation: 1.8to 7 V
•
Compressor and expandor circuitry
•
Adjustable voltage gain (0 to 40 dB)
FPT-28P-M01
•
Limiter circuit
•
AmplHier circuit for use with a splatter filter
Pin Assignment
•
Data input and output pins
•
Output signal muting function
•
INHIBIT function that sets the compression and expansion ratio to 1:1
•
STANDBY mode
•
28-pin plastic SOP
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Value
Unit
Supply Voltage
Vee
1.8to 7 (Typical = 3)
V
Operating Temperature
T.
-20 to +75
°C
$-OUT
BP2
8-IN
BP1
GND
Vee
A-OUT
IDC
A-IN
NC
C-OUT
5B
C-A-OUT
INH
C-BP
MUTE
C-G-IN
E-OUT
C-R-IN
Note: Permanent device damage may occur if absolute maximum ratings
are exceeded. Functional operation should be restricted to the conditions as detailed in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
C-R-OUT
C-A-IN
C-M-OUT
C-IN
E-R-OUT
E-R-IN
E-G-IN
E-I-OUT
E-IN
This device contains circuMry 10 plOl8c:tlho lop'" against
damage dUB to high atalic voltages or electric fields. However. II:
._BOd that "",mat ""","",,0118 be takan 10 avoid """"cation
aI any W>Itago higher than maximum rated VORageslO this high
"""",ancocircuM.
©
1991 by FUJITSU LIMITED and Fujl1su M_"",IaI.lnc.
7-15
MB3121
BLOCK DIAGRAM
4.71JF
Bias
Vee
.~
(3
~r----------'
T------1.~
::J
Voice/Data In
10110
7-16
f--o
2.2jJF
MB3121
ELECTRICAL CHARACTERISTICS
Value
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply Current
lee
No Signal Applied
-
3.3
5.0
mA
Supply Current, STANDBY Mode
iSB
VSB=O V
-
0.1
10.0
j.tA
VOCI
VIn -100mV,,,,,
-20.8
-17.8
-14.8
dBm
Output Level
VOCl1
Vln =-20dB
-10.5
-10.0
-9.5
dB
Output Level
VOCl2
VIn =-40dB
-21.0
-20.0
-19.0
dB
VlIM
VIn=+14dB
-
550
-
mVp-p
MUTE Attenuation
ATTc
Vln = OdB
BW =200 Hzt05 kHz
60
80
-
dB
input/Output
Reference Level
VOCI
Vln = 100 mV,,,,,
-20.8
-17.8
-14.8
dBm
Input/Output
Reference Level
Compressor
Expandor
Compandor
Input Limiting Voltage
Output Level
VOCII
Vln =-20dB
-41.0
-40.0
-39.0
Output Level
VOCl2
Vln=-40dB
-65.0
-63.0
-60.0
dB
Maximum Output
Voltage
VOml
THD=2%
500
700
-
mV
MUTE Attenuation
ATTc
Vln = 0 dB
BW -200 Hzt05 kHz
60
80
-
dB
Output Noise Voltage
Vox
RL=On
BW = 200 Hz to 5 kHz
-
10
-
~V
Total Harmonic
Distortion
THO
VOCI = 100 mV,,,,,
-
0.5
1.5
%
Vln - 100 mV,,,,,
-1.5
0.0
1.5
dB
40
50
-
dB
Voltage Gain
Ay
Open Circuit
Voltage Gain
Ayo
Maximum OUlput
Voltage
AoM2
THO =2%
500
700
-
mV
Filter Gain
AVFl
Vln = 100 mV,ms(typ)
f= 1 kHz
-0.5
0.0
0.5
dB
Filter Gain
AVF2
1=3kHz
-3.5
-3.0
-2.5
dB
Filter Gain
AVF3
I =30 kHz
-65.0
-60.0
-55.0
dB
STANDBY (SB)
VSBH
Normal
1.0
-
Vee
V
Pin Control Voltage
VSBL
In STANDBY
0.0
MUTE
VMUTED
Muted
0.8
Pin Control Voltage
VMUTEL
Normal
0.0
INHIBIT (INH)
V INHH
Normal
Pin Control Voltage
VINHL
CompressionlExpansion Inhibited
Amplifiers
Filter
-
-
0.3
V
Vee
V
-
0.2
V
0.8
Vee
V
0.0
-
0.2
V
7-17
MB3121
28-Lead Plastic Flat Package
(case NOo:FPT-28P-M01)
.1102.
MAX
(SEATED HEIGHT)
f
AD2± .016
(10.20 0 OAO)
.299± .012
(1.6000.30)
.020± .008
(0.50 0 0.20)
-- . . ----- --- ----I
°Ao
,--
Detaltsof·A-part
.008 (0.20)
;
,
,
,
,
,,
1-----.650(16.5~1)~R~EF~==~
MAX
:
.. -- -------------~
7-18
DIm ....onsin
~dI.(mI.imeters)
00
June 1990
Edition 2.0
DATA SHEET
FUJITSU
MB4513
TELEPHONE Ie
TELEPHONE IC
(SPEECH NETWORK, TONE RINGER, FILTER)
The Fujitsu MB4513 has an on-<:hip speech network circuit, filter circuit, and tone ringer
circuit. The MB4513 is intended 10 be used with dialer IC's (MB87003/4, MB87007A18A,
MB87029) to produce a telephone which can be connected to a rotary dial line or push
bUllon line.
•
On-chip speech network circuit, filter circuit and lone ringer circuit
•
Uses a ceramic piezoelectronic transmitter and receiver
•
Reception amplifier adopts BTl (Balanced Transformer Less) circuit
•
Three selections of lone by the extemal switches
•
Connectable to pulse or DTMF lines
PLASTIC PACKAGE
DIP-48P-M01
PLASTIC PACKAGE
DIP-48P-M02
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Parameter
Value
Unit
Supply Voltage
VL
20
V
Supply Current
Symbol
Speech
I L
150
mA
Supply Voltage
VTR
20
V
Supply current
I TR
7
mA
°c
°c
Tone Ringer
Operating Ambient Temperature
TA
-301060
Slorage Temperature
TSTG
-55 to 125
NOTE:
Permanent device damage may occur if the above Absolute Maximum
Ratln!;ls are exceeded. Functional operation should be restricted to the
condibons as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
PLASTIC PACKAGE
FPT-48P-M02
This device contains circuitry to protect the Inputs against
damage due 10 high static voltages or eJedrlc fields. However. it
is advised that normal precautions be taken to avoid application
of any voltage h~her than maximum rated vollages to this high
irrpedance cirCUli.
Copyrlghl© 1990 by FUJITSU LlMllED
7-19
MB 4513
PIN ASSIGNMENT
a
Xl!
X1
FIN
F1
F2
TSI
TS2
TTH
F3
F4
52
S1
TaT
TVI
HAU
TV2
TRIN
MUTE
FOUT
R1
R2
RMV
RIN
RPO
RPC
SPBA
SPI
SP2
SPO
TPO
TIN
TPF
TMB
SPI
TMC
VLL
TME
TMV
LS
PRY
VL
(DIP-48P-MOI )
(DIP-48P-M02)
(FPT -48P-M02)
7-20
33
32
HAU
TV2
TRIN
27
26
25
a
TH
TGT
30
29
28
Aca
SPC
81
35
34
31
N.C
VCC
36
TV1
MUTE
N.C.
ACG
TPO
TIN
TPF
MB 4513
BLOCK DIAGRAM
TV2
TVl
TGT
TTH
TS2
X2
TSl
HAU
S1
S2
MUTE
VLL
FIN
F1
VL
TH
PRY
Transmit power
supply mute
circuit
F3
Filter
F2
F4
Vee
FOUT
ACG
GND
GND
TPO
TMV
MB4513
TPF
TMC
TMB
TIN
TME
RMV
R1
RIN
SPl
N.C
SP2
RPC RPO
LS
SPBA
SPI SPC SPO
Note: The pin numbers correspond to QFP package.
7-21
MB 4513
DC CHARACTERISTICS
(TA = 25°C)
Condition
Parameter
VL Voltage
VL Voltage
Supply Voltage
Values
Symbol
Unit
VL
I LImA)
Min
Typ
Max
20
1.9
2.7
3.9
90
5.0
6.2
7.5
V
20
2.2
3.2
4.4
V
90
5.3
6.5
8.0
V
20
1.4
1.7
2.0
V
VL
MUTE: ON
Vee
During Speech
AC CHARACTERISTICS
(TA = 25°C)
Condition
Parameter
7-22
V
MUTE: OFF
Symbol
AC Impedance
ZTEL
Transmit
Voltage Gain
GTV
VIN = -50 dBm
Transmit
Dynamic Range
VTO
DIS> -20 dB
Reception Voltage Gain
GRV
Reception
Dynamic Range
VRD
Reception Pad Loss
LRP
Values
Unit
Id mA)
Freq
(kHz)
Min
Typ
Max
400
600
800
n
48
dB
30
1.0
90
1.0
30
1.0
42
45
30
1.0
-2
2.5
90
1.0
0
8
VIN = -50 dBm
30
1.0
38
43
DIS> -20 dB
30
1.0
-3
4
90
1.0
-1.0
7
VIN = -50 dBm
30
1.0
L RP= GRV (30mA)
-GRV (90mA)
3
6
9
dB
90
1.0
73
dB
dBV
Speaker Gain
Gsv
VIN = -70 dBm
30
1.0
61
67
Speaker
Dynamic Range
VSD
DIS> -20 dB
30
1.0
3
8
46
dB
dBV
dBV
MB 4513
AC CHARACTERISTICS
(Cont'd)
Condition
Parameter
Symbol
.
Filter Input
Output
Characteristics
Values
IL(mA)
Freq
(kHz)
Min
Typ
Max
LFl
0.5
17
20
23
LF2
1.0
17
20
23
LF3
= -40 dBm
VIN
30
3.0
12
20
LF4
6.0
-7
5
LF5
12.0
-21
-9
30
Tone Ringer
Start Current
I TR
Load
= 47 nF
1.0
1.7
Tone Ringer
Output Voltage
VTR
Load = 47 nF
ITR = 5 mA
19
21
HAU
Tone Ringer Tone
..
Fl
Load
47 nF
F2
F3
=
ITR
=
Open
SmA
F4
F5
Note
Close
Unit
dB
mA
dBV
TSl
TS2
Open
Open
(1024, 819) 8Hz warble frequency
Tone
Close
Open
(1024, 819) 16Hz warble frequency
Open
Close
(1024, 1365) 8Hz warble frequency
Close
Close
1024
(1024, 1365) 8Hz warble frequency
LF VOUT - VIN
Provides a tone signal that shifts between warble frequency at 8Hz or 16Hz.
7-23
MB 4513
MEASUREMENT CIRCUIT
52
Xtal
32.76SkHz
51
X2
Tone Ringer
circuit
Xl
TRIN
FOUT
F4
Filter
F2
In
'C
In
'C
FIN
5P2
DI
5Pl
0
sn
.. _ _ _ ... _ _ J
III
R2
Rl
~
N
~
.
CI
..Q
0
Z
;;;-
::>
0
~
CI
..Q
0
::>
0
~
~
CI
..Q
CI
..Q
'"II '">II '"II '"II
Reception circuit
>
a:
,
CJ
"
iii
RIN
CI
0
0
a:
>
(J)
!J
~Ol
CJ
CJ
~
~E ..Q15." '".,
~
TIN
In
'C
~
;:: ;::::> M~I- ~
;::
::>
0
Loundspeaker
circuit
5PI
In
'C
~5
«j:,
Transmit circuit
'"CD'"
Q)
0
a.
II>
~
Q)
II>
"a.
0
II>
~
l;;
ijg
CD
Ol
l\l
""()
l\l
a.
~
~LL
'1~
56n
5W
Q)u.
transmission mode
reception mode
80
.,"z
~~
2.2kn
Transmit power
supply mute
circuit
00..
~~
~o
~o
' " II
_03:
i·~
11>'"
"iii
~o
g.
24n
~w
+1 +1
Eo~
~a.
iii
VL
7-24
x~
.!.
LL
a
.9
'0
c
0
a.
Ul
CD
~
()
~o-,
e?
~
.0
.,'"
.,E
"'"
a.
II>
VL
a.
0
'C
Q)
.s
<.i
.i
CD
E
:l
"c
'0.
CD
.r:
ICD
'0
z
MB 4513
APPLICATION CIRCUIT
R5
220
DP
dialer
'1
Tone ringer
power supply control
circuit
III
'2
Driver
'3
Transmit
main-amp.
'4
Transmit
pre-amp.
Ceramic
transmit
'5
Reception
pre-amp.
29
N.C
RPC
'6
Buffer
amp.
R18
200K
7 6
RPO
16
'7
Reception
main-amp.
100nF
'S
Loudspeaker
pre-amp.
'9
Loudspeaker
main-amp.
Note
R15 ":"
S.1K
The pin numbers correspond to QFP package
7-25
MB 4513
TYPICAL CHARACTERISTICS CURVES
SUPPLY VOLTAGE VS. SUPPLY CURRENT
9
I
8
VL' (MJTE
7
.II'
4
~V
3
~ ......
f
;;...
VL
q
'I
(M~TE FFF)
~
-
f = 1kHz
LS: OFF
600
400
I
Jee I_ f--
V
2
800
bN) ,
6
5
1
o
AC IMPEDANCE VS. SUPPLY CURRENT
o
20
40
60
80
100
IL (mA)
I
o
20
40
80
60
100
IL (mA)
TRANSMIT GAIN VS. FREQUENCY
AC IMPEDANCE VS. FREQUENCY
60
BOO
700
D
q
a;
50
600
N
500
-
40
0.2 0.3
r-...
30
400
0.1
IL =130m~
VIN = -50dBm
1)= 30L
LS: OFF -
0.5
2
3
5
20
0.1
10
0.2 0.3
f (kHz)
2
VIN = -50dBm
i'"""- ....
IL =
30
90-;:'r-..... .......
20
............
'
2
0.5
3
~
~,
5
.....
-2
iii'
:!!.
>
II:
Cl
10
r-....
-4
10
I
I
""'r-...,.
LRP
........ ~l
-6
-50~Bm
-8
VIN =
f = 1kHz
-10
-12
-
I
o
f (kHz)
7-26
0
lL =
30mA
.......
0.2 0.3
5
RECEPTION GAIN VS. SUPPLY CURRENT
RECEPTION GAIN VS. FREQUENCY
40
3
f (kHz)
50
10
0.1
2
0.5
20
40
60
IL (mA)
80
100
MB 4513
TYPICAL CHARACTERISTICS CURVES
DYNAMIC RANGE VS. SUPPLY CURRENT
SPEAKER GAIN VS. FREQUENCY
16
80
14
60
./
".
",.,
IL = 30mA
50
'"
= rorm
VIN
'>
OJ
:e
.......
(I)
0>
''""
II:
-
0
40
0.1
0.2 0.3
0.5
2
3
10
5
GTD
8
I
6
fo"':::
GRD
V
4
1/
I /
0
IL = 30mA
f = 1kHz
1/
-2
D'I =
-4
f (kHz)
-
L
10
E
'>-"
0'"
~s~
~
12
70
r
dB,
r-r--
-6
o
20
40
60
80
100
IL (rnA)
TONE RINGER OUTPUT VOLTAGE VS.
TONE RINGER INPUT CURRENT
FILTER RESPONSE
24
30
23
IL =130mAI
20
E
OJ
:e
YIN
r\
".
22
= -40dBm -
"
21
10
20
\
0
'>
OJ
r\
u.
...J
-10
:e
a:
\
-20
f-
>
II'
19
-
I
18
17
16
J
I
15
14
-30
13
0.1 0.2 0.3 0.5
2
f (kHz)
3
5
10
20
12
11
o
2
4
3
ITR
5
6
(mAl
7-27
MB 4513
PACKAGE DIMENSIONS
48-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-48P-MOI)
L
.600(15.24)
.543±.010
TYP
(13.80±0.25)
~~~~i"i"iTi'TTi=n=;=;=n=;:~_J
.070(1.7781
MAX
.070± .007
(1.778±0.18)
~------
1610(40.894) REF
-
..........
-
--J.k018 ± .004
(0.45±0.10)
-------1
Dimensions in
© 1988 FUJITSU LIMITED 0480028-3C
inches (millimeters)
48-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-48P-M02)
2.372~g~~16025 ~g~g)--'-------jl
~~~~~~~~~
INDEX-1
T
o
.543+ 010
(13.80±0.251
.600(15.24)
~"i"'I"FFn=l'i'T9"i"i'T'fRTi''l''i''Fi''iFf'T'i''j'Tft''FiET'IT'fTff'EjF''f!-
J
.
TYP
L. .010±.002
(0.25±0.051
MAX
TYP
Dimensions in
© 1988 FUJITSU LIMITED 048003S-3C
7-28
inches (millimeters)
MB 4513
PACKAGE DIMENSIONS
48-LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT-48P-M02)
116:~~~~1:0)
sa ~
472+. 012
'-- __
._
- .004
.10612.70) MAX
ISEATED HEIGHT)
sa
112.00~g~g)
.00210.05) MIN
@
if4J
LEAD No. Ci)
.031510.80)
TYP
II
@
.012±.00~$I.00610.16) ~
10.30±0.06)
...roi;t
:
~R!ht8gRgn
D-;00610.1:;~ I
1.071± .012
11.80±0.30)
I
L.006+·002 10.15+ 0 .05 )
-.0004
-0.01
r----------------,
• -',:(
:
!
I
:
© 1988 fUJITSU LIMITED f480D2s-7C
I
I
I
1.02410.60) :
I!
.00~~~15)
.02010.50)
MAX
I
I
Dimensions in
inches (millimeters)
7-29
MB 4513
7-30
cO
April 1991
Edition 1.0
FUJITSU
DATA SHEET
MB4518
TELECOMMUNICA TION CIRCUIT
The MB4518 provides many of the major speech circuit functions of the telephone
handset. Additional features include a level expander circuit to minimize ambient
acoustic noise interference and an on-chip amplnier with speaker-drive capability.
Combined with general-purpose dialer and tone-ringer ICs, the MB4518 provides all of
the basic handset functions.
The MB4518 easily interfaces with microprocessors designed for telephone handset
control to provide microprocessor-controlled speaker level, transmitter muting, and
side-tone level adjustments. The sidetone level adjustment circuit detects loop current
levels and switches between two balance networks for proper sidetone level.
• On-chip power amplnier drives an 8 n speaker
• Transmit level expander
• Simple receive level boost
• Balanced transmitter input for improved noise rejection
• Drives low-impedance receiver (dynamic receiver)
PLASTIC PACKAGE
(DIP·28p·M03)
• Switchable balance network for optimum side-tone level
• Loop-current monitoring automatic gain control (automatic pad function)
• Low loop current drain (I.!; 5 rnA)
• Superior branching properties
• Gain and frequency characteristics edjustable by external resistor and capacitor.
• Simple telephone microcomputer interface
• Available in 28-pin shrink dip and flat packages
ABSOLUTE MAXIMUM RATINGS (See NOTE)
(T.= +25°C)
Supply voltage
VL
18
V
Supply current
IL
120
rnA
Operating temperature range
Top
-30 to +60
·C
Storage temperature range
Tstg
-55 to +125
°C
NOTE: Permanent device damage may occur n the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
,
PLASTIC PACKAGE
(FPT·28P·M01)
This dovloo co...... d ...~ry to prol8cl lhe l"puIS
agalnat damage due to high I1atlc vo~ or eJec:Iric
fields. H""""er. H Is advised lhal normal precautions
be_"to awld ~Ion III anyvoHage hlgherlhan
maximum _
WlitageB to lhls high irr!>Odance drcult.
CopyrIghtO 1991 by FUJITSU LIMITED
7·31
MB4518
PIN ASSIGNMENT
(TOP VIEW)
GND
7-32
28
TI2
V""
2
RPI
3
26
MUTE
RPO
4
25
EXC
VREF
5
Til
EXR
PADC
6
23
BNC
RGU
7
22
BN2
RBO
8
21
BN1
SPSW
9
20
MFIN
RI
10
19
TOE
RO
11
18
VL
SPREF
12
VSP
13
16
SPI
SPO
14
15
SPGND
SPH
MB4518
PIN FUNCTIONS
GND
Chip ground.
Connected to the (-) side of an external diode bridge connected to the subscriber loop.
2
Vee
Power supply pin.
Supplies power to the chip circuits. Coupled from the loop (AC-grounded) by an
external capacitor.
3
RPI
Receive preamplifier input.
Connected to the receive input through an external coupling capacitor.
4
RPO
S
VREF
Reference voltage pin.
Connected to the internal reference vottage and AC-grounded through an external
capacitor.
6
PADC
Pad insertion control.
Start-up current for the pad insertion control is adjusted by connecting an external
resistor to this pin.
7
RGU
Simple receive gain control.
Grounding this pin increases the receive preamplifier gain by about 6 dB.
Normally left open.
8
RBO
9
SPSW
10
RI
11
RO
12
SPREF
13
VSP
14
SPO
0
0
Receive preamplifier output.
The receive preamplifier gain and frequency compensation are externally adjusted with
a resistor and capacitor connected between this pin and the RPI pin.
Receive buffer output.
Connected to the RI and SPI pins through external coupling capacitors.
Speaker defeat switch.
When this pin is open, the speaker is connected; when grounded, the speaker is
disconnected.
Receive main amplifier input.
The receive signal is coupled to this pin from the RBO pin by an external capacitor.
0
Receive main amplifier output.
Connected to a low-impedance receiver by an external coupling capacitor.
Some receivers may require a shunt capacitor to prevent oscillation.
Speaker circuit reference voltage pin.
Reference voltage pin for the speaker and receive output circuit.
AC-grounded through an external capacitor.
Speaker amplifier power supply pin.
The speaker amplifier receives power from this pin.
The speaker power supply can be coupled at this point by an external capacitors.
0
Speaker output.
Connected to an 8 Q speaker through an external capacitor.
Some applications may require a speaker shunt capacitor to prevent oscillation.
7-33
MB4518
15
SPGND
16
SPI
Speaker amplifier input.
Connected to the RBO pin through an external capac~or and resistor for adjustment of
speaker amplifier gain and frequency compensation.
17
SPH
Speaker circuit power control.
The speaker power supply circuit is connected to the speaker amplifier input (VSP)
through an external network which can be adjusted to control chip power consumption.
18
VL
Line input.
Connected to the (+) side of an external diode bridge connected to the subscriber loop.
19
TOE
20
MFIN
DTMF signal input.
Connected to the base of the transmit output transistor.
The input impedance is about 24 lin.
During voice transmission this pin must be open.
21,
22
BN1,
BN2
Balance network pins.
Used for connection of external balance networks.
BN1: Short loop, BN2: Long loop
23
BNC
Balance network switching control.
An external resistor is connected between this pin and Vee or ground to adjust the BNl
and BN2 switching current.
24
EXR
Level expander reference vo~age pin.
Reference voltage pin for the control of the level expander.
Connecting an external capacitor holds the positive peak voltage level.
25
EXC
Level expander control.
Control pin for the level expander.
Connecting an external capac~or holds the negative peak vottage level.
When grounded, this pin disables the expander function.
26
MUTE
27,
Til,
TI2
28
7-34
Speaker amplifier ground.
This pin must be connected to the circuit network ground.
o
Transmit main amplHier output.
Connected to the emitter of the transmit transistor.
Muting.
Grounding this pin suppresses output to the loop.
During communication this pin must be left open.
Transm~ preamplifier input.
Connected to the transmitter through external coupling capac~ors.
The input is balanced. Til is the noninverting input and TI2 is the inverting input.
MB4518
BLOCK DIAGRAM
SPREF
SPI
RI
RBO RGU
RPO
RPI
SPH
VSP
Gain
Control
BN1
SPSW
BNC
BN2
SPGND
III
Pad
r-------------------------~insert~n
Line
control
VREF
TOE
TI1
(27)----,
1
Transm~
GND
preamplifier
EXC
EXR
MUTE MFIN
7-35
MB4518
RECOMMENDED OPERATING CONDITIONS
(T. - +25°C)
7-36
Supply voltage
12
Supply current
20 to 120
rnA
MB4518
ELECTRICAL CHARACTERISTICS
(To a +2S0C)
VLI
20
2.9
3.2
3.S
V
VL2
90
6.0
6.S
7.0
V
Vee
20
1.3
1.6
1.9
V
ZTELI
30
SOO
600
700
n
ZYEL2
90
SOO
600
700
n
Handset DC voRage
Supply voltage
Handset AC impedance
Transmit circuit gain
Grv.
V.. --50dBV
30
38.0
41.0
44.0
dB
Grv.
V... -50dBV
90
36.S
39.s
42.S
dB
30
4.0
7.0
10.0
dB
30
-o.s
2.S
dBV
90
4.S
7.S
dBV
8Grv
Transmit circuit dynamic
range
Transmit circuit residual
noise
On
Distortion attenuation:
~
20 dB
Ora
NT.
-56
dBV
GAY.
V... -30dBV
30
-8.0
-5.0
-2.0
dB
G...
V.. =-30dBV
90
-13.0
-10.0
-7.0
dB
GRUP
V.. =-30dBV
30
4.0
6.0
8.0
dB
30
-lS.0
-12.0
dBV
90
-10.S
-7.s
dBV
Receive circuit gain
Receive circuit gain
increase
Receive circuit dynamic
range
DR.
Distortion attenuation: ~ 20 dB
0 ...
Gs..
V... -30dBV
30
4.0
7.0
10.0
dB
Gs..
V.. =-30 dBV
90
0.0
3.0
6.0
dB
30
-22.0
-19.0
dBV
90
-ll.S
-8.S
dBV
Speaker circuit gain
Speaker circuit dynamic
range
Balance network switching
Os.
Distortion attenuation: ~ 20 dB
0 ..
IFN
Far -+ near
43.0
55.0
70.0
mA
INF
Near -+ far
32.s
42.S
52.5
mA
IH
Hysteresis width
9.0
12.5
27.5
mA
.: Design guaranteed
7-37
MB4518
TEST CIRCUITS
•
Test circuit
R9
C6
C5
+
Rl0
RPO
}------{4
Pad
insertion
control
RPI
3
Une
current
detector
R2
7-38
MB4518
•
DC characteristics test circuit
r-----~~~--------__;VL
Vee
BNlr--------,
BN2
IL
~----~---+----~~~GND
Abstracted from the electrical characteristics circun
IL
: Current source (AC impedance ~ 60 kQ, 1 kHz, 30 mAl
® : DC vottmeter
Balance network swnching
IF.
INF
The tolerance of the load impedance for each pin shall be ±1%. (All test circuits)
Note:
•
When IL increases from 30 mA to 70 mA
IL (mA) for which VBN2 increases from 1.5 V to 3.5 V or more
When IL decreases from 70 rnA to 30 rnA
IL (rnA) for which VBNl decreases from 3.5 V to 1.5 V or less
Transmission characteristics test circuit
VL
TIl
TI2 r---~-----I
IL
MFIN
GND
1----...-----.
GND
Abstracted from the electrical characteristics circu~
o:
Oscillator (Output impedance and DC resistance :s; 4 Q at 1 kHz)
IL
: Current source (AC impedance ~ 60 kQ, 1 kHz, 30 rnA)
® : AC vottmeter
Transmn circuit gain:
Grv (dB) = 20 Log V3Nl (oscillator 1)
GMFV (dB) = 20 Log V3N2 (oscillator 2)
Dynamic range
: The distortion attenuation with the output signal level fixed is at least 20 dB.
Residual noise
: Measure the transmtt output signal level with no transmit input signal.
7-39
MB4518
•
Receive characteristics test circuit
VL
RGU
GND 1 - - - - - - '
RO 1-------,
IL
GND
GND
Abstracted from the electrical characteristics circuit
o .:
Oscillator (Output impedance and DC resistance :s; 4 n. f - 1 kHz)
IL
: Current source (AC impedance ~ 60 kn. 1 kHz. 30 mAl
® : AC vokmeter
Receive circuit gain:
GAY (dB) _ 20 Log V4N3
: Measure the V3 AC signal level boost when SWl is closed.
•
Gain boost
•
Dynamic range : The distortion attenuation with the output signal level fixed is at least 20 dB.
•
Speaker characteristics test circuit
VL
SPSW
GND J - - - - - - - l
SPO 1 - - - - - - ,
IL
GND
GND
Abstracted from the electrical characteristics circuit
o:
Oscillator (Output impedance and DC resistance s 4 n. f = 1 kHz)
IL
: Current source (AC impedance ~ 60 kn. 1 kHz. 30 mAl
® : AC voltmeter
Speaker system gain: Gsv (dB) = 20 Log V5N3 (SW2 open)
•
7-40
Dynamic range : The distortion attenuation with tl)e output signal level fixed is at least 20 dB.
MB4518
•
Test circuit components
7-41
III
MB4518
TYPICAL CHARACTERISTIC CURVES
DC characteristics
AC impedance loop current
8
-
V
6
VL(V)
f= 1 kHz
800
10
,."
/
,.. i"""
4
./
600
-
lm(O)
400
2
;;
0
20
40
60
80
100
120
0
20
40
60
Transmit gain loop current characteristic
100
120
Receive gain loop current characteristic
0
!.Vim =-50
f= 1 kHz
dBV
45
!.Vim=..,'3()dBV
f= 1 kHz
,.
, ---.. .......
40
80
IL(mA)
l"mA)
--.....
-10
GTV(dB)
~~
GRV(dB)
-20
35:
0
;;
20
40
60
80
100
120
0
20
60
40
Transm~
Speaker gain loop current characteristic
10
.I.
;t""
~
80
100
120
"(rnA)
l"mA)
f= 1 kHz
Vim =-30 dBV
input vs. output characteristic
/
0
(
r--...... ~
0
-20
GSV(dB)
/
Vl-GND level
(dBV)
f=lkHz
1c=30mA
V
-40
-10
~
;
0
20
40
60
"(rnA)
7-42
80
100
120
-80
-80
-40
Tn - T,2 input level (dBV)
-20
MB4518
--
Transmit dynamic range loop current characteristic
Receive dynamic range loop current characteristic
10
-5
~
5
V
/
/ '"
DT (dBV)
0
f= 1 kHz
Dis =,20 dB
20
~
DR (dBV)
-15
-5
0
V
V
-10
60
40
100
80
f= 1 kHz
-20
;.
120
Dis ="120 dB
0
40
20
lc(mA)
/'"
-15
I
Ds(dB)
-20
V
".".,
GTV(dB)
20
120
,...
,...
1L=30mA
.........
IL= 9b
mi:'
f= 1 kHz
Dis =120 dB
t"
0
100
Transmit frequency response
40
V
-25
80
45
/"
/
60
IdmA)
Speaker dynamic range loop current characteristic
-10
- -
40
60
80
100
35
.,:;
120
0.3
0.5
1.0
3.0
IL(mA)
f(kHz)
Receive frequency response
Speaker frequency response
0
10
5.0
1.
!c=30mA
--...
~~
IL JmA
-10
~
IL=~~
GRV(dB)
-20
""i'-
-......... r--.....
0
!c=90mA
GSV (dB)
-10
;;
0.3
0.5
1.0
f(kHz)
3.0
5.0
0.3
0.5
1.0
3.0
5.0
f(kHz)
7-43
MB4518
PACKAGE DIMENSIONS
28-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-28P-M031
.400(10.16)
TYP
~----------
1.024
~:g~~
(26.00~:~g)
----------~
.070(1 778)MAX
-I
I
~
.070±.007
(1.778±0.18)
II
~
r r ~
HHH)-{.H
V
.039:J1 20
(1.00~g.50)
ij--11~ ..~
HI-l
018±.004
(0.45±0.10)
p
~
i !'m"~'.~
.118(3.00)·MIN
.020(0.51 )MIN
.910(23.114)REF
Dimensions In
inches (millimeters)
7-44
MB4518
PACKAGE DIMENSIONS
2B-LEAD PLASTIC FLAT PACKAGE
(Case No. : FPT-28P-MOI)
.110(2.80) MAX
(MOUNTING HEIGHT)
.362±.012
(9.20±0.30)
INDEX
if
====tI
.020±.008
(0.50±0.20)
-L006~ggt(0 15~g:g~)
r--- ---- -------,
Details of "A" part
'"A"
.008(0.20)
.024(0.60)
"------.650(16.51) R E F - - - - - J
I
I
I
.007(0.18)
MAX
.027(0.68)
MAX
1....-------------Dimensions in
inches (millimeters)
7-45
MB4518
III
7-46
OJ
FUJITSU
June 1991
DATA SHEET
MB4752A
Subscriber Line Interface Ie
The Fujitsu MB4752A is designed for PBX (Private Branch Exchange), and has
battery feed, supervision, and 4-wire-to-2-wire conversion functions.
The battery feed mode can be set to a 200 x 2 or 440 x 2 constant feed resistor by
using the terminal connection.
The subscriber line interface circuit is used for dig~al PBX and CO. This device can
be used worldwide to achieve high longitudinal balance with 4W-to-2W gain and
characteristics by adjusting the external resistor.
•
•
•
•
•
•
•
440 Q x 21200 Q x 2 feeding resistance
Loop detection function
Line fauH protection
Hybrid function (4-wire to 2-wire conversion function)
Ring trip comparator
BalanCing impedance is selected by external parts
Digital output terminal has open-collector output with a pull up resistor
28-pad LCC package:
(Suffix: -TV)
LCC-28C-F01
Pin Assignment
PB PE G Z RTPB NC Vee
ABSOLUTE MAXIMUM RATINGS
Rating
Power Supply
VoHage
Input Voltage
Storage
Temperalure
Symbol
Value
Unit
Note
Vas
-60 to +0.5
V
Referenced to GND
Vcc
-0.5 to +7
V
VEE
-7 to +0.5
V
Referenced to E
Referenced to GND
VEG
-7.5 to +0.5
V
VA
Vss -0.5 to +0.5
V
VB
VSB -0.5 to +0.5
V
RTPA
VBB-0.5 to VBB +30
V
RTPB
-30 to +0.5
V
Vow
VEE -0.5 to Vcc +0.5
V
TSTG
-55 to +150
°C
B'
SCNB
SCNA
NC
B
CB
NC
CA
E
4W
VEE
A
A'
Rf
Referenced to GND
NB NE VBB RTPA NC ZT Vo
Referenced to E
Note: Permanent device damage may occur Wabsolute maximum ratings
are exceeded. Functional operation should be restricted to the conditions as detailed in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Th. devk:e contains c:lraJltry to protect the Inputs against
damage due to Ngh Italic vollages Of electric flelds. HOMMN'.1l
II advised that normal precautions be taken to avoid application
of any vo/Iag8 higher than maximum rated volages to this high
lfT1*Iance circuit.
© 1991 by FUJITSU LIMITED and FujitmJ MicnJelect....k:8.lnc.
7-47
MB4752A
Figure 1. MB4752A Block Diagram
PE
PB
G
ZT
"T
"
Vo
J,
Ckt-
l
4W-2W
Interface
Circuit
Rf
f-'
4W
-+
.... _--------B
Battery
Feed
Control
Circuit
CB
CA
A
Ring Trip
Comparator
NE
+Vee
~
z
SCNB
Digital
Output
Circuit
Loop
Detection
Circuit
,L
RTPB
RTPA
E
C
VEE
MB4752A
PIN DESCRIPTION
Description
Pin No.
Symbol
1
NC
No Connection
2
CA
High-impedance capacitor pin. A capacttor is connected between this terminal and CB
terminal. AC impedance of Battey Feed circuit is made up to high impedance by this
external capacttor.
3
A
440 n battery feed for line A
4
A1
200 n battery feed for line A
5
NB
Base drive output for the NPN power transistor
6
NE
Emitter current sensing input for the NPN power transistor
7
Vaa
8
RTPA
Most negative voltage supply, --48 V
Ring-trip input for line A
9
NC
No Connection
10
ZT
4 W to 2 W transformation impedance
11
Vo
4 W to 2 W gain setting resistor input
12
At
4 W to 2 W gain setting resistor input
13
VEE
Negative voltage supply, -5 V
14
4W
4-wire input
15
E
16
NC
17
SCNA
SCN detecting output for line A
18
SCNB
SCN detecting output for line B
19
Vee
20
NC
21
RTPB
Ground
No Connection
Positive vottage supply, +5 V
No Connection
Ring trip input for line B
22
Z
Compensation capacttor input
23
G
Ground
24
PE
Emitter current sensing input for the PNP power transistor
25
PB
Base drive output for the PNP power transistor
26
B1
200 n battery feed for line B
27
B
440 n battery feed for line B
28
CB
High-impedance capacitor pin. A capacttor is connected between this terminal and CB
terminal. AC impedance of Battery Feed circutt is made up to high impedance by this
external capacttor.
7-49
MB4752A
FUNCTIONAL DESCRIPTION
Battery Feed
By selecting connection A, B or A', B', balanced feeding resistance of 440 n for PBX or 200 n for CO application is selected.
Loop Detection
The digital signal output indicates the handset condition as off the hook, both the SCNA and SCNB terminals simukaneously, by
detecting the current that is generated when the handset is off the hook.
Line Fault Protection
Line fau~ protection outputs the signals when line A or B is short circu~ed to SCNA and SCNB, respectively.
When excesscurrentflows, arrester provides system protection, and DC feeding resistance becomes six times as large as the normal
value. As a resuk, current decreases.
Hybrid (Four-to-two wire conversion)
Asforthe communication channel, the telephoneswnching system has a four-wire line internally, and the telephone set system has a
two-wire line. This device also has a bui~-in four-wire to two-wire converter. The two-wire to four-wire converter contains external
common industrial operational amplHier.
Ring Trip Comparator
~
is necessary for the electrical telephone swnching system to detect that the receiver is on the hook during a calling signal.
Ring trip detection is performed by connecting external low pass fi~er to the input RTPA or RTPB terminal. The output signal is
superimposed on the trip supervise SCA when the handset is on the hook.
III
RECOMMENDED OPERATING CONDITIONS
Parameter
Condition
Unit
VBB
-48±S
V
Referenced to GND
Vee
S.0±0.2S
V
Referenced to E
VEE
-S.0±0.2S
V
VEG
-{l.S to +O.S
V
Referenced to GND
At
oto 1200
Line resistor +
200 Q Feeding Loop Resistor
At
Oto 1900
n
n
Low Frequency Inductive Current
lAC
Ot06.4
mArrns
Input Offset Voltage
VRCs
-{l.2to 0.2
V
Input Voltage
S4W
7.0
dBm
Top
St070
°c
Power Supply Voltage
440 Q Feeding Loop Resistor
2W
4W
Operating Temperature
7-50
Symbol
Note
terminal resistor
Single line current f = S0I60 Hz
MB4752A
DC CHARACTERISTICS
(Recommended operating cond~ion unless otherwise noted.)
Symbol
Parameter
CondHlon
ISSl
Power Supply Current
440 n Feeding Mode
200 n Feeding Mode
1\tp.
Max.
UnH
-3.8
-
mA
6.6
1cc,
Va=OV
-
2.5
IEEl
VA - Vas
-2.2
-1.1
Off-Hook
1_
Va =-26.5 V
-13
-8
RL-On
Icc2
VA- Vas
Vas--53 V
-
-
2.5
6.4
mA
IEE2
+26.5 V
Vrx;=5.25 V
-2.2
-1.2
-
mA
VEE--o.25V
-7.5
-4
mA
VEG=OV
-
-
2.5
6.6
mA
-
mA
On·Hook
laB3
Power Supply Current
Min.
-6.4
On-Hook
1003
Va=OV
mA
mA
mA
IEE3
VA = Vaa
-2.2
-1.1
Off-Hook
ISB4
Vs=-26.5 V
-15.6
-9.5
RL=On
IcC4
VA = Vas
-
2.5
6.4
mA
IEE4
+26.5 V
-2.2
-1.2
-
mA
mA
7-51
MB4752A
DC CHARACTERISTICS (Continued)
(Recommended operating cond~ion unless otherwise noted.)
Parameter
Power Supply Current
440
n
Feeding Mode
Loop Supply Current
200
n
Feeding Mode
Une-Fau~
440
Drooping Current
n Feeding Mode
Une-Fau~ Drooping Current
200
n Feeding Mode
Loop
Detection
Current
DI
200
n Feeding Mode
Une-Fau~ Detection VoH.
440
n Feeding Mode
Une-Fau~
"lYP.
Max.
VB =-24 V
47.5
54
65
mA
IBl
VA = VBB +24 V
-65
-54
-47.5
mA
VB s-l0V
VBB =-48 V
16.8
21
26.5
mA
VA = VBB +l0 V
Vee=5.0V
-26.5
-21
-16.8
mA
1A3
VB =-24 V
VEE --5.0V
72.5
83
91.4
mA
IB3
VA = VBB +24 V
VEG=OV
-91.4
-83
-72.5
mA
mA
1M
VB =-10V
35.7
45
58
184
VA = VBB +l0 V
-58
-45
-35.7
mA
IpG1
VA=GND
VBB=-53 V
-
22
28
mA
-
mA
36
mA
IPBl
VB = VBB
Vee=5.0V
-28
-22
1PG2
VA=GND
VEE =-5.0 V
-
29
IpB2
VB - VBB
VBB = --43 V
VEG-OV
-36
-29
Vee = 5.0 V
11.1
12.4
14.2
mA
IoNl
Release
IOFFl
1oN2
Release
IoFF2
RTPA
VR01
RTPS
UneAto GND
mA
10.4
11.5
13.4
mA
VEG=OV
14.4
16.0
18.1
mA
13.4
14.8
16.6
mA
On-hook
-44
--43.3
-42.5
V
V RD2
On-hook
-5
-4.4
-4
V
VG01
VB-Open
VBB =-48 V
24
26.5
30
V
VA-Open
Vcc=5.0V
24
26.5
30
V
VB -Open
VEE =-5.0 V
11
15.5
21
V
VA=Open
VEG= 0 V
VGD2
Line S to VBB
SCNA
-
VEE =-5.0 V
Line Sto V BB
SCN
Unit
1A2
Detection
UneAtoGND
Condition
IB2
Detection
Ring Trip Detection Volt.
Une-Fautt Detection Volt.
Min.
IAl
Symbol
IMA
VBB = -53 V
11
15.5
21
V
VB = VBB
3.3
4.4
5.9
mA
-5.9
-4.4
-3.3
mA
0.02
0.4
V
V
Mask Current
SCNS
1MB
VA=OV
SCNOutput
SCNA
VOLA
1=1.2mA
-
Low Voltage
SCNS
VOLB
Vcc =5.25 V
On-hook
VBB=-48 V
-
0.02
0.4
SCNOutput
SCNA
VOHA
VEE =-5.0 V
2.4
3.8
-
V
VEG = OV
Ref.toE
2.4
3.8
-
V
High Voltage
Nole:
7-52
SCNS
..
VOHB
1= -50
J.lA
Vee.-4.75 V
Off-hook
Unless RTPA terminal IS In use, It must be connected to VBB.
MB4752A
AC CHARACTERISTICS
(Recommended operating condRion unless otherwise noted.)
Parameter
4W\o2WGain
Symbol
Condition
Min.
Typ.
Max.
G42
L - +'IdBm. f - 1kHz
-5.4
-4.4
-3.4
dB
-0.1
+0.07
-
dB
f - 0.2 kHz
1- 0.3 kHz
4 W \0 2 W Gain Frequency Response
Gt42
-0.1
+0.04
+0.2
dB
1.0.4kHz
Referenced
-0.1
+0.02
+0.2
dB
f = 0.6 kHz
to output at
-0.1
0
+0.2
dB
f - 2.4 kHz
f-l kHz
-0.1
-0.01
+0.2
dB
f=3.0kHz
L = -10 dBr
-0.1
-0.01
+0.2
dB
-0.1
-0.01
+0.2
dB
f-3.4kHz
4 W to 2 W Gain Level LinearRy
Idle Channel Noise
G142
L=+3dBr
Referenced
-0.1
0
+0.1
dB
L =-40 dBr
to output at
-0.1
0
+0.1
dB
L=-50dBr
L_-l0dBr
f-l kHz
-0.2
0
+0.2
dB
-
N'2
4Wt02W
SN42
SignallNoise Ratio
L- OdBr
L _ -30 dBr
1=1 kHz
L.-40 dBr
L _-45 dBr
Longitudinal Balance
LB2W
Vssto2W
PSRS
Power Supply
Vcct02W
PSRe
Noise Rejection
VEE t02W
PSRE
Note:
Unit
-94
-76
dB
50
57
-
dB
46
61
36
52
-
dB
-
dB
-
dB
31
47
f = 0.3 kHz
Adjust
43
60
REA
43
60
-
dB
f= 1.0 kHz
f-3.4 kHz
48t0530
VEGt02W
PSRR
Unless RTPA term,nal,s ,n usa, ,I musl be connected to Vss.
dB
43
60
-
dB
20
39
-
dB
L=0.24 Vrms
20
41
-
dB
f= 1 kHz
20
55
20
43
-
dB
dB
7-53
MB4752A
SCN Logical Table
SCNA
SCNB
Il ION
Loop Release
It < IOFF
H
H
ION: IONI.IaN2
H
H
IOFF: 10m,
(On-hook to Off-hook) Il > IOFF
L
L
See DC Characteristics
Input Condition
Loop Detection
Loop Detection
RTPAlnput
Ring Trip Detection
RTPBlnput
Une A to Ground
Line-Fault Detection
Une B to Ground
III
Note:
Note
IoFF2
VRTPA< VRDI
L
L
VRTPA : RTPA Input Volt.
VRTPA • VRDI
H
L
VRTPS : RTPB Input VoR.
VRTPs ION *2 and
IB < 1MB
H
L
IA: Line A Current
IA + IB > ION *2 and
IB>IMB
H
H
IB: Line B Current
IA+ IB < ION *2
L
L
IMA: See DC Char.
IA + lB.> ION *2 and
IA ION *2 and
IA>IMA
H
H
..
Unless RTPA tellmnails HI use, itmusl be connected to Vss.
Line Fault Protection
2WStale
Line to GroundNss
7-54
Feed Mode
Note
VA: Une A Voltage
VB: Line B Voltage
I VB + (VA -
Vss I < VGD
I VB + (VA -
VGD, VGD1, VGD2: See
Vss I > VGD Feeding Resistor (6 times that of normal value) DC Char.
Normal Feeding (No Protection)
MB4752A
Figure 2. Power Supply Mode (440 0)
60W
0.011lF
ZT
4W-2W
Interface
Circu~
.
-----------,
B
1 IlF
15 IlF
600 0
~CB::l)_ _--1 Battery
Feed
CA
Control
Circuit
Loop
Dig~al
Detection
Circuit
Output
Circu~
A
D=
DCCircu~
Z
RTPB
RTPA
IO.1 1lF
I
-48V
7-55
MB4752A
Figure 3. Power Supply Mode (200 Q)
J 1
REB
PE
PB
BS
MB4752A
As
AS
NB
NE
REA
VBB
28-PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER
(Case No.: LCC-28C·F01)
III
.085 2.16
TYP
r
PIN NO. 1 INDEX
n
C.04O 1.02 TYP
(3 PLCS)
.445 (11.30)
.460 (11.68)
.300(7.62)
TYP
C.01S 0.38)
TYP
.445-'11.30)
.460 (11.68)
.050 1.27 TYP
.105 (2.67) MAX
7-56
00
FUJITSU
January 1990
DATA SHEET
MBB700 7AlMBB700BA
DTMF Pulse Dialer
The Fujitsu MB87007A1MB87008A is a Dual Tone Multnrequency (DTMF)
pulse dialer for pushbutton telephone sets. It uses the Si-Gate CMOS
process and is suitable for both DTMF and PULSE modes. The
MB87007A1MB87008A can be switched from a PULSE mode to a DTMF
mode by a mode selection entry or by an input from the keyboard. It has a
26-dign redial memory that permns the coexistence of PULSE and DTMF <6l
modes and enables mixed redialing in both PULSE and DTMF modes by a ~
signal key entry.
• Redial inhibit function is
included for redial memory
overflow
• Pulse 10 pps. 20 pps. or
DTMF operation that is
selected by the mode swnch
pin (MODE IN)
PLASTIC PACKAGE
DIP-18P-M02
• PAUSE function is provided
and pause accumulation is
possible
• On-chip 26 digits of redial
memory (up to 25 digns can be
wrnten into the memory)
• FLASH function is provided
(ON HOOK mbde is selected
by keyboard input)
• MB87007A has a make ratio of
39% and MB87008A has a
make ratio of 33%
• Crystal or ceramic oscillator
(3.579545 MHz) can be used
• LDT function is provided
(swnching from PULSE mode
to DTMF mode by key entry)
PLASTIC PACKAGE
FPT-24P-M02
• Pause release function is
provided (two or more
consecutive pauses can be
released)
• Beep tone for input
confirmation can be output (for
all effective key entry
independently PULSEIDTMF
modes)
• Operating voltages:
PULSE mode: 2.0 V to 6.0 V
DTMF mode: 2.5 V to 6.0 V
• Mixed redialing of both PULSE
and DTMF modes is possible
PIN ASSIGNMENT
0
Voo -
18
-g~~t6UT
17 _'ROWT
roIT-
(TA = -30 to 60°C)
"CO[2' _
"COI:3_
'001:4-
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Pin Name
Power Supply Voltage
Voo
Voo
Value
GND-0.3to7P
MODEIN_
Unit
V
13 - POLSEOOT
MODEOUTOSCIN _
OSCOUT-
Input Voltage
VI
All inputs
GND - 0.3 to Voo + 0.3
V
Ouput Voltage
VO
All outputs
GND - 0.3 to Voo + 0.3
V
Storage TemPerature
TSTG
-05 to +150
°c
(DIP-18P-M02)
Note: Permanent device damage may occur n absolute maximum ratings
are exceeded. Functional operation should be restricted to the conditions as detailed in the operation sections of this data sheet. Exposure to absolute maximum rating condnions for ex1enlled periods
may affect device reliabilny.
©
FPT PIN ASSIGNMENT
See Page 6-88
This device contains circuitry to protect the inputs against damage due
to high aleile voltages or electric fields. However, it is advised that
normal precautions be taken to avoid application of any voltage higher
than maximum rated voltages to this high lrJ1)8dance circuli:.
1991 by FUJITSU LIMITED and Fujitsu Microelectronics. Inc.
7-57
MB87007A
MB87008A
Figure 1. MB87007A1MB87008A Block Diagram
OTMF Generator
OSCIN~
OSCOUT(
:t ""'.
r----------------,
rI
~L
+L
C.",,,
SM.·
~
I
:+:f
I
r
I
I
RowProg.
{)
I
Wave
Adder
Column prog'
Gen.
Counter
..
IL _________
-.-
I
------..1
MOOEIN
External
Keyboard
1
4
I ROWf
2
P
l....,.
MOOEOUT
-
IR0W2
I
Control
Logic
CircuH
~
- rr-
3 RED
5 6
~( )~
-,
I
r- Pulse
I ROW3
7 8 9 LOT I
01
.o
#
F
r~
II ROW4
II
I
IroIA
loom
i
I
Keyboard
Logic
CircuH
Output
Generator
~f)
I
Memory
CircuH
Yf)
I
I "OOI2
I
I rorr
I
I
()
HKS
7-58
OTMFI
BEEPOUT
BeepTone
Generator
6 6
Veo
GNO
~
pOLSEOOI
MB87007A
MB87008A
PIN DESCRIPTIONS
Pin No.
110
DIP
FPT
Symbol
1
1
Voo
10
12
GND
Description
Power supply voltages:
Power
Supply
2
2
corr
3
3
~
Pulse mode 2.0 V to 6.0 V
DTMF mode 2.5 V to 6.0 V
Memory Retention mode 2.0 V min.
Ground
Uses key entries from 2 of 7 or 2 of 8 keyboard with common GND. This Ie is
available with a single contact Irom A type key board and electronic input (Low
entry).
4
4
~
5
5
COlA
Key input release guard time is 23 ms typo for both PULSE and DTMF modes.
17
23
16
22
15
21
ROWT
FlOW2
ROW3
14
20
ROW4
Key entry is accepted in PULSEIDTMF mode only when a single key (one key on
the keyboard) is pressed longer than the debouncing time. If two or more keys
are pressed, they are not accepted unless they are released one-by-one and the
last key is held closed longer than the debouncing time, after all other keys are
released.
Key input debouncing time is 23 ms typo lor both PULSE and DTMF modes.
Key entry is accepted in DTMF mode only when etther a single key (dual-tone
key) is pressed, ortwoor more keys in the same CO[or FIDW (single-tone keys)
are pressed longer than the debouncing time. If even one key is pressed in
COlA, the single-tone keys are ineffective. When muttiple single-tone keys are
pressed, il they are released one-by-one, and the last key is held closed longer
than the debouncing time (after all other keys are released), the key is effective
as the dual-tone key.
Input
Hereafter, key entries are described with the premise that keys are held closed
longer than the debouncing time.
Pauses between key entries in PULSE and DTMF modes must be 50 ms or
more. However, up to 50 ms is necessary from key entry to output start for a
single-tone output.
Key switch contact resistance up to 5k.Q is allowable.
6
8
MODE IN
This pin selects the pulse 10 pps, 20 pps and DTMF mode.
Setting
Mode
10 pps
PULSE made:
DTMFmode
20pps
Open (1 M n or more)
Voo
GND
When mode swttching is requested by MODEIN during PULSE or TONE
transmission, the request will not be accepted.
The request is accepted by key entry alter data entry transmission is completed.
In ON HOOK mode, MODE IN is set to a high impedance state.
Contmued on next page
7-59
MB87007A
MB87008A
PIN DESCRIPTIONS
Pin No.
110
Input
DIP
12
FPT
15
Symbol
HKS
Description
Hook switch input pin.
ON HOOK Mode
OpenorVoo
OFFHOOK Mode
GND
g~~Et is inhibited in ON HOOK mode and POLSEOOT, DTMFIBEEPOUT,
, and MODEOUT are set at a high impedance state.
All key entries are set to HZ and the on-chipoperational amplifier and oscillator
(OSCIN = l, OSCOUT = L) become power down states.
This pin is pulled up by a high resistance internally.
The input level is in the CMOS level.
S
10
OSCIN
9
11
OSCOUT
Oscillator input pin.
This pin is pulled up by a high resistance in ONHOOK mode.
Oscillator output pin.
This pin is pulled down by a high resistance in ONHOOK mode.
The output level is in the CMOS level and set to a high impedance state in
ONHOOK mode.
Low level is output in the PULSE mode and high level is output in the DTMF
mode, including the LDT function.
MODEOUT blinks on and off at a frequency of 2.5Hz typ., if there is no pause
before and after mode switching in redial function.
Independent of PULSElDTMF modes, the beep tone is output at the BEEPOUT
when the FLASH key is pressed. The MODEOUT pin is output low level during
the beep tone output. High impedance of 0.6 second typo is output!ollowing the
beep tone output. The key acceptance state (OFFHOOK mode) is now entered.
7
9
MODEOUT
11
13
lJOTE
N-channel open drain output.
The following are lJOTE pin HZ conditions during PULSElDTMF modes.
1. There is no key entry.
2. When the FLASH key is pressed, HZof 0.6 typo second is output after the beep
tone is output.
3. During pause output state. (However, when a key is pressed,lJOTEis low level while beep tone is being output.)
4. During MODEOUT blinking.
After key entries become effective in the PULSE or DTMF modes, the output
level is low during the beep tone transmission, pulse transmission in accordance
with effective key entries, and DTMF output transmission.
13
16
pOLSEOOI
N-channel open drain output.
High impedance (HZ) is set in ONHOOK or DTMF modes.
In PULSE mode, this pin is set low for pulse brakes, according to numerical key
entries.
When the FLASH key is pressed in either the PULSE or DTMF mode, a low level
is output for 600 milliseconds typo after the beep tone is sent (even during a
PULSEIOTMF send). The key acceptance state (OFFHOOKstate) then returns.
The make ratio for PULSE output is 39% for MB87007A and 33% for MB87008A.
Output
Continued on neKl page
7-60
MB87007A
MB87008A
PIN DESCRIPTIONS
Pin No.
I/O
DIP
FPT
Symbol
Description
18
24
DTMFI
BEEPOUT
The DTMF/BEEPOUTpin is a bipolar emitter follower that can drive a lOOn load
between pin and GND.
In the DTMF mode (exclude 'CODr) when a single key (numeric,
or 0) is
pressed, a dual tone is output.
Pressingtwoor more keys in the same ROW or 00[ on the keyboard outputs the
signal tone in the ROW or 00[.
However, ff a key in 'CODr is pressed, DUAL TONE or single tone in the ROW or
00[ is not output (see Electrical Characteristics).
If the FLASH key is pressed during DTMF sending, the beep tone is output at
BEEPOUT and subsequent DTMF tones are not output. The ONHOOK mode is
entered for 600 millisecondstyp. afterwhich, MODEIN and key entries are placed
in the acceptance state (OFFHOOK mode).
Beeptone (key entry confirmation tone) is output in PULSE mode. The 41 ms typo
beep tone (1 kHz square wave) is output when the following keys are pressed.
1. Numerical key entry.
2. First LDT key entry (subsequent LDT key entries are ineffective).
3. Pause key entries:
or
key. (However, if the first key after OFFHOOK is
the PAUSE key, the key entry is ineffective or not accepted.)
4. Redial key entries: 00r @[)* key. (They are effective only when the redial
key is the first key after OFFHOOK.)
eJ
eJ ®
III
eJ, ®,
5. PAUSE release key entries:
or [RED I key. (They are accepted only
during redialing and effective only when MODEOUT is blinking or at a pause
time during redialing.)
6. FLASH key entry:
key. (For FLASH key entry, the beep tone is output in
PULSE and DTMF modes.)
When two or more keys are pressed simuttaneously, that is, double or multiple
key entries, the key entries are ineffective and the beep tone is not output. If
DTMF mode tone request is received during a beep tone transmission, the beep
tone is terminated even though the duration is 41 ms or shorter and DTMFtone is
output.
DUAL TONE output time cond~ions are as follows:
1. 80 ms typo for redial output.
2. 80 ms typo when the key entry time is within 130 ms typo and more than the debouncing time.
3. DUAL TONE output is stopped at once if a key is pressed over 130 ms typo and
released.
4. Signal tone is outputfrom the end of debouncing time until the key is released.
5. When a beep or DTMF tone is not being output, this pin is placed in a high imoedance state.
®
.
( RED) = Redial key
7-61
MB87007A
MB87008A
FUNCTIONAL DESCRIPTIONS
Ordinal Dialing
In the OFFHOOK mode, PULSElDTMF signals are output according 10 the key input, regardless of number of key input figures. Forthe
PULSE mode, any numberofdigital entries with keys 010 9. Forthe DTMF mode, any numberofdigital entries with keys Oto 9,
eJ and
0·
Upto 26 digits can be stored in the redial memory. In the PULSE mode, a redial digit is counted for any numeric, pause, and LOT entry.
In the DTMF mode, a redial digit is counted for any numeric,
e::J, 0, and 0
entry.
In both the PULSE and DTMF modes, one digit is counted as mode information when MODEIN is used for mode switching. After
OFFHOOK, the first numeric entry is counted as mode digit. In the PULSE mode the numeric key is counted as a mode digit. In the
e::J,
0
DTMF mode, a numeric key,
and
entry is counted as a mode digit. In either the OFFHOOK or PULSE modes, the
mode-information digit is written into the redial memory.
Redialing Function
The redial memory is read out to execute the redialing operation when a redial key is the first key pressed in OFFHOOK state. In the
PULSE mode, the redial keys are
0
and
e::J. In the DTMF mode, only the ~ key is accepted for redial.
When 27 or more digits are written into the redial memory, PULSE or DTMF signals that correspond to the key entries are output, but
the redialing operation is ineffective because of memory overflow. At this time, even if the first key pressed after the state change from
ON HOOK to OFFHOOK is the redial key, the entry is not accepted and the beep tone is not output in either mode of operation.
e::J, 0
AfterOFFHOOK, if a numeric or LOT key is the first entry in PULSE mode, or the first entry in the DTMF mode is a numeric,
or
a single-tone key entry (excluding COIA), the redial memory is cleared and data is written into memory according to key entry
information.
Mixed Redialing
Mixed redialing is executed when the mode is changed from the PULSE 10 DTMF mode (done by pressing the LOT key), or when
MODE is changed during key entries.
H, at redialing, there is a pause before or after mode switching (including LOT), PULSElDTMF is sent and PULSElDTMF signals are
transmitted after the pause. To redial when there is no pause before or after mode switching (including LOT), all operations must cease
after mode switching and a HALT state is enabled. MODEOUT blinks (indicates that mode switching has no automatic pause) and
prompts a pause release.
e::J,
0
0
The pause release keys in PULSE mode are
~,and the
key. In the DTMF mode, the ( RED) and the
keys are used
for pause release. PULSE and DTMF signals can now be sent by key entry. The FLASH key, is the only other acceptable entry.
ill
During redial output, the
key is the only key entry accepted. The pause release key is only accepted when MODEOUT is blinking or
during a pause at redialing.
Mode Switching
During PULSE or TONE transmissions, mode switching by MODEIN is not permitted; after transmission is complete, MODEIN can be
used for mode switching.
When PULSE or DTMF modes are swilchpd by MODE IN, one digit is stored into redial memory as mode information. After
OFFHOOK, if the first key entry is numeric in the PULSE mode, or a numeric
is written into redial memory.
7-62
e::J or 0
in the DTMF mode, the mode-information digit
MB87007A
MB87008A
In the PULSE mode, after the LOT key is accepted only one time, the OTMF mode is selected (regardless of MOOEIN pin switching).
The LOT key is not accepted in the OTMF mode. The MOOEIN pin switching enables the desired mode of operation to be selected.
Line Dial Tone (LOT) Function
If the LOT key is pressed in the PULSE mode, the OTMF mode is selected and OTMF tones can be output. In PULSE mode, only the
first LOT key is accepted after key acceptance state (OFFHOOK mode) is entered. Once the LOT key is accepted, the following LOT
key entries are ignored.
When the LOT key is used to enter the OTMF mode, all keys (excluding "COlA keys) provide dual-tone and single-tone outputs. (Note:
If even one "COlA key is pressed, neither dual nor single tones are output.) The mode after that is not switched. If mode switching by
LOT from memory is done during redialing, key entries after redialing are executed in OTMF mode regardless of the MOOEIN state
and the data is written into the redial memory. However, for effective keys (not the redial key) afterONHOOK changes to OFFHOOK,
memory is reset and written in the current mode.
Pause Function
A pause state can be entered by pause key entry.
0
®
®
In the PULSE mode, a pause is introduced by preSSing the
or
keys; in the OTMF mode (including LOT) only the
key is
effective. If a pause key is the first key pressed aiterchanging from ONHOOKto OFFHOOK, the entry is not accepted. One pause key
entry introduces a pause state that is typically 4 seconds; contiguous pause (N X 4 seconds) can be executed by making consecutive
key entries. The pause can be reduced by entering
® or ~ during a redialing pause time.
eJ
Inthe PULSE mode, the
key is used as a pause release key. Multiple pauses can be sent up to 500 times faster by entering a pause
release key, that is, N X 4 seconds becomes N X 800 milliseconds.
Flash Function
Keyboard entries enableONHOOK mode. Only the
® key is used as a FLASH key in both PULSE and OTMF modes (including LOT).
®
When the
key is pressed, the ONHOOK mode is entered for 600 milliseconds (typical), after beep tone is sent. Ouring this time, the
key entry pin is not accepted. MOOEIN, J.roTE, MOOEOUT, and OTMF/BEEPOUT pins are placed in the high-impedance state and
the PULSEOUT pin is set low level. After 600 milliseconds (typical), the return of OFFHOOK is automatic and key entries can again be
accepted.
Test (High-speed Mode)
A test mode circuit is built into the IC. In the ONHOOK state, pins OSCIN and OSCOUT are pulled down by a high resistance. To
activate the test mode, tie the OSCIN high and apply clock signalto OSCOUT. The internal circuit operates upto 128 times faster than
normal operation.
7-63
D
MB87007A
MB87008A
Figure 1. Keyboard Configuration
An example of a single contact type keyboard
_,,..--=---::=7'--=-?-- ROWl
2 of 8 Keyboards
Single Contact Type Keyboard
(Effective with "L" entry)
COIT
"CO[2
~
Legend
COIA
P _;, c:I
Figure 2. Reference Circuit
Voo
l1li
DTMF
Mode
PULSE
Mode
10
pps
(N.C.)
OFFHOOK
CSA3.58MGU
C1, C2 - 30 P
GND
Note:
Key input capacitance (2 to 5.14 to 17 pins): 500 pF.
When electronic input is used. there is no need for connecting a capacitance with key input pins.
7-64
MB87007A
MB87008A
KEY OPERATION DIAGRAM
Redial key for PULSE mode
IRED (P)) = ~
ore!)
Redial key for DTMF mode
IRED (D)) = ~
Pause key for PULSE mode
=
Pause key for DTMF mode
mE)
(LID
Pause release key of PULSE mode
~
=~.{E).oreJ
Pause release key of DTMF mode
(§JQD = ~or{E)
Pause output
®
=
(E)ore!)
(E)
= Pause
KEY ENTRIES IN PULSE MODE
When MODEIN Is set
to 10 pps
PULSE Output
HOOK
Key Entry
MODEIN
10pps
20pps
DTMFOUtput
ON
OFF
OPEN
CD0
1-2
OPEN
( RED (P) )
1-2
ON
OFF
CD
3
ON
OFF
OPEN
( RED (P))
1-2-3
(P1I
1-2-3
( RED (D) )
1-2-3
ON
OFF
Voo
( RED
ON
OFF
GND
0
4
Continuea on next page
7-65
MB87007A
MB87008A
KEY ENTRIES IN PULSE MODE
When MODEIN Is set to 20 pps
PULS.E Output
HOOK
MODEIN
Key Entry
10ppa
20pps
DTMFOutput
ON
OFF
Voo
CD@)
ON
OFF
Voo
[ RED (P)
1-2
I
1-2
ill
3
ON
I
1-2-3
OPEN
( RED (PlI
1-2-3
GND
( RED (D)
I
1-2-3
OFF
ON
Voo
OFF
( RED (P)
ON
OFF
4
0
KEY ENTRIES IN DTMF MODE
PULSE Output
HOOK
Key Entry
MODEIN
10pps
20pps
DTMFOUtput
ON
OFF
GND
CD@)
1-2
ON
OFF
GND
[ RED (Oil
1-2
ill
3
ON
OFF
ON
GND
( RED (D)
I
1-2-3
OFF
OPEN
( RED (P!I
1-2-3
GND
( RED (PJJ
ON
OFF
0
1-2-3
4
onlinuea on next page
7-66
MB87007A
MB87008A
KEY ENTRIES WHEN THE LOT KEY IS USED
When there Is a pause before LOT
PULSE Output
HOOK
Key Entry
MODEIN
10ppa
20ppa
DTMFOutput
ON
OFF
OPEN
ON
OFF
(Dill~
1-2-0
3
1-2-0
3
@D0
GND
( RED (PlI
8)
4
ON
OFF
ON
Voo
( RED (P»)
1-2-0
3-4
OFF
GND
(RED !Ol)
1-2-0
3-4
KEY ENTRIES WHEN THE LOT KEY IS USED
When there Is a pause after LOT
PULSE Output
HOOK
Key Entry
MODEIN
10pps
20pps
III
DTMFOutput
ON
OFF
OPEN
OFF
(Dill@!]
1-2
0-3
1-2
0-3
CIID0
ON
GND
( RED (P»)
8)
4
ON
OFF
ON
Voo
( RED
!PI)
1-2
0-3--4
OFF
GND
(RED (D»)
1-2
0-3--4
ontinued on next page
7-67
MB87007A
MB87008A
KEY ENTRIES WHEN THE LDT KEY IS USED
When there Is no pause before and after LOT
PULSE Output
HOOK
MODEIN
Kay Entry
10ppa
20pps
DTMFOutput
ON
OFF
ON
OFF
OPEN
OPEN
GJ0
@Dill
1-2
( RED (P) )
1-2-MODEOUT
§JID
3
blinks
3
0
ON
OFF
Voo
4
( RED (P) )
§JID
1-2-MODEOUT
blinks
3-4
ON
OFF
GND
( RED (Oil
§JID
1-2-MODEOUT
blinks
3-4
KEY ENTRIES WHEN PULSE/DTMF MODE IS SWITCHED (MIXED REDIAL)
When there Is a pause before mode swHchlng
PULSE Output
HOOK
MODEIN
Kay Entry
10pps
20pps
DTMFOUtput
ON
OFF
OPEN
GJ0~
Voo
ill0ITJfiJ
mc:J rr::lED
GND
OPEN
00
OPEN
( RED (P) )
1-2-0
3-4-0
5-'-0
6-7
ON
OFF
1-2-0
6-7
ON
OFF
Voo
( RED (P) )
GND
( RED (D) )
5-'-0
3-4-0
5-'-0
3-4-0
5-'-0
1-2-0
6-7
ON
OFF
3-4-0
1-2-0
6-7
onvnued on next page
7-68
MB87007A
MB87008A
KEY ENTRIES WHEN PULSE/DTMF MODE IS SWITCHED (MIXED REDIAL)
When there Is a pause after mode swItchIng
PULSE OUtput
HOOK
Kay Entry
MODEIN
10ppa
20pps
DTMFOutput
ON
OFF
OPEN
VOO
GND
CD0
1-2
0-3-4
CIID00
crrumc:J
OPEN
CIID00
OPEN
( RED (P»)
0~7
0--5-·
ON
OFF
1-2
0~7
ON
OFF
Voo
[ RED (Pll
1-2
0~7
ON
OFF
GND
( RED (D»)
1-2
0~7
0-3-4
0--5-·
0-3-4
0--5-·
0-3-4
0--5-·
;onDnuea on next page
7-69
MB87007A
MB87008A
KEY ENTRIES WHEN PULSElDTMF MODE IS SWITCHED (MIXED REDIAL)
When there Is no pause before and after mode switching
PULSE Output
HOOK
Key Entry
MODEIN
10pps
20pps
DTMFOutput
ON
OFF
OPEN
VOD
GND
OPEN
ON
OFF
OPEN
mill
1-2
00
0El
00
( RED (PH
CffiJID
3-4
S-"
6-7
1-2-MODEOUT
blinks
lEJ§D
CffiJID
3-4-MODEOUT
blinks
6-7
S-"-MODEOUT
blinks
ON
OFF
Voo
( RED (PII
CffiJID
1-2-MODEOUT
blinks
lEJ§D
III
CffiJID
ON
OFF
GND
( RED (D) )
CE[]ill
6-7
1-2-MODEOUT
blinks
lEJ§D
CE[]ill
7-70
3-4-MODEOUT
blinks
6-7
3-4-MODEOUT
blinks
S-*-MODEOUT
blinks
5-"-MODEOUT
blinks
MB87007A
MB87008A
REDIAL MEMORY INHIBIT FUNCTION
PULSE OUtput
HOOK
MODEIN
Key Entry
10ppa
20ppa
DTMFOutput
ON
OFF
OPEN
OFF
(DCD ... CDCD
OPEN
I RED
~
IPl)
1-1······1-1
~
ON
OFF
ON
OFF
1-1······1-1
25
~
ON
25
OPEN
CDCD ... CDCD
~
26
OPEN
OPEN
ON
OFF
Voo
ON
OFF
GND
I RED
'2"6"
No output
(RED IP»)
(])
ON
OFF
1-1······1-1
2
(P!
I
2
(RED (P)
I
2
(RED (D»)
2
3
CD
ON
OFF
mDCDCD···
CD CD
~
1 -1······1 -1
OPEN
I RED
1-1······1-1
OPEN
CDCD@DCDCD···
CD
CD
~
OPEN
ON
OFF
~
25
25
(P»)
~
ON
OFF
ON
OFF
1-1
1 -1······1 -1
~
23
23
OPEN
I RED
IP!)
NooU1put
No output
7-71
MB87007A
MB87008A
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Power Supply Voltage
Symbol
Voo
Pin Name
Voo
Input Voltage
VI
All
Inputs
Output Load
Resistance
Ro
DTMFI
BEEPOUT
Operating Temperature
III
7-72
TA
Min
'1\'p Max
PULSE mode and memory
retention mode
2.0
6.0
V
DTMFmode
2.5
6.0
V
0
Voo
V
0.1
20
k.Q
100
k.Q
60
°C
Condition
Between output
pinandGND
DTMFmode
PULSE mode
0.1
-30
10
Unit
MB87007A
MB87008A
ELECTRICAL CHARACTERISTICS
VDD: PULSE mode = 2.0 to 6.0 V, VDD: DTMF mode = 2.5 to 6.0 V,TA =-30 to 60°C
Value
Parameter
Power Supply
Current
Symbol
Pin Name
Condition
5.0
mA
lop
All outpUI pins are
open in PULSE mode
1.0
2.0
mA
All output pins, HKS
pin open in Standby
1.5
10
!lA
All output pins
open in DTMF
1.0
2.0
mA
All output pins
open in PULSE
0.3
0.6
mA
All output pins
HKSopen in
Standby
0.2
1.0
!lA
lOST
Voo
TA=
25°C
TDSTl
VIM
"COIT to COlA
VILl
ROWf to FIOW4
0.8 Voo
Voo
V
1 Voo
.5
V
Voo
V
0
1
.5 Voo
V
VI= Voo
-0.01
1Voo
5
mA
VI=GND
-0.01 Voo
0.01
mA
-10
10
!lA
0
V 1H2
0.8 Voo
IIHl
1111
"COIT to COlA
ROWf TO FIOW4
Key entry HZ
GND::; VI::; Voo
IlZl
1
75 Voo
mA
Voo
0.01
mA
MODEIN HZ
GND::; VI::; Voo
-10
10
!lA
VI =Voo
-10
10
!lA
400
k.Q
VI = Voo
11H2
Digital Input
Current 2
IIL2
Digital Input
Leakage current 2
IIZ2
Digital Input
Current 3
11H3
Pull-up
Resistor
D
HKS, MODE IN
VII2
Digital Input
Leakage Current 1
Unit
2.5
1002
Digital Input
Current 1
Max
All output pins are
open in DTMF mode
Voo=
2.5V
Digital Input
Voltage 2
Typ
100
loOl
Digital Input
Voltage 1
Min
MODEIN
VI=GND
-0.01
-1175
HKS
RpLU
100
200
on&nuea on neKt page
7-73
MB87007A
MB87008A
ELECTRICAL CHARACTERISTICS
Value
Parameter
Digital Output
VoHage
BEEP TONE High
Output VoHage
Digital Output
011 Leakage
Current
III
Symbol
Pin Name
VOH
MODEOUT
Min
TyP
Max
Unit
IoH - -<1.2 rnA
Voo-o.5
Voo
V
IoL~0.5mA
0
0.5
V
Voo-1.0
Voo
V
-10
10
~
MODEOUT,
Va.
POLSEOOi,
mITE
VBTDH
DTMFIBEEPOUT
IOL
POLSEOOI.
~
MODEOUT
External Resistance
when digital input is
open
RolO
Pull-down
Resistance
RpLD
Oscillator
Frequency
OSCIN
ROWfTOR0W4
rorTtor0r4
HKS. MODE IN
PULSE mode
10o.Q is placed between
output pin and GND
GNDSVoSVoo
Resistance connected to
external circu~ when input is open. The other
end of the resistance
.must be between OV and
Voo.
1
ONHOOKmode
75
OSCIN.
OSCOUT
DTMFOutput
VoHage
1Oo.Q placed
between output
pin and GND.
Condition
AouT
DTMFOUT
Redial Memory
Digit
NRKEY
rorTtor0r4
ROWfTOR0W4
Make Ratio
WYAKE
POLSEOOI
loss
Oscillation
Stop time
tossP
Key Entry HZ
Hold lime
IHzKH
OSCIN.
OSCOUT
rorTtor0r4
ROWfTOR0W4
150
300
3.579545
kn
MHz
No signal is output
0
V
OIIset voHage when
signals are output
0.63 Voo
-<1.75
V
DTMF TONE output voltage
1.44
Vp-p
ROW single tone
output voHage
0.64
Vp-p
COLUMN single tone
output voHage
0.80
Vp-p
COLUMNIROW tone ratio
2.0
dB
26
MB87007A
MB87008A
Oscillation
Start time
MO
digits
39
0/0
33
0/0
0
8
16
ms
0
8
16
ms
5
rna
0
( onbnu9d on next
7-74
MB87007A
MB87008A
ELECTRICAL CHARACTERISTICS
Value
Parameter
Symbol
Pin Name
MODEIN HZ
Hold time
tHZMIH
MODEIN
MODEOUTHZ
Hold time
tHZMOH
MODEOUT
COUto "00[4
CondHlon
Typ
Max
UnH
0
5
ms
0
5
ms
0
5
ms
Min
Key Entry HZ
Start time
tHZKS
MODEIN HZ
Start time
tHZMIS
MODEIN
0
5
ms
MODEOUTHZ
Start time
tHZMOS
MODEOUT
0
5
ms
4.15
s
ROWfTOR0W4
pU[SEOUI.
Pause lime
tpAS
MODEOUT Switch
Start time 1
tMoo1
MODEOUT Switch
Start time 2
tMoo2
MODEOUTHZ
Start lime by F
key entry
tMOFs
MODEOUTHZ
Hold lime by F
key entry
tMDFH
0.59
0.6
0.61
s
MODEOUT Blinking
Period
tMOSI
0.39
0.4
0.41
s
MODEOUT Change
Start time by
pause release
key entry
tMOPS
DTMFOUT Output
Start time when
mode is switched
DTMF/BEEPOUT
3.85
4.0
ms
12
2
5
8
ms
ms
72
MODEOUT
ms
28
2
tMST
10
15
ms
DTMF/BEEPOUT
DTMFOutput
Start time by
pause release
key entry
!POT
pU[SEoU I Output
Hold time
by F key entry
tpuFH
ms
39
0.59
0.6
0.61
s
pULSEOOT
pOLSEoOI
OUTPUT
Start time by
F key entry_
tPUFS
72
ms
( onMuec1 on next p8,
7-75
MB87007A
MB87008A
ELECTRICAL CHARACTERISTICS
Value
Parameter
Symbol
Pin Name
CondHlon
Min
1YP
Max
UnH
Key Entry Width1
tWKl
50
ms
Key Entry Width2
tW1(2
50
ms
Key Input Pause
Time
tpK
50
ms
COIT to-COlA
ROWlTOR0W4
Key Entry
Debouncing time
tCH
21
23
25
ms
Key Entry Release
Guard time
tRE
21
23
25
ms
BEEP TONE Output
Start time
tBES
BEEP TONE Output
Width
mJTE lOW Output
Start time
III
39
tWBE
ms
41
43
31
tl/US
mJTE
mJTE lOW Output
Hold time 1
31
DTMFIBEEPOUT
luUSPl
ms
10pps
26
30
34
20pps
13
15
17
Dual Tone Output
100
110
120
10pps mode
950
980
1016
20pps mode
480
510.5
556
10pps mode
950
974
1016
20 pps mode
480
507.5
556
MB87007A
Pulse Predigital
Pause Time
tpDP
10pps mode
38
39
40
20 pps mode
19
19.5
20
10ppsmode
32
33
34
20 pps mode
16
16.5
17
10 pps mode
60
61
62
20pps mode
30
30.5
31
MB87008A
POLSEOOI
tWBR
10 pps mode
66
67
68
20pps mode
33
33.5
34
MB87008A
10ppsmode
900
939
960
20ppsmode
450
469.5
480
MB87007A
Pulse Interdignal
Pause lime
tlop
ms
ms
MB87007A
Pulse Break
Width
ms
ms
MB87007A
tWIIA
ms
ms
MB87008A
Pulse Make
Width
ms
10 pps mode
900
933
960
20ppsmode
450
466.5
480
MB87008A
ms
ms
ms
( onMusd on next pag9
7-76
MB87007A
MB87008A
ELECTRICAL CHARACTERISTICS
Value
Parameter
mITE LOW Output
Hold time 2
Symbol
Pin Name
~USP2
mITE
Condition
Single Tone Output
Min
Typ
0
Max
Unit
8
ms
DUAL TONE Output
Time
tWOT
78
80
82
ms
DTMF Interpause
Time
tOTP
78
80
82
ms
Single Tone
Output start time
tslS
Single Tone
Output stop time
tSISP
DUAL TONE
Output start time
loTS
DUAL TONE
Output stop time
tOTSP
0
8
0
tpSMl
ms
ms
39
mITE Hold Time 1
by PAUSE key
entry
ms
31
DTMF/BEEPOUT
5
ms
0
10
20
ms
75
90
105
ms
0
5
10
ms
mITE
mITE Hold Time 2
by PAUSE key
entry
tpsM2
MODEOUT Blinking
Start time
tMosT
MODEOUT
7-77
MB87007A
MB87008A
DTMF OUTPUT SIGNALS
ltam
DTMF Output Signal·
(Hz)
Error to Standard TDMF
(%)
697
696.95
-0.01
770
770.13
+0.02
FR3
852
852.27
+0.03
FR4
941
940.99
-0.01
FC1
1209
1209.31
+0.03
FC2
1336
1335.65
-0.03
FC3
1477
1476.71
-0.02
Symbol
Standard DTMF
(Hz)
ROW1
FR1
ROW2
FR2
ROW3
ROW4
COL1
COl2
COl3
NOle:
"USClllation lrequency 3.Sf 1Mb MHZ
Figure 4. Key Input Timing
Key Input
D
---'WM
ICH~1~1-
It---.
NoI..: 1 Key Inpul Debouncing Time tC
Key entry is accepted if low level is longer 111811 23 ms typo
2Key Inpul Release Guard TlII1e IRE
Key release is recognized if low level is longer lhan 23 ms typo
7-78
MMII
I.
J
MB87007A
MB87008A
TIMING CHART 1-A
When there Is a ause before LDT ke In PULSE mode
"H"
HKS
OSCIN
OSCOUT
KEY INPUT
MODEIN
(OPEN)
MODEIN
(Voo)
"
L"
't-::;;:-:------------:-:----"H"
I --t"'~ ___________________ ~ tossp
"L"
"H~~
_ ~7J~ _____ --+--11"-------
_
... i-!tWK~
"L"_.!!Z~I
1
.... tPK
3
P
I
1:!9'"l.:J
I
I
tHIMI'"
--t t-- tWK2
"H"-1 -- - - - - - - - - - - -
H
"L"-.!:!.Z-fJ
IL-_____ ~~(10
pps)
- ---
~
-----f.I
"H""- --fI~Ifr_-----------;::=---.--------~----I II
(2
)
"L"---l--r
0 pps
,,~~~ 1--1
--tt--tM0C2
MODEOUT "L" HZ
l.L-jIi-_____________---I-I1i
""1.--:-._-__---'11
I
"H"
ftpmO[~scEO~O~1 "L"
DTMFI
"H"
BEEPOUT
°L"
tBES--I
[
I
°L"
""'1
"'1 ....
I tWA
II
.---------!-'II--+-----
ununuM'.~~~-~.iI
--I :. tWBR!!
...... tWBE
B D
W
II
"H"
I-I·--r-~
..II
tlOP
U
'I'lJI'
tpAS
1\
~ j... tMST
I rs'1!--+I----I
--t..-tPSMl
I
I
H
tMUSPJ,...------
~IMUS
TIMING CHART 1-B
When there Is a pause before LDT key In PULSE mode
HKS
OSCIN
OSCOUT
:~~~----------------------I r----------------,
~!!1~ _____
z
"H"
"L"
I
MODEIN
(OPEN)
MODEIN
(Voo)
r-
L _ _....
CiW.,;:;3:.;;::;.S..:..;79:=S-..:,;45:..:W:.::
H
.:::....L._
4lzKs
"H"
KEY INPUT "L"
_____
I
L~~
I 7 I
-----.---IIT"---...II--,--
----------
"H·1
r'?~
"L" I L~J 1 L - - - - - 1 kHz(10fPS-L-._~
II
"H~-~
L~.i II
"H"
I
I
"L" I
(20 pps)
MODEOUT "L"
I·
PO[sEOOl
"H"
DTMFI
0H"
BEEPOUT
"L"
11L.~1k;,;;,H;,;;;Z+j_-J
tpllP
.IUI'
tlOP
·1
ununu l....-..---aoI.
I
I
tPAS
I
I
I
I
I
I
I
I
I
I
I
I
--t "'tOTS ...... tDTSP
I
I
"L"·----R.B----------ill----+JIf'tl...- - -.. .rw;""1!---"H'l.."----.
I I
I -ai ~1
"L"
Continued on next page
7-79
MB87007A
MB87008A
TIMING CHART 2-A
When there Is no ause before or after LOT ke In PULSE mode
HKS
"H"
"L·IL...-_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OSCIN
OSCOUT
·H·
"L.'_ _
MODEIN
(OPEN)
·H·
MODE IN
(Voo)
·H·~--ri---------~-~-------------"L.
____ ...J
(20 pps)
--'-C
__-__=__ - 3,279545 MHz_
- ~ _ _ _ _ _ _ _ __
- ---- --- - --- - --,-----------
.L.-.!:!.~J
L . . I_ _ _
.....:..1;.;;.kH~(10pps)
I
....I I.
.L.-H'zl......._________-t.-t
II .
MODEOUT "H"
~0C2
I 1'---_ _ _ _ _ _ _ _ _ _ _ __
•H"
U
-.n:!"1:7"rrlT
POLSEOO i
.L.
DTMFI
BEEPOUT
"H·
·L",_ _ _ _
X-~L....~
D B B
U1J1J-
~~~M5~ST
______
L..-_ _ _ _ _ _ _ _ _ __
·H·!....----.
·L"
TIMING CHART 2-B
When there Is no ause before or after LOT ke In PULSE mode
HKS
OSCIN
OSCOUT
"H·
"L·~
·H·
·L·'_ _ _
~~H_z_ _ : _ _ _
,..-_ _ _ _ _ _ _ _ _ _ _-, 6/.Pause releas ...
e _ _ _ __
"H~-
KEY INPUT "L.
MODEIN
(OPEN)
"L·
MODEIN
(Voo)
"Hit
ilL"
MODEOUT
:::L
-'CL-_-____:
L~~
I p""1 key
I
L....__ _
!.kHz (10 ppsL
1___....._ _ _ _ _ __
L~J~~------------~
"H~
(20 pps)
..j FtMOPS
'H~-
"L·
L~.J
I
"H"
pO[SEOOI
"L·
DTMFI
BEEPOUT
"H"
mITE
"H·
"L·
·L·
I
I
U
U1J1JI II
... i--IMDST
B
I
I
I
I
I
I
I
I
Ft
rt1
:Q
PDT
I
I
I
I
Continued on next page
7-80
MB87007A
MB87008A
TIMING CHART 3-A
InDTMFmode
·H·
HKS
·L·---,. . .---------------------
OSCIN
OSCOUT
·W
"L·_ _ _rL..--=3.:.::!57~ MHLJ. ~~C-
--------,
~.579545
MHz
_
Single tone
I
MODEIN
(GND)
II
H---,I~I 1~tuOCl
" "
MODEOUT "L" HZ
I
I
I
I
I
I
I
I
II
~~----------~I--~I------------~
I
I
"H·
1"I1POrrT["l'1SE""'O"--'OUTSWS
I _
iV'V'1
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
L
OTMFOUT "L"
. H"----..,
"L"
NOTE: MA/BR '" "H" for make rate 39% and "L" for 33%,
Timing chart 2·8 (When there is no pause before or after LOT in PULSE model
Key entries in Timing chart 2·A are written as memory data.
r-1,'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
HKSW
.."H"
L .. ...J
XI
"H"
X2
,.-----
" L - - - - 1___________
----.=_-I_~-----------
3.579646 MHz
Key entry
MaDEe
(OPEN)
"H"i-~-n="L"
MOOEe
"H"
IVool
"L"
10 __ "
_
lkHz(10PP,~._I_ _ _ _
(20ppsl
tMOBLNKli
MOOED
jtMOSWPL
U
'" -----------------t-~-------'M,.IlL------------W:J ~~. J ,--'_"
"L."
OTMFOUT .. L ..
..H ..- - - - - ,
I
"t"
.
NOTE: MA/BR = "H" for make rate 39% and "L" for 33%.
7-106
-
:::::L-~~-f__,L -_ _ _ _ _ _ _ _ _ _ _ _~r----------------"H"
PoUT
+____-'1
MB87009
Timing chart 3-A (in DTMF mode)
HKSW
:::.... ' L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
XI
X2
"H" _ _ _ _
Keventrv
MQDEC
(GND)
H Z.1.
"L" ____
"H"--"L"
MOOEO
-----tL-,---------+---f-------------------
"H"----.,
HZ I
"L"---"H .. -
+-_______-+__+ _________________
__
"l"
DTMFOUT
"H"
+ ....
.. L .. _ _ _
..H"----I-,
"L"
BEEPOUT ::H,:'---H;---!l---n----------II-~------II---a---n---II-------------L _ _ _ _ _ _ A. __ A __________ .lt. ________ J:l __ Jl __ A __ A _____________ _
D
NOTE: MA/BR'" "H" for make rate 39% and "L" for 33%.
Timing chart 3-B (in DTMF mode)
Key entries in Timing chart 3-A are written as memory data.
HKSW
XI
X2
"H"
.. L .. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
:::::
I
3.5795~~~,____
3.579545 MHz
_ _ _ _ _ _-,--..- - - , L_ _ _ _ __
r-_____-iREO,r-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _- ,
Keyentry
':.:::~
MQDEC
IGND)
"H"
..
L ..
u
~~P-'"-"-"-"..-'-k'~V------
l!J
_-I_--:____________________-+__________
~.~~~ --r-~z~~'=l
MOOED
I.. _ _ _
HZ_ _ I
"l"
"H"_
"L"
'H"
----r-'""---Ir--------------------t----------I
I
-,pou~
M
-
r.::' '.________
UTPL
DTMFQUT .. L .. _ _ _ _ _ _ _ _ _ _--'~~---------'IU;'
"H"-U
tlNPS
"L"
BEEPQUT
:::::::~_=_.D:=-~_:.:===:.:I:=:=:==:==:=::::::::==_1!:_::::==:::====
NOTE: MA/BR = "H" for make rate 39% and "L" for 33%.
7-107
MB87009
PACKAGE DIMENSIONS (Suffix: PI
20·LEAD PLASTIC DUAL IN·LINE PACKAGE
(CASE No.: DIP·20P-MO.1)
-tF=;==:::::::::;::"115'
INDEX·l
"
/
n
(EJECTOR MJ>.RKI
I
.25016.351
.27016.851
MAX
.29017.371
.31017.871
~
INDEX·2
I
.953(24.21
.976124.81
05011.271MAX
.03410.861
.04611.161
.17214.36IMAX
D
.11813.0IMIN
.10012. 541 1
TYP
l~)1986 FUJITSU LIMITED D20005S-1C
7-108
Dimensions in
inches (millimeters)
MB87009
PACKAGE DIMENSIONS
(Suffix: PF)
24·LEAD PLASTIC FLAT PACKAGE
(CASE No.: FPT·24P·M02)
.00210.051
rD."
I .417(10.61
.287(7.31
INDEX
!<\T:::;:;::::;:;::::;:;;:::;:;=;:;:::;;=;;;=;;=n=:;:;=~~17.91
.005(0.131
.00810.201
Detail of "A" part
..05011.271
TYP
.00710.181
MAX
.02710.681
MAX
Dimensions in
inches (millimeters)
Q1985FUJlTSU LIMITED F24QOBS-1C
Circuit diagrams utilizing Fujitsu products are included as a
means of illustrating typical semiconductor applications; can·
sequently, complete information sufficient for construction pur·
poses is not necessarily given. The information has been carefully
checked and is believed to be entirely reliable. However, no
responsibility is assumed for inaccuracies. Furthermore, such in-
formation does not convey to the purchaser of the semiconductor
devices described herein any license under the patent rights of
Fujitsu Limited or others. Fujitsu Limited reserves the right to
change device specifications.
7-109
MB87009
D
7-110
OJ
April 1991
Edition 2.0
FUJITSU
DATA SHEET
M8870178
DTMF RECEIVER
DUAL TONE MULTI FREQUENCY RECEIVER
The MB87017B is a one chip DTMF receiver w~h an input ampiHier gain adjuster
and low power consumption, integrating filter and decoder circuns. The MB87017B
can select either automatic guard time setting mode or adjustable external guard
time setting mode.
This circu~ consists of SCFs (Switched CapaCitor Fiiters) and decoders which
convert 16 types of DTMF tone pairs into hexadecimal four-bit codes.
• All DTMF receiver functions are integrated on one chip.
• Low power consumption
• Built-in input amplifier gain adjustment circuit
• Selectable automatic or adjustable external guard time setting modes
PLASTIC PACKAGE
(DIP-18P-M02)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Supply Voltage
V""
+6.0
V
Analog Input Voitage
V.,N
-0.3 to Voo + 0.3
V
Digital Input Voitage
V","
-0.3 to Voo + 0.3
V
Operating Temperature
T.
Oto+70
°C
Storage Temperature
TSTG
-55 to +125
°C
PLASTIC PACKAGE
(FPT-24P-M02)
NOTE: Permanent device damage may occur Hthe above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
This device contains clrcuftry 10 project thai","", against
conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
avoid application of any voltage higher than maxlnNm
. - voItagooto this high l..,adanco clrcuft.
::::T1~~~~rt~r:c==~'l:~
Copyright" 1991 by FUJITSU LIMITED
7-111
MB87017B
PIN ASSIGNMENT
PIN ASSIGNMENT
(TOP VIEW)
A,.
PIN ASSIGNMENT
(TOP VIEW)
18
Voo
A,.
Voo
GAl
2
17
GT
Go,
GA2
3
16
OF
Go.
VREF
4
15
OS
VREF
GT
NC
OF
OS
AG
5
14
O.
TEST
6
13
03
OSCl
7
12
02
OSC2
8
11
0,
GNO
9
10
TOE
NC
AG
TEST
OSCl
NC
NC
OSC2
GNO
O.
03
NC
NC
10
11
12
(DIP-18P-M02)
DI
02
0,
TOE
(FPT-24P-M02)
BLOCK DIAGRAM
(DIP PACKAGE)
AnalogCircuit ---------------;------ Digital Circuit ------;
I
I
I
Dial Tone
Fiher
OSCl
7-112
OSC2
Voo
GNO
OF
GT
OS
TOE
M8870178
PIN DESCRIPTIONS
A,.
Analog input pin (non-inverted operational amplifier input)
2
2
GA,
3
3
G...
0
Operational amplifier gain adjustment pin 1 (inverted operand amplifier input).
Operational amplifier gain adjustment pin 2 (operand amplifier output pin).
These pins are provided for operational amplifier gain adjustment.
The polarity of GA' is opposite to that of GA2.
4
5
V_
0
Reference vottage output pin. (112 VDD)
5
6
AG
6
7
TEST
7
8
OSCl
8
11
OSC2
9
12
GND
Ground pin
10
13
TOE
Three-state output enable pin.
• Data from 0, to O. may be output when this pin is set to "High".
11 to 14
14,15
18,19
O,toO.
0
15
20
DS
0
•
Analog ground pin
Test pin. Usually set to ground level.
0
Clock input pin.
Clock output pin.
• Connect a 3.5795 MHz crystal between OSCl and OSC2 pins.
Three-state data output pin.
is received and de16
21
DF
0
17
23
GT
0
Guard time mode select pin.
When GT pin is clamped to Voo, automatic guard time setting circun is
selected; Guard Time Present (GTP) and Guard Time Absent (GTA) are
set to 20 milliseconds.
See functional descriptions on page 5.
When GT pin exceeds 112Voo, DS pin outputs high level.
When GT pin is less than 112Voo, DS pin outputs low level.
•
•
•
18
24
VDD
4,9
10,16
17,22
NC
Positive supply vokage pin.
The voltage must be +5 V ±5'Yo.
•
No connection
7-113
ID
MB87017B
FUNCTIONAL DESCRIPTIONS
FILTER
The fikers consist of 3 sixth-order SCFs. The dial tone removal fiHer (including the 60 Hz fiker) output is connected to the individual
hysteresis comparators through the low group and high group filters.
In the figure below, the solid line shows the characteristics of the low group filter while the broken line shows the characteristics of the
high group filter. At a frequency of 770 Hz, it is assumed that 0 dB are lost. Therefore, this point is used for reference .
o
I[
~
I
I
Gain (dB) -50
/
I'
, - .,j
"in
o
.L _1--1 __
I I I
.I'
\:
i
,
V, =-10dBm _
T.=25°C _
\
\
,....
'I
"
.,
1/
'\.J
2
Frequency (kHz)
DECODER
1. Digital Frequency-detecting Circuit
The OF (Detect Frequency) pin goes to "High" when the detector circuit acknowledges the output signals from the two comparators
as valid DTMF signal frequencies in the digital frequency detecting block.
2. Guard Time Setting Circuit
Automatic or adjustable external guard time setting modes are provided. Guard time has two types: GTP (Guard Time Present)
and GTA (Guard TIme Absent).
2.1
Au10matic Guard Time Setting Circu~
When GT pin is clamped to VDD, au10matic guard time setting circu~ is selected; tc.TP and tGTA are set to 20 milliseconds. The
output signal from the filters may be acknowledged as a DTMF signal if:
(D
A signal w~h valid DTMF frequency lasts more than 40 milliseconds. This signal is decoded into a DTMF signal.
These pulses correspond to the input signal enable period and disable period for akernative current
characteristics.
®
A period of more than 40 milliseconds exists between DTMF signals nand (n + 1). If this is not the case the DTMF
signal (n + 1) is disabled.
These pulses correspond to the inter-digit pauses for acceptance and rejection for alternative current
characteristics.
In (D, ~ takes the OS (Detect Signal) pin GTP to acknowledge that the input signal is a DTMF signal after OF switches to
"High". The OS pin switches to "High" when the input signal is acknowledged as a DTMF signal.
In ®, ~ takes the OS pin GTA to disable DTMF signal n after OF switches to "low". The OS pin switches to "loW-when
the signal is disabled. (See Page 10 for the timing chart.)
Iso. > IGTl' + tPDF
t'DA > IADF + tc.TA
7-114
MB87017B
2.2 Adjustable External Guard Time Setting Circutt
The simplified adjustable external guard time setting circuH shown below enables any guard time present (GTP) or guard time
absent (GTA) setting.
The guard time is adjusted by selecting external register R when the external capacoor is 0.1 IiF.
---------------------------------------------------,
I
O•1 /lF
R
112Voo
OF
Adjustable external guard time
Automatic guard time
---------------------------------------------------~
tGTP
~ tGTA=
(R.C) In (V""'-II2VDD)
2.3 Automatic Guard-time/Adjustable External Guard-time Setting Mode Selection Circuit
•
•
Adjustable external guard time setting mode
Adjustable external guard time setting mode (GT pin is set low) is selected on the rising edge of the detected
frequency (OF).
Automatic guard time setting mode
The automatic guard time setting mode (GT pin is set high) is selected the power-on reset signal and on the rising
edges of the OF.
2.4 Power-on Reset Circuit
The power-on reset circuH generates a reset signal to initialize the automatic guard time or adjustable guard time setting circuit
when power is applied.
The power-on reset circuit specnications and timing diagram are shown below.
Power supply rise time
Power supply fall time
0.1
Power-off time
100
50
ms
Power-on reset operation conditions
ms
7-115
MB87017B
FUNCTIONAL DESCRIPTIONS
•
Power-on reset timing diagram·
,..---------Voo
OV
NOTE: If the values of power supply rise time, fall time, and power off time shown in the table are not satisfied, the power-on
reset signal will not be generated and the automatic guard time setting circuit may not recover from malfunction (receive
disabled).
The adjustable external guard time setting circu~ will not enter malfunction even if the power-on reset signal is not
generated.
Therefore, npower supply conditions disable the power-on reset circu~, the adjustable external guard setting circuit can
be used.
III
7-116
MB87017B
OUTPUT CIRCUIT
When the signal detector pin (OS) swnches to "High", a received tone pair is stored in the output circun register. The output latch
status may be output on the output bus by setting the three state control input (TOE) to "High".
COLO
COL1
COL2
COL3
ROWO [J [J [J 0
ROW1888[J
ROW2 [] [J [J G
ROW3 DG8G
OTMF Dial Matrix
SAMPLE DIFFERENCE INPUT CONFIGURATION
The MB87017B uses a dHference input amplifier and provides for a bias power source (V-) to apply a bias voltage to the input
signal. This also allows a pin to connect a gain adjustment resistor to the amplifier output.
Input ( ) - - - ;
1--..J,J<'Ir----oI----{
RL2:50kQ
}----r-....
L
7-117
MB87017B
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Voo
4.75
5.25
V
Input Voltage
V,
0
Voo
V
Oscillation Frequency
lose
3.5759
3.5831
MHz
OSC1 Pin load Capac~ance
eu"
10.0
50.0
pF
OSC2 Pin load Capac~ance
Cr.oo
10.0
50.0
pF
GA2 Pin load Resistance
RLA
50
GA2 Pin load Capac~ance
c...
Operating temperature
T.
5.0
3.5795
kQ
100
pF
70
"C
0
DC CHARACTERISTICS
Veo = 5 V ±5%. T. = O"C to 70"C
Power Consumption
Po
low level Input Voltage
V,L
High level Input Voltage
V..
low level Input leak Current
I,L
High level Input leak Current
37
mW
0
0.8
V
2.0
Voo
V
V,=GND
-10
10
)JA
I'H
V, = Voo
-10
10
)JA
low level Output Voltage
VOl.
IOL-2mA
0
0.4
V
High level Output Voltage
VOH
IoH .-Q.4mA
2.4
VDD
V
VAEI' Output Voltage
VAEF
7-118
I = 3.58 MHz. Voo = 5 V
25
2.5
V
M8870178
AC CHARACTERISTICS
v"" _5 V ±50/0, T. =O°C to 70°C
T•• 25°C, V",,-5V
Signal Input Level
-29
TWIST
-10
-1
±10
dBm
dB
Allowable Frequency Deviation
±1.5±2 Hz
0/0
Prohibited Frequency Deviation
±3.5
0/0
Allowable Noise Level
Allowable Dial Tone Level
-12
dB
22
dB
Input Signal Detection Timing
5
11
14
ms
Input Signal Detection Timing
0.5
4
8.5
ms
40
ms
Input Signal Enable Period (Accept)
Input Signal Enable Period (Reject)
20
ms
Inter-digit Pause (Accept)
40
Inter-digit Pause (Reject)
9
Input Clock Frequency
fiN
Clock Rise Time
ms
3.5831
MHz
tr
110
ns
Clock Fall Time
If
110
ns
Clock Duty
DR
*1
dBm: 600 ohm reference
*2
TWIST = High group tone voHagelLow group tone voHage
3.5759
ms
3.5795
50
0/0
*3
Allowable noise = Total allowable noise within the range 300 Hz to 3.4 kHzlMinimum amplitude tone level in valid tone pairs
*4
Allowable dial tone level = Total allowable normal dial tone volumelMinimum amplitude tone in valid tone pairs
*5
See Timing Chart.
*6
Specified values are referenced to the automatic guard time setting mode.
See page 5 for IGrp, and tOT' in the adjustable external guard time setting mode.
7-119
MB87017B
TIMING CHART
#N
Input
#N+l
bp.
IsoR
~PR
IsDA
IAoF
OF
Iorp
(j)OS
Iorp
lor.
®OS
(j)GT
®GT
III
TOE
I
(j)O,tOo.3
(
#N
®O,toO·3
(
#N
NOTE: (j)
®
7-120
X
X
#N + 1
#N + 1
Automatic guard time setting mode (GT pin is clamped to Voo)
Adjustable external guard time setting mode (See circuit on page 5)
M8870178
PACKAGE DIMENSIONS
l8-LEAD PLASTIC DUAL IN-LINE PACKAGE
(case No.: DIP-18P-M02)
-----==~t
15° MAX
INDEX-l
INDEX-2
Ai:=;:::::;::::;=:;=:;=:;=;==;=;:=;:::;=:::;=:;=;==;=;:=?!
(0.25±0.05)
MAX
Dimensions in
TYP
inches (millimeters)
24-LEAD PLASTIC DUAL IN-LINE PACKAGE
(case No.: FPT-24P-M02)
.110(2.80) MAX
(MOUNTING HEIGHT)
r- O;t;il;-of .;-:-: pa;t--l
"A"
I
.008(0.20)
:
I
I
I
I
.024(0.60)
Dimensions in
inches (mil1imeters)
.007(0.18)
MAX
.027(0.68)
L _______~A!_____
I
I
I
I
I
I
l
7-121
MB87017B
7-122
00
FUJITSU
January 1990
DATA SHEET
MB87029
DTMF Pulse Dialer
The Fujitsu MB87029 is a Dual Tone MultHrequency (DTMF) pulse dialer that
is designed for pushbutton telephone sets and uses the Si-Gate CMOS
process.
The MB87029 is used in both DTMF and PULSE modes and can be switched
from PULSE mode to DTMF mode by a mode selection entry orby inputfrom
the keyboard. The MB87029 contains a 26-dig~ redial memory that perm~s ~
the coexistence of PULSE and DTMF modes, enabling mixed redialing in
both PULSE and DTMF modes by a signal key entry.
• Pulse 10 pps, 20 pps, or
DTMF operation can be
selected by the mode sw~ch
pin (MODEIN)
• On-chip 26 digits of redial
memory (up to 25 digits can
actually be written in the
memory)
• Selectable make ratio by
MAlBR: 39% or 33%
• Line Dial Tone (LOn function
is provided (sw~ching from
PULSE mode to DTMF mode
by key entry)
• Output of a beep tone for input
confirmation (for all effective
key entry independently
PULSElDTMF modes)
• Redial inhibit function is
included for redial memory
overflow
• PAUSE function is provided
and pause accumulation is
possible
• Single-tone output is enabled
bySCNTpin
PLASTIC PACKAGE
DIP-22P-M03
• FLASH function is provided
(ON HOOK mode is selected
by keyboard input)
• FLASH output time, 0.1
second or 0.6 second, is
selected by FCNT pin
• Crystal or ceramic oscillator
(3.579545 MHz) can be used
PLASTIC PACKAGE
FPT-24P-M02
• Pause release function is
provided (two or more
consecutive pauses can be
released)
(TA = -30 to 60°C)
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Pin Name
roIT
ROW1
CO[2
ROW2
CO[3
ROW3
CO[4
ROW4
MAlBR
Value
Unit
MODEIN
MODEOUT
Positive Supply Voltage
VDD
Input Voltage
VI
Voo
GND - 0.3 to 7.0
V
All inputs
GND - 0.3 to Voo + 0.3
V
OSCIN
OSCOUT
GND
Ouput Voltage
VO
Storage Temperature
TSTG
NOIe:
©
All outputs
DTMFOUT
VDD
• Operating voltages:
PULSE mode: 2.0 V to 6.0 V
DTMF mode: 2.5 V to 6.0 V
• Mixed redialing of both PULSE
and DTMF modes
ID
PIN ASSIGNMENT
GND - 0.3 to VDD + 0.3
V
..')5 to +150
°C
Permanent device damage may occur if absolute maximum ratings are
exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may allectdevice reliability.
TOP VIEW
SCNT
FCNT
POLSEOOT
HKS
BEEPOUT
~
This device contains clrculby to prated the inputs against damage
due to high stalk: voltages or electric fields. However, II is advised
that normal precautions be taken to avOId application of any voltage
higher than maximum rated voltages to this high irJl)8dance circuli.
1991 by FUJITSU LIMITED and Ful~'u Mk:roelectronic:s,Im:.
7-123
MB87029
Figure 1. MB87029 Block Diagram
DTMF Generator
OSCIN~
OSCOUTC
0
Lr------------~
r ~~ ·
'
I
Row Prog....--
""'''''', I-- rH. Co,,,,,
,
~ Column prog·
r
Wave
Adder
I--
I
I
Gen.
,L ________________
Counter
'--,~ DTMFOUT
~
MAlBR
MODEIN
External
Keyboard
II
2 3 RED
4
5
6
P
7 8 9 LOT
.o
#
F
MODEOUT
Control
Logic
Circuit
-
IROWf
1
~
r-
,, ROW2J
,'ROm ....
r-l- f-
t-r-I~
T
' ROW4
,,I
IC0C4
BEEPOUT
I
Keyboard
Logic
Pulse
Output
Circuit
Memory
Circu~
Circu~
,iI~
401)
SCNT
-C)
FCNT
4f~
I rnr:2
I
, rorr
,
I
!
HKS
7-124
4f'
'"
Voo
BeepTone ~
Generator
!
'"
GND
pOLSEOOI
MB87029
PIN DESCRIPTIONS
Pin No.
110
DIP
FPT
1
1
Symbol
Vo
0
Power
SUpply
11
12
2
3
Description
Power supply voltages: Pulse mode 2.0 V to 6.0 V
DTMF mode 2.5 V to 6.0 V
Memory Retention mode 2.0 V min.
GND
Ground
2
3
'CO[f
'CUm
COJ:4
ROWf
'ROW2
Uses key entries from 2 of 7 or 2 of 8 keyboards with common GND. This IC is
available with a single contact from A type keyboard and electronic input (Low
entry).
Key input debouncing time is 23 ms typo for both PULSE and DTMF modes.
Key input release guard time is 23 ms typo for both PULSE and DTMF modes.
Key entry is accepted in PULSElDTMF modes only when a single key (one key
on the keyboard) is pressed longer than the debouncing time. Iftwo or more keys
are pressed, they are not accepted unless they are released one-by-one and the
last key is held closed longer than the debouncing time, after all other keys are
released.
Key entry is accepted in DTMF mode only when either a single key (dual·tone
key) is pressed or two or more keys in the same 'CO['or ROW (single-tone keys)
are pressed longer than the debouncing time. Hone key in CODi is pressed, the
single·tone keys are ineffective. If multiple single-tone keys are pressed, and the
last key is held closed longer than the debouncing time, after all other keys are
released, the key is effective as the dual-tone key.
Hereafter, key entries are described with the premise that keys are held closed
longer than the debouncing time.
Pauses between key entries in PULSE and DTMF modes must be 50 ms or
more. However, up to 50 ms is necessary from key entry to output start for
single·tone outputs.
4
5
5
6
21
20
23
22
'C'O[2
19
21
18
20
Rom
'ROW4
6
7
MAlBR
Input
Key switch contact resistance up to 5k.Q is allowable.
This pin selects the make rate.
MAlBR
Make Rate ("!o)
Voo
39
Break Rate ("!o)
61
GND
33
67
Make ratio switching by MAlBR is inhibited during PULSEIDTMF transmission.
The input level is in the CMOS level.
6
7
MODE IN
This pin selects the pulse mode, 10 pps, 20 pps, or the DTMF mode.
MODEIN
Mode
Pulse Mode 20 pps
Open (1 Mil or more)
Pulse Mode10 pps
DTMFMode
Voo
GND
Mode switching is not accepted by MODEIN. After data transmission is
completed, mode switching is honored by key entry.
In the ON HOOK mode, this pin is set to a high impedance state.
continued on next page
7-125
MB87029
PIN DESCRIPTIONS
Pin No.
11O
DIP
FPT
Symbol
Description
Hook lIwitch input pin.
14
15
HKS
ON HOOK Mode
OpenorVoo
OFFHOOK Mode
GND
Output is inhibited inONHOOK mode, and PULSEOUT, DTMFOUT, BEEPOUT,
gQTE, and MODEOUT are set at a high impedance state.
All key entries are set to HZ and the on-chip operational amplifier and oscillator
(OSCIN. L, OSCOUT. L) become power down states.
This pin is pulled up by a high resistance internally.
The input level is in the CMOS level.
Input
9
10
OSCIN
Oscillator input pin.
In the ONHOOK mode this pin is pulled to a low level by a high resistance.
16
17
FNCT
This pin selects FLASH time period.
FNCT
Voo
GND
FLASH output time
0.6 second
0.2 second
Swttching is prohibtted during PULSElDTMF transmission.
Input level is in the CMOS level.
01
17
18
SCNT
This input enables a single-tone output.
SCNT
Voo
Single tone output
Output
GND
Not output
Switching is prohibtted during a PULSEIDTMF transmission.
Input level is in the CMOS level.
OUtput
7-126
10
11
OSCOUT
8
9
MODEOUT
Oscillator output pin.
In the ON HOOK mode, this pin is pulled to a low level by a high resistance.
The output is in the CMOS level and set to a high impedance state in the
ONHOOK mode.
Low level is output in the PULSE mode and high level is output in the DTMF
mode, including the LDT function.
MODEOUT blinks on and off at a frequency of 2.5 Hz typ., if there is no pause
before and after mode swttching in redial function.
When the FLASH key is pressed in etther PULSE or DTMF mode, High
impedance is output for a 0.6 second (typical) following the BEEP tone output.
The key acceptance state (OFFHOOK mode) is now entered.
contlnU6d on next page
MB87029
PIN DESCRIPTIONS
Pin No.
110
DIP
FPT
Symbol
Description
Output
12
13
mITE
N-channel open drain output.
In both PULSE and DTMF modes, the mITE pin is in a high impedance state for
the following c:ondkions:
1. There is no key entry.
2. After the beep tone is output and the FLASH key is pressed, HZ is output for
0.6 second (typical).
3. During pause output state. (However, when key is pressed, mTEis low level
while beep tone is being output.)
4. During MODEOUT blinking.
After key entries become effective in the PULSE or DTMF modes, the mTE pin
is ~r:i.during output of the beep tone, pulse output (according to numeric key
ent ,and output of DTME
13
14
BEEPOUT
The output is in CMOS level and the pin is set to a high impedance state unless
beep tone is output.
In PULSE/DTMF modes, Ihe beep lone is output according to effective key
entries.
Beep tone is output in 41 ms typo at 1 kHz in rectangular pulse.
13
14
pO[SeOOI
N-channel open drain output.
This pin is in a high impedance state in the ONHOOK mode or DTMF mode.
In PULSE mode, this pin is at Iowfor brakes (according to numerical key entries).
When the FLASH key is pressed in the PULSE or DTMF mode, a low level is
output for 600 ms typo after the beep tone is sent (even during a PULSEIDTMF
send). The key aoceptance state (OFFHOOK mode) then returns.
22
24
DTMFOUT
This DTMFOUT output pin is a bipolar follower that can drive a 100 load
between pin and GND.
When a single key (numerical,C) or0 ) is pressed in the DTMF modes, dual
tone is output.
Pressing two or more keys in the same ROW orOO[onthe keyboard outputs the
signal tone in the ROW or 00[.
If a key in COlA is pressed, then the DUAL TONE or single tone in the ROW or
00[ is not output. (Please see Electrical Characteristics.)
If the FLASH key is pressed during DTMF sending. the beep tone is output at
BEEPOUT and subsequent DTMF tones are not output. The ONHOOK mode is
entered for 600 ms typo after the key aoceptance state (OFFHOOK mode) is
entered.
DUAL TONE output time c:ondkions are as follows:
1. 80 ms typo for redial output
2. 80 ms typo when the key entry time is within 130 ms typo and more than the
debouncing time
3. DUAL TONE output is stopped at once Ha key is pressed longer than 130 ms
typo and released.
4. Signaltone is output from the end of debouncing time until the key is released.
This pin is set to a high impedance state unless DTMF tone is output.
n
7-127
MB87029
FUNCTIONAL DESCRIPTIONS
Ordinal Dialing
In OFFHOOK mode, PULSEIDTMF signals areoulput according tothe key input, regardless of the number of key inpulfigures. Forthe
PULSE mode, any numberof digital entries withkeysOto 9. Forthe DTMF mode, any number of digital entries with keys Oto 9,
eJ and
0·
Upto 26 digits can be stored inthe redial memory. In the PULSE mode, a redial digit is counted for any numeric, pause, and LDT entry.
In the DTMF mode, a redial digit is counted for any numeric,
eJ, 0, and 0
entry.
In both the PULSE and DTMF modes, one digit is counted as mode information when MODEIN is used for mode switching. After
OFFHOOK, the first numeric entry is counted as a mode digit. In the PULSE mode the numeric key is counted as a mode digit. In the
eJ,
DTMF mode, a numeric key,
and 0 entry Is counted as a mode digit. In either OFFHOOK or PULSE modes, the
mode-information digit Is written into the redial memory.
Redialing Function
The redial memory is read out to execute the redialing operation when a redial key is the first key pressed in OFFHOOK state. In the
PULSE mode, the redial keys are 0
and
eJ. In the DTMF mode, only the (]§[) key is accepted for redial.
When 27 or more digits are written into the redial memory, PULSE or DTMF signals that correspond to the key entries are output, but
the redialing operation is ineffective because of memory overflow. AI this time, even nthe first key pressed after the state change from
ON HOOK to OFFHOOK is the redial key, the entry is not accepted and the beep tone is not output in either mode of operation.
III
eJ,
AfterOFFHOOK, na numeric or LDTkey is the first entry in PULSE mode, orthefirst entry in the DTMF mode isa numeric,
0 or
a single-tone key entry (excluding 'COIA), the redial memory is cleared and data is written into memory aocording to key entry
information.
Mixed Rediating
Mixed redialing is executed when the mode is changed from the PULSE to DTMF mode (done by pressing the LOT key), or when
MODE is changed during key entries.
H, at redialing, there is a pause before or after mode switching (including LDT), PULSEIDTMF is sent and PULSEIDTMF signals are
transm itted after the pause. To redial when there is no pause before or after mode switching (including LDT), all operations must cease
after mode switching and a HALT state is enabled. MODEOUT blinks (indicates that mode switching has no automatic pause) and
prompts a pause release.
The pause release keys in PULSE mode are
eJ, (]§[), and the 0
key. In the DTMF mode, the (]§[) and the
0
keys are used
for pause release. PULSE and DTMF signals can now be sent by key entry. The FLASH key is the only other acceptable entry.
0
During redial output, the
key is the only key entry accepted. The pause release key is only accepted when MODEOUT is blinking or
during a pause at rediallng.
Mode Switching
During PULSE or TONE transmissions, mode switching by MODEIN is not permitted; after transmission is complete, MODEIN can be
used for mode switching.
When PULSE or DTMF modes are switched by MODEIN, one digit is stored into redial memory as mode information. After
OFFHOOK, if the first key entry is numeric in the PULSE mode, ora numeric
is written into redial memory.
7-128
eJ or0 in the DTMF mode, the mode-information digit
MB87029
In the PULSE mode, after the LOT key is accepted only one time, the OTMF mode is selected (regardless of MOOEIN pin swnching).
The LOT key is not accepted in the OTMF mode. The MOOEIN pin switching enables the desired mode of operation to be selected.
Line Dial Tone (LOT) Function
Hthe LOT key is pressed in the PULSE mode, the OTMF mode is selected and OTMF tones can be output. In PULSE mode, only the
first LOT key is accepted after key acceptance state (OFFHOOK mode) is entered. Once LOT key is accepted, the following LOT key
entries are ignored.
When the LOT key is used to enter the OTMF mode, all keys (excluding t:Or4keys) provide dual-tone and single-tone outputs. (Note:
Heven one 00[4 key is pressed, neither dual nor single tones are output.) The mode after that is not switched. If mode switching by
LOT from memory is done during redialing, key entries after redialing are executed in OTMF mode regardless of the MODE IN state
and the data is written into the redial memory. However, for effective keys (nolthe redial key) after ON HOOK changes to OFFHOOK,
memory is reset and written in the current mode.
Pause Function
A pause state can be entered by pause key entry.
In the PULSE mode, a pause is introduced by pressing the
0
or
® keys; in the OTMF mode (including LOT) only the ® key is
effective. If a pause key is the first key pressed after changing from ONHOOK to OFFHOOK, the entry is not accepted.
One pause key entry introduces a pause state that is typically 4 seconds; contiguous pause (N X 4 seconds) can be executed by
making consecutive key entries. The pause can be reduced by entering
® or (]ill during a redialing pause time.
c:J
In the PULSE mode, the
key is used as a pause release key. Mukiple pauses can be sent upto 500 times faster by entering a pause
release key, that is, N X 4 seconds becomes N X 800 milliseconds.
Flash Function
® key is used as a FLASH key in both PULSE and OTMF modes (including LOT).
® key is pressed, the ONHOOK mode is entered for 600 milliseconds (typical) after beep tone is sent. During this time, the
Keyboard entries enable ON HOOK mode. Only the
When the
key entry pin is not accepted. MODE IN, lVIDTE, MOOEOUT, and OTMF/BEEPOUT pins are placed in the high-impedance state and
the PULSEOUT pin is set low level. After 600 milliseconds (typical), the return of OFFHOOK is automatic and key entries can again be
accepted.
Test (High-speed Mode)
A test mode circuit is buik into the IC. In the ON HOOK state, pins OSCIN and OSCOUT are pulled down by a high resistance. To
activate the test mode, tie the OSCIN high and apply clock signal to OSCOUT. The internal circuit operates upto 128 times faster than
normal operation.
7-129
MB87029
Figure 2. Keyboard Configuration
2 of 8 Keyboards
Single Contact Type Keyboard
An example of a single contact type keyboard:
ROWf
Electronic Input
VIH
VIL
--,
r- ROW
L-.J
(Effective with "L" entry)
Figure 3. Reference Circuit
Voo
o
100'1
Keyboard
Single Tone
MB87029
20pps
__-r________~
10~o~~
(N.C.)
DTMF
Flast Output
0.65,0-----,
CSA3.58MGU
C1, C2 = 30 pFt-----'
20kQ
OFFHOOK
20kQ
GND
7-130
MB87029
KEY OPERATION DIAGRAM
0
Redial key for PULSE mode
I RED
Redial key for DTMF mode
(RED (D») =
Pause key for PULSE mode
rr:ID = ®or0
ITID =®
~ = eN[). ® .ore)
(EJQD = [RED) or®
Pause key for DTMF mode
Pause release key of PULSE mode
Pause release key of DTMF mode
®
Pause output
= eN[)
eN[)
(P»)
or
-Pause
KEY ENTRIES IN PULSE MODE
When MODEIN Is set to 10 "DS
PULSE output
HOOK
MODEIN
Key Entry
10pps
20pps
DTMFOutput
ON
OFF
ON
OPEN
(Dill
1-2
OFF
OPEN
[ RED (P>I
1-2
0
3
ON
OFF
OPEN
[ RED (P»)
1-2-3
Voo
( RED (P»)
1-2-3
GND
( RED (D»)
1-2-3
ON
OFF
ON
OFF
ill
4
conllnuect on next page
7-131
MB87029
KEY ENTRIES IN PULSE MODE
Wh en MOEII
0 N Ssetto20~PS
PULSE OUtput
HOOK
MODEIN
Key Entry
10ppa
20pps
DTMFOutput
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
Voo
CD ill
1-2
Voo
( RED (P!I
1-2
3
0
Voo
[ RED (PI J
1-2-3
OPEN
( RED (PI)
1-2-3
GND
( RED (01)
1-2-3
ill
III
4
KEY ENTRIES IN DTMF MODE
PULSE Output
HOOK
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
MODEIN
Key Entry
10ppa
20pps
DTMFOutput
GND
CD ill
1-2
GND
( RED (01)
1-2
0
3
GND
( RED
(o!l
1-2-3
OPEN
( RED (plI
1-2-3
GND
( RED (P!I
ill
1-2-3
4
conllflued on next page
7-132
MB87029
KEY ENTRIES WHEN THE LOT KEY IS USED
When there Is a Dause before LOT
PULSE OUtput
HOOK
MODEIN
ON
OFF
ON
OPEN
OFF
GND
ON
OFF
ON
OFF
Key Entry
10pp.
20pps
DTMFOUtput
CD0 c:E'liJ
am0
1-2-0
3
( RED (P))
1-2-0
3
0
4
Voo
( RED (P)
I
1-2-0
3-4
GND
(RED (D))
1-2-0
3-4
KEY ENTRIES WHEN THE LOT KEY IS USED
When there Is a Dause after LOT
PULSE Output
HOOK
MODEIN
ON
OFF
ON
OPEN
CD0@D
CIJID0
OFF
GND
( RED (p))
ON
OFF
ON
OFF
Key Entry
10pp.
20pps
DTMFOUtput
1-2
0-3
1-2
0-3
0
4
Voo
( RED (P))
1-2
0--3-4
GND
(RED
!Oll
1-2
0--3-4
COntllJU9fJ
on next page
7-133
MB87029
KEY ENTRIES WHEN THE LOT KEY IS USED
When t here s no pause be ore and after L DT
PULSE OUtput
HOOK
Kay Entry
MODEIN
10pps
20pps
DTMFOUtput
ON
OFF
OPEN
CD0
1-2
@D®
3
ON
OFF
OPEN
( RED (P»)
~
ON
OFF
1-2-MODEOUT
blinks
3
0
Voo
4
( RED (P>l
@ID
1-2-MODEOUT
blinks
3-4
ON
OFF
GND
( RED (D»)
~
IJII
1-2-MODEOUT
blinks
3-4
KEY ENTRIES WHEN PULSE/DTMF MODE IS SWITCHED (MIXED REDIAL)
When there Is a pause before mode swltchlna
PULSE Output
HOOK
Kay Entry
MODEIN
10pps
20pps
DTMFOutput
ON
OFF
OPEN
®0c:E:ID
GND
0eJCEJQiJ
OPEN
00
OPEN
( RED (P»)
ON
OFF
CD0CI:][)
Voo
1-2-0
3-4-0
5-*-0
6-7
1-2-0
6-7
3-4-0
5-*-0
3-4-0
5-*-0
3-4-0
5-*-0
ON
OFF
Voo
[ RED (p))
1-2-0
6-7
ON
OFF
GND
( RED (D»)
1-2-0
6-7
contlnooa on next pa
7-134
MB87029
KEY ENTRIES WHEN PULSE/DTMF MODE IS SWITCHED (MIXED REDIAL)
When there Is a pause after mode switching
PULSE OUtput
HOOK
ON
MODEIN
OFF
OPEN
KevEntrv
mm
Voo
([E00
GND
(LE0(:J
OPEN
Cf:ID00
OFF
OPEN
( RED (P»)
ON
OFF
Voo
( RED (P»)
10PP8
20PP8
DTMFOutput
1-2
0-3-4
0-6-7
0-&-"
ON
ON
OFF
1-2
0-6-7
1-2
0-6-7
GND
( RED (D»)
1-2
0-6-7
ON
OFF
ON
OFF
OPEN
mm
Voo
00
GND
0(:J
OPEN
00
OPEN
( RED (P»)
CE[]ill
§JIDJ
CE[]ill
0-3-4
0-&-"
0-3-4
0-&-"
0-3-4
0-&-"
1-2
3-4
S-'
6-7
1-2-MODEOUT
blinks
3-4-MODEOUT
blinks
6-7
S-'-MODEOUT
blinks
ON
OFF
Voo
( RED (P»)
§Jill
CffiJ§D
CE[]ill
ON
OFF
GND
( RED (D»)
CE[]ill
1-2-MODEOUT
blinks
6-7
1-2-MODEOUT
blinks
(PR (D»)
CE[]ill
3-4-M0DEOUT
blinks
6-7
3-4-MODEOUT
blinks
S-'-MODEOUT
blinks
S-"-MODEOUT
blinks
7·135
MB87029
REDIAL MEMORY INHIBIT FUNCTION
PULSE Output
HOOK
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
7-136
MODEIN
OPEN
OPEN
OPEN
Key Entry
mm·. mm
--------mm . . mm
--------m
~
(RED !P!)
1-1······1-1
(RED !P!)
DTMFOUtput
"--y--J
25
1-1······1-1
"--y--J
26
No output
2
OPEN
(RED (P) I
2
Voo
(RED (P»)
2
GND
(RED (D»)
2
ill
OPEN
20pps
1-1······1-1
25
26
OPEN
10pps
3
@Dmm . ·
mm
1-1 ......1-1
"--y--J
25
~
25
OPEN
OPEN
(RED (P»)
1-1 ......1-1
mmQillmm . ·
mm
~
1 -1
1-1 ......1-1
"--y--J
23
'--y-J
23
OPEN
(RED !P!)
No output
No output
MB87029
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Power Supply Voltage
Symbol
Voo
Input Voltage
VI
output Load
Resistance
Ro
Operating Temperature
TA
Pin Name
VDD
Condition
PULSE mode and memory
retention mode
DTMFmode
All
Inputs
DTMFOUT
Between output pin and GND
Max
Unit
2.0
6.0
V
2.5
6.0
V
0
Voo
V
0.1
20
k.Q
-30
60
·C
Min
Typ
7-137
MB87029
ELECTRICAL CHARACTERISTICS
Voo: PULSE mOde = 2.0 to 6.0 V, Voo: DTMF mOde = 2.5 to 6.0 V, TA = -30 to 60"C
Value
Parameter
Power Supply
Current
Symbol
Condition
Pin Name
5.0
mA
lop
All output pins are
open in PULSE mode
1.0
2.0
mA
All output pins. HKS
pin open in Standby
1.5
10
~
All output pins
open in DTMF
1.0
2.0
mA
All output pins
open in PULSE
0.3
0.6
mA
All output pins
HKSopen in
Standby
0.2
1.0
~
loST
Voo
V'Hl
V'Ll
VIH2
V'l2
Digital Input
Current 1
Voo=
2.5V
TAe
25°C
Digital Input
Current 2
Digital Input
Leakage Current 2
Digital Input
Current 3
0.8Voo
mt:l to "COrA
ROWf to FIOWil
0
0.8 Voo
HKS. FCNT
MODEIN. SCNT
MAlBR
0
V
1 Voo
5
V
Voo
V
1V
5 oo
V
-{).01
lVoo
.5
mA
V,-GND
-{).01 Voo
0.01
mA
Key entry HZ
GNDSV,SVoo
-10
10
~
mt:l to "COrA
ROWf TO FIOWil
IlZl
Voo
VIa Voo
11H1
"L1
Digital Input
Leakage Current 1
Unit
2.5
TDSTl
Digital Input
Voltage 2
Max
All output pins are
open in DTMF mode
IOPl
II
1YP
100
1001
Digital Input
Voftagel
Min
1
V,-Voo
-{).01
75 Voo
mA
V,-GND
-1175
Voo
0.01
mA
MODEIN HZ
GNDSV,SVoo
-10
10
~
"L3
MAIBR. SCNT,
FCNT
V,=GND
-10
10
~
I,HS
HKS. MAIBR.
SCNT, FCNT
V,-Voo
-10
10
~
"H2
112
MODE IN
"22
conttnuea on next page
7-138
MB87029
ELECTRICAL CHARACTERISTICS
Value
Parameter
Pull-up
Resistor
Digital Output
Vokage
Digital Output
011 Leakage
Current
Symbol
Pin Name
RPLU
HKS
VOH
MODEOUT
BEEPOUT
VOl.
MODEOUT,
pOLSEOOI.
mITE. BEEPOUT
IoH=~·2mA
IOL= 0.5mA
Min
Typ
Max
Unit
100
200
400
k.G
Voo -O.5
Voo
V
0
0.5
V
-10
10
JlA
mrrE;""
IOL
External Resistance
when dignal input is
open
ROlo
Pull-down
Resistance
RpLD
Oscillator
Frequency
OSCIN
PO[SEOOI.
MODEOUT,
BEEPOUT
ROWTTOR0W4
rorrtor0"L4
HKS. MODEIN
GND S Vo:S Voo
Resistance connected to
external circun when input is open. The other
end of the resistance
must be between 0 V
and Voo.
ONHOOKmode
AoUT
75
NRKEY
rorrtor0"L4
ROWTTOR0W4
Make Ratio
WMAKE
pO[SEOOI
loss
Oscillation
Stop time
Iossp
150
300
3.579545
k.G
MHz
No signal is output
0
V
OIIset voltage when
signals are output
0.6 Voo
-0.75
V
DTMF TONE output voltage
1.44
Vp-p
ROW single tone
output voltage
0.64
Vp-p
COLUMN single tone
output voltage
0.80
Vp-p
COLUMNIROW tone ratio
2.0
dB
DTMFOUT
Redial Memory
Digit
Oscillation
Start time
MO
1
OSCIN.
OSCOUT
DTMFOutput
Vokage
1000 placed
between output
pinandGND.
Condition
OSCIN.
OSCOUT
26
digits
MAlBR= Voo
39
%
MAlBR = GND
33
0/0
0
8
16
ms
0
8
16
ms
continued on next page
7-139
MB87029
ELECTRICAL CHARACTERISTICS
Value
Parameter
Key Entry HZ
Hold time
MODEIN HZ
Hold time
MOD EOUTHZ
Hold time
III
Symbol
Pin Name
Condition
UOITto~
Max
Unit
0
5
ms
Min
1YP
tHZKH
ROWfTOR0W4
tHZMIH
MODEIN
0
S
ms
MODEOUT
0
5
ms
0
5
ms
tHZMOH
UOITto~
Key Entry HZ
Start time
tHZKS
MODEIN HZ
Start time
ItizMIS
MODE IN
0
5
ms
MODEOUTHZ
Start time
tHZMOS
MODEOUT
0
5
ms
Pause lime
tpAS
pOLSEOOl,
DTMFOUT
3.85
4.15
s
MODEOUT Switch
Start time 1
iyOC1
MODEOUT Switch
Start time 2
MODEOUTHZ
Start lime by F
key entry
MODEOUTHZ
Hold lime by F
key entry
MODEOUT Blinking
Period
MODEOUT Change
Start time by
pause release
key entry
DTMFOUT Output
Start time when
mode is switched
DTMFOutput
Start time by
pause release
key entry
pOLSEOO I Output
Hold time
by F key entry
ROWfTOR0W4
4.0
ms
12
2
tMOC2
5
8
ms
72
tMOFS
MODEOUT
tMOFH
FCNT = Voo
0.59
0.6
0.61
FCNT=GND
0.09
0.1
0.11
0.39
0.4
0.41
iyOSI
2
tMST
10
s
s
ms
28
tMOPS
ms
15
ms
DTMFOUT
!PDT
ms
39
tPUFH
FCNT - Voo
0.59
0.6
0.61
FCNT-GND
0.09
0.1
0.11
s
PULSEOUT
pOLSEOOI
OUTPUT
Start time by
Fkeyentry
tPUFS
72
ms
continued on next page
7-140
MB87029
ELECTRICAL CHARACTERISTICS
Value
Parameter
Symbol
Pin Name
Condition
Min
Typ
Max
Unit
Key Entry Widthl
tWK'
50
ms
Key Entry Width2
tWK2
50
ms
Key Input Pause
Time
tpK
50
ms
Key Entry
Debouncing time
tCH
21
23
25
ms
Key Entry Release
Guard time
tRE
21
23
25
ms
BEEP TONE Output
Start time
tBEs
31
tWBE
MOTE lOW Output
Start time
tMUS
39
26
30
34
13
15
17
Dual Tone Output
100
110
120
10 pps mode
950
980
1016
20ppsmode
480
510.5
556
10pps mode
950
974
1016
20pps mode
480
507.5
556
tMuSP'
Voo
tpDP
POLSEOOT
10 pps mode
38
39
40
20ppsmode
19
19.5
20
MAlBR=
GND
10pps mode
32
33
34
20pps mode
16
16.5
17
10 pps mode
60
61
62
Vee
20 pps mode
30
30.5
31
MAlBR=
GND
10pps mode
66
67
68
20 pps mode
33
33.5
34
10 pps mode
900
939
960
Voo
20 pps mode
450
469.5
480
MAlBR=
GND
10pps mode
900
933
960
20pps mode
450
466.5
480
MAlBR=
ms
ms
ms
ms
tWBR
MAlBR=
Pulse Interdigital
Pause Time
ms
ms
Voo
tWMA
ms
ms
10 pps
MAlBR=
Pulse Break
Width
43
20pps
MUTE
MAlBR=
GND
Pulse Make
Width
41
31
MAlBRPulse Predigital
Pause Time
ms
DTMFIBEEPOUT
BEEP TONE Output
Width
MOTE lOW Output
Hold time 1
COll toCOl4
ROWl TO ROW4
tlOP
ms
ms
ms
continued on next page
7-141
D
MB87029
ELECTRICAL CHARACTERISTICS
Value
Parameter
Symbol
Pin Name
Hold time 2
luusP2
twrE
DUAL TONE Output
TIme
tWI)T
78
DTMF Interpause
Tillie
torp
78
Single Tone
Output start time
tslS
Single Tone
Output stop time
IsISP
DUAL TONE
Output start time
loTS
DUAL TONE
Output stop time
tDTSP
twrE LOW Output
Single Tone Output
Min
Max
Unit
8
ms
80
82
ms
80
82
ms
'1WI
0
31
SCNT-Veo
ms
DTMF/BEEPOUT
twrE Hold TIme 1
0
45
39
ms
ms
0
tpSMI
by PAUSE key
entry
D
Condition
5
ms
0
10
20
ms
75
90
105
ms
0
5
10
ms
twrE
twrE Hold TIme 2
by PAUSE key
entry
tpSM2
MODEOUT Blinking
Start time
tMOST
MODEOUT
DTMF OUTPUT SIGNALS
Item
Symbol
Standard DTMF
(Hz)
DTMF Output Signal·
(Hz)
Error to standard TDMF
(%)
ROW1
FR1
697
696.95
-0.01
ROW2
FR2
770
770.13
+0.02
ROW3
FRS
852
852.27
+0.03
ROW4
FR4
941
940.99
-0.01
COL1
FC1
1209
1209.31
+0.03
COL2
FC2
1336
1335.65
-0.03
COL3
FC3
1477
1476.71
-0.02
l'Iot8:
7-142
'USQ"ation rrequency 3.579545 MHZ
MB87029
Figure 4. Key Input Timing
Key Input - - -
VWvJ.~J
Notea:
Key Inpul Debouncing Tme tCH
Key entry is accepted if low lewl is longer than 23 ms typo
2Key Input Release Guard Time IRE
Key release is recognized" low level is longer than 23 ms typo
7-143
M887029
TIMING CHART 1-A
When there Is a ause before LOT ke In PULSE mode
HKS
OSCIN
OSCOUT
'H'
' L · ! I - - - , . , . - - - - - - - - - - -Iossp
----
I1!=l0§.S----------- --------...::w- ___ -
"W
"L'
_ _ _ _ _ ~711~
l:tb
--+-;1..1.------
'H!Hz~i-I~r-'I_I... t~
'L·:.!Kp, L!.J
KEY Entry
MODEIN
(OPEN)
"L·:FdJ
MODEIN
'H'
(Voo)
"H~HZIotI~r-1
--I I__ tWi(2
Ic::::.:::::.:.-
I
I
I
'H'
I-
"H'
I
I
:~:
I
'L'
I
_I I-
tpDP
U
tlDP
-I -; r- tWMA
LrulJ
11
I-
~ ~ twsJ.111
..11.-
L
~;..:I--~t~M0C2il!iL__I_f_-----II
tpAS
II
I
'!III
I
I
~I j.. tMST
M
II
tpSMl
I
..! I--lMus
5
I:-:-!I---+-----
q
~ ~tWBE
,.-Hi--1I:
..:::-I-]--[--------------------------"H'
BEEPOUT
II
(20 pps)
,,~~~~ 1--1
1 I
pOLSEoOI 'L'
I
----:::JJ
1 kH~'<10PPS)-
"l'---1-~
MODEOUT "L' HZ
DTMFOUT
I
I.!.l L!J 1:!9l.!.1
tBES-=.!
L----.
1k~
- -- ---------------------------
TIMING CHART 1-8
When there Is a ause before LOT ke In PULSE mode
HKS
"H"
"L·-II
____________________
OSCIN
OSCOUT
"W
"L'
KEY Entry
''H4t
"L' 1 L~~
I1
c= =____-3.579545bl~ _
lHZKS
-
L_--'-CiW~3"'.57t..:i9!>!:s4:!>!5~"MH7J(!!.H~z_'__
I
7
I
--l rtHzMI~
I
'L" I LtgJ IL::----- 1 kHz (10.Pe!!L.-_-==-::J---r---....
11r---k"'"H"i-l-I--"---
~~~~I~
'H"
MODEIN
"W
(Voo)
"L'
- ___ - ___ - ___ -
1
1
1
1
I
I
I
I L-.!..=.!!:.J.I_..J
I
I
1
1
I
I
I
I
(20 PPS)
'H" --t I-- tHZMcIs
~-~
MODEOUT "L'
Ltg.J jI
....
pOrtT[-..,-SE""o.....Ol"TT
"H'
"L'
DTMFOUT
"w
I-
I
tpDP
'UlI-
tlDP
I
!
I
"I
LrulJ I_
I
'-I-'t'""PAB--I-j
I
--I r-tDTS1oIr-toTSP
"L··-------------4!---...f.J!rt'1L----..JfWi"'1!---::~:'------.L..-_______.l1
BEEPOUT
7-144
I
I
~ ~1
___________________________________ _
""H'L-____
.-Hi---I----------------------------[--------
MB87029
TIMING CHART 2-A
When there Is no ause before or after LOT ke In PULSE mode
HKS
"H"
0L"---,L.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OSCIN
OSCOUT
KEY Entry
MODE IN
(OPEN)
"H"
MODEIN
(Voo)
"H"
"L"____ ..JI
MODEOUT
·H~--l
DTMFOUT
::~,___________________________
_
r~-!....--------------------------
"L"_l!~J
L.-_ _ ----1k~~--_---_
(20 pps)
III..
"L" HZ ...- - - - - - - - - - H
0H"
I 1;.--------------~~
u
LflIlJ
pU[sEoUT "L"
..I I.
tMOC2
~~L5t-=M~
"H"~--...,
I
I
JVflJTE
"L"
BEEPOUT
"H"~-HZ---~-W-Ir-]-----------------------------"L _____ ..JL._.Il_-'L_ _ ____________________________ _
TIMING CHART 2-B
When there Is no ause before or after LOT ke In PULSE mode
HKS
"H"
"L"-.fIL..
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OSCIN
OSCOUT
"H"
"L"~_ _
-==_
-==:.--, ___________
KEY Entry
-,-C
___
3.S79S45!AHz
:.
_~'-Pause release
"H"
r------------------------__W
P1 key
"L"---r~~
MODEIN
(OPEN)
°H'--r I
°L"
L~.J
MODEIN
oW
(Voo)
°L"
I
- - - - - ""[kHZi10-ppsr- (20 pps)
H
° '!-.-r-,-,
MODEOUT 0L"
L~.J IL..-_ _ _ _ _ _ _
"H"
..,pUnr[.....
sE""o.....U....1 "L"
DTMFOUT "W
°L"
"H"~--...,
U
i ___. . .
-+I--------r-------------
II
1-lo:,1
~~i-_~_o_PS_________________
1Ltuij
.
I
~I
LflIlJr+1-----iIr--------i
I
.j
r-
II
tMOST
~ ~ /PDT
~~-------
"L"
BEEPOUT
L ____________________________ (1,1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
:~-Hz---~---------------------~---------------
7-145
MB87029
TIMING CHART 3-A
InDTMFmode
HKS
"H"
OSCIN
OSCOUT
·L"'___
~"~~
ow
________________________________________________
___'__r.::.3.~57!!P45
__M_H_Ll_ ~~~L
KEY Entry
MODEOUT
"W-----h
I
I,
--:------1'"""---+---------------t-I
"L"---;'.L;-I
"H"
0;1,
"L"-HZ-,.LI_Ij-JI~_ _ _ _ __t!--+----------------
"H'
I
"w
tOT1
IMOC1
II
,."POnT[.....
SE
....O
....O....
' ~"I
DTMFOUT
"L"
~1 _
~
•
Is
1s"s1~ ~,. _"1J
..... IsISP
~
I
...
I
"H::'"----..;....,
"L"
BEEPOUT
.L._
Single to e
I
MODEIN
(GND)
-,
__-___ ].~57:.:::9::::54s~M~H::O'z_ _ _
__
....IMUSP1
--...--
Single tqne
I
.., t-- lMus
...
t--
IMUSP2
L---__
_______ ______
_________- :H~Hz---~-~-------a------~-~-a-~----------JL_~
~
~_~_~_~
TIMING CHART 3-B
InDTMFmode
HKS
OSCIN
OSCOUT
"H"
"L''----------------------------::~:
r3.5795~
"H"---1 _
KEY Entry
ilL"
MODEIN
(GND)
"w
MHz
"L'
H
MODEOUT "L"
I
I
POLSEOOl "L"
~
~
Pause release key
l!:J
I
"L"
tPUFH
... tpuFS
:~:--rJ
7-146
___-_---,---1._ _ _ __
lMOFH -I
r----'
____
..L-.....JI~-------------'--------HZ
iI
"H" ...
BEEPOUT
-
,!MO~;'-
~"",......... "H~·
DTMFOUT
3.579545 t..!,Hz
,.--_ _ _ _ _ _ _ _ _--,
LtJ
I
I
I
-L.-_-==-= _
-I.
h;;I
riLJ"'fLJ'tl
I
It:!
I
... r-
tPOT
f'\s'1L..-----I
0-1- - - -
L ___ L ________ L __________________ L ___________ _
:~-Hz-r--------r------------------r------------
MB87029
PACKAGE DIMENSIONS
22-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Caoe No.: DIP-22P-MOO)
INDEX-l
-,-
O
./In=ol"'i""l""l'i"'I""F'i'"'I""I'"'I"'I'I'"I""I"'I"""""""'-/~
.368 •.008
(9.10. Q.2O)
INDEX-2
24-LEAD PLASTIC FLAT PACKAGE
(Caoe No.: FPT-24P-M02)
.110
•
MAX
(SEATED HEIGHT)
""">----If- .Cl2O •
.ooa
(0.50.0.20)
1
TYP
.Q6O
..... __ ...... __ .. __ .... _,
DehrRloI-A-part
MAX
:
·····
··
·i
:
............ __ ............ _1
7-147
MB87029
7-148
cP
May 1991
Edition 2.0
FUJITSU
DATA SHEET
MB87057
DTMF RECEIVER
DUAL TONE MULTI FREQUENCY RECEIVER
The MB87057 is a one chip DTMF receiver wnh an input amplifier gain adjuster and
low power consumption, integrating fiHer and decoder circuits. The MB87057 can
automatically set guard times.
This circun consists of SCFs (Switched Capacnor Filters) and decoders which
convert 16 types of DTMF tone pairs into hexadecimal four-bn codes.
• All DTMF receiver functions are integrated on one chip.
• Low power consumption
• Built-in input amplifier gain adjustment circuit
• Automatic guard time setup
PLASTIC PACKAGE
(DIP-18P-M02)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
Supply VoHage
Voo
+6.0
V
Analog Input VoHage
VAIN
-0.3 to Voo + 0.3
V
Digital Input VoHage
VOIN
-0.3 to Voo + 0.3
V
Operating Temperature
T.
Oto+70
DC
Storage Temperature
T..
-5510 +125
DC
NOTE: Permanent device damage may occur Wthe above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods
may affect device reliabilny.
PLASTIC PACKAGE
(FPT-24P-M02)
This device contains circuitry to protect Ihe lnpula against
damage due to high static voltages or electric fields. However. it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages 10 Ihl. high 11l"!I"d'""" clrQJR.
CopyrlghtO 1991 by FUJITSU LIMITED
7-149
MB87057
PIN ASSIGNMENT
PIN ASSIGNMENT
(TOP VIEW)
AI.
PIN ASSIGNMENT
{TOP VIEW)
18
y""
YDD
2
17
GT
AI.
1
GA,
GA,
2
G..
3
16
OF
GAO
YAEl'
4
15
OS
Y-
GT
NC
OF
OS
AG
5
14
a.
TEST
6
13
Co
OSCl
7
12
a.
OSC2
8
11
0,
GND
9
10
TOE
NC
21
AG
TEST
OSCl
NC
NC
OSC2
GND
O.
O.
NC
NC
a.
12
TOE
0,
(FPT·24P·M02)
(DIP·1SP-M02)
D
10
11
BLOCK DIAGRAM
(DIP PACKAGE)
AnalogCircuit ---------------~------ Digital Circuit ------;
o.
o.
0,
OSCl
7-150
YDD
GND
OF
GT
OS
TOE
MB87057
PIN DESCRIPTIONS
A,.
Analog input pin (non-inverted operational amplifier input)
2
2
GA,
3
3
G..
0
Operational amplifier gain adjustment pin 1 (inverted operand amplWier input).
Operational amplWiergain adjustment pin 2 (operand amplWieroutput pin).
* These pins are provided for operational amplWier gain adjustment. The
polarity of Go, is oppos~e to that of G...
4
5
VPE.F
0
Reference voltage output pin. (112 VDD)
5
6
AG
6
7
TEST
Test pin. Usually set to ground level.
7
8
OSCl
8
11
OSC2
Clock input pin.
Clock output pin.
* Connect a 3.5795 MHz crystal between OSCl and OSC2 pins.
9
12
GND
Ground pin
10
13
TOE
Three-state output enable pin.
* Data from a, to a. may be output when this pin is set to "High".
11 to 14
14,15
18,19
a,toa.
0
Three-state data output pin.
15
20
DS
0
Signal detection pin.
* This pin goes to "High" when an available tone pair is received and decoded, and the data in the output data-bus is updated.
16
21
DF
0
Frequency detection pin.
* This pin goes to "High" when a received tone pair is acknowledged as
the valid DTMF signal frequency.
17
23
GT
0
Since "H" has been output, secure the pin in the "Open" or VDD position.
18
24
Voo
Positive supply voltage pin.
* The voltage must be +5 V:t5%.
4,9
10,16
17,22
NC
No connection
Analog ground pin
0
7-151
B
MB87057
FUNCTIONAL DESCRIPTIONS
1. FILTER
The fi~ers consist of 3 sixth-order SCFs. The dial tone removal filter (including the 60 Hz fitter). Output is connected to the individual
hysteresis comparators through the low group and high group filters.
In the figure below, the solid line shows the characteristics olthe low group filter while the broken line shows the characteristics olthe
high group filter. At a frequency of no Hz, ~ is assumed that 0 dB are lost. Therefore, this point is used for reference .
,,'
IA
I
I
Gain (dB) -SO
.
l_~-I
o
,
/
"
o
'If
~.
\
f
.,
,
\
I
I
__
I
VI=-10dBm _
T.-25°C _
\
11""1
1/
1'-
y
~
2
Frequency (kHz)
2. DECODER
2.1 Digital Frequency-detecting Circuit
The DF (Detect Frequency) pin goes to "High" when the detector circuit acknowledges the output signals from the two comparators
as valid DTMF signal frequencies in the digital frequency detecting block.
2.2 Guard Time Setup Circuit
The automatic setup mode is provided for guard time setup. Guard time has two types: GTP (Guard Time Present) and GTA
(Guard Time Absent).
2.2.1
Automatic guard·time setup circuit
The automatic guard time setup circuit sets both tGTP and IGT. to 20 ms. The output signal from the fitters may be acknowledged
as aOTMF signal if:
taTP + tPDF
tlDA > t_ + IGT.
7-152
MB87057
FUNCTIONAL DESCRIPTIONS
3. OUTPUT CIRCUIT
When the signal detector pin (OS) switches to "High", a received tone pair is stored in the output circun register. The output latch
status may be output on the output bus by setting the three state control input (TOE) to "High".
COLO
ROWO
ROW1
ROW2
ROW3
COL1
COl2
COL3
[J[][]G
8[][][]
[][][]G
[JG8G
DTMF Dial Matrix
4. SAMPLE DIFFERENCE INPUT CONFIGURATION
The MB87057 uses a difference input amplifier and provides for a bias power source (VREF) to apply a bias vohage to the input signal.
This also allows a pin to connect a gain adjustment resistor to the amplHier output.
Input ~ 1-....#,J1fv---.l-----{ )----f"........
~_60-_
Rl250kO
L
7-153
MB87057
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
v""
5.25
V
Input Voltage
V,
0
Voo
V
Oscillation Frequency
fose
3.5759
3.5831
MHz
OSCI Pin Load Capacitance
CLD!
10.0
50.0
pF
OSC2 Pin Load Capacitance
eu.,
10.0
50.0
pF
GA2 Pin Load Resistance
At..
50
GA2 Pin Load Capacnance
Co...
Operating temperature
T.
4.75
5.0
3.5795
kn
100
pF
70
·c
0
DC CHARACTERISTICS
Voo • 5 V ±5%. T. -
D
Supply Voltage
VDD
Power Consumption
PD
Low Level Input Voltage
V'L
High Level Input Voltage
V'H
Low Level Input Leak Current
I'L
High Level Input Leak Current
5.0
5.25
V
25
37
mW
0
0.8
V
2.0
V""
V
V,=GND
-10
10
!iA
I'H
V,. VOD
-10
10
!iA
Low Level Output Voltage
VOL
IOL-2mA
0
0.4
V
High Level Output Voltage
VOH
IOH.-o.4mA
2.4
Voo
V
VPIS' Output Voltage
V_
7-154
4.75
o·c to 70·C
f = 3.58 MHz. Voo - 5 V
2.5
V
MB87057
AC CHARACTERISTICS
Voo = 5 V ±50/0, T. = O°C to 70°C
T. = 25°C, Voo = 5 V
Signal Input Level
-29
TWIST
-10
-1
±10
dBm
dB
Allowable Frequency Deviation
±1.5±2 Hz
0/0
Prohibited Frequency Deviation
±3.5
0/0
Allowable Noise Level
-12
dB
Allowable Dial Tone Level
22
dB
Input Signal Detection Timing
tpOF
5
11
14
ms
Input Signal Detection Timing
t.o.
0.5
4
8.5
ms
Input Signal Enable Period (Accept)
Iso.
40
ms
Input Signal Enable Period (Reject)
lsoR
Inter-digit Pause (Accept)
tlPA
Inter-dig~
tlPR
Pause (Reject)
20
ms
40
9
ms
ms
3.5831
MHz
tr
110
ns
Clock Fall Time
If
110
ns
Clock Duty
DR
Input Clock Frequency
fiN
Clock Rise Time
*1
dBm: 600 ohm reference
*2
TWIST = High group tone vottage/Low group tone voltage
3.5759
3.5795
50
0/0
*3
Allowable noise = Total allowable noise within the range 300 Hz to 3.4 kHzlMinimum amplitude tone level in valid tone pairs
*4
Allowable dial tone level = Total allowable normal dial tone volume/Minimum amplitude tone in valid tone pairs
*5
See Timing Chart.
7-155
MB87057
TIMING CHART
Input
tIN
'N+l
~PA
~PR
IBOA
IADF
OF
IGTp
OS
GT
TOE - - - - ,
0,100.
III
7-156
~
I
<
#N
X
#N+ 1
MB87057
PACKAGE DIMENSIONS
18-LEAD PLASTIC DUAL IN·L1NE PACKAGE
(case No.: DIP-18P-M02)
b868~:g?~(22.05~g:~g)
~~~~~~'!
INDEX·1
T7
____
+
==~
15° MAX
.244±.01 0 .300(7.62)
(6.20±0.25) TYP
INOEX·2
/I2j:=;=r=r=;=:;=r=r=;=:;=;=;==r=;=;:=;=r=;Y~
.1 1047~i?12
(1.20~g·30)
.050(1.27)
MAX
.11·047~i?12
(1.20~g·30)
Lh
-
.......:Sl!§
.010±.002
(0.25±0.05)
.100(2.54)
TYP
Dimensions in
inches (millimeters)
7-157
MB87057
PACKAGE DIMENSIONS
24-LEAD PLASTIC DUAL IN·L1NE PACKAGE
(case NO.: FPT-24P-M02)
,110(2,80) MAX
(MOUNTING HEIGHT)
,382±,012
(9,20± 0,30)
INDEX
d
I
===t
II
,020±,OOB
(0,60±0,20)
,050(1,27)
.002(0 16 +0,06
--Il-,008 +-.001'
-0,02)
TYP
r--08t8il;of .;,-;: P'a'rt--l
"A"
I
I
.008(0.20)
I
: '=:;r-....~--±
I
~I-r' ,024(0,80)
: .......
,550(13,97) REF----!
I
,007(0,18)
MAX
,027(0,8B)
L______ ~~____ _
Dimensions in
inches (millimeters)
7·158
Section 8
Companding
Page
DevIce
8-3
Law
Operallon
Package
OplIona
P.-Law
SynciAsync
SynciAsync
l6-pin Plastic
l6-pad Plastic
A-Lew
DIP
LCC
• Available in North America only
8-1
CoderslDecodflfS fCQDECsl
8-2
I91ecommunjcatjons Data Book
00
FUJITSU
October 1991
DATA SHEET
MB602116022
PCMCODEC
The Fujitsu CMOS B06020 series consists of both ~-Iaw and A-law single-chip
codeclfilter ICs for either synchronous-only or sync/asyne operation. These
monolithic, single-channel, voice-frequency codecs incorporate both transmn and
receive circunries that are used for PCM (pulse coded modulation) systems.
•
Transmn high-pass and low-pass filters
•
Receive low-pass fitter wnh SinXlX Correction
•
Anti-aliasing filter
•
Conforms to CCITT and AT&T specifications
•
Synchronous and asynchronous operation: MB6021, MB6022
•
Serial data rates of 64 kHz to 3.152 MHz
•
PLL circuns as internal clock generator
•
Internal vottage reference
•
Internal auto-zero circun
•
TTL compatible dignal interface
Ceramic Package
CEROIP
DIP·16C-C04
•
Input gain adjust amplifier
•
Pin selectable on-chip analog loopback
•
~-Iaw:
•
Package: 16-pin ceramic DIP package (Suffix: -CZ)
MB6021
A-law: MB6022
Pin Assignment
D
ABSOLUTE MAXIMUM RATINGS
AIN
Pin
MB6021
MB6022
Min.
-{l.3
7
V
AG
-7
0.3
V
AOUT
-Vs
+Vs
V
VREFrr
Posnive Supply Vottage
+Vs
7
Negative Supply Voltage
-Vs
16
Reference Supply
Vottage
VREF
6
Analog Input Voltage
VAIN
1
Digital Input Vottage
VOIN1
8,9,10,
11,12
Digital Input Vottage
VOIN2
14
-55
TSTG
PDll
Unit
Symbol
Storage Temperature
DOUT
GA2
Max.
Rating
+Vs+0.3
V
-{l.3
+Vs+0.3
V
-Vs-O.3
+Vs+0.3
V
150
°C
-Vs-O.3
Note: Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
-VS
GA1
DG
XSYNC
RSYNC
+Vs
XClK
DIN
RClK
Th& device contains circuitry to protect the Inputs againat
damage due to high slatlc vollages Of electric fields. However, it
is advised that normal precautions be taken to avoid application
of any vottage higher than rnaxmum rated voltages to this high
in1'Jedance circuit
© 1991 by FUJITSU LIMITED and FulllSU M~roeloctron"". Inc.
8-3
MB6021
MB6022
BLOCK DIAGRAM
::f-----I
XSYNC
o-t--I=11C::1
' - - - - - 0 XCLK
POlL o--t-+-I~~~~
VREFfT
o-+-.+---------"f---------'
RSYNC
o-+---I=lP~LLCJ
. - - - - - 0 RCLK
AOUT
~I:>-----I~
+VS
8-4
DIN
-VS
AG
OG
MB6021
MB6022
FUNCTIONAL DESCRIPTION
The transmn section in the upper-half of the block diagram is composed of an input gain amplifier, an anti-aliasing filter (ANTI-ALIAS),
a band-pass fiker (COS, LPT, and HPF), and a compressing coder (CODER). An auto-zero circun (Al) is also included in this section.
The receive section (lower half) is composed of an expanding decoder (DECODER) and a low-pass fiker (LPF).
TRANSMIT SECTION
Analog signals are input to an operational amplifier to provide gain adjustment. This amplifier is followed by a 2nd order analog
anti-aliasing @er (ANTI-ALIAS). This filter provides attenuation of 40 dB (typical) at the 256 kHz effective clock frequency of the
following swnched capacnorcosine filter (COS). From the cosine filter, the signals enter a5th order low-pass (LPF) clocked at 128 kHz,
followed by a 3rd order high-pass fiker (HPF) clocked at 128 kHz. The resuking band-pass characteristics meet both the D31D4
specification and the CCIT G. 712 recommendation. The output olthe high-pass filter is then sampled by the coder (CODEC) at 8 kHz.
This coder transforms the analog signals into 8-bit words using compressing law. The encoded PCM data is then output serially from
the OUTPUT REGISTER at a frequency determined by the external clock, 64 kHz to 3. 152 MHz. An auto-zero circun (AZ) is utilized for
DC offset correction.
RECEIVE SECTION
This fiHer smooths the decoded signals and corrects for SinXlX attenuation caused by the 8 kHz sample and hold operation. The
decoder (DECODER) reconstructs the analog signals from the PCM data using expanding law. The decoder is followed by a 5th order
low pass filter (LPF). This filter smooths the decoded signals and corrects them for the SinXIX attenuation due to the 8 kHz sampling
and holding operation.
INTERNAL CLOCK
Two independent phase locked loops (PLL) generate internal clocks for the transmn and receive sections from the respective
synchronization clocks (XSYNC and RSYNC).
ANALOG LOOPBACK MODE
The analog loopback mode allows all decoding and coding functions to be exercised without using the analog input (AIN) and analog
output (AOUT). In this mode, a digital input signal is decoded and internally routed to the transmit filters.
The output is available from the digital output (DOUT). The analog output (AOUT) is forced tothe analog ground (AG) level. The analog
Ioopback mode is selected by connecting the PD/L input to the negative supply voltage (-VS).
POWER DOWN MODE
Two power down modes are provided. Thetransmit and receive sections independently go into power down operation inthe absense
olthe respective synchronization clock (XSYNC and RSYNC). Hthe external power down input (PD/L) is connected to a TTLiow level,
both the transmn and receive section are powered down regardless of the synchronization clocks. During power down operation,
AOUT is forced to the level of AG, and DOUT goes into a high-impedance state.
TEST MODE
The VREFIT pin is connected to-VS, test mode allows independent evaluation olthe coder and decoder. In this mode, AIN is internally
connected tothe inputofthe coder and ns output is available on the DOUT pin. Also, the output olthe decoder is made available on pin
AOUT.
8-5
MB6021
MB6022
PIN DESCRIPTION
MB6021, MB6022
8-6
Pin Name
Pin No.
AIN
1
Analog Input. This is an input pin for analog signals to be filtered and coded.
GAl
GA2
2
3
Gain Adjust 1
Gain Adjust 2
These pins are provided for adjusting the gain of transmit section. GAl and GA2 are the inverting
input and output of the amplifier, respectively. GA2 can drive a load impedance of 10 to 20 kQ and
50 pF or less.
AG
4
Analog Ground. All analog signals are referenced to this pin.
AOUT
5
Analog Output. This pin outputs the decoded and fiHered analog signals. Hcan drive a load im·
pedance of 3 kQ or greater, and 100 pF or less. This output is forced to AG level in the analog
Ioopback mode and power down mode.
VREFIf
6
Reference Voltage Supplylfest. This pin is provided for the supply of an external voltage refer·
ence, for the selection of an internal reference, or for the selection of test mode. If VREFIf is
greater than 2 V, the external voltage reference is selected. In this mode, a 2.5 V reference is recom mended. If this pin is at the TTL low level or left open, the internal reference (2.5 V) is selected. If this pin is connected to -VS, the test mode with the internal reference results. In this
mode, AIN is internally connected to the input of the coder and its output is available on the DOUT
pin.
Also, the output of the decoder is directly available on the AOUT pin.
+VS
7
Positive Voltage Supply, +5 V
DIN
8
Digital Input. This is a TTL compatible input to the decoder and accepts an eight-bit data word into
the shfft register on the falling edge of RCLK.
RCLK
9
Receive Clock. This TTL compatible input defines the bit rate on the receive PCM highway. The
device can operate with clock rates of 64 kHz to 3.152 MHz. The digital PCM codes are accepted
on the falling edge of the clock.
XCLK
10
Transmit Clock. This TTL compatible input defines the bit rate on the transmit PCM highway. The
device can operate with bit rates of 64 kHz to 3.152 MHz. The digital PCM codes are shifted out
of the digital output (DOUT) pin on the rising edge of the XCLK.
RSYNC
11
Receive Synchronization Clock. This TTL compatible input defines the beginning of the receive
timeslot on the receive PCM highway. It must be synchronized with RCLK. The clock rate is typically 8 kHz and its duration can be equal to or more than one RCLK cycle.
XSYNC
12
Transmit Synchronization Clock. This TTL compatible input defines the beginning of the transmit
timeslot on the transmit PCM highway. Hmust be synchronized with XCLK. The clock rate is typically 8 kHz and its duration can be equal to or more than one XCLK cycle.
DG
13
Digital Ground. All digital signals are reference to this pin.
PD/L
14
Power Down/Analog Loopback. This three level input is provided for the selection of power down
mode or analog loopback mode. If this pin is at the TTL high level, the normal operation is selected. If this pin is at the TTL low level, the device is powered down regardless of the synchronization clocks.
If this pin is connected to -VS, the analog loopback mode is selected. In this mode, the output of
the receive filter in internally connected to the input of the transmit filter and AOUT is forced to AG
level.
DOUT
15
Digital Output. This is a TTL compatible open-drain output. A pull-up resistor greater than 0.5 kQ
must be connected to + VS. PCM digital codes are shifted out of the device on the rising edges of
XCLK in a serial format. This output goes into high-impedance state when eight bits are shifted
out of the output sMt register.
-VS
16
Positive Voltage Supply, -5 V + 5%.
Description
± 5%.
MB6021
MB6022
RECOMMENDED OPERATING CONDITIONS
Value
Rating
Pin
Symbol
Min.
Typ.
Max.
Unit
7
+VS
+4.75
+5.0
+5.25
V
Negative Supply VoHage
16
-VS
-5.25
-5.0
-4.75
V
External Reference Voltage
6
V REF
-
2.5
-
V
Internal Reference Voltage"
6
V IREF
-0.8
0
0.8
Digital Output Load Resistance
15
ROI.
0.5
-
-
k.Q
Pos~ive
Supply Voltage
V
Digital Output Load Capac~ance
15
COl.
-
pF
5
RL
3
-
144
Analog Output Load Resistance
-
k.Q
Analog Output Load Capacitance
5
Ct
-
-
100
pF
Operating Temperature
-
Top
0
25
70
°C
Note:
"VREFfT Pin (pin No.6) may be left open to seleel Internal Reference VoHage
8-7
MB6021
MB6022
DC CHARACTERISTICS
(Recommended operating condnions unless otherwise noted.)
Value
Conditions
Pin
MB6021/22
Symbol
Operating
7
+Iys
Negative Supply Current
Operating
16
-Iys
Posttive Supply Current
XSYNC • RSYNC = VIL
SYNC.VIL
7
+IYSST
Parameter
Pos~ive
Supply Current
Power Down Mode
Negative Supply Current
POll. VIL
XSYNC _ RSYNC _ VIL
SYNC.VIL
Max.
Unit
7.0
10.0
mA
-10.0
-5.0
-
mA
-
1.0
2.0
mA
-
0.3
1.0
mA
-0.5
-0.1
-
mA
16
-IVSST
-0.5
-0.1
-
mA
6
IYREF
10
40
100
J.IA
Digital Input High Voltage
8,9,10,11,
12,14
VIH
2.0
-
+VS
V
Digital Input Low Voltage
8,9,10,11,
12,14
Vil
0
-
0.8
V
Digital Input High Current
8,9,10,11,
12,14
IIH
-
-
10
J.IA
Digital Input Low Current
8,9,10,11,
12,14
III
-
-
10
J.IA
Digital Input Capacnance
8,9,10,11,
12, 14
COIN1
-
-
10
pF
-
COIN2
-
-
20
pF
15
VOll
-
-
0.4
V
J.IA
Power Down Mode
Reference Supply Current
POll = VIL
VREFIT = 2.5 V
Digital Input Capacttance
Digital Output Low Voltage
8-8
Typ.
Min.
ROL = 0.5 k.Q
+IoL - 0.4 mA
Digital Output Leakage Current
15
ILO
10
15
-
12
pF
Analog Input Offset Voltage
1
CoeUT
AINOFF
-
-
Digital Output Capacttance
-200
0
200
mV
Analog Input Resistance
1
RAIN
300
k.Q
1
CAIN
-
10
pF
Analog Output Offset Voltage
5
AoUTOFF
-150
-
-
Analog Input Capacitance
150
mV
Analog Output Resistance
5
RAOUT
-
10
30
n
MB6021
MB6022
AC CHARACTERISTICS (MB6021, MB6022)
(Recommended operating cond~ions unless otherwise noted.)
Value
Conditions
Pin
MB6021122
Symbol
Min.
TYP·
Max.
Unit
Digital Input Rise Time
0.8 V -+ 2.0 V
8,9,10,
11,12
t,
-
-
50
ns
Digital Input Fall lime
2.0 V-+ 0.8 V
8,9,10,
11,12
It
-
50
ns
-
-
3152
kHz
-
ns
Parameter
Shift Clock Frequency
9, 10
Fc
64
Shift Clock High Width
VIH-2.0V
9, 10
tWCH
140
Shift Clock Low Width
VIL = 0.8 V
9, 10
twcL
140
-
11, 12
Fs
-
8
11,12
tWSH
1/Fc
Fc:MHz)
-
10,12
tsx
10,12
RCLK to DIN Delay
-
DIN to RCLK Delay
-
Synchronization Frequency
Synchronization High Width
XSYNC to XCLK Delay
XCLK to XSYNC Delay
RSYNC to RCLK Delay
RCLK to RSYNC Delay
XCLK or XSYNC to DOUT
Delay
XCLK to DOUT Delay
XCLK to DOUT Disable Time
DOUT Fall Time
Note:
-
-
kHz
-
117
IJ.A
100
-
-
ns
txs
50
-
ns
9,11
IsR
100
tRS
50
8,9
tRO
50
8,9
loR
50
-
ns
9,11
Note 1, Bit 1
10,12,15
tzo
30
-
-
200
ns
Note 1, Bit2-8
10,15
txo
30
-
ns
10,15
toz
30
-
-
High-Z
15
tOf
10
-
V1H = 2.0 V
-
-
ns
ns
ns
ns
-
ns
100
ns
DOUT Load Conditions: ROL = 0.5 kn, COL = 144 pF, +IoL = 0.4 mA
8-9
MB6021
MB6022
TIMING DIAGRAM
twCH
RCLK
RSYNC
2.0V
O.BV
2.0V
------
--------------
O.8V
------
--------------
twSH
DIN
8-10
2.0V
O.8V
-------
-
MB6021
MB6022
TRANSMISSION CHARACTERISTICS OF ~-LAW (MB6021)
(Recommended operating condnions unless otherwise noted.)
Value
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
-
-
dB
dB
dB
Signal to Distortion (A to A)
1020 Hz tone
(Cmessage)
+3 to -30 dBmO
-40dBmO
-45dBmO
SDA
35.0
30.0
25.0
Signal to Distortion (A to D)
1020 Hz tone
(Cmessage)
+3 to -30 dBmO
-40dBmO
-45dBmO
SDX
36.0
31.0
26.0
-
-
dB
dB
dB
Signal to Distortion (D to A)
1020 Hz tone
(Cmessage)
+3 to -30 dBmO
-40dBmO
-45dBmO
SDR
36.0
31.0
26.0
-
-
dB
dB
dB
Gain Tracking (A to A)
1020 Hz tone
+3 to -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO
GlX
-0.4
-0.8
-2.0
-
0.4
0.8
2.0
dB
dB
dB
Gain Tracking (A 10 D)
1020 Hz lone
+3 to -40 dBmO
-4010 -50 dBmO
-50 10 -55 dBmO
GlX
-0.2
-0.4
-0.8
-
0.2
0.4
0.8
dB
dB
dB
Gain Tracking (D to A)
1020 Hz lone
+310 -40 dBmO
-40 to -50 dBmO
-50 to -55 dBmO
GTR
-0.2
-0.4
-0.8
-
0.2
0.4
0.8
dB
dB
dB
FRA
24.0
-0.2
-0.2
-0.2
Note 1
64.0
0.3
1.6
dB
dB
dB
dB
dB
dB
FRX
24.0
-0.1
-0.1
-0.1
Nole2
32.0
-
0.15
0.8
dB
dB
dB
dB
dB
dB
FRR
-0.1
-0.1
-0.1
Note 2
32.0
-
0.15
0.8
dB
dB
dB
dB
dB
dB
Frequency Response (A to A)
01060Hz
60 to 300 Hz
300 to 3000 Hz
3000103400 Hz
3400 to 4600 Hz
4.6 to 12 kHz
Relative to 0 dBmO, 820 Hz
Frequency Response (A 10 D)
Oto 60 Hz
6010 300 Hz
300 to 3000 Hz
3000 to 3400 Hz
3400 to 4600 Hz
4.6 to 12 kHz
Relative to 0 dBmO, 820 Hz
Frequency Response (D to A)
Ot0300 Hz
300 to 3000 Hz
3000 to 3400 Hz
3400 to 4600 Hz
4.6 to 12 kHz
Relative to 0 dBmO, 820 Hz
Noles: 1.
29(I-Sin
1t(4000-1)
1200
)
2.
29 (1 -Sin
1t(4000-f)
1200
)
-
8-11
MB6021
MB6022
TRANSMISSION CHARACTERISTICS OF J.1-LAW (MB6021) (Continued)
Value
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
ICNA
-
-80
-72.0
dBmOc
-
-83
-74.0
dBmOc
-83
-78.0
dBmOc
-66
dB
-66
dB
-
VoP
-
V"",
Idle Channel Noise (A to A)
Cmessage
Idle Channel Noise (A to D)
Cmessage
ICNX
Idle Channel Noise (D to A)
Cmessage
ICNR
Crosstalk (A to A)
1020 Hz. OdBmO
CTA
-
Crosstalk (D to D)
1020 Hz. OdBmO
cm
-
Absolute level
Overload level 3.17 dMbO
VABS
-
2.500
Analog Input level
1020 Hz. OdBmO
±VS = ±S.O V. TA = 25°C
All
-
1.227
Analog Output level
1020 Hz. OdBmO
±VS = ±5.0 V. TA = 25°C
AOl
1.206
1.227
2.248
V"",
Gain Accuracy (A to A)
1020 Hz. OdBmO
Internal VREF
±VS = ±5.0 V. TA = 25°C
GAA
-0.5
-0.3
0
0
+0.5
+0.3
dB
dB
Gain Accuracy (A to D)
1020 Hz. OdBmO
Internal VREF
±VS = ±5.0 V. TA = 25°C
Variation with power supply
Variation with temperature
GAX
-0.25
-0.15
0
0
±0.02
±0.001
+0.25
+0.15
dB
dB
dB
dBt'C
Gain Accuracy (D to A)
1020 Hz. OdBmO
Internal VREF
±VS = ±5.0 V. TA = 25°C
Variation with power supply
Variation with temperature
GAR
-0.25
-0.15
0
0
±0.02
±O.OOt
+0.25
+0.15
dB
dB
dB
dBt'C
Propagation Delay (A to A)
FC~1544kHz
PDA
-
-
540
J.lS
8-12
-
MB6021
MB6022
TRANSMISSION CHARACTERISTICS OF J..l-LAW (MB6021) (Continued)
Value
Parameter
Delay to Dislortion (A to A)
Conditions
50010600 Hz
600 10 1000 Hz
1000 10 2600 Hz
2600 to 2800 Hz
1020 Hz, OdBmO
Relative to minimum delay
Symbol
Min.
"TYP.
Max.
Unit
DDA
-
-
1.5
0.75
0.25
1.5
ms
ms
ms
ms
PSRRA+
25
30
-
dB
PSRRA-
35
40
-
dB
o
Production Prooess
Test/Inspection
Production Prooess
and Test/Inspection
ac Gate (Sampling)
Note:
The How sequence may vary slighUy
with individual product type.
9-5
Quality and ReQability
9-6
Tsfscommuajcations para Bgqk
Section 10
Ordering Information -
I Page
At a Glance
TItle
10-3
10-4
IC Packages, Inserted Types
IC Packages, Surface Mounted Types
1~
Part Number System
10-1
Ordering Information
10-2
Telecommunications Data Book
Ie Packages
This section on Fujitsu packages is arranged as follows:
1. Package technology: inserted or surface mount types.
2. Package types within the technology.
3. Package type illustration and description with (a) package width(s) and (b) lead pitch
(when applicable).
4. Package material.
5. Package ordering code. This code appears as a suffix to the product part number. See Part Number System in this section.
For the most up-to-date device and packaging information, including available packages and exact ordering code, please contact your nearest Fujitsu Sales Office, Sales Representative, or Distributor. (See the
Sales Information section of this book.)
Inserted Packages
Paeka e1' e
DIP
SHDIP
SKDIP
SL
Deseri Hon
Dual In-fine Package
Package widths:
300,400, 600, 900 mil
Lead p~ch: 100 mil
Shrink Dual In-fine
Package
Lead p~ch: 70 mil
Skinny Dual In-line Package
Package width: 300 mil
Lead pitch: 100 mil
Paekage
Material
Plastic
CerDIP
Z
Ceramic w~h lrit seal
T
Ceramic with metal seal
C
Plastic
CerDIP
PSH
ZSH
Ceramic w~h lrit seal
TSH
Ceramic with metal seal
CSH
Plastic
CerDIP
ZSK
PSK
Ceramic w~h Ir~ seal
TSK
Ceramic with metal seal
CSK
Plastic
CerDIP
PSL
ZSL
Ceramic w~h Ir~ seal
TSL
Ceramic with metal seal
CSL
Pin Grid Array Package
Lead p~ch: 50/100 mil
Plastic
Ceramic with metal seal
PR
CR
Single In-line Packag
(For modules only.)
Plastic
PS
Single In-line Package
Lead p~eh: 100 mil
Plastic
PL
Slim Dual In-line Package
Package width: 400 mil
Lead pitch: 100 mil
DIP
PGA
iIiI
SIM
SIP
Continued on fJ8Xt page
10-3
Ordering Information
Telecommunications Data Book
Inserted Packages (Continued)
Package Type
Description
Zig-zag In-line Package
Package width: 100 mU
Lead pitch:50 mil
100 mil (modules)
ZIP
Package
Material
Fujitsu Ordering Code
(Suffix)
Plastic
PSZ
Package
Material
Fujitsu Ordering Code
(Suffix)
Surface Mount Packages
Package Type
Description
Ral (Disk Button type)
Package
Ceramic
CF
Leadless Chip Carrier
Lead pitch: 40, 50 mil
Ceramic with Fr. seal
TV
Ceramic with metal seal
CV
(Plastic) Leaded Chip Carrier
Lead pitch: 50 mil
Plastic
PDorPV
FPT
LCC
<>
PLCC
QFP
Quad Flat Package
Lead plch: 0.65, 0.80,
l.00mm;O.50mmfor
straight leads
Plastic
PFQ
Ceramic
CFQ
Shrink Quad Flat Package
Lead p~ch: 0.50 mm
Plastic
PFQVorPFV
Thin Quad Ral Package
(Thin profile)
Lead pitch: 0.50 mm
Plastic
PFT
Plastic
PJ
CJ
SQFP
1m
TQFP
Small Outline Package
~hJ-leads
SOJ
Lead pRch: 50 mil
Conlin
10-4
011
nextpage
Ceramic
Telecommunications Data Book
Orderina Information
Surface Mount Packages (Continued)
Package Type
Descrlptlon
Rat (Disk Button type)
Package
Package
Material
Ceramic
Fujitsu Ordering Code
(Suffix)
CF
FPT
Small Outline Package
Lead pkch: 50 mil
SOP
Shrink Small Outline
Package Lead Pkch:
0.65, 0.80, 1.00 mm
SSOP
Plastic
PF
Ceramic
CF
CeIpack wkh gullwing leads
ZFL
Ceramic wkh metal seal
end gullwing leads
CFL
Plastic
PFV
Thin Small Outline Package
Plastic wkh normal leads
PFTN
(Thin profile)
f-=:Plast-::-ic-w-::k:-h-re-verse---+---------;
Lead pkch: 0.50,
bend leads
PFTR
0.55,0.60 mm
TSOP
Memory cards
Package Type
fiB-Pln
card
Descrlptlon
Package
Material
68-PinCard
Plastic
Fujitsu Ordering Code
(Suffix)
-
~
10-5
Ordering Information
Telecommunications Data Book
Part Number System
Standard Products Part Number
Found on most Standard Products: Memory, Analog, Logic, Telecommunications, Microprocessor,
and Special Controller Products
l
II
T
I
MB
NNNNN
A
NN
A
NNN
L
Package Suffix
low Power Designator (When apPliCable)}
Speed Designator (When applicable)
Die Revision (When applicable)
Device Type
Fujitsu Designator
Part Number
S-Pln SMT Piezoelectric SAW Filter
F5
CB
T
1
NNNMNN _ GNNN _
N
l:. Tape and Reel
}
T = 1000IReei
R = 3000/Reel
Serial Number
Frequency Designator
Ceramic Package
Fujitsu Designator
Examples:
Memory Product, MB81C1001A-60 PFTN
MB
Fujitsu
81C1001 DRAM Device
A
Die Revision
60
Access Speed (60 ns)
L
Low Power Feature
PFTN
Plastic SOP (Package)
with normal leads
Telecommunications Product, MB87086AP
MB
Fujitsu
87086
PLL Device
A
Die Revision
P
Plastic DIP (Package)
10-6
Analog Product, MB3731 PS
MB
Fujitsu
3731
Audio Power Amplifier
PS
Plastic SIP (Package)
Controller Product,
MB
8876
A
C
MB8876AC
Fujitsu
Floppy Disk Controller
Die Revision
Ceramic DIP (Package)
with metal seal
Section 11
Sales Information - At a Glance
I
Page
11--3
11--3
11-4
11-6
1HI
11~
11-10
11-11
11-14
11-15
11-17
11-18
11-19
11-20
11-21
11-21
Title
Introduction to Fujitsu
Fujitsu Umited (Japan)
Fujitsu Microelectronics, Inc. (U.S.A.)
Fujitsu Electronic Devices Europe
Fujitsu Microelectronics Asia PTE Ltd. (Singapore)
Integrated Circuits Corporate Headquarters - Worldwide
FMI Sales Offices for North and South America
FMI Representatives - USA
FMI Representatives - Canada, Mexico, and Puerlo Rico
FMI Distributors - USA
FMI Distributors-Canada
FMG, FML, and FMIL Sales Offices for Europe
FMG, FML, and FMIL Distributors - Europe
FMAP Sales Offices for Asia, Australia and Oceania
FMAP Representatives - Asia and Australia
FMAP Distributors - Asia
11-1
Sales lnfprmatiqa
III
11-2
Telecpmrouofcatjpas Data Book
Telecommunications Data Book
Sales Information
Introduction to Fujitsu
Fujitsu Limited (Japan)
Fujitsu Limited was founded as a telecommunications equipment
manufacturer in 1935, and today is not only one of Japan's leading
telecommunications companies, but also one of the world's largest
computer manufacturers.
This leadership has resulted, at least in part, from the superb quality of the
company's semiconductors and electronic components. Manufactured by
the company's Electronics Devices Operations Group, these vital
electronic devices also contribute to the high reliability and performance of
products made by many other manufacturers around the world.
Today, Fujitsu is one of the world's top manufacturers of semiconductors
and electronic components. In Japan, Fujitsu's R&D laboratories for
semiconductor and electronic components are situated in Kawasaki and
Mie, and manufacturing works are located in Iwate, Aizu, Wakamatsu and
Suzaka. Fujitsu also has six affiliated manufacturing works in the country.
Overseas facilities in the U.S, Europe, and Asia also help to meet the
growing global demand for Fujitsu semiconductors and electronic
components.
Fujitsu enforces strict quality control at all stages of production, from
materials selection through manufacturing to final testing. As a result,
Fujitsu's electronic devices are known for their extremely high reliability
and excellent cost-to-performance ratio.
ill
Fujitsu manufactures a full line of semiconductors and electronic components to meet the diverse applications of a wide variety of customers.
Backed by Fujitsu's extensive R&D commitment equal to over 10 percent
of annual sales, Fujitsu's electronic devices stay on the cutting edge of
electronics technology.
11-3
Sales Information
Telecommunications Data Book
Introduction to Fujitsu
Fujitsu Microelectronics, Inc. (U.S.A.)
Fujitsu Microelectronics, Inc. (FMI), with headquarters in San Jose,
California, was established in 1979 as a wholly-owned Fujitsu Limited
subsidiary for the marketing, sales, and distribution of Fujitsu integrated
circuit and component products. Since 1979, FMI has grown to four
marketing divisions and two manufacturing divisions. FMI offers a
complete array of components including semiconductor products for its
customers throughout North and South America.
The Advanced Products Division (APD) is responsible for designing and
selling a full line of SPARC processors, peripheral chips, and the
EtherStar™ LAN controller that it designed. The EtherStar LAN controller is
the first VLSI device to integrate both StarLANTM and Ethernet® protocols
into one device. The core of APD's EtherStar chip was the result of a
cooperative venture with Ungermann-Bass.
The Microwave and Optoelectronics Division (MOD) markets GaAs FETs
and FET power amplifiers, lightwave and microwave devices, optical
devices, emitters, and 81 transistors.
The Electronic Components Division (ECD) markets connectors, keyboards, thermal printers, plasma displays, and relays.
The largest FMI marketing division is the Integrated Circuits Division (ICD)
which markets the following standard devices, components, and ASICs.
ID
11-4
Memory Products
BiCMOS SRAMs
Bipolar PROMs
CMOS Masked ROMs
CMOSSRAMs
DRAMs
ECLRAMs
EEPROMs
EPROMs
NOVRAMs
STRAMs (self-timed RAMs)
Memory Module Products
DRAM modules
Memory card Products
Memory Cards:
EPROM, Flash, OTPROM, and SRAM
Controller
DeSign kits
Programming adaptors
Telecommunication Products
CODECs
Modems
Piezoelectric devices
PLLs
Prescalers
Telephone ICs
VCOS
Telecommunications Data Book
Sales Information
Introduction to Fujitsu
Microprocessor Products
4-bit microcontrollers
DSPs
Logic Products
Interface devices
Translator circuits
Ultra high-speed ECl
Analog Products
Audio ICs
Comparators
Converters, NO and D/A
Darlington transistor arrays
Disk drive ICs
Linear devices
MOSFET arrays
Motor drivers
Operational amps
Power supply controllCs
RETs
VCOs
Hybrid Products
Custom modules
Multi-chip modules
Thick- and Thin-film
T2
Special Purpose Controller
Products
ASIC Products
SCSI controllers
Data communication controllers:
ECC, Ethernet, Floppy disk, Multiprotocol, and DMA
Video controllers:
CRT, PIP, and TV display
CMOS gate arrays (channeled and channelless)
ECl gate arrays
SiCMOS gate arrays
GaAs gate arrays
CMOS standard cells
ASIC GalieryTM (SuperMacros™, Compiled Cells)
CAD Reference Environment that integrates with
third-party CAD tools
ill
11-5
Sales Information
Telecommunications Data Book
Introduction to Fujitsu
Design and customer support for ASIC products are available throughout
the country and at FMI Sales Offices located in Atlanta, Boston, Chicago,
Dallas, Denver, Irvine, Minneapolis, Portland, and San Jose,
FMl's manufacturing divisions are in San Diego, California and Gresham,
Oregon. The San Diego Manufacturing Division (SMD) assembles and
tests memory devices. The Gresham Manufacturing Division (GMD) began
manufacturing in 1988. GMD fabricates wafers, and produces ASIC
products and DRAM memories.
ID
11-6
Telecommunications Data Book
Sales Information
Introduction to Fujitsu
Fujitsu Electronic Devices Europe:
Fujitsu Mikroelektronlk GmbH (FMG), West Germany
Fujitsu Microelectronics Limited (FML), U.K.
Fujitsu Microelectronics Italla S.R.L (FMIL), Italy
Fujitsu Microelectronics Ireland, Ltd. (FME), Ireland
Fujitsu Mikroelektronik GmbH (FMG) was established in June 1980 in
Frankfurt, West Germany, as Fujitsu's European headquarters and is a
totally owned subsidiary of Fujitsu Limited, Tokyo. Fujitsu Microelectronics
Limited (FML) is a sister company based in Maidenhead, England and
dedicated to serving the U.K., Ireland, and Scandanavia. Fujitsu Microelectronics Italia (FMIL) is based in Milan, Italy and serves Italy, Spain,
Portugal, and the rest of Southern Europe. Together, FMG, FML, and
FMIL supply the European market with a full range of semiconductors and
electronic components. Sales offices are located in Munich, Frankfurt,
Stuttgart, PariS, Eindhoven, Milan, Maidenhead, and Stockholm.
Fujitsu Microelectronics Ireland, Ltd. (FME) was established in 1980, in
Dublin, Ireland, as Fujitsu's European Assembly Center for integrated
circuits. FME produces DRAMs, EPROMs, and other LSI memory
products.
Fujitsu has two European VLSI design centers, both in the U.K. The
Manchester Design Center, in operation since 1983, is equipped with two
mainframe computers and is linked by satellite to production plants in
Japan and the U.S. Staffed with a team of experienced engineers, the
center is involved in the design of VLSI standard products, SuperMacros,
CAD tools and ASICs. A second design center was set up in London in
1990 for designing telecommunication ICs. Additionally, Fujitsu offers a
network of 17 ASIC deSign centers in eight European countries.
Fujitsu has further demonstrated its commitment to the European market
by commencing construction of a full wafer fabrication plant in Durham in
the North of England. The new plant is due to start production of 4
megabyte DRAMs and ASICs in 1991.
ill
11-7
Sales Information
Telecommunications Data Book
Introduction to Fujitsu
The range of semiconductor products offered by FMG, FMl, and FMll for
the European market includes:
ID
Memory Products
DRAMs
SRAMs
EPROMs
EEPROMs
Mask ROMs
Bipolar PROMs
Video RAMs
EClRAMs
Memory modules
Memory cards
ASIC Products
CMOS gate arrays
BiCMOS gate arrays
Bipolar (ECl) gate arrays
Gallium Arsenide gate arrays
CMOS standard cells
ECl gate masterslice devices
Wide range of ASIC design software
Microprocessor Products
4-Bit Microcontrollers
4- 8- and 16-bit F2MC flexible Microcontrollers
32-Bit SPARCTM RISC microprocessors
32-Bit GMICRO™ TRON-based CISC microprocessors
Telecommunication Products
Prescalers
PlLs
COOECs
LAN devices
OSPs
SCSI and LAN devices
ISDN products
Telecom devices for the GSM
Pan-European digital cellular telephone system.
Analog Products
OPAmps
Comparators
NO and 01A Converters
Application Specific ICs
The range of electronic components offered by FMG, FMl, and FMll
incudes relays, connectors, keyboards, thermal printers, plasma displays,
liquid crystal displays, hybrid ICs, and piezoelectric devices.
11-8
Telecommunications Data Book
Sales Information
Introduction to Fujitsu
Fujitsu Microelectronics Asia PTE Ltd. (Singapore)
Fujitsu Microelectronics Asia PTE Ltd. (FMAP) opened in August 1986, in
Hong Kong, as a wholly-owned Fujitsu subsidiary for sales of electronic
devices to the Asian, Australian, and Southwest Pacific markets. In 1990,
FMAP moved to a new location in Singapore.
FMAP offers memory, ASIC, microprocessor, and telecommunication
products along with Fujitsu's wide range of electronic components.
SPARe- is a trademark 01 Spare Intemational.
EtharnatR ill a regi8tefed trademark of Xerox Corporation.
Ethers,a,TM II a trademark 01 Fujitsu Microelectronics, Inc.
SUuLMiTM Is a trademark of AT&T.
o..CAO~ is a trademark 01 Hitachi
SuperMacro™iB a trademark d Fufltsu Microelectronics. Inc.
ASlCOpen™ Is a trademark of Fujitsu Microelectronics, Inc.
VIEMCAOlIII is a trademark 01 Fujitsu Mlc:rosIecrronics. Inc.
III
11-9
Sales Information
Telecommunications Data Book
Integrated Circuits Corporate Headquarters -
Worldwide
International Corporate Headquaners
FUJITSU LIMITED
Marunouchi Headquarters
6-1, Marunouchi l--<:home
Chiyoda-ku, Tokyo 100
Japan
Tel: (03) 3216-3211
Telex: 781-22833
FAX: (03) 3213-7174
For integrated circuits marketing information please contact the
following:
HeadquanersforJapan
FUJITSU LIMITED
Integrated Circuits and Semiconductor Marketing
Furukawa 5ogo Bldg.
6-1, Marunouchi 2-chome
Chiyoda-ku, Tokyo 100
Japan
Tel: (03) 3216-3211
Telex: 781-2224361
FAX: (03) 3211-3987
Headquaners for Nonh and South America
FUJITSU MICROELECTRONICS, INC.
Integrated Circuits Division
3545 North First Street
San Jose, CA 95134-1804
USA
Tel: (408) 922-9000
Telex: 910-336-0190
FAX: (408) 432-9044
Headquaners for Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
6072 Dreieich-Buchschlag
Germany
Tel: (06) 1036900
Telex: 411963
FAX: (06) 103 690122
lID
Headquaners for Asia, Australia and Oceania
FUJITSU MICROELECTRONICS ASIA PTE LIMITED
06-04/-07 Plaza By The Park
No. 51 Bras Basah Road
Singapore 0718
Tel: (65) 336-1600
Telex: RS 55573 FESPL
FAX: (65) 336-1609
11-10
Telecommunications Data Book
Sales Information
Fujitsu Microelectronics, Inc. (FMI) Sales Offices - North and
South America
NORTHERN CALIFORNIA
ILLINOIS (Chicago)
NEW YORK (Hauppauge)
Fujitsu Microelectronics, Inc.
100ooN. De Anza Blvd.
Suite 225
Cupertino, CA 95014
Tel: (408) 996-1600
FAX: (408) 725-8746
Fujitsu Microelectronics, Inc.
One Pierce Place
Suite 1130 West
Itasca,IL60143-2681
Tel: (708) 250-8580
FAX: (708) 250-8591
Fujitsu Microelectronics, Inc.
601 Veterans Memorial Highway
Suite P
Hauppauge, NY 11788-1054
Tel: (516) 361-6565
FAX: (516) 361-6480
SOUTHERN CALIFORNIA
MASSACHUSETTS (Boston)
OREGON (Portland)
Fujitsu Microelectronics, Inc.
Century Centre
2603 Main Street
Suite 510
Irvine, CA 92714
Tel: (714) 724-an7
FAX: (714) 724-an8
Fujitsu Microelectronics, Inc.
Bay Colony Corp. Center
Suite 2500
1000 Winter Street
Waltham, MA 02154
Tel: (617) 487-0029
FAX: (617) 890-9002
Fujitsu Microelectronics, Inc.
15220 NW Greenbrier Pkwy
Suite 360
Beaverton, OR 97006
Tel: (503) 690-1909
FAX: (503) 690-8074
COLORADO (Denver)
MINNESOTA (Minneapolis)
Fujitsu Microelectronics, Inc.
5445 DTC Parkway
Suite 300
Englewood, CO 80111
Tel: (303) 740-8880
FAX: (303) 74O-a988
Fujitsu Microelectronics, Inc.
3460 Washington Drive
Suite 209
Eagan, MN 55122·-1303
Tel: (612) 454"'()323
FAX: (612) 454"'()601
Fujitsu Microelectronics, Inc.
14785 Preston Road
Suite 274
Dallas, TX 75240
Tel: (214) 233-9394
FAX: (214) 386-7917
TEXAS (Dallas)
GEORGIA (Atlanta)
Fujitsu Microelectronics, Inc.
3500 Parkway Lane
Suite 210
Norcross, GA 30092
Tel: (404) 449-8539
FAX: (404) 441-2016
III
11-11
Sales Information
Telecommunications Data Book
FMI Sales Representatives - USA
For product information, contact your nearest FujRsu representative.
Alabama
CSR Electronics
Huntsville, AL
Tel: (205) 533-2444
FAX: (205) 536-4031
District of Columbia
Arbotek Associates
Towson, MD
Tel: (301) 825-0775
FAX: (301)337-2781
Iowa
Electromec Sales
Cedar Rapids, IA
Tel: (319) 393-1637
FAX: (319)393-1752
Arizona
Aztech Component Sales Inc.
Scottsdale, /lZ.
Tel: (602) 991--eaoo
FAX:(602) 991-0563
Florida
Semtronic Associates, Inc.
Altamonte Springs, FL
Tel: (407) 831-a233
FAX: (407) 831-2844
Kansas
Rothkopf 8< Associates, Inc.
Olathe, KS
Tel: (913) 829-8897
FAX: (913) 829-1664
Arkansas
Technical Marketing, Inc.
Semtronic Associates, Inc.
Clearweter, FL
Tel: (813) 461--4675
FAX: (813) 442-2234
Carrollton, TX
Tel: (214) 387-3601
FAX:(214) 387...,'3605
california
Northern California
Norcomp
Santa Clara, CA
Tel: (408) 727-7707
FAX: (408) 986-1947
Norcomp
Roseville, CA
Tel: (916) 782--8070
FAX: (916) 782--8073
Southern California
Infinity Sales, Inc.
Newport Beach, CA
Tel: (714) 833-0300
FAX: (714) 833-0303
San Diego County
Harvey King, Inc.
San Diego, CA
Tel: (619) 587--S300
FAX: (619) 587-0507
Samtronic Associates, Inc.
Ft. Lauderdale, FL
Tel: (305) 731-2484
FAX: (305) 731-1019
III]
Connecticut
Conntech Sales, Inc.
Cheshire, CT
Tel: (203) 272-1277
FAX: (203) 272-2790
Delaware
BGR Associates
Marlton, NJ
Tel: (609) 983-1020
FAX: (609)983-1879
11-12
Louisiana
Technical Marketing, Inc.
Carrol~on,
Georgia
CSR Electronics
AUanta, GA
Tel: (404) 396-3720
FAX: (404) 394-a387
Idaho
Northern Idaho
L-Squared, Lid.
Kirkland, WA
Tel: (206) 827-8555
FAX: (206) 828-0102
TX
Tel: (214) 387...,'36Ql
FAX; (214) 387...,'3605
Technical Marketing, Inc.
Houston, TX
Tel: (713) 783-4497
FAX: (713) 783-5307
Maine
Mill-Bern Associates
Wobum,MA
Tel: (617) 932...,'3311
FAX: (617) 932-0511
Southern Idaho
Intermountain Technical Marketing
Meridan,lD
Tel: (208) 888-0071
FAX: (208) 888-0074
Illinois
Colorado
Talisman Assoc.
Englewood, CO
Tel: (303) 773-2533
FAX: (303) 741--6312
Kentucky
Fujitsu Microelectronics, Inc.
Itasca,lL
Tel: (708) 250-8580
FAX: (708) 250-8591
Northern IlHnois
Beta Technology
Itasca,IL
Tel: (708) 250-9586
FAX: (708) 250--S592
Maryland
Arbotek Associates
Towson, MD
Tel: (301) 825-0775
FAX: (301) 337-2781
Massachusetts
Mill-Bern Associates
Wobum,MA
Tel: (617) 932-3311
FAX: (617)932-0511
Southern Illinois
Rothkopf 8< Assoc.
St. Louis, Me
Tel: (314) 961-4485
FAX: (314) 961-4736
Indiana
Fujitsu Microelectronics, Inc.
Itasca,IL
Tel: (708) 250-8580
FAX: (708) 250-8591
Michigan
R.C. Merchant 8< Co., Inc.
Farmington Hills, MI
Tel: (313) 476-4600
FAX: (313) 476...,'3162
R.C. Merchant 8< Co., Inc.
St. Joseph, MI
Tel: (616) 983-7378
FAX: (616) 983-3506
Telecommunications Data Book
Sales Information
FMI Sales Representatives - USA (Continued)
Minnesota
Electromec Sales
Burnsville, MN
Tel: (612) 8~200
FAX: (612)894-9352
New Hampshire
Mill-Bern Assoc.
Wobum,MA
Tel: (617) 932-3311
FAX; (617-932-0511
North Dakota
Electromec Sales
Burnsville, MN
Tel: (612) 894-9200
FAX: (612) 894-9352
Mississippi
CSR Electronics
Huntsville, AL
Tel: (205) 533-2444
FAX: (205) 536-4031
New Jersey
Northern New Jersey
Technical Applications & Marketing
Fairfield, NJ
Tel: (201) 575-4130
FAX: (201) 575-4563
Ohio
Stegman Blaine Marketing, Inc.
Cincinnati, OH
Tel: (513) 729-1969
FAX: (513) 729-1984
Missouri
Rothkopf & Associates, Inc.
SI. Louis, Me
Tel: (314) 961-4485
FAX: (314) 961-4736
Southern New Jersey
BGR Associates
Mariton, NJ
Tel: (609) 983-1020
FAX: (609) 983-1879
Montana
Eastern Montana
Talisman Assoc.
Englewood, CO
Tel: (303) n3-2533
FAX: (303) 741-6312
New Mexico
Aztech Component Sales, Inc.
Scottsdale, AZ
Tel: (602) 991-6300
FAX: (602) 991-0563
Western Montena
Intermountain Technical Marketing
Meridan,lD
Tel: (208) 888-0071
FAX: (208) 888-6074
New York
Northem New York
Quality Components
Buffalo, NY
Tel: (716) 837-5430
FAX: (716) 837-0662
Nebraska
Eastern Nebraska
Rothkopf & Assoc.
Olathe, KS
Tel: (913) 829-8897
FAX: (913) 829-1664
Quality Components
Manlius, NY
Tel: (315) 682-8885
FAX: (315) 682-2277
Nebraska (Continued)
Western Nebraska
Talisman Assoc.
Englewood, CO
Tel: (303) n3-2533
FAX: (303) 741-6312
Nevada
Northem Nevada
Norcomp
Roseville, CA
Tel: (916) 782-8070
FAX: (916) 782-8073
Southern Nevada
Atech Component Sales, Inc.
Scottsdale, AZ
Tel: (602) 991-6300
FAX: (602) 991-0563
Stegman Blaine Marketing, Inc.
Cleveland, OH
Tel: (216) 572-0003
FAX; (216) 238-3229
Stegman Blaine Marketing, Inc.
Vandalia, OH
Tel: (513) 890-7975
FAX: (513) 890--5191
Oklahoma
Technical Marketing, Inc.
Carrollton, TX
Tel: (214) 387-3601
FAX: (214) 387-3605
Oregon
L-Squared Limited
Beaverton, OR
Tel: (503) 629-9555
FAX: (503)845-6196
Quality Components
Rochester, NY
Tel: (716) 342-7229
FAX: (716) 342-7227
Pennsylvania
Eastern Pennsylvania
BGR Associates
Marlton, NJ
Tel: (609) 983-1020
FAX: (609) 983-1879
Southern New York
Technical Applications & Mktg.
Fairfield, NJ
Tel: (201) 575-4130
FAX: (201) 575-4563
Western Pennsylvania
Stegman Blaine Marketing, Inc.
Cincinnati,OH
Tel: (513) 729-1969
FAX: (513) 729-1984
North Carolina
CSR Electronics
Chariotte, NC
Tel: (704) 847--5806
FAX: (704) 847-0056
Rhode Island
Mill-Bern Associates
Woburn, MA
Tel: (617) 932-3311
FAX: (617) 932-0511
CSR Electronics
Raleigh, NC
Tel: (919) 878--9200
FAX: (919) 878--9117
South Carolina
CSR Electronics
Raleigh, NC
Tel: (919) 878--9200
FAX: (919) 878--9117
iD
11-13
Telecommunications Data Book
Sales Information
FMI Sales Representatives - USA (Continued)
South Dakota
Electromec Sales
Burnsville, MN
Tel: (612) 894-8200
FAX; (612) 894-9352
Tennessee
Eastern Tannessee
CSR Electronics
Knoxville, TN
Tel: (615) 837-0293
FAX: (615) 637-0466
Western Tennessee
CSR Electronics
Huntsville, AL
Tel: (205) 533-2444
FAX: (205) 536-4031
Texas
Technical Marketing, Inc.
Carrollton, TX
Tel: (214) 387-3601
FAX: (214) 387-3605
Technical Marketing, Inc.
Houston, TX
Tel: (713) 783-4497
FAX: (713) 783-0307
11-14
Technical Marketing, Inc.
Round Rock, TX
Tel: (512) 244-2291
FAX; (512) 388-1596
Utah
R-Squared Marketing
Salt Lake City, UT
Tel: (801) 595-0631
FAX: (801) 595-0435
Vermont
Mill-Bern Associates
Woburn,MA
Tel: (617) 932->'3311
FAX: (617)932-0511
Virginia
Arbotek Associates
Towson, MD
Tel: (30 1) 825-0775
FAX: (301) 337-2781
Washington
L-Squared Limited
Kirkland, WA
Tel: (206) 827-8555
FAX; (206) 8~102
Wisconsin
Eastsrn Wisccnsin
Beta Technology
Milwaukee, WI
Tel: (414)5~609
FAX; (414) 543-9288
Westem Wisccnsin
Electromec Sales
Burnsville, MN
Tel: (612) 894-8200
FAX: (612) 894-9352
West Virginia
Stegman Blaine Marketing, Inc.
Cincinnati,OH
Tel: (513) 729-1969
FAX: (513) 72~1984
Wyoming
Talisman Assoc.
Englewood, CO
Tel: (303) 773-2533
FAX; (303) 741~12
Telecommunications Data Book
Sales Information
FMI Sales Representatives - Canada, Mexico, Puerto Rico,
Central and South America
Canada
Mexico
Central and South America
British Columbia
Solano EI9CII'onica (Sonika)
Guadalajara, JAl.
All Countries
Fujitsu Microelectronics, Inc.
Headquarter Sales
San Jose, CA
l-Squared,lTD.
Kirldand, WA
Tel: (206) 827-8555
FAX: (206) 828--6102
Tel: (52) 3647--4250
FAX: (52) 3647-8433
Pipe-Thompson limited
Solano Electronics, S.A. De C.V.
07300 Mexico City, D.F.
Tel: (52) 5754 6480
Islington, Ontario
FAX: (52)5581h9443
Rest of Canada
Tel: (408) 922-9310
FAX; (408) 432-9044
Tel: (416) 236-2355
FAX: (416) 236-3387
Puerto Rico
Pipe-Thompson limited
Semtronic Associates, Inc.
Hato Ray, Puerto Rico
Kandata, Ontario
Tel: (613) 591-1821
FAX: (613) 591-4161
Tel: (809) 766-0700
FAX: (813) 442--2234
11-15
Telecommunications Data Book
Sales Information
FMI Distributors -.;.. USA
Alabama
Marshall Industries
Huntsville, AL
(205) 881-9235
Reptron Electronics
Huntsville, AL
Merit Electronics
San Jose, CA
(408) 434-0800
Milgray Electronics
Camarillo,CA
(805) 484-4055
(205) 722-9565
Milgray Electronics
Irvine, CA
Arizona
(714) 753-1282
Insight Electronics
Tempe,AZ
(602) 829-1800
Marshall Industries
Phoenix,AZ
(602)49~90
california
Bell Microproducts
Fountain Valley, CA
(714) 963-0667
Bell Microproducts
Milpitas, CA
(408)434-1150
Insight Electronics
Agoura, CA
(818) 707-2100
Insight Electronics
Irvine, CA
(714) 727-2111
Insight Electronics
San Diego, CA
(818)407-4100
Marshall Industries
EI Monte, CA
(818) 307-60000z
Marshall Industries
Irvine, CA
III]
(714) 458-5318
Marshall Industries
Milpitas, CA
(408) 942-4600
Marshall Industries
Rancho Cordova, CA
(916) 635-9700
Marshall Industries
San Diego, CA
(619)578-9600
11-16
Marshall Industries
Norcross, GA
(404) 923-5750
Milgray Electronics
Norcross, GA
(404)446-9n7
Reptron Electronics
Norcross, GA
Western Microtechnology
San Diego, CA
(404) 446--1300
(619)453-8430
illinois
Western Microtechnology
Saratoga, CA
(408) 725-1660
Colorado
Classic Components
Northbrook, IL
(312) 272-9650
Marshall Industries
Schaumburg, IL
Insight Electronics
Aurora, CO
(303) 693-4256
(312)~155
Marshall Industries
Thomton,CO
(303) 451-8383
(708)202-1900
Connecticut
Marshall Industries
Wallingford, CT
(203) 265-3822
Milgray Electronics
Palatine,lL
Reptron Electronics
Schaumburg, IL
(312) 882-1700
Indiana
Marshall Industries
Indianapolis, IN
Milgray Electronics
Millord, CT
(317) 297-0483
(203) 878-6538
Kansas
Florida
Marshall Industries
Lenexa, KS
(619) 587-9757
Marshall Industries
Chatsworth, CA
Georgia
Marshall Industries
Altamonte Springs, FL
(407) 767-8585
Marshall Industries
Ft Lauderdale, FL
(305) 9n-4880
Marshall Industries
SI. Petersburg, FL
(813) 573-1399
Milgray Electronics
Winter Park, FL
(407) 647--5747
Reptron Electronics
Ft. Lauderdale, FL
(305) 735-1112
Reptron Electronics
Tampa,FL
(813) 855-4656
(913)492~121
Milgray Electronics
Overland Park, KS
(913) 236-8800
Maryland
Marshall Industries
Silver Springs, MD
(301)622-1118
Milgray Electronics
Columbia, MD
(301)995-6169
Vantage Components, Inc.
Columbia, MD
(301) 720--5100
Telecommunications Data Book
FMI Distributors Massachusetts
Bell Microproducts
Wilmington, MA
(508) 658-0222
Interface Electronic Corp.
Hopkinton, MA
(508) 43!Hl858
Marshall Industries
Wilmington, MA
(508) 658-0810
Milgray Electronics
Wilmington, MA
(508) 657-5900
Vantage Components, Inc.
Andover, MA
(508) 687-3900
Western Microtechnology
Burlington, MA
(617) 273-2800
Michigan
Marshall Industries
Livonia, MI
(313) 525-5850
Sales Information
USA (Continued)
Milgray Electronics
Mar1ton,NJ
Marshall Industries
5o10n,OH
(609) 983-5010
(216)248-1788
Milgray Electronics
Parsippany, NJ
Milgray Electronics
Cleveland, OH
(201)335-1766
(216)447-1520
Vantage Components, Inc.
Clilton, NJ
Reptron Electronics
5o10n,OH
(201) 777-4100
(216)349-1415
Western Microtechnology, Inc.
Fairfield, NJ
Reptron Electronics
Worlhington, OH
(20 1) 882-4999
(614)436-6675
New York
Oregon
Marshall Industries
Hauppauge, NY
Marshall Industries
Beaverton, OR
(516) 273-2424
(503) 644-5050
Marshall Industries
Johnson City, NY
Western Microtechnology
Beaverton, OR
(607) 785-2345
(503) 629-2082
Marshall Industries
Rochester, NY
Pennsylvania
(716) 235-7620
Marshall Industries
Pittsburg, PA
Mast Distributors
Ronkonkoma, NY
(412) 788-0441
(516) 471-4422
Texas
(313) 525-2700
Milgray Electronics
Farmingdale, NY
Minnesota
Insight Electronics, Inc.
Richardson, TX
(516) 420-9800
(214) 783-0800
Milgray Electronics
Pittsford, NY
Marshall Industries
Austin, TX
(716) 381-9700
(512)837-1991
Vantage Components, Inc.
Smithtown, NY
Marshall Industries
Carrollton, TX
Reptron Electronics
Livonia, MI
Marshall Industries
Plymouth, MN
(612) 559-2211
Reptron Electronics
Minnetonka, MN
(612) 938-3995
Missouri
Marshall Industries
Bridgeton, MO
(314) 291-4650
New Jersey
Interface Electronics
Marlton, NJ
(609) 988-5448
Marshall Industries
Fairfield, NJ
(201) 882-0320
(516) 543-2000
(214) 233-5200
North Carolina
Marshall Industries
EI Paso, TX
Marshall Industries
Raleigh, NC
(919) 878-9682
(915) 593-0706
Marshall Industries
Harlingen, TX
Reptron Electronics
Raleigh, NC
(512) 421-4621
(919) 870-5189
Milgray Electronics
Dallas, TX
Ohio
(214) 248-1603
Marshall Industries
Dayton,OH
Western Microtechnology, Inc.
Dallas, TX
(513) 898-4480
(214)418-0103
iD
Marshall Industries
MI. Laurel, NJ
(609) 234-9100
11-17
Sales Information
FMI Distributors Utah
Telecommunications Data Book
USA (Continued)
Marshall Industries
Bothwell,WA
Marshall Industries
Salt Lake Cily, UT
(801) 973-2288
(206) 486-0747
Milgray Electronics
Salt Lake CiIy, UT
(801) 272--4999
(206) 869-7557
Washington
Merit EIeCb'ic
Redmond,WA
Western Microtechnology
Redmond,WA
(206) 881-6737
Insight Electronics, Inc.
Kirkland, WA
FMI Distributors - Canada
Quebec
Marshall Industries
Bramton,ON
Marshall Industries
Pointe Claire, au
(416) 458-8046
(514)683-9440
Milgray Electronics
Willowdale, ON
Active Components
Point Claire, au
(514)694-7710
(416) 756-4481
II]
11-18
Marsh Electronics
Milwaukee, WI
(414)475-6000
Marshall Industries
Waukesha, WI
(414) 797-8400
(206)820-8100
Ontario
Wisconsin
Classic Components
New Berlin, WI
(414) 786-5300
Telecommunications Data Book
Sales Information
Fujitsu Electronic Devices Europe* Sales Offices - Europe
FMG - Benelux
FMG - Germany (Southwest)
FMl- Scandinavia
Fujitsu Mikroelektronik, GmbH
EuropaJaan 26A
5623 LJ Eindhoven
The Netherlands
Tel: (40) 447440
Telex: 59265
FAX: (40) 444158
Fujitsu Mikroelektronik GmbH
Am Joachimsberg 10-12
7033 Herrenberg
Germany
Tel: (7032) 4085
Telex: 7265485
FAX: (7032) 4088
Fujitsu Miaoelectronics Ltd.
Torggatan8
17154 SoIna
Sweden
Tel: (8) 7646365
Telex: 13411
FAX: (8) 280345
FMG-France
FMG - Germany (South)
FMl- United Kingdom
Fujitsu Mikroelektronik GmbH
Immeuble Ie Trident
3-0, voie Fetix Eboue
94024 CreteU Cedex
France
Tel: (1) 45131212
Telex: 262861
FAX: (1) 45131213
Fujitsu Mikroelektronik GmbH
eM-Zeiss-Ring 11
8045lsmaning
Germany
Tel: (89) 9609440
Telex: (17) 897446
FAX: (89) 96094422
Fujitsu Microelectronics Ltd.
Hargrave House
Belmont Road
Maidenhead
Berkshire SL6 6NE
England
Tel: (628) 76100
Telex: 848955
FAX: (628) 781484
FMll-ltaly
FMG - Germany (Central)
Fujitsu Mikroelektronik GmbH
Am Siebenstein 6-10
6072 Dreieich-Buchschlag
Germany
Tel: (6103) 6900
Telex: 411963
FAX: (6103) 690122
Fujitsu Microelectronics ltalia S.R.l.
Centro Direzionale Milanofiori
Strada 4 - Palazzo Al2
20094 Assago (Milano)
Italy
Tel: (2) 82461701176
Telex: 318546
FAX: (2) 8246189
*FujHsu Mikroelektronlk, GmbH (FMG)
Fujitsu Microelectronics, ltd. (FMl)
Fujitsu Microelectronic ltalla S.R.l. (FMll)
11-19
Sales Information
Telecommunications Data Book
FMG, FML and FMIL Distributors Austria
Germany
Spain
Eljapex Handelsges mbH
Wien
Tel: (222) 861531
Telex: 133128
FAX: (222) 861531300
Eljapex GmbH
WaidshUl-liengen
Tel: (n51) 2035
Telex: (n51) 6603
Comella SA
Barcelona
Tel: (3) 300n12
Telex: 51934
FAX: (3) 3005156
MHVIEBV Elektronik
WI8I1
Tel: (222) 838519
Telex: 134946
FAX:(222) 8941n5
Belgium
MHVlEBV Elektronik
Zaventem
Tel: (2) 7209936
Telex: 62590
FAX: (2) 7208152
Denmark
Nordisk Elektronik AS"
Herlev
Tel: (42) 842000
Telex: 35200
FAX: (44)921552
Finland
AspecsOY
Vantea
Tel: (0)5668686
FAX: (0)5666051
France
EBV Elektronik
Champs Sur Mame
Tel: (1) 64686600
Telex: 694301
FAX: (1) 64682767
Elbatex
Bievres Cedex
Tel: (1) 69412BOO
FAX: (1) 69412846
BI
Europe
F2S (Groupe ASAP)
Trappes
Tel: (1) 30438233
Telex: 698887
FAX: (1) 30570719
Microram (Groupe SCAIB)
Rungis Cedex
Tel: (1) 46868170
Telex: 204674
FAX: (1) 45605549
Micro Halbleiter GmbH"
Haar
Tel: (89) 4601004
FAX: (89) 468808
Italy
Hantelec
Milano
Tel: (2) 66010569
FAX: (2) 66013311
Malpassi S.R.L.
Bologna
Tel: (51) 727252
Telex: 583118
FAX: (51) 727515
Ireland
Allied Semiconductors
International Ud.
Shannon
Co. Clare
Tel: (61) 61n7
Telex: 70358
FAX: (61) 363141
The Netherlands
MHVlEBV Elektronik
Maarssenbroek
Tel: (3465) 60791
Telex: 76089
FAX: (3465) 642n
Norway
Odin Electronics AS
Skedsmokorset
Tel: (6) 875480
FAX: (6) 875430
Portugal
Niposom J. Nabais LOA
Usboa
Tel: (1) 894637
Telex: 14028
FAX: (1) 809517
*This Distributor has an ASIC Design Center
**Microcontrollers only
11-20
Comella SA
Madrid
Tel: (1) 7543001
Telex: 42007
FAX: (1) 7542151
Sweden
Martinsson Elektronik AB
Hagersten
Tel: (8) 7440300
Telex:13On
FAX: (8) 7443403
Switzerland
EljapexAG"
Wettingen
Tel: (56) 275m
Telex: 826300
FAX: (56) 261486
United Kingdom
Hawke Component Distribution
Nr. Basingstoke
Hants
Tel: (256) 880800
FAX: (256) 880325
MMD*
Reading
Berkshire
Tel: (734) 752266
Telex: 846112
FAX: (734) 312728
Pronto Electronic Systems Ltd.
llford
Essex
Tel: (81) 5546222
Telex: 8954213
FAX: (15) 183222
Telecommunications Data Book
Sales Information
Fujitsu Microelectronics Asia PTE Limited (FMAP) Sales Offices ASia, Australia and Oceania
Taiwan
Singapore
Hong Kong
Fujitsu Miaoelectronics Pacific Asia Ltd.
Taiwan Branch
Room 1906 No. 333 Keelung Road
Sec.1 Taipei 10548
Taiwan, Republic of China
Tel: (886) 2-7576548
FAX: (866) 2-7576571
Fujitsu Electronics Asia PTE Ltd.
#OlHl4I07 Plaza by the Park
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Singapore 0718
Tel: (65) 336600
FAX: 3361609
Fujitsu Microelectronics Pacific Asia Ltd.
616-617, Tower B
New Mandarin Plaza
14 Science Museum Road
Tsimshatsui East, Kowloon
Hong Kong
Tel: (852) 7230393
FAX: (852) 7216555
m
11-21
Sales Information
Telecommunications Data Book
FMAP Representatives - Asia and Australia
Australia
Korea
Singapore
Pacific Microelectronics PTY Ltd.
Thornleigh.
Australia
Tel: (61) 2-481-0065
FAX: (61) 2-484-4460
KML Corporation
Seoul. Korea
Tel: (82) 2-588--2011
FAX: (82) 2-588--2017
Fujitsu Devices (S) PTE Ltd.
Singapore
Tel: (65) 3361600
FAX: (65) 3361609
FMAP Distributors - Asia
Hong Kong
Taiwan
Singapore
Famint (HK) Ltd.
Causeway Bay. Hong Kong
Tel: (852) 5760130
FAX: (852) 5765619
Famint (Taiwan) Co.• Ltd.
Taipei. Taiwan
Tel. (65) 2962111
FAX: (65) 2960339
Cony Electronics (S) PTE Ltd.
Singapore
Tel: (65) 2962111
FAX: (65) 2960339
Mobicon Electronic Supplies Company
Kowloon. Hong Kong
Tel: (852) 3976628
FAX: (852) 2970339
m
11-22
Section 12
Telecommunication Products
Design Information - At a Glance
I Page nua
12-3
Appfication Note. Prescalers and PLLs: Fujitsu Presea/ers and
Phase-Locked Loops for VHF SlId UHF Frequency Synthesis.
A Tutorial with Selection Guides
.
12-1
Apolicatjon Nores
12-2
Telecommunications Data Book
OJ
liii._gFUJITSU
IMarchI1991• •
Fujitsu Prescalers and Phase-Locked Loops
for VHF and UHF Frequency Synthesis
A Tutorial with Selection Guides
Fujitsu Microelectronics, Inc.
Field Applications Engineering
Abstract
This Application Note includes a broad introduction to the relevant high frequency synthesis theory and its
application areas, a description of prescaler and phase-locked loop (PLL) components, and guidelines for
selecting and designing with Fujitsu's extensive selection of prescaler and PLL Ie products.
12-3
12-4
Contents
Introduction ......................................................................... 13-9
PLL Tuning Systems .................................................................. 13-9
Whatisa PLL? ...................................................................... 13-11
Frequency Synthesis With PLLs and Prescalers .......................................... 13-12
The Pulse Swallow Method ........................................................... 13-13
Stand-alone PLLs and Integrated PLLs ................................................. 13-14
Selecting the Right PLL IC ............................................................ 13-16
Selecting a PLL ...................................................................... 13-17
Width ofthe counters ......................................................... 13-17
Selecting the N and A counters ................................................. 13-18
PLL Counter Selection Guide. .. . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . . . . . . . . . . . .. . . . . .. 13-18
A Practical Example: Selecting the PLL IC for an PM Receiver ............................. 13-18
Example ..................................................................... 13-18
Programming ofthe counters ..................................................
Set-up and switching times of the counters and modulus control logic ...............
Positive or negative edge triggering of counters ..................................
Phase detector ...............................................................
13-19
13-19
13-19
13-20
Charge pump ................................................................ 13-20
Charge pump waveforms and fr and fv . . . . . . . . . . . . . . . .. . . . .. . . . .. . . . . . . . .. . . . ... 13-21
4-bit Microcontrollers with PLLs .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-22
What is a Prescaler? .................................................................. 13-22
Dual modulus prescalers ...................................................... 13-23
Single modulus prescalers ..................................................... 13-23
Microwave Prescalers ......................................................... 13-24
Stand-alone Prescaler Application. . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-24
Selecting the Right Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-25
Toggling speed ....... . . . . . . . . . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . . .. . . . . . . . . . . . . . .. 13-25
Termination resistor internal/ external ..... . . .. . . . . . . . .. . . . .. . . . .. .. . . . . . . . . . . . .. 13-26
Stability of Vout ......................................•.•..................... 13-26
Flexibility of the input voltage .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .. 13-27
ECL level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-27
Flexibility of Vcc .............................................................. 13-27
12-5
Contents
(Continued)
Modulus set-up time .............•............................................
Input impedance and reactance ...................................•.............
Smith chart ..............................................•.•..................
Packaging •.....................•..........•....•..•.....••................•..
Signal propagation delay through the prescaler .....•.......................•.....
Balanced inputs ....................•....................................•.....
Output duty cycles ...•....•........................•..........................
Power dissipation ....•..................................................•.....
Conclusion .....••...................................................................
13-27
13-27
13-27
13-28
13-30
13-30
13-30
13-30
13-31
References .......................................................................... 13-32
Books ..•....•..••••.•••.......•..•...•.••.•...•........•.•••..•••••••.•••••. 13-32
Articles ...................................................................... 13-32
12-6
Illustrations
Figures
1.
Page
A Typical Heterodyne FM Receiver Tuned to the 88.1 MHz Signal .................... 3-10
2.
A Typical Heterodyne (Audio) Sender. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-11
3.
A Basic PLL Configuration ...................................................... 3-11
4.
Frequency Synthesis with a Programmable Counter .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-12
5.
Prescaler Accommodating for a Slow Program Counter ............................. 3-12
6.
PulseSwaIlow ................................................................ 3-13
7.
System Blocks ................................................................. 3-14
8.
Fujitsu's Integrated PLL ICs ..................................................... 3-14
9.
Varactor Diode in a VCO or a VCXO ............................................. 3-15
10.
A Varactor Diode Acting as a Voitage-controlled Variable Capacitance . . . . . . . . . . . . . . .. 3-16
11.
PLL Program Counter Triggered by Opposite Edge ................................ 3-19
12.
PLL Program Counter Triggered by Same Edge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-20
13.
Active Low Pass Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-21
14.
External Charge Pump Example ................................................. 3-21
15.
Frequency Division ............................................................ 3-22
16.
Selection Guide to the Fujitsu Bipolar Prescaler Family ............................. 3-24
17.
A Stand-alone Application of a Prescaler: Clock Rate Reduction ..................... 3-24
18.
Input Signal Amplitude Versus Input Frequency for MB509 Dual Modulus Prescaler ... 3-26
19.
Smith Chart Constant Resistance ................................................ 3-28
20.
Smith Chart Constant Reactance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-28
21.
Input Impedance of Fujitsu's MBSOIL Dual Modulus Prescaler as a Function of
Frequency Shown on a Smith Chart .............................................. 3-29
Tables
Page
1.
Fujitsu's Low Power CMOS PLLs ................................................ 3-16
2.
Fujitsu's Super PLLs ........................................................... 3-17
3.
Fujitsu Prescalers .............................................................. 3-31
12-7
12-8
Fujitsu Microelectronics, Inc.
Prescalers and PLLs
Introduction
Phase-locked loops (PLLs) and prescalers are used for synthesizing and controlling frequencies in a multitude of high frequency systems. These systems range from radio and television broadcasting, cellular
phones, computer local area networks (LANs), and measurement instrumentation to satellite and microwave systems.
Dedicated PLL integrated circuits (lCs) are manufactured in CMOS technology and typically operate in
the 20-30 MHz range (maximum). Prescalers manufactured in bipolar ECL or GaAs technologies are considered interface ICs that allow the relatively slower PLLs to accurately control and select frequencies well
into the microwave range (> 1 GHz).
Fujitsu manufactures a broad range of high frequency telecommunication ICs that includes prescalers,
PLLs, integrated PLLs, as well as microcontrollers with onboard PLL and prescaler circuits.
PLL Tuning Systems
Tuning of telecommunication senders and receivers is, by far, the largest application area for today's PLLs
and prescalers. High frequency PLLs have largely replaced older methods such as direct tuning an RC or
LC oscillator to the desired local oscillator frequency.
At the expense of a quantized (instead of a continuous frequency) resolution, PLLs and the so-called digital tuning circuits into which they are incorporated provide a cheaper, faster, more compact and reliable
solution to tuning circuitry. The fact that PLLs only allow selection of frequencies in discrete steps, rather
than over a continuous range, is not a concern because the available frequencies (for airwaves, long distance telephone cables, satellites, microwave links, ISDN etc.) are heavily regulated and limited to preassigned channel frequencies.
The frequency position and spacing between channels depends on the physical carrier medium and the
program material involved. For example, U.S. airwaves regulations of the Federal Communications Commission (FCC) specify that:
AM radio must be broadcast at 530, 540, 550 to 1610, or 1620 kHz
PM radio must be broadcast at 87.9, 88.1 to 107.7, 107.9 MHz
TV (channels 2-69) must be broadcast at 55.25, 61.25, 67.25, 77.25, 83.25 to 795.25, 801.25 MHz.
These frequencies represent the center frequencies of each channel. The spacing of 10 KHz between assigned AM channels, 200 kHz between assigned FM channels, and 6 MHz between assigned TV channels
reflects the progressively higher bandwidths necessary for PM and TV.
Other regulated frequencies worth mentioning within the VHF (30 - 300 MHz) and UHF (300 MHz - 3
GHz) bands include: 46/49 MHz for cordless telephones, 800-900 MHz for cellular phones (also known as
land mobile radio services), 0.1-1.5 GHz for cable TV and >2 GHz for emerging Digital TV standards and
Integrated Services Digital Network (ISDN). Fuji tsu prescalers and PLL ICs are appropriate for most of
these applications.
Figure 1 shows a superheterodyne FM broadcast receiver and some of the involved spectra and frequencies. For an example, let us examine the steps involved in tuning to the PM station at 88.1 MHz.
12-9
!I:W
~
Prescalers and PLLs
Fujitsu Microelectronics, Inc.
"b, HIM rJA .... J".
87.9
88.1
88.3
107.7
AL"
107.9 MHz
/ AI.. .J" ....JJA HIM "tty
10.5
10.7
10.9
"
MHz
./
'-
•.
98.8 MHz
fc= 10.7 MHz
~
150 kHz
Figure 1. A Typical Heterodyne FM Receiver Tuned to the 88.1 MHz Signal
The antenna is exposed to a multitude of transmission frequencies. In order to retrieve the desired signal,
several stages of amplification and progressive selective filtration must be applied. In PM broadcasting
each radio station is allowed to use up to 150 kHz around the assigned center frequency. Since the spacing
between the assigned channels is 200 kHz, this leaves a 50-kHz wide isolation gap between the stations to
avoid a spectral overlap. Thus, a ISO-kHz wide filter can be used in the final stage to isolate the desired
station from all the others. Accurate tuning of such a narrow filter over the 2O-MHz wide PM frequency
range is not an easy task. To achieve accurate tuning. the filter is kept at a constant frequency, the so-called
Intermediate Frequency (IF), and the desired radio signal is shifted in frequency to falI exactly within the
filter passband. 10.7 MHz is the broadly used value for IF in commercial PM tuners.
The antenna signal is converted to a lower frequency by mixing (or heterodyning) with an appropriately
chosen local oscillator frequency f/oc. A PLL is employed for synthesizing floc. In order to place the desired radio station (originally located at fin) exactly at the center of the IF bandpass filter, the PLL frequency fIoc must be set so that IF =:floc - fin. In other words, to tune to the 88.1 MHz signal, afIoe of 88.1+10.7
MHz =98.8 MHz is necessary. Tuning to another signal is accomplished by selecting a different floc.
An appropriate FM demodulator working at the IF provides the final restoration of the original signal.
On the sender side (see Figure 2) the sequence is reversed: a modulated IF signal is mixed with the local
frequency oscillator up to the appropriate channel-frequency and broadcast.
12-10
Fujitsu Microelectronics, Inc.
Prescalers and PLLs
Modulator
(FM. AM. TV etc.)
Local OsciHator
Figure 2. A Typical Heterodyne (Audio) Sender
Near-ideal PSK, PM, or FM demodulators can be implemented with PLLs as well as local oscillators.
What is a PLL?
A PLL is a control loop consisting of a phase detector (PO), low pass filter (LPF), voltage controlled oscillator (VeO), program counter(s), and, as necessary, single- or dual-modulus prescalers. (See Figure 3.)
t.!o
fref-11--r--(---IH,--- H,---vc_o
LP
---lF
Figure 3. A Basic PLL Configuration
The output of the PO is a voltage indicating the phase difference between its two inputs.
The LPF smooths the PO output and determines the dynamic performance of the loop. The dynamic performance includes general servo loop issues, such as the capture and lock ranges, the noise suppression
bandwidth and the transient response.
When the loop is out of lock, the PO voltage changes the frequency of the veo in a direction that reduces
the phase difference between the input signal and the local oscillator signal. When the loop is locked, the
signals at both inputs are in phase and have the same frequency.
Generally speaking, the output of the veo is considered the desired PLL output. It should be mentioned,
however, that in some instances (such as when a PLL is used as an PM de-modulator), the filtered output
of the PO, rather than the output of the veo, can be viewed as the system output.
The bandwidth of the low-pass loop filter is crucial to the dynamic- and noise-filtering performance of the
loop. The two performance requirements are conflicting, since faster lock-up times require wider LP filters
while better noise characteristics are achieved with narrower filters. Therefore, a reasonable compromise
has to be met for each application.
Narrow filter bandwidths provide long-loop averaging times and are useful in applications where a noiSY,
intermittent, or varying reference source must be cleaned up.
For example, in digital LANs, a PLL is used to regenerate a local clock rate from frame synchronization
bits, which appear intermittently on most asynchronous communications networks.
In a similar way, the "flywheel synchronizers" for vertical and horizontal scan in today's 1V receivers, are
operated using PLL circuits. In both cases the "slow" lowpass filter maintains a relatively constant veo
frequency between occurrences of synchronization patterns on the input.
12-11
Prescalers and PLLs
Fujitsu Microelectronics, Inc.
In frequency synthesis applications, the reference frequency souree will typically be a high quality, rela-
tively noise-free, crystal oscillator. The loop filter can be extensively wide to provide for fast switching
times without compromising noise performance.
A novel approach to PLL design is to electronically bypass the loop filter during the bulk of a frequency
Switching period and then to activate it back into the loop for final lock-in.
As previously mentioned, the loop filter is the single most important factor in determining the dynamic
performance of the servo loop. A thorough theoretical treatment of servo loop analysis is beyond the
scope of this publication. References 1 through 4 listed in the back of this note are recommended for more
in-depth information.
Frequency Synthesis With PLLs and Prescalers
Figure 4 shows a simple frequency-synthesizing configuration employing a PLL and a single program
counter.
fret
fOUl
=N x fret
Figure 4. Frequency Synthesis with a Programmable Counter
When the loop is in lock, the two input frequencies of the PD are equal, hence:
fret = faIN <=> fa = N • fret
A reprogramming of "N" by +1 or -1 will result in selection of a new output frequency with channel separation of fret.
The scheme of Figure 4, although attractive in its simplicity, is only applicable to output frequencies below
40 MHz, since higher veo frequencies will exceed the program counter's toggling rate.
Figure 5 shows a widely used remedy to the high frequency problem: a 11M prescaler is inserted in the
feedback loop as a buffer between the veo and the program counter. This lowers the program counter's
input frequency to foutlM instead of fout.
f=frof R
fret
Prescaler
+M
....._ _ _ _ _"" fOIJl=NoMxfret
R
Figure 5. "rescaler Accommodating for a Slow Program Counter
Figure 5 also shows a reference frequencv divider, 1/R, inserted in the reference frequency path to allow
more flexibility in output frequency programming. Without the reference frequency divider, the presence
12-12
Fujitsu Microelectronics. Inc.
Prescalers and PLLs
of the prescaler would result in broadening the channel separation to M • fret. A resolution of fret is maintained by setting R equal to M.
In many cases, the scheme of Figure 5 is a satisfactory solution, with one drawback. Compared to Figure 4,
the operational frequency of the phase detector is lowered by the prescaling factor M. A lowered PO frequency necessitates use of a narrower low-pass filter to suppress spurious output signals from the phase
detector at the comparison frequency and its harmonics. Especially in very high frequency synthesizers,
where the divide ratio of the prescaler becomes substantial, the loop's lock-in and switching speed characteristics will be severely degraded as a result of narrowing the lowpass filter.
The Pulse Swallow Method
The widely used "multi-modulus division", also known as pulse swallowing (see Figure 6), offers a solution to previously mentioned problems. This method employs two programmable counters and a dual
modulus prescaler inside the loop. (For simplicity the reference frequency divider is not shown.)
f ..
PO
Dual Modulus
Prescaler
11M & It(M+l)
fOlA= IN x M +A) xf..
Swallow Coun1er
ItA
Modulus
Control Logic
Figure 6. Pulse Swallow
A description of the pulse swallow method is as follows:
N must be larger than A (N)A). The dual modulus prescaler is initially set to divide by M+1. After"A"
pulses out of the prescaler, the swallow counter is full and changes the prescaler modulus to M. After additional (N-A) pulses out of the prescaler, the program counter changes the prescaler modulus back to
M+ 1, restarts the swallow counter and the cycle repeats.
In this way each cycle of the liN counter is a result of:
A. (M+V+ (N-A). M=N. M+A
cycles of the fpil'
In other words:
f ... = (N· M +A)· fret
12-13
Presca/ers and PLLs
Fujitsu Microelectronics, Inc.
Since M is multiplied by N, but not A, the frequency will change by fro{ when A is changed by 1. In this
way both the channel separation and the PO frequencies are maintained at fre, to provide for an uncompromised loop performance.
As previously mentioned, more complex variations of the multi-modulus theme include: N/N+Z prescalers (as in MB508 with 128/130,256/258 and 512/514) and quad-modulus schemes involving multiple
swallow counters and special prescalers.
Stand-alone PLLs and Integrated PLLs
Figure 7 shows a general purpose high frequency synthesizer and the functional blocks. These blocks are:
the PO, the reference counter, the A and the N counters and modulus control logiC. The MB87014, manufactured entirely in CMOS, includes an onboard 180 MHz prescaler.
f ..
Dual Modulus
Prescaler
l/M& 1/(M+l)
Figure 7. System Blocks
Advances in recent years in CMOS and BiCMOS (combined ECL and CMOS on one chip) have allowed
integration of gigahertz prescalers on the same chip as the PLL. The architecture of these integrated PLL
BiCMOS devices is illustrated in Figure 8.
Bipolar
prescaler
integrated
on chip
Figure 8. Fujitsu'S Integrated PLL ICs
12-14
Fujitsu Microelectronics, Inc.
Prescalers and PLLs
Before discussing the blocks on the PLL chip, let us briefly mention the circuits not found on it. As stated
earlier, the low-pass filter must yield a good compromise between accommodating the desired noise and
switching characteristics on one side and removing spurious components from the phase detector output
on the other side. A charge pump output (see Figure 14) from the PLL is provided in most cases, allowing
direct connection of an external passive RC filter. The charge pump output is simply a very high impedance output (Zout . 16,OK
6.
12-18
N""", of 593 requires a lO-bit wide N-counter
Fujitsu Microelectronics, Inc.
•
Prescalers and PLLs
A 4-bit wide (swallow) counter
• Either an MB8700IA or an MB87006A
• ChooseMB8700IA
8.
Choose an frefof 3.2 MHz and set the R-counter to 16 to yield IlfcJum",,/ = 0.2 MHz
Programming of the counters
In order to preserve board space, all Fujitsu PLLs have serially programmable counters. The divisor values are fed through a serial pin to a shift register and latched-in with a control pulse. This allows 16-pin
packaging to be used for all devices.
Set-up and switching times of the counters and modulus contro/logic
These delays are important and can become a limiting factor, especially when operating in pulse swallow
mode. When the circuit has counted down so that the N program counter is full, the whole counter system
is reset. The reset function must be completed within the next cycle of the M/M+1 prescaler or,
trese! < M/fou!,max
Where frese! equals the sum of propagation delays through the A and N counters, (the required modulus
set-up time of the prescaler and release time of the modulus control logic).
Positive or negative edge triggering of counters
As previously mentioned, when the modulus of a dual-modulus prescaler is changed from 64 to 65, one
half-cycle of the output (output low) will be extended to 33 input cycles. The other half-cycle will remain
unchanged at 32 input cycles.
Therefore, modulus set-up time of the prescaler will be expressed relative to an edge of the affected halfcycle (in this case the negative-going edge). If the program counters and the modulus control logic are
triggered on an opposite edge, valuable set-up time margin will be lost. (See Figures 11 and 12).
When necessary, insertion of a fast inverter between the prescaler and the program counter may provide
some timing relief.
DIvide by M
Prescaler
output
/
Divide by M+1
\
--.-I
r\
PLL
Modulus
control output
'\ V
/ I\.
Required
modulus set-up time
tpel
~
Margin
Figure 11. PLL Program Counter Triggered by opposne Edge
12-19
Presca/ers and PUs
Fujitsu Microelectronics, Inc.
Divide
byM
Prescaler
oulpUt
Divide
byM+1
\
\
L
1\
'VI
PLL
Modulus
control output
Ii\.
-
Ipd
Margin
Required
modulus
set-uptime
Figure 12. PLL Program Counter Triggered by Same Edge
Phase detector
There are some differences between analog and digital phase detectors.
An analog phase detector works on a so-called integrating multiplier principle (Gilbert Cell multiplier is
one example) and reflects not only timing differences, but also (if the signals are not purely sinusoidal or
square) differences in the shape of the input signals. Analog phase detectors can offer superior signal-tonoise (SIN) ratios and can react almost instantaneously to minute changes in input waveforms. However,
they are relatively complex and lend themselves poorly to high speed CMOS integration.
The digital phase-frequency detector is a simple and extremely fast sequential circuit (4 flip-flops). The
circuit detects only positive-going threshold crossings and indicates which of the two inputs is ahead of
the other one. It is not dependent on the shape of the signals. The digital phase-frequency detector is in all
Fujitsu PLLs.
Charge pump
The single-ended output from the phase detector is called the internal charge pump. The three-state
charge pump output goes high when fret >fflCO, low when fret < fflCO and high-impedance state when
fret = fflCO. This output can be connected directly to an active or passive external filter. The MB87014 provides an inverted charge pump output as well.
The charge pump output is derived from two flip-flops out of the phase detector, oIIr and oIIv. In the case of
MB87006A, MB87014 and the MB870861 when the loop is unlocked, the appropriate output terminal, oIIr or
oIIv, pulls low to indicate which of the two inputs fret or fvco is at a higher frequency.
The signals oIIr and oIIv would normally be considered an intermediate result; however, they are also made
accessible on two output terminals allowing construction of an external charge pump.
A charge pump combines the two digital outputs (oIIr and oIIv) into one output. (See Figure 13.) The external
configuration shown here also directly implements the lowpass filter. Note that due to different polarity
assignments, this configuration is not appropriate for MB87001A, 87073, 87076, and the integrated PLLs.
Also note that often a large resistor is inserted following the op-amp output to increase the output impedance.
12-20
Fujitsu Microelectronics, Inc.
Prescalers and PLLs
PO
ToVCO
Figure 13. Active Low Pass Filter
A fast external charge pump implementation appropriate for the MB87001A, 87073, 87076 PU.s, ICs, and
an integrated PLL is shown in Figure 14. The cjlr and cjlv outputs on these devices are of the open- Iv
Low
I r =I v
I r w
o
o
:>
....
..
:::;
:0
-20
-30
1.0
1.2
1.4
1.6
INPUT FREQUENCY fiN (GHz)
Figure 18. Input Signal Amplitude Versus Input Frequency for MB509 Dual Modulus Prescaler
Prescalers with higher frequency ratings will typically be associated with higher power dissipation and
higher switching noise. For example, measurements of gallium arsenide dividers suggest noise performances 20 to 30 dB worse than for ECL dividers (reference 10).
Also note that the input coupling capacitance of a prescaler will limit the lowest useful frequency.
Termination resistor internal/external
All Fujitsu prescalers, except MB501LV, MB504LV, MBSOlSL, MB509, and MB510 have an open emitter
output. 1YJ>ically a 2.2k n resistor to ground for a load capacitance of 12 pF is recommended. By choosing
a smaller or a larger external resistor, the prescaler's output can be tailored to drive higher or lower loads,
respectively.
The prescalers with on-chip termination can drive output load capacitances of up to 8 pF undistorted. A
shunt resistance can be added for driving larger loads.
In some situations it is desirable to "overdesign" the termination resistor. The limited current driving ability will tend to smooth the output signal, thus reducing its harmonic content and switching noise induced
into supply lines.
Stability of Vout
One of the purposes of prescaling is to eliminate amplitude modulation from the output of the VCO.
Therefore, it is absolutely mandatory that the output high and low are stable and guaranteed over a wide
range of Vin, Vco and temperature.
12-26
Fujitsu Microelectronics, Inc.
Prescalers and PUS
Flexibility of the input voltage
A prescaler should be able to toggle properly with relatively widely varying input voltage levels (anywhere between 0.15 to 2 Vp-p for the Fujitsu MB 5(4), while maintaining a constant output level.
EeL level
For most Fujitsu prescalers the maximum allowable input voltage swing is 2 Vp-p. This means that a typical TIL voltage swing of 3 V will overload the prescaler, whereas EeL voltage levels can be accommodated without problems. The outputs of the prescaler are EeL compatible, too.
The statement "The outputs are 1.6 V peak on EeL level" found on the data sheet for MB501, 503, 504 etc.
means that FUjitsu prescalers do not require negative supply voltages. In this sense they are not "true"
EeL devices.
Flexibility of Vee
A wide operational range ofVcc is essential (2.7 V to 4.5 V, 3.0 V typical for MBSOILV), if a prescaleris to
be used in a battery-powered system. Most Fujitsu prescalers, except the low voltage (LV-suffix) types
which operate from a 3 V supply, operate from a single 5 V supply. The integrated PLLs, MB1S01 and
MB1504, however, operate from a 3 V supply (a higher supply voltage between V 500 MHz), the input impedance should be given on a Smith chart.
The nominal input impedance of Fujitsu's high frequency prescalers is SOO.
Smith chart
Signals on a printed circuit board travel at approximately 2/3 the speed of light. This means that at frequencies above 500 MHz, the signal wavelengths become less than 0.4 m and comparable in size to the
board itself. At this point, circuit board traces start acting as transmission lines; i.e., the RMS voltage level
will vary along the trace unless impedances of the termination and the trace are matched.
A Smith chart is a graphical impedance representation widely used in transmission theory. It is a tool allowing an easy assessment of impedance mismatch.
The chart consists of two sets of circles: the constant resistance circles (see Figure 19) and the constant reactance circles (see Figure 20). The values of these circles are normalized to the characteristic impedance of
the system by dividing the actual value of resistance or reactance by the characteristic impedance, for example, in a 50 0 system, a resistance of 100W is normalized to a value of 2.0.
A further series of circles may be plotted on the chart; these are the circles of constant voltage standing
wave ratio (VSWR) and represent the degree of mismatch in the system. The VSWR is the ratio of the device impedance to the characteristic impedance. It is always expressed as a ratio greater than 1 (a 25 0
device in a 50 0 system gives rise to a 2:1 VSWR). See Figure 21.
12-27
iB
Prssca/ers and PLLs
Fujitsu MictrJetect,."nics, Inc.
Packaging
All Fujitsu prescalers are available in 8-pin DIP or surface mountable 8-pin plastic flat packages. Space
saving and better stray capacitance performance are obtained with surface mounting.
CMOS PLLs and BiCMOS integrated PLLs are available in 16-pin DIP and Flatpacks.
o
Figure 19. Smith Chart Constant
Resistance
12-28
Figure 20. Smith Chart Constant
Reactance
Fujitsu Microelectronics, Inc.
Prescalers and PLLs
IMPEDANCt OR ADMITTANC£ COOROINATES
I
~B!I.
:::
a.8f.
2
!~ 1'~·I"'.nOll_
fi
•t
iii
~~t::a;:p~::;~~;~I!~~.~~~~S:~:'
Note:
500 MHz
RADIALLY SC.t.LfD PARAIII[TfltS
·.tl._ . . 1., ••
I
113
o~t:::;:
: !
of Smith chart graph paper. Copyrighted 1949 by Philip Smith, Analog Instruments, New Providence.
The nominal Zin is 50 Q.
Figure 21. Input Impedance of Fujitsu's MB501L Dual Modulus Prescaler as a Function of
Frequency Shown on a Smith Chan
12-29
Prescalers and PLLs
Fujitsu Microelectronics, Inc.
Signal propagation delay through the prescaler
Although a signal delay through the prescaler will affect the lock-in times of the loop, the prescaler is, in
this respect, of little importance relative to the loop lowpass filter. Extensive phase shifts between the input and the output of the prescaler may, however, affect the PLL stability.
High capacitive loading will typically be the main cause for delays. This situation can be remedied by decreasing the output termination resistor value, thereby improving drive performance.
Self-oscillation problems can be caused by poor grounding, lack of decoupling. or cross-talk due to board
layout. Fujitsu prescalers are guaranteed to be non-oscillatory under most conditions.
Balanced inputs
The ability to drive balanced inputs can be beneficial at high frequencies. All Fujitsu prescalers offer complementary inputs. The prescaler outputs, however, are single ended as they are intended to drive singleended PLL inputs.
Output duty cycles
The output duty cycle should be 50 percent when the modulus is an even number (such as three input
clock periods high and three input clock periods low for division with modulus 6). Division by an odd
number should cause minimal deviation from 50 percent duty cycle (such as four input clocks high and
three input clocks low for division with modulus 7). Rise and fall times are, of course,load dependent and
deviations from idealized waveforms will occur. Also, clearly specify which of the output half-cycles (output low or output high) is the one that is extended in the M +1 mode of a dual modulus prescaler.
Power dissipation
Thanks to a proprietary, "third generation," 0.8 IUII emitter self-align and polysilicon electrode and resistor (ESPER) manufacturing technology, Fujitsu can offer bipolar prescalers with the most beneficial frequency rating/power dissipation ratio available. See Table 3.
1m
12-30
Fujitsu Microelectronics, Inc.
Prescalers and PLLs
Table 3. Fujitsu Prescalers
Icc (TYP)
Supply
Voltage
10120
6mA
5V±10%
8Pin
DIPIFPT
64/65
1281129
30mA
5V± 10%
8Pin
DIPIFPT
10mA
5V±100/o
8 Pin
DIPIFPT
12mA
3V
-10-+50%
8Pin
DIPIFPT
64/65
1281129
SmA
5V± 10%
8 Pin
DiP/FPT
32/33
8mA
5V±100/o
8 Pin
DIPIFPT
10mA
5 V ± 10%
8 Pin
DIPIFPT
32/33
64165
SmA
5V±100/o
8 Pin
DIPIFPT
150 mVp-p
32/33
64/65
6mA
3V
-10-+50%
8 Pin
DIPIFPT
1.6GHz
150 mVp-p
1281129
9mA
5 V ± 10%
8 Pin
DIPIFPT
MB506
2.4GHz
400 mVp-p
18mA
5 V ± 10%
8 Pin
DIPIFPT
MB507
1.6GHz
400 mVp-p
18mA
5 V ± 10%
8 Pin
DIP/FPT
MB508
2.3GHz
400 mVp-p
24mA
5 V ± 10%
8 Pin
DIPIFPT
MB509
1.1 GHz
400 mVp-p
11 mA
5 V ± 10%
8 Pin
DIPIFPT
M8510
2.7GHz
400 mVp-p
10mA
5V±10%
8 Pin
FPT
MB511
1.0GHz
60 mVp-p
23mA
5 V ± 10%
8 Pin
DIPIFPT
PIN
FIN (MAX)
V1N(MIN)
MB467
200 MHz
150 mVp-p
MB501
1.0GHz
400 mVp-p
MB501l
1.1 GHz
400 mVp-p
MB501lV
1.1 GHz
150 mVp-p
M8501Sl
1.1 GHz
loomVp-p
MB503
200 MHz
150mVp-p
MB504
520 MHz
150 mVp-p
MB504l
520 MHz
150 mVp-p
MB504lV
520 MHz
MB505-16
Divide
Ratio
64/65
128/129
64/65
128/129
32/33
64/65
64/128
256
128/129
2561257
1281130
2561258
512/514
64165
1281129
1281144
2561272
112/8
Package
Conclusion
For further technical assistance and product information, including updates, please contact your nearest
Fujitsu Microelectronics Sales Office. You will find a listing of the offices at the back of this paper.
12-31
Prescalers and PLLs
Fujitsu Microelectronics, Inc.
References
Books
1.
Berlin, Howard M. Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis: Howard
W. Sams &. Co. 1978.
2.
Blanchard, Alain. Phllse-Locked Loops: Application to Coherent Receiver Design. New York:
Wiley-Interscience, 1976.
3.
Egan, William F. Frequency Synthesis by PhRse Lock. New York: Wiley-Interscience, 1981.
4.
Gardner, Floyd M. PhRseloc1c Techniques. New York: John Wiley and Sons, 1979.
5.
Kinley, Harold. The PLL Synthesizer Cookbook. Blue Ridge Summit: TAB Books, 1980.
6.
Kroupa, V.F. Frequency Synthesis. New York: Wiley, 1973.
7
Undsay, W. C. and M. K. Simon, eds. Phllse-Loc1ced Loops and Their Application. New York: IEEE
Press, 1978.
8.
Manassewitch, Vadim. Frequency Synthesizers. Theory and Design. New York: Wiley, 1976.
9.
Plessey Semiconductors. Radio Telecoms IC Handbook. Irvine: Plessy Semiconductors, 1987.
10. Rohde, Ulrich L. Digital PLL Frequency Synthesizers Theory and Design. Englewood Giffs: PrenticeHall,1983.
Articles
11. Hillstrom, TIm L. "Design method yields low-noise, wide-range crystal oscillators." EDN (March
1988).
12. Ormond, Thm. "Crystal Oscillators." EDN (October 17, 1985).
12-32
----------------Glossary
G-1
G/oSSSlV
Telecommuajcations Data Book
Telecommunications Data Book
Glossary
CATV
Cable Television.
CBRADIO
Citizen Band Radio. The frequency bands allocated for short-distance personal or
business radio communication. Present USA bands are 26.965 to 17.405 kHz,
72 to 76 MHz, and 462.550 to 467.425 MHz.
CMOS
Complimentary Metal Oxide Semiconductor. A technology that is used for the
manufacturing of low power consumption devices.
CODEC
COder/DECoder.
DTMF
Dual Tone Multifrequency
DIP
Dual In-line Package.
ECl
Emitter Coupled Logic. A technology that is used for the manufacturing of devices that
operate at high frequencies.
Frequency
The number of oscillations or cycles per unit of time.
FPT
Flat Package Technology, usually referred to as Surface Mount Technology (SMT).
FSK
Frequency shift keying. The form of frequency modulation in which the modulating wave
shifts the output frequency between or among pre-determined values, and the output
wave has no phase discontinuity.
GaAs
Gallium Arsinide.
GHz
Gigahertz. A unit of frequency equal to one billion cycles per second.
ISDN
Integrated System Digital Network. A digital network in which all forms of
communications, such as voice, data, and video, are converted to digital code and
manipulated by computers serving as intelligent switching devices.
MHz
Megahertz. A unit of frequency equal to one million cycles per second.
MSK
Minimum shift keying.
Modem
MOdulator/DEModulator. An equipment that connects data terminal equipment to a
communication line.
Modulus
The divide-by ratio of a prescaler counter.
Pll
A device that locks onto a particular frequency. It is typically used in applications that
require the tuning or selecting of communication channels.
Prescaler
A device that divides the frequency of an incoming signal by a factor of N. N is the divideby ratio of the counter and is called the modulus.
PSK
Phase shift keying. The form of phase modulation in which the modulating function shifts
the instantaneous phase of the modulated wave among pre-determined discrete values.
RF
Radio Frequency. A frequency in the electromagnetic spectrum that is useful for radio
transmission. Presently this refers to the limits of 10kHz to 100,000 MHz.
UHF
Ultra High Frequency. This range is 300 MHz to 3 GHz.
VHF
Very High Frequency. This range is 30 MHz to 300 MHz.
Glossary
G-4
T9lm;pmmunjcatiqns Data Bqqk
..
Prescalers
DI
Phase-Locked Loops (PLLs)
l1li
III
Ell
011
D
011
IU
Single-Chip PLLs/Prescalers
Single-Chip VCOs/Prescalers
Piezoelectric Devices
Cordless Telephone Integrated Circuits
Telephone Integrated Circuits
Coders/Decoders (CODECs)
Quality and Reliability
lID]
Ordering Information
lID
Sales Information
1m
Appendix: Design Information
FUJITSU LIMITED
Marunouchi Headquarters
6-1 , Marunouchi 1-chome
Chiyoda-ku , Tokyo 100, Japan
Tel: (03) 216-3211
Telex: 781-22833
FAX (03) 213-7174
For further information , please contact:
Japan
FUJITSU LIMITED
Integrated Circuits and Semiconductor Marketing
Furukawa Sogo Bldg.
6-1 , Marunouchi 2-chome
Chiyoda-ku , Tokyo 100, Japan
Tel: (03) 216-3211
Telex: 781-2224361
FAX: (03) 216-9771
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstrein 6-10
6072 Dreieich-Buchschlay
Germany
Tel: (06103) 690-0
Telex: 441-963
FAX (06103) 691-122
Asia
FUJITSU MICROELECTRONICS ASIA PTE. LTO.
No. 51 Bras Basah Road
Plaza By the Park #06-04/07
Singapore 0718
Tel: (65) 336-1600
Telex: RS 55573 FESPL
FAX (65) 336-1609
North and South America
FUJITSU MICROELECTRONICS, INC.
Integrated Circuits Division
3545 North First Street
San Jose , CA 95134-1804 USA
Tel (408) 922-9000
Telex: 910-338-0190
FAX (408) 432-9044
© 1991 FUJITSU LIMITED and Fujitsu Microelectronics, Inc.
Printed in USA
I C-082 3 6 -4- 92-DB
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