1992_Micron_DRAM_Data_Book 1992 Micron DRAM Data Book

User Manual: 1992_Micron_DRAM_Data_Book

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DYNAMIC RAMS .............................................. . .
WIDE DRAMS ................................................... . .
DRAM MODULES ............................................. _ _
IC DRAM CARDS ............................................. _ _
MULTIPORT DRAMS ........................................ . .
APPLICATION/TECHNICAL NOTES ................ . .
PRODUCT RELIABILITy.................................. . .
PACKAGE INFORMATION ............................... _ _
SALES INFORMATION ..................................... . .

DRAM DATA BOOK

2805 East Columbia Road
Boise, Idaho 83706
Telephone: (208) 368-3900
FAX: (208) 368-4431
Customer Comment Line:
800-932-4992 (USA)
01-208-368-3410 (IntI.)
©1992, Micron Technology, Inc.
Printed in the U.S.A.
Micron Technology, Inc., reserves the right to change products or specifications without notice.

I'IIIC:~ON

ABOUT THE COVER:
Front - Clockwise from left, 1) Micron's 16 Meg DRAM
wafer; 2) More than 4,000 Micron team members give
painstaking attention to every step of the production process; 3) Scanning electron microscope (SEM) photograph
of Micron's DRAM mini-stack process; and 4) Micron's.
Triple Port, Dual Port and 4 Meg DRAMs inSOJ, ZIP and .
TSOP packages.
Back - Micron's Boise, Idaho, corporate headquarters
including three fabrication facilities.

ftJIlC:~CN

1-·

r""'I '"

,

PREFACE
GENERAL INFORMATION

IMPORTANT NOTICE
Micron Technology, Inc., reserves the
right to change products or specifications without notice. Customers are
advised to obtain the latest versions of
product specifications, which should
be considered in evaluating a product's
appropriateness for a particular use.
There is no assurance that Micron's
semiconductors are appropriate for any
application by a customer.
MICRON TECHNOLOGY, INC.,
MAKES NO WARRANTIES EXPRESSED OR IMPLIED OTHER THAN
COMPLIANCE WITH MICRON'S
SPECIFICATION SHEET FOR THE
COMPONENT AT THE TIME OF
DELIVERY. ANY CLAIM AGAINST
MICRON MUST BE MADE· WITHIN
NINETY (90) DAYS FROM THE DATE
OFSHIPMENTFROMMICRON,AND
MICRON HAS NO LIABILITY
THEREAFTER. ANY MICRON LIABILITY IS LIMITED TO REPLACEMENT OF DEFECTIVE ITEMS OR
RETURN OF AMOUNTS PAID FOR
DEFECTIVE ITEMS (AT THE BUYER'S
ELECTION).

PREFACE

REV.A/9.2

'

MICRON'S PRODUCTS ARE NOT
AUTHO~DFORUSEASCRITICAL

COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT
THE EXPRESS WRITTEN APPROVAL
OF THE PRESIDENT OF MICRON
TECHNOLOGY, INC. AS USED
HEREIN:
A. LIFE SUPPORT DEVICES OR
SYSTEMS AR~ DEVICES OR SYSTEMS WHICH (1) ARE INTENDED
FOR SURGICAL IMPLANT INTO THE
BODY, OR (2) SUPPORT OR SUSTAIN
LIFE AND WHOSE FAILURE TO
PERFORM WHEN PROPERLY USED
IN ACCORDANCE WITH INSTRUCTIONS FOR USE PROVIDED IN THE
LABELING CAN BE REASONABLY
EXPECTED TO RESULT IN A
. SIGNIFICANT INJURY TO THE USER.
B. CRITICAL COMPONENT IS ANY

COMPONENT OF A LIFE SUPPORT
DEVICE OR SYSTEM WHOSE
FAILURE TO PERFORM CAN BE
REASONABLY EXPECTED TO CAUSE
THE FAILUREOF THE LIFE SUPPORT
DEVICE OR SYSTEM OR TO AFFECT
ITS SAFETY OR EFFECTIVENESS.

MicI'onTed,'101ogy, m., J8$8f\IM the right In change products or speeificationfl wilhouH'Iotlce.
@1992, Micron Technology, Inc.

PREFACE
GENERAL INFORMATION

I"IICI=ION

PREFACE
REV.41Q2

ii

MIC:RON
1-·

PREFACE
GENERAL INFORMATION

no"""o,,,,,

Dear Customer:
Micron Technology, Inc., is dedicated to the design,
manufacture and marketing of high quality, highly reliable
memory components. Our corporate mission is

"To be a world class team
developing advantages for our customers"
At Micron, we are investing time, talent and resources
to bring you the finest DRAMs, SRAMs, VRAMs and other
specialty memory products. We have developed a unique
intelligent burn-in system, AMBYX which evaluates and
reports the quality level of each and every component we
prodl;lce.
M

,

We are dedicated to continuous improvement of all our
products and services. This means continual reduction of
electrical and mechanical defect levels. It also means the
addition of new services such as "just-in-time" delivery
and electronic data interchange programs. And, when you
have a design or application question, you can get the
answers you need from the source through one of Micron's
applications engineers.
We're proud of our products, our progress and our
performance. And we're pleased that you're choosing
Micron as your memory supplier.

The Micron Team

PREFACE

REV. 4192

iii

Micron Technology, Inc., reserves the right to change products or specifications wilhout notice.

©1992, Micron Technology, Inc.
AMByX .... is a trademark of Micron Technology, Inc.

MIC:RON
1-·

PREFACE
GENERAL INFORMATION

'"''''''0,"'''

ADVANTAGES
certification for both our NMOS and CMOS process
technologies.

Micron Technology brings quality, productivity and
innovation together to provide advantages for our customers. Our products feature some of the industry's
fastest speeds and smallest die sizes. And we establish
delivery standards based on your expectations, including
JIT programs, made possible by ever-increasing product
reliability.

DIE SALES
In addition to our durable packaging, Micron also
provides memory devices in bare die form. These
are increasingly in demand for commercial and military
use in highly specialized applications. Micron's bare die
products are available both in 6" wafers and wafflepacks.

COMPONENT INTEGRATED CIRCUITS
Micron Technology entered the memory market 14
years ago first designing, then manufacturing dynamic
random access memory (DRAM). From there, we developed high-performance fast static RAM (SRAM), multiport
DRAM (VRAM and Triple Port DRAM), and a variety
other memory products.
As we bring progressive memory solutions to our
customers, we enjoy recognition for our achievements.
Micron's Triple Port DRAM was the first IC ever to
incorporate a second, independent serial access port,
allowing unparalleled flexibility in data manipulation. In
1990, Micron's Triple Port received the 1990 "Product of
the Year" award from Electronic Products magazine.

CUSTOM MANUFACTURING SERVICES
For total project management, Micron offers addedvalue services. These include both standard contract
manufacturing services for system-level products including .design, assembly, customer kitted assembly, comprehensive quality testing or shipping as well as complete
turnkey services covering all phases of production. Our
component and system-level manufacturing facilities
are centrally located in Boise, Idaho, so the component
products you need are readily available.

QUALITY
Without a doubt, quality is the most important thing
we provide to every Micron customer with every Micron
shipment. That's because we believe that quality must
be internalized consistently at every level of our company. We provide every Micron team member with the
training and motivation needed to make Micron's quality
philosophy a reality.
One way we have measurably improved both productivity and product quality is through our own quality
improvement program formed by individuals throughout the company. Micron quality teams get together to
address a wide range of issues within their areas. We
consistently and regularly perform a company-wide selfassessment based on the Malcolm Baldrige National
Quality Award criteria. We've also implemented statistical process controls to evaluate every facet of the memory
design, fabrication, assembly and shipping process. And
our AMBYX" intelligent burn-in and test system" gives
Micron a unique edge in product reliability.

SPECIALTY MEMORY PRODUCTS
Beyond our standard component memory, Micron is
introducing many revolutionary products that we expect
will follow the Triple Port's tradition. From FIFOs to
processors, Micron continues to forge ahead into new
and exciting frontiers.
We are pleased to be first to market with our compact,
easy-to-install 88-pin IC DRAM Card. Ideal for laptop,
notebook and other portable systems, Micron's IC DRAM
Card offers both high density and low power within
JEDEC and JEIDA specifications.*

MILITARY CERTIFIED PRODUCTS
As one of the few manufacturers of military-grade
memory in North America, Micron is proud to provide a
documented source inspection from wafer start to finished product. We've earned recognition from U.S. and
European space agencies as well as Joint Army/Navy

*See NOTE, page v.
**For more information on Micron's AMBYXm , see Section 7.
PREFACE
REV. 4/92

iv

Micron Technology, tnc., reserv9slhe right to change products or specifications without notice.
©1992, Micron Technology, Inc.
AMBY)(1'M IS a trademark of Micron TechnolCIQY. Inc.

UIC:I=ION
1-·

PREFACE
GENERAL INFORMATION

","cccem""

ABOUT THIS BOOK
CONTENT
The 1992 DRAM Data Book from Micron Technology
provides complete specifications on all standard DRAMs
and DRAM modules as well as specialty and derivative
products based on our DRAM production process.
The DRAM Data Book is one of three product data books
Micron currently publishes. Its two companion volumes
include our SRAM Data Book and Military Data Book.

DATA SHEET SEQUENCE
Data sheets in this book are ordered first by width and
second by depth. For example, the DRAM section begins
with the 1 Meg x 1 followed by 4 Meg x 1 and all other xl
configurations in order of ascending depth. Next come the
x4 products, followed by x8, etc., as applicable to the
specific product family.
DATA SHEET DESIGNATIONS
As detailed in the table below, each Micron product
data sheet is classified as either Advance, Preliminary or
Final. In addition, new product data sheets that are new
additions are designated with a "New" indicator in the tab
area of the front page.

SECTION ORGANIZATION
Micron's 1992 DRAM Data Book contains a detailed
Table of Contents with sequential and numerical indexes of
products as well as a complete product selection guide. The
Data Book is organized into nine sections:

SURVEY
We have included a removable, postage-paid survey
form in the front of this book. Your time in completing and
returning this survey will enhance our efforts to continually
improve our product literature.
For more information on Micron product Iitcraturl', or to
order additional copies of this publication, contact

• Sections 1-5: Individual product families. Each
contains a product selection guide followed by
data sheets.
• Section 6: Application/technical notes.
• Section 7: Summary of Micron's unique
quality and reliability programs and testing
operation, including our AMBYX=intelligent
burn-in and test system.'
• Section 8: Packaging information.
• Section 9: Product ordering information,
including a list of sales representatives and
distributors worldwide.

Micron Technology, Inc.
2805 East Columbia Road
Boise, ID 83706
Phone: (208) 368-3900
FAX: (208) 368-4431
Customer Comment Line:
800-932-4992 (USA)
01-208-368-3410 (Intl.)

DATA SHEET DESIGNATIONS
DATA SHEET MARKING

DEFINITION

"Advance"

This data sheet contains initial descriptions of products still under development.

"Preliminary"

This data sheet contains initial characterization limits that are subject to change upon full
characterization of production devices.

No Marking (Final)

This data sheet contains minimum and maximum limits specified over the complete power
supply and temperature range for production devices. Although considered final, these
specifications are subject to change, as further product development and data characterization sometimes occur.

"New"

This data sheet (which may be either Advance, Preliminary or Final) is a new addition to
the Data Book.

NOTE: Micron's DRAM Data Book uses acronyms to refer to certain industry-standard-setting bodies. These are defined
below for your reference:
EIAIJEDEC-Electronics Industry Association/Joint Electron Device Enllineering Council.
JEIDA-Japanese Electronics Industry Development Association.
PCMCIA-Personal Computer Memory Card International Association.
'Micron's Quality/Reliability Handbook is available by calling (208) 368-3900.
'"REFACE
~EV.419.2

v

Micron Technology, Inc.. reserves the right to change products or specifications without notice.
©1992, Micron Technology, Inc.
AMBY)(TM is a trademark of Micron Techl'lOlogy, Inc.

MIC:RON

1-·

PREFACE
GENERAL INFORMATION

"'""",0<0"""

WIDE DRAM PRODUCT SELECTION GUIDE
Memory
Configuration

Optional
Access Cycle

Part
Number"

Access
Time (ns)

Typical Power Oissipation
Standby
Active

Package/Number of Pins
ZIP
SOJ
TSOP

512K x 8

FP

MT4C8512

70,80,100

3mW

350mW

28

28

28

2-1

512K x 8

FP, WPB

MT4C8513

70,80,100

3mW

350mW

28

28

28

2-1

512K x 8

FP,LP

MT4C8512 L

70,80,100

1mW

350mW

28

28

28

512K x 8

FP, WPB, LP

MT4C8513 L

70,80,100

1mW

350mW

28

28

28

2-15"
2-15

Page

2Megx8

FP,4KR

MT4(L)C2M8A 1

60,70,80

5mW

400mW

28,32

28,32

2-31

2Megx8

FP,4KR, WPB

MT4(L)C2M8A2

60,70,80

5mW

400mW

28,32

28,32

2-31

2Megx8

FP,2KR

MT4(L)C2M8B1

60,70,80

5mW

400mW

28,32

28,32

2-47

2Megx8

FP, 2KR, WPB

MT4(L)C2M8B2

60,70,80

5mW

400mW

28,32

28,32

2-47

2Megx8

FP, 4KR, S, LP

MT4(L)C2M8A1 S

60,70,80

2mW

400mW

28,32

28,32

2-63

2Megx8

FP, 4KR, WPB, S, LP

MT4(L)C2M8A2 S

60,70,80

2mW

400mW

28,32

28,32

2-63

2Megx8

FP, 2KR, S, LP

MT4(L)C2M8B1 S

60,70,80

2mW

400mW

28,32

28,32

2-81

2Megx8

FP, 2KR, WPB, S, LP

MT4(L)C2M8B2 S

60,70,80

2mW

400mW

-

28,32

28,32

2-81

64K x 16

FP,DW

MT4C1664

70,80,100

3mW

225mW

40

40

40

2-99

64K x 16

FP, WPB

MT4C1665

70,80,100

3mW

225mW

40

40

40

2-99

64K x 16

FP, DW, LP

MT4C1664 L

70,80,100

lmW

225mW

40

40

40

2-115

64K x 16

FP, WPB, LP

MT4C1665 L

70,80,100

1mW

225mW

40

40

40

2-115

64K x 16

SC,DW

MT4C1670

70,80,100

3mW

225mW

40

40

40

2-133

64K x 16

SC, WPB

MT4C1671

70,80,100

3mW

225mW

40

40

40

2-133

64K x 16

SC, OW, LP

MT4C1670 L

70,80,100

1mW

225mW

40

40

40

2-151

64Kx 16

SC, WPB, LP

MT4C1671 L

70,80,100

1mW

225mW

40

40

40

2-151

256K x 16

FP,DW

MT4C16256

70,80,100

3mW

500mW

40

40

40

2-169

256K x 16

FP,DC

MT4C16257

70,80,100

3mW

500mW

40

40

40

2-169

256K x 16

FP, DW, WPB

MT4C16258

70,80,100

3mW

500mW

40

40

40

2-169

256K x 16

FP, DC, WPB

MT4C16259

70,80,100

3mW

500mW

40

40

40

2-169

256K x 16

FP, DW, LP

MT4C16256 L

70,80,100

1mW

500mW

40

40

40

2-191

256K x 16

FP, DC, LP

MT4C16257 L

70,80,100

1mW

500mW

40

40

40

2-191

256K x 16

FP, DW, WPB, LP

MT4C16258 L

70,80,100

1mW

500mW

40

40

40

2-191

256K x 16

FP, DC, WPB, LP

MT4C16259 L

70,80,100

1mW

500mW

40

40

40

2-191

256K x 16

FP,ASY, DW

MT4C16260

70,80,100

1mW

500mW

40

40

40

2-213

256K x 16

FP, WPB, ASY

MT4C16261

70,80,100

1mW

500mW

40

40

40

2-213

1 Meg x 16

FP, DC

MT4(L)C1M16C3

60,70,80

5mW

500mW

42

44

2-229

1 Meg x 16

FP,DW

MT4(L)C1M16C5

60,70,80

5mW

500mW

-

42

44

2-229

1 Meg x 16

FP, DC, WPB

MT4(L)C1M16C6

60,70,80

5mW

500mW

42

44

2-229

1 Meg x 16

FP, DW, WPB

MT4(L)C1 M16C7

60,70,80

5mW

500mW

42

44

2-229

1 Meg x 16

FP, DC,S, LP

MT4(L)C1M16C3 S

60,70,80

2mW

500mW

42

44

2-251

1 Meg x 16

FP, DW,S, LP

MT4(L)C1M16C5 S

60,70,80

2mW

500mW

42

44

2-251

1 Megx16

FP, DC, WPB, S, LP

MT4(L)C1M16C6 S

60,70,80

2mW

500mW

42

44

2-251

1 Meg x 16

FP, DW, WPB, S, LP

MT4(L)C1M16C7 S

60,70,80

2mW

500mW

42

44

2-251

FP = Fast Page Mode, SC = Static Column, LP = Low Power, Extended Refresh; WPB = Write Per Bit, DW
2KR = 2,048 Refresh, 4KR = 4,096 Refresh, S = Self Refresh, ASY = Asymmetrical Addressing
'(L)C means device is available in both 5V Vcc (MT4CXXXXX) and 3/3.3V Vcc (MT4LCXXXXX) versions

PREFACE

REV. 4/92

xxii

-

= Dual WE, DC = Dual CAS,

Micron Technology, Inc•• reserves the right to change products or specificatiOns without notice.
©1992, Micron Technology, Inc.

MICRON
1-·

PREFACE
PRODUCT SELECTION

m"",w" "

DRAM MODULE PRODUCT SELECTION GUIDE
Memory
Configuration

Part
Number

Optional
Access Cycle

Access
Time (ns)

MT2D2568

LP, LV'

60,70,80

1 Megx8

MT2D18

LP, LV'

60,70,80

1 Megx8

MT8D18

LP

60,70,80

4 Meg x8

MT2D48

60,70,80

4 Meg x8

MT8D48

16Megx8

MT8D168

256K x 8

256K x 9
1 Megx9

LP

6mW

Package
SIMM
SIP

350mW

30

6mW

450mW

24mW

1,400mW

10mW

60,70,80

Page

30

3-1

30

30

3-11

30

30

3-21

550mW

30

30

3-31

24mW

1,800mW

30

30

3-41

60,70,80

24mW

2,200mW

30

30

3-51

MT3D2569

LP

60,70,80

9mW

625mW

30

30

3-61

MT3D19

LP

60,70,80

9mW

625mW

30

30

3-71

LP

60,70,80

27mW

1,575mW

30

30

3-81

60,70,80

12mW

775mW

30

30

3-91

60,70,80

27mW

2,025mW

30

30

3-101

60,70,80

27mW

2,475mW

30

30

3-111

1 Megx9

MT9D19

4 Meg x 9

MT3D49

4 Meg x 9

MT9D49

16 Meg x 9

MT9D169

LP

512K x 16

MT8D25632

LP, LV'

60,70,80

24mW

1,400mW

72

3-121

1 Megx16

MT16D51232

LP,LV'

60,70,80

48mW

2,800mW

72

3-133

2Megx16

MT8D132

LP, LV'

60,70,80

24mW

1,800mW

72

3-145

4Megx16

MT16D232

LP, LV'

60,70,80

48mW

1,824mW

72

3-157

BMegx16

MT8D432

60,70,80

40mW

2,200mW

72

3-169

16Megx16

MT16D832

60,70,80

80mW

2,240mW

72

3-179

MT10D25636

60,70,80

30mW

1,750mW

72

3-199

512K x 18
1 Megx18

MT6D118

60,70,80

18mW

1,250mW

72

3-209

1 Megx18

MT20D51236

60,70,80

60mW

1,780mW

72

3-229

2Megx18

MT12D136

LP

60,70,80

36mW

2,500mW

72

3-249

4Megx18

MT24D236

LP

60,70,80

72mW

2,536mW

72

3-271
3-283

8Megx18

MT12D436

60,70,80

52mW

3,100mW

72

16Megx18

MT24D836

60,70,80

104mW

3,152mW

72

3-293

1,400mW

72

3-121

256K x 32

MT8D25632

LP,LV'

60,70,80

24mW

MT16D51232

LP, LV'

60,70,80

48mW

1,424mW

72

3-133

1 Megx32

MT8D132

LP, LV'

60,70,80

24mW

1,800mW

72

3-145

2Megx32

MT16D232

LP, LV'

60,70,80

48mW

1,824mW

72

3-157

4 Meg x 32

MT8D432

60,70,80

40mW

2,200mW

72

3-169

8 Megx32

MT16D832

60,70,80

80mW

2,240mW

72

3-179

256K x 36

MT9D25636

60,70,80

27mW

1,575mW

72

3-189

256K x 36

MT10D25636

60,70,80

30mW

1,750mW

72

3-199

512K x 36

MT18D51236

60,70,80

54mW

1,600mW

72

3-219

512K x 36

MT20D51236

60,70,80

60mW

1,780mW

72

3-229

1 Meg x 36

MT9D136

60,70,80

27mW

2,175mW

72

3-239

60,70,80

36mW

2,500mW

72

3-249

60,70,80

54mW

2,052mW

72

3-261

60,70,80

72mW

2,536mW

72

3-271

512K x 32

1 Meg x 36

MT12D136

2Megx36

MT18D236

LP

2Megx36

MT24D236

4 Meg x36

MT12D436

60,70,80

52mW

3,100mW

72

3-283

8Megx36

MT24D836

60,70,80

104mW

3,152mW

72

3-293

LP

256K x 40

MT10D25640

LP, LV'

60,70,80

30mW

1,750mW

72

3-303

512K x 40

MT20D51240

LP, LV'

60,70,80

60mW

1,780mW

72

3-315

1 Megx40

MT10D140

LP, LV'

60,70,80

30mW

2,250mW

72

3-327

2 Meg x 40

MT20D240

LP, LV'

60,70,80

60mW

2,280mW

72

3-339

=

=

LP Low Power, Extended Refresh; LV Low Voltage
NOTE: All modules include FAST PAGE MODE cycle.

'REFACE
lEV. 4192

Power Dissipation
Standby
Active

'Contact factory regarding availability of low voltage versions.

xxiii

Micron Technology. Inc.. reserves the right to change products or specifications without notice.
©1992, Micron Technology, Inc.

MIC::RON

1-·

PREFACE
PRODUCT SELECTION

, "" ,."

IC DRAM CARD SELECTION GUIDE

Memory
Configuration
512K x 16

1 Megabyte

Part
Number

Access
Time (ns)

Number of Pins
Card

MT8D88C25632

60,70,80

88

4-1

Page

1 Meg x 16

2 Megabytes

MT16D88C51232

60,70,80

88

4-17

2 Meg x 16

4 Megabytes

MT8D88C132

60,70,80

88

4-33

4 Meg x 16

8 Megabytes

MT16D88C232

60,70,80

88

4-49

512Kx18

1 Megabyte

MT12D88C25636

60,70,80

88

4-65

1 Meg x 18

2 Megabytes

MT24D88C51236

60,70,80

88

4-79

2 Meg x 18

4 Megabytes

MT12D88C136

60,70,80

88

4-93

4Megx18

8 Megabytes

MT24D88C236

60,70,80

88

4-107

512K x 20

1 Megabyte

MT12D88C25640

60,70,80

88

4-121

1 Meg x 20

2 Megabytes

MT24D88C51240

60,70,80

88

4-137

2 Meg x20

4 Megabytes

MT12D88C140

60,70,80

88

4-153

4 Meg x20

8 Megabytes

MT24D88C240

60,70,80

88

4-169

256K x 32

1 Megabyte

MT8D88C25632

60,70,80

88

4-1

512K x 32

2 Megabytes

MT16D88C51232

60,70,80

88

4-17

1 Meg x 32

4 Megabytes

MT8D88C132

60,70,80

88

4-33

2 Meg x ,32

8 Megabytes

MT16D88C232

60,70,80

88

4-49

256K x 36

1 Megabyte

MT12D88C25636

60,70,80

88

4-65

512K x 36

2 Megabytes

MT24D88C51236

60,70,80

88

4-79

1 Meg x 36

4 Megabytes

MT12D88C136

60,70,80

88

4-93

2 Meg x 36

8 Megabytes

MT24D88C236

60,70,80

88

4-107

256K x 40

1 Megabyte

MT12D88C25640

60,70,80

88

4-121

512K x 40

2 Megabytes

MT24D88C51240

60,70,80

88

4-137

1 Meg x 40

4 Megabytes .

MT12D88C140

60,70,80

88

4-153

2 Meg x40

8 Megabytes

MT24D88C240

60,70,80

88

4-169

PREFACE
REV. 4192

xxiv

Micron Technology, Inc., reserves the right to change products or specifications without notice
©t992, Micron Technology, Inc

MIC:RON

1-·

PREFACE
PRODUCT SELECTION

we ,"moe"

DUAL PORT DRAM (VRAM) PRODUCT SELECTION GUIDE
Memory

Access

Configuration Cycle

Part

Access

Power Dissipation

Number

Time (ns)

Standby

Active

SOJ

Package and Number of Pins
SOG

TSOP

ZIP

Page

256Kx4

FP

MT42C4255

80, 100

15mW

275mW

28

-

28

5-1

256Kx 4

FP, BW, LP

MT42C4256

70,80,100

15mW

275mW

28

28

5-3

128K x 8

FP

MT42C8127

60, 100

15mW

275mW

40

-

-

FP, BW, LP

MT42C8128

70,80,100

15mW

275mW

40

-

40/44

256Kx 8

FP,BW

MT42C8255

70,80

10mW

300mW

40

-

40/44

256Kx8

FP,BW

MT42C8256

70,80

10mW

300mW

40

-

40/44

256Kx 16

FP,BW

MT42C256K16A1

60,70,80

10mW

350mW

-

64

-

-

5-39

128K x 8

FP

i

5-41
5-79
5-111
5-153

=Fast Page Mode, BW =Block Write, LP =Low Power, Extended Refresh

TRIPLE PORT DRAM PRODUCT SELECTION GUIDE
Memory

Access

Part

Access

Configuration

Cycle

Number

Time (ns)

Standby

Active

SOJ

SOG

FP, BW, QSF pin

MT43C4257

80, 100

15mW

500mW

40

-

40/44

256Kx4

FP, BW, SSF pin

MT43C4258

80, 100

15mW

500mW

40

-

128Kx 8

FP, BW, QSF pin

MT43C8128

80, 100

15mW

550mW

-

-

128K x 8

FP, BW, SSF pin

MT43C8129

80, 100

15mW

550mW

-

256Kx 8

FP,BW

MT43C256K8A 1 60,70,80

f5mW

400mW

-

256Kx4

FP = Fast Page Mode, BW

'AEFACE
lEV. 4/92

Power Oissipation

Package/Number of Pins
TSOP PLCC

Page
5-155

40/44

-

-

52

5-201

-

-

52

5-201

64

-

-

5-247

5-155

=Block Write

xxv

Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1992, Micron Technology, Inc.

MIC:RON
1-·

"'"

PREFACE
PRODUCT SELECTION

"

APPLICATION/TECHNICAL NOTE SELECTION GUIDE
Technical Note
TN-OO-01

PREFACE

REV. 4192

Title

Page

Moisture Absorption in Plastic Packages

6-1

TN-OO-02

Micron Tape and Reel Procedures

6-3

TN-04-01

DRAM Power-Up and Refresh Constraints

6-9

TN-04-02

MT4C1664 and MT4C1665 Compatibilities

6-11

TN-04-03

MT4C1664: 256 Kilobyte Memory System with Four RAS Lines

6-13

TN-04-04

MT4C1664: 256 Kilobyte Memory System with Four CAS Lines

6-15

TN-04-06

DRAM OE Controlled/LATE-WRITE Cycles

6-17

TN-04-08

DRAM Timing Parameters

6-19

TN-04-09

LPDRAM BBU Current vs. RAS Active Time (1 Meg)

6-21

TN-04-12

LPDRAM BBU Current vs. RAS Active Time (4 Meg)

6-23

TN-04-14

Low Voltage (3V) DRAM Design Issues

6-25

TN-43-01

MT43C4257/MT43C4258 Comparison

6-27

TN-88-01

88-Pin IC DRAM Cards

6-29

AN-04-01

Chips & Technologies' 82C456 VGA Controller Using MT4C1664

6-35

xxvi

Micron Technology, Inc., reserves the right to change products or specifications without notice
©1992, Micron Technology. InQ

DYNAMIC RAMS ....................... :..................... .

DRAM PRODUCT SELECTION GUIDE
Memory
Configuration

Optional
Access Cycle

Part
Number

Access
Time (ns)

FP

MT4C1024

60,70,80

1 Meg x 1

FP,LP

MT4C1024 L

70,80,100

1 Meg x 1

SC

MT4C1026

70,80

4 Meg x 1

FP

MT4C1004J

4 Meg x 1

FP,LP

4 Meg x 1

1 Meg x 1

Typical Power Dissipation Package and Number of Pins
Standby
Active
PDlP ZIP SOJ TSOP

Page

3mW

175mW

18

20

20

20

1-1

0.3mW

150mW

18

20

20

20

1-13

3mW

175mW

18

20

20

-

1-25

60,70,80

3mW

225mW

20

20

20

1-37

MT4C1004J L

60,70,80

1mW

225mW

-

20

20

20

1-49

SC

MT4C1006J

70,80

3mW

225mW

20

20

-

1-61

FP,4KR

MT4C16M1A1

60,70,80

3mW

325mW

-

24

24

1-73

16 Meg x 1

FP, 4KR, LV

MT4LC16M1A1

60,70,80

1mW

125mW

-

24

1-73

SC,4KR

MT4C16M1D1

60,70,80

3mW

330mW

-

-

24

16Megx1

24

-

1-85

256Kx4

FP

MT4C4256

60, 70, 80

3mW

175mW

20

20

20

20

1-87

256Kx 4

FP,LP

MT4C4256 L

70,80,100

0.3mW

150mW

20

20

20

20

1-97

256Kx 4

FP,LP,LV

MT4C4256 VL

100,120

0.1mW

100mW

-

20

20

20

1-109

256Kx 4

SC

MT4C4258

70,80,100

3mW

175mW

20

20

20

-

1-121

1 Meg x4

FP

MT4C4001J

60,70,80

3mW

225mW

-

20

20

20

1-133

1 Megx4

FP, LP

MT4C4001J L

60,70,80

1mW

225mW

-

20

20

20

1-145

1 Megx4

SC

MT4C4003J

70,80

3mW

225mW

-

20

20

FP, QCP

MT4C4004J

70,80,100

3mW

225mW

FP,4KR

MT4C4M4A1

60,70,80

3mW

325mW

24

24

1-183

4Megx4

FP,2KR

MT4C4M4B1

60,70,80

3mW

400mW

24

24

1-183

4Megx4

FP, 4KR, LV

MT4LC4M4A1

60,70,80

1mW

125mW

24

24

1-195

4Megx4

FP, 2KR, LV

MT4LC4M4B1

60,70,80

1mW

175mW

24

24

1-195

4 Megx4

SC,4KR

MT4C4M4D1

60,70,80

3mW

325mW

-

24

4Megx4

-

-

1-157

1 Megx4

24

-

1-207

16 Meg x 1

-

FP = Fast Page Mode, SC = Static Column Mode, LP = Low Power, Ex1ended Refresh; QCP = Quad CAS Parity,
LV = Low Voltage, 2KR = 2,048 Row Refresh, 4KR = 4,096 Row Refresh

1-169

DRAM

1 MEG x1 DRAM

I

c

FAST PAGE MODE

::D

»

FEATURES
• Industry standard xl pinout, timing, functions and
packages
• High-performance, CMOS silicon-gate process
• Single +5V ±10% power supply
• Low power, 3mW standby; 175mW active, typical
• All inputs, outputs and clocks are fully TTL
compatible
• 512-cycle refresh in 8ms
• Refresh modes: RAS-ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
• Optional FAST PAGE MODE access cycle

OPTIONS

PIN ASSIGNMENT (Top View)
18-Pin DIP
(N-1 )

MARKING

• Timing
60ns access
70ns access
80ns access
• Packages
Plastic DIP (300 mil)
Plastic ZIP (350 mil)
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)***

1
2

"AS

'-../ 18 ~ Vss
17

ho

0

o

- 7

None
Z
DJ
TG

2

16

CAS

-

4

15

AS'

RAS

AO

5

14

A8

A1

6

13

A7

A2

7

12

A6

Vee 15 ~'.~ 16 A4

NC

,~ 6
7 ~'.~ 8

CAS
Vss

3

WE
TF"

9 ~'.~ 10 NC

AO 11 ~',~ 12 A1
A2 13 ~",~ 14 A3

A3

8

11

AS

A5 17 ~',~ 18 AS

Vee

9

10

A4

A7 19 ~',~ 20 AS

D 1

None
IT

,~

5~'

"TF

20-Pih SOJ
(0-1)

- 8

1S-

3 '::\-:. 4

RAS

-

- 6

NOTE: Available in die fonn (commercial or military) or rt)ilitary ceramic
packages. Please consult factory for die data sheets or refer to Micron's
Military Data Book.

• Operating Temperature, TA
Commercial (O°C to +70°C)
Industrial (-40°C to +85°C)

0
WE

20-Pin ZIP
(0-1 )

WE
RAS
"TF
NC

2
3
4
5

AO
Ai
A2
A3
Vee

10
11
12
13

9

Vss

26
25
24
23
22

CAS
NC
A9'

18
17
16
15
14

A8
A7
A6
AS
A4

0

20.;PinTSOP
(R-1 )

W~~~

26
25
24
23
22

AOa
A1a
A2a
A3a
Vee a

18
17
16
15
14

RASa 3
"TFa 4
NCa 5

9
10
11
12
13

:OVss

:00
:oCAS
:ONC
:oA9'

:0 A8
:oA7
:0 A6
:0 AS
:oA4

'Address not used for RAS"-ONLY refresh
"TF = Test Function, V,N must not exceed Vcc+ 1V for normal operation
"'Consult factory on availability of reverse pinout TSOP packages

GENERAL DESCRIPTION
The MT4C1024 is a randomly accessed solid-state memory containing 1,048,576 bits organized in a xl configuration. During READ or WRITE cycles, each bit is uniquely
addressed through the 20 address bits, which are entered 10
bits (AO -A9) at a time. RAS is used to latch the first 10 bits
and CAS the latter 10 bits. READ and WRITE cycles are
selected with the WE input. A logic HIGH on WE dictates
READ mode while a logic LOW on WE dictates WRITE
mode. During a WRITE cycle, data in (D) is latched by the
falling edge of WE or CAS, whichever occurs last. If WE goes
LOW prior to CAS going LOW, the output pin, data out (Q),
remains open (High-Z) until the next CAS cycle. If WE goes
LOW after data reaches the output pin, Q is activated and
MT4C1024
REV. 4/92

retains the selected cell data as long as CAS remains LOW
(regardless of WE or RAS). This late WE pulse results in a
READ-WRITE cycle.
FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
row address (AO-A9) defined page boundary. The FAST
PAGE MODE cycle is always initiated with a row address
strobed-in by RASfoliowed by a column address strobedin by CAS. CAS may be toggled by holding RAS LOW and
strobing-in different column addresses, thus executing
faster memory cycles. Returning RAS HIGH terminates the
FAST PAGE MODE operation.

1-1

Micron Technology, Inc., reserves the rIght to change products or specifications without notice'.
©1992, Micron Technology, Inc.

s:

I

c

Jl

(READ, WRITE, RAS-ONLY, CAS-BEFORE-RAS (CBR), or
HIDDEN refresh) so that all 512 combinations of RAS addresses (AO-A8) are executed at least every 8ms, regardless
of sequence. The CBR refresh cycle will invoke the internal
refresh counter for automatic RAS addressing.

Returning RAS and CAS HIGH tenninates a memory
cycle and decreases chip current to a reduced 'standby leveL
Also, the chip is preconditioned for the next cycle during the
RAS high time. Memory cell data is retained in its correct
state by maintaining power and executing any RAS cycle

l>

s::

FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE

WE~------------------------~----------~~~

CAS

o

~----------~I

)---r--::::=:--J-~----o

Q

AO
Al

A2
A3
A4

AS
A6
A7

AS
A9

RAS

MEMORY
ARRAY

o------j

--.0

Vee

--.0

Vss

'NOTE: WE LOW prior to CAS LOW, EW detection circuit output is a HIGH (EARLY-WRITE)
CAS LOW prior to WE LOW, EW detection circuit output is a LOW (LATE-WRITE)

MT4C1024

REV.4f92

1-2

Micron Technology, Ino., reserves the right to change products or specifications wifuout notice.
©1992, Micron Technology, hie.

TRUTH TABLE
ADDRESSES
IR
IC

DATA
D (Dala In)

Q(Dala Oul)

HAS"

CAS

WE

Standby

H

H-+X

X

X

X

Don't Care

High-Z

READ

L

L

H

ROW

COL

Don't Care

Data Out

EARLV-WRITE

L

L

L

ROW

COL

Data In

High-Z

FUNCTION

L

L

H-+L

ROW

COL

Data In

Data Out

FAST-PAGE-MODE

1st Cycle

L

H-+L

H

ROW

COL

Don't Care

Data Out

READ

2nd Cycle

L

H-+L

H

n/a

COL

Don't Care

Data Out

FAST-PAGE-MODE

1st Cycle

L

H-+L

L

ROW

COL

Data In

High-Z

EARLV-WRITE

2nd Cycle

L

H-+L

L

n/a

COL

Data In

High-Z

FAST-PAGE-MODE

1st Cycle

L

H-+L

H-+L

ROW

COL

Data In

Data Out

READ-WRITE

2nd Cycle

L

H-+L

H-+L

n/a

COL

Data In

Data Out

L

H

X

ROW

n/a

Don't Care

High-Z

H

ROW

COL

Don't Care

Data Out

READ-WRITE

RAS-ONLV REFRESH
HIDDEN

READ

L-+H-+L

L

REFRESH

WRITE

L-+H-+L

L

L

ROW

COL

Data In

High-Z

H-+L

L

X

X

X

Don't Care

High-Z

CAS-BEFORE-RAS REFRESH

MT4C1024
REV. 4192

1-3

Micron Technology, Inc., reserves the right to change products or specifications wiltlout notice.
©1992, Micron Technology, Inc.

II
c
:D

»
s:

MICRON
1-·

1 MEG

m,"oco",,,

II ABSOLUTE MAXIMUM RATINGS*
c
::D
l>

s:

MT4C1024
x 1 DRAM

'Stresses greater than those listed under" Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

Voltage on Any Pin Relative to Vss .................... -lV to +7V
Operating Temperature, TA (Ambient) ......... O°C to +70°C
Storage Temperature (Plastic) .................•.. -SsoC to + IS0°C
Power Dissipation ...................................................... 600mW
Soldering Temperature (Soldering 10 Seconds) ........ 260°C
Short Circuit Output Current ...................................... SOmA

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 4, 6, 7) (Vcc = 5V ±1 0%)
SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

Vcc

4.5

5.5

V

1

Input High (Logic 1) Voltage, All Inputs

VIH

2.4

Vcc+1

V

1

Input Low (Logic 0) Voltage, All Inputs

VIL

-1.0

0.8

V

1

II

-2

2

ItA

102

-10

10

ItA

VOH

2.4

PARAMETER/CONDITION

INPUT LEAKAGE CURRENT
Any Input OV S; VIN S; 6.5V
(All other pins not under test = OV)
OUTPUT LEAKAGE CURRENT (0 is disabled, OV s; VOUT s; 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT = -5mA)
Output Low Voltage (lOUT = 4.2mA)

V
0.4

VOL

V

MAX
SYMBOL

-6

-7

-8

UNITS

STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)

Icct

2

2

2

mA

STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)

Icc2

1

1

1

mA

OPERATING CURRENT: Random READ/WRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC (MIN))

Icc3

90

80

70

mA

3,4

OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL; CAS, Address Cycling: tpc = tpc (MIN))

Icc4

70

60

50

mA

3,4

REFRESH CURRENT: RAS-ONLY
Average power supply current
(RAS Cycling; CAS = VIH: tRC = tRC (MIN))

Icc5

90

80

70

mA

3

REFRESH CURRENT: CAS-BEFORE-RAS
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC (MIN))

Icc6

90

80

70

mA

3,5

PARAMETER/CONDITION

MT4Cl024
REV. 4/92

1-4

NOTES

Micron Technology, Inc., reserves the right to change products or speCifications without notice.
©1992, Micron Technology, Inc.

MIC:RON

1-·

MT4C1024
1 MEG x 1 DRAM

",",oeoc""

CAPACITANCE
PARAMETER

SYMBOL

Input Capacitance: AO-A9, D
Input Capacitance: RAS, CAS, WE
Output Capacitance: Q

MIN

MAX

CI1
CI2

5
7

Co

7

UNITS
pF

NOTES

pF

2
2

pF

2

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9,10,11,12,13) (Vcc = 5.0V ± 10%)
AC CHARACTERISTICS
PARAMETER
Random READ or WRITE cycle time
READ-WRITE .cycle time
FAST-PAGE-MODE READ
or WRITE cycle time
FAST-PAGE-MODE READ-WRITE
cycle time

REV. 4/92

MIN

-8
MIN

110
135
40

130
155
40

150
175
45

tpRWC

60

65

70

60
60
20
40
20
60
10
10
20
5
0
10
15

MAX

MAX

MIN

tRAC
Access time from liAS
tCAC
Access time from CAS
tAA
Access time from column address
tCPA
Access time from CAS" precharge
tRAS
RAS pulse width
tRASP
RAS pulse width (FAST PAGE MODE)
tRSH
RAS hold time
tRP
RAS precharge time
tCAS
CAS pulse width
tCSH
CAS" hold time
tCPN
CAS precharge time
CAS" precharge time (FAST PAGE MODE) tcp
tRCD
RAS to CAS delay time
tCRP
CAS to liAS precharge time
tASR
Row address setup time
tRAH
Row address hold time
tRAD
RAS to column
address delay time
tASC
Column address setup time
tCAH
Column address hold time
tAR
Column address hold time
(referenced to RAS)
tRAl
Column address to
RAS lead time
tRCS
Read command setup time
tRCH
Read command hold time
(referenced to CAS")
tRRH
Read command hold time
(referenced to RAS)
tClZ
CAS to output in low-Z
tOFF
Output buffer turn-off delay
twcs
WE command setup time
MT4C1024

-7

-6
SYM
tRC
tRWC
tpc

60
20
30
35
100,000
100,000

70
70
20
50
20
70
10
10
20
5
0
10
15

100,000

40

30

70
20 ,
35
40
100,000
100,000

100,000

50

35

80
80
20
60
20
80
10
10
20
5
0
10
15

MAX

UNITS
ns
ns
ns

NOTES

ns
,

80
20
40
45
100,000
100,000

100,000

60

40

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

14
15

16
17

18

0
15
45

0
15
55

0
15
60

ns
ns
ns

30

35

40

ns

0
0

0
0

ns
ns

19

0

0

ns

19

ns
ns
ns

20
21

0
0

..

0
0
0
0

20

1-5

0
0
0

20

0
0
0

20

Micron Technology, Inc., reserves'the right to change products or specifications without notice.
©1992, Micron Technology, Inc.

I
c

::IJ

»

s:

AJlIC:F=lON

1-·

I
:J

XI
I>

s:

MT4C1024
1 MEG x 1 DRAM

,," "

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = 5V ±1 0%)

AC .CHARACTERISTICS
PARAMETER
Write command hold time
Write command hold time
(referenced to 1!iAS")
Write command pulse width
Write command to RAS" lead time
Write command to CAS" lead time
Data-in setup time
Data-in hold time
Data-in hold time
(referenced to 1!iAS")
RAS" to WE delay time
Column address
to WE delay time
CAS" to WE delay time
Transition time (rise or fall)
Refresh period (512 cycles)
RAS to "CAS precharge time
CAS setup time
(CAS-BEFORE-RAS" refresh)
"CAS hold time
(CAS-BEFORE-RAS refresh)

MT4C1024

REV. 4192

-7

-6
MAX

MIN

10
45

15
55

15
60

UNITS
ns
ns

twp
tRWL
tCWL
tDS
tDH
tDHR

10
20
20
0
15
45

15
20
20
0
15
55

15
20
20
0
15
60

ns
ns
ns
ns
ns
ns

tRWD
tAWD

60
30

70
35

80
40

ns
ns

21
21

tCWD
ty

15
3

21
9,10

tREF
tRPC
tCSR

0
10

0
10

0
10

ns
ns
ms
ns
ns

tCHR

10

15

15

ns

5

50
8

1-6

MIN

-8

SYM
tWCH
tWCR

20
3

MAX

50
8

MIN

20
3

MAX

50
8

NOTES

22
22

5

Micron Technology, Inc., reserves the right to change products or speclflcations without notice.
©1992, Micron TechnolOQY, Inc.

NOTES
1.
2.
3.
4.

All voltages referenced to Vss.
This parameter is sampled.Vee = SV ±10%,f = 1 MHz.
Icc is dependent on cycle rates.
Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOl1s is required after power-up
followed by any eight RAS cycles before proper
device operation is assured. The eight RAS cycle
wake-up should be repeated any time the tREF
refresh requirement is exceeded.
8. AC characteristics assume tT = Sns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to 2 TTL gates and
100pF.
14. Assumes that tRCD < IRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, !RAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ;:: IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a

MT4C1024

AEV,4192

new cycle and clear the data out buffer, CAS must be
pulsed HIGH for tCPN.
17. Operation within the tRCD (MAX) limit ensures that
tRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by tCAe.
18. Operation within the tRAD (MAX) limit ensures that
!RAC (MIN) and tCAC (MIN) can be met. tRAD
(MAX) is specified as a reference point only; if tRAD
is greater than the specified !RAD (MAX) limit, then
access time is controlled exclusively by tAA.
19. Either tRCH or tRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL.
21. twcs, tRWD, tAWD and tCWD are restrictive
operating parameters. If twcs ;:: twcs (MIN), the
cycle is an EARLY-WRITE cycle and the data output
will remain an open circuit throughout the entire
cycle. If IRWD ;:: tRWD (MIN), tAWD ;:: tAWD (MIN)
and tCWD ;:: tCWD (MIN), the cycle is a READWRITE and the data output will contain data read
from the selected cell. If neither of the above
conditions is met, the cycle is a LATE-WRITE and the
state of Q is indeterminate (at access time and until
cAs goes back to VIH).
22. These parameters are referenced to CAS-leading edge
in EARLY-WRITE cycles and WE leading edge in
LATE-WRITE or READ-MODIFY-WRITE cycles.
23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.

1-7

Micron Technology, Inc., reserves the right to change products or spectflcations wlthout notice
©1992, Micron Technology, Inc.

II
c
::rJ

l>

s:

II

READ CYCLE

c

lAC
lAP

tRAS

::D

»
s:

.
-

ICRP

:~

tRCD

I

IAR

tRAL

~

ROW

ADDR

tRRH

tCAS

IRAD

:W/l{I~~~

\

.

tCSH
IRSH

~

W///////////////////////,X

COLUMN

~

ROW

~

tRCS

VlIIIIIIIIIIIIIIIIIII/;

:'i'111111111111111111111111111111/
IAA

tRAG
'CAG

10FF

~l

a ~g~-

~I
OPEN---

VAllO DATA

OPEN

EARLY-WRITE CYCLE

RC
IRAS

RAS

VIH
VIL

IRP

-

I

\
tCSH

IRSH
tCRP

CAS

VIH
VIL

IRCD

I
=~

tCAS

IAR
IRAL

IRAQ

I~
ADDR

VIH
VIL

~

ROW

IRAH

~~

~

~h(

COLUMN

ROW

II

tCWL
'RWL

tWCR

Iwes

tWCH
IWp

If/////////////

J//////////////
tOHR

~I
~:~ ~~~~V-AL-ID-D-AT-A~-~
!

I

I~

D

a ~gr='-----~~~~~~~~~~~~~~-OPEN~~~~~~~~~~~~~~~-

MT4C1024

REV. 4192

1-8

~

DON'T CARE

~

UNDEFINED

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1992, Micron Technology, Inc.

II
c

READ-WRITE CYCLE
(LATE-WRITE and READ-MODIFY-WRITE CYCLES)

JJ

»
s:

tCSH

tCAS

J·~;-CL-Z---"'''''-<~I
Q

~gr = ' - - - - - - - - - - OPEN-------{I£~9t==~V~AL~ID~D~AT~A===:J

OPEN--

FAST-PAGE-MODE READ CYCLE

RAS

V,H
Vil

CAS

V,H
Vil

j~ ,tcRP

=~

t:ZJ DON'T CARE
~
1IT4C1024
tEV.4/92

1-9

UNDEFINED

Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1992, Micron Technology, Inc.

II
c

FAST-PAGE-MODE EARLY-WRITE CYCLE

:rJ

RAs

VIH -

VIL _

l>

s::

CAs

ADDR

V,H
Vil

WE

V,H
Vil

0

V,H
Vil

Q

V1H ~----------------·----------------QPEN---------------------------------Vil

FAST-PAGE-MODE READ-WRITE CYCLE
(LATE-WRITE and READ-MODIFY-WRITE CYCLES)

Q

~gr ----------OPEN----------C@~~~f___----~l0(Jl~}_~--~~(]ID

'lpC is for LATE-WRITE only.
MT4C1024
REV. 4192

1-10

OPEN--

~

DON"TCARE

~

UNDEFINED

Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1992, Micron Technology, Inc.

I
c

"RAS-ONL Y REFRESH CYCLE
(ADDR = AO-A8; A9 and WE = DON'T CARE)

::rJ

l>

3:

Q

~gr : : - - - - - - - - - - - - O P E N - - - - - - - - - - -

~-BEFORE-"RAS REFRESH CYCLE

(AO-A9 and WE = DON'T CARE)
tRP

-1~
ICPN

Q

~gr

tRAS

RP

RAS

~.
~

tAPe

tCHR

\l

!cSR

I"CHR

-'--------------OPEN-----------

HIDDEN REFRESH CYCLE 23
(WE = HIGH)
(REFRESH)

(READ)

Q

~g~-'-----

~

DON'T CARE

Il8l l1 UNDEFINED
MT4C1024

REV. 4192

1-11

Micron Technology, Inc., reserves the rlght to change products or specifications without notice.
©1992, Micron Technology, Inc.

I

c

lJ

J>

s::

MT4Cl024
REV. 4192

1-12

Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1992, Micron Technology, tnc.

1 MEG x1 DRAM

DRAM

LOW POWER,
EXTENDED REFRESH

::D
l>

FEATURES
PIN ASSIGNMENT (Top View)

• Industry standard xl pinout, timing, functions and
packages
• High-performance, CMOS silicon-gate process
• Single +5V ±10% power supply
• Low power, .3mW standby; 150mW active, typical
• All inputs, outputs and clocks are fully TTL
compatible
• Optional FAST PAGE MODE access cycle
• Refresh modes: RAS-ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN and BATTERY BACKUP (BBU)
• 512-cycle extended refresh in 64rns
• Low CMOS STANDBY CURRENT, 20011A maximum

OPTIONS

18-Pin DIP
(N-1 )

• Packages
Plastic DIP (300 mil)
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)***
Plastic ZIP (350 mil)

- 8
-10

'J

18

Vss

17

Q

'A9
Q

o

1 eo;-

3

'0

2

CAS

-::'1

5~'

'°4

Vss

3

16

CAS

-

"TF

4

15

A9'

RAS

AO

5

14

AB

A1

6

13

A7

A2

7

12

A6

Vee 15 ~,,~ 16 A4

A3

8

11

AS

AS 17 ~'.o 18 A6

Vee

g

10

A4

A7 19

NC

,~

6

7 ~'.o 8

WE
TF"

9 ~,,~ 10 NC

AO 11

0'.0

12 A1

A2 13 ~,,~ 14 A3

20-Pin SOJ
(0-1 )

None
OJ
TG
Z

~ 20 AS

D
WE
RAS
"TF
NC

1
2
3
4
5

26
25
24
23
22

AO
A1
A2
A3
Vee

9
10
11
12
13

18

20-Pin TSOP
(R-1)

Vss
Q

CAS
NC
A9'

Da
WEEr
RASa
"TFCI
NCa

1
2 '
3
4
5

26
25
24
23
22

TI Vss
TIQ'
TI CAS
TINC
:0 A9'

AOa
A1 CI
A2a
A3CI
Veea

9
10
11
12
13

18 :oAB
17 TIA7
16 :0 A6
15TIAS
14 TI A4

"-

None
IT

• Part Number Example: MT4C1024DJ-7 L

17
16
15
14

A8
A7
A6
AS
A4

'Address not used for RAS-ONL Y refresh
"TF = Test Function. VIN must not exceed Vcc+1V for normal operation
'''Consult factory on availability of reverse pinout TSOP packages

GENERAL DESCRIPTION
The MT4C1024 L is a randomly accessed solid-state
memory containing 1,048,576 bits organized ina xl configuration. During READ or WRITE cycles, each bit is uniquely
addressed through the 20 address bits, which are entered 10
bits (AO-A9) at a time. RASis used to latch the first 10 bits
and CAS the latter 10 bits. READ and WRITE cycles are
selected with the WE input. A logic HIGH on WE dictates
READ mode while a logic LOW on WE dictates WRITE
mode. During a WRITE cycle, data in (D) is latched by the
falling edge of WE or CAS, whichever occurs last. If WE goes
LOW prior to CAS going LOW, the output pin, data out (Q),
remains open (High-Z) until the next CAS cycle. If WE goes
LOW after data reaches the output pin, Q is activated and
MT4C1024 L
REV. 4192

2

20-Pin ZIP
(0-1)

- 7

NOTE: Available in die form (commercial or military) or military ceramic
packages. Please consult factory for die data sheets or refer to Micron's
Military Data Book.

• Operating Temperature, TA
Commercial (O°C to +70°C)
Industrial (-40°C to +85°C)

1

RAS

MARKING

• Timing
70ns access
BOns access
lOOns access

D
WE

retains the selected cell data as long as CAS remains LOW
(regardless of WE or RAS). This late WE pulse results in a
READ-WRITE cycle.
FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
row address (AO-A9) defined page boundary. The FAST
PAGE MODE cycle is always initiated with a row address
strobed-in by RASfoliowed by a column address strobedin by CAS. CAS may be toggled by holding RAS LOW and
strobing-in different column addresses, thus executing faster
memory cycles. Returning RAS HIGH terminates the FAST
PAGE MODE operation.

1-13

II
c

Micron Technology, Ino., reserves the right to change products or specifications without notice.
©1992, Micron Technology, Inc.

s:

I
c
:a
»
s:

Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during the
RAS high time. Memory cell data is retained in its correct
state by maintaining power and executing any RAS cycle

(READ, WRITE, RAS-ONLY, CAS-BEFORE-RAS (CBR), or
HIDDEN refresh) so that all 512 combinations of RAS addresses (AO-A8) are executed at least every 64ms, regardless
of sequence. The CBR refresh cycle will invoke the internal
refresh counter for automatic RAS addressing.

FUNCTIONAL BLOCK DIAGRAM
LOW POWER, FAST PAGE MODE

WE~------------------~--------~~~r-

________·I~;';;-~----~

D

CAS~--~--------------------+-----~----~~~

Q

AO
A1
A2
A3

A4
A5

AS
A7

AS
A9

MEMORY
ARRAY

RAS 0----1

---.0

Vee

---.0

Vss

-NOTE: WE LOW prior to CAS LOW, EW detection circuit output is a HIGH (EARLV-WRITE)
CAS LOW prior to WE LOW, EW detection circuit output is a LOW (LATE-WRITE)

MT4Cl024I.
REV,4192

1-14

Micron Technology, Inc., reserves th$ right to change products or specifications without notice.
©1992, Micron Technology,

1m::.

MIC:RON

1-·

MT4C1024 L
1 MEG x 1 DRAM

"",owo"

I

TRUTH TABLE
ADDRESSES
IR
IC

DATA
D (Data In)

Q (Data Out)

X

X

Don't Care

High-Z

1m"

ns

WE

Standby

H

H--'-X

X

READ

L

L

H

ROW

COL

Don't Care

Data Out

EARLV-WRITE

L

L

L

ROW

COL

Data In

High-Z

READ-WRITE

L

L

H-+L

ROW

COL

Data In

Data Out

FUNCTIDN

FAST-PAGE-MODE

1st Cycle

L

H-+L

H

ROW

COL

Don't Care

Data Out

READ

2nd Cycle

L

H""'L

H

n/a

COL

Don't Care

Data Out

FAST-PAGE-MODE

1st Cycle

L

H-+L

L

ROW

COL

Data In

High-Z

EARLV-WRITE

2nd Cycle

L

H-+L

L

n/a

COL

Data In

High-Z

FAST-PAGE-MODE

1st Cycle

L

H-+L

H-+L

ROW

COL

Data In

Data Out

READ,WRITE

2nd Cycle

L

H-+L

H-+L

n/a

COL

Data In

Data Out

L

H

X

ROW

n/a

Don't Care

High-Z

H

ROW

COL

Don't Care

Data Out

RAS-ONLV REFRESH
HIDDEN

READ

L-+H-+L

L

REFRESH

WRITE

L-+H-+L

L

L

ROW

COL

Data In

High-Z

CAS-BEFORE-RAS REFRESH

H-+L

L

X

X

X

Don't Care

HighcZ

BATTERV BACKUP REFRESH

H-+L

L

X

X

X

Don't Care

High-Z

MT401Q24 L

REV. 4192

1-15

Micron Technology, Inc., reserves the light to change products or specifications without notice.

©1992, Micron Technology, Inc.

c

::D

»

s:

MIC:RON'

, 1-·

I

c

::D

»
s:

MT4C1024 L
1 MEG x 1 DRAM

'''''"'co"''"'

*Stresses greater than those listed under" Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Vss .................... -IV to +7V
Operating Temperature, TA (Ambient) ......... DoC to +70°C
Storage Temperature (Plastic) .................... -SSoC to +IS0°C
Power Dissipation ...................................................... 600mW
Soldering Temperature (Soldering 10 Seconds) ........ 260°C
Short Circuit Output Current ...................................... SOmA

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 4, 6, 7) (Vcc = 5V ±1 0%)

PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, All Inputs
Input Low (Logic 0) Voltage, All Inputs
INPUT LEAKAGE CURRENT
Any Input OV :::; VIN :::; 6.5V
(All other pins not under test = OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV :::; VOUT:::; 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT = -5mA)
Output Low Voltage (lOUT = 4.2mA)

PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS = CAS = VI H)
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Single Address Cycling: IRC = IRC (MIN))
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL; CAS, Address Cycling: IpC = IpC (MIN))
REFRESH CURRENT: RAS-ONLY
Average power supply current
(RAS Cycling; CAS = VIH: IRC = IRC (MIN))
REFRESH CURRENT: CAS-BEFORE-RAS (CBR)
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC (MIN))
REFRESH CURRENT: BATTERY BACKUP (BBU)
Average power supply current during BATTERY BACKUP refresh:
CAS = 0.2V or CAS-BEFORE-RAS cycling; RAS = IRAS (MIN) to
111S; WE, ,AO-A9 and DIN = Vcc -0.2V or 0.2V (DIN may be left
OPEN), IRC = 125J.ls (512 rows at 125J.ls = 64ms)
MT4CI024l
REV. 4192

1-16

SYMBOL
Vcc
VIH
VIL

MIN
4.5
2.4
-1.0

MAX
5.5
Vcc+1
0.8

UNITS
V
V
V

II

-2

2

J.tA

loz

-10

10

J.tA

VOH

2.4

NOTES
1
1
1

V

VOL

0.4

V

2

MAX
-10
-8
2
2

UNITS
mA

Icc2

200

200 200

J.tA

ICC3

75

65

60

mA

3,4

Icc4

55

45

40

mA

3,4

Iccs

75

65

60

mA

3

Icc6

75

65

60

mA

3,5

Icc?

200

200 200

J.tA

3,5,
7, 24

SYMBOL
ICCl

-7

NOTES

Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1992, Micron Technology, Inc.

MIC:RON

1-·

MT4C1024 L
1 MEG x 1 DRAM

"'""OW"""

CAPACITANCE
MAX

UNITS

NOTES

Input Capacitance: AO-A9, D

Cll

5

pF

2

Input Capacitance: RAS, CAS, WE

CI2

7

pF

2

Output Capacitance: Q

Co

7

pF

2

PARAMETER

MIN

SYMBOL

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vcc = 5V ±1 0%)
AC CHARACTERISTICS
PARAMETER
Random READ or WRITE cycle time
READ-WRITE cycle time
FAST-PAGE-MODE READ
or WRITE cycle time

-7

-8

MIN

130
155
40

150
175
45

180
205
55

UNITS
ns
ns
ns

FAST-PAGE-MODE READ-WRITE
cycle time

'PRWC

65

70

85

ns

Access time from RAS
Access time from CAS
Access time from column address
Access time from CAS precharge
RAS pulse width
RAS pulse width (FAST PAGE MODE)
RAS hold time
RAS precharge time
CAS pulse width
CAS hold time
CAS precharge time
CAS precharge time (FAST PAGE MODE)
RAS to CAS delay time
CAS to RAS precharge time
Row address setup time
Row address hold time
RAS to columnaddress delay time

'RAC
'CAC
'AA
'CPA
'RAS
'RASP
'RSH
'RP
'CAS
'CSH
'CPN
'CP
'RCD
'CRP
'ASR
'RAH
'RAD

Column address setup time
Column address hold time
Column address hold time
(referenced to RAS)

ASC
ICAH

70
70
20
50
20
70
10
10
20
5
0
10
15

MAX

70
20
35
40
100,000
100,000

100,000

50

35

MIN

-10

SYM
'RC
'RWC
'PC

80
80
20
60
20
80
10
10
20
5
0
10
15

MAX

80
20
40
45
100,000
100,000

100,000

60

40

MIN

100
100
25
70
25
100
15
10
25
5
0
15
20

MAX

100
25
50
50
100,000
100,000

100,000

75

50

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

NOTES

14
15

16
17

18

'AR

0
15
55

0
15
60

0
20
70

ns
ns
ns

Column address to
RAS lead time

'RAL

35

40

50

ns

Read command setup time
Read command hold time
(referenced to CAS)

'RCS
'RCH

0
0

0
0

0
0

ns
ns

19

Read command hold time
(referenced to RAS)

'RRH

0

0

0

ns

19

CAS to output in low-l
Output buffer turn-oil delay
WE command setup time

'Cll
tOFF

0
0

'wcs

a

ns
ns
ns

20
21

MT4C1024L
REV, 41$2

20

1-17

0
0
0

20

0
0
0

20

Micron Technology> Inc, reserves the right to change products or specifications wilhout notice.

©1992, Micron Technology, Inc.

II
c

:::D

»
==

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9,10,11,12,13) (Vee = 5V ±10%)

AC CHARACTERISTICS
PARAMETER

-7

-8

MIN

Write command hold time

twCH

15

15

20

ns

Write command hold time
(referenced to RAS)

twCR

55

60

75

ns

twp
tRWL
tCWL
tDS
tDH
tDHR

15
20
20
0
15
55

15
20
20
0
15
60

20
25
25
0
20
75

ns
ns
ns
ns
ns
ns

delay time
Column address
to WE delay time

tRWD
tAWD

70
35

80
40

100

ns
ns

21
21

CAS to WE delay time
Transition time (rise or fall)
Refresh period (512 cycles)
RAS to CAS precharge time
CAS setup time
(CAS-BEFORE-RAS refresh)

tCWD
tT

20
3

21
9,10

tREF
tRPC
tCSR

0
10

0
10

0
10

ns
ns
ms
ns
ns

CAS hold time

tCHR

15

15

15

ns

5

Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in setup time
Data-in hold time
Data-in hold time
(referenced to tiAS)

tiAS to

wr=

MAX

MIN

-10

SYM

MAX

3

MAX

50

20
50
64

MIN

50
64

25
3

50
64

UNITS

NOTES

22
22

5

(CAS-BEFORE-RAS refresh)

MT4C1024 L

AEV.4/92

1-18

Micron Technology, Inc., reserves the right 10 change products or specifications without nOllce.
@1992,MlcronTechnology,lno.

NOTES
1.
2.
3.
4.

All voltages referenced to Vss.
This parameter is sampled. Vee = SV ±1O%,f = 1 MHz.
Icc is dependent on cycle rates.
Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOlls is required after power-up
followed by any eight RAS cycles before proper
device operation is assured. The eight RAS cycle
wake-up should be repeated any time the IREF
refresh requirement is exceeded.
8. AC characteristics assume IT =Sns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and Vrn).
10. In addition to meeting the transition rate specification, all input signals must transit between Vrn and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = Vrn, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to 2 TTL gates and
100pF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a
new cycle and clear the data out buffer, CAS must be
pulsed HIGH for tcPN.

MT401,024L
REV. 4/92

17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
18. Operation within the tRAD (MAX) limit ensures that
lRAC (MIN) and tCAC (MIN) can be met. lRAD
(MAX) is specified as a reference point only; if lRAD
is greater than the specified tRAD (MAX) limit, then
access time is controlled exclusively by tAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. toFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL.
21. twcs, tRWD, tAWD and ICWD are restrictive
operating parameters in LATE-WRITE, and READMODIFY-WRITE cycles only. If twcs ~ twcs (MIN),
the cycle is an EARLY-WRITE cycle and the data
output will remain an open circuit throughout the
entire cycle. If IRWD ~ tRWD (MIN), tAWD ~ tAWD
(MIN) and ICWD ~ tcWD (MIN), the cycle is a
READ-WRITE and the data output will contain data
read from the selected cell. If neither of the above
conditions is met, the cycle is a LATE-WRITE and the
state of Q is indeterminate (at access time and until
CAS goes back to Vrn).
22. These parameters are referenced to CAS leading edge
in EARLY-WRITE cycles and WE leading edge in
LATE-WRITE or READ-MODIFY-WRITE cycles.
23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE =LOW.
24. BBU current is reduced as tRAS is reduced from its
maximum specification during the BBU cycle.

1-19

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©1992, Micron Technol09Y, Inc.

II
c

::rJ

l>
3:

I
c

READ CYCLE

tRAS

::rJ

l>
3:

AAS

V,H
VIL

~I

'AP

tCSH

IRRH

tASH

CAS

V,H
V,l

=~

'AA

IRAD

I~
ADDR

V,H
V,l

teAs

tACO

teRP

~IjIIM

:

tRAH

tRAl

.~I

~

WIIII,,0

AOW

~

WIIIIIIIIIIIIIIIIIIIIII;0<

COLUMN

WE

V,H
V,l

AOW

~

IRCS

YI!/ilh'!/II!/II&lllllllulllll

~
'AA

tRAG
tCAC

"elZ

-

OPEN

'b

~I

VALID DATA

~

OPEN----

EARLY-WRITE CYCLE
'Re
tRAS

RAS

'RP

VIH VIL _
tCSH

IRSH
teRP

CAS

tRCO

teAS

VIH VIL _

'AR
tRAD

ADDR

V,H
V,l

ROW

AOW

tWCR

tWGH

twes

'WP

Q

~gt-~----------------------------------OPEN------------------------------------

mI DON'T CARE
~
MT4Ci024 L

REV. 4/92

1-20

UNDEFINED

Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1992,MicronTechnology, Inc.

MIC:RON

1-·

MT4C1024 L
1 MEG x 1 DRAM

"'"",COGne

II

READ-WRITE CYCLE

(LATE-WRITE and READ-MODIFY-WRITE CYCLES)

RAS

VIH V,L
tCSH
tRSH

tCRP
CAS

teAs

tRCD

'I,

VtH -

VIL

_
tAR
tRAD

~
ADDR

Q

V,H
V,L

tRAH

ROW

ROW

~g~ = - - - - - - - - . - - - OPEN'----------l~~~--~V_;,A~L1;;;D_;;DA_;.T;;;A---i

OPEN--

FAST-PAGE-MODE READ CYCLE
1-----------------t~M~S~P----------------I~

ADDR

T4C1024L
EV.4/92

1-21

~

DON'T CARE

~

UNDEFINED

Micron Technology. Inc., reserves the right to change products or specifications without notice.

© 1992, Micron Technolqgy, Inc.

FAST-PAGE-MODE EARLY-WRITE CYCLE

a ~:~ : : : : : - - - - - - - - - - - - - - - - - - OPEN

------------------

FAST-PAGE-MODE READ-WRITE CYCLE
(LATE-WRITE and READ-MODIFY-WRITE CYCLES)

RAS

V,H

v"

tCSH

I'"
CAS

V,H

v"

*tpc / 'PRWC

=--.1

tAR}

I··IASR.
~
V,H
ROW :WII);>
:JIIIM
v"

I

COLUMN

tRAL

K"//IIII,1

0

tcwo-j -I,tts

COLUMN :WIIIII;>

I

HO

I~

I

~~I
VALID DATA

tRAe

:OFF]
'eLl-

'CLZOPEN

I
I

,

'AA

I teAer

tCWL I

VALID
DATA

I I
~I~
tew~

I~
rrX").

I

ROW

I

ICWL

-

=

~

~

ttlIs_ VALID DATA

I
I

tAA

tCPA

I

COLUMN

tRWL I

IT

lewo--

VALID DATA

I

~II~II

1·IASe. ~I

tRWD I I
I
tRcsl I I~
tAWD

JI/I/I/I/1//1//I//I
I

tePN

~

r---

~II~
I

tASH

tcp

1~ ~~

IRCD

ICRP

'RAD

AOOR

'R-

-

,
'liACiD
DATA

teLZ-

tAA

tePA

I~
--

L

- J-toFF
Ir-VAUo

OPEN--

DATA

[Zj DON'T CARE
~

*lpC is for LATE-WRITE only.
MT4C1(J24L

REV.4!92

1-22

UNDEFINED

Micron Technology, Inc., reserves the right to change products or specifications without notice
©1992, Micron Technology, Inc

RAS-ONL Y REFRESH CYCLE
(ADDR = AO-A8; A9 and WE = DON'T CARE)
'RP

'RAS

J'

Q

\

/RP

---

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