1992_WSI_Programmable_Peripherals_Design_and_Applications_Handbook 1992 WSI Programmable Peripherals Design And Applications Handbook

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Programmable Peripherals
Design and Applications
Handbook

Programmable Peripherals
Design and Applications
Handbook
1992

Copyright © 1992 WaferScale Integration, Inc.
(All rights reserved.)
47280 Kato Road, Fremont, California 94538
Tel: 510-656-5400 Facsimile: 510-657-5916 Telex: 289255
Printed in U. S. A.

________________________________________________

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________________________________________________

General Information

•

Section Index

General
Information

Table of Contents ................................................................................................................1-1
Company Profile .................................................................................................................1-3
Article Reprint .....................................................................................................................1-7
Product Selector Guide ..................................................................................................... 1-11
Ordering Information ......................................................................................................... 1-15

For additional information,
call800-TEAM-WSI (800-832-6974).
In California, Call 800-562-6363.

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Table of Contents

----~

General
Information

Table of Contents ................................................................................................................1-1
Company Profile .................................................................................................................1-3
Article Reprint .....................................................................................................................1-7
Product Selector Guide ..................................................................................................... 1-11
Ordering Information .........................................................................................................1-15

PS03XX

PSD301

Programmable Microcontroller
Peripheral with Memory .................................................................2-1

PSD311

Programmable Microcontroller
Peripheral with Memory ...............................................................2-45

PSD302

Programmable Microcontroller
Peripheral with Memory ...............................................................2-83

PSD312

Programmable Microcontroller
Peripheral with Memory .............................................................2-127

PSD303

Programmable Microcontroller
Peripheral with Memory .............................................................2-165

PSD313

Programmable Microcontroller
Peripheral with Memory .............................................................2-209

Application Note 011

The PSD3XX Device Description .............................................. 2-247

Application Note 013

The PSD301 Streamlines a
Microcontroller-based
Smart Transmitter Design .......................................................... 2-301

Application Note 014

Using the PSD3XX PAD for System
Logic Replacement ....................................................................2-313

Application Note 016

Power Considerations In The PSD3XX ..................................... 2-327

Application Note 018

Security of Design in the PSD3XX ............................................ 2-341

Application Note 019

The PSD311 Simplifies an Eight Wire Cable
It:Si8i" ~t:O:;IYII oj HJ ;111.,;1 t;:d::>eti riexiuiiily ..................................... 2-345

Family

1-1

•

I

Table of Contents

MAP168

Development
Systems

MAP168 Introduction

User-Configurable Peripheral
with Memory ..................................................................................3-1

MAP168

DSP Peripheral with Memory ........................................................ 3-3

Application Note 002

Introduction to the MAP168
User-Configu rable
Peripheral with Memory ...............................................................3-21

Electronic Bulletin Board ......................................................................................................4-1
PSD-Gold/Silver Development System ............................................................................... .4-3
WS6000 MagicPro ™ Memory and
Programmable Peripheral Programmer .............................................................................. .4-7

Package
Information ............................................................................................................................................................5-1
Sales
Representatives
and Distributors ...................................................................................................................................................6-1

---------------------------------~~~~---------------------------------

1-2

Company Profile
Company
Description

WSI is a market leading producer of highperformance programmable peripheral
integrated circuits. The company was
founded in 1983 to serve the needs of
system designers who need to achieve
higher system performance, reduce the
size and power consumption of their
systems, and shorten their product
development cycles in order to achieve
faster market entry.
WSI produces an innovative portfolio of
Programmable Peripherals as well as a
broad line of high-performance non-volatile
programmable PROM and EPROM
memory products, both based on its
patented self-aligned split-gate CMOS
EPROM technology. The new
Programmable Peripherals enable rapid
system design of high-performance

application specific controllers and related
products. These devices are the first to
integrate high-performance EPROM,
SRAM and user-configurable logic and
deliver a performance and integration
breakthrough to the programmable
peripherals market.
WSI's Programmable Peripherals and nonvolatile memory products enable electronic
designers to reduce their system size,
shorten product development cycles and
bring new system products to market in
less time. As a result, WSI has established
itself as a leading supplier of highperformance programmable solutions to a
broad customer base that includes some of
the world's largest and most technologically
advanced electronics companies.

Technology

WSI's patented self-aligned, split-gate
EPROM technology enables higher
performance and greater memory densities
per chip area than the traditional stackedgate method. By developing significantly
higher read current, the WSI EPROM cell
has enabled the development of several
memory devices that are the fastest of their
type on the market. This core NVM
technology is further leveraged by WSI's
architecture and design innovations such
as staggered virtual ground and

contactless memory arrays resulting in
dramatic die area savings. This high
density memory capability enables WSI to
provide cost-effective market leading
products such as the smallest 4-Mbit
EPROM on the market. WSI's proprietary
NVM technology (licensed to Sharp
Corporation and National Semiconductor
Corporation) has enabled WSI to be first in
the industry with numerous product
breakthroughs in speed, high density,
process innovations and packaging.

Markets and
Applications

WSI'S Programmable Peripheral and highperformance non-volatile memory products
are used by the world's leading suppliers of
advanced electronic systems in
telecommunications, data processing,
military, automotive and industrial markets.

controllers and others. High performance
memory applications include digital signal
processing, engineering workstations,
high-speed modems, video graphics
controllers, radar and others. By virtue of
their high speed and programming
capability, WSI products are ideally suited
for these applications where designers are
pushing the limits of system performance in
highly competitive markets.

Applications for the Programmable
Peripherals include cellular telephones,
disk drive controllers, modems, bus
controllers, engine management
computers, telecom switchers, motor

1-3

•

I

Company Profile

Product Groups

Programmable Peripherals

PAC1000 Peripheral Controller

WSI's family of Programmable Peripherals
represents a new class of programmable
products. They enable system designers
to reduce the size of their products,
achieve lower operating power, optimize
system performance and shorten product
development cycles. They are the first
devices to integrate high-speed EPROM,
SRAM and programmable logic on a single
chip. The Programmable Peripherals
include the PSD3XX family, the MAP168
and the PAC1000.

The high speed PAC1 000 sets a new
standard for Programmable Peripheral
performance, integration and functionality.
The PAC1000 replaces up to 50 complex
devices in high-end embedded controllers
and microprocessor-based systems.
Combining a CPU, 1K x 64 EPROM and
extensive user-configurable logic, the
PAC1 000 assists its host processor with
high rates of data manipulation and control,
freeing the processor for other system
functions. The 16 MHz PAC1000 has been
designed into numerous high-performance
applications such as work-station direct
memory access controllers, video imaging
digital signal processors, and VME bus
LAN controllers.

PSD3XX Family: Microcontroller
Peripherals with Memory
Each member of the PSD3XX family is a
single-chip, field-programmable circuit that
integrates all the required peripheral
memory and logic elements for an
embedded-control design. Programmable
logic, page logic, programmable I/O ports,
busses, address mapping, port
address/data tracking, 256K to 1 Mb
EPROM, and 16K SRAM are all on board.
Advanced features such as memory
paging, microcontroller port reconstruction,
track mode, configuration security bit, and
cascading further enhance the utility and
value of the PSD3XX family. PSD3XX
family devices are ideal for applications
requiring high-performance, low power and
very small form factors such as fixed disk
control, cellular telephones, modems,
computer peripherals, and automotive and
military applications.

MAP168lJser-Configurable Peripheral
with Memory
Similar to the PSD3XX family, the high
speed MAP168 integrates highperformance EPROM, SRAM, a PAD and
user-configurable logic. Ideal for highspeed applications requiring expanded
memory, system integration and increased
data security, the 45 ns MAP168 is used
with high speed digital signal processors,
microprocessors and microcontrollers.

Programmable Peripheral
Development Tools
WSI's Programmable Peripheral products
are supported with complete easy-to-use
system development tools from both Data
I/O and WSI. The Data I/O Unisite
programmer can be used for production
programming. The WSI tools include
program development, simulation, and
programming software, the IBM-PC hosted
MagicPro™ Memory and Peripheral
Programmer, a dial-in applications bulletin
board and WSI's team of factory service
and field application engineers. The menudriven software tools run on popular
customer owned computers and enable
designers to rapidly configure and program
the WSI part and try it in a prototype
system. Additional design iterations are
quickly accomodated. The system
development tools increase the efficiency
of the design process resulting in faster
market entry for WSI's customers'
products.

-------------------------------------f~=~~-------------------------------------

1-4

Company Profile

HighPerformance
Memory
Products

WSI offers a broad product line of highperformance CMOS PROMs and EPROMs
featuring architectures ranging from 2K x 8
to 512K x 8, plus several x16 products, with
speeds ranging from 25 to 150 ns.
Commercial, industrial and military
products including MIL-STD-883C/SMD are
available. A wide variety of package
selections include plastic and hermetic,
through-hole and surface mount types.

CMOS PROMs
As WSl's fastest family of products,
Re-Programmable Read Only Memories
(RPROMs) provide high-speed bipolar
PROM pinout with matching speed and low
power operation. The product family
includes architectures ranging from 2K x 8
to 32K x 8 with speeds ranging from 25 to
90 ns. Commercial, industrial and military
MIL-STD-883C/SMD configurations are
available in a variety of hermetic and
plastic package types.

Manufacturing

WSl's manufacturing strategy includes
utilizing multiple world-class manufacturing
partners for each facet of the production
process.
WSI has licensed its CMOS EPROM and
logic process technology to Sharp
Corporation in Japan and National
Semiconductor Corporation in the USA.
The Sharp facility in Fukuyama, Japan
employs the most advanced sub-micron
VLSI integrated circuit manufacturing
equipment available including ion
implantation, reactive ion etch, and wafer
stepper lithographic systems. The worldclass high volume National Semiconductor
operation delivers low cost production of
1.2 micron CMOS technology product on 6"
wafers. This low defect density
manufacturing resource is capable of
producing sub-micron technology product
in thR nRar futurR.

"F" Family EPROMs
The high-speed "F" series EPROM family
offers speeds ranging from 35 to 70 ns and
architectures from 8K x 8 to 32K x 8, plus
several x16 products. "F" family
EPROMs are ideal for use in high-end
engineering and scientific workstations,
data communications and similar highperformance applications.

"L" Family Military EPROMs
WSl's "L" family military EPROM memory
products feature high-density and high
speed in popular JEDEC pinouts. With
speeds ranging from 120 to 300 ns and
architectures from 64K x 8 to 512K x 8
including several x16 products, the "L"
family offers significant speed and high
density benefits for developers of military
avionics, communications, and control
systems. The "L" family delivers world class
densities from WSl's conservative 1.2
micron lithography CMOS process
technology.

High-volume, low cost integrated circuit
packaging and testing is performed for WSI
by ANAM Electronics in Seoul, Korea, Fine
Products in Hsinchu,Taiwan, National
Semiconductor in Santa Clara, CA and at
WSI in Fremont, CA. ANAM is the largest
independent manufacturer of I.C.
packaging and produces excellent product
quality. Test capability ranges from simple
logic devices to complex VLSI product.
ANAM routinely processes a wide variety of
high volume packages and enables WSI to
leverage its materiel needs through
ANAM's combined high-volume, low cost
procurement activity. Commercial,
industrial, and military grade product
processing is available from ANAM.
Additional quality assurance and reliability
testing are performed at WSI in Fremont,
CA.
WSl's manufacturing strategy ensures the
supply of double-sourced high quality, highvolume product with low variable cost and
fast delivery.

-------------------------------------rJrArjF~-----------------------------------.,.,.
1-5

•

Company Profile

Sales Network

WSI's international sales network includes
several regional sales managers who direct
the resources of the company to major
market opportunities. Experienced
technical field application engineers located
in each field office assist WSI's customers
during their advanced product development
and match customer needs with WSI's
product solutions. Over sixty
manufacturer's representatives and leading
national and regional component
distributors in the United States, Europe
and Asia round out the WSI sales network.

United States
Direct sales and field application
engineering offices in Boston, Chicago,
Huntsville, Philadelphia, Dallas, Los
Angeles and Fremont, CA; More than 25
manufacturer's representatives for major
national accounts; national distributors
include Arrow/Schweber, Time Electronics
and Wyle Laboratories; and regional
distributors.

International

Financing

Management and Previous
Affiliations:
Michael Callahan
President, CEO and
Chairman of the Board
(Advanced Micro Devices, Monolithic
Memories, Motorola)

Robert J. Barker
V. P. Finance, CFO and Secretary
(Monolithic Memories, Lockheed)

John Ekiss
V. P. Marketing
(Intel, Motorola)

Thomas Branch
V. P. Worldwide Sales
(Monolithic Memories, Fairchild)

George Kern
V. P. Operations
(Advanced Micro Devices, Monolithic
Memories)

BoazEitan
V. P. New Product and.
Technology Development
(Intel)

Direct WSI Sales management offices in
Paris, Munich and Hong Kong; sales
representatives and distributors in
Germany, England, France, Italy, Sweden,
Finland, Denmark, Norway, Spain,
Belgium, Luxembourg, the Netherlands,
and Israel. Sales representatives and
distributors for the Asia/Pacific Rim region
in Japan, Korea, Taiwan, Hong Kong,
Singapore and Australia.

Bob Buschini

WSI is a privately held California
corporation founded in August, 1983. The
company has been financed by corporate
investors, institutional investors, venture
capital groups and private investors.
Corporate investors are Sharp Corporation,
National Semiconductor Corporation,
Intergraph Corporation, and Kyocera
Corporation. Venture capital investors
include Accel Partners, Adler and
Company, Bessemer Venture Partners,
Genevest Consulting Group S. A.,

J. H. Whitney, Oak Investment Partners,

Director of Human Resources
(General Electric, Raychem)

Robertson Stephens and Co., Smith
Barney Venture Corporation, and Warburg
Pincus. The company has been audited
annually since its inception by Ernst &
Young (Arthur Young prior to 1989) and
regularly reports financial information to
Dunn & Bradstreet (Dunns number is
10-209-8167).

MagicPro™is a trademark of WaferScale Integration, Inc.
IBM and IBM·PC are registered trademarks of International Business Machines Corporation.
S'JiiFE 8EJE
--------------------------------------~~af~--------------------------------------

1-6

PRODUCT INNOVATION

PROGRAMMABLE SYSTEM'M
DEVICE FITS MULTIPLE
MICRO CONTROLLERS

•

IC HAS EPROM, RAM,
AND LOGIC FOR
45 CONFIGURATIONS;
INTERFACES
8- AND 16-BIT

MICRO CONTROLLERS.
MILT LEONARD
he embedded-controller market embraces a myriad of 8- and 16bit microcontroller architectures that can satisfy just about any
conceivable application requirement. However, each different
controller requires its own unique combination of discrete devices to link the
part to other system elements. Furthermore, changing application requirements usually call for restructuring 110 ports. Consequently, the application
may eventually outgrow system memory and shared resources may demand
multiple chip solutions. This means that in addition to comparing controllers on
the merits of price and performance, prospective users must also consider the
external circuitry that the controller needs to interface to the rest ofthe system.
A new chip from WaferScale Integration Inc., Fremont, Calif., simplifies system integration by combining RAM, EPROM, programmable decoding, and
contJgurable I/O ports that expand 8- or 16-bit microcontrollers when they run
out of on-chip resources. WaferScale's PSD301 is the first single-chip solution
to offer a microcontroller with port expansion, latched address lines, a programmable address decoder (PAD), an expansion interface to shared resources, a
256-kbit EPROM, and a 16-kbit static RAM. In addition, the chip links directly to
popular 8- and 16-bit microcontrollers without using glue logic.
The PSD301 architecture is a major enhancement of WaferScale's MAP168
mappable memory chip introduced last year (see ELECTRONIC DESIGN, July 28,
1988, p. 91). In addition to the memory, decoding, and muitipiexer functions of
the 168, the 301 includes three software-configurable 8-bit 110 ports (A, E, and
C), configuration registers, latched inputs, more chip-select lines, and more
control on the strobe lines (Fig. 1). Like the 168, a programmable security bit is
given to protect against reverse engineering.
Most controllers can't be reprogrammed once they're configured. Moreover,
their controller's 110 ports are designed to perform one of two mutually excluReprinted with permission from ELECTRONIC DESIGN

-----------------------------------------rAfAr~~---------------------------------------
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1-7

Article Reprint

USER·CONFIGURABLE
MICROCONTROLLERINTERFACE
sive functions: convey control signals to peripheral devices or address
and data signals to shared resources.
Supplying both of these functions requires a multiple chip solution.
Microcontrollers also differ in
boot-up locations and address mapping in memory. The 8051 and 8096
microcontrollers, for example, locate
boot-up sequences in the lower half
of their memory maps, while the
80186/88 and 68HCXXX use a high
memory boot-up address. Another
factor is the differences in controlsignal polarities.
The PSD301 is designed to adapt
the characteristics of different microcontrollers to an embedded-control design. The PAD plays a major
role in this function. It performs similarly to a small programmable array
logic (PAL) device. The PAD has up
to 13 inputs and 11 outputs in a NORgate array, and it can implement up
to four sum-of-product expressions

Configuration
registers

.

Vcc
GND
RillE

based on address inputs, control signals, and chip-select inputs. The PAD
selects all of the chip's internal parts.
and generates external chip selects
with a 35-ns delay.
Address inputs from the host microcontroller are first fed to the 301's
input latches, which stabilize the inputs when the device accesses memory in the multiplexed mode. The
latches are made transparent in the
non multiplexed mode. Five low-order address inputs and five programmable control lines are fixed functions; the Address-Latch-Enable and
Reset lines have programmable polarity. The high-order address lines
can be either address or general-purpose inputs for logic functions.
For more efficient use of memory
space, internal and external PAD-Select signals can override EPROM
memory with overlapping addresses. Therefore, if all of the EPROM
isn't used for program storage, the

J

-

WR/Vpp or R/W

Control

BHE/PSEN
Reset
A19/CSi

~
Lat~hB

ALE
AS
A0-7 /AD0-7

.r-tl

A0-7

Latch A

...
80r16
select
(CData)

-

1

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~

Programmable
address
decoder
(PAD)

~"

• 

-- &

-

CS0-7

PortB

D0-7/AD0-7

-- -- I~ "". "' IL~
.....

RSO

~

Key:
ALE = Address Latch Enable
AS = Address Strobe

~

256·Kbit EPROM
8blocks
(4k X 80r2k X 16)
of EPROM
8or 16 select
(CD~

AO

T

A8-15/AD8-15

,

~

unused space can be allocated to II 0
ports, static RAM, or other PAD-select signals.
The EPROM is configurable as 32
kwords by 8 bits, or 16 kwords by 16
bits, and it's partitioned into eight
equal mappable blocks with a resolution of 4 kbytes or 2 kwords. Access
time, including PAD decoding time,
is 120 ns. The configuration registers
also consist of EPROM cells. The
registers store the programmed configuration bits that make it possible
for users to set the device, II 0, and
control functions according to the required operating mode. The 16-kbit
120-ns static RAM is configurable as
2 kwords by 8 bits, or 1 kword by 16
bits. The memory blocks can be noncontiguously mapped ove,- the addressable range of 1 Mbyte or 0.5
Mwords. Consequently, programmers can scramble the code to prevent direct copying.
I/O ports A and B in the 8- and 16-

D8-15

DO_7/AD0-7

(2k X 80rlk X 16)

Address bus AO_15

Multiplexed or
nonmultiptexed
select

8or 16 select = Data Bus·
Width Select

T A,_lO

PortA

,.-------

A16-18

PC0-2

PortC

CS8-lO
RSO = RAM Select
ES0-7= EPROM Block Select

L--...-

PC0-2 = PAD input or out·
putO-3

1. AHIGHLY RECONFIGURABLE PSD 301 microcontroller peripheral from WaferScale Integration has multiplexed or

nonmultiplexed data and address buses with selectable 8- or I6-bit bus widths. The programmable address decoder (PAD) helps supply up to 45
configuration options for supporting a range of 8- and I6-bit microcontrollers.

===:!if!fE§

------------------------------------------~~~~------------------------------------------

1-8

Article Reprint

USER·CONFIGURABLE
MICROCONTROLLERINTERFACE
AD8-15
ADII-7
ALE
BHE/PSEN
R/W Dr WR/V pp
Ril/E
AI9/CSi
Reset

ALE = Address Latch Enabte
PortA

I/O Dr AII-7 ADII-7

PortB

I/O Dr Chip Selectll-7

BHE/PSEN = Byte High Enable Dr Program Store Enable
R/W orWR/Vpp = Read/Write Dr Write/Programming Voltage

•

Ril/E = Read/Enable
AI9/CSi = High Address Bit Dr Chip Select Input (power down)

porte

A'6-18 or Chip Select8-1O

I/O or AII-7 ADII-7 = I/O, non· multiplexed low·order address
input byte, or multiplexed low· order address/data byte.

1

2. 1/0 PORT CONFIGURATION FOR THE PSD:301 IS PROGRAMMED by signals from the PAD, which are derived
partly from programmed bits in the configuration registers. The three ports configured for multiplexed address and data with a I&bit wide data
bus are shown.

bit configurations are data ports in
the nonmultiplexed mode, and both
ports can be configured as either
data or address ports in the multi·
plexed mode (Fig. 2). Port C is inde·
pendent of any configuration-it can
supply multiple chip-select outputs
or serve as address inputs.
The default configuration of port
A in the nonmultiplexed address I
data mode sets the port to deliver II
o lines. In this mode, each pin can be
set as an input or output and can
have a CMOS or open-drain output.
Alternatively, each bit of port A can
be configured as a low-order latchedaddress-bus bit to access external
peripherals or memory that requires
several low-order lines. Another option in this mode sets the entire port
to track the low-order addressl data
multiplexed bus. This feature links
the host microcontroller to shared
resources without the use of external buffers and decoders.
In the non multiplexed mode, port

PRICE AND AVAILABILITY
The commercial version of the
PSD301, packaged in a 44·pin
plastic leaded chip carrier, is
priced at $15 each in quantities of
1000. Military parts are also available. Other packagE vptivn3 ai.~€
ceramic leaded chip carriers and
pin grid array packages with windows. The PSD301 is being sampled now, with production quantities available in January, 1990.
WaferScale Integration Inc.,
47280 Kato Rd., Fremont, CA
94538; (415) 656·5400.

A becomes the chip's low-order data- mance of 16·bit controllers, such as
bus byte. When a read operation is the 80186, 8096, 80196, 16000, and
executed from an internal 301 loca- others, without adding external detion, data is directed out on port A vices. And the 8051 microcontroller
pins. When a write cycle is executed family can extend its memory space
into an internal 301 location, data is by using the separate address and
driven into port A.
program memory space of the 301.
The operation of port B in the mul- The 301 is cascadable for increased
tiplexed address/data and 8-bit non- width or depth for mUltiplexed bytemultiplexed modes is the same as or word-wide embedded-control deport A. However, as an alternative, signs.
each bit can be configured to supply
In the standby mode, commercial
a Chip-Select Output signal from the versions of the 301 draw 150 ,..,A and
PAD. In the 16-bit nonmultiplexed 1.5 rnA for CMOS and TTL intermode, port B is the high-order data- faces, respectively. Active current
bus byte of the chip. When a read op- for CMOS interfaces with or without
eration is executed from an internal selected memory blocks, or with the
high-order data-bus byte location, EPROM blocks selected, is 55 rnA.
the data appears on port B pins. That level increases to 80 rnA for
When a write operation is executed TTL interfaces. Selecting the static
into an iniernal high-order data-bus RAM block increases active current
byte location, data and write opera- to 105 rnA and 130 rnA for CMOS and
TTL, respectively.
tion signals are present at port B.
Each pin of port C in all modes can
WaferScale Integration houses
be configured as an input or output the device in a 44-pin surface-mount·
from the PAD. Although designated ed package to meet the form-factor
as high-order address bus pins, they requirements of such products as
can be used for any logic inputs to 5.25·, 3.5-, and 2.5-in. disk drives, celthe PAD or for external chip-select lular phones, and modems. System
development tools include an IBM·
outputs from the PAD.
With this degree of operational PC plug-in programmer board and
flexibility, the 301 can team up with remote socket adaptor. They also
all popular 8- and 16-bit microcon- contain a software development
trollers from such companies as Ad- package that runs on an IBM PCI
vanced Micro Devices, Intel, Motor- XT I AT or compatible computer with
ola, National Semiconductor, Texas a MS-DOS version 3.1 or higher, 640
Instruments, and Zilog. For exam- kbytes of RAM, and a hard disk.o
ple, the polarity of the 301's control
signals can be programmed for direct connection of the read-write and iFEE liE=:
output enable pins of the 68HCXX rESS ..
microcontroller family. The 16·bit
---~
configuration can boost the perfor- WAFERSC4LE INTEGRATION, INC.

- '--- ---

-----------------------------------~~~~----------------------------------

1-9

r~
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F

1-10

___________________________

§_~

_III

-- -

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____________~P~R~O~D~U~C~T~S~E=L=E~C~TI~O~R~G~U~/~D~E
JANUARY 1992

PROGRAMMABLE PERIPHERALS
SINGLE-CHIP CMOS USER-CONFIGURABLE PERIPHERAL WITH MEMORY - COMMERCIAL & MILITARY
Speed (ns)
Availability
Package Selection
J
L Q
X
Samples Prodn
Part No.
Description
Comm'l Military
PSD301

Programmable Microcontroller
Peripherals with Memory;

120
150-200

x8/x16; 256Kb-1Mb EPROM;
PSD311

16K SRAM; PAD; System
Features.

NOW

04 '91

NOW

NOW

NOW

04 '91

NOW

04 '91

NOW

200
120
150-200

04'91

200
120

NOW

01 '92

150-200

NOW

01 '92

PSD312

120
150-200

NOW
NOW

01 '92
01 '92

PSD303

120

04 '91

01 '92

150-200

04'91

01 '92

120

04'91

01 '92

150-200

04'91

01 '92

45-55

NOW

NOW
NOW

PSD302

PSD313
MAP168

DSP Peripheral with Memory. Features:
128K Bits EPROM, 32K Bits SRAM

55

Programmable Address Decoder (PAD)

·
·
·
·

··
·
·

·
·
·
··
·
·
··
·

·
· ·
·
·· ·
·

-_._-

·· · ·· ·

Configurable: x8 or x16.

HIGH-PERFORMANCE CMOS USER-CONFIGURABLE EMBEDDED CONTROLLER COMMERCIAL & MILITARY
Availability
Speed (ns)
Part No. Description
Comm'l Military
Samples Prodn
PAC1000

Programmable Peripheral Controller
optimized for High-Performance Control
Systems. Key Features Include:

12MHz
12MHz
16MHz

NOW

NOW

NOW
NOW

NOW
NOW

Package Selection

Q

X

16-Bit CPU, 16-Bit Address Port, 16-Bit
Output Control, 8-Bit 1/0 Port and
Configuration Registers.

HIGH-PERFORMANCE CMOS USER-CONFIGURABLE MICROSEQUENCERISTATE MACHINECOMMERCIAL & MILITARY

Part No_
SAM448

Description

Speed (ns)
Comm'l Military

User-Programmable Microsequencer

20-25MHz

for Implementing High-Performance

20MHz

Availability
Samples Prodn
NOW

NOW

NOW

NOW

Package Selection
J
L
S
T

*

*

State Machines. Includes EPROM
integrated with Branch Control Logic,
Pipeline Register, Stack and Loop
Counter and 768 Product Terms.

*J and S packages not available in 30MHz
1-11

II

PRODUCT SELECTOR GUIDE

SOFTWARE DEVELOPMENT TOOLSt
Part No.

Availability

Includes

PSD- GOLD

NOW

Contains PSD301/MAP168 Software, Users Manual,
WS6000 MagicPro (PC Based Programmer), WS6014(J/L)
or WS6015( X ) Adapter and 2 Sample Devices

PSD - SILVER

Contains PSD301/MAP168 Software and Users Manual

NOW

PAC1 000 - GOLD

Contains PAC1000 Software, Users Manual,

NOW

WS6000 MagicPro (PC Based Programmer), WS6010 (X)
Adapter and 2 Sample Devices
PAC1000 - SILVER
SAM448 - GOLD

Contains PAC1000 Software and Users Manual

NOW

Contains SAM448 Software, Users Manual,

NOW

WS6000 MagicPro (PC Based Programmer), WS6008(T)
or 6009(C,J,L) Adapter and 2 Sample Devices
SAM448 - SILVER

Contains SAM448 Software and Users Manual

NOW

MEMORY - SILVERtt

Contains WSI EPROM/RPROM Programming Software

NOW

and Users Manual
t

1) All Development Systems include: 12 Month Software Update Service, access to WSl's 24 Hour Electronic Bulletin Board.
2) Package adaptor must be specified when ordering any "Gold" system.

tt

1) Memory-Silver is included in all development systems.

NON-VOLATILE MEMORY
CMOS PROMs - COMMERCIAL

Part No.

Architecture

Description

Speed (ns)

WS57C191B

2Kx 8

16K CMOS PROM

35-55

WS57C291B

2Kx 8

16K CMOS PROM

35-55

WS57C45

2Kx 8

16K CMOS Reg. PROM

25-35

WS57C43B

4K x 8

32K CMOS PROM

35-70

WS57C49B

8K x 8

64K CMOS PROM

35-70

WS57C49C

8K x 8

64K CMOS PROM

35-70

WS57C51C

16Kx 8

128K CMOS PROM

35-70

WS57C71C

32Kx 8

256K CMOS PROM

45-70

D

Package Selection
L
T
J
P
S

C

Package Selection
D
F H
K T

CMOS PROMs - MILITARY

Part No.

Architecture

Description

Speed (ns)

WS57C191B

2Kx 8

16K CMOS PROM

45-55

WS57C291B

2Kx 8

16K CMOS PROM

45-55

WS57C45

2K x 8

16K CMOS Reg. PROM

35-45

WS57C43B

4K x 8

32K CMOS PROM

45-70

WS57C49B

8K x 8

64K CMOS PROM

45-70

WS57C49C

8Kx 8

64K CMOS PROM

45-70

WS57C51C

16Kx 8

128K CMOS PROM

45-70

WS57C71C

32Kx 8

256K CMOS PROM

55-70
if_IE 4lEE

1-12

filII

DESC
SMD

Z

PRODUCT SELECTOR GUIDE
NON- VOLATILE MEMORY (Cont.)
HIGH-SPEED CMOS EPROMs - COMMERCIAL

Part No.

Architecture

Description

WS57C64F

8K x 8

High-Speed 64K CMOS EPROM

Package Selection
D
J
L
T

Speed (ns)
55-70

WS57C128F

16Kx 8

High-Speed 128K CMOS EPROM

55-70

WS57C128FB

16Kx 8

High-Speed 128K CMOS EPROM

35-45

WS57C256F

32Kx 8

High-Speed 256K CMOS EPROM

45-70

HIGH-SPEED CMOS EPROMs - MILITARY

Part No.

Architecture

Description

Speed (ns)

WS57C64F

8K x 8

High-Speed 64K CMOS EPROM

WS27C64F

8K x 8

Low-Power 64K CMOS EPROM

90

WS57C128F

16K x 8

High-Speed 128K CMOS EPROM

70
45-55

DESC
SMD

Package Selection
eDT
L

70

WS57C128FB

16K x 8

High-Speed 128K CMOS EPROM

WS27C128F

16K x 8

Low-Power 128K CMOS EPROM

90

WS57C256F

32K x 8

High-Speed 256K CMOS EPROM

55-70

WS27C256F

32K x 8

Low-Power 256K CMOS EPROM

90

CMOS EPROMs - COMMERCIAL

Part No.

Architecture

Description

Package Selection
D J
L

Speed (ns)

WS27C010L

128K x 8

Low-Power 1 Meg CMOS EPROM

120-150

WS27C210L

64K x 16

Low-Power 1 Meg CMOS EPROM

100-200

CMOS EPROMs - MILITARY

Part No.

Architecture

Speed (ns)

Description

WS27C256L

32Kx 8

Low-Power 256K CMOS EPROM

120-250

WS27C512L

64Kx 8

Low-Power 512K CMOS EPROM

120-200

WS27C010L

128K x 8

Low-Power 1 Meg CMOS EPROM

150-200

WS27C210L

64K x 16

Low-Power 1 Meg CMOS EPROM

150-200

--=

DESC
SMD

Package Selection
C D
L
T

-----------------------------------rJrJr~~--------------------------------------~~
1-13

•

PRODUCT SELECTOR GUIDE
CMOS BIT SLICE AND LOGIC
Part No.

Description

Speed
Comm'l
Military

WS5901

4-Bit CMOS Bit Slice Processor

32,43 MHz

B

G

Package Selection
J
K
L
P
S

y

32,43MHz

WS59016

16-Bit CMOS Bit Slice Processor

15 MHz

12.5MHz

WS59032

32-Bit CMOS Bit Slice Processor

26.4,33 MHz

23.6,29 MHz

WS5910

CMOS Microprogram Controller

20,30 MHz

20,30 MHz

WS59510

16K x 16 CMOS Multiplier-Accum.

WS59520

CMOS Pipeline Register

Tpd

= 22ns

WS59521

CMOS Pipeline Register

Tpd

WS59820

CMOS Bi-Directional Register

Tpd

30-50 ns
Tpd

= 24ns

= 22ns

Tpd

= 24ns

= 23ns

Tpd

= 25ns

WSI PACKAGE DESCRIPTIONS
Package Code
BIR
C

C/Z
DIY
F/H

J
LIN
P
Q
S
T/K
XlG

Description
Ceramic Sidebrazed Dip
Ceramic Leadess Chip Carrier (CLLCC)
Ceramic Leadless Chip Carrier (CLLCC)
0.600" Ceramic Dip
Ceramic Flatpack
Plastic Leaded Chip Carrier (PLDCC)
Ceramic Leaded Chip Carrier (CLDCC)
Plastic Dip
Plastic Quad Flat Pack (PQFP)
0.300" Plastic Dip
0.300" Ceramic Dip
Ceramic Pin Grid Array (CPGA)

Window

Surface Mount

NIY
Y

N
Y
Y
N
Y
Y
Y
N
Y
N
N
N

YIN
YIN
YIN

N
YIN

N
N
N
YIN
YIN

Plastic/OTP

Y
Y
Y
Y

WSI REGIONAL HOTLINES

47280 Kato Road
Fremont, California 94538-7333
Tel: 510-656-5400 Fax: 510-657-5916
800-TEAM-WSI (800-832-6974)
In California 800-562-6363

1-14

USA Northwest:
USA Southwest:
USA Midwest:
USA Southeast:
USA Mid-Atlantic:
USA Northeast:
Europe (France):
Europe (Germany)
Asia (Hong Kong)

Tel:
Tel:
Tel:
Tel:
Tel:
Tel:
Tel:
Tel:
Tel:

510-656-5400
714-753-1180
708-882-1893
214-680-0077
215-638-9617
508-685-6101
33 (1) 69-32-01-20
(49) 89.23.11.38.49
852-575-0112

Fax:
Fax:
Fax:
Fax:
Fax:
Fax:
Fax:
Fax:
Fax:

510-657-5916
714-753-1179
708-882-1881
214-680-0280
215-638-7326
508-685-6105
33 (1) 69-32-02-19
(49) 89.23.11.38.11
852-893-0678

Printed in U. S. A. 1/92 • Revision 8.4

Ordering Information
High-Performance CMOS Products

PSD3XX

~

-35

o

B

L

Basic Part Number

•

Manufacturing Process:
(Blank) = WSI Standard Manufacturing Flow
B

= MIL-STD-883C Manufacturing Flow

Operating Temperature Range:
(Blank) = Commercial: 0° to + 70°C
Vee: +5V ± 5%
= Industrial: -40° to +85°C
Vee: +5V ± 10%
M

L

= Military: -55° to +125°C
Vee: +5V ± 10%

Package:

Window

A
B
C
D
F
G
H
J
K
L
N
P
Q
R
S
T
W
X
Y
Z

No
No

=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=

PPGA Plastic Pin Grid Array
0.900" Size Brazed Ceramic DIP
CLLCC Ceramic Leadless Chip Carrier
0.600" CERDIP
Ceramic Flatpack
CPGA Ceramic Pin Grid Array
Ceramic Flatpack
Plastic Leaded Chip Carrier
0.300" Thin CERDIP
CLDCC Ceramic Leaded Chip Carrier
CLDCC Ceramic Leaded Chip Carrier
0.600" Plastic DIP
Plastic Quad Flatpack
Ceramic Side Brazed
0.300" Thin Plastic DIP
0.300" Thin CERDIP
Waffle Packed Dice
Ceramic Pin Grid Array
0.600" CERDIP
CLLCC

Yes'
Yes
Yes'

No
No'
No'
No
Yes'

No'
No
No'
Yes

No
Yes
Yes

No
No

Speed:
-120 = 120 ns
-150=150ns
- 200 = 200 ns
Etc.
• Surface Mount

----JIj

-----------------------------------~~;--------------------------------1----15

~1-~16~-------------------~f~;------------------------

......--.. _-- - -........-.-==...,
~
-~

--~

~

~

:;:

~'!!i-i!i!!iii==-~-=
-"'"
~~

PSD3XX Family

•

Section Index

PSD3XX

PSD301

Programmable Microcontrolier
Peripheral with Memory ...............................................................2-1

PSD311

Programmable Microcontrolier
Peripheral with Memory .............................................................2-45

PSD302

Programmable Microcontrolier
Peripheral with Memory .............................................................2-83

PSD312

Programmable Microcontrolier
Peripheral with Memory ........................................................... 2-127

PSD303

Programmable Microcontrolier
Peripheral with Memory ...........................................................2-165

PSD313

Programmable Microcontrolier
Peripheral with Memory ........................................................... 2-209

Application Note 011

The PSD3XX Device Description ............................................. 2-247

Application Note 013

The PSD301 Streamlines a
Microcontrolier-based
Smart Transmitter Design ........................................................2-301

Application Note 014

Using the PSD3XX PAD for System
Logic Replacement ..................................................................2-313

Application Note 016

Power Considerations in the PSD3XX ..................................... 2-327

Application Note 018

Security of Design in the PSD3XX ........................................... 2-341

Application Note 019

The PSD311 Simplifies an Eight Wire Cable
Tester Design and Increases Flexibility .................................... 2-345

Family

For additional information,
caI/800-TEAM-WSI (800-832-6974).
In California, CaI/800-562-6363.

Programmable Peripheral
'80301

Programmable Microcontrol/er Peripheral
with Memory

Key Features

o
o

19 Individually Configurable I/O pins
that can be used as

-

Microcontroller I/O port expansion

-

Programmable Address Decoder
(PAD) I/O

-

Latched address output

-

Open drain or CMOS

o

Two Programmable Arrays
(PAD A and PAD B)

-

Total of 40 Product Terms and up to
16 Inputs and 24 Outputs

-

Address Decoding up to 1 MB

-

Logic replacement

o
-

Partial Listing
of
Microcontrollers
Supported

Single Chip Programmable Peripheral
for Microcontroller-based Applications

-

Block resolution is 4K x 8 or 2K x 16

-

120 ns EPROM access time, including
input latches and PAD address
decoding.

o

16 Kbit Static RAM

-

Configurable as 2K x 8 or as 1K x 16

-

120 ns SRAM access time, including
input latches and PAD address
decoding

o
-

o
-

Address/Data Track Mode
Enables easy Interface to Shared
Resources (Mail Box SRAM) with other
Microcontrollers or a Host Processor
Built-In Security
Locks the PSD301 Configuration and
PAD Decoding

"No Glue" Microcontroller Chip-Set
Built-in address latches for multiplexed
address/data bus
Non-multiplexed address/data bus
mode

-

Selectable 8 or 16 bit data bus width

-

ALE and Reset polarity programmable

-

Selectable modes for read and write
control bus as RD/WR or R/W/E

-

BHE/pin for byte select in 16-bit mode

-

PSEN/pin for 8051 users

o

256 Kbits of UV EPROM

-

Configurable as 32K x 8 or as 16K x 16

-

Divides into 8 equal mappable blocks
for optimized mapping

o Motorola family:
M68D5, M68HC11, M68HC16,
M68000/10/20, M60008, M683XX

o Intel family:
8031/8051,8096/8098,80186/88,
80196/98

o

Available in a Variety of Packaging

-

44 Pin PLDCC and CLDCC

-

52 Pin PQFP

-

44 Pin CPGA

o
o

Simple Menu-Driven Software:
Configure the PSD301 on an IBM PC
Pin Compatible with the
PSD3XX Family

OTI:

o Signetics:
o Zilog:
o National:

TMS320C14
SC80C451, SC80552
Z8,Z80,Z180
HPC16000, HPC63400

2-1

•

P5D301

Applications

o
o

Introduction

Product
Description

Computers (Workstations and PCs)
Fixed Disk Control, Modem, Imaging,
Laser Printer Control

o

Telecommunications
Modem, Cellular Phone, Digital PBX,
Digital Speech, FAX,
Digital Signal Processing

o

The PSD301 is a member of the rapidly
growing family of PSD devices. The
PSD301 is ideal for microcontroller-based
applications, where fast time-to-market,
small form factor, and low power consumptions are essential. When combined
in an 8- or 16-bit system, virtually any
microcontroller (68HC11, 8051,8096,
16000, etc.) and the PSD301 work together
to create a very powerful chip-set solution.
This implementation provides all the

The PSD301 integrates high performance
user-configurable blocks of EPROM,
SRAM, and programmable logic technology
to provide a single chip microcontroller
interface. The major functional blocks
include two programmable logic arrays,
PAD A and PAD B, 256K bits of high speed
EPROM, 16K bits of high speed SRAM,
input latches, and output ports. The
PSD301 is ideal for applications requiring
high performance, low power, and very
small form factors. These include fixed disk
control, modem, cellular telephone, instrumentation, computer peripherals, military
and similar applications.
The PSD301 offers a unique single-chip
solution for microcontrollers that need:

o

o
o

I/O reconstruction (microcontrollers
lose at least two I/O ports when
accessing external resources).
More EPROM and SRAM than the
microcontroller's internal memory.
Chip-select, control, or latched address
lines that are otherwise implemented
discretely.

o

Industrial
Robotics, Power Line Access,
Power Line Motor
Medical Instrumentation
Hearing Aids, Monitoring Equipment,
Diagnostic Tools
Military
Missile Guidance, Radar, Sonar,
Secure Communications, RF Modems

required control and peripheral elements of
a microcontroller-based system peripheral
with no external discrete "glue" logic
required.
The solution cornes complete with simple
system software development tools for integrating the PSD301 with the microcontroller. Hosted on the IBM PC platforms or
compatibles, the easy to use software
enables the designer complete freedom in
designing the system.

o

An interface to shared external
resources.

WSI's PSD301 (shown in Figure 1) can efficiently interface with, and enhance, any 8or 16-bit microcontroller system. This is the
first solution that provides microcontrollers
with port expansion, latched addresses,
two programmable logic arrays PAD A and
PAD B, an intertace to shared resources,
256K bit EPROM, and 16K bit SRAM on a
single chip. The PSD301 does not require
any glue logic for interfacing to any 8- or
16-bit microcontroller.
The 8051 microcontroller family can take
full advantage of the PSD301 's separate
program and data address spaces. Users
of the 68HCXX family of microcontrollers
can change the functionality of the control
signals and directly connect the RiW and
E, or the R/W and DS signals. Users of 16bit microcontrollers (including the 80186,
8096, 80196, 16XXX) can use the PSD301
in a 16-bit configuration. Address and data
buses can be configured to be separate or
multiplexed, whichever is required by the
host processor.

------------------ r== =..:-----------------2-2

~:='~

PSD301

Product
Oiscription
(Cont.)

The flexibility of the PSD301 1/0 ports
permits interfacing to shared resources.
The arbitration can be controlled internally
by PAD A outputs. The user can assign the
following functions to these ports: standard
1/0 pins, chip-select outputs from the PAD
A and PAD B, or latched address or mUltiplexed low-order addressldata byte. This
enables users to design add-on systems
such as disk drives, modems, etc., that
easily interface to the host bus (e.g., IBM
PC, SCSI).

Figure 1.
P80301
Architecture

The PSD301 on-chip programmable
address decoder (PAD A) enables the user
to map the 110 ports, eight segments of
EPROM (as 4K x 8 or as 2K x 16) and
SRAM (as 2K x 8 or as 1K x 16) anywhere
in the address space of the microcontroller.
PAD B can implement up to 4 sum-ofproduct expressions based on address
inputs and control signals.

-

A16 A18
L
A
T
C
H

AD8-AD15

A19

-r- I·

CSIOPORT
A19
CSI

PADA

ALE/AS

t---

'--

WR
RESET

13 P.T.

.. -

27 P.T.

~
CS8-

ESO

~~~

~

CSOCS7

'----t

~

-- I.~

.

r

D8-D15

r+-



BOC196KB

~

~~
I

~

'--'=-----"

r---?

II-----<:

3

~
6
5

.-

11
10

'------"

~
~

18
1?

44

RF

XTALl

Pl.0

V"

P1.1

READY

P1.2
Pl.3
Pl.4
P1.5
Pl.6

BUSWIDTH

Pl.?

XTAl2
NMI

CDE
RESET

P3,QIADQ
P3.1/ADl

PO.D

P3.2/AD2

PO.l

P3.3/AD3

PO.2

P3.4IAD4
P3.5/AD5

PO.3
PO.4
PO.S
PO.6
PO.?

P3.6/A06

19
20

22
23
30
31
32

}

60
59
58

ADOIAO
AD1/A1
AD2/A2
AD3/A

56
55
54

AD4/A4
AD5/A5

~

."81M

~

P3.7/AD7
P4.0/AD8

P2.QITXD

P4.1/A09
P4,2/ADlO

P2.1/RXO

P4.3/AD11

P2.2IEXINT
P2.3!T2CLK
P2.4!T2RST

P4.4/AD12

P2.5IPWM

P4.71AD15

P4.51AD13

P4.6/AD14

ADBIAI

~
+5V

0.1

"F;:~

CLKOUT

P2.7iT2 CAPTR

--~

-,.
24

25

27
13

t:±

BHE/WRH
--

HSI.O
HSl.l

WR/WRL

HSI.2.1HSO.4
HSI.3IHSO.5

ALE/AOV
INST

-

VPP

HSO.O
HSO.1

ANGND

HSO.2

VREF

CA

'\, "",

1

36

68

FOUR
GENERAL
PURPOSE
INPUTS

-

~

AD

HS01

23
2,

ADO/AD

AD2/A2
AD3/A

25
?R

AD2JA2

~

AD?/A

30

~

AD7!A7

AD81AB

"

ADS/AS

r-,.-

49 AD11/A11
48 AD12/A1:

. 47A5i:j)Ai
46 AD14/A14
-45A5i57A15

I::-T,40
61

±-

Rt=
ns---

~

~

Veo

ADl/Al

AD3/A3
AD4/A4

ADS/AS
AD6/A6

AD9/A9

P2.6iT2 UPtON

'------"

ADOIAO
"/A1

~

52
51

~01"F

P80301

09/A9

~i

"

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB?

AD9/A9
AD10/Al0

A0111Al1
AD121A12
AD131A13
A0141A14

~

A0151A15

40

~

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PAY

PCO
PC1
PC2
-

CSI/A19

21
20

19
19

14
11
10

8

INAi

±-

5

~
4.7KO

$<"<~

4.7KO

-

~

BHE/PSEN

~

WRIVDP
AD
ALE
--

RESET

>

(~~~RED

~+5V

- -

l-

PORT 1
110 PINS

GNO GNO

~
y4

I---<:

' ------"
~

'------"

______________________________ f===E_______________________________

2-23

PS0301

Absolute
Maximum
Ratings'9

Symbol

Parameter

Condition

Min

Max

Unit

CERDIP

-65

+ 150

PLASTIC

-65

+ 125

Voltage on any Pin

With Respect to GND

-0.6

+7

V

Vpp

Programming
Supply Voltage

With Respect to GND

-0.6

+14

V

Vcc

Supply Voltage

With Respect to GND

-0.6

TSTG

Storage Temperature

ESD Protection

DC

+7

V

>2000

V

NOTE: 19. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.

Operating Range
Range
Commercial
Industrial
Military

Recommended
Operating
Conditions

DC
Characteristics

Symbol
vee
V1H
V 1L

Symbol
VOL

VOH

ISB1
ISB2

lee1

Temperature

Vee

ODC to + 70 DC
_40DC to + 85 DC

+5V
+5V

-55 DC to + 125°C

+5V

Parameter
Supply Voltage
High-level Input Voltage
Low-level Input Voltage

Tolerance

Vee = 4.5 V to 5.5 V
Vee = 4.5 V to 5.5 V

Output Low Voltage

Output High Voltage

-20

±10%

±10%

±10%

±10%

± 10%

±10%

Min

Typ

Max Unit

4.5
2
0

5

±5%

Conditions

Parameter

-15

-12

Conditions

Min

5.5
Vee
0.8

Typ Max Unit

IOL = 20 f..lA
Vee =4.5 V

0.01

0.1

IOL=8mA
Vee=4.5V

0.15

0.45

V

IOH = -20 f..lA
Vee = 4.5 V

4.4

4.49

IOH = -2 mA
Vee = 4.5 V

2.4

3.9

V

Vee Standby Current
(CMOS) (Notes 20 and 22)

Comm'l

50

100

Ind/Mil

75

150

Vee Standby Current (TIL)
(Notes 21 and 22)

Comm'l

1.5

3

Ind/Mil

2

3.2

Comm'l (Note 24)

16

35

Comm'l (Note 25)

28

50

Ind/Mil (Note 24)

16

45

Ind/Mil (Note 25)

28

60

Active Current (CMOS)
(SRAM Not Selected)
(Notes 20 and 23)

V
V
V

f..lA
mA

mA

-----------------------------------~~~----------------------------------2-24

P50301

DC
Characteristics
(Cont.)

Symbol

Parameter
Active Current (CMOS)
(SRAM Block Selected)
(Notes 20 and 23)

ICC2

Active Current (TTL)
ICC3

(SRAM Not Selected)
(Notes 21 and 23)
Active Current (TTL)

ICC4

(SRAM Block Selected)
(Notes 21 and 23)

Min Typ Max Unit

Conditions
Comm'l Note 24

47

80

Comm'l Note 25

59

95

Ind/Mil (Note 24)

47

100

Ind/Mil (Note 25)

59

115

Comm'l (Note 24)

36

65

Comm'l (Note 25)

58

80

Ind/Mil (Note 24)

36

80

Ind/Mii (Note 25)

58

95

Comm'l (Note 24)

67

105

Comm'l (Note 25)

79

120

Ind/Mil (Note 24)

67

130

79

145

Ind/Mil (Note 25)

III

Input Leakage Current

V 1N = 5.5 V or GND

-1

±0.1

1

ILO

Output Leakage Current

VOUT = 5.5 V or GND

-10

±5

10

rnA

rnA

rnA

IlA

NOTE: 20. CMOS inputs: GND ± 0.3 V or Vcc ± 0,3V.
TTL inputs: V 1L ~ 0.8 V, V 1H ~ 2.0 V.
CSI/A19 is high in a power-down configuration mode.
AC power component is 3.5 mA/MHz (power = AC + DC).
Ten (10) PAD product terms active. (Add 380 J.lA per product term, typical, or 480 I1A
per product term maximum.)
25. Forty-one (41) PAD product terms active.

21.
22.
23.
24.

AC
Characteristics

Symbol

Parameter

-12
-15
-20
Unit
Min Max Min Max Min Max

T1

ALE or AS Pulse Width

30

40

T2

Address Set-up Time

5

10

15

T3

Address Hold Time

13

15

25

T4

ALE or AS Trailing Edge to
Leading Edge of Read

12

15

20

T5

ALE Valid to Data Valid

T6

Address Valid to Data Valid

120

150

200

T7

CSI Active to Data Valid
Leading Edge of Read to
Data Valid

150

160

200

38

55

60

T8
T9

Read Data Hold Time

T10

Trailing Edge of Read to
Data High-Z

T11

Trailing Edge of ALE or AS
to Leading Edge of Write

140

170

0

220

0

15

45
20

RD, E, or PSEI'J Pulse VVidth

~5

EO

75

WR Pulse Width

25

35

45

T13

Trailing Edge of Write or
Read to Leading Edge
of ALE or AS

20

30

40

T14

Address Valid to Trailing
Edge of Write

120

150

200

T12
T12A

ns

0
40

35
12

50

-----------------------------------~~~~~-----------------------------------

2-25

•

PS0301

AC
Characteristics
(Cont.)

Symbol

-12
-15
-20
Unit
Min Max Min Max Min Max

Parameter

T15

CSI Active to Trailing
Edge of Write

130

160

210

T16

Write Data Set-up Time

20

30

40

T17

Write Data Hold Time

5

10

15

T18

Port Input Set-up Time

30

35

45

T19

Port Input Hold Time

0

0

0

T20

Trailing Edge of Write to
Port Output Valid

40

50

60

T21

ADi 26 or Control to
CSOi 27 Valid

6

35

6

35

5

45

T22

ADi 26 or Control to
CSOi 27 Invalid

5

35

4

35

4

45

Track Mode Address
Propagation Delay:
T23

• CSADOUT1 Already True or:
• CSADOUT1 Becomes
True During ALE or AS

T24

Track Mode Address
Hold Time

T25

Track Mode Read
Propagation Delay

T26

Track Mode Read Hold Time

T27

Track Mode Write Cycle Data
Propagation Delay

T28

Track Mode Write Cycle Write
to Data Propagation Delay

8

T29

Hold Time of Port A Valid
During Write CSOi Trailing
Edge

2

22

22

28

33

40

50

15
29

T30

CSI Active to CSOi

T31

CSI Inactive to CSOi

T32

Direct PAD Input

T33

27

Active
27

Inactive

Hold Time

11

29

29
10

20
30

29

35
10

20
7

40

4

35
30

7

55

4

9

45

9

45

8

60

9

45

9

45

8

60

10

12

15

RIW Active to E High

20

30

40

T34

E Low to RIW Inactive

20

30

40

T35

AS Inactive to E High

15

20

25

28

ns

27

15

NOTES: 26. ADi = any address line.
27. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or
through Port C (CS8-CS10).
28. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent
A19, RDIE, WR or R/W, transparent PCO-PC2, ALE (or AS).

-----------------------------------~~~----------------------------------2-26

PSD301

Figure 13.
Timing of a·Bit
Multiplexed
Address/Data Bus,
CRRWR = 0

~

-

READ CYCLE

_

~

__

32~

WRITE CYCLE

--

_
.....

32~~iOOo\l\J\l

~______~______~~~~~~____~~________+4~'X~'X~I~X:~X:~X:~X

CSI/A19
asCSI

7

15
36

1_ 1-32

..... 1--32

wI7\.

v

Direct( 29l
~
IVVV 'vvX
PAD Input h ~1'-_ST_A_B_L_E_IN_P_U_T____+-+-r~~~..::S::.T:.AB~L~E:.:I,:::N:.,.P~UT:...-+-+.jIIA'\,j'A~'~
A'.JY.
A, A~
14

Multiplexed (30 IV\
x:1r------b~7O'i7d~~7\l\Jr_------_1t1Ol:JdA.
Yf,-__

~ l:.:j ~
r-

IL
r,t====35=====!i-_~~1

,.Jr

--'

12 .....--..

33

34

RolE as E +-I-_ _ _-+-__~J

-

34

WRIVPP or m~X7i.X7i.X7iXJ'X\}:\}X:utxr---t----jt----,t-V~
XX7i.X7i.X7iX
:N

Rm as R/W

~
~

-2

~MIJ£.~------.jf----'1
20
i-=-

Any of PAO- \\AJ~7\}\J\}'\7'\:7\li7\ll-~=:_:_----,1iA;k7\:7\}\J\}'\7'\:7\li1\JO\J1tA7'J._:JjO\J~:::-:-=-=
PA7asi/OPin X XXXXXXXXX
INPUT
!XXXXXXX XXXXXYXX XY OUTPUT

Any of PBO- \ J\~1\JO\J1tA7\liJ'\J\Ir-=~-\l~1\JO\J1tA7'J.J'\J\7\;~7\}\J\}\7\;~Ir:==-=
PB7asi/OPin X, XXXXXX
X
INPUT
:)(IXXXxxxXXXXXx'YYYYYYY OUTPUT

Any of PAOPA7 Pins -

~

~

-r,-----A-D-D-R-ES-S-A--------

WRITTEN
DATA

-

hILf

--.J

-,
35

orAS

12

!'-r---'

33

33

32-

xxx x :XXX

WRIVPP or

Rm as RiiN

~

~

-{

AoR'\

DATA
IN

gj[J..J

_ _ (31,34I
CSOi

29.
30.
31.
32.
33.
34.
35.

36

~

A

f-

xx xx

.HX

_23 .:..
PAD-PA7

I

\

1/

RD/E as E

Notes for
Timing Diagrams

12

35

_

1=-32

23

H

~

--

"ADR\

~

-

27_

..Qb!Jj

~

DATA
OUT

~

~

~

Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E, WR or
R/w' transparent PCO-PC2, ALE and A11/AD11-A15/AD15 in non-multiplexed modes.
Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS):
AO/ADO-A15/AD15, CSIIA19 as ALE dependent A19, ALE dependent PCO-PC2.
CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or through
Port C (CS8-CS10).
CSADOUT1, which internally enables the address transfer to Port A, should be derived only from direct PAD
input signals, otherwise the address propagation delay is slowed down.
CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively, can be
derived from any combination of direct PAD inputs and multiplexed PAD inputs.
The write operation signals are included in the CSOi expression.
Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE
(or AS) in the multiplexed modes: A11/AD11-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent
PCO-PC2.
CSOi product terms can include any of the PAD input signals shown in Figure 3, except for reset and CSI.

!"iEE

~=

-----------------------------------------~~=----------------------------------------

2-36

==-'='~

==

PSD301

Table 14.
Pin
Capacitance S7

Symbol
CIN
COUT
CvPp

Parameter

Conditions Typical" Max Units

Capacitance (for input pins only)
Capacitance (for inpuVoutput pins)
Capacitance (for WRNpp or RIWNpp)

VIN = 0 V

4

6

pF

VOUT= 0 V
Vpp = 0 V

8

12

pF

18

25

pF

NOTES: 37. This parameter is only sampled and is not 100% tested.

38. Typical values are for TA = 25°C and nominal supply voltages.

Figure 24.
AC Testing
Input/Output
Waveform

~

3· 0 V - Y
0V

---.1\

•

TEST POINT -- ~

Figure 25.
AC Testing
Load Circuit

2,;.!1.1..Y

<:.

~ 1950

DEVICE
UNDER
TEST

I

....r..... CL =30pF

_

Erasure and
Programming

To clear all locations of their programmed
contents, expose the device to an ultraviolet light source. A dosage of
15 W-second/cm2 is required. This dosage
can be obtained with exposure to a
wavelength of 2537 A and intensity of
12000 IlW/cm2 for 15 to 20 minutes. The
device should be about 1 inch from the
source, and all filters should be removed
from the UV light source prior to erasure.
The PSD301 and similar devices will erase
with light sources having wavelengths
shorter than 4000 A. Although the erasure
times will be much longer than with UV
sources at 2537 A, exposure to fluorescent
light and sunlight eventually erases the

(INCLUDING
SCOPEANDJIG
CAPACITANCE)

device. For maximum system reliability,
these sources should be avoided. If used in
such an environment, the package
windows should be covered by an opaque
substance.
Upon delivery from WSI, or after each
erasure, the PSD301 device has all bits in
the PAD and EPROM in the "1" or high
state. The configuration bits are in the "0"
or low state. The code, configuration, and
PAD MAP data are loaded through the
procedure of programming
Information for programming the device is
available directly from WSI. Please contact
your local sales representative.

-----------------------------------;JrJrJF~----------------------------------,.,~.

2-37

PSD301

PS0301
Pin Assignments

Name
BHEIPSEN
WRNppor RiW
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
GND
ALE orAS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
RD/E
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD10/A10
GND
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
PCO
PC1
PC2
A19/CSI

Vee

44-Pin
PLOCC/
CLOCC
Package

44-Pin
CPGA
Package

52-Pin
PQFP
Package

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

A5
A4
B4
A3
B3
A2
B2
B1
C2
C1
02
01
E1
E2
F1
F2
G1
G2
H2
G3
H3
G4
H4
H5
G5
H6
G6
H7
G7
Ga
F7
Fa
E7
Ea
Da
07
Ca
C7
Ba
B7
A7
B6
A6
B5

46
47
48
49
50
51
2
3
4
5
6
7
8
9

10
11
12
15
16
17
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
36
37
38
41
42
43
44
45

-------------------------------~~~-----------------------------2-38
----

PSD30f

Package
Information
Figure 26.
Drawing l4 --:
44 Pin Ceramic
Leaded Chip
Carrier (ClDCC)
with Window
(Package Type l)

~jUUUUUUUUUU

39 AD15/A15

PB4

7

PB3

8

38 AD/14/A14

PB2

9

37 AD13/A13

o

PB1 10
PBO 11
GND 12

36 AD12/A12
35 AD11/A11
34 GND
33 AD10/A10
32 AD9/A9
31 ADS/AS
30 AD7/A7
29 AD6/A6

Figure 27.
Drawing J2 -:44·Pin PlastiC
leaded Chip
Carrier (PlDCC)
(Package Type J)
7

uuuu u Uu uu u UC::.

PB3

8

,....
:-- ..

39 AD14/A14

PB2

9

C::.

37 AD13/A13

:-:.:'.

36 AD121A12

PB4

C::.
C::.
C::.
C::.
C::.

- - - - - WI;

39 AD15/A15

35 AD11/A11
34 GND
33 AD10/A10
32 AD9/A9
31 AD8/ A8

:-:::.

30 AD7/ A7

C::.

29 AD6/A6

--------~2-39

•

PSD301

Figure 28.
OrawingQ252-PinPQFP
(Package Type QJ

I~

II:

IZ

o~ W

II> co
o m
m

Z

NC

1

Il.

Il.

IW

a. (/)
~a. ~

~ ~ I~ I~

o

PB4

2

38 AD15/A15

PB3

3

37 AD14/A14

PB2

4

36 AD13/A13

PB1

5

35 AD12/A12

PBO

6

GND

7

ALE or AS

8

PA7

9

31 AD9/A9

PA6 10

30 AD8/A8

PAS 11

29 AD7/A7

PA4 12

28 AD6/A6

32 AD10/A10

27 NC

NC 13

"=!I' It)
,....
,.... CD
,.... ....
,...
(J

Z

('I')

(\I

,....

2000

V

ESD Protection

NOTE: 15. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.

Operating
Range

Range

Temperature

Commercial

Recommended
Operating
Conditions

DC

Characteristics

Tolerance

Vee

-12

-15

-20

±5%

0° C to +70°C

+5V

±10%

± 10%

Industrial

-40°C to +80°C

+5V

± 10%

± 10%

Military

-55°C to + 125°C

+5V

± 10%

± 10%

Symbol

Parameter

Conditions

Min

Typ Max Unit

vcc

Supply Voltage

-12 Version

4.75

5

5.25

V

Vee
V 1H

Supply Voltage

-15/-20 Versions

4.5

5

5.5

V

High-level Input Voltage

Vee = 4.5 V to 5.5 V

2

V1L

Low-level Input Voltage

Vee = 4.5 V to 5.5 V

0

Symbol
VOL

VOH

Parameter
Output Low Voltage

Output High Voltage

Conditions

V
0.8

Min Typ Max Unit

IOL = 20 IlA
Vee=4.5V

0.01

0.1

IOL = 8 mA
Vee=4.5V

0.15

0.45

V

IOH = -20 IlA
Vee=4.5V

4.4

4.49

IOH =-2 mA
Vee=4.5V

2.4

3.9

V

ISB1

Vee Standby Current
(CMOS) (Notes 16 and 18)

Comm'l

50

100

Ind/Mil

75

150

Vee Standby Current
(TTL) (Notes 17 and 18)

Comm'l

1.5

3

ISB2

Ind/Mil

2

3.2

Active Current (CMOS)
lee1

(SRAM Not Selected)
(Notes 16 and 19)

V

Comm'l (Note 20)

16

35

Comm'l (Note 21)

28

50

Ind/Mil (Notes 20)

16

45

Ind/Mil (Notes 21)

28

60

IlA
mA

mA

-----------------------------------f#:AF:----------------------------------=
=,",=,EIF

2-67

•

PSD311

DC
Characteristics
(Cont.)

Symbol

Parameter

Conditions

Active Current (CMOS)
(SRAM Block Selected)

ICC2

(Notes 16 and 19)

ICC3

Min Typ Max Unit

Comm'l (Note 20)

47

80

Comm'l (Note 21)

59

95

Ind/Mil (Note 20)

47

100

Ind/Mil (Note 21)

59

115

Active Current (TTL)

Comm'l (Note 20)

36

65

(SRAM Not Selected)

Comm'l (Note 21)

58

80

(Notes 17 and 19)

Ind/Mil (Note 20)

36

80

Ind/Mil (Note 21)

58

95

Active Current (TTL)

Comm'l (Note 20)

67

105

(SRAM Block Selected)

Comm'l (Note 21)

79

120

(Notes 17 and 19)

Ind/Mil (Note 20)

67

130

79

145

III

Input Leakage Current

V 1N

ILO

Output Leakage Current

ICC4

Ind/Mil (Note 21)

NOTE:

AC
Characteristics
(See Timing
Diagrams)

= 5.5 V or GND
VO UT = 5.5 V or GND

-1

± 0.1

1

-10

±5

10

CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
TTL inputs: V 1L ::; 0.8 V, V1H ~ 2.0 V.
CSI/A19 is high and the part is in a power-down configuration mode.
AC power component is 3.0 rnA/MHz (power = AC + DC).
Ten (10) PAD product terms active. (Add 380 I1A per product term, typical, or 480
per product term maximum.)
21. Forty-one (41) PAD product terms active.

16.
17.
18.
19.
20.

Symbol

Parameter

Min

-12
Max

-15
Min Max

ALE or AS Pulse Width

30

40

T2

Address Set-up Time

5

10

15

T3

Address Hold Time

13

15

25

T4

ALE or AS Trailing Edge
to Leading Edge of Read

12

15

20

T5

ALE Valid to Data Valid

140

170

220

T6

Address Valid to
Data Valid

T8

CSI Active to Data Valid
Leading Edge of Read to
Data Valid

150

200

150

160

200

38

55

60

T9

Read Data Hold Time

T10

Trailing Edge of Read to
Data High-Z

T11

Trailing Edge of ALE
or AS to Leading
Edge of Write

12

15

20

T12

RD,E,PSEN
Pulse Width

45

60

75

T12A

40

!!A

45

WR Pulse Width

25

35

45

T13

Trailing Edge of Write or
Read to Leading Edge
of ALE or AS

20

30

40

T14

Address Valid to Trailing
Edge of Write

120

150

200

!i"EiiF BF§

I-lA

ns

0

0
35

mA

50

120

0

mA

-20
Unit
Min Max

T1

T7

mA

-----------------------------------~~;-----------------------------------

2-68

PSD311

AC
Characteristics
(Cont.)

Symbol

Parameter

-12
-15
-20
Unit
Min Max Min Max Min Max

T15

CSI Active to Trailing
Edge of Write

130

160

210

T16

Write Data Set-up Time

20

30

40

T17

Write Data Hold Time

5

10

15

T18

Port Input Set-up Time

30

35

45

T19

Port Input Hold Time

0

0

0

T20

Trailing Edge of Write
to Port Output Valid

40

50

60

T21

ADi or Control to
CSOi Valid

6

35

6

35

5

45

T22

ADi or Control to
CSOi Invalid

5

35

4

35

4

45

T23

Track Mode Address
Propagation Delay:
CSADOUT1 Already True

22

22

28

Track Mode Address
Propagation Delay:
CSADOUT1 Becomes
True During ALE or AS

33

40

50

T23A

T24

Track Mode Address
Holding Time

T25

Track Mode Read
Propagation Delay

T26

Track Mode Read
Hold Time

T27

Track Mode Write Cycle
Data Propagation Delay

T28

Track Mode Write Cycle
Write to Data Propagation
Delay

8

T29

Hold Time of Port A Valid
During Write CSOi
Trailing Edge

2

T30

CSI Active to CSOi Active

9

45

9

45

8

60

T31

CSllnactive to CSOi
Inactive

9

45

9

45

8

60

T32

Direct PAD Input as
Hold Time

10

12

15

T33

R/W Active to E or
OS Start

20

30

40

T34

E or End to R/W

20

30

40

T35

AS Inactive to E High

15

20

25

15

15
29

29
11

29

10

20

30

27

29

40

4

ns
35

10

20

7

II

35
30

7

55

4

NOTES: 22. ADi = any address line.
23. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or
through Port C (CS8-CS10).
24. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent
A19, RD/E, WR or R/Vii, transparent PCO-PC2, ALE (or AS).
25. Control signals RD/E or WR or R/W.

-------------------------------------~~~~-----------------------------------2-69

PS0311

Figure 13.
Timing of 8-Bit
Multiplexed
Address/Data
Bus, CRRWR =0

...

READ CYCLE

.. ....

-~
32

---,
CS I/A19
as CSI

7

WRITE CYCLE
32

-

XX .XXXX
15

-

32

Direct (26)
PAD In put

.:z: 00(

ISTABLE INPUT
6

Multiplex ed (27)
Inp uts

X
~

AOIADOA7IAD7
Active High
ALE ,

~ ~.

I DATA

-

\ OUT

3
4

Active Low ,
ALE
'------1

f4~
RD/EasRD

3

~

~
~

)--·1

DATA
IN

~

P-SEN

\

L

I--'

-'

WRIVpp or
a sWR

Riiiii

I\if

13

~

~

19

f+-1!!Any of PAOPA7 as II Pin

~
,

Any of PBOPB7 as II Pin

\
,..

Any of PAOPA7 Pins
as Ad dress
Outputs

I

11

~

o

~

:x

-'

5

o

~

IXXX XXX

XIJ XMJ.v

ADDRESS B
2_

.~

32

14

14

~: r-

81-

r~

STABLE INPUT

~

ADDRESS A
2

~

XJ..X'/\I..}.. K} l\I\A

6

14-

20

~

~

fY,'{'X'xY,\iY'y,'l

INPUT

~

xxxxxxxxxxxxxxx')0 YXl

OUTPUT

XXXXXXXXX

INPUT

J IXXXXXXXXXXXXXXXXXJCJ\.

OUTPUT

~.

~
~I

rEADDRESS B

ADDRESS A

See referenced notes on page 2-75.

==-~~E
---------------------------------;-------------------------------------

2-70

=",,=,~E

PS0311

Figure 14.
Timing of 8-Bit
Multiplexed
Address/Data
Bus, CRRWR = 1

-

----,

READ CYCLE

CS I/A19
a sCSI

Direct(26)
PAD Input

Multiplex ed (27)
Inp uts

7

A7IAD7

X
~
-x:

Active High
AS

I-

15

- lAMMXX
32

I-

I-

STABLE INPUT
6

~

STABLE INPUT
14

DATA
\ OUT

-

3

Irh

14

~

4

~>~

3

..:-.
35
12

33

~

DATA
IN

~

h

~~

Active Low'
AS
~f---'

'>-

ADDRESSB

8~

35

-'

'---

F1 rL
VIr-

'34

I

RD/E as E
5

-

\

asDS
WRIVp po.!.,.
RiW as R/W

~r--

33

34

\

II-I-J

~

...::..

~
Ir-

,XXXXX'

IXXXX:XXX
~

~

~

Any of PAOPA7 as 1/0 Pin

rI.Y.Y.'J.'iY."

INPUT

() XXXxxxxxxx"l(')()('Xxn ''I.'f'

OUTPUT

Any of PBDPB7 as 1/0 Pin

:XXXXXXXX)(X,

INPUT

xxxxxxxxxffl)()(X)()()()

OUTPUT

Any of PADPA7 Pins
as Add ress
Outputs

•

xxxx 'lXtYJr-~

xxxxxx n x'l.'l

ADDRESS A

..
-- ~lXXXX
32

1

--,
2

WRITE CYCLE

32

6

ADIADD-

.. ..

-~
-~
32

~.

I

~
ADDRESSA

ADDRESSB

See referenced notes on page 2-75.

----------------------------~~=---------------------------

2-71

PS0311

Figure 15.
Timing of 8-Bit
Data NonMultiplexed
Address/Data
Bus, CRRWR = 0

.

READ CYCLE

-~
32

:-----.
CS I/A19
a sCSI

Dir ect (26)
PAD In put

.:E 00

1-

X

PAD -PA7

6

Active Low
ALE

IDATA
3

r~

4

. ..:....

-- Si-

- IXXX

.xX'!..

I-

32

r-~

14

~

DATA

IN

2_

3

~

~

xx:

~,-

'-f---I

.~

~

--'

'--

~

5

WRlVp par

RiWasWR

X)( IXXXXXXXXX

I

INPUT

-

J

13

~
~

L

11

,

-

o

XXX

XXXX XXXX

.2-.

RD/Ea sRD

Any of PBDPB7 as II Pin

STABLE INPUT

32

~
\ OUT

2

Active High
ALE I

~~

IXXXXXX U IXXX

'
-.l

IXXX

14

STABLE INPUT

Multiplex ed (27)
_
Inpu ts

- VXX) XXXY.

STABLE INPUT

6

AD -A15

..

32

15

~ OC

STABLE INPUT

WRITE CYCLE

I-

I

7

.:E ooc

...

~

1'--'

20

IXXXXXXXXXXXXXXX'1.J\1.:A

OUTPUT

See referenced notes on page 2-75.

----------------------------------,jrjrAF~--------------------------------i!!!F'I!!Ii!!!!iiFE

2-72

P80311

Figure 16
Timing of 8-Bit
Data NonMultiplexed
Address/Data
Bus, CRRWR = 1

REAOCYCLE

.. ..

.=---'\

CS I/A19
asCSI

Oi rect (26)
PAO In put

7

.:x: 00(

6

AO -A15

Multiplex ed (27)
Inputs

.:x: 00

STABLE INPUT

I-

X
6

Active High
ALE I
Active Low,
ALE

XX [XXX)(

DATA
OUT
2

--

3

r---.

4

14

~~

STABLE INPUT

32

~

~
35

h

16

~

~

~

Ir-

/

.,..--

L

35

~

~

33

34

X

~

34

I

ROlE as E
5

as OS

~

" I-'

WRN pp 2.!:

V~

RiWas R/W

"f:'. rYX~

Any of PBOPB7 as II Pin I

o

3

1"-""""'\

12

I32

DATA
IN

~

.. f2-,.

33

-

[XXX :XXX

:xxx XXXX

14

8~

~r--'

1m v:x'iY..

STABLE INPUT

~

PAO -PA7 '

I-

15

[XXxxxY ~ )00(;

~

--'

32

-

~ P<

STABLE INPUT

..

WRITE CYCLE

-~
32

'---'
XXX X)(

~
INPUT

~

~

-

r

20

II~XXXXM

OUTPUT

See referenced notes on page 2-75.

----------------------------------~~~--------------------------------2-73

•

PSD311

Figure 17.
Chip-Select
Output Timing

~

30

CSI/A19
as CSI

1

Direct PAD (26)
Input

INPUT STABLE

-'

Multiplexed (32)
PAD Inputs

X

XXXXXXX X 'XX
2

ALE
(Multiplexed
Mode Only)

I

3

-I

Ir----

II

If. .2...

or ALE
(Multiplexed
Mode Only)

I\- ~
22

21

I+- 1,----

CSOi (28,33)

.

FIgure 18.
PortA as
ADD-AD7 Timing
(Track Mode),
CRRWR=O

-

READ CYCLE
Direct (26,29)
PAD
Input

Multiplexed (30,32)
PAD Inputs

t--

WRITE CYCLE

INPUT STABLE

J~

XXXXXX)( IX D(

INPUT STABLE
2

AD/ADDA7/AD7

T

3

ADDRESS

orALE

I} - -

XXXXXX,XX

INPUT STABLE
2

ki~

I

1
ADDRESS)--~ WRITIEN
DATA

READ
DATA

Iff---,

f4f-2.0

I"'~

~f--J

~+_..J

4

WRNpp or
RiWasWR
....

PAD-PA7

I
Y

1- P2]:

V\..\....J

12

-

-I

~
23~

2i-

DATA
IN

I
\

I

)-

12

11

~

-23

-~

:X

I

3

h

RD/Eas RD

t--

OOnrV"VT
INPUT STABLE

INPUT STABLE

V\I\IV\

Input
Multiplexed
PAD Inputs

(30,32)

xx;

INPUT STABLE

XXXXXXX It

I
I

AO/ADOA7/AD7

AS

~X

INPUT STABLE

~I- 26~

,x

XXXXXXXX
I

-j-~-;~~~--~
__-+-{~~
ADDRESS
~1~W~RI~n~E~N~
ADDRESS
~TA ~I'--+________+,I
DATA
_2~
~~

~~

IL---------+-~~

J

r- r2+

1+ --.:.

1\

1L----------+-r~1

~

orAS

RDIE as E

RDIE as DS
WR/vpp or
RiWas RNV

xxx :xXXX
24

~
-23

PAD-PA7

CSO;

Notes for
Timing
Diagrams

ADR
OUT

(28,31)

26, Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19,RD/E,
WR or Riw, transparent PCO-PC2, ALE in non-multiplexed modes.
27. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS):
AO/ADO-A7/AD7, CSI/A19 as ALE dependent A19, ALE dependent PCO-PC2,
28. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or through
Port C (CS8-CS1 0),
29. CSADOUT1, which internally enables the address transfer to Port A, should be derived only from
direct PAD input signals, otherwise the address propagation delay is slowed down,
30. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively,
can be derived from any combination ot direct PAD inputs and muitiplexed PAD Inputs,
31, The write operation signals are included in the CSOi expression,
32, Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE
(or AS) in the multiplexed modes: All-A15, CSI/A19 as ALE dependent A19, ALE dependent
PCO-PC2,
33, CSOi product terms can include any of the PAD input signals shown in Figure 3, except for
reset and CSI.

---------------------------------------r~~~:-------------------------------------5?$FEF ==
2-75

•

PSD311

Table 12
Pin
Capacitance 34

Symbol

Conditions Typical35 Max Units

Parameter

CIN

Capacitance (for input pins only)

VIN = 0 V

4

6

pF

COUT

Capacitance (for inpuVoutput pins)

VOUT= 0 V

8

12

pF

CvPP

Capacitance (for WR/vpp or RIW/Vpp)

Vpp = 0 V

18

25

pF

NOTES: 34. This parameter is only sampled and is not 100% tested.
35. Typical values are for TA = 25°C and nominal supply voltages.

Figure 20.
AC Testing
Input/Output
Waveform

3· 0 V
0V

-V
-A

TEST POINT -

Figure 21.
AC Testing
Load Circuit

v-:-:

~V

2.01 V

~ 1950
DEVICE
UNDER

TEST

I

......... C L = 30 pF

_

Erasure and
Programming

To clear all locations of their programmed
contents, expose the device to ultra-violet
light source. A dosage of 15 W second/cm2
is required. This dosage can be obtained
with exposure to a wavelength of 2537 A
and intensity of 12000 ~W/cm2 for 15 to 20
minutes. The device should be about 1
inch from the source, and all filters should
be removed from the UV light source prior
to erasure.
The PSD311 and similar devices will erase
with light sources having wavelengths
shorter than 4000 A. Although the erasure
times will be much longer than with UV
sources at 2537 A, exposure to fluorescent
light and sunlight eventually erases the
device. For maximum system reliability,

(INCLUDING
SCOPEANDJIG
CAPACITANCE)

these sources should be avoided. If used in
such an environment, the package
windows should be covered by an opaque
substance.
Upon delivery from WSI, or after each
erasure, the PSD311 device has all bits in
the PAD and EPROM in the "1" or high
state. The configuration bits are in the "0"
or low state. The code, configuration, and
PAD MAP data are loaded through the
procedure of programming
Information for programming the device is
available directly from WSI. Please contact
you r local sales representative.

_____________________________________ fAfjfjF=_____________________________________

2-76

;';EE

PSD311

Pin
Assignments

Name
PSEN
WRlVpp or Riw
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
GND
ALE or AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
RD/E
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
A8
A9
A10
GND
A11
A12
A13
A14
A15
PCO
PC1
PC2
A19/CSI
Vcc

44-Pin
PLDCC/
CLDCC
Package

44-Pin
CPGA
Package

52-Pin
PQFP
Package

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

As
A4
B4
A3
B3
A2
B2
B1
C2
C1
02
01
E1
E2
F1
F2
G1
G2
H2
G3
H3
G4
H4
HS
Gs
HS
Gs
H7
G7
Gs
F7
Fs
E7
Es
Os
07
Cs
C7
Bs
B7
A7
Bs
AS
Bs

46
47
48
49
50
51
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
36
37
38
41
42
43
44
45

NOTE: 36. Pins 1, 13, 14, 26, 27, 39, 40, and 52 are No Connect.

--------------------------------~Jr~-------------------------------2-77

•

PSD311

Package
Information

13:

0:
(;

t-

o.
o.

Figure 22
DrawingL444 Pin Ceramic
Leaded Chip
Carrier (CLDCC)
with Window
(Package Type

D..

'"

7

PB3

8

PB2

9

D..

It>

0
D..

~

i'.. ,'

0

0
D..

0
D..

:;;

0

,i.. ,:

uU'

: : : :
:--:
Lj

.....

39 A15
38 A14

o

PB1 10
PBO 11

L)

'"

. '" '" ... ..'" '".. ..

'"
D..

/ UU
PB4

I~

IZ

> w >()"m
10:
::;;c
~ 3: ~

r- w
al al al 00

It)

GND 12
ALE or AS 13
PA7 14
PA6 15

.....

37 A13

.....

36 A12

.. __ .

35 A11

.. __ .

34 GND

... __

33 A10
32 A9

.....

31 A8

PA5 16

30 AD7/A7

PA417

.. __ .

..

.

29 AD6/A6

r- eo
'"Iii '" '"'"w '"'" '" '" '"'" '" '"
'"D.. '"D.. D.. D.. II:c ~ ~ '"~ '"~ ~ ~
c C c '"
c c c
0

~ ~

c(

~

0
c(

c(

It>

0

It)

c(

It>

(TOP VIEW)

Figure 23.
DrawingJ244-Pin Plastic
Leaded Chip
Carrier (PLDCC)
(Package Type
J)

c(

c(

c(

I~

>""

c(

c(

c(

'"0D..

0D..

0
D..

:;;

0

13:
0:
(;
t-

It)

al
D..

'"
/
I

.--

o.
o.

~

7

PB3

8

.. _--'

PB2

9

----"

PB110

____ -'

I~
m

0

. '" '" .. .'" '". .

'"
al
D..

D..

It>

II:

I~

~

~

t.i t.! t.; tj

____ "

PB4

PBO 11

w
r- oo
al w

L! t.! tj Lj t.; Lj P
-----

___ oJ

._ ....

GND 12
ALE or AS 13

____ oJ

PA7 14

----'

----- b 31 A8
----- ~ 30 AD7/A7

PA6 15 L ._._ ...
PA5 16

I

PA4 171

___ -'

r-1 f"1 r-1 r-1 r-1 ["1 :- r-1 r-1 r-l r-1
~

~ ~

0

'"~

'"c(D.. '"c(D..

D..

(TOP VIEW)

2-78

39 A15

P39 A14
P37 A13
----- P36 A12
..... P35 A11
----- P34 GND
----- P33 A10
_._-- P32 A9
_._--

N
0
c(

D..

..

~'='-

-

It>

0

c(

~::

..

'"'" '"'" '" '" '"'" '"r- '"eo
cII: ~ ~ ~'" g ~ ~
c c c
c C c '"
w

c(

c(

c(

c(

It>

c(

_._-- ~ 29 AD6/A6

PSD311

Figure 24.
OrawingQ252-PinPQFP
(Package Type QJ

I~

II:

o

oz

~
~

:8
~

:n
~

tu 8: z I~
ffi I~ I»! 8 ~ ~ [) 8 0
II: > ~ > C ~ ~ ~ z

~ ~ ~ ~ ~ ~ ~ ~

:

~ ~

;

o

~

39 NC

NC

1

PB4

2

38 A15

PB3

3

37 A14

PB2

4

36 A13

PB1

5

35 A12

PBO

6

34 A11

GND

7

33 GND

ALE or AS

8

32 A10

PA7

9

31 A9

PA610

30 A8

PA511

29 AD7/A7

PA412

28 AD6/A6

•

27 NC

NC 13

(TOP VIEW)

Figure 25.
OrawingX244-PinCPGA
(Package Type XJ

2345678
A
B

C
D
E
F
G

11

000000
00000000
00
00
00
00
00
00
00
00
00000000
888888

(TOP VIEW, THROUGH PACKAGE)

--------------------------------~Jr~--------------------------------

2-79

PSD311

Ordering
Information

Part Number

Spd.
(ns)

PSD311-12J
PSD311-12L
PSD311-120
PSD311-12X
PSD311-15J
PSD311-15JI
PSD311-15L
PSD311-15L1
PSD311-15LM
PSD311-15LMB
PSD311-150
PSD311-15X
PSD311-15XI
PSD311-15XM
PSD311-15XMB
PSD311-20J
PSD311-20JI
PSD311-20L
PSD311-20Ll
PSD311-20LM
PSD311-20LMB
PSD311-200
PSD311-20X
PSD311-20XI
PSD311-20XM
PSD311-20XMB

120
120
120
120
150
150
150
150
150
150
150
150
150
150
150
200
200
200
200
200
200
200
200
200
200
200

Package
Type
44-pin
44-pin
52-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
52-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
52-pin
44-pin
44-pin
44-pin
44-pin

PLDCC
CLDCC
POFP
CPGA
PLDCC
PLDCC
CLDCC
CLDCC
CLDCC
CLDCC
POFP
CPGA
CPGA
CPGA
CPGA
PLDCC
PLDCC
CLDCC
CLDCC
CLDCC
CLDCC
POFP
CPGA
CPGA
CPGA
CPGA

WSI
Package Operating
Drawing Temperature Manufacturing
Range
Procedure
J2

L4
02
X2
J2
J2

L4
L4
L4
L4
02
X2
X2
X2
X2
J2
J2

L4
L4
L4
L4
02
X2
X2
X2
X2

Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
Commercial
Industrial
Military
Military
Commercial
Commercial
Industrial
Military
Military
Commercial
Industrail
Commercial
Industrial
Military
Military
Commercial
Commercial
Industrial
Military
Military

Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
Standard
MIL -STD-883C
Standard
Standard
Standard
Standard
Standard
MIL -STD-883C
Standard
Standard
Standard
Standard
MIL-STD-883C

-----------------------------------r~=~=----------------------------------
=",-JEg

2-80

=

PSD311
System
Development Tools

System
Development
Tools

The PSD311 features a complete set of
System Development Tools. These tools
provide an integrated, easy-to-use software
and hardware environment to support
PSD311 device development. To run these
tools requires an IBM-XT, -AT, or compatible computer, MS-DOS 3.1 or higher, 640K
byte RAM, and a hard disk.

Hardware
The PSD311 System Programming
Hardware consists of:

o
o
o
o

Support

WS6020 52-pin PSD311 PQFP
Package Adaptor
WS6021 44-pin LCC Package Adaptor
(for CLDCC and PLDCC packages)
WS6022 44-pin CPGA Package
Adaptor

WSI provides a complete set of quality
support services to registered System
Development Tools owners, including:

o
o

Training

WS6000 MagicPro Memory and PSD
Programmer

The MagicPro Programmer is the common
hardware platform for programming all WSI
programmable products. It consists of an
IBM-PC plug-in programmer board and a
remote socket adaptor.

Software
The PSD311 System Development
Software consists of:

o WISPER, WSI's Software Environment
o MAPLE, the PSD311 Location Editor
Software

o

MAPPRO, the Device Programming
Software

The configuration of the PSD311 device is
entered using MAPLE software. MAPPRO
software uses the MagicPro programmer
and the socket adaptor to configure the
PSD311 device, which then can be used in
the target system. The development cycle
is depicted in Figure 26.

o

24-hour Electronic Bulletin Board for
design assistance via dial-up modem.

12-month software updates
DeSign assistance from WSI field
application engineers and group
experts

WSI provides in-depth, hands-on workshops for the PSD311 device and System
Development Tools. Workshop participants
learn how to program high-performance,
programmable peripherals. Workshops are
held at the WSI facility in Fremont,
California.

-------------------------------------,JrAr~~-----------------------------------
.-1E.
2-81

•

I

PSD311

Ordering
Information System
Development
Tools

PSO-60LO

o
o
o
o
o
o

WS6021

WISPER Software
MAPLE Software
User's Manual
WSI Support
WS6000 MagicPro™ Programmer
One Package Adaptor and Two PSD311
Product Samples

o

WS6022

o

PSO-SILVER

o

o
o
o

WISPER Software
MAPLE software
User's Manual
WSI Support

Support services include:
12-month Software Update Service
Hotline to WSI Application Experts
24-hour access to WSI Electronic
Bulletin Board

o
o
o

MagicPro Programmer
IBM-PC© Plug-in Adaptor Card
Remote Socket Adaptor

WS6020

o

44-Pin CPGA Package Adaptor. Used
with the WS6000 MagicPro
Programmer.

WSISupport

WS6000

o
o
o

44-Pin LCC Package Adaptor for
CLDCC and PLDCC Packages. Used
with the WS6000 MagicPro
Programmer.

52-pin PQFP Package Adaptor. Used
with the WS6000 MagicPro
Programmer

Figure 26.
PSD311
Development
Cycle

WSI Training

o
o

Workshops at WSI, Fremont, CA
For details and scheduling, call PSD
Marketing (510) 656-5400.

IBM PLATFORM

Menu Selection

Configuration Data

Programming Data

MagicPro Hardware

-----------------------------------~aF~----------------------------------2-82

Programmable Peripheral
PS0302
Preliminary
Key Features

Programmable Microcontrol/er Peripheral
with Memory
o Single Chip Programmable Peripheral
o 512 Kbits of UV EPROM
for Microcontroller-based Applications

o

19 Individually Configurable I/O pins
that can be used as
Microcontroller I/O port expansion
Programmable Address Decoder
(PAD) I/O

-

Configurable as 64K x 8 or as 32K x 16

-

Divides into 8 equal mappable blocks
for optimized mapping

-

Block resolution is 8K x 8 or 4K x 16

-

120 ns EPROM access time, including
input latches and PAD address
decoding.

Latched address output
-

o

Open drain or CMOS
Two Programmable Arrays
(PAD A & PAD B)

-

Total of 40 Product Terms and up to
16 Inputs and 24 Outputs

-

Direct Address Decoding up to 1 Meg
address space and up to 16 Meg
with paging

-

Logic replacement

o

"No Glue" Microcontroller Chip-Set

-

Built-in address latches for multiplexed
address/data bus

-

Non-multiplexed address/data bus
mode

-

Selectable 8 or 16 bit data bus width

-

ALE and Reset polarity programmable

-

Selectable modes for read and write
control bus as RD/WR, RJW/E, or
R/W/DS

-

BHE/ pin for byte select in 16-bit mode

-

PSEN/ pin for 8051 users

o

o

16 Kbit Static RAM

-

Configurable as 2K x 8 or as 1K x 16

-

120 ns SRAM access time, including
input latches and PAD address
decoding

o

Address/Data Track Mode

-

Enables easy Interface to Shared
Resources (Mail Box SRAM) with other
Microcontrollers or a Host Processor

o

Built-In Security
Locks the PSD302 Configuration and
PAD Decoding

-

o

Available in a Variety of Packaging

-

44 Pin PLDCC and CLDCC

-

52 Pin PQFP

-

44 Pin CPGA

o
o

Simple Menu-Driven Software:
Configure the PSD302 on an IBM PC
Downward Pin and Functionally
Compatible with the PSD301

Built-In Page Logic

-

To Expand the Address Space of
Microcontrollers with Limited Address
Space Capabilities

-

Up to 16 pages

---------------------_.
Partial Listing
of
Microcontrollers
Supported

o Motorola family:

M6805, M68HC11, M68HC16,
M68000/10/20, M60008, M683XX

o

Intel family:
8031/8051,8096/8098,80186/88,
80196/98

o Signetics:
o Zilog:
o National:

------------------

SC80C451, SC80C552

l8, l80, l180
HPC16000

2-83

•

PSD302

Applications

o
o

Introduction

Product
Description

Computers (Workstations and PCs)
Fixed Disk Control, Modem, Imaging,
Laser Printer Control

o

Telecommunications
Modem, Cellular Phone, Digital PBX,
Digital Speech, FAX,
Digital Signal Processing

o

The PSD302 is the latest member in the
rapidly growing family of PSD devices. The
PSD302 is ideal for microcontroller-based
applications, where fast time-to-market,
small form factor, and low power consumptions are essential. When combined
in an 8- or 16-bit system, virtually any
microcontroller (68HC11, 8051, 8096,
16000, etc.) and the PSD302 work together
to create a very powerful chip-set solution.
This implementation provides all the

The PSD302 integrates high performance
user-configurable blocks of EPROM,
SRAM, and programmable logic technology
to provide a single chip microcontroller
interface. The major functional blocks
include two programmable logic arrays,
PAD A and PAD B, 512K bits of EPROM,
16K bits of SRAM, input latches, and
output ports. The PSD302 is ideal for applications requiring high performance, low
power, and very small form factors. These
include fixed disk control, modem, cellular
telephone, instrumentation, computer
peripherals, military and similar applications.
The PSD302 offers a unique single-chip
solution for microcontrollers that need:

o
o
o

I/O reconstruction (microcontrollers
lose at least two I/O ports when
accessing external resources).
More EPROM and SRAM than the
microcontroller's internal memory.
Chip-select, control, or latched address
lines that are otherwise implemented
discretely.

iF • •

~E

-2---84-----------------~~~

o

Industrial
Robotics, Power Line Access,
Power Line Motor
Medical Instrumentation
Hearing Aids, Monitoring Equipment,
Diagnostic Tools
Military
Missile Guidance, Radar, Sonar,
Secure Communications, RF Modems

required control and peripheral elements of
a microcontroller-based system peripheral
with no external discrete "glue" logic
required.
The solution comes complete with simple
system software development tools for integrating the PSD302 with the microcontroller. Hosted on the IBM PC platforms or
compatibles, the easy to use software
enables the designer complete freedom in
designing the system.

o
o

An interface to shared external
resources.
Expanding address space of
microcontrollers

WSI's PSD302 (shown in Figure 1) can efficiently interface with, and enhance, any 8or 16-bit microcontroller system. This is the
first solution that provides microcontrollers
with port expansion, latched addresses,
page logic, two programmable logic arrays
PAD A and PAD B, an interface to shared
resources, 512K bit EPROM, and 16K bit
SRAM on a single chip. The PSD302 does
not require any glue logic for interfacing to
any 8- or 16-bit microcontroller.
The 8051 microcontroller family can take
full advantage of the PSD302's separate
program and data address spaces. Users
of the 68HCXX family of microcontrollers
can change the functionality of the control
signals and directly connect the Rm and
E, or the RiW and DS signals. Users of 16bit microcontrollers (including the 80186,
8096, 80196, 16XXX) can use the PSD302
in a 16-bit configuration. Address and data
buses can be configured to be separate or
multiplexed, whichever is required by the
host processor.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

P50302

Product
Oiscription
(Cont.)

The flexibility of the PSD302 1/0 ports
permits interfacing to shared resources.
The arbitration can be controlled internally
by PAD A outputs. The user can assign the
following functions to these ports: standard
1/0 pins, chip-select outputs from the PAD
A and PAD B, or latched address or multiplexed low-order addressldata byte. This
enables users to design add-on systems
such as disk drives, modems, etc., that
easily interface to the host bus (e.g., IBM
PC, SCSI).

to map the 1/0 ports, eight segments of
EPROM (as 8K x 8 or as 4K x 16) and
SRAM (as 2K x 8 or as 1K x 16) anywhere
in the address space of the microcontroller.
PAD B can implement up to 4 sum-ofproduct expressions based on address
inputs and control signals.
The page register extends the accessible
address space of certain microcontrollers
from 64K to 1 M. There are 16 pages
that can serve as base address inputs to
the PAD, thereby enlarging the address
space of 16 address line processors by a
factor of 16.

The PSD302 on-chip programmable
address decoder (PAD A) enables the user

Figure 1.
P50302
Architecture

•

PAGE LOGIC
P3 PO

;

6

AD8-AD15

~

A16-A18

f::E

, - - A11-A15

[C CSI~ORT

~

r'~~~~~---+/-'----'----'-I

H

~~~

PAD A

ALE/AS
RD
WR

111LOGICIN

r----PAD B

ALE/AS

f-+

RD
13 PT.

PROG.
PORT
EXP.

..,W-,,-R'--..--.!
RESET

27 P.T.

F"'-'---L----.J
r - - - - - I - -....
EPROM

CS8CS10

PORT
C

PCO-

~
I~

~

512K BIT

~----~~----,
ES5
ES4
ES3
ES2

rPROG.
PORT
EXP.
CSOCS7 r - - - - -

1Es1~
ESO -J

r;s:;s

o---

111 +I-I-H1+]'t+11+t+t
I-++-tH:++t-ni:+\1'-++-tIt-\,-o-H
-"~E-r.. +f++1,'.1.,Hi+!;I,+Itt: i+++4-rl::+++-,ttIII++!!+!4!t--l::>-H
CSi

..

CS7/PB7

CSB/pca
eS9/pel
CS10/PC2

NOTES: 2. eSI is a power-down Signal. When high, the PAD is in stand-by mode and all its outputs
become non-active. See Tables 12 and 13.
3. RESET deselects all PAD output signals. See Tables 10 and 11.
4. A18, A17, and A16 are internally multiplexed with eS10, eS9, and eS8, respectively.
Either A18 or eS10, A17 or eS9, and A16 or eS8 can be routed to the external pins of
Port e. Port e can be configured as either input or output.

-2--9-0--~--------------------------~~~---------------------------------

P5D302

Tab/e 3.
PS0302PAOA
andS/fO
Functions

Function
PAD A and PAD 8 Inputs
CSlorA19
A16-A18
A11-A15
PO-P3
RD or E
WR or R/W
ALE
RESET

In CSI mode (when high), PAD deselects all of its outputs and enters a
power-down mode (see Tables 12 and 13). In A19 mode, it is another
input to the PAD.
These are general purpose inputs from Port C. See Figure 3, Note 4.
These are address inputs.
These are page number inputs.
This is the read pulse or enable strobe input.
This is the write pulse or R/W select signal.
This is the ALE input to the chip.
This deselects all outputs from the PAD; it can not be used in product
term equations. See Tables 10 and 11.

PAD A Outputs
ESO-ES7

These are internal chip-selects to the 8 EPROM banks. Each bank can
be located on any boundary that is a function of one product term of the
PAD address inputs.

RSO

This is an internal chip-select to the SRAM. Its base address location is
a function of one term of the PAD address inputs.

CSIOPORT

This internal chip-select selects the I/O ports. It can be placed on any
boundary that is a function of one product term of the PAD inputs. See
Tables 6 and 7.

CSADIN

This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the input
direction of Port A. CSADIN is gated externally to the PAD by the
internal read signal. When CSADIN and a read operation are active, data
presented on Port A flows out of ADO/AO-AD7/A7. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure 5.

CSADOUT1

This internal chip-select, when Port A is configured as a low-order
address/data bus in track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT1 is gated externally to the PAD by the ALE
signal. When CSADOUT1 and the ALE signal are active, the address
presented on ADO/AO-AD7/A7 flows out of Port A. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure 5.

CSADOUT2

This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT2 must include the write-cycle control
signals as part of its product term. When CSADOUT2 is active, the data
presented on ADO/AO-AD7/A7 flows out of Port A. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure 5.

PAD B Outputs
CSO-CS3

These chip-select outputs can be routed through Port B. Each of them is
a function of up to four product terms of the PAD i~~~~ ___

CS4-CS7

These chip-select outputs can be routed through Port B. Each of them is
a function of up to two product terms of the PAD inputs.

CS8-CS10

These chip-select outputs can be routed through Port C. See Figure 3,
Note 4. Each of them is a function of one product term of the PAD inputs.

-------------------------------------~~~--------------------------------~~
2-91

•

P50302

Configuration
Bits

Table 4.
PS0302
Non-Volatile
Configuration
Bits

The configuration bits shown in Table 4 are
non-volatile cells that let the user set the
device, I/O, and control functions to the
proper operational mode. Table 5 lists all
configuration bits. The configuration bits
are programmed and verified during the

Use This Bit
CDATA
CADDRDAT
CEDS
CA19/CSI

To
Set the da.ta bus width to 8 or 16 bits.
Set the address/data buses to multiplexed or non-multiplexed mode.
Determine the polarity and functionality of read and write.
Set A 19/CSI to CSI (power-down) or A 19 input.

CALE

Set the ALE polarity.

CPAF2

Set Port A either to track the low-order byte of the address/data
multiplexed bus or to select the I/O or address option.

CSECURITY
CRESET

Set the security on or off (a secured part can not be duplicated).
Set the RESET polarity.

COMB/SEP

Set PSEN and RD for combined or separate address spaces
(see Figures 8 and 9).

CPAF1
(8 Bits)

Configure each pin of Port A in multiplexed mode to be an I/O or
address out.

CPACOD
(8 Bits)

Configure each pin of Port A as an open drain or active CMOS
pull-up output.

CPBF
(8 Bits)

Configure each pin of Port B as an I/O or a chip-select output'

CPBCOD
(8 Bits)

Configure each pin of Port B as an open drain or active CMOS
pull-up output.

CPCF
(3 Bits)

Port Functions

programming phase. In operational mode,
they are not accessible. To simplify implementing a specific mode, use the WSl's
PSD302 MAPLE software to set the bits.

Configure each pin of Port C as an address input or a chip-select output.

CADDHLT

Configure pins A 16-A 19 to go through a latch or to have their
latch transparent.

CADLOG
(4 Bits)

Configure A 16-A 19 individually as logic or address inputs.

CLOT

Determine in non-multiplexed mode if address inputs are transparent
or latched.

CRRWR

Configure the polarity and control methods of read and write cycles.

The PSD302 has three I/O ports (Ports A,
B, and C) that are configurable at the bit
level. This permits great flexibility and a
high degree of customization for specific

applications. The following is a description
of each port. Figure 4 shows the pin
structure of Port A.

-------------------------------------'jfAf~~------------------------------------
i!EF!Esg ==

2-92

PS0302

Figure 4.
Port A Pin
Structure

N
T
E
R
N
A
L
WRITE DATA CK
A
OFF
D
D ...- - - - - I D R
R
I
D
"'!:!!''=---IG
A
LATCH
T ...f - - - - - I D
R
A

r-A~L~E~-~~====~

OUT

ENABLE
ADDR

MUX

•

AD 110 I

B
U
S
A
D

a

I
A
D
7

CONTROL

WRITEDIR

RESET

NOTE: 5. CMOS/OD determines whether the output is open drain or CMOS.

FigureS.
Port A Track
Mode
WRorRIW

-I
CSADIN

ROlE

PAO-PA7

ADO-AD7
INTERNAL
ALE

ALE or AS

.. •
AD8-AD15

A16-A19

LATCH A11-A15

PAD
CSADOUT2 (6)

LJI

~LJ

NOTE: 6. The expression for CSADOUT2 must include the following write operation cycle signals:
For CRRWR = 0, CSADOUT2 must include WR = O.
For CRRWR = 1, CSADOUT2 must include E = 1 and RiW = o.

-----------------------------------~~~~----------------------------------~~
2-93

PS0302

TableS.
P5D302
Configuration
Bits7,B

Configuration
Bits

No.
of Bits

CDATA

1

8-bit or 16-bit Data Bus Width
CDATA = a eight bits
CDATA = 1 sixteen bits

CADDRDAT

1

ADDRESS/DATA Multiplexed (separate buses)
CADDRDAT = 0, non-multiplexed
CADDRDAT = 1, multiplexed

CA19/CSI

1

A19 or CSI
CA 19/CSI = 0, enable power-down
CA 19/CSI = 1, enable A 19 input to PAD

CALE

1

Active HIGH or Active LOW
CALE = 0, Active high
CALE = 1, Active low

CRESET

1

Active HIGH or Active LOW
CRESET = 0, Active low RESET
CRESET = 1, Active high RESET

COMB/SEP

1

Combined or Separate Address Space
for SRAM and EPROM
a = Combined, 1 = Separate

CPAF2

1

Port A ADO-AD? (address/data multiplexed bus)
CPAF2 = 0, address or I/O on Port A
(according to CPAF1)
CPAF2 = 1, address/data multiplexed on Port A
(track mode)

CADDHLT

1

A 16-A 19 Transparent or Latched
CADDHLT = 0, Address latch transparent
CADDHLT = 1, Address latched (ALE dependent)

CSECURITY

1

SECURITY On/Off
CSECURITY = 0, off
CSECURITY = 1, on

1

AO-A 15 Address Inputs are transparent or
ALE-dependent in non-multiplexed modes
CLOT = 0, transparent
CLOT = 1 , ALE-dependent

CRRWR
CEDS

2

Determine the polarity and control methods of
read and write cycles.
CEDS CRRWR
R12-and WR active low pulses
a
a
1
R/W status and high,E,pulse
a
1
1
R/W status and low DS pulse

CPAF1

8

Port A I/O or AO-A?
CPAF1 = 0, Port A pin is I/O
CPAF1 = 1, Port A pin is Ai (0

CPACOD

8

Port A CMOS or Open Drain Output
CPACOD = 0, CMOS output
CPACOD = 1, open-drain output

CPBF

8

Port B is I/O or CSO- CS?
CPBF = 0, Port B pin is CSI (0
CPBF = 1, Port B pin is I/O

CLOT

Function

~

~

i

~

?)

i ~ ?)

----------------------------------~aF~-----------------------------------

2-94

PSD302

Table 5.
PS0302
Configuration
Bits (Cont.)

Configuration
Bits

No.
of Bits

CPBCOD

8

Port B CMOS or Open Drain
CPBCOD = 0, CMOS output
CPBCOD = 1, open-drain output

CPCF

3

Port C A 16-A 18 or CS8-CS10
CPCF = 0, Port C pin is ~16:::; i:::; 18)
CPCF = 1, Port C pin is CSI (8 < i < 10)

CADLOG

4

A 16-A 19 Address or Logic Input_
CADLOG = 0, Port C pin or A 19/CSI is
logic input
CAD LOG = 1, Port C pin or A 19/CSI
is Ai (16 < i < 19)

Total Bits

51

Function

NOTES: 7. WSI's MAPLE software will guide the user to the proper configuration choice.
8. In an unprogrammed or erased part, all configuration bits are O.

Port Functions
(Cont.)

Port A in Multiplexed
Address/Data Mode
The default configuration of Port A is I/O. In
this mode, every pin can be set as an input
or output by writing into the respective pin's
direction flip flop (DIR FF, in Figure 4). As
an output, the pin level can be controlled by
writing into the respective pin's data flip flop
(DFF, in Figure 4). When DIR FF = 1, the
pin is configured as an output. When DIR
FF = 0, the pin is configured as an input.
The controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the DFF bits by accessing the READ
DATA register. Port A pin levels can be
read by accessing the READ PIN register.
Individual pins can be configured as CMOS
or open drain outputs. Open drain pins
require external pull-up resistors. For
addressing information, refer to Tables 6
and 7.
Alternatively, each bit of Port A can be
configured as a low-order latched address
bus bit. The address is provided by the port
address latch, which latches the address
on the trailing edge of ALE. PAO-PA7 can
become AO-A7, respectively. This feature
of the PSD302 lets the user generate loworder address bits to access external
peripherals or memory that require several
low-order address lines.

Another mode of Port A (CPAF2 = 1) sets
the entire port to track the inputs
ADO/AO-AD7/A7, depending on specific
address ranges defined by the PAD's
CSADIN, CSADOUT1, and CSADOUT2
signals. This feature lets the user interface
the microcontroller to shared external
resources without requiring external buffers
and decoders. In this mode, the port is
effectively a bi-directional buffer. The direction is controlled by using the input signals
ALE, RD/E/DS, WRIVpp or R/W, and the
internal PAD outputs CSADOUT1 ,
CSADOUT2 and CSADIN (see Figure 5).
When CSADOUT1 and ALE are true, the
address on the input ADO/A7-AD7/A7 pins
flows out through Port A. (Carefully check
the generation of CSADOUT1 , and ensure
that it is stable during the ALE pulse; see
Figures 22 and 23). When CSADOUT2 is
active, a write operation is performed (see
note to Figure 5). The data on the input
ADO/A7-AD7/A7 pins flows out through
Port A. When CSADIN and a read operation is performed (depending on the mode
of the RD/E/DS and WR/vpp or RiW pins),
the data on Port A flows out through the
ADO/A7-AD7/A7 pins. In this operational
mode, Port A is tri-stated when none of the
above-iT~entjOi,ed

three

cor.da~ons

exist.

-----------------------------f==~§----------------------------

2-95

•

PSD3D2

Port Functions
(Cont.)

Port A in Non-Multiplexed
Address/Data Mode

Port Bin 16-Bit Non-Multiplexed
Address/Data Mode

In this mode, Port A becomes the low order
data bus byte of the chip. When reading an
internal PSD302 location, data is presented
on Port A pins. When writing to an internal
PSD302 location, data present on Port A
pins is written to that location.

In this mode, Port B becomes the highorder data bus byte of the chip. When
reading an internal PSD302 high-order
data bus byte location, the data is
presented on Port B pins. When writing to
an internal PSD302 high-order data bus
byte location, data present on Port B is
written to that location. See Table 9.

Port B in Multiplexed Address/Data
and in 8-Bit Non-Multiplexed Modes
The default configuration of Port B is 1/0. In
this mode, every pin can be set as an input
or output by writing into the respective pin's
direction flip flop (DIR FF, in Figure 6). As
an output, the pin level can be controlled by
writing into the respective pin's data flip flop
(DFF, in Figure 6). When DIR FF = 1, the
pin is configured as an output. When DIR
FF = 0, the pin is configured as an input.
The controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the DFF bits by accessing the READ
DATA register. Port B pin levels can be
read by accessing the READ PIN register.
Individual pins can be configured as CMOS
or open drain outputs. Open drain pins
require external pull-up resistors. For
addressing information, refer to Tables 6
and 7.
Alternatively, each bit of Port B can be
configured to provide a chip-select output
signal from PAD B. PBO-PB7 can provide
CSO-CS7, respectively. Each of the signals
CSO-CS3 is comprised of four product
terms.Thus, up to four ANDed expressions
can be ORed while deriving any of these
signals. Each of the signals CS4-CS7 is
comprised of two product terms. Thus, up
to two ANDed expressions can be ORed
while deriving any of these signals.

Accessing the I/O Port Registers
Tables 6 and 7 show the offset values with
the respect to the base address defined by
the CSIOPORT. They let the user access
the corresponding registers.

Port C in All Modes
Each pin of Port C (shown in Figure 7) can
be configured as an input to PAD A and
PAD B or output from PAD B. As inputs,
the pins are named A 16-A 18. Although the
pins are given names of the high-order
address bus, they can be used for any
other address lines or logic inputs to PAD A
and PAD B. For example, A8-A 10 can also
be connected to tho~ns, improving the
boundaries of CSO-CS7 resolution to 256
bytes. As inputs, they can be individually
configured to be logic or address inputs. A
logic input uses the PAD only for Boolean
equations that are implemented in any or
all of the CSO-CSl 0 PAD B outputs. Port C
addresses can be programmed to latch the
inputs by the trailing edge ALE or to be
transparent.
Alternatively, PCO-PC2 can become
CS8-CS10 outputs, respectively, providing
the user with more external chip-select
PAD outputs. Each of the signals
CS8-CS10 is comprised of one product
term.

-----------------------------------~~~----------------------------------2-96

PSD302

Figure 6.
PortB Pin
Structure

Figure 6 shows the structure of Port B.
READ PIN

N
T
E

R
N

A
L

c
s
o
U
T
B
U
S

I
N
T
E
R
N
A
L

READ DATA
CMOS/OD(9)
WRITE DATA

~

OUT

OFF
D

D
A
T
A

R
DI

PORTB PIN

ENABLE

MUX

B
U
S

•

CSI
D

C
S

CK

READDIR

8

o
D

D

7

1
5

WRITEDIR

OIR
CK
R

CONTROL

FF

RESET

NOTE: 9. CMOSIOD determines whether the output is open drain or CMOS.

Table 6.
I/O Port
Addresses in an
8-bit Data Bus
Mode

Table 7.
I/O Port
Addresses in an
16-bit Data Bus
Mode 1o,11

Register Name

Byte Size Access of the I/O Port Registers
Offset from the CSIOPORT

Pin Register of Port A

+ 2 (accessible during read operation only)

Direction Register of Port A

+4

Data Register of Port A

+6

Pin Register of Port B

+ 3 (accessible during read operation only)

Direction Register of Port B

+5

Data Register of Port B

+7

Register Name

Word Size Access of the I/O Port Registers
Offset from the CSIOPORT

Pin Register of Ports B and A

+ 2 (accessible during read operation only)

Direction Register of Ports B and A

+4

Data Register of Ports B and A

+6

NOTES: 10. When the data bus width is 16, Port B registers can only be accessed if the BHE
signal is low.
11. 1/0 Ports~nd B are still byte-addressable, as shown in Table 6. For 1/0 Port B register
access, BHE must be low.

-----------------------------------f~~~~---------------------------------."'I!!UE!II
2-97

PSD302

Port Functions
(Cont.)

ALE/AS and ADO/AD-AD15/A15 in
Non-Multiplexed Modes
In non-multiplexed modes,
AOOIAO-A0151A 15 are address inputs only
and can become transparent (CLOT = 0) or
ALE dependent (CLOT = 1). In transparent
mode, the ALE/AS pin can be used as an
additional logic input to the PAOs. The nonmultiplexed ALE dependent mode is useful
in applications for which the host processor

has a multiplex address/data bus and
AOO/AO-AO?/A? are not multiplexed with
AO-A? but rather are multiplexed with other
address lines. In these applications, Port A
serves as a data bus and each of its pins
can be directly connected to the corresponding host's multiplexed pin, where that
data bit is expected.
(See Table 8.)

EPROM

The PS0302 has 512K bits of EPROM.
Oepending on the configuration of the data
bus, the EPROM can be organized as 64K
x 8 (8-bit data bus) or as 32K x 16 (16-bit
data bus). The EPROM has 8 banks of
memory. Each bank can be placed in any

address location by programming the PAO.
BankO-Bank? can be selected by PAO
outputs ESO-ES?, respectively. The
EPROM banks are organized as 8K x 8
(8-bit data bus) or as 4K x 16
(16-bit data bus).

SRAM

The PS0302 has 16K bits of SRAM.
Oepending on the configuration of the data
bus, the SRAM organization can be 2K x 8

(8-bit data bus) or 1K x 16 (16-bit data
bus). The SRAM is selected by the RSO
output of the PAO.

Page Register

The page register consists of four
flip-flops, which can be read from, or
written to, through the 1/0 address space
(CSIOPORT). The page register is
connected to the 03-00 lines. The Page
Register address is CSIOPORT + 18H. The

page register outputs are P3-PO, which are
fed into the PAO. This enables the host
microcontroller to enlarge its address
space by a factor of 16 (there can be a
maximum of 16 pages). See Figure 8.

Control Signals

The PS0302 control signals are WRlVpp or
R/W, RO/E/OS, ALE, BHE/PSEN, Reset,
and A 19/CSI. Each of these signals can be
configured to meet the output control signal
requirements of various microcontrollers.

RO/E/OS

WR/Vpp or R/W
In operational mode, this signal can be
configured as WR or R/IN. As WR, all write
operations to the PS0302 are activated by
an active low signal on this pin. As R/W,
the pin works with the E strobe of the
RO/E/OS pin. When RiW is high, an active
high signal on the ROlE/OS pin performs a
read operation. When RiW is low, an active
high signal on the RO/E/OS pin performs a
write operation.

In operational mode, this signal can be
configured as RO, E, or OS. As RO, all
read operations to the PS0302 are activated by an active low signal on this pin. As
E, the pin works with the R/W signal of the
WRlVpp or R/W pin. When R/W is high, an
active high signal on the RO/E/OS pin
performs a read operation. When R/W is
low, an active high signal on the RO/E/OS
pin performs a write operation.
As OS, the pin functions with the R/W
signal as an active low data strobe signal.
As OS, the RiW defines the mode of
operation (Read Or Write).

-2--9-8----------------------------------~~~-------------------------------------

PSD302

Figure 7.
Port CStructure

I J -D
CADLOG
CONF.
BIT

pco

1

11

(NOTE 12)

.I ADDRESS I

I

LATCH

I

.. CS8 !OUTPUT LINE!

I I
CPCFO
CONF.
BIT

I

ADDRESS INDICATOR

CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL

A16
TO PAD

FROM PAD

CADLOG1
CONF.
BIT

1

I

D-

I

D-

ALE

11
.I ADDRESS I

I

PC11

LATCH

I

.. CS9 !OUTPUT LINE!

I I
CPCF1
CONF.
BIT

I

FROM PAD

CADLOG2
CONF.
BIT

1

11
I ADDREssL

PC2 ,{

I

A17
TO PAD

LATCH

I

.. CS10 !OUTPUT LINE!

I
A18
TO PAD

FROM PAD
TO
EPROM

NOTE:

FigureS.
Page Register

12. The CADDHLT configuration bit determines if A18-A16 are transparent via the latch, or if
they must be latched by the trailing edge of the ALE strobe.

r---.,---------------------------:~ }

r----r---------------

P1

TO PAD
INPUTS

r--..J;::~r-po

INTERNAL
RESET

INTERNALWR
PAGE SELECT
INTERNAL RD
ADO

y

)

DATA BUS

rl'-Ji§

-----------------------------------------~~Ar-------------------------------------2---9-9

P60302

Control Signals
(Cont.)

Figure 9.
Combined
Address Space

ALE or AS

BHE/PSEN

ALE polarity is programmable. When
programmed to be active high, a high on
the pin causes the input address latches,
Port A address latches, Port C, and A 19
address latches to be transparent. The
falling edge of ALE locks the information
into the latches. When ALE is programmed
to be active low, a low on the pin causes
the input address latches, Port A address
latches, Port C, and A 19 address latches to
be transparent. The rising edge of ALE
locks the appropriate information into the
latches.

This pin's function depends on the PSD302
data bus width. If it is 8, the pin is PSEN; if
it is 16, the pin is SHE. In 8-bit mode, the
PSEN function enables the user to work
with two address spaces: program memory
and data memory (if COMB/SEP = 1). In
this mode, an active low signal on the
PSEN pin causes the EPROM to be read if
selected. The SRAM and I/O ports read
operation are done by RD low (CRRWR =
0), or by E high and R/Vii high (CRRWR =
1, CEDS = 0) or by OS low and Rm high
(CRRWR, CEDS = 1).

~

ADDRES~

....

cs

PAD

SRAM

OE
INTERNAL
RD

r=

~,
PSEN

.)

OE

~

EPROM

"

CS

cs
OE

I/O PORTS

Figure to.
BOat-Type
Separate Code
andOata
Address Spaces

INTERNAL

I

I/O PORTS

RD

ADRESS

•

OE

•,

J

I

,

CS

-~

I

PAD

f---+

OE
CS

SRAM

CS
PSEN

EPROM
-" OE

-----------------------------------'Arl~~----------------------------------2-100
~.,=

PSD302

Control Signals
(Cont.)

SRAM, and I/O ports are read by RD low
(CRRWR = 0), or by E high and Riw high
(CRRWR = 1, CEDS = 0) or by DS low
and R/W high (CRRWR, CEDS = 1). See
Figures 9 and 10.

BHE/PSEN
Whenever a member of the S031 family
(or any other similar microcontroller) is
used, the PSD302's PSEN pin must be
connected to the PSEN pin of the
microcontroller.

If COMB/SEP = 0, the address spaces of
the program and the data are combined. In
this configuration (except for the S031-type
case mentioned above), the PSEN pin
must be tied high to Vee, and the EPROM,

Table 8.
Signal Latch
Status in All
Operating
Modes

Signal
Name

In BHE mode, this pin enables accessing of
the upper-half byte of the data bus. A low
on this pin enables a write or read operation to be performed on the upper half of
the data bus (see Table 9).

Configuration
Bits
CDATA , CADDRDAT, CLOT
CDATA, CADDRDAT

ADS/ASAD15/A15

ADO/AOAD7/A7

A19 and
PC2-PCO

=0

= 0, CLOT = 1

Signal Latch
Status

S-bit data,
non-multiplexed

Transparent
ALE
Dependent

16-bit data,
non-multiplexed

Transparent
ALE
Dependent

CDATA

= 1, CADDRDAT, CLOT = 0

CDATA

= 1, CADDRDAT = 0, CLOT = 1

CDATA

= 0, CADDRDAT = 1

S-bit data,
multiplexed

Transparent

CDATA

= 1, CADDRDAT = 1

16-bit data,
multiplexed

ALE
Dependent

CADDRDAT

= 0, CLOT = 0

CADDRDAT

= 0, CLOT = 1

CADDRDAT

=1

non-multiplexed
modes

Transparent
ALE
Dependent

multiplexed modes

ALE
Dependent

CDATA

=0

S-bit data,
PSEN is active

Transparent

CDATA

= 1, CADDRDAT = 0

16-bit data,
non-multiplexed
mode,
BHE is active

Transparent

CDATA

= 1, CADDRDAT = 1

16-bit data,
multiplexed mode,
BHE is active

ALE
Dependent

=0

A16-A19 can
become logic inputs

Transparent

=1

A16-A19 can
become
multiplexed
address lines

ALE
Dependent

--

BHE/
PSEN

Configuration
Mode

CADDHLT

CADDHLT

i

_________________

r~~~E·

__________________
2-101

•

PSD302

Control Signals
(Cont.)

Table 9.
High/Low Byte
Selection Truth
Table (in 16-Bit
Configuration
Only)
Table 10.
Signal States
During and After
Reset

Table 11.
Internal States
During and After
Reset

RESET

A19/CSI

This is an asynchronous input pin that
clears and initializes the PSD302. Reset
polarity is programmable (active low or
active high). Whenever the PSD302 reset
input is driven active for at least 100 ns, the
chip is reset. During boot-up (Vee applied),
the device is automatically reset internally
(internal automatic reset is over by the time
Vee operating range has been achieved
during boot-up). Tables 10 and 11 indicate
the state of the part during and after reset.

When configured as CSI, a high on this pin
deselects, and powers down, the chip. A
low on this pin puts the chip in normal
operational mode. For PSD302 states
during the power-down mode, see Tables
12 and 13, and Figure 11.
In A 19 mode, the pin is an additional input
to the PAD. It can be used as an address
line (CADLOG3 = 1) or as a generalpurpose logic input (CADLOG3 = 0). A19
can be configured as ALE dependent or as
transparent input (see Table 8). In this
mode, the chip is always enabled.

SHE

Au

0

0

Whole Word

0

1

Upper Byte From/To Odd Address

1

0

Lower Byte From/To Even Address

1

1

None

Operation

Signal

Configuration Mode

Condition

ADO/AO-AD15/A 15

All

Input

PAO-PA?)
(Port A

I/O
Tracking ADO/AO-AD?
Address outputs AO-A?

Input
Input
Low

PBO-PB?
(Port B)

I/O
CS?-CSO CMOS outputs
CS?-CSO open drain outputs

Input
High
Tri-stated

PCO-PC2
(Port C)

Address inputs A 16-A 18
CS8-CS10 CMOS outputs

Input
High

Component
PAD

Data register A
Direction register A
Data register B
Direction register B

Signals

Contents

CSO-CS10

All

= 1 (Note 13)

CSADIN, CSADOUT1 ,
CSADOUT2, CSIOPORT,
RSO, ESO-ES?

All

= 0 (Note 13)

n/a
n/a
n/a
n/a

0
0
0
0

NOTE: 13. All PAD outputs are in a non-active state.

-----------------------------------~~~----------------------------------2-102

PS0302

Figure ".
A191CSI Cell
Structure

ADDRESS INDICATOR
TO EPROM

(NOTE 14)

CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL
ALE-------------------,

~

>-----+1

.;..<'

A19/CSI- :
.;,..,.t>----"'~~~~~=L---------_

/',

-l-i
NOTES:

Table 12. Signal
States During
Power-Down
Mode

Table 13.
Internal States
During PowerDown

TO PAD, EPROM, SRAM,
PORTS, LATCHES, ETC.

14. The CADDHLT configuration bit determines if A19-A16 are transparent via the latch,
or if they must be latched by the trailing edge of the ALE strobe.

Signal

Configuration Mode

Condition

ADO/ AO-AD 15/A 15

All

Input

PAO-PA7

I/O
Tracking ADO/AO-AD7/A7
Address outputs AO-A7

Unchanged
Input
A1I1's

PBO-PB7

I/O
CSO-CS7 CMOS outputs
CSO-CS7 open drain outputs

Unchanged
A1I1's
Tri-stated

PCO-PC2

Address inputs A 18-A 16
CS8-CS10 CMOS outputs

Input
A1I1's

Component
PAD

Data register A
Direction register A
Data register B
Direction register B

Signals

Contents

CSO-CS10

All 1's (deselected)

CSADIN, CSADOUT1 ,
CSADOUT2, CSIOPORT,
RSO, ESO-ES7

All O's (deselected)

n/a
n/a
n/a
n/a

All
unchanged

-----------------------------~~~-------------------------2~-~10=3

•

PSD302

Figure 12.
'S0302
Interface With
Intel's 80e31

Vee

31

-

Hi

PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7

EANP
X1

CJ
X2

RESET

INTO

15
1
2
3
4
5
6
7
8

T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

E-:L
-=-

0.1~F

Microcontroller

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

Ri5"
WR

PsEN

ALE
TXD
RXD

39
38
37
36
35
34
33
32

23
24
25
26
27
28
29
30

21
22
23
24
25
26
27
28

31
32
33
35
36
37
38
39

17
16
29
30
11
10

22 Ri5
2 WANpp
1
8RE/PSEN"
13
ALE
3
RESET

ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/M
AD5/A5
AD6/A6
AD7/A7

PAO
PA1
PA2
PA3
PM
PA5
PA6
PA7

ADS/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PCO
PC1
PC2
A19/CSl

21
20
19
18

17
16
15
14
11
10
9
S
7
6
5
4
40
41
42
43

GND

PSD302
80C31

34

12

-

The configuration bits for Figure 12 are:
CRESET

1

COMB/SEP

o or 1 (both valid)

CALE

0

CRRWR

0

CDATA

0

CEDS

0

CADDRDAT
All other configuration bits may vary according to the application requirements.

Security Mode

Security Mode in the PSD302 locks the
contents of the PAD A , PAD B and all the
configuration bits. The EPROM, SRAM,
and I/O contents can be accessed only
through the PAD. The Security Mode can

be set by the MAPLE or Programming
software. In window packages, the mode is
erasable through UV full part erasure. In
the security mode, the PSD302 contents
cannot be copied on a programmer.

System
Applications

In Figure 12, the PSD302 is configured to
interface with Intel's 80C31 , which is a 16bit address/8-bit data bus microcontroller.
Its data bus is multiplexed with the loworder address byte. The 80C31 uses
signals RD to read from data memory and
PSEN to read from code memory. It uses
WR to write into the data memory. It also
uses active high reset and ALE signals.
The rest of the configuration bits as well as
the unconnected signals (not shown) are
application specific and, thus, user
dependent.

In Figure 13, the PSD302 is configured to
interface with Motorola's 68HC11, which is
a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the
low-order address byte. The 68HC11 uses
E and RiiJ signals to derive the read and
write strobes. It uses the term AS (address
strobe) for the address latch pulse. RESET
is an active low signal. The rest of the
configuration bits as well as the unconnected signals (not shown) are application
specific and, thus, user dependent.

----------------------------------___ 'AVAVAF~------------------------------------2.104

"#If#_

PSD302

Figure 13.
PS0302
Interface With
Motorola's
68NC11

Vee

pco

20
21
22
23
24
25

PDO
PD1
PD2
PD3
PD4
PD5

43
45
47
49
44
46
48
50

PEO
PE1
PE2
PE3
PE4
PES
PE6
PE7

34
33
32
31
30
29
28
27

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7

52
51

VRH
VRL

~
-=-

0.1~F

Microcontroller
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

9
10
11
12
13
14
15
16

23
24
25
26
27
28
29
30

42
41
40
39
38
37
36
35

31
32
33
35
36
37
38
39
22

E

FWi
~
RESET
XIRQ
IRQ
MODB
MODA

2
13
3

6
4
17
18
19
2
3

ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/M
ADS/AS
AD6/A6
AD7/A7

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7

AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

E

PCO
PC1

R/W/vpp
AS

RESEi'

11
10
9
8
7
6
5
4

•

40
41
42
43

BHE/PSEN

Vee
GND

PSD302

68HC11

PC2
A19/CSI

21
20
19
18
17
16
15
14

34

12

-:-

The configuration bits for Figure 13 are:
CRESET

0

COMB/SEP

CALE

0

CRRWR

1

CDATA

0

CEDS

0

0

CADDRDAT
All other configuration bits may vary according to the application requirements.

System
Applications
(Cont.)

In Figure 14, the PSD302 is configured to
work directly with Intel's 80C 196KB microcontroller, which is a 16-bit address/16-bit
data bus processor. Address and data lines
multiplexed. In the example shown, all
configuration bits are set. The PSD302 is
configured to use PCO, PC1, PC2, and
CSI/A19 as A16, A17, A18, and A19 inputs,
respectively. These signals are independent of the ALE pulse (latch-transparent).
They are used as four general-purpose
logic inputs that take part in the PAD equations implementation.

Port A is configured to work in the special
track mode, in which (for certain conditions)
PAO-PA7 tracks lines ADO/AO-AD7/A7.
Port B is configured to generate CSO-CS7.
In this example, PB2 serves as a WAIT
signal that slows down the 80C 196KB
during the access of external peripherals.
These 8-bit wide peripherals are connected
to the shared bus of Port.A.. The WA.IT
signal also drives the buswidth input of the
microcontroller, so that every external
peripheral cycle becomes an 8-bit data bus
cycle. PB3 and PB4 are open-drain output
signals; thus, they are pulled up externally.

___________________________________ f=~=E------------------------------~~
2-105

P50302

Figure 14.
PS0302
Interface With
Intel's
80C196KB.
+5V

'1
)

80C196KB

Ej

.-!!!....

=c.- ~
3

NMI

~
64

IJ!§C:::
.----..

I
I

-

~
~

=t
16

6
5
7
4
11
10
8
9

~

~
T,D

L::5
FS
L--...,..;l

~
L-....,;l
+5V

18
17
15
44

~
39
33
38
24
25
26
27
13
37

XTAl1

0.1 >IF

FOUR
GENERAL
PURPOSE
INPUTS

.----..

Pi.3
Pi.4
Pi.S
Pi.6
Pi.?

XTAL2

CDE
RESET

60 ADO/AD
59 AD1/Al
58 AD21A2
57 AD3fA3
56 AD4/A4
55 ADS/A5
54 AD6/A6
53 A07/A7

P3.0/ADO
P3.1JADl
P3.2/AD2
P3.3/AD3
P3.4/AD4

PO.O
PO.;
PO.2
PO.3
PC.4

P3.S/AD5
P3.61AD6
P3.7JAD7

PO.S
PO.6
PO.?

52 ADS/AS
51 AD91A9
50 ADiO/AiD
49 AD11/Al1
48 AD12/A12
47 AD13/A13
46 A014/A14
45 A015/A15

P4.0/AD8
P4.1/AD9

P2.0fTXD
P2.1!RXD
P2.2!EXINT
P2.31T2CLK
P2.41T2RST
P2.5/PWM
P2.61T2 UP/ON
P2.71T2 CAPTR

P4.21AD10
P4.3/AD11
P4.4/AD12
P4.5/AD13
P4.6/AD14
P4.7/AD15
ClKOUT
BHE/WRH

HSI.O
HSI.1
HSI.2/HSO.4
HSI.3/HSO.5

RD

VAEF
VPP
ANGND
V"

t

V"

HSO.O
HSO.l
HSO.2
HSO.3

AD[O. .151

ADDRESS/DATA MULTIPLEXED BUS

>

}

PORT 1

I/GPINS

~

PSD302

~
~

ADO/AD
ADlfAl
AD2/A2
AD3/A3
AD4/A4

~
~
~

~
41
40
61

WR/WRl
AlEIADiJ
INST

"F
19
20
21
22
23
30
31
32

Pl.D
Pl.1
Pl.2

Vee

NMI
READY
BU$WIDTH

M~ EA

AO[O .. 15J
01

ADS/AS
AD6JA6
AD7/A7
ADS/AS
A09/A9
A010/A1Q
AD11/Al1
A012/A12
A013/A13
AD141A14
AD151A15

23
24
25

'"

~
63

37

38

-*~

28

~
~

1
2
22

34

13

36

ADO/AD
ADi/Al
AD2/A2
AD3/A3
AD4/A4
AD6/A6

40
41

I---

Vee

ADS/AS

31
32
33
::Ifi

,.L

O.l,..F
SHARED
BUS

44:r

AD7/A7
ADS/AS
AD9/A9
AD10/A10
AD11!Al1
AD12!A12
AD13fA13
AD14/A14
AD15!A15

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

21
20
19
18

PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB?

11
10
9 WAIT
8
7
6

pco

17

16
15
14

:f3
~

-?

r-+-!.....
4.7KO

PCl
PC2
CSI/A19

ti:'-----'

~

4.7KO

+5V

~

- -

BHE/PSEN

~

\iVRlV pp
AD
ALE

RESET

GNO GND

~

----

Li4

I---<

L:::5
~

The configuration bits for Figure 14 are:
CRESET
CALE
CDATA
CADDRDAT
CPAF1
CPAF2
CA19/CSI
CRRWR
COMB/SEP
CADDHLT

o

o
1
1
Don't care
1
1

o
o
o

CSECURITY
CPCF2, CPCF1, CPCFO
CPACOD7-CPACODO
CPBF7-CPBFO
CPBCOD7-CPBCODO
CEDS
CADLOG3-CADLOGO

Don't care
0,0,0
OOH
OOH
18H

o

OH

-----------------------------------------------'AfAf~~----------------------------------------------:;;e;E!!F IE

2-106

PSD302

Absolute
Maximum
Ratings 15

Condition

Min

Max

Unit

-65

+ 150

°C

Voltage on any Pin

With Respect to GND

- 0.6

+7

V

Vpp

Programming
Supply Voltage

With Respect to GND

- 0.6

+14

V

Vcc

Supply Voltage

With Respect to GND

- 0.6

+7

V

>2000

V

Symbol

Parameter

T STG

Storage Temperature

ESD Protection

NOTE: 15. Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at
theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.

Operating
Range

Range

Temperature

Commercial

Recommended
Operating
Conditions

DC
Characteristics

Tolerance

Vee

-12

-15

-20

±5%

± 10%

± 10%

0° C to +70°C

+5V

Industrial

-40° C to +80°C

+5V

± 10%

± 10%

Military

-55° C to + 125°C

+5V

± 10%

± 10%

Conditions

Min

vee

Supply Voltage

-12 Version

4.75

5

5.25

Vee
V 1H

Supply Voltage

-15/-20 Versions

4.5

5

5.5

High-level Input Voltage

Vce; 4.5 V to 5.5 V

2

V1L

Low-level Input Voltage

Vee; 4.5 V to 5.5 V

0

Symbol

Symbol
VOL

V OH

ISB1
ISB2

Parameter

Parameter
Output Low Voltage

Output High Voltage

Min

0.8

0.01

0.1

IOL; 8 rnA
Vee; 4.5 V

0.15

0.45

4.4

4.49

2.4

3.9

V

Comm'l

50

100

Ind/Mil

75

150

Vee Standby Current

Comm'l

1.5

3

(TTL) (Notes 17 and 18)

Ind/Mil

2

3.2

Comm'l (Note 20)

16

35

Comm'l (Note 21)

28

50

Ind/Mil (Note 20)

16

45

Ind/Mil (Note 21)

28

60

(Notes 16 and 19)

V

V

(CMOS) (Notes 16 and 18)

(SRAM Not Selected)

V

Typ Max Unit

IOL; 20 flA
Vee; 4.5 V

IOH; -20 flA
V ee ;4.5V
IOH ;-2 mA
Vee; 4.5 V

V
V

Vec Standby Current

Active Current (CMOS)
lee1

Conditions

Typ Max Unit

flA
mA

--

.

111/"\

-----------------------------------~~~~----------------------------------2-107

•

PS0302

DC
Characteristics
(Cont.)

Symbol

Parameter
Active Current (CMOS)
(SRAM Block Selected)
(Notes 16 and 19)

ICC2

Active Current (TTL)
ICC3

(SRAM Not Selected)
(Notes 17 and 19)
Active Current (TTL)

ICC4

(SRAM Block Selected)
(Notes 17 and 19)

Conditions

Min Typ Max Unit

Comm'l (Note 20)

47

80

Comm'l (Note 21)

59

95

Ind/Mil (Note 20)

47

100
115

Ind/Mil (Note 21)

59

Comm'l (Note 20)

36

65

Comm'l (Note 21)

58

80

Ind/Mil (Note 20)

36

80

Ind/Mil (Note 21 )

58

95

Comm'l (Note 20)

67

105

Comm'l (Note 21)

79

120

Ind/Mil (Note 20)

67

130

79

145

Ind/Mil (Note 21)
III

Input Leakage Current

V1N = 5.5 V or GND

-1

± 0.1

1

ILO

Output Leakage Current

V OUT = 5.5 V or GND

-10

±5

10

NOTE:

AC
Characteristics
(See Timing
Diagrams)

mA

IlA

CMOS inputs: GND ± 0.3 V or Vcc ± 0.3V.
TTL inputs: V 1L 0; 0.8 V, V 1H ~ 2.0 V.
CSI/A19 is high and the part is in a power-down configuration mode.
AC power component is 3.0 mA/MHz (power = AC + DC).
Ten (10) PAD product terms active. (Add 380 IlA per product term, typical, or 480 IlA
per product term maximum
21. Forty-one (41) PAD product terms active.

Parameter

Min

-12
Max

-15
-20
Unit
Min Max Min Max

T1

ALE or AS Pulse Width

30

40

50

T2

Address Set-up Time

9

12

15

T3

Address Hold Time

9

12

15

T4

ALE or AS Trailing Edge
to Leading Edge of Read

12

15

20

T5

ALE Valid to Data Valid

130

140

170

T6

Address Valid to
Data Valid

T8

mA

16.
17.
18.
19.
20.

Symbol

T7

mA

CSI Active to Data Valid
Leading Edge of Read to
Data Valid

120

150

200

130

160

200

38

55

60

T9

Read Data Hold Time

T10

Trailing Edge of Read to
Data High-Z

0

0

T11

Trailing Edge of ALE
or AS to Leading
Edge of Write

12

15

20

T12

RD,E,PSEN,DS
pulse width

45

60

75

T12A

WR Pulse Width

25

35

45

T13

Trailing Edge of Write or
Read to Leading Edge
of ALE or AS

0

0

0

T14

Address Valid to Trailing
Edge of Write

120

150

200

32

0
35

ns
40

-----------------------------------~~~----------------------------------2-108

PS0302

AC
Characteristics
(Cont.)

Symbol

Parameter

-12
Min Max

-15
-20
Unit
Min Max Min Max

T15

CSI Active to Trailing
Edge of Write

130

160

200

T16

Write Data Set-up Time

20

30

40

T17

Write Data Hold Time

5

10

15

T18

Port Input Set-up Time

30

35

45

T19

Port Input Hold Time

0

0

0

T20

Trailing Edge of Write
to Port Output Valid

40

50

60

T21

ADi or Control to
CSOi Valid

6

35

6

40

5

45

T22

ADi or Control to
CSOi Invalid

5

35

4

40

4

45

T23

Track Mode Address
Propagation Delay:
CSADOUT1 Already True

22

28

28

Track Mode Address
Propagation Delay:
CSADOUT1 Becomes
True During ALE or AS

33

50

50

T23A

T24

Track Mode Address
Holding Time

T25

Track Mode Read
Propagation Delay

T26

Track Mode Read
Hold Time

T27

Track Mode Write Cycle
Data Propagation Delay

T28

Track Mode Write Cycle
Write to Data Propagation
Delay

8

T29

Hold Time of Port A Valid
During Write CSOi
Trailing Edge

2

T30

CSI Active to CSOi Active

9

45

9

55

8

60

T31

CSI Inactive to CSOi
Inactive

9

45

9

55

8

60

T32

Direct PAD Input as
Hold Time

10

12

15

T33

R/W Active to E or
OS Start

20

30

40

T34

E or OS End to RIW

20

30

40

T35

AS Inactive to E high

15

20

25

15

27
29

11

29

10

20

30

29

35
10

30
7

ns

27
35

40

•

35
30

7

55

4

4

NOTES: 22. ADI = any address line.
23. CSOi = any of the chip-select output signals coming through Port B (CSo-CS7) or
through Port C (CSB-CS10).
24. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent
A19, RD/E/DS, WR or R/W, transparent PCO-PC2, ALE (or AS).
25. Control signals RD/E/DS or WR or R/IN.

-----------------------------------~~~~------------------------------~~
2-109

PSD302

Figure 15.
Timing of 8-Bit
Multiplexed
Address/Data
Bus, CRRWR = 0

...

READ CYCLE

-----,
CS IIA19
as CSI

..

-~
- Xx
32

7

...

..

WRITE CYCLE

- --fXX) "/.XXX
- J.J..X v..xx
32

15

L

32

Dire ct(26) . ]
PAD Inp ut

Multiplex ed(27)
Inp uts

AOIADOA?lAD?

~

STABLE INPUT
6

;c

14
,---

6
--..

ADDRESS A
2

-

3

DATA
OUT

4

IXXXX IXXXX
ADDRESS B

::.

.2.

I-'

... ~
\

RDIEIDS as RD
5

BHE/P-SEN
asP-SEN

\

~

}-

3

--.

~4

IN

~

1

xx:
~r

DATA

11

~

--'

'~

J

J

~
p or
sWR

~

~

19

18

Any of PAOPAl as 1/0 Pin

:x.II ~

Any of PBOPB? as 1/0 Pin

,

Any of PAOPAl PinS
as Add ress
Outputs

~

14

~-

8-

~h

Active Low'
ALE
~

~

STABLE INPUT

XXXXXX XX IXXX
~

_

Active High
ALE I

32_

X) IXXXXXXXXX
_

i'i'I.YX..

INPUT

~X X X X

INPUT

XXXXXXX'XXXXXXXXXXXX

~

I

2?.

~

OUTPUT

OUTPUT

~
ADDRESS A

ADDRESS B

'I

See referenced notes on page 2- t 19.

-2--1-10----------------------------~~Jr~-------------------------------

PSD302

Figure 16.
Timing of 8-Bit
Multiplexed
Address/Data
Bus, CRRWR = 1

....

....
-~

READ CYCLE

-

CS I/A19
as CSI

7

L

1-

Direct(26) ~
PAD Input

OOC

STA8LEINPUT
6

Multiplexed (27)
Inputs

AO/A DO-

~

DATA
\ OUT

ADDRESS A

-

3

~ P<

4

5

I-

.xXX ,XXX

12

~

3

~ 1--1 V--

35

~
33

34

-

XXXXXXXXX

rL
.F

34

~

r

.XXXXX

)0 IXXXXXXXXX

1-

~~

rxxxxxxx

~I

xx:

~

I-'

9

DATA
IN

17

h

,

RD/E/DS as DS

~

ADDRESS 8

I

RD/E/DS as E

-

32

14

2_

35

33

Any of P
AOPA7 Pins
as Add ress
Outputs

STA8LEINPUT

~

Active Low \
AS
~r--'

)C

'XX IXXXX

IXXXx1Xru

~f-

14-~

Any of P 80P87 as 1/0 Pin

..

14

81-

Active High Irh
AS I

Any of PAOPA7 as 1/0 Pin

-

32

~

6

2

WR/vp p or

I-

~

-.

R/Was R;W

-

32

15

IXXXXXX )()( IXXX

..XI

A71AD7 --.J

WRITE CYCLE

32

~

~

INPUT

J~

~
XXXXXXXXXXXXxxxn xX

OUTPUT

INPUT

~

XXXXXXXXXXXXXXXXXXX

OUTPUT

rEADDRESS A

ADDRESS B

See referenced notes on page 2-119.

----------------------------------~~jf---------------------------------

2-111

PS0302

Figure 17.
Timing of 16-Bit
Multiplexed
AddreSS/Data
Bus, CRRWR = 0

--

----.

READ CYCLE

CS I/A19
asCSI

Direct (26)
PAD In put

7

.:x 00<
X

DATA
\ OUT

-

3

. ..:....

4

I,(XXX IXXXX
I~

ADDRESS B
2_

3

h

~

,r-~

A

}-

DATA

IN

.!!

11

~

~

WAN PP....2!
RiWasWR

~

Any of PADPA7 as 1/0 Pin

'fj XXXXXXXXX

INPUT

Any of PBDPB7as II Pin

\
,..

INPUT

XXXXXXXXX

~
---'

19

1.---

DC1 -

Rr I\-

f-1

i-J

5

I~

14

~f--

81-

r~

RD/E/DS asRD

Any of PADPA7 Pins
as Address
Outputs

14

,(XXXXX IXli XXIX

Active Low'
ALE
'--.J

o

XXX .XXX

STABLE INPUT

XXXX IXXXX

~

ADDRESS A

,

32

1.---

2

Active High
ALE

..

XX XXXX

XXXXXX )0 XXX

Xl

ADIADDA15/A D15

--32

15

~~

STABLE INPUT

6

BHE/P-SEN
as BHE

WRITE CYCLE

•

32

6

Multiplexed (27)
Inputs

.. -

-~
32

V-

~

r----<

~
,X XXXXXXXXXXXXXXXJ(XXX:

OUTPUT

:X XXXXXXXXXXXXXXXXXXX

OUTPUT

.E.
ADDRESS A

ADDRESS B

See referenced notes on page 2-119.

--~---------------------------rllAF._Ar------------------------------2-112
fFiiI'#..!

PSD302

Figure 18.
Timing of 16·8it
Multiplexed
AddreSS/Data
8us, CRRWR = 1

..

32

~

CS
asCSI

Di reet (26)
PAD Input

Multiplexed (27)
Inputs

7

.:xl

1-

~

STABLE INPUT
6

X

2

3

--

~

Ir h
I

'DATA
\ OUT

4

32

~ P<

STABLE INPUT

ActiveLow ,
AS

~

~

1-

17

16

l- H V-J

35

~

~

-'

34

I~

13

~ t---

RD/E/DS asDS

~
RiWasRIW

xx:

33

5

~

3

DATA
IN

J

RD/Eli)
Sas E

WRNpp

I}-

--'

34

f-.

~

II

.XXXXX

JIXXXXXXX
19

~

~

t--

Any 0 f PAO- \
PA7 as I10 Pin ,..) lXXXXXXX;()(

INPUT

JIXXXXXXXXXXXXXXXXXXX

OUTPUT

Any 0 fPBO- \
PB7 as I10 Pin ,..

INPUT

:)1

XXXXXXXXXXXXXXXXXXX

OUTPUT

Any 0 f PAOPA7 Pins
as Ad dress Outputs

•

~

ADDRESS B

h
.2-.
12

IXXX :XXX

I. !!:

IiliUJ

'"

lfi

0'"

U
'"D..
...... ... ...'"

>0

0

~

0
D..

U

M

;;:

...

D..

0

uU "

o

PBl 10
PBO 11
GND 12
ALE or AS 13
PA7 14
PA615

.....

39 AD15/A15

.....

38 AD/14/A14

.....

37 AD13/A13

.....

36 AD12/A12
35 ADll/All

.....

34 GND

.....

32 AD9/A9

33 AD10/Al0
.....

PA516

29 AD6/A6

PA417

\.. [-1 ["1 f"1 [-1 r-1 [-1 [-1 [-1 f"1
0
... co
...
~ ~
'" N0 Ul'"'" '"0 '" '" '"'" ...'" '"
~~

M

M
c(

D..

'"D..
c(

iii
D..

c(

D..

c

~

W c0
c(

I~

(TOP VIEW)

Figure 29.
DrawingJ244-Pin Plastic
Leaded Chip
Carrier (PLDCC)
(Package Type
J)

I~
ex:
o~

...
m m
m '"
D.. D.. D..
'" ...
It)

It)

/u

I-

M

~~

12
UJ

8:: en

w >
Ul
~ Iii:
3:

'"

~

Iili
UJ
~

./

~

It)

M

~ '"
~ M~ ~ ~
C
c c c c
c( c( c( c( c(

It)

lfi

'" 0
...... ... '"... ... 0...
o ~ U 0 U
>o '"
c( D.. D.. D..
M

~

:__ !

Lj
C::. ]

....•

39 AD15/A15

PB4

7

PB3

8 l ::::,

,.:::. ] 39 AD14/A14

PB2

9

,.:::. ] 37 AD13/A13
,.:::. ] 36 AD12/A12

PBl 10

C::. ]
C::. ]

PBO 11
GND 12

35 ADll/All
34 GND

:.:::. ] 33 AD10/Al0

ALE or AS 13
PA714

,.:::. ] 32 AD9/A9

PA6 15

.....

31 AD8/A8

,.:.:. p30 AD7/A7
,.:::. p29 AD6/ AS

PA5 16
PA4 17

["1 [-1 ["1 ["1 ["1 r-l r-1 ["1 ["1 [-1
~ ~
M

c(

D..

'"D..
c(

...
... co
'" N~ I~'"'" '" '" '" '"'" ...'" '"
«
'"
W~ ~ N ~
~
0

M

0

D..

D..

I~

(TOP VIEW)

2-122

31 AD8/A8
30 AD7/A7

ruf!

It)

c(

M

..

It)

c(

c c c c
cc( C
c( c( c( c( c(

P50302

Figure 30.
OrawingQ252·PinPQFP
(Package Type Q)

o

NC

1

39 NC

PB4

2

38 AD15/A15

PB3

3

37 AD14/A14

PB2

4

36 AD13/A13

PB1

5

35 AD12/A12

PBO

6

34 AD11/A11

GND

7

33 GND

ALE or AS

8

32 AD10/A10

PA7

9

31 AD9/A9

PA6 10

30 AD8/A8

PA5 11

29 AD7/A7

PA4 12

28 AD6/A6
27 NC

NC 13

:! ~ ~ ~ ~ ~ 0
'"
'"a. «'"a. ;:;(a. a.~ I~W 0~
z «
Q
I~ «

0

(TOP VIEW)

Figure 31:
OrawingX244·PinCPGA
(Package Type X)

•

'"'"
'"~
'"
«
Q

.,.
'"'" .,.'" '" '"
0
It)

'"«M
Q

CD

.,« ~ z
It)

Q

Q

« « «

2345678
A
B
C
D
E

F
G
H

888888
88888888
88
88
88
88
88
88
88
88
88888888
888888

(TOP VIEW, THROUGH PACKAGE)

----------------------------------rjfAf~~--------------------------------~!!!!E=

2·123

PS0302

Ordering
Information

Part Number

Spd.
(ns)

PSD302-12J
PSD302-12L
PSD302-120
PSD302-12X
PSD302-15J
PSD302-15JI
PSD302-15L
PSD302-15L1
PSD302-15LM
PSD302-15LMB
PSD302-150
PSD302-15X
PSD302-15XI
PSD302-15XM
PSD302-15XMB
PSD302-20J
PSD302-20JI
PSD302-20L
PSD302-20Ll
PSD302-20LM
PSD302-20LMB
PSD302-200
PSD302-20X
PSD302-20XI
PSD302-20XM
PSD302-20XMB

120
120
120
120
150
150
150
150
150
150
150
150
150
150
150
200
200
200
200
200
200
200
200
200
200
200

Package
Type
44-pin
44-pin
52-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
52-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
52-pin
44-pin
44-pin
44-pin
44-pin

PLDCC
CLDCC
POFP
CPGA
PLDCC
PLDCC
CLDCC
CLDCC
CLDCC
CLDCC
POFP
CPGA
CPGA
CPGA
CPGA
PLDCC
PLDCC
CLDCC
CLDCC
CLDCC
CLDCC
POFP
CPGA
CPGA
CPGA
CPGA

WSI
Package Operating
Drawing Temperature Manufacturing
Range
Procedure
J2
L4
02
X2
J2
J2
L4
L4
L4
L4
02
X2
X2
X2
X2
J2
J2
L4
L4
L4
L4
02
X2
X2
X2
X2

Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
Commercial
Industrial
Military
Military
Commercial
Commercial
Industrial
Military
Military
Commercial
Industrail
Commercial
Industrial
Military
Military
Commercial
Commercial
Industrial
Military
Military

Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
Standard
MIL-STD-883C

-----------------------------------~~~~----------------------------------2-124

_ -_-

..5FEE~=
.... ..... ....
--~

r .........

PS0302
System
Development Tools

~..-

~~==:::'

:=

System
Development
Tools

The PSD302 features a complete set of
System Development Tools. These tools
provide an integrated, easy-to-use software
and hardware environment to support
PSD302 device development. To run these
tools requires an IBM-XT, -AT, or compatible computer, MS-DOS 3.1 or higher, 640K
byte RAM, and a hard disk.

Hardware
The PSD302 System Programming
Hardware consists of:

o

o
o
o

Support

WS6000 MagicPro Memory and PSD
Programmer
WS6020 52-pin PSD302 PQFP
Package Adaptor
WS6021 44-pin LCC Package Adaptor
(for CLDCC and PLDCC packages)
WS6022 44-pin CPGA Package
Adaptor

WSI provides a complete set of quality
support services to registered System
Development Tools owners, including:

The MagicPro Programmer is the common
hardware platform for programming all WSI
programmable products. It consists of an
IBM-PC plug-in programmer board and a
remote socket adaptor.

Software
The PSD302 System Development
Software consists of:

o
o
o

WISPER, WSl's Software Environment
MAPLE, the PSD302 Location Editor
Software
MAPPRO, the Device Programming
Software

The configuration of the PSD302 device is
entered using MAPLE software. MAPPRO
software uses the MagicPro programmer
and the socket adaptor to configure the
PSD302 device, which then can be used in
the target system. The development cycle
is depicted in Figure 32.

o 24-hour Electronic Bulletin Board for
design assistance via dial-up
modem.

o 12-month software updates
o Design assistance from WSI field
application engineers and
application group experts

Training

WSI provides in-depth, hands-on workshops for the PSD302 device and System
Development Tools. Workshop participants
leam how to program high-performance,
programmable peripherals. Workshops are
held at the WSI facility in Fremont,
California.

2-125

•

~

I

PSD302

Ordering
Information System
Development
Tools

PSO-GOLO

o
o
o
o
o
o

WS6021

WISPER Software
MAPLE Software
User's Manual
WSI Support
WS6000 MagicPro™ Programmer
One Package Adaptor and Two
PSD302 Product Samples

o

WS6022

o

PSO-SILVER

o
o
o
o

WISPER Software
MAPLE software
User's Manual
WSI Support

44-Pin CPGA Package Adaptor.
Used with the WS6000 MagicPro
Programmer.

WSISupport
Support services include:
12-month Software Update Service
Hotline to WSI Application Experts
24-hour access to WSI Electronic
Bulletin Board

o
o
o

WS6000

o
o
o

44-Pin LCC Package Adaptor for
CLDCC and PLDCC Packages.
Used with the WS6000 MagicPro
Programmer.

MagicPro Programmer
IBM-PC© Plug-in Adaptor Card
Remote Socket Adaptor

WSI Training

o

Workshops at WSI, Fremont, CA

WS6020

o

52-pin PQFP Package Adaptor. Used
with the WS6000 MagicPro
Programmer

Figure 32.
PSD302
Development
Cycle

IBM PLATFORM

Menu Selection

Configuration Data

Programming Data

MagicPro Hardware

-2--1-2-6------------------------------~~~----------------------------------

Programmable Peripheral
PS0312
Key Features

Programmable Microcontrol/er Peripheral
with Memory
o Single Chip Programmable Peripheral
o 512 Kbits of UV EPROM
for Microcontroller-based Applications

-

Organized as 64K x 8

19 Individually Configurable I/O pins
that can be used as

-

Divides into 8 equal mappable blocks
for optimized mapping

-

Microcontroller I/O port expansion

-

Block resolution is 8K x 8

-

Programmable Address Decoder
(PAD) I/O

-

120 ns EPROM access time, including
input latches and PAD address
decoding.

o

Partial Listing
of
Microcontrol/ers
Supported

-

Latched address output

-

Open drain or CMOS

o

Two Programmable Arrays
(PAD A & PAD B)

-

Total of 40 Product Terms and up to
16 Inputs and 24 Outputs

-

Direct Address Decoding up to 1 Meg
address space and up to 16 Meg
with paging

-

Logic replacement

o

o

16 Kbit Static RAM

-

Organized as 2K x 8

-

120 ns SRAM access time, including
input latches and PAD address
decoding

o
-

Address/Data Track Mode
Enables easy Interface to Shared
Resources (Mail Box SRAM) with other
Microcontrollers or a Host Processor

"No Glue" Microcontroller Chip-Set

o

-

Built-in address latches for multiplexed
address/data bus

-

-

Non-multiplexed address/data bus
mode

o

Available in a Variety of Packaging

-

8 bit data bus width

-

44 Pin PLDCC and CLDCC

-

ALE and Reset polarity programmable

-

52 Pin PQFP

-

Selectable modes for read and write
control bus as RD/WR, R/W/E, or
R/W/DS

-

44 Pin CPGA

o

Simple Menu-Driven Software:
Configure the PSD312 on an IBM PC

o

Downward Pin and Functionally
Compatible with the PSD301
in 8-bit Mode

-

PSEN/ pin for 8051 users

o

Built-In Page Logic

-

To Expand the Address Space of
Microcontrollers with Limited Address
Space Capabilities

-

Up to 16 pages

o

Motorola family:
M6805, M68HC11, M68HC16,
M68000/10/20, M60008, M683XX

o Intel family:

Built-In Security
Locks the PSD312 Configuration and
PAD Decoding

o Signetics:

SC80C451

o

Z8, Z80, Z180

Zilog:

o National:

HPC16000

8031/8051,8096/98,80186/88,
80196/98

2-127

•

PSD312

Applications

Introduction

Product
Description

a

Computers (Workstations and PCs)
Fixed Disk Control, Modem, Imaging,
Laser Printer Control

a

Industrial
Robotics, Power Line Access,
Power Line Motor

a

Telecommunications
Modem, Cellular Phone, Digital PBX,
Digital Speech, FAX,
Digital Signal Processing

a

Medical Instrumentation
Hearing Aids, Monitoring Equipment,
Diagnostic Tools

a

Military
Missile Guidance, Radar, Sonar,
Secure Communications, RF Modems

The PSD312 is the latest member in the
rapidly growing WSI family of PSD devices.
The PSD312 is ideal for microcontrollerbased applications, where fast time-tomarket, small form factor, and low power
consumption are essential. When
combined in a system, virtually any microcontroller (68HC11, 8051 etc.) and the
PSD312 work together to create a very
powerful chip-set solution. This implementation provides all the required control and

The PSD312 integrates high performance
user-configurable blocks of EPROM,
SRAM, and programmable logic technology
to provide a single chip microcontroller
interface. The major functional blocks
include two programmable logic arrays,
PAD A and PAD B, 512K bits of EPROM,
16K bits of SRAM, input latches, and
output ports. The PSD312 is ideal for
applications requiring high performance,
low power, and very small form factors.
These include fixed disk control, modem,
cellular telephone, instrumentation,
computer peripherals, military and similar
applications.
The PSD312 offers a unique single-chip
solution for microcontrollers that need:

a

I/O reconstruction (microcontrollers
lose at least two 1/0 ports when
accessing external resources).

a

More EPROM and SRAM than the
microcontroller's internal memory.

a

Chip-select, control, or latched address
lines that are otherwise implemented
discretely.

peripheral elements of a microcontrollerbased system peripheral with no external
discrete "glue" logic required.
The solution comes complete with simple
system software development tools for
integrating the PSD312 with the microcontroller. Hosted on the IBM PC platforms or
compatibles, the easy to use software
enables the designer complete freedom in
designing the system.

a

An interface to shared external
resources.

a

Expanding address space of
microcontrollers

WSI's PSD312 (shown in Figure 1) can
efficiently interface with, and enhance, any
microcontroller system. This is the first
solution that provides microcontrollers with
port expansion, latched addresses, page
logic, two programmable logic arrays PAD
A and PAD B, an interface to shared
resources, 512K bit EPROM, and 16K bit
SRAM on a single chip. The PSD312 does
not require any glue logic for interfacing to
any 8-bit microcontroller.
The 8051 microcontroller family can take
full advantage of the PSD312's separate
program and data address spaces. Users
of the 68HCXX family of microcontrollers
can change the functionality of the control
signals and directly connect the Rfij
and E, or the RiW and OS signals. Address
and data buses can be configured to be
separate or multiplexed, whichever is
required by the host processor.

r ....#."'___________________
---------------------~~Af

2-128

PSD312

Product
Oiscription
(Cont.)

The flexibility of the PSD312 I/O ports
permits interfacing to shared resources.
The arbitration can be controlled internally
by PAD A outputs. The user can assign the
following functions to these ports: standard
I/O pins, chip-select outputs from the PAD
A and PAD B, or latched address or multiplexed low-order address/data byte. This
enables users to design add-on systems
such as disk drives, modems, etc., that
easily interface to the host bus (e.g., IBM
PC, SCSI).

to map the I/O ports, eight segments of
EPROM (8K x 8 each) and SRAM (2K x 8)
anywhere in the address space of the
microcontroller. PAD B can implement up to
4 sum-of-product expressions based on
address inputs and control signals.
The page register extends the accessible
address space of certain microcontrollers
from 64K to 1 M. There are 16 pages
that can serve as base address inputs to
the PAD, thereby enlarging the address
space of 16 address line processors by a
factor of 16.

The PSD312 on-chip programmable
address decoder (PAD A) enables the user

Figure 1.
P$0312
Architecture

PAGE LOGIC

r:F

P3-PD
, - A11-A15
L
A
T
C
H

AB-A15

~

~
A19

CSIOPORT
A19

PADA

r-----

RESET

---

27 PT

ES3
ES2
ES1

r-

~

CSOCS7

1....+

64K BIT
BLOCK

~ l -I~

'----

~

PROG.
PORT
EXP.

~

'------1

,-

CS8CS1D

EPROM
512K BIT

ES7
ES6
ES5
ES4

'----

L.......,

r~~

--

l_

r---PORT

~

-

ALE/AS
PROG. CHIP
CONFIGURATION

i

WR/RfW
PSEN

PROG.
PORT
EXP.
PADPORT
A

ADO-AD7/DD-D7

RESET

I-

,-'--SRAM
16K BIT

AD-A7

58

PBOPB7

CSIOPORT

TRACK MODE
SELECTS

RD/E /

PCDPC2

l-

- - -

L
A
T
C
H

~.

PORT
C

I--

RD
WR
RESET

13 P.T.

t--

L-

PROG.
PORT
EXP.

!LOGIC IN

PADB

ALE/AS

RD
WR

~

~~

CSI

CSI
ALE/AS

.----

A DO-AD7

A16-A1B

~

-

I

X8.
MUX or NON-MUX BUSSES
SECURITY MODE

PROG.
CONTROL
SIGNALS

A19/CSI

FEE JF§

-----------------------------------------~~Af----------------------------------------

2-129

•

PS0312

Table 1.
PSD312 Pin
Descriptions

Description

Type

Name

The PSEN is the active low EPROM read pulse. The SRAM and 1/0
read sig!!.?1 is generated according to the description of the
WRIVpp or R/W, and RO/E/OS pins. If the host processor is a
member of the 8031 family, PSEN must be connected to the
corresponding host pin. In other 8-bit host processors that do not
have a special EPROM-only read...§.trobe, PSEN should be tied to
Vcc. In this case, RO or E and R/W provide the read strobe for the
SRAM, 1/0 ports, and EPROM.

~s

PSEN

I

In !be operating mode, this pin's function is WR (CRRWR = 0) or
R/W (CRRWR = 1) when configured as RIW. The following tables
summarize the read and write operations (CRRWR = 1):
WRIVpp
or
R/W

I

CEOS
RIW
E
X
0
1
0
1
1

=0
NOP
write
read

CEOS = 1
R/W OS
1
NOP
X
write
0
0
read
0
1

When configured as WR, a write operation is executed during an

active low pulse. When configured as R/W, with R/W = 1 and E = 1,
a read operation is executed; if R/W = 0 and E = 1, a write
operation is executed. In programming mode, this pin must be tied
to Vpp voltage.

RO/E/OS

CSI/A19

RESET

Legend:
NOTE:

The pin function depends on the CRRWR and CEOS configuration
bits. If CRRWR = 0, RO is an active low read pulse. When
CRRWR = 1, this pin and the Riw pin define the following cycle type:
If CEOS = 0, E is an active high strobe. If CEOS = 1, OS is an active
low strobe.
This pin has two configurations. When it is CSI (CA 19/CSI = 0) and
the pin is asserted high, the device is deselected and powered down.
(See Tables 10 and 11 for the chip state during power-down mode.)
If the pin is asserted low, the chip is in normal operational mode.
When it is configured as A 19, (CA 19/CSI = 1), this pin can be used
as an additional input to the PAD. CAOLOG3 = 1 defines the pin as
an address; CAOLOG3 = 0 defines it as a logic input. If it is an
address, A 19 can be latched with ALE (CADOHLT = 1) or be a
transparent logic input (CAOOHLT = 0). In this mode, there is no
power-down capability.
This user-programmable pin can be configured to reset on high
level (CRESET = 1) or on low level (CRESET = 0). It should remain
active for at least 100 ns. See Tables 8 and 9 for the chip state after
reset.

The 1/0 column abbreviations are: I = input; 1/0

= input/output; P = power.

1. All the configuration bits mentioned in Table 1 appear in parentheses and are explained in
the Configuration Register section.

-------------------------------------~=-~-------------------------------------

2-130

PSD312

Table 1.
PSD312 Pin
Descriptions
(Cont.)

Name
ALE
or
AS

PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO

PB7
PB6
PB5
PB4
PB3
PB2
PBO

PCO
PC1
PC2

Description

Type

I

1/0

1/0

1/0

In the multiplexed modes, the ALE pin functions as an Address
Latch Enable or as an Address strobe and can be configured as an
active high or active low signal. The ALE or AS trailing edge
latches lines AD15/A15-ADO/AO, A16-A19, and BHE, depending
on the PSD312 configuration. See Table 7. In the non-multiplexed
modes, it can be used as a general-purpose logic input to
the PAD.
PA7-PAD is an 8-bit port that can be configured to track
AD7/A7-ADO/AO from the input (CPAF2 = 1). Otherwise
(CPAF2 = 0), each bit can be configured separately as an 110 or
lower-order latched address line. When configured as an 1/0
(CPAF1 = 0), the direction of the pin is defined by its direction bit,
which resides in the direction register. If a pin is an 1/0 output, its
data bit (which resides in the data register) comes out. When it is
configured as a low-order address line (CPAF1 =1), A7-AO can be
made the corresponding output through this port (e.g., PA6 can be
configured to be the A6 address line). Each port bit can be a
CMOS output (CPACOD = 0) or an open drain output (CPACOD =
1). When the chip is in non-multiplexed mode (CADDRAT = 0), the
port becomes the data bus lines (00-07). See Figure 4.
PB7-PBO is an 8-bit port for which each bit can be configured as
an 1/0 (CPBF = 1) or chip-select output (CPBF = 0). Each port bit
can be a CMOS output (CPBCOD = 0) or an open drain output
(CPBCOD = 1). When configured as an 1/0, the direction of the
pin is defined by its direction bit, which resides in the direction
register. If a pin is an 110 output, its data (which resides in the data
~st~omes out. When configured as a chip-select output,
CSO-CS3 are a function of up to four product terms of the inputs to
the PAD B; CS4,-CS7 then are each a function of up to two
product terms. See Figure 6.
This is a 3-bit port for which each bit is configurable as a PAD A
and B input or output. When configured as an input (CPCF = 0), a
bit individually becomes an address (CAD LOG = 1) or a logic input
(CADLOG = 0). The addresses can be latched with ALE
(CADDHLT = 1) or be transparent inputs to the PADs
(CADDHLT = 0). When a pin is configured as an output
(CPCF = 1), it is a function of one product term of all PAD inputs.
See Figure 7.

-----------------------------------rArjf~:----------------------------------~.

~m

•

PSD312

Table 1.
PSD312 Pin
Descriptions
(Cont.)

Name
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
ADS/AS
AD7/A7
AS
A9
A10
A11
A12
A13
A14
A15

Operating
Modes

Description

Type

I/O

In multiplexed mode, these pins are the multiplexed low-order
address/data byte. After ALE latches the addresses, these pins
~t or outp~data, depending on the settings of the RD/E/DS,
WRN pp or RIW, and PSEN pins. In non-multiplexed mode, these
pins are the low-order address input.

I/O

These pins are the high-order address input.

GND

P

Vss (ground) pin.

Vcc

P

Supply voltage input.

The PSD312's two operating modes allow
it to interface directly to S-bit microcontrollers with multiplexed and nonmultiplexed address/data buses. These
operating modes are described below.

Multiplexed B-blt Address/Data Bus
This mode is used to interface to microcontrollers with an S-bit data bus and a 1S-bit
or larger address bus. The low-order
address/data bus (ADO/AD-AD7/A7) is
bidirectional and permits the latching of the
address when the ALE signal is active. On
the same pins, the data is read from or
written to the device; this depends on the
state of the RD/E/DS, PSEN and WRNpp
or RiW pins. The high-order address bus
(AS-A15) contains the high-order address
bus byte. Ports A and B can be configured
as in Table 2.

Non-Multiplexed
Address/Data, B-bit Data Bus
This mode is used to interlace to a
microcontroller with an S-bit non-multiplexed bus and a 1S-bit or larger address
bus. The low-order address/data bus
(ADO/AO-AD7/A7) is the low-order address
input bus. The high-order address/data bus
(AS-A 15) is the high-order address bus
byte. Port A is the low-order data bus. Port
B can be configured as shown in Table 2.
Table 2 summarizes the effect of the
different operating modes on ports A, B,
and the address/data pins. The configuration of Port C is independent of the four
operating modes.

-----------------------------------~ArAi-----------------------------------

2·132

----

P80312

Programmable
Address
Decoder (PAD)

The PSD312 consists of two programmable
arrays referred to as PAD A and PAD B
(Figure 3). PAD A is used to generate chip
select signals derived from the input
address to the internal EPROM blocks,
SRAM, I/O ports, and Track Mode signals.
All its I/O functions are listed in Table 3 and
shown in Figure 3. PAD B outputs to Ports
Band C for off-chip usage.
PAD B can also be used to extend the
decoding to select external devices or as a
random logic replacement. The input bus to

Figure 2.
PSD312 Port
Configurations

Figure 2 shows the PSDS312's I/O port configurations.
AD8·AD15

1/0 or AO·A7 or

AD~AD7

PA

ALE

AL E

I--

~
EN

1/0 or CSO·CS7

PB

R;WorWRlVpp

PB
RI Wor WRlVpp

RoIE/55

t-A16·A180rCS8·C

A 19/CSI

PC

RESET

A1 9/CSI

r--A16·A18 or CS8·

PC

RE SET

1. PSD312 configured for multiplexed
16-bit address/data bus.

Legend:

DO·D7

PA

AO ·A7

1/0 or CSO·CS7

RD/E/55

AS ·A15

ADO·AD7

r---

p SEN

Table 2.
PSD312 Bus
and Port
Configuration
Options

both PAD A and PAD B is the same. Using
WSI's MAPLE software, each
programmable bit in the PAD's array can
have one of three logic states of 0, 1, and
don't care (X). In a user's logic design, both
PADs can share the same inputs using the
X for input signals that are not supposed to
affect other functions. The PADs use
reprogram mabie CMOS EPROM
technology and can be programmed and
erased by the user.

ADO-AD7

=

2. PSD312 configured for nonmultiplexed address/data, 8-bit bus.

Addresses AO-A7 multiplexed with data lines DO-D7.

Multiplexed Address/Data

Non-Multiplexed Address/Data

B-bit Data Bus
I/O or low-order address
lines or Low-order multiplexed
address/data byte

DO-D7 data bus byte

Port B

I/O or CSO-CS7

I/O and/or CSO-CS7

ADO/AO-AD7/A7

Low-order multiplexed
address/data byte

Low-order address bus byte

A8-A15

High-order address bus byte

High-order address bus byte

Port A

-------------------------------------~~~Jr-----------------------------------2-133

II

PSD312

Figure 3.
PSD312 PAD
Description

I

I

II

I

I I

I

i

I

H

i

I I

I

I

I

ES3

-D----- ES4

.I

8 EPROM BLOCK
SELECT LINES

-D----- ES5

PAD

ES6
I

II

I

WR or Riw

till I. II

"d= ;:\- ft·

--'.[;L'

~.

11-

A1S

ii.1;· r--o-- g~~6,~RT} ~::::~:::RESS

It

~ f'Q-

A

ES7

---0--- RSO-S RAM BLOCK SELECT

+i-++-I++t-tl-~-

1Ht+1t-tl
1-tt*it-'lcHt-tl-~-

CSADOUTl

V:~-:~il~~~~~'~~~'~'~~~~~~'~~~~==:
Ns -t
; It r
~c::j
j

,

CONTROL SIGNALS

CSADOUT2
eSO/PBO

I!

it-" . H=H-T

:1 ~!=1.~'---r---.--

eSl/PBl

--

CS2/PB2

PAD
B

C$7/PB7

~f~ I--~I-:Ht-h-'i'-titt-+lht-+t

II

I III i i i

i--I>-{>o----o--{:>o-----

ess/peo
CS9/PC1

1!.!·!II'lil~
I
II
CS10/PC2
.1

II I i , II

.i

NOTES: 2. CSI is a power·down signal. When high. the PAD is in stand-by mode and all its outputs
become non-active. See Tables 10 and 11.
3. RESET deselects all PAD output signals. See Tables 8 and 9.
4. A18, A17, and A16 are internally multiplexed with CS10, CS9, and CS8, respectively.
Either A 18 or CS1 0, A 17 or CS9, and A 16 or CS8 can be routed to the external pins of
Port C. Port C can be configured as either input or output.

-----------------------~~~~----------------------

2-134

PSD312

Tab/e3.
PSD312 PAD A
andS/IO
Functions

Function
PAD A and PAD B Inputs
CSI or A19

In CSI mode (when high), PAD deselects all of its outputs and enters a
power-down mode (see Tables 10 and 11). In A19 mode, it is another
input to the PAD.

A16-A18

These are general purpose inputs from Port C. See Figure 3, Note 4.

A11-A15

These are address inputs.

PD-P3
RD or E
WRorR/W
ALE
RESET

These are paae number inputs.
This is the read pulse or enable strobe input.
This is the write pulse or RIW select signal.
This is the ALE input to the chip.
This deselects all outputs from the PAD; it can not be used in product
term eguations. See Tables 8 and 9.

PAD A Outputs
ESO-ES7

These are internal chip-selects to the 8 EPROM banks. Each bank can be
located on any boundary that is a function of one product term of the PAD
address inputs.

RSO

This is an internal chip-select to the SRAM. Its base address location is a
function of one term of the PAD address inputs.

CSIOPORT

This internal chip-select selects the I/O ports. It can be placed on any
boundary that is a function of one product term of the PAD inputs. See
Table 6.

CSADIN

This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the input
direction of Port A. CSADIN is gated externally to the PAD by the internal
read signal. When CSADIN and a read operation are active, data
presented on Port A flows out of ADO/AO-AD7/A7. This chip-select can be
placed on any boundary that is a function of one product term of the PAD
inputs. See Figure 5.

CSADOUT1

This internal chip-select, when Port A is configured as a low-order
address/data bus in track mode (CPAF2 = 1), controls the output direction
of Port A. CSADOUT1 is gated externally to the PAD by the ALE signal.
When CSADOUT1 and the ALE signal are active, the address presented
on ADO/AD-AD7/A7 flows out of Port A. This chip-select can be placed on
any boundary that is a function of one product term of the PAD inputs.
See Figure 5.

CSADOUT2

This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT2 must include the write-cycle control
signals as part of its product term. When CSADOUT2 is active, the data
presented on ADO/AO-AD7/A7 flows out of Port A. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure 5.

PAD B Outputs
CSO-CS3

These chip-select outputs can be routed through Port B. Each of them is
a function of up to four product terms of the PAD inputs.

CS4-CS7

These chip-select outputs can be routed through Port B. Each of them is
a function of up to two product terms of the PAD inputs.

CS8-CS10

These chip-select outputs can be routed through Port C. See Figure 3,
Note 4. Each of them is a function of one product term of the PAD inputs.

-------------------------~Jri------------------------2-135

PS0312

Configuration
Bits

Table 4.
PSD312
Non-Volatile
Configuration
Bits

The configuration bits shown in Table 4 are
non-volatile cells that let the user set the
device, 1/0, and control functions to the
proper operational mode. Table 5 lists all
configuration bits. The configuration bits
are programmed and verified during the

Use This Bit
CADDRDAT
CEDS
CA19/CSI
CALE
CPAF2
CSECURITY
CRESET
COMB/SEP
CPAF1
(8 Bits)
CPACOD
(8 Bits)
CPBF
(8 Bits)
CPBCOD
(8 Bits)
CPCF
(3 Bits)

To
Set the addressldata bus to multiplexed or non-multiplexed mode.
Determine the polarity and functionality of read and write.
Set A19/CSI to CSI(power-dowQL or A19 input.
Set the ALE polarity.
Set Port A either to track the low-order byte of the addressldata
multiplexed bus or to select the 1/0 or address option.
Set the security on or off (a secured part can not be duplicated).
Set the RESET polarity.
Set PSEN and RD for combined or separate address spaces
(see Figures 8 and 9).
Configure each pin of Port A in multiplexed mode to be an 1/0 or
address output.
Configure each pin of Port A as an open drain or active CMOS
pull-up output.
Configure each pin of Port B as an 1/0 or a chip-select output.
Configure each pin of Port B as an open drain or active CMOS
pull-up output.
Configure each pin of Port C as an address input or a chip-select output.

CADDHLT

Configure pins A 16-A19 to go through a latch or to have their
latch transparent.

CAD LOG
(4 Bits)

Configure A16-A19 individually as logic or address inputs.

CLOT
CRRWR

Port Functions

programming phase. In operational mode,
they are not accessible. To simplify implementing a specific mode, use the WSI's
PSD312 MAPLE software to set the bits.

Determine in non-multiplexed mode if address inputs are transparent
or latched.
Configure the polarity and control methods of read and write cycles.

The PSD312 has three 1/0 ports (Ports A,
B, and C) that are configurable at the bit
level. This permits great flexibility and a
high degree of customization for specific

applications. The following is a description
of each port. Figure 4 shows the pin
structure of Port A.

---------------------------~Jf;--------------------------2-136

PSD312

Figure 4.
PortA Pin
Structure

I
N

T

E I-------------------------------~
R
N

A I------~
L

A
D
D

WRITE DATA CK

OUT

OFF

1 - - - - - - \ DR

R

ENABLE

I

ALE

D

G

A

T __I--------l

AD DR

MUX

LATCH

•

D
R

A

ADI/DI
B __I---------------------~I
U

S
A
D

1-1f----------C

a J-I------rr;----,

I
A

CONTROL

WRITEDIR

D

7
RESET

NOTE: 5. CMOS/OD determines whether the output is open drain or CMOS.

Figure 5.
PortA Track
Mode
WRorRiW

-I
CSADIN

RD/E
ADO-AD7

PAc-PA7
INTERNAL
ALE

ALE or AS

•

AD8-AD15

•

LATCH A11-A15

PAD
CSADOUT2 (6)

A16-A19

NOTE: 6. The expression for CSADOUT2 must include the following write operation cycle signals:
For CRRWR = 0, CSADOUT2 must include WR = O.
For CRRWR = 1, CSADOUT2 must include E = 1 and R/W = O.

---------------------------------------~~~~-------------------------------------2-137

PSD312

Table 5.

PSD312

Configuration
Bitsl,B

Configuration
Bits

No.
of Bits

CADDRDAT

1

ADDRESS/DATA Multiplexed (separate buses)
CADDRDAT = 0, non-multiplexed
CADDRDAT = 1, multiplexed

CA19/CSI

1

A19 or CSI
CA19/CSI = 0, enable power-down
CA 19/CSI = 1, enable A 19 input to PAD

CALE

1

Active HIGH or Active LOW
CALE = 0, Active high
CALE = 1, Active low

CRESET

1

Active HIGH or Active LOW
CRESET = 0, Active low RESET
CRESET = 1, Active high RESET

COMB/SEP

1

CPAF2

1

CADDHLT

1

A 16-A 19 Transparent or Latched
CADDHLT = 0, Address latch transparent
CADDHLT = 1, Address latched (ALE dependent)

CSECURITY

1

SECURITY OnlOff
CSECURITY = 0, off
CSECURITY = 1, on

1

AO-A 15 Address Inputs are transparent or
ALE-dependent in non-multiplexed modes
CLOT = 0, transparent
CLOT = 1, ALE-dependent

CRRWR
CEDS

2

Determine the polarity and control methods of
read and write cycles.
CEDS CRRWR
R~and WR active low pulses
1
R/Y'{ status and high.E. pulse
1
1
RIW status and low DS pulse

CPAF1

8

Port A 1/0 or AO-A?
CPAF1 = 0, Port A pin is 1/0
CPAF1 = 1, Port A pin is Ai (0

CPACOD

8

Port A CMOS or Open Drain Output
CPACOD = 0, CMOS output
CPACOD = 1, open-drain output

CPBF

8

Port B is 1/0 or CSO- CS?
CPBF = 0, Port B pin is CSI (0
CPBF = 1, Port B pin is 1/0

CLOT

Function

Combined or Separate Address Space
for SRAM and EPROM
= Combined, 1 = Separate
Port A ADO-AD? (address/data multiplexed bus)
CPAF2 = 0, address or 1/0 on Port A
(according to CPAF1)
CPAF2 = 1, addressldata multiplexed on Port A
(track mode)

°

°
°

°

~

i

~

~

?)

i ~ ?)

-----------------------------------~~~----------------------------------2-138

PSD312

Table 5.
PS0312
Configuration
Bits (Cont.)

Configuration
Bits

No.
of Bits

CPBCOD

8

Port B CMOS or Open Drain
CPBCOD = 0, CMOS output
CPBCOD = 1, open-drain output

CPCF

3

Port C A16-A18 or CS8-CS10
CPCF = 0, Port C pin is ~16 ~ i ~ 18)
CPCF = 1, Port C pin is CSI (8 < i < 10)

CAD LOG

4

A16-A19 Address or Logic Input
CADLOG = 0, Port C pin or A19/CSI is
logic input
CAD LOG = 1, Port C pin or A 19/CSI
is Ai (16 < i < 19)

Total Bits

50

Function

NOTES: 7. WSl's MAPLE software will guide the user to the proper configuration choice.
8. In an unprogrammed or erased part, all configuration bits are O.

Port Functions
(Cont.)

Port A in Multiplexed
Address/Data Mode
The default configuration of Port A is 110. In
this mode, every pin can be set as an input
or output by writing into the respective pin's
direction flip flop (DIR FF, in Figure 4). As
an output, the pin level can be controlled by
writing into the respective pin's data flip flop
(DFF, in Figure 4). When DIR FF = 1, the
pin is configured as an output. When DIR
FF = 0, the pin is configured as an input.
The controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the DFF bits by accessing the READ
DATA register. Port A pin levels can be
read by accessing the READ PIN register.
Individual pins can be configured as CMOS
or open drain outputs. Open drain pins
require external pull-up resistors. For
addressing information, refer to Table 6.
Alternatively, each bit of Port A can be
configured as a low-order latched address
bus bit. The address is provided by the port
address latch, which latches the address
on the trailing edge of ALE. PAD-PA7 can
become AO-A7, respectively. This feature
of the PSD312 lets the user generate loworder address bits to access external
peripherals or memory that require several
low-order address lines.

Another mode of Port A (CPAF2 = 1) sets
the entire port to track the inputs
ADO/AO-AD7/A7, depending on specific
address ranges defined by the PAD's
CSADIN, CSADOUT1, and CSADOUT2
signals. This feature lets the user interface
the microcontroller to shared external
resources without requiring external buffers
and decoders. In this mode, the port is
effectively a bi-directional buffer. The
direction is controlled by using the input
signals ALE, RD/E/DS, WRIVpp or R/W,
and the internal PAD outputs CSADOUT1 ,
CSADOUT2 and CSADIN (see Figure 5).
When CSADOUT1 and ALE are true, the
address on the input ADO/A7-AD7/A7 pins
flows out through Port A. (Carefully check
the generation of CSADOUT1 , and ensure
that it is stable during the ALE pulse; see
Figure 18). When CSADOUT2 is active, a
write operation is performed (see note to
Figure 5). The data on the input
ADO/A7-AD7/A7 pins flows out through
Port A. When CSADIN and a read operation is performed (depending on the mode
of the RD/EIDS and WRIVpp or R/W pins),
the data on Port A flows out through the
ADO/A7-AD7/A7 pins. In this operational
mode, Port A is tri-stated when none of the
above-mentioned three conditions exist.

-------------------------------------~~~-----------------------------------2-139

•

PSD312

Port Functions
(Cont.)

Port A in Non-Multiplexed
Address/Data Mode
In this mode, Port A becomes the low order
data bus byte of the chip. When reading an
internal PSD312 location, data is presented
on Port A pins. When writing to an internal
PSD312 location, data present on Port A
pins is written to that location.

PortS
The default configuration of Port B is I/O. In
this mode, every pin can be set as an input
or output by writing into the respective pin's
direction flip flop (DIR FF, in Figure 6). As
an output, the pin level can be controlled by
writing into the respective pin's data flip flop
(DFF, in Figure 6). When DIR FF = 1, the
pin is configured as an output. When DIR
FF = 0, the pin is configured as an input.
The controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the DFF bits by accessing the READ
DATA register. Port B pin levels can be
read by accessing the READ PIN register.
Individual pins can be configured as CMOS
or open drain outputs. Open drain pins
require external pull-up resistors. For
addressing information, refer to Table 6
Alternatively, each bit of Port B can be
configured to provide a chip-select output
~al from PAD B. PBO-PB7 can provide
CSO-CS7, respectively. Each of the signals
CSO-CS3 is comprised of four product
terms.Thus, up to four ANDed expressions
can be ORed while deriving ~ of these
signals. Each of the signals CS4-CS7 is
comprised of two product terms. Thus, up
to two ANDed expressions can be ORed
while deriving any of these signals.

Accessing the I/O Port Registers
Table 6 shows the offset values with the
respect to the base address defined by the
CSIOPORT. They let the user access the
corresponding registers.

Port C in All Modes
Each pin of Port C (shown in Figure 7) can
be configured as an input to PAD A and
PAD B or output from PAD B. As inputs,
the pins are named A 16-A 18. Although the
pins are given names of the high-order
address bus, they can be used for any
other address lines or logic inputs to PAD A
and PAD B. For example, A8-A 10 can also
be connected to those pins, improving the
boundaries of CSO-CS7 resolution to 256
bytes. As inputs, they can be individually
configured to be logic or address inputs. A
logic input uses the PAD only for Boolean
equations that are implemented in any or
all of the CSO-CS1 0 PAD B outputs. Port C
addresses can be programmed to latch the
inputs by the trailing edge ALE or to be
transparent.
Alternatively, PCO-PC2 can become
CS8-CS10 outputs, respectively, providing
the user with more external chip-select
PAD outputs. Each of the signals
CS8-CS 10 is comprised of one product
term.

ALE/AS and ADO/AD-A01/Al in
Non·Multiplexed Modes
In non-multiplexed modes, ADO/AOAD15/A 15 are address inputs only and can
become transparent (CLOT = 0) or ALE
dependent (CLOT = 1). In transparent
mode, the ALE/AS pin can be used as an
additional logic input to the PADs. The nonmultiplexed ALE dependent mode is useful
in applications for which the host processor
has a multiplex address/data bus and
ADO/AO-AD7/A7 are not multiplexed with
AO-A7 but rather are multiplexed with other
address lines. In these applications, Port A
serves as a data bus and each of its pins
can be directly connected to the corresponding host's multiplexed pin, where that
data bit is expected. See Table 7.

-------------------------------------~~jr------------------------------------2-140

PSD312

Figure 6.
PortB Pin
Structure

Figure 6 shows the structure of Port B.
N
T
E
R

N
A
L

c

s

o
U
T
B
U

I
N
T
E
R
N
A
L

READ DATA
CMOS/OD(9)
WRITE DATA

OFF
D

D
A
T
A

R

.~

DI

PORT B PIN

ENABLE

MUX

B
U
S

•

CSI
D
8

D
1

7

hl

OUT

CK

S

C
S

READ PIN

5

READ DIR

D
WRITEDIR

orR

CONTROL

CK FF
R

I

RESET

NOTE: 9. CMOS/aD determines whether the output is open drain or CMOS.

Table 6.
I/O Port
Addresses in an
8-bit Data Bus
Mode

Byte Size Access of the I/O Port Registers
Offset from the CSIOPORT

Register Name
Pin Register of Port A

+ 2 (accessible during read operation only)

Direction Register of Port A

+4

Data Register of Port A

+6

Pin Register of Port B

+ 3 (accessible during read operation only)

Direction Register of Port B

+5

Data Register of Port B

+7

-----------------------------------fjrjrjF:----------------------------------~I!E=

2-141

PSD312

Figure 7.
Port CStructure

ADDRESS INDICATOR

(NOTE 10)
A16
I - -.......~TOPAD

CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL

FROM PAD

ALE

A17
!--""".TOPAD
FROM PAD

A18
PC2

I---~TOPAD

!

r--L~~~CS~1~0~(O~U~T~PU~T~L~IN~E~)_ _ _ _ _ _ _ FROMPAD
TO
EPROM

NOTE: 10. The CADDHLTconfiguration bit determines if A18-A16 are transparent via the latch, or if
they must be latched by the trailing edge of the ALE strobe.

Table 7.
Signal Latch
Status in All
Operating
Modes

Signal
Name

Configuration
Bits

PSEN

Signal Latch
Status

non-multiplexed
modes

Transparent
ALE
Dependent

CADDRDAT= 1

multiplexed modes

ALE
Dependent

CDATA=O

8-bit data,
PSEN is active

Transparent

CADDHLT = 0

A16-A19 can
Transparent
become logic inputs

CADDHLT= 1

A16-A19 can
become
multiplexed
address lines

CADDRDAT = 0, CLOT = 0
ADO/AOAD7/A7

Configuration
Mode

CADDRDAT = 0, CLOT = 1

A19 and
PC2-PCO

ALE
Dependent

-------------------------------------~~Ar-----------------------------------2-142

P50312

EPROM

The PS0312 has 512K bits of EPROM
and is organized as 64K x 8. The EPROM
has 8 banks of memory. Each bank can
be placed in any address location by
programming the PAD. BankO-Bank? can

SRAM

The PS0312 has 16K bits of SRAM and is
organized as 2K x 8. The SRAM is selected
by the RSO output of the PAD.

Page Register

The page register consists of four flip-flops,
which can be read from, or written to,
through the 1/0 address space
(CSIOPORT). The page register is
connected to the 03-00 lines. The Page
Register address is CSIOPORT + 18H.
The page register outputs are P3-PO,

Control Signals

The PS0312 control signals are WR/v pp or
Rlw, RO/E/OS, ALE, PSEN, Reset, and
A 19/CSI. Each of these signals can be
configured to meet the output control signal
requirements of various microcontrollers.

WR/V" or R/W
In operational mode, this signal can be
configured as WR or RIW. As WR, all write
operations to the PS0312 are activated by
an active low signal on this pin. As R/W,
the pin works with the E strobe of the
RO/E/OS pin. When R/W is high, an active
high signal on the RO/E/OS pin performs a
read operation. When R/W is low, an active
high signal on the RO/E/OS pin performs a
write operation.

RO/E/OS
In operational mode, this signal can be
configured as RO, E, or OS. As RO, all
read operations to the PS0312 are
activated by an active low signal on this
pin. As E, the pin works with the R/W signal
of the WR/v pp or R/W pin. When R/W is
high, an active high signal on the RO/E/OS
pin performs a read operation. When R/W
is low, an active high signal on the
RO/E/OS pin performs a write operation.

be selected by PAD outputs ESO-ES?,
respectively. The EPROM banks are organized as 8K x 8.

which are fed into the PAD. This enables
the host microcontroller to enlarge its
address space by a factor of 16 (there can
be a maximum of 16 pages). See Figure 8.

ALE orAS
ALE polarity is programmable. When
programmed to be active high, a high on
the pin causes the input address latches,
Port A address latches, Port C, and A 19
address latches to be transparent. The
falling edge of ALE locks the information
into the latches. When ALE is programmed
to be active low, a low on the pin causes
the input address latches, Port A address
latches, Port C, and A 19 address latches to
be transparent. The riSing edge of ALE
locks the appropriate information into the
latches.

PSEN
The PSEN function enables the user to
work with two address spaces: program
memory and data memory (if COMB/SEP =
~this mode, an active low signal on the
PSEN pin causes the EPROM to be read if
selected. The SRAM and 1/0 ports read
operation are done by RO low (CRRWR =
0), or by E high and R/W high (CRRWR =
1, CEOS = 0) or by OS low and R/W high
(CRRWR, CEOS = 1).

As OS, the pin works with the R/W signal
as an active low data strobe signal. As OS,
the RIW defines the mode of
operation (Read or Write).

_____________________________________

r~=~E

=="'='~~

____________________________________
2-143

PS0312

Control Signals
(Cont.)

PSEN
Whenever a member of the 8031 family
(or any other similar microcontroller) is
used, the PSD312's PSEN pin must be
connected to the PSEN pin of the
microcontroller.

SRAM, and I/O ports are read by RD low
(CRRWR = 0), or by E high and R/W high
(CRRWR = 1, CEDS = 0) or by DS low
and R/W high (CRRWR, CEDS = 1). See
Figures 9 and 10.

If COMB/SEP = 0, the address spaces of
the program and the data are combined. In
this configuration (except for the 8031-type
case mentioned above), the PSEN pin
must be tied high to Vc c , and the EPROM,

Figure 8.
Page Register

,---r--------------=;
}
,---r------P1

TOPAD
INPUTS

, - - - r - - - PO

INTERNAL

RESET

INTERNAL WR
PAGE SELECT
INTERNAL RD

y
DATA BUS

Table 8.
Signal States
During and After
Reset

Signal

Configuration Mode

Condition

ADO/AO-AD7/A7

All

Input

A8-A15

All

Input

PAO-PA7)
(Port A

I/O
Tracking ADO/AO-AD7
Address outputs AO-A7

Input
Input
Low

PBO-PB7
(Port B)

I/O
CS7-CSO CMOS outputs
CS7-CSO open drain outputs

Input
High
Tri-stated

PCO-PC2
(Port C)

Address inputs A 16-A 18
CS8-CS10 CMOS outputs

Input
High

----------------------------------fjrjrjF:---------------------------------IE'
2-144

E!!'$'..;5iF

PSD312

Figure 9.
Combined
Address Space

cs

ADDRESS

PAD

SRAM

EPROM

Table 9.
Internal States
During and After
Reset

Component

Signals

PAD

Data register A
Direction register A
Data register B
Direction register B

•

Contents

CSO-CS10

All - 1 (Note 11)

CSADIN, CSADOUT1,
CSADOUT2, CSIOPORT,
RSO,ESO-ES7

All = 0 (Note 11)

n/a
n/a
n/a
n/a

0
0
0
0

NOTE: 11. All PAD OUtputs are in a non-active state.

Figure 10.
8031-Type
Separate Code
and Data
Address Spaces

INTERNAL

-RD

I

1/0 PORTS

. .

OE

I

CS

.1

ADDRESS

•

PSEN

~=16E.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ~§ §

PAD

~

•

OE
CS

SRAM

..

cs

......

OE

EPROM

____________________________

~~

2-145

PSD312

Control Signals
(Cont.)

Table 10. Signal
States During
Power-Down
Mode

RESET

A19/CSI

This is an asynchronous input pin that
clears and initializes the PSD312. Reset
polarity is programmable (active low or
active high). Wheneverthe PSD312 reset
input is driven active for at least 100 ns, the
chip is reset. During boot-up (Vee applied),
the device is automatically reset internally
(internal automatic reset is over by the time
Vee operating range has been achieved
during boot-up). Tables 8 and 9 indicate the
state of the part during and after reset.

When configured as CSI, a high on this pin
deselects, and powers down, the chip. A
low on this pin puts the chip in normal
operational mode. For PSD312 states
during the power-down mode, see Tables
10 and 11 , and Figure 11.

Signal

In A 19 mode, the pin is an additional input
to the PAD. It can be used as an address
line (CADLOG3 = 1) or as a generalpurpose logic input (CADLOG3 = 0). A 19
can be configured as ALE dependent or as
transparent input (see Table 7). In this
mode, the chip is always enabled.

Configuration Mode

Condition

ADO/AO-AD7/A7

All

Input

A8-A15

All

Input

PAO-PAl

I/O
Tracking ADO/AO-AD7/A7
Address outputs AO-A7

Unchanged
Input
A1I1's

PBO-PB7

I/O
CSO-CS7 CMOS outputs
CSO-CS7 open drain outputs

Unchanged
A1I1's
Tri-stated

PCO-PC2

Address inputs A 18-A 16
CS8-CS10 CMOS outputs

Input
A1I1's

Figure 11.
AI9/CSI Cell
Structure

ADDRESS INDICATOR
TO EPROM

ALE------------,

r

------+1

!.A'

!
-L!

A19
1-----. TO
PAD

A19/CSI/

...-"""-,~:=.:",-,,,c....:::;=-:;c=_ _ _ _ _ _. .
~.

TO PAD, EPROM, SRAM,
PORTS. LATCHES, ETC.

-=-:

NOTE:

12. The CADDHLTconfiguration bit determines if A19-A16 are transparent via the latch, or
if they must be latched by the trailing edge of the ALE strobe.

-----------------------------------~~~~----------------------------------2-146

PS0312

Table 11.
Internal States
During PowerDown

Component

Signals

PAD
Data register A
Direction register A
Data register B
Direction register B

Security Mode

All 1's (deselected)

CSADIN, CSADOUT1 ,
CSADOUT2, CSIOPORT,
RSO,ESO-ES7

All O's (deselected)

n/a
n/a
n/a
n/a

All
unchanged

Security Mode in the PSD312 locks the
contents of the PAD A , PAD B and all the
configuration bits, The EPROM, SRAM,
and I/O contents can be accessed only
through the PAD. The Security Mode can

Figure 12.
PSD312
Interface With
Intel's 80C31

Contents

CSO-CS10

be set by the MAPLE or Programming
software. In window packages, the mode is
erasable through UV full part erasure. In
the security mode, the PSD312 contents
cannot be copied on a programmer.

Vee

31

-

19

PO.O
PO.1
PO.2
PO.3
POA
PO.S
PO.6
PO.7

EANP
X1

c::::J
18

9

12
13
14
15

2
3
4
5
6
7
8

X2

RESET

INTO
INT1
TO
T1
P1.0
P1.1
P1.2
P1.3
P1A
P1.S
P1.6
P1.7

E--::L
-=-

0.1~F

Microcontroller

P2.0
P2.1
P2.2
P2.3
P2A
P2.S
P2.6
P2.7
RD

WR
PSEN
ALE
TXD
RXD

39
38
37
36
35
34
33
32

23
24
25
26
27
28
29
30

21
22
23
24
25
26
27
28

31
32
33
35
36
37
38
39

17
16
29
30
11
10

22 RD
2 WANpp
1
BHE/PSEN
13
ALE
3
RESET

ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
ADS/AS
AD6/A6
AD7/A7

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7

AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

PC2
A19/cm

11
10
9
8
7
6
5
4
40
41
42
43

GND

PSD312

80C31

PCO
PC1

21
20
19
18
17
16
15
14

34

12

-

The configuration bits for Figure 12 are:
CRESET

1

COMB/SEP

o or 1 (both valid)

CALE

0

CRRWR

0

CDATA

0

CEDS

0

CADDRDAT
All other configuration bits may vary according to the application requirements.

-------------------------------------~~~~------------------------------------

2-147

•

PS0312

System
Applications

Figure 13.
PS0312
Interface With
Motorola's
68HCl1

In Figure 12, the PSD312 is configured to
interface with Intel's 80C31 , which is a 16bit address/8-bit data bus microcontroller.
Its data bus is multiplexed with the loworder address byte. The 80C31 uses
signals RD to read from data memory and
PSEN to read from code memory. It uses
WR to write into the data memory. It also
uses active high reset and ALE signals.
The rest of the configuration bits as well as
the unconnected signals (not shown) are
application specific and, thus, user
dependent.

In Figure 13, the PSD312 is configured to
interface with Motorola's 68HC11, which is
a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the
low-order address byte. The 68HC11 uses
E and Riw signals to derive the read and
write strobes. It uses the term AS (address
strobe) for the address latch pulse. RESET
is an active low signal. The rest of the
configuration bits as well as the unconnected signals (not shown) are application
specific and, thus, user dependent.

Vee

pco

20
21
22
23
24
25

PDO
PD1
PD2
PD3
PD4
PD5

43
45
47
49
44
46
48
50

PEO
PE1
PE2
PE3
PE4
PE5
PE6
PE7

34
33
32
31
30
29
28
27

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

52
51

VRH
VRL

PC1
PC2
PC3
PC4
PC5
PC6
PC7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

9
10
11
12
13
14
15
16

23
24
25
26
27
28
29
30

42
41
40
39
38
37
36
35

31
32
33
35
36
37
38
39

5

22

6
4
17

2
13
3

E

Riii
AS

RESET
Xi"RQ
IRQ
MODB
MODA
XTAL

~
-=-

0.1~F

Microcontroller

18
19
2
3

ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

E

PCO
PC1

RiWNpp
AS

M/PSEN'"
Vee
GND

EXTAL

PSD3l2

68Hell

PC2
A19/CSI

RESET

34

12

-

The configuration bits for Figure 13 are:
CRESET

0

COMB/SEP

CALE

0

CRRWR

CDATA

0

CEDS

0
0

CADDRDAT
All other configuration bits may vary according to the application requirements.

2-148

'I: sr:

!!!!!!!l!"!!IF.:="~

21
20
19
18
17
16
15
14
11
10
9
8
7
6
5
4
40
41
42
43

I'S0312

Absolute
Maximum
Ratings'3

Symbol

Parameter

TSTG

Storage Temperature
Voltage on any Pin
Programming
Supply Voltage
Supply Voltage
ESD Protection

Vpp
Vce

Condition

Min

Max

Unit

With Respect to GND

-65
-0.6

+ 150
+7

°C
V

With Respect to GND

-0.6

+14

V

With Respect to GND

-0.6

+7
>2000

V
V

NOTE: 13. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.

Operating
Range

Range

Temperature

Commercial
Industrial
Military

Recommended
Operating
Conditions

DC

Characteristics

Symbol

0° C to +70°C
-40° C to +80°C
-55° C to +125°C

Parameter

vee

Supply Voltage

Vee
V1H
VIL

Supply Voltage
High-level Input Voltage
Low-level Input Voltage

Symbol
VOL

VOH

Parameter
Output Low Voltage

Output High Voltage

ISB1

Vee Standby Current
(CMOS) (Notes 14 and 16)

ISB2

Vee Standby Current
(TTL) (Notes 15 and 16)
Active Current (CMOS)

lee1

(SRAM Not Selected)
(Notes 14 and 17)

Tolerance

Vee
+5V
+5V
+5V

·12

·15

·20

±5%

±10%
±10%
±10%

±10%
± 10%
±10%

Typ Max Unit

Conditions

Min

-12 Version

4.75

5

5.25

V

-15/-20 Versions
Vee = 4.5 V to 5.5 V
Vee = 4.5 V to 5.5 V

4.5
2
0

5

5.5

V
V
V

Conditions
IOL = 20 I!A
Vee = 4.5 V
IOL= 8 mA
Vee = 4.5 V
IOH = -20 I!A
Vec = 4.5 V
IOH =-2 mA
Vee = 4.5 V
Comm'l

0.8

Min Typ Max Unit
0.01

0.1
V

0.15 0.45
4.4

4.49

2.4

3.9

V
50

100

Ind/Mil

75

Comm'l
Ind/Mil

1.5
2

150
3
3.2
35

Comm'l (Note 18)

16

Comm'l (Note 19)

28

50

Ind/Mil (Note 18)

16

45

Ind/Mil (Note 19)

28

60

!!A
mA

mA

--------------------------------~~;-------------------------------
~~~~

2·149

•

PSD312

DC
Characteristics
(Cont.)

Symbol
Icc2

Parameter

Conditions

Active Current (CMOS)
(SRAM Block Selected)
(Notes 14 and 17)
Active Current (TTL)

Icc3

(SRAM Not Selected)
(Notes 15 and 17)
Active Current (TTL)

Icc4

(SRAM Block Selected)
(Notes 15 and 17)

Min Typ Max Unit

Comm'l (Note 18)

47

80

Comm'l (Note 19)

59

95

Ind/Mil (Note 18)

47

100
115

Ind/Mil (Note 19)

59

Comm'l (Note 18)

36

65

Comm'l (Note 19)

58

80

Ind/Mil (Note 18)

36

80

Ind/Mil (Note 19)

58

95

Comm'l (Note 18)

67

105

Comm'l (Note19)

79

120

Ind/Mil (Note 18)

67

130

79

145

Ind/Mil (Note 19)
~

III

Input Leakage Current

VIN

5.5 V or GND

ILO

Output Leakage Current

VOUT

~

5.5 V or GND

-1

± 0.1

1

-10

±5

10

mA

mA

mA

~A

NOTE: 14. CMOS inputs: GND ± 0.3 Vor Vcc ± 0.3V.
15. TTL inputs: VIL::;; 0.8 V, V1H ~ 2.0 V.
16. CSI/A19 is high and the part is in a power-down configuration mode.
17. AC power component is 3.0 mA/MHz (power = AC + DC).
18. Ten (10) PAD product terms active. (Add 380 !lA per product term, typical, or 480 ILA
per product term maximum.)
19. Forty-one (41) PAD product terms active.

AC
Characteristics
(See Timing
Diagrams)

Symbol

Parameter

Min

·12
Max

·15
Min Max

·20
Unit
Min Max

T1

ALE or AS Pulse Width

30

40

T2

Address Set-up Time

9

12

15

T3

Address Hold Time

13

15

25

T4

ALE or AS Trailing Edge
to Leading Edge of Read

12

15

20

T5

ALE Valid to Data Valid

130

140

170

T6

Address Valid to
Data Valid

T7
T8

CSI Active to Data Valid
Leading Edge of Read to
Data Valid

50

120

150

200

130

160

200

38

55

60

T9

Read Data Hold Time

T10

Trailing Edge of Read to
Data High-Z

T11

Trailing Edge of ALE
or AS to Leading
Edge of Write

12

15

20

T12

RD, E, PSEN, DS
Pulse Width

45

60

75

T12A

0

0
32

40

35

WR Pulse Width

25

35

45

T13

Trailing Edge of Write or
Read to Leading Edge
of ALE or AS

0

0

0

T14

Address Valid to Trailing
Edge of Write

120

150

200

...

ns

0

---------------------------------~~~-----------------------------------,..

2-150

~

PS0312

AC
Characteristics
(Cont.)

Symbol

Parameter

-12
-15
-20
Unit
Min Max Min Max Min Max

T15

CSI Active to Trailing
Edge of Write

130

160

200

T16

Write Data Set-up Time

20

30

40

T17

Write Data Hold Time

5

10

15

T18

Port Input Set-up Time

30

35

45

T19

Port Input Hold Time

0

0

0

T20

Trailing Edge of Write
to Port Output Valid

40

50

60

T21

ADi or Control to
CSOi Valid

6

35

6

40

5

45

T22

ADi or Control to
CSOi Invalid

5

35

4

40

4

45

T23

Track Mode Address
Propagation Delay:
CSADOUTI Already True

22

28

28

Track Mode Address
Propagation Delay:
CSADOUTI Becomes
True During ALE or AS

33

50

50

T23A

T24

Track Mode Address
Holding Time

T25

Track Mode Read
Propagation Delay

T26

Track Mode Read
Hold Time

T27

Track Mode Write Cycle
Data Propagation Delay

T28

Track Mode Write Cycle
Write to Data Propagation
Delay

8

T29

Hold Time of Port A Valid
During Write CSOi
Trailing Edge

2

T30

CSI Active to CSOi Active

9

45

9

55

8

60

T31

CSI Inactive to CSOi
Inactive

9

45

9

55

8

60

T32

Direct PAD Input as
Hold Time

10

12

15

T33

R/W Active to E or
OS Start

20

30

40

T34

E or OS End to R/W

20

30

40

T35

AS Inactive to E High

15

20

25

15

27
29

11

29

35
10

29

7

40

4

ns
35

10

30

20

30

27

•

35
30

7

55

4

NOTES: 20. ADi = any address line.
21. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or
through Port C (CS8-CS10).
22. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent
A19, RD/E/DS, WR or R/W, transparent PCO-PC2, ALE (or AS).
23. Control signals RD/E/DS or WR or R/W.

-------------------------------------rJif~~~-----------------------------------="~~E

2-151

PSD312

Figure 14.
Timing of 8-Bit
Multiplexed
AddreSS/Data
Bus. CRRWR = 0

...

READ CYCLE

-

~

CS I/At9
as CSI

1\
7

32

. ...
~I

WRITE CYCLE

Direct (24)
PAD In put

Multiplex ed(25)
Inputs

.:z:

00<

STABLE INPUT
6

X

15

6

~

STABLE INPUT

DATA
\ OUT

----.

--

XXXX XXXX
14

4

J.Cf-

ADDRESS B

~

81-

~

Active Low'
,---.J
ALE

f4~
RD/E/DS asRD

A

D~~A

}-

3

h

.-2....

.XXX .XXX

14

~

ADDRESS A
2
3

Active High r
ALE'

32

mY.XX DO XXX

~

AOIADOA7lAD? -

~~

- VXX' 'XXXX
~

2

I-

..

32

I

XA

~~ ~

-

L

11

f.--I

'--

~

f-'

5
BHE/P-SEN
asP-SEN

f-'

~

or
sWR

~

pp

Any of PAOPA7 as IIOPin

)0 :XXXXXXXXX·

Any of PBOPB7 as 1/o Pin

I

Any of PAOPA7 Pins
as Ad dress
Outputs

yj ixxxxxxffl

~
INPUT

INPUT

-

r------'

19

~
lXIXXXXXXXXX~

OUTPUT

:)(IXXXXXXXXXXXXXXXXXXX

OUTPUT

~

~
ADDRESS A

ADDRESS B

See referenced notes on page 2-157.

----------------------------------rArArAr~--------------------------------5I!F!iEJE E
2-152

PSD312

Figure 15.
Timing of B-Bit
Multiplexed
Address/Data
Bus, CRRWR = 1

..

READ CYCLE

----.
CS I/A19
asCSI

Direct (24)
PAD Input

Multiplex ed
Inputs

(25)

1-

~
X

STABLE INPUT
6

IXXXXXX n

-

Active High
AS J

10ATA

ADDRESS A
2

\

-

3

Irh

4

OUT

I-

'XX IXXXX

15

32

~~

STABLE INPUT

32

IIXXX :XXX

•

XXXX IX~
14

~I-

}- V DATA
IN

ADDRESS B

~

81-

3

~

h

~
35
33

-

14

xw

~r!--

Active Low \
AS

..
-32

~

6

AOIADOA?lAD?

WRITE CYCLE

p

I

7

.:x

. ..

-IJ~
32

12

~

.....:;

~34

XX

~ It-

35

f--I

'33

~
J

34

1-

RD/E/DS as E
5

~~

-

~

I'--I-J

RD/E/DS asDS

WRNp p Q!

~
Any of PAOPAY as 110 Pin

~

Any of PBOPB? as 110 Pin

~

It-

,XXXXX

IXXXJ(XXX

RiWas RIW

~

~

~

XXXXXXXXX

INPUT

.XIXXXXXXXXXXXXXXXXXXX

OUTPUT

XXXXXXXXX

INPUT

.XIXXXXXXXXXXXXXXXXXXY'

OUTPUT

Any of PAO~
PAY Pins -'----.
as Add ress
Outputs

-

~
ADDRESS A

ADDRESSB

See referenced notes on page 2-157.

----------------------------------;I;~~--------------------------------"# W >0,,0;::;;( U'"c.. Uc.. Uc..0
m c..
m c..
~ ;= ~
c.. '"
M
M
'" :;: ...0
It)

Figure 23
DrawingL444 Pin Ceramic
Leaded Chip
Carrier (CLDCC)
with Window
(Package Type

'"

7 [

PB3

8

PB2

9

PBO 11

L)

GND 12
ALE or AS 13
PA7 14
PA6 15
PA5 16
PA4 17

...

'"

...... ... ...

~

U

"'
/ U U [.. j UU U UU ......j c::.
p 39 A15
.:·::i
C.:·.
p 38 A14
[ ::::i
,. :.:. b 37 A13
[ ..: ..:i
,.::". p 36 A12
[ ..:::i
C:... b 35 All
[::::i
C:... p 34 GND
[ ::::i
c::. p 33 Al0
[ ::::i
[ ..:::i
C::. b 32 A9
C::. b 31 A8
[ : ......i
,.:::. p 30 AD7/A7
[ ..:::i
,.:::. p 29 AD6/A6
[ ::::i

PB4

PBl 10

It)

[ j [

o

\. [.] [.] [.] [.] ;.];-] [.] ;-] [·1 [.] [.] /
~ ~
M

0

'"

N

iii ~

'" ~ '"
ICC

M

'"

0
'"c.. u
c.. c..
0

" 0;
u
~

>"

W

~ ;= ~



B'HEIPSEN
WRNPP

R1i
ALE

PSD303

~

20

I ~

PCO
PCl
PC2

2- Fi'ESei'

6

BUS

~

21

PBO
PBl
PB2
PB3
PB4
PBS

,--£- Csi/A19

--?-

SHARED

"

GND

GND

U.J.!

~
~

~

The configuration bits for Figure 14 are:
CRESET
CALE
CDATA
CADDRDAT
CPAF1
CPAF2

o
o

CA19/CSI

1

CRRWR
COMB/SEP
CADDHLT

o
o
o

Don't care
1

ii'_iES~

CSECURITY
CPCF2, CPCF1, CPCFO
CPACOD7-CPACODO
CPBF7-CPBFO
CPBCOD7-CPBCODO
CEDS
CADLOG3-CADLOGO

Don't care
0, 0, 0
OOH
OOH
18H

o
OH

-2---1-8-8-----------------------------------------~~~-----------------------------------------------

P50303

Absolute
Maximum
Ratings '5

Symbol

Parameter

Condition

Min

Max

Unit

-65

+ 150

°C

Voltage on any Pin

With Respect to GND

-0.6

+7

V

Vpp

Programming
Supply Voltage

With Respect to GND

-0.6

+14

V

Vee

Supply Voltage

With Respect to GND

-0.6

+7

V

>2000

V

T STG

Storage Temperature

ESD Protection

NOTE: 15. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.

Operating
Range

Recommended
Operating
Conditions

DC
Characteristics

Range

Temperature

Commercial

0° C to +70°C

+5V

Industrial

-40° C to +80°C

Military

-55° C to + 125°C

Symbol

Parameter

Tolerance

Vcc

-12

-15

-20

±5%

±10%

±10%

+5V

± 10%

± 10%

+5V

± 10%

± 10%

Typ Max Unit

Conditions

Min

Vee

Supply Voltage

-12 Version

4.75

5

5.25

V

Vee
V1H

Supply Voltage

-15/-20 Versions

4.5

5

5.5

V

High-level Input Voltage

Vee = 4.5 V to 5.5 V

2

VIL

Low-level Input Voltage

Vee = 4.5 V to 5.5 V

0

Symbol
VOL

VOH

ISB1
ISB2

Parameter
Output Low Voltage

Output High Voltage

0.01

0.1

IOL= 8 mA
Vee = 4.5 V

0.15

0.45

V

IOH =-20 ~A
Vee=4.5V

4.4

4.49

IOH =-2 mA
Vee =4.5 V

2.4

3.9

V

Comm'l

50

100

(CMOS) (Notes 16 and 18)

Ind/Mil

75

150

Vee Standby Current

Comm'l

1.5

3

(TIL) (Notes 17 and 18)

Ind/Mil

2

3.2

(SRAM Not Selected)
(Notes 16 and 19)

F_S"~

V

Min Typ Max Unit

IOL = 20 ~A
Vee = 4.5 V

Vee Standby Current

Active Current (CMOS)
lee1

Conditions

V
0.8

Comm'l (Note 20)

16

35

Comm'l (Note 21)

28

50

Ind/Mil (Note 20)

16

45

Ind/Mil (Note 21)

28

60

~A

mA

mA

-----------------------------------~~;-------------------------------2---18--9

•

PSD303

DC
Characteristics
(Cont.)

Symbol

Parameter
Active Current (CMOS)
(SRAM Block Selected)
(Notes 16 and 19)

ICC2

Active Current (TTL)
ICC3

(SRAM Not Selected)
(Notes 17 and 19)
Active Current (TTL)

ICC4

(SRAM Block Selected)
(Notes 17 and 19)

Conditions

Min Typ Max Unit

Comm'l (Note 20)

47

80

Comm'l (Note 21)

59

95

Ind/Mil (Note 20)

47

100

Ind/Mil (Note 21)

59

115

Comm'l (Note 20)

36

65

Comm'l (Note 21 )

58

80

Ind/Mil (Note 20)

36

80

Ind/Mil (Note 21)

58

95

Comm'l (Note 20)

67

105

Comm'l (Note 21)

79

120

Ind/Mil (Note 20)

67

130

79

145

Ind/Mil (Note 21)
III

Input Leakage Current

VIN = 5.5 V or GND

ILO

Output Leakage Current

VOUT = 5.5 V or GND

NOTE:

AC
Characteristics
(See Timing
Diagrams)

± 0.1

1

-10

±5

10

CMOS inputs: GND ± 0.3 Vor Vee ± 0.3V.
TTL inputs: V 1L " 0.8 V, V1H 2 2.0 V.
CSIIA19 is high and the part is in a power-down configuration mode.
AC power component is 3.0 mA/MHz (power = AC + DC).
Ten (10) PAD product terms active. (Add 380 ~A per product term, typical, or 480
per product term maximum
21. Forty-one (41) PAD product terms active.

16.
17.
18.
19.
20.

Symbol

Parameter

T1

ALE or AS Pulse Width

30

40

Address Set-up Time

9

12

15

T3

Address Hold Time

9

12

15

T4

ALE or AS Trailing Edge
to Leading Edge of Read

12

15

20

T5

ALE Valid to Data Valid

130

140

170

T6

Address Valid to
Data Valid

T8

CSI Active to Data Valid
Leading Edge of Read to
Data Valid

mA

~A

~A

50

120

150

200

130

160

200

38

55

60

T9

Read Data Hold Time

T10

Trailing Edge of Read to
Data High-Z

T11

Trailing Edge of ALE
or AS to Leading
Edge of Write

12

15

20

T12

RD,E,PSEN,DS
pulse width

45

60

75

T12A

WR Pulse Width

25

35

45

T13

Trailing Edge of Write or
Read to Leading Edge
of ALE or AS

0

0

0

T14

Address Valid to Trailing
Edge of Write

120

150

200

___________________________________

mA

·12
·15
·20
Unit
Min Max Min Max Min Max

T2

T7

2-190

-1

mA

0

0
32

0
35

ns
40

r~~=r:-----------------------------------

PS0303

AC
Characteristics
(Cont.)

Symbol

Parameter

-12

-15

Min

Max Min

Max Min

-20
Unit
Max

T15

CSI Active to Trailing
Edge of Write

130

160

200

T16

Write Data Set-up Time

20

30

40

T17

Write Data Hold Time

5

10

15

T18

Port Input Set-up Time

30

35

45

T19

Port Input Hold Time

0

0

0

T20

Trailing Edge of Write
to Port Output Valid

40

50

60

T21

ADi or Control to
CSOi Valid

6

35

6

40

5

45

T22

ADi or Control to
CSOi Invalid

5

35

4

40

4

45

T23

Track Mode Address
Propagation Delay:
CSADOUT1 Already True

22

28

28

Track Mode Address
Propagation Delay:
CSADOUT1 Becomes
True During ALE or AS

33

50

50

T23A

T24

Track Mode Address
Holding Time

T25

Track Mode Read
Propagation Delay

T26

Track Mode Read
Hold Time

T27

Track Mode Write Cycle
Data Propagation Delay

T28

Track Mode Write Cycle
Write to Data Propagation
Delay

8

T29

Hold Time of Port A Valid
During Write CSOi
Trailing Edge

2

T30

CSI Active to CSOi Active

9

45

9

55

8

60

T31

CSllnactive to CSOi
Inactive

9

45

9

55

8

60

T32

Direct PAD Input as
Hold Time

10

12

15

T33

R/W Active to E or
OS Start

20

30

40

T34

E or OS End to R/W

20

30

40

T35

AS Inactive to E high

15

20

25

15

27
29

11

29
20
30

29

35
10

30
7

ns

27
35

10

II

40

4

35
30

7

55

4

I

NOTES: 22. ADI = any address Ime.
23. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or
through Port C (CSB-CS1 0).
24. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent
A19, RD/E/OS, WR or R/W, transparent PCO-PC2, ALE (or AS).
25. Control signals RD/E/DS or WR or R/\N.

-------------------------------------~~~~----------------------------------~
2-191

----------

PSD303

Figure 15.
Timing of 8-Bit
Multiplexed
AddreSS/Data
Bus, CRRWR =0

...

READ CYCLE

..

-~
32

:-----I

CS I/A19
as CSI

7

...

_321-

VX'X' rYXXX
15

I.

3<

Direct (26)
PAD In put

.:x:

STABLE INPUT
6

X

Multiplex ed(27)
Inputs

2

I DATA

-

\ OUT

3
4

XXXX xxxX
ADDRESS B

~

~

'---'
r-~

A

BHE/P-SEN
asP-SEN

\

Any of PAO-

PA7 Pins
as Ad dress
Outputs

'tv lXXXX X'I.'I.XX.
\

P IXXXXXXXXX
"\

I~

rL

~

-'

~

Lr

13

~

19

i--'

I-20

I--

INPUT

() )()()(XXXXXXXXXXXXX) :XX

OUTPUT

INPUT

) .XXXXXXXXXXXXXXXXXXX

OUTPUT

_~.

X.

~r

11

~

or
RiWasWR

Any of PBOPB7 as IIOPin

~

f--'

WRNpp

o Pin

\

X

DATA
IN

-

f--'

5

Any of PAO-

>-

3

~

.. -2......

RD/E/DSasRD

PA7 as II

14

14

.;..J; r-

81-

r~

Active Low'
ALE

~

STABLE INPUT

~

ADDRESS A

I

~~

- IXXX W.J..
32

IXXXXXX DO XXX
6

AOIADOA7IAD7
Active High
ALE

~

1-

...

WRITE CYCLE

~
ADDRESS A

ADDRESS B

See referenced notes on page 2-201.

---------------------------------rJrAr
..~--------------------------------2-192
ee"==

PSD303

Figure 16.
Timing of 8-Bit
Multiplexed
Address/Data
Bus, CRRWR =1
.-

READ CYCLE

-

~

CS I/A19
as CSI

WRITE CYCLE
32

7

..... 32 foo:

~

-xx:

"I.Y.' rxYW

15

32

I-

~

Direct(26) ]
PAD Inp ut

STABLE INPUT
6

Multiplexed (27) ...,.
Inpu ts

1J

AOIA DOA71AD7

Active High
AS

DATA
OUT

ADDRESS A

I

Active Low
AS

--

3

Irh

4

1If.r-

~

ADDRESS B

~

3

.2.
35

~

DATA
IN

~

---,

12

IXXX XXX

•

14

14

f4~

'--.J

I-

IXXXX XXXX)

8_

33

35

OC

R rL
I,

'--

f--'
33

34

~

'-----

V-

34

I

as E
5

,

RD/E/DS as DS
WR/vp p or
RiWas R/W

~~
f\.---I

f-J

~ IXXXXXXX

~
Any of PAOPA7 as 1/0 Pin

~.

32

STABLE INPUT

~

---,
2

.....

IXXXXXX ~ XX

6

•

---".

\

N. XXXXXXXXX

Any of PBO- ~
PB7 as 1/0 Pin

XXXXXXXXX

Any of PAO~
PA7 Pins ~
as Add ress - - - 1
Outputs

INPUT

INPUT

~

It-

v..xxxx
~

()lXXXWx XXxxxx"l"NY.

XX'

OUTPUT

IXXXXXXXXXXXXXXXXXXX'

OUTPUT

~
ADDRESS A

ADDRESSB

See referenced notes on page 2-201.

----------------------------------rJfAr~~--------------------------------F!!E!'f!!FEEE

2-193

PSD303

Figure 17.
Timing of 16-Bil
Multiplexed
Address/Dala
Bus! CRRWR = 0

...

READ CYCLE

.. ...

-~
32

~

CS I/A19
asCSI

I

7

WRITE CYCLE

15

32

Direct (26)
PAD In put

.:z: 00(

ISTABLE INPUT
6

Multiplex ed
Inputs

(27)

X

AOIADOA15/A D15

-

2

r ____

Active High
ALE
Active Low
ALE

,DATA
\ OUT

-

3

I

'

~

~

.. .2...

\

as RD
5

}-

ADDRESS B
3

f'oI~

~

DATA
IN

~

~

'---'

Ie-

IXXX :XXX

Any of PAOPAl as II Pin

Xl IXXXXXXXJV\,

Any of PBOPBl as II Pin

I

o
o

Any of PAOPAl Pins
as Ad dress
Outputs

X")

~

INPUT

INPUT

I

~

'- ~

~

~

~

~

X-

11

-

13

~
WRIV pp....£!:
RiWa sWR

~

,(XXX XXXX

~r-

8 Ie--

4

32

14

.<
ov

Figure 27.
AC Testing
Load Circuit

2.01 V
~

~ 1950
DEVICE
UNDER

TEST

........ C L = 30 pF

I

(INCLUDING
SCOPE AND JIG
":'" CAPACITANCE)

Erasure and
Programming

To clear all locations of their programmed
contents, expose the device to ultra-violet
light source. A dosage of 15 W second/cm2
is required. This dosage can be obtained
with exposure to a wavelength of 2537 A
and intensity of 12000 J.lW/cm 2 for 15 to 20
minutes. The device should be about 1
inch from the source, and all filters should
be removed from the UV light source prior
to erasure.
The PSD303 and similar devices will erase
with light sources having wavelengths
shorter than 4000 A. Although the erasure
times will be much longer than with UV
sources at 2537 A, exposure to fluorescent
light and sunlight eventually erases the

--------__________________________
2-202

device. For maximum system reliability,
these sources should be avoided. If used in
such an environment, the package
windows should be covered by an opaque
substance.
Upon delivery from WSI, or after each
erasure, the PSD303 device has all bits in
the PAD and EPROM in the "1" or high
state. The configuration bits are in the "0"
or low state. The code, configuration, and
PAD MAP data are loaded through the
procedure of programming
Information for programming the device is
available directly from WSI. Please contact
your local sales representative.

__________________________________

fl.~g

';;11'#11

PSD3D3

Pin
Assignments

Name
BHEIPSEN
WRN pp or RIW
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
GND
ALE or AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
RD/EIDS
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD10/A10
GND
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
PCO
PC1
PC2
A19/CSI

Vee

_______________________________

44-Pin
PLDCC/
CLDCC
Package

44-Pin
CPGA
Package

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

A5
A4
B4
A3
B3
A2
B2
B1
C2
C1
D2
D1
E1
E2
F1
F2
G1
G2
H2
G3
H3
G4
H4
H5
G5
He
Ge
H7
G7
Ga
F7
Fa
E7
Ea
Da
D7
Ca
C7
Ba
B7
A7
Be
Ae
B5

•

rl;_~,~--------------------------~~

~

2·203

PS0303

Package
Information

I~

II:

I

Z
o~ w

Figure 28.
DrawingL444 Pin Ceramic
Leaded Chip
Carrier (CLDCC)
with Window
(Package Type
L

It>

III
Q.

co

III
Q.

...
III

Q.

I-

W

I!: ~

> iii

~ I~

lili

I~

0'"

>0

...

c0

Q.

0
Q.

0

0

Q.

PB4

7

PB3

8 [

.....

38 AD/14/A14

PB2

9

.....

37 AD13/A13

.....

36 AD12/A12

.....

35 AD11/A11

.....

34 GND

PB1 10
PBO 11

39 AD15/A15

::::J
[ ::::J
[ ::::J
[ ::::J

o

GND 12 [ _-::_-J
ALE or AS 13 [
PA7 14

_-_-_-_-J

[_-_-:_-J

PA6 15 [_-_-_...J

::::J
[ ::::J

c::. ~ 33 AD10/A10

,.:::. p32 AD91A9

C::. p31
r:::. ~ 30

PA5 16 [
PA4 17

AD7/A7

,.:::. p29 AD61A6

'[.] [.] [.] ["] [.] [.] [.]
IX)
~

~

:2
Q.

Q.

:;;:

~ iii
Q.

(TOP VIEW)

~

... ...... ...'" ... ... ~ ...... ...
~
~ ~ '"
~ ~ Q
~ ~
c
c c c
c '"
~

~

II)

~

It>

c(

c(

IX)

0

Q.

I~

Figur829.
DrawingJ244-Pin Plastic
Leaded Chip
Carrier (PLDCC)
(Package Type

AD8/A8

c(

c(

c(

c(

I~
o~ IZ
w

113
o CD 0... 0 0
... Iii I!: ~ ~c
~ lil~
co
... '" ... ... '" ~ ... i
Li i..i Li Li t.i Lj Li Li Li Lj Li
It>

III
Q.

co

III

Q.

0

III

It>

J)

~

Q.

Q.

~

~

Q.

Q.

~

PB4

7

...

.....

39 AD15/A15

PB3

8

--_ ..

.....

39 AD14/A14

PB2

9

... ,

.•...

37 AD13/A13

.....

36 AD121A12

~

.:::J
PBO 11 [::::J
GND 12 [::::J
ALE or AS 13 [::::J
PA7 14 [ :.::J
PA6 15 ::::J
PA5 16 [ .:::J
PA4 17 [ .:::J
PB1 10 [

L:·:. ] 35
C::. ] 34
C::. ] 33
C::. ] 32
C::. ] 31
C::. p30
C::. p29

AD11/A11
GND
AD10/A10
AD91A9
AD8/A8
AD7/A7
AD61A6

(TOP VIEW)

___________________________________
2-204

'#I.'

rl=~~

___________________________________

PSD303

Figure 30:
DrawingX244-PinCPGA
(Package Type X)

2345678
A

B
C
D
E

F

G
H

000000
00000000
00
00
00
00
00
00
00
00
00000000
000000

(TOP VIEW, THROUGH PACKAGE)

Ordering
Information

Part Number

Spd.
(ns)

PSD303-12J
PSD303-12L
PSD303-12X
PSD303-15J
PSD303-15JI
PSD303-15L
PSD303-15L1
PSD303-15X
PSD303-15XI
PSD303-15XM
PSD303-15XMB
PSD303-20J
PSD303-20JI
PSD303-20L
PSD303-20Ll
PSD303-20X
PSD303-20XI
PSD303-20XM
PSD303-20XMB

120
120
120
150
150
150
150
150
150
150
150
200
200
200
200
200
200
200
200

Package
Type
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin
44-pin

PLDCC
CLDCC
CPGA
PLDCC
PLDCC
CLDCC
CLDCC
CPGA
CPGA
CPGA
CPGA
PLDCC
PLDCC
CLDCC
CLDCC
CPGA
CPGA
CPGA
CPGA

WSI
Package Operating
Temperature
Manufacturing
Drawing
Range
PrDcedure
J2
L4
X2
J2
J2
L4
L4
X2
X2
X2
X2
J2
J2
L4
L4
X2
X2
X2
X2

Commercial
Commercial
Commercial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Military
Military
Commercial
Industrail
Commercial
Industrial
Commercial
Industrial
Military
Military

Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
MIL-STO-883C
Standard
Standard
Standard
Standard
Standard
Standard
Standard
MIL-STD-883C

--------------------------------~Jf~----------------------------~-2-205

PSD303

~~~--

2-206

____________________________________

---rJrJf~··

";"';1=

____________________________________________---

PS0303
System
Development Tools

System
Development
Tools

The PSD303 features a complete set of
System Development Tools. These tools
provide an integrated, easy-to-use software
and hardware environment to support
PSD303 device development. To run these
tools requires an IBM-XT, -AT, or compatible computer, MS-DOS 3.1 or higher, 640K
byte RAM, and a hard disk.

Software
The PSD303 System Development
Software consists of:

Hardware

o WISPER, WSI's Software Environment
o MAPLE, the PSD303 Location Editor

The PSD303 System Programming
Hardware consists of:

o

o
o

o

WS6000 MagicPro Memory and PSD
Programmer
WS6021 44-pin LCC Package Adaptor
(for CLDCC and PLDCC packages)
WS6022 44-pin CPGA Package
Adaptor

The MagicPro Programmer is the common
hardware platform for programming all WSI

Support

programmable products. It consists of an
IBM-PC plug-in programmer board and a
remote socket adaptor.

WSI provides a complete set of quality
support services to registered System
Development Tools owners, including:

Software
MAPPRO, the Device Programming
Software

The configuration of the PSD303 device is
entered using MAPLE software. MAPPRO
software uses the MagicPro programmer
and the socket adaptor to configure the
PSD303 device, which then can be used in
the target system. The development cycle
is depicted in Figure 31.

o 24-hour Electronic Bulletin Board for
design assistance via dial-up
modem.

o 12-month software updates
o Design assistance from WSI field
application engineers and
application group experts

Training

WSI provides in-depth, hands-on workshops for the PSD303 device and System
Development Tools. Workshop participants
learn how to program high-performance,
programmable peripherals. Workshops are
held at the WSI facility in Fremont,
California.

2-207

~

II

PSD303

Ordering
Information System
Development
Tools

PSO-GOLO
D WISPER Software
D MAPLE Software
D User's Manual
D WSI Support
D WS6000 MagicPro™ Programmer
D One Package Adaptor and Two
PSD303 Product Samples

PSO-SILVER
D
D
D
D

WISPER Software
MAPLE software
User's Manual
WSI Support

WS6021
D 44-Pin LCC Package Adaptor for
CLDCC and PLDCC Packages.
Used with the WS6000 MagicPro
Programmer.

WS6022
D 44-Pin CPGA Package Adaptor.
Used with the WS6000 MagicPro
Programmer.

WSISupport

WS6000
D MagicPro Programmer
D IBM-PC© Plug-in Adaptor Card
D Remote Socket Adaptor

Figure 31.
PSD303
Development
Cycle

Support services include:
D 12-month Software Update Service
D Hotline to WSI Application Experts
D 24-hour access to WSI Electronic
Bulletin Board

WSI Training
D Workshops at WSI, Fremont, CA

IBM PLATFORM

Menu Selection

Configuration Data

Programming Data

MagicPro Hardware

~=---------------------fl;';-------------------------

2-208

~I&

Programmable Psripheral

iFEE':E

---E'=_=-F,_=-P'=
-~-

-

~

----~.-.-

Key Features

PSD313
Programmable Microcontroller Peripheral
with Memory
o Single Chip Programmable Peripheral
o 1 Mbit of UV EPROM
for Microcontroller-based Applications

-

Microcontroller I/O port expansion

-

Block resolution is 16K x 8

Programmable Address Decoder
(PAD) I/O

-

120 ns EPROM access time, including
input latches and PAD address
decoding.

-

Latched address output

-

Open drain or CMOS
Two Programmable Arrays
(PAD A & PAD B)

-

Total of 40 Product Terms and up to
16 Inputs and 24 Outputs

-

Direct Address Decoding up to 1 Meg
address space and up to 16 Meg
with paging

-

Logic replacement

o

"No Glue" Microcontroller Chip-Set

o

16 Kbit Static RAM

-

Organized as 2K x 8

-

120 ns SRAM access time, including
input latches and PAD address
decoding

o
-

o

Address/Data Track Mode
Enables easy Interface to Shared
Resources (Mail Box SRAM) with other
Microcontrollers or a Host Processor
Built-In Security
Locks the PSD313 Configuration and
PAD Decoding

-

Built-in address latches for multiplexed
address/data bus

-

Non-multiplexed address/data bus
mode

o

Available in a Variety of Packaging

-

8 bit data bus width

-

44 Pin PLDCC and CLDCC

-

ALE and Reset polarity programmable

-

44 Pin CPGA

-

Selectable modes for read and write
control bus as RDIWR, RIW/E, or
R!W/DS

o

-

PSEN/ pin for 8051 users

o

o

Microcontrollers
Supported

Divides into 8 equal mappable blocks
for optimized mapping

19 Individually Configurable I/O pins
that can be used as

o

of

Organized as 128K x 8

-

o
-

Partial Listing

-

Built-In Page Logic

-

To Expand the Address Space of
Microcontrollers with Limited Address
Space Capabilities

-

Up to 16 pages

o

Motorola family:
M6805, M68HC11 , M68HC16,
M68000/10/20, M60008, M683XX

o Intel family:

Simple Menu-Driven Software:
Configure the PSD313 on an IBM PC
Downward Pin and Functionally
Compatible with the PSD311
and PSD313

o Signetics:
o Zilog:
o National:

SC80C451
Z8, Z80, Z180
HPC16000

8031/8051,8096/98,80186/88,
80196/98

2-209

•

PS0313

Applications

o
o

Introduction

Product
Description

Computers (Workstations and PCs)
Fixed Disk Control, Modem, Imaging,
Laser Printer Control

o

Telecommunications
Modem,Celiular Phone, Digital PBX,
Digital Speech, FAX,
Digital Signal Processing

o

Medical Instrumentation
Hearing Aids, Monitoring Equipment,
Diagnostic Tools

o

Military
Missile Guidance, Radar, Sonar,
Secure Communications, RF Modems

Industrial
Robotics, Power Line Access,
Power Line Motor

The PSD313 is the latest member in the
rapidly growing WSI family of PSD devices.
The PSD313 is ideal for microcontrollerbased applications, where fast time-tomarket, small form factor, and low power
consumption are essential. When
combined in a system, virtually any microcontroller (68HC11, 8051 etc.) and the
PSD313 work together to create a very
powerful chip-set solution. This implementation provides all the required control and
peripheral elements of a microcontroller-

based system peripheral with no external
discrete "glue" logic required.

The PSD313 integrates high performance
user-configurable blocks of EPROM,
SRAM, and programmable logic technology
to provide a single chip microcontroller
interface. The major functional blocks
include two programmable logic arrays,
PAD A and PAD B, 1 Mbit of EPROM, 16K
bits of SRAM, input latches, and output
ports. The PSD313 is ideal for
applications requiring high performance,
low power, and very small form factors.
These include fixed disk control, modem,
cellular telephone, instrumentation,
computer peripherals, military and similar
applications.

o

The PSD313 offers a unique single-chip
solution for microcontrollers that need:

o
o
o

I/O reconstruction (microcontrollers
lose at least two I/O ports when
accessing external resources).
More EPROM and SRAM than the
microcontroller's internal memory.
Chip-select, control, or latched address
lines that are otherwise implemented
discretely.

The solution comes complete with simple
system software development tools for
integrating the PSD313 with the microcontroller. Hosted on the IBM PC platforms or
compatibles, the easy to use software
enables the designer complete freedom in
designing the system.

o

An interface to shared external
resources.
Expanding address space of
microcontrollers

WSI's PSD313 (shown in Figure 1) can
efficiently interface with, and enhance, any
microcontroller system. This is the first
solution that provides microcontrollers with
port expansion, latched addresses, page
logic, two programmable logic arrays PAD
A and PAD B, an interface to shared
resources, 1 Mbit EPROM, and 16K bit
SRAM on a single chip. The PSD313 does
not require any glue logic for interfacing to
any 8-bit microcontroller.
The 8051 microcontroller family can take
full advantage of the PSD313's separate
program and data address spaces. Users
of the 68HCXX family of microcontrollers
can change the functionality of the control
signals and directly connect the RiW
and E, or the RiW and OS signals. Address
and data buses can be configured to be
separate or multiplexed, whichever is
required by the host processor.

-------------------------------------fjfJr~:------------------------------------~~=

2-210

P50313

Product
Oiscription
(Cont.)

to map the I/O ports, eight segments of
EPROM (16K x 8 each) and SRAM (2K x
8) anywhere in the address space of the
microcontroller. PAD B can implement up to
4 sum-of-product expressions based on
address inputs and control signals.

The flexibility of the PSD313 I/O ports
permits interfacing to shared resources.
The arbitration can be controlled internally
by PAD A outputs. The user can assign the
following functions to these ports: standard
I/O pins, chip-select outputs from the PAD
A and PAD B, or latched address or mUltiplexed low-order address/data byte. This
enables users to design add-on systems
such as disk drives, modems, etc., that
easily interface to the host bus (e.g., IBM
PC, SCSI).

The page register extends the accessible
address space of certain microcontrollers
from 64K to 1 M. There are 16 pages
that can serve as base address inputs to
the PAD, thereby enlarging the address
space of 16 address line processors by a
factor of 16.

The PSD313 on-chip programmable
address decoder (PAD A) enables the user

Figure 1.
PS0313
Architecture

PAGE LOGIC
P3-PO

L
A
T
C
H

AB-A15

~
A19
CSI
ALE/AS

*

~

PADA

~
RD

!LOGICIN

PAD B

--

WR
RESET

WR
RESET

13 P.T.

- --

f--

'--

II

CSIOPORT
A19
CSI

RD

,.-

-

'----

27 P.T.

-~
~

CSBCS10_

-r

CsoCS7

SRAM
16K BIT

AC!--A7
ADO-AD7IDO-D7

--

~

_Br-

PROG.
PORT
EXP.

f---PORT
A

r-:~------l
PROG. CHIP
CONFIGURATION

t

PBC!-PORT

,---'--

~

TRACK MODE
SELECTS

RO/E/OS

-

PROG.
PORT
EXP.

CSIOPORT

1-

ALE/AS

~

-

-.l_--

'----

PcoPORT
C

EPROM
1MBIT

12BK BIT
BLOCK

.--

-

-

PROG.
PORT
EXP.

-ES7
ES6
ES5
ES4
ES3
ES2
ES1
--t
§.o-+i

L
A
T
C
H

A DO-AD7

A16 A1B

~r=

. - - A11-A15

PAC!--

~

I...--

-

WR/R/W
PSEN
RESET

PROG.
CONTROL
SIGNALS

XB.
MUX or NON-MUX SUSSES
SECURITY MODE

A19/CSI

---------------------------------------~~~--------------------------------------

2-211

•

PS0313

Table 1.
PSD313 Pin
Descriptions

Name

Description

Type

The PSEN is the active low EPROM read pulse. The SRAM and 1/0
read sig~1 is generated according to the description of the
WRIVpp or R/W, and RO/E/OS pins. If the host processor is a
member of the 8031 family, PSEN must be connected to the
corresponding host pin. In other 8-bit host processors that do not
have a special EPROM-only read strobe, PSEN should be tied to
Vee. In this case, RO or E and RiW provide the read strobe for the
SRAM, 1/0 ports, and EPROM.

~s

In the operating mode, this pin's function is WR (CRRWR = 0) or
RiW (CRRWR = 1) when configured as R/W. The following tables
summarize the read and write operations (CRRWR = 1):
CEOS = 0
WRIVpp
or
R/W

R/W

E

o

0
1
1

x
1

CEOS = 1
OS
X 1 NOP
0
0
write
1
0
read

R/W
NOP
write
read

When configured as WR, a write operation is executed during an
active low pulse. When configured as R/W, with R/W = 1 and E = 1,
a read operation is executed; if R/W = 0 and E = 1, a write
operation is executed. In programming mode, this pin must be tied
to Vpp voltage.

RO/E/OS

CSI/A19

RESET

Legend:
NOTE:

The pin function depends on the CRRWR and CEOS configuration
bits. If CRRWR = 0, RO is an active low read pulse. When
CRRWR = 1, this pin and the Riw pin define the following cycle type:
If CEOS = 0, E is an active high strobe. If CEOS = 1, OS is an active
low strobe.
This pin has two configurations. When it is CSI (CA 19/CSI = 0) and
the pin is asserted high, the device is deselected and powered down.
(See Tables 10 and 11 for the chip state during power-down mode.)
If the pin is asserted low, the chip is in normal operational mode.
When it is configured as A 19, (CA 19/CSI = 1), this pin can be used
as an additional input to the PAO. CAOLOG3 = 1 defines the pin as
an address; CAOLOG3 = 0 defines it as a logic input. If it is an
address, A 19 can be latched with ALE (CAOOHLT = 1) or be a
transparent logic input (CAOOHLT = 0). In this mode, there is no
power-down capability.
This user-programmable pin can be configured to reset on high
level (CRESET = 1) or on low level (CRESET = 0). It should remain
active for at least 100 ns. See Tables 8 and 9 for the chip state after
reset.

The 1/0 column abbreviations are: I = input; 1/0

= input/output; P = power.

1. All the configuration bits mentioned in Table 1 appear in parentheses and are explained in
the Configuration Register section.

-------------------------------------~~~------------------------------------2-212

P50313

Table 1.
PSD313 Pin
Descriptions
(Cont.)

Name
ALE
or
AS

PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAD

PB7
PB6
PB5
PB4
PB3
PB2
PBO

PCO
PC1
PC2

Description

Type

I

I/O

I/O

I/O

In the multiplexed modes, the ALE pin functions as an Address
Latch Enable or as an Address strobe and can be configured as an
active high or active low signal. The ALE or AS trailing edge
latches lines AD15/A15-ADO/AO, A16-A19, and BHE, depending
on the PSD313 configuration. See Table 7. In the non-multiplexed
modes, it can be used as a general-purpose logic input to
the PAD.
PA7-PAO is an 8-bit port that can be configured to track
AD7/A7-ADO/AO from the input (CPAF2 = 1). Otherwise
(CPAF2 = 0), each bit can be configured separately as an I/O or
lower-order latched address line. When configured as an I/O
(CPAF1 = 0), the direction of the pin is defined by its direction bit,
which resides in the direction register. If a pin is an I/O output, its
data bit (which resides in the data register) comes out. When it is
configured as a low-order address line (CPAF1 =1), A7-AO can be
made the corresponding output through this port (e.g., PA6 can be
configured to be the A6 address line). Each port bit can be a
CMOS output (CPACOD = 0) or an open drain output (CPACOD =
1). When the chip is in non-multiplexed mode (CADDRAT = 0), the
port becomes the data bus lines (00-07). See Figure 4.
PB7-PBO is an 8-bit port for which each bit can be configured as
an I/O (CPBF = 1) or chip-select output (CPBF = 0). Each port bit
can be a CMOS output (CPBCOD = 0) or an open drain output
(CPBCOD = 1). When configured as an I/O, the direction of the
pin is defined by its direction bit, which resides in the direction
register. If a pin is an I/O output, its data (which resides in the data
~st~omes out. When configured as a chip-select output,
CSO-CS3 are a function of up to four product terms of the inputs to
the PAD B; CS4,-CS7 then are each a function of up to two
product terms. See Figure 6.
This is a 3-bit port for which each bit is configurable as a PAD A
and B input or output. When configured as an input (CPCF = 0), a
bit individually becomes an address (CADLOG = 1) or a logic input
(CADLOG = 0). The addresses can be latched with ALE
(CADDHLT = 1) or be transparent inputs to the PADs
(CADDHLT = 0). When a pin is configured as an output
(CPCF = 1), it is a function of one product term of all PAD inputs.
See Figure 7.

=

!i'EEE§
-------------,-------1411=
aI----------------SFeiEE

2-213

•

PS0313

Table 1.
PSD313 Pin
Descriptions
(Cont.)

Name
ADO/AO
AD1/Al
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
A8
A9
Al0
All
A12
A13
A14
A15

Operating
Modes

Description

Type

I/O

In multiplexed mode, these pins are the multiplexed low-order
address/data byte. After ALE latches the addresses, these pins
input or outp~data, depending on the settings of the RD/E/DS,
WRIV pp or R/W, and PSEN pins. In non-multiplexed mode, these
pins are the low-order address input.

I/O

These pins are the high-order address input.

GND

P

Vss (ground) pin.

Vcc

P

Supply voltage input.

The PSD313's two operating modes allow
it to interface directly to 8-bit microcontrollers with multiplexed and nonmultiplexed address/data buses. These
operating modes are described below.

Multiplexed B-bit Address/Data Bus
This mode is used to interface to microcontrollers with an 8-bit data bus and a 16-bit
or larger address bus. The low-order
address/data bus (ADO/AO-AD7/A7) is
bidirectional and permits the latching of the
address when the ALE signal is active. On
the same pins, the data is read from or
written to the device; this depends on the
state of the RD/E/DS, PSEN and WRIVpp
or R/W pins. The high-order address bus
(A8-A 15) contains the high-order address
bus byte. Ports A and B can be configured
as in Table 2.

_____________________________________

2-214

Non-Multiplexed
Address/Data, B-bit Data Bus
This mode is used to interface to a
microcontroller with an 8-bit non-multiplexed bus and a 16-bit or larger address
bus. The low-order address/data bus
(ADO/AO-AD7/A7) is the low-order address
input bus. The high-order address/data bus
(A8-A 15) is the high-order address bus
byte. Port A is the low-order data bus. Port
B can be configured as shown in Table 2.
Table 2 summarizes the effect of the
different operating modes on ports A, B,
and the address/data pins. The configuration of Port C is independent of the four
operating modes.

_____________________________________

F§§~§

~;§;

P50313

Programmable
Address
Decoder (PAD)

The PSD313 consists of two programmable
arrays referred to as PAD A and PAD B
(Figure 3). PAD A is used to generate chip
select signals derived from the input
address to the internal EPROM blocks,
SRAM, 1/0 ports, and Track Mode signals.
All its 1/0 functions are listed in Table 3 and
shown in Figure 3. PAD B outputs to Ports
Band C for off-chip usage.
PAD B can also be used to extend the
decoding to select external devices or as a
random logic replacement. The input bus to

Figure 2.
PSD313 Port
Configurations

both PAD A and PAD B is the same. Using
WSI's MAPLE software, each
programmable bit in the PAD's array can
have one of three logic states of 0, 1, and
don't care (X). In a user's logic design,
both PADs can share the same inputs
using the X for input signals that are not
supposed to affect other functions. The
PADs use
reprogrammable CMOS EPROM
technology and can be programmed and
erased by the user.

Figure 2 shows the PSDS313's 1/0 port configurations.
AD 8-AD15

1/0 or AO-A? or

A8 -A15
DO-D?

ADO-AD?
AD O-AD?

AO -A?

PA

AL E

AL E

r--

PS EN

PA

1/0 or CSO-CS?

r--

EN

1/0 or GSO-GS?

PB

PB

RI WorWRNpp

or WRNpp

RDIE/Os
A1 9lCSI

'--

.

IE/Os
A16-A180rCS8-C

PC

RE SET

Table 2.
PSD313 Bus
and Port
Configuration
Options

A16-A18 or GS8-C
PC

RE SET

1. PSD313 configured for multiplexed
16-bit addressldata bus.

Legend:

A1 giGS I

~

2. PSD313 configured for nonmultiplexed addressldata, 8-bit bus.

ADO-AD7 = Addresses AO-A7 multiplexed with data lines DO-D7.

Multiplexed Address/Data

Non-Multiplexed Address/Data

B-bit Data Bus
1/0 or low-order address
lines or Low-order multiplexed
addressldata byte

DO-D7 data bus byte

Port B

1/0 or CSO-CS7

1/0 andlor CSO-CS7

ADO/AO-AD7/A7

Low-order multiplexed
addressldata byte

Low-order address bus byte

A8-A15

High-order address bus byte

High-order address bus byte

Port A

-------------------------------------~~~-----------------------------------2-215

•

P50313

Figure 3.
PSD313 PAD
Description

I

~

!

I
ESO

~~~
P,

r-

Po

r-

ESl
ES2
ES3
ES4

8 EPROM BLOCK
S ELECT LINES

::>r-

AL EorAS

....

::>
ES7
RSO-S RAM BLOCK SELECT

DorE

v

">

orRiW

ilill

"".>
A19

v

PAD
A

ES5
ES6

CSIOPORT ~ I/O BASE ADDRESS
CSADIN

I

I

CSADOUTl
CSADOUT2

}

TRACK MODE
CONTROL SIGNALS

">
CSO/PBO

A18

v

-

">

CS1/PBl

A17

~

-~\..-">
CS21PB2

A16

I

""S

v

~

CS3/PB3

A15

-V

">

I

A14

-

v

A13

I

">

CS4/PB4

PAD

I
CS51PB5

"".>

B

I

!

CS6/PB6
A12

I

">

CS7/PB7

All

"".>

I
IIII

S"'____.
-.----.
RESET

I

I II II

I

I I

I I i I II II I
I

I

I

I

Ii

-{>o----

CSB/PCO

~~{>o__-

CS9/PCl
CS10lPC2

I

NOTES: 2. CSI is a power-down signal. When high, the PAD is in stand-by mode and all its outputs
become non-active. See Tables 10 and 11.
3. RESET deselects all PAD output signals. See Tables 8 and 9.
4. A18, A17, and A16 are internally multiplexed with CS10, CS9, and CS8, respectively.
Either A18 or CS10, A17 or CS9, and A16 or CS8 can be routed to the external pins of
Port C. Port C can be configured as either input or output.

---------------------------------------r~~~~------------------------------------------E!!WI~E
2-216

PSD313

Table 3.
PSD313 PAD A
and B I/O
Functions

Function
PAD A and PAD BInputs
CSI or A19

In CSI mode (when high), PAD deselects all of its outputs and enters a
power-down mode (see Tables 10 and 11). In A19 mode, it is another
input to the PAD.

A16-A18

These are general purpose inj:luts from Port C. See Figure 3, Note 4.

A11-A15

These are address inputs.

PO-P3

These are page number inputs.

RDorE

This is the read pulse or enable strobe input.

WRor RIW
ALE
RESET

This is the write pulse or R/W select signal.
This is the ALE input to the chip.
This deselects all outputs from the PAD; it can not be used in product
term equations. See Tables 8 and 9.

PAD A Outputs
ESO-ES7

These are internal chip-selects to the 8 EPROM banks. Each bank can be
located on any boundary that is a function of one product term of the PAD
address inputs.

RSO

This is an internal chip-select to the SRAM. Its base address location is a
function of one term of the PAD address inputs.

CSIOPORT

This internal chip-select selects the I/O ports. It can be placed on any
boundary that is a function of one product term of the PAD inputs. See
Table 6.

CSADIN

This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the input
direction of Port A. CSADIN is gated externally to the PAD by the internal
read signal. When CSADIN and a read operation are active, data
presented on Port A flows out of ADO/AO-AD7/A7. This chip-select can be
placed on any boundary that is a function of one product term of the PAD
inputs. See Figure 5.

CSADOUT1

This internal chip-select, when Port A is configured as a low-order
address/data bus in track mode (CPAF2 = 1), controls the output direction
of Port A. CSADOUT1 is gated externally to the PAD by the ALE signal.
When CSADOUT1 and the ALE signal are active, the address presented
on ADO/AO-AD7/A7 flows out of Port A. This chip-select can be placed on
any boundary that is a function of one product term of the PAD inputs.
See Figure 5.

CSADOUT2

This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT2 must include the write-cycle control
signals as part of its product term. When CSADOUT2 is active, the data
presented on ADO/AO-AD7/A7 flows out of Port A. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure 5.

PAD B Outputs
CSO-CS3

These chip-select outputs can be routed through Port B. Each of them is
a function of up to four product terms of the PAD inputs.

CS4-CS7

These chip-select outputs can be routed through Port B. Each of them is
a function of up to two product terms of the PAD inputs.

CS8-CS10

These chip-select outputs can be routed through Port C. See Figure 3,
Note 4. Each of them is a function of one product term of the PAD inputs.

;EEliE

-----------------------------------~aJ;-----------------------------------

2-217

•

PSD313

Configuration
Bits

Table 4.
PS0313
Non- Volatile
Configuration
Bits

The configuration bits shown in Table 4 are
non-volatile cells that let the user set the
device, I/O, and control functions to the
proper operational mode. Table 5 lists all
configuration bits. The configuration bits
are programmed and verified during the

Use This Bit
CADDRDAT
CEDS
CA19/CSI

To
Set the address/data bus to multiplexed or non-multiplexed mode.
Determine the polarity and functionality of read and write.
Set A 19/CSI to CSI (power-down) or A 19 input.

CALE

Set the ALE polarity.

CPAF2

Set Port A either to track the low-order byte of the address/data
multiplexed bus or to select the I/O or address option.

CSECURITY
CRESET

Set the security on or off (a secured part can not be duplicated).
Set the RESET polarity.

COMB/SEP

Set PSEN and RD for combined or separate address spaces
(see Figures 8 and 9).

CPAF1
(8 Bits)

Configure each pin of Port A in multiplexed mode to be an I/O or
address output.

CPACOD
(8 Bits)

Configure each pin of Port A as an open drain or active CMOS
pull-up output.

CPBF
(8 Bits)

Configure each pin of Port B as an I/O or a chip-select output.

CPBCOD
(8 Bits)

Configure each pin of Port B as an open drain or active CMOS
pull-up output.

CPCF
(3 Bits)

Configure each pin of Port C as an address input or a chip-select output.

CADDHLT

Configure pins A 16-A 19 to go through a latch or to have their
latch transparent.

CADLOG
(4 Bits)

Configure A 16-A 19 individually as logic or address inputs.

CLOT
CRRWR

Port Functions

programming phase. In operational mode,
they are not accessible. To simplify implementing a specific mode, use the WSl's
PSD313 MAPLE software to set the bits.

Determine in non-multiplexed mode if address inputs are transparent
or latched.
Configure the polarity and control methods of read and write cycles.

The PSD313 has three I/O ports (Ports A,
B, and C) that are configurable at the bit
level. This permits great flexibility and a
high degree of customization for specific

applications. The following is a description
of each port. Figure 4 shows the pin
structure of Port A.

-----------------------------------~~~-----------------------------------

2-218

PS0313

Figure 4.
Port A Pin
Structure

I
N
T
E
R
N
A
L

READ PIN

READ DATA
CMOS/OD(5)
WRITE DATA

A

CK

--J

OUT
OFF

0
0

DR

R
I

PORTA PIN

ENABLE

ALE

0

ADDR _..

G

A
T
A

MUX

LATCH

0

•

R
ADI/DI

B
U
S

READDIR

A
D

0

D

I
A
D
7

DIR
WRITEDIR

CONTROL

CK FF
R

I

I

RESET

NOTE: 5. CMOS/aD determines whether the output is open drain or CMOS.

Figure 5.
Port A Track
Mode
WRorR/W

-I
CSADIN

ROlE
ADO-AD7

INTERNAL
ALE

ALE or AS

..

AD8-AD15

•

LATCH A11-A15

I--.o.j

PAD
CSADOUT2 (6)

A16-A19

NOTE: 6. The expression for CSADOUT2 must include the following write operation cycle signals:
For CRRWR = 0, CSADOUT2 must include WR = 0.
For CRRWR = 1, CSADOUT2 must include E = 1 and R/W = O.

if'====g

---------------------------------------~~;--------------------------------------

2-219

PSD313

Table 5.
PS0313
Configuration
Bils 7,8

Configuration
Bits

of Bits

CADDRDAT

1

ADDRESS/DATA Multiplexed (separate buses)
CADDRDAT = 0, non-multiplexed
CADDRDAT = 1, multiplexed

CA19/CSI

1

A19 or CSI
CA19/CSI = 0, enable power-down
CA 19/CSI = 1, enable A 19 input to PAD

CALE

1

Active HIGH or Active LOW
CALE = 0, Active high
CALE = 1, Active low

CRESET

1

Active HIGH or Active LOW
CRESET = 0, Active low RESET
CRESET = 1, Active high RESET

COMB/SEP

1

Combined or Separate Address Space
for SRAM and EPROM
o = Combined, 1 = Separate

CPAF2

1

Port A ADO-AD? (address/data multiplexed bus)
CPAF2 = 0, address or I/O on Port A
(according to CPAF1)
CPAF2 = 1, address/data multiplexed on Port A
(track mode)

CADDHLT

1

A 16-A 19 Transparent or Latched
CADDHLT = 0, Address latch transparent
CADDHLT = 1 , Address latched (ALE dependent)

CSECURITY

1

SECURITY On/Off
CSECURITY = 0, off
CSECURITY = 1, on

CLOT

1

AO-A 15 Address Inputs are transparent or
ALE-dependent in non-multiplexed modes
CLOT = 0, transparent
CLOT = 1 , ALE-dependent

CRRWR
CEDS

2

Determine the polarity and control methods of
read and write cycles.
CEDS CRRWR
RD and WR active low pulses
0
0
R/W status and high E pulse
1
0
1
1
R/W status and low OS pulse

CPAF1

8

Port A I/O or AO-A?
CPAF1 = 0, Port A pin is I/O
CPAF1 = 1, Port A pin is Ai (0 $ i $ ?)

CPACOD

8

Port A CMOS or Open Drain Output
CPACOD = 0, CMOS output
CPACOD = 1, open-drain output

CPBF

8

Port B is I/O or CSO- CS?
CPBF = 0, Port B pin is CSI (0 $ i $ ?)
CPBF = 1, Port B pin is I/O

No.

Function

___________________________________ FEEaFE ___________________________________

2-220

il:lsll

PS0313

Table 5.
PS0313
Configuration
Bits (Cont.)

Configuration
Bits

No.
of Bits

CPBCOD

8

Port B CMOS or Open Drain
CPBCOD = 0, CMOS output
CPBCOD - 1, open-drain output

CPCF

3

Port C A16-A18 or CS8-CS10
CPCF = 0, Port C pin is Ai (16 ~ i ~ 18)
CPCF = 1, Port C pin is CSI (8 < i < 1O)

CADLOG

4

A 16-A 19 Address or Logic Input
CADLOG = 0, Port C pin or A 19/CSI is
logic input
CADLOG = 1, Port C pin or A 19/CSI
is Ai (16 ~ i ~ 19)

Total Bits

50

Function

NOTES: 7. WSl's MAPLE software will guide the user to the proper configuration choice.
8. In an unprogrammed or erased part, all configuration bits are O.

Port Functions
(Cont.)

Port A in Multiplexed
Address/Data Mode
The default configuration of Port A is 1/0. In
this mode, every pin can be set as an input
or output by writing into the respective pin's
direction flip flop (DIR FF, in Figure 4). As
an output, the pin level can be controlled by
writing into the respective pin's data flip flop
(DFF, in Figure 4). When DIR FF = 1, the
pin is configured as an output. When DIR
FF = 0, the pin is configured as an input.
The controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the OFF bits by accessing the READ
DATA register. Port A pin levels can be
read by accessing the READ PIN register.
Individual pins can be configured as CMOS
or open drain outputs. Open drain pins
require external pull-up resistors. For
addressing information, refer to Table 6.
Alternatively, each bit of Port A can be
configured as a low-order latched address
bus bit. The address is provided by the port
address latch, which latches the address
on the trailing edge of ALE. PAO-PA7 can
become AO-A7, respectively. This feature
of the PSD313 lets the user generate loworder address bits to access external
peripherals or memory that require several
low-order address lines.

Another mode of Port A (CPAF2 = 1) sets
the entire port to track the inputs
ADO/AO-AD7/A7, depending on specific
address ranges defined by the PAD's
CSADIN, CSADOUT1, and CSADOUT2
signals. This feature lets the user interface
the microcontroller to shared external
resources without requiring external buffers
and decoders. In this mode, the port is
effectively a bi-directional buffer. The
direction is controlled by using the input
signals ALE, RD/E/DS, WR/vpp or RiW,
and the internal PAD outputs CSADOUT1 ,
CSADOUT2 and CSADIN (see Figure 5).
When CSADOUT1 and ALE are true, the
address on the input ADO/A7-AD7/A7 pins
flows out through Port A. (Carefully check
the generation of CSADOUT1, and ensure
that it is stable during the ALE pulse; see
Figure 18). When CSADOUT2 is active, a
write operation is performed (see note to
Figure 5). The data on the input
ADO/A7-AD7/A7 pins flows out through
Port A. When CSADIN and a read operation is performed (depending on the mode
of the RD/E/DS and WR/vpp or R/W pins),
the data on Port A flows out through the
ADO/A7-AD7/A7 pins. In this operational
mode, Port A is tri-stated when none of the
above-mentioned three conditions exist

-------------------------------------~~~-----------------------------------2-221

•

P50313

Port Functions
(Cont.)

Port A in Non-Multiplexed
Address/Data Mode
In this mode, Port A becomes the low order
data bus byte of the chip. When reading an
internal PSD313 location, data is presented
on Port A pins. When writing to an internal
PSD313 location, data present on Port A
pins is written to that location.

PortS
The default configuration of Port B is I/O. In
this mode, every pin can be set as an input
or output by writing into the respective pin's
direction flip flop (DIR FF, in Figure 6). As
an output, the pin level can be controlled by
writing into the respective pin's data flip flop
(OFF, in Figure 6). When DIR FF = 1, the
pin is configured as an output. When DIR
FF = 0, the pin is configured as an input.
The controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the OFF bits by accessing the READ
DATA register. Port B pin levels can be
read by accessing the READ PIN register.
Individual pins can be configured as CMOS
or open drain outputs. Open drain pins
require external pull-up resistors. For
addressing information, refer to Table 6
Alternatively, each bit of Port B can be
configured to provide a chip-select output
~al from PAD B. PBO-PB7 can provide
CSO-CS7, respectively. Each of the Signals
CSO-CS3 is comprised of four product
terms. Thus, up to four ANDed expressions
can be ORed while deriving any of these
signals. Each of the signals CS4-CS7 is
comprised of two product terms. Thus, up
to two ANDed expressions can be ORed
while deriving any of these signals.

Accessing the I/O Port Registers
Table 6 shows the offset values with the
respect to the base address defined by the
CSIOPORT. They let the user access the
corresponding registers.

Port C in All Modes
Each pin of Port C (shown in Figure 7) can
be configured as an input to PAD A and
PAD B or output from PAD B. As inputs,
the pins are named A 16-A 1S. Although the
pins are given names of the high-order
address bus, they can be used for any
other address lines or logic inputs to PAD A
and PAD B. For example, AS-A 10 can also
be connected to those pins, improving the
boundaries of CSO-CS7 resolution to 256
bytes. As inputs, they can be individually
configured to be logic or address inputs. A
logic input uses the PAD only for Boolean
equations that are implemented in any or
all of the CSO-CS1 0 PAD B outputs. Port C
addresses can be programmed to latch the
inputs by the trailing edge ALE or to be
transparent.
Alternatively, PCO-PC2 can become
CSS-CS10 outputs, respectively, providing
the user with more external chip-select
PAD outputs. Each of the signals
CSS-CS10 is comprised of one product
term.

ALE/AS and ADo/AD-AD1/Al in
Non-Multiplexed Modes
In non-multiplexed modes, ADO/AOAD15/A15 are address inputs only and can
become transparent (CLOT = 0) or ALE
dependent (CLOT = 1). In transparent
mode, the ALE/AS pin can be used as an
additional logic input to the PADs. The
non-multiplexed ALE dependent mode is
useful in applications for which the host
processor has a multiplex address/data bus
and ADO/AO-AD7/A7 are not multiplexed
with AO-A7 but rather are multiplexed with
other address lines. In these applications,
Port A serves as a data bus and each
of its pins can be directly connected to the
corresponding host's multiplexed pin,
where that data bit is expected. See
Table 7.

-------------------------------------~~;'-------------------------------------

2-222

P5D313

Figure 6.
PortS Pin
Structure

Figure 6 shows the structure of Port B.
READ PIN

N
T
E

R
N

A
L

I
N
T

READ DATA

E
R
N
A
L

CMOS/OD(9)
WRITE DATA CK

~

OUT

OFF

C
S

o
U

0

0

R

A
T
A

01

PORTB PIN

ENABLE

MUX

T

B
U

B
U
S
CSI

S
C
S

0
8

j

READDIR

o
D

D

7

1
5

WRITEDIR

OIR
CK FF

CONTROL

R

I

RESET

NOTE: 9. CMOS/aD determines whether the output is open drain or CMOS.

Table 6.
I/O Port
Addresses in an
8-bit Data Sus
Mode

Register Name

Byte Size Access of the I/O Port Registers
Offset from the CSIOPORT

Pin Register of Port A

+ 2 (accessible during read operation only)

Direction Register of Port A

+4

Data Register of Port A

+6

Pin Register of Port B

+ 3 (accessible during read operation only)

Direction Register of Port B

+5

Data Register of Port B

+7

-----------------------------------~~~~----------------------------------2-223

•

PS0313

Figure 7.
Port C Structure

ADDRESS INDICATOR

(NOTE 10)

PCO

A16
I---~" TO PAD

I

CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL

FROM PAD

ALE

A17

I----.TO PAD
FROM PAD

A18

PC2

!---.TOPAD

I

r--L~~~~~~~-------FROMPAD

TO
EPROM

NOTE:

Table 7.
Signal Latch
Status in All
Operating
Modes

10. The CADDHLT configuration bit determines if A18-A16 are transparent via the latch, or if
they must be latched by the trailing edge of the ALE strobe.

Signal
Name
ADO/AOAD7/A7

Configuration
Bits

= 0, CLOT =

CADDRDAT

= 0, CLOT = 1

CADDRDAT = 1
PSEN

CDATA

=

°
°

CADDHLT

=

CADDHLT

=1

A19 and
PC2-PCO

____________________________

2-224

°

CADDRDAT

FEISF~

~ss

Configuration
Mode
non-multiplexed
modes

Signal Latch
Status
Transparent
ALE
Dependent

multiplexed modes

ALE
Dependent

8-bit data,
PSEN is active

Transparent

A16-A19 can
Transparent
become logic inputs
A16-A19 can
become
multiplexed
address lines

ALE
Dependent

______________________________

PSD313

EPROM

The PS0313 has 1M bit of EPROM
and is organized as 128K x 8. The EPROM
has 8 banks of memory. Each bank can
be placed in any address location by
programming the PAO. BankO-Bank? can

SRAM

The PS0313 has 16K bits of SRAM and is
organized as 2K x 8. The SRAM is selected
by the RSO output of the PAO.

Page Register

The page register consists of four flip-flops,
which can be read from, or written to,
through the 1/0 address space
(CSIOPORT). The page register is
connected to the 03-00 lines. The Page
Register address is CSIOPORT + 18H.
The page register outputs are P3-PO,

Control Signals

Th~PS0313

control signals are WRlVpp or
RIW, RO/E/OS, ALE, PSEN, Reset, and
A 19/CSI. Each of these signals can be
configured to meet the output control signal
requirements of various microcontrollers.

WRIV,.,. or R/W
In operational mode, this signal can be
configured as WR or R/W. As WR, all write
operations to the PS0313 are activated by
an active low signal on this pin. As RiW, the
works with the E strobe of the
RO/E/OS pin. When R/W is high, an active
high signal on the RO/E/OS pin performs a
read operation. When R/W is low, an active
high signal on the RO/E/OS pin performs a
write operation.

e!!!

RD/E/DS
In operational mode, this signal can be
configured as RO, E, or OS. As RO, all read
operations to the PS0313 are activated by
an active low signal on this pin. As E, the
~ works wit~e RIW signal-2! the
WR/Vpp or RIW pin. When R/W is high, an
active high signal on the ROlE/OS pin
performs a read operation. When RIW is
low, an active high signal on the ROlE/OS
pin performs a write operation.

be selected by PAO outputs ESO-ES?,
respectively. The EPROM banks are organized as 16K x 8.

which are fed into the PAO. This enables
the host microcontroller to enlarge its
address space by a factor of 16 (there can
be a maximum of 16 pages). See Figure 8 .

ALE or AS
ALE polarity is programmable. When
programmed to be active high, a high on
the pin causes the input address latches,
Port A address latches, Port C, and A 19
address latches to be transparent. The
falling edge of ALE locks the information
into the latches. When ALE is programmed
to be active low, a low on the pin causes
the input address latches, Port A address
latches, Port C, and A 19 address latches to
be transparent. The rising edge of ALE
locks the appropriate information into the
latches.

PSEN
The PSEN function enables the user to
work with two address spaces: program
memory and data memory (if COMB/SEP =
1). In this mode, an active low signal on the
PSEN pin causes the EPROM to be read if
selected. The SRAM and 1/0 ports read
operation are done by RO low (CRRWR =
0), or by E high and R/W high (CRRWR =
1, CEOS = 0) or by OS low and R/W high
(CRRWR, CEOS = 1).

As OS, the pin works with the R/W signal
as an active low data strobe signal. As OS,
the R/W defines the mode of
operation (Read or Write).

-----------------------------------,Arjr~;----------------------------------ifIf!"!!!!!Il£

2-225

•

PS0313

Control Signals
(Cont.)

PSEN
Whenever a member of the 8031 family
(or any other similar microcontroller) is
used, the PSD313's PSEN pin must be
connected to the PSEN pin of the
microcontroller.

SRAM, and 110 ports are read by RD low
(CRRWR = 0), or by E high and Riw high
(CRRWR = 1, CEDS = 0) or by DS low
and RIW high (CRRWR, CEDS = 1). See
Figures 9 and 10.

If COMB/SEP = 0, the address spaces of
the program and the data are combined. In
this configuration (except for the 8031-type
case mentioned above), the PSEN pin must
be tied high to Vc c , and the EPROM,

Figure 8.
Page Register

.-----r------------:; }
.-----r-------P1
r---T---PO

TOPAD

INPUTS

INTERNAL WR
PAGE SELECT

INTERNAL AD
AD1

y

ADO

)

DATA BUS

Table 8.
Signal States
During and After
Reset

Signal

Configuration Mode

Condition

ADO/AO-AD7/A7

All

A8-A15

All

Input

110

Input
Input
Low

PAO-PA7)
(Port A
PBO-PB7
(Port B)
PCO-PC2
(Port C)

Tracking ADO/AO-AD7
Address outputs AO-A7

110

Input

CS7-CSO CMOS outputs
CS7-CSO open drain outputs

Input
High
Tri-stated

Address inputs A 16-A 18
CS8-CS10 CMOS outputs

Input
High

-------------------~~~~-------------------2-226

PSOS1S

FigureS.
Combined
Address Space

cs

ADDRESS

PAD

SRAM

INTERNAL

TableS.
Internal States
During and After
Reset

Component

Signals

PAD

CSO-CS10

All - 1 (Note 11)

CSADIN, CSADOUT1,
CSADOUT2, CSIOPORT,
RSO, ESo-ES7

All = 0 (Note 11)

n/a
n/a
n/a
n/a

0
0
0
0

Data register A
Direction register A
Data register B
Direction register B
NOTE: 11. All PAD outputs are

Figure 10.
8031-Type
Separate Code
and Data
Address Spaces

In

Contents

a non-active state.

INT ERNAL
RD

AD RESS

I

1/0

PORTS

(JE

CS

•

4

J

•

• I

•

OE
~

PAD

CS

SRAM

cs

Pm!

EPROM
OE

---------------------------~Jr;'----------------------~2-~n~7

•

PS0313

Control Signals
(Cont.)

Table 10. Signal
States During
Power-Down
Mode

RESET

A19/CSI

This is an asynchronous input pin that
clears and initializes the PSD313. Reset
polarity is programmable (active low or
active high). Whenever the PSD313 reset
input is driven active for at least 100 ns,
the chip is reset. During boot-up (Vee
applied), the device is automatically reset
internally (internal automatic reset is over
by the time Vee operating range has been
achieved during boot-up). Tables 8 and 9
indicate the state of the part during and
after reset.

When configured as CSI, a high on this pin
deselects, and powers down, the chip. A
Iowan this pin puts the chip in normal
operational mode. For PSD313 states
during the power-down mode, see Tables
10 and 11, and Figure 11.

Signal

In A19 mode, the pin is an additional input
to the PAD. It can be used as an address
line (CADLOG3 = 1) or as a generalpurpose logic input (CADLOG3 = 0). A19
can be configured as ALE dependent or as
transparent input (see Table 7). In this
mode, the chip is always enabled.

Configuration Mode

Condition

ADO/AO-AD7/A7

All

Input

A8-A15

All
1/0
Tracking ADO/AO-AD7/A7
Address outputs AO-A7
1/0
CSO-CS7 CMOS outputs
CSO-CS7 open drain outputs
Address inputs A18-A16
CS8-CS10 CMOS outputs

Input
Unchanged
Input
A1I1's
Unchanged
A1I1's
Tri-stated
Input
A1I1's

PAO-PA7

PBO-PB7
PCO-PC2

Figure ".

ADDRESS INDICATOR
TO EPROM

AI9/CSI Cell
Structure

ALE-----------,
A19
1-----. TO
PAD
A19/CSI--

A ....--"''''-'''....:::..:.=.:'-=....=:..:''"''-'=-------.. TO PAD, EPROM, SRAM,

-1 i

PORTS, LATCHES, ETC.

-=-:

NOTE:

12. The CADDHLTconfiguration bit determines if A19-A16 are transparent via the latch, or
if they must be latched by the trailing edge of the ALE strobe.

----------------------------------',Jr~:----------------------------------~.,,-

2-228

1'10313

Table 11.
Internal States
During PowerDown

Component

Signals

PAD

Data register A
Direction register A
Data register B
Direction register B

Security Mode

All 1's (deselected)

CSADIN, CSADOUT1 ,
CSADOUT2, CSIOPORT,
RSO, ESO-ES7

All O's (deselected)

nfa
nfa
nfa
nfa

All
unchanged

be set by the MAPLE or Programming
software. In window packages, the mode is
erasable through UV full part erasure. In
the security mode, the PSD313 contents
cannot be copied on a programmer.

Security Mode in the PSD313 locks the
contents of the PAD A , PAD B and all the
configuration bits. The EPROM, SRAM,
and 1/0 contents can be accessed only
through the PAD. The Security Mode can

Figure 12.
PS0313
Interface With
Intel's BBe31

Contents

CSO-CS10

Vee

31

-

19

PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7

EAtvP
X1

CJ
18

9

12
13
14
15
1
2
3
4
5
6
7
8

X2

RESET

INTO
INT1
TO
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

~
-=-

0.1~F

Microcontroller

P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7

AD
WR
PSEN
ALE
TXD
RXD

39
38
37
36
35
34
33
32

23
24
25
26
27
28
29
30

21
22
23
24
25
26
27
28

31
32
33
35
36
37
38
39

17
16
29
30
11
10

22 AD
2 WANpp
1
BHEtPSEN
13
ALE
3
RESET

ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD5/A5
AD6/A6
AD7/A7

PAO
PA1
PA2
PA3
PM
PA5
PA6
PA7

AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

AD4/M

PC2
A19/CSi

11
10
9
8
7
6
5
4
40
41
42
43

GND

PSD313

8OC31

PCO
PC1

21
20
19
18
17
16
15
14

34

12

-

The configuration bits for Figure 12 are:

o or 1 (both valid)

CRESET

1

COMBfSEP

CALE

0

CRRWR

0

CDATA

0

CEDS

0

CADDRDAT
All other configuration bits may vary according to the application requirements.

_____________________________________

rl~~~------------------------------------

'rI1#_ -

2.229

•

PSD313

System
Applications

Figure 13.
PSD313
Interface With
Motorola's
6BHe11

In Figure 12, the PSD313 is configured to
interface with Intel's 80C31 , which is a 16bit address/8-bit data bus microcontroller.
Its data bus is multiplexed with the loworder address byte. The 80C31 uses
signals RD to read from data memory and
PSEN to read from code memory. It uses
WR to write into the data memory. It also
uses active high reset and ALE signals. The
rest of the configuration bits as well as the
unconnected signals (not shown) are application specific and, thus, user
dependent.

In Figure 13, the PSD313 is configured to
interface with Motorola's 68HC11, which is
a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the
low-order address byte. The 68HC11 uses
E and R/W signals to derive the read and
write strobes. It uses the term AS (address
strobe) for the address latch pulse. RESET
is an active low signal. The rest of the
configuration bits as well as the unconnected signals (not shown) are application
specific and, thus, user dependent.

Vee

Microcontroller
20
21
22
23
24
25

PDO
PDl
PD2
PD3
PD4
PD5

43
45
47
49
44
4S
48
50

PEO
PEl
PE2
PE3
PE4
PE5
PES
PE7

34
33
32
31
30
29
28
27

PAO
PAl
PA2
PA3
PA4
PA5
PAS
PA7

52
51

VRH
VRL

PCO
PCl
PC2
PC3
PC4
PC5
PCS
PC7
PBO
PBl
PB2
PB3
PB4
PB5
PBS
PB7

9
10
11
12
13
14
15
lS

23
24
25
2S
27
28
29
30

42
41
40
39
38
37
3S
35

31
32
33
35
3S
37
38
39

5

22

S
4
17

2
13
3
1

E

RiW
AS

FiEsET
XiRQ
iRQ
MODB
MODA
XTAL

18
19
2
3

ADO/AO
AD1/Al
AD2!A2
AD3/A3
AD4/A4
AD5/A5
ADS/AS
AD7/A7

PAO
PAl
PA2
PA3
PA4
PA5
PAS
PA7

AD8/A8
AD9/A9
AD10/Al0
ADll/All
AD12/A12
AD13/A13
AD14/A14
AD15/A15

PBO
PBl
PB2
PB3
PB4
PB5
PBS
PB7

E

PCO
PCl

RIWNpp
AS
RESET

BREiPSEN"

11
10
9
8
7
S
5
4
40
41
42
43

Vee
GND

EXTAL

PSD313

68HC11

PC2
A19/Csi

21
20
19
18
17
16
15
14

34

12

-

The configuration bits for Figure 13 are:
CRESET

0

COMB/SEP

CALE

0

CRRWR

1

CDATA

0

CEDS

0

0

CADDRDAT
All other configuration bits may vary according to the application requirements.

-------------------------------------;A;Ar~~------------------------------------
"'I!!!FIB

2-230

P50313

Absolute
Maximum
Ratings 13

Symbol

Parameter

TSTG

Storage Temperature

Condition

Min

Max

Unit

-65

+ 150

°C

Voltage on any Pin

With Respect to GND

- 0.6

+7

V

Vpp

Programming
Supply Voltage

With Respect to GND

-0.6

+14

V

Vce

Supply Voltage

With Respect to GND

-0.6

ESD Protection

+7

V

>2000

V

NOTE: 13. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.

Operating
Range

Range

Temperature

Commercial

Recommended
Operating
Conditions

DC
Characteristics

Tolerance

Vee

-12

-15

-20

±5%

0° C to +70°C

+5V

± 10%

± 10%

Industrial

-40° C to +80°C

+5V

± 10%

± 10%

Military

-55° C to + 125°C

+5V

± 10%

± 10%

Symbol

Parameter

Conditions

Min

Typ Max Unit

vcc

Supply Voltage

-12 Version

4.75

5

5.25

vce
V 1H

Supply Voltage

-15/-20 Versions

4.5

5

5.5

High-level Input Voltage

Vee ~ 4.5 V to 5.5 V

2

V 1L

Low-level Input Voltage

Vee ~ 4.5 V to 5.5 V

0

Symbol

Parameter

Conditions

VOH

Output Low Voltage

Output High Voltage

Vee~4.5V

ISB1
ISB2

Ice1

0.1

0.15 0.45
4.4

4.49

2.4

3.9

V

Vee Standby Current
(CMOS) (Notes 14 and 16)

Comm'l

50

100

Ind/Mii

75

150

Vee Standby Current
(TTL) (Notes 15 and 16)

Comm'l

1.5

3

Ind/Mil

2

3.2

Active Current (CMOS)
(SRAM Not Selected)
(Notes 14 and 17)

V

V

IOL ~ 8 mA
Vce ~ 4.5 V

IOH ~-2 mA

0.8

0.01

Vee~4.5V

IOH ~ -20 ~A
Vee ~ 4.5 V

V
V

Min Typ Max Unit

IOL ~ 20 ~A
VOL

V

Comm'l (Note 18)

16

35

Comm'l (Note 19)

28

50

Ind/Mil (Note 18)

16

45

Ind/Mil (Note 19)

28

60

~A

mA

mA

-----------------------------------~~sr----------------------------------2-231

•

PS0313

DC
Characteristics
(Cont.)

Symbol

Parameter
Active Current (CMOS)
(SRAM Block Selected)
(Notes 14 and 17)

Icc2

Active Current (TIL)
(SRAM Not Selected)

Icc3

47

80

Comm'l (Note 19)

59

95

Ind/Mil (Note 18)

47

100

Ind/Mil (Note 19)

59

115

Comm'l (Note 18)

36

65

Comm'l (Note 19)

58

80

Ind/Mil (Note 18)

36

80

(Notes 15 and 17)
Active Current (TIL)
(SRAM Block Selected)

Icc4

Min Typ Max Unit

Conditions
Comm'l (Note 18)

(Notes 15 and 17)

Ind/Mil (Note 19)

58

95

Comm'l (Note 18)

67

105

Comm'l (Note19)

79

120

Ind/Mil (Note 18)

67

130

79

145

Ind/Mil (Note 19)

III

Input Leakage Current

VIN = 5.5 V or GND

-1

± 0.1

1

ILO

Output Leakage Current

VO UT = 5.5 V or GND

-10

±5

10

mA

mA

mA

~

NOTE: 14. CMOS [nputs: GND ± 0.3 Vor Vcc ± 0.3V.
15. TTL inputs: VIL S 0.8 V, VIH '" 2.0 V.
16. CSIIA19 is high and the part is in a power-down configuration mode.
17. AC power component is 3.0 rnA/MHz (power = AC + DC).
18. Ten (10) PAD product terms active. (Add 380 ~ per product term, typical, or 480 ~
per product term maximum.)
19. Forty-one (41) PAD product terms active.

AC
Characteristics
(See Timing
Diagrams)

Symbol

Parameter

-12
Min Max

-15
Min Max

-20
Unit
Min Max

T1

ALE or AS Pulse Width

30

40

T2

Address Set-up Time

9

12

15

T3

Address Hold Time

13

15

25

T4

ALE or AS Trailing Edge
to Leading Edge of Read

12

15

20

T5

ALE Valid to Data Valid

130

140

170

T6

Address Valid to
Data Valid

T7
T8

CSI Active to Data Valid
Leading Edge of Read to
Data Valid

50

120

150

200

130

160

200

38

55

60

T9

Read Data Hold Time

0

0

T10

Trailing Edge of Read to
Data High-Z

T11

Trailing Edge of ALE
or AS to Leading
Edge of Write

12

15

20

T12

RD,E,PSEN,DS
Pulse Width

45

60

75

WR Pulse Width

32

40

35

25

35

45

T13

Trailing Edge of Write or
Read to Leading Edge
of ALE or AS

0

0

0

T14

Address Valid to Trailing
Edge of Write

120

150

200

T12A

ns

0

----------------------------------~~Jr--------------------------------2-232

PSD313

AC
Characteristics
(Cont.)

Symbol

Parameter

·12
·15
·20
Unit
Min Max Min Max Min Max

T15

CSI Active to Trailing
Edge of Write

130

160

200

T16

Write Data Set-up Time

20

30

40

T17

Write Data Hold Time

5

10

15

T18

Port Input Set-up Time

30

35

45

T19

Port Input Hold Time

0

0

0

T20

Trailing Edge of Write
to Port Output Valid

40

50

60

T21

ADi or Control to
CSOi Valid

6

35

6

40

5

45

T22

ADi or Control to
CSOi Invalid

5

35

4

40

4

45

T23

Track Mode Address
Propagation Delay:
CSADOUT1 Already True

22

28

28

Track Mode Address
Propagation Delay:
CSADOUT1 Becomes
True During ALE or AS

33

50

50

T23A

T24

Track Mode Address
Holding Time

T25

Track Mode Read
Propagation Delay

T26

Track Mode Read
Hold Time

T27

Track Mode Write Cycle
Data Propagation Delay

T28

Track Mode Write Cycle
Write to Data Propagation
Delay

8

T29

Hold Time of Port A Valid
During Write CSOi
Trailing Edge

2

T30

CSI Active to CSOi Active

9

45

9

55

8

60

T31

CSllnactive to CSOi
Inactive

9

45

9

55

8

60

T32

Direct PAD Input as
Hold Time

10

12

15

T33

R/W Active to E or
DS Start

20

30

40

T34

E or DS End to R/W

20

30

40

T35

AS Inactive to E High

15

20

25

15

27
29

11

29

35
10

20

30

27

29

35
10

30
7

40

4

ns

35
30

7

55

4

NOTES: 20. ADi = any address line.
21. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or
through Port C (CSB-CS10).
22. Direct PAD !!!eut = any of.!!1e following direct PAD input lines: CSI/A19 as transparent
A 19, RD/E/DS, WR or RIW, transparent PCO-PC2, ALE (or AS).
23. Control signals RD/E/DS or WR or RJW.

"'Ir~

----------------------------------~.,,------------------------------2--2-3-3

PSD313

Figure 14.
Timing of 8-Bit
Multiplexed
Address/llata
Bus, CRRWR = 0
READ CYCLE

WRITE CYCLE
32

-~

----..,
CS I/A19
as CSI

Direct(24)
PAD In put

Multiplex ed (25)
Inputs

.:x

~

-

STABLE INPUT
6

x:

ill'

roo ~

I DATA

ADDRESS A
2

-

\ OUT

3
4

32

I-

[XXX XXX

IXXXX X.XXX

!.Dr-:-

ADDRESS B

~

,f4~I-'

5

BHE/P-SEN
asP-SEN

~

X
, IXXXXXXXXX

~ r-

11
\.....

rL
Lr

I'----'

~

20

I--

INPUT

)(XXXXXXXXXxxxxxxn XX

OUTPUT

INPUT

:)( xxxxxxxxxxxxxxxxxxx

OUTPUT

23
_~
~

~

1-

13

or

X,XXXXXXXXX

I

X

~-

R,wasWR

PA7 as 1/0 Pin ,

1'--Ir--

D'iJA

~

I-'

~

r-

3

~

~

RD/E/DS asRD

Any of PAOPA7 Pins
as Ad dress
Outputs

XX) [XXXX

14

81-

Active Low'
ALE
~--1

Any of PBOPB7 as 1/0 Pin

t-

14

~

1+-2-.

Any of PAO-

32

Ir--

Ir~
Active High
ALE I

WRNpp

STABLE INPUT

XXX XXX DO XXX
6

AOIADOA7IAD7

15

I

7

-

.E.
ADDRESS A

ADDRESS B

See referenced notes on page 2-239.

----------------------------------~~~---------------------------------
r:tr~.." . .

2-234

PS0313

Figure 15.
Timing of 8-Bit
Multiplexed
Address/Data
Bus, CRRWR = 1

..

READ CYCLE

Direct(24)
PAD Input

1\
7

.:x

1-

~

STABLE INPUT
6

Multiplexed (25) ......
Inputs

DCXXXXY

)C

~

2
Active High
AS I

-

3

4

32

~ ~.

-

14

}-

ADDRESS B

~

3

~

DATA
IN

~

h

12

•

XXXX IXv..x
14

~I-

35

IIXXX :l(XX

STABLE INPUT

~

)()C

~v-

rL
i'-- Lr

35

f-1
33

34

34

J

RD/E/DS as E
5

~

,

--

RD/EIDSas DS

WRNp P2!:

32

14- .2...
33

RiWas RIW

'XX IXXXX

15

81-

Ir n

Active Low'
AS

I-

~

'DATA
OUT

ADDRESS A

...
-32

-

~

6

AOIA DOA71AD7

WRITE CYCLE

-~

-----.
CS I/A19
as CSI

...-

32

,~

~

~

~

tr-

XX XX X

DIXXXXXXX

~

~

~

Any of PAOPA7 as 1/0 Pin

~ IXXXXXXXXX

INPUT

XXXXXXXXXxxxxxxn :'i.Y.'

OUTPUT

Any of PBOPB7 as 1/0 Pin

[XXXXXXXXX

INPUT

:) XXXXXXXXXXXXXXXXXXY'

OUTPUT

Any of PAOPA7 Pins
as Add ress
Outputs

,

~

~

---=----..

ADDRESS A

ADDRESSB

See referenced notes on page 2-239.

----------------------------------,JrJr~:--------------------------------."..,.
2-235

PS0313

Figure 16.
Timing of 8-Bit
Data NonMultiplexed
Address/Data
Bus, CRRWR -- 0

-

READ CYCLE

~

CS I/A19
a s CSI

Direct (24)
PAD Input

AOIADOA15/A D15

7

.:x
.:x

asAO -A15

.

-~
32

-

STABLE INPUT

~

STABLE INPUT

6

X;

- ~~

--1

2

Active Low
ALE

3

h

"

4

STABLE INPUT

-

IYxx :XXX
I32

D(XX)( ~

~

-

DATA
OUT

DATA

IN

~

8-

-

\
5

.

3

--,

.2-.

'- f--/

4
~

~

1'---

Ir-

~

----'

~

p or
sWR

~

XI r -

11

J

•

~

14

.!.l:

* f2.+

RD/E/DSasRD

Any of PBOPBl as 1/0 Pin

:ffl

IXXX

I~

6

I

'XXJ lXXXX

14

XXXXXX XJ XXX

PAO - P A l '

Active High
ALE

I-

STABLE INPUT

32

Multiplexe d (25)
Inpu ts

-

..

32

15

~~

~

WRITE CYCLE

IL

U-

~

'--1

XXX'/XttXXX
,}

~
INPUT

~

~

'l.'fXY.Xl.xXXXXXXXXX'N'tJ

OUTPUT

See referenced notes on page 2-239.

---------------------------------~aF~--------------------------------2-236

PS0313

Figure 17.
Timing of 8-Bit
Data NonMultiplexed
AddreSS/Data
Bus, CRRWR =1

...

READ CYCLE

;:------'\

CS I/A19
asCSI

7

Di rect (24) ,]:
PAD In put

00<

~

-~
32

00

STABLE INPUT

1-

Multiplexed (25) ~
_
Inputs

--1
2

-

3

Active High ~ h
ALE I

4

DATA
OUT

~~

STABLE INPUT

-..::;;

DATA
IN

.2..
12

33

~

~r-l '\
Lo-

33

34

'"-

L

35

~

34

~

asDS

Any of PBD- \
PB7 as IIOPin ,..

xx:

171

3

-1

5

WRN PP 2!:

-

I

RD/E/DS as E

R!Was R/W

~

14

2_

35

IXXX 'XXX

IXXXX IXXXX

~

1- r--"

'XX IXXXX

32

~

1+ f2-

i.-

14

32

81-

32

IXXX :)(XX

STABLE INPUT

~

PAD -PA7 '

-

15

IXXXXXX n IXXX
6

Active Low,
ALE

WRITE CYCLE

~~

STABLE INPUT
6

ADIADD- ,]:
A151AD15
asA D-AI5

...

\

J

'----'

XX XX.XXX,

r-

.XXXXX
~

18

XXXXXXXXX

~

INPUT

~

XX XX Xx:XXXXXXXXX XX XX

OUTPUT

See referenced notes on page 2-239.

---------------------------------~Jr~-------------------------------2-237

•

PSD313

Figure 18.
Chip-Select
Output Timing

~

30

CSI/A19
asCSI

I

Direct PAD (24)
Input

Multiplexed (30)
PAD Inputs

INPUT STABLE

~

X

XXXXXXX :X [XX'
',

~

2

ALE
(Multiplexed
Mode Only)

1 -r--

J"I

3

Irh

V

If. ~

orALE
(Multiplexed
Mode Only)

\

IL

1'-/----1
22

21

I- It--

CSOi (26,31)

Figure 19.
PortA as
ADD-ADl Timing
(Track Mode), Direct (24,27)
CRRWR=O
PAD
Input
Multiplexed (28,30)
PAD Inputs

...

XX;

READ CYCLE

INPUT STABLE

orALE

ADDRESS

XXXXXXX Ie :X

I! __

~

XXXX)lXXX

READ
DATA

ADDRESS

1/1----1

f. t-2.

j-If-2-..

I'- j---I

1\1----1

}-1

1

WRITTEN
DATA

1- r~

V\~

~

4

.I
.I

12

-

~

24

-'23~

--<:TI

X

3

ft~

I

PAO-PA7

INPUT STABLE
2

Ir h

RD/E/DS as RD

WRNppor
RiWasWR

32

INPUT STABLE

I

3

-- -

WRITE CYCLE

f+- ~

~

AO/ADOA7/AD7

f.J

.. ..

I-

INPUT STABLE

2

ALE

-

~

-. 23

DATA
IN

J

I

CSOi (26,29)
See referenced notes on page 2-239.

}-

12

11

OUT

1-

27 -

\

~

DATA
OUT

~

~

~

------------------------------------'A;Arjf~------------------------------------..,.,.
2-238

PS0313

Figure 20.
PortA as
ADD-AD7 Timing
(Track Mode),

32

.....

CRRWR= 1
Direct
PAD

(24,27)

READ CYCLE

-

-32

r:. . .

WRITE CYCLE

~-"IIr--+-----------n.Ir--+------------"klNV""""'JJ,xvboct:'XrIN:-:ip~U-:::T:-:S::T:-:-A-=-B:-:LE:1X>JXrJ\JX\JX,\J
O\I
X,~
X: X7'i:X7tJlbo,rn
X

(28,30) ......

--LJ~~VI\-':':2+::":"":'3.:..:..::=:..p
IO£\aI~l¥lP~L2..::.:;r-.:::"":::':":"::::::':::,.I~Dl.~~illf~OJ

I

~I-wr

I

~TA

3

I

-~~~.I~-A~D-D-R-E-S-S-~'r-~~~AD~Ir--+----h
ADDRESS

AO/ADOA7/AD7

)--

WRIDEN
DATA I

'-

v~

AS

f4~
35

or AS

33
,..-

RD/E/DSas E

RD/E/DS as DS

XXX

X

:XXX
24

~~
ADR
OUT

~

~

I

~

.lIX
~

--23

PAO-PA7

1/ """\

I

\

WRNpp or
RiWasRtW

f-

'\
~

r--L

V-

12

35

12
33

321-

r-

XXXX
~

--23"';'

-27-~

_ _ _-I~DA~T'AA-)- ~ADR~_ _ _t-~r~DA~T'5Alh
IN
OUT
OUT

I

~

CSOi (26,29)

Notes for
Timing
Diagrams

24. Direct PAD input = any of the following direct PAD input lines: CSIIA19 as transparent A19,
RD/E/DS, WR or RiW, transparent PCo-PC2, ALE in non-multiplexed modes.
25. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS):
AO/ADO-A7/AD7, CSI/A19 as ALE dependent A19, ALE dependent PCo-PC2.
26. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or through
Port C (CSS-CS10).
27. CSADOUT1, which internally. enables the address transfer to Port A, should be derived only
from direct PAD input signals, otherwise the address propagation delay is slowed down.
28. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively,
can be derived from any combination of direct PAD inputs and multiplexed PAD inputs.
29. The write operation signals are included in the CSOi expression.
30. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE
(or AS) in the multiplexed modes: A11-A15, CSI/A19 as ALE dependent A19, ALE dependent
PCO-PC2.
31. CSOi product terms can include any of the PAD input signals shown in Figure 3, except for
reset and CSI.

!F'.~"=

---------------------------------------~~I--------------------------------------

2-239

•

PSD313

Table 12.
Pin
Capacitance 32

Symbol
C IN

Parameter

Conditions Typical33 Max Units
VIN = a v

Capacitance (for input pins only)

COUT

Capacitance (for input/output pins)

VOUT = a v

CvPP

Capacitance (for WRlVpp or R/WlVpp)

V pp =

av

4

6

pF

8

12

pF

18

25

pF

NOTES: 32. This parameter is only sampled and is not 100% tested.
33. Typical values are for T A = 25°C and nominal supply voltages.

Figure 21.
AC Testing
Input/Output
Waveform

3· 0 V
0V

-V
--.A

v-:-:

TEST POINT - - ~V

Figure 22.
AC Testing
Load Circuit

2.01 V

195
DEVICE
UNDER
TEST

I

Q

CL =30pF

(INCLUDING
SCOPEANDJIG
":'" CAPACITANCE)

Erasure and
Programming

To clear all locations of their programmed
contents, expose the device to ultra-violet
light source. A dosage of 15 W second/cm2
is required. This dosage can be obtained
with exposure to a wavelength of 2537 A
and intensity of 12000 flW/cm2 for 15 to 20
minutes. The device should be about 1
inch from the source, and all filters should
be removed from the UV light source prior
to erasure.
The PSD313 and similar devices will erase
with light sources having wavelengths
shorter than 4000 A. Although the erasure
times will be much longer than with UV
sources at 2537 A, exposure to fluorescent
light and sunlight eventually erases the
device. For maximum system reliability,

these sources should be avoided. If used in
such an environment, the package
windows should be covered by an opaque
substance.
Upon delivery from WSI, or after each
erasure, the PSD313 device has all bits in
the PAD and EPROM in the "1" or high
state. The configuration bits are in the "0"
or low state. The code, configuration, and
PAD MAP data are loaded through the
procedure of programming
Information for programming the device is
available directly from WSI. Please contact
your local sales representative.

_____________________________________ f§;~E------------------------------------2-240

FiFii!EE

PSD313

Pin
Assignments

Name
PSEN
WR/V pp or Rm
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
GND
ALE or AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
RD/E/DS
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
A8
A9
A10
GND
A11
A12
A13
A14
A15
PCO
PC1
PC2
A19/CSI
Vee

44-Pin
PLOCC/ 44-Pin
CP6A
CLOCC Package
Package
1
2
3
4

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

As
A4
B4
A3
B3
A2
B2
B1
C2
C1
D2
D1
E1
E2
F1
F2
G1
G2
H2
G3
H3
G4
H4
Hs
Gs
H6
G6
H7
G7
Ga
F7
Fa
E7
Ea
Da
D7
Ca
C7
Ba
B7
A7
B6
A6
Bs

•

______________________________ ',.JFE_____________________________

'#;//f.'

2-241

PSD313

Package
Information

I~
a:

..

0
It)

 « c. c. c.
... '" ... '"... ;;;: ...
t.i L: : i j j Ll t.! t__ ; Lj 1..j
I-

J)

....
m

..

W >

til
M

.. ..

0

()

()

M

~

0

.. '-.:

,._..-.-_ ] 39 A15

PB4

7 [ ------.,

PB3
PB2

8 [. __ .;

c_·:. ] 39

9 [-._..:.,

,.:.-.-. ] 37 A 13

PBO 11

[_.:_.:J
[.-_-_.:J

,..-_._.. ] 35 All

GND 12

[::::J

,-_..-.-_ ] 34 GND

PBl 10

A14

,-.-_-.-. ] 36 A12

c_·.-.-. ] 33 A 10

ALE or AS 13 [_..-:_.,

c.-_·:. ]
C:_·_ 1

PA7 14 [.-.-::,
PA6 15

32 A9
31 A8

,:. -.-. p30 AD7/A7
,.:_._._ p29 AD6/A6

PA5 16
PA417

~ ~

0

'"
« «
'"c. :;:c.
c.
M

N
~
c.

.

..

'"'" '" '" '" '" ....'" re
I~
«
W ~ ~ '"
~ ~ ~ ~
M

0

It)

t3->--4P1.4
5
.>-j51.S
P1.6
P1.7

>--}-

H--

>--t>---"'--

RESET
P2.0

INT1
14
t~i~31~3~
TO
15

<

r--'U,,2'-_ _ _ _ _ _ _ _-----.
PO.O
PO.1
PO.2
PO.3
PO.4
PO.S
PO.6
PO.7

INTO

~~.~

INT1
TO

P2.3
.
P2.4

T1
Pl.Q
P1.1
P1.2
P1.3
P1.4
P1.S
Pl.6
Pl.7

8OC31

~~:~
P2.7
RD
WR
PSEN
ALEIP
TXD
RXD

39
38
37

23
24
25

34
33
32

28
29
30

21
22

31
32

23
25
24
26
27
28

38
39

17
16
29
30

22
2
1
13

~~

ADO/AO
AD1/A1
AD2IA2
AD3/A3
AD4/A4
ADS/AS
AD6/A6
AD7/A7

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7

AD8/A8

33

~g~~~~10

PBO

36
35
37

AD11/A11
AD121A12

PB3
PB4

~~

~
_

I

~

,.;L-

~~~

~gi~~~i!

~~~

AD1S/A1S

PB7

RD
WRIVPP
BHEIPSEN
ALE
RESET

PSD3XX

A16/CS8
A17/CS9
A18/CS10
A19/CSI

21
20
19

~AO

16
15
14

~P~

i~

11
10

PA1

~
PA3
PAS
PA6
PA7
~
~

9

~

7
8
6

~PB3
PB4

5
4

~40.
41
42
43
GND

~~~
PB7

PSD3XX - Application Note 011

TwoPSD3XX
Byte-Wide
Interfaces to the
Intel BOC31

Table 4.
BOC31 Interface
to Two PSD3XX
Devices with
Power Economy
Feature

Figure 11 illustrates an extension to the
previous design in that two PSD3XX devices
have been used, doubling the memory and
port resources of the system solution. In this
application, the power-down capability has
been used so that one PSD3XX can be active
while the other device is in power-down
mode. The mean power consumption is
reduced, so this configuration can be considered for power-sensitive applications.

Configuration
CDATA

Bits
0

The configuration Table 4 indicates that Port
C has been configured as outputs. Provided
one PSD3XX is powered up for the whole
address range, its PAD can decode an
address range to select and deselect the
second PSD3XX device through the CS1 0
output. In Figure 11, the PAD output A 18/
CS10 on PSD3XX U2 can be used to powerdown the second PSD3XX through the A 19/
CSI input.

Function
8-bit data bus

CADDRDAT

1

Multiplexed address/data

CRRWR

0

Set RD and WR mode

CA19/CSI

0

Set CSI input power-down mode

CALE

0

Active HIGH ALE

CRESET

1

Active HIGH RESET

COMB/SEP

1

Code and data memory separate
Input/Output Port A

CPAF2

0

CPAF1

OOH

CPBF

FFH

Input/Output Port B

CPCF

111 B

Outputs CS8-CS 10

CPACOD

OOH

Configure CMOS outputs Port A

CPBCOD

OOH

Configure CMOS outputs Port B

CADDHLT

X

"Don't care" for latched A 16-A 19

CSECURITY

0

No security

•

Input/Output Port A (0-7)

It is not recommended that the two PSD3XX
devices select each other because the PAD
section of a PSD device is powered down
with the rest of the device. At least one PAD

decoder must be kept active to select and
deselect others. Port C outputs CS16-CS18
can power-down as many as three other
PSD3XX devices.

-----------------------------------f~=_=:----------------------------------

2-265

~!~
-a
tl ~ !
C;' - ; ;

~

~

~~
::t~-a.

8

~'

CI)~

~
)(

~
I

:...

!n'
a

E·

Is

...

C3
20pF

U3

U2
GND

19

I-

X1

~~iiQ:

qlillQI
Ihlllill
QIIIII"

18

I

9

I

X2

PO.O
PO.1
PO.2
PO.3
PO.4
PO.S
PO.6
PO.?

RESET
P2.0
INTO
INT1
TO
T1
P1.D
P1.1

P1.2
P1.3
P1.4
P1.5
P1.6

~

aDC3l

f®5<
TXO:
Vee

1

C1

R1

GND

P2.1
P2.2

P2.3
P2.4

P2.S
P2.6
P2.7
RD
WR
PSEN
ALE!?
TXD
RXD

39
38
37
36
35
34
33
32

23
24
25
26
27
28
29
30

21
22
23
24
25
26
27
28

31
32
33
35
36
37
38
39
22
2
1
13
3

ADO/AO

AD6/A6
AD7/A7

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

ADS/A8
ADS/A9
AD1 O/A1 0
AD11/A11
AD12fA12
AD13/A13
AD14/A14
AD15/A15

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13

ADO/AQ

AD1/A1
AD2/A2
AD3/A3
AD4/A4

ADS/AS

AD
WR/VPP
BHE/PSEN
ALE
RESET

A16/CS8
A17/CS9
A18/CS10
A19JCSI

AD1/A1
AD2/A2
AD3/A3
AD4/A4
ADS/A5
AD6/A6
AD7/A7

AD14/A14
AD15/A15
40
41
42
43
GND

PSD3XX

peoo
PC01

RD
WR/VPP
BHE/PSEN
ALE

RESET

PSD3XX

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
A16/CSa
A17/CS9

A18/CS10
A19/CSI

I'SIJ3XX - Application IItIfe 011

PSD3XX M6BHCI1
Byte-Wide
Interlace

Table 5.
M6BHC11 tD
PSD3XX Interlace

Figure 12 illustrates the configuration of an
M68HC11 microcontroller which also uses the
8-bits wide multiplexed address/data bus.
The application is similar to that given in
Figures 6 and 7 except that the RiW and E
control lines have been invoked to establish
compatibility with the Motorola device. The
address strobe output from the M68HC 11 is
HIGH so the AS(ALE) input is set HIGH. The
SRAM and EPROM section are programmed
as combined and both Ports A and Bare
enabled as I/Os with CMOS drives. Port C is
programmed with chip-select outputs
CS8-CS10. Other PSD3XX devices can be
mapped into the addressing scheme or the
lines can be programmed to transition as
strobes in defined mapping areas. The latch
enable bit for the higher-order address lines
A 16-A 19 is not used establishing a don't care
condition. The CADDHLT condition must be
selected if anyone of A 16-A19 lines is
selected as input to the PSD.

Configuration

Bits

In this design, the security bit is programmed.
This bit prevents the reading of the PAD
configuration by an unauthorized user.
Furthermore, if the security bit has been
programmed, standard programming machines can not read the internal code of a
PSD3XX. However, data can always be read
from the EPROM, RAM, and ports. This
provides normal use of the device. If the
address map in the PAD cannot be interpreted, the actual location of data within the
address and 1/0 space is difficult to determine. Besides programming the CSECURITY bit, added security can be applied by
scrambling the sequence of address and data
inputs. A short PASCAL or 'C' program can
be written to reorganize the original Intel MCS
code to be aligned with the scrambled pins.
Table 5 indicates the configuration for the
M68HC11/ PSD3XX interface.

Function

CDATA

0

8-bit data bus

CADDRDAT

1

Multiplexed address/data

CRRWR

1

Set R/IN and E mode

CA19/CSI

0

Enable CSI input

CALE

0

Active HIGH AS (ALE)

CRESET

0

Active LOW RESET

COMB/SEP

0

Combined memory mode

CPAF2

0

Input/Output Port A

CPAF1

OOH

Input/Output Port A

CPBF

FFH

Input/Output Port B

CPCF

111B

Output CS8-CS10

CPACOD

OOH

CMOS drivers

CPBCOD

OOH

CMOS drivers

CADDHLT

X

"Don't care" A 16-A19 not used

CSECURITY

1

Security on

-------------------------------~JrJr------------------------------2-267

•

~m~

~

"5 ;C~

i;=~;

"~ .....
S:::v~

=-1
fI)~

~

j

~I
~

:a

IEI

If

...

S

U1

XTAL

PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC7

XTAL
PDO
PD1
PD2
PD3
PD4
PD5

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PEO
PE1
PE2
PE3
PE4
PE5
PE6
PE7

I11"'"1
bllQ
IlItb
1011110

IQUIiIi

E
RMi

PAO
PA1

~PA2

Vee

R2
1K

AS

~~~

~~~

27

MOD~

MODA I
VRH
VRL

G-ND

ADO/AD
AD1/A1
AD2/A2
AD3/A3

27

A04/A4

16
17
18
19
20
21
22
23

31
32
33
35
36
37
38
39

5
6

22
2

~

XIRQ
IRQ

~PA5

23
24
25
26

4
17
18

RESET

PA3
PA4

~ ~

Vee

~

U3
2

I

Voo

RESET

~~

GND

MC34064

R1
4K7

--41-

28

ADS/AS

29
30

AD6/A6
AD7/A7

PAD
PA1
PA2
PA3
PA4
PA5
PA6
PA7

ADS/A8
AD9/A9
AD1 O/A1 0
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

PBO ~
PB1 ~
PB2
PB3 ~
PB4
PB5
PB6
PB7 ~

be

~

~

~
.....1±

-4-

E

BHEJPSEN
AS

3

~

~
---.g.

-+-%-+

"RiWivpp

,----&-

RESET

A16/CS8
A17/CS9

~
---±L

A18/CS10

---#
~

A19/CSI

GND

PSD3XX
Vee

~

68HCll

Vee

,lR-

8
9
10
11
12
13
14
15

R1
4K7

~

R1
4K7

I'SIJ3XX - Application 110", 811

B-BlT Non-Multiplexed PSD3XX
Interface to

Jf68DOB

Figure 13 illustrates an application in which
the address and data are not multiplexed.
The M68008 has an 8-bit data bus and 20-bit
address bus. The PSD3XX can be programmed to support the microprocessor by
providing data I/O through Port A. The
address lines from the microprocessor go to
inputs AD-A 19. Port B outputs are used for
external chip-selects to other MAP devices or
other memory resources. The configuration
has been set for compatibility with Motorola
control signals. There are six chip-select
outputs (CSO-CS5) and an address decode
for DTACK and BERR. The PAD decodes an
address range which is fed back to the
microprocessor through these inputs. Using
the open-drain configuration has been implemented in Port B bits 6 and 7. The two pullup resistors enable external memory and
peripherals to access the DTACK and BERR
inputs as a wired-OR function.

needed to avoid possible bus contention on
these lines. In this application, ALE (AS) can
be used as a general-purpose logic input to
the PAD because the function of ALE becomes redundant in a non-multiplexed
address/data bus. Also shown in Figure 13 is
a method of inverting the active LOW DS
(Data Strobe) M68008 output. The A 19 input
is enabled to the PSD internal PAD and
inverted at the output of CS1 0 to drive the
PSD3XX E input. The E input must be active
HIGH but DS is active LOW and qualifies a
valid data transfer. Thus, the PAD must
perform a signal inversion. The E signal
output from the M68008 is used to interface to
Motorola 8-bit peripherals. However, with
Motorola microcontroller families such as the
M68HC11, the E signal output can drive the E
input to the PSD3XX. Table 6 gives the
configuration information associated with the
design given in Figure 13.

If other· PSD3XX devices are mapped into the
M68008 system, no additional glue logic is

Table 6.
Jf68DOBto
PSD3XX Interface

Configuration

Bits

Function

CDATA

0

8-bit data bus

CADDRDAT

0

Non-multiplexed address/data

CRRWR

1

Set R/W and E mode

CA19/CSI

1

Enable A 19 input'

CALE

X

"Don't care" non-multiplexed mode

CRESET

0

Active LOW RESET

COMB/SEP

0

Combined memory mode

CPAF2

X

"Don't care" Port A used for data

CPAF1

XXH

"Don't care" Port A used for data

CPBF

OOH

Port B used for chip-selects

CPCF

001B

Configure A16 and A17 In, CS10 OuF

CPACOD

OOH

CMOS drivers

CPBCOD

3FH

CMOS drivers, PB6, PB7 open drain

CADDHLT

0

Address latch transparent A 16-A19

CSECURITY

1

Security on

1. The OS output from the M68008 drives the A19 input to the PSD3XX.
2. The internal PAD of the PSD3XX inverts the DS input to drive its own E input from the CSI 0 PAD output. A16 and
A17 are programmed as PSD inputs.

_____________________________________ ;jfAf~E-----------------------------------'riJ1#., B

2-269

•

:lDa.1:~

I

~I·
..S·B' ;.....

~I
c:I

~

r:::

I

t

~

II

I

r

~.

Is
I

Vee

Vee

R1
560R

R2
560R

DTACK
BERR

DTACK
~
U2

U1
CLK
~

15

IPLO/2
~

34
39

CLK
VPA

42
41

IPLO/2
IPL1

._I~

'EiR"'

~
~

FC',<

~
E

~

33
31
40

BR
DTACK
BERR

45

FCO
FC1
FC2

44
43
32

BG

38

E

36

HALT
RESET
AS
DS

~
29
~
~

R!W

68008

_.

AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

DO
D1
D2
D3
D4
D5
D6
D7

46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
14

23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39

=B T--¥-

ADO/AO

AD1/A1
AD2/A2
AD3/A3
AD4/A4
ADS/A5

AD6/A6
AD7/A7

ADS/A8
AD9/A9
AD10/A10
AD111A11
AD121A12
AD131A13
AD141A14
AD151A15

Vee

~
-1!L
27

~
25

23
~

=IR
21

~

1
13
3

E
RtWNPP
BHE/i5"§EN
AS
RESET

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7

21
20
19
18
17
16
15
14

11
PBO
10
PB1
9
PB2
8
PB3
7
PB4
6
PBS
5
PB6
PB7 ~
A16/CSS
A17/CS9

A18/CS10
A19/CSI

11
40
41

~

PSD3XX

OS

S

CSO

~
CS2
~
CS4
CS5

....

I'SII3XX - Application IIofB 011

16-BitNonMultiplexed
AddreSS/Data
PSD3XX Interlace
toM68ODO
Table 7.
M68ODO Microprocessor to one
PSD3XX Interlace

An extension to the design is shown in
Figure 14, with the configuration
information shown in Table 7. The M68000
interface to the PSD3XX has a 16-bit data
bus. Both Ports A and B are used to
convey data. The generation of an E input
to the PSD3XX has been extended from

Configuration

Bits

the signal inversion shown in Figure 13.
The M68000 has two data strobe signals
(LOS and UDS), to qualify the lower and
uppe~tes of a 16-bit word. The LOS
and UDS lines drive the A18 and A19
inputs and are gated to provide the correct
logic condition into the M68000.

Function

CDATA

1

16-bit data bus

CADDRDAT

0

Non-multiplexed address/data

CRRWR

1

Set R/Wand E control inputs

CA19/CSI

1

Enable A19 input

CALE

X

ALE polarity set at "don't care"

CRESET

0

Active LOW RESET

COMB/SEP

0

Combined memory mode

CPAF2

X

"Don't care" Port A

CPAF1

XX

"Don't care" Port A

CPBF

X

"Don't care" Port B

CPCF

110B

Enable A16 and A17 Out, A1a In'

CPACOD

OOH

Configure CMOS buffers Port A

CPBCOD

OOH

CADDHLT

0

Transparent A 16-A 19

CSECURITY

0

Secu rity off

Configure CMOS buffers Port B

1. Outputs UDS and LDS drive the A18 and A19 inputs of the PAD and are gated internally to give a valid E input
signal to the M68000 from the CS9 output. DTACK comes from the CS8 output.

This application takes advantage of the AS
input which is redundant as a latch control
input in a non-multiplexed system; however, it
can be used as general-purpose logic input to

...

the PAD. CS9 and csa are used as output
signals to the M68000's DTACK and BERR
inputs.

-----------------------------------~~:---------------------------------2-271
~611'.

•

:t..=--~

~

'!.
:'II
;:;. l!!!iiiiciS'
;;:

~

~

!

I
I

1M ' t

R i

:.c

Is

....

U2
U1
15
23
27
26
25

~

~

12
13
10
24
30
29
28
11
21
22

CLK
VPA
IPLO
IPL1
IPL2
BGACK
BR
DTACK
BERR
FCO
FC1
FC2
BG
VMA
E

A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21

A22
A23

HALT
RESET
AS
UDS
LDS

R!W

32
33
34
35
36
37
38
39

40
41
42
43
44
45
46
47
48
49
50
51
53
54
55

ADO/AO
ADlIA1
AD2IA2
AD3/A3
AD4IA4
ADS/AS
AD6/A6
AD7/A7
AD8IA8
AD9/A9
AD10/A10
AD11/A11
AD121A12
AD13/A13
A014/A14
AD15/A15
E
RtWNPP

~~E/PSEN
RESET

~

UD

ill

A16/CS8
A17/CS9
A181CS10
A19/CSI

·o=t>:r

LDS(A19)

UDS(A18) INPUTS E(CS9

SIGNAL

PSD3XX - Application Note 011

M6S000/
2XPSD3XX
Applications

TableS.
M6S000 Microprocessor to Two
PSD3XX Devices
in Parallel

With the circuit design given in Figure 15, two
PSD3XX devices are used in a byte-wide
mode. One PSD stores the upper data byte
and one the lower data byte of a 16-bit word.
By using the devices in this way, two 6-bit
wide ports can be created in Port B of each
device. PB6 and PB7 are programmed as
open-drain outputs and wired-OR giving

Configuration

Bits

composite DT ACK and BERR feedback
signals to the M68000. The generation of the
E signal for both PSD devices is achieved in
the same way it was in the M68008. The LDS
and UDS inputs (to U2 and U3 respectively)
are inverted by the PAD and drive the relevant E inputs. Table 8 gives the configuration
information relevant to both PSD devices.

Function

CDATA

0

8-bit data bus

CADDRDAT

0

Non-multiplexed address/data

CRRWR

1

Set RfW and E control inputs

CA19/CSI

1

Enable A 19 input'

CALE

X

"Don't care" not used

CRESET
COMB/SEP

0
0

Combined memory mode

CPAF2

X

"Don't care" Port A used for data

CPAF1

XXH

"Don't care" Port A used for data

CPBF

FFH

Port B used for I/O

CPCF

111 B

Configure CS8-CS 102

CPACOD

OOH

CMOS drivers

CPBCOD

OOH

CMOS drivers

CADDHLT

0

Transparent A 19

CSECURITY

0

No security

Active LOW RESET

1. A 19 input to the PSD3XX's is used to receive UDS and LDS from the M6aOOO microprocessor. These signals are
inverted by the PAD of each PSD3XX and fed back to the E input of each divice.
2. GS10 of each PSD3XX drives the inverted UDS and LDS back to E input. Port G is programmed to output GSa and
GS9. Additional byte-wide peripherals can be configured to the system and selected by these signals.

-------------------------------------rAr~AF~-----------------------------------i!!!'E!F~iE
2-273

•

t~l~
;;::;J I
fta
II.~~ .~ t
I-

I

~I
~

I

lIIi

I

I I!

vee
[A1-A18]
R1
470R
OTACK
U2
U1

fC[i('>. 15

~2~

~~~
IP1--> 25

.JEL-

I~

~~

BGACK

12
13

B~
24

~

~
~~ 28
~
~

CLK
VPA

IPLO
IPL1
IPL2

8GACK
BR
OTACK

BERR
FCO
FC1
FC2
BG
VMA
E

A1

A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23

~

I-4l!-~
~
~

r--W-

r-#-

5
00
01 I ;
02
03
I
04
05
06
66
07
08 ~
09
010
011 ~
012 ~
013 ~
014 ~
015 ~

19
20
6
7
8
9

HALT
RESET
AS
UOS
LOS
RMI

68000

U3

ADO/AO

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

AD1/A1
AD2/A2
AD3/A3
AD4/A4
ADS/AS

ADS/AS
AD7/A7

ADS/A8
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

AD9/A9
AD10/A1Q
AD111A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

Vee

l

c¥1
13
3

~

~
~ ~
~~
r--*-\

HALT

23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

E

A16/CS8
A17/CS9

R!WNPP
BHEIPSEN
AS
RESET

21
20
19
18
17
16
15
14

00
01
02
03
04
05
06
07

11~
10
~1

I-~---< ~~

~
I--+-<
--'=2. >
4
40

r-11-- --.§bL

~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~

~-?l+
--k-

'r-+
'~-L

A18/CS10~
A19/CSIIl

PSD3XX

ADO/AQ

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

AD1/A1

AD2IA2
AD3/A3
AD4/A4
ADS/AS

AD6IAB
AD7/A7

AD8IA8
AD9/A9
AD10/A10

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

E

R/W/VPP
BH'E/PSEN
AS
RESET

A16/CS8
A17/CS9

A19/CSI

UOS

[00-015]

I~~
Vee

<

R2
470R
BERR

08
09
010
011
012
013
014
015

---1-',..-..'

-

X1

X2
TIO
TI1
RES
TEST
DRQD

OROl
INTO
INT1
INT2ITAO
INT3ITM

U2
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
A010

AD11
AD12
AD13
AD14
AD15
A16/S3
A17/S4
A18/S5
A19/S6

ARDY

SRDY
NMI
HOLD

BHE/S7
ALE/asO
WR/QS1
RO/QSMD

MCSO
MCS1
MCS2
MeS3

pcso
PCS1
PCS2
PCS3
PCS4

PCS5/A1
PCS6IA2

1 I

~~

15
13
11
8
6
4
2
16
14
12
10
7
5
3
1

24
25
26
27
28
29
30

~
~
~
~
64
61
63
62

TOO

22

LCS

;~

I

3i ~cg~

~~~ ~~
so

LCS

~

53

~~~II~

CLKO

56

RESET

57

HLDA

51

22
2
1
13

,L

AD4/A4
ADS/AS
ADS/AS
AD7/A7

ADS/AS
AD9/A9
AD10/A10
A011/A11
AD12/A12
A013/A13
AD14/A14
AD1S/A15

RD
WR/VPP
BHE/PSEN
ALE
RESET

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
A16/CSB
A17/CS9

A18/CS10
A19/CSI

~
-l:'
19
18

P2

16

P4

~3~

~
P7

~

m
~
7
6
5
4

P11
P12
P13
P14
~

40
41
42

n.

GND

~

DT/R~
DEN 39
HLDA
LCK~

80186

31
32
33
35
36
37
38
39

ADO/AQ
AD1/A1
AD2/A2
AD3/A3

g~/R

L..--..<~r.K

PSD3XX

PSD3XX - Application Not. DI1

16-8it Address!
Data PSD3XX to
Intel 80196
Interlace
Table 10.
Intel 80196 to
PSD3XX Configuration for LED
Drivers

In Figure 17, the PS03XX is connected to an
Intel 80196 microcontroller. In many microcontroller applications it is necessary to
illuminate indicators (such as LEOs). Here,
the PS03XX· is used to drive LED indicator

Configuration

Bits

displays. High-efficiency LEDs can be
illuminated through the open drain outputs of
Port B. The configuration information in Table
10 indicates that Port B has open drain
drivers to sink LED illumination current.

Function

CDATA

1

CADDRDAT

1

16-bit data bus
Multiplexed address/data

CRRWR

0

Set RD and WR mode

CA19/CSI

X

"Don't care" A 19/CSI

CALE

0

Active HIGH ALE

CRESET

0

Active LOW RESET

COMB/SEP

0

Combined memory mode

CPAF2

0

I/O Port A

CPAF1

OOH

I/O Port A

CPBF

FFH

I/O Port B

CPCF

OOOB

Output A 16-A 18

CPACOD

OOH

CMOS drivers

CPBCOD

FFH

Open drain drivers

CADDHLT

X

"Don't care" (not used)

CSECURITY

0

No security

iFEE

•

4E~

----------------------------------~~I---------------------------------

2-277

~:::t:!S'::!l

....
g
"'III:

~

~arlC:i
~_;::

Si'~!;QCi
CD)oCC5,""

~

:::i~;:;::"-I

~~ .@!

,

!==:
=:Ii' CO)

i~
I

t

I-~

if
if

...

Sf
U1
X1

X2
Vee
NMI

READY
COE
BUSWIDTH
RESET

G NO

ACHO/PO.O
ACH1/PO.1
ACH2/PO.2
ACH3/PO.3
ACH4/PO.4
ACH5/PQ.5
ACH6/PO.6
ACH7/PO.?

qdliilo:
tillill
111111111
111111111

P2.0/TXD
P2.1/RXD
P2.2/EXINT
P2.3!T2CLK
P2.41T2RST
P2.5/PWM
P2.6IT2UP-DN
P2.7/T2CAPTURE

HSf.O
HSI.1
HSf.2/HSOA
HSf.3/HSO.S
VREF
12
2

Vee

ANGND
EA

U2
P3.0/ADQ
P3.1/AD1
P3.2/AD2
P3.3/A03
P3.4/AD4
P3.S/AOS
P3.6/AD6
P3.7/AD7
P4.0/ADa
P4.1/A09
P4.2/AD10
P4.3/AD11
P4.4/AD12
P4.5/A013
P4.6/AD14
P4.7/AD15

RO
WRUWR
WHE/BHE
ADV/ALE
rNST
CLKOUT
P1.0
P1.1

P1.2
P1.3
P1.4
P1.S
P1.6
P1.7
HSO.O
HSO.1
HSO.2
HSO.3

60
59
58
57
56
55
54
53

23
24
25
26
27
28
29
30

52
51
50
49
48
47
46
45

31
32
33
35
36
37
38
39
22
2
1
13
3

ADO/AO

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7

AD1/A1
AD2/A2

AD3/A3
AD4/A4
ADS/A5
AD6/A6
AD7/A7

ADa/AS
AD9/A9
AD10/A10
AD11/A11

PA3.2
PA3.3
PA3.4

PA3.S
PA3.6

PA3.?

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

AD12/A12
AD13/A13
AD14/A14
AD15/A1S

RD
WR
BHE/PSEN
ALE
RESET

PA3.0
PA3.1

A16/CS8
A17/CS9

A18/CS10
Ai9/eSI

VCC

PSD3XX
2
R1A
470R

3
R1B
470R

01

~

R1C
470R
1
4

1
5

1
6

4

02

~

R1D
470R
1
3

03

~

D4

~
VCC

80196
R1
10K

5

6
R1E
470R

T

GNO

C3
O.01JJF

R1F
470R

1
2

1
0
05

~

06

~

9
07

~

08

~

PSD3XX - ApplicatiDn NDte 011

Interfacing the
PSD3XX to 8·Bit
Microprocessors
180 and M6809
Applications

Table 11.
180B to PSD3XX
Interface

Figures 18 and 19 illustrate the PSD3XX used
with 8-bit microprocessors, such as the Z80B
and M6809B. Tables 11 and 12 reflect the
configuration of each design, respectively.
The mode of operation is 8-bit data bus with a
non-multiplexed address/data input. In the
case of the Z80B, CS8-CS 10 inputs are tied
to M1, MREO, and 10RO respectively. Since

Configuration

Bits

the PAD can be programmed to distinguish
between memory and I/O operations, the
Z80B system has access to an 8-bit data port
Port B. With the M6809B system, CS8 is
used to respond to the MRDY input of the
microprocessor and CS9 and CS1 0 are
available for external chip-select.

Function

CDATA

0

8-bit data bus
Non-multiplexed address/data

CADDRDAT

0

CRRWR

0

Set RD and WR mode

CA19/CSI

0

CSI input

CALE

X

"Don't care" (not used)

CRESET

0

Active LOW RESET

COMB/SEP

0

Combined memory mode

CPAF2

X

"Don't care" Port A used for data

CPAF1

XXH

"Don't care" Port A used for data

CPBF

FFH

I/O Port B

CPCF

OOOB

Configure A 16-A 18 as inputs

CPACOD

OOH

CMOS drivers

CPBCOD

OOH

CADDHLT

0

A 16-A 18 transparent'

CSECURITY

0

No security

CMOS drivers

1. A 16-A18 inputs are used as MI. MREO. and IORO inputs to the PAD from the Z80B output. Use the ALIAS
command in the support software.

Table 12.
M6889 to PSD3XX
Interface

Configuration

Bits

Function

CDATA

0

8-bit data bus

CADDRDAT

0

Non-multiplexed address/data

CRRWR

1

Set R/W and E mode

CA19/CSI

0

Enable CSI input

CALE

X

"Don't care" non-multiplexed mode

CRESET

0

Active LOW RESET

COMB/SEP

0

Combined memory mode

CPAF2

X

"Don't care" Port A used for data

CPAF1

XXH

"Don't care" Port A used for data

CPBF

FFH

Port B used for I/O

CPCF

111 B

CS8-CS 10 outputs

CPACOD

OOH

CMOS drivers

CPBCOD

OOH

CMOS drivers

CADDHLT

0

"Don't care"

CSECURITY

0

No security

-----------------------------------rAfAf~~---------------------------------5Fe!===
2-279

•

~

·iI~
caii=~Ci1

i~

CIi~

tif

~

'1:i .... ;:

~~~
is-~
:::I~

•

a

I"

ISi

...

U1

U2

~

27
19
20
22
21

~
q~·qll

II~::::

HALT

oc

WAIT

Iq~11I1

R1
10K

lall lill

18
2£

~16
~17
26

f

C1

BUSRQ
BUSACK

25
23

~6

M1
MREQ
lORa
WR
RO
REFSH

HALT
WAIT
.NT
NM.

~-

AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15

RESET
BUSRQ
BUSAK
CLK

G NO

Z80e

DO
01
02
03
04
05
06
07

30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5

23
24
25
26
27
28
29
30

~

~
33
35
36
37
38
39

14

~
~

v'TC

*

G~O

=B
~

~
v+
13

,L

ADO/AD
AD1/A1
AD2/A2
AD3JA3
AD4/A4

ADS/AS
AD6/A6
AD7/A7

ADS/AS
AD9/A9
AD1 O/A1 0
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A1S
RO
WR
BHE/PSEN
ALE
RESET

21
20
19
18
17
16
15
14

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PBO ~
'0:>
PB1 H l9' - : dP1
PB2
PB3
PB4
6
PB5
5
P6
PB6
4
P7
PB7

I

A16/CS8
A17/CS9
A18/CS10
A19/CSI

T:j

~~ >

>
>

40
41

n
42

M1
MREQ

lORa

GNO

PSD3XX

~I::!!

~i'l
c;.~ iii
s· ~ co

aM ....
=:a~

fn~

rl

~

GND

-

qqliii;::
q~IIQI

IIII~~

HLT
IRO

FIRQ
DMA

U1

X1

D

L---=-=_+-___-'3"'B'-j
RST

NMI

C1
20pF

EX2

37
2

RESET
NMI

40
3
4

HALT
IRQ

36
33

U2

~~

~

~

10

25

~g~~~~

A3

11

26

A4
AS
A6
A7
AS
A9
A10

12
13
14
15
16

27
28
29
30
31

AD

~I~~y

~~~

DMAii3

A13
A14
A15

PAD

~6

AD3/A3

PA3

18

PA4
PAS
PA6
PA7

17
16
15
14

ADO/AD

~~~

~~

~~

19

35

AD4/A4
ADS/AS
AD6/A6
AD7/A7
ADS/AS
AD9/A9
AD1 O/A1 0

20
21
22
23

36
37
38
39

AD13/A13
AD14/A14
AD15/A15

psa

PB1 f---'ll'-<~rr:>

~g~~~~~~

~~~

PB4
PBS
PBG

PB7
22

2"
Vee
T

1

l1"3
3

E
RIW/VPP
BHE/PSEN
AS
RESET

19

A16/CSB
A17/CS9

.-~'---=""-~
.-~'---=""-~

I-'''-C"E§v
t---;rr--::==------,

A18/CS10
A19/CSI

GND

PSD3XX

i~

6809B

I

~

ir
~

1&

IS2

~

-

•

...

PSD3XX - Application Note 011

PS03XX
Interface to the
Intel 80286

Table 13.
Intel 80286 to
PS03XX Interface

Figure 20 provides a schematic of the
PSD3XX interface to an 80286. The device is
configured for a 16-bit data bus in the nonmultiplexed mode. Ports A and B are converted automatically for use as a bi-directional
data path into the PSD3XX. (This was also

Configuration

Bits

the case for the M68000 microprocessor). To
eliminate (or lessen) glue logic, CS1 and CS2
are generated from the internal PAD. This is
programmed as an address decoder. Table
13 provides configuration information relevant
to this system design.

Function

CDATA

1

16-bit data bus

CADDRDAT

0

Non-multiplexed address/data
Set RD and WR control inputs

CRRWR

0

CA19/CSI

1

Enable A 19 input

CALE

X

"Don't care" non-multiplexed mode

CRESH

1

Active HIGH RESET

COMB/SEP

0

Combined memory mode

CPAF2

X

"Don't care" Port A used for data
"Don't care" Port A used for data

CPAF1

XXH

CPBF

XXH

"Don't care" Port B used for data

CPCF

011B

A16 input; CS9 and CS10 outputs

CPACOD

OOH

CMOS drivers

CPBCOD

OOH

CMOS drivers

CADDHLT

0

Transparent A 16-A 19 input

CSECURITY

0

No security

-----------------------------------'jfjr~:----------------------------------

2-282

== ==

'E!!1:e

-....

:t.~-~

~

M:::a.:::::,
Cit--~

'eli ~

C;' ~ ~ Ci1

~:..c~!:i

S'

i
U1

CJ

~ci~

X1

U2

READY
CLK
RESET

X2
PCLK

4
10
12

SO
S1

MiR)"

13

READY

EFI

CEN/AEN

14
7
6

SYEN
SO
S1

CENL
CMDLY
MB

MWTC

OT/R~
DEN
ALE
MCE

16
5

82288

RES
FIG
~"~I

CLK

V CC15

AYEN
SRDY

I

INTA
IORC

lowe

MRDe

ARDY

Vee

GNO
U4

02284

~------

U3

READY
CLK
RESET

IIIIIUI
1'1"'''''
111111111
111II
11111 nli

SO
S1

T

GNO

LOCK
NMI
INTR

67
68
59
57

M/i'O'""
LOCK
NMI
lNTR
HOLD
HLDA

ERROR
BUSY
PEREQ
PEACK
CODJINTA

cAP)

52

I

CAP

AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23

34
33
32
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
8
7

23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39

ADO/AD
AD1/A1
AD2JA2

AD3/A3
AD4/A4
ADS/AS
AD6/A6
AD7/A7
ADS/AS
AD9/A9

AD10/A10
AD11/A11
A012/A12
AD13/A13
AD14/A14
AD1S/A15

AD

DO
01
02
03
04
05
06
07
08
09
D10
011
012
013
014
015

I\,)

36
38
40
42
44
46
48
50
37
39
41
43
45
47
49
51

PAO
PA1
PA2
PA3
PM
PA5
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
A16/CS8
A17/CS9

BHE/PSEN
ALE
RESET

A18/CS10
A19/CSI

21
20
19
18
17
16
15
14
11
10
9
8
7
6
5
4
40
41
42
43

PSD3XX

BHE

~

;0-

~

CS1

a~~
I

:a:.

CS2

!1'>'

i'"

~
Ii'

""......

80286

11

PSD3XX - Application Note Ott

External
Peripherals to the
PS03XX/M68HC11
Configuration

Table 14.
M68HC11/PS03XX
to External
Peripheral
M68230
Interface

The configuration in Figure 21 illustrates how
~he user can feed address outputs from the
Internal latch to Port A. Addresses AO-A?,
derived from a multiplexed address/data bus,
can go directly to an additional peripheral
without the need for an additional octal latch
such as the ?4HC3?3 or ?4HC5?3. Port A
CE.,' be used for address outputs AO-A? while
PBO-PB? can be used as chip-selects. Lines
AO-A4 of the PSD3XX drive the RS1-RS5
register select inputs of the M68230. For the
M68HC11, the eight bits of address and data
come from its PC port PCO-PC? (ADO-AD?)
and are latched by the AS input. Configured
in this mode, the PSD3XX can address and
map additional peripheral chips. Port A of the
PSD3XX conveys the internally latched

Configuration

Bits

address outputs AO-A? to the output and can
be used to address registers in the peripheral
chips while Port B outputs can place individual peripherals at peripheral or memorymapped boundaries. Thus, a number of
additional chips can be selected through Port
B. This effectively can increase the port
density of the system design. The general 110
capability can then be extended to extra
ports, timers, UARTs, serial communications
channels, keyboard interface devices, CRT
controllers, etc. without the need for additional
glue logic. Table 14 highlights the configuration information programmed into the PSD3XX
when configuring the M68HC11 to a M68230
peripheral.

Function

CDATA

0

8-bit data bus

CADDRDAT

1

Multiplexed address/data

CRRWR

1

Set R/W and E mode

CA19/CSI

0

Set power-down mode

CALE

0

Active HIGH AS

CRESET

0

Active LOW RESET

COMB/SEP

0

Combined memory mode

CPAF2

0

CPAF1

FFH

Port A set for address
Port B set for chip-select

Port A = address AO-A?

CPBF

OOH

CPCF

111B

Port C set for chip-select

CPACOD

OOH

CMOS buffers
CMOS buffers

CPBCOD

OOH

CADDHLT

X

"Don't care"

CSECURITY

0

No security

___________________________________ f~E=€----------------------------------2-284

~_!iIIo~

~ c::i ~ca'

1:1:1§
n I C"'5 CI

..;S' ~~"-'~
~ "-'
i

~

2

~

C1

20pF

XTAL
XTAL

PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC7

POD
P01
P02
P03
P04
P05

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PEO
PE1
PE2
PE3
PE4
PE5
PE6
PE7

qilliii;::
III~I

1IIIllin
111_ 1111

RES~'::

16
17
18
19
20
21
22
23

31
32
33
35
36
37
38
39

11

V$C

6
4
17

XIRO*
IRQ -=--'1

~gg~

~VRH
51
VRL

:JI

12
13
14
15

23
24
25
26
27
28
29
30

5

E

R/W

PAD
PA1
PA2
PA3
PA4
PA5
PA6
PA7

Vee

8
9
10

--+

I II

GNO

ADO/AD

PAD
PA1
PA2
PA3
PA4
PA5
PA6
PA7

AD1/A1
AD2/A2
AD3/A3
AD4/A4

ADS/AS
AD6/AS
AD7/A7

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

ADS/AS
AD9/A9
AD10(A10
A011/A11
A012/A12
AD13/A13
AD14/A14
AD15/A15

E

RIWIVPP
BHE/PSEN
AS
RESET

A16/CS8
A17/CS9
A18/GS1Q
Ai9/eSl

21

20
19

is
17

25
26
27
28
29

AD
A1
A2
A3
A4

16

15
14
11

44
45
CSO

V

46
47
48
1
2
3

10

9

8
7'

"6
"5
"4

43
41

40

41

39

42

RIW
CS
RESET

GNO

PAD
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PCO
PC1

PC2ITIN

PC3ITOUT '---'-"--~-","O,
PG4/DMAREQ
pes!p I RQ '---'-"--~-",""
PCS/PIACK
PC71TIACK

PSD3XX

""'"'--==/

H2~

Vee

Vee

H3
H4
DTAGK

Vee
R1
4.7K

'"F
r--

68230

J~
I

GNO

t
I

U4

Vee
2

~

00
01
02
03
04
05
06
07

43

C3

~

RS1
RS2
RS3
RS4
RS5

H1

II I

68HCll

22
2
1
13
3

U3

U2
,---

~
VDD

~t

RESET

C;'
~

~
if

GNO

MC34064

...!:2

11

psoaxx - Application Note 011

Additional
External SRAM

Table 15.
M68HC11/PSD3XX
Configured to
Address
Additional SRAM

Figure 22 illustrates how additional SRAMs
can be configured into a system. This
PSD3XX configuration is not limited to external peripheral expansion; it can also be used
to add additional memory without the need for
external glue logic. With an 8-bit addressl
data multiplexed scheme, the higher-order
addresses (A8-A 15) are non-multiplexed.
These address lines are fed directly to the

Configuration

Bits

external SRAM from the microcontroller and
do not need to go through the PSD3XX
These lines can drive the RAM chip directly.
Thus the M68HC11 system, which is highly
memory-intensive and requires more RAM
than the microcontrolier and PSD3XX can
supply, can take advantage of the configuration shown in Figure 23 which is detailed in
Table 15.

Function

CDATA

1

8-bit data bus

CADDRDAT

0

Multiplexed address/data

CRRWR

1

Set R/W and E mode

CA19/CSI

1

Set power-down mode

CALE

0

Active HIGH AS

CRESET

0

Active LOW RESET

COMB/SEP

0

Combined memory mode

CPAF2

0

Port A = address AO-A7

CPAF1

FFH

Port A set for address

CPBF

OOH

Port B set for chip-select

CPCF

111B

Port C set for chip-select

CPACOD

OOH

CMOS buffers

CPBCOD

OOH

CADDHLT

X

Latched A 16-A 19 "don't care"

CSECURITY

0

No security

CMOS buffers

-----------------------------------r~~=~----------------------------------

2-286

~=-=

.-.~
~
a CI'i
'!!IiI.:::.
't5
.....
__

;:::~I§

n :IiIIi; C"5

lID

I:I=~
I·~

"-I
~

G

't

T

X1

IP.1HZ

~
P01

PD2

7
8
20

~
22

~
PE1

:~

PE3
PE4
PES

44
46
48

PE~

~~~

50

~
~ 33
PA2

~~

~
">-fA~ 29
PAS

28

~
~
52

r:::§t:

'e

PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC7

XTAL

~
P05
25

'hQIIIUII
••

U2

XTAL

<

1:::

20pF

GNO
U1

R4
1K

POO
P01
P02
P03
P04
P05

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PEO
PE1
PE2
PE3
PE4
PE5
PE6
PE7

23
24
25
26
27
28
29
30

16

31
32
33
35
36
37
38
39

17
18
19
20
21
22
23

5
E

RJiiii

PAD
PA1
PA2
PA3
PA4
PA5
PA6
PA7

AS
RESET
XIRQ
IRQ

Vee

6
4
17
18

1 '9

~

2
MOOB
~,
MODA

22
2
1
13
3

U3

ADO/AD

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

A01/A1
A02lA2
AD3/A3
AD4/A4

ADS/AS
AD6/A6
A07/A7

ADS/AS
ADS/A9

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

AD10/A1Q
A011/A11
AD12!A12
AD13/A13
AD14/A14
AD15/A15
E
RlWNPP
BHEIPSEN
AS
RESET

A16/CSB
A17/CS9

A18/CS10
A19/CSI

PSD3XX

I

21
20
19
18
17
16
15
14

AD
A1
A2
A3
A4
A5
A6
A7

11

CSO

's"

A8
A9
A10
A11
A12

CS11

K-I
H-t---4--r--*-

Vee

68HC11

G~O

C3
1 F

~O
Vee

-~

~
27
22

-

~
~
43

Ilo

R1
4.7K

20

~
27
22

~

11
12
13
15
16
17
18
19

CS1
CS2
WE
OE

AD
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12

00
01
02
03
04
05
06
07

11
12
13
15
16
17
18
19

rJ

CS1
CS2
WE
QE

6164

!

~

I

V OD
1

I

GNO

GNO

~

00
01
02
03
04
05
06
07

U4

1 1
R1
4.7K

AD
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

6164
10
9
8
7
6
5
4
3
25
24
21
23
2

Vee

U4

RESET

?-

~

R1
47K

10
9
8
7
6
5
4
3
25
24
21
23
2
20

r--+-

r---L

VRH
VRL

t----

j

8
9
10
11
12
13
14
15

I

t

I!i!l

I!i

MC34064

~

""l

•

....

PSD3XX - Application Note 011

Additional
External SRAM
(Cont.)

Table 16.
SCB0C451/
PS03XX
Configured to
Address
Additional SRAM

Figure 23 illustrates, and Table 16 details, a
similar system using the Signetics
SC80C451. This microcontroller has many
ports and some SRAM but requires off-chip
EPROM to store programmed instructions.
This device is similar to the 8051/31 family
which uses the active LOW PSEN signal to
differentiate between executable code and

Configuration

Bils

data. Since it is a multiplexed 8-bit machine,
it can use the on-chip latches. In highly RAMintensive applications, an additional two 8K x
8 SRAM chips can be included and selected
through Port B. If additional SRAM chips are
not needed, Ports A and B can recreate Ports
o and 2 which are lost in addressing external
memory.

Function

CDATA

1

8-bit data bus

CADDRDAT

0

Multiplexed address/data

CRRWR

0

Set RD and WR mode

CA19/CSI

0

Set power-down mode

CALE

0

Active HIGH ALE

CRESET

0

Active LOW RESET

COMB/SEP

1

Separate data/program memory

CPAF2

0

Port A = address AO-A?

CPAF1

FFH

Port A set for address

CPBF

OOH

Port B set for chip-select

CPCF

111 B

Port C set for chip-select

CPACOD

OOH

CMOS buffers

CPBCOD

OOH

CMOS buffers

CADDHLT

0

"Don't care" (not used)

CSECURITY

0

No security

___________________________________ ~~SF~----------------------------------2-288

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PS.5
PS.4
PS.3
P6.2
PS.1
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23
24
25
26
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62
61
60
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P3.41AD4

NMI

P3.5/AD5

READY

P3.6/AD6
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CDE
BUSWIDTH
RESET

ACHO/PO.O
ACH1/PO.1
ACH2/PO.2
ACH3JPQ.3
ACH4IPO.4
ACH5IPO.5
ACH6/PO.S
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P4.1/AD9
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RD

WRlJWR
P2.0fTXD
P2.1/RXD
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P2.7!T2CAPTURE
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HSI.2/HSO.4
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ANGND
EA

80196

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INST
CLKOUT
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
HSO.O
HSO.1
HSO.2
HSO.3

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
61
40
41
62

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59
58
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ADO
AD1
AD2
AD3
AD4
AD5
ADS
AD7

AS
A9
A10
A11
A12
A13
A14
A15

23
24
25
26
27
28
29
30

ADS/AS
ADS/AS
AD7/A7

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7

AD8JAB
AD9/A9
ADiD/AiD
AD11/A11
AD12/A12
AD13/A13
AD141A14
AD1S/A15

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

ADO/AD
AD1/A1
AD2JA2
AD3/A3
AD4/A4

31
32
33
35
36
37
38
39
22
2
1
13

RD
WR
BHE/PSEN
ALE
RESET

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17
16
15
14
11

3
4
7
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13
14
17
18

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01
02
03
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06
07

00
01
02
03
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06
07

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2
5
6
9
12
15
16
19

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A1
A2
A3
A4

AS
A6
A7

AS

CS1

11

A9
A10

DC

~
=P r:E~
=+=
::±:

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RD
WR

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1\:1

~

....

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1

GND

C1
10l-lF

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;r-1-!L
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01
02
03
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FROM HOST SYSTEM

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f

Is

-

PSD3XX - Application Note 011

_________________________________________

2-292

fAFAf~=

~~SF~----------------------------------------

Programmable Peripheral

Wli

Application Note 011
Software Support

Chapter 3
The support software for both PSD3XX
family and MAP168 memory-mapped
peripheral devices is designed to run on
IBM PC XT/AT or 1'00% compatible
systems. It is menu-driven and very userfriendly. In many cases it has the capability
of preventing the user from creating invalid
configurations. For example, in a nonmultiplexed system with a 16-bit data bus,
Ports A and B are used for data 1/0. The
software recognizes this and prevents the

user from inadvertently programming Ports
A and B as regular ports.
When running in the IBM PC environment,
the PSD development software creates the
menu shown in Figure 25. Initially, the
designer selects the part type with the user
key F8 or moves the screen cursor to
PARTNAME. In the example shown, the
selection for the part type is PSD301.

Figure 25.
MAPLE Main

Menu
F1

DOS

FZ

EXIT

F3
Fi

MAPPRO
PARTLIST
LOAD
SAVE
COMPILE

F5

F6
F7

II;.mili;wi"
~

Partnaroe

: PSD301

Specify PARTNAME to he configured and press .
Cursor - Up.t Down:!

Left.~

C:\WSI
240226

ALIASES Menu

The ALIASES selection lets the user individually
define the port pins with user-relevant names.
The circuit diagram shown in Figure 13 uses
an M68008 processor, with BERR and

DTACK signals coming from the PAD, as well
as the remaining CSO, CS5 Chip-select
outputs.

_____________________________________ ____________________________________
f.-~~

2-294

~II

PSD3XX - Application Note 011

Figule27.
CONFIGURATION
Menu

Figure 27 gives the CONFIGURATION menu.
In this case, the PSD301 has been configured
for the system shown in Figure 10: interfacing
to an 80C31 ; the 8-bit data/address bus is
multiplexed. The chip-select input is chosen
over the A 19 input. The RESET and ALE
polarity is set as active HIGH with RD and
WR control inputs enabled. The inputs
A 16-A 19 are transparent and separate
strobes are enabled for SRAM and EPROM.

This feature activates the PSEN input. In this
configuration it is possible for the SRAM and
EPROM to share the same address space.
After the device is configured, Ports A, 8, and
C can be set up. If the main menu is invoked
by selecting F1 (Figure 28), Port C can be
selected as shown in Figure 26. Here, the
individual selection of CS/Ai configures the
three pins as outputs.

CONF I GURAT ION
Address~Data Mode (Multiplexed: MX. Non-Multiplexed: NM)
Data Bus Width (8~16 bits)
CSI (Power-Down~Chip Enable) or A19
Reset Polarity (Active Low: LO. Active High: HI)
ALE Polarity (Active Low: LO. Active High: HI)
WR and RD (WRD) or R~W and E (RWE)?
A19-A16 Transparent or Latched by ALE (Trans: T. Latched: L)
Using different READ Strobes for SRAM and EPROM ? (Y~N)
Separate SRAM and EPROM address spaces? (VN)

If SRAM and EPROM share the

FI-Return to Main Menu

sa~e

MX
8

•
CSI
HI
HI
WRD
T
Y

Address space. press SPACEBAR.

FZ-Te~porary

exit to Dos Cursor- Up:t Down:!

240227

!i'==~J§

-------------------------------------~~~~------------------------------------

2-295

I

PSIJ3XX - AppllcatkJn 110", mt

Figure 28.
PortC
Configuration
Menu

PORT C

--

.,

CS,IAi

PI"

PCl
PCZ

CS'J
CS10

-

-

E: figure

-

-

--

~~

-- ------- --- - -- - --=:]

- - -

-~---

- -

-------------

all the 3 pins before going to any CS Definition.

---==---------=-'-----=------=-----=-=---=-=--==---=---=----

If you want to configure PCO as A16. press SPACEBAR.
F1 - Return to Main Menu
F3 - Goto CS Definition

FZ - TeMporary exit to Dos
Cursor
Up:t Down.!

C:\WSI
240228

Figure 29.
PortA
Configuration
Menu, Part 1.

Figure 29 shows the configuration of Port A.
This could be applied to the example shown
in Figure 21 which shows the PSD301 interfacing to an M68230. Port A passes the.

PSD301 's internally latched address lines
AO-A4 directly to the M68230. PA5-PA7 are
configured as port outputs and can be used
as general I/0s.

PORT A (ADDRESS/IO)

[[- ----

- - - - - - - - - -

I~~s

-~~~9

figure each pin
conf igured as
~MdllY have CMOS

- - =------==-===-----=------==-

To configure

PAO as 1,10. press SPACEBAR.

FI-Return to PORT A

Cursor -

Ai,lIO r.MOS,IOD
PI"
CMOS
~
PAl
CMOS
Ai
PAZ
AZ
CMOS
PA3
A3
CMOS
PM
Ai
CMOS
PAS
IO
CMOS
PA6
CMOS
IO
PA?
IO
CMOS

0'

l~:t

Down !

Left:~

Right.~

C:\WSI
240229

____________________________________
2-296

____________________________________

f·Ar~E

fN#ll

PSD3XX - Application Note 011

Figure 30.
PortA
Configuration
Menu, Part 2.

designer wants to program the device as
shown in Figure 24.

Port A can be programmed to be either
address I/O or track mode, as illustrated in
Figure 30. Track mode is selected if the

PORT A

rev Config: ..

ADDRESS/IO
TRACI< MODE

•

If you want to configure PORT A pins indiuidually as Address
or I/O bits, press .

Fl - Return to Main Menu
Cursor - Up:t Down:!

FZ - Temporary exit to Dos.

240230

Figure 31.
PortB
Configuration
Menu

Figure 31 gives the configuration of Port B.
This is similar to the configuration pattern for
the M68008 shown in Figure 13. Here, CS6

and CS7 have been programmed as opendrain outputs connected to the microprocessor's DTACK and BERR, respectively.

PORT H
PIt!
PHa
PB1
PBZ
PB3
PB1
PB5
PBf>

CS.dO
csa
CS1
CSZ
CS3
CS1
CS5
CSf>
CS?

CMOS/OD
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
OD

-- -If you haue CMOS output

Fl - Return to Main Menu
F3 - Goto CS Definition

for

PB? press SPACEBAR.

FZ - Temporary exit to Dos
Cursor - Up:t Down:! Left:<- Right: ..

240231

-------------------------------------~~~-----------------------------------2-297

I'SIJ3XX - Application 110m 011

Figure 32.
ADDRESS MAP
Menu

Figure 32 shows the ADDRESS MAP menu.
The designer can enter a binary code for the
address range of the various select lines;
ESO-ES7, RSO, and CSP, being the EPROM,
SRAM, and PERIPHERAL assignments,

respectively. A space for individual hexadecimal files is reserved under the FILENAME
section. The Intel MCS files are listed as they
would be compiled and programmed into the
device.

ADDRESS MAP

I

FILE NAME

Flil in Al'J~All (Binary) or SEGMT START (flex); and FILHSTART, STOP)
dnd fiLE NAME. Use SPACEBAR Lu erdse dny field ualue.
F!
Retllrn 10 MaIn Menu
FZ
TFmporary exit to DOS
F3 - Goto Help
Cursor
Up:t Down:' Left:. Right:~
N - Non editable bit.

240232

After configuration has been established, the
user can return to the main menu and select
the COMPILE option. The configuration is
compiled and converted to a JEDEC array
program map.
When successfully finished, the designer can
select the MAPPRO option (see Figure 25),
and when a WSI MAGICPROTM programmer

• •,6SR

is available in the PC system, finalize the
design by programming a PSD301.
The Address Map for Port B can be configured as shown in Figure 33. Per Figure 31,
depress function key F3 to invoke the chip
select definition. The entries can be made for
logic HIGH, LOW, or "don't care" conditions.

-------------------------------------~~jr------------------------------------

2-290

I'SD3XX - Application /10", 011

Figure 33.
PortB

Configuration
Menu with
AddressMap

PIli
',I

PBl
PB2
PB3
PB1
PB5
PB&
PB?

--

CS/IO ~HOS/OD
CHOS
CSl
CIIOS
CS2
CHOS
CS3
CIIOS
CS1
CIIOS
CS5
CHOS
CS&
CIIOS
CS?
CHUS

PORT B

"'ii.

.;,,4,8 ' ••.lIIU .....

AlB A17 Al& A15 Al1 A13 A12 ~11 ALE RD
a a a 1 1 1 1 1 X X

WR

a

CS definition is the MOR of the product terns(rows). Enter 1 to select
Actiue High signal, a to select Actiue Low signal, X to nean 'don't
care', SPACEBAR to erase. Enter ualues in colunns releuant to your
application: other blank colunns will be treated as 'don't care's.
Fl - Return tu PORT B

Cursor

Up·t

Down:~ Left:~ Rlght:~

240231

Summary

The PSD3XX microcontroller peripheral with
memory, supported with low-cost software
and programming capability form WSI,
greatly simplifies the overall design of
microcontroller based systems. The key
advantage is the extensive condensing of
glue logic, latches, ports, and discrete
memory elements into a single-device,

enhancing the reliability of the final product.
Applications for the device extend to practically any area that uses microcontrollers or
microprocessors, from modems and vending
machines to disc controllers and high-end
processor systems.

-------------------------------------fJrj;jF~------------------------------------

...._-

2-299

~2_~~~O~-----------------------~Jr;---------------------------

Programmable Peripheral
Application Note 013
The I'SD301 Streamlines a Microcontroller-based
Smart Transmitter Design
By Seyamak Keyghobad - Bailey Controls,
and Karen Spesard - WSI

Abstract

A smart transmitter design is described
which takes advantage of the integration
capabilities and flexibility of WSI's
PSD301 microcontroller peripheral. The
following discussion illustrates how the

PSD301, in effect, was responsible for
eliminating an extra 2.5 inch diameter
board in a system where real estate is at
a premium by reducing the number of
components from 12 down to 5.

Introduction

Designers of systems using microcontrollers and microprocessors often
face the problem of how to integrate
peripheral logic and memory functions
into their designs without using many
discrete chips and large areas of board
space. For example, when external
EPROM and SRAMs are configured into
systems with ROM less microcontrollers,
general I/O ports are typically sacrificed
for address, data inpuVoutput, and control
functions. When these I/O ports are
depleted, the total chip count of the
system is increased by requiring the use
of additional external ports and steering
logic. Designers, who have limited board
space, such as found in the disk drive,

modem, cellular phone, industrial/process
control, and automotive industries, find
this a critical problem.

The Design
Application

The smart transmitter, shown in Figure 1,
was developed by Bailey Controls, a
manufacturer of process control
instruments, to support a popular field
bus protocol. One of its functions in this
sensor application is to measure
pressure, differential pressure, and flow
rates through pipes in industrial
environments such as chemical plants, oil
refineries, or utility plants. A host system
monitors the transmitter via a process
control network.
The completed transmitter design
consists of three main boards. The first
board includes the power supply and
communications hardware to provide
power to the rest of the system and feedback to the process control network. It
consists of communications transformers
and line drivers/receivers.

The PSD301 programmable peripheral
device from WSI solves this problem by
integrating all SRAM, EPROM, programmable decoding and configurable I/O port
functions needed in 8 or 16-bit microcontroller designs into a single-chip
user-configurable solution. This is
illustrated in the following industrial
control application where the PSD301
eliminates seven chips and saves the
designer from needing another board in
the system.

The second board is the digital microcontroller board and contains the 68HC11
microcontroller as well as the PSD301
programmable peripheral, a PLD, UART,
and LCD display. Its function is to
communicate and receive the inputs from
the third board, process the data, and
display the appropriate results to the LCD.
The third board or input board is mostly
analog. It receives inputs from string gauge
sensors which use a bridge circuit for
measuring pressure using a diaphragm.
The input board then converts the signals
so the microcontroller can read them.

2-301

~

I

PSII3IJt - Application IIoIe

Of'

Figure 1.
"Smart"
Transmitter from
Bailey Controls

.. Pressure/Flow

Design
Considerations

The smart transmitter system is rather
small. Its case is only 2.5 inches in
diameter and thus requires boards that
fit this small form factor as shown in
Figure 2. Not surprisingly, the major
design consideration during"development
was board space. This was especially
true for the microcontroller/digital board
where real estate is at a very high
premium.

meant extending the number of boards
used beyond one unless a way could be
found to integrate some of these
elements.

One of the problems was that there were
already requirements for the 68HC11
microcontroller, a 256K EPROM, 16K
SRAM, a PLD, TTL logic, a UART, and
an LCD display on the digital board. This

To meet these objectives, Bailey Controls
looked to WSI's user-configurable
peripheral, the PSD301, for its integration
capabilities, its flexibility, and its low
power of less than 35 mA active and
90 J.IA typical powerdown.

Other important considerations, or goals
actually, for the design were to reduce
power consumption to less than 2.4W,
improve reliability, lower design costs,
and shorten the time-to-market.

Figure 2.
The Bailey Smart
Transmitter Board
Using the WSI

PSD3D1.

-------------------------~Jr;~"------------------------

2-302

PS0301-Application Note 013

P50301
Architecture

The PSD301 is a field programmable device
that has the ability to interface to virtually
any 8- or 16-bit microcontroller without the
need for external glue logic. This is possible
because the PSD301 combines the
elements necessary for a complete
microcontroller peripheral solution, such as
user-configurable logic, I/O ports, EPROM
and SRAM, all into one device. The
functional block diagram of the PSD301 in
Figure 3 shows its main sections: the
internal latches and control signals, the
programmable address decoder (PAD), the
memory, and the I/O ports.

Figure 3.

•

A16 - AlB

r-

P50301
Architecture

The control signals and internal latches in
the PSD301 were designed so interfacing
to any microcontroller would be easy and
require no glue logic. For instance, the
PSD301 can interface directly to all
multiplexed (and non-multiplexed) 8- and
16-bit microcontroller address/data buses
because it has two on-chip 8-bit address
latches. This means no external latches
are required to interface to multiplexed
buses. It also has programmable polarity
on the control inputs ALE/AS and RESET,
so they can be configured to be active high
or active low.

All-A1S

L
A
T
C
H

ADB-AD1S

~
A19
CSI

'-L
A
T
C
H

I·

~

i

-

WR
RESET

13 P.T.

- --

I-

27 P.T.

CS10

r-

~~~

CSOCS7

'16iB
~

~

--

li~

~

32K BIT
BLOCK

'--

r---

r ~Br-

PBO-

~

CSIOPORT

rDO-D7

~

~

PC2

PROG.
PORT
EXP.

PORT

DB-DIS

I.[>~

 i -

'---

-

pco-

,---

~
ESI
~O~

~

~
CSa-

PORT
C

EPROM
2S6K BIT

ES7
ES6
ES5
ES4
ES3

'---

L...-.

r----

RD

WR
RESET

PROG.
PORT
EXP.

!LOGIC IN

PAD B

ALE/AS

RD

~

-r

PAD A

ALE/AS

.-

ADIl-AD7

1

CSIOPORT
A19
CSI

,-'-SRAM
16K BIT
TRACK MODE
SELECTS

AIl-A7
ADO-AD7/DIl-D7

PROG.
PORT
EXP.

r--PORT
A

PAO-

~

ALE/AS
-

RD/E

PROG. CHIP
CONFIGURATION

i

WR/R/W
BHE/PSEN
RESET

PROG.
CONTROL
SIGNALS

'-----

I

XB, XI6
MUX or NON-MUX BUSSES
SECURITY MODE

AI9/CSI

---------------------------------------~~~Ar--------------------------------------

2-303

PSJJ3D1-ApplicatiOR /lDte 013

PSD301
Architecture
(Cont.)

The other control signals, RDIE, and
WRiRIW, are also programmable as IRD
and IWR or E and RiW, enabling direct
interface to all Motorola- and Intel-type
controllers.
The programmable array decoder (PAD) is
an EPROM-based reprogrammable logic
"fuse" array with 11 dedicated inputs, up to
4 general-purpose inputs, and up to 24
outputs. The PAD is used to configure the a
EPROM blocks on 2K word boundaries and
the SRAM on a 1K word boundary
anywhere within a 1 Meg address space. It
is also used to generate a base address for
mapping ports A and 8, as well as to
provide mapping for the track mode. The
PAD, like a traditional PLD, can generate up
to eight sum-of-product outputs to extend
address decoding to external peripherals or
to implement logic replacement on a board.
Memory in the PSD301 is provided by
EPROM for program and table storage and
SRAM for scratch pad storage and
development and diagnostic testing. The
EPROM density is 256K bits and the SRAM
density is 16K bits. 80th can be operated in
either word-wide or byte-wide fashion,
which translates to a 32K x a or 16K x 16
EPROM configuration and a 2K x a or 1K x
16 SRAM configuration. As described
above, the EPROM is divided into a blocks
(of 4K x a or 2K x 16), with each block
typically on a 2K boundary locatable within
a 1 Meg address space.
There are 3 ports on the PSD301 that are
highly flexible and programmable: Ports A,
8 and C, illustrated in Figure 4. Port A is an

ligure4.
PSD3D1
Multiplexed
Address/Data
Configuration

A8 - A15,

AD8 - AD15

ALE

a-bit port that can be configured in a variety
of ways. For example, if the PSD301 is in
the multiplexed mode, port A can be
configured pin-by-pin to be an 1/0 or a lower
order latched address. Alternatively, port A
can be configured in the track mode to
transfer a bits of address and data inputs
through port A. This enables the microcontroller to share external resources, such
as additional SRAM, with other controllers.
In either case, each port A output can be
configured to be CMOS or open drain. If the
PSD301 is in the non-multiplexed mode,
port A becomes the lower order data for the
chip.
Port 8 is another flexible a-bit port. In the
multiplexed mode or a-bit non-multiplexed
mode, each pin on port 8 can be
customized to function as an 1/0 or a
chip-select output. The chip-select signals
are determined by the PAD programming
and are used for general logic replacement
or to extend the address decoding to
external peripherals. Each pin in this mode
can also be programmed to have a CMOS
or an open drain output. In the 16-bit
non-multiplexed mode, port 8 becomes the
higher order data for the chip.
Port C is the third port which is available on
the PSD301. It is a 3-bit port that can be
programmed on a pin-by-pin basis to be
chip-select outputs andlor general-purpose
logic inputs or addresses to the PAD.
Some uses for port C might be to extend the
address range to 1 Meg, or to create finer
address decoding resolution down to 256.
Or, one might use port C to help create a
simple state machine.

PORT A

PORT B

ADO -AD7

YO or AO -A7 or ADO - AD7

110 or CSO - CS7

PORT C

----------------------------------~.,.Jr---------------------------------

2-304

1'SD3D1-AppllcatIDn Note 013

Simple
Interfaces
to the PSD301.

One of the overwhelming advantages of the
PSD301 is its ability to interface to virtually
any microcontroller without any glue logic,
while providing additional I/O ports and
memory. This is accomplished by
configuring or programming the part to
function in an operational mode geared for
a specific application.
For instance, there are 45 configuration
bits on the PSD301 that have to be
programmed in addition to the EPROM
prior to usage. These configuration bits are
determined during development by the
designer using the WSI MAPLE software
package. After the configuration bits are
determined, the EPROM code and
configuration data can be merged during
compilation and the part subsequently
programmed.

configuration bits discussed above. To
illustrate how this works, two examples are
provided.
The first example is with the 80C196
microcontroller. This 16-bit microcontroller
from Intel interfaces directly to the PSD301,
providing it with additional off-chip program
store EPROM and data store SRAM, as
well as the flexibility that comes with three
additional I/O ports. As illustrated in Figure
5, the 80C196's 16-bit multiplexed address/
data bus and control signals (RD,WR,
BHE, ALE, RESET) connect directly to the
PSD301. This is achieved with the PSD301
in the following configuration:

o
o
o
o
o
o
o

Interfacing the PSD301 to different
microcontrollers is accommodated by the

Figure 5.
General
Schematic
Diaglamof
theBOC196
andPSD301.

, ~Cl

80196

30pF
Fl

---<

,

11
=Xl

'J

r'f2
30pF

12

--fa
14

G ND

84
16

~

6

~
~
7
~4

~
~O

~
PO.6 >-----t
~

~

~

~
~

~

~
P2.6 >-------ii
P2.7

>---=

~

~
HS2i4

Xl

8MHz

VCC

1

16-bit data bus
Multiplexed address/data
RD and WR mode set
Active HIGH ALE
Active LOW RESET
A16-A18 configured as output
Combined memory mode

27

~

13
12
2

X2
NMI
READY
CDE

BUSWIDTH

PSD301
P3.OIADO
P3.1/AD1·
P3.2/AD2
P3.3/ADS
P3.41AD4
P3.51AD5
P3.6/AD6
P3.7/AD7

RESET
ACHOIPO.O
ACHlIPO.l
ACH2/PO.2
ACH3IPO.3
ACH4IPO.4
ACH5JPO.5
ACH6IPO.6
ACH7/PO.7
P2.OITXD
P2.1/RXD
P2.2/EXINT
P2.31T2CLK
P2A1T2RST
P2.5/PWM
P2.61T2Up..DN
P2.7fT2CAPTURE
HSI.O
HSI.l
HSI.2iHSOA
HSI.3JHSO.5

P4.OIAD8
P4.1/AD9
P4.2iAD10
P4.3JADl1
P4A/AD12
P4.5JAD13
P4.6/AD14
P4.7/AD15

-

RD
WRUWR
WHElBHE
ADV/ALE
INST
CLKOUT
Pl.D
Pl.1
Pl.2
Pl.3
Pl.4
Pl.5
Pl.6
Pl.7

VREF
ANGND
EA

U1

HSO.O
HSO.l
HSO.2
HSO.3

60

23
24
25

59

58
57

26
27
28

56
55
54
53

29
30
31
32
33
35
36
37
38

52
51
50
49
48
47

46
45

39

61

22

40

2
1
13

41
62

~
~

---..!..

ADO/AD
ADI/Al

AD2/A2
ADS/A3
AD4/A4
AD5JAS
AD6/AS
AD7/A7
AD8/A8
AD9/A9
AD101Al0
AD111Al1

AD12/A12
ADl3JA13
AD14/A14
ADl5JA15

iii)
WR
BHEtPSEN
ALE
RESET

U2

~
~~
~

~

Al6iCS8
A17/CSB
Al8/CS10
A19/CSI

~PA3.2
r-&-<;>PA3.3
~PA3.4
15 ; PA3.5
PA3.6

r--ti")

~

~
9
; PB4.1
f-i--<;, PB4.2
f-T)

::!,

c-W PB4.5'

f-i--s
~
PB4:&"

40

~

VCC

~
34

PBO
PBl
PB2
PB3
PB4
PB5
PBS
PB7

I~~~
~PA3.1

GND

:: 'P1.O'
~
~

~

PAO
PAl
PA2
PA3
PA4
PAS
PAS
PA7

Rl
10K

Pl.1

~
Pl.3

~

T

C3

O.D1~F

GND

_ _IIEE
-----------------------------------------rJrJr~~----------------------------------------

2-305

•

1'SIJ3IJ1-Application IIotll 013

Simple
Interfaces
to the I'S0301
(Cont.)

The other configuration options that are
available, but not listed above, are application dependent and can be changed to
meet the requirements of the design. For
instance, on e!!!..43 (A 19/CSI), the powerdown option CSI could be selected if
power consumption savings is important.
If it isn't and another logic input to the
PAD would be helpful, A19 could be
selected. And, if open-drain drivers are
important on one of the ports to drive a
display, for example, they also could be
selected instead of CMOS drivers.

from Motorola. For simplicity's sake, the
PSD301 interface to 68HC11 versions
with multiplexed address/data buses will
be discussed, although the nonmultiplexed versions will interface to the
PSD301 in a similar manner, except in
this case port A will become dedicated for
8-bit data.
Figure 6 illustrates the interconnections
between the PSD301 and the 68HC11
microcontroller with multiplexed
address/data buses. Again, all the
address/data connections are direct, as
well as the control Signals (E, RIW, AS,
and /RESET). Because BHE/PSEN is not
used, this PSD301 input signal is tied
HIGH.

All other microcontrollers have simple
interfaces to the PSD301 as well. This
includes all the variations of microcontrollers in the 8-bit 68HC11 family

Figure 6.
Genera/Schematic
Diagram of the
6BHC11and
PSD301.

1

cl.l

1

R2 1M

0

lC2

Xl
8MHz

1

20PF l

GND

?

EXTAL
IRQ

~
39
~

XlRQ
RESET
PAOIIC3
PA1~C2

6

PA2~Cl

~
PO.2~
PO.O
PO.l

PEOIANO
PEl/ANI
PE2IAN2
PE3IAN3

18
19

~

~

~~::

P01~XD

45

VCC~~

l~
...A

R4
4K

r
24

PCS/ADS
PC6IAD6
PC7/AD7
PBOIA6
PB1/A9
PB2IA10
PB3IA11
PB4/AI2
PBSlA13
PB6IAI4
PB7/AI5

POO/RXD

~

)

XTAL
PCOIADO
PC1/ADl
PC2IAD2
PC3IAD3

PC4/AD4

~
::~:~

20PF

68HC11A8

PD2IMISO
PD3IMDSI
PD4ISCK
PDSlSS
MDDB
MODAILIR

PA3IOCSlOCI
PA4/0C4iOCl
PASlOC3lOCl
PA6IOC2IOCI
PA71PIAlOCl
E
STRB/RIW
STRAIAS

VRL
VRH

~

23
24
2S
26
27
28
29

32
33

34
35
36
37
38

30

16
15
14
13
12
11
10
9

31
32
33
35
36
37
39
39

5

22
2

~

r--4r-~
l--"4-

tB
~

~

r¥.-

PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7

AD8
ADS
AD10
ADll
AD12
AD13
AD14
ADIS

PBO ~
PBl
PB2
8
~
PB3
PB4
PBS ~ PB.S
PB6
PB.6
PB7
...f!!L

1

I

~
I-1e)
PA.2

t--tr
16

PA.3

~:~

~PA.6

~~
~O

"..m-.

~
~

t-t-'

E

PCO
PCl
PC2

RIW
BHE/PSEN
AS
RESET
A19/CSI

~
41
PCl
~

U3

26

21

22

~D

"PAii3'

VCC

-

PAOA

>PAO.s

VCC

LMC34064

~~ )PA.O

ADO
ADI
AD2
AD3
AD4
ADS
AD6
AD7

28

VCC

U1

PSD301

GND

Rl
lk

R3
lk

~

~
-

VDD
3
RESET

(tJ2

GND

'----'

r

l~F

C3

GND

-----------------------------~Jf;---------------------------2·306

PS0301-Application Note 013

Simple
Interfaces
to the PS0301
(Cont.)

The PSD301 must be programmed using
WSI's MAPLE software package in the
following modes to achieve this
configuration:

The "Smart"
Transmitter
Design.

The microcomputer-based smart
transmitter design, by Bailey Controls,
requires program store 256K bits EPROM
for storing algorithms and data store 16K
bits SRAM for storing A/D, communication and LCD routines. It also
requires two octal latches, a PLD, and a
variety of glue logic to interface to its

o
o
o
o
o
o

Figure 7.
Detailed Block
Diagram of
Bailey Control's
Alternative
De'
l t"Ion
sIgn Sou
~ithout PS0301.

8-bit data bus
Multiplexed address/data
R/W and E mode set
Active HIGH AS (ALE)
Active LOW RESET
Combined memory mode

68HC11 microcontroller, UART, and LCD
display. This is illustrated in Figure 7. Of
course, with board space on the digital
board being limited, another board would
have been needed to accommodate
these components, unless they in some
way could be integrated.

1~----T------.---tl
~

INTEGRATOR
&
COMPARATORS

rrNPUT

lMULTIPLEXERS

SELECTORS

68HC11E1
MICRO·
CONTROLLER

T

POWER
SUPPLY

•
I

1
1
1
1
1

r--

GLUE LOGIC

I

SENSOR

Again, other parameters on the PSD301
can be set to fit additional design
requirements. These include the security
bit, the port I/Os, and the PAD inputs and
outputs.

74HC10

Ir11'-

I 74HCOQ
I 74HC08 Ihl
I 74HC14 I

HC373
LCD
OCTAL
LATCH

B~~

r

LCD

~~

SMART
XMITTER
UART

~.--

,+

~

I

COMMUNICATIO~
TRANSFORMERS

~

ADDRESS!

DATAl

BUS

VOLTAGE
REGULATOR

HC373

1
1
1
1
1
1
1

INPUT BOARD
BLOCK DIAGRAM

ADD!DATA
OCTAL
LATCH

~
~

EPROM
32K

.--

~

.--~

'-

~

SRAM
2K
~

PAL
22V10

1'-1
1
1

~

LINE
DRIVERS
&
RECEIVERS

1
1
1
1
I

MICROCONTROLLER BOARD
BLOCK DIAGRAM

POWER SUPPLY &
COMMUNICATION BOARD
BLOCK DIAGRAM

-------------------------------------~~~-----------------------------------2-307

PSD301-Application Note 013

The "Smart"
Transmitter
Design
(Cont.)

This is where the PSD301 provides
exceptional value. As discussed, the
PSD301 already integrates EPROM,1
SRAM,2 a PLD, and other glue logic all
on one chip. It interfaces to the 68HCll
directly and actually integrates 8 chips
from the alternative design into one,
eliminating the need to add another board.
The resultant architecture is illustrated in
Figure 8.

port A is configured as an liD and mapped
to the byte-wide LCD data inputs. Then to
write to or read from the LCD display, port
A is accessed like a memory-mapped
peripheral via an address offset from the
base CSIOPORT defined in the PAD.
Since port A is qualified by and handled
through the PAD, there is no need for an
external octal latch.
Other TTL logic is not required to interface
to the 68HCll 's control signals, memory,
or peripherals either. It is all integrated in
the PSD30l. Thus, a smaller PLD than
originally thought required in the design
was used - a l6V8 instead of a
22Vl0 - because the PAD was able to
reduce the amount of logic by creating
chip selects for the UART and other logic
functions.

Note that in the alternative design shown
in Figure 7, ports typically lost when
connecting the microcontroller to external
memory had to be recreated externally with
latches and buffers when memory was
connected to the microcontroller. With the
PSD30l, these ports are recreated internally, eliminating the latches and buffers.
For example, to interface the PSD301 to
the 24-character LCD display, each pin of

Figure 8.
Block Diagram of
Bailey Control's
''Smart'' Transmitter
Design with PSD301

--.

POWER
SUPPLY

INTEGRATOR
&
COMPARATORS

I
I
I
I
I

!
PORT A DATA

r--

PSD301
WI32K EPROM
2K SRAM
PAD & PORTS

MULTIPLEXERS

SENSOR

~

SELECTORS

VOLTAGE
REGULATOR

INPUT BOARD
BLOCK DIAGRAM

1

68HC11E1

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

LCD
PORT B

COMMUNICATION
TRANSFORMERS
I
I
I
I
I
I
I
I
I
I
I

ADDRESS/
DATA BUS

MICRO·
CONTROLLER

...

•
SMART
XMITIER
UART

--I

MICROCONTROLLER BOARD
BLOCK DIAGRAM

I
I
I
I

PAL16V8

I

•

1+

LINE
DRIVERS
&
RECEIVERS

,

POWER SUPPLY &
COMMUNICATION BOARD
BLOCK DIAGRAM

-------------------------------------~~~-----------------------------------2-308

I'SD301- Application Note 013

PS0301

Bonuses

Besides considerably reducing board
space in this smart transmitter design by
reducing parts count, several other
benefits of the PSD301 were also seen.
These include reliability improvement,
power consumption savings, inventory
savings, faster time-to-market, and cost
savings.
Reliability was improved because there
are seven less chips required for
implementation that could fail in the
design. Also, by reducing chip count, 112
pins and about 100 traces were eliminated
and the number of layers on the board
were reduced from 8 to 4, making failures
due to open or shorted pins and traces
less likely to occur.
Power consumption was reduced because
much faster discrete EPROM and SRAM
devices with access times of -75 ns would
have been required in conjunction with
glue logic for selecting different devices
instead of using the PSD301, saving at
least 20 mA Icc. (The access time for the
PSQ301 memories include decoding and
input address latch delays). If the
power-down feature on the PSD301 were
also used, power savings could be
increased further. For example, in a
system which is accessing the PSD301
only a quarter of the time, the power
consumption could be reduced by 75% to
8 mA typical.

As an added benefit, the PSD301 helped
reduce inventory significantly by
obsoleting multiple chips. And, if last
minute changes in the design were
required, the PSD301 would be able to
accomodate them without additional
hardware modifications. So, purchasing
line item management is made simpler
and easier.
With the reprogram mabie PSD301,
development time was kept to a minimum
by easily accommodating design iterations
in both hardware and software. Changes
in 1/0, address mapping, bus interface,
and code were simple to make. Also,
debugging -was made easier with the
PSD301 's on-chip SRAM for downloading test programs. This all helped to
shorten the design development cycle,
reduce development costs, and speed up
market introduction of the smart
transmitter.
By using the PSD301, cost savings were
realized by reducing system cost with
fewer boards (or reduced board space),
improving reliability, and reducing
inventory levels. Savings were also
attributable to lower manufacturing costs
because there were fewer parts to
program and place. And by getting to
market faster, profits were improved
significantly.

Summary

The PSD301 peripheral solved a fundamental problem often seen in that instead
of getting "locked into" an inflexible
multiple chip memory sub-system
solution, the PSD301 was able to provide

Notes

1.

If more EPROM was needed, the PSD302/312 w/512K bits EPROM and the
PSD303/313 w/1 024K bits EPROM are available in the same pinout and packages
(please call your local WSI sales representative for availability). Or, multiple PSD301 s
can be cascaded together with the added benefit of increased functionality and 1/0's.

2.

If more SRAM is needed, it can be added externally without requiring any additional
glue logic. See WSI Application Note 011. Note that many engineers have 8K x 8
SRAM in their systems now - not because they need it, but because 2K x 8 SRAMs
are not as readily available.

much higher integration and flexibility all
at the same time. Clearly, using the
PSD301 was the better choice for the
smart transmitter design.

-------------------------------------~~~-----------------------------------2-309

•

1'SDSD1- Application /lots 013

Appendix 1.
PSD301
Configuration
wsi PSD301 configuration Save Pile for Smart Transmitter Desiqn
ALIASES
CSo = ASICCS
*******************************************************************************
GLOBAL CONFIGURATION
Address/Data Mode:
Data Bus Size:
CSI/A19:
Reset Polarity:
ALE Polarity:
WRD/RWE:
A16-A19 Transparent or Latched by ALE:
using different READ strobes for SRAM and EPROM:

MX
8
CSI
LO
HI
RWE
T
N

*******************************************************************************
PORT A CONFIGURATION (Address/IO)
Bit No.

Ai/IO.
IO
IO
10
10
10
10
10
10

a

1
2
3
4
5
6
7

CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

*******************************************************************************
PORT B CONFIGURATION
Bit No.

CS/IO.

1
2
3
4
5
6
7

CS1
CS2
CS3
CS4
CS5
CS6
CS7

a

CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

csO

CHIP SELECT EQUATIONS
/ASICCS
/CS1

= /A15
/A15

*

* A14 * /A13 * /A12 * E
A14

*

/A13

*

A12

/CS2 - /A15 * A14 * A13 * /A12

*

E

* E

/CS3 - /A15 * A14 * A13 * A12 *

E

/CS4
/A15 * /A14 * /A13 * /A12 * /A11 * E
+ /A15 * /A14 * /A13 * /A12 * /A11 * / R/W
/CS5 = /A15 * /A14 * /A13 * /A12 * All * E
+ /A15 * /A14 * /A13 * /A12 * All * / R/W
/CS6 = /A15 * /A14 * /A13 * A12 * /A11 * E
+ /A15 * /A14 * /A13 * A12 * /A11 * / R/W

=

/CS7
/A15 * /A14 * /A13 * A12 * All * E
+ /A15 * /A14 * /A13 * A12 * All * / R/W
,.• • .eE

---------------------------------------~~jf--------------------------------------

2-310

PSD301-Application Note 013

Appendix 1.
PS0301
Configuration.
(Cont.)
********************************************************************************

PORT C CONFIGURATION
Bit No.
0
1
2

CS/Ai.
CS8
CS9
CS10
CHIP SELECT EQUATIONS

/A15 ,. /A14 ,. A13 ,. /A12 ,. /All ,.

/CS8

/CS9 .. /A15 ,. /A14 ,. A13 ,. /A12 ,. All ,.

R/W
R/W

/CS10 = /A15 ,. /A14 ,. A13 ,. A12 ,. /All ,.

R/W

********************************************************************************

ADDRESS

ESO
ES1
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

MAP

A A A A A A A A A
19 18 17 16 15 14 13 12 11
N N N N 1 0 0 0 N
N N N N 1 0 0 1 N
N N N N 1 0 1 0 N
N N N N 1 0 1 1 N
N N N N 1 1 0 0 N
N N N N 1 1 0 1 N
N N N N 1 1 1 0 N
N N N N 1 1 1 1 N
N N N N 0 1 1 0 0
N N N N 0 0 1 1 0

******************************

.. 0
CDATA
CADDRDAT
1
.. 1
CRRWR
CA19/(/CSI)
0
CALE
0
CRESET
0
COMB/SEP
0
CADDHLT
0

END

SEGMT
STOP
8FFF
9FFF
AFFF
BFFF
CFFF
DFFF
EFFF
FFFF
67FF
37FF

EPROM
START
8000
9000
aOOO
bOOO
cOOO
dOOO
eOOO
fOOO

EPROM
STOP
8fff
9fff
afff
bfff
cfff
dfff
efff
ffff

File Name
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0

****************************************

CPAF1
CPAF1
CPAF1
CPAF1
CPAF1
CPAF1
CPAF1
CPAF1

0
0
0
0
0
0
0
0

[0]
[1]
[ 2]
[3]
[4]
[ 5]
[6]
[7]

=0

CPAF2
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF

SEGMT
STRT
8000
9000
AOOO
BOOO
COOO
DOOO
EOOO
FOOO
6000
3000

[0] ,. 0
0
[ 1]
0
[2]
0
[3]
0
[4]
0
[5]
0
[6]
[ 7] = 0

CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD

[0] .. 0
[ 1] .. 0
0
[2]
0
[3]
[4]
0
0
[5]
0
[6]
[7] .. 0

[0] .. 0
0
[1]
0
[2]
0
[3]
0
[4]
[ 5]
0
0
[6]
0
[7J

CPCF [0]
CPCF [1]
CPCF [2]

fffffr;

1
1
1

2-311

•

~2-~31=2-----------------------~Jr~;-------------------------

Programmable Peripheral
Application Note 014
Using the PSD3XX PAD for System Logic
Replacement
By Jeff Miller

Introduction

In 1990, WSI introduced the Programmable
System Device (PSD): the first device in
the world integrating UVEPROM, SRAM
and programmable logic on a single chip of
silicon. The highly-successful PSD301 was
the first device in the PSD family and is
currently used in applications ranging from
fluid analyzers to high performance
computers. The PSD device, by combining
most of the peripheral functionality required
by a typical microcontroller unit into one
package, has enabled designers to greatly
reduce part count, power and board space
which has translated into significant cost
savings.
Even if the PSD3XX family were simply a
collection of EPROM and SRAM with an

PAD
Architecture

The Programmable Array Decoder (PAD)
contained in the PSD3XX family is a standard PLD array designed to provide all of
the internal memory and I/O device chip
selects as well as an external logic replacement capability. It has 14 inputs, 24 outputs
and 40 product terms with which to perform
these functions. See Figure 1 for an
illustration of the PAD.
The PAD's 14 inputs are as follows:

o
o
o
o

All-A19
ALE or AS
RD or E
WRor RiW

The All - A 19 pins are labeled as address
inputs, however, they do not have to be.
All - A 15 are generally sourced by the
microcontroller or microprocessor that is
connected to the PSD device. If the
controller generates more than 16 bits of
address, the A 16 - A 19 inputs may be
used to connect the high order address bits
for a full 1 MByte of address space. If the
controller does not require this much
address space, A16 - A19 may be used for
other purposes, like general I/O or logic
inputs.
A19 is multiplexed with the CSI signal,
which is used to place the PSD device in a

on-chip decoder, it would be capable of
adding significant value to the system into
which it were designed. However, the
PSD3XX family is much more than just a
combination of memory devices. The onchip PLD may be used for many useful
purposes in addition to providing the
address decode capability. The purpose of
this note is to demonstrate, in detail, the full
capability of the PAD section of the
PSD3XX family. A basic, though not extensive, knowledge of the PSD 3XX family and
the Maple programming software is
assumed by this note. Please consult
Application Note 011 and/or the appropriate
PSD3XX family data s~eet for this general
knowledge.

low power mode when the system requires
it. When configured as CSI, the A19 pin
may not be used for any other purpose
except the power down mode. In this
mode, the CSI signal is used by the PAD
only to disable it, causing it to expend less
power. When configured as A 19, this signal
may be used as a general purpose input to
the PAD from the external system. This
capability will be described in more detail
later in this note. A 16 - A 18, when not
necessary for address expansion, may also
'be used as general purpose inputs to the
PAD. Thus, a total of four of the 14 PAD
inputs may be general purpose, allowing
the replacement of external logic by the
PSD device. These inputs may be
combined with the other PAD inputs to form
complex equations involving addresses,
strobes and external signals.
When attempting to visualize the full capability of the PAD outputs, it is most clear
when it is broken into two sections, labeled
in Figure 1 as PAD A and PAD B. PAD A is
responsible for providing all of the internal
chip selects for the EPROM, SRAM and I/O
ports and the track mode control signals,
and PAD B is responsible for the external
logic replacement function.

2-313

•

~

I

I'SD3XX - Application Note 014

Figure 1.
PAD
Architecture
ALEorAS ~

ESO

"

~

"
Ro or E

-g-:

~

v

,...
"S

WR or R/W

-q

A19

-

-"

"

AlB

A17

A16

-:s_

,.....

-

-g.•

-

-q

A15

"

ES1
ES2
8 EPROM Block
ES3
ES4
Select Lines
ES5
ES6
ES7
RSO _ _ SRAM Block Select
CSIOPORT _I/O Base Address
CSADIN
Track Mode
CSADOU
} Control Signals
CSADOU

H

CSO/PSO

1

PAD A

!

CS1/PB1

CS2/PB2

~

-j

J").

CS3/PB3

"'S

,.....

A14

~.

-q

A13

A12

All

-

"

CS4/PB4

"

CS5/PB5

'"

CS6/PB6

'"
K

CS7/PB7

"

CS8/PCO

"

~

CS9/PC1

-"

CS10/PC2

PADB

~

N
...

,.....

"5
-

CSI

~

RESET
~

PAD A

Thirteen of the 24 PAD outputs and thirteen
of the 40 product terms are dedicated to
PAD A. PAD A should be considered the
internal address decoder, used to select
the various on-chip memories and 1/0
devices according to the memory map
programmed by the user. Each output has
a single product term, allowing a particular

resource to be allocated a single
contiguous range of addresses which will
be used to access it. All of the PAD inputs
are available for generation of the PAD A
outputs, allowing the designer to select
internal resources using any combination of
address, strobe and external signals.

-------------------------------------~~~-----------------------------------2-314

PS03XX - Application Note 014

PAD A
(Cont.)

The PAD A outputs are as follows:

o
o
o
o
o
o

ESO- ES7
RSO
CSIOPORT
CSADIN
CSADOUT1
CSADOUT2

ESO - ES7 are used to select the internal
EPROM resources. Using the PSD301 as
an example, there are eight select lines
with which to access 32 KBytes of EPROM.
Thus, each select line can enable a block
of 4 KBytes of EPROM configured as
4K x 8 or 2K x 16. Each block must be
contiguous, but the blocks may be placed
anywhere within the address space of the
microcontroller.
RSO is used to select the SRAM resource.
This single signal accesses a single 2
KByte block of SRAM which may be
configured as 2K x 8 or 1K x 16. Again, this
block must be contiguous but may be
placed anywhere in the address map.
CSIOPORT is the signal which defines the
base address of the on-chip I/O ports and
control registers. The I/O ports and control
registers occupy a 2K block of addresses
which, like the memories, must be
contiguous but may be located anywhere in
the address space of the microcontroller.
Once configured in the address map,
CSIOPORT defines the base address of
these ports and registers. An offset is
added to the base address to individually
access the registers. Table 1 below lists the
offset values for these registers.

Table 1.
I/O Port
Offset
Addresses

Register Name
Pin Register of Port A

CSADIN, CSADOUT1 and CSADOUT2 are
used to control the Track Mode operation.
The Track Mode is an available option for
Port A to allow it to "track" the
Address/Data bus inputs to the PSD device
from the microcontroller. This provides the
capability to connect the PSD device, and
therefore the microcontroller, to one or
more shared resources. These resources
may be memory or other devices which
must be accessed by more than one microprocessor or microcontroller.
CSADIN is generated when the microcontroller is attempting to read data from Port
A in the track mode. It is generated from
one product term involving the address
inputs and the RD sirobe (Intel mode) or
RiW and E (Motorola mode). This allows
the user to configure the address range in
which the data is to be read from Port A.
CSADOUT1 is generated when the microprocessor is accessing a "tracked" address.
It is generated from a single product term
involving the address inputs and ALE.
When the address generated by the microcontroller is within the block specified by
the user for track mode, and the ALE is
active, CSADOUT1 becomes active, transferring the address and outputting it from
Port A. CSADOUT2 is generated when the
microcontroller is performing a write operation to a tracked address. It also has one
product term involving the address inputs
and WR (Intel mode) or R/W and E
(Motorola mode). When the microcontroller
performs a write to the appropriate
address, CSADOUT2 is generated, transferring the data and outputting it from Port
A. For further details on the operation of
the Track Mode, please consult Application
Note 017.

•

Byte Size Access of the I/O Port Registers
Offset from the CSIOPORT
+ 2 (accessible during read operation only)

Direction Register of Port A

+4

Data Register of Port A

+6

Pin Register of Port B

+ 3 (accessible during read operation only)

Direction Register of Port B

+5

Data Register of Port B

+7

-------------------------------------~~~~------------------------------------

2-315

------

------

PS03XX - Application Note 014

Example:
Address
Mapping
With PAD A

In this example, we will choose a sample
address map which is similar to those used
in typical microcontroller applications. This
example assumes the us~ of a PSD301
device with 256 Kbits of EPROM and 16
Kbits of SRAM. Figure 2 below illustrates
our sample address map.
In this example, we have located the boot
code and interrupt service routines beginning at address 0000 in EPROM block O.
The SRAM is located in the 2K block beginning at address Ox1 000 and can be used
for the stack and/or other scratch pad data.
The I/O ports occupy the 2K block beginning at address Ox1800. Addresses in this
range will access ports A and B and their
control registers. The area from Ox2000 to
Ox8FFF is unused in this example, though
it could be used for external resources as
will be shown later. Finally, the main
program resides in the 28K block of
EPROM located from address Ox9000 to
OxFFFF and is selected by ES1 - ES7.

Figure 2.
Example
Memory Map

Configuring this memory map would
normally require designing a decoder to
generate the appropriate chip selects for
each given address range. For example,
assuming that a microcontroller with a 16bit address bus is used, the chip select for
EPROM bank 0 (ESO) would be generated
with the following equation:
ESO

= /A12· /A13· /A14· /A15

Equations like this one would be formulated
for each of the chip selects, and the entire
function would probably be placed in some
kind of programmable device. When the
PSD device is used, PAD A replaces this
programmable device. Programming PAD
A to perform this function is a simple task
using WSI's Maple software.
Entering the ADDRESS MAP menu in the
Maple software running on a PC compatible computer, the user will see a screen
similar to the one shown in Figure 3.

FFFF

MAIN
PROGRAM

USING

9000

ES7
ES6
ES5
ES4
ES3
ES2
ESl

-

-

-

60
56
52
48
44
40
36

-

64K
60K
56K
52K
48K
44K
40K

8FFF

2000

lFFF
USING CSIOPORT -

I/O PORTS

6 - 8K

1800

17FF

SRAM

USING

RSO

-

4 - 6K

BOOT CODE &
INTERRUPT SERVICE

USING

ESO

-

0 - 4K

1000

OFFF
0000

________________________________
2-316

f~==E

________________________________

PSD3XX - Application Note 014

Example:
Address
Mapping With
Pad A (Cont.)

PADB

Upon displaying this screen, the Maple
software is ready for the user to enter the
memory map data. This is performed quite
simply by moving the cursor to the appropriate point with the arrow keys, and then
entering the appropriate data. The address
mapping may be entered in either of two
ways. First, the user may select each
address bit individually for each chip select
and enter a 0 or 1 as appropriate for the
equation desired. In our example, for ESO
we would enter a 0 in the columns for A 12,
A 13, A 14 and A 15. The other bits are don't
cares. In the other method of programming
the pad, the user simply moves the cursor
to the SEGMT START column and enters
the desired starting address for the block.
Again, using our sample memory map, the
user would move to the SEGMT START
column for ESO and enter 0000. Maple
Eleven of the PAD outputs and 27 of the
product terms are dedicated to PAD B.
Where PAD A was used to control the onchip PSD device resources, PAD B controls
any off-chip resources required by the
system. As with PAD A, all inputs to the
PAD are available to PAD B, allowing the
system designer to formulate outputs
involving any combination of address,
strobes and external signals. Unlike PAD A,
several of the outputs of PAD B have up to
four product terms each.

Figure 3.
Maple Address
Map Entry

then automatically programs the O's and 1's
into the address bits correctly to program a
4K block of EPROM beginning at address
OxOOOO. Note that all EPROM blocks must
begin on 4K boundaries. Figure 3 shows
the resulting address map table for our
example.
The address inputs which were unused in
this example (A16, At7, A18 and A19)
could have been used as general purpose
inputs to the PAD for specialized control of
the on-chip memory and 1/0 resources.
When this is done, the designer has
complete flexibility as to the configuration
of the PSD device resources and may
easily absorb many system functions into
the PSD device. More detail about the use
of A 16 - A 19 will be provided later in
this note.
The outputs of PAD B are as follows:

o
o

CSO - 7 (Port B)
CS8 -10 (Port C)

The outputs from PAD B are brought to the
outside world through Port B and Port C.
These outputs are called chip selects,
though they may be used for any function
whatsoever. The port pins are configured
as selected by the user when the device is
programmed with the Maple output file.
There are many configuration options for
each port pin.

ADDRESS MAP
A

A

A
17

A

A

A

A

A

16 15

14

13 12

11

X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X

a

a a

N
N
N
N
N
N
N
N

x

x

x a

0
0
0
0
1
1
1
1
0
0

19 18
ESO
ES1
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

X
X
X
X
X
X
X
X
X
X

A

0
1
1
1
1
1
1

a

0
1
1

1

a
1

a a
a 1
1
1

a
a

0
1
1
1

a
1

SEGMT
START

SEGMT
STOP

0000
9000
AOOO
BOOO
COOO
0000
EOOO
FOOO
1000
1800

OFFF
9FFF
AFFF
BFFF
CFFF
DFFF
EFFF
FFFF
17FF
1FFF

FILE
START

FILE
STOP

FILENAME

ALIASES:
Fill in A19 - A11 (Binary) or SEGMT START (Hex): and FILE (START, STOP)
and FILE NAME, Use SPACEBAR to erase any field value.
F1 - Return to Main Menu
F2 - Temporary Exit to DOS F3 - Go to Help
Cursor - UP: t
Down: l
Left Col: Right Col: Right - F4
Left - F5

-------------------------------------'AfjfjF~-----------------------------------'EiFiEJEg IE

2-317

•

PSD3XX - Application Note 014

PADB
(Cont.)

If you require more information about port
configuration, please consult application
note 011. If the port outputs are
configured as chip selects (outputs from
the PAD), they may not be used for any
other purpose. For example, the three Port
C signals may be configured as chip
selects (outputs) or addresses (inputs) but
cannot be both. Fortunately, the flexibility of
the PSD device and the Maple software
allows the designer to configure each Port
Band C pin individually, so that the number
of outputs and inputs may be optimized for
a particular design requirement. See Table
2 below for an example of this flexibility.

Table 2.
Sample Port
Configuration

Example:
Generating a
Logic Equation
WithPADB

Pin

Configuration
Address
Address
Address
Address
1/0
1/0
1/0
1/0

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

CSO
CS1
CS2
CS3
1/0
1/0
1/0
1/0

CMOS
CMOS
CMOS
CMOS

PCO
PC1
PC2

A16
A17
CS10

00

= A15" A14 "/A13 "/A17" RD
+ I A 15 " A 14 " A 12 " WR + A 16

Figure 4 illustrates the Maple programming
sequence to generate this equation.
To program this equation, the PORT B
menu is entered from the Maple software.
CSO is selected by moving the cursor to it
using the arrow keys. With CSO selected,
the user then presses the F3 key to bring
up the CHIP SELECT DEFINITION table
for CSO. The table contains four rows for

2-318

Out
Out
Out
Out

CMOS/DO

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

Assume that it is necessary to generate the
following equation given the port configuration in Table 2 above. This equation is a
simple OR of three product terms.
CSO

This sample port configuration demonstrates all of the possible uses of a particular port pin. Though only Ports Band C
may be inputs or outputs tolfrom the PAD,
Port A is included in the table for completeness. In this example, five of the port pins
are configured as PAD outputs (CS) and
two are configured as PAD inputs (A). The
remaining port pins in this example are
configured as either 1/0 or address outputs.
Several of the CS outputs have been
configured as open drain. This allows them
to be connected together in a wired OR
configuration to increase the number of
product terms even further if desired.

CMOS
CMOS
CMOS
CMOS
CMOS

00
00
CMOS
CMOS
CMOS

00
00

data entry, each one corresponding to one
of the available product terms for CSO.
Implementing this equation required using
three of the four available product terms.
The fourth is left blank and will not be used
to generate the output.
To enter the equation into the table, simply
move the cursor around into the appropriate position and enter a 1 if the corresponding signal should be high for the
equation to be true, a if it should be low,
and X or SPACE if the signal is a don't
care. The first term of the equation requires
a low on A17, a high on A15, a high on
A 14, a low on A 13 and a high on RD for the
term to become active. Thus, 1's are
placed in the A15, A14 and RD positions,

PSD3XX - Application Note 014

Example:
Generating a
Logic Equation
WithPADB
(Cont.)

and O's are placed in the A 17 and A 13
positions. The remaining terms in the equation are entered in the same way. Note that
A 17 and A 16 in this example need not be
address bits, but may instead be used to
bring external signals into the PAD.

of the CSO - CS3 outputs, two terms are
available on the CS4 - CS7 outputs and
one term is available on CS8 - CS1 O.
When planning the use of the PAD outputs,
it is important to consider this so that the
most efficient use of the product terms can
be achieved.

Four product terms are available on each

Figure 4.
Programming
PAD Outputs

PORTB
PIN

CS/I/O

CMOS/OD

PBa
PB1
PB2
PB3
PB4
PB5
PB6
PB7

csa
CS1
CS2
CS3
CS4
CS5
CS6
CS7

CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

CHIP SELECT DEFINITION CSO
A19 A18 A17 A16 A15 A14 A13 A12 A11 ALE

1
1

a

x

x

X

1
a

x

1

1

X

X

X

X

X

X

a

x

X

X

X

X

X

X

RD WR

1

X

X

X
X

X

1

X

X

X

X

ALIASES:
CS definition is the NOR of the product terms (rows). Enter 1 to select Active High signal,
o to select Active Low signal, X to mean "don't care", SPACEBAR to erase. Enter values
in columns relevant to your application; other blank columns will be treated as
"don't cares".
F1 - Return to PORT B

Application
Examples

Cursor - Up:

The following section will illustrate the use
of the PAD for system logic replacement in
some common microcontroller applications.

Basic Chip Select Generation
One of the simplest uses of PAD B is the
generation of chip selects for off-chip
resources such as I/O devices or memories. Figure 5 below depicts the connection
between a 68HC11 microcontroller, the
PSD301 and two common peripheral
devices: the 8250 UART and the 8254
counter/timer.
The 68HC11 is an 8-bit microcontroller with
a 16-bit address bus. The lower 8 bits of
address are multiplexed with the data bus
while the upper 8 bits are transmitted on
their own bus. An address strobe (AS) is
provided to latch the address off of the
multiplexed bus. A RlW signal indicates
whether the current bus transaction is a
read or a write (R/W = 1 = read, R/W = 0 =

t

Down: ~

Left:...

Right: ...

write). The E signal is the clock used to
strobe the data in or out of the microcontroller. The PSD301 can be configured to
exactly match this signal definition and then
connected as shown in the diagram. Not all
of the 68HC11 or PSD301 signals are
shown, only those relevant to this example
of PAD capability.
The 8250 is a UART device commonly
used in microcontroller systems to provide
a serial data communication port. It has a
simple bus interface, yet does not directly
connect with the 68HC11 bus architecture.
It requires an 8-bit bus to transfer data to
and from the microcontroller and a separate 3-bit address bus used to access its
internal registers. It also requires a chip
select and separate read and write strobes
(RD and WR). The chip select is generated
by decoding the address from the microcontroller. The RD and WR signals may be
generated from the R/W and E signals

-------------------------------------fAf~~=-----------------------------------...~~=
2-319

•

PS03XX - Application Note 014

Figure 5.
A Typical
Microcontroller
System

PS0301

68Hell

pco

~E
~~
I ~
I ~~

PCl
I
PC2
PC3
PC4 I
PC5
PC6
PC7
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
E

RIW
AS

r

INS8250

r=
~

ADO
AOl
A02
A03
A04
A05
A06
A07

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

AS
A9
Al0
All
A12
A13
A14
A15

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

E

PCO f - PCl I---

R/W

AS

fC
c;=

"

DO
01
02
03
04
05
06
07
AO
Al
A2

V

CS2

AD

WR
8254

~
~

PC2'l

::=
c;=

Y

DO
01
02
03
04
05
06
07
AO
Al
RO
WR

cs
Application
Examples
(Cont.)

according to the following equations:
/RD = /(Riw • E)
/WR

= /(/R/W • E)

These equations may be easily generated
using PAD B and sent out through two of
the chip select outputs. We have chosen
CS5 and CS6, which come out on PB5 and
PB6, for this example.
In order to provide the address lines to the
8250, we have configured Port A to output
the latched address. This eliminates the
need for any external latches to demultiplex
the address/data bus from the microcontroller. Though all eight of the Port A pins
have been configured as address outputs
in this example, it is possible to configure
only those address bits required for the
application, AO - A2 in this example, and
configure the remaining Port A pins as
general I/O.
The 8254 is a programmable interval timer

which, like the 8250, is a peripheral used in
many microcontroller applications. Its bus
connection is very similar to the 8250,
allowing it to use the same read and write
strobes (RD and WR) and address lines. It
also requires a chip select which is
decoded from the microcontroller address.
The chip selects for both of the peripheral
devices may be easily decoded from the
address inputs to PAD B. Normally, the
addresses which are inputs to the PAD
(A 11 - A 19) would give decoding resolution
down to 2K. This means that each of the
two peripheral devices that require chip
selects would be allocated an address
range of at least 2K. Since these devices
do not require this much space and the
68HC11 has only a 16-bit address bus, it is
possible to use the high order address
inputs of the PSD device to improve the
decoding resolution. To achieve this goal,
we have configured Port C as address
inputs A 16 - A 18, but have connected
them to A8 --, A 10 from the microcontroller.
This means that the PAD will now have

-------------------------------------fAfAfAF:-----------------------------------'i!EREE!9 ==
2-320

PSD3XX - Application Note 014

Application
Examples
(Cont.)

access to A8 - A 15 for decoding, thus
providing a resolution of 256 instead of 2K.
This could actually be further reduced to a
resolution of 128 if we were to configure
the A 19/CSI input to be A 19, and then
connect it to A7 from the microcontroller. In
this example, we have not done this so that
CSI is still available to place the PSD301
into low power mode if required.
We now have to define the addresses of
each of the peripherals so that the chip
select equations may be defined. We will
start from the memory map provided earlier
in Figure 2. This map allocated all of the
internal resources of the PSD device. The
external peripherals may be easily added
to the unused area between addresses
Ox2000 and Ox8FFF. Figure 6 depicts the
new map with the external devices added.
Notice that the internal resources can keep

Figure 6.
Memory Map
With Peripherals

their original address mapping even though
the additional address inputs (A8 - A 10)
have been added. This is because these
inputs may be don't cares in the decoding
for the internal resources even when they
are being used for the external resources.
Now, to wrap up this simple design, we
must enter the configuration and mapping
information into Maple. The configuration of
the PSD device must be consistent with the
operation of the 68HC11 microcontroller.
The address/data mode must be multiplexed, the data bus must be 8 bits wide,
CSI/A 19 may be configured either way, the
reset polarity should be active low, the ALE
polarity is active high, the read and write
lines must be Riw and E, A 19 - A 16
should be latched so that these bits
become available just like the rest of the
address bus, and the read strobes for the

FFFF

MAIN
PROGRAM

USING

8000

7FFF
7000

60
56
52
48
44
40
36
32

ES7
ES6
ES5
ES4
ES3
ES2
ES1
ESO

-

64K
60K
56K
52K
48K
44K
40K
36K

PERIPHERAL # 3
1 WS

USING CS7

PERIPHERAL # 2
6 WS

USING CS6

-

24 - 28K

PERIPHERAL # 1
3 WS

USING CS5

-

20 - 24K

USING CSIOPORT -

18 - 20K

-

16 - 18K

28 - 32K

6FFF
6000

5FFF
5000

4FFF
I/O PORTS
4800

47FF
SRAM

USING RSO

4000

3FFF

80C196KB
INTERNAL RESOURCE

0000

-------------------------------------~~~~-----------------------------------2-321

PSD3XX - Application Note D14

Application
Examples
(Cont.)

SRAM and EPROM will be the same. This
configuration should be entered from the
configuration menu of the Maple software.
The address map programming for this
example will remain the same as the one
used earlier in Figure 3. The only items
remaining are the programming of the ports
and the generation of the equations for the
chip selects and read/write strobes. First
we must configure Port A to provide the
latched address to the peripherals. This is
accomplished by entering the PORT A
menu in the Maple software. Maple will
then ask you if you would like Port A
configured for address 1/10 or the Track
Mode. For this example, we will use the
address/l/O configuration. Next, Port A
must be configured pin for pin as an
address output. This is easily performed by
using the cursor keys to select the appropriate pin and pressing the SPACE BAR to
change the configuration. It is also possible
to configure each pin as an open drain or
CMOS output, but for address outputs, it is
better to make them CMOS.

Wait State
Generation

Lastly, we must configure the Port B
outputs to become the chip selects and
read/write strobes. First, the PORT B menu
must be entered. Now, we must configure
each pin as an 110 or CS output.
PBO - PB3 may be configured as general
purpose 1/0 pins. PB4 - PB7 must be
configured as chip selects. Once configured as chip selects, the equations for each
output may be entered by following the
Maple instructions. The procedure is the
same as the one used in the earlier chip
select example. Our equations, including
the ones developed earlier for the read and
write strobes, are defined for each output
as follows:
PB5

= ICS5 = IRD = I(R/W • E)

PB6

= ICS6 = IWR = I(/R/W • E)

PB4 = ICS4 = 18250CS = I(A15· IA14·
A13· IA12· IA11 • IA18· IA17· IA16)
PB7 = ICS7 = 18254CS = I(A15· IA14·
A13· IA12· IA11 • IA18· IA17· A16)

Now, PORT C must be configured to
provide the three additional address inputs.
This is performed by entering the PORT C
menu in Maple and selecting the appropriate pin with the cursor. Each pin should be
configured as an address bit (Ai). Maple will
call the pins A 16 - A 18 even though we will
be using them as A8 - A 10.

This completes the design integrating these
four components with no additional logic
whatsoever. There is also additional space
in the PAD for more functions if necessary,
so we have not yet reached the limit of the
integration possibilities with the PSD301.

Often, when using some of the newer highperformance microcontrollers with slower
external peripherals, it is not possible to
complete a read or write cycle to the
peripheral in the time allowed by the microcontroller's minimum bus cycle. In this
case, one or more wait states must be
added to slow the controller down to the
speed of the peripheral. One way of doing
this is to fix a number of wait states for all
bus cycles to allow the slowest device
enough time for its access. Some
controllers even provide the capability to do
this internally through the programming of a
register. This works, of course, but can
severely impact the performance of the
system. There is no need to penalize the
performance of the entire system, which
can include zero wait state memory
devices and other peripherals, simply
because one or more of the external

devices requires some number of wait
states. It is possible, with minimal logic, to
create a completely programmable automatic wait state generator using the
PSD301 which will allow the fast resources
to operate at zero wait states and still
provide from one to eight wait states for the
slower resources.
For this example, we will use an Intel
80C196KB microcontroller running at 12
MHz. This controller has the capability to
operate in a 16-bit data mode, providing
the opportunity to further increase performance if the system can also operate in
this mode. The PSD301 does have the
capability of operating in the 16-bit mode,
making it a good match for the 80C 196. We
will assume that the 80C196 must be interfaced to several slow 8-bit peripherals
requiring from one to eight wait states. With

FEJEEE=
-------------------------------------~sf:------------------------------------

2-322

PS03XX AppllcatlDn NDte 014

Wait State
Generation
(Cont.)

the PSD301, we can provide the correct
number of wait states for each peripheral
with the added capability of dynamically
sizing the bus to the appropriate width for
the current access.
The memory map we will use for this
design is depicted in Figure 7. The internal
resources of some aoc 196 derivatives
occupy most of the address space from
OxOOOO to Ox3FFF, though some have less
resources. Therefore, we have constructed
the memory map to place the PSD device
resources above address Ox4000. The
PSD301 SRAM and I/O devices occupy
from address Ox4000 to Ox4FFF. This
leaves the area from Ox5000 to Ox7FFF for
external peripherals while leaving oxaooo
to OxFFFF for the EPROM banks. We
assume that we must connect three external peripherals to the PSD device using
this address space, one requiring one wait
state, one requiring three and one requiring
six. This memory map is entered into the
part similarly to the previous examples.

To achieve the variable number of wait
states, the ideal solution is to decode the
address to determine the number of wait
states required for a particular address
range, and then to use a counter to count
the appropriate number. By using the PAD
to initialize an external counter, a variable
wait state counter can be created in this
manner. This wait state generator requires
only one external device, a 74FCT191
counter. The circuit used to implement this
function is illustrated in Figure a. The
aOC196KB is directly connected to the PSD
device which in turn provides the three chip
select signals for the external peripherals
(PER1CS, PER2CS and PER3CS) as well
as the wait state generator function and the
dynamic bus sizing. Ports Band C are fully
utilized to provide the logic inputs and
outputs required to implement these functions, while Port A is still available for
general 110 or address use.
This circuit uses PAD B to decode the
addresses driven by the microcontroller

PSD3XX - Application Note 014

Wait State
Generation
(Cont.)

Figure 8.
Wait State
Generation
Circuit

and provide four outputs, based on these
addresses, which are used to initialize the
74FCT191 counter with its initial value. The
counter is initialized using ALE to latch
these four PAD outputs. The load signal for
the counter is active low, however, while
ALE is active high, so ALE is inverted using
PAD B and sent out through Port C.
Though the 80C196KB can be configured
to provide an active-low address strobe,
ADV, the timing of the signal is inappropriate for use as the LOAD input to the
counter. Once the counter is initialized, it
counts up from the initial value until the
most significant bit increments from 0 to 1.
The output of the most significant counter
bit is routed to the READY input of the
microcontroller. Thus, the controller will be
held in wait states until the most significant
counter bit is incremented. This output is
also routed to the CTEN signal of the
counter so that counting will cease once
the READY signal has been issued to the
controller. The clock for the counter is an
inverted version of the CLKOUT signal
from the controller. This clock must be
inverted since the 80C196KB uses the
falling edge of the clock to sample the

READY input. PAD B again provides the
inversion function by routing CLKOUT
into one of the Port C pins, inverting it
and routing it back out through another
Port C pin.
The counter provides from zero to eight
wait states depending on the initialized
value. For zero wait states, the most significant counter bit is initialized to a "1 ", which
provides the READY signal to the controller
immediately and disables the counter from
incrementing. If one wait state is desired,
the counter is loaded with the value 7 (0111
binary) so that after it increments once, the
most significant bit switches to a "1" and
provides the READY to the controller.
When two wait states are required, a 6
(0110 binary) is loaded into the counter,
and so on for the rest of the wait state
values.
To properly size the bus to the appropriate
width, PAD B is again used to decode the
addresses of the 8-bit devices. When the
address of an 8-bit device is encountered,
the BUSWIDTH signal is driven to
configure the 80C196KB address to eight

PSD301

80C196KB
ADO
AD'!
AD2
AD3
AD4
AD5
AD6
AD7

ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7

PAD
PA1
PA2
PA3
PA4
PA5
PA6
PA7

ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7

ADS
AD9
AD10
AD11
AD12
AD13
AD14
AD15

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

RD
WR
ALE
BHE
ClKOUT
BUSWIDTH ~
READY t---

RD
WR
ALE
BHE

PCO
PC1
PC2

}

G~EML

PURPOSE
ADDRESS OR I/O
74FCT191

t-- PER1CS
t-- PER2CS
t-- PER3CS

Ifr
rr

~

r

QA
QB
QC
QD
CTEN
__
lOAD
ClK

DI-

Diu

r--

I

_____________________________________ WIll ____________________________________
'--~E

2-324

PSD3XX - ApplicatIDn NDte 014

Wait State
Generation
(Cont.)

bits. For all other addresses, the width is
set for 16 bits. The BUSWIDTH signal is
output from one of the Port B pins.
The PSD device must now be configured to
provide the functions required by the
example circuit. The configuration of the
PSD must first be programmed to function
with the 80C196KB. This is easily
performed by the Maple software as in the
previous example. The address/data mode
should be multiplexed, the data bus width
should be 16 bits, CSI/A19 may be
configured as required for the application,
the reset polarity should be active low, the
ALE polarity should be active high, separate RD and WR strobes should be used
and A 19 - A 16 should be transparent, not
latched, since they are used as logic inputs
to the PAD.
Next, we must program the functionality of
Port C. For this example, PCO and PC1 are
used as outputs from the PAD to provide
the LOAD and CLK signals for the '191
counter. This is performed by entering the
PORT C menu in Maple and configuring
PCO and PC1 as CS8 and CS9, respectively. PC2 is used to input the CLKOUT
signal from the microcontroller to the PAD
so that it may be inverted. Therefore, it
must be configured as address input A 18.
Now, the equations used to generate the
PCO and PC1 outputs must be entered into
the PAD. PCO is the LOAD signal which is
just the ALE input inverted. PC1 is an
inverted version of A 18, which contains the

Tab/e3.

Wait State

Summary

CLKOUT signal. These equations are listed
below:
PCO = /LOAD = /ALE
PC1 = /CLKOUT = /A18
The equations are programmed by entering
the CHIP SELECT DEFINITION menu for
each of the two chip selects, as in the
previous example, and entering the appropriate 1's, O's and DON'T CARES. In the
case of PCO, there are don't cares in all of
the PAD inputs except ALE, where there is
a O. Similarly, for PC1 , the A 18 input is a 0
while the rest of the PAD inputs are don't
cares.
Port A is usually configured next, and in
this example it is free to be configured in
any mode necessary for the application. It
may become either I/O or address outputs,
or may be set in the Track Mode as
described earlier.
We are now ready to configure Port B. This
example requires that all of the Port B pins
be used as chip selects (logic outputs) from
PAD B. PBO - PB3 are used to initialize the
counter with the correct number of wait
states for each device. These outputs are
defined according to the address ranges for
each of the peripherals and the number of
wait states required for each. Table 3
summarizes the outputs required for each
peripheral so that we may define the
correct equations for the outputs.

Peripheral No.

Address Range

No. Wait States

PB~PB3

1

Ox5000-5FFF

3

1010

2

Ox6000-6FFF

6

0100

3

Ox7000-7FFF

1110

___________________________________ ;jr=~E---------------------------------
~_I

2-325

•

PS03XX - Application Note 014

Wait State
Generation
(Cont.)

This table can be easily used to form the
necessary equations for PBO - PB3. PB3
can be considered the enable for the wait
state generator which is active low only in
the address ranges of the three peripherals. It must remain high for all other
address ranges. The other three outputs
simply encode the proper number of wait
states. The resulting equations are listed
below:
PBO = fOA = f(AI5· A14· A13· fA12)
PBl

= fOB =f(AI5'

PB2

= fOC =f(AI5· A14· A13 ° fA12)

A14· fA13· A12)

PB3 = fOD = f(AI5· A14 ° fA13· A12 +
fA15· A14· A13· fA12 + fA15· A14·
A13· A12)
PB4 - PB6 are used as chip selects for
each of the three peripherals and are
simply decoded from the address inputs by
PAD B corresponding to the address
ranges listed in Table 2. These equations
are listed below:

Conclusion

PB4 = fPERl CS
fA13 o A12)

= f(A 15 • A 14 •

PB5 = fPER2CS
A13· fA12)

= f(A15 ° A14·

PB6 = fPER3CS
A13 o A12)

= f(A15 ° A14 °

The PSD device may be used in a variety
of applications requiring the simplicity,
space savings and performance possible
by the integration of memory and
programmable elements. But a significant
portion of the value of the PSD device, is
its ability to absorb much of the logic
functionality which normally surrounds a

Finally, PB7 is used to perform the bus
sizing function. It should be sized to eight
bits whenever any of the external peripherals is accessed. It should be sized to 16
bits for all other accesses. The 80C196KB
requires a high on the BUSWIDTH input for
16-bit operation and a low for 8-bit operation. This is accomplished by the equation
below:
PB7 = BUSWIDTH = f(A15 ° A14· A13 +
fA15· A14· fA13· A12)
This completes the equations for Port B.
These equations are entered in the Maple
software by selecting the Port B chip select
definition screens as described in the previous example and entering 1's and O's in the
appropriate locations. Remember that don't
cares (X's or blanks) must be entered in all
inputs which are not used by a particular
equation.
Finally, we must enter the memory map
into Maple Address Map screen. This is
performed as in the previous example by
entering 1's, O's or don't cares in the appropriate places.

microcontroller application. The
programmability of the device allows the
designer to make changes to both the
software and the design itself as required.
This is not possible with masked ROM or
ASIC-based designs. The PSD device can
truly turn a microcontroller into a complete
two-chip solution.

-------------------------------------~~~Ar-----------------------------------2-326

Programmable Peripheral
Application Note 016
Power Considerations In The PSD3XX
By Jeff Miller

Introduction

The PSD3XX is a configurable microcontroller peripheral integrating programmable
logic, EPROM and SRAM technologies into
a single piece of silicon. It has been used
extensively in microcontroller applications
around the world by virtue of its high level
of integration, configurability and ease of
use. This integration makes possible the
design of very compact microcontroller
systems, enabling the user to squeeze a
great deal of functionality into a very small
space. Thus, the PSD3XX has found its
way into many small hand-held and/or
battery operated applications such as cellular phones, medical instrumentation and
laptop or notebook computers which
usually require, in addition to small space,
a very low power consumption.
The PSD3XX family is based on a patented
high-performance CMOS technology and,

Power Use
In The PSD3XX

The PSD3XX contains several modules
internally, each of which can be considered
a power consumer when in operation.
These modules include the PAD,
(Programmable Address Decoder)EPROM
and SRAM blocks. The key to reducing the
power used by the PSD3XX is to reduce
the power used by each of these modules
individually.
Under normal operation, several of the
functional modules may be operating, while
others may be standing by. A module in
stand by uses much less power than one
that is active. For example, whenever the
SRAM is not being actively used, it is
disabled and therefore consumes less
power. This is also true of the PAD. A PAD
term which is active expends more power
than one which is inactive. This would also
be true of the EPROM. However, in some
PSD3XX models, the EPROM is always
active, in which case it will always draw
power. This is done in order to provide the
best access time possible for the EPROM.
The Low Power family of PSD3XXs does
not keep the EPROM enabled at all times,

like other CMOS devices, requires very
low power consumption even when no
particular effort is made to minimize the
PSD3XX power. But, when some special
care is taken during the programming
and configuration of the device, power can
be reduced even further, making the
PSD3XX even more valuable in these
power-sensitive applications. This application note will describe the methods which
can be used to reduce the PSD3XX power
consumption in both active and stand-by
modes. It makes sense to use some of
these techniques even when low power is
not a primary design requirement since
they are easy to implement and require no
additional expense. We believe that proper
implementation of the material in this note
will make the PSD3XX an invaluable
member of any low-power microcontroller
system.
and thus the designer can save power by
minimizing the time during which the
EPROM is accessed. Use of this feature
does impact the speed of the PSD3XX
EPROM, which results in the loss of the
120 ns speed grade. There are other
methods of reducing EPROM power even
when the EPROM is enabled. These will
be discussed in detail later in this note.
When the time that each PSD3XX function
is kept in standby mode is maximized, the
power expense is minimized.
There is a way to place the entire PSD3XX
into the standby mode at once, thereby
reducing power usage to the bare
minimum. This can be done through the
use of the CSI (Chip Select Input) pin.
When the PSD3XX is deselected by the
CSI pin, the entire part enters the standby
mode using only about 50 IlA of current.
While in this mode, the PSD3XX is incapable of performing any functions, including PAD logic equations, but this is an
excellent method of reducing system
power in deSigns which have low active
duty cycles.

2-327

•

PSD3XX - Application Note 016

CMOS
Power
Characteristics

As a CMOS part, the PSD3XX behaves in
the same way as other CMOS devices in
terms of power dissipation. The PSD3XX
consumes the most power when the
temperature is low, the voltage is high and
the frequency is high. Low temperature in
CMOS devices, unlike in bipolar devices,
causes the transistors to speed up, thus
consuming more power. Therefore, if the
system will never operate in low
temperature environments, power
dissipation will be lower. Another result of
this characteristic is that CMOS parts do
not generally experience thermal runaway.
As temperature increases, the power
expended by the CMOS device decreases,
thus the part tends to effectively cool itself
off.
Another characteristic of CMOS devices is
the effect of voltage variations. CMOS
behaves similarly to TTL devices with
respect to voltage. When input voltage

rises, the current drawn by a CMOS device
also rises. As input voltage falls, input
current also falls. Thus, the CMOS device
will draw the least current at its lowest
allowable supply voltage. This voltage is
4.5V in the PSD3XX. Taking the voltage
below this level will generally slow the
device down to below its specified speed
as well as jeopardize its data retention
capability. Between 4.5 and 5.5V, the
PSD3XX varies by about 0.85mA per 0.1 V
variation. Thus, the PSD3XX will draw
approximately 0.85 mA less current at 4.9V
than at 5.0V Vcc.
Lastly, frequency of operation plays an
important role in the power dissipation of a
CMOS device. A CMOS gate expends the
greatest power while it is switching
between the logic 0 and logic 1 states, or
vice versa. This can be easily understood
when looking at the circuit diagram for a
typical CMOS output shown in Figure 1.

Figure 1.
Typical CMOS
Output Circuit
.......- - - 1 t - - -

The circuit above represents a typical
CMOS inverter output. Normally, either the
top transistor is off (output = logic 0) or the
bottom transistor is off (output = logic 1).
MOS transistors have very low leakage
currents which means that under these
normal conditions, very little current will be
passing from Vcc to ground~ However,
when the input to the inverter is switching,
both transistors will not switch from their
present conditions to their new conditions
at precisely the same instant. Therefore,
both transistors will be on for a very brief
instant during the transition. During this
time there is a low impedance path from
Vcc to ground and some current is drawn
by the circuit. In addition, the output will
have some load capacitance (C l )
which must be charged during switching,

OUTPUT

even if the load itself draws little or no
static current. Thus, during the switching
process the power expended by a CMOS
device is at its highest.
The switching current drawn by the device
is dependent on the number of times the
outputs are forced to switch logic states in
a unit of time. Therefore, the frequency of
operation of the part directly influences its
dynamic power consumption. The lower
the operational frequency, the low~r the
dynamic power expended by the device. In
the PSD3XX, frequency of operation is
determined by the rate at which the
addresses are changing, usually indicated
by the frequency of the ALE or AS signal.
Generally, the PSD3XX draws about 3 mA
of additional current for each 1 MHz added
to the frequency of operation.

-------------------------~Jr;------------------------2-328

PSD3XX - Application Note 016

Power
Management
Techniques
In The PSD3XX

The above mentioned features and characteristics can be used to the designer's
advantage when designing compact microcontroller systems which have a tight
power budget. In the sections that follow,
several methods for reducing the PSD3XX
power will be presented.

the PSD3XX should be placed in the
power down mode (CSI inactive) to reduce
the PSD3XX current down to its standby
value.
The PSD3XX must also be awakened
when the microcontroller is awakened so
that it may provide an instruction to the
controller when it requires one. If the
microcontroller itself has a chip select
output, like the Motorola 683XX series
controllers, it may be used to awaken the
PSD3XX as necessary. However, if it does
not, there will be a problem. If the microcontroller itself is used to power down the
PSD3XX, through an I/O port pin for
example, there will be no way to power up
the PSD3XX again since the PSD3XX
itself contains the instruction that the
microcontroller must use to activate the
CSI signal to awaken the PSD3XX. The
way to correct this situation is to design a
circuit which detects when the microcontroller is coming out of its power down
mode before it must fetch the first instruction. Such a circuit is depicted in Figure 2

Power Down Mode
Many system designs do not require the
microcontroller, and therefore the PSD3XX,
to operate continuously. Systems, like
cellular telephones and notebook
computers, spend a large amount of time
inactive - waiting for something to happen
like a press of a button or keyboard. During
this time, many designers place the microcontroller into a low power idle or sleep
mode. In the sleep mode, the controller
expends significantly lower power. The
microcontroller is usually awakened by
some event - a key on a keypad being
pressed, for instance, which may result in
an interrupt. There is no need for the
PSD3XX to be active during the time that
the microcontroller is not active. Therefore,

Figure 2.
Simple Power
Down Circuit

Voo

R
PSD301

68HC11

74ACT05

E

V--

--CSI

fC
-

=

In this circuit diagram, a Motorola 68HC11
microcontroller is connected to a PSD3XX
in a low power system. The circuit functions
quite simply. The E signal from the HC11 is
normally a free running clock at 1/4 the
frequency of the input clock. When the
HC11 is placed into the sleep mode by the
software (by executing the STOP
instruction), the E signal stops oscillating
and remains low until an interrupt or
internal timer event occurs. After the
='~==

interrupt has been received by the
controller, the E signal resumes toggling,
but there will be a minimum of two E
clock cycles prior to the first AS. This
characteristic can be used to place the
PSD3XX into its low power standby mode
whenever the STOP has been executed in
the HC11 and to awaken it before it must
supply an instruction to the HC11.

4::1#

---------------------~sf'~--------------------

2-329

•

PSD3XX - Application Note 016

Power
Management
Techniques
In The PS03XX
(Cont.)

capacitor to slowly charge up to a logic one
level which then places the PSD3XX into
the standby mode in which it will consume
only about SOIlA of current. After the
controller exits the sleep mode, the E signal
will resume oscillating which rapidly
discharges the capacitor. This, in turn,
activates the CSI input to the PSD3XX,
bringing it out of the power down mode.
Since the E signal will oscillate for at least
two full cycles before the first AS strobe
begins a new bus cycle, the PSD3XX will
have ample time to recover from the power
down mode before having to supply an
instruction to the HC11 for processing. In
operation, the circuit results in a timing
diagram similar to the one in Figure 3.

The ACTOS device shown in the diagram is
simply an open collector inverter. When the
E signal is oscillating, the output of the
inverter will be toggling between ground
and high impedance. When the output is at
ground, the capacitor will rapidly discharge
from its present state into the ACTOS.
When the output is high impedance, the
capacitor will slowly charge up to Vee
through the resistor. Thus, under normal
operation the CSI input of the PSD3XX will
be at or near 0 V, provided the RC time
constant is large enough to prevent the
capacitor from charging up beyond a logic
zero level of 0.6 V.
When the HC 11 enters the sleep mode the
E signal remains low. This enables the

Figure 3.
6BHC11 Stop
Timing

RECOVERY

STOP ACTIVE
E

A similar circuit can be used for Intel 8031
type controllers. Controllers conforming to
the Intel 8031 family generally have two
low power modes: IDLE and POWER
DOWN. The IDLE mode causes the
controller to cease instruction execution,
but its internal clocks continue to run. This
saves significant power while leaving the

Figure 4.
B031 Idle
Circuit

internal timers and other functions operational. When in the IDLE mode, both the
ALE signal and the PSEN signal are held
high. A circuit similar to the one illustrated
for the 68HC11 may be used to detect the
end of oscillation on the ALE signal. This
circuit is shown in Figure 4.

Voo

R

80C31

ALE

~

74ACT09

PSD301
CSI

Ie
-=-

!FSEIi6=

~2~-3~3~O~-------------------------------~~Jf-------------------------------------

I'SD3XX - Application Note 016

Power
Management
Techniques
In The psoaxx
(Cont.)

Figure 5.
B831ldle
Timing

The circuit operates on the same principle
as the one used earlier for the Motorola
processor. The ALE signal normally
oscillates high for 2 clocks out of every 6 or
12 clocks, depending on whether
instruction or data accesses are being
performed. The software places the 8031
into the Idle mode by setting bit 0 in the
PCON register. Once set, the ALE and
PSEN signals remain high until an interrupt
or hardware reset occur. During this time,
the CSI signal will float high with the RC
circuit, as in the earlier example. The

ACT09 is simply an AND gate with an
open collector output. It performs the same
function as the inverter in the previous
example without inverting the signal. When
an interrupt or reset is received, the ALE
signal begins to toggle again, but at least
two "dummy" unused ALE cycles will occur
before the first meaningful instruction is
fetched, giving the PSD3XX time to
recover from the power down mode. The
timing for the above circuit is shown in
Figure 5.

•

ALE
CSI

If the system requires truly the lowest
power available, the 8031 POWER DOWN
mode may be used. This disables all
intemal operations of the 8031 as well as
the extemal ones. Thus, anyon-chip
peripherals like timers and serial communication links will be disabled. This places the
controller into its lowest power mode
possible. Software may place the 8031 into
the POWER DOWN mode by setting bit 1
in the PCON register. When execution of
the instruction is complete, the ALE signal
will be driven low and will remain in this

state until a hardware reset or an interrupt
is received. Thus, a circuit similar to the
one above may be used to detect the static
condition of the ALE signal, but an
inverting gate must be used instead of the
ACT09 (such as the ACTOS used in the
Motorola example earlier).
If both the POWER DOWN and IDLE
modes must be used, the gate may be
replaced with an ACT266 exclusive NOR
with an open collector output. This circuit is
shown in Figure 6.

Figure 6.
B831 Power
Oownorldle
Circuit

80C552

110 BIT

PSD301

)0---+----/ CSI
1...-_ _ _ _---1

74ACT266

-------------------------~Jr;----------------------~~
2-331

I'SD3XX - AppllcatlDn NDte 016

Power
Management
Techniques
In The PSDaXX
(Cont.)

The I/O bit can be provided by either the
PSD3XX or the controller itself. If the
controller is used to provide the I/O bit, it
must hold the correct value on the output
even when in the idle or sleep mode, as the
PSD3XX does. When the I/O bit is low, the
POWER DOWN mode is enabled (a low on
ALE and a LOW on the I/O bit will result in
a high on CSI). When the I/O bit is high,
the IDLE mode is enabled (a high on ALE
and a high on the I/O bit will result in a high
on CSI).
For all of the above circuits to operate
correctly, the value of the RC network must
be carefully calculated to insure proper
operation in the normal mode. This means
that under normal operation, CSI must
never climb above 0.4 V, which will
guarantee that it is always recognized by
the PSD3XX as a low.
For example,the 68HC11 circuit shown in
Figure 2 used the E signal from the
controller to disable the PSD3XX. The E
signal oscillates at 1/4 the frequency of the
HC11's input clock. If an 8 MHz HC11 is
used, the,E signal will oscillate at2 MHz.
This results in an E signal clock period of
500 ns. During this 500 ns the E signal will
be low for 250 ns. Thus, the RC network
must be chosen to prevent the CSI signal
from climbing above 0.4 V for at least
250 ns. The equation below governs the
voltage across the capacitor (Vd, and thus
the voltage present on the CSI pin:
Vc=Vcd1-e-VRC)
where Vc is the voltage across the
capacitor (which is the same as the CSI
pin), Vcc is the supply voltage, and t is the
time in seconds after the output of the open
collector gate switches from a low to an
open circuit. Solving for RC we get:
RC = -Vln(1-VcfVcd
In order to determine the minimum values
for Rand C, we must solve this equation
for the point of time which is of interest. We
must have Vc no greater than 0.4V at time
t = 250 ns. Thus, with Vcc = 5 V,the
equation may be rewritten as follows:

An acceptable RC network for this case
might be a resistor of 100KQ and a
capacitor of 30pF. These values will
provide no margin for the circuit so some
additional resistance or capacitance may
be desired. Of course, larger values may
be used without harming the circuit, they
will just cause the low power mode to be
entered more slowly. The case of leaving
the low power mode is less critical, since
the capacitor will discharge more quickly
through the gate than it will charge up
through the resistor. In the interest of
minimizing power use by the circuit itself, it
is best to use a larger resistor value and a
smaller capacitor value, since this will
cause less current to be sunk by the gate
which drives the circuit.
Using this equation, it is possible to
determine the RC value required for any
controller and/or frequency. It is only
necessary to determine the length of time
that the RC will be required to hold the CSI
signal below 0.4 V and plug that value into
the above equation.
If a more deterministic method is desired
for placing the PSD3XX in the power
down mode, a fully digital circuit may be
implemented which uses very few additional components. This circuit is shown in
Figure 7 for the 68HC11 controller.
This circuit performs the same function as
the RC circuit described earlier, but does it
digitally. The 74ACT164 is a shift register
which is used in this example to detect
when eight HC11 input clocks occur while
the E Signal remains low. In normal
operation, no more than two clocks should
occur without E transitioning from low to
high, thus providing a clear to the ACT164.
If the HC11 is stopped, the E signal will
remain high until an interrupt is received,
but the input clock continues to run freely.
Thus, the shift register will shift in "one's"
until the E signal goes high again. When
the ACT164 has shifted eight times, the
CSI signal will go high, placing the
PSD3XX into the power down mode. The
timing diagram corresponding to this circuit
is shown in Figure 8.

RC = -250 x 1O-9/ln (1 - 0.4/5.0) =
3.0 x 10-6
~~

2-332

_______________________

__________________________

rl~E

~LI

I'SDaXX - ApplicatiDn NDte 016

Figure 1.
Digital Sleep
Circuit For
68NC11
74ACT164

A
B

ClK
68HC11A1

Figure 8.
68NC11 Stop
Mode Timing

QH

CSI

PSD301

74ACT04

STOP ACTIVE

RECOVERY

ClK
E

+-____________

CSI ____

Power
Management
Techniques
In The PSD3XX
(Cont.)

~

A similar circuit may be used for the 8031
family of controllers, and is depicted in
Figure 9.
This circuit, like the others, detects when
ALE stops toggling. Since up to 10 clocks
may normally occur without an ALE pulse,
a counter which can count to at least 11 is
required in order to function properly. Thus,
an 8-bit shift register like the one used with
the HC11 will not work. In this case, a
74ACT191 is used to count 16 clocks prior
to raising its MAXIMIN output high. A low
on the ALE signal will load zero's into the
counter and clear the MAXIMIN output. The
MAXIMIN output is also used as the

counter enable to prevent the counter from
counting further after attaining the count of
16. The circuit shown will function with the
IDLE mode of the 8031. If the POWER
DOWN mode is used, an inverter must be
inserted in the ALE signal path.
Other controllers, not listed here, may also
have power down modes which may function with these circuits. Any controller which
has some sort of external indication when
the power down mode has been entered
may usually be used to place the PSD3XX
in its low power mode also.

------------------------~Jr;-----------------------2-333

PSD3XX - Appllt:lltiOR Note D16

Figure 9.
Digital Sleep
Circuit for
8031 Family
74ACT191
ClK

A
B

80C31

Power
Management
Techniques
In The PSD3XX
(Cont.)

C 't,~~
D
ALE 1---1---1 lOAD
DIU
CTEN

PAD PrDgramming Techniques
The preceding section has described
methods of using the power down
capability of the PSD3XX with several
microcontrollers. There are also techniques
which may be utilized during programming
of the device to further reduce power.
These techniques can significantly reduce
the power expended by the PSD3XX when
it is in full operation.
The programmable logic section of the
PSD3XX, called the PAD, provides much of
its great flexibility and configurability. It is
used to control the internal resources of the
PSD3XX and can also be used to control
external resources as well. The power
use of the PAD varies greatly depending
on how its product terms are programmed
and used.
The PAD is illustrated in Figure 10. It is
divided into two sections, called PAD A and
PAD B. PAD A is responsible for generating
the control and selection for the internal
resources of the PSD3XX and utilizes 13
product terms to perform these functions.
PAD B provides any external chip selection
and logic replacement that is necessary for
the system and has 27 product terms for
this purpose. A single product term is
functionally illustrated in Figure 11.

CSI

PSD301

Each of the PAD inputs and its complement
is available to each of the 40 product terms
of the PAD. Each of these inputs is
connected to an n-channeltransistor which
is used to connect the entire line to ground
when the input is in the appropriate state. A
high on the input to the gate causes the
transistor to turn on. When the device is
programmed, each of these transistors may
be left in place or may be functionally
removed (programmed out) from the circuit.
If all of the transistors are programmed out,
the line is left connected only to the pull-up
resistor which makes it always high. Thus,
the output of the inverter is always low. If
an equation such as:

ICSx = In#1 • Iln#2
is programmed into the PAD, the output
CSx must be high except when In#1 is high
and In#2 is low. Thus, all of the transistors
are programmed out except the ones
connected to In#1 and In#2. This means
that unless In#1 is high and In#2 is low,
there will always be at least one of the two
remaining transistors turned on, which in
turn results in the CSx output being high.
When the appropriate input condition is
met, the remaining two transistors will turn
off, which allows the output to become low.

-------------------------~Jr;------------------------2-334

PS03XX - Application Note 016

Figure 10.
PAD
Illustration

~J~~~~tttta~~~j~lE~ i i
ES4

~::~~~~~ififtt~~~~~~ESS

l

8 EPROM Block
Select Lines

ESG
ES7
RSO - - SRAM Block Select

A19

1

PAD A

~:]~Jjjjjjjiil~§ g~~g~UT1}

CSIOPORT-I/O Base Address
Track Mode
CSADOUT2
Control Signals

----~CSO/PBO

Ala

•

CS1/PBl

CS2/PB2

A16

CS3/PB3

A15

CS4/PB4

PADB
CSS/PBS

CSG/PBG

A12
CS7/PB7

CSB/PCO
CS9/PCl

..

Figure 11.
Product
Term
Functionality

Vee

IN #1

CS10/PC2

IN #2

IN#n

CSx

________________________________________ fAfaraFE _________________________________________
~#;

2-335

PS03XX - Application Note 016

Power
Management
Techniques
In The PSD3XX
{Cont.}

As can be seen in the figure, the product
term expends very little power when all of
the transistors are either programmed out
or turned off. The only power used in this
case is the result of the leakage current
through the various off transistors, which is
very low in CMOS technology. When one
or more of the transistors is turned on
there will be current drawn through th~ pullup resistor to ground. Therefore, the power
used by a product term varies greatly
according to the way it is programmed.
Experimental data has shown that a
product term with all of the transistors
programmed out draws approximately
380llA less current at room temperature
and 5.0 V Vcc than a product term which
has some active transistors. WSI's MAPLE
software packages take advantage of this
fact to reduce power as much as possible.
When the user intends to use some or all of
the Port 8 pins as I/O signals, then they are
not connected to the PAD in any way.
Thus, the MAPLE software is free to
program the unused PAD 8 product terms
in any way. In MAPLE versions 4.038 and
subsequent, the software automatically
programs out all transistors in each unused
product term, which can eliminate up to 24
product terms for Port 8. This results in a
power reduction of up to 9.1 mA.
If one or more of the Port C pins is
programmed as an address or logic input,
MAPLE is free again to program out all of
the transistors in each unused PAD 8
product term dedicated to Port C. This can
eliminate up to 3 additional product terms
resulting in a power reduction of over 1 mAo
Finally, there are three product terms from
PAD A which are dedicated to controlling
the Port A Track Mode operation. If the
Track Mode is not used in the application,
these product terms may also be
eliminated by MAPLE for a power reduction
of over 1 mA.
The remaining ten product terms are the 8
EPROM select lines, the SRAM select line
and the 1/0 port select line. These terms
may not be eliminated by MAPLE without
disrupting the operation of the device. But
in a system which uses Port A and Port 8
as 1/0 or address outputs, and Port C as
address or logic inputs, the total system
power saving is 10.2 mA typical.

The same methods may also be used in
non-multiplexed microcontroller
applications. In this case, Port A and Port 8
may be used as microcontroller data input
pins, depending on whether the controller is
8- or 16-bit. As in the earlier cases, if the
ports are used as data input pins, they are
not connected to the PAD which allows
MAPLE to program out the appropriate
product terms.
Again, MAPLE 4.038 or a subsequent
revision must be used to obtain this
capability. If your software is an older
revision, contact your local WSI regional
sales office for a free update.

EPROM Programming Techniques
Like the PAD, the EPROM in the PSD3XX
uses varying amounts of power depending
on how it is programmed. When
programmed to a one, an EPROM bit
draws more current than when
programmed to a zero. Thus, for minimum
power usage it is best to have the majority
of the EPROM programmed to zeros.
Unfortunately, the contents of the EPROM
are fixed by the program and data
requirements of the system and thus
cannot be easily optimized for power.
However, the user can program all unused
sections of the EPROM to zeros. This will
not substantially cut the power used by the
PSD3XX under normal operation when
EPROM accesses are being performed, but
it will reduce the power consumption during
periods when there is not a valid address
on the bus because these invalid
addresses will often point to unused
EPROM locations. When an EPROM
location is currently addressed, it is
expending power even if the RD or PSEN
signals are not actually enabling an output.
Therefore, it is best that unused EPROM
locations be filled with zeros so that power
is minimized during these periods of invalid
addresses. It should be noted that all power
figures used in this application note as well
as those specified in the PSD3XX data
sheet are based on an average of 50%
"ones" and 50% "zeros" contained in the
EPROM. An EPROM location programmed
to "ones" will draw approximately 1.5 mA of
additional current over an EPROM location
programmed to "zeros".

~2~-3=3=6~---------------------------------~~~--------------------------------------

PS03XX - Application Note 016

Power
Management
Techniques
In The PSD3XX
(Cont.)

An even better way to help minimize power
usage is to control the addresses which
appear on the bus when there is no valid
address being driven by the microcontroller.
The least power expense will be when this
unused address points to an area which
has no PSD3XX resource mapped into it.
This will result in no internal resource block
receiving a chip select and thus the least
amount of current will be drawn. The next
best approach is to have the unused
address point to an EPROM area
containing zeros. The next lowest power
would be to have the unused address point
to an EPROM area containing something
other than zeros. Finally, the highest power
will occur when the unused address points
to an SRAM location.

Since there is not much that can be done
about the address that is appearing at the
output of the microcontroller, the best that
can be done is to know what address the
controller will have active on its bus at
various non-operational times and insure, if
possible, that the PSD3XX's address map
maps that address into a desired range of
memory (preferably no memory at all). This
will truly minimize the power expended by
the PSD3XX during these times.

Summing
It All Up

After taking all of these factors into
account, what kind of power use can you
expect from the PSD3XX in your own
system? As a guideline, we will calculate
the typical power required of a PSD3XX
installed in a hypothetical system. The
requirements of this system are listed in
Table 1.

and temperature conditions specified. The
base power of the PSD3XX is the power
used by the PSD3XX when only the
product terms which control the EPROM,
SRAM and I/O ports are not programmed
out (10 active product terms). The base
power also assumes that no internal
resources (EPROM, SRAM and I/O ports)
are being currently accessed. The current
drawn by the PSD3XX under these
conditions has been determined
experimentally to be 16 mAo To this current,
we must add additional current for the other
active product terms, SRAM access and
EPROM access.

Using this information, we can calculate
the approximate typical power
requirements of the PSD3XX. Before we
can begin, we must know what the base
power of the PSD3XX is under the voltage

Table 1.
Hypothetical
System
Requirements

Characteristic

SpeCification

PSD3XX Operational Frequency

2 MHz

Port A

Address Output

Port B

4 Chip Select, 4 I/O

Port C

Logic inputs

CSI

Configured for Auto. Power Down
5.0 V

Vcc
Temperature

...

25°C

Standby duty cycle

60%

EPROM duty cycle

30%

SRAM duty cycle

10%

- ------------------------------------••
-~€_-----------------------------------fill;
2-337

•

I'SD3XX - Application Note 016

Summing
It All Up
(Cont.)

The system is requiring only four of the 11
available chip select outputs. Therefore,
most of the PAD B product terms may be
programmed out. To determine how many
product terms we will be using, we must
look at the equations for the four chip
selects. Assume that the following equations are to be used:
/CS#1 =/(A15· A14· RD + A13· A12· WR)
/CS#2 = /(/A18 + /A17)
/CS#3 = /(A16· A18 + A17· ALE)

as logic inputs (A16, A17 and A18) and
therefore cannot be used as chip selects.
Since the rest of the Port pins are not used
as PAD outputs, the MAPLE software will
automatically program them out.
If we do configure the chip selects to output
on PB[0:3], we must add 8 product terms to
the 10 used in calculating the base power
number. Using the current per product term
of 380/lA provided earlier, eight additional
product terms result in an additional 3.0 mA
of current.

/CS#4 = A17
In order to configure the system for the
lowest power usage, we must be sure that
we place these chip selects on the output
pins which will require the minimum
number of product terms to remain
active. Since the maximum number of
product terms required to generate the
above equations is only two, there is no
need to place these chip selects on Port B
pin 0,1,2 or 3 since these pins each have
four product terms. The lower power
configuration would place these chip
selects on Port B pin 4,5,6 and 7, where
only two product terms will be drawing
power for each chip select. One of the
above chip selects, #4, actually requires
only one product term, meaning that it
could be placed on one of the Port C pins
which have only one product term.
However, all of Port C is used in this case

Table 2.
Summary of
PSD3XX Current
Usage In
Hypothetical
System

Experimental data has shown that
accessing the SRAM results in an
additional current expense of 31 mA above
the base current. Also, accessing the
EPROM draws an additional 0.5 mA over
the base current. The standby current has
been measured at 50 /lA. Finally, we must
consider the additional current used by the
frequency of operation. This is 3 mA per
1 MHz for a total of 6 rnA, since the
PSD3XX will be operating at 2 MHz. This
provides us with all of the data that we
need to calculate the total power usage of
the PSD3XX in this system.
Table 2 can be used to calculate the
EPROM access current, the SRAM access
current and the standby current.

Current Used

PSD3XX Block
Base Configuration

16mA

PAD (as configured)

3.0mA

EPROM

0.5mA

SRAM

31 mA

Frequency Component

6mA

Standby Current

50/lA

Now, summarizing further, the total
EPROM access current is:
Base Current + PAD Current + EPROM
Current + Frequency Component
= 16 mA + 3.0 mA + 0.5 mA + 6 mA
=25.5 mA

J--_.E

The total SRAM access current is:
Base Current + PAD Current + SRAM
Current + Frequency Component
= 16 mA + 3.0 mA + 31 mA + 6 mA
=56.0mA

-2--3-3-8-------------------------------~~;----------------------------------

PSD3XX - Application Note 016

Summing

All"

It
(Cont.

Now we must account for the duty cycle of
the system to determine the total average
power for the PSD3XX. In order to apply
the duty cycle, we simply multiply each
power component by its duty cycle and add
them all together. The equation to perform
this is given below:
Total Current
+ 0.1 (isRAM)

= 0.6(iSBY) + 0.3(iEPROM)

The average current drawn by the PSD3XX
under the specified conditions of
configuration, frequency and environment
is therefore 13.3 mAo The peak typical
current used by the PSD3XX is 54 mA
while the SRAM is being accessed. The
minimum current is 50 !lA, drawn by the
PSD3XX while it is in the Power Down
mode. This compares very favorably with
the typical current usage of a fully discrete
solution.

where iSBY is the standby current, iEPROM is
the active EPROM current and iSRAM is the
active SRAM current. Plugging in the
numbers we developed earlier, the equation
becomes:
Total Current = 0.6 (50 !lA) + 0.3
(25.5 mAl + 0.1 (56.0 mAl = 13.3 mA

Typical VS.
Maximum
Current

The typical and maximum current numbers
are both specified by most integrated circuit
manufacturers. Many designers are unsure
of what these parameters are and how they
relate to the power which will actually be
dissipated by the system. This is
compounded by the configurability of the
PSD3XX.
The maximum power numbers published in
most product specifications are usually
chosen as the number which will never be
exceeded by the device under any
circumstances, including variations in
processing, Vee and temperature. To truly
be a maximum number, all three of these
parameters must be at their worst cases
simultaneously, which is quite unlikely.
Therefore, power use will more likely follow
the typical values when the system is
actually running.
In the PSD3XX data sheet published by
WSI, two current values are published for
typical conditions and another two are
published for worst case conditions. These
two sets of numbers are used to specify
current use in two different PSD3XX
configurations. The lower numbers
represent the current drawn by the
PSD3XX while configured with 10 active
product terms. To arrive at the maximum
value for this configuration, we assume that
the programming of the device has not
changed, but we take the temperature,
voltage and processing to their worst case

conditions. These numbers are generated
again for the configuration of the PSD3XX
which has all 40 product terms active. To
determine the typical current drawn by the
PSD3XX in your system, it is best to use
the techniques presented in this application
note. All of the typical current values used
in this note are the result of careful experimentation, and should parallel very closely
the values measured in your own system.
To extrapolate the worst case current for
your configuration from your calculated
typical value, you must add about 50% to
account for voltage, temperature and
process variation.
When calculating the worst case current for
your entire system it is usually best to use
the typical current numbers for all of the
components installed and then apply some
margin to allow for worst case conditions.
This is much more accurate than using the
worst case parameters for each
component since it is extremely unlikely
that a/l of the components used are
simultaneously at their worst case process
parameters, though they may all be at
worst case voltage and temperature.
Usually 20% margin above the typical
numbers will sufficiently cover the worst
case for the entire system.
Table 3 summarizes the typical current
numbers for the PSD3XX which can be
used when calculating the current used in
your own system.

---------------------------------------rAf~~~-------------------------------------i!!7-!EE!!F IE

2-339

•

PSD3XX - Application Note 016

Tab/e3.
Summary of

PSD3XX

Typica/
Current
Usage

Base Current (10 product terms, SRAM and EPROM Unselected)
Additional Current per Product Term
Additional Current for SRAM Access

31 mA

Additional Current for EPROM Access

0.5 mA

Additional Current for Frequency Effects
Additional Current for Voltage> 5V
Standby Current

Conclusion

16 mA
0.38 mA

3 mA/MHz
0.85 mAIO. 1V
50/-lA

The PSD3XX is a very important device in
the design of compact, low-power systems.
It provides a cost effective minimum part
count solution for a typical microcontroller
system. It also provides a very low power
solution for those designs which are
handheld and/or battery operated. As the
PSD3XX family grows and evolves, more

iiE. JiFE

innovations will be presented in terms of
integration and power usage. The new low
power PSD3XX family will be introduced
soon, providing the designer with an even
lower power solution. Until then, use of the
techniques described in this note will
provide a minimum power solution for your
microcontroller system.

-------------------------------------ULB~.------------------------------------

2-340

.... _""' ..

Programmable Peripheral
Application Note 018
Security of Design in the PSD3XX
By Dud; MDran

Introduction

The PSD3XX is a family of field programmable and UV erasable microcontroller
peripherals that have the ability to interface
to virtually any microcontroller without the
need for external glue logic.
Any PSD3XX family member is a complete
microcontroller peripheral solution with
Memory (EPROM, SRAM), Logic, I/O Ports
and a Security bit on chip.
In today's competitive business environment, where the cost of the product and its
quick introduction to market are the most
important factors for success, some
companies tend to copy a competitor's
design. By doing so, they can save
development time which can reduce their
engineering cost and eventually reduce the
product's price and its introduction time to
the market.

Ussofthe
Security Bit

Since the PSD3XX is a field programmable
device, its contents may be read by an I.C.
programmer, decompiled and copied by a
competitor.
Obviously, it is an undesirable situation for
the EPROM, PAD and configuration data of
the PSD3XX to fall into the hands of a
competitor. To prevent this, the PSD3XX
device implements a security "fuse" or
programmable bit feature to protect its
contents from unauthorized access and use
by a competitor.
Uploading the programmed data from
EPROM, PAD, ACR and NVM port configuration sections of a secured PSD3XX
device is disabled by the security bit
(if turned ON). The RAM of the programmer
(after trying to upload a secured PSD3XX
device) will contain invalid random data.

This is true mainly for the consumer and
commodity product markets where microcontrollers are widely used. The PSD3XX,
as the primary microcontroller peripheral,
contains all the important code and
architectural data that a potential competitor
may want to copy.

A secured PSD3XX device will function
properly in the system - the microcontroller
will be able to access the EPROM, SRAM,
PAD and the I/O ports but any attempt to
read or verify the contents of a secured
PSD3XX by external hardware will fail.

PSD3XX devices contain non-volatile
configuration bits to enable the user to set
and configure the device to the proper
operational mode. The configuration bits will
configure the device to interface successfully with the microcontroller and also
configure the PSD3XX I/O Ports. The
configuration bits are programmed during
the programming phase and cannot be
accessed in operational mode.

2) The NVM section of the PSD3XX device
contains port configuration bits for proper
set up of Ports A, Band C.

During programming the configuration bits
are programmed as two separate sections:
1) The ACR section of the PSD3XX device
contains global configuration bits for
proper microcontroller interface. The
security bit resides as an individual
configuration bit in the ACR section of
the device.

PSD3XX devices use the security bit to
prevent unauthorized access to the
configuration data inside. Since the security
bit is part of the ACR global configuration
bits section, it can be programmed in the
same manner as all other configuration bits.
All ACR and NVM configuration bits of the
PSD3XX are non-volatile, so their contents
will not be erased or corrupted during the
power down mode of the device (when the
PSD3XX is deselected with CSI/A19 =
High) or during power down when Vcc is
removed.

2-341

•

I
i

PSD3XX - Application Note 018

Use of the
Security Bit
(Cont.)

The security configuration bit is user
programmable and UV erasable as well, so
a secured part can be erased completely
and be reprogrammed (only if the device is
in a windowed package).
Setting the security bit will lock all the
contents of the PAD, ACR global configuration bits, and NVM port configuration
bits. By setting the security bit the device
cannot be entered into Initialization and
Override mode (resets the device and
enters it to a known default configuration
before activating the individual read mode
for each section). Any attempt afterwards to
enter the device to DIRECT mode for
uploading or programming will fail. Setting
the security bit prevents a programmer from
directly accessing the various sections of
the device.

setting the security bit, it is impossible to
read them by using external equipment
(except by the microcontroller in the system
where the PSD3XX designed in). This is
because the external equipment will lack
information about the address mapping of
the eight EPROM blocks, SRAM and I/O
ports in the memory map of the
microcontroller and the unknown status of
the global and I/O port configuration bits.
Even if an unauthorized user figures out the
configuration of the part by knowing what
microcontroller is interfaced (ALE polarity,
what type of read and write signals, etc.)
and gets data out of the PSD3XX (after
applying address and control signals to the
device), the user will have no idea where it
came from: EPROM, SRAM, I/O Port
Register, Page Register, etc. This
effectively renders the data useless.

Even though the EPROM, SRAM and I/O
port contents are not directly disabled by

Setting the
Security Bit

The security configuration bit is called
CSECURITY.

If CSECURITY = 0, it means security is off
(security bit is not set and its value will be '1'
in the object file).
If CSECURITY = 1, it means security is on
(security bit is set and its value will be '0' in
the object file).
Setting the security bit and activating the
security mode can be done in two different
ways:
1) By turning security ON in the configuration menu of Maple development
software.

2) By setting the security in the
programming software (done after the
device is fully programmed and verified).

addresses of the object file created after
compilation. (See Security Bit File Location
section of this document).
If Setting of the security bit is done in the
programming software (Third party programming software or WSI Mappro
programming software), the user should
program and verify the device using a
Maple generated object file (with security
option OFF) and then set the security ON by
using a separate programming software
command.
Some third party programmer manufacturer's software will load the Maple
generated object file but mask the security
bit before programming the device. In that
case the user will have to set the security
bit (if necessary) by using a separate
command in the programming software
menu.

Using Maple development software to turn
security ON gives the security bit the value
'0', and will integrate it in one of the ACR

-------------------------------------[~~~~-----------------------------------2-342

PSD3XX - Application Note 018

Security
Bit File
Location

The object file created by compilation with
Maple software is an Intellntelec format,
compatible file,
The programming algorithm defines the
address scrambling that translates the file
addresses to device addresses (the address
that the device "sees" on its address pins
during programming), By looking at a
screen dump or a hard copy of the object
file the user can determine the status of the
security bit.
The security bit of the PSD301/311 resides
in data bit #1 of file address 81 D3h, This
address contains three configuration bits
that reside in data bits 0 - 2, so this address
in the file can have any value between 0
and 7,
If this address has a value X1 X (where X
can be either 0 or 1), the security bit is off
('1' value means an unprogrammed bit) and
CSECURITY = 0 (displayed by Mappro WSI
programmer interface software as
SECA = 0),
If this address has a value XOX, the security
bit is on and CSECURITY = 1 (displayed

Summary

The PSD3XX family of programmable
microcontrolier peripheral devices provides
security of design not readily available in
conventional PLDs and EPROMs,

by Mappro WSI programmer interface
software as SECA = 1),
The security bit of PSD302/312 resides in
data bit #1 of file address 10253h, This
address contains three configuration bits
that reside in data bits 0 - 3 (bit 3 is
reserved for future usage), This address
can have any value between 0 and F. If this
address has a value XX1 X (where X can be
either 0 or 1), the security bit is OFF
( '1' value means an unprogrammed bit) and
CSECURITY = 0 (displayed by Mappro WSI
programmer interface software as SECA =
0), If this address has a value XXOX, the
security bit is ON and CSECURITY = 1
(displayed by Mappro WSI programmer
interface software as SECA = 1),
If users do not want to look for the security
bit status in the object file, they can cali
MAPPRO programming software from the
main menu of MAPLE, Load the RAM with
the object file and Display the ACR
configuration bits status on the screen,
The value of SECA will indicate the status of
the security bit (SECA = 0 means security is
OFF, SECA = 1 means security is ON),
Though not entirely fool-proof, the security
bit feature helps make it more cost effective
for competitors to design their own
hardware instead of trying to copy systems
that already exist.

-------------------------------------~~~-----------------------------------2-343

•

~~~-------------------------------------------'AfjfjfF~------------------------------------------_____
2-344
__E

Programmable Peripheral
Application Note 019
The PSD311 Simplifies an Eight Wire Cable
Tester Design and Increases Flexibility
in the Process - By Timothy E. Dunavin, Antee - Anixter Mfg.
and Karen S. Spesard, WSI

Abstract

With the ever increasing complexity of
wiring networks and cables to match a wide
variety of computer and telecommunication
systems, a means of testing them becomes
a necessity. The wire tester design
described below is a simple yet effective

design which uses the Motorola 68HC11
and WSI PSD311 pairto create a system
that insures 8-wire cables are wired
properly, and at the same time offers a
substantial increase in design flexibility
over alternative hardware solutions .

Introduction

More and more microcontroller and
microprocessor designers are trying to
design integrated core-based systems with
the intention of being able to easily
configure their systems to fit a wide variety
of product applications. The problem is that
when these applications require new or
changing features such as expanding II0s
or address maps, they may find their
deSigns are not flexible enough to
accommodate the new requirements,
forcing a lengthy and expensive redesign
anyway.

can be re-configured for other applications
using the same core design. Also, the
PSD3XX product family can enhance
microcontroller-based systems in other
ways. For instance, it can improve system
integration resulting in lower system costs,
and it can significantly shorten time to
market resulting in increased revenues and
profits.

A solution to this problem is to design in
user-configurable programmable peripheral
products which are flexible enough to
accommodate future design revisions
without the need for board relayout. The
PSD3XX family from WSI, Inc., fits this
profile exactly in that the products can be
tailored to a specific application and then

The Cable
Tester System
Design

The cable tester described below operates
by sending a known bit pattern through the
cable under test and checking the bit
pattern at the other end. The hardware
configuration utilized to achieve this
function is shown in Figure 1.
Note that there are very few components
overall in the design. The core contains
just the 68HC11 microcontroller from
Motorola, the PSD311 Programmable
Peripheral with Memory from WSI
and a few other key components including
a keypad, LCD display, and an optional
RS232 communications device.

In the cable tester system in which the
PSD311 was used with the 68HC11, the
PSD311 integrates address decoding,
latches, 32K x 8 EPROM, and 2K x 8
SRAM all into a one-chip user-configurable
microcontroller peripheral. It also replaces
the two ports lost by the 68HC11 to extend
program and data memory outside the
MCU with two additional configurable 8-bit
I/O ports, and adds a third 3-bit port, while
easily enabling still further port expansion.

Also note that the interconnections
between the 68HC11 and PSD311 are
direct and require no "glue logic". That
means that no external latches are needed
to demultiplex the multiplexed address and
data bus from the 68HC11. And, no other
external logic is needed to generate the
address mapping for the on-board EPROM
and SRAM and to select external
peripherals, or create the control signal
interface. The PSD311 already
incorporates these features internally,
thereby simplifying the design considerably. In fact, the PSD311's architecture, as
shown in Figure 2, specifically includes
32K x 8 mappable EPROM for program

2-345

•

~

~

~
0)

H;JUl

Figure 1. PSD311/68HC11 Implementation in the Cable Tester Design

,~

"'"

2

U3

:

AD21A2

AD3 1A3
AD4/A4

ADS/AS
AD7/A7

ADS/AS
AD9/A9

HI :~:~;!~;

PB3/All

--,

,l

51

'4

RESET

13
17

3
1

~~Npp
RESET

M/PSEN

A19/CSJ

~

____ .J

12

111111111

W

'"lllhl

!

PSD311

MODA~-~-t--+-~

BZ1

fl~4k~H"-'-c---:-+--~

!;
Ie

EPROM(1) - COOO~FFF
EEPROM - 8BOO-BFFF
EPROM(2) - 6000-AFFF
RAM - 5000-5FFF
PORTS - 4000-4007
LATCH - 2000
RAM - 1000-1 OFF
REG/PTS - 000-003F

MODB~-~-t--+--~

CABLEUNDERTEST
===~~~~~~~~~~~===t====~====~=-~~~
-----------------------------------U5

01
20
02

19

Q3

16

~
!$t
$t14
$!: ,-;;$t

AU1<::lAU

i KEYS

Illiii_:

I

~

.11-1,-

13

AD6/A6

PB2/Al0

..

~

:to.

'44

ADO/AD
ADlIAl

16KEY
GENTRALAB MONOPANEL
KEYBOARD
MRK016CD2300

2

~-:,
~"'~: 'tS=J~.~'

Vee

""~

1-1

~

20K.Q
...A A A

'1 11 1111

PS03XX - Application Note 019

Figure 2.
P5D311
Architecture

A16-A18
r--- A11-A15
L
A
T
C
H

A8-A15

~

A8-A10
A19
CSI

CSIOPORT
A19
CSI
PADA

ALE/AS

RD

WR
ALE/AS

RESET

---

'---

27 P.T.

ESO

~

CSOCS7

.----



eS2/PB2

,.,.

A16

~

A15

-

,.,.
~

_ ..
A14

-g

j;

-

eS4/PB4

-

eS5/PB5

-'"
F;

eS6/PBS

--"
F;

eS7/PB7

j;

A13

A12

A11

CSI
--

RESET

N

-

......
~

eS3/PB3

......

PADB

~

esa/peo

..

..

-

~r>

.

-'"

eS9/PC1
eS10/PC2

-----------------------------------rJfJf~;------------------------------~~~
_ElFIE

2-349

PS03XX - Application Note 019

Interfacing
To The PS0311
(Cont.)

The PAD enables the 8 blocks of 4K bytes
EPROM (256K bits) to be located
anywhere within the available address
space - in this case, the address space of
the 68HC11 is 64K bytes. So, the EPROM
memory is split into two segments of 16K
bytes EPROM each, separated by the 512
bytes of the internal E2PROM on the
68HC11. This means that the first 4
EPROM blocks are mapped contiguously,
as well as the last 4 EPROM blocks.
Here,the program memory (6000H-9FFFH:
EPROM2, and COOOH-FFFFH: EPROM1)
is allocated to the upper portion of address
space.
The data or SRAM memory, on the other
hand, is allocated to the lower portion of
address space and is partitioned into

Benefits
of the PS0311
Usage in
System

Board layout of the cable tester design was
greatly simplified with the PSD311. In fact,
when pin 1 of the PSD311 is oriented 180
degrees from pin 1 of the 68HC11 in the
PLCC package, port B of the 68HC11 is
directly across from the AD8-AD15 pins of
the PSD311. This positioning enables close
layout of the two parts, greatly reducing
costs due to less board space.
Additional space is saved by using the latch
and buffer for general-purpose 1/0 instead
of the larger and more expensive PIA. And
other 1/0 port lines are not sacrificed by
using the multiplexed addressldata bus
instead of the Serial Peripheral Interface of
the 68HC11.

two segments: one segment containing the
SRAM internal to the 68HC11 (256 bytes)
and the other containing the SRAM
internal to the PSD311 (2K bytes). The
SRAM in the PSD311 is mapped via the
address decoder to location 5000H-5FFFH,
respectively.
Data direction and data registers of the
PSD311's two ports are paired and
accessed via an offset from a configurable
1/0 port mapped base address, such as
4000H in this cable tester design. This
enables 16-bit data instructions to access
the two 1/0 ports together, which in turn
reduces both the Load and Store times
during program execution.

This translates into requiring a smaller
power supply and a further reduction in
cost.
The flexibility of the PSD311 in the cable
tester design is also an advantage when
design changes need to be made quickly.
Since the 1/0 ports, PAD, control signals,
and EPROM are all programmable, the
part just needs to be reprogrammed when
the configuration or program memory for
the entire system needs modifying.
For instance, the current system has ten

1/0, eleven input, and eleven output lines

In fact, board space is estimated to have
been reduced by more than 50% over the
alternative cumbersome design because of
the PSD311 positioning on the PC board,
its port expansion capabilities, and of
course, the number of parts it replaces:
including a 256K EPROM, a 16K SRAM, a
latch, a decoder, and other miscellaneous
CMOS logic.

remaining. This can change if other
variables need to be stored or other
peripherals need to be accessed. To
avoid relaying out another board to
accommodate these changes, the PSD311
may be able to be reconfigured to easily
handle them. Also, if more features andlor
capabilities in EPROM are required, the
PSD312 and PSD313 with 512Kbits (64K x
8) and 1Mbits (128K x 8) EPROM, respectively, are available in the same package
and pinout.

A benefit of parts reduction is lower CMOS
power consumption that results from an
integrated single-chip CMOS peripheral!
memory solution. By analyzing the power
that would have been consumed with the
alternative design and comparing that
against the PSD311 solution, it was found
that power was reduced by at least 30%.

The PSD311 also provides additional
SRAM beyond the limited amount that may
be on the microcontroller being used.
This provides obvious benefits including
more scratch pad RAM for such uses as
storing cable "signatures" and system tests
that can be downloaded for diagnostic
purposes.

-2--3-5-0---------------------------~~~-------------------------------

PS03XX - Application Note 019

Benefits
of the PS0311
Usage in
System
(Cont.)

But other benefits not readily seen are also
important. For product designs that have a
short life cycle and are "pushed" to go to
market quickly, the additional SRAM gives
the designer the option of writing the code
in a high-level language such as "C",
without the worry of running out of variable

storage space. The capability of writing
software in "C" could speed up the software
development cycle, thereby reducing timeto-market!

Configuring and
Programming
thePS0311

All of the control logic, address mapping,
and port configurations for the PSD311 are
handled during device configuration as part
of WSI's easy-to-use, menu-driven PSD
MAPLE software program, which is
included in the PSD-SILVER or PSD-GOLD
software development package. See
Appendix A for the PSD311 configuration
used in this application.

"Compile". "Compile" reads the code written
for the microcontroller (in Intel hex format)
and concatenates or merges it with the
PSD311 configuration data to produce the
desired output file for downloading to a
programmer for programming.

After the configuration for the PSD311 has
be~n determined and "Save"d, the hex file
that is needed for programming the
PSD311 is created. That is done during

The 68HC11/
PS0311 System
Software

The software for the 68HC11 was written
with a word processor and assembled using
a cross assembler. A portion of the cable
tester design code which is programmed
into the PSD311 is listed in Appendix B.
Here the register and RAM memory locations are set up within the first 64 clock
cycles from reset of the 68HC11 and
located at OOOOH to enable easy Direct
Addressing and Bit manipulations of often
used registers.
Initialization of the Option Register,
Timer prescaler, Stack and Serial
Communications Interface complete the
basic set up for the 68HC11 operation.
Other initialization operations include: Ports
A and B of the PSD311 which are set up as
outputs for display control and data transfer
operations, and the LCD display which is
set up to display the first screen. Final
initialization is achieved by setting several
internal registers and clearing any
pending interrupts. Now, the IRQ mask bit
can be cleared and the main program loop
entered.

iFES JE/F€ff

That is all there is to programming the
PSD311 which is now supported on
industry-standard programmers like the
Data 1/0, BP Microsystems, Bytek, and
Logical Devices programmers as well as
the low-cost WSI MagicPro programmer.

Included in the code is a demonstration of
some useful routines which will illustrate
how to easily work with the Latch and
Buffer expansion from the 68HC111
PSD311. Rememberthat these extended
addresses off the 68HC11 can be accessed
in several ways. The example code shown
uses the Bit Set and Bit Clear instructions
in the indexed addressing mode. With
these Bit Set and Bit Clear instructions,
which are read-modify-write instructions, an
additional register should be set up in the
internal RAM, not on the latched (writeonly) address, so the
instructions will function properly. Data can
then be manipulated and stored as a
complete byte to the latch enabling data to
be read and the current value in the latch to
be checked. (Bit manipulation on the
latched addresses using the indexed
addressing mode will result in a correct
bit change. However, the rest of the byte
will be unusable as data on the bus will be
scrambled at the rising edge of the chip
select signaL) The latch and buffer
expansion keeps software algorithms
Simple.

--------------------------------------~~af----------------------------------2---3-5--1

•

PS03XX - Application Note 019

The 68HCl1/
PS0311 System
Software
(Cont.)

Regarding the software for the keypad, no
debounce software is necessary because
the 74C922 has a built in debounce circuit.
Actually, direct access from Port E to the
keypad data and the AND instruction allows
easy compare and execution of the correct
routine.

The remaining subroutines in the program
are straightforward and basic to most
microcontrollers and microprocessors.
Those used by the 68HC11 are found in
previously published handbooks and
articles which can be obtained through
your local Motorola sales office.

Putting the
System to
Work

The 68HC11/PSD311 cable tester design
could be expanded very easily with
software to learn many different wiring
configurations and to check several cables
against a good one. Its usefulness can also
be increased by making it battery operated
for field use because of the low current
draw of the tester.

The cable tester, as designed, will display
the test results and step through the
program to show the pin by pin connections
of the cable. Results are then stored and
later fed into a computer through the
RS232 communications port of the tester.

Summary

Requirements for microcontroller-based
designs are continually changing and to be
able to adapt to these changes means
being flexible. Of course, flexibility in
hardware is sometimes hard to achieve,
while flexibility in software is mostly a
given. One of the goals of the PSD3XX
family of products is to bridge the gap in
flexibility between hardware and software.

a user-configurable peripheral solution for
hard)Nare designers. So, if an application is
modified and the 110 configuration
changes, or design fixes are required, the
P.C. board does not have to be
re-engineered. The PSD3XX can just be
reprogrammed to reflect the new changes.

By that, it is meant that hardware will not be
a gating item when developing a new
design that needs to be introduced to
market quickly. And the PSD311, as
illustrated in this cable tester design,
addresses that issue perfectly by providing

The flexibility provided by the PSD311
solution in this design is crucial in that it
enabled development to be completed
quickly and successfully using a "core"
approach which can handle many different
cable applications, including applications
for telephone interconnections, printers,
and local area networks.

~2~-3~52~------------------------~E~------------------------------

PSD3XX - Application Note 019

Appendix A.
PS0311 Part
Configuration
Listed in .SV1
File'
A16/cse

ALIASES

A17/CS9
Aie/CSIO
A19/CSI

cse
IRQ
DA
CSI

*********************************************************************

GLOBAL CONFIGURATION
Address/Data Mode:
Data Bus Size:
CSI/A19:
Reset Polarity:
ALE Polarity:
WRD /RWE:
A16-A19 Transparent or Latched by ALE:
using different READ strobes for SRAM and EPROM:

MX
e
CSI
LO
HI
RWE
T
N

*********************************************************************

PORT A CONFIGURATION (Address/IO)
Bit No.

o

1
2
3

4

5
6

Ai/IO.
IO
IO
IO
IO
IO
IO
IO
IO

CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

7
*********************************************************************

PORT B CONFIGURATION
Bit No.
0
1
2
3
4
5
6
7

CS/IO.
IO
IO
IO
IO
IO
IO
IO
CS7

CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

CHIP SELECT EQUATIONS
/CS7

+

= /A15

* /A14 * A13 * /A12 *

E

*

R/W

*********************************************************************

PORT C CONFIGURATION
Bit No.

o

1
2

CS/Ai.
cse
CS9
A18
CHIP SELECT EQUATIONS

/cse
/IRQ

= /A15
=

* /A14 * A13 * /A12 *

E

* / R/W

DA

*********************************************************************

ADDRESS

ESO
ES1

A A
19 18
N X
N X

MAP

A A A A A A A
17 16 15 14 13 12 11
N N 0 1 ION
N N 0 1 1 1 N

SEGMT
STRT
6000
7000

SEGMT
STOP
6FFF
7FFF

EPROM
START
6000

EPROM
STOP
6fff

File Name
BASE301.0BJ

---------------------------~Jr;---------------------------2-353

PS03XX - Application Note 019

AppendixA.
PSD311 Part
Configuration
Listed in .SVt
File (Cont.)
ES2

N

x

N

N

1

0

0

0

N

8000

8FFF

ES3

N

X

N

N

1

0

0

1

N

9000

9FFF

ES4
ES5
ES6
ES7
RSO

N
N
N
N
N

X
X
X
X
X

N
N
N
N
N

N
N
N
N
N

1
1
1
1
0

1
1
1
1
1

0
0
1
1
0

0
1
0
1
1

N
N
N
N

0

COOO
DOOO
EOOO
FOOO
5000

CFFF
DFFF
EFFF
FFFF
57FF

CSP

N

X

N

N

0

1

0

0

0

4000

47FF

cOOO
dOOO
eOOO
fOOO

cfff
dfff
efff
ffff

BASE301.0BJ
BASE301.0BJ
BASE301.0BJ
BASE301.0BJ

****************************** END ***********************************

CDATA
CADDRDAT
CRRWR
CA19/(/CSI)
CALE
CRESET
COMB/SEP
CADDHLT

0
1
1
0
0
0
0

CPAF2

0

CPAF1
CPAF1
CPAF1
CPAF1
CPAF1
CPAF1
CPAF1
CPAF1

0
0
0
0
0

[0 ]
[l]

[ 2]
[ 3]
[ 4]
[ 5]
[ 6]
[ 7]

CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF

0

0
0
0

[0]

[ 1]
[ 2]
[ 3]
[ 4]
[ 5]
[ 6]
[7]

[0 ]
[ 1]
[2]
[ 3]
[ 4]
[5]
[6]
[ 7]

CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD

0
0
0

0

0
0
0

0
1
1
1
1
1
1
1
0

[0 ]

0
0

[ 1]
[2]
[ 3]
[ 4]
[5]
[6]
[7]

CPCF [0 ]
CPCF [ 1]
CPCF [ 2]

0
0
0
0
0

0
1
1
0

FifE: s= _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

-2--3-5-4------------------~af;

PSD3XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design
0000
0000

CPU
HOF

"6811.TBL"
UINTa"

i

i***************************************************** *****
i*
THE 68HCll IN CONJUNCTION WITH THE PSD301
*
i*
ARE USED IN DEVELOPEMENT OF SOFTWARE FOR
*
i*
DISPLAY, KEYBOARD FUNCTION, AND OTHER APPL.
*
i*
MEMORY MAP:EPROM(l)
COOO-FFFF (PROGRAM)
*
i*
EEPROM
B600-BFFF (68HC11)
*
i*
EPROM(2)
6000-9FFF (DATA)
*
i *
RAM
sOOO-sFFF (PSD301)
*
i *
I/O
4000-4007 (PSD301)
*
i *
LAT
2000
(LATCH & BUFFER)
*
i*
RAM
1000-10FF (68HC11)
*
i*
I/O & REG 0000-003F (68HC11)
*

*

j*

i

*

i*
i

*
*
*

BY TIM DUNAVIN
ANTEC
ANIXTER MANUFACTURING

*

i***************************************************** *****

6000

ORG

06000H

iDATA MEMORY

i

6000
6011
6023
6037

;***********************
i*
LOOKUP TABLES
*
;***********************
i
3638484331DATTAB: DFB
"68HC11/PSD311 UP",OOH
i
s4494D4Fs4CREDITS: DFB
"TIMOTHY E. DUNAVIN"
414Es44s43
DFB
"ANTEC - ANIXTER MFG."
s24F434B20
DFB
"ROCK FALLS, ILL. 61071"
j***************************************************** **

COOO
103D
4000
2000
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
OOOA
OOOB
OOOC
OOOD
OOOE
OOOF

ORG

OCOOOH

iPROGRAM MEMORY

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

103DH
04000H
02000H
OOH
01H
02H
03H
04H
OsH
06H
07H
08H
09H
OAH
OBH
OCH
ODH
OEH
OFH

iRAM AND I/O MAPPING REGISTER
iI/O BASE ADDRESS OF THE 301
i LATCH AND BUFFER
iKEYPAD 1
iKEYPAD 2
iKEYPAD 3
iKEYPAD A
iKEYPAD 4
iKEYPAD 5
iKEYPAD 6
iKEYPAD B
iKEYPAD 7
iKEYPAD 8
iKEYPAD 9
iKEYPAD C
iKEYPAD *
iKEYPAD 0
i KEYPAD #
iKEYPAD 0

i

INIT:
PORTBC:
LAT:
KEY1:
KEY2:
KEY3:
KEYA:
KEY4:
KEYS:
KEY6:
KEYB:
KEY7:
KEY8:
KEY9:
KEYC:
KEYZ:
KEYO:
KEYY:
KEYD:

---------------------------~Jr;--------------------------2-355

I'SD3XX - Application Note 019

AppendixB.
Core System
Soffware for
Cable Tester
Design (Cont.)
COOO OF
COOl 8610
C003 B7103D

;************************************************

;*
INITIALIZATION ROUTINE
*
i************************************************
,

;NOTE: OPTION and TMSK2 must be programed in first 64 E
cycles out of RESET
;
START:
SEI
;SET IRQ MASK
LDAA
#010H
;SET RAM AT 1000 AND
STAA
INIT
;SET REGISTERS AT 0000
i************************************************
;

i******* 64 BYTES OF REGISTER AREA

0000

EQU

OOOOH

0002
0003
0004
0005

PORTA:
;
PIOC:
PORTC:
PORTB:
PORTCL:

EQU
EQU
EQU
EQU

0002H
0003H
0004H
0005H

0007
0008
0009
OOOA
OOOB
OOOC
0000
OOOE

DDRC:
PORTD:
DDRD:
PORTE:
CFORC:
OC1M:
OC1D:
TCNT:

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

0007H
0008H
0009H
OOOAH
OOOBH
OOOCH
OOODH
OOOEH

0010

TIC1:

EQU

0010H

0012

TIC2:

EQU

0012H

0014

TIC3:

EQU

0014H

0016

TOC1:

EQU

00l6H

0018

TOC2:

EQU

00l8H

001A =

TOC3:

EQU

001AH

001C

TOC4:

EQU

OOlCH

001E

TOC5:

EQU

OOlEH

TCTL1
TCTL2
TMSK1
TFLG1
TMSK2
TFLG2
PACTL
PACNT
SPCR:
SPSR:
SPDR:
BAUD:
SCCR1:
SCCR2:
SCSR:
SCDR:
ADCTL:
ADR1:
ADR2:
ADR3:
ADR4:

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

0020H
002lH
0022H
0023H
0024H
0025H
0026H
0027H
0028H
0029H
002AH
002BH
002CH
002DH
002EH
002FH
0030H
003lH
0032H
0033H
0034H

0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A
002B
002C
002D
002E
002F
0030
0031
0032
0033
0034

=

=

*******

;PORT A DATA REGISTER
;0001 IS RESERVED
;PARALLEL I/O CONTROL REGISTER
;PORT C DATA REGISTER (ADO - AD7)
;PORT B DATA REGISTER (A8 - A15)
;PORT C LATCHED DATA REGISTER
;0006 IS RESERVED
;DATA DIRECTION REG FOR PORT C
;PORT D DATA REGISTER (RxD, TxD, AND I/O)
;DATA DIRECTION REG FOR PORT D
;PORT E DATA REGISTER
;TIMER COMPARE FORCE REGISTER
;OUTPUT COMPARE 1 MASK REGISTER
;OUTPUT COMPARE 1 DATA REGISTER
;TIMER COUNTER REGISTER (16 BIT)
;OOOF LSB TCNT
;TIMER INPUT CAPTURE REGISTER 1 (16 BIT)
; 0011 LSB TIC1
;TIMER INPUT ,CAPTURE REGISTER 2 (16 BIT)
;0013 LSB TIC2
;TIMER INPUT CAPTURE REGISTER 3 (16 BIT)
;0015 LSB TIC3
;TIMER OUTPUT COMPARE REG 1 (16 BIT)
; 0017 LSB TOC1
;TIMER OUTPUT COMPARE REG 2 (16 BIT)
;0019 LSB TOC2
;TIMER OUTPUT COMPARE REG 3 (16 BIT)
;OOlB LSB TOC3
;TIMER OUTPUT COMPARE REG 4 (16 BIT)
;OOlD LSB TOC4
; TIMER OUTPUT COMPARE REG 5 / INPUT CAPTURE
;REGISTER 4 (16 BIT) 001F LSB TOC5/TIC4
;TIMER CONTROL REGISTER 1
;TIMER CONTROL REGISTER 2
;MAIN TIMER INT MASK REGISTER 1
; MAIN TIMER INT. FLAG REG 1
;MAIN TIMER INT MASK REGISTER 2
; MAIN TIMER INT. FLAG REG 2
;PULSE ACCUMULATOR CONTROL REG
; PULSE ACCUMULATOR COUNT REG
;SPI CONTROL REGISTER
;SPI STATUS REGISTER
;SPI DATA REGISTER
;SCI BAUD RATE CONTROL REGISTER
;SCI CONTROL REGISTER 1
;SCI CONTROL REGISTER 2
;SCI STATUS REGISTER
;SCI DATA REGISTER
;A/D CONTROL/STATUS REGISTER
;A/D RESULT REGISTER 1
;A/D RESULT REGISTER 2
;A/D RESULT REGISTER 3
;A/D RESULT REGISTER 4
;0035 - 0038 RESERVED

--------------------------------rl, ..~--------------------------------

2·356

....11

PSD3XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)
0039 =
003A =
003B
003C
003E
003F

OPTION:
COPRST:
PPROG:
HPRIO:
;INIT:
TEST1:
CONFIG:

EQU
EQU
EQU
EQU
EQU
EQU
EQU

0039H
003AH
003BH
003CH
003DH
003EH
003FH

SYSTEM CONFIGURATION OPTIONS
ARM/RESET COP TIMER CIRCUITRY
EEPROM PROGRAMMING REGISTER
HIGHEST PRIORITY INTERRUPT
RAM AND I/O MAPPING REGISTER (NEW ADD.)
FACTORY TEST REGISTER
CONFIGURATION CONTROL REGISTER

;

i******* 256 BYTES OF INTERNAL RAM *******

1000
1001
1002
10FF

FLAGS:
LA1:
STOR:
STACK:
;

EQU
EQU
EQU
EQU

1000H
1001H
1002H
10FFH

;FLAG REGISTER
;LATCH DATA REGISTER
;BASIC RAM STORAGE AREA
;STACK AREA

•

;******* 2K X 8 EXTERNAL RAM ********
MASSTOR: EQU
05000H
;MASS STORAGE RAM IN PSD301

5000

;

;******* EEROM AREA, 512 BYTES *******

B600

EROM:

EQU

OB600H

;DATA RETENTION AREA

;
i************************************************

C006 01
C007 86E3

NOP
LDAA

#OE3H

C009 9739

STAA

OPTION

COOB
COOD
COOF
C012
C015
C017

8602
9724
7F0028
8E10FF
8680
9726

C019
C01B
COlD
C01F
C021
C024
C027
C029
C02A

86FC
9709
8600
9708
7F002C
7F002D
962E
4F
972F

ONSCI:

C02C CEFFFF
C02F FF4004

ONPIA:

con

DISINIT:

LDAA
#002H
STAA
TMSK2
CLR
SPCR
LDS
#STACK
LDAA
#080H
STAA
PACTL
;PA7 OUTPUT
INITIALIZE THE SCI TO 9600 BAUD AT 8MHZ (DISABLED)
LDAA
#OFCH
;INIT. PORT 0 DDR (02H)
STAA
DDRD
;PDO, POl - INPUT, PD2-PD5 - OUTPUT
LDAA
#OOOH
;SET UP PORT D
STAA
PORTD
CLR
SCCR1
;SET UP SER. COM. CON. REG. 1
CLR
SCCR2
LDAA
SCSR
;TO CLEAR TDRE AND TC OF SCSR
CLRA
; READ STATUS REG., LOAD TRANS. DATA REG.
STAA
SCDR
INITIALIZE THE 301 FOR DISPLAY INTERFACE
LDX
#OFFFFH
;SET UP PORTS B & C AS OUTPUTS
STX
PORTBC+4
DISPLAY SET UP (NEW REV. 15 MAY 91) *******
LDX
#02710H
;100mS DELAY (POWER UP DELAY FOR DISPLAY)
JSR
TDELAY
;TlME DELAY
LDAA
#030H
;SET UP DISPLAY
JSR
SEND I
;SEND INSTRUCTION (30 1ST TIME)
LDX
#00300H
;6.1mS DELAY
JSR
TDELAY
;TlME DELAY
JSR
SENDI
;SEND INSTRUCTION (30 2ND TIME)
JSR
TD40
;TlME DELAY
JSR
SENDI
;SEND INSTRUCTION (30 3RD TIME)
JSR
TD40
;TlME DELAY
LDAA
#038H
;FUNCTION SET (8 BIT-SINGLE LINE)
JSR
SEND I
;SEND INSTRUCTION
LDX
#00280H
;5mS DELAY
JSR
TDELAY
;TlME DELAY
LDAA
#OOCH
;DISPLAY ON - NO CURSOR

C035
C038
C03A
C03D
C040
C043
C046
C049
C04C
C04F
C051
C054
C057
C05A

CE2710
BDCOE1
8630
BDCOF4
CE0300
BDCOE1
BDCOF4
BDCODE
BDCOF4
BDCODE
8638
BDCOF4
CE0280
BDCOE1
860C

;*******

;*******
;*******

;SLIGHT DELAY TO ALLOW REGISTER SET UP
;SET UP OPTION REG. - ADPU =1, CSEL = 1,
IRQE = 1
; (ENABLE EEPROM CHARGE PUMP, IRQ EDGE
SENSITIVE)
;SET TIMER PRESCALER TO 8
;AND DISABLE TIMER INTERRUPTS
;DISABLE ALL SPI INT.
;SET UP STACK

. . #.

_____________________________ ~~E----------------------------__
2-357

PSD3XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)

C05C
C05F
C062
C065
C067
C06A
C06D
C070
C073
C076
C079
C07D

BDCOF4
CE0280
BDCOE1
8606
BDCOF4
CE0280
BDCOE1
BDCOEC
CE0190
BDCOE1
18CE6000
BDCOCC

C080
C082
C084
C086
C088
C08A
C08C

9629
962A
86FF
9723
9725
962E
962F

,.*******

FINIT:

JSR
SENDI
LOX
#00280H
JSR
TDELAY
#OO6H
LDAA
SENDI
JSR
#OO280H
LOX
JSR
TDELAY
JSR
HOME
#OO190H
LOX
JSR
TDELAY
LOY
#DATTAB
JSR
PDOD
FINAL INIT. *******
LDAA
SPSR
LDAA
SPDR
#OFFH
LDAA
STAA
TFLG1
STAA
TFLG2
LDAA
SCSR
SCDR
LDAA

;SEND INSTRUCTION
;5mS DELAY
;TIME DELAY
;ENTRY MODE SET
;SEND INSTRUCTION
;5mS DELAY
;TIME DELAY
;DISPLAY CURSOR HOME I
; 4 • omS DELAY
;TIME DELAY
;TOP OF DATA TABLE
;SEND MESSAGE TO DISPLAY
;CLEAR ANY SPI INT.
; CLEAR ANY TIMER INT.
;CLEAR ANY SCI INT.

;

C08E
C091
C094
C097
C099
C09C

7F2000
CE1001
1C0200
A600
B72000
B62000

;EXAMPLES OF WORKING WITH LATCH AND BUFFER
LAT
; CLEAR LATCH
CLR
#LA1
LOX
;SET INDEX
;SET BIT 2 OF LA1
BSET
2,X,OOH
;GET LATCH REGISTER
LDAA
O,X
;STORE DATA TO LATCH
STAA
LAT
;GET DATA FROM BUFFER
LDAA
LAT

C09F BDCOBO

JSR

COA2 OE

BEEP

CLI

; SOUND OFF I
; CLEAR IRQ MASK

;
i*************************

;*

COA3 01
COA4 7ECOA3

COA7
COA9
COAB
COAD
COAF

8655
973A
86AA
973A
39

COBO
COB4
COB6
COB8
COBB
COBE
COBF
COC1
COC4
COC7
COC9
COCB

18CE01FF
8640
9700
CE0014
BDCOE1
4F
9700
CE0014
BDCOE1
1809
26E9
39

MAIN LOOP
*
i*************************
;
LOOP:
NOP
JMP
LOOP
; RETURN
;
,.************************************
;*
SUBROUTINES
*
i************************************
;
i******* WATCHDOG SERVICE ROUTINE ******
LDAA
#055H
;RESET WATCHDOG TIMER
DOG:
STAA
COPRST
LDAA
#OAAH
STAA
COPRST
;RETURN FROM SUB.
RTS
;
i******* HOOTER OSC. ROUTINE ********
#OOlFFH
BEEP:
LOY
;SET COUNT
#040H
;BEEPER ON
BEEP1:
LDAA
STAA
PORTA
#00014H
LOX
JSR
TDELAY
; DELAY
CLRA
;BEEPER OFF
STAA
PORTA
LOX
#00014H
JSR
TDELAY
DELAY
DEY
COUNT -1
BEEP1
IF NOT DONE, KEEP GOING
BNE
RTS
RETURN FROM SUB.

-----------------------------------------~~~-----------------------------------------

2-358

PSo3XX - Application Note 019

Appendix B.
Core System
Software for
Cable Tester
Design (Cont.)
i******* PUT DATA ON DISPLAY

cocc
COCF
COD1
COD4
COD6
COD8

18A600
2707
BDC100
1808
20F4
39

PDOD:

PDOD1 :

LDAA
BEQ
JSR
INY
BRA
RTS

O,Y
PDOD1
SENDD
PDOD

********

iGET BYTE
iIF END, GOTO NEXT1

iNEXT BYTE
i RETURN TO NEXT
iRETURN FROM SUB.

i

COD9
CODC
CODE
COE1
COE2
COE5
COE7

CEOO02
2003
CEOOOF
09
8COOOO
26FA
39

i******* TIME DELAY ROUTINE *********
TD20:
LDX
#OOOO2H
i20US DELAY
BRA
TDELAY
#OOOOFH
TD40:
LDX
i150us DELAY
TDELAY: DEX
iDECRAMENT COUNT
CPX
#OOOOOH
iCOUNT = 01
BNE
TDELAY
iIF NOT DONE, GOTO TDELAY
RTS
iRETURN FRO SUB.

COE8
COEA
COEC
COEE
COFO
COF2
COF4
COF7
COF9
COFC
COFF

8601
2008
8602
2004
86CO
2000
CE4000
A706
1C0702
1D0702
39

i******* CLEAR SCREEN, CURSOR HOME, AND SEND INSTRUCTION *******
CSCREEN: LDAA
#OOlH
iCLEAR DISPLAY
BRA
iSEND INSTRUCTION
SENDI
HOME:
LDAA
#002H
iCURSOR HOME
BRA
SENDI
iSEND INSTRUCTION
LINE2:
LDAA
#OCOH
iSET CURSOR TO LINE 2
BRA
iSEND INSTRUCTION
SENDI
SENDI:
iSET UP DATA TRANSFER
LDX
#PORTBC
STAA
6,X
iSTORE AT PIA PORT A
BSET
7 ,X, 02H
iDISPLAY E HIGH
BCLR
7,X,02H
iDISPLAY E LOW
RTS
iRETURN FROM SUB.

C100
C103
C105
C108
C10B
C10E
Cll1
C1l4

CE4000
A706
1C0701
1C0702
1D0702
1D0701
BDCODE
39

i

,

i******* SEND DATA TO DISPLAY

SENDD:

LDX
STAA
BSET
BSET
BCLR
BCLR
JSR
RTS

#PORTBC
6,X
7,X,01H
7,X,02H
7,X,02H
7,X,01H
TD40

********

iSET UP DATA TRANSFER
iSEND DATA
iDISPLAY RS HIGH
iDISPLAY E HIGH
iDISPLAY E LOW
iDISPLAY RS LOW
i150us TIME DELAY
iRETURN FROM SUB.

i

i******************************************************
i*
ROUTINE TO CHANGE BYTE IN EEROM
*
i*
PRELOADED X = ADDRESS IN EEROM (B600 - B7FF) *
i*
DATA TO BE STORED, IS IN "STOR"
*

C1l5
C1l7
C1l9
CllB
CllD
CllF
C121
C123
C125
C127
c128
C12B
C12E
C12F
C130
C132

AGOO
81FF
2717
8616
973B
86FF
A700
8617
973B
3C
CE0300
BDCOE1
38
4F
973B
8602

i*
(THIS IS A MOTOROLA ROUTINE)
*
i******************************************************
CHGBYT: LDAA
O,x
iGET DATA AT ADDRESS TO BE CHANGED
CMPA
#OFFH
iCHECK IF ERASED
BEQ
CHGBYT1
iJUMP IF BYTE ERASED
LDAA
#016H
iSET BYTE, ERASE, AND EELAT
STAA
PPROG
LDAA
#OFFH
STAA
O,X
LDAA
#017H
;SET EEPRG
STAA
PPROG
PSHX
iSAVE X
#00300H
LDX
JSR
TDELAY
i20mS TIME DELAY
PULX
iRESTORE X
CLRA
iCLEAR BYTE, ERASE, EELAT, AND EEPRG
STAA
PPROG
iEND OF BYTE ERASE
CHGBYT1: LDAA
#002H
iSET EELAT - DO BYTE PROGRAM

----------------------------------------~~~----------------------------------------
~'="~=

2-359

•

I'SD3XX - AppllcatlDn NDte 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)
C134
C136
C139
C13B
C13E
C13F
C142
C145
C146
C149
C14C

973B
B61002
A700
7C003B
3C
CE0300
BDCOEl
38
7A003B
7F003B
39

;GET DATA TO BE STORED
;STORE IN NEW LOCATION IN EEROM
;SAVE x

#00300H
TDELAY

;20ms DELAY
;RESTORE x
;CLEAR EEPRG
; CLEAR EELAT, END OF BYTE PROGRAM
;RETURN FROM SUB.

PPROG
PPROG

;
i*****************************************************
ROUTINE TO SET UP AID CONVERTER
*
ACC A
VALUE TO INITIATE CONVERSION
*
BEFORE ENTRY TO THIS ROUTINE
*
i*****************************************************
CONV:
STAA
ADCTL
;SET UP AID CONVERTER
CONV1:
BRCLR
ADCTL,80H,CONVl ;WAIT HERE TILL CONVERSION COMPLETE
RTS
;RETURN FROM SUB.

;*
;*
;*

C14D 9730
c14F 133080FC
C153 39

PPROG
STOR
O,X
PPROG

STAA
LDAA
STAA
INC
PSHX
LDX
JSR
PULX
DEC
CLR
RTS

=

;
i****************************

;*
INTERRUPT ROUTINES
*
;****************************
;
i*****************************************************
;*
SERIAL COMMUNICATIONS INTERFACE _ IRQ
*
i*****************************************************
;

C154 3B

SCOM:
;

RTI

;RETURN FROM INT.

i******************************

;*

*

SERIAL TRANSFER COMPLETE

i******************************
;

C155 3B

TRANC:
;

RTI

;RETURN FROM INT.

i*******************·*************

;*

PULSE ACCUMLATOR INPUT EDGE

*

i*********************************
;

C156 3B

PULSEE: RTI
;RETURN FROM INT.
;
;********************************
;* PULSE ACCUMULATOR OVERFLOW *
i********************************

,
C157 3B

PULSEO:

,

RTI

; RETURN FROM INT.

i********************

;*

TIMER OVERFLOW

*

i********************
;

C158 3B

TIMEO:
;

RTI

;RETURN FROM INT.

i****************************

;*

TIMER OUTPUT COMPARE 5

*

i****************************

,
C159 3B

COMP5:

RTI

;RETURN FROM INT.

-----------------------------~~;-----------------------------

2·360

I'SD3XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)

i***************************

;*

TIMER OUTPUT COMPARE 4 *

i***************************
;

C1SA 3B

COMP4:
;

;RETURN FROM INT.

RTI

i****************************

;*

*

TIMER OUTPUT COMPARE 3

i****************************
;

C1SB 3B

COMP3:

RTI

;RETURN FROM INT.

;
i****************************

;*

*

TIMER OUTPUT COMPARE 2

i****************************
;

C1SC 3B

COMP2:
;

RTI

;RETURN FROM INT.

i****************************

;*

*

TIMER OUTPUT COMPARE 1

i****************************
;

CISD 3B

COMP1:
;

; RETURN FROM INT.

RTI

i***************************

;*

TIMER INPUT COMPARE 3

*

i***************************
;

C1SE 3B

ICOMP3:
;

RTI

;RETURN FROM INT.

i***************************

;*

TIMER INPUT COMPARE 2

*

i***************************
;

C1SF 3B

ICOMP2:

,

RTI

;RETURN FROM INT.;
I

i***************************

;*

TIMER INPUT COMPARE 1

*

i***************************

C160 3B

;
ICOMP1:

,

;RETURN FROM INT.

RTI

i****************************
i* REAL TIME INT. ROUTINE *
i****************************
;

C16l 3B

REALT:
;

RTI

;RETURN FROM INT.

j**********************

;*

C162 960A
C164 840F

IRQ INT. ROUTINE *
;**********************
;
DOlT:
LDAA
PORTE
#OOFH
ANDA

C166 8100
C168 2601
C16A 3B
C16B 8101
C16D 2601
C16F 3B

;
DOITIO:

;GET KEYBOARD DATA
;FILTER DATA

CMPA
BNE
RTI

#KEYl
DOIT10

;1 KEY?
;IF NOT GOTO DOITIO
;RETURN FROM INT.

CMPA
BNE
RTI

#KEY2
DOIT20

2 KEY?
IF NOT GOTO DOIT20
RETURN FROM INT.

",-IE

-------------------------------~.,,----------------------------2--3--61

PSD3XX - Application Note 019

AppendixB.
'Core System
Software for
Cable Tester
Design (Cont.)
C170 8102
C172 2601
C174 3B
C175 8103
C177 2601
C179 3B
C17A 8104
C17C 2601
C17E 3B
C17F 8105
C18l 2601
C183 3B
C184 8106
C186 2601
C188 3B

;
DOIT20:
;
DOIT30:
;
DOIT40:
;
DOIT50:
;
DOIT60:

CMPA
BNE
RTI

#KEY3
DOIT30

3 KEY?
IF NOT, GOTO DOIT30
RETURN FROM INT.

CMPA
BNE
RTI

#KEYA
DOIT40

;A KEY?
;IF NOT GOTO DOIT40
; RETURN FROM INT.

CMPA
BNE
RTI

#KEY4
DOIT50

;4 KEY?
;IF NOT GOTO DOIT50
; RETURN FROM INT.

CMPA
BNE
RTI

#KEY5
DOIT60

;5 KEY?
;IF NOT GOTO DOIT60
; RETURN FROM INT.

CMPA
BNE
RTI

#KEY6
DOIT70

;6 KEY?
;IF NOT GOTO DOIT70
; RETURN FROM INT.

CMPA
BNE
RTI

#KEYB
DOIT80

;B KEY?
;IF NOT GOTO DOIT80
; RETURN FROM INT.

CMPA
BNE
RTI

#KEY7
DOIT90

;7 KEY?
;IF NOT GOTO DOIT90
; RETURN FROM INT.

CMPA
BNE
RTI

#KEY8
DOITlOO

;8 KEY?
;IF NOT GOTO DOITlOO
;RETURN FROM INT.

#KEY9
DOITllO

;9 KEY?
;IF NOT GOTO DOITllO
; RETURN FROM INT.

#KEYC
DOIT120

;C KEY?
;IF NOT GOTO DOIT120
;RETURN FROM INT.

#KEYZ
DOIT130

;* KEY?
;IF NOT GOTO DOIT130
; RETURN FROM INT.

#KEYO
DOIT140

;0 KEY?
;IF NOT GOTO DOIT140
;RETURN FROM INT.

;

C189 8107
C18B 2601
C18D 3B
C18E 8108
C190 2601
C192 3B
C193 8109
C195 2601
C197 3B
C198 8l0A
C19A 2601
C19C 3B

DOIT70:
;
DOIT80:
;
DOIT90:

;
DOITlOO: CMPA
BNE
RTI
;

C19D 8l0B
C19F 2601
ClAl 3B
ClA2 8l0C
ClA4 2601
ClA6 3B
ClA7 8l0D
CIA9 2601
ClAB 3B

DOITllO: CMPA
BNE
RTI
;
DOIT120: CMPA
BNE
RTI
;
DOITI30: CMPA
BNE
RTI
;

ClAC 8l0E
ClAE 2601
CIBO 3B
CIBI 810F
CIB3 2600
ClB5 3B

#KEYY
DOITl40: CMPA
;# KEY?
DOITl50
;IF NOT
BNE
;RETURN
RTI
;
#KEYD
DOITI50: CMPA
;D KEY?
DOITl60
;IF NOT
BNE
DOIT160: RTI
; RETURN
;
i*******************************
,. * XIRQ SERVICE ROUTINE
*
i*******************************

- _.

·-iiI -=

2-362

-----------

---

fill:

GOTO DOIT150
FROM INT.
GOTO DOIT160
FROM INT.

PSD3XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)

CIB6 3B

NOMASK:

RTI

iRETURN FROM INT.

i

CIB7 3B

i*******************************
i* SWI SERVICE ROUTINE
*
i*******************************
INTER:
RTI
i RETURN FROM INT.
i

i***********************************
i* RESET AND INTERRUPT VECTORS
*
i***********************************

FFCO

ORG

OFFCOH

DFS
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM

11*2
SCOM
TRANC
PULSEE
PULSEO
TlMEO
COMP5
COMP4
COMP3
COMP2
COMP!
ICOMP3
ICOMP2
ICOMPI

i

FFCO
FFD6
FFD8
FFDA
FFDC
FFDE
FFEO
FFE2
FFE4
FFE6
FFEB
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFFB
FFFA
FFFC
FFFE

Cl54
Cl55
Cl56
Cl57
Cl58
Cl59
Cl5A
Cl5B
Cl5C
Cl5D
Cl5E
Cl5F
Cl60
Cl61
C!62
CIB6
C!B7
coDa
CODa
CODa
CODa

RES:
SERCOM:
SPISTC:
PAlE:
PAOV:
TOV:
TOCP5:
TOCP4:
TOCP3:
TOCP2:
TOCPI:
TICP3:
TICP2:
TICPI:
RTlME:
IRQ:
XIRQ:
SWI:
lOT:
COPS:
COPS! :
RESET:

REALT

DOlT
NOMASK
INTER
START
START
START
START

iNOT USED
iSERIAL COMM. INT.
iSERIAL TRANSFER COMPLETE
iPULSE ACCUMLATOR INPUT EDGE
iPULSE ACCUMULATOR OVERFLOW
i TIMER OVERFLOW
iTlMER OUTPUT COMPARE 5
iTlMER OUTPUT COMPARE 4
iTlMER OUTPUT COMPARE 3
iTlMER OUTPUT COMPARE 2
iTlMER OUTPUT COMPARE !
iTlMER INPUT COMPARE 3
iTlMER INPUT COMPARE 2
iTlMER INPUT COMPARE !
i REAL-TIME INT.
iTlMER/VIA INT.
iNON-MASKABLE INT.
iSOFTWARE INT.
iILLEGAL OPCODE TRAP (START OVER)
iCOP FAILURE (RESET)
iCOP CLOCK MONITOR FAIL (RESET)
i RESET

i

0000

;************************************************
END
iTHE ENDIIIII

----------------__________ ilf!!FL , - - - - - - - - - - - - - 2 - . - 3 6 - 3
r·~E

•

.1
!

72-~3;64;------------------------------~~~---------------------------------

MAP168

•

Section Index

MAP168

MAP168 Introduction

User- Configurable Peripheral
with Memory .....................................................................3-1

MAP168

DSP Peripheral with Memory ........................................... 3-3

Application Note 002

Introduction to the MAP168
User-Configurable
Peripheral with Memory .................................................3-21

For additional information,
call 800-TEAM-WSI (800-832-6974).
In California, Call 800-562-6363.

Programmable Peripheral
MAP168 Introduction
User-Configurable Peripheral
with Memory
Overview

The MAP168 is a high-performance, userconfigurable DSP peripheral with memory.
It is used in DSP applications including
modems, motor control and medical
instrumentation. The MAP168 is ideal for
DSP based applications where fast time-tomarket, small form factor and low power
consumption are essential. When
combined together in an 8- or 16-bit
system, virtually any DSP chip (TMS320
series, etc.) and the MAP168 work together
to create a very powerful 2-piece chip-set.
This implementation provides the core of
the required control and peripheral
elements of a DSP system.

The MAP168 contains three elements
normally associated with discrete solutions
to system memory requirements. It
incorporates EPROM and SRAM plus a
Programmable Address Decoder (PAD), all
on the same die. The MAP168 is ideal for
the systems designer who wishes to
reduce the board space of his final design.
By using the MAP168 in a system, five or
six EPROM, SRAM and decode logic chips
may be reduced into a single 44-pin
PLDCC, CLDCC or PGA package.

Architecture

The MAP168 incorporates the flexibility of
using discrete memory addressing and
decoding. With the support of WSI's user
friendly PSD software called MAPLE,
designers may configure their MAP168
subsystem for 8- or 16-bit data paths. If the
host system uses an 8051 microcontroller,
the MAP168 can be programmed with an
eight bit data path. A sixteen bit data path
can be programmed for microcontrollers
like Intel's 80196. The depth of the memory
organization will be modified accordingly to
accept the different dat path widths. The
low cost MAPLE software package will
handle the data path width adjustment
automatically. The user can select either
16K bytes of EPROM and 4K bytes of
SRAM or 8K words of EPROM and 2K
words of SRAM. The flexibility of the
MAP168 enables two devices to be
cascaded in width. It is possible to double
the memory size of a sixteen bit system by
using two MAP168 products in parallel but
programmed in a byte-wide configuration.
For example, with two MAP168 devices,
16K words of EPROM and 4K words of
SRAM may be organized as upper and
lower data bytes of a 16 bit word.
Alternately, two MAP168 chips may
expand the system memory vertically as
two word organized memory devices. A
block diagram of the MAP168 is shown in
Figure 1.

decoding on-chip. One MAP168 memory
peripheral can reside with other MAP168
devices in the same memory addressing
scheme, with the on-chip decoder
allocating the memory blocks to different
non-conflicting segments of the entire
memory area. The decoding function is
achieved by an on-chip feature called a
Programmable Address Decoder (PAD),
which is similar to a single fuse array
programmable logic device supporting one
product term (AND gate) per output in the
MAP168.

An important feature of the MAP168 is its
ability to incorporate the '"1lemory address

In the MAP168, eighteen standard chip
select outputs from the PAD are available
with one fast chip select output generally
used to select other external high speed
memory devices. The chi~lect lines may
be subdivided into (ESO-ES7, active low
internal EPROM chip selects, and two
internal RAM chip selects RSO and RS1. In
byte-wide applications, eight chip select
outputs drive external pins CSO-CS7.
These can be used as external chip
selects for other MAP168 devices or
system memory. These outputs are not
available for word-wide MAP168
configurations because the CSO-CS7
output pins carry the higher order data
byte. Only FCSO is available for external
chip selection.
Figure 1 shows the organization of the
EPROM and SRAM in relation to the PAD,
for the MAP168 device.

3-1

•

MAP168 IntroductlDn

Figure 1.
MAP168
Memory
Architecture
EPROM
2K x 8 OR 1K x 16

2K

(Ao-A,. BHE)
ADDRESS BUS

EPROM
OR 1K

x8

x 16

EPROM
2K x 8 OR 1K x 16

'-';;'(A-,,';;;-A-,.-)""+-H----I
EPROM
2K x 8 OR 1K x 16

PAD
ESO

EPROM
2K x 8 OR 1K x 16

ES1

ES2

EPROM

2K

x 8 OR 1K x 16

ES31----'
ES41---......I
ESSt-----'

EPROM
2K x 8 OR 1K x 16

ES6i-----...J
EPROM

ffi 1----I--I1..:2~K~X~8~O:R~1~K~X~16~
CSO[0:7]
CSO[O:7] I-----+-----~~--+-+~

OR

RSOt-----,
RS1/----,
FCSO

HIGH
DATA
BYTE

NO
EPROM
2K x 8 OR 1K x 16

[0:7]

EPROM
2K x 8 OR 1K x 16

Important Features:
• 45 ns EPROM/SRAM Access lime.
• Byte or Word Operation, Mappable into 1M Word or 2M Byte Address Space.
• 22 ns Chip-Select 8 Outputs, 17 ns Fast Chip Select Output.
• 128K EPROM Bits, 32K SRAM Bits, On-Chip Programmable Decoder, Security Bit.

Software
Support

The object code generated for the support
microprocessor/microcontrolier is
generated by an assembler. This code,
when generated as an Intel MCS file, may
be easily programmed into the EPROM
section of the MAP168 device because the
MAPLE software has been designed to
accept this standard format.

EPROM and SRAM memory blocks. This
mapping is achieved by the designer in the
MAPLE environment. The software
provides a safeguard that prevents the
designer from inadvertently overlapping the
address selection. After selecting the
memory block assignments, the MAP168
device maybe programmed by the WSI
MagicPro™ memory and PSD programmer.

The programmable address decoder is
used to define the mapping of the various

---------------------------~Jri--------------------------3-2

Programmable Peripheral
MAP168
DSP Peripheral with Memory
Features

0

First-generation Programmable System
Device (PSD)
User-Configurable Peripheral with
Memory
16Kx8 EPROM
4Kx8 SRAM
Programmable address decoder

General
Description

0

Byte or Word Memory Configurations
16Kx8 or 8Kx16 EPROM
4Kx8 or 2Kx16 SRAM
2Mbyte or 1 Mword address range

0

High-Speed Operation
45-nsec memory access
17-nsec fast chip select output

0

External Chip Select Outputs
8 external chip selects
1 fast chip-select output

In 1988 WSI introduced a new concept in
programmable VLSI, Programmable System
Devices (PSD). The PSD family consists of
user-configurable system-level building
blocks on-a-chip, enabling quick implementation of application-specific controllers and
peripherals. The first generation PSD series
includes the MAP168 User-Configurable
Peripheral with Memory; the SAM448, a
User-Configurable Microsequencer; and the
PAC1000, a User-Configurable Microcontroller.
The MAP168 is the first of WSI's Programmable System Devices (PSD) product line.
The device integrates high performance,
user-configurable blocks of EPROM, SRAM,
and logic in a single circuit. The major
functional blocks include a Programmable
Address Decoder (PAD), 16K bytes of high
speed EPROM, and 4K bytes of high speed
SRAM. A block diagram is given in Figure 1.
The MAP168 device is a complete memory
subsystem that can be mapped anywhere in
a 2M-byte address space of a microprocessor or microcontroller system. The EPROM
and SRAM memory blocks can be userconfigured in either byte-wide or word-wide
organizations. The MAP168 device signifi-

0

Programmable Security
Protects memory map
Protects program code

0

Programming Support Tools
PSD integrated software environment
PC-XT/AT/PS2 platform support
MAPLE location entry Software
MAPPRO device programming Software
MagicPro device programmer (PC-XT,
AT)

0

Military and Commercial Specifications
44-pin Ceramic Leaded Chip Carrier
package
44-pin Plastic Leaded Chip Carrier
package
44-pad Ceramic Leadless Chip Carrier
package
44-pin Ceramic Pin Grid Array package

cantly reduces the board space and power
necessary to implement memory subsystems, increases system performance, and
provides for secure data or program storage.
The device's high level of integration and
flexibility make it ideal for high-speed microprocessors, microcontrollers, and Digital
Signal Processors like the TMS320XX family.
The EPROM can be configured either as
16Kx8 or 8Kx16. The SRAM can be configured either as 4Kx8 or 2Kx16. Individual
memory blocks of 2Kx8 or 1Kx16 can be
selectively mapped anywhere in the address
space. Since the Chip Select Input (CSI) can
be programmed as A20, the highest-order
address bit, the device's address range can
extend from 1M byte with CSI to 2M byte
without CSI.
For 16-bit microprocessors capable of byte
operations, the MAP168 device provides a
Byte High Enable input for accessing bytes
on any address boundary.
Pinout is compatible with the JEDEC
WS27C257 256K high-speed EPROM. This
pinout provides for memory expansion with
future WSI EPROM and PSD products.
The device's PAD and EPROM memory are

3-3

II

I

MAP168

Figure 1.
Block Diagram

MAP168
-----.EECODED EPROM
ADDRESS

~

AO-A12
PGMH

~

PGM

"AO-A19

I-V

EPROM
8Kx 8

,.--.

EOEH

v

OE

OUTa-7

IN 0-7

EOEl

~
~

AO-A12
SRAM
2Kx 8

WEH
WE
OE

OE -

SI/A 20 FCSO -

f----f-----

,.--.

OE

L

ROEl

-

-

OEH

CS O_7

i-

-

,(J

......

INO_7

OUTa-7

L

-

r-----

SRAM
2K x 8
WE

INa-7

-

OEl

t--

OUTa-7

WEl

CON

i-

AO-A12

~

ROEH

~

INO_7

OUTa-7

r----- r---

PAD

E/\.I>p_

OE

I-

f--

DECODED SRAM
ADDRESS

f-----

EPROM
8Kx 8
PGM

L

PGMl

SHE -

AO-A12

S2:1
MUX

,.

2:1
MUX

I-

-

1
-

-

It\

~

tv1

n

'-r-

I
l

-

-]A

\1

L,-,

-

1/0 8- 15 OR CS0a-7

iFils

-,E

1/0 0_ 7
1737 01

--------------------~~Ar----------------------------

3-4

MAP168

General
Description
(Con't)

Functional
Description

Table 1.
Pin Description

programmed using the same WSI MagicPro
programmer used to program other WSI
devices. Two software packages, MAPLE
Location Entry and MAP PRO Device Programming Software are available in the
menu-driven WISPER software environment
on an ISM® PC XT/AT or 100% compatible
platform.

For additional information on the MAP168
device, refer to Application Note No. 002,
Introduction to the MAP168 User-Configurable Peripheral with Memory. For additional
information on development and programming software for the MAP168 device, refer
to the MAP168 User-Configurable Peripheral
with Memory Software User's Manual.

The user-configurable architecture of the
MAP168 consists of an EPROM memory
block, an SRAM memory block, and a fast
Programmable Address Decoder (PAD) that
can be configured to select 2K-byte memory
blocks anywhere in a 2M-byte address

range. The device can be programmed to
operate with memory configured either in a
byte or word organization (bytes can be
addressed in word mode). A programmable
security bit prevents access to the PAD
address-decode configuration table.

Signal

I/O

A0-19
FCSO

Description
Address Lines. For access to EPROM-or SRAM.

°

Fast Chip-Select Output (active low). Used by the Programmable Address Decoder (PAD).

SHE

Byte High Enable (active low). Selects the high-order
byte when writing to SRAM.

WENpp

Write Enable (active low) or Programming Voltage. In
normal mode, this pin causes data on the 110 pins to be
written into SRAM. In programming mode, the pin
supplies the programming voltage, Vpp'

OE

Output Enable (active low). Enable the 110 pins to drive
the external bus.

CSI/A20

Chip Select Input (active low) or High-Order Address.
This pin can be programmed as the bus-access chip
select or as an additional high-order address bit (A20 ).

1/°0-7
1/08-15. CS00-7

11O

Low-Order Byte of EPROM or SRAM.

11O

High-Order Byte or Chip-Select Outputs. In word mode,
these pins serve as the high-order byte (1/08-15) of
EPROM or SRAM. In byte mode, the bits serve as ChipSelect Out signals (CS00-7 ) for the Programmable
Address Decoder (PAD).

FEE =:g

----------------~--------------~~;------------------------------3---5

II

MAP168

Programmable
Address Decoder

The MAP168 device has a minimum of 20
address inputs Ao-A'9 allowing the EPROM
and SRAM memory blocks to reside anywhere in a 1M-byte address space. If the
CSl/A,o input is user-configured as an address line, the maximum addressable space
increases to 2M bytes, as shown in the
Configurations table.
The 16K bytes of EPROM and 4K bytes of
SRAM, can be configured into eight independent 2K-byte blocks and two 2K-byte
blocks respectively, as shown in the Memory
Architecture figure. The PAD is a userconfigurable address decoder that compares
input addresses to the 2K-byte address
range selected for each of the eight EPROM
blocks and two SRAM blocks. When the
input address Ao-A,o is detected to be within
one of the EPROM or SRAM address
ranges, the PAD enables an internal chip
select (ESo-ES, or RSo-RS,) to the selected
block. If no block is selected, both the
EPROM and SRAM memories remain in a
power-down mode and the outputs are
disabled allowing other devices to drive the

Memory
Subsystem
EPROM Memory

The memory configuration of the MAP168
device includes 128K bits of WSI's patented
high-speed, split-gate, UV-erasable EPROM.
The EPROM is configured in byte mode as
16Kx8 and in word mode as 8Kx16. The
memory is organized as eight 2Kx8 or 1Kx16
. blocks, as shown in the Block Diagram
figure. Each block has a separate and
independent address range that cannot
overlap. Each block is individually selected
by one of the ESo-ES, internal chip selects
generated by the PAD when an input address is detected within its designated
address range, as shown in the Memory
Architecture figure. If not selected, each
block of EPROM remains in a power-down
mode.

data bus. The SRAM retains its data in the
power-down mode. The 2K-byte address
ranges for any of the eight EPROM or two
SRAM blocks may not overlap.
The PAD can also be user-configured to
generate up to eight external chip selects,
CSo-CS,. These outputs can be used to
decode the input address lines Ao-A,o and to
select other devices in the system. The
outputs CSo-CS, are available on the eight
higher-order I/OB-1/0,5 lines but only when
the MAP168 device is configured in the byte
mode; the lines are not available as chipselect outputs when the device is configured
in the word mode.
The CSl/A,o input is user-configurable as the
most-significant address line or as an activelow chip enable. Its function is programmed
as part of the PAD programming cycle.
The PAD also provides FSCO, a single, fast
chip-select output configurable by the user for
any address. It can overlap with any of the
internal EPROM, SRAM or external CSO
addresses.

SRAMMemory
The device also includes 32K bits of highspeed SRAM. The SRAM is configured in
byte mode as 4Kx8 and in word mode as
2Kx16. The memory is organized as two
2Kx8 or one 2Kx16 block(s), each with a
separate and independent address range that
cannot overlap. Each SRAM block is individually selected by one of the RSo-RS" shown
in the Memory Architecture figure, when an
input address is detected by the PAD within
its designated address range. When not
selected, each of the SRAM memory blocks
remains in a power down mode but does
retain all data stored.
Data can be written into the SRAM only when
the WEN pp input is active low.

For programming, the EPROM memory
requires the WEN pp input to maintain the
programming voltage V pp.

!FlE. pE_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

- - - - - - - - - - - - - - - - - - ~#;
3-6

MAP168

Memory
Subsystem
EPROM Memory
(Con't)

Byte/Word Mode

PAD available on the eight high-order input!
output lines 1/08-1/0,~d enabled onto the
output bus when the OE input is low.

The PAD can be programmed to configure
the MAP168 device for either a byte or word
memory architecture. This allows the device
to be used conveniently with either 8-bit or
16-bit microcontrollers, microprocessors or
digital signal processor (DSP) systems. See
the Configurations table.

In word mode, the EPROM is organized as
8Kx16 and the SRAM as 2Kx16. The outputs
of both are tied to the 16 input!output lines
1/00-1/0 15 and enabled onto the bus when OE
is low.

In byte mode, the EPROM is organized as
16Kx8 and the SRAM as 4Kx8. The outputs
of both are tied to the eight low-order input!
output lines 1/00-1/0, and enabled onto the
output bus when the OE input is low.

In word mode, the BHE input along with
address input AO allows the eight bits of any
16-bit word on an even or odd boundary to
be selected as shown in the High-Low Byte
Selection table. This is a useful feature for
16-bit processors that are not restricted to
reading or writing memory only on even-word
address boundaries.

Only when configured in byte mode are the
eight external chip selects provided by the

Mode Selection

are ten separate modes of operation, all of
which are shown the Mode Selection table.

The device's operational mode is controlled
by three inputs, CSI, OE, and WENpp. There

Table 2.
Configurations

xB Configuration

x16 Configuration

CSi

A20

CSi

A20

Address Space
words

1M bytes

2M bytes

512K words

1M

Block Size
words

2K bytes

2K bytes

1K words

1K

Addressable Blocks

512

1024

512

1024

EPROM Blocks

8

8

8

8

2

2

SRAM Blocks

2

2

Chip-Select Outputs

9

9

EPROM Configuration

16Kx8

16Kx8

8Kx16

8Kx16

SRAM Configuration

4Kx8

4Kx8

2Kx16

2Kx16

1/0 Pins

8

8

16

16
no

II

1

Low-power Standby

yes

no

yes

Protected Mode

yes

yes

yes

yes

Byte Operations

yes

yes

yes

yes

iF_= gg _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

--------------------~~;

3-7

MAP168

Table 3.
Mode Selection

CSI OE

WE/Vpp Address

Read EPROM/SRAM

V'L

V'L

V'H

EPROM/SRAM
Selected

Read External

V'L

V'L

V'H

EPROM/SRAM
Not Selected

High Z

CS OUT

Output Disable

X

V'H

X
X

CS OUT

High Z

CS OUT

V'L

SRAM Selected

D'N

CS OUT

Write External

V'H X
V'L X
V'L X

X
X

High Z

Stand-By

V'L

No SRAM
Selected

X

CS OUT

Program EPROM

V'L

V'H

Vpp

EPROM
Program Address

D'N

D'N

Program Verify
EPROM

V'L

V'L

V'H

EPROM
Program Address

DOUT

CS OUT

Program PAD

V'L

V'H

Vpp

PAD Program
Address

D'N

D'N

Program Verify PAD

VIL

V'L

V'H

PAD Program
Address

DOUT

CS OUT

Write SRAM

Table 4.
High/Low Byte
Selection

x16(FCSO)
x16 (I/Oo_1J
x8 FCSO, CSlJ0-7
x8 (//00-7)
CS OUT
DOUT

Mode/Pin

x16 Configuration Only
BHE(Pin 1)

Ao

Write Operation

Read Operation

0
0

0

Whole word

Whole word

Upper byte from/to
odd address

Upper byte = Data Out
Lower byte = 'FF'

Lower byte from/to
even address

Whole word

None

Upper byte = Data Out
Lower byte = 'FF'

0

WR and BHE are used for SRAM functions

Table 5. Product
Selection Guide

Parameter

MAP168-45

MAP168-55

Units

Address Access Time (max)

45
45
21
25
20

55
55
23
27
22

ns

Chip-Select Access Time (max)
Output Enable Time (max)
Chip-Select Output Time
Fast Chip-Select Output Time (max)

ns
ns
ns
ns

-----------------------------------~~~---------------------------------3-8

MAP168

Tab/e6. DC
Characteristics

Parameter

Symbol

Test Conditions

Output Low Voltage

VOL
VOH

IOL=B mA

ISB1

notes 1,3

Output High Voltage
CMOS Standby
Current
-Commercial
-Military

IOH=-2 mA

Min

Max

Units

0.5

V
V

2.4

25
35

mA
mA

35
45

mA
mA

25
35

mA
mA

40
50

mA
mA

BO
90

mA
mA

35
45

mA
mA

45
55

mA
mA

90
100

mA
mA

-10

10

I1A

-10

10

I1A

TTL Standby
Current
-Commercial
-Military

ISB2

CMOS Active Current
No Blocks Selected
-Commercial
-Military

Icc 1A

CMOS Active Current
EPROM Block Selected
-Commercial
-Military

Icc 1B

CMOS Active Current
SRAM Block Selected
-Commercial
-Military

Icc 1C

notes 2,3

notes 1, 4

notes 1, 4

notes 1, 4

TTL Active Current
No Blocks Selected
-Commercial
-Military

Icc 2A

notes 2, 4

TTL Active Current
EPROM Block Selected
-Commercial
-Military

Icc 2B

notes 2, 4

TTL Active Current
SRAM Block Selected
-Commercial
-Military

Icc 2C

Input Load Current

III

notes 2, 4

V 1N =5.5V
or GND

Output Leakage Current

ILO

VouT =5.5V
orGND

Notes:
1. CMOS inputs: GND ± 0.3V or VCC ± 0.3V.
2. TTL inputs: V1L:S; O.BV, V 1H ~ 2.0V.
3. Add 1.5 mA/MHz for AC power component.
4. Add 3.5 mA/MHz for AC power component.

-----------------------------------'jfjrjF~---------------------------------iiFill/Ffjg =
3-9

II

MAPt68

Table 7. AC
Characteristics

PlII'lII1IIIltIP

Symbol

MAPt68-45
Min Max

MAPt68-55
Min Max

Units

Read Cycle Time

t Rc

45

55

ns

Address to Output Delay

tACC

45

55

ns

CSI to Output Delay

tCE

45

55

ns

OE to Output Delay

tOE

21

23

ns

Output Disable to Output Float

tOEF

18

20

ns

Chip Disable to Output Float

tCSF
tOH

18

20

ns

Address to Output Hold
Address to CS00-7 True

10

ns

25

27

ns

20

22

ns

Address to FCSO True

tcso
tFCSO

SRAM Write Cycle Time

twc

45

55

ns

55

ns

Address Setup Time

tcsw
tAS

45
0

0

ns

Address Hold Time

tAH

0

0

ns

Address Valid to Write End

tAW

45

55

ns

SRAM Write Enable Pulse Width

30

35

ns

Data Setup Time

tpWE
tDS

20

30

ns

Data Hold Time

tDH

0

0

Write Enable to Data Float

tWEF

Chip Enable to Write End

Write Disable to Data Low Z
SHE Setup Time
SHE Hold Time

Table 8. Data
Retention
Characteristics

10

21

ns
23

ns

tWELZ
t BHES

3

3

ns

0

0

ns

tBHEH

10

10

ns

I'III'amtIltIP

Symbol

Minimum Vee for Data Retention

VDR

Current in Data Retention Mode

ICCDR

Chip Deselect to Data Retention

tCSDR

Recovery Time from Data Retention

tRDA

Test Conditions

Min

Vcc=2.0V,
CSI <: Vcc-0.2V,
VIN <: Vcc-0.2V
or VIN ::;; O.2V

2.0

Max

Units
V
mA

0

ns

tAC

ns

-----------------------------------~~~----------------------------------3-10

MAP168

Absolute
Maximum Ratings

stress rating only and functional operation of
the device at these or any other conditions
above those indicated in the operational
sections of this specification is not implied.
Exposure to absolute maximum rating
conditions for extended periods of time may
affect device reliability.

Storage Temperature ........... -65°C to + 150°C
Voltage to any pin with
respect to GND .......................... -O.6V to +7V
Vpp with respect to GND ....... -0.6 V to + 14.0V
ESD Protection ................................... >2000V
Stresses above those listed here may cause
permanent damage to the device. This is a

Table 9. Operating
Range

Range

Temperature

Vee

O°C to +70°C
-40° to +85°C
-55° to + 125°C

Commercial
Industrial
Military

Figure 3.
Read Cycle
Timing Diagram

+5V ±5%
+5V ± 10%
+5V ± 10%

lAC

ADDRESSES

=>

(

II

_IOH_

IACC

ICSF -

ICE - - - 0

\

~

/
i-

IOE

I/

DOUT

\

DATA VALID

IOEFJ

~4-

~
_IFCSO _
_

lcsO_
1737 03

_____________________________________ ,Arjr~~-----------------------------------~iSF_

3-11

MAP168

Figure 4.
Test Load

==l
98rl

2.

01V

D.U.T.

I.,.

30 pF
(INCLUDING
SCOPE AND JIG
CAPACITANCE)

High-impedance test systems

Table 10.
Timing Levels

Level

Voltage

Input

o and 3V

Reference

1.SV

Figure 5.
Write Cycle
Timing Diagram

1737 04

twc

ADDRESSES

~

---1

\\\1\\\\\\\\
tcsw
tAW

II

\
~tAS

tpWE

....

tWE~

DOUT

tAH_

~tDS---.. j4-tDH1

J1

f4----

I

~
1\\

\

tWELZ

I
DATA-IN VALID

.\

\

,\ ,\
t BHES ....

...

SHE VALID
t BHEH -

\I

.lL
/

/ ,\\\\\\\\\\\\\\\\

...

1737 05

-------------------------------------~~~-----------------------------------3-12

MAP168

Figure 6.
Memory
Architecture

DIRECT ADDRESSES

ADDRESS BUS
BLOCK
DECODE
ADDRESSES
PAD
ES0-7 1----r'--------'--1

•

FE'; -=_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
----------------------------~==E

3-13

MAP168

Table 11. MAP168
Pin Assignments

44-pin CLDCC Package
44-pin PLDCC Package
44-pad CLLCC Package
Pin No.

x8

x16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

GND

BHE
WENpp
eSI/A2D

WENpp
eSI/A2D

es0 7
es06
esos
es04
es03
es0 2
eso,
eso o

1/0'2
1/0 11
1/010
I/0 g

liDs

GND

FeSO
1/07
1/06
1105
1104
1/0 3
1/02
liD,
1100
DE

FeSO
1/07
1/06
1105
1/04
1/03
1/02
1100
DE

AD
A,
A2
A3
A4
As
A6
A7
As
Ag

AD
A,
A2
A3
A4
As
A6
A7
As
Ag

A'D

A'D

A11

A11

A'2
A'3
A'4
A,s

A'2
A'3
A'4
A,s
A'6
A'7
A,s
A,g
Vee

GND

A'6
A'7
A,s
A,g
Vee

~~;;

1/0'4
1/0 13

GND

WE and BHE are for SRAM functions.

3-14

liD,s

liD,

GND

MAP168

Table 12. MAP168
Pin Assignments

44-pin CPGA Package
Pin No.
x8
GNO
As
WENpp
A.
CSI/A20
B.
CS0 7
A3
CSOs
B3
CSO s
A2
CS04
B2
CS0 3
B,
C2
CS02
CSO,
C,
O2
CSO o
GNO
0,
FCSO
E,
E2
1/°7
I/O s
F,
I/0 s
F2
G,
1/°4
G2
1/°3
1/°2
H2
G3
11O,
1/°0
H3
OE
G.
H.
Ao
A,
Hs
Gs
A2
Hs
A3
G6
A.
H7
As
G7
As
Gs
A7
F7
As
Ag
Fs
E7
A,o
GNO
Es
Os
A"
07
A'2
Cs
A'3
C7
A,.
A,s
Bs
B7
A'6
A7
A'7
A,s
B6
A,g
As
Bs
Vee

x16

BHE
WENpp
CSI/~o

1/0,s
1/°'4
1/°'3
1/°,2
11O"
1/0 10
I/0 g

I/0 s
GNO
FCSO
1/°7
I/Os
I/0s
I/0.
1/°3
1/°2
I/O,
1/°0
OE
Ao
A,
A2
A3
A4
As
As
A7
As
Ag
A,o
GNO

•

A"
A'2
A'3
A,.
A,s
A,s
A'7
A,s
A,g
Vee

-------------------------------",AP:------------------------------rgetEF4I
3-15

MAP168

Figure 7.
Pin Assignments
Programming

44 PIN PLOCC PACKAGE
6 5 4 3 2 1 4443424140
III1IIIIIII

r IIIIII1111

'_I I_I I_I I_I '_I I I 1_' 1_' U

8
10
11
12
13
14
15
16
17

-,
:,
--,
:'
:'-,
--,
--',
--,
-,

44 PAD CLLCC OR CLOCC PACKAGE
6 5 4 3 2 1 4443424140

U

U

,-,-,--'--

'-'

.-, I-I I-I I-I I-I I-I

,-,
,---

IIIII111111 t IIII1I1111
'_I ,_, ,_, 1_' 1_' I I I_I I_I '_I '_I I_I

39
38
37
36
35
34
33
32
31
30
29

,-, ,-, (-, .-, .-,

II1I1I1I1III1I11111111

- -,
--

10
11
12
13
14
15
16
17

::1
---,
- -,
-::1

::1
,
--- -,
-::1
- -,
-::1

'-'

0

I-I I-I I-I I-I I-I I-I ,-, '-I I-I I-I I-I
IIII t IIIIII111IIIII111

c:
c:
c:
-'-c:
c:
,--c:
,-,---,---

1819202122232425262728

18192021 22232425262728

TOP (THROUGH PACKAGE) VIEW

TOP (THROUGH PACKAGE) VIEW

39
38
37
36
35
34
33
32
31
30
29

44 PIN CPGA PACKAGE
12345678

000000
800000000
C 00
00
000
00
E 00
00
F 00
00
G 00000000
H
000000
A

TOP (THROUGH PACKAGE) VIEW
1737 07

Upon delivery from WSI or after each
erasure (see Erasure section), the MAP168
device has all bits in the PAD and EPROM in
the "one" or high state. Zeros are loaded
through the procedure of programming.

Information for programming the device is
available directly from WSI. Please contact
your local sales representative.

Erasure

To clear all locations of their programmed
contents, expose the device to an
ultra-violet light source. A dosage of
15W-second/cm2 is required. This dosage
can be obtained with exposure to a
wavelength of 2537A and intensity of
12000~W/cm2 for 15 to 20 minutes. The
device should be about one inch from the
source and all filters should be removed
from the UV light source prior to erasure.

The MAP168 device and similar devices will
erase with light sources having wavelengths
shorter than 4000A. Although erasure times
will be much longer than with UV sources at
2537A, the exposure to fluorescent light and
sunlight will eventually erase the device; for
maximum system reliability, these sources
should be avoided. If used in such an environment, the package windows should be
covered by an opaque label or substance.

System
Development
Tools

MAP168 System Development Tools are a
complete set of PC-based development
tools. Installed on an IBM PC or compatible
computer, these tools provide an integrated,
easy-to-use software and hardware environment to support MAP168 device develop-

men!. The tools run on an IBM-XT, AT, or
compatible computer running MS-DOS
version 3.1 or later. The system must be
equipped with 640K bytes of RAM and a hard
disk.

---------------------------------------~~~-------------------------------------'="'='~ ==
3-16

MAP168

System
Development
Tools (Con't)

Hardware

Software

The MAP168 System Programming Hardware consists of:

The MAP168 System Development Software
consists of the following:

o

WS6000 MagicPro Memory and PSD
Programmer

o

WISPER Software-PSD Software
Environment

o

WS6014 44-pin LCC Package Adaptor
(for 44-pin CLLCC, CLDCC, and PLDCC
packages)

o

MAPLE Software-MAP168 Location
Editor

o

MAPPRO Software-Device Programming Software

o

WS6015 44-pin CPGA Package Adaptor

The MagicPro Programmer is the common
hardware platform for programming all WSI
programmable products. It consists of the
IBM-PC plug-in Programmer Board and the
Remote Socket Adaptor Unit.

Figure 8. MAP168
Development
Cycle

The configuration of the MAP168 device is
entered using MAPLE software. MAPRO
software configures MAP168 devices by
using the MagicPro programmer and the
socket adaptor. The programmed MAP168 is
then ready to be used. The development
cycle is depicted in Figure 8.

,-------,
IBM PC PLATFORM

•

I

Menu Selection

Conti uration Data I

MAPLE

DISK
Pro rammin Data I

MAPRO

MagicPro Hardware
1737 08

-------------------------------~~~-----------------------------3-17

MAPt68

System
Development
Tools (Con't)

Ordering
Information

Support

Training

WSI provides a complete set of quality
support services to registered System
Development Tools owners. These support
services include the following:

WSI provides in-depth, hands-on workshops
for the MAP168 device and System Development Tools. Workshop participants learn how
to program their own high-performance, userconfigurable mappable memory subsystems.
Workshops are held at the WSI facility in
Fremont, California.

o

12-month Software Updates.

o

Hotline to WSI Application ExpertsFor direct design assistance.

o

24-Hour Electronic Bulletin BoardFor design assistance via dial-up
modem.

MAPt68
Part Number

Speed Package
(ns) Type

Package Operating
Drawing Temperature

Manufacturing
Procedure

MAP168-45J
MAP168-45L
MAP168-45X
MAP168-55C
MAP168-55CI
MAP168-55CM
MAP168-55CMB
MAP168-55J
MAP168-55L
MAP168-55LM
MAP168-55LMB
MAP168-55X
MAP168-55XI
MAP168-55XM
MAP168-55XMB

45
45
45
55
55
55
55
55
55
55
55
55
55
55
55

J2
L4
X2
C3
C3
C3
C3
J2
L4
L4
L4
X2
X2
X2
X2

Standard
Standard
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
MIL-STD-883C

44-pin PLDCC
44-pin CLDCC
44-pin CPGA
44-pad CLLCC
44-pad CLLCC
44-pad CLLCC
44-pad CLLCC
44-pin PLOCC
44-Pin CLDCC
44-Pin CLDCC
44-pin CLDCC
44-pin CPGA
44-pin CPGA
44-pin CPGA
44-pin CPGA

Commercial
Commercial
Commercial
Commercial
Industrial
Military
Military
Commercial
Commercial
Military
Military
Commercial
Industrial
Military
Military

-----------------------------------1JfJfjF:----------------------------------'IIII!!!'..,SiiiiFiiI
3-18

MAP168

Ordering
Information

System Development Tools
Part Number

Contents

MAP168-GOLO

WISPER Software
MAPLE Software
User's Manual
WSI-SUPPORT
WS6000 MagicPro Programmer

MAP168-SILVER

WISPER Software
MAPLE Software
User's Manual
WSI-SUPPORT

WS6000

MagicPro Programmer
IBM PC plug-in Adaptor Card
Remote Socket Adaptor

WS6014

44-pin LCC Package Adaptor for
44-pin CLLCC, CLOCC, and PLOCC Packages.
Used with the WS6000 MagicPro Programmer.

WS6015

44-pin CPGA Package Adaptor.
Used with the WS6000 MagicPro Programmer.

WSI-SUPPORT

WSI-TRAINING

•

Support Services including:
Q

12-month Software Update Service

Q

Hotline to WSI Application Experts

Q

24-hour access to WSI Electronic Bulletin Board

Workshops at WSI, Fremont, CA.
For details and scheduling, call PSO Marketing, (415) 656-5400.

-----------------------------------r;jrJF§---------------------------------~--

3-19

~3-~20~------------------------~~;---------------------------

Programmable Peripheral
Application Note 002
Introduction to the MAP168
User-Configurable Peripheral with Memor,

Memory
Structure

Memory configurations in microprocessor and
microcontroller systems have similar structure, irrespective of the application. (see
Figure 1.) They share basic components,
such as an EPROM (for program storage),
and an SRAM (for data storage). In addition,
a decoder circuit is required to select blocks
of memory from the address inputs applied by
the processor. A common implementation of
address decoding originally used MSI building

blocks, such as 74xx138 devices. Memoryconfiguration changes and expansions in a
fixed-logic solution required jumpers on the
printed circuit board. More recently, decoders
based on PAL® devices have provided a more
compact and flexible solution. PAL devices
allow configuration changes to be implemented by insertion of a programmed device
and avoid jumper changes.

•

Figure 1.
Memory
Subsystem
Using Standard
Devices

Address Bus

RDI----+

Mlcroprocessor WR

1-_ _+

Decode
Logic and
Jumpers
To Other Devices

Data Bus

CSO
1739 01

80th solutions involve compromises that
affect system performance, board space,
power and cost. Since the decoder is in the
memory access path, the total memory
access time is the sum of the decoder delay
and the access time of the memory itself. For
example, a 40ns total access time can be
achieved with a 12ns decoder and a 25ns
memory. This allows 3ns for on-board interconnect delay. Memory products in the 25ns

range are expensive and therefore such a
performance entails additional cost. To be
able to integrate the' programmable address
decoder with system memory, EPROM and
static RAM would offer a more flexible
approach. The resulting device would provide
board-space economy, higher performance
and less overall power consumption without
the cost of a multichip solution.

3-21

I
'I

MAP168

Application Note 002

I

I

MemlJry
Structure
(Cont.)

The WSI MAP168 user-configurable
peripheral with memory has been developed to significantly enhance system
performance by integrating high density
EPROM for program store, high density
SRAM for data store and high performance
logic in the form of a Programmable
Address Decoder (PAD) on one chip. (See
Figure 2.) The MAP168 integrates 128K
bits of EPROM and 32K bits of SRAM. It is

Figure 2.
Using the
MAP168

ideally suited for a number of common
design applications:

Cl

Expanding memory systems for
microprocessors and microcontrollers

Cl

Space- and power-sensitive applications
(plug-in cards, avionics, portable
systems)

ADDRESS

v

RD 1 - - - - - - - - - 1 OE

1---------1

WE

/L--:O-Da-:-ta--;;B---:us--~

I/O

L."._ _---''''J~----=:'''''-'e=._-l/V
Microprocessor

MAP168

High-speed Digital Signal Processor
applications (modems, analog data
filtering or analysis)

r - - - l - - - CA'"'dd7 re-s-sB""u-s-~

WR

Features
of the

Cl

The MAP168 offers significant design
advantages through integration,
performance and user-configurability. It
integrates both volatile and non-volatile
memory on the same chip, along with a
flexible decoding system. The memory is
structured as a series of blocks to achieve
a highly configurable circuit for general
purpose applications. The device operates
in one of several modes, one of which is
for normal operation and the rest are for
device configuration. At the heart of all
MAP168 device's is a Programmable
Address Decoder (PAD), which is
programmed during the PAD programming
mode through the circuit's address and I/O
pins. The PAD offers the following features:
Cl

Flexible EPROM/SRAM location within
the address space

Cl

Memory array power-down when not
being accessed

Cl

Secu rity protection of memory
configuration data to inhibit copying

r----- cso
r----- eso

To Other Devices

L--:-:~=-....J
MAP168

Cl

1739 02

Integrated external device mapping
through Chip Select Outputs

Memory Architecture And Technology
The memory in the MAP168 consists of
non-volatile EPROM and volatile SRAM.
(See Figure 3.) The EPROM is subdivided
into 8 blocks and the SRAM into 2 blocks.
The blocks may be configured in either a
2Kx8 or a 1Kx16 format, allowing optimal
interaction with both 8- and 16-bit systems.
These memory blocks can be considered
as separate memories with dedicated
internal chip selects. The PAD selects the
appropriate block, decoded from the
incoming address provided at the device
inputs. This architecture enables the
product to be configured and compatible
with virtually any system address map.
Complicated address maps of microcontroller systems can be fully realized by
programming blocks of EPROM and SRAM
in the memory-mapping scheme of the
system.

-------------------~~~-----------------=;=="'="_
3-22
IW

MAP168 - Application Note 002

Features

of the

MAP168
(Cont.)

fast decode and reconfiguration of the
same device. The MAP168 contains a
128K-bit UV erasable EPROM which can be
organized as 16Kx8 (byte-wide) or as 8Kx16
(word-wide) .

In addition to having fine control of memory
allocation, software updates which require
changes in the address map boundaries can
be easily accomplished by simply reprogramming the PAD at the same time as the
EPROM code. This means only one part
need be sent to the end-product customer to
accommodate field software changes. This
becomes a user-transparent method that
requires no change of PC board jumpers.

The SRAM is based on the industry standard
full CMOS 6-transistor cell. The advantages
of this cell are high speed, very low stand-by
power, high noise immunity and good data
retention when disturbed by alpha particles.
In the MAP168 device, the SRAM contains
32K bits which can be configured as 4Kx8 in
the byte mode or 2Kx16 in the word-wide
mode.

The EPROM is based on WSl's patented
split-gate EPROM technology for high density
and very high speed. It is also used in the
reconfigurable PAD section, permitting both

Figure 3.
Internal
Architecture

MAP168

•

PGMH

f----~PGM

PGM

EOEH
OE

---- OE

1NO_7

OUTO_7

1N0-7
L

PGML
EOEL

~

-

-

-

DECODED SRAM
ADDRESS r---.J......J.----'--'-,

~ Ao-A'2

PAD

---v

SRAM
2Kx 8

WEH

,---.

f----~WE

--

ROEH

f----~OE

OUTO_7

L

WEL
WE/Vpp
OE

-r-r-

CSI/A 20 -

f----t

r---

ROEL

CON

1N0-7

I--CS O_7

~

~~

,

>

i'-

SRAM
2K x 8
WE
OE

OUTO_7

1N0-7
L

i'-

I---

r--

f------~

,,-J--J'----,

OEL

r-OEH

2:1

2:1

MUX

MUX

r-

L

'------

-

r-

Dl'-------~--4.~;-t
1/08-'5 OR CS00-7

1/°0_7

1739 03

___________________________________ rAfjfAF:____________________________________
'FIiif_ iI!1

3-23

MAP168 - Application Note 002

Features
of the
MAP168
(Cont.)

PAD Logic Implementation
The PAD uses the same non-volatile EPROM
cells as the EPROM array. (See Figure 4.) It
can be erased and configured at the same
time as the EPROM. After UV erase or with
new parts, the EPROM cells in the MAP168
device normally connect between the address
inputs and the select outputs. The EPROM
cells are disconnected by selective programming.
The PAD performs as an address
comparator. When the address configuration
previously programmed into the PAD is
detected, the internal chip-select signal to the
memory block selected by that address is
enabled. If no block is selected by the
address, neither the EPROM nor the SRAM
arrays are enabled and other devices may
drive the data bus. Independent of internal
block selection, external chip-select decoding
(known as CSOs) are programmable in the
same block resolution as the internal
memory.
Actual implementation of the PAD is similar to
that of a PAL device. (See Figure 5.) In the
erased state, all the block decode addresses
are connected to the AND plane. There is
only one output per AND gate and there is no
OR plane. Each AND gate output either
selects a block of internal memory or a
number of blocks of external memory for the
external CSOs. Only addresses A,,-A2o are

Figure 4.
PAD
Programming
Examples

used as block decode address. Lower-order
address lines are used only for addressing
within the internal memory arrays.
EPROM select outputs ES o-ES 7 (ES outputs)
select 1 of the 8 available EPROM blocks.
SRAM select outputs RS o-RS, (RS outputs)
select one of the 2 available SRAM blocks.
Because only one EPROM or SRAM block
can be active at a particular time, only one
line from either ES o-ES 7 or RS o-RS, is
allowed to be active at one time. The CSOs
are independent of the ES and RS outputs
and therefore anyone address can be
programmed to select one or more of the
CSOs, even simultaneous to the selection of
one of the ES or RS outputs. This is particularly useful for I/O control or address decode
for wait state generation.
Programming the decoder is similar to
programming a PAL device that has only one
product term (AND gate) per output. To
enable an output S, as shown in Figure 4,
~se loc~ions A" and A'2 are left intact while
A" and A'2 are programmed. Conversely, if
A" and A'2 are programmed while their complements are left intact, then the select S
function is active when A" = A'2 = O. If all
fuse locations are programmed on a product
term, the inputs are pulled HIGH and no
select output can take place. If all fuse
locations are left intact, the S output is
permanently LOW, always selected.

S, = A" A,2
S2= A A;2
"
S3 = HARD DESELECTED

S5 = DONT CARE

=

=

NEVER SELECTED

ALWAYS SELECTED

• = CONNECTED

X = DISCONNECTED
1739 04

-------------------------------------~Jr~~-----------------------------------3-24

MAP168 - Application Note 002

Features
of the
MAP168
(Cont.)

Device Array Power-Down
Power dissipation on the chip is minimized
through logic in the PAD. It selectively
powers up the EPROM or SRAM arrays only
when they are being accessed. If the
EPROM is selected through the decoder, it
will draw power while the SRAM stays
powered down and vice versa. When neither
the EPROM or the SRAM is selected, both
are powered down. Note that data integrity in
a "powered down" SRAM is maintained. A
Chip Select Input (CSI) to the device is

provided for a very low-power quiescent
mode. With CSI=1 , the EPROM and SRAM
are powered down but the PAD is powered
up, independent of the incoming address
signals. The CSI input pin can be connected
to a system power-down signal. If such a
signal is unavailable, addressing a location in
memory that does not select either the
EPROM or the SRAM also reduces power
drain. In this case, only the PAD is powered
up and draws a small fraction of the active
power.

Figure 5.
PAD Array
Architecture

ES O
ES,
ES 2
ES 3
ES •
ES 5
ES 6
ES 7
RS o
RS ,
CSO o

cso,
cso 2
cso 3
CSO.

cso 5
CS0 6
CS0 7
FCSO

-

CSI

IA 20
CSI/A20

/\'9

A '9 A ,S A ,S

/\17

A'7

A'6

A '6 A '5 A '5 1\"

A, •

A'3

A '3

1\'2 A'2 A"

A"
1739 05

------------------------------------~~sfF~-----------------------------------

3-25

•

MAPt68 - Application Note 002

Features
of the

MAP168
(Cont.)

The CSI/A20 input is actually a dual function
pin. It can be an address (MSB) input, or it
can be programmed to be a chip select input
as well. As a chip select input, it will enable
the EPROM and SRAM memory when active.
(LOW). If the address option A 20 is chosen the
chip is always enabled.

Address Map Security
Upon entering the PAD programming
mode, the contents of the PAD are fully
accessible through the 1/0 pins. 'After
programming is completed, it is possible to
render the PADs programmed configuration
invisible by programming the security
(SEC) bit. This disables external access to
the PAD and ensures that the PAD
configuration can not be copied. To further
aid in securing data in the MAP168, it is
suggested that memory blocks that are
addressed in a linear block placement be
programmed in the PAD as chip selects
from product terms that are randomly placed.

Chip Select Outputs
The MAP168 device can be user-configured
for 8-bit or 16-bit systems. In the former case,
eight unused data lines (CSOO_ 7 ) are available
as chip select outputs, driven by the address
decoder section of the PAD. This provides the

Systems
Applications

The MAP168 device is designed to reduce
memory access time and board area utilization in high performance digital signal processor, microcontroller and microprocessor
systems. These systems typically have the
following requirements:

o
o

16-bit data path
64K to 1 Meg address space

o

Fast memory access time (1 OOns to
40ns)

o
o

Decoding for 1/0 and memory

o

Multiple types of memory, including
EPROMs and SRAMs for program and
data store.

Printed circuit board area limitations

The DSP System Architecture shown in
Figure 6 illustrates a typical system based

ability to integrate external devices into the
address map with no hardware overhead.
Unlike the internal memory blocks, a CSO
can be active for more than one address
combination or block. Also, groups of blocks
may overlap both each other and the internal
memory. By deselecting both the true and the
complement it is possible to make an address
line "don't care".
An external memory can therefore be selected with only one CSO. It is possible to
enable another external 128K byte memory
by programming a single CSO to be active for
that entire address range.
A CSO can be programmed to function as a
configuration bit which is always deselected
(e.g., CSOo=:1) or always selected (e.g.,
CSOo=O) by programming the addresses with
"hard deselect" or with the "don't care"
patterns, respectively. This is similar in
function to a PC-board wire jumper. If unused
CSOs are programmed with all addresses
"don't care", then switching is eliminated and
power consumption reduced for those lines.
Since the PAD is always powered up when
the device is selected (CSI=O), CSOs are
always active and their state is a direct
function of the PAD configuration and current
address line inputs.
upon a 40MHz TMS320C25 digital signal
processor. Such a system allows only 40ns
for memory access time. The access time
must be broken down into decoding time
and memory-access time. The fastest
decoders available today require
approximately 1Ons to complete their
decode function. Due to this decoding time,
memory access time for both the EPROM
and SRAM must be 30ns or less. The
MAP168 performs decoding on-chip
with no speed penalty. As a result, the
performance of a 45ns MAP168 device in
the above example is equivalent to a 10ns
decoder and a 35ns EPROM and SRAM
memory. In addition, the package
equivalent of two fast EPROMs, two fast
SRAMs and at least one decoder are
combined into one MAP168 chip resulting
in at least a 5-to-1 component count
reduction.

-------------------------------------~~~-----------------------------------="~EiF_
3-26

MAPt68 - Application Note 002

Systems
Applications
(Cont.)

High-Speed, Word-Oriented Application

Memory (OS). These functions are connected to the higher order address of the
MAP168 device. PS is connected to AlB
and OS is connected to All" Usually PS will
select the EPROM and OS will select the
SRAM. The PAO permits partitioning of the
MAP168 memory to accommodate virtually
any system address map. Figure 8 shows
two possibilities.

The MAP168 device is especially suited for
high-speed word-only microprocessors. The
TMS320C20/25 OSP family is an example of
such a microprocessor. Interfacing the
MAP168 device to a TMS320C25 operating
at 40MHz with no wait states is illustrated in
Figure 7. The TMS320C25 has two pins for
selecting Program Memory (PS) and Oata

Figure 6.
DSPSystem
Architecture

.

,..

CSTo Ports

Fast
Decoder
(PLD)

110 Port
Interface

EPROM

1~.18

ADDRESS

*

EPROM

>- H

AD

AD

L...., CS

--< CS

OE

--< DE

-

RD
Digital Signal

DATA (0:7)

DATA (0:7)

Processor,
Microprocessor, or
Microcontroller

.

16

DATA

- - --

I
I
I

-

WR

1

I

BHE

-------1

~

I

DATA
(0:7)

_

*

L- DE

,..

-

I
I

~

Only Where Byte

I

_

L- DE

I
I

I
I

-----I

WR
SRAM
_
CS

I-- f.--, CS

AD

L-

--<0

DATA
(0:7)

*

WR
SRAM
_
AD

: _OEe~a~o~s_A~e_N:e~:.d ~
• Replaced by
MAP168 Device

1739 06

Figure 1.
TMS320C25
Interfacing
xt6 Configuration

40 MHz

-

~

PS

Memory Configuration
8Kx 16 EPROM
2K x 16 SRAM

AlB

CK

BS

A17
A l _ 16

Ao-A15
V

TMS320C25

~

-

A 19

D o-D 15

MAP168
Ao
D o-D 15

V

READY

STRB

>--

ANi

I

WR
DE

~

CSI/A 20
1739 07

---------------------,JrJr~~------------------""~41!
3-27

•

MAP168 - Application Note 002

Systems
Applications
(Cont.)

When in a word-wide (x16) configuration, the
total memory available on the MAP168 device
is 8Kx16 of EPROM and 2Kx16 of SRAM.
The implementation shown in Figure 7
replaces at least five circuits:

o
o

One high-speed decoder (10ns)

o

Two 2Kx8 SRAMs (30ns)

Two 8Kx8 EPROMs (30ns)

If the system was previously implemented
using a boot EPROM, the MAP168 device
replaces ten circuits:

o

One high-speed decoder (1 Ons)

o
o
o
o

Two 8Kx8 EPROMs (30ns)
Two 2Kx8 SRAMs (30ns)
Two 8Kx8 slow EPROMs
Three ICs for Wait-State generation

For expanded memory requirements in a
word-wide (x16) configuration, two MAP168
devices can be interfaced directly with a
TMS320C25, as shown in Figure 9. The two
MAP168 devices provide the total system
memory. Key features of this system are:

o
o
o
o

40ns access time
16Kx16 EPROM
4Kx16 EPROM
16 general purpose programmable chip
selects

The general-purpose programmable chip
select outputs can be mapped to any location
in the address space via the PAD. These chip
selects can be used to access 110 ports,
select additional memory or control other
system functions.

FigureS.
Memory
Mapping with
MAP

a. Contiguous Mapping

b. Split Mapping

1739 08

-------------------------------------~~~-----------------------------------3-28

MAP168 - Application Note 002

Microcontrol/er
Application

The MAP168 device has two basic configurations. They are a word-wide (x16) configuration with byte operation capability and a bytewide (x8) configuration with 8 chip select
outputs.
The 128K address space (during byte operations in the word-wide mode) makes the
MAP168 device especially suited for microcontroller applications. Figure 10 illustrates a

Figure 9.
DSPwith
Expanded
Memory

40 MHz

The MAP168 device can be configured in a
byte-wide (x8) mode and can also be
doubled-up with a second device.

PS
58

--

A'B
An

MAP16S

f'-

Ao-A'5

TMS320C25
Do-D,s

-

simple interconnection of the MAP168 device
to a microcontroller. The HPC16040 operating without wait states requires a memory
access time of 65ns or better. This makes the
MAP168 device a good fit, since it offers an
access time of 45ns, leaving a 20ns margin.

STRS
READY

RNi

v

~

r

A'_'6
Ao_ A'9 _CSI

"Do-D,s

V-

SHE

-

)"r---'

I

~

•

WE

-

DE

A'B
A,?

"-

1t
v

MAP16S

A'_'6
Ao_ A'9_ CSI

Do-D,s

Lf--4

WE

L....t

DE

SHE

n
1739 09

- - - - - - - - - - - - - - - - - - ~.r;
___ s -----------------3---2-9

MAP168 - Application Note 002

Microcontrol/er
Application
(Cont.)

Embedded Controller Application
An embedded controller is an intelligent
section of logic, usually based around a
processor, dedicated to a particular task and
is not accessible for software alteration by the
user. Such applications are generally complex and are becoming more common in
system design. Typically, embedded controllers are high performance systems designed
under severe space/power constraints. On
the other hand, they have a limited ability to
be upgraded and limited program memory.
This makes them ideal candidates for the
MAP168 implementation. The MAP168 has
the following key features which are useful
in such an application:

o
o
o
MAP168
Development
Support

1M address space decoding
45ns access time
Byte operations in word-wide mode
(BHE)

WSI provides the development environment needed to program the MAP168. A
menu-driven software package known as
MAPLE is available under the WISPER toplevel software. It operates on the popular
IBM-PC® as a platform and includes extensive documentation on installation and
operation. It generates configuration files

Figure 10.
Microcontrol/er
Interfacing

o

One output chip select when in the wordwide mode (FCSO)

o

Nine output chip selects when in the bytewide mode

o

Programmable Address Decoder (PAD)

A popular processor for embedded applications, due largely to its extensive software
library and development support, wide
availability of compatible peripherals and low
cost from volume production is the 80186
from Intel. Figure 11 shows how a MAP168
device can be interfaced to an 80186.
The UCS (Upper Chip Select) is connected to
CSI/A 2D on the MAP168 device. The PAD is
programmed to locate a 1Kx16 EPROM slot
in the upper memory address space for a
reset subroutine. The rest of the memory can
be located as required by the user. Figure 12
shows one possibility.

for use by the programming tools. These
programming tools include the MagicPro ™
programmer hardware and the MAP PRO
software. They enable the user to program
the PAD and the EPROM. For additional
information, consult your nearest WSI sales
representative.

Memory
Configuration
8K
2K

x16 Configuration

x 16 EPROM

x 16 SRAM

A D- 15

MAP168
ALE

Microcontroller
(HPC16000,
8096, .'c.)

vee

READY

BHE
D0- 15
WR ~--------------------------RD ~----------------------------~

1739 10

-3--3-0--------------------------------~aF~-----------------------------------

MAP168 - Application Note 002

Figure 11.
Interfacing To
An 80186

t-..
A ,B-A '9

A'B A '9

x16 Configuration

AD O_ 15

ALE

I
G

J
+
G

-

I

Latch

t

SRDY
ARDY

I

t-..
A0-7

I

80186

Vee

AD s_15

Latch

Y-

BHE

MAP168
(x16)

-

-

BHE

-CSI/A 20

UCS I - - WR

r---

--

AD

'---

6E

FCSO To

1-----+ User
Port

WE

ADO-15

Do-15

~~

>

-

LCS

MCS0-3

Figure 12.
Optional Memory
Mapping For An

1739 11

1K x t6
EPROM Reset

80186

Program
Store

Data

Store

Vector
Interrupt -Store

tK x 16 SRAM
1739 12

---------------------------------------~~~-------------------------------------3-31

•

~~~~------------------------------------------------

3-32

~==;:E
--,..- .... _-------

-~

~~

Development Systems

•

Section Index

Development
Systems

Electronic Bulletin Board ..................................................................................................... .4-1
PSD-Gold/Silver Development System ............................................................................... .4-3
WS6000 MagicPro™ Memory and Programmable Peripheral Programmer. ...................... .4-7

For additional information,
caI/800-TEAM-WSI (800-832-6974).
In California, Call 800-562-6363.

Programmable Peripheral
Electronic Bulletin Board

Bulletin
Board

Access Line

WSI provides a 24-hour electronic bulletin
board system that provides the user with
the latest information on software updates,
enhancements, and applications relating to
WSI products. In addition, users
developing applications software for WSI
products can send portions of their code
to WSI for application's consultation if desired.

To access the bulletin board, dial

(510) 498-1002
and wait for the modem tone. When your
modem establishes a connection, enter
  to signal the bulletin
board software. The board should respond:

The following hardware is required to use
the WSI bulletin board:

r:J Computer Terminal
r:J 300, 1200, 2400 Baud Modem
r:J 8 Data Bits
r:J No Parity
r:J 1 Stop Bit
followed by some other messages, after
which you will be asked for your name,
and a password. Upon initial use, follow
the on-screen prompts for establishing
your password.
Now that you have entered the bulletin
board service, you will be given a choice
of "MAIN" commands:

•

WSI Customer Engineering Support
Electronic Bulletin Board Service

Main Commands

M)sg-Section

L)ist-Callers

Choose this option to leave messages.

Choose this option to see who else is
using the board at this moment.

F)ile-Section
Choose this option to download or upload
data files and/or utility programs

B)ulletins
Choose this option to see the latest
important news such as software versions
and programming tips for WSI Memory
and PSD products.

S)tatistics
This option describes the current bulletin
board statistics

A)ns-Questionnaire
Choose this option to answer a user
profile questionnaire.

V)ersion
Describes the board software version.

6)oodbye
Choose this to leave the bulletin board.
See the individual software manuals for
more detailed explanation and usage of
the bulletin board.

C)hange
Choose this option to change operational
settings that the bulletin board maintains
for your user name.

P)age-Operator
Choose this to page the operator for
assistance. It is not likely that the operator
will be available during West Coast U.S.
non-business hours.

EF====E

-------------------------------------r~
~~-----------------------------------=="'=';::; IE

4-1

I1
!

4~-~2-----------------------------~~~~-------------------------------

iFEE_E
----- -E

Programmable Peripherals

-

~

!!!!-!F.!!!!!!-~"::

1!'

---~~

PSD-Gold/PSD-Silver
Development System
PSD3XX/MAP168

Description

PSD-Gold/PSD-Silver is a complete set of
IBM-PC-based development tools. They
provide the integrated easy-to-use environment to support PSD3XX family and
MAP168 program development and device
programming.

The tools run on an IBM-PC XT, AT or
compatible computer running MS-DOS
version 3.1 or later.

MAPLE

MAPLE is the Locator Editor. It has the
following features:

o

Generating the PAD programming data
that maps the EPROM, SRAM and Chip
Selects Outputs to the user's address
space.

o

Combining all the different files to be
programmed into the EPROM
segments.

o
o
o
o
o
o
o

Write RAM to FILE

o

MAPPRO

Simple Menu Driven Commands for
selecting different configurations of the
PSD3XX/MAP168
- Byte wide or word wide operation.
- Address or Chip Select Input (CSI)
Mode.
- PAD security option.

MAPPRO is the interface software that
enables the user to program a PSD3XX or
MAP168 device on the WS6000
MagicPro™ programmer. The MAPPRO
enables the user to load the program into
the programmer and to execute the
following operations.

o
o
o

Help

•

Display MAP data
Blank test MAP
Verify MAP
Program MAP
Configuration
Quit

Upload RAM from MAP
Load RAM from disk

WS6000
MagicPro™
Programmer

The wS6000 MagicPro Programmer is an
engineering development tool designed to
program all WSI programmable products
(EPROMs, RPROMs, PAC1000, MAP168,
PSD3XX family and SAM448). It is used
within the IBM-PC and compatible
environment. The MagicPro consists of a
short plug-in board and a Remote Socket

WS6014
Socket
Adaptor

The WS60 14 is a socket adaptor that
mounts on the MagicPro RSA and adapts
the MAP168 in 44-in CLDCC, PLDCC or
CLLCC packages to the programmer.

Adaptor (RSA). It occupies a short expansion slot in the PC. The RSA has two ZIFDIP sockets that will support WSl's 24, 28,
32 and 40 pin standard 600 mil or slim 300
mil DIP packages without adaptors. Other
packages are supported using adaptors.

4-3

PSD-GDId/Sllver

PSD-GDld

CDntents

o
o
o

MAPLE-MAP Locator editor.
MAPPRO
Interface software to MAP168 device
programmer (MagicPro TM)

o
o
o

WSI-Support agreement
WS6000 MagicPro Programmer
A Socket Adaptor and Two
Product Samples

Software user's manual

...

----------------------------------,-,
Will --------------------------------4-4

PSD-GDldlSllnl

PSO-Silver

CDntents

o
o

MAPLE-MAP Locator editor.

o

Software user's manual

MAPPRO

o

WSI-SUPPORT agreement.

Interface software to MAP168 device
programmer (MagicPro TM)

-----------------------------~Jrl----------------------------

4-5

PSD-Gold/Silver

WS6015
Socket
Adaptor

The WS6015 is a socket adaptor that
mounts on the MagicPro RSA and adapts

the PS03XX or MAP168 in a 44-pin PGA
package to the programmer.

WS6020
Socket
Adaptor

The WS6020 is a socket adaptor that
mounts on the MagicPro RSA and adapts

the PS03XX in a 52-pin PQFP package to
the programmer.

WS6021
Socket
Adaptor

The WS6021 is a socket adaptor that
mounts on the MagicPro RSA and adapts

the PS03XX in a 44 pin CLOCC or PLOCC
package to the programmer.

WSI-Support

WSI provides on-going support for users
of PSO-Gold/Silver. For the first year,
software and programmer updates are
included at no charge. After that, the user

may purchase the WSI-Support agreement
to continue to receive the latest software
releases.

Ordering
Information

Product

Description

PSO-Silver

Contains PS03XX and MAP168 Software (MAPLE-MAP and
MAPPRO), Software User's Manual, WSI-Support.

PSO-Gold

Contains PSO-Silver, WS6000 MagicPro Programmer, a Socket
Adaptor and Two Product Samples, WSI-Support.

WSI-Support

12-Month Software Update Service, Access to WSI's 24-Hour
Electronic Bulletin Board, and Hotline to WSI System Application
Experts.

-------------------------------'I;AF:------------------------------4-6
'IiNfi• •

WS6DDD

MagicPro™ Memory and Programmable
Peripheral Programmer
Key Features

o
o

General
Description

Programs All WSI CMOS Memory and
and Programmable Peripheral Products
and All Future Programmable Products
Programs 24, 28, 32 and 40 Pin
Standard 600 Mil or Slim 300 Mil Dip
Packages without Adaptors

MagicPro is an engineering
development tool designed to program
existing WSI EPROMs, RPROMs,
Programmable Peripherals, and future WSI
programmable products. It is used within
the IBM-PC® and compatible computers.
The MagicPro is meant to bridge the gap
betweeen the introduction of a new WSI
programmable product and the availability
of programming support from programmer
manufacturers (e.g., Data 1/0, etc.). The
MagicPro programmer and accompanying
software enable quick programming of
newly released WSI programmable

o
o
o

Programs LCC, PGA and OFP
Packaged Product by Using Adaptors
Easy-to-Use Menu-Driven Software
Compatible with IBM PC/XT/AT
Family of Computers (and True
Plug-Compatible

products, thus accelerating the system
design process.
The MagicPro plug-in board is integrated
easily into the IBM-PC. It occupies a short
expansion slot and its software requires
only 256K bytes of computer memory. The
two external ZIF-Dip sockets in the Remote
Socket Adaptor (RSA) support 24, 28, 32
and 40 pin standard 600 mil or slim 300
mil Dip packages without adaptors. LCC,
PGA and OFP packages are supported
using adaptors.

4-7

•

WS6000

General
Description
(Cont.)

Many features of the MagicPro
Programmer show its capabilities in
supporting WSI's future products. Some of
these are:

o
o

24 to 40 pin JEDEC Dip Pinouts
1 Meg Address Space
(20 address lines)

The MagicPro menu driven software
makes using different features of the
MagicPro an easy task. Software updates
are done via floppy disk which eliminates
the need for adding a new memory device
for system upgrading. Please call
800-TEAM-WSI for information regarding
programming WSI products not
listed herein. The MagicPro reads Intel
Hex format for use with assemblers and
compilers.

o

16 Data I/O Lines

MagicPro
Commands

o
o
o
o
o
o
o

Help
Upload RAM from Device
Load RAM from Disk
Write RAM to Disk
Display ,RAM Data
EditRAM
Move/Copy RAM

0
0
0
0
0
0
0

Technical
Information

o

Size:

o

IBM-PC Short Length Card

o

Port Address Location:
1OOH to 1FFH- default 140H (if a
conflict exists with this address space,
the address location can be changed
in software and with the switches on
the plug-in board.)

o

System Memory Requirements:
256K Bytes of RAM

o

Fill RAM
Blank Test Device
Verify Device
Program Device
Select Device
Configuration
Quit MagicPro

Remote Socket Adaptor (RSA):
The RSA contains two ZIF-Dip sockets
that are used to program and read WSI
programmable products. The 32 pin
ZIF-Dip socket supports 24, 28 and 32
pin standard 600 mil or slim 300 mil
Dip packaged product. The 40 pin
ZIF-Dip socket supports all 40 pin Dip
packages. Adaptor sockets are
available for LCC, PGA and QFP
packages.

Power:
+ 5 Volts, 0.03 Amp; +12 Volts,
0.04 Amp

------------------------~Jr;.-----------------------4-8

WS6000

Ordering
Information

The WS6000 MagicPIO Systems Contains:

o
o
o

MagicPro IBM-PC Plug-in Programmer Board
MagicPro Remote Socket Adaptor and Cable
MagicPro Operating System Floppy Disk and Operating Manual

The WS6000 MagicPro Adaptors Include:
0

WS6001 28-Pin CLLCC Package
Adaptor for Memory.

0

WS6014 44-Pin CLDCC/PLDCC
Package Adaptor for MAP168

0

WS6008 28-Pin 0.3" Wide Dip Adaptor
for SAM448

0

WS6015 44-Pin PGA Package Adaptor
for MAP168 and PSD3XX

0

WS6009 28-Pin PLDCC/CLDCCI
CLLCC Package Adaptor for SAM448

0

WS6016 44-Pin CLDCC/PLDCC
Package Adaptor for Memory

0

WS6010 88-Pin PGA Package Adaptor
for PAC1000

0

WS6020 52-Pin POFP Package
Adaptor for PSD3XX

0

WS6012 32-Pin CLDCC Package
Adaptor for Memory

0

WS6021 44-Pin CLDCC/PLDCC
Package Adaptor for PSD3XX

0

WS6013 1~O-Pin OFP Package
Adaptor for PAC1000

•

MagicPro™ is a trademark of WaferScale Integration, Inc.
IBM-PC® is a registered trademark of IBM Corporation.
rJ1if-~

-----------------------------------~~I-----------------------------------

4-9

~4-~10~-------------------~Jr;-----------------------

Package Information

•

Section Index

Package
Information ............................................................................................................................................................5-1

For additional information,
ca/l800-TEAM-WSI (800-832-6974).
In California, Ca/l 800-562-6363.

Programmable Peripherals
Package Information
Drawing C3 44 Pad Ceramic lead/ess Chip Carrier (CllCC)
(Package Type C)

3

2

1

l

44

liB

E

---o----J~I -I

1--

E3 E2

A

1-

--03---

1_ _

1 - - - - - 02 - - - - - I

Symbol
A
A1
B
81
D
D2
D3
E
E2
E3
e1
N

Min
2.41
1.47
0.56
16.26

16.36

Family:
Millimeters
Max
3.30
2.03
0.46
0.71
16.81
13.97
12.70
16.81
13.97
12.70
1.27
44

Ceramic Leadless Chip Carrier
Inches
Notes
Min
Max
0.095
0.130
0.058
0.080
0.018
Typical Oia.
0.022
0.028
0.640
0.662
Typical
0.550
Reference
0.500
0.640
0.662
Typical
0.550
Reference
0.500
Reference
0.050
44

C3b Rev. 3

Notes

Typical Dia.

Typical
Reference
Typical
Reference
Reference
C3, C3b

5-1

II

~

Package Information

!

Drawing J2 44 Pin Plastic Leaded Chip Carrier (PLoCC)
(Package Type J)

A1

Symbol
A
A1
A2

8
81
C
D
D1
D2
D3
E
E1
E2
E3
e1
N

Min

Family:
Millimeters
Max

4.19
4.57
2.54
2.79
3.76
3.96
0.33
0.53
0.66
0.81
0.246
0.262
17.40
17.65
16.51
16.61
14.99
16.00
12.70
17.40
17.65
16.51
16.61
16.00
14.99
12.70
1.27
44

A2 A

Plastic Leaded Chip Carrier
Notes

Min

Inches
Max

0.165
0.100
0.148
0.013
0.026
0.0097
0.685
0.650
0.590

0.180
0.110
0.156
0.021
0.032
0.0103
0.695
0.654
0.630

Reference

0.500

Reference
0.695
0.654
0.630

0.685
0.650
0.590
Reference
Reference

Notes

0.500
0.050
44

Reference
Reference

_______________________________ r • • jF.·______________________________
5-2

"",..,.

Package Information

Drawing L4 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window
(Package Type L)
,...1-------- 0
----01
3

2 1 44

E

~

t

t

A2

t

~~
Symbol
A
A1
A2

8
81

C
D
D1
D2
D3
E
E1
E2
E3
e1
N

f

f

A1

A

Family: Ceramic Leaded Chip Carrier-CERQUAD
Inches
Millimeters
Min
Max
Min
Max
Notes
3.94
2.29
3.05
0.43
0.66
0.15
17.40
16.31
14.99
12.70
17.40
16.31
14.99
12.70
1.27
44

0.500

Reference
0.685
0.642
0.590

17.65
16.66
16.00
Reference
Reference

•

Notes

0.180
0.115
0.145
0.021
0.032
0.010
0.695
0.656
0.630

0.155
0.095
0.120
0.017
0.026
0.006
0.685
0.642
0.590

4.57
2.92
3.68
0.53
0.81
0.25
17.65
16.66
16.00

Reference
0.695
0.656
0.630

0.500
0.050
44

Reference
Reference

fJlI-~

-----------------~~I-------------------

5-3

Package InformatiaR

Drawing Q2

52 Pin Plastic Quad Flatpack (PQFP)

'I 'I

..

0,

1
2
3

I I

ill
W

Index
Mark

E3 E1

E

~II
~
A2 A1

JLB

A

e1
Rev. 6

Symbol

a
A
A1
A2
B

C
D
D1
D3
E
E1
E3
e1
L
N

Min
00
2.55
0.00
2.55
0.35
0.13
17.65
13.95

17.65
13.95

0.65

Family: Plastic Quad Flatpack
Millimeters
Inches
Max
Min
Max
Notes
80
00
80
3.05
0.100
0.120
0.010
0.25
0.000
2.80
0.100
0.110
0.50
0.014
0.020
0.23
0.005
0.009
18.15
0.695
0.715
14.05
0.549
0.553
12.00
Reference
0.472
18.15
0.695
0.715
14.05
0.549
0.553
12.00
Reference
0.472
1.00
Reference
0.0394
0.95
0.026
0.037
52
52

Notes

Reference

Reference
Reference

".,E
-------------------------------..,.,;-----------------------------5-4

Package Information

Drawing X2 44 Pin Ceramic PGA

,...-----------,A2-11-- r

876

A1

543

2

@@@@@

81

+

A

@~@@@@~@8

@@
E2 @@
@@
@@

@@c
@@o
@@E
@@F
~@@@@~
G
@@@@@
H

e1 _
I~.----

02 - - - - + j

Standoff
Pins,
4 Places
Rev. 6

Symbol
A
A1
A2
8
81
D
D2
E

E2
e1

L
N

Min
3.81

Family: Ceramic Pin Grid Array Package
Inches
Millimeters
Notes
Min
I Max
I Max

I

4.83

1.27
1.78
0.41

I

I

Typical
2.29
0.51

1.19
21.21

I
I
17.78
2.54
3.30
44

I

Diameter
Typical Dia.

0.070
0.016
0.835

f.,.·

I
I
0.700
0.100
0.130
44

Diameter
TYQical Dia.

0.865
Reference

0.700
0.835

Reference
Reference
Typical

i

•

Typical
0.090
0.020

0.047

Reference
21.97

I

Notes

0.190

0.050

21.97

17.78
21.21

0.150

0.865
Reference
Reference
Typical

----------------~.,,---------------

5-5

-=-=-_____________________
....
5-6
FIIli----------------45.=

---=' == == ==JE
--------- ---

-- -----

~~

r .....

~~_

~~

Sales Representatives
and Distributors

•

Section Index

Sales
Representatives
and Distributors ...................................................................................................................................................6-1

For additional information,
call800-TEAM-WSI (800-832-6974).
In California, Call 800-562-6363.

iF==~E

~ . . . ..-r ...
!!!iii~~_~=='
E

Domestic
Representatives

Sales Representatives and Distributors

________________________~_________________________________________________

ALABAMA

GEORGIA

MISSOURI

Rep. Inc.
Huntsville
Tel: (205) 881-9270
Fax: (205) 882-6692

Rep. Inc.
Tucker
Tel: (404) 938-4358
Tax: (404) 938-0194

John G. Macke Company
SI. Louis
Tel: (314) 432-2830
Fax: (314) 432-1456

ARIZONA

ILLINOIS

NEW JERSEY

Summit Sales
Scottsdale
Tel: (602) 998-4850
Fax: (602) 998-5274

Victory Sales
Hoffman Estates
Tel: (708) 490-0300
Telex: 206248
Fax: (708) 490-1499

Metro Logic Corp.
(AT&T only)
Fairfield
Tel: (201) 575-5585
Fax: (201) 575-8023

INDIANA

Strategic Sales, Inc.
Teaneck
Tel: (201) 833-0099
Fax: (201) 833-0061

CALIFORNIA
Bager Electronics, Inc.
Fountain Valley
Tel: (714) 957-3367
Fax: (714) 546-2654
Bager Electronics, Inc.
Woodland Hills
Tel: (818) 712-0011
Fax: (818) 712-0160
Earle Assoc., Inc.
San Diego
Tel: (619) 278-5441
Fax: (619) 278-5443
I Squared, Inc.
Santa Clara
Tel: (408) 988-3400
Fax: (408) 988-2079
CANADA
Intelatech, Inc.
Mississauga
Tel: (416) 629-0082
Fax: (416) 629-1795
COLORADO
Waugaman Associates, Inc.
Wheat Ridge
Tel: (303) 423-1020
Fax: (303) 467-3095

Giesting & Associates
Carmel
Tel: (317) 844-5222
Fax: (317) 844-5861
IOWA
Gassner & Clark Co.
Cedar Rapids
Tel: (319) 393-5763
Twx: 62950087
Fax: (319) 393-5799
KANSAS/NEBRASKA
C. Logsdon & Assoc.
Prairie Village
Tel: (913) 381-3833
Fax: (913) 381-9774
KENTUCKY
Giesting & Associates
Versailles
Tel: (606) 873-2330
Fax: (606) 873-6233
MARYLANDNIRGINIA
New Era Sales, Inc.
Severna Park
Tel: (410) 544-4100
Fax: (410) 544-6092

CONNECTICUT
Advanced Tech Sales
Wallingford
Tel: (203) 284-0838
Fax: (203) 284-8232
FLORIDA
OXi of Florida, Inc.
Fort Lauderdale
Tel: (305) 978-0120
Fax: (305) 972-1408
OXi of Florida, Inc.
Orlando
Tel: (407) 872-2321
Fax: (407) 321-2098
OXi of Florida, Inc.
SI. Petersburg
Tel: (813) 894-4556
Fax: (813) 894-3989

MASSACHUSETTS
Advanced Tech Sales, Inc.
North Reading
Tel: (508) 664-0888
Fax: (508) 664-5503

S.J. Associates, Inc.
MI. Laurel, NJ 08084
Tel: (609) 866-1234
Fax: (609) 866-8627

NEW MEXICO
S & S Technologies
Albuquerque
Tel: (505) 298-7177
Fax: (505) 298-2004

OKLAHOMA
West Associates
Tulsa
Tel: (918) 665-3465
Fax: (918) 663-1762
OREGON
Thorson Company
Northwest
Portland
Tel: (503) 293-9001
Fax: (503) 293-9007
PENNSYLVANIA
Giesting & Associates
Pittsburgh
Tel: (412) 828-3553
Fax: (412) 828-6160

NEW YORK

Metro Logic Corp.
(AT&T only)
Fairfield, NJ
Tel: (201) 575-5585
Fax: (201) 575-8023

Strategic Sales, Inc.
New York City
Tel: (201) 833-0099
Fax: (201) 833-0061

S.J. Associates, Inc.
MI. Laurel, NJ 08084
Tel: (609) 866-1234
Fax: (609) 866-8627

Tri-Tech Electronics, Inc.
East Rochester
Tel: (716) 385-6500
Twx: 62934993
Fax: (716) 385-7655

OXi of Florida, Inc
Fort Lauderdale
Tel: (305) 978-0120
Fax: (305) 972-1408

Tri-Tech Electronics, Inc.
Fayetteville
Tel: (315) 446-2881
Twx: 7105410604
Fax: (315) 446-3047
Tri-Tech Electronics, Inc.
Fishkill
Tel: (914) 897-5611
Twx: 62906505
Fax: (914) 897-5611

MICHIGAN

NORTH CAROLINA

Giesting & Associates
Comstock Park
Tel: (616) 784-9437
Fax: (616) 784-9438

Rep, Inc.
Morrisville
Tel: (919) 469-9997
Fax: (919) 481-3879

Giesting & Associates
Livonia
Tel: (313) 478-8106
Fax: (313) 477-6908

Giesting & Associates
Columbus
Tel: (614) 459-4800
Fax: (614) 459-4801

OHIO

MINNESOTA

Giesting & Associates
Cincinnati
Tel: (513) 385-1105
Fax: (513) 385-5069

OHMS Technology, Inc.
Edina
Tel: (612) 932-2920
Fax: (612) 932-2918

Giesting & Associates
Cleveland
Tel: (216) 261-9705
Fax: (216) 261-5624

PUERTO RICO

TENNESSEE
Rep. Inc.
Jefferson City
Tel: (615) 475-9012
Fax: (615) 475-6340

•

TEXAS
West Associates
Austin
Tel: (512) 343-1199
Fax: (512) 343-1922
West Associates
Houston
Tel: (713) 621-5983
Fax: (713) 621-5895
West Associates
Richardson
Tel: (214) 680-2800
Fax: (214) 699-0330

6-1

Sales Representatives and Distributors

Domestic
Representatives
(Cont.)

Domestic
Distributors

UTAH

WASHINGTON

WISCONSIN

Utah Component
Sales Inc.
Midvale
Tel: (801) 561-5099
Fax: (801) 561-6016

Thorson Company
Northwest
Bellevue
Tel: (206) 455-9180
Twx: 9104432300
Fax: (206) 455-9185

Victory Sales
Milwaukee
Tel: (414) 789-5770
Fax: (414) 789-5760

ALABAMA
Arrow/Schweber
Huntsville
Tel: (205) 837-6955
Fax: (205) 721-1581
Time Electronics
Huntsville
Tel: (205) 721-1133

ARIZONA
Arrow/Schweber
Tempe
Tel: (602) 431-0030
Fax: (602) 431-9555
Insight
Tempe
Tel: (602) 829-1800
Insight
Tucson
Tel: (602) 792-1800
Time Electronics
Tempe
Tel: (602) 967-2000
Wyle Laboratories
Phoenix
Tel: (602) 437-2088

Insight
Sunnyvale
Tel: (408) 720-9222
Time Electronics
Anaheim
Tel: (714) 669-0100
Time Electronics
Chatsworth
Tel: (818) 998-7200
Time Electronics
San Diego
Tel: (619) 578-2500
Time Electronics
Sunnyvale
Tel: (408) 734-9888
Time Electronics
Torrance
Tel: (213) 320-0880
Wyle Laboratories
Santa Clara
Tel: (408) 727-2500

COLORADO
Arrow/Schweber
Englewood
Tel: (303) 799-0258
Fax: (303) 799-0730
Insight
Aurora
Tel: (303) 693-4256
Time Electronics
Englewood
Tel: (303) 799-8851
Wyle Laboratories
Thornton
Tel: (303) 457-9953

CONNECTICUT
Arrow/Schweber
Wallingford
Tel: (203) 265-7741
Fax: (203) 265-7988
Time Electronics
Tel: (203) 271-3200

FLORIDA

Arrow/Schweber
AT&T DOES Center
Tel: (908) 949-7621
Fax: (201) 984-8908
Marsh Electronics
Schaumburg
Tel: (708) 240-9290
Time Electronics
Schaumburg
Tel: (708) 303-3000

INDIANA
Arrow/Schweber
Indianapolis
Tel: (317) 299-2071
Fax: (317) 299-2379
Time Electronics
Tel: (800) 331-5114

IOWA
Arrow/Schweber
Cedar Rapids
Tel: (319) 395-7230
Fax: (319) 395-0185
Time Electronics
Tel: (800) 325-9085

Wyle Laboratories
Rancho Cordova
Tel: (916) 638-5282

Arrow/Schweber
Deerfield Beach
Tel: (305) 429-8200
Fax: (305) 428-3991

Arrow/Schweber
Calabasas
Tel: (818) 880-9686

Wyle Laboratories
Irvine
Tel: (714) 863-9953

Arrow/Schweber
Lake Mary
Tel: (407) 333-9300

Arrow/Schweber
Lenexa
Tel: (913) 541-9542
Fax: (913) 541-0328

Arrow/Schweber
San Diego
Tel: (619) 565-4800

Wyle Laboratories
Irvine (Military Div.)
Tel: (714) 851-9953

Time Electronics
Tel: (305) 484-7778

Time Electronics
Tel: (800) 325-9085

Arrow/Schweber
San Jose
Tel: (408) 441-9700

Wyle Laboratories
Calabasas
Tel: (818) 880-9000

Arrow/Schweber
San Jose
Tel: (408) 432-7171

Wyle Laboratories
San Diego
Tel: (619) 565-9171

CALIFORNIA

Arrow/Schweber
Tustin
Tel: (714) 838-5422

FIX Electronics
Calabasas
Tel: (818) 591-9220

FIX Electronics
Mission Viejo
Tel: (714) 457-0298
Insight
San Diego
Tel: (619) 587-1100
Insight
Westlake Village
Tel: (818) 707-2101

6-2

Insight
Irvine
Tel: (714) 727-3291

OHMS Technology, Inc.
Edina, MN
Tel: (612) 932-2920
Fax: (612) 932-2918

CANADA
Arrow/Schweber
Bu rnaby, B. C.
Tel: (604) 421-2333
Arrow/Schweber
Dorval, Quebec
Tel: (514) 421-7411
Arrow/Schweber
Mississauga, Ontario
Tel: (416) 670-7769
Arrow/Schweber
Nepean, Ontario
Tel: (613) 226-6903

Time Electronics
Orlando
Tel: (407) 841-6565
Vantage Components
Altamonte Springs
Tel: (407) 682-1199
Vantage Components
Deerfield Beach
Tel: (305) 429-1001

GEORGIA
Arrow/Schweber
Duluth
Tei: (404) 497-1300
Time Electronics
Tel: (404) 448-4448

ILLINOIS
Arrow/Schweber
Itasca
Tel: (708) 250-0500

KANSAS

KENTUCKY
Time Electronics
Tel: (800) 331-5114

MARYLAND
Arrow/Schweber
Columbia
Tel: (301) 596-7800
Fax: (301) 596-7821
TIme Electronics
Baltimore
Tel: (301) 964-3090
Vantage Components
Columbia
Tel: (301) 720-5100
or: (301) 621-8555

Sales Representatives and Distributors

Domestic
Distributors
(Cont.)

MASSACHUSETTS

Arrow/Schweber
Wilmington
Tel: (508) 658-0900
Port Electronics
Tyngsboro
Tel: (508) 649-4880
Time Electronics
Peabody
Tel: (508) 532-9900
Wyle Laboratories
Burlington
Tel: (617) 272-7300
MICHIGAN

Arrow/Schweber
Livonia
Tel: (313) 462-2290
Fax: (313) 462-2686
Time Electronics
Tel: (800) 331-5114
MINNESOTA

Arrow/Schweber
Eden Prairie
Tel: (612) 941-5280
Fax: (612) 941-9405
Arrow/Schweber
Eden Prairie
Tel: (612) 941-1506
Fax: (612) 943-2086
MISSOURI

Arrow/Schweber
St Louis
Tel: (314) 567-6888
Fax: (314) 567-1164
Time Electronics
Manchester
Tel: (314) 391-6444
NEBRASKA

Time Electronics
Tel: (800) 325-9085
NEW JERSEY
Arrow/Schweber
AT&T DOES Center
Tel: (908) 949-7627
Fax: (201) 984-8708
Arrow/Schweber
Holmdel
Tel: (908) 949-4700
Fax: (908) 949-4035
Arrow/Schweber
Marlton
Tel: (609) 596-8000
Fax: (609) 596-9632
Arrow/Schweber
Pine Brook
Tel: (201) 227-7880
Fax: (201) 227-2064
Time Electronics
Marlton
Tel: (609) 596-6700

Time Electronics
N, New Jersey
Tel: (201) 882-4611
Vantage Components
Clifton
Tel: (201) 777-4100
NEW MEXICO
Insight
Tel: (505) 823-1800

OREGON

Almac/Arrow Electronics
Beaverton
Tel: (503) 629-8090
Fax: (503) 645-0611
Insight
Portland
Tel: (503) 644-3300

NEW YORK

Time Electronics
Portland
Tel: (503) 684-3780

Arrow/Schweber
Melville (Headquarters)
Tel: (516) 391-1300

Wyle Laboratories
Beaverton
Tel: (503) 643-7900

Arrow/Schweber
Hauppauge
Tel: (516) 231-1000
Fax: (516) 231-1072
Arrow/Schweber
Rochester
Tel: (716) 427-0300
Fax: (716) 427-0735
Time Electronics
Hauppauge (NYC)
Tel: (516) 273-0100
Time Electronics
East Syracuse
Tel: (315) 432-0355
Time Electronics
Rochester
Tel: (716) 383-8853
Vantage Components
Smithtown
Tel: (516) 543-2000
NORTH CAROLINA

Arrow/Schweber
Raleigh
Tel: (919) 876-3132
Fax: (919) 878-9517
Time Electronics
Tel: (800) 833-8235
NORTH DAKOTA

Time Electronics
Tel: (800) 331-5114
OHIO

Arrow/Schweber
Solon
Tel: (216) 248-3990
Fax: (216) 248-1106
Arrow/Schweber
Centerville
Tel: (513) 435-5563
Fax: (513) 435-2049

PENNSYLVANIA

Arrow/Schweber
Pittsburgh (Sales Office)
Tel: (412) 963-6807
Fax: (412) 963-1573
Time Electronics
Philadelphia
Tel: (215) 337-0900
Time Electronics
Pittsburgh
Tel: (800) 331-5114
Time Electronics
Marlton, NJ
Tel: (609) 596-6700
SOUTH DAKOTA

Time Electronics
Tel: (800) 331-5114
TEXAS

Arrow/Schweber
Austin
Tel: (512) 835-4180
Fax: (512) 832-9875
Arrow/Schweber
Carrollton
Tel: (214) 380-6464
Fax: (214) 248-7208
Arrow/Schweber
Houston
Tel: (713) 530-4700
Fax: (713) 568-8518
Insight
Austin
Tel: (512) 467-0800
Insight
Ft Worth
Tel: (817) 338-0800
Insight
Houston
Tel: (713) 448-0800

Time Electronics
Columbus
Tel: (614) 761-1100

Insight
Richardson
Tel: (214) 783-0800

OKLAHOMA

Time Electronics
Austin
Tel: (512) 339-3051

Arrow/Schweber
Tulsa
Tel: (918) 252-7537
Fax: (918) 254-0917

Time Electronics
Houston
Tel: (713) 530-0800
Time Electronics
Richardson
Tel: (214) 241-7441
Wyle Laboratories
Austin
Tel: (512) 345-8853
Wyle Laboratories
Houston
Tel: (713) 879-9953
Wyle Laboratories
Richardson
Tel: (214) 235-9953
UTAH

Arrow/Schweber
Salt Lake City
Tel: (801) 973-6913
Fax: (801) 972-0200
Time Electronics
West Valley
Tel: (801) 973-8181
Wyle Laboratories
West Valley
Tel: (801) 974-9953
WASHINGTON

Almac/ Arrow Electronics
Bellevue
Tel: (206) 643-9992
Fax: (206) 643-9709
Almac/Arrow Electronics
Spokane
Tel: (509) 924-9500
Fax: (509) 928-6096
Insight
Kirkland
Tel: (206) 820-8100
Time Electronics
Redmond
Tel: (206) 882-1600
Wyle Laboratories
Redmond
Tel: (206) 881-1150
WISCONSIN

Arrow/Schweber
Brookfield
Tel: (414) 792-0150
Fax: (414) 792-0156

II

Marsh Electronics
Milwaukee
Tel: (414) 475-6000
Time Electronics
Tel: (800) 331-5114

6-3

Sales Representatives and Distributors

International
Distributors

AUSTRALIA
GEC/George Brown
Rydalmare, N.S.W.
Tel: 61-2-638-t888
Fax: 61-2-638-1798

Microel
BP3
91941 Les Ulis
CEDEX
Tel: 33 (1) 69-07-08-24
Tlx: 692493F
Fax: 33 (1) 69-07-17-23

AUSTRIA
Eljapex
Eitnergasse 6
GERMANY
Jermyn GmbH
A-1232 Wein
Tel: (43) 222-86-15-31
6250 Limburg
Fax: (43) 222-86-15-31-200 Tel: (06) 431-5080
Fax: (06) 431-508289
BELGIUM, LUX
D&D Electronics bvba
Scantec GmbH
Antwerp
D-33 Planegg
Tel: 32-38277934
Tel: (089) 859-8021
Fax: 32-38287254
Tlx: 5213219
DENMARK
C-88 A/S
101 Kokkedallndustripark
DK-2980 Kokkedal
Tel: 45-42-24-48-88
Fax: 45-42-24-48-89
BRITISH ISLES
Micro Call, ltd.
Thame, Oxon OX9 3XD
Tel: 44-84-426-1939
Fax: 44-84-426-1678

HONG KONG
CET, ltd.
Tel: 852-520-0922
Fax: 852-865-0639

Nippon Imex Corporation
Setagaya-ku, Tokyo
Tel: 813-3-321-8000
Tlx: 78123444
Fax: 813-3-325-0021

FRANCE
A2M
B.P.89
78152 LE CHESNAY
CEDEX
Tel: 33 (1) 39-54-91-13
Tlx: 698376F
Fax: 33 (1) 39-54-30-61

INDIA
Pamir Electronics Corp.
400 West Lancaster
Devon, PA 19333 USA
Tel: 215-688-5299
Fax: 215-688-5382
Tlx: 210656 Pamir UR

KOREA
Eastern Electronics, Inc.
Kangnam-Ku, Seoul
Tel: 82-2-553-2997
Tlx: 78727381
Fax: 82-2-553-2998

REGIONAL SALES
Northeast
Stow, MA
Tel: (508) 685-6101
Fax: (508) 685-6105

Mid-Atlantic
Trevose, PA
Tel: (215) 638-9617
Fax: (215) 638-7326

Southwest
Irvine, CA
Tel: (714) 753-1180
Fax: (714) 753-1179

.:==
==== .., ==--

NORWAY
Nortec Electronics A/S
Postbox 123
N-1364 Hvalstad
Tel: 2-84-62-10
Fax: 2-84-65-45

Southeast
Dallas, TX
Tel: (214) 680-0077
Fax: (214) 680-0280
Northwest
Fremont, CA
Tel: (510) 656-5400
Telex: 289255
Fax: (510) 657-5916

EUROPE SALES
WSI- France
2 voie LA CARDON
91126 PALAISEAU
CEDEX, France
Tel: 33 (1) 69-32-01-20
Fax: 33 (1) 69-32-02-19

PORTUGAL
ATD Electronica, Lda.
Rua Faria de
Vasconcelos, 3-A
1900 Lisboa
Tel: 3511-847-2200
Fax: 3511-847-2197
SINGAPORE
Westech Electronics
Singapore 1334
Tel: 65-743-6355
Tlx: RS 55070
WESTEC
Fax: 65-746-1396
SPAIN
Sagitron
Corazon de Maria 80
28002 Madrid
Tel: 416-92-61
Tlx: 43819
Fax: 415-86-52
SWEDEN
Nortec Electronics A/B
Box 1830
S-171 27 Solna
Tel: 8-7051800
Fax: 8-836918
SWITZERLAND
Eljapex
Hardstr.72
CH - 5430 Wettingen
Tel: (41) 56-27-57-77
Fax: (41) 56-26-14-86
Laser & Electronic
Equipment
8053 Zurich
Tel: 41 (1) 55-33-30
Fax: 41 (1) 55-34-58

TAIWAN
Ally, Inc.
Taipei
Tel: 886-2-788-6270
Fax: 886-2-786-3550

ASIA SALES
WSI - Asia, ltd.
1006 C.C. Wu Bldg.
302-308 Hennessy Road
Wan Chai, Hong Kong
Tel: 852-575-0112
Fax: 852-893-0678

WSI-Germany
c/o B&RS
Rosenstrasse 7
8000 Munich 2, Germany
Tel: (49) 89.23.11.38.49
Fax: (49) 89.23.11.38.11

~ 47280 Kato Road

=- =

I'
II=:
I' ~ .=til .=tII.=tII

="'='

JAPAN
Internix, Inc.
Shinjuku Hamada
Bldg. 7-4-7
Nishi-Shinjuku, Shinjuku-Ku
Tokyo 160
Tel: 813-3-369-1105
Fax: 813-3-363-8486
Kyocera Corporation
Setagaya-ku, Tokyo
Tel: 813-3-708-3111
Tlx: 7812466091
Fax: 813-3-708-3864

Midwest
Hoffman Estates, IL
Tel: (708) 882-1893
Fax: (708) 882-1881

='

Topas Electronic GmbH
3000 Hannover 1
Tel: (0511) 13-12 -17
Tlx: 9218176
Fax: (0511) 13-12-16

ITALY
Comprel s.p.a.
20092 Cinisello B.
Milano
Tel: (02) 6120641/5
Tlx: 332484 COMPRL
Fax: (02) 6128158

HOLLAND
Arcobel bv
Griekenweg 25
5342 Px OSS
Tel: 31-4120-30335
Fax: 31-4120-30635

FINLAND
OY ComdaxAB
SF-00210 Helsingfors
Tel: 358-067-02-77
Tlx: 857125876
Fax: 358-06922326

WSI Direct
Sales Offices

Fax: (089) 857-6574

ISRAEL
Vectronics
60 Medinat Hayehudim St.
P.O. Box 2024
Herzlia B 46120, Israel
Tel: 972-52-556070
Tlx: 922342579
Fax: 972-52-556508

Fremont, CA 94538
Tel: (510) 656-5400
Fax: (510) 657-5916

Corporate
Headquarters
6-4

2/5/92 Rev. 1.52

LIFE SUPPORT POLICY:
WaferScale Integration, Inc. (WSI) products are not authorized for use as critical components in life support systems or devices without the express
written approval of the President of WSI. As used herein:

A) Life support devices or systems are devices or systems which 1) are intended for surgical implant into the body, or 2) support or sustain life
and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury or death to the user,
B) A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system or to affect its safety or effectiveness.
Information furnished herein by WaferScale Integration, Inc. (WSI) is believed to be accurate and reliable. However, no responsibility is assumed
for its use. WSI makes no representation that the use of its products or the interconnection of its Circuits, as described herein, will not infringe
on existing patent rights. No patent liability shall be incurred by WSI for use of the circuits or devices described herein. WSI does not assume
any responsibility for use of any circuitry described, no circuit patent rights or licenses are granted or implied, and WSI reserves the right without
commitment, at any time without notice, to change said circuitry or specifications. The performance characteristics listed in this book result from
specific tests, correlated testing, guard banding, design and other practices common to the industry. Information contained herein supersedes
previously published specifications. Contact your WSI sales representative for specific testing details or latest information.
Products in this book may be covered by one or more of the following patents. Additional patents are pending.
U.S.A: 4,328,565; 4,361,847; 4,409,723; 4,639,893; 4,649,520; 4,795,719; 4,763,184; 4,758,869;
5,006,974; 5,016,216; 5,014,097; 5,021,847; 5,034,786
West Germany: 3,103,160
Japan: 1,279,100
England: 2,073,484; 2,073,487
MagicPro,M is a trademark of WaferScale Integration, Inc.
IBM and IBM Personal Computer are registered trademarks of International Business Machines Corporation.
Copyright © 1991 WaferScale Integration, Inc. All Rights Reserved.
Patents Pending

Rev. 1.4

- - -_______________ f=E ,sE_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
=''=''==

6-5

•

Notes:

--------------------------------------~~~------------------------------------6:-~6

===;:E
--..... - .... r~'-

_
~_

----'
---- - ....~~

47280 Kato Road
Fremont, California 94538-7333
Phone: 510/656-5400
Fax: 510/657-5916
TELEX: 289255
800/ TEAM-WSI (800/832-6974)
In California 800/562-6363
Printed in U.S.A. 2192

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2013:08:13 18:33:21-08:00
Modify Date                     : 2013:08:14 11:17:14-07:00
Metadata Date                   : 2013:08:14 11:17:14-07:00
Producer                        : Adobe Acrobat 9.55 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:07860285-cb39-4e40-9564-667b02e76563
Instance ID                     : uuid:5566be12-1be8-8b43-83d1-3b5a1363e432
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 450

EXIF Metadata provided by EXIF.tools

1992_WSI_Programmable_Peripherals_Design_and_Applications_Handbook 1992 WSI Programmable Peripherals Design And Applications Handbook

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