1993_IDT_High Speed_CMOS_Logic_Design_Guide 1993 IDT High Speed CMOS Logic Design Guide
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1993
IDT High·Speed CMOS
Logic Design Guide
Includes Double-Density and
3.3V Application Notes
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Integrated Device Technology, Inc.
1993
High Speed CMOS
Logic Design Guide
TABLE OF CONTENTS
Introduction .. ... ..... ...... ... ... ........ ...... ... ........ ... ... ... ........ ......... ... ... ..... ...... ........... ... ... ... ... ... ..... ... ... ...... .......
Product Selector Guide ..........................................................................................................................
1
2
High Speed Design
AN-117
AN-102
AN-103
AN-116
AN-118
AN-47
AN-48
AN-49
AN-50
AN-51
AN-52
AN-53
AN-54
AN-82
Double-Density Logic Characteristics/and Applications ......................................................
Power Off Disable in lOT's Double-Density Family .............................................................
3.3V Logic ...........................................................................................................................
Decoupling Double-Density Components ...........................................................................
Maximum Frequency Considerations for the IDT49FCT805/6 ............................................
Simultaneous Switching Noise ............................................................................................
Using High Speed Logic. .... ..... ...... ... ... ........ ... ......... ..... ...... ...... ..... ...... ... ...... ........ ......... ... ...
Characteristics of PCB Traces ............................................................................................
Series Termination ..............................................................................................................
Power Dissipation in Clock Drivers .. ........... ... ... ...... ..... ...... ...... ..... ...... ... ...... ........... ... ...... ...
FCT Output Structures and Characteristics ................ ...... ...... ..... ...... ... ..... ...... ........... ........
Power-Down Operation .......................................................................................................
FCT-T Logic Family .............................................................................................................
Clock Distribution with IDT Guaranteed-Skew Clock Drivers ..............................................
6
25
27
35
39
41
49
50
54
56
58
61
63
71
Error Detection and Correction
Designing with the IDT49C460 and IDT39C60 Error Detection and Correction Units ........
Protecting your Data with IDT49C465 32-Bit FlowThru EDC Unit ......................................
Error Detection and Correction with 49C466 ..... ........ ... ... ...... ..... ... ... ... ...... ..... .............. ... ....
Cascading 49C460 and 49C465 ........ ........... ... ........ ...... ...... ..... ...... ... ... ..... ... ... ... ... ... ..... .....
82
96
112
123
Conference Papers
CP-10
Integrated Line Termination Solutions for High Speed Logic ..............................................
CP-11
New Output Structure Designs Reduce System Noise Problems .......................................
CP-12
Double-Density Logic: the Fast. Flexible Family ................................................................
CP-13
Mixed Supply Design Considerations for Notebook PCs ....................................................
127
130
135
139
AN-24
AN-64
AN-94
AN-96
Integrated Device Technology, I nco reserves the rightto make changes to its products or specifications at any time, without notice, in order
to improve design or performance and to supply the best possible product. lOT does not assume any responsibility for use of any circuitry
described other than the circuitry embodied in an lOT product. The Company makes no representations that circuitry described herein is
free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise
under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
LIFE SUPPORT AGREEMENT
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a
specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of lOT.
1. Life fupport devices or systems are devices or sytems which (1) are intended for surgical implant into the body or (b) support or
sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness.
The lOT logo is a registered trademark, and BiCameral, BurstRAM, BUSMUX, CacheRAM. DEenat, Double~Density, FASTX, FourFort, FLEX1-CACHE, FLEX)"PAK, Flow-thruEDC, 10Tlc, JOTenvY. IDT/sae,
IDTfsim, IDT/ux, MacStation; MICROSUCE, PaietteDAC,REALB, R3051 , R3081 , RISCompiler, RISController, RISCors, RISC SubSystem, RISCwindows, SARAM, SmartLogic, SyncFIFO, SyncBiFIFO, SPC,
TargetSystem and WideBus are trademarks of Integrated Device Technology. Inc.
All others are trademarks of their respective companies.
ii
INTRODUCTION
This collection of application notes and conference papers
is presented to provide information which has been proven
useful to the designers who use or plan to use high-speed
TIL-compatible, CMOS logic in high-performance systems.
These notes cover a broad range of topics; some discuss
aspects of high-speed design with new application notes
specifically related to the new Double-Density family. Also
included are application notes on error detection and correction.
Double-Density Family Defined
The demand for higher integration and high speed continues to push the need for high-performance, high-density logic
families. IDT has recently introduced a new series of extraquiet, high-performance, 16-, 18-, and 20-bit logic functions.
This exciting new family offers users significant board area
savings, power savings, higher speeds, excellent guaranteed
low noise characteristics, and guaranteed low output skew.
The Double-Density family is the premiere octal upgrade and
is considered the high-speed, low-power replacement for all
existing CMOS and SiCMOS wide bus width products.
High Speed Design
With the push for higher clock rates to increase system
performance in a predominantly TIL world, the hardware
designer is now required to deal with problems and issues
which were largely academic only a few years ago. The
introduction of high-speed, high-drive CMOS logic, combined
with the increased packing density of multi-layer boards has
resulted in the awareness and the need to deal with problems
such as ground bounce, transmission line effects, and dynamic power dissipation.
Error Detection and Correction
Today's high-performance systems are becoming increasingly DRAM intensive. IDT has developed a range of highperformance EDC devices that eliminate the performance
penalties once associated with these circuits while assuring
the designer continuous, error-free operation necessary in
high-reliability systems.
ABOUT THE PRODUCT SELECTOR GUIDE
Pages 2-5 contain the 1993 IDT Logic Product Selector
Guide. The data book page numbers are preceded by the
alpha character "G". This signifies the IDT 1992/1993 HighPerformance Logic data book. Following the character will be
the section number and the page number, consecutively.
"CALL" might appear in the page number area as well. This
means the data sheet was not included in the data book. A
copy of the data sheet may be obtained by contacting IDT's
Literature Department at (800) 345-7015 [( 408) 492-8674], or
from your local sales representative.
Shaded areas indicate new products introduced since the
last publication of the product selector guide.
Boldface type indicates an improved IDT product feature.
The availability column shows the date when limited production quantities will be available.
The symbol ..... after the data book page number indicates
further updated information has become available since the
publication of the 1992/1993 High-Performance Logic data
book. This information should be available from your 10caiiDT
sales office.
High-Speed CMOS Logic Products -
Bus Interface Devices
o
FCT and FCT-T CMOS families are the fastest in the
industry with maximum propagation delays as low as 3.6 ns.
2.
24mA balanced output drive with on-chip resistors for
internal bus and point to point driving.
o
The FCT-T family offers the lowest-power solution. No other
logic family uses less dynamic power, standby power, or static
high or low power.
3.
3.3V bus interface logic for systems with 3.3V regulated
supplies.
o
o
The clock driver family provides guaranteed low-skew clock
distribution in a variety of configurations.
The new Double-Density bus interface family offers users
significant board area savings, power savings, higher speeds,
guaranteed low noise, and a choice of output drive characteristics. Three configurations are available:
1.
Standard 64mA high drive device for bus and backplane
interface.
o
The EDC (Error Detection and Correction) devices can detect
multiple errors as fast as 10ns and correct as fast as 14ns.
o
IDTfeatures a series of read-write buffers with 8& 18 bit bidirectional registers and 16-bit pipeline registers.
o
The DSP Building Blocks are composed of 16-bit ALUs, Multipliers, and Multiplier-Accumulators with speeds as fast as20ns.
o
Parity generation and checking circuits designed to minimize
part count and maximize parity checking time.
Max. Speed (ns)
Max.
Power
Description
Mil.
Com'l.
(mW)
Avail.
Page
IDT29FCT52A1B/C
IDT29FCT52AT/BT/CT/DT
Non-inverting Octal Registered
Transceiver
7.3
4.5
1.0
NOW
G 6.26
G 6.1
IDT29FCT53A1B/C
IDT29FCT53AT/BT/CT
Inverting Octal Registered
Transceiver
7.3
6.3
1.0
NOW
G 6.26
G6.1
IDT29FCT520A/BIC
IDT29FCT520AT/BT/CT/DT
Multi-level Pipeline Register
7.0
5.2
1.0
NOW
G6.27
G6.2
IDT29FCT521 AT/BT/CT/DT
Octal Multi-level Pipeline
Register (level 1 replaced)
7.0
5.2
1.0
NOW
G 6.2
IDT54/74FCT1381A1C
IDT54/74FCT138T/AT/CT
1-of-8 Decoder
6.0
5.1
1.0
NOW
G6.29
G 6.3
IDT54174FCT139/A1C
IDT54174FCT139T/AT/CT
Duall-of-4 Decoder
6.2
5.0
1.0
NOW
G6.30
G 6.4
IDT54175FCT151 T/AT/CT
8-lnput Multiplexer
6.2
5.6
1.0
NOW
G 6.5
3.9
1.0
NOW
CALL
Part Number
Data
Book
FCT/FCT-T FAMILY
IDT54174FCT157T/AT/CT/DT
Quad 2-input Multiplexer
5.0
IDT54174FCT161/A
IDT54174FCT161T/AT/CT
Synchronous Binary Counter
w/Synchronous Reset
6.3
5.8
1.0
NOW
G 6.31
G6.7
IDT54/74FCT163/A
IDT54/74FCT163T/AT/CT
Synchronous Binary Counter
w/Asynchronous Master Reset
6.3
5.8
1.0
NOW
G 6.31
G6.7
IDT54/74FCT1821A
Carry Lookahead Generator
10.7
7.0
1.0
NOW
G 6.32
IDT54/74FCT191/A
Up/Down Binary Counter
10.5
7.8
1.0
NOW
G 6.33
IDT54/74FCT193/A
Up/Down Binary Counter
6.9
6.5
1.0
NOW
G 6.34
IDT54/74FCT240/A/C
IDT54/74FCT240TIAT/CT/DT
Inverting Octal Buffer Line Driver
4.7
3.6
1.0
NOW
G 6.35
G 6.10
IDT54/74FCT241/A1C
IDT54/74FCT241T/AT/CT/DT
Inverting Octal Buffer Line Driver
4.6
3.6
1.0
NOW
G 6.35
G 6.10
IDT54/74FCT244/A1C
IDT54/74FCT244T/AT/CT/DT
IDT54/74FCT3244/A
Inverting Octal Buffer Line Driver
4.6
3.6
1.0
NOW
4.8
1.0
NOW
G 6.35
G 6.10
G7.7
4.5
3.8
1.0
NOW
3.3V Inverting Octal Buffer Line Driver
IDT54/74FCT2451A1C
IDT54174FCT245T/AT/CTIDT
IDT54/74FCT3245/A
Inverting Octal Buffer Transceiver
3.3V Inverting Octal Buffer Transceiver
4.6
1.0
NOW
IDT54/74FCT257T/AT/CT/DT
Quad 2-input Multiplexer w/OE
5.0
3.9
1.0
NOW
CALL
IDT54174 FCT273/A1C
IDT54174FCT273T/AT/CT/DT
Octal D Flip-Flop with Reset
6.5
5.8
1.0
NOW
G 6.37
IDT54/74FCT2991AlC
IDT54/74FCT299/AT/CT
Octal Universal Shift Register
w/Common Parallel 110 Pins
7.5
6.5
1.0
NOW
G 6.38
G 6.13
IDT54174FCT3731AlC
IDT54174FCT373T/AT/CT/DT
Octal Transparent Latch
5.1
3.8
1.0
NOW
G 6.39
G 6.14
2
•
G 6.36
G 6.11
G7.8
•
Hiah-Seeed CMOS Loaic Products
Max. Speed (ns)
Mil.
Com'l.
Max.
Power
!mWI
Avail.
Data
Book
Paae
Part Number
Descrietion
IDT54174FCT374/A/C
IDT54/74FCT374T/AT/CT/DT
Octal D Register
6.2
4.2
1.0
NOW
G 6.40
CALL
IDT54/74FCT377IA1C
IDT54/74FCT377T/AT/CT/DT
Octal D Flip-Flop w/Clock Enable
5.5
4.4
1.0
NOW
G 6.41
G 6.16
IDT54/74FCT399/A
IDT54/74FCT399T/AT/CT
Quad Dual-Port Register
6.6
6.1
7.0
NOW
G 6.42
G 6.17
IDT54175FCT521/A/B/C
IDT54174FCT521T/AT/BT/CT
8-Bit Identity Comparator
5.1
4.5
1.0
NOW
G 6.43
G 6.18
IDT54174FCT533/A/C
IDT54174FCT533T/AT
Inverting Octal Transparent
Latch w/3-State
5.1
4.7
1.0
NOW
G 6.39
G 6.14
IDT54/74FCT534/A/C
IDT54/74FCT534T/AT/CT
Inverting Octal D Register
w/3State
6.2
5.2
1.0
NOW
G 6.40
G 6.15
IDT54/74FCT540/AlC
IDT54/74FCT540T/AT/CT
Inverting Octal Buffer/Line Driver
4.7
4.3
1.0
NOW
G6.35
G 6.10
IDT54/74FCT541/A/C
IDT54/74FCT541T/AT/CT
Non-Inverting Octal Buffer/Line
Driver
4.7
4.3
1.0
NOW
G 6.35
G 6.10
IDT54/74FCT543/A1C
IDT54/74FCT543T/AT/CT/DT
Non-Inverting Octal Latched
Transceiver
6.1
4.4
1.0
NOW
G 6.44
G 6.19
IDT54174FCT573/A1C
IDT54/74FCT573T/AT/CT/DT
Octal Transparent Latch
5.1
3.8
1.0
NOW
G 6.39
G 6.19
IDT54/74FCT574/A1C
IDT54/75FCT574T/AT/CT/DT
Octal D Register wi 3-State
6.2
4.2
1.0
NOW
G 6.40
G 6.15
IDT54/74FCT620T/AT/CT
Inverting Octal Bus Transceiver
w/3-State
5.1
4.5
1.0
NOW
G 6.21
IDT54174FCT621T/AT
Non-Inverting Octal Bus
Transceiver w/Open Drain
12.5
12.0
1.0
NOW
G6.22
IDT54/74FCT623T/AT/CT
Non-Inverting Octal Bus
Transceiver w/3-State
5.4
4.8
1.0
NOW
G 6.21
IDT54174FCT640/AlC
IDT54/74FCT640T/AT/CT
Inverting Octal Transceiver
4.7
4.4
1.0
NOW
G 6.36
G 6.11
IDT54174FCT645/A1C
IDT54174FCT645T/AT/CT/DT
Non-Inverting Bidirectional
Transceiver
4.5
3.8
1.0
NOW
G 6.36
G 6.11
IDT54/74FCT646/A1C
IDT54/74FCT646T/AT/CT/DT
Octal Transceiver/Register
6.0
4.4
1.0
NOW
G 6.45
G6.20
IDT54/74FCT648T/AT/CT
Octal Transceiver/Register
6.0
5.4
1.0
NOW
G 6.20
IDT54/74FCT651T/AT/CT
Inverting Octal Registered
Transceiver
6.0
5.4
1.0
NOW
G 6.20
IDT54/74FCT652T/AT/CTIDT
Non-Inverting Octal Registered
Transceiver
6.0
4.4
1.0
NOW
G 6.20
IDT54174FCT821 AlBIC
IDT54174FCT821AT/BT/CT
10-Bit Non-Inverting Register
7.0
6.0
1.0
NOW
G 6.46
CALL
IDT54/74FCT823A1B1C
9-Bit Non-inverting Register
IDT54174 FCT823AT/BT/CT/DT
7.0
5.0
1.0
NOW
G 6.46
G 6.23
IDT54/74FCT825A/B/C
IDT54/74FCT825AT/BT/CT
7.0
6.0
1.0
NOW
G 6.46
G 6.23
5.0
3.8
1.0
NOW
G 6.47
G 6.24
IDT54174FCT828AT/BT/CT/DT 10-Bit Inverting Register
5.0
3.8
1.0
NOW
G6.24
IDT54174FCT833A1B
8-Bit Transceiver w/Parity
10.0
7.0
1.0
NOW
G 6.48
IDT54/74FCT841 AlBIC
IDT5417 4FCT841 ATlBT/CTIDT
10-Bit Non-Inverting Latch
6.3
4.2
1.0
NOW
G 6.49
G 6.25
IDT54/74FCT843A1B1C
IDT54174FCT843AT/BT/CT
9-Bit Non-Inverting Latch
6.3
5.5
1.0
NOW
G 6.49
G 6.25
8-Bit Inverting Register
10-Bit Non-Inverting Buffer
IDT54/74FCT827AlBIC
IDT54/7 4FCT827AT/BTlCT/DT
3
•
•
High-Speed CMOS Logic Products
Max. Speed (ns)
Com'l.
Mil.
Max.
Power
(mW)
Avail.
Data
Book
Page
Part Number
Description
IDT54/74FCT845A1B1C
IDT54/74FCT845AT/BT/CT
8-Bit Non-Inverting Latch
6.3
5.5
1.0
NOW
G 6.49
G 6.25
IDT54/74FCT861A1B1C
1O-Bit Non-Inverting Transceiver
6.5
6.0
1.0
NOW
G 6.50
IDT54/74FCT863A1B1C
9-Bit Non-Inverting Transceiver
6.5
6.0
1.0
NOW
G 6.50
Clock Driver w/Guaranteed Skew
6.8
5.8
1.0
NOW
G 6.28
CLOCK DRIVER FAMILY
IDT49FCT805lA
iQW~ff«too$l.lltl¢m:::II,I::I:}I'
,: : : : : : : : : : : : : : .: :.: • ':.::.,,:::• ;,/", rrIm:rm ::::::::::::::::I:'\j.;.::.:';'."I~II41§ mr:I:rr1i9.I
IDT49FCT806/A
Inverting Clock Driver
.
6.8
5.8
1.0
rIIMAi!!!~~:~:rJti~MI
NOW
:. ::' ~ ~~ ~~ :: :; =:' :; =; :; ::' ::: ::: :: :; ~: ;:
:..:.::::::::::::::::: ::',::.:'
. . . , , ' , ' , ' , ' , . ' , " : : ",::
:':
..:.:.:
; ,;.
. .: " .: :: :: :; :: :: :: .;. ,
,~.: ,i.~·
.......
,,',"',.:::::
::.:::;
:: :: :: ::: . ,: :: :: :: '. " : :: .: "
. .;:
~~ ~~ ~~ ::~ ~; :: :~ =; :: ::: " .
. . " . " .; .; :. :. ,,' ,'; ;: :.
. . , , ' , ' , ',' ::::; .;::::;.:".
Low Skew PLL-Based Clock Driver
N/A
N/A
1.0
Q2'93
CALL
16-Bit Buffer/Line Driver
4.7
4.3
0.006
NOW
G 5.1
G 5.1
IDT54/74FCT16244T/AT/CT
IDT54/74FCT162244T/AT/CT
16-Bit Buffer/Line Driver
4.6
4.1
0.006
NOW
G 5.2
G 5.2
IDT54/74FCT16245T/AT/CT
IDT54/74FCT162245T/AT/CT
16-Bit Bidirectional Transceivers
4.5
4.1
0.006
NOW
G 5.3
G 5.3
IDT54174FCTI6373T/AT/CT
IDT54/74FCT162373T/AT/CT
16-BitTransparent Latches
5.1
4.2
0.006
NOW
G 5.4
G 5.4
IDT54/74FCT16374T/AT/CT
16-Bit Register (3-State)
6.2
5.2
0.006
NOW
G 5.5
G5.5
16-Bit Bus Transceiver/Registers
(3-State)
6.0
5.4
0.006
NOW
IDT54174FCT162646T/AT/CT
G5.9
G 5.9
IDT5417 4FCT16500AT/CT
IDT5417 4FCT162500AT/CT
18-Bit Registered Bus Transceiver
(3-State)
5.1
4.6
0.006
NOW
G 5.6
G 5.6
IDT54/74FCT16501AT/CT
IDT54/7 4FCT162501ATlCT
18-bit Registered Bus Transceiver
(3-State)
5.1
4.6
0.006
NOW
G5.7
G5.7
IDT54/74FCT16543T/AT/CT/DT 16-Bit Latched Transceiver
IDT54/74FCT162543T/AT/CT/DT
6.1
4.4
0.006
NOW
G 5.8
G 5.8
IDT54/74FCT16952T/AT/CT/DT 16-Bit Registered Transceivers
IDT54/74FCT162952T/AT/CT/DT
7.3
4.5
0.006
NOW
G 5.11
IDT54/74FCT88915
5V DOUBLE-DENSITY FAMILY
IDT54/74FCT16240T/AT/CT
IDT54174FCTI62240T/ATICT
IDT54174FCT162374T/AT/CT
IDT54174FCT16646T/AT/CT
IDT54/74FCT16652T/AT/CT
IDT54/74FCT162652T/AT/CT
16-Bit Transceiver/Registers
6.0
5.4
0.006
NOW
G 5.10
IDT54174FCTI6823AT/BT/CT
18-Bit Bus Interface Registers
7.0
6.0
0.006
NOW
G 5.12
20-Bit Buffers
5.0
4.4
0.006
NOW
G 5.13
IDT54174FCT162823AT/BT/CT
IDT54174FCTI6827AT/BT/CT
:]ii'r
G6.28
IDT54174FCTI62827AT/BT/CT
3.3V DOUBLE-DENSITY FAMILY
IDT54/74FCT163244/A
3.3V CMOS 16-Bit Buffer/Line Driver
4.8
0.006
NOW
G7.1
IDT54174FCT1632451A
3.3V CMOS 16-Bit Bidirectional
Tranceivers
4.6
0.006
NOW
G7.2
4
•
High-Speed CMOS Logic Products
Max.
Power
(mW)
Avail.
6.3
0.006
NOW
Max. Speed (ns)
Com'l.
Mil.
Data
Book
Page
Part Number
Description
IDT54/74FCT164245T
CMOS 16-Bit Bidirectional3.3V to
5V Translator
IDT54/74FCT163373/A
3.3V CMOS 16-Bit Bidirectional Latches
5.2
0.006
NOW
G 7.3
IDT54/74FCT163374/A
3.3V CMOS 16-Bit Register
5.2
0.006
NOW
G7.4
IDT54/74FCT163646/A
3.3V CMOS 16-bit Bus Transceiverl
Registers
6.3
0.006
NOW
G 7.6
IDT54/74FCT163501/A
3.3V 18·Bit Registered Bus Transceiver
5.1
0.006
NOW
G7.5
ERROR DETECTION AND CORRECTION
G 7.9
Detect Time
IDT39C60
IDT39C60-1
IDT39C60A
IDT39C60B
16·bit Cascadable EDC
Replaces Am2960, -1, A; N2960,
MC74F2960, -1, A
36
28
24
22
32
25
20
18
300
NOW
NOW
NOW
NOW
G 8.10
IDT49C460
IDT49C460A
IDT49C460B
IDT49C460C
IDT49C460D
32-bit Cascadable EDC
Replaces Am29C660.
Functional equivalent to DP8402;
ASJALS632
44
33
28
21
16
40
30
25
16
12
350
NOW
NOW
NOW
NOW
NOW
G 8.11
G 8.11
G 8.11
G 8.11
G 8.11
IDT49C465/A
32-bit Flow-thruEDC'" two separate
bidirectional 32-bit buses; expandable
to 64-bit, 144-pin PGA.
15
20
400
NOW
G 8.12
IDT49C466
64-bit Flow-thruEDC-two separate
bidirectional 64-bit buses; 208-pin PGA
25
20
500
NOW
G 8.13
73200
16-bit 8-level-deep pipeline
Register; replaces four Am29520s
12
10
150
NOW
G 8.7
73201
16-bit 7-level-deep pipeline
Register with pass-through mode
12
10
150
NOW
G 8.7
73210/AlB
8-bit bidirectional registers with
parity; two registers from B to A
7.5
6.0
50
NOW
G 8.8
73211/A1B
8-bit bidirectional registers with
parity; one register from B to A
7.5
6.0
50
NOW
G8.8
IDT7381
16-bit cascadable ALU
(replaces Logic Devices' L4C381)
20
16
150
NOW
G 8.6
IDT7383
16-bit cascadable ALU
(32 instructions)
20
16
150
NOW
G 8.6
IDT7210L
16 x 16-bit with 35-bit output,
replaces TDC1010J
20
16
225
NOW
G8.4
IDT7216L
16 x 16-bit, replaces Am29516
20
16
200
NOW
G 8.5
IDT7217L
16 x 16-bit with single-clock
architecture, replaces Am29516
20
16
200
NOW
G 8.5
350
NOW
NOW
NOW
G 8.2
READ-WRITE BUFFERS
DSP BUILDING BLOCKS
MICROSLICETM PRODUCTS
(Com'I.)
= 47ns
= 37ns
= 28ns
IDT49C402
IDT49C402A
IDT49C402B
16-Bit Zf!P Slice, quad 2901
with 8 additional destination
functions and 64 x 16 register file
capacity-superset of Am29Cl 01,
CY7C91 01 , WS159016
IDT39Cl0B
IDT39Cl0C
12-bit Sequencer with 33-deep stack
-replaces AM291 O/A, CY7C910
o to Y = 20ns
o to Y = 12ns
150
NOW
NOW
G 8.2
IDT49C410
IDT49C410A
16-bit Sequencer with 33-deep stack
address up to 64K microcode
Dto Y = 20ns
to Y = 12ns
150
NOW
NOW
G 8.3
A,B addr to Y
A,B addr to Y
A,B addr to Y
o
5
- ---- -
-----
~
W
[.7
APPLICATION
DOUBLE-DENSITYTM LOGIC
NOTE
CHARACTERISTICS AND APPLICATIONS
AN-117
Integrated Device Technology, Inc.
By Anupama Hegde and Stanley Hronlk
TABLE OF CONTENTS
INTRODUCTION
The increasing demand for integration in computer systems has lead to the evolution of logic components with wider
buses and highly integrated functionality. Shorter delays and
fewer components are welcome features when board space
and performance are at a premium. With such increased
integration and increased ciock speeds, power dissipation
and simultaneous switching noise become important issues.
In the light of such developments, IDT has introduced a new
16-bit wide logic family - Double-Density - to address the
system designer's need for increased performance, reduced
noise and low power dissipation. The family not only doubles
the number of bits in a single package but also offers users
other features such as a small package size, extremely low
power dissipation, low leakage, reduced ground bounce and
a very friendly user interface. The Double-Density logic family
is an extension of IDT's Fast CMOS TTL-compatible (FCT-T)
line of logic products. These devices are built using IDT's submicron CMOS 5E technology.
The Double-Density logic family consists of three subfamilies, each of which seeks to address specific design
needs. The first is the High-Drive FCT16xxxT family, designed for backplane and other applications that require a high
static and dynamic output drive capability. The second is the
Balanced-Drive FCT162xxxT family. This family features a
balanced output drive and has excellent noise characteristics,
which is a central issue to most high-speed applications. The
last is the Low Voltage (3.3V), FCT163xxx family which is
aimed at low-power, high-performance design applications.
For a detailed discussion of the FCT163xxx family, please
refer to Logic Application Note, AN-103 ( "3.3V Logic" ). All
three Double-Density sub-families offer lower power solutions
than their industry counter parts.
This application note discusses IDT's Double-Density HighDrive and Balanced-Drive families which are designed to give
the best cost/performance ratio in a variety of applications. It
provides useful information needed to evaluate and/or design
in these devices. The focus is on the families' features and
benefits, product characteristics and design guidelines. The
application note is divided into several sections, each dealing
with a specific characteristic or feature of the family. Design
information and actual data on the Double-Density FCT16xxxT
and FCT162xxxT families are provided in the form of graphs
and tables making them easier to interpret and access. In
cases where the characteristics are common to both the
FCT16xxxT and FCT162xxxT families, only one graph is
given for both families.
PAGE
DOUBLE-DENSITY LOGIC FAMILIES
Description ..............................................................
7
DOUBLE-DENSITY FAMILY FEATURES
Functions ................................................................
Speed grades .........................................................
Operating range ..... ..... ... ............ ..... ... ... ... ........ ... ....
7
7
7
DC ELECTRICAL CHARACTERISTICS
Input characteristics .. ........ ...... ... ...... ..... ... ...... ... ......
Output characteristics.............................................
Power dissipation.. ... ..... ... ... ... ... ... ..... ......... ........ .....
Static and dynamic drive .........................................
8
9
11
12
AC PERFORMANCE
AC test conditions...................................................
Propagation delay.. ... ........... ...... ........ ... ...... ... ..... ....
Rise and fall time .. ........ ... ... ... ... ... ........... ................
Enable and disable times ........................................
Skew .......................................................................
Simultaneous switching noise .................................
13
14
15
16
17
17
MISCELLANEOUS ISSUES
ESD ........................................................................
Decoupling ........ ..... ... ......... ... ..... ...... ... ... ..... ...... ......
Maximum input rise and fall times ..........................
Unused inputs .. ...... ..... ... ... ... ........ ...... ......... ..... .......
19
19
19
19
SUMMARY ................................................................
19
APPENDIX A
Balanced-Drive capability........ ........ ...... ... ..... ... ... ...
APPENDIXB
Standard device specifications ...............................
APPENDIXC
Package information .. ... ... .............. ........ ... ... ... ... .....
The lOT logo is a registered trademark and Double-Density is a trademark of Integrated Device Technology, Inc.
6
20
21
24
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
DOUBLE-DENSITY LOGIC FAMILIES
DOUBLE-DENSITY FAMILY FEATURES
lOT's Double-Density FCT16xxxT and FCT162xxxT device fam ilies are an extension olthe lOT FCT-T (Fast Cm as TILcompatible - TIL level output swings) family. Many of the
features discussed in this application note are common to all
three Double-Density families, but since this document deals
exclusively with the FCT16xxxT High-Drive and the
FCT162xxxT Balanced-Drive devices, all further references
to lOT Double-Density are used in connection with these last
two families.
Description
lOT's Double-Density product line is comprised of 16, 18
and 20-bit fast CMOS interface parts available in 48 and 56 pin
dual-in-line surface mount packages. Three broad families are
available to serve different market segments.
FCT16xxxT High-Drive Family
The key features of the FCT16xxxT family are high static
and dynamic drive. This family includes drivers which a
suitable for driving low-impedance busses, back planes or
heavily terminated lines while retaining excellent noise immunity. Certain standards such as the VME bus electrical
specification require a high static output drive for which
FCT16xxxT devices are a good choice. Low-impedance and
high-capacitance driving ability are the hallmarks of the HighDrive family.
Functions
Double-Density devices, as the name indicates, are comprised of two byte-wide functions on a single die, in a single
package. These components offer 16,18 or 20-bit bus widths
with control signals for each group of 8, 9 or 10 bits (for
standard functions) that correspond to their octal counterparts. This allows designers to use these new devices without
changing their system architecture. Most of the popular octal
functions are available in the Double-Density family.
In addition to the dual byte-wide functions, there are several
new functions available in Double-Density which broaden the
product line offerings beyond the octal capabilities. These
products take advantage of the larger pin counts of the
packages by offering increased functionality while providing
single control pins for both bytes.
FCT162xxxT Balanced-Drive Family
The FCT162xxxT family offers controlled edge rates and
Balanced-Drive resulting in reduced undershoot and overshoot. Balanced-Drive components significantly reduce board
level noise and solve many of the transmission line problems
that develop with high-speed logic.
The Balanced-Drive output structure has been designed to
match the impedance of a typical transmission line for effective line driving. This is accomplished through a symmetric
pull-up and pull-down current drive capability during transitions, and through integrated source-termination. The source
termination emulates external series termination without severely limiting the drive capability of the device. The Balanced-Drive characteristics provide transmission line matching for signals undergoing both HIGH and LOW transitions. In
addition, controlled output transitions reduce EMI and RFI
effects. The main features of the Balanced-Drive family are
reduced ground bounce, fewer line reflections and smaller
over/undershoot making it very effective for point-to-point line
driving. For further details on the Balanced-Drive implementation refer to Appendix A.
Speed Grades
The Double-Density components are specified at the same
speed asthe industry standard FCT/FCT-Tfamily. This means
that existing deSigns can be upgraded to reduce space and
improve performance with very little effort.
Operating Range
lOT Double-Density family components have been characterized and specified over the extended commercial temperature range (industrial range) of -40 °C to +85°C and the
power supply(Vcc) range of ±10% to be consistent with the
trend to offer system deSigners a wider operating range and
greater operating margin.
FCT163xxx Low-Voltage(3.3V) Family
lOT's LOW Vcc family is intended for use with a regulated
3.3V power supply and has been developed to maintain
system speed at lower voltages. A benefit of using the reduced
power supply is the significant reduction in the overall system
power consumption. These devices will interface with the
future and existing 3.3V devices. The family is designed to be
TTL compatible and meets the J EDEC standard 8-1 A for lowvoltage interfacing. Another benefit of the low-voltage family is
the decreased switching noise due to a reduction in overall
output voltage swing. These devices are ideal for use in laptop
and notebook computer designs. Space applications will also
benefit from the lower noise and power levels from using a
lower Vcc. lOT's low-voltage 163xxx family uses the same
process technology as the other 5V Double-Density families,
meaning that at 3.3V supply, the 163xxx family provides an
excellent reliability margin due to minimal part stress.
7
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
DC ELECTRICAL CHARACTERISTICS
on voltage below ground, the input clamp diode turns on as
shown by the increase in current around -0.6V. The diode
clamps negative voltage spikes at the input.
Balanced-Drive and High-Drive devices have no clamp
diode to Vee at the input. Consequently, voltages much
higher than Vee can be tolerated with input breakdown occurring at approximately 14V as shown in Figure 3. These
characteristics apply to pure inputs only, whereas I/O{inpuV
output) pins will follow the characteristics shown in Figure 8.
INPUT CHARACTERISTICS
The input structure of the FCT16xxxT and FCT162xxxT
Double-Density families is shown in Figure 1. The equivalent
circuit for the input stage includes the ESD protection circuit,
input clamp diode, TTL-CMOS translator and the hysteresis
circuit.
IIN(mA)
CLAMP ....
DIODE
-40
-60
3020 drw 03
Figure 3. Double-Density Input Characteristics
Figure 1. Input Circuit for Double-Density FCT16xxxT and
FCT162xxxT
Although breakdown occurs at approximately 14V, the
absolute maximum steady state input voltage rating for reliable device operation is limited to a lower level. FCT16xxxT
can tolerate a steady state voltage of 7V at inputs and I/O pins
while FCT162xxxT can tolerate 7V at inputs and Vee + 0.5V
at I/O pins. Beyond this, long term reliability of the device may
be affected.
The absolute maximum voltage specification of GND -Q.5V
for all pins on both the FCT16xxxT and FCT162xxxT, and Vee
+0.5V for I/O and output pins on the Balanced-Drive part
refers to a steady-state condition. The specification does not
imply that the device cannot withstand transient overshoots!
undershoots greater than the rated values. Under transient
conditions, the device is expected to withstand an overshoot
of 7V or an undershoot of -3V for 20ns regardless of clamp
diodes. While the part will not sustain damage from these
overshoots/undershoots, it is possible that false switching
may occur if there are device inputs sitting at a marginal
voltage level or if other marginal conditions exist.
In addition to the above, Double-Density devices have the
advantage of extremely-low input capacitance where typical
values range from 3 to 5pF. This makes it possible for a highimpedance source elsewhere on the board to drive many
Double-Density inputs.
All of the inputs for the Double-Density family are designed
with 1OOmVof hysteresis in the input stage as shown in Figure
2. Due to the hysteresis, the effective LOW-to-H IGH and
HIGH-to-LOW switching thresholds are separated. This feature improves both static and dynamic noise margins. It is also
useful in providing immunity against overriding noise associated with slowly ramping inputs.
High
Low _ _
...,~_
1.45V
1.55V
VIN (Volts)
3020drw02
Figure 2. Double-Density Transfer Characteristic
showing hysteresis
The typical input V-I characteristics for the High-Drive and
Balanced-Drive Double-Density devices are shown in Figure
3. In the normal input operating voltage range of 0 to 5V,
practically zero current is drawn by the input stage. The input
stage offers very high-impedance and; therefore, low leakage
currents «+/-51JA). When the input voltage is one diode turn-
8
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
VOH (V)
OUTPUT CHARACTERISTICS
The output stage of FCT16xxxT and FCT162xxxT devices
has a "totem pole" configuration with N-channel pulldown and
N-channel pullup transistors. The N-channel pull-up in the
output stage reduces the output swing to TTL levels by limiting
the output voltage in a logic HIGH state to around 3.5V (TTL
logic high level). A simplified output circuit for the High-Drive
family is shown in Figure 4a and a circuit for the BalancedDrive family is shown in Figure 4b.
o
2
4
3
5
VOH SPEC·
-25
-50
-75 ~
3'
Vcc
-100~
FROM
PREVIOUS
STAGE
LOGIC HIGH STATE
-125
...........-0 OUTPUT
-150
Ta = 25°C
Vee = 5V
OESIGNAL ~=::jt==~
3020 drw 05
3020 drw04
Figure 5. Logic High Output Characteristics
Figure 4a. Output Circuit for FCT16xxxT
350
Vee
300
FROM
PREVIOUS
STAGE
250
;;(
.s
OUTPUT
OE SIGNAL
200
.J
LOGIC LOW STATE
.Q
~=:::t=~
150
100
3020 drw 4b
Ta = 25°C
50
Vee = 5V
Figure4b. Output Circuit Schematic for FCT162xxxT
2
3
VOL (V)
The FCT16xxxT and FCT162xxxTfamilies both have resistors in the drain of the device pull up structure giving the two
families similar pull-up capabilities. The clamp diode to Vee
in the pull up of the FCT162xxxT does not affect the output
characteristics of the device if the output voltage remains
between Vcc and ground. The typical logic high output impedance characteristics are shown in Figure 5 for both FCT16xxxT
and FCT162xxxT devices. In the logic HIGH state, the output
impedance, as obtained from the linear portion of the V-I
characteristic, is 28!l.
4
5
3020 drw 06
Figure 6. FCT16xxxT Logic LOW Output Characteristics
The typical output characteristics are different for the two
families for the logic LOW state. This is because of a different
pull down structure for the Balanced-Drive (FCT162xxxT)
family which includes a resistor in the source of the pull down
transistor. Because of this, the Balanced-Drive part has a
higher output impedance when pulling down than the HighDrive part.
The typical V-I curve for the High-Drive logic low state is
shown in Figure 6. From the chart it can be seen that the
output impedance for the logic LOW state is about 6!l which
is sufficiently LOW to allow the part to drive low-impedance
loads such as backplanes operating at high speeds.
9
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
FCT16xxxT
output
breakdown
LOGIC LOW STATE
200
150
loul(mA)
;;(
.s
100
Ta = 25°C
Vcc= 5V
-'
.Q
FCT16xxxT,
FCT162xxxT
parasitic
clamp diode
50
234
VOL (VOLTS)
5
3020 drw 07
-..
-40
-60
Vcc
YOUl(Y)
3020 drw 08
Figure 8. Output High-Z Characteristics for FCT16xxxT and
FCT162xxxT
Figure 7. FCT162xxxT Logic LOW Output Characteristics
The Power-Off Disable feature is useful in interface applications where one side of the interface may intentionally or
inadvertently become unpowered. Some of the applications
where this is possible include Hot Insertion where a board is
installed into an active, powered system or where a cable may
accidently become disconnected or attached to a live system.
The power off disable feature of the FCT16xxxT family ensures that the device outputs will remain in the high-impedance state when Vee=OV and that there is no path through
which voltage applied to an output can raise the supply rail of
the powered down device.
Applications which may require the Power-Off Disable
feature include power conserving systems, fault tolerant systems, telecommunications, networking systems and
backplanes. These applications may use Power-Off Disable
to power off unused portions of the system to conserve power,
allow the replacement of faulty boards in an active system, or
switch portions of a network in and out without disrupting
network communications. Refer to AN-1 02 [6] for a detailed
discussion on the Power-Off Disable feature.
Any signal pin of an FCT16xxxT device may be at any
voltage within the ABSOLUTE MAXIMUM VOLTAGE rating
forthe input while the device is powered off. During the poweroff state, the device supply voltage is at OV and the device
outputs remain in high-impedance, hence there is no contention when plugging such a device into an active bus. Devices
having this feature specify an "IOFF" current in the datasheet.
This is a measure of the leakage current at the outputs when
Vee=OV.
During power ramping, control (OE) signals must be suitably conditioned to ensure that the outputs remain in the highZ state. For negative assertion output enable pins, the output
enable should be tied to a logic HIGH (>Vee/2). When the
outputs of these devices are so conditioned, all 3-state outputs will offer high-impedance independent of the power
supply (within ABSOLUTE MAXIMUM Vee limits). At Vee
levels of less than 1.5V, the device outputs will not turn on,
regardless of the state of the output enable.
The FCT162xxxT family does not have the Power-Off
Disable feature. The presence of a diode to Vee at the outputs
of these devices creates a DC path to the supply pin during
power-off conditions precluding use of these devices in poweroff situations.
The V-I curve forthe Balanced-Drive part isshown in Figure
7 and shows an output impedance of about 12.50. This gives
the Balanced-Drive family enhanced output edge rate control
which improves the signal characteristics during transitions
and improves the overshoot and undershoot characteristics of
the device. Due to differences in the output structure of the
Balanced-Drive from that of the High-Drive part, the Balanced-Drive will exhibiit about 0.5ns less propagation delay
for the HIGH-to-LOW transition than the High-Drive part for
loads of less than 200pf. A discussion of this can be seen in
Appendix A.
As the graphs show, the actual device static drive current
under typical conditions is larger than that indicated by the
datasheet specifications. The typical dynamic drive current
during switching will be much larger than the data sheet static
specification and can also be seen from the charts. For
example, a device driving a capacitive load, upon switching,
will easily drive over 100mA dynamic current until the load
acquires the new state. The dynamic switching current for the
FCT162xxxT family is specified in the data book at 115mA
(typical for both directions), but the FCT16xxxT switching
current will be much higher for the transition to a logic LOW.
The output V-I characteristics (pure outputs and 1/0) for
FCT16xxxT and FCT162xxxT in the high-impedance state
are shown in Figure 8. Undernormal operating voltages, in the
high-Z state, the pull-up and pull-down transistors are off and
the output current is small (50~), as revealed by an almost
flat line, close to zero on the current axis of the V-I graph. For
output voltages one diode voltage drop below ground, the
parasitic diode olthe N-channel pull-down transistor turns on,
clamping the voltage at around 0.6V. For output voltages
above Vce, since the FCT16xxxT devices have no parasitic
diode to Vec, breakdown occurs at approximately 14V which
gives the Power-Off Disable feature. FCT162xxxT devices
have a parasitic diode to Vee at their outputs and hence voltages above Vce+0.5V are clamped. The user must maintain
static output voltages within the maximum ratings stated in the
datasheets in order to maintain reliable operation.
10
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
POWER DISSIPATION
. Power calculations are done to determine power supply
sizing, cooling/heat sink requirements and criteria for device
selection. Power calculations can also determine maximum
reliable operating frequency.
Power dissipation calculations for High-Drive and Balanced-Drive parts are discussed below.
5
<'
4
§.
'S
3
..
2
c.5
CD
Q.
g
Power dissipation in an unloaded device is
PD(unloaded} = Vcc x Ic
where Ic= Total power supply current
Vcc - VTP, only one of the transistors
of the input translator is on and the other is off. Hence, the
current drawn from the supply is very small. For VTN < VIN <
Vcc - VTP, both the pull-up and pull-down transistors are
partially on and current is drawn from the supply. The ~Icc is
maximum at the switching threshold (nominally 1.SV for FCT/
FCT-T at Vcc=SV) and progressively tapers off for input voltages greater or less than this.
Icco (loaded) = Icco (unloaded) + fCLVOH
where CL = Load Capacitance
11
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
10
ACT
8
/
/
J
o
~
~
o
--
/
ABT
...............
~
./'"
~
..--- --
L~
2
/
I
/
,-~ FCT-T
40
20
APPLICATION NOTE AN-117
a very low-static power, at higher frequencies they consume
more total power than corresponding Bipolar/BiCMOS parts,
due to a larger dynamic power supply component. This may
have been true for older technologies. The Double-Density
family, however, has dynamiC power dissipation characteristics that are much superior to older CMOS technologies and
existing advanced BiCMOS logic families.
As an example of a power comparison between ABT and
FCT-Twith no load (Figure 10), an FCT-T part will consume
the same current level at 34MHz as ABT at BMHz. It should
also be noted that when the devices are not switching, ABT
consumes a significant static current level while FCT will
approach zero in current consumption.
STATIC AND DYNAMIC DRIVE
Drive is one of the key features that differentiates the
FCT16xxxT and FCT162xxxT Double-Density families. HighDrive devices are specified at 64/-32mA static drive while the
Balanced-Drive devices are specified at 24/-24mA static.
The static drive is the current that the device is continuously
capable of sourcing or sinking in a stable logic state. It is
typically specified at the minimum VOH or the maximum VOL.
Dynamic drive is the transient output current that the device
can sink or source during a H IGH-to-LOW or a LOW-to-H IGH
transition. Dynamic drive is not always specified in datasheets,
but it can be determined from the device V-I graphs. Static
drive indicates the ability of the device to maintain static noise
margins in the presence of a DC load. It is the current at which
VOH and VOL are specified. Dynamic drive, on the other hand,
indicates the ability of the device to charge and discharge
capacitive loads while meeting the AC performance limits and
incident wave switching requirements.
Unless there is a DC load on the line or a low-impedance
line (e.g. a loaded backplane) is being driven, a large static
drive is typically not required to drive CMOS devices to valid
logic levels. Due to their large input impedance and low-input
current requirements, CMOS devices do not require a driver
with a large static drive capability except in the case of lowresistive termination. Dynamic drive, however, plays a more
important role since it determines the speed derating with
capacitive loading.
FCT162xxxT devices have a modest static drive compared
to FCT16xxxT devices; but, as indicated by datasheet specifications, they have ample dynamiC drive (typically> 100 mA
at 1.5V). Due to the particular implementation of the source
termination, unlike some other series terminated parts, the
FCT162xxxT devices do not sufferfrom lackof drive duetothe
additional impedance.
60
Frequency, MHz
3020 drw 10
Figure 10. IcC vs Frequency (no output loading)
30
'~r-~-~-
./
-~
ACY
24
:g
Ci:
18 -1-----
./
-~~-
E
/
o
.!:! 12
V
/'
/"
...... V
./
V
/ V',/ " . /
6 -fo-----
~
o ~
o
~
20
V./"
A~
FCT-T
".,
40
Frequency, MHz
60
3020drw11
Figure 11. Icc vs Frequency (with 50pF output load ing)
Figure 10 shows the total power supply as a function of
frequency for various 16-bit logic families. Figure 11 shows a
similar graph for the loaded case. The total supply current in
these graphs includes the static and dynamic power supply
components but not dice as the inputs are at CMOS levels.
inputs. Because of their internal structure, bipolar technologies have a larger static or quiescent power component than
CMOS. CMOS has almost zero power dissipation under static
conditions due to the fact that one transistor of the CMOS pair
is off in a valid logic state leading to a high-impedance path
between Vec and ground.
It is seen that power dissipation characteristics of both
FCT16xxxTand FCT162xxxTfamiliesaresimilar. Total power
dissipation, under typical operating conditions, however, is an
important Figure of merit. A common argument against
CMOS families in the past has been that although they have
12
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
0.40
APPLICATION NOTE AN-l17
_. . ."..- _. "., .,- '-r- _. . -,- .VCC, = f?V
,~
3'8t~Ta~.~.;5~'bd~·I+~·I"~~"I'·III~
3.6
«
E
1
>
-£
o
>
0.20
-60
-20
20
60
Temperature, °C
100
3.4
«
2.8.!OO
4.4
4.6
3020 drw 12a
""
N
. .
0.30
>
.,;
0
>
,
0.25
.-
-~
.
,
..
~
.... f,·
,
,...1-
"'F
+"1'.
4.6
4.8
:~.
•
..
-
,,
,
j
':.t ft:-
~
."
...
4.8
5.4
5.6
3020 drw 13b
AC PERFORMANCE
AC TEST CONDITIONS
Double-Density is offered in the same speed grades as the
octal FCT and FCT-T devices. With different speed grades
available, the designer can choose cost/performance tradeoffs for the overall system implementation. The following
chart shows the commercial speed grades for four of the most
popular Double-Density functions.
.
,
""t'
..J....
. .
~.........
5.0
5.2
Vce, V
Figure 13b. VOH vs VCC at 25°C
·1'a _25'oC
!
0.35
E
@J
1
'''~-
:.:=~-;t'''';FI·al":
Figure 12a. VOL vs Temperature at VCC = 5V
0.40
.
..
0.20
4.4
5.0
Vee, V
5.2
5.4
5.6
3020 drw 12b
Function
244
245
373
374
NOTE:
Figure 12b. VOL vs VCC at 25°C
Because of the excellent noise characteristics of BalancedDrive devices, it is in the best interest of the designer, to use
Balanced-Drive parts unless high static drive is essential.
Figures 12a and 12b show the variation of VOL with temperature and Vee at a drive current of 24mA static drive.
Figures 13a and 13b show similiar characteristics for VOH at
-24mAstatic drive. Referto appendix B forstandard datasheet
specifications.
3.8
.~
,....
3.6
«
E
3.4
@J
3.2
""
"t
>-£
-'.- ,-
-1-'·-
"·"-H-
,+, .. Vcc
... .... ... .
..
.-t.
~
~
~
m
II-
_.... .+
.............................
,- ."
,
,
~
.........
.-
.~
,..... ,-
Aspeed(l)
C Speed(l)
6.5
7.0
8.0
10.0
4.8
4.6
5.2
6.5
4.1
4.1
4.2
5.2
3020 1b1 01
1. All speeds in ns.
AC limits of the Double-Density family are specified over
extended commercial, industrial and military temperature
ranges. Vee tolerance is ±10 % for both commercial and
military devices. The limits are based on the worst case
operating conditions with Vee = 4.5V and TA = 85°C for
commercial grade limits and TA = 125°C for military grade
limits. All AC parameters are measured using the industry
standard load shown in Figure 14. AC tests are done with a
single bit switching and timings may need to be derated for the
worst case of 16/18/20-bits switching simultaneously.
-J..-
._,.....' ,- ..,
-+- ,...-
,
"
5V
Standard
Speed(l)
- 1"-
,......, ." _. I-
~ 7.0V
Vcc
0
> 3.0
2.8
-60
500n
-20
20
Temperature,oC
60
VIN
100
VOUT
I-f<+-......-I D.u.T. I-f<+-......-
3020 drw 13a
Figure 13a. VOH vs Temperature at VCC = 5V
...
RT
500n
3020 drw 14
Figure 14. Standard Logic Test Load
13
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
1.2
The 50pF capacitance in the standard load allows for stray
and parasitic capacitances due to the ATE test fixture. In most
measurements the switch is in the open position. The 500n
resistors offer a nominal DC load and help establish "artificial"
logic levels for testing enable and disable time parameters.
In many cases, the test load may not be a true representation of a customer's load. When the loading is lighter, the limits
may be used as a worst case, but when the loading is heavier
they may need to be derated. Also the system under consideration may normally operate in a narrower temperature and/
or Vee range. In such circumstances, it is useful to have the
option to derate for the different variables that affect the AC
characteristics. In order to serve this purpose a variety of
derating graphs are provided in the following sections.
1.1
1;c
Cii
1.0
"tI
Gl
.!:!
i6
Derating factor
E
0
:
-H#+ = .0125 x tpo 110°C :
N
0.9
z
0.8
-100
o
100
200
Temperature,OC
3020 drw 16
Figure 16. FCT162xxxT Delay vs Temperature
PROPAGATION DELAY
DELAY AS A FUNTION OF TEMPERATURE
Figures 15 and 16 show the normalized graphs of propagation delay as a function of temperature for FCT16xxxT and
FCT162xxxT. The FCT16244T and FCT162244T are used as
a basis for these graphs.
1.2
tPLH i
tPHL i
---GI-
-+--
>-
.!!!
1.1
l
fit
:
f-Vcc = 5V
Note: Due to the similarity in output structure, the graphs
are representative of the characteristics of all devices belonging to the same family.
Derating factors are useful in accounting for the effect of a
variable on a specific parameter. For example given a temperature derating factor of 0.0157tPD/1 O°C for FCT16xxxT,
the FCT16245CT (delay spec = 4.1 ns) when operating at
25°C can be assumed to have a delay of:
Gl
C
"tI
Gl
tPD = [4.1 - 0.015 x 4.1 (85-25)/10] = 3.73ns max
Delay as a Function of Supply Voltage
Figures 17 and 18 show the normalized graphs of propagation delay as a function of supply voltage. Again the data is
based on the FCT16244T and FCT162244T, but is representative of all devices within each of these families. With an
increase in Vee the current available for charging and discharging goes up and hence the propagation delays go down.
For reduced Vee, the current goes down and there is an
increase in the propagation delay.
.!:!
iii
E
0
1.0
z
0.9
-55
~
Derating factor =
N.015? x tpo/l O°C
!
-5
45
Temperature,OC
95
145
3020 drw 15
1.1
Figure 15. FCT16xxxT Delay vs Temperature
'l,
1;-
Propagation delay is related to the current available for
charging and discharging the internal and external capacitances. The current itself depends on a number of process
parameters, which vary with temperature. As a result,
propagation delay has a temperature gradient as shown.
;!l
l5
'iii
J
i
i
1.0
.- ~-t~!
~-
tpLH
tpHL
----G~~-.
" ,
I
._- ~ ~
D..
f..-..-
~~
~
-t~
'i
Z~
0.9
4.4
4.6
4.8
5.0
5.2
Vee
Figure 17. FCT16xxxT Delay vs VCC
14
5.4
5.6
3020 drw 17
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
1.2
ie'
~
'~."'.""''''~
iii
...............
Q
c
0
~
1.1
-- ,......_- ------ ............. --- .................
~
.,D..
Cl
~
D..
tPHL
tPLH
.........
6
--
!
.-
E
............
1.0
--- --=t-~~t=~- ,.......-- _._i---
-
c
~
5
4
-
!',C,
...........
..,- ":...-
~
......
....
3
l
-
~
~
I
........... ...
--- ....................
-- --+-' / ~ f----- --I
I
~
0.9
4.5
4.75
5
50
5.5
5.25
Vee, V
150
CL,pF
3020 drw 18
Delay as a Function of Number of Outputs Switching
8
The AC characteristics are tested and specified for single
bit switching. In reality, multiple bits can switch simultaneously generating internal noise which causes the observed
propagation delays to change. Figure 19 shows the change
in propagation delay as a function of number of outputs
switching. The data forthis graph is based on the FCT16245T
and FCT162245T.
._- -- --- --
1---6
~
!
tPHL
!
5
& 4
.---
3
.....-
..,.r-
tPLH
2
2
~
-- -- ._- ,- -
50
c
16xxx
.- ,....~
o
150
CL,pF
-
10
# of outputs switching
~>-
-
!
-- --
"- -- ,......-
-
--
--I
250
3020 drw 21
Figure 21. FCT162xxxT Delay vs Load
-
162xxx
I/)
3020 drw 20
!
7
3
._f--.
250
Figure 20. FCT16xxxT Delay vs Load
Figure 18. FCT162xxxT Delay vs VCC
o
--
---=r-":-P"
.--
2
z
E
-+--+--i
o
0.4
l
4.4
~r
1.0
iii
E
~l
0.8
50
100
150
Load,pF
200
250
5.2
5.4
3020 drw 26
Figure 26. Enable Time vs VCC for FCT16xxxT
300
3020drw23
Figure 23. FCT162xxxT Trlse and Tfall vs Load
ENABLE AND DISABLE TIMES
Like propagation delay and rise and fall times, enable and
disable times also vary with temperature and Vee. Figures 24,
25, 26 and 27 show the variation of enable time with temperature and Vee and are based on data taken on the FCT16245T
and FCT162245T. Variation of disable time is more a function
of the load than the device itself. Therefore derating of disable
time is independent of the device but depends on the temperature and Vee coefficients of the load.
16
5.6
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
2.0
-----I!I-
CD
E
i=
CD
jj
1.6
1.2
~iU
1
0.8
0.4
z
1
,
,
E
Is
tPZL
tPZH
j
as
I:
W
APPLICATION NOTE AN-117
~t-
, !
0.0
4.4
!
+i .
~
...
- ..
-
4.6
+
j
!
4.8
5.0
Vee, V
5.2
5.4
up. Due to this correlation between speed and ground
bounce, high-speed logic families arouse increased concern
over noise due to the simultaneous switching of outputs.
The standard method of measuring ground bounce involves keeping one output in a logic LOW state and switching
all other outputs at a given frequency (1 MHz typical). The quiet
output will reflect the bounce on the internal device ground.
Similarly Vee bounce can be observed by keeping one output
in the logic HIGH state. The naming convention for ground
bounce characterization is as follows:
VOLP = Peak positive ground bounce on a LOW output
VOLV = Peak negative ground bounce on a LOW output
VOHP = Peak positive Vee bounce on a HIGH output
VOHV = Peak negative Vee bounce on a HIGH output
5.6
3020 drw 27
Figure 27. Enable Time vs VCC for FCT162xxxT
SKEW
Skew reflects the worst case propagation delay difference
between the different outputs. Skew results from design
(routing/placement), process and packaging specific to the
device. For the user, as the clock frequency goes up, timing
margins become tighter. Signal skew makes the timing margin
even tighter. Reduction in the spread of the output propagation delays results in reduced skew and improved timing
margins.
There is a tendency among designers to compute the
difference between the maximum and minimum specifications and use this Figure as the worst case skew; however,
this is not a realistic measure of skew because the maximum
(worst case) and minimum (best case) delays occur under
mutually exclusive conditions of temperature, power supply
voltage and process. In order to provide the user with the
required information, Double-Density devices have an output
skew specification of O.Sns maximum between outputs on the
same device. For further discussion on types of skew, the
reader is referred to Application Note AN-82[8].
V
"5
c..
"5
0
~
Cl
0 -1----!--:C....~-~~-.......,_======I
-....;;:::......- VOLV
o
Time
3020 drw 28
Figure 28. Ground Bounce for HIGH-to-LOW Transitions
V
SIMULTANEOUS SWITCHING NOISE
In a digital circuit when multiple outputs switch, the current
through the ground or Vee lead changes rapidly. As this current flows through the ground (or Vee) return path, it develops
a voltage across the parasitic inductance of the bond wire and
package pin. This phenomenon is called simultaneous
switching noise. The noise is seen as ground bounce or Vee
bounce and can cause problems such as data loss and false
triggering in a system. For a detailed discussion of ground
bounce the reader is directed to Application Note AN-47 [4].
Ground and Vee bounce cannot be entirely eliminated, but
they can be minimized by controlling edge rates, reducing
output swing and providing multiple power, ground and Vee
pins. Double-Density has 8 ground pins and 4 Vee pins. This
is a marked improvement over the ground distribution in the
octal devices and manifests itself in the noise characteristics
of the device. Ground bounce depends on many factors with
device speed being one of the important influences. As device
speed goes up, the rate of change of current in the parasitic
inductances increases and the related switching noise goes
0
-1-_ _ _1-_.::..._ _ _ _ _ _ _ _ _ _ _ _-1
"[
"S
0
o
Time
3020 drw 29
Figure 29. Vee Bounce for LOW-to-HIGH Transitions
The "ground bounce" phenomenon is primarily dependent
on the output edge rate, number of outputs switching and
package lead inductance. Other factors that can affect ground
bounce are the output swing and drive. Most current technology consists of TTL -compatible logic where the output drivers
can be made to pull the outputs from rail-to-rail with a p..
channel pullup transistor ("CMOS level outputs") or they may
17
DOUBLE-DENSITY lOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
Ground Bounce vs Load
drive the output to approximately 3V with an n-channel pullup
(''TTL-level outputs"). The equations below illustrate why the
ground bounce is higher with CMOS level output swings.
i
= CldVo
Simultaneous switching noise is affected by the output
loading. As the value of the load capacitance increases, the
charge stored in the capacitance is increased. The larger
charge implies a slower rate of discharge through the package parasitics and hence lower ground bounce as shown in
Figures 31 and 32. Another way to look at it is, the load slows
down the signal transition increasing the transition time and
reducing ground bounce.
... (i)
ill
where,
Vo = Output voltage
CL = load capacitance
Vg = voltage induced on ground pin
Lg = inductance at the ground pin
Vg
=
dt
using (i) in (iia), we get Vg = LgCL d2 Vo
>
a:
... (iib)
;g
dt2
~
0.8
-g
..5Cl
_
111
"0.
iii
E
o
z
VOLV
//
0.6
//
I?
--
300
400
3020 drw31
FCT16xxxT
FCT162xxxT
1.2
>
;!
~
0.8
0.4
0.0
0
100
200
CL,pF
Figure 32. VOlV vs load
VOLP
10
# of outputs switching
200
1.6
'l
o
100
2.0
.--
!:::="'"
r- i-o
-~
.~
Figure 31. VOlP vs Load
ij
0.4
0.2
./
"/
t--
:
-..- _.
--
.~
CL,pF
1.2
--r-~
0.8
0.0
Every logic family has a characteristic edge rate (for a given
load condition) and every package has a fixed lead inductance. Hence given a specific family, package, and loading, a
distinct correlation can be observed between the number of
outputs switching and the amount of undershoot/overshoot
due to ground bounce. Figure 30 illustrates this relationship
for the Double-Density devices in an SSOP package.
1.0
TA= 25°C
.Yr:.9. ..?y. .... ...:
0.4
Ground Bounce vs Number of Outputs Switching
2l
1.2
FCT16xxxT
FCT162xxxT
-~
Because of the lower voltage swing, TTL level outputs give
better noise immunity than CMOS, rail swing, output levels.
The other factor affecting ground bounce is output drive.
The higher the output current, the greater the switching noise.
This is evident from the equation (iia) above.
FCT16xxxT/162xxxT devices are available in SSOP and
Cerpack packages. These packages have multiple ground
and Vee pins, giving multiple parallel paths and low inductance to the high-speed switching currents. The surface
mount package avoids the inductance of through hole mounting and is the package configuration for high-speed logic. The
combination of these package characteristics results in a
significant reduction in the magnitude of simultaneous switching noise. Package dimensions and pin inductance values are
shown in Appendix C.
c
~
1.6
... (iia)
Lg di
-
2.0
20
3020 drw 30
Figure 30. Double-Density ground bounce
vs number of outputs switching
(16-bit function)
18
300
400
3020 drw32
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
MISCELLANEOUS ISSUES
MAXIMUM INPUT RISE AND FALL TIMES
When an input rises or falls slowly, the noise overriding the
input can cause the device to oscillate for some time before
the output becomes steady. Such oscillations are not desirable because they cause the effective propagation delay to go
up by a large amount, and affect system reliability. There is a
restriction on the maximum input rise and fall time for reliable
circuit operation. For FCT16xxxT, the slowest recommended
rise and fall times on the device inputs are SOns. The hysteresis circuit in the input stage (see Figure 2) helps in reducing
the effect of noise on slowly changing inputs.
ESD
There are two standard methods to characterize ESD, the
machine model and the human body model. Double-Density
devices meet MIL-STD-883 (Method 3015) Class 2 ESD level
requirements. This means that they can withstand voltage
levels greater than 2KV (4KV typical) under the human body
model test methodology. With the machine model test methodology, Double-Density ESD tolerance is greater than 200V.
Storage of devices in protective foam and the use of a ground
strap during handling are standard precautions.
UNUSED INPUTS
DECOUPLING
Good decoupling techniques are required to achieve optimum noise and performance levels from Double-Density
components. The multiple ground and Vee pins on the SSOP
and Cerpack packages reduce the effect of the lead inductance of the devices, but do not provide a single point for the
capacitor. The best style and location of the decoupling
capacitor is the use of a surface mount chip capacitor placed
directly over the component, on the reverse side of the board.
An alternative location for boards with components on one
side only is to place the capacitor at either end of the component. The capacitor should have a LOW series inductance
and resistance in order to maximize the effect of the capacitance. The function of the capacitor is to provide a lowimpedance path to high-frequency components, while also
satisfying the load's initial high-current requirements.
O.3
J
The unused inputs of logic devices should not be left
floating because these high-impedance inputs act like antennae and pick up noise. To prevent the noise on such inputs
from switching the device and consuming extra power, all
unused inputs must be connected to Vee or ground, preferably via a current limiting series resistor to limit unwanted
current surges.
SUMMARY
lOT has introduced the Double-Density logic family to meet
the demands of high-performance systems. These highintegration components save board space while maintaining
the compatibility with the older octal devices in terms of speed
and functionality. Three different varieties are offered to meet
to the users' diverse application needs. The standard HighDrive family is ideal for bus/backplane applications. The
Balanced-Drive family has user friendly outputs for low noise,
reliable systems. The 3.3V family is ideal for power-sensitive
~pPlications such as laptops and notebooks. The various
characteristics, graphs, and information provided herein are
intended to aid the designer in achieving desired cost/performance goals.
3.3
~
---.
)
._
Z = 30n
)
~------------3020 drw 33
Figure 33. Buffer Driving a Loaded Trace
REFERENCES
[1] "Series Termination"(AN-SO), High-Speed CMOS Logic
Design Guide, lOT, Inc., November 1991.
[2] "Power Dissipation in Clock Drivers"(AN-S1), HighSpeed CMOS Logic Design Guide, IDT, Inc., November 1991.
[3] "Characteristics of PCB Traces"(AN-49), High-Speed
CMOS Logic Design Guide, IDT, Inc., November 1991.
[4] "Simultaneous Switching Noise"(AN-47), High-Speed
CMOS Logic Design Guide, IDT, Inc., November 1991.
[5] "3.3V Logic"(AN-1 03), IDT 3.3V Logic Product Information, IDT, Inc., February 1992.
[6] "Power off Disable in lOT Double-Density Devices"(AN102), lOT, Inc., 1992-93.
[7] "Decou piing Double-Density Components"(AN-116),
IDT, Inc.,1992.
[8] "Clock Distribution Simplified With lOT Guaranteed
Skew Clock Drivers"(AN-82), Logic Databook, lOT, Inc., 199091.
As an example of a decoupling situation, Figure 33 shows
a driver driving a 30n transmission line as could be encountered when driving a heavily loaded backplane. When the
output of the buffer switches LOW-to-HIGH, about 100mA
(dynamic) drive is required [(3.3 - 0.3)/30 = 100]. For 16 bits
switching simultaneously 1.6A dynamic drive is required. For
a Vcc drop of 0.1 V and a 3ns rise time on the signal, the value
of the decoupling capacitor can be decided as shown below.
i = C(dV/dt) approximating this with deltas
1.6 = C(0.1/3x10**-9)
Hence, C = 0.0481lF
With this calculation, the value of the capacitor can then be
selected from the standard capacitor values. A capacitor
equal to the value in the equation or larger should be selected
to achieve the noise value decided upon. The value of 0.11lF
is a good choice. The application note AN-116, Decoupling
Double-Density Components, contains a complete discussion on capacitor selection and placement.
19
DOUBLE·DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN·117
APPENDIX A
BALANCED-DRIVE CAPABILITY
The output structure of the Balanced·Drive part (Figure 6)
has been specifically designed to give similar transition times
with matching absolute edge rates in both the high going and
low going directions. This means the lOT Balanced·Drive
Family has a matched dynamic drive capability for driving
transmission lines, but still has sufficiently low static output
impedance to maintain state during steady state conditions.
As shown in Figure A 1, during transitions the Balanced-Drive
output structure will current limit at about 115mA typical
forboth low-to-high and high-to-Iow transitions, limiting surge
current into the transmission line, but still providing sufficient
drive current to drive all except the most demanding loads.
Limiting the pull down drive capability of the device during
transitions also reduces problems with undershoot, ground
bounce and general noise generation. In almost all applications, the Balanced-Drive part will generate less noise than
BiGMOS components and the associated ringing that BiGMOS
generates.
3020 drw35
Figure A2, Static Balanced·Drive Output
Adding External Resistors to Balanced-Drive
With the Balanced-Drive components, the effective series
termination impedance of 2sn is slightly lower than the
characteristic impedance of most transmission lines.
Backplanes may sometimes approach levels as low as 30n,
but most lines will have a higher impedance. Despite this
difference, the current surge driven into the transmission line
will be limited by the output impedance and controlled edge
rate.
If it is desirable to further enhance the quiet operation and
to achieve a close match between the source impedance and
the line impedance, the user may add external resistors to the
output of his Balanced-Drive parts. Because of the integrated
resistor in the drain olthe pull up FET, and the output structure
of the Balanced-Drive part, the addition of an external series
resistor will not cause significant attenuation of the output
signal in the pull-up structure of the device as happens with
standard TTL output components. This means that when
series resistors are added to a Balanced-Drive part, the LOWto-HIGH edge rate will retain similar .characteristics to the
HIGH-to-LOW edge rate. With similar edge rates, the performance and noise levels will be superior to situations where
an external resistor has been added to a standard TIL output
part.
3020 drw 34
Figure A1, Dynam ic Balanced·Drive Output
During steady state DG conditions, lOT specifies the static
drive capability of the devices at 24mA worst case in both
directions as shown in Figure A2. Balanced-Drive components will give better line matching than equivalent drivers with
lower output impedance eliminating the need for external
resistors in most cases.
Driving Capacitive Loads
Standard parts which have a low pull-down impedance and
a high pull-up impedance have problems with RG time delays
when driving capacitive loads. This is due to the inability to
match the line impedance for both directions. Usually the
addition of a large enough resistor to perform line matching in
the pull down direction will cause significant degradation of the
pull up capability of the part. IDT's Balanced-Drive parts have
overcome this problem by providing equal line driving capability in both directions and will drive capacitive loads equallywell
in both directions with or without external resistors. This
means that adding a series resistor will not degrade the speed
of the part significantly because the effective line matching
resistor will have a lower resistance value than one that would
be used with a standard part.
20
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
IDT's Balanced-Drive and High-Drive components have
very similar response times for capacitive loads of less than
300pf. Because of its quicker response, the Balanced-Drive
part will switch faster than a High-Drive part for loads of less
than 200pf. As the load increases above 200pf the High-Drive
part will respond more quickly for a high-to-Iow because of its
lower output impedance. Despite these minor differences the
differences in the effects of capacitance on propagation delay
between the High-Drive and Balanced-Drive parts should be
less than 0.5ns for any load of less than 300pf. The capacitive
derating curves are shown in Figure A3.
When the capacitive load is larger than 400pf at high
switching speeds, the load will begin looking like a direct short
upon switching and may begin to overdrive the output of both
the Balanced-Drive and High-Drive part. The power dissipation
equation is P = fCV 2 and should be used to calculate the power
consumption for each pin to assure that the total power
dissipation in the device does not exceed the maximum rated
limits. To avoid exceeding the limit for heavy capacitive loads,
a 100n series resistor can be used to limit the current to
acceptable levels.
APPENDIXB
STANDARD DEVICE SPECIFICATIONS
This section includes specifications and ratings for lOT's
High-Drive and Balanced-Drive families. The standard tables
for DC Electrical characteristics, output drive, capacitance
and absolute maximum ratings are common to all DoubleDensity device types and are the same as in any characteristics are similiar if not identical for all devices.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
CIN
Parameter(1) Conditions
Input
Capacitance
Typ.
Max.
Unit
VIN = OV
4.5
6.0
pF
pF
1/0
ClIO
Capacitance
VOUT= OV
5.5
8.0
COUT
Output
Capacitance
VOUT= OV
5.5
8.0
NOTE:
1. This parameter is measured at characterization but not tested.
pF
3020 tbJ 02
8~------------------------------~
ABSOLUTE MAXIMUM RATINGS
7
Symbol
Rating
VTERM(2)
Terminal Voltage
with Resect to
GND
-0.5 to +7.0 -0.5 to +7.0
V
VTERM(3)
Terminal Voltage
with Resect to
GND
-0.5 to VCC -0.5 to VCC
V
TA
Operating
Temperature
-40 to +85 -55 to +125
°c
TBIAS
Temperature
Under Bias
-55 to +125 -65 to +135
°C
TSTG
Storage
Temperature
-55 to +125 -65 to +150
6
5
~
4
:J'
e.3
2
o
50
100
150
200
250
300
Capacitive Load (pf)
Figure
350
PT
400
3020 drw 36
lOUT
A3, Capacitive Derating for Double Density
Power DiSSipation
DC Output
Current
Commercial
1.0
Military
1.0
-BOto +120 -60 to +120
Unit
°C
W
mA
NOTES:
3020 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other cond itions
above those indicated in the operational sections ofthis specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. All device terminals except FCT162XXXT Output and 1/0 terminals.
3. Output and 1/0 terminals for FCT162XXXT.
Balanced-Drive and High-Drive
SUMMARY
Utilizing the Balanced-Drive family in high speed bus
driving applications will solve most of the problems with noise
and line termination experienced with traditional high-speed,
low-output impedance line drivers. The Balanced-Drive logic
family provides the benefits of series termination on signal
lines while avoiding many of the drawbacks of adding external
series termination resistors. The Balanced-Drive family of
devices from lOT will generate lower levels of noise than other
components in the same speed grade, solve many of the
termination line problems encountered by the designer, reduce power consumption and give superior performance to
other high speed logic. Balanced-Drive is the logic family of
choice for most applications.
21
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Typ,C2)
Max.
Unit
-
0.5
1.5
mA
VIN=VCC
VIN=GND
-
60
100
Vcc = Max.
Outputs Open
1i = 10MHz
VIN= VCC
VIN= GND
-
0.7
2.5
50% Duty Cycle
xOE= xDIR = GND
One Bit Toggling
VIN = 3.4V
VIN= GND
-
0.9
3.3
Vcc = Max.
Outputs Open
1i = 2.5MHz
VIN= VCC
VIN = GND
-
2.5
5.5(5)
50% Duty Cycle
xOE = xDIR = GND
Sixteen Bit Toggling
VIN = 3.4V
VIN = GND
-
6.5
17.5(5)
Test Conditions(1)
.:llcC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC= Max.
VIN = 3.4V(3)
ICCD
Dynamic Power Supply Current(4)
Vcc = Max.
Outputs Open
xOE = xDIR = GND
One Input Toggling
50% Duty Cycle
Ic
Total Power Supply Current(S)
Min.
NOTES.
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vce = 5.0V, +25°C ambient.
3. Per TTL driven input (V IN = 3.4V); all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. Ie = IQUIESCENT + IINPUTS + IDYNAMIC
Ic = Icc + Alcc DHNT + ICCD (fCPNCPf2 + fiNi)
Icc = Quiescent Current (ICCL, ICCH and Iccz)
Alcc = Power Supply Current for a TTL High Input (VIN = 3AV)
DH = Duty Cycle for TTL Inputs HIGH
NT = Number of TTL Inputs at DH
Icco = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fcp
fi = Input Frequency
Ni = Number of Inputs at fi
22
flA/
MHz
mA
3020 tbl 04
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Test Condltions(1)
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2.0
VIL
Input LOW Level
Guaranteed Logic LOW Level
Input HIGH Current (Input Pins)
Vee= Max.
VI = vee
-
VI = GND
-
IIH
Input HIGH Current (I/O Pins)
Input LOW Current (Input Pins)
ilL
-
Vo= 0.5V
-
(3-State Output Pins)
VIK
Clamp Diode Voltage
Vee + Min., liN = -18mA
loS
Short Circuit Current
Vee = Max., va = GND 3)
-80
10
Output Drive Current
Vee = Max., Va = 2.5V(3}
-50
VH
Input Hysteresis
Quiescent Power Supply Current
Vee= Max.
Va = 2.7V
High-Impedance Output Current
10ZL
-
Vee = Max., VIN = GND or Vee
Max.
-
-
Input LOW Current (I/O Pins)
10ZH
leeL
Typ'!;':)
Min.
Unit
-V
0.8
V
±5
J.tA
±15
±5
±15
J.tA
±10
±10
--{).7
-1.2
V
-140
-200
mA
-180
mA
-
-
100
-
mV
0.05
1.5
mA
leeH
leez
3020 tbl 05
OUTPUT DRIVE CHARACTERISTICS FOR FCT16XXXT
Symbol
VOH
Parameter
Output HIGH Voltage
Min.
Typ.(2)
Max.
Vee = Min.
10H =-3mA
2.5
3.5
V
VIN = VIH or VIL
10H =-12mA MIL.
2.4
3.5
-
2.09
3.0
-
V
-
0.2
0.55
-
-
±100
Test Conditions(1)
Unit
V
10H = -15mA COM'L.
10H = -24mA MIL.
10H = -32mA COM'L(4)
VOL
10FF
Output LOW Voltage
InpuVOutput Power-Off Leakage
Vee= Min.
10L = 48mA MIL.
VIN = VIH or VIL
10L = 64mA COM'L.
Vee = OV, VIN or Va :'>4.5V
V
J.tA
3020 tbl 06
OUTPUT DRIVE CHARACERISTICS FOR FCT162XXXT
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
10DL
Output LOW Current
Vee = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
60
115
150
mA
10DH
Output HIGH Current
vce = 5V, VIN = VIH or VIL, VOUT = 1.5V(3)
-60
-115
-150
mA
VOH
Output HIGH Voltage
vce= Min.
10H = -16mA MIL.
2.4
3.3
-
V
VIN = VIH or VIL
IOH = -24mA COM'L
-
0.3
VOL
Output LOW Voltage
Vcc= Min.
IOL = 16mA MIL.
VIN = VIH or VIL
10L = 24mA COM'L
NOTES:
1.For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2.Typical values are at Vcc = 5.0V, +25'C ambient.
3.Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4.Duration of the condition can not exceed one second.
23
0.55
V
3020 tbl 07
DOUBLE-DENSITY LOGIC CHARACTERISTICS AND APPLICATIONS
APPLICATION NOTE AN-117
APPENDIXC
PACKAGE INFORMATION
AREA COMPARISON FOR CERPAK
PACKAGES
Double-Density devices are offered in the space saving
48- and 56-pin SSOP (shrink small outline package) for
commercial and the 48- and 56-pin CERPACK for military.
Figure C1 shows the dimension details for the two SSOP
packages, and figure C2 shows the dimensions of the two
CERPACK packages .
48 CERPAK
................r-----."..:;::;;;:::::;----.-
390 mil
390mil
Body Length
626 mil
727 mil
Body Height
86 mil
86 mil
Body Weight
.6g
.6g
8JC
8JA
Pin Inductance
25 mil
Pitch
56 CERPAK
Body Width
5
5
70
75
1.5nH (ground)
1.8nH (ground)
3.1nH (I/O)
3.1nH (I/O)
3020 drw 09
0.625/
0.725
-I
1 •
The thermal characteristics are used for estimating the
junction temperature for given loading and frequency conditions. The devices should be operated below the maximum
junction temperature for reliable operation over an extended
period of time. For the FCT16xxxT family the maximum
junction temperature allowed is about 150°C.
3020 drw37
0.406
Figure C1. The Physical Dimensions of SSOP
25mil
Pitch
Both SSOP packages have the same width and pin-to-pin
separation but different body lengths. Due to the fine pitch (25
mil), significant area savings are achieved over multiple octal
packages. Table C1 shows the key dimensions and characteristics of the SSOP packages.
48SS0P
56 SSOP
300 mil
300mil
Body Length
625 mil
725 mil
Body Height
2.74mm
2.74mm
Body Weight
0.6grams
-
8JC
8JA
Pin Inductance
17
17
70
70
1.5nH (ground)
1.8nH (ground)
2.9nH (VO)
3.1nH (1/0)
0.727
3020 drw 38
AREA COMPARISON FOR SSOP PACKAGES
Body Width
0.6261
Figure C2, The Physical Dimensions of CERPACK
3020 drw 08
24
~
~
POWER-OFF DISABLE
IN lOT'S FCT16xxxT
DOUBLE-DENSITYTM DEVICES
APPLICATION
NOTE
AN-102
Integrated Devlc:e Technology, Inc:.
By Stanley Hronik
INTRODUCTION
Power-off Disable is a feature of IDT's FCT16xxxT family
which allows a user to shut down portions of his system, or to
remove and install boards or peripherals during full power
conditions, in a properly designed system. In order to have the
ability to remove and install during live power conditions, the
devices must be able to withstand the maximum rated voltages on their inputs and outputs when Vcc is between 5 volts
and zero. The devices must not source or sink current that
would affect the remaining fully functional system, or drive an
active data bus in the power off state. The purpose of the
Power-off Disable feature is to maintain data integrity, to
eliminate bus contention, and to avoid component damage
during power off while tied to or while being inserted into or
removed from an active system.
This application note describes the Power-off Disable
feature built into IDT's FCT16xxxT High-drive Double-Density
family of products and portions of the eight bit FCT6xxTfamily,
both of which are designed for standard 5V supply operation.
Design techniques and applications for partially powered
systems are discussed and the circuit configurations used in
the FCT16xxxT Double-Density family of components to
achieve the Power-off Disable feature are described.
the computer without powering off the system. Also,
frequently a cable will become inadvertently disconnected during system installation, or if an activity adjacent to a system causes a disruption of the setup. Under
these conditions the components interfacing the disconnection point should sustain no damage from the powered disconnection and subsequent powered
reconnection.
COMPONENT SELECTION
AIiIDT logic components will support Power-off Disable on
their inputs. The IDT logic components that will support
Power-off Disable on their outputs, and liD ports include all of
the FCT16xxxT High Drive family, the FCT164245T 3.3 volt
translator, and FCT620T, FCT621T, FCT622T, FCT623T,
FCT646T, FCT648T, FCT651T, and FCT652Tfrom the eightbit family.
Component families which will not support Power-off Disable on their outputs have a parasitic clamp diode from the
device output or liD to Vcc. Some of these families are the
FCT162xxxT Balanced Drive parts, the FCT 3.3 volt devices
(except the translator), the FCT CMOS output devices, and
the FCT -T octals which have not specifically been mentioned
as having Power-off Disable.
APPLICATIONS OF POWER OFF DISABLE
Vee
There are many applications for the Power-off Disable
feature in systems that either intentionally or accidentally
become partially powered. A few of them are:
a) Fault Tolerant/Fault Resilient Systems
Fault-tolerant/fault-resilient systems often employ multiple redundancy. Critical system elements and functions are duplicated with the provision to transfer operation from one module or board to its "identical twin" if a
fault is detected. The faulty board can then be removed
from the rack for repair while the system is in operation,
and replaced by a substitute board to maintain redundancy. The active data bus on the backplane must not
be affected during the "live" insertion of the board.
b) Power Conserving Systems
Certain parts of a system may be powered off or operated at a lower Vcc to conserve power in redundant,
backup or unused circuits. The maximum amount of
power is conserved when the Vcc rail of the powered
down section is at GND potential. Under these conditions, all signal pins of the powered down circuits must
offer high impedance in order to prevent loading of the
surrounding circuits.
c) Attaching Peripherals
It is a fairly common practice for people who are using
computers and peripherals to connect the peripheral to
Cb1992 Integrated Device Technology, Inc,
2546 drw 01
Figure 1. FCT16xxxT Input Stage
SYSTEM DESIGN CONSIDERATIONS
Input Considerations
Figure 1 shows the equivalent schematic of the input stage
of an IDT FCT16xxxT Double-Density device. A signal on the
input that is between 0 volts and the Absolute Maximum
Rating Voltage will see the gate to the MOS-FET transistors,
the cathode of the clamp diode to ground, and the ESD
protection circuit. There is no clamp diode from the input pin
to Vcc and therefore the input will maintain a high impedance
when the voltage on the input rises above the Vcc level. With
25
4/92
POWER-OFF DISABLE IN lOTS FCT16xxxT DOUBLE-DENSITY DEVICES
APPLICATION NOTE AN-102
Situations to Be AVOided
Vcc at any voltage level between 0 and the maximum rated
voltage, the input voltage could be as high as the device's
Absolute Maximum Rating without damaging the device or
causing significant current drain into or out of the input.
The connection of Vcc only without GN D should be avoided.
Under this condition the devices will "look for" a ground
connection on their inputs or outputs through the clamp diode
and ESD protection circuit as the pins are connected. With all
of the components on the powered down board using a
common ground, the entire current draw of the board may
pass into the component ground pin on a single device and out
the grounded input or output of that component. If the driving
component on the other side of the connection is a bus driver
or similar device, currents high enough to cause device
damage to the connected components may occur.
Tying device inputs directly to Vcc and GND on a backplane
or cable without series resistors may also produce a damaging current flow. This situation usually arises with board
configuration pins on a backplane (e.g. for card slot identification, parity sense, pipeline register depth, etc.) All configuration pins should be current limited with series resistors if they
are to tie directly to device inputs. This same situation is
experienced if unused inputs are tied to Vcc or GND across a
cable without series resistors.
If the above situations are avoided while attaching Vcc first,
there is still the probability that bus contention or bus interference will occur which will cause system disruption during the
board installation or removal. Designers should make provisions to assure that during installation into, and removal of
components from powered systems, the GND connection is
made first.
Some methods of guaranteeing that the GND pins will
make first contact are as follows. The ground pins on the card
edge connector can be made longer than the other pins so
they make contact first. The ground pins can be placed
towards both ends of the connector with Vcc near the center
so that when the board goes in at a slight angle, the ground will
make contact first. A ground wire can be connected between
the board ground and the connection point ground prior to, and
during insertion, to assure ground contact before Vcc. In the
case of an electrically isolated connector, the connector
shroud can be grounded.
Output Considerations
Figure 2 shows the equivalent circuit schematic of an
output buffer with 3-state control as used in the FCT16xxxT
family. The output stage contains a totem-pole structure
which consists of N-Channel pull up/down transistors. These
transistors have a clamp diode from their drains to GND, but
have no clamp to Vcc and therefore no low impedance path to
Vcc through a forward biased diode.
EN
OUT
DATA~----------~
Figure 2. FCT16xxxT Output Buffer
Combination Input/Output Port Considerations
The I/O ports on IDT's FCT16xxxT High Drive and other
families that support Power-off Disable contain combinations
of the input and output structures shown in figures 1 and 2.
These parts will handle powered installation/removal and
other Power-off Disable functions with no problems.
I/O ports on families that do not support Power-off Disable
on the device outputs have a diode from the I/O port to Vcc
causing the same restrictions as the device outputs for those
families.
Using Power-off Disable
In the system design, the designer must disable the outputs
on all drivers which interface the pOint at which connection is
being made, through control of the output enable pins, to
assure that the bus interface components are not driving the
bus despite their low power condition. On devices that require
a logic high on the output enable pin (EN) to disable the output,
maintaining the output enable pins near Vec will assure that
the output is disabled despite the voltage on Vcc approaching
zero. As the Vcc level drops, the voltage required for a logic
high will drop proportionately and the high impedance is
maintained for power supply voltages from OV to Vccmax
(maximum operating Supply Voltage). If properly done, the
power down condition will be transparent to active boards on
the system bus despite other active components in the system
driving the bus to logic high conditions.
CONCLUSION
The need for Power-off Disable is becoming prevalent in
many of the high reliability and power conserving systems
currently being designed. To utilized Power-off Disable,
certain design criteria must be followed. The first item is to
assure that the ground pin is connected across the interface
before the Vcc pin, the ground pin remains connected while
Vcc is connected, and that Vcc is disconnected before the
ground pin. The second item is to condition the output enables
of the powered down component so that the device outputs
will remain disabled. The third item is to assure that there are
no inputs hardwired to GND or Vcc across the interface
without series resistors. The IDT parts which support Poweroff disable will function in partially powered situations and will
26
~
g
APPLICATION
NOTE
AN-103
3.3 VOLT LOGIC
Integrated Device Technology, Inc.
By Stanley Hronik and Suren Kodical
INTRODUCTION
The demand for an increase in performance and portability
of digital systems has created a need for integrated circuits of
ever increasing performance and density with reduced power
consumption. To meet this need, the semiconductor industry
is moving rapidly towards a lower supply voltage standard
based on 3 .3Vs nominal supply. This new standard allows the
retention of TTL threshold levels while providing improved
reliability, noise levels and a significant reduction in power
consumption. The lower power consumption internal to the
circuitry will allow component densities to reach new levels of
integration utilizing fine line technologies. Eventually it is
expected that the sophistication level of 3.3V circuitry will
dwarf 5V technologies.
Currently in the marketplace there are processors, memories and ASICs available which are either designed for or
characterized for 3.3V operation. To support and accelerate
the transition to the new 3.3V environment, Integrated Device
Technology has developed families of 3.3V logic and bus
interface circuits which will enable the designer to develop
complete 3.3V systems. The 3.3V components now available
are approaching the speeds of their 5V counterparts and in
the near future will exceed those capabilities. These speed
breakthroughs will be obtained by the further miniaturization
of components as the lowering of breakdown levels allows the
reduction in critical dimensions, path sizes, and device capacitances which will increase the device speed. Additional
benefits include an increase in reliability due to lower power
consumption and a reduction in noise generation due to lower
voltage swings.
Systems that will find use for 3.3V logic include battery
operated portable systems such as notebook/laptop computers, hand-held electronic field instruments and portable
communications gear. Space and military systems that require low power with high reliability should find the 3.3V
operation an attractive alternative. Thermally sensitive systems such as any electronic system that operates in harsh
environments or has extremely high density will benefit from
3.3V logic. Eventually the uses of 3.3V logic will exceed those
of the 5V systems.
These families are offered in a plastic Shrunk Small Outline
Package (SSOP) for commercial applications and a CERPAK
package for military applications. These packages offer significant space savings.
This Application Note on IDT's 3 .3V families will discuss the
following topics:
• Input and Output structures
• Performance characteristics
• Power, noise and reliability issues
• System considerations
• Solutions for "mixed supply" operation
KEY FEATURES OF THE 3.3V LOGIC FAMILY
The FCT3xxx and FCT163xxx families of circuits are optimized for high performance 3.3V systems. Important features
of these families include:
• True TIL compatibility with a minimum of 400 mV noise
margin.
• Rail-to-rail output swing provides additional noise
immunity.
• Quiescent power supply current of 80 f.1A maximum.
• Typical Ground Bounce is underO.3 Vforthe FCT163xxx
family and under 1.0V for the FCT3xxx family.
• Input and Output leakages guaranteed to be under
500 nanoamps.
• Propagation delays match those of 5 V FCT logic for like
functions.
• All inputs (except I/O) can be driven from either 3.3V or
5V components.
• Extended Commercial temperature range of -40°C to
+85°C.
• ESD >2000 V per MIL-STD-883, Method 3015.
The low leakage and quescent currents offer a distinct
advantage in power-critical systems through longer battery
life and improved reliability. True TIL compatibility offers the
system designer the freedom to mix 3.3V components and 5V
components on the same board in most situations without
sacrificing noise margin. By offering the same speed grades
as the 5V logic for the same function, reduced power consumption is achieved without performance compromise.
3.3V LOGIC FAMILY FROM lOT
3.3V LOGIC FAMILY CHARACTERISTICS
IDT is responding to the need for products that operate from
a 3.3 ± 0.3 volt supply by introducing new logic families which
have been named FCT3xxx and FCT163xxx. These families
contain 8-bit and 16-bit bus interface functions, key "glue"
logic elements and special interface components which solve
interfacing problems in mixed 3.3V/5V supply systems. The
IDT parts have all of the benefits inherent in 3.3V logiC as well
as, excellent drive capability and performance characteristics.
©1993 Integrated Device Technology, Inc.
DC Specifications
AppendixA shows the complete set of DC specifications for
the FCT3xxx and FCT163xxx families. These DC specifications meet or exceed the proposed JEDEC standard for 3.3V
± 0.3V TTL-compatible circuits.
27
4192
3.3 VOLT LOGIC
APPLICATION NOTE AN-t03
Input Characteristics
The input to the FCT3xxx and FCT163xxx families consists
of an ESD protection circuit, a clamp diode to GND, and the
gates of two MOSFET transistors as is shown in Figure 1.
Vee
HYSTERESIS
~ ESD-P-ROTECTION- - - - - I
-
AND INPUT CLAMP
TO NEXT
STAGE
INPUT
---- ----i---
2728 drw 01
Figure t. Input Stage of FCT 3.3V Components
The Input protection circuit provides excellent immunity
(>2000 volts) to the effects of electrostatic discharge (ESD).
It also provides an effective clamp for input voltage undershoots by forward-biasing the p-njunction during input voltage
excursions below device ground. Note that there is no similar
clamp to vee. Therefore the input can withstand a maximum
voltage rating of 7 volts, thus allowing the inputs to be driven
by either3.3V circuits or 5V circuits without exceeding maximum
ratings. Typical input V-I characteristic is shown in Figure 2.
The input translator consists of two CMOS inverters with a
feedback circuit which provides Hysteresis in the input transfer characteristic by means of a change in the ratio of Pchannel to N-channel transistor areas in the input translator.
Typical transfer characteristic with 150 m V of hysteresis is
shown in Figure 3. Hysteresis increases static noise immunity
in both logic states and also offers immunity to noise superimposed on slow edge-rate input signals if the amplitude of the
superimposed noise is less than the hysteresis margin.
VOH
40
Ii
(ma)
30
20
VOUT
(VOLTS)
Breakdown
10
VOL
-20
Clamp
-30
-40
1.40V
1.55V
VIN (VOLTS)
2728 drw 02
2728 drw 03
Figure 3. Typical Input Hysteresis Characteristics
Figure 2. Typical Input V-I Characteristics
28
---- ..........
-~
3.3 VOLT LOGIC
APPLICATION NOTE AN-103
Output Characteristics
The outputs on the FCT163xxx and FCT3xxx parts switch
rail to rail in order to provide a good noise margin and fu1l3.3V
CMOS output capability at low current levels and TIL-compatible guaranteed output levels at high drive currents. In
order to achieve the CMOS output levels there is a P channel
'source' between the device output and Vcc acting as a pullup
on the output. Inherent in this transistor is a parasitic clamp
diode between the output and Vcc which will drain excess
current if the voltage on the output rises a diode drop level
above the Vcc rail. Similarly, there is a parasitic diode to GND
associated with the N channel 'sink' transistor. Because of the
presence of the clamp diode to Vcc there is no ability to shut
off the power on a component that has an output directly tied
to an active data bus. In other words, the FCT 3.3V components have no power-down disable capability on device outputs. Also, the 3.3V output cannot be readily connected to a
5V output on a bus because of the possibility of drawing large
amounts of current through the parasitic diode under certain
conditions. When connecting a 3.3V output to a 5V bus or
output, the user needs to utilize the techniques for overcoming
this problem as described later in this document or use the 5V
to 3.3V interface components which lOT has developed to
solve this problem.
The output structure of a typical FCT 3.3V logic circuit is
shown in Figure 4. Along with this the typical Output V-I
characteristic for a high-impedance (Hi-Z) state @ Vcc =
3.3Vs is shown in Figure 5.
Vee
Figure 6 shows the output drive characteristics of the FCT
3.3V families for a logiC LOW state. The low output impedance
allows incident wave switching when driving transmission
lines of >45n (typ.) characteristic impedance. The output also
offers excellent dynamic current capability to drive large
capacitive loads without significant speed degradation. The
typical propagation delay derating is 1ns per 50pF of output
load.
140
120
100
lOUT 80
(ma)
60
Logic Low State
40
20
1.0
2.0
4.0 VOUT(V)
2728 drw 06
Figure 6. Typical Output Low Characteristics
o
o
1.0
2.0
3.0
4.0 VOUT (V)
-20
-40
-60
lOUT
(ma) -80
-100
-120
-140
Logic High State
2728 drw 07
Figure 7. Typical Output High Characteristics
2728 drw 04
Figure 4. Output Structure of the FCT 3.3V Logic Families
Figure 7 shows the output drive characteristics for a logic
HIGH state. The V-I characteristic is somewhat linear due to
the parallel combination of the P channel 'source' transistor
and the N channel transistor shown in Figure 4. Again, the low
output impedance in the logic HIGH state allows incident wave
switching when driving transmission lines of >35n (typ) characteristic impedance. The output 'pull-up' circuit also offers
excellent dynamic current drive to charge large capacitive
loads without significant speed degradation. Typical propagation delay derating is 1 ns per 50pF for the low to high
transition.
8
Clamp
6
loz
(ma)
4
2
2
Clamp
4
6
8
2
Voz
(VOLTS)
4
Vcc = 3.3
volts
POWER SPECIFICATIONS
There are three components of power supply current in
CMOS circuits. The total power supply current is given by:
2728 drw 05
Figure 5. Typical Three-State Output V-I Characteristics
Ic
29
= IQUIESCENT + IINPUTS + IDYNAMIC
3.3 VOLT LOGIC
APPLICATION NOTE AN-103
The first one is the Quiescent Power Supply current (Icc).
This is a static current through the power pins of the device
when all inputs are held at either supply rails. This current is
typically in the nanoampere range.
The second component of supply current is the sum of the
static component through the input stages (8Icc) when the
input voltage is between VCC and GND. Under this condition
both N channel and P channel transistors of the input translator shown in Figure 1 can conduct current. The magnitude
of this current is dependent on the voltage on the input pin.
Typical input translator current 81cc as a function of input
voltage is shown in Figure 8.
1.0
(nom) represents a 56% reduction in the dynamic power
dissipation.
The equation for dynamic power dissipation can be rewritten as follows:
ICCD= fCV
IcCD is expressed in mA or ~ per MHz of switching frequency
which will be constantfor a set voltage and capacitance. In bus
interface circuits with several identical paths, it is customary to
specify ICCD per bit. Over a wide frequency range, IcCD is a linear
function of frequency. Figure 9 shows ICCD for the FCT163245
16-bit transceiver in comparison with other popular 5V 16-bit
transceivers.
1.3V
25
ACT a15.5V
ACT a15.0V
""Icc O.B
Per Input
(ma) 0.6
20
0.4
Icclbit 15
(ma)
0.2
ABT at S.SV
10
FCT-T a15.5V
FCT-Tal 5.0V
FCT3.3V
5
Figure 8. Typical alcc characteristics
20
40
60
BO
100
Frequency MHz
The 81cc component is specified in the data sheets for the
FCT3xxx and FCT163xxx families at VIN = 2.4V and at VIN =
VCC - 0.6V. The first test condition where VIN = 2.4V is useful
when a worst-case power supply mismatch is expected between two circuits interfacing with each other. When the
circuits are operating from substantially the same supply
voltage, the condition of VIN = Vcc - 0.6V is more realistic. A
detailed explanation of the use of the power supply components is provided in the data sheets forthe 3.3V logic products.
The 81cc component can be significant when a 5V circuit is
driven from a 3.3V circuit, particularly if the 3.3V supply is at
its minimum of 3.0 volts and the 5V supply is at 5.5Vs. Under
these conditions, both the P channel and the N channel
transistors olthe input translator are operating in the saturation
region.
The third component of power supply cu rrent is the Dynam ic
Power Supply Current or ICCD. This component represents the
power consumed by the device in charging and discharging
the internal node capacitances of the circuit through the
transistors. Since each internal node switches between the
supply rails, the power consumption is given by the formula:
P = Vicco = fCV2
where f = equivalent frequency of the voltage transitions, C is
the net capacitance of the circuit ( sum of the switching node
capacitances) and V is the supply voltage. Notice the squared
term in the equation. This equation shows the benefits of a
lower operating voltage since a drop from 5Vs (nom) to 3.3Vs
2728 drw 09
Figure 9. ICCD vs Frequency for the 16245
A comparison of dynamic power supply current per MHz
per bit for various 16-bit transceivers is shown in Table 1. Note
that this current represents the power consumption in the
device with the outputs unloaded.
Device
IceD/MHz/Bit
Vee
240!JA
5.5V
ABT16245
90!JA
5.5V
FCT16245T
4B!JA
5.0V
FCT163245
27!JA
3.3V
ACT16245
2728 tbl 01
Table 1. Dynamic Power Supply Current Comparison
Power Consumption Due To Device Output Loading
From the preceding discussion on power supply current
components, one can see that the dynamic current will become dominant at higher frequencies. When the outputs of a
circuit drive capacitive loads, the dynamic power supply
current component due to the load capacitance increases the
device power dissipation. This component is given by the
equation:
30
3.3 VOLT LOGIC
APPLICATION NOTE AN-l03
PL = fCLV2
Since the voltage swing on the output pin is the same as
that on the internal nodes, the total power dissipation of the
device with loaded outputs is:
PTOTAL = f(CPD + CL)V2
where Cpo represents an equivalent total capacitance for
internal device nodes, CPO can be obtained from the following
equation: CPD = IceD I V (~MHz).
RELIABILITY
The 3.3V family will inherently dissipate less power and run
at cooler temperatures than corresponding 5V parts. The
reduced supply voltage level means that internal dielectrics
are not stressed at the levels they would be in higher voltage
applications and therefore device breakdowns will be less
prevalent than in higher voltage families. The lOT 3.3V
components retain the 7V breakdown voltage on device
inputs, equivalent to that of 5V parts, giving a wide margin of
protection against potentially damaging input voltage levels.
The devices also have ESO protection on the inputs and
outputs helping to avoid handling problems.
In addition to the device reliability, system reliability is
improved by using 3.3V components which generate less
system noise, reduce device power dissipation and possibly
reduce system size and cooling requirements.
NOISE CONSIDERATIONS
Accompanying the increase in system speed and bus
widths, there is a concern about the increase in system noise.
Several types of device-generated noise are associated with
high speed integrated circuits. The most commonly recognized
noise component is the Simultaneous Switching noise, often
referred to as Ground Bounce. This transient noise is a result
of voltage developed across the parasitic inductance associated with the ground return path of the circuit during simultaneous HIGH-to-LOW switching of several outputs. At its
worst, ground bounce can cause false switching and data
integrity problems in storage elements such as latches and
registers. Since the ground lead inductance plays a major role
in the amount of ground bounce generated, Octal bus interface circuits with a single ground generate more noise than
16-bit bus interface circuits with 8 ground return paths. The
3.3V logic families from lOT feature edge-rate control to
contain ground bounce to 1.0V typical in the octal interface
components and to O.3V typical in the 16-bit interface components. These noise levels are considerably lower than
those in 5V circuits of the same performance characteristics.
lOT's Application note AN-47 offers a detailed discussion on
this subject.
The second component of noise is that associated with
output edge rates. For fast edge rates a PCB trace behaves
like a transmission line. Signal overshoots and undershoots
are generated when driving such traces without termination
31
which matches the characteristic impedance of the traces.
Under the worst-case scenario, these transients can degrade
system reliability. The FCT3xxx and FCT163xxx families are
designed to minimize these noise components. For a more
complete treatment on this subject, the reader is referred to
lOT Application note AN-49 'Characteristics of PCB Traces.'
Lastly, by avoiding abrupt voltage changes during the
output voltage transitions, transmission of EMI and RFI noise
is minimized. This helps with the board layout by reducing the
need for special considerations in component placement,
decoupling, line termination, and shielding and leads to quicker,
easier designs that meet FCC guidelines.
Noise Immunity
To improve immunity to system noise, the FCT3xxx and
FCT163xxx families of components have been optimized for
an inputtrip point at 1.4 Vtypical, at the center of the guaranteed
input voltage range. Addition of the hysteresis feature further
increases immunity to noise on signal lines. Since the outputs
are designed to swing rail to rail, any 3.3V component interfacing with the 3.3V logic from lOT will experience the benefit
of an additional noise margin.
PERFORMANCE
The device performance for the FCT3xxx and FCT163xxx
families is the same as for the 5V FCT16xxxT family and
FCT xxxT families. These speeds can be seen in the lOT Logic
Data Book. Propagation delay limits of key parameters for
commonly used functions in the FCT 3.3V families are
compared with industry-accepted 74AC series devices operating at 3.3Vs. See Table 2.
Function
Path
74FCT163xxxA
74ACxxx
245
Input to Output
5.2n5
12.4n5
373
Input to Output
5.2ns
15.0ns
374
Clock to Output
6.5ns
18.0ns
2728 tbl 02
Table 2. Speed Comparison of FCT 3.3V with AC at 3.3Vs
INTERFACING 3.3V COMPONENTS TO
5V FAMILIES
During the transition from 5V to 3.3V, there will be a need
to interface between 3.3V parts and 5V parts in a system or
between a 3.3V system and a 5V peripheral. When operating
3.3V parts and 5V parts in the same system, the designer
needs to be aware of the compatibility issues between the
families and provide protection against component damage in
some cases where excess current or voltage may develop.
The 3.3V family was designed to be TTL-compatible with 3.3V
or 5V components, but there are many situations inherent in
the interface that will cause problems if the interface is not
properly constructed.
3.3 VOLT LOGIC
APPLICATION NOTE AN-103
3.3 Volt
5 Volt
5 Volt
TIL
TIL
7.0
3.3 Volt
TIL
TIL
7.0
Input and Output
Breakdown
7.0 Volts
6.0
Input Breakdown
7.0 Volts
6.0
VOH 5.5 Volts Max.
VOHMax.
3.6 Volts
5.0
5.0
4.0
4.0
3.0
3.0
VOHMin.
2.4 Volts
VOH 2.4 Volts Min.
2.0
2.0
VIH 2.0 Volts
1.0
1.0
VIL 0.8 Volts
0
GND
VIH 2.0 Volts
VIL 0.8 Volts
VOL 0.5 Volts
VOL 0.4 Volts
GND
Output Breakdown
Vcc+ 0.3V
GND
2728 drw 10
0
GND
2728 drw 11
Figure 10. 3.3 Volt Device Driving a 5 Volt System
Figure 11. 5 Volt Device Driving a 3.3 Volt Device
3.3V Logic Driving a 5V System
As described earlier in this application note, the FCT 3.3V
logic components have CMOS outputs which offer rail to rail
output swing and guarantee TTL compatible output logic
levels at high drive currents. Because of this, there is no
problem with 3.3V logic driving standard 5V TTL logic. The
logic input thresholds on the 5V TTL parts are VIL = O.BV, VIH
= 2.0V. The 3.3V logic is guaranteed to drive a LOW to less
than O.4V and to drive a HIGH to greater than 2.4V at rated
output load currents. This provides very good driving voltages
forthe 5Vinputswith noise immunity making 3.3V outputs fully
compatible with 5V TTL inputs.
Despite the logic compatibility of the 3.3V outputs with the
5V inputs, the designer needs to be aware of the slight
increase in power consumption that may occur when interfacing 3.3V parts to 5V parts as discussed in the section on power
consumption.
True 5V CMOS devices that utilize CMOS thresholds
(not TTL) require higher input voltages to reach the guaranteed minimum logic high. (The 3.3V logic is not guaranteed to
reach the output voltage levels necessary to drive CMOS level
inputs on true CMOS devices operating at a 5V supply level.)
rating on the 3.3V parts.
Problems may develop from the output clamp diode when
5V TTL outputs are connected to 3.3V outputs or I/O ports on
a bus. The logic HIGH on 3.3V device outputs and I/O ports
is limited to Vcc + O.5V. Driving a 3.3V liD port directly from
a 5V part may exceed this absolute maximum rating and
damage the 3.3V device.
Other mixed supply situations include interfaCing a 3.3V
module or sub-system with a 5V system and interfacing a 3.3V
system such as a laptop/notebook computer with an external
5V peripheral such as a printer. The 3.3V parts have no power
down disable on the device outputs and therefore they cannot
be unpowered and receiving voltage on their outputs without
sustaining damage. It is likely in a dual power supply system
that one supply will become active or shut down prior to the
other. To avoid damage to the 3.3V part, the current from the
5V outputs to the 3.3V outputs must be limited.
Members of the 5V FCT16xxxT and FCT6xxT family do
have power-down disable capability and therefore will sustain
no damage in the partially powered situation regardless of
whether only the 5V supply is active or only the 3.3V supply is
active.
To avoid excessive current flow from an active 5V output
into a 3.3V output, the user may place a resistor between each
5Voutput and the corresponding 3.3V output or I/O. When the
3.3V 110 is in a high-impedance state, a current will flow from
the 5V part to the 3.3V part through the resistor and clamp
diode causing a voltage drop between the devices and preventing damage. When calculating the value of the resistor,
the designer should consider the worst case situation of the 5V
5V Logic Driving a 3.3V System
As stated earlier, 5V logic will drive 3.3V inputs (not I/O
ports or three-state outputs) directly and will meet all voltage
levels and input requirements of the 3.3V logic without component damage on either side while retaining full functionality.
The 5V TTL component may output up to 5.5Vs worst case
which will not exceed the 7V absolute maximum input voltage
32
3.3 VOLT LOGIC
APPLICATION NOTE AN-103
supply at the maximum operating rated voltage and the 3.3V
supply at the minimum operating voltage. If the 3.3V system
may power down when the 5V system is active the calculation
should consider the 3.3V supply at zero. See Figure 12.
+5VDC or +3.3VDC
Output Stage of
a 5 volt
74FCT621T
I
R
.....-_.....-'--''--_ _ _ To any 3.3Vor 5V
Input or 1/0
-l
Vcc =
a volts
-----------,
500 ohm
5.5 volts
R must be sufficiently large to
current limit the output to less
than 20 ma worst case if R is
tied to +5V DC.
2728 drw 13
Figure 13. Using Ope Drain Components as a 3.3V Interface
5 Volt Part
Series
Resistor
I
-----------.1
I
3.3 Volt Part
._--------2728 drw 12
Using Open-Drain Components as an Interface
Figure 12. A 5V Part Driving a 3.3V 1/0 Port
Placing a series resistor between 5V and 3.3V parts will
cause some speed degradation due to the RC time constant
that will develop between the series resistor and the input
capacitance of the 3.3V part and other parts that may be
similarly attached.
The designer must be aware of the following situation
when connecting 5V parts to 3.3V parts with a series resistor.
If the 3.3V power supply is off and the 5V power supply is
active, current may flow from the 5V output into the 3.3V
output and through the clamp diode to the 3.3V power supply
plane. When this happens, the voltage on the 3.3V power
plane will rise if there is no low impedance path from the power
plane to ground. Undercertain conditions, it may rise sufficiently
to cause unstable operation of the 3.3V parts or failure of the
power on reset when the 3.3V supply is activated. This
condition may be avoided by shorting the 3 .3V power plane to
ground when the power is off. This could be done through the
use of a pull down transistor in the power on reset circuit.
Another solution is to use the 3.3V to 5V interface components
developed by lOT which avoid this and other problems.
If the user can guarantee power sequencing and tracking
between the 3.3V and 5V power supplies, the value of the
current-limiting resistor between the 3.3V inputs and 5V
outputs can be significantly reduced.
33
Another means of interfacing 5V outputs to 3.3V lID ports
is to use the FCT621 T and FCT622T 5V open drain components as interface devices. If the pull-up resistor from the
open-drain output is returned to the 3.3V supply as shown in
Figure 13, the voltage on the bus will never exceed the 3.3V
supply voltage and will assure safe operation. If the series
resistor is tied from the device output to the 5V power supply
instead of the 3.3V power supply, the output current would be
limited by the resistor and also provide safe operation.
5V TO 3.3V INTERFACE COMPONENTS
To combat the problems associated with mixed supply
operation, any of IDT's 3.3V unidirectional parts can be used
as translators when connected as described earlier. This
would include the FCT163244, FCT163373, FCT163374 and
others.
When connecting 3.3V outputs to a 5V bus, it is necessary
to use special interface components which will handle the
higher voltages on the device outputs. One of the devices that
IDT has developed for this purpose is the FCT164245Twhich
will directly tie a bidirectional 3.3V bus to a bidirectional 5V
bus. This part is also useful in situations where there is no
power sequencing or where one of the power supplies may
remain off while the other is active.
3.3 VOLT LOGIC
APPLICATION NOTE AN-103
DEVICE CONFIGURATION
AND NOMENCLATURE
CONCLUSION
Using the FCT3xxx and FCT163xxx families of logic parts
in 3.3V, high speed designs will help the designer overcome
problems with noise and power consumption, and improve
reliability. With the high density and lower power consumption, the user may be able to reduce his overall system size
and cost without sacrificing performance. Prior to the availability of a complete 3.3V family, there are techniques for
interfacing the 3.3V parts with 5V systems including special
translator functions for mixed supply environment. The
FCT3xxx and FCT163xxx families of devices are ideal for
transmission line driving, point-to-point driving, bus interface
and memory interface applications.
A1I3.3V parts are pin compatible with the industry standard
for their 5V counterparts. This includes the FCT163xxx parts
that are configured as 16 bit wide DOUBLE-DENSITY parts
for wide bus widths and the FCT3xxx octal and glue parts.
The DOUBLE-DENSITY device types within the family
retain the familiar naming conventions of the eight bit families
(e.g. 245, 373, 374 etc.) but are arranged with two octal
functions with independent control per package giving the
devices dual eight bit capability or full sixteen bit operation. An
example of the naming convention would be an FCT163245
which is a sixteen bit 3.3V device, with an FCT245T type
function.
The pins on the DOUBLE-DENSITY devices are configured so that all power and ground pins are in identical
locations for all functions. In addition data inputs have a flowthru architecture for ease of board layout.
APPENDIX A
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
VIH
Min.
Tvp.
Max.
Unit
Guaranteed Logic HIGH Level
2.0
5.5
V
2.0
-0.5
-
Vcc +0.5
O.S
V
VI = 5.5V
-
-
±0.5
J.LA
VI = Vcc
-
+0.5
VI =GND
-
-
Parameter
Input HIGH Level (Input pins)
Test Conditions
Input HIGH Level (I/O pins)
VIL
Input Low Level
Guaranteed Logic LOW Level
IIH
Input HIGH Current (Input pins)
Vcc= Max.
Input HIGH Current (I/O pins)
IlL
Input LOW Current
lozH
High Impedance Output Current
IOZL
(3·State Output pins)
VIK
IODH
Clamp Diode Voltage
Vec=Min.,IIN=-1SmA
Output HIGH Current
Vce = 3.3V, VIN = VIH or VIL, Vo = 1.5V
IODL
Output LOW Current
Vce = 3.3V, VIN = VIH or VIL, Vo = 1.5V
VOH
Output HIGH Voltage
Vce= Min.
IOH = -o.1mA
VIN = VIH or VIL
IOH = -6mA Mil.
10H = -8mA Com'l.
Vce = Min.
VIN = VIH or VIL
IOL = 0.1mA
IOL = 16mA
IOL = 24mA
VOL
Output LOW Voltage
los
Short Circuit Current
VH
Input Hysteresis
leeL
lecH
lecz
Quiescent Power Supply
Current
Vce= Max.
Vo=VCC
Vo=GND
Vec = Max., Vo = GND
Vee = Max., VIN = GND or Vee
±D.5
+0.5
J.LA
±D.5
-0.7
-60
-1.2
V
-
mA
90
-
mA
Vee-0.2
-
2.4
3.0
V
-
-
-
-
0.2
0.3
-
135
-
mA
150
-
0.02
SO
J.LA
0.2
0.4
0.5
V
mV
27281b103
34
~
:J
~
APPLICATION
NOTE
AN-116
DECOUPLING
DOUBLE-DENSITYTM
COMPONENTS
Integrated Device Technology,lnc.
By Stanley Hronik
INTRODUCTION
of simultaneous switching noise. This also reduces the effects
of inductance in the board metalization by decentralizing the
current path.
When laying out a circuit board for use with DoubleDensity, the designer should use full ground and power planes
with all ground and power pins on all devices connected to the
proper plane. No power or ground pins on any Double-Density
device should be left floating. The board should have a large
capacitor near the power entry point on the board to stabilize
any power surges from the power distribution system. If the
board has an effective power distribution system, decoupling
Double-Density should be easier than decoupling corner Vcc
and ground packages.
Double-Density is IDT's FCT-T family of 16, 18, and 20 bit
bus interface components. The family is functionally compatible with the Wide Bus product line, but offers users power
savings, higher speeds, and excellent guaranteed low noise
operation with a choice of output drive characteristics. The
components are available in a 64ma drive version for use in
backplane driving where line termination exists, a balanced
drive 24ma version with internal series line termination for
quiet operation, and a 3.3V version for use in applications
requiring the lower supply voltage.
Although IDT's Double-Density family is more forgiving
than the older eight bit families, the decoupling must be
properly executed to achieve optimum results. The three
versions of the Double-Density components (64ma, 24ma,
and 3.3V) have similar switching speeds and therefore have
similar decoupling needs despite having different device
parameters and output specifications. Because of this, the
techniques for decoupling which are addressed herein apply
uniformly across all versions of the Double-Density family.
When setting goals for decoupling a circuit, a designer
should focus his attention on reducing the radiated emissions
to meet the FCC limitations for the geographical area in which
his circuit will be used. When this has been accomplished, the
low noise levels needed to prevent cross talk and false
switching will probably have been achieved. If the circuit
contains low-level analog signals, additional decoupling will
probably be necessary.
GND
Vee
GND
GND
3
4
5
6
7
8
9
10
11
12 8048-1
13
14
15
16
17
SELECTING THE CAPACITOR PACKAGE
Vee
The effectiveness of decoupling capacitors is often degraded by the series resistance and inductance inherent in the
capacitor. The use of chip capacitors reduces the inductance
due to the capacitor leads and through hole placement,
making chip capacitors the optimum choice where that package style can be used. If the use of chip capacitors is not
possible, the package should allow the capacitor to fit close to
the board with very short lead lengths. With through hole
capacitors the excess lead should be trimmed as close to the
board surface as possible.
GND
18
19
20
21
22
23
24
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Vee
GND
GND
Vee
GND
3011 drw01
Figure 1. A 4811in Double Density package
Capacitors have a circle of influence around them meaning
that pins and components that are in the immediate proximity
of the capacitor will be effectively decoupled while those
components that are further away will be less affected. This
characteristic is modeled in Figure 2.
While the number of capacitors per component will vary
depending upon the decoupling needs of the circuit and the
cost sensitivity of the design, it is suggested that the designer
use at least one ceramic capacitor per IC on the board. In cost
sensitive applications it may be possible to reduce the overall
number of capacitors to less than one per component. In noise
PC BOARD POWER AND GROUND PLANE
IDT's Double-Density devices are packaged in a 48- or 56pin SSOP with multiple power and ground pins as shown in
Figure 1. Unlike older logic families with corner Vcc and
ground pins, Double-Density packages have eight ground
pins and 4 Vcc pins which are equally spaced on both sides
of the package. By providing multiple, short, parallel paths for
current, the lead inductance is lowered, reducing the effects
The lOT logo is a registered trademark and Double-Density is a trademark of Integrated Device Technology, Inc,
©1992 Integrated Device Technology, Inc.
35
DECOUPLING DOUBLE·DENSITY COMPONENTS
sensitive circuits (e.g. ND applications) more than one capacitor type per component may be necessary. Tantalum
capacitors work well in high frequency analog situations which
already include a ceramic capacitor.
If the board has components on only oneside, the capacitor
can be placed at either end of the device (considering the
direction to the power source) with a solid connection to the
power and ground planes as shown in Figure 4. This will give
I
I
3011 drw 04
Figure 4. Capacitor macement for boards with one component side
the board designer direct access to the sides of the package
to run traces and avoid placement interference.
If more than one capacitor is used, the capacitors can be
placed at either end of the package or if that causes placement
conflicts the capacitors can be located at adjacent corners of
the package as shown in Figure 5.
Figure 2. All capacitors have a "circle of influence" around them
CAPACITOR PLACEMENT RELATIVE TO THE
COMPONENT
+
The decoupling capacitor should be placed as close as
possible to the component being decoupled. It is not necessary to provide a separate capacitor for each Vcc on the
device, but the decoupling capacitor should be solidly connected to both planes providing a short conductive path to all
power and ground pins on the device. Relative to the component, the optimum placement would be on the reverse side of
the board, centered over the device as shown in Figure 3.
The power and ground pins on the SSOP package that are
adjacent to the device outputs will generate more switching
noise than pins near the device inputs or enable pins. Since
these pins are usually near the center of the package, placing
the decoupling capacitor on the reverse side of the board
centered over the component will provide the shortest path
from the capacitor to the pins giving optimum decoupling.
+
3011 drw 05
Figure 5. Placement of dual capacitors on the component side for
special applications
POSITION RELATIVE TO POWER ENTRY
The decoupling capacitor should be placed between the
power entry point on the board and the component that is
being decoupled as is shown in Figure 6. Since the ultimate
source of all charge is the power entry point, placing the
capacitor between the component and the entry point positions the capacitor to receive and stabilize the voltage prior to
the component. If the capacitor and component are reversed,
the charge will flow directly from the entry point to the component and not pass the capacitor. This will make it easier for
noise in the power system to reach the component, and for
noise generated by the component to propagate into the
3011 drw 03
Figure 3. Capacitor placementfor a board with components on both
sides
36
DECOUPLING DOUBLE-DENSITY COMPONENTS
power system. When the capacitor is not in the path of the
charge flow, the capacitor can only react to noise after it has
passed into the component or power system rather than
prevent it.
I
ToVCC
model can be considered as a single capacitive element with
no inductance or resistance. As the noise frequency increases to levels above 50MHz the influence of the inductance and resistance increases to the point that the inductance becomes the dominating component of the capacitor's
impedance. If noise issues are critical, the designer may be
required to use two capacitors to cover both the high and low
frequency components of the spectrum.
Capacitors that are operating near their characteristic
frequency will resonate at that frequency and provide good
noise filtration with no inductive kick. Using this characteristic,
designers frequently use a 0.01 uf or a 0.001 uf capacitor to
filter out high frequency noise. The characteristic frequency
of the capacitor can be obtained by contacting the capacitor
manufacturer. Typically ceramic capacitors have a characteristic frequency in the 20-40MHz range. Tantalum capacitors
typically work best at frequencies above BOMHz and have
decreasing effectiveness at lower frequencies.
While picking capacitors at the resonant frequency of the
circuit will prove beneficial to noise suppression, the selection
of smaller valued capacitors will not. The value of the capacitor
should always be at the resonant frequency or have a larger
capacitance value. If small valued capacitors are used, it will
be necessary to have good low frequency decoupling through
additional larger valued capacitors located near the component.
3011 drw 06
Figure 6. The decoupling capacitor works best if placed between the
power source and the pin being decoupled
FREQUENCY CONSIDERATIONS
USING CAPACITORS WITH DIFFERING
INTERNAL STRUCTURES
lOT's Double-Density components have very high internal
switching speeds, but the lead inductance, packaging, and
board placement will absorb most of the high frequency
components above 120MHz before the noise can enter the
power distribution system or radiate. The frequencies most
likely to cause problems by reaching the power distribution
system are in the 60-BOMHz range (40-120MHz on a broader
scale) and therefore the decoupling effort should be focused
on this range.
Capacitors can be modeled as a capacitor in series with an
inductor and a resistor as shown in Figure 7. With typical
ceramic capacitors at low noise frequencies «10MHz), the
When using capacitors of different values and different
types on the same board in close proximity to one another, it
is possible for the two capacitors to begin interacting with one
another. With different frequency responses, the two capacitors will respond with different timings to voltage spikes with
CAPACITOR 1
SWITCHING'
TRANSIENT
Jl
GROUND LEAD
-,---JI
r - - - - - - - - - - - - -.
NOISE
1 SPIKE
R
L
1
CAPACITOR 2
1
:j:
C
3011 drw 08
1 _____________ I
L
1
Figure 8. If using two capacitors with different characteristics,
oscillations may develop between them
1
,----------------~
3011 drw 07
the result being an instantaneous difference in the internal
voltages between the two capacitors. The two capacitors can
then begin oscillating by passing charge between themselves
through their characteristic series inductors as modeled in
Figure B. The end result will be a reduction in the effective
decoupling that takes place and the possible addition of a
noise source on the board.
Figure 7. Model of the Influence of a noise source and a decoupling
capacitor on a node
37
DECOUPLING DOUBLE-DENSITY COMPONENTS
CONCLUSIONS
Additionally, two capacitors with highly different dielectric
constants in close proximity on the same board may affect
each other because the high dielectric constant part will
dampen the high frequency resonance of the low dielectric
constant capacitor and the end result will be reduced noise
suppression.
To effectively handle the problem of capacitors with differing internal structures, be sure the two types are not placed in
close proximity to one another as shown in Figure 9. This can
be done by placing the different capacitors at opposite ends
+
To properly decouple lOT's Double-Density parts do the
following:
1) Select a capacitor that will meet the needs of the
component. A 0.1 uf ceramic is a good starting point. A 0.01 uf
ceramic may be better in situations which have good low
frequency decoupling elsewhere on the board but are experiencing high frequency noise.
2) For best results use at least one capacitor per IC. More
may be necessary in noisy situations, fewer may be possible
with careful component and capacitor placement.
3) Place the capacitor as close to the component as
possible. On the reverse side of the board is best. At either
end of the component is also good.
4) Make sure that there is a good connection between all
ground pins on the component and the capacitor. This should
be in the form of a solid ground plane under the device. The
same is true for the Vcc pins.
5) Place the capacitor between the component and the
power entry point on the board if possible.
6) In critical situations two or more capacitors of different
values may be used. In this case select a larger capacitor to
provide low frequency stability and a smaller capacitor to give
a series resonance to higher frequencies. Examples may be
a 0.1 uf or a 1uf ceramic along with a 0.001 uf or a 0.01 ufo
7) If caps of different internal structures are used, they
should not be placed in close proximity to one another.
Capacitors of different types that are close to one another may
resonate between themselves and negate any positive effect
of using two capacitors.
+
&SSSSSj
3011 drw 09
Figure 9. Exercise care when positioning two capacitors with
differing frequency response in close proximity to one another
of the device or equally spaced on the backside of the board.
If these choices are notfeasible, the capacitors can be spaced
in opposing corners of the device. The key to placement is to
avoid having the Vcc pins of two capacitors adjacent or having
the Gnd pins of two capacitors adjacent.
38
APPLICATION
NOTE
AN-118
MAXIMUM FREQUENCY
CONSIDERATIONS FOR
THE IDT49FCT80S/6
Integrated Device Technology, Inc.
By Anupama Hegde
INTRODUCTION
Power dissipation in an unloaded CMOS device can be
calculated using the following equation:
An important factor in determining maximum operating
frequency of a device is total power dissipated in the device.
In CMOS circuits, the total power dissipation is dominated by
the frequency-dependant dynamic component, since the static
component is typically very small. The maximum permissible
power dissipation is determined by the thermal characteristics
of the package and the environment, which, in turn, sets the
upper limit forthe operating frequency. Although this is true for
all CMOS circuits, the implications are particularly important in
the case of clock drivers, where multiple outputs are continuously switching at the system clock rate and are driving
significant capacitive loads.
Factors that influence the maximum operating frequency of
a device based on power dissipation include:
• Maximum allowable junction temperature for reliable
operation
• Junction-to-ambient thermal resistance of the device
• Ambient temperature
• Inherent device power dissipation characteristics
• Number of TTL level inputs
• Number of outputs switching
• Output loading
The following equations demonstrate how these factors
determine operating frequency limits.
Po (unloaded) = (ICCQ + ~Icc Nr Dr + Nof Icco)Vcc
1
1
static power
1
1_'1--'
...
dynamic power
...... (iia)
where,
f = output frequency
ICCQ = static or quiescent current
Nr = Number of TTL level inputs
~Icc = static current due to TTL level inputs
Dr = Duty cycle of TTL level inputs
Icco = dynamic power supply current per MHz per bit
No = Number of output bits switching at frequency f
Some manufacturers express the dynamic power dissipation component in terms of another parameter - Cpo, rather
than Iceo, as shown above.
Cpo = Iceo/Vcc = equivalent device power dissipation
capacitance
Equation (ii) may be expressed in terms of Cpo as follows:
Po (unloaded) = (lcCQ + ~Icc Nr Dr +NofCpoVcc)Vcc
.......... (iib)
MAXIMUM FREQUENCY CALCULATIONS
In order to determine the maximum operating frequency,
one must first calculate the maximum allowable power dissipation based on thermal limitations and maximum allowable
junction temperature for the device. Starting with the thermal
equation;
9JA = (TJ - TA)/PO
the maximum allowable power dissipation for a device is given
by:
POMAX= (TJMAX - TA)/9JA
.......... (i)
where,
9JA = Junction to Ambient thermal resistance of the device
TJ = Junction Temperature
TJMAX = Maximum allowable TJ (TJMAX = 150°C for IDT
logic devices)
TA = Ambient Temperature
Po = Total Power Dissipation
POMAX = Maximum allowable Power Dissipation based on
TJMAX
Device loading can dramatically alter the dynamic power
dissipation. Additional power is dissipated due to switching of
the load. Consequently, equations (iia) and (iib). change as
follows with the addition of a load:
Po (loaded) = Po (unloaded) + NofCLVOH2
= (Iceo + ~Icc Nr Dr + ND f Icco) Vcc + NofCLVOH 2
1
1 1
static Ipower
I
1
dynamic power
.......... (iiia)
= (ICCQ + ~Icc Nr Dr + NofCpoVcc) Vcc + NofCLVOH 2
.......... (iiib)
where,
CL = Load Capacitance
VOH = Logic High Output Voltage level (which is the
voltage across the load)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2912
©1993 Integrated Device Technology, Inc.
39
12/9'
MAXIMUM FREQUENCY CONSIOERATIONS FOR THE IOT49FCT805/6
APPLICATION NOTE AN-118
Since CMOS devices have a negligible static power dissipation component, and VOH equals VeeforCMOSoutputswing
FCT devices, equation (iiib) is sometimes approximated as;
Assumed conditions:
TA = 25°C
Vee = 5V
11 bits switching
CL = 40pF (on each output)
No airflow/cooling
}
Package = 20-pin SOIC } ==> (9JA = 90°C /Watt)
f = operating frequency in MHz
TIL level inputs (for CMOS level input signals ~Iee = 0)
PD (loaded) = PD (unloaded) x [1 + CllCPD]
.......... (iiic)
From eqn(iiia),
PDMAX = (leeQ + ~Iee NT OT + NDfMAX IceD) Vee +
NDfMAXCLVOH2
.......... (iv)
This gives:
PDMAX =(TJMAX - TA) / 9JA = (150- 25) / 90
... using equation (i)
= 1.38W
Substituting the PDMAX value obtained from eqn(i) in equation (iv) gives:
Power dissipation of the device, at frequency f, with no load is:
(TJMAX- TA)/9JA = (leeQ+~lee NTOT + NDfMAX IceD) Vcc
+ NDfMAXCLVOH 2
PD (unloaded) = (1.5+2.5x 2 x 0.5+0.2 x f x 11)mA x Vee V
... using equation (ii)
= (4 + 2.2f) mA x Vee V
= 5(4 + 2.2f) x 10-3 W
For a given set of operating conditions, the only variable in
this equation is the frequency. So, transposing all other factors
to the righthand side gives the operating frequency limit.
With the assumed 40pF loading on each output:
=
fMAX
{(TJMAX-TA}/9JA {NolccoVcc + NOCLVOH2}
(lcCQ+~lccNTDT}VCC}/
PD (loaded) = PD (unloaded) + [11 f x 40 X 52 X 10-6]W
... using equation (iii-a)
= PD (unloaded) + [111 x 10.3] W
.......... (v)
The application of these equations is illustrated in the
following example for the lOT 49FCT805/6 clock drivers.
Using eqn (iv) gives:
1.38W = PD (unloaded) + 11fMAX x 10.3
1.38W = 5(4 + 2.2fMAX) x 10-3 + 11 fMAX x 10-3
1.38W = 5(4 + 4.4fMAX) x 10-3
=> fMAX = 62.2MHz
This is the figure obtained assuming TTL level inputs. With
CMOS level inputs, since ~Iee = 0, fMAxgoes up to 62.7MHz.
Similar calculations can be done to obtain the operating
frequency limits for various other cases. The table below gives
fMAX values for these different cases.
Example (for the 49FCT80S/6)
49FCT805/6 specifications:
leeQ = 1.5mA
~Iee =2.5mA
IceD = 0.2mAlMHzloutput
#of Bits
TA
11
25°C
6
70°C
11
25°C
6
70°C
11
25°C
11
70°C
NOTES:
1. LFM = Linear Feet per Minute.
2. Graphs for 9JA are given in Section
Load
40pF
40pF
40pF
40pF
40pF
40pF
Package
20-pin SOIC
20-pin SOIC
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SOIC
Airflow(1)
o LFM
OLFM
OLFM
OLFM
250LFM
250LFM
6JA(2)
90°CIW
90°CIW
10rCIW
107°CIW
82°CIW
82°CIW
fMAX
62.2MHz
72.5MHz
52.2MHz
60.6MHz
68.4MHz
43.4MHz
2913 tbl 01
4.1
of 1992 High-Performance Logic data book.
SUMMARY
This application note discusses frequency limits based on
thermal considerations. The theory discussed here is applicable to all CMOS devices, but the issue is particularly
relevant to clock driver operation. This is due to the large
number of simultaneously switching outputs and higher aver-
40
age power dissipation in clock drivers, as compared to other
logic devices such as simple data/address buffers. Other
considerations such as timing margins may fix an even lower
maximum operating frequency than one calculated on the
basis of thermal limits, in which case, power considerations do
not limit the operating frequency.
d
~
APPLICATION
NOTE
AN-47
SIMULTANEOUS
SWITCHING NOISE
Integrated DevIce Technology, In~.
By Suren Kodlcal
INTRODUCTION
ence between the device power trace (ground or Vcc trace) and the
external power plane. The term "lead" used here refers to the combination of bonding wire and package pin. A specific area of interest is the simultaneous switching of several "sink" transistors during the logic HIGH to LOW transition and the resultant transient potential difference between the chip ground and the external ground
plane. This phenomenon is the simultaneous switching noise on
the device (chip) ground plane and is commonly referred to as
"GROUND BOUNCE".
Second, the high dynamic drive currents will cause very fast voltage edges at the switching outputs of the device subjected to predominantly capacitive loads. For example, a load capacitance of
50pF (equivalent of 6 to 7 typical CMOS inputs) will be discharged
at a rate of 2V/ns during the high-ta-Iow output transition if the dynamic drive current of the output sink transistor is 100mA. Such
rapid edge rates will make relatively short PCB traces look like
transmission lines. For example, a 2V/ns edge rate will make a
typical trace of 6 inches or more look transmissive. These fast
edges will contribute to system noise due to ringing, overshoots
and undershoots on the signals, EMI and RFI due to sharp output
voltage transitions and cross-talk between two adjacent signal
lines on a PCB surface.
In this application note we will discuss the phenomenon of
GROUND BOUNCE, its contributing factors and some design and
application guidelines for minimizing the effects of ground bounce.
The ne~ for in~reasing levels of throughput and improved performance '" today s systems has placed certain demands on the
logic. and interface ~evices used in these systems. Two of the key
reqUirements are high speed and high dynamic drive. Often the
traditional glue logic and interface parts are in the critical timing
paths and playa key role in determining system performance. Better s~eed (shorter propagation delays) lead to improved timing
margl~s and offer opportu~ities for performance upgrading. The
techniques used for Improving the speed also result in faster edge
ra~es at ~he .outputs of these devices. As edge rates get faster,
p~lnted circuit boa.rd traces and back plane wiring appeartransmisslve at shorter distances. More and more interconnections between circuits now have to be treated as transmission lines. This
scenario leads to a requirement for higher dynamic drive at the outputs of. m~st ~igh-speed circuits in order to drive low impedance
transmission lines and to sustain high levels of DC current nthe
traces or backplane wiring are terminated at the far end.
Thi~ ~imultaneo.us r~qu!remen.t for high speed and high drive has
certain Important Implications. First, the high speed in most CMOS
integrated circuits is achieved by improved device processing and
topology. Internal nodes slew faster and transistors reach their
saturation c~rren.t more r~pi~ly, result~ng in a higher rate of change
of curre~t (dI/t!t) '" all sWltc~,"g transistors. Since most outputs of
glue logiC. and Interface deVices are designed to handle high levels
of dy~amlC current, the ~ate of build-up of current is particularly severe In the output transistors. When several outputs switch simultaneousl~, the total build-up of current in the common ground or
Vcc lead Inductance can be substantial (of the order of 200mAlns
to 300mAlns) and can develop a large transient potential differ-
THE "GROUND BOUNCE" PHENOMENON
Figure 1 shows the equivalent circuit of a typical CMOS output
buffer stage with the package parasitics and the external load.
PCB Vee PLANE
: ~ Vee Lead
CHIP Vee
SWITCHING
CURRENTS
FROM
OTHER
CIRCUITS
ON CHIP
Output Lead
Cl
LOAD
Ground Lead
-+ ,:
Figure 1. Output Buffer with External Parasltlcs
© 1988lnllegratod Device Technology, Inc.
41
111811
APPLICATION NOTE A~7
SIMULTANEOUS SWITCHING NOISE
The parasitic components which influence ground bounce are;
(a) inductance and resistance of the ground bond wire and pin, (b)
inductance and resistance of the output bond wire and pin, and (c)
load impedance. Forfirst order analysis, the parasitics associated
with the Vee terminal can be ignored. Also the external ground
plane is assumed to be ideal.
During the output high to low transition, the sum of output load
current and all switching current through the internal gates of the
device flows through the ground lead. The rate of change of this
current (di/dt) develops a voltage drop across the ground lead inductance (Lg) and causes a positive ground bounce or an overshoot in an otherwise quiet ground. This positive bounce is normally followed by an undershoot coincident with the voltage
waveform on the output terminal. The amplitudes of both positive
and negative ground bounce are a function Lgdi/dt and of the number of outputs switching simultaneously. The ground bounce phenomenon can be clearly observed at an unswitched "LOW" output
of a device by switching several other outputs simultaneously from
logic HIGH to LOW. Figure 2 shows a typical output voltage transition and the corresponding ground bounce as observed at the unswitched LOW output.
The positive ground bounce is primarily the result of the rate of
change of current (dig/dt) through the ground lead inductance.
This rate is determined by the rate at which the gate to source voltage (Vgs) of the sink transistor changes. During the early part of
the output fall time, the ground voltage rises while the output voltage (at the drain of the transistor) falls, forcing the sink transistor
into the linear region. The transistor then behaves like a resistor
Ron (the "on" resistance of the transistor in the linear region). For
the remainder of the output voltage excursion, the equivalent circuit at the output can be treated like a resonant L-C-R circuit
formed by the ground and output lead inductance, load capacitance and the total resistance in the loop which includes Ron. The
oscillation frequency is determined by the net values of Land C
while the damping is determined by L and the total resistance in the
loop.
VOUT
. . . - - (SWITCHED OUTPUT H ~ L TRANSITION)
1
• _ _ _ _ _ POSITIVE GROUND BOUNCE
V
NEGATIVE
GROUND
BOUNCE
TIME
Figure 2. Ground Bounce Waveform
allel with a soon resistor to ground. Two outputs are connected to
the oscilloscope; one for observing the HIGH to LOWtransition of a
"switched" output and the other for observing the ground bounce
on the "quiet" output. At these outputs, the soon load is split into a
450n resistor in series with the son input impedance of the scope
probe. Alternatively, a soon load resistor can be returned to
ground and a high impedance probe connected to the device output pins.
With careful layout, proper bypassing to filter out high frequency
noise and with a good oscilloscope and probes (bandwidth of at
least 400 MHz), it is possible to observe the ground bounce on the
internal ground of the chip by observing the voltage at the unswitched "LOW· output whose sink transistor operates in the linear
region and provides a "Kelvin connection" to the chip ground.
Ground bounce is also generated during the output LOW to
HIGH transition. However, the magnitude of this ground bounce is
much smaller because of the absence of load current in the ground
lead.
GROUND BOUNCE MEASUREMENT
There is no industry standard per se for measuring ground
bounce. However, the method most commonly used by IC vendors
and customers alike is based on observing the disturbance of the
logic LOW level of an unswitched output of a multiple output device
while switching all other (or several other) outputs from HIGH to
LOW state. Figure 3 shows the schematic for measuring ground
bounce on a device such as the FCT244 octal buffer. One output is
in the LOW state while 7 outputs are switched simultaneously. The
load on each output consists of a SOpF capacitor to ground in par-
42
APPLICATION NOTE A~7
SIMULTANEOUS SWITCHING NOISE
@
@
oselLLoseop
PULSE GEN
PRR = 1 MHZ
50 OHM
OUT
INPUTS
LOAD CAPACITORS ARE
PLACED AS CLOSE TO
THE OUT AS POSSIBLE
Figure 3. Ground Bounce Teat Circuit
A scheme similar to the one shown in Figure 3 can be adapted for
any multiple-output circuit. It can also be modified (by changing
the load on the switched outputs) to observe and measure ground
bounce during HIGH Z to LOW transitions in devices with 3-state
control.
rameter also determines the saturation current (dynamic drive current) in the output sink transistor. A shorter Leff results in a faster
device, but at the same time gives a larger di/dt in the sink transis·
tor. Therefore, there is a direct correlation between ground bounce
(caused by di/dt) and speed. This relationship is shown in Figure 4
where the positive ground bounce is plotted as a function of tpHL for
an FCT244 device in PDIP, SOIC and LCC. The ground bounce is
measured at room temperature and Vee = 5V using the test
method shown in Figure 3.
THE RELATIONSHIP BETWEEN GROUND
BOUNCE AND SPEED
In CMOS circuits, the effective channel length (Leff) is the primary determ inant of speed. However, for a given topology, this pa·
3
2
(voHs)
Vg
3
4
5
tPHL
6
(ns)
Figure 4.
Figure 4 illustrates two important points. First, because faster
devices show a higher amplitude of ground bounce, one must exercise caution when comparing different logic families or different
vendors for ground bounce. The samples to be compared should
be in the same type of package and their propagation delays
should be in close proximity. Second, package parasitics (ground
lead inductance in particular) have a significant impact on the mag·
nitude of ground bounce. In a standard DIP package, the corner
pin ground lead inductance (pin #10 in a 20 pin package) is around
12 nH. In an SOIC this inductance is only about 7 nH and shrinks to
around 4 nH in an LCC. The difference in ground bounce ampli·
tude for different packages is clear from the above graph.
43
SIMULTANEOUS SWITCHING NOISE
APPLICATION NOTE AN-47
rent in the transistor. As more outputs switch simultaneously, the
peak current in each transistor actually decreases, although the total current in the ground lead increases. This "diminishing returns"
effect results in a non-linear relationship between ground bounce
and the number of outputs switching simultaneously.
Figure 5 shows the ground bounce for an FCT244 octal buffer in
a PDIP package measured on pin #18 under nominal operating
conditions.
EFFECT OF NUMBER OF OUTPUTS
SWITCHING
Ground bounce increases as more outputs switch HIGH to LOW
simultaneously. Actual measurements indicate that the relationship is not linear. The reason is as follows. When the chip ground
voltage rises due to the Ldi/dt effect, it modulates the gate-tosource voltage (Vgs) of the sink transistor and limits the peak cur-
Vg
(V)
EXPECTED
RANGE
o~---+----r---+----+--~~--~----
2345678
NUMBER OF OUTPUTS SWITCHING
Figure 5. Simultaneous Switching Effect on Ground Bounce
skew for an FCT244 device used as a clock driver. The actual
measurements were made under worst case commercial temperature and Vee conditions for speed.
In critical clock driving applications, the absolute magnitude of
output skew can be reduced by using devices in SOIC or LCC
packages. Switching fewer outputs per device will further reduce
the skew. However, this approach has to be weighed against the
device to device skew if more packages have to be used as a result.
4. The most serious effect of ground bounce is associated with
the loss of dynamic noise margin which results in the loss of stored
data in latches and registers. This loss of noise margin is often
caused by the negative ground bounce which follows the high to
Io.w transiti~n of several simultaneously switching outputs (see
Figure 2). Simply stated, the undershoots on the chip ground lower
the input threshold, or trip point, of the device. This has the same
effect as an input making a LOW to HIGH transition relative to the
chip ground. Hthe undershoot is large enough to bring the input
threshold near the logic LOW level of any of the inputs held LOW
(with reference to the external ground plane), all dynamic noise immunity in the input stage of the device is destroyed. The apparent
LOW to HIGH transition of clock (or latch enable) and any logic
"LOW" data inputs of registers (or latches) will have the effect of
losing stored "LOW" data which is now replaced by "HIGH" data.
EFFECT ON DEVICE PERFORMANCE
Ground bounce causes a variety of effects in the application environment as described below:
1: The most commonly. observed effect is the noise on a "quiet"
logic LOW output level In a device when several other outputs
~witch from high to low simultaneously. Ifthe amplitude ofthe positive ground bounce exceeds the input threshold of the device
driven by it, then all noise margin disappears and the driven device
may recognize the noise as a legitimate input transition. A worka~und for this problem is to allow some settling time before the
signals atthe output of the device are treated as valid. This solution
g~.nerally appl!es to combinatorial paths only. A large positive transition on certain control signals such as CLOCK, LATCH ENABLE,
RESET, etc. can cause loss of data. Such a problem can only be
solved by taking steps to reduce the magnitude of the positive
g~ound bounce below the recognition level (threshold) of the device.
2. Changes in the chip ground voltage disturb the thresholds or
trip points, of internal gates. This can cause non-monotonic output
transitions that look similar to the effect of short unterminated
transmission lines. Often this is not a serious issue.
3. The phenomenon described in (2) also causes a skew or a
separatio~ betwe?n edges.of several outputs switching simultaneo~sly. ThiS skew IS a function of the number of outputs switching.
Figure 6 shows the effect of simultaneous switching on output
44
SIMULTANEOUS SWITCHING NOISE
APPLICATION NOTE AN-47
SKEW: SEPARATION BETWEEN THE
FASTEST AND THE SLOWEST EDGE
WHEN SEVERAL GATES ARE SWITCHED
SIMULTANEOUSLY IN THE SAME DIRECTION
1000
800
600
Tskew
(ps)
400
EXPECTED BOUNDS
200
0
2
3
4
5
6
8
7
NUMBER OF OUTPUTS SWITCHING
Figure 6. Effect of Simultaneous Switching on Output Sk_
Using Smaller Packages
Since ground bounce is the voltage induced in the ground lead
inductance by the rapid rate of change of current through it, there is
a direct correlation between the amount of inductance and the
magnitude of ground bounce. Ground lead inductance can be reduced by using packages with smaller internal cavities and lead dimensions. For example, for corner Vee and GND configuration,
the typical ground lead inductance for a 20 or 24 pin Plastic DIP
package is of the order of 12 nH to 15 nH. This inductance drops to
about 7 nH in an SOIC package and to about 4 nH in an LCC package. Figure 7 shows the effect of package lead inductance on the
positive ground bounce for an FCT244 device.
Another method of reducing ground lead inductance is to arrange the pad layout such that the power pins (particularly the
GND pins) are at the center of the package for the shortest lengths.
Mhough this is an acceptable solution, it raises standardization
and compatibility issues on industry-standard functions. This
choice does exist for new functions and as an addition to existing
standard functions.
SOLUTIONS TO THE GROUND BOUNCE
PROBLEM
Ground bounce is a pervasive phenomenon. It can be minimized
or circumvented, but rarely eliminated since the parasitic inductance cannot be totally removed from the package. The solutions
to the ground bounce problem take essentially two forms; (a) minimizing the effects of ground bounce and (b) minimizing the magnitude of ground bounce.
To minimize the effects of ground bounce, the design should be
made "ground bounce tolerant". This can only be done at the expense of system throughput, since additional time must be allowed
for the ground bounce to settle. As a result, the benefit of using
high speed logic is partially negated.
The techniques for minimizing the magnHude of ground bounce
take many forms. They are generally aimed at reducing eHher the
parasHic inductance, or the amount of dildt or both. These techniques are discussed in some detail below.
MEASURED ON OUTPUT: PIN 18
3
2
Vg
(volts)
1
MEASURED
RANGE
o
o
4
8
12
16
GROUND LEAD INDUCTANCE - nH
Figure 7. Effect of Package Lead Inductance
45
20
SIMULTANEOUS SWITCHING NOISE
APPLICATION NOTE AN-47
Series Damping
di/dt can be reduced either by limiting the magnitude of the peak
current (Imax) through the ground leador by slowing down the buildup of the total ground lead current during the output transition.
The value of Imax depends on the size of the output sink transistor
as well as on the load. Since this is a dynamic phenomenon, the
peak current depends more on the amount of energy stored in the
load capacitance.
One effective method of limiting the magnitude of Imax is to use a
series damping resistor at the output. During the output transition,
this resistor comes in series with the "on" resistance of the output
buffer and limits the peak current, and hence the di/dt. Figure 8
shows the effect of series damping resistance on ground bounce
for an FCT244 device.
3
NO SERIES DAMPING
2
(voHs)
Vg
3
4
5
tpHL
6
(ns)
Figure 8. Effect of Series Damping on Positive Ground Bounce
As seen from the figure above, the series damping resistor
causes a significant reduction in ground bounce. However, it is important to understand the implications of using series damping.
Since the total output impedance is significantly higher, the transmitted signal is attenuated at the driving end; the attenuation being
determined by the source impedance (Ro + Rs) and the loaded
transmission line impedance (ZL). Ro is the "on" impedance of the
output circuit. This attenuation limits the amplitude of the first incident wave. Therefore, the series damping technique must be used
with caution and is not recommended if first incident wave switching is desired. This subject is covered more thoroughly in the Application Note entitled "SERIES TERMINATION'. The series
damping resistor, if properly chosen, does have the advantage of
limiting overshoots and undershoots on the transmitted signal
without increasing system power dissipation.
The series damping resistor also decreases the magnitude of
negative ground bounce and the undershoot on HIGH to LOW
transitions. Therefore, series damping is effective in driving CMOS
memories, particularly DRAMs where undershoots on input signals are undesirable.
swing at the output is limited, less energy stored in the load. For
example, if the output swing is limited to 3.3 volts nominal (similar
to most bipolar or BiCMOS totem-pole outputs) instead of rail-torail, the energy stored in the output load can be decreased by a factor of 2.5:1 for a given load capacitance. This results in a smaller
positive as well as negative ground bounce.
There is a beneficial side effect of this method. Since the high to
low transition starts from a lower voltage level, the fall time component (the time taken for the output to switch from the logic HIGH
level to the 1.5V measurement level) of tPHL is smaller than that for
a rail-to-rail transition. This translates into an improvement in tPHL.
However, since speed improvement is not the primary objective,
some or all of this speed improvement can be sacrificed in order to
further reduce the simultaneous switching noise. This can be
achieved by means of a circuit configuration which provides a
smaller initial dildt during the logic HIGH to LOW transition. The
resulting degradation in the output fall time cancels the speed improvement. In practice, about 40 improvement in ground bounce
(relative to rail to rail swing output) can be obtained for the same
speed. The FCT- T family of products introduced by lOT has been
designed using this approach. Figure 9 shows the ground bounce
characteristics for IDT74FCT244T/AT devices in PDIP and SOIC
packages in comparison with the IDT74FCT244/A.
Reduced Output Swing
Another technique for reducing ground bounce relies on limiting
the energy stored in the load on the device output(s). If the voltage
46
SIMULTANEOUS SWITCHING NOISE
APPLICATION NOTE AN-47
3
244 BUFFER
2
Vg
(volts)
+ SIMULATION DATA
C
3
CHARACTERIZATION DATA
4
5
tpHL
6
(ns)
Figure 9. Improved Ground Bounce In FCT-T Family
duced by using smaller packages with lower ground lead induc·
tance, by switching fewer outputs of a device simultaneously, or by
using a series damping resistor in the rail-ta-rail swing FCT logic.
The new FCT-T logic family is designed to offer much smaller
ground bounce at the same speed by reducing the output voltage
swing and by controlling the dildt in the ground lead during the output transitions.
SUMMARY
The requirement for high speed and high drive results in the phenomenon of ground bounce or simultaneous switching noise in
high speed logic and interlace circuits. The effects of ground
bounce range from a noise spike on a quiet output to data loss in
registers and latches. The magnitude of ground bounce can be re-
47
USING HIGH-SPEED LOGIC
APPLICATION
NOTE
AN-48
Integrated DevIce Technology. Inc.
By Suren Kodlcal
This application note gives some general guidelines and recommendations for using high speed logic such as FCT, FCT A and
FCT B family of products.
when compared to driving with devices with bipolar outputs which
have a higher logic low level due to the offset voltage of the Schottky-damped NPN sink transistor.
b. Reducing DC loading, Le. reduce the fanput, on the outputs of devices that drive the data and control inputs of latches and
registers.
c. Using devices with "hysterisis" on the inputs. This will further improve dynamic as well as static noise margin.
d. Use of series damping resistors (25 to 35 ohms) at the
output of latches and registers will reduce the undershoot on the
device intenal ground due to simultaneous switching of mu~iple
outputs of the device. This undershoot normally follows the overshoot (also referred to as the ground bounce).
Series damping will overdamp the series L-C-R circuit
formed by the parasitic ground path inductance, load capacitance
and the low impedance of the sink transistor.
2. Several measures can be taken to reduce the power supply
noise - both ground bounce and Vee bounce:
a. Contention should be avoided on devices connected to a
bus. Although bus contention is not detrimental to the device in a
normal application, it causes very large positive and negative di/dt
in the ground and Vee paths. Such contention has the same effect
as charging a very large load capacitance.
b. Series termination (i.e. series damping resistors) will also
reduce the magnitude of the ground bounce by limiting the maximum transient current and thereby decreasing the total energy
transferred to the parasitic inductances.
c. Use of local high frequency filtering will minimize the
propagation of noise on ground and Vee traces.
3. Avoid running control lines through a device that drives datal
address buses.
4. Since the magnitude of ground and Vee noise is a direct function of parasitic inductance, if all other conditions are unchanged,
much benefit is gained by using packages with lower bond-wire
and lead inductance. Thus, surface mount packages (SO, LCC,
PLCC, etc.) will offer lower levels of ground and Vee noise than
standard DIP packages
5. Output drive "overkill" should be avoided. In non-critical
paths, use of low-drive circuits will generally reduce the overall
supply noise.
6. In very high speed circuits, minimize the loading per device to
reduce total load capacitance.
POWER DISTRIBUTION
1. Use Ground and Vee planes on mu~i-Iayer boards.
2. On two-layer boards with no Vee and Ground plane, use a
"grid" type ground distribution system to equalize ground potential
at different points on the P C board.
3. Use Power Distribution Elements - PDEs (conductor-dielectric-conductor) to reduce characteristic impedance. Use separate
PDEs for devices that sw~ch large amounts of sink and source currents.
4. Do not use jumper wires for ground connections.
5. Provide a separate "noisy" ground distribution for high current drivers, particularly those driving backplanes.
6. Place high current driving circuits near their loads. For example, place backplane drivers at the edge of the board.
7. Make adequate provision for supplying transient energy to
handle PC trace impedance and load capacitance. This is done by
connecting individual bypass capacitors across the power pins of
high current switching circuits.
8. Use low-inductance, ceramic disk capacitors (4700 pFto 0.1
uF) for high frequency fi~ering. These can be used in parallel with
normal bypass capac~ors.
SIGNAL TRACES
1. Treat the PC board traces as transmission lines. A conservative rule of thumb is to consider a trace as a transmission line if the
unloaded signal transition time at the driving end equals the
round-trip propagation delay for the trace in question. Typically,
the transmission line delay is 0.15 ns per inch, or 0.3 ns for one inch
round-trip. That means, for a transition time of 2 ns, a trace longer
than 7 inches should be considered as a transmission line.
2. To minimize cross-talk between signal traces, avoid running
sensitive signal lines close to traces connected to high current drivers.
3. Any signal lines that cross each other should be placed at
right angles to further reduce cross-talk.
DEVICE SELECTION
1. Select devices which offer the largest amount of "real" noise
margin. Ground noise due to simu~aneous switching of multiple
outputs causes a loss of dynamic noise immunity in the logic low
state. Therefore, it is important to improve "low level" noise immun~y. This can be achieved by:
a. Using CMOS outputs to drive inputs of "storage" devices
such as latches and registers. This will offer better noise margin
SUMMARY
A combination of high speed (particularly fast edge rates) and
high drive contribute to increased noise in power supply path as
well as in signal paths. Much care is needed to minimize such
noise so that maximum performance benefit is derived from the
FCT family of high speed logic products.
© 111881ntog_ DevIce T_agy, Inc.
11/88
48
APPLICATION
NOTE
AN--49
CHARACTERISTICS OF
PCB TRACES
fJ
Integrated DevIce Technology. Inc.
By Suren Kodlcal
Printed circuit board traces carrying high speed digital signals
can behave like transmission lines for fast edge rates of the driving
signal. The transmission line effects can cause signal distortion.
~vershoots •. undershoots and crosstalk between adjacent lines. It
IS therefore Important to understand this behavior for trouble--free
board design. In this application note we discuss the transmissive
effects of PCB traces. the relevant electrical parameters and a simple technique for measuring unloaded or loaded characteristic impedance.
PCB TRACE AS A TRANSMISSION LINE
A PCB trace is normally regarded as a very low impedance medium which carries electrical signals from one point to another.
This is true for most signals with relatively slow edge rates (long
rise and fall times). However. when a trace is subjected to fast
edge rates. its behavior changes completely. It behaves like a
transmission line with a certain characteristic impedance Z. This
impedance now presents a load to the driving circuit. In addition.
the transmissive trace introduces a finite signal delay from source
(driving end) to destination (receiving end). The equivalent circuit
for a transmission line. represented by distributed l+R and C is
shown in Figure 1.
Lo
---------~
T
Figure 1. Tranamlsslon Une -
In this schematic.
La = Inductance of the trace per unit length. and
Co = Capacitance per unit length.
For the purpose of this discussion the series resistance can be
ignored. thus treating the PCB trace as a "Iossless" transmission
line. The subscript "0" implies that the inductance and capacitance
pertain to the "unloaded" condition. i.e. the inductance is the "self
inductance" of the trace and the capacitance is that offered by the
dielectric separating the trace in question from the adjacent conducting media.
Two important parameters can be derived from lo and Co. The
first one is Zo. the characteristic impedance of the trace. The second parameter is To. the propagation delay per unit length of the
trace. It should be noted that the parameter Zo is independent of
the length of the trace.
Equivalent Circuit
Zo = (lo/Co )1/2. normally defined in ohms ......... (l)
To = ( loCo )1/2 per unit length. normally defined in
nanoseconds ..... (2)
Example
A typical MICROS TRIP PCB trace (a dielectric separating the
trace from the ground plane on one side and free air on the other 3
sides of a rectangular trace cross-section) which is 10 mils wide
and 1.5 mil thick separated from the ground plane by 15 mil glassfilled epoxy has a typical Co =2 pF/inch and La =10 nHlinch. Using
the above equations. we get Zo = 70 n and To = 0.15 ns/inch. The
table in Figure 2 gives various transmission line geometries and
their parameters.
© 1989ln1egratod Device Technology. Inc.
11/89
49
CHARACTERISTICS OF PCB TRACES
APPLICATION NOTE AN-49
TYPE
CO-AX
WIRE OVER
GROUND
Zo
ohms
To
ns / inch
@
50-125
0.13
0
70 -170
0.14
30-150
0.15
15 -100
0.19
50-200
0.16
GEOMETRY
GND
.1211;i~~6.I¥
MICROSTRIP
LINES
GN12-I.
STRIP LINE
GN~I: :;~:;::::;I
PC BOARD
TRACES
I
-I
I
.",...,
E:ll
DIELECTRIC
I
Figure 2. Transmlsalon Une Geometries
input capacitance, most CMOS inputs offer a capacitive load (ignoring the effects of input lead inductance).
As a result, the transmission line parameters are modified under
the loaded condition, because the additional distributed load capacitance must be taken into account in addition to the unloaded
distributed capacitance Co.
To simplify the discussion,let us assume that the distributed load
capacitance is represented by Cl per unit length, as shown in Figure 3.
EFFECT OF LOADING
The concept of an unloaded transmission line applies to pointto-point connections which consist of a driver and a receiver at the
two ends of a trace, with no connections to the trace in-between.
Most often, a PCB trace is tapped at several points and connected
to inputs of several ICs. Clock, RIW, Chip Select lines and Data
and Address buses are examples of this. These IC inputs represent a quasi-<:listributed load to the driving circuit. Whereas bipolar TTL inputs present a DC leakage path to Vee in addition to the
.. ---_.- --------_._ .. _.---_ ..
UNIT
LENGTH
Figure 3. Loaded Transmlaslon Une
10 pF per inch .. Using the example for the PCB trace given earlier,
the loaded parameters can be calculated using equations (3) and
Taking the effect of CL into account, the loaded trace impedance
ZL and the loaded transmission delay TL per unit length are given
by:
ZL = Zo [ Col (Co + Cl) ]1/2 ohms............................... (3)
andTl - To [(Co+ CL)/CO p/2 per unit length ................... (4)
(4):
Zl =70 [2/ ( 2+ 10 ) )1/2 =70[ 1/6 p/2 =7012.45
TL = 0.15 x 2.45 = 0.37 nslinch.
=29 Q
and
Example
This example illustrates the need for a significantly higher drive
as the trace impedance drops from 70 Q to 29 Q. It also shows the
impact of such loading on clock skew caused by the increase in
transmission delay.
Consider a clock driver driving a bank of registers in DIP package, mounted 0.5 inches apart. Assuming a typical input capacitance of the clock pin of 5 pF, the PCB trace is loaded with 5 pF
capacitance every 112 inch. This is equivalent to a distributed Cl of
50
APPLICATION NOTE AN-49
CHARACTERlsncs OF PCB TRACES
ful. Described below is one such method which is particularly applicable to traces with well-{jistributed loading.
Equipment required:
1. Pulse generator with known source impedance (typ. 50 0)
and capable of rise and fall times faster than 2.5 ns.
2. Oscilloscope: >350 MHz bandwidth.
3. High impedance scope probes.
WHEN IS THE PCB TRACE TRANSMISSIVE?
As a general statement, a PCB trace looks like a transmission
line for fast edge rates of the transmitted signal. To quantify this, a
commonly used rule of thumb is:
TREAT A PC BOARD TRACE AS A TRANSMISSION LINE IF
Ts...2Lx h.
Method
a. Hthe source impedance of the pulse generator is~, it
can be easily obtained by observing the unloaded output
waveform of the pulse generator, and then loading the pulse generator output with a resistance that will halve the amplitude of the
original signal. The value of this load resistance is the source impedance (Rs) of the pulse generator.
b. Connect the pulse generator and the oscilloscope to one end
of the PCB trace. Use a minimum of 9 inches of PCB trace. Insert
the devices that will form the distributed load on the PCB trace. See
Figure 5.
In this equation, T = output transition time (rise or fall time)
TL= loaded transmission delay per unit length.
T l = To for the poinHo-point case
l = length of the PCB trace
Example
Consider the loaded transmission line in the example cited
above. If the clock driver has an output transition time of 5 ns, the
length at which the PCB trace should be treated as transmissive is
given by:
l = T 12Tl - 51 (2 x 0.37) = 6.8 inches.
I! is clear that, with slower edge rates a driver can drive longer
traces without transmission line effects. The table in Figure 4
shows the limiting signal line length for different logic families
based on typical edge rates for each of the families and lYRical unloaded signal traces.
lOGIC FAMILY
PCB TRACE
SIGNAL LINE LENGTH·
(INCHES)
lS
25
S,AS
11
F,ACT
8
AS,ECl
6
FCT, FCTA
5
'SCOPE
Figure 5. Tesl Sel-Up for Measuring PCB Trace Paramelers
c. Set up the pulse generator to obtain a 5V amplitude square
wave of 1 MHz frequency. Adjust the rise and fall times to get 30 ns
(10% to 90%). These slow edges ensure that the PCB trace behaves like a lumped load and not like a transmission line. Overshoots and undershoots on the waveform are avoided. Record the
amplitude (Vs) observed on the oscilloscope under these conditions as shown in Figure 6A.
d. Now change the setting on the pulse generator to get the
fastest rise and fall time. Observe the high to low transition on the
oscilloscope. Note that there is a step in the output transition as
shown in Figure 6B. Record the amplitude of the first segment of
the output transition (VI) and time interval between the start of the
first transition and the start of the second transition (2l x T l).
e. Determine the characteristic impedance of the loaded PCB
"Length above which the signal trace looks like a transmission line.
Figure 4. Signal Line Length vs Logic Family
This table shows that, as we go to faster logic devices, it becomes more critical to understand the transmission-line effects.
Note that the signal lengths given in the table are not guarantees
for any logic family. The actual limiting signal length is a function of
trace and board characteristics, trace loading and the edge rates of
individual devices in any logic family.
MEASUREMENT OF PCB TRACE
PARAMETERS
trace (Zl) by the formula:
Zl = Rs x [VII (Vs - VI) 1
Since both Zl and Tl depend on board layout and loading, a simple practical method of determining these two parameters is use-
51
CHARACTERISTICS OF PCB TRACES
v
APPLICATION NOTE AN-49
Vs
V
J
-- --
Q
2L·T,
~
Time (ns)
Measuring Vt and TL with Fast Edge Rate
Time (ns)
Measuring Vs w~h Slow Edge Rate
Flgure6A.
Flgure6B.
device may not respond to the signal at the driving end (see Figure
SB) until the reflected wave reinforces the signal after a turnaround delay along the PCB trace. This implies that if a driver is
driving a PCB trace from one end, the receiver nearer to the driver
will respond afterthe receiver at the far end of the PCB trace. Such
skew may be unacceptable in certain conditions.
The relative values of trace impedance and the load impedance
at the far end also determine the amount of reflection and hence
the overshoots and undershoots on the waveform. By understanding the implications of transmissive traces, a designer can choose
the right termination and drive capability of the driving circu~ to derive the maximum benefit.
The line propagation delay to the end of the trace is given by TL.
Example
=
In a test performed on a 9 inch trace, we get As - 45 n, VI 2.8 V
and 2L x TL = S ns. Then,
ZL = 45 x [ 2.8 / (5 - 2.8) I
=57n.
TL= S/(2x 9)
= 0.33 ns per inch
THE IMPORTANCE OF PCB TRACE
CHARACTERISTICS
SUMMARY
The relative values of source impedance (As) of the driving circuit
and the loaded characteristic impedance of the transmission line
(ZL) determine the effectiveness of driving transmission lines. As
Rs increases for a given ZL, the amplitude of the transmitted component of the waveform (VI) decreases. If the transmitted wave
does not cross the threshold of a receiving device, the receiving
This application note describes the effect of fast edge-rates on
the behavior of PCB traces. A simplified method for measuring the
trace parameters in a given application environment is shown. The
procedure discussed here can be extended to fully loaded backplanes.
52
~
g
APPLICATION
NOTE
AN-50
SERIES TERMINATION
Integrated DevIce Technology. Inc.
By Suren Kodlcal
Series termination is one of several forms of terminating transmissive lines. In this bulletin we discuss the pros and cons of series
termination and the effect of termination impedance on simultaneous switching noise (a.k.a. Ground Bounce).
SERIES TERMINATION
Figure 1 shows a typical case of a series terminated driver connected to a load via a PCB trace.
~ Flo, •
WHY TERMINATE?
With the constant push for higher speeds, particularly in the area
of standard logic and bus interface products, system designers
have to deal with devices with fast edge rates. At the same time,
high packing density of multl-layer boards results in PC board
traces with low loaded impedance and long transmission delays.
This combination of fast edge rates and low transmission line impedance requires the system designer to pay careful attention to
PCB design in order to maximize the benefits of today's highspeed logic. As more and more devices on the boards go to CMOS
technology, typical nets consist of outputs with fast edges looking
into transmission lines with some distributed capacitance along
the line or lumped capacitance of CMOS IC inputs at the end of the
line or a combination of both. In the absence of some form oftermination, overshoots and undershoots on the signal can impose
bandwidth limitation on the system, or subsystem due to settling
time requirements or, even worse, can cause false triggering and
data loss.
Termination oftransmission lines is the time-honored method of
improving signal quality. There are several forms of termination:
a. Parallel or shunt termination: a single resistor terminated
to either Vee or GND at the end of the PCB trace. For backplanes, termination is provided at each end.
b. Series termination: a single resistor is connected between
the output node of the driver and the PCB trace or any other transmission line being driven.
c. Thevenln termination: two resistors form a potential divider
at the far end of the transmission line. The junction of the two resistors goes to the transmission line and the two ends typically go to
GND and Vee. This type oftermination is commonly used on backplanes at both ends.
d. RC termination: an R-C series combination is connected
between the transmission line and GND at the far end.
Each of the termination schemes listed above has certain advantages and disadvantages. A detailed discussion of the relative
merits of these schemes will be part of a separate application note.
In this issue, we will focus on SERIES TERMINATION.
~\
DRIVER
PCB TRACE
Zo
+-TD--'
€
LOADS
" - - SERIES TERMINATION
Rs
Figure 1.
The effective output impedance of the driver is now the sum of
device source impedance (Ro) and the series terminating resistance (Rs). This modified output impedance of the driver comes in
series with the characteristic impedance (Zo) of the PCB trace and
forms a potential divider for the incident signal. Therefore, the signal that propagates down the trace is a fraction of the "open-circuit" signal at the driving end. The magnitude of the transmitted
wave is given by the following equation:
VI = Vs [ Zo I (Ro + Rs + Zo) I ................ (1)
This equation shows that, as the total source impedance approaches the characteristic impedance of the line, approximately
half of the incident wave will be transmitted to the other end of the
trace. Since the load impedance is much larger than Zo due to the
high input impedance of the CMOS devices, most of the transmitted wave is reflected. As a result, overshoots and undershoots on
the signal are minimized at the receiving end. If Ro + As is much
smaller than Zo, a larger portion of the incident wave is transmitted
down the trace. Since most of it is reflected, such a condition will
cause overshoots and undershoots at the receiving end. Figure 2
shows the effect of series termination under prefect matching (total
source impedance equals trace impedance).
UiT"'
G)
OPEN-CIRC
SIGNAL AT
NO'"
SENDING-E
SIGNAL AT
Wl
To
To
To
RECEIVING END
SIGNAL AT
-
,.---
To
J
@
Figure 2.
© 1988 Integrated Device Technology, Inc.
11i8t
53
SERIES TERMINATION
APPLICATION NOTE AN-SO
The example shown highlights some important points:
1. For the best signal quality, the series terminating resistor
should be chosen such that the total source impedance (Ro + Rs) is
close to the characteristic impedance of the PCB trace. It is not essential that the two quantities match exactly. It is, however, important to ensure that the total source impedance is not greater than
the trace impedance. Otherwise, multiple reflections may be
needed to obtain the entire signal transition at the receiving end.
2. The waveforms in Figure 2 clearly show the effect of series
termination on the waveform at both the sending end A and receiving end B. For a perfectly matched condition, the signal will attain
the final value at the sending end after a round-trip delay ( 2To ),
although it will attain the final value after one transmission delay
(To) at the receiving end. H loads (several IC inputs) are distributed along the PCB trace and are driven by the driver at one end,
this condition results in signal skew which may be unacceptable.
Therefore, series termination may not be the most suitable form of
termination for distributed loads. Of course, the ratio of source to
trace impedance can be adjusted to ensure that the threshold of
the receiver is crossed on the first Incidence of the transmitted
wave, but this is normally at the expense of some undershoot and
overshoot during signal transitions.
3. There is no limit to the number of lumped loads (as shown in
Figure 1) that can be used, provided that the total DC loading does
not reduce the static noise margin because of a voltage drop
across the series terminating resistor. This implies that series termination is well-suited to drive inputs of CMOS devices because
of their very low input current requirements. The primary limitation
to the number of CMOS loads is the additional delay due to the total input capacitance being driven.
4. When series termination is used with lumped loads, the distance between the indvidualloads should be kept to a minimum. If
the loads being driven are spread apart, a preferred method of driving them from one source is to make several groups of loads and
drive each group from the driving source via individual transmission lines with their own series termination resistors. The driver
should of course be capable of handling this additional transmission line loading.
5. It is clear that the series termination does not add any power
dissipation to the system. it is, therefore, the preferred form of termination if power dissipation is a key consideration.
6. Series termination adds flexibility to the design in that the termination values can be tailored to suit a variety of trace characteristics and timing requirements.
Reworking equation #1 , we get:
Zo= (Ro+ Rs)[ (VOH-V1l)/VIL)
Therefore,
Rs = Zo [ VIL I (VOH - VIL) j- Ro
............... ( 2 )
Using the values for Vs and VI and for a device source impedance of 6 ohms, the maximum value of series termination resistance which will assure incident wave switching is given by
Rs = Zo [0.81 (4.8 - O. ) j- 6
= (0.2Zo - 6) ohms
For example, ff the PCB trace impedance is 70 ohms, the maximum value of series termination resistance is 8 ohms to assure incident wave switching. A similar consideration for the low to high
transition yields the expression:
Rs = Zo [ ( VOH - VIH) I VIH )- Ro .............. ( 3 )
For a VOH = 4.8 V, VIH = 2.0 V and a source impedance of 25
ohms in the logic high state, the maximum value of series termination resistance to assure incident wave switching is,
Rs = (1.4Zo - 25) ohms
Again, if the PCB trace impedance is 70 ohms, the maximum
value of Rs is 73 ohms. This indicates thatthe high to low transition
is the worst case.
The above example shows that a requirement for incident wave
switching will impose severe restrictions on the series termination
resistance due to the high to low switching case. Since the termination value is much less than the trace impedance, a certain
amount of overshoots and undershoots are to be expected on the
output waveform at the far end of the PCB trace. In effect, the incident wave switching requirement is in conflict with signal integrity
for FCT logic devices with rail to rail output switching when using
series termination. If signal integrity is the primary consideration,
then the series termination has to be chosen to match the trace impedance. However, signal skew has to be tolerated when driving a
transmission line with distributed loading. Alternatively, series termination should be limited to driving lumped loads at the far end of
the transmission line (PCB trace).
In high-speed switching circuits, series termination offers another advantage. When driving predominantly capacitive loads,
the series resistor serves to limit the peak current in the output
pull-down transistor and therefore the resultant di/dt in the parasitic lead and bond wire inductance. This has the beneficial effect
of limiting the amount of ground bounce (induced by the L.di/dt effect) as a result of simultaneous switching of high drive outputs.
SERIES TERMINATION WITH FCT DRIVERS
Like most TTL-<:ompatible drivers designed to meet the standard DC specffications, the FCT output buffers offer different output impedance in the logic LOW and HIGH states. Typically, the
output impedance is 6 ohms in the LOW state and 25 ohms in the
HIGH state. Since the internal thresholds of all TTL-<:ompatible
devices (independent of technology) are with reference to GND
and the noise immunity is normally worse in the logic LOW state, it
is important to consider the logic LOW state and the high-to-Iow
transitions when evaluating the effect of terminations.
First, let us consider the requirements for first incident wave
switching. The aim is to cause enough voltage swing on the first
part of the transmitted wave to cross the threshold of a receiving
device close to the driver. For a typical VOH of 4.8V with CMOS
P-channel pull-up transistors and specified VIL = 0.8 V for the receiver, the required amplitude of the incident signal is VI. VOHVIL = 4.8 - 0.8 - 4 V. The open circuit swing is Vs = 4.8 V.
SUMMARY
Series termination is an effective method for minimizing overshoots and undershoots on signals with fast edges and for reducing the amount of ground bounce caused by simultaneous switching. An understanding of the device output characteristics, particularly the output impedance values, is required to properly determine the value of series termination in order to assure incident
wave switching.
54
-..
~.
APPLICATION
NOTE
POWER DISSIPATION IN
CLOCK DRIVERS
AN-51
Integrated DevIce Technology, Inc.
By Suren Kodlcal
Power dissipation in switching circuits is discussed in this bulletin, particularly with reference to CMOS clock driver circuits. The
IDT54/74FCT244 octal buffer is used as an example to compare
the power supply current in CMOS, bipolar and bipolar-based BiCMOS technologies over a wide range of operating frequencies.
ECI2M.
First, we need to determine the Cpo for the device. Since Cpo =
leeoN in pF if IceD is expressed in IJAIMHz, we can determine Cpo
using the max. limit specified for lecD in the data sheet. Therefore,
Cpo = 250 15.5 = 45 pF
POWER DISSIPATION COMPONENTS
When the device is loaded with 30 pF capacitance per output, the
dynam ic dissipation component increases due to load. The loaded
value is given by,
There are two components of power dissipation in integrated circuits. One is the steady-state component. This is the dissipation
when all inputs are held at some fixed voltage level. The other
component is frequency dependent and is generally referred to as
the dynamic component.
In CMOS and CMOS-based BiCMOS circuits, the steady-state
component is further divided into two sutrcomponents; the quiescent power supply current (Icc) primarily due to device leakage
and the quescent power supply current when inputs are at TTL
high level (6Icc). This latter component applies to circuits with TTL
compatible inputs. In bipolar and bipolar-based BiCMOS circuits,
no such distinction is made and it is customary to specify power
supply current for a given logic state on the output(s).
The dynamic component of power dissipation (ICCD) is dominant
in CMOS circuits because most of the power is dissipated in moving charge in the parasitic capacitors of CMOS gates. Therefore,
the simplified model of a CMOS circuit consisting of several gates
looks like one large capacitor which is charged and discharged between power supply rails. For this reason, a parameter called Cpo
(power dissipation capacitance) is often specified as a measure of
this equivalent capacitance and is used by the designers to estimate the dynamic power supply component. In the bipolar technology, the dynamic component is generally very small in comparison with the steady-state component because internal voltage
swings are small.
Since power supply parameters are traditionally specified under
"unloaded" condition, a comparison of power dissipation for a
given device type (FCT244 with F244, for example) based on data
sheet numbers alone can be misleading. For a true "apples-to-apples" comparison, the effect of capacitive load on the device
should be taken into consideration. This is particularly true in the
case of clock drivers which drive heavy capacitive loads and operate at high frequency. Under these conditions, the dynamic power
dissipation component due to output loading could be significant in
both bipolar and CMOS circuits. This is illustrated in the following
section by using the '244 Octal Buffer as an example.
leGD ( loaded) = { (Cpo + Cl) I Cpo} ICGD
= { (45 + 30) 145 } 250 IJA I MHz I bit
= 0.42 mA I MHz I bit.
When all eight outputs are switching simultaneously, the total
IceD (loaded) is 3.3 mAlMHz.
If quiescent power dissipation is ignored, the above equation can
be used to determine the total power dissipation at any frequency
when the input levels are CMOS compatible. For the case where
the inputs are driven from a bipolar TTL device, the 6lcc component needs to be added in order to obtain the total power dissipation. Assuming a 50 duty cycle, for 61ec (max.) of 2 rnA, this static
Icc component is 8 rnA. Figure 1 shows the power dissipation versus frequency for both conditions.
F244
The specified power dissipation is lecl R 90 rnA and IccH = 60
rnA. For a 50 duty cycle, the steady-state dissipation is 75 rnA. In
addition, the dynamic dissipation component appears due to the
external load capacitance and the output pin capacitance of the
device. For Cl = 30 pF and COUT 10 pF (assumed), the dynamic
component can be derived:
=
IceD (loaded) = 40 pF x (4.3 V - 0.3 V) in IJAIMHz.
= 160 IJA I MHz I bit
where the 4.3 V - 0.3 V represents the voltage swing (for Vce =
5.5V) on the total load capacitance. For 8 outputs switching simultaneously, lecD is 1.28 mAl MHz. The total dissipation as a function of frequency is also shown in Figure 1.
BCJ244
The BCT family from TI is developed with a bipolar-based
BiCMOS process. Therefore, the power dissipation characteristics are similar to F244. The steady-state dissipation is 57.5 rnA
for a 50 duty cycle. The dynamic component of the dissipation is
1.28 mAlMHz. The total power dissipation versus frequency is
again shown in Figure 1.
'244 Example
Considerthe '244 as a clock driver with 30 pF load on each of the
8 outputs, operating at room temperature and Vee ~ max. Power
dissipation of IDTs FCT244 is compared with F244 (FAST"') and
Tl's BCT244. Data sheet numbers are used where applicable.
© 1989ln1ogratod Device Technology, Inc.
11/88
55
POWER DISSIPATION IN CLOCK DRIVERS
APPLICATION NOTE AN-51
The graph in Figure 1 shows that over a wide range of frequencies the power dissipation of FCT family of circuits is much less
than that of BCT and F families, even under heavy capacitive
loading.
120
100
80
TOTAL
Icc
(mA)
60
! FCT244!
(TIL LEVEL INPUTS)
40
20
o
5
10
15
FREQUENCY (MHz)
20
25
Figure 1. Total Icc va Frequency
method can be extended to any other product and can be used to
determine realistic power consumption if the loading and effective
operating frequency can be estimated for each device.
SUMMARY
A simple method for calculating "real" power dissipation in an operating environment is shown by using '244 as an example. This
56
APPLICATION
NOTE
AN-52
FCT OUTPUT STRUCTURES
AND CHARACTERISTICS
~
Integrated DevIce Technology, Inc.
By Sure" Kodlcal
ration is designed to give a resistive characteristic during the LOW
to HIGH transition at the output.
INTRODUCTION
The FCT family of products has gone through an evolution in
terms of die size, process technology (critical dimensions) and circuit implementation. Originally, the family of products was derived
from the Z-step gate arrays ("4004" gate array for small gate count
and "8000" array for large gate count). Later, a "shrunk" version of
the smaller array was developed to obtain performance improvement. This array is called the V-step. Recently, some of the high
volume runners have been "customized", i.e. redesigned to minimize the die size and get some performance improvement with a
more efficient topology. These customized versions are called the
W-step devices. The current FCT portfolio consists of a mix of Z, V
and W step devices. This bulletin describes the output structures
used in different steppings and the corresponding output characteristics for the logic HIGH and LOW states.
"4004" Z- STEP OUTPUT BUFFER
The schematicforthe buffer used in the "4004" Z step devices is
shown in Figure 1. This output consists of an N-channel "sink"
transistor which turns on in the logic low state at the output and
maintains a logic low voltage close to GROUND for normalloading.
The pull-up or "source" circuit consists of a combination of a Pchannel transistor, an N-channel transistor and an NPN bipolar
transistor with a series current limiting resistor. This circuit configu-
Figure 1. Stap Output Structure
The output V-I characteristics for the Z step output structure in
the logic HIGH and LOW states are shown in Figures 2A and 28,
respectively.
(VOUT)
o
2
3
4
5
250
200
-50
150
(mA)
-100
(mA)
100
-150
50
-200
o
-250
2
3
4
5
(VOUT)
Rgure 2B. "4004" Z Step Logic "Low" Characteristics
Figure 2A. "4004" Z Step Logic "High" Characteristics
The output characteristic in the logic HIGH state is dominated by
the current limiting resistor in series with the NPN pull-up transistor. As the output reaches the Vee rail, the output characteristic is
primarily influenced by the P-channel transistor. In the logic LOW
state, the output characteristic is that of a large N-channel pulldown transistor. Note that the characteristics shown in Figure 2
represent typical process parameters at 25°C.
© 111891ntegra1td Device Todmalogy, Inc.
11/88
57
FCT OUTPUT STRUCTURES AND CHARACTERISTICS
APPLICATION NOTE AN-52
Y-5TEP OUTPUT BUFFER
The circuit schematic for the Y step output buffer is shown in Figure 3.
Figure 3. Y-Step Output Structure
This output structure is designed to get shorter propagation delays. The output characteristic in both HIGH and LOW states is
non-linear as shown in Figures 4A and 48, below.
(VOUT)
3
4
5
250
200
-50
150
-100
(rnA)
(rnA)
100
-150
50
-200
o
-250
2
3
(Vour)
4
5
Figure 4A. Y Step logic "High" Characteristics
Figure 4B. Y Step Logic "Low" Characteristics
W STEP & "8000" Z STEP OUTPUT BUFFER
structure consists of a parallel combination of P--channel and Nchannel transistors in the pull-up circuit and a large N--channel
transistor in the pull-down circuit.
The schematic of the output buffer used in the "8000· Z step gate
array as well as the W step devices is shown in Figure 5. The
58
FCT OUTPUT STRUCTURES AND CHARACTERISTICS
APPLICATION NOTE AN-52
Figure 5. W Step and "8000" Z Slep Output Structure
The pull-up structure yields an almost resistive characteristic in
the logic HIGH state. The characteristic in the logic LOW state is
again non-linear due to the N~hannel transistor.
These output characteristics are shown in Figures SA and S8.
(Vour)
o
2
3
4
300
5
250
-50
200
-100
150
(mA)
(mA)
-150
100
-200
50
-250
o
2
3
4
5
(Vour)
Figure 6A. W & "8000" Z Step Logic "High"
Characterlsliea
. Figure 68. W & "8000" Z Step Logic "Low"
Characterlstlea
The characteristics are intended to aid the designer in developing
nominal circuit simulation models so that the effect of driving different types of lumped and transmissive loads can be evaluated. In
order to develop suitable models. the customer should first determine the stepping for the subject device. This information can be
obtained by contacting IDTs LOGIC Marketing group.
SUMMARY
The output V-I characteristics are determined by the circuit implementation and transistor geometries. Output buffer schemes
and the corresponding typical characteristics for FCT devices
manufactured in the Z. Y and W stepping are shown in this bulletin.
59
~
g
APPLICATION
NOTE
AN-53
POWER-DOWN
OPERATION
Integrated DevIce Technology, Inc.
By SureR Kodlcal
power-down operation because the logic high noise immunity is
not compromised. In addition. these circuits have the following design features:
• The inputs (except for 110 ports) do not have a clamp diode to
Vee but do have a clamp diode to ground to prevent
excessive undershoot on the inputs.
• The outputs have P-channel pull-up transistors to raise output
high level close to Vee.
The P-channel devices have a junction diode as an integral part
of the geometry. To prevent this junction from floating. the cathode of this diode is tied to Vee. the most positive potential. Similarly. the N-channel transistors used in the output circuit have an
integral junction diode whose anode is tied to GNO. the most negative potential. Figure 1 shows the diodes associated with inputs
and outputs.
INTRODUCTION
In a POWER-DOWN mode. a device operates with a supply voltage that is lower than the normal operating range of 5V ± 5 for commercial grade and 5V ± 10 for military grade. This should not be
confused with the "/ow-powerdissipation standby mode" of CMOS
static RAMs where part of internal circuitry is shut off to reduce
standby power. The power-down mode is used to either conserve
power in a part of a system or to provide a battery back-up in faulttolerant systems. The devices operating in the power down mode
are expected to co-exist with other devices which are connected to
normal power supply rails in the same system. This bulletin discusses the use of our FCT devices in the power---.
tPLHA1
OUTPUT A2
OUTPUTA1
tPLHA2
OUTPUT A2
OUTPUT An
MIN DELAY
tPLHAn
INPUT
DEVICEB
OUTPUT An
OUTPUT B1
\
.••
L---{S>--.
tPLHB1
OUTPUT B1
OUTPUT B2
MAX DELAY
tPLHB2
OUTPUTB2
OUTPUT Bm
tPLHBm
Package Skew, t SK(T) =
tP(max Device B) - tP(min Device A) =
OUTPUTBm
MAX-MIN DELAY
tSK(T)
t PLHB2 - tPLHAn
(same transition, temperature, supply
voltage, loading and package type)
2521 drw 07
Package skew is the difference in propagation delay
between the fastest and the slowest outputs of two
or more devices for the same input and output transition.
Figure 7. Package Skew t8K(T) Schematic and Timing Diagram
74
CLOCK DISTRIBUTION SIMPLIFIED WITH
IDT GUARANTEED SKEW CLOCK DRIVERS
APPLICATION NOTE-B2
THE IDT49FCT805 & IDT49FCT806 CLOCK
DRIVERS
where two generalized clock drivers are driven by a common
input. The result is "n" outputs from device A and "m" outputs
from device B making the same transition. The package skew
is the difference in propagation delay between the slowest
output of one device and the fastest output of the other device
for the same transition. In this case the output An is the fastest
output and the output B2 is the slowest If tPLHAn is 4.0ns and
tPLHB2 is 6.0ns the package skew is 2.0ns. Certain conditions
must be satisfied for the package skew specification to apply.
The devices must have the same Vce, ambient temperature
and be assembled in the same package type. Also each
device must have equivalent loading and be of the same
speed grade.
Part-to-part skew is difficult to specify because it implies
that the characteristics every part ever sold will operate within
a window of operation. The window of operation ensures that
parts that run too fast or too slow do not get sold. Figure 8
shows the measured values of package skew on several
IDT49FCT80SAs under typical conditions. The maximum
measured package skew from this sample is S2S picoseconds. In the IDT49FCT80S/806 data sheet this value is
guaranteed to be less than 1.S nanoseconds over the commercial operating range.
The IDT49FCT80S and 49FCT806 are high-speed guaranteed skew clock driver chips specifically designed to meet
the clocking requirements of today's high-performance systems. The logic diagram and pin configuration of the
IDT49FCT80S are given in Figure 9. The IDT49FCT806 is the
inverting option of IDT49FCT80S.
Skew inthe IDT49FCT80S/806 is minimized throughout the
design process. Careful circuit design and layout in silicon
have resulted in a pin configuration that is specifically designed
for very low output and pulse skew. Independent power and
ground pins reduce the amount of ground bounce and dynamic threshold shift caused by multiple outputs switching.
The 1:S input to output ratio reduces the amount of capacitive
loading on the previous stage which simplifies termination and
reduces component count when compared to conventional
solutions. The devices are optimized for both PDIP and SOIC
packages.
The IDT49FCT80S/806 clock drivers consist of two independent banks of drivers. Each bank drives five output buffers
from a single standard TIL compatible CMOS input. The input
has 200mV of hysteresis for increased immunity to system
noise. Independent active low output enable pins (OEA and
OE8) control each of the banks, allowing for independent
control ofthe outputs. This feature may be used in applications
where clock bussing or a power savings mode is required. The
input INB drives the B bank as well as an output called MON
(Monitor). The MON output is not controlled by OEB and
therefore runs continuously. The MON signal can be used for
priming phase locked loops or driving diagnostic hardware.
Each IDT49FCT80S/806 has 3 ground pins and 2 VCC
pins. The ground pins, GNDA and GNDB, are located in the
middle of the package to minimize inductance in the ground
return path. The two grounds are returns for the A and B bank
output buffer and pre-driver currents. The third ground pin,
GNDa (Quiet Ground), provides a ground return for the
remaining circuitry. The ground pin arrangement reduces
ground bounce on the outputs and noise on the thresholds of
the internal logic. Since GNDA and GNDB are completely
49FCT805A PACKAGE (PART-TO-PART) SKEW
VERSUS TEMPERATURE
Vee = S.OV
2.0 - . - - - - - - - - - - - - - - ,
1.S ~---- tSK(T)
Package
•
Skew 1.0":
(ns)
SPEC----~
.
O.S
···.·.·.w.·.·.·...... ,·,·,·,,·,·,·,···········,·,·,·,··,·," ..., ......
-...........
..... .... .......:...
:.:.:-~:-:.:-:
~
~
:.:~.:
MEAS.SKEW/
0.0 ~-r-"--...
.-"r-r--."T.-r-r---y,-r-.,-"
o
20
40
60
80
TEMP (C)
2521 drwOB
Figure B. Measured Package Skew tSK(T) for SeveraIIDT49FCT805As
20· PIN
DIPORSOIC
OA1-0As
OB1-0Bs
VCCA
VCGS
OA1
OA2
OA3
081
OB2
OB3
GNDs
GNDA
OBs
OB6
OA4
OAs
GNDa
MON7
OEA
OEB
INA
INB
PIN CONFIGURATION
LOGIC DIAGRAM
2521 drw 09
Figure 9. Logic Diagram and Pinout of the IDT49FCTB05
75
CLOCK DISTRIBUTION SIMPLIFIED WITH
IDT GUARANTEED SKEW CLOCK DRIVERS
APPLICATION NOTE-82
isolated from each other on the die, switching effects on one
bank will have minimal effects on the other bank. The independent Vec pins, VeeA and VeeB, supply power to the two
banks.
Each output of the lOT49FCTB05!B06 clock driver features
a high current drive output buffer. These outputs can be used
to drive both TTL and CMOS loads. With a typical Vol of 0.3
volts the buffer can sink64mA. For a typical Voh of 3.B volts the
output buffer can source 24mA. These output buffers are
optimized around the 1.5 volts switching threshold which is the
standard for TTL compatible logic. These output buffers can
easily meet Ihe edge rate requirements of loday's microprocessors and peripheral components. Typical edge rates for
Ihe IOT49FCTB05A are 1.0 volVnanosecond for risetime and
2.0 vall/nanosecond for falltime
The Switching Characteristics (Table 1) for the FCTB05N
B06A show the maximum propagation delay (tPLH/HL) to be
5.B ns and the minimum propagation delay to be 1.5ns. If the
skew is calculated by subtracting the minimum delay from the
maximum delay the result is a number much larger than the
tSK(O) spec of 700ps. How can lOT guarantee a 700ps output
skew number and still have such a wide range of minimum and
maximum propagation delay values?
The range of values between the minimum and maximum
propagation delay reflects the wide range of conditions under
which the part must operate and the range of manufacturing
process parameters. Consider a part that under typical conditions has a median propagation delay of 5.0ns. According to
the tSK(O) specification of 700ps, each output of that driver will
switch within a 5.0±0.35 ns window. If the median propagation
delay drops to 4.0ns, due to variations in Vee or temperature,
the specification guarantees that each output will then switch
within a 4.0±D.35ns window. In the unlikely event that the
operating conditions cause the median delay to drop to
1.B5ns, then all outputs will switch within a 1.B5±0.35ns
window. It is important to recognize that all the devices are
assumed to be operating under the same conditions. If one
part is running fast because of cold temperature and high Vcc,
all the other parts will be running fast as well. The following
data is provided to show that the lOT49FCTB05A does indeed
meet its skew specifications over the commercial operating
range.
Figure 10 shows the range of output skew measurements
for low-to-high and high-to-Iow transitions with Vees of 4.75
and 5.25 volts. For both low-to-high and high-to-Iowtransitions,
WORKING WITH THE DATA SHEET
In the past, designers have used the minimum and maximum limits of a clock driver's propagation delay specifications
to determine skew in their designs. With the I0T74FCT244A
(tPHL min= 1.5ns and tPHL max=4.B ns) the difference between
the two limits results in a3.3nswindow. With the lOT 49FCTB05!
B06, subtracting the minimum from the maximum limit is no
longer necessary because the skew is specified in the data
sheet. However, because the IOT49FCTB05!B06 data sheet
still specifies a 1.5ns minimum for propagation delay there
may be some confusion as to whether or not the skew
specifications are real. In the following discussion it will be
shown that meeting the skew specifications is not a problem
for IOT49FCTB05.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT49FCT805/806
IDT49FCT805A/806A
Com'l.
Com'l.
Symbol
Conditions (1)
Parameter
Min.<2)
Max.
Max.
Unit
1.5
6.5
1.5
5.8
ns
Output Enable Time
OEA to OAn,
OEsto 08n
Output Disable Time
OEA to OAn,
OEsto 08n
1.5
8.0
1.5
8.0
ns
1.5
7.0
1.5
7.0
ns
tSK(O)(3)
Skew between two outputs of
same package (same transition)
-
0.7
-
0.7
ns
tSK(p)(3)
Skew between opposite transitions
(tPHL-tPLH) of same output
Skew between two outputs of
different package at same power
supply voltage and temperature
(same transition)
-
1.0
-
1.0
ns
-
1.5
-
1.5
ns
tPLH
Propagation Delay
CL= 50pF
tPHL
INA to OAn, INs to 08n
RL= 500n
tPZL
tPZH
tPLZ
tPHZ
tSK(T)(3)
NOTES:
1.
2.
3.
Mln.(2)
See test circuit and waveforms.
Minimum limilS are guaranteed but not tested on Propagation Delays
Skew guaranteed across temperature range but measured at maximum temparature only.
Skew parameters apply to propagation delays only.
Table 1. IDT49FCT8051806 Switching Characteristics
76
CLOCK DISTRIBUTION SIMPLIFIED WITH
IDT GUARANTEED SKEW CLOCK DRIVERS
APPLICATION NOTE·82
49FCT805A OUTPUT SKEW VERSUS TEMPERATURE
LOW-TO-HIGH, Vcc= 4.75V
LOW-TO-HIGH, Vcc= 5.25V
0.8
0.8
0.7
tSK(O) SPE
0.7
Output 0.6
Skew
(ns) 0.5
Output 06
Skew
.
(ns) 0.5
0.4
0.4
0.3
tSK(O) SPE
0.3
0
20
40
TEMP (C)
60
80
0
40
TEMP (C)
60
80
HIGH-TO-LOW, Vcc= 5.25V
HIGH-TO-LOW, Vcc= 4.75V
0.8
0.8
tSK(O)
0.7
tSK(O)
0.7
20
Output 06
Skew .
(ns) 0.5
Output 06
Skew .
(ns) 0.5
0.4
0.4
0.3
0.3
0
20
40
TEMP (C)
60
0
80
20
40
TEMP (C)
60
80
2521 drw 10
Figure 10. Measured Output Skew tSK(O) for SeverallDT49FCT805As over the Operating Range
the graphs show that output skew is maximum at hot temperature (70°C). In each case the skew is well below the data sheet
specification of 700ps.
Figure 11 shows the range of pulse skew measurements
with Vees of 4.75 and 5.25 volts. The measured pulse skew
peaks at hot temperature and is slightly greater for a Vee of
4.75V. The measured performance is safely within the data
sheet specification of 1 .Ons.
Figure 12 shows the range of package skew measurements for low-to-high and high-to-Iow transitions with Vees of
4.75 and 5.25 volts. For both low-to-high and high-to-Iow
transitions the skew peaks at hot temperature with minimal
differences between low and high Vee. Again the measured
performance easily meets the data sheet specification of
1.5ns.
49FCT805A PULSE SKEW VERSUS TEMPERATURE
Vcc = 5.25V
1.5.....-------------,
Vcc =4.75V
1.5.....--------------,
Pulse 1.0 - t + - - - - tSK(P) SPEC----~
.................................................:.:...:.:-:..:.:.:.:.:...
Pulse 1.0 - f + - - - - tSK(P) SPEC ----~
Skew
.................................-.. :.:.:.:.:.:~.:.:.'I.•••: .....
••••:
Skew
(ns)
(ns)
0.5
MEAS.SKEW/
:.:~.:.:.:.:-:
0.5
0.0 +--,-..-..--.--.--.--.--.--.--.-~
o
20
40
60
80
TEMP (C)
MEAS.SKEW/
0.0 -!-"-"-'---'-"-'---'-"-'--'-"'--;
60
80
o
20
40
TEMP (C)
2521 drw 11
Figure 11. Measured Pulse Skew tSK(P) for SeverallDT49FCT805As over the Operating Range
77
CLOCK DISTRIBUTION SIMPLIFIED WITH
lOT GUARANTEED SKEW CLOCK DRIVERS
APPLICATION NOTE-82
CLOCK DISTRIBUTION SIMPLIFIED
(1), the skew between the ends of the trace approaches 15ns
(38" X 0.37nS/inch). Given a 20ns cycle time (40 MHz), 14ns
of clock skew implies that 70% of the clock cycle is given to
clock distribution.
A second approach is the clock tree shown in Figure 14. By
adding a level of buffers between the clock source and the 75
loads, the capacitive loading on the buffer outputs is reduced
from 750pF to 50pF and the amount of PCB trace associated
with each driver is reduced to 2.5". If IDT74FCT244As are
used at least three packages (8 drivers per package) will be
required. Since the 244's do not specify skew the designer
might assume that each device output will switch within a
3.3ns window (tPHLmax-tPHLmin= 4.8ns -1.5ns). If the output
transitions at points B, C, and D occur within a 3.3ns window,
then the outputs of the second level (point E) may occur within
a 6.6ns window. Assuming a 20ns cycle time (50Mhz) the
designer has lost 33% of the cycle time to clock distribution
without even considering transmission line effects.
A third approach is to use IDT49FCT805As as shown in
Figure 15. Since each group of six buffers in Figure 14 can be
replaced by 1/2 of an IDT49FCT805, only two devices are
To show how easy it is to design with the IDT49FCT805,
consider a hypothetical clock distribution system. The system
has a 50Mhz clock source and must drive 75 loads. Each load
is a CMOS input connected by 700 micro-strip trace at a
densityof 1 load every 0.5 inches. Assume that all the inputs
are positive edge triggered and the objective is to minimize
skew.
One approach would be to drive all 75 inputs with a single
clock driver output (Figure 13). There are many problems with
this approach. The first problem is the large amount capacitance associated with 75 CMOS inputs. Assuming 10pF
maximum of capacitance per CMOS input, the total capacitive
load is 750pF. A standard clock driver such as the
IDT74FCT244A has .itPLH of 2ns/1 OOpF for loads above 50pF.
If the IDT74FCT244A is used the capacitance alone adds up
to 14ns of additional propagation delay. If 75 loads are
distributed along a single trace, the trace length is 38 inches
(75 X 0.5 inputs/inch). If the PCB trace has an intrinsic delay
of 0.15ns/inch (1), the delay from point B to point C is 5.7ns
(38" X 0.15 nS/inch). Using a loaded trace delay ofO.37ns/inch
49FCT805A PACKAGE (PART-TO-PART) SKEW
VERSUS TEMPERATURE
Vcc= 5.25V
2.0....._-------------.
VCC= 4.75V
2.0....._-------------.
1.5 " M - - - - - tSK(T) SPEC----~
1.5-k---- tSK(T) SPEC----~
Package
Skew 1.0
(ns)
Package
Skew 1.0~
(ns)
0.5
0.0 +-_._.-r~---.-_r_.....__._r__r__.___.___1
o
20
40
60
80
TEMP (C)
."...-...:-:-:.:-.~:.:.:.:.:::~::::.::::::....;.;.::.::. ::::::::.;~::~::~::::.::::~:=:;::~:::;~:::::
····~·EAS. SKEW/
o
20
40
TEMP (C)
60
80
2521 drw 12
Figure 12. Measured Output Skew tSK(T) for SeverallDT49FCT805As over the Operating Range
CLOCK DISTRIBUTION SYSTEM FOR 75 LOADS
- SINGLE DRIVER CONFIGURATION-
..
40" OF 70n MICRO-STRIP TRACE
CLOCK
SOURCE
2521 drw 13
Figure 13. Single Driver Clock Distribution System
78
CLOCK DISTRIBUTION SIMPLIFIED WITH
lOT GUARANTEED SKEW CLOCK DRIVERS
APPLICATION NOTE-82
CLOCK DISTRIBUTION SYSTEM FOR 75 LOADS
"CLOCK DRIVER TREE CONFIGURATION"
CLOCK
SOURCE
rvl-----1H
I
®
2521 drw 14
Figure 14. Clock Tree Distribution System Using 244'5
79
CLOCK DISTRIBUTION SIMPLIFIED WITH
IDT GUARANTEED SKEW CLOCK DRIVERS
APPLICATION NOTE-S2
CLOCK DISTRIBUTION SYSTEM FOR 75 LOADS
- CLOCK DRIVER TREE CONFIGURATION -
2.5" OF 700. MICRO-STRIP TRACE
CLOCK
SOURCE
rv
2521 drw 15
Figure 15. Clock Tree Distribution System Using IDT49FCTS05's
so
CLOCK DISTRIBUTION SIMPLIFIED WITH
IDT GUARANTEED SKEW CLOCK DRIVERS
APPLICATION NOTE-82
required to implement the design. Using the 1.Sns package
skew specification reduces the 6.6ns skew window to a 1.5ns
skew window. If 0.92Sns of loaded trace delay (2.5" X 0.37 nsf
inch) is considered the maximum skew is 2.425ns including a
1st order treatment of transmission line effects. For a 20ns
cycle time, the penalty imposed by the clock distribution
system is reduced to 12% of the cycle time including transmission line effects. Besides reducing the size of the skewwindow
of the second approach by 77%, the IDT49FCT805 increases
the level of integration associated with the clock distribution
tree. A significant benefit is the reduced loading on previous
stages. Reduced loading helps minimize skew and makes the
termination of clock lines clean and simple. The reduced chip
count also saves valuable board space and simplifies the
layout of the board.
RECOMMENDATIONS
To realize the performance benefits offered by the
lOT 49FCT80S/806 clock drivers, lOT recommends the following high speed design practices:
• Use low impedance power and ground planes.
• Keep loading balanced and light.
• Keep trace lengths short, avoiding sharp bends and
discontinuities (eg. use two 45° bends vs one 90° bend).
• Decouple both Vec pins with a combination of capacitors
(0.1IlF and 0.011lF or 0.005IlF) for effective high frequency
filtering.
• Use termination for signal lines longer than 3 inches.
• Only use parts of same speed grade (non-A or A speed).
CONCLUSIONS
SUMMARY
Clock skew is an important design consideration in today's
high-speed systems. For successful and reliable operation,
the clock skew must be kept within an acceptably small
fraction of the system clock period. The IDT49FCT80S and
IDT49FCT806 simplify the design of minimum skew clock
distribution networks by specifying guaranteed low-skew
performance. The skew specifications allow system designers to control the clock skew at each stage of the design which
simplifies the problem of meeting global system requirements.
With the IDT49FCT80S/806 clock driver and a design methodologythat pays close attention to high-speed design issues,
maximum system performance can be achieved without risking
reliability.
The following features of the IDT49FCT805/806 address
clock driver skew and clock distribution problems:
• Circuit design, chip layout, and pin configuration specifically designed for very low output, pulse and package
skew.
• Independent power and ground pins for reduced ground
bounce and dynamic threshold shift.
• High current drive capability for driving heavily loaded/
terminated PCB traces.
• 1:5 input/output ratio for reduced loading on previous
stages.
• 11 outputs reduce the need for additional drivers-saves
board space and simplifies PCB layout.
• Multiple grounds and Vecs to minimize ground bounce
effects on propagation delay and skew.
• Input Hysteresis for increased immunity to system noise.
• Available in SOICs for increased packing density and
reduced lead inductance.
REFERENCES
(1) "Application Note AN-49", High-Speed CMOS Logic
Design Guide, Integrated Device Technology Corp., November 1989.
81
~
~
Integrated Device Technology. Inc.
DESIGNING WITH THE
IDT49C460 AND IDT39C60
ERROR DETECTION AND
CORRECTION UNITS
APPLICATION
NOTE
AN-24
By Roben Stodleck
INTRODUCTION
buffers to be a latched type such as an lOT? 4FCT646 instead
ofthe IDT?4FCT245shown. A family of waveforms appropriate
for the bus format shown in Figure 1 is shown in Figure 2. The
waveform diagrams do not include precise timing considerations which are left to the designer.
In any given system. any of the buffers separating the EDC
from the memory IC's may be eliminated if bus capacitance
and speed considerations allow.
The Error Detection and Correction (EDC) chip itself is one
element of an EDC system. How it is connected to the
surrounding system and controlled is left to the system designer.
~ecause there are so many design variations possible, it is
Important for the designer to develop a clear idea of the target
design before beginning the design process. Basic design
ap~roaches and perturbations are enumerated in this application note.
The details of the EDC control logic depend on the configuration of the EDC system, EDC bus topology, the nature
ofthe CPU orsystem bus involved, and the nature of diagnostic
hardware used. The data bus topology is highly dependent on
the individual target system.
This application note approaches the bus topology issue first.
The advantages and disadvantages of using EDC word widths
that are different from the system bus are discussed. The next
topic to be covered is the use of E DC in a system with a cache.
Then the operational configuration of the EDC system is
discussed. This implies answering questions about how the
EDC unit handles errors in a particular system is discussed.
How an operating system deals with the EDC function is
discussed, fOllowed by a practical discussion of some non
obvious hardware topics. The final topic is memory system
diagnostics and verification. An appendix includes tables and
software that are useful in debugging and in writing diagnostic
software for an EDC board.
EDC Bus Width vs. System Bus Width
Thewidth of the EDC bus and the System Bus are normally
matched. However, there are valid reasons for making the
EDC bus both wider or narrower than the system bus.
Wide EDC words are significantly more efficient than
narrower EDC word widths in terms of the amount of checkbit memory used for a given amount of data memory. The
amount of check-bit memory required for 64 data bits is 8 bits
if the 64 data bits are organized as one word and 14 bits if it
is handles as two 32-bit words. Twenty-four bits of check-bit
memory would be required for 64 data bits organized as four
16-bit EDC data words.
For the purposes of speed, it would be ideal to have 8-bit
EDC words for systems that do byte write operations. This
woul? make it unn~~essary to ever have to read a memory
locatIOn before writing a partial word on these systems.
Unfortunately, eight-bit EDC words are grossly inefficient in
terms of check-bit memory usage. Therefore, The EDC word
widths are normally 16-bits or more.
Since the EDC word widths must generally be 16-bits or
more for check-bit memory efficiency, and since generalpurpose computers generally use byte or partial-word-write
operations, general-purpose computers force the EDC unit to
be able to process partial EDC word-width write operations.
Partial word-width write operations require the E DC subsystem
to execute a read-modify-write type memory cycle. Thus, the
EDC controller must take over control of the memory system
and execute a read before completing a partial word write. For
some applications, where EDC is in use, it may be desirable
to speed up processing by prohibiting partial word operations
either at the hardware level or software level. Speed critical
sections of code should be executed without partial-wordwrite
operations.
The read-modify-write EDC cycle executed during a partial-word write is identical to the EDC correction cycle executed
during a read cycle when an error has occurred. The readmodify-write EDC cycle should not be confused with the readmodify write cycle executed by some CPU's.
Verification of a memory system using an E DC word wider
than the system word is complicated by the fact that all
me~ory write ~ycles become read-modify-write cycles (Le.
partlal-word-wrlte EDC cycles). Careful consideration of
diagnostic procedures needs to be made during the design to
avoid unnecessarily complex debugging procedures.
Data Bus Topology
Most contemporary CPUs execute write operations of a
byte or other sub-word width types. These cause special
problems for all EDC units since EDC transactions with the
memory are carried out on whole width EDC words. To
facilitate partial word write operations with the IDT39C60 or
IDT49C460 type E DC u nits, a set of tri-state transceivers are
normally required between the system bus and the EDC unit.
These buffers are required to prevent bus contention between
the CPU or system bus drivers and the EDC units data outputs
during partial word write operations. Figure 3 shows a bus
arrangement appropriate for large DRAM arrays. The need
for isolation of the EDC data bus and the system bus is shown
by examining the data paths, shown with white arrows. These
are used by the final write operation of a partial-word write
cycle. In this case, only data bits 0-7 are being written from
the processor to memory. If the processor or system bus
drivers can be tri-stated on byte boundaries then this set of
buffers could be removed, but this is not a common Situation.
Depending on the memory size, additional buffering may
be required between the EDC and the memory bus proper.
The buffer configuration must be determined before beginning
the EDC and memory controller deSign.
An appropriate general purpose bus topology is shown in
Figure 1. It is common for one or the other sets ofbi-directional
1/93
©1993 Integrated Device Technology, Inc.
82
DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECT10N AND CORRECTION UNITS
rr.;;8
CPU
ct
f-
APPLlCAT10N NOTE AN-24
Ll)
-
-
-
-
""
DIAG MODEo, 1 = 00
LEOIAG = X
CODE IDa, 1 = 00
2917 drw 10
Figure 7. Memory correct and check-bit regenerate. Identical for the second phase of a read operation in which an error has occurred, and
for a partial-word-write operation except for the state of the individual byte output enables.
91
DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS
ERROR
DECIMAL
SYNDROME
HEX
0
53 52
0
0
51
0
APPLICATION NOTE AN-24
HEX
0
1
2
3
4
5
6
7
56
55
54
50
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
NE
C4
C5
T
T
30
16
32
48
C6
64
T
0
80
96
112
DECI I.1AL EQUIVALENT»
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CO
T
T
14
T
M
M
T
1
17
33
49
65
81
97
113
C1
T
T
M
T
2
24
T
2
18
34
50
66
82
98
114
T
18
8
T
M
T
T
M
3
19
35
51
67
83
99
115
C2
T
T
15
T
3
25
T
4
20
36
52
68
84
100
116
T
19
9
T
M
T
T
31
5
21
37
53
69
85
101
117
T
20
10
T
M
T
T
M
6
22
38
70
86
102
118
T
4
26
T
71
87
103
119
M
T
T
54
M
7
23
39
55
C3
T
T
M
T
5
27
T
8
24
40
56
72
88
104
120
T
21
11
T
M
T
T
M
9
25
41
57
73
89
105
121
T
22
12
T
1
T
T
M
10
26
42
58
74
90
106
122
17
T
T
M
T
6
28
T
11
27
43
59
75
91
107
123
T
23
13
T
M
T
T
M
12
28
44
60
76
92
108
124
M
T
T
M
T
7
29
T
13
29
45
61
77
93
109
125
16
T
T
M
T
M
M
T
14
30
46
62
78
94
110
126
M
M
T
T
15
31
47
63
T = Two errors
NE= NO ERROR
Cn = check-bit error bit n
M = Multiple errors
n = data-bit error bit n
n = decimal equivalent of the syndrome
0
T
T
M
79
95
111
127
2917tbi01
Table 1. 32-blt Syndrome Tables with Hex, Binary and Decimal Equivalents.
92
DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS
ERROR
HEX
0
1
2
3
4
5
HEX
57
56
55
54
53 52 51 50
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
0
0
0
0
0
T
0
3
C2
4
T
5
6
0
1
1
0
T
6
7
8
9
0
1
1
1
0
0
1
0
0
1
0
1
C
1
1
0
1
1
0
E
F
1
1
1
1
1
1
0
1
1
5
0
1
0
1
C4
16
C5
32
T
T
17
33
T
48
14
49
C6
64
B
1
0
1
0
1
0
1
1
C
1
1
0
0
D
1
1
0
1
M
M
T
M
T
161
40
162
177
193
209
M
T
66
T
M
51
15
52
67
T
68
T
83
35
84
T
210
2
211
T
M
M
T
T
M
T
99
57
100
115
131
147
51
148
163
41
164
179
195
T
T
116
63
117
132
T
T
54
M
T
T
M
M
T
T
M
T
70
86
102
58
103
59
104
118
134
150
52
151
53
152
166
42
167
43
168
182
198
M
T
56
72
T
165
T
212
3
213
4
214
101
T
T
149
M
196
T
40
11
41
12
42
M
133
T
180
47
181
85
T
T
T
119
135
T
T
120
136
T
197
E
1
1
1
0
F
1
1
1
1
T
T
M
215
231
247
T
M
T
M
T
184
200
216
5
217
6
218
T
T
M
M
T
T
M
T
89
105
121
137
49
138
153
169
185
201
T
T
M
T
11
27
23
28
43
13
44
59
75
T
T
M
106
60
107
122
T
T
123
139
T
T
M
T
154
54
155
170
186
202
1
203
44
T
171
187
T
M
T
T
M
M
T
T
M
T
60
76
108
61
109
124
140
156
55
157
172
45
173
188
204
T
77
T
92
39
93
1
M
T
T
M
29
45
61
0
13
16
14
T
T
M
30
46
62
T
63
78
32
79
T
T
125
141
T
219
7
220
T
M
T
189
205
0
206
221
M
M
T
T
M
M
T
94
110
126
142
158
174
190
T
222
T
T
M
48
T
T
M
T
M
95
111
127
143
159
175
191
207
223
NE = NO ERROR
T = Two errors
Cn = check-bit error bit n
M = Multiple errors
n = data-bit error bit n
n = decimal equivalent of the syndrome
M
M
M
90
38
91
T
226 242
24
T
227 243
31
T
228 244
25
T
229 245
26
T
230 246
199
73
33
74
T
T
T
T
58
M
224 240
30
T
225 241
183
57
17
M
M
194
M
24
21
25
22
26
47
T
178
69
0
M
T
130
T
87
37
88
31
T
114
53
36
T
M
208
145
50
146
50
15
T
192
T
T
T
46
176
129
71
T
T
160
T
M
T
T
144
113
T
T
C7
128
M
34
8
35
36
9
37
10
38
62
112
97
56
98
55
1
A
M
T
0
9
1
0
0
1
81
34
82
39
1
8
1
0
0
0
T
T
T
T
96
T
0
7
0
1
1
1
65
18
18
19
20
19
21
20
22
T
23
1
6
0
1
1
0
80
7
C3
8
12
D
4
0
1
0
0
M
10
B
3
0
0
1
1
1
9
A
2
0
0
1
0
--===-==--=-=-===-=-=====--------=-=-=-----=---=-=-=-=-----=-=--------------NE
0
CO
1
C1
2
1
1
1
0
0
0
1
APPLICATION NOTE AN-24
232 248
27
T
233 249
28
T
234 250
T
M
235 251
29
T
236 252
M
T
237 253
M
T
238 254
M
T
239 255
2917 tbl 02
Table 2. 64-bit Syndrome Tables with Hex, Binary and Decimal Equivalents.
93
DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECnON AND CORRECTION UNITS
APPLICATION NOTE AN-24
CB
DATA
CB
DATA
CB
DATA
CB
DATA
0
1
2
3
4
5
6
7
8
9
A
8
C
0
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
28
1000F
1000
27
1000C
2B
24
10003
10024
3
C
10028
0
10027
10028
F
10022
5
A
10020
6
10021
1002E
9
2E
10009
10006
21
1000A
20
22
10005
20
21
22
23
24
25
26
27
28
29
127
10100
1010F
128
10103
124
12B
1010C
1012B
10C
103
10124
10F
10128
10127
100
10120
10A
105
10122
109
1012E
10121
106
121
10106
10109
12E
10105
122
12D
1010A
40
41
42
43
44
45
46
47
48
49
4A
48
4C
40
4E
4F
50
51
52
E
10029
10026
60
61
62
63
1002A
D
2
10025
1002
25
64
101
10126
10129
10E
10125
102
10D
1012A
10100
12A
125
10102
129
1010E
10101
126
10108
12C
123
10104
12F
10108
10107
120
107
10120
1012F
108
10123
104
108
1012C
2A
2B
2C
20
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
53
54
55
56
57
58
59
5A
58
5C
50
5E
5F
2A
10000
26
10001
1000E
29
10004
23
2C
10008
20
10007
10008
2F
8
1002F
10020
7
1002C
8
4
10023
65
66
67
68
69
6A
68
6C
60
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
78
7C
70
7E
7F
2917tbl03
Table 3. Minimal 32-check·bit to data tables tor diagnostic use. One data value is listed
to generate every possible check·bit pattern.
94
-- ....- - - - - - DESIGNING WITH THE IDT49C460 AND IDT39C60
ERROR DETECTION AND CORRECTION UNITS
DATA
0
1
2
3
4
5
6
7
8
9
A
8
C
D
E
F
20
21
22
23
24
25
26
27
28
29
2A
28
2C
2D
2E
2F
CB
C
43
46
9
5E
11
14
58
58
17
12
5D
A
45
40
F
54
18
1E
51
6
49
4C
3
0
4F
4A
5
52
10
18
57
APPLICATION NOTE AN-24
DATA
100
101
102
103
104
105
106
107
108
109
10A
108
10C
10D
10E
10F
120
121
122
123
124
125
126
127
128
129
12A
128
12C
12D
12E
12F
DATA
10000
10001
10002
10003
10004
10005
10006
10007
10008
10009
1000A
10008
1000C
1000D
1000E
1000F
10020
10021
10022
10023
10024
10025
10026
10027
10028
10029
1002A
10028
1002C
1002D
1002E
1002F
CB
2F
60
65
2A
7D
32
37
78
78
34
31
7E
29
66
63
2C
77
38
3D
72
25
6A
6F
20
23
6C
69
26
71
3E
38
74
CB
2
4D
48
7
50
1F
1A
55
56
19
1C
53
4
48
E
1
5A
15
10
5F
8
47
42
D
E
41
44
8
5C
13
16
59
DATA
10100
10101
10102
10103
10104
10105
10106
10107
10108
10109
1010A
10108
1010C
1010D
1010E
1010F
10120
10121
10122
10123
10124
10125
10126
10127
10128
10129
1012A
10128
1012C
1012D
1012E
1012F
CB
21
6E
68
24
73
3C
39
76
75
3A
3F
70
27
68
6D
1F
79
36
33
7C
28
64
61
2E
2D
62
67
28
7F
30
35
7A
2917tbl04
Table 4. Minimal 32-bit data to check-bit tables for diagnostic use. At least one data
value Is listed for every possible check-bit pattern. This table is identical to Table 3
except in sequence of presentation.
95
~
~
PROTECTING YOUR DATA
WITH THE IDT49C465
32-BIT Flow-thruEDCTM UNIT
APPLICATION
NOTE
AN-64
Integrated Devlc:e Tec:hnology, Inc:.
by Tao Lin, Gerard Lyons and Frank Schapfel
INTRODUCTION
high-density dynamic RAMs, typically with access times of
100 nanoseconds or more, but with four times the density of
static RAMs. So, when the state-of-the-art static RAMs are 1
Megabit large, the newest density dynamic RAM is 4 Megabits.
Therefore, dynamic RAMs will always provide the most
cost-effective implementation for system memory.
Dynamic RAMs, though, are very prone to externally
induced errors. These externally induced errors are called soft
errors, since they do not cause permanent damage to the
memory cell. Soft errors can be induced by system noise,
alpha particle and power supply surges, and will cause random
data bits to be flipped from "1" to "0", or vice versa. Although
these soft error occurrences may be rare and inconsequential
when using small amounts of DRAMs, large DRAM arrays are
much more error prone. Also, as seen in Figure 1, larger
DRAM components are much more susceptible to soft errors
by virtue of their smaller memory cell size. Hardware errors
may also occur on system memory boards. These hard errors
occur if one RAM component or RAM cell fails and is stuck at
"0" or stuck at "1 n. Although less frequent, hard errors may
cause a complete system shut down.
A TIME FOR ERROR-FREE MEMORIES
With the advent of high-performance 32-bit RISC and
CISC microprocessors, general purpose computing across a
wide spectrum of applications software is now easily
accessible on a desktop. We can now draw on computer
resources which are very sophisticated, multi-task systems
with distributed processing power, and we no longer must rely
on the centralized mini-computers and mainframes for
processing horsepower. Both the technical and the commercial
computing environments demand the insatiable hunger for
processing power.
This increasing demand for sophisticated applications
software requires more system memory on a local level.
Tightly coupled microprocessors and cache memory are
designed for optimized processing throughput, but the cache
memory is no substitute for system memory. Cache memory
is typically composed of very high-speed static RAMs, with
access times of 35 nanoseconds or less. System or main
memory is almost always comprised of slower but very
Typical
Error
Rate
% Per
1,000 Hours
•
SOFT ERRORS DUE TO ALPHA PARTICLES ONLY
o
HARD ERRORS
0.1
0.01
0.001
0.0001
Density Bits/Chip
Figure 1. Typical Error Rates
The lOT logo is a registered trademark and F'ow~thruEDC is a trademark of Integrated Device Technology, Inc.
©1993 Integrated Device Technology, Inc.
96
"'"II
~~
coPROCESSOR
Data
14
I~~
~:::!
~I
.lo~
:r
~<
Co
me:
0:0
Data 1..-
~
I
~O
'--(,
e:~
ii!:l>
-I::E
::::j
Buffer
1
CPU
::J:
-I
::J:
m
Address
Tag
is
I
I
I
Write
Buffer
....
U)
I
~I
I-Cache
&
D-Cache
r- I L,J
I
Write I
Buffer
I
Data
Main
Memory
i!
U)
Address
~
'"
~11111!rl~-~1'llll'!lil
1!'!I!;I:!I ~;I !:rl:l il'l !i lfi"Jil~l!il -
~Data
Check Bit
Memory
Address
~I
DRAM
Controller
l>
Timing
Control
Logic
~
C
Crystal
Oscillator
Figure 2. A Typical Architecture of High-performance RiSe or else Systems
~
z
~
iii
~
PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruE[)CTM UNIT
APPLICAnON NOTE AN-64
ERROR CORRECTION TO THE RESCUE
The operation of an EDC device can be generally split
into:(1) generation of a coded word based on the data-word
being written to memory. This coded word is called The CheckBit Word. This operation is called Generate; (2) detection of
errors in a data-word read from memory by comparing the
corresponding check-bit word read from memory and a newly
generated check-bit word (based on the data-word read from
memory) and if possible correcting this error. The comparison
of these two check-bit words (an exclusive-or (XOR) function)
produces the so-called Syndrome Word. This operation is
called Detect/Correct.
The coding scheme employed in lOT's EDC devices is a
modified Hamming Code. For each data-word written to
memory, a coded pattern, or check-bit word, is appended to
the date-word. The new word (the data-word plus the checkbit word) can be termed a valid code. The modified Hamming
Code establishes a Distance-of-4 between one valid code
and another. This means that to go from one valid code to
another, 4-bits have to change. It can be shown that a
Distance-of-4 code enables you to detect all Single and
Double-Bit errors and correct all Single-Bit errors.
To implement a Distance-of-4 code on a 32-bit data-word,
a 7-bit check-bit word must be appended. For a 64-bit word,
a 8-bit check-bit word must be appended. The Hamming
Code algorithm to generate a check-bit word from a 32-bit
data-word or a 64-bit data-word can be found in either
IDT49C460 data sheet or IDT49C465 data sheet.
A scheme exists that not only is able to detect soft and hard
errors, but is capable of correcting the erroneous bits. This
scheme is implemented by a family of error detection and
correction chips from Integrated Device Technology. Using a
modified Hamming code, developed at AT&T Bell Labs, all
single-bit errors may be detected and corrected, while all
two-bit and mostthree-bit errors can be detected.IDT pioneered
EDC chips, using CMOS technology in 1986, after recognizing
the importance of large DRAM memory arrays in distributed
computing.
TYPICAL ARCHITECTURE OF
HIGH-PERFORMANCE RISC/CISC SYSTEMS
Figure 2 shows a typical architecture of high-performance
RISC or CISC systems which have the following features: (1)
high-speed cache memory (separate or common, Instructioncache and Data-cache) for fast access to frequently used
instructions and data, (2) write and read buffers to handle the
mismatch between the high-speed CPU and the slow-speed
main memory and (3) high-speed flow-thru EDC unit to insure
data integrity.
While most high-performance computer systems in current market have the first and second features, the third
feature is becoming more attractive and important when the
main memory space grows and the memory word-length
increases. Certainly, using an EDC unit is an effective way to
improve the system reliability.
EDC ARCHITECTURES AND WORD-LENGTH
There are two basic architectures for EDC operation: flowthru and bus-watch. IDT provides a full line of EDC devices to
support 16-bit and 32-bit bus-watch architectures and 32-bit
and 64-bit flow-thru architectures, as shown in Table 1.
GENERAL EDC OPERATION
The basic function of an EDC device is to check the
integrity of data being read from a memory system, flag an
error if one has been detected and if possible correct that
error. The IDT family of EDC devices implements this function
using the same general principles, with some variations from
device to device.
Part Number
Architecture
Word-length
Comment
IDT39C60
Bus-watch
16-bit
Cascadable up to 64·bit
using 4 devices
IDT49C460
Bus-watch
32-bit
Cascadable up to 64-bit
using 2 devices
IDT49C465
Flow·thru
32-bit
Cascadable up to 64-bit
using 2 devices
IDT49C466
Flow-thru
64-bit
Table 1.IDT EDC Product Line
98
PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDCTM UNIT
APPLICATION NOTE AN-64
------------------------------~
WRITE (GENERATE)
READ (DETECT and CORRECT)
Main
Memory
Main
Memory
CPU
DRAM
DRAM
, Error
IDT49C460
Check
Bit
Check
Bit
DRAM
DRAM
EDC
L ______________________________ ,
-------------------------------
,,
(a) Common 1/0 Memory System
,------------------------------,,
WRITE (GENERATE)
READ (DETECT and CORRECT)
-
r--
•
CD
CPU
;t'\r
>
.~
JL
~
I-
"-
'L~'
.~
CPU
")I
'§
"-
CD
.....
CD
DRAM
~ to
-
Main
Memory
~ -'~"
...
c
~
~
L--
r
~i--,111''-
Main
Memory
DRAM
j
Error
Data "
-
Error
;..
IDT49C4'e
"EDC
"I
Data
...
SC
CB
...
'"
IDT49C460
Check
Bit
'---
EDC
"-
tsc
'"
\..
DRAM
CB
"
Check
Bit
.....
DRAM
1- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
(b) Separate 1/0 Memory System
Figure 3. Basic Configurations Using a Bus-watch EDC Architecture
99
PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow·thruE[)CTM UNIT
APPLICATION NOTE AN-64
WRITE (GENERATE)
READ (DETECT and CORRECT)
Main
CPU
Main
1/1----''' Memory
1/'--.....1'''-1 Memory
CPU
DRAM
DRAM
Error
Error
Check
Bit
Check
Bit
DRAM
DRAM
(a) Common 1/0 Memory System
READ (DETECT and CORRECT)
WRITE (GENERATE)
Main
Memory
Main
Memory
DRAM
DRAM
Error
Error
Check
Bit
Check
Bit
DRAM
DRAM
(b) Separate 1/0 Memory System
Figure 4. Basic Configurations Using a Flow·thru EDC Architecture
100
PROTECTING YOUR DATA WITH THE IDT49C465
32·BIT Flow·thruEDCTM UNIT
APPLICATION NOTE AN·64
System Data Bus
32- It
64·bit
Memory Data Bus
32- It
SD
SD
IDT49C465
Upper
32·bit
32·blt
8-bit Partial Checkblt
(Generate Only)
CBO
Check
Bit In
CODE ID
SYO
=10
8-blt
MD
IDT49C465
Lower
CBI
PCBI
Check
Bit Out
CODE ID
= 11
CBI
SYO
PCBI
IERR
IMERR
CBO
8- it
(a) Cascading Flow·thru EDC IDT49C465
Data
Bus
(
32-bit
64-bit
I~
~
~
----...s-lI
Data
IDT49C460
Upper
IDT49C460
Lower
8-bit
""
>
/~
...
~
.,
CODE ID
=10
CB
~
32·bit
32·blt
Check
Bit In
~/E RR
Data
.1..
8-bit
SC
.,
CB
3-State
Buffer
0-01
(b) Cascading Bus-watch EDC IDT49C460
Figure 5. 64-bit Configurations by Cascading Two 32·bit EDC Units
101
Check
Bit Out
CODE ID
= 11
SC t--
.
rv
PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDcm UNIT
APPLICATION NOTE AN-64
BUS-WATCH ARCHITECTURE
A bus-watch EDC such as the IDT49C460 has a single
data bus. The basic configurations, using the IDT49C460 for
common lID memory and separate lID memory, are illustrated
in Figure 3.
During a write (store) operation, the CPU sends data to the
main memory. At the same time the data goes to the EDC unit,
which then generates the check bits and stores them in the
check-bit memory.
On the other hand, during a read (load) operation, the data
from the main memory and the check bits from the check-bit
memory first go to the EDC unit. Based on the information
carried by the check bits, the EDC unit can detect all single-bit
and some multiple-bit errors, and correct all single-bit errors.
The corrected data is then sent to the CPU.
FLOW-THRU ARCHITECTURE
In contrast to a bus-watch EDC, a flow-thru EDC such as
the IDT49C465 provides two data buses: a system data (SD)
bus and a memory data (MD) bus. The dual-bus architecture
improves the throughput of the EDC operation and simplifies
the interface between the CPU system bus and the memory
bus. The basic configurations using the IDT49C465 for common
lID memory and separate lID memory are illustrated in
Figure 4.
In the common lID configuration, during a write (store)
operation, the data from CPU flows through the EDC unit and
is written to the main memory. When the data flows through
the EDC, the check bits are generated and stored into the
check-bit memory. During a read (load) operation, the data
from the main memory enters the EDC unit through the MD
bus while the check bits enter the EDC unit through the CSI
bus. The EDC unit then detects any errors and loads the
corrected data to the CPU through the SD bus.
In the separate lID configuration, during a write (store)
operation, the data from CPU are directly sent to the main
memory. At the same time, the data is sent to the EDC unit
through the SD bus. The EDC unit then generates the check
bits and stores them into the check-bit memory. During a read
(load) operation, the data from the main memory enters the
EDC unit through the MD bus while the check bits enter the
EDC unit through the CBI bus. The EDC unit then detects any
errors and loads the corrected data to the CPU through the
SD bus.
......._ _ _ _• • = 32-bit wide Busses
Syst.
Mux
Byte
Irr==t===~rliii~~
L..JL-"''------'
=rnI==L..--4K::J
~
!\mE
MDO-31
MLE
L-----.....
~~~SYOO_7
ERROR
MERR
SYNCLK
~,]!,)S'
CBO O_7
C8OE"
>------------==:t11-11lliJltlRJill••----tstt:.::::J PCBI0_7
SCLKENr-~------------------------~
CLEAR
CB1 0 _7
CODE ID 1,0
MODE 2-0
Figure 6. Block Diagram of IDT49C465
102
PROTECTING YOUR DATA WITH THE IDT49C465
32·BIT Flow·thruEI)C1'M UNIT
APPLICATION NOTE AN·64
CASCADING 32·BIT EDC DEVICES FOR 64·BIT
MEMORY SYSTEMS
As mentioned in the previous section, for a 32-bit data
word, 7 check bits are necessary, while for a 64-bit data word,
check bits are needed. Although the IDT49C460 and the
IDT49C465 are both 32-bit EDC units, they have an 8·bit
output·bus for output of generated check-bits to memory and
an 8·bit input bus to read back check-bit from memory. In this
way, they can be cascaded to support 64-bit applications. In
the 32-bit mode, only 7 bits of the check-bit input and output
buses are used, while in the 64-bit mode, all a bits are used.
Figure 5 shows how two I DT 49C465s (or two IDT 49C460s)
can be cascaded to build a complete 64-bit EDC unit. In the
cascaded 64-bit mode, the EDC operation can be broken into
two stages; a lower 32·bit stage and an upper 32·bit stage.
For the IDT49C465 (see Figure 5a), a general description
of the EDC operation is discussed below.
1. Generation starts by generating a Partially Generated
Check·bit Word in the lower slice, based on the lower
32-bit of the 64-bit data-word, and sending this to the
upper slice. The upper slice combines the Partially
Generated Check-bit word from the lower slice, with its
generated check-bit word (based on the upper 32-bit of
the 64-bit data-word), to form a final check-bit word. Thus,
the source of check-bit in a cascaded system is the
upper-slice device.
2. Detection/Correction starts in the lower·slice where the
check-bits from memory are input, as well as the lower
32-bit of the 64-bit data-word. Here the inputted checkbits are compared with the newly generated check-bits
(based on the lower 32-bit of DATA-word) using an XOR
function to produce a Partial Syndrome Word, which is
passed onto the upper-slice device. At the same time, in
the upper slice the upper 32-bits of 64-bit data-word is
used to generated a so-called Partial Check·Bit Word
which is sent to the lower slice. So now we have in both
the upper and lower slice devices almost simultaneously
two pieces of data; the Partial Syndrome Word (generated in the lower-slice) and the Partial Check·Bit Word
(generated in the upper-slice). In each slice these two
pieces of data are XOR'd to produce a Final Syndrome
Word which is used to detect and correct errors on the
64-bit data word.
a
The IDT49C460 carries out Detect!Correct slightly differently (see Figure 5b), namely, the Partial Syndrome generated in the lower-slice is sent to the upper slice, then the Final
Syndrome is generated in the upper-slice and this FinalSyndrome is now fed back to the lower-slice. Thus Detect!
Correct in the IDT49C460 employs a serial approach, whereas
the IDT49C465 uses a faster paralleled approach. Moreover,
in the IDT49C460 case, an additional tri-state buffer such as
the IDT74FCT244 is needed while in the IDT49C465 case, no
additional external logic is needed.
OVERVIEW OF THE IDT49C465
ARCHITECTURE
The IDT49C465 architecture is an evolutionary development on the IDT49C460 EDC device. The IDT49C460 is a
single-bus 32-bit EDC cascadable to 64-bits. The IDT 49C465
draws on this basic architecture to provide a dual-bus or
flow-Thru 32-bit EDC cascadable to 64-bits. Figure 6 shows
a block diagram of the IOT49C465; the key difference
between the lOT 49C460 and the lOT49C465 is the presence
of a second 32-bit DATA bus to provide the flow-thru path for
data through the device.
DATA BUSES
The System Data Bus, or SO Bus, is a 32-bit bi-directional
bus. Data is written to the EDC using this bus for Check·Bit
Generation, so that when a data-word is written to memory
the corresponding check-bits are written simultaneously. Also
when a data-word read from memory is corrected, the corrected data-word is read from the SO Bus by the system
processor. The SD Bus has associated with parity-checking
and generation and also separate byte enables on the SD Bus'
output buffers so that Partial Byte operations can be supported.
The Memory Data Bus, or MD Bus, is a 32-bit bi-directional
bus. Data written from the system processor through the SD
Bus can be written to memory using this bus. When the
processor is reading a word from memory, the data word is
read in through the MO Bus and the corrected data word
(depending on the status of the data) is sent to the processor
through the SO Bus.
103
PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDC"" UNIT
APPLICATION NOTE AN-64
EXPANSION BUSES
The IDT49C465 has four a-bit buses that are an integral
part in the Detect/Correct path for both a 32-bit EDC system
and a 64-bit EDC system.
CBI(7:0)
1. When the IDT49C465 is operating as a 32-bit EDC
system or is the lower 32-bit slice in a 64-bit E DC system,
this a-bit bus is the input port for Check-Bits read from
Memory.
2. When the IDT49C465 is operating as the upper 32-bit
slice in a 64-bit EDC system, this bus is the input port for
partial Syndromes from the lower slice.
PCBI(7:0)
1. When the IDT49C465 is operating as a 32-bit EDC
system, this bus is unused.
2. When the lOT 49C465 is operating as the lower 32-bit slice
in a 64-bit EDC system, this a-bit bus is the input port for
Partial Check-Bits read from the upper slice.
3. When the IDT49C465 is operating as the upper 32-bit
slice in a 64-bit EDC system, this bus is the input port for
Partially Generated Check-Bits from the lower slice.
CBO(7:0)
1. When the IDT49C465 is operating as a 32-bit EDC
system or is the upper 32-bitslice in a 64-bit EDCsystem,
this a-bit bus is the output port for Check-Bits being written
to Memory
2. When the lOT 49C465 is operating as the lower 32-bit slice
in a 64-bit EDC system, this bus is the output port for
Partially Generated Check-bits being sent to the upper
slice.
SYO(7:0)
1. When the IDT49C465 is operating as a 32-bit EDC
system, this a-bit bus outputs the Final Syndrome word
associated with the Detect/Correct logic.
2. When the lOT49C465 is operating as the lower 32-bit slice
in a 64-bit EDC system, this bus is the output port for
Partial Syndrome word being sent to the upper slice.
3. When the IDT49C465 is operating as the upper 32-bit
slice in a 64-bit EDC system, this bus is the output port for
Partial Check-bit word being sent to the lower slice.
Operating Modes
The IDT49C465 has 3 mode control pins, MODEID(2:0),
which enable the user to select which mode the part is
operating in. These modes are summarized in Table 2.
MODE DESCRIPTION
000
ERROR DATE MODE
X01
DIAGNOSTIC OUTPUT MODE
X10
GENERATE-DETECT MODE
100
CHECK-BIT INJECTION MODE
X11
NORMAL OPERATING MODE
Table 2. IDT49C465 Operating Modes
104
PROTECTING YOUR DATA WITH THE IDT49C465
32-81T Flow-thruEDCTM UNIT
APPLICATION NOTE AN-64
ERROR DATA MODE (000):
In this mode the contents of the Error-Data Register are
output uncorrected on the SO Bus. The Error-Data Register
is a 32-bit register which gets latched under the following
conditions: 1. an error condition has been detected by the
EDC-ERROR) and is asserted low, 2. the on-chip 4-bit
Error-Counter reads zero 0000 (i.e. no error has occurred
since the last clear operation), 3. the input signal, SCLKEN),
is held low so that the diagnostic clock, SYNCLK, is enabled,
4. the diagnostic clock, SYNCLK, undergoes a LOW-to-HIGH
transition.
Data is latched into the Error-Data Register from the output
of the Memory Data Latch when and only when these conditions are met. Thus, the Error Data Register contains the
Memory Data word corresponding to the first error since a
clear operation (assuming SYNCLK has been run continuously). If the Error Data Register has just been cleared, then
output of the contents of this register will provide a source of
zero-data if that is required.
BIT16:23
The contents of the Syndrome Register, which is
an 8-bit register within the Diagnostic Unit, is
output on the SO Bus at these positions (LSB at
bit 16, MSB at bit 23). The Syndrome Register
gets latched at the same time as the Error Data
Register and contains the Final Syndrome corresponding to the first error to occur since a clear
operation.
BIT 24:27
The contents of the on-chip 4-bit Error-Counter
are output on the SO Bus at these positions (LSB
at bit 23 and MSB at bit 27). The Error-Counter
which gets clocked under the following conditions: 1 . An error condition has been detected by
the EDC, i.e. xto(ERROR) is asserted low, 2. the
on-chip 4-bit Error Counter does not read 1111
(or F HEX), therefore, not more than 16 errors
have occurred since the last clear operation, 3.
the input signal, xto(SCLKEN), is held low so that
the diagnostic clock, SYNCLK is enabled and 4.
the diagnostic clock, SYNCLK, undergoes a LOWto-HIGH transition.
DIAGNOSTIC OUTPUT MODE (X01) :
In this mode a 32-bit Diagnostic Word is output on the SO
Bus. The structure of this word is outlined in Figure 7.
BITS 0:7
BIT 8:15
Error
Type
The output of the check-bit multiplexer is output
directly on the SO Bus at these positions (LSB at
bit 0 and MSB at bit 7).
Whatever is being forced on the PCBI(7:0) input
pins is output on the SO Bus at these positions
(LSB at bit 8 MSB at bit 15).
Test
Error
Counter
Syndrome Bits
Register Contents
The Error Counter will tell the number of errors
that have occurred since the last clear operation.
BIT28:29
Reserved
BIT30:31
The contents of the Error Signal Register, which
is a 2-bit register is output on the SO Bus at these
positions (SB at bit 30 and MSB at bit 31 ). Bit 0
and bit 1 of the register are set if a Multiple Error
has been flagged and bit 1 only is set if a Single
Error has been flagged at the same time and
under the same conditions as the Error Data and
Syndrome Registers are latched.
Partial Checkbits
from Input Pins
3
Byte 0
Byte 2
Byte 1
2311121
12°
716151413121110
716151413121110
716151413121110
-128 27
24 23
16 15
8 7
Byte
MiS
31
Checkbits
Figure 7. Output Syndrome/Diagnostic Word
105
PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow·thruEDcn< UNIT
APPLICATION NOTE AN-64
GENERATE·DETECT MODE (X10) :
In this mode, detection and generation take place but no
correction. Data whether correct or not, passes thru the
device from the MD Bus to the SD Bus.
NORMAL OPERATING MODE (X11):
This is the mode where normal detection/correction and
generation takes place for a single-slice device (32-bit EDC
system) or for the upper and lower slices in a cascaded 64-bit
EDCsystem.
CHECK·BIT INJECTION MODE (100):
In this mode the check-bit multiplexer enables bits cl:7 from
the output olthe System Data Latch to be fed into the EDC as
a check-bit input, normal correction is activated. This is a very
useful capability for carrying out a diagnostic check on the
detect/correct path of the EDC.
PARITY FOR THE SYSTEM BUS
The IDT49C465 supports byte parity on the SD Bus, with
the polarity of the parity ( even or odd) selectable using the
input pin PSEL. If PSEL is low, then parity (both checking and
generation) will be even. If SPSEL is high, then parity will be
odd. The part has 4 parity I/O lines one for each byte of the
SD Bus and a parity error signal, PERR), which flags a parity
error on in-coming data by being asserted low.
PARTIAL BYTE WRITE AND READ·MODIFY·WRITE
CAPABILITY
The IDT49C465 supports, through a number of features,
Partial Byte Writes and Read-Modify-Writes cycles. Firstly
the SD Bus has 4 Byte Enable signals associated with it,
BE(3:0), these input lines provide, in conjunction with SOE),
separate output enable control on each byte of SD bus data.
The BE bus is also the control input to the Sys-Byte-Mux, this
mux enables mixing on a byte-by-byte basis of data from the
SD latch (A input to mux) and from the Pipe-Line latch (B input
to mux). So, for example, if the processor wanted to do a
Partial Write or Partial Store of a byte (byte position 3) to a
memory location byte position 3 the following sequence would
occur: (1) read the memory location in question through the
MD Bus and correct if possible or necessary. The corrected
data-word will be latched into the Pipe-Line latch, (2) the byte
to be written is latched into the SD Latch at byte position 3, all
other byte are undetermined, (3) Now we have both pieces of
data necessary to construct the 32-bit word to be written to
memory and (4) BE(3) is held low and all other BEs are held
high. Thus the output of the Sys-byte-Mux is the correctly
constructed 32-bit word which is then written to memory
through the MD Bus with it's corresponding check-bits.
64-BIT GENERATE
A very useful and ultimately cost-saving measure associated with the IDT49C465, is its 64-bit generate mode. If the
CODE ID of the IDT49C465 is set at 01, the part is configured
as a single-slice 64-bit generate EDC. While operating in this
mode, the lower 32-bit of the 64-bit data word is input on the
MD bus pins and the upper 32-bit of the 64-bit data word is
input on the SD bus. The a-bit generated check bits are output
on the CBO bus. In 64-bit generate mode, the EDC is dedicated to check-bit generation, all other features are disabled.
Because the 64-bit generate is executed in a single slice,
very fast generate speed can be achieved (15ns as opposed
to 30ns in a two-slice 64-bit cascaded system). This feature
can also help reduce part count. In 64-bit memory systems, it
is common to use 4 32-bit EDC devices; 2 for detect/correct
and 2 for generate. With the 64-bit generate capability, this
part count is reduced from four to three.
WHY FLOW·THRU EDC
To fully understand the advantages of the IDT49C465
flow-thru EDC over the IDT49C460 bus-watch EDC, it is
necessary to first know the architectural differences between
the IDT49C465 and the IDT49C460. Figure a compares the
simplified internal architectures of the two chips. As compared with the IDT49C460, the IDT49C465 has the following
unique features:
•
•
•
•
•
•
•
•
Dual data buses
Dual check-bit generators: one for SD Bus and the otherfor
MDbus
Independent check-bit generation path
Independent error detection/correction path
Dedicated syndrome output
Dedicated check-bit output
Output pipeline latch
Parity check/generation
These features greatly simplify the interface of the EDC
unit with the system data bus and the memory data bus, and
thus can considerably improve the system performance.
Generally speaking, in a single bus EDC architecture like the
IDT49C460, the data bus connects to both the processor and
the memory system. Thus, in a normal correction cycle, data
is read into the EDC from memory through the data bus, and
the data is corrected. Then, the data bus is enabled as an
output and the corrected data is sent to the processor.
Therefore, during a correction cycle, the data bus must be
turned around from being an input to being an output.
Consequently, a single bus architecture has inherent delays
associated with the enable/disable times of the data bus
output buffer. On the other hand, separate data buses, as in
the IDT49C465, allow us to dedicate buses to a specific
direction of data flow and, as such, is a superior architecture.
In a 32-bit system using common I/O memory, the dual bus
architecture of the IDT49C465 allows direct interface of the
flow-thru EDC unit with the system data bus and the memory
data bus, as shown in Figure 4a. On the other hand, if the
IDT49C460 is used, then two sets of transceivers are needed
to buffer both system data bus and memory data bus to the
single data bus of the IDT49C460, as shown in Figure 3a.
Similarly, in a 32-bit system using separate I/O memory,
the dual bus architecture of the IDT49C465 allows direct
interface of the flow-thru EDC unit with the memory data bus.
Only a single set of transceivers is used to connect the CPU
106
PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDCfM UNIT
APPLICATION NOTE AN-64
system data bus to the EDC unit, as shown in Figure 4b. On
the other hand, if the IDT49C460 is used, then a set of
transceivers and a set of buffers are needed to hook up both
system data bus and memory data bus with the single data
bus of the IDT49C460.
In particular, the multi-bus architecture and the independent
error generation and detection/correction paths of the
IDT49C465 provide significant performance improvement in a
64-bit system using two cascaded EDC units. Figure 9 shows
the internal data paths of cascaded IDT49C465s and cascaded
IDT49C460s during a read (error detecVcorrect) operation. In
the IDT49C465 case, the entire error detecVcorrect path can
be divided into two steps. In the first step, the lower 32-bit unit
generates the partial check bits from the lower 32-bit data, and
then compares the partial check bits with the original check
bits to generate the partial syndrome bits. At the same time,
the upper 32-bit unit generates the partial check bits from the
upper 32-bit data. Then, the partial syndrome bits from the
lower unit and the partial check bits from the upper unit are
exchanged between the two units. In the second step, both
lower and upper units generate the final syndrome bits
independently and then correct errors in the lower 32-bit data
and the upper 32-bit data, respectively, in parallel. Therefore,
the total delay time is the sum of MD-to-SYO plus CBI-to-SD.
On the other hand, in the IDT49C460 case, the entire error
detecVcorrect path can be divided into three steps. In the first
107
step, like in the IDT49C465 case, the lower 32-bit unit generates
the partial check bits from the lower 32-bit data, and then
compares the partial check bits with the original check bits to
generate the partial syndrome bits. At the same time, the
upper 32-bit unit generates the partial check bits from the
upper 32-bit data. However, in contrast to the IDT49C465
case, only the partial syndrome bits from the lower unit are
sent to the upper unit. In the second step, the upper unit
compares the partial check bits from the upper 32-bit data with
the partial syndrome bits from the lower unit to generate the
final syndrome bits. Then, the final syndrome bits are sent
back to the lower unit. Finally, in the third step, the lower unit
and the upper unit correct the errors in the lower 32-bit data
and the upper 32-bit data, respectively. Consequently, the
total delay time is the sum of DATA-to-SC plus BC-to-SC plus
CB-to-DATA, which is much longer than the delay in the
IDT49C465 case. Moreover, since the IDT49C460 has only
one check bit input bus, an external octal tri-state buffer is
needed to multiplex the original check bits and the partial
check bits.
Based on the above discussion, Table 3 summarizes the
performance comparison between the IDT49C465 and the
IDT49C460D, the fastest version of the IDT49C460. It can be
seen that in most situations, the IDT49C465 has significant
speed advantage over the IDT49C460.
PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDCTM UNIT
APPLICATION NOTE AN-64
(
• • • • • •IIIIqIlJlll~ syndrome
Features Of IDT49C465 )
-Dual Data Bus Architecture
generator
-Dual CheckBit(CB) Generators
-Independent CB Generate Path
-Independent Error
DetecVCorrect Path
-Dedicated Syndrome Output
-Dedicated CB Output
-Output Pipeline Latch
-Parity Check/Generate
-1 Off-chip Feedback for
64-bit Error Correct
-144-pin PGA
-
c:::J
Path For Detect
and Correct Only
Path For Generate,
Detect and Correct
(a) Simplified Block Diagram of IDT49C465 EDC Unit
(
syndrome
generator
())
Features Of IDT49C460 )
-Single Data Bus Architecture
E
-Single Checkbit Generator
"0
c>,:l
-
-Shared Syndrome and CB Output
eSa.
CI)
-2 Off-chip Feedback for
S4-bit Error Correct
a I11III1IIIIIIIIliliiii1IIIIIIIIliliiiil1li
-S8-pin PGA
-
Path For Detect
and Correct Only
Path For
1""""""',',',',1 Generate Only
c:::J
Path For Generate,
Detect and Correct
(b) Simplified Block Diagram of IDT49C460 EDC Unit
Figure 8. Internal Architecture Differences Between IDT49C465 and IDT49C460
108
PROTECTING YOUR DATA WITH THE IDT49C465
32·BIT Flow·thruEDCTM UNIT
APPLICATION NOTE AN·64
SD32-63
MD32·63
Generate
Final
Upper 32-Bit
CODE ID = 11
CBIO-7
Lower 32-Bit
CODE ID= 10
Syndrome
Syndrome
SDO-31
MDO-31
(a) 64·bit Error Detect/Correct Path of Cascading IDT49C465
DATA32-63
DATA32-63 -
----------------1IIj
....
Upper 32-Bit
CODE ID = 11
Bits
Generate
Partial Syndrome
DATAO-31
Lower 32-B it
CODE ID= 10
DATAO-31
(b) 64-bit Error Detect/Correct Path of Cascading IDT49C460
Figure 9. Comparison of 64-bit Error Detect/Correct Path Between IDT49C465 and IDT49C460
109
"'-V
'l"~
~-l
-lm
6'g
:ilz
"'1:)
Common 1/0
:r<
Co
Separate 1/0
me
c:a
64-bit
Cascade
32-bit
(1)
Read (1)
MD->SD
Write
20ns
SD->CBO
Read
15ns
Read(1)
Write
MD->SYO
15ns
SD->CBO
CBI->SD
20ns
PCBI->CBO 15ns
15ns
MD->SD
FCT2~2)
Read(1)
Write
20ns
FCT2452)
5ns
SD->CBO
5ns MD->SYO
15ns
CBI->SD
FCT24!)
IDT49C
465
20ns
o
IDT49C
4600
15ns
35ns
40%
Faster
26%
Faster
34%
Faster
28ns
19ns
47ns
FCT2~)
D->D
FCT2452)
5ns
18ns
FCT2J2)
D->SC
5ns
5ns
14ns
FCT2J2)
D->SC
-
_L-
____
NOTES:
1. The EDC units perform correction always.
2. FCT245 is high-speed bidirectional transceiver.
25ns
20ns
30ns
5ns
14ns
11ns
CB->D
12ns
FCT2J2)
D->SC
CB->SC
FCT24~2)
14ns
D->D
11ns
FCT2J2)
19ns
5ns
18ns
FCT2J2)
D->SC
5ns
14ns
5ns
FCT2452)
FCT24S2)
5ns
20ns
SD->CBO
15ns
!
5ns PCBI->CBO 15ns
35ns
-_._--
30ns
-------
5ns
FCT2J2)
5ns
D->SC
14ns
D->SC
14ns
CB->SC
11ns
CB->SC
11ns
CB->D
12ns
FCT245 2)
Table 3. Performance Comparison
15ns
47ns
5ns
------
5!
:i!m
18%
Faster
28ns
5ns
§~
=i::e
Write
40ns
12%
Faster
CB->SC
FCT2J2)
-~~
30ns
~c
64-bit
Cascade
32-bit
-
5ns
,
S
o
z
~
iil
i
PROTECTING YOUR DATA WITH THE IDT49C465
32-BIT Flow-thruEDCTM UNIT
APPLICATION NOTE AN-64
CONCLUSIONS
Whether designing a correct always (flow-thru) EDC or
bus-watch EDC memory systems, lOT offers a high
performance solution for keeping memories error free. The
key system benefit for using EDC is the continuous system
operation, even with hard or soft errors occur. The key benefit
for using a flow-thru EDC is the reduced memory design time
when performing the correct always function, and improved
performance for 64-bit memory systems.
111
~
i,;;)
APPLICATION
NOTE
AN·94
ERROR DETECTION AND
CORRECTION WITH IDT49C466
~
Integrated Devic;e Tedtnology, Inc;.
By Anupama Hegde
INTRODUCTION
It is widely accepted that system failures and down time
claim a heavy toll in terms of cost and performance. When a
system crashes, unrecoverable data may be lost. Even in the
best case, the user suffers a great deal of inconvenience.
Erroneous data or loss of data integrity is a major cause of
system failure. Hence system designers are constantly trying
to minimize the occurrence of errors in their systems.
Data errors commonly occur in storage devices such as
RAM, disks and magnetic tapes. Henceerror handling schemes
are commonly aimed at protecting the data in these devices.
Dynamic memory is, in particular, highly susceptible to errors.
As we move towards systems with larger memories, data
protection schemes become increasingly relevant because
the error rate is found to increase with the memory size. Till
recently parity has been the traditional method of data protection. Parity, however, has several drawbacks: it masks out
even bit errors, it cannot locate the bit in error and beyond a
certain buswidth it can become inefficient. These factors have
lead to the development of a new breed of devices for data
protection. Error Detection and Correction circuits (EDCs or
EDACs) are today's response to the growing need for greater
data reliability. They afford a greater level of protection than
that offered by parity, by using a higher order error correction
code (Modified Hamming code).
Implementing error detection & correction in a system involves not just the hardware to perform the error checking but
also extra memory for storage of "checkbits", which are the basis
of error detection and correction. An EDC may add some
overhead to a system in terms of speed and cost. This is,
however, compensated by a significant improvement in
system performance. The following Figures underline this pOint:
Given a 4M x 64 DRAM memory with an FIT(Failure in time)
specification of 252 1 :
MTBF (mean time between failures) without
EDC = 1.76 years
MTBF with single-bit error correcting 64-bit
EDC = 3935.4 years
The Figures given here are merely a guideline for comparison of the two cases and will depend entirely on the DRAM
used and the memory configuration.
Thus EDC can be looked upon as a sophisticated parity
system with the capacity to correct. Two primary functions are
performed by an EDC unit within the framework olthe memory
read and write cycles - during a memory read, errors are
detected andfor corrected and during a memory write, checkbits
are generated.
ERROR DETECTION AND CORRECTION WITH
THE 49C466
Choosing the Right EDC
EDC considerably upgrades reliability but, as mentioned
earlier, there is a certain amount of overhead associated with
implementing EDC. This is because of the checkbit memory
required and the nanoseconds it adds to the main memory
cycle times. The checkbit overhead can be minimized by
increasing the size of the data word used to generate the
checkbits. The table below illustrates this point and shows
how parity compares with EDC for various data word sizes.
Assuming a distance-of 4 Hamming code for the EDC and
byte parity:
As an example, consider a 32-bit EDC and a 64-bit EDC.
We see from the table above, the former requires 7 checkbits
DATA WORD
SIZE
PARITY BITS
REQUIRED
EDC CHECKBITS
REQUIRED
16
32
64
128
2
4
8
16
6
7
8
9
2596tbl01
for each 32-bit data word. Hence every 64 bits of data requires
7+7=14checkbits in memory. A 64-bit EDC on the other hand
requires only 8 checkbits to provide single bit error correction
and dual bit error detection. Thus, as far as checkbit efficiency
goes, a 64-bit EDC is better than a 32-bit EDC. One other
advantage of a wider EDC is that less checkbit memory
implies a lower error rate in checkbit memory. Going after
even wider EDCs seems tempting in this light, but a compromise has to be made because of two factors.
Prevalent system bus widths impose a practical limitation
on how wide a bus can get. It is fairly common nowadays,
however, to see a 64-bit memory bus and hence a 64-bit EDC
is often easily accomodated. An EDC that is wider than the
memory bus needs additional control and logic circuitry to
integrate the EDC with the memory system. The greater this
difference in (EDC and memory) bus widths, the more complex is this interface. Also, the error handling capacity effectively decreases as the EDC bus gets wider because the same
level of protection (1 bit correction,2 bit detection) is provided
for a wider word. Two 32-bit EDCs provide this for each 32-bit
word, which allows correction of some 2-bit errors and detection of some 4-bit errors for each 64-bitword. Thus, constraints
for a given system determine the optimum trade-off.
NOTE: See appendix for further details on calculation of MTBFs.
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
©1993 Integrated Device Technology, Inc.
9/91
112
.....,....-- ------ ....... - -- -ERROR DETECTION AND CORRECTION WITH IDT49C466
APPLICATION NOTE AN·94
49C466 Operation and Features
Memory Write
By the nature of its function, the EOC is concerned with data
transfers between the processor and memory. The IDT 49C466
has a flowthrough architecture which permits transparent data
flow through the EOC. The 49C466 also increases checkbit
efficiency by providing two 64-bit wide bidirectional data
buses.
The error detection & correction operation in the 49C466 is
similar to previous generation lOT devices. A modified Hamming code is used to generate the checkbits and the syndrome
decoding is identical to cascaded mode operation in the 32-bit
EOC, the 49C465. The modified Hamming code used allows
for flagging of all single, dual and three bit errors in the 64-bit
data word. Some three bit errors alias as single bit errors,
however, and may hence be wrongly decoded by the syndrome decoding logic (MERR* may not be asserted). The
code allows for correction of all single bit errors in the data
word.
The 49C466 has five modes of operation. In the normal
mode, two kinds of operations are performed. During a "memory
write", checkbits are generated based on the data that is
written and during a "memory read" single-bit errors in the data
are corrected. In the detect-only mode, the "memory write"
operation remains the same but during a "memory read" any
errors detected are flagged by ERR and MERR pins. The data
is passed though unaltered. The other three modes are useful
fortesting & diagnostic purposes. The EDC mode of operation
is set by the user by loading the mode register through the
system data bus.
Read and write paths are independent of each other in the
49C466. In fact, the device has alternate paths for each of
these (read and write cycles). One path includes the 8/16deep data buffer while the other provides a latch in place of this
buffer. WBSEL(Write Buffer Select) and RBSEL(Read Buffer
Select) pins select the output of either the buffer or the latch
(for example - RBSEL=high selects output from the Read
Buffer rather than the MD_OUT latch, WBSEL = 0 selects the
output of the SO_IN latch rather than the Write Buffer).
During a memory write, the EOC generates checkbits
corresponding to the data being written to memory (data flow
from SD bus to MO bus). These are output onto the CBSYN
bus and written to checkbit memory. This is a necessary part
of EDC operation. Unless all checkbits corresponding to the
data in memory have been generated and stored in checkbit
memory, no error checking is possible.
To prevent contention on the SD bus, the SD output buffer
must be disabled, during a memory write. The MD and
checkbit output buffers must be enabled to pass data and
checkbits to memory.
There are several ways that the "write path" can be configured but the maximum "write time" with input and output
latches transparent is 15ns.
Figure 2 illustrates the data path during a write operation.
The alternate write path, where the data is buffered, is shown
in Figure 3.
Memory Read
A memory read involves checking data from memory for
errors. Given below is a description of what actually takes
place during a "read cycle".
Data and checkbits from main memory are fed to the EDC.
Checkbits corresponding to the read data are generated
within the EOC. The two sets of checkbits are internally
compared to produce the syndrome word. The EDC then
decodes the syndrome word to check for errors.
The syndrome is also clocked into the syndrome register on
the rising edge of SYNCLK. The syndrome register contents
can be output on the CBSYN bus. The CBSEL pin controls the
output of the CBSYN bus. While CBSEL is low, checkbits
generated during a write are output. When CBSEL is high,
syndrome generated during a read are output. Figure 4 shows
the data path during a normal read operation.
A buffered read operation is illustrated in Figure 5.
...-------------1 CB_in
ERROR
CORRECT
L--J-------------'---1 MD_in
SDjn
Write Path
CB-out
2596 drw 01
Figure 1. Basic Memory Read and Write paths Through the 49C66
113
ERROR DETECTION AND CORRECTION WITH IDT49C466
APPLICATION NOTE AN-94
BEO-? -'i---1I....----------,
SOE -.f---,--,
read path
SOO-63
write back path
~
:::2:
wH------~
SO OUT
LATCH
>----l~
~
MOO-63
'----.---114-- MOE
__-----~--~--SOOLE
.---~._~- CBSEL
I-a:
_0
!Ill-
o:':::~
CIl@ W
SO
CHECKBIT
LATCH
Z
>-
IZ
OW
Cl
POOl
~
o
~-------------------------_44_~WBSEL
EOC466
2596 drw 02
Figure 2. Memory Write without Write Buffer
SOE -"1-----,
r---------------------------~~ WBSEL
BEO-?~+--tI......
SOO-63
......----I~
SO OUT
LATCH
MOO-63
~--
____44__-MOE
----------~~~--SOOLE
.------f--,.-~-
SO
CHECKBIT
LATCH
Z
~
SO checkbits
o
2596drw 03
Figure 3. Memory Write with Write Buffer
114
CBSEL
-----
--
.....
ERROR DETECTION AND CORRECTION WITH IDT49C466
APPLICATION NOTE AN-94
Beside its primary task of error checking, the 49C466
integrates certain other useful functions on chip. It supports
parity checking and generation, partial word writes and diagnostics. It provides the user with flexibility by providing 8/16
deep Read and Write buffers and the facility to latch all data
flowing in and out of the part.
The parity generation and checking capability in the 49C466
is very useful in checking the integrity of the data being written
to memory. Parity checking is done on data from the system
side. The parity bits are input on the EDC POol pins. Parity is
then generated for the input system data and a comparison of
this and the input parity bits is carried out internally. The result
of this comparison is reflected in the PERR pin output (a
discrepancy asserts PERR). Parity bits are also generated for
data read from memory and output on the POol pins once
again. The parity type (odd or even) is selected using the
PSEL pin. The PERR signal does not affect any of the other
circuitry in the device and hence the user may safely ignore
the parity feature if his system does not support parity.
A partial word write or byte merge is analogous to a readmodify-write cycle. The checkbit word generated by a partial
data word would be incomplete and hence incorrect. Hence
the need to differentiate the "partial word write" case from a
normal write operation. The following steps must be followed
to ensure correct generation of checkbits for the complete 64
bit word :
1. Read the contents of the location being written to.
2. Merge the partial word with these contents forming a
composite 64 bit data word.
3. Generate the 8 checkbits for this composite word.
On account of the dual bus feature of the 49C466, data may
be written to the EDC (from processor/cache) while data is
read from main memory to the EDC. This feature is useful
during partial word writes (writing less than eight bytes) and
can buy some time for the designer for whom each nanosecond counts. The time required to turn the external buses
around must, however, be taken into consideration.
PARTIAL WORD WRITES
The 49C466 supports "partial word writes" or "byte merging".
These refer to write operations involving words shorter than 64
bits such as a byte write. Partial word writes are handled in the
49C466 by the byte multiplexer. The 49C466 has eight BE (byte
enable) control pins. These control the byte multiplexer and
enable the system data output buffer. When a BE input is high,
it selects a byte from the MD "write back path" shown in Figure
3 and Figure 4 rather than the normal EDC write path. Each BE
input is AND-ed with the SOE signal and the result determines
which byte is output on theSD bus. A BE pin that is low disables
the SO output buffer for the particular byte referenced and
selects a byte from the write bufferor SO_in latch rather than one
from the MD write back path.
DESIGNING WITH THE 49C466
As typical application examples, we consider 32-bit and 64bit processor designs using EDC to protect the slower dynamic main memory. On account of its 64-bit data buses, the
49C466 is easily interfaced to 64-bit systems. As mentioned
earlier, providing a 64 bit memory subsystem bus is often
advantageous even in 32 bit processor systems. Thus, even
though the interface between 32- and 64-bit wide buses may
be slightly more complex, it is often worthwhile. Consequently
providing a 64-bit EDC may still be an attractive choice.
ERR~+---------~~~~
MD
i-------\CHECKBIT
MERR:I-----iQ!~~
SOE~-~---.
BEQ-? ...-+-.....-:1......0.
. -______~~========~--------~~L~A~TC~H~~~__
MD
CHECKBIT
GENERATOR
MD IN
LATCH
write back path
>--.......---<
MDO-63
'-----e~~~ MOE
POol
PARITY
r----,.-+~
\.r-~~t---I GENERATOR
SD checkbits
EDC 466
2596 drw 04
Figure 4_ Memory Read without Read Buffer
115
CBSEL
ERROR DETECTION AND CORRECTION WITH IDT49C466
APPLICATION NOTE AN·94
ERROR:~~I SYNDROME I.
ERR
MERR
RBREN ...
MCLK
DECODE
MD
CHECKBIT
LATCH
GENERATOR j.
-
r:rnrn
~
CBIO-?
"
If'
MDllE
SCLK
&il:
BEQ-7
.A
SDO-63
f-
RBSEl
f
~'IR~D
~ ~YiF,~~, ~
I
ERROR
CORRECT
write
back
pam
"
MD
CHECKBIT
GENERATOR
l
I
...
~
w
=-...
POol
~ GENERATOR
PARITY
~
.....--.,.x
~
CD
<
MD IN
LATCH
I
7~
i
I
I"MDO-63
... MOE
CBSEl
~:::J
SD ,"''''''''' -
EDC466
"
CBSYNO-?
2596 drw 05
Figure 5 Memory Read with Read Buffer
R3000 BASED SYSTEM
The MIPS R3000 RISC architecture has attained much
popularity in recent years. Therefore, we discuss here a
design example showing the interface between the 32-bit
R3000 and the 64-bit 49C466. This typical R3000 design
employs 2 data buses. The high speed "processor" data bus
is the interface between processor, caches & buffers while the
slower 'memory' data bus links the buffers and I/O devices
(peripherals & memory). Providing two separate buses for the
processor and memory subsystems, in this manner, serves
multiple purposes. It reduces the traffic on each bus and
allows for different speeds and widths on the two buses.
In the design shown, the 49C466 is positioned between the
64-bit memory bus and main memory as in Figure 6. Programmable logic is used to generate the control signals for the
49C466 64-bitflowthruEDC"'. Appropriate control signals from
the R3000 processor provide input to the PAL.
The example considered here does not use the on-chip
read/write buffers of the 49C466 and the device is used in a
non-pipelined mode. External read/write buffers are provided
as the interface between the 32-bit processor bus and the 64bit memory bus. A 64-bit wide memory bus demands that an
appropriate scheme for (32-bit) word gathering be devised.
One method of implementing such a scheme is described
here.
On write cycles, two 32-bit words are gathered in the two
external write buffers and the 64-bit word is output to the
memory bus.
Gathering 32-bits words, in this fashion, may not always be
permissible because of requirements thatthe two 32-bitwords
be written to specific, non-sequential locations. Such cases
are treated as partial word writes by the EDC. Each 32-bit
word write is hanoled as an individual partial word write cycle.
A partial word write cycle requires thatthe 32-bitword from the
adjoining memory location is read before the whole 64-bit
word is written back to memory.
The two categories of writes - "gathering permissible" and
"gathering not permissible" - are differentiated by comparing
the write addresses generated by the processor for the two
words. This demands that the first write address must be
latched until the next write request is received. If the two
addresses are not consecutive, a partial word write signal is
sent to the PAL. This initiates a partial word write cycle for
writing the first word to the EDC.
To understand this particular situation better, let us consider a case where two write addresses have been compared
and found to be non-sequential. The first write data is buffered
in WBufA and the second one in WBufB. Each of these write
request are treated as "partial word writes" and handled in the
order they were received. In order to support byte access, the
memory must be byte addressable. The contents of
WBufA are output to the SD bus of the 49C466. To perform
the "partial word write" cycle contents of the location address
output from WBufA are simultaneously read
onto the MD bus of the 49C466. Merging of these two 64bit wide data words is performed inside the 49C466 and the
merged 64-bit word is output on the 49C466 MD bus and
written back to the same location. When this cycle is complete,
the same thing is done for the second write data which is
stored in WBufB.
During read cycles, the issue of gathering "reads" and
comparing read addresses can be avoided altogether by
always reading a 64-bit word from memory.The required 32
bits are selected and the rest ignored.
116
ERROR DETECTION AND CORRECTION WITH IDT49C466
APPLICATION NOTE AN-94
STEP 1 :
Main Memory
EDC
MD
,.----1
IXXXXEFGH I
BEO-? = 00001111
STEP 2:
EDC
Main Memo
~
S
IABCDEFGH
16~
~'$<'ll:'
- ,- ,
___
I
BYTE
"~~IMUX
2596 drw 06
Figure 6. Byte Merge
Details of this scheme, implemented with IDT parts, are
shown in Figures 7 and B.
The design shown, uses a bus mUltiplexer, the
IDT49FCTB04 to transfer each 32-bit word to the appropriate
SD bus lines (0-31 or 32-63). The write buffer used (IDT
79R3020) buffers both addresses and data. Two bus multiplexers are used to create a crossbar type of arrangement, so
that the output of each write buffer can be directed to either the
upper or lower SD lines of the 49C466.
64 BIT SYSTEMS
The 49C466 interface to a 64-bit processor is quite straightforward. Intel's iB60 and MIPS' R4000 are two popular processors matching this buswidth. Figure 9 shows an iB60 based
system with EDC. In the system shown all memory accesses
go through the 49C466. This kind of a setup would ensure
filtering of errors from all memory data accessed. The iB60
does not support parity but external parity support circuits (like
the AMD2BO) enable the user to still take advantage of the
parity feature of the 49C466. This is particularly useful when
caches are employed and some monitoring of data written to
main memory is required.
As mentioned earlier, with the trend to segregate processor
and memory subsystem designs, a 64 bit memory bus is not
unlikely in a 32-bit processor design. In these cases too the
49C466 interface is similar to the one shown above.
Also additional hardware is required to correct more than one
bit in error. Taking these factors into account, little motivation
to move towards multiple bit error correction can exist at this
point.
Since hard errors are non-random it is possible for hardware to differentiate them from soft errors. Once this is done
it is a simple matter to correct the data provided there is not
more than one soft error present. Given below is a brief
description of how hard errors can be eliminated.
When an error occurs, the error data is latched in the "error
data register" of the 49C466. This data can be read by the
processor in the Error Data Mode. In order to filter out hard
errors, this data should be inverted and written back to the
same location. A subsequent read will serve to identify hard
errors, for due to the hard error, the affected bits remain at their
original logic level.
Consider a case where bits 3,6 and 7 (shown by bold
letters) are affected by hard errors:
Correct Data
Error Data (ED)
Inverted error data
Inverted error data after
subsequent read (SlED)
By XOR-ing the Error Data
with the data from the subsequent
read, the bits in (hard) error are
isolated (indicated by zeroes).
(SlED) XOR (ED)
MORE EFFECTIVE EDCS
Most present generation EDC units are able to correct only
single bit errors. Given the probability of occurrence of multiple bit errors, this is, in most cases, sufficient. The ratio of
single bit errors to dual bit errors ranges from 5:1 to 10:1. The
probability of multiple bit soft errors occurring is negligible.
= 10101001
=01100001
= 10011110
= 01010110
= 00110111
Thus, all that is externally needed to perform this check is
XOR logic.
117
ERROR DETECTION AND CORRECTION WITH IDT49C466
APPLICATION NOTE AN-94
l
R3DDD
D - Cache
~5
I I
I
1- Cache
~~
Processor Data Bus
I
e
I
RIW Buffers
-'
U
I
I
Memory Data Bus
V
Controller
--'"
EDC466
Checkbit
Memory
<:=)
D
Main Memory
2596 drw 07
Figure 7. R3000 based System with EDC
AddrBus2
LE
~CE1
u
Even Memory Bank
MOo-63
C/)
~
C/)
'" '"
w
~
~
C/)
C/)
a::
o
o
«
EOC 466
a:«
0.
+
Even CBMemory
~
CB10-7
CBSYNO-7
«
o
Odd CBMemory
WBUFB
79R3020
X4
SOBS1B
OE
WBUFA WBUFB BMUXA BMUXB
control control control control
WtMemB
MemWr
CONTROLLER
(with Address
comparator logic)
MemRd
RdBusy
EOC
control
CE1
CE2
WrBusy
Figure 8. R3000 based EDC System - Memory Write
118
2596drw 08
ERROR DETECll0N AND CORRECTION WITH IDT49C466
APPLICAll0N NOTE AN-94
AddrBus2
u
Even Memory Bank
1-________-1 Data
Memory
Moo-63
Odd Memory Bank
'"
:oJ
co
(f)
(f)
w
a:
o
oc(
~
0::
c(
0.
~
CBIO-7
CBSYNO-7
o
Even Memory Bank
1--_____________1Checkbit
Memory
Odd Memory Bank
RBUFC
control
BMUXC
control
MemWr--------~.~r~~--~~--_.
MemRd --------~.~I
RdBusy
.---------1
WrBusy
+--------1
EDC control
CONTROLLER
(with Address
comparator logic)
2596 drw 09
Figure 9. R3000 based EDC System - Memory Read
MEMORY SCRUBBING
CONCLUSIONS
An alternative (or in addition) to putting the EDC directly in
the read/write path, is putting it in the DRAM refresh path. This
ensures that memory is periodically checked for data validity.
This is a good practice as it prevents buildup of single bit errors
at infrequently accessed memory locations. There are, however, chances of errors slipping through the net in this scheme
when an error occurs between a memory refresh and the next
memory read or write.
The urge to provide greater value and reliability in today's
competitive computer systems, is likely to make EDC a
standard feature in the near future. With the continuing trend
towards wider buses, it is only natural to move towards wider
EDCs. This also makes the EDC implementation more efficient. IDT is at the forefront of this new generation of EDCs
with the powerful new 64-bit flowthruEDC, the 49C466. The
49C466 has an edge over it's competition by providing several
useful features such as byte merge capability, 16 deep buffering, latches, diagnostic registers, parity generation and
checking and competitive detect and correct times. Currently
the device is available in 208 pin PGA and PQFP packages.
119
ERROR DETECTION AND CORRECTION WITH IDT49C466
APPLICATION NOTE AN-94
MEMWR?
~
____________________-.YES
BMUXA: PORTA ->PORTC(SDO-31)
BMUXA: PORTA ->PORTC(SDO-31)
BMUXB: PORTB->PORTC(SD32-63)
Output address on
AddrBus2
2596 drw 10
Figure 10. Flowchart for Write Buffer and Bus MuHiplexer Control During Memory Write
120
ERROR DETECTION AND CORRECTION WITH IDT49C466
APPLICATION NOTE AN-94
APPENDIX
MTBF Calculations
DRAM manufacturers specify a soft error rates in terms of
FITs (failures in time). Assume a 1M x 1 DRAM with soft error
rate = 252 FITs
Thus,
109
MTBF for each 1M x 1 DRAM chip = 252
Output address on
AddrBus2 and assert
CEI and CE2
MTBF for a 4M x 64
memory system (without EDC)
=
453 years
453
= - - = 1.76 years
4 x 64
[A memory system without EDC assumes a system failure
each time a single bit error occurs. This may not be the reality
but this exercise is aimed at showing the difference between
two analogous cases, hence such assumptions are in place.
Failures due to all higher order (dual, three bit, etc.) errors can
be safely ignored in this case due to the overwhelming dominance of single bit errors over other higher order errors. 1
With EDC, extra memory is required to store checkbits,
hence the number of DRAM chips required for the same
memory system goes up.
Checkbit memory (with 64 bit
EDC) required for the above system
Assert RDBUSY
Total memory system chip count
1
= -x 4 x 64 = 32 chips
8
= ( 4 x 64 ) + 32 = 288
So now,
453
= 1.57 years
Memory system MTBF = 288
BMUXC:
PORTB -> PORTA or
PORTC -> PORTA
Now if we assume that with EDC, all single bit errors are
corrected, failures due to dual bit errors become dominant.
Neglecting failures due to higher order errors, we get an
approximation of the MTBF using the following formula:
MTBF (with EDC) =
(MTBF without EOC) x
= 1.57 x y(
2596 drw 11
Figure 11. Flowchart for Read Buffer and
Bus Multiplexer Control During Memory Read
1tx4x1012
2
y( 1t X #
f
0
d
memory wor s)
2
) = 3935.4 years
Thus we see that there is a significant improvement in the
MTBF of a system with EDC.
121
ERROR DETECTION AND CORRECTION WITH IDT49C466
APPLICATION NOTE AN·94
CLK
GENERATION
CIRCUITRY
--0 VCC
SCLK~
MCLK
r~
RBSEL WBSEL SDILE
CLK
,!)4
D
BE
MAIN
MEMORY
DRAM
,8
,
SD
"'
49C466
BE
MD
,64...
i860
1.
MDOLE*
CBSYN
-
READY* W/R*
,8
...
.
CHECKBIT
MEMORY
~
EDC_CONTROL_IN
EDC_CONTROL_OUT
EDC& DRAM
CONTROLLER
NB: EDC_CONTROL_IN: SDOLE*,MDILE,wBEN*,WBREN*,RBEN*,WBREN*,CBSEL,RSO-1,
EDC_CONTROL_OUT: WBEF*,wBFF*,RBEF*,RBFF*,RBHF*,ERR*,MERR*
2596 drw 12
Figure 10. Flowchart for Write Buffer and Bus Multiplexer Control During Memory Write
122
I
'II
g
APPLICATION
NOTE
AN-96
CASCADING THE
IDT49C460 AND IDT49C465
Integrated Device Technology, Inc.
By Anupama Hegde
the partial checkbits in anyone of the slices rather than after
the complete checkbit word is produced. Figure 1 illustrates
the operations involved in a cascade.
During a regular memory read with EDC, checkbits and
data from memory are fed to the EDC. Checkbits generated
from the data are compared with the input checkbits resulting
in the syndrome. This is decoded to produce error signals and
to correct data. When using a pair of cascaded EDCs, the
same operation is done as follows: Partial checkbits are
generated from the partial data input to that particular slice.
These are XOR-ed to produce the final syndrome. The final
syndrome is made available in all the slices. An alternate way
of doing things is to simultaneously generate the final syndrome in all the slices. This parallel approach is faster.
INTRODUCTION
Error Detection and Correction units or EDCs are used to
check and ensure data integrity in computer systems. Standard off-the-shelf devices do not always meet the needs of the
user and need to be cascaded. Cascading EDCs allow the
user to expand the EDC bus width. Wider bus operation is
advantageous because wider EDCs call for less checkbit
memory. On the other hand, an EDC bus wider than the
existing system data bus may call for complicated control
schemes and hardware overhead. Typically, it is desirable to
have the EDC and system bus widths match.
Cascaded EDC operation requires additional logic circuitry. This can be built into the EDC or provided externally by
the user. The IDT49C460 and the IDT49C465 each have the
required cascading circuitry built into them. This application
note explains cascaded EDC operation using the IDT 49C460
and IDT49C465.
THE CASCADING PRINCIPLE
When several EDC slices are combined to create a wider
data bus, none of the slices can individually produce the
complete checkbits. This is because only a part of the complete data word is fed to each slice. Partial checkbits are
generated in each slice. The partial checkbits from each slice
are XOR-ed to generate the complete checkbit word. The
syndrome is produced by an XOR of the complete checkbits
and the input checkbits. The sequential order in which these
XOR operations occur may vary depending on the implementation. For example, the input checkbits may be XOR-ed with
Slice 1
(
PCB1
CASCADING 32-BIT EDCS FOR 64-BIT
OPERATION
Any number of EDCs may be cascaded depending on the
available support logic and performance demands. A dual
EDCcascade, assupportedbythe IDT49C460and IDT49C465
is discussed here.
32-bit checkbit generation logic differs from the 32-bit
partial checkbit generation logic that is required for cascading
two 32-bit EDCs. Eight checkbits are needed by a 64-bit EDC
but the 32-bit checkbit generation logic produces only 7
checkbits. Hence, additional logic is required to generate
partial checkbits. The 64-bit checkbit generation scheme (as
indicated by 64-bit checkbit generate tables in data sheets)
may be split into two 32-bit generation schemes - one
Slice 3
Slice 2
)
(
PCB2
)
2530 drw 01
Figure 1. Complete Checkbit Generation From Cascaded Slices
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
©1993 Integrated Device Technology, Inc.
12191
123
CASCADING THE IDT49C460 AND IDT49C465
APPLICATION NOTE AN-96
operating on data bits 0-31 and the other on data bits 32-63.
This determines the 'partial checkbit generation logic'. Each
cascaded slice then produces 8 checkbits which can be XORed to produce the complete checkbit word.
Also, there mustbesome mechanism to determine whether
the EOC is in cascaded mode or not. If it is in cascaded mode,
each EOC unit must be identified as a unique slice (first,
second, etc.) in the cascade.
The lOT 49C460 and the lOT49C465 differ in their architectures. The IDT49C460 has an older 'bus-watch' architecture
with one data bus, while the lOT49C465 has a dual data bus
Flowthru™ architecture. Both parts have 32-bit wide data
buses and use the same basic principle of operation. The
lOT49C460 and lOT49C465 have CodeD, 1 lines that program
the EOC units to operate in non-cascaded mode or as upper
or lower slices in cascaded mode.
CASCADING THE IDT49C460
The figure below shows the correct connections for cascading two 32-bit IOT49C460s. This makes them function as
a 64-bit EOC for either generate (memory write) or correct
(memory read) operations. Control signals not shown are
common to both units and parallel connections to each slice
may be used.
Memory Write
During this kind of operation you need to generate 8
checkbits for a 64-bit data word. In 32-bit mode, the lOT49C460
generates 7 checkbits for each 32-bit data word. In cascaded
mode the IOT49C460 must generate 8 partial checkbits for
each set of 32 data bits.
If you compare the checkbit generate tables (Tables 6 and
11) of the lOT 49C460 data sheet, you will notice that they are
different. For 64-bit cascaded mode operation, Table 11 is to
be used. Eight partial checkbits are generated by a logic
implementation of the 64-bit checkbit generate table.
In the lower slice; partial checkbit word = 64-bit checkbit
generate table applied to data bits 0-31. In the upper slice;
partial checkbit word = 64-bit checkbit generate table applied
to data bits 32-63.
Example:
Partial Checkbit 0 in lowerslice (PCBO-,s) = 01 EB 02 EB 03
EB 05 EB 08 $ 09 $ 011 $ 014 $ 017 $ 018 EB 019 $ 021
EB 024 EB 025 EB 027 EB 030
Partial Checkbit 0 in upper slice (PCBO_us)= 032 $ 036
$~$~EB~EB~EB~EB~EB~EB~EB
054 EB 055 EB 058 EB 060 EB 061 EB 063
XOR-ing the Partial checkbit 0 from the upper slice and the
Partial checkbit #0 from the lower slices gives the final
checkbit o. Thus, check bit 0 for the 64-bit data word =
(PCBO_ls) EB (PCBO_us)
01 EB 02 EB 03 EB 05$ 08 $ 09 EB 011 EB 014 EB 017 $
018 EB 019 EB 021 $ 024 $ 025 $ 027 EB 030 EB 032 EB 036
EB 038 $ 039 EB 042 EB 044 EB 045 EB 047 EB 048 EB 052 EB
054 E9 055 EB 058 E9 060 E9 061 E9 063,
which is what we get from Table 11 for 64-bit data.
The complete checkbit word for the 64-bit data word is
generated by XOR-ing each of the partial checkbits from the
upper and lower slices. A block diagram illustrating this
operation is given in Figure 2.
UPPER SLICE
LOWER SLICE
49C460
49C460
32 bit EDC
DATAinO-31
32 bit EDC
DATAin32-63
Final Checkbits
2530 drw 02
Figure 2. IDT49C460 Cascaded Mode "Memory Write"
124
CASCADING THE IDT49C460 AND IDT49C465
APPLICATION NOTE AN-96
Memory Read
A memory read or correct operation involves generation of
a complete set of 8 checkbits for the 64-bit data, computation
and decoding of the syndrome word, and correction of the
data.
A regular 32-bit correct operation involves 7 -bit checkbit
words and a 7-bilsyndrome. Apart from this, the procedure is
the same as above.
In 64-bit cascaded mode, you have 8 input checkbits (CBO7), but each individual slice only generates a 'partial checkbit
word'. This is why it is necessary to combine the 'partial
This entire operation is illustrated in Figure 2. It can be
summarized as follows:
1) In the first pass through the lower slice the partial
syndrome is generated.
2) The final syndrome is generated in the upper slice. If an
error occurs in Data bits 32-63, the appropriate bit in the
lower slice is corrected.
3) The final syndrome is sent back to the lower slice. If an
error occurs in the Data bits 0-31, the appropriate bit in
the upper slice is corrected.
Final Syndrome
LOWER SLICE
UPPER SLICE
49C460
49C460
32 bitEDC
Buffer
Enable
32 bit EDC
seQ-?
Partial S ndrome
Final
1 - - - - - , / Syndrome
DATAin 32-63
2530 drw 03
Figure 3. IDT49C460 Cascaded Mode "Memory Read"
checkbit words' from each slice to obtain a complete checkbit
word. Once this is done the syndrome can be computed by
XOR-ing the 8 input checkbits with the 8 (complete) generated
checkbits as usual. Thus,
Final Syndrome = (CBO-7) E!:J (8 checkbits generated from
64-bit data)
= (CBO-7) E!:J [(PCB_lsO-7) E!:J (PCB_usO-7))
= [(CBO-7) E!:J [(PCBJsO-7)) E!:J PCB_usO-7)
1
1
1
1
1
lower slice
1
1_ _ _ _ _ -1
1
upper slice
The first two terms constitute the partial syndrome. In the
IDT49C460, the first XOR is done in the lower slice and the
result is output on the SCO-7 bus of the lower slice. The
second XOR is done in the upper slice and the (final syndrome) result is output on the SCO-7 bus of the upper slice.
This final syndrome is then fed back to the lower slice. It must
be made available in both slices in order for a correction of
either DataO-31 or Data32-63 to be possible.
USING THE IDT49C465 IN 64-BIT
OPERATIONS
In the IDT49C460 the partial checkbits and partial syndrome are output multiplexed on the same bus. In the
IDT49C465, however, these are available on separate buses.
During a 'memory write', the partial checkbits from the
lower slice are output on the CBO bus of this slice. They are
fed to the PCBI bus of the upper slice. The final checkbits are
available on the CBO bus of this upper slice.
While doing a 'memory read' or detecVcorrect, the partial
syndrome (XOR of input checkbits and checkbits generated in
that particular slice) is output on the SYO bus. It is fed to the
CBI bus of the upper slice. In this slice, this partial syndrome
is XOR-ed with partial checkbits generated in this upper slice
to produce the final syndrome. Simultaneously, the partial
checkbits produced in the upper slice (from upper 32 data bits)
are sent back to the lower slice. They are then XOR-ed with
the partial syndrome already available in the lower slice
producing the final syndrome in the lower slice as well. Thus,
the final syndrome is simultaneously generated in both slices
of the IDT49C465 cascade.
125
CASCADING THE IDT49C460 AND IDT49C465
APPLICATION NOTE AN-96
Partial Checkbits
LOWER SLICE
UPPER SLICE
CBIQ-?
==>H-~~~~
---I~
DATAinQ<=>.\4-.........
_ _ _..J
SCQ-?
Syndrome Register
Final Syndrome
49C465
Syndrome Register
32-bit EDC
49C465
32-bit EDC
2530 drw04
Figure 4. IDT49C465 Cascaded Mode EDC Operation
SUMMARY
As system bus widths continue to grow, cascading EDCs
may be necessary. This application note clearly explains the
basic principle behind cascading EDCs. It also describes the
cascading support available with two 32-bit IDT EDC chipsthe IDT49C460 and the IDT49C465.
126
~
f;y
CONFERENCE
PAPER
CP-10
INTEGRATED LINE
TERMINATION SOLUTIONS FOR
HIGH-SPEED LOGIC
Integrated Device Technology, IDC.
By: Stanley Hromk
As logic speeds increase, there is an increase in noise
generated by faster edge rates. To reduce noise emissions
and generate cleaner waveforms, it is often necessary to
terminate signal lines. The need for termination becomes
more pronounced when the signals are driven over longer
lines, smaller width traces, across backplanes, or at higher
frequencies. Properly terminated lines will also reduce noise
on the power distribution system which may ease board layout
and decoupling.
Termination with external components increases part count,
cost and the complexity of board designs. In addressing this
problem, component manufacturers have integrated termination schemes into the output buffers of interface circuits which
greatly eases the board level design and layout task. By
utilizing these traditional and integrated line termination
schemes, designers have the ability to increase system performance and reduce costs.
THE NATURE OF THE PROBLEM
With the new families of high speed logic, internal propagation delays have been reduced to the point that the external
interface accounts for most of the component propagation
delay. In order to increase device speed further, the edge
rates and drive capabilities of the devices have been increased. These faster edge rates are adding higher frequency components to the frequency spectrum of the transmitted signal. If the rise/fall time of the signal is shorter than the
round trip propagation delay in the signal path, the signal path
will act like a transmission line and need termination. The
edge rate on high speed logic can be faster than 1 voltlns. A
commonly used equation to determine the maximum
unterminated trace length is as follows:
L
TRADITIONAL TERMINATION SCHEMES
The following cursory review of the traditional termination
methods gives insight into the benefits and drawbacks of each
scheme.
Parallel or Shunt Termination:
Parallel termination is the addition of a line matching
impedance at the receiver as shown in Figure 2. When the
charge from the signal reaches the receiving end of the line,
the resistor will drain off excess charge preventing reflections.
Figure 2. Transmission Line with Shunt Termination
---IL
=
To maintain good signal quality on a transmission line, the
dynamiC impedance of the transmission line needs to be
constant throughout the line. This means that stubs,
unterminated lines and very low source impedances can all
contribute to poor signal quality. When a signal passes down
a transmission line, if it sees a continuous impedance, it will
travel smoothly without reflections. If there are abrupt changes
in the impedance at any point in the transmission line, reflections will bounce off of these points and may cause noise if
uncontrolled. In designing the transmission line it is best to
utilize a single line from source to load. It is acceptable to drive
a distributed load by daisy chaining the loads and avoiding
stubs. If there is a low impedance load to be driven, it should
be at the end of the transmission line.
2Tpd
Thevenin Termination:
Tr = Rise/fall time of the signal (ns)
Tpd = Propagation delay of the transmission line (ns/ft)
L = Maximum Unterminated Cable Length (It)
The Thevenin Termination balances the DC loading on the
driver between the logic high state and the logic low state
reducing Signal distortion. In this scheme, there is a path for
DC current to pass directly from the Vcc to Gnd through the
termination resistors which will dissipate power regardless of
the state of the output driver including the high-impedance
state.
f,t>-
I
I
I
I
I
I
R1
~~'
+i I I I Ii
Figure 1. Transmission Line
;;;:-
;;;:-
;;;:-
R2
;;;:-. ;;;:-
3014 drw 03
Figure 3. Transmission Line with Thevenin Termination
The lOT logo is a registered trademark of Integrated Device Technology, Ino.
9/92
©1993 Integrated Device Technology, Inc.
127
INTEGRATED LINE TERMINAL SOLUTIONS FOR HIGH-SPEED LOGIC
RC Termination:
An effective method of termination is the RC termination
using a 47pf to 200pf capacitor in series with a resistor to
ground at the receiver. Larger capacitors give a cleaner
waveform but consume more power at high frequencies than
lower valued capacitors. The resistor value should equal the
characteristic impedance of the transmission line.
3014 drw 04
Figure 4. Transmission Line with RC termination
RC termination is very effective for point to pointtermination
over long distances because the signal passes down the
transmission line and does not reflect. This makes it possible
to use RC termination in cases where the propagation delay
of the transmission line exceeds the cycle time of the driving
Signal. With the AC coupling at the terminating end, there is
no DC power consumed by the termination making the scheme
useful for low power applications.
CONFERENCE PAPER CP-10
As the output driver undergoes a transition, the voltage is
divided equally between the output impedance (driver and
resistor) and the transmission line, as shown in Figure 6.
Because ofthe matched source impedance, the voltage at the
receiver builds up to a level equivalent to the driving voltage
and will reflect the signal back from receiver to source and
eventually allow a full voltage transition at the source as
shown in Figure 6.
Series termination is the simplest, most effective form of
reducing signal noise in transmission lines. This method
consumes no DC power and helps to reduce dynamic power
consumption. Series termination is the only method that
handles stubs well and reduces ground bounce. In situations
in which the loads on the transmission line are highly capacitive, the series termination may cause time delays due to the
RC time constants.
Summary of Traditional Schemes
A relative comparison of the attributes of the four traditional
termination schemes is summarized in Table 1.
FEATURES OF THE FOUR TERMINATION
SCHEMES
Characteristic
Series Termination!l):
~
1
I= I I=
I
I
3014 dlW 05
Figure 5. Transmission Line with Series Termination
Series termination is the addition of a resistor between the
component output and the transmission line as shown in
Figure S. The combination of the series resistor and the
source impedance of the driver act to match the characteristic
"
\\.._ _ _ _ _-11
I
I
1
~~
I
I
"I
I
I
Signal at transmitting e n d :
I
I
:
:
I
I
\ rI
Signal at receiving end
RC
Series
4
1
1
Dynamic Power Dissipation
4
3
2
1
4
4
3
1
1
Works with Stubs
3
2
1
Distributed Load Driving
1
1
1
2
Parts Count for Termination
1
2
2
1
Works With Heavy
Capacitive Loads
1
1
1
2
Good for Low·lmpedance
Backplanes
1
1
1
Works with Tpd > Data Rate
1
1
1
2
2
Ibl01
INTEGRATED SERIES TERMINATION:
impedance of the trace.
Open Circuit
\
Signal at Transmitter
Thev
3
Signal Distortion Due to
Unbalance
Iii>-=
-
Shunt
Static Power Dissipation
I
1 ' - - - - - - . . . J , 3 0 1 4 drw06
Figure 6. Signals Produced When Using a
Series Terminator
Improvements to the series method can be gained if the
series resistor is integrated into the driving component. By
integrating the resistor, the output impedances of the driver
can be matched to the typical load of a transmission line in
both the high and low going cases. Properly designed
integrated schemes can outperform external resistor terminations by reducing source follower problems and increasing
output drive current. The removal of the external resistors will
also reduce part count.
Figure 8A shows a high drive, MOS output structure without
any integrated termination. In most component designs with
this configuration, the impedance of the pull-up is higher than
that of the pull-down. Especially important is the fact that the
pull-up loses drive as the output voltages approaches the SV
supply on a low-to-high transition, whereas the pull-down
transistor will not suffer this affect on a high to low transition.
128
INTEGRATED LINE TERMINAL SOLUTIONS FOR HIGH-SPEED LOGIC
CONFERENCE PAPER CP·10
Figure BB shows the same structure with an integrated a
series resistor on the output. The effective pull·up and pull·
down impedance is now matched better to the line, but the
pull-up impedance still remains higher than the pull-down
impedance. More importantly, because this configuration
creates a source follower, the series resistor exacerbates the
relationship between the output voltage and the loss of pull-up
drive. An integrated series resistor, directly connected to an
output pin, if not properly designed into the component, can
easily be damaged by system transients.
An additional reason for line termination problems in high
speed logic is the fact that some drivers have different drive
capability between the high going and low going signals. This
makes it difficult to impossible to make a perfectly matched
transmission line when the signal has different driving impedances for the two states. To avoid this problem many of the
new components that have internal resistors also have a
balanced drive capability so that both high going and low going
signals demonstrate the same output impedance. Limiting the
pull down drive capability of the device also reduces problems
with undershoot, ground bounce and general noise generation. Reducing these problems will make the whole task of
termination easier.
--l
Benefits of Integrated Series Termination
--l
FIG BA
FIG BB
FIG BC
1) Captures all of the benefits of external series termination
a) No static power consumption
b) Reduces dynamic power consumption
c) Moderately good for stubs
d) Noise reduction over other termination methods
e) Reduces component ground bounce
2) Balanced drive produces less signal distortion
3) No external components are needed for termination
a) Reduced part count, inventory, and costs
b) Easier board layout
4) Terminated parts are pin compatible with non terminated
parts
a) Plug in replacement.
b) No new CAD models
5) Higher drive capability than when using external series
resistors
FIGBD
Figure 8. Various Integrated Output Configurations
Placing the series resistor in the drain of both transistors as
shown in Figure BC alleviates the problems with the source
follower created in configuration of BB. The configuration in
BC will provide good balanced drive and good line termination
for both high to low transitions and low to high transitions. The
value of the resistors can be adapted to match the line
impedance without having to make compromises for the
opposite transitions. Despite this, the resistor in the drain of
the pull down N channel transistor is still exposed to the output
pin and may short if stressed.
In Figure BD the resistors are sized and placed in the drain
of the pull-up and the source of the pull-down transistors to
provide good balance between the two paths. The resistors
are isolated from the external pin and are now protected
against shorting. An added advantage is that a lower value
resistor can be used to generate the same drive current that
can be generated with a higher value resistor used in configuration BC.
Several IC manufacturers have introduced components
with integrated series resistors. Each of the configurations
shown in figure B is available from at least one source.
Balanced Output Drive Capability
(m.
Disadvantages of Integrated Series Termination
1) Captures some of the disadvantages of external series
termination
a) May not drive very low impedance backplanes
b) May not have first incident wave switching with
distributed loads
2) Some components are susceptible to damage (Check with
manufacturer).
CONCLUSION
Olthe methods of termination available, the series termination works best in most applications, especially those situations utilizing shorter distances. Other termination methods
have applications in which they will work best, but their overall
performance is not as good as series termination in board
level applications. When integrating the series resistor into
the line driving component there are improvements that can
be seen over the use of an external resistor, but careful
consideration needs to be given to how the resistor is integrated to achieve optimum results.
(1) "Series Termination," Application Note 50, 1990/91 Logic
Data Book, Integrated Device Technology.
3014 drw 08
Note: This paper was presented at Electro192, May 12, 1992
Figure 9. Balanced Drive Output
129
~
GJ
~
NEW OUTPUT STRUCTURE
DESIGNS REDUCE SYSTEM
NOISE PROBLEMS
CONFERENCE
PAPER
CP-11
Integrated DevIce Technology. Inc.
By Stanley Hronlk
INTRODUCTION
The new high-speed logic families available in the market
place are capable of much higher data rates than earlier
families. This is due to a combination of shorter propagation
delays in the parts. faster output edge rates, and reduced
output switching voltages compared to the CMOS switching
levels. These component changes are requiring strict
adherance to the design rules to maintain signal integrity. To
assist designers in the task of maintaining high speed, low
noise operation, many component manufacturers are developing new output structure designs to assist in signal waveform control.
The output structures of the new devices are designed to
control internal chip noise and to treatthe attached circuitry as
a transmission line. Three of the techniques to accomplish
this are adjusting the output voltage levels, controlling the
output edge rate, and reducing reflections in the transmission
line. Each of these techniques will lower the drive current
surge in the device output structure which will also assist in
controlling ground bounce and Vcc bounce.
Reducing the output voltage swing from CMOS levels to
TTL levels allows the signal to acquire state more quickly. The
lower voltage swing will reduce the charge dumped into the
transmission line which will reduce the energy and noise in the
signal transmission. The output edge rate control and the
transmission line effects are interrelated and must be approached as a unit.
TRANSMISSION LINE EFFECTS
DUE TO FAST EDGE RATES
To determine if a transmission line effect is present, the
equation in Figure 1 may be used to determine the maximum
unterminated trace length. The equation states that if the risel
fall time of the signal is shorter than the round trip propagation
delay in the signal path, the signal path will act like a transmission line and need termination. As an example, lOT's FCT-T
family has an edge rate of less than WIns which will require
termination on any trace that is over approximately 3 inches.
Because of the speed of newer logic families, the need for
proper termination is becoming universal. To simplify board
designs a few manufacturers are integrating termination
schemes into the output structure of their devices to overcome
the need for adding additional termination to the board. By
integrating termination schemes into the output structure of
the components,other signal quality improvements can also
be obtained. To establish the benefits of integrated termination schemes, a few transmission line characteristics need to
be understood.
V
Tf = Rise or Fall Time
Tpd = Delay or Transmission Line Per Unit Length
L = Length of the Transmission Line
L> Tf
2Tpd
If the equation is true,
the line is transmissive
and may need termination
Figure 1. Transmission Line
TRANSMISSION LINE PROBLEMS
To maintain good signal quality on a transmission line, the
dynamic impedance of the transmission line needs to be
constant throughout the line. This means that very low source
impedances, stubs, and high-impedance receivers without
line matching termination can all contribute to poor signal
quality. If there are abrupt changes in the impedance at any
point in the transmission line, reflections will bounce off these
points and may cause noise. In designing the transmission
line it is best to utilize a single line from the source to the load
by daisy chaining distributed high impedance loads and
avoiding stubs which cause impedance mismatches. If lowimpedance loads are to be driven, they should be at the end
of the transmission line opposite the source.
When a driver changes output state and sends a signal
down the transmission line, the driver will sense the transmission line but does not have the capability to sense the load at
the far end of the line until the signal has had a chance to travel
down to the load and reflect back. Because of this the driver
for high-speed signals which meet the requirements of the
equation for a transmission line as shown in Figure 1 should
be optimized to drive the transmission line and not the load.
A transmission line has the same impedance for both highgoing and low-going signals. Contrasting this, most transmission line drivers have different drive capabilities in the high and
low going directions making it difficult to maintain a high signal
integrity for both transitions because of the impedance mismatches between the two directions.
The lOT logo is a registered trademark of Integrated Device Technology, Inc.
©1993 Integrated Device Technology, Inc.
130
5/92
NEW OUTPUT STRUCTURE DESIGNS REDUCE SYSTEM NOISE PROBLEMS
CONFERENCE PAPER CP-11
Series Termination
One of the most successful methods of dealing with transmission line effects is the use of series termination. Series
termination is the addition of a resistor between the component output and the transmission line, as shown in Figure 2.
The combination of the series resistor and the source impedance of the driver act to match the characteristic impedance
of the trace or transmission line.
Open Circuit
1:
\ ..._ _ _ _ _ _ _....
Signal at transmitting end
Signal at receiving end
I=- I-= I-=
1
~
Signal at Transmitter
\
I
,~------~,
! drw 02
I
drw03
Figure 3. Signals Produced When Using a Series
Terminator
Figure 2. Transmission Line with Series Termination
As the output driver undergoes a transition, the voltage is
divided between the output impedance (driver plus the resistor) and the transmission line, as shown in Figure 3. If the
output impedance matches the impedance of the transmission line, the output waveform will develop a step at 50% of the
voltage transition. If the impedances are not matched, the
voltage will divide proportionately to the impedances. To
achieve first incident wave switching, the source impedance
should be slightly lower than the impedance of the transmission line so that the step appears after crossing the logic
threshold of the receiver.
After the driver makes a transition, the signal will propagate
down the transmission line and strike the far end. Upon
reaching the far end, the signal will look for an impedance
matching that of the transmission line. Since the receiver is
usually a high-impedance input, the voltage will build up at this
point from the current flow until the voltage level has reached
a high enough level to counter the inductive nature of the
transmission line. If the source impedance matches the line
impedance and there were no losses, the voltage would build
to twice the driving voltage. At this point, the matching
impedance is seen back on the transmission line and the
signal will propagate back down the transmission line to the
source. Since the driving voltage was about half of the final
state voltage, this will bring the voltage in the entire transmission line to the proper level, as shown in Figure 3.
If a designer has a distributed load, and the step voltages
shown in Figure 3 do not cross the logic threshold of the daisychained load, first incidentwaveswitching may not be achieved.
This can be countered by slightly reducing the series resistance values to adjust the step voltage levels so that the steps
occur beyond the logic thresholds and first incident wave
switching can be guaranteed. This will tend to overdrive the
transmission line, but countering this effect will be the "lossy"
nature of the line. The series resistor significantly cuts the
drive current into the line alleviating most noise problems at
the source. Resistive and capacitive elements of the transmission line will absorb portions of the charge which will
quickly quiet the signal.
131
Using the series resistor limits, the charge that the source
passes into the transmission line reduces the drive current
surge of the source. This also reduces the need to dissipate
the energy from the charge after the transmission line has
reached full voltage levels which will reduce noise spikes on
the line, cross talk, power dissipation, noise problems in the
power distribution system, and reflection problems.
In most situations, series termination is the simplest, most
effective form of reducing signal noise in transmission lines.
Series termination consumes no DC power, helps to reduce
dynamic power consumption, reduces ground bounce and
handles stubs better than most end of the line termination
schemes.
INTEGRATED SERIES TERMINATION
Benefits can be received by integrating the series resistor
into the output structure of the driving component. By integrating the resistor, the output impedances of the driver can be
matched to the typical load of a transmission line for both the
high and low going signals, which is not possible with external
termination. Properly designed integrated schemes can outperform external resistor terminations by reducing source
follower problems and increasing the output drive current.
The removal of the external resistors will also reduce part
count. To demonstrate the effects of various output structures, a review of several output configurations will be given.
NEW OUTPUT STRUCTURE DESIGNS REDUCE SYSTEM NOISE PROBLEMS
CONFERENCE PAPER CP·11
Figure 4. Totem Pole output structure with an N channel pull
up transistor. This structure is excellent for backplane
driving and low impedance loads.
Figure 6. Drain resistors overcome the gain problems with
the external resistor.
The configuration in Figure 4 shows a totem pole structure
with N channel FETs in both the pull up and pull down
positions. The pull up FET requires a Gate to Source turn on
voltage of about 1.5V which will drop the typical loaded output
voltage to less than 3.5V giving TIL level outputs. In this
configuration, the impedance of the pullup is typically higher
than that of the pulldown, giving unbalanced drive capabilities
in the two directions. With lOT's High Drive components that
contain this configuration, the impedance is usually about
60hms pull down and 220hms pull up. This structure gives
excellent drive capability for low-impedance backplanes and
heavy loads that contain external termination.
PlaCing the series resistor in the drain of both transistors, as
shown in Figure 6, alleviates the problems with the gain
created in the configuration of Figure 5. The value of each
resistor can be adapted to match the line impedance, thus
giving similar drive currents in both directions without conflicting with the opposite transition. The configuration in Figure 6
will provide a good balanced drive capability and good line
termination for both high-to-Iow transitions and low-to-high
transitions.
In Figure 7, the resistors are sized and placed in the drain
of the pull-up and the source of the pull-down transistors. With
this configuration the same results as shown in Figure 6 can
be achieved by properly sizing the resistors. lOT uses this
structure in the Balanced Drive IDTFCT162xxx family.
Figure 5. Totem Pole with a series resistor which simulates
the addition of an external series resistor.
Figure 7. A drain pull up and source pull down allow better
drive in the pull down (IDTFCT162xxx).
Figure 5 shows the same structure with a series resistor on
the output. The effective output impedance is now matched
more closely to the line, but the pull-up impedance remains
higher than the pull-down impedance. Because the series
resistor degrades the gate to source voltage drop in the pull
up FET, the pull up drive capability is reduced, significantly
increasing the effective impedance beyond the value of the
resistor. The pull down drive is not affected by gate to source
degradations. This creates an unbalanced condition, where
the pull up drive capability is much lower than the pull down
drive strength. The pull up may degrade to an impedance of
over 1OOohms when utilizing a 250hm resistor while the pull
down will remain at about 31 ohms with the same resistor. This
problem will be experienced either when an external series
resistor is used or when the resistor is integrated into the
output structure of the device.
Using resistors in the output structure of Figure 7 provides
a natural internal current limiting capability to the component
which will then allow a restructuring of the driving stage. By
doing this it is possible to speed up the internal logic of the
component to where the output switching will begin more
quickly than is possible with the other configurations shown.
Driving Capacitive Loads
In situations in which the loads on the transmission line are
highly capacitive, the use of series termination may cause
time delays due to the RC time constants. When using lOT's
Balanced Drive components, this problem is reduced because of the lower output impedance, quicker response time,
and controlled edge rate. lOT's Balanced Drive and High
132
NEW OUTPUT STRUCTURE DESIGNS REDUCE SYSTEM NOISE PROBLEMS
Drive components have very similar response times for capacitive loads of less than 300pf. Because of its quicker
response, the Balanced Drive part will switch faster than a
High Drive part for loads of less than 200pf. As the load
increases above 200pf, the High Drive part will respond more
quickly because of its lower output impedance. Despite these
minor differences, the differences in the effects of capacitance
on propagation delay between the High Drive and Balanced
Drive parts should be less than O.Sns for any load of less than
300pf. The capacitive derating curves are shown in Figure B.
CONFERENCE PAPER CP-11
both directions, limiting surge current into the transmission
line, butstill providing sufficient drive currentto drive all except
the most demanding loads. Limiting the pull down drive
capabilityofthe device during transitions also reduces problem s
with undershoot, ground bounce and general noise generation. During steady state DC conditions, IDT specifies the
static drive capability of the devices at 24ma worst case in both
directions as shown in Figure 10.
Delay vs Capacitive Load
8~r-----~----~----------------,
7
6
5
drw09
tpd (LH)
3
Figure 9, Dynamic Balanced Drive Output
o
50
100
150
200
250
300
350
Capacitive Load (pi)
400
drw 08
Figure 8, Capacitive Derating for
Double Density Balanced Drive and High Drive
When the capacitive load is larger than 400pl at high
switching speeds, the load will begin looking like a direct short
upon switching and may begin to overdrive the output of both
the balanced drive and high drive part. The power dissipation
equation is P =fCV 2 and should be used to calculate the power
consumption for each pin to assure that the total power
dissipation in the device does not exceed the maximum rated
limits. To avoid exceeding the limit for heavy capacitive loads,
a 1000hm series resistor can be used to limit the current to
acceptable levels.
Balanced Drive Capability
The output structure of the Balanced Drive part has been
specifically designed to give similar transition times with
matching absolute edge rates in both the high-going and lowgoing directions. This means the IDT Balanced Drive family
has a matched dynamic drive capability for driving transmission lines, but still has sufficiently low static output impedance
to maintain state during during steady state conditions. As
shown in Figure 9, during transitions, the Balanced Drive
output structure will current limit at about 11 Oma, typical for
~
~
~
~
F
drw 10
Figure 10. Static Balanced Drive Output
Adding External Resistors to Balanced Drive
With the Balanced Drive components, the effective series
termination impedance of about 220hms is slightly lower than
the characteristic impedance of most transmission lines.
Backplanes may sometimes approach levels as low as 300hms,
but most lines will have a higher impedance. Despite this
difference, the current surge driven into the transmission line
will be limited by the output impedance and controlled edge
rate. This will usually be sufficient to provide quiet operation
without the addition of additional termination.
If it is desirable to further enhance the quiet operation and
to achieve a close match between the source impedance and
the line impedance, the user may add external resistors to the
output of his balanced drive parts. Because of the integrated
resistor in the drain of the pull up FET in the Balanced Drive
part, the addition of an external resistor will not degrade the
gate to source voltage to the extent that the gain degradation
133
NEW OUTPUT STRUCTURE DESIGNS REDUCE SYSTEM NOISE PROBLEMS
would take place with the standard TTL output of figure 4 for
equivalent total resistance values. The voltage drop across
the drain resistor will increase the gate to source voltage,
partially countering the effect of the external series resistor
and retaining some of the balanced drive attributes. As a
result, adding an external resistor to a Balance Drive part will
not cause a significant impedance mismatch between the
high-going and low-going signals, as happens with normal
TTL output components.
CONFERENCE PAPER CP-11
CONCLUSION
Utilizing the Balanced-Drive family in high-speed bus driving applications will solve most of the problems with noise and
line termination experienced with traditional high-speed, low
output impedance line drivers. The Balanced Drive logic
family provides the benefits of series termination on signal
lines while avoiding many of the drawbacks of adding external
series termination resistors. The Balanced-Drive family of
devices from IDTwili generate lower levels of noise than other
components in the same speed grade, solve many of the
termination line problems encountered by the designer, reduce power consumption and give superior performance to
other high-speed logic. Balanced Drive is the logic family of
choice for most applications.
134
~
CONFERENCE
PAPER
CP-12
DOUBLE-DENSITYTM LOGIC:
THE FAST, FLEXIBLE
LOGIC FAMILY
GJ
L/
Integnoted Device Technology,lnc.
By Wayne T. Yoshimoto
Double-Density is comprised of three distinct versions:
ABSTRACT
This paper discusses how the FCT-T Double-DensityTM
Logic family addresses the problems faced by PC designers.
With microprocessor frequencies rising both in desktops and
portables, logic must also rise in performance, but still maintain good noise and power characteristics. High speed/low
noise operation for speed-critical paths and high speed/low
power operation for battery operated systems are ideal for the
designer. Since space is a premium both in portable and
desktop PCs, high speed, low power, and low noise must be
combined with small packaging.
INTRODUCTION
16XXX
162XXX
163XXX
Balanced
64MA
Output Drive 1-----1 Output Drive
3.3V
on Chip Resistors
drw01
Figure 1. Double-Density Versions
The high-drive version (FCT16XXX) provides-32mA/64mA
(Ioh/lol) drive with ground bounce typically less than 1V.
Power-off disable is supported for "live" insertion in fault
tolerant systems. This version is a drop-in upgrade for ABT
and ACT WideBus™ meeting or exceeding all DC specifications.
The balanced drive version (FCT162XXX) provides-24mN
24mA (Ioh/lol) drive with integrated series terminating resistors. This reduces ringing/undershoots and ground bounce is
typically less than .6V. These are pin-compatible with the
high-drive family providing easy upgrade.
The 3.3V version (FCT163XXX) is deSigned to meet the
JEDEC LVTTL standard for 3.3V operation, not a
recharacterized or derated 5V device. It provides a drive of 8mA/24mA (Ioh/lol) and ground bounce typically less than
.3V. A number of unidirectional and bidirectional translators
are part of this group also to provide solutions for mixed 3.3VI
5V hybrid systems.
All three versions of the family are well suited in the
following categories and thus provide solutions for PC designers of different types of systems.
The level of integration and the rise in frequencies of the
microprocessor has had an enormous impact on the PC
marketplace. The performance attained only by huge mainframes 15 years ago can now be realized on the desktop.
Similarly, the performance and battery life attainable 10 years
ago in a 25 pound monster is today far surpassed by a 5
pound, 386-class machine. Correspondingly, the interface
logic (buffers, latches, transceivers, etc.) surrounding the
microprocessor has gone through significant improvements.
Designers are beginning to realize that the older families of
interface logic no longer meet the needs of today's and
tomorrow's PCs.
Identified shortcomings are in the areas of speed, power
consumption (both static and dynamic), packaging, and noise.
For example, in a desktop PC running at 50MHz, designers
were forced to look elsewhere instead of the popular, butslow,
"F" or "AS/ALS" families which were adequate for a 25MHz
design. In the case of the newest notebook PCs, designers
need to replace the slow "HCT" and high power "ACT" families. Newer families of logic, such as FCT-T Double-Density
Logic, can provide designers of both high-performance desktops and low-power notebooks with the best of both worlds, as
well as new capabilities, such as 3.3V operation.
In order to keep up with the ever-increaSing frequencies of
the microprocessor, logic products are constantly pushed to
attain faster and faster speeds. Today, with the systems
running at 50MHz, logic products with delays of less than 5ns
are desirable.
FCT-T DOUBLE-DENSITY DEFINED
PERFORMANCE OF LOGIC FAMILIES
FCT-T Double-Density is one of the IDT families of highperformance CMOS logic. It is comprised of 16-, 18-, 20-bit
wide, extra-quiet, very-low-power, high-performance bus interface logiC products. Double-Density is an extension of
IDT's earlier family of octal FCT -T devices. Microprocessors'
buses have moved beyond 8-bits, creating the need for wider
bus interface devices. With the wider devices, partcount is
minimized as well board area.
PERFORMANCE
245 Transceiver
ACT
-
-
FCT-T Octal
3.8ns
4.1ns
4.6ns
7.0ns
DD High Drive
3.8ns
4.1ns
4.6ns
7.0ns
DD Balanced Drive
3.8ns
4.1ns
4.6ns
7.0ns
4.6ns
7.0ns
FAST
ABT
is a trademark of Integrated Device
Std-Speed
-
ASiALS
Double~Oensity
-
-
DD3.3V
The lOT logo is a registered'trademark: and
Technology, Inc.
O-Speed C-Speed A-Speed
HCT
-
-
29ns
9.0ns
7.0ns
-
-
7.5n5
-
-
4.6n5
IbIOt
5/92
©1993 Integrated Device Technology, Inc.
135
DOUBLE-DENSITY LOGIC: THE FAST, FLEXIBLE LOGIC FAMILY
CONFERENCE PAPER CP-12
FCT-T Double-Density provides the performance necessary for today's high-performance systems with the power
consumption one would expect from CMOS technology. With
future systems in mind, lOT has recently announced D-speed
logic. AD-speed '244 buffer specifies a maximum of 3.6ns
propagation delay. This is ideal for high-performance, 75Mhz
and 100Mhz, workstations and 67Mhz+ P5 designs.
Logic has come a long way from the days of LS, TTL, and
even HCT. A comparison of the old and new generation of
logic is shown in Table 1.
60mA
90mA
90mA
~ ICCZ
~ ICCH
IS:'! ICCl
POWER
Running at high frequencies is not without its drawbacks.
Since the amount of power dissipated by CMOS is proportional to the frequency, high-frequency operation also means
high power. Figure 2 compares the dynamic power consumptions versus frequency of several logic families. As illustrated
by the graph, Double-Density provides better power characteristics at all frequency points benefiting both the desktop
(high-drive family) and the notebook (balanced drive/3.3V
family) designer.
20
0
~
.s
Iz
w
a:
a: 10
::>
0
0
..J
~
0
I-
0
20
30
40
FREQUENCY (MHZ)
50
drw 02
Figure 2. Dynamic Power Comparison
Dynamic power is important when the system is active.
During inactivity, static power consumption becomes equally
important. The CMOS technology families on the graph,
Double-Density and ACT, benefit from very low static power
consumption on the order of a few microamps. On the other
hand, the other families, FAST (bipolar) and AST (SiCMOS),
suffer from high-static-power consumption. See Figure 3.
FCT16245
Double Density
ABT16245
Widebus™
FASfTM
(two octals)*
drw03
Figure 3. Static Power Comparison
NOISE
Noise issues came to the forefront with the introduction of
the first generation of fast CMOS logic in the mid-eighties.
Most of these issues were smoothed out by the second
generation, with the inclusion of output edge rate controls and
reduced output swings. In addition, designers were aware of
high-speed design techniques such as series termination and
transmission line effects. The Double-Density family makes
ground bounce and noise non-issues.
The 48-/56-pin SSOP package provides multiple Vcc (4)
and Ground (8) pins forthe entire family of 16-bit wide devices.
See Figure 4 for the pinouts of a 48-pin SSOP package. As
a reSUlt, the high-drive version specifies typical ground bounce
of less than 1V. The balanced-drive version takes advantage
of series termination to reduce noise. They provide integrated
series resistors, bringing the typical ground bounce specifications even lower, to less than .6V. The 3.3V version specifies
a typical ground bounce of less than .5V due to a smaller
output swing of about 3.0V.
10E
101
102
GND
103
104
vee
105
106
GND
107
108
201
202
GND
203
204
vee
205
206
GND
207
208
20E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
lLE
101
102
GND
103
104
vee
105
106
GND
107
108
201
202
GND
203
204
• Flow-thru Pinouts
• 4 Vccs, 8 Grounds
• 25-mil pin pitch
vee
205
206
GND
207
208
2LE
Figure 4. SSOP Package
136
drw04
DOUBLE-DENSITY LOGIC: THE FAST, FLEXIBLE LOGIC FAMILY
CONFERENCE PAPER CP-12
Double-Density family specifies output skew at typically less
than 2S0 ps, and guaranteed less than SOO ps. These characteristics allow the IDT74FCT16240/244 to be used as
minimum skew clock drivers.
SSOP
SO-56
ill
0.504
ITl
~
[]06~ Dl7~
~
14-
3.3V OPERATION
3.3V operation will provide the next step in portable computing. Lighter, smaller, and longer lasting systems will be
possible. For example, a 7" x 9" x 2", 4 pound, eight-hour
system will be possible in the near future. IDT is ready for the
conversion to a 3.3V supply voltage with the 3.3V DoubleDensity family of bus interface functions, key "glue" logic
elements, and 3.3V to SV interface components. This family
will allow designers to develop complete 3.3V or mixed supply
3.3V/SV systems. These devices have been designed to
operate from a regulated 3 .3V supply for optimal performance
and are not simply "recharacterized" or "derated" SV CMOS
parts. Thus, they are able to maintain sub-Sns propagation
delays for high-performance portables. See Table 3 for a
summary of IDT's 3.3V Double-Density offerings.
~
0.406
0.406
0.409
drw 05
Figure 5. SOIC vs. SSOP Package Comparison
SOIC VS. SSOP PACKAGE
(2) 20-pin
SOIC
(1) 48'pin
SSOP
(1) 56-pin
SSOP
Area
(sq. Inches)
0.474
0.254
0.295
Body Width
(Mils)
0.300
0.300
0.300
Area
(Normalized)
DOUBLE-DENSITY 3.3V OFFERINGS
1.00
0.536
0.523
tbl02
PACKAGING
Packaging is rapidly becoming an important consideration,
due to the integration and size limitations of today's systems.
Luckily, packaging technology has not been a limiting factor.
Today's highly integrated boards in desktop and notebook
PCs have been a result of new packaging technologies. The
Double-Density family is packaged in a 2S-mil pin pitch 48-/
S6-pin SSOP package (refer to Figure 4 in the last section). A
comparison of the SSOP package versus the standard SOIC
package can be seen in Figure S.
A 47% area-savings can be realized when using the 48-pin
SSOP package versus a 20-pin SOIC package. Future packaging capabilities are currently being studied. After all, the
trend is toward smaller and smaller packages. Some of the
alternatives are: a 21 O-mil wide, 19.6-mil pin pitch package or
a 1S0-mil wide, 19.6-mil pin pitch package or a 1SO-mil wide,
1S.7-mil pin pitch package. The area savings versus the
current SSOP package is 41%, S4%, and 62% respectively.
This decision can not be made in a vacuum, since
manufacturability must be considered. As the pin pitch and
overall package size shrinks, fewer board manufacturers are
able to handle production without large investments in new
machinery. These considerations will weigh heavily upon
where the next step in packaging will be.
SKEW
Skew is defined as the absolute value of the difference
between the actual propagation delays for any two separate
outputs of the same device. With processor clock frequencies
migrating to SOMHz and 67MHz+, any delay due to skew
increasingly becomes a percentage of the clock period. The
137
Part #
Function
Avail
FCT163244
Buffer/Line Driver
NOW
FCT163245
Bidirectional Transceiver
NOW
FCT163373
Transparent Latch
NOW
FCT163374
Register (3·State)
NOW
FCT163501
Registered Transceiver
NOW
FCT163646
Transceiver/Registers
NOW
tbl03
High-speed desktops and fileservers will also benefit from
3.3Voperation. Their large memory requirements will force
the use of large density DRAMs, 16Mb and 64Mb. Due to the
gate geometries of these dense memories, a 3.3V supply
voltage will be necessary. Also, at greater than SOMHz, these
high-speed systems will benefit from the reduced swings in
terms of performance and noise.
3.3V/5V TRANSLATION
Using mixed supply systems will be a necessary transitional
phase between the current 5V systems and the upcoming full
3.3V systems. Technological and performance limitations will
slow down the conversion of some functions to 3.3V. Therefore, designers must understand the compatibility issues of
interfacing between 3.3V and SV components, as well as what
translation functions are available today.
IDT's 3.3V Double-Density family is designed such that any
input pin (except I/O) can take an input voltage up to 7V. This
feature allows these 3.3V devices to be directly driven by a SV
device. This also allows the unidirectional parts, i.e.
FCT163244, FCT163373, FCT163374, to act as one-way SVto-3.3V translators. The unidirectional translators accept
TTL-or CMOS-compatible signals from SV components at the
inputs, and provide TIL-compatible output levels. These
translators avoid any problems associated with a direct interface between a SV component and a 3.3V bus.
DOUBLE-DENSITY LOGIC: THE FAST, FLEXIBLE LOGIC FAMILY
CONFERENCE PAPER CP-12
Since not all bus interface applications are unidirectional,
there also needs to be bidirectional solutions to the 3.3V to 5V
interface. A solution to this is the FCT164245T. This part
interfaces between a 3.3V bus and a 5V bus in a mixed 3.3V/
5V supply environment, handling all ofthe 3.3V/5Vbidirectional
interfacing issues (Figure 6). The FCT164245T is configured
as a 16-bit '245 transceiver, giving the designer tri-state
capabilities and the ability to select either bidirectional or
unidirectional modes. The translator has separate 3.3V and
5V supply and I/O pins both on separate sides of the device.
The translator part also features power-off disable, which
allows the device to withstand the maximum rated voltages on
the inputs and outputs while it is unpowered or partially
powered. This is a desirable feature for bus-interface logic in
a portable system, because of power management schemes
which power down certain subsystems when inactivity is
detected. The bus interface device will then have to buffer the
active system bus with a powered-off device without damaging
itself.
3.3V
BUS
3.3V
5V
5V
BUS
164245T
TRANSLATOR
drw06
Figure 6. Bidirectional 3.3V15V Interface
CONCLUSION
As the complexity and frequency of the microprocessor
increases, surrounding glue and bus interface logic must keep
pace. lOT has done so with the introduction of the DoubleDensity FCT-T Logic family. This family excels in all categories, including performance, noise reduction, power consumption, skew, and packaging. It also provides innovative
3.3V and 5V/3.3V translation options. The Double-Density
Logic family provides solutions for a variety of PC applications
ranging from a 3.3V subnotebook to a high-performance
fileserver.
REFERENCES
1. Alba, Manuel; "Application of High Speed/Low Power
Logic to PCs"; SVPC'92 Proceedings.
2. lOT; "High-Performance Logic Data Book"; 1992.
3. Yoshimoto, Wayne; "Mixed Supply Design Considerations in Notebook PCs"; SVPC'92 Proceedings.
NOTE: This paper was presented at WesCon'92, November 17, 1992.
138
CONFERENCE
PAPER
CP-13
MIXED SUPPLY DESIGN
CONSIDERATIONS IN
NOTEBOOK PCs
Integrated Device Technology, Inc.
By Wayne T. Yoshimoto
INTRODUCTION
The explosive growth of the portable Personal Computer
(PC) market has manufacturers clamoring for market share by
differentiating themselves in battery life and weight from their
competitors. The push for longer battery life and lighter weight
has reached a point where improvements via traditional
design techniques alone are not satisfying users. In order to
make the larger, quantum leap to eight or more hours of
battery life and weight less than 4 pounds, designers must
move to a 3.3V supply voltage. Although most of the components are currently available at 3.3V (Le. processor, chipset,
DRAM, glue logic), the next generation of portable PCs will
have to be "hybrid" systems with both 3.3V and 5V supplies
until some of the missing components, namely the disk drive
and LCD driver, become available. Even after a full 3.3V
system is available, the designer must consider the interface
with external peripherals, i.e. printers, modems, etc., since
these are not likely to move to 3.3V in the near future. The
designer will be faced with new challenges pertaining to
designing in the mixed supply environment.
MARKET OVERVIEW
1992 marks an explosive point in the portable PC market.
Portables have invaded the mainstream and are appearing
everywhere from the street corner to the office. Dataquest
estimates that by 1994, portables will account for over onethird of the PCs shipped. This shift to portable computing
reflects the strides made in the basic technology; they are now
powerful enough to replace desktop PCs. There is now no
need to have a desktop for the office and a portable for the
road.
6
5
•
Notebooks
c==J
Sub notebooks
mlml
Palmtops
4
!l
'2
:::l
'0
c: 3
~
:E
2
o
1991
1992
1993
1994
1995
drwOl
Figure 1. PC Worldwide Market Forecast
Source: Phoenix Technologies Inc.
The lOT logo is a registered trademark of Integrated Device Teohnology, Inc.
©1993 Integrated Device Technology, Inc.
8/92
139
MIXED SUPPLY DESIGN CONSIDERATIONS IN NOTEBOOK PCS
CONFERENCE PAPER CP-13
The market is broken up into a number of segments based
on weight: desktops, transportables, laptops, notebooks,
subnotebooks, and handhelds. As a whole, the PC market is
fast growing with a Compounded Annual Growth Rate (CAGR)
of almost 10%. A closer look at the cross section of the market
reveals that notebooks and subnotebooks are fueling this
growth with a CAGR of 34% and 79% respectively, while the
other categories are flat (Figure 1). In order to continue the
projected rapid growth, designers must push the battery life
and drive the weight down to points way beyond today's limits.
To do this, notebook and subnotebook PCs must move to a
3.3V supply voltage.
BENEFITS OF A LOWER SUPPLY VOLTAGE
Moving to a 3 .3V supply voltage provides extended battery
life and contributes to lighter and smaller systems. Component reliability, and thus, overall reliability is also enhanced
resulting from lower heat buildup and a reduction in boardlevel noise. The end user can expect one of two things: lighter
and smaller systems or higher-performance systems with
more features, such as built-in faxlmodem or color displays,
for the same weight.
Decreasing the supply voltage directly increases the battery life. It reduces the power consumption exponentially,
leading to a 56% savings [1-(3.3 2/5 2 )] at 3.3Vversus 5V. The
power savings also can amount to less weight because
smaller and lighter batteries can be used to provide the same
amount of battery life. For example, a 5V notebook typically
utilizes five 1.2V NiCd batteries while a 3.3V notebook would
use only three batteries, thereby reducing the weight by 40%.
On the other hand, the same number of batteries can also be
used to provide a system with more built-in features or an even
longer battery life. Lower power consumption also results in
less heat generation, which leads to fewer cooling requ irements
and higher reliability of the overall system.
Noise generation has become a problem due to ihe sharp
rise and fall times required by today's high speed systems. By
decreasing supply voltage, the voltage swing olthe 3.3V parts
outputs (typically3V) is reduced, compared to CMOS (rail-torail) swings (typically 4.8V) and TIL-compatible swings
(typically 3.3V). This will reduce noise generation, which
makes board level design easier, and also will reduce EMI
radiation, requiring less shielding to obtain FCC approval.
Lighter weight systems will be possible with the reduced
shielding requirements.
lOT 3_3V LOGIC CHARACTERISTICS
lOT provides families of optimized low voltage (Vee =
3.3V±.3V) logic functions which allow designers to develop
complete 3.3V systems. These families have been designed
to operate from a regulated 3.3V supply for optimal performance and are not simply "recharacterized" or "derated" 5V
CMOS parts. These "true" 3.3V families contain 16-bit
(IDT74FCT163XXX) and 8-bit (IDT74FCT3XXX) bus interface functions, key "glue" logic elements, and 3.3V to 5V
interface components. lOT's leading-edge CEMOS"" 5E
process achieves the combination of very low power can-
sumption and high speed. See Table 1 for a comparison
between lOT 3.3V FCT and other 3.3V products.
3_3V LOGIC COMPARISON
MFR. Device
TPD (max) ICCL(typ)
ICCD(typ)
lOT
FCT3245A
4.6ns
50uA
60uAlMHz
lOT
FCT163245A
4.6ns
50uA
50uAlMHz
TI
LVT
4.6ns
15mA
-
10.5ns
5uA
221uAlMHz
NSC LVQ245
tbl 01
Although TI's LVT family provides high speed by going to
a BiCMOS technology, this is at the expense of static power
consumption. National's LVQ family, which is merely a
recharacterized version of its FACTQ family, has very slow
speeds and high dynamic power. No other 3.3V family
provides the high speed and low power combination of lOT's
3.3V logic families.
In addition to speed and low power consumption, lOT's
3.3V logic families provide the following features:
• True TTL compatibility with 400mV noise margin.
• 50% area savings versus standard SOIC packages from
SSOP packaging
• Input and Output leakages less than 500 nA.
• Propagation delays match those of 5V FCT logic for like
functions
• All inputs (except 1/0) can be driven from either 3.3V or 5V
components
• Extended commercial temperature range of-40°C to +B5°C.
• ESD >2000V per MIL-STD-883, Method 3015.
All of lOT's 3.3V products operate functionally with Vce as
low as 2.5V, allowing them to be used in unregulated battery
driven systems.
WHY MIXED SUPPLY VOLTAGES?
Mixed supply systems will be a necessary transitional
phase between the current 5V systems and the upcoming full
3.3V systems. Technological and performance limitations will
slow down the conversion of some functions to 3.3V. For
example, disk drive and LCD driver components will not run off
of a 3.3V supply until the end of 1992. Therefore a full 3.3V
system will not be available until mid-1993. A mixed supply
system, on the other hand, can be realized today. Even a
mixed supply system provides enough of a gain in battery life
and reduced weight that any manufacturer who waits until a
fu1l3.3V system is possible will be at a competitive disadvantage.
140
MIXED SUPPLY DESIGN CONSIDERATIONS IN NOTEBOOK PCS
CONFERENCE PAPER CP·13
3.3V driving 5V
5V driving 3.3V
3.3V
Device
5V
Device
Bidirectional
dow 02
Figure 2. 3V/SV Interface
The mixed supply design concept will not go away once a
fu1l3.3V notebook is possible. The problem of interfacing with
external 5V peripherals will still exist. Issues faced while
designing the 3.3V /5V interfaces on the motherboard will also
be faced in the external interfaces.
INTERFACING 3.3V TO 5V COMPONENTS
In the new design environment of mixed supplies, the
designer needs to consider the compatibility issues of inter·
facing between 3.3Vand 5V components. Figure 2 shows the
different 3.3V/5V interface scenarios. Although the 3.3V fam·
ily is TTL·compatible with 3.3V and 5V devices, there are
situations where excess current or voltage can develop and
damage the components. The designer must understand
these situations and provide for them.
3.3 Volt
TTL
S Volt
TTL
7.0
Fora 3.3V device driving a TTL compatible 5V device, there
are no interface problems. The logic input thresholds for the
5V TTL part are VIL = O.BV and VIH = 2.0V. The 3.3V device
is guaranteed to drive a LOW of less than 0.4 V and a HIGH of
greater than 2.4V at the rated output load currents. This
provides ample noise immunity on both ends making this
interface problem-free (Figure 3). A 3.3V device will not drive
a non-TTL compatible CMOS 5V device, i.e. AC or HC, since
the input voltages required are higher than 3.3V, typically
3.B5V.
For a 5V device driving a 3.3V device, there are some
potential interface problems which must be understood and
dealt with; 5V logic will drive 3.3V logic's inputs (except 110)
directly without damage (Figure 4). Some manufacturers
have an internal clamp diode from the input or output pin to
Vcc in order to boost ESD protection. In these cases, directly
driving from a 5V device will forward bias the diode and cause
excessive current to flow into the 3.3V supply. lOT's 3.3V
Logic family implements ESD protection elsewhere and does
not suffer from this problem. Thus, driving from a 5V device
is not a problem (Figure 5A).
However, on outputs and lias, there is a clamp diode to
Vcc limiting the voltage applied to outputs to Vcc+.5V. If a
voltage greater than Vcc+.5V is applied, the clamp diode will
forward bias and possibly damage the device (Figure 58).
Here the designer must be careful of the output swings of
driving devices. Directly driving the 3.3V part from a CMOS
swing (rail-to-rail) 5V device could exceed the absolute maximum and damage the device. As long as the 3.3V and 5V
supplies track with each other, reduced-swing, TTL-compatible devices can safely drive 3.3V devices.
S Volt
TTL
Input and Output
Breakdown
7.0V
3.3 Volt
TTL
7.0
6.0
Input Breakdown
7.0 Volts
6.0
VOH (max) S.SV
5.0
5.0
4.0
4.0
3.0
3.0
VOH (max) 3.6V
VOH (min) 2.4V
VOH (min) 2.4V
2.0
2.0
VIH 2.0V
1.0
1.0
VIL O.BV
VIH 2.0 V
VIL O.BV
VOL (max) O.SV
VOL (max) 0.4V
GND
Output Breakdown
VCC+ O.SV
0
GND
GND
drw03
Figure 3. 3.3V Device Driving a SV System
0
GND
Figure 4. SV Device Driving a 3.3V Device
141
dow 04
MIXED SUPPLY DESIGN CONSIDERATIONS IN NOTEBOOK PCS
CONFERENCE PAPER CP-13
UNIDIRECTIONAL TRANSLATORS
Input clamp
to Vee
As described above, a number of lOT's 3.3V FCT and 5V
3.3V
5V
FCT-T parts can be used as unidirectional 5V-to-3.3V translators. The input pins of the 3.3V FCT family can take an input
voltage up to 7V allowing them to be driven by 5V components. Figure 6 contains a list of 3.3V unidirectional transla5V
tors currently available today. The 5V FCT -T family's reduced
Device
output swings, VOH typically 3.3V, allows them to safely drive
3.3V components.
The unidirectional translators accept TTL- or CMOS-compatible signals from 5V components at the inputs and provide
drw 06
TTL-compatible output levels. These translators avoid any
Figure 58. Simplified Output Structure
problems associated with a direct interface between a 5V
component and a 3.3V component or between a 5V compo3.3V/5V BIDIRECTIONAL TRANSLATOR
nent and a 3.3V bus.
Since not all bus interface applications are unidirectional,
No Input clamp
there
needs to also be a bidirectional solution to the 3.3V to 5V
to Vee
3.3V
interface. A solution to this is the IOT74FCT164245T. It
5V
interfaces between a 3.3V bus and a 5V bus in a mixed 3.3VI
5V supply environment handling all of the 3.3V/5V bidirectional interfacing issues (Figure 7). It is configured as a 16-bit
'245 transceiver, giving the designer tri-state capabilities and
5V
the ability to select either bidirectional or unidirectional modes.
Device
The translator has separate 3.3V and 5V supply and 1/0 pins
both on separate sides of the device (Figure 8).
All 1/0 pins and input pins can withstand a maximum input
drw05
voltage of 7V. This allows both ports to be driven by 3.3V or
Figure 5A. Simplified Input Structure
5V devices.
3.3V
3.3V
BUS
r
5V Components
3r
I
~
z
w
IDT74FCT3244
IDT74FCT163244
IDT74FCT163373
IDT74FCT163374
Z
o
a..
~
8
>
(')
<'i
drw 07
Figure 6. Mixed 5V/3.3V System
142
MIXED SUPPLY DESIGN CONSIDERATIONS IN NOTEBOOK PCs
3.3V
BUS
3.3V
Component
~
.....
3.3V
5V
BUS
5V
t t
164245T
TRANSLATOR
CONFERENCE PAPER CP-13
f- f+
CONCLUSION
5V
Component
dtw08
Figure 7. 3.3V to 5V Bidirectional Translator
The translator part also features power-down disable. This
allows the device to withstand the maximum rated voltages on
the inputs and outputs while it is unpowered or partially
powered. This is a desirable feature for bus-interface logic in
a portable system because of power management schemes
which power down certain subsystems when inactivity is
detected. The bus interface device will then have to buffer the
active system bus with a powered off device without damaging
itself.
To avoid damage to a part which does not support powerdown disable, the current from the 5V outputs to the 3.3V
outputs or I/O must be limited. The designer may place a
resistor between each 5V output and corresponding 3.3V I/O.
When the 3.3V I/O is in a high-impedance state, a current will
flow from the 5V part to the 3.3V part through the resistor and
clamp diode causing a voltage drop between the devices and
preventing damage. However, placing a resistor between the
5V and 3.3V part will cause some speed degradation due to
the RC time constant which develops between the series
resistor and the input capacitance of the 3.3V part and other
parts that may be similarly attached.
3.3V
5V
1
b:o
b:
oa.
a.
>
<'l
>
LO
<'i
•
•
x16
j
1
FCT164245T
drw 09
Figure 8. IDTFCT164245T Translator Block Diagram
143
The benefits of a 3.3V supply voltage have forced designers to an interim solution while not all of the components are
available at 3.3V. "Hybrid" or mixed supply systems seem to
be the interim solution until a full 3.3V system is possible.
When the full 3.3V system is possible, the concepts learned
must be applied to interfacing with external 5V peripherals.
Designing in the mixed supply environment provides new
challenges for the designer both in the "hybrid" system and in
the external peripheral interface. The compatibility issues of
the 3.3V/5V interface and the solutions available today must
be understood in order to see notebook PCs with 8 -12 hour
battery life and weight under 4 pounds.
NOTE: This paper was presented at the Silicon Valley Personal Computer
(SVPC) Conference on 8/4/92.
REFERENCES
1. lOT; "3.3 Volt Logic"; Application Note #103
2. lOT; "High Performance Logic Databook"; 1992
3. Prince, Betty; "ICs Going on a 3-V Diet"; IEEE Spectrum; 3/92
4. Ristow, Ken; "Mixing It up with 3.3 Volts"; Electro'92
Proceedings
Integrated
Device Technology, Inc.
U.S. HEADQUARTERS
Integrated Device Technology, Inc.
2975 Stender Way
P.O. Box 58015
Santa Clara , CA 95052-8015
Tel: (408) 727-6116
FAX: 408-492-8674
UNITED KINGDOM
Integrated Device Technology, Ltd.
21 The Crescent
Leatherhead
Surrey, UK KT2280Y
Tel: (44) 0372-363339
FAX: (44) 0372-378851
HONG KONG
Integrated Device Technology, Asia, Ltd.
Room 1505, 15F, The Centre Mark
287-299 Queen's Road Central
Hong Kong
Tel: 852-542-0067
FAX: 852-544-5603
/
JAPAN
Integrated Device Technology, KK
U.S. Building 201
1-6-15 Hirakarasho, Chiyoda-Ku
Tokyo 102, Japan
Tel: 81-3-221-9821
FAX: 81-3-221-7372
© 1993 Integrated Device Technology, Inc.
Printed in U.S.A.
MAN-LOGIC-00023
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