1993_Philips_PSD3XX_Programmable_Microcontroller_Peripherals 1993 Philips PSD3XX Programmable Microcontroller Peripherals
User Manual: 1993_Philips_PSD3XX_Programmable_Microcontroller_Peripherals
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INTEGRA TEO CIRCUITS
WYLE
ELEC1RONICS
MARKETING
LABORATORIES GROUP
SANTA CLARA DIVISION
3000 Bowers Avenue
S;:tnta Clara, CA 95051
(408) 727-2500 • (800) 866-9953
e
PHILIPS
PHILIPS
PSD3XX
Programmable
Microcontroller Peripherals
PHILIPS
Philips Semiconductors and North American Philips Corporation reserve the right to make
changes, without notice, in the products, including circuits, standard cells, and/or software,
described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products,
conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from
patent, copyright, or mask work right infringement, unless otherwise specified. Applications
that are described herein for any of these products are for illustrative purposes only.
Philips Semiconductors makes no representation or warranty that such applications will be
suitable for the specified use without further testing or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and North American Philips Corporation Products are not designed
for use in life support appliances, devices, or systems where malfunction of a Philips
Semiconductors and North American Philips Corporation Product can reasonably
be expected to result in a personal injury. Philips Semiconductors and North American
Philips Corporation customers using or selling Philips Semiconductors and North American
Philips Corporation Products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors and North American Philips Corporation for any
damages resulting from such improper use or sale.
© Copyright North American Philips Corporation, 1993
I
Preface
PSD3XX
Programmable Microcontro"er Peripherals
PSDX3XX Programmable Microcontro"er Peripherals from Philips
Semiconductors
Philips Semiconductors supplies a wide range of microcontrollers peripherals for use with all of the
popular microcontroller architectures. By offering a wide range of peripheral products, we can meet
a broad range of specific or unique application requirements. In addition, Philips Semiconductors
supplies a full line of microcontrollers based on the 80C49 and 8OC51 architectures. With over 50
derivatives of the 80C51 microcontroller available, Philips Semiconductors has the broadest offering
on the market.
This data handbook covers the PSD3XX products. These programmable microcontroller peripherals
contain 32K to 128K bytes of EPROM (UV erasable or One Time Programmable) external program
memory, 2K bytes of SRAM external data memory, and memory paging and port reconstruction logic.
Philips Semiconductors' PSD3XX products interface directly to our 8OC51 microcontrollers without
need of any other parts. This allows the memory of the microcontroller to be increased with the
addition of only one part and without the loss of the functionality of the microcontroller ports used in
the interface.
Philips Semiconductors supplies a wide range of microcontrollers based on mainstream architectures,
spanning 8-, 16-, and 32-bit product lines. All of our microcontrollers are based on mainstream
architectures to allow our customers to take advantage of existing software and a vast array of
third-party support.
Philips Semiconductors' 8-bit microcontrollers are based on the popular 80C51 and 80C49
architectures. We offer most of the Industry Standard products as well as a large selection of powerful
derivatives. Many of the derivatives have an 12C serial interface that allows them to be easily
connected to over 70 other parts: this increases their capabilities even further. The 80C51 products
are covered in the BOCS1-Based B-Bit Microcontrollers data handbook (IC20) and the 12C parts that
are most commonly used with microcontrollers are covered in the 12C Peripherals for Microcontrollers
data handbook. Philips Semiconductors offers the most 80C51 derivatives in the world.
Philips Semiconductors' 16-bit microcontroller family is based on the powerful 68000 architecture.
While these are called 16-bit microcontrollers, the 68000 CPU core architecture is 32-bit. This offers
the user a great deal more processing power, when the need arises in a design to move from an 8-bit
to a 16-bit microcontroller. Philips Semiconductors' 16-bit microcontrollers are software compatible with
existing 68000 code. As with our popular 8-bit microcontrollers, EPROM and OTP versions of our
16-bit products are available. The 16-bit microcontrollers are covered in a separate data handbook, the
IC21, 68000-Based 16-bit Microcontrollers.
Philips Semiconductors is developing a family of 32-bit microcontrollers based on the SPARC RISC
architecture. This family of microcontrollers will offer the ultimate in processing power for those
applications that are computation-intensive in a embedded control environment.
Philips Semiconductors offers uncompromising quality, service, and support with all of our
microcontroller and miCiocontrolier peripheral products. For a complete family and the best in
microcontroller products, look to Philips Semiconductors.
Philips Semiconductors - Microcontroller Products
iii
Product Status
PSD3XX
Programmable Microcontroller Peripherals
DEFINITIONS
Data Sheet
Identification
Product Status
Objecl/WI SpeC/fical/on
Fonnatlve or In Design
This data sheet contains the design target or goal specifications for
product development. Specifications may change In any manner
without notice.
Prellmlflllry SpeC/fical/on
Preproduction Product
This data sheet contains preliminary data, and supplementary data
will be published at a later date. Philips Semiconductors reserves the
right to make changes at any time without notice In order to Improve
design and supply the best possible product.
Product Specifical/on
Full Production
iv
Definition
This data sheet contains Final Specifications. Philips Semiconductors
reserves the right to make changes at any time wtthout notice, In order
to improve design and supply the best possible product.
Philips Semiconductors PSD3XX Programmable Mlcrocontroller Peripherals
Ordering Information
PART NUMBER EXPLANATION
PSD3XX _;.. J~
_!-
_~
L...-__
L--_ _ _ _ _
Package
A
= Plastic Leaded Chip Carrier (PLCC)
B
= Plastic Quad Flat Pack
KA
= Ceramic Leaded Chip Carrier (CLCC)
Operating Temperature Range:
Blank = Commercial: 0° to +70°C
I
= Industrial: -40° to + 85°C
Speed
X10ns
- = 5V Standard Operation
L = 3V Low Voltage Operation
Basic
Part
Number
*Surface Mount
**Socketing Recommended
v
Window
No*
No**
Yes**
Contents
PSD3XX
Programmable Mlcrocontroller
Peripherals
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
Product Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
Ordering Information ...........................................................................................
v
Section 1
PSD3XX Family
PSD3XX Family Field-programmable microcontroller peripherals ......................................................
PSD301® Field-programmable microcontroller peripheral (x8/x16; 256Kb EPROM, 16Kb SRAM) .............................
3
33
PSD311 Field-programmable microcontroller peripheral (x8; 256Kb EPROM, 16Kb SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSD302 Field-programmable microcontroller peripheral (x8/x16; 512Kb EPROM, 16Kb SRAM) ..............................
55
73
PSD312 Field-programmable microcontroller peripheral (x8; 512Kb EPROM, 16Kb SRAM). . . . . . .. . . . . . . . . ... . .. . . . . . . . . . . ..
95
PSD303 Field-programmable microcontroller peripheral (x8/x16; 1Mb EPROM, 16Kb SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
113
PSD313 Field-programmable microcontroller peripheral (x8; 1Mb EPROM, 16Kb SRAM) ................................... 133
Section 2
PSD3XXL Family
PSD3XXL Family 3-volt single-chip microcontroller peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 151
PSD301 ®L 3-volt single-chip microcontroller peripheral (x8/x16; 256Kb EPROM, 16Kb SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 181
PSD311 L 3-volt single-chip microcontroller peripheral (x8; 256Kb EPROM, 16Kb SRAM) ................................... 203
PSD302L 3-volt single-chip microcontroller peripheral (x8/x16; 512Kb EPROM, 16Kb SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 221
PSD312L 3-volt single-chip microcontroller peripheral (x8; 512Kb EPROM, 16Kb SRAM) ................................... 243
PSD303L 3-volt single-chip microcontroller peripheral (x8/x16; 1Mb EPROM, 16Kb SRAM) ................................. 261
PSD313L 3-volt single-chip microcontroller peripheral (x8; 1Mb EPROM, 16Kb SRAM) . . . . . . . . . . . . .
. . . . . . . . . . . . . . . .. 283
Section 3
Application Notes
Application Note 011 The PSD3XX Device Description .............................................................. 303
Application Note 013 The PSD301 Streamlines a Microcontroller-Based Smart Transmitter Design. . . . . . . . . . . .. . . . . . . . . . . . . . .. 357
Application Note 014 Using the PSD3XX PAD for System Logic Replacement ............................................ 371
Application Note 015 Using Memory Paging with the PSD3XX ........................................................ 385
Application Note 016 Power Considerations in the PSD3XX .......................................................... 399
Application Note 018 Security of Design in the PSD3XX ............................................................. 413
Application Note 019 The PSD311 Simplifies an Eight Wire Cable Tester Design and Increases Flexibility ...................... 417
Application Note 020 Benefits of 16-Bit Design with PSD3XX ......................................................... 437
Section 4
Developing Systems
PSD GoldlPSD Silver Development System ....................................................................... 451
WS6000 MagicPro@ Memory and Programmable Peripheral Programmer ............................................... 455
Section 5
Package Outlines
J2 44-Pin Plastic Leaded Chip Carrier (PLCC) ..................................................................... 461
L4 44-Pin Ceramic Leaded Chip Carrier (CLCC) with Window (Package Type L) ......................... . . . . . . . . . . . . . . . .. 462
Q2 52-Pin Plastic Quad Flatpack (PQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 463
Section 6
Sales Offices, Representatives & Distributors .......................................................... . 467
PSD301 Is a regislered trademark of WaferScale Integration, Inc.
MagicPro is a registered trademark of WaferScale Integration. Inc.
May, 1993
vii
Philips Semiconductors
Section 1
PSD3XX Family
PSD3XX Programmable
Mlcrocontroller Peripherals
INDEX
PSD3XX
Family
Field-programmable
microcontroller peripherals ..................................................3
PSD301®
Field-programmable
microcontroller peripheral
(xS/x16; 256Kb EPROM, 16Kb SRAM) .............................33
PSD311
Field-programmable
microcontroller peripheral
{xS; 256Kb EPROM, 16Kb SRAM) ....................................55
PSD302
Field-programmable
microcontroller peripheral
(xS/x16; 512Kb EPROM, 16Kb SRAM) ............................. 73
PSD312
Field-programmable
microcontroller peripheral
{xS; 512Kb EPROM, 16Kb SRAM) ....................................95
PSD303
Field-programmable
microcontroller peripheral
(xS/x16; 1Mb EPROM, 16Kb SRAM) ............................... 113
PSD313
Field-programmable
microcontroller peripheral
(xS; 1Mb EPROM, 16Kb SRAM) ..................................... 133
PSD301® is a registered trademark of WaferScale Integration, Inc.
Preliminary specification
Philips Semiconductors Mlcrocontroller Peripherals
Field-programmable microcontroller peripherals
Key Features
o
Single Chip Programmable Peripheral
for Microcontroller-based Applications
o
19 Individually Configurable I/O pins that
can be used as
-
Microcontroller I/O port expansion
-
Programmable Address Decoder
(PAD) I/O
-
Latched address output
-
Open drain or CMOS
o
Two Programmable Arrays
(PAD A and PAD B)
-
Total of 40 Product Terms and up to
16 Inputs and 24 Outputs
-
Address Decoding up to 1 MB
-
Logic replacement
o
"No Glue" Microcontroller Chip-Set
-
Built-in address latches for multiplexed
address/data bus
-
Non-multiplexed address/data bus mode
-
ALE and Reset polarity programmable
-
Selectable modes for read and write
control bus as RDIWR or R/W/E
o
256 Kbits of UV EPROM
-
Configurable as 32K x 8 or as 16K x 16
-
Divides into 8 equal mappable blocks
for optimized mapping
PSD3XX
Family
Feature
Summary
May. 1993
Part
PSD3XX Family
-
Block resolution is 4K x 8 or 2K x 16
-
120 ns EPROM access time, including
input latches and PAD address
decoding.
o
16 Kbit Static RAM
-
Configurable as 2K x 8 or as 1K x 16
-
120 ns SRAM access time, including
input latches and PAD address
decoding
o
Address/Data Track Mode
-
Enables easy Interface to Shared
Resources (Mail Box SRAM) with other
Microcontrollers or a Host Processor
o
Built-In Security
-
Locks the PSD3XX Configuration and
PAD Decoding
o
Available in a Variety of Packaging
-
44 Pin PLDCC and CLDCC
o
Simple Menu-Driven Software:
Configure the PSD3XX on an IBM PC
PtO
Inputs! Ports EPROM SRAM Configuration Memory C-Miser Security
Paging
Bit
Size
Size
Bit
Product
Terms
PSD301@
14/40
19
PSD311
14/40
PSD302
18/40
PSD312
X
16 Kb
19
256 Kb
16 Kb
x8
X
X
19
512 Kb
16 Kb
x8 or x16
X
X
X
18/40
19
512 Kb
16 Kb
x8
X
X
X
PSD303
18/40
19
1 Mb
16 Kb
x8 or x16
X
X
X
PSD313
18/40
19
1 Mb
16 Kb
x8
X
X
X
3
x8 or x16
X
256 Kb
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD3XX Family
Field-programmable microcontroller peripherals
Partial Listing
o
of
MlcfDcontrollelS
Supported
o
Motorola family:
M6805, M68HC11, M68HC16,
M6800011 0/20, M60008, M683XX
Applications
Z8,Z80,Z180
Fixed Disk Control, Modem, Imaging,
Laser Printer Control
Introduction
Telecommunications
Modem, Cellular Phone, Digital PBX,
Digital Speech, FAX,
Digital Signal Processing
The PSD3XX Series are members of the
rapidly growing family of PSD devices. They
are the market's first low-voltage single-chip
solution for microcontroller-based
applications where consistent specifications
for deSign, fast time-to-market, small form
factor, and low power consumptions are
essential. When combined in an 8- or 16-bit
system, virtually any microcontroller
(68HC11, 8051,80186, etc.) and the
PSD3XX device work together to create a
very powerful chip-set solution. This
implementation eliminates mixing and
matching low voltage specifications for
PSD301 Is a registered trademark of WaferScaie Integralion. Inc.
PAL Is a registered trademark of Advanced Micro Devices. Inc.
May. 1993
o National:
HPC 16000, HPC46400
Signetlcs:
SC80C451, SC80552
o Computers (Notebook and Portable PCs)
o
o ZlIog:
Intel family:
8031/8051,8096/8098,80186/88,
80196/98
o
OTI:
SC80C451, TMS320C14
4
o
Portable Industrial Equipment
Measurement Meters, Data Recorders
o
Medicallnstrumentation
Hearing Aids, Monitoring Equipment,
Diagnostic Tools
various discrete components. It also
provides all the required control and
peripheral elements needed in a
microcontroller-based system with no
external discrete "glue" logic required.
The solution comes complete with simple
system software development tools for
integrating the PSD3XX with the
microcontroller. Hosted on IBM PC
platforms or compatibles, the easy to use
software enables the designer to quickly
configure the device and use it immediately.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
Product
Description
The PSD3XX family integrates high
performance user-configurable blocks of
EPROM, SRAM, and programmable logic.
The major functional blocks include two
programmable logic arrays, PAD A and
PAD B, 256K to 1Mbit of EPROM, 16K bits
of SRAM, input latches, and output ports.
The PSD3XX family is ideal for
applications requiring low power and very
small form factors. These include hard disk
control, modems, cellular telephones,
instrumentation, computer peripherals,
military and similar applications.
The 8051 microcontroller family can take
full advantage of the PSD3XX's separate
program and data address spaces. Users
of the 68HCXX microcontroller family can
change the functionality of the control
signals and directly connect the R/W and E,
or the RIW and DS signals. (Users of
16-bit microcontrollers, including the 80186,
8096,80196 and 16XXX, can use the
PSD301/302/303 in a 16-bit configuration).
Address and data buses can be configured
as separate or multiplexed, whichever is
required by the host processor.
The PSD3XX family offers a unique singlechip solution for microcontrollers that need:
The flexibility of the PSD3XX I/O ports
permits interfacing to shared resources.
The arbitration can be controlled internally
by PAD A outputs. The user can assign the
following functions to these ports: standard
I/O pins, chip-select outputs from PAD A
and PAD B, or latched address or
multiplexed low-order address/data byte.
This enables users to design add-on
systems such as disk drives, modems, etc.,
that easily interface to the host bus (e.g.,
IBM PC, SCSI).
o
o
o
o
o
I/O reconstruction (microcontrollers
lose at least two I/O ports when
accessing external resources).
More EPROM and SRAM than the
microcontroller's internal memory.
Chip-select, control, or latched address
lines that are otherwise implemented
discretely.
An interface to shared external
resources.
Expanded microcontroller address
space.
The PSD3XX Family Architecture
(Figure 1) can efficiently interface with, and
enhance, any low-voltage 8- or 16-bit
microcontroller system. This is the first
solution that provides microcontrollers with
port expansion, latched addresses, page
logic, two programmable logic arrays (PAD
A and PAD B), an interface to shared
resources, 256K, 512K or 1M bit EPROM,
and 16K bit SRAM on a single chip. The
PSD3XX family does not require any glue
logic for interfacing to any 8- or 16-bit
microcontroller.
May, 1993
PSD3XX Family
5
The page register extends the accessible
address space of certain microcontrollers
from 64 K to 1 M. There are 16 pages
that can serve as base address inputs to
the PAD, thereby enlarging the address
space of 16 address line microcontrollers
by a factor of 16..
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontrol\er peripherals
PSD3XX Family
FIgure 1.
PSD3XX
FamIly
ArchItecture
I
PAGELOGIC*
P3-PO
-
A11-A15
L
A
T
C
H
A08-A015
A8-A10
A19/CSI
r--
ALE/AS
A16-A18
ALEIAS
PAD A
AD
RO
WR
WR
13P.T.
ES7
ES6
ES5
ES4
ES3
ES2
ES1
'---
-
-
ESQ-+f
-~- ... :J~
r;6i8
~
~
...
-
MUX
..
-,
roo
.....
CSGCS7
-.
EPROM
256KbTO 1Mb
r
08-015
PBoPORT
B
~
CSIOPORT
00-07
"
i+- ! ~
SRAM
16K BIT
TRACK MODE
SELECTS
PROG.CHIP
CONFIGURATION
t
WRlRiW
X8,X16
MUX or NON-MUX BUSSES
SECURITY MODE
PROG.
CONTROL
SIGNALS
A19/CSI
*PSD30213121303/313 only.
6
PROG.
PORT
EXP.
PAGPORT
A
ALE/AS
May, 1993
PROG.
PORT
EXP.
'---
AO-A7
ADo-A07/00-07
BHEIPSEN
A
"l
f-
'---
RESET
PORT
C
CS8CS10
27P.T.
-
Ro/E/OS
PROG.
PORT
EXP.
..- -- - - -
L
A
T
C
H
~
PAOB
RESET
RESET
'--
1.....+
LOGIC IN
CSIOPORT
A19/CSI
PCG-
ALE/AS
~
A0G-A07
-=-
~
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripherals
Table 1.
PSD3XXPIn
Descriptions
Description
Type
Name
SHE/PSEN
(PSD30X
Devices)
or
PSD3XX Family
When the data bus width is 8 bits (CDATA = 0), this pin is PSEN. In
this mode, PSEN is the active low EPROM read pulse. The SRAM
and 110 ports read signal is generated according to the description of
the WRIVpp or R/W and RD/E/DS pins. If the host processor is a
member of the 8031 family, PSEN must be connected to the
corresponding host pin. In other 8-bit host processors that do not
have a special EPROM-only read strobe, PSEN should be tied to
Vcc. In this case, RD or E and R!W provide the read strobe for the
SRAM, 1/0 ports, and EPROM. When the data bus width is
configured as 16 (CDATA = 1), this pin is SHE. When SHE is low,
data bus bits D8-D15 are read from, or written into, the PSD3XX,
depending on the operation being read or write, respectively. In
programming mode, this pin is pulsed between Vpp and O.
The PSEN is the active low EPROM read pulse. The SRAM and 110
read signal is generated according to the description of the
WRNpp or RIW, and RD/E pins. If the host processor is a member
Of the 8031 family, PSEN must be connected to the correspondinbg
host pin. In other 8-bit host processors that do not have a special
EPROM-only read strobe, PSEN should be tied to Vcc. In this case,
RD or E and R/W provide the read strobe for the SRAM, 1/0 ports,
and EPROM.
~s
PSEN
(PSD31X
Devices
Only)
In the operating mode this pin's function is WR (CRRWR = 0) or
R/W (CRRWR = 1) when configured as R/W. The following tables
summarize the read and write operations (CRRWR = 1):
WRIVpp
or
R/WIVpp
CEDS
R/W
E
x
o
o
1
1
1
=0
R/W
NOP
write
read
x
o
1
CEDS = 1
DS
1
NOP
write
read
o
o
When configured as WR, a write operation is executed during an
active low pulse. When configured as R/W, with RIW = 1 and E = 1,
a read operation is executed; if RIW = 0 and E = 1, a write
operation is executed. In programming mode, this pin must be tied
to Vpp voltage.
RD/E/DS
(Note 2)
or
RD/E
(Note 3)
Legend:
NOTE:
May, 1993
The pin function depends on the CRRWR and CEDS configuration
bits. If CRRWR = 0, RD is an active low read pulse. When
CRRWR = 1, this pin and the R/W pin define the following cycle type:
If CEDS = 0, E is an active high strobe. If CEDS = 1, DS is an active
low strobe.
When configured as RD (CRRWR = 0), this pin provides an active
low RD strobe. When configured as E (CRRWR = 1), this pin
becomes an active hi9!!.pulse, which, together with RIW defines the
cycl~pe. Then, if R/W = 1 and E = 1, a read operation is executed.
If RIW = 0 and E = 1 , a write operation is executed.
The 1/0 column abbreviations are: I = input; 110 = input/output; P = power.
1. All the configuration bits mentioned in Table 1 appear in parentheses and are explained in
the Configuration Register section.
2. PSD302131213031313 only.
3. PSD3011311 only.
7
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
Table 1.
PSD3XXPln
DescrIptIons
{Cont.}
Name
CSI/A19
I
RESET
I
ALE
or
AS
PA7
PA6
PAS
PA4
PA3
PA2
PA1
PAO
PB7
PB6
PBS
PB4
PB3
PB2
PB1
PBO
May, 1993
Type
I
I/O
110
PSD3XX Family
Description
This pin has two configurations. When it is CSI (CA19/CSI = 0) and
the pin is asserted high, the device is deselected and powered
down. (See Tables 12 and 13 for the chip state during power-down
mode.) If the pin is asserted low, the chip is in normal operational
mode. When it is configured as A19, (CA19/CSI = 1), this pin can
be used as an additional input to the PAD. CADLOG3 = 1 defines
the pin as an address; CADLOG3 = 0 defines it as a logic input. If it
is an address, A19 can be latched with ALE (CADDHLT = 1) or be
a transparent logic input (CADDHLT = 0). In this mode, there is no
power-down capability.
The user-programmable pin can be configured to reset on high
level (CRESET = 1) or on low level (CRESET = 0). It should
remain active for at least 100 ns. See Tables 10a, 10b and 11
for the chip state after reset.
In the multiplexed modes, the ALE pin functions as an Address
Latch Enable or as an Address strobe and can be configured as
an active high or active low signal. The ALE or AS trailing edge
latches lines AD1S1A 1S-ADOIAO and A 16-A19 in 16-bit mode
(AD7/A7-ADO/AO and A16-A19 in 8-bit mode) and BHE,
depending on the PSD3XX configuration. See Table 8. In the
non-multiplexed modes, it can be used as a general-purpose
logic input to the PAD.
PA7-PAO is an 8-bit port that can be configured to track
AD7/A7-ADO/AO from the input (CPAF2 = 1). Otherwise
(CPAF2 = 0), each bit can be configured separately as an I/O or
lower-order latched address line. When configured as an I/O
(CPAF1 = 0), the direction of the pin is defined by its direction bit,
which resides in the direction register. If a pin is an 110 output, its
data bit (which resides in the data register) comes out. When it is
configured as a low-order address line (CPAF1 =1), A7-AO
can be made the corresponding output through this port (e.g., PA6
can be configured to be the A6 address line). Each port bit
can be a CMOS output (CPACOD = 0) or an open drain output
(CPACOD = 1). When the chip is in non-multiplexed mode
(CADDRAT = 0), the port becomes the data bus lines (DO-D7).
See Figure 4.
PB7-PBO is an 8-bit port for which each bit can be configured as
an 110 (CPBF = 1) or chip-select output (CPBF = 0). Each port bit
can be a CMOS output (CPBCOD = 0) or an open drain output
(CPBCOD = 1). When configured as an I/O, the direction of the
pin is defined by its direction bit, which resides in the direction
register. If a pin is an I/O output, its data (which resides in the data
register) comes out. When configured as a chip-select output,
CSO-CS3 are a function of up to four product terms of the inputs to
the PAD B; CS4,-CS7 then are each a function of up to two
product terms. On the PSD301 U302U303L, when the chip is in
non-multiplexed mode (CAD DRAT = 0) and the data bus width is
16 (CDATA = 1), the port becomes the data bus (D8-D1S).
See Figure 6.
8
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD3XX Family
Field-programmable microcontroller peripherals
Table 1.
PSD3XXPIn
Descriptions
(Cont.)
Name
I/O
This is a 3-bit port for which each bit is configurable as a PAD A
and B input or output. When configured as an input (CPCF = 0),
a bit individually becomes an address (CADLOG = 1) or a logic
input (CADLOG = 0). The addresses can be latched with ALE
(CADDHLT = 1) or be transparent inputs to the PADs
(CADDHLT = 0). When a pin is configured as an output (CPCF = 1),
it is a function of one product term of a" PAD inputs.
See Figure 7.
I/O
In muHiplexed mode, these pins are the multiplexed low-order
address/data byte. After ALE latches the addresses, these
pins input or output data, depen~ on the settings of the RD/E
(RD/E/DS on the PSD302/303), WR/v pp or R/W, and BHEIPSEN
pins. In non-multiplexed mode, these pins are the low-order
address input.
ADS/AS
ADS/AS
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD1S/A1S
I/O
In 16-bit multiplexed mode, these pins are the multiplexed
high-order address/data byte. After ALE latches the addres~s, these
pins input or output data, depending on the settings of the RD/E or
RD/EIDS, WR/vpp or RIW, and BHE/PSEN pins. In a" other modes,
these pins are the high-order address input.
GND
P
Vss (ground) pin.
Vcc
P
Supply voltage input.
PCO
PC1
PC2
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
ADS/AS
AD6/A6
AD7/A7
May. 1993
Description
Type
9
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripherals
Operating
Modes
The PSD3XX's four operating modes
enable it to interface directly to 8- and
16-bit microcontrollers with multiplexed and
non-multiplexed address/data buses.
These operating modes are:
o Multiplexed 8-bit address/data bus
o Multiplexed 16-bit address/data bus
(PSD30X)
a Non-multiplexed address/data, 8-bit
data bus
a Non-multiplexed 16-bit address/
data bus (PSD30X)
Multiplexed B-bit Address/Data Bus
This mode is used to interface to
microcontrollers with an 8-bit data bus and
a 16-bit or larger address bus. The
address/data bus (ADO/AQ-AD7/A7) is
bi-directional and permits the latching of the
address when the ALE signal is active. On
the same pins, the data is read from or
written to the device; this depends on
the state of the RD/E or RD/EiOS pin,
BHEIPSEN or PSEN pin and WR/vpp or
R/W pins. The high-order address/data bus
(AD8/A8-AD15/A15) contains the highorder address bus byte. Ports A and B can
be configured as in Table 2.
Multiplexed 16-bit Address/Data Bus
This mode is used to interface to microcontrollers with a 16-bit data bus and a 16bit or larger address bus. The low-order
address/data bus (ADO/AQ-AD7/A7) is
bi-directional and permits the latching of the
address when the ALE signal is active. On
the same pins, the data is read from or
written to the device; this depends on the
state of the RD/EIDS, BHEIPSEN, and
WR/vpp or RIW pins. The high-order
address/data bus (AD8/A8-AD15/A15) is
bi-directional and permits latching of the
high-order address when the ALE signal is
active on the same pins. The high-order
data bus is read from or written to the
device~eRending on the state of the
_
RD/ElDS, BHE/PSEN, and WR/vpp or RIW
pins. Ports A and B can be configured as in
Table 2.
May, 1993
10
PSD3XX Family
Non-Multiplexed
Address/Data, B-bit Data Bus
This mode is used to interface to nonmultiplexed 8-bit microcontrol\ers with an
8-bit data bus and a 16-bit or larger
address bus. The low-order address/data
bus (ADO/AQ-AD7/A7) is the low-order
address input bus. The high-order
address/data bus (AD8/AS-AD15/A15)
(A8-A15 on the PSD31X) is the high-order
address bus byte. Port A is the low-order
data bus. Port B can be configured as
shown in Table 2.
Non-Multiplexed
Address/Data, 16-bit Data Bus
This mode is used to interface to nonmultiplexed 16-bit microcontrollers with a
16-bit data bus and a 16-bit or larger
address bus. The low-order address/data
bus (ADO/AO-AD7/A7) is the low-order
address input bus. The high-order
address/data bus (AD8/A8-AD15/A15) is
the high-order address bus byte. Port A is
the low-order data bus. Port B is the highorder data bus.
Table 2 summarizes the effect of the
different operating modes on ports A, B,
and the address/data pins. The configuration of Port C is independent of the four
operating modes.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
Flgure2a.
PSD3XXPort
Configurations
(xB/x16)
AD,!AD15
ADO;".AD?
E
...
...
--.
r
ElPSEN
PA
PB
RIW
-or WRN pp ..
RDIEJDs
..
_
19/CSi
...
SET
--
-
ADO:...AD?
f--
..-
SEN
..
RIW
-or
..
..
1. Configured for multiplexed 16-bit
address/data bus.
.
AO-A?
PA
...
ALE
BiTEtPSEN
-
..
..
SET
...
A19/CSI
SET
--""
r
I--
PB
RIW or WRlV pp•
RDlEtrm
DO-D?
Ds..D15
...
..
...
PC
AD-A?
BHEIPSEN
RD/EIDS
~6-A18orCS8~
A19/CSI
RESET
_
r
As.. A15
-
VO or AD-A? or
ADO~D?
ALE
~
EN
..
..
.
..
PA
A19/CSI
--.
r
RESET
May, 1993
.
..
...
..
..
..
VO or CS&CS7
...
r
~ 6-A 18 or
css;.c
r
PA
OO-D?
-
r
I--
PB
,10 or CSO-CS~
I--
..
A 16-A18 or CSi-c
PC
..
A8 -A15
...
AO -A?
.
..
PB
~ or CSO-CS? ..
AL E
..
N
PSE
...
RtW or WRlV pp ..
-
ADIEtDs
PC
~6-A18orCSs....C
PA
...
OO-D?
..
..
.
r---
..
..
-
r---
...
A16-A18orCSS-C
PC
--
2. Configured for non-multiplexed
address/data, a-bit bus.
AD8-AD15 = Addresses A8-A15 multiplexed with data lines D8-D15.
ADO-AD? = Addresses AO-A? multiplexed with data lines Do-D?
11
...
VO or CSO-CS?
PB
r
A1 9/CSi
SET
~
1. Configured for multiplexed a-bit
address/data bus.
Legend:
r
r
or WRtv PP ..
D/EIDs
ADO-AD?
..
-
4. Configured for non-multiplexed
address/data, a-bit bus.
3. Configured for non-multiplexed
16-bit address/data bus.
Flgure2b.
PSD3XXPort
Configurations
(xBOn/y)
PC
--.
RIW or WRlV p':.
I--
PB
VO or AO-A? or
.. ADO-AD?
2. Configured for multiplexed a-bit
address/data bus.
ALE
..
-
.
r
As..A15
...
.
19/CSi
r
AS-A15
-
WRiv pp...
RDIE/OS
A16-A18orCSS-C
PC
..
r
VO or CS(}.CS7
PA
...
.
E
f--
...
..
AS-A15
110 or AO-A? or
__ ADO-AD?
_
PSD3XX Family
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
Table 2.
PSD30XBus
and Port
Configuration
Options
PSD3XX Family
Multiplexed Address/Data
Non-Multiplexed Address/Data
'-bit Data Bus
I/O or low-order address
lines or Low-order multiplexed
address/data byte
Do-D7 data bus byte
Port B
I/O or CSO-cS7
I/O and/or CSO-cS7
ADO/Ao-AD7/ A7
Low-order multiplexed
address/data byte
Low-order address bus byte
ADS/AS-AD15/A15
High-order multiplexed
address data byte
High-order address bus byte
Port A
I/O or low-order address
lines or Low-order multiplexed
address/data byte
Low-order data bus byte
Port B
I/O or CSO-CS7
High-order data bus byte
ADO/Ao-AD7/A7
Low-order multiplexed
address/data byte
Low-order address bus byte
ADS/AS-AD15/A15
High-order multiplexed
address/data byte
High-order address bus byte
Port A
16-bit Data Bus
Table2a.
PSD31XBus
and Port
Configuration
Options
Programmable
Address
Decoder (PAD)
Multiplexed Address/Data
'-bit Data Bus
Port A
I/O or low-order address
lines or Low-order multiplexed
address/data byte
DO-D7 data bus byte
Port B
I/O or CSO-CS7
I/O and/or CSO-CS7
ADO/Ao-AD7/A7
Low-order multiplexed
address/data byte
Low-order address bus byte
AS-A15
High-order address bus byte
High-order address bus byte
The PSD3XX consists of two programmable
arrays referred to as PAD A and PAD B
(Figure 3). PAD A is used to generate chip
select signals derived from the input
address to the internal EPROM blocks,
SRAM, I/O ports, and Track Mode signals.
All its I/O functions are listed in Table 3 and
shown in Figure 3. PAD B outputs to Ports B
and C for off-chip usage.
PAD B can also be used to extend the
decoding to select external devices or as a
random logiC replacement. The input bus
to both PAD A and PAD B is the same.
May, 1993
Non-Multiplexed Address/Data
12
Using MAPLE software, each
programmable bit in the PAD's array can
have one of three logic states of 0, 1, and
don't care (X). In a user's logic design,
both PADs can share the same inputs
using the X for input signals that are not
supposed to affect other functions. The
PADs use reprogrammable CMOS EPROM
technology and can be programmed and
erased by the user.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
PSD3XX Family
Flgurea.
PAD Description
~
J'\.
~
....
P,
v
~
....
Po
v
AL EarAS
ESO'
...
r.
ESl
ES2
..
ES3
ES4
..
~
8 EPROM BLOCK
S ELECT LINES
PAD
....
;;
-
ESS
ES6
....
;::;
~~~'-s RAM BLOCK SELECT
r.
CSIOPORT
CSADIN
~
V
DarE
>
A
~
V
orRiW ... _
"'4.{
A19
...
-....
....
~
CSOIPBO
...
...
-....
-
CS1/PBl
-
CS2IPB2
...
.....
~
A15
~
v
A14
V
D-
CS3IPB3
CS4/PB4
PAD
-
I
CSSlPB5
J
CS6IPB6
I
CS7/PB7
B
J'\.
h
~
V
RESET
"
h
~
A12
CSI
...
...
...
~
~
A13
All
.-
-
~
A16
TRACK MODE
CONTROL SIGNALS
.--
~
A17
CSADOUTl }
CSADOUT2
-....
,..
AlB
- va BASE ADDRESS
...
J'\.
-
;:;
..
~
~
..
..-
[>0[>0[>0-
CS8/PCO
eS9/pCl
CS101PC2
NOTES: 4. CSI is a power-down signal. When high, the PAD is in stand-by mode and all its outputs
become non-active. See Tables 12 and 13.
5. RESET deselects all PAD output signals. See Tables 10 and 11.
6. A18, A17, and A16 are internally multiplexed with CS10, CS9, and CS8, respectively.
Either A 18 or CS1 0, A 17 or CS9, and A 16 or CS8 can be routed to the external pins of
Port C. Port C can be configured as either input or output.
7. PO-P3 are not included on PSD3X1 devices.
May, 1993
13
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
Tabl.3.
PSD3XXPADA
andPADB
Functions
PSD3XX Family
Function
PAD A and PAD BInputs
A19/CSI
A16-A18
A11-A15
PQ-P3
RDorE
WRorRlW
ALE
RESET
In CSI mode (when high), PAD deselects all of its outputs and enters a
power-down mode (see Tables 12 and 13). In A19 mode, it is another
input to the PAD.
These are general purpose inputs from Port C. See Figure 3, Note 4.
These are address inputs.
These are page number inputs (for the PSD302/312/303/313 only).
This is the read pulse or enable strobe input.
This is the write pulse or RIW select signal.
This is the ALE input to the Chip.
This deselects all outputs from the PAD; it can not be used in product
term equations. See Tables 10 and 11.
PAD A Outputs
ESQ-ES7
RSO
CSIOPORT
These are internal chip-selects to the 8 EPROM banks. Each bank can
be located on any boundary that is a function of one product term of the
PAD address inputs.
This is an internal chip-select to the SRAM. Its base address location is
a function of one term of the PAD address inputs.
This internal chip-select selects the I/O ports. It can be placed on any
boundary that is a function of one product term of the PAD inputs. See
Tables 6 and 7.
CSADIN
This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the input
direction of Port A. CSADIN is gated externally to the PAD by the
internal read Signal. When CSADIN and a read operation are active, data
presented on Port A flows out of ADO/AO-AD7/A7. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure S.
CSADOUT1
This internal chip-select, when Port A is configured as a low-order
address/data bus in track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT1 is gated externally to the PAD by the ALE
signal. When CSADOUT1 and the ALE signal are active, the address
presented on ADO/AQ-AD7/A7 flows out of Port A. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure S.
CSADOUT2
This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT2 must include the write-cycle control
signals as part of its product term. When CSADOUT2 is active, the data
presented on ADO/AO-AD7/A7 flows out of Port A. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure S.
PAD B Outputs
MaY,1993
CSO-CS3
These chip-select outputs can be routed through Port B. Each of them is
a function of up to four product terms of the PAD inputs.
CS4-CS7
These Chip-select outputs can be routed through Port B. Each of them is
a function of up to two product terms of the PAD inputs.
CS8-CS10
These chip-select outputs can be routed through Port C. See Figure 3,
Note 4. Each of them is a function of one product term of the PAD inputs.
14
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
PSD3XX Family
Field-programmable microcontroller peripherals
Configuration
Bits
Table 4.
PSD3XX
Non- Volatile
Configuration
Bits
The configuration bits shown in Table 4 are
non-volatile cells that let the user set the
device, I/O, and control functions to the
proper operational mode. Table 5 lists all
configuration bits. The configuration bits
are programmed and verified during the
Use ThisBit
CDATA
CADDRDAT
CEDS
CA19/CSI
To
Set the data bus width to 8 or 16 bits (PSD30X only).
Set the address/data buses to multiplexed or non-multiplexed mode.
Determine the polarity and functionality of read and write. (Note 9)
Set A 19/CSI to CSI (power-down) or A 19 input.
CALE
Set the ALE polarity.
CPAF2
Set Port A either to track the low-order byte of the address/data
multiplexed bus or to select the I/O or address option.
CSECURITY
Set the security on or off (a secured part can not be duplicated).
CRESET
COMB/SEP
CPAF1
(8 Bits)
Set the RESET polarity.
Set PSEN and RD for combined or separate address spaces
(see Figures 9 and 10).
Configure each pin of Port A in multiplexed mode to be an I/O or
address out.
CPACOD
(8 Bits)
Configure each pin of Port A as an open drain or active CMOS
pull-up output.
CPBF
(8 Bits)
Configure each pin of Port B as an I/O or a chip-select output.
CPBCOD
(8 Bits)
Configure each pin of Port B as an open drain or active CMOS
pu II-up output.
CPCF
(3 Bits)
Configure each pin of Port C as an address input or a chip-select output.
CADDHLT
Configure pins A 16 - A 19 to go through a latch or to have their
latch transparent.
CADLOG
(4 Bits)
Configure A16 - A19 individually as logic or address inputs. (Note 9)
CATD
Configure pins A 16-A19 as PAD logic inputs or high-order address
inputs (Note 8).
CLOT
Determine in non-multiplexed mode if address inputs are transparent
or latched (Note 9).
CRRWR
Set the RD/E.,MId WR/vpp or RIW pins to RD and WR pulse, or to E
strobe and RIW status (Note 8).
CRRWR
Configure the polarity and control methods of read and write cycles.
(Note 9)
CMISER
Controls the lower-power mode.
9. PSD30213121303/313 only.
NOTES: 8. PSD31X only.
Port Functions
May, 1993
programming phase. In operational mode,
they are not accessible. To simplify
implementing a specific mode, use the
PSD3XX MAPLE software to set the bits.
The PSD3XX has three liD ports (Ports A,
B, and C) that are configurable at the bit
level. This permits great flexibility and a
high degree of customization for specific
15
applications. The following is a description
of each port. Figure 4 shows the pin
structu re of Port A.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
Figure 4.
PortA Pin
Structure
I
N
T
E
R
N
A
L
A
D
D
R
I
D
A
T
A
READ PIN
CMOSlOD(10)
WRITE DATA CK
OUT
OFF
DR
ENABLE
ALE
ADDR
G
MUX
LATCH
D
R
ADIIDI
B
U
S
A
D
0
I
A
D
7
PSD3XX Family
D
CONTROL
WRITEDIR
RESET
NOTE: 10. CMOS/OD determines whether the output is open drain or CMOS.
Figure 5.
PortA Track
Mode
WRorRiii
~I
CSADIN
ADO-AD7
PAO-PA7
INTERNAL
ALE
ALE or AS
AD8-AD15
CSADOUT2
(11)
A16-A19
NOTE: 11. The expression for CSADOUT2 must include the following write operation cycle signals:
For CRRWR = 0, CSADOUT2 must include WR = O.
For CRRWR = 1, CSADOUT2 must include E = 1 and RIW = O.
MaY,1993
16
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD3XX Family
Field-programmable microcontroller peripherals
Table 5.
PSD3XX
Configuration
Bits 12. 13
No.
Configuration
of Bits
Bits
CDATA
(Note 14)
1
a-bit or 16-bit Data Bus Width
CDATA = eight bits
CDATA = 1 sixteen bits
CADDRDAT
1
ADDRESSIDATA Multiplexed (separate buses)
CADDRDAT = 0, non-multiplexed
CADDRDAT = 1, multiplexed
CA19/CSI
1
A190rCSI
CA19/CSI = 0, enable power-down
CA 19/CSI = 1, enable A 19 input to PAD
CALE
1
Active HIGH or Active LOW
CALE = 0, Active high
CALE = 1 , Active low
CRESET
1
Active high or active low
CRESET = 0, active low reset signal
CRESET = 1, active high reset signal
COMB/SEP
1
Combined or Separate Address Space
for SRAM and EPROM
0= Combined, 1 = Separate
CPAF1
a
Port A II0s or AO-A7
CPAF1 = 0, Port A pin = 1/0
CPAF1 = 1, Port A pin = AO - A7
CPAF2
1
Port A ADO-AD7 (address/data multiplexed bus)
CPAF2 = 0, address or 1/0 on Port A (according to CPAF1)
CPAF2 = 1, addressldata multiplexed on Port A (track mode)
CATD·
(Note 16)
1
A 16-A19 address or logic inputs
CATD = 0, logic inputs
CATD = 1, address inputs
CADDHLT
1
A 16-A19 Transparent or Latched
CADDHLT = 0, Address latch transparent
CADDHLT = 1, Address latched (ALE dependent)
CSECURITY
1
SECURITY OnlOff
CSECURITY = 0, off
CSECURITY = 1, on
1
AO-A15 Address Inputs are transparent or
ALE-dependent in non-multiplexed modes
CLOT = 0, transparent
CLOT = 1, ALE-dependent
CRRWR
CEDS
(Note 15)
2
Determine the polarity and control methods of read and
write cycles.
CRRWR
CEDS
RD and WR active low pulses
1
RIW status and high-E,.pulse
RIW status and low DS pulse
1
1
CRRWR
(Note 16)
1
CRRWR = 0, RD and WR active low strobes
CRRWR = 1, R/W status and E active high pulse
CPACOD
a
Port A CMOS or Open Drain Output
CPACOD = 0, CMOS output
CPACOD = 1, open-drain output
CLOT
(Note 15)
May. 1993
Function
°
°°
17
°
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
Table 5.
PSD3XX
Configuration
Bits (Cont.)
Configuration
Bits
Function
CPBF
8
Port B is 1/0 Of Csa- CS7
CPBF = 0, Port B pin is CSO - CS7
CPBF = 1, Port B pin is 1/0
CPBCOD
8
Port B CMOS or Open Drain
CPBCOD = 0, CMOS output
CPBCOD = 1, open-drain output
CPCF
3
Port C A16-A18 or CS8-CS10
CPCF = 0, Port C pin is A16-A18
CPCF = 1, Port C pin is CS8-CS10
CADLOG
(Note 15)
4
Port C: A16-A19 Address or Logic Input
CADLOG = 0, Port C pin or A19/CSl is logic input
CADLOG = 1, Port C pin or A 19/CSl is address input
CMISER
1
Default: CMISER = 0
CMISER = 1, lower-power mode
NOTES: 12.
13.
14.
15.
16.
Port Functions
(Cont.)
No.
of Bits
The Maple software will guide the user to the proper configuration choice.
In an unprogrammed or erased part, all configuration bits are O.
PSD30X only.
PSD3X213X3 only.
PSD3X1 only.
Port A in Multiplexed
Address/Data Mode
The default configuration of Port A is 1/0. In
this mode, every pin can be set as an input
or output by writing into the respective pin's
direction flip flop (DIR FF, in Figure 4). As
an output, the pin level can be controlled by
writing into the respective pin's data flip flop
(OFF, in Figure 4). When DIR FF = 1, the
pin is configured as an output. When DIR
FF = 0, the pin is configured as an input.
The controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the OFF bits by accessing the READ
DATA register. Port A pin levels can be read
by accessing the READ PIN register.
Individual pins can be configured as CMOS
or open drain outputs. Open drain pins
require external pull-up resistors. For
addressing information, refer to Tables 6
and 7.
Alternatively, each bit of Port A can be
configured as a low-order latched address
bus bit. The address is provided by the port
address latch, which latches the address on
the trailing edge of ALE. PAO-PA7 can
become AO-A7, respectively. This feature
enables the user generate low-order
address bits to access external peripherals
or memory that require several low-order
address lines.
May, 1993
PSD3XX Family
18
Another mode of Port A (CPAF2 = 1) sets
the entire port to track the inputs
ADO/AO-AD7/A7, depending on specific
address ranges defined by the PAD's
CSADIN, CSADOUT1, and CSADOUT2
signals. This feature lets the user interface
the microcontroller to shared external
resources without requiring external buffers
and decoders. In this mode, the port is
effectively a bi-directional buffer. The
direction is controlled ~using the input
signals ALE, ROlE or RO/E/OS, WR/vpp or
RIW, and the internal PAO outputs
CSAOOUT1, CSADOUT2 and CSAOIN
(see Figure 5). When CSADOUT1 and ALE
are true, the address on the input
AOO/AO-A07/A7 pins is output through Port
A. (Carefully check the generation of
CSAOOUT1, and ensure that it is stable
during the ALE pulse. When CSADOUT2 is
active, a write operation is performed (see
note to Figure 5). The data on the input
AOO/AO-A07/A7 pins flows out through
Port A. When CSADIN and a read operation is performed (depending on the mode
of the ROlE or RO/E/OS, and WRlVpp or
RIW pins), the data on Port A flows out
through the ADO/AO-AD7/A7 pins. In this
operational mode, Port A is tri-stated when
none of the above-mentioned three
conditions exist.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
Port Functions
(Cont.)
Port A in Non-Multiplexed
Address/Data Mode
Accessing the YO Port Registers
In this mode, Port A becomes the low order
data bus byte of the chip. When reading an
internal location, data is presented on Port
A pins. When writing to an internal location,
data present on Port A pins is written to
that location.
Port B in Multiplexed Address/Data
and in a-Bit Non-Multiplexed Modes
The default configuration of Port B is I/O. In
this mode, every pin can be set as an input
or output by writing into the respective pin's
direction flip flop (DIR FF, in Figure 6). As
an output, the pin level can be controlled by
writing into the respective pin's data flip flop
(OFF, in Figure 6). When DIR FF = 1, the
pin is configured as an output. When DIR
FF = 0, the pin is configured as an input.
The controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the OFF bits by accessing the READ
DATA register. Port B pin levels can be
read by accessing the READ PIN register.
Individual pins can be configured as CMOS
or open drain outputs. Open drain pins
require external pull-up resistors. For
addressing information, refer to Tables 6
and 7.
Alternately, each bit of Port B can be
configured to provide a chip-select output
signal from PAD B. PBQ-PB7 can provide
CSO-CS7, respectively. Each of the signals
CSO-CS3 is comprised of four product
terms.Thus, up to four ANDed expressions
can be ORed while deriving ~of these
signals. Each of the signals CS4-CS7 is
comprised of two product terms. Thus, up
to two ANDed expressions can be ORed
while deriving any of these signals.
Port B in 16-Bit Non-Multiplexed
Address/Data Mode
(PSD30Xj
In this mode, Port B becomes the highorder data bus byte of the chip. When
reading an internal high-order data bus
byte location, the data is presented on Port
B pins. When writing to an internal highorder data bus byte location, data present
on Port B is written to that location. See
Table 9.
May, 1993
PSD3XX Family
19
Tables 6 and 7 show the offset values with
the respect to the base address defined by
the CSIOPORT. They let the user access
the corresponding registers.
Port C in All Modes
Each pin of Port C (shown in Figure 7) can
be configured as an input to PAD A and
PAD B or output from PAD B. As inputs,
the pins are named A 16-A1S. Although the
pins are given names of the high-order
address bus, they can be used for any
other address lines or logic inputs to PAD A
and PAD B. For example, AS-A 10 can also
be connected to tho~ns, improving the
boundaries of CSo-CS7 resolution to 256
bytes. As inputs, they can be individually
configured to be logic or address inputs. A
logic input uses the PAD only for Boolean
equations that are implemented in any or
all of the CSO-CS10 PAD B outputs. Port C
addresses can be programmed to latch the
inputs by the trailing edge ALE or to be
transparent.
Alternately, PCO-PC2 can become
CSS-CS10 outputs, respectively, providing
the user with more external chip-select
PAD outputs. Each of the signals
CSS-CS10 is comprised of one product
term.
ALE/AS and ADO/AD-AD15/A15 in
Non-Multiplexed Modes
In non-multiplexed modes,
ADO/AQ-AD15/A15 are address inputs only
and can become transparent (CLOT = 0) or
ALE dependent (CLOT = 1). In transparent
mode, the ALEIAS pin can be used as an
additional logic input to the PADs. The nonmultiplexed ALE dependent mode is useful
in applications for which the host processor
has a multiplex address/data bus and
ADO/AO-AD7/A7 are not multiplexed with
AO-A7 but rather are multiplexed with other
address lines. In these applications, Port A
serves as a data bus and each of its pins
can be directly connected to the corresponding host's multiplexed pin, where that
data bit is expected.
(See Table S.)
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
PSD3XX Family
Figure 6.
PortB Pin
Structure
REAOPIN
I
N
T
E
R
N
A
L
c
S
o
U
~
I
N
T
E
R
N
A
L
REAOOATA
CMOSI00(17)
WRITEOATA CK
0
0
A
T
A
H}
OUT...
~
OFF
R
I
01
.
CSi
...
T
.~
PORTB PIN
ENABLE
MUX
B
B
U
U
S
S
~
c
o
0
0
1
7
J Il
REAOOIR
8
S
o
WRITEOIR
5
DPll
~ Il
CONTROL
CK FF
R
I
RESET
NOTE:
Tab/e6.
//0 Port
Addresses In an
8-blt Data Bus
Mode
Tab/e 7.
//0 Port
Addresses In a
16-b/t Data Bus
Model', 19
(PSD30X)
17. CMOS/OD determines whether the output is open drain or CMOS.
Byte Size Access of the I/O Port Registers
Offset from the CSIOPORT
Register Name
Pin Register of Port A
+ 2 (accessible during read operation only)
Direction Register of Port A
+4
Data Register of Port A
+6
Pin Register of Port B
+ 3 (accessible during read operation only)
Direction Register of Port B
+5
Data Register of Port B
+7
Page Register
+18
Word Size Access of the VO Port Registers
Offset from the CSIOPORT
Register Name
Pin Register of Ports B and A
+ 2 (accessible during read operation only)
Direction Register of Ports B and A
+4
Data Register of Ports B and A
+6
NOTES: 18. When the data bus width is 16, Port B registers can only be accessed if the BHE
signal is low.
19. I/O Ports A and B are still byte-addressable, as shown in Table 6. For I/O Port B register
access, BHE must be low.
May, 1993
20
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripherals
Figure 7.
Port C Structure
PSD3XX Family
ADDRESS INDICATOR
(NOTE 20)
A16
! - - -.... TOPAD
CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL
~~==~~~----------FROMPAD
.-----.
ALE
PC1
A17
!---"'TOPAD
1
.....!-=C;.:;;S9::..1(..:,O;:;.,:UT:..:..P;:;..UT:..,:L:.::,.IN:.=,El'--_ _ _ _ _ FROM PAD
.__...i--..,
PC21
A18
i - - -.... TOPAD
.......:::C:.:::.S1~O...l.::(O~U:.:.:TP..:::U:.:..T.=:LI~NE;L.)_ _ _ _ _ FROM PAD
.-----.
TO
EPROM
NOTES: 20. The CADDHLT configuration bit determines if A 18-A16 are transparent via the latch, or if
they must be latched by the trailing edge of the ALE strobe.
21. PSD3X2/3X3: Individual pins can be configured independently as address or logic
inputs (CADLOG, bits 0-2).
PSD3X1 : All Port C pins are either address or logic inputs (CATD).
Port Functions
(Cont.)
May, 1993
ALE/AS and ADD/AD-AD15/A15 in
Non-Multiplexed Modes
(PSD3X2/3X3)
ALE/AS and ADD/AD-AD7/A7 in
Non-Multiplexed Modes
(PSD31X)
In non-multiplexed modes,
ADO/AO-AD15/A15 are address inputs only
and can become transparent (CLOT = 0) or
ALE dependent (CLOT = 1). In transparent
mode, the ALE/AS pin can be used as an
additional logic input to the PADs. The nonmultiplexed ALE dependent mode is useful
in applications for which the host processor
has a multiplex address/data bus and
ADO/AO-AD7/A7 are not multiplexed with
AD-A7 but rather are multiplexed with other
address lines. In these applications, Port A
serves as a data bus and each of its pins
can be directly connected to the corresponding host's multiplexed pin, where that
data bit is expected. (See Table 8.)
In non-multiplexed modes, AO-A 15 are
address inputs only and can become
transparent (CLOT = 0) or ALE dependent
(CLOT = 1). In transparent mode, the
ALE/AS pin can be used as an additional
logic input to the PADs. The non-multiplexed ALE dependent mode is useful in
applications for which the host processor
has a multiplex address/data bus and
ADO/AO-AD7/A7 are not multiplexed with
AO-A7 but rather are multiplexed with other
address lines. In these applications, Port A
serves as a data bus and each of its pins
can be directly connected to the corresponding host's multiplexed pin, where that
data bit is expected. (See Table 8.)
21
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
A16-A19
Inputs
EPROM
PSD3XX Family
If one or more of the pins PCO, PC1 PC2
and CSI/A19 are configured as inputs, the
configuration bits CADDHLT and CATD
define their functionality inside the part.
CADDHLT determines if these inputs are to
be latched by the trailing edge of the
ALE or AS signal (CADDHLT = 1), or
enabled into the PSD3XX at all times
(CADDHLT = 0, transparent mode). CATD
determines whether these lines are highorder address lines, that take part in the
derivation of memory and I/O select
signals inside the chip (CATD = 1), or logic
input lines that have no impact on memory
or I/O selections (CATD = 0). Logic input
lines typically participate in the Boolean
expressions implemented in the PAD.
The EPROM has 8 banks of memory. Each
bank can be placed in any address location
by programming the PAD. BankO-Bank7
is selected by PAD outputs ESO-ES7,
respectively.
Device
EPROM
Size
EPROM
Architecture
EPROM Bank
Architecture
(Bea)
xB
x16
xB
x16
PSD301
256Kb
32Kx8
16K x 16
4Kx8
2Kx 16
PSD311
256Kb
32K x8
-
4Kx8
-
PSD302
512Kb
64Kx8
32K x 16
8Kx8
4Kx 16
PSD312
512Kb
64Kx8
-
8Kx8
-
PSD303
1Mb
128K x 8
64K x 16
16K x8
8Kx 16
PSD313
1Mb
128K x 8
-
16K x 8
-
SRAM
Each PSD3XX device has 16K bits of
SRAM. Depending on the configuration of
the data bus, the SRAM organization can
be 2K x 8 (8-bit data bus) or 1K x 16 (16-bit
data bus). The SRAM is selected by the
RSO output of the PAD.
Memory Paging
The page register consists of four
flip-flops, which can be read from, or
written to, through the 1/0 address space
(CSIOPORT). The page register is
connected to the D3-DO lines. The Page
Register address is CSIOPORT + 18H. The
page register outputs are P3-PO, which are
fed into the PAD. This enables the host
microcontroller to enlarge its address
space by a factor of 16 (there can be a
maximum of 16 pages). See Figure 8.
(PSD3X213X3)
May, 1993
22
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
F/gure8.
Page Reg/ster
(PSD3X2/3X3)
PSD3XX Family
~--~----------------------~~}roP~
~--'""'t"""'-------------Pl
INPUTS
,....--....---PO
INTERNAL
RESET
INTERNALWR
PAGE SELECT
INTERNAL RD
~2
ADl
ADO
)
V
DATA BUS
Tab/eS.
Signal Latch
Status /n All
Operating Modes
Signal
Name
Configuration
Bits
CDATA , CADDRDAT, CLOT = 0
C DATA , CADDRDAT
AD8/A8AD15/A15
ADO/AOAD7/A7
CDATA
= 1, CADDRDAT, CLOT = 0
CDATA
= 1, CADDRDAT = 0, CLOT = 1
CDATA
CDATA
A19 and
PC2-PCO
1993
Transparent
ALE
Dependent
Transparent
ALE
Dependent
= 0, CADDRDAT = 1
8-bit data,
multiplexed
Transparent
= 1, CADDRDAT = 1
16-bit data,
multiplexed
ALE
Dependent
= 0, CLOT = 0
CADDRDAT
= 0, CLOT = 1
CADDRDAT
=1
non-multiplexed
modes
Transparent
ALE
Dependent
multiplexed modes
ALE
Dependent
=0
8-bit data,
PSEN is active
Transparent
CDATA
= 1, CADDRDAT = 0
16-bit data,
non-multiplexed
mode,
SHE is active
Transparent
CDATA
= 1, CADDRDAT = 1
16-bit data,
multiplexed mode,
SH E is active
ALE
Dependent
A16-A19 can
become logic inputs
Transparent
CADDHLT
CADDHLT
May.
8-bit data,
non-multiplexed
Signal Latch
Status
16-bit data,
non-multiplexed
CADDRDAT
CDATA
SHE/
PSEN
= 0, CLOT = 1
Configuration
Mode
=0
A16-A19 can
become multiplexed
address lines
=1
23
ALE
Dependent
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD3XX Family
Field-programmable microcontroller peripherals
Control Signals
The PS03XX control signals are WR/vpp
or R/W, ROlE or ROlE/OS, ALE,
BHE/PSEN or PSEN, RESET, and
A19/CSI. Each of these signals can be
configured to meet the output control signal
requirements of various microcontrollers.
WR/Vpp or R/W
In operational mode, this signal can be .
configured as WR or RIW. As WR, all write
operations are activated by an active low
signal on this pin. As RIW, the.,2!.n 0Rerates
with the E strobe of the ROlE/OS or ROlE
pin. When RIW is h!9!!, an active high
signal on the ROlE/OS or ROlE pin _
performs a read operation. When R/W ~
low, an active high signal on the ROlE/OS
or ROlE pin performs a write operation.
RD/E/DS (or ROlE on PSD3X1)
In operational mode, this signal can be
configured as RO, E, or OS. As RO, all
read operations are activated by an active
low signal on this pi~As E, the pin
~rates with..!!!e R/W signal of t.he .
WR/Vpp or R/W pin. Whe~R/W~ high, an
active high signal on the RO/EIDS pin
performs a read operation. When R/W ~
low, an active high signal on the ROlE/OS
pin performs a write operation.
As OS, the pin functions with the RIW
signal as an active low data strobe signal.
As OS, the R/W defines the mode of
operation (Read or Write).
May,1993
SHE/PSEN
This pin's function depends on the
PS03XX data bus width. If it is 8 bits, the
pin is PSEN; if it is 16 bits, the pin is BHE.
In 8-bit mode, the PSEN function enables
the user to work with two address spaces:
program memory and data memory
(if COMB/SEP = 1). In this mode, an active
low signal on the PSEN pin causes the
EPROM to be read if selected. The SRAM
and 1/0 ports read operation are done
by RO low (CRRWR = 0), or by E high and
R/W hla!:! (CRRWR = 1, CEOS = 0)
or by OS low and RIW high (CRRWR,
CEOS = 1).
Whenever a member of the 8031 family
(or any other similar microcontroller) is
used, the PSEN pin must be connected to
the PSEN pin of the microcontroller.
If COMB/SEP = 0, the address spaces of
the program and the data are combined. In
this configuration (except for the 8031-type
case mentioned above), the PSEN pin
must be tied high to Vcc, and the EPROM,
SRAM, and 1/0 ports are read by RO low
(CRRWR = 0), or by E high andj!IW high
(CRRWR = 1, CEOS = 0) or by OS low and
R/W high (CRRWR, CEOS = 1). See
Figures 9 and 10.
In SHE mode, this pin enables accessing of
the upper-half byte of the data bus. A low
on this pin enables a write or read
operation to be performed on the upper half
of the data bus (see Table 9).
ALE or AS
RESET
ALE polarity is programmable. When
programmed to be active high, a high on
the pin causes the input address latches,
Port A address latches, Port C, and A19
address latches to be transparent. The
falling edge of ALE locks the information
into the latches. When ALE is programmed
to be active low, a low on the pin causes
the input address latches, Port A address
latches, Port C, and A19 address latches to
be transparent. The rising edge of ALE
locks the appropriate information into the
latches.
This is an asynchronous input pin that
clears and initializes the PS03XX. Reset
polarity is programmable (active low or
active high). Whenever the PS03XX reset
input is driven active for at least 100 ns, the
chip is reset. The PS03XX must be reset
before it can be used. Tables 10a, 10b and
11 indicate the state of the part during and
after reset.
24
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD3XX Family
Field-programmable microcontroller peripherals
Control Signals
(Cont.)
In A19 mode, the pin is an additional input
to the PAD. It can be used as an address
line (CADLOG3 = 1) or as a generalpurpose logic input (CADLOG3 = 0). A19
can be configured as ALE dependent or as
transparent input (see Table 8). In this
mode, the chip is always enabled.
A19/CSI
When configured as CSI, a high on this pin
deselects, and powers down, the chip. A
low on this pin puts the chip in normal
operational mode. For PSD3XX states
during the power-down mode, see Tables
12 and 13, and Figure 11.
Figure 9.
Combined
Address Space
s
ADDRESS --".~I
PAD
.
a
SRAM
OE
INTERNAL RD
CS OE
1/0 PORTS
Table 9.
Hlgh/Low Byte
Selection Truth
Table (In 16-Blt
Configuration
Only)
May. 1993
Operation
SHE
Ao
0
0
0
1
Upper Byte FromlTo Odd Address
1
0
Lower Byte FromlTo Even Address
1
1
None
Whole Word
25
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
Figure 1D.
BD31-Type
Separate Code
and Data
Address Spaces
PSD3XX Family
INTERNALRD
OE
ADDRESS-....~
cs
PAD
SRAM
L....-----I~CS
EPROM
PSEN
~~---------I~OE
Table 10a.
Signal States
During Reset
Cycle (RESET)
Table 10b.
Signal States
After Reset Cycle
(RESET)
Signal
Condition
ADOIAO-AD15/A 15
Input
PAO-PA7 (Port A)
Input
PBQ-PB7 (Port B)
Input
PCQ-PC2 (Port C)
Input
Signal
Condition
ADO/AQ-AD71A 7
All
Input
A8-A15
All
Input
1/0
Input
Input
Low
PAQ-PA7)
(Port A
PBQ-PB7
(Port B)
PCO-PC2
(Port C)
May. 1993
Configuration Mode
Tracking ADO/AO-AD7
Address outputs AQ-A7
1/0
CS7-CSO CMOS outputs
CS7-CSO open drain outputs
Input
High
Tri-stated
Address inputs A16-A18
CS8-CS10 CMOS outputs
Input
High
26
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripherals
Table 11.
Internal States
DurIng and After
Reset Cycle
Component
PSD3XX Family
Signals
PAD
Contents
CSO-CS10
All = 1 (Note 22)
CSADIN, CSADOUT1,
CSADOUT2, CSIOPORT,
RSO, ESO - ES7
All = 0 (Note 22)
nfa
nfa
Data register A
Direction register A
Data register B
Direction register B
0
0
0
0
n/a
n/a
NOTE: 22. All PAD outputs are in a non-active state.
FIgure 11.
A191CSI Cell
Structure
ADDRESS INDICATOR
TO EPROM
(NOTE 23)
CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL
ALE-------------------,
-----..
i
-r~.
A19/CSI-
CSI (POWER-UP SIGNAL)
_..;...;;..;.~...;.;..;;...;.....;..;....;..;---....;;.:..----------___...
JooI','
.,..,;
!~
NOTES:
May, 1993
A19
1-------+-. TO PAD
TO PAD, EPROM, SRAM,
PORTS, LATCHES, ETC.
23. The CADDHLT configuration bit determines if A 19-A 16 are transparent via the latch,
or if they must be latched by the trailing edge of the ALE strobe.
27
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
Table 12a. Signal
States During
Power-Down
"ode
(PSD30X)
Table 12b.
Signal States
During PowerDown"ode
(PSD31X)
Table 13.
Interna/ States
During PowerDown
Condition
ADO/AD-AD15/A 15
All
Input
PAD-PA7
I/O
Tracking ADO/AD-AD7/A7
Address outputs AO-A7
Unchanged
Input
A1I1's
PBD-PB7
I/O
CSO-CS7 CMOS outputs
CSO-CS7 open drain outputs
Unchanged
A1I1's
Tri-stated
PCD-PC2
Address inputs A18-A16
CS8-CS 10 CMOS outputs
Input
A1I1's
Configuration Ifode
Signal
Condition
ADO/AD-AD7/A7
All
Input
A8-A15
All
PAD-PA7
I/O
Tracking ADO/AO-AD7/A7
Address outputs AD-A7
Input
Unchanged
Input
A1I1's
PBD-PB7
I/O
CSD-CS7 CMOS outputs
CSO-CS7 open drain outputs
Unchanged
A1I1's
Tri-stated
PCD-PC2
Address inputs A 18-A16
CS8-CS10 CMOS outputs
Input
A1I1's
Signals
Component
PAD
Data register A
Direction register A
Data register B
Direction register B
May, 1993
Configuration Ifode
Signal
PSD3XX Family
Contents
CSO-CS10
All 1's (deselected)
CSADIN, CSADOUT1 ,
CSADOUT2, CSIOPORT,
RSO,ESO-ES7
All O's (deselected)
n/a
n/a
n/a
n/a
All
unchanged
28
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
PSD3XX Family
Figure 12.
PSD3XX
Vee
Intedace With
Inters 8OC31
MICROCONTROLLER
po.o
31
-
EANP
19
PO.1
PO.2
PO.3
PO.4
PO.S
PO.6
PO.7
X1
X2
RESET
P2.0
P2.1
P2.2
P2.3
P2.4
P2.S
P2.6
P2.7
INTO
INT1
TO
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.S
P1.6
P1.7
8
RD
WR
PSEN
ALE
TXD
RXD
39
38
37
36
35
34
33
32
23
24
25
26
27
28
29
30
21
22
23
24
25
26
27
28
31
32
33
35
36
37
38
39
17
16
29
30
11
10
22
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
ADS/AS
AD6IA6
AD7/A7
PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7
AD8/AS
AD9/A9
AD1 0/A1 0
AD11/A11
AD121A12
AD13/A13
AD141A14
AD15/A1S
PBO
PB1
PB2
PB3
PB4
PBS
PBS
PB7
RD
PCO
PC1
2 WR/Vpp
1
BHEIPSEN
13
ALE
3
RESET
GND
PSD3XX
80C31
PC2
A19/CSI
34
12
-
NOTE: RESET to the PSD3XX must be the output of a RESET chip or buffer.
If RESET is the output of an RC circuit, a separate buffered RC RESET to the PSD3XX
(shorter than the 80C31 RC RESET) must be provided to avoid a race condition.
The configuration bits for Figure 12 are:
CALE
0
COMB/SEP
oor 1 (both valid)
CDATA
0
CRRWR
o
o
CADDRDAT
CEDS
CRESET
All other configuration bits may vary according to the application requirements.
System
Applications
May,
1993
In Figure 12, the PSD3XX is configured to
interface with Intel's 80C31 , which is a 16bit address/8-bit data bus microcontroller.
Its data bus is multiplexed with the loworder address byte. The 80C31 uses
signals RD to read from data memory and
PSEN to read from code memory. It uses
WR to write into the data memory. It also
uses active high reset and ALE signals.
The rest of the configuration bits as well as
the unconnected signals (not shown) are
application specific and, thus, user
dependent.
29
In Figure 13, the PSD3XX is configured to
interface with Motorola's 68HC 11, which
is a 16-bit address/8-bit data bus
microcontroller. Its data bus is multiplexed
with the low-order address byte. The
68HC11 uses E and RIW signals to derive
the read and write strobes. It uses the term
AS (address strobe) for the address latch
pulse. RESET is an active low Signal. The
rest of the configuration bits as well as the
unconnected signals (not shown) are
specific and, thus, user dependent.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
PSD3XX Family
Figure 13.
Vee
PSD3XX
Interface With
Motorola's
6BHC11
MICROCONTROLLER
PCO
PC1
PC2
PC3
PC4
PCS
PC6
PC7
PDQ
PD1
PD2
PD3
PD4
PD5
PEO
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PBO
PB1
PB2
PB3
PB4
PB5
PBS
PB7
PAO
PA1
PA2
PA3
PM
PAS
PAS
PA7
9
10
11
12
13
14
15
16
23
24
25
26
27
28
29
30
42
41
40
39
38
37
36
35
31
32
33
35
36
37
38
39
5
22
6
4
17
2
13
3
1
E
RIW
AS
RESET
XIRQ
IRQ
MODB
MODA
VRH
VRL
XTAL
18
19
2
3
ADO/AO
AD1/A1
AD2IA2
AD3/A3
AD4IA4
AD5/A5
AD6IA6
AD7/A7
PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7
ADS/AS
AD9/A9
AD10/A10
AD12/A12
AD13/A13
AD14/A14
AD15/A15
PBO
PB1
PB2
PB3
PB4
PB5
PBS
PB7
E
PCO
AD11/A11
AS
PC2
A19/CSI
RESET
BHEIPSEN
Vee
GND
EXTAL
PSD3XX
68HC11
PC1
RiViNpp
34 12
-::-
The configuration bits for Figure 13 are:
CALE
CDATA
CADDRDAT
CRESET
0
0
COMB/SEP
CRRWR
CEDS
0
1
0
0
All other configuration bits may vary according to the application requirements.
System
Applications
(Cont.)
May, 1993
In Figure 14, the PSD3XX is configured to
work directly with Intel's 80C196KB microcontroller, which is a 16-bit address/16-bit
data bus processor. Address and data lines
multiplexed. In the example shown, all
configuration bits are set. The PSD3XX is
configured to use PCO, PC1, PC2, and
CSI/A19 as A16, A17, A18, and A19
inputs, respectively. These signals
are independent of the ALE pulse (Iatchtransparent). They are used as four
general-purpose logic inputs that take part
in the PAD equations implementation.
30
Port A is configured to work in the special
track mode, in which (for certain conditions)
PAO-PA7 tracks lines ADO/AO-AD7/A7.
Port B is configured to generate CSO-CS7.
In this example, PB2 serves as a WAIT
Signal that slows down the 80C196KB
during the access of external peripherals.
These 8-bit wide peripherals are connected
to the shared bus of Port A. The WAIT
signal also drives the buswidth input of the
microcontroller, so that every external
peripheral cycle becomes an 8-bit data bus
cycle. PB3 and PB4 are open-drain output
signals; thus, they are pulled up externally.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripherals
PSD3XX Family
Figure 14.
PSD3XX Interface With Intel's BOC196KB.
+5V
C
6
T
NMI
67
XTAl1
66
XTAl2
3
~
~
rit
r---
i----c
i----c
~
~
~
i----c
1--4
a....--
~
~
§
~
+5V~
TO'"
PO.O
PO.l
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
18
17
15
44
P2.OJTXD
P2.1/RXD
P2.2lEXINT
P2.3IT2CLK
P2.4iT2RST
P2.51PWM
P2.6IT2 UPION
P2.71T2CAPTR
......g..
39
33
38
19
20
21
22
23
30
31
32
P3.OJADO
P3.1/ADl
P3.21AD2
P3.3IAD3
P3.4/AD4
P3.5IAD5
P3.61AD6
P3.7/AD7
60
59
58
57
56
55
54
53
ADOJAO
ADl/Al
AD2IA2
AD3IA3
AD4/A4
AD5IA5
AD6IA6
AD7/A7
P4.OJAD8
P4.1/AD9
P4.21AD10
P4.3/ADll
P4.41AD12
P4.51AD13
P4.61AD14
P4.7/AD15
52
51
AD8IA8
AD9IA9
S(
AU10/AH -~
49
48
47
46
45
ADll/All
~
AD121A12-'"
AD131A13 ~
AD14/A14
I\,.
AD151A15./
NMI
READY
BUSWIDTH
CDE
RESET
24
25
26
27
HSI.O
HSI.1
HSI.21HSO.4
HSI.3IHSO.5
13
37
VREF
VPP
ANGND
~
~ EA
0.11'F ::::::
8OC196KB
Vas
1:
CLKOur
BHEiWRH
"WR-WRi.
Vss
~
~
44
~i'\..
./~
-"'i'\..
-"'1\.:
I\.:
~
I\.:
I\.:
I\.:
,
~
~
~
41
c::::: 40
~
0
X
.~
ADO/AO 23
ADl/Al 24
AD2IA2 25
AD3IA3 26
AD4/A4 27
AD5IA5 28
AD6IA6 29
AD7/A7 30
AD8/Ali 31
AD9/A9 32
AD1OJA1033
ADll/A1135
AD121A1236
AD131A1337
AD14/Al438
AD151A1539
ADOJAO
ADl/Al
AD2IA2
AD3IA3
AD4IA4
AD5IA5
AD6IA6
AD7/A7
AD8IA8
AD9IA9
AD10/A10
AD11/Al1
AD121A12
AD131A13
AD14/A14
AD151A15
40
41
~
~
-4~
--#-2L-
1
2
22
13
3
6
PAO
PAl
PA2
PA3
PM
PAS
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PBS
PBS
PB7
PCO
PCl
PC2
CSI/A19
'SHARED
BUS
1
21
20
19
18
~
~
~
17
16
15
14
11
10
9
8
7
6
'WlII!'
~
r--!-
4.71<0
~
.
-c=::>
~
"'L-->
~ ~4.71
110 PINS
AD ~61
62
AlEIADV
INST ~
HSO.O
HSO.1
HSO.2
HSO.3
ADO .. 15
ADDRESSIOATA MULTIPLEXED BUS
}~,
Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.5
Pl.6
Pl.7
Vee
6
5
7
4
11
10
8
9
AD(O .. 15J
~
GND
GND
UJ~
2
4
'-----'
-cm::::>
The configuration bits for Figure 14 are:
CALE
CDATA
CADDRDAT
CPAF1
CPAF2
CA19/CSI
CRRWR
COMB/SEP
CADDHLT
CRESET
May, 1993
o
1
1
Don't care
1
1
o
o
o
o
31
CSECURITY
CPCF2, CPCF1 , CPCFO
CPACOD7-CPACODO
CPBF7-CPBFO
CPBCOD7-CPBCODO
CEDS
CADLOG3-CADLOGO
Don't care
0,0,0
OOH
OOH
18H
o
OH
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripherals
May, 1993
32
PSD3XX Family
Philips Semiconductors Mlcrocontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Key Features
a
o
-
a
-
a
-
o
-
May, 1993
Single Chip Programmable Peripheral
for Microcontroller-based Applications
19 Individually Configurable I/O pins
that can be used as:
Microcontroller I/O port expansion
Programmable Address Decoder
(PAD) I/O
Latched address output
Open drain or CMOS
Two Programmable Arrays
(PAD A and PAD B)
Total of 40 Product Terms and up to
16 Inputs and 24 Outputs
Address Decoding up to 1 MB
Logic replacement
"No Glue" Microcontroller Chip-Set
Built-in address latches for multiplexed
address/data bus
Non-multiplexed address/data bus
mode
Selectable 8 or 16 bit data bus width
ALE and Reset polarity programmable
Selectable modes for read and write
control bus as RDIWR or RIW/E
BHE pin for byte select in 16-bit mode
PSEN pin for 8051 users
256 Kbits of UV EPROM
Configurable as 32K x 8 or as 16K x 16
Divides into 8 equal mappable blocks
for optimized mapping
Block resolution is 4K x 8 or 2K x 16
120 ns EPROM access time, including
input latches and PAD address
decoding.
33
a
-
o
-
o
-
a
-
PSD301
16 Kbit Static RAM
Configurable as 2K x 8 or as 1K x 16
120 ns SRAM access time, including
input latches and PAD address
decoding
Address/Data Track Mode
Enables easy Interface to Shared
Resources (e.g., Mail Box SRAM) with
other Microcontrollers or a Host
Processor
Built-In Security
Locks the PSD301 and PAD Decoding
Configuration
Available in a Choice of Packages
44 Pin PLCC and CLCC
52 Pin PQFP
o
Simple Menu-Driven Software:
Configure the PSD301 on an IBM PC
o
Pin Compatible with the PSD3XX and
PSD3XXL Family
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
Security
Mode
Security Mode in the PSD3XX locks the
contents of the PAD A , PAD B and all the
configuration bits. The EPROM, SRAM,
and 1/0 contents can be accessed only
through the PAD. The Security Mode can
be set by the MAPLE or Programming
software. In window packages, the mode is
erasable through UV full part erasure. In
the security mode, the PSD3XX contents
cannot be copied on a programmer.
eMlser-BIt
The CMiser-Bit provides a programmable
option for power-sensitive applications that
require further reduction in power
consumption. The CMiser-Bit (CMiser = 1)
in the Maple portion of the PSD3XX sytem
development software can be used to
reduce power consumption. The CMiser-Bit
turns off the EPROM blocks in the PSD3XX
whenever the EPROM is not accessed,
thereby reducing the active current
consumed by the PSD3XX.
In the default mode, or if the PSD3XX is
configured without programming the
CMiser-Bit (CMiser = 0), the device
operates at specified speed and power
rating as specified in the A.C. and D.C.
Characteristics.
Absolute
Maximum
Ratlngs 1
Symbol
.
Min
Max
CERDIP
-65
+ 150
°C
PLASTIC
-65
+ 125
°C
Voltage on any Pin
With Respect to GND
-0.6
+7
V
Vpp
Programming
Supply Voltage
With Respect to GND
-0.6
+14
V
Vcc
Supply Voltage
With Respect to GND
-0.6
+7
V
>2000
V
TSTG
Parameter
However, if the CMiser-Bit is programmed
(CMiser = 1), the device consumes even
lower current, and is reflected in the data
sheet. This mode has an adder in
propagation delay in T5, T6, and T7
parameters in the A.C. Characteristics, and
should be added to compute worst-case
timing requirements in the application.
Condition
Storage Temperature
ESD Protection
Unit
NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.
Operating
Range
Recommended
Operating
Conditions
May. 1993
Range
Temperature
Vee
Commercial
0° Cto +70°C
+5V
Industrial
-40° C to +80°C
+5V
Military
-55° C to + 125°C
+5V
Symbol
Parameter
vcc
Supply Voltage
VIH
High-level Input Voltage
VIL
Low-level Input Voltage
34
Vee Tolerance
-12
·15
·20
±10%
±10%
±10%
±10%
±10%
±10%
Conditions
Min
All Speeds
4.5
= 4.5 V to 5.5 V
Vcc = 4.5 V to 5.5 V
2
Vcc
0
Typ Max Unit
5
5.5
V
V
0.8
V
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
DC
Characteristics
Symbol
VOL
VOH
15B1
ICC1
ICC2
ICC3
Parameter
Output Low
Voltage
Output High
Voltage
Vcc Standby
Current (CMOS)
(Notes 2 and 4)
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
Active Current
(CMOS) (SRAM
Block Selected
(Notes 2 and 5)
Conditions
PSD301
CMiser= 1
Subtract:
Min Typ Max Min Typ Max Unit
IOL = 20 JlA
Vcc = 4.5 V
0.01
IOL= 8 rnA
Vcc = 4.5 V
0.15 0.45
V
0.1
V
IOH = -20 JlA
Vcc = 4.5 V
4.4
4.49
V
IOH =-2 rnA
Vcc = 4.5 V
2.4
3.9
V
Cornrn'l
50
100
JlA
Incl/Mil
75
150
JlA
Cornrn'l
(Note 6)
16
35
7
10
rnA
Cornrn'l
(Note 7)
28
50
7
10
rnA
Ind/Mil
(Note 6)
16
45
7
10
rnA
Ind/Mil
(Note 7)
28
60
7
10
rnA
Cornrn'l
(Note 6)
16
35
0
0
rnA
Cornrn'l
(Note 7)
28
50
0
0
rnA
Incl/Mil
(Note 6)
16
45
0
0
rnA
Ind/Mil
(Note 7)
28
60
0
0
rnA
Cornrn'l
(Note 6)
47
80
7
10
rnA
Cornrn'l
(Note 7)
59
95
7
10
rnA
Ind/Mil
(Note 6)
47
100
7
10
rnA
Ind/Mil
(Note 7)
59
115
7
10
rnA
III
Input Leakage
Current
VIN = 5.5 V
orGND
-1
±0.1
1
JlA
ILO
Output Leakage
Current
VOUT = 5.5 V
orGND
-10
±5
10
JlA
NOTES: 2. CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
3. TTL inputs: VIL ~ 0.8 V, VIH ~ 2.0 V.
4. CSI/A 19 is high and the part is in a power-down configuration mode.
5. Add 3.0 mAIMHz for AC power component (power = AC + DC).
6. Ten (10) PAD product terms active. (Add 380 j.l.A per product term, typical, or 480 j.l.A
per product term maximum
7. Forty-one (41) PAD product terms active.
May, 1993
35
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
AC Characteristics
·12
·90
Symbol
Parameter
·15
·20
Min Max Min Max Min Max Min Max
T1
ALE or AS Pulse Width
20
T2
Address Set-up Time
T3
Address Hold Time
T4
Leading Edge of Read
to Data Active
T5
ALE Valid to Data Valid
CMiser=1 Unit
Add:
30
40
50
0
ns
5
9
12
15
0
ns
8
13
15
25
0
ns
0
0
0
0
0
ns
200
10
ns
100
140
170
T6
Address Valid to Data Valid
90
120
150
200
10
ns
T7
CSI Active to Data Valid
100
150
160
200
15
ns
T8
Leading Edge of Read
to Data Valid
32
38
55
60
0
ns
0
ns
0
ns
T9
Read Data Hold Time
0
0
0
0
T10
Trailing Edge of Read to
Data High-Z
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
0
0
0
0
0
ns
RD, E, PSEN, or DS
Pulse Width
40
45
60
75
0
ns
T12
35
40
35
45
WR Pulse Width
20
25
35
45
0
ns
T13
Trailing Edge of Write or
Read to Leading Edge
of ALE or AS
0
0
0
0
0
ns
T14
Address Valid to Trailing
Edge of Write
90
120
150
200
0
ns
T15
CSI Active to Trailing Edge
of Write
100
130
160
200
0
ns
T16
Write Data Set-up Time
20
25
30
40
0
ns
T17
Write Data Hold Time
5
10
15
0
ns
T18
Port to Data Out Valid
Propagation Delay
0
ns
T19
Port Input Hold Time
0
0
0
0
0
ns
T20
Trailing Edge of Write
to Port Output Valid
40
40
50
60
0
ns
T21
ADi or Control to CSOi
Valid
6
25
6
30
6
35
5
45
0
ns
T22
ADi or Control to CSOi
Invalid
5
25
5
30
4
35
4
45
0
ns
T12A
May, 1993
5
30
35
30
36
45
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
AC Characteristics (Cont.)
·15
·12
·90
·20
eMiser= 1 Unit
Add:
Symbol
Parameter
T23
Track Mode Address
Propagation Delay:
CSADOUT1 Already True
22
22
22
28
0
ns
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes
True During ALE or AS
33
33
40
50
0
ns
T24
Track Mode Trailing Edge
of ALE or AS to Address
High-Z
32
32
35
40
0
ns
T25
Track Mode Read
Propagation Delay
29
29
29
35
0
ns
T26
Track Mode Read
Hold Time
35
0
ns
T27
Track Mode Write Cycle,
Data Propagation Delay
30
0
ns
T28
Track Mode Write
Cycle, Write to Data
Propagation Delay
8
55
0
ns
T29
Hold Time of Port A
Valid During Write
CSOi Trailing Edge
2
0
ns
T30
CSI Active to CSOi Active
9
40
9
45
9
45
8
60
0
ns
T31
CSllnactive to CSOi
Inactive
9
40
9
45
9
45
8
60
0
ns
T32
Direct PAD Input as
Hold Time
10
10
12
15
0
ns
T33
RIW Active to E High
20
20
30
40
0
ns
T34
E End to R/W
20
20
30
40
0
ns
T35
AS Inactive to E high
0
0
0
0
0
ns
T36
Address to Leading
Edge of Write
20
20
25
30
0
ns
T23A
Min Max Min Max Min Max Min Max
11
29
11
20
30
29
10
20
8
30
2
29
10
20
7
40
2
7
2
NOTES: 8. AOi = any address line.
9. CSOT = any of the chip-select output signals coming through Port B (~-CS7) or through Port C (CS8-~).
10. Direct PAD input = any of the following direct PAD input lines: CSi/A 19 as transparent A 19, ROlE/OS, WR or RiW,
transparent PCo-PC2, ALE (or AS).
11. Control signals ROIEIOS or WR or RNi.
May, 1993
37
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
Figure t.
Timing of 8-BIt
Multiplexed
AddreSS/DataBusJ
CRRWR=O
-
... .......
-
READ CYCLE
......
-,
CSI/A19
asCSI
32
32-
AXX
7
Direct
PAD Input
Multiplexed
Inputs
(12)
(13)
AO/ADOA7/AD7
Active High
ALE
Active Low
ALE
~~
I
14
XXXXXXXX XXXXX XXXXXX
~m
2
•
~~
1
, r--+
3
DATA VALID
ADDRESS B
2
~
4
\..~
13
8
~ Ir
161-
~
-
,. XX -
~(
3
h
1\
DATA
)N
14
XX; I-~\.
~
~
~
IXXXX XXXX
10
ADDRESSA I
J
XXX .XXX
STABLE INPUT
I.
6
6
I~
32-
~ 0(
STABLE INPUT
-
-
15
X)
-
~
A}.,\.
\
-. xxx
WRITE CYCLE
11
~
~
rL
U-
12
ROlE as RD
I
36
5
,
BHEIPSEN
as PSEN
~
,
WRNppor
RWas WR
18
Any of
PAO-PA7
as 1/0 Pin
X) XXXXXXXXX
I
Any of
PBO-PB7
as 1/0 Pin
}) XXXXXXXXX
Any of
PAO-PA7 Pins
as Address
Outputs
'I
J
..--.....
19
~
XXXXXXXXXXXXXXXX) XX
OUTPUT
INPUT
IXXXXXXXXXXXXXXXXXXX
OUTPUT
\.
23
----1\
23
,
~
ADDRESS A
I
See referenced notes on page 48.
May, 1993
If
INPUT
\.
-
~
13
f-+
38
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
Figure 2.
Timing of 8-Blt
Multiplexed
Address/DataBus,
CRRWR=1
-
.
READ CYCLE
p
~
....,
CSI/A19
asCSI
.......
32
I'(XX .XXX
7
Direct
PAD Input
Multiplexed
Inputs
(12)
(13)
~
00f
Active Low
AS
6
6
.'ffi
DATA VALID
3
1
Ir+ r---+
IXXXX XXXX
~ ~(
2
16 : -
I
34
13
Any of
PAO-PA7 Pins
as Address
Outputs
19
INPUT
X) XXXXXXXXX
INPUT
J
23
*~
J\
ADDRESS A
\
See referenced notes on page 48.
May, 1993
~
XXXXXXXXXXXXXXXXXXX
J XXXXXXXXXXXXXXXXXXX
23
f-+
-
r-
xxxxx
X) XXXXXXXXX
I
I~\
~
18
Any of
PBO-PB7
as 1/0 Pin
p
12
" XXXXXX
I
'---'
~
36
33
~
34
33
5
Any of
PAO-PA7
as 1/0 Pin
,
~
13
8
RiW
!~r
35
35
RD/E as E
WRNppor
1\
~
..i.
Rfij as
>-
)N
1/ ~\
3
h
,
-
DATA
ADDRESS B
~
\
J
XXX XXX
14
14
~
~ r--,
1\
~
10
ADDRESSA J
2
Active High
AS
XX
32STABLE INPUT
XXXXXXXX XXXXX XXXXXX
AO/ADOA7/AD7
-
15
STABLE INPUT
-X
~
32-
/X~
\
....
WRITE CYCLE
39
ADDRESS B
OUTPUT
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
Flgurea.
T/mlng of 16-Blt
Multiplexed
AddresslOataBusJ
CRRWR=O
...
.....
READ CYCLE
.....-..
32
-..,
CSIIA19
asCSI
-. ..
32- I--
J ~\
~
~XX)
7
Multiplexed
Inputs
(13)
~~
I
~ 0\
STABLE INPUT
-X~
14
14
10
X)~
~
XXXX ~XXX
XXXXXXXX ~XXXX IXXXXXX
6
XXX I(XXX
STABLE INPUT
I..
6
XXXX
-
15
32-
Direct (12)
PAD Input
-..
WRITE CYCLE
.....
Mx XXXX
I.-
ADDRESS B
-\
ADDRESS B
OUTPUT
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
FigureS.
Timing of '-Bit Data,
Non-Multiplexed
AddrBSS/DataBus,
CRRWR=O
-
....,
CSI/A19
asCSI
READ CYCLE
-
~
32
....
AO/ADOA15/AD15
as AO-A15
PCO-PC2,
CSI/A19 as
Multiplexed
Inputs
.-
32--+
.....
'(XX XXX
l"~
1\
7
Direct (12)
PAD Input
WRITE CYCLE
15
~~
STABLE INPUT
~ 00
STABLE INPUT
6
~
~~
STABLE INPUT
~~
STABLE INPUT
IXXX XXX
14
IXXX XXX
.-
32--+
1-
-X~
XXXXXXXX XXXXX OCOCOCXXX
XXXX XXXX
14
10
6
-
DATA
jN
PAO-PA7
Active High
ALE
Active Low
ALE
"\
-'
~ro
2
DATA VALID
rh
I .. 1
~
4
13
,
I
........
,
'-
11
~
J
36
'x, XOCXXXXXOCOC
13
12A 1--+
~
,~
19
18
~
XXXOCXXXXXXXXXXXXXXX
INPUT
See referenced notes on page 48.
May, 1993
1lJ r-
--'16 ~J
1
-1
~'
/
12
5
I
~
3
~
,
8
'--1
WRNpp or
RiWasWR
Any a f
PBO-PB7
as 1/0 Pin
2
J
,
RD/E as RD
XX
~
3
42
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
Figure 6.
Timing of '-Bit Data,
Non-Multiplexed
AddreSS/DataBus,
CRRWR=1
-
-.. ..
READ CYCLE
.....
32
~
CS IIA19
asCSI
'(XX XXX
15
7
00\
STABLE INPUT
6
AOIADOA151AD15
asAO -A15
)C ~
STABLE INPUT
.E...
PCO- PC2,
CSIIA 19 as
Multiplexed
Iriputs
X
-
6
:00
2
Active Low,
ALE
XE ~
STABLE INPUT
XXXX IXXXX
~
~
2
4
~
h
13
I
~
WRNppor
RiWas pjijj
'J
•
OC
XXXXXXJ
:XXXXX
r---\
12
33
~
Lr
34
~-
-
13
,--
I
18
19
\
Xl XXXXXXXXX
12.9.
XXXXXXXXXXXXXXXXXXX
INPUT
I
See referenced notes on page 48.
May, 1993
,
36
8
33
~
I
35
I
PBO -PB7
as IIo Pin
161-
-
1lJ r
1\
12
J
I/~~
3
~
34
RDIE as E
Anyot
DATA
IN
1\
1
35
+-
32 ......
14
1 1\
~
'f
XXX XXX
/
3
~ ~.
XXX XXX
14
DATA VALlD)(X;
~h
r--
STABLE INPUT
10
--,
I
~ 0(
IXXXXXXXX XXXXX XXXXXX
~
PAO -PA7 -J
Active High
ALE
+----
32 -+
1~\
~
Direct(12) ~
PAD Inp ut
-..
WRITE CYCLE
......
43
OUTPUT
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD301
Field-programmable microcontroller peripheral
Figure 7.
Timing of 16-BIt
Non-Multiplexed
Address/DataBus,
CRRWR=O
-
..... ....--
READ CYCLE
.....
32
~
CSIIA19
asCS I
~
I/XX XXX
7
00<
15
STABLE INPUT
6
-] 00
AO/ADO
A151AD15
as AO-A15
PCO-PC2 ,
CSI/A19 as
Multiplexed
Inputs
...
32-
/X\
~
Direct (12
)~
PAD Input
.
WRITE CYCLE
STABLE INPUT
~
)0
~ tx
STABLE INPUT
~ 0(
STABLE INPUT
!XXX XXX
14
XXX .XXX
...
32-
XXXXXXXX XXX XX XXXXXX
XXXX IXXXX
14
:x~
I,(XXX XXXX
,(XXXXXXX )(XXXX XXXXXX
6
DATA
IN
.,
/,
~
PAD-PA7
(Low Byte ) - i
,
~m
PBO-PB7
(High Byte)--'
2
Active High
ALE
Active Low
ALE
RDIE as RD
DATA VALID
~
DATA VALID
-
~
\.
2
3
10
--;
r--;
I. 1
-+
,
8
, ..
13
12
.,
J
16
--'
IN
Ir'
j\..
36
,~
0r
RtW asWR
See referenced notes on page 48.
44
13
f..-.
May, 1993
~TA
11
12A
WRNpp
-
L
\~ r
iL-
~
4
\..--1
~
\.
17
~
3
~
XXt
~
J
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
Figure S.
Timing of 16-Blt
Non-Multiplexed
AddreSS/DataBus,
CRRWR=1
--
--,
CSI/A19
asCS I
READ CYCLE
...
WRITE CYCLE
.....
32
~XX
7
00\
STABLE INPUT
PCO-PC2
CSI/A19 as
Multiplexed
Inputs
-~ (X;~.
STABLE INPUT
r--
~
-X
xz: P<
xz: ~
XXX IXXX
STABLE INPUT
14
XXX IXXX
STABLE INPUT
...
32-
IXXXXXXXX XXXXX XXXXXX
~XXX
XXXX
,(XX
,(XXXXXXX IlXXXX XXXXXX
XXXX~
6
DATA
IN
....,
/
PAO-PA7
(Low Byte )--J
~
DATA VALID
~
I
'- I/XX ~
-
.2..
....,
DATA
IN
, 1/ 'XI.. r \.
'-/
PBO-PB7
(High Byte )--J
~ro
2
Active Low
AS
-
14
]~
Active High
AS
XXXX
15
6
AO/ADO
A15/AD15
as AO-A15
~
/X~
\
Direct (12
)~
PAD Input
...
32-
DATA VALID
~
10
3
~h
..~I
16
3
~
1 \.
If+ f--+
.......
,
'-~
2
1
4
35
•
--i
~
RD/E as E
•
35
•
,
8
13
.-
13
36
~
~
IJ
f+33
34
~
:J
J
I(
12
34
1\
~
~
WRNppo r
X XXXXXX
XXXXX
RlWas RIW
See referenced notes on page 48.
May, 1993
45
If-
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
PSD301
Flgul".
Chlp-Ssl,ct
Output Timing
30
CsI/A19
asCsl
I(
""""'
Direct PAD (12)
Input
Multiplexed
PAD Inputs
31
~
(18)
-
w
INPUT STABLE
J~
orALE
(Multiplexed
Mode Only)
CSc5i (14,1 9)
..
1
......
-
II
..
3
I
~
,
'-W
-
..
L
22
21
1\
See referenced notes on page 48.
May, 1993
,
'IIIIIII II
~~
114-
J~
I
~
2
ALE
(Multiplexed
Mode Only)
,
46
r-
J
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
Figure 10.
PortA
as ADO-AD7 Timing
(Track Mode),
CRRWR=O
..
READ CYCLE
.....
~
Direct
PAD Input ..J~
(16,18)
X~
r--
2
orALE
ADDRESS
-~
-n
'r
--YJ
~
m
J
"
1
32
4
--'
12
r+----+
ADDRESS
--..
DATA
~
00( ADROUT) -{XXX
f\
'--f
'(
~~
~
11
27
~
12A
24
24
-
If WRITIEN
~~
1\
,
XXX>- roo ADROUT'
DATA IN
23 ~
~
CSOi
23 f+--
J
-00
DATA
OUT
29
~
~
j
(14,17)
See referenced notes on page 48.
May, 1993
[}-,-
I..!-.
,
WRlVppor
RiWas WR
X
~XXXXXX
3
32
f+ --.
~
STABLE INPUT
2
26
DATA VALID
I
,.~
ROlE as RD
PAO·PA7
IX X X X X X X X X X X X X XXXX X
3
J~
STABLE INPUT
2
STABLE INPUT
AO/ADO·
A7/AD7
ALE
32--.. ~
2 I
-
...
WRITE CYCLE
STABLE INPUT
(12,15)
Multiplexed
PAD Inputs
.... .......
47
XX>--
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
Flgur. 11. Port A as ADO-AD7 Timing
(Track .ode). CRRWR =1
Direct
PAD Input
(18,18)
AO/ADOA7/AD7
....
WRITE CYCLE
~
STABLE INPUT
j
(12,15)
Multiplexed
PAD Inputs
... .....-
READ CYCLE
....
32-
1\
~
~(XXX
STABLE INPUT
1-
21
)( KX. 1\ STABLE INPUT OCXXXXXXXXXXXX IX .XXX
-
STABLE INPUT
X
~XYYYYY
~
2
3
j~ ADDRESS
J
-r--
~
~
r:xYJ
DATA VALID
3
2
26
ro-
I
ADDRESS
~
" WRITTEN
DATA
I-
32AS
or AS
~h
~~
1
~
-~~1-+
-n
-
35
12
I-I'--'
33
RD/Eas E
12
35
,
~
,
J
V\
U
I\.
~
-. 34
X X) IXXXX
WRNppor
RIW as Rfii
-
-.
00( ADROUT) -{XxX
23
24
XXX>- roo ADROUT
DATA IN
.....
-.
(14,17)
May, 1993
23
I+-
.... .....
27
00(
DATA
OUT
~
~
"----'
CSOi
Notes for
Timing
Diagrams
V-
.XX .XXXX
34
24
PAO-PA7
.....
12. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E,
WR or R/W, transparent PCQ-PC2, ALE and A11/AD11-A15/AD15 in non-multiplexed modes.
13. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS):
AO/ADQ-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PCo-PC2.
14. CSOi = !!!X of the chip-select output signals coming through Port B (~0-CS7) or through
Port C (CS8-CS10).
15. CSADOUT1, which internally enables the address transfer to Port A, should be derived only
from direct PAD input signals, otherwise the address propagation delay is slowed down.
16. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively,
can be derived from any combination of direct PAD inputs and multiplexed PAD inputs.
17. The write operation signals are included in the CSOi expression.
18. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in
the multiplexed modes: A11/AD11-A15/AD15, CSIIA19 as ALE dependent A19, ALE dependent
PCQ-PC2.
19. CSOi product terms can include any of the PAD input signals except for reset and CSI.
48
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Pin
Capacltance20
Symbol
PSD301
Parameter
CIN
Capacitance (for input pins only)
COUT
Capacitance (for input/output pins)
CvPp
Capacitance (for WR/vpp or R/WNpp)
Conditions Typical21 Max Unit
4
pF
6
VIN = 0 V
8
12
pF
VOUT = 0 V
Vpp = 0 V
18
25
pF
NOTES: 20. This paramter is only sampled and is not 100% tested.
21. Typical values are for TA = 25°C and nominal supply voltages.
Figure 12.
AC Testing
Input/Output
Waveform
v:
3· 0 V - Y
-A
TEST POINT
-
~v
0V
Figure 13.
AC Testing
Load Circuit
2.01 V
~
DEVICE
UNDER
TEST
:><:..,.
I..l...
_
Erasure and
Programming
To clear all locations of their programmed
contents, expose the device to ultra-violet
light source. A dosage of 15 W secondlcm 2
is required. This dosage can be obtained
with exposure to a wavelength of 2537 A
and intensity of 12000 JlW/cm 2 for 15 to 20
minutes. The device should be about 1 inch
from the source, and all filters should be
removed from the UV light source prior to
erasure.
The PSD3XX and similar devices will erase
with light sources having wavelengths
shorter than 4000 A. Although the erasure
times will be much longer than with UV
sources at 2537 A, exposure to fluorescent
light and sunlight eventually erases the
May. 1993
49
195(2
C L =30pF
(INCLUDING
SCOPE AND JIG
CAPACITANCE)
device. For maximum system reliability,
these sources should be avoided. If used in
such an environment, the package
windows should be covered by an opaque
substance.
Upon delivery, or after each erasure, the
PSD3XX device has all bits in the PAD and
EPROM in the "1" or high state. The
configuration bits are in the "0" or low state.
The code, configuration, and PAD MAP
data are loaded through the procedure of
programming
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Pin
Assignments
44-Pin
PLCC/CLCC
Package
Pin Name
BHEIPSEN
WRNpporR/W
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
GND
ALE or AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
RD/E
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD1 0/A1 0
GND
AD11/A11
AD121A12
AD13/A13
AD14/A14
AD15/A15
PCO
PC1
PC2
A19/CSI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Vee
NOTE: 36. Pins 1, 13, 14, 26, 27, 39, 40, and 52 are No Connect.
May, 1993
50
PSD301
52-Pin
PQFP Package
46
47
48
49
50
51
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
36
37
38
41
42
43
44
45
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
Package
Infonnatlon
Figure 14.
DrawlngL444 Pin Ceramic
Leaded Chip
Carrier (CLCC)
with Window
(Package Type L)
PB4
7
39 AD15/A15
PB3
S
38 AD/14/A14
PB2
9
37 AD13/A13
o
PBl 10
PBO 11
GND 12
ALE or AS 13
PA714
PA6 15
34 GND
33 AD10/Al0
32 AD9/A9
31 ADS/AS
PA5 16
30 AD7/A7
PA4 17
29 AD6/A6
~ ~
~
N
c(
0. 0.
(rop VIEW)
0
N
iii
0.
...
N
N
N
~ I(/)
0.
C")
N
..
N
I/)
N
~
~
~ ~ ~ ~ M
I~
Figure 15.
DrawlngJ244 Pin Plastic
Leaded Chip
Carrier (PLCC)
(Package Type J)
N
0
0
4(
C
4(
0
4(
0
4(
..... Nco
N
~
0
4(
~
its
0
4(
uuuuuuuuuuu
PB4
7
39 AD15/A15
PB3
S
39 AD14/A14
PB2
9
37 AD13/A13
PBl 10
36 ADl21A12
35 AD11/All
PBO 11
34 GND
GND 12
33 AD10/Al0
ALEorAS 13
PA714
32 AD9/A9
PA6 15
31 ADS/AS
PA5 16
30 AD7/A7
PA417
29 AD6/A6
(rop VIEW)
May, 1993
36 ADl21A12
35 ADll/All
51
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD301
Flgur, 16.
DrawIng 0252PlnPOFP
(Packag' Typ. OJ
NC
1
3D NC
PB4
2
38 AD151A15
PB3
3
37 AD141A14
PB2
4
36 AD131A13
PB1
5
35 AD121A12
PBO
6
34 AD11/A11
GND
7
33 GND
ALEor AS
8
32 AD10/A10
PA7
sa
31 ADO/AD
PA610
30 ADa/A8
PAS 11
20 AD7/A7
PA412
28 AD6/A6
27 Ne
NC 13
(TOP VIEW)
May. 1993
52
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Ordering
Information
May. 1993
PSD301
Package Operating Manufacturing
Drawing Temperature
Procedure
Range
Spd.
(ns)
Package
Type
PSD301-90 A
90
44-pin PLCC
J2
Commercial
Standard
PSD301-90 KA
90
44-pin CLCC
L4
Commercial
Standard
PSD301-12 A
120
44-pin PLCC
J2
Commercial
Standard
PSD301-12 KA
120
44-pin CLCC
L4
Commercial
Standard
PSD301-12 B
120
52-pin POFP
02
Commercial
Standard
PSD301-15 A
150
44-pin PLCC
J2
Commercial
Standard
PSD301-151 A
150
44-pin PLCC
J2
Industrial
Standard
PSD301-15 KA
150
44-pin CLCC
L4
Commercial
Standard
PSD301-151 KA
150
44-pin CLCC
L4
Industrial
Standard
PSD301-15 B
150
52-pin POFP
02
Commercial
Standard
PSD301-151 B
150
52-pin POFP
02
Industrial
Standard
Standard
Part Number
PSD301-20 A
200
44-pin PLCC
J2
Commercial
PSD301-201 A
200
44-pin PLCC
J2
Industrial
Standard
PSD301-20 KA
200
44-pin CLCC
L4
Commercial
Standard
PSD301-201 KA
200
44-pin CLCC
L4
Industrial
Standard
PSD301-20 B
200
52-pin POFP
02
Commercial
Standard
PSD301-201 B
200
52-pin POFP
02
Industrial
Standard
53
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
May, 1993
54
PSD301
Philips Semiconductors Mlcrocontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Key Features
Cl Single Chip Programmable Peripheral
for Microcontroller-based Applications
Cl 19 Individually Configurable I/O pins
Cl 16 Kbit Static RAM
-
Configurable as 2K x 8
-
120 ns SRAM access time, including
input latches and PAD address
decoding
that can be used as:
-
Microcontroller I/O port expansion
-
Programmable Address Decoder
(PAD) I/O
-
Latched address output
-
Open drain or CMOS
PSD311
Cl Address/Data Track Mode
-
Enables easy Interface to Shared
Resources (e.g., Mail Box SRAM) with
other Microcontrollers or a Host
Processor
Cl Two Programmable Arrays
(PAD A and PAD B)
Cl Built-In Security
-
Total of 40 Product Terms and up to
16 Inputs and 24 Outputs
-
-
Address Decoding up to 1 MB
-
Logic replacement
Cl Available in a Choice of Packages
-
44 Pin PLCC and CLCC
Cl "No Glue" Microcontroller Chip-Set
-
52 Pin PQFP
-
Built-in address latches for multiplexed
address/data bus
-
44 Pin CPGA
-
Non-multiplexed address/data bus
mode
-
8-bit data bus width
-
ALE and Reset polarity programmable
-
Selectable modes for read and write
control bus as RDtWR or R/W/E
-
PSEN pin for 8051 users
Cl 256 Kbits of UV EPROM
May. 1993
Locks the PSD311 and PAD Decoding
Configuration
-
Configurable as 32K x 8
-
Divides into 8 equal mappable blocks
for optimized mapping
-
Block resolution is 4K x 8
-
120 ns EPROM access time, including
input latches and PAD address
decoding.
55
Cl Simple Menu-Driven Software:
Configure the PSD311 on an IBM PC
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
PS03.11
Field-programmable microcontroller peripheral
Security
Mode
Security Mode in the PSD3XX locks the
contents of the PAD A , PAD B and all the
configuration bits. The EPROM, SRAM,
and I/O contents can be accessed only
through the PAD. The Security Mode can
be set by the MAPLE or Programming
software. In window packages, the mode is
erasable through UV full part erasure. In
the security mode, the PSD3XX contents
cannot be copied on a programmer.
eMlseT-BIt
The CMiser-Bit provides a programmable
option for power-sensitive applications that
require further reduction in power
consumption. The CMiser-Bit (CMiser = 1)
in the Maple portion of the PSD3XX sytem
development software can be used to
reduce power consumption. The CMiser-Bit
turns off the EPROM blocks in the PSD3XX
whenever the EPROM is not accessed,
thereby reducing the active current
consumed by the PSD3XX.
In the default mode, or if the PSD3XX is
configured without programming the
CMiser-Bit (CMiser = 0), the device
operates at specified speed and power
rating as specified in the A.C. and D.C.
Characteristics.
Absolute
Maximum
Ratings 1
Symbol
However, if the CMiser-Bit is programmed
(CMiser = 1), the device consumes even
lower current, and is reflected in the data
sheet. This mode has an adder in
propagation delay in T5, T6, and T7
parameters in the A.C. Characteristics, and
should be added to compute worst-case
timing requirements in the application.
Min
Max
Unit
CERDIP
-65
+ 150
°C
PLASTIC
-65
+ 125
°C
Voltage on any Pin
With Respect to GND
-0.6
+7
V
Vpp
Programming
Supply Voltage
With Respect to GND
-0.6
+14
V
Vcc
Supply Voltage
With Respect to GND
-0.6
+7
V
>2000
V
TSTG
Parameter
Condition
Storage Temperature
ESD Protection
NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.
Operating
Range
Range
Temperature
Commercial
Recommended
Operating
Conditions
May. 1993
0° C to +70°C
+5V
Industrial
-40° C to +80°C
+5V
Military
-55° C to + 125°C
+5V
Symbol
Parameter
Vee Tolerance
Vee
·12
·15
·20
± 10%
±10%
±10%
±10%
±10%
±10%
Conditions
Min
vcc
Supply Voltage
All Speeds
4.5
VIH
High-level Input Voltage
V cc = 4.5 V to 5.5 V
2
VIL
Low-level Input Voltage
Vcc =4.5 Vto 5.5 V
0
56
Typ Max Unit
5
5.5
V
V
0.8
V
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontrolier peripheral
PSD311
DC
Characteristics
Symbol
Parameter
Conditions
Min
VOL
VOH
IS81
ICCl
ICC2
ICC3
Output Low
Voltage
Output High
Voltage
Vcc Standby
Current (CMq5)
(Notes 2 and 4)
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
Active Current
(CMOS) (SRAM
Block Selected
(Notes 2 and 5)
III
Input Leakage
Current
ILo
Output Leakage
Current
~Typ
CMiser= 1
Subtract:
Max Min Typ Max Unit
IOL = 20 JlA
Vcc = 4.5 V
0.01
IOL =8 rnA
Vcc = 4.5 V
0.15 0.45
V
0.1
V
IOH = -20 JlA
Vcc=4.5V
4.4
4.49
V
IOH =-2 rnA
Vcc = 4.5 V
2.4
3.9
V
Cornrn'l
50
100
JlA
JlA
IndlMiJ
75
150
Cornrn'l
(Note 6)
16
35
7
10
rnA
Cornrn'l
(Note 7)
28
50
7
10
rnA
IndlMil
(Note 6)
16
45
7
10
rnA
IndlMil
(Note 7)
28
60
7
10
rnA
Cornrn'l
(Note 6)
16
35
0
0
rnA
Cornrn'l
(Note 7)
28
50
0
0
rnA
IndlMil
(Note 6)
16
45
0
0
rnA
IndlMil
(Note 7)
28
60
0
0
rnA
Cornrn'l
(Note 6)
47
80
7
10
rnA
Cornrn'l
(Note 7)
59
95
7
10
rnA
IndlMil
(Note 6)
47
100
7
10
rnA
Ind/Mil
(Note 7)
59
115
7
10
rnA
-1
±0.1
1
JlA
-10
±5
10
JlA
VIN = 5.5 V
orGND
VOUT = 5.5 V
orGND
NOTES: 2. CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
3. TTL inputs: VIL ~ 0.8 V, V 1H ~ 2.0 V.
4. CSIIA19 is high and the part is in a power-down configuration mode.
5. Add 3.0 mA/MHz for AC power component (power = AC + DC).
6. Ten (10) PAD product terms active. (Add 380 JlA per product term, typical, or 480 JlA
per product term maximum
7. Forty-one (41) PAD product terms active.
May, 1993
57
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD311
AC Character/stlcs
-90
SymbDI
Parameter
-12
-15
-20
Min Max Min Max Min Max Min Max
CMiser=1 Unit
Add:
T1
ALE or AS Pulse Width
20
30
40
50
0
ns
T2
Address Set-up Time
5
9
12
15
0
ns
T3
Address Hold Time
8
13
15
25
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
0
0
ns
T5
ALE Valid to Data Valid
100
140
170
200
10
ns
T6
Address Valid to Data Valid
90
12~
150
200
10
ns
ns
T7
CSI Active to Data Valid
100
150
160
200
15
T8
Leading Edge of Read
to Data Valid
32
38
55
60
0
ns
T9
Read Data Hold Time
0
ns
T10
Trailing Edge of Read to
Data High-Z
0
ns
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
0
0
0
0
0
ns
T12
RD, E, PSEN, or DS
Pulse Width
40
45
60
75
0
ns
WR Pulse Width
20
25
35
45
0
ns
T13
Trailing Edge of Write or
Read to Leading Edge
of ALE or AS
0
0
0
0
0
ns
T14
Address Valid to Trailing
Edge of Write
90
120
150
200
0
ns
T15
CSI Active to Trailing Edge
of Write
100
130
160
200
0
ns
T16
Write Data Set-up Time
20
25
30
40
0
ns
T17
Write Data Hold Time
5
5
10
15
0
ns
T18
Port to Data Out Valid
Propagation Delay
T12A
0
0
0
40
35
35
45
35
30
30
0
45
0
ns
T19
Port Input Hold Time
0
0
0
0
0
ns
T20
Trailing Edge of Write
to Port Output Valid
40
40
50
60
0
ns
T21
ADi or Control to CSOi
Valid
6
25
6
30
6
35
5
45
0
ns
T22
ADi or Control to CSOi
Invalid
5
25
5
30
4
35
4
45
0
ns
May, 1993
58
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD311
AC Characteristics (Cont.)
-90
-15
-12
-20
CMiser.1 Unit
Add: *
Min Max Min Max Min Max Min Max
Symbol
Parameter
T23
Track Mode Address
Propagation Delay:
CSADOUT1 Already True
22
22
22
28
0
ns
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes
True During ALE or AS
33
33
40
50
0
ns
T24
Track Mode Trailing Edge
of ALE or AS to Address
High-Z
32
32
35
40
0
ns
T25
Track Mode Read
Propagation Delay
29
29
29
35
0
ns
T26
Track Mode Read
Hold Time
35
0
ns
T27
Track Mode Write Cycle,
Data Propagation Delay
30
0
ns
T28
Track Mode Write
Cycle, Write to Data
Propagation Delay
8
55
0
ns
T29
Hold Time of Port A
Valid During Write
CSOi Trailing Edge
2
0
ns
T30
CSI Active to CSOi Active
9
40
9
45
9
45
8
60
0
ns
T31
CSI Inactive to CSOi
Inactive
9
40
9
45
9
45
8
60
0
ns
T32
Direct PAD Input as
Hold Time
10
10
12
15
0
ns
T33
RIW Active to E High
20
20
30
40
0
ns
T34
E End to R/W
20
20
30
40
0
ns
T35
AS Inactive to E high
0
0
0
0
0
ns
T36
Addre.ss to Leading
Edge of Write
20
20
25
30
0
ns
T23A
11
29
11
20
30
29
10
20
8
30
2
29
10
20
7
40
2
7
2
NOTES: 8. ADi = any address line.
9. ~ = any of the chip-select output signals coming through Port B (CSO-CS?) or through Port C (~~).
10. Direct PAD input = any of the following direct PAD input lines: ~/A19 as transparent A19, RDIEIlrn, WR or
Rfii, transparent PCo-PC2, ALE (or AS).
11. Control signals RD/E/DS or WR or Rfiii.
May.
1993
59
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
PSD311
Field-programmable microcontroller peripheral
Figure 1.
Timing Df B-BIt
Multiplexed
AddreSS/DataBus,
CRRWR=O
-...
CSI/A19
asCSI
~
READ CYCLE
32
-
..- --
-
(12)
f4:..
32-
I~XX
A"\
~
7
Direct
PAD Input
.....
WRITE CYCLE
~~
-
15
~
STABLE INPUT
6
32-
~
XXX
XXX XXX
STABLE INPUT
14
I
Multiplexed
Inputs
(13)
AO/ADOA7/AD7
Active High
ALE
Active Low
ALE
-X~
-
ADDRESSA
J
,'..
XXXX IXXXX
I}['}['}['XXXXX ~}[.}[.XX XXXXXX
10
6
2
~XXX DATA VALID ~ f-\
2
~
I+-
J
3
\
1
ADDRESS B
)- ~ 1/
3
17
161-
it-+
-+
'(
'(
4
\..-J
13
8
,
5
~
~
11
J
,
36
J
If
\....--J
18
~) XXXXXXXXX
I
Any a f \.
PBO-PB7 X)
I
as 1/0 Pin
XXXXXXXXX
19
INPUT
~
)XXXXXXXXXXXXXXXX) XX
OUTPUT
INPUT
)XXXXXXXXXXXXXXXXXXX
OUTPUT
~
-
J\
23
i+-.
'"
ADDRESS A
JI\
See referenced notes on page 66.
May, 1993
-
13
,
WRNppor
RWasWR
I\L!
12
12A
..--.
Any of
PAO-PA7 Pins
as Address
Outputs
r
J
1 1\
RD/E as RD
Any a
PAO-PA7f
as 1/0 Pin
)(X \-
1-1
h
r~
DATA
IN
14
60
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD311
Figure 2.
Timing of 8-BIt
Multiplexed
Address/DataBus,
CRRWR=1
CSI/A19
as CSI
--
..,
.... ---
READ CYCLE
32
32-
AX~
~
...
WRITE CYCLE
~
'(XX XXX
7
-
15
32-
Direct (12)
PAD Input
Multiplexed
Inputs
(13)
~
~
Active Low
AS
14
---.
..
3
~m
,
DATA VALID
D(XXX OCXXX
~ 'r-'\
2
161-
35
rL
,
'- L!
J
35
J
13
~
36
34
I~I\
34
8
1\
33
33
12
12
)XXXXXX
13
r-
XXXXX
18
19
XXXXXXXXX
INPUT
~
XXXXXXXXXXXXXXXXXXX
OUTPUT
\) IXXXXXXXXX
INPUT
IXXXXXXXXX XXXXX XX XXX
OUTPUT
Any of \
PAO-PA7 X)
I
as I/O Pin
Any of
PBO-PB7 I
as I/O Pin
23
_\
23
~
'I
ADDRESS A
JI\.
See referenced notes on page 66.
May, 1993
~ ,-
.....=-.
5
Any of
PAO-PA7 Pins
as Address
Outputs
'(
1 1\
RD/E as E
WRNppor
RiWasRiW
r( 1/ X~
3
---.
'(
.J
DATA
IN
ADDRESS B
-
~
•
:,1 ~
Jf4- ---+
~
~
14
10
ADDRESSA )
XXX XXX
STABLE INPUT
IXXXXXXXX XXXXX XXXXXX
6
2
Active High
AS
6
-X
AO/ADOA7/AD7
~ 0<
I..
STABLE INPUT
61
ADDRESS B
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
PSD311
Figure 3.
Timing of '-Bit Data,
Non-Multiplexed
Address/DataBus,
CRRWR=O
-~
CSIIA19
asCS I
-.
READ CYCLE
32
WRITE CYCLE
32-+
t..
7
Direct (12)
PAD Input
AO-A15
Multiplexed (13)
Inputs
~
00\
15
~ 0\ ..
STABLE INPUT
6
~ 00
STABLE INPUT
~
-~
Active Low
~
~
DATA VALID
1
I~ f-+-
1\
,
8
13
,
WRNpp or
12
'x) XXXXXXXXX
I
2
~
:x
n
---'
~ r-
3
..... 16 ..... J
,
\...
11
36
~
.J
13
12A ~
~
,
5
~
19
18
~
XXXXXXXXXXXXXXXXXXX
INPUT
See referenced notes on page 66.
May,1993
DATA
,.,
j
RiWasWR
Any a f
PBO-PB7
as lID Pin
~
1/
~
4
~f--.J
RD/Eas RD
XXX XXX
XXXX IXXXX
14
XX;
~
3
r~
ALE
STABLE INPUT
J,N
2
ALE
XXX XXX
14
32-+
10
,
Active High
)00 0<
STABLE INPUT
IXXXXXXXX ~XXXx XXXXXX
6
PAO-PA7
~
.(XX XXX
JrA\
~
--
.....
62
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Figure 4.
Timing of '-Bit Data,
Non-Multiplexed
AddreSS/DataBus,
CRRWR=1
-
.
READ CYCLE
~
PSD311
WRITE CYCLE
~
32
AX\
CSI/A19""""" \
asCS I
AO-A15
~
00\
6
STABLE INPUT
r--
Multiplexed (13)
Inputs
XXX
15
STABLE INPUT
-~ 00
~
~XX
7
Direct (12)
PAD Input
....
32 ......
~
~P<
STABLE INPUT
~~
STABLE INPUT
,XXX XXX
14
~XX
32 --.
4-
~XXX
IXXXX
XXX
1-
X~
XXXXXXXX OCXXXX ~XXXXX
-
6
14
10
DATA
IN
/
PAO-PA7
~
"""""
-I
2
DATA VALlD)()C
~
3
Active High r h
ALE I . 1
Active Low
ALE
,
2
..
rL
,
i'-Lr
35
13
36
34
8
RDIE as E
J~-"'
~
5
33
~r
j
,~
4
1/ XX'~
-
161~
J
35
3
~
I""-;
f--+
\..f-I ..
~
..
12
33
..
34
~-
12
13
IWRNppor
X XXXXXX
Rfii as Rfii
XXXXX
18
Any of \
PBO-PB7 X)
as 1/0 Pin
,
XXXXXXXXX
19
INPUT
See referenced notes on page 66.
May, 1993
63
~
XXXXXXXXXXXXXXXXXXX
rOUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD311
Figure 5.
Chip-Select
Output Timing
CSI/A19
,
30
31
4--+
I(
asCSI
Direct PAD (12)
Input
--i~
Multiplexed
PAD Inputs
}O'
(18)
I
,
IXXXXXXX I(X XX
2
r
ALE
(Multiplexed
Mode Only)
orALE
(Multiplexed
Mode Only)
INPUT STABLE
h
3
-
It
1
114- r--.
,
L
~ ---i
22
21
~
CS5i (14,1 9)
~
See referenced notes on page 66.
MaY,1993
64
r--
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD311
Figure 6.
PortA
as ADO-AD7 Timing
(Track Mode),
CRRWR=O
--
~
Direct
'(
PAD Input --1r\
Multiplexed
PAD Inputs
(16,18)
orALE
XXXXXXXXXXXXX XXXX X
STABLE INPUT
3
-
~
ADDRESS
m
J
DATA VALID
~ [)-\
>-
ADDRESS
'f WRITTEN
DATA
32
~
Ir~
I...:!-.
-~
"- ---'
~
4
,
12
~----I
r\
'f
.....
J
11
27 4 -
V\.
V
12
,
WRlVpp or
Rfiias WR
24
-
.....
~
ADROUT)
24
---\
~
ADDRESS
'f WRITIEN
1\
DATA
I-
32AS
or AS
-
r~
1
oJ.
~~
I....!-.
r--+
-~
35
1\..--
33
J
WRNppor
X
x~
,.
II
~
)XX XXXX
34
24
-
XX
ADROUT)
-. 23 I+-
24
-<'ro
XXX)- ~
DATA IN
-.
CSOi
23
ADROUTJ
+-
....
27
{XX
.DATA
OUT
Y»-
~
~
-
(14,17)
Notss for
Timing
Diagrams
33
\
-. 34 .-
XXXX
RlWasRiW
PAD·PA7
12
35
,
r-RD/Eas E
I
1\
12
V\.
V
\
J
12. Direct PAD input = any of the following direct PAD input lines: CSI/A 19 as transparent A 19,
i1OlE, WR or Rfil, transparent PCo-PC2, ALE in non-multiplexed modes.
13. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS):
AO/ADO-A15/AD15, CSi/A19 as ALE dependent A19, ALE dependent PCo-PC2.
14. CSOi = !!!i: of the chip-select output signals coming through Port B (CSO-CS?) or through
Port C (CS8-CS1 0).
15. CSADOUT1, which internally enables the address transfer to Port A, should be derived only
from direct PAD input signals, otherwise the address propagation delay is slowed down.
16. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively,
can be derived from any combination of direct PAD inputs and multiplexed PAD inputs.
17. The write operation signals are included in the CSOi expression.
18. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in
the multiplexed modes: A11/AD11-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent
PCO-PC2.
19. CSOi product terms can include any of the PAD input signals except for reset and CSI.
May, 1993
66
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Pin
Capacltance211
Symbol
PSD311
Conditions Typical21 Max Unit
Parameter
CIN
Capacitance (for input pins only)
COUT
CvPp
Capacitance (for inpuVoutput pins)
Capacitance (for WR/vpp or R/WNpp)
VIN = 0 V
4
6
pF
VOUT=OV
Vpp = 0 V
8
12
pF
18
25
pF
NOTES: 20. This paramter is only sampled and is not 100% tested.
21. Typical values are for T A = 25°C and nominal supply voltages.
FigureS.
AC Testing
Input/Output
Wavefonn
v:
3· 0 V - Y
-"
TEST POINT -
~v
0V
Figure 9.
AC Testing
Load Circuit
......
2.01 V
:><:>
DEVICE
UNDER
TEST
I
-
_
Erasure and
Programming
To clear all locations of their programmed
contents, expose the device to ultra-violet
light source. A dosage of 15 W secondlcm 2
is required. This dosage can be obtained
with exposure to a wavelength of 2537 A
and intensity of 12000 J.1W/cm 2 for 15 to 20
minutes. The device should be about 1 inch
from the source, and all filters should be
removed from the UV light source prior to
erasure.
The PSD3XX and similar devices will erase
with light sources having wavelengths
shorter than 4000 A. Although the erasure
times will be much longer than with UV
sources at 2537 A, exposure to fluorescent
light and sunlight eventually erases the
May.
1993
67
1950
~
CL =30pF
(INCLUDING
SCOPE AND JIG
CAPACITANCE)
device. For maximum system reliability,
these sources should be avoided. If used in
such an environment, the package
windows should be covered by an opaque
substance.
Upon delivery, or after each erasure, the
PSD3XX device has all bits in the PAD and
EPROM in the "1" or high state. The configuration bits are in the "0" or low state. The
code, configuration, and PAD MAP data
are loaded through the procedure of
programming
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Pin
Assignments
"-Pin
PLCC/CLCC
Package
Pin Name
PSEN
WR/vpp or R/W
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
GND
ALE or AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
RD/E
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
AS
A9
A10
GND
A11
A12
A13
A14
A15
PCO
PC1
PC2
A19/CSI
Vee
NOTE: 36. Pins 1, 13, 14, 26, 27, 39, 40, and 52 are No Connect.
May, 1993
68
PSD311
52-Pin
POFP Package
46
47
48
49
50
51
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
36
37
38
41
42
43
44
45
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD311
Field-programmable microcontroller peripheral
Package
Information
Figure 10.
DrawlngL444 Pin Ceramic
Leaded Chip
Carrier (CLCC)
with Window
(Package rype L)
uuuuuuuuuuu
39 A15
PB4
7
PB3
8
38 A14
PB2
9
37 A13
o
PBl 10
PBO 11
GND 12
ALEorAS 13
PA714
PA6 15
36
35
34
33
A12
All
GND
Al0
32 A9
31 A8
PA5 16
30 AD7/A7
PA4 17
29 AD6/A6
(TOP VIEW)
Figure 11.
DrawlngJ244 Pin Plastic
Leaded Chip
Carrier (PLCC)
(Package Type J)
I~
PB4
7
39 A15
PB3
8
39 A14
PB2
9
37 A13
PBl 10
36 A12
PBO 11
35 All
GND 12
34 GND
33 Al0
ALEorAS 13
PA714
32 A9
PA615
31 A8
PA516
30 AD7/A7
PA417
29 AD6/A6
(TOP VIEW)
May. 1993
69
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
Figure 12.
DrawlngQ252PlnPQFP
(Package Type QJ
I~
Ne
1
39 Ne
PB4
2
38 A15
PB3
3
37 A14
PB2
4
36 A13
PB1
S
35 A12
PBO
6
34 A11
GND
7
33 GND
ALEor AS
8
32 A10
PA7
9
31 A9
PA610
30 A8
PAS 11
29 AD7/A7
28 AD6IA6
PA412
27 Ne
Ne 13
(TOP VIEW)
May, 1993
PSD311
70
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Ordering
Information
May. 1993
PSD311
Package Operating Manufacturing
Drawing Temperature
Procedure
Range
Spd.
(ns)
Package
Type
PSD311-90 A
90
44-pin PLCC
J2
Commercial
Standard
PSD311-90 KA
90
44-pin CLCC
L4
Commercial
Standard
PSD311-12 A
120
44-pin PLCC
J2
Commercial
Standard
PSD311-12 KA
120
44-pin CLCC
L4
Commercial
Standard
PSD311-12 B
120
52-pin POFP
02
Commercial
Standard
PSD311-15 A
150
44-pin PLCC
J2
Commercial
Standard
PSD311-151 A
150
44-pin PLCC
J2
Standard
PSD311-15 KA
150
44-pin CLCC
L4
Industrial
Commercial
PSD311-151 KA
150
44-pin CLCC
L4
Industrial
Standard
PSD311-15 B
150
52-pin POFP
02
Commercial
Standard
PSD311-151 B
150
52-pin POFP
02
Industrial
Standard
PSD311-20 A
200
44-pin PLCC
J2
Commercial
Standard
PSD311-201 A
200
44-pin PLCC
J2
Industrial
Standard
PSD311-20 KA
200
44-pin CLCC
L4
Commercial
Standard
PSD311-201 KA
200
44-pin CLCC
L4
Industrial
Standard
PSD311-20 B
200
52-pin POFP
02
Commercial
Standard
PSD311-201 B
200
52-pin POFP
02
Industrial
Standard
Part Number
71
Standard
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
May, 1993
72
PSD311
Philips Semiconductors Mlcrocontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Key Features
o
o
Single Chip Programmable Peripheral
for Microcontroller-based Applications
19 Individually Configurable I/O pins
that can be used as:
-
Microcontroller I/O port expansion
-
Programmable Address Decoder
(PAD) I/O
-
Latched address output
-
Open drain or CMOS
o
Two Programmable Arrays
(PAD A & PAD B)
-
Total of 40 Product Terms and up to
16 Inputs and 24 Outputs
Direct Address Decoding up to 1 Meg
address space and up to 16 Meg
with paging
-
-
Logic replacement
o
"No Glue" Microcontroller Chip-Set
-
Built-in address latches for multiplexed
address/data bus
Non-multiplexed address/data bus
mode
-
Selectable 8 or 16 bit data bus width
-
ALE and Reset polarity programmable
-
Selectable modes for read and write
control bus as RD/WR, R/W/E, or
R/W/DS
-
BHE pin for byte select in 16-bit mode
PSEN pin for 8051 users
o
-
-
May. 1993
o
512 Kbits of UV EPROM
-
Configurable as 64K x 8 or as 32K x 16
-
Divides into 8 equal mappable blocks
for optimized mapping
-
Block resolution is 8K x 8 or 4K x 16
-
120 ns EPROM access time, including
input latches and PAD address
decoding.
o
16 Kbit Static RAM
-
Configurable as 2K x 8 or as 1K x 16
-
120 ns SRAM access time, including
input latches and PAD address
decoding
o
Address/Data Track Mode
-
Enables easy Interface to Shared
Resources (e.g., Mail Box SRAM) with
other Microcontrollers or a Host
Processor
o
-
o
To Expand the Address Space of
Microcontrollers with Limited Address
Space Capabilities
Up to 16 pages
73
CMiser-Bit
Programmable option to further reduce
power consumption
-
Built-In Security
Locks the PSD302 and PAD Decoding
Configu ratio n
o
Available in a Choice of Packages
-
44 Pin PLCC and CLCC
-
52 Pin PQFP
o
Built-In Page Logic
PSD302
o
Simple Menu-Driven Software:
Configure the PSD302 on an IBM PC
Pin and Function Compatible with
the PSD301
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
PSD302
Security
Mode
Security Mode in the PSD3XX locks the
contents of the PAD A , PAD B and all the
configuration bits. The EPROM, SRAM,
and 1/0 contents can be accessed only
through the PAD. The Security Mode can
be set by the MAPLE or Programming
software. In window packages, the mode is
erasable through UV full part erasure. In
the security mode, the PSD3XX contents
cannot be copied on a programmer.
CMlser-BIt
The CMiser-Bit provides a programmable
option for power-sensitive applications that
require further reduction in power
consumption. The CMiser-Bit (CMiser = 1)
in the Maple portion of the PSD3XX sytem
development software can be used to
reduce power consumption. The CMiser-Bit
turns off the EPROM blocks in the PSD3XX
whenever the EPROM is not accessed,
thereby reducing the active current
consumed by the PSD3XX.
In the default mode, or if the PSD3XX is
configured without programming the
CMiser-Bit (CMiser = 0), the device
operates at specified speed and power
rating as specified in the A.C. and D.C.
Characteristics.
Absolute
Maximum
Ratlngsl
Symbol
TSTG
However, if the CMiser-Bit is programmed
(CMiser = 1), the device consumes even
lower current, and is reflected in the data
sheet. This mode has an adder in
propagation delay in T5, T6, and T7
parameters in the A.C. Characteristics, and
should be added to compute worst-case
timing requirements in the application.
Condition
Parameter
Storage Temperature
CERDIP
Min
Max
Unit
-65
+ 150
°C
PLASTIC
-65
+ 125
°C
Voltage on any Pin
With Respect to GND
-0.6
+7
V
Vpp
Programming
Supply Voltage
With Respect to GND
-0.6
+14
V
Vcc
Supply Voltage
With Respect to GND
-0.6
+7
V
>2000
V
ESD Protection
NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.
Operating
Range
Recommended
Operating
Conditions
May, 1993
Range
Temperature
Vee
Commercial
0° C to +70°C
+5V
Industrial
-40° C to +80°C
+5V
Military
-55° C to + 125°C
+5V
Symbol
Parameter
vcc
Supply Voltage
VIH
High-level Input Voltage
VIL
Low-level Input Voltage
74
Vee Tolerance
-12
-15
-20
± 10%
±10%
±10%
±10%
±10%
±10%
Conditions
Min
All Speeds
4.5
=4.5 V to 5.5 V
Vee =4.5 Vto 5.5 V
2
Vce
0
Typ Max Unit
5
5.5
V
V
0.8
V
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
DC
Characteristics
Symbol
Parameter
Conditions
PSD302
CMiser=1
Subtract:
Min Typ Max Min Typ Max Unit
IOL=20~
VOL
IS81
0.45
V
Vcc Standby
Current (CMOS)
(Notes 2 and 4)
Comm'l
50
100
~
~
Active Current
(CMOS) (SRAM
Block Selected
(Notes 2 and 5)
ICC3
0.15
Vcc= 4.5 V
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
ICC2
V
Output High
Voltage
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
ICC1
0.1
Vcc = 4.5 V
IOL = 8 rnA
Vcc = 4.5 V
IOH=-20~
VOH
0.01
Output Low
Voltage
IOH =-2 rnA
Vcc=4.5V
4.4
4.49
V
2.4
3.9
V
IndlMil
75
150
Comm'l
(Note 6)
16
35
7
10
rnA
Comm'l
(Note 7)
28
50
7
10
rnA
Ind/Mil
(Note 6)
16
45
7
10
rnA
Ind/Mil
(Note 7)
28
60
7
10
rnA
Comm'l
(Note 6)
16
35
0
0
rnA
Comm'l
(Note 7)
28
50
0
0
rnA
IndlMil
(Note 6)
16
45
0
0
rnA
IndlMii
(Note 7)
28
60
0
0
rnA
Comm'l
(Note 6)
47
80
7
10
rnA
Comm'l
(Note 7)
59
95
7
10
rnA
Ind/Mil
(Note 6)
47
100
7
10
rnA
Ind/Mil
(Note 7)
59
115
7
10
rnA
III
Input Leakage
Current
VIN = 5.5 V
orGND
-1
±0.1
1
~
ILO
Output Leakage
Current
VOUT = 5.5 V
orGND
-10
±5
10
~
CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
TTL inputs: V1L ~ 0.8 V, VIH ~ 2.0 V.
CSI/A19 is high and the part is in a power-down configuration mode.
Add 3.0 rnA/MHz for AC power component (power = AC + DC).
Ten (10) PAD product terms active. (Add 380 IlA per product term, typical, or 480 !lA
per product term maximum
7. Forty-one (41) PAD product terms active.
NOTES: 2.
3.
4.
5.
6.
May, 1993
75
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
AC Chalacterlstlcs
-90
Symbol
Parameter
-12
-20
-15
Min Max Min Max Min Max Min Max
CMlser.1 Unit
Add:
T1
ALE or AS Pulse Width
20
30
40
50
0
ns
T2
Address Set-up Time
5
9
12
15
0
ns
T3
Address Hold Time
8
9
12
15
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
0
0
ns
T5
ALE Valid to Data Valid
ns
T6
T7
100
130
160
200
10
Address Valid to Data Valid
90
120
150
200
10
ns
CSI Active to Data Valid
100
130
160
200
15
ns
T8
Leading Edge of Read
to Data Valid
32
38
55
60
0
ns
T9
Read Data Hold Time
0
ns
T10
Trailing Edge of Read to
Data High-Z
0
ns
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
0
0
0
0
0
ns
RD, E, PSEN, or DS
Pulse Width
40
45
60
75
0
ns
T12
T12A
0
0
0
32
32
0
35
40
WR Pulse Width
20
25
35
45
0
ns
T13
Trailing Edge of Write or
Read to Leading Edge
of ALE or AS
0
0
0
0
0
ns
T14
Address Valid to Trailing
Edge of Write
90
120
150
200
0
ns
T15
CSI Active to Trailing Edge
of Write
100
130
160
200
0
ns
T16
Write Data Set-up Time
20
25
30
40
0
ns
T17
Write Data Hold Time
5
5
10
15
0
ns
T18
Port to Data Out Valid
Propagation Delay
0
ns
T19
Port Input Hold Time
0
0
0
0
0
ns
T20
Trailing Edge of Write
to Port Output Valid
40
40
50
60
0
ns
T21
ADi or Control to CSOi
Valid
6
25
6
30
6
35
5
45
0
ns
T22
ADi or Control to CSOi
Invalid
5
25
5
30
4
35
4
45
0
ns
May, 1993
30
30
76
35
45
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
AC Characteristics (Cont.)
-90
Symbol
Parameter
-12
-20
-15
Min Max Min Max Min Max Min Max
eMiser.1 Unit
Add:'"
T23
Track Mode Address
Propagation Delay:
CSADOUT1 Already True
22
22
28
28
0
ns
T23A
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes
True During ALE or AS
33
33
50
50
0
ns
T24
Track Mode Trailing Edge
of ALE or AS to Address
High-Z
32
32
35
40
0
ns
T25
Track Mode Read
Propagation Delay
29
29
35
35
0
ns
T26
Track Mode Read
Hold Time
35
0
ns
T27
Track Mode Write Cycle,
Data Propagation Delay
30
0
ns
T28
Track Mode Write
Cycle, Write to Data
Propagation Delay
8
55
0
ns
T29
Hold Time of Port A
Valid During Write
CSOi Trailing Edge
2
0
ns
T30
CSI Active to CSOi Active
9
40
9
45
9
50
8
60
0
ns
T31
CSI Inactive to CSOi
Inactive
9
40
9
45
9
50
8
60
0
ns
T32
Direct PAD Input as
Hold Time
10
10
12
15
0
ns
T33
R/W Active to E or OS Start
20
20
30
40
0
ns
T34
E or OS End to RIW
20
20
30
40
0
ns
T35
AS Inactive to E high
0
0
0
0
0
ns
T36
Address to Leading
Edge of Write
20
20
25
30
0
ns
11
29
11
20
30
29
10
20
8
30
2
29
10
30
7
40
2
7
2
NOTES: 8. ADi = any address line.
9. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or
through Port C (CS8-CS10).
10. Direct PAD"!!!put = any oUDe following direct PAD input lines: CSI/A 19 as transparent
A19, ROlE/OS, WR or RIW, transparent PCo-PC2, ALE (or AS).
11. Control signals RD/E/DS or WR or RIW.
May, 1993
77
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
Figure t.
Timing of '-Bit
Multiplexed
Address/DataBus,
CRRWR=O
--
....,
CSI/A19
asCSI
READ CYCLE
WRITE CYCLE
.. --
32
4:..
'(XX XXX
J"'~
\
7
Direct (12)
PAD Input
....
32-
~~
-
15
32-
~~
STABLE INPUT
6
XXX XXX
STABLE INPUT
14
I
Multiplexed
Inputs
(13)
~
XXXXXXXX XXXXX ~XXXXX
10
6
AO/ADOA7/AD7
Active High
ALE
Active Low
ALE
~ro
ADDRESSA J
2
XXXX IXXXX
~
DATA VALID
3
~
-
,
4
~~
13
8
,
5
11
~
12
J
1\
,
36
•
WRNppor
RWasWR
18
19
XXXXXXXXX
INPUT
Any 0 f \
PBO-PB7 Xl
I
as 1/0 Pin
XXXXXXXXX
INPUT
f-+
If
~
XXXXXXXXXXXXXXXX) XX
23
23
ADDRESS A
See referenced notes on page 88.
May,1993
,
12A
~
)XXXXXXXXXXXXXXXXXXX
IJ
13
•
\---J
Any 0
PAO-PA7f ~)
I
as 1/0 Pin
-
rL
I\- U-
161-
~
XX -
~r
3
~
RD/EIDS as RD
Any 0 f
PAO-PA7 Pins
as Address
Outputs
'(
~ I\. 1/
ADDRESS B
2
'r h
1 ~
I~ f-+
DATA
;N
14
-
-
78
1\
ADDRESS B
OUTPUT
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
FlgUf,2.
Timing of '-Bit
Multlpl,x,d
AddlBSS/DataBus,
CRRWR=1
CSI/A19
asCSI
-
...,
..... -....
READ CYCLE
....
32
/X~
~
7
Direct (12)
PAD Input
Multiplexed (13)
Inputs
~~
I
AO/ADOA7/AD7
~
Active High
AS
Active Low
AS
~
6
\'f.:!l
DATA VALID
3
~
,-
13
...:-.
36
J
'~
,
"
f+--.
INPUT
"X) XXXXXXXXX
INPUT
I
23
lAny of
PAO-PA7 Pins
as Address --.-JI\.
Outputs
-
'"
~
XXXXX
,'x) XXXXXXXXX
~
XXXXXXXXXXXXXXXX) XX
IXXXXXXXXX XXXXXXXXXX
23
i-
'"
ADDRESS A
JI\.
See referenced notes on page 88.
79
LI
~
12
19
L
34
~
)XXXXXX
V-
,
35
J
18
May, 1993
17
161- l-i
34
~
J,N
)(X
I
12
WRNppor
RiWas RiW
Any of
PBO-PB7
as 1/0 Pin
[/
1
5
Any of
PAO-PA7
as 1/0 Pin
>-
3
I\.
33
8
ROlE/OS as E
DATA
ADDRESSB
2
35
~
XXX XXX
XXXX 'XXXX
XX) - \
J
ROlE/OS as OS
-
14
~
'r h
1
r--+
'-r---I
32-
.(xx XXX
14
10
ADDRESSA J
,'.
~
STABLE INPUT
XXXXXXXX XXXXX XXXXXX
6
2
32-
15
STABLE INPUT
-X~
.....
WRITE CYCLE
ADDRESS B
rOUTPUT
OUTPUT
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
PSD302
Figure 3.
Timing of 16-Blt
Multiplexed
AddrBSS/DataBus,
CRRWR=O
......
READ CYCLE
.--.
32
.......
CSIIA19
asCS I
..... .......
Multiplexed
Inputs
(13)
~ 00\
r
-
15
~
STABLE INPUT
6
X~
,XXXX
~XX
7
Direct (12)
PAD Input
~
32-
1 ~\
~
.....
WRITE CYCLE
32-
~
XXX {XXX
STABLE INPUT
14
XXXX IXXXX
XXXXXXXX lXXXX lXXXXX
-
14
6
])~
'(XXX IXXXX
'(XXXXXXX OCXXXX XXXXXX
10
DATA
;N
AO/ADOA15/AD15
2
Active High
ALE
Active Low
ALE
~ro
ADDRESSA J
3
-
~
~\
3
~
1 ~
4
,
ADDRESSB
2
~
r~
1
J~ ---+
DOC I-~
DATA VALID
16 -
'1?J" ~~
,-
8
~---I
,
11
.J
\....
13
5
~
J
it-+
Lr
12
'f
ROlE/OS as RD
J
36
13
12A ~
~
,
WR/Vpp 0 r
RiW as WR
~
18
~
19
Any 0
PAO-PA7f ~)
I
as 1/0 Pin
XXXXXXXXX
INPUT
XXXXXXXXXXXXXXXXl XX
OUTPUT
Any 0 f \
PBO-PB7 Xl
I
as 1/0 Pin
XXXXXXXXX
INPUT
JXXXXXXXXXXXXXXXXXXX
OUTPUT
Any of
PAO-PA7 Pins
as Address
Outputs
-
23
23
f4'f
-~
'f
ADDRESS A
~
See referenced notes on page 88.
May, 1993
80
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
Flgule4.
Timing 01 16-BIt
Multiplexed
AddreSS/DataBus,
CRRWR=1
-...
....,
CSI/A19
asCS I
READ CYCLE
32
~
~
n
-.. ...
WRITE CYCLE
IXX) XXXX
j'A\
7
Direct (12)
PAD Input
Multiplexed (13)
Inputs
- .....
~
~
15
6
XJ~
A151AD15
14
XXXX IXXXX
14
Active Low
AS
DATA
~
ADDRESS A J
......
1
~
3
~
.,
jN
35
~
'(
ROlE/OS as E
2
3
13
J
35
.J
36
X XXX XXX
RiWas RiW
XXXXX
18
Any 0
f
PBO-PB7
as VO Pin
~ 13
f-+
~
If
~
XXXXXXXXX
INPUT
.XXXXXXXXXXXXXXXX) XX
OUTPUT
Xl XXXXXXXXX
INPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
I
23
:.-.
~
-
J(
r--
'"
ADDRESS A
A
See referenced notes on page 88.
May, 1993
~
19
23
Any 0 f
PAO-PA7 Pins
as Address
Outputs
~ 34
,
J
WRNppor
Any 0 f ~
PAO-PA7 Xl
I
as VO Pin
~
33
12
~
'--
, Lr
J
I\.
XX~
~ ,...
t-+
5
ROlE/OS as OS
~
/
1
34
8
'I'
161-
~
J
-~
>-
ADDRESS B
DATA VALlDX}C -\c
~r--,
,
.(XXI IIXX
10
- ~.
I'r+
..
14
,(XXXXXXX XXXXX XXXXXX
2
Active High
AS
IXXX lXXX
STABLE INPUT
XXXXXXXX XXXXX XXXXXX
-~~
r-
32-
~ 0\
STABLE INPUT
6
AO/ADO-
-•
32-
81
ADDRESSB
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
Figure 5.
Timing Df '-Bit Data,
Non-Multiplexed
AddrBSS/DataBus,
eRRWR=O
-
-,
CSI/A19
asCS I
. ......
READ CYCLE
32
32---+-
l1"li
Direct (12)
~~
15
STABLE INPUT
6
AO/ADOA15/AD15
as AO-A15
~ 00
STABLE INPUT
~
Multiplexed (13)~
6
,
ALE
Active Low
ALE
ROlE/OS as RD
STABLE INPUT
fOC ~
STABLE INPUT
.ID
DATA VALID
3
r-h
1
'1+ f-+
2
1
~f..-J
,
8
13
,
.-..
-I
)"
36
19
18
Any af
PBO-PB7
as I/O Pin
,X) XXXXXXXXX
~
~
if
\_--'
13
2E..
XXXXXXXXXXXXXXXX) XX
INPUT
See referenced notes on page 88.
May, 1993
r
12
5
RiW asWR
~J
11
~
WRNp~ or
1/ XX
~
~16
\
-
171
3
~
-
DATA
IN
~
-
~
....
XXXX XXXX
14
1\
,
XXX XXX
32---+-
XX)
4
IXXX XXX
14
10
.....J
2
Active High
~~
IXXXXXXXX XXXXX XXX XXX
Inputs
PAO-PA7
.... -
I.:z: 00\
15
STABLE INPUT
6
AO/ADO
A15/AD15
as AO-A15
-~ -00
STABLE INPUT
~
>)C
Multiplexed (13
Inputs
PAO-PA7
6
~XXX
-1
2
Active High
ALE I . 1
,
DATA VALID
----.
\..--1
14
IXXX XXX
32~
I+-
XXXX XXXX
DATA
IN
1\
2
3
16i-
~
J
/ xx:~
.!lJ r
_4
-
J
36
J
~
,
13
J\XXXX
18
19
~
See referenced notes on page 88.
83
,-
A
XXXXXXXXXXXXXXXXXXX
INPUT
I
Lr
34
12
'---J
X XXX XXX
Xl XXXXXXXXX
'33
34
~
~
,
35
13
12
as OS
~
j
~
~
35
-
/
XX
~
8
WRNppor
RJWas Rfii
May. 1993
STABLE INPUT
IXXX XXX
14
5
Any of
PBO-PB7
as 1/0 Pi n
~~
~
3
ROlE/OS as E
ROlE/OS
STABLE INPUT
10
r~
Active Low
ALE
~ 0<
IXXXXXXXX ~XXXX ~XXXXX
,
~
).XX ,XXX
7
Direct (12
PAD Input
-
WRITE CYCLE
.....
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
Figure 7.
Timing of 16-Blt
Non-Multiplexed
Address/DataBus,
CRRWR=O
........
READ CYCLE
32
~
CSI/A19
asCS I
WRITE CYCLE
...... .....
IXX XXX
7
00\
15
STABLE INPUT
6
AO/ADO·
A15/AD15
as AO·A15
~
/X\
I\.
Direct (12
PAD Input l~
...
32-
~~
STABLE INPUT
~
Multiplexed (13l X
Inputs
~ P<
STABLE INPUT
~~
STABLE INPUT
IXXX XXX
14
IXXX XXX
r-
32-
IXXXXXXXX XXXXX XXXXXX
OCXXX XXXX
14
X~
'(XXX IXXXX
IAXXXXXXX lCXXXX XXXXXX
6
DATA
IN
"'
~ro
PAO·PA7
(Low Byte )....J
~
~ro
PBO·PB7
(High Byte )....J
2
Active High
ALE
Active Low
ALE
DATA VALID
~
DATA VALID
, /.
XX
I\.
3
17
~
'\
3
10
rh
1
I~ r-+
~
16
\
DATA
IN
r
~
4
~~
\
)
1\
,
X(--
, - ,,-x::A
2
8
11
13
~
12
Ro,E/OS as RD
j
5
36
12A ~
..-.
'~
WRNpp or
RiW asWR
See referenced notes on page 88.
May, 1993
-
-
84
~
~
J
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
FigureS.
Timing of 16-BIt
Non-Multiplexed
Address/DataBus,
CRRWR=1
..
WRITE CYCLE
32
32-
JO\~
\
~ 00\
STABLE INPUT
Multiplexed (13)
Inputs
-X) -00
STABLE INPUT
~
-X)
~ 0\
STABLE INPUT
~~
STABLE INPUT
XXX KXXX
14
XXX KXXX
~
32-
XXXX XXXX
IXXXXXXXX DlXXXX IXXXXXX
14
BHEIPSEN
asBHE
.x~
I'(XXXXXXX KXXXX ~XXXXX
'(XX'
DATA
IN
:m
PAO-PA7 ~
(Low Byte) -.J
PBO-PB7 ~
(High Byte) -.J
~m
Active Low
AS
r-~
1
'~ --+~~
DATA VALID
XX)
II'
I\.
2
1+-+
~
'r
35
35
•
.E..'(
r--
8
13
•
13
36
j\....
'U
f-33
34
-J
J
34
~
12
5
1\
~
,
12
L-J
J
X XXXXXX
XXXXX
See referenced notes on page 88.
May. 1993
'" XX '---
~
4
RD/EIDS as DS
/
16 17
h
I\.
DATA
IN
-
3
~
RD/EIDS as E
WRNppor
RfiJ as RfiJ
,
"
XX)
10
3
,
"'XX r/
DATA VALID
~
Active High
AS
-
XXXX~
6
2
XXXX
15
6
AO/ADOA15/AD15
as AO-A15
....
~XX
7
Direct (12)
PAD Input
-
.....
.....,
CSI/A19
asCSI
.... ..
READ CYCLE
....
85
,---
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
Figure 9.
Chip-Select
Output Timing
30
,
31
~
CSI/A19
asCSI
"""'"'
Direct PAD (12)
Input
Multiplexed
PAD Inputs
(18)
INPUT STABLE
J
I
,
X;
'XXXXXXX I(X XX
2
ALE
. (Multiplexed
Mode Only)
orALE
(Multiplexed
Mode Only)
'r ......,
1 I\.
114- -.
,
,
3
'(
~W
...
'---
22
21
CSc5i (14,1 9)
~
See referenced notes on page 88.
May, 1993
J~
86
J
r--
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
Figure 10.
PortA
as ADO-AD7 Timing
(Track Mode),
CRRWR=O
.......
Direct
PAD Input
(16,18)
STABLE INPUT
~~
or ALE
2
(
- 'IJ
~
ADDRESS
~'I:t.X
J
rh
1 1\
f..J~ ~
-n
~W
I
3
~{
If WRITIEN
DATA
~
32
r~
"
32
~
4
,
ROlE/OS as RD
12
I\.
If
\.----J
-.. 27 f4-
WRIVppor
24
Alii as WR
-
-..
ro
ADROUT)
24
KXXX
DATA IN
XXX>- -00 ADROUT;
-..
23 ~
23
-4---
,
12A
J
""
00
DATA
OUT
~
28
r---
CSOi
(14,17)
J
See referenced notes on page 88.
May, 1993
r-\
\.J
J
11
PAO-PA7
>-
ADDRESS
I....!.-.
X
XXXXXXX
STABLE INPUT
2
26
DATA VALID
~
):xxx
STABLE INPUT
\
XXXXXXXXXXXXX ~XXX ,X
3
_
~
2
STABLE INPUT
.
WRITE CYCLE
...
32-.
21
AO/ADOA7/AD7
ALE
~
\
(12,15)
Multiplexed
PAD Inputs
..
READ CYCLE
87
~
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
Figure 11. Port A as ADO-AD7 Timing
(Track Mode), CRRWR = 1
-Direct
PAD Input
(12,15)
READ CYCLE
..
WRITE CYCLE
~
STABLE INPUT
J~
-
r
~
32-
~
STABLE INPUT
~
21
Multiplexed
PAD Inputs
(16,18)
)( XX I\. STABLE INPUT
2
AO/ADOA7/AD7
IXX X XXXXXXXX XX XXXXXX
3
~
:ro
ADDRESS
'f
26
,X
XXXXXXX
3
2
~
DATA VALID
STABLE INPUT
I
ro-
ADDRESS
~
WRITTEN
DATA
I-
32AS
or AS
'r~
r~
- UI+ --.1\
1
...:!-.
-~
'f
35
1\..--
f\
1\
1-.
RD/E/DS as E
33 ....
~
,
'f
J
J
WR/Vppor
RlWas RiiJ
X
X~
XXX X
1\
-
(XX ADR OUTJ HXXX
-. 23
....
24
DATA IN
-.
23
....
...
27
XX
28
.-.
~
DATA
OUT
ID-
29
~
L-J'f
CSOi
(14,17)
Notes for
Timing
Diagrams
m>- KX
ADROUT
~
r
XX} .XXXX
34
24
PAC-PA7
\
-. 34
I
J
RD/E/DS as DS
\...J
12
35
12
12. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19,
RDIE, WR or RIW, transparent PCO-PC2, ALE in non-multiplexed modes.
13. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS):
AO/ADO-A15/AD15, CSIIA19 as ALE dependent A19, ALE dependent PCO-PC2.
14. CSOi = ~ of the chip-select output signals coming through Port B (CSO-CS7) or through
Port C (CS8-CS10).
15. CSADOUT1, which internally enables the address transfer to Port A, should be derived only
from direct PAD input signals, otherwise the address propagation delay is slowed down.
16. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively,
can be derived from any combination of direct PAD inputs and multiplexed PAD inputs.
17. The write operation signals are included in the CSOi expression.
18. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in
the multiplexed modes: A11/AD11-A15/AD15, CSIIA19 as ALE dependent A19, ALE dependent
PCO-PC2.
19. CSOi product terms can include any of the PAD input signals except for reset and CSI.
May, 1993
88
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
Pin
Capacltance 20
Symbol
PSD302
Conditions Typical21 Max Unit
Parameter
CIN
Capacitance (for input pins only)
COUT
Capacitance (for input/output pins)
CvPP
Capacitance (for WR/vpp or RIWNpp)
=0 V
VOUT = 0 V
Vpp = 0 V
VIN
4
6
12
pF
8
18
25
pF
pF
NOTES: 20. This paramter is only sampled and is not 100% tested.
21. Typical values are for TA = 25°C and nominal supply voltages.
Figure 12.
AC Testing
Input/Output
Waveform
v:
3· 0 V - Y
-.1\
TEST POINT -
~v
0V
Figure 13.
AC Testing
Load Circuit
2.01 V
-,....
<
~ 1950
DEVICE
UNDER
TEST
I
--- CL =30pF
_
Erasure and
Programming
To clear all locations of their programmed
contents, expose the device to ultra-violet
light source. A dosage of 15 W second/cm2
is required. This dosage can be obtained
with exposure to a wavelength of 2537 A
and intensity of 12000 Jj.W/cm 2 for 15 to 20
minutes. The device should be about 1
inch from the source, and all filters should
be removed from the UV light source prior
to erasure.
The PSD3XX and similar devices will erase
with light sources having wavelengths
shorter than 4000 A. Although the erasure
times will be much longer than with UV
May, 1993
89
(INCLUDING
SCOPE AND JIG
CAPACITANCE)
sources at 2537 A, exposure to fluorescent
light and sunlight eventually erases the
device. For maximum system reliability,
these sources should be avoided. If used in
such an environment, the package windows
should be covered by an opaque
substance.
Upon delivery, or after each erasure, the
PSD3XX device has all bits in the PAD and
EPROM in the "1" or high state. The configuration bits are in the "0" or low state. The
code, configuration, and PAD MAP data are
loaded through the procedure of programming
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Pin
Assignments
44-Pin
PLCC;CLCC
Package
Pin Name
BHE/PSEN
WR/vpp or R/W
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
GND
ALE or AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
RD/E/DS
ADO/AO
AD1/A1
AD2IA2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD10/A10
GND
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
PCO
PC1
PC2
A19/CSI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Vcc
NOTE: 36. Pins 1, 13, 14, 26, 27, 39,40, and 52 are No Connect.
May, 1993
90
PSD302
52-Pin
POFP Package
46
47
48
49
50
51
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
36
37
38
41
42
43
44
45
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
Package
Information
Figure 14.
DrawlngL444 Pin Ceramic
Leaded Chip
Carrier (CLCC)
with Window
(Package Type L)
....
0
oQ,
0
...
0
....
Q,
PB4
7
39 AD15/A15
PB3
8
38 AD/14/A14
PB2
9
37 AD13/A13
o
PB1 10
PBO 11
GND 12
ALE or AS 13
PA714
PA6 15
36 AD121A12
35 AD11/A11
34 GND
33 AD10/A10
32 AD9/A9
31 AD8/A8
PA5 16
30 AD7/A7
PA4 17
29 AD6/A6
~ ~ ~
M
~
...
N ~ ~ ~ ~ ~ ~ ~
0
~ ~ ~ ~
(TOP VIEW)
Figure 15.
DrawlngJ244 Pin Plastic
Leaded Chip
Carrier (PLCC)
with Window
(Package Type J)
/0
ffi
I~
0
...
~
M
..
~
~ ~ ~ ~ ~ ~
51 51 51 51 51 51
uuuuuuuuuuu
PB4
7
39 AD15/A15
PB3
8
39 AD14/A14
PB2
9
37 AD13/A13
PB1 10
36 AD12/A12
PBO 11
35 AD11/A11
34 GND
GND 12
33 AD10/A10
ALEorAS 13
32 AD9/A9
PA714
PA615
31 AD8/A8
PA516
30 AD7/A7
PA417
29 AD6/A6
~ ~ ~
M
(TOP VIEW)
May, 1993
~
...
N~
~ ~ ~ ~ ~ ~
0
0
10
...
~
M
..
~
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
I~ ~ ~ ~ ~ ~ ~
91
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD302
Figure 16.
DrawlngQ252PlnPQFP
(Package Type QJ
NC
1
39 NC
PB4
2
38 AD15/A15
PB3
3
37 AD14/A14
PB2
4
36 AD13/A13
PB1
5
35 AD121A12
PBO
6
34 AD11/A11
GND
7
33 GND
ALEor AS
8
32 AD10/A10
PA7
9
31 AD9/A9
PA610
30 AD8/A8
PA5 11
29 AD7/A7
PA412
28 AD6IA6
27 NC
NC 13
(TOP VIEW)
May, 1993
92
Philips Semiconductors Microcontro/ler Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Ordering
Information
May. 1993
Part Number
Spd.
(ns)
Package
Type
PSD302
WSI
Package Operating
Temperature
Manufacturing
Drawing
Range
Procedure
PSD302-90 A
90
44-pin PLCC
J2
Commercial
Standard
PSD302-90 KA
90
44-pin CLCC
L4
Commercial
PSD302-12 A
120
44-pin PLCC
J2
Commercial
Standard
Standard
PSD302-12 KA
120
44-pin CLCC
L4
Commercial
Standard
PSD302-12 B
120
52-pin POFP
Q2
Commercial
Standard
PSD302-15 A
150
44-pin PLCC
J2
Commercial
Standard
PSD302-151 A
150
44-pin PLCC
J2
Industrial
Standard
PSD302-15 KA
150
44-pin CLCC
L4
Commercial
Standard
PSD302-151 KA
150
44-pin CLCC
L4
Industrial
Standard
PSD302-15 B
150
52-pin POFP
02
Commercial
Standard
PSD302-151 B
150
52-pin POFP
02
Industrial
Standard
PSD302-20 A
200
Commercial
Standard
200
44-pin PLCC
44-pin PLCC
J2
PSD302-201 A
J2
Industrial
Standard
PSD302-20 KA
200
44-pin CLCC
L4
Commercial
Standard
PSD302-201 KA
200
44-pin CLCC
L4
Industrial
Standard
PSD302-20 B
200
52-pin POFP
02
Commercial
Standard
PSD302-201 B
200
52-pin POFP
02
Industrial-
Standard
93
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
May,1993
94
PSD302
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Key Features
a
Single Chip Programmable Peripheral
for Microcontroller-based Applications
a
19 Individually Configurable I/O pins
that can be used as:
-
Microcontroller I/O port expansion
-
Programmable Address Decoder
(PAD) I/O
-
Latched address output
-
Open drain or CMOS
a
Two Programmable Arrays
(PAD A & PAD B)
-
Total of 40 Product Terms and up to
16 Inputs and 24 Outputs
-
Direct Address Decoding up to 1 Meg
address space and up to 16 Meg
with paging
-
Logic replacement
o
"No Glue" Microcontroller Chip-Set
-
Built-in address latches for multiplexed
address/data bus
-
Non-multiplexed address/data bus
mode
-
8-bit data bus width
-
ALE and Reset polarity programmable
-
Selectable modes for read and write
control bus as RD/WR, R/W/E, or
R/W/DS
PSEN pin for 8051 users
o
May.
1993
Built-In Page Logic
-
To Expand the Address Space of
Microcontrollers with Limited Address
Space Capabilities
-
Up to 16 pages
95
PSD312
a
512 Kbits of UV EPROM
-
Configurabl~
-
Divides into 8 equal mappable blocks
for optimized mapping
-
Block resolution is 8K x 8
-
120 ns EPROM access time, including
input latches and PAD address
decoding.
as 64K x 8
a
16 Kbit Static RAM
-
Configurable as 2K x 8
-
120 ns SRAM access time, including
input latches and PAD address
decoding
o
Address/Data Track Mode
-
Enables easy Interface to Shared
Resources (e.g., Mail Box SRAM) with
other Microcontrollers or a Host
Processor
a
CMiser-Bit
-
Programmable option to further reduce
power consumption
o
Built-In Security
Locks the PSD312 and PAD Decoding
Configuration
-
a
Available in a Choice of Packages
-
44 Pin PLCC and CLCC
-
52 Pin PQFP
a
Simple Menu-Driven Software:
Configure the PSD312 on an IBM PC
a
Pin and Function Compatible with
the PSD31X
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD312
Security
Mode
Security Mode in the PSD3XX locks the
contents of the PAD A , PAD B and all the
configuration bits. The EPROM, SRAM,
and I/O contents can be accessed only
through the PAD. The Security Mode can
be set by the MAPLE or Programming
software. In window packages, the mode is
erasable through UV full part erasure. In
the security mode, the PSD3XX contents
cannot be copied on a programmer.
CM/ser-BIt
The CMiser-Bit provides a programmable
option for power-sensitive applications that
require further reduction in power
consumption. The CMiser-Bit (CMiser = 1)
in the Maple portion of the PSD3XX sytem
development software can be used to
reduce power consumption. The CMiser-Bit
turns off the EPROM blocks in the PSD3XX
whenever the EPROM is not accessed,
thereby reducing the active current.
consumed by the PSD3XX.
In the default mode, or if the PSD3XX is
configured without programming the
CMiser-Bit (CMiser = 0), the device
operates at specified speed and power
rating as specified in the A.C. and D.C.
Characteristics.
Absolute
Maximum
Ratings 1
Symbol
Min
Max
CERDIP
-65
+ 150
°C
PLASTIC
-65
+ 125
°C
Voltage on any Pin
With Respect to GND
-0.6
+7
V
Vpp
Programming
Supply Voltage
With Respect to GND
-0.6
+14
V
Vcc
Supply Voltage
With Respect to GN D
-0.6
+7
V
>2000
V
TSTG
Parameter
However, if the CMiser-Bit is programmed
(CMiser = 1). the device consumes even
lower current, and is reflected in the data
sheet. This mode has an adder in
propagation delay in T5, T6, and T7
parameters in the A.C. Characteristics, and
should be added to compute worst-case
timing requirements in the application.
Condition
Storage Temperature
ESD Protection
Unit
NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.
Operating
Range
Temperature
Range
Commercial
Recommended
Operating
Conditions
May, 1993
0° C to +70°C
+5V
Industrial
-40° C to +80°C
+5V
Military
-55° C to + 125°C
+5V
Symbol
Vee Tolerance
Vee
Parameter
-12
-15
-20
± 10%
±10%
±10%
±10%
Conditions
Min
vcc
Supply Voltage
All Speeds
4.5
VIH
High-level Input Voltage
V cc = 4.5 V to 5.5 V
2
VIL
Low-level Input Voltage
V cc
= 4.5 V to 5.5 V
0
96
±10%
±10%
Typ Max Unit
5
5.5
V
V
0.8
V
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
DC
Characteristics
Symbol
Parameter
Output Low
Voltage
VOL
Output High
Voltage
VOH
Vcc Standby
Current (CMOS)
(Notes 2 and 4)
IS81
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
ICC1
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
ICC2
Active Current
(CMOS) (SRAM
Block Selected
(Notes 2 and 5)
ICC3
Conditions
PSD312
CMiser= 1
Subtract:
Min Typ Max Min Typ Max Unit
IOL = 20 JJ.A
Vcc = 4.5 V
0.01
IOL = 8 rnA
Vcc = 4.5 V
0.15 0.45
V
0.1
V
IOH = -20 JJ.A
Vcc = 4.5 V
4.4
4.49
V
IOH =-2 rnA
Vcc = 4.5 V
2.4
3.9
V
JJ.A
JJ.A
Comm'l
50
100
IndlMii
75
150
Comm'l
(Note 6)
16
35
7
10
rnA
Comm'l
(Note 7)
28
50
7
10
rnA
Ind/Mil
(Note 6)
16
45
7
10
rnA
Ind/Mil
(Note 7)
28
60
7
10
rnA
Comm'l
(Note 6)
16
35
0
0
rnA
Comm'l
(Note 7)
28
50
0
0
rnA
Ind/Mil
(Note 6)
16
45
0
0
rnA
IndlMii
(Note 7)
28
60
0
0
rnA
Comm'l
(Note 6)
47
80
7
10
rnA
Comm'l
(Note 7)
59
95
7
10
rnA
Ind/Mil
(Note 6)
47
100
7
10
rnA
Ind/Mil
(Note 7)
59
115
7
10
rnA
III
Input Leakage
Current
VIN = 5.5 V
orGND
-1
±0.1
1
JJ.A
ILO
Output Leakage
Current
VOUT = 5.5 V
orGND
-10
±5
10
JJ.A
NOTES: 2.
3.
4.
5.
6.
CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
TTL inputs: VIL ~ 0.8 V, VIH ~ 2.0 V.
CSI/A19 is high and the part is in a power-down configuration mode.
Add 3.0 mA/MHz for AC power component (power = AC + DC).
Ten (10) PAD product terms active. (Add 380 J.l.A per product term, typical, or 480 J.LA
per product term maximum
7. Forty-one (41) PAD product terms active.
May, 1993
97
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
PSD312
AC Characteristics
-90
Symbol
Parameter
-12
-20
-15
Min Max Min Max Min Max Min Max
eMlser= 1 Unit
Add:
T1
ALE or AS Pulse Width
20
30
40
50
0
ns
T2
Address Set-up Time
5
9
12
15
0
ns
T3
Address Hold Time
8
9
12
15
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
0
0
ns
T5
ALE Valid to Data Valid
200
10
ns
T6
Address Valid to Data Valid
90
120
150
200
10
ns
T7
CSI Active to Data Valid
100
130
160
200
15
ns
T8
Leading Edge of Read
to Data Valid
32
38
55
60
0
ns
T9
Read Data Hold Time
0
ns
T10
Trailing Edge of Read to
Data High-Z
0
ns
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
0
0
0
0
0
ns
RD, E, PSEN, or DS
Pulse Width
40
45
60
75
0
ns
T12
100
0
130
0
0
32
160
32
0
40
35
WR Pulse Width
20
25
35
45
0
ns
T13
Trailing Edge of Write or
Read to Leading Edge
of ALE or AS
0
0
0
0
0
ns
T14
Address Valid to Trailing
Edge of Write
90
120
150
200
0
ns
T15
CSI Active to Trailing Edge
of Write
100
130
160
200
0
ns
T16
Write Data Set-up Time
20
25
30
40
0
ns
T17
Write Data Hold Time
5
5
10
15
0
ns
T18
Port to Data Out Valid
Propagation Delay
T19
Port Input Hold Time
0
0
0
T20
Trailing Edge of Write
to Port Output Valid
40
40
50
T21
ADi or Control to CSOi
Valid
6
25
6
30
6
35
5
T22
ADi or Control to CSOi
Invalid
5
25
5
30
4
35
4
T12A
May, 1993
30
30
98
45
0
ns
0
0
ns
60
0
ns
45
0
ns
45
0
ns
35
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD312
AC Characteristics (Cont.)
-90
Symbol
Parameter
-12
-20
-15
eMiser.1 Unit
Add:
Min Max Min Max Min Max Min Max
Track Mode Address
Propagation Delay:
CSADOUT1 Already True
22
22
28
28
0
ns
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes
True During ALE or AS
33
33
50
50
0
ns
T24
Track Mode Trailing Edge
of ALE or AS to Address
High-Z
32
32
35
40
0
ns
T25
Track Mode Read
Propagation Delay
29
29
35
35
0
ns
T26
Track Mode Read
Hold Time
35
0
ns
T27
Track Mode Write Cycle,
Data Propagation Delay
30
0
ns
T28
Track Mode Write
Cycle, Write to Data
Propagation Delay
8
55
0
ns
T29
Hold Time of Port A
Valid During Write
CSOi Trailing Edge
2
0
ns
T30
CSI Active to CSOi Active
9
40
9
45
9
50
8
60
0
ns
T31
CSllnactive to CSOi
Inactive
9
40
9
45
9
50
8
60
0
ns
T32
Direct PAD Input as
Hold Time
10
10
12
15
0
ns
T33
R/W Active to E or DS Start
20
20
30
40
0
ns
T34
E or DS End to RIW
20
20
30
40
0
ns
T35
AS Inactive to E high
0
0
0
0
0
ns
T36
Address to Leading
Edge of Write
20
20
25
30
0
ns
T23
T23A
11
29
11
10
20
20
30
29
8
30
2
29
10
30
7
40
2
7
2
NOTES: 8. ADi = any address line.
9. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or through Port C (CS8-CS1 0).
10. Direct PAD'!!!put = any of the following direct PAD input lines: CSI/A 19 as transparent
A19, RO/E/OS, WR or RIW, transparent PCO-PC2, ALE (or AS).
11. Control signals RO/E/DS or WR or Rm.
May, 1993
99
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Figure 1.
TIming of B-Blt
Multiplexed
Addl'BSS/OataBus,
CRRWR=O
....
CSI/A19
asCS I
.....
READ CYCLE
., -
PSD312
32
32-
~
.(XX XXX
I"'~
~
7
Direct (12
PAD Input
.....
WRITE CYCLE
....
>:x ~
-
15
~
STABLE INPUT
6
32-
~
XXX XXX
STABLE INPUT
14
I
Multiplexed
Inputs
(13
>X)
XXXXXXXX XXXXX XXXXXX
-
AO/ADOA7/AD7
Active Low
ALE
~m
ADDRESSA J
2
Active High
ALE
10
6
J
DATA VALID
3
DATA
14
XX) - \
2
~
r~
1
J'r+ !-+
XXXX XXXX
ADDRESSB
>-
3
J
,
4
~~
13
.,. 1/ J4
1\
XX:~-
161-
~
1\
I~ r
11
,
~
r-I
8
rL
J
1 1\
..,.;..
-
..r
12
ROlE/OS as RD
1
1\
5
,
J
WR/Vppor
RWasWR
19
Any 0 f '"
PAO-PA7 IX
as 1/0 Pin
XXXXXXXXX
INPUT
Any 0 f \
PBO-PB7 Xl
I
as 1/0 Pin
XXXXXXXXX
INPUT
Anyof
PAO-PA7 Pins
as Address
--
.~
ADDRESS A
if
~
XXXXXXXXXXXXXXXX) XX
OUTPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
JI\.
Outputs
See referenced notes on page 106.
May. 1993
!4-""
23
!::=
-----'1\
12
,..---.
-
23
13
II
~
...----..
18
36
"4
100
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD312
Figure 2.
Timing of '-Bit
Multiplexed
AddressIDataBus,
CRRWR=1
...CSI/A19
asCSI
~
-
READ CYCLE
32
WRITE CYCLE
......
Jr.x~
~
Multiplexed
Inputs
(13)
AO/ADOA7/AD7
Active High
AS
Active Low
AS
15
XX
STABLE INPUT
I
6
~
14
~XXX XXXX
IXXXXXXXX XXXXX OCXXXXX
6
J~ ADDRESS A
2
4
,'... -+
~XX'J..,
J
DATA VALID
~ -"1\
~
16
35
13
..i.
35
r---
I~~
'~
12 ~
~
~
)XXXXXXy
AXAXA
18
Any of
PAO-PA7 Pins
as Address
Outputs
19
w
OUTPUT
INPUT
IXXXXXXXXXXXXXXXXXXX
OUTPUT
23
f-
w
ADDRESS A
JI\.
See referenced notes on page 106.
May, 1993
~
XXXXXXXXXXXXXXXXXXX
~
----11\.
r-
INPUT
\.
X) XXXXXXXXX
rL
,
'- L!
36
12
"X) XXXXXXXXX
I
r-
34
33
34
8
I
H
~
ROlE/OS as OS
Any of
PBO-PB7
as 1/0 Pin
~
J
5
Any of
PAO-PA7
as 1/0 Pin
171
3
~
h
ROlE/OS as E
WRNppor
RiNas RiN
~ \ 1/ )QC~-
ADDRESS B
2
\
\..--1
DATA
I,N
14
10
..
3
rh
1
!XXX XXX
STABLE INPUT
I
-~~
-
I-
32-
~~
-
11XX XXX
7
Direct (12)
PAD Input
I+-
32-
101
ADDRESS B
~
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD312
FIgure 3.
TImIng of '-Bit Data,
Non-MultIplexed
AddrBSS/DataBus,
CRRWR=D
..-
~
CSI/A19
asCS I
READ CYCLE
...
32
irJ
32-+-
'(XX XXX
JIf..J\
\
7
Direct
PAD Input
(12
)~
AO/ADOA15/AD15
as AO-A15
Multiplexed
Inputs
(13
)
PAO-PA7
~
Active Low
ALE
15
STABLE INPUT
STABLE INPUT
~
~~
~ P\
STABLE INPUT
~ P<
STABLE INPUT
I~
6
~~
,
;m...
--1
DATA VALID
XX)
~
3
It- ~
1
11+ ---+
,
~ -1
8
13
IXXX XXX
....
14
2
--I
DATA
f
\.
3
~
--
J,N
1/ 't\A -
XXXX XXXX
-+16
.!.
4
•
32-+-
10
6
IXXX XXX
14
IXXXXXXXX O(XXXX ~XXXXX
2
Active High
ALE
.... -
WRITE CYCLE
--
~r
\....
i'+-J
,
~
11
J
12
f
ROlE/OS as RD
36
j
1+--+
WRNpp or
RiW as WR
,~
5
19
18
Any 0
t
PBO-PB7
as 1/0 Pin
'k) IXXXXXXXXX
I
lEXXXXXXXXXXXXXXXX) XX
INPUT
See referenced notes on page 106.
May, 1993
13
12
102
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD312
Flgule4.
Timing of 8-BIt Data,
NOR-Multiplexed
AddleSS/DataBus,
CRRWR=1
-
~
CSI/A19
asCSI
-.. ..
READ CYCLE
.....
32
h- ~
IAXX XXX
15
~
STABLE INPUT
6
AO/AOOA151A015
as AO-A15
Multiplexed
Inputs
(13)
PAO-PA7
Active High
ALE
Active Low
ALE
-~ -OC
STABLE INPUT
.B-.
)G
--'
~ 0\
STABLE INPUT
~~
STABLE INPUT
2
DATA VALID
IXXXX 'XXXX
14
\
2
~
3
h
16,-
~:-..J
35
4
13
..
ROlE/OS as E
33
-}
36
12
ROlE/OS as OS
Any of
PBO-PB7
as VO Pin
,X
XXXXXXXXX
19
INPUT
See referenced notes on page 106.
May, 1993
,
'(
13
XXXXX
18
\
1\'
12
1-
OC XXXXXX
RNJas RiW
103
..r
~ 34
~
~
-
L
~
~
34
8
5
WRNppor
~r
~
35
-
X-
1/
)
1
, ---
-
DATA
IN
X)O
~
3
r~
J.
f.-
/
~~
XXX
LXXX XXX
32-'
10
6
~XX
14
XXXXXXXX )(XXXX XXXXXX
,
-
32 ... ~
A.x~
~
7
Direct (12)
PAD Input
WRITE CYCLE
~
XXXXXXXXXXXXXXXXXXX
'r
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD312
FigureS.
Chip-Select
Output Timing
30
31
CSI/A19
asCSI
Direct PAD (12)
Input
Multiplexed
PAD Inputs
INPUT STABLE
(18)
3
ALE
(Multiplexed
Mode Only)
orALE
(Multiplexed
Mode Only)
21
CSOi
(14,19)
See referenced notes on page 106.
May, 1993
104
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD312
FlgureB.
PortA
as ADO-AD7 Timing
(Track Mode),
CRRWR=O
-
READ CYCLE
....
Direct
PAD Input
(16.18)
32-.
r---)(~
AO/ADOA7/AD7
STABLE INPUT
I
2
2
IX. X. X. X. X. X. X.XX XX X XOCXXX X
STABLE INPUT
2
3
~
ADDRESS
J
:ro
J
..
WRITE CYCLE
.....
STABLE INPUT
\.
(12.15)
Multiplexed
PAD Inputs
~
....
DATA VALID
ALE
orALE
-I-'
1
1+ --.
3
~~
~
ADDRESS
'(' WRITTEN
DATA
~
n.
r~
1\
.1-.
-h
~ ---1
32
4
,
RD/E/DS as RD
f4--+
12
\
\,----1
I
-. 27 14...
24
PAC-PA7
-
-.
:xx
23
-
ADR OUTJ
KXXX
,
24
DATA IN
'tAX)- KXX ADR OUT'
-.
~
23
I+-
J
{XX
DATA
OUT
29
......--.
~
CSOi
J
(14.17)
See referenced notes on page 106.
May. 1993
105
V
12A
11
WRlVpp or
Alii as WR
X
~XXXXXX
STABLE INPUT
32
'r ---,
Jm..
-'
2
26
~
~
y:jj-
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD312
Figure 11. Po" A as ADO-AD7 Timing
(Track Mode), CRRWR =1
....
Direct
PAD Input
(12,15)
Multiplexed
PAD Inputs
(16,18)
READ CYCLE
~
-
STABLE INPUT
J
.... ..
.....
WRITE CYCLE
......
32-
J
2
XXX
- \ STABLE INPUT IXXXXXXXXXXXXX XX) XXX
2
AO/ADOA7/AD7
3
-
~
ADDRESS
~
J
DATA VALID
,X
XXXXXXX
STABLE INPUT
3
2
26
I
XX}-(
WRITTEN
DATA
~
ADDRESS
I-
32AS
or AS
r~
- f-I. f-+
1
rr---,
f\
,..1-.1\
\
-~
35
\..r---'
~
RD/E/DS as E
If
\
12
~
12
35
~
,
1
-
/~
-
STABLE INPUT
\
J
-.. 34
RD/E/DS as OS
J
WRlVppor
RiWasRiW
X Xli XXXX
-..
00( ADROUl) HXXX
24
DATA IN
CSOi
23
ADROUT
f+-
-. 27 +DATA
~ OUT
...-...-.
28
.......
'IXJ-
29
----i
(14,17)
Notes for
Timing
Diagrams
.'ttIJ-KXX
-..
23 +-
r-
XX .XXXX
24
PAC-PA7
J
\
34
~
12. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19,
RD/E, WR or RNJ, transparent PCO-PC2, ALE in non-multiplexed modes.
13. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS):
AO/ADO-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PCO-PC2.
14. CSOi = ~ of the chip-select output signals coming through Port B (CSO-CS7) or through
Port C (CS8-CS10).
15. CSADOUT1, which internally enables the address transfer to Port A, should be derived only
from direct PAD input signals, otherwise the address propagation delay is slowed down.
16. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively,
can be derived from any combination of direct PAD inputs and multiplexed PAD inputs.
17. The write operation signals are included in the CSOi expression.
18. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in
the multiplexed modes: A11/AD11-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent
PCO-PC2.
19. CSOi product terms can include any of the PAD input signals except for reset and CSI.
May, 1993
106
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Pin
Capacltance2D
Symbol
FigureS.
AC 1BStIng
Input/Output
Waveform
Conditions Typical21 Max Unit
Parameter
CIN
Capacitance (for input pins only)
COUT
CvPp
Capacitance (for input/output pins)
NOTES:
PSD312
Capacitance (for WRlVpp or RIWNpp)
VIN = 0 V
4
6
pF
VOUT= 0 V
Vpp = 0 V
8
12
pF
18
25
pF
20. This paramter is only sampled and is not 100% tested.
21. Typical values are for TA = 25°C and nominal supply voltages.
3· 0 V
-V
---"
TEST POINT
-
v-:: v
~
0V
Figure 9.
AC 1BStIng
Load Circuit
2.01 V
...,...
~
~ 195Q
DEVICE
UNDER
TEST
~
I
_
Erasure and
Programming
To clear all locations of their programmed
contents, expose the device to ultra-violet
light source. A dosage of 15 W second/cm2
is required. This dosage can be obtained
with exposure to a wavelength of 2537 A
and intensity of 12000 J..lW/cm 2 for 15 to 20
minutes. The device should be about 1
inch from the source, and all filters should
be removed from the UV light source prior
to erasure.
The PSD3XX and similar devices will erase
with light sources having wavelengths
shorter than 4000 A. Although the erasure
times will be much longer than with UV
May, 1993
107
CL =30pF
(INCLUDING
SCOPEANDJIG
CAPACITANCE)
sources at 2537 A, exposure to fluorescent
light and sunlight eventually erases the
device. For maximum system reliability,
these sources should be avoided. If used in
such an environment, the package windows
should be covered by an opaque
substance.
Upon delivery, or after each erasure, the
PSD3XX device has all bits in the PAD and
EPROM in the "1" or high state. The configuration bits are in the "0" or low state.
The code, configuration, and PAD MAP
data are loaded through the procedure of
programming.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Pin
Assignments
Pin Name
44-Pin
PLCC/CLCC
Package
PSEN
WRNpporR/W
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
GND
ALE or AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
RD/E/DS
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
A8
A9
A10
GND
A11
A12
A13
A14
A15
PCO
PC1
PC2
A19/CSI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Vee
NOTE: 36. Pins 1,13,14,26,27,39,40, and 52 are No Connect.
May, 1993
108
PSD312
52-Pin
POFP Package
46
47
48
49
50
51
2
3
4
5
6
7
8
9
10
11
12
15
16
17
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
36
37
38
41
42
43
44
45
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD312
Package
Information
Figure 10.
DrawlngL444 Pin Ceramic
Leaded Chip
Carrier (CLCC)
with Window
(Package Type L)
uuuuuuuuuuu
PB4
7
PB3
8
38 A14
PB2
9
37 A13
o
PB1 10
PBO 11
GND 12
AlEorAS 13
PA714
PA6 15
39 A15
36 A12
35 A11
34 GND
33 A10
32 A9
31 A8
PA5 16
30 AD7/A7
PA4 17
29 AD6/A6
~
~
_
0
N
_
N
N
M
N
~
N
~
N
~
N
~
N
~
N
M
N
_
0
10
0
-
N
M
~
~
_
N
~ ~ ~ ~ ~ ~ § ~ ~ ~ ~
I~ ~ ~ ~ ~ ~ ~
(TOP VIEW)
Figure 11.
DrawlngJ244 Pin Plastic
Leaded Chip
Carrier (PLCC)
with Window
(Package Type J)
PB4
7
39 A15
PB3
8
39 A14
PB2
9
37 A13
PB1 10
36 A12
PBO 11
35 A11
GND 12
34 GND
33 A10
AlEorAS 13
PA714
32 A9
PA615
31 A8
PA516
30 AD7/A7
PA417
29 AD6/A6
~
~
_
0
N
_
N
N
N
M
N
~
N
~
N
~
N
~
N
~
N
M
N
_
0
10
0
-
N
M
~
~
_
(TOP VIEW)
May. 1993
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
I~~~~~~~
109
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Figure 12.
DrawlngQ252PlnPQFP
(Package Type QJ
I~
39 NC
NC
1
PB4
2
38 A15
PB3
3
37 A14
PB2
4
36 A13
PBl
5
35 A12
PBO
6
34 All
GND
7
33 GND
ALE or AS
8
32 Al0
PA7
9
31 A9
PA610
30 A8
PA5 11
29 AD7/A7
PA412
28 AD6/A6
27 NC
NC 13
(TOP VIEW)
May, 1993
PSD312
110
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
PSD312
Field-programmable microcontroller peripheral
Ordering
Information
May, 1993
Package Operating Manufacturing
Drawing Temperature
Procedure
Range
Spd.
(ns)
Package
Type
PSD312-90 A
90
44-pin PLCC
J2
Commercial
Standard
PSD312-90 KA
90
44-pin CLCC
L4
Commercial
PSD312-12 A
120
44-pin PLCC
J2
Commercial
Standard
Standard
PSD312-12 KA
120
44-pin CLCC
L4
Commercial
Standard
PSD312-12 B
120
52-pin POFP
02
Commercial
Standard
PSD312-15 A
150
44-pin PLCC
J2
Commercial
Standard
PSD312-151 A
150
44-pin PLCC
J2
Industrial
Standard
PSD312-15 KA
150
44-pin CLCC
L4
Commercial
Standard
PSD312-151 KA
150
44-pin CLCC
L4
Industrial
Standard
PSD312-15 B
150
52-pin POFP
02
Commercial
Standard
PSD312-151 B
150
52-pin POFP
02
Industrial
Standard
PSD312-20 A
PSD312-201 A
200
44-pin PLCC
J2
Commercial
Standard
200
44-pin PLCC
J2
Industrial
Standard
PSD312-20 KA
200
44-pin CLCC
L4
Commercial
Standard
PSD312-201 KA
200
44-pin CLCC
L4
Industrial
Standard
PSD312-20 B
200
52-pin POFP
02
Commercial
Standard
PSD312-201 B
200
52-pin POFP
02
Industrial
Standard
Part Number
111
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
May, 1993
112
PSD312
Philips Semiconductors Mlcrocontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Key Features
o
o
Single Chip Programmable Peripheral
for Microcontroller-based Applications
19 Individually Configurable I/O pins
that can be used as:
-
Microcontroller I/O port expansion
-
Programmable Address Decoder
(PAD) I/O
-
Latched address output
-
Open drain or CMOS
o
Two Programmable Arrays
(PAD A & PAD B)
-
Total of 40 Product Terms and up to
16 Inputs and 24 Outputs
-
Direct Address Decoding up to 1 Meg
address space and up to 16 Meg
with paging
-
Logic replacement
o
"No Glue" Microcontroller Chip-Set
-
Built-in address latches for multiplexed
address/data bus
-
Non-multiplexed address/data bus
mode
-
Selectable 8 or 16 bit data bus width
-
ALE and Reset polarity programmable
-
Selectable modes for read and write
control bus as ROIWR, R/W/E, or
RIW/OS
-
BHE pin for byte select in 16-bit mode
PSEN pin for 8051 users
o
May. 1993
Built-In Page Logic
-
To Expand the Address Space of
Microcontrollers with Limited Address
Space Capabilities
-
Up to 16 pages
113
PSD303
o
1 M bit of UV EPROM
-
Configurable as 128K x 8 or as 64K x 16
-
Divides into 8 equal mappable blocks
for optimized mapping
-
Block resolution is 16K x 8 or 8K x 16
-
120 ns EPROM access time, including
input latches and PAD address
decoding.
o
16 Kbit Static RAM
-
Configurable as 2K x 8 or as 1 K x 16
-
120 ns SRAM access time, including
input latches and PAD address
decoding
o
Address/Data Track Mode
-
Enables easy Interface to Shared
Resources (e.g., Mail Box SRAM) with
other Microcontrollers or a Host
Processor
o
Built-In Security
Locks the PSD303 and PAD Decoding
Configuration
-
o
Available in a Choice of Packages
-
44 Pin PLCC and CLCC
o
Simple Menu-Driven Software:
Configure the PS0303 on an IBM PC
o
Pin and Function Compatible with
the PSD301 and PS0302
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD303
Field-programmable microcontroller peripheral
Security
Mode
Security Mode in the PSD3XX locks the
contents of the PAD A , PAD B and all the
configuration bits. The EPROM, SRAM,
and 110 contents can be accessed only
through the PAD. The Security Mode can
be set by the MAPLE or Programming
software. In window packages, the mode is
erasable through UV full part erasure. In
the security mode, the PSD3XX contents
cannot be copied on a programmer.
CM/ser-Blt
The CMiser-Bit provides a programmable
option for power-sensitive applications that
require further reduction in power
consumption. The CMiser-Bit (CMiser = 1)
in the Maple portion of the PSD3XX sytem
development software can be used to
reduce power consumption. The CMiser-Bit
turns off the EPROM blocks in the PSD3XX
whenever the EPROM is not accessed,
thereby reducing the active current
consumed by the PSD3XX.
In the default mode, or if the PSD3XX is
configured without programming the
CMiser-Bit (CMiser = 0), the device
operates at specified speed and power
rating as specified in the A.C. and D.C.
Characteristics.
Absolute
Maximum
Ratlngs t
However, if the CMiser-Bit is programmed
(CMiser = 1), the device consumes even
lower current, and is reflected in the data
sheet. This mode has an adder in
propagation delay in T5, T6, and T7
parameters in the A.C. Characteristics, and
should be added to compute worst-case
timing requirements in the application.
Min
Max
Unit
CERDIP
-65
+ 150
°C
PLASTIC
-65
+ 125
°C
Voltage on any Pin
With Respect to GN D
-0.6
+7
V
Vpp
Programming
Supply Voltage
With Respect to GND
-0.6
+14
V
Vcc
Supply Voltage
With Respect to GND
-0.6
+7
V
>2000
V
Symbol
TSTG
Parameter
Condition
Storage Temperature
ESD Protection
NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.
Operating
Range
Recommended
Operating
Conditions
May, 1993
Range
Temperature
Vcc
Commercial
0° C to +70°C
+5V
Industrial
-40° C to +80°C
+5V
Military
-55° C to + 125°C
+5V
Symbol
Supply Voltage
V1H
High-level Input Voltage
VIL
Low-level Input Voltage
114
-12
-15
-20
± 10%
±10%
±10%
±10%
±10%
±10%
Conditions
Min
All Speeds
4.5
= 4.5 V to 5.5 V
Vcc = 4.5 V to 5.5 V
2
Parameter
vcc
Vcc Tolerance
V cc
0
Typ Max Unit
5
5.5
V
V
0.8
V
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
DC
Characteristics
Symbol
Parameter
Output Low
Voltage
VOL
Output High
Voltage
VOH
Vcc Standby
Current (CMOS)
(Notes 2 and 4)
ISB1
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
ICC1
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
ICC2
Active Current
(CMOS) (SRAM
Block Selected
(Notes 2 and 5)
ICC3
III
Input Leakage
Current
ILO
Output Leakage
Current
Conditions
PSD303
eMiser= 1
Subtract:
Min Typ Max Min T,P Max Unit
IOL = 20 JlA
Vcc = 4.5 V
0.01
0.1
V
IOL= 8 rnA
Vcc = 4.5 V
0.15
0.45
V
IOH = -20 JlA
Vcc=4.5V
4.4
4.49
V
IOH =-2 rnA
Vcc = 4.5 V
2.4
3.9
V
Cornrn'l
50
100
JlA
Ind/Mil
75
150
JlA
Cornrn'l
(Note 6)
16
35
7
10
rnA
Cornrn'l
(Note 7)
28
50
7
10
rnA
Ind/Mil
(Note 6)
16
45
7
10
rnA
Ind/Mil
(Note 7)
28
60
7
10
rnA
Cornrn'l
(Note 6)
16
35
0
0
rnA
Cornrn'l
(Note 7)
28
50
0
0
rnA
Ind/Mil
(Note 6)
16
45
0
0
rnA
Ind/Mil
(Note 7)
28
60
0
0
rnA
Comrn'l
(Note 6)
47
80
7
10
rnA
Cornrn'l
(Note 7)
59
95
7
10
rnA
Ind/Mil
(Note 6)
47
100
7
10
rnA
Ind/Mil
(Note 7)
59
115
7
10
rnA
-1
±0.1
1
JlA
-10
±5
10
JlA
VIN = 5.5 V
orGND
VOUT =5.5 V
orGND
CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
TIL inputs: V1L ~ 0.8 V, VIH ~ 2.0 V.
CSI/A19 is high and the part is in a power-down configuration mode.
Add 3.0 rnA/MHz for AC power component (power = AC + DC).
Ten (10) PAD product terms active. (Add 380 ~A per product term, typical, or 480 ~
per product term maximum
7. Forty-one (41) PAD product terms active.
NOTES: 2.
3.
4.
5.
6.
May, 1993
115
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD303
AC Characteristics
-90
Symbol
Parameter
T1
ALE or AS Pulse Width
-12
-20
-15
Min Max Min Max Min Max Min Max
20
30
40
eMiser= 1 Unit
Add:
50
0
ns
T2
Address Set-up Time
5
9
12
15
0
ns
T3
Address Hold Time
8
9
12
15
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
0
0
ns
T5
ALE Valid to Data Valid
100
130
160
200
10
ns
T6
Address Valid to Data Valid
90
120
150
200
10
ns
T7
CSI Active to Data Valid
100
130
160
200
15
ns
T8
Leading Edge of Read
to Data Valid
32
38
55
60
0
ns
T9
Read Data Hold Time
0
ns
T10
Trailing Edge of Read to
Data High-Z
0
ns
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
0
0
0
0
0
ns
RD, E, PSEN, or DS
Pulse Width
40
45
60
75
0
ns
T12
0
0
32
0
32
0
40
35
WR Pulse Width
20
25
35
45
0
ns
T13
Trailing Edge of Write or
Read to Leading Edge
of ALE or AS
0
0
0
0
0
ns
T14
Address Valid to Trailing
Edge of Write
90
120
150
200
0
ns
T15
CSI Active to Trailing Edge
of Write
100
130
160
200
0
ns
25
30
40
0
ns
5
10
15
0
ns
T12A
T16
Write Data Set-up Time
20
T17
Write Data Hold Time
5
T18
Port to Data Out Valid
Propagation Delay
T19
Port Input Hold Time
0
0
0
T20
Trailing Edge of Write
to Port Output Valid
40
40
50
T21
ADi or Control to CSOi
Valid
6
25
6
30
6
35
5
T22
ADi or Control to CSOi
Invalid
5
25
5
30
4
35
4
May, 1993
35
30
30
116
45
0
ns
0
0
ns
60
0
ns
45
0
ns
45
0
ns
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD303
AC Characteristics (Cont.)
-90
SymbDI
Parameter
-15
-12
-20
Min Max Min Max Min Max Min Max
eMiser= 1 Unit
Add:
T23
Track Mode Address
Propagation Delay:
CSADOUT1 Already True
22
22
28
28
0
ns
T23A
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes
True During ALE or AS
33
33
50
50
0
ns
T24
Track Mode Trailing Edge
of ALE or AS to Address
High-Z
32
32
35
40
0
ns
T25
Track Mode Read
Propagation Delay
29
29
35
35
0
ns
T26
Track Mode Read
Hold Time
35
0
ns
T27
Track Mode Write Cycle,
Data Propagation Delay
30
0
ns
T28
Track Mode Write
Cycle, Write to Data
Propagation Delay
8
55
0
ns
T29
Hold Time of Port A
Valid During Write
CSOi Trailing Edge
2
0
ns
T30
CSI Active to CSOi Active
9
40
9
45
9
50
8
60
0
ns
T31
CSI Inactive to CSOi
Inactive
9
40
9
45
9
50
8
60
0
ns
T32
Direct PAD Input as
Hold Time
10
10
12
15
0
ns
T33
R/W Active to E or DS Start
20
20
30
40
0
ns
T34
E or DS End to RIW
20
20
30
40
0
ns
T35
AS Inactive to E high
0
0
0
0
0
ns
T36
Address to Leading
Edge of Write
20
20
25
30
0
ns
11
29
11
10
20
20
30
29
8
30
2
29
10
30
7
40
2
7
2
NOTES: 8. AOi = any address line.
9. CSOi = any of the chip-select output signals com ing through Port B (CSO-CS7) or through Port C (CS8-CS 10).
10. Oirect PAO '!!!put = any of the following direct PAO input lines: CSI/A19 as transparent
A 19, ROlE/OS, WR or RIW, transparent PCO-PC2, ALE (or AS).
11. Control signals RO/E/OS or WR or RIW.
May, 1993
117
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD303
Figure 1.
TIming of 8-BIt
Multiplexed
AddfBSS/DataBus,
CRRWR=O
--
.....,
CSI/A19
asCSI
......
READ CYCLE
32
32-
4:,.
J~\
~
~XX
7
Direct (12)
PAD Input
......
WRITE CYCLE
....
~~
~
STABLE INPUT
6
32-
~
XXX
-
15
XXX XXX
STABLE INPUT
14
I
Multiplexed
Inputs
(13)
AO/ADOA7/AD7
IXXXXXXXJ. ~XXXX xxxxxx
-X~
-
~
10
6
3
~
,
DATA
IN
~--
~
3
16 -
1 I\.
~
--.
4
'---'
13
8
f--I
1/
17
h
Active High r~
ALE J. 1 ~
Active Low
ALE
ADDRESSB
2
-
IXXXX
14
~XX'J.. DATA VALID ~ r-"\
ADDRESSA J
2
~XXX
XX"-
l-t
J
r
rL
11
"
'--
Lr
12
RD/E/DS as RD
J
5
,
BHEIPSEN
asPSEN
,.
36
•
,
WRNppor
RWasWR
Anyo
f
PAO-PA7
as 1/0 Pin
18
X) XXXXXXXXX
I
Anyof \
PBO-PB7 Xl XXXXXXXX~
I
as 1/0 Pin
23
Any of
IPAO-PA7 Pins
as Address -----1\
Outputs
~
19
.--...
A
INPUT
)XXXXXXXXXXXXXXXX} XX
OUTPUT
INPUT
lXXXXXXXXXXXX~XXXXXX
OUTPUT
-"
23
ADDRESS A
~
See referenced notes on page 128.
MaY,1993
,13
12A
~
118
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD303
Figure 2.
Timing of B-Bit
Multiplexed
Address/DataBus,
CRRWR=1
CSIIA19
asCSI
-
--,
READ CYCLE
......
32
32- f+:.
1~~
\
I1XX XXX
15
7
Direct
PAD Input
Multiplexed
Inputs
(12)
(13)
] ~
-X\
6
14
XXXXXXXX XXXXX xxxxxx
6
ffix IXXXX
~
DATA VALID
3
XX) - \
-
2..
~
r ~ 1\
1
I~ ~
,
J
,
'(
~~
35
13
~
n1
I~
WRNppor
161-
.-..
J
1\
'(
35
~
34
~
34
j"""'-'
36
---
12
' ----.1
J
A
) XXXXXI
Rfij as Rfij
3
33
8
RD/E/DS as DS
r '" XXl
~ ,L
,
F
(
ADDRESS B
5
XXXXX
18
19
-
13
,--
}) XXXXXXXXX
INPUT
~
IXXXXXXXXXXXXXXXXXXX
OUTPUT
X) XXXXXXXXX
INPUT
IXXXXXXXXXXXXXXXXXXX
OUTPUT
Any of \
PAO-PA7
as 1/0 Pin
Any of
PBO-PB7 I
as 1/0 Pin
23
l-
---1
23
f+ADDRESS A
J
See referenced notes on page 128.
May. 1993
DATA
14
10
RD/E/DS as E
Any of
PAO-PA7 Pins
as Address
Outputs
IXXX ,XXX
STABLE INPUT
I
ADDRESSA J
2
Active Low
AS
32- I-
~~
STABLE INPUT
J,N
AO/ADOA7/AD7
Active High
AS
-.
WRITE CYCLE
--
119
ADDRESS B
Philips Semiconductors Microcontro\ler Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD303
Figure 3.
Timing of 16-BIt
Multiplexed
AddrBSS/DataBus,
CRRWR=O
-...
....,
CSI/A19
asCS I
..
.....
READ CYCLE
.--...
32
32-
J~~
~
(12
):x ~
15
~
STABLE INPUT
6
32-
~
(13
)X
~
.(XXX !XXXX
I'(XXXXXXX XXXXX XXXXXX
DATA
,
3
r~
I,.
,
~~
ADDRESSA J
2
Active Low
ALE
14
},N
-
AO/ADO
A15/AD15
Active High
ALE
XXX XIXXXX
10
-~\
-
14
IXXXXX.XXX OCXXXX XXXXXX
6
XXXX
XXX leXXX
STABLE INPUT
I
Multiplexed
Inputs
I-
~XX)
7
Direct
PAD Input
-..
WRITE CYCLE
.....
1
\
~
DATA VALID
4
J
~
8
,
ROlE/OS as RD
,-
ADDRESS B
2
~
..
\.~
-
1
--+
3
\
}- 1\". [/
XX
17
,.
f.-I
16iJ
,
11
.J
'-
13
5
,
12
J
36
-
r\..
Lr
''---.J
13
12A
+-+
WRNp~ 0 r
RiWasWR
18
~
19
~
Any 0 f \
PAO-PA7
as 1/0 Pin
,X) XXXXXXXXX
Any 0 f "PBO-PB7
I
as 1/0 Pin
X) XXXXXXXXX
INPUT
)XXXXXXXXXXXXXXXX XX
OUTPUT
INPUT
lIXXXXXXXXXXXXXXXXXXX
OUTPUT
23
23
Any of
PAO-PA7 Pin s
as Address
Outputs
~
---1\
ADDRESS A
J
See referenced notes on page 128.
May, 1993
120
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD303
Figure 4.
Timing 01 16·Blt
Multiplexed
AddreSS/DataBus,
CRRWR=1
CSI/A19
asCSI
-
...,
....
READ CYCLE
....
32
...
WRITE CYCLE
Multiplexed (13)
Inputs
~
~
~
STABLE INPUT
6
~~
Active High
AS
Active Low
AS
~.
14
IXXXX XXXX
10
~
{XX)(
ADDRESSA )
2
DATA VALID
~XXX XXX X
1\
1
)()O ~\
~
3
~~
'f
35
~
'I'
ROlE/OS as E
2
I
1 ~
..-+
'f
~
~
~
19
-
13
r-
A
XXXXXXXXX
INPUT
XXXXXXXXXXXXXXXX) XX
OUTPUT
X) XXXXXXXXX
INPUT
)(XXXXXXXXXXXXXXXXXXX
OUTPUT
I
23
l-
-
J
r--
IADDRESS A
J~
See referenced notes on page 128.
May, 1993
~
XXXXX
23
Any of
PAO-PA7 Pins
as Address
Outputs
36
12
~
18
Any of
PBO-PB7
as VO Pin
~ 34
,
J
X XXX XXX
Any of \
PAO-PA7 X)
I
as VO Pin
'--
33
34
rL
, Lr
35
12
ROlE/OS as OS
'(
161- ++1,-
~
-i
XX ~
/
17'
3
~
13
8
~(
ADDRESS B
5
WRNppor
-
14
DATA
IN
1f4- r--+
Rfjj as Rfjj
XXX lXXX
~
,(XXXXXXX XXXXX ~XXXX~
~h
,
I-
32STABLE INPUT
XXXXXXXX XXXXX ~XXXXX
-~~
-
XXXX
15
6
AO/ADOA151AD15
•
~XX)
A"~
~
7
Direct (12)
PAD Input
I+-
32-
In
121
ADDRESS B
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
PSD303
FIgure 5.
TImIng of '-Bit Data,
lion-Multiplexed
Address/DataBus,
CRRWR=O
CSI/A19
asCSI
--
.....,
.....
..
il\r\.
READ CYCLE
32
\
7
Direct (12)
PAD Input
~ 00\
WRITE CYCLE
32--..
Multiplexed
Inputs
(13)
PAO-PA7
~ 0\
STABLE INPUT
Active High
ALE
Active Low
ALE
~
~ 9\
STABLE INPUT
32--..
14
10
:~
DATA VALID
~h
2
~
,
h
8
13
,
,
12
~
X) .XXXXXXXXX
~
XXXXXXXXXXXXXXXX) XX
INPUT
See referenced notes on page 128.
May. 1993
13
~
~
19
18
I
~
~
,
5
RJWasWR
Any 0 f
PBO-PB7
as 1/0 Pin
"'-J
11
~
WR/Vpp or
,-
,
3'6
j
-
++I
~16
-
)(X~
17
~
4
'-~
'"
3
1 ~
1
I~ r-+
...
DATA
IN
"I:t...
~
3
XXX XXX
XXXX IXXXX
XXXXXXXX ~XXXX OCXXXXX
6
,
ROlE/OS as RD
XXX XXX
14
,.1
STABLE INPUT
-X
2
XXX
15
STABLE INPUT
~ 00
-'
...
~XX
6
AO/ADOA15/AD15
as AO-A15
... ..
122
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD303
Figure 6.
Timing of 8-BIt Data,
Non-Multiplexed
AddreSS/DataBus,
CRRWR=1
...
....
READ CYCLE
.....
32
--,
CSIIA19
asCS I
32 - .
.(xx XXX
7
-
AO/ADO
A15/AD15
as AO-A15
~
15
STABLE INPUT
6
Xl)
STABLE INPUT
~
Multiplexed
Inputs
)
(13
X~
Active Low
ALE
STABLE INPUT
~ 0(
STABLE INPUT
~
XXX
DATA VALID
l,- n
1 1\
Ir.- r-.
,
-
XXXX XXX X
2
3
~
~
I
1\
~
Lr
34
~
J
36
,
12
~
J
~
XXXXXX
X) XXXXXXXXX
\..
33
34
ROlE/OS as OS
,
,
13
12
13
I-
XXXXX
18
19
INPUT
I
See referenced notes on page 128.
May, 1993
/
35
,.4
35
5
Any of
PBO-PB7
as 110 Pi n
XX
~r
1611\
~
8
IX
DATA
IN
/
XX
J
ROlE/OS as E
WRNppor
Rfii as RfiJ
+
14
'(
~W
XXX XXX
32-.
~
3
,XXX XXX
14
10
--I
2
Active High
ALE
~ P<
XXXXXXXX lXXXX IXXXXXX
6
PAO-PA7
'4-
lX\
~
Direct (12
)~
PAD Input
.....
WRITE CYCLE
......
123
~
.JXXXXXXX XXXXXXXXXXXX
I(
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Figure 7.
Timing of 16-'1t
Non-Multiplexed
AddressJDataBus,
CRRWR=O
......,
CSI/A19
as CS I
-...
PSD303
..- ......
READ CYCLE
~
32
32-
/X\
~
>~ OCX
~~
STABLE INPUT
00
..-
~
>x
XXX XXX
STABLE INPUT
14
STABLE INPUT
Multiplexed (13
Inputs
~~
XXX XXX
STABLE INPUT
....
32-
IXXXXXXXX XXXXX OCXXXXX
XXXX XXXX
14
X~
DATA
IN
/
~
~m
PAO-PA7
(Low Byte).-J
~
~m
PBO-PB7
(High Byte) - '
2
DATA VALID
~
DATA VALID
XYJ
~
,
~
\.
2
16
3
Ie-
10
Active Low
ALE
,
1
4
,
8
~f.-I
~\
\.
~TA
11
36
,
WRNpp or
RiiJ asWR
~
See referenced notes on page 128.
124
13
12A
~
5
'r
~
~
~
~
j~
RD/E/DS as RD
-
IN
13
12
May, 1993
I-
h
r+
-
17
~
3
~
\.
r~
J..
-
i.(XXX XXXX
,(XXXXXXX XXXXX X.XXXXX
6
Active High
ALE
XXX
15
6
AO/ADO
A151AD15-~
as AO-A15
~
~XX
7
Direct (12
PAD Input
WRITE CYCLE
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
PSD303
Figure B.
Timing of 16-Blt
Non-Multiplexed
Address/DataBus,
CRRWR=1
--
READ CYCLE
~
--.
-
32
.......
CSI/A19
asCS I
1\
J~I\.
-
32-
AO/ADO
A15/AD15
as AO-A15
Multiplexed
Inputs
(13
~
15
STABLE INPUT
~ p(
STABLE INPUT
~~
STABLE INPUT
STABLE INPUT
~
> X~
XXX DeXXX
14
6
-x: KX;-
t-
VXX lXXXX
7
Direct (12
PAD Input >:x:
....
WRITE CYCLE
XXX X.XXX
32-
IXXXXXXXX OCXXXX XXXXXX
I+'-
IXXXX IXXXX
14
:x~
I'(XXXXXXX I)(XXXX XXXXXX
AXX
6
DATA
IN
.....,
/
PAO-PA7
(Low Byte )--1
~ro
....,
~XX)
2
Active Low
AS
DATA VALID
~
"
~
~
PBO-PB7
(High Byte )-J
Active High
AS
DATA VALID
.
3
Irh
v
1\
~
2
-
I--
/
I/XX~, -
~
1\
J/4 f-+
,
.
35
35
8
13
•
~ 1/
•
13
36
~J
~
rL
Lr
[\..
~
33
34
34
12
5
~
,
12
RDIE/DS as DS
'r
J
~
I~
RDIE/DS as E
1\
-J
X XXXXXX
I\--J
:XXXXX
See referenced notes on page 128.
May. 1993
16
.
3
h
1
I\-~
I/XX~
DATA
IN
10
'II
WRNppo r
RlWas RIW
XXXX~
125
V-
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD303
FigureS.
Chip-Select
Output TIming
30
31
CSI/A19
asCSi
Direct PAD (12)
Input
INPUT STABLE
Multiplexed (18)
PAD Inputs
3
ALE
(Multiplexed
Mode Only)
orALE
(Multiplexed
Mode Only)
21
CsOi (14,19)
See referenced notes on page 128.
May, 1993
126
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD303
Figure 10.
PortA
as ADO-AD7 Timing
(Track Mode),
CRRWR=O
..
READ CYCLE
.....
Direct
PAD Input
(12,15)
Multiplexed
PAD Inputs
(16,18)
~
.- .....
32 .....
STABLE INPUT
-J
2
XXX \ STABLE INPUT
2
AO/ADOA7/AD7
~
IXXXX X XXXXXXXX XXXX X
3
ADDRESS
~
m
J
tDATA VALID
I
OCXXXXXX
STABLE INPUT
~ }-\
If WRITIEN
DATA
~ 1\
ADDRESS
32
ALE
or ALE
r~
..:!-.
-,
32
..--...
4
\..~
,
12
f\.
\.
,
\.--J
.....
J
27 ~
\J
12A
11
,
WRlVppor
RiW'as WR
24
-
.....
00 ADROUTJ KXXX
J
24
DATA IN
XXX)- -00 ADROUT
.....
23 ~
CSOi
23
..--
{XX
~
DATA
OUT
~
'f
(14,17)
See referenced notes on page 128.
May, 1993
~
r~
1
- .J .. r--+
RDIE/DS as RD
PAO-PA7
X
3
2
26
~
rxxx
-
STABLE INPUT
I
2
.-
WRITE CYCLE
127
~
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD303
FlgurB 11. Port A as ADO-AD7 Timing
(Track ModB), CRRWR =1
..
Direct
PAD Input
(12.15)
Multiplexed
PAD Inputs
-
~
~
)(KX
STABLE INPUT
STABLE INPUT IXXXXXXXXXXXXX OCXXXXX
2
AO/ADOA7/AD7
32- I+-
3
ADDRESS
~
~
~
DATA VALID
)
'XXX
STABLE INPUT
~
I
2
.....
WRITE CYCLE
"
STABLE INPUT
(16.18)
.... .......
READ CYCLE
....
XXXXXXX
X
3
2
26
~~
ADDRESS
r-
I
'( WRITTEN
1\
DATA
I-
32-
rh
AS
_..J
or AS
-n
r~
J
1
~~
'(
35
~
ROlE/OS as E
V\.
~
"
1\
12
''''~
l.... ~
~
,
J
J
X Xl XXXX
-
~ ADR OUT) KXXX
...... 23
24
DATA IN
XXX}-
......
04-
roo
23
ADROUTJ
f+-
...
I
,----
XX} ,XXXX
34
24
... ...
27
{XX
DATA
OUT
~
'tI}-
29
...-..
L-...J
CSOi
(14.17)
NotBS for
Timing
Diagrams
\
...... 34
\
WRIVppor
RlWas Rfii
PAO-PA7
"
,
ROlE/OS as OS
\.J
12
35
12. Direct PAD input = any of the following direct PAD input lines: CSI/A 19 as transparent A 19,
RD/E, WR or Rfii, transparent PCO-PC2, ALE in non-multiplexed modes.
13. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS):
AO/ADD-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PCD-PC2.
14. CSOi = ~ of the chip-select output signals coming through Port B (CSO-CS7) or through
Port C (CS8-CS10).
15. CSADOUT1, which internally enables the address transfer to Port A, should be derived only
from direct PAD input signals, otherwise the address propagation delay is slowed down.
16. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively,
can be derived from any combination of direct PAD inputs and multiplexed PAD inputs.
17. The write operation signals are included in the CSOi expression.
18. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in
the multiplexed modes: A11/AD11-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent
PCO-PC2.
19. CSOi product terms can include any of the PAD input signals except for reset and CSI.
May. 1993
128
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Pin
Capacltance20
Conditions Typical21 Max Unit
4
Capacitance (for input pins only)
pF
6
VIN = 0 V
CIN
pF
8
12
VOUT = 0 V
COUT Capacitance (for input/output pins)
pF
18
25
CvPP Capacitance (for WR/vpp or RIWNpp) Vpp = 0 V
Symbol
NOTES:
Figure 12.
AC Testing
Input/Output
Waveform
PSD303
Parameter
20. This paramter is only sampled and is not 100% tested.
21. Typical values are for T A = 25°C and nominal supply voltages.
3· 0 V
-V
--"
TEST POINT -
v-:: v
~
0V
Figure 13.
AC Testing
Load Circuit
2.01 V
....,..
~
~ 1950
DEVICE
UNDER
TEST
Erasure and
Programming
To clear all locations of their programmed
contents, expose the device to ultra-violet
light source. A dosage of 15 W second/cm 2
is required. This dosage can be obtained
with exposure to a wavelength of 2537 A
and intensity of 12000 J.lW/cm 2 for 15 to 20
minutes. The device should be about 1
inch from the source, and all filters should
be removed from the UV light source prior
to erasure.
The PSD3XX and similar devices will erase
with light sources having wavelengths
shorter than 4000 A. Although the erasure
times will be much longer than with UV
May, 1993
129
I
- - CL =30pF
(INCLUDING
_ SCOPE AND JIG
CAPACITANCE)
sources at 2537 A, exposure to fluorescent
light and su nlight eventually erases the
device. For maximum system reliability,
these sources should be avoided. If used in
such an environment, the package windows
should be covered by an opaque
substance.
Upon delivery from WSI, or after each
erasure, the PSD3XX device has all bits in
the PAD and EPROM in the "1" or high
state. The configuration bits are in the "0" or
low state. The code, configuration, and
PAD MAP data are loaded through the
procedure of programming.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Pin
Assignments
Pin Name
44-Pin
PLCC/CLCC
Package
BHEIPSEN
WRlVpp or R/W
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
GND
ALE or AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
RD/EIDS
ADO/AO
AD1/A1
AD2IA2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD10/A10
GND
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
PCO
PC1
PC2
A19/CSI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Vee
May, 1993
130
PSD303
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD303
Package
Information
Figure 1.
DrawlngL444 Pin Ceramic
Leaded Chip
Carrier (CLCC)
with Window
(Package rype L)
PB4
7
PB3
8
39 AD15/A15
38 AD/14/A14
PB2
9
37 AD13/A13
o
PB1 10
PBO 11
GND 12
ALE or AS 13
PA714
PA6 15
36 AD121A12
35 AD11/A11
34 GND
33 AD10/A10
32 AD9/A9
31 AD8/A8
PAS 16
30 AD7/A7
PA4 17
29 AD6/A6
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
M
N
~
0
I~
0
~
N
M
~
~
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
I~ 5i! 5i! 5i! 5i! 5i! 5i!
(TOP VIEW)
Figure 2.
DrawingJ244 Pin Plastic
Leaded Chip
Carrier (PLCC)
with Window
(Package rype J)
PB4
7
39 AD15/A15
PB3
8
39 AD14/A14
PB2
9
37 AD13/A13
PB1 10
36 AD121A12
35 AD11/A11
PBO 11
34 GND
GND 12
33 AD10/A10
ALE or AS 13
32 AD9/A9
PA714
(TOP VIEW)
May, 1993
PA615
31 AD8/A8
PAS 16
30 AD7/A7
PA417
29 AD6/A6
~
~
Q
_
0
N
N
N
N
M
N
~
N
~
N
~
N
~
N
~
N
M
N
~
0
I~
0
~
N
M
~
~
~~~~~~~~~~~
I~~~~~~~
131
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Ordering
Information
WSI
Package Operating
Temperature
Manufacturing
Drawing
Range
Procedure
Part Number
Spd.
(ns)
Package
Type
PSD303-90 A
90
44-pin PLCC
J2
Commercial
PSD303-90 KA
90
120
44-pin CLCC
44-pin PLCC
L4
Commercial
Standard
J2
Commercial
Standard
PSD303-12 KA
120
44-pin CLCC
L4
Commercial
Standard
PSD303-15 A
150
44-pin PLCC
J2
Commercial
Standard
PSD303-151 A
150
44-pin PLCC
J2
Industrial
Standard
PSD303-15KA
150
44-pin CLCC
L4
Commercial
Standard
PSD303-151 KA
150
44-pin CLCC
L4
Industrial
Standard
PSD303-20 A
200
44-pin PLCC
J2
Commercial
Standard
PSD303-201 A
200
44-pin PLCC
J2
Industrial
Standard
PSD303-20 KA
200
44-pin CLCC
L4
Commercial
Standard
PSD303-201 KA
200
44-pin CLCC
L4
Industrial
Standard
PSD303-12 A
May. 1993
PSD303
132
Standard
Preliminary specification
Philips Semiconductors Mlcrocontroller Peripherals
Field-programmable microcontroller peripheral
Key Features
o
o
19 Individually Configurable I/O pins
that can be used as:
-
Microcontroller I/O port expansion
-
Programmable Address Decoder
(PAD) I/O
-
Latched address output
-
Open drain or CMOS
o
Two Programmable Arrays
(PAD A & PAD B)
-
Total of 40 Product Terms and up to
16 Inputs and 24 Outputs
-
Direct Address Decoding up to 1 Meg
address space and up to 16 Meg
with paging
-
Logic replacement
o
"No Glue" Microcontroller Chip-Set
-
Built-in address latches for multiplexed
address/data bus
-
Non-multiplexed address/data bus
mode
-
8-bit data bus width
-
ALE and Reset polarity programmable
-
Selectable modes for read and write
control bus as RD/WR, R/W/E, or
R/W/DS
-
PSEN pin for 8051 users
o
May. 1993
Single Chip Programmable Peripheral
for Microcontroller-based Applications
o
1 M bit of UV EPROM
-
Configurable as 128K x 8
-
Divides into 8 equal mappable blocks
for optimized mapping
-
Block resolution is 16K x 8
-
120 ns EPROM access time, including
input latches and PAD address
decoding.
o
16 Kbit Static RAM
-
Configurable as 2K x 8
-
120 ns SRAM access time, including
input latches and PAD address
decoding
o
Address/Data Track Mode
-
Enables easy Interface to Shared
Resources (e.g., Mail Box SRAM) with
other Microcontrollers or a Host
Processor
o
Built-In Security
Locks the PSD313 and PAD Decoding
Configuration
-
o
Available in a Choice of Packages
-
44 Pin PLDCC and CLDCC
o
o
Built-In Page Logic
-
To Expand the Address Space of
Microcontrollers with Limited Address
Space Capabilities
-
Up to 16 pages
133
PSD313
Simple Menu-Driven Software:
Configure the PSD313 on an IBM PC
Pin Compatible with the PSD311 and
PSD312
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontroller peripheral
PSD313
Security
Mode
Security Mode in the PSD3XX locks the
contents of the PAD A, PAD B and all the
configuration bits. The EPROM, SRAM,
and 1/0 contents can be accessed only
through the PAD. The Security Mode can
be set by the MAPLE or Programming
software. In window packages, the mode is
erasable through UV full part erasure. In
the security mode, the PS03XX contents
cannot be copied on a programmer.
CMlser-Blt
The CMiser-Bit provides a programmable
option for power-sensitive applications that
require further reduction in power
consumption. The CMiser-Bit (CMiser = 1)
in the Maple portion of the PSD3XX sytem
development.software can be used to
reduce power consumption. The CMiser-Bit
turns off the EPROM blocks in the PS03XX
whenever the EPROM is not accessed,
thereby reducing the active current
consumed by the PS03XX.
In the default mode, or if the PS03XX is
configured without programming the
CMiser-Bit (CMiser = 0), the device
operates at specified speed and power
rating as specified in the A.C. and D.C.
Characteristics.
Absolute
Maximum
Rat/ngst
Parameter
Symbol
TSTG
However, if the CMiser-Bit is programmed
(CMiser = 1), the device consumes even
lower current, and is reflected in the data
sheet. This mode has an adder in
propagation delay in T5, T6, and T7
parameters in the A.C. Characteristics, and
should be added to compute worst-case
timing requirements in the application.
Condition
Storage Temperature
CERDIP
Min
Max
Unit
-65
+ 150
°C
PLASTIC
-65
+ 125
°C
Voltage on any Pin
With Respect to GND
-0.6
+7
V
Vpp
Programming
Supply Voltage
With Respect to GNO
-0.6
+14
V
Vcc
Supply Voltage
With Respect to GNO
-0.6
+7
V
>2000
V
ESO Protection
NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
theses or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.
Operating
Range
Range
Temperature
Vee
Commercial
0° Cto +70°C
+5V
-400 C to +80°C
+5V
Industrial
Military
Recommended
Operating
Conditions
May. 1993
Symbol
-55° C to + 125°C
Parameter
Vee Tolerance
-12
-15
-20
±10%
±10%
±10%
±10%
+5V
Conditions
Min
Vcc
Supply Voltage
All Speeds
4.5
VIH
High-level Input Voltage
Vcc=4.5Vt05.5V
2
V1L
Low-level Input Voltage
Vee = 4.5 V to 5.5 V
0
134
±10%
±10%
Typ Max Unit
5
5.5
V
V
0.8
V
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
DC
Characteristics
Symbol
Parameter
Output Low
Voltage
VOL
Output High
Voltage
VOH
Vcc Standby
Current (CMOS)
(Notes 2 and 4)
1581
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
ICC1
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
ICC2
Active Current
(CMOS) (SRAM
Block Selected
(Notes 2and 5)
ICC3
Conditions
PSD313
CMiser= 1
Subtract:
Min Typ Max Min Typ Max Unit
IOL = 20 J,JA
Vcc = 4.5 V
0.01
0.1
V
IOL=8 rnA
Vcc = 4.5 V
0.15
0.45
V
IOH = -20 J,JA
Vcc = 4.5 V
4.4
4.49
V
IOH =-2 rnA
Vcc = 4.5 V
2.4
3.9
V
Comm'l
50
100
J,JA
J,JA
Ind/Mil
75
150
Comm'l
(Note 6)
16
35
7
10
rnA
Comm'l
(Note 7)
28
50
7
10
rnA
Ind/Mil
(Note 6)
16
45
7
10
rnA
Ind/Mil
(Note 7)
28
60
7
10
rnA
Comrn'l
(Note 6)
16
35
0
0
rnA
Cornm'l
(Note 7)
28
50
0
0
rnA
IndlMil
(Note 6)
16
45
0
0
rnA
Ind/Mil
(Note 7)
28
60
0
0
rnA
Cornrn'l
(Note 6)
47
80
7
10
rnA
Comm'l
(Note 7)
59
95
7
10
rnA
Ind/Mil
(Note 6)
47
100
7
10
rnA
Ind/Mil
(Note 7)
59
115
7
10
rnA
III
Input Leakage
Current
VIN = 5.5 V
orGND
-1
±0.1
1
J,JA
ILO
Output Leakage
Current
VOUT =5.5 V
orGND
-10
±5
10
J,JA
NOTES: 2.
3.
4.
5.
6.
CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
TTL inputs: VIL ~ 0.8 V, VIH ~ 2.0 V.
CSI/A19 is high and the part is in a power-down configuration mode.
Add 3.0 rnA/MHz for AC power component (power = AC + DC).
Ten (10) PAD product terms active. (Add 380 IlA per product term, typical, or 480 IlA
per product term maximum
7. Forty-one (41) PAD product terms active.
May, 1993
135
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD313
AC Character/sties
-90
Symbol
Parameter
-12
-15
-20
eMiser= 1 Unit
Add:
Min Max Min Max Min Max Min Max
T1
ALE or AS Pulse Width
20
30
40
50
0
ns
T2
Address Set-up Time
5
9
12
15
0
ns
T3
Address Hold Time
8
9
12
15
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
0
0
ns
T5
ALE Valid to Data Valid
100
130
160
200
10
ns
T6
Address Valid to Data Valid
90
120
150
200
10
ns
T7
CSI Active to Data Valid
100
130
160
200
15
ns
T8
Leading Edge of Read
to Data Valid
32
38
55
60
0
ns
T9
Read Data Hold Time
0
ns
T10
Trailing Edge of Read to
Data High-Z
0
ns
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
0
0
0
0
0
ns
RD, E, PSEN, or DS
Pulse Width
40
45
60
75
0
ns
WR Pulse Width
20
25
35
45
0
ns
T13
Trailing Edge of Write or
Read to Leading Edge
of ALE or AS
0
0
0
0
0
ns
T14
Address Valid to Trailing
Edge of Write
90
120
150
200
0
ns
T15
CSI Active to Trailing Edge
of Write
100
130
160
200
0
ns
T16
Write Data Set-up Time
20
25
30
40
0
ns
T17
Write Data Hold Time
5
5
10
15
0
ns
T18
Port to Data Out Valid
Propagation Delay
T12
T12A
0
0
32
0
32
30
0
40
35
30
45
35
0
ns
T19
Port Input Hold Time
0
0
0
0
0
ns
T20
Trailing Edge of Write
to Port Output Valid
40
40
50
60
0
ns
T21
ADi or Control to CSOi
Valid
6
25
6
30
6
35
5
45
0
ns
T22
ADi or Control to CSOi
Invalid
5
25
5
30
4
35
4
45
0
ns
May, 1993
136
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD313
AC Characteristics (Cont.)
-90
Symbol
Parameter
-12
-20
-15
Min Max Min Max Min Max Min Max
eMiser= 1 Unit
Add:
Track Mode Address
Propagation Delay:
CSADOUT1 Already True
22
22
28
28
0
ns
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes
True During ALE or AS
33
33
50
50
0
ns
T24
Track Mode Trailing Edge
of ALE or AS to Address
High-Z
32
32
35
40
0
ns
T25
Track Mode Read
Propagation Delay
29
29
35
35
0
ns
T26
Track Mode Read
Hold Time
35
0
ns
T27
Track Mode Write Cycle,
Data Propagation Delay
30
0
ns
T28
Track Mode Write
Cycle, Write to Data
Propagation Delay
8
55
0
ns
T29
Hold Time of Port A
Valid During Write
CSOi Trailing Edge
2
0
ns
T30
CSI Active to CSOi Active
9
40
9
45
9
50
8
60
0
ns
T31
CSI Inactive to CSOi
Inactive
9
40
9
45
9
50
8
60
0
ns
T32
Direct PAD Input as
Hold Time
10
T33
R/W Active to E or DS Start
20
T34
E or DS End to RIW
20
T35
AS Inactive to E high
0
T36
Address to Leading
Edge of Write
20
T23
T23A
11
29
11
20
30
29
10
20
8
30
2
29
30
7
40
2
10
10
7
2
12
15
0
ns
20
30
40
0
ns
20
30
40
0
ns
0
0
0
0
ns
20
25
30
0
ns
NOTES: B. AOi = any address line.
9. CSOi = any of the chip-select output signals coming through Port 8 (CSO-CS7) or
through Port C (CSB-CS1 0).
10. Direct PAD'!!!put = any outJe following direct PAD input lines: CSI/A 19 as transparent
A19, ROlE/OS, WR or RIW, transparent PCO-PC2, ALE (or AS).
11. Control signals RO/E/OS or WR or RIW.
May, 1993
137
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD313
Figure 1.
Timing of B-BIt
Multiplexed
Address/DataBus,
CRRWR=O
..
...,
CSI/A19
asCSI
..... "'"..
READ CYCLE
"'"
,-
32
32-
Multiplexed
Inputs
(13)
~
'(XX XXX
00f
6
X;\.
2
Active Low
ALE
•
'r h
,
14
:ro
3
~
•
1
r--.
~
4
j\.. ~
,
5
161~
:x:
~r
11
~
13
8
RD/E/DS as RD
~~ /
3
h
1
BHEIPSEN
as PSEN
-
ADDRESS B
2
-
DATA
IN
14
XX ....
DATA VALID
•
OCXXX XXXX
10
ADDRESS A
XXX XXX
STABLE INPUT
iXXXXXXXX ~XXXX XXXXXX
A7/AD7
I~
32-
~ 0(
I.
STABLE INPUT
AD/ADO-
-
15
6
Active High
ALE
~
AX\
'7
Direct (12)
PAD Input
.....
WRITE CYCLE
~
rL
Lr
12
J
,
'f
36
J
12A
,~
WRNppor
RWasWR
18
13
f-I{
I\----J
19
Any of \
PAO-PA7 I X)
as 1/0 Pin
XXXXXXXXX
INPUT
~
XXXXXXXXXXXXXXXX) XX
OUTPUT
Any 0
f ~)
PBO-PB7
I
as 1/0 Pin
XXXXXXXXX
INPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
~
Any of
PAO-PA7 Pins
as Address
Outputs
-=
-
23
23
JI\
~
ADDRESS A
~
See referenced notes on page 144.
May, 1993
138
ADDRESS B
£
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
PSD313
Figure 2.
Timing of '-Bit
Multiplexed
Address/DataBus,
CRRWR=1
...
CSIIA19
asCSI
....,
.....
READ CYCLE
--
32
..
32-
J~\
\
Multiplexed
Inputs
(12)
(13)
~ 00\
I.
6
Active Low
AS
•
r~
1
I~ -+
~
3
DATA VALID
J
,
35
13
-
Any of
PBO-PB7
as 1/0 Pin
Any of
PAC-PA7 Pins
as Address
Outputs
I
X) XXXXXXXXX
19
,-
A
lXXXXXXXXXXXXXXXXXXX
OUTPUT
INPUT
IX XXXXXXXXX XXX XXXXXX
OUTPUT
23
----11\
~
INPUT
23
r--ADDRESS A
J
See referenced notes on page 144.
May, 1993
~
XXXXX
I'f
rL
Lr
,
12
\
\
\..
34
-
I~
36
) XXX XXX
}J XXXXXXXXX
,
35
-'
r+-+
18
Any of
PAC-PA7
as 1/0 Pin
J
-J
~
)OC~
~ r-
t-+
34
"
12
~
1/
161-
~
1 ~
5
RD/E/DS as DS
>-
3
-
J,N
f
1\
33
8
RD/E/DS as E
DATA
ADDRESS B
2
1\
..J
xxxx IXXXX
~ -'--
~
~
~
WRNppor
RfiJ as RfiJ
•
14
,
1\
14
10
ADDRESS A
XXX XXX
STABLE INPUT
XXXXXXXX XXXXX rxxxxxx
2
Active High
AS
32-
~ 0(
STABLE INPUT
6
AO/ADOA7/AD7
-
15
I
-X
~
'(XX XXX
7
Direct
PAD Input
......
WRITE CYCLE
--
139
ADDRESSB
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
Field-programmable microcontrolier peripheral
PSD313
Figure 3.
TIming of B-BIt Data,
Non-Multiplexed
AddrBSS/DataBus,
CRRWR=O
-
......
CSI/A19
asCS I
....
READ CYCLE
....
-
32
-
32--.
~ 00\
15
STABLE INPUT
~~
STABLE INPUT
~ 00
STABLE INPUT
~~
STABLE INPUT
~
»)C
Multiplexed (13
Inputs
PAO-PA7
2
Active High
ALE
Active Low
ALE
m
-;
--1
3
DATA VALID
1
I~ r--+
2
3
14-.
h
~~
,
8
13
,
~
'(
~
~
11
~
12
I(
36
J
13
,
12A
14--+
WRNpp or
RtWasWR
""'-
5
X) XXXXXXXXX
I
~
XXXXXXXXXXXXXXXXXXX
INPUT
See referenced notes on page 144.
May, 1993
r-+
~
19
18
Any 0 f
PBO-PB7
as 1/0 Pin
'~" )OC~
,rL
,
Lr
-'16 +-J
1 ~
,
ROlE/OS as RD
J.N
1\
1\
4
-
DATA
'tIJ
~
rr---,
....
IXXXX XXXX
14
10
6
XXX XXX
32--.
XXXXXXXX XXXXX XXXXXX
-
XXX ,XXX
14
6
AO/ADOA15/AD15
as AO-A15
.... ..
I.0- [>0[>0-
RESET ...
A
CS3IPB3
-...
.
PAD
---
-....
-...;:::
....
A12
CSADOUT1 }
CSADOUT2
-
""'S
A14
CSIOPORT CSAOIN
- ...-
""S
"S
A15
8 EPROM BLOCK
S ELECT LINES
~~J_sRAM BLOCK SELECT
~
...
>
ESS
ES6
..
-
~
A19
ES3
ES4
.....
"S
orRiW
ES1
ES2
;:::
,..
~
....
OorE
:.
..
-..
-
"S
...
ESO"
-
,..
...
-
B
CS8IPCO
CS9IPC1
CSiliIPC2
NOTES: 4. eSI is a power-down signal. When high, the PAD is in stand-by mode and all its outputs
become non-active. See Tables 12 and 13.
5. RESET deselects all PAD output signals. See Tables 10 and 11.
6. A18, A17, and A16 are internally multiplexed with eS10, eS9, and eS8, respectively.
Either A 18 or es 10, A 17 or eS9, and A 16 or eS8 can be routed to the external pins of
Port e. Port e can be configured as either input or output.
7. PO-P3 are not included on PSD3X1 L devices.
May, 1993
161
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
Tab/e3.
PSD3XXL PAD A
andPADB
Functions
Function
PAD A and PAD B Inputs
A19/CSI
In CSI mode (when high), PAD deselects all of its outputs and enters a
power-down mode (see Tables 12 and 13). In A19 mode, it is another
input to the PAD.
A16-A18
These are general purpose inputs from Port C. See Figure 3, Note 4.
A11-A15
These are address inputs.
PO-P3
These are page number inputs (for the PSD302L1312L1303L1313L only).
RDorE
This is the read pulse or enable strobe input.
WR or RIW
ALE
RESET
This is the write pulse or RIW select signal.
This is the ALE input to the Chip.
This deselects all outputs from the PAD; it can not be used in product
term equations. See Tables 10 and 11.
PAD A Outputs
ESO-ES7
These are internal chip-selects to the 8 EPROM banks. Each bank can
be located on any boundary that is a function of one product term of the
PAD address inputs.
RSO
This is an internal chip-select to the SRAM. Its base address location is
a function of one term of the PAD address inputs.
CSIOPORT
This internal chip-select selects the I/O ports. It can be placed on any
boundary that is a function of one product term of the PAD inputs. See
Tables 6 and 7.
CSADIN
This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the input
direction of Port A. CSADIN is gated externally to the PAD by the
internal read signal. When CSADIN and a read operation are active, data
presented on Port A flows out of ADO/AO-AD7/A7. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure 5.
CSADOUT1
This internal chip-select, when Port A is configured as a low-order
address/data bus in track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT1 is gated externally to the PAD by the ALE
signal. When CSADOUT1 and the ALE signal are active, the address
presented on ADO/AQ-AD7/A7 flows out of Port A. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure 5.
CSADOUT2
This internal chip-select, when Port A is configured as a low-order
address/data bus in the track mode (CPAF2 = 1), controls the output
direction of Port A. CSADOUT2 must include the write-cycle control
signals as part of its product term. When CSADOUT2 is active, the data
presented on ADO/AO-AD7/A7 flows out of Port A. This chip-select can
be placed on any boundary that is a function of one product term of the
PAD inputs. See Figure 5.
PAD B Outputs
MaY,1993
CSO-CS3
These chip-select outputs can be routed through Port B. Each of them is
a function of up to four product terms of the PAD inputs.
CS4-CS7
These chip-select outputs can be routed through Port B. Each of them is
a function of up to two product terms of the PAD inputs.
CS8-CS10
These chip-select outputs can be routed through Port C. See Figure 3,
Note 4. Each of them is a function of one product term of the PAD inputs.
162
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
CooflguratloR
Bits
Table 4.
PSD3XXL
NOR- Volatile
CORflguratloR
Bits
The configuration bits shown in Table 4 are
non-volatile cells that let the user set the
device, I/O, and control functions to the
proper operational mode. Table 5 lists all
configuration bits. The configuration bits
are programmed and verified during the
Use This Bit
CDATA
CADDRDAT
CEDS
CA19/CSI
PSD3XXL Family
programming phase. In operational mode,
they are not accessible. To simplify
implementing a specific mode, use the
PSD3XXL MAPLE software to set the bits.
To
Set the data bus width to 8 or 16 bits (PSD30XL only).
Set the address/data buses to multiplexed or non-multiplexed mode.
Determine the polarity and functionality of read and write. (Note 9)
Set A 19/CSI to CSI (power-down) or A 19 input.
CALE
Set the ALE polarity.
CPAF2
Set Port A either to track the low-order byte of the address/data
multiplexed bus or to select the I/O or address option.
CSECURITY
Set the security on or off (a secured part can not be duplicated).
COMB/SEP
Set PSEN and RD for combined or separate address spaces
(see Figures 9 and 10).
CPAF1
(8 Bits)
Configure each pin of Port A in multiplexed mode to be an I/O or
address out.
CPACOD
(8 Bits)
Configure each pin of Port A as an open drain or active CMOS
pull-up output.
CPBF
(8 Bits)
Configure each pin of Port B as an I/O or a chip-select output'
CPBCOD
(8 Bits)
Configure each pin of Port B as an open drain or active CMOS
pull-up output.
CPCF
(3 Bits)
Configure each pin of Port C as an address input or a chip-select output.
CADDHLT
Configure pins A 16 - A 19 to go through a latch or to have their
latch transparent.
CADLOG
(4 Bits)
Configure A16 - A19 individually as logic or address inputs.
(Note 9)
CATD
Configure pins A 16-A19 as PAD logic inputs or high-order address
inputs (Note 8).
CLOT
Determine in non-multiplexed mode if address inputs are transparent
or latched (Note 9).
CRRWR
Set the RD/E and WR/vpp or R/W pins to RD and WR pulse, or to E
strobe and R/W status (Note 8).
CRRWR
Configure the polarity and control methods of read and write cycles.
(Note 9)
CMISER
Controls the lower-power mode.
NOTES: 8. PSD31XL only.
9. PSD302U312U303U313L only.
Port FURCtioRS
May. 1993
The PSD3XXL has three I/O ports (Ports A,
B, and C) that are configurable at the bit
level. This permits great flexibility and a
high degree of customization for specific
163
applications. The following is a description
of each port. Figure 4 shows the pin
structure of Port A.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
Figure 4.
PortA Pin
Structure
I
N
T
E
R
N
A
L
READ PIN
~.
READ DATA
CMOSIOO(10)
---J
our
WRITE DATA CK
A
0
0
R
I
0
A
T
A
OFF
DR
OJ ENABLE
I
ALE
PORTA PIN
ADOR ..
G
MUX
LATCH
0
R
AOIIOI ..
B
U
S
~
REAOOIR
A
0
0
I
A
0
7
WRITEOIR
DDI~
~
CONTROL
CK FF
R
I
I
RESET
NOTE: 10. CMOS/OD determines whether the output is open drain or CMOS.
Figure 5.
PortA Track
Mode
WRorRiW
~I
CSAOIN
ROlE
ADO-A07
INTERNAL
ALE
ALE or AS
..
AD8-A015
~-
~
LATCH A11-A15
PAD
CSADOUT2 (11)
A16-A19
NOTE: 11. The expression for CSADOUT2 must include the following write operation cycle signals:
For CRRWR = 0, CSADOUT2 must include WR = O.
For CRRWR = 1, CSADOUT2 must include E = 1 and RiW = o.
May, 1993
164
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
TableS.
PSD3XXL
Configuration
811s 12,13
Configuration
No.
of Bits
Bits
°
CDATA
(Note 14)
1
a-bit or 16-bit Data Bus Width
CDATA = eight bits
CDATA = 1 sixteen bits
CADDRDAT
1
ADDRESS/DATA Multiplexed (separate buses)
CADDRDAT = 0, non-multiplexed
CADDRDAT = 1, multiplexed
CA19/CSI
1
A19 or CSI
CA19/CSI = 0, enable power-down
CA 19/CSI = 1, enable A 19 input to PAD
CALE
1
Active HIGH or Active LOW
CALE = 0, Active high
CALE = 1, Active low
COMB/SEP
1
Combined or Separate Address Space
for SRAM and EPROM
= Combined, 1 = Separate
CPAF1
a
Port A I/Os or AO-A7
CPAF1 = 0, Port A pin
CPAF1 = 1, Port A pin
CPAF2
1
Port A ADO-AD7 (address/data multiplexed bus)
CPAF2 = 0, address or I/O on Port A (according to CPAF1)
CPAF2 = 1, address/data multiplexed on Port A (track mode)
CATD
(Note 16)
1
A 16-A19 address or logic inputs
CATD = 0, logic inputs
CATD = 1, address inputs
CADDHLT
1
A 16-A19 Transparent or Latched
CADDHLT = 0, Address latch transparent
CADDHLT = 1, Address latched (ALE dependent)
CSECURITY
1
SECURITY On/Off
CSECURITY = 0, off
CSECURITY = 1, on
1
AO-A15 Address Inputs are transparent or
ALE-dependent in non-multiplexed modes
CLOT = 0, transparent
CLOT = 1, ALE-dependent
CRRWR
CEDS
(Note 15)
2
Determine the polarity and control methods of read and
write cycles.
CEDS
CRRWR
RD and WR active low pulses
1
RIW status and high E pulse
1
1
RIW status and low OS pulse
CRRWR
(Note 16)
1
CRRWR
CRRWR
CPACOD
a
Port A CMOS or Open Drain Output
CPACOD = 0, CMOS output
CPACOD = 1, open-drain output
CLOT
(Note 15)
CPBF
May, 1993
Function
a
°
°°
= I/O
= AO -
A7
°
= 0, RD and WR active low strobes
= 1, R/W status and E active high pulse
Port B is I/O or CSO- CS7
CPBF = 0, Port B pin is CSO - CS7
CPBF = 1, Port B pin is I/O
165
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
Table 5.
PSD3XXL
Configuration
Bits (Cont.)
Configuration
Bits
No.
of Bits
CPBCOD
8
Port B CMOS or Open Drain
CPBCOD = 0, CMOS output
CPBCOD = 1, open-drain output
CPCF
3
Port C A16-A18 or CS8-CS10
CPCF = 0, Port C pin is A16-A18
CPCF = 1, Port C pin is CS8-CS10
CADLOG
(Note 15)
4
CMISER
NOTES: 12.
13.
14.
15.
16.
Port Functions
(Cont.)
Function
1
Port C: A16-A19 Address or L09!£Jnput
CADLOG = 0, Port C pin or A19/CSI is logic input
CADLOG = 1, Port C pin or A 19/CSI is address input
Default: CMISER = 0
CMISER = 1, lower-power mode
WSI's Maple software will guide the user to the proper configuration choice.
In an unprogrammed or erased part, all configuration bits are o.
PSD30XL only.
PSD3X2L13X3L only.
PSD3X1 L only.
Port A in Multiplexed
Address/Data Mode
The default configuration of Port A is I/O. In
this mode, every pin can be set as an input
or output by writing into the respective pin's
direction flip flop (DIR FF, in Figure 4). As
an output, the pin level can be controlled by
writing into the respective pin's data flip flop
(DFF, in Figure 4). When DIR FF = 1, the
pin is configured as an output. When DIR
FF = 0, the pin is configured as an input.
The controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the DFF bits by accessing the READ
DATA register. Port A pin levels can be
read by accessing the READ PIN register.
Individual pins can be configured as CMOS
or open drain outputs. Open drain pins
require external pull-up resistors. For
addressing information, refer to Tables 6
and 7.
Alternatively, each bit of Port A can be
configured as a low-order latched address
bus bit. The address is provided by the port
address latch, which latches the address
on the trailing edge of ALE. PAO-PA7 can
become AO-A7, respectively. This feature
enables the user generate low-order
address bits to access external peripherals
or memory that require several low-order
address lines.
May, 1993
166
Another mode of Port A (CPAF2 = 1) sets
the entire port to track the inputs
ADO/AQ-AD7/A7, depending on specific
address ranges defined by the PAD's
CSADIN, CSADOUT1, and CSADOUT2
signals. This feature lets the user interface
the microcontroller to shared external
resources without requiring external buffers
and decoders. In this mode, the port is
effectively a bi-directional buffer. The
direction is controlled !2Y.usi~9..the input
siQ!!.als ALE, RD/E or RD/E/DS, WR/vpp or
R/W, and the internal PAD outputs
CSADOUT1, CSADOUT2 and CSADIN
(see Figure 5). When CSADOUT1 and ALE
are true, the address on the input
ADO/AO-AD7/A7 pins is output through Port
A. (Carefully check the generation of
CSADOUT1, and ensure that it is stable
during the ALE pulse. When CSADOUT2 is
active, a write operation is performed (see
note to Figure 5). The data on the input
ADO/AQ-AD7/A7 pins flows out through
Port A. When CSADIN and a read operation is ~rformeE.Jdepending on the mode
of the RD/E or RD/E/DS, and WR/vpp or
R/W pins), the data on Port A flows out
through the ADO/AQ-AD7/A7 pins. In this
operational mode, Port A is tri-stated when
none of the above-mentioned three
conditions exist.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
Port Functions
(Cont.)
Port A in Non-Multiplexed
Address/Data Mode
AcceSSing the I/O Port Registers
In this mode, Port A becomes the low order
data bus byte of the chip. When reading an
internal location, data is presented on Port
A pins. When writing to an internal location,
data present on Port A pins is written to
that location.
Port B in Multiplexed Address/Data
and in a-Bit Non-Multiplexed Modes
The default configuration of Port B is I/O. In
this mode, every pin can be set as an input
or output by writing into the respective pin's
direction flip flop (DIR FF, in Figure 6). As
an output, the pin level can be controlled by
writing into the respective pin's data flip flop
(DFF, in Figure 6). When DIR FF = 1, the
pin is configured as an output. When DIR
FF = 0, the pin is configured as an input.
The controller can read the DIR FF bits by
accessing the READ DIR register; it can
read the DFF bits by accessing the READ
DATA register. Port B pin levels can be
read by accessing the READ PIN register.
Individual pins can be configured as CMOS
or open drain outputs. Open drain pins
require external pull-up resistors. For
addressing information, refer to Tables 6
and 7.
Alternately, each bit of Port B can be
configured to provide a Chip-select output
~al from PAD B. PBO-PB7 can provide
CSO-CS7, respectively. Each of the signals
CSo-CS3 is comprised of four product
terms.Thus, up to four ANDed expressions
can be ORed while deriving ~of these
Signals. Each of the signals CS4-CS7 is
comprised of two product terms. Thus, up
to two ANDed expressions can be ORed
while deriving any of these signals.
Port Bin 16-8it Non-Multiplexed
Address/Data Mode
(PSD3DXL)
In this mode, Port B becomes the highorder data bus byte of the Chip. When
reading an internal high-order data bus
byte location, the data is presented on Port
B pins. When writing to an internal highorder data bus byte location, data present
on Port B is written to that location. See
Table 9.
May, 1993
167
Tables 6 and 7 show the offset values with
the respect to the base address defined by
the CSIOPORT. They let the user access
the corresponding registers.
Port C in All Modes
Each pin of Port C (shown in Figure 7) can
be configured as an input to PAD A and
PAD B or output from PAD B. As inputs,
the pins are named A 16-A18. Although the
pins are given names of the high-order
address bus, they can be used for any
other address lines or logic inputs to PAD A
and PAD B. For example, A8-A10 can also
be connected to those pins, improving the
boundaries of CSo-CS7 resolution to 256
bytes. As inputs, they can be individually
configured to be logic or address inputs. A
logic input uses the PAD only for Boolean
equations that are implemented in any or
all of the CSO-CS10 PAD B outputs. Port C
addresses can be programmed to latch the
inputs by the trailing edge ALE or to be
transparent.
Alternately, PCO-PC2 can become
CS8-CS10 outputs, respectively, providing
the user with more external chip-select
PAD outputs. Each of the signals
CS8-CS10 is comprised of one product
term.
ALE/AS and ADO/AD-AD15/A15 in
Non-Multiplexed Modes
In non-multiplexed modes,
ADO/AO-AD15/A15 are address inputs only
and can become transparent (CLOT = 0) or
ALE dependent (CLOT = 1). In transparent
mode, the ALE/AS pin can be used as an
additional logic input to the PADs. The nonmultiplexed ALE dependent mode is useful
in applications for which the host processor
has a mu Itiplex address/data bus and
ADO/AO-AD7/A7 are not multiplexed with
AO-A7 but rather are multiplexed with other
address lines. In these applications, Port A
serves as a data bus and each of its pins
can be directly connected to the corresponding host's multiplexed pin, where that
data bit is expected.
(See Table 8.)
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
FlgureB.
PortBPln
Structure
REAOPIN
I
N
T
E
R
N
A
L
c
o
S
U
T
B
U
I
N
T
E
R
N
A
L
REAOOATA
CMOS/OO(17)
WRITEOATA CK
0
0
A
T
A
01
B
U
S
..
.~
PORTB PIN
ENABLE
MUX
CSi ....
0
8
~
REAOOIR
S
o
7
-
R
I
S
C
~
OUT...
OFF
0
1
5
WRITEOIR
DDPll
CONTROL
CK FF
R
RESET
~
I
I
NOTE: 17. CMOS/DO determines whether the output is open drain or CMOS.
Table B.
VOPort
Addresses In an
'-bit Data Bus
Mode
Table 7.
I/O Port
Addresses In a
1B-blt Data Bus
Mode 1B,19
(PSD30XL)
Byte Size Access of the I/O Port Registers
Offset from the CSIOPORT
Register Name
Pin Register of Port A
+ 2 (accessible during read operation only)
Direction Register of Port A
+4
Data Register of Port A
+6
Pin Register of Port B
+ 3 (accessible during read operation only)
Direction Register of Port B
+5
Data Register of Port B
+7
Page Register
+18
Word Size Access of the VO Port Registers
Offset from the CSIOPORT
Register Name
Pin Register of Ports B and A
+ 2 (accessible during read operation only)
Direction Register of Ports B and A
+4
Data Register of Ports B and A
+6
NOTES: 18. When the data bus width is 16, Port B registers can only be accessed if the BHE
signal is low.
19. 110 PortsEnd B are still byte-addressable, as shown in Table 6. For I/O Port B register
access, BHE must be low.
MaY,1993
168
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD3XXL Family
3-volt single-chip microcontroller peripherals
Figure 7.
Port CStructure
ADDRESS INDICA TOR
(NOTE 20)
A16
t---"'TOPAD
PCO /.
1 .. CS8 (OUTPUT LlNEJ
CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL
FROM PAD
,...---.,
ALE
A17
_
I - - -.... TOPAD
.......---.
~~=.:..:....:;..:...=.;.;~-----
FROM PAD
A18
t - - -.... TOPAD
t-=~=~..,:;.::.:~-----
PC21, ...
FROM PAD
TO
EPROM
NOTES: 20. The CADDHLT configuration bit determines if A18-A16 are transparent via the latch, or if
they must be latched by the trailing edge of the ALE strobe.
21. PSD3X2U3X3L: Individual pins can be configured independently as address or logic
inputs (CAD LOG, bits 0-2).
PSD3X1 L: All Port C pins are either address or logic inputs (CATD).
Port Functions
(Cont.)
May,1993
ALE/AS and ADO/AD-AD15/A15 in
Non-Multiplexed Modes
(PSD302l/303LJ
ALE/AS and ADD/AD-AD7/A7 in
Non-Multiplexed Modes
(PSD31XLJ
In non-multiplexed modes,
ADO/AO-AD15/A15 are address inputs only
and can become transparent (CLOT = O) or
ALE dependent (CLOT = 1). In transparent
mode, the ALE/AS pin can be used as an
additional logic input to the PADs. The nonmultiplexed ALE dependent mode is useful
in applications for which the host processor
has a multiplex address/data bus and
ADO/AO-AD?/A? are not multiplexed with
AD-A? but rather are multiplexed with other
address lines. In these applications, Port A
serves as a data bus and each of its pins
can be directly connected to the corresponding host's multiplexed pin, where that
data bit is expected. (See Table 8.)
In non-multiplexed modes, AD-A 15 are
address inputs only and can become
transparent (CLOT = 0) or ALE dependent
(CLOT = 1). In transparent mode, the
ALE/AS pin can be used as an additional
logic input to the PADs. The non-multiplexed ALE dependent mode is useful in
applications for which the host processor
has a multiplex address/data bus and
ADO/AO-AD?/A? are not multiplexed with
AO-A? but rather are multiplexed with other
address lines. In these applications, Port A
serves as a data bus and each of its pins
can be directly connected to the corresponding host's multiplexed pin, where that
data bit is expected. (See Table 8.)
169
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
A16-A19
Inputs
If one or more of the pins PCO, PC1 PC2
and CSIIA19 are configured as inputs, the
configuration bits CADDHLT and CATD
define their functionality inside the part.
CADDHLT determines if these inputs are to
be latched by the trailing edge of the
ALE or AS signal (CADDHLT = 1), or
enabled into the PSD3XX at all times
(CADDHLT = 0, transparent mode). CATD
determines whether these lines are highorder address lines, that take part in the
derivation of memory and 110 select
Signals inside the chip (CATD = 1), or logic
input lines that have no impact on memory
or 110 selections (CATD = 0). Logic input
lines typically participate in the Boolean
expressions implemented in the PAD.
EPROM
The EPROM has S banks of memory. Each
bank can be placed in any address location
by programming the PAD. Banko-Bank7
is selected by PAD outputs ESo-ES7,
respectively.
Device
EPROM
Size
EPROM Bank
Architecture
(Bea)
xB
x16
xB
x16
2Kx 16
PSD301L
256Kb
32KxS
16K x 16
4KxS
PSD311L
256Kb
32KxS
-
4KxS
-
PSD302L
512Kb
64KxS
32K x 16
SKxS
4Kx 16
PSD312L
512Kb
64KxS
-
SKxS
-
PSD303L
1Mb
12SK x S
64K x 16
16K x S
SKx 16
PSD313L
1Mb
12SK x S
-
16K x S
-
SRAM
Each PSD3XXL device has 16K bits of
SRAM. Depending on the configuration of
the data bus, the SRAM organization can
Memory Paging
(PSD3X2L/3X3LJ
The page register consists of four
flip-flops, which can be read from, or
written to, through the I/O address space
(CSIOPORT). The page register is
connected to the 03-00 lines. The Page
Register address is CSIOPORT + 1SH. The
May, 1993
EPROM
Architecture
170
be 2K x S (S-bit data bus) or 1K x 16 (16-bit
data bus). The SRAM is selected by the
RSO output of the PAD.
page register outputs are P3-PO, which are
fed into the PAD. This enables the host
microcontroller to enlarge its address
. space by a factor of 16 (there can be a
maximum of 16 pages). See Figure S.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
FlgureB.
Page Register
(PSD3X2L/3X3L)
r---..,.------------~ }
.--_.....-_ _ ~
TO PAD
INPUTS
INTERNAL
RESET
INTERNALWR
PAGE SELECT
INTERNAL RD
ADl
AD2
y
ADO
J
DATA BUS
TableB.
Signal Latch
Status In All
Operating Modes
Configuration
Bits
Signal
Name
CDATA , CADDRDAT, CLOT = 0
CDATA, CADDRDAT = 0, CLOT = 1
CDATA = 1, CADDRDAT, CLOT = 0
AD8/A8AD15/A15
CDATA = 1, CADDRDAT = 0, CLOT = 1
BHE/
PSEN
A19 and
PC2-PCO
May. 1993
8-bit data,
non-multiplexed
16-bit data,
non-multiplexed
Signal Latch
Status
Transparent
ALE
Dependent
Transparent
ALE
Dependent
CDATA = 0, CADDRDAT = 1
8-bit data,
multiplexed
Transparent
CDATA = 1, CADDRDAT = 1
16-bit data,
multiplexed
ALE
Dependent
CADDRDAT = 0, CLOT = 0
ADO/AOAD7/A7
Configuration
Mode
CADDRDAT = 0, CLOT = 1
non-multiplexed
modes
Transparent
ALE
Dependent
CADDRDAT= 1
multiplexed modes
ALE
Dependent
CDATA = 0
8-bit data,
PSEN is active
Transparent
CDATA = 1, CADDRDAT = 0
16-bit data,
non-multiplexed
mode,
BHE is active
Transparent
CDATA = 1, CADDRDAT = 1
16-bit data,
multiplexed mode,
BHE is active
ALE
Dependent
CADDHLT = 0
A16-A19 can
become logic inputs
Transparent
CADDHLT= 1
A16-A19 can
become
multiplexed
address lines
ALE
Dependent
171
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
Control Signals
The PS03XXL control ~nals are WR/vpp
or R/W, ROlE or ROlE/OS, ALE,
BHE/PSEN or PSEN, RESET, and
A 19/CSI. Each of these signals can be
configured to meet the output control signal
requirements of various microcontrollers.
WR/V"
01 R/W
In operational mode, this signal can be .
configured as WR or R/W. As WR, all write
operations are activated by an active low
signal on this pin. As R/W, the..E.!.n operates
with the E strobe of the ROlE/OS or ROlE
pin. When R/W is h~, an active high
signal on the RO/E/OS or ROlE pin _
performs a read operation. Whe'l.B!W ~
low, an active high signal on the RO/EIDS
or ROlE pin performs a write operation.
ROIEIOS (01 ROlE on PS03X1LJ
In operational mode, this signal can be
configured as RO, E, or OS. As RO, all
read operations are activated by an active
low signal on this pi~As E, the pin
~rates with.,!!!e RIW signal of t.he .
WR/vpp or R/W pin. Whe~R/W~ high, an
active high signal on the RO/E/OS pi!!..
performs a read operation. When..B.IW ~
low, an active high signal on the RO/E/OS
pin performs a write operation.
As OS, the pin functions with the R/W
signal as an active low data strobe signal.
As OS, the RIW defines the mode of
operation (Read or Write).
MaY,1993
BHE/PSEN
This pin's function depends on the
PS03XXL data bus width. If it is 8 bits, the
pin is PSEN; if it is 16 bits, the pin is BHE.
In 8-bit mode, the PSEN function enables
the user to work with two address spaces:
program memory and data memory
(if COMB/SEP = 1). In this mode, an active
low signal on the PSEN pin causes the
EPROM to be read if selected. The SRAM
and 1/0 ports read operation are done
by RO low (CRRWR = 0), or by E high and
R/W high (CRRWR = 1, CEOS = 0)
or by OS low and RIW high (CRRWR,
CEOS = 1).
Whenever a member of the 8031 family
(or any other similar microcontroller) is
used, the PSEN pin must be connected to
the PSEN pin of the microcontroller.
If COMB/SEP = 0, the address spaces of
the program and the data are combined. In
this configuration (except for the 8031-type
case mentioned above), the PSEN pin
must be tied high to Vee, and the EPROM,
SRAM, and 1/0 ports are read by RO low
(CRRWR = 0), or by E high and RIW high
(CRRWR = 1, CEOS = 0) or by OS low and
R/W high (CRRWR, CEDS = 1). See
Figures 9 and 10.
In BHE mode, this pin enables accessing of
the upper-half byte of the data bus. A low
on this pin enables a write or read
operation to be performed on the upper half
of the data bus (see Table 9).
ALE 01 AS
RESET
ALE polarity is programmable. When
programmed to be active high, a high on
the pin causes the input address latches,
Port A address latches, Port C, and A19
address latches to be transparent. The
falling edge of ALE locks the information
into the latches. When ALE is programmed
to be active low, a low on the pin causes
the input address latches, Port A address
latches, Port C, and A19 address latches to
be transparent. The rising edge of ALE
locks the appropriate information into the
latches.
This is an asynchronous input pin that
clears and initializes the part. For the
PS03XXL, reset is a low signal only.
Whenever the reset input is driven low for
at least 500 ns, the chip is reset. After reset
becomes high, the chip will be operational
only after an additional 500 ns. See
Figure 11. Note that during boot-up, the
part is not automatically reset internally and
does require an external reset. Tables 10a,
10b and 11 indicate the state of the part
during and after reset.
172
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
Control Signals
(Cont.)
PSD3XXL Family
In A19 mode, the pin is an additional input
to the PAD. It can be used as an address
line (CADLOG3 = 1) or as a generalpurpose logic input (CADLOG3 = 0). A19
can be configured as ALE dependent or as
transparent input (see Table 8). In this
mode, the chip is always enabled.
A191CSI
When configured as CSI, a high on this pin
deselects, and powers down, the chip. A
low on this pin puts the chip in normal
operational mode. For PSD3XXL states
during the power-down mode, see Tables
12 and 13, and Figure 12.
Figure 9.
Combined
Addrsss Space
ADDRESS --"~~I
r=l
PAD
L:J
INTERNAL RD
CS OE
1/0 PORTS
Table 9.
High/Low Byte
Selection Truth
Table (In 16-Blt
Configuration
Only)
May, 1993
SHE
Ao
0
0
1
1
0
Operation
Whole Word
1
Upper Byte FromfTo Odd Address
0
1
Lower Byte FromfTo Even Address
None
173
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
Figure 10.
BOa1-Type
Separate Code
and Data
Address Spaces
I
INTERNALRD
...
-
ADDRESS
1/0
OE
PORTS
cs
Il
•
PAD
I
-...
SRAM
~
PSEN
~
Table 10a.
Signal States
During Reset
Cycle (RESET)
Table 10b.
Signal States
After Reset Cycle
(RESET)
cs
EPROM
OE
Signal
Condition
ADOIAO-AD 15/A 15
Input
PAO-PA7 (Port A)
Input
PBO-PB7 (Port B)
Input
PCD-PC2 (Port C)
Input
Signal
Configuration Mode
Condition
ADO/AD-AD7/A7
All
Input
A8-A15
All
Input
1/0
Tracking ADOIAD-AD7
Address outputs AD-A7
1/0
CS7-CSO CMOS outputs
CS7-CSO open drain outputs
Address inputs A 16-A18
CS8-CS10 CMOS outputs
Input
Input
Low
PAD-PA7)
(Port A
PBO-PB7
(Port B)
PCO-PC2
(Port C)
May, 1993
+
OE
cs
174
Input
High
Tri-stated
Input
High
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
Figure ".
TheReset
Cycle (RESET)
V1H
V1L
1----------.. . .
5OOn8
500n8
••
RESET LOW
Table 11.
Internal States
During and After
Rsset Cycle
RESET HIGH
PART
OPERATIONAL
Signals
Component
PAD
Data register A
Direction register A
Data register B
Direction register B
Contents
CSO-CS10
All
= 1 (Note 13)
CSADIN, CSADOUT1 ,
CSADOUT2, CSIOPORT,
RSO, ESO - ES7
All
= 0 (Note 13)
n/a
n/a
n/a
n/a
0
0
0
0
NOTE: 23. All PAD outputs are in a non-active state.
Figure 12.
A19/CSI Cell
Structure
ADDRESS INDICATOR
TO EPROM
CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL
~E------------------~
~.:..e.-----..
A19/CSI-
~
A19
1-------+-.. TO PAD
PO
~.'_C.;....;S;.;..I(1O..
..;;..W;.;.;E;;.;..R;...;-U;.;..P..;;.S;.;;IG;...;NA...;.;;L;L..)__________... TO PAD, EPROM, SRAM •
.......-:
PORTS, LATCHES, ETC.
~~
NOTES:
May, 1993
22. The CADDHLT configuration bit determines if A 19-A 16 are transparent via the latch,
or if they must be latched by the trailing edge of the ALE strobe.
175
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
Table 12a. Signal
States During
Power-Down
Mode
(PSD30XL)
Configuration Mode
Condition
ADO/AD-AD15/A15
Signal
All
PAD-PA7
Tracking ADOIAD-AD7IA 7
Address outputs AO-A7
Input
Unchanged
Input
A1I1's
PBo-PB7
CSO-CS7 CMOS outputs
CSO-CS7 open drain outputs
Unchanged
A1I1's
Tri-stated
Address inputs A 18-A16
CS8-CS10 CMOS outputs
Input
A1I1's
1/0
1/0
PCo-PC2
Table 12b.
Signal States
During PowerDown Mode
(PSD31XL)
Table 13.
Internal States
During PowerDown
Signal
Condition
ADO/AO-AD7/A7
All
Input
A8-A15
All
Input
1/0
Tracking ADO/AO-AD7/A7
Address outputs Ao-A7
Unchanged
Input
A1I1's
PBo-PB7
I/O
CSO-CS7 CMOS outputs
CSO-CS7 open drain outputs
Unchanged
A1I1's
Tri-stated
PCO-PC2
Address inputs A 1S-A16
CSS-CS10 CMOS outputs
Input
A1I1's
PAo-PA7
Signals
Component
PAD
Data register A
Direction register A
Data register B
Direction register B
MaY,1993
Configuration Mode
Contents
CSO-CS10
All 1's (deselected)
CSADIN, CSADOUT1,
CSADOUT2, CSIOPORT,
RSO, ESO-ES7
All O's (deselected)
n/a
n/a
nla
n/a
176
All
unchanged
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
Figure 13.
PSD3XXL
Interface With
Intel's BOC31
Vee
MICROCONTROUER
31
-
PO.O
PO.1
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
EANP
X1
X2
9
RESET
P2.0
P2.1
P22
P2.3
P2.4
P2.5
P2.6
P2.7
INTO
INT1
TO
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
WR
PSEN
ALE
TXD
39
23
24
25
26
27
28
38
37
36
35
34
33
3
ADO/AO
AD1/A1
AD2IA2
AD3IA3
AD4/A4
ADSlA5
29
AD6IA6
30 AD7/A7
1
22
23
24
25
26
27
28
31
32
33
35
36
37
38
39
17
16
22 RD
2 WRNpp
1
BHEIPSEN
ALE
RESET
29
30
AD8IA8
AD9IA9
AD10/A10
AD11/A11
AD121A12
AD131A13
AD14/A14
AD1S1A15
RXD
PSD3XXL
80C31
34
12
-=-
NOTE: RESET to the PSD3XXL must be the output of a RESET chip or buffer.
If RESET is the output of an RC circuit, a separate buffered RC RESET to the PSD3XXL
(shorter than the 80C31 RC RESET) must be provided to avoid a race condition.
The configuration bits for Figure 13 are:
CALE
0
CDATA
0
CADDRDAT
COMB/SEP
CRRWR
CEDS
oor 1 (both valid)
o
o
All other configuration bits may vary according to the application requirements.
System
Applications
May, 1993
In Figure 13, the PSD3XXL is configured to
interface with Intel's 80C31 , which is a 16bit address/8-bit data bus microcontroller.
Its data bus is multiplexed with the loworder address byte. The 80C31 uses
signals RD to read from data memory and
PSEN to read from code memory. It uses
WR to write into the data memory. It also
uses active high reset and ALE signals.
The rest of the configuration bits as well as
the unconnected signals (not shown) are
application specific and, thus, user
dependent.
177
In Figure 14, the PSD3XXL is configured to
interface with Motorola's 68HC11, which
is a 16-bit address/8-bit data bus
microcontroller. Its data bus is multiplexed
with the low-order address byte. The
68HC11 uses E and R/W signals to derive
the read and write strobes. It uses the term
AS (address strobe) for the address latch
pulse. RESET is an active low signal. The
rest of the configuration bits as well as the
unconnected signals (not shown) are
specific and, thus, user dependent.
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD3XXL Family
3-volt single-chip microcontroller peripherals
Figure 14.
PSD3XXL
Interface With
Motorola's
BSHC11
Vee
MICROCONTROLLER
PCO
20
PDQ
PC1
PC2
PC3
PC4
PC5
PD1
PD2
PD3
PD4
PD5
PC6
PC7
PEO
PE1
PE2
PE3
PE4
PES
PE6
PE7
PBO
PB1
PB2
PB3
PB4
PBS
PBS
PB7
PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7
9
10
11
12
13
14
15
16
23
42
41
40
39
38
37
36
35
31
32
5
22
6
4
17
2
13
3
1
E
RiW
AS
RESET
XIRO
IRO
MODB
MODA
VRH
VRL
XTAL
18
19
2
3
24
25
26
27
28
29
30
33
35
36
37
38
39
ADO/AO
AD1/A1
AD2IA2
AOOIA3
AD4/M
ADS/AS
AD6IA6
AD7/A7
AD8IA8
AD9IA9
AD10/A10
AD11/A11
AD121A12
AD13/A13
AD14/A14
AD15/A15
E
RiWNpp
AS
RESET
BHEIPSEN
Vee
GND
EXTAL
PSD3XXL
68HC11
34
12
-::-
The configuration bits for Figure 14 are:
CALE
0
CRRWR
1
CDATA
0
CEDS
o
CADDRDAT
1
COMB/SEP
0
All other configuration bits may vary according to the application requirements.
System
Applications
(Cont.)
May, 1993
In Figure 15, the PSD3XXL is configured to
work directly with Intel's 80C196KB microcontroller, which is a 16-bit address/16-bit
data bus processor. Address and data lines
multiplexed. In the example shown, all
configuration bits are set. The PSD3XXL is
configured to use PCO, PC1, PC2, and
CSI/A19 as A16, A17, A18, and A19
inputs, respectively. These signals
are independent of the ALE pulse (Iatchtransparent). They are used as four
general-purpose logic inputs that take part
in the PAD equations implementation.
178
Port A is configured to work in the special
track mode, in which (for certain conditions)
PAD-PA7 tracks lines ADO/AD-AD7/A7.
Port B is configured to generate CSO-CS7.
In this example, PB2 serves as a WAIT
Signal that slows down the 80C 196KB
during the access of external peripherals.
These 8-bit wide peripherals are connected
to the shared bus of Port A. The WAIT
Signal also drives the buswidth input of the
microcontroller, so that every external
peripheral cycle becomes an 8-bit data bus
cycle. PB3 and PB4 are open-drain output
signals; thus, they are pulled up externally.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
Figure 15.
PSD3XXL
Interface With
Intel's
BOC196KB.
+5V
C)
rt· ",
¢
cm:c.:::
67
XTALl
66
XTAL2
3
~
~
r""1"t
roo-f-----oI
-----01
-----01
-----01
------
~
~
~
§
-
O.lI'F
18
17
15
44
4 39
33
38
~
+5V
6
5
7
4
11
10
8
9
,r:;
24
25
26
27
13
37
...4
-2-
P1.0
P1.1
P1.2
P1.3
P1.4
Pl.5
P1.6
Pl.7
19
20
21
22
23
30
31
32
P3.0/ADO
60
59
58
57
56
55
Vee
NMI
READY
BUSWIDTH
CDE
RESET
P3.1/ADl
P3.2/AD2
P3.3/AD3
P3.4/AD4
P3.5/AD5
P3.61AD6
P3.7/AD7
PO.O
PO.l
PO.2
PO.3
PO.4
PO.5
PO.6
PO.7
P4.0/AD8
P4.1/AD9
P4.21AD10
P4.31AD11
P4.4/AD12
P4.SlAD13
P4.6JAD14
P4.7/AD15
P2.OITXD
P2.1/RXD
P2.2lEXINT
P2.31T2CLK
P2.41T2RST
P2.5IPWM
P2.6JT2 UPIDN
P2.71T2 CAPTR
CLKOUT
BHEIWRH
~
HSI.O
HSl.l
HSI.2IHSO.4
HSI.3IHSO.5
AD
ALElADV
INST
8OC196KB
Vss
1:
Vs.
}-,
~
ADO/AO
ADl/Al
AD2IA2
AD3IA3
'/
'/
.
AD4/M
.~t\.
FOUR
ft'
X
44
~
53
52
51
ADBlA8
AD9o'A9
49
48
47
46
45
AD12/A12 ~
AD13/A13 ~
AD14/A14 ~ ~
AD15/A15 ~ '-.:
~
-"""
~
.i"~
ADll/All
'"
''X
~
~40
A
A
A
A
O/AO
l/Al
23
24
25
26
1M 27
SlAS 28
A6JA6 29
A 7/A7 30
A BlAB 31
9o'A9 32
1O/Al 033
I2IA2
31A3
ll/A1135
A 12/A1236
A 13/Am7
AD14/A1438
AI 15/A1539
Vee
ADOIAO
ADl/Al
AD2IA2
AD3IA3
AD4/M
ADSIAS
AD6JA6
AD7/A7
ADBlA8
AD9o'A9
ADl OIAl 0
ADll/All
AD121A12
AD131A13
AD14/A14
AD1SiA15
~ 61
40
41
~
r--E-
~
,........iL
HSO.O
HSO.l
HSO.2
HSO.3 ~
1
2
22
13
r-ir
3
6
L
21
20
19
18
PBO
PBl
PB2
11
10
9
8
7
6
PB3
PB4
PBS
PBS
8
>
~SHARED
BUS
PAO
PAl
PA2
PA3
PM
PAS
PAS
PA7
PCO
PCl
PC2
CSI/A19
~
/
/
'/
'/
'/
'/
17
16
15
14
-
'Wlm'
"'L...--.....?
....;....--.!....
...
.. ~ ..
4.71<0 ..
~
~
~
=4.71<0
_ _ O+5V
E3
BHEIPsEN
WFwPP
iii
ALE
RESET
PSD3XXL
I=:<
O.l I'F
...
PB7
~
GENERAL
PURPOSE
INPUTS
GND
GND
UJ:...
2
4
ALE
The configuration bits for Figure 15 are:
CALE
CDATA
CADDRDAT
CPAF1
CPAF2
CA19/CSI
CRRWR
COMB/SEP
CADDHLT
May, 1993
>
IJOPINS
ADSIAS
AD6JA6
AD7/A7
54
AUlO .. 15
ADDRESSIDATA MULTIPLEXED BUS
~
~
VREF
VPP
ANGND
EA
ADjO .. 151
~
o
1
Don't care
1
1
o
o
o
179
CSECURITY
CPCF2, CPCF1 , CPCFO
CPACOD7-GPACODO
CPBF7-GPBFO
CPBCOD7-CPBCODO
CEDS
CADLOG3-CADLOGO
Don't care
0,0,0
OOH
OOH
18H
o
OH
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripherals
PSD3XXL Family
Security
Mode
Security Mode in the PSD3XX locks the
contents of the PAD A , PAD B and all the
configuration bits. The EPROM, SRAM,
and 1/0 contents can be accessed only
through the PAD. The Security Mode can
be set by the MAPLE or Programming
software. In window packages, the mode is
erasable through UV full part erasure. In
the security mode, the PSD3XX contents
cannot be copied on a programmer.
eMlser-'1t
The CMiser-Bit provides a programmable
option for power-sensitive applications that
require further reduction in power
consumption. The CMiser-Bit (CMiser = 1)
in the Maple portion of the PSD3XX sytem
development software can be used to
reduce power consumption. The CMiserBit turns off the EPROM blocks in the
PSD3XX whenever the EPROM is not
accessed, thereby reducing the active
current consumed by the PSD3XX.
In the default mode, or if the PSD3XX is
configured without programming the
CMiser-Bit (CMiser = 0), the device
operates at specified speed and power
rating as specified in the A.C. and D.C.
Characteristics.
May, 1993
180
However, if the CMiser-Bit is programmed
(CMiser = 1), the device consumes even
lower current, and is reflected in the data
sheet. This mode has an adder in
propagation delay in T5, T6, and T7
parameters in the A.C. Characteristics, and
should be added to compute worst-case
timing requirements in the application.
Philips Semiconductors Mlcrocontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
Key Features
o
o
o
May, 1993
o
256 Kbits of UV EPROM
-
Configurable as 32K x 8 or as 16K x 16
3.0 to 5.5 Volt Operation
-
Divides into 8 equal mappable blocks
for optimized mapping
19 Individually Configurable I/O pins
that can be used as:
-
Block resolution is 4K x 8 or 2K x 16
-
250 ns EPROM access time, including
input latches and PAD address
decoding.
Single Chip Programmable Peripheral
for Microcontroller-based Applications
-
Microcontroller I/O port expansion
-
Programmable Address Decoder
(PAD) I/O
-
Latched address output
-
Open drain or CMOS
o
Two Programmable Arrays
(PAD A and PAD B)
-
Total of 40 Product Terms and up to
14 Inputs and 24 Outputs
-
Address Decoding up to 1 MB
-
Logic replacement
o
"No Glue" Microcontroller Chip-Set
-
PSD301L
Built-in address latches for multiplexed
address/data bus
-
Non-multiplexed address/data bus
mode
-
Selectable 8 or 16 bit data bus width
-
ALE and Reset polarity programmable
-
Selectable modes for read and write
control bus as RDIWR or R/W/E
-
BHE pin for byte select in 16-bit mode
-
PSEN pin for 8051 users
181
o
16 Kbit Static RAM
-
Configurable as 2K x 8 or as 1K x 16
-
250 ns SRAM access time, including
input latches and PAD address
decoding
o
Address/Data Track Mode
-
Enables easy Interface to Shared
Resources (e.g., Mail Box SRAM) with
other Microcontrollers or a Host
Processor
o
-
Built-In Security
Locks the PSD301 L and PAD Decoding
Configuration
o
Available in a Choice of Packages
-
44 Pin PLDCC and CLDCC
o
o
Simple Menu-Driven Software:
Configure the PSD301 L on an IBM PC
Pin Compatible with the PSD3XX and
PSD3XXL Series
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
Absolute
Maximum
Ratlngs1
Symbol
Palametel
PSD301L
Min
Max
Unit
CERAMIC
Condition
-65
+ 150
°C
PLASTIC
-65
+ 125
°C
-65
+ 150
°C
Voltage on any Pin
With Respect to GND
-0.6
+7
V
Vpp
Programming
Supply Voltage
With Respect to GND
-0.6
+14
V
Vce
Supply Voltage
With Respect to GND
-0.6
+7
V
>2000
V
TSTG
Storage Temperature
TSTG
Storage Temperature
ESD Protection
NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.
Operating
Range
Recommended
Operating
Conditions
Range
Tempelatule
Vee
Commercial
0° C to +70°C
3.0 to 5.5 V
Symbol
Palametel
Conditions
vcc
Supply Voltage
VIH
High-level Input Voltage Vcc = 3.0 V to 5.5 V
VIL
All Speeds
Low-level Input Voltage
* Before 8/1/1993.
** After 8/1/1993.
May, 1993
182
Vc c =3.0Vt05.5V
Min
Typ
Max
Unit
3.0
3.3
5.5
V
Vcc + 0.5
V
0.2 Vcc *
V
0.3 Vee**
V
0. 7Vcc
-0.5
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD301 L
DC
CMiser= 1
Subtract: It It
Characteristics
Symbol
Parameter
Output Low
Voltage
VOL
Output High
Voltage
VOH
IS81
Vcc Standby
Current (CMOS)
(Notes 2 and 3)
Icc1
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
Icc2
Active Current
(CMOS) (SRAM
Block Selected)
(Notes 2 and 5)
Icc3
Conditions
Min Typ Max Min Typ Max Unit
IOL = 20 JlA
Vcc = 3.0 V
0.01
0.1
V
IOL = 4 rnA
Vcc = 3.0 V
0.15
0.4
V
IOH = -20 JlA
Vcc =3.0 V
2.9
2.99
V
IOH =-1 rnA
Vcc = 3.0 V
2.4
2.6
V
10*
25*
1**
5**
Vcc = 3.3 V
(Note 5)
6
12
3.0
5
rnA
Vcc = 3.3 V
(Note 6)
10
20
3.0
5
rnA
Vcc = 3.3 V
(Notes 5
and 7)
6
12
0
0
rnA
Vcc = 3.3 V
(Note 6
and 7)
10
20
0
0
rnA
Vcc = 3.3 V
(Note 5
and 7)
20
33
3
5
rnA
Vcc = 3.3 V
(Notes 6
and 7)
24
40
3
5
rnA
Vcc = 3.3 V
JlA
III
Input Leakage
Current
VIN = Vcc
orGND
-1
±0.1
1
JlA
ILo
Output Leakage
Current
VOUT = Vcc
orGND
-10
±5
10
JlA
CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
CSI/A 19 is high and the part is in a power-down configuration mode.
Add 2.0 mA/MHz for AC power component (power = AC + DC).
Ten (10) PAD product terms active. (Add 190 ~ per product term, typical, or 240 ~
per product term maximum.)
6. Forty (40) PAD product terms active.
7. In 8-bit mode, an additional 3 mA Max can be saved under CMiser.
NOTES: 2.
3.
4.
5.
* Before 8/1/1993.
** After 8/1/1993.
May, 1993
183
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
Figure 1.
Normalized
Supply Current
PSD301L
2.5
fS.
Supply Voltage
2.25
a:
w
:i
a..
I
2.0
F=
...I
::J
:E
~
zw
a:
a:
/
1.75
1.5
/
::J
0
>
...I
a..
a..
1.25
/
::J
en
1.0
/
/
V
/
V
./:
I
0.75
2.5
3.0 3.3 3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
The Normalized Supply Current vs. Supply
Voltage graph shown above, provides a
multiplier for any ISB or Icc value in the D.C.
Characteristics table. As noted, it is
normalized for a supply voltage of 3.3 volts.
Since device characterization data shows
very little supply current difference
over speed, the multiplier includes all
May, 1993
184
frequencies of operation from standby to
quiescent to full dynamic speed. To use,
calculate the supply current at 3.3 volts for
your operation configuration using the D.C.
Characteristics table. Then multiply that
value by the Supply Current Multiplier for
the supply voltage actually being used.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
AC
Characterlstlcs(8)
(See Timing
Diagrams)
PSD301L
-3D
-25
Symbol
Parameter
Min Max Min Max
Add:**
T1
ALE or AS Pulse Width
75
80
ns
T2
Address Set-up lime
30
35
ns
T3
Address Hold lime
30
35
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
ns
T5
ALE Valid to Data Valid
250
25
ns
T6
Address Valid to Data Valid
250
300
25
ns
T7
CSI Active to Data Valid
275
325
30
ns
T8
Leading Edge of Read
to Data Valid
90
95
0
ns
T9
Read Data Hold lime
0
ns
T10
Trailing Edge of Read
to Data High-Z
50
55
0
ns
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
40
45
T12
RD, E, PSEN, OS Pulse Width
100
110
0
ns
WR Pulse Width
90
95
0
ns
0
0
0
ns
T12A
300
0
0
ns
T13
Trailing Edge of Write or Read
to Leading Edge of ALE or AS
T14
Address Valid to Trailing
Edge of Write
250
300
0
ns
T15
CSI Active to Trailing Edge
of Write
275
375
0
ns
T16
Write Data Set-up Time
60
65
0
ns
T17
Write Data Hold lime
25
30
0
ns
T18
Port to Data Out Valid
Propagation Delay
0
ns
75
70
T19
Port Input Hold Time
T20
Trailing Edge of Write to Port
Output Valid
0
0
0
ns
100
110
0
ns
T21
ADi or Control to CSOi Valid
6
80
5
85
0
ns
T22
ADi or Control to CSOi Invalid
4
80
4
85
0
ns
T23
Track Mode Address Propagation
Delay: CSADOUT1 Already True
70
75
0
ns
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes True
During ALE or AS
100
110
0
ns
Track Mode Trailing Edge of ALE
or AS to Address High-Z
60
65
0
ns
T23A
T24
NOTE: 8. These AC Characteristics are for Vee = 3.0 - 3.6V.
May. 1993
eMiser= 1 Unit
185
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD301 L
3-volt single-chip microcontroller peripheral
AC
Characteristics
(Cont.)
·25
Symbol
·30
Min Max Min Max
Palametet
CMisel=1
Add:*'" Unit
T24
Track Mode Trailing Edge of ALE
or AS to Address High-Z
60
65
0
ns
T25
Track Mode Read Propagation
Delay
70
75
0
ns
T26
Track Mode Read Hold Time
T27
Track Mode Write Cycle,
Data Propagation Delay
T28
Track Mode Write Cycle,
Write to Data Propagation Delay
7
T29
Hold Time of Port A Valid
During Write CSOi Trailing Edge
4
T30
CSI Active to CSOi Active
9
110
T31
CSllnactive to CSOi Inactive
9
110
T32
Direct PAD Input as Hold Time
24
30
0
ns
T33
RIW Active to E or DS Start
60
65
0
ns
10
70
10
60
80
7
75
ns
65
0
ns
85
0
ns
0
ns
0
ns
0
ns
4
8
120
8
120
T34
E or DS End to R/W
60
65
0
ns
T35
AS Inactive to E high
40
45
0
ns
T36
Address to Leading Edge of Write
50
60
0
ns
NOTES: 9. AOi = any address line.
10. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or
through Port C (CS8-CS10).
11. Oirect PAO '!!put = any ofJ!le following direct PAO input lines: CSI/A 19 as transparent
A19, RO/E/OS, WR or RIW, transparent PCo-PC2, ALE (or AS).
12. Control signals ROlE/OS or WR or RIW.
** After 8/1/1993.
MaY,1993
186
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
PSD301 L
3-volt single-chip microcontroller peripheral
Figure 2.
AC Testing
Input/Output
Waveform
009V:=x___-\ -___-'
Figure 3.
AC Testing
Load Circuit
2.0 V
-,....
c>
:~
DEVICE
UNDER
TEST
400 n
I
--- CL =30pF
(INCLUDING
SCOPE AND JIG
":'" CAPACITANCE)
Figure 4.
The Reset
Cycle (RESET)
V1H
V1L
..
500 ns
• ..
RESET LOW
May, 1993
SOOns
RESET HIGH
187
•
PART
OPERATIONAL
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD301L
Figure 5.
Timing of '-Bit
Multiplexed
AddreSS/Data
Bus, CRRWR = 0
-
....,
CSI/A19
as CSI
READ CYCLE
....
...
32
32-
AX\
\
~XX
7
Direct (13)
PAD Input
Multiplexed
Inputs
(14)
~
-X)
~
Active High
ALE
Active Low
ALE
~ OC
I.
STABLE INPUT
6
...
3
,
4
~~
13
8
,
DATA
;N
r
ADDRESS B
,1
...:-.
'(
1\
3
~
161-
-
X~
/
~ If
-
rL
,
Lt
J
~
11
~
~
12
~
J
,
36
J
13
12A ~
~
If
,
18
\
Xl XXXXXXXXX
I
-
XXXXXXXXXXXXXXXX XX
OUTPUT
INPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
-
23
_\
~
INPUT
\
}l XXX XXX XXX
~
19
23
ADDRESS A
See referenced notes on page 198.
May, 1993
,XXXX IXXXX
2
J
WRNppor
RWasWR
Any of
PAO-PA7 Pins
as Address
Outputs
~
14
~
J~ ~
XXX XXX
14
~ ~\
DATA VALID
•
Ir~
1 1\
5
Any of
PBO-PB7
as 1/0 Pin
,ID
:-
STABLE INPUT
10
ADDRESSA J
ROlE as RD
Any of
PAO-PA7
as 1/0 Pin
32-
XXXXXXXX ~XXXX XXXXXX
2
.XXX
15
6
AO/ADOA7/AD7
--
WRITE CYCLE
.....
188
1\
ADDRESSB
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
PSD301L
Flgule6.
Timing of 8-Blt
Multiplexed
AddlBSS/Data
Bus, CRRWR = 1
CSI/A19
asCSI
..,
--
-.. ......
READ CYCLE
....
32
32-
/X\
~
Multiplexed (14)
Inputs
AO/ADOA7/AD7
~~
I
-
!XXXX IXXXX
..
3
DATA VALID
~ -"I\.
2
4
•
h
161-
13
~
34
Any of
PBO-PB7
as liD Pin
Any of
PAO-PA7 Pins
as Address
Outputs
Xl XXXXXXXXX
19
~
OUTPUT
INPUT
IXXXXXXXXXXXXXXXXX XX
OUTPUT
23
~
'I
ADDRESS A
JI\.
See referenced notes on page 198.
May. 1993
r-
iXXXXX XXXXXXXXXXX) XX
23
"
-
INPUT
I-
---11\.
12
~-
XXXXX
\.
I
~
13
18
~) XXXXXXXXX
Lr
'34
12
)XXXXXX
I
,
I
36
33
rL
r-
35
-
33
8
~
J
.!..
35
.J
3
'--
xx:
~
~{ 1/
ADDRESSB
5
Any of
PAO-PA7
as liD Pin
-
DATA
IN
~m
RD/E as E
WRNppor
RiWasRfii
•
14
r--+
~
~.
-
XXX XXX
14
10
ADDRESSA )
2
,
32STABLE INPUT
IXX XXXXXX D(XXXX !XXXXXX
6
Active High r h
AS I . 1 ~
Active Low
AS
XX
6
-X~
-~
15
STABLE INPUT
4:..
'(XX XXX
7
Direct (13)
PAD Input
-..
WRITE CYCLE
189
ADDRESS B
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
PSD301L
Figure 7.
Timing of 16-Blt
Multiplexed
Address/Data
Bus, CRRWR = 0
-
.....,
CSIIA19
asCSI
. ...
READ CYCLE
.--..
J
\
~~
....
32-
IXX XXXX
7
15
r--
32Direct (13)
PAD Input
~~
(14)
~ 0\
I.
STABLE INPUT
I
Multiplexed
Inputs
-.
WRITE CYCLE
-
~
32
6
X~
14
•
XXXXXXXX XXXXX XXXXXX
6
DeXXX XXXX
14
10
~~
XXX KXXX
STABLE INPUT
I'(XXXXXXX XXXXX XXXXX)(
-
I.{XXX XXXX
DATA
AO/ADOA151AD15
-
J~
~m
ADDRESS A J
2
DATA VALID
3
Active High r h
ALE I .. 1 \
---+
4
Active Low
ALE
8
,
'I
,
RD/Eas RD
DOO _"I\.
-
~
>-
ADDRESS B
2
3
~
16i-
~
,
XX -
~ ,J
1
j
\..---1
J,N
I
I\. 1/
...,:....
'I
,
11
.J
'-
13
5
rL
Lr
12
J
"
...
36
12A
~
~
'L-I
WRNpp 0 r
RiWasWR
18
Any 0
f
PAO-PA7
as 1/0 Pin
X) XXXXXXXXX
INPUT
X) XXXXXXXXX
INPUT
#
Any 0
f
PBO-PB7
I
as 1/0 Pin
Any of
PAO-PA7 Pins
as Address
Outputs
19
XXXXXXXXXXXXXXXX) XX
23
J
23
fADDRESS A
J
See referenced notes on page 198.
May, 1993
OUTPUT
)(1 XXXXXXXXXXXXXXXXXXX OUTPUT
l+-
-
~
190
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD301L
FigureS.
Timing of 16-Blt
Multiplexed
AddreSS/Data
Bus, CRRWR = 1
-
~
CSI/A19
asCS I
READ CYCLE
32
XX) XXXX
["I\.
7
Direct (13
)~
PAD Input
~
l+-
32-
[..,
~J
--
I\.
....
WRITE CYCLE
....
~
15
6
I+-
32-
~~
STABLE INPUT
IXXX KXXX
STABLE INPUT
14
I
Multiplexed
Inputs
(14
) X~
IXXXXXXXX xxxxx IXXXXXX
6
~~
!XXXX IXXXX
14
10
.(XXXXXXX XXXXX IXXXXXX
'(XXX IXXXX
DATA
AO/ADO
A15/AD15
-
J,N
~
2
Active High
AS
Active Low
AS
~ro
ADDRESS A J
DATA VALID
XXJ
P1 -
2
3
V-r--,
~ 1\
If
ADDRESS B
i-\
3
-
~
1
J~ 1---+
J
,
,
35
l\- I---'
~
13
ROlE as E
l-
~ VJ
,
35
~
I\33
12
J
16
~
34
If
I/)OC L--
J
5
12
13
I
WR/Vppor
X XXXXXX},
RfiN as RfiN
33
I
Any 0 f \
PAO-PA7 JD 'XXXXXXXXX
I
as lID Pin
X) IXXXXXXXXX
Any 0
f
PBO-PB7 I
as lID Pin
Any 0 f
PAO-PA7 Pins
as Address
Outputs
~
18
36
19
--
)IXXXXXXXXXXXXXX XXXXX
OUTPUT
INPUT
)IXXXXXXXXX X XXXXXXXXX
OUTPUT
~
~
~
INPUT
'If
ADDRESS A
J~
See referenced notes on page 198.
May, 1993
r-
XXXXX
8
IE.
-
Lr
~ 34
191
ADDRESS B
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
PSD301L
FlgureB.
TImIng of '-Bit
Data Non-
MultIplexed
AddreSS/Data
Bus, CRRWR =0
-
CSI/A19
asCSI
......,
.... ......
READ CYCLE
.....
32
WRITE CYCLE
iXX XXX
jr"~
\
7
Direct (13)
PAD Input
AO/ADOA15/AD15
as AO-A15
PCO-PC2.
CSI/A19 as
Multiplexed
Inputs
PAO-PA7
~~
~
6
~
STABLE INPUT
~
-
6
~ro
DATA VALID
14
XX
4
8
13
-
3
~
1
.-.:-.
~
DATA
IN
L
~
2
,
'(
,
~
17
I
,
'-
11
36
Lr
19
Xl IXXXXXXXXX
#
13
'\.-.1
5
A
)XXXXXXXXXXXXXXXXXXX
INPUT
See referenced notes on page 198.
May. 1993
iL
12
18
Any 0
f
PBO-PB7
as 1/0 Pin
-
1/ ~
f-I
r
-'16 ~J
12A
....-.
WRNpF' or
RiWas WR
...
XXXX XXXX
J
f--+
~~
RD/E as RD
IXXX .XXX
32---.
~
3
'r~
1 1\
,
~ P<
•
STABLE INPUT
10
-i
ALE
14
IXXXXXXXX ){XXXX XXXXXX
,
ALE I ..
~.
'XXX XXX
STABLE INPUT
1-
~
2
Active Low
15
STABLE INPUT
-~ W
Active High
...
32---.
irI
.....
192
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontro"er peripheral
PSD301L
Figure 10.
Timing of '-Bit
Data MonMultiplexed
AddreSS/Data
Bus, CRRWR = 1
-
:----,
CS I/A19
as CSI
.
READ CYCLE
....
~
32
-
AOIADOA15/A 015
~
~
asAO-A15 -
STABLE INPUT
~
STABLE INPUT
6
~
X
I'(XX XXX
m
3
XXX XXX
32 --.
'-~
)()Q
\
~
2
~
3
h
16 -
1
4
35
f-J
13
35
1/
X
~r
)
33
8
~ 34
1\.J
12
13
1-
X XXXXXXJ
RiNas Rm
~
'- J
36
12
WRIV pp or
-
DATA
IN
,
34
33
~
1XY.'lX XXXX
14
1 \
+--+
I
XXXXX
If
I
18
\
PBO-PB7 X)
as IIOPin '
XXXXXXXXX
19
INPUT
~
I\.
See referenced notes on page 198.
May, 1993
STABLE INPUT
/
DATA VALID
r~
ROlE as E
An yof
~ 0(
XXX ~XXX
14
~
--J
Active Low'
ALE
STABLE INPUT
10
~
Active High
ALE I
~ 0(
IXXXXXXXX OCXXXX XXXXXX
6
2
~
-.
15
00\
PCO- PC2,
CSI/A19as _I\.
Multiplexed
Inputs
PAO -PA7
32 - .
AX~
~
7
Direct(13)
PAD Input
WRITE CYCLE
.....
193
XXXXXXXXXXXXXXXXXXX
OUTPUT
Preliminary specification
Philips Semiconductors Microcontrol\er Peripherals
PSD301L
3-volt single-chip microcontroller peripheral
Figure 11.
Timing of 16-BIt
Non-Multiplexed
Address/Data
Bus, CRRWR =0
--
....,
CSIIA19
asCS I
.
READ CYCLE
32
32-
/.X~
1\
(13
)~
00(
15
~
STABLE INPUT
6
AO/ADO
A15/AD15-~
as AO-A15
PCO-PC2
CSIIA19as
Multiplexed
Inputs
~
STABLE INPUT
~
-X
tx
IXXX XXX
STABLE INPUT
14
~~
-...
IXXX XXX
STABLE INPUT
32-
lXXX IXXXX
I'(XXX IXXXX
I'(XXXXXXX ~XXXX DCXXXXX
-.,
00)
-.,
1\."IJj
PBO-PB7
(High Byte )...J
2
DATA VALID
~
DATA VALID
v
~
DATA
IN
/
1;-
~
1\
17
1v
1\
D2000
V.
V
NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods of time may affect device reliability.
Operating
Range
Recommended
Operating
Conditions
Range
Temperature
Vee
Commercial
0° C to +70°C
3.0 Vto 5.5 V
Symbol
Conditions
Parameter
vee
Supply Voltage
VIH
High-level Input Voltage Vee
VIL
All Speeds
Low-level Input Voltage
* Before 8/1/1 993.
** After 8/1/1993.
May, 1993
204
Vee
= 3.0 V to 5.5 V
=3.0 V to 5.5 V
Min
Typ
Max
Unit
3.0
3.3
5.5
V
Vee + 0.5
V
0.2 Vee *
V
0.3 Vee **
V
0.7 Vee
-0.5
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD311L
3-volt single-chip microcontroller peripheral
DC
CMiser= 1
Subtract:**
Characteristics
Symbol
Parameter
Output Low
Voltage
VOL
Output High
Voltage
VOH
Vcc Standby
Current (CMOS)
(Notes 2 and 3)
IS81
Conditions
Min Typ Max Min Typ Max Unit
IOL = 20 JJA
Vce=3.0V
0.01
0.1
V
IOL = 4 rnA
Vcc=3.0V
0.15
0.4
V
IOH = -20 JJA
Vcc=3.0V
2.9
2.99
V
IOH = -1 rnA
Vce=3.0V
2.4
2.6
V
10*
25*
1**
5**
JJA
Vcc=3.3V
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
Vce=3.3V
(Note 5)
6
12
3.0
5
rnA
Vcc=3.3V
(Note 6)
10
20
3.0
5
rnA
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
Vcc=3.3V
(Note 5)
6
12
2
3
rnA
Vce=3.3V
(Note 6)
10
20
2
3
Active Current
(CMOS) (SRAM
Block Selected)
(Notes 2 and 5)
Vce = 3.3 V
(Note 5)
20
33
5
8
rnA
Vce=3.3V
(Note 6)
24
40
5
8
rnA
III
Input Leakage
Current
VIN = Vcc
orGND
-1
±0.1
1
JJA
ILO
Output Leakage
Current
VOUT = Vce
orGND
-10
±5
10
JJA
Icc1
Icc2
Ice3
CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
CSI/A19 is high and the part is in a power-down configuration mode.
Add 2.0 mA/MHz for AC power component (power = AC + DC).
Ten (10) PAD product terms active. (Add 190 IlA per product term, typical, or 240 IlA
per product term maximum.)
6. Forty (40) PAD product terms active.
NOTES: 2.
3.
4.
5.
* Before 8/1/93.
** After 8/1/93.
May, 1993
205
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
Figure 1.
Normalized
Supply Current
PSD311 L
2.5
/
rB.
Supply Voltage
2.25
a:
w
:::i
Q.
L
2.0
~
;:)
::E
z~
w
a:
a:
;:)
)
1.75
1.5
0
>
..J
1.25
Q.
Q.
.I
;:)
en
1.0
V
/
V
V
/
IV:
I
0.75
2.5
3.0 3.3 3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
The Normalized Supply Current vs. Supply
Voltage graph shown above, provides a
multiplier for any ISB or Icc value in the D.C.
Characteristics table. As noted, it is
normalized for a supply voltage of 3.3 volts.
Since device characterization data shows
very little supply current difference
over speed, the multiplier includes all
May, 1993
206
frequencies of operation from standby to
quiescent to full dynamic speed. To use,
calculate the supply current at 3.3 volts for
your operation configuration using the D.C.
Characteristics table. Then multiply that
value by the Supply Current Multiplier for
the supply voltage actually being used.
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD311L
3-volt single-chip microcontroller peripheral
AC
Characterlstlcs,l)
(See Timing
Diagrams)
-30
-25
CMiser= 1
Symbol
Min Max Min Max
Parameter
T1
ALE or AS Pulse Width
75
80
Unit
ns
T2
Address Set-up Time
30
35
T3
Address Hold Time
30
35
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
ns
T5
ALE Valid to Data Valid
250
300
25
ns
T6
Address Valid to Data Valid
250
300
25
ns
T7
CSI Active to Data Valid
275
325
30
ns
T8
Leading Edge of Read
to Data Valid
90
95
0
ns
0
ns
0
ns
T9
Read Data Hold Time
T10
Trailing Edge of Read
to Data High-Z
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
ns
0
0
50
55
40
45
ns
RD, E, PSEN, DS Pulse Width
100
110
0
ns
WR Pulse Width
90
95
0
ns
T13
Trailing Edge of Write or Read
to Leading Edge of ALE or AS
0
0
0
ns
T14
Address Valid to Trailing
Edge of Write
250
300
0
ns
T15
CSI Active to Trailing Edge
of Write
275
375
0
ns
T16
Write Data Set-up Time
60
65
0
ns
T17
Write Data Hold Time
25
30
0
ns
T18
Port to Data Out Valid
Propagation Delay
0
ns
T19
Port Input Hold Time
T20
Trailing Edge of Write to Port
Output Valid
T12
T12A
70
75
0
0
0
ns
100
110
0
ns
T21
ADi or Control to CSOi Valid
6
80
5
85
0
ns
T22
ADi or Control to CSOi Invalid
4
80
4
85
0
ns
T23
Track Mode Address Propagation
Delay: CSADOUT1 Already True
70
75
0
ns
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes True
During ALE or AS
100
110
0
ns
T23A
NOTE: 8. These AC Characteristics are for Vee = 3.0 - 3.6V.
May. 1993
Add:**
207
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
AC
Characteristics
(Cont.) ,
PSD311L
·25
Symbol
·30
Min Max Min Max
Parameter
eMiser= 1
Add:** Unit
T24
Track Mode Trailing Edge of ALE
or AS to Address High-Z
60
65
0
ns
T25
Track Mode Read Propagation
Delay
70
75
0
ns
T26
Track Mode Read Hold Time
T27
Track Mode Write Cycle,
Data Propagation Delay
T28
Track Mode Write Cycle,
Write to Data Propagation Delay
T29
Hold Time of Port A Valid
During Write CSOi Trailing Edge
4
T30
CSI Active to CSOi Active
9
110
T31
CSllnactive to CSOi Inactive
9
110
T32
Direct PAD Input as Hold Time
24
30
T33
R/W Active to E or OS Start
60
10
70
10
60
7
80
7
75
ns
65
0
ns
85
0
ns
0
ns
4
8
120
0
ns
8
120
0
ns
0
ns
65
0
ns
T34
E or OS End to RIW
60
65
0
ns
T35
AS Inactive to E high
40
45
0
ns
T36
Address to Leading Edge of Write
50
60
0
ns
NOTES: 9. AOi = any address line.
10. CSOi = any of the chip-select output signals coming through Port B (CSo-CS7) or
through Port C (CS8-CS10).
11. Oirect PAO '!!!put = any ofJ!le following direct PAO input lines: CSI/A19 as transparent
A 19, RO/E/OS, WR or RIW, transparent PCo-PC2, ALE (or AS).
12. Control signals RO/E/OS or WR or RIW.
** After 8/111993.
MaY,1993
208
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
Figure 2.
AC Testing
Input/Output
Waveform
PSD311L
O.9V:=x"--__~'c---...J
Figure 3.
AC Testing
Load Circuit
..,...
2.0V
:>~
~
DEVICE
UNDER
TEST
I
- - - C L =30pF
_
Figure 4.
The Reset
Cycle (RESET)
VIL
(INCLUDING
SCOPEANDJIG
CAPACITANCE)
1---------.....
. ..
500 ns
RESET LOW
May, 1993
4000
500ns
RESET HIGH
209
PART
OPERATIONAL
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD311L
FigureS.
Timing of '-Bit
Multiplexed
AddreSS/Data
Bus, CRRWR = 0
-
.....
READ CYCLE
......
....,
CSIIA19
asCSI
32
~
32-
/,,~
~
I'(XX XXX
7
-
15
32-
Direct
PAD Input
(13)
Multiplexed (14)
Inputs
~~
I
Active Low
ALE
m
.
~h
3
,'. f--+
ADDRESS B
2
~
•
>-
~
1/ )OC\
161-
~r
~
4
'-~
13
8
--.J
-
/
'f
3
~
1
DATA
IN
14
XX) -(
DATA VALID
~
XXXX IXXXX
10
~ ADDRESS A ~
2
Active High
ALE
14
IX XXXXXXXXXXXX XXXXXX
6
XXX XXX
STABLE INPUT
I..
6
-X~
AO/ADOA7/AD7
XX P<
STABLE INPUT
-..
WRITE CYCLE
.....
~
11
rL
L!
12
RD/E as RD
J
5
36
,
J
~
,
WRNppor
RWasWR
Anyo
f
PAO-PA7
as I/O Pin
18
X) XXXXXXXXX
I
Any 0 f ,
PBO-PB7 X)
I
as I/O Pin
Any of
PAO-PA7 Pins
as Address
Outputs
XXXXXXXXX
A
) XXXXXXXXXXXXXXXX) XX
OUTPUT
INPUT
~XXXXXXXXXXXXXXXXXXX
OUTPUT
23
ADDRESS A
See referenced notes on page 216.
May, 1993
If
INPUT
23
J
13
~
19
I-
-
-
210
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD311L
FlgureB.
Timing of 8-BIt
Multiplexed
Address/Data
Bus, CRRWR = 1
...,
CSI/A19
asCSI
-
..
READ CYCLE
p
32
32-
Multiplexed
Inputs
(14)
] ~
I
-
Active Low
AS
6
~
I
DATA VALID
3
XX)
-
-
...=-.
,
35
13
161-
J
35
-
~
36
34
-
rL
L!
j~~
33
33
WRNppor
[~ r
\
5
AMi as AMi
1/ XX
3
34
8
RD/E as E
}-~
~
1
~
DATA
IN
ADDRESS B
2
1'r4- -+
.J
XXXX XXXX
14
~
r~
1 ~
~
14
10
~XX'J.,
XXX XXX
STABLE INPUT
xxxxxxxx ocxxxx xXXXXX
ADDRESSA J
XXX
-
32-
~~
6
2
Active High
AS
.(xx
15
STABLE INPUT
-'i.J
AO/ADOA7/AD7
~
llA\
\
7
Direct (13)
PAD Input
..
WRITE CYCLE
.......
12
12
) XXXXXX
13
~
XXXXX
18
19
~
Any of
PAO-PA7
as I/O Pin
,'k) xxxxxxxxx
INPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
Any of
PBO-PB7
as I/O Pin
,~) XXXXXXXXX
INPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
Any of
PAO-PA7 Pins
as Address
Outputs
23
23
i+-
l-
---.J
ADDRESS A
J~
See referenced notes on page 216.
May. 1993
211
ADDRESS B
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt s~ngle-chip microcontroller peripheral
PSD311L
Figure 7.
Timing of '-Bit
Data NonMultiplexed
Address/Data
Bus, CRRWR = 0
--....
-,
CSVA19
asCS I
...
READ CYCLE
32
-
1_
Direct (13
l~
AO-A15
00\
STABLE INPUT
I.2000
V
ESD Protection
NOTE:
Operating
Range
Recommended
Operating
CondltloDS
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
Range
Temperature
Vee
Commercial
0° C to +70°C
3.0 V to 5.5 V
Symbol
Parameter
Conditions
vce
Supply Voltage
VIH
High-level Input Voltage Vee = 3.0 V to 5.5 V
VIL
Low-level Input Voltage
All Speeds
* Before 8/1/1993.
** After 8/1/1993.
May, 1993
Unit
222
Vee = 3.0 V to 5.5 V
Min
Typ
3.0
3.3
0.7 Vee
-0.5
Max
Unit
5.5
V
Vee + 0.5
V
0.2 Vee *
V
0.3 Vee **
V
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD302L
DC
CMiser= 1
Subtract:
Characteristics
Symbol
Parameter
Output Low
Voltage
VOL
Conditions
IOL = 20 ~
Vee = 3.0 V
0.01
0.1
V
IOL = 4 rnA
Vee=3.0V
0.15
0.4
V
IOH=-20~
Output High
Voltage
VOH
Vee Standby
Current (CMOS)
(Notes 2 and 3)
IS81
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
lec1
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
lec2
Active Current
(CMOS) (SRAM
Block Selected)
(Notes 2 and 5)
Ice3
Min Typ Max Min Typ Max Unit
Vee= 3.0 V
IOH =-1 rnA
Vee = 3.0 V
2.9
2.99
V
2.4
2.6
V
10*
25*
1 **
5**
Vee=3.3V
(Note 5)
6
12
3.0
5
rnA
Vcc=3.3V
(Note 6)
1()
20
3.0
5
rnA
Vce=3.3V
(Notes 5
and 7)
6
12
0
0
rnA
Vce = 3.3 V
(Note 6
and 7)
10
20
0
0
rnA
Vee = 3.3 V
(Note 5
and 7)
20
33
3
5
rnA
Vec = 3.3 V
(Notes 6
and 7)
24
40
3
5
rnA
~
Vee=3.3V
III
Input Leakage
Current
V 1N = Vec
orGND
-1
±0.1
1
~
ILO
Output Leakage
Current
V OUT = Vce
orGND
-10
±5
10
~
CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
CSIIA19 is high and the part is in a power-down co"nfiguration mode.
Add 2.0 mA/MHz for AC power component (power = AC + DC).
Ten (10) PAD product terms active. (Add 190 ~ per product term, typical, or 240 ~
per product term maximum.)
6. Forty (40) PAD product terms active.
7. In 8-bit mode, an additional 3 mA Max. can be saved under CMiser.
NOTES: 2.
3.
4.
5.
* Before 8/1/1993.
** After 8/1/1993.
May, 1993
223
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
Figure 1.
Normalized
Supply Cu«ent
PSD302L
2.5
/
r5.
Supply Voltage
2.25
IE:
w
::::i
D..
i=
2.0
..J
::l
:::E
I-
/
1.75
zW
IE:
IE:
1.5
/
::l
0
> 1.25
D..
..J
D..
::l
fJ)
J
1.0
/
/
V
/
V
./:
I
0.75
2.5
3.0 3.3 3.5
4.0
4.5
5.0
5.5
6.0
SUPPLYVOLTAGE (V)
The Normalized Supply Current vs. Supply
Voltage graph shown above, provides a
multiplier for any ISB or Icc value in the
D.C. Characteristics table. As noted, it is
normalized for a supply voltage of 3.3 volts.
Since device characterization data shows
very little supply current difference
over speed, the multiplier includes all
May. 1993
224
frequencies of operation from standby to
quiescent to full dynamic speed. To use,
calculate the supply current at 3.3 volts for
your operation configuration using the D.C.
Characteristics table. Then multiply that
value by the Supply Current Multiplier for
the supply voltage actually being used.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD302L
AC
Characterlstlcs(8)
(See Timing
Diagrams)
-25
Symbol
Parameter
-30
Min Max Min Max
T1
ALE or AS Pulse Width
75
80
T2
Address Set-up Time
30
35
T3
Address Hold Time
30
35
0,
ns
T4
Leading Edge of Read
to Data Active
0
0
0
ns
T5
ALE Valid to Data Valid
250
300
25
ns
T6
Address Valid to Data Valid
250
300
25
ns
T7
CSI Active to Data Valid
275
325
30
ns
T8
Leading Edge of Read
to Data Valid
90
95
0
ns
0
ns
0
ns
ns
ns
T9
Read Data Hold Time
T10
Trailing Edge of Read
to Data High-Z
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
T12
RD, E, PSEN, DS Pulse Width
100
110
0
ns
WR Pulse Width
90
95
0
ns
0
0
0
ns
T12A
0
0
50
55
40
45
ns
T13
Trailing Edge of Write or Read
to Leading Edge of ALE or AS
T14
Address Valid to Trailing
Edge of Write
250
300
0
ns
T15
CSI Active to Trailing Edge
of Write
275
375
0
ns
T16
Write Data Set-up Time
60
65
0
ns
T17
Write Data Hold Time
25
30
0
ns
T18
Port to Data Out Valid
Propagation Delay
0
ns
70
75
T19
Port Input Hold Time
T20
Trailing Edge of Write to Port
Output Valid
T21
ADi or Control to CSOi Valid
6
80
5
T22
ADi or Control to CSOi Invalid
4
80
4
T23
Track Mode Address Propagation
Delay: CSADOUT1 Already True
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes True
During ALE or AS
T23A
0
0
0
ns
100
110
0
ns
85
0
ns
85
0
ns
70
75
0
ns
100
110
0
ns
NOTE: 8. These AC Characteristics are for Vee = 3.0 - 3.6V.
May, 1993
CMiser= 1
Add:
Unit
225
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD302L
3-volt single-chip microcontroller peripheral
AC
Character/sties
(Cont.)
·25
Symbol
Parameter
·30
Min Max Min Max
CMiser= 1
Add:
Unit
T24
Track Mode Trailing Edge of ALE
or AS to Address High-Z
60
65
0
ns
T25
Track Mode Read Propagation
Delay
70
75
0
ns
T26
Track Mode Read Hold Time
T27
Track Mode Write Cycle,
Data Propagation Delay
T28
Track Mode Write Cycle,
Write to Data Propagation Delay
7
T29
Hold Time of Port A Valid
During Write CSOi Trailing Edge
4
T30
CSI Active to CSOi Active
9
110
8
T31
CSllnactive to CSOi Inactive
9
110
8
T32
Direct PAD Input as Hold Time
24
T33
R/W Active to E or OS Start
60
T34
E or OS End to R/W
10
70
10
75
ns
65
0
ns
85
0
ns
0
ns
120
0
ns
120
0
ns
30
0
ns
65
0
ns
60
65
0
ns
60
80
7
4
T35
AS Inactive to E high
40
45
0
ns
T36
Address to Leading Edge of Write
50
60
0
ns
NOTES: 9. AOi = any address line.
10. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or
through Port C (CSS-CS10).
11. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent
A19, RO/E/OS, WR or RiW, transparent PCO-PC2, ALE (or AS).
12. Control signals RO/E/OS or WR or RIW.
May, 1993
226
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD302L
3-volt single-chip microcontroller peripheral
Figure 2.
AC Testing
Input/Output
Waveform
Figure 3.
AC Testing
Load Circuit
~~
~
DEVICE
UNDER
TEST
I
......... C L =30pF
_
-
Figure 4.
The Reset
Cycle (RESET)
4000
(INCLUDING
SCOPEANDJIG
CAPACITANCE)
VIH
Vil
..
500ns
500 ns
to
RESET LOW
May. 1993
..
RESET HIGH
227
..
PART
OPERATIONAL
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD302L
Figure 5.
Timing of '-Bit
Multiplexed
Address/Data
Bus, CRRWR = 0
-
.....,
CSI/A19
as CSI
-.. ...
READ CYCLE
32
32-
1-
I'(XX XXX
A"~
~
7
Direct (13)
PAD Input
Multiplexed (14)
Inputs
AO/ADOA7/AD7
Active High
ALE
Active Low
ALE
~~
I
15
-
32- I-
~~
STABLE INPUT
6
14
~
IXXXXXXXX OCXXXX XXXXXX
DeXXX XXXX
10
6
IXXX XXX
STABLE INPUT
I
.x;~
-
... -
WRITE CYCLE
.....
-
DATA
IN
14
/
'( ADDRESSA ~
2
~
3
•
rh
,'. --.
1
~~ DATA VALID ~ I-~
2
~
~
h
'\
3
4
13
8
~
'" YX.'\
17
161-
1 1\
~
\..---'
~"
\
ADDRESS B
1-1
,-
J
11
'f
'-
~
LI
12
RD/E/DS as RD
5
,
BHE/PSEN
as PSEN
J
WRNppor
RWasWR
Any 0
f
PAO-PA7
as I/O Pin
'f
13
12A
,..--.
•
X) XXXXXXXXX
I
XXXXXXXXX
19
.---...
I
XXXXXXXXXXXXXXXX XX
OUTPUT
INPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
23
23
l-
-
J
2£..
INPUT
,
iADDRESS A
J\
See referenced notes on page 238.
May, 1993
36
•
\-.....J
18
Anyo f ,
PBO-PB7 X)
I
as I/O Pin
Anyof
PAO-PA7 Pins
as Address
Outputs
I
\
228
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD302L
Figure 6.
Timing of 8-Blt
Multiplexed
Address/Data
Bus, CRRWR = 1
...,
CSI/A19
asCSI
. ....-
READ CYCLE
.-
...
11XX XXX
7
Direct (13)
PAD Input
Multiplexed (14)
Inputs
]: ~
15
6
1,1\
AO/ADOA7/AD7
Active Low
AS
...
~ro
ADDRESSA J
J
2
Active High
AS
STABLE INPUT
14
D(XXX IXXXX
IXXXXXXXX !XXXXX OCXXXXX
6
3
J~ r--+
1
XXj _v1\
35
13
~
36
5
12
RD/E/DS as DS
,
1-
Ir-
'XXXXX
19
~
Xl IXXXXXXXXX
INPUT
)IXXXXXXXXXXXXXXXXXXX
OUTPUT
X) IXXXXXXXXX
INPUT
)IXXXXXXXXXXXXXXXXXXX
OUTPUT
Any of
PBO-PB7 I
as 1/0 Pin
23
23
- l!::::
-
IADDRESS A
J
See referenced notes on page 238.
May, 1993
Lr
1""-""1\
12
18
Any of
PAO-PA7 Pins
as Address
Outputs
~
34
33
~
JIXXXXXX
Any of \
PAO-PA7
I
as 1/0 Pin
,
iL
~ 13
33 1\
I~
WRNppor
RiWas RiW
XX
35
34
8
RD/E/DS as E
-
-
~
~r
J
16-
.!.
,
1\..r---1
/
3
h
I\.
DATA
~
ADDRESSB
~
~
r~
.
14
10
DATA VALID
IIXXX XXX
32-
~~
STABLE INPUT
I
-
I+-
32-
)~I\
1\
..
WRITE CYCLE
~
32
229
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
PSD302L
3-volt single-chip microcontroller peripheral
Figure 7.
Timing of 16-BIt Multiplexed
Address/Data BusJ CRRWR =0
-..
....,
CSI/A19
asCSI
..
READ CYCLE
r"
..-.
32
WRITE CYCLE
~
J ~~
\
-
32-
'XX XXXX
7
15
~
32Direct (13)
PAD Input
~~
~
~
STABLE INPUT
6
~
XXX )(XXX
STABLE INPUT
14
I
Multiplexed (14)
Inputs
X\
XXXX IXXXX
IXXXXXXXX XXXXX XXXXXX
14
6
1)\
1,( XXX XXXX
I'(XXXXXXX XXXXX XXXXXX
10
AO/ADOA15/AD15
~
ADDRESS A
2
Active High
ALE
Active Low
ALE
;m DATA VALID XX -(
j
3
rh
I+J
8
~
16~
J
11
.J
~
"L
J
12
13
12A
1-+---+
18
'~
19
Any 0 f \
f--
~
}) XXXXXXXXX
INPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
X) XXXXXXXXX
INPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
Any 0
f
PBO-PB7
I
as 1/0 Pin
23
23
t--
Any of
-
J
IADDRESS A
ADDRESS B
See referenced notes on page 238.
MaY,1993
'tf..
~ ,-
~
WR/Vpp 0 r
RiW asWR
PAO-PA7 Pins
as Address
Outputs
J~
1
36
PAO-PA7
as 1/0 Pin
/
13
5
,
RD/E/DS as RD
>-
3
h
1
... ~
\..--l
ADDRESS B
2
~
4
,'
DATA
230
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD302L
FigureS.
Timing of 16-BIt Multiplexed
Address/Data Bus, CRRWR = 1
-
.....,
CSI/A19
asCS I
....-
~
32
7
Direct
PAD Input
(13)
]: ~
BHEIPSEN
asBHE
~
6
-X~
.--
32-
XX XXXX
-
15
txI.
32-
XXX X.XXX
STABLE INPUT
14
~
XXXXXXXX XXXXX OCXXXXX
XXXX !XXXX
14
6
~~
-
WRITE CYCLE
'"
,'''\
STABLE INPUT
I
Multiplexed (14)
Inputs
-. ....
READ CYCLE
.(XXX IXXXX
,(XXXXXXX XXXXX X.XXXXX
DATA
10
),N
AO/ADO
A15/AD15
2
Active High
AS
Active Low
AS
~
ADDRESS A J
DATA VALID
'tIJ 1-\
-
~
3
'r---;
1 \
I:. --.
}- '(I\. 1/ "!:A \
ADDRESS B
2
3
161-
~
J 1 ~
~r-
l\,J
I
~
,
35
~--
~
13
'-
33
34
8
RD/EIDS as E
35
r--I
~
34
5
12
RD/EIDS as DS
J
~
WRNppor
RNi as RNi
XXXXX
X XXXXXX
18
Any 0 f \
PAO-PA7 }.
as I/O Pin
19
XXXXXXXXX
INPUT
X' XXXXXXXXX
INPUT
Any 0 f ~
PBO-PB7 I
as I/O Pin
-
l!::! "(
r---11\.
~ 13
~
-
~
XXXXXXXXXXXXXXXXXXX
)(XXXXXXXXXXXXXXXXXXX
23
Any 0 f PAO-PA7 Pins
as Address
Outputs
23
,
IADDRESS A
J~
See referenced notes on page 238.
May, 1993
36
231
ADDRESS B
If
OUTPUT
OUTPUT
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD302L
3-volt single-chip microcontroller peripheral
Figure 9.
Timing of 8-BIt
Data NORMultiplexed
Address/Data
Bus, CRRWR = 0
-
CSI/A19
asCS I
-
..
READ CYCLE
~
32
I...
~Jr~~
1\
-
7
Direct (13
PAD Input
):x:
~
~
STABLE INPUT
~ 00
STABLE INPUT
~
Multiplexed (14 )~
Inputs
Active High
ALE
Active Low
ALE
~.
~~
.XXX
....,
:m
....J
DATA VALID
14
v-h
1 1\
J~ 1--+
,
~~
14
3
....
-
~
1-
DATA
IN
II' 'A/...'
17
1-1
~
13
-~
...... 16
1 ~
~
8
IXXX .XXX
XXXX XXXX
~
4
•
STABLE INPUT
'tIJ
~
3
IXXX XXX
STABLE INPUT
32--.
10
6
2
.... ..
I~XX
IXXXXXXXX XXXXX XXXXXX
-
PAO-PA7
32--.
15
6
AO/ADOA151AD15
as AO-A15
.
WRITE CYCLE
I+-JV- ~
,
~
11
Lr
12
RD/E/DS as RD
WRNpp 0 r
RiW asWR
X) iXXXXXXXXX
I
19
tE.
IXXXXXXXXXXXXXXXXXXX
INPUT
See referenced notes on page 238.
May, 1993
13
12A I-~
'~
5
18
Any 0 f
PBO-PB7
as I/O Pin
36
J
232
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD302L
Figure 10.
Timing of 8-Blt
Data NonMultiplexed
Address/Data
Bus, CRRWR = 1
...
READ CYCLE
.....
~
.....,
CSIIA19
asCS I
....
32
32 ....
/Xi\
~
AOIADO
A15/AD15
as AO-A15
)
Multiplexed (14
Inputs
~
15
STABLE INPUT
6
~~
STABLE INPUT
~
X~
Active High
ALE
Active Low
ALE
STABLE INPUT
)00 ~
STABLE INPUT
m
2
DATA VALID
,
~~
\
~
h
4
35
16 -
36
12
Any of
PBO-PB7
as 1/0 Pin
J
~
~
j
Lr
~ 34
\12
,
13
XXXXX
18
19
\
!-
233
r
~
XXXXXXXXXXXXXXXXXXX
INPUT
See referenced notes on page 238.
May, 1993
-
j\........)
X XXXXXX
,X) XXXXXXXXX
-' r
~
-,
-
Xl--
,
33
~
5
RiW as Riii
1/
35
34
8
WR/Vpp 0 r
~
13
RD/E/DS as E
ROlE/OS as OS
XXX
171
3
,~
'f
~XX
DATA
IN
'f.:X
1 1\
If+ ~
XXX
r/.Xxx XXXX
14
~
3
~h
~XX
14
32 .....
10
--,
-'
XX ~
IXXXXXXXX XXX XX XXX XXX
6
PAO-PA7
---
~
!.-
ADDRESS
J
I....!-.
~
4
--'
,
I
WRITTEN
DATA
~
32
12
,
~~
1\
"
~
I
27
12
11
24
00(
~
23
ADROUT)
24
---('f:;f;X
DATA IN
f+-
.XY»-KXX ADROUT'
~
23 ~
J
1\
«X
DATA
OUT
29
~
~
CSOi
J
(15,18)
See referenced notes on page 238.
May, 1993
237
n.
V
f4-
,
WRNppor
RiWasWR
-
X
3
~~
-h
!::.jm..
I
2
1
~ ---+
~
STABLE INPUT
26
'r ~
RD/E/DS as RD
PAO-PA7
xxxxxxxxxxxxx XXXX
STABLE INPUT
32-..
1\
I
2
-
WRITE CYCLE
.....
"
STABLE INPUT
AO/ADOA7/AD7
ALE
..
~
READ CYCLE
y::jJ-
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD302L
Figure 15. Port A as ADO - AD7 Timing
(Track Mode), CRRWR = 1
..
Direct
PAD Input
(13,16)
Multiplexed
PAD Inputs
(17,19)
..... .......
READ CYCLE
.....
~
-
STABLE INPUT
~
--
STABLE INPUT
2
AO/ADOA7/AD7
32-
IXXXXXXXXXXXXX XXXXXX
3
- ro-
~
:~
ADDRESS
26
STABLE INPUT
XXXXXXX
X
3
2
I
DATA VALID
~
ADDRESS
WRITTEN
DATA
I-
32AS
or AS
'r -,
1
- ~I+ ---+-
-h
~
~~
~
J
-
I....!-.
,
35
33
'(
RDIE/DS as DS
II
X X) IXXXX
-
(XX ADROUlj HXXX
-.. 23
J XX
23
r-
ADROUT
~
..... 27 ....
~
DATA
OUT
'ttr-
~
28
~
-
(15,18)
Notes for
Timing
Diagrams
XXX)- -2000
V
ESD Protection
NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
Operating
Range
Recommended
Operating
Conditions
Range
Temperature
Vee
Commercial
0° C to +70°C
3.0 Vto 5.5 V
Parameter
Symbol
Conditions
vee
Supply Voltage
VIH
High-level Input Voltage Vee
VIL·
All Speeds
Low-level Input Voltage
* Before 8/111993 .
•* After 8/1/1993.
May, 1993
244
Vee
=3.0 V to 5.5 V
= 3.0 Vto 5.5 V
Min
Typ
Max
Unit
3.0
3.3
5.5
V
Vee + 0.5
V
0.2 Vee•
V
.*
V
0.7 Vee
-0.5
0.3 Vee
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD312L
DC
CMiser= 1
Subtract:
Characteristics
Symbol
Parameter
Output Low
Voltage
VOL
Output High
Voltage
VOH
Vee Standby
Current (CMOS)
(Notes 2 and 3)
ISB1
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
lee1
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
Icc2
Active Current
(CMOS) (SRAM
Block Selected)
(Notes 2 and 5)
Ice3
Conditions
Min Typ Max Min Typ Max Unit
IOL = 20 JlA
Vee=3.0V
0.01
0.1
V
IOL=4 mA
Vee = 3.0 V
0.15
0.4
V
IOH = -20 JlA
Vee = 3.0 V
2.9
2.99
V
IOH =-1 mA
Vee = 3.0 V
2.4
2.6
V
10*
25*
1**
5**
Vee = 3.3 V
(Note 5)
6
12
3.0
5
mA
Vee = 3.3 V
(Note 6)
10
20
3.0
5
rnA
Vee=3.3V
(Note 5)
6
12
2
3
mA
Vee = 3.3 V
(Note 6)
10
20
2
3
rnA
Vee = 3.3 V
(Note 5)
20
33
5
8
mA
Vee = 3.3 V
(Note 6)
24
40
5
8
rnA
-1
±0.1
1
JlA
-10
±5
10
JlA
Vee = 3.3 V
III
Input Leakage
Current
V1N = Vee
orGND
ILo
Output Leakage
Current
VOUT = Vee
orGND
JlA
CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
CSI/A19 is high and the part is in a power-down configuration mode.
Add 2.0 mA/MHz for AC power component (power"" AC + DC).
Ten (10) PAD product terms active. (Add 190 JlA per product term, typical, or 240 JlA
per product term maximum.)
6. Forty (40) PAD product terms active.
NOTES: 2.
3.
4.
5.
* Before 8/1/1993.
** After 8/1/1993.
May, 1993
245
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
Figure 1.
Normalized
Supply Cuwent
PSD312L
2.5
rB.
Supply Voltage
2.25
a:
w
:J
D.
i=
...J
2.0
:E
1.75
/
:::)
~
)
zw
a:
a:
1.5
:::)
0
>
...J
D.
D.
1.25
/
:::)
en
1.0
/
I
/
/
V
/
(:
I
0.75
2.5
3.0 3.3 3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
The Normalized Supply Current vs. Supply
Voltage graph shown above, provides a
multiplier for any ISB or Icc value in the
D.C. Characteristics table. As noted, it is
normalized for a supply voltage of 3.3 volts.
Since device characterization data shows
very little supply current difference
over speed, the multiplier includes all
May. 1993
246
frequencies of operation from standby to
quiescent to full dynamic speed. To use,
calculate the supply current at 3.3 volts for
your operation configuration using the D.C.
Characteristics table. Then multiply that
value by the Supply Current Multiplier for
the supply voltage actually being used.
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
PSD312L
AC
Characterlstlcs(8)
(See Timing
Diagrams)
·25
Symbol
·30
Min Max Min Max
Parameter
T1
ALE or AS Pulse Width
75
80
ns
T2
Address Set-up lime
30
35
ns
T3
Address Hold lime
30
35
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
ns
T5
ALE Valid to Data Valid
250
300
25
ns
T6
Address Valid to Data Valid
250
300
25
ns
T7
CSI Active to Data Valid
275
325
30
ns
T8
Leading Edge of Read
to Data Valid
90
95
0
ns
0
ns
0
ns
T9
Read Data Hold Time
T10
Trailing Edge of Read
to Data High-Z
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
T12
RD, E, PSEN, OS Pulse Width
100
110
0
ns
WR Pulse Width
90
95
0
ns
T13
Trailing Edge of Write or Read
to Leading Edge of ALE or AS
0
0
0
ns
T14
Address Valid to Trailing
Edge of Write
250
300
0
ns
T15
CSI Active to Trailing Edge
of Write
275
375
0
ns
T12A
0
0
50
55
40
45
ns
T16
Write Data Set-up Time
60
65
0
ns
T17
Write Data Hold Time
25
30
0
ns
T18
Port to Data Out Valid
Propagation Delay
0
ns
70
·75
T19
Port Input Hold lime
T20
Trailing Edge of Write to Port
Output Valid
T21
ADi or Control to CSOi Valid
6
80
5
T22
ADi or Control to CSOi Invalid
4
80
4
T23
Track Mode Address Propagation
Delay: CSADOUT1 Already True
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes True
During ALE or AS
T23A
0
0
0
ns
100
110
0
ns
85
0
ns
85
0
ns
70
75
0
ns
100
110
0
ns
NOTE: 8. These AC Characteristics are for VCC = 3.0 - 3.6V.
May, 1993
CMiser=1
Unit
Add:
247
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
AC
Character/sties
(Cont.)
PSD312L
·25
Symbol
Palametel
·30
Min Max Min Max
CMisel= 1
Add:
Unit
T24
Track Mode Trailing Edge of ALE
or AS to Address High-Z
60
65
0
ns
T25
Track Mode Read Propagation
Delay
70
75
0
ns
T26
Track Mode Read Hold Time
T27
Track Mode Write Cycle,
Data Propagation Delay
T28
Track Mode Write Cycle,
Write to Data Propagation Delay
T29
Hold Time of Port A Valid
During Write CSOi Trailing Edge
4
T30
CSI Active to CSOi Active
9
110
8
T31
CSllnactive to CSOi Inactive
9
110
8
T32
Direct PAD Input as Hold Time
24
T33
R/W Active to E or DS Start
T34
E or DS End to RIW
T35
T36
10
70
10
75
ns
65
0
ns
85
0
ns
0
ns
120
0
ns
120
0
ns
30
0
ns
60
65
0
ns
60
65
0
ns
AS Inactive to E high
40
45
0
ns
Address to Leading Edge of Write
50
60
0
ns
60
7
80
7
4
NOTES: 9. ADi = any address line.
10. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or
through Port C (CS8-CS1 0).
11. Direct PAD '!!!put = any ofJ!le following direct PAD input lines: CSI/A19 as transparent
A 19, RO/E/OS, WR or RIW, transparent PCo-PC2, ALE (or AS).
12. Control signals RO/E/OS or WR or RIW.
May, 1993
248
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
PSD312L
Figure 2.
AC Testing
Input/Output
Waveform
Figure 3.
AC Testing
Load Circuit
2.OV
-~
DEVICE
UNDER
TEST
--- C L =30pF
I
(INCLUDING
SCOPE AND JIG
":' CAPACITANCE)
Figure 4.
The Reset
Cycle {RESET}
V1L ~-----------
SOOns
••
RESET HIGH
RESET LOW
May, 1993
SOOns
249
PART
OPERATIONAL
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD312L
Flgure5.
Timing of '-Bit
Multiplexed
AddreSS/Data
Bus, CRRWR =0
..
READ CYCLE
-~
r
WRITE CYCLE
....
32
~
CSI/A19
asCSI
32-
/,,~
\
(13)
~ 00\
15
(14)
6
Active Low
ALE
,
(xXX xxxx
ADDRESS B
-
3
>-
.2.
1--+
....
'-I--i
4
13
8
,
/
\
3
16~
~
1
DATA
;,N
14
~XX'J.. DATA VALID ~ - \
2
~
ADDRESS A )
rh
I.
~XX
'I\A
~ rJ
11
\....
--'
12
RDIE/DS as RD
5
BHEIPSEN
as PSEN
XXX
14
10
6
2
Active High
ALE
~
STABLE INPUT
XXXXXXXX XXXXX OCXXXXX
~
~
32-
I
-X
AO/ADOA7/AD7
XX
STABLE INPUT
I
Multiplexed
Inputs
-
'(XX XXX
7
Direct
PAD Input
~
-
'--'
J
,
WRNppor
RWasWR
..
36
~
12
...-....
,
13
I
\......-J
18
19
~
~
Any af \
PAO-PA7
as 1/0 Pin
I·J
XXXXXXXXX
INPUT
XXXXXXXXXXXXXXXX) XX
OUTPUT
Any af \
PBO-PB7 X)
as 1/0 Pin
XXXXXXXXX
INPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
,
Anyof
PAO-PA7 Pins
as Address
Outputs
-
23
23
I-
----I
ADDRESS A
J\
See referenced notes on page 256.
May, 1993
250
ADDRESS B
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD312L
3-volt single-chip microcontroller peripheral
Figure 6.
Timing of '-Bit
Multiplexed
Address/Data
Bus, CRRWR = 1
..
...,
CSI/A19
asCSI
-.
READ CYCLE
32
32-
AX\
\
Multiplexed
Inputs
(13)
(14)
~
00f
STABLE INPUT
6
XXXX IXXXX
~ro
DATA VALID
3
'tX
-
'r h
1 1\
If+ ~
3
-,
161-
35
\....
13
~
L
F
34
33
I~
34
36
12
,
-
~ 13
J
)XXXXXX
XXXXX
18
~
J
35
8
WR/Vppor
RiWas RiW
~
.!.
,
~~
)-( 1/ "{X L - -
ADDRESS B
-\
2
.......
~
~
~
19
r-
~
I) XXXXXXXXX
INPUT
)(XXXXXXXXXXXXXXXX XX
OUTPUT
X) XXXXXXXXX
INPUT
)(XXXXXXXXXXXXXXXXXXX
OUTPUT
I
Any of
PBO-PB7 I
as I/O Pin
23
.......
_1\
23
.......
ADDRESS A
1\
See referenced notes on page 256.
May, 1993
-
jN
ADDRESSA J
RD/E/DS as DS
PAO-PA7 Pins
as Address
Outputs
DATA
14
10
5
Any of
XXX XXX
I
RD/E/DS as E
Any of
PAO-PA7
as I/O Pin
-
14
XXXXXXXX XXXXX XXXXXX
2
Active Low
AS
32-
~~
6
-X
AO/ADOA7/AD7
Active High
AS
15
STABLE INPUT
+:.
..-KXX
......
23 ~
23
ADROUTJ'
~
{XX
DATA
OUT
~
~
CSOi
I
J
(15,18
See referenced notes on page 256.
May, 1993
X
3
2
26
DATA VALID
.1
32
ALE
~
32-+
STABLE INPUT
X~
....
WRITE CYCLE
.....
255
m-
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD312L
3-volt single-chip microcontroller peripheral
Figure 11. Port A as ADO - AD7 Timing
(Track Mode), CRRWR = 1
..
Direct
PAD Input
(13,16)
Multiplexed
PAD Inputs
(17,19)
...
READ CYCLE
~
~
32-
'f
STABLE INPUT
1\
-
WRITE CYCLE
-
2
)( ~
XXXXXXXXXXXXX XXXXXX
STABLE INPUT
2
AO/ADOA7/AD7
3
ADDRESS
J
~
~
~XX)(
DATA VALID
STABLE INPUT
XXXXXXX
X
3
2
~~
ADDRESS
)- ,
I
WRITIEN
DATA
I-
32AS
_J
~~
tr
1
.. """'
I
~
or AS
-'"
35
\.~
RD/E/DSas E
I...!-.
{\
1\
'f
~
12
35
,
33
J
• 33 ~
I
X Xl( XXXX
WRNppor
RlWasRiW
OC}, ADROUT
-.
23
24
Hm
DATA IN
XXX}- ~
-.
f4-
23
ADROUTj
f4-
~
'r-
XX} .XXXX
34
-. 27 ~
00
DATA
OUT
~
~
~
'I
CSOi
---'
(15,18)
Notes for
Timing
Diagrams
\
-. 34
/
\
24
-
V
12
,
RD/E/DS as OS
PAO-PA7
~
XXX
STABLE INPUT
II\.
13. Direct PAD...J!!put = ~ of the following direct PAD input lines: CSI/A19 as transparent A19,
RD/E/DS, WR or R/W, transparent PCo-PC2, ALE in non-multiplexed modes.
14. Multiplexed inputs: a.!!t.of the following inputs that are latched by the ALE (or AS):
AO/ADO-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PCo-PC2.
15. CSOi = ~ of the chip-select output signals coming through Port B (CSo-CS7) or through
Port C (CS8-CS1 0).
16. CSADOUT1, which internally enables the address transfer to Port A, should be derived only
from direct PAD input signals, otherwise the address propagation delay is slowed down.
17. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively,
can be derived from any combination of direct PAD inputs and multiplexed PAD inputs.
18. The write operation signals are included in the CSOi expression.
19. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in
the multiplexed modes: A11/AD11-A15/AD15, ~I/A19 as ALE dependent A19, ALE dependent
PCo-PC2.
20. CSOi product terms can include any of the PAD input signals except for reset and CSI.
May, 1993
256
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD312L
3-volt single-chip microcontroller peripheral
Pin
Capacltance 21
TA
= 25°C, f = 1 MHz
Symbol
Conditions Typical22 Max Unit
Parameter
CIN
Capacitance (for input pins only)
COUT
Capacitance (for input/output pins)
C vPp
Capacitance (for WRNpp or R/W/vpp)
=0 V
=0 V
Vpp = 0 V
pF
V IN
4
6
VO UT
8
12
pF
18
25
pF
NOTES: 21. This parameter is only sampled and is not 100% tested.
22. Typical values are for TA = 25°C and nominal supply voltages.
Erasure and
Programming
To clear all locations of their programmed
contents, expose the device to ultra-violet
light source. A dosage of 15 W secondlcm 2
is required. This dosage can be obtained
with exposure to a wavelength of 2537 A
and intensity of 12000 JlW/cm 2 for 15 to 20
minutes. The device should be about 1
inch from the source, and all filters should
be removed from the UV light source prior
to erasure.
The PSD312L and similar devices will
erase with light sources having wavelengths shorter than 4000 A. Although the
erasure times will be much longer than with
UV sources at 2537 A, exposure to fluorescent light and sunlight eventually erases
May, 1993
257
the device. For maximum system reliability,
these sources should be avoided. If used in
such an environment, the package
windows should be covered by an opaque
substance.
Upon delivery, or after each erasure, the
PSD312L device has all bits in the PAD
and EPROM in the "1" or high state. The
configuration bits are in the "0" or low state.
The code, configuration, and PAD MAP
data are loaded through the procedure of
programming
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
Pin
Assignments
Pin Name
44-Pin
PLCC/CLCC
Package
PSEN
WRN pp or RIW
RESET
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PBO
GND
ALE or AS
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PAO
RD/E/DS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
A8
A9
A10
GND
A11
A12
A13
A14
A15
PCO
PC1
PC2
A19/CSI
Vee
May. 1993
258
PSD312L
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
PSD312L
3-volt single-chip microcontroller peripheral
Package
Information
Figure 12.
DrawlngL4U Pin Ceramic
Leaded Chip
Carrier (CLCC)
with Window
(Package Type L)
PB4
7
39 A15
PB3
8
38 A14
PB2
9
o
PB1 10
PBO 11
GND 12
ALE or AS 13
PA714
PA615
37 A13
36 A12
35 A11
34 GND
33 A10
32 A9
31 A8
PA5 16
30 AD7/A7
PA4 17
29 AD6/A6
(TOP VIEW)
Figure 13.
DrawlngJ2U-Pln Plastic
Leaded Chip
Carrier (PLCC)
(Package Type J)
uuuuuuuuuuu
PB4
7
39 A15
PB3
8
39 A14
PB2
9
37 A13
PB1 10
36 A12
PBO 11
35 A11
GND 12
34 GND
33 A10
ALE or AS 13
32 A9
PA714
PA615
31 A8
PA516
30 AD7/A7
PA417
29 ADS/A6
(TOP VIEW)
May. 1993
259
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
Ordering
Information
Part Number
PSD312L25
PSD312L25
PSD312L30
PSD312L30
May. 1993
A
KA
A
KA
PSD312L
Spd.
(ns)
Package
Type
Package
Drawing
Operating
Temperature
Range
Manufacturing
Procedure
250
250
300
300
44-pin PLCC
44-pin CLCC
44-pin PLCC
44-pin CLCC
J2
L4
J2
L4
Commercial
Commercial
Commercial
Commercial
Standard
Standard
Standard
Standard
260
Philips Semiconductors Mlcrocontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
Key Features
o
o
o
Single Chip Programmable Peripheral
for Microcontroller-based Applications
o
1M bit of UV EPROM
-
Configurable as 128K x 8 or as 64K x 16
3.0 to 5.5 Volt Operation
-
Divides into 8 equal mappable blocks
for optimized mapping
19 Individually Configurable I/O pins
that can be used as:
-
Block resolution is 16K x 8 or 8K x 16
-
250 ns EPROM access time, including
input latches and PAD address
decoding.
-
Microcontroller I/O port expansion
-
Programmable Address Decoder
(PAD) I/O
-
Latched address output
-
Open drain or CMOS
o
-
Total of 40 Product Terms and up to
18 Inputs and 24 Outputs
Direct Address Decoding up to 1 Meg
address space and up to 16 Meg
with paging
-
Logic replacement
o
"No Glue" Microcontroller Chip-Set
-
Built-in address latches for multiplexed
address/data bus
-
Non-multiplexed address/data bus
mode
16 Kbit Static RAM
Configurable as 2K x 8 or as 1K x 16
-
250 ns SRAM access time, including
input latches and PAD address
decoding
o
Address/Data Track Mode
-
Enables easy Interface to Shared
. Resources (e.g., Mail Box SRAM) with
other Microcontrollers or a Host
Processor
o
CMiser-Bit
-
Programmable option to further reduce
power consumption
o
-
Selectable 8 or 16 bit data bus width
Built-In Security
Locks the PSD303L and PAD Decoding
Configuration
-
ALE and Reset polarity programmable
o
Available in a Choice of Packages
-
Selectable modes for read and write
control bus as RDIWR, R/W/E, or
RIW/DS
-
44 Pin PLDCC and CLDCC
o
-
BHE pin for byte select in 16-bit mode
Simple Menu-Driven Software:
Configure the PSD303L on an IBM PC
PSEN pin for 8051 users
o
May. 1993
o
-
Two Programmable Arrays
(PAD A & PAD B)
-
-
PSD303L
o
Built-In Page Logic
-
To Expand the Address Space of
Microcontrollers with Limited Address
Space Capabilities
-
Up to 16 pages
261
Pin and Functionally Compatible with
the PSD3XX and PSD3XXL Series
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
Absolute
Maximum
Ratlngs1
Symbol
Parameter
PSD303L
Min
Max
CERAMIC
Condition
-65
+ 150
°C
PLASTIC
-65
+ 125
°C
TSTG
Storage Temperature
TSTG
Storage Temperature
-65
+ 150
°C
Voltage on any Pin
With Respect to GND
-0.6
+7
V
Vpp
Programming
Supply Voltage
With Respect to GND
-0.6
+14
V
Vee
Supply Voltage
With Respect to GND
-0.6
+7
V
>2000
V
ESD Protection
NOTE:
Operating
Range
Recommended
Operating
Conditions
May. 1993
Unit
1. Stresses above those liste~ under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
Range
Commercial
Symbol
Temperature
Vee
0° C to +70°C
3.0 Vto 5.5 V
Parameter
Conditions
vee
Supply Voltage
V 1H
High-level Input Voltage Vee
All Speeds
V 1L
Low-level Input Voltage
262
= 3.0 V to 5.5 V
Vee = 3.0 V to 5.5 V
Min
Typ
Max
Unit
3.0
3.3
5.5
V
0.7 Vee
Vee +0.5
V
-0.5
0.3 Vee
V
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD303L
DC
CMiser= 1
Subtract:
Characteristics
Symbol
VOL
VOH
Parameter
Output Low
Voltage
Output High
Voltage
IS81
Vcc Standby
Current (CMOS)
(Notes 2 and 3)
Icc1
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
Icc2
Icc3
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
Active Current
(CMOS) (SRAM
Block Selected)
(Notes 2 and 5)
Conditions
Min Typ Max Min Typ Max Unit
IOL = 20 IJ.A
Vcc = 3.0 V
0.01
0.1
V
IOL = 4 rnA
Vcc = 3.0 V
0.15
0.4
V
IOH = -20 IJ.A
Vcc =3.0 V
2.9
2.99
V
IOH = -1 rnA
Vcc = 3.0 V
2.4
2.6
V
Vcc = 3.3 V
1
5
Vcc = 3.3 V
(Note 5)
6
12
3.0
5
rnA
Vcc = 3.3 V
(Note 6)
10
20
3.0
5
rnA
Vcc = 3.3 V
(Notes 5
and 7)
6
12
0
0
rnA
Vcc=3.3V
(Note 6
and 7)
10
20
0
0
rnA
Vcc=3.3V
(Note 5
and 7)
20
33
3
5
rnA
Vcc = 3.3 V
(Notes 6
and 7)
24
40
3
5
rnA
-1
±0.1
1
IJ.A
-10
±5
10
IJ.A
III
Input Leakage
Current
VIN = Vcc
orGND
ILO
Output Leakage
Current
VOUT = Vcc
orGND
IJ.A
NOTES: 2. CMOS inputs: GND ± 0.3 Vor Vee ± 0.3V.
3. CSI/A19 is high and the part is in a power-down configuration mode.
4. Add 2.0 mA/MHz for AC power component (power = AC + DC).
5. Ten (1 O) PAD product terms active. (Add 190 J.LA per product term, typical, or 240 J.LA
per product term maximum.)
6. Forty (40) PAD product terms active.
7.ln 8-bit mode, an additional 3 mA Max. can be saved under CMiser.
May. 1993
263
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
Figure 1.
Normalized
Supply Current
PSD303L
2.5
vs.
Supply Voltage
2.25
a:
w
:::::i
D.
2.0
j::
...J
~
:e
Izw
a:
a:
I
1.75
1.5
/
~
0
>
...J
D.
D.
1.25
/
~
tJ)
1.0
/
I
V
/
/
V
V:
I
0.75
2.5
3.0 3.3 3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
The Normalized Supply Current vs. Supply
Voltage graph shown above, provides a
multiplier for any ISB or Icc value in the
D.C. Characteristics table. As noted, it is
normalized for a supply voltage of 3.3 volts.
Since device characterization data shows
very little supply current difference
over speed, the multiplier includes all
May, 1993
264
frequencies of operation from standby to
quiescent to full dynamic speed. To use,
calculate the supply current at 3.3 volts for
your operation configuration using the D.C.
Characteristics table. Then multiply that
value by the Supply Current Multiplier for
the supply voltage actually being used.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
AC
Characterlstlcs(8)
(See Timing
Diagrams)
PSD303L
-25
Symbol
-3D
Min Max Min Max
Parameter
T1
ALE or AS Pulse Width
75
80
T2
Address Set-up Time
30
35
T3
Address Hold Time
30
35
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
ns
T5
ALE Valid to Data Valid
250
300
25
ns
T6
Address Valid to Data Valid
250
300
25
ns
T7
CSI Active to Data Valid
275
325
30
ns
T8
Leading Edge of Read
to Data Valid
90
95
0
ns
0
ns
0
ns
T9
Read Data Hold Time
T10
Trailing Edge of Read
to Data High-Z
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
T12
0
ns
ns
0
50
55
40
45
ns
RD, E, PSEN, DS Pulse Width
100
110
0
ns
WR Pulse Width
90
95
0
ns
T13
Trailing Edge of Write or Read
to Leading Edge of ALE or AS
0
0
0
ns
T14
Address Valid to Trailing
Edge of Write
250
300
0
ns
T15
CSI Active to Trailing Edge
of Write
275
375
0
ns
T16
Write Data Set-up Time
60
65
0
ns
T17
Write Data Hold Time
25
30
0
ns
T18
Port to Data Out Valid
Propagation Delay
0
ns
T19
Port Input Hold Time
T20
Trailing Edge of Write to Port
Output Valid
T12A
70
75
0
0
0
ns
100
110
0
ns
T21
ADi or Control to CSOi Valid
6
80
5
85
0
ns
T22
ADi or Control to CSOi Invalid
4
80
4
85
0
ns
T23
Track Mode Address Propagation
Delay: CSADOUT1 Already True
70
75
0
ns
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes True
During ALE or AS
100
110
0
ns
T23A
NOTE: 8. These AC Characteristics are for VCC = 3.0 - 3.6V.
May, 1993
CMiser=1
Add:
Unit
265
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD303L
AC
Character/sties
(Cont.)
·25
Symbol
Palamete,
·30
Min Max Min Max
eMise,= 1
Add:
Unit
T24
Track Mode Trailing Edge of ALE
or AS to Address High-Z
60
65
0
ns
T25
Track Mode Read Propagation
Delay
70
75
0
ns
T26
Track Mode Read Hold Time
T27
Track Mode Write Cycle,
Data Propagation Delay
T28
Track Mode Write Cycle,
Write to Data Propagation Delay
7
T29
Hold Time of Port A Valid
During Write CSOi Trailing Edge
4
T30
CSI Active to CSOi Active
9
110
T31
CSI Inactive to CSOi Inactive
9
110
T32
Direct PAD Input as Hold Time
24
30
T33
R/W Active to E or OS Start
60
T34
E or OS End to RIW
60
T35
AS Inactive to E high
T36
Address to Leading Edge of Write
10
70
10
60
80
7
75
ns
65
0
ns
85
0
ns
0
ns
4
8
120
0
ns
8
120
0
ns
0
ns
65
0
ns
65
0
ns
40
45
0
ns
50
60
0
ns
NOTES: 9. AOi = any address line.
10. CSOi = any of the chip-select output signals coming through Port B (CS~S7) or
through Port C (CS8-CS10).
11. Direct PAD '!!!put = any of..QJe following direct PAD input lines: CSI/A19 as transparent
A19, RO/E/OS, WR or RIW, transparent PCo-PC2, ALE (or AS).
12. Control signals RO/E/OS or WR or RIW.
May. 1993
266
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD303L
Figure 2.
AC Testing
Input/Output
Waveform
Figure 3.
AC Testing
Load Circuit
...,...
2.0V
:>~ 4000
~
DEVICE
UNDER
TEST
- - C L =30pF
I
(INCLUDING
SCOPE AND JIG
"::'" CAPACITANCE)
Figure 4.
The Reset
Cycle (RESET)
VIL
1----------.. .
500 ns
500 ns
Ii
RESET LOW
May, 1993
..
RESET HIGH
267
..
PART
OPERATIONAL
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD303L
FigureS.
Timing Df 8-BIt
Multiplexed
AddreSS/Data
Bus, CRRWR = 0
....
READ CYCLE
32
~
CSI/A19
asCSI
32-
~XX
7
Direct (13)
PAD Input
Multiplexed
Inputs
(14)
~~
I
-X
I~
6
r- h
1
I~ ~
,
~ f-I
~
3
.m
DATA VALID
2
•
.!.
"
ADDRESS B
r
4
13
8
/
16 11
-
XX
~r
3
~
1\
DATA
;N
14
~ ~\
~
..
14
XXXX XXXX
10
ADDRESSA J
2
XXX XXX
STABLE INPUT
XXXXXXXX XXXXX XXXXXX
AO/ADOA7/AD7
Active Low
ALE
32-
~P<
STABLE INPUT
XXX
-
15
6
Active High
ALE
~
/A\
\
-
WRITE CYCLE
.....
L
,
'-
....J
F
12
RD/E/DS as RD
5
J
I\.
,
36
II
WRNppor
RWasWR
Any of
PAO-PA7
as 110 Pin
X) XXXXXXXXX
Any of
PAO-PA7 Pins
as Address
Outputs
.--..
-
XXXXXXXXXXXXXXXX) .XX
OUTPUT
INPUT
)XXXXXXXXXXXXXXXXXXX
OUTPUT
23
ADDRESS A
J\
See referenced notes on page 278.
May, 1993
~
INPUT
23
_I\.
If
19
\.
Any of \.
PBO-PB7
I
as 110 Pin
,~
13
t--
~
18
X) XXXXXXXXX
I
•
268
ADDRESS B
Preliminary specification
Philips Semiconductors Microcontro\ler Peripherals
PSD303L
3-volt single-chip microcontroller peripheral
Figure B.
Timing of 8-BIt
Multiplexed
Address/Data
Bus, CRRWR = 1
CSI/A19
asCSI
--
-.,
..
READ CYCLE
32
32-
Multiplexed (14)
Inputs
~
~
6
2
Active Low
AS
~ro
4
3
1
,
~ -(
2
~
161-
~ ,-
35
35
~
"Xl XXXXXXXXX
,~
J
~~
JJ\I\IW
19
r-
~.
INPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
INPUT
IXXXXXXXXXXXXXXXXXXX
OUTPUT
23
23
~
I\
rL
L1
36
)XXXXXX
Any of
PBO-PB7 I
as 1/0 Pin
-
- -
J~\
34
~
I
34
33
12
X) XXXXXXXXX
'--
13
18
ADDRESS A
J
See referenced notes on page 278.
May. 1993
J,N
J
'(
RDIE/DS as DS
-
-
-
/ )OC~
.2..
5
Any of
PAO-PA7 Pins
as Address
Outputs
3
h
8
Rfii as Rm
>-
ADDRESS B
~
~
~~
DATA
14
~
~
~
I~ r--+
WRNppor
~
XXXX IXXXX
10
RDIE/DS as E
Any of
PAO-PA7
as 1/0 Pin
14
XXXXXXXX XXXXX XXXXXX
DATA VALID
XXX XXX
STABLE INPUT
14
r
ADDRESSA J
r-
32-
xx: P<
STABLE INPUT
X
AO/ADOA7/AD7
-
15
6
Active High
AS
.(xx XXX
/X\
\
7
Direct (13)
PAD Input
--
WRITE CYCLE
....
269
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD303L
Figure 7. Timing of 16-Blt
Multiplexed Address/Data Bus,
CRRWR=O
...
....,
CSI/A19
READ CYCLE
~
32
~
~
asCS I
I
-..
~
32-
~~
XX) XXXX
7
-
15
32-
Direct (13)
PAD Input
~ 00\
I
~
STABLE INPUT
6
-..
WRITE CYCLE
~
~
XXX )(XXX
STABLE INPUT
14
I
Multiplexed (14 ) .x;~
Inputs
IXXXXXXXX rxxxxx XXXXXX
XXX XIXXXX
10
6
~~
14
1'i'l'J. IXXXX
I'(XXXXXXX XXXXX XXXXXX
DATA
ADIADOA15/AD15
Active High
ALE
Active Low
ALE
-
~m
( ADDRESSA J
2
3
1
I~ --+-
,
~--'
J
8
13
5
r\
3
16 ....
~
~
'f
2
~
4
r~
'fA -
DATA VALID
ADDRESS B
/¥;X IN
'(
~
EJ r
~
I
---..
1
, J
11
---1
~
12
RD/E/DS as RD
-'
36
,
WRNpp 0 r
~
RiWasWR
18
Any 0
f
PAO-PA7
as 1/0 Pin
'x) XXXXXXXXX
I
Any 0 f \.
PBO-PB7 }.)
as 1/0 Pin
Any of
PAO-PA7 Pins
as Address
Outputs
XXXXXXXXX
--
INPUT
J XXXXXXXXXXXXXXXX)( XX
OUTPUT
INPUT
XXXXXXXXXXXXXXXXXXX
OUTPUT
-
23
---1~
~
19
23
ADDRESS A
See referenced notes on page 278.
May. 1993
13
12A 1-+
~
270
\
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD303L
Figure B. Timing of 16-Blt
Multiplexed Address/Data Bus,
CRRWR=1
--
--,
CSVA19
asCSI
READ CYCLE
-... ...
32 w-,
I
\
32- I+-
~XX'
,,~
7
Direct (13)
PAD Input
~~
15
~
STABLE INPUT
6
-
Multiplexed (14)
Inputs
-..
WRITE CYCLE
.....
p
.x;~
32-
~.
14
x.xx.XXXXX
10
~~
-
XXX KXXX
STABLE INPUT
XXXXXXXX XXXXX XXXXXX
6
XXXX
-
14
,(XXXXXXX OCXXXX XXXXXX
,(XXX XXXX
DATA
J,N
AO/ADOA15/AD15
J~
ADDRESS A
2
Active High
AS
Active Low
AS
XX')
J
DATA VALID
r-~
1
Jr+ ---+
XX; I-~
2
~
,
~--
3
16
~
35
~
f--I4
13
,
.
35
,
12
J
.E-.
36
X XXXXXX
'--.J
12 ~
..--...
XXXXX
18
p
X, XXXXXXXXX
Any of \
PBO-PB7 I
as 1/0 Pin
X) XXXXXXXXX
-
INPUT
XXXXXXXXXXXXXXXXJ XX
OUTPUT
INPUT
XXXXXXlXXXXXXXXXXXX
OUTPUT
23
Any of
PAO-PA7 Pins
as Address
Outputs
-
--i~
23
I+ADDRESS A
J
See referenced notes on page 278.
May, 1993
r-
~
"'"- 19
\
I
V
'-
J
RDIE/DS as DS
PAO-PA7
as 1/0 Pin
~
~ 34
33
5
Any of
,--
I
34
8
/XX~
r- ~
1 ~
~
RDIE/DS as E
WRNppor
RlWasRIW
>--
ADDRESS B
-"
~
3
271
ADDRESS B
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD303L
Figure 9.
Timing of 8-Blt
DataNDnMultiplexed
Address/Data
Bus, CRRWR = 0
CSI/A19
asCSI
.....
.....,
..... ........
READ CYCLE
-
32
32-+-
I'(XX XXX
Ji"\
~
7
Direct (13)
PAD Input
AO/ADOA151AD15
as AO-A15
Multiplexed (14)
Inputs
PAO-PA7
-
Active Low
ALE
15
'--
h~
~
STABLE INPUT
6
- h
~
STABLE INPUT
~
-
lJr\
,
14
~
IXXX XXX
...
STABLE INPUT
32-+-
XXX XXXXX
14
-
DATA
J.N
~XXX
DATA VALID
r~
1
'. --.
'tIJ
~
3
\
,
4
--
~r-1
8
13
,
or
RlWasWR
"
2
~
3
~
h
~
f---J
:X:~
-
17
.... 16
r+-J
r
~
~
11
36
,
5
f
X) XXXXXXXXX
~
~
'f
~
19
18
Any 0 f
PBO-PB7 I
as VO Pin
/
12
J
WRNp~
~
XXXXXXXXXXXXXXXX) XX
INPUT
See referenced notes on page 278.
May. 1993
~ 0(
10
--1
RD/E/DS as RD
~.
IXXX XXX
STABLE INPUT
XXXXXXXX OCXXXX XXXXXX
6
2
Active High
ALE
... -
WRITE CYCLE
272
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD303L
Figure 10.
Timing of 8-BIt
Data NonMultiplexed
Address/Data
Bus, CRRWR = 1
-
--,
CSI/A19
asCS I
-
READ CYCLE
....
32
WRITE CYCLE
.....
32 ....
AX~
~
7
Direct (13
)~
PAD Input
AOIADO
A151AD15
as AO-A15
~
6
STABLE INPUT
PAO-PA7
-
6
~m
-I
Active Low
ALE
r- h
1
I'r+ r-+
,
~~
STABLE INPUT
DATA VALID
XX
32-'
-
~
3
161-
~
1lJ r
rL
,
'- Lr
J
~
13
-
33
34
8
---
ROlE/OS as OS
"J
36
5
J
~
,
12
13
XXXXX
18
J.) XXXXXXXXX
r-\. 34
\........J
X XXXXXX
Any of \
PBO-PB7
as 1/0 Pin
19
273
,--
~
XXXXXXXXXXXXXXXXXXX
INPUT
See referenced notes on page 278.
May. 1993
II'Y;X L -
35
4
-
/
12
RiWasRiW
DATA
IN
~
35
XXX
~
XXXX IXXXX
2
1\
ROlE/OS as E
WR/Vpp 0 r
~XX
14
~
3
IXXX XXX
14
'I
\..~
...
STABLE INPUT
10
~
2
Active High
ALE
~P<
~
IXXXXXXXX ~XXXX OCXXXXX
) XI\
Multiplexed (14
Inputs
-
15
STABLE INPUT
~~
~
I'(XX XXX
OUTPUT
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD303L
Figure ". Timing of 16-BIt
Non-Multiplexed Address/Data Bus,
CRRWR=O
--
--.
CSI/A19
asCS I
..
READ CYCLE
~
32
)
Multiplexed (14
Inputs
-
040:,.
IXX XXX
7
AO/ADO A151AD15
as AO-A15
-'""
32-
lX\
~
Direct (13
)~
PAD Input
..
WRITE CYCLE
.....
~
15
~
STABLE INPUT
6
'--
~W
STABLE INPUT
~
X~
tx
~~
14
XXX XXX
STABLE INPUT
32-
l+-
rNfx xxxx
XXXXXXXX ~XXXX XXXXXX
-
XXX XXX
STABLE INPUT
14
.x~
IAXXY XXX X
iAXXXXXXX ~XXXX XXXXXX
6
,
m
PAO-PA7
(Low Byte ).....i
,
~m
PBO-PB7
(High Byte )....J
2
DATA VALID
~
DATA VALID
Active Low
ALE
r--.
,
J
4
,
'(
\.W
8
13
5
,
-
3
h
16
r--
\
r
'~
274
13
~
See referenced notes on page 278.
~
'- J
11
12A
•
~
DATA
IN
1
~
,"
WRNpp or
RlWas WR
r--
\~ r
~
36
RDIE/DS as RD
..
~~
\.
2
~
12
May, 1993
X'IJ
r~
J.. 1
/
\
17
10
~
Active High
ALE
,
XX;
~
3
DATA
IN
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD303L
FIgure 12. TImIng of 16-Blt
Non-MultIplexed Address/Data Bus,
CRRWR=1
--
-.,
CSI/A19
asCS I
... ......
READ CYCLE
32
WRITE CYCLE
32-
AX,
\
~
15
STABLE INPUT
~ 0(
STABLE INPUT
~ -O(~
STABLE INPUT
~ C(
STABLE INPUT
~
IX
Multiplexed (14
Inputs
..
IXXX ~XXX
32-
XXXXXXXX XXX XX XXXXXX
-
XXX KXXX
14
6
AO/ADOA15/AD15
as AO-A15
......
IXX XXXX
7
Direct (13
PAD Input l~
.-
.-
XXXX XXX X
14
]~
,(XXXXXXX KXXXX OCXXXXX
lXX'
6
PBO-PB7 -,
(High Byte )--J
m
2
DATA VALID
~
II'
'"
~W
DATA
IN
, /'f:A
L
/
DATA VALID
~
~
2
10
3
V- h
1
'1'+ f-+
,
1\
J
'f
J
35
35
r-
8
13
~
~ '(
-, r---'.
~
Lr
'-
~
33
34
34
12
.....-.
,
"---'
J
X XXXXXX
XXXXX
See referenced notes on page 278.
May, 1993
13
36
12
RO/E/OS as OS
r
~
4
I. . . . . . . .
5
RiW
16
h
ROlE/OS as E
WRNppo r
-~I
3
J
II
R/Was
/XX ,-~
/
~'tY..'A
~
Active low
AS
XXXX~
DATA
IN
PAD-PA7 -,
(low Byte )-..J
Active High
AS
-
275
r-
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
Figure 13.
Chip-Select
Output Timing
Csi/A19
asCSI
PSD303L
30
,-
I
Direct PAD (13)
Input
Multiplexed
PAD Inputs
(19)
INPUT STABLE
-X)
orALE
(Multiplexed
Mode Only)
J
3
rh
I,. 1 1\
,
V-
r--+
L
~~
(15,2 0)
See referenced notes on page 278.
276
...rr-22
p
May, 1993
'-
,
21
CSOi
,
IXXXXXXX I(X XX
2
ALE
(Multiplexed
Mode Only)
31
...-.
p
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD303L
Figure 14. Port A as ADO- AD7 Timing
(Track Mode), CRRWR = 0
Direct
PAD Input
(13,16)
Multiplexed
PAD Inputs
(17,19)
-
or ALE
~
~
~~
XXXXXXXXXXXXX XXXX X
3
A
r:cIJ
DATA VALID
~
X) ~
f+
.....
r~
..1--.
~
--'
1
,
~
ADDRESS
12
, WRITTEN
DATA
32 ~
1\
1\
~ i'-----I
4
X
3
2
26
I-
IXXXXXXX
STABLE INPUT
Ir ~
\J
-+ 27 f+--
I
12A
11
,
WRlVppor
RiWasWR
24
-
~
ADR OUT)
24
---w:t.
DATA IN
-+ 23 -+--
YXfJ-- -ro ADROUT
-+ 23 f4-
CSOi
1\
J
~
DATA
OUT
~
~
j
(15,18)
See referenced notes on page 278.
May, 1993
:xxx
_I
I
STABLE INPUT
ADDRESS
-n
r---
32-+
2
2
-~
.....
WRITE CYCLE
STABLE INPUT
21
ROlE/OS as RD
PAO-PA7
......
STABLE INPUT
~
AO/ADOA7/AD7
ALE
...
READ CYCLE
277
"
m-
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
PSD303L
Figure 15. Port A as ADO - AD7 Timing
(Track Mode), CRRWR = 1
...
Direct
PAD Input
Multiplexed
PAD Inputs
(17.19)
STABLE INPUT
~
(13.16)
-... ......
..E-.
READ CYCLE
--
-~~
'--
STABLE INPUT
2
~
1-
XXXXXXXXXXXXX XXXXXX
3
ADDRESS
J
~
~
:00
DATA VALID
26
STABLE INPUT
X
XXXXXXX
3
2
I
X'f)-
ADDRESS
WRITIEN
~
DATA
I-
32AS
orAS
_J
-,
rh
r~
.. 1
..!-.
~
..
12
~
ROlE/OS as E
ROlE/OS as OS
~
X .X' IXXXX
\
--.
J
J
WRlVppor
RiWasRiW
12
35
,
J
00( ADROUT) -{m
24
--.
DATA IN
--.
23 ~
CSOi
23
ADR OUTJ
~
27
{XX
..-.
DATA
OUT
YJJ-
.......... .....-..
28
~
(15.18)
Notes for
Timing
Diagrams
XXX>-KX)(
..-.
,----
XX XXXX
34
I ....
-
34
/
\
24
PAO-PA7
f\.
\J
\
35
'-~
-XXX
32STABLE INPUT
I
2
AOIADOA71AD7
-...
WRITE CYCLE
29
---I
13. Direct PAD""!!!put = any of the following direct PAD input lines: CSI/A 19 as transparent A 19,
RD/E/DS, WR or RiViI, transparent PCo-PC2, ALE in non-multiplexed modes.
14. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS):
AO/ADO-A15/AD15, CSIIA19 as ALE dependent A19, ALE dependent PCo-PC2.
15. CSOi = ~ of the chip-select output signals coming through Port B (CSO-CS7) or through
Port C (CS8-CS10).
16. CSADOUT1, which internally enables the address transfer to Port A, should be derived only
from direct PAD input signals, otherwise the address propagation delay is slowed down.
17. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively,
can be derived from any combination of direct PAD inputs and multiplexed PAD inputs.
18. The write operation signals are included in the CSOi expression.
19. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in
the multiplexed modes: A11/AD11-A15/AD15, CSIIA19 as ALE dependent A19, ALE dependent
PCO-PC2.
20. CSOi product terms can include any of the PAD input signals except for reset and CSI.
May. 1993
278
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD303L
Field-programmable microcontroller peripheral
Pin
Capacltance21
TA
= 25°e, f ==
Symbol
1 MHz
Parameter
CIN
Capacitance (for input pins only)
COUT
Capacitance (for input/output pins)
CvPp
Capacitance (for WRNpp or R/W/Vpp)
Conditions Typical22 Max Unit
4
pF
6
VIN = 0 V
pF
8
12
VOUT = 0 V
18
pF
25
Vpp = 0 V
NOTES: 21. This parameter is only sampled and is not 100% tested.
22. Typical values are for TA = 25°C and nominal supply voltages.
Erasure and
Programming
To clear all locations of their programmed
contents, expose the device to ultra-violet
light source. A dosage of 15 W second/cm2
is required. This dosage can be obtained
with exposure to a wavelength of 2537 A
and intensity of 12000 IlW/cm 2 for 15 to 2Q
minutes. The device should be about 1
inch from the source, and all filters should
be removed from the UV light source prior
to erasure.
The PSD303L and similar devices will
erase with light sources having
wavelengths shorter than 4000 A. Although
the erasure times will be much longer than
with UV sources at 2537 A, exposure to
fluorescent light and sunlight eventually
May, 1993
279'
erases the device. For maximum system
reliability, these sources should be avoided.
If used in such an environment, the
package windows should be covered by an
opaque substance.
Upon delivery, or after each erasure, the
PSD303L device has all bits in the PAD
and EPROM in the "1" or high state. The
configuration bits are in the "0" or low state.
The code, configuration, and PAD MAP
data are loaded through the procedure of
programming
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Pin
Assignments
Pin Name
U-Pin
PLDCC/CLDCC
Package
BHEIPSEN
1
WRN pp or RIW
2
3
RESET
PB7
PB6
PBS
4
5
6
7
8
9
PB4
PB3
PB2
PB1
PBO
10
11
12
13
14
15
GND
ALE or AS
PA7
PA6
PAS
PA4
PA3
PA2
PA1
PAO
16
17
18
19
20
21
RD/E/DS
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
ADS/AS
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD10/A10
GND
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD1S/A15
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
A19/CSI
37
38
39
40
41
42
43
Vee
44
PCO
PC1
PC2
May 1993
280
PSD303L
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
3-volt single-chip microcontroller peripheral
Package
Information
Figure 16.
DrawlngL444 Pin Ceramic
Leaded Chip
Ca"ler (CLCC)
with Window
(Package Type L)
PSD303L
I~
..o \ZW t f
I~
. . (/) ~ IW~>uCC
u ~
IDW\
ti
:g
PB4
7
PB3
S
PB2
9
~
0.
0.
CD
II)
0.
a: 3:
.,
c")
N
ID
...
:::
~
N
(,)
...
(,)
(,)
0.
0.
0.
0
N
...
0
., ., .,
UUUUULjUUUUU
38 AD/14/A14
37 AD13/A13
o
PB1 10
PBO 11
GND 12
ALE or AS 13
PA714
PA615
36 AD121A12
35 AD11/A11
34 GND
33 AD10/A10
32 AD9/A9
31 ADS/AS
PA516
30 AD7/A7
PA417
29 AD6/A6
[-1
r1
~ ~
c")
cc
0.
N
CC
0.
ri r-i r-i
0
N
...
N
0
:( cc
0. 0.
N
N
l:g
:-: f-:
: : : :
c")
.,
N
: :
II)
....
N
CD
N
N
N
CC
~
CC CC CC
cc
N
~ ~
r-:
r-1 ri
~
r1
II)
N
II)
(i;I M
~
W c c c
c c c
I~
(TOP VIEW)
Figure 17.
DrawlngJ244 Pin Plastic
Leaded Chip
Ca"ler (PLCC)
(Package Type J)
CC CC
I~
"\Z
o
0.
0.
W
len~
u Q)
W
. . (/) I~ I
~ ~ 3: ~ ~:(
CD
II)
.,
ti 8: If
II)
CD
ID ID
c")
N
...
N
(,)
0.
0
0.
0
(,)
0.
., ., ., .,... .,
.,
c")
0
N
PB4
7
39 AD15/A15
PB3
S
39 AD14/A14
PB2
9
37 AD13/A13
PB1 10
36 AD121A12
PBO 11
35 AD11/A11
GND 12
34 GND
33 AD10/A10
ALE or AS 13
PA714
32 AD9/A9
PA615
31 ADS/AS
PA516
30 AD7/A7
PA417
29 AD6/A6
~ ~
c")
N
cc
cc 0.
0.
May.
1993
39 AD15/A15
281
N
N
...
N
N
:.;:
~
l:g
0
0. 0.
c")
N
0
.,
II)
CD
N
N
N
~
c
N
c")
....N
.,
II)
N
II)
cc
cc
(i;I M ~ ~
c
c c c c
I~ cc cc cc cc cc cc
W ~
0
II)
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
Field-programmable microcontroller peripheral
Ordering
Information
May, 1993
PSD303L
Part Number
Spd.
(ns)
Package
Type
Package
Drawing
Operating
Temperature
Range
Manufacturing
PrDcedure
PSD303L25
PSD303L25
PSD303L30
PSD303L30
250
250
300
300
44-pin PLCC
44-pin CLCC
44-pin PLCC
44-pin CLCC
J2
L4
J2
L4
Commercial
Commercial
Commercial
Commercial
Standard
Standard
Standard
Standard
A
KA
A
KA
282
Preliminary specification
Philips Semiconductors Mlcrocontroller Peripherals
PSD313L
3-volt single-chip microcontroller peripheral
Key Features
o
o
o
o
1M bit of UV EPROM
-
Configurable as 128K x 8
3.0 to 5.5 Volt Operation
-
Divides into 8 equal mappable blocks
for optimized mapping
19 Individually Configurable I/O pins
that can be used as:
-
Block resolution is 16K x 8
-
250 ns EPROM access time, including
input latches and PAD address
decoding.
-
Microcontroller I/O port expansion
-
Programmable Address Decoder
(PAD) I/O
-
Latched address output
-
Open drain or CMOS
o
-
o
16 Kbit Static RAM
-
Configurable as 2K x 8
-
250 ns SRAM access time, including
input latches and PAD address
decoding
Two Programmable Arrays
(PAD A & PAD B)
Total of 40 Product Terms and up to
18 Inputs and 24 Outputs
-
Direct Address Decoding up to 1 Meg
address space and up to 16 Meg
with paging
-
Logic replacement
o
"No Glue" Microcontroller Chip-Set
-
Built-in address latches for multiplexed
address/data bus
-
Non-multiplexed address/data bus
mode
o
Address/Data Track Mode
-
Enables easy Interface to Shared
Resources (e.g., Mail Box SRAM) with
other Microcontrollers or a Host
Processor
o
CMiser-Bit
-
Programmable option to further reduce
power consumption
o
-
Built-In Security
Locks the PSD313L and PAD Decoding
Configuration
-
8-bit data bus width
-
ALE and Reset polarity programmable
o
Available in a Choice of Packages
-
Selectable modes for read and write
control bus as RDIWR, R/W/E, or
RIW/DS
PSEN pin for 8051 users
-
44 Pin PLDCC and CLDCC
-
o
May. 1993
Single Chip Programmable Peripheral
for Microcontroller-based Applications
o
o
Built-In Page Logic
-
To Expand the Address Space of
Microcontrollers with Limited Address
Space Capabilities
-
Up to 16 pages
283
Simple Menu-Driven Software:
Configure the PSD313L on an IBM PC
Pin and Functionally Compatible with
the PSD3XX and PSD3XXL Series
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
Absolute
Maximum
Ratlngsl
Symbol
Parameter
PSD313L
Condition
TSTG
Storage Temperature
TSTG
Storage Temperature
Min
Max
Unit
CERAMIC
-65
+ 150
°C
PLASTIC
-65
+ 125
°C
-65
+ 150
°C
Voltage on any Pin
With Respect to GND
-0.6
+7
V
Vpp
Programming
Supply Voltage
With Respect to GND
-0.6
+14
V
Vee
Supply Voltage
With Respect to GND
-0.6
+7
V
>2000
V
ESD Protection
"NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
Operating
Range
Recommended
Operating
Conditions
May, 1993
Range
Temperature
Vee
Commercial
0° C to +70°C
3.0 Vto 5.5 V
Symbol
Parameter
Conditions
vee
Supply Voltage
All Speeds
VIH
High-level Input Voltage Vee
VIL
Low-level Input Voltage
284
Vee
=3.0 Vto 5.5 V
= 3.0 Vto 5.5 V
Min
Typ
Max
Unit
3.0
3.3
5.5
V
0.7 Vee
Vee + 0.5
V
-0.5
0.3 Vee
V
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD313L
DC
CharacterIstIcs
CMiser= 1
Subtract:
Symbol
Parameter
Output Low
Voltage
VOL
Output High
Voltage
VOH
ISB1
Vcc Standby
Current (CMOS)
(Notes 2 and 3)
Icc1
Active Current
(CMOS) (No
Internal Memory
Block Selected)
(Notes 2 and 5)
Active Current
(CMOS) (EPROM
Block Selected)
(Notes 2 and 5)
Icc2
Active Current
(CMOS) (SRAM
Block Selected)
(Notes 2 and 5)
Icc3
Conditions
Min Typ Max Min Typ Max Unit
IOL = 20 J,LA
Vcc = 3.0 V
0.01
0.1
V
IOL= 4 rnA
Vcc= 3.0 V
0.15
0.4
V
IOH = -20 J,LA
Vcc = 3.0 V
2.9
2.99
V
IOH = -1 rnA
Vcc = 3.0 V
2.4
2.6
V
Vcc = 3.3 V
1
5
Vcc = 3.3 V
(Note 5)
6
12
3.0
5
rnA
Vcc = 3.3 V
(Note 6)
10
20
3.0
5
rnA
Vcc = 3.3 V
(Note 5)
6
12
2
3
rnA
Vcc = 3.3 V
(Note 6)
10
20
2
3
rnA
Vcc = 3.3 V
(Note 5)
20
33
5
8
rnA
Vcc=3.3V
(Note 6)
24
40
5
8
rnA
J,LA
III
Input Leakage
Current
VIN = Vcc
orGND
-1
±0.1
1
J,LA
ILO
Output Leakage
Current
VOUT = Vcc
orGND
-10
±5
10
J,LA
CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
CSI/A 19 is high and the part is in a power-down configuration mode.
Add 2.0 mA/MHz for AC power component (power = AC + DC).
Ten (10) PAD product terms active. (Add 190 IlA per product term, typical, or 240 ~
per product term maximum.)
6. Forty (40) PAD product terms active.
NOTES: 2.
3.
4.
5.
May, 1993
285
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
Figure 1.
Normalized
Supply Cu«ent
PSD313L
2.5
rB.
Supply Voltage
2.25
a:
w
~
0.
2.0
~
;:)
:IE
t-
j
1.75
z
w
a:
a:
1.5
;:)
0
>
..J
1.25
0.
0.
;:)
U)
/
(:
1.0
I
/
/
I
/
/
/
I
0.75
2.5
3.0 3.3 3.5
4.0
4.5
5.0
5.5
6.0
SUPPL y VOLTAGE (V)
The Normalized Supply Current vs. Supply
Voltage graph shown above, provides a
multiplier for any ISB or Icc value in the
D.C. Characteristics table. As noted, it is
normalized for a supply voltage of 3.3 volts.
Since device characterization data shows
very little supply current difference
over speed, the multiplier includes all
May. 1993
286
frequencies of operation from standby to
quiescent to full dynamic sp~ed. To use,
calculate the supply current at 3.3 volts for
your operation configuration using the D.C.
Characteristics table. Then multiply that
value by the Supply Current Multiplier for
the supply voltage actually being used.
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD313L
3-volt single-chip microcontroller peripheral
AC
Characterlstlcs(8)
(See Timing
Diagrams)
Symbol
Parameter
Min Max Min Max
CMiser=1
Unit
Add:
T1
ALE or AS Pulse Width
75
80
T2
Address Set-up Time
30
35
T3
Address Hold Time
30
35
0
ns
T4
Leading Edge of Read
to Data Active
0
0
0
ns
T5
ALE Valid to Data Valid
250
300
25
ns
T6
Address Valid to Data Valid
250
300
25
ns
T7
CSI Active to Data Valid
275
325
30
ns
T8
Leading Edge of Read
to Data Valid
90
95
0
ns
T9
Read Data Hold Time
0
ns
T10
Trailing Edge of Read
to Data High-Z
0
ns
T11
Trailing Edge of ALE or AS
to Leading Edge of Write
T12
T12A
ns
ns
0
0
50
55
40
45
ns
RD, E, PSEN, OS Pulse Width
100
110
0
ns
WR Pulse Width
90
95
0
ns
0
0
0
ns
T13
Trailing Edge of Write or Read
to Leading Edge of ALE or AS
T14
Address Valid to Trailing
Edge of Write
250
300
0
ns
T15
CSI Active to Trailing Edge
of Write
275
375
0
ns
T16
Write Data Set-up Time
60
65
0
ns
T17
Write Data Hold Time
25
30
0
ns
T18
Port to Data Out Valid
Propagation Delay
0
ns
70
75
T19
Port Input Hold Time
0
0
0
ns
T20
Trailing Edge of Write to Port
Output Valid
100
110
0
ns
T21
ADi or Control to CSOi Valid
6
80
5
85
0
ns
T22
ADi or Control to CSOi Invalid
4
80
4
85
0
ns
T23
Track Mode Address Propagation
Delay: CSADOUT1 Already True
70
75
0
ns
Track Mode Address
Propagation Delay:
CSADOUT1 Becomes True
During ALE or AS
100
110
0
ns
T23A
NOTE: 8. These AC Characteristics are for
May, 1993
·3D
·25
287
vec = 3.0 -
3.6V.
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD313L
AC
CharacterIstics
(Cont.)
·25
Symbol
Parameter
·30
Min Max Min Max
CMiser.1
Add:
Unit
T24
Track Mode Trailing Edge of ALE
or AS to Address High-Z
60
65
0
ns
T25
Track Mode Read Propagation
Delay
70
75
0
ns
T26
Track Mode Read Hold Time
T27
Track Mode Write Cycle,
Data Propagation Delay
T28
Track Mode Write Cycle,
Write to Data Propagation Delay
T29
Hold Time of Port A Valid
During Write CSOi Trailing Edge
4
T30
CSI Active to CSOi Active
9
110
8
T31
CSI Inactive to CSOi Inactive
9
110
8
T32
Direct PAD Input as Hold Time
24
T33
R/W Active to E or DS Start
T34
E or DS End to RIW
T35
T36
10
70
10
60
75
ns
65
0
ns
85
0
ns
0
ns
120
0
ns
120
0
ns
30
0
ns
60
65
0
ns
60
65
0
ns
AS Inactive to E high
40
45
0
ns
Address to Leading Edge of Write
50
60
0
ns
7
80
7
4
NOTES: 9. AOi = any address line.
10. CSOi = any of the chip-select output signals coming through Port B (CSO-CS7) or
through Port C (CS8-CS10).
11. Oirect PAO J!!.put = any ofJ!le following'direct PAO input lines: CSI/A19 as transparent
A19, RO/E/OS, WR or RIW, transparent PCO-PC2, ALE (or AS).
12. Control signals ROIEIDS or WR or RIW.
May, 1993
288
Preliminary specification
Philips Semiconductors Microcontroller Peripherals
PSD313L
3-volt single-chip microcontroller peripheral
Figure 2.
AC Testing
Input/Output
Waveform
Figure 3.
AC Testing
Load Circuit
~~
4>
:>
DEVICE
UNDER
TEST
>
L
(INCLUDING
SCOPE AND JIG
CAPACITANCE)
V1H
V1L
1------------11
SOOns
SOOns
RESET HIGH
RESET LOW
May. 1993
n
_ .... C =30pF
I
_
Figure 4.
The Reset
Cycle (RESET)
400
289
PART
OPERATIONAL
Philips Semiconductors Microcontroller Peripherals
Preliminary specification
3-volt single-chip microcontroller peripheral
PSD313L
Figure 5.
Timing of 8-BIt
Multiplexed
Address/Data
Bus, CRRWR =0
---
....,
CSIIA19
asCSI
.....
READ CYCLE
32
32-
1-
Multiplexed (14)
Inputs
~
i..
";:;.
A18
CSI
ES3
ES4
ESS
ES6
~
A13
::::
:::::
orRiW
A1S
ES1
ES2
...
~
V"
v
A17
:::::
-
,...
DorE
A19
ESO
-........
[>0- [>0-... [>0-
~
~
311
eS8/pco
eS9/pC1
eS1o/pC2
PAD
B
Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
PSD3XX
Programmable
Array Decoder
(PAD)
The PAD is an EPROM-based reprogrammabie logic fuse array with sum-of-product
outputs. For Intel-type configurations, inputs
to the PAD are A11-A19, ALE, RD, and WR.
For Motorola type configurations, they are
R/W, AS, and E. The CSI and RESET inputs
are used to deselect the PAD for power-down
configurations and initialization, respectively.
Internal to the PSD301 are the ESO-ES7
EPROM select lines. There is one product
term dedicated to each EPROM block,
and a single product term (RSO) for the
SRAM selection. Address and control for
each EPROM bank can programmed to a
resolution of a 4K word boundary and positioned anywhere in the mapping scheme of
the designer's system. Similarly, the SRAM
can be positioned on 2K word boundaries.
product term generates the CSIOPORT
signal; this provides a base address for Ports
A and B. The registers relevant to these ports
are addressed as a base offset (see Table 1).
The CSADIN signal is used to control the
input buffer in the track mode. It can be
enabled to read data in a programmed
address space from Port A through the
PSD3XX. CSADOUT1-2 are used to control
the multiplexed address and write data
through the PSD3XX to the Port A pads. The
address range is programmed into the PAD
qualifying the address space, but CSADOUT1
is qualified by the ALE signal outside of the
PAD. This automatically lets the design
distinguish between address and write data.
To qualify valid write data, the PSD3XX
automatically includes the CSADOUT2
product term with the WR or R/Vii signal.
Other internal product term outputs from the
PAD are the CSIOPORT, CSADIN, CSADOUT1, and CSADOUT2 lines. A single
Table 1.
Port Base Address
Offset
Register Name
Offset From The CSIOPORT Base Address
Pin Register of Port A
Pin Register of Port B
Direction Register Port A
Direction Register Port B
Data Register Port A
Data Register Port B
Pin Register of Ports A and B
Direction Register of Ports A and B
Data Register of Ports A and B
The PAD structure enables additional chipselects to be routed to the Port B output pins.
The four chip-select outputs (CSO-CS3) are
supported by four product terms per output.
CS4-CS7 have two product terms per output.
the ability to use more than one product term
from a chip-select enables the mapping of
additional devices to be distributed through
the address space, rather than selecting
memory as a block. Sacrificing Port B
terminals for chip-selects could occur in
systems requiring a larger EPROM, RAM, or
May, 1993
312
1/0 space. Additional PSD3XX devices can
be designed into a system by using the chipselect outputs from Port C or B of one master
PSD3XX. This is required for addressing a
space greater than 1M. Finally, the outputs of
the sum-of-product terms are inverted to be
consistent with active LOW chip-select inputs
for additional external RAM, EPROM, peripherals, or busses. Port C has the capability of
providing three additional external chipselects, each supporting one product term per
output.
Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
Microcontroller/
Microprocessor
Control Inputs
Input and Output
Ports
PSD3XX
The control inputs are also programmable:
WR or R/W and RD or E are used for readl
write control of the internal EPROM, RAM,
and 1/0 capability. Other control inputs are a
programmable option for Bus High Enable or
Program Store Enable (BHE/PSEN) and
Address Latch Enable or Address Strobe
(ALE/AS). These pins are selected to suit the
bus protocol of the host processor or, where
not applicable, they can be ignored. The CSII
A 19 input is available either for a power-down
chip-select enable or as a higher-order
address input without the power-down
feature. The final control input is the RESET
input; this also is a programmable option. Its
active polarity can be chosen to be compat-
The port section comprises Port A (8 bits),
Port B (8 bits), and Port C (3 bits). These
support the many different 1/0 operations.
For port expansion, Ports A and B can be
configured as general 1/0 ports, each to
convey eight bits of digital data to and from an
external device. Figure 8 shows a single cell
of Port A; Figure 9 shows a single cell of
Port B.
Writing data to a port is similar to writing data
to a RAM location. If a port is programmed as
an output, data is loaded into the output
register as if it were a RAM location. Although the ports are not bit addressable,
individual bits can be selected as either input
or output. Thus, PAO-5 can be set as data
outputs while PA6 and PA7 can be configured
as inputs. Any mix of II0s is possible giving
the ports additional flexibility.
The direction of data flow through the port is
determined by the data direction register.
This register is dynamically programmable so
that the 1/0 direction through Ports A and B
can be altered during the microcontroller
program execution. The data direction
register initializes with logic zeros after an
active RESET and causes each port bit to be
set as an input. This state of initialization
guarantees that the ports are prevented from
driving the output lines at start-up. If the user
requires all the Port A or Port B bits to be
May, 1993
313
ible with the host system. The function of the
RESET input is to clear and initialize the
PSD301 at start-up. All II0s are set up as
inputs and all outputs are either in a nonactive or three-state condition.
Consequently, the PSD3XX is prevented from
actively driving outputs during start-up. This
feature was incorporated to prevent potential
bus conflicts. In Figure 2, the CSI and
RESET inputs are shown also as PAD inputs.
CSI is a hardwire option into the PAD that
powers down the internal circuitry and is
used in power-sensitive applications. Neither
signal is available as a programmable option.
inputs, the data direction register can be left
in this default state. To enable it as an
output, logic ones can be written into the data
direction location.
Due to the internal design, it is possible to
program Port A or Port B bit lines as inputs
and still write data to the port locations. This
is because both ports have on-chip latches
and can hold data. These registers are
hidden or buried; i.e., they exist in the port
and their condition can be read back at any
time. However, these outputs do not drive the
output pins because the port has been
enabled as an input.
To access the port as a memory mapped
location, the initial selection is made through
the PAD's CSIOPORT. This provides a base
address from which the locations shown in
Table 1 give access to the various ports or
their options. The configuration support
software automatically ensures that there is
no conflict between an SRAM location and 1/0
port in the case of memory mapped peripherals. It is also possible for the PSD3XX to
distinguish between 1/0 and memory mapped
locations. The user can input memory and
Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
Input and Output
Ports (Cont.)
I/O control signals to the PAD through the
A 16-A18 inputs and program an active
CSIOPORT output by decoding these signals.
This can be achieved with Intel- and Zilogtype processors which have separate memory
and I/O controls. Signal input through pins
A 16-A18 is made possible through Port C.
This 3-bit port is responsible for either PAD
chip-select outputs or address/logic inputs.
CSIOPORT points to a base address at which
Ports A and B reside . Table 1 provides the
offset from the base address and the associated port function. Figure 2 shows that Port A
Figure 8.
PSD3XX Port A
Structure
The other options available to the user are
selecting 1) the shared resource or track
mode where ADO-AD? is routed directly
through to the Port A output, or 2) the latched
address AD-A? In track mode, ADO-AD?
inputs to the PSD3XX are used to access
local or private memory and peripherals and
the outputs ADO-AD? through Port A are
used to access a public resource.
A 1 A2 WR RD CSIOPORT
ADO - AD7
May, 1993
is driven by a multiplexed address/data bus of
ADO-AD? and the selection of address/data
is made from the configuration memory and
internal control functions.
ALE
RESET
314
240208
Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
Figure 9.
PSD3XX Port B
Structure
PSD3XX
A 1 A2 WR RD CSIOPORT
RESET
PSD3XX Beneral
System Configuration
May, 1993
The PSD3XX family devices consists of two
byte-wide configurable 1/0 ports (Ports A
and 8), 256K to 1M bits of EPROM, 16K
bits of RAM, and the PAD. Additional 1/0
capability to and from the PAD is through a
3-bit 1/0 (Port C). There are also on-chip
latches to support processors and
controllers that multiplex address and
data on the same bus. The EPROM memory
section of the device is programmable just
like a standard EPROM device. However,
unlike the single-chip EPROM, the PSD3XX
must also be configured to function into one
of its many possible modes of operation. This
315
240209
is done by programming a non-volatile
EPROM memory location with 45 configuration bits. These bits select the mode of
operation and are programmed into the
EPROM along with the hexadecimal microprocessor/microcontroller assembly language
object code. When using MAPLE software,
the assignment of logic conditions to the
configuration bits locations is transparent to
the user; the resultant word is merged with
the EPROM code and the data map for the
PAD.
Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
PSD3XX General
System CDnfigu~atiDn (Cont.)
PSD3XX
Table 2 shows the the configuration locations
and their functional assignment. For example, one of the configuration bits enables
the device architecture to be compatible for
either byte- or word-wide data buses. This is
the configuration data or CDATA bit. The 256
Kbits of EPROM can be configured as a 32K
byte-wide bus for applications with an 8031
microcontroller or as a 16K word-wide bus for
applications with an M68000 microprocessor.
These configuration bits are discussed in
detail as each feature is covered in this
application note.
In addition to bus width, the polarity and mode
of the bus control signals are programmable.
There are two types of read/write control: one
is consistent with either a Motorola and Texas
Instruments control bus standard; the other is
consistent with the Intel/National Semiconductor/Zilog control bus standard. The
configure read and write bit (CRRWR),
distinguishes between one of two conventions: either an Intel (8031) or Motorola
(M68HC11) convention can be selected by
programming this single bit in the configuration memory. The Intel device requires the
PSD3XX to be programmed with an active
LOW RD and WR controls (CRRWR = 0).
For applications with the Motorola microprocessor, select the R/Wand E option (CRRWR
= 1). In addition to a choice of two READ/
WRITE controls, the user can select either a
multiplexed Address/Data Bus or separate
address and data lines.
Figure 3 shows the configuration that is best
suited for the 8031 microcontroller; Figure 4
shows the configuration for an 80196 microcontroller with a 16-bit multiplexed addressed/
data bus. For the non-multiplexed modes:
Figure 5 applies to M6809 microprocessors,
while Figure 6 shows the mode applicable to
the M68000. Selection of multiplexed or nonmultiplexed buses is a programmable option
that can be invoked through the configure
address/data multiplex (CADDRAT) bit. With
the 8031 controller, address outputs AO-A7
are multiplexed with the data DO-D7 input!
output lines to create a composite ADO-AD7
bus.
May, 1993
316
The PSD3XX's input latches can be programmed to catch a valid address when the
microcontroller's ALE signal transitions from
active HIGH to inactive LOW. The polarity of
the ALE signal is also a programmable
feature in the CALE field of the configuration
table. Address latching can be programmed
to occur on either an active HIGH or an active
LOW ALE signal. With Intel devices, the address is valid when ALE is HIGH. Once
latched, data or code can be read from, or
written to, the PSD3XX. The CALE active
HIGH or LOW ALE configuration bit only
applies to addresses AO-A 15. A separate
configuration bit, (CADDHLT), exists for the
control of the higher-order address inputs
(A16-A19). If necessary, these addresses
can also be latched by the host system.
The highest address input is A19 but this
signal can be omitted in favor of a powerdown chip-select input (CSI). A19/CSI is
selected by the CA 19/CSI configuration bit.
When the CSI input is selected and the pin is
driven HIGH, the device can be powereddown consuming only standby power. When
configured with other CMOS devices, the
standby power is in the 80-250 IlA range.
Many CMOS microcontrollers do not need a
large memory address space; thus, address
inputs A16-A19 would be unnecessary. The
CA 19/CSI input can be programmed with a
logic LOW to enable a power-down option for
power sensitive applications.
The address/data multiplexed scheme also
supports the 16-bit processors. In this case,
ADO-AD15 convey a 16-bit address qualified
by ALE (or AS for the Motorola convention)
and 16-bits of data I/O. This feature is shown
in Figure 4. A microcontroller that would use
this scheme is the 80C196. The M68HC11,
like the 8031, uses the 8-bit multiplexed
scheme but with the Motorola convention for
bus control.
Another control pin used for 80C31 applications used to distinguish between program
and data memory is the PSEN output. The
COMB/SEP configuration bit should be
programmed HIGH if data and memory are
separate and LOW to configure a combined
memory space in the PSD3XX. This is a
Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
PSD3XX General
Confi"u:I'
ration (Cont.)
S~em
,.,.1
PSD3XX
useful feature for systems that require program memory and data memory to be in
separate blocks.
For systems that use separate data and
address buses, the address latches can be
set into a transparent mode by clearing the
CADDRDAT bit location. Thus, the PSD3XX
is suitable for multiplexed or non-multiplexed
bus structures employing 8- or 16-bit bus
widths.
The RESET input to the PSD3XX enables the
device to be initialized at start-up. RESET
Table 2.
Non-volatile
Configuration
Bits
Configuration
Bits
Number of Bits
can be either active HIGH or active LOW
depending on the processor type. The
CRESET configuration bit selects the polarity
of the RESET input: LOW for active LOW and
HIGH for active HIGH RESET. Normally,
memory systems do not require a RESET
input; however, the PSD3XX contains data
direction registers for the ports that must be
initialized at start-up. Note that all port I/O
buffers are automatically programmed as
inputs during start-up.
Function
= eight bits, 1 = sixteen bits
= Non-multiplexed,
CDATA
1
CDATA. 0
CADDRAT
1
ADDRESS/DATA Multiplexed. 0
1 = Multiplexed
CRRWR
1
CA19/CSI
1
= RD and WR, 1 = R/Wand E
= Enable power-down, 1 = Enable A 19
ALE Polarity. 0 = Active HIGH,1 = Active LOW
CRESEI. 0 = Active LOW RESET, 1 = Active HIGH RESET
CRRWR. 0
A 19 or CSI. 0
CALE
1
CRESET
1
COMB/SEP
1
Combined or Separate Address Space for SRAM and
EPROM. 0 = Combined, 1 = Separate
CPAF2
1
Port A Track Mode or Port Mode. 0
1 = ADO-AD? Track Mode
CPAF1
8
Port A I/O or AO-A? 0 = Port A pin is I/O,
1 = Port A pin is Address
CPBF
8
Port B I/O or CS. 0 = Port B pins are CSi (i
1 = Port B pins are I/O
CPCF
3
Port C A16-A18 or CS8-CS10. 0 = Port C pins are
Address, 1 = Port C pins are Chip-select
CPACOD
8
Port A CMOS or Open Drain. 0
1 = Open Drain
= CMOS drivers,
CPBCOD
8
Port B CMOS or Open Drain. 0
1 = Open Drain
= CMOS Drivers,
CADDHLT
1
= Port or Address,
A 16-A 18 Transparent or Latched. 1
o = Address transparent
CSECURITY
PSD3XX
Configuration
for Port
Reconstruction
May, 1993
1
= O-?),
= Address latched,
CSECURITY On/Off. 0 = Off, 1 = On
A key feature of the PSD3XX is the concept of
port reconstruction. When using microcontrollers with additional off-chip memory, port
I/O address lines are sacrificed for address,
317
data, and memory control lines. With a
multiplexed address/data scheme, two 8-bit
controller ports could be lost to address and
Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
PSD3XX
Configuration
for Port
Reconstruction
(Cont.)
PSD3XX
data. Furthermore, in some control applicaADO-AD? passes through the PSD3XX logitions, many port I/O bits are required to send
cally unaltered. In summary, PAO-PA? can
actuating signals to solenoids, instrument
be programmed as port I/O or latched addisplays, etc., and receive data through
dress outputs AD-A? (each bit being prosensors and switch panels. In many control
grammed on an individual basis), or as
environments, a large amount of I/O capability ADO-AD? outputs (track mode).
is required; also, additional external memory
Port B bits PBO-PB? can be programmed
is needed for microcontroller instructions to
either as regular port I/Os, or as chip-select
perform data manipulation. Without the
outputs CSO-CS? encoded from the PAD
PSD3XX , the supplement of extra ports as
outputs. Figure? shows the PAD structure as
discrete latches addressed through logic
a conventional PLD. Eight bits are prodecoders can add a number of chips to the
grammed into CPBF. Logic LOW indicates that
final design. By using the PSD3XX, additional
a port pin is a chip-select output derived from
EPROM, RAM, and ports are all provided on
the PAD. Programming a logic HIGH sets the
one chip. Port reconstruction lets the deappropriate pin as an I/O function. The bit
signer reclaim the two ports sacrificed for the
pattern 11111 OOOB programmed into the
microcontroller's address and data.
CPBF location sets up PBO.,..PB4 as I/O ports
Port configuration is achieved through the
and PB5-PB? as chip-selects. The typical
configuration register bits. CPAF1 configura- applications, where Port B is programmed as
bi-directional, would be with microcontroller
tion of Port A contains eight bits; programchips that need additional port bits. This
ming a logic LOW assigns the selected bit
would be in applications where port reconwith I/O capability as if it were a conventional
struction is needed to drive many indicators,
port. If programmed HIGH, the internally
latched address inputs AD-A? are routed to
solenoids, read switches, sensors, etc. In
Port A lines PAO-PA? This feature enables
large microprocessor-based systems, the
other on-card peripherals to use AD-A? as
chip-select option would probably be chosen;
latched addresses. Without this feature,
in this case, the PAD outputs select other
external peripherals to the PSD3XX would
PSD devices, DRAM memory chips, and
require an external octal latch to catch the
peripherals such as timers, UARTs, etc.
multiplexed address when it becomes valid at The three bits comprising Port C can be
the microcontroller's output. Configuration of programmed by the CPCF configuration bits.
Port A as general I/O or address/data is on a
This group of three bits define whether Port C
bit-wise basis; thus, the choice of port or
is used for inputs (typically A 16-A18) or
address/data assignment can be mixed. For
whether the pins are used as chip-select
example, configuration code 111 OOOOOB
outputs from the PAD. Although labeled as
programmed into location CPAF1 passes
A 16-A18, the nomenclature of these pins
addresses AO-A2 to outputs PAO-PA2 and
does not constrain the designer to using
enables PA3-PA? as conventional port lines. these inputs as dedicated higher-order
Configuration bit CPAF2 is a 1-bit location.
When programmed LOW, it selects the port!
address option, as described above. If
CPAF2 is programmed HIGH, port bits
PAO-PA? are set into track mode. Activity on
the PAO-PA? outputs follow logic transitions
on inputs ADO-AD? The multiplexed address/ data input is tracked through
PAO-PA? Track mode enables the host
microcontroller to access a shared memory
and peripheral resource through the PSD3XX
while maintaining the ability to access its own
(private) memory/peripheral resource directly
from the microcontroller's address/data
outputs. In this mode, the address/data
May, 1993
318
address inputs. In fact, they can be generalpurpose inputs to the PAD for processors that
do not have an address capability above 64K
locations. When the PSD3XX is used with the
Z80B microprocessor, the Port C inputs have
been programmed as MREQ, lORa, and M1.
In the case of an interface to the M6809B, two
inputs of Port C have been converted to chipselect outputs for other memory devices and
one output has been used to feedback a
READY input to the M6809B. Port C can be
used as a general I/O from the PAD in the
form of address, control, and chip-select bits.
A logic LOW programs a port bit as an input;
a HIGH programs it as an output.
Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
PSD3XX
Chapter 2 Applications
B-Bit Microcontroller to "S03XX
•
,.,6
,nte"ace
Tab/e3.
Small Controller
System with One
BOC31 and One
"S03XX
May, 1993
Figure 10 illustrates the minimum configuration?f o.ne ~ontroller and one PSD3X~. The
application Illustrates port reconstruction
through the device's Port A and Port B 1/0,
reconstituting port 2 and port 0 of the microcontroller. Table 3 gives the configuration
information that would be programmed in the
configuration section of the PSD. Table 3
shows that both port II0s have been programmed with CMOS load and drive characteristics. A feature of the 8051/8031 family is
the PSEN signal, which determines whether
the memory selection is active for executable
Configuration
Bits
code or data. This family of controllers has
separate memory locations for code and data.
To maintain full compatibility, the PSD3XX is
also capable of being programmed to respond
to the PSEN signal. When A 16-A 18 are
programmed as inputs but not driven, they
should be tied active HIGH or LOW. Unused
inputs to the PSD3XX must not be permitted
to float. Tying can be avoided on unused
A 16-A 18 lines if these are programmed as
'dummy' CS8-CS1 0 outputs. A 19/CSI cannot
be programmed as an output; thus, it must be
tied if not used.
Function
CDATA
0
8-bit data bus
CADDRDAT
1
Multiplexed addressldata
CRRWR
0
Set RD and WR mode
CA19/CSI
0
Set CSI input power-down mode
CALE
0
Active HIGH ALE
CRESET
1
Active HIGH RESET
Code and data memory separate
COMB/SEP
1
CPAF2
0
CPAF1
OOH
Input/Output Port A (0-7)
CPBF
FFH
Input/Output Port B
Input/Output Port A
CPCF
OOOB
Port C programmed for inputs
CPACOD
OOH
Configure CMOS outputs Port A
CPBCOD
OOH
Configure CMOS outputs Port B
CADDHLT
0
Transparent inputs A 16-A 19
CSECURITY
0
No security
319
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~~
AD5IA5
AD6IA6
AD7/A7
PA5
PA6
PA7
AD8IA8
AD9/A9
AD10/A10
AD11/A11
AD121A12
AD13/A13
AD14/A14
AD15/A15
PBO
11
PB1
10
PB2:
PB3
7
PB4
PB5
6
PBS
5
PB7
4
RD
WRNPP
BHEIPSEN
ALE
RESET
14
A16/CS8 ~
A17/CS9 ~
~>
~:
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~
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PB4 ..
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A18/CS10 ~
A19iCS1 ~
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.....
Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
TwoPSD3XX
Byte-Wide
Interfaces to the
Intel BOC31
Table 4.
BOC31 Interface
to Two PSD3XX
Devices with
Power Economy
Feature
Figure 11 illustrates an extension to the
previous design in that two PSD3XX devices
have been used, doubling the memory and
port resources of the system solution. In this
application, the power-down capability has
been used so that one PSD3XX can be active
while the other device is in power-down
mode. The mean power consumption is
reduced, so this configuration can be considered for power-sensitive applications.
Configuration
CDATA
Bits
Function
0
8-bit data bus
CADDRDAT
1
Multiplexed address/data
CRRWR
0
Set RD and WR mode
CA19/CSI
0
Set CSI input power-down mode
CALE
0
Active HIGH ALE
CRESET
1
Active HIGH RESET
COMB/SEP
1
Code and data memory separate
CPAF2
0
Input/Output Port A
CPAF1
OOH
CPBF
FFH
Input/Output Port B
CPCF
111 B
Outputs CS8-CS 10
CPACOD
OOH
Configure CMOS outputs Port A
CPBCOD
OOH
Configure CMOS outputs Port B
CADDHLT
X
"Don't care" for latched A16-A19
CSECURITY
0
No security
Input/Output Port A (0-7)
It is not recommended that the two PSD3XX
devices select each other because the PAD
section of a PSD device is powered down
with the rest of the device. At least one PAD
May. 1993
The configuration Table 4 indicates that Port
C has been configured as outputs. Provided
one PSD3XX is powered up for the whole
address range, its PAD can decode an
address range to select and deselect the
second PSD3XX device through the CS 10
output. In Figure 11, the PAD output A18/
CS10 on PSD3XX U2 can be used to powerdown the second PSD3XX through the A19/
CSI input.
321
decoder must be kept active to select and
deselect others. Port C outputs CS16-CS18
can power-down as many as three other
PSD3XX devices.
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PO.2
36
PO.3
35
POA
34
PO.5
33
~~:~
32
P2.0
P2.1
P2.2
P2.3
P2.4
23
24
25
26
33
35
36
37
27
28
38
39
RESET
INTO
INn
TO
n
~~:~
P1.0
P2.7
~~
~~:~"RD
P1.3
P1.4
P1.5
P1.6
P1.7
~!
25
26
27
28
29
30
~~
ADO/AO
AD1/A1
AD2IA2
AD3/A3
AD4/A4
AD5/A5
PAO
PA1
PA2
PA3
PA4
PA5
~~~~~
~~~ L---'=---~""''''''-
ADS/A8
AD9/A9
AD10/A10
AD11/A11
AD121A12
PBO
PB1
PB2
PB3
PB4
~g~~~~!
~~~
AD151A15
PB7
RD
WRIVPP
BHEIPSEN
ALE
RESET
WR
PSEN
ALEIP
TXD
RXD
80C31
PSD3XX
.g.
U3
A161CS8
A17/CS9
A18/CS10
A19/CSI
L~J~~""""="""""
40
41
PCOO
PC01
ADO/AO
AD1/A1
AD2IA2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
ADS/A8
AD9/A9
AD10/A10
AD11/A11
AD121A12
AD131A13
AD141A14
AD151A15
RD
~~::EN
ALE
RESET
=r
PAO
PA1
CD
~
PA2.---.~..........!....::!..l.:::__
PA3
en
PA4
PAS
PA6~~~""""'''''-:;''''''''''
PA7
PBO . .17\............:....::::..:..:::'--""
PB1
PB2 .-..-............:....::~__
PB3
PB4
PBS L_9_~"""";-;-;:;"""""
PB6
PB7
A161CS8
A17/CS9 .-~-..........:....::::.!...:.-A181CS10
A19iCSi
PSD3XX
TX~----------------------------~
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Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
PSD3XX M68HC11
Byte-Wide
Interface
Table 5.
M68HC11 to
PSD3XX Interface
May. 1993
Figure 12 illustrates the configuration of an
M68HC11 microcontroller which also uses the
8-bits wide multiplexed address/data bus.
The application is similar to that given in
Figures 6 and 7 except that the R/W and E
control lines have been invoked to establish
compatibility with the Motorola device. The
address strobe output from the M68HC 11 is
HIGH so the AS(ALE) input is set HIGH. The
SRAM and EPROM section are programmed
as combined and both Ports A and Bare
enabled as I/Os with CMOS drives. Port C is
programmed with chip-select outputs
CS8-CS10. Other PSD3XX devices can be
mapped into the addressing scheme or the
lines can be programmed to transition as
strobes in defined mapping areas. The latch
enable bit for the higher-order address lines
A 16-A 19 is not used establishing a don't care
condition. The CADDHLT condition must be
selected if anyone of A 16-A 19 lines is
selected as input to the PSD.
Configuration
CDATA
Bits
0
In this design, the security bit is programmed.
This bit prevents the reading of the PAD
configuration by an unauthorized user.
Furthermore, if the security bit has been
programmed, standard programming machines can not read the internal code of a
PSD3XX. However, data can always be read
from the EPROM, RAM, and ports. This
provides normal use of the device. If the
address map in the PAD cannot be interpreted, the actual location of data within the
address and I/O space is difficult to determine. Besides programming the CSECURITY bit, added security can be applied by
scrambling the sequence of address and data
inputs. A short PASCAL or 'c' program can
be written to reorganize the original Intel MCS
code to be aligned with the scrambled pins.
Table 5 indicates the configuration for the
M68HC11/ PSD3XX interface.
Function
8-bit data bus
CADDRDAT
1
Multiplexed address/data
CRRWR
1
Set R/W and E mode
CA19/CSI
0
Enable CSI input
CALE
0
Active HIGH AS (ALE)
CRESET
0
Active LOW RESET
COMB/SEP
0
Combined memory mode
CPAF2
0
Input/Output Port A
CPAF1
OOH
Input/Output Port A
CPBF
FFH
Input/Output Port B
CPCF
111 B
Output CS8-CS 10
CPACOD
OOH
CMOS drivers
CPBCOD
OOH
CMOS drivers
CADDHLT
X
"Don't care" A 16-A 19 not used
CSECURITY
1
Security on
323
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XTAL
XTAL
PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD~
PD1
PD2
PD3
PD4
PD5
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PEO
PE1
PE2
~PE3
E'E4
~!
PE4
(,)
N
~
PE5
PE6
PE7
Vee
PA2
8
9
10
11
12
13
14
15
23
24
25
26
27
28
29
30
16
17
18
19
20
21
22
23
31
32
33
35
36
37
38
39
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
A16/CS8
A17/CS9
E
34
33
32
31
30
29
28
27
Fi!W!vpp
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
52
51
G-ND
..,
U2
U1
BHE/PSEN
AS
RESET
A18/CS10
A19/CSI
"S
(,-
21
20
19
18
17
16
15
14
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11
10
9
8
7
6
5
4
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PB1
PB2
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40
41
42
43
GND
PSD3XX
MOD
MOD
VRH
VRL
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II
68HC11
~
R1
4K7
~
R1
4K7
~
R1
.4K7
~
R1
4K7
Vee
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2
"2-
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RESET
3
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R1
4K7
U3
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Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
B-BIT Non-Multiplexed PSD3XX
Interlace to
M6BOOB
Figure 13 illustrates an application in which
the address and data are not multiplexed.
The M68008 has an 8-bit data bus and 20-bit
address bus. The PSD3XX can be programmed to support the microprocessor by
providing data I/O through Port A. The
address lines from the microprocessor go to
inputs AO-A 19. Port B outputs are used for
external chip-selects to other MAP devices or
other memory resources. The configuration
has been set for compatibility with Motorola
control signals. There are six chip-select
outputs (CSO-CS5) and an address decode
for DTACK and BERR. The PAD decodes an
address range which is fed back to the
microprocessor through these inputs. Using
the open-drain configuration has been implemented in Port B bits 6 and 7. The two pullup resistors enable external memory and
peripherals to access the DTACK and BERR
inputs as a wired-OR function.
needed to avoid possible bus contention on
these lines. In this application, ALE(AS) can
be used as a general-purpose logic input to
the PAD because the function of ALE becomes redundant in a non-multiplexed
address/data bus. Also shown in Figure 13 is
a method of inverting the active LOW DS
(Data Strobe) M68008 output. The A 19 input
is enabled to the PSD internal PAD and
inverted at the output of CS 10 to drive the
PSD3XX E input. The E input must be active
HIGH but DS is active LOW and qualifies a
valid data transfer. Thus, the PAD must
perform a signal inversion. The E signal
output from the M68008 is used to interface to
Motorola 8-bit peripherals. However, with
Motorola microcontroller families such as the
M68HC11, the E signal output can drive the E
input to the PSD3XX. Table 6 gives the
configuration information associated with the
design given in Figure 13.
If other PSD3XX devices are mapped into the
M68008 system, no additional glue logic is
Table 6.
M6BOOBto
PSD3XX Interlace
Configuration
Bits
Function
CDATA
0
8-bit data bus
CADDRDAT
0
Non-multiplexed address/data
CRRWR
1
Set R/W and E mode
CA19/CSI
1
Enable A 19 input1
CALE
X
"Don't care" non-multiplexed mode
CRESET
0
Active LOW RESET
COMB/SEP
0
Combined memory mode
CPAF2
X
"Don't care" Port A used for data
CPAF1
XXH
"Don't care" Port A used for data
CPBF
OOH
Port B used for chip-selects
Configure A16 and A171n, CS10 OuF
CPCF
001B
CPACOD
OOH
CMOS drivers
CPBCOD
3FH
CMOS drivers, PB6, PB7 open drain
CADDHLT
0
Address latch transparent A 16-A 19
CSECURITY
1
Security on
1. The DS output from the M68008 drives the A19 input to the PSD3XX.
2. The internal PAD of the PSD3XX inverts the DS input to drive its own E input from the CS10 PAD output. A 16 and
A17 are programmed as PSD inputs.
May, 1993
325
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FCO
FC1
FC2
BG
34
39
42
41
33
31
40
45
44
43
32
38
E
HALT
36
~
29
~
~
CLK
VPA
IPLO/2
IPL1
BR
DTACK
BERR
FCO
FC1
FC2
BG
E
HALT
RESET
AS
OS
RtW
46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
14
16
23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
~
I 17
~
~
27
DO
01 I 26
25
02
03 I 24
23
04
05 I 22
21
06
07 I 20
Vee
T-¥-
/1
~
~
~
~
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD1 0/A1 0
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
V
V
1
13
3
E
"RtWNPP
BHE/PSEN
AS
RESET
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
A16/CS8
A17/CS9
~
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c:
~
en
s:
0"
CD
....
(1)
.g"
:::r
U2
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
3
0
"'tJ
DTACK
CLK
VPA
(1)
0"
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R2
560R
::J
DTACK
BERR
en
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0
8
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2-
Vee
Vee
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18
~
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;111
~
21
20
19
18
17
16
15
14
(1)
~
en
11
10
9
8
7
6
5
~
>--Cst
~
~
>--Cs4
~
~
Fl1
40
41
S
MoYeS'
A19/CSI0 ~
PSD3XX
{
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68008
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Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
lB-SitMonMultiplexed
AddreSS/Data
"S03XX Interface
toMB8000
Table 7.
MB8000 Microprocessor to one
"S03XX Interface
An extension to the design is shown in
Figure 14, with the configuration
information shown in Table 7. The M68000
interface to the PSD3XX has a 16-bit data
bus. Both Ports A and B are used to
convey data. The generation of an E input
to the PSD3XX has been extended from
Configuration
CDATA
Bits
the signal inversion shown in Figure 13.
The M68000 has two data strobe signals
(LOS and UDS), to qualify the lower and
upper bytes of a 16-bit word. The LOS
and UDS lines drive the A 18 and A 19
inputs and are gated to provide the correct
logic condition into the M68000.
Function
1
16-bit data bus
CADDRDAT
0
Non-multiplexed address/data
CRRWR
1
Set R/W and E control inputs
CA19/CSI
1
Enable A 19 input
CALE
X
ALE polarity set at "don't care"
CRESET
0
Active LOW RESET
COMB/SEP
0
Combined memory mode
CPAF2
X
"Don't care" Port A
CPAF1
XX
"Don't care" Port A
CPBF
X
"Don't care" Port B
CPCF
110B
Enable A16 and A17 Out, A181n 1
CPACOD
OOH
Configure CMOS buffers Port A
CPBCOD
OOH
CADDHLT
0
Transparent A 16-A19
CSECURITY
0
Security off
Configure CMOS buffers Port B
1. Outputs UDS and LOS drive the A18 and A 19 inputs of the PAD and are gated internally to give a valid E input
signal to the M68000 from the GS9 output. DTAGK comes from the GS8 output.
This application takes advantage of the AS
input which is redundant as a latch control
input in a non-multiplexed system; however, it
can be used as general-purpose logic input to
May, 1993
327
the PAD. CS9 and CS8 are used as output
signals to the M68000's DTACK and BERR
inputs.
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~
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
"9-
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD1 O/A1 0
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
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Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
M6BOOO/
2XPSD3XX
Applications
TableB.
M6BOOO Microprocessor to Two
PSD3XX Devices
in Parallel
With the circuit design given in Figure 15, two
PSD3XX devices are used in a byte-wide
mode. One PSD stores the upper data byte
and one the lower data byte of a 16-bit word.
By using the devices in this way, two 6-bit
wide ports can be created in Port B of each
device. PB6 and PB7 are programmed as
open-drain outputs and wired-OR giving
Configuration
Bits
composite DTACK and BERR feedback
signals to the M68000. The generation of the
E signal for both PSD devices is achieved in
the same way it was in the M68008. The LOS
and UDS inputs (to U2 and U3 respectively)
are inverted by the PAD and drive the relevant E inputs. Table 8 gives the configuration
information relevant to both PSD devices.
Function
CDATA
0
CADDRDAT
0
Non-multiplexed address/data
CRRWR
1
Set R/W and E control inputs
8-bit data bus
CA19/CSI
1
Enable A 19 input1
CALE
X
"Don't care" not used
CRESET
0
Active LOW RESET
COMB/SEP
0
Combined memory mode
CPAF2
X
"Don't care" Port A used for data
CPAF1
XXH
"Don't care" Port A used for data
CPBF
FFH
Port B used for I/O
CPCF
111 B
Configure CS8-CS10 2
CPACOD
OOH
CMOS drivers
CPBCOD
OOH
CMOS drivers
CADDHLT
0
Transparent A 19
CSECURITY
0
No security
1. A 19 input to the PS03XX's is used to receive UOS and LOS from the M68000 microprocessor. These signals are
inverted by the PAD of each PS03XX and fed back to the E input of each divice.
2. CS10 of each PS03XX drives the inverted UOS and LOS back to E input. Port e is programmed to output eS8 and
eS9. Additional byte-wide peripherals can be configured to the system and selected by these signals.
May, 1993
329
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3:
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it
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>
>
U2
~
~
IPLO
IPL1
IPL2
VPA
IP1
IP2
BGACK
c..>
~
23
26
25
~
~
24
~
~
FC1
FC2
VMA
E
29
28
21
22
BGACK
BR
DTACK
BERR
FCO
FC1
FC2
BG
VMA
E
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
~
~
~
---W~
-¥.-
~
2!L
DO
D1
D2
D3
D4
D5
D6
66
D7
D8
D9
D10 ~
D11 ~
D12 ~
D13 ~
D14
D15 ~
U3
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
ADa/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
PAO
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PA6
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21
20
19
18
17
16
15
14
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D2
D3
D4
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D6
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AD4/A4
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AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
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AS
RESET
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
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A17/CS9
21
20
19
18
17
16
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Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
16- Bit Address!
DataPSD3XX
Interface to Intel
80186
PSD3XX
Figure 16 and Table 9 give the configuration
of the PSD3XX in an Intel 80186 system. This
device has a 16-bit multiplexed address/data
bus. Ports A and B are used for data I/O
functions, so this design can take advantage
of the port expansion capability. To distinguish between memory and I/O functions, it is
necessary to decode the S2 output from the
80186. This output line goes directly to the
PAD through Port C bit zero. When LOW,
this signal qualifies a memory access; when
HIGH, it indicates that an 110 operation is in
progress. Programming the PAD can use this
input to differentiate between I/O and memory
access.
Two additional signals from the 80186 are
UCS and LCS (upper chip-select and lower
TableB.
Intel 80186 to
PSD3XX Configuration for CMOS
Ports
May, 1993
Configuration
Bits
chip-select, respectively). The signals have
been included in the system to help minimize
. the requirement for additional glue logic. Both
can be used in the PAD decoder to position
sections of EPROM and RAM. The UCS is
designed to decode addresses FFFFFH to a
programmable limit. The 80186 begins
executing from memory location FFFFOH
after a system reset; thus, this signal should
be used to select EPROM that contain a
system initialization sequence. The LCS has
been designed to program from OOOOOH up to
a programmable limit. In this example, the
RESET line from the 80186 is active HIGH
and drives the RESET input of the PSD301
which is programmed to respond to a HIGH
level.
Function
CDATA
1
16-bit data bus
CADDRDAT
1
Multiplexed address/data
CRRWR
1
Set RD and WR mode
CA19/CSI
1
CSI input to PAD
CALE
X
Active HIGH ALE
CRESET
0
Active LOW RESET
COMB/SEP
0
Combined memory mode
CPAF2
X
I/O Port A
CPAF1
XXH
I/O Port A
CPBF
FFH
I/O Port B
CPCF
OOOB
Input A 16-A18
CPACOD
OOH
CMOS drivers
CPBCOD
OOH
CMOS drivers
CADDHLT
0
Latched A 16-A19
CSECURITY
0
No security
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AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD 13
AD14
AD15
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Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
16-Bit Address!
~ata PS03XX to
Intel 80196
Interface
Table 10.
Intel 80196 to
PS03XX Configuration for LEO
Orivers
Interfacing the
PS03XX to 8-Bit
IIIicroprocessors
ZBO and 1116809
Applications
May, 1993
In Figure 17, the PSD3XX is connected to an
Intel 80196 microcontroller. In many microcontroller applications it is necessary to
illuminate indicators (such as LEOs). Here,
the PSD3XX is used to drive LED indicator
Configuration
Bits
displays. High-efficiency LEOs can be
illuminated through the open drain outputs of
Port B. The configuration information in Table
10 indicates that Port B has open drain
drivers to sink LED illumination current.
Function
CDATA
1
16-bit data bus
CADDRDAT
1
Multiplexed address/data
CRRWR
0
Set RD and WR mode
CA19/CSI
X
"Don't care" A 19/CSI
CALE
0
Active HIGH ALE
CRESET
0
Active LOW RESET
COMB/SEP
0
Combined memory mode
CPAF2
0
I/O Port A
CPAF1
OOH
I/O Port A
CPBF
FFH
I/O Port B
CPCF
OOOB
Output A 16-A18
CPACOD
OOH
CMOS drivers
CPBCOD
FFH
Open drain drivers
CADDHLT
X
"Don't care" (not used)
CSECURITY
0
No security
Figures 18 and 19 illustrate the PSD3XX used
with 8-bit microprocessors, such as the Z80B
and M6809B. Tables 11 and 12 reflect the
configuration of each design, respectively.
The mode of operation is 8-bit data bus with a
non-mUltiplexed address/data input. In the
case of the Z80B, CS8-CS10 inputs are tied
to M1, MREO, and IORO respectively. Since
333
the PAD can be programmed to distinguish
between memory and I/O operations, the
Z80B system has access to an 8-bit data port
Port B. With the M6809B system, CS8 is
used to respond to the MRDY input of the
microprocessor and CS9 and CS1 0 are
available for external chip-select.
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PO.2
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6
5
7
4
11
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ACH1/PO.1
ACH2/PO.2
ACH3/PO.3
ACH4/P0.4
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P4.1/AD9
P4.2/AD10
P4.3/AD11
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P4.5/AD13
P4.6/AD14
P4.7/AD15
RD
WRLlWR
WHE/BHE
ADV/ALE
INST
CLKOUT
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
~~
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58
57
56
55
54
53
25
26
27
28
29
30
~~
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50
49
48
47
46
45
33
35
36
37
38
39
61
40
41
62
63
65
59
58
57
56
55
48
47
~
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P1.1
P1.2
P1.3
P1.4
P1.5
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PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
RD
WR
BHE/PSEN
ALE
RESET
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PB4.5
PB4.6
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9
8
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6
5
4
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42
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PA3.1
PA3.2
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ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
VREF
80196
>
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P3.1/AD1
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Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
Table 11.
180B to PSD3XX
Interface
Configuration
Bits
Function
CDATA
0
8-bit data bus
CADDRDAT
0
Non-multiplexed address/data
CRRWR
0
Set RD and WR mode
CA19/CSI
0
CSI input
CALE
X
"Don't care" (not used)
CRESET
0
Active LOW RESET
COMB/SEP
0
Combined memory mode
CPAF2
X
"Don't care" Port A used for data
CPAF1
XXH
"Don't care" Port A used for data
CPBF
FFH
I/O Port B
CPCF
OOOB
Configure A 16-A 18 as inputs
CPACOD
OOH
CMOS drivers
CPBCOD
OOH
CMOS drivers
CADDHLT
0
A 16-A18 transparent 1
CSECURITY
0
No security
1. A 16-A 18 inputs are used as M1, MREO, and IORO inputs to the PAD from the Z80B output. Use the ALIAS
command in the support software.
Table 12.
M680S to PSD3XX
Interface
May, 1993
Configuration
Bits
Function
CDATA
0
8-bit data bus
CADDRDAT
0
Non-multiplexed address/data
CRRWR
1
Set RlW and E mode
CA19/CSI
0
Enable CSI input
CALE
X
"Don't care" non-multiplexed mode
CRESET
0
Active LOW RESET
COMB/SEP
0
Combined memory mode
CPAF2
X
"Don't care" Port A used for data
CPAF1
XXH
"Don't care" Port A used for data
CPBF
FFH
Port B used for 110
CPCF
111 B
CS8-CS 10 outputs
CPACOD
OOH
CMOS drivers
CPBCOD
OOH
CMOS drivers
CADDHLT
0
"Don't care"
CSECURITY
0
No security
335
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20
22
21
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IORO
WR
RD
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(,,)
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Rl
10K
INT
NMI
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
23
24
25
26
27
28
29
30
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
RESET
r
Cl
BUSRO
BUSAK
CLK
G NO
ZSOB
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01
02
03
04
05
06
07
GND
ADO/AO
AD1/Al
AD2IA2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7
AD8/A8
AD9/A9
AD10/Al0
ADll/All
ADl21A12
AD13/A13
AD14/A14
AD15/A15
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
RD
WR
BHEIPSEN
ALE
RESET
21
20
19
18
17
16
15
14
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A17/CS9
A18/CS10
A19/CSI
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33
RESET
NMI
HALT
IRO
1
FIRO
MRDY
DMAIB
S
9
10
11
12
13
14
15
16
17
1S
19
20
21
22
23
ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
ADS/AS
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
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0
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A1
A2
A3
A4
A5
A6
A7
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A9
A10
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A12
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A15
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PA6
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PB1
PB2
PB3
PB4
PB5
PB6
PB7
A16/CSS
A17/CS9
A18/CS10
A19/CSI
42
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GND
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Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
PSD3XX
Interface to the
InteI8D2B6
Table 13.
Intel8D286 to
PSD3XX Interface
May, 1993
Figure 20 provides a schematic of the
PSD3XX interface to an 80286. The device is
configured for a 16-bit data bus in the nonmultiplexed mode. Ports A and B are converted automatically for use as a bi-directional
data path into the PSD3XX. (This was also
Configuration
CDATA
Bits
1
the case for the M68000 microprocessor). To
eliminate (or lessen) glue logic, CS1 and CS2
are generated from the internal PAD. This is
programmed as an address decoder. Table
13 provides configuration information relevant
to this system design.
Function
16-bit data bus
CADDRDAT
0
Non-multiplexed address/data
CRRWR
0
Set RD and WR control inputs
CA19/CSI
1
Enable A19 input
CALE
X
"Don't care" non-multiplexed mode
CRESET
1
Active HIGH RESET
COMB/SEP
0
Combined memory mode
CPAF2
X
"Don't care" Port A used for data
CPAF1
XXH
"Don't care" Port A used for data
CPBF
XXH
"Don't care" Port B used for data
CPCF
011B
A16 input; CS9 and CS10 outputs
CPACOD
OOH
CMOS drivers
CPBCOD
OOH
CADDHLT
0
Transparent A16-A19 input
CSECURITY
0
No security
CMOS drivers
338
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A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
~
co
~
ur
AD8/A8
AD9/A9
AD1 O/A1 0
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
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Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
External
Peripherals to the
PSD3XX/MBBHC11
Configuration
Table 14.
M6BHCII/PSD3XX
to External
Peripheral
MBB2.
Interface
May, 1993
PSD3XX
The configuration in Figure 21 illustrates how
the user can feed address outputs from the
internal latch to Port A. Addresses AO-A?,
derived from a multiplexed address/data bus,
can go directly to an additional peripheral
without the need for an additional octal latch
such as the ?4HC3?3 or ?4HC5?3. Port A
can be used for address outputs AO-A? while
PBO-PB? can be used as chip-selects. Lines
AO-A4 of the PSD3XX drive the RS1-RS5
register select inputs of the M68230. For the
M68HC11, the eight bits of address and data
come from its PC port PCO-PC? (ADO-AD?)
and are latched by the AS input. Configured
in this mode, the PSD3XX can address and
map additional peripheral chips. Port A of the
PSD3XX conveys the internally latched
Configuration
Bits
address outputs AO-A? to the output and can
be used to address registers in the peripheral
chips while Port B outputs can place individual peripherals at peripheral or memorymapped boundaries. Thus, a number of
additional chips can be sale\;ted through Port
B. This effectively car. increase the port
density of the system design. The general I/O
capability can then be extended to extra
ports, timers, UARTs, serial communications
channels, keyboard interface devices, CRT
controllers, etc. without the need for additional
glue logic. Table 14 highlights the configuration information programmed into the PSD3XX
when configuring the M68HC 11 to a M68230
peripheral.
Function
CDATA
8-bit data bus
0
CADDRDAT
1
Multiplexed address/data
CRRWR
1
Set RIW and E mode
CA19/CSI
0
Set power-down mode
CALE
0
Active HIGH AS
CRESET
0
Active LOW RESET
COMB/SEP
0
Combined memory mode
CPAF2
0
Port A
CPAF1
FFH
=address AO-A?
Port A set for address
CPBF
OOH
Port B set for chip-select
CPCF
111 B
Port C set for chip-select
CPACOD
OOH
CMOS buffers
CPBCOD
OOH
CMOS buffers
CADDHLT
X
"Don't care"
CSECURITY
0
No security
340
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Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
Additional
External SRAM
Table 15.
M68HC11/PSD3XX
Configured to
Address
Additional SRAM
May, 1993
Figure 22 illustrates how additional SRAMs
can be configured into a system. This
PSD3XX configuration is not limited to external peripheral expansion; it can also be used
to add additional memory without the need for
external glue logic. With an 8-bit address/
data multiplexed scheme, the higher-order
addresses (A8-A 15) are non-multiplexed.
These address lines are fed directly to the
Configuration
Bits
external SRAM from the microcontroller and
do not need to go through the PSD3XX
These lines can drive the RAM chip directly.
Thus the M68HC11 system, which is highly
memory-intensive and requires more RAM
than the microcontroller and PSD3XX can
supply, can take advantage of the configuration shown in Figure 23 which is detailed in
Table 15.
Function
CDATA
1
CADDRDAT
0
Multiplexed address/data
CRRWR
1
Set R/W and E mode
CA19/CSI
1
Set power-down mode
8-bit data bus
CALE
0
Active HIGH AS
CRESET
0
Active LOW RESET
COMB/SEP
0
Combined memory mode
CPAF2
0
Port A = address AO-A 7
CPAF1
FFH
Port A set for address
CPBF
OOH
Port B set for chip-select
CPCF
111 B
Port C set for chip-select
CPACOD
OOH
CMOS buffers
CMOS buffers
CPBCOD
OOH
CADDHLT
X
Latched A 16-A19 "don't care"
CSECURITY
0
No security
342
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Application Note 011
Philips Semiconductors MicrocontrolJer Peripherals
PSD3XX
PSD3XX Device Description
Additional
External SRAM
(Cont.)
Figure 23 illustrates, and Table 16 details, a
similar system using the Signetics
SC80C451. This microcontroller has many
ports and some SRAM but requires off-chip
EPROM to store programmed instructions.
This device is similar to the 8051/31 family
which uses the active LOW PSEN signal to
differentiate between executable code and
data. Since it is a multiplexed 8-bit machine,
it can use the on-chip latches. In highly RAMintensive applications, an additional two 8K x
8 SRAM chips can be included and selected
through Port B. If additional SRAM chips are
not needed, Ports A and B can recreate Ports
and 2 which are lost in addressing external
memory.
o
Table 16.
SCB0C451/
CDATA
1
8-bit data bus
PSD3XX
CADDRDAT
0
Multiplexed address/data
CRRWR
0
Set RD and WR mode
CA19/CSI
0
Set power-down mode
CALE
0
Active HIGH ALE
CRESET
1
Active HIGH RESET
COMB/SEP
1
Separate data/program memory
Configured to
Address
Additional SRAM
May, 1993
Configuration
Bits
Function
= address AO-A 7
CPAF2
0
CPAF1
FFH
Port A set for address
CPBF
OOH
Port B set for chip-select
CPCF
111 B
Port C set for chip-select
CPACOD
OOH
CMOS buffers
CPBCOD
OOH
CMOS buffers
Port A
CADDHLT
0
"Don't care" (not used)
CSECURITY
0
No security
344
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PO.2/AD2
PO.3/AD3
P0.4/AD4
PO.5/AD5
PO.6/AD6
PO.7/AD7
(;:::l
P2.0/AB
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
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RD/P3.7
WR/P3.6
T1/P3.5
TO/P3.4
INT2/P3.3
INT1/P3.2
TXD/P3.1
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Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
PSD3XX Used in
Track lfIIade
Figure 24 illustrates a design that utilizes the
track mode of operation that has been
discussed but not illustrated in an application.
Here, Port A passes or tracks through the
multiplexed address and data of the 80196.
Address and data outputs ADO-AD7 from the
80196 appear on the PSD3XX Port A pins. In
this mode, the SRAM, shown in Figure 24 as
U4, can be accessed either by the 80196
(used in byte mode) or by a second processor
in the host system. The SRAM in the design
can be used as a common resource. An
example would be a system in which the host
uses the memory to pass parameters to the
local 80196. Table 17 gives the configuration
data for an 80196/PSD301 interface to SRAM
using Track Mode.
A Direct Memory Access can transfer data to
the common memory via a BUSRQ/BUSGR
handshake. Note that the PAD in the
PSD3XX controls the three-state condition of
the octal latch U3 74HCT373 enabling the
host system to control SRAM addresses
AO-A7. Port A of the PSD3XX is also put into
Table 17.
Intel80196 to
PSD3XX Used to
Access External
SRAIfII in Track
lfIIode
May, 1993
Configuration
Bits
a three-state condition during host-to-SRAM
activity. In the design given in Figure 24, Port
B outputs PBO, PB1, and PB2 are used to
control the SRAM inputs CE, OE, and WR respectively. Also, A8, A9, and A10 are fed
through the PAD as identity functions to the
open drain drivers of PB3, PB4, and PB5
respectively. There is no track-through
feature for these address lines; however, if
they are fed through the PAD, they can drive
the external memory resource as if they were
tracked through.
The M80196 can operate in either byte- or
word-wide mode controlled by its BUSWIDTH
input. In this application, the PB6 output
drives the BUSWIDTH line to switch between
the byte-wide bus of the external SRAM and
the word-wide interface of the PSD3XX. All
Port B outputs, with the exception of PB6, are
configured as open-drain. Provided the host
system also has open drain/ collector drivers,
both systems can access the SRAM without
bus conflict. The only additional circuitry required would be the pull-up resistors.
Function
CDATA
1
16-bit data bus
CADDRDAT
1
Multiplexed address/data
CRRWR
0
Set RD and WR mode
CA19/CSI
0
Set power-down mode
CALE
0
Active HIGH ALE
CRESET
0
Active LOW RESET
COMB/SEP
0
Separate data/program memory
CPAF2
1
Address/data (Track Mode)
CPAF1
XXH
"Don't care" in Track Mode
CPBF
OOH
Port B set for chip-select outputs
CPCF
111 B
Port C set for logic outputs
CPACOD
OOH
CMOS buffers
CPBCOD
FFH
Open drain buffers
CADDHLT
X
Latched A 16-A 19 "don't care"
CSECURITY
0
No security
346
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64
16
NMI
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CDE
BUSWIDTH
RESET
ACHO/PO.O
ACH1/PO.1
ACH2/PO.2
ACH3/PO.3
ACH4/PO.4
ACH5/PO.5
ACH6/PO.6
ACH7/PO.7
~
....
P2.0/TXD
P2.1/RXD
P2.2/EXINT
P2.3!T2CLK
P2A!T2RST
P2.5/PWM
P2.6!T2UP-DN
P2.7!T2CAPTURE
HSI.O
HSI.1
HSI.2/HSOA
HSI.3/HSO.5
VREF
P3.0/ADO
P3.1/AD1
P3.2/AD2
P3.3/AD3
P3.4/AD4
P3.5/AD5
P3.6/AD6
P3.7/AD7
P4.0/AD8
P4.1/AD9
P4.2/AD10
P4.3/AD11
P4A/AD12
P4.5/AD13
P4.6/AD14
P4.7/AD15
60
59
58
57
56
55
54
53
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
23
24
25
26
27
28
29
30
52
A8
51 "A9
50 --" A10
49~ A11
48
A12
47
A13
46
A14
45
A15
31
32
33
35
36
37
38
39
U2
'ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
U4
DO
D1
D2
D3
D4
D5
D6
D7
AD8/A8
AD9/A9
AD10/A10
AD1 VA1 1
AD12/A12
AD13/A13
AD14/A14
AD15/A15
RD
WR
BHE/PSEN
ALE
RESET
r.S1
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
I
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01
02
03
04
05
06
07
2
5
6
9
12
15
16
19
OC
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A1
A2
A3
A4
A5
A6
A7
A8
A9
AlO
8
7
6
5
4
3
2
1
23
22
19
CS
RD
WR
18
20
21
ALE 74HCT373
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
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D3
D4
D5
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9
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11
13
14
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16
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A17/CS9
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A18/CS10
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P1.3
P1.4
P1.5
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Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
May, 1993
PSD3XX
348
Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
PSD3XX
Chapter a
The support software for the PSD3XX
family is designed to run on IBM PC XT/AT
or 100% compatible systems. It is
menu-driven and very user-friendly. In
many cases it has the capability of
preventing the user from creating invalid
configurations. For example, in a
non-multiplexed system with a 16-bit data
bus, Ports A and B are used for data 1/0.
The software recognizes this and prevents
Figure 25.
MAPLE Main
Menu
-------[;~L~1~~!fht(Cl
I
~~-
---~--
the user from inadvertently programming
Ports A and B as regular ports.
When running in the IBM PC environment,
the PSD development software creates the
menu shown in Figure 25. Initially, the
designer selects the part type with the user
key F8 or moves the screen cursor to
PARTNAME. In the example shown, the
selection for the part type is PSD301.
1988, W.ferSe.le Integr.tion, Inc
------------------------- -
F1
~
Part name
Reoi",,''-
--------------------
DOS
FZ
EXIT
F3
F4
F?
MAPPRO
PARTLIST
LOAD
SAVE
COMPILE
FB
PARTNAME
F5
F6
3,,;:=J
-------~~~----I
------~-
IJERS lOti 3.008
: PSD3al
Specify PARTNAME to be configured and press .
Cursor
~
Up:! Down:l
C:\WSI
240225
The menu listed to the left of Figure 25 links
the function keys and their association. F1
suspends the MAPLE software to DOS for file
editing or updating. F2 exits the program and
returns the user to the DOS environment. F3
selects the programmer option so the user
can program the compiled object file into the
PSD301 device provided a programmer is
connected to the system. The LOAD selection (F5), loads an existing program into the
MAPLE environment for editing and compiling. F6 saves that program under a user-
May. 1993
349
defined name. F7 compiles the user-generated file into an object file that can be transferred to the programmer. F8 provides part
type selection, either PSD301 or MAP168.
Figure 26 illustrates a second menu to the
right of the main menu. The list shows
ALIASES, CONFIGURATION, PORT C,
PORT A, PORT B, and ADDRESS MAP. The
designer selects each choice, starting from
ALIASES, and moves down through the list
configuring each option.
Application Note 011
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSD3XX Device Description
Figure 26.
MAPLE Menu
with PARTNAME
Submenu
~
N 3.00B
~--
988 ~_~aferSca Ie _~
F1
FZ
F3
F1
F5
F6
F7
FO
If you want to
DOS
EXIT
I'IAPPRO
PARTLIST
LOAD
SAVE
COI'IPILE
PART"AI'IE
na~e so~e
Cursor - Up:' Down:!
_ _ _ __
~
PARTNAME: PSD301
ALIASES
CO"FIGURAT 10"
PORT C
PORT A
PORT B
ADDRESS I'IAP
signals, press .
F1 - Return to Main Menu
Cursor - Up:t Down:!
FZ -
Temporar~
exit to Dos.
240230
Figure 31.
PortS
Configuration
Menu
Figure 31 gives the configuration of Port B.
This is similar to the configuration pattern for
the M68008 shown in Figure 13. Here, CS6
and CS7 have been programmed as opendrain outputs connected to the microprocessor's DT ACK and BERR, respectively.
-------------------------------------------------_.------_.-.. -
PORT B
PUt
PBa
PB1
PB2
PB3
PB4
PB5
PB6
1m.
CS/IO
csa
CS1
CS2
CS3
CS4
CS5
CS6
CS?
CMOS/OD
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
on
.w.
If you haue CMOS output for
F1 - Return to Main Menu
F3 - Goto CS Definition
PB? press SPACEBAR.
FZ - Temporary exit to Dos
Cursor - Up:t Down:! Left:.
240231
May, 1993
353
Right:~
Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
Figure 32.
ADDRESS MAP
Menu
PSD3XX
Figure 32 shows the ADDRESS MAP menu.
The designer can enter a binary code for the
address range of the various select lines;
ESO-ES7, RSO, and CSP, being the EPROM,
SRAM, and PERIPHERAL assignments,
respectively. A space for individual hexadecimal files is reserved under the FILENAME
section. The Intel MCS files are listed as they
would be compiled and programmed into the
device.
ADDRESS MAP
FILE NAME
HilT .nes
l.nes
.Mes
.nes
l.nes
l.nes
Fill in A19-A11 (Binary) or SEGMT START (Hex); and FILE(START. STOP)
and FILE NAME. Use SPACEBAR to erase any field value.
F1 - Return to Main Menu
FZ - Temporary exit to DOS
F3 - Goto Help
Cursor - Up:T Down:! Left:. Right:~
N - Non-editable bit.
e:,wsI
240232
After configuration has been established, the
user can return to the main menu and select
the COMPILE option. The configuration is
compiled and converted to a JEDEC array
program map.
When successfully finished, the designer can
select the MAPPRO option (see Figure 25),
and when a WSI MAGICPROTM programmer
May,1993
354
is available in the PC system, finalize the
design by programming a PSD301 .
The Address Map for Port B can be configured as shown in Figure 33. Per Figure 31,
depress function key F3 to invoke the chip
select definition. The entries can be made for
logic HIGH, LOW, or "don't care" conditions.
Philips Semiconductors Microcontroller Peripherals
Application Note 011
PSD3XX Device Description
Figure 33.
PortB
Configuration
Menu with
Address Map
...PI"
PBl
PB2
PB3
PBi
PBS
PB6
PB?
CS/IO CMOS/OD
CMOS
CS1
CMOS
CS2
CMOS
CS3
CMOS
CSi
CMOS
CSS
CMOS
CS6
CMOS
CS?
CMOS
PSD3XX
PORT B
II
AlB Al? Al6 AlS Ali A13 Al2 AU ALE
a
a
a
1
1
1
II
m ..."{o
I
1
1
X
RD
WR
x lEI
CS definition is the "OR of the product terMs{rows). Enter 1 to select
Actiue High signal, a to select Actiue Low signal, X to Mean 'don't
care', SPACEBAR to erase. Enter ualues in coluMns releuant to your
application; other blank coluMns will be treated as 'don't care's.
Fl - Return to PORT B
Cursor - Up:! Down:'
Left:~ Right:~
C:\WSI
240231
Summary
May, 1993
The PSD3XX microcontroller peripheral with
memory, supported with low-cost software
and programming capability form WSI,
greatly simplifies the overall design of
microcontroller based systems. The key
advantage is the extensive condensing of
glue logic, latches, ports, and discrete
memory elements into a single-device,
355
enhancing the reliability of the final product.
Applications for the device extend to practically any area that uses microcontrollers or
microprocessors, from modems and vending
machines to disc controllers and high-end
processor systems.
Philips Semiconductors Mlcrocontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter design By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
PSD301
WSI
Abstract
A smart transmitter design is described
which takes advantage of the integration
capabilities and flexibility of WSl's
PSD301 microcontroller peripheral. The
following discussion illustrates how the
PSD301, in effect, was responsible for
eliminating an extra 2.5 inch diameter
board in a system where real estate is at
a premium by reducing the number of
components from 12 down to 5.
Introduction
Designers of systems using microcontrollers and microprocessors often
face the problem of how to integrate
peripheral logic and memory functions
into their designs without using many
discrete chips and large areas of board
space. For example, when external
EPROM and SRAMs are configured into
systems with ROM less microcontrollers,
general 1/0 ports are typically sacrificed
for address, data input/output, and control
functions. When these I/O ports are
depleted, the total chip count of the
system is increased by requiring the use
of additional external ports and steering
logic. Designers, who have limited board
space, such as found in the disk drive,
modem, cellular phone, industrial/process
control, and automotive industries, find
this a critical problem.
The Design
Application
The smart transmitter, shown in Figure 1,
was developed by Bailey Controls, a
manufacturer of process control
instruments, to support a popular field
bus protocol. One of its functions in this
sensor application is to measure
pressure, differential pressure, and flow
rates through pipes in industrial
environments such as chemical plants, oil
refineries, or utility plants. A host system
monitors the transmitter via a process
control network.
The completed transmitter design
consists of three main boards. The first
board includes the power supply and
communications hardware to provide
power to the rest of the system and feedback to the process control network. It
consists of communications transformers
and line drivers/receivers.
May, 1993
357
The PSD301 programmable peripheral
device from WSI solves this problem by
integrating all SRAM, EPROM, programmable decoding and configurable I/O port
functions needed in 8 or 16-bit microcontroller designs into a single-chip
user-configurable solution. This is
illustrated in the following industrial
control application where the PSD301
eliminates seven chips and saves the
designer from needing another board in
the system.
The second board is the digital microcontroller board and contains the 68HC11
microcontroller as well as the PSD301
programmable peripheral, a PLD, UART,
and LCD display. Its function is to
communicate and receive the inputs from
the third board, process the data, and
display the appropriate results to the LCD.
The third board or input board is mostly
analog. It receives inputs from string gauge
sensors which use a bridge circuit for
measuring pressure using a diaphragm.
The input board then converts the signals
so the microcontroller can read them.
Philips Semiconductors Microcontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter design By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
WSI
PSD301
Figure 1.
"Smart"
Transmitter from
Bailey Controls
... Pressure/Flow
Design
Considerations
May, 1993
The smart transmitter system is rather
small. Its case is only 2.5 inches in
diameter and thus requires boards that
fit this small form factor as shown in
Figure 2. Not surprisingly, the major
design consideration during development
was board space. This was especially
true for the microcontroller/digital board
where real estate is at a very high
premium.
meant extending the number of boards
used beyond one unless a way could be
found to integrate some of these
elements.
One of the problems was that there were
already requirements for the 68HC11
microcontroller, a 256K EPROM, 16K
SRAM, a PLD, TTL logic, a UART, and
an LCD display on the digital board. This
To meet these objectives, Bailey Controls
looked to user-configurable peripheral, the
PSD301 , for its integration capabilities, its
flexibility, and its low power of less than 35
rnA active and 90 JlA typical powerdown.
358
Other important considerations, or goals
actually, for the design were to reduce
power consumption to less than 2.4W,
improve reliability, lower design costs,
and shorten the time-to-market.
Philips Semiconductors Microcontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter desig n By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
WSI
PSD301
Figure 2.
The Bailey Smart
Transmitter Board
Using the WSI
I'S0301.
I'S0301
Architecture
The PSD301 is a field programmable device
that has the ability to interface to virtually
any 8- or 16-bit microcontroller without the
need for external glue logic. This is possible
because the PSD301 combines the
elements necessary for a complete
microcontroller peripheral solution, such as
user-configurable logic, 110 ports, EPROM
and SRAM, all into one device. The
functional block diagram of the PSD301 in
Figure 3 shows its main sections: the
internal latches and control signals, the
programmable address decoder (PAD), the
memory, and the I/O ports.
The control signals and internal latches in
the PSD301 were designed so interfacing
to any microcontroller would be easy and
require no glue logic. For instance, the
PSD301 can interface directly to all
multiplexed (and non-multiplexed) 8- and
16-bit microcontroller address/data buses
because it has two on-chip 8-bit address
latches. This means no external latches
are required to interface to multiplexed
buses. It also has programmable polarity
on the control inputs ALE/AS and RESET,
so they can be configured to be active high
or active low.
The other control signals, RD/E, and
WR/R/W, are also programmable as /RD
and /WR or E and R/W, enabling direct
interface to all Motorola- and Intel-type
controllers.
May, 1993
359
The programmable array decoder (PAD) is
an EPROM-based reprogram mabie logic
"fuse" array with 11 dedicated inputs, up to
4 general-purpose inputs, and up to 24
outputs. The PAD is used to configure the 8
EPROM blocks on 2K word boundaries and
the SRAM on a 1K word boundary
anywhere within a 1 Meg address space. It
is also used to generate a base address for
mapping ports A and B, as well as to
provide mapping for the track mode. The
PAD, like a traditional PLD, can generate up
to eight sum-of-product outputs to extend
address decoding to external peripherals or
to implement logic replacement on a board.
Memory in the PSD301 is provided by
EPROM for program and table storage and
SRAM for scratch pad storage and
development and diagnostic testing. The
EPROM density is 256K bits and the SRAM
density is 16K bits. Both can be operated in
either word-wide or byte-wide fashion,
which translates to a 32K x 8 or 16K x 16
EPROM configuration and a 2K x 8 or 1K x
16 SRAM configuration. As described
above, the EPROM is divided into 8 blocks
(of 4K x 8 or 2K x 16), with each block
typically on a 2K boundary locatable within
a 1 Meg address space.
There are 3 ports on the PSD301 that are
highly flexible and programmable: Ports A,
Band C, illustrated in Figure 4. Port A is an
Philips Semiconductors Microcontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter design By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
WSI
'S0301
Architecture
(Cont.)
8-bit port that can be configured in a variety
of ways. For example, if the PSD301 is in
the multiplexed mode, port A can be
configured pin-by-pin to be an I/O or a lower
order latched address. Alternatively, port A
can be configured in the track mode to
transfer 8 bits of address and data inputs
through port A. This enables the microcontroller to share external resources, such
as additional SRAM, with other controllers.
In either case, each port A output can be
configured to be CMOS or open drain. If the
PSD301 is in the non-multiplexed mode,
port A becomes the lower order data for the
chip.
Port B is another flexible 8-bit port. In the
multiplexed mode or 8-bit non-multiplexed
mode, each pin on port B can be
customized to function as an I/O or a
chip-select output. The chip-select signals
are determined by the PAD programming
Simple
Interfaces
to the 'S0301.
One of the overwhelming advantages of the
PSD301 is its ability to interface to virtually
any microcontroller without any glue logic,
while providing additional I/O ports and
memory. This is accomplished by
configuring or programming the part to
function in an operational mode geared for
a specific application.
For instance, there are 45 configuration
bits on the PSD301 that have to be
programmed in addition to the EPROM
prior to usage. These configuration bits are
determined during development by the
designer using the WSI MAPLE software
package. After the configuration bits are
determined, the EPROM code and
configuration data can be merged during
compilation and the part subsequently
programmed.
Interfacing the PSD301 to different
microcontrollers is accommodated by the
configuration bits discussed above. To
illustrate how this works, two examples are
provided.
May,1993
360
PSD301
and are used for general logic replacement
or to extend the address decoding to
external peripherals. Each pin in this mode
can also be programmed to have a CMOS
or an open drain output. In the 16-bit
non-multiplexed mode, port B becomes the
higher order data for the chip.
Port C is the third port which is available on
the PSD301. It is a 3-bit port that can be
programmed on a pin-by-pin basis to be
chip-select outputs and/or general-purpose
logic inputs or addresses to the PAD.
Some uses for port C might be to extend the
address range to 1 Meg, or to create finer
address decoding resolution down to 256.
Or, one might use port C to help create a
simple state machine.
The first example is with the 80C196
microcontroller. This 16-bit microcontroller
from Intel interfaces directly to the PSD301,
providing it with additional off-chip program
store EPROM and data store SRAM, as
well as the flexibility that comes with three
additional I/O ports. As illustrated in Figure
5, the 80C196's 16-bit multiplexed address/
data bus and control signals (RD,WR,
BHE, ALE, RESET) connect directly to the
PSD301. This is achieved with the PSD301
in the following configuration:
o
o
o
o
o
o
o
16-bit data bus
Multiplexed address/data
RD and WR mode set
Active HIGH ALE
Active LOW RESET
A 16 A 18 configured as output
Combined memory mode
The other configuration options that are
available, but not listed above, are application dependent and can be changed to
meet the requirements of the design. For
instance, on e!!!..43 (A 19/CSI), the powerdown option CSI could be selected if
Philips Semiconductors Microcontro\ler Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter desig n By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
WSI
Simple
Interfaces
to the I'SD301
(Cont.)
power consumption savings is important.
If it isn't and another logic input to the
PAD would be helpful, A 19 could be
selected. And, if open-drain drivers are
important on one of the ports to drive a
display, for example, they also could be
selected instead of CMOS drivers.
All other microcontrollers have simple
interfaces to the PSD301 as well. This
includes all the variations of microcontrollers in the 8-bit 68HC11 family
from Motorola. For simplicity's sake, the
PSD301 interface to 68HC11 versions
with multiplexed address/data buses will
be discussed, although the nonmultiplexed versions will interface to the
PSD301 in a similar manner, except in
this case port A will become dedicated for
8-bit data.
Figure 6 illustrates the interconnections
between the PSD301 and the 68HC11
microcontroller with multiplexed
address/data buses. Again, all the
The ''Smart''
Transmitter
Design.
The microcomputer-based smart
transmitter design, by Bailey Controls,
requires program store 256K bits EPROM
for storing algorithms and data store 16K
bits SRAM for storing A/D, communication and LCD routines. It also
requires two octal latches, a PLD, and a
variety of glue logic to interface to its
68HC11 microcontroller, UART, and LCD
display. This is illustrated in Figure 7. Of
course, with board space on the digital
board being limited, another board would
have been needed to accommodate
these components, unless they in some
way could be integrated.
This is where the PSD301 provides
exceptional value. As discussed, the
PSD301 already integrates EPROM,1
SRAM,2 a PLD, and other glue logic all
May, 1993
361
PSD301
address/data connections are direct, as
well as the control signals (E, R/W, AS,
and /RESET). Because BHE/PSEN is not
used, this PSD301 input signal is tied
HIGH.
The PSD301 must be programmed using
WSl's MAPLE software package in the
following modes to achieve this
configuration:
o
o
o
o
.0
o
8-bit data bus
Multiplexed address/data
R/W and E mode set
Active HIGH AS (ALE)
Active LOW RESET
Combined memory mode
Again, other parameters on the PSD301
can be set to fit additional design
requirements. These include the security
bit, the port I/Os, and the PAD inputs and
outputs.
on one chip. It interfaces to the 68HC11
directly and actually integrates 8 chips
from the alternative design into one,
eliminating the need to add another board.
The resultant architecture is illustrated in
Figure 8.
Note that in the alternative design shown
in Figure 7, ports typically lost when
connecting the microcontroller to external
memory had to be recreated externally with
latches and buffers when memory was
connected to the microcontroller. With the
PSD301, these ports are recreated internally, eliminating the latches and buffers.
For example, to interface the PSD301 to
the 24-character LCD display, each pin of
Philips Semiconductors Microcontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter design By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
WSI
The "Smart"
Transmitter
Design
(Cont.)
Figure 3.
PSD301
Architecture
PSD301
Other TTL logic is not required to interface
to the 68HC11 's control signals, memory,
or peripherals either. It is all integrated in
the PSD301 . Thus, a smaller PLD than
originally thought required in the design
was used - a 16V8 instead of a
22V10 - because the PAD was able to
reduce the amount of logic by creating
chip selects for the UART and other logic
functions.
port A is configured as an I/O and mapped
to the byte-wide LCD data inputs. Then to
write to or read from the LCD display, port
A is accessed like a memory-mapped
peripheral via an address offset from the
base CSIOPORT defined in the PAD.
Since port A is qualified by and handled
through the PAD, there is no need for an
external octal latch.
A16-A18
-
A11-A15
L
A
T
C
H
AD8-AD15
~
AS-A1D
A19
CSI
CSIOPORT
A19
CSI
PADA
ALE/AS
RD
WR
RESET
WR
13 P.T.
PROG.
PORT
EXP.
PCO-
PAD B
ALE/AS
RD
r--
LOGIC IN
27 P.T.
RESET
r-+CS8-
PORT
C
~
CS10
I ALE/AS
---
'--
AD 0-AD7
EPROM
256K BIT
ES7
ES6
ES5
ES4
ES3
L
A
T
C
H
-
~
~.
~
r--
-~----
~
MUX
~
-- 1"<]
.- -
~
----
--+-
32K BIT
BLOCK
J~
----
.-
r--
--.. <]
CSOCS7
~
SRAM
16K BIT
TRACK MODE
SELECTS
t
-
PROG. CHIP
CONFIGURATION
-
WR/R/W
- -
BHE/PSEN
RESET
X8, X16
MUX or NON-MUX BUSSES
SECURITY MODE
PROG.
CONTROL
SIGNALS
A19/CSI
May, 1993
j
362
PROG.
PORT
EXP.
PADPORT
A
ALE/AS
-
~
DO-D7
AO-A7
ADO-AD7/DO-D7
RD/E
PBOPORT
B
CSIOPORT
I-
-
r
D8-D15
PROG.
PORT
EXP.
~
Philips Semiconductors Microcontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter desig n By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
WSI
Figure 4.
PSD301
Multiplexed
Address/Data
Configuration
A8 -
A15,
PORT A
AD8 - AD15
ALE
Figure 5.
General
Schematic
Diagram of
the BOC196
andPS0301.
I/O or AO - A7 or ADO - AD7
PORT B
ADO - AD7
I/O or CSO -
Vcc
12
3
43
14
64
Xl
X2
NMI
READY
CDE
BUSWIDTH
RESET
GND
ACHO/PO.O
ACH1/PO.l
ACH2IPO.2
ACH3/PO.3
ACH4/PO.4
ACH5/PO.5
ACH6/PO.6
ACH7/PO.7
P2.0ITXD
P2.1/RXD
P2.2/EXINT
P2.31T2CLK
P2.41T2RST
P2.5/PWM
P2.61T2UP·DN
P2.71T2CAPTURE
HSI.O
HSI.l
HSI.2/HSO.4
HSI.3/HSO.5
13
12
2
PSD301
P3.0/ADO
P3.1/ADl
P3.2/AD2
P3.3/AD3
P3.4/AD4
P3.5/AD5
P3.6/AD6
P3.7/AD7
P4.0/AD8
P4.1/AD9
P4.2/AD10
P4.3/ADll
P4.4/AD12
P4.5/AD13
P4.6/AD14
P4.7/AD15
_
RD
WRUWR
WHElBHE
ADV/ALE
INST
CLKOUT
Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.5
Pl.6
P1.7
VREF
ANGND
EA
HSO.O
HSO.l
HSO.2
HSO.3
60
59
58
57
56
55
54
53
23
24
25
26
27
28
29
30
52
51
50
49
48
47
46
45
31
32
33
35
36
37
38
39
61
40
22
1
13
3
ADO/AO
AD1/Al
AD2/A2
AD3/A3
AD4/A4
ADS/AS
AD6/A6
AD7/A7
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
AD8/A8
AD9/A9
ADlO/Al0
ADll/All
AD12/A12
AD13/A13
AD14/A14
AD15/A15
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
RD
WR _
BHE/PSEN
ALE
RESET
U2
VCC
Rl
10K
GND
363
A16/CS8
A17ICS9
A18/CS10
A19/CSI
21
40
41
42
43
GND
1
U1
May, 1993
CS7
A16, A17, A18 or CS8, CS9, CS10
PORT C
80196
11
PSD301
C3
O.Ol~F
Philips Semiconductors Microcontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter desig n By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
WSI
PSD301
Figure 6.
General Schematic
Diagram of the
68HC11and
I'SD301.
FI
C2
Cl
I 2 0PF
20P
68HC11A8
GND
EXTAL
IRQ
XIRQ
RESET
PAOIIC3
PA1/IC2
PA211Cl
PEO/ANO
PE1/ANl
PE2/AN2
PE3/AN3
POO/RXD
P0111XD
PD2/MISO
PD3/MOSI
P04/SCK
PDS/SS
MODB
MODA/LiR
XTAL
PCO/ADO
PC1/ADl
PC2/AD2
PC3/AD3
PC4/AD4
PCS/ADS
PC6/AD6
PC7/AD7
PBO/AB
PB1/A9
PB2/Al0
PB3/All
PB4/A12
PBS/A13
PB6/A14
PB7/A1S
23
24
2S
26
27
2B
29
30
16
lS
14
13
12
11
10
9
31
32
33
3S
36
37
3B
39
22
2
1
13
3
43
PA3/0CS/OCl
PA4/0C4/0Cl
PAS/OC3/0Cl
PA6/0C2/0Cl
PA7/PIA/OCl
STRB/RIW
STRA/AS
GND
VRL
VRH
27
2B
26
ADO
ADl
AD2
AD3
AD4
ADS
AD6
AD7
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
ADB
AD9
AD10
ADll
AD12
AD13
AD14
AD1S
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
E
RIW
BHE/PSEN.
AS
RESET
A19/CSI
PCO
PCl
PC2
U3
21
22
vcc
U1
PSD301
GND
30
31
32
33
34
3S
36
37
3B
GND
VCC
VCC
MC34064
1
Rl
lk
VDD
RESET
GND
U2
GND
May. 1993
364
R3
lk
Philips Semiconductors Microcontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter desig n By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
WSI
Figure 7.
Detailed Block
Diagram of
Bailey Control's
Alternative
Design Solution
Without PSD301.
!,....---.T----.-----.--!-----T---il
.....
i"
INTEGRATOR
&
COMPARATORS
roo--GLUE LOGIC
I
I
I
I
MULTIPLEXERS
SELECTORS
T
6~7g~~1
CONTROLLER
74HC10
74HCOO
74HC08
74HC14
POWER
SUPPLY
I
1
1
rr-NPUT
SENSOR
PSD301
B
HC373
LCD
I - - OCTAL
I
I r-- LATCH
I
r
I L-t-........- - - - - - '
hl '- : ;
SMART
XMITIERI....
UART
COMMUNICATION
TRANSFORMERS
,.....-
~
1
~1~A~D~DRiiEiiSS"/_"""'IIIiI!. . ._
...
I" DATA
BUS
IVOLTAGE
REGULATOR
ADD/DATA
OCTAL
LATCH
II ~
r--t....-
---
HC373
'-
.........
EPROM
32K
~
4
:
SRAM
2K
PAL
1
1
LINE
DRIVERS
&
22V10 ~ RECEIVERS
1
Ii
~----------------------------~
INPUT BOARD
BLOCK DIAGRAM
May. 1993
MICROCONTROLLER BOARD
BLOCK DIAGRAM
365
1
POWER SUPPLY &
COMMUNICATION BOARD
BLOCK DIAGRAM
Philips Semiconductors Microcontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter design By Seyamak Keyghobad -Bailey Controls, and Karen Spesard -
WSI
PSD301
Figure 8.
Block Diagram of
Bailey Control's
''Smart'' Transmitter
Design with PSD301
POWER
SUPPLY
1
PORT A DATA ..
INTEGRATOR
M COMPA~ATORS ~
PSD301
LCD
W/32K EPROM
2K SRAM
PAD & PORTS t- PORT B
COMMUNICATION
TRANSFORMERS
Ir----"'---,
MULTIPLEXERS
I ....
SELECTORS
I
"""_---II~
L - _........
SENSOR
l,oj
6SHC11E1
1
ADDRESSI
DATA BUS
MICRO·
CONTROLLER
I
I
I
I
I
VOLTAGE
REGULATOR
U
--,
'--_ _ _ _-1
J
SMART
XMITTER
UART
•
LINE
DRIVERS
&
-l,---P_A....,L1,....6V_S---.....J-t-- RECE,VERS
I
INPUT BOARD
BLOCK DIAGRAM
MaY,1993
MICROCONTROLLER BOARD
BLOCK DIAGRAM
366
POWER SUPPLY &
COMMUNICATION BOARD
BLOCK DIAGRAM
Philips Semiconductors Microcontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter desig n By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
WSI
PS0301
Bonusss
Besides considerably reducing board
space in this smart transmitter design by
reducing parts count, several other
benefits of the PSD301 were also seen.
These include reliability improvement,
power consumption savings, inventory
savings, faster time-to-market, and cost
savings.
Reliability was improved because there
are seven less chips required for
implementation that could fail in the
design. Also, by reducing chip count, 112
pins and about 100 traces were eliminated
and the number of layers on the board
were reduced from 8 to 4, making failures
due to open or shorted pins and traces
less likely to occur.
Power consumption was reduced because
much faster discrete EPROM and SRAM
devices with access times of .. 75 ns would
have been required in conjunction with
glue logic for selecting different devices
instead of using the PSD301 , saving at
least 20 mA Icc. (The access time for the
PSD301 memories include decoding and
input address latch delays). If the
power-down feature on the PSD301 were
also used, power savings could be
Increased further. For example, in a
system which is accessing the PSD301
only a quarter of the time, the power
consumption could be reduced by 75% to
8 mA typical.
PSD301
As an added benefit, the PSD301 helped
reduce inventory significantly by
obsoleting multiple chips. And, if last
minute changes in the design were
required, the PSD301 would be able to
accomodate them without additional
hardware modifications. So, purchasing
line item management is made simpler
and easier.
With the reprogrammable PSD301,
development time was kept to a minimum
by easily accommodating design iterations
in both hardware and software. Changes
in 110, address mapping, bus interface,
and code were simple to make. Also,
debugging -was made easier with the
PSD301 's on-chip SRAM for downloading test programs. This all helped to
shorten the design development cycle,
reduce development costs, and speed up
market introduction of the smart
transmitter.
By using the PSD301, cost savings were
realized by reducing system cost with
fewer boards (or reduced board space),
improving reliability, and reducing
inventory levels. Savings were also
attributable to lower manufacturing costs
because there were fewer parts to
program and place. And by getting to
market faster, profits were improved
significantly.
Summary
The PSD301 peripheral solved a fundamental problem often seen in that instead
of getting "locked into" an inflexible
multiple chip memory sUb-system
solution, the PSD301 was able to provide
Notes
1.
If more EPROM was needed, the PSD302/312 w/512K bits EPROM and the
PSD303/313 w/1 024K bits EPROM are available in the same pinout and packages
(please call your local WSI sales representative for availability). Or, multiple PSD301s
can be cascaded together with the added benefit of increased functionality and I/O's.
2.
If more SRAM is needed, it can be added externally without requiring any additional
glue logic. See Application Note 011. Note that many engineers have 8K x 8
SRAM in their systems now - not because they need it, but because 2K x 8 SRAMs
are not as readily available.
May. 1993
367
much higher integration and flexibility all
at the same time. Clearly, using the
PSD301 was the better choice for the
smart transmitter design.
Philips Semiconductors Microcontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter desig n By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
WSI
PSD301
Appendix 1. I'SD301 Configuration
wsi PSD301 confiquration Save File for Smart Transmitter Desiqn
ALIASES
CSo
= ASICCS
*******************************************************************************
GLOBAL CONFIGURATION
Address/Data Mode:
Data Bus Size:
CSI/Al9:
Reset Polarity:
ALE Polarity:
WRD/RWE:
Al6-Al9 Transparent or Latched by ALE:
Using different READ strobes for SRAM and EPROM:
MX
8
CSI
LO
HI
RWE
T
N
*******************************************************************************
PORT A CONFIGURATION (Address/IO)
Bit No.
Ai/IO.
10
10
10
10
10
10
10
10
0
1
2
3
4
S
6
7
CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
*******************************************************************************
PORT B CONFIGURATION
Bit No.
CS/IO.
CSO
CSl
CS2
CS3
CS4
CSS
CS6
CS7
0
1
2
3
4
S
6
7
CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CHIP SELECT EQUATIONS
/ASICCS
= /AlS *
Al4
*
/Al3
*
*
/Al2
/CSl
/AlS
* Al4 * /Al3 * Al2 * E
/CS2
/AlS
* Al4 * Al3 * /Al2 *
/CS3
/Al5
* Al4 * Al3 * A12 *
E
E
E
/CS4
/AlS * /Al4 * /Al3 * /Al2 * /All * E
+ /Al5 * /Al4 * /Al3 * /Al2 * /All * / R/W
/CSS = /Al5 * /Al4 * /Al3 * /Al2 * All * E
+ /AlS * /Al4 * /Al3 * /Al2 * All * / R/W
/CS6 = /Al5 * /Al4 * /Al3 * Al2 * /All * E
+ /Al5 * /Al4 * /Al3 * Al2 * /All * / R/W
/CS7 = /Al5 * /Al4 * /Al3 * Al2 * All * E
+ /AlS * /Al4 * /Al3 * Al2 * All * / R/W
May, 1993
368
Philips Semiconductors Microcontroller Peripherals
Application Note 013
The PSD301 streamlines a microcontroller-based smart
transmitter design By Seyamak Keyghobad - Bailey Controls, and Karen Spesard -
WSI
PSD301
Appendix ,. PSD301 Configuration (Cont.)
********************************************************************************
PORT C CONFIGURATION
Bit No.
0
1
2
CS/Ai.
CS8
CS9
CSI0
CHIP SELECT EQUATIONS
/A15 * /A14 * A13 * /A12 * /All *
/CS8
/CS9 ... /A15 * /A14 * A13 * /A12 * All *
= /A15
/CSI0
R/W
R/W
* /A14 * A13 * A12 * /All *
R/W
********************************************************************************
ADDRESS
ESO
ESl
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP
MAP
A A A A A A A A A
19 18 17 16 15 14 13 12 11
N N N N 1 0 0 0 N
N N N N 1 0 0 1 N
N N N N 1 0 1 0 N
N N N N 1 0 1 1 N
N N N N 1 1 0 0 N
N N N N 1 1 0 1 N
N N N N 1 1 1 0 N
N N N N 1 1 1 1 N
N N N N 0 1 1 0 0
N N N N 0 0 1 1 0
******************************
CDATA
CADDRDAT
CRRWR
CA19/(/CSI)
CALE
CRESET
COMB/SEP
CADDHLT
...
...
...
...
...
...
CPAF2
... 0
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
May, 1993
0
1
1
0
0
0
0
0
SEGMT
STRT
8000
9000
AOOO
BOOO
COOO
DOOO
EOOO
FOOO
6000
3000
END
SEGMT
STOP
8FFF
9FFF
AFFF
BFFF
CFFF
DFFF
EFFF
FFFF
67FF
37FF
EPROM
START
8000
9000
aOOO
bOOO
cOOO
dOOO
eOOO
fOOO
EPROM
STOP
8fff
9fff
afff
bfff
cfff
dfff
efff
ffff
File Name
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0
****************************************
CPAFI
CPAFI
CPAFI
CPAFI
CPAFI
CPAFI
CPAFl
CPAFl
[0] ... 0
[ 1] ... 0
[2] = 0
0
[ 3]
0
[4]
0
[5 ]
[6]
0
[7 ] ... 0
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
[0] ... 0
[1] ... 0
0
[2]
0
[3]
0
[4]
0
[5 ]
[6]
0
[7] ... 0
0
[0]
0
[ 1]
0
[2 ]
[3] = 0
0
[4]
[5 ] = 0
[6] = 0
[ 7] = 0
[0] ... 0
0
[1]
[2 ] ... 0
0
[3]
0
[4]
0
[ 5]
[6]
0
[7] ... 0
CPCF [0]
CPCF [ 1]
CPCF [2]
369
1
1
1
Philips Semiconductors Microcontroller Peripherals
Application Note 014
Using the PSD3XX PAD for system logic
PSD3XX
By Jeff Miller - WSI
Introduction
In 1990, WSI introduced the Programmable
System Device (PSD): the first device in
the world integrating UVEPROM, SRAM
and programmable logic on a single chip of
silicon. The highly-successful PSD301 was
the first device in the PSD family and is
currently used in applications ranging from
fluid analyzers to high performance
computers. The PSD device, by combining
most of the peripheral functionality required
by a typical microcontroller unit into one
package, has enabled designers to greatly
reduce part count, power and board space
which has translated into significant cost
savings.
Even if the PSD3XX family were simply a
collection of EPROM and SRAM with an
PAD
Arch/tectue
The Programmable Array Decoder (PAD)
contained in the PSD3XX family is a standard PLD array designed to provide all of
the internal memory and I/O device chip
selects as well as an external logic replacement capability. It has 14 inputs, 24 outputs
and 40 product terms with which to perform
these functions. See Figure 1 for an
illustration of the PAD.
The PAD's 14 inputs are as follows:
o
o
o
o
A11 -A19
ALEorAS
RD or E
WRor R/W
The A 11 - A 19 pins are labeled as address
inputs, however, they do not have to be.
A11 - A15 are generally sourced by the
microcontroller or microprocessor that is
connected to the PSD device. If the
controller generates more than 16 bits of
address, the A 16 - A 19 inputs may be
used to connect the high order address bits
for a full 1 MByte of address space. If the
controller does not require this much
address space, A16 - A19 may be used for
other purposes, like general I/O or logic
inputs.
A19 is multiplexed with the CSI Signal,
which is used to place the PSD device in a
May. 1993
371
on-chip decoder, it would be capable of
adding significant value to the system into
which it were deSigned. However, the
PSD3XX family is much more than just a
combination of memory devices. The onchip PLD may be used for many useful
purposes in addnion to providing the
address decode capability. The purpose of
this note is to demonstrate, in detail, the full
capability of the PAD section of the
PSD3XX family. A basic, though not extensive, knowledge of the PSD 3XX family and
the Maple programming software is
assumed by this note. Please consult
Application Note 011 and/or the appropriate
PSD3XX family data sheet for this general
knowledge.
low power mode when the system requires
it. When configured as CSI, the A19 pin
may not be used for any other purpose
except the ~er down mode. In this
mode, the CSI signal is used by the PAD
only to disable it, causing it to expend less
power. When configured as A19, this Signal
may be used as a general purpose input to
the PAD from the external system. This
capability will be described in more detail
later in this note. A16 - A18, when not
necessary for address expansion, may also
be used as general purpose inputs to the
PAD. Thus, a total of four of the 14 PAD
inputs may be general purpose, allowing
the replacement of external logic by the
PSD device. These inputs may be
combined with the other PAD inputs to form
complex equations involving addresses,
strobes and external signals.
When attempting to visualize the full capability of the PAD outputs, it is most clear
when it is broken into two sections, labeled
in Figure 1 as PAD A and PAD B. PAD A is
responsible for providing all of the internal
chip selects for the EPROM, SRAM and I/O
ports and the track mode control signals,
and PAD B is responsible for the external
logic replacement function.
Philips Semiconductors Microcontroller Peripherals
Application Note 014
Using the PSD3XX PAD for system logic
PSD3XX
Figure 1. PAD Description
ALE .rAS
..n..ESO
..,
~
..J"'I.
o or E
or R/W
A19
A18
I<
I<
~
....
I-
....
I<
I<
I<
..,
~
....
-B--
~
-v
....
I<
I<
I<
\
I
..,
A16
A14
A13
A12
A11
~
I<
I<
RESET
PAD A
May. 1993
CSO/PBO
CS2/PB2
I<
..,
~
....
\
:JB
....
~
....
~
~
CS3/PB3
1:t1
...,
CS4/PB4
-Q-1
..,
CS5/PB5
....
K
..,
I
PADB
CS6/PB6
~
~
CS7/PB7
....
...,
-(>0- csa/pco
(>0(>0-
-v
~
.
CSI
1
CS1/PB1
I<
..,
....
..10(
A15
l
PAD A
'"'S
I<
I<
A17
ES1
ES2
ES3
8 EPROM Block
ES4
Select Lines
ES5
ES6
ES7
RSO _ _. SRAM Block Select
CSIOPORT _I/O Base Address
CSADIN
Track Mode
CSADOU i~
} Control Signals
CSADOU
~
-{)--
..
.....
....
Thirteen of the 24 PAD outputs and thirteen
of the 40 product terms are dedicated to
PAD A. PAD A should be considered the
internal address decoder, used to select
the various on-chip memories and I/O
devices according to the memory map
programmed by the user. Each output has
a single product term, allowing a particular
372
CS9/PC1
CS10/PC2
resource to be allocated a single
contiguous range of addresses which will
be used to access it. All of the PAD inputs
are available for generation of the PAD A
outputs, allowing the designer to select
internal resources using any combination of
address, strobe and external signals.
Philips Semiconductors Microcontroller Peripherals
Application Note 014
Using the PSD3XX PAD for system logic
PAD A
(Cont.)
PSD3XX
The PAD A outputs are as follows:
o
o
o
o
o
o
ESO-ES7
RSO
CSIOPORT
CSADIN
CSADOUT1
CSADOUT2
ESO - ES7 are used to select the internal
EPROM resources. Using the PSD301 as
an example, there are eight select lines
with which to access 32 KBytes of EPROM.
Thus, each select line can enable a block
of 4 KBytes of EPROM configured as
4K x 8 or 2K x 16. Each block must be
contiguous, but the blocks may be placed
anywhere within the address space of the
microcontroller.
RSO is used to select the SRAM resource.
This single signal accesses a single 2
KByte block of SRAM which may be
configured as 2K x 8 or 1K x 16. Again, this
block must be contiguous but may be
placed anywhere in the address map.
CSIOPORT is the signal which defines the
base address of the on-chip I/O ports and
control registers. The I/O ports and control
registers occupy a 2K block of addresses
which, like the memories, must be
contiguous but may be located anywhere in
the address space of the microcontroller.
Once configured in the address map,
CSIOPORT defines the base address of
these ports and registers. An offset is
added to the base address to individually
access the registers. Table 1 below lists the
offset values for these registers.
Table 1.
I/O Port
Offset
Addresses
May, 1993
CSADIN, CSADOUT1 and CSADOUT2 are
used to control the Track Mode operation.
The Track Mode is an available option for
Port A to allow it to ''track'' the
Address/Data bus inputs to the PSD device
from the microcontroller. This provides the
capability to connect the PSD device, and
therefore the microcontroller, to one or
more shared resources. These resources
may be memory or other devices which
must be accessed by more than one microprocessor or microcontroller.
CSADIN is generated when the microcontroller is attempting to read data from Port
A in the track mode. It is generated from
one product term involving the address
inQuts and the RD strobe (Intel mode) or
R/Wand E (Motorola mode). This allows
the user to configure the address range in
which the data is to be read from Port A.
CSADOUT1 is generated when the microprocessor is accessing a ''tracked'' address.
It is generated from a single product term
involving the address inputs and ALE.
When the address generated by the microcontroller is within the block specified by
the user for track mode, and the ALE is
active, CSADOUT1 becomes active,
transferring the address and outputting it
from Port A. CSADOUT2 is generated
when the microcontroller is performing a
write operation to a tracked address. It also
has one product term involving the address
inputs and WR (Intel mode) or R/W and E
(Motorola mode). When the microcontroller
performs a write to the appropriate
address, CSADOUT2 is generated,
transferring the data and outputting it from
Port A. For further details on the operation
of the Track Mode, please consult
Application Note 017.
Byte Size Access of the VO Port Registers
Offset from the &l10'OR1
Register Name
Pin Register of Port A
+ 2 (accessible during read operation only)
Direction Register of Port A
+4
Data Register of Port A
+6
Pin Register of Port B
+ 3 (accessible during read operation only)
Direction Register of Port B
+5
Data Register of Port B
+7
373
Application Note 014
Philips Semiconductors Microcontroller Peripherals
PSD3XX
Using the PSD3XX PAD for system logic
Example:
Addl'llSS
Mapping
With PAD A
In this example, we will choose a sample
address map which is similar to those used
in typical microcontroller applications. This
example assumes the use of a PSD301
device with 256 Kbits of EPROM and 16
Kbits of SRAM. Figure 2 below illustrates
our sample address map.
In this example, we have located the boot
code and interrupt service routines beginning at address 0000 in EPROM block O.
The SRAM is located in the 2K block beginning at address Ox1000 and can be used
for the stack and/or other scratchpad data.
The I/O ports occupy the 2K block beginning at address Ox1800. Addresses in this
range will access ports A and B and their
control registers. The area from Ox2000 to
Ox8FFF is unused in this example, though
it could be used for external resources as
will be shown later. Finally, the main
program resides in the 28K block of
EPROM located from address Ox9000 to
OxFFFF and is selected by ES1 - ES7.
Figure 2.
Example
Memory Map
Configuring this memory map would
normally require designing a decoder to
generate the appropriate chip selects for
each given address range. For example,
assuming that a microcontroller with a 16-bit
address bus is used, the chip select for
EPROM bank 0 (ESO) would be generated
with the following equation:
ESO = /A12 ·/A13 ·/A14 ·/A15
Equations like this one would be formulated
for each of the chip selects, and the entire
function would probably be placed in some
kind of programmable device. When the
PSD device is used, PAD A replaces this
programmable device. Programming PAD A
to perform this function is a simple task
using WSI's Maple software.
Entering the ADDRESS MAP menu in the
Maple software running on a PC compatible
computer, the user will see a screen similar
to the one shown in Figure 3.
FFFF
ES7
ES6
ES5
ES4
ES3
ES2
ES1
-
MAIN
PROGRAM
USING
I/O PORTS
USING CSIOPORT -
9000
BFFF
60 ·64K
56 • 60K
52 • 56K
48 • 52K
44 • 48K
40· 44K
36· 40K
2000
1FFF
6 - BK
1800
17FF
1000
OFFF
SRAM
USING
RSO
4·6K
BOOT CODE &
INTERRUPT SERVICE
USING
ESO
o•
0000
May. 1993
374
4K
Philips Semiconductors Microcontroller Peripherals
Application Note 014
PSD3XX
Using the PSD3XX PAD for system logic
Example:
Address
Mapping With
Pad A (Cont.)
PADS
Upon displaying this screen, the Maple
software is ready for the user to enter the
memory map data. This is performed quite
simply by moving the cursor to the appropriate point with the arrow keys, and then
entering the appropriate data. The address
mapping may be entered in either of two
ways. First, the user may select each
address bit individually for each chip select
and enter a 0 or 1 as appropriate for the
equation desired. In our example, for ESO
we would enter a 0 in the columns for A 12,
A13, A14 and A15. The other bits are don't
cares. In the other method of programming
the pad, the user simply moves the cursor
to the SEGMT START column and enters
the desired starting address for the block.
Again, using our sample memory map, the
user would move to the SEGMT START
column for ESO and enter 0000. Maple
then automatically programs the O's and 1's
into the address bits correctly to program a
4K block of EPROM beginning at address
OxOOOO. Note that all EPROM blocks must
begin on 4K boundaries. Figure 3 shows
the resulting address map table for our
example.
Eleven of the PAD outputs and 27 of the
product terms are dedicated to PAD B.
Where PAD A was used to control the onchip PSD device resources, PAD B controls
any off-chip resources required by the
system. As with PAD A, all inputs to the
PAD are available to PAD B, allowing the
system designer to formulate outputs
involving any combination of address,
strobes and external signals. Unlike PAD A,
several of the outputs of PAD B have up to
four product terms each.
The outputs of PAD B are as follows:
Figure 3.
Maple Address
Map Entry
A A A A A A A A
ESO
ES1
ES2
ES3
ES4
ES5
ESG
ES7
RSO
CSP
May. 1993
19 18 17 16 15
14
13 12
0
0
1
1
1
0
0
0
0
0
0
1
0
0
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
x
x
x
0
0
0
0
0
0
0
0
375
The address inputs which were unused in
this example (A16, A17, A1a and A19)
could have been used as general purpose
inputs to the PAD for specialized control of
the on-chip memory and I/O resources.
When this is done, the designer has
complete flexibility as to the configuration
of the PSD device resources and may
easily absorb many system functions into
the PSD device. More detail about the use
of A 16 - A 19 will be provided later in
this note.
o
o
The outputs from PAD B are brought to the
outside world through Port B and Port C.
These outputs are called chip selects,
though they may be used for any function
whatsoever. The port pins are configured
as selected by the user when the device is
programmed with the Maple output file.
There are many configuration options for
each port pin.
A SEGMT
START
N
0000
N
9000
N
AooO
N
8000
N
COOO
N
DooO
N
EOOO
N
FooO
1000
0
1800
11
CSO - 7 (Port B)
csa -10 (Port C)
SEGMT FILE
STOP START
OFFF
9FFF
AFFF
BFFF
CFFF
DFFF
EFFF
FFFF
17FF
1FFF
FILE
STOP
FILENAME
Application Note 014
Philips Semiconductors Microcontroller Peripherals
Using the PSD3XX PAD for system logic
PADB
(Cont.)
If you require more information about port
configuration, please consult application
note 011. If the port outputs are
configured as chip selects (outputs from
the PAD), they may not be used for any
other purpose. For example, the three Port
C signals may be configured as chip
selects (outputs) or addresses (inputs) but
cannot be both. Fortunately, the flexibility of
the PSD device and the Maple software
allows the designer to configure each Port
Band C pin individually, so that the number
of outputs and inputs may be optimized for
a particular design requirement. See Table
2 below for an example of this flexibility.
Table 2.
Sample Port
Configuration
Example:
Generating a
Logic Equation
With PAD B
PSD3XX
Pin
Configuration
CMDS/DD
PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7
Address Out
Address Out
Address Out
Address Out
1/0
1/0
1/0
1/0
CMOS
CMOS
CMOS
CMOS
CMOS
CSO
CS1
CS2
CS3
1/0
1/0
1/0
1/0
CMOS
CMOS
PCO
PC1
PC2
A16
A17
CS10
-
Assume that it is necessary to generate the
following equation given the port configuration in Table 2 above. This equation is a
simple OR of three product terms.
CSO
= A15· A14 • IA13 ·/A17· RD
+ I A15 • A14 • A12 • WR + A16
Figure 4 illustrates the Maple programming
sequence to generate this equation.
To program this equation, the PORT B
menu is entered from the Maple software.
eso is selected by moving the cursor to it
using the arrow keys. With CSO selected,
the user then presses the F3 key to bring
up the CHIP SELECT DEFINITION table
for CSO. The table contains four rows for
data entry, each one corresponding to one
May, 1993
This sample port configuration demonstrates
all of the possible uses of a particular port
pin. Though only Ports Band C may be
inputs or outputs tolfrom the PAD, Port A is
included in the table for completeness. In
this example, five of the port pins are
configured as PAD outputs (CS) and two are
configured as PAD inputs (A). The remaining
port pins in this example are configured as
either 1/0 or address outputs. Several of the
CS outputs have been configured as open
drain. This allows them to be connected
together in a wired OR configuration to
increase the number of product terms even
further if desired.
376
00
00
CMOS
00
00
CMOS
CMOS
CMOS
CMOS
00
of the available product terms for CSO.
Implementing this equation required using
three of the four available product terms.
The fourth is left blank and will not be used
to generate the output.
To enter the equation into the table, simply
move the cursor around into the appropriate
position and enter a 1 if the corresponding
signal should be high for the equation to be
true,O if it should be low, and X or SPACE if
the signal is a don't care. The first term of
the equation requires a low on A17, a high
on A15, a high on A14, a low on A13 and a
high on RD for the term to become active.
Thus, 1's are placed in the A15, A14 and
RD positions,
Application Note 014
Philips Semiconductors Microcontroller Peripherals
Using the PSD3XX PAD for system logic
Example:
Generating a
Logic Equation
WlthPADB
(Cont.)
Figure 4.
Programming
PAD Outputs
PSD3XX
and O's are placed in the A17 and A13
positions. The remaining terms in the equation are entered in the same way. Note that
A17 and A16 in this example need not be
address bits, but may instead be used to
bring external Signals into the PAD.
PIN
CSIIIO
CMOS/OD
PSc)
cso··
PBl
PB2
PB3
PB4
PB5
PB6
PB7
CSl
CS2
CS3
CS4
CS5
CS6
CS7
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
Four product terms are available on each
of the CSO - CS3 outputs, two terms are
available on the CS4 - CS7 outputs and
one term is available on csa - CS10.
When planning the use of the PAD outputs,
it is important to consider this so that the
most efficient use of the product terms can
be achieved.
A19 A18 A17 A16 A15 A14 A13 A12 A11 ALE
X
X
X
X
X
X
0
X
X
X
X
1
1
0
X
0
1
X
X
X
X
X
1
1
X
X
X
X
X
X
RD WR
1
X
X 1
X X
CS definition is the NOR of the product terms (rows). Enter 1 to select Active High signal,
oto select Active Low Signal, X to mean "don't care", SPACEBAR to erase. Enter values
in columns relevant to your application; other blank columns will be treated as
"don't cares".
Application
Examples
The following section will illustrate the use
of the PAD for system logic replacement in
some common microcontroller applications.
Basic Chip Select Generation
One of the simplest uses of PAD B is the
generation of chip selects for off-chip
resources such as I/O devices or memories. Figure 5 below depicts the connection
between a 68HC11 microcontroller, the
PSD301 and two common peripheral
devices: the 8250 UART and the 8254
counter/timer.
The 68HC 11 is an 8-bit microcontroller with
a 16-bit address bus. The lower 8 bits of
address are multiplexed with the data bus
while the upper 8 bits are transmitted on
their own bus. An address strobe (AS) is
provided to latch the ~dress off of the
multiplexed bus. A R/W signal indicates
whether the current bus transaction is a
read or a write (RIW = 1 = read, Riw = 0 =
May, 1993
377
write). The E signal is the clock used to
strobe the data in or out of the microcontroller. The PSD301 can be configured to
exactly match this signal definition and then
connected as shown in the diagram. Not all
of the 68HC11 or PSD301 signals are
shown, only those relevant to this example
of PAD capability.
The 8250 is a UART device commonly
used in microcontroller systems to provide
a serial data communication port. It has a
simple bus interface, yet does not directly
connect with the 68HC11 bus architecture.
It requires an 8-bit bus to transfer data to
and from the microcontroller and a separate 3-bit address bus used to access its
internal registers. It also requires a chip
select and separate read and write strobes
(RD and WR). The chip select is generated
by decoding the address from the microcontroller. The RD and WR signals may be
generated from the RIW and E signals
Philips Semiconductors Microcontroller Peripherals
Application Note 014
Using the PSD3XX PAD for system logic
Flgure5.
A Typical
Mlcrocontrol/er
System
PSD3XX
PSD301
68HC11
pco
PCl
PC2
PC3
PC4
PCS
PC6
PC7
I
~~
I ~~
I ~~
I ~~
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
E
INS8250
ADO
ADl
AD2
AD3
A04
ADS
A06
AD7
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
AS
A9
Al0
All
A12
A13
A14
A1S
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7
E
PCO
PCl
PC2
RtW
R/W
AS
AS
"\
"\
"
"\
"\
"\
"\
"V
~
~
~
~
-
V
V
DO
01
02
03
04
05
06
07
AO
Al
A2
CS2
AD
WR
8254
-
~
~
~
~
l
V
V
00
01
02
03
04
05
06
07
AO
A1
AD
ViR
cs
Application
Examples
(Cont.)
according to the following equations:
IRD
= I(R/W • E)
IWR
=I(/RIW • E)
These equations may be easily generated
using PAD B and sent out through two of
the chip select outputs. We have chosen
CS5 and CS6, which come out on PB5 and
PB6, for this example.
In order to provide the address lines to the
8250, we have configured Port A to output
the latched address. This eliminates the
need for any external latches to demultiplex
the addressldata bus from the microcontroller. Though all eight of the Port A pins
have been configured as address outputs
in this example, it is possible to configure
only those address bits required for the
application, AO - A2 in this example, and
configure the remaining Port A pins as
general 1/0.
The 8254 is a programmable interval timer
which, like the 8250, is a peripheral used in
May. 1993
378
many microcontroller applications. Its bus
connection is very similar to the 8250,
allowing it to use the same read and write
strobes (RD and WR) and address lines. It
also requires a chip select which is
decoded from the microcontroller address.
The chip selects for both of the peripheral
devices may be easily decoded from the
address inputs to PAD B. Normally, the
addresses which are inputs to the PAD
(A11 - A19) would give decoding resolution
down to 2K. This means that each of the
two peripheral devices that require chip
selects would be allocated an address
range of at least 2K. Since these devices
do not require this much space and the
68HC11 has only a 16-bit address bus, it is
possible to use the high order address
inputs of the PSD device to improve the
decoding resolution. To achieve this goal,
we have configured Port C as address
inputs A16 - A18, but have connected
them to A8 - A10 from the microcontroller.
This means that the PAD will now have
Philips Semiconductors Microcontroller Peripherals
Application Note 014
Using the PSD3XX PAD for system logic
Application
Examples
(Con'.)
access to A8 - A 15 for decoding, thus
providing a resolution of 256 instead of 2K.
This could actually be further reduced to a
resolution of 128 if we were to configure
the A19/CSI input to be A19, and then
connect it to A7 from the microcontroller. In
this example, we have not done this so that
CSI is still available to place the PSD301
into low power mode if required.
We now have to define the addresses of
each of the peripherals so that the chip
select equations may be defined. We will
start from the memory map provided earlier
in Figure 2. This map allocated all of the
internal resources of the PSD device. The
external peripherals may be easily added
to the unused area between addresses
Ox2000 and Ox8FFF. Figure 6 depicts the
new map with the extemal devices added.
Notice that the internal resources can keep
Figure 6.
Memory Map
With Peripherals
PSD3XX
their original address mapping even though
the additional address inputs (A8 - A 10)
have been added. This is because these
inputs may be don't cares in the decoding
for the internal resources even when they
are being used for the external resources.
Now, to wrap up this simple design, we
must enter the configuration and mapping
information into Maple. The configuration of
the PSD device must be consistent with the
operation of the 68HC11 microcontroller.
The address/data mode must be multiplexed, the data bus must be 8 bits wide,
CSI/A19 may be configured either way, the
reset polarity should be active low, the ALE
polarity is active high, the read and write
lines must be R/Wand E, A19 - A16
should be latched so that these bits
become available just like the rest of the
address bus, and the read strobes for the
FFFF
MAIN
PROGRAM
USING
9000
8FFF
ES7
ES6
ES5
ES4
ES3
ES2
ES1
-
60
56
52
48
44
40
36
-
64K
60K
56K
52K
48K
44K
40K
2200
21FF
8254
INTERVAL TIMER
USING CS7
-
8.125 - 8.25K
8250
UART
USING CS4
-
8 - 8.125K
2100
20FF
2000
1FFF
I/O PORTS
USING CSIOPORT -
6 - 8K
SRAM
USING RSO
-
4 - 6K
BOOT CODE &
INTERRUPT SERVICE
USING ESO
-
0 - 4K
1800
17FF
1000
OFFF
0000
May. 1993
379
Philips Semiconductors Microcontroller Peripherals
Application Note 014
Using the PSD3XX PAD for system logic
Application
Examples
(Cont.)
SRAM and EPROM will be the same. This
configuration should be entered from the
configuration menu of the Maple software.
The address map programming for this
example will remain the same as the one
used earlier in Figure 3. The only items
remaining are the programming of the ports
and the generation of the equations for the
chip selects and readlwrite strobes. First
we must configure Port A to provide the
latched address to the peripherals. This is
accomplished by entering the PORT A
menu in the Maple software. Maple will
then ask you if you would like Port A
configured for address 1/10 or the Track
Mode. For this example, we will use the
address/lID configuration. Next, Port A
must be configured pin for pin as an
address output. This is easily performed by
using the cursor keys to select the appropriate pin and pressing the SPACE BAR to
change the configuration. It is also possible
to configure each pin as an open drain or
CMOS output, but for address outputs, it is
better to make them CMOS.
Now, PORT C must be configured to
provide the three additional address inputs.
This is performed by entering the PORT C
menu in Maple and selecting the appropriate pin with the cursor. Each pin should be
configured as an address bit (Ai). Maple will
call the pins A16 - A18 even though we will
be using them as A8 - A10.
Walt State
Generation
May, 1993
Often, when using some of the newer highperformance microcontrollers with slower
external peripherals, it is not possible to
complete a read or write cycle to the
peripheral in the time allowed by the microcontroller's minimum bus cycle. In this
case, one or more wait states must be
added to slow the controller down to the
speed of the peripheral. One way of doing
this is to fix a number of wait states for all
bus cycles to allow the slowest device
enough time for its access. Some
controllers even provide the capability to do
this internally through the programming of a
register. This works, of course, but can
severely impact the performance of the
system. There is no need to penalize the
performance of the entire system, which
can include zero wait state memory
devices and other peripherals, simply
380
PSD3XX
Lastly, we must configure the Port B
outputs to become the chip selects and
read/write strobes. First, the PORT B menu
must be entered. Now, we must configure
each pin as an 1/0 or CS output.
PBO - PB3 may be configured as general
purpose 1/0 pins. PB4 - PB7 must be
configured as chip selects. Once configured as chip selects, the equations for each
output may be entered by following the
Maple instructions. The procedure is the
same as the one used in the earlier chip
select example. Our equations, including
the ones developed earlier for the read and
write strobes, are defined for each output
as follows:
=I(R/W e E)
PB6 =ICS6 =IWR =I(/R/W • E)
PB5 =ICS5 =IRD
PB4 = ICS4 = 18250CS = I(A15 e/A14 e
A13 e/A12 e/A11 e/A18 e/A17 e/A16)
PB7 =ICS7 =18254CS = I(A15 e/A14 e
A13 e/A12 e/A11 e/A18 e/A17 e A16)
This completes the design integrating these
four components with no additional logic
whatsoever. There is also additional space
in the PAD for more functions if necessary,
so we have not yet reached the limit of the
integration possibilities with the PSD301.
because one or more of the external
devices requires some number of wait
states. It is possible, with minimal logic, to
create a completely programmable automatic wait state generator using the
PSD301 which will allow the fast resources
to operate at zero wait states and still
provide from one to eight wait states for the
slower resources.
For this example, we will use an Intel
80C196KB microcontroller running at 12
MHz. This controller has the capability to
operate in a 16-bit data mode, providing
the opportunity to further increase performance if the system can also operate in
this mode. The PSD301 does have the
capability of operating in the 16-bit mode,
making it a good match for the 80C196. We
will assume that the 80C196 must be
Philips Semiconductors Microcontroller Peripherals
Application Note 014
Using the PSD3XX PAD for system logic
Walt State
Generation
(Cont.)
interfaced to several slow S-bit peripherals
requiring from one to eight wait states. With
the PSD301, we can provide the correct
number of wait states for each peripheral
with the added capability of dynamically
sizing the bus to the appropriate width for
the current access.
The memory map we will use for this
design is depicted in Figure 7. The internal
resources of some SOC196 derivatives
occupy most of the address space from
OxOOOO to Ox3FFF, though some have less
resources. Therefore, we have constructed
the memory map to place the PSD device
resources above address Ox4000. The
PSD301 SRAM and I/O devices occupy
from address Ox4000 to Ox4FFF. This
leaves the area from Ox5000 to Ox7FFF for
external peripherals while leaving OxSOOO
to OxFFFF for the EPROM banks. We
assume that we must connect three external peripherals to the PSD device using
this address space, one requiring one wait
state, one requiring three and one requiring
six. This memory map is entered into the
part similarly to the previous examples.
Figure 7.
Memory
Map
PSD3XX
To achieve the variable number of wait
states, the ideal solution is to decode the
address to determine the number of wait
states required for a particular address
range, and then to use a counter to count
the appropriate number. By using the PAD
to initialize an external counter, a variable
wait state counter can be created in this
manner. This wait state generator requires
only one external device, a 74FCT191
counter. The circuit used to implement this
function is illustrated in Figure S. The
SOC 196KB is directly connected to the PSD
device which in turn provides the three chip
select signals for the external peripherals
(PER1 CS, PER2CS and PER3CS) as well
as the wait state generator function and the
dynamic bus sizing. Ports Band C are fully
utilized to provide the logic inputs and
outputs required to implement these functions, while Port A is still available for
general 1/0 or address use.
This circuit uses PAD B to decode the
addresses driven by the microcontroller
and provide four outputs, based on these
FFFF
MAIN
PROGRAM
USING
8000
7FFF
7000
ES7
ES6
ESS
ES4
ES3
ES2
ES1
ESO
60
56
52
48
44
40
36
32
-
64K
60K
56K
52K
48K
44K
40K
36K
PERIPHERAL # 3
1 WS
USING CS7
28 - 32K
PERIPHERAL # 2
6 WS
USING CS6
-24-28K
PERIPHERAL # 1
3 WS
USING CSS
-
20 - 24K
USING CSIOPORT -
18 - 20K
USING RSO
16 - 18K
6FFF
6000
5FFF
5000
4FFF
I/O PORTS
4800
47FF
SRAM
4000
3FFF
80C196KB
INTERNAL RESOURCE
0000
May, 1993
381
-
Application Note 014
Philips Semiconductors Microcontroller Peripherals
PSD3XX
Using the PSD3XX PAD for system logic
Walt State
Generation
(Cont.)
Figure 8.
Walt State
Generation
Circuit
addresses, which are used to initialize the
74FCT191 counter with its initial value. The
counter is initialized using ALE to latch
these four PAD outputs. The load signal for
the counter is active low, however, while
ALE is active high, so ALE is inverted using
PAD B and sent out through Port C.
Though the 80C196KB can be configured
to provide an active-low address strobe,
ADV, the timing of the signal is inappropriate for use as the LOAD input to the
counter. Once the counter is initialized, it
counts up from the initial value until the
most significant bit increments from 0 to 1.
The output of the most significant counter
bit is routed to the READY input of the
microcontroller. Thus, the controller will be
held in wait states until the most significant
counter bit is incremented. This output is
also routed to the CTEN signal of the
counter so that counting will cease once
the READY signal has been issued to the
controller. The clock for the counter is an
inverted version of the CLKOUT signal
from the controller. This clock must be
inverted since the 80C196KB uses the
falling edge of the clock to sample the
READY input. PAD B again provides the
The counter provides from zero to eight
wait states depending on the initialized
value. For zero wait states, the most significant counter bit is initialized to a "1", which
provides the READY signal to the controller
immediately and disables the counter from
incrementing. If one wait state is desired,
the counter is loaded with the value 7 (0111
binary) so that after it increments once, the
most significant bit switches to a "1" and
provides the READY to the controller.
When two wait states are required, a 6
(0110 binary) is loaded into the counter,
and so on for the rest of the wait state
values.
To properly size the bus to the appropriate
width, PAD B is again used to decode the
addresses of the 8-bit devices. When the
address of an 8-bit device is encountered,
the BUSWIDTH signal is driven to
configure the 80C196KB address to eight
bits. For all other addresses, the width is
PSD301
80C196KB
r-j
==
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ADS
AD9
AD10
AD11
AD12
AD13
AD14
AD15
PBO
PB1
PB2
PB3
PB4 r-- PER1CS
PB5 r--- PER2CS
PB6
PB7
RD
WR
ALE
BHE
PCO
PC1
PC2 r--
RD
WR
ALE
BHE
ClKOUT
i=ll I
BUSWlDTH
READY t -
May. 1993
inversion function by routing CLKOUT
into one of the Port C pins, inverting it
and routing it back out through another
Port C pin.
382
r--r---
f--
GENERAL
PURPOSE
ADDRESS OR I/O
r---
74FCT191
L-
~R3CTrI
r
QA
QB
QC
QD
CTEN
lOAD
ClK
Diu
01--<
Philips Semiconductors Microcontroller Peripherals
Application Note 014
Using the PSD3XX PAD for system logic
Walt State
Generation
(Cont.)
set for 16 bits. The BUSWIDTH signal is
output from one of the Port B pins.
The PSD device must now be configured to
provide the functions required by the
example circuit. The configuration of the
PSD must first be programmed to function
with the 80C196KB. This is easily
performed by the Maple software as in the
previous example. The address/data mode
should be multiplexed, the data bus width
should be 16 bits, CSI/A19 may be
configured as required for the application,
the reset polarity should be active low, the
ALE .E,2larity should be active high, separate RD and WR strobes should be used
and A 19 - A 16 should be transparent, not
latched, since they are used as logic inputs
to the PAD.
Next, we must program the functionality of
Port C. For this example, PCO and PC1 are·
used as outputs from the PAD to provide
the LOAD and CLK signals for the '191
counter. This is performed by entering the
PORT C menu in Maple and configuring
PCO and PC1 as CS8 and CS9, respectively. PC2 is used to input the CLKOUT
signal from the microcontroller to the PAD
so that it may be inverted. Therefore, it
must be configured as address input A18.
Now, the equations used to generate the
PCO and PC1 outputs must be entered into
the PAD. PCO is the LOAD signal which is
just the ALE input inverted. PC1 is an
inverted version of A18, which contains the
CLKOUT signal. These equations are listed
Tab/e3.
Walt State
Summary
May. 1993
PSD3XX
below:
PCO
= /LOAD = /ALE
PC1
= /CLKOUT = /A18
The equations are programmed by entering
the CHIP SELECT DEFINITION menu for
each of the two chip selects, as in the
previous example, and entering the appropriate 1's, O's and DON'T CARES. In the
case of PCO, there are don't cares in all of
the PAD inputs except ALE, where there is
a O. Similarly, for PC1, the A18 input is a 0
while the rest of the PAD inputs are don't
cares.
Port A is usually configured next, and in
this example it is free to be configured in
any mode necessary for the application. It
may become either I/O or address outputs,
or may be set in the Track Mode as
described earlier.
We are now ready to configure Port B. This
example requires that all of the Port B pins
be used as chip selects (logic outputs) from
PAD B. PBO - PB3 are used to initialize the
counter with the correct number of wait
states for each device. These outputs are
defined according to the address ranges for
each of the peripherals and the number of
wait states required for each. Table 3
summarizes the outputs required for each
peripheral so that we may define the
correct equations for the outputs.
PSo-PS3
Peripheral No.
Address Range
No. Wait States
Ox5000-5FFF
3
1010
2
Ox6000-6FFF
6
0100
3
Ox7000-7FFF
383
1110
Philips Semiconductors Microcontroller Peripherals
Application Note 014
Using the PSD3XX PAD for system logic
Walt Statl
',n'tat/on
(Cont.)
This table can be easily used to form the
necessary equations for PBO - PB3. PB3
can be considered the enable for the wait
state generator which is active low only in
the address ranges of the three peripherals. It must remain high for all other
address ranges. The other three outputs
simply encode the proper number of wait
states. The resulting equations are listed
below:
PBO = lOA = I(A15 e A14 e A13 e/A12)
PB1
=laB =I(A15 e A14 e/A13 e A12)
PB2 = lac
=I(A15 e A14 e A13 e/A12)
PB3 = laD = I(A15 e A14 e/A13 e A12 +
IA15 e A14 e A13 e/A12 + IA15 e A14 e
A13 e A12)
PB4 - PB6 are used as chip selects for
each of the three peripherals and are
simply decoded from the address inputs by
PAD B corresponding to the address
ranges listed in Table 2. These equations
are listed below:
PSD3XX
Finally, PB7 is used to perform the bus
sizing function. It should be sized to eight
bits whenever any of the external peripherals is accessed. It should be sized to 16
bits for all other accesses. The 80C196KB
requires a high on the BUSWIDTH input for
16-bit operation and a low for 8-bit operation. This is accomplished by the equation
below:
PB7 = BUSWIDTH = I(A15 e A14 e A13 +
IA15 e A14 ./A13 e A12)
This completes the equations for Port B.
These equations are entered in the Maple
software by selecting the Port B chip select
definition screens as described in the previous example and entering 1's and O's in the
appropriate locations. Remember that don't
cares (X's or blanks) must be entered in all
inputs which are not used by a particular
equation.
Finally, we must enter the memory map
into Maple Address Map screen. This is
performed as in the previous example by
entering 1's, O's or don't cares in the appropriate places.
PB4 =IPER1CS = I(A15 e A14 e
IA13 e A12)
PB5 =IPER2CS =I(A15· A14·
A13 e/A12)
PB6 =IPER3CS =I(A15· A14·
A13 e A12)
Conclusion
May, 1993
The PSD device may be used in a variety
of applications requiring the simplicity,
space savings and performance possible
by the integration of memory and
programmable elements. But a significant
Portion of the value of the PSD device, is
its ability to absorb much of the logic
functionality which normally surrounds a
384
microcontroll~r application. The
programmability of the device allows the
designer to make changes to both the
software and the design itself as required.
This is not possible with masked ROM or
ASIC-based designs. The PSD device can
truly turn a microcontroller into a complete
two-chip solution.
Philips Semiconductors Mlcrocontroller Peripherals
Using memory paging with the PSD3XX
Application Note 015
PSD3XX
By Jeff Miller - WSI
Introduction
The PSD3XX is a compact, high
performance microcontroller peripheral
used to extend the capabilities of a
microcontroller in a space-limited
embedded control system. It provides the
programmable logic, memory and I/O
requirements needed by most microcontroller designs in a single small package.
The PSD301, introduced in November
1990, was the first of a six-member family
of devices providing varying amounts of
on-chip resources. The PSD301 contains
32K Bytes of EPROM for program storage
and 2K Bytes of SRAM scratchpad
memory. As the family expanded, the
EPROM memory size grew to 128K Bytes
in some versions. This large memory may
be needed in many applications requiring
large feature sets. In many cases the
What Is
Paging?
The primary purpose of a page register is
to extend the width of the address bus by a
number of bits to increase the size of the
address space. These bits are added to the
address bus as outputs of a register which
is loaded from the data bus of the MCU.
Each additional bit doubles the effective
address space. Though the page register
address bits increase address space, they
are not the same as the true address bits
which are generated by the microcontroller
since they do not appear with the same
timing or ~equence of the address. They
must be controlled carefully to avoid
unexpected behavior. They can also be a
problem for compiler-generated code since
the compiler does not inherently know how
to use a page register. Because of this,
the designer must take care .in designing
software which uses the PSD3XX page
register.
The purpose of this note is to explain the
usage of the page register and some of the
techniques which may be used when
designing software which uses the page
register. A typical page register design
is shown in Figure 1. In the figure, a
typical 8-bit microcontroller with a
multiplexed address/data bus is shown
May, 1993
385
microcontroller is capable of addressing
only 64K Bytes of memory with its
limited 16-bit address bus. In these
applications, the designer is often faced
with the difficult choice of eliminating
features, using a more expensive
microcontroller with a wider address bus,
or adding external paging logic requiring
several extra components.
With this in mind, designers at WSI have
included a simple but very effective paging
system in the PSD3XX models containing
more than 32K Bytes of EPROM. This
enables cost effective microcontrollers like
the 80C31 , 80196, Z80, 68HC11 and
others to take full advantage of additional
memory without any additional hardware or
design effort.
connected with the logic required to
implement a 4-bit page register. The least
significant address bits are demultiplexed
from the data bus by the '573 transparant
latch, which is clocked by the ALE signal.
The most significant 8-bits of address are
driven directly by the microcontroller. When
combined with the least significant address
bits from the address latch, the address
bus is 16-bits wide. This provides the
capability to directly access 64K Bytes of
address space, which may be any
combination of program and data storage.
To implement more address space, two '74
devices (a dual D-type flip flop) have been
used to create a page register. The inputs
of the '74 are four bits of the address/data
bus. These bits are stored into the '74
when a write to a specific address, as
decoded by the '138, is performed by the
microcontroller. The outputs of the '74
form an additional 4 address bits, thus
extending the address bus to 20-bits or 1
MByte of address space. The '74 page
register can be considered to hold
a page number. Each page number
provides a complete duplication of the
microcontroller's memory space. To get to
another 64K Byte page of address space,
Philips Semiconductors Microcontroller Peripherals
Application Note 015
Using memory paging with the PSD3XX
What Is
Paging
(Cont.)
the controller simply has to change the
page number by writing a different value to
the page register.
The circuit below has one major
complication. If the microcontroller is
currently in a particular memory page, page
X, and it changes the page number to Y
using a store instruction which it fetched
from page X, as soon as the store is
PSD3XX
complete the next instruction fetched will
come from page Y. This means that page
Y must pick up the programming sequence
exactly as it was left off from page X. This
is a complication that must be handled in
software and can make programming very
difficult. Additionally, interrupts can be a
significant problem since they must force
the program to an interrupt vector which
may exist on a different page.
Figure t.
Discrete Page
Register
ADO:7
ALE
MCU
....- - - -...- - -....-
ThePSD3XX
Implementation
Figure 2 illustrates the block diagram of the
PSD3XX with the internal page register. It is
similar to the discrete circuit above, but with
some important differences. The page
register provides 4-bits of additional
addressing capability, but does not provide
them directly to the memory devices themselves. Instead, the page register output
bits are taken into the Programmable Array
Decoder of the PSD3XX. This enables the
user to program them as necessary for the
system design.
The PAD provides a flexibility that most
page register implementations are not
capable of providing. If you are unfamiliar
with the capabilities of the PSD3XX PAD,
please consult Application Note 014, USing
the PSD3XX PAD for System Logic
Replacement. Figure 3 illustrates the PAD
logic in a PSD3XX with a page register. The
PAD generates the outputs which are used
to select the PSD3XX's eight EPROM
blocks, the SRAM block, the 1/0 ports, the
shared resource interface, the page register
itself and all external functions which use
May, 1993
386
....-I~(AO:19)
the chip selects provided by Port Band
Port C of the PSD3XX. Thus, the page
register bits may be combined with the
address bits and control signals in any
combination to generate the select Signals
for all of the above resources. In addition,
any or all of the page register bits may be
don't cares in any or all of the PAD chip
select equations, enabling the user to
select which resources may be selcted
from which page, or to select some
resources from any page. This extremely
useful feature enables the programmer to
avoid the problem of software continuity
between pages described above by making
at least one of the EPROM blocks appear
in all pages and then using that block to
contain code for interrupt servicing and
page switching. This is performed simply
by making the page register bits 'don't .
cares' in the chip select equation for that
block. All of this is fully programmable with
the PSD3XX, enabling the deSigner to
choose the paging scheme that is best for
the application.
Philips Semiconductors Microcontroller Peripherals
Application Note 015
Using memory paging with the PSD3XX
PSD3XX
Figure 2.
PSD3XX
Architecture
PAGE LOGIC
P3-PO
~
r - - A11-A15
L
A
T
C
H
AD8-AD15
~
A8-A10
A19
i.-r--
ALE/AS
CSI
ALE/AS
RD
WR
RESET
If
PAD A
13P.T.
ES7
ES6
ES5
ES4
ES3
ES2
ES1
L
A
T
C
H
"--
~~- ...
~
"--
~
1618
_. I·
~
-
,LOGIC IN
PCOPADB
f-+-
27 P.T.
csa-
r-
32K-128K BIT
BLOCK
CS7
~
r
D8-D15
-
SRAM
16K BIT
RESET
X8,X16
MUX or NON-MUX BUSSES
A19/CSI
MaY,1993
387
~
PROG.
PORT
EXP.
PORT
A
PROG.CHIP
CONFIGURATION
PROG.
CONTROL
SIGNALS
~
,
ALE/AS
BHE/PSEN
PBOPORT
B
CSIOPORT
TRACK MODE
SELECTS
WR/RIW
PROG.
PORT
EXP.
DO-D7
~
t
~
-I
AO-A7
ADO-AD7/DO-D7
RD/E
PORT
C
pS8PS10
~ 1-
-
PROG.
PORT
EXP.
EPROM
256K BIT -1 M BIT
1
... - -
-
~
CSIOPORT
A19
CSI
ALE/AS
RD
WR
RESET
'Es():!L ".
~
r---
--+
A16-A18
..- -
'--
ADO-AD7
--
-~
PAOPA7
~
Philips Semiconductors Microcontroller Peripherals
Application Note 015
Using memory paging with the PSD3XX
ThePSD3XX
Implementation
(Cont.)
Figure 3.
PSD3XXPAD
Diagram
The Microcontroller can write or read the
page register to place a new page number
in it or read the current page number. To
perform this, the microcontroller must
simply access the address programmed in
the PAD for the page register. This address
~
-
ESO"'l
.-
;:;
ES1
ES2
'"'S
v
Po
is based on the CSIOPORT select signal
programming. If address 8000 hex is
programmed for CSIOPORT, the
corresponding page register address is
8018 hex and read and write data will be to
and from the page register.
-'"
~
PI
PSD3XX
-'"
~: ~
-'"
-
ESS
ES6
;::;
:~J_s RAM BLOCK SELECT
;:;
.......
..:;
ALEorAS ........
~
.......
v
orRiW
A19
..
~
-
-
.-
-'"
....
..
~
A16
.-
v
A15
..
~
."'S
V
-'"
..::.
..
;::;
.-
A14
v
~
.-
A13
D-
--
--
CSO/PBO
CS1/PB1
Cs2JPB2
~
-
CS3IPB3
J
CS4IPB4
PAD
CSS/PBS
"'S
V
-'"
::
.......
""'S
...
..:;
-
.....
A11
""'S
May. 1993
TRACK MODE
CONTROL SIGNALS
~
A17
REsET
- va BASE ADDRESS
CSADOUT1 }
CSADOUT2
;::;
.-
"'S
CSI
CSIOPORT
CSADIN
N
A18
A12
PAD
A
V
Dor E
8 EPROM BLOCK
S ELECT LINES
""S
..
•
-
~
-'"
388
CS6IPB6
I
~
t>o--
~/PB7
CS8IPCO
CS9/PC1
CS10/PC2
B
Philips Semiconductors Microcontroller Peripherals
Application Note 015
Using memory paging with the PSD3XX
A Simple
Paging
Example
To illustrate the operation of the PSD3XX
page register, assume that a designer
requires a full 128K Bytes of program
storage space, 32K Bytes of buffer SRAM
and three peripheral devices which also
must be memory mapped. We can also
assume that the required program is easily
broken into four modules which are
somewhat independent, but do need the
capability to call one another and must be
able to pass global data among one
another. Further, assume that the
external peripheral devices may be
selected from three of the four modules, but
must not be accessed from the fourth for
security reasons. Lastly, assume that the
designer is constrained by cost and
compatibility considerations to use an 8-bit
microcontroller with a 1S-bit address bus
(in this example, an 8031).
These requirements may be easily
implemented using the PSD313 device.
The PSD313 is an 8-bit device with 128K
Bytes of EPROM for program storage. It
also contains the PAD and page register
logic described above. The memory map
required for this application is shown in
Figure 4.
The memory map shown utilizes the page
register to provide a unique address for all
of the PSD313's 128K Bytes of EPROM in
addition to the SRAM and peripherals. This
memory map consists of four pages of 64K
Bytes each. The map is further divided into
program and data space by the PSEN and
RD signals which are available in the 8031
microcontrol/er. This enables the PSD313
to overlap the addresses of the EPROM,
I/O and SRAM. The pages are numbered
0- 3, and are written into the page register
by the microcontroller. The page register is
part of the I/O addressing and resides in
the RD = 0 map.
The software must be broken into four
segments, one residing in each page, in
order to function efficiently with this
memory scheme. The software which
enables the machine to boot, service
interrupts and switch memory pages is
located in a block of EPROM which is
mapped into all memory pages. This
enables simple page switching and
interrupt servicing regardless of the page
that the microcontroller is currently
operating in. Locating an EPROM block in
May,
1993
389
PSD3XX
multiple pages is very simple using the
PAD 'don't care' feature. In this example,
EPROM block 0 has been chosen to hold
the page-independent software. The PAD
output which controls block 0 is ESO.
Therefore, in the definition of the ESO
Signal, all four of the page register bits
(PO - P3) are programmed as 'don't cares'.
ESO is further defined to be from address
0000 to 3FFF. Thus, whenever the
microcontroller places an address on the
bus which is in this range with PSEN low,
the data will be read from EPROM block 0,
regardless of the contents of the page
register.
The remaining EPROM blocks are evenly
distributed into the four pages. This
segmentation has been used in this
example, but there is no requirement that
the pages contain equal memory sizes.
Each can have a different amount of
resources contained within it. We have
placed EPROM blocks 1 and 2 in page O.
This is done by requiring PO - P3 to be O's
to generate the ES1 and ES2 selects.
Similarly, ES3 and ES4 in page 1, ES5 and
ESS in page 2 and ES7 in page 3 require
the PO - P3 signals to be in the correct
states to generate the ES signals.
The SRAM and I/O devices most likely
must be accessible from all pages, like the
page switching software and interrupt
service routines. In this way, each of the
program segments may store and load
data from the SRAM which may be used to
pass global parameters among the
programs. All programs may also
communicate with the external I/O devices,
which is most likely required. It is very
important that the internal PSD3XX I/O
registers, which include the I/O port control
and data registers as well as the page
register itself, be mapped into all pages.
Otherwise, after the page has been'
switched, there will be no way of switching
back to the original page since the page
register would not be accessible. To make
the page register accessible from all
pages, the designer must simply make the
page register bits (PO - P3) 'don't cares' in
the equation for the CSIOPORT signal.
This can also be done for any of the
external chip select equations which are
generated by the PAD and brought to the
outside world through Port B or Port C.
Philips Semiconductors Microcontroller Peripherals
Application Note 015
Using memory paging with the PSD3XX
PSD3XX
FIgure 4. Memory Map
PSEN=O
PROGRAM
#4
}
ES748-64K
CSIOPORT
~--------------~
RSO
PAGE 3
~ ~~~
}
l_E_s..o_ :
PROGRAM
#3
}
E~
SRAMCS 0 - 32K
CSIOPORT
ESS32-64K
i
RSO
PAGE 2
EXTERNAL
CHIP SELECTS
E~_O :~~~
} __
PROGRAM
#2
}
E~
ES3
__
32
-
EXTERNAL
SRAM
i
RSO
EXTERNAL
CHIP SELECTS
l-:~-~:!~~
}
SRAMCS 0 - 32K
CSIOPORT
64K
PAGE 1
PROGRAM
#1
Eu~
ExtCS1
ExtCS2
EXTERNAL
SRAM
~~
ExtCS1
ExtCS2
SRAMCS 0 - 32K
CSIOPORT
ES2 32 _ 64K
ES1
i
RSO
PAGE 0
EXTERNAL
CHIP SELECTS
l.~~-~~~~~
May. 1993
390
EXTERNAL
SRAM
EuC~
ExtCSO
ExtCS2
SRAMCS 0 - 32K
Philips Semiconductors Microcontroller Peripherals
Application Note 015
Using memory paging with the PSD3XX
A Simple
Paging
Example
(Cont.)
If it is desirable for some pages not to have
access to some resources, this may be
done also. The designer must simply use
the page register bits in the equation which
selects the resource which is to be
protected. This can provide a program
security or error handling feature while
protecting certain I/O or memory devices
from accidental corruption.
Figure 5 contains the output of WSi's
Maple software for the above example.
The part chosen to implement the sample
design was the 8-bit only PSD313, chosen
because it contains the required 128K
Bytes of EPROM but is less expensive
than the PSD303. The PSD303, which also
contains 128K Bytes of EPROM, can be
configured in a 16-bit data bus mode which
would be suitable for use with 16-bit
microcontrollers like the 80196.
The PSD313 was programmed and
configured to implement the memory map
shown in Figure 4. Not all of the capability
of the PSD313 has been utilized in this
example but is available to satisfy other
system design requirements if necessary.
The PSD313 has been configured to
function with the 8031 microcontroller and
its associated control signals. This can be
seen in the Configuration portion of the
output file in Figure 5. We have also
configured Port B 0-3 to provide the
required chip select functions for the
external 110 and SRAM devices. These
chip selects have been given the aliases
ExtCS1, ExtCS2 and ExtCS3 for the 1/0
devices and SRAMCS for the SRAM. The
equations entered for the chip selects
correspond to the addresses for which they
should be active. ExtCS1 will become
active when address 8000 - 87FF hex is
accessed. ExtCS2 and ExtCS3 will
become active for addresses 8800 - 8FFF
hex and 9000 - 97FF hex respectively. The
SRAM chip select will become active for
address 0 - 7FFF hex. All of these chip
selects will function independently from the
page register contents since the page
register outputs (PO - P3) do not appear in
the equations. This means that all of these
external devices will be selectable from
any page.
May, 1993
391
PSD3XX
The address map lists the start and stop
addresses and the page numbers for each
of the blocks of memory and 1/0 inside the
PSD313. The first EPROM block is
selected by ESO, which has been mapped
from address 0000 to 3FFF hex. This block
has been deSignated to contain the page
switching software and the boot and
interrupt service routines. Since all pages
need the capability to switch from one to
another, and since an interrupt may be
received at any time while the software is
executing in any page, EPROM block 0
has been made accessible from all pages
by making the page register bits
'don't cares' (x's) in the address map for
ESO.
ES1 and ES2 map EPROM blocks 1 and 2
into address 8000 - FFFF hex in page O.
Thus, whenever a program address
within this range is accessed by the
microcontroller while the page register
contains a 0, ES1 or ES2 will activate
EPROM block 1 or 2. While the
microcontroller is executing code from one
of these blocks in page 1 , it may still
access internal or external SRAM, or
internal or external 1/0 without changing
pages. ES3 - ES7 are mapped to pages
1 - 3 in a similar manner.
In addition to the external SRAM, the
PSD313's internal SRAM has been
mapped into all address pages where it
may be used to supplement the
microcontroller's register file and internal
SRAM. This SRAM may be used for
global variable storage, stack space or
many other purposes. The PSD313's 1/0
ports have been mapped at address
C800 - CFFF hex in this example. This
places the page register address at C81A
hex (see the PSD3XX data sheet for 1/0
addressing in the PSD3XX). As discussed
earlier, the page register has been mapped
into the same address from all memory
pages, so that it may be accessed from all
program subroutines in the system.
Application Note 015
Philips Semiconductors Microcontroller Peripherals
Using memory paging with the PSD3XX
Flgur.5. MAPLE Softwar. Exampl.
PSD PART USED: PSD313
********************PROJECT INFORMATION*****************
Project Name:
Page Register App Note
Your Name
= Jeff Miller
Date
1/15/92
Host Processor:
= 8031
********************************************************
********************ALIASES*****************************
/CS4
ExtCSl
/CSS
ExtCS2
/CS6
Extcs3
/CS7
SRAMCS
*******************************************************
********************GLOBAL CONFIGURATION***************
Address/Data Mode:
MX
Data Bus Size
8
Reset Polarity:
HI
Security
OFF
ALE Polarity
HI
A15-AO ALE dependent (Y) or Transparent (N):
N
Using Different READ strobes for Data and Program: Y
*******************************************************
********************READ WRITE CONTROL*************
/P.D and /WR
**********************************************
********************PORT A CONFIGURATION **********
ADDRESS/IO
**********************************************
********************PORT A (ADDRESS/IO}*****************
PIN
Ai/IO
CMOS/OD
PAO
AO
CMOS
PAl
Al
CMOS
PA2
A2
CMOS
PA3
A3
CMOS
PA4
A4
CMOS
PAS
AS
CMOS
PA6
A6
CMOS
PA7
A7
CMOS
********************************************************
********************PORT B CONFIGURATION***************
Pin
CS/IO
CMOS/OD
PBO
CSO
CMOS
PBl
CMOS
CSl
CMOS
PB2
CS2
CMOS
PB3
CS3
CMOS
PB4
CS4
CMOS
PBS
CS5
CMOS
PB6
eS6
CMOS
PB7
CS7
********************************************************
May, 1993
392
PSD3XX
Philips Semiconductors Microcontroller Peripherals
Application Note 015
Using memory paging with the PSD3XX
PSD3XX
Figure 5. MAPLE Software Example (Cont.)
******************PORT B CHIP SELECT EQUATIONS************
I
ExtCSl
(A15 * IA14 * IA13 * IA12 * IAll *
IpO
+ A15 * IA14 * IA13 * IA12 * IAll * IP1)
ExtCS2
I (A15 * IA14 * /Al3 * /A12 * All * /PO
+ A15 * IA14 * IA13 * /A12 * All * /Pl)
ExtCS3
I (A1S * IA14 * /A13 * A12 * IAll * /PO
+ A1S * /A14 * IA13 * A12 * /All * IP1)
SRAMCS
I (/A15)
******************PORT C
Pin
CS/Ai
pco
A16
A17
A18
CSI
PCl
PC2
A19
CONFIGURATION**********~*******
LOGIC/AODR
LOGIC
LOGIC
LOGIC
********************************************************
*****************PORT C CHIP SELECT EQUATIONS***********
******************************AODRESS MAP***********************************
A A A A A A A A A SEGMT SEGMT FILE
19 18 17 16 15 14 13 12 11 STRT STOP STRT
FILE
STOP
File Name
Page Reg Q.F
3210
ALE
X
3fff 0
XXXX
3fff PROGO.HEX
ESO
N 0 0 0 0 0 N N N 0
0000
X
3fff PROG1.HEX
ESl
N 0 0 0 1 0 N N N 8000 bfff 0
0000
X
ES2
N 0 0 0 1 1 N N N cOOO ffff 4000 7fff PROG1.HEX
0001
X
3fff PROG2.HEX
ES3
N 0 0 0 1 0 N N N 8000 bfff 0
0001
X
4000 7fff PROG2.HEX
ES4
N 0 0 0 1 1 N N N cOOO ffff
X
0010
ESS
3fff PROG3.HEX
N 0 0 0 1 0 N N N 8000 bfff 0
0010
4000 7fff PROG3.HEX
X
ES6
N 0 0 0 1 1 N N N cOOO ffff
X
0011
ES7
3ff! PROG4.HEX
N 0 0 0 1 1 N N N cOOO ffff 0
X
N/A
N/A
N/A
XXXX
RSO
N 0 0 0 1 1 0 0 0 cOOO c7ff
N/A
X
N/A
N/A
XXXX
CSP
N 0 0 0 1 1 0 0 1 c800 cff!
****************************************END***********************************
*********************AODRESSES OF I/O PORTS****************
C802 Page (Binary) : XXXX
Pin Register of Port A :
Direction Register of Port A
C804
Data Register of Port A :
C806
C803
Pin Register of Port B :
Direction Register of Port B : caos
Ca07
Data Register of Port B :
Page Register :
C81A
************************************************************
May, 1993
393
Philips Semiconductors Microcontroller Peripherals
Application Note 015
Using memory paging with the PSD3XX
Softwar,
Considerations
May. 1993
PSD3XX
The software example shown in Figure 5,
has been divided into four sections to
facilitate placing it into the four pages.
These four program blocks have been
called PROG1.HEX, PROG2.HEX,
PROG3.HEX and PROG4.HEX. In order to
create these files to be loaded into the
PSD3XX, the software designer must plan
for this event when the software is written.
It is most easily accomplished by breaking
the tasks into logical groups that do not
need to access one another frequently.
Most software can be split in this manner.
Then, the designer can create the page
switching algorithm which is used to jump
between the tasks which are on different
pages.
To build the table, the labels of all
subroutines which may be shared among
pages must be accumulated from all of the
programs. These labels must be placed in
the table along with the corresponding
page numbers. This table must then be
placed in the global EPROM block. The
labels must be made global so that each
program may have access to them. Then
pointers into the table must be assigned,
one for each global subroutine. These
must also be made global so that they may
be used by each program. The pointers
must remain constant, even when the
software is modified. This way, software
modifications may change the values of the
labels, but not the pointers.
There are many ways to implement this
capability, but we will provide as an
example one method which can be used.
This method of memory paging involves
the use of a table of addresses and page
numbers of all program tasks which may be
called from page to page. This table can be
made global when the code is compiled so
that it may be used in all four of the
programs used in this example. This table
would reside in EPROM block 0 along with
the interrupt service routines and page
switching algorithms so that it may be
accessed from all memory pages. Thus,
when PROG1 is executing and must run a
task or subroutine which is in PROG2, the
software should jump to the page switching
algorithm while passing the table lookup
address of the task that it wishes to run. In
this way, only the pointer into the table
must be known by all programs instead of
the address and page number of each
routine. This simplifies the process of
modifying the software by permitting the
programmer to keep all of the pointers into
the table constant, even if the actual
subroutine addresses change. In this
table, the page switching routine will find
the page that it must switch to as well as
the address to jump to after the page has
been switched. The return address and
page number may simply be pushed onto
the stack, which is stored in the SRAM.
Since the SRAM is also page independent,
all programs may share the same stack.
This provides a very clean paging solution
which may be implemented using high level
language compilers. The only penalty when
using this method is the overhead
experienced when switching from page to
page. This overhead may be minimized by
careful software design which minimizes
the number of program calls and jumps
between routines on different pages. Care
must also be taken when nesting jumps
from page to page if it is important to keep
track of return addresses. Interrupts, since
they are accessible from all pages, are very
simple to handle. The page need not even
be switched to service an interrupt unless
the service routine needs to access a task
which is not located in the global EPROM
block. Even then, the only consideration is
that before returning from the interrupt, the
page number must be restored to its value
prior to the interrupt. This paging scheme
is illustrated in Figure 6.
394
Philips Semiconductors Microcontroller Peripherals
Application Note 015
PSD3XX
Using memory paging with the PSD3XX
Complier
Issues
The paging algorithm shown below is
relatively easy to implement and somewhat
automatic. However, it is not a totally
transparent solution for the software
programmer. There is such a solution
available from at least one compiler
manufacturer. Archimedes makes
compilers for several microcontrollers
including the 8031 family and 68HC11
family. These compilers are available with
built in memory paging which use some of
the microcontroller's port bits as additional
address bits. These compilers generate
bank switching code automatically which
can be easily modified to utilize the page
register inside the PSD3XX.
When this is done, the use of the page
register becomes transparent to the user.
The attached code excerpt shows the
calling structure resulting from the use of
the Archimedes compiler with the
modifications to utilize the PSD3XX page
register.
Figure 6.
Software
Paging
Flow
SUB#1
PROG 1PAGE 1
SUB#2
PROG 2PAGE 2
SUB ADDR 1
SUB ADDR2
SUB ADDR3
PN
PN
PN
n
PN
··
SUB ADDR
May, 1993
,,
,,
,,
,,
,,
,
- - - - - - - -I---------l
395
PAGING
PROGRAMPAGE 0
Application Note 015
Philips Semiconductors Microcontroller Peripherals
Using memory paging with the PSD3XX
PSD3XX
Archimedes Code
836
837
838
\
\
\
0268
026A
026D
7400
900000
120000
/* Init DCC & SCR registers */
init_dsl_hdsl_dcc_scr();
MOV
A,#$BYTE3 init dsl hdsl dcc scr
MOV
DPTR,#REFFN inIt dsl hdsl dec scr
LCALL
?X_CALL_L18
-
7400
90000'0
120000
/* Init Master/Slave Polynomial */
init_ms_poly();
MOV
A,#$~YTE3 init_ms_poly
MOV
DPTR,#$REFFN init~-poly
LCALL
?X_CALL_LI8
839
840
841
\
\
\
0270
0272
0275
842
843
844
845
}
Notes: 1.
2.
$Byte 3 is a directive that addresses the "page" of the
specified function.
$REFFN Addresses the 16-bit offset of the function.
MODULE
TITL
RSEG
?BANK SWITCHER L18
'8051-- C - BANK-SWITCHER'
RCODE
i-------------------------------------------------------------------;
- L18.S03 Function{s):
Banked switched CALL and RET
Must be tailored for actual bank-switching hardware.
In the sample system the PI port was. used.
Version: 4.00
[IANR]
;-------------------------------------------------------------------;
i-----------------------------------------------------;
Call a non-local function
Inputs:
Stack: 16-bit return address
DPTR: 16-bit function-address
A: 8-bit page address
The above Archimedes code is courtesy of Jeff Fayne, Tellabs, Inc.
May, 1993
396
Application Note 015
Philips Semiconductors Microcontroller Peripherals
Using memory paging with the PSD3XX
Archimedes Code (ConI.)
PUBLIC
Save.old bank
PUSH
Pl
Bank-switch
MOV
Pl,A
Go to function
CLR
JMP
A
@A+DPTR
;-----------------------------------------------------~
Leave current function
;----------------------------------------------------- i
Input:
Stack:
24-bit return address
;-----------------------------------------------------;
PUBLIC ?X_RET_L1S
?X_RET_L1S:
=============================
Bank-switch
pop
Pl
Return
=============================
RET
END
May, 1993
397
PSD3XX
Philips Semiconductors Microcontroller Peripherals
Application Note 015
Using memory paging with the PSD3XX
CORclus/OR
May, 1993
The PSD3XX page register system can
greatly assist designers of systems
requiring large memory spaces with 16-bit
address buses. The PSD3XX offers
capability not found in most discrete page
register implementations. The capability to
define global resources as well as
page-specific resources enables the
designer to implement the paging
technique most suitable for the application.
The page register is included in the
PSD302, PSD312, PSD303 and PSD313
devices, all of which are pin compatible
398
PSD3XX
with one another. This provides the
capability of expanding the memory size as
required even after a system has been
designed. The designer can simply drop
the new, and larger, PSD3XX into the
same footprint as the old, and update the
software to add more memory pages. This
capability can be important for product
feature additions after a design is
complete. Since the system is fully
programmable, it may be updated and
changed anytime.
Philips Semiconductors Microcontroller Peripherals
Power considerations in the PSD3XX
Application Note 016
PSD3XX
By Jeff Miller - WSI
Introduction
The PSD3XX is a configurable microcontroller peripheral integrating programmable
logic, EPROM and SRAM technologies into
a single piece of silicon. It has been used
extensively in microcontroller applications
around the world by virtue of its high level
of integration, configurability and ease of
use. This integration makes possible the
design of very compact microcontroller
systems, enabling the user to squeeze a
great deal of functionality into a very small
space. Thus, the PSD3XX has found its
way into many small hand-held and/or
battery operated applications such as
cellular phones, medical instrumentation
and laptop or notebook computers which
usually require, in addition to small space,
a very low power consumption.
The PSD3XX family is based on a patented
high-performance CMOS technology and,
Power Use
In The PSD3XX
The PSD3XX contains several modules
internally, each of which can be considered
a power consumer when in operation.
These modules include the PAD,
(Programmable Address Decoder)EPROM
and SRAM blocks. The key to reducing the
power used by the PSD3XX is to reduce
the power used by each of these modules
individually.
Under normal operation, several of the
functional modules may be operating, while
others may be standing by. A module in
stand by uses much less power than one
that is active. For example, whenever the
SRAM is not being actively used, it is
disabled and therefore consumes less
power. This is also true of the PAD. A PAD
term which is active expends more power
than one which is inactive. This would also
be true of the EPROM. However, in some
PSD3XX models, the EPROM is always
active, in which case it will always draw
power. This is done in order to provide the
best access time possible for the EPROM.
The Low Power family of PSD3XXs does
not keep the EPROM enabled at all times,
May, 1993
399
like other CMOS devices, requires very
low power consumption even when no
particular effort is made to minimize the
PSD3XX power. But, when some special
care is taken during the programming
and configuration of the device, power can
be reduced even further, making the
PSD3XX even more valuable in these
power-sensitive applications. This
application note will describe the methods
which can be used to reduce the PSD3XX
power consumption in both active and
stand-by modes. It makes sense to use
some of these techniques even when low
power is not a primary design requirement
since they are easy to implement and
require no additional expense. We believe
that proper implementation of the material
in this note will make the PSD3XX an
invaluable member of any low-power
microcontroller system.
and thus the designer can save power by
minimizing the time during which the
EPROM is accessed. Use of this feature
does impact the speed of the PSD3XX
EPROM, which results in the loss of the
120 ns speed grade. There are other
methods of reducing EPROM power even
when the EPROM is enabled. These will
be discussed in detail later in this note.
When the time that each PSD3XX function
is kept in standby mode is maximized, the
power expense is minimized.
There is a way to place the entire PSD3XX
into the standby mode at once, thereby
reducing power usage to the bare
minimum. This can be done through the
use of the CSI (Chip Select Input) pin.
When the PSD3XX is deselected by the
CSI pin, the entire part enters the standby
mode using only about 50 jJA of current.
While in this mode, the PSD3XX is
incapable of performing any functions,
including PAD logic equations, but this is
an excellent method of reducing system
power in designs which have low active
duty cycles.
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
CMOS
Power
Characteristics
As a CMOS part, the PSD3XX behaves in
the same way as other CMOS devices in
terms of power dissipation. The PSD3XX
consumes the most power when the
temperature is low, the voltage is high and
the frequency is high. Low temperature in
CMOS devices, unlike in bipolar devices,
causes the transistors to speed up, thus
consuming more power. Therefore, if the
system will never operate in low temperature
environments, power dissipation will be
lower. Another result of this characteristic
is that CMOS parts do not generally
experience thermal runaway. As temperature
increases, the power expended by the
CMOS device decreases, thus the part tends
to effectively cool itself off.
Another characteristic of CMOS devices is
the effect of voltage variations. CMOS
behaves similarly to TTL devices with
respect to voltage. When input voltage rises,
Figure t.
Typical CMOS
Output Circuit
the current drawn by a CMOS device also
rises. As input voltage falls, input current
also falls. Thus, the CMOS device will draw
the least current at its lowest allowable
supply voltage. This voltage is 4.5V in the
PSD3XX. Taking the voltage below this level
will generally slow the device down to below
its specified speed as well as jeopardize its
data retention capability. Between 4.5 and
5.5V, the PSD3XX varies by about 0.85mA
per 0.1 V variation. Thus, the PSD3XX will
draw approximately 0.85 rnA less current at
4.9V than at 5.0V Vcc.
Lastly, frequency of operation plays an
important role in the power dissipation of a
CMOS device. A CMOS gate expends the
greatest power while it is switching between
the logic 0 and logic 1 states, or vice versa.
This can be easily understood when looking
at the circuit diagram for a typical CMOS
output shown in Figure 1.
Vee
.......--......-OUTPUT
The circuit above represents a typical
CMOS inverter output. Normally, either the
top transistor is off (output = logic 0) or the
bottom transistor is off (output = logic 1).
MOS transistors have very low leakage
currents which means that under these
normal conditions, very little current will be
passing from Vcc to ground. However,
when the input to the inverter is switching,
both transistors will not switch from their
present conditions to their new conditions
at precisely the same instant. Therefore,
both transistors will be on for a very brief
instant during the transition. During this
time there is a low impedance path from
Vcc to ground and some current is drawn
by the circuit. In addition, the output will
have some load capacitance (Cd
which must be charged during switching,
May, 1993
400
even if the load itself draws little or no static
current. Thus, during the switching process
the power expended by a CMOS device is
at its highest.
The switching current drawn by the device is
dependent on the number of times the
outputs are forced to switch logic states in a
unit of time. Therefore, the frequency of
operation of the part directly influences its
dynamic power consumption. The lower the
operational frequency, the lower the
dynamic power expended by the device. In
the PSD3XX, frequency of operation is
determined by the rate at which the
addresses are changing, usually indicated
by the frequency of the ALE or AS signal.
Generally, the PSD3XX draws about 3 rnA
of additional current for each 1 MHz added
to the frequency of operation.
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
Power
Management
Techniques
In The PSD3XX
The above mentioned features and characteristics can be used to the designer's
advantage when designing compact microcontroller systems which have a tight
power budget. In the sections that follow,
several methods for reducing the PSD3XX
power will be presented.
Power Down Mode
Many system designs do not require the
microcontroller, and therefore the PSD3XX,
to operate continuously. Systems, like
cellular telephones and notebook
computers, spend a large amount of time
inactive - waiting for something to happen
like a press of a button or keyboard. During
this time, many designers place the microcontroller into a low power idle or sleep
mode. In the sleep mode, the controller
expends significantly lower power. The
microcontroller is usually awakened by
some event - a key on a keypad being
pressed, for instance, which may result in
an interrupt. There is no need for the
PSD3XX to be active during the time that
the microcontroller is not active. Therefore,
the PSD3XX should be placed in the
power down mode (CSI inactive) to reduce
the PSD3XX current down to its standby
value.
The PSD3XX must also be awakened
when the microcontroller is awakened so
that it may provide an instruction to the
controller when it requires one. If the
microcontroller itself has a chip select
output, like the Motorola 683XX series
controllers, it may be used to awaken the
PSD3XX as necessary. However, if it does
not, there will be a problem. If the microcontroller itself is used to power down the
PSD3XX, through an I/O port pin for
example, there will be no way to power up
the PSD3XX again since the PSD3XX
itself contains the instruction that the
microcontroller must use to activate the
CSI signal to awaken the PSD3XX. The
way to correct this situation is to design a
circuit which detects when the microcontroller is coming out of its power down
mode before it must fetch the first instruction. Such a circuit is depicted in Figure 2
Figure 2.
Simple Power
Down Circuit
PSD301
68HC11
74ACT05
E
XJ~---'------1
In this circuit diagram, a Motorola 68HC11
microcontroller is connected to a PSD3XX
in a low power system. The circuit functions
quite simply. The E signal from the HC 11 is
normally a free running clock at 1/4 the
frequency of the input clock. When the
HC11 is placed into the sleep mode by the
software (by executing the STOP
instruction), the E signal stops oscillating
and remains low until an interrupt or
May, 1993
401
CSI
internal timer event occurs. After the
interrupt has been received by the
controller, the E signal resumes toggling,
but there will be a minimum of two E
clock cycles prior to the first AS. This
characteristic can be used to place the
PSD3XX into its low power standby mode
whenever the STOP has been executed in
the HC11 and to awaken it before it must
supply an instruction to the HC11.
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
Power
Management
Techniques
/n The PSD3XX
(Cont.)
capacitor to slowly charge up to a logic one
level which then places the PSD3XX into
the standby mode in which it will consume
only about SOJ.LA of current. After the
controller exits the sleep mode, the E signal
will resume oscillating which rapidly
discharges the capacitor. This, in turn,
activates the CSI input to the PSD3XX,
bringing it out of the power down mode.
Since the E signal will oscillate for at least
two full cycles before the first AS strobe
begins a new bus cycle, the PSD3XX will
have ample time to recover from the power
down mode before having to supply an
instruction to the HC11 for processing. In
operation, the circuit results in a timing
diagram similar to the one in Figure 3.
The ACTOS device shown in the diagram is
simply an open collector inverter. When the
E signal is oscillating, the output of the
inverter will be toggling between ground
and high impedance. When the output is at
ground, the capacitor will rapidly discharge
from its present state into the ACTOS.
When the output is high impedance, the
capacitor will slowly charge up to Vcc
through the resistor. Thus, under normal
operation the CSI input of the PSD3XX will
be at or near 0 V, provided the RC time
constant is large enough to prevent the
capacitor from charging up beyond a logic
zero level of 0.6 V.
When the HC 11 enters the sleep mode the
E signal remains low. This enables the
Figure 3.
6BHe11 Stop
Timing
STOP ACTIVE
A similar circuit can be used for Intel 8031
type controllers. Controllers conforming to
the Intel 8031 family generally have two low
power modes: IDLE and POWER DOWN.
The·IDLE mode causes the controller to
cease instruction execution, but its internal
clocks continue to run. This saves
significant power while leaving the internal
RECOVERY
timers and other functions operational.
When in the IDLE mode, both the ALE
signal and the PSEN signal are held high.
A circuit similar to the one illustrated for the
68HC11 may be used to detect the end of
oscillation on the ALE signal. This circuit is
shown in Figure 4.
Flgure4.
BOa1/dle
Circuit
PSD301
8OC31
74ACT09
I
May. 1993
402
C
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
Power
Management
Techniques
In The PSD3XX
(Cont.)
The circuit operates on the same principle
as the one used earlier for the Motorola
processor. The ALE signal normally
oscillates high for 2 clocks out of every 6 or
12 clocks, depending on whether
instruction or data accesses are being
performed. The software places the 8031
into the Idle mode by setting bit 0 in the
PCON register. Once set, the ALE and
PSEN signals remain high until an interrupt
or hardware reset occur. During this time,
the CSI signal will float high with the RC
circuit, as in the earlier example. The
ACT09 is simply an AND gate with an
open collector output. It performs the same
function as the inverter in the previous
example without inverting the signal. When
an interrupt or reset is received, the ALE
signal begins to toggle again, but at least
two "dummy" unused ALE cycles will occur
before the first meaningful instruction is
fetched, giving the PSD3XX time to
recover from the power down mode. The
timing for the above circuit is shown in
Figure 5.
FigureS.
B031 Idle
Timing
ALE
CSI
If the system requires truly the lowest
power available, the 8031 POWER DOWN
mode may be used. This disables all
internal operations of the 8031 as well as
the external ones. Thus, anyon-chip
peripherals like timers and serial communication links will be disabled. This places the
controller into its lowest power mode
possible. Software may place the 8031 into
the POWER DOWN mode by setting bit 1
in the PCON register. When execution of
the instruction is complete, the ALE signal
will be driven low and will remain in this
Flgure6.
B031 Power
Down or Idle
Circuit
state until a hardware reset is received.
Thus, a circuit similar to the one above may
be used to detect the static condition
of the ALE signal, but an inverting gate
must be used instead of the ACT09
(such as the ACT05 used in the Motorola
example earlier).
If both the POWER DOWN and IDLE
modes must be used, the gate may be
replaced with an ACT266 exclusive NOR
with an open collector output. This circuit is
shown in Figure 6.
R
I/O BIT
8OC552
PSD301
ALE
CSI
74ACT266
May, 1993
403
JC
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
Power
Management
Techniques
In The PSDaXX
(Cont.)
The 1/0 bit can be provided by either the
PSD3XX or the controller itself. If the
controller is used to provide the I/O bit, it
must hold the correct value on the output
even when in the idle or sleep mode, as the
PSD3XX does. When the 1/0 bit is low, the
POWER DOWN mode is enabled (a low on
ALE and a LOW on the 1/0 bit will result in
a high on CSI). When the 1/0 bit is high,
the IDLE mode is enabled (a high on ALE
and a high on the I/O bit will result in a high
on CSI).
For all of the above circuits to operate
correctly, the value of the RC network must
be carefully calculated to insure proper
operation in the normal mode. This means
that under normal operation, CSI must
never climb above 004 V, which will
guarantee that it is always recognized by
the PSD3XX as a low.
For example, the 68HC11 circuit shown in
Figure 2 used the E signal from the
controller to disable the PSD3XX. The E
signal oscillates at 1/4 the frequency of the
HC11's input clock. If an 8 MHz HC11 is
used, the E signal will oscillate at 2 MHz.
This results in an E signal clock period of
500 ns. During this 500 ns the E signal will
be low for 250 ns. Thus, the RC network
must be chosen to prevent the CSI signal
from climbing above 004 V for at least
250 ns. The equation below governs the
voltage across the capaCitor (Vd, and thus
the voltage present on the CSI pin:
Ve
= Ved1
- e-VRC)
where Ve is the voltage across the _
capaCitor (which is the same as the CSI
pin), Vee is the supply voltage, and t is the
time in seconds after the output of the open
collector gate switches from a low to an
open circuit. Solving for RC we get:
RC
= -Vln(1-VeNed
In order to determine the minimum values
for Rand C, we must solve this equation
for the point of time which is of interest. We
must have Vc no greater than OAV at time
t = 250 ns. Thus, with Vee = 5 V, the
equation may be rewritten as follows:
RC
= -250 x 10-9/1n (1
- 00415.0)
3.0 x 10-6
May, 1993
404
=
An acceptable RC network for this case
might be a resistor of 100K!} and a
capaCitor of 30pF. These values will
provide no margin for the circuit so some
additional resistance or capacitance may
be desired. Of course, larger values may
be used without harming the circuit, they
will just cause the low power mode to be
entered more slowly. The case of leaving
the low power mode is less critical, since
the capacitor will discharge more quickly
through the gate than it will charge up
through the resistor. In the interest of
minimizing power use by the circuit itself, it
is best to use a larger resistor value and a
smaller capaCitor value, since this will
cause less current to be sunk by the gate
which drives the circuit.
Using this equation, it is possible to
determine the RC value required for any
controller andlor frequency. It is only
necessary to determine the length of time
that the RC will be required to hold the CSI
signal below 004 V and plug that value into
the above equation.
If a more deterministic method is desired
for placing the PSD3XX in the power
down mode, a fully digital circuit may be
implemented which uses very few additional components. This circuit is shown in
Figure 7 for the 68HC11 controller.
This circuit performs the same function as
the RC circuit described earlier, but does it
digitally. The 74ACT164 is a shift register
which is used in this example to detect
when eight HC11 input clocks occur while
the E signal remains low. In normal
operation, no more than two clocks should
occur without E transitioning from low to
high, thus providing a clear to the ACT164.
If the HC11 is stopped, the E signal will
remain high until an interrupt is received,
but the input clock continues to run freely.
Thus, the shift register will shift in "one's"
until the E signal goes high again. When
the ACT164 has shifted eight times, the
CSI signal will go high, placing the
PSD3XX into the power down mode. The
timing diagram corresponding to this circuit
is shown in Figure 8.
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
Figure 7.
Digital Sleep
Circuit For
6BHC11
OSC.
PSD301
68HC11A1
74ACT04
E
FigureS.
6BHC11 Stop
Mode Timing
STOP ACTIVE
RECOVERY
ClK
E
CSI ____+-____________~
Power
Management
Techniques
In The PSD3XX
(Cont.)
May. 1993
A similar circuit may be used for the 8031
family of controllers, and is depicted in
Figure 9.
This circuit, like the others, detects when
ALE stops toggling. Since up to 10 clocks
may normally occur without an ALE pulse,
a counter which can count to at least 11 is
required in order to function properly. Thus,
an 8-bit shift register like the one used with
the HC11 will not work. In this case, a
74ACT191 is used to count 16 clocks prior
to raising its MAXIM IN output high. A low
on the ALE signal will load zero's into the
counter and clear the MAXIMIN output. The
MAXIMIN output is also used as the
405
counter enable to prevent the counter from
counting further after attaining the count of
16. The circuit shown will function with the
IDLE mode of the 8031. If the POWER
DOWN mode is used, an inverter must be
inserted in the ALE signal path.
Other controllers, not listed here, may also
have power down modes which may function with these circuits. Any controller which
has some sort of external indication when
the power down mode has been entered
may usually be used to place the PSD3XX
in its low power mode also.
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
FlgureB.
Digital Sleep
C/rcultfor
B031 Family
74ACT191
ClK
A
8OC31
B MAXI
C MIN
D
ALE I---+----t lOAD
DIU
CSI
PSD301
CTEN
Power
Management
Techniques
In The PSD3XX
(Cont.)
PAD Programming Techniques
The preceding section has described
methods of using the power down
capability of the PSD3XX with several
microcontrollers. There are also techniques
which may be utilized during programming
of the device to further reduce power.
These techniques can significantly reduce
the power expended by the PSD3XX when
it is in full operation.
The programmable logic section of the
PSD3XX, called the PAD, provides much of
its great flexibility and configurability. It is
used to control the internal resources of the
PSD3XX and can also be used to control
external resources as well. The power
use of the PAD varies greatly depending
on how its product terms are programmed
and used.
The PAD is illustrated in Figure 10. It is
divided into two sections, called PAD A and
PAD B. PAD A is responsible for generating
the control and selection for the internal
resources of the PSD3XX and utilizes 13
product terms to perform these functions.
\ PAD B provides any external chip selection
and logic replacement that is necessary for
the system and has 27 product terms for
this purpose. A single product term is
functionally illustrated in Figure 11.
May. 1993
406
Each of the PAD inputs and its complement
is available to each of the 40 product terms
of the PAD. Each of these inputs is
connected to an n-channel transistor which
is used to connect the entire line to ground
when the input is in the appropriate state. A
high on the input to the gate causes the
transistor to turn on. When the device is
programmed, each of these transistors may
be left in place or may be functionally
removed (programmed out) from the circuit.
If all of the transistors are programmed out,
the line is left connected only to the pull-up
resistor which makes it always high. Thus,
the output of the inverter is always low. If
an equation such as:
ICSx
= 1n#1
• /In#2
~ogrammed into the PAD, the out~ut .
CSx must be high except when 1n#1 IS high
and In#2 is low. Thus, all of the transistors
are programmed out except the ones
connected to 1n#1 and In#2. This means
that unless In#1 is high and 1n#2 is low,
there will always be at least one of the two
remaining transistors turned on, which in
turn results in the CSx output being high.
When the appropriate input condition is
met, the remaining two transistors will turn
off, which allows the output to become low.
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
Figure 10.
PAD
Illustration
AL
~
E~
"
~
RNi .. '",
"
or
"S
A1a
"
,...
A19
:D-
. '"
"S
A17
"
.g
A1S
-g
A14
,...
CS1/PBl
-
CS2/PB2
-
CS3/PB3
~
....
;:;.
CS4/PB4
"
CS5/P85
"""S
PADB
.~
A13
~
r-..t"\.
~
...
V
A12
'"
"S
A11
. """S'"
;:;.
eS6/PB6
-
CS7/PB7
K
...
eSI
RESET
Figure 11.
Product
Term
Functionality
Vee
CSO/PBO
.--
.g
A16
I
PAD A
H
-
"""S
I
ESl
ES2
8 EPROM Block
ES3
ES4
Select Lines
ES5
ES6
ES7
RSO _ _ SRAM Block Select
eSIOPORT_I/O Base Address
eSADIN
Track Mode
eSADOU
} Control Signals
eSADOU
"
-
..
-
..
IN #1
IN #2
t>o-t>o-t>o--
CS8/peO
eS9/PCl
CS10/PC2
IN#n
CSx
May, 1993
407
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
Power
Management
Techniques
In The PSD3XX
(Cont.)
As can be seen in the figure, the product
term expends very little power when all of
the transistors are either programmed out
or turned off. The only power used in this
case is the result of the leakage current
through the various off transistors, which is
very low in CMOS technology. When one or
more of the transistors is turned on, there
will be current drawn through the pull-up
resistor to ground. Therefore, the power
used by a product term varies greatly
according to the way it is programmed.
Experimental data has shown that a
product term with all of the transistors
programmed out draws approximately
380J,lA less current at room temperature
and 5.0 V Vcc than a product term which
has some active transistors. WSl's MAPLE
software packages take advantage of this
fact to reduce power as much as possible.
When the user intends to use some or all of
the Port 8 pins as 1/0 signals, then they are
not connected to the PAD in any way. Thus,
the MAPLE software is free to program the
unused PAD 8 product terms in any way. In
MAPLE versions 4.038 and subsequent,
the software automatically programs out all
transistors in each unused product term,
which can eliminate up to 24 product terms
for Port 8. This results in a power reduction
of up to 9.1 mA.
If one or more of the Port C pins is
programmed as an address or logic input,
MAPLE is free again to program out all of
the transistors in each unused PAD 8
product term dedicated to Port C. This can
eliminate up to 3 additional product terms
resulting in a power reduction of over 1 mA.
Finally, there are three product terms from
PAD A which are dedicated to controlling
the Port A Track Mode operation. If the
Track Mode is not used in the application,
these product terms may also be
eliminated by MAPLE for a power reduction
of over 1 rnA.
The remaining ten product terms are the 8
EPROM select lines, the SRAM select line
and the I/O port select line. These terms
may not be eliminated by MAPLE without
disrupting the operation of the device. But
in a system which uses Port A and Port 8
as 1/0 or address outputs, and Port C as
address or logic inputs, the total system
power saving is 10.2 mA typical.
May, 1993
408
The same methods may also be used in
non-multiplexed microcontroller
applications. In this case, Port A and Port 8
may be used as microcontroller data input
pins, depending on whether the controller is
8- or 16-bit. As in the earlier cases, if the
ports are used as data input pins, they are
not connected to the PAD which allows
MAPLE to program out the appropriate
product terms.
Again, MAPLE 4.038 or a subsequent
revision must be used to obtain this
capability. If your software is an older
revision, contact your local WSI regional
sales office for a free update.
EPROM Programming Techniques
Like the PAD, the EPROM in the PSD3XX
uses varying amounts of power depending
on how it is programmed. When
programmed to a one, an EPROM bit
draws more current than when
programmed to a zero. Thus, for minimum
power usage it is best to have the majority
of the EPROM programmed to zeros.
Unfortunately, the contents of the EPROM
are fixed by the program and data
requirements of the system and thus
cannot be easily optimized for power.
However, the user can program all unused
sections of the EPROM to zeros. This will
not substantially cut the power used by the
PSD3XX under normal operation when
EPROM accesses are being performed, but
it will reduce the power consumption during
periods when there is not a valid address
on the bus because these invalid
addresses will often point to unused
EPROM locations. When an EPROM
location is currently addresse.9z..it is _ _
expending power even if the RD or PSEN
signals are not actually enabling an output.
Therefore, it is best that unused EPROM
locations be filled with zeros so that power
is minimized during these periods of invalid
addresses. It should be noted that all power
figures used in this application note as well
as those specified in the PSD3XX data
sheet are based on an average of 50%
"ones" and 50% "zeros" contained in the
EPROM. An EPROM location programmed
to "ones" will draw approximately 1.5 mA of
additional current over an EPROM location
programmed to "zeros".
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
Power
Management
Techniques
In The PSD3XX
(Cont.)
An even better way to help minimize power
usage is to control the addresses which
appear on the bus when there is no valid
address being driven by the microcontroller.
The least power expense will be when this
unused address points to an area which
has no PSD3XX resource mapped into it.
This will result in no internal resource block
receiving a chip select and thus the least
amount of current will be drawn. The next
best approach is to have the unused
address point to an EPROM area
containing zeros. The next lowest power
would be to have the unused address point
to an EPROM area containing something
other than zeros. Finally, the highest power
will occur when the unused address points
to an SRAM location.
Since there is not much that can be done
about the address that is appearing at the
output of the microcontroller, the best that
can be done is to know what address the
controller will have active on its bus at
various non-operational times and insure, if
possible, that the PSD3XX's address map
maps that address into a desired range of
memory (preferably no memory at all). This
will truly minimize the power expended by
the PSD3XX during these times.
Summing
After taking all of these factors into
account, what kind of power use can you
expect from the PSD3XX in your own
system? As a guideline, we will calculate
the typical power required of a PSD3XX
installed in a hypothetical system. The
requirements of this system are listed in
Table 1.
and temperature conditions specified. The
base power of the PSD3XX is the power
used by the PSD3XX when only the
product terms which control the EPROM,
SRAM and I/O ports are not programmed
out (10 active product terms). The base
power also assumes that no internal
resources (EPROM, SRAM and I/O ports)
are being currently accessed. The current
drawn by the PSD3XX under these
conditions has been determined
experimentally to be 16 rnA. To this current,
we must add additional current for the other
active product terms, SRAM access and
EPROM access.
/tAil Up
Using this information, we can calculate
the approximate typical power
requirements of the PSD3XX. Before we
can begin, we must know what the base
power of the PSD3XX is under the voltage
Table 1.
Hypothetical
System
Requirements
May, 1993
Characteristic
Specification
PSD3XX Operational Frequency
2MHz
Port A
Port B
Port C
CSI
Vee
Temperature
Standby duty cycle
EPROM duty cycle
SRAM duty cycle
Address Output
4 Chip Select, 4 I/O
Logic inputs
Configured for Auto. Power Down
5.0V
25°C
60%
30%
10%
409
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
Summing
/tAl/Up
(Cont.)
The system is requiring only four of the 11
available chip select outputs. Therefore,
most of the PAD B product terms may be
programmed out. To determine how many
product terms we will be using, we must
look at the equations for the four chip
selects. Assume that the following equations are to be used:
/CS#1 =/(A15· A14· RD + A13· A12· WR)
/CS#2 = /(/A18 + /A17)
/CS#3 =/(A16· A18 + A17· ALE)
/CS#4 = A17
In order to configure the system for the
lowest power usage, we must be sure that
we place these chip selects on the output
pins which will require the minimum
number of product terms to remain
active. Since the maximum number of
product terms required to generate the
above equations is only two, there is no
need to place these chip selects on Port B
pin 0,1,2 or 3 since these pins each have
four product terms. The lower power
configuration would place these chip
selects on Port B pin 4,5,6 and 7, where
only two product terms will be drawing
power for each chip select. One of the
above chip selects, #4, actually requires
only one product term, meaning that it
could be placed on one of the Port C pins
which have only one product term.
However, all of Port C is used in this case
Table 2.
Summary of
PSD3XX Current
Usage In
Hypothetical
System
If we do configure the chip selects to output
on PB[O:3], we must add 8 product terms to
the 10 used in calculating the base power
number. Using the current per product term
of 380J,JA provided earlier, eight additional
product terms result in an additional 3.0 rnA
of current.
Experimental data has shown that
accessing the SRAM results in an
additional current expense of 31 rnA above
the base current. Also, accessing the
EPROM draws an additional 0.5 rnA over
the base current. The standby current has
been measured at 50 J,JA. Finally, we must
consider the additional current used by the
frequency of operation. This is 3 rnA per
1 MHz for a total of 6 rnA, since the
PSD3XX will be operating at 2 MHz. This
provides us with all of the data that we
need to calculate the total power usage of
the PSD3XX in this system.
Table 2 can be used to calculate the
EPROM access current, the SRAM access
current and the standby current.
Current Used
PSD3XX Block
Base Configuration
16mA
PAD (as configured)
3.0 rnA
EPROM
SRAM
Frequency Component
Standby Current
0.5 rnA
31mA
6mA
50 J,JA
Now, summarizing further, the total
EPROM access current is:
Base Current + PAD Current + EPROM
Current + Frequency Component
= 16 rnA + 3.0 rnA + 0.5 rnA + 6 rnA
= 25,5 rnA
May, 1993
as logic inputs (A16, A17 and A18) and
therefore cannot be used as chip selects.
Since the rest of the Port pins are not used
as PAD outputs, the MAPLE software will
automatically program them out.
410
The total SRAM access current is:
Base Current + PAD Current + SRAM
Current + Frequency Component
= 16 rnA + 3.0 rnA + 31 rnA + 6 rnA
= 56,QrnA
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
Summing
It All Up
(Cont.}
Now we must account for the duty cycle of
the system to determine the total average
power for the PSD3XX. In order to apply
the duty cycle, we simply multiply each
power component by its duty cycle and add
them all together. The equation to perform
this is given below:
Total Current
+ 0.1 (isRAM)
= 0.6(iSBY) + 0.3(iEPROM)
where iSBY is the standby current, iEPROM is
the active EPROM current and is RAM is the
active SRAM current. Plugging in the
numbers we developed earlier, the equation
becomes:
The average current drawn by the PSD3XX
under the specified conditions of
configuration, frequency and environment
is therefore 13.3 rnA. The peak typical
current used by the PSD3XX is 54 mA
while the SRAM is being accessed. The
minimum current is 50 J.LA, drawn by the
PSD3XX while it is in the Power Down
mode. This compares very favorably with
the typical current usage of a fully discrete
solution.
Total Current = 0.6 (50 J.lA) + 0.3
(25.5 mA) + 0.1 (56.0 mA) = 13.3 mA
Typical VB.
Maximum
Current
The typical and maximum current numbers
are both specified by most integrated circuit
manufacturers. Many designers are unsure
of what these parameters are and how they
relate to the power which will actually be
dissipated by the system. This is
compounded by the configurability of the
PSD3XX.
The maximum power numbers published in
most product specifications are usually
chosen as the number which will never be
exceeded by the device under any
circumstances, including variations in
processing, Vee and temperature. To truly
be a maximum number, all three of these
parameters must be at their worst cases
simultaneously, which is quite unlikely.
Therefore, power use will more likely follow
the typical values when the system is
actually running.
In the PSD3XX data sheet published by
WSI, two current values are published for
typical conditions and another two are
published for worst case conditions. These
two sets of numbers are used to specify
current use in two different PSD3XX
configurations. The lower numbers
represent the current drawn by the
PSD3XX while configured with 10 active
product terms. To arrive at the maximum
value for this configuration, we assume that
the programming of the device has not
changed, but we take the temperature,
voltage and processing to their worst case
May, 1993
411
conditions. These numbers are generated
again for the configuration of the PSD3XX
which has all 40 product terms active. To
determine the typical current drawn by the
PSD3XX in your system, it is best to use
the techniques presented in this application
note. All of the typical current values used
in this note are the result of careful experimentation, and should parallel very closely
the values measured in your own system.
To extrapolate the worst case current for
your configuration from your calculated
typical value, you must add about 50% to
account for voltage, temperature and
process variation.
When calculating the worst case current for
your entire system it is usually best to use
the typical current numbers for all of the
components installed and then apply some
margin to allow for worst case conditions.
This is much more accurate than using the
worst case parameters for each
component since it is extremely unlikely
that all of the components used are
simultaneously at their worst case process
parameters, though they may all be at
worst case voltage and temperature.
Usually 20% margin above the typical
numbers will sufficiently cover the worst
case for the entire system.
Table 3 summarizes the typical current
numbers for the PSD3XX which can be
used when calculating the current used in
your own system.
Philips Semiconductors Microcontroller Peripherals
Application Note 016
Power considerations in the PSD3XX
PSD3XX
Tab183.
Summary
0'
PSD3XX
Typical
CU"8Rt
Usag8
Base Current (10 product terms, SRAM and EPROM Unselected)
Additional Current per Product Term
Additional Current for SRAM Access
31mA
Additional Current for EPROM Access
0.5mA
Additional Current for Frequency Effects
Additional Current for Voltage> 5V
May. 1993
3 mA/MHz
0.85 mA/0.1V
50~
Standby Current
CORcluslOR
16mA
0.38 mA
The PSD3XX is a very important device in
the design of compact, low-power systems.
It provides a cost effective minimum part
count solution for a typical microcontroller
system. It also provides a very low power
solution for those designs which are
handheld and/or battery operated. As the
PSD3XX family grows and evolves, more
412
innovations will be presented in terms of
integratian and power usage. The new low
power PSD3XX family will be introduced
soon, providing the designer with an even
lower power solution. Until then, use of the
techniques described in this note will
provide a minimum power solution for your
microcontroller system.
Philips Semiconductors Microcontroller Peripherals
Security of Design in the PSD3XX
Application Note 018
PSD3XX
By Oudi Moran - WSI
Introduction
The PSD3XX is a family of field programmable and UV erasable microcontroller
peripherals that have the ability to interface
to virtually any microcontroller without the
need for external glue logic.
Any PSD3XX family member is a complete
microcontroller peripheral solution with
Memory (EPROM, SRAM), Logic, I/O Ports
and a Security bit on chip.
In today's competitive business environment, where the cost of the product and its
quick introduction to market are the most
important factors for success, some
companies tend to copy a competitor's
design. By doing so, they can save
development time which can reduce their
engineering cost and eventually reduce the
product's price and its introduction time to
the market.
USBofthB
SBcurity Bit
Obviously, it is an undesirable situation for
the EPROM, PAD and configuration data of
the PSD3XX to fall into the hands of a
competitor. To prevent this, the PSD3XX
device implements a security "fuse" or
programmable bit feature to protect its
contents from unauthorized access and use
by a competitor.
Uploading the programmed data from
EPROM, PAD, ACR and NVM port configuration sections of a secured PSD3XX
device is disabled by the security bit
(if turned ON). The RAM of the programmer
(after trying to upload a secured PSD3XX
device) will contain invalid random data.
This is true mainly for the consumer and
commodity product markets where microcontrollers are widely used. The PSD3XX,
as the primary microcontroller peripheral,
contains all the important code and
architectural data that a potential competitor
may want to copy.
A securedPSD3XX device will function
properly in the system - the microcontroller
will be able to access the EPROM, SRAM,
PAD and the I/O ports but any attempt to
read or verify the contents of a secured
PSD3XX by external hardware will fail.
PSD3XX devices contain non-volatile
configuration bits to enable the user to set
and configure the device to the proper
operational mode. The configuration bits will
configure the device to interface successfully with the microcontroller and also
configure the PSD3XX I/O Ports. The
configuration bits are programmed during
the programming phase and cannot be
accessed in operational mode.
2) The NVM section of the PSD3XX device
contains port configuration bits for proper
set up of Ports A, B and C.
During programming the configuration bits
are programmed as two separate sections:
All ACR and NVM configuration bits of the
PSD3XX are non-volatile, so their contents
will not be erased or corrupted during the
power down mode of the device (when the
PSD3XX is deselected with CSI/A19 =
High) or during power down when Vcc is
removed.
1) The ACR section of the PSD3XX device
contains global configuration bits for
proper microcontroller interface. The
security bit resides as an individual
configuration bit in the ACR section of
the device.
MaY,1993
Since the PSD3XX is a field programmable
device, its contents may be read by an I.C.
programmer, decompiled and copied by a
competitor.
413
PSD3XX devices use the security bit to
prevent unauthorized access to the
configuration data inside. Since the security
bit is part of the ACR global configuration
bits section, it can be programmed in the
same manner as all other configuration bits.
Philips Semiconductors Microcontroller Peripherals
Application Note 018
PSD3XX
Security of Design in the PSD3XX
By Oudi Moran - WSI
U$Bofthe
Security Bit
(Cont.)
The security configuration bit is user
programmable and UV erasable as well, so
a secured part can be erased completely
and be reprogrammed (only if the device is
in a windowed package).
Setting the security bit will lock all the
contents of the PAD, ACR global configuration bits, and NVM port configuration
bits. By setting the security bit the device
cannot be entered into Initialization and
Override mode (resets the device and
enters it to a known'default configuration
before activating the individual read mode
for each section). Any attempt afterwards to
enter the device to DIRECT mode for
uploading or programming will fail. Setting
the security bit prevents a programmer from
directly accessing the various sections of
the device.
setting the security bit, it is impossible to
read them by using external equipment
(except by the microcontroller in the system
where the PSD3XX designed in). This is
because the external equipment will lack
information about the address mapping of
the eight EPROM blocks, SRAM and I/O
ports in the memory map of the
microcontroller and the unknown status of
the global and I/O port configuration bits.
Even if an unauthorized user figures out the
configuration of the part by knowing what
microcontroller is interfaced (ALE polarity,
what type of read and write Signals, etc.)
and gets data out of the PSD3XX (after
applying address and control signals to the
device), the user will have no idea where it
came from: EPROM, SRAM, I/O Port
Register, Page Register, etc. This
effectively renders the data useless.
Even though the EPROM, SRAM and I/O
port contents are not directly disabled by
Setting the
Security Bit
The security configuration bit is called
CSECURITY.
If CSECURITY = 0, it means security is off
(security bit is not set and its value will be '1'
in the object file).
If CSECURITY =1, it means security is on
(security bit is set and its value will be '0' in
the object file).
Setting the security bit and activating the
security mode can be done in two different
ways:
1) By turning security ON in the configuration menu of Maple development
software.
2) By setting the security in the
programming software (done after the
device is fully programmed and verified).
Using Maple development software to turn
security ON gives the security bit the value
'0', and will integrate it in one of the ACR
May. 1993
414
addresses of the object file created after
compilation. (See Security Bit File Location
section of this document).
If Setting of the security bit is done in the
programming software (Third party programming software or WSI Mappro
programming software), the user should
program and verify the device using a
Maple generated object file (with security
option OFF) and then set the security ON by
using a separate programming software
command.
Some third party programmer manufacturer's software will load the Maple
generated object file but mask the security
bit before programming the device. In that
case the user will have to set the security
bit Of necessary) by using a separate
command in the programming software
menu.
Philips Semiconductors Microcontroller Peripherals
Application Note 018
Security of Design in the PSD3XX
PSD3XX
By Oudi Moran - WSI
Security
Bit File
Location
The object file created by compilation with
Maple software is an Intellntelec format,
compatible file.
The programming algorithm defines the
address scrambling that translates the file
addresses to device addresses (the address
that the device "sees" on its address pins
during programming). By looking at a
screen dump or a hard copy of the object
file the user can determine the status of the
security bit.
The security bit of the PSD301/311 resides
in data bit #1 of file address 81 D3h. This
address contains three configuration bits
that reside in data bits 0 - 2, so this address
in the file can have any value between 0
and 7.
If this address has a value X1X (where X
can be either 0 or 1), the security bit is off
('1' value means an unprogrammed bit) and
CSECURITY =0 (displayed by Mappro WSI
programmer interface software as
SECA =0).
If this address has a value XOX, the security
bit is on and CSECURITY = 1 (displayed
Summary
May, 1993
The PSD3XX family of programmable
microcontroller peripheral devices provides
security of design not readily available in
conventional PLDs and EPROMs.
415
by Mappro WSI programmer interface
software as SECA = 1).
The security bit of PSD302/312 resides in
data bit #1 of file address 10253h. This
address contains three configuration bits
that reside in data bits 0 - 3 (bit 3 is
reseNed for future usage). This address
can have any value between 0 and F. If this
address has a value XX1X (where X can be
either 0 or 1), the security bit is OFF
( '1' value means an unprogrammed bit) and
CSECURITY = 0 (displayed by Mappro WSI
programmer interface software as SECA =
0). If this address has a value XXOX, the
security bit is ON and CSECURITY = 1
(displayed by Mappro WSI programmer
interface software as SECA = 1).
If users do not want to look for the security
bit status in the object file, they can call
MAPPRO programming software from the
main menu of MAPLE, Load the RAM with
the object file and Display the ACR
configuration bits status on the screen.
The value of SECA will indicate the status of
the security bit (SECA = 0 means security is
OFF, SECA = 1 means security is ON).
Though not entirely fool-proof, the security
bit feature helps make it more cost effective
for competitors to design their own
hardware instead of trying to copy systems
that already exist.
Philips Semiconductors Mlcrocontroller Peripherals
Application Note 019
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process By Timothy E. Dunavin, Antec - Anixter Mfg. and Karen S. Spesard, WSI
Abstract
With the ever increasing complexity of
wiring networks and cables to match a wide
variety of computer and telecommunication
systems, a means of testing them becomes
a necessity. The wire tester design
described below is a simple yet effective
design which uses the Motorola 68HC11
and WSI PSD311 pairto create a system
that insures 8-wire cables are wired
properly, and at the same time offers a
substantial increase in design flexibility
over alternative hardware solutions.
Introduction
More and more microcontroller and
microprocessor designers are trying to
design integrated core-based systems with
the intention of being able to easily
configure their systems to fit a wide variety
of product applications. The problem is that
when these applications require new or
changing features such as expanding I/0s
or address maps, they may find their
designs are not flexible enough to
accommodate the new requirements,
forcing a lengthy and expensive redesign
anyway.
can be re-configured for other applications
using the same core design. Also, the
PSD3XX product family can enhance
microcontroller-based systems in other
ways. For instance, it can improve system
integration resulting in lower system costs,
and it can significantly shorten time to
market resulting in increased revenues and
profits.
A solution to this problem is to deSign in
user-configurable programmable peripheral
products which are flexible enough to
accommodate future design revisions
without the need for board relayout. The
PSD3XX family from WSI, Inc., fits this
profile exactly in that the products can be
tailored to a specific application and then
The Cable
Tester System
Design
The cable tester described below operates
by sending a known bit pattern through the
cable under test and checking the bit
pattern at the other end. The hardware
configuration utilized to achieve this
function is shown in Figure 1.
Note that there are very few components
overall in the design. The core contains
just the 68HC11 microcontroller from
Motorola, the PSD311 Programmable
Peripheral with Memory from WSI
and a few other key components including
a keypad, LCD display, and an optional
RS232 communications device.
May. 1993
417
In the cable tester system in which the
PSD311 was used with the 68HC11, the
PSD311 integrates address decoding,
latches, 32K x 8 EPROM, and2K x 8
SRAM all into a one-chip user-configurable
microcontroller peripheral. It also replaces
the two ports lost by the 68HC11 to extend
program and data memory outside the
MCU with two additional configurable 8-bit
1/0 ports, and adds a third 3-bit port, while
easily enabling still further port expansion.
Also note that the interconnections
between the 68HC11 and PSD311 are
direct and require no "glue logic". That
means that no external latches are needed
to demultiplex the multiplexed address and
data bus from the 68HC11. And, no other
external logiC is needed to generate the
address mapping for the on-board EPROM
and SRAM and to select external
peripherals, or create the control signal
interface. The PSD311 already
incorporates these features internally,
thereby simplifying the design considerably. In fact, the PSD311's architecture, as
shown in Figure 2, specifically includes
32K x 8 mappable EPROM for program
3:
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Philips Semiconductors Microcontroller Peripherals
Application Note 019
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Interfacing
To The 'S0311
(C t )
Dn •
The PAD enables the 8 blocks of 4K bytes
EPROM (256K bits) to be located
anywhere within the available address
space - in this case, the address space of
the 68HC11 is 64K bytes. So, the EPROM
memory is split into two segments of 16K
bytes EPROM each, separated by the 512
bytes of the internal E2PROM on the
68HC11. This means that the first 4
EPROM blocks are mapped contiguously,
as well as the last 4 EPROM blocks.
Here,the program memory (6000H-9FFFH:
EPROM2, and COOOH-FFFFH: EPROM1)
is allocated to the upper portion of address
space.
The data or SRAM memory, on the other
hand, is allocated to the lower portion of
Benefits
of the 'S0311
Usage In
System
Board layout of the cable tester design was
greatly simplified with the PSD311. In fact,
when pin 1 of the PSD311 is oriented 180
degrees from pin 1 of the 68HC11 in the
PLCC package, port B of the 68HC11 is
directly across from the AD8-AD15 pins of
the PSD311. This positioning enables close
layout of the two parts, greatly reducing
costs due to less board space.
Additional space is saved by using the latch
and buffer for general-purpose I/O instead
of the larger and more expensive PIA. And
other I/O port lines are not sacrificed by
using the multiplexed address/data bus
instead of the Serial Peripheral Interface of
the 68HC11.
In fact, board space is estimated to have
been reduced by more than 50% over the
alternative cumbersome design because of
the PSD311 positioning on the PC board,
its port expansion capabilities, and of
course, the number of parts it replaces:
including a 256K EPROM, a 16K SRAM, a
latch, a decoder, and other miscellaneous
CMOS logic.
A benefit of parts reduction is lower CMOS
power consumption that results from an
integrated single-chip CMOS peripherall
memory solution. By analyzing the power
that would have been consumed with the
alternative design and comparing that
against the PSD311 solution, it was found
May, 1993
422
address space and is partitioned into
two segments: one segment containing the
SRAM internal to the 68HC11 (256 bytes)
and the other containing the SRAM
internal to the PSD311 (2K bytes). The
SRAM in the PSD311 is mapped via the
address decoder to location 5000H-5FFFH,
respectively.
Data direction and data registers of the
PSD311's two ports are paired and
accessed via an offset from a configurable
I/O port mapped base address, such as
4000H in this cable tester design. This
enables 16-bit data instructions to access
the two I/O ports together, which in turn
reduces both the Load and Store times
during program execution.
that power was reduced by at least 30%.
This translates into requiring a smaller
power supply and a further reduction in cost.
The flexibility of the PSD311 in the cable
tester design is also an advantage when
design changes need to be made quickly.
Since the 110 ports, PAD, control signals,
and EPROM are all programmable, the part
just needs to be reprogrammed when the
configuration or program memory for the
entire system needs modifying.
For instance, the current system has ten
I/O, eleven input, and eleven output lines
remaining. This can change if other
variables need to be stored or other
peripherals need to be accessed. To
avoid relaying out another board to
accommodate these changes, the PSD311
may be able to be reconfigured to easily
handle them. Also, if more features and/or
capabilities in EPROM are required, the
PSD312 and PSD313 with 512Kbits (64K x
8) and 1Mbits (128K x 8) EPROM, respectively, are available in the same package
and pinout.
The PSD311 also provides additional SRAM
beyond the limited amount that may be on
the microcontroller being used.
This provides obvious benefits including
more scratchpad RAM for such uses as
storing cable "signatures" and system tests
that can be downloaded for diagnostic
purposes.
Philips Semiconductors Microcontroller Peripherals
Application Note 019
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Benefits
of the PSD311
Usage In
System
(Cont.)
But other benefits not readily seen are also
important. For product designs that have a
short life cycle and are ''pushed'' to go to
market quickly, the additional SRAM gives
the designer the option of writing the code
in a high-level language such as "C",
without the worry of running out of variable
storage space. The capability of writing
software in "C" could speed up the software
development cycle, thereby reducing timeto-market!
Configuring and
Programming
thePSD311
All of the control logic, address mapping,
and port configurations for the PSD311 are
handled during device configuration as part
of WSl's easy-to-use, menu-driven PSD
MAPLE software program, which is
included in the PSD-SILVER or PSD-GOLD
software development package. See
Appendix A for the PSD311 configuration
used in this application.
"Compile". "Compile" reads the code written
for the microcontroller (in Intel hex format)
and concatenates or merges it with the
PSD311 configuration data to produce the
desired output file for downloading to a
programmer for programming.
After the configuration for the PSD311 has
been determined and "Save"d, the hex file
that is needed for programming the
PSD311 is created. That is done during
The 68HC11/
PSD311 System
Software
The software for the 68HC11 was written
with a word processor and assembled using
a cross assembler. A portion of the cable
tester design code which is programmed
into the PSD311 is listed in Appendix B.
Here the register and RAM memory locations are set up within the first 64 clock
cycles from reset of the 68HC11 and
located at OOOOH to enable easy Direct
Addressing and Bit manipulations of often
used registers.
Initialization of the Option Register,
Timer prescaler, Stack and Serial
Communications Interface complete the
basic set up for the 68HC11 operation.
Other initialization operations include: Ports
A and B of the PSD311 which are set up as
outputs for display control and data transfer
operations, and the LCD display which is
set up to display the first screen. Final
initialization is achieved by setting several
internal registers and clearing any
pending interrupts. Now, the IRQ mask bit
can be cleared and the main program loop
entered.
May, 1993
423
That is all there is to programming the
PSD311 which is now supported on
industry-standard programmers like the
Data 110, BP Microsystems, Bytek, and
Logical Devices programmers as well as
the low-cost WSI MagicPro programmer.
Included in the code is a demonstration of
some useful routines which will illustrate
how to easily work with the Latch and
Buffer expansion from the 68HC11/
PSD311. Remember that these extended
addresses off the 68HC11 can be accessed
in several ways. The example code shown
uses the Bit Set and Bit Clear instructions
in the indexed addressing mode. With
these Bit Set and Bit Clear instructions,
which are read-modify-write instructions, an
additional register should be set up in the
internal RAM, not on the latched (writeonly) address, so the
instructions will function properly. Data can
then be manipulated and stored as a
complete byte to the latch enabling data to
be read and the current value in the latch to
be checked. (Bit manipulation on the
latched addresses using the indexed
addressing mode will result in a correct
bit change. However, the rest of the byte
will be unusable as data on the bus will be
scrambled at the rising edge of the chip
select signal.) The latch and buffer
expansion keeps software algorithms
simple.
Philips Semiconductors Microcontroller Peripherals
Application Note 019
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
The6BHC11/
PSD311 System
Software
(Cont.)
Regarding the software for the keypad, no
debounce software is necessary because
the 74C922 has a built in debounce circuit.
Actually, direct access from Port E to the
keypad data and the AND instruction allows
easy compare and execution of the correct
routine.
The remaining subroutines in the program
are straightforward and basic to most
microcontrollers and microprocessors.
Those used by the 68HC11 are found in
previously published handbooks and
articles which can be obtained through
your local Motorola sales office.
Putting the
System to
Work
The 68HC11/PSD311 cable tester design
could be expanded very easily with
software to learn many different wiring
configurations and to check several cables
against a good one. Its usefulness can also
be increased by making it battery operated
for field use because of the low current
draw of the tester.
The cable tester, as deSigned, will display
the test results and step through the
program to show the pin by pin connections
of the cable. Results are then stored and
later fed into a computer through the
RS232 communications port of the tester.
Summary
Requirements for microcontroller-based
designs are continually changing and to be
able to adapt to these changes means
being flexible. Of course, flexibility in
hardware is sometimes hard to achieve,
while flexibility in software is mostly a
given. One of the goals of the PSD3XX
family of products is to bridge the gap in
flexibility between hardware and software.
a user-configurable peripheral solution for
hardware designers. So, if an application is
modified and the I/O configuration
changes, or design fixes are required, the
P.C. board does not have to be
re-engineered. The PSD3XX can just be
reprogrammed to reflect the new changes.
By that, it is meant that hardware will not be
a gating item when developing a new
design that needs to be introduced to
market quickly. And the PSD311, as
illustrated in this cable tester deSign,
addresses that issue perfectly by providing
May, 1993
424
The flexibility provided by the PSD311
solution in this design is crucial in that it
enabled development to be completed
quickly and successfully using a "core"
approach which can handle many different
cable applications, including applications
for telephone interconnections, printers,
and local area networks.
Philips Semiconductors Microcontroller Peripherals
Application Note 019
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Appendix A. PSOa11 Part Configuration
Listed In .SV1 File
ALIASES
A16/csa
Al7/cS9
Ala/CSlO
A19/CSI
csa
IRQ
DA
CSI
*********************************************************************
GLOBAL CONFIGURATION
Address/Data Mode:
Data Bus Size:
CSI/Al9:
Reset Polarity:
ALE Polarity:
MX
a
CSI
LO
HI
WRD /RWE :
RWE
A16-Al9 Transparent or Latched by ALE:
T
Using different READ strobes for SRAM and EPROM: N
*********************************************************************
Bit No.
o
1
2
3
4
5
6
7
PORT A CONFIGURATION (Address/IO)
Ai/IO.
CMOS/OD.
IO
CMOS
IO
CMOS
IO
CMOS
IO
CMOS
IO
CMOS
IO
CMOS
IO
CMOS
IO
CMOS
*********************************************************************
PORT B CONFIGURATION
Bit No.
0
1
CS/IO.
IO
IO
IO
IO
IO
IO
IO
CS7
2
3
4
5
6
7
CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CHIP SELECT EQUATIONS
ICS7 = /AlS
+
*
/Al4
*
Al3
*
/A12
*
E
*
R/W
*********************************************************************
PORT C CONFIGURATION
Bit No.
CS/Ai.
csa
CS9
Ala
o
1
2
CHIP SELECT EQUATIONS
/CSS
/IRQ
=
/A1S
= DA
*
/A14
*
A13
*
/A12
*
E
* /
R/W
*********************************************************************
ADDRESS
ESO
ESI
May. 1993
A A
19 18
N 'X
N X
MAP
A A A A A A A
17 16 15 14 13 12 11
N N 0 1 1 0 N
N N 0 1 1 1 N
SEGMT
STRT
6000
7000
SEGMT
STOP
6FFF
7FFF
425
EPROM
START
6000
EPROM
STOP
6fff
File Name
BASE30l.0BJ
Application Note 019
Philips Semiconductors Microcontroller Peripherals
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Appendix A. PSD311 Part Configuration
Listed In .SV1 File (Cont.)
ES2
N
X
N
N
1
0
0
0
N
8000
8FFF
ES3
N
X
N
N
1
0
0
1
N
9000
9FFF
ES4
ES5
ES6
ES7
RSO
N
N
N
N
N
X
X
X
X
X
N
N
N
N
N
N
N
N
N
N
1
1
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
1
1
N
N
N
N
0
cooo
0000
EOOO
FOOO
5000
CFFF
OFFF
EFFF
FFFF
57FF
CSP
N
X
N
N
0
1
0
0
0
4000
47FF
1
cooo
dOOO
eOOO
fOOO
cfff
dfff
efff
ffff
BASE301.0BJ
BASE301.0BJ
BASE301.0BJ
BASE301.0BJ
****************************** END ***********************************
CDATA
0
CADDRDAT
1
CRRWR
= 1
CA19/ (lCSI)
0
CALE
=0
CRESET
=0
COMB/SEP
0
CADDHLT
=0
CPAF2
0
CPAFl
CPAFl
CPAFl
CPAFl
CPAFl
CPAFl
CPAFl
CPAFl
[1 ]
[2 ]
[3 ]
[4 ]
[5]
[6]
[7]
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOO
CPACOD
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
0
0
0
0
0
0
0
0
[0 ]
[1]
[2 ]
[3 )
[4 ]
[5]
[6 ]
[7 ]
[ 0]
[1 ]
[2 ]
[3 ]
[4 ]
[5]
[6]
[7]
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOO
CPBCOO
CPBCOD
1
1
1
1
1
1
1
0
[ 0]
0
[1 ]
0
0
[2 )
[3]
0
[4 ]
0
0
0
0
[5]
[6 ]
[7 ]
CPCF [ 0]
CPCF [1]
CPCF [2 ]
May, 1993
0
0
0
0
0
0
0
0
[0]
1
1
0
426
Philips Semiconductors Microcontroller Peripherals
Application Note 019
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Appendix B. Core System Software for
Cable Tester Design
0000
0000
CPU
HOF
"68ll.TBL"
"INT8"
;
;**********************************************************
,.*
THE 68HCll IN CONJUNCTION WITH THE PSD301
*
;*
,.*
,• *
;*
,· *
;*
,.*
;*
;*
;*
,· *
;*
,· *
ARE USED IN DEVELOPEMENT OF SOFTWARE FOR
DISPLAY, KEYBOARD FUNCTION, AND OTHER APPL.
MEMORY MAP:EPROM(l)
COOO-FFFF (PROGRAM)
EEPROM
B600-BFFF (68HCll)
EPROM(2)
6000-~FFF (DATA)
RAM
5000-5FFF (PSD30l)
I/O
4000-4007 (PSD30l)
LAT
2000
(LATCH & BUFFER)
RAM
1000-10FF (68HCll)
I/O & REG 0000-003F (68HCll)
BY TIM DUNAVIN
ANTEC
*
*
*
*
*
*
*
*
*
*
*
*
*
,.*
ANIXTER MANUFACTURING
*
;**********************************************************
6000
ORG
06000H
;DATA MEMORY
;
i***********************
i*
LOOKUP TABLES
*
;***********************
i
6000 36384843310ATTAB:
OFB
"68HCll/PS031l UP",OOH
;
6011 54494D4F54CREDITS: OFB
6023 4l4E544543
DFB
6037 524F434B20
OFB
"TIMOTHY E. OUNAVIN"
"ANTEC - ANIXTER MFG."
"ROCK FALLS, ILL. 61071"
i***************************************************** **
COOO
1030
4000
2000
0000 =
0001 =
0002
0003
0004
0005
0006
0007
0008
0009
OOOA
OOOB
OOOC
0000
OOOE
OOOF
May, 1993
;
INIT:
PORTBC:
LAT:
KEY1:
KEY2:
KEY3:
KEYA:
KEY4:
KEYS:
KEY6:
KEYB:
KEY7:
KEYS:
KEY9:
KEYC:
KEYZ:
KEYO:
KEYY:
KEYO:
ORG
OCOOOH
; PROGRAM MEMORY
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
103DH
04000H
02000H
OOH
OlH
02H
03H
04H
05H
06H
07H
08H
09H
OAH
OBH
OCH
ODH
OEH
OFH
;RAM AND·I/O MAPPING REGISTER
;I/O BASE ADDRESS OF THE 301
;LATCH AND BUFFER
;KEYPAD 1
;KEYPAD 2
;KEYPAD 3
;KEYPAD A
;KEYPAD 4
;KEYPAD 5
;KEYPAD 6
;KEYPAD B
;KEYPAD 7
;KEYPAD 8
;KEYPAD 9
;KEYPAD C
iKEYPAD *
; KEYPAD 0
; KEYPAD #
iKEYPAD 0
427
Application Note 019
Philips Semiconductors Microcontroller Peripherals
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Appendix B. COle System Softwale fOI
Cable Testel Design (Cont.)
;************************************************
;*
INITIALIZATION ROUTINE
*
i************************************************
COOO OF
COOl 8610
C003 B7103D
;
;NOTE: OPTION and TMSK2 must
cycles out of RESET
;
START:
SEI
LDAA
#010H
STAA
INIT
be programed in first 64 E
;SET IRQ MASK
;SET RAM AT 1000 AND
iSET REGISTERS AT 0000
i************************************************
i
;******* 64 BYTES OF REGISTER AREA *******
0000
PORTA:
;
PIOC:
PORTC:
PORTB:
PORTCL:
EQU
OOOOH
EQU
EQU
EQU
EQU
0002H
0003H
0004H
0005H
DDRC:
PORTO:
DDRD:
PORTE:
CFORC:
OCIM:
OC1D:
TCNT:
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
0007H
0008H
0009H
OOOAH
OOOBH
OOOCH
OOODH
OOOEH
0010
TIC1 :
EQU
0010H
0012
TIC2:
EQU
0012H
0014
TIC3:
EQU
0014H
0016
TOC1 :
EQU
0016H
0018
TOC2:
EQU
0018H
TOC3:
EQU
001AH
001C
TOC4:
EQU
00lCH
001E
TOC5:
EQU
001EH
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A
002B
002C
0020
002E
002F
TCTL1
TCTL2
TMSK1
TFLG1
TMSK2
TFLG2
PACTL
PAC NT
SPCR:
SPSR:
SPDR:
BAUD:
SCCR1:
SCCR2:
SCSR:
SCDR:
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
0020H
0021H
0022H
0023H
0024H
0025H
0026H
0027H
0028H
0029H
002AH
002BH
002CH
002DH
002EH
002FH
0002
0003
0004
0005
0007
0008
0009
OOOA
OOOB
OOOC
0000
OOOE
001A
=
=
=
=
=
=
=
May, 1993
;PORT A DATA REGISTER
;0001 IS RESERVED
;PARALLEL I/O CON~ROL REGISTER
;PORT C DATA REGISTER (ADO - AD7)
iPORT B DATA REGISTER (A8 - A1S)
;PORT C LATCHED DATA REGISTER
;0006 IS RESERVED
;DATA DIRECTION REG FOR PORT C
;PORT 0 DATA REGISTER (RxD, TxD, AND I/O)
;DATA DIRECTION REG FOR PORT 0
;PORT E DATA REGISTER
;TlMER COMPARE FORCE REGISTER
;OUTPUT COMPARE 1 MASK REGISTER
;OUTPUT COMPARE 1 DATA REGISTER
iTlMER COUNTER REGISTER (16 BIT)
iOOOF LSB TCNT
;TIMER INPUT CAPTURE REGISTER 1 (16 BIT)
; 0011 LSB TIC1
;TIMER INPUT CAPTURE REGISTER 2 (16 BIT)
; 0-013 LSB TIC2
;TIMER INPUT CAPTURE REGISTER 3 (16 BIT)
;0015 LSB TIC3
iTIMER OUTPUT COMPARE REG 1 (16 BIT)
; 00.17 LSB TOC1
iTIMER OUTPUT COMPARE REG 2 (16 BIT)
;0019 LSB TOC2
; TIMER OUTPUT COMPARE REG 3 (16 BIT)
;001B LSB TOC3
iTIMER OUTPUT COMPARE REG 4 (16 BIT)
;0010 LSB TOC4
i TIMER OUTPUT COMPARE REG 5 / INPUT CAPTURE
iREGISTER 4 (16 BIT) 001F LSB TOC5/TIC4
;TIMER CONTROL REGISTER 1
iTIMER CONTROL REGISTER 2
iMAIN TIMER INT MASK REGISTER 1
; MAIN TIMER INT. FLAG REG 1
;MAIN TIMER INT MASK REGISTER 2
; ~IN TIMER INT. FLAG REG 2
;PULSE ACCUMULATOR CONTROL REG
; PULSE ACCUMULATOR COUNT REG
;SP~ CONTROL REGISTER
;SPI STATUS REGISTER
iSPI DATA REGISTER
iSCI BAUD RATE CONTROL REGISTER
;SCI CONTROL REGISTER 1
;SCI CONTROL REGISTER 2
iSCI STATUS REGISTER
;SCI DATA REGISTER
428
Philips Semiconductors Microcontroller Peripherals
Application Note 019
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Appendix B. Core System Software for
Cable Tester Design (Cont.)
0030
0031
0032
0033
0034
ADCTL:
ADR1:
ADR2:
ADR3:
ADR4:
EQU
EQU
EQU
EQU
EQU
0030H
0031H
0032H
0033H
0034H
0039
003A
003S
003C
OPTION:
COPRST:
PPROG:
HPRIO:
;INIT:
TEST1:
CONFIG:
EQU
EQU
EQU
EQU
EQU
EQU
EQU
0039H
003AH
003BH
003CH
003DH
003EH
003FH
003E
003F
=
;A/D CONTROL/STATUS REGISTER
;A/O RESULT REGISTER 1
;A/D RESULT REGISTER 2
;A/D RESULT REGISTER 3
;A/D RESULT REGISTER 4
i0035 - 0038 RESERVED
iSYSTEM CONFIGURATION OPTIONS
iARM/RESET COP TIMER CIRCUITRY
iEEPROM PROGRAMMING REGISTER
;HIGHEST PRIORITY INTERRUPT
iRAM AND I/O MAPPING REGISTER (NEW ADD.)
;FACTORY TEST REGISTER
;CONFIGURATION CONTROL REGISTER
;
;******* 256 BYTES OF INTERNAL RAM *******
1000
1001
1002
10FF
FLAGS:
LA1:
STOR:
STACK:
EQU
EQU
EQU
EQU
1000H
1001H
l002H
lOFFH
;FLAG REGISTER
iLATCH DATA REGISTER
iBASIC RAM STORAGE AREA
;STACK AREA
;
;******* 2K x 8 EXTERNAL RAM ********
MASSTOR: EQU
05000H
;MASS STORAGE RAM IN PSD301
;
;******* EEROM AREA, 512 BYTES *******
EROM:
EQU
OB600H
;DATA RETENTION AREA
5000
8600
i
COO6 01
C007 86E3
#************************************************
NOP
LDAA
#OE3H
C009 9739
STAA
OPTION
coos
LDAA
#002H
STAA
TMSK2
CLR
SPCR
LDS
#STACK
LDAA
#080H
STAA
PACTL
;PA7 OUTPUT
INITIALIZE THE SCI TO 9600 BAUD AT 8MHZ (DISABLED)
LDAA
#OFCH
;INIT. PORT DOOR (02H)
STAA
DDRD
iPDO, POl - INPUT, PD2-PDS - OUTPUT
LDAA
#OOOH
iSET UP PORT 0
STAA
PORTD
CLR
SCCRl
iSET UP SER. COM. CON. REG. 1
CLR
SCCR2
LDAA
SCSR
; TO CLEAR TDRE AND TC OF SCSR
CLRA
i READ STATUS REG., LOAD TRANS. DATA REG.
STAA
SCDR
INITIALIZE THE 301 FOR DISPLAY INTERFACE
LDX
#OFFFFH
iSET UP PORTS B & C AS OUTPUTS
STX
PORTBC+4
DISPLAY SET UP (NEW REV. 15 MAY 91) *******
LDX
#02710H
;lOOmS DELAY (POWER UP DELAY FOR DISPLAY)
JSR
TDELAY
iTlME DELAY
LDAA
#030H
iSET UP DISPLAY
JSR
SENDI
;SEND INSTRUCTION (30 1ST TIME)
LOX
#00300H
;6.1mS DELAY
COOO
COOF
C012
C015
C017
8602
9724
7F0028
8E10FF
8680
9726
C019
C01S
COlD
C01F
C02l
C024
C027
C029
C02A
86FC
9709
8600
9708
7FOO2C
7F002D
962E
4F
972F
ONSCI:
C02C CEFFFF
C02F FF4004
ONPIA:
C032
C035
C038
C03A
C030
DISINIT:
CE2710
BOCOE1
8630
BOCOF4
CE0300
May, 1993
i*******
i*******
i*******
;SLIGHT DELAY TO ALLOW REGISTER SET UP
;SET UP OPTION REG. - ADPU =1, CSEL = 1,
IRQE = 1
; (ENABLE EEPROM CHARGE PUMP, IRQ EDGE
SENSITIVE)
iSET TIMER PRESCALER TO 8
iAND DISABLE TIMER INTERRUPTS
iDISABLE ALL SPI INT.
;SET UP STACK
429
Application Note 019
Philips Semiconductors Microcontroller Peripherals
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Appendix B. Core System Software for
Cabls Tester Design (Cont.)
C040
C043
C046
C049
C04C
C04F
C051
C054
C057
COSA
COSC
COSF
C062
C06S
C067
C06A
COGD
C070
C073
C076
C079
C07D
BDCOEI
BDCOF4
BDCODE
BDCOF4
BDCODE
8638
BDCOF4
CE0280
BDCOEI
860C
BDCOF4
CE0280
BDCOEI
8606
BDCOF4
CE0280
BDCOEI
BDCOEC
CE0190
BDCOEI
18CE6000
BDCOCC
C080
C082
C084
C086
C088
C08A
C08C
9629
962A
86FF
9723
972S
962E
962F
C08E
C09l
C094
C097
C099
C09C
7F2000
CEIOOI
lC0200
AGOO
872000
B62000
;*******
FINIT:
;TIME DELAY
;SEND INSTRUCTION (30 2ND TIME)
;TIME DELAY
iSEND INSTRUCTION (30 3RD TIME)
;TIME DELAY
;FUNCTION SET (B BIT-SINGLE LINE)
;SEND INSTRUCTION
;5mS DELAY
;TIME DELAY
;DISPLAY ON - NO CURSOR
;SEND INSTRUCTION
iSmS DELAY
;TIME DELAY
;ENTRY MODE SET
;SEND INSTRUCTION
;5mS DELAY
;TIME DELAY
;DISPLAY CURSOR HOME!
;4.0mS DELAY
;TlME DELAY
;TOP OF DATA TABLE
;SEND MESSAGE TO DISPLAY
;CLEAR ANY SPI INT.
;CLgAR ANY TIMER INT.
;CLEAR ANY SCI INT.
;
iEXAMPLES OF WORKING WITH LATCH AND BUFFER
CLR
LAT
; CLEAR LATCH
LOX
#LAI
;SET INDEX
BSET
2,X,OOH
;SET BIT 2 OF LAI
LDAA
O,X
;GET LATCH REGISTER
;STORE DATA TO LATCH
STAA
LAT
;GET DATA FROM BUFFER
LDAA
LAT
C09F BDCOBO
COA2 OE
TDELAY
JSR
JSR
SENDI
JSR
TD40
SENDI
JSR
TD40
JSR
LDAA
#038H
JSR
SEND I
#002BOH
LOX
JSR
TDELAY
#OOCH
LDAA
JSR
SENDI
#002BOH
LOX
JSR
TDELAY
LDAA
#006H
JSR
SENDI
#00280H
LOX
JSR
TDELAY
JSR
HOME
LOX
#00190H
JSR
TDELAY
LOY
#DATTAB
JSR
PDOD
FINAL INIT. *******
LDAA
SPSR
LDAA
SPDR
#OFFH
LDAA
STAA
TFLGI
TFLG2
~TAA
LDAA
SCSR
LDAA
SCDR
JSR
,
;SOUND OFF!
BEEP
; CLEAR IRQ MASK
CLI
;*************************
;*
MAIN LOOP
*
i*************************
COA3 01
COA4 7ECOA3
;
LOOP:
NOP
JMP
LOOP
; RETURN
;
;************************************
;*
SUBROUTINES
*
;************************************
;
COA7
COA9
COAB
COAD
COAF
8655
973A
86AA
973A
39
May, 1993
;******* WATCHDOG SERVICE ROUTINE ******
DOG:
LDAA
STAA
LDAA
STAA
RTS
#055H
COPRST
#OAAH
COPRST
;RESET WATCHDOG TIMER
;RETURN FROM SUB.
430
Philips Semiconductors Microcontroller Peripherals
Application Note 019
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Appendix B. Core System Software for
Cable Tester Design (Cont.)
;
;******* HOOTER OSC. ROUTINE ********
COBO
COB4
COB6
COB8
COBB
COBE
COBF
COCI
COC4
COC7
COC9
COCB
18CE01FF
8640
9700
CE0014
BDCOEI
4F
9700
CE0014
BDCOE1
1809
26E9
39
BEEP:
BEEPl:
COCC
COCF
CODI
COD4
COD6
COD8
18A600
2707
BDClOO
1808
20F4
39
PDOD:
LDY
LDAA
STAA
LDX
JSR
CLRA
STAA
LDX
JSR
DEY
BNE
RTS
#OOlFFH
#040H
PORTA
#00014H
TDELAY
iSET COUNT
iBEEPER ON
iDELAY
iBEEPER OFF
PORTA
#00014H
TDELAY
; DELAY
;COUNT -1
iIF NOT DONE, KEEP GOING
iRETURN FROM SUB.
BEEPI
i******* PUT DATA ON DISPLAY ********
PDODI:
LDAA
BEQ
JSR
INY
BRA
RTS
O,Y
PDODl
SENDD
iGET BYTE
iIF END, GOTO NEXTl
PDOD
iNEXT BYTE
iRETURN TO NEXT
;RETURN FROM SUB.
i
COD9
CODC
CODE
COE1
COE2
COES
COE7
CE0002
2003
CEOOOF
09
acoooo
26FA
39
;******* TIME DELAY ROUTINE *********
TD20:
TD40:
TDELAY:
LDX
BRA
LOX
DEX
CPX
BNE
RTS
#00002H
TDELAY
#OOOOFH
;20uS DELAY
;lSOuS DELAY
;DECRAMENT COUNT
;COUNT = O?
;IF NOT DONE, GOTO TDELAY
;RETURN FRO SUB.
#OOOOOH'
TDELAY
;
COES
COEA
COEC
COEE
COFO
COF2
COF4
COF7
COF9
COFC
COFF
8601
2008
8602
2004
a6CO
2000
CE4000
A706
1C0702
1D0702
39
i******* CLEAR SCREEN, CURSOR HOME, AND SEND INSTRUCTION *******
CSCREEN: LDAA
#OOlH
;CLEAR DISPLAY
BRA
SENDI
;SEND INSTRUCTION
HOME:
#002H
LDAA
i CURSOR HOME
BRA
SENDI
;SEND INSTRUCTION
LINE2:
LDAA
#OCOH
;SET CURSOR TO LINE 2
BRA
SENDI
;SEND INSTRUCTION
SENDI:
LOX
#PORTBC
;SET UP DATA TRANSFER
STAA
6,X
;STORE AT PIA PORT A
BSET
7,X,02H
iDISPLAY E HIGH
BCLR
7,X,02H
iDISPLAY E LOW
RTS
iRETURN FROM SUB.
i
CIOO
CI03
CIOS
CIOS
C10B
CIOE
Clll
Cll4
CE4000
A706
1C0701
lC0702
1D0702
1D0701
BDCODE
39
i******* SEND DATA TO DISPLAY ********
SENDD:
LOX
STAA
BSET
BSET
BCLR
BCLR
JSR
RTS
#PORTBC
6,X
7,X,OlH
7,X,02H
7,x,02H
7,X,OlH
TD40
iSET UP DATA TRANSFER
;SEND DATA
;DISPLAY RS HIGH
iDISPLAY E HIGH
iDISPLAY E LOW
;DISPLAY RS LOW
;lSOuS TIME DELAY
iRETURN FROM SUB.
******************************************************
*
*
*
*
ROUTINE TO CHANGE BYTE IN EEROM
PRELOADED X = ADDRESS IN EEROM (B600 - B7FF)
DATA TO BE STORED, IS IN "STOR"
(THIS IS A MOTOROLA ROUTINE)
*
*
*
*
******************************************************
May, 1993
431
Philips Semiconductors Microcontroller Peripherals
Application Note 019
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Appendix B. COIS Systsm Softwals fOI
Cabl. Testsl Design (Cont.)
C1l5
C1l7
C1l9
CllB
CllD
CllF
C121
C123
C125
C127
c128
C12B
C12E
C12F
C130
Cl32
C134
C136
C139
C13B
C13E
C13F
C142
C145
C146
C149
Cl4C
A600
81FF
2717
8616
973B
86FF
A700
8617
973B
3C
CE0300
BDCOE1
38
4F
973B
8602
973B
B61002
A700
7C003B
3C
CE0300
BDCOEl
38
7A003B
7F003B
39
CHGBYT:
LDAA
CMPA
BEQ
LDAA
STAA
LDAA
STAA
LDAA
STAA
PSHX
LDX
JSR
PULX
CLRA
STAA
CHGBYT1: LDAA
STAA
LDAA
STAA
INC
PSHX
LDX
JSR
PULX
DEC
CLR
DATA AT ADDRESS TO BE CHANGED
IF ERASED
;JUMP IF BYTE ERASED
;SET BYTE, ERASE, AND EELAT
O,X
#OFFH
CHGBYTl
#016H
PPROG
#OFFH
O,X
#017H
PPROG
~GET
~CHECK
;SET EEPRG
~SAVE
#00300H
TDELAY
X
j20mS TIME DELAY
;RESTORE X
;CLEAR BYTE, ERASE, EELAT, AND EEPRG
~END OF BYTE ERASE
JSET EELAT - DO BYTE PROGRAM
PPROG
#002H
PPROG
STOR
O,X
PPROG
;GET DATA TO BE STORED
iSTORE IN NEW LOCATION IN EEROM
~SAVE
#00300H
TDELAY
X
i20mS DELAY
~RESTORE X
~CLEAR EEPRG
iCLEAR EELAT, END OF BYTE PROGRAM
;RETURN FROM SUB.
PPROG
PPROG
RTS
;
;*****************************************************
;*
ROUTINE TO SET UP AID CONVERTER
*
;*
ACC A = VALUE TO INITIATE CONVERSION
*
;*
BEFORE ENTRY TO THIS ROUTINE
*
C14D 9730
C14F 133080FC
C153 39
~*****************************************************
STAA
ADCTL
~SET UP AID CONVERTER
CONV:
CONV1:
BRCLR
RTS
ADCTL,80H,CONVl ;WAIT HERE TILL CONVERSION COMPLETE
;RETURN FROM SUB.
;
~*************************~**
i
*
INTERRUPT ROUTINES
.
*
j****************************
,
i*************·***************************************
SERIAL COMMUNICATIONS INTERFACE - IRQ
*
j*
j*****************************************************
;
C154 3B
SCOM:
RTI
~RETURN
FROM INT.
;
;******************************
;* SERIAL TRANSFER COMPLETE *
;******************************
j
C155 3B
TRANC:
;RETURN FROM INT.
RTI
;
;*********************************
;* PULSE ACCUMLATOR INPUT EDGE *
;*********************************
;
C156 3B
PULSEE:
;RETURN FROM INT.
RTI
i
;******************************~*
;* PULSE ACCUMULATOR OVERFLOW *
;********************************
May, 1993
432
Philips Semiconductors Microcontroller Peripherals
Application Note 019
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Appendix B. Core System Software for
Cable Tester Design (Cont.)
;
ClS7 3B
PULSEO:
RTI
iRETURN FROM INT.
;
;********************
i*
TIMER OVERFLOW
*
i********************
;
Clsa 3B
TIMEO:
;RETURN FROM INT.
RTI
;
;****************************
;* TIMER OUTPUT COMPARE 5 *
;****************************
;
CIS9 3B
COMPS:
jRETURN FROM INT.
RTI
i***************************
i* TIMER OUTPUT COMPARE 4 *
;***~***********************
ClSA 3B
i
COMP4:
RTI
;RETURN FROM INT.
;
i****************************
i*
TIMER OUTPUT COMPARE 3
*
i****************************
;
ClSB 3B
COMP3:
RTI
;RETURN FROM INT.
i
;**************************~*
i* TIMER OUTPUT COMPARE 2 *
i****************************
ClSC 3B
i
COMP2:
RTI
iRETURN FROM INT.
i
;****************************
;* TIMER OUTPUT COMPARE I *
i****************************
C15D 3B
i
COMPI:
RTI
iRETURN FROM INT.
;
;***************************
i* TIMER INPUT COMPARE 3 *
;***************************
ClSE 3B
i
ICOMP3:
RTI
iRETURN FROM INT.
;
i***************************
; * TIMER INPUT COMPARE 2 *
;***************************
ClSF 3B
i
ICOMP2:
,
RTI
;RETURN FROM INT.
i***************************
i* TIMER INPUT COMPARE 1 *
i***************************
;
C160 3B
ICOMPI:
RTI
iRETURN FROM INT.
i
;****************************
;* REAL TIME INT. ROUTINE *
;****************************
;
C161 3B
May. 1993
REALT:
RTI
433
jRETURN FROM INT.
Application Note 019
Philips Semiconductors Microcontroller Peripherals
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Appendix B. Core System Software for
Cable Tester Design (Cont.)
;**********************
IRQ INT. ROUTINE *
;**********************
,.*
;
C162 960A
C164 840F
DOlT:
C166 8100
C168 2601
C16A 3B
LDAA
ANDA
PORTE
#OOFH
;GET KEYBOARD DATA
;FILTER DATA
CMPA
BNE
RTI
#KEYl
DOIT10
;1 KEY?
;IF NOT GOTO DOIT10
;RETURN FROM INT.
CMPA
BNE
RTI
#KEY2
DOIT20
;2 KEY?
;IF NOT GOTO DOIT20
;RETURN FROM INT.
CMPA
BNE
RTI
#KEY3
DOIT30
;3 KEY?
;IF NOT, GOTO DOIT30
;RETURN FROM INT.
CMPA
BNE
RTI
#KEYA
DOIT40
;A KEY?
;IF NOT GOTO DOIT40
;RETURN FROM INT.
CMPA
BNE
RTI
#KEY4
DOIT50
;4 KEY?
;.IF NOT GOTO DOIT50
;RETURN FROM INT.
CMPA
BNE
RTI
#KEY5
DOIT60
5 KEY?
IF NOT GOTO DOIT60
RETURN FROM INT.
CMPA
BNE
RTI
#KEY6
DOIT70
6 KEY?
IF NOT GOTO DOIT70
RETURN FROM INT.
CMPA
BNE
RTI
#KEYB
DOIT80
B KEY?
IF NOT GOTO DOIT80
RETURN FROM INT.
CMPA
BNE
RTI
#KEY7
DOIT90
7 KEY?
IF NOT GOTO DOIT90
RETURN FROM INT.
;
C16B 8101
Cl60 2601
C16F 3B
DOITIO:
C170 8102
C172 2601
C174 3B
DOIT20:
C175 8103
Cl77 2601
C179 3B
OOIT30:
C17A 8104
el7C 2601
C17E 3B
DOIT40:
C17F 8105
C181 2601
C183 3B
DOIT50:
C184 8106
C186 2601
Clee 3B
DOIT60:
C189 8107
C18B 2601
C18D 3B
DOIT70:
C18E 8108
Cl90 2601
C192 3B
DOIT80:
C193 8109
C195 2601
C197 3B
DOIT90:
CMPA
BNE
RTI
#KEY8
DOIT100
8 KEY?
IF NOT GOTO DOIT100
RETURN FROM INT.
Cl98 810A
C19A 2601
C19C 3B
DOIT100: CMPA
BNE
RTI
#KEY9
DOITllO
9 KEY?
IF NOT GOTO DOIT110
RETURN FROM IN'!'.
C190 810B
C19F 2601
C1Al 3B
OOITllO: CMPA
BNE
RTI
#KEYC
DOIT120
C KEY?
IF NOT GOTO DOIT120
RETURN FROM INT.
C1A2 810C
C1A4 2601
CIA6 3B
DOIT120: CMPA
BNE
RTI
#KEYZ
DOIT130
* KEY?
;
;
;
;
;
;
;
;
;
;
;
May, 1993
434
IF NOT GOTO DOIT130
RETURN FROM INT.
Philips Semiconductors Microcontroller Peripherals
Application Note 019
The PSD311 simplifies an eight wire cable tester design and increases
flexibility in the process
Appendix B. Core System Software for
Cable Tester Design (Cont.)
;
C1A7 810D
C1A9 2601
C1AB 3B
C1AC SlOE
C1AE 2601
C1BO 3B
C1Bl 810F
C1B3 2600
C1BS 3B
CIB6 3B
CIB7 3B
#KEYO
DOIT130: CMPA
;0 KEY?
DOIT140
;IF NOT
BNE
; RETURN
RTI
;
DOIT140:· CMPA
#KEYY
;# KEY?
DOIT1SO
BNE
iIF NOT
RTI
iRETURN
i
DOIT1SO: CMPA
#KEYD
;D KEY?
DOITl60
;IF NOT
BNE
; RETURN
DOIT160: RTI
;
;*******************************
,.* XIRQ SERVICE ROUTINE
*
;*******************************
NOMASK: RTI
;RETURN
;
;*******************************
;* SWI SERVICE ROUTINE
*
;*******************************
INTER:
RTI
;RETURN
GOTO DOIT140
FROM INT.
GOTO DOIT1SO
FROM INT.
GOTO DOITl60
FROM INT.
FROM INT.
FRbM INT.
;
;***********************************
;* RESET AND INTERRUPT VECTORS
*
;***********************************
FFCO
ORG
OFFCOH
;
FFCO
FFD6
FFD8
FFDA
FFDC
FFDE
FFEO
FFE2
FFE4
FFE6
FFE8
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE
C154
C15S
C156
ClS7
C1S8
C1S9
C1SA
C1SB
ClSC
ClSD
ClSE
C1SF
C160
C161
Cl62
ClB6
ClB7
COOO
COOO
COOO
COOO
0000
May, 1993
RES:
DFS
11*2
;NOT USED
SERCOM: DWM
SCOM
;SERIAL COMM. INT.
SPISTC: DWM
TRANC
;SERIAL TRANSFER COMPLETE
PAlE:
DWM
PULSEE
iPULSE ACCUMLATOR INPUT EDGE
PAOV:
DWM
PULSEO
; PULSE ACCUMULATOR OVERFLOW
TOV:
DWM
TlMEO
; TIMER OVERFLOW
TOCPS:
COMPS
DWM
;TlMER OUTPUT COMPARE S
TOCP4:
DWM
COMP4
;TlMER OUTPUT COMPARE 4
TOCP3:
DWM
COMP3
;TlMER OUTPUT COMPARE 3
TOCP2 :
DWM
COMP2
;TlMER OUTPUT COMPARE 2
TOCPl:
DWM
COMPl
;TlMER OUTPUT COMPARE 1
TICP3:
DWM
ICOMP3
;TlMER INPUT COMPARE 3
TICP2:
DWM
ICOMP2
iTlMER INPUT COMPARE 2
TICP1:
ICOMPl
DWM
iTlMER INPUT COMPARE 1
RTlME:
DWM
REALT
; REAL-TIME INT.
IRQ:
DOlT
DWM
iTlMER/VIA INT.
XIRQ:
DWM
NOMASK
;NON-MASKABLE INT.
SWI:
DWM
INTER
;SOFTWARE INT.
rOT:
DWM
START
;ILLEGAL OPCODE TRAP (START OVER)
COPS:
DWM
START
;COP FAILURE (RESET)
COPS1:
DWM
START
;COP CLOCK MONITOR FAIL (RESET)
RESET:
START
DWM
; RESET
;
;************************************************
END
; THE END I I I I I
435
Phlllps Semiconductors Mlcrocontrolier Peripherals
Application Note 020
Benefits of 16-bit design with PSD3XX
PSD3XX
By Ching Lee - WSI
Introduction
ryplca/f6-Blt
Mlcrocontrol/er
System
Architecture
Embedded controller architecture has been
evolving from 4-bit, 8-bit to 16-bit through
the years. The increase in the data bus
bandwidth is a natural progression for
microcontrollers to achieve higher
performance. Today, 16-bit embedded
controllers such as the 80C196 and 683XX
families provide excellent performance at
reasonable cost. Yet many designers are
weary of the cost of higher chip count,
more board space and power consumption
in 16-bit applications and prefer to stay with
a-bit designs. Some microcontroller
manufacturers tackle this problem by
introducing processors with 16-bit internal
architectures but have 8-bit external data
busses. Later additional enhancements
such as dynamic bus sizing provide the
choice of selecting either an 8 or 16-bit bus
for further cost reduction. This compromise
certainly increases the performance; it is
still not as good as a true 16-bit implementation.
There is no one standard 16-bit
architecture, especially in the field of
embedded controller applications. For a
typical80C196 deSign, the basic building
block consists of two address latches
(74AC373), address decoding logic (with
PAL or discrete logiC), program memory
(EPROMs), data memory (one or more
SRAM), and I/O devices.
bus cycle. EPROM accesses are 16-bits
wide, SRAM is 8-bits while I/O bus cycles
can be a or 16-bits, depending on the
device being accessed. The BWIDTH
output from the PAL informs the processor
what type of bus width is to be expected for
that particular cycle.
Figure 1 is the schematic of such a system.
In this deSign, 64K bytes of program
memory/EPROM, and a 2K byte SRAM for
scratch pad are required. Since the
80C196 has only 64K byte memory space,
the INST signal provides the paging
capability, with program memory residing in
the first 64K page while SRAM and I/O
devices occupy the second page. The I/O
section consists of one output port
(74AC374) and other peripheral devices.
The chip select signals for the I/O devices
and memory are connected directly from
the decoding PAL outputs. The processor's
data bus width is determined by the type of
May, 1993
437
With the introduction of the PSD3XX family
of field programmable microcontroller
peripherals from WSI, there is no reason
not to use 16-bit microcontrollers. The
PSD3XX provides an integrated solution in
a single chip, which includes user
configurable I/O ports, Chip Select outputs,
logic replacement, Page Register,
Programmable Address Decoder (PAD),
EPROM and SRAM. The PSD3XX is a
perfect match for 16-bit microcontroller
applications. In this application note, we will
look at some of the advantages of 16-bit
deSigns, and how PSD3XX interfaces to
microcontrollers such as the 80C196 and
68302.
An I/O device usually takes longer time to
complete the bus cycle. Let us assume, in
this case, I/O devices require 3 wait states
with the exception of the I/O latch. The
configuration register of the 80C196 is then
programmed to insert 3 wait states.
Whenever there is an I/O bus cycle, the
READY output signal from the PAL goes
low to activate the processor's wait state
control to insert the programmed amount of
wait state. For memory bus cycles, no wait
state is inserted.
Figure 1. ryplcal16-BIt Mlcrocontroller System Architecture
i
OJ
co
~
1\ A1
us
:::J
~
10 lAO
en
oom
1
00
~:
1
17
~
00
en
en
I
c:
7
C"'
;:::+
~
....
CD
en
~
NMI
14
~6~DY
RESET
-
f:j
:::J
BUSWIDTH
RESET
ACHOIPO.O
ACH1/PO.1
ACH2IPO.2
ACH3/PO.3
ACH4IPO.4
ACH5/PO.5
PCS6IPO.6
PCS7/P0.7
P2.OITXD
P2.1/RXD
P2.21EXINT
P2.3IT2CLK
P2.4IT2RST
P2.51PWM
P2.6/T2UP-DN
P2.7IT2CAP
CD
HSI.O
HSI.1
HSI.21HSO.4
HSI.3/HSO.5
.Jl..
~
VREF
27C256
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A3
A4
A5
".:
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I\'
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A7
A8
A9
A10
A11
A12
A13
A14
lR
01
02 1
03 1
04 1
05 7
06
07
11
111
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==
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(j)
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~~
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U3
ANGND
EA
10
I\.
~
Q.
~
-=
P4.OIAD8
P4.1/AD9
P4.21AD10
P4.3/AD11
P4.4/AD12 _ ........"'-',
P4.5/AD13
P4.6IAD14
P4.7/AD15
RD rJ".",........~
WR
BHE
ALE
INST
CLKOUT ".....,..-='-
3
o
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a.
:
to"
43
CD
0"
a.
MI
en
o
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.....
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Philips Semiconductors Microcontroller Peripherals
Application Note 020
Benefits of 16-bit design with PSD3XX
Typical 16-81t
MlclOcontroller
System
Architecture
(Cont.)
PSD3XX
resides inside the EPROM from
location 1000H to 17FFH. The 2K scratch
RAM and I/O starts from 4000H in the
second page.
Table 1 is the memory address map of the
80C 196 microcontroller, and the addresses
of the I/O devices. Address locations
OOOOH through OOFFH and 1FFEH through
207FH are reserved for the microcontroller.
The remaining locations can be used for
program/data memory or memory mapped
I/O devices. EPROM occupies the first 64K
bytes, where program codes start from
2080H to FFFFH, and a 2K look-up table
EPROMCS
The address map requires the following
PAL equations to be programmed to the
decoder PAL. The 10_CS lines are enabled
after ALE goes low.
INST
+ INST/ * A15/ * A14/
RAMCS
INST/ * A15/ * A14 * A13/ * A121
BWIDTH
RAMCS
+ 10_CSO
+ 10_CS1
+ 10_LAT
READY
10_CSO
+ 10_CS1
+ 10_CS2
+ 10_CS3
10_LAT
10_CSO
10_CS1
10_CS2
10_CS3
Table 1.
SOC196
Memory Map
May, 1993
INST/
INST/
INST/
INST/
INST/
*
*
*
*
*
WR *
ALE! *
ALE! *
ALE! *
ALE! *
A15/ *
A15/ *
A15/ *
A15 *
A15 *
INST
A14
A14
A14
A14/
A14/
*
*
*
*
*
A13/* A12
A13 * A12/"1/0
A13 * A12 "I/O
A13/* A12/"1/0
A13/* A12 "I/O
DEV.#O
DEV.#1
DEV.#2
DEV.#3
(Page)
Address
(Hex)
Buswidth
(Bit)
EPROM (Code)
1
2080 - FFFF
16
EPROM (Table + Data)
X
1000 - 27FF
16
RAM
0
4000 -47FF
8
I/O LATCH
0
5000
8
I/O CSO
0
6000
I/O CS1
0
7000
8
8
Device
1/0_CS2
0
8000
16
1/0_CS3
0
9000
16
439
Philips Semiconductors Microcontroller Peripherals
Application Note 020
Benefits of 16-bit design with PSD3XX
16-Blt
Performance
Advantages
It is obvious that a 16-bit bus provides
more performance than an 8-bit bus,
at least the data bus bandwidth will double.
The following factors contribute to the
performance improvement:
Program Code Fetch
Instructions such as ANDB of the 80C196
consists of 4 bytes. In an 8-bit bus system
it takes 4 bus cycles to fetch the instruction,
while in 16-bit bus designs it takes only 2
bus cycles.
Data Fetch
For applications with high data transfer
rate, where indexed or indirect references
are frequently used, a 16-bit bus takes
much less time to accomplish the same
job.
Queue Flush for Branch/Jump
Instructions
A pre-fetch queue usually speeds up
instruction execution time by providing
instructions to the Execution Unit in a
timely manner. However there is a penalty
which goes with the queue when a
successful branch or jump instruction is
executed. The queue has to be flushed,
Program Counter to be reloaded, and new
instructions to be fetched. A 16-bit bus
helps to fill up the queue much faster. This
is critical to system performance since
BranchlJump instructions are the most
frequently used instructions in general.
Free Up The System Bus
The microcontroller reduces its number of
operand fetches in a 16-bit bus, freeing the
bus for other devices which share the same
bus. In system which has a DMA Controller
or Slave Processor sharing the same
memory space with the microcontroller, the
less usage of the memory bus will enhance
system performance.
May, 1993
440
PSD3XX
Let us look at a sample program to
calculate the differences in execution time
between an 8 and a 16-bit bus. In the
typical 16-bit design example above, there
is a look-up table residing in the EPROM.
A look-up table is a quick way for the
program to provide an output to an 1/0
device based on the input value without
getting into complex mathematical
operations. The following program, which is
published in Intel application note AP-248,
does table look-up and interpolation.
Assuming the 80C196 queue is always full,
to execute the following code takes 128
state times in a 16-bit bus. In an 8-bit bus, it
takes 32 more state times just to fetch the
codes and data, not including the time the
microcontroller waits for the queue to be
filled. The estimated performance penalty
for an 8-bit bus in this application is at least
25%, and will certainly be more in the
actual run time environment. The published
statement from Intel is that it is difficult to
measure the 8-bit bus performance penalty,
but has shown to be up to 30%, depending
on the instruction mix.
The 16-bit bus design will increase the
system performance, especially for
microcontrollers which usually don't have
internal program cache or a pre-fetch
pipeline queue to lessen the penalty
caused by the bottle neck on the memory
bus. The 80C196 has an internal 4 byte
queue. This helps execution time but bus
width still remains the critical factor.
Philips Semiconductors Microcontroller Peripherals
Application Note 020
PSD3XX
Benefits of 16-bit design with PSD3XX
Table
Look-up and
Interpolation
RSEG
at 22H
IN-VAL:
TABLE_LOW:
TABLE HIGH:
IN_DIF:
IN DIFB:
TAB DIF:
OUT:
RESULT:
OUT_DIF:
1
dsb
dsw
dsw
dsw
iActual Input Value
1
1
1
IN DIF
1
equ
dsw
dsw
dsw
dsl
iUpper Input-Lower Input
:byte
iUpper Output- Lower Output
1
1
1
iDelta Out
CSEG at 2080H
LD
SP, 4I=100h
Look:
LDB
SHRB
AL, IN
AL, 41=3
VAL
ANDB
AL, 4I=11111110B
LDBZE AX, AL
LD
TABLE_LOW, TABLE
iLoad temp with Actual Value
iDivide the byte by 8
iInsure AL is a word address
iThis effectively divides AL by 2
iSO AL = IN_VAL/16
iLoad byte AL to word AX
[AX]
iTABLE_LOW is loaded with the value
iin the table at table location AX
LD
TABLE_HIGH, (TABLE+2)
SUB
iTABLE_HIGH is loaded with the value
iin the table at table loco AX+2
i (The next value in the table)
TAByIF, TABLE_HIGH, TABLE LOW
[AX]
LDBZE IN_DIF,IN_DIFB
OUT_DIF, IN_DIF, TAB DIF
iIN_DIFB=least significant 4 bits of
iIN_VAL
iLoad byte IN_DIFB to word IN_DIF
MUL
SHRAL OUT_DIF, 41=4
ADD
OUT, OUT_DIF, TABLE LOW
iOutput_difference =
iInput difference * Table difference
iDivide by 16 (2**4)
-
OUT, 41=4
OUT, ZERO
iAdd output difference to output
igenerated with truncated IN VAL as input
iRound to 12-bit answer
iRound up if Carry = 1
BR
OUT, RESULT
Look
iStore OUT to RESULT
iBranch to "Look"
CSEG
at 2100h
SHRA
ADDC
NO_Inc:
ST
Table:
DCW
Dew
Dew
Dew
Dew
OOOOH,
5DOOH,
7BOOH,
5DOOH,
1000H
2000H,
6AOOH,
7DOOH,
4BOOH,
END
May. 1993
441
3400H,
7200H,
7600H,
3400H,
4COOH iA random function
7800H
6DOOH
2200H
Philips Semiconductors Microcontroller Peripherals
Application Note 020
Benefits of 16-bit design with PSD3XX
PSD3XX
SOlutlDR
f0116-BIt
If/clDcDntlollel
In this section, we will see how a single
PSD302 is able to replace all the basic
building blocks as shown in the design
example in Figure 1. As seen from the
block diagram (Figure 2.), the PSD302
provides the following functional blocks:
o
64K bytes EPROM, as 64K x 8 or
32K x 16
o
2K bytes SRAM, as 2K x 8 or 1K x 16,
expanding the microcontroller's internal
scratch SRAM
o
Address latches/data buffers, bus
interface to most microcontrollers.
o
Programmable Address Decoder (PAD);
provides PAL type function:
18 inputs, 24 outputs and 40 product
terms.
o
Port A: an 8-bit port, each bit can be
configured as :
-I/O line
-latched address output (AO-A7)
- track ADO/AD7 as I/O lines in track
mode for shared access.
- data port DO/D7 in non-multiplexed
mode
- CMOS or open drain output
o
MaY,1993
Port B: an 8-bit port, each bit can be
configured as :
-I/O line
- chip select or logic replacement output
from the PAD
- D8-D15 in non-multiplexed mode
- CMOS or open drain output
442
PSD3XX
o
Port C: 3-bit port, each bit can be
configured as input to or output from the
PAD
o
Page Register: a 4-bit Page Register for
bank switching
o
A19/CSI input pin for power down
configuration
Figure 3 is the schematic of the design
example with the PSD302. Not all the
functions of the PSD3XX are utilized in this
example. The Page Register is not used
since the INST signal from the 80C196 can
be easily included in the PAD for page
decoding (for design with the Page
Register, see WSI Application Note 015).
The internal EPROM and SRAM of the
PSD302 replaces U5, U6, and U7 in Figure
1. Port A is configured as an I/O port to
replace U3, the I/O latch. The PAD provides
decoding functions for all the chip selects,
as well as the READY and BWIDTH inputs
to the microcontroller. Please note the
PSD302 is able to provide a 16-bit SRAM
for faster data accesses.
In this application the PSD302 is configured
to operate in a 16-bit, multiplexed mode.
The PAL equations are programmed into
the PAD. Depending on the particular bus
cycle, the PSD3021atches the microcontroller address, determines which
device is to be enabled, and provides data
output for a read cycle. If it is an I/O bus
cycle, either Port A is enabled or one of the
I/O_CS lines are activated. At the same
time, the appropriate READY and BWIDTH
signals are generated.
Philips Semiconductors Microcontroller Peripherals
Application Note 020
Benefits of 16-bit design with PSD3XX
PSD3XX
Figure 2.
PSD302
Block
Diagram
,
PAGE LOGIC
P3-PO
-
A11-A15
L
A
T
C
H
AD8-AD15
A8-A10
ill
--
~
CSI
PAD A
ALE/AS
ALE/AS
CSIOPORT
A19
CSI
,
A16-A18
,LOGIC IN
WR
RESET
13P.T.
WR
RESET
.. -
PROG.
PORT
EXP.
PCOPADB
ALE/AS
RD
RD
ro-
I
r--
27P.T.
.....
PORT
C
A
CS8CS10
f- "--
ES7
ES6
ES5
ES4
ES3
ES2
ES1
L
A
T
C
H
ADO-AD7
-
-
l
-,
~
~
-@0...-
16/8
~
r+-
..
:I~
I64KBIT
BLOCK
@
-.
08-015
SRAM
16KBIT
AO-A7
ALE/AS
PROG. CHIP
CONFIGURATION
WRlRiW
BHE/PSEN
RESET
X8,X16
MUX or NON-MUX BUSSES
SECURITY MODE
LOW POWER - CMISER
PROG.
CONTROL
SIGNALS
A19/CSI
May, 1993
443
~
I
PROG.
PORT
EXP.
PAOPORT
A
ADO-AD7/DO-D7
+
PBOPORT
B
CSIOPORT
TRACK MODE
SELECTS
RO/E/OS
PROG.
PORT
EXP.
DO-D7
~
0...-
r
r
r-
f+-
CSOCS7
~
I-
-
~
EPROM
512K BIT
~
Philips Semiconductors Microcontroller Peripherals
Application Note 020
Benefits of 16-bit desig n with PS D3XX
PSD3XX
Figure 3.
Design Example
wlthPSD302
ADO AD15
~
ADO AD15
16MIO
US
11
I
NMI
I
2
43
~
64
I
RESETI
r---fs::
-
X1
NMI
READY
CDE
BUSWIDTH
RESET
....§.. ACHO/PO.O
~
-+
4
1'1
10
8"
9
~
ACH1/PO.1
ACH2/PO.2
ACH3/PO.3
ACH4/PO.4
ACH5/PO.5
ACH6/PO.6
ACH7/PO.7
~
P2.0ITXD
P2.1/RXD
~ P2.2/EXINT
~ P2.3/T2CLK
~ P2.4IT2RST
~ P2.5/PWM
P2.6/T2UP_ON
~ P2.7IT2CAP
-4
....g.
~
-l§..
~
Jl..
...11.
+
4
-..:-
May, 1993
HSI.O
HSI.1
HSI.21HSO.4
HSI.3IHSO.5
VREF
ANGND
EA
X2
P3.0/ADO
P3.1/AD1
P3.2IAD2
P3.3/AD3
P3.4/AD4
P3.5/AD5
P3.6/AD6
P3.7/AD7
P4.0/AD8
P4.1/AD9
P4.2IAD10
P4.3/AD11
P4.4/AD12
P4.5/AD13
P4.6/AD14
P4.71AD15
Ul
12
~DOj \
59
AD1-j !\
58
AD2·j r\
57
AD3i !\
56
55
54
53
52
51
50
4lt
48
47
46
45
RD ..... 61
WR ~40
;:::41
BHE
62
ALE
63
INST
CLKOUT ~
ADa
AD1
AD2
AD3
AD4-j 1\ AD4
AD5! !\ AD5
AD6-j !\ AD6
AD7-j !\ AD7
!\ AD8
ADS j 1\ AD9
AD9-j !\ AD10
AD10-j !\ AD11
AD11-j 1'\ AD12
AD12l !\ AD13
AD13l \ AD14
AD14-j \ AD15
AD15-j
RDI
WRI
II
BHE!
ALE
INST
23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39
ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ADS
AD9
AD10
AD11
AD12
AD13
AD14
AD15
22
2
1
ill
WR
Irl
~
-1
-
4
P1.0
P1.1 58
P1.2
P1.3 ~
P1.4
P1.5 ~
r-;&P1.6
P1.7 ~
HSO.O ~
HSO.1 ~
HSO.2 ~
HSO.3 ~
~
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
21
20
19
18
17
16
15
14
11 READYI
PBa
10 BWIDTHI
PB1
PB2
8
PB3
71/0 CSOI
PB4
6 110 CS11
PB5
5 110 CS2I
PB6
4 110 CS31
PB7
-+
BHE/PSEN
ALE
RESET
A19/CSi
PCO
PC1
PC2
~
~
42
PSD302
T7'
r-ss
I/O DEVICES
8OC196
444
110 OUTO
110 OUT1
I/O OUT2
110 OUT3
110 OUT4
110 OUT5
1/00UT6
110 OUT?
1/0
1/0
110
1/0
CSOI
CS11
CS21
CS31
INST
>
Philips Semiconductors Microcontroller Peripherals
Application Note 020
Benefits of 16-bit design with PSD3XX
PSD3XX
Solution
for 16-Bit
Mlcrocontroller
(Cont.)
PSD3XX
WSI supplies PSD users with easy to use
software tools and programming devices.
MAPLE software. which is PC based.
enables designers to configure the
PSD3XX. Some of the computer screen
configuration displays for this design
example are shown in Figure 4. Figure 4A
is the address map decode for the
EPROM. SRAM and Port A. Figure 4B is
the truth table input for the READY signal.
Flgure4A.
PSD3XX
Address
Map
A
£50
ES1
ES2
ES3
ES4
ES5
ESG
ES7
RSO
CSP
A
A
A
A
A
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
1
1
0
19 18
17
16 15 14
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
N
N
N
N
N
N
N
N
N
N
1
1
1
1
1
1
0
0
ALIAS: A18
0
0
A
A
A
13 12
11
N
N
N
N
N
N
N
N
0
N
N
N
N
N
N
N
N
0
0
1
1
1
1
0
0
1
SEGMT
START
SEGMT
STOP
FILE
START
FILE
STOP
FILENAME
0
2000
4000
6000
8000
AOOO
COOO
EOOO
N/A
N/A
1FFF
3FFF
5FFF
7FFF
9FFF
BFFF
DFFF
FFFF
N/A
N/A
TEST.HEX
TEST. HEX
TEST.HEX
TEST. HEX
TEST. HEX
TEST. HEX
TEST. HEX
TEST.HEX
N/A
N/A
..
= INST
Fillil"iA19.+.)\1?i(ainarY)• •()I"$IE@MT• $"T"AAm(H~xV.~r1(j • Plq5• ($"T"A8"t,··$TOP)·.····.·.·...
Fiw.l;.NAMI$ .•• F?@·.·.eQ • • ~l"i(j • A4~!A$.•••l.J$~.·$.RAgl$aARto··~r~$~.·~MyJj~IQ·V~JQ~.·· •.•. .•. • .• • .•.•.•.
F1H$etprrttoMainMenU ..... g?""T~mppr~tyE*inppq$ F$t-@9J§fI~IP.
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PART NAME: PSD302
Figure4B.
READY
Signal
Truth Table
PIN
CS/1/0
CMOS/OD
BBO
CSO
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
PB1
PB2
PB3
PB4
PB5
PB6
PB7
C:\WSI\OLDMAP
A18 A17 A16 A15 A14 A13 A12 A11 RD WR ALE P3
0
X
X
0
1
1 0
X
X
0
X
X
X
1
0
X
0
1 1
X
X
X
0
X
0
X
X
1
0
0
X
0
0
X
X
X
0
X
X
ALIAS: A18
1
0
= INST
0
1
X
X
X
0
..
X
CS definition is the NOR of the product terms (rows). Enter 1 to select High signal. 0 to
select Active Low signal. X to mean "don't care". SPACEBAR to erase. Enter values in
columns relevant to your application; leave other columns untouched.
PART NAME: PSD302
May. 1993
C:\WSI\OLDMAP
445
Philips Semiconductors Microcontroller Peripherals
Application Note 020
Benefits of 16-bit design with PSD3XX
PSD3XX
Solution
for 16-BIt
Processor with
Non-Multiplexed
Bus
Table 2.
68302 Byte
Enable
PSD3XX
A PSD3XX can be configured to operate in
the 16-bit mode with a non-multiplexed bus.
In this case, the microcontroller address
lines AO-A 15 are tied to ADO-AD15 inputs
of the PSD3XX; Port A and B of the
PSD3XX are then configured as data ports,
connecting to data bus DO-D15. In
applications where the EPROM space in a
PSD3XX is not enough, or a large amount
of 1/0 lines and chip selects are needed,
two PSD3XXs will provide a viable solution.
Connecting two PSD3XXs to a microcontroller needs special consideration.
UDSI
LDSI
D8-D15
DO-D7
Low
Low
Enabled
Enabled
Low
High
Enabled
Disabled
High
Low
Disabled
Enabled
High
High
Disabled
Disabled
The above table is also true for most other
microcontrollers. Some use different signal
names, such as HBEI for UDSI and AO is
equivalent to LDS/. The decoding for bank
select is the same for both cases. The
following points must be considered when
configuring the PSD3XX for this type of
application:
o Address inputs to the PSD3XX have to
shift right by one. Address line A 1
connects to ADO pin of the PSD3XX and
so on. For processors which have AO,
AO is no longer used as address input.
o Provide bank select signals to the
appropriate PSD3XX for proper bank
decoding. The even bank PSD3XX must
include signal LDSI as input to the PAD,
and the odd bank PSD3XX requires the
signal UDS/. These signals can be
connected to Port C or the A 19/CSI
pin in order to be routed as PAD inputs.
May, 1993
Figure 5 shows a basic design of a 68302
microcontroller interfacing to two PSD312s.
The implementation is fairly straightforward; the two PSD302's are configured to
work in 8-bit non-multiplexed mode. The
first PSD302 (U2) occupies the even bank
of the memory space of the 68302; the
second PSD302 (U3) occupies the odd
bank. The 68302 has no AO in the address
bus; it depends on signals UDSI and LDSI
(Upper and Lower Data Strobe) to control
the flow of data on the data bus as shown
in Table 2.
446
o While inside the MAPLE software during
PSD3XX configuration, the address map
decode of the EPROM, SRAM, 1/0 port
must also reflect the shift of the address
inputs.
o The codes of the user's program have
to be split into two files, one for the
even bank PSD3XX and one for the
odd bank PSD3XX.
Philips Semiconductors Microcontroller Peripherals
Application Note 020
Benefits of 16-bit design with PSD3XX
PSD3XX
FigureS.
PSD3XX
Interface
to 68302
rc::::J
l
Vee
~
~U1
)
100
..ae..
~
.. ~
i
if
92
91
94
~
73
.l--
:\ DO
:\
.\. D2
,\. 03
4
D5
D6
D7
D8
D9
D10
\. 11
\. D12
\' D13
\' D12
\" D15
RXD1_L1RXD
TXD1_LlTXD
RCLK1_L1CLK
TCLKUDSl
CD1U1SYl
CTS1U1CR
RTS1U1RO
BRCl
RESET/
HALT!
BERRI
BUSW
DISCPU
*
79
.."~10K 1§:
RESET/
HALT!
Al
A2
A3
A4
A5
tyj
A7
A8
EXTAL
XTAL
CLKO
48
47
46
45
43
42
41
40
38
37
36
35
33
32
31
30
DO
Dl
D2
D3
D4
05
D6
D7
D8
A9
Al0
All
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
AS!
R_W!
UDSLAO
LDS,-DS!
DTACKI
RMC!
lAC
BCLRI
D9
Dl0
Dll
D12
D13
D14
D15
~ DREOUA13
~ DACKI_PA14
2.!..
DONEUA15
~~ IACK7,-PBO
~~ IACK6,-PBl
~~ IACK1,-PB2
~.g.. TIN1_PB3
1~ TOUT1UB4
1.14- TIN2UB5
~~ TOUT2I PB6
~~ WDOG{PB7
~~ PB8
~4¥- PB9
~~ PB10
1l1.. PBll
E
BRI
BG!
BGACKI
IR01!
IR06!
IR07!
FCO
FCl
FC2
AVEC!
CSO!
CS1!
CS2!
CS3!
FRll
1
2
3
5
6
7
8
9
10
11
12
14
15
16
17
19
20
21
22
24
25
26
27
AS/
A7 /
A8
Vee
1
~~O/
()
M
A7
A8
A9
Al0
All
A12
A13
A14
All/
A12/
A13/
A14~
A15
A16 ~/
10K
.. ~: ~~~ ~
::>"~ >.> >
A17~/
A18~
~~~/
A21 ~/
23
24
25
26
27
28
9
0
2
3
~t5
A16
A22 ~/
A23/
2
1
~
105
t=
t-
DO
11 _,
PAD
PAl
PA2
PA3
PA4
PA5
ptyj
PA7
E
RIW
BHEIPSEN
AS
RESET
A19!esl
PCO I dn -;;;:;--PCl 141
CSO
PC2 JjZ...
~
14
5
16
D7 _,
,
~-n1/02
PBO
PBl
PB2 ~
PB3
PB4 ~
PB5
PB6 _4
PB7
tt:
1103
1104
1/05
1/06
1107
IlnR
U3
Al
Al
Vee
Al~KAJ
p,;j
A4
A5
yyy
~
~
M
A7
AH
A9
Al0
All
AlL
A1J
A14
A15
A16
fsfi
~
I ~~8
129
~
~
21
20
19
18
17
16
15
14
ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
PSD312
L1
RWI
A:S
~
~
~
~ Al
:\A2
:\A3
A4
A5
lllti
63
i
May, 1993
U2
~~
104
103
RXD2_PAO
RXD3_PA8
~
TXD2_PAl
TXD3_PA9
RCLK2_PA2 RCLK3_PA10
TCLK3_PAll
~ TCLK2_PA3
CTS2_PA4 CTS3,-SPRXD
RTS2_PA5 RTS3,-SPTXD
~
CD2Utyj
CD3,-SPCLK
..;;.;... BRG2_PA7
BRG3_PA12
*
Al /
A2 ~/
A3/
RESETI
UDSI
fTa
Vee
LJ
~
68302
447
23
D9 -,
Dl0
Dll
D12
13
D14
14
15
PAD
PAl
PA2
PA3
PA4
PA5
ptyj
PA7
35
36
37
38
39
22
2
1
13
3
43
E
RIW
BHEIPSEN
AS
RESET
A19!esl
PCO dn
41
PCl
PC2 ~
26
27
~
~
30
Jl
32
~
nR ,
21
20
19
18
17
16
15
ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
ADll
AD12
AD13
AD14
AD15
l4
l5
¢I
~cw=
PBO
PBl
PB2
PB3
PB4 ~ CS5
PB5
PB6 ~
S7
PB7 ~ ~
CS8!
PSD312
CSl
csa
Philips Semiconductors Microcontroller Peripherals
Application Note 020
Benefits of 16-bit design with PSD3XX
PSD3XX
Solution
for 16-81t
Mlcrocontrol/er
with NonMultiplexed
Bus
The columns A15, A14, A13 in the address
map are actually A 16, A 15 and A 14 after
the input address lines to the PSD3XX are
shifted by one. Entries to the SEGMT
START/STOP or FILE START/STOP
columns must also change to relflect the
shift of the address lines. For example,
the top address of the EPROM (128K
bytes) was 1FFFF, and is now OFFFF after
the shift.
Figure 6 shows the address map of the odd
bank PSD3XX. In the map table, the
columns A19, A17, A16 are input signals of
UDS, CSO and CS1. Since this is the
decoding for the odd bank, UDS
(column A19) has to be low for any of the
PSD3XX devices to be enabled.
Furthermore, the CSO selects the EPROM
and CS1 selects SRAM and I/O Port.
The chip select logic of the 68302 also
generates the programmed amount of wait
state internally.
FlgureB.
Address Map,
Odd Bank
PSD3XX
PSD3XX
ESO
ES1
ES2
ES3
ES4
ES5
ESG
ES7
RSO
esp
A
A
A
A
19
18 17 16 15 14 13 12
11
::·0
0
0
0
0
0
0
0
0
0
x
N
N
N
N
N
N
N
N
0
0
X
X
X
X
X
X
X
X
A
A
A
A
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
1
N
N
N
N
N
N
N
N
1
1
0
0
0
0
0
0
0
0
0
x
ALIAS: A19 = UDS
1
1
1
1
SEGMT
START
SEGMT
STOP
FILE
START
FILE
STOP
FILENAME
0
2000
4000
6000
8000
1FFF
3FFF
4FFF
7FFF
9FFF
BFFF
DFFF
FFFF
N/A
N/A
ODD.HEX
ODD.HEX
ODD.HEX
ODD.HEX
ODD.HEX
ODD.HEX
ODD.HEX
ODD.HEX
N/A
N/A
AOoo
eooo
EOOO
N/A
N/A
..
6111!ri~1~%~1g(§jM~tY}9r§g§Mi)§[ABm{8~¥}:~n~FIi..$(§tAR1)§"J;9g)
Bltf;NAMq~Rq"PQ,~I'lCtALJWAS;Ps~$PACeeARJgerasear}ylj~lqyali.I~.
····:·r1• ·H • R~tLJrnt() • Main···Mehu..
9ijr$grBR~;tP.<:)Vlft'l;I
Conclusion
May, 1993
F?H·T~mpqta.IY• ·f~)(tt .• tP • PQS
L~fl¢QH.E
.·'3i9HI(;;91:4-
After going through the design examples
with the PSD3XX, it is not difficult to see the
advantages the PSD3XX family offers over
designs with discrete ICs. Besides
providing 16-bit performance, PSD3XX
devices are able to replace 7 ICs in the
80C196 example. This not only reduces
the board size dramatically but also
provides benefits such as cost reduction in
board manufacturing, higher product
reliability, lower power consumption and
reduced component cost.
448
F3.:."":.Gp.tQH~lp
Right.... F4~~mhf~
Other PSD3XX advantages over the
discrete component design include the
power down mode to reduce power
consumption when the microcontroller is
idle. The security feature protects the code
stored in the EPROM from illegal copy. The
flexibility, programmability, and ease of use
which come with the PSD3XX truly make it
an optimal solution for 16-bit embedded
applications.
Philips Semiconductors
Section 4
Development Systems
PSD3XX Programmable
Mlcrocontroller Peripherals
INDEX
PSDGold/PSDSilver Development System ............................................ ..451
WS6000 MagicPro® Memory
and Programmable Peripheral Programmer. .......................................... ..455
MagicPro@ is a registered trademark of WaferScale Integration. Inc.
Philips Semiconductors Mlcrocontroller Peripherals
PSDGold/PSDSilver
Development System
PSD3XX
Description
PSDGoldlPSDSilver is a complete set of
IBM-PC-based development tools. They
provide the integrated easy-to-use environment to support PSD3XX family.
The tools run on an IBM-PC XT, AT or
compatible computer running MS-DOS
version 3.1 or later.
MAPLE
MAPLE is the Locator Editor. It has the
following features:
o
Generating the PAD programming data
that maps the EPROM, SRAM and Chip
Selects Outputs to the user's address
space.
o
Combining all the different files to be
programmed into the EPROM
segments.
o
o
o
Write RAM to FILE
o
Verify MAP
o
o
o
Program MAP
o
MAPPRO
WS6000
MaglcPro@
Programmer
May, 1993
Simple Menu Driven Commands for
selecting different configurations of the
PSD3XX
- Byte wide or word wide operation.
- Address or Chip Select Input (CSI)
Mode.
- PAD security option.
MAP PRO is the interface software that
enables the user to program a PSD3XX on
the WS6000 MagicPro® programmer. The
MAPPRO enables the user to load the
program into the programmer and to
execute the following operations.
o
Help
o
o
Upload RAM from MAP
Display MAP data
Blank test MAP
Configuration
Quit
Load RAM from disk
The WS6000 MagicPro Programmer is an
engineering development tool designed to
program all WSI programmable products
(EPROMs, RPROMs, PAC 1000, PSD3XX
family and SAM448). It is used within the
IBM-PC and compatible environment. The
MagicPro consists of a short plug-in board
and a Remote Socket
451
Adaptor (RSA). It occupies a short
expansion slot in the PC. The RSA has two
ZIF-DIP sockets that will support 24,28,32
and 40 pin standard 600 mil or slim 300 mil
DIP packages without adaptors. Other
packages are supported using adaptors.
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSDGold/PSDSilver
Development System
PSDGold
Contents
o MAPLE-MAP Locator editor.
o MAP PRO
o
o
Interface software to MAP168 device
programmer (MagicPro)
o
May, 1993
Software user's manual
452
WS6000 MagicPro Programmer
A Socket Adaptor and Two
Product Samples
Philips Semiconductors Microcontroller Peripherals
PSDGold/PSDSilver
Development System
PSD3XX
PSDS/I"el
Contents
o
MAPLE-MAP Locator editor.
o
MAPPRO
Interface software to PSD100 device
programmer (MagicPro)
o
May, 1993
Software user's manual
453
Philips Semiconductors Microcontroller Peripherals
PSD3XX
PSDGold/PSDSilver
Development System
WS6D15
Socket
Adaptor
The WS6015 is a socket adaptor that
mounts on the MagicPro RSA and adapts
the PSD3XX or MAP168 in a 44-pin PGA
package to the programmer.
WS6D20
Socket
Adaptor
The WS6020 is a socket adaptor that
mounts on the MagicPro RSA and adapts
the PSD3XX in a 52-pin PQFP package to
the programmer.
WS6D21
Socket
Adaptor
The WS6021 is a socket adaptor that
mounts on the MagicPro RSA and adapts
the PSD3XX in a 44 pin CLDCC or PLDCC
package to the programmer.
OrderIng
Information
May, 1993
Description
Product
PSDSilver
Contains PSD3XX and PSD100 Software (MAPLE-MAP and
MAPPRO), Software User's Manual.
PSDGold
Contains PSD-Silver, WS6000 MagicPro Programmer, a Socket
Adaptor and Two Product Samples.
454
Philips Semiconductors Mlcrocontroller Peripherals
MaQicPro® Memory and Programmable
Peripheral Programmer
Key Features
o
o
General
Description
Programs All CMOS Memory and
Programmable Peripheral Products
and all future Programmable Products
Programs 24,28,32 and 40 Pin
Standard 600 Mil or Slim 300 Mil Dip
Packages without Adaptors
MagicPro is an engineering
development tool designed to program
Programmable Peripherals. It is used
within the IBM-PC® and compatible
computers. The MagicPro is meant to
bridge the gap betweeen the introduction of
a new programmable product and the
availability of programming support from
programmer manufacturers (e.g., Data 110,
etc.). The MagicPro programmer and
accompanying software enable quick
programming of newly released
programmable products, thus accelerating
the system design process.
The MagicPro plug-in board is integrated
easily into the IBM-PC. It occupies a short
expansion slot and its software requires
only 256K bytes of computer memory. The
two external ZIF-Dip sockets in the Remote
May, 1993
455
WS6000
o
o
o
Programs LCC, PGA and QFP
Packaged Product by Using Adaptors
Easy-to-Use Menu-Driven Software
Compatible with IBM PC/XT/AT
Family of Computers (and True
Plug-Compatible
Socket Adaptor (RSA) support 24, 28, 32
and 40 pin standard 600 mil or slim 300
mil Dip packages without adaptors. LCC,
PGA and QFP packages are supported
using adaptors.
Many features of the MagicPro
Programmer show its capabilities in
supporting future products. Some of these
are:
o
24 to 40 pin JEDEC Dip Pinouts
o
1 Meg Address Space
(20 address lines)
o
16 Data 110 Lines
Philips Semiconductors Microcontroller Peripherals
Ma~icPro® Memory and Programmable
Penpheral Programmer
WS6000
General
Description
(Cont.)
The MagicPro menu driven software
makes using different features of the
MagicPro an easy task. Software updates
are done via floppy disk which eliminates
the need for adding a new memory device
for system upgrading.
The MagicPro reads Intel Hex format for
use with assemblers and compilers.
MaglcPro
Commands
Q
Q
Q
Q
Q
Q
Q
Help
Move/Copy RAM
Q
Q
Q
Q
Q
Q
Q
Q
Size:
Q
Technical
Information
Upload RAM from Device
Load RAM from Disk
Write RAM to Disk
Display RAM Data
Edit RAM
IBM-PC Short Length Card
Q
Port Address Location:
100H to 1FFH - default 140H (if a
conflict exists with this address space,
the address location can be changed
in software and with the switches on
the plug-in board.)
Q
System Memory Requirements:
256K Bytes of RAM
Q Power:
+ 5 Volts, 0.03 Amp; +12 Volts,
0.04 Amp
May, 1993
456
Fill RAM
Blank Test Device
Verify Device
Program Device
Select Device
Configuration
Quit MagicPro
Remote Socket Adaptor (RSA):
The RSA contains two ZIF-Dip sockets
that are used to program and read WSI
programmable products. The 32 pin
ZIF-Dip socket supports 24, 28 and 32
pin standard 600 mil or slim 300 mil
Dip packaged product. The 40 pin
ZIF-Dip socket supports all 40 pin Dip
packages. Adaptor sockets are
available for LCC, PGA and QFP
packages.
Philips Semiconductors Microcontroller Peripherals
MagicPro® Memory and Programmable
Peripheral Programmer
Ordering
Information
WS6000
The WS6000 MagicPlo System Contains:
o
o
o
MagicPro IBM-PC Plug-in Programmer Board
MagicPro Remote Socket Adaptor and Cable
MagicPro Operating System Floppy Disk and Operating Manual
The WS6000 MagicPlo AdaptolS Include:
0
WS6001 28-Pin CLLCC Package
Adaptor for Memory.
0
WS6023 100-Pin PQFP Package
Adaptor for PAC 1000
0
0
WS6008 28-Pin Dip Adaptor for SAM448
0
WS6009 28-Pin PLDCC/CLDCCI
CLLCC Package Adaptor for SAM448
WS6024 28-Pin CLLCC Package
Adaptor for Memory
0
WS6025 32-Pin PLDCC/CLDCC
Package Adaptor for Memory
(WS57C51 B/C Only)
0
WS6026 32-Pin CLLCC
Package Adaptor for Memory
(WS57C51 B/C Only)
0
WS6027 32-Pin PLDCC/CLDCC
Package Adaptor for Memory
(WS57C71 COnly)
0
WS6028 32-Pin CLLCC
Package Adaptor for Memory
(WS57C71 COnly)
0
WS6010 88-Pin PGA Package Adaptor
for PAC 1000
0
WS6012 32-Pin CLDCC/CLLCC/PLDCC
Package Adaptor for Memory
0
WS6020 52-Pin PQFP Package
Adaptor for PSD3XX
0
WS6021 44-Pin CLDCC/PLDCC
Package Adaptor for PSD3XXl3XXL
0
WS6022 44-Pin PGA Package Adaptor
for PSD3XXl3XXL
MagicPro is a registered trademark of WaferScale Integration, Inc.
IBM-PC is a registered trademark of IBM Corporation.
May, 1993
457
Philips Semiconductors
Section 5
Package Outlines
PSD3XX Programmable
Mlcrocontroller Peripherals
INDEX
J2
44-Pin Plastic Leaded Chip Carrier (PLCC) ................... .461
L4
44-Pin Ceramic Leaded Chip Carrier (CLCC)
with Window (Package Type L) .......................................462
Q2
52-Pin Plastic Quad Flatpack (PQFP) ............................ .463
Philips Semiconductors Mlcrocontrolier Peripherals
Package Outlines
J2
44-PIN PLASTIC LEADED CHIP CARRIER (PLCC) (PACKAGE TYPE J)
","I
m
!JJ
E1
.-L
E
! !
c
Rev.S
Symbol
A
A1
A2
8
81
C
0
01
02
03
E
E1
E2
E3
e1
N
May, 1993
Family: Plastic Leaded
Millimeters
Min
Max
Notes
4.19
4.57
2.54
2.79
3.76
3.96
0.53
0.33
0.66
0.81
0.246
0.262
17.40
17.65
16.51
16.61
14.99
16.00
12.70
Reference
17.65
17.40
16.51
16.61
14.99
16.00
12.70
Reference
1.27
Reference
44
Chip Carrier
Inches
Max
0.180
0.110
0.156
0.021
0.032
0.0103
0.695
0.654
0.630
Min
0.165
0.100
0.148
0.013
0.026
0.0097
0.685
0.650
0.590
0.500
0.685
0.650
0.590
Notes
Reference
0.695
0.654
0.630
0.500
0.050
Reference
Reference
44
461
J2
Philips Semiconductors Microcontroller Peripherals
Package Outlines
L4
44-PIN CERAMIC LEADED CHIP CARRIER (CLCC) WITH WINDOW (PACKAGE TYPE L)
1
A1
A
Rev.S
Symbol
A
A1
A2
8
81
C
0
01
02
03
E
E1
E2
E3
e1
N
Family: Ceramic Leaded Chip Carrler-CERQUAD
Inches
MlIlIl1\eters
Min
Max
Min
Max
Notes
3.94
2.29
3.05
0.43
0.66
0.15
17.40
16.31
14.99
0.155
0.095
0.120
0.017
0.026
0.006
0.685
0.642
0.590
4.57
2.92
3.68
0.53
0.81
0.25
17.65
16.66
16.00
12.70
17.40
16.31
14.99
Reference
12.70
1.27
44
0.500
0.685
0.642
0.590
17.65
16.66
16.00
Reference
Reference
Notes
0.180
0.115
0.145
0.021
0.032
0.010
0.695
0.656
0.630
Reference
0.695
0.656
0.630
0.500
0.050
44
Reference
Reference
L4
May, 1993
462
Philips Semiconductors Microcontroller Peripherals
Package Outlines
Q2
52-PIN PLASTIC QUAD FLATPACK (PQFP)
Rev. 7
Symbol
a
A
A1
A2
8
C
D
D1
D3
E
E1
E3
e1
L
N
Min
Family: Plastic Quad Flatpack
MIllimeters
Min
Max
Notes
0°
2.55
0.00
2.55
0.35
0.13
17.65
13.95
8°
3.05
0.25
2.80
0.50
0.23
18.15
14.05
12.00
17.65
13.95
Reference
12.00
1.00
0.95
0.65
0.472
0.472
0.0394
Reference
Reference
0.037
0.026
52
Reference
0.715
0.553
0.695
0.549
Reference
Reference
Notes
8°
0.120
0.010
0.110
0.020
0.009
0.715
0.553
0°
0.100
0.000
0.100
0.014
0.005
0.695
0.549
18.15
14.05
Inches
Max
52
Q2
May, 1993
463
Philips Semiconductors
Section 6
Sales Offices, Representatives &
Distributors
PSD3XX Programmable
Mlcrocontroller Peripherals
Philips Semiconductors Microcontroller Peripherals
Sales Offices, Representatives and Distributors
PHILIPS
SEMICONDUCTORS
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, CA 94088-3409
ALABAMA
Huntsville
Philips Semiconductors
Phone: (205) 464-0111
Elcom, Inc.
Phone: (205) 830-4001
ARIZONA
Scottsdale
Thorn Luke Sales, Inc.
Phone: (602) 541-5400
CAUFORNIA
Calaba..s
Philips Semiconductors
Phone: (818) 880~04
Irvine
Philips Semiconductors
Phone:~14)833-8980
( 14) 752-2780
Orangevale
Webster Associates
Phone: (916) 989-0843
San Diego
Philips Semiconductors
Phone: (619) 560-0242
San Jose
B.A.E. Sales, Inc.
Phone: (408) 452-8133
Sunnr.ale
Philips Semiconductors
Phone: (408) 991-3737
COLORADO
E,lewood
hilips Semiconductors
Phone: (303) 792-9011
Thom Luke Sales, Inc.
Phone: (303) 649-9717
CONNECTICUT
Wallingford
JEBCO
Phone: (203) 265-1318
FLORIDA
Oviedo
Conley and Assoc., Inc.
Phone: (401) 365-3283
GEORGIA
Atlanta
Philips Semiconductors
Phone: (404)594-1392
Norcross
Elcom,lnc.
Phone: (404) 447-8200
ILLINOIS
Hoffman Estates
Micro-Tex, Inc.
Phone: (708) 765-3000
May, 1993
OHIO
Aurora
S.J Associates, Inc.
Phone: (216) 562-2050
1ta8Ca
Philips Semiconductors
Phone: (708) 250-0050
Ma=,
INDIANA
Indianapolis
Inc.
Mohrfield
Phone: (311)
969
Kokomo
Philips Semiconductors
Phone: (317) 459-5355
Columbus
S-J Associates, Inc.
Phone: (614) 885~700
Kettering
S-J Associates, Inc.
Phone: (513) 298-7322
MARYLAND
Columbia
Third Wave Solutions, Inc.
Phone: (301) 290-5990
MASSACHUSEnS
Chelmsford
JEBCO
Phone: (508) ~5800
Westford
Philips Semiconductors
Phone: (508) 692~211
MICHIGAN
Monroe
S.J Associates
Phone: (313) 242-0450
Novl
Philips Semiconductors
Phone: (313) 347-1400
Parma
S-J Associates, Inc.
Phone: (216) 888-7004
West Carrollton
S.J Associates, Inc.
Phone: (513) 438-1700
OREGON
Beaverton
Philips Semiconductors
Phone: (503) 627-0110
Westem Technical Sales
Phone: (503) 644-8860
PENNSYLVANIA
erie
S.J Associates, Inc.
Phone: (216)888-7004
Hatboro
Delta Technical Sales, Inc.
Phone: (215) 957-0600
MINNESOTA
Bloom"~ton
High echnol~ Sales
Phone: (612) 4-9933
MISSOURI
Bridgeton
Centech, Inc.
Phone: (314) 291-4230
Raytown
Centech, Inc.
Phone: (816) 358-8100
Pittsburgh
S-J Associates, Inc.
Phone: (216) 888-7004
Plymouth Meeting
Philips Semiconductors
Phone: (215) 825-4404
TENNESSEE
Greeneville
Philips Semiconductors
Phone: (615) 639-0251
NEW JERSEY
Toms River
Philips Semiconductors
Phone: (908) 505-1200
TEXAS
Austin
Philips Semiconductors
Phone: (512) 339-9945
NEW YORK
Ithaca
Bob Dean, Inc.
Austin
Phone: (601) 257-1111
Rockville Centre
S.J Associates
Phone: (516) 536-4242
S~ergiStiC Sales, Inc.
P
ne:(512)346-2122
Houston
S~ergiStiC Sales, Inc.
Wa~~lngers Falls
ilips Semiconductors
Phone: (914) 297-4074
Bob Dean, Inc.
Phone: (914) 297-6406
NORTH CAROUNA
Matthews
ADI,lnc.
Phone: (704) 847-4323
P
ne:(713)937-1990
Richardson
Philips Semiconductors
Phone: (214) 644-1610
Richardson
WASHINGTON
Bellevue
Western Technical Sales
Phone: (206) 641-3900
Spokane
Western Technical Sales
Phone: (509) 922-7600
WISCONSIN
Waukesha
Micro-Tex, Inc.
Phone: (414) 542-5352
CANADA
PHI UPS
SEMICONDUCTORS
CANADA, LTD.
Ca~ary, Alberta
ectI-Trek. Ltd.
Phone: (403) 241-1719
Kanata, Ontario .
Philips Semiconductors
Phone: (613) 599-8720
Tech-Trek. Ltd.
Phone: (613) 599-8787
Mlssls.auga, Ontario
Tech-Trek. Ltd.
Phone: (416) 238-0366
Richmond, B.C.
Tech-Trek, Ltd.
Phone: (604) 276-8735
Ville St Laurentk Quebec
Tech-Trek. L .
Phone: (514) 337-7540
MEXICO
Anzures Section
Philips Components
Phone: 52-5-533-3858
EIPaso,TX
Philips Components
Phone: (915) 775-4200
PUERTO RICO
Santurce
Mectron Grou~
Phone: (809) 23~165
DISTRIBUTORS
Contact one of our
local distributors:
AlmaclArrow Electronics
Anthem Electronics
Arrow/Schweber Electronics
Falcon Electronics, Inc.
Gerber Electronics
Hamilton/Avnet Electronics
Marshall Industries
Wyle/EMG
Zentronics, Ltd.
S~ergistic Sales, Inc.
P
ne:(214)644-3500
UTAH
Salt Lake City
Electrodyne
Phone: (801) 264-8050
Smithfield
ADI,lnc.
Phone: (919) 934-8136
467
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Tel. (02)52U111,FaX.(02}5251246
Brazil: Aua doAocia 22Q"'5tbFlilOr,
CEP: 045S~SAOPAt.lL()'s~ BIaZiI
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canada: INTEGRATED OIRCUlTS:
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Finland: Sinikal~IItie~;Sf~EspQO.
Tel. {9} 50261, Fa(9}520971
F,.nce: 41'\1e do Port~,Vins.BP3t1
92156 SURESNES~,
Tel, (01}4Q998161;F.;(01}40998536
Getmany: Burcl!ardstf~19jl)f2»AMBURG 1;
Tel. (040) 3296-0, Fax, «(J40}3296213
Gmce: No,15, 25th March $1f~;GfUm8TAVRO$;
T$1. (01) 4894 3391489i\9t1.Fax{01) 48.14 240
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Tel. (0}42 45121, Fax. (0)4806960
India: PEICO ElECTRONiC$&ElECTRlCAlS UO .•
ComponeoISOepl~,.ShivsagatEstate,·8Iock·A'.
Dr. AnllkJBesanIRd..Worti, BOMBAY4pO 018.
Tel. (022)49 38 541,1'.:(022) 4938722
IrufoMsia:PhiJiP$ Ho\l$6,~IlH.R.Rasuna Said Kav. 3-4,
P.O,SQX4252. JAKARTA 1~
T$\. (021)5201122,Fax{~1)52051sg,
J~lI:Newst~,CIonskeagh. OOBLIN14;
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lI(tly: V.l.e F: T!I$ti; 327; 20162:-MItANQ)
Tel. (02) 6752,1. Fax, (02) 6752 3350
• 1\: Philips Bldg. 13,37,I(Qhnan2-:17lW\CEt.bNA.
reI. {93}3016312. Fax.~{93}~014243
SWeden: Kotlbyga1ilO 7,AkaI!a;Post: S-1li4a5STOCKHOLM,
Tel, (O)$-63212tlOO,F~. (O)~632 2745
S.rland: Alfmendstmsse t4M42. CH'8027 ZORICH,
TeI.(01J48112~ 11,fax.(01~4$285 9S
Tahvan:69.Min.SIieng~tRo!ld,~3, RO.llok 22978,
tAlPEll0446. TeI,{2}~7666,F:ax. (2)5005e99
TNiland: PHIj.;IPS.EtE(:TRON!C$\HAIlANIl ltd.
60/14 MOO tt.8AHGl\fA" TradRoad KiltS
PrakanoogiBANGKOI(10~
Tel.(2}399 3280 to9,(2)398~, Fax (2)~Q82080
l\irkey:TaIa~ cad.NO.. 5; 8O&4OLEVENTIISTANBUl.;
Te.,,<01) 27i21m,Fax,{01J4693094
United Kingdom: Phifips SemIconductors Umii!ld; RO. Box.6$.
Philips Ho\l$6; TorringtonP~.l.ONOON WC1E1'HD.
Tel. (071) 436 4144, Fax; {071}323 0342
Unittc(States: .IlIftEGRATEf)CIRCUtTS:
811 EastArqUllSAvenue,SUNNYVAl.E,.CA ~08&-3409,
1el. (800} 234-1381,Fax,{7()8}296~
OIS¢RETESJ:MlCONt'.lVCroRS: 2001.W~tBiueHeronBMI.,
P.O. Sox 10330, IllVtEHABEAqH,aoRIOA 33404,
Tet(800}447-3762and (401)881.gzoo,Fax:.(407) ~1~~
UtiigUay:Cortmel Mora433.MOHTEVIOEO;
Tet{Q2p04044. F.(02} 920601
Ven~.: (;aile 6, EdJa Tr$S -tOlas. CARACAS1074A,
App; Post. 7a1t 7.T$1: (02) 2417509, Fax (02) 24t 4518
Forall other countries apply to;.flhilips Semiconductors•
InternatiOnal Marketingand Sales: BuHding BAF4,
P.O~Box 218, 56OOMOElNDHOVEN, The Nelti~ands,
Telex. 35000phtcnl. Fax .+3140~724S25
Scr)19
@PltilipsElecl{onicSS.¥-1993
All rights are reserved. ReprtXludion in whole orin part is prohibited
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The information. pre$ented ill this dQculilent d!leS not form part. of any
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