1995_Intel_Flash_Memory_Volume_1 1995 Intel Flash Memory Volume 1
User Manual: 1995_Intel_Flash_Memory_Volume_1
Open the PDF directly: View PDF 
.
Page Count: 1602
| Download | |
| Open PDF In Browser | View PDF |
SANTA CLARA DIVISION
3000 Bowers Avenue
Santa Clara, CA 95051-0919
(408) 727-2500 • (800) 866-9953
intel®
24-HOUR AUTOMATED TECHNICAL SUPPORT*
Intel's Application Bulletin Board System (BBS) and FaxBack System are at your service, 24-hours a day, at no
charge, and the information is updated frequently.
FaxBack SYSTEM
Technical and product information are available 24-hours a day! Order documents containing:
o Design/Application Recommendations
• Stepping/Change Notifications
• Quality and Reliability Information
• Product Announcements
• Product Literature
• Intel Device Characteristics
Information on the following subjects is also available:
•
•
•
•
Microcontroller and Flash
OEM Branded Systems
Multibus/BBS Listing
Multimedia
• Development Tools
• Quality and Reliability/Change Notification
• Microprocessor/PCI/Peripheral
o Intel Architecture Lab
To use FaxBack for Intel components and systems, dial (800) 628-2283 or (916) 356-3105 (U.S. and Canada)
or +44{O} 1793-496646 (Europe) and follow the automated voice-prompt menu. Document orders will be faxed
to the fax number you specify. Catalogs are updated twice a month, so call for the latest information!
BULLETIN BOARD SYSTEM
Intel's Application Bulletin Board System (BBS) enables file retrieval 24-hours a day. The following can be
located on the BBS:
• ProductlTechnical Documentation
• Firmware Upgrades
• Quality and Reliability Data
• Software Drivers
• Tool Information
• Software/Application Utilities
To use the Intel Application BBS (components and systems), dial (916) 356-3600 for download access (U.S.
and Canada) or +44{O} 1793-496340 (Europe). The BBS will support 1200-19200 baud rate modem. Typical
modem configuration: 9600 baud rate, No Parity, 8 Data Bits, 1 Stop Bit. A directory listing of BBS files is also
available through Fax Back or our 800 BBS (800-897-2536).
Retail Products
Information on Intel's retail products (Coprocessors and wireless, video, personal conferencing and network
products) is available through the following services:
Internet:
CompuServe :
country
ftp.intel.com (143.185.65.2)
GO INTELFORUM (modem settings: E-7 -1, up to 14.4 Kbps)
BBS (N-8-1 J up to 14.4 Kbps)
FaxBack
North America
(503) 264-7999
(800) 525-3019 or
(503) 264-6835
Europe
Australia
Taiwan
+44 1 793-432955
+61 2975-3066
+44 1 793-432509
+886 2 718-6422
+61 2 975-3922
+8862514-0815
+65 256-4776
+65 256-5350
Singapore
Hong Kong
+852 530-4116
+852 844-4448
Korea
+822 784-3430
+822767-2594
'Support services provided courtesy of Intel Application Support
LITERATURE
For additional information on Intel products in the U.S. or Canada, call Intel's Literature Center at
(800) 548-4725 or write to:
Intel Literature
P.O. Box 7641
Mt. Prospect, II 60056-7641
To order literature outside of the U.S. and Canada contact your local international sales office.
CURRENT DATABOOKS
Product line databooks contain datasheets, application notes, article reprints, and other design information.
Databooks can be ordered in the U.S. and Canada by calling TABlMcGraw-HiII at 1-800-822-8158; outside of
the U.S. and Canada contact your local international sales office.
Title
Automotive Products
Embedded Applications (2 vol. set)
Embeclded Microcontrollers
Embedded Microprocessors
Flash Memory (2 vol. set)
Intel486™ Microprocessors and Related Products
i960® Processors and Related Products
Military and Special Products
Networking
OEM Boards, Systems and Software
Packaging
Pentium™ Processors and Related Products
Peripheral Components
Intel Order Number
231792
270648
270646
272396
210830
241731
272084
210461
297360
280407
240800
241732
296467
ISBN
N/A
1-55512-242-6
1-55512-230-2
1-55512-231-0
1-55512-232-9
1-55512-235-3
1-55512-234-5
N/A
1-55512-236-1
1-55512-237-X
1-55512-238-8
1-55512-239-6
1-55512-240-X
A complete set of this information is available on CD-ROM through Intel's Data on Demand program, order
number 240897. For information about Intel's Data on Demand ask for item number 240952.
Flash Memory
Volume 1
Synchronous and DRAM-Interface Components,
FlashFile ™ Components, Boot Block Components,
Bulk-Erase Components
1995
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as
provided in Intel's Terms and Conditions of Sale for such products.
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors
which may appear in this document nor does it make a commitment to update the information contained
herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your
product order.
I
MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its
FASTPATH trademark or products.
·Other brands and names are the property of their respective owners.
Additional copies of this document or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
@INTELCORPORATION,1995
DATASHEET DESIGNATIONS
Intel uses various datasheet markings to designate each phase of the document as it
relates to the product. The markings appear in the lower inside comer of each datasheet
page. Following are the definitions of each marking:
Datasheet Marking
Description
Product Preview
Contains information on products in the design phase of
development. Do not finalize a design with this
information. Revised information will be published
when the product becomes available.
Advanced Information
Contains information on products being sampled or in
the initial production phase of development. *
Preliminary
Contains preliminary information on new products in
production. *
No Marking
Contains information on products in full production. *
* Specifications within these datasheets are subject to change without notice. Verify with your local Intel
sales office that you have the latest datasheet before finalizing a design.
Memory Overview
Flash Memory Overview and
Support Tools
Synchronous &. DRAM-Interface
Flash Memory Components and
FlashFUe Components
Boot Block Components
Bulk-Erase Components
PCMCIA Flash Memory Cards
PCMCIA-ATA Flash Memory
Drives
Flash Automotive Components
Process Engineerin~ Reports
Flash Memory SmartDieTM
Products
Article Reprints
CONTENTS
Table of Contents
Alphanumeric Index ........................... '........................... .
xv
CHAPTER 1
Memory Overview
Intel Memory Technologies ................................................ .
1-1
CHAPTER 2
Flash Memory Overview and Support Tools
Flash Memory Overview .................................................. .
SUPPORT TOOLS
Flash Memory Customer Support.-.......................................... .
Sprint PLUS4811ntei Support Version ....................................... .
Multi-APRO Programmer/Intel Support Version ........................•......
Flash Memory Card and Flash Drive Evaluation Kit Product Brief ............... .
Small Outline Package Guide Overview ..................................... .
Intel FLASH Builder Software Product Brief .................................. .
APPLICATION NOTES
AP-357 Power Supply Solutions for Flash Memory ............................ .
AP-374 Flash Memory Write Protection Techniques .......................... .
AB-29 Flash Memory Applications in Laser Printers ........................... .
TECHNICAL PAPER
Small and Low Cost Power Supply Solution for Intel's Flash Memory Products
2-1
2-7
2-9
2-13
2-16
2-18
2-20
2-22
2~64
2-71
2-78
CHAPTER 3
Synchronous and DRAM-Interface Flash Memory Components
PRODUCT BRIEFS
Intel 28F016XS Embedded Flash RAM Product Brief .......................... .
Intel 28F016XD Embedded Flash RAM Product Brief .... , .................... .
DATA SHEETS
28F016XS 16-Mbit (1-Mbit x 16, 2-Mbit x 8) Synchronous Flash Memory ......... .
28F016XD 16-Mbit (1-Mbit x 16) DRAM - Interface Flash Memory ...........•...
APPLICATION NOTES
AB-58 28F016XD - Based SIMM Designs .................................... .
AP-398 Designing with the 28F016XS ....................................... .
AP-384 Designing with the 28F016XD .........•.............................
AP-600 Performance Benefits and Power/Energy Savings of 28F016XS-Based
System Designs ..•..................•..............•..... '.............. .
TECHNICAL PAPERS
Interfacing the 28F016XS to the i960@ Microprocessor Family .................•
Interfacing the 28F016XS to the Intel486TM Microprocessor Family ............. .
3"1
3-2
3-3
3-50
3-104
3-112
3-142
3-172
3-196
3-238
FlashFile™ Components
DATA SHEETS
DD28F032SA 32-Mbit (2-Mbit x 16, 4-Mbit x 8) FlashFile Memory ............... .
28F016SV 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFile Memory .................. .
28F016SA 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFile Memory .................. .
Extended Temperature 28F016SA 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFile
Memory .......•.......•.•.........................................' .....
28F008SA 8-Mbit (1-Mbit x 8) FlashFile Memory (Extended Temperature
Specifications Included) .................................................•
28F008SA-L 8 Mbit (1 Mbit x 8) Flash Memory ..................•.... '......... .
APPLICATION NOTES
AP-607 Multi-Site Layout Planning with Intel's FlashFile Components, Including
I ROM Compatibility ................................... ,.................. .
I
3-257
3-303
3-359
3-403
3-443
3-476
3-504
xi
CONTENTS
Table of Contents (Continued)
AP-393 28F016SV Compatibility with 28F016SA ............................. .
AP-359 28F008SA Hardware Interfacing ...................................•.
AP-360 28F008SA Software Drivers ........................................ .
AP-362 Implementing Mobile PC Designs Using High Density FlashFile
Components ................................•..........................
AP-364 28F008SAAutomation and Algorithms ............................... .
AP-375 Upgrade Considerations from the 28F008SA to the 28F016SA .......... .
AP-377 16-Mbit Flash Product Family Software Drivers 28F016SA, 28F016SV,
28F016XS, 28F016XD .................................................. .
AP-378 System Optimization Using the Enhanced Features of the 28F016SA .... .
AP-399 Implementing Mobile Intel486 SX Microprocessor PC Designs Using
FlashFile TM Components ................................................ .
ENGINEERING REPORT
ER-27 The Intel 28F008SA Flash Memory ................................... .
3-533
3-551
3-562
3-585
3-640
3-654
3-667
3-722
3-743
3-783
CHAPTER 4
Boot Block Components
DATA SHEETS
8-Mbit (512K x 16, 1-Mbit x 8) SmartVoltage Boot Block Flash Memory Family. . . ..
4-Mbit (256K x 16, 512K x 8) SmartVoltage Boot Block Flash Memory Family
(Extended Temperature Specifications Included) ........................... .
2-Mbit (128K x 16, 256K x 8) SmartVoltage Boot Block Flash Memory Family
(Extended Temperature Specifications Included) ........................... .
28F400BX-T/B, 28F004BX-T/B 4 Mbit (256Kx 16, 512K x 8) Boot Block Flash
Memory Family ........................................... : ............ .
28F400BL-T IB, 28F004BL-T IB 4-Mbit (256K x 16, 512K x 8) Low Power Boot
Block Flash Memory Family ; ............................................ .
28F200BX-T/B, 28F002BX-T/B 2 Mbit (128Kx 16, 256K x 8) Boot Block Flash
Memory Family ........................................................ .
28F200BL-T/B, 28F002BL-T/B 2-Mbit (128K x 16, 256K x 8) Low Power Boot
Block Flash Memory Family ............................................. .
28F001 BX-T128F001 BX-B 1M (128K x 8) CMOS Flash Memory ................ .
APPLICATION NOTES
AP-604 Using Intel's Boot Block Flash Memory Parameter Blocks to Replace
EEPROM ............................................................. .
AB-60 2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family Overview ..... .
AP-341 Designing an Updatable BIOS Using Flash Memory .................... .
AP-363 Extended Flash Bios Concepts for Portable Computers ................ .
. ENGINEERING REPORTS
ER-26 The Intel 28F001 BX-T and 28F001 BX-B Flash Memories ................ .
ER-29 The Intel2/4-Mbit Boot Block Flash Memory Family .................... .
TECHNICAL PAPER
Boot Block Flash: The Next Generation White Paper .....•.....................
.
4-1
4-13
4-68
4-124
4-174
4-218
4-265
4-307
4-341
4-349
4-357
4-400
4-422
4-437
4-466
CHAPTER 5
Bulk-Erase Components
DATA SHEETS
28F020 2048K (256K x 8) CMOS Flash Memory ............................... .
28F010 1024K (128K x 8) CMOS Flash Memory ........... ~ .................. .
28F512 512K (64K x 8) CMOS Flash Memory ................................ .
xii
5-1
5-33
5-64
I
CONTENTS
Table of Contents (Continued)
28F256A 256K (32K x 8) CMOS Flash Memory .............................. .
5-92
APPLICATION NOTES
AP-316 Using Flash Memory for In-System Reprogrammable Nonvolatile Storage . 5-117
AP-325 Guide to First Generation Flash Memory Programming ................. . 5-162
ENGINEERING REPORT
ER-24 Intel Flash Memory 28F256A, 28F512, 28F010, 28F020 ................. . 5-184
CHAPTER 6
PCMCIA Flash Memory Cards
Series 2 + Flash Memory Card User's Manual Overview ....................... .
DATA SHEETS
Series 2 + Flash Memory Cards 4-, 8-, 20- and 40-Megabyte ................... .
Series 2 Flash Memory Cards iMC002FLSAliMC004FLSAliMC01 OFLSAI
iMC020FLSA (Extended Temperature Specifications Included) ............... .
iMC004FLKA 4-Megabyte Flash Memory Card ............................... .
iMC002FLKA 2-Mbyte Flash Memory Card .................................. .
iMC001 FLKA 1-Megabyte Flash Memory Card ............................... .
APPLICATION NOTES
AP-606 Interchangeability of Series 1, ·Series 2 and Series 2 + Flash Memory
Cards ...... ; .......................................................... .
AP-343 Solutions for High Density Applications Using Intel Flash Memory ....... .
AP-361 Implementing the Integrated Registers of the Series 2 Flash Memory Card.
SUPPORT TOOLS
Flash Memory Card and Flash Drive Evaluation Kit Product Brief ............... .
TECHNICAL PAPER
Intel FlashFile Memory-The Key to Diskless Mobile PCs ..................... : ..
6-1
6-2
6-42
6-80
6-110
6-140
6-170
6-185
6-215
6-232
6-234
CHAPTER 7
PCMCIA-ATA Flash Memory Drives
DATA SHEET
iFD005P2SAliFD010P2SA Flash Drive .. .' .................................. .
7-1
DESIGN GUIDE
Flash Drive Design Guide (for iFD005P2SAliFD01 OP2SA) ..................... .
7-46
SUPPORT TOOLS
Flash Memory Card and Flash Drive Evaluation Kit Product Brief ............... . 7-118
CHAPTER 8
Flash Automotive Components
DATA SHEETS
A28F400BR-T/B 4-Mbit (256K x 16, 512K x 8) SmartVoltage Boot Block Flash
Memory Family ........................................................ .
A28F400BX-T /B 4-Mbit (256K x 16,' 512K x 8) Boot Block Flash Memory Family .. .
A28F200BR-T /B 2-Mbit (128K x 16, 256K x 8) SmartVoltage Boot Block Flash
Memory Family ........................................................ .
A28F200BX-T /B 2-Mbit (128K x 16, 256K x 8) Boot Block Flash Memory Family .. .
A28F010 1024K (128K x 8) CMOS Flash Memory ............................ .
A28F512 512K (64K x 8) CMOS Flash Memory .............................. .
A28F256A 256K (32K x 8) CMOS Flash Memory ............................. .
CHAPTER 9
Process Engineering Reports
ER-20 ETOX II Flash Memory Technology ................................... .
ER-28 ETOX III Flash Memory Technology .................................. .
I
8-1
8-35
8-69
8-102
8-135
8-158
8-182
9-1
9-6
xiii
CONTENTS
Table of Contents (Continued)
ER-33 ETOX IV Flash Memory Technology: Insight to Intel's Fourth Generation
Process Innovation .......•.....••.......•..•.....•...•..•..•....•..••...
CHAPTER 10
Flash Memory SmartDle™ Products
DATA SHEETS
28F0101024K (128Kx8) Flash Memory .................. " .... '............. .
28F020 2048K (256K x 8) Flash Memory •..... ; .......•......................
28F008SA 8 Mbit (1 Mbit x8) Flash Memory ..............•...................
28F400BX-T 4 Mbit (256K x 16, 512K x 8) Boot Block Flash Memory .........•...
28F001 BX-T /B 1M (128K x 8) CMOS Flash Memory ..•..•. , •.....•.•..•..•.•..
CHAPTER 11
Article Reprints
AR-71 0 Flash Solid-State Drive with 6 MBs Read/Write Channel and Data
Compression .........•..................•..•.......•.........•......... "
AR-711 Flash: Big New in Storage? ......................................... .
AR-715 Flash Memory: Meeting the Needs of Mobile Computing .....•...•..••..
AR-716 Flash Memory for Top Speeds in Mobile Computing Applications ..'; ..•...
AR-717 The Many Facts of Flash Memory ...................................'.
AR-718 Standardizing on a Flash File System ............................... ..
AR-723 Interfacing BootBlock Flash Memories to the MCS 96 Family ........... .
xiv
9-19
10-1
. 10-9
10-17
10-25
10-33
11-1
11-4
11-8,
11-16
11-18
11-28
11-32
I
ALPHANUMERIC INDEX
Alphanumeric Index
28F001 BX-T128F001 BX-B 1M (128K x 8) CMOS Flash Memory .....................•.
28F001 BX-T IB 1 M (128K x 8) CMOS Flash Memory ...............•.................
28F008SA 8 Mbit (1 Mbit x 8) Flash Memory ...•.....................................
28F008SA 8-Mbit (1-Mbit x 8) FlashFile™ Memory (Extended Temperature Specifications
Included) .................................................................... .
28F008SA-L 8 Mbit (1 Mbit x 8) Flash Memory ...................................... .
28F010 1024K (128K x 8) CMOS Flash Memory ...................................•.
28F010 1024K (128K x 8) Flash Memory .......................................... ..
28F016SA 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFile Memory ..................•....•.
28F016SV 16-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFile Memory .......................•.
28F016XD 16-Mbit (1-Mbit x 16) DRAM - Interface Flash Memory ..................... .
28F016XS 16-Mbit (1-Mbit x 16, 2-Mbit x 8) Synchronous Flash Memory ............... .
28F020 2048K (256K x 8) CMOS Flash Memory ...................................•.
28F020 2048K (256K x 8) Flash Memory ........................................... .
28F200BL-T/B, 28F002BL-T/B 2-Mbit (128K x 16, 256K x 8) Low Power BootBlock Flash
Memory Family ............................................................... .
28F200BX-T IB, 28F002BX-T IB 2 Mbit (128K x 16, 256K x 8) Boot Block Flash Memory
Family ....................................................................... .
28F256A 256K (32K x8) CMOS Flash Memory ..................................... .
28F400BL-T/B, 28F004BL-T/B 4-Mbit (256K x 16, 512K x 8) Low Power Boot Block Flash
Memory Family ............................................................... .
28F400BX-T 4 Mbit (256K x 16, 512K x 8) Boot Block Flash Memory .................. .
28F400BX-T/B, 28F004BX-T/B 4 Mbit (256Kx 16, 512K x 8) Boot Block Flash Memory
Family ....................................................................... .
28F512 512K (64K x 8) CMOS Flash Memory ...................................... ..
2-Mbit (128K x 16, 256K x 8) SmartVoltage Boot Block Flash Memory Family (Extended
Temperature Specifications Included) ........................................... .
4-Mbit (256K x 16, 512K x 8) SmartVoltage Boot Block Flash Memory Family (Extended
Temperature Specifications Included) .......................................... ..
8-Mbit (512K x 16, 1-Mbitx 8) SmartVoltage Boot Block Flash Memory Family .......... .
A28F010 1024K (128K x 8) CMOS Flash Memory ........•...........................
, A28F200BR-T IB 2-Mbit (128K x 16, 256K x 8) SmartVoltage Boot Block Flash Memory
Family .................... ·.•..................................................
A28F200BX-T/B 2-Mbit (128K x 16, 256K x 8) Boot Block Flash Memory Family ....•....
: A28F256A 256K (32K x 8) CMOS Flash Memory .................................... .
A28F400BR-T/B 4-Mbit (256Kx 16, 512K x 8) SmartVoltage Boot Block Flash Memory
Family ....................................................................... .
A28F400BX-T/B 4-Mbit (256K x 16, 512K x 8) Boot Block Flash Memory Family ......•..
A28F512 512K (64K x 8) CMOS Flash Memory ..................................... .
AB-29 Flash Memory Applications in Laser Printers .................................. .
AB-58 28F016XD - Based SIMM Designs .......................................... .
AB-60 2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family Overview ............ .
AP-316 Using Flash Memory for In-System Reprogrammable Nonvolatile Storage ....... .
AP-325 Guide to First Generation Flash Memory Programming ........................ .
AP-341 Designing an Updatable BIOS Using Flash Memory .......................... .
AP-343 Solutions for High Density Applications Using Intel Flash Memory .............. .
AP-357 Power Supply Solutions for Flash Memory ................................. ..
AP-359 28F008SA Hardware Interfacing ........................................... .
AP-360 28F008SA Software Drivers ............................................... .
AP-361 Implementing the Integrated Registers of the Series 2 Flash Memory Card .... ~ ..
AP-362 Implementing Mobile PC DeSigns Using High Density FlashFile Components .... .
AP-363 Extended Flash Bios Concepts for Portable Computers .....................•..
I
4-307
10-33
10-17
3-443
3-476
5-33
10-1
3-359
3-303
3-50
3-3
5-1
10-9
4-265
4-218
5-92
4-174
10-25
4-124
5-64
4-68
4-13
4-1
8-135
8-69
8-102
8-182
8-1
8-35
8-158
2-71
3-104
4-349
5-117
5-162
4-357
6-185
2-22
3-551
3-562
6-215
3-585
4-400
xv
ALPHANUMERIC INDEX
Alphanumeric Index (Continued)
AP-364 28F008SA Automation and Algorithms .....•.....•.•..•.•...•...............
AP-374 Flash MemoryWrite Protection Techniques .........•..................•.....
AP-375 Upgrade Considerations from the 28F008SA to the 28F016SA ................. .
AP-377 16-Mbit Flash Product Family Software Drivers 28F016SA, 28F016SV, 28F016XS,
28F016XD ...........................................•......................•..
AP-378 System Optimization Using the Enhanced Features of the 28F016SA .......•...•
AP-384 Designing with the 28F016XD ....•..•..........•...........................
AP-393 28F016SV Compatibility with 28F016SA .................................... .
AP-398 Designing with the 28F016XS ....•..•..•....................•..............
AP-399 Implementing Mobile Intel486™ SX Microprocessor PC Designs Using FlashFile
Components .....•.....•.•..••.. '....•..•....... : .•.......• '.....•.....•........
AP-600 Performance Benefits and Power/Energy Savings of 28F016XS-Based System
Designs ................••......•.........•.....••.....•.•........•..•...•...•
AP-604 Using Intel's Boot Block Flash Memory Parameter Blocks to Replace EEPROM ...
AP-606 Interchangeability of Series 1, Series 2 and Series 2 + Flash Memory Cards .•....
AP-607 Multi-Site Layout Planning with Intel's FlashFile Components, Including ROM
Compatibility •..•. , .•......•.••.....•.. '......•....•.......•....•...•....••..•....
AR-71 0 Flash Solid-State Drive with 6 MBs Read/Write Channel and Data Compression.,
AR-711 Flash: Big New in Storage? ............................................... .
AR~715 Flash Memory: Meeting the Needs of Mobile Computing ...•...•........' ......•
AR-71 Flash Memory for Top Speeds in Mobile Computing Applications .........•.....
AR-717 The Many Facts of Flash Memory .......•..•.....•.•...........•....• ;...•..•
AR-718 Standardizing on a Flash File System ...................•...................
AR-723 Interfacing BootBlock Flash Memories to the MCS 96 Family ...•........•......
Boot Block Flash: The Next Generation White Paper .......................•.•..•....
DD28F032SA 32-Mbit (2-Mbit x 16; 4-Mbit x 8) FlashFile Memory ...••....•.....•....••
ER-20 ETOX II Flash Memory Technology .......•..................................
ER-24 Intel Flash Memory 28F256A, 28F512, 28F010, 28F020 ..•....••........•......
ER-26 The Intel 28F001 BX-T and 28F001 BX-B Flash Memories ...........•.........••
ER-27 The Intel 28F008SA Flash Memory .•..•..•..•.................•......•.......
ER-28 ETOX III Flash Memory Technology ......•..•......... ; ...•...•..•..•........
ER-29 The InteI2/4-Mbit Boot Block Flash Memory Family ............••..•...........
ER-33 ETOX IV Flash Memory Technology: Insight to Intel's Fourth Generation Process'
Innovation .•..•.......•..............•..•........................•....•........
Extended Temperature 28F016SA t6-Mbit (1-Mbit x 16, 2-Mbit x 8) FlashFile Memory .•..
Flash Drive Design Guide (for iFD005P2SAliFD01 OP2SA) ...........•..••............
Flash Memory Card and Flash Drive Evaluation Kit Product Brief ...................... .
Flash Memory Card and Flash Drive Evaluation Kit Product Brief .........•..•..........
Flash Memory Card and Flash Drive Evaluation Kit Product Brief .........•........•....
Flash Memory Customer Support .........•.............•...•....•.......•..•....•.
Flash Memory Overview ...•.•.... , •..•...•...........•...................•.......•
iFD005P2SAliFD010P2SA Flash Drive ....•..•..•.. , ..•......•......•...•..... ; ....
iMC001 FLKA 1-Megabyte Flash Memory Card .•......................•.....•........
iMC002FLKA 2-Mbyte Flash Memory Card ........................... ; •..•..•.......
iMC004FLKA 4-Megabyte Flash Memory Card .................•.......•..•..•..•....
Intel 28F016XD Embedded Flash RAM Product Brief ................................ .
Intel 28F016XS Embedded Flash RAM Product Brief ..........•..........•..•........
Intel FLASH Builder Software Product Brief ...•..•..•..•.......•............•........
Intel FlashFile Memory-The Key to Diskless Mobile pes •......•. : .................... .
Intel Memory Technologies ..........•................•...•......... : ........•....
Interfacing the 28F016XS to the Intel486 Microprocessor Family .........•..•.......•..
Interfacing the 28F016XS to the i960® Microprocessor Family .................... '.' .. .
a
xvi
3-640
2-64
3-654
3-667
3-722
3-142
3-533
3-112
3-743
3-172
4-341
6-170
3-504
11-1
11-4
11-8
11-16
11-18
11-28
11-32
4-466
3-257
9-1
5-184
4-422
3-783
9-6
4-437
9-19
3-403
7-46
7-118
6-232
2-16
2-7
2-1
7-1
6-140
6-110
6-80
3-2
3-1
2-20
6-234
1-1
3-238
3-196
I
ALPHANUMERIC INDEX
Alphanumeric Index (Continued)
Multi-APRO Programmer/Intel Support Version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Series 2 Flash Memory Cards iMC002FLSA/iMC004FLSAliMC01 OFLSAliMC020FLSA
(Extended Temperature Specifications Included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Series 2 + Flash Memory Card User's Manual Overview .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Series 2 + Flash Memory Cards 4-, 8-, 20- and 40-Megabyte ..........................
Small and Low Cost Power Supply Solution for Intel's Flash Memory Products . . . . . . . . . . .
Small Outline Package Guide Overview.............................................
Sprint PLUS4811ntei Support Version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
2-13
6-42
6-1
6-2
2-78
2-18
2-9
xvii
1
Memory Overview
I
INTEL MEMORY TECHNOLOGIES
Most of this handbook is devoted to techniques and
information to help you design and implement semiconductor memory in your application or system. In
this section, however, the memory chip itself will be
examined and the processing technology required to
turn a bare slice of silicon into high performance
. memory devices is described. The discussion has
been limited to the basics of MOS (Metal Oxide
Semiconductor) technologies as they are responsible for the majority of memory devices manufactured
at Intel.
There are three major MOS technology familiesPMOS, NMOS, and CMOS (Figure 1). They refer to
the channel type of the MOS transistors made with
the technology. PMOS technologies implement
p-channel transistors by diffusing p-type dopants
(usually boron) into an n-type silicon substrate. to
form the source and drain. P-channel is so named
because the channel is comprised of positively
charged carriers. NMOS technologies are similar,
but use n-type dopants (normally phosphorus or arsenic) to make n-channel transistors in p-type silicon
substrates. N-channel is so named because the
channel is comprised of negatively charged carriers.
CMOS or Complementary MOS technologies combine both p-channel and n-channel devices on the
same silicon. Either p- or n-type silicon substrates
can be used, however, deep areas of the opposite
doping type (called wells) must be defined to allow
fabrication of the complementary transistor type.
Most of the early semiconductor memory devices,
like Intel's pioneering 11 OS dynamic RAM and 1702
EPROM were made with PMOS technologies. As
higher speeds and greater densities were needed,
most new devices were implemented with NMOS.
This was due to the inherently higher speed of
n-channel charge carriers (electrons) in silicon along
with improved process margins. CMOS technology
has begun to see widespread commercial use in
memory devices. It allows for very low power devices used for battery operated or battery back-up applications. Historically, CMOS has been slower than
any NMOS device. Today, CMOS technology has
been improved to produce higher speed devices.
GATE
GATE
296102-2
296102-1
PMOS
NMOS
P·CHANNEL
DEVICE
N·CHANNEL
DEVICE
F.O.
P-SUBSTRATE
296102-3
CMOS
Figure 1. MOSProcess Cross-sections
I
1-1
INTEL MEMORY TECHNOLOGIES
In the following section,. the basic fabrication sequence for an HMOS circuit will be described.
HMOS is a high performance n-channel MOS process developed by Intel for 5V single supply circuits.
HMOS, and CHMOS, CHMOS-E (EPROM) and
ETOX (Flash Memory), along with their evolutionary
counterparts comprise the process family responsi.
ble for most of the memory components produced
by Intel today..
The MOS IC fabrication 'process begins with a slice
(or wafer) of single crystal silicon. Typically, it's 150
or 200 millimeter in diameter, about a half millimeter
thick, and uniformly doped p-type. The wafer is then
oxidized in a furnace at around 1000·C to grow a
thin layer of silicon dioxide (Si02) on the surface.
Silicon nitride is then deposited on the oxidized wafer in a gas phase chemical reactor. The wafer .is
now ready to receive the first pattern of what is to
become a many layered complex circuit. The pattern
is etched into the silicon nitride using a process .
known as photolithography, which will be described
in a later section. This first pattern (Figure 2) defines
the boundaries of the active regions of the IC, where
transistors, capacitors, diffused resistors, and first
level interconnects will be made.
r -_ _ _ ETCHED _ _ _"\.
Ie .Ni;'::~
~\
OXIDE";-
P-SUBSTRATE
296102-4
Figure 2. First Mask
The patterned and etched wafer is then implanted
with additional boron atoms accelerated at high energy. The boron will only reach the silicon substrate
where the nitride and oxide was etched away, providing areas doped strongly p-type that will electrically separate active areas. After implanting, the wafers are oxidized again and this time a thick oxide is
grown. The oxide only grows in the etched areas
due to silicon nitride's properties as an oxidation barrier. When the oxide is grown, some of the silicon
substrate is consumed and this gives a physical as
well as electrical isolation for adjacent devices as
can be seen in Figure 3..
. NITRIDE
P+
FIELD OX
P-SUBSTRATE
P+
Having fulfilled its purpose, the remaining silicon nitride layer is removed. A light oxide etch followstaking with it the underlying first oxide but leaving the
thick (field) oxide.
Now that the areas for active transistors have been
defined and isolated, the transistor types needed
can be determined. The wafer. is again patterned
and then if special characteristics (such as depletion
mode operation) are required, it is implanted with
dopant atoms. The energy and dose at which the
dopant atoms are implanted determines much of the
transistor's characteristics. The type of the dopant
provides for depletion mode (n-type) or enhancement mode (p"type) operation.
The transistor types defined, the gate oxide of the
.active tr~nsistors are grown in a high temperature
furnace. Special care must be taken to prevent contamination or inclusion of defects in the oxide and to
ensure uniform consistent thickness. This is important to provide precise, reliable device characteristics. The gate oxide layer is then masked and holes
are etched to provide for direct gate to diffusion
("buried") contacts where needed.
The wafers are now deposited with a layer of gate
material. This i!3 typically poly crystaline silicon
("poly") which is deposited in a gas phase chemical
reactor similar to that used for silicon nitride. The
poly is then doped (usually with phosphorus) to bring
the sheet resistance down to 10-20 n/square. This
layer is also used for circuit interconnects and if a
lower resistance is required, a refractory metal/polysilicon composite or refractory metal silicide can be
used instead. The gate layer is then patterned to
define the actual transistor gates and interconnect
paths (Figure 4).
296102-6
Figure 4. Post Gate Mask
The wafer is next diffused with n-type dopant (typi. cally arsenic or phosphorus) to form the source and
drain junctions. The transistor gate material acts as
a barrier to the dopant providing an undiffused channel self-aligned to the two junctions. The wafer is
then oxidized to seal the junctions from contamination with a layer of Si02 (Figure 5).
296102-5
Figure 3. Post Field Oxidation
1-2
I
INTEL MEMORY TECHNOLOGIES
+ Va
SECOND-LEVEL
POLYSILICON
FIELD
OXIDE
296102-7
Figure 5. Post Oxidation
P-SUBSTRATE
A thick layer glass is then deposited over the wafer
to provide for insulation and sufficiently low capacitance between the underlying layers and the metal
interconnect signals. (The lower the capacitance,
the higher the inherent speed of the device.) The
glass layer is then patterned with contact holes and
placed in a high temperature furnace. This furnace
step smooths the glass surface and rounds the contact edges to provide uniform metal coverage. Metal
(usually aluminum or aluminum/silicon) is then deposited on the wafer and the interconnect patterns
and external bonding pads are defined and etched
(Figure 6). The wafers then receive a low temperature (approximately 500°C) alloy that insures good
ohmic contact between the aluminum and diffusion
or poly.
EPROM/FLASH MEMORY CELL
296102-8
Figure 6. Complete Circuit (without passivation)
At this point the circuit is fully operational, however,
the top metal layer is very soft and easily damaged
by handling. The device is also susceptible to contamination or attack from moisture. To prevent this
the wafers are sealed with a passivation layer of silicon nitride or a silicon and phosphorus oxide compOSite. Patterning is done for the last time opening
up windows only over the bond pads where external
connections will be made.
This completes basic fabrication sequence for a single poly layer process. Double poly processes such
as those used for high density Dynamic RAMs,
EPROMs, flash memories, and EEPROMs follow the
same general process flow with the addition of gate,
poly deposition, doping, and interlayer dielectric process modules required for the additional poly layer
(Figure 7). These steps are performed right after the
active areas have been defined (Figure 3) providing
the capacitor or floating gate storage nodes on
those devices.
I
296102-9
Figure 7. Double Poly Structure
After fabrication is complete, the wafers are sent for
testing. Each circuit is tested individually under conditions designed to determine which circuits will operate properly both at low temperature and at conditions found in actual operation. Circuits that fail
these tests are noted to distinguish them from good
circuits. From here the wafers are sent for assembly
where they are sawed into individual circuits with a
paper-thin diamond blade. The noted circuits are
then separated out and the good circuits are sent on
for packaging.
Packages fall into two categories-hermetic and
non-hermetic. Hermetic packages are Cerdip, where
two ceramic halves are sealed with a glass fritt, or
ceramic with soldered metal lids. An example of hermetic package assembly is shown in Table 1. Nonhermetic packages are molded plastics.
The ceramic package has two parts, the base, which
has the leads and die (or circuit) cavity, and the metal lid. The base is placed on a heater block and a
metal alloy preform is inserted. The die is placed on
top of the preform which bonds it to the package.
Once attached, wires are bonded to the circuit and
then connected to the leads. Finally the package is
placed in a dry inert atmosphere and the lid is soldered on.
The cerdip package consists of a base, lead frame,
and lid. The base is placed on a heater block and
the lead frame placed on top. This sets the lead
frame in glass attached to the base. The die is then
attached and bonded to the leads. Finally the lid is
placed on the package and it is inserted in a seal
furnace where the glass on the two halves melt together making a hermetic package.
In a plastic package, the key component is the lead
frame. The die is attached to a pad on the lead
frame and bonded out to the leads with gold wires.
The frame then goes to an injection molding machine and the package is formed around the lead
frame. After mold the excess plastic is removed and
the leads trimmed.
1-3
INTEL MEMORY TECHNOLOGIES
After assembly, the individual circuits are retested at
an elevated operating temperature to assure critical
operating parameters and separated according to
speed and power consumption into individual specification groups. The finished circuits are marked and
then readied for shipment.
The basic process flow described above may make
VLSI device fabrication sound straightforward, however, there are actually hundreds of individual operations that must be performed correctly to complete a
working circuit. It usually takes well over two months
to complete all these operations and the many tests
and measurements involved throughout the manufacturing process. Many of these details are responsible for ensuring the performance, quality, and reliability you expect from Intel products. The following
sections will discuss the technology underlying each
of 'the major process elements mentioned in the basic pru:'ess flow.
PHOTOLITHOGRAPHY
The photo or masking technology is the most important part of the manufacturing flow if for no other
reason than the number of times it is applied to each
wafer. The manufacturing process gets more complex in order to make smaller and higher performance circuits. As this happens the number of masking steps increases, the features get smaller, and
the tolerance required becomes tighter. This is
largely because the minimum size of individual pattern elements determine the size of the whole circuit, effecting its cost and limiting its potential complexity. Early MOS IC's used minimum geometries
(lines or spaces) of 8-10 microns (1 micron = 10- 6
meter "" 1/25,000 inch). The n-channel processes
of the mid 1970's brought this down to approximately 5 microns, and today minimum geometries of 0.8
and even 0.6 microns are in production. This dra-
Table 1. Typical Hermetic Package Assembly
Flow
Process/Materials
Typical Item
Frequency
Criteria
Waler
Die saw wafer break
I
Die wash and plate
Die visual inspection
......()
Passivation, metal
On6.
Wet out
4 x/operator/shift
0/11 LTPD=20%
Orientation. lead
dressing, etc.
4 x/operator/
machine/shift
OAgate
Ali previous items
every Jot
1/129. LTPD_3%
Seal and Mark
(Process monitor)
Cap align. glass
integrity, moisture
4 x /furnace/shift
0115.
lOx to mil std.
883cond. C
1111, LTPD = 20%
Die attach
(Process monitor)
Post die attach visual
Wire bond
(Process monitor)
100% devices
Temp cycle
o.-
4
LTPD~5%
100% 01 devices
Post bond inspection
......()
100% oldie
Every lot
OA gate
Hermeticity check
(Process monitor)
F/G leak
100% devices
Lead Trim
(Process monitor)
Burrs, etc .. (visual)
Fine leak
4 x Istation/shift
2 x Istation/shift
External visual
Solder voids, cap
alignment, etc.
100% devices
OAgate
Ali previous items
Ali lots
Class test
(Process monitor)
Run standards
(good and reject)
Calibrate every
system using
Every 48 hrs.
LTPD~
15%
OilS, LTPD=15%
11129, LTPD=3%
11129, LTPD=3%
"autover" program
2.
_
Mark and Pack
FlnalOA
(See attached)
296102-11
NOTES:
1. Units for assembly reliability monitor.
2. Units for product reliability monitor.
1-4
I
INTEL MEMORY TECHNOLOGIES
matic reduction in feature size was achieved using
the newer high resolution photo resists and optimizing their processing to match improved optical printing systems.
A second major factor in determining the size of the
circuit is the registration or overlay error. This is how
accurately one pattern can be aligned to a previous
one. Design rules require that space be left in all
directions according to the overlay error so that unrelated patterns do not overlap or interfere with one
another. As the error space increases the circuit size
increases dramatically. Only a few years ago standard alignment tolerances were ~ ± 2 microns; now
advanced Intel processes have reduced this dramatically due mostly to the use of advanced projection
and step and repeat exposure equipment.
The wafer that is ready for patterning must go
through many individual steps before that pattern is
complete. First the wafer is baked to remove moisture from its surface and is then treated with chemicals that ensure good resist adhesion. The thick
photoresist liquid is then applied and the wafer is
spun flat to give a uniform coating, critical for high
resolution. The wafer is baked at a low temperature
to solidify the resist into gel. It is then exposed with a
machine that aligns a mask with the new pattern on
it to a previously defined layer. The photo-resist will
replicate this pattern on the wafer.
Negative working resists are polymerized by the light
and the unexposed resist can be rinsed off with solvents. Positive working resists use photosensitive
polymerization inhibitors that allow a chemically reactive developer to remove the exposed areas. The
positive resists require much tighter control of exposure and development but yield higher resolution
patterns than negative resistance systems.
The wafer is now ready to have its pattern etched.
The etch procedure is specialized for each layer to
be etched. Wet chemical etch ants such as hydrofluoric acid for silicon oxide or phosphoric acid for
aluminum are often used for this. The need for
smaller features and tighter control of etched dimensions is increasing the use of plasma etching in fabrication. Here a reactor is run with a partial vacuum
into which etchant gases are introduced and an
electrical field is applied. This yields a reactive plasma which etches the required layer.
The wafer is now ready for the next process step. Its
single journey through the masking process required
the careful engineering of mechaniCS, optics, organic chemistry, inorganic chemistry, plasma chemistry,
physics,- and electronics.
I
DIFFUSION
The picture of clean room garbed operators tending
furnace tubes glowing cherry red is the one most
often associated with IC fabrication. These furnace
operations are referred to collectively as diffusion
because they employ the principle of sold state diffusion of matter to accomplish their results. In MOS
processing, there are three main types of diffusion
operations: predeps, drives, and oxidations.
Predeposition, or "predep," is an operation where a
dopant is introduced into the furnace from a solid,
liquid, or gaseous source and at the furnace temperature (usually 900°C-1200°C) a saturated solution is
formed at the silicon surface. The temperature of the
furnace, the dopant atom, and rate of introduction
are all engineered to give a specific dose of the dopant on the wafer. Once this is completed the wafer is
given a drive cycle where the dopant left at the surface by the predep is driven into the wafer by high
temperatures. These are generally at different temperatures than the predeps and are designed to give
the required junction depth and concentration profile.
Oxidation, the third category, is used at many steps
of the process as was shown in the process flow.
The temperature and oxidizing ambient can range
from 800°C to 1200°C and from pure oxygen to mixtures of oxygen and other gases to steam depending
on the type of oxide required. Gate oxides require
high dielectric breakdown strength for thin layers
(between 0.01 and 0.1 micron) and very tight control
over thickness (typically ± 0.005 micron or less than
± 115,000,000 inch), while isolation oxides need to
be quite thick and because of this their dielectric
breakdown strength per unit thickness is much less
important.
The properties of the diffused junctions and oxides
are key to the performance and reliability of the finished device so the diffusion operations must be extremely well controlled for accuracy, consistency
and purity.
ION IMPLANT
Intel's high performance products require such high
accuracy and repeatability of dopant control that
even the high degree of control provided by diffusion
operations is inadequate. However, this limitation
has been overcome by replacing critical predeps
with ion implantation. In ion implantation, ionized
dopant atoms are accelerated by an electric field
1-5
INTEL MEMORY TECHNOLOGIES
and implanted directly into the wafer. The acceleration potential determines the depth to which the
dopant is implanted.
The charged ions can be counted electrically during
implantation giving very tight control over dose. The
ion implanters used to perform this are a combination of high vacuum system, ion source, mass spectrometer, linear accelerator, ultra high resolution current integrator, and ion beam scanner. You can see
that this important technique requires a host of sophisticated technologies to support it.
THIN FILMS
Thin film depositions make up most of the features
on the completed circuit. They include the silicon ni·
tride for defining isolation, polysilicon for the gate
and interconnections, the glass for interlayer dielectric, metal for interconnection and external connections, and. passivation layers. Thin film depositions
are done by two main methods: physical deposition
and chemical vapor deposition. Physical deposition
is most common for deposition metal. Physical depositions are performed in a vacuum and are accomplished by vaporizing the metal with a high energy
electron beam and redepositing it on the wafer or by
sputtering it from a target to the wafer under an elec-,
tric field.
Chemical vapor deposition can be done at atmospheric pressure or under a moderate vacuum. This
type of deposition is performed when chemical gas-
1·6
es react at the wafer surface and deposit a solid film
of the reaction product. These reactors, unlike their
general industrial counterparts, must be controlled
on a microscale to provide exact chemical and physical properties for ,thin films such as silicon dioxide,
silicon nitride, and polysilicon.
The fabrication of modern memory devices is a long,
complex process where each step must be monitored, measured and verified. Developing a totally
new manufacturing process for each new product or
even product line takes a long time and involves significant risk. Because of this, Intel has developed
process families, such as HMOS, on which a wide
variety of devices can be made. These families are
scalable so that circuits need not be totally redesigned to meet your needs for higher performance.(1) They are evolutionary so that development
time of new processes and products can be reduced
without compromising Intel's commitment to consistency, quality, and reliability.
The manufacture of today's MOS memory devices
requires a tremendous variety of technologies and
manufacturing techniques, many more than could be
mentioned here. Each requires a team of experts to
design, optimize, control and maintain it. All these
people and thousands of others involved in engineering, design, testing and production stand behind
Intel's products.
(1)R. Pashley, K. Kokkonen, E. Boleky, R. Jecmen, S. Liu,
and W. Owen, "H·MOS Scales Traditional Devices to High·
er Performance Level," Electronics, August 18, 1977.
I
2
Flash Memory Overview
and Support Tools
I
intel·
Flash Memory Overview
The ideal memory system optimizes density, nonvolatility, fast readability and cost effectiveness. While traditional memory technologies may individually exhibit
one or more of these desired characteristics, no single
memory technology has achieved all of them without
major tradeoffs-until the introduction of Intel Flash
Memory.
ROM (read-only memory) is a mature, high density, nonvolatile, reliable and low cost memory technology widely used in PC and embedded applications. Once it is manufactured however, the
contents of a ROM can never be altered. Additionally, initial ROM programming involves a timeconsuming mask development process that requires
stable code and is most cost-effective in high volumes.
WHAT IS FLASH MEMORY?
Introduced by Intel in 1988, ETOX flash memory is a
high-density, truly nonvolatile and high performance
read-write memory solution also characterized by low
power consumption and extreme ruggedness and high
reliability. The cost trend of Intel Flash Memory components continues to decline sharply due to: (1) manufacturing economies inherent in ETOX, Intel's industry-standard EPROM-based flash technology, (2)
increases in memory density, and (3) rapid growth in
production volume.
A comparison between Intel Flash Memory and other
solid-state memory technologies underscores the fact
that flash offers a design solution with distinct advantages. These advantages are key to future product differentiation for many applications requiring firmware
updates or compact mass storage (Figure 1).
Easy updatability makes flash memory clearly more
flexible than ROM in most applications.
-
SRAM (static random-access memory) is a highspeed, reprogrammable memory technology which
is limited by its volatility and relatively low density.
As a volatile memory technology, SRAM requires
constant power to retain its contents. Built-in battery backup is therefore required when the main
power source is turned off. Since battery failure is
an inevitable fact of life, SRAM data loss is an everpresent danger. Additionally, SRAM requires four
to six transistors to store one bit of information.
This becomes a significant limitation in developing
higher densities-effectively keeping SRAM cost
relatively high.
Figure 1. Intel Flash Memory vs Traditional Memory Technologies
Memory
One
In-System Code
Hands
Inherently
Byte
High
Low
Blocking
off
NonTransistor
Reand Data
Density Power
Alterable
Volatile
Cell
Writable Storage
Updates
Flash
",
+ Battery
DRAM + Disk
",
",
",
SRAM
",
EEPROM
",
OTP/EPROM
",
",
",
",
Masked ROM
",
",
",
",
",
",
",
",
",
",
",
",
",
",
",
",
",
",
",
",
",
",
",
",
OMS-DOS and Windows are registered trademarks of Microsoft Corporation.
November 1992
Order Number: 296101-004
2-1
FLASH MEMORY OVERVIEW
In contrast, Intel flash memory is inherently nonvolatile, and the single transistor cell design of Intel's
ET?X manufacturing process is extremely scalable, alI?wmg the development of continuously higher densities and steady cost improvement over SRAM
(Figure 2).
...
..3
N
en
cl
(.)
~
0
EEPROM
1
2
15/L
38/L
0.1%
5%
Transistors
Cell Size
(1-Micro Lithogrpahy)
CyCling Features
.....
Intel
ETOXFlash
Figure 3
1000
500
DRAM (dynamic random access memory) is a volatile memory known for its density and low cost.
Because of its volatility, however, it requires not
only a constant power supply to retain data, but
also a~ archival storage technology, such as disk, to
back It up.
200
100
50
20
10
i!'l
:z
Partnered with hard disks for permanent mass storage,
DRAM technology has provided a low-cost, yet space
and power-hungry solution for today's PCs.
2.0
1.5
1.2
1.0
O.S 0,7 0.6 0.5
MINIMUM FEATURE SIZE. (}')
296101-1
Figure 2
-
EPROM (electrically programmable read-only
memory) is a mature, high-density, nonvolatile
technology which provides a degree of updatability
not found in ROM. An OEM may program
EPRO~ as needed to accommodate code changes
or varymg manufacturing unit quantities. Once programmed, however, the EPROM may only be
erased by removing it from the system and then
exposing the memory component to ultraviolet
light-an impractical and time-consuming procedure for many OEMs and a virtually impossible
task for end-users.
Unlike EPROM, flash memory is electrically re-writable within the host system, making it a much more
flexible and easier to use alternative. Flash memory offers OEMs not only high density and nonvolatility, but
higher functionality and the ability to differentiate their
systems.
.
EEPROM (electrically erasable programmable
read-only memory) is nonvolatile and electrically
byte-erasable. Such byte-alterability is needed in
certain applications but involves a more complex
cell structure, and significant trade-offs in terms of
limited density, lower reliability and higher cost,
making it unsuitable as a mainstream memory.
Unlike EEPROM, Intel flash memory technology utilizes ~. one-transistor cell, allowing higher densities,
scalabIlity, lower cost, and higher reliability, while taking advantage. of in-system, electrical erasability (Figure 3).
2-2
With ETOX process technology, Intel manufactures a
flash memory cell that is 30% smaller than equivalent
DRAM cells. Flash memory's scalability offers a price
advantage as well, keeping price parity with DRAM,
and also becoming more attractive as a hard disk replacement in portable systems as densities grow and
costs· decline.
Intel flash memory combines advantages from each of
.memory technologies. In embedded memory applIcatIOns, flash memory provides higher-performance
and more flexibility than ROM and EPROM, while
providing higher density and better cost effectiveness
than battery-backed SRAM and EEPROM. Moreover,
the true nonvolatility and low power consumption
charact~ristics of flash memory make it a compelling
.
alternatIve to DRAM in many applications.
th~e
ETOX III TECHNOLOGY
ynlike other approaches to flash memory, Intel ETOX
IS a proven technology. As its name suggests, ETOX
(or "EPROM tunnel oxide") technology evolved from
EPROM. With 95% process compatibility with
EPROM, E:rOX taps experience gained from a mature
high-volume manufacturing base pioneered by Intel in
the 1970s.
Data retention and lifetime reliability statistics for
ETOX III flash are equivalent to those of EPROM.
Representing the third generation of Intel flash memory. technology, the ETOX III O.8/L process provides
< 100 FITS (failures in time) @ 55°C in a specification
t~~t de~iv~rs 100,000 write cycles per block. This capabIlIty sIgnIficantly exceeds the cycling requirements of
even the most demanding applications.
I
FLASH MEMORY OVERVIEW
For example, code storage for embedded control programs used in standard computer applications is infrequently updated. Twenty-year system lifetimes may require fewer than 100 rewrites. Even routinely-changed
data tables (used in navigational computers and black
box controllers) only require about 1,000 write cycles
over a 20-year period. The most demanding flash memory application of all, archival data storage in PC applications, typically requires about 5,000 write cycles in 20
years.
ETOX flash memory's simple single-transistor cell
structure makes it smaller than other flash cells, allowing designers to create highly integrated systems which
are more reliable and cost-effective than those based on
more complex and less mature flash technologies. The
inherent scalability of ETOX III Flash Memory and
high-volume manufacturing is enabling a corresponding downtrend in flash cost.
Flash memory has added a new dimension to nonvolatile memory applications. Embedded systems, such as
PC BIOS, hard disk drive controllers and cellular telephone applications take advantage of the easy update
capability, high density and high performance of Intel
Flash Memory. Today's new generation of portable
computers require the optimum combination of performance, size, weight, low power and shock resistance.
Whether implemented in memory cards, solid state
disks or at the component level, Intel's Flash Memories
are also enabling a whole new generation of mobile
computers.
IMPLEMENTING INTEL FLASH
MEMORY
Today, Intel continues to serve both updatable nonvolatile memory applications as well as the rapidly emerging solid-state mass storage applications with flash
memory solutions tailored to meet the needs of these
markets.
Updatable Code Storage
Code and data storage comprise the updatable nonvolatile memory applications that require high performance, high density, and easy update capability. Because
these applications are not updated as frequently as solid-state mass storage applications, erase/write cycles
are not as critical as integration and performance requirements. This application segment is served effectively with full chip-erase or Boot Block products.
Intel's 28FooIBX 1 Mbit Boot Block flash component,
featuring a sectored architecture, has been widely accepted in embedded code storage applications, particularly in PC BIOS and cellular communications. By
adopting Boot Block for their products, over 20 PC
manufacturers have gained added flexibility and the
ability to differentiate in a highly competitive market.
End users also benefit from the ability to upgrade BIOS
software quickly and securely. The blocked architecture allows the OEM to store critical system code securely in the lockable "boot block" of the device that
can minimally bring up the system and download to
other locations of the device to initialize the system.
The hardware boot locking feature guarantees that even
if the power is disrupted during a BIOS update, the
system will be able to recover immediately.
In response to customer requests for speed, density, low
power, surface-mount options and an industry-standard
upgrade path for portable computing and telecommunications, Intel more recently introduced the 2 Mbit
28F2ooBX and 4 Mbit 28F400BX Boot Block products.
These products offer 60 ns performance; two surface
mount packages: 4O-lead TSOP (X8 only) and 44-lead
PSOP; and a proprietary Boot Block architecture similar to the 1 Mbit Boot Block device. The Boot Block
stores the code necessary to initialize the system, while
parameter blocks can be used to store manufacturing
product code, setup parameters, and frequently updated code such as system diagnostics. The main operating
code is stored in the main blocks. Both devices are
available in a x16/x8 ROM-compatible pin-out in
44-lead PSOP surface mount packaging. These pinouts
and packages allow an easy upgrade from 2 Mb to
4 Mb, since only one address is added to the 4 Mb
device.
Solid-State Mass Storage
This major application segment requires very high density memory, automated programming and high-performance erase/write capability at a very low cost per
bit. Erasing and writing portions of the code or data is
much more frequent in solid-state mass storage than in
updatable firmware applications.
Intel's symmetrically blocked 8 Mbit 28FOO8SA FlashFile™ memory is the highest density nonvolatile read/
write solution for solid-state mass storage. What's
more, it is the first flash memory device optimized for
solid-state storage of software and data files.
The 28F008SA is packaged in an advanced 4O-lead
TSOP (thin, small outline package) or 44-lead PSOP
(plastic SOP) to provide the extremely small form factor required for today's handheld, pen-based and sub-
• Based on 10 MB card design, 5,000 cycle yields 50,000 MB of stored
data, which far exceeds most usage environments and file system
methodologies.
I
2-3
FLASH MEMORY OVERVIEW
notebook portable computers. The compactness of an
8 Mbit device in a TSOP package allows for high-density flash arrays to be included both on a system motherboard for direct execution of user programs or operating systems, as well as memory cards for transportable
program and me storage.
ty, size and performance of their systems, as well as the
disk media themselves.
Yet the disk drive is an electro-mechanical system with
inherent limitations. Any mechanical hardware is much
more vulnerable than solid state semiconductor technology to the shock, vibration, and impurities that portable PCS encounter during normal use. Hard disk
drives can typically withstand up to lOGs of operating
shock; Intel FlashFile memory, with no moving parts,
can withstand as much as loooGs. Additionally, Intel's
Series 2 Memory Cards feature approximately 1.6 million hours mean time between failure (MTBF). Such
endurance and reliability is essential for many of today's truly mobile handheld palmtop and notebook
sized PCS, particularly within applications requiring extreme data integrity.
Memory Cards
Intel's family of flash memory cards provides the most
reliable and rugged form of removable memory media.
High density, true nonvolatility, rewrite flexibility, and
proven cost effectiveness make Intel Series I Flash
Memory Cards the ideal medium for storing and updating application code as well as capturing data.
For me storage applications that require high performance, ruggedness, long battery life, small size and light
weight, Intel's Series 2 Flash Memory Cards in
4-Mbyte, lO-Mbyte and 20-Mbyte densities provide the
best solution. Based on Intel's 8-Mbit FlashFile memory components, the Series 2 card's block-erase functionality and high density take full advantage of flash filing
systems like Microsoft·'s Flash File System software to
provide full disk emulation in the form of removable,
nonvolatile storage. The cards conform to the
PCMCIA 2.0/JEIDA 4.1 68-pin standards and are
compatible with Intel's Exchangeable Card Architecture (ExCATM) to ensure system-to-system interoperabililty.
Power consumption is another major consideration for
today's mobile PC designer and user. The drive typically requires anywhere from 3 watts to as many as
8 watts of power to run-which means rapid drain of
the system's batteries. Compare this to flash memory in
a hard disk configuration. It consumes less than one
two-hundredth the average power of a comparable
magnetic disk drive based on the typical user model. At
the chip level, the 8 Mbit FlashFile Memory component has a DEEP POWERDOWN mode that reduces
. power consumption to less thfUl 0.2 ,..,A.
THE IMPETUS BEHIND THE "SOLIDSTATE" DISK
Because the disk-based PC is so prevalent and eminently familiar to both designers and end-users, many of
today's portable systems still rely on it as their primary
medium. At the same time, disk drive manufacturers
have made great strides toward improving the reliabili-
Average Seek Time
Latency
Data Transfer Rate
Read:
Write:
Total Time to Access
(1 Kbyte File)
...:c
Additional shortcomings of disk drives are their size,
weight and floor costs. Magnetic drives do not scale
well, that is, it becomes increasingly difficult to improve or even retain density as platter size shrinks.
Thus, every reduction in drive size requires complete
retooling and costly learning. Also, the complex controller circuitry provides a price floor under which
magnetic drives cannot drop. Since flash is scalable, at
some point in the near future, small magnetic drives are
likely to become more expensive per Mbyte than flash
cards and are certain to have less capacity.
Disk/DRAM
Flash
28.0ms
0
8.3ms
0
8 Mbits/sec.
8 Mbits/sec.
... Now Read from RAM
106.7 Mbits/sec.
1 Mbitlsec.
Direct Processor Access
37.3 ms
O.077ms
Figure 4
2-4
I
FLASH MEMORY OVERVIEW
From a performance standpoint, disk-based systems
still require some form of supplementary memory that
is directly executable. TypicalIy, DRAM is used for executable code storage and data manipulation. Data
from the disk is downloadable into the DRAM cache
before users can access the information. Then when a
"save" operation is desired, the data is uploaded from
DRAM back into the disk. This download/upload process slows down system throughput while the redundant memory media produce even more system overhead in the form of added space, power consumption
and weight (Figure 4).
Today's PCs are typically configured with
4 Mbytes-8 Mbytes of DRAM backed up by at least a
4O-Mbyte disk. FlashFile memory fulIy supports this
system configuration when used simply as a maguetic
drive replacement: Instructions and data are still
swapped to DRAM, but at a faster rate. Plus execution
speed can be enhanced if the DRAM is replaced with
SRAM.
In the solid-state computer, the "DRAM + magnetic
hard drive" is replaced by a "flash memory +
SRAM". The key to this architecture is the ability to
eXecute-in-Place (XIP). Program instructions stored in
flash memory are read directly by the processor. Results are written directly to the flash memory. Compute-intensive operations that require the fastest memory access and byte-alterability can use high-speed
SRAM or pseudo SRAM. Some of the system DRAM
can be replaced by low-cost flash and a smalJ part of
the DRAM can be replaced by SRAM. The flash memory space is made even more storage efficient through
the use of compression techniques which may offer up
to 2:1 compression.
SOFTWARE DEVELOPMENTS
POSITION FLASH FOR PORTABLE
APPLICATIONS
The majority of today's portable computers and supporting software programmers are designed to run using Microsoft's MS-DOS' disk operating system. MSDOS was developed to alIow broad-based compatibility
between systems and software and to optimize the sectoring scheme inherent to disk technology.
SpecificalIy, two recent developments alIow this
achievement: DOS in ROM-executable form (DOS was
formerly designed to be stored on disk and then downloaded to/executed out of RAM); and a file system designed for flash memory technology that allows the devices to erase blocks of memory instead of the whole
chip.
ROM-executable DOS provides several benefits to both
system manufacturers and ultimately end users. First,
since most of the operating system is composed of fixed
code, the amount of system RAM required to execute
DOS is reduced from 5DK to 15K, thereby conserving
system space and power. Secondly, DOS can now be
permanently stored in and executed from a single
ROM-type of device-flash memory-so systems come
ready to run. Lastly, users enjoy "instant on" performance since the traditional disk-to-DRAM boot function
and software downloading steps are eliminated.
For example, by storing application software and operating system code in a Resident Flash Array (RFA),
users enjoy virtually instant-on performance and rapid
in-place code execution. An RFA also protects against
software obsolescence because it is in-system updatable.
Resident software, stored in flash rather than disk, extends battery life and increases system reliability.
Since erasing and writing data to flash memory is a
distinctly different operation than rewriting information to a disk, new software techniques were necessary
to allow flash to emulate disk functionality. File management software like Microsoft"s Flash File System
(FFS) alIows Intel's Flash Memory components and
flash cards to emulate the file storage capabilities of
disk. Microsoft's~FS transparently handles data swaps
between flash blocks similar to the way MS-DOS handles swaps between disk sectors. Under FFS, the user
may input a MS-DOS or Windows' command without
regard for whether a flash memory or magnetic disk is
instalIed in the system. The FFS also employs wear-leveling algorithms that prevent any block from being cycled excessively, thus assuring millions of hours of reliability. Flash filing systems make the management of
flash memory devices completely transparent to the
user.
CONCLUSION
Intel's Flash Memory, based on a block-erase architecture, divides the flash memory into segments that are
loosely analogous to the zones recognized in MS-DOS.
Thanks to recent software developments, flash memory
can effectively serve as the main memory within portable computers, providing user functions virtually identical to, and even improved over, those of disk-based systems.
I
Intel Flash Memory presents an entirely new memory
technology alternative. As a high-density, nonvolatile
read/write technology, it is exceptionalIy welI-suited to
serve as a solid-state disk or a cost-effective and highly
reliable replacement for DRAMs and battery-backed
static RAMs. Its inherent advantages over these technologies make it particularly useful in portable systems
that require the utmost in low power, compact size, and
ruggedness while maintaining high performance and
full functionality.
2-5
FLASH MEMORY OVERVIEW
Intel Flash Memory offers:
• Inherent Nonvolatility: Unlike static RAMs, no
backup battery is required to ensure data retention.
In contrast to DRAMs, flash requires no disk to
provide backup storage of data, programs or files.
• Cost·Effective High Density: Today, Intel flash
memories cost about the same as DRAMs and
about one fourth of SRAMs on a per·bit basis. The
broad acceptance of flash is driving manufacturing
volumes' up and costs down at an unprecedented
rate, allowing flash to soon compete on a cost basis
even with disk drive within the notebook, sub-note·
book and palmtop markets.
• Solid·State Performance: Because it is a semiconductor technology, flash memory consumes much
less power, is much lighter in weight and is smaller
and more shock-resistant and reliable than disk
drives. Mobile computers no longer have to drain
the battery to run a disk drive motor or accommodate the disk assembly'S added bulk and weight.
Now users no longer have to be threatened with the
possibility of losing their data after a disk crash
when conditions become unusually rough.
• Direct Execution: Since no disk-to-DRAM download step, seek or latency times are incurred with
2-6
•
•
•
•
flash memory, users enjoy significantly higher speed
program and file access, as well as systems that tum
on instantly to wherever the user left off.
Easy Updatability: Unlike other nonvolatile memory technologies-ROM that can never be altered after it is manufactured or EPROM that can only be
erased by removing itfrom the system and exposing
it to ultraviolet light-flash can be erased and reprogrammed electrically while resident in the host system.
Software Compatibility: With Flash File System
software and ROM-executable versions of the disk
operating system (DOS), complete software compatibility between a user's desktop and portable system
is ensured.
Exchangeable Card Architecture (ExCATM):
Through Intel's ExCA card interface standard, Intel's flash memory cards meet all specifications of
PCMCIA 2.0,en~uring interchangeability between a
host of PCMCIA-compatible systems.
Family of Products: Intel Flash Memory products
are currently available in component densities up to
8 Mbits, and in 4-Mbyte, lO-Mbyte and 20-Mbyte
memory cards. Additionally, Intel offers Boot Block
devices in densities up to 4 Mbits.
I
intel·
FLASH MEMORY CUSTOMER SUPPORT
New/Updated Technical Literature
By the time you receive this databook, new information
may be available for Intel's Flash Memory products.
This could include advanced information on new devices or important new applications information or datasheet addendums for those described in this databook.
Call 1-800-548-4725 (US and Canada) for the newest
information on Intel Flash Memories. This service is
available from 7am to 7pm Central Standard Time.
Contact your local distributor or sales office if outside
US or Canada.
Applications Support Hotline
The Technical Hotline is staffed by applications personnel during normal business hours-5am to 5pm Pacific
Standard Time. Toll free number 1-800-628-8686 is
available for US and Canada; 916-356-7599 is also
available for those who cannot access the toll free number.
Additionally, assistance can be obtained through your
local InteVdistributor sales office. You can leave a message during off hours or when applications personnel
are already handling calls.
Intel's Application Bulletin Board
System (BBS)
Intel's Application Support BBS provides the designer,
developer or OEM using or contemplating the use of
Intel components, systems or software with the latest
information on Intel's product line.
The Intel Application Support BBS is duplicated at two
sites worldwide, and can be accessed at 916-356-3600
(Folsom, California USA) or 44-793-496340 (Swindon,
England UK). Upon calling your are prompted
through an automatic registration process. You then
have immediate access to the downloadable mes area.
For non-urgent requests or technical assistance you
may leave a message to one of our System Operators
(SysOps). Online forums among users are not supported. In North America you may also call our tollfree line
December 1994
Order Number: 297539-001
at 1-800-897-2536. This limited access allows you to
download the current BBS master file list (generated
nightly), FaxBACK* catalogs, our Windows-based
FaxFind keyword search utility and the BBS user's
guide. The BBS supports baud rates up to 19.2 Baud;
settings are 8 data bits, No parity and I stop bit.
'NOTE:
Other brands and names are the property of their respective owners.
The eight flash memory me areas are:
•
•
•
•
•
•
•
•
Bulk Erase
Boot Block
FlashFile™
Flash Card
Flash Drive
Tools
FlashFile™ Layout: 8/16/32 Mbit
Boot Block Layout: 2/4 Mbit
These file areas include the following types of support:
• Software drivers
• 3rd-party programming support, tools, adapters and
vendor information
• ReaderIWriter support for Flash Memory Cards
and ATA Flash Drives
• Orcad and Workview schematic symbols
• Timing Designer mes
• FLASHBuilder 16-Mb FlashFile Memory Windows-based designlhelp me
• Information (document) navigator utility
• Design recommendations
• Component flexible layout mes
• Presentations
• Socket information
• Data sheet addendums
• Errata notifications
2-7
FLASH MEMORY CUSTOMER SUPPORT
FaxBACK System
Available 24 hours a day. Order documents by phone
for prompt delivery to your fax machine.
Dial toll free number 1-800-628-2283 if inside US or
Canada (or 916-356-3105, which also supports users
not having tollfree access), and the user-friendly system
will prompt you along. In Europe, dial 44793-49-6646.
Have your fax number ready.
Each document is assigned an order number. All documents for a particular product group (e.g., Flash Memory, Multimedia, PCI ... ) are listed in their subject
catalog. First time users should order the appropriate
catalog(s) for a complete reference of available information; this is down by following the automated system's
voice prompts and selecting catalog order. Document
orders are made by selecting document order at the
voice prompt; you are allowed up to five documents per
call.
Rely on FaxBACK for the following types of information about flash memory products:
• Product briefs and literature references
• Press releases and new product announcements
• Datasheet addendums
• Technical support material and references
• Product evaluation kits
• 3rd-party programming support, tools, adapters and
vendor information,
2-8
•
•
•
•
System/compatibility validation reports
Application articles
Design recommendations
Errata notifications
Document Highlight: #2204 is the all-inclusive "Flash
Memory Technical Support Summary". This document
summarizes available literature and order numbers,
FaxBACK and BBS references, evaluation kits and
support tools/information, programmer and reader/
writer support and vendor contact references, programming adapter information and vendors, prototyping
and bum-in/test socket vendors and information, 12Vconvertor vendors, PCMCIA development tools/compliance testing/general support contacts, PCMCIA
card-connector vendors, FFS vendors, disk emulator
vendors and BIOS vendors.
FaxFind
A Windows-based utility to search all FaxBACK documents-and BBS files via keyword entry. Available on
the Applications BBS under. the Bulletins menu -or in
the FaxBACK area selected via File Locator. Also
available via the dedicated FaxFind number:
1-800-897-2536.
I
SPRINT PLUS48
SPRINT PLUS48
Intel Support Version
Universal Device
Programmer
General Description
The PLUS48 is the newest Universal Device Programmer· in the
Sprint family. Complete with 48
universal pin drivers, it sets a new
standard for low-cost programmers
in this class. A specially-configured
version supports all Intel Flash,
Microcontroller, PLD, EPROM
and EEPROM devices at a very attractive price. Controllable lockout
of standard software libraries allow
you to purchase the Intel support
you need today, with the capability
to switch to full industry support
later.
Full custom ASIC pin drivers were
developed enabling the programming and testing of new high-speed
CMOS devices. A compact design
is achieved because of these analog!
digital ASICs, allowing pin drivers
and Vee and GND relays to be as
close to device pins as possible. This
technology virtually eliminates
ground bounce, greatly improving
programming yields.
As a peripheral attachment, the
PLUS48 utilizes your PCs RAM,
CPU and Hard Disk Drive. Key to
this approach, the PLUS48's cost is
extremely competitive while providing lots of programming power.
Additionally, file download times
of stand-alone programmers is
eliminated.
November 1994
Order Number: 297540-001
PC Interface is through the standard parallel port. With included software
installed, the PLUS48 automatically interrogates LPT ports to determine
where it is attached-then configures itself. Ant LPT port, such as that on a
Notebook PC, can be used to control the PLUS48 giving you the freedom to
take your support on the road.
Specifications
STANDARD FEATURES
• INTEL device support.
• Standard 48-pin DIP/ZIF socket.
• Larger pin-count and non-DIP devices supported via adapters.
• Precise digital and analog signals on every pin.
• PC peripheral-Uses computer's existing RAM, CPU and HDD to provide maximum price performance.
• Portable-Connects to any standard LPT port.
• Compact design eliminates yield loss due to ground bounce.
• An internal crystal-controlled state machine insures accurate waveform
generation-independent of the PC.
• Intuitive full screen menus make the PLUS48 simple to learn and easy to
use.
• Batch mode operation-All commands can be executed from a batch file.
2-9
SPRINT PLUS48
Available Versions
INTEL SUPPORT VERSION.
Electrical. Requirementsl
Physical Specifications
• Supports all devices from SPRINT device list.
•
•
•
•
•
•
PLUS48 is easily upgraded from Intel Support Version
to Full Support via KEYFAX.
Safety Standards
• Programs Intel devices only.
• . Reads all manufacturer's
devices.
.
UNLIMITED VERSIONS
Operating voltages: 100 to 250 VAC
Frequency range: 47 to 63 Hz
Power consumption: 25W
Operating temperature: 1000C to 4Q°C
Dimensions: 2.56 x 17.9 x 20.5 cm
Operational weight: 2.61 kg
• UL, CSA and GS
PC Requirements
• DOS-based PC, Laptop or Notebook (tested to 486).
•
•
•
•
512 KB free RAM.
3 MB free space on HDD.
CGA, EGA, VGA or LCD.
Centronics Parallel port.
System Operations
• Read, Blank check, Program and Verify.
• Sum check, ID test, Illegal bit and Continuity
check.
.
• Address r~ge, Change device, Execute DOS, Input
file.
• Edit data, List memory and Write file.
Translation Formats
•
•
•
•
•
INTEL 8/16/32-bit
286/386 OMF.
Motorola 8/16/32 bit.
TEK HEX, ASCII HEX, MOS Tech.
JEDEC, POF, Binary.
Standard Accessories
•
•
•
•
•
The PLUS48 comes with a standard 48-pin DIP/ZIF
socket. Affordable adapters are available for larger pincount DIP devices or other package types. Please contact SMS or one of the SMS distributors from the following distribution list for availability.
SMS Service Centers
. • USA
SMS North America Inc.
P.O. Box 3159
Redmond, WA 98073-3159
Phone: (206) 883-8847
FAX: (206) 883-8601
• Japan
Micron Inc.
4-26-16, Koenji-Minami
Suginami Tokyo 166
Phone: + 81 3 3796 1860
FAX: + 81 3 3796 1866
• Europe
SMSGmbH
1m Grund 15
88239 Wangen, Germany
Phone: + 49 7522 9728 0
FAX: +4975229728 50
48-pin DIP/ZIF socket.
User's manual.
System Software.
Power supply.
Line cord.
2-10
I
SPRINT PLUS48
International
Distributors for SMS
SPRINT products:
Austria
Memo ELECTRONICS
Muehlberg str. 22
A-I 140 Vienna (Wien)
Phone: + (43) 1 975 626
FAX: +(43) 1975627
Belgium
Sonetech BELGIUM
de Limburg Stirumlaan 243, Bus 3
B-1780 Wemmel
Phone: + (32) 2 460 07 07
FAX: + (32) 2 460 12 00
Denmark
sd Elektronik & Data
Rejnstrupvej 11
DK - 4640 Faskse
Phone: + (45) 56 71 41 51
FAX: +(45) 56 7141 51
Finland
Computer 2000 Finland OY
P.O. Box 44
Pyyntitie 3
02231 Espoo
Phone: + (358) 0887 331
FAX: + (358) 0887 33 343
France
Emulations
Chernin de Gizy
Pare Burospace A 13
F-91572 Bievres Cedex
Phone: + (33) 1-69.41.28.01
FAX: + (33) 1-60.19.29.50
Newtek
8 rue de I'Esterel-SILIC 583
F-94663 Rungis Cedex
Phone: + (33) 1-46.87.22.00
FAX: +(33) 1-46.87.80.49
Germany
Logic Design
Riepacker str. 65
D-31 691 He1psen
Phone: +(49) 5721 97140
FAX: +(49) 5721 971497
I
MSC Vertriebs GmbH
Industrie str. 16
D-76297 Stutensee
Phone: +(49) 7249 910 175
FAX: +(49) 7249 910 221
SE Spezial Electronic
Kreuzbreite 15
D-31675 Buckeburg
Phone: +(49) 5722 203 0
FAX: +(49) 5722 203120
Synatron
Bretonischer Ring 13
D-85630 Grasbrunn
Phone: + (49) 89 460 20 71 .
FAX: +(49) 89 460 56 61
Trias
Zur Eibe 11
D-47802 Krefeld
Phone: + (49) 2151 476701
FAX: +(49) 21514747 15
Great Britain
Concentrated Programming Ltd.
Unit 3A The Maltings
Station Rd., Sawbridgeworth
Herts, CM21 9JX
Phone: + (44) 279 600 313
FAX: +(44) 279 600 322
Pronto Electronic Systems Ltd.
City Gate House
399-425 Eastern Ave., Gants Hill
Illford, Essex IG2 6LR
Phone +(44) 81 5545700
FAX: +(44) 81 5183222
Hong Kong
Int'I Technology Enterprise Co.
5 Long Yuet St. 6th Floor
F2, Kowloon
Phone: + (852) 3622309
FAX: +(852) 3620886
Israel
Talviton Electronics Ltd.
9, Biltmor str., P.O. Box 21104
Tel Aviv 61216
Phone: + (972) 3 54 42 430
FAX: +(972) 35442085
Italy
De Mico
Viale Vittorio Veneto, 8
20060 Cassina De'Pecchi-Miiano
Phone: + (39) 2 95 343 600
FAX: + (39) 2 95 219 12
Silverstar
Viale Fulvio Testi, 280
20126 Milano
Phone: + (39) 2-66 12 51
FAX: + (39) 2-66101359
Japan
Micron Inc.
4-26-16, Koenji-Minami
Suginami, Tokyo 166
Phone: + (81) 3 33179911
FAX: +(81) 3 33179917
Korea
Logicom Corporation
1634-9 Bongchum-Dong
Kwanak-Ku, Seoul
Korea 151-061
Phone: + (82) 2 888 2858
FAX: + (82) 2 888 7040
Netherland
Sonetech Netherland bv
Gulberg 33
NL-5674 TE Nuenen
Phone: +(31) 40 838009
FAX: + (31) 40 83 92 71
Norway
Kjell G. Knutsen A.S.
P.O. Box 113
N-4520 SOR-AUDNEDAL
Phone: +(47) 38 25 6205
FAX: + (47) 38 25 68 18
Poland
Cadel sp.z.o.o.
UL, Tamka 38
00355 Warszawa
Phone: +(48) 2 227 50 61
FAX: +(48) 26355262
2-11
SPRINT PLUS48
Singapore
WesTech Electronics Pte Ltd.
12, Lorong Bakar Batu, #05-07
Ko1am Ayer Industrial Park
Singapure 1334
Phone: + (65) 743 6355
FAX: +(65) 7461396
Spain
ADM Electronica SA
Tomas Breton, 50 3i 2
E-28045 Madrid
Phone: +(34) 1 53041 21
FAX: +(34) 1 5300164
2-12
Suisse
RedacomAG
Gurze1enstrasse 6
CH-2502 Bie1IBienne
Phone: + (41) 32 410 111
FAX: + (41) 32 41 49 49
Taiwan
Prospect Technology Corp.
5F, No. 348, Sec. 7 Cheng Teh Rd.
Taipei, Taiwan ROC
Phone: + (886) 2 820 5353
FAX: +(886) 2 820 5731
Sweden
Gordia Elektronik
Box 1240
S-221 05 LUND
Phone: + (46) 46 120211
FAX: +(46) 46 138 156
USA
SMS North America Inc.
P.O. Box 3159
Redmond, WA 98073-3159
Phone: + (206) 883-8447
FAX: + (206) 883-8601
I
MULTI-APRO
SYSTEM
GENERAL
297541-2
Multi-APRO Programmer
Intel Support Version
General Description
The new System General MultiAPRO is a revolutionary concept in
device programmers. Based on 48
Universal pin driver design, it can
support virtually any programmable device. The Intel Support Version of Multi-APRO programs all
Intel Flash, Microcontroller, FLEXlogic, EPLD and E(E)PROM devices at significant discount off our
standard version. Additionally, all
other manufacturer's devices can be
read into buffer memory.
This unit comes with full standalone control, but can be PC driven
for added flexibility. Expansion is
possible in two ways:
1. Full Universal (programs all
manufacturer's devices) by
swapping signature keys, or
2. Production (gang) programmer
by adding modules.
Different package types are supported via our own proprietary
adapters or DIP converters. With
adapter method, the device sits as
close to the pin drivers as possible.
This virtually eliminates any noiserelated problems due to ground
bounce. When adapters are unavailable, quality third-party converters
will be specified by System General.
November 1994
Order Number: 297541-001
297541-1
Multi-APRO comes standard with 1 megabyte of user RAM, upgradable to
16 megabytes. The device driver and related file can be downloaded via
parallel or RS232 (up to 11S.2K baud) or read in from a master, then stored
in RAM. Programming therefore is done stand-alone which improves
throughput time and yield because clock control issues are not present.
When expanded to a gang programmer, Multi-APRO is the most efficient
production tool on the market. Since each socket is independent, programming proceeds continuously from one device to the next, minimizing insertion overhead.
Support for Intel devices is provided via normal distribution media (Intel
Flash Memory Card) or BBS (Downloaded to Flash). New devices are supported prior to their introduction, handled via secure methods on a customer-by-customer basis.
In addition to the best device support available, upgrades are free for the life
of the programmer via our 24-hour BBS line.
Specifications
• Supports full range of INTEL programmable devices.
• Standard 48-pin DIP/ZIF socket.
• Optional adapters or converters available for different package configurations.
• Universally pin-driven.
• On-board RAM means programming is done directly to chip, providing
highest yield and throughput.
• Easy to use PC-assisted SW included.
• Full Batch-mode capabilities.
2-13
MULTI-APRO
Available Versions
INTEL SUPPORT VERSION
Features:
• Programs all Intel devices.
.' Reads any master device.
• Expandable to full Universal version via fie1d-installable signature key.
• Expandable to production model.
FULL UNIVERSAL VERSION
Features:
• Supports virtually all programmable device technologies.
• Expandable to production model.
GANG/PRODUCTION VERSION
Features:
• Up to eight programming modules.
• Each independent from the others-allows continuous programming for highest throughput.
• No future constraints!
Translation Formats
• Intel-HEX (32, 24, 16)
• Tektronix-HEX
• Motorola S (3,2,1)
• Signetics-HEX
• Extended Tekhex
• HP 64000 Absolute
•
•
•
•
ASCII-HEXO
ASCII-HEX(%)
ASCII-HEX(")
ASCII-HEX(,)
•
•
•
•
•
ASCII-HEX SMS
ASCII-OCTO
ASCII-OCT(%)
ASCII -OCT(")
ASCII-OCT SMS
•
•
•
•
•
BlOF
BHLF
BPNF
JEDEC
Binary (no format, no header)
PC Requirements
• DOS-based PC, Laptop or Notebook.
Standard Accessories
• 512KB free RAM.
• CGA, EGA, VGA, SVGA or LCD.
• Remote control and data transfer via PC parallel
port.
• Remote control and data transfer via RS232, Baudrate Max 115.2K bps.
'
• 48-pin DIP/ZIF socket adapter (Intel Support Version)
System Operations
• Read, insertion check, illegal bit check, erase, blank
check, program, continuity check and verify.
•
•
•
•
•
•
•
•
•
•
•
•
•
Auto-Sense™, ID test.
Even/Odd programming.
Special on-screen editor.
Sum check, Pass/Fail counter.
EPROM Auto-Identify.
Address range modification.
Current sense, boot-block secure.
Functional Test, Margin Verify.
PLD JEDEC fuse screen editor.
Upload/Download functions.
Context-sensitive help screen.
Stand-alone and remote control.
Connects to IBM PC, compatible or non-IBM PC
via RS232.
2-14
• System software (IBM PC or compatible)
• Power Supply
• All neccessary cabling
• User's manual
Adapter Options
• PLCC 20, 28, 32, 44, 52, 68 or 84 pins
• QFP100
Electrical Requirements/Physical
Specifications
•
•
•
•
Operation Voltages: 90 to 250 VAC
Frequency range: 47 to 63 Hz
Power consumption: 30W max
Operation Temperature: (J' to 45°C
• Dimensions:
Controller-350mm x 200mm
Module--350mm x 155mm
• Safety Standards: UL, CSA, VDE
• EMI: FCC class B, VDE 0871 B
I
MULTI·APRO
INTERNATIONAL CONTACTS
FOR SYSTEM GENERAL
US
System General Corp.
1603-A South Main St.
Milpitas, CA 95035
TEL: (408) 263-6667
FAX: (408) 262-9220
SALES: (800) 967-4776
Japan
Nippon System General
TEL: 81-3-34411510
Korea
Wooyoung Tech. Co., Ltd.
TEL: 82-2-3697099
Dasan Technology
TEL: 82-2-5018276
Hong Kong
Twin-Star Trading Company, Ltd.
TEL: 852-3469085
Singapore
WesTech Electronics Pte., Ltd.
TEL: 65-7436355
EPE Computronics Pte:, Ltd.
TEL: 65-7468182
Taiwan
System General Corp.
3F, No.1, Alley 8, Lane 45
Bao Shing Rd., Shin Dian
Taipei, Taiwan R.O.C.
TEL: 886-2-917-3005
FAX: 886-2-911-1283
Switzerland
Novitas Elektronik AG
TEL: 41-1-9450300
Belgium
Eurodis Inelco NV/SA
TEL: 32-2-2442924
France
Micropross
TEL: 33-20479040
Norway
Tormatic A/S
TEL: 47-34-25011
Australia
Macro Dynamics Pty., Ltd.
TEL: 61-3-7202399
South Africa
Specitec Pty., Ltd.
TEL: 27-11-7891743
CONTACT YOUR LOCAL DISTRIBUTOR FOR
PRICING AND AVAILABILITY.
I
2-15
Flash Memory Card and Flash Drive Evaluation Kit
Product Brief
Product Highlights
Complete kit for adding a
PCMCIA soeket to an AT-based
system
_ The Flash Drive Kit (iA TAKIT)
includes a 5MB Flash Drive
_ The Flash Card Kit
(S2S2PLUSKIT) includes both
a 4MB Series 2+ and a 2MB
Series 2 Flash Card
_ Includes ISA-based PCMCIA
ReaderlWriter that fits into
an empty floppy disk slot on
your system
_ Created for x86 DOS- or
Wlndows'-based systems
_ Includes source code for
non-DOS system development
_ Includes SystemSoft's·
CardSoft· suite of software
_ Contains industry-standard
PCMCIA software, including
SystemSoft Flash File System
(FFS) software
_ Contains a 68-pin PCMCIAATA to 4OI440pin IDE
adapter for easy conversion
(iATAKITonly)
_ Excellent for evaluating
Flash Card or Flash Drive
performance with mUltiple
software configurations
Product Description
The Flash Drive (iATAKIT) and the Flash Card (S2S2PLUSKlT) evaluation kits
are designed to make DOS-based AT systems Intel Flash Card or Flash Drive-ready
- quickly and simply. Each kit provides everything necessary to add a PCMCIA
socket to a desktop system.
The Flash Drive and Flash Card kits are ideally suited for designers creating PDAlike products; designers of mobile, handheld and sub-notebook products; designers
who want to evaluate Flash Card and/or Flash Drive products for embedded
applications; and ISVs who write software for Flash Card or Fla,h Drive products.
To shorten time to market, both kits contain all necessary tools in a single box.
Thus eliminating the time-consuming task of seeking and obtaining separate
components.
Each kit includes SystemSoft's CardSoft suite utilizing industry-standard PCMCIA
software - as well as SystemSoft's Flash File System (FFS) software. Additionally, each kit includes low-level driver and MTD source code, enabling modification
for your specific requirements or product differentiation. For easy conversion of
PCMClA-ATA to IDE pinouts a 68-pin to 40/44-pin adapter is included.
infel~
2-16
I
Features
Benefits
- AII-in-one kit
- Contains everything needed to develop Intel
Flash Card or Fla~h Drive-ready systems
- Includes low-level driver and MTD source code
- Enables code modification for specific requirements
- SystemSoft CardSoft
- Industry-standard PCMCIA software suite
- Flash File System (FFS) software
- Industry-standard file system from SystemSoft
- 68-pin ATA to 40/44-pin IDE adapter
- Easily converts PCMCIA-ATA pinout to IDE
The Intel logo is a registered trademark of Intel Corporation.
Other brands and names are the propeny of their respective owners.
Printed in USA/0694/40KlASIiLK
© 1994 Intel Corporation
Order Number: 297506-00 I
I
2-17
infel®
SMALL OUTLINE PACKAGE GUIDE OVERVIEW
Intent
Contents
How to Order
This overview provides a quick reference for the Small Outline Package Guide, Intel literature
order number 296514.
The table below details, in outline form, the type of information that can be found in the guide.
Phone: (800) 548-4725 in US and Canada
Outside US/Canada, contact local Intel or distributor sales office
or write to:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
Chapter
2-18
Contents
Package
Description
• Small-Form-Factor/Fine-Pitch Introduction
• TSOP, SSOP and PSOP Key Features
• Device/Package Offerings
SOP4yout
Features and
Applications
• Space-Saving Features
• Device Pinouts • SOP Applications
SOP Physical
Dimensions
• Package Drawings and Specifications
• PCB Land-Pad Layout Diagrams
• Component Volume and Weight
SOP Package
Characteristics
• Electrical Characteristics
• Thermal Data
SOP Manufacturing
•
•
•
•
•
Assembly Process Flow
Package Materials
Cross-Section Diagrams
Electrical and Solderability Test
Mechanical Inspection
SOP Reliability
StreSses·
•
•
•
•
•
•
•
•
•
Temperature Cycling via Convection
Thermal Shock, Liquid-to-Liquid Stress
Steam, Accelerated Moisture Penetration Stress
85°C/85% Relative Humidity, Alternate Pins Biased (+ 5V and GND)
High-Temperature Dynamic Life Test
Solder-Joint Reliability
Surface Mount Process Considerations
Use Condition Considerations
Solder-Joint Life Predictions Curves
SOP Handling
•
•
•
•
•
•
SOP Shipping Formats
Tray Diagrams and Dimensions
Tray Recycling
Tape and Reel carrier Diagrams and Dimensions
Tube Diagrams and Dimensions
Moisture Considerations and Data
- Plastic Package Aggressive Preconditioning Flow
- Reliability Data
- Moisture Absorption
- Moisture Desorption
.-
. November 1994
Order Number: 297542-001
Chapter
I
Contents
SOP SMT Assembly
Considerations
- Storage and Handling
- Screen Printing
- Soider Paste
- Solder Volume
- Solder Mask
-Stencil
- Vision System
-Squeegee
- Placement Equipment
- Cleaning
-IR Furnace
- PCB Design Considerations
- Lead Placement Examples:
- Good Placement
-Misaligned
- Lifting
SOP Ordering
Information
- Production/Package Identification
References and
Additional
Information
- Other Reference Material
SOP 3rd-Party
Equipment
Suppliers
•
-
SOP Standards
Bodies
- EIA/JEDEC
-ANSI
-IPC
- EIAJ
SOP Suction Wand Suppliers
SOP Programming Adapter Suppliers
SOP Programming Vendors
SOP Socket Suppliers
- Prototyping Sockets
- Burn-In/Test Sockets
• SOP Handier Equipment Suppliers
• SOP Manufacturing Equipment Suppliers
- SOP Custom Board Manufacturing and Interposer Mounting
2-19
I
Intel FLASHBuilder Software
Product Brief
Product •
HigbUgbts
Supports I6-Mblt 18FOI6SA
F1asbFIIelll memory
• Text bJgbIlpts for qulck_
to lnformaUoo about device
fanctioaa) blocks
• On-line documeDlatIoo
• Toolbar for r.t _
to
lnformaUoo _
• FLASRText window for Ups
on using FLASHBuIIder
Product Description
FLASHBuilder is a Windows·-based software tool developed to facilitate \be
undmlallding of and designing with Intel Flash Memory components. Its user
interface provides a graphicill representation of device functional blocks within \be
flash memory architecture.
FLASHBuilder also features dialog boxes in the toolbar for quick access to
infonnation about 28FOI6SA operations, commands, algorithms and registers. For
example, the command dialog box displays on a single screen the 28FO 16SA
command set and corresponding hexadecimal values, bus-cyc\e counts for each
command, and status register output indicating a successful operation.
infel·
2-20
Currently supporting the I6-Mbit 28FOI6SA FlashFile memory, FLASHBuilder
contains the associated user's manual, application notes and dntasheet specifications
in an easy-tOouse, on-line Hypertext format for point-and-click access. Documentation embedded in the software includes:
- 28FOI6SA User's Manual
- 28FOI6SA Application Notes:
- AP-357 "Power Supply Solutions for Flash Memory"
- AP-359 "28F008SA Hardware Interfacing"
- AP-375 "Upgrade Considerations from the 28FOO8SA to the 28FOI6SA"
- AP-317 ''28FOI6SA Software Drivers"
- ' AP-378 "System Optimization Using the Enhanced Features of the
28FOI6SA"
.
- 28FOI6SA timing and waveform specifications
-" 28FOI6SA Qs and As - Frequently asked questions and answers regarding
28FOI6SA FlashFile memory
- Flash Memory Overview - A high level description of flash technology and
product applications.
I
I
Future updates to FLASHBuilder will provide support for multiple devices and chip
architectures. To speed decision making and reduce user resource requirements,
options allowing minimal or partial install will be added. With minimal install
selected, a subset of available information can be installed, allowing the designer to
quickly decide which device best suits the application need. Partial install minimizes
disk consumption by installing only the necessary files for the selected device(s).
Features
Benefits
- Graphical user interface
- Easy-ta-use point and click access
- On-line documentation
- Quick reference to technical specifications and
product applications notes
- Integrated toolbar dialog boxes
- Intuitive resource for operations, registers, commands,
algorithms, documentation, help
- Enhancement path
- Variable install options will meet application needs
(minimal/partial installations)
System Requirements - Version 1.Oa
- Inte1386rM microprocessor or higher
- 2-MBRAM
40MB free hard disk space
-
VGA display (SVGA recommended)
3V," floppy disk drive
Windows 3.1 or above
To order FLASHBuilder or additional literature, calli (800) 548-4725.
FLASHBuilder order number: 297508.
For technical assistance and/or the name of your local distributor call
I (800) 628-8686.
FLASHBuilder is also available through Intel's Bulletin Board Service (BBS):
in NorthlSouth America and Asia Pacific dial (916) 356-3600; in Europe dial
+44 (0) 793-496340
*Otber brands and names are the trademarks of their respective ownen.
Prinled in USAlI094JIOKIASlITCIMCD.
" 1994 Intel Corporation
Order Number: 297536-001
I
2-21
AP-357
APPLICATION
NOTE
Power Supply Solutions
for Flash Memory
MICHAEL EVANS
ANIL SAMA
BRIAN DIPERT
APPLICATIONS ENGINEERING
INTEL CORPORATION
August 1994
2-22
I
Order Number: 292092-002
Power Supply Solutions for Flash Memory
'CONTENTS
PAGE
CONTENTS
PAGE
1.0 INTRODUCTION .................... 2-24
5.~;VF~~1..S~L~~I~~~: .~~~~~.~~.I~~. 2-39
2.0 FLASH MEMORY POWER
REQUIREMENTS ..................... 2-24
Vee Characteristics ............... 2-24
Vpp Characteristics ................ 2-24
2.1 Supplies For Battery Powered
Applications ........................ 2-25
2.2 Choice of a DC-DC Converter ..... 2-25
The Modular Solution .............. 2-25
The Discrete Switching Regulator
Solution ......................... 2-25
The Discrete Charge-Pump
Solution ......................... 2-26
Attributes of a DC-DC Converter ... 2-26
2.3 Summary ......................... 2-26
5.1 Maxim MAX756 ................... 2-39
5.2 Linear Tech LT1301 .............. 2-41
3.0 12V Vpp SOLUTIONS:
CONVERTING UP FROM 5V ......... 2-26
3.1 Maxim MAX734 ................... 2-27
3.2 Maxim MAX761 ................... 2-28
. 3.3 Maxim MAX662 ................... 2-30
3.4 Linear Technology LT1109-12 .... 2-31
3.5 Linear Technology LT1301 ........ 2-33
3.6 Motorola MC3406.3A .............. 2-34
4.0 12V Vpp SOLUTIONS:
CONVERTING UP FROM 3V ......... 2-36
4.1 Maxim MAX761 ................... 2-36
4.2 Linear Technology LT1301 ........ 2-37
I
6.0 12V Vpp SOLUTIONS: DOWNCONVERTING FROM A HIGHER
VOLTAGE ............................ 2-42
6.1 Maxim MAX667 ................... 2-42
6.2 Linear Technology LT1111-12 .... 2-44
6.3 National Semiconductor
LM2940CT-12 ..................... 2-45
7.0 12V Vpp FROM 12V
UNREGULATED ...................... 2-46
8.0 SUMMARY .......................... 2-46
APPENDIX A: MODULAR
SOLUTIONS ............... '........... 2-47
APPENDIX 8: SURVEY OF SOLUTIONS
PRESENTEI) ......................... 2-48
APPENDIX C: SOURCES FOR DC-DC
CONVERTERS .. : .................... 2-49
APPENDIX D: SOURCES FOR
DISCRETE COMPONENTS ........... 2-52
APPENDIX E: OTHER DESIGN
CONSIDERATIONS .................. 2-54
APPENDIX F: PC LAYOUTS FOR SOME
RECOMMENDED SOLUTIONS ....... 2-58
2-23
AP-357
1.0
INTRODUCTION
Intel flash memory is rapidly being incorporated into a
wide range of applications, adding enhanced capability
to existing "traditional" memory markets, and creating
new markets that exploit its benefits. Sometimes the
design platforms may not possess the low powered 12V
supply for writing flash memory. The system design
engineer then needs to identify a power conversion solution with features and capabilities matching the needs
of the application. For example, portable equipment requires a power supply converter that minimizes size
and weight, maximizes efficiency to extend battery life,
and can be switched into a standby mode to conserve
power.
The following pages present some state of the art DCDC converter solutions. These new solutions are smaller and more efficient than those typically seen in the
past. Each of these solutions optimizes a subset of all
possible power converter features. The choice of an optimal solution for a given application will be a tradeoff
between several attributes. The solutions shown should
meet the conversion needs of the majority of applications involving flash memory. Specifically, the solutions
that follow encompass the following five categories:
•
•
•
•
•
5V to 12V conversion
3V (2 alkaline/NiCd cells) to 12V conversion
3V (2 Alkaline/NiCd cells) to 5V conversion
Downconverting to 12V from a higher voltage
Converting 12V unregulated to 12V regulated
More than one solution is presented within each of
these categories. These different solutions have distinct
optimal features/advantages. The optimal attributes of
each solution are outlined. In addition, the. appendix
contains a survey of all solutions presented here, and
provides a basis for comparing their features. The reader should reference it to choose an optimal solution for
hislher application.
NOTE:
Solutions were selected from products offered by over
thirty DC-DC converter vendors. Since this industry
develops many new solutions each year, Intel recommends that designers contact vendors for latest products. Intel will continue to work with the industry to
develop optimum solutions for power conversion. Intel
Corporation assumes no responsibility for circuitry
other than circuitry embodied in. Intel products. No
other circuit patent licenses are implied.
2-24
2.0 INTEL FLASH MEMORY POWER
REQUIREMENTS
Intel flash memory is powered by two sources; a 5V
Vee line and a 12V Vpp line. Vee is the primary power source and the only power source needed to read the
memory. Vpp is required when writing or erasing the
memory.
Vee Characteristics
Vee supplies power to the flash device during all operational modes. Maximum Vee current is demanded by
the device during the read operation. The data sheets
for specific Intel flash memory devices should be consulted to determine the maximum read current (led
for the device. If multiple components are read simultaneously, the Vee current requirement increases proportionately. Vee tolerance must be maintained to within
specification limits at all times for proper functioning of
the device.
Vpp Characteristics
The supplemental Vpp source provides the higher voltages needed to carry out the erase, erase verify, program, and program verify operations. Maximum Vpp
current is typically demanded during the program and
erase modes. The data sheets for specific Intel Flash
Memory devices should be consulted to determine the
Vpp voltage and maximum Vpp write/erase current
(Ipp) for the device. If multiple components are programmed/erased simultaneously, the current requirement increases proportionately. Vpp must be maintained to within specification limits at all times during
device program, and erase. The tolerance specification
on Vpp must be strictly maintained. Over-voltage can
damage the device, and under-voltage can decrease
specified device reliability. Although the Vpp supply
must meet these worst case specifications, power usage
will typically be much lower. The lower typical values
seen in the data sheets should be used in calculating
typical battery life.
I
AP-357
2.1 Supplies for Battery Powered
Applications
In applications where batteries are the primary source
of power, the power supplies providing Vee and Vpp
need to be selected very carefully. Optimized operating
efficiency of these supplies is important to extend battery life. Another attractive feature is the capability of
these supplies to be switched into a very low power
shutdown mode. It is important to minimize this shutdown current consumption as well since flash memory
Vpp generators will often be in this state for extended
periods of time. Moreover, since these supplies are used
in equipment that is physically small and space-constrained, size and height of the supply need to be minimized.
Where two alkaline/NiCd batteries are used as the primary source of power, the primary voltage varies depending on the type and the state of discharge of the
batteries. For example, alkaline batteries start life off at
1.5V, but may still retain a significant amount of energy
when the voltage falls to 1.0V with use, and will work
all the way down to 0.8V. On the other hand, NiCd
cells maintain a near constant voltage of 1.25V
throughout most of their discharge cycle, and work
down to 1.0V. A solution that derives Vee or Vpp from
2 AA batteries must hence be capable of doing so from
an input voltage that lies in the range of 1.6V to 3.0V.
It is best to directly convert the primary battery voltage
into the various voltages needed throughout the system.
A step conversion (e.g. a 3V to 5V converter for Vee.
followed by a 5V to 12V converter for Vpp) is not recommended, since the inefficiency involved in each conversion step combines into one large inefficiency for the
sum 3V to 12V conversion. Section 4 presents appropriate 3V battery to 12V converter solutions. Most of the
solutions presented in this application note, while specifically designed for battery powered applications, are
also viewed as ideal for other applications that incorporate flash memory.
2.2 Choice of a DC-DC Converter
The solution to finding the right power supply for flash
memory lies in picking the right DC-DC converter for
the job. Three broad categories of DC-DC converters
available in the market today can be applied towards
this purpose. These are the low power hybrid DC-DC
converter module (or modular solution), the low power
discrete switching regulator IC solution, and the low
power discrete charge-pump solution.
I
The Modular Solution
The modular solution generally consists of a push-pull
(Royer type) oscillator built around an isolation transformer, and in some cases followed by a linear regulator; all of which is encapsulated within a module. This
hybrid module includes all components that are required by the DC-DC converter, and so no additional
design effort is needed. The input and output voltages
are fixed, and the input and output are almost always
isolated via the isolation transformer. The main advantage of these solutions is that no design effort and/or
external components are involved. They simply plug
into a socket on a PC board. Disadvantages include
lower efficiency (generally 60%), larger sizelheight (in
most cases), and higher cost (generally 3x to lOx the
cost of discrete solutions).
It would seem that the integration inherent in these
solutions contributes towards system reliability, however the type and quality of the discrete components used
internal to these hybrid devices is open to question. The
isolation offered between the input and output is viewed
as overkill for flash applications, since the total power
required is typically less than IW. Note also that the
isolation transformer is often the main reason for the
lower efficiencies.
The Discrete Switching Regulator
Solution
The discrete switching regulator IC solution consists of
a DC-DC converter IC (containing a switching regulator controller and an output power switch), along with
a few discrete external components (inductor, diode,
capacitors, resistors, etc.). The layout of the power supply system in this case is mostly left up to the user.
However, application notes and data sheets explain the
design process, and provide recommended circuits for
commonly used solutions. The design can be tailored to
deliver different output voltages and current levels depending on the characteristics of the input voltage and.
the external components.
Some vendors offer fixed output voltage versions, further simplifying the design process. The newer generation of high frequency low power switching regulator
ICs are specifically targeted at battery powered operation, and most can be switched into a low quiescent
current shutdown mode to extend battery life. These
have typical efficiencies in the 75% to 90% range. Furthermore, the higher switching frequencies of these new
parts (typically 100 KHz to 200 KHz) allow the use of
smaller external components, which are available in
surface mount varieties. As a consequence, these newer
solutions are overall much smaller than what was typically seen just a year ago.
2-25
Ap·357
The Discrete Charge-Pump Solution
2.3 Summary
The discrete charge-pump solution is similar to the discrete switching regulator IC solution in that it also consists of a DC-DC converter IC and a few discrete
external components (capacitors). The charge-pump,
however, operates in a significantly different fashion
(see Appendix E), and as a result does not require inductors and diodes as a discrete switching regulator solution does, which means that a charge-pump solution
is generally smaller and cheaper~ On the down side,
charge-pump solutions generally have lower efficiencies
and lower output current capabilities than discrete
switching regulator solutions.
The reader is referred to Appendix B, which provides a
survey of all the solutions that are presented in this
application note, in order to compare their attributes.
Attributes of a DC-DC Converter
Several attributes of a power supply converter must be
evaluated and prioritized when choosing the best solution for a given application. These attributes include:
• Input Voltage Range
• Output Voltage and Tolerance
• Output Current Capability
• Efficiency of Conversion
• Printed Circuit Area
•
•
•
•
•
Height
Total Cost
Shutdown Capability
Quiescent Current Consumed in Shutdown Mode
Rise Time from Shutdown
• Surface Mountability
2-26
This application note primarily presents state of the art
discrete switching regulator IC solutions (and one
charge-pump solution) which have been carefully designed for operation with flash memory. Included along
with schematics are component values and sources/
contacts for obtaining components. Actual layouts have
also been included where possible. These are provided
in Appendix F.
NOTE:
External components recommended in the designs
should be used. These components (inductors, capacitors, resistors) were chosen based on recommendations
by the converter IC vendors and provide the necessary
quality for a clean design. Alternate "equivalent"
parts should be chosen with care as their resistive and
inductive elements can affect the operation of the solution. Please contact the respective converter IC companies for assistance if you select an alternate value/
source for passive components.
3.0 Vpp SOLUTIONS: CONVERTING
UP FROM 5V
Most computer systems have available a 5V Vee line
that is used for the majority of system power. Frequently, this 5V supply is used to generate 12V for flash
memory. This section presents some of the new state of
the art solutions that can achieve this function. These
are all discrete switching regulators that optimize different attributes, mentioned along with the main features section of each example. Refer to Appendix B for
a more detailed comparison of the attributes of these
solutions.
I
AP-357
3.1 Maxim Integrated Products-MAX734: Vpp
@
120 mA
VIN (4V-7V)
L1
18 )LH
SHUTDOWN
C2
~
~
SHDN
2
3
0.1 J.4F 4
VREF
V+
r-t--......~-...- ...- ..
SS
CC
Rl
VOUT
lfi.5%
R2
........._ _ _01-- Vpp @ 120mA
GND
lfi.5%
MAX734CSA
C4
1000 pF
+ C6
.I.
O.I)LF
OPTIONAL
FILTER
~----------292092-1
Figure 3·1. Maxim MAX734 5V to 12V Converter
Optimal Attributes
• High Efficiency
• Low Shutdown Current
• Small Size: 0.3 sq. in. Total Board Area
(Single Sided)
• All Surface Mount
Main Features
• Input Voltage Range: 4V to 7V
• Output Voltage: l2V ± 5%
• Output Current Capability:
Up to 120 rnA @ VIN = 5V
• Typical Efficiency: 83%@ ILOAD = 120 mA,
VIN = 5V
• 170 KHz Switching Frequency
• Shutdown Feature on Chip
• Low Quiescent Current at Shutdown: 70 /LA typical
• Low Operating Quiescent Current: 1.3 rnA typical
• Rise, Time from Shutdown: 1.5 ms typical
• Soft-start Capability
I
The MAX734 is a 12V-o~tput step-up converter which
uses 6 small external surface mount components to implement a small 5V to l2V converter solution. It is
available in a small 8-pin surface mount package. The
MAX734 design as shown is capable of providing up
to 120 rnA ofVpp current at an efficiency of 83%. The
supply can be switched into a shutdown mode where
the output voltage falls to approximately VIN 100 mV and the quiescent input current falls to below
70 /LA. The rise time from shutdown mode is typically
1.5 ms. The MAX734 also has a Soft-start feature
which allows the designer to limit surge currents at
start-up by adding a capacitor between the MAX734's
SS pin and ground. The high switching frequency of the
MAX734 allows the use of very small external capacitors and contributes to the small size of the supply circuit. Series inductance in the filter capacitor and diode
switching transients may cause high-frequency noise
which appears as sharp voltage spikes in the output.
Such spikes can be eliminated by practicing good PCboard layout or by using the optional filter circuit
shown in the design. Applications assistance and a surface mount evaluation board are available from Maxim.
2-27
AP-357
Table 3·1. Parts List for the MAX734 SV to 12V Converter
Ref
Part #
Value/Type
Source
Cost·
U1
MAX734CSA
SMPSIC
Maxim
(408) 737-7600
$1.83
C1,C5
267M1602-336-MR-720
33,...F/16V
Tantalum
Matsuo
(714) 969-2491
$0.48
C2
GRM40Z5U104M050AD
0.1,...F
Murata Erie
(404) 436-1300
$0.05
C3 (opt)
GRM40Z5U103M050AD
0.01,...F
Murata Erie
(404) 436-1300
$0.03
C4
GRM40Z5U102M050AD
0.001,...F
Murata Erie
(404) 436-1300
$0.03
C6 (opt)
GRM40Z5U104M050AD
0.1,...F
Murata Erie
(404) 436-1300
$0.05
01
EC15QS02L
1N5817 Diode
. Nihon
(805) 867-2555
$0.30
L1
CD43-180
18,...H
Sumida
(708) 956-0666
$0.55
R1, R2 (opt)
9C08052A 1ROOJLR
10.,5%
Philips
(817) 325-7871
$0.03
Total Cost
$3.35
• Cost estimates based on published 10K unit pricing at the time this application note was written.
3.2 Maxim Integrated Products-MAX761: Vpp
@
150 mA
V1N (4.75V-12V)
Rl
01
lN5817
FB
SHUTDOWN _ _ _4"-1 SHDN
GND
6
REF
5
t.lAX761CSA
C5
.I 0.1 I'F
-=- -=-
.I
C3
0.1 I'F
C2
+
22 I'F / 16V.I.
TANT
In,5%
+ C4
. I . O.lI'F
OPTIONAL
FILTER
.. _----------
292092-2
Figure 3·2. Maxim MAX761 SV to 12V Converter
2-28
I
AP-357
Optimal Attributes
•
•
•
•
High Efficiency
Lowest Shutdown Current
Low Quiescent Supply Current
All Surface Mount
Main Features
• Input Voltage Range: 4.7SV to 12V
• Output Voltage: 12V ±4%
• Output Current Capability:
Up to ISO rnA @ VIN = SV
• Typical Efficiency: 86% @ ILOAD = ISO rnA,
VIN = SV
• 300 KHz Switching Frequency
• Shutdown Feature on Chip
• Low Quiescent Current at Shutdown: S /LA max
• Low Operating Quiescent Current: 2S0 /LA typical
• Rise Time from Shutdown: 1 ms typical
The MAX761 is a 12V-output step-up converter which
uses pulse-frequency-modulated (PFM) control to offer
high efficiency over a wide range ofloads. It is available
in a small 8-pin surface mount package and uses only 6
small external surface mount components to provide a
12V ± S% supply. The MAX761 design as shown is
capable of providing up to 150 rnA ofVpp current at an
efficiency of 86%. The supply can be switched into a
shutdown mode where the output voltage falls to approximately VIN and the quiescent supply current falls
to below 5 /LA. The rise time from shutdown mode is
typically 1 ms. The high switching frequency of the
MAX761 allows the use of very small external capacitors and contributes to the small size of the supply circuit. Series inductance in the filter capacitor and diode
switching transients may cause high-frequency noise
which appears as sharp voltage spikes in the output.
Such spikes can be eliminated by practicing good PCboard layout or by using the optional filter circuit
shown in the design. Applications assistance and a surface mount evaluation board are available from Maxim.
Table 3-2. Parts List for the MAX761 5V to 12V Converter
Source
Cost"
U1
MAX761 GSA
SMPS IC
Maxim
(408) 737-7600
$2.02
C1, C2
267M 1602-226-MR.720
22/LF/16V
Tantalum
Matsuo
(714) 969-2491
$0.48
C3,C5
GRM40Z5U10!l.M050AD
0.1/LF
Murata Erie
(404) 436-1300
$0.05
C4 (opt)
GRM40Z5U104M050AD
0.1 /LF
Murata Erie
(404) 436-1300
$0.05
01
EC10QS02L
1N5817 Diode
Nihon
(805) 867-2555
$0.22
L1
CD43-180MC
18/LH
Sumida
(708) 956-0666
$0.53
R1, R2 (opt)
9C08052A 1 ROOJLR
10.,5%
Philips
(817) 325-7871
$0.03
Total Cost
$3.38
Ref
Value/Type
Part #
..
• Cost estimates based on published 10K Unit pricing at the time thiS application note was written .
I
2-29
AP-357.
3.3 Maxim Integrated Products-MAX662: Vpp
@
30 mA
VIN (4.7SV-S.SV)
C4
+
4.7 P.F/16VI.
TANT
SHUTDOWN - - - - - - - - - - ,
-----------.
Rl
Cl
0.22 p.F
~~~---r_-~t_-~ln,S%t------~
C2
0.22 p.F
Vpp @ 30 rnA
R2
MAX662CSA
C5
+
4.7 P.F/16VI.
TANT
In,S%
+ C6
I . O.lp.F
OPTIONAL
FILTER
~-----------
292092-38
Figure 3-3. Maxim MAX662 5V to 12V Converter
Optimal Attributes
•
•
•
•
•
•
Lowest Cost
Low Shutdown Current
Low Quiescent Supply Current
Fast Rise Time from Shutdown
No Inductors Necessary
Small Size: 0.2 sq. in. Total Board Area
(Single Sided)
• All Surface Mount
Main Features
• Input Voltage Range: 4.75V to 5.5V
• Output Voltage: 12V ± 5%
• Output Current Capability:
Up to 30 rnA @ VIN = 5V
• Typical Efficiency: 74% @ ILOAD = 30 rnA,
VIN = 5V
• 400 KHz Switching Frequency
• Shutdown Feature on Chip
2-30
• Low Quiescent Current at Shutdown: 70 /-I-A typical
• Low Operating Quiescent Current: 320 /-I-A typical
• Rise Time from Shutdown: 600 /-I-s typical
The MAX662 is a 12V-output boost converter. It uses
internal charge pumps and 5 small external surface
mount capacitors to generate Vpp, with no need for
inductors. It is available in a small 8-pin narrow surface
mount package. The MAX662 design as shown is capable of providing up to 30 rnA of Vpp current at an
efficiency of 74%. The supply can be switched into a
shutdown mode where the output voltage falls to VIN
and the quiescent supply current falls to below 70 /-I-A.
The rise time from shutdown mode is typically 600 /-I-s.
The high switching frequency of the MAX662 allows
the use of very small external capacitors and contributes to the small size of the supply circuit. Series inductance in the filter capacitor and diode switching transients may cause high-frequency noise which appears as
sharp voltage spikes in the output. Such spikes can be
eliminated by practicing good PC-board layout or by
using the optional filter circuit shown in the design.
Applications assistance and a surface mount evaluation
board are available from Maxim.
I
AP-357
Table 3-3. Parts List for the MAX662 5V to 12V Converter
Ref
Part #
Value/Type
Source
Cost·
lJ1
MAX662CSA
SMPS IC
Maxim
(408) 737-7600
$1.69
C1,C2
GRM40Y5V224Z025AD
0.22,.,.F
Murata Erie
(404) 436-1300
$0.15
C3
GRM40Z5U104M050AD
0.1,.,.F
Murata Erie
(404) 436-1300
$0.05
C4,C5
267M1602-475-MR-533
4.7,.,.F/16V
Tantalum
Matsuo
(714) 969-2491
$0.21
C6 (opt)
GRM40Z5U104M050AD
0.1,.,.F
Murata Erie
(404) 436-1300
$0.05
R1, R2 (opt)
9C08052A 1ROOJLR
1n,5%
Philips
(817) 325-7871
$0.03
Total Cost
$2.18
..
• Cost estImates based on published 10K umt pricIng at the tIme thIs applicatIon note was written .
3.4 Linear Technology LT1109-12: Vpp
@
60 rnA
SHUTDOWN - - - - - - - - - - - - - ,
Vee
Cl
+
22 pF/l OV '1'
TANT -L..
RI
Ul
VIN
FB
SHDN
N/c
SUMIDA
CD54-330
SW
GND
8
1+-+-.-.....
---..
7
N/c 56
N/c
LT1109-12
01
111,5%
R2
"---4I~.a- Vpp
@ 60 rnA
+ C2
"T'
-L..
_
22pF
16V
TANT
In,5%
FI
C3
O.I P
OPTIONAL
FILTER
_
.. _------(MBRS 120T3)
292092-3
Figure 3.4 Linear Technology LT1109-12 5V to 12V Converter
I
2-31
AP-357
• Low Operating Quiescent Current: 320 IJ-A typical
• Rise Time from Shutdown: 800 IJ-s typical
Optimal Attributes .
• Low Quiescent Supply Current
• Small Size
• All Surface Mount
Main Features
• Input Voltage Range: 4.5V to 5.5V
• Output Voltage: l2V ±5%
• Output Current Capability:
Up to 60 rnA, @ VIN = 5V
• Typical Efficiency: 84% @ ILOAD = 60 rnA,
VIN = 5V
• 120 KHz Switching Frequency
• Shutdown Feature on Chip
• Low Quiescent Current at Shutdown: 320 IJ-A
typical
The LT1109-12 is a fixed 12V-output part which is well
suited to flash memory applications. It is available in a
small 8-pin surface mount package and uses only 4
small external components to implement a very small
size 5V to l2V converter solution. The LTI109-12 design as shown is capable of providing up to 60 rnA of
Vpp current at an efficiency of 84%. The supply can be
switched into a shutdown mode where the output voltage falls to approximately VIN-550 mY. Quiescent
supply current at shutdown remains at approximately
320 IJ-A. The rise time from shutdown mode is typically
800 ,...s. Series inductance in the filter capacitor and
diode switching transients may cause high-frequency
noise which appears as sharp voltage spikes in the output. Such spikes can be eliminated by practicing good
PC-board layout or by using the optional filter circuit
shown in the design. Applications assistance is available
from Linear Technology Corporation.
Table 3-4. Parts List for the LT1109-12 5V to 12V Converter
Ref
Part #
Value/Type
Source
Cost·
U1
LT1109CS8-12
SMPSIC
Linear Tech
(408) 432-1900
$2.16
C1
267M 1002-226-M.R-720
22IJ-F/10V
Tantalum
Matsuo
(714) 969-2491
$0.16
C2
267M2502-106-MR-720
10 ,...F/25V
Tantalum
Matsuo
(714) 969-2491
$0.24
C3·(opt)
GRM40Z5U104M050AD
0.1,...F
Murata Erie
(404) 436-1300
$0.05
01
MBRS120T3
Schottky Diode
Motorola
(800) 521-6274
$0.37
L1
CD54-330LC
3,...H
Sumida
(708) 956-0666
$0.55
R1, R2 (opt)
9C08052A 1 ROOJ LR
10.,5%
Philips
(817) 325-7871
$0.03
Total Cost
$3.56
..
• Cost estimates based on published 10K Unit pnclng at the time thiS applicalion note was wntten.
2-32
I
AP-357
3.5 Linear Technology LT1301: Vpp
200 mA
@
YIN (3Y-l0Y)
L1
221'H
Rl
~--f--4~"'*'-"'''''''4
lfl,5%
R2
lfl,5%
..........---'- Y
pp @ 120mA
+ C3
.I.
.. _---------
O.lI'F
OPTIONAL
FILTER
C2
47I'F/ 16Y
TANT
+
.I.
292092-29
Figure 3-5. Linear Technology LT1301 5V to 12V Converter
Optimal Attributes
•
•
•
•
High Efficiency
High Output Current Capability
Low Shutdown Current
Low Quiescent Supply Current
• Small Size
Main Features
• Input Voltage Range: 3V to lOY
• Output Voltage: 12V ± 5%
• Output Current Capability:
Over 200 rnA @ VIN = 5V
• Typical Efficiency: 88% @ ILOAD = 200 rnA,
VIN = 5V
• 155 KHz Switching Frequency
• Shutdown Feature on Chip
• Low Quiescent Current at Shutdown: 15 J.LA max
• Low Operating Quiescent Current: 120 J.LA typical
• Rise Time from Shutdown: 1.2 ms typical
I
The LT1301 is a micropower step-up DC-DC converter. It is available in a small 8-pin surface mount package and uses only 4 small external surface mount components. The LT1301 design as shown is capable of
providing over 200 rnA of Vpp current at an efficiency
of 88%. The supply can be switched into a shutdown
mode where the output voltage falls to approximately
VIN - 550 mV and the quiescent supply current falls
to below 15 J.LA. The LT1301 also has an input which
selects between a 5V and 12V output, for flexibility in
migration to Smart Voltage flash memory. The high
switching frequency of the MAX761 allows the use of
very small external capacitors and contributes to the
small size of the supply circuit. Series inductance in the
filter capacitor and diode switching transients may
cause high-frequency noise which appears as sharp
voltage spikes in the output. Such spikes can be eliminated by practicing good PC-board layout or by using
the optional filter circuit shown in the design. Applications assistance is available from Linear Technology
Corporation.
2-33
AP-357
Table 3-5. Parts List for the LT1301 5V to 12V Converter
Part #
Ref
Value/Type
Source
Cost·
U1
LT1301CS8
SMPSIC
Linear Tech
(408) 432-1900
$2.40
C1
267M1002-107·MR-720
100 J-LF!10V
Tantalum
Matsuo
(714) 969-2491
$0.35
C2
267M1602-476cMR-720
4 J-LF!16V
Tantalum
Matsuo
(714) 969-2491
$0.35
C3 (opt)
GRM40Z5U104M050AD
0.1 J-LF
Murata Erie
(404) 436-1300
$0.05
01
EC10QS02L
1N5817 Diode
Nihon
(805) 867-2555
$0.22
L1
CD75-220KC
22J-LH
Sumida
(708) 956-0666
$0.63
R1, R2 (opt)
9C08052A 1ROOJLR
10,5%
Philips
(817) 325-7871
$0.03
Total Cost
$4.03
~
• Cost estimates based on published 10K unit pricing at the time this application note was wntten.
3.6 Motorola MC34063A: Vpp
@
120 mA
SHUTDOWN - - - - - - - - - - - - - - - - - ,
Dl (MBRSI20T3)
II
47!,H
SUMIDA
CD54-470
R4
3k,5%
Ul
1
.--_ _ _-'2;-1
.--_ _....::3~
C 1 300pF
4
gln,5%
SWC COll 8
SWE IPKS t-:~;----t
TCAP Vee 1-i5;---~
GND COMP
In,5%
MC34063AD
R3
172k, 1%
...............-
20k,l%
Vpp @ 120mA
R2
In,5%
C2
33!'F!16V
TANTALUM
+
"1'
...J..
C4
O.I!,F
I
OPTIONAL
FilTER
._-------
292092-4
FIgure 3-6. Motorola MC34063A 5V to 12V Converter
2-34
I
AP-357
Optimal Attributes
• Low Cost
• Low Shutdown Current
• All Surface Mount
Main Features
• Input Voltage Range: 4.SV to S.SV
• Output Voltage: 12V ± S%
• Output Current Capability:
Up to 120 mA @ VIN = SV
• Typical Efficiency: 80% @ ILOAD = 120 mA,
VIN = SV
• 100 KHz Switching Frequency
• Shutdown Feature using External Components
• Low Quiescent Current at Shutdown: 2S J.LA typical
• Rise Time from Shutdown: 2 ms typical
The MC34063A solution presented uses 11 small sized
external components to implement a low cost surface
mount SV to l2V converter solution. Three external
components (U2, R4, RS) are used to shut down supply
to the part when Vpp is not needed. These could be
eliminated to further lower the cost if power consumption is not important. The quiescent current in shutdown state is 2S J.LA. The output voltage in shutdown is
approximately VIN-SSO mY. Series inductance in the
filter capacitor and diode switching transients may
cause high-frequency noise which appears as sharp
voltage spikes in the output. Such spikes can be eliminated by practicing good PC-board layout or by using
the optional filter circuit shown in the design. Applications assistance is available from Motorola.
Table 3-6. Parts List for the MC34063A 5V to 12V Converter
Ref
Part #
Value/Type
Source
Cost'
U1
MC34063A
SMPS IC
Motorola
(800) 521-6274
$0.85
U2
MMBT4403LT1
PNP Transistor
Motorola
(800) 521-6274
$0.10
C1
267M 1002-336-M R-720
33 J.LF/10V
Tantalum
Matsuo
(714) 969-2491
$0.24
C2
267M 1602-336-M R-720
33 J.LF/16V
Tantalum
Matsuo
(714) 969-2491
$0.24
C3
GRM40X7R330M050AD
330 pF
Murata Erie
(404) 436-1300
$0.08
C4 (opt)
GRM40Z5U104M050AD
0.1 J.LF
Murata Erie
(404) 436-1300
$0.05
D1
MBRS120T3
Schottky Diode
Motorola
(800) 521-6274
$0.37
L1
CD54-470LC
47 J.LH
Sumida
(708) 956-0666
$0.55
R1
9C08052A9100JLR
91n,5%
Philips
(817) 325-7871
$0.02
R2
9B08053A 1723FCB
172 Kn, 1 %
Philips
(817) 325-7871
$0.03
R3
9B08053A2002FCB
20 Kn, 1%
Philips
(817) 325-7871
$0.03
R4
9C08052A3001JLR
3 Kn, 5%
Philips
(817) 325-7871
$0.02
R5
QC08052A1002JLR
10 Kn, 5%
Philips
(817) 325-7871
$0.02
R6, R7 (opt)
9C08052A 1 ROOJLR
1n,5%
Philips
(817) 325-7871
$0.03
Total Cost
$2.63
• Cost estimates based on published 10K unit pricing at the time this application note was written.
I
2-35
AP-357
4.0
voltage is down near 1.8V. Currently there exist two
good solutions that achieve a 12V output with inputs as
low.as 1.8V, and yet supply at least 30 rnA of current.
These are the LT1301 from Linear Technology Corporation, and the MAX76 I from Maxim Integrated Products.
Vpp SOLUTIONS: CONVERTING
UP FROM 2 NiCdlALKALINE
CELLS
Palmtop computers that use 2 alkaline/NiCd batteries
require that the system work even when the battery
4.1 Maxim Integrated Products-MAX761: Vpp
@
75 mA
VIN (3V-12V)
L1
18 pH
----------- ..
Rl
2
01
V+ ...8::..-_--.
LBO
lN5817
LX ...7;....._--11--<..........._ ......_ ..... 1 n, 5% ......_ _ _' - Vpp @ 75 rnA
R2
LBl
GNO
SHUTDOWN _ _ _.;;:;4... SHDN
REf
6
I
-= -=
C5
O• 1 pF
- - - -... -LC3
I.tAX761CSA IO.1 J.<
enm
"'0
::D
m
m
en
z
-t
m
o
--
-
€:
@l
Ap·357
APPENDIX C
SOURCES/CONTACTS FOR RECOMMENDED
DC-DC CONVERTERS
Linear Technology Corporation
Recommended Products:
- LT1109-12 (DC-DC Converter IC)
- LT1111-12 (DC-DC Converter IC)
- LT1301 (DC-DC Converter IC)
In U.S.A.:
1630 McCarthy Blvd.
Milpitas, CA 95035-7487
Tel: (408) 432-1900
Fax: (408) 432-0507
In Asia (Japan):
Maxim Japan Co., Ltd.
Tel: 81 (03) 3232-6141
Motorola Semiconductor Inc.
Recommended Product:
- MC34063AD (DC-DC Converter IC)
In U.S.A.:
616 West 24th Street
Tempe, AZ 85282
Tel: (800) 521-6274
In Europe (U.K.):
111 Windmill Road
Sunbury
Middlesex TW 16 7EF
U.K.
Tel (44)(932) 765688
Fax (44)(932) 781936
In Asia (Japan):
4F Ichihashi Bldg
1-8-4 Kudankita Chiyoda-ku
Tokyo 102 Japan
Tel (81) (03) 3237-7891
Fax (81) (03) 3237-8010
Maxim Integrated Products
Recommended Products:
- MAX662 (DC-DC Converter IC)
- MAX667 (DC-DC Converter IC)
- MAX734 (DC-DC Converter IC)
- MAX756 (DC-DC Converter IC)
- MAX761 (DC-DC Converter IC)
In U.S.A.:
120 San Gabriel Drive
Sunnyvale, CA 94086
Tel (408) 737-7600
Fax (408) 737-7194
In Europe (U.K.):
Maxim Integrated Products (UK), Ltd.
Tel: (44) (734) 845255
I
In Europe (U.K.):
Tel: (44) (296) 395-252
In Asia (Japan):
Tel: (81) (3) 440-3311
National Semiconductor
Recommended Product:
- LM2940CT-12 (Voltage Regulator IC)
In the U.S.:
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052
Tel: (408) 721-5000
In Europe:
National Semiconductor (UK) Ltd.
The Maple, Kembrey Park
Swindon, Wiltshire SN26UT
U.K.
Tel: (07-93) 614141
Fax: (07-93) 697522
In Asia:
National Semiconductor Japan Ltd.
Sanseido Bldg. 5F
4-15 Nishi Shinjuku
Shinjuku-ku
Tokyo 160 Japan
Tel: (81) (3) 299-7001
Fax: (81) (3) 299-7000
2-49
Ap·357
Newport Componentsl
International Power
Recommended Product:
- NMF0512S (5V-12V Converter Module)
In U.S.A.:
International Power Sources
200 Butterfield Drive
Ashland, MA 01721
Tel: (508) 881-7434
Fax: (508) 879-8669
In Europe:
Newport Components
4 Tanners Drive
Blakelands North
Milton Keynes MK14 5NA
Ttil: (0908) 615232
Fax: (0908) 617545
Shindengen Electric Co. Ltd.
Recommended Product:
- HDF0512D (12V unreg. to 12V reg. converter
module)
In the U.S.:
2649 Townsgate Road #200
Westlake Village, CA 91361
Tel: (800) 634-3654
Fax: (805) 373-3710
In Europe:
Shindengen Magnaquest U.K: Ltd.
Unit 13, River Road,
Barking Business Park,
33 River Road, Barking,
Essex IGll ODA
Tel: (44) (81) 591-8703
Fax: (44) (81) 591-8792
2-50
In Asia:
.
2-1,2-Chome Ohtemachi
Chiyoda-ku
Tokyo 100
Japan
Tel: (81) (3) 279-4431
Fax: (81) (3) 279-6478
Valor Electronics, Inc.
Recommended Product:
-PM6064
In U.S.A.: .
9715 Business Park Avenue
San Diego, CA 92131-1642
Tel: (619) 537-2500
Fax: (619) 537-2525
In Europe:
Valor Electronics GmbH
Steinstra/3e 68
81667 Munchen
Germany
Tel: (49) (89) 480-2823
Fax: (49) (89) 484-743
In Asia:
Valor Electronics, Ltd.
Room 510, 5th Floor
1 Kornhill Road, Kornhill Metro Tower
Quarry Bay, Hong Kong
Tel: (852) 513-8210
Fax: (852) 513-8214
Xentek Inc.
Recommended Product:
- NPSC0512S (5V-12V Converter Module)
In U.S.A.:
760 Shadowridge Drive
Vista,· CA 92083
Tel: (619) 727-0940
Fax: (619) 727-8926
I
AP·357
In Europe (Germany):
Xentek, Inc.
c/o Taiyo Yuden GMBH.
Obermaierstrasse 10,
D-85oo Nurnberg 10
Federal Republic of Germany
Tel: (49) (911) 350-8400
Fax: (49) (911) 350-8460
In Asia (Japan):
Xentek, Inc,
c/o Taiyo Yuden., Ltd.
6-16-20, Ueno, Taito-ku
Tokyo 110
Japan
Tel: (81) (3) 3837-6547
Fax: (81) (3) 3835-4752
I
2-51
Ap·357
APPENDIX D
CONTACTS FOR DISCRETE COMPONENTS
Matsuo Electric Co., Ltd.
Matsuo's 267 series surface mount tantalum, chip capacitors are recommended by Maxim and Linear Technology for input and output filter capacitors on their
DC-DC converters. Part #s are included on the parts
list that' accompanies most solutions. If alternate
"equivalents" are required, choose high reliability, low
ESR (Equivalent Series Resistance) and low ESL
(Equivalent Series Inductance) type tantalums, which
help in keeping output ripple and switching noise to a
minimum.
In U.S.A.:
2134 Main St., Ste. 200
Huntington Beach , CA 92648
Tel: (714) 969-2491
Fax: (714) 960-6492
In U.S.A.:
637 East Golf Road
Suite 209
Arlington Heights, IL 60005
Tel: (708) 956-0666
Fax: (708) 956-0702
In Asia:
4-8 Kanamachi 2-chome,
Katsushika-ku,
Tokyo 125
Japan
Tel: (81) (03) 3607-5UI
Fax: (81) (03) 3607-5428
Coiltronix Inc.
In Europe:
Steucon - Center II Mergenthalleralle 77
D-6236 EschbenlTs.
Federal Republic of Germany
Tel: 6196-470-361
Fax: 6196-470-360
Coiltronix is recommended as, a good alternate source
for surface mount inductors. The CTX series offered by
Coiltronix is well suited to DC-DC converter applications. These are shielded, and have a toroidal core.
However, they are bigger in size and currently much
more expensive (7X to 8X) than the Sumida varieties
recommended in the solutions herein. The equivalent
part numbers are:
In Asia:
Oak Esaka Bldg.
10-28 Hiroshiba-Cho
Suita-shi
Osaka 564
Tel: (06) 337-6450
Fax: (06) 337-6456
Sumida
Sumida
Sumida
Sumida
Sumida
<
Sumida ElectriC Co. Ltd.
Sumida CD series surface mount inductors are recommended by Maxim, Linear Technology for their miniature size and relatively low cost. These are well suited
to low power DC-DC converter applications. Contact
Sumida Electric directly for procuring these. The part
#s are included in the parts list that accompanies most
solutions. In applications where noise (EMI) is a concern, shielded varieties are also offered by Sumida.
2-52
CD54-470 - Coiltronix CTX50-1
CD54-180 - Coiltronix CTX20-1
CD54-220 - Coiltronix CTX20-1
CD75-470 - Coiltronix CTX50-2
CDR105-470 - Coiltronix CTX50-2
In U.S.A.:
Coiltronix Inc.
984 S.W. 13th Court
Pompano Beach, FL 33069
Tel: (305) 781-8900
Fax: (305) 782-4163
In U.K.:
Microelectronics Technology Ltd.
Great Haseley Trading Estate
Great Haseley
Oxfordshire OX9 7PF
U.K.
Tel: (08) 44 278781
Fax: (08) 44 278746
I
AP-357
In Asia:
Serial System Mktg.
Poh Leng Bldg., #02-01
21 Moonstone Lane
Singapore 1232 .
Tel: 2938830
Fax: 2912673
Coilcraft
Coilcraft is also recommended as a good alternate
source for surface mount inductors. The N2724-A
shielded series is well suited to DC-DC converter applications. These are bigger and currently more expensive
(2x to 3x) than the Sumida inductors recommended in
the solutions. Contact Coilcraft directly for any applications assistance or for prcicurement of these parts.
The equivalent part niunbers are:
Sumida CD54-470 -+ Collcraft N2724-A 47 ,...H
Sumida CD54-180 -+ Collcraft N2724-A 18 ,...H
Sumida CDRI05-470 -+ Coilcraft N2724-A 47 ,...H
In the US:
1102 Silver Lake Road
Cary , IL 60013
Tel: (708) 639-6400
Fax: (708) 639-1469
In Europe:
21 Napier Place
Wardpark North
Cumbernauld
Scotland G68 OLL
Tel: 0236 730595
Fax: 0236 730627
In Asia:
Block 101, Boon Keng Road
#06-13/20
Kallang Basin Industrial Estate
Singapore ·1233
Tel: 2966933
Fax: 2964463
Philips Components
Philips Components is recommended as a good source
for surface mount (SMD) resistors (standard 9C series,
and 9B (MELF) series). Part #s are included in the
parts list that accompanies most of the solutions in the
application note. Many alternate sources exist.
I
In the US:
2001 W. Blue Heron Blvd.
P.O. Box 10330
Riviera Beach, FL 33404
Tel: (407) 881-3200
Fax: (407) 881-3304
In Europe:
Philips Components Ltd.
Mullard House
Torrington Place
London WCIE 7HD
Tel: (44) 71 580 6633
Fax: (44) 71 6360394
In Asia:
Philips K.K.
Philips Bldg. 13-37
Kohnan 2-chome
Minato-Ku Tokyo 108
Tel: (81) 3 740-5028
Fax: (81) 3 740-5035
Siliconix-Logic Level PFETs
Siliconix offers low-"on" resistance logic level PFETs
(Si9400, and Si9405) that can be used for switching a
DC-DC converter into a shutdown state by using these
switches on the high side of the input to the converter
(see Appendix E).
In the US:
2201 Laurelwood Road
P.O. Box 54951
Santa Clara, CA 95056-9951
Tel: (408) 988-8000
Fax: (408) 727-5414
In Europe:
Weir House
Overbridge Square, Hambridge Lane
Newbury, Berks RG14 5UX
Tel: (0635) 30905
Fax: (0635) 34805
In Asia:
Room 709, Chinachem Golden Plaza
77 Mody Road
TST East Kowloon
Tel: (852) 724-3377
Fax: (852) 311-7909
2-53
AP·357
APPENDIX E
OTHER DESIGN CONSIDERATIONS
Vpp Valid Handshake Logic
It is often desirable to have, along with the Vpp solution, a handshake signal (using extra hardware) that is
asserted as long as the voltage level on Vpp is valid.
The following schematic illustrates a good way of
achieving this. This handshake signal could be used to
determine when it is suitable to perform writes/erases
on the flash device. The circuit sho~n useS a precision
zener voltage reference and a comparator, along with
bias resistors, to monitor the voltage level on Vpp. The
point at which the comparator trips must be set after
careful consideration of the variation in the reference
voltage and the tolerances on the bias resistors. The
worst case conditions on these variations must guarantee that the handshake signal is asserted when Vpp is at
its worst case lower-end level (11.4V). Care must be
taken to use the exact Same components as specified in
order to maintain the tight tolerance on the trip level of
the output signal.
Obtaining Shutdown Using Logic Level
PFETs
Low "on" resistance logic level PFETs can be used on,
the high side of the input to the DC-DC converters to
obtain shutdown. One such part is the Si9405 from Siliconix Inc. The device is part of the "little foot" series,
and is available in anS08 (8-pin surface mount) package. The Si9405 is a logic level PFET with an "on re-
Vpp
sistance" of 0.20 (at a gate drive of 4.5V). It is important to have as Iowan "on" resistance as possible, since
the peak currents and start-up currents into the supply
are high. Care must be taken to ensure that the DC-DC
conversion process is not affected after accounting for
the drop in input voltage across the PFET.
Working of the Discrete Step Up
Switching Regulator
'
This section presents a brief overview of the operation
of discrete' step up switching regulators, and presents
issues that the user needs to be concerned with while
designing these solutions into the system. '
The four most basic elements of a discrete switching
regulator power supply are:
'
1. The SMPS IC (which includes the switch control
element and logic, along with the power switch itself),
2. An inductor for storage and transfer of energy between the input and output,
3. A switching diode to direct the inductor energy to
"catch", or channel, the inductor energy to the output, and
4. An output filter capacitor.
Vee
R1
107k,0.1%
>-U;"1- - Vpp VALID#
R2
12.4k,0.1%
01:LINEAR TECHNOLOGY CORP LT1004-1'.2
U1:LlNEAR RECHNOLOGY CORP LT1017CN8
292092-13
Figure E-1. Vpp Valid Handshake Circuit
2-54
I
AP-357
In the boost configuration where the output voltage is
greater than the input voltage, the basic switching power supply configuration is as shown in Figure E.2:
o
r--rT'l'T"'---'--I~-.....-
VOUT
292092-14
Figure E-2. Working of the Step-Up
SWitching Regulator
The power switch SW can be turned on and off, the
control for it is derived from a feedback mec~
that senses the output voltage. While the switch is
turned on, the inductor stores energy as the current
flows through it from the input supply. The peak current through the inductor IL can be approximated as
(V!NIL • toN); where toN is the on time of the switch.
During this time, the energy is supplied by the input
voltage, VL = VIN. The output is isolated from the
inductor via the reverse-biased diode, and the load current is supplied by the output filter capacitor. When the
switch turns off, the energy stored in the inductor appears as a rapidly increasing voltage across the inductor. AI. soon as this voltage reaches a value equal to the
outpu~ voltage plus the voltage drop across the diode,
the diode switches on at).d current starts to flow
through the diode. This diode current supplies the load
current while also at the same time charging up the
output filter capacitor to the output voltage.
'J?le switch is controlled by sensing the output voltage
via a feedback mechanism-usually a pair of resistors.
This sense voltage is gated via a comparator whose output acts as a control signal to an oscillator. The oscillator output controls the switch.
The power into the inductor PL can be approximated
as:
and the power into the load PLOAD (out of the inductor) can be approximated as
PLOAD = (VOUT
I
+ Vo
- VIN) • lOUT
The peak currents through the inductor is usually several times higher than the load current, is mostly of the
value of the load ~urrent and builds up during time
toN' On most of the solutions presented here, peak operating currents lie in the range of 500 rnA to 1.2A.
Though this may seem high, most of this in-rush of
energy is transferred to the output, and little is lost to
heat due to the efficient energy storage characteristic of
indu~tors. Note that since the peak currents are high,
!he m1?ut voltage source must be capable of providmg this current, and the current capability of the
input source must not be calculated simply as
(VOUT • IOUT)/(VIN • Etl). A large bypass capacitor
at the input pin of the converter is hence also necessary
on all designs.
Some of the solutions presented in this application note
are of the fixed duty cycle or fIXed on time type (e.g.
LTll09-12, MC34063A), whereas some of them vary
the duty cycle depending on the load current (e.g.
MAX734). These latter ones provide higher efficien. cies.
Inductor Selection
The choice of an inductor is crucial to the design of the
power supply system. To begin with, the inductor value
must be low enough to supply the peak currents needed
when the ~put voltage VIN, as well as the on time ton,
are at therr worst case low value. On the other hand
the indu~tor value must be high enough so that th~
peak currents at the worst case high values do not exceed the maximum peak currents that can be handled
by the switch. Furthermore, once the value has been
picked, the physical inductor that is chosen for the job
must be able to handle these peak currents, and must
not saturate. This is done by picking an inductor whose
DC current rating is more than the worst case peak
current that will be required by the operation of the
device. The other characteristic to consider is the resistance of the inductor. In order to keep losses to a minimum, it is essential that the resistance of the coil is a
minimum. Thus, it is important to use the inductors
s!,ecified in the parts list that accompanies the solutions. These have been carefully chosen after reviewing
the requirements. Alternate inductors may be used, as
long as they are "equivalent".
EMI Concerns
Since the switching regulators presented in this application note switch at frequencies between 100 KHz and
500 KHz, there exists a potential for EMI. In cases
where EMI may be a problem, shielded inductors can
be used. This will reduce EMI significantly. Shielded
versions of the inductors specified are readily available.
Contact the vendor directly for these.
2-55
AP-357
Output Switching Noise
Output switching noise has several sources. The most
sigilificant one is the IR drop through the ESR (Equivalent Series Resistance) of the output filter capacitor..
This is caused by switching current pulses from the
inductor. There is also noise in the form of switching
spikes riding on the DC output. This is due to the output filter capacitor's ESL (Equivalent Series Induc.tance), current spikes in the ground trace and rectifier
turn-on transients.
It is important to use low ESR and low ESL output and
_input filter capacitors. Proper layout is also essential in
order to avoid spikes in the output. The safest solution
is to use a filter circuit at the output. LC filters are not
recommended, because of the transient nature of the
load currents on flash devices. An RC filter is recommended on most solutions as an option. Two In resistors are used in parallel to avoid causing a significant
drop across the resistance. This method is inexpensive
and assures that the spikes riding on the output waveform are contained to within the 5% tolerance requirement on Vpp.
In addition, care must be taken to keep the leads from
the output of the solution to all flash devices as short as
possible. Use of a 0.1 ,..,F capacitor at the Vpp pin of
each flash device is highly reconrinended.
.
Working of the Discrete Charge-Pump
DC-DC Converter
.
The three most basic elements of a discrete chargepump DC-DC converter are:
1. The charge-pump IC (which includes the internal
charg&-pumps as well as output regulation logic),
2. External capacitors to store energy from the input,
and
3. An output filter capacitor.
The basic charge"pump power supply conftguration is
as shown in Figure E.3 (a).
The S I and S2 switches can be opened and closed; the
control is derived from a feedback mechanism that senses the output voltage. When the SI switches are open,
the S2 switches are closed, and vice versa. When the S I
switches are closed (Figure E.3 (b», capacitors CI and
C2 are charged to VIN. When the S2 switches are
closed (Figure E.3 (c», capacitors CI and C2 are connected in series betWeen VIN and VOUT' This triples
the input voltage, with the feedback scheme in the
charge-pump IC adjusting the output voltage to 12V.
During one cycle, energy is transferred from the input
to the external charge-pump capacitors. (SI switches
clOsed), and then from the charge-pump capacitors to
the output filter capacitor and the load (S2 switches
closed).
The S I and S2 switches are controlled by sensing the
output voltage via a feedback mechanism. This sense
voltage is gated via a comparator whose output acts as
a control signal to an oscillator. The oscillator output
controls the S2 switches, and the inverted oscillator
output controls the SI ·switches.
. This section provides a brief overview of the operation
of discrete charge-pump DC-DC converters.
2-56
I
AP-357
YIN
0---------,
,.----------IS1
-.,
~>-----+--+--......
I
I
C1
52
---0
I
I
I
I
YOUT
COUT
51
1.. _ _ _ _ _ _ _ _ _ _ _ _ _
292092-30
(a)
YIN
0----------,
YIN
0-------:-----,
,.------- -,
,.------
-,
~-'------+_-L-.....-__o YOUT
I
C1
COUT
l
I
I
C2
T:
C2
L....!-I---l"""l
I
ILo
L. _ _ _ _ _ _ _ _
292092-32
(c) S2 Switches Closed
________ _
292092·31
(b) S1 Switches Closed
Figure E-3. Working of the Charge-Pump DC-DC Converter
I
2·57
AP-357
APPENDIX F
PC LAYOUTS FOR SOME RECOMMENDED SOLUTIONS
Maxim Integrated Products MAX662
Maxim Integrated Products MAX761
The double-sided layout presented below (Figure F-l)
has been designed for the MAX662 5V -12V converter
solution (Section 3.3). It has been designed for the parts
specified in the parts list that accompanies the solution.
Contact Maxim for any additional layout assistance.
The double-sided layout presented below (Figure F-3)
has been designed for the MAX761 3.3V/5V-12V converter solution (Sections 3.2 and 4.1). It has been designed for the parts specified in the parts list that accompanies the solution. Contact Maxim for any additional layout assistance.
Maxim Integrated Products MAX734
The double-sided layout presented below (Figure F-2)
has been designed for MAX734 5V-12V converter solution (Section 3.1). It has been designed for the parts
specified in the parts list that accompanies the solution.
Contact Maxim for any additional layout assistance.
Linear Technology Corporation
LT1109-12
The single-sided layout presented below (Figure F-4)
can be used to implement the LTl109-12 5V-12V converter solution (Section 3.4). The layout has been designed for the parts that are specified in the parts list
that accompanies the solution. Contact Linear Technology for any additional layout assistance.
(1X Scale Top Side Trace View)
Surface Mount Drilling Guide (1X Scale)
+z +z
M
+z
+
M
+z
+z
M +z+z+z
SIZE
QTY
SYM
20
I
+
lOa
4
M
35
9
Z
+z
M
292092-17
-
(1X Scale Bottom Side Trace View)
292092-15
•
•
•. ~_I.
(Component Placement Diagram)
_
v _
our
,••,C5_
MAXIM'[:lS r-II~
~
C2r-1
REV C
~C3' • • , C4
I •
2•
3,
_,•
_ VIN
10/9~1
292092-18
_
MAX662 EVALUATION BOARD
292092-16
Figure F·1
2-58
I
Ap-357
(1X Scale Top Side Trace View)
ll
r
I:•
••
I
(1X Scale Bottom Side Trace View)
IIi
ll
r
IIi
I
•
II.J
r_
_i
292092-19
292092-20
(1X Scale Component Placement Diagram)
_
MAX734 EVKit
l eI
L1
n="
"':: u:.
n fr .
I ...".".
·
e
L
8/92
_
MAXIM
MADE IN USA
~
I;;t :
REV·e
-
.J
292092-22
FlgureF-2
I
2-59
AP·357
(1X Scale Top Side Component
Placement Diagram)
•
•
MAX761
EVALUAliON 80ARD
V+
••
•
L81_
~
ul.I.C5.1~~
::rul= ~_
01
~
•
(_)Ll
_VOUT
_VIN
I• • 1
L80_
JU31 • • • 1
U
C3
1 2 3
SHDN _
[ ; ] JU2
C;+
GND
MAXIM
•
REV 8
MADE IN THE USA
11/93
SMH
•
292092-33
(1X Scale Top Side
Trace View)
292092-35
Figure F·3
2·60
I
AP-357
•
(1X Scale Bottom Side
Component Placement Diagram)
- .-
•
III
•
•
292092-34
(1X Scale Bottom SideTrace View)
292092-36
Figure F-3
I
2-61
AP-357
(1X Scale Surface Mount Drilling Guide)
x
XX
+
X
XX
+
XX
XX
+
XX
XXX
XX
XX
SIZE OTY SYM
20
3
+
37
21
X
125
4
X
292092-37
Figure F-3
(2X Scale Trace View)
(2X Scale Component Placement Diagram)
@]
8m
le21
292092-25
292092-26
(1X Scale Trace View)
I
2-62
,~" ,_"
(1X Scale Component Placement Diagram)
@)
0c
8@)
292092-28
Figure F-4
I
AP-357
Revision History
Version
I
Description
001
Original Version
002
Added MAX734, MAX761, MAX662, MAX756, LT1301, PM6064. Deleted MAX732, LT111 0,
MAX658.
2-63
AP-374
APPLICATION
NOTE
Flash Memory Write
Protection Techniques
BRIAN DIPERT
SENIOR TECHNICAL MARKETING ENGINEER
September 1993
2-64
I
Order Number: 292123-001
Flash Memory Write Protection Techniques
CONTENTS
PAGE
1.0 INTRODUCTION .................... 2-66
2.0 WHY IS WRITE PROTECTION
IMPORTANT? ........................ 2-66
CONTENTS
PAGE
5.0 PREVENTING UNINTENDED
WRITES DURING NORMAL SYSTEM
OPERATION ......................... 2-67
3.0 SYSTEM WRITES WITH BULK·
ERASE FLASH MEMORIES .......... 2-66
6.0 PREVENTING UNINTENDED
WRITES DURING SYSTEM
POWERUP/POWERDOWN AND
RESET ............................... 2-68
4.0 SYSTEM WRITES WITH
BOOTBLOCK AND FlashFile™
MEMORIES ........................... 2-67
6.1 Designing for Flash Memory
System Power Sequencing
Protection .......................... 2-69
7.0 SUMMARY .......................... 2-70
I
2-65
AP-374
1.0
INTRODUCTION
Flash memory's combination of nonvolatility and easy
in-system updateability are key attributes driving its
adoption into today's system designs. However, this
flexibility also brings with it the responsibility (for
hardware and software engineers) to ensure that writes
to flash memory occur only when intended. This is especially important for those who are accustomed to designing with various ROM (nonvolatile but non-updateable) and RAM (updateable but volatile) memories.
This application note discusses techniques for proactively designing systems to prevent unintentional writes
to flash memory. These design techniques are by no
means complex or costly, but their implementation is
crucial to ensuring reliable operation through system
lifetime. For more information on the devices and specifications discussed in this document, please consult
specific flash memory datasheets.
2.0
WHY IS WRITE PROTECTION
IMPORTANT?
Let's begin by identifying the key characteristics of two
generic memory technologies: ROM (Read-Only-Memory) and RAM (Random-Access-Memory). Flash
memory combines many of the Capabilities of both in
one solution. Therefore, it is often being utilized to replace ROM and/or RAM in new designs. At a minimum, flash memory's status as a relatively new technology means that many engineers are moving to it
from the familiarity of a ROMIRAM knowledge base.
RAM is fully alterable on a bit-by-bit basis, and the
mechanism for writing to it is established and well understood. RAM is in-system updateable, yet it is volatile. This means that when a RAM memory loses power, it also loses its data. RAM is guaranteed not to
contain valid information on powerup.
ROM offers the advantage of nonvolatility, i.e. when
power is removed from the device, the information
stored inside is retained. However, ROM is not in-system updateable. Once the information is initially put
into the device, it is permanent and unchangeable. To
replace the information, you have to physically remove/replace the device itself.
Traditional system memory architectures often included both ROM (nonvolatile but non-updateable) and
RAM (volatile but in-system updateable). The new
model for system design retains some RAM for temporary data storage, but replaces the rest of RAM and
ROM with flash memory. Being both nonvolatile and
in-system updateable, flash memory encompasses the
2-66
strengths of both RAM and ROM, offering new system
architecture possibilities. However, whereas in the past
RAM was guaranteed to be invalid on system powerup
and ROM was guaranteed to be unalterable, the same
cannot be said for flash memory.
Any alteration of flash memory contents (whether
planned or unintended) is permanent regardless of system power transitions, until the data is again modified.
As we'll see later, command writes to flash memory can
also put it in modes where it outputs something other
than array data, a non-permanent but still undesirable
condition when not intended. This means that the system hardware and software must ensure that flash
memory is written only when specifically desired, to
ensure a predictable system environment. The following
sections will discuss how this can be accomplished.
3.0 SYSTEM WRITES WITH BULKERASE FLASH MEMORIES
First-generation bulk erase flash memories from Intel
Corporation are shown in Figure 1. These devices automatically power up in a "Read Array" mode in which
they output array data when read. Transitions to alternate modes occur by writing commands to the flash
memory.
Device
Density
28F256A
32 Kbytes (x8)
28F512
64 Kbytes (x8)
28F010
128 Kbytes (x8)
28F020
256 Kbytes (x8)
Figure 1. Intel Corporation
Bulk-Erase Flash Memories
Bulk-erase flash memories include several forms of
"protection" to guard against unintended writes.
Writes with Vpp (the program/erase voltage) at VPPL
(OV to 6.5V) are disregarded by the flash memory. Similarly, write attempts with Vee at or below VLKO
(2.5V on most devices) are ignored. Finally, these devices require multi-byte command sequences to initiate
internal program or erase algorithms. Note, however,
that while the erase command sequence (shown in Figure 2) requires both the proper Erase Setup and Erase
Confirm commands, the program sequence (Figure 3)
relies only on the valid Program Setup command. The
second command in the latter sequence can have any
value, and is interpreted as data to be programmed.
This means that if the flash memory receives an unintended Program Setup command, the very next write to
the device (intended or not) will be interpreted as program data and initiate an internal program event (if
Vpp is above VppV.
I
Ap·374
BOOT BLOCK ARCHITECTURE
Erase Setup
Device
(20H)
Density
28FOO1BX
128 Kbytes (x8)
28F200BX
256 Kbytes (x16)
:.:.:.:.:.:.:.:.:.:.:.:.:.;.:.;.:.:.
28FOO2BX
256 Kbytes (x8)
28F400BX
512 Kbytes (x16)
28FOO4BX
512 Kbytes (x8)
FlashFile™ ARCHITECTURE
Beyond the program and erase sequences, the Read Intelligent Identifier Codes command will, when written
to the flash memory, put it in a mode where it outputs
device signature IDs instead of array information when
read.
Density
1 Mbyte (x8)
Figure 4. Intel Corporation
Block-Erase Flash Memories
292123-1
Figure 2. Flash Memory Erase
Command Sequence (Simplified)
Device
28FOO8SA
For full access to the flash memory Status Register, as
well as for enhanced interface to internal device identifiers, these block-erase flash memories will accept commands written to them regardless of Vpp voltage, as
long as Vee is above VLKO. Program and erase algorithms initiated by command sequences will terminate
with Status Register error indication and unaltered array data, ifVpp is at VPPL. However, regardless ofVpp
level, the device will still transition to a "Read Status
Register" mode after program/erase command sequences are written. In this case, it will output data that
the system, if the write was unintended, will not expect.
The same multi-byte command sequences (shown in
Figures 2 and 3) are used as in bulk-erase flash memories.
Boot Block and FlashFile memories provide commands
(in addition to the program and erase sequences) which
transition the memory to alternate modes, outputting
data other than array information for subsequent reads.
In this respect, they are similar to bulk-erase flash
memory discussed earlier. These commands are Intelligent Identifier and Read Status Register.
292123-2
Figure 3. Flash Memory Programming
Command Sequence (Simplified)
4.0
SYSTEM WRITES WITH BOOT
BLOCK AND FlashFile™
MEMORIES
Second-generation block-erase Boot Block and FlashFile memories from Intel Corporation are shown in
Figure 4. They function similarly to the bulk-erase devices described earlier, with a few key enhancements.
As before, these devices automatically power up in
"Read Array" mode, and transition to alternate modes
via command writes.
I
Block-erase devices include a hardware input called
RP# (or ResetiPowerdown). Among its many uses,
this pin acts as a "master on/off switch" to completely
disable the flash memory and lock all other control inputs. RP# is extremely effective at blocking unintended writes during system power transitions. This technique will be covered in detail, in a few paragraphs.
5.0
PREVENTING UNINTENDED
WRITES DURING NORMAL
SYSTEM OPERATION
Preventing unintended writes to flash memory during
normal system operation is a routine part of debugging
a new design, and a common concern for any "writeable" device on the processor interface. Any combina2-67
AP-374
tion of active chip select (CE#) and active write enable
(WE#) has the potential of being decoded by the flas~
memory as a valid write attempt. One common culpnt
in these situations is the chip select decoder logic (PAL,
etc.) between the processor and external devices. As
addresses propogate through this logic at the beginning
of an access cycle, or in the undefined address state
between accesses, spurious chip selects of indeterminate
duration can be generated. System hardware should ensure that at these times, WE# to flash memory stays at
a logic "I" and doesn't transition low.
So~e concern has also been expressed in the past about
unintended writes in certain "open" systems such as
the personal computer. In these environments, the type
and function of software run on the machine is beyond
the control of the computer manufacturer, who must
accordingly design his!her hardware. For example, a
third-party software utility may write to flash memory
assuming DRAM at that location. More malicious, of
course, is the case of the computer virus. Fortunately,
in cases like this, hardware design to prevent unintended writes is fairly simple.
WR# (FROM SYSTEM)
GPIO
~
~
WE# (TO FLASH
MEMORY)
VO~~:~~ ----1r---t:;--,
MAX734
ON/OFF#
SHDN#
Vour
GND
t-"""---""""1 +
cc
292123-4
Figure 6. Vpp 12V Converter with
Integrated Switch (Example)
In a traditional "closed" system, the software directing
the hardware is totally under control of the system
manufacturer. No additional effort should be needed
(after the initial prototype hardware and soft~are debugging) to protect the flash memory from uruntended
writes during normal system operation. Write control
during system powerup and powerdown also requires
attention, however; a topic covered next.
292123-3
Figure 5. WE # Gating
Figure 5 shows one means of clarifying the WE# signal. When flash memory is used for BIOS storage, for
example, the manufacturer's update utility is the only
software that should be writing to the device. By toggling the general purpose I/O line (whose default state
is, of course, "disabled"), the update utility can control
whether writes from the system are blocked or allowed
to pass to the flash memory. This type ofWE# clarifying function is integrated in the Inte1386TMSL and Intel486TMSL Microprocessor Supersets. ASICs integrating motherboard functions should also be designed to
include such logic.
One other method for preventing flash memory alteration is by controlling (or "switching") the Vpp voltage,
turning it on to VPPH only when desired for system
update. Many 12V converters and power supplies integrate this on/off function as shown in Figure 6, or it
can be provided by an external FET. This approach
will be used again in the next section on write protection during system power transitions. Note, however,
that although it prevents actual flash memory data alteration, VPP control is insufficient to keep block-erase
flash memories from transitioning to alternate data output modes by unintended writes.
2-68
6.0
PREVENTING UNINTENDED
WRITES DURING SYSTEM
RESET AND POWERUPI
POWERDOWN
System powerup and/or powerdown offer the greatest
potential for unintended writes in flash memory-based
system designs. As mentioned earlier, similar potential
also exists for other "nonvolatile/rewriteable" memory
technologies, such as EEPROM and battery-backed
SRAM. Several reasons for this are listed below.
• When a system begins to power up, all logic outputs
are at OV. This is also the "enable" condition for
flash memory CE# and WE# inputs.
• Logic devices have specified, documented and guaranteed operation only at a specific supply voltage
range (typically 5V ± 10% or 3.3V ±0.3V). Operation beyond this voltage range is not guaranteed and
may not be consistent. Specifically, device output
behaviour is typically undefmed.
• Similarly, logic operation is sometimes undefined
and erratic when devices are being reset. For example, MCS-186 embedded processors, when reset, tristate their WR# (write enable) outputs, which will
then typically drift toward OV (or "enabled", to
TIL inputs).
I
AP-374
Flash
Memory
Processor
292123-5
Figure 7. Basic Processor/Flash Memory Interface
• If both the Vee and Vpp power supplies are
switched "on" at the s~e time, one or the other is
likely to ramp to a "valid" level first, depending on
the relative capacitive loading at the supply outputs.
Similarly, one supply will often ramp below its valid
voltage range before the other, on system poweroff.
This situation is acceptable, as long as the WE#
and/or CE# signals to the flash memory are controlled.
Figure 7 shows a very basic example processor/memory interface. When the system power is switched on, the
processor (or logic) WE# output and logic CE# output are both at GND. Depending on the processor and
logic, these outputs may not reliably stabilize until Vee
ramps to 4.5V. In most cases, CPU and logic outputs
will smoothly follow the supply voltage up to operating
levels. Any oscillations on these outputs, however, can
be decoded as a valid write by the flash memory, which
begins to "wake up" below 4.5V Vee. Similarly, ad, dress and data processor outputs are typically undefined below operating voltage ranges. Given a x8 interface between processor and flash memory (therefore,
with 256 possible combinations of data inputs), there is
a finite chance that a valid command byte will be randomly generated and written to the' flash memory.
If the Vpp power supply output is less capacitively
loaded than Vee, Vpp can ramp above VPPL before
Vee reaches 4.5V. This can cause unintended flash
memory program and erase if the correct command
data values ru:e "spuriously" written to the device.
I
Again referencing Figure 7, the behaviour of processor/
logic CE#, WE# and address/data outputs are typically undefined once Vee drops below 4.5V. If the
power supply Vpp output is more capacitive1y loaded
than Vee, Vpp can remain above VPPL as Vee decays
toward OV. This has the potential to initiate program!
erase operations in response to unintended flash memory writes.
6.1
Designing for Flash Memory
System Power Sequencing
Protection
Intel has taken several steps with respect to its flash
memory designs to significantly minimize the possibility of an unwanted write during system powerup or
powerdown. By synergizing system designs to these
flash memory features, you can easily eliminate the potential for unwanted flash memory mode switching
and/or data alteration.
Flash memories from Intel are guaranteed not to program or erase with Vpp below 6.5V. First generation
bulk-erase devices additionally block all write attempts
with Vpp below 6.5V. The implication here is clear; if
possible, don't switch on Vpp until after the system
Vee is stable (on powerup), and switch offVpp before
the system is powered down. The Vpp supply itself can
be switched on/off, or an inline PET switch can be
installed between the power supply output and flash
memory input and controlled via an I/O line from the
processor or discrete logic. Figure 6 gives an example of
circuitry for the former case.
2-69
AP-374
using the Maxim component. Voltage monitoring circuits like those mentioned above have adjustable trip
points and tight tolerances, and can be set to the lower
value of the system logic normal operating voltage.
Supply
Voltage
5V - -~.....>--_
Logic
Outputs
------------
~D-
-
-------------
292123-6
Figure 8. Supply Voltage/Device Output
Relationship During Powerup
Intel flash memory also provides Vee-driven "lockout
protection" from unwanted writes. With Vee below
VLKO, all write attempts to the flash memory are ignored. VLKO varies between 2.SV and 2.0V depending
on the specific flash memory, and its value is targeted
to take advantage of the fact that in most cases device
outputs closely follow Vee inputs (both up and down).
Referencing Figure 8, when Vee exceeds VLKO, device
outputs will in most cases also be at approxiMately
VLKO, and consequently at a TTL "1" level (or disabled). The flash memory "protects itself" up to VLKO,
and the system designer must above that point ensure
that flash memory control inputs are stable. Similarly,
the flash memory is again protected once Vee drops
below VLKO on system powerdown.
The RP# input (formerly known as PWD#), available
on Intel Boot Block and FlashFile memories, acts as a
"master on/off switch" for the device. With RP# at
VIL, the flash memory is put in a very low power mode
called Deep Powerdown, and is essentially turned
"ofT". In this state, all write attempts to the flash memory are disregarded. RP# can be driven by the
POWERGOOD output of the system power supply (if
this output exists) or from an external analog "power
supply monitoring" device like the Maxim MAX70S or
Motorola MC34064, providing absolute flash memory
protection. Figure 9 gives an example system design
2-70
EXTERNAL
RESET#
PWR
SYSTEM
MAX705 GOOD 1 - -.... RESET#
292123-7
Figure 9. Reset Control during
System Powerup and Powerdown
7.0 SUMMARY
Unintended writes to flash memory can, at a minimum,
cause it to output data that the system does not expect,
forcing system reset or power sequencing to restore
normal operation. Depending on the specific data written to the device, and the Vpp voltage at the time of the
write, actual "permanent" alteration of flash memory
contents can result from unintended program or erase.
However, Intel flash memory, in combination with
proper system interfacing techniques, easily eliminates
the potential for either of these scenarios.
Closely analyze the powerup/down and reset behaviour
of the system CPU and any interface logic that interacts with the flash memory. In the vast majority of
cases, no problems will be found. If potential for unwanted writes does exist, however, nonvolatile/rewrite·
able memory protection can easily be included if incorporated early in the design, by following the hints described in this application note.
I
int:el.
AB-29
APPLICATION
BRIEF
Flash Memory Applications in
Laser Printers
BRIAN DIPERT
MCD MARKETING APPLICATIONS
August 1993
I
O
~1'1'1
Display List
J
I
Band Buffer
CD
~
Font Cache
L __________ J
=
3
@)
r----------l
CD
o
IMAGING AND
COMMUNICATION
€:
PROGRAM
AND FONT
FLASH
MEMORY
i960™
KA/KB
PROCESSOR
MEMORY
EXPANSION
INTERFACE
CD
3
CD
a
FONT CAROl
CARTRIDGE
INTERFACE
3'
r;
DI
Q.
3'
co
82961KD
PRINTER
COPROCESSOR
"BOISE"
1'1'1
D
Q.
co
CD
ri..
CD
'U
:1
r
HOST
COMMUNICATION
A
INTERFACE
IDlH
..........rT
PARALLEL
SERIAL
LOCALTALK
SCSI
:I
;~
NETWORK
292110-2
~
I\J
..:..
01
m
I
I\)
CD
AB-29
Today, upgradeability once a system reaches the customer's hands is achieved via proprietary, costly add-in
ROM cards. These emulation modules connect to the
host system through low-performance interface buses.
Updating the local code memory in the printer requires
a technician visit, is very costly to the customer, and is
therefore rarely done. The result can be a less-than-optimized system with subpar performance, and a dissatisfied customer that will not consider your company for
hislher next printer purchase!
Flash memory's in-system reprogramming makes system code upgrade as simple as running an "UPDATE"
utility on the host computer, and can be done by the
customer at hislher PC using a diskette sent by the
printer manufacturer, or a file downloaded from a
OEM computer bulletin board service. Configuring the
printer with the exact emulations needed is equally
straightforward. Customer service is perhaps the supreme differentiator in multiple-source markets. As
companies focus more and more on the customer and
the service aspects of their business, they will turn to
flash memory as a means of readily and economically
achieving their goals.
Intel's Boot Block flash memory product line has been
specifically defined to meet the specific requirements of
high-density embedded code storage and execution.
These devices are also available in ROM-compatible
pinouts. This allows printer OEMs to achieve quick
time-to-market with rev. 0 software (updateable once
initial systems are in customer hands) and later convert
their designs to ROM if desired, once final production
code is stable. For further information on these products, reference the Additional Information section at
the conclusion of this. application brief.
Computer users are more and more outgrowing the capabilities of the resident ROM fonts stored in their laser printers, or available through the ROM expansion
font cartridges. ATM and TrueType are enabling these
users to customize their documents by varying not only
font size and attributes, but also the font typefaces
themselves. Many corporations have 'developed custom
fonts for use by their employees for a consistent documentation "look and feel" .. These unique typefaces are
not a part of the resident standard typeface set. Finally,
not only fonts, but also graphic bitmaps (corporate logos, bitmapped signatures, etc.) and page layout templates are being integrated into desktop-published documents. All of this non-resident information must be
repeatedly downloaded from the host computer to the
printer DRAM after each printer poweroff or reset.
Since this download. is accomplished via the serial or
parallel connection, print performance is dramatically
and negatively impacted, especially noticeable in a networked printer arrangement.
Flash memory, with its unique set of attributes, combines the best qualities of today's font and template
storage solutions while' incorporating none of their
weaknesses. Like DRAM, it is in-system updateable
and has comparable per-device cost at higher densities.
Like ROM, it is nonvolatile. Like both of these technologies, it is a very dense' storage medium, available in
sizes up to 1 Mbyte per component, and 20 Mbytes per
card, at the time this application note was written.
Where extremely high density memory is needed, as in
the case of Kanjii font storage, flash memory components have an over 2oo,OOOx first read access advantage
and an over 14x data transfer performance advantage
over hard disk drives. The performance of a printer
computing subsystem is significantly hindered by the
slow access time of a HDD. Flash memory, with its
sub-loo ns read speed, is the superior solution.
2.2 Font Storage
Today's laser printers ship from the factory with a
number of "resident" fonts stored in nonvolatile ROM.
The density of this memory varies with the end market
for the printer. A "Roman" set of resident' typefaces
requires anyWhere from I Mbyte-2 Mbytes of storage.
Japanese "Kanjii" fonts, on the other hand, require upwards of 5 Mbytes per typeface. A minimum-configured laser printer for the Japanese market therefore
needs 10 Mbytes-20 Mbytes of resident font memory.
Additional permanent font storage is often available
through ROM font cartridges, similar to the "emulation" fonts mentioned earlier. Finally, software such as
Adobe Type Manager" and Microsoft' TrueType*
downloads font information to the printer, storing it in
volatile DRAM. This latter temporary font data is lost
when the printer is turned off or reset. Resets can occur, for example, each time the printer output jams, or
when the paper supply is depleted.
2-76
A resident high-density array of flash memory is coupled directly to the CPU local bus for highest performance. It allows the customer to exactly configure the
printer font, bitmap graphic and page template information for hislher specific applications. This data is
downloaded to the printer once, and from that point on
is always available for use, even after the printer is
turned off or reset. If expanded printer usage (as in a
network environment) requires additional resident
"font" storage in the future, easy density upgrade is
enabled by designing in a PCMCIA memory-I/O card
socket, again interfacing directly to the embedded processor bus. Plugging in a flash memory card means no
'printer disassembly is required!
I
AB-29
Intel's FlashFile™ flash memory component and Series 2 flash memory card lines combine the high density
and high performance required for resident "font" storage. For further information on these products, reference the Additional Information section at the conclusion of this application brief.
2.3 Image Storage and Manipulation
The temporary graphic memory subsystem stores the
image to be printed as it is "constructed" by the processor from data provided by the host computer. Optimum
characteristics of this memory include full "real-time"
bit-level alteration, infinite rewrite capability and fast
read/write performance. Nonvolatility is not required
in this area of the memory subsystem. Therefore,
DRAM will continue to be the memory of choice for
temporary image storage.
3.0
SUMMARY
This application brief has discussed the various memory subsystems in today's laser printers, and their operating characteristics. Flash memory is an exciting new
approach that offers the very real potential to significantly improve your next-generation laser printer designs. Its capabilities are superior to traditional solutions in the system code and font memory areas, and
enable laser printers that are more expandable, more
flexible, higher performance and easier to use than ever
before. The end result is a satisfied customer, a customer that will choose your product over a competitor's,
and a customer that will remain loyal to your company
far into the future.
ADDITIONAL INFORMATION
For additional information on the Intel flash memory products mentioned in this article, please reference the
following documents, available through your local Intel sales representative.
Boot Block Components
28F001 BX Datasheet
28F200BX/28F002BX Datasheet
28F400BX/28F004BX Datasheet
ER-26 "The Intel 28F001BX-T and 28F001BX-B Flash Memories"
ER-29 "The Intel 214 Mbit Boot Block Flash Memory Family"
FlashFile Components
28F008SA Datasheet
AP-359 "28F008SA Hardware Interfacing"
AP-360 "28F008SA Software Drivers"
AP-364 "28F008SA Automation and Algorithms"
ER-27 "The Intel 28F008SA Flash Memory"
FlashFile Series 2 Cards
Series 2 Flash Memory Card Datasheet
AP-361 "Implementing the Integrated Registers of the Series 2 Flash Memory Card"
General Flash Information
AP-357 "Power Supply Solutions for Flash Memory"
ER-20 "ETOX II Flash Memory Technology"
ER-28 "ETOX III Flash Memory Technology"
Order Number
290406
290448
290451
294010
294013
Order Number
290429
292094
292095
292099
294011
Order Number
290434
292096
Order Number
292092
294005
294012
'Microsoft and· TrueType are trademarks of Microsoft Corporation. Adobe Type Manager and PostScript are
trademarks of Adobe Systems Incorporated. PCL is a trademark of Hewlett Packard Corporation. ETOX and
FlashFile are trademarks of Intel Corporation.
I
2-77
intel·
TECHNICAL
PAPER
Small and Low-Cost Power
Supply Solution for Intel's·
Flash Memory Products
BILAL QURESHI
MCD APPLICATIONS ENGINEER
SALIM B. FEDEL
SENIOR APPLICATIONS ENGINEER
November 1994
Order Number: 297534·001
2·78
1.0 INTRODUCTION
2.1
Intel Flash memory devices with two power supply
sources, a 5V Vee and 12V Vpp, offer flexibility. For
example, in a flash array, one simple off-chip circuit
can be used by the entire array to supply the Vpp voltage to any flash chip. Vee is the primary power source,
and the only power source needed to read the memory.
Vpp is required when writing or erasing the memory.
This technical paper describes a state-of-the-art 5V to
12V power conversion solution, which uses no inductors, fits in 0.1" sq. area and yet costs less than $2.00,
in volume quantities.
A detailed description of the solution is presented in the
next section. Section 3.0 deals with the components
used, their type, value, price and vendors to contact.
References are provided in the Additional Information
section.
2.0 DETAILED DESCRIPTION
The power solution uses one MAXIM's MAX662A
with four small, surface-mount capacitors to generate
regulated Vpp with no need for inductors (Figure 1).
MAX662A is available in a small, 8-pin narrow surface
mount package. The entire design fits in 0.1" sq. area,
as shown in the layouts of Figures 2 and 3.
Optimal Attributes
• Very Low Cost
• Small Size: 0.1" sq. (67.9 mm2) Total Board Area
(Single Sided)
• Low Shutdown Current
• Fast Rise Time from Shutdown
• No Inductor Necessary
Main Features
• Input Voltage Range: 4.75V to 5.5V
• Shutdown Feature on Chip
The MAX662A provides a regulated l2V output voltage at 30 mA from a 5V ± 5% power supply. It uses
internal charge pumps and external capacitors to generate l2V, eliminating inductors. Regulation is provided
by pulse-skipping scheme· that monitors the output
voltage level and turns on the charge pumps when the
output voltage begins to droop. The solution boasts a
typical efficiency of 74% with Vee = 5V and lOUT =
30 rnA.
For protection from accidental erasure of flash memory, a shutdown pin is provided. In shutdown mode, the
charge-pump switching action is halted and VIN is connected to VOUT through a lk internal resistor.
2.2 Charge-Pump CapaCitors,
C1 and C2
Since the values of Cl and C2 are critical, 0.22 I-I-F
ceramic capacitors are used. Small surface-mount capacitors C20l2Y5VlE224Z from TDK are used to
achieve smallest board area size.
2.3 Input and Output CapaCitors,
C4and C5
The type of input bypass (C4) and output filter capacitor (C5) affect performance. TDK C32l6Y5VlC225Z
and C20l2Y5VlCl05Z, 2.2 I-I-F and 1 I-I-F low ESR ceramic capacitors are used. The low ESR of these units
eliminates the need for decoupling between VIN and
VOUT·
2.4 layout Considerations
• All-Surface Mount
• Output Voltage: l2V ± 5%
• Output Current Capability up to 30 rnA at VIN
5V
• Typical Efficiency: 74% at Load = 30 mA
• 500 KHz Switching Frequency
Maxim Integrated ProductsMAX662A: Vpp at 30 rnA
=
To ensure stability and decrease noise, careful attention
is paid to keeping the connections short. Since only one
side of the board is used, this l2V solution can be
placed right beneath the flash chip in a two-sided board
designs, thereby saving space and reducing pin to pin
track length.
To keep the inductance in· the circuit to a minimum,
thick track lines are employed (0.025" wide). Some
critical dimensions are given below:
Total Length: 0.345" (8.763 mm)
Total Width: 0.305" (7.747 mm)
Track Width: 0.025" (0.635 mm)
Track-Track Spacing: 0.01" (0.254 mm)
2-79
INPUT
4.7SVtoS.SV
C4
+2.2IlF
I
OUTPUT
12V±S%
30mA
Vee
VOUT
SHDN
Vpp
+1 IlF
C1+
0.221lF
MAXIM
MAX662A
C1-
C2-
Ics
FLASH
MEMORY
C2+
GND
297534-1
Figure 1. Maxim MAX662A 5V to 12V Converter Circuit
DEI
297534-2
Figure 2. 5x Scale Top Side Component
Placement View
2-80
297534-3
Figure 3. 5x Scale Top Side Trace View
3.0 PARTS LIST
Table 1. Parts List for the MAX662A 5V to 12V Converter
Part Number
Reference
U1
MAX662ACSA
C1,C2
C2012Y5V1E224Z
Value/Type
Source
Cost(1)
SMPSIC
Maxim
(408) 737-7600
$1.69
TDK
$0.06
0.22 ,...F Ceramic
(408) 437·9585
C4
C3216Y5V1C225Z
2.2 ,...F Ceramic
TDK
$0.09
(408) 437·9585
C5
C2012Y5V1C105Z
1.0 ,...F Ceramic
TDK
$0.07
(408) 437·9585
Total Cost
$1.97
NOTE:
1. Cost estimates based on published 10K unit·pricing at the time this technical paper was written.
4.0 SUMMARY
This technical paper summarizes low·cost 5V to 12V
power solution, which uses no inductors and fits in 0.1 n
sq. area. The solution is based on recommendations
provided by the supplier vendors, and has been verified
at the Intel Corporation laboratory.
5.0 ADDITIONAL INFORMATION
5.1 References
Order Number
Document
292092
AP·357, "Power Supply Solutions for Flash Memory"
292153
AS·59, "Multi-Site Layout Planning with Intel's Flash File™ Components Including ROM
Compatability"
. 2-81
3
Synchronous and
DRAM-Interface Flash
Memory Components
and FlashFile
Components
I
Intel 28FO 16XS Embedded Flash RAM
Product Brief
Product •
Highlights
Ideal for embedded applications:
Datacom
omce automation
Telecom
Computing
Games
• Supports burst-mode processolli:
i960I aod InleJ486T'l
CPU-based systems
• Superior power, integration and
price to DRAM + ROM or code
DRAM + IIDD:
Ideal for battery-powered
portable applications lit
high-speed embedded designs
• Synchronous nasb RAM
• Supports 33-MHz zero-walt state
Product~ription
• Very blgh read performance:
2XDRAM
The Intel 28Rll6XS embedded flash RAM is a 16Mb synchronous memory
component that blends very high read perfonnance with the nonvolatility,
updatability and low power of flash memory. It provides higher integration, 3.3V
capability and up to twice the perfonnance of DRAM, without price premiums or
additional board space requirements. As a result, the 28FOl6XS embedded flash
RAM is ideal forburit-mode proceSSOri, such as the i96O"' and Intel486™
microprocessors, as well as for embedded applications where redundant code
DRAM + ROM or code DRAM + IIDD were used for code execution/storage
memory.
• SmartYoItage feature supports
botb SV aod 12V device writes
and SV or 3.3V device reads
• Nonvolatile and updatable
• In-system updatabillty for faster
lime to market
• Requires less board space tban
redundant muiti-chlp oode .
solutions
• Fim Dash memory-based device
wltb synchronous pipelined read
interface
Because the Intel 28Rll6XS embedded flash RAM is a nonvolatile, code storage
and execution solution, there is no need for refresh, redundant memory or HDD
"spin-up" latency when returning from deep power-down mode. It also enables
instant-on system design. Using minimal glue logic, the Intel 28F0l6XS embedded flash RAM can easily interface directly to bum-mode processori, supporting
33-MHzzero-wait state, 5V read perfonnance code storage. The embedded flash
RAM device is internally partitioned into 16 software-lockable, 128KB blocks.
The Intel 28Rll6XS embedded flash RAM is particularly well suited for such data
communication needs as routers. hubs and ATM switches; for office automation
components, inclUding printeri, scanneri and copieri; for telecommunications
central office switches, local exchange switches, premise switches and cell base
stations; for such computing purposes ~ POS tenninals, diskless workstations and
mobile communications; and for games applications for arcade, set-top and highend home use.
intel·
I
3-1
I
Intel 28F016XD Embedded Flash RAM
Product Brief.
Product •
DlnhH....ts
.~
""""'ft
emlJedded IIIIIb
RAM dnIce'
DRAM.syslalbderfIce
NOIIwIIIIIe, apdatable ....
Jowpower
• Better price ad perf_
tIIID DRAM +ROM ....
DRAM+HDD:
0Ifen Id&her iDtep'ItIoa II1II
3.3V C8pI/JIIIty
Requires lower power ad lea
llamdspu
• Ida! for emIJedded appIIcadolls:
0.0IIIce ulomllloa
TeIeaJm
Compadng
GIDIes
• Simple DRAM.IaIerf_:
Allows lISe III sIaDdard
DRAM COIIIruIIen
0pdmIzes 1liiie to market
SIts dIftcII)' 0118 cadIabIe
bus
• IdaI for portable
8JIIIII!:adoIIs
• Easy bderfIce to systems ....
embedded ~:
For 19611'KX,1t6GCS, I960JX
.... ~CPU·bad
systems
• IDIeruIIy putltIoaed lalo 32
ilClftftre.JocbbIe, 32KB IIIocks
• SmutVohIge feaIare:
Supports both 5V ud 12V
device writes .... 5V or 3.3V
demerads
• FIrst IIIIh memory dnIce willi
DRAM.laterl'ace
Product Description
The Intel 28FOI.6XD embedded flash RAM is an innovative 16Mb memory
component thai combioes a DRAM-like system interface with the nonvolatility,
updatability and lower power of flash memory. The 28FOI6XD embedded flash
RAM is an ideal solution for embedded applications where redundant code DRAM
+ ROM or code DRAM + HDD were used for code executionfstorage memory.
Its simple DRAM-like interface allows use of standard DRAM controllers,
optimizing time to nwket. In addition, the Intel 28FOI6XD embedded flash RAM
is in~syslem updalable, reducing the risk of early manufacturing as compared to
DRAM + ROM and DRAM + OTP EPROM options. The Intel 28FOI6XD
embedded flash RAM can easily interface to systems using such embedded
processors as the i96O"KX, i960X, i960JX and the Intei386TMEX CPU-based
systems. Several vendors offer 28R1I6XD embedded flash RAM SIMM modules,
making it easier to upgrade code DRAM designs to embedded flash RAM.
The Intel 28FOI6XD embedded flash RAM is internally partitioned into 32
software-lockable, 32-KB blocks. Like Intel's 28FOI6SV SmartVoItage device,
the 28FOI6XD embedded flash RAM supports both 5V and 12V device writes as
well as 5V or 3.3V device reads. Because the Intel 28FOI6XS embedded flash
RAM: is a nonvolatile, code storage and execution solution, there is no need for
refresh, redundant memory or HDD ·spin-up" latency when returning from deep
power-doWD mode. It also enables instant-on system design.
DIe Intel 28F016XD embedded flash RAM, which is the fllSt flash memory device
with a DRAM-like interface, is particularly well suiled for data communications,
office automation, telecommunications, computing and games.
'0Ihcr _11111 ......... 1hc InIdcmarts oflhcirmpecti•• ownm.
Printed in USAJI094I17.SKlASIITCIMCD
OI994In..IC..........
0nIer Number. 297547.(101
3-2
I
28F016XS
16-MBIT (1-MBIT x 16, 2-MBIT x 8)
SYNCHRONOUS FLASH MEMORY
O-Wait-State Performance up
• toEffective
33
Technology
• -SmartVoltage
User-Selectable 3.3V or 5V Vcc
- User-Selectable 5V or 12V Vpp
MB/sec Burst Write Transfer Rate
• 30.8
0.48 MB/sec Sustainable Write Transfer
• Rate
x8 or x16 Operation
• Configurable
Separately-Erasable/Lockable
• 16128-KByte
Blocks
• 56-Lead TSOP Type I Package
MHz
Backward Compatible with
• 28F016SA/SV,
28F008SA Command-Set
Revolutionary Architecture
• - Synchronous Pipelined Reads
- Multiple Command Execution
- Write During Erase
- Page Buffer Write
/-LA Typical Deep Power-Down
• 21 mA
Active Icc Current in
• Static Typical
Mode
II 1 Million Erase Cycles per Block
III State-of-the-Art 0.6 /-Lm ETOXTM IV
Flash Technology
Intel's 28F016XS 16-Mbit Flash memory is a revolutionary architecture which is the ideal choice for designing
truly revolutionary high-performance products. Combining very high read performance with the intrinsic nonvolatility of flash memory, the 28F016XS eliminates the traditional redundant memory paradigm of shadowing
code from a slow nonvolatile storage source to a faster execution. memory, such as DRAM, for improved
system performance. The innovative capabilities of the 28F016XS enable the design of direct-execute code
and mass storage data/file flash memory systems.
The 28F016XS is the highest performance high density nonvolatile read/write flash memory solution available
today. Its synchronous pipelined read interface, flexible Vee and Vpp voltages, extended cycling, fast write and
read performance, symmetrically blocked architecture, and selective block locking provide a highly flexible
memory component suitable for resident flash component arrays on the system board or SIMMs. The synchronous pipelined interface and x8/x16 architecture of the 28F016XS allow easy interface with minimal glue logic
to a wide range of processors/buses, providing effective O-wait-state read performance up to 33 MHz. The
28F016XS's dual read voltage allows the same component to operate at either 3.3V or S.OV Vee. Programming voltage at SV Vpp minimizes external circuitry in minimal-chip, space critical designs, while the 12V Vpp
option maximizes writel erase performance. Its high read performance combined with flexible block locking
enable both storage and execution of operating systems/application software and fast access to large data
tables. The 28F016XS is manufactured on Intel's 0.6 ,...rri ETOXTM IV process technology.
290532-21
November 1994
Order Number: 290532-001
3-3
,
28F016XS
16-MBIT (1-MBIT x 16, 2-MBIT X 8)
SYNCHRONOUS FLASH MEMORY
CONTENTS
PAGE
1.0 INTRODUCTION ..................... 3-5
1.1 Product Overview .................. 3-5
2.0 DEVICE PINOUT ........... : ......... 3-8
2.1 Lead Descriptions ................. 3-9
3.0 MEMORY MAPS .................... 3-11
3.1 Extended Status Register Memory
Map ............................... 3-12
4.0 BUS OPERATIONS, COMMANDS .
AND STATUS REGISTER
DEFINITIONS ........................ 3-13
4.1 Bus Operations for Word-Wide
Mode (BYTE # = VI H) ............. 3-13
4.2 Bus Operations for Byte-Wide
Mode (BYTE# = VII] .............. 3-14
4.3 2BFOOBSA-Compatible Mode
Command Bus Definitions .......... 3-15
4.4 2BF016XS-Perfor~ance
Enhancement Command Bus
Definitions ......................... 3-16
4.5 Compatible Status Register ....... 3-18
4.6 Global Status Register ............ 3-19
4.7 Block Status Register ............. 3-20
4.B Device Configuration Code .... ; ... 3-21
4.9 SFI Configuration Table ........... 3-21
CONTENTS
PAGE
5.0 ELECTRICAL SPECiFiCATIONS .... 3-22
5.1 Absolute Maximum Ratings ....... 3-22
5.2 Capacitance ....................... 3-23
5.3 Transient Input/Output Reference
Waveforms ... , .................... 3-24
5.4 DC Characteristics (Vee = 3.3V
± O.3V) ............................ 3"25
5.5 DC Characteristics (Vee = 5.0V
± O.5V) ............................ 3-27
5.6 Timing Nomenclature ....... " ..... 3-29
5.7 AC Characteristics-Read Only
Operations ......................... 3-30
5.B AC Characteristics for WE#Controlled Write Operations ........ 3-36
5.9 AC Characteristics for CEx#Controlled Write Operations ........ 3-39
5.10 AC Characteristics for WE #Controlled Page Buffer Write
Operations ........................ ~ 3-42
5.11 AC Characteristics for CEx #Controlled Page Buffer Write
Operations ......................... 3-43
5.12 Power-Up and Reset Timings .... 3-44
5.13 Erase and Word/Byte Write
Performance ....................... 3-45
6.0 MECHANICAL SPECIFICATIONS . .. 3-47
DEVICE NOMENCLATURE AND
ORDERING INFORMATION . ......... 3-48
ADDITIONAL INFORMATION .......... 3-49
DATASHEET REVISION HiSTORy ..... 3-49
3-4
28F016XS FLASH MEMORY
1.0 INTRODUCTION
The documentation of the Intel 2BF016XS Flash
memory device includes this datasheet, a detailed
user's manual, a number of application notes and
design tools, all of which are referenced at the end
of this datasheet.
The datasheet is intended to give an overview of the
chip feature-set and of the operating AC/DC specifications. The 16-Mbit Flash Product Family User's
Manual provides complete descriptions of the user
modes, system interface examples and detailed descriptions of all principles of operation. It also contains the full list of software algorithm flowcharts,
and a brief section on compatibility with the Intel
2BFOOBSA.
1.1 Product Overview
The 2BF016XS is a high-performance, 16-Mbit
(16,777,216-bit) block erasable nonvolatile random
access memory organized as either 1-MWord x 16
or 2-MByte x B, subdivided into even and odd banks.
Address A1 makes the bank selection. The
2BF016XS includes sixteen 12B-KByte (131,072
byte) blocks or sixteen 64-KWord (65,536 word)
blocks. Chip memory maps for x8 and x16 modes
are shown in Figures 3 and 4.
The implementation of a new architecture, with
many enhanced features, will improve the device operating characteristics and result in greater product
reliability and ease-of-use as compared to other
flash memories. Significant features of the
2BF016XS as compared to previous asynchronous
flash memories include:
• Synchronous Pipelined Read Interface
• Significantly Improved Read and Write Performance
• SmartVoltage Technology
- User-Selectable 5.0V or 12.0 Vpp
• Internal 3.3V/5.0V Vee Detection Circuitry
• Block Write/Erase Protection
The 2BF016XS's synchronous pipelined interface
dramatically raises read performance far beyond
previously attainable levels. Addresses are synchronously latched and data is read from a 2BF016XS
bank every 30 ns. This capability translates to 0wait-state reads at clock rates up to 33 MHz at 5V
Vee, after an initial address pipeline fill delay and
assuming even and odd banks within the flash mem-
ory are alternately accessed. Data 'is latched and
driven valid 20 ns (teHQV) after a rising ClK edge.
The 2BF016XS is capable of operating up to 66 MHz
(5V Vee>, and the programmable SFI Configuration
enables system design flexibility optimizing the
2BF016XS to a specific system clock frequency. See
Section 4.9, SFI Configuration Table, for specific SFI
Configurations for given operating frequencies.
The SFI Configuration optimizes the 2BF016XS for a
wide range of system operating frequencies. The default SFI Configuration is 4, which allows system
boot from the 2BF016XS at any frequency up to 66
MHz at 5V Vee. After initiating an access, data is
latched and will begin driving on the data outputs
after a ClK count corresponding to the SFI Configuration has elapsed. The 2BF016XS will hold data valid until CE # or OE # is deactivated or a ClK count
corresponding to the SFI Configuration for a subsequent access has elapsed.
The ClK and ADV # inputs, new to the 2BF016XS in
comparison to previous flash memories, control address latching and device synchronization during
read operations. ClK input controls the device latencies, times out the SFI Configuration and synchronizes data outputs. ADV # indicates the presence of
a valid address on the 2BF016XS address inputs.
During read operations, addresses are latched and
accesses are initiated on a rising ClK edge in conjunction with ADV # low. Both ClK and ADV # are
ignored by the 2BF016XS during write operations.
The 2BF016XS incorporates SmartVoltage technology, providing Vee operation at both 3.3V and 5.0V
and program and erase capability at Vpp = 12.0V or
5.0V. Operating at Vee = 3.3V, the 2BF016XS consumes less than one half the power consumption at
5.0V Vee, while 5.0V Vee provides highest read performance capability. Vpp operation at 5.0V eliminates the need for a separate 12.0V converter, while
the Vpp = 12.0V option maximizes write/erase performance. In addition to the flexible program and
erase voltages, the dedicated Vpp gives complete
code protection with Vpp :s: VPPLK.
Internal 3.3V or 5.0V Vee detection automatically
configures the device internally for optimized 3.3V or
5.0V Read/Write operation. Hence, the 2BF016SA's
3/5# pin is not required and is a no-connect (NC)
on the 2BF016XS maintaining backwards-compatibility between components.
A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation.
3-5
28F016XS FLASH MEMORY
Internal Algorithm Automation allows BytelWord
Writes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the 2SFOOSSA S-Mbit FlashFile™
memory.
A super-set of commands has been added to the
basic 2SFOOSSA command-set to achieve higher
write performance and provide additional capabilities. These new commands and features include:
•
•
•
•
•
•
Page Buffer Writes to Flash
Command Queuing Capability
Automatic Data Writes during Erase
Software Locking of Memory Blocks
Two-Byte Successive Writes in S-bit Systems
Erase All Unlocked Blocks
Writing of memory data is performed in either byte or
word increments, typically within 6 /Lsec at 12.0V
Vpp, which is a 33% improvement over the
2SFOOSSA. A Block Erase operation erases one of
the 16 blocks in typically 1.2 sec, independent of the
other blocks.
Each block can be written and erased a minimum of
100,000 cycles. Systems can achieve one million
Block Erase Cycles by providing wear-leveling algorithms and graceful block retirement.. These techniques have already been employed in many flash
file systems and hard disk drive designs.
The 2SF016XS incorporates two Page Buffers of
256 bytes (12S words) each to allow page data
writes. This feature can improve a system write performance by up to 4.S times over previous flash
memory devices, which have no Page ijuffers.
All operations are started by a sequence of Write
commands to the device. Three Status Registers
(described in detail later in this datasheet) and a
RY IBY # output pin provide information on the progress of the requested operation.
While the 2SFOOSSA requires an operation to complete before the next operation can be requested,
the 2SF016XS allows queuing of the next operation
while the memory executes the current operation.
This eliminates system overhead when writing several bytes in a row to the array or erasing several
blocks at the same time. The 2SF016XS can also
perform Write operations to one block of memory
while performing Erase of another block.
3-6
The 2SF016XS provides selectable block locking to
protect code or data such as direct-e~ecutable oper- .
ating systems or application code. Each block has
an associated nonvolatile lock-bit which .determines
the lock status of the block. In addition, the
2SF016XS has a master Write Protect pin (WP#)
which prevents any modifications to memory blocks
whose lock-bits are set.
The 2SF016XS contains three types of Status Registers to accomplish various functions:
• A Compatible Status Register (CSR) which is
100% compatible with the 2SFOOSSA FlashFile
memory Status Register. The CSR, when used
alone, provides a straightforward upgrade capability to. the 2SF016XS from a 2SFOOSSA-based
design.
• A Global Status Register (GSR) which informs
the system of command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
• 16 Block Status Registers (BSRs) which provide
block-specific status information such as the
block lock-bit status.
The GSR and BSR memory maps for Byte-Wide and
Word-Wide modes are shown in Figures 5 and 6.
The 2SF016XS incorporates an open drain RY/BY#
output pin. This feature allows the user to OR-tie
many RY IBY # pins together in a multiple memory
configuration such as a Resident Flash Array. The
RY IBY # output pin employs five distinct configurations, which are enabled via special CUI commands
and are described in detail in the 16-Mbit Flash
Product Family User's Manual.
The 2SF016XS also incorporates a dual chip-enable
function with two input pins, CEo# and CE1 #.
These pins have exactly the same functionality as
the regular chip-enable pin, CE #, on the 2SFOOSSA.
For minimum chip designs, CE1 # may be tied to
ground and system logic may use CEo# as the chip
enable input. The 2SF016XS uses the logical combination of these two signals to enable or disable the
entire chip. Both CEo# and CE1 # must be active
low to enable the device. If either one becomes inactive, the chip will be disabled. This feature, along
with the open drain RY IBY # pin, allows the system
deSigner to reduce the number of control pins used
in a large array of 16-Mbit devices.
28F016XS FLASH MEMORY
The BYTE# pin allows either x8 or x16 read/writes
to the 28F016XS. BYTE # at logic low selects 8-bit
mode with address Ao selecting between low byte
and high byte. On the other hand, BYTE# at logic
high enables 16-bit operation with address A1 becoming the lowest order address and address Ao is
not used (don't care). A device block diagram is
shown in Figure 1.
Vee
BYTE#
e~====t======~,-----~
ADV#
+---- OE#
14-.....
14----+------
WEI
14-----wP#
14-------- RP#
Input
Buffer
Y Gating/Sensing
X
Decoder
.
Even Bank
~
CIl
~
0
~
CIl
~
~
g
g
iii
iii
f-------.RYIBY#
CIl
'!!.
~
~CIl
CIl
Odd Bank
~
:t--
-4-GND
Y Gating/Sensing
290532-1
Figure 1. 28F016XS Block Diagram
Architectural Evolution Includes Synchronous Pipelined Read Interface, SmartVoltage Technology,
Page Buffers, Queue Registers and Extended Status Registers
3-7
28F016XS FLASH MEMORY
The 28F016XS incorporates an Automatic Power
Saving (APS) feature, which substantially reduces
the active current when the device is in static mode
of operation (addresses not switching). In APS
mode, the typical Icc current is 1 rnA at 5.0V (3 rnA
at 3.3V).
A deep power-down mode of operation is invoked
when the RP# (called PWD# on the 28F008SA) pin
transitions low. This mode brings the device power
consumption to less than 2.0 p,A, typically, and provides additional write protection by acting as a device reset pin during power transitions. A reset time
of 300 ns is required from RP# switching high before latching an address into the 28F016XS. In the
Deep Power-Down state, the WSM is reset (any current operation will abort) and the CSR, GSR and
BSR registers are cleared.
A CMOS standby mode of operation is' enabled
when either CEo# or CE1 # transitions high and
RP# stays high with all input control pins at CMOS
levels. In this mode, the device typically draws an
Icc standby current of 70 p,A at 5V Vee.
The 28F016XS will be available in a 56-Lead, 1.2mm
thick, 14mm x 20mm TSOP Type I package. The
package's form factor and pinout allows for very
high board layout densities.
2.0 DEVICE PINOUT
The 28F016XS is pinout compatible with the
28F016SAlSV 16-Mbit FlashFile™ memory component, providing an performance upgrade path to the
28F016XS. The 28F016XS 56-Lead TSOP pinout
configuration is shown in Figure 2.
2BFOt6S
2BF016SA 28F016S
~
NC
A20
A,.
A,.
Au
A,.
Vee
A,s
A,.
A'3
A'2
CEo#
Vpp
RP#
A"
A,o
A.
A.
GND
A7
A.
As
A.
A3
A,
A,
NC
CE,'
NC
A20
A,.
A,.
Au
A,.
Vee
A,s
A,.
A'3
A'2
CEo#
Vpp
RP#
A"
AlO
A.
A.
'GND
A7
A.
As
A.
A3
A2
A,
NC
CE,#
NC
A20
A,.
A,.
Au
A,.
Vee
A,.
A,.
A'3
A'2
CEo#
Vpp
RP#
A"
AlO
A.
A.
GND
A7
A.
A.
A.
A3
A2
A,
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
0
E28F016XS
56-lEAD TSOP PINOUT
14mmx20mm
TOP VIEW
WP#
WEN
OE#
RYIBY#
DO,.
D0 7
DO,.
DO.
GND
00'3
DO.
DO'2
DO.
Vee
GND
DO"
00 3
00'0
00 2
Vee
DO.
DO,
DO.
~o
BYTE#
ADV#
ClK
2BF016SA
WP#
WEN
OE#
RYIBYI/
DO,.
D0 7
DO,.
DO.
GND
DO'3 DO'3
DO.
DO.
DO'2 DO'2
DO.
DO.
Vee
Vee
GND
GND
DO"
DO"
00 3
00 3
00,0 DOlO
00 2
002
Vee
Vee
DO.
DO.
DO,
DO,
DO.
DO.
DOD
DOD
AD
AD
BYTE# BYTE#
C
C
C
C
WP#
WEN
OE#
RYIBY
00'5
D0 7
DO,.
~~&
290532-2
Figure 2. 28F016XS 56-Lead TSOP Pinout Configuration Shows Compatibility with the 28F016SA/SV,
Allowing for Easy Performance Upgrades from Existing 16-Mbit Designs
3-8
28F016XS FLASH MEMORY
2.1 Lead Descriptions
Symbol
Type
Name and Function
Ao
Input
BYTE-SELECT ADDRESS: Selects between high and low byte when device is in
x8 mode. This address is latched in x8 Data Writes and ignored in x16 mode (Le.,
the Ao input buffer is turned off when BYTE # is high).
A1
Input
BANK-SELECT ADDRESS: Selects an even or odd bank in a selected block. A
128-KByte block is subdivided into an even and odd bank. A1 = 0 selects the even
bank and A1 = 1 selects the odd bank, in both byte-wide mode and word-wide
mode device configurations.
A2-A16
Input
WORD-SELECT ADDRESSES: Select a word within one 128-KByte block.
Address A1 and A7-16 select 1 of 2048 rows, and A2-6 selects 16 of 512 columns.
These addresses are latched during both data reads and writes.
A17-A20
Input
BLOCK-SELECT ADDRESSES: Select 1 of 16 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
DOO-D07
Input
Output
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate read mode.
Floated when the chip is de-selected or the outputs are disabled.
D08-D015
Input
Output
HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations. Outputs
array, buffer or identifier data in the appropriate read mode; not used for Status
Register reads. Outputs floated when the chip is de-selected, the outputs are
disabled (OE# = VIH) or BYTE # is driven active.
CEo#,CE1#
Input
CHIP ENABLE INPUTS: Activate the device's control logic, input buffers,
decoders and sense amplifiers. With either CEo#or CE1 # high, the device is
de-selected and power consumption reduces to standby levels upon completion of
any current Data-Write or Erase operations. Both CEo# and CE1 # must be low to
select the device.
All timing specifications are the same for both signals. Device Selection occurs
with the latter falling edge of CEo# or CE1 #. The first rising edge of CEo# or
CE1 # disables the device.
RP#
Input
RESET/POWER-DOWN: RP# low places the device in a Deep Power-Down
state. All circuits that consume static power, even those circuits enabled in standby
mode, are turned off. When returning from Deep Power-Down, a recovery time of
tpHCH is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are terminated,
and the device is reset. All Status Registers return to ready, clearing all status
flags. Exit from Deep Power-Down places the device in read array mode.
OE#
Input
OUTPUT ENABLE: Drives device data through the output buffers when low. The
outputs float to tri-state off when OE # is high. CEx # overrides OE # , and OE #
overrides WE # .
WE#
Input
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Oueue Registers
and Address Oueue Latches. WE# is active low, and latches both address and
data (command or array) on its rising edge. Page Buffer addresses are latched on
the falling edge of WE # .
3-9
28F016XS FLASH MEMORY
2.1 Lead Descriptions
(Continued)
Symbol
Type
CLK
Input
CLOCK: Provides the fundamental timing and internal operating frequency. CLK
latches input addresses in conjunction with ADV #, times out the desired output SFI
Configuration as a function of the CLK period, and synchronizes device outputs. CLK
can be slowed or stopped with no loss of data or synchronization. CLK is ignored
during write operations.
ADV#
Input
ADDRESS VALID: Indicates that a valid address is present on the address inputs.
ADV # low at the rising edge of CLK latches the address on the address inputs into the
flash memory and initiates a read access to the even or odd bank depending on the
state of address A1. ADV # is ignored during write operations.
Open
Drain
Output
READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. RY /BY # high indicates that the WSM is ready
for new operations (or WSM has completed all pending operations), or Erase is
Suspended, or the device is in deep power-down mode. This output is always active
(Le., not floated to tri-state off when OE # or CEo#, CE1 # are high), except if a
RY /BY # Pin Disable command is issued.
WP#
Input
WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile lock-bit for
each block. When WP# is low, those locked blocks as reflected by the Block-Lock
Status bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP#
is high, all blocks can be written or erased regardless of the state of the lock-bits. The
WP# input buffer is disabled when RP# transitions low (deep power-down mode).
BYTE #
Input
BYTE ENABLE: BYTE # low places device in x8 mode. All data is then input or output
on DOO-7, and D08-15 float. Address Aoselects between the high and low byte.
BYTE # high places the device in x16 mode, and turns off the Ao input buffer. Address
A1 then becomes the lowest order address.
Supply
WRITE/ERASE POWER SUPPLY (12.0V ± O.6V, 5.0V± O.5V): For erasing memory
array blocks or writing words/bytes/pages into the flash array. Vpp = 5.0V ± O.5V
eliminates the need for a 12V converter, while the 12.0V ± O.6V option maximizes
Write/Erase Performance.
RY/BY#
Vpp
Name and Function
Write and Erase attempts are inhibited with Vpp at or below 1.5V. Write and Erase
attempts with Vpp between 1.5V and 4.5V, between 5.5V and 11.4V, and above 12.6V
produce spurious results and should not be attempted.
Vee
Supply
DEVICE POWER SUPPLY (3.3V ±O.3V, 5.0V ±O.5V): Internal detection configures
the device for 3.3V or 5.0V operation. To switch 3.3V to 5.0V (or vice versa), first ramp
Vee down to GND, and then power to the new Vee voltage. Do not leave any power
pins floating.
GND
Supply
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.
NC
3-10
NO CONNECT: No internal connection to die, lead may be driven or left floating.
28F016XS FLASH MEMORY
3.0 MEMORY MAPS
x8 Mode
x16 Mode
A 20-0
A 20-1
lFFFFF
12B-KByte Block
15
FFFFF
64-KWord Block
15
64-KWord Block
14
64-KWord Block
13
64-KWord Block
12
64-KWord Block
11
64-KWord Block
10
64-KWord Block
9
64-KWord Block
8
64-KWord Block
7
64-KWord Block
6
64-KWord Block
5
64-KWord Block
4
64-KWord Block
3
64-KWord Block
2
64-KWord Block
1
64-KWord Block
0
FOooO
EFFFF
1EOooO
1DFFFF
12B-KByte Block
14
12B-KByte Block
13
12B-KByte Block
12
12B-KByte Block
11
12B-KByte Block
10
12B-KByte Block
9
12B-KByte Block
8
12B-KByte Block
7
12B-KByte Block
6
128-KByte Block
5
128-KByte Block
4
12B-KByte Block
3
128-KByte Block
2
12B-KByte Block
1
128-KByte Block
0
EOOOO
OFFFF
lCoooo
lBFFFF
1AOOOO
19FFFF
00000
CFFFF
180000
17FFFF
COOOO
BFFFF
160000
15FFFF
BOOOO
AFFFF
AOOOO
9FFFF
140000
13FFFF
90000
8FFFF
120000
llFFFF
100000
OFFFFF
80000
7FFFF
OEOOOO
OOFFFF
70000
6FFFF
OCOOOO
,OBFFFF
60000
5FFFF
OAooOO
09FFFF
50000
4FFFF
060000
07FFFF
40000
3FFFF
060000
05FFFF
30000
2FFFF
040000
03FFFF
20000
lFFFF
10000
OFFFF
020000
01FFFF
00000
000000
290532-3
Figure 3. 28F016XS Memory Map
(Byte-Wide Mode)
290532-4
Figure 4. 28F016XS Memory Map
(Word-Wide Mode)
3-11
28F016XS FLASH MEMORY
3.1 Extended Status Register Memory Map
x8Mode
A 20,()
x16 Mode
A 20-1
FFFFFH
,1FFFFFH
RESERVED
RESERVED
RESERVED
GSR
RESERVED
BSR 15
RESERVED
RESERVED
1E0006H
1E0005H
- -- - --- - - GSR
1E0004H
1E0003H
1E0002H
1E0001H
1EOOOOH
F0003H
RESERVED
-
- - F0002H
RESERVED
- - - - '- - - - - - - BSR 15
F0001H
RESERVED
- -- - --- - - - - RESERVED
•
•
•
•
•
•
OFFFFH
01FFFFH
RESERVED
RESERVED
000006H
RESERVED
GSR
RESERVED
BSRO
RESERVED
RESERVED
FOOOOH
000005H
00OO3H
...
-
RESERVED
-.. - - - -
000004H
000003H
-
-- -00002H
RESERVED
------- - - - -BSRO
000002H
000001H
OOOOOOH
- -
GSR
- -
-
-
RESERVED
-- --- RESERVED
00001H
--OOOOOH
290532-5
290532-6
Figure 5. Extended Status Register Memory
Map '(Byte-Wide Mode)'
Figure 6. Extended Status Register Memory
Map (Word-Wide Mode)
3-12
28F016XS FLASH MEMORY
4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
4.1 Bus Operations for Word-Wide Mode (BYTE #
Mode
latch Read
Address
Inhibit
Latching
Read Address
= VIH)
Notes
RP#
CEO-l#
OE#
WE#
AOV#
ClK
Al
OQO-15
RY/BY#
1,9,10
VIH
VIL
X
VIH
VIL
t
X
X
X
1,9
VIH
VIL
X
VIH
VIH
t
X
X
X
Read
1,2,7,9
VIH
VIL
VIL
VIH
X
t
X
DOUT
X
Output
Disable
1,6,7,9
VIH
VIL
VIH
VIH
X
X
X
HighZ
X
Standby
1,6,7,9
VIH
VIL
X
X
X
X
X
HighZ
X
Deep
Power-Down
1,3
VIL
.X
X
X
X
X
X
HighZ
VOH
Manufacturer
ID
1,4,9
VIH
VIL
VIL
VIH
X
t
VIL
0089H
VOH
Device ID
1,4,8,9
VIH
VIL
VIL
VIH
X
t
VIH
66A8H
VOH
Write.
1,5,6,9
VIH
VIL
VIH
VIL
X
X
X
DIN
X
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH, or High Z or DOUT for
data pins depending on whether or not OE# is active.
2. RY IBY # output is open drain. When the WSM is ready, Erase is suspended or the device is in deep !lOwer-down mode.
RY/BY# will be at VOH if it is tied to Vee through a resistor. RY/BY# at VOH is independent of OE# while a WSM
operation is in progress.
3. RP# at GND ±0.2V ensures the lowest deep power-down current.
4. Ao and Al at VIL provide device manufacturer codes in xS and x16 modes respectively. Ao and Al at VIH provide device
ID codes in xS and x16 modes respectively. All other addresses are set to zero.
5. Commands for Erase, Data Write, or Lock-Block operations can only be completed successfully when Vpp = VpPHl or
Vpp = VPPH2.
6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes
to VOH when the WSM is not busy or in erase suspend mode.
7. RY/BY# may be at VOL while the WSM is busy performing various operations. For example, a Status Register read
during a Write operation.
S. The 2SF016XS shares an identical device identifier with other Intel Flash memories. Reading this identifier in conjunction
with the unique Device Proliferation Code (read from the Page Buffer after writing the Upload Device Configuration com~
mand), the 2SF016XS can be identified by system software.
9. CEO-l # at VIL is defined as both CEo# and CEl # low, and CEO-l # at VIH is defined as either CEo# or CEl # high.
10. Addresses are latched on the rising edge of CLK in conjunction with ADV# low. Address Al = 0 selects the even bank
and Al = 1 selects the odd bank, in both byte-wide mode and word-wide mode device configurations.
3-13
28F016XS FLASH MEMORY
4.2 Bus Operations for Byte-Wide Mode (BYTE # =
Mode
Latch Read
Address
Inhibit
Latching
Read Address
V,Ll
Notes
RP#
CEO-1#
OE#
WE#
AOV#
ClK
Ao
OQO-7
RY/BY#
1,9,10
VIH
VIL
X
VIH
VIL
t
X
X
X
1,9
VIH
VIL
X
VIH
VIH
t
X
X
X
VIH
VIL
VIL
VIH
X
t
X
DOUT
X
X
X
X
HighZ
X
Read
1,2,7,9
Output
Disable
1,6,7,9
VIH
VIL
VIH
VIH
Standby
1,6,7,9
VIH
VIH
X
X
X
X
X
HighZ
X
Deep
Power-Down
1,3
VIL
X
X
X
X
X
X
HighZ
VOH
Manufacturer
1.4,9
VIH
VIL
VIL
VIH
X
t
VIL
89H
VOH
Device 10
1.4,8,9
VIH
VIL
VIL
VIH
X
t
VIH
A8H
VOH
Write
1,5,6,9
VIH
VIL
VIH
VIL
X
X
X
DIN
X
10
NOTES:
1. X can be VIH or VILfor address or control pins except for RY/BY#, which is either VOL or VOH, or High Z or DOUT for
data pins depending on whether or not OE# is'active.
2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended or the device Is In deep power-down mode.
RY/BY# will be at VOH if it is tied to Vee through a resistor. RY/BY# at VOH is independent of OE# while a WSM
operation is in progress.
3. RP# at GND ±O.2V ensures the lowest deep power-down current.
4. Ao and Al at VIL provide device manufacturer codes in x8 and x16 modes respectively. Ao and Al at VIH provide device
ID codes in x8 and x16 modes respectively. All other addresses are set to zero.
.
5. Commands for Erase, Data Write, or Lock-Block operations can only be completed successfully when Vpp = VPPHt or
Vpp = VPPH2.
'
'
6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes
to VOH when the WSM is not busy or in erase suspend mode.
7, RY/BY# may be at VOL while the WSM is busy performing various operations. For example, a Status Register read
during a Write operation.
'
8. The 28F016XS shares an identical device identifier with other Intel Flash memories. Reading this identifier in conjunction
with the unique Device Proliferation Code (read from the Page Buffer after writing the Upload Device Configuration command), the 28F016XS can be identified by system software.
.
9. CEO_l # at VIL is defined as both CEoII' and CEl # low, and CEo-l # at VIH is defined as either CeoII' or CEl # high.
to. Addresses are latched on the rising edge of CLK in conjunction with ADV# low. Address At = 0 selects the even bank
and Al = 1 selects the odd bank, in both byte-wide mode and word-wide mode device configurations.
3-14
28F016XS FLASH MEMORY
4.3 28F008SA-Compatible Mode Command Bus Definitions
Command
Notes
First Bus Cycle
Oper
Second Bus Cycle
Addr
Data
Oper
Addr
Data
Write
X
FFH
Read
AA
AD
1
Write
X
90H
Read
IA
ID
Read Compatible Status Register
2
Write
X
70H
Read
X
CSRD
Clear Status Register
3
Write
X
50H
Word/Byte Write
Write
X
40H
Write
WA
WD
Alternate Word/Byte Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
SA
DOH
Erase Suspend/Resume
Write
X
BOH
Write
X
DOH
Read Array
Intelligent Identifier
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don't Care
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the Intelligent Identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase, or Suspend operations.
3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register definitions.
3-15
28F016XS FLASH MEMORY
4.4 28F016XS-Performance Enhancement Command Bus Definitions
Command
Mode
Notes
First Bus Cycle
Second Bus Cycle
Oper Addr Data Oper. Addr
1
Write
X
Page Buffer Swap
7
Write
X
72H
Read Page Buffer
11
Write
X
Write
Read Extended
Status Register
Sequential Load
to Page Buffer
Page Buffer
Write to Flash
Two-Byte Write
RA
GSRD
BSRD
75H
Read
PA
PD
X
74H
Write
PA
PD
Write
X
EOH
Write
X
BCL
Write
X
x16
4,5,6,10 Write
X
EOH
Write
X
WCL
Write
X
xB
3,4,9,10 Write
X
OCH
Write
Ao
BC(L,H)
Write
X
OCH
Write
X
WCL
xB
4,6,10
x16
4,5,10
xB
3
Lock Block/Confirm
WD(L,H) Write
WA
WD(H,L)
Write
X
FBH
Write
Ao
Write
X
77H
Write
BA
DOH
X
97H
Write
X
DOH
Upload Device
Information/Confirm
12
Write
X
99H
Write
X
DOH
Write
X
A7H
Write
X
DOH
Write
X
96H
Write
X
DCCD
Sleep
Write
X
FOH
Abort
Write
X
BOH
ADDRESS
BA = Block Address
PA = Page Buffer Address
RA = Extended Register Address
WA = Write Address
X = Don't Care
3-16
DATA
AD = Array Data
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
WCH
BC(H,L)
WCH
Write
B
BCH
WA
2
Erase All Unlocked
Blocks/Confirm
Write . WA
Data
Write
Upload Status
Bits/Confirm
Device
Configuration
Third Bus Cycle
Oper Addr
Read
Single Load to
Page Buffer
71H
Data
WC (L,H) = Word Count (Low, High)
BC (L,H) = Byte Count (Low, High)
WD (L,H) = Write Data (Low, High)
DCCD = Device Configuration Code Data
28F016XS FLASH MEMORY
NOTES:
1. AA can be the GSA address or any BSR address. See Figures 5 and 6 for Extended Status Register memory maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3. Ao is automatically complemented to load second byte of data. BYTE# must be at VIL. Ao value determines which
WD/BC is supplied first: Ao = 0 looks at the WDl/BCl, Ao = 1 looks at the WDH/BCH.
4. BCH/WCH must be at OOH for this product because of the 256-byte (128-word) Page Buffer size, and to avoid writing the
Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandabilily.
5. In x16 mode, only the lower byte DOO_7 is used for WCl and WCH. The upper byte DOa-15 is a don't care.
6. PA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. This command reconfigures RY IBY # output and SFI Configuration.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer.
Refer to the 16-Mbit Flash Product Family User's Manual.
10. BCl = OOH corresponds to a byte count of 1. Similarly, WCl = OOH corresponds to a word count of 1.
11. Page buffer reads are valid at any frequency up to the corresponding SFI Configuration setting of 2. Page buffer reads
above this frequency may produce invalid results and should not be attempted. See Section 4.9 for SFI Configuration
frequency settings.
12. After writing the Upload Device Information command and the Confirm command, the following information is output at
Page Buffer addresses specified below:
Address
06H, 07H (Byte Mode)
03H (Word Mode)
1EH (Byte Mode)
OFH (DOo_7)(Word Mode)
1FH (Byte Mode)
OFH (DOa_15)(Word Mode)
Information
Device Revision Number
Device Revision Number
Device Configuration Code
Device Configuration Code
Device Proliferation Code (03H)
Device Proliferation Code (03H)
A page buffer swap followed by a page buffer read sequence is necessary to access this information. The contents of all
other Page Buffer locations, after the Upload Device Information command is written, are reserved for future implementation
by Intel Corporation. See Section 4.8 for a deSCription of the Device Configuration Code. This code also corresponds to data
written to the 28F016XS after writing the Device Configuration command.
3-17
28F016XS FLASH MEMORY
4.5 Compatible Status Register
I
WSMS
lESS
6
?
I
ES
DWS
VPPS
R
5
4
3
2
CSR.? = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
R
R
o
NOTES:
RY /BY # output or WSMS bit must be checked to determine
completion of an operation (Erase, Erase Suspend, or Data
Write) before the appropriate Status bit (ESS, ES or DWS) is
checked for success.
CSR.6 = ERASE-SUSPEND STATUS
1 = Erase Suspended
= Erase In Progress/Completed
o
CSR.5 = ERASE STATUS
1 = Error In Block Erasure
o = Successful Block Erase
If DWS and ES are set to "1" during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
CSRA = DATA-WRITE STATUS
1 = Error in Data Write
o = Data Write Successful
CSR.3 = Vpp STATUS
1 = Vpp Error Detect, Operation
Abort
0= VppOK
The VPPS bit, unlike an AID converter, does not provide
continuous indication of Vpplevel. The WSM interrogates
Vpp's level only after the Data Write or Erase command
sequences have been entered, and informs the system if
Vpp has not been switched bn. VPPS is not guaranteed to
report accurate feedback between VpPLK(max) and
VPPH1 (min), between VPPH1 (max) and VpPH2(min), and
above VpPH2(max).
CSR.2-0 = RESERVED FOR FUTURE EI')IHANCEMENTS
These bits.are reserved for future use; mask them out when polling theCSR.
3-18
28F016XS FLASH MEMORY
4.6 Global Status Register
I
I
WSMS
7
055
I
6
DOS
055
QS
PBAS
S
4
3
2
GSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
GSR.6
= OPERATION SUSPEND STATUS
1 = Operation Suspended
GSR.S
= DEVICE OPERATION STATUS
o=
PBS
PBSS
o
NOTES:
[1] RY/BY# output orWSMS bit must be checked to
determine completion of an operation (Block Lock,
Suspend, any RY /BY # reconfiguration, Upload Status
Bits, Erase or Data Write) before the appropriate Status
bit (055 or DOS) is checked for success.
Operation in Progress/Completed
1 = Operation Unsuccessful
Operation Successful or Currently
Running
o=
GSR.4 = DEVICE SLEEP STATUS
1 = Device in Sleep
o = Device Not in Sleep
MATRIXS/4
o0 =
Operation Successful or
Currently Running
o 1 = Device in Sleep mode or
Pending Sleep
1 0 = Operation Unsuccessful
1 1 = Operation Unsuccessful or
Aborted
GSR.3
If operation currently running, then GSR.7 = O.
If device pending sleep, then GSR. 7 = o.
Operation aborted: Unsuccessful due to Abort
command.
= QUEUE STATUS
1 = Queue Full
Queue Available
o=
GSR.2 = PAGE BUFFER AVAILABLE STATUS
1 = One or Two Page Buffers
Available
o = No Page Buffer Available
The device contains two Page Buffers.
GSR.1 = PAGE BUFFER STATUS
1 = Selected Page Buffer Ready
o = Selected Page Buffer Busy
Selected Page Buffer is currently busy with WSM
operation
GSR.O
= PAGE BUFFER SELECT STATUS
1 = Page Buffer 1 Selected
Page Buffer 0 Selected
o=
NOTE:
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.
3-19
28F016XS FLASH MEMORY
4.7 Block Status Register
I
BS
7
I
BLS
I
BOS
BOAS
QS
VPPS
S
4
3
2
6
vppL
R
o
NOTES:
BSR.7 = BLOCK STATUS
1 = Ready
0= Busy
[1] RY IBY # output or BS bit must be checked to
determine completion of an operation (Block Lock,
Suspend, Erase or Data Write) before the appropriate
Status bits (BOS, BLS) is checked for success.
BSR.6 = BLOCK LOCK STATUS
1 = Block Unlocked for Write/Erase
o = Block Locked for Write/Erase
BSR.S = BLOCK OPERATION STATUS
1 = Operation Unsuccessful
o = Operation Successful or Currently
Running
BSRA = BLOCK OPERATION ABORT STATUS
1 = Operation Aborted
o = Operation Not Aborted
The BOAS bit will not be set until BSR.7 = 1.
MATRIXS/4
o 0 = Operation Successful or
Currently Running
o 1 = Not a Valid Combination
1 0 = Operation Unsuccessful
1 1 = Operation Aborted
Operation halted via Abort command.
BSR.3 = QUEUE STATUS
1 = Queue Full
o = Queue Available
BSR.2 = VPP STATUS
1 = Vpp Error Detect, Operation Abort
0= VppOK
BSR.1 = VPP LEVEL
1 = VPP Detected at S.OV ± 10%
0= VPP Detected at 12.0V ±S%
BSR.1 is not guaranteed to report accurate feedback
between the VPPH1 and VPPH2 voltage ranges. Writes
and erases with Vpp between VpPLK(max) and VPPH1
(min), between VPPH1 (max) and VpPH2(min), and above
VpPH2(max) produce spurious results and should not be
attempted.
BSR.O = RESERVED FOR FUTURE ENHANCEMENTS
This bits is reserved for future use; mask it out when polling the BSRs.
NOTE:
1. When multiple operations are queued, checking BSA.70nly provides indication of completion for that particular block.
GSA.7 provides indication when all queued operations are completed.
3-20
28F016XS FLASH MEMORY
4.8 Device Configuration Code
I
R
I
7
R
I
SFI2
I
5
6
SFI1
SFIO
RB2
4
3
2
DCC.5-DCC.3 = SFI CONFIGURATION
(SFI2-SFI0)
001 = SFI Configuration 1
010 = SFI Configuration 2
011 = SFI Configuration 3
100 = SFI Configuration 4
(Default)
DCC.2-DCC.0 = RY/BY# CONFIGURATION
(RB2-RBO)
001 = Level Mode (Default)
010 = Pulse-On-Write
011 = Pulse-On-Erase
100 = RY IBY # Disabled
101 = Pulse-On-Write/Erase
RB1
RBO
o
NOTES:
Default SFI Configuration on powerup or return from deep
powerdown mode is 4, allowing system boot from the
28F016XS at any frequency up to the device's maximum
frequency. Undocumented combinations of SFI2-SFI0 are
reserved by Intel Corporation for future implementations
and should not be used.
Undocumented combinations of RB2-RBO are reserved by
Intel Corporation for future implementations and should not
be used.
DCC.7-DCC.6 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when reading the Device Configuration Code. Set
these bits to "0" when writing the desired RY IBY # configuration to the device.
4.9 SFI Configuration Table
.SFI
Configuration
Notes
28F016XS-15
Frequency (MHz)
28F016XS-20
Frequency (MHz)
28F016XS-25·
Frequency (MHz)
4
1,2
66 (and below)
50 (and below)
40 (and below)
3
2
50 (and below)
37.5 (and below)
30 (and below)
2
2
33 (and below)
25 (and below)
20 (and below)
1
2
16.7 (and below)
12.5 (and below)
10 (and below)
NOTE:
1. Default SFI Configuration aiter powerup or return from deep power-down mode via RP# low.
2. SFI Configuration is retained if put in sleep mode via a Sleep or Abort Command.
3-21
28F016XS FLASH MEMORY
5.0 ELECTRICAL SPECIFICATIONS
NOTICE: This data sheet contains information on
products in ~he sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.
5.1 Absolute Maximum Ratings*
+ BO°C
+ 125°C
Temperature Under Bias ............ O°C to
Storage Temperature ............ 65°C to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Vee = 3.3V ± 0.3V Systems(5)
Symbol
Parameter
Notes
Min
Max
Units
Test Conditions
Ambient Temperature
TA
Operating Temperature, Commercial
1
0
70
°C
Vee
Vee with Respect to GND
2
-0.2
7.0
V
Vpp
Vpp Supply Voltage with
Respect to GND
2,3
-0.2
14.0
V
V
Voltage on any Pin (except Vee, Vpp)
with Respect to GND
2
-0.5
I
Current into any Non-Supply Pin
lOUT
Output Short Circuit Current
Vee
4
+ 0.5
V
30
mA
100
mA
Vee = 5.0V ± 0.5V Systems(5)
Symbol
Parameter
Notes
Min
Max
Units
Test Conditions.
Ambient Temperature
TA
Operating Temperature, Commercial
1
0
70
°C
Vee
Vee with Respect to GND
2
-0.2
7.0
V
Vpp
Vpp Supply Voltage with Respect to GND
2,3
-0.2
14.0
V
V
Voltage on any Pin (except Vee, Vpp) with
Respect to GND
2
-2.0
7.0
V
I
Current into any Non-SupplyPin
30
mA
lOUT
Output Short Circuit Current
100
mA
4
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is - 0.5V on input! output pins. During transitions, this level may undershoot to - 2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee+ 0.5V which may overshoot to Vee + 2.0V for periods
<20 ns.
3. Maximum De voltage on Vpp may overshoot to + 14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Ae specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
3-22
28F016XS FLASH MEMORY
5.2 Capacitance
For a 3.3V ± 0.3V System:
Symbol
Parameter
Notes
Typ
Max
Units
Test Conditions
CIN
Capacitance Looking into an
Address/Control Pin
1
6
8
pF
TA
=
25'C, f
=
1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
8
12
pF
TA
=
25'C, f
=
1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
50
pF
For the 28F016XS-20
and 28F016XS-25
1,2
For 5.0V ± 0.5V System:
Notes
Typ
Max
Units
CIN
Symbol
Capacitance Looking into
an Address/Control Pin
Parameter
1
6
8
pF
T A = 25'C, f
COUT
Capacitance Looking into an
Output Pin
1
8
12
pF
TA= 25'C, f = 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
100
pF
For the 28F016XS-20
30
pF
For the 28F016XS-15
1,2
Test Conditions
=
1.0 MHz
NOTE:
1. Sampled, not 100% tested. Guaranteed by design.
2. Intel is currently developing more accurate models for the Transient Equivalent Testing Load Circuits. For more information or to obtain iBIS models, please contact your local Intel/Distribution Sales Office.
3-23
infel~
28F016XS FLASH MEMORY
5.3 Transient Input/Output Reference Waveforms
X::::> 5
2.4 _ _
IN_PU_T_J
0.45
2.0
OUTPUT
T!T POINTS,
0.8
290532-7
AC test inputs are driven at VOH (2.4VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic'''O.'' Input timing begins at
VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns.
Figure 7. Transient InpuVOutput Reference Waveform
(Vee = 5.0V ±O.5V) for Standard Testing Conflguratlon(1)
IN_P_UT_J~'5'--TfT
::: _ _
POINTS---..
1.5 OUTPUT
290532-8
AC test inputs are driven at 3.0V for a Logic "1" and O.OV for a Logic "0." Input timing begins, and output timing ends, at
1.5V. Input rise and fall times (10% to 90%) <10 ns.
Figure 8. Transient Input/Output Reference Waveform (Vee = 3.3V ±O.3V)
High Speed Reference Waveform(2)(Vee = 5.0V ±O.5V)
NOTES:
1. Testing characteristics for 28F016XS-20 at 5V Vee.
2. Testing characteristics for 28F016XS·15 at 5V Vee and 28F016XS-20/28F016XS-25 at 3.3V Vee.
3·24
28F016XS FLASH MEMORY
5.4 DC Characteristics
vee = 3.3V ±0.3V, TA = O°C to +70°C
Symbol
Parameter
Notes
III
Input Load Current
ILO
Output Leakage
Current
Ices
Vee Standby
Current
Max
Units
1
±1
/J- A
Vee = Vee Max,
VIN = Vee or GND
1
±10
/J- A
Vee = Vee Max,
VOUT = Vee or GND
70
130
/J- A
Vee = VeeMax,
CEo#, CE1 #, RP# = Vee ±0.2V
BYTE#, WP# = Vee ±0.2V
orGND ±0.2V
1
4
rnA
Vee = Vee Max,
CEo#, CE1 #, RP# = VIH
BYTE#, WP# = VIH orVIL
1
2
5
/J- A
RP# = GND ± 0.2V
BYTE# = Vee ±0.2VorGND ±0.2V
1,5
Min
Typ
Test Conditions
IceD
Vee Deep
Power-Down
Current
leeR1
Vee Word/Byte
Read Current
1,4,5
65
85
rnA
Vee = Vee Max
CMOS: CEo #, CE1 # = GND ± 0.2V
BYTE# = GND ±0.2VorVee ±0.2V
Inputs = GND ± 0.2V or Vee ± 0.2V
4-Location Access
Sequence: 3-1-1-1 (clocks)
f = 25 MHz, lOUT = 0 rnA
leeR2
Vee Word/Byte
Read Current
1,4,
5,6
60
75
rnA
Vee = Vee Max
CMOS: CEo#, CE1 # = GND ± 0.2V
BYTE# = GND ±0.2V or Vee ±0.2V
Inputs = GND ±O.2V or Vee ± 0.2V
4-Location Access
Sequence: 3-1-1-1 (clocks)
f = 16 MHz, lOUT = 0 rnA
leew
Vee Write Current
1,6
8
12
rnA
Word/Byte Write in Progress
Vpp = 12.0V ±5%
8
17
rnA
Word/Byte Write in Progress
Vpp = 5.0V ± 10%
6
12,
rnA
Block Erase in Progress
Vpp = 12.0V ±5%
9
17
rnA
Block Erase in Progress
Vpp = 5.0V ± 10%
3
6
rnA
CEo#,CE1# = VIH
Block Erase Suspended
IeeE
leeES
Vee Block Erase
Current
Vee Erase
Suspend Current
1,6
1,2
3-25
28F016XS FLASH MEMORY
5.4 DC Characteristics
Vee
=
3.3V ± 0.3V, TA
Symbol
=
(Continued)
O°C to + 70°C
Parameter
Notes
Min
Typ
Max
Units
Test Conditions
±1
±10
Vpp":; Vee
30
50
Ipps
IpPR
Vpp Standby/Read
Current
1
IpPD
Vpp Deep PowerDown Current
1
0.2
5
p.A
p.A
p.A
Ippw
Vpp Write Current
1,6
10
15
rnA
Vpp = 12.0V ±5%
Word/Byte Write in Progress
15
25
rnA
Vpp = 5.0V ± 10%
Word/Byte Write in Progress
4
10
rnA
Vpp = 12.0V ±5%
Block Erase in Progress
14
20
rnA
Vpp = 5.0V ±10%
Block Erase in Progress
30
50
p.A
Vpp = VPPHl or VPPH2,
Block Erase Suspended
IpPE
IpPES
Vpp Erase Current
Vpp Erase
Suspend Current
1,6
1
Vpp> Vee
RP#
=
GND
± 0.2V
6
-0.3
0.8
V
VIH
Input High Voltage
6
2.0
Vee
+0.3
V
VOL
Output Low
Voltage
6
0.4
V
Vee = Vee Min and
IOL = 4 rnA
VOHl
Output High
Voltage
6
V
IOH = -2.0 rnA
Vee = Vee Min
VIL
Input Low Voltage
IOH = -100 p.A
Vee = Vee Min
Vee
-0.2
VOH2
VPPLK
2.4
Vpp Erase/Write
Lock Voltage
3,6
0.0
1.5
V
VPPHl
Vpp during Write/Erase
Operations
3
4.5
5.0
5.5
V
VPPH2
Vpp during Write/Erase
Operations
3
11.4
12,0
12.6
V
VLKO
Vee Erase/Write
Lock Voltage
2.0
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 3.3V, VPP = 12.0V or 5.0V, T = 25'e. These
currents are valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when Vpp \ VPPLK and not guaranteed in the
ranges between VpPLK(max) and VpPH1(min), between VpPH1(max) and VpPH2(min) and above VpPH2(max).
4. Automatic Power Savings (APS) reduces ICCR to 3 mA typical in static operation.
5. eMOS Inputs are either VCC ±0.2V or GND ±0.2V. TIL Inputs are either VIL or VIH.
6. Sampled, but not 100% tested. Guaranteed by design.
3-26
28F016XS FLASH MEMORY
5.5 DC Characteristics
vee = 5.0V ±0.5V, TA = O°C to +70°C
Symbol
Parameter
III
Input Load Current
ILO
Output Leakage
Current
Ices
Vee Standby
Current
Notes Min Typ Max Units
Test Conditions
1
±1
p..A
Vee = Vee Max
VIN= Vee or GND
1
±10
p..A
Vee = Vee Max
VOUT = VeeorGND
70
130
p..A
Vee= Vee Max
CEo#,CE1#,RP# = Vee ± 0.2V
BYTE#, WP# = Vee ±0.2Vor GND ±0.2V
2
4
rnA
Vee = Vee Max
CEo#, CE1 #, RP# = VIH
BYTE#,WP# = VIHorVIL
1,5
IceD
Vee Deep PowerDown Current
1
2
5
p..A
RP# = GND ±0.2V
BYTE # = Vee ± 0.2V or GND ± 0.2V
leeR1
Vee Read Current
1.4,5
120
175
rnA
Vee = Vee Max,
CMOS: CEo# ,CE1 # = GND ±0.2V
BYTE# = GND ±0.2VorVee ±O.2V
Inputs = GND ± 0.2V or Vee ± 0.2V
4-Location Access
Sequence: 3-1-1-1 (clocks)
f = 33 MHz, lOUT = 0 rnA
leeR2
Vee Read Current
1.4,
5,6
105
150
rnA
Vee = Vee Max,
CMOS: CEo #, CE1 # = GND ± 0.2V
BYTE# = GND ±0.2VorVee ±0.2V
Inputs = GND ±0.2VorVee ±0.2V
4-Location Access
Sequence: 3-1-1-1 (clocks) .
f = 20 MHz, lOUT = 0 rnA
leew
Vee Write Current
1,6
25
35
rnA
Word/Byte in Progress
Vpp = 12.0V ±5%
25
40
rnA
Word/Byte in Progress
Vpp = 5.0V ± 10%
18
25
rnA
Block Erase in Progress
Vpp = 12.0V ±5%
20
30
rnA
Block Erase in Progress
Vpp = 5.0V ± 10%
5
10
rnA
CEo#,CE1# = VIH
Block Erase Suspended
IeeE
leeES
Vee Erase
Suspend Current
Vee Block Erase
Current
1,6
1,2
i
3-27
28F016XS FLASH MEMORY
5.5 DC Characteristics
(Continued)
Vee = 5.0V ± 0.5V, T A = O·C to + 70·C
Symbol
Typ
Max
Units
Ipps
IpPR
Vpp Standby/Read
Current
Parameter
Notes
1
Min
±1
± 10
/-LA
Vpp
s
30
50
/-LA
Vpp
IpPD
Vpp Deep PowerDown Current
1
0.2
5
/-LA
RP#
> Vee
= GND
Ippw
Vpp Write Current
1,6
7
12
rnA
Vpp = 12.0V ±5%
Word/Byte Write in Progress
17
22
rnA
Vpp = 5.0V ±10%
Word/Byte Write in Progress
\
IpPE
Vpp Block Erase
Current
1,6
Test Conditions
Vee
±0.2V
5
10
rnA
Vpp = 12.0V ±5%
Block Erase in Progress
16
20
rnA
Vpp = 5.0V ± 10%
Block Erase in Progress
30
50
/-LA
Vpp = VPPH1 or VPPH2,
Block Erase Suspended
IpPES
Vpp Erase
Suspend Current
1
VIL
Input Low Voltage
6
-0.5
0.8
V
VIH
Input High Voltage
6
2.0
Vee
+0.5
V
VOL
Output Low
Voltage
6
0.45
V
Vee = Vee Min
IOL = 5.8 rnA
VOH1
Output High
Voltage
6
V
Vee
IOH = -2.5 rnA
Vee = Vee Min
Vee
-0.4
IOH = -100/-LA
Vee = Vee Min
VOH2
0.85
VPPLK
Vpp Write/Erase
Lock Voltage
VPPH1
Vpp during Write/Erase
Operations
4.5
VPPH2
Vpp during Write/Erase
Operations
11.4
VLKO
Vee Write/Erase
Lock Voltage
2.0
3,6
1.5
V
5.0
5.5
V
12.0
12.6
V
0.0
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = S.OV, VPP = 12.0V or S.OV, T = 2Soe. These
currents are valid for all product versions (package and speeds).
2. ICCES is specified'with the device de-selected, If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when VPP S; VpPLK and not guaranteed in the
ranges between VpPLK(max) and VpPH1(min), between VpPH1(max) and VpPH2(min) and above VpPH2(max).
4. Automatic Power Saving (APS) reduces ICGR to 1 mA typical in Static operation.
5. eMOS Inputs are either VCC ±0.2V or GND ±0.2V. TTL Inputs are either VIL or VIH.
6. Sampled, but not 100% tested. Guaranteed by design.
:
3-28
28F016XS FLASH MEMORY
5.6 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems, use the standard JEDEC cross point definitions (standard testing) or from where signals
cross 1.5V (high speed testing).
Each timing parameter consists of5 characters. Some common examples are defined below:
tELCH time(t) from CE# (E) going low (l) to ClK (C) going high (H)
tAVCH time(t) from address (A) valid (V) to ClK (C) going high (H)
tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)
Pin States
Pin Characters
A
Address Inputs
H
High
C
ClK (Clock)
l
low
0
Data Inputs
V
Valid
Q
Data Outputs
X
Driven, but Not Necessarily Valid
E
CE# (Chip Enable)
Z
High Impedance
F
BYTE# (Byte Enable)
l
latched
G
OE# (Output Enable)
W
WE# (Write Enable)
P
RP# (Deep Power-Down Pin)
R
RY IBY # (Ready Busy)
V
ADV # (Address Valid)
5V
Vcc at 4.5V Minimum
3V
VCC at 3.0V Minimum
3-29
28F016XS FLASH MEMORY
5.7 AC Characteristics-Read Only Operations(1)
vcc
= 3.3V ±0.3V, TA = O°C to +700C
Verslons(3)
Symbol
Parameter
Notes
28F016XS-20
28F016X8-25
Min
Min
Max
Units
Max
fClK
ClK Frequency
tClK
ClKPeriod
20
25
ns
tCH
ClK High Time
6
8.5
ns
tCl
ClKlowTime
6
tClCH
ClK Rise Time
tCHCl
ClKFaliTime
tElCH
CEx# Setup to ClK
tYlCH
ADV # Setup to ClK
20
25
ns
tAvCH
Address Valid to ClK
20
25
ns
tCHAX
Address Hold from ClK
0
0
ns
tCHVH
ADV # Hold from ClK
0
0
ns
tGlCH
OE # Setup to ClK
20
tcHQV
ClK to Data Delay
7
50
40
8.5
4
4
6
ns
4
ns
4
ns
35
25
ns
25
30
MHz
ns
35
ns
tpHCH
RP# High to ClK
480
480
ns
tcHQX
Output Hold from ClK
2
6
6
ns
tElQX
CEx# to Output low Z
2,6
0
tEHQZ
CEx# High to Output High Z
2,6
lGlQX
OE # to Output low Z
2
tGHQZ
OE # High to Output High Z
2
toH
Output Hold from CEx# or OE#
Change, Whichever Occurs First
6
3-30
0
30
0
30
0
ns
0
30
ns
30
0
ns
ns
ns
· 28F016XS FLASH MEMORY
5.7 AC Characteristics-Read Only Operations(1)
VCC = 5.0V ±0.5V, TA = O·C to +70"C
Verslons(3)
Symbol
Parameter
(Continued)
28F016XS-15(4)
Notes
Min
Max
28F016X8-20(5)
Min
Units
Max
fClK
ClK Frequency
tClK
ClKPeriod
15
20
ns
tCH
ClK High Time
3.5
6
ns
tel
ClKlowTime
3.5
telCH
ClK Rise Time
teHCl
ClK Fall Time
,
, tElCH
CEx# Setup to ClK
tVlCH
7
66
50
6
4
ns
4
4
4
6
MHz
ns
ns
25
30
ns
ADV # Setup to ClK
15
20
ns
tAVCH
Address Valid to ClK
15
20
ns
tCHAX
Address Hold from ClK
0
0
ns
teHVH
ADV # Hold from ClK
0
0
ns
lGlCH
OE # Setup to ClK
15
tCHQV
ClK to Data Delay
20
ns
30
20
ns
tPHCH
RP# High to ClK
300
300
ns
tcHQX
Output Hold from ClK
2
5
5
ns
tElQX
CEx# to Output low Z
2,6
0
tEHQZ
CEx# High to Output High Z
2,6
lGlQX
OE # to Output low Z
2
tGHQZ
OE # High to Output High Z
2
toH
Output Hold from CEx# or OE#
Change, Whichever Occurs First
6
0
30
0
0
30
0
ns
30
ns
30
0
ns
ns
ns
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements.
2. Sampled, not 100% tested. Guaranteed by design.
3.. Device speeds are defined as:
15 ns at Vee = 5.0V equivalent to
20 ns at Vee = 3.3V
20 ns at Vee = 5.0V equivalent to
25 ns at Vee = 3.3V
4. See the high speed AC Input/Output Reference Waveforms.
5. See the standard AC Input/Output Reference Waveforms.
6. CEx# is defined as the latter of CEo# or CEl # going low, or the first of CEo# or CEl # going high.
7. Page buffer reads are valid at any frequency up to the corresponding SFI Configuration setting of 2. Page buffer reads
above this frequency may produce invalid results and should not be attempted. See Section 4.9 for SFI Configuration
frequency settings.
3-31
28F016XS FLASH MEMORY
1 4 - - - - t CH - - - - t i
t ClCH
t CHCl
290532-9
Figure 9. ClK Waveform
ClK
ADDR
ADV#
IXxxxxxxxxxxxxxxXXXXXXX
tEHOZ-:""
CEx#
-
OE#
DATA
290532-10
NOTE:
1. The 28F016XS can sustain an endless burst access assuming alternating bank accesses; the length of the burst
access is dictated by the control CPU or bus architecture.
Figure 10. Read Timing Waveform(l) (SFI Configuration = 1, Alternate-Bank Accesses)
3-32
28F016XS FLASH MEMORY
elK
290532-11
NOTE:
1. The 28F016XS can sustain an endless burst access assuming alternating bank accesses; the length of the burst
access is dictated by the control CPU or bus architecture.
Figure 11. Read Timing Waveform(1) (SFI Configuration
=
2, Alternate-Bank Accesses)
3·33
28F016XS FLASH MEMORY
tAVGH
~)/ :~m !~!U :·WlA :~iU .~~ :~!U
CEX#
:tCHVH
I
I
,
I
,
I
:w :ij1 :ummmim~!!~~
,
t'
OE#
DATA
--~--~----~--~~
290532-12
NOTES:
1. The 28F016XS can sustain an endless burst access assuming alternating bank accesses; the length of the burst
access is dictated by the control CPU or bus architecture.
2. Depending on the actual operation frequency, a consecutive alternating bank access can be initiated one clock period
earlier. See AP-398 for further information.
.
Figure 12. Read Timing Waveform(1) (SFI Configuration = 3, Alternate-Bank Access~s)
3-34
28F016XS FLASH MEMORY
tAVGH
,
,
~1l. ~!i! •~!~ .,. ~!~ .1n~ •~llr •wr ., ., •~nml!l!~~lmm
CEx#
,..
taax
~HQZ
~
DE#
DATA
--~--~--~----~--~H
}4-IpHCH :
290532-13
NOTE:
1. The 28F016XS can sustain an endless burst access assuming alternating bank accesses; the length of the burst
access is dictated by the control CPU or bus architecture.
Figure 13. Read Timing Waveform(1) (SFI Configuration
=
4, Alternating Bank Accesses)
3-35
intel~
28F016XS FLASH MEMORY
5.8 AC Characteristics for WE#-Controlled Write Operations(1)
vcc
= 3.3V ±0.3V, TA = O·Gto +70·G
Versions
Symbol
Parameter
tAVAV
Write Cycle Time
tVPWH
Vpp Setup to WE#
Going High
tpHEL
28F016XS-20
Notes
Min
Typ
Max
28F016XS-25
Min
Typ
Unit
Max
75
75
ns
3
100
100
ns
RP# Setup to GEx#
Going Low
3,7
480
480
ns
tELWL
GEx# Setup to WE#
Going Low
3,7
0
0
' ns
tAVWH
Address Setup to WE #
Going High
2,6
60
60
ns
tOVWH
Data Setup to WE #
Going High
2,6
60
60
ns
tWLWH
WE # Pulse Width
60
60
ns
tWHOX
Data Hold from WE# High
2
5
5
ns
tWHAX
Address Hold from
WE# High
2
5
5
ns
tWHEH
GEx# hold from WE# High
tWHWL
WE # Pulse Width High
tGHWL
Read Recovery
before Write
3
tWHRL
WE # High to RY IBY #
Going Low
3
tRHPL
RP# Hold from Valid Status
Register (GSR, GSR, BSR)
data and RYIBY # High
3
,0
tPHWL
RP# High Recovery
to WE # Going Low
3
tWHCH
Write Recovery
before Read
tavvL
VPP Hold from Valid Status
Register (GSR, GSR, BSR)
Data and RY IBY # High
tWHQV1
Duration of WordlByte
Write Operation
tWHQV2
Duration of Block
Erase Operation
3-36
3,7
5
5
ns
15
15
ns
0
0
ns
100
100
ns
0
ns
480
480
ns
3
20
20
ns
3
0
0
/Ls
3,4,5
5
9
TBD
5
9
TBD
/Ls
3,4
0.6
1.6
20
0.6
1.6
20
sec
28F016XS FLASH MEMORY
5.8 AC Characteristics for WE #-Controlled Write Operations(1)
(Continued)
Vcc = 5.0V ±0.5V, TA = O°C to +70°C
Versions
Symbol
Parameter
28F016XS·15
Typ
Max
28F016XS-20
Min
Typ
Unit
Notes
Min
Max
65
65
ns
3
100
100
ns
tAVAV
Write Cycle Time
tVPWH
Vpp Setup to WE#
Going High
tpHEL
RP# Setup to CEx# Going Low
3,7
300
300
ns
tELWL
CEx# Setup to WE#
Going Low
3,7
0
0
ns
tAVWH
Address Setup to WE #
Going High
2,6
50
50
ns
tDVWH
Data Setup to WE # Going High
2,6
50
50
ns
tWLWH
WE # Pulse Width
50
50
ns
tWHDX
Data Hold from WE# High
0
0
ns
2
5
5
ns
3,7
5
5
ns
15
15
ns
0
0
ns
2
tWHAX
Address Hold from WE # High
tWHEH
CEx# hold from WE# High
tWHwL
WE # Pulse Width High
tGHWL
Read Recovery
before Write
3
tWHRL
WE # High to RY IBY #
Going Low
3
tRHPL
RP# Hold from Valid Status
Register (CSR, GSR, BSR)
data and RY IBY # High
3
0
0
ns
tPHWL
RP # High Recovery
to WE# Going Low
3
300
300
ns
tWHCH
Write Recovery
before Read
3
20
20
ns
tQVVL
Vpp Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RY IBY # High
3
0
0
JLs
tWHQV1
Duration of Word/Byte
Write Operation
3,4,5
4.5
6
TBD
4.5
6
TBD
JLs
tWHQV2
Duration of Block
Erase Operation
3,4
0.6
1.2
20
0.6
1.2
20
sec
100
100
ns
NOTES:
1. Read timings during Write and Erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested. Guaranteed by design.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Word/Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE# for all Command Write operations.
7. CEx# is defined as the latter of CEo# or CE1 # going low, or the first of CEo# or CE1 # going high.
3-37
28F016XS FLASH MEMORY
ct.,
DEEP
POWER-DOWN
'"'V.
NO'' '
CEll. IE)
NOT"
OE'(Gj
VIH
V ..
WE'(W)
DATA(QiQ)
v":"'--:==-+-<1
V,
.... ,F'}
~~~~~~~~~~~~~'"WW'~H=--:::~__:=__~=-~-=~~:=__~=-'\~~~~~~~~!!I
V,~
V,,,",
V,,,,,
v~
_________________________ _
~7
290532-14
NOTES:
1. This address string depicts Data Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data Write/Erase cycles with corresponding verification via eSRD.
3. This cycle is invalid when using CSRD for verification during Data Write/Erase operations.
4. CEx# is defined as the latter of CEo# or CEl # going low or the first of CEo* or CEl # going high.
5. RP# low transition is only to show tRHPL; not valid for above Read and Write cycles.
6. Data Write/Erase cycles are asynchronous; CLK and ADV* are ignored.
7. Vpp voltage during Data Write/Erase operations valid at both 12.0V and 5.0V.
B. Vpp voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 14. AC Waveforms for WE#Command Write Operations, illustrating a
Two Command Write Sequence Followed by a Extended Status Register Read
3-38
28F016XS FLASH MEMORY
5.9 AC Characteristics for CEx#-Controlied Write Operations(1)
vcc
= 3.3V
± 0.3V, T A
= O°C to
+ 70°C
Versions
Symbol
Parameter
28F016XS·20
Notes
Min
Typ
Max
28F016XS·25
Min
Typ
Unit
Max
tAVAV
Write Cycle Time
75
75
ns
tVPEH
VPP Setup to CEx#
Going High
3,7
100
100
ns
tPHWL
RP# Setup to WE#
Going Low
3
480
480
ns·
tWLEL
WE# Setup to CEx#
Going Low
3,7
0
0
ns
tAvEH
Address Setup to CEx#
Going High
2,6,7
60
60
ns
tOVEH
Data Setup to CEx#
Going High
2,6,7
60
60
ns
tELEH
CEx # Pulse Width
7
60
60
ns
tEHOX
Data Hold from CEx# High
2,7
10
10
ns
tEHAX
Address Hold from
CEx# High
2,7
10
10
ns
tEHWH
WE hold from CEx# High
3,7
5
5
ns
tEHEL
CEx# Pulse Width High
7
15
15
ns
tGHEL
Read Recovery
before Write
3
0
0
ns
tEHRL
CEx# High to RY IBY #
Going Low
tRHPL
RP# Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RYIBY # High
tpHEL
RP# High Recovery to
CEx# Going Low
tEHCH
100
100
3,7
ns
3
0
0
ns
3,7
480
480
ns
Write Recovery
before Read
3
20
20
ns
tQVVL
VPP Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RYIBY # High
3
0
0
/Ls
tEHQVl
Duration of Word/Byte
Write Operation
3,4,5
5
9
TBD
5
9
TBD
/Ls
3,4
0.6
1.6
20
0.6
1.6
20
sec
tEHQV2
Duration of Block
. Erase Operation
3-39
28F016XS FLASH MEMORY
5.9 AC Characteristics for CEx # Controlled Write Operations(1)
(Continued)
Vcc = 5.0V ±0.5V, TA = O·C to +70·C
Versions
Symbol
28F016XS-15
Parameter
tAVAV
Write Cycle Time
tPHWL
RP# Setup to WE# Going Low
tVPEH
Notes
Min
Typ
Max
28F016XS-20
Min
Typ
Unit
Max
60
60
ns
3
300
300
ns
Vpp Setup to CEx#
Going Low Going High
3,7
100
100
ns
tWLEL
WE# Setup to CEx#
Going Low
3,7
0
0
ns
tAVEH
Address Setup to CEx#
Going High
2,6,7
45
45
ns
tDvEH
Data Setup to CEx# Going High
2,6,7
45
45
ns
tELEH
CEx# Pulse Width
7
45
45
ns
tEHDX
Data Hold from
Going HighCEx# High
2,7
0
0
ns
ns
tEHAX
Address Hold from CEx# High
2,7
5
5
tEHWH
WE hold from CEx# High
3,7
5
5
ns
tEHEL
CEx# Pulse Width High
7
15
15
ns
tGHEL
Read Recovery
before Write
3
0
0
ns
tEHRL
CEx# High to RY/BY#
Going Low
tRHPL
RP# Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RYIBY # High
3,7
100
100
ns
3
0
0
ns
3,7
300
300
ns
..
tpHEL
RP# High Recovery to
CEx# Going Low
tEHCH
Write Recovery
before Read
3
20
20
ns
tQWL
Vpp Hold from Valid Status
Register (CSR, GSR, BSR)
Data and RY IBY # High
3
0
0
,...s
tEHQV1
Duration of Word/Byte
Write Operation
3,4,5
4.5
6
TBD
4.5
6
TBD
,...s
tEHQV2
Duration of Block
Erase Operation
3,4
0.6
1.2
20
0.6
1.2
20
sec
NOTES:
1.
2.
3.
4.
5.
6.
7.
Read timings during Write and Erase are the same as for normal read.
Refer to command definition tables for valid address and data values.
Sampled, but not 100% tested. Guaranteed by design.
Write/Erase durations are measured to valid Status Register (CSR) Data.
Word/Byte Write operations are typically performed with 1 Programming Pulse.
Address and Data are latched on the rising edge of WE# for all Command Write operations.
CEx# is defined as the latter of CEo# or CE1 # gOing low, or the first of CEo# or CE1 # going high.
3-40
28F016XS FLASH MEMORY
AOV'
V ,H
WE'(W)
VOL
'eHCH
V,H
OE'(G)
VOL
'EHOV12
V,H
""'0.,
VOL
V IH
OATA(DIQ)
VOL
VOH
RYISV.(R)
vOl.
V,H
RPf(P)
VOL
t VPEH
V pPH1
VpPH2
VppM
VPPlJ(
VOL
NOTE a
290532-15
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
This address string depicts Data Write/Erase cycles with corresponding verification via ESRD.
This address string depicts Data Write/Erase cycles with corresponding verification via CSRD.
This cycle is invalid when using CSRD for verification during Data Write/Erase operations.
CEx# is defined as the latter of CEo# or CEl # going low or the first of CEo# or CEl # going high.
RP# low transition is only to show tRHPL; not valid for above Read and Write cycles.
Data Write/Erase cycles are asynchronous; ClK and ADV# are ignored.
Vpp voltage during Data Write/Erase operations valid at both 12.0V and 5.0V.
Vpp voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 15. AC Waveforms for CEx#--,Controlled Write Operations, illustrating a
Two Command Write Sequence Followed by a Extended Status Register Read
3-41
28F016XS FLASH MEMORY
5.10 AC Characteristics for WE#-Controlled Page Buffer Write Operations(1)
vee = 3.3V ±O.3V, TA = O·C to +70·C
Versions
Symbol
tAVWL
I
28F016XS·20
Parameter,
Notes
Min
Address Setup to WE#
Going Low
2
0
Parameter
Notes
Min
Address Setup to WE #
Going Low
2
0
Typ
28F016XS·25
Max
Min
Typ
Unit
Max
0
ns
Vee = 5.0V ±O.5V, TA = O·C to +70·C
Versions
Symbol
tAVWL
28F016XS·15
Typ
Max
28F016X5-20
"
Min
Typ
0
Unit
Max
ns
NOTES:
1. All other specifications for WE#Controlied Page Buffer Write Operations see Section 5.B.
2. Address must be valid during the entire WE# low pulse.
V1H
CEx#(E)
NOTE 1
V1L
1 ELWL
1WHEH
V1H
1WHWL
WE#(!N)
V1L
'WLWH
'WHAX
V1H
ADDRESSES (A)
VALID
V1L
J
'OVWH
V1H
DATA (OIQ)
V1L
HIGHZ
(
OjN
9
c
290532-16
NOTE:
1. CEx# is defined as the latter of CEo# or CE I # going low, or the first of CEo# or CEI # going high.
Figure 16. WE#--controlled Page Buffer Write Timing Waveforms
(Loading Data to the Page Buffer)
3·42
28F016XS FLASH MEMORY
5.11 AC Characteristics for CEx #-Controlled Page Buffer Write Operations
vcc =
3.3V ±O.3V, TA
=
O·C to +70·C
Symbol
tAVEL
VCC
=
Parameter
Notes
Min
Address Setup to CEx#
Going Low
2,3
0
Parameter
Notes
Min
Address Setup to CEx#
Going Low
2,3
0
5.0V ±O.5V, TA
=
tAVEL
Typ
Max
Min
Typ
Unit
Max
0
ns
O·C to +70"C
28F016XS-15
Versions
Symbol
28F016XS-25
28F016XS-20
Versions
Typ
Max
28F016XS-20
Min
Typ
0
Unit
Max
ns
NOTES:
1. All other specifications for CEx#Controlled Page Buffer Write Operations see Section 5.9.
2. Address must be valid during the entire CE# low pulse.
3. CEx# is defined as the latter of CEo# or CEl # going lOw, or the first of CEo# or CEl # going high.
WE#(W)
VIL
IWLB.
IEHWH
VIH
IEHEL
, CExII (E)
NOTE 1
VIL
IELEH
IEHAX
VIH
ADORESSES (A)
VALlO
VIL
J
IOVEH
VIH
DATA (DIQ)
VIL
HIGHZ
(
OjN
9
c
290532-17
NOTE:
1. CEx# is defined as the latter of CEo# or CEl # going low, or the first of CEo# or CEl # going high.
Figure 17. CEx#-Controlled Page Buffer Write Timing Waveforms
(Loading Data to the Page Buffer)
3-43
28F016XS FLASH MEMORY
5.12 Power-Up and Reset Timings
Vee POWER-UP
___
---I.
API!
S.OV
(P)
,---~-------------
,
'.
Vee
(3V,SV)
ISVPH
'
~'
~,
290S32-18
NOTE:
For read timings following reset see Section 5.7.
Figure 18. Vee Power-Up and RP# Reset Waveforms
Symbol
Parameter
Notes
Min
tpL5V
RP# Low to Vee at 4,5V (Minimum)
2
0
Max
Unit
f-Ls
tpL3V
RP# Low to Veeat 3.0V (Minimum)
2
0
p.s
t5VPH
Vee at 4.5V Minimum) to RP# High
1
2
p.s
t3VPH
Vee at 3.0V (Minimul"(1) to RP# High
1
2
p.s
NOTES:
1. The tSVPH and/or t3VPH times must be strictly followed to guarantee all other read and write specifications for the
28F016XS,.
2. The power supply may start to switch concurrently with RP# going low.
3-44
28F016XS FLASH MEMORY
5.13 Erase and Word/Byte Write Performance(3,5)
vee
= 3.3V ± 0.3V, vpp = 5.0V ± 0.5V, TA = DoC to + 70°C
Symbol
Parameter
Notes
Min
Typ(1)
Max
Units
fLs
fLs
fLs
fLs
Page Buffer Byte Write Time
2
TBD
6.0
TBD
Page Buffer Word Write Time
2
TBD
12.1
TBD
Test Conditions
tWHRH1A
Byte Write Time
2
TBD
16.5
TBD
tWHRH1B
Word Write Time
2
TBD
24.0
TBD
tWHRH2
Block Write Time
2
TBD
2.2
TBD
sec
Byte Write Mode
tWHRH3
Block Write Time
2
TBD
1.6
TBD
sec
Word Write Mode
Vee
Block Erase Time
2
TBD
2.8
TBD
sec
Full Chip Erase Time
2
TBD
44.8
TBD
sec
Time From Erase
Suspend Command to
WSM Ready
4
TBD
10
TBD
fLs
= 3.3V ±0.3V, Vpp = 12.0V ±0.6V, TA = DOC to +70°C
Symbol
Parameter
Notes
Min
Typ(1)
Max
Units
Page Buffer Byte Write Time
2
TBD
2.2
TBD
Test Conditions
Page Buffer Word Write Time
2
TBD
4.4
TBD
tWHRH1
Word/Byte Write Time
2
5
9
TBD
fLs
fLs
fLs
tWHRH2
Block Write Time
2
TBD
1.2
4.2
sec
Byte Write Mode
tWHRH3
Block Write Time
2
TBD
0.6
2.0
sec
Word Write Mode
Block Erase Time
2
0.6
1.6
20
sec
Full Chip Erase Time
2
TBD
25.6
TBD
sec
Time From Erase
Suspend Command to
WSM Ready
4
TBD
10
TBD
fLs
3-45
28F016XS FLASH MEMORY
5.13 Erase and Word/Byte Write Performance(3,5)
Vcc
=
s.OV ±O.SV, Vpp
=
(Continued)
S.OV ±O.SV, TA = O°C to +70·C
Notes
Min
Typ(1)
Max
Units
Page Buffer Byte
Write Time
2
TBD
6.0
TBD
Il s
Page Buffer Word
2
TBD
12.1
TBD
Il s
tWHRH1A
Byte Write Time
2
TBD
11
TBD
tWHRH1B
Word Write Time
2
TBD
16
TBD
Il s
tWHRH2
Block Write Time
2
TBD
1.6
TBD
sec
Byte Write Mode
Word Write Mode
Symbol
Parameter
Test Conditions
Write Time
tWHRH3
Vcc
=
Block Write Time
2
TBD
1.2
TBD
sec
Block Erase Time
2
TBD
2.0
TBD
sec
Full Chip Erase Time
2
TBD
32.0
TBD
sec
Time From Erase
Suspend Command to
WSM Ready
4
TBD
10
TBD
Il s
S.OV ±O.SV,Vpp
Symbol
, Il s
=
12.0V ±0.6V, TA
Parameter
=
O·C to +70·C
Notes
Min
Typ(1)
Max
Units
Il s
Test Conditions
Page Buffer Byte Write Time
2
TBD
2.1
TBD
Page Buffer Word Write Time
2
TBD
4.1
TBD
Il s
tWHRH1
Word/Byte Write Time
2
4.S
6
TBD
Il s
tWHRH2
Block Write Time
2
TBD
0.8
4.2
sec
Byte Write Mode
tWHRH3
Block Write Time
2
TBD
0.4
2.0
sec
Word Write Mode
Block Erase Time
2
0.6
1.2
20
' sec
Full Chip Erase Time
2
. TBD
19.2
TBD
sec
Time From Erase
Suspend Command to
WSM Ready
4
TBD
10
TBD
Il s
NOTES:
1. 25°C, and nominal voltages.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Specification applies to interruPt latency for Single Block Erase. Suspend latency for Erase All Unlocked Block operation
typically extends erase suspend latency time to 140 IJ.s.
5. Sampled, but not 100% tested. Guaranteed by design.
3-46
28F016XS FLASH MEMORY
6.0 MECHANICAL SPECIFICATIONS
o
1+----o1-----+1
A~r__-----------,~SEE.OETAIL A
r--)------------~~
OETAIL A
DETAIL B
®
JL.
290532-19
Figure 19. Mechanical S~eclflcatlons of the 28F016XS56·Lead TSOP Type I Package
Family: Thin Small Out·Line Package
Millimeters
Symbol
Minimum
Nominal
Notes
Maximum
1.20
A
A2
0.50
0.965
0.995
1.025
b
0.100
0.150
0.200
c
0.115
0.125
0.135
01
18.20
13.80
18.40
14.00
14.20
0
19.80
20.00
20.20
L
0.500
0.600
0.700
0°
56
3°
5°
0.150
0.250
0.350
A1
E
e
N
0
0.50
Y
Z
18.60
0.100
3-47
28F016XS FLASH MEMORY
DEVICE NOMENCLATURE AND ORDERING INFORMATION
Product line designator for all Intel Flash products
..............
y
'-r-'
Period of Maximum eLK
Input Frequency (ns)
Package
E=TSOP
Device Type
S = Synchronous Pipelined
Interface
'
290532-20
Valid Combinations
Option
Order Code
Vee = 3.3V ±0.3V,
SO pFload,
1.SV 1/0 Levels(1)
1
E28F016XS15
28F016XS-20
2
E28F016XS20
28F016XS-25
3-48
= S.OV ± 10%,
100 pFload
TTL 1/0 Levels(1)
Vee
= S.OV ± 10%,
30 pF load
1.SV 1/0 Levels(1)
Vee
28F016XS-15
28F016XS-20
28F016XS FLASH MEMORY
ADDITIONAL INFORMATION
Order Number
Document/Tool
297372
16-Mbit Flash Product Family User's Manual,
28F016SA/28F016SV/2BF016XS/28F016XD
292147
AP-398, "Designing with the 28F016XS"
297500
"Interfacing the 28F016XS to the i960@ Microprocessor Family"
297504
"Interfacing the 28F016XS to the Intel486TM Microprocessor Family"
292146
AP-600, "Performance Benefits and Power/Energy Savings of 2BF016XS
Based System Designs"
297508
FlashBuilder Utility
Contact Intel/Distribution
Sales Office
28F016XS Benchmark Utility FlashBuilder
Contact Intel/Distribution
Sales Office
28F016XS iBISIVHDL Models
Contact Intel/Distribution
Sales Office
28F016XS OrcadlViewlogic Schematic Symbols
292126
AP 377, "16-Mbit Flash Product Family Software Drivers
28F016SAl28F016SV /28F016XS/28F016XD;'
294016
ER 33, "ETOXTM Flash Memory Technologylnsight to Intel's
Fourth Generation Process Innovation"
•
DATASHEET REVISION HISTORY
Description
Original Version
3-49
28F016XD
16-MBIT (1 MBIT X 16)
DRAM-INTERFACE FLASH MEMORY
ns Access Time (tRAC)
• 85Multiplexed
Address Bus
• RAS# and CAS#
Inputs
• No-Glue Interface Control
• Controllers to Many Memory
Technology
• -SmartVoltage
User-Selectable 3.3V or 5V VCC
- User-Selectable 5V or 12V Vpp
MB/sec Burst Write Transfer Rate
• 30.8
0.48 MB/sec Sustainable Write Transfer
• Rate
Architecture
• x16
56-Lead TSOP Type I Package
•
Backwards-Compatible with
• 28F016SA/SV,
28F008SA Command Set
Revolutionary Architecture
• - Multiple Command Execution
- Write during Erase
- Page Buffer Write
2 p,A Typical Deep Power-Down
• Current
1 rnA Typical Icc Active Current in
• Static
Mode
32 Separately-Erasable/Lockable
• 64-Kbyte Blocks
1 Million Erase Cycles per Block
• State-of-the-Art
• Flash Technology0.6 p,m ETOXTM IV
Intel's 28F016XD 16-MBit Flash memory is a revolutionary architecture which is the ideal choice for designing
truly revolutionary high-performance products. Combining its DRAM-like read performance and interface with
the intrinsic non-volatility of flash memory, the 28F016XD eliminates the traditional redundant memory paradigm of shadowing code from a slow nonvolatile storage source to a faster execution memory, such as DRAM,
for improved system performance. The innovative capabilities of the 28F016XD enable the design of direct-execute code and mass storage data/file flash memory systems.
'
The 28F016XD is the highest performance high density nonvolatile read/write flash memory solution available
today. Its DRAM-like interface with a multiplexed address bus, flexible Vee and Vpp voltages, power saving
features, extended cycling, fast write and read performance, symmetrically blocked architecture, and selective
block locking provide a highly flexible memory component suitable for resident flash component arrays on the
system board or SIMMs. The DRAM-like interface with RAS# and CAS# control inputs allows for easy
migration to flash memory in existing DRAM-based systems. The 28F016XD's dual read voltage allows the
same component to operate at either 3.3V or 5.0V Vee. Programming voltage at 5V Vpp minimizes external
circuitry in minimal-chip, space critical designs, while the 12V Vpp option maximizes write/erase performance.
The x16 architecture allows optimization of the memory-to-processor interface. Its high read performance
combined with flexible block locking enable both storage and execution of operating systems/application
software and fast access to large data tables. The 28F016XD is manufactured on Intel's 0.6 J.Lm ETOXTM IV
process technology.
290533-22
3-50
November 1994
Order Number: 2905330001
28F016XD
16-MBIT (1 MBIT X 16)
DRAM-INTERFACE FLASH MEMORY
CONTENTS
PAGE
1.0 INTRODUCTION .................... 3-52
1.1 Product Overview ................. 3-52
2.0 DEVICE PINOUT .................... 3-55
2.1 Lead Descriptions ................ 3-56
3.0 MEMORY MAPS .................... 3-58
3.1 Extended Status Registers Memory
Map ............................... 3-59
4.0 BUS OPERATIONS, COMMANDS
AND STATUS REGISTER
DEFINITIONS ........................
4.1 Bus Operations ...................
4.2 2BFOOBSA-Compatible Mode
Command Bus Definitions ..........
4.3 2BF016XD-Performance
Enhancement Command Bus
Definitions .........................
4.4 Compatible Status Register .......
4.5 Global Status Register ............
4.6 Block Status Register .............
4.7 Device Configuration Code ........
5.0 ELECTRICAL SPECiFiCATIONS ....
5.1 Absolute Maximum Ratings .; .....
5.2 Capacitance ......................
5.3 Transient Input/Output Reference
Waveforms ........................
3-60
CONTENTS
PAGE
5.6 AC Characteristics
(Vee = 3.3V ± O.3V) .............. 3-77
Read, Write, Read-Modify-Write and
Refresh Cycles (Common
Parameters) .................... 3-77
Read Cycle ....................... 3-77
Write Cycle ........................ 3-78
Read-Modify-Write Cycle .......... 3-79
Fast Page Mode Cycle ............ 3-79
. Fast Page Mode Read-Modify-Write
Cycle ........................... 3-79
Refresh Cycle ..................... 3-80
3-60
Misc. Specifications ............... 3-81
3-61
5.7 AC Characteristics
(Vee = 5.0V ± O.5V) .............. 3-82
3-62
Read, Write, Read-Modify-Write and
Refresh Cycles (Common
Parameters) .................... 3-82
3-64
Read Cycle ....................... 3-83
3-65
Write Cycle ........................ 3-84
3-66
3-67
Read-Modify-Write Cycle .......... 3-84
Fast Page Mode Cycle ............ 3-84
3-68
Fast Page Mode Read-Modify-Write
Cycle ........................... 3-85
3-68
3-69
3-70
Refresh Cycle ..................... 3-85
Refresh ........................... 3-85
Misc. Specifications ............... 3-86
5.4 DC Characteristics
(Vee = 3.3V ± O.3V) .............. 3-71
5.B AC Waveforms ................... 3-87
5.5 DC Characteristics
(Vee = 5.0V ± O.5V) .............. 3-74
5.10 Erase and Word Write
Performance ...................... 3-100
5.9 Power-Up and Reset Timings ..... 3-99
6.0 MECHANICAL SPECIFICATIONS .. 3-101
DEVICE NOMENCLATURE AND
ORDERING INFORMATION ......... 3-102
ADDITIONAL INFORMATION ......... 3-103
DATASHEET REVISION HiSTORy .... 3-103
I
3-51
28F016XD
1.0 INTRODUCTION
The documentation of the Intel 28F016XD flash
memory device includes this datasheet, a detailed
user's manual, and a number of application notes
and design tools, all of which are referenced at the
end of this datasheet.
The datasheet is intended to give an overview of the
chip feature-set and of the operating AC/DC specifications. The 16-Mbit Flash Product Family User's
Manual provides complete descriptions of the user
modes, system interface examples and detailed descriptions of all principles of operation. It also contains the full list of software algorithm flowcharts,
and a brief section on compatibility with the Intel
28F008SA.
The 28F016XD incorporates SmartVoltage technology, providing Vee operation at both 3.3V and 5.0V
and program and erase capability at Vpp = 12.0Vor
5.0V. Operating at Vee = 3.3V, the 28F016XD consumes less than 60% of the power consumption at
5.0V Vee, while 5.0V Vee provides highest read performance capability. Vpp = 5.0V operation eliminates the need for a separate 12.0V converter, while
Vpp = 12.0V maximizes write/erase performance.
In addition to the flexible program and erase voltages, the dedicated Vpp gives complete code protection with Vpp ,,;: VPPLK.
Internal 3.3V or 5.0V Vee detection automatically
configures the device internally for optimized 3.3V or
5.0V Read/Write operation.
1.1 Product Overview
A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation.
The 28F016XD is a high-performance, 16-Mbit
(16,777,216-bit) block erasable, nonvolatile random
access memory, organized as 1 Mword x 16. The
28F016XD includes thirty-two 32-KW (32,768 word)
blocks. A chip memory map is shown in Figure 3.
Internal Algorithm Automation allows Word Writes
and Block Erase operations to be executed using a
Two-Write command sequence to the CUI in the
same way as the 28F008SA 8-Mbit FlashFile™
memory.
The implementation of a new architecture, with
many enhanced features, will improve the device operating characteristics and result in greater product
reliability and ease-of-use as compared to other
flash memories. Significant features of the
28F016XD include:
A super-set of commands has been added to the
basic 28F008SA command-set to achieve higher
write performance and provide additional capabilities. These new commands and features include:
• No-Glue Interface to Memory Controllers
• Improved Word Write Performance
• SmartVoltage Technology
- Selectable 3.3Vor 5.0V Vee
- Selectable 5.0V or 12.0V Vpp
• Internal 3.0V/5.0V Vee Detection Circuitry
• Block Write/Erase Protection
The 28F016XD's multiplexed address bus with
RAS# and CAS# inputs allows for a "No Glue" interface to many existing in-system memory controllers. As such, 28F016XD-based SIMMs (72-pin
JEDEC Standard) offer attractive advantages over
their DRAM counterparts in many applications. For
more information on 28F016XD-based SIMM designs, see the application note referenced at the end
of this datasheet.
3-52
•
•
•
•
•
Page Buffer Writes to Flash
Command Queuing Capability
Automatic Data Writes during Erase
Software Locking of Memory Blocks
Erase All Unlocked Blocks
Writing of memory data is performed in word increments typically within 6 /Lsec (12.0V Vpp) - a 33%
improvement over the 28F008SA. A Block Erase operation erases one of the 32 blocks in typically 0.6
sec (12.0V Vpp), independent of the other blocks,
which is about a 65% improvement over the
28F008SA.
Each block can be written and erased a minimum of
100,000 cycles. Systems can achieve one million
Block Erase Cycles by providing wear-leveling algorithms and graceful block retirement. These techniques have already been employed in many flash
file systems and hard disk drive designs.
28F016XD
The 2BF016XD incorporates two Page Buffers of
256 bytes (12B words) each to allow page data
writes. This feature can improve a system write performance by up to 4.B times over previous flash
memory devices, which have no Page Buffers.
All operations are st~rted by a sequence of Write
commands to the device. Three types of Status
Registers (described in detail later in this datasheet)
and a RY IBY # output pin provide information on
the progress of the requested operation.
While the 2BFOOBSA requires an operation to complete before the next operation can be requested,
the 2BF016XD allows queuing of the next operation
while the memory executes the current operation.
This eliminates system overhead when writing several bytes in a row to the array or erasing several
blocks at the same time. The 2BF016XD can also
perform Write operations to one block of memory
while performing Erase of another block.
The 2BF016XD provides selectable block locking to
protect code or data such as direct-executable operating systems or application code. Each block has
an associated nonvolatile lock-bit which determines
the lock status of the block. In addition, the
2BF016XD has a master Write Protect pin (WP#)
which prevents any modifications to memory blocks
whose lock-bits are set.
The 2BF016XD contains three types of Status Registers to accomplish various functions:
• A Compatible Status Register (CSR) which is
100% compatible with the 2BFOOBSA FlashFile™
memory Status Register. The CSR, when used
alone, provides a straightforward upgrade capability to the 2BF016XD from a 2BFOOBSA-based
design.
• A Global Status Register (GSR) which infdrms
the system of command .Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
• 32 Block Status Registers (BSRs) which provide
block-specific status information such as the
block lock-bit status.
The GSR and BSR memory maps are shown in Figure 4.
The 2BF016XD incorporates an open drain RY IBY #
output pin. This feature allows the user to OR-tie
many RY IBY # pins together in a multiple memory
configuration such as a Resident Flash Array. The
RY IBY # pin employs five distinct configurations,
which are enabled via special CUI commands and
are described in detail in the 16-Mbit Flash Product
Family User's Manual.
The 2BF016XD's enhanced Upload Device Information command provides access to additional information that the 2BF016SA previously did not offer.
This command uploads the Device Revision Number, Device Proliferation Code and Device Configuration Code. The Device Proliferation Code for the
2BF016XD is 04H, and the Device Configuration
Code identifies the current RY IBY # configuration.
Section 4.3 documents the exact page buffer address locations for all uploaded information. A subsequent Page Buffer Swap and Page Buffer Read
command sequence is necessary to read the correct
device information.
The 2BF016XD is specified for a maximum fast page
mode cycle time of 65 ns (tpc R) at 5.0V operation
(4.75V to 5.25V) over the commercial temperature
range (O·C to + 70·C). A corresponding ,maximum
fast page mode cycle time of 75 ns at 3.3V (3.0V to
3.6V and O·C to .+ 70·C) is achieved for reduced
power consumption applications. '
The 2BF016XD incorporates an Automatic Power
Saving (APS) feature, which substantially reduces
the active current when the device is in static mode
of operation (addresses not switching). In APS
mode, the typical Icc current is 1 mA at 5.0V (3.0 mA
at 3.3V).
A deep power-down mode of operation is invoked
when the RP# (called PWD# on the 2BFOOBSA) pin
transitions low. This mode brings the device power
consumption to less than 2.0 /LA, typically, and provides additional write protection by acting as a device reset pin during power transitions. A reset time
of 300!,)s (5.0V Vcc operation) is required from RP#
switching high until dropping RAS#. In the Deep
Power-Down, state, the WSM is reset (any current
operation will abort) and the CSR, GSR and BSR
registers are cleared.
A CMOS standby mode of operation is enabled
when RAS# and CAS# transition high and RP#
stays high with all input control pins at CMOS levels.
In this mode, the device typically draws an Icc
standby current of 70 /LA at 5V Vcc.
3-53
28F016XD
I
!
Y GalingtSensing
_GND
290533-1
Figure 1. 28F016XD Block Diagram
Architectural Evolution Includes Multiplexed Address Bus, SmartVoltage
Technology, Page Buffers, Queue Registers and i;:xtended Registers
3·54
28F016XD
The 28F016XD is available in a 56-Lead, 1.2mm
thick, 14mm x 20mm TSOP Type I package. This
form factor and pinout allow for very high board layout densities.
NC
GND
NC
A.
A.
A7
A.
As
Vee
RAS#
CAS#
NC
NC
GND
V pp
RP#
NC
NC
NC
NC
GND
NC
NC
A.
A3
A2
A,
A.
~
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2.0 DEVICE PINOUT
The 28F016XD 56-Lead TSOP Type I pinout configuration is shown in Figure 2.
0
WP#
WE#
OE#
RYIBY#
DO ,~
E28F016XD
56-LEAD TSOP PINOUT
14mmx20mm
TOP VIEW
D07
DO,.
DO •
GND
DO 13
DOs
DO '2
DO.
Vee
GND
DO"
D03
DO,.
D02
Vee
DO.
DO,
DO.
DO.
NC
Vee
NC
NC
290533-2
Figure 2. 28F016XD 56-Lead TSOP Type I Pinout Configuration
3-55
28F016XD
2.1 Lead Descriptions
Symbol
A(rAe
DQo-DQ15
Type
Name and Function.
INPUT
MULTIPLEXED ROW/COLUMN ADDRESSES: Selects a word within one
of thirty-two 32-Kword blocks. Row (upper) addresses are latched on the
falling edge of RAS #, while column (lower) addresses are latched on the
falling edge of CAS # .
INPUT/OUTPUT
DATA BUS: Inputs data and commands during CUI write cycles. Outputs
array, buffer, identifier or status data (DQO.7) in the appropriate read mode.
Floated when the chip is de-selected or the outputs are disabled.
RAS#
INPUT
ROW ADDRESS STROBE: Latches row address information on inputs
Ae.o when RAS# transitions low. A subsequent CAS # low transition.
initiates 28F016XD read or write operations.
CAS #
INPUT
COLUMN ADDRESS STROBE: Latches column address information on
inputs Ae-o when CAS # transitions low. When preceded by a RAS# low
transition, CAS# low initiates 28F016XD Read or Write operations, along
with OE # and WE #. Subsequent CAS # low transitions, with RAS# held
low, enable fast page mode reads/writes.
RP#
INPUT
RESET/POWER-DOWN: RP# low places the device in a Deep PowerDown state. All circuits that consume static power, even those circuits
enabled in standby mode, are turned off. When returning from Deep
Power-Down, recovery time of 300 ns at 5.0V Vee is required to allow
these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
Exit from Deep Power-Down places the device in read array mode.
a.
OE#
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when
low in combination with RAS# and CAS# low. The outputs float to tristate off when OE # is high. OE # can be tied to GND if not controlled by
the system memory controller. RAS# and CAS# high override OE# low.
WE # low also overrides OE # low.
WE#
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
RegisterS and Address Queue Latches. WE# is active low and initiates
writes in combination with RAS# and CAS# low. WE# low overrides
OE# low. RAS# and CAS# high override WE# low.
RY/BY#
WP#
3-56
OPEN DRAIN
OUTPUT
INPUT
READY/BUSY: Indicates status of the internal WSM. When low, it
indicates that the WSM is busy performing an operation. RY/BY # floating
indicates that the WSM is ready for new operations (or WSM has
completed all pending operations), or Erase is Suspended, or the device is
in deep power-down mode. This output is always active (i.e., not floated to
tri-state off when OE #, RAS # or CAS # are high), except if a RY/BY # Pin
Disable command is issued.
WRITE PROTECT: Erase blocks can be locked by writing a nonvolatile
lock-bit for each block. When WP# is low, those locked blocks as
reflected by the Block-Lock Status bits (BSR.6), are protected from
inadvertent Data Writes or Erases. When WP# is high, all blocks can be
written or erased regardless of the state of the lock-bits. The WP# input
buffer is disabled when RP# transitions low (deep power-down mode).
28F016XD
2.1 Lead Descriptions (Continued)
Symbol
Type
Name and Function
Vpp
SUPPLY
WRITE/ERASE POWER SUPPLY (12.0V ± O.6V,5.0V ± O.5V): For erasing memory
array blocks or writing words/pages into the flash array. Vpp = 5.0V ± O.5V
eliminates the need for a 12V converter, while connection to 12.0V ± O.6V maximizes
Write/Erase Performance.
,
NOTE:
Write and Erase attempts are inhibited with Vpp at or below 1.5V. Write and Erase
attempts with Vpp between 1.5V and 4.5V, between 5.5V and 11.4V, and above 12.6V
produce spurious results and should not be attempted.
Vee
SUPPLY
DEVICE POWER SUPPLY (3.3V ± O.3V, 5.0V ± O.5V): Internal detection configures
the device for 3.3V or 5.0V operation. To switch 3.3V to 5.0V (or vice versa), first ramp
Vee down to GND, and then power to the new Vee voltage.
Do not leave any power pins floating.
GND
SUPPLY
GROUND FOR ALL INTERNAL CIRCUITRY:
Do not leave any ground pins floating.
NC
NO CONNECT: No internal connection to die, lead may be driven or left floating.
3-57
28F016XD
3.0 MEMORY MAPS
A[19-0j
FFFFF
F8000
F7FFF
FOOOO
EFFFF
E8000
E7FFF
EOooo
OFFFF
08000
D7FFF
00000
CFFFF
C8000
C7FFF
cooao
BFFFF
B8000
87FFF
80000
ASFFF
ABOOD
A7FFF
AoaDO
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
1FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
80000
5FFFF
58000
57FFF
50000
4FFFF
48000
41FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
OFFFF
08000
07FFF
0000 0
32-Kword Block
31
32-Kword Block
30
32-Kword Block
29
32-Kword Block
28
32-Kword Block
27
32-Kword Block
26
32-Kword Block
25
32-Kword Block
24
32-Kword Block
23
32-Kword Block
22
32-Kword Block
21
32-Kword Block
20
32-Kword Block
19
32-Kword Block
18
32-Kword Block
17
32-Kword Block
16
32-Kword Block
15
32-Kword Block
14
32-Kword Block
13
32-Kword Block
12
32-Kword Block
11
32-Kword Block
10
32-Kword Block
9
32-Kword Block
8
32-Kword Block
7
32-Kword Block
6
32-Kword Block
5
32-Kword Block
4
32-Kword Block
3
32-Kword Block
2
32-Kword Block
1
32-Kword Block
0
290533-3
NOTE:
The upper 10 bits (AI9-10) reflect 28F016XD addresses A9_0,latched by RAS#.
The lower 10 bits (A9-0) reflect 28F016XD addresses A9-0, latched by CAS#.
Figure 3. 28F016XD Memory Map
3-58
28F016XD
3.1 Extended Status Registers Memory Map
FFFFFH
RESERVED
F8003H
RESERVED
GSR
F8002H
BSR31
F8001H
RESERVED
RESERVED
F8000H
r-------------------~
RESERVED
07FFFH
RESERVED
00003H
RESERVED
......................................................................................
GSR
RESERVED
00002H
BSRO
RESERVED
RESERVED
00001H
OOOOOH
290533-4
NOTE:
The upper 10 bi1s'(A19-10) reflect 28F016XD addresses A9_0.latched by RAS#.
The lower 10 bits (As-D) reflect 28F016XD addresses As-D. latched by CAS#.
Figure 4. Extended Status Register Memory Map
3-59
28F016XD
4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
4.1 Bus Operations
,
Notes
RP#
Row Address Latch
1,2,9
V,H
RAS#
J,
Column Address Latch
1,2,9
V,H
V,L
Mode
CAS#
OE#
V,H
X
J,
X
WE#
OQO-15
RV/BV#
X
X
X
X
·X
X
Read
1,2,7
V,H
V,L
V,L
V,L
V,H
DOUT
X
Output Disable
1,6,7
V,H
V,L
V,L
V,H
V,H
HighZ
X
Standby
1,6,7
V,H
V,H
V,H
X
X
HighZ
X
1,3
V,L
X
X
X
X
HighZ
VOH
VOH
Deep Power-Down
Manufacturer 10
4,8
V,H
V,L
V,L
V,L
V,H
0089H
Device 10
4,8
V,H
V,L
V,L
V,L
V,H
66A8H
VOH
V)L
X
V,L
D,N
X
Write
1,5,6
V,H
V,L
NOTES:
1. X can be VIH or VIL for address or control pins except for RY IBY #, which is either VOL or VOH, or High Z or DOUT for
data pins depending on whether or not OE # is active.
2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode,
RY/BY# will be at VOH if it is tied to Vee through a resistor. RY/BY# at VOH is independent of OE# while a WSM
operation is in progress.
3. RP# at GND ± O.2V ensures the lowest deep power-down current.
4. Ao (Iatc!led by CAS#) at VIL provides the Manufacturer ID code. Ao (latched by CAS#) at VIH provides the Device ID
code. All other addresses (row and column) should be set to zero.
5. Commands for Erase, Data Write, or Lock-Block operations can only be completed successfully when Vpp = VPPH1 or
Vpp = VPPH2.
6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes
to VOH when the WSM is not busy or in erase suspend mode.
7. RY/BY# maybe at VOL while the WSM is busy performing various operations. For example, a Status Register read
during a Write operation.
8. The 28F016XD shares an identical device identifier with other Intel Flash memories. Reading this identifier in conjunction
with the unique Device Proliferation Code (read from the Page Buffer after writing the Upload Device Configuration command) allows unique identification of the 2BF016XD by system software.
9. Row (upper) addresses are latched via inputs AO-9 on the falling edge of RAS #. Column (lower) addresses are latched
via inputs AO-9 on the falling edge of CAS # . Row addresses must be latched before column addresses are latched.
3-60
28F016XD
4.2 28F008SA-Compatible Mode Command Bus Definitions
Command
Notes
First Bus Cycle
Second Bus Cycle
Oper
Addr
Data
Oper
Addr
Data
Write
X
FFH
Read
AA
AD
1
Write
X
90H
Read
IA
ID
Read Compatible Status Register
2
Write
X
70H
Read
X
CSRD
Clear Status Register
3
Write
X
SOH
Word/Byte Write
Write
X
40H
Write
WA
WD
Alternate Word/Byte Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
BA
DOH
Erase Suspend/Resume
Write
X
BOH
Write
X
DOH
Read Array
Intelligent Identifier
ADDRESS
AA =. Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don't Care
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the Intelligent Identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase, or Suspend operations.
3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSRA and BSR.2 bits. See Status Register
definitions.
3-61
28F016XD
4.3 28F016XD-Performance Enhancement Command Bus Definitions
Command
Notes
First Bus Cycle
Second Bus Cycle
Oper
Addr
Data
Oper
Addr
Data
Read
RA
GSRD
BSRD
Read Extended
Status Register
1
Write
X
71H
Page Buffer Swap
6
72H
Write
X
Read Page Buffer
Write
X
75H
Read
PA
PD
Single Load to Page Buffer
Write
X
74H
Write
PA
PD
Third Bus Cycle
Oper
Addr
Data
Sequential Load to
Page Buffer
3,4,5,9
Write
X
EOH
Write
X
WCL
Write
X
WCH
Page Buffer Write
to Flash
3,4,9
Write
X
OCH
Write
X
WCL
Write
WA
WCH
Write
X
77H
Write
BA
DOH
Upload Status
Bits/Confirm
2
Write
X
97H
Write
X
DOH
Upload Device
Information/Confirm
10
Write
X
99H
Write
X
DOH
Write
X
A7H
Write
X
DOH
Lock Block/Confirm
Erase All Unlocked
Blocks/Confirm
RY /BY # Enable to
Level-Mode
7
Write
X
96H
Write
X
01H
RY/BY#
Pulse-an-Write
7
Write
X
96H
Write
X
02H
RY/BY#
Pulse-an-Erase
7
Write
X
96H
Write
X
03H
RY /BY # Disable
7
Write
X
96H
Write
X
04H
RY /BY # Pulse-OnWrite/Erase
7
Write
X
96H
Write
X
05H
Sleep
Write
X
FOH
Abort
Write
X
BOH
ADDRESS
DATA
BA = Block Address
PA = Page Buffer Address
RA = Extended Register Address
WA = Write Address
X = Don't Care
AD = Array Data
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
3-62
WC (L,H) ,; Word Count (Low, High)
WD (L,H) = Write Data (Low, High)
28F016XD
NOTES:
1. RA can be the GSR address or any BSR address. See Figure 4 for the Extended Status Register memory map.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3. WCH must be at OOH for this product because of the 128-word Page Buffer size, and to avoid writing the Page Buffer
contents to more than one 128-word segment within an array block. They are simply shown for future Page Buffer expandability.
4. Only'the lower byte 000-7 is used for WCL and WCH. The upper byte 008-15 is a don't care.
5. PA and PO (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.
6. This command allows the user to swap between available Page Buffers (0 or 1).
7. These commands reconfigure RY/BY# output to one of three pulse-modes or enable and disable the RY/BY# function.
8. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer.
Refer to the 16-Mbit Flash Product Family User's Manual.
9. WCL = OOH corresponds to a word count of 1.
10. After writing the Upload Device Information command and the Confirm command, the following information is output at
Page Buffer addresses specified below:
Row Address
OOH
OOH
OOH
Column Address
03H
OFH (000-7)
OFH (008-15)
Information
Device Revision Number
Device Configuration Code
Device Proliferation Code (04H)
A Page Buffer Swap followed by a Page Buffer Read sequence is necessary to access this information. The contents of all
other Page Buffer locations, after the Upload Device Information command is written, are reserved for future implementation
by Intel Corporation. See Section 4.7 for a description of the Device Configuration Code. This code also corresponds to data
written to the 28FO.16XD after writing the RY/BY# Configuration command.
3-63
28F016XD
4.4 Compatible Status Register
WSMS
I
7
1
ESS
1
6
ES
DWS
VPPS
R
5
4
3
2
CSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
R
I·
R
o
NOTES:
.
RY /BY" output or WSMS bit must be checked to determine
completion of an operation (Erase, Erase Suspend, or Data
Write) before the appropriate Status bit (ESS, ES or DWS) is
checked for success.
CSR.6 = ERASE-SUSPEND STATUS
1 = Erase Suspended
o = Erase In Progress/Completed
CSR.5 = ERASE STATUS
1 = Error In Block Erasure
o = Successful Block Erase
CSR.4 = DATA-WRITE STATUS
1 = Error in Data Write
o = Data Write Successful
If DWS and ES are set to "1" during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
CSR.3 = VppSTATUS
1 = Vpp Error Detect, Operation Abort
0= VppOK
.
The VPPS bit, unlike an A/D converter, does not provide
continuous indication of Vpp level. The WSM interrogates
Vpp's level only after the Data Write or Erase command
sequences have been entered, and informs the system if
Vpp has not been switched on. VPPS is not guaranteed to
report accurate feedback between VpPLK(max) and
VpPH1(min), between VpPH1(max) and VpPH2(min) and
above VpPH2(max).
CSR.2-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.
3-64
28F016XD
4.5 Global Status Register
I
WSMS
7
I
OSS
6
I
DOS
DSS
QS
PBAS
5
4
3
2
GSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
PBS
PBSS
o
[1] RY/BY# output or WSMS bit must be checked to
determine completion of an operation (Block Lock,
Suspend, any RY IBY # reconfiguration, Upload Status
Bits, Erase or Data Write) before the appropriate Status
bit (OSS or DOS) is checked for success.
GSR.6 = OPERATION SUSPEND STATUS
1 = Operation Suspended
o = Operation in Progress/Completed
GSA.5 = DEVICE OPERATION STATUS
1.= Operation Unsuccessful
o = Operation Successful or Currently Running
GSR.4 = DEVICE SLEEP STATUS
1 = Device in Sleep
o = Device Not in Sleep
MATRIX 5/4
o0 = Operation Successful or Currently
Running
o 1 = Device in Sleep mode or Pending
Sleep
1 0 = Operation Unsuccessful
1 1 = Operation Unsuccessful or
Aborted
If operation currently running, then GSA. 7 = O.
If device pending sleep, then GSR.7 =
o.
Operation aborted: Unsuccessful due to Abort
command.
GSR.3 = QUEUE STATUS
1 = Queue Full
o .= Queue Available
GSA.2 = PAGE BUFFER AVAILABLE STATUS
1 = One or Two Page Buffers Available
0= No Page Buffer Available
GSA.1 = PAGE BUFFER STATUS
1 = Selected Page Buffer Ready
o = Selected Page Buffer Busy
GSR.O = PAGE BUFFER SELECT STATUS
1 = Page Buffer 1 Selected
o = Page Buffer 0 Selected
The device contains two Page Buffers.
Selected Page Buffer is currently busy with WSM
operation
NOTE:
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.
3-65
28F016XD
4.6 Block Status Register
I
BS
7
I
BLS
I
6
BOS
BOAS
QS
VPPS
5
4
3
2
BSA.7 = BLOCK STATUS
1 = Ready
0.= Busy·
VPPL
R
o
NOTES:
[1] RY IBY # output or BS bit must be checked to
determine completion of an operation (Block Lock,
Suspend, Erase or Data Write) before the appropriate
Status bits (BOS, BLS) is checked for success.
BSA.6 = BLOCK LOCK STATUS
1 = Block Unlocked for Write/Erase
o = Block Locked for Write/Erase
BSR.5 = BLOCK OPERATION STATUS
1 = Operation Unsuccessful
o = Operation Successful or
Currently Running
BSR.4 = BLOCK OPERATION ABORT STATUS
1 = Operation Aborted
0= OPeration Not Aborted
MATRIX 5/4
o0 = Operation Successful or
Currently Running
o 1 = Not a Valid Combination
1 0 = Operation Unsuccessful
1 1 = Operation Aborted
The BOAS bit will not be set until BSA. 7 = 1.
Operation halted via Abort command.
BSA.3 =QUEUE STATUS
1 = Queue Full
o = Queue Available
BSA.2 = Vpp STATUS
1 = Vpp Error Detect, Operation Abort
0= VppOK
BSR.1 = Vpp LEVEL
1 = Vpp Detected at 5.0V ± 10%
o = Vpp Detected at 12.0V ± 5%
BSR.1 is not guaranteed to report accurate feedback
between the VPPH1 and VPPH2 voltage ranges. Writes
and erases with Vpp between VpPLK(max) and VPPH1
(min), between VpPH1(max) and VpPH2(min), and above
VpPH2(max) produce spurious results and should not be
attempted.
BSR.1 was a RESERVED bit on the 28F016SA.
BSR.O = RESERVED FOR FUTURE ENHANCEMENTS
This bit is reserved for future use; mask it out when polling the BSRs.
NOTE:
1. When multiple operations are queued, checking BSA.7 only provides indication of completion or that particular block.
GSR.7 provides indication when all queued operations are completed.
3-66
intel®
28F016XD
4.7 Device Configuration Code
I
R
7
I
R
6
I
R
5
I
R
R
RB2
4
3
2
RB1
RBO
0
NOTES:
DCC.2-DCC.0 = RY/BY# CONFIGURATION
Undocumented combinations of RB2-RBO are reserved
by Intel Corporation for future implementations and
(RB2-RBO)
should not be used.
001 = Level Mode (Default)
010 = Pulse-an-Write
011 = Pulse-an-Erase
100 = RY IBY # Disabled
101 = Pulse-On-Write/Erase
DCC.7-DCC.3 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when reading the Device Configuration Code. Set
these bits to "0" when writing the desired RY IBY # configuration to the device.
3-67
28F016XD
5.0 ELECTRICAL SPECIFICATIONS
5.1 Absolute Maximum Ratings*
Temperature Under Bias ............ O°C to + 80°C
Storage Temperature .......... -65°C to + 125°C
Vee
=
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may_ cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
3.3V ± O.3V Systems(S)
Symbol
Parameter
TA
Operating Temperature, Commercial
Vcc
Vcc with Respect to GND
Vpp
Vpp Supply Voltage with Respect to GND
V
Voltage on any Pin (except Vce, Vpp)
with Respect to GND
I
Current into any Non-Supply Pin
lOUT
Output Short Circuit Current
Notes
Min
Max
Units
Test Conditions
1
0
70
°C
Ambient Temperature
2
-0.2
7.0
V
2,3
-0.2
14.0
V
2
-0.5
Vec
+0.5
V
4
±30
mA
100
mA
Max
Units
Test Conditions
Ambient Temperature
Vee = S.OV ± O.SV Systems(S)
Symbol
Parameter
Notes
Min
TA
Operating Temperature, Commercial
1
0
70
°C
Vcc
Vee with Respect to GND
2
-0.2
7.0
V
Vpp
Vpp Supply Voltage with Respect to GND
2,3
-0.2
14.0
V
V
Voltage on any Pin (except Vcc, Vpp)
with Respect to GND
2
-2.0
7.0
V
I
Current into any Non-Supply Pin
±30
mA
lOUT
Output Short Circuit Current
100
mA
4
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee +
2.0V for periods <20 ns.
3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
3-68
28F016XD
5.2 Capacitance
For a 3.3V ± O.3V System:
Symbol
Notes
Typ
Max
Units
Test Conditions
CIN
Capacitance Looking into an
Address/Control Pin
Parameter·
1
6
8
pF
TA = 25°C, f = 1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
8
12
pF
TA = 25°C, f = 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
50
pF
1,2
For S.OV ± O.SV System:
Symbol
Typ
Max
Units
Test Conditions
CIN
Capacitance Looking into an
Address/Control Pin
6
8
pF
TA = 25°C, f = 1.0 MHz
COUT
Capacitance Looking into an
Output Pin
8
12
pF
TA = 25°C, f = 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
100
pF
Parameter
Notes
1,2
NOTE:
1. Sampled, not 100% tested.
2. Intel is currently developing more accurate models for the Transient Equivalent Testing Load Circuits. For more
iliformation or to obtain iBIS models, please contact your local Intel/Distribution Sales Office.
3-69
28F016XD
5.3 Transient Input/Output Reference Waveforms
2.4 _ _
IN_PU_T_...IX:::
0.45
>. T!T POINTS <::
5
2.0
OUTPUT
0.8
290533-5
AC test inputs are driven at VOH (2.4 VTTl) for a logic "1" and VOL (0.45 VTTl) for a logic "0." Input timing begins at
VIH (2.0 VTTl) and VIL (0.8 VTTl). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 5. Transient Input/Output Reference Waveform for Vee' = 5.0V
I_NP_U_T_JX'5+-T~T
::: __
POINTS--+
1.5
± O.5V(1)
OUTPUT
290533-6
AC test inputs are driven at 3.0V for a logic "1" and O.OV for a logic "0." Input timing begins, and output timing ends, at
1.5V. Input rise and fall times (10% to 90%) <10 ns.
Figure 6. Transient Input/Output Reference Waveform for Vee
NOTES:
1. Testing characteristics for 28F016XD·85.
2. Testing characteristics for 28F016XD-95.
3-70
=
3.3V
± O.3V(2)
28F016XD
5.4 DC Characteristics
= 3.3V ± 0.3V, T A = O·C to + 70·C
vee
Symbol
Parameter
lee1
Vee Word Read
Current
lee2
Vee Standby Current
lee3
lee4
Vee RAS#-Only
Refresh Current
Vee Fast Page Mode
Word Read Current
Notes Min Typ Max Unit
Test Condition
1,4,5
50
70
mA Vee = Vee Max
RAS#, CAS# = VIL
RAS#, CAS#, Addr. Cycling @
tRe = min
lOUT = OmA
Inputs = TTL or CMOS
1,5
1
4
mA Vee = Vee Max
RAS#, CAS#, RP#
WP# = VIL or VIH
1,5
1,4,5
50
40
70
60
=
VIH
mA Vee = Vee Max
CAS# = VIH
RAS# = VIL
RAS #, Addr. Cycling @tRe
Inputs = TTL or CMOS
mA Vee = Vee Max
RAS#, CAS# = VIL
CAS#, Addr. Cycling @tpe
lOUT = OmA
Inputs = VIL or VIH
=
=
min
min
lee5
Vee Standby Current
1,5
70
130
,...A Vee = Vee Max
RAS# CAS# RP# = Vee± 0.2V
WP# = Vee± 0.2V or GND ± 0.2V
lee6
Vee CAS#-8eforeRAS# Refresh Current
1,5
40
55
mA Vee = Vee Max
CAS#, RAS# = VIL
CAS#, RAS#, Addr. Cycling @tRe
1
Inputs = TTL or CMOS
55
mA Vee = Vee Max
RAS#, CAS# = VIL
lOUT = OmA
Inputs == VIL or VIH
1
± 1
,...A Vee = Vee Max
VIN = Vee or GND
Output Leakage
Current
1
± 10
,...A Vee = Vee Max
VOUT = Vee or GND
Vee Deep Power-Down
Current
1
lee7
Vee Standby Current
(Self Refresh Mode)
III
Input Load Current
ILO
leeD
1,5
40
2
5
,...A
RP#
=
=
min
GND ± 0.2V
3-71
28F016XD
5.4 DC Characteristics
Vee
=
3.3V ± 0.3V, TA
Symbol
lecw
ICCE
=
(Continued)
O·C to +70·C
Typ
Max
Unit
Test Condition
8
12
rnA
Word Write in Progress
Vpp = 12.0V ± 5%
8
17
rnA
Word Write in Progress
Vpp = 5.0V ± 10%
6
12
rnA
Block Erase in Progress
Vpp = 12.0V ± 5%
9
17
rnA
Block Erase in Progress
Vpp = 5.0V ± 10%
1,2
1
4
rnA
RAS#, CAS# = VIH
Block Erase Suspended
1
±1
±10
/LA
Vpp:;;; Vee
30
50
/LA
Vpp> Vcc
/LA
RP#
Parameter,
Notes
Vee Word Write Current
1,6
1,6
'Vee Block Erase
Current
ICCES
Vee Erase Suspend
Current
Ipps
Vpp Standby/Read
Current
Min
"
.'
= GND
IpPD
Vpp Deep Power-Down
Current
1
0.2
5
Ippw
Vpp Word Write Current
1,6
. 10
15
. rnA
Vpp = 12.0V ± 5%
Word Write in Progress
25
rnA
Vpp = 5.0V ± 10%
Word Write in Progress
4
10
rnA
Vpp = 12.0V ± 5%
Block Erase in Progress
14
20
rnA
Vpp = 5.0V ± 10%
Block Erase in Progress
30
50
p.A
Block Erase Suspended
15
IpPE
I
Vpp Block Erase
Current
1,6
I
IpPES
Vpp Erase Suspend
Current
1
VIL
Input Low Voltage
6
-0.3
0.8
V
VIH
Input High Voltage
6
2.0
Vcc
+ 0.3
V
3-72
± 0.2V
28F016XD
5.4 DC Characteristics
Vee = 3.3V
Symbol
±
(Continued)
0.3V, TA = O·C to +70·C
Parameter
Notes
Max
Unit
Test Condition
0.4
V
Vee = Vee Min
IOL = 4.0 rnA
2.4
V
IOH = -2.0 rnA'
Vee = Vee Min
6
Vee
-0.2
V
IOH = -100,...A
Vee = Vee Min
3,6
0.0
VOL
Output Low Voltage
6
VOH1
Output High Voltage
6
VOH2
Min
VPPLK
Vpp Erase/Write Lock
Voltage
VPPH 1
Vpp during Write/Erase
Operations
3
4.5
VPPH 2
Vpp during Write/Erase
Operations
3
11.4
VLKO
Vee Erase/Write Lock
Voltage
2.0
Typ
1.5
V
5.0
5.5
V
12.0
12.6
V
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 3.3V, VPP = 12.0V or 5.0V, T = 25·C. These
currents are valid for all product speed versions.
2. ICCES is specified with the device de-selected. If the device is read while in Erase Suspend mode, current draw is the sum
of ICCES and ICC1/IcC4'
3. Block erases. word writes and lock block operations are inhibited when VPP = VPPLK and not guaranteed in the ranges
between VpPLK(max) and VPPHl (min). between VPPHl (max) and VpPH2(min), and above VpPH2(max).
4. Automatic Power Saving (APS) reduces ICCl and 1CC4 to 3.0 mA typical in static operation.
5. CMOS inputs are either Vcc ± 0.2V or GND ± 0.2V. TIL inputs are either VIL or VIH.
6. Sampled, but not 100% tested. Guaranteed by design.
3-73
28F016XD
5.5 DC Characteristics
vee = 5.0V ± 0.5V, TA = O·C to
Symbol
Parameter
+ 70·C
Typ
Max
Unit
1,4,5
90
120
mA
Vee = Vee Max
RAS#, CAS# = VIL
RAS#, CAS#, Addr. Cycling @
tRe = min
lOUT = OmA
Inputs = TTL or CMOS
Notes Min
Test Condition
lee1
Vee Word Read Current
lee2
Vee Standby Current
1,5
2
4
mA
Vee = Vee Max
RAS#, CAS#, RP# = VIH
WP# = VILorVIH
lee3
Vee RAS#-Only
Refresh Current
1,5
90
120
mA
Vee = Vee Max
CAS# = VIH
RAS# = VIL
RAS#, Addr. Cycling @tRe = min
Inputs = TTL or CMOS
lee4
Vee Fast Page Mode
Word Read Current
1,4,5
80
110
mA
Vee = Vee Max
RAS#, CAS # = VIL
CAS#, Addr. Cycling @tpe = min
IOUT.= 0 mA
Inputs = VIL or VIH
lee5
Vee Standby Current
1,5
70
130
p.A
Vee = Vee Max
RAS#, CAS#, RP# = Vee ± 0.2V
WP# = Vee ± 0.2Vor
GND ± 0.2V
lee6
Vee CAS#-8eforeRAS # Refresh Current
1,5
50
65
rnA
Vee = Vee Max
CAS#, RAS# = VIL
CAS#, RAS#, Addr. Cycling
@tRe = min
Inputs = TTL or CMOS
leel
Vee Standby Current
(Self Refresh Mode)
1,5
50
65
mA
Vee = Vee Max
RAS#, CAS# = VIL
lOUT = OmA
Inputs = VIL or VIH
III
Input Load Current
1
±1
p.A
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage
Current
1
±10
p.A
Vee = Vee Max
VOUT = VeeorGND
ICCD
Vee Deep Power-Down
Current
1
2
5
p.A
RP# = GND ±0.2V
leew
Vee Word Write Current
1,6
25
35
mA
Word Write in Progress
Vpp = 12.0V ±5%
25
40
mA
Word Write in Progress
Vpp = 5.0V ±10%
3-74
28F016XD
5.5 DC Characteristics (Continued)
Vcc = 5.0V ± 0.5V, TA = O°C to + 70°C
Symbol
ICCE
Parameter
Vcc Block Erase
Current
Notes
Min
1,6
Typ
Max
Unit
Test Condition
18
25
rnA
Block Erase in Progress
Vpp = 12.0V ± 5%
20
30
rnA
Block Erase in Progress
Vpp = 5.0V ± 10%
ICCES
Vcc Erase Suspend
Current
1,2
2
4
rnA
RAS#, CAS# = VIH
Block Erase Suspended
IpPS
Vpp Standby/Read
Current
1
±1
±10
p.A
Vpp:S; Vec
30
50
p.A
Vpp> Vcc
IpPD
Vpp Deep Power-Down
Current
1
0.2
5
p.A
RP#
Ippw
Vpp Word Write Current
1,6
7
12
rnA
Vpp = 12.0V ± 5%
Word Write in Progress
17
22
rnA
Vpp = 5.0V ± 10%
Word Write in Progress
5
10
rnA
Vpp = 12.0V ± 5%
Block Erase in Progress
16
20
rnA - Vpp = 5.0V ± 10%
Block Erase in Progress
30
50
p.A
IpPE
Vpp Block Erase
Current
1,6
IpPES
Vpp Erase Suspend
Current
1
VIL
Input Low Voltage
6
-0.5
0.8
V
VIH
Input High Voltage
6
2.0
Vcc
+0.5
V
= GND ± 0.2V
Block Erase Suspended
3-75
28F016XD
5.5 DC Characteristics (Continued)
= 5.0V ± 0.5V, TA = O·C to + 70·C
Vee
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
0.45
V
Vee = Vee Min
IOL = 5.8 rnA
VOL
Output Low Voltage
6
VOH1
Output High Voltage
6
0.85
Vee
V
IOH = -2.5 rnA
Vee = Vee Min
6
Vee
-0.4
V
IOH = -100/LA
Vee = Vee Min
3,6
0.0
VOH2
VPPLK
Vpp Erase/Write Lock
Voltage
VPPH 1
Vpp during Write/Erase
Operations
3
4.5
VPPH 2
Vpp during Write/Erase
Operations
3
11.4
VLKO
Vee Erase/Write
Lock Voltage
2.0
1.5
V
5.0
5.5
V
12.0
12.6
V
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values atVcc = 5.0V, Vpp = 12.0V or 5.0V, T = 25'e. These
currents are valid for all product speed versions.
2. ICCES is specified with the device de-selected. If the device is read while in Erase Suspend mode, current draw is the sum
of ICCES and ICC1/1CC4'
3. Block erases, word writes and lock block operations are inhibited when VPP=VPPLK and not guaranteed in the ranges
between VpPLK(max) and VpPH1(min), between VpPH1(max) and VpPH2(min), and above VpPH2(max).
4. Automatic Power Saving (APS) reduces ICCl and ICC4 to 1 mA typical in static operation.
5. eMOS inputs are either VCC ± 0.2V or GND ± 0.2V. TTL inputs are either VIL or VIH.
6. Sampled, not 100% tested. Guaranteed by design.
3-76
28F016XD
5.6 AC Characteristics(11)
vcc = 3.3V ± 0.3V, T A = O°C to
+ 70°C
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
Versions
Symbol
28F016XD-95
Parameter
Notes
Min
Units
Max
tRP
RAS# Precharge Time
10
ns
tcp
CAS# Precharge Time
15
ns
tASR
Row Address Set-Up Time
9
0
ns
tRAH
Row Address Hold Time
9
15
ns
tASC
Column Address Set-Up Time
9
0
ns
tCAH
Column Address Hold Time
9
20
ns
tAR
Column Address Hold Time Referenced to RAS#
3,9
35
tRAO
RAS # to Column Address Delay Time
8,9
15
tCRP
CAS# to RAS# Precharge Time
10
ns
tOED
OE # to Data Delay
10
30
ns
tozo
OE # Delay Time from Data In
10
0
ns
tozc
CAS# Delay Time from Data In
10
0
ns
tT
Transition Time (Rise and Fall)
10
2
ns
15
4
ns
ns
Read Cycle
Versions
Symbol
Parameter
28F016XD-95
Notes
Min
Units
Max
tRC(R)
Random Read Cycle Time
105
tRAS(R)
RAS# Pulse Width (Reads)
95
00
ns
tCAS(R)
CAS# Pulse Width (Reads)
40
00
ns
tRCO(R)
RAS# to CAS # Delay Time (Reads)
15
55
ns
1
ns
tRSH(R)
RAS# Hold Time (Reads)
30
ns
tCSH(R)
CAS# Hold Time (Reads)
95
ns
tRAC
Access Time from RAS #
1,8
95
ns
tCAC
Access Time from CAS #
1,2
40
ns
8
75
ns
40
ns
tM
Access Time from Column Address
tOEA
OE# Access Time
3-77
28F016XD
Read Cycle (Continued)
Versions
Symbol
Parameter
28F016XD·95
Notes
tROH
RAS# Hold Time Referenced to OE#
tRCS
Read Command Set-Up Time
tRCH
Read Command Hold Time Referenced to CAS#
6,10
Min
Units
Max
40
ns
5
ns
0
ns
6,10
tRRH
Read Command Hold Time Referenced to RAS#
0
ns
tRAl
Column Address to RAS# Lead Time
9
15
ns
tCAl
Column Address to CAS# Lead Time
9
75
ns
tCLl
CAS# to Output in Low-Z
0
ns
tOH
Output Data Hold Time
0
ns
tOHO
Output Data Hold Time from OE#
0
ns
tOFF
Output Buffer Turn-Off Delay
tOEZ
Output Buffer Turn Off Delay Time From OE #
tcoo
CAS# to Data in Delay Time
4
30
ns
30
ns
30
ns
Write Cycle
Versions
Symbol
Parameter
28F016XD·95
Notes
Min
Units
Max
tRC(W)
Random Write Cycle Time
90
tRAS(W)
RAS# Pulse Width (Writes)
80
co
ns
tCAS(W)
CAS# Pulse Width (Writes)
65
co
ns
tRCO(W)
RAS # to CAS # Delay Time (Writes)
15
15
ns
tRSH(W)
RAS# Hold Time (Writes)
tCSH(W)
CAS # Hold Time (Writes)
twcs
Write Command Set-Up Time
tWCH
Write Command Hold Time
tWCR
Write Command Hold Time Referenced to RAS#
twp
1
ns
65
ns
80
ns
5
0
ns
15
ns
3
30
ns
Write Command Pulse Width
15
ns
tRWl
Write Command to RAS # Lead Time
65
ns
tcWl
Write Command to CAS # Lead Time
65
ns
tos
Data-In Set-Up Time
0
ns
tOH
Data-In Hold Time
7,9
15
ns
tOHR
Data-In Hold Time Referenced to RAS#
3,9
30
ns
3-78
7,9
28F016XD
Read-Modify-Write Cycle
Versions
Symbol
Parameter
tRWC
Read-Modify-Write Cycle Time
tRWD
RAS # to WE # Delay Time
tCWD
CAS # to WE # Delay Time
tAWD
Column Address to WE # Delay Time
tOEH
DE # Command Hold Time
28F016XD-95
Units
Max
Notes
Min
10
200
ns
5,10
125
ns
5,10
70
ns
5,9,10
105
ns
10
15
ns
Fast Page Mode Cycle
28F016XD-95
Versions
Symbol
Parameter
Notes
Min
tpC(R)
Fast Page Mode Cycle Time (Reads)
75
tpC(W)
Fast Page Mode Cycle Time (Writes)
80
tRASP(R)
RAS# Pulse Width (Reads)
tRASP(W)
RAS# Pulse Width (Writes)
tePA
Access Time from CAS# Precharge
tcpw
WE# Delay Time from CAS# Precharge
tCPRH(R)
tePRH(W)
Units
Max
ns
ns
95
00
ns
80
00
ns
85
ns
0
ns
RAS# Hold Time from CAS# Precharge (Reads)
75
ns
RAS# Hold Time from CAS# Precharge (Writes)
80
ns
10
Fast Page Mode Read-Modify-Write Cycle
Versions
Symbol
tPRWC
Parameter
I
I Notes
Fast
Page
Mode
Read-Modify-Write
Cycle
Time
I 10
I
28F016XD-95
Min
170
I
I
Units
Max
ns
3-79
28F016XD
Refresh Cycle
28F016XD-95
Versions
Symbol
Units
Parameter
Notes
Min
CAS# Set-Up Time (CAS#-Before-RAS# Rlilfresh)
10
10
ns
tcHR
CAS# Hold Time (CAS#-Before-RAS# Refresh)
10
10
ns
tWRP
WE# Set-Up Time (CAS#-Before-RAS# Refresh)
10
10
ns
tWRH
WE# Hold Time (CAS#-Before-RAS# Refresh)
10
10
ns
tRPC
RAS# Precharge to CAS # Hold Time
10
10
ns
tRASS
RAS# Pulse Width (Self-Refresh Mode)
10
0
ns
tRPS
RAS# Precharge Time (Self-Refresh Mode)
10
10
ns
tCPN
CAS# Precharge Time (Self-Refresh Mode)
10
10
ns
tcHS
CAS# Hold Time (Self-Refresh Mode)
10
0
ns
tcSR
Max
Refresh
28F016XD-95
Versions
Symbol
tREF
3-80
I
I
Parameter
Refresh Period
I
I
Notes
10
Min
I
I
Units
Max
00
ms
28F016XD
Miscellaneous Specifications
28F016XD-95
Versions
Units
Notes
Min
RP# High to RAS# Going Low
10
480
ns
RP# Set-Up to WEll' Going Low
10
480
ns
100
Parameter
Max
Vpp Set-Up to CAS # High at End of Write Cycle
10
WE # High to RY IBY # Going Low
10
RP # Hold from Valid Status Register Data and RYIBY # high
10
0
ns
Vpp Hold from Valid Status Register Data and RYIBY # high
10
0
ns
ns
100
ns
NOTES:
1.
2.
3.
4.
5.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point.
Assumes that tRCD z tRCD(max).
tAR. tWCR. tDHR are referenced to tRAD(max)·
toFF(max) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL.
twcs. tRWD. lewD and tAWD are non restrictive operating parameters. They are included in the datasheet as electrical
characteristics only. If twcs z tWCS(min) the cycle is an early write cycle and the data output will remain high impedance
for the duration of the cycle. If lewD z leWD(min). tRWD z tRWD(min). tAWD z tAWD(min). then the cycle is a read-write
cycle and the data output will contain the data read from the selected address. If neither of the above conditions are
satisfied. the condition of the data out is indeterminate.
6. Either tRCH or tRRH must be satisfied for a read cycle.
7. These parameters are referenced to the CAS# leading edge in early write cycles and to the WEll' leading edge in readwrite cycles.
8. Operation within the tRAD(max) limit ensures that tRAC(max) can be met. tRAD(maxl is specified as a reference point only. If
tRAD is greate! than the specified tRAD(max) limit. then the access time is control ed by tM.
9. Refer to command definition tables for valid address and data values.
10. Sampled. but not 100% tested. Guaranteed by design.
11. See AC Input/Output Reference Waveforms for timing measurements.
3-81
28F016XD
5.7 AC Characteristics(11)
vee =
5.0V ± 0.5V, TA = O·C to
+ 70·C
Read, Write, Read·ModlfY-Wrlte and Refresh Cycles (Common Parameters)
28F016XD-85
Versions
Symbol
Parameter
Notes
Min
tRP
RAS# Precharge Time
10
tcp
CAS # Precharge Time
15
Units
Max
ns
ns
. ns
tASR
Row Address Set-Up Time
9
0
tRAH
Row Address Hold Time
9
15
ns
tASC
Column Address Set-Up Time
9
0
ns
tcAH
Column Address Hold Time
9
20
ns
35
15
tAR
Column Address Hold Time Referenced to RAS#
3,9
tRAO
RAS# to Column Address Delay Time
8,9
tcRP
CAS# to RAS# Precharge Time
toED
OE #to Data Delay
,tozo
OE # Delay Time from Data In
tozc
CAS# Delay Time from Data In
tr
Transition Time (Rise and Fall)
10
.2
3-82
ns
15
ns
10
ns
30
ns.
10
0
ns
10
0
10
ns
4
ns
28F016XD
Read Cycle
Versions
Symbol
Parameter
28F016XD-85
Notes
Min
tRC(R)
Random Read Cycle Time
95
tRAS(R)
RAS# Pulse Width (Reads)
tCAS(R)
CAS# Pulse Width (Reads)
tRCD(R)
RAS# to CAS # Delay Time (Reads)
tRSH(R)
RAS# Hold Time (Reads)
tcsH(R)
CAS# Hold Time (Reads)
tRAC
Access Time from RAS#
1,8
1
Units
Max
ns
85
00
ns
35
00
ns
15
50
ns
30
ns
85
ns
85
ns
1,2
35
ns
8
65
ns
35
ns
tCAC
Access Time from CAS#
tM
Access Time from Column Address
toEA
OE # Access Time
tROH
RAS# Hold Time Referenced to OE#
tRCS
Read Command Set-Up Time
tRCH
Read Command Hold Time Referenced to CAS #
6,10
35
ns
5
ns
0
ns
6,10
0
ns
9
15
ns
tRRH
Read Command Hold Time Referenced to RAS#
tRAl
Column Address to RAS# Lead Time
teAL
Column Address to CAS # Lead Time
9
65
ns
tell
CAS# to Output in Low-Z
10
0
ns
toH
Output Data Hold Time
10
0
ns
toHO
Output Data Hold Time from OE #
10
0
toFF
Output Buffer Turn-Off Delay
4,10
toEZ
Output Buffer Turn-Off Delay Time from OE #
10
teDD
CAS # to Data in Delay Time
10
30
ns
30
ns
30
ns
ns
3-83
28F016XD
Write Cycle
28F016XD-85
Versions
Symbol
Parameter
Min
Notes
Units
Max
tRC(W)
Random Write Cycle Time
75
tRAS(W)
RAS# Pulse Width (Writes)
65
00
ns
tCAS(W)
CAS# Pulse Width (Writes)
50
00
ns
tRCO(W)
RAS# to CAS# Delay Time (Writes)
15
15
ns
1
hs
tRSH(W)
RAS# Hold Time (Writes)
50
ns
tCSH(W)
CAS# Hold Time (Writes)
65
ns
twcs
Write Command Set-Up Time
tWCH
Write Command Hold Time
5
3
0
ns
15
ns
tWCR
Write Command Hold Time Referenced to RAS#
30
ns
twp
Write Command Pulse Width
15
ns
tRWL
Write Command to RAS# Lead Time
50
ns
tCWL
Write Command to CAS # Lead Time
50
ns
tos
Data-In Set-Up Time
7,9
0
ns
tOH
Data-In Hold Time
7,9
15
ns
tOHR
Data-In Hold Time Referenced to RAS#
3,9
30
ns
Read-Modify-Write Cycle
28F016XD-85
Versions
Symbol
Parameter
tRWC
Read-Modify-Write Cycle Time
tRWO
RAS # to WE # Delay Time
tcwo
CAS # to WE # Delay Time
tAWO
Column Address to WE # Delay Time
tOEH
OE # Command Hold Time
Units
Max
Notes
Min
10
175
ns
5,10
115
ns
5,10
65
ns
5,9,10
100
ns
10
15
ns
Notes
Min
Fast Page Mode Cycle
28F016XD-85
Versions
Symbol
Parameter
Units
Max
tpC(R)
Fast Page Mode Cycle Time (Reads)
65
ns
tpc(W)
Fast Page Mode Cycle Time (Writes)
65
ns
3-84
28F016XD
Fast Page Mode Cycle (Continued)
28F016XD-85
Versions
Symbol
Parameter
Notes
Min
Max
Units
tRASP(R)
RAS# Pulse Width (Reads)
85
00
ns
tRASP(W)
RAS# Pulse Width (Writes)
65
00
ns
70
ns
tCPA
Access Time from CAS# Precharge
tcpw
WE # Delay Time from CAS # Precharge
tCPRH(R)
tCPRH(W)
10
0
ns
RAS# Hold Time from CAS# Precharge (Reads)
65
ns
RAS# Hold Time from CAS# Precharge (Writes)
65
ns
Fast Page Mode Read-Modify-Write Cycle
28F016XD-85
Versions
. Symbol
tPRWC
I
I
Parameter
Fast Page Mode Read-Modify-Write Cycle Time
I Notes
I 10
I
I
Min
145
Units
Max
ns
Refresh Cycle
28F016XD·85
Versions
Units
Parameter
Notes
Min
tCSR
CAS# Set-Up Time (CAS#-Before-RAS# refresh)
10
10
ns
tCHR
CAS# Hold Time (CAS#-Before-RAS# Refresh)
10
10
ns
tWRP
WE# Set-Up Time (CAS#-Before-RAS# Refresh)
10
10
ns
tWRH
WE# Hold Time (CAS#-Before-RAS# Refresh)
10
10
ns
tRPC
RAS # Precharge to CAS # Hold Time
10
10
ns
tRASS
RAS# Pulse Width (Self-Refresh Mode)
10
0
ns
tRPS
RAS# Precharge Time (Self-Refresh Mode)
10
10
ns
tCPN
CAS# Precharge Time (Self-Refresh Mode)
10
10
ns
tCHS
CAS# Hold Time (Self-Refresh Mode)
10
0
ns
Symbol
Max
Refresh
28F016XD-85
Versions
Symbol
tREF
I
I
Parameter
Refresh Period
I
J
Notes
10
Min
I
I
Units
Max
00
ms
3-85
28F016XD
Misc. Specifications
28F016XD·85
Versions
Parameter
Max
Units
Notes
Min
RP# High to RAS# GOing Low
10
300
ns
RP# Set-Up to WE# Going Low
10
300
ns
100
Vpp Set-Up to CAS# High at End of Write Cycle
10
WE # High to RYIBY # Going Low
10
RP # Hold from Valid Status Register Data and RYIBY # High
10
0
ns
Vpp Hold from Valid Status Register Data and RYIBY # High
10
0
ns
ns
100
ns
NOTES:
1. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point.
2. Assumes that tRCD :2: tRCD(max)'
3. tAR, tWCR, tDHR are referenced to tRAD(max)'
4. toFF(max) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL.
5. twcs, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the datasheet as electrical
characteristics only. If twcs :2: tWCS(min) the cycle is an early write cycle and the data output will remain high impedance
for the duration of the cycle. If tCWD :2: tCWD(min), tRWD :2: tRWD(min), tAWD :2: tAWD(min), then the cycle is a read-write
cycle and the data output will contain the data read from the selected address. If neither of the above conditions are
satisfied, the condition of the data out is indeterminate.
6. Either tRCH or tRRH must be satisfied for a read cycle.
7. These parameters are referenced to the CAS# leading edge'in early write cycles and to the WE# leading edge in readwrite cycles.
S. Operation within the tRAD(max) limit ensures that tRAC(max) can be met, tRAD(max) is specified as a reference point only. If
tRAD is greater than the specified tRAD(max) limit, then the access time is controlled by tAA.
9. Refer to command definition tables for valid address and data values.
10. Sampled, but not 100% tested. Guaranteed by design.
11. See AC Input/Output Reference Waveforms for timing measurements.
3-86
28F016XD
5.8 ;AC Waveforms
~
4
I RAS
I RP
RAS#
1\
II
IT . . .
-
\
I CRP
ICSH
t RSH
RCD
I CAS
-4-:
CAS#
I
IRAO
I ASR
Address
•
~
Row
IRAL
-~
lRAH
IASC
I. . . .
.
CAL
ICAH
~
Column
-
IRRH
IRCS
WE#
I RCH
I DZC
ICDD
OPEN
Din
I DZO
IOED
IOEA
~
OE#
\\
I.
/I
\\
1M
tCAC
:)
~ 4-~F~HO
IRAC
Doul
~
~
4 - I OEZ
..
4-IoH
Doul
~ :Don~Care
290533-7
Figure 7. AC Waveforms for Read Operations
3-87
28F016XD
tRAS
4
RAs#
•
t RP
,\
t CRP
tCSH
t RSH
t RCD
tr..,
tCAS
~
CAS#
.......
t ASR
Address
WEI
•
Row
tRAH
. t ASC
~
tCAH
'-'
~
Column
t WCH
t,f'lCS
~
\Vo.
-
t DS
Din
tDH
Din
OPEN
Dout--------------------------------------------------------
OE# : Don't Care
~
: Don't Care
twcs ~ twcs (min)
290533-8
Figure 8. AC Waveforms for Early Write Operations
3-88
28F016XD
..
~
t RAS
t RP
RAS#
\
.
tCSH
t RCO
t T ...
CAS#
......
t ASR
Address
•
Row
t RSH
1\
tCAS_
~
tRAH
-
tASC
~
~
tCAH
Column
-
t RCS
t CWl -
...... tos
tozc
I......
\'
tozo
--rWI.
--
...
tOH
~.
OPEN
Oin
t RWl
twp
WE#
OE#
t CRP
V
tOEO
r--
Oin
.
\\
tOEH
~
/ tOEZ
1.\
r---
tClZ
Oout
Invalid'
~
~
~
: Oon't Care
290533-9
Figure 9. AC Waveforms for Delayed Write Operations
3-89
28F016XD
.
RWC
I RP
I RAS
..
RAS#
\
IT
CAS#
...
I RCD
..
I CAS
4
V
04-
1\
I CRP
II
IRAD
I ASR
...
IRA-l
..
•
~
... ..
IA~C
Row
Address
..
ICAH
Column
--
I CWO
IAWD
I RWD
IRC
~
~
ICW
~I RWL
IWp
'I
WE#
..:.~
IDS
~
OP N
Din
IDZO
IOEC
loi:'
1-
/IN
4-
ICAC
IAf:oi=+
1m
..
Din
V-
4-
OE#
r:-
-- -IOEH
10EZ
~
I RAC
~.
Dou t
ICLZ
r
,---.,
Dout
~
: Don'ICare
290533-10
Figure 10. AC Waveforms for Read-Modify-Wrlte Operations
3-90
28F016XD
I RASP
RAS#
IRP
ICPRH
-
II
... --..
L
IT
ICSH
IRSr
.....
I..
IpC
•
~ ~~ I~
IRCD
i'ICAS
1,------,
I~
ICRP
~
~
CAS#
~
'------'
..... .... ....
-)
~
lRAD
IASR
lRAH
IAL
IASC
ICAH
Address
Row
Din
Calumn1
OPEN
M~
I
I A
IASC
14-+
C L
I.....
~
Calumn2
~
~S(
ICAH
ICA
~
~ ~ alumn N
ICDC
--I
OPEN
OPEN
OE#
Doul
~
: Don'l Care
290533-11
Figure 11. AC Waveforms for Fast Page Mode Read Operations
3-91
intel®
28F016XD
..
.. .. ..
t RASP
t RP
RAS#
t RSH
t RP
CAS#
Address
WE#
Din
OPEN
Dout
OE#
: Don't Care
~
: Don't Care
t WCS >= t WCS (min)
290533-12
Figure 12. AC Waveforms for Fast Page Mode Early Write Operations
3-92
28F016XD
!RASP
RAS#
o
CAS#
Address
Dout----------------~_i--------~--~------~--+_----------
~
: Don't Care
Invalid Dou!
Invalid Dou!
Invalid Dou!
290533-13
Figure 13. AC Waveforms for Fast Page Mode Delayed Write Operations
3-93
28F016XD
'RASP
1\
RAS#
'CRP
-CAS#
'CP
I-
-- Ih
1\
'ASC,
'CAH
~~.mI
Address
Column 2 I.QQOQ
,
,~
~f"
'~
iCWD
WE#
Din
OE#
\'
Dout
290533-14
Figure 14. AC Waveforms for Fast Page Mode Read-Modify-Write Operations
3·94
28F016XD
•
RC
~
t RAS
..
t RP
RAS#
\
1\
t T...,
CAS#
~
~
Address
t CRP
'~
t ASR
.-... •
\\,{X¥Y'
t RPC
tRAH
~
~
ROW
\\
tOFF
Dout
~_________________________________O_P_E_N_________________
OE#,WE# : Don't Care
~
: Don't Care
290533-15
Figure 15. AC Waveforms for RAS#-Only Refresh Operations
3-95
28F016XD
....
RAS#
'RP
~
....
'RPC
'r....
~
'CSR
-;,;
'RAS
-I~
......
,
WRP
'RP
~
1\
II
f\-
~
~
'RPC
~
....
'CHR
....
'CSR
~
~
/
\
..
....
t RP
'RAS
~
C---..J
'CP
'!II
~
1\
~
CAS#
.
..
'WRH
~
'CRP
-
'CHR
,I
\
'WRP
':"
I"'~
WE# /.
Address
\\
\'
'I
/.
'OFF
........
Dout
OPEN
OE#: Don', Care
~ : Don" Care
290533-16
Figure 16. AC Waveforms for CAS #-before-RAS # Refresh Operations
3-96
28F016XD
RAS#
I RP
I RAS
-
V
'\
~
IT
I RAS
F
I RSH
I RCD
I RAS
,~
ICHR
~
I RP
I CRP
~
CAS#
IRAD
... . ...
RAL
lAS
~
Address
.... I.~~
»,,~ ;~~
lAS
ICAH
F
Column
I-'
IRRH
IFPS
IRCH
~
II ZC
ICDD
WE#
Din
t DZO
~
I OED
IOEA
I-t
~
j4-
I
OE#
I~C
~
I~
OFF
AA
"'RA
Dou t
•
-- W7
f4 f--
~~
=w
IOEZ
IOHO
IOH
Doul
I)-:--
~
:Don'Care
290533-17
Figure 17. AC Waveforms for Hidden Refresh Operations
3-97
28F016XD
tRASS
RAS#
-.I --
t CPN
55
tCSR
~
~
\
/
CAS#
I
t RPC ..
-
'"
55
..... /
t CHS
tOFF
\'
IJ
HI-Z
55
290533-18
Figure 18. AC Waveforms for Self·Refresh Operations
3-98
28F016XD
5.9 Power-Up and Reset Timings
Vee POWER-UP
,
RP#
(P)
"
Vee
(3V,SV)
1
~!
ov
~l
.~~~1i----
,13,3V
_-+_______
l+----.1
!t
!
!
',i
3VPH
! !
!,
~
.
t
PLSV
r
!,
t SVPH
1"
,
~i
~
290533-19
Figure 19. Vee Power·Up and RP# Reset Waveforms
Parameter
Notes
Min
RP# Low to Vee at 4,5V (Minimum)
2
0
J.ts
tpLSV
RP# Low to Vee at 3.0V (Minimum)
2
0
J.ts
t5VPH
Vee at 4.5V Minimum) to RP# High
1
2
J.ts
tsvPH
Vee at 3.0V (Minimum) to RP# High
1
2
J.ts
Symbol
tpL5V
Max
Unit
NOTES:
For Read Timings following Reset, see sections 5.6 and 5.7.
1. The t5VPH and/or t3VPH times must be strictly followed to guarantee all other read and write specifications for the
2BF016XD.
'2. The power supply may start to switch concurrently with RP# going low.
3-99
28F016XD
5.10 Erase and Word Write Performance(3,5)
± 0.5V, Vpp = 5.0V ± 0.5V, TA = O·C to + 70·C
vee = 5.0V
Symbol
Parameter
Notes
Min
Typ(1)
Max
Units
Page Buffer Word Write Time
2
TBD
12.1
TBD
p.s
tWHRH1
Word Write Time
2
TBD
16
TBD
p.s
tWHRH 3
Block Write Time
2
TBD
0.6
TBD
sec
Block Erase Time
2
TBD
1.0
TBD
sec
Full Chip Erase Time'
2
TBD'
32.0
TBD
sec
Time From Erase Suspend
Command to WSM Ready
4
TBD
10
TBD
p.s
Vcc
=
5.0V ± 0.5V, Vpp
=
12.0V ± 0.6V, TA
= O·C to
+70·C
Parameter
Notes
Min
Typ(1)
Max
Units
Page Buffer Word Write Time
2
TBD
4.1
TBD
p.s
tWHRH1
Word Write Time
2
4.5
6
TBD
p.s
tWHRH 3
Block Write Time
2
TBD
0.2
1.0
sec
Block Erase Time
2
0.3
0.6
10
' sec
Full Chip Erase Time
2
TBD
19.2
TBD
sec
Time From Erase Suspend
Command to WSM Ready
4
TBD
10
TBD
p.s
Symbbl
NOTES:
1. 25°C, and nominal voltages.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Specification applies to interrupt latency for Single Block Erase. Suspend latency for Erase All Unlocked Block operation
extends the latency time to 140 /Ls (typical).
5. Sampled, but not 100% tested. Guaranteed by design.
3-100
28F016XD
6.0 MECHANICAL SPECIFICATIONS
0-1
E
~OU
I+---
il:-
~1-----+1.1 J
A L - , - -_ _ _ _ _ _ _
A1
m~
-.~SEE DETAIL A
r--~------------~~
DETAIL A
DETAIL B
®
JI_b
290533-20
Figure 20. Mechanical Specifications of the 28F016XD 56·Lead TSOP Type I Package
Family: Thin Small Outline Package
Millimeters
Symbol
Minimum
Nominal
Notes
Maximum
1.20
A
A1
0.50
A2
0.965
0.995
1.025
b
0.100
0.150
0.200
c
0.115
0.125
0.135
01
18:20
18.40
18.60
E
13.80
14.00
14.20
e
0.50
0
19.80
20.00
20.20
L
0.500
0.600
0.700
00
56
30
50
0.150
0.250
N
0
Y
Z
0.100
0.350
3-101
28F016XD
DEVICE NOMENCLATURE AND ORDERING INFORMATION
Product line.. designator for all Intel Flash products
,-L-,
IEI21slFlol1161xlij -Isisl
y
L.,-J
Package
E = TSOP
Random Access Time
(tRAC) at 5V Vcc(ns)
Device Type
D = Main Memory
(DRAM-like) Interface
290533-21
Valid Combinations
Order Code
E28F016XD 85
Vee
=
3.3V ± 0.3V, 50 pF load,
1.5V I/O Levels(1)
E28F016XD-95
NOTE:
1. See Section 5.2 for Transient Input/Output Reference Waveforms.
3-102
Vee
=
5.0V ± 10%, 100 pF IQad,
TTL I/O Levels(1)
E28F016XD-85
28F016XD
ADDITIONAL INFORMATION
Order Number
Document/Tool
297372
16-Mbit Flash Product Family User's Manual,
2BF016SA/2BF016SV/2BF016XS/2BF016XD
292152
AB-5B, "28F016XD-Based SIMM Designs"
292092
AP-357, "Power Supply Solutions for Flash Memory"
292123
AP-374, "Flash Memory Write Protection Techniques"
292126
AP-377, "16-Mbit Flash Product Family Software Orivers,
28F016SAl28F016SV /28F016XS/28F016XO"
292131
AP-384, "Designing with the 28F016XO"
297508
FlashBuilder Utility
Contact Intel/Oistribution
Sales Office
28F016XO Benchmarking Utility
Contact Intel/Oistribution
Sales Office
28F016XO iBIS Models
Contact Intel/Distribution
Sales Office
28F016XO VHOLlVeriiog Models
Contact Intel/Oistribution
Sales Office
2BF016XO Timing DeSigner Library Files
Contact Intel/Distribution
Sales Office
28F016XO Orcad and ViewLogic Schematic Symbols
DATASHEET .REVISION HISTORY
Description
Original Version
3-103
infel·
AB-58
APPLICATION
BRIEF
28F016XD-Based'SIMM
Designs
BRIAN DIPERT
SENIOR TECHNICAL
MARKETING ENGINEER
SUJAN KAMRAN
TECHNICAL MARKETING
ENGINEER
November 1994
Order Number: 292152·001
3·104
AB-58
The example design explained in detail in this application brief (Section 2), uses the JEDEC 72-lead DRAM
SIMM standard and supports densities of I-Mbyte x 32
and 2-Mbyte x 32. Section 3 discusses ideas for extrapolating this design to other JEDEC DRAM SIMM
pinouts, while Section 4 provides software guidelines
corresponding to flash memory-based SIMM hardware
designs. See Section 6 for additional information on
Intel's flash memory products.
1.0 INTRODUCTION
This application brief provides design information for
SIMM (Single In-Line Memory Module) configurations based on the 28F016XD flash memory. The
28F016XD is an Intel 16 Mbit Flash memory component with a multiplexed address bus hardware interface,compatible with system DRAM controllers. As
such, it is an ideal high-density flash memory for use in
existing designs with DRAM SIMM connectors, or in
new designs where flexibility in system memory configuration is needed. The 28F016XD preserves all traditional FlashFile™ memory attributes, including perbit programmability and per-block eraseability. Its low
power consumption, full nonvolatility (i.e., no refresh
required) and in-system updateability are desirable attributes in comparison to the DRAM memory alternative. The 28F016XD supports both standard and fast
page mode reads/writes and all refresh cycles (which it
internally disregards).
o
28F016XD
(For 2M SIMM
EJ
28F016XD
2.0 72-LEAD SIMM DESIGN EXAMPLE
Figure 1 shows a full-size layout for the 72-lead SIMM
explained in this section, while Tables 1 and 2 show and
describe the SIMM pinout. Figure 2 shows the SIMM
component interconnect.
L=:J
MAX70Sc=l
D
28F016XD
(For 2M SIMM)
0
292152-1
NOTE:
Filter and~bypass capacitors not shown.
Figure 1. Flash Memory-Based 72-Lead SIMM (1M x 32 or 2M x 32) with
Identical Dimensions and Pinout as the DRAM-Based Alternative
3-105
AS-58
Table 1. 72-Lead SIMM Pinout
GND
13
Al
25
D022
37
NC
49
D08
61
D013
2
DOo
14
A2
26
D07
38
NC
50
D024
62
D030
3
D016
15
As
27
D023
39
GND
51
D09
63
D014
4
DOl
16
~
28
A7
40
CASo*
52
D025
64
D031
5
D017
17
A5
29
NC
41
CAS2*
53
DOlO
65
D015
6
D02
18
As
30
Vee
42
CAS1*
54
D026
66
NC
7
D018
19
NC
31
A8
43
CAS3*
55
DOll
67
PDl
8
D03
20
D04
32
A9
44
RASo*
56
D027
68
PD2
1
9
D019
21
D020
33(1)
10
Vet
22
D05
34
11
NC
23
D021
12
Ao
24
D06
NOTES:
45(1)
NC/RAS1*
57
D012
69
PD3
RAS2*
46
NC
58
D028
70
PD4
35
NC
47
w*
59
Vee
71
NC
36
NC
48
NC
60
D029
72
GND
NC/RAS3*
:
1. Pin 33 is a Ne for the 1M x 32 SIMM and RAS3* for the 2M x 32 SIMM.
2. Pin 45 is a NC for the 1M x 32, SIMM and RAS1 * for the 2M x 32 SIMM.
3-106
AS-58
Table 2. 72-Lead SIMM Pin Description
Symbol
Type
Name and Function
INPUT
MULTIPLEXED ROW/COLUMN ADDRESSES: Select a location within the flash
memory array in conjunction with appropriate RAS# and CAS # signals. Row
(upper) addresses are latched on the falling edge of RAS #, while column (lower)
addresses are latched on the falling edge of CAS #.
INPUT/
OUTPUT
DATA BUS: Inputs flash memory data and commands during CUI write cycles.
Outputs flash memory array, buffer, identifier or status data in the appropriate read
mode. Floated when the SIMM is de-selected or the outputs are disabled.
RASo_3#
INPUT
ROW ADDRESS STROBE: Latches row address information on inputs AO-9 when
RAS# transitions low. A subsequent CAS# low transition initiates flash memory
read or write operations. RASo# selects the lower 1M x 32 memory bank, while
RAS1 # selects the upper 1M x 32 bank (for the 2M x 32 SIMM). Signals RAS2#
and RAS3 # are not used in the design shown in Section 2.
CASO-3#
INPUT
COLUMN ADDRESS STROBE: Latches column address information on inputs
AO-9 when CAS# transitions low. When preceded by a RAS# low transition,
CAS # low initiates flash memory read or write operations in conjunction with W #.
Subsequent CAS # low transitions, with RAS # held low, enable fast page mode
reads/writes. CASo # selects the lower 16 bits of a memory bank, while CAS2 #
selects the upper 16 bits. Signals CAS1 # and CAS3 # are not used in the design
shown in Section 2.
W#
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Oata Queue
Registers and Address Queue Latches. W # is active low and initiates writes in
combination with RAS# and CAS# low. W# inactive high with RAS# and CAS #
low signifies a flash memory read operation. RAS # and CAS # high override W #
low.
Ao-A9
OQO-OQ31
OUTPUT
PRESENCE DETECT: Indicates SIMM speed/density information for system
identification. Various combinations of PO pins, either connected to GNO or left
not connected (pulled high by a resistor on the system board) refer to JEOEC
standards, as indicated in Table 3.
Vee
INPUT
OPERATIONAL AND ERASE/WRITE POWER SUPPLY (5V ± O.5V). 00 not
leave any power pins unconnected. Vee also provides the flash memory Vpp
update voltage. The design example in Section 2 does not support operation at
Vee = 3.3V ± 0.3V (see Section 3.4).
GND
SUPPLY
P01-4
NC
GROUND FOR ALL INTERNAL CIRCUITRY: 00 not leave any ground pins
floating.
NO CONNECT: Lead may be driven or left floating.
3-107
•
AB-58
GNO
SIMM Connector
: 0016-31 ':
Vpp
Vee
CASII
Wp#28F016XD AO-9
.
(Upper x16)
RYIBY#
RASII
MR#
AO-9
RPII
VcclN
~
: CAS2#
RASOII
WI
PWRGOOO
Vcc'-;
MAX705
Vcc
•
•
••
~
GN~' GNO
CASO#
Vee
000-15 .~
GNO
: RAS111
------
BANK 0 (1 Mbyte X 32)
oOplional
Bank 1
~
•
•
•
292152-2
Figure 2. The 28F016XD's Multiplexed Address Bus Interface
Makes DRAM-Compatible SIMM Designs Simple
2.1 Address and Data Bus
The multiplexed address and data buses of all flash
memories are connected together. See the 28F0l6XD
data sheet (Additional Inforination, Section 6) for percomponent address and data bus pin capacitance.
RAS #, CAS # and W # control prevents data bus contention between multiple flash memory components.
2.2 RAS#, CAS#, W#
The 28FOl6XD is a xl6-only flash memory, and each
28F0l6XD contains one CAS# input. CASo# connects to the lower 16-bit component in each 28FOl6XD
bank, while CAS2# connects to the upper 16-bit component. Therefore, this interface supports xl6 or x32
reads and writes. RASo# selects the first I Mbyte x 32
bank,while RASI # selects the optional second bank.
W # from the SIMM interface connects to all flash
memories.
2.3 .SIMM Power Pins
Vee from the SIMM interface Connects to the Vee and
Vpp inputs of all 28FOl6XD flash memories, and Vee
also connects to the optional supply voltage monitoring
3-108
circuit. GND from the SIMM interface connects to all
SIMM component GNDs. This design uses the S.OV
Vpp option of Intel's SmartVoltage technology. A
small ceramic capacitor filters each flash memory' Vcc
and Vpp input, while a larger decoupling capacitor filters Vee at the SIMM interface. See Section 3.4 for
aliernate Vee and Vpp techniques.
2.4 Other 28F016XD Signals
RP# Reset/Power-Down
This design includes an option8I low-cost supply voltage monitoring circuit (Maxim MAX70S) whose
POWERGOOD output controls flash memory RP#
inputs. This scheme protects the flash memory from
spurious command writes during system power transitions. Include the monitoring circuit unless you can
guarantee that your DRAM controller holds the
RAS#/CAS# combination and W# inactive with
Vee above VLKO (see 28FOl6XD specifications) in all
cases except when intentionally writing to flash memory. Experience has shown that many memory controllers have unspecified and unpredictable operation' during system power transitions.
AB·58
IT the monitoring circuit is not used, remove the 8-pin
SOIC layout from the SIMM and connect RP# to
Vee. Alternatively, connect SOIC layout pins corresponding to the (non-present) monitoring circuit Vee
input and POWERGOOD output, together with a
O-ohm resistor.
3.0 RECOMMENDATIONS FOR
DESIGN MODIFICATIONS AND
OTHER SIMM INTERFACES
This design connects WP# to Vee, driving this input
inactive at all times.
The 72-lead SIMM interface is only one of several pinouts approved by JEDEC and other standards bodies.
This section gives recommendations for adapting the
design techniques of Section 2 to other SIMM interfaces. In addition, it discusses providing voltages other
than 5.0V to the 28F016XD SIMM and enhancing system control of 28F016XD operations.
RY/BY#
3.1 Parity
This design does not use the RY/BY# output, leaving
it disconnected. System software should poll the flash
memory Status Registers to determine device status and
completion of internal operations.
Flash memory- is not subject to the alpha particle soft
errors that plague DRAM, as it stores the data value
(" 1" or "0") intrinsically on the floating gate of the
flash memory transistor. For this reason, a parity output was not included as part of the 28F016XD pinout.
In systems that employ parity check to confirm the
integrity of the DRAM memory subsystem, on-SIMM
programmable or dedicated logic can generate parity
bits required for the flash memory-based SIMM read
interface, if required. See Figure 3 for an example.
WP#
OE#
This design connects OE# to GND. RAS# and
CAS# active, in conjunction with an inactive (high)
W #, initiate a flash memory read. W # active low overrides the state of OE#. RAS# and CAS# inactive
high override OE# active low.
.A
Ul.lx_y
"
2.5 Other SIMM Signals
18# Ct8#
PD1-4
PD leads are connected to GND or left unconnected on
the SIMM, and are connected to Vee via pull-up resistors on the system board. Their state (" I" or "0"),
when read by system logic, provide SIMM speed/density information and reference the speed bin of the
28F016XD flash memories. JEDEC standard Presence
Detect pin combinations for 4-MB, 8-MB and 16-MB
(x36 72-pin) SIMMs with tRAe = 100 ns are shown in
Table 3. PD combinations for other "non-standard"
speed/density combinations are user definable.
PROG.
LOGIC
~
"
~
"
FLASH
MEMORY
ARRAY
PARITY
1,
292152-3
Table 3. PD Signal Combinations for Various
Densities
(tRAC = 100 ns)
4MB
8MB
16MB
PDl
GND
NC
GND
PD2
GND
NC
NC
PD3
GND
GND
GND
Figure 3. Parity Generation for DRAM Controller
Compatibility
PD4
GND
GND
GND
3-109
AB-58
3.2 8-Bit or 9-Bit SIMM Interfaces
3.4 .Vee and Vpp Flexibility
The 28F016XD is a x16-only flash memory component. When used in a x8 or x9 (see Section 3.1) SIMM
pinout, interface logic like that .shown in Figure 4
should be used to route system data to the correct 8 bits
of the flash memory bus and drive the alternate 8 bits to
"l"s. System software must write commands to the
flash memory only on the lower 8 bits for such an interface.
The 28F016XD, by virtue of its SmartVoltage technology can be operated at either 3.3V or S.OV Vee, and at
either S.OV or 12.0V Vpp. If 3.3V Vee operation is
desired (for lower power), an on-SIMM 3.3V-to-S.OV
converter can generate the necessary S.OV Vpp voltage.
RAS#
t
t
A
"
k'
~
"-
A
<"
CAS#
000-7
v
PROG.
LOGIC
008-15
28F016XD
A
DO 0-7
"
~
PARITY
(OPTIONAL)
1#
t
292152-4
Figure 4. Converting the 16-Blt Flash Memory
Data Bus to a x8/x9 System Interface
3.3 Flash Memory Control Inputl
Output and Vpp Control
SIMMs other than the 72-lead version described in Section 2 may include additional inputs and outputs that
can provide a system RESET # to the supply voltage
monitoring circuit MR # input. Alternatively, if system
RESET # includes power supply monitoring, this signal can directly control the 28F016XD RP# inputs.
Additionally, system I/O signals can control the flash
memory WP# input and route the RY/BY# output to
a system port pin or hardware interrupt line. Finally,
by separating out supply and program/erase voltage
pins, alternate or semi-custom SIMM interfaces can
provide 12.0V to the 28F016XD flash memory Vpp inputs for fast write performance and switch this program/erase voltage to GND when not updating flash
memory contents for additional write protection.
3-110
Some designs may desire to program and erase the
28F016XD at 12.0V Vpp for high write performance.
In these cases, include a S.OV-to-12.0V or 3.3V-to12.0V converter on the SIMM to generate the 12.0V
Vpp voltage. See application note AP-3S7 for industryrepresentative 12V-converters.
4.0 SOFTWARE GUIDELINES
System software should not attempt to scan/check the
28F016XD memory space as part of system initialization. The 28F016XD does not support the DRAM selfcheck function. Data combinations written to the
28F016XD may be decoded as valid commands and
result in unintended flash memory operations. Checksum calculation and comparison with a checksum data
value stored in the flash memory is a recommended
technique for ensuring data/code integrity.
The hardware interface described in Section 2 allows
only 16- and 32-bit command/data writes to flash
memory. When programming a flash memory location,
set bits not to be programmed to "l"s as part of the
data write. This technique can also be used to mask a
write to the alternate byte of a 16-bit word when performing a byte program operation.
The 72-lead SIMM interface of Section 2 does not allow
use ofthe flash memory RY /BY # output. System software should poll flash memory Status Registers to determine status of device operations, including program
and erase.
System software should separate temporary data from
code and "permanent" data tables, and route writes to
the former to the system DRAM memory space. Flash
memory is per-bit programmable (changing data "l"s
to "O"s) and per-block erasable (changing data "O"s to
"l"s), unlike DRAM, which is fully per-bit alterable.
AB-58
5.0 CONCLUSION
This application brief has described one possible SIMM
design using Intel's 28F016XD Flash memory, and has
provided design recommendations for alternative
SIMM approaches. Consult reference documentation
for a more complete understanding of device capabilities and design techniques. Please contact your local
Intel or distribution sales office for more information
on Intel's flash memory products.
6.0 ADDITIONAL INFORMATION
6.1 References
Order Number
Document/Tool
290533
28F016XD DRAM-Interface Flash Memory Datasheet
297372
"16-Mbit Flash Product Family User's Manual,
28F016SAl28F016SV /28F016XS/28F016XD"
292092
AP-357 "Power Supply Solutions for Flash Memory"
292123
AP-374 "Flash Memory Write Protection Techniques"
292126
AP-377 "16-Mbit Flash Product Family Software Drivers,
28F016SA/28F016SV /28F016XS/28F016XD"
292131
AP-384 "Designing with the 28F016XD"
Contact Intel/Distribution
Sales Office
FlashBuilder Utility
Contact Intel/Distribution
Sales Office
28F016XD Benchmarking Utility
Contact Intel/Distribution
Sales Office
28F016XD iBIS Models
Contact Intel/Distribution
Sales Office
28F016XD VHDLlVerilog Models
Contact Intel/Distribution
Sales Office
28F016XD Timing DeSigner Library Files
Contact Intel/Distribution
Sales Office
28F016XD Orcad and ViewLogic Schematic Symbols
6.2 Revision History
Description
Original Version
3-111
AP-398
APPLICATION
NOTE
Designing with the
28F016XS
KEN MCKEE
TECHNICAL MARKETING
ENGINEER
November 1994
Order Number: 292147-001
3-112
DESIGNING WITH THE 28F016XS
CONTENTS
PAGE
1.0 INTRODUCTION . .................. 3-114
2.0 OPERATIONAL FUNDAMENTALS
OF THE 28F016XS .................. 3-114
2.1 2SF016XS Pinout Comparison to
the 2SF016SA .................... 3-114
2.2 Enhanced Read Capability ....... 3-115
CONTENTS
PAGE
4.4 Interfacing Examples ............ 3-127
4.5 Optimizing Read Performance in xS
Mode ............................. 3-132
4.6 Consecutive Accesses Across
Memory Bank Boundaries ......... 3-133
4.7 Handling Asynchronous Writes ... 3-136
4.S System Boot from 2SF016XS .... 3-137
2.3 SFI Configuration ................ 3-117
3.0 CPU/BUS COMPATIBILITY WITH
28F016XS ........................... 3-118
4.0 INTERFACING TO THE
28F016XS ........................... 3-120
4.1 Clocking Options ................ 3-120
4.2 Alternating-A1 Access Rule ...... 3-124
5.0 DESIGNING A FLEXIBLE
INTERFACE FOR THE 28F016XS
AND 28F016SA/SV ................. 3-138
6.0 CONCLUSION ..................... 3-140
ADDITIONAL INFORMATION ......... 3-140
REVISION HiSTORy .................. 3-140
4.3 Same-A1 Access Rule ........... 3-126
I
3-113
Ap·398
1.0 INTRODUCTION
The interfacing concepts discussed in this document are
based on preliminary 28F016XS specifications. Please
contact your Intel or distribution sales office for up-todate information. Do not finalize a design based on the
specifications in this document.
The 28FOl6XS is an extremely high performance 16Mbit memory component, organized as either 2
MBytes or 1 MWord. The 28F016XS contains sixteen
128-KByte (64 KWord) blocks. Each block is separately erasable, lockable and capable of I million write/
erase cycles by providing wear-leveling algorithms and
graceful block retirement.
28FOI6XS's enhancements over first generation 16Mbit flash memories include:
• Synchronous pipelined read interface providing significantly improved read performance
• SmartVoltage technology
The 28F016XS's synchronous pipelined read interface
delivers highest read performance when interfaced to a
microprocessor with a burst or pipelined bus, such as
the i960® and Intel486™ microprocessors. The
28F016XS delivers equivalent or better read performance than DRAM, given an optimized interface.
The enhanced read performance capability of the
28F016XS eliminates the need of code shadowing from
nonvolatile memory (ROM, EPROM, etc.) to DRAM
for increased system performance. The 28F016XS eliminates the need for this multi-component memory model, enabling direct code execution out of nonvolatile
memory with its high read performance.
This application note will discuss the concepts involved
in interfacing to the 28F016XS, illustrating that it requires minimal glue logic and is compatible with a wide
range of processors and buses.
3-114
2.0 OPERATIONAL FUNDAMENTALS
OF THE 28F016XS
The 28F016XS, in read mode, is a fully synchronous
component with a maximum operating frequency of
66 MHz at 5V Vee. Write operations to the 28F016XS
are asynchronous, similar to traditional flash memories
such as the 28F016SA. Flash memory is read, erased
and written in system via the local processor.
2.1
28F016XS Pinout Comparison to
the 28F016SA
The 28F016XS's pinout is very similar to the pinout's of
the 28FOI6SA/SV (see Figure I). All devices use the
56-Lead TSOP package.
The 28FOl6SA uses the 3/5# pin (pin I) to configure
the flash memory for operation at 3.3V or 5.0V Vee.
The 28FOl6XS and 28F016SV use an internal detector
connected to Vee to accomplish this same function.
The 3/5# pin is no longer needed on the 28F016XS
and 28FOI6SV, and pin 1 has been renamed NC ("no
connect"). This pin maybe driven to VIL or VIH, or
may be left unconnected.
The 28F016XS also incorporates two new pins in comparison to the 28F016SA/SV: CLK (pin 29) and
ADV # (pin 30). These two pins. control the
28F016XS's synchronous pipelined read interface.
elK
CLK provides the fundamental timing and internal operating read frequency for the 28F016XS (maximum
frequency of 66 MHz at 5.0V ± 0.5V Vee and 50
MHz at 3.3V ± 0.3V Vee). CLK latches input addresses on its rising edge in conjunction with ADV #,
times out the SFI Configuration (configurable via the
Configure Device Command), and synchronizes device
outputs. CLK can be slowed or stopped without loss of
data synchronization. CLK is ignored during write operations.
Ap·398
28FO'6SJ 2BF016SV
~
CE"
NC
A20
A,.
A,.
A17
A16
Vee
A,S
A,.
A'3
A12
CEo'
Vpp
RP#
A11
A,o
Ag
A.
GND
A7
As
As
A.
A3
A2
A,
NC
CE,#
NC
A20
A,.
A,.
A17
A'6
Vee
A,S
A1'
A'3
A12
CEo#
Vpp
RP#
A11
A,o
Ag
As
GND
A7
A6
As
A.
A3
A2
A,
NC
CE,#
NC
A2fJ
A19
A,.
A17
A16
Vee
A,s
A,.
A'3
A'2
CEo'
Vpp
RP#
A11
A,o
A.
A.
GND
A7
As
As
A.
A3
A2
A,
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
17
18
19
20
21
22
23
24
25
26
27
28
WP#
WE#
OE#
RYIBY#
DO,s
D0 7
DO '4
D0 6
GND
DO '3
DOs
DO '2
DO.
Vee
GND
D011
D0 3
DO 10
D02
Vee
DO.
DO,
DO.
DO o
Ao
BYTE#
E28F016XS
56-LEAD TSOP PINOUT
14mm x20mm
. TOP VIEW
WP#
WEI
OE#
RY/BY
DO,s
D0 7
DO '4
D06
GND
DO'3
DOs
DO'2
DO.
Vee
GND
D011
D0 3
DO '0
D02
Vee
DO.
DO,
DO.
DO o
Ao
WP#
WEI
OE#
RYIBY#
DO,s
D0 7
DO,•
D06
GND
DO'3
DOs
DO'2
DO.
Vee
GND
D011
D0 3
DO '0
D02
Vee
DO.
DO ,
DO.
DO o
Ao
ADV#
eLK
292147-1
Figure 1. 28F016XS Pinout Configuration Compared to the 28F016SA/SV
ADV#
Address Valid (ADV #) indicates that a valid address is
present on the 28F016XS's address pins. ADV # sensed
active low on the rising edge of eLK latches the address into the 28F016XS, which initiates a read access.
ADV# is ignored by the 28F016XS during write cycles.
.li
Given an optimized interface, the 28F016XS's read,performance is up to 2x higher than traditional asynchronous flash memory. The 28F016XS's synchronous
pipelined read interface is capable of executing multiple
read accesses in parallel. This parallel execution capability more than doubles read performance.
·
• ··
• •
"I
.li
'<""-
c
i '?D
A2D
A1'
2.2 Enhanced Read Capability
AD
EVEN MEMORY BANK
....
A2
A1
"I
c
D
D
C
~
'?
c
i D
·•
·. •
•
2
_J
DJ
2
8'i-
2
-~
D
2
8y-
J
ODD MEMORY BANK
Mem~ry
Address Decoding
Figure 2 illustrates the 28F016XS's memory address
decoding. Addresses A20-1 select a 16-bit location within the 28F016XS's memory array. Address Al makes
the bank selection, even or odd bank. Byte selection, in
x8 mode (BYTE# = Vld, is based on the value of
address Ao. In xl6 mode (BYTE# = Vnv, the
28F0l6XS does not use Ao.
292147-2
Figure 2. Memory Address Decoding illustrating
Ao Selecting the Byte Location and
A1 Selecting the Even or Odd Bank
3-115
AP-398
CLK
(33 MHz
Example)
ADDR
A1
ADV#
CE#
OE#
Access 1
DATA
tCHQV
292147-3
NOTE:
Refer to the 28F016XS datasheet for timing specifications.
Figure 3. Initiating a Single Read Access Waveform
(28F016XS-15, SFI Configuration = 2)
Executing a Read Access Cycle
In read mode, ADV# and CLK together initiate read
accesses when the device is selected (Figure 3). A read
cycle is initiated and addresses are latched when the
28F016XS senses ADV# low on a rising CLK edge.
After a read cycle begins and the SFI Configuration
value has elapsed, data is latched and begins driving on
the output pins. Valid data is guaranteed tcHQV after
.the elapse of the SFI Configuration value.
Refer to Section 2.3 for further information about the
SFI Configuration.
Consecutive Read Accesses
Consecutive accesses to the 28F016XS, from the processor perspective, occur in either an Alternating-A] or a
Same-A] pattern. Of the two sequences, consecutive Alternating-A] accesses offer highest read performance.
3-116
Consecutive Alternating-A] accesses change the value
of address A I between consecutive read cycles. As Figure 4 illustrates, up to three accesses can be initiated
before data from the first access is valid on the output
pins. Consecutive Alternating-A] accesses allow multiple accesses to the 28F016XS to occur in parallel, effectively filling the 28FO 16XS's internal pipeline.
Consecutive Same-A] accesses retain the same address
Al value between consecutive read cycles. This pattern
allows up to two accesses to be initiated before data
from the first accesses is read. The SFI Configuration
value must elapse before a second access can begin (see
Section 2.3).
Refer to Sections 4.2 and 4.3, the Alternating-A] and
Same-A] access rules, for minimum delays between
consecutive read accesses. The Alternating-A] and
Same-A] access rules both apply to consecutive Alternating-A] accesses, while only the Same-A] rule applies
to consecutive Sam(!-A] accesses.
AP-398
ClK
(33 MHz
Example)
ADDR
A1
ADV#
CE#
OE#
DATA
tCHQV
292147-4
NOTE:
Refer to 28F016XS datasheet for timing specifications.
Figure 4. Synchronous Pipelined Read Waveform Example
(28F016XS-15, SFI Configuration = 2, Consecutive Alternating-A 1 Access)
2.3 SFI Configuration
The SFI Configuration (Table 1) optimizes the
28F016XS for a wide range of input CLK frequencies.
After a read access begins, the 28F016XS will latch
data on its output pins after a CLK count corresponding to the SFI Configuration has elapsed.
The 28F016XS default SFI Configuration is 4 after
power-up or return from deep power-down mode
(RP# = VIL), allowing system boot from the
28F016XS, if desired, at any CLK frequency up to 66
MHz at 5.0V ± 0.5V Vee (50 MHz at 3.3V ± 0.3V
Vee). SFI Configurations are retained if the 28F016XS
is put in sleep mode via a Sleep or Abort command. An
optimized SFI Configuration for a given frequency (Table 1) enables the highest read performance. The SFI
Configuration is updated via the Device Configuration
command. SFI Configurations can range from 1 to 4.
The 28F016XS is fully synchronous. CLK can be
slowed or stopped at any time within a series of accesses without loss of data synchronization.
Table 1. SFI Configuration
Correspondence to ClK Frequency
28F016XS-15
Frequency (MHz)
SFI Configuration
66 (and below)
4
50 (and below)
3
33 (and below)
2
16.7 (and below)
1
28F016XS-20
Frequency (MHz)
SFI Configuration
50 (and below)
4
37.5 (and below)
3
25 (and below)
2
12.5 (and below)
1
3-117
AP-398
Table 1. SFI Configuration Correspondence to
ClK Frequency (Continued)
Table 2. Intel Burst Order
Address A3-2 on a 32-Bit Processor
28F016XS-25
Intel-Burst Order
Frequency (MHz)
SFI Configuration
40 (and below)
4
First
Address
30 (and below)
3
20 (and below)
10 (and below)
Second
Address
Third
Address
Fourth
Address
00
01
10
11
2
01
00
11
10
1
10
11
00
01
11
10
01
00
NOTE:
SFI Configurations other than those shown in Table 1 pro, duce spurious results and should not be used.
3.0 CPU/BUS COMPATIBILITY WITH
28F016XS
The 28FOI6XS's synchronous read interface pipelines
up to three accesses at time. This multiple execution
capability makes the 28F016XS highly compatible with
CPUs and buses that employ an Intel or linear burst, or
pipelined bus.
Table 3. linear Burst Order
Address A3-2 on a 32-Bit Processor
Linear Burst Order
First
Address
Second
Address
Third
Address
00
01
10
11
01
10,
11
00
Fourth
Address
10
11
00
01
11
00
01
10
Burst Bus
A burst bus executes a series of accesses in retrieving
data from the memory subsystem. Accessing data consecutively, a processor or bus employing an Intel or
linear burst order increments the lower address lines,
effectively executing consecutive Alternating-A1 accesses. Tables 2 and 3 illustrate the Intel and linear burst
order, for a 4-access burst.
3-118
During a burst cycle, some CPUs themselves increment
addresses, while others only supply the initial address,
requiring peripheral logic to increment the address.
CPUs that increment addresses, however, may not provide addresses quick enough to take full advantage of
the 28F016XS's synchronous pipelined interface. Some
processors wait for the completion of the frrst access
before incrementing the address for the next access.
Generating addresses within the interfacing logic, the
28FOl6XS is not forced to wait for the CPU. Therefore,
several accesses can be initiated before the 28FOl6XS
completes the initial access.
AP-398
Figure 5 shows a block diagram of a four double-word
burst CPU interface to the 28FOI6XS. This interface
executes a 4 double word burst. Notice that addresses
A2-1 are controlled by the interface. A multi-bit counter generates the addresses for the burst cycle.
Using the interface to increment addresses, the
28FOl6XS achieves highest read performance executing
multiple Alternating-A I accesses at the same time. For
example, the 28F016XS-15, at 33 MHz and 5.0V Vee,
can deliver effective zero wait state performance interfacing to a burst bus, after the initial pipeline fill.
ADDRESS/DATA
A
~
'rCPU
r
lL
I~
C~K
READY
28F016XS
A 2_1
INTERFACE
LOGIC
~
r
ADV#
WE#
OE#
CE#
292147-5
Figure 5. Burst Address Generation and Wait-State Control
When Interfacing the 28F016XS to a Burst Processor
3-119
AP-398
104.
..
ADDRESS/DATA
r
CPU
•
lL
l'
28F016XS
INTERFACE
LOGIC
ADV#
C~K
WE#
bE#
CE#
READy .....
-
292147-6
Figure 6. Comparing Past Address with Current Address to Determine Whether an Alternatlng-A1 or
Same-A1 Access Occurs When Interfacing the 28F016XS to a Pipellned Bus Processor
Plpelined Bus
4.0 INTERFACING TO THE 28F016XS
A pipelined bus activates the address and control signals for the next cycle before completing the current
cycle. Pipelined buses have no defined access order;
therefore, Alternating-A1 accesses are not guaranteed.
The interface must guard against a possible mixture of
consecutive Alternating-A1 and Same-A1 accesses. Figure 6 illustrates a pipelined bus interface to the
28F016XS.
The 28F016XS can interface to a wide range of CPUs
and bus architectures. Glue logic is minimal and the
performance enhancements are significant. Below are
key considerations to keep in mind when interfacing to
the 28FOI6XS:
In a pipelined interface, the system logic does not increment the 28F016XS's lower addresses. The system logic instead latches address Al and compares it to Al of
the following cycle. Comparing AI> the interface logic
can identify Alternating-A1 and Same-A1 accesses,
which directly informs the interface logic when it can
initiate a read access to the 28F016XS. The AlternatingA 1 and Same-A 1 access rules define the minimum delay
between consecutive accesses (see Section 4.2 and 4.3).
In the past, external latches were required to latch the
next address and control signals. The 28FOl6XS eliminates this extra system overhead, latching the next address -internally and initiating the next cycle prior to
completing the current cycle. The 28F016XS's synchronous pipelined interface takes full advantage of a pipelined bus.
3-120
• Clocking Options
• Alternating-A1 Access Rule
• Same-A1 Access Rule
•
•
•
•
Optimizing Read Performance in x8 Mode
Consecutive Accesses across Bank Boundaries
Handling Asynchronous Write Cycles
System Boot-Up out of the 28F016XS
4.1 Clocking Options
In choosing a CLK option, keep in mind that the
28F016XS operates at optimum performance with a
CLK frequency at an upper SFI Configuration boundary (50 MHz and 33 MHz are two of four SFI Configuration upper boundaries for the 28F016XS-15 at 5.0V
Vce). See Section 2.3 for information about the SFI
Configuration.
AP-398
~ OSCILLATOR
I
I
B
u
F
F
E
R
ClK
DIVIDER
1
1x CLK (Option1)
2x CLK (Option2)
2xCLK
1x CLK (Option3)
1xCLK
PROCESSOR
292147-7
NOTE:
The buffer in Figure 7 eliminates loading effects on the oscillator
Figure 7. Different ClK Options when Interfacing to a Processor that Requires a 2x ClK Input
For example, a processor running at 25 MHz with a 2x
CLK input of 50 MHz provides both 25 MHz and
50 MHz CLK options (Figure 7). Using the 25 MHz
CLK, the 28F016XS-151-20 will begin driving data to
the output pins two clocks (or 80 ns) after initiating a
read cycle (SFI Configuration = 2 at 5.0 ± 0.5V
Veo. Using the 2x CLK, the 28F016XS-15 will begin
driving data to the output pins in three clocks, or 60 ns
(SFI Configuration = 3 at 5.0 ± 0.5V Veo. The CLK
frequency and SFI Configuration relationship affects
the 28F016XS's read performance.
time for interface logic to meet the 28F016XS's set-up
time (ADV #, CEx# and OE# to rising CLK edge). A
Ix CLK, on the other hand, has a longer period, relaxing the demands on the interfacing logic to meet the
28F016XS set-up time.
A general "rule of thumb" when choosing a CLK option: The higher the CLK frequency the higher the
28F016XS read performance but the faster the interfacing logic required.
Clock Generation and Synchronization
2x vs.1x ClK
Figure 7 illustrates three possible CLK options when
interfacing to a processor requiring a 2x CLK input
(processors such as the i960 processor and Inte1386TM
processor are two examples). Depending on the processor frequency, the 2x CLK may be closer to an upper
SFI Configuration boundary, thereby reducing the
28F016XS's access time. The higher frequency of the
2x CLK however, reduces the amount of available
External clock generation and synchronization may be
required when the interfacing processor uses a 2x CLK
input and does not provide external access to the internally synchronized Ix CLK. Generating and synchronizing a Ix CLK from a 2x or 4x CLK can be accomplished with simple flip-flop logic. (Many processors,
such as the Inte1386 processor, synchronize their internallx CLK with the trailing edge of RESET.) Example
PLD equations that generate and synchronize a Ix system output CLK are located in Appendix A.
3-121
AP-398
Clock skew can arise depending upon the approach taken to derive the Ix CLK. Figure 8 (A) will have a
maximum skew between the 2x and Ix clock of tcO!.
Figure 8 (B) will have minimal-to-no skew because
2x ClK
ClK Input
----.-----+ 102x Processor
both the 2x and Ix CLK outputs will have the same
delay, tCO!, through the EPLD. Figure 9 graphically
illustrates the amount of skew the two different CLK
generation circuits produce.
4x ClK - - - - - - ,
2x ClK Input
to Processor
EPLD
EPlD
1xClK
RESET
1xClK
RESET
(A)
(8)
292147-8
Figure 8. 1x ClK Configurations Using RESET for ClK Synchronization
3-122
AP-398
2xCLK
tCOt
1xCLK
Configuration (A) Skew
(Skew = tcov
4xCLK
2xCLK
1xCLK
Configuration (B) Skew
(Skew = 0)
292147-9
Figure 9. ClK Skew Produced by 1x ClK Configurations In Figure 8
3-123
AP-398
ClK
(33 MHz
Example)
ADDR
A1
ADV#
CE#
OE#
DATA
tCHQV
292147-10
NOTE:
Refer to the 28F016XS datasheet for timing specifications.
Figure 10. Alternating Access Rule, Illustrating tCHCHA
(28F016XS·15, SFI Configuration = 2, Cons,cutive Alternating-A 1Accesses)
4.2 Alternating-A 1 Access Rule
some designs, however, the sum oftcHQY, system delay
and CPU set-up requirement may exceed the CLK period, requiring access stretching.
The Alternating-A1 access rule (Figure 10) defines the
minimum time required between consecutive accesses
with different A 1 values. The Alternating-A 1 access rule
is:
Section 4.4 describes several interface examples demonstrating the Alternating-A 1 access rule.
tCHCHA > = tCHQV + (System Propagation Delay)
+ (CPU Set-up Requirement)
Access Stretching
tCHCHA is then rounded up to the nearest CLK period.
For example, if the summation of tCHQY, system delay
and CPU set-up requirement equals 24 ns, and .the
CLK (33 MHz) period equals 30 ns, tCHCHA is rounded up to 30 ns (I CLK period).
Access s~retching (Figure 11) extends the amount of
time data is held between consecutive accesses. Intermediate cycles with ADV# disabled between initial access and subsequent access will extend the number of
CLKs that the 28FOl6XS holds data. Intermediate cycles with ADV# disabled are required in all cases when
tCHQY exceeds the CLK period.
When tCHCHA equal one CLK period, an Alternating- '
A 1 access can execute on the next rising CLK edge. In
3-124
AP-398
ClK
(40 MHz
Example)
ADDR
A1
ADV#
CE# )
OE#
DATA
292147-11
NOTE:
Refer to the 2BF016XS datasheet for timing specifications.
Figure 11. Access Stretching Example at 40 MHz
(28F016XS-15, SFI Configuration = 3, Consecutive Alternating-A 1Accesses)
3-125
AP-398
4.3 Same-A 1 Access Rule
The Same-A] access rule (Figure 12) defines the minimum time required between accesses with the same address Al value. The Same-A] access rule is:
tCHCHS > = SFI.Configuration
or
tCHCHS = 2 • tcHCHA
>
tcHCHS equals the largest value derived from the two
above equations. For instance, a system operating at 50
MHz (20 ns period) with a SF! Configuration value set
to 3 and a tcHCHA equaling 40 ns
SFI Configuration (3) = 60 ns
2 • tcHCHA
= 80 ns
will have a tcHCHS equal to 80 ns.
Section 4.4 describes several interface examples that .
show the Same-A] access rule.
tCHQV
292147-12
NOTE:
Refer to the 28F016XS datasheet for timing specifications.
Figure 12. Ssme-A 1 Access Rule, illustrating tcHCHS
(28F016X8-15, SFI Configuration = 3, Consecutive Alternating-A 1 Accesses)
3-126
Ap·398
4.4 Interfacing Examples
The following wavefonn examples illustrate the Alternating-A 1 and Same-A 1 access rules.
tCHCHA calculation:
tCHQV
System Propagation Delay
CPU Set-up Requirement
Consecutive Alternating-A 1 Accesses at 33 MHz
Figure 13 illustrates consecutive Alternating-A 1 accesses at 33 MHz, interfacing to a burst bus. The system
logic controls ADV#, CEX# and OE# to initiate read
accesses to the 28F016XS. tCHCHA and tCHCHS (delay
between Alternating-A1 and Same-A1 accesses) define
the rate at which the system logic can initiate read accesses to the 28F016XS.
=
=
=
20 ns
Ons
4ns
Summation
= 24ns
tCHCHA
= 30ns
Access 2 can begin on the next rising CLK edge after
access I because tCHCHA equals one CLK period.
tCHCHS calculation:
SFI Configuration (2)
or
2' tCHCHA
= 60ns
= 60ns
= 60 ns
tCHCHS
tCHCHS is equal to two CLK periods. A second SameA 1 access can occur two clocks after the initial access.
This burst bus interface delivers 1-0-0-0 wait-state read
perfonnance at 33 MHz, excluding system-level overhead.
tCHQX
tCHQV
292147-13
NOTE:
Refer to the 28F016XS datasheet for timing specifications.
Figure 13.33 MHz Read Timing Waveform Example
(28F016XS-15, SFI Configuration = 2, Consecutive Alternating-A 1 Accesses)
3-127
AP-398
tcHCHS calculation:
Consecutive Same-A 1 Accesses at 33 MHz
Figure 14 .illustrates consecutive Same-A 1 accesses at
33 MHz. This situation could occur when interfacing to
a pipelined bus. Pipelined buses do not guarantee consecutive Alternating-A] accesses.
Consecutive Same-A1 accesses. as shown in this example. retain the same address Al value between accesses.
Therefore. the tcHCHA calculation is not required because no Alternating-A] accesses occur.
SFI Configuration (2)
= 60ns
tcHCHS
= 60ns
tCHCQS equals two CLK periods. Hence. access 2 can
begin two CLK periods after access 1.
This example read wait-state performance is 1-1 at 33
MHz. excluding system-level overhead.
ClK
(33 MHz
Example)
ADDR
A1
ADV#
CE#
OE#
DATA
tCHQV
tCHQX
292147-14
NOTE:
Refer to the 28F016XS datasheet for timing specifications.
Figure 14. 33 MHz Read Timing Waveform Example
(28F016XS·15, SFI Configuration = 2, Consecutive Same-A, Access)
3-128
Ap·398
Consecutive Alternating-A 1 Accesses at
40 MHz, Example 1
Figure 15 illustrates consecutive Alternating-A1 accesses at 40 MHz, interfacing to a burst bus.
tcHCHA calculation:
tCHQV
System Propagation Delay
CPU Set-up Requirement
Summation
tcHCHA
tCHCHS calculation:
SFI Configuration (3)
or
2' tCHCHA
tcHCHS
= 20ns
=
=
Ons
4ns
= 24ns
=
25ns
= 75ns
= 50ns
= 75ns
tCHCHS is equal to three eLK periods. A second SameA 1 access, therefore, can start three clocks after the
initial access.
This interface delivers 2-0-1-0 wait-state read perfonnance at 40 MHz, excluding system-level overhead.
tCHCHA equals one eLK period (25 ns). Therefore, an
Alternating-A1 can begin on the next rising eLK edge.
292147-15
NOTE:
Refer to the 28F016XS datasheet for timing specifications.
Figure 15.40 MHz Read Timing Waveform Example 1
(28F016X5-15, SFI Configuration = 3, Consecutive Alternating-A 1 Accesses)
3-129
Ap·398
tenCHA equals two CLK periods (25 n8). Therefore,
access stretching is required between Alternating-AI accesses.
ConsecutlveAltsmatlng-A 1 Accesses at
40 MHz, Example 2
Figure 16 also illustrates consecutive Alternating-A1 accesses at 40 MHz, interfacing to a burst bus. In this
example, a transceiver between the 28F016XS's outputs
and the CPU inputs add a system propagation delay to
the tcnCHA calculation.
tCHCHA calculation:
tcHQV
System Propagation Delay
CPU Set-up Requirement
tcHCHS calculation:
SFI Configuration (3)
or
2 * tcHCHA
tcHCHS
= 20ns
=
715 ns
= 100 ns
= 100 ns
5ns
4ns
tenens is equal to four CLK periods. A second SameA 1 access can begin four clocks after the initial access.
Summation
= 29ns
tcHCHA
= 50ns
This burst bus interface to the 28F016XS gives 2-1-1-1
wait-state read performance at 40 MHz, excluding system-level overhead.
=
=
CLK
(40 MHz
Example)
A1
CBI
OE#
. DATA
tCHQV
_
'cHQX
292147-16
NOTE:
Refer to the
28F016XS datasheet for timing specifications.
Figure 16. 40 MHz Rea~ Timing Waveform Example 2
(28F016X8-15, SFI Configuration = 3, Consecutive Altematlng-A 1Accesses, Access Stretching)
3-130
AP-398
Consecutive Alternating-A 1 Accesses at 66 MHz
Figure 17 illustrates consecutive Alternating-A] accesses at 66 MHz, interfacing to a burst bus.
tcHCHS calculation:
SFI Configuration (4)
or
2· tCHCHA
s required between Alternating-AI accesses.
tcHCHA calculation:
tCHQV
System Propagation Delay
CPU Set-up Requirement
tcHCHS
= 20ns
= Ons
=
= 60ns
= 60ns
= 60ns
tcHCHS is equal to four CLK periods. Hence, a second
Same-A] access can begin four clocks after the initial
access.
4ns
Summation
= 24ns
tcHCHA
= 30ns
This burst bus interface to the 28F016XS delivers
3-1-1-1 wait-state read performance at 66 MHz, excluding system-level overhead.
.
tCHCHA equals two CLK periods or 30 ns. Therefore,
access stretching is required between Alternating-A] accesses.
CLK
(66 MHz
Example)
A1
CEIl!
OEll!
DATA
'cHQV
'cHQX
292147-17
NOTE:
Refer to the 28F016XS datasheet for timing specifications.
Figure 17.66 MHz Read Timing Waveform Example
(28F016X5-15, SFI Configuration = 3, Consecutive Alternating-A 1 Accesses, Access Stretching)
3-131
AP-398
4.5 Optimizing Read Performance in
x8 Mode
When using the 28F016XS as a x8 device, the system
interface· to flash memory should be slightly modified
to ensure highest read performance. The interface
shown in Figure 18 ensures that, for a series ofsequential accesses, address A I will alternate between "0" and
"I." This configuration takes advantage of consecutive
Alternating-A1 accesses and enables highest the
28F016XS read performance.
The examples below show the Au/A I ·address sequence
that will be presented to the 28F016XS when either the
conventional or optimized Ao and AI interface configurations are used.
Implementing this hardware solution requires that code
and data be stored to the 28F016XS in a modified sequence when using a PROM programmer. This allows
expected data to be read in-system with addresses Ao
and AI swapped. On-board or in-system data write and
erase "proceed as normal;" the address translation is
handled automatically by hardware.
Figure 19 shows the code/data pattern that should be
used when storing information to the 28F016XS using
a PROM programmer. Figure 20 shows how that same
data pattern appears to the system bus, after the Au/A I
address swap.
bn
bn-2
Conventional Ao and A1 Configuration
A1
Ao
Access
0
0
1
1
0
1
0
1
Initial Access
Subsequent Same-A 1 Access
Subsequent Alternating-A 1 Access
Subsequent Same-A 1 Access
bn-1
bn-3
Optimized A and A. Confiauration
A1
Ao
Access
b4
0
1
0
1
0
0
1
1
Initial Access
Subsequent Alternating-A 1 Access
Subsequent Alternating-A 1 Access
SubseqLJent Alternating-A 1 Access
b3
b1
b2
bO
CODE/DATA PATTERN
BYTE#
S
,
~ !
~_.~!
28F016XS
x:
" ' -_ _ _....I
292147-18
Figure 18. Ao/A1 Optimized
Interface for x8 Mode Operation
3-132
292147-19
Figure 19. Code/Data Structure when
Performing Off-Board Programming
AP·398
Burst Bus
bn
A burst bus will only cross memory bank boundaries
when the length of the burst transfer exceeds the size of
the individual banks. Refer to Tables 2 and 3 for the
Intel and linear burst orders.
bn-1
bn-2
bn-3
Pipelined Bus
Pipelined buses do not guarantee linear sequential accesses. Therefore, consecutive accesses can potentially
bounce back and forth between different memory
banks, crossing bank boundaries.
b4
Handling Consecutive Accesses That Cross
Memory Bank Boundaries
b3
b2
b1
bO
CODE/DATA PATTERN
292147-20
Figure 20. Code/Date
Structure Seen by the Processor
4.6 Consecutive Accesses Across
Memory Bank Boundaries
Figure 21 illustrates a multi-bank 28FO 16XS configuration. CEQ# and CEI # make the particular memory
bank selection.
In this configuration, a sequence of accesses can potentially begin and end in different memory banks, which
could potentially cause bus contention if not properly
handled. All pipe1ined accesses to the initial bank must
complete before activating the output buffer to the next
memory bank. Both burst and pipelined buses are susceptible to this occurrence because of their sequential
accessing nature.
When consecutive accesses cross memory bank boundaries, it is important to guard against enabling the output buffers for both banks. All pipeline accesses to the
initial bank must complete before activating the OE#
to the next bank. Enabling the buffers for both banks at
the same time will cause bus contention.
System logic can handle consecutive accesses that cross
bank boundaries in one of two ways:
1. Complete all accesses initiated in the first memory
bank before addressing a new bank (Figure 22). This
configuration requires only one OE# (Figure 21).
2. Before finishing all accesses to the initial memory
bank, read cycles targeting a new bank can start as
long as its OE# is deactivated. All accesses to the
initial bank must finish before activating the OE #
to the next bank. The OE# for the next bank is
activated tGHQZ after the OE# to the initial bank
has been deactivated (Figure 23). This configuration
requires an OE# for each bank.
3-133
. AP-398
Bank1
I
ADDRESSJDATA
A
....
~
V
•
CPU
/
....
"..
...-
28F016XS
_
~
L...I\,
BankO
---,/
I
AM~II
READY
ADV#
Wet
OE#
CEo#
CE1 #
......
....
INTERFACE
LOGIC
-...
....
r--t-
v
....
- :..-..
..
--..1.
28F016XS
f292147-21
Figure 21. Two-Bank 28F016XS Combination, Burst Bus Interface, Single OE #
3-134
AP-398
292147-22
NOTE:
Refer to the 28F016XS datasheet for timing specifications.
Figure 22. Consecutive Alternating-A 1 Accesses Crossing Bank Boundaries,
One OE# (28F016XS-15, SFI Configuration = 2)
3-135
AP-398
CLK
(33 MHz
Exampl
A
ADDR
A1
ADV#
CEo#
DATA
t cHax
tCHav
292147-23
NOTE:
Refer to the 28F016XS datasheet for timing specifications.
Figure 23. Consecutive Allernallng-A 1 Accesses Crossing Bank Boundaries,
One OE# per Bank (28F016XS-15, SFIConflguratlon = 2)
4.7 Handling Asynchronous Writes
The 28F016XS write interface is asynchronous, similar
to other Intel flash memories. The 28F016XS's write
interface is not pipelined, therefore a write cycle must
complete before another begins.
When the interfacing CPU can execute a burst write
cycle, the system logic needs to manage the write cycle,
allowing only one write cycle to the 28F016XS at a
time. Write-back caches, for example, support burst
write cycles. The 28F016XS does support word/byte
write queuing, but the Queue Status (QS) bit in the
Global Status Register (GSR) should be checked before
attempting a second Write operation. If the queue is
available, a second Write operation can begin before the
Write State Machine (WSM) has completed the initial
Write operation. In addition to the command queuing,
the 28F016XS has two 256-byte page buffers.
3-136
The page buffers allow sequential loading at high
speeds. Refer to Intel's 16-Mbit Flash Product Family
User's Manual for further information about command
queuing and page buffer operations.
When the interfacing CPU does not support burst
writes, the 28F016XS's asynchronous write interface is
not an issue. The processor will only execute one write
cycle at a time.
When executing a write cycle, the interfacing processor
or bus will drive a write signal informing the system of
the desired operation. Monitoring this signal, the interfacing logic can correctly transition into an appropriate
state machine sequence. In this situation, the interfacing logic directly controls the 28F016XS's write control
signals (Figure 24), just as with asynchronous Intel
flash memories.
Ap·398
OEEP
POWER·DOWN
WRITEOATA-WfUTEOfI
ERASE SETtlP COMMAND
WAITE VALID ADDRESS
E~AJ~~~:~~W~~~~~O
AlJTOMATED DATA.WRITE
WRITE AEAD EXTENDED
OA ERASE DELAY
REGISTER COMMAND
ADORESSE~~~I~~~~~
Vll~
~
I
READ EXTENDED
,STATUS REGISTER DATA
NOTEt
t WHAX
"H~~~~~~~~~~~~~~~~~~~~~~~
ADDRESSES (A)
NOTE2 VI
I.STATUS
READ COMPATlaLE
REGISTER DATA
~~
~
NOTE 3
A IN
t AVAIi
I",\IWH
tWHA)(
NOTE.
',H
CElc'{E)
'IC
'IH
DE. (a)
'IC
WE,(W)
'''"
RY/Bvt (AJ
'OL
RP,(P)
292147-24
NOTE:
Refer to the 28F016XS datasheet for timing specifications.
Figure 24. Write Timing Waveform with Vpp at 5V or 12V
4.8 System Boot from 28F016XS
When booting from the 28F016XS, the interfacing logic
must first support the default SFI Configuration value,
4. Depending on the actual CLK frequency however,
the SFI Configuration (Section 2.3) may require adjustment to achieve maximum read performance. To
achieve this flexibility, the interfacing logic must:
I
• Support the default SFI Configuration
• Be aware of changes to the SFI Configuration
• Alter the interface accordingly to handle optimized
configuration
If a change is made to the SFI Configuration, the interface must be informed so that it can adjust accordingly.
If the interface does not adjust, it will continue performing read cycles assuming a default SFI Configuration.
3-137
AP-398
~igure 25 illustrates a possible way of informing the
Interface of a change to the SFI Configuration, using a
general purpose input/output (GPIQ). Qn system power up or reset, the GPIO'transitions to a specific logic
level (VIL or VnI>, informing the interface of a default
~FI Configuration. After altering the SFI Configuration, software changes the GPIQ value. This input inf?rms the interface of changes to the SFI ConfiguratIon.
~.~
........•.......
,.....
(
\
\
READY
INTERFACE
lOGIC
...
-
..
......
ADV#
..
ClK
....
....
WE
OE#
GPIO
.
RECONF
CE#
-
....
292147-25
Figure 25. Informing Interface of a SFI
Configuration Change
Figure 26 illustrates the internal state machine. Depending upon the value of the GPIQ (RECQNFIG),
the state machine will. take one of two paths. One path
is ~apable of handling the default SFI Configuration,
whtle the second path supports the optimized SFI Configuration. Supporting the default configuration, the interface logic initiates accesses to the 28F016XS corresponding to a SFI Configuration of 4. In the optimized
SFI Configuration, the interface can initiate read accesses to the 28F016XS at a faster rate if the SFI Configuration is less than 4. The rate at which the system
logic can start read cycles is related to the SFI Configuration value. Refer to section 4.2 and 4.3 for the Alternating-A1 and Same-A1 access rules.
CONTINUE READ CYCLE
STATE MACHINE
292147-26
Figure 26. State Machine Handling of Boot-Up
and OptlmlzedSFI Configuration
5.0 DESIGNING A FLEXIBLE
INTERFACE FOR THE 28F016XS
AND 28F016SA/SV
~esigners using the 28F016SA/SV now who are planrung a future upgrade to the 28F016XS can design system logic capable of interfacing to both components.
Pinout similarities between the 28F016XS and
28F016SA/SV support a single footprint suitable for
both components (see Section 2.1).
Supporting both components, the interface incorporates
a state machine designed to control the 28F016SA and
a second one to control the 28F016XS enhanced read
interface.
The device identifiers can be used to communicate
whether the 28F016SA/SV or enhanced 28F016XS device is in the system. The 28F016SA/SV and
28FO 16XS have distinct device IDs. A jumper configuration can also be used to communicate 28F016SA/SV
?r 28!,016.XS presence. Figure 27 illustrates the jumper
Identification method. The status of the jumper controls state machines within interface logic and/or can
be read by system software to set wait state registers
within the CPU.
Device ID or jumper identification can also be used to
enable system software usage of 28F016XS's Status
Register enhancements and the Device Configuration
Code.
3-138
AP-398
....
A
CPU
"" l
"""'"'-v"
...
ADDRESSIDATA
INTERFACE
LOGIC
OEIt
FlASH
MEMORY
WElt
CElt
Cr
ADVIt
READY
CLK
va
t
S.OV
JP1
292147-27
Figure 27. Jumper Identification of 28F016SA/SV or 28F016XS Presence for Wait State Control
3-139
AP-398
. 6.0 CONCLUSION
The read performance of the 28F016XS far exceeds
that of traditional flash memories. Up to three accesses
at a time can execute in parallel. The 28F016XS's synchronous interface makes it highly compatible with
CPU and bus architectures that implement an Intel
or linear burst or pipelined bus. This application note
has provided the fundamental knowledge that will enable designers to easily interface to the 28FO 16XS. For
further information about the 28F016XS, consult reference documentation for a more comprehensive understanding of device capabilities and design techniques.
ADDITIONAL INFORMATION
Order Number
290532
Document/Tool
28F016XS Datasheet
297500
"Interfacing the 28F016XS to the i960 Vcc
AP-384
Table 3. 28F016XD Added/Revised DC Characteristics
Vee = 5.0V ± 0.5V, TA = O°C to +70°C
Sym
lee 1
lec2
lee3
lec4
Parameter
Vee Word Read Current
Vee Standby Current
Vee RAS#·Only
Refresh Current
Vee Fast Page Mode
Word Read Current
Min
Typ
Max
Unit
90
120
rnA
2
90
80
4
120
110
rnA
rnA
rnA
Test Condition
Vee = Vee Max
RAS#, CAS# = VIL
RAS#, CAS#, Addr. Cycling @tRe
lOUT = OmA
Inputs = TIL or CMOS
Vee = Vee Max
RAS#, CAS#, RP#
WP# = VIL or VIH
=
Vee = Vee Max
CAS# = VIH
RAS# = VIL
RAS#, Addr. Cycling @tRe
Inputs = TIL or CMOS
Vee = Vee Max
RAS#, CAS# = VIL
CAS#, Addr. Cycling @tpe
lOUT = OmA
Inputs = VIL or VIH
=
min
=
min
Vee Standby Current
70
130
p.A
Vee = Vee Max
RAS#,CAS#,RP# = Vee ± 0.2V
WP# = Vee ± 0.2Vor
GND ± 0.2V
lee6
Vee CAS#-Before-RAS#
Refresh Current
50
65
rnA
Vee = Vee Max
CAS#, RAS# = VIL
CAS#, RAS#, Addr. Cycling @tRe
Inputs = TIL or CMOS
50
65
rnA
Vee = Vee Max
RAS#, CAS # = VIL
lOUT = OmA
Inputs = VIL or VIH
Vee Deep Power-Down
Current
2
5
p.A
RP#
Vee Word Write Current
25
35
rnA
Word Write in Progress
Vpp = 12.0V ± 5%
25
40
rnA
Word Write in Progress
Vpp = 5.0V ± 10%
18
25
rnA
Block Erase in Progress
Vpp = 12.0V ± 5%
20
30
rnA
Block Erase in Progress
Vpp = S.OV ± 10%
2
4
rnA
RAS#,CAS# = VIH
Block Erase Suspended
Vee Standby Current
(Self Refresh Mode)
ICCD
leew
IeeE
leeES
Vee Block Erase Current
Vee Erase Suspend
Current
=
min
=
min
VIH
lee5
lee7
=
GND ± 0.2V
3-147
Ap·384
Table 3. 28F016XD Added/Revised DC Characteristics (Continued)
Vee = 5.0V
± 0,5V, TA = O°C to +70°C
Typ
Max
Unit
Vpp Standby/Read
Current
±1
± 10
,..,A
Vpp
30
50
,..,A
Vpp> Vee
IpPD
Vpp Deep Power-Down
Current
0.2
5
,..,A
RP#
Ippw
Vpp Word Write Current
7
12
mA
Vpp = 12.0V ± 5%
Word Write in Progress
17
22
mA
Vpp = 5.0V ± 10%
Word Write in Progress
5
10
mA
Vpp = 12.0V ± 5%
Block Erase in Progress
16
20
mA
Vpp = 5.0V ± 10%
Block Erase in Progress
30
50
,..,A
Block Erase Suspended
1.5
V
Sym
Ipps
Parameter
Min
,
IpPE
Vpp Block Erase Current
IpPES
Vpp Erase Suspend
Current
VPPLK
Vpp Erase/Write Lock
Voltage
0.0
VPPH1
Vpp during Write/Erase
Operations
4.5
5.0
5.5
V
VPPH2
Vpp during Write/Erase
Operations
11.4
12.0
12.6
V
VLKO
Vee Erase/Write Lock.
Voltage
2.0
2.2 Timing Specifications
28F016XD timing specifications are divided into the
following categories in the datasheet.
• Common Parameters
•
•
•
•
Read Cycle
Write Cycle
Read-Modify-Write Cycle
Fast Page Mode Cycle (including fast page mode
read-modify-write)
• Refresh Cycle (including refresh period)
• Miscellaneous
Many 28F016XD specifications match or improve on
those of 60 ns and 70 ns DRAMs, Programming additional DRAM controller wait states will accommodate
most slower 28F016XD specs.
3-148
Test Condition
s
Vee
=
GND ± 0.2V
V
In some cases, specifications that have identical values
for both reads and writes to DRAM (such as RAS#
and CAS# pulse widths and hold times), have been
differentiated (separate specs for read and write) on the
28F016XD. This differentiation both accurately reflects
28F016XD functionality and improves the DRAM
controller interface to 28F016XD, in some cases.
Common Parameters
Table 4 compares 28F016XD common parameters to
DRAM, with incompatible specifications shaded for
emphasis. Areas where the 28F016XD improves upon
DRAM specifications are outlined in bold. Notice that
the 28F016XD's RAS# precharge time specification is
much shorter than that for DRAM, while the
28F016XD's CAS# precharge time specification is
slightly longer. Also, the 28FO 16XD's row address hold
time after RAS #, column address hold time after
CAS# and CAS#-to-RAS# precharge time are slightly longer than those for DRAM.
AP-384
Table 4. 28F016XD Common Parameters Compared to 60-70 ns 16-Mblt DRAM
Symbol
Description
DRAM
(3.3V)
2BF016XD
(3.3V)
DRAM
(S.OV)
2BF016XD
(S.OV)
tRP
RAS" Precharge Time (min)
40 ns
10 ns
40-50 ns
10 ns
tcp
CAS# Precharge Time (min)
10 ns
15 ns
10 ns
15 ns
tASR
Row Address Set-Up Time (min)
o ns
o ns
o ns
o ns
tRAH
Row Address Hold Time (min)
10 ns
15 ns
10 ns
15 ns
tAse
Column Address Set-Up Time (min)
o ns
ons
ons
o ns
tcAH
Column Address Hold Time (min)
10-15 ns
20 ns
10-15 ns
20 ns
tcRP
CAS# to RAS# Precharge Time
(min)
5 ns
10ns
5 ns
10 ns
toze
DE # Delay Time from Data-In (min)
Ons
Ons
toze
CAS# Delay Time from Data-In
(min)
o ns
o ns
o ns
o ns
o ns
o ns
Read Cycle Specifications
28F016XD read cycle specification incompatibilities
compared to DRAM can be summarized in the following three points:
• The 28F016XD's-access time from column address
is longer than that for DRAM
• The 28F016XD's access time from OE# and CAS#
active is longer than that for DRAM
• The 28F016XD's data tri-state delay from OE#,
RAS # or CAS # inactive is longer than that for
DRAM
Table 5 compares 28FOl6XD read cycle specifications
to DRAM, with incompatible specifications shaded for
emphasis. Areas where the 28FOl6XD improves upon
. DRAM specifications are outlined in bold.
3-149
AP-384
Table 5. 28F016XD Read Cycle Specifications Compared to 60-70 ns 16-Mbit DRAM
3-150
Read Command Hold Time Referenced to
CAS #
Ons
o ns
Ons
ons
Read Command Hold Time Referenced to
RAS# (min)
ons
Ons
o ns
o ns
AP-384
Write Cycle Specifications
Read-Modify-Write Cycle Specifications
Most 28F016XD write cycle specification incompatibilities compared to DRAM can be summarized by the
fact that the 28F016XD CAS# active pulse width during writes is longer than the DRAM requirement. The
28F016XD's data hold time and WE# hold time from
CAS# are also longer than that specified for l3V
DRAM. Table 6 compares 28F016XD write cycle specifications to DRAM, with incompatible specifications
shaded for emphasis. Areas where the 28F016XD improves upon DRAM specifications are outlined in bold.
28F016XD read-modify-write cycle specification incompatibilities compared to DRAM are caused by a
combination of the read and write cycle incompatibilities described earlier. Read-modify-cycles are commonly used to "flip bits" in DRAM data tables and video
memory. Given the flash memory usage model (read
mostly, alter data infr~quently), read-modify-write cycles to the 28F016XD will not occur in most applications.
Table 7 compares 28F016XD read-modify-write cycle
specifications to DRAM, with incompatible specifications shaded for emphasis.
Table 6. 28F016XD Write Cycle Specifications Compared to 60-70 ns 16-Mblt DRAM
Table 7. 28F016XD Read-Modify-Write Cycle Specifications Compared to 60-70 ns 16-Mblt
3-151
AP-384
Fast Page Mode Cycle Specifications
Refresh Cycle Specifications
28F016XD fast page mode cycle specification incompatibilities compared to DRAM have the same root
causes as the read and write cycle incompatibilities described earlier. Fast page mode read-modify-write cycles to the 28F016XD will not occur in the majority of
applications.
Flash memory does not require refresh to retain stored
data contents. However, by interfacing to a DRAM
controller, it will automatically receive the same refresh
cycles that DRAM receives. The 28F016XD supports
all common refresh cycles; CAS#-before-RAS#,
RAS#-only, hidden and self-refresh. In these modes, it
will either drive or float the data bus just as a DRAM
would. Refresh cycles have no other effect on
28F016XD stored data.
Table 8 compares 28FOl6XD fast page mode cycle
specifications to DRAM, with incompatible specifications shaded for emphasis. Areas where the 28F016XD
improves upon DRAM specifications are outlined in
bold.
Table 9 compares 28F016XD refresh cycle specifications to DRAM, with incompatible specifications shaded for emphasis. Areas where the 28F016XD improves
upon DRAM specifications are outlined in bold.
Table 8. 28F01SXD Fast Page Mode Cycle Specifications Compared to SO-70 ns 1S-Mbit DRAM
3-152
AP-384
Table 9. 28F016XD Refresh Cycle Specifications Compared to 60-70 ns 16-Mbit DRAM
DRAM
(3.3V)
28F016XD
(3.3V)
DRAM
(S.OV)
28F016XD
(S.OV)
5ns
Ons
10n8
10ns
tcHR
CAS# Hold Time (CAS#·before·RAS#
Refresh) (min)
10-15 n8
10 n8
10-20 n8
10 ns
twRP
WE# Set·Up Time (CAS#·before·RAS#
Refresh) (min)
10 ns
10 ns
10 ns
10 ns
tWRH
WE# Hold Time (CAS#-before-RAS#
Refresh) (min)
15 ns
10 ns
10-15 ns
10 ns
Miscellaneous Specifications
The 28F016XD documentation contains timing specifi·
cations not found in DRAM datasheets. These timings
relate to the 28FOI6XD's additional control inputs/
Vee
=
3.3V ± 0.3V, TA
outputs and voltages (WP#, RP#, RY/BY#, Vpp) as
well as minimum Data Write and Erase durations. Tables 10 and 11 show these additional specifications, at
3.3V Vee and 5.0V Vee respectively.
Table 10. 28F016XD Added/Revised AC Timings
+7d"C
= O"C to
28F016XD-9S
Versions
Parameter
Min
Max
Unit
RP # High to RAS # going low
480
ns
RP# Set-Up to WE #. going low
480
ns
Vpp Set-Up to CAS# high at end of write cycle
100
WE# High to RY IBY # going low
ns
100
ns
RP # Hold from Valid Status Register Data and RY IBY # high
0
ns
Vpp Hold from Valid Status Register Data and RY IBY # high
0
n8
Vee at 3.0V (minimum) to RP# high
2
,.,.8
3·153
AP-384
Table 10. 28F016XD Added/Revised AC Timings (Continued)
Vee = 3.3V ± 0.3V, Vpp = 5.0V ± 0.5V, TA = O"C to + 70"C
Sym
Parameter
Min
Typ
Max
Units
Page Buffer Word Write Time
TBD
12.1
TBD
,.,.s
twHRH1
Word Write Time
TBD
24;0
TBD
,.,.s
tWHRH3
Block Write Time
TBD
0.8
TBD
sec
Block Erase Time
TBD
1.4
TBD
sec
Full Chip Erase Time
TBD
44.8
TBD
sec
Vee = 3.3V ± 0.3V, Vpp = 12.0V ± 0.6V, TA = O·C to +70"C
Sym
Parameter
Min
Typ
Max
Units
Page Buffer Word Write Time
TBD
4.4
TBD
,.,.s
tWHRH1
Word Write Time
5
9
TBD
,.,.s
tWHRH3
Block Write Time
TBD
0.3
1.0
sec
Block Erase Time
0.3
0.8
10
sec
TBD
25.6
TBD
sec
Full Chip Erase Time
Vee
=
5.0V ± 0.5V, TA
Table 11. 28F016XD Added/Revised AC Timings
+ 70"C
= O"C to
28F016XD-85
Versions
Parameter
Min
Max
Unit
RP# High to RAS# going low
300
ns
RP# Set·Up to WE# going low
300
ns
Vpp Set-Up to CAS # high at end of write cyqle
100
ns
WE# High to RY/BY# going low
Rp# Hold from Valid Status Register Data and RY IBY # High
Vpp Hold from Valid Status Register Data and RY IBY # High
Vee at 4.5V (minimum) to RP# High
3·154
100
0
ns
ns
0
ns
·2
,.,.s
AP-384
Table 11. 28F016XD Added/Revised AC Timings (Continued)
Vee = 5.0V ± 0.5V, Vpp = 5.0V ± 0.5V, TA
=
O°C to +70°C
Parameter
Min
Typ
Max
Units
Page Buffer Word Write Time
TBD
12.1
TBD
J-Ls
tWHRH1
Word Write Time
TBD
16
TBD
J-Ls
tWHRH3
Block Write Time
TBD
0.6
TBD
sec
Sym
Vee = 5.0V
Sym
Block Erase Time
TBD
1.0
TBD
sec
Full Chip Erase Time
TBD
32.0
TBD
sec
Units
± 0.5V, Vpp = 12.0V ± 0.6V, TA = O°C to +70°C
Parameter
Min
Typ
Max
Page Buffer Word Write Time
TBD
4.1
TBD
/Ls
tWHRH1
Word Write Time
4.5
6
TBD
J-Ls
tWHRH3
Block Write Time
TBD
0.2
1.0
sec
Block Erase Time
0.3
0.6
10
sec
TBD
19.2
TBD
sec
Full Chip Erase Time
2.3 Package and Pinout
Although the 28F016XD includes all necessary inputs
and outputs for interfacing to DRAM controllers, its
pinout and package do not match those of DRAMs but
instead evolve from other 16-Mbit Intel flash memories.
The 28F016XD uses a 56-lead TSOP package, with
pinout shown in Figure 1 and package dimensions
shown in Figure 2.
Table 12 summarizes pinout comparisons between the
28F016XD in 56-lead TSOP and various DRAM package options.
If compatibility between the 28FOl6XD and DRAM
"footprints" is desired, 28F016XD flash memories can
be placed on DRAM-compatible SIMMs. Please see
the Additional Information section of this application
note for documentation that covers this topic in more
detail.
Comparable 1M x 16 (16-Mbit) DRAMs use two packages, a 42-lead SOJ and 44-lead TSOP. Examples of
these DRA-M pinouts are shown in Figures 3 and 4.
3-155
AP-384
NC
GND
NC
A.
A.
A,
A.
As
1
2
3
4
5
6
7
Vee
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
RAS#
CAS#
NC
NC
GND
V pp
RP#
NC
NC
NC
NC
GND
NC
NC
A.
A.
A,
A,
A.
0
WP#
WE'
OEI
RYIBY'
DQ,.
DQ,
DQ"
DQ.
GND
DQ"
DQ.
DQ"
DQ.
s
E28F016XD
56-LEAD TSOP PINOUT
Vee
41
14mmx20mm'
TOP VIEW
GND
DQ11'
DQ.
DQ,.
DQ,
Vee
DQ.
DQ,
DQ.
DQ.
NC
26
27
,28
31
Vee
NC
NC
292131-1
Figure 1. 28F016XD 56-Lead TSOP Type I Pinout Configuration
3-156
Ap·384
L-=-____________~~
°
,3 ()
1
,
~O
SEE DETAIL B
Ll
-------,0
-~I~.IJ
1.1---.
A~~SE'D"ALLA
.
r--~~------------~~
DETAIL B
DETAIL A
292131-2
Figure 2. 28F016XD 56-Lead TSOP Type I Package Dimensions
Family: Thin Small Out-Line Package
Symbol
Millimeters
Minimum
Nominal
A
Maximum
1.20
A1
0.50
A2
0.965
0.995
1.025
b
0.100
0.150
0.200
c
0.115
0.125
0.135
01
18.20
18.40
18.60
E
13.80
14.00
14.20
e
0.50
0
19.80
20.00
20.20
L
0.500
0.600
0.700
N
0
56
O·
3°
Y
Z
Notes
5·
0.100
0.150
0.250
0.350
3-157
AP-384
GND'
Vee
1101
1102
41
11018
1101.
11014
11013
A2
2
3
4
5
8
7
8
9
10
11
12
13
14
15
16
17 '
18
19
A3
20
A4
Vee
21
GND
1/03
1/04
Vee
1105
1108
1107
1/08
NC
NC
WRITE#
RAS#
A11R
A10R
AO
A1
GND
11012
11011
11010
1109
NC
LCAU
UCAS#
OEI
AIR
AIR
A7
A8
A5
292131-3
Figure 3. 16-Mblt DRAM 42-Lead SOJ Pinout Configuration
Vee
1101
1102
1103
1104
Vee
1105
1106
1107
1108
NC
NC
NC
WRITE.
RASIlI
AllR
Ai OR
AO
A1
A2
A3
Vee
2
3
4
5
8
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
QND
43
11018
11015
11014
11013
QND
11012
11011
11010
1109
NC
NC
LCAS.
UCAS.
OE'
AIR
AIR
A7
A8
AS
A4
QND
292131-4
Figure 4. 16-Mblt DRAM 44-Lead TSOP Pinout Configuration
3·158
AP-384
Table 12. 28F016XD Pinout Compared to 16·Mbit DRAM
Pin Name
42·Lead SOJ DRAM
Pin Number
44·Lead TSOP DRAM
Pin Number
56·Lead TSOP
28J;016XD Pin
Number
Vee
1,6,21
1,6,22
9,31,37,43
Vpp
-
-
15
GNO
22,37,42
23,39,44
2,14,21,42,48
000
2
2
33
001
3
3
35
002
4
4
38
003
5
004
7
5
40
7
44
005
006
8
8
46
9
9
49
..
007
10
10
51
DOs
33
35
34
DOg
34
36
36
0010
35
37
39
DOn
36
38
41
0012
38
40
45
0013
39
41
47
0014
40
42
50
0015
41
43
52
Ao
17
18
28
A1
18
19
27
A2"
19
20
26
A3
20
21
25
A4
23
24
24
A5
24
25
8
A6
25
26
7
A7
26
27
6
As
27
28
5
Ag
28
29
4
WE#
13
14
55
3-159
AP-384
Table 12. 28F016XD Pinout Compared to 16-Mblt DRAM (Continued)
Pin Name
42-Lead SOJ DRAM
Pin Number
44-Lead TSOP DRAM
Pin Number
56-Lead TSOP
28F016XD Pin
Number
30
54
OE#
29
RAS#
14
15
10
CAS #
-
-
11
-
CASL#
31
32
CASH #
30
31
-
RP#
WP#
11
-
16
RY/BY#
-
NC
11,12,15,16,32
53
55
11,12,13,33,34
1,3,12,13,17,18,19,
20,22,23,29,30,32
2.4 Capacitance
28FOI6XD input/output capacitance specifications
compared to 16·Mbit DRAMs are shown in Table 13.
Table 13. 28F016XD Capacitance Specifications Compared to 16-Mblt DRAM
S~mbol
DeSCription
DRAM
(3.3V)
C'N
Capacitance Looking into an Address Pin
CCTRl
Capacitance Looking into a Control Pin
COUT
Capacitance Looking into an Output Pin
3.0 28F016XD INTERFACING TO
DRAM CONTROLLERS'
Section 2.0 identified areas of compatibility and incompatibility between the 28F0l6XD and DRAMs. This
section, on the other hand, discusses how to determine '
the 28FOI6XD's ability to interface with an aIready-designed DRAM controller. Section 3.0 is divided into
'
three topics:
• Configurable Specification Interfacing
• Non-Configurable Specification Interfacing
• Additional 28FOI6XD Interface Hardware
Figure 5 shows an example interface between the
28FOI6XD and system CPU via a standard DRAM
3-160
28F016XD
(3.3V)
DRAM
(5.0V)
28F016XD
(5.0V)
5pF
8pF
5-6pF.
8pF
7pF
8pF
7pF
8pF
7pF
. 12 pF
7-10 pF
12 pF
controller. This interface diagram will be used in the
example calculations to follow. The DRAM controller
provides no RD# output, so the 28F016XD's OE#
input is grounded. CAS # low in conjunction with active WR # is decoded as a write, overriding OE#. Parity is disabled within the DRAM controller (at least for
the banks in which the 28FOI6XD resides).
Note that data buffering is done by the'DRAM controller itself. In designs that do not provide this capability
or in very high chip count arrays, transceivers can be
used to minimize CPU local bus or DRAM bus loading
by the DRAM/28FOI6XD memory subsystem. When
determining the need for isolation transceivers, keep in
mind that the 28FOl6XD input and output capacitance
are higher than those for comparable DRAM (as explained in Section 2.4).
Ap·384
+5V
1
,~
MEMORY
CONTROLLER
CPU
--'"
T
I
vee.
I
RY/BY#
INT
+5V/+12V _______ Vpp
WR#
WE#
RASX#
S#
CASx#
AS#
A9·0
015-0
28F016XD
A9·0
I
.
OQ15.Q
OE#
GNO
I
I
-
-1-
-
292131-5
Figure 5. Example DRAM Controller Interface to the 28F016XD
Please reference Figures 6 and 7 for example DRAM
controller waveforms, which will also be used in calculations to follow. These diagrams show timings for a
lx-clock driven (i.e., 25 or 33 MHz) system. For a
2x-clock driven (i.e., 50 or 66 MHz) DRAM controller
waveform, the main difference is in the clock period
shown; CLK is halved within the DRAM controller to
generate its signals. The X-Y-Y-Y format shows how
many Ix or 2x clock cycles are used for the first data
access (including RAS# transitions) and subsequent
accesses (toggling CAS# in fast page mode).
The examples assume that both minimum and maximum delays after CLK edges are provided for RAS # ,
CAS# and addresses. If minimum delays are not given
in DRAM controller documentation, contact the vendor for more information. Alternatively, a 0 ns delay
can be assumed, although this may impact interface to
the 28F016XD.
X-Y-Y-Y wait-state formats are often shown in conjunction with a clock frequency (i.e., 4-2-2-2 at
33 MHz) in DRAM controller datasheets. This does
not mean that this wait-state· setting is unique to the
CLK shown; wait-state settings are frequency-independent from the DRAM controller point of view. The
wait-state format/clock frequency combination simply
indicates a standard DRAM speed bin setting (i.e., 60
or 70 ns DRAM). For DRAM controllers. with mini·
mal flexibility in wait-state confignration, the
28FOl6XD may still be interface·compatible, albeit at a
slower frequency.
The following sections will make the assumptions listed
below:
• The DRAM controller will not generate read-modify-write cycles to the 28F016XD.
• Only areas in which 28FOl6XD specifications exceed those for DRAM will be discussed. Compatibility is assumed when 28FOl6XD specifications
match or improve upon DRAM specifications.
• Signal transition times (rise and fall) will not be included in example calculations.
3-161
AP-384
ClK
i
f
T1
! T3
'x ~
ADDR
X
ICOLUMN
x
X
.
!,.,.:\~--~~----~
i
RAS#
T4
i4--+
CASt
DATA (WRITES)
\II \17 'CD
!
I
WEI
i
--t----t-----t-------'lK
TI
.OOH,..------*~...,..,."
.~
. 292131-6
Figure 6. 4-2-2-2 Fast Page Mode DRAM Controller Sequence
ClK
i
ii4-+
T8
T3
x
i+-+
ADDR
i
T2
X
x
ICOlUMN
i++
RAS#
\'-+----+-----+------'-+---+---+-------;i T4
T5
i
CASt
!\\...-+---+i4---+-.J0--+---+--<1
I..
WEI
DATA (WRITES)
T6
~
,\~--+---II
i
---t----!----+-----l~~---+r-7--~~~f..L.l
Read mode power consumption is 2.2W (5.0V x
220 rnA x 2 devices). Read mode energy consumption
is 17 ,..,Joules (2.2W x 256 clocks x 30 ns/clock).
Standby power consumption is 400 mW (5.0V x 40 rnA
x 2 devices). Data retention current at 5.0V Vcc is the
same as standby current, therefore data retention
(sleep) power consumption is 400 mW.
Power and Energy Consumption (3.3V Vcd
Read mode power consumption is 1.3W (3.3V x
200 rnA x 2 devices). Read mode energy consumption
is 10 ,..,Joules (1.3W x 256 clocks x 30 ns/clock).
Standby power consumption is 198 mW (3.3V x 30 rnA
x 2 devices). Data retention current at 3.3V Vcc is the
same as standby current, therefore' data retention
(sleep) power consumption is 198 mW.
Ap·600
16·Mblt PAGED MASK ROM
Calculations that follow used the x16 version of the
16-Mbit paged mask ROM, which is not yet widely
available from multiple vendors. The xS 16-Mbit paged
mask ROM is the more common version today.
Power and Energy Consumption (5.0V Vcc>
Read mode power consumption is 250 mW (5.0V x
50 rnA). Read mode energy consumption is 6.S ,..,Joules
(250 mW x 900 clocks x 30 ns/clock).
Read Performance (S.OV Veel
Sequential reads allow use of the mask ROM page
,mode. The assumed 5.0V Vee 16-Mbit mask ROM
random access time is 150 ns, with 75 ns accesses in
page mode (4-word page). Therefore; 16-Mbit mask
ROMs are capable of 5-3-3-3-5-3-3-3 .... read performance at 5.0V Vee and 33 MHz (4-2-2-2-4-2-2-2 .... in
terms of wait states). This results in a 19 MByte/sec
read transfer rate, as shown by the calculation below:
512 bytes/(9oo clocks x 30 ns/clock) = x MByte/sec
x = 19 MByte/sec
Read Performance (3.3V Veel
Standby power consumption is 500 ,..,W (5.0V
xloo ,..,A). 16-Mbit mask ROM does not provide a
sleep mode, so sleep current is equal to standby current,
or 500 ,..,W.
Power and Energy Consumption (3.3V Vcc>
Read mode -power consumption is 132 mW (3.3V x
40 rnA). Read mode energy consumption is 4.S 1l-10ules
(132 mW x 1216 clocks x 30 ns/clock).
Standby power consumption is 330 ,..,W (3.3V x
100 ,..,A). 16-Mbit mask ROM does not provide a sleep
mode, so sleep current is equal to standby current, or
330,..,W.
The assumed 3.3V Vee 16-Mbit mask ROM random
access time is 200 ns, with 100 ns accesses in page mode
(4-word page). Therefore, 16-Mbit mask ROMs are capable of 7-4-4-4-7-4-4-4.... read performance at 3.3V
Vee and 33 MHz (6-3-3-3-6-3-3-3 .... in terms of wait
states). This results in a 14 MByte/sec read transfer
rate, as shown by the calculation below:
512 bytes/(1216 clocks x 30 ns/clock) = x MByte/sec
x = 14 MByte/sec
3-191
Ap·600
4-Mbit EPROM
Calculations that follow used the xl6 version of the
4-Mbit EPROM (Intel 27C400 or equivalent).
Power and Energy Consumption (S.OV Vcd
Read Performance (S.OV Vcd
Read mode power consumption is 250 mW (5.0V x
50 rnA). Read mode energy consumption is 9.6 J.Uoules
(250 mW x 1280 clocks x 30 ns/clock).
The assumed 5.0V Vee 4-Mbit EPROM random access time is 150 ns. Therefore, 4-Mbit EPROMs are
capable of 5-5-5-5-5-5-5-5 .... read performance at 5.0V
Vee and 33 MHz (4-4-4-4-4-4-4-4 .... in terms of wait
states). This results in a 13.3 MByte/sec read transfer
rate, as shown by the calculation below:
Standby power consumption is 500 ,...W (5.0V x
100 ,...A). 4-Mbit EPROM does not provide a sleep
mode, so sleep current is equal to standby current, or
500 ,...W.
512 bytes/(1280 clocks x 30 ns/clock) = x MByte/sec
x = 13.3 MByte/sec
Read Performance (3.3V Vcd
The assumed 3.3V Vee 4-Mbit EPROM random access time is 200 ns. Therefore, 4-Mbit EPROMs are
capable of 7-7-7-7-7-7-7-7 .... read performance at 3.3V
Vee and 33 MHz (6-6-6-6-6-6-6-6 .... in terms of wait
states). This results in a 9.5 MByte/sec read transfer
rate, as shown by the calculation below:
5l2.bytes/(1792 clocks x 30 ns/clock) = x MByte/sec
x = 9.5 MByte/sec
3-192
Power and Energy Consumption (3.3V Vcd
Read mode power consumption is 132 mW (3.3V x
40 rnA). Read mode energy consumption is 7.1 J.Uoules
(132 mW x 1792 clocks x 30 ns/clock).
Standby power consumption is 330 ,...W (3.3V x
100 ,...A). 4-Mbit EPROM does not provide a sleep
mode, so sleep current is equal to standby current, or
330,...W.
AP-600
1-Mblt EEPROM
This analysis used two I-Mbit (x8) EEPROMs to create the assumed 16-bit system interface.
Power and Energy Consumption (S.OV VeC>
Read Performance (S.OV Vcc>
Read mode power consumption is 500 mW (S.OV x
100 rnA). Read mode energy consumption is
15 pJoules (500 mW x 1024 clocks x 30 ns/clock).
The assumed S.OV Vee I-Mbit EEPROM random access time is 120 ns. Therefore, I-Mbit EEPROMs are
capable of 4-4"4-4-4-4-4-4.... read performance at S.OV
Vee and 33 MHz (3-3-3-3-3-3-3-3 .... in terms of wait
states). This results in a 16.7 MByte/sec read transfer
rate, as shown by the calculation below:
Standby power consumption is 2.5 mW (S.OV x
500 ,..,A). l-Mbit EEPROM does not provide a sleep
mode, so sleep current is equal to standby current, or
2.SmW.
512 bytes/(l024 clocks x 30 ns/clock) = x MByte/sec
x = 16.7 MByte/sec
Read Performance (3.3V Vec>
The assumed 3.3V Vee I-Mbit EEPROM random access time is 200 ns. Therefore, I-Mbit EEPROMs are
capable of 7-7-7-7-7-7-7-7.... read performance at 3.3V
Vcc and 33 MHz (6-6-6-6-6-6-6-6.... in terms of wait
states). This results in a 9.5 MByte/sec read transfer
rate, as shown by the calculation below:
Power and Energy Consumption (3.3V Vcc>
Read mode power consumption is 264 mW (3.3V x
80 rnA). Read mode energy consumption is 14 pJoules
(264 mW x 1792 clocks x 30 ns/clock).
Standby power consumption is 990 ,..,W (3.3V x
300 ,..,A). I-Mbit EEPROM does not provide a sleep
mode, so sleep current is equal to standby current, or
990,..,W.
512 bytes/(1792 clocks x 30 ns/clock) = xMByte/sec
x = 9.5 MByte/sec
3-193
infel~
AP-800
1.8" HDD
Only information for 5.0V Vee 1.8" HDDs was used
in the calculations that follow; 3.3V Vee 1.8" HDDs
were not yet available.
cc>
Effective read transfer rate is highly dependent on
length ofread sequence.
Power and Energy Consumption (5.0V Vcc>
Read Performance (5.0V V
The HDD must flI'St locate data stored on its platter(s)
and transfer it to the sector buffer before the system can
read it. The assumed 5.0V Vee 1.8" HDD seek access
time (including rotational latency) is 30 ms. The assumed peak media transfer rate is 2 MByte/sec or
477 ns/byte, and the peak interface transfer rate is
3 MByte/sec or 318 ns/byte. Therefore, 1.8" HDD at
5.0V Vee can access 256 words (512 bytes) of data in
30.4 ms (1 x 106 33 MHz clocks), resulting in a
16.8 Kbyte/sec read transfer rate, as shown by the calculations below:
+ (477 ns/byte x 512 bytes) +
(318 ns/byte x 512 bytes) =30.4 ms
(1 clock/30 ns) x (30.4 ms) = 1 x 106 33 MHz clocks
512 bytes/30.4 ms = x MByte/sec
x = 16.8 Kbyte/sec
Access time = 30 ms
3-194
Read mode power consumption is 1.9 W (5.0V x
380 mA). Read mode energy. consumption is
57.8 mJoules «1.9 W) x (1 x 106 clocks) x (30 nsf
clock».
Standby power consumption is 750 mW (5.0V x
150 mA). Sleep power consUmption is 25 mW (5.0V x
5 mA).
AP-600
1.3" HOD
Only information for 5.0V Vee 1.3" HDDs was used
in the calculations that follow; 3.3V Vee 1.3" HDDs
were not yet available.
Effective read transfer rate is highly dependent on
length of read sequence.
Power and Energy Consumption (S.OV Vcd
Read Performance (S.OV Vcd
The HDD must first locate data stored on its platter(s)
and transfer it to the sector buffer before the system can
read it. The assumed 5.0V Vee 1.3" HDD seek access
time (including rotational latency) is 15 ms. The assumed peak media transfer rate is 1.5 MByte/sec or
636 ns/byte, and the peak interface transfer rate is also
1.5 MByte/sec or 636 ns/byte. Therefore, 1.3" HDD at
5.0V Vee can access 256 words (512 bytes) of data in
15.7 ms (522 x 103 33 MHz clocks), resulting in a
32.7 Kbyte/sec read transfer rate, as shown by the calculations below:
Read mode power consumption is 1.5W (5.0V x
300 rnA). Read mode energy consumption is
23.5 mJoules «1.5W) x (522 x 103 clocks) x (30 nsf
clock».
Standby power consumption is 500 mW (5.0V x
100 rnA). Sleep power consumption is 15 mW (5V x
3 rnA).
Access time = 15 ms + (636 ns/byte x 512 bytes) +
(636 ns/byte x 512 bytes) = 15.7 ms
(1 clock/30 ns) x (15.7 ms) = 522 x 103 33 MHz
clocks
512 bytes/15.7 ms = x MByte/sec
x = 32.7 Kbyte/sec
3-195
\
TECHNICAL
PAPER
Interfacing the
28F016XS to the i960®
Microprocessor Family
KEN MCKEE
TECHNICAL MARKETING ENGINEER
TIM KELLY
ENGINEER
RANNA PRAJAPATI
ENGINEER
November 1994
Order Number: 297500-001
3-196
INTERFACING THE 28F016XS TO THE
i960® MICROPROCESSOR FAMILY
CONTENTS
PAGE
CONTENTS
PAGE
1.0 INTRODUCTION ................... 3-19B
4.0 i960® KB·25 MICROPROCESSOR
INTERFACE ......................... 3-217
2.0 1960® CA·33 MICROPROCESSOR
INTERFACE ......................... 3-199
4.1 Circuit Description ............... 3-217
2.1 Circuit Description ............... 3-199
4.2 Software Interface
Considerations ........ , , , . , , , .. , .. 3-219
2.2 Software Interface
.
Considerations .................... 3-201
4.3 Read Burst Cycle Description at
25 MHz ....... " ...... " .......... 3-219
2.3 Single and Burst Read Cycle
Description at 33 MHz ............. 3-202
4.4 Write Burst Cycle Configuration at
25 MHz." ..... , ... , .. ".,", .. ". 3-223
2.4 Single Burst Write Cycle
Description at 33 MHz ............. 3-206
3.0 i960® JF·33 MICROPROCESSOR
INTERFACE ......................... 3-209
3.1 Circuit Description ............... 3-209
I
5.0 INTERFACING TO OTHER i960®
MICROPROCESSORS ... , . , . , , ...... 3-225
6.0 CONCLUSION ., ... " .. , ....... " .. 3-225
ADDITIONAL INFORMATION., ... , ... 3-226
3.2 Software Interface
Considerations .................... 3-210
REVISION HISTORY ... , .............. 3-226
3.3 Burst Read Cycle Description at
33 MHz ........................... 3-211
APPENDIX A: PLD FILES .. , .......... 3-227
3.4 Burst Write Cycle Description at
33 MHz ........................... 3-215
APPENDIX B: BENCHMARK
PERFORMANCE ANALYSIS .. , ..... 3-236
3-197
28F016XS/i960® Interface
1.0 INTRODUCTION
This technical paper describes several designs interfacing the high-performance 28F016XS Flash memory to
the i960® microprocessor family. All designs are based
on preliminary 28F016XS specifications. These designs
have been fully simulated but no yet taken to lab prototype. Please contact your Intel or distribution sales office for up-to-date information. Do not fmalize a design
based on the specifications in this document.
The 28F016XS is a 16-Mbit flash memory with a highperformance synchronous pipelined read interface. The
28FOl6XS combines ROM-likenon-volatility, DRAMlike read performance and in-system update ability in
one memory technology. These characteristics enable
code execution directly from the 28F016XS memory
space, replacing the costly practice of shadowing code
from HDD or ROM to DRAM for increased performance. The 28F016XS improves' system performance,
ruggedness and cost of any burst microprocessor, such
as the i960 microprocessor, base design. The i960 microprocessor family sees widespread use in various applications, including imaging and data communications.
The 28F016XS performs synchronous pipelined reads.
Up to three accesses can be initiated before reading
data output from the initial cycle. This pipelined structure is ideal for use with the i960 microprocessor's
burst transfer mechanism. The 28F016XS brings signif-'
icant system performance enhancements to an i960 microprocessor-based environment. This technical paper
describes processor-to-memory interfaces that exploit
these capabilities to achieve maximum system performance. Figures 1 and 2 illustrate relative system performance enhancements that the 28F016XS brings to an
i960 microprocessor-based environment, compared to
other memory technologies. The benchmark parameters are documented in Appendix B.
Relative System
Performance (%)
100
90
80
70
60
50
40
30
20
10
297500-1
Figure 1. Relative System Performance
Enhancement of the 28F016XS Compared to
Other Memory Technologies In an 1960® KB-25
Microprocessor-Based Design
Relative System
Performance (%)
f] EPROM
100
l1li ROM
[j DRAM
f] 28F016XS
60
40
20
o
UOP/IP Networking
Benchmark
Imaging Benchmark
297500-2
Figure 2. Relative System Performance
Enhancement of the 28F016XS Compared to
Other Memory Technologies in an 1960® CA-33
Processor-Based Design
3-198
28F016XS/1960@ Interface
2.0 1960@ CA·33 MICROPROCESSOR INTERFACE
Chip Selact
Decode
~
Logic
----:--->..
Ie
I~CA
CEo #
OV- CE,#
L
r1~::::::::::r--~A~"~~-~ A~3
11
ProCHllsor
A3,..
CSIIH...-.----~
A3'.'
ClKIN ~33 MHz
ClKMODE!4-sV
28F016XS
L-.r--Cio;EE#ii1---.loE#
A".
WEI I-----.IWE#
WP#
CTR, t - - - - ' I A .
AD
BLAST#I-------i4---.j State CTR
A,
Machine
0
RYIBY#
1-------
Part
SFI Configuration
2
i960 CA-33
Microprocessor
Ready Inputs
OFF
Byte Ordering
LITTLE
ENDIAN
Bus Width
32-BIT
Wait States:
Nrad
3
Nrdd
0
Nwad
2
Nwdd
2
Nxda
0
Address Pipelining
ON
Burst mode
ON
3-201
28F016XS/1960® Interface
2.3 Single and Burst Read Cycle
Description at 33 MHz
Refer to the read cycle timing diagrams (Figures 7 and
8) and the state diagram (Figure 6) for the following
read cycle discussion.
RESET
~--""S9
BLASTII=O
'ADSII=1
BLASTtI=1
297500-6
NOTE:
CEll' and WEll' are clocked on the inverted elK edge
Figure 6. Read State Diagram of Single and Address Plpelined Burst Control Interface
Shown In Figure 3
3-202
28F016XSli960® Interface
Initial Configuration
Figure 7 illustrates a read cycle with the 28F016XS-15s
and i960 CA microprocessor in a reset/power-up configuration state. The initial configuration permits only
non-burst transfers. The i960 CA microprocessor initiates a read cycle by asserting ADS # with W /R # =
"0," presenting the valid address and control signals.
At N = 1, the two-bit counter loads the values on
address bits A3-2. The state machine asserts ADV# for
the next clock edge (N = 2), where the 28F016XS-15
will clock in the address if CS # is asserted. If CS # is
not asserted, the state machine returns to inactive state
at N = 2. The state machine asserts ADV# for only
one clock edge before entering a hold state to await the
assertion of BLAST # by the i960 CA microprocessor.
The state machine asserts OE# (to meet timing requirements OE # is falling-edge triggered) on the falling edge between N = 2 and N = 3 to enable the
28F016XS-15 data output buffers. With SFI Configuration = 4, the data will be valid at the N = 7. The
28F016XS-15s will hold data on the bus until the i960
CA microprocessor asserts BLAST #. During the clock
period following N = y, the state machine returns to
its inactive state, de-asserting OE# to tri-state the
28F016XS-15 data outputs.
PCLf(
(33MHz)
tSU1,
ADS#
~
WIR#
~I+-+,
tSU11
I
BLAST
A31-4
A3-2
°31-0
CSt
CFG
ADV#
mx
mx
X>~-----r-------.-------.--------.-------.-------.:~
,
tSU1
I
tSU1
,
~
,
,
~
~I-,
I
~I-,
,
tVLCH
,
, \14--, I
,
\
DE#
WEt
,
CTRo-o
~
----'---~~
297500-7
Figure 7_ Example Read Cycle, Initial Configuration,
Showing Key Specifications Requiring Consideration
3-203
28F016XS/l960® Interface
Optimized Configuration
cycle. After detecting the assertion of BLAST IF, the
state machine will return to its inactive state waiting for
a new access targeting the 28F016XS memory space.
Figure 8 illustrates a two double-word burst read followed by a four double-word burst read with the
28F016XS-15s, i960 CA microprocessor and state machine configured for optimum read performance. With
CFG· = I, the counter increments the two lower bits of
the address at N = 2, N = 3 and N = 4, and ADV IF
remains asserted so that the 28F0l6XS-15 latches in
four successive addresses at N = 2 through 5. With
SFI Configuration = 2, the first data will be valid at
N = 5. If a second read cycle follows the current read
cycle, the i960 CA microprocessor will assert ADS IF
one clock after asserting BLAST IF. The state machine
will respond by immediately re-entering the read
OJ
.. 1
When implementing the i960 CA microprocessor address pipelining capability, the state machine controlling CS IF monitors the upper ad9ress lines, ADS IF and
BLAST IF. CS IF is held active upon detecting an access
targeting the flash memory space until BLAST IF is asserted with ADS IF de-asserted. When BLAST IF and
ADS IF are active at the same time, a pipelined read
access is in progress. The CSIF state machine examines
the upper address lines to determine whether or not the
current pipelined access is aimed at the 28F016XS
memory space.
Dk
OJ+1
Dk.
Ok.2
______~~~~:._a_c_H~____~__~~__~____~__~____~__~,_.__~____~~~--J~
CFG
ADVt
CE.
WE.
I
I .........su•
.......
___~\;.VLCH
.
_ _ _.......J
'VLCH I
I,..--L. ~
~~----:~'G~L~CH--L:----LJ'!
______~__-L.I---\1.,-,
I
tVlGH,
I
,
I \~.__~I
1.1
~_ _~~_ _-u
..
.L-.Jr.-
____
!;-\....L:~__.L-..,...-L.____
.L-.,--L____
I-
1-
~~~-~~j.~.3~~---<:~~---:Lk-.~3--L-~-L.----~j_--
297500-8
Figure 8. Example Two Double-Word Burst Read Followed by Pipellned Four Double Word Burst Read
Showing Key Specifications Requiring Consideration
3-204
28F016XSli960® Interface
Critical Timings
data hold from CE# going high, the chip select state
machine must hold CS # active for 5 ns to satisfy the
i960 CA-33 microprocessor data input hold specification of 5 ns. Hence, the chip select state machine holds
CS# active for an additional clock period after detecting BLAST # active.
Table 2 describes the critical timings illustrated in Figures 7 and 8. One particularly critical timing in this
designs, is the data hold time. The i960 CA-33 microprocessor requires a 5 ns hold time afterthe clock edge.
The 28F016XS-15 guarantees a 5 ns data hold after
clock, meeting the processor's hold requirement with 0
ns of margin.
The i960 CA-33 microprocessor control outputs
ADS # and W!R # have 3 ns of margin and BLAST #
has 5 ns of margin to meeting the 85C22VlO-15 input
setup requirement.
This design provides 7 ns of margin in meeting the 3 ns
setup time of the i960 CA-33 microprocessor data inputs, outputting data tCHQV after a rising CLK edge.
Consult the appropriate datasheets for full timing information.
Another critical area concerns CS# during pipelined
read accesses. Since the 28FO 16XS-15 specifies zero
Table 2. Example Read Cycle Timing Specifications at 5V Vee
Part
Symbol
Parameter
Minimum Specified
Value (ns)
Input Setup Time to ClK
9
85C22V10-15
tSU1
i960 CA-33 Microprocessor
TI81
Input Setup D31-0
3
TIH1
Input Hold 031-0
5
tElCH
CE # Setup to ClK
25
tVlCH
AOV # Setup to ClK
15
Address Setup to ClK
15
28F016XS-15
tAVCH
tGlCH
, OE # Setup to ClK
15
NOTE:
Consult appropriate datasheets for up-tO-date specifications.
3-205
28F016XSli960® Interface
Initial Configuration
2.4 Single Burst Write Cycle
Description at 33 MHz
Refer to the write cycle timing diagrams and the state
diagram (Figure 9) for the following write cycle discussion.
Figure 10 illustrates a write cycle. In the reset/powerup configuration state, the interface supports only nonburst writes. The i960 CA microprocessor initiates a
write cycle by asserting ADS# with W/R# = "I,"
presenting a valid address and control signals. At N =
I, the. two-bit counter loads the values on address bits
A3-2. The state machine asserts WE# (to meet timing
requirements, WE# is falling-edge triggered) on the
falling edge between N = 1 andN = 2. WE# remains
asserted for two clock periods, in order to meet the
28F016XS-15 timing requirements. The state machine
then enters a holding state until the processor asserts
BLAST #, after which time the interface state machine
will return to SO.
Optimized Configuration
297500-9
Figure 9. Write State Diagram of Control
Interface Shown in Figure 3
3-206
Figure II illustrates a two double-word burst write
with CFG = "1." When the first data write is complete
at N = 4, the counter increments the two lower
address bits, and the state machine asserts WE# on
the next falling clock edge to begin the next the
28FOI6XS-15.data write. The i960 CA microprocessor
must provide the next data during the clock period following N = 4. The data writes continue to the next
consecutive addresses until the i960 CA microprocessor
asserts BLAST #, indicating the end of the burst write
cycle.
28F016XS/1960® Interface
PCLl<
(33 MHz)
ADS.
~
tSU1
,
~""
I
W/R.
I
BlASTt
I~ISUI
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ItSU1
I
I
I
I
I
I
I
I
I
I
I
I
:
:
:
:
:
:
:
:
:
:
:
:
:
I
I
I
I
I
I
I
I
I
I
I
I
I
I
ADV.
I
I
CE.
I
I
I
I
I
I
I
: i+-'WHAX :
I
I
A 31 ....
A 3-2
mlOO<
mlOO< I
~
10VWH
--+
i+-IWHOX
01
"\~"LI
CSt
I
I
CFG
I
\
WE.
I
IIA~
I
:
:X
I
I
I
I
I
'wLWH
'-----+1
:
:
,
,
I
...
I
I
X
I
I
,
"
:~
:~
:~
I
I
I
,
,
r-
I
297500-10
Figure 10. Example Write Cycle, Initial Configuration,
Showing Key Specifications Requiring Consideration
W/R.
~'._.:'S,Ul
1---.
--r---J
ItSU1
Bwrr'~~----~------~-----r------r------T------T-~~
A 31-4
. . . 'wHAX
xxxxxx
XXXXXXJ
.
XXXXXX I
' XXXXXXJ
IOVWH
--+
01
CSt
I
..."1iiiHox
... WHOX
xxxx
01+1
'E 1"-1
1\10--0
I
I
,
,
I
I
I
I
,
,
,
CFG
~11wHEH
,
ACVI
DE.
WE.
I
I
IIA::'"
~
... ~
IWLWH 1-----+1
~HAX
i+-'WHAX
X
I
I
I
I
I
,
X
X
1+1
I
I
I
297500-11
Figure 11. Example Two Double-Word Burst Write illustrating
Key Specifications Requiring Considerations
3~207
28F016XS/i960® Interface
Critical Timings
Table 3 describes the critical timings illustrated in Figures 10 and 11.
One critical hold time to notice is tWHAX. WE# is
guaranteed to transition within 8 ns from the falling
clock edge. Therefore, the tWHAX requirement has 2 ns
of margin on CTR1_O, and 5 ns of margin on A31-4.
Also notice that CfRl-O must be valid before WE# is
asserted. CfRl-O are guaranteed valid 8 ns after the
rising clock edge, providing 9 ns of margin.
Consult the appropriate datasheets for full timing information.
Table 3. Example Write Cycle Timing Parameters at SV Vee
Part
85C22V10·15
28F016XS-15
Symbol
Parameter
tSU1
Input Setup Time to ClK
9
tELwL
CE # Setup to WE # Going low
0
tAVWL
Address Setup to WE # Going low
0
tWLWH
WE # Pulse Width
50
tOVWH
Data Setup to WE # Going High
50
tWHOX
Data Hold from WE # High
0
tWHAX
Address Hold from WE # High
tWHEH
CE# Hold from WE# High
5
5'
NOTE:
Consult appropriate datasheets for up-to-date specifications.
3-208
Minimum Specified'
Value (ns)
28F016XS/i960® Interface
3.0 i960® JF-33 MICROPROCESSOR INTERFACE
l1Q'~
AD 3 1"()
'I-- AD3~
4 OCTAL
LATCHES
I--
a~
CHIP SELEC
DECODE
LOGIC CS.
J
1960'"JF
Processor
ALE
L....:..
~
LE
ov ________
OQ,5-0
CEO#
CE1#
eLK
28F016XS
I
QA21-4
A2(}'3
r-
VPP
,- 5V
BYTE.
OEO
DE.
rr- OV
GPIQ
WP'
WE.
A
A3-2
ADS#
W/R.
BLAST#
RDYRCV#
elKIN
RESET.
14-----
33 MHz
j4---- RESET.
~
CFGt
WEO
CTR,
A,
ClRo
A,
STATE
MACHINE ADV'
AND BURST
COUNTER
ADV#
Switched
5VOr12V
Ao
~ INT
r- RESET.
RYIBY#
RPO
CLK
RESET.
22V10
297500-12
Figure 12. Minimal Interface Logic Required In Interfacing the 28F016XS-15 to the
1960 JF-33 Microprocessor
Using this interface, the 28FOI6XS-15/i960 JF-33 microprocessor system can achieve 3-0-0-0 wait state read
performance, supporting burst transfers.
CLK Option
A 33 MHz clock signal drives the i960 JF microprocessor CLKIN input and the PLD and 28F016XS-15s
CLK input.
3.1 Circuit Description
Reset
This design (Figure 12) uses two 28F016XS-15s to
match the 32-bit data bus of the i960 JF microprocessor, providing 4 Mbytes of flash memory. Four octal
latches, enabled by the ALE signal, de-multiplex the
32-bit address from the AD bus. The latched address
bits QAD21-4 and'the counter outputs CTR1-O from the
PLD select locations within the 28F016XS memory
space. The two-bit counter implemented in the PLD
loads the address bits on A3-2, at the beginning of each
memory cycle, and generates the lower two bits of the
burst addresses on its outputs CTR1_O to the
28F016XS-15.
An active-low reset signal, RESET # , connects to the
RESET # inputs of the i960 JF microprocessor and
PLD and to the RP# input of the 28F016XS-15. Figure 5 illustrates a suggested logic configuration for generating RESET # .
Interface Control Signals
ADS # and W/R # i960 JF microprocessor signals, just
as in the i960 CA microprocessor design, serve as inputs to the state machine, which controls the two-bit
counter and generates the OE#, WE# and ADV# signals for the 28F016XS-15s. The state machine also generates the RDYRCV # signal for the i960 JF microprocessor to control the insertion of wait states during
data transfers.
3-209
28F016XS1I960® Interface
Configuration Signal
A general purpose input/output (GPIO) generates the
configuration signal for input to the state machine. The
configuration signal must be reset to logic "0" on power-up and system reset to ensure that the operation of
the state machine matches the 28FOI6XS-15s. After
optimizing the 28FOI6XS-15s, the reconfiguration signal must switch to a logic "I" to take advantage of the
new configuration.
Additional Control Signals
For information regarding BYTE#, WP#, RY/BY#
and Vpp, see Section 2.1.
3.2 Software Interface
Considerations
Boot·up Capability
This interface supports processor boot-up from the
28F016XS-15 memory space after power-up or reset.
Burst reads and writes may commence with no configuration. However, read wait state performance will be
5-1-1-1 until the SFI Configuration is set to 2 and the
CFG input is set to logic "1." Program control should
jump to an area of RAM to execute the configuration
sequence. A pseudocode flow for this configuration sequence is shown below.
Execute Device Configuration command sequence
Activate CPG signal
End
The SFI Configuration must be set to 2 before theCFG
input is set to logic "1." Thereafter, burst read wait
state performance will improve to 3-0-0-0.
3-210
28F016XSli960® Interface
3.3 Burst Read Cycle Description at
33 MHz
Refer to the read cycle timing diagrams and state diagram (Figure 13) for the following discussions of the
read cycle.
RESET
_---t~S13
CS#=O
• CFG=O
BLAST#=l
·CFG=O
BLAST#=l
297500-13
Figure 13. Read State Diagram of Burst Control Interface Shown In Figure 12
3-211
28F016XS/i960® Interface
C,"
(33MHz)
ADS.
WIR'
I
•
I
I
I
I
LAD;n.o ~. - A, 3-2
I...
t
I
-
-
-
..
I
-
-
-
...
I
I
-
-
_
...
I
-
-
-
I
I
I
t
I
I
I
:'
I
:r-
_1@(1"";§::-:-,---i">tXXX'::"DJC":".,:-"----;'X'«X~DJ"".'7',---!',~,
..
•
~~.!..J-r:----:---,-----r---r--,---I:xC:::~'.,.,Jc.:.'=-'=-'=-~lV:X'--------..,.7:'-'J,.....:.,=---_-_...,~(\--,,'J~.3'--_~
OA,,~ ~
V"~A"""
::~
:,CF.
ADV,
0"
.
=~~~~~X~-~~_-~~_-_-_-~~X~=;J::~===]X=:J;"~:===:j~=~~~===:===~:==:~::=::=:~~:=::
297500-14
Figure 14. Example Four Double-Word Burst Read in Initial Configuration
Showing Key Specifications Requiring Consideration
Initial Configuration
Figure 14 illustrates a four double-word burst read cycle with the 28F016XS-15s and the state machine in the
reset/power-up configuration state. The i960 JF microprocessor initiates a read cycle by asserting ADS # with
W/R# = "0", presenting a valid address and control
signals. At N = I with ADS # = "0", the two-bit
counter loads the values on the address bits A3-2.
The state machine asserts ADV # after clock edge N =
I where the 28F016XS-15s will clock in the first addressat the next rising clock edge (N = 2), if CS# is
asserted. If CS # is not asserted, the state machine will
return to its inactive state at N = 2.
The state machine deactivates ADV # at N = 2. The
state machine then asserts ADV # at N = 3 to load the
next read address into the 28FO 16XS-15s. De-asserting
ADV # for one clock cycle (at N = 2, 4, 6 and 8)
between accesses forces the 28F016XS-15s to hold data
output for two clock cycles (access stretching), which
allows time for the data to stabilize and meet the timing
requirements of the i960 JF microprocessor bus.
3-212
The counter increments the two lower bits of the address at N = 3, 5 and 7 to provide the four successive
burst addresses. The state machine asserts OE# (to
meet timing requirements OE# is falling-edge triggered) on the falling edge between N = 4 and N = 5
to enable the 28F016XS-15 data output buffers. With
the SFI Configuration = 4, the data will be valid at the
i960 IF microprocessor data inputs at N = 7.
The state machine asserts RDYRCV # to inform the
i960 JF microprocessor that the data is valid.
RDYRCV# is returned active at N = 7,9, 11 and 12.
The interface will follow this methodology until the
processor asserts BLAST #, which identifies the end of
the burst transaction. BLAST # is examined at N = 7,
9, II and 13. The interface will transition to its inactive
state, SO, after the assertion of BLAST # .
28F016XS/i960® Interface
Optimized Configuration
Figure 15 illustrates a four double-word burst read with
the 28F016XS-15s and state machine configured for optimum read performance. With the SFI Configuration
= 2, ADV # is held active and the counter increments
at N = 2, 3 and 4, supplying the 28F016XS-15s with
four consecutive accesses. Data from the initial access
will be valid for transfer at N = 5. Subsequent data
will be valid at N = 6, 7 and 8. This interface and
28F016XS-15 configuration improve read wait-state
performance to 3-0-0-0. All other signal monitoring
and generation are identical to the reset/power-up configuration read cycle documented in the preceding section.
DI+~
I...-l_,..-___,..-___,..-__~,.._--~'X
1+1
'X
I
1+2
'X
I
1+3
'XXXXXXXXIC~1lXl1nD
I
,xxxxxxxx/\JOOIt~~
~---~---~---~--~~--~~--~,..---~,
,
.!
~
ROYRCV#
~
1+1
~
1+2
~
,'\
1+3
'r--
~--._---._---r_---~I
297500-15
Figure 15. Example Four Double-Word Burst Read illustrating
Important Timing Parameters Requiring Consideration
3-213
28F016XS1I960® Interface
Critical Timings
Table 4 describes the critical timings illustrated in Figures 14 and 15. One particularly critical timing in this
design is the data hold time, which the 28F016XS-15
meets with 0 ns margin. The 28F016XS holds data for
5 ns after a rising clock.
The 28F016XS-15 will provide data 10 ns before the
rising edge of the system clock, which satisfies the i960
IF-33 microprocessor's data input requirement.
ADV# and CTRI-O are guaranteed valid 8 ns after the
rising clock edge. Setup times for these inputs to
28F016XS-15 are each 15 ns. Since the clock period is
30 ns, this allows 7 ns margin for these timings.
RDYRCV # is guaranteed valid 8 ns after the rising
clock edge to met the microprocessor's setup time to
rising clock edge.
Consult the appropriate datasheets for full timing information.
Table 4. Example Write Cycle Timing Parameters at 5Y Yee
Part
85C22V10-15
28F016XS-15
Parameter
Symbol
9
tsU1
Input Setup Time to ClK
tELCH
CE # Setup to ClK
25
tVLCH
ADV # Setup to ClK
15
tAvCH
Address Setup to ClK
15
tGLCH
DE # Setup to ClK
15
NOTE:
Consult appropriate datasheets for up-tO-date specifications.
3-214
Minimum Specified
Yalue(ns)
28F016XS/i960® Interface
Write Configuration
3.4 Burst Write Cycle Description at
33 MHz
Figure 17 illustrates a two double-word burst write cycle. The i960 JF microprocessor initiates a write cycle
by asserting ADS # with W/R # = I and presenting a
valid address and control signals. At N = I with
ADS# = 0, the two-bit counter loads the values on the
address bits A3-2. The state machine asserts WE# (to
meet timing requirements, WE# is falling-edge triggered) on the falling edge between N = I and N = 2.
WE# remains asserted for four clock periods, in order
to meet 28F016XS-15 timing requirements. The state
machine asserts RDYRCV # for N = 4 to inform the
i960 JF microprocessor to supply the next data. At N
= 4, the counter increments the two lower address bits,
and the state machine asserts WE# on the next falling
clock edge to begin the next data write to the
28F0l6XS-15s. The data writes continue until the processor asserts BLAST#, noting the end of the current
write transaction. The SFI Configuration has no effect
on the write cycle.
297500-16
Figure 16. Write State Diagram of Burst Control
Interface Shown In Figure 12
CLK
(33MHz)
WIR.
'--.J.J
I
AOSt
~.ISU1.'
I
I
I
1\
BLAST.
IIOVWH
XXXXX
Address
X
I
I
tw~H-D-X----------~------~IWHDX
I
I
X
DJ
,;----
-!.t ...............
,
I.law..:
A 3-2
XXXXX
X
1
,~
X
1+1
-
ValklAddress
cSt
AOV.
DE.
WE.
I
I
~ELrL
I
I
I
I .... IWHEH
~
I
I
I
I
If
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
'-.1
~twH'~ I
I
I
I X
I X
J+l
-.______.,J~--~.-------~-----.,~~~~.-------~-----.~-----~J
~IAItwL
I
T12
RDYRCV.
I
I
'IWLWH
[XXX
----..1'5::
rJA,VWL
I
...............
X
[XX [XX
'
OJ +1
I
Tll,.-__-,...______..,...,
•
\I~I.----.,.:'r
..J'V
-
I \
I
I ;---'-----,i~
297500-17
Figure ,17. Two Double-Word Burst Write
3-215
28F016XSli960® Interface
Critical Timings
Consult the appropriate datasheets for full timing information.
Table 5 describes the critical timings illustrated in Figure 17.
Notice that CTR1_O, and CS# must be valid before
WE# is asserted. CTR1-O are guaranteed valid 8 ns
after the rising clock edge, providing 12 ns of margin.
Table 5. Example Write Cycle Timing Parameters at 5V Vee
Part
Symbol
Parameter
Input Setup Time to CLK
9
tELWL
CE # Setup to WE # Going Low
0
tAVWL
Address Setup to WE # Going Low
0
tWLWH
WE # Pulse Width
50
tDVWH
Data Setup to WE # Going High
50
85C22V10-15
tSU1
28F016XS-15
tWHDX
Data Hold from WE# High
0
tWHAX
Address Hold from WE # High
5
tWHEH
CE # Hold from WE # High
5
NOTES:
Consult appropriate datasheets for up-to-date specifications.
3-216
Minimum Specified
Value (ns)
28F016XS/i960® Interface
4.0 i960 KB-25 MICROPROCESSOR INTERFACE
LAD,s.()
JDO,s.()
LAD3''()
4 Octal
~~ Latches
~or
..
196o®KB
Processor
Chip
Select
Decode
Logic CSII
LE
n.
lA~
I
CEO II
OV_ CE1#
ClK
r
--
OA2'-4
l
OA,""
..:...
LAD3-2
ALEII
ADSII
State
Machine
and Burst
Counter
W/RII
D015-0
OEII
WEll
CTR
CTR: ~
ADVII ~
28F016XS
A20-3
Vpp'
OEII
WEll
BYTEII
WPII
Ao
A2
A,
ADVII
RY/BYII
RPII
Switched
.... 5Vor
12V
.... 5V
~
GPIO
OV
~
tNT
RESETII
~
...
READYII
CLK2 f+--50MHZ
RESET ~ RESET
CFG25MHz~CLK
I
RESET
B5C22Vl0-15
297500-18
Figure 18. Minimal Logic Required in Interfacing 28F016XS-20 to the
1960 KB·25 Microprocessor
Using this interface, the 28FOI6XS-20/i960 KB-25 microprocessor system can achieve 3-0-0-0 wait state read
performance (5-1-1-1 read performance) in terms of the
CPU's internal 25 MHz CLK, supporting burst cycles_
This design operates the logic and 28F016XS-20s at
25 MHz_
4.1 Circuit Description
This interface uses two 28F016XS-20s to match the
32-bit data bus of the i960 KB microprocessor, providing access to 4 Mbytes of flash memory_Like the
28F016XS-20 interface to the i960 JF microprocessor,
four octal latches de-multiples the 32-bit address from
the LAD bus_ The latches are enabled by an inverted
ALE# signal from the microprocessor_ The latched address and two-bit counter integrated into the PLD select locations with the flash memory space_ The two-bit
counter loads the address bits on LAD3_2 at the beginning of each memory cycle, and generates the lower
two bits of the burst addresses on its outputs CTR 1-0-
CLK Option
In this interface, a 50 MHz clock signal drives the i960
KB microprocessor CLK2 input, and an external
25 MHz clock signal, synchronized to the i960 KB microprocessor internal 25 MHz clock, drives the CLK
inputs for the 28F016XS-20s and the PLD_ The reduced clocking frequency places a less stringent demand on the PLD to meet setup times, thereby aHowing the usage of a slower PLD_
External 25 MHz CLK generation and synchronization
can be accomplished using simple flip-flop logic_ The
i960 KB microprocessor synchronizes its internal
25 MHz dock on the falling edge of RESET_
Two different methods for generating a 25 MHz CLK
are illustrated in Figure 19, and the PLD equations are
located in the Appendix A.
3-217
28F016XS/i960® Interface
The two IX clock generation methods in Figure 19 will
produce a different amount of clock skew between the
2x and lx CLK. Clock generation method (A) will have
2xCLK
l
2xCLKlnput
to Processor
a maximum skew of Teo!> while method (B) will have
little to no clock skew because the 2x and lx CLKs are
exposed to the same PLD delay (see Figure 20).
4xCLK
l
r-EPLD
EPLD
-'---+ 1x CLK
2x CLK Input
to Processor
1---+ 1xCLK
RESET _ _
RESET_
(A)
(8)
297500-19
Figure 19. Example 1x eLK Generation and Synchronization Circuitry
2XC~
L
!cOl
lX~,
'<---I-----,-----:-,'1
',---I_
: Configuration (A) Skew:
(Skew =!cOl )
H
'!col
2XC~
lXC~
,I
'I
'I
: 1
'I
: 1
Configuration (8) Skew
(Skew = 0)
L
297500-20
Figure 20. CLK Skew Produced by the Two DlfferentCLK Generation Methods Illustrated In Figure 19
3-218
28F016XS/i960® Interface
4.2 Software Interface
Considerations
Boot·up Capability
This interface supports processor boot-up from the
28F016XS-20 memory space after power-up or reset.
Burst reads and writes may commence with no configuration. However, read wait-state performance will be
5-0-2-0 until the SF! Configuration is set to 2 and the
CFG input is set to logic "I." Thereafter, burst transfers will improve to 3-0-0-0 wait state perform-
ance. Program control should jump to an area of RAM
to execute the configuration sequence. The code must
set the SF! Configuration to 2 before setting the CFG
input to logic "I."
4.3 Read Burst Cycle Description at
25 MHz
Refer to the read cycle timing diagrams and the state
diagram (Figure 21) for the following discussion of the
read cycle.
297500-21
Figure 21. Read State Diagram of Burst Control Interface Logic Shown in Figure 18
3-219
28F01.6XS/i960® Interface
,
,
~
3
,
,
-: ~,--,--------,",:)OOQOOC)OOOO¢OO
:
:
:
:
:
: >OOOO6OOOOO<
: >OOOO6OOOOO<
_ _ _..........M.'ELCH
CSt
CFG
----~~~~~~~~~--~--~--~--~--~--~--~--~!
---",",,",~,
,
'\'--'-__.J..J!
'\
_ _ _..I...../I4--+J'VLCH
ADV.
OE'
WE'
"GLCH'
\\.._"'--_--'-,-'/~
---~-~---'---~~~\..~_~~_~_'V_~_H~'
__~__~_~__~'u'-~--\.,
./
I
I
!
____~:.~j
~~~Hj+" --j-+:~--~--~r-~----~--~--~----L---~r--L---,~---'-'-'~"----'-_-u:x
+
X'--;-,.,,--'-_
j 3 :
_ _ _.!-_---!_ _-'-_ _.!-_---!_ _- ' - - {
......t12
READY'
-,-~I
\\..-,-, _ _
'
,
't
:
., .... 11
I
\\.._'--_-'---'1
297500-22
Figure 22. Example Four Double-Word Burst Read in Initial Configuration Showing Key
Specifications Requiring Consideration
Initial Configuration
Figure 22 illustrates a four double-word burst read cycle with the 28F016XS-20s and state machine in the
reset/power-up configuration state. The i960 KB microprocessor initiates a read cycle by asserting ADS#
with W /R # = "0," presenting valid address and control signals.
At N = I, the two-bit counter loads the values on
address bits A3.2. The state machine asserts ADV # at
the next clock edge (N = 2), where 28F016XS-20 will
latch in the address if CS # is asserted. If CS # is not
asserted, the state machine will return to its inactive
state at N = 2. The counter increments the two lower
bits of the address at N = 2 and ADV # remains asserted so that the 28F016XS-20 clocks in the first two
burst addresses at N = 2 and 3.
With the SFI Configuration = 4, the state machine
must wait 4 clock periods between loading two even or
two odd addresses into 28FOI6XS-20. Therefore, the
state machine asserts ADV# at N=6 and N=7 to
latch the third and fourth addresses, respectively,
3-220
into 28FOI6XS-20. The state machine asserts OE# (to
meet timing requirements OE# is falling-edge triggered) on the falling edge between N = 4 and N = 5
to enable the 28F016XS-20 data output buffers. Data
will be valid at the i960 KB microprocessor data inputs
at N = 7.
The state machine asserts READY # to inform the
i960 KB microprocessor that the data is valid. To compensate for the delayed third and fourth burst addresses, the state machine must de-assert READY# for N
third and fourth addresses, respectively, N=9 and
N= 10 before again asserting READY# for N= 11
and N= 12, when the third and fourth data, respectively, become valid.
.
The i960 KB microprocessor encodes the length of the
burst transfer onto the two lowest bits of the initial
address. Therefore, the state machine decodes QAD1-O
to determine the end of the burst transfer. At this point,
the state machine will return to its inactive state, SO,
de-asserting OE# to tri-state the 28FOI6XS-20's data
outputs.
28F016XS/i960® Interface
CLK
(2SMHz)
ADS#
LADs,-o
LADs'2
QA 21-4
OA,-o
CS#
CFG
~
,
--
,
--
~
,
- -
,
I~
xxxxxxxmx
xxxxxxxmx :
:
: ~:
: : 1"fu7:
:~
:~
vaJkI:Mdress
3
\
ADV#
/1-'
''vLCH I
1-,
'vLCH '
'GLCH'
\1+-+
OE.
I
1
1
WE'
1
,
~
:XCX
CTR1-o
j+1
,X
1+2
:X
1+3
,
~Ir
T121
\18,
READY#
297500-23
Figure 23. Example Four Double-Word Burst Read Illustrating
Key Specifications Requiring Consideration
Optimized Configuration
Figure 23 illustrates a four double-word burst read with
the 28F016XS-20s and state machine configured for optimum read performance. With the SFI Configuration
= 2, 28F016XS-20 can accept addresses with only two
clock periods between each even address and two clock
periods between each odd address. Therefore, the four
burst addresses flow into SFI on successive rising clock
edges and the four data become valid for transfer on
successive rising clock edges with the first data valid by
N = 5. Otherwise, the transaction is similar to the
reset/power-up configuration read cycle.
Critical Timings
Table 6 describes the critical timings illustrated in Figures 22 and 23. One particularly critical timing in this
design is the data hold time. The i960 KB-25 microprocessor requires a 5 ns hold time' after the clock edge.
The 28F016XS-20 guarantees a 5 ns data hold after
clock, meeting the setup requirement with 0 ns of margin. This design provides:
1/25 MHz - tlO
=
7 ns
of margin to meeting the 3 ns setup time of the i960
KB-25 microprocessor data inputs.
Another critical area concerns CS# and QA21-4 setup
time to 28FOI6XS-20. This design allows two clock periods (80 ns) for these signals to stabilize and meet the
28F016XS-20 setup time. Since the i960 KB-25 microprocessor guarantees ALE# and ,LAD31_0 18 ns after
the rising clock edge and the 28F016XS-20 setup time
is 30 ns, this leaves:
2*1/25 MHz - t6 - tELCH
=
32 ns
for the propagation delays of the inverter plus the latch
plus the chip select decode logic (if applicable, for
CS#).
3-221
28F016XS/i960® Interface
.-
READY # is guaranteed valid 8 ns after the falling
clock edge, providing 5 ns of margin on the 7 ns setup.
required by the i960 KB-25 microprocessor.
n+'eI®
_I
Consult the appropriate datasheets for full timing information.
OE# is also guaranteed valid 8 ns after the falling
clock edge, providing 0 ns of margin on the 12 ns setup
requirement.
Table 6. Example Read Burst Cycle Timing Parameters at 5V Vee
Part
Symbol
Parameter
Minimum Specified
Value (ns)
85C22V10-15
tSU1
Input Setup Time to CLK
9
i960 KB-25 Microprocessor
T10
Input Setup 1
3
T11
Input Hold
5
T12
Input Setup 2
7
tELCH
CE # Setup to CLK
30
tVLCH
ADV # Setup to CLK
20
tAVCH
Address Setup to CLK
20
tGLCH
OE # Setup to CLK
20
28F016XS~20
3·222
28F016XS/i960® Interface
4.4 Write Burst Cycle Configuration at 25 MHz
297500-24
Figure 24. Write State Diagram of Burst Control Interface Logic in Figure 18
3·223
28F016XS/i960® Interface
CLK
(25MHz)
ADS.
W/R,
~I.ISUI~:
~A~
-~
LAD:!-2
~
=x
J
i
i
X
i
i
IOVWH
IjNHDX
i
X
OJ
x
i
i
i
i
i
i
OJ +1
.,.............
X
~
J, lJ,.lJ,J,J,
~i~
-
................
J,J,J,[J,J,
1
IELWL
CSt
i
i
i
i
\'
i
~i
i
i
i
i
i
I. i~L
ADV,
OE#
i
WE'
cTR,.o
\
IWLWH
i
~
X i
'"I,
X
~_ _ _"""'_ _ _L-_ _--""'----,
READYI/
i
itwHAX\
...;.j'
T120 T11
~UI'·
.,
-X
_
_-
1.1
. . .'L-_ _- - " _ - - .
til
i
i.
\I.......I._-JI
297500-25
Figure 25. Example Two Double-Word Burst Write Showing Key Timing Parameters Requiring
Consideration
Write Considerations
The i960 KB microprocessor initiates a write cycle by
asserting ADS# with W!R# = 1 and presenting a
valid address and control signals. At N = 1 with
. ADS# = 0, the two-bit counter loads the values on the
address bits LAD3_2' The state machine asserts WE#
(to meet timing requirements, WE# is falling-edge triggered) on the falling edge between N = 1 and N = 2.
WE# remains asserted for two clock periods, in order
to meet the 28F016XS-20 timing requirements. The
state machine asserts READY # for N = 4 to inform
the i960 KB microprocessor to supply the next data. At
N = 4, the counter increments the two lower address
bits, and the state machine asserts WE# on the next
falling clock edge to begin the next data write to the
28FOI6XS-20s. The data writes continue until the burst
cycle is complete. The state machine determines the
length of the burst cycle by decoding QADI-O. The
28F016XS-20 Configuration has no effect on the write
cycle.
3-224
Critical Timings
Table 7 describes the critical timings illustrated in Figure 25.
One critical hold time to notice is twHAX' WE# is
guaranteed to transition with 8 ns from the falling clock
edge. Therefore, the tWHAX requirement. has 7 ns of
margin on CTRI-O and 9 ns of margin on A31-4.
Also notice that CTRI-O must be valid before WE# is
asserted. CTRI-O are guaranteed valid 8 ns after the
rising clock edge, providing 12 ns of margin.
'Consult the appropriate datasheets for full timing information.
.
28F016XS/i960® Interface
Table 7. Example Write Burst Cycle Timing Parameters at 5V Vee
Part
Symbol
Parameter
Minimum Specified
Value (ns)
85C22V10-15
tSU1
Input Setup Time to ClK
9
i960 KB-25
Microprocessor
T11
Input Hold
5
28F016XS-20
T12
Input Setup 2
7
tELWL
CE # Setup to WE # Going low
0
tAVWL
Address Setup to WE # GOing low
0
tWLWH
WE # Pulse Width
50
tovwH
Data Setup to WE # Going High
50
tWHOX
Data Hold from WE # High
0
tWHAX
Address Hold from WE # High
5
tWHEH
CE # Hold from WE # High
5
5.0 INTERFACING TO OTHER i960
MICROPROCESSORS
i960@CF-16, i960@CF-25 and i960@CF-33
Microprocessors
The i960 CF microprocessor bus interface is completely
compatible with the i960 CA microprocessor bus interface. Therefore, the 28F016XS-15 interfaces described
above for the i960 CA-33 microprocessor work equally
well with the i960 CF-25 and 33 MHz microprocessors.
At 16 MHz, the interface requires a slight modification
because the SF! Configuration value at 16 MHz equals
1. The 28F016XS-15 will begin driving the data pin 1
CLK period after initiating a read access. The interface
returns READY# to the i960 CF-16 microprocessor, 1
CLK cycle earlier. Therefore, the 28F016XS-15 interface to the i960 CF-16 microprocessor will deliver
3-0-0-0 wait-state read performance.
i960@ SA Microprocessor, i960@ SB Microprocessor
The 28F016XS's interface to the i960@ Sx microprocessor series will be similar to the i960 KB microprocessor
interfaces, with the following differences:
• The i960 Sx microprocessor series has II: 16-bit data
bus multiplexed with the lower 16 of 32 IuIdress bits.
Therefore,. a single 28F016XS will match the width
of the data bus.
• Two octal latches will de-multiplex the address/data
bus, and the ALE signal, without inversion, will
properly enable the latches.
• The i960 Sx microprocessor series supports eight
double-word burst transfers. Therefore, the
28F016XS interface will require a three-bit counter
to generate the lower three bits of the burst addresses.
• The interface state machine must use the i960 Sx
microprocessor BLAST # signal to recognize the
end of a burst cycle (see the i960 CA microprocessor
state diagrams).
6.0 CONCLUSION
This technical paper has described the interface between the 28F016XS 16-Mbit Flash memory component and the i960 microprocessor family. This simple
design has been implemented with a minimal number of
components and achieves exceptional read perfonnance. The 28FO 16XS provides the microprocessor with
the non-volatility and update ability of flash memory
and the perfonnance of DRAM. For further infonnation about 28F016XS, consult reference documentation
for a more comprehensive understanding of device capabilities and design techniques. Please contact your
local Intel or distribution sales office for more information on Intel's flash memory products.
3-225
28F016XS/I960@ Interface
ADDITIONAL INFORMATION
Order Number
290532
297500
Document/Tools
28F016XS Datasheet
"Interfacing 28F016XS to the Intel486TM MicroproCessor Family"
,
292147
AP-39E!, "Designing with the 28F016XS"
292146
AP-600, "Performance Benefits and Power/Energy Savings of 28F016XS
Based System Designs"
297372
16-Mbit Flash Product Family User's Manual,
28F016SA/28F016SV/28F016XS/28F016XD
297508
FlashBuilder Utility
Contact Intel/Distribution
Sales Office
28F016XS Benchmark Utility
Contact Intel/Distribution
Sales Office
28F016XS iBIS Models
Contact Intel/Distribution
Sales Office
28F016XS VHDLlVeriiog Models
Contact Intel/Distribution
Sales Office
28F016XS Timing Designer Library Files
Contact Intel/Distribution
Sales Office
28F016XS Oread and ViewLogic Schematic Symbols
--
REVISION HISTORY
Description
Original Version
3-226
28F016XS/1960® Interface
APPENDIX A
PLD FILES
PLD File for the 28F016xs Interface to the i960 CA-33 Microprocessor
Title
Pattern
Revision
Authors
Company
Date
CHIP
; inputs
PIN 1
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN 25
; outputs
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
28FOl6XSI i960 CA Microprocessor Interface Slate Machine
PDS
1
Example
Intel Corporation - Folsom. California
1-25-94
STATEMACHINE
8SC22VIO
CLK.
ADS_n
W_R_n
BLAST_n
CS_n
CFG
A2
A3
RESET
GLOBAL
; address status - i960 CA microprocessor
; WIRtI - i960 CA microprocessor
; burst last - i960 CA microprocessor
; chip select - 28FOI6XS
; 28FOI6XSIi960 CA microprocessor contig status set input
; LAD bit 2
; LAD bit 3
; resets all Ws in device
; virtual pin to implement reset
CTRO
CTRI
; burst counter out - 28FOI6XS-Al
; burst counter out - 28FOI6XS-A2
; write enable - 28F016XS
; output enable - 28RH6XS
; slate variables
/WE
IDE
QO
Ql
IADV
Q3
; burst counter control signals
STRING LD '(/ADS_n)'
STRING INC '(ADV */Ql */QO
+ Q3 * ADV * IQl
+ Q3 */Ql */QO)'
; state variable and address valid - 28FO 16XS
; load
; increment
STATE
MOORE_MACHINE
DEFAULT_BRANCH SO
297500-26
3-227
28F016XS/i960@ Interface
; state assignments
SO
SI =
S2=
S3 =
S4=
S5=
S6=
S7 =
S8=
= IQ3 ·/ADV ·/Ql .IQO
IQ3· ADV ·/Ql , IQO
Q3· ADV·/QI·/QO
Q300 ADV ·/Ql· QO
IQ300 ADV·/QI· QO
IQ3 OO/ADV*/QIOO QO
IQ3OO/ADVOO QIOO/QO
Q3 ·/ADVOO Ql ./QO
Q3 ·/ADVOO/QI·IQO
; state transitions
;REAOcycle
SO:= (/ADS_n"/w_R_n) ·>SI
; WRITE cycle
+ (/ADS_n • W_R_n)
.> S6
; else. stay
+->SO
; 28FO 16XS selected, initial configurations
·>S5
SI := (/CS_n • ICPO)
; 28F016XS selected. 28FOI6XS and i960CA microprocessor configured
·>S2
+ (/CS_n .. CPO)
; else. retum to idle state
+->SO
S2 := VCC
.> S3
S3 := VCC
.> S4
; 28F016XS is configured to wait 4 clocks
S4 := (/BLAST_n • ADS_n) .> SO
; I double word read
+ (/BLASTJI·/ADS_n) .> SI
; pipelinecl read
+-> S5
; else. continue
S5 := (/BLASTJI • ADS_n) .> SO
; bunt read finished
+
(/BLASTJIOO/ADS_n)·> SI
; pipelinecl read
+-> S5
; else. continue
.> S7
; 28FOI6XS selected, continue
+-> SO
; else. return to idle state
S7 := VCC
.> S8
continue bunt
S8 := (BLAST":'n • CFG)
.> S6
pre-config write
+ (BLAST..n • /CPO) .> S8
write is fmished
+->SO
; transition outputs
SO.OUTP :=
10E ./WE
SI.OUTP :=
/oE ·/wE
S2.0UTP :=
OE·/WE
S3.0UTF :=
OE ./WE
S4.0UTF :=
OE ·/wE
S5.0UTF :=
OE ./WE
S6.0UTF:=
OE ·/wE
S7.0UTF :=
/OE" WE '
10E· WE
S8.0UTF :=
S9.0UTF :=
10EOO /WE
EQUATIONS
; implement RESET
OLOBAL.RSTF !RESET
=
; implement2-bit bunt counter· registered counter equations
CTRI := (LD • Al) + (ILD • INC • CTRO OO/CTRl)
+ (ILDOO INC OO/CTROOO CTRl) + (ILD • /INC • CTRI)
CTRO := (LD • A2) + (ILD • INC • ICTRO) + (ILD • /INC • CTRO)
; flop OE and WE on falling edge
OE.CLKf. /CLK
WE.CLKF ICLK
=
297500-27
3-228
28F016XS/i960® Interface
PLD File for the 28F016XS Interface to the i960 JF-33 Microprocessor
Title
Pattern
Revision
Authors
Company
Date
CHIP
; inputs
PIN I
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN 25
; outputs
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
28F0l6XSIi960 IF Microprocessor Interface State Machine
POS
1
Example
Intel Corporation - Folsom. California
8-16-94
STATEMACHINE
CLK
ADS
W_R
BLAST
CS
CFG
A2
A3
RESET
GLOBAL
CTRO
CTRl
!WE
IOE
/ROYRCV
QO
Ql
IADV
85C22VIO
; address status - i960 FJ microprocessor
; W/RtI- i960 FJ microprocessor
; burst last - i960 IF microproCessor
; chip setect
; 28F016XSIi960 IF microprocessor config status set input
;Abit2
;Abit3
; resets all FFs in device
; virtual pin to implement reset
; burst counter out - 28FOI6XS-Al
; burst counter out - 28F016XS-A2
; write enable - 28F016XS
; output enable - 28R>16XS
; wait-state control
; state variables
; state variable and address valid - 28FO 16XS
Q3
; burst counter control signals
STRING LO '(lADS)' .
; load
STRING INC '(ADV
+ ROYRCV • Q3 • Ql • QO)' ; increment
STATE
MOORE_MACHINE
DEFAULT_BRANCH SO
297500-28
3-229
28F016XS/i960® Interface
; state assignments
50 = /RDYRCV * IQ3 * IADV * IQI * I~
SI = IRDYRCV * IQ3 * ADV * IQI */~
52 = /RDYRCV * IQ3 * ADV * IQI * ~
53 = IRDYRCV */Q3 * ADV * QI */~
54 = RDYRCV * IQ3 * ADV * QI * ~
55 = RDYRCV */Q3 * IADV * IQl * ~
56 = IRDYRCV */Q3 */ADV * Ql */~
57 = IRDYRCV· 03· ADV */Ql */~
58 = IRDYRCV */Q3 */ADV * Ql * ~
59 = IRDYRCV * Q3 * ADV */Ql * QO
510 = RDYRCV * Q3 */ADV */Ql */~
511= IRDYRCV* Q3* ADV* Ql*/~
S12 = IRDYRCV * Q3 */ADV */Ql * ~
513 = IRDYRCV * Q3 */ADV * QI */~
514 = IRDYRCV * Q3 */ADV * Ql * ~
S15 = RDYRCV * Q3 */ADV * Ql * ~
; state transitions
50:= (lADS ·!W~R)
(/AD5 * W_R)
+
51 :=
+
52:=
53:=
54:=
S5:=
+
+
56:=
57 :=
58:=
S9:=
510:=
+
S11:=
SI2:=
SI3:=
+
SI4:=
51S:=
+
-> SI
-> 513
+->50
(/CS */CFG)
-> 56
(lC5 * CFG)
->S2
+->50
VCC
->53
VCC
->54
(!BLAST * ADS)
->SO
+->S5
!BLAST
->SO
(BLAST· CFG)
->SS
(BLAST */CFG)
-> 512
VCC
->57
->58
VCC
VCC
-> 59
->SI0
VCC
->50
!BLAST
->Sl1
BLA5T
-> S5
VCC
VCC
->55
->SO
CS
->SI4
IC5
VCC
->SIS
BLAST
->S13
->SO
!BLAST
; READ cycle
; WRITE cycle
; else, stay
; 28FOI6XS selected, init configurations
; 28FOI6XS selected. optimized configured
; else, return to idle state
; 28F016X5 is configured to wait 4 clocks
; 1 double word read
; else, continue
; burst read finished
; continue, optimized configuration
; continue, initial configuration
; BLAST - end of the burst read lransaCtion
; write cycle control
; BLAST - end of burst write lransaCtion
; transition outputs
SO.OUTF:=
IOE * !WE
SI.OUTF:=
IOE * !WE
52.0UTF :=
OE * !WE
53.0UTF :=
OE * !WE
54.0UTF :=
OE * !WE
OE • !WE
5S.0UTF :=
S6.0UTF:=
IOE *'!WE
57.0UTF:=
IOE • !WE
S8.0UTF :=
OE * !WE
OE * !WE
S9.0UTF :=
297500-29
3-230
28F016XS1I960® Interface
SlO.OUTF:=
Sll.OUTF:=
S12.0UTF:=
S13.oUTF:=
S14.0UTF:=
SlS.OUTF:=
OE·IWB
OE·/WB
OE·IWB
lOB· WE
lOB· WB
10E·IWE
EQUATIONS
; implement RESET
GLOBAL.RSTF = !RESET
; implement 2-bit bunt counter - registered counter eqllltiona
CTRl := (LO * A3) + (ILO • INC • CTRO */CTRl)
+ (ILO * INC ·/CTRO· CTRl) + (ILD ·/INC • CTRl)
CTRO := (LD • A2) + (ILD • INC • /CTRO) + (ILD • IINC • CTRO)
; flop OE and WE on fallin, edp
OE.CLKF = ICLK
WE.CLKF = ICLK
297500-30
3-231
28F016XS/i960® Interface
PLD File for the 28FOl6XS Interface to the i!l6OKB·25 Microprocessor
Tide
Pat1em
Revision
Authors
Company
Date
CHIP
28F016XS/i!l6O KB Microprocessor Interface State Machine· lSMHz Version
PDS
1
Example
Intel Corporation - Folsom, Califomia
1-18·94
STATEMACHINE
; inputs
PIN ,I
PIN
PIN
PIN
PIN
PIN
PIN
CLK
ADS
QAO
QAI
W_R
CS
CFG
PIN
PIN
PIN
PIN 2S
A2
A3
RESET
GLOBAL
; outputs
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
PIN
85C22VlO
CTRO
CTRI
IDE
/WE
/READY
IADV
fYJ
; address status - i960 KB microprocessor .
; latched LAD bit 0
; latched LAD bit I
; W/R,· i960 KB microprocessor. ~
; chip select· 28F016XS
; 28FOI6XS config status input
; CFG=O => 28FOI6XS config=4 (initial config)
; CFG=I => 28FOI6XS config=2
; LAD bit 2
.
; LAD bit 3
; n:sets all FFs in device
; virtual pin to implement n:set
; burst counter out - 28FOI6XS·AI
; burst counter out - 28FOI6XS-A2
; output enable" 28FOl6XS
; wrile enable - 28FOI6XS
; i960 KB microprocessor
; state n:gis1er and address valid- 28FOI6XS
; stale n:gis1ers
QI
Q2
Q3
; burst counler control signals
STRING LD '(SO • lADS)'
STRING INC '(SI + 52 +S3
+ S9 + SI3 + S16 + SI9)'
; load
; incn:ment
STATE .
MOORE_MACHINE
.DEFAULT..BRANCH SO
; stale assignments
SO = IADV • IQ3 ./Q2 • IQI ./fYJ
SI = ADV ·/Q3· IQ2 ·/QI ./fYJ
S2 = ADV ·/Q3· IQ2 ·/QI • fYJ
S3 = ADV ·/Q3 • IQ2· QI • fYJ
54 = ADV·/Q3*1Q2* Ql·1fYJ
S5 =/ADV */Q3 */Q2 * QI ./fYJ
56 = ADV * Q3 * IQ2 * QI */fYJ
S7 = IADV *1Q3 */Q2 • IQI • fYJ
S8 =/ADV * IQ3· Q2 * QI * fYJ
297500-31
3-232
28F016XS/i960® Interface
59 = ADV */Q3 * Q2 * QI * QO
510 = ADV */Q3 * Q2 * QI */QO
Sl1 = IADV * Q3 */Q2 */QI */QO
512 = IADV * Q3 */Q2 */Ql * QO
513 =/ADV * Q3*/Q2* QI* QO.
SI4=/ADV* Q3*/Q2* QI*/QO
51S =/ADV * Q3 * Q2 * QI */QO
516=/ADV* Q3* Q2* Ql* QO
517 =/ADV * Q3 * Q2 */QI * QO
518 = ADV * Q3 * Q2 */QI * QO
519 =/ADV * Q3 * Q2 */QI */QO
520 =/ADV */Q3 * Q2 */QI */QO
521 = ADV*/Q3* Q2*/QI*/QO
522 =/ADV * IQ3 * Q2 */QI * QO
523 =/ADV */Q3 * Q2 * QI */QO
S24=/ADV */Q3 */Q2 * QI* QO
S2S = ADV * Q3 * Q2 * QI */QO
; state transitions
50:= (I AD5 * IW_R_n)
+ (I AD5 • W_R_n)
51 :=
les
S2:=
ICFG
S3 :=
54:=
(/QAI */QAO)
SS :=
+
(/QAI * QAO)
(QAl */eFG)
S6:=
(QAl*/QAO)
S7:=
S8:=
59:=
Sl1 :=
vee
vee
vee
vee
les
vee
SI2:=
S13 := (/QAI */QAO)
vee
vee
SI4:=
SIS :=
SI6:= (/QAI * QAO)
vee
vee
S17 :=
SI8:=
SI9:= (QAl */QAO)
520:=
521 :=
S22:=
523 :=
S24:=
S25:=
vee
vee
vee
vee
vee
vee
-> SI
-> 511
+->50
->S2
+->50
->S24
+->S3
->S4
->SO
+->SS
->SO
->S23
+->S6
->SO
+->S7
-> so
->S9
+->S5
-> SI2
+->50
-> S13
->SO
+-> 514
-> SIS
-> 516
->SO
+-> 517
-> 518
-> S19
-> SO
+->S20
-> S21
->S22
-> SO
->S25
-> S8
->S6
; READ cycle
; WRITE cycle
; else. stay
; continue if 28FOI6X5 is selected
; else. return to idle state
; 28F016XS is configured to wait 4 clocks
; else. continue
; else. continue
; I double word read
; else. continue
; 2 double word burst read
; SFI Configuration = 4
; else. continue
; 3 double word burst read
; else. continue
; 4 double word burst read
; else. continue
; continue if 28FO 16X5 is selected
; else. return to idle state
; I double word write
; else. continue
; 2 double word burst write
; else. continue
; 3 doubie word burst write
; else. continue
; 4 double word burst write
297500-32
3-233
28F016XS1/960® Interface
; transition outputs
SO.OUTF.- /WE - IbE • /READY
S1.0UTF.- /WE -/OE -/READY
S2.0UTF.- /WE -/OE • /READY
S3.0UTF:= /WE - OE -/READY
S4.0UTF.- /WE - OE - READY
SS.OUTF .- . /WE - OE - READY
S6.0UTF.- /WE - OE - READY
S7.0UTF.- /WE - OE - READY
SB.OUTF.- /WE - OE ·/READY
S9.0UTF:= /WE· OE· /READY
SIO.OUTF:= /WE - OE - READY
SII.OUTF:=
WE ·/OE ·/READY
S12.0UTF :=
WE ·/OE ·/READY
SI3.0UTF:= /WE-/OE- READY
S14.0UTF :=
WE ·/OE -/READY
SIS.OUTF:=
WE -/OE -/READY
S16.0UTF := /WE -/OE - READY
SI7.0UTF:=
WE -/OE -/READY
SIB.OUTF:=
WE -/OE -/READY
S19.0UTF := /WE -/OE - READY
S20.0UTF :=
WE - IOE -/READY
S21.0UTF :=
WE -/OE - /READY
S22.0UTF := /WE -/OE - READY
S23.0UTF := /WE - OE - /READY
S24.0UTF := /WE -/OE - /READY
S2S.0UTF := /WE - OE - /READY
EQUATIONS
; implement RESET
GLOBAL.RSTF = RESET
; implement 2-bit bunt counter - registered counter eq,wions
CTRI := (LD - A3):" (ILD -INC - CTRO -/CTRt)
+ (ILD - INC -/CTRO - CTRl) + (ILD -/INC • CTRt)
CTRO := (LD - A2) + (ILD • INC • ICTRO) + (ILD • IINC • CTRO)
; flop WE. OE. and READY on fallinl edp
WE.CLKF ICLK
OE.CLKF = ICLK
READY.CLKF ICLK
=
=
3-234
297500-33
28F016XS/i960® Interface
PLD File for the 1x CLK Generation and Synchronization
Ix Clock Generations &: Sychronization
Title
Pattern
Revision
Author
Company Name
Date
Example
Intel
5/26/94
; input pins
PIN
PIN
CLK
RESET
; output pins
PIN
SYSCLK
PDS
I
; clk frequency 33MHz
EQUATIONS
SYSCLK := ISYSCLK -!RESET
SYSCLK.CLKF = CLK
297500-34
PLD File for thl 1x and 2x CLK Generation and Synchronization
Title
Pattern
Revision
Author
Company Name
Date
Ix and 2x Clock Generation and Synchronization
PDS
I
Example
Intel
5126194
; input pins
PIN
PIN
CLK
RESET
; clk frequency 4x
; System RESET
; output pins
PIN
PIN
CLK2
SYSCLK
; 2x CLK output
; Sychronized Ix CLK output
EQUATIONS
CLK2 := ICLK2
CLK2.CLKF = CLK
SYSCLK:= CLK2· SYSCLK·!RESET
+ ICLKl • ISYSCLK • !RESET
SYSCLK.CLKF = eLK
297500-35
3-235
28F016XS/i960® Interface
APPENDIX B
BENCHMARK PERFORMANCE ANALYSIS
The following section provides detailed memory technology information used in the performance analysis (UDP/IP
Networking and Imaging Benchmarks) contained in the introduction. The performance analysis was based on actual
memory component performance in an i960 processor-based environment. System interface delay between microprocessor and memory was not included in the analysis. The two be!lchmarks illustrate relative system memory
performance.
A. 28F016XS Flash Memory
28F016XS is capable of 3-1-1-1-1-1-1-1 ... read performance at 5.0V VCC and 33 MHz or 25 MHz (2-0-0-0-0-0-0-0
... in terms of wait states). The benchmarking analysis is shown below:
UDP/IP Networking Benchmark
Imaging Benchmark
Time (sec)
Time (sec)
i960 KB-25
Microprocessor
1.30
1.64
i960 CA-33
Microprocessor
.89
.89
i960 CF-33
Microprocessor
.53
.59
B. 16-Mbit DRAM
16-Mbit DRAMs were, at the time this technical paper was published, only beginning to ramp into produCtion. Only
advance information for the wider x16, 16-Mbit DRAMs was available for use in the calculations that follow.
Sequential reads allow use of the DRAM fast page mode. Assumed DRAM specifications are shown below:
• 80 ns tRAC, 40 ns tAA (5.0V Vcd
• 256 word (512 byte) page buffer
Therefore, 16-Mbit DRAMs are capable of 3-2-2-2-2-2-2-2 ... read performance at 33 MHz and 25 MHz (2-1-1-1-11-1-1 in terms of wait states ... ). The benchmarking analysis is shown below:
3-236
UDP/IP Networking Benchmark
Imaging Benchmar.k
Time (sec)
Time (sec)
i960 KB-25
Microprocessor
1.88
1.89
i960 CA-33
Microprocessor
1.06
1.03
i960 CF-33
Microprocessor
.59
.64
28F016XS/1960® Interface
c. 4-Mbit EPROM
Calculations that follow us~d the x16 version of the 4-Mbit EPROM (Intel 27C400 or equivalent).
The assumed 5.0V Vee 4-Mbit EPROM random access time is 150 ns. Therefore, 4-Mbit EPROMs are capable of 55-5-5-5-5-5-5 ... read performance at 5.0V Vee and 33 MHz (4-4-4-4-4-4-4-4 ... in terms of wait states). The
benchmarking analysis is shown below:
UDP/IP Networking Benchmark
Imaging Benchmark
Time (sec)
Time (sec)
i960 KB-25
Microprocessor
NA
NA
i960CA-33
Microprocessor
1.56
1.49
i960 CF-33
Microprocessor
.78
.81
D. 16-Mbit PAGED MASK ROM
Calculations that follow used the x16 version of the 16-Mbit paged mask ROM, which is not yet widely available
from multiple vendors. The x8, 16-Mbit paged mask ROM is the more common version today.
Sequential reads allow use of the mask ROM page mode. The assumed 5.0V Vee 16-Mbit mask ROM random
acCess time is 150 ns, with 75 ns accesses in page mode (4-word page). Therefore, 16-Mbit mask ROMs are capable
of 5-3-3-3-5-3-3-3 ... read performance at 5.0V Vee and 33 MHz (4-2-2-2-4-2-2-2 ... in terms of wait states). The
benchmarking analysis is shown below:
UDP/IP Networking Benchmark
Imaging Benchmark
Time (sec)
Time (sec)
i960 KB-25
Microprocessor
NA
NA
i960CA-33
Microprocessor
1.35
1.30
i960CF-33
Microprocessor
.71
.73
3-237
infel·
TECHNICAL
PAPER
Interfacing the 28F016XS to
the Intel486™ Microprocessor
Family
KEN MCKEE
TECHNICAL MARKETING
ENGINEER
PHILIP BRACE
APPLICATIONS ENGINEER
December 1994
Order Number: 297504-001 . .
3-238
Interfacing the 28F016XS to the Intel486™
Microprocessor Family
CONTENTS
PAGE
1.0 INTRODUCTION ................... 3-240
2.0 INTERFACE CIRCUITRY
CONTENTS
PAGE
5.0 READ CYCLE CONTROL FOR
SINGLE AND BURST
TRANSACTIONS .................... 3-245
DESCRiPTION ...................... 3-241
6.0 WRITE CYCLE CONTROL . ........ 3-250
3.0 INTERFACING SIGNAL
DEFINITIONS ....................... 3-243
3.1 28F016XS Signal Descriptions ... 3-243
3.2 Intel486TM SX Signal
Descriptions ...................... 3-244
4.0 SYSTEM INTERFACE
7.0 INTERFACING TO OTHER
INTEL486TM
MICROPROCESSORS ............... 3-252
8.0 CONCLUSION ..................... 3-252
ADDITIONAL INFORMATION ......... 3-253
REQUIREMENT ..................... 3-244
REVISION HISTORY .................. 3-253
I
3-239
28FO16XSlintel486™ Interface
1.0 INTRODUCTION
This technical paper describes designs interfacing the
high performance 28F016XS flash memory to the
Inte1486TM microprocessor. These designs are based on
preliminary 28F016XS specifications. Please contact
your Intel or distribution sales office for up-to-date information. Do not finalize a design based on the specifications in this document. These designs have been fully
simulated by not yet taken to lab prototype.
The 28F016XS is a 16-Mbit flash memory with a synchronous pipelined read interface. This enhanced flash
memory interface delivers equivalent or better read performance compared to DRAM. The 28F016XS combines ROM-like non-volatility, DRAM-like read performance and in-system updateability into one memory
technology. These inherent capabilities will improve
performance and lower the over-all system cost of a
burst microprocessor, such as the Intel486 microprocessor based design. The Intel486 microprocessor sees
widespread use in a variety of applications ranging
from the PC to numerous embedded products, while
providing code compatibility with thousands of commercially available software packages and the performance necessary for today's leading-edge systems. The
Intel486 microprocessor's bus interface provides a burst
transfer mechanism whereby four consecutive data
items. are fetched in one access sequence. The
28F016XS's synchronous pipelined read interface
makes special use of the burst transfer mechanism to
achieve extremely high read performance.
When interfacing the 28F016XS to a processor that executes an Intel or linear burst cycle, up to three simultaneous read accesses can be piped into the 28F016XS.
At 33 MHz, the 28F016XS-15 delivers zero wait-state
performance after the initial pipeline fill. This enhanced
3-240
read performance eliminates the costly expense of shadowing code from slow non-volatile memory (ROM,
hard disk drive, etc.) to fast DRAM for increased system performance. The 2,8F016XS enables direct code
execution out of the flash memory array, eliminating
unnecessary software and hardware overhead involved
in shadowing code.
In an Intel486 microprocessor-based environment,
BAPCo benchmarking analysis revealed a 13% system
performance improvement using the 28F016XS-15 over
70 ns DRAM.
In addition to the increased read performance, the
28F016XS offers an Intel486 microprocessor-based system a low power, non-volatile memory that is electrically updateable via local processor control. The
28F016XS's low power consumption reduces system
power dissipation and heat emission, and its updateability increases code flexibility and system reliability.
Combined, the 28F016XS and the Intel486 microprocessor deliver a high performance, low power and costeffective system solution.
The Intel486 interface to the 28F016XS requires minimal logic while offering significant system enhancements. One programmable logic device (PLD), a
85C22VIO-15, generates and monitors all 28F016XS
and Intel486 microprocessor control signals. This technical paper 'explores the· interface between the
28F016XS-15 and the Intel486 SX-33, describing the
interface circuitry, explaining the read and write cycles
and providing the interfacing PLD equations. It also
provides detailed design suggestions for interfacing the
28F016XS to other Intel486 microprocessors.
28F016XSllntel486TM Interface
0,,-0
A31_2
D,>-o
~ r~(:'~~
LOGIC
Intal488TII
n
GNo-i
A2o-3
CEo It
CE1'
28F018XS-15
SX-33
CLK
AD..
WIR.
BLASn
~
33JHZ
••
"1'
CLK
".,
CT....O
ADVII
ACYl
BYTE'
OE.
OE.
RY/BV'
WE.
WE.
WP'
KEN.
INTERFACE
BROV,
~OGIC
ROY'
RESET ....- RESET
-+
Vpp
RESET'--' AP,
5V
+- I- orSVottched
12V
+- I - 5V
-
~ INT
+-
f-
GP10
""7'
(B5=V111-15)
BOFF' . . - BOFF' ---.....
AECONFIG
---+
297504-1
Figure 1. Minimal Glue Logic in Interfacing the 28FO16XS-1511nte1486™ SX-33
2.0
INTERFACE CIRCUITRY
DESCRIPTION
The 28F016XS-15 interface to the Intel486 SX-33 illustrated in Figures I delivers 3-0-0-0 wait-state read performance.
28FOl6XS memory space, arranged as I Meg double
words. The two-bit counter implemented in the PLD
loads addresses A3-2 at the beginning of each memory
cycle and increments through the Intel burst order,
feeding consecutive addresses to the 28FOI6XSs.
Reset
Memory Configuration
This design uses two 28FOI6XS-15s, each configured in
xl6 mode and arranged in parallel to match the Intel486 SX's 32-bit data bus, providing 4 MBytes of flash
memory. Signals A21-4 from the Inte1486 SX and
CTR1_O from the PLD select locations within the
The Intel486 SX requires an active high reset signal,
while the 28FO 16XSs use an active low RESET #. Figure 2 illustrates a suggested logic configuration for generating both an active high and low reset signal. The
active high RESET controls the Inte1486 SX and PLD
RESET inputs, while the active low RESET# drives
the 28FOl6XS RP# input.
3-241
28FO16XSlintel486™ Interface
28F106XS
Vee
I
RP#
Voltage Monitor
RESET#
SYSTEM RESET -
MR#
RESET
~------------~~~.---
RESET#
~------------------ RESET
MAX707
297504-2
Figure 2. RESET Generation Method
Chip Select Logic
Chip select decode logic may use A31-22 to generate
active low chip select signals, CEx#, for the 28F016XS
memory space and other system peripherals. The chip
select addressing the 28F016XS memory space drives
CEo# on each 28F016XS-15 and a control input to the
PLD. The 28F016XS-15s' eEl # inputs are grounded.
For many systems, using the upper address bits in a
linear selection scheme may provide a sufficient number of chip select signals, thus eliminating chip select
decode logic. (See Figure 3 for an example of using
linear selection for chip selects.) When using a linear
chip select scheme however, software must avoid using
addresses that may select more than one device, which
could result in bus contention. For example, addresses
OlOOOOOOH through OlOFFFFFH drive both A22 and
A23 to a logic "0," which inadvertently selects two peripheral devices.
Intel486™
SXCPU
Chip Select
1
2
3
A22 -
Chip Select 1
A 23 -
Chip Select 2
A24 -
Chip Select 3
Address Space
01800000 - 01 BFFFFF H
01400000 - 017FFFFF H
OOCOOOOO - OOFFFFFF H
297504-3
Figure 3. Example of Using Linear Chip Selection
with Active Low Chip Select Signals
3-242
28FO16XSlintel486™ Interface
CLKOption
3.0
A 33 MHz CLK drives the Inte1486 SX, the PLD and
the 28FOI6XS-ISs. Position the PLD and the
28FOI6XS-ISs within close proximity to the microprocessor to minimize CLK skew between CPU, interface logic and flush memory components.
The interface logic that controls the 28FOI6XS-IS
Intel486 SX-33 interface monitors and regulates specific signals. The next two sections describe these signals.
Interface Control Signals
3.1 28F016XS Signal Descriptions
The interfacing state machine monitors the Intel486
SX's external bus signals to control the two-bit counter
and generate OE#, WE# and ADV # signals to the
28FOI6XS-ISs. At the beginning of the burst cycle, the
interface logic loads the two-bit counter and generates
burst addresses to the 28FOI6XS-ISs. The state machine also generates KEN #, BRDY # and RDY # signals, informing the Inte1486 SX of the nature of the bus
cycle.
INTERFACING SIGNAL
DEFINITIONS
This section describes the 28FO 16XS signals that are
pertinent to this design.
ADV #- Address Valid (Input)
This active low signal informs the 28FOl6XS that a
valid address is present on its address pins. ADV #, in
conjunction with a rising CLK edge, initiates a read
access to the 28FOI6XS. This signal is ignored during
write operations.
Configuration Signal
A general purpose input/output (GPIO) generates the
configuration signal input to the state machine. The
configuration signal must reset to logic "0" on powerup and system reset to ensure that the operation of the
state machine matches the initial SFI Configuration of
the 28FOI6XS-ISs. After optimizing the SFI Configuration, the GPIO must switch to logic "1." See Section
4 for more information regarding the configuration signal.
CLK-Clock (Input)
CLK provides the fundamental timing and internal operating read frequency for the 28FOI6XS. CLK initiates read accesses (in conjunction with ADV #), times
out the SFI Configuration, and synchronizes device
outputs. CLK can be slowed or stopped with no loss of
data synchronization. This signal, like ADV #, is ignored during write operations.
OE#-Qutput Enable (Input)
Additional 28F016XS Control Signals
The BYTE# input to the 28FOI6XS-ISs is tied to S.OV
to configure the 28FOI6XS-ISs for xl6 mode, and Ao is
tied to GND (Ao is only used for byte addressing). A
GPIO controls the write protect input, WP#, to the
28FOI6XS-ISs. The 28FOl6XS is compatible with either a S.OV or a 12.0V Vpp voltage and is completely
protected from data alteration when Vpp is switched
. below VPPLK. With Vpp s VPPLK, the 28FOl6XS will
not successfully complete Data Write and Erase operations, resulting in absolute flash memory data protection. Figure I also illustrates the 28FOI6XS-IS's RY/
BY # output connecting directly to a system interrupt,
which enables background Write/Erase operations.
RY/BY#, WP#, and Vpp implementations are application dependent. Consult the Additional Information
section of this technical paper for documentation covering these topics in more detail.
This active low signal activates the 28FOI6XS's output
buffers when OE# equals "0". The outputs tri-state
when OE# is driven to "I".
WE#-Write Enable (Input)
This active low signal controls access to the Control
User Interface (CUI), Page Buffers, Data Queue Registers and Address Queue Latches. Addresses (command
or array) and data are latched on the rising edge of
WE# during write cycles, while page buffer addresses
are latched on the falling edge of WE#.
3-243
28FO16XSlintel486™ Interface
3.2 Intel486™ SX Signal Descriptions
BLAST#-Burst Last (Output)
This section describes the Intel486 SX signals that are
relevant to this interface. This interface assumes processor inputs are driven by only one controlling device (the
PLD). If more than one device drives a processor input,
the PLD output should be configured as open drain to
avoid signal contention. Many PLDs, FPGAs and ASICs provide output configuration capability.
This active low output from the microprocessor signals
the final transfer in a burst cycle. The next time
BRDY # is returned, it will be treated the same as
RDY # and thus terminate any multiple cycle transfers.
AOS#-Address Status (Output)
This active low output signal from the Intel486 SX
processor indicates the presence of valid bus cycle and
address signals on the bus. ADS# is driven in the same
clock as the address signals. Typically, external circuitry uses ADS# to indicate the beginning of a bus cycle.
KEN#-Cache Enable (Input)
This active low input to the Intel486 SX determines
whether data being returned in the current bus cycle
will be cached. In order for the current data to be cached, KEN # must be returned active in the clock prior to
the first RDY# or BRDY# of the cycle and must also
be returned active in the last clock of the data transfer.
ROY #-Non-Burst Ready (Input)
RDY # indicates the completion of the current bus' cycle. During a read, the assertion of RDY # indicates to
the microprocessor that valid data exists on the data
bus. During a write, RDY # indicates that the external
device has accepted the data being supplied by the microprocessor.
4.0
SYSTEM INTERFACE
REQUIREMENT
The system logic controlling the 28FOI6XS-15/Intel486 SX interface has both an initial and an optimized
read configuration, correlating to specific SFI Configuration values. The interface read configuration is dependent upon the value of RECONFIG (PLD input),
which informs the interface of the SFI Configuration
status. Note, the SFI Configuration status does not affect Write operations.
Initial Read Configuration
Upon power-up/reset, the 28F016XS-15 defaults to a
SFI Configuration value of 4, and the interface logic
supports single read accesses to the 28F016XS-15 memory space. The interface returns RDY # to inform the
processor that the interface does not support burst cycles. A general purpose input/output (GPIO) informs
the system interface of the status of the SFI Configuration.
The GPIO, RECONFIG, must be set to logic "0" on
power-up/reset. With RECONFIG driven low, the
state machine correctly matches the 28F016XS-15's default configuration.
BROY #-Burst Ready (Input)
Optimized Read Configuration
This active low input to the microprocessor performs
the same function during a burst cycle as RDY # performs during a non-burst cycle. During a burst cycle,
BRDY # is sampled on the rising edge of every clock.
Upon sampling BRDY # active, the data on the data
bus will be latched into the microprocessor (for burst
reads). ADS# will be negated during the second transfer of the burst cycle; however, the lower address lines
and byte enables may change to indicate the next data
item requested by the processor.
At 33 MHz, the 28F016XS-15 operates at highest performance with a SFI Configuration value set to 2. Reconfiguring the 28FOI6XS-IS, program control should
jump to an area of RAM to execute the configuration
sequence. After reconfiguring the 28F016XS-lS, the
GPIO value must change to logic "I," in order to take
advantage of the 28F016XS-lS's optimized configuration. A pseudocode flow for this configuration sequence
is shown below.
Execute Device Configuration command sequence
Activate RECONFIG signal
End
In the optimized read configuration, the system logic
supports burst cycles by ge~erating BRDY #, which
informs the microprocessor that the memory subsystem
3-244
28F016XS/intel486TM Interface
is capable of handling a burst transfer. The 28FOI6XS15 memory array, when executing burst cycles, transfers data to the processor at a rate of 132 MBytes/sec.
5.0
READ CYCLE CONTROL FOR
SINGLE AND BURST
TRANSACTIONS
At this point, RECONFIG and CE# are examined to
determine the configuration status of the 28FOI6XS15s, and whether or not the current address targets the
28FOl6SX memory space. If CE# = "I," the state
machine returns to an idle state waiting for a new access. In the initial configuration (RECONFIG = "0"),
read control regulates ADV#, RDY# and OE#.
Read Abort Condition
At N = I (Figure 5), the counter loads address bits
A3-2 and transitions ADV # low. With ADV # at logic
"0" the interface initiates a read access to the
28F016XS-15s at N = 2. After initiating the read access, ADV# immediately switches to a logic "I" at N
= 2 and remains at this value throughout the rest of
the access.
A read cycle will abort only when an external system
bus master asserts BOFF #, which forces the processor
to give immediate bus control to the requester. When
this situation occurs, the Intel486 SX floats the address
bus, which will cause the address decode logic to de-select the 28FOl6XS memory space. The interfacing logic, monitoring BOFF #, will transition to an idle state
waiting for the processor to re-initiate the interrupted
bus cycle after the bus master has relinquished the bus
to the processor. OE# is immediately driven high, deactivating the 28FOI6XS-15's output buffers, upon detecting BOFF# driven active. This BOFF# condition
can occur in both the initial and optimized configurations de~cribed in the paragraphs that follow.
In the default SFI Configuration (SFI Configuration =
4), data will be accessible to the processor at N = 7.
The 28FOI6XS-15's output buffers are enabled at N =
4 and RDY # is driven low at N = 6. The processor
will sample ROY # active and latch the information
residing on the data bus at N = 7, marking the completion of the read access. The Intel486 SX requires a 3 ns
hold time after sampling ROY # active, therefore, the
state machine transitions to a state where it holds OE#
active to force the 28F016XS-15s to hold the data on
their output pins. At N = 8, the state machine transitions to an idle state where it deactivates OE# and
waits for the Intel486 SX to initiate a new bus cycle
targeting the 28FOl6XS memory space.
The read state machine (Figure 4) performs one of two
different read cycles, initial or optimized configuration,
depending upon the RECONFIG input value.
Initial Configuration
Initial Configuration Timing Consideration
Refer to Figures 4 and 5 for the following read cycle
discussion.
With RECONFIG set to logic "0," the interfacing read
state machine executes single non-cacheable read cycles. This configuration occurs upon power-up and reset.
The microprocessor initiates a read access to the
28F016XS memory space by providing an address,
driving W/R# low and activating ADS#. Monitoring
the external bus of the Intel486 SX, the state machine
transitions into read control.
If ADS# = 0 and W/R#
READ CONTROL
In the initial read configuration, CE# setup is a key
system timing parameter.
To satisfy the 28F016XS-15 setup requirement, CE#
must be valid 25 ns prior to the first rising CLK edge
with ADV# = "0." Therefore, the maximum time allotted for the address decoding logic to generate CE#
equals:
2·1/33 MHz - t6 - tELCH
=
19 ns
Consult the appropriate datasheets for full timing information.
o then
3-245
28F016XS/intel486TM Interface
297504-4
Figure 4. State Diagram of Single and Burst Read Control
(Interface Shown in Figure 1)
3-246
28F016X5/1ntel486TM Interface
N=O
'N=1
N=2
N=3
N=4
N=5
N=6
N=7
N=8
-ILILIL
L L L LLIL
f--i
ClK
-
ADS#
~
I~
/
HI.
'-
A<31:4>
VIJj
\
t ELCH
CE#
ADV#
i-Ilpzx
~Ipzx
~
Ifj
~
:*i Ipzx
r
f-ilpzx
~
OE#
~tpzx
CTR<1: 0>
~ tl.
~
t:-t Ipzx Hlpzx
Ifj
~
RDY#'
I CHQV
~
Wf
Data
t
1--1
297504-5
Figure 5. Example Non-Burst Read Cycle Showing
Key Timing Specifications Requiring Consideration
Table 1. Example Initial Read Cycle Timing Specifications at 5V Vee
Symbol
Min
Max
Unit
fa
ADS# Delay (Inte1486™ SX-33)
Description
3
16
ns
t16
ROY # Setup Time (Inte1486™ SX-33)
5
ns
t22
031-0 Setup Time (Inte1486™ SX-33)
5
ns
tELCH
CEx# Setup Time to ClK (28F016XS-15)
25
ns
tVLCH
ADV # Setup Time to ClK (28F016XS-15)
15
ns
tGLCH
OE# Setup Time to ClK (28F016XS-15)
15
tCHQV
ClK to Data Delay (28F016XS-15)
tpzx
ClK Output Delay (85C22V1 0-15)
2
ns
20
ns
8
ns
NOTE:
Consult appropriate datasheets for up·to-date specifications.
3-247
28FO16XSllntel486™ Interface
Optimized Configuration
Refer to Figures 4 and 6 for the following discussion:
With the 28F016XS-15s in the optimized configuration
(SFI Configuration = 2 at 33 MHz), and RECONFIG
set to a logic "I" value, the system interface executes
cacheable burst cycles.
The Intel486 SX processor drives ADS# low, notifying
the interface logic that a valid address is on the address
bus. Monitoring the external bus of the Intel486 SX,
the state machine then transitions into read control.
If ADS# = 0 and W/R# = 0 then
READ CONTROL
In optimized read control, the state machine drives
OE#, KEN# and BRDY#. IfCE# = "0," the state
machine at N = I loads the two-bit counter (A3-2)
and activates ADV # (ADV # = "0") for the next four
consecutive clock periods (N = I through 5). While
ADV # is driven low, the counter increments through
the Intel burst order (Table 2), supplying the
28F016XS-15s with a new address at N = 2, 3, 4 and
5. If CE# = "I," the state machine returns to an idle
state waiting for a new memory access.
At N = 3, the state machine drives KEN # active and
holds it active until the end of the burst cycle, thereby
executing a cache line fill.
The state machine activates the 28F016XS-15 output
buffers (OE# driven to a logic "0" value) at N = 3
and holds them active throughout the burst read cycle.
With the SFI Configuration value set to 2, new data
will be available on the 28FO 16XS-15 output pins at
N = 5,6,7 and 8. Driving BRDY# low at N = 4, the
Intel486 SX microprocessor will sample BRDY # active at N = 5, which informs the processor of valid
information on data pins D31-0 and that the 28FOl6XS
memory space supports a burst read transfer. BRDY#
is held low until the end of the burst cycle while the
processor retrieves data on every rising clock edge.
BRDY# is driven high upon sampling BLAST# low,
marking the end of the burst cycle.
The Intel486 SX requires a 3 ns hold time after sampling the last BRDY # active in a burst cycle. Therefore, the state machine transitions to a state where it
holds OE# active, which forces the 28F016XS-15s to
hold the data on their output pins. At N = 9, the state
machine transitions to an idle state, where it deactivates
OE# and waits for the Intel486 SX to initiate a new
bus cycle targeting the 28F016XS memory space.
Table 2. Intel Burst Order (A3-2)
First
Address
Second
Address
Third
Address
Fourth
Address
0
4
8
C
4
0
C
8
8
C
0
4
C
8
4
0
3-248
Optimized Configuration Timing Considerations
In the optimized configuration, CE# setup time is
again a key system timing parameter. For information
regarding the CE# setup time requirement, see the Initial Configuration Timing Considerations Timing section.
28FO16XSllntel486™ Interface
CLK
~ ~ iLiL~ ~ ~ ~ ~ I
-
f---I t.
-
~
ADS
L..../t.
Addres s -
Wi
r
---oi t "
'fJtfJ..
BLAST#
t ElCH
-
'------<
\
CE#
/
_tpzx
--Itpzx
'ff:A
ADV
~
tfIJ
ytpzx
'ff:A
KEN#
yt"zx
tPZX(mil
'ff:A
OE#
CR<1: 0>
~ ru=- ~ ru=- r;i
~tpZl
f--Lt pzx
tfIJ
'ff:tA
BRDY#
Wi £
Data
'!--
~ £"
297504-6
Figure 6. Example Burst Read Cycle Showing
Key Timing Specifications Requiring Consideration
Table 3. Example Optimized Read Cycle Specifications at 5V Vee
Symbol
Min
Max
Unit
ts
ADS# Delay (Inte1486™ SX-33)
Description
3
16
ns
taa
BLAST# Delay (Inte1486™ SX-33)
3
20
ns
t22
031-0 Setup Time (Inte1486™ SX-33)
5
tELCH
CEx# Setup Time to ClK (28F016XS-15)
25
ns
tVLCH
ADV# Setup Time to ClK (28F016XS-15)
15
ns
tGLCH
OE# Setup Time to ClK (28F016XS-15)
15
tCHQV
ClK to Data Delay (28F016XS-15)
tpzx
ClK Output Delay (85C22V10-15)
2
ns
ns
20
ns
8
ns
NOTE:
Consult appropriate datasheets for up-to-date specifications.
3-249
28F016XS/intel486TM Interface
6.0
WRITE CYCLE CONTROL
Refer to Figures 7 and 8 for the following write cycle
discussion:
Write Abort Condition
A write cycle will abort only when an external system
bus master asserts BOFF#, which forces the processor
to give immediate bus control to the requester. When
this situation occurs, the Inte1486 SX will float the address bus, causing the address decode logic to de-select
the 28FOl6XS memory space. The interfacing logic,
monitoring BOFF#, will transition to an idle state
waiting for the processor to re-initiate the interrupted
bus cycle after the bus master has relinquished the bus
to the processor. WE# is immediately deactivated
upon sensing BOFF# low.
Write Cycle Description
The 28F016XS-15 executes asynchronous write cycles
like traditional flash memory components such as the
28FOI6SA/SV. The SFI Configuration does not influence write operations; therefore, the interfacing state
machine does not examine RECONFIG once detecting
a write cycle.
During the first clock period, the Intel486 SX microprocessor drives ADS# low and W/R# high. The
state machine detects a write cycle, loads the two-bit
counter, activates WE# and transitions to write control at N = 1 (Figure 8). The counter only supplies the
28F016XS-15 with one address. A write transaction
must compete fully before issuing a second write operation.
If ADS# = aand W/R#
WRITE CONTROL
1 then
In write control, the state machine performs WE#Controlled Command Write operations to the
28F016XS-15s. Data is written to the 28F016XS-15
memory space via processor control. The interface only
supports double word writes.
For the next three clock periods, N = 2 through 4, the
state machine holds WE# low to satisfy the
28F016XS-15's WE# active requirement. At N = 4,
WE# transitions to a logic "I," which latches the address and data into the 28FO l6XS-15s.
297504-7
Figure 7. Non-Burst Write State Diagram
Controlling the Interface Shown in Figure 1
ROY # is not returned to the processor at N = 4 because the Intel486 SX will only hold an address 3 ns
after sampling ROY # low. Instead, the interface activates RDY# after N = 4, causing the processor to
hold the address valid for an additional clock cycle,
which satisfies the 28FOI6XS-15's address hold specification (tWHW. The state machine then returns to an
inactive state at N = 5, waiting for a new memory
access.
Write Timing Consideration
When performing a write operation, CE# is a critical
system timing parameter, which must satisfy the interface logic's required setup time. The 85C22VlO-15 requires a 9 ns setup time to CLK. Therefore, the system
decode logic must generate a valid CE# to the interface within:
2 • 1/33 MHz - t6 - tsu = 35 ns
Consult the appropriate datasheets for full timing infor'
mation.
3-250
28F016X5/1ntel486TM Interface
N=O
N=1
N=2
N=3
N=4
N=5
ClK
ADS#
A<31:4>
CE#
CTR
WE#
RDY#
r--r-----+----~----~~
111
Data
297504-8
Figure 8. Example Write Cycle Showing
Key Timing Specifications Requiring Consideration
Table 4. Example Write Cycle Timing Specifications at 5V Vee
Symbol
Min
Max
Unit
ts
ADS# Delay(lntel486™ SX-33)
Description
3
16
ns
t10
Data Write Valid Delay (Inte1486™ SX-33)
3
t11
Data Write Float Delay (lnte1486™ SX-33)
tWlWH
18
ns
20
ns
WE# Pulse Width (28F016XS-15)
50
ns
tDVWH
Data Setup to WE # Going High (28F016XS-15)
50
ns
tpzx
ClK Output Delay (85C22V1 0-1 0)
8
ns
2
NOTE:
Consult appropriate datasheets for up-to-date specifications.
3-251
28F016XS/intel486TM Interface
7.0
BRDY# and OE# active upon initiating the first access to the 28F016XS-15. BRDY# and OE# remain
low throughout the burst cycle. At 16 MHz, this interface delivers 2-0-0-0 wait-state performance.
INTERFACING TO OTHER
INTEL486™
MICROPROCESSORS
The Intel486 microprocessor family provides designers
a large and diverse selection of CPUs, which offers designers different performance points to meet different
market segment needs. Throughout the product family,
the external bus architecture has remained consistent,
which makes the 28F016XS interface to the entire Intel486 microprocessor family similar, if not identical, to
the Intel486 SX interface described in Sections 2
through 6. The 28F016XS-15 Intel486 SX-33 interface
works equally well for the following Intel486 microprocessors at 5.0V Vee.
•
•
•
•
•
Intel486 SX-20, 25
Intel486 SX2TM-50
Intel486 DX-25, 33
Intel486 DX2TM-40, 50, 66
InteIDX4™-75, 100 (1/0 buffers configured for
5.0V, Vee5 = 5.0V)
The 28F016XS-15 Intel486 SX-33 interface also works
well for the following Intel486 microprocessors at 3.3V
Vee. The 3.3V Vee design utilizes a iPLD22VlO-15
low voltage PLD to control the interface between the
28F016XS-15 (operating at 3.3V Vee) and the processor.
•
•
•
•
Intel486 SX-20, 25
Intel486 DX-25
Intel486 DX2-40, 50
InteIDX4-75
(1/0 buffers configured for 3.3V, Vee5
=
3.3V)
When the external bus frequency falls outside the 16.7
MHz through 33 MHz frequency range at 5.0V Vee
(12.5 MHz through 25 MHz at 3.3V Vee), the optimized SFI Configuration value for the 28F016XS-15
differs in respect to the Intel486 SX-33 design documented earlier. The state machine, therefore, requires
slight modifications to accommodate the different SFI
Configuration. Note, the initial read configuration and
write control state machine remains consistent
throughout all designs because they are not affected by
the optimized SFI Configuration.
Intel486TM SX-16 Interface at 5.0V Vee
The 28F016XS-15's optimized SFI Configuration at 16
MHz equals 1. Therefore, 28F016XS-15 will begin
driving data one CLK period after initiating the first
read access. The optimized state machine' must drive
3-252
Intel486™ OX-50 Interface at 5V Vee
Operating at 50 MHz, the 28F016XS-15's optimized
SFI Configuration equals 3. The interface loads the
two-bit counter and drives ADV# active at the first
rising CLK edge after the processor initiates the read
access. The optimized read state machine increments
the two-bit counter and drives ADV # low every other
CLK, thereby adhering to the Alternating-AI and
Same-AI access rules (see Additional Information). The
28F016XS-15 Intel486 DX-50 interface delivers 5-1-1-1
wait-state read performance.
Intel486TM OX-33 and InteIOX4TM-100 Interface
at 3.3V Vee
Operating at 33 MHz with 3.3V Veo the
28FOI6XS-15's optimized SFI Configuration equals 3.
The interface loads the two-bit counter and drives
ADV # active at the first rising CLK edge after the
processor initiates the read access. The optimized read
state machine increments the two-bit counter and
drives ADV # low for two CLK periods and then
strobes ADV # high for one CLK period. ADV # is
again driven low for two CLK periods finishing the
burst cycle. Refer to the Alternating-AI and Same-AI
access rules (see Additional Information) for further
information on consecutive accesses. The 28F016XS-15
Intel486 DX-33 interface at 3.3V Vee delivers 4-0-1-0
wait-state read performance.
8.0
CONCLUSION
This technical paper has described the interface between the 28F016XS 16-Mbit flash memory component
and the Intel486 microprocessor. This simple design
has been implemented with a minimal number of components and achieves exceptional read performance.
The 28F016XS provides the microprocessor with the
non-volatility and updateability of flash memory and
the performance of DRAM. For further information
about 28F016XS-15, consult reference documentation
for a more comprehensive understanding of device capabilities and design techniques. Please contact your
local Intel or distribution sales office for more information on Intel's flash memory products.
28F016XS/intel486TM Interface
ADDITIONAL INFORMATION
Order Number
Document/Tools
290532
28F016XS Datasheet
297500
"Interfacing 28F016XS to the i960® Microprocessor
Family"
292147
AP-398, "Designing with the 28F016XS"
292146
AP-600, "Performance Benefits and Power/Energy Savings of
28F016XS Based System Designs"
297372
16-Mbit Flash Product User's Manual,
28F016SA/28F016SV/28F016XS/28F016XD
297508
FlashBuilder Utility
Contact Intel/Distribution
Sales Office
28F016XS Benchmark Utility
Contact Intel/Distribution
Sales Office
28F016XS iBIS Models
Contact Intel/Distribution
Sales Office
28F016XS VHDLlVeriiog Models
Contact Intel/Distribution
Sales Office
28F016XS Timing Designer Library Files
Contact Intel/Distribution
Sales Office
28F016XS Orcad and ViewLogic Schematic Symbols
REVISION HISTORY
Description
Original Version
3-253
28FO16XSlintel486™ Interface
APPENDIX A
PLD FILE FOR THE 28F016XS INTEL486™ INTERFACE
Title
Pattem
Revision
Author
, Company Name
Date
CHIP
28F016XS-15 I 486™ Interface
PDS
1
Example
Intel Corporation
2114/94
SFL486_lnterface
; input pins
PIN
PIN
PIN
PIN
PIN
PIN
ClK
ADS
WR
BLAST
CE
RECONF
PIN
PIN
PIN
PIN
A3
RESET
GLOBAL
A2
25
; output pins
PIN
IADV
PIN
!KEN
PIN
IAU
PIN
'/WE
PIN
IBRDY
PIN
IRDY
PIN
PIN
Q1
PIN
CONTO
PIN
CONn
ao
85C22V10 ; 85C22V1Q-15
; clk frequency 33MHz
; address strobe from 486
; multiplexed readlwrlte strobe
; BLAST from the 486
; CE from the address decoding logic
; informs Interface to changes to the SFI
; Configuration
; lower address lines from the 486 used
; In loading the counter
; system reset
; address valid Input to 28F016XS
; cache control
; output enable input to 28F016XS
; write enable input to 28F016XS
; initiating a burst cycle, 486 Input
; non-burst cycle ready, again 486 input
; state variable
; state variable
; lower bit of the 2·bit counter
; higher bit of the 2-bit counter
STATE MOORE_MACHINE
DEFAULT_BRANCH SO
297504-9
3-254
28FO 16XSllntel486TM Interface
; state assignments
SO = IADV " /KEN" IAU " /WE " IBRDY " IRDY " IQO " IQ1
S1 = ADV" /KEN" IAU " /WE " IBRDY " IRDY " IQO " IQ1
S2 = ADV" IKEN " IAU " /WE " IBRDY " IRDY " IQO" Q1
S3 = ADV" KEN" AU" /WE " IBRDY " IRDY " IQO " IQ1
S4 = ADV" KEN" AU" /WE" BRDY" IRDY .. IQO .. IQ1
S5 = IADV" KEN" AU" /WE" BRDY" IRDY .. IQO .. IQ1
S6 = IADV .. IKEN" AU" /WE .. IBRDY " IRDY" QO" Q1
S7 = IADV .. IKEN .. IAU .. /WE .. IBRDY .. IRDY " IQO" Q1
S8 = IADV .. IKEN" IAU " /WE .. IBRDY " IRDY" ao" IQ1
S9 = IADV " /KEN * AU" /WE " IBRDY .. IRDY * IQO .. IQ1
S10 = IADV "/KEN * AU" /WE *IBRDY "/RDY */QO" Q1
S11 = IADV * /KEN * AU * /WE .. IBRDY" ROY * lao .. IQ1
S12 = IADV * /KEN * IAU * WE" IBRDY *IRDY .. lao */Q1
S13 = IADV * /KEN" IAU * WE * IBRDY * IRDY * IQO * Q1
S14 = IADV" IKEN .. IAU" WE * IBRDY * IRDY * QO * IQ1
S15 = IADV" /KEN */AU" /WE" IBRDY'* ROY */QO */Q1
; state transitions
SO := ADS" BOFF
+ lADS" IBOFF .. /wR
+ lADS" IBOFF" WR
S1 := IRECONF " ICE
+ RECONF "ICE
+ BOFF+CE
S2 :=IBOFF
+ BOFF
S3 :=/BOFF
+ BOFF
S4 :=IBOFF
+ BOFF
S5 := BLAST
+ IBLAST + BOFF
S6 := ADS" BOFF
+ lADS" IBOFF " /wR
+ lADS" IBOFF" WR
S7 :=IBOFF
+ BOFF
S8 :=IBOFF
+ BOFF
S9 ;=/BOFF
+ BOFF
S10 :=IBOFF
+ BOFF
S11 ;= VCC
.S12 :=/BOFF
+ BOFF
S13 :=/BOFF
+ BOFF
S14 :=IBOFF
+ BOFF
S15:= VCC
-> SO
-> S1
-> S12
->S7
->S2
-> SO
-> S3
->SO
->S4
-> SO
->S5
->SO
->S5
->S6
->SO
-> S1
-> S12
-> S8
-> SO
-> S9
->SO
-> S10
-> SO
-> S11
->SO
->S6
-> S13
->SO
-> S14
->SO
->S15
->SO
->SO
; start of an access
; not reconfigured
; reconfig active low
; if BOFF Is asserted,
; quit the access and retum
; to state SO. The 486 will
; re-inltiate the access.
; continuos cycling until BLAST is
; presented - end the burst cycle
; holds OE# active for one additional
; ClK to satisfy the 486's data hold
; time.
; if BOFF is activated,
; quit the access and retum
; to state SO. The 486 will
; re-initiate the access.
; write cycle
297504-10
3-255
28FO16XSlintel486™ Interface
EQUATIONS
CONT1 := (lADS • ICE • AS) + (CONT1 • S1)
+ (/CONT1 • S2) + (CONT1 • S3)
+ (CONT1 • S12) + (CONT1 • S13) + (CONT1 • S14)
CONTO:= (lADS· ICE· A2) + (/CONTO· S1)
+ (/CONTO • S2) + (/CONTO • 83)
+ (CONTO· S12) + (CONTO· S13) + (CONTO· S14)
CONTO.ClKF
CONT1.ClKF
ADV.ClKF
OE.ClKF
WE.ClKF
BRDY.ClKF
RDY.ClKF
KEN.ClKF
QO.ClKF
Q1.ClKF
GLOBAL. RSTF
=ClK
=ClK
=ClK
=CLK
=ClK
=ClK
=ClK
-ClK
=CLK
=ClK
= RESET
297504-11
3-256
DD28F032SA
32-MBIT (2 MBIT X 16, 4 MBIT X 8)
FlashFile™ MEMORY
•
User-Selectable 3.3V or 5V Vcc
•
User-Configurable x8 or x16 Operation
•
70 ns Maximum Access Time
•
• 0.43 MB/sec Write Transfer Rate
Revolutionary Architecture
-100% Backwards-Compatible with
Intel 28F016SA
- Pipelined Command Execution
- Write during Erase
1 Million Typical Erase Cycles per
Block
•
2 mA Typical Icc in Static Mode
•
2 /-LA Typical Deep Power-Down
•
56-Lead, 1.2 x 14 x 20mm Advanced
Dual Die TSOP Package Technology
• State-of-the-Art 0.6 /-Lm ETOXTM IV
Flash Technology
•
64 Independently Lockable Blocks
•
Intel's DD28F032SA 32-Mbit FlashFile™ memory is a revolutionary architecture which enables the design of
truly mobile, high performance, personal computing and communication products. With innovative capabilities,
low power operation and very high read/write performance, the DD28F032SA is also the ideal choice for
designing embedded mass storage flash memory systems.
The DD28F032SA is the result of highly advanced packaging innovation which encapsulates two 28F016SA
die in a single Dual Die Thin Small Outline Package (DDTSOP).
The DD28F032SA is the highest density, highest performance nonvolatile read/write solution for solid-state
storage applications. Its symmetrically blocked architecture (100% compatible with the 28F016SA 16-Mbit
FlashFile memory), very high cycling, low power 3.3V operation, very fast write and read performance and
selective block locking provide a highly flexible memory component suitable for high density memory cards,
Resident Flash Arrays and PCMCIA-ATA Flash Drives. The DD28F032SA's dual read voltage enables the
design of memory cards which can interchangeably be read/written in 3.3V and 5.0V systems. Its x8/x16
architecture allows the optimization of memory to processor interface. The flexible block locking option enables bundling of executable application software in a Resident Flash Array or memory card. The
DD28F032SA will be manufactured on Intel's 0.6 ,..,m ETOX IV technology.
290490-2
November 1994
Order Number: 290490-003
3-257
CONTENTS
PAGE
1.0 PRODUCT OVERVIEW ............ 3-259
2.0 DEVICE PINOUT ................... 3-260
2.1 Lead Descriptions ............... 3-262
3_0 MODES OF OPERATION .......... 3-264
4.0 MEMORY MAPS ................... 3-265
4.1 Extended Status Registers Memory
Map for Either Upper or Lower
2BF016SA ........................ 3-266
5.0 BUS OPERATIONS, COMMANDS
AND STATUS REGISTER
DEFINITIONS .......................
5.1 Bus Operations for Word-Wide
Mode (BYTE # = VIH) ............
5.2 Bus Operations for Byte-Wide
Mode (BYTE# = VIIJ .............
5.3 2BFOOBSA Compatible Mode
Command Bus Definitions .........
5.4 2BF016SA-Performance
Enhancement Command Bus
Definitions ........................
5.5 Compatible Status Register ......
5.6 Global Status Register ...........
5.7Block Status Register ............
3-267
3-267
3-267
3-268
3-269
CONTENTS
PAGE
6.0 ELECTRICAL SPECIFICATIONS .. 3-273
6.1 Absolute Maximum Ratings· ..... 3-273
6.2 Capacitance ..................... 3-274
6.3 Timing Nomenclature ............ 3-275
6.4 DC Characteristics (Vee =
3.3V) ............................. 3-278
6.5 DC Characteristics (Vee =
5.0V) ............................. 3-280
6.6 AC CharacteristicsRead Only
Operations ...................... ; . 3-282
6.7 Power-Up and Reset Timings .... 3-286
6.B AC Characteristics for WE #Controlled Command Write
Operations ........................
6.9 AC Characteristics for CEx#Controlled Write Operations .... , ..
6.10 AC Characteristics for Page
Buffer Write Operations ...........
6.11 Erase and Word/Byte Write
Performance, Cycling Performance
and Suspend Latency .............
3-287
3-290
3-293
3-296
3-270
7.0 DERATING CURVES .............. 3-297
3-271
8.0 MECHANICAL SPECIFICATIONS .. 3-299
3-272
DEVICE NOMENCLATURE/ORDERING
INFORMATION , ..................... 3-301
ADDITIONAL INFORMATION ......... 3-301
DATA SHEET REVISION HISTORY ... 3-302
3-258
I
DD28F032SA
• Software Locking of Memory Blocks
1.0 PRODUCT OVERVIEW
The DD28F032SA is a high-performance 32-Mbit
(33,554,432-bit) block erasable nonvolatile random
access memory organized as either 2 Mword x 16,
or 4 Mbyte x 8. The DD28F032SA is built using two
28F016SA chips encapsulated in a single 56L-TSOP
Type I package. The DD28F032SA includes sixtyfour 64-KB (65,536) blocks or sixty-four 32-KW
(32,768) blocks.
The DD28F032SA architecture allows operations to
be performed on a single, 16-Mbit chip at a time.
The implementation of a new architecture, with
ma~y enhanced f.e~tures, will improve the device operating charactenstlcs and results in greater product
reliability and ease of use.
Among the significant enhancements on
DD28F032SA:
the
• 3.3V Low Power Capability
• Improved Write Performance
• Dedicated Block Write/Erase Protection
A 3/5,,!, ~nput pin reconfigures the device internally
for optimized 3.3V or 5.0V Read/Write operation.
The DD28F032SA will be available in a 56-lead
1.2mm thick, 14mm x 20mm Dual Die TSOP Type
package. This form factor and pinout allow for very
high board layout densities. The DD28F032SA is
pinout and footprint compatible with the 28F016SA.
i
Two Command User Interfaces (CUI) serve as the
system interface between the microprocessor or microcontroller and the internal memory operation.
Int~rnal Algorithm Automation allows Word/Byte
Wntes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the 28F016SA 16-Mbit FlashFile
memory.
A super-set of commands has been added to the
basic 28F008SA (8-Mbit FlashFile memory) command-set to achieve higher write performance and
provide additional capabilities. These new commands and features include:
• Page Buffer Writes to Flash
• Command Queueing Capability
• Automatic Data Writes during Erase
• Two-Byte Successive Writes in 8-bit Systems
• Erase All Unlocked Blocks
Note that these operations can only be performed
on one 16-Mbit device at a time. If the WSM is busy
performing an operation, the system should not attempt to select the other device.
Writin~ of memory data is performed in either byte or
word Increments typically within 6 1'-s, a 33% impr~)Vement over the 28F008SA. A Block Erase oper~tlon erases one of the 64 blocks in typically 0.6 sec,
Independent of the other blocks, which is about a
65% improvement over the 28F008SA.
Each block can be written and erased a minimum of
~ 00,000 cycles. Systems can achieve typically 1 milhan Block Erase Cycles by providing graceful block
retirement. This technique is already employed in
hard disk drive designs. Additionally, wear leveling of
block erase cycles can be used to minimize the
write/ erase performance differences across blocks.
The DD28F032SA incorporates two Page Buffers of
256 Bytes (128 Words) on each 28F016SA to allow
pa.ge data writes. This feature can improve a system
wnte performance by up to 4.8 times over previous
flash memory devices.
All operations are started by a sequence of Write
commands to the device. Three Status Registers
(described in detail later) and a RY /BY # output pin
provide information on the progress of the requested
.
operation.
The DD28F032SA allows queueing of the next oper~tion w~ile t.h~ memory executes the current operation. ThiS ehn:lnates system overhead when writing
several bytes In a row to the array or erasing several
blocks at the same time. The DD28F032SA can also
perform Write operations to one block of memory
while performing Erase of another block. However,
simultaneous Write and/or Erase operations are not
allowed on both 28F016SA devices. See Modes of
Operation, Section 3.0.
The DD28F032SA provides user-selectable block
locking to protect code or data such as Device Drivers, PCMCIA card information, ROM-Executable
O/S or Application Code. Each block has an associated nonvolatile lock-bit which determines the lock
status of the block. In addition, the DD28F032SA
has a master Write Protect pin (WP #) which prevents any modifications to memory blocks whose
lock-bits are set.
3-259
DD28F032SA
The DD28F032SA contains three types of Status
Registers to accomplish various fuhctions:
• A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory's Status Register. This register, when
used alone, provides· a straightforward upgrade
capability to the DD28F032SA from a 28F008SAbased design.
The BYTE# pin allows either x8 or x16 read/writes
to the DD28F032SA. BYTE # at logic low selects
8-bit mode with address Ao selecting between low
byte and high byte. On the other hand, BYTE # at
logic high enables 16-bit operation with address A1
becoming the lowe~t order address and address Ao
is not used (don't care). A device block diagram is
shown in Figure 1.
• A Global Status Register (GSR) which informs
the system of command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
• 64 Block Status Registers (BSRs) which provide
block-specific status information such as the
block lock-bit status.
The DD28F032SA incorporates an Automatic Power
Saving (APS) feature which substantially reduces
the active current when the device is in static mode
of operation (addresses not switching) .
The GSR and BSR memory maps for Byte-Wide and
Word-Wide modes· are shown in Figures 4 and 5.
The DD28F032SA incorporates an open drain RY /
BY # output pin. This feature allows the user to ORtie many RY /BY # pins together in a multiple memory configuration such as a Resident Flash Array.
Other configurations of the RY /BY # pin are enabled via special CUI commands and are described
in detail in the 28F016SA User's Manual.
The DD28F032SA also incorporates three chip-enable input pins, CEo#, CE1 # and CE2#. The active
low combination of CEo# and CE1 # controls the
upper 28F016SA. The active low combination of
CEo# and CE2# controls the lower 28F016SA.
3-260
A deep power-down mode of operation is invoked
when the RP# (called PWD on the 28F008SA) pin is
driven low. This mode provides additional write protection by acting as a device reset pin during power
transitions. n the Deep Power-Down state, the WSM
is reset (any current operation will abort) and the
CSR, GSR and BSR registers are cleared.
A CMOS standby mode of operation is enabled
when either CEo #, or both CE 1# and CE2 #, transition high and RP# stays high with all input control
pins at CMOS levels.
2.0 DEVICE PINOUT
The DD28F032SA Standard 56L-Dual Die TSOP
Type I pinout configuration is shown in Figure 2.
DD28F032SA
0°0_7
o
6'"
""
_---wp#
_---RP#
Y-DECODER
Y GATING/SENSING
'....- - - _ RY /SY#
.........
o
'"'"
Vpp
u
o
3/5#
a;
••••••••••••
290490-3
Figure 1. Block Diagram of 16-Mblt Devices
Architectural Evolution Includes Page Buffers, Queue Registers and Extended Registers
3-261
DD28F032SA
2.1. Lead Descriptions
Symbol
Type
Name and Function
Ao
INPUT
BYTE-SELECT ADDRESS: Selects between high and low byte when
device is in x8 mode. This address is latched in x8 Data Writes. Not
used in x16 mode (i.e., the Ao input buffer is turned off when BYTE # is
high).
A1- A15
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte
block. AS-15 selects 1 of 1024 rows, and A1-5 selects 16 of 512
columns. These addresses are latched during Data Writes.
A1S-A20
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These
addresses are latched during Data Writes, Erase and Lock-Block
operations.
DQo-DQ7
INPUT/OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the appropriate
read mode. Floated when the chip is de-selected or the outputs are
disabled.
DQa-DQ15
INPUT/OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations.
Outputs array, buffer or identifier data in the appropriate read mode;
not used for Status register reads. Floated when the chip is deselected or the outputs are disabled.
CEo #
CEx# =
CE1# or
CE2#
INPUT
CHIP ENABLE INPUTS: Activate the device's control logic, input
buffers, decoders and sense amplifiers. CEo# or CE1 # enable/disable
the first 28F016SA (16 Mbit No.1) while CEo#, CE2# enable/disable
the second 28F016SA (16 Mbit No.2). CEo # active low enables chip
operation while CE1 # or CE2# select between the first and second
device, respectively. CE1 # or CE2# must not be active low
simultaneously. Reference Table 3.0.
RP#
INPUT
RESET/POWER-DOWN: RP# low places the device in a Deep PowerDown state. All circuits that burn static power, even those circuits
enabled in standby mode, are turned off. When returning from Deep
Power-Down, a recovery time of 400 ns is required to allow these
circuits to powElr-up. When RP# goes low, any current or pending
WSM operation(s) are terminated, and the device is reset. All Status
registers return to ready (with all status flags cleared).
OE#
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when
low. The outputs float to tri-state off when OE# is high.
NOTE:
CEx # overrides OE # , and OE # overrides WE # .
WE#
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data
Queue Registers and Address Queue Latches. WE# is active low, and
latches both address and data (command or array) on its rising edge.
3-262
DD28F032SA
2.1. Lead Descriptions (Continued)
Symbol
Type
Name and Function
RY/BY#
OPEN DRAIN OUTPUT
READY/BUSY: Indicates status of the internal WSM. When low, it
indicates that the WSM is busy performing an operation. RY /BY #
high indicates that the WSM is ready for new operations (or WSM
has completed all pending operations), or Erase is Suspended, or
the device is in deep power-down mode. This output is always
active (i.e., not floated to tri-state off when OE# or CEo#, CE1 #
are high), except if a RY/BY # Pin Disable command is issued.
WP#
INPUT
WRITE PROTECT: Erase blocks can be locked by writing a
nonvolatile lock-bit for each block. When WP# is low, those
locked blocks as reflected by the Block-Lock Status bits (BSR.6),
are protected from inadvertent Data Writes or Erases. When WP #
is high, all blocks can be written or erased regardless of the state
of the lock-bits. The WP # input buffer is disabled when RP #
transitions low (deep power-down mode).
BYTE #
INPUT
BYTE ENABLE: BYTE # low places device in x8 mode. All data is
then input or output on 000-7, and 008-15 float. Address Ao
selects .between the high and low byte. BYTE # high places the
device in x16 mode, and turns off the Ao input buffer. Address A1,
then becomes the lowest order address.
3/5#
INPUT
3.3/5.0 VOLT SELECT: 3/5 # high configures internal circuits for
3.3V operation. 3/5 # low configures internal circuits for 5.0V
operation.
NOTES:
Reading the array with 3/5# high in a 5.0V system could damage
the device.
There is a significant delay from 3/5 # switching to valid data.
Vpp
SUPPLY
ERASE/WRITE POWER SUPPLY: For erasing memory array
blocks or writing words/bytes/pages into the flash array.
Vee
SUPPLY
DEVICE POWER SUPPLY (3.3V ±0.3V, 5.0V ±0.5V): Do not
leave any power pins floating.
GND
SUPPLY
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any
ground pins floating.
NC
NO CONNECT: No internal connection to die, lead may be driven
or left floating.
3-263
DD28F032SA
WP#
WE#
OE#
3/5#
C~ #
CE2 #
A20
1<,9
1<,8
RY/BY#
DQIS
D~
DQ14
DQs
AI7
1<,6
GND
Vec
1<,5
00,3
DD28F032SA
DQs
1<,2
56 - LEAD TSOP PINOUT
DQ4
Vpp
14 mm x 20 mm
AI4
'-,3
CEo #
RP#
1<,1
1<,0
00,2
Vee
GND
00, I
DQ3
TOP VIEW
00,0
O~
As
As
Vee
DOg
GND
A7
DO,
As
As
000
DOs
Ao
BYTE#
NC
NC
A4
A3
A2
I<,
290490-1
Figure 2. Dual Die TSOP Pinout Configuration
3.0 MODES OF OPERATION
RP#
CEo#
0
X
X
X
DPD
DPD
DPD
1
1
X
X
Standby
Standby
Standby.
CE1#
CE2#
28F016SA No.1
28F016SA No.2
DD28F032SA Chip
1
0
0
1
Active
Standby
Active
1
0
1
0
Standby
Active
Active
1
0
1
1
-Standby
Standby
Standby
1
0
0
0
NOTES:
X = Don't Care
DPD = Deep Power-Down
2BF016SA No.1 = First 16 Mbit device
2BF016SA No.2 = Second 16 Mbit device
3-264
Illegal Condition
DD28F032SA
4.0 MEMORY MAPS
lrrFFF
1rODeD
IEFFrF
lEOOOO
lOFFFF
100000
lcrrrr
leaDOD
10FFFr
lBOOOO
IAFFfF
lAOOOO
19FFFF
190000
18F'FFF
180000
In-rFf
170aoo
16FFFF
160000
15FFFF
150000
14FFFF
,.0000
13FFFF
13000Q
12FFFF
120000
llFFFF
110000
IOFFFF
100000
OFFFFF
DrODOO
OEFFFr
0[0000
OOFFFF
000000
OCFFFF
aeaOOD
DBrFFr
000000
OAFFFF
OAOOOO
09FFFF
090000
Q8FFFF
080000
07FFFF
070000
06FFFF
060000
OSFFFF
050000
04FFFF
040000
03FFFr
030000
02FFFF
020000
01FFFF
010000
ODFFFF
000000
64 KByte Block
64 KByte Block
30
64 KByte Block
29
64 KByte Block
28
64 KByte Block
27
64 KByte Block
26
64 KByte Block
25
BI~ck
24
64 KByte Block
23
64 KByte Block
22
64 KByte
lFFFFF
31
64 KByte Block
21
64 KByte Block
20
64 KByte Block
19
64 KByte Block
18
64 KByte Block
17
64 KByte Block
16
64 KByte Block
15
64 KByte Block
14
64 KByte Block
13
64 KByte Block
12
64 KByte Block
11
64 KByte Block
10
64 KByte Block
9
64 KByte Block
8
64 KByte Block
7
64 KByte Block
6
64 KByte Block
5
64 KByte Block
4
64 KByte Block
3
64 KByte Block
2
64 KByte Block
1
64 KByte Block
0
1rODeD
IEFHF
1[0000
IDFFFF
100000
lrr-FrF
leaDOO
IBFFrr
lBOOoo
IAFFrF
lAOOOO
19FFFr
190000
18FFFr
180000
17FrFr
170000
ISFFFF
160000
15FrrF
150000
14FFFr
140000
13FFFr
130000
12FHF
120000
IIFFFF
110000
10FFFF
100000
OFFFFr
OFOOOO
OEFFFr
OEOOOO
OOFFFr
000000
OCFFFF
OCOOOO
OBFFFF
080000
OAFFFF
OAOOOO
09FFFF
090000
08FFFF
080000
07FFFF
070000
oeFFFF
060000
OSFFFF
050000
04FFFF
04QOOO
03FFFF
030000
02FFFF
020000
OIFFFF
010000
OOFFfF
000000
64 KByte Block
63
64 KByte Block
62
64 KByte Block
61
64 KByte Block
60
64 KByte Block
59
64 KByte Block
58
64 KByte Block
57
64 KByte Block
56
64 KByte Block
55
64 KByte Block
54
64 KByte Block
53
64 KByte Block
52
64 KByte Block
51
64 KByte Block
50
64 KByte Block
49
64 KByte Block
48
64 KByte Block
47
64 KByte Block
46
64 KByte Block
45
64 KByte Block
44
64 KByte Block
43
64 KByte Block
42
64 KByte Block
41
64 KByte Block
40
64 KByte Block
39
64 KByte Block
38
64 KByte Block
37
64 KByte Block
36
64 KByte Block
35
64 KByte Block
34
64 KByte Block
33
64 KByte Block
32
290490-4
28F016SA No.1
290490-5
28F016SA No.2
Figure 3. DD28F032SA Memory Map (Byte-Wide Mode)
I
3-265
DD28F032SA
4.1 Extended Status Registers Memory Map for
Either 28F016SA No.1 or 28F016SA No.2
x8 MODE
RESERVED
GSR
RESERVED
BSR 31
RESERVED
RESERVED
•
•
•
A[20:0]
1F0006H
1F0005H
1F0004H
1F0003H
1F0002H
1F0001H
1FOOOOH
x 16 MODE
A[20: 1]
. . . - - - - - - , F8003H
RESERVED
GSR
1 - - - - - - 1 F8002H
RESERVED
BSR 31
1 - - - - - - 1 F8001H
RESERVED
RESERVED
.......- - - -.... F8000H
010002H
•
•
...-------.., 08001 H
•
RESERVED
RESERVED
RESERVED
GSR
RESERVED
BSR 0
RESERVED
RESERVED
1 - - - - - - 1 00003H .
000006H
000005H
000004H
000003H
000002H
000001H
OOOOOOH
RESERVED
GSR
1------I00002H
RESERVED
BSR 0
1 - - - - - - 1 00001 H
RESERVED
RESERVED
.......- - - -.... OOOOOH
290490-6
Figure 4. Extended Status Register Memory Map
(Byte-Wide Mode)
3·266
290490-7
Figure 5. Extended Status Register Memory Map
(Word-Wide Mode)
DD28F032SA
5.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
= VIH)
5.1 Bus Operations for Word-Wide Mode (BYTE #
Mode
Notes
RP#
CEX#(8)
Read
1,2,7
VIH
VIL
Output Disable
1,6,7
VIH
VIL
VIL
VIH
VIH
X
HighZ
X
Standby
1,6,7
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
HighZ
X
CEo#
OE#
WE#
A1
000-15
RY/BY#
VIL
VIL
VIH
X
DOUT
X
1,3
VIL
X
X
X
X
X
HighZ
VOH
Manufacturer 10
4
VIH
VIL
VIL
VIL
VIH
VIL
0089H
VOH
Device 10
4
VIH
VIL
VIL
VIL
VIH
VIH
66AOH
VOH
1,5,6
VIH
VIL
VIL
VIH
VIL
X
DIN
X
000-7
RY/BY#
Deep Power-Down
Write
5.2 Bus Operations for Byte-Wide Mode (BYTE#
Mode
= VILl
Notes
RP#
CEX#(8)
CEo#
OE#
WE#
Ao
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
VIH
VIH
X
HighZ
X
X
X
X
HighZ
X
Read
1,2,7
Output Disable
1,6,7
VIH
VIL
Standby
1,6,7
VIH
VILVIH
VIH
VIH
VIL
VIH
VIL
1,3
VIL
X
X
X
X
X
HighZ
VOH
Manufacturer 10
4
VIH
VIL
VIL
VIL
VIH
VIL
89H
VOH
Device 10
4
VIH
VIL
VIL
VIL
VIH
VIH
AOH
VOH
1,5,6
VIH
VIL
VIL
VIH
VIL
X
DIN
X
Deep Power-Down
Write
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH.
2. RY/BY# output is open drain. When the WSM is ready, erase is suspended or the device is in deep power-down mode,
RY/BY#will be at VOH if it is tied to Vee through a resistor. RY/BY# at VOH is independent of OE# while a WSM
operation is in progress.
3. RP# at GND ± O.2V ensures the lowest deep power-down current.
4. Ao and A1 at VIL provide device manufacturer codes in x8 and x16 modes respectively. Ao and A1 at VIH provide device
ID codes in x8 and x16 modes respectively. All other addresses are set to zero.
5. Commands for different Erase operations Data Write operations or Lock-Block operations can only be successfully com. pleted when Vpp = VPPH.
6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes
to VOH when the WSM is not busy or in erase suspend mode.
7. RY/BY# may be at VOL while the WSM is busy performing various operations. For example, a status register.read during
a Write operation.
8. CEx# = CE1 # or CE2#.
3-267
DD28F032SA
5.3 28F008SA Compatible Mode Command Bus Definitions
Command
Notes
Read Array
First Bus Cycle
Second Bus Cycle
Oper
Addr
Data
Oper
Addr
Data
Write
X
FFH
Read
AA
AD
Intelligent Identifier
1
Write
X
90H
Read
IA
10
Read Compatible Status Register
2
Write
X
70H
Read
X
CSRD
Clear Status Register
3
WD
Write
X
50H
Word/Byte Write
Write
X
40H
Write
WA
Alternate Word/Byte Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
BA
DOH
Erase Suspend/Resume
Write
X
BOH
Write
X
DOH
ADDRESS
A = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don't Care
DATA
AD = Array Data
CSRD = CSR Data
10 = Identifier Data
WD = Write Data
NOTES:
1. Following the Intelligent Identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase, or Suspend operations.
3. Clears CSR.3, CSR.4 and CSR.4. Also clears GSR.4 and all BSR.4 and BSR.2 bits.
See Status Register definitions.
3·268
DD28F032SA
5.4 28F016SA-Performance Enhancement Command Bus Definitions
Command
Mode Notes
First Bus Cycle
Second Bus Cycle
Oper Addr Data Oper Addr
Read Extended Status
Register
1
Write
X
71H Read
Page Buffer SY{ap
7
Write
X
72H
Write
X
Write
Write
x16
4,5,6,10 Write
x8
3,4,9,10 Write
Read Page Buffer
Single Load to Page Buffer
Sequential Load to Page
Buffer
Page Buffer Write to Flash
Two-Byte Write
x8
4,6,10
Data
RA
GSRD
BSRD
75H Read
PA
PO
X
74H Write
PA
PO
X
EOH Write
X
BCL
Write
X
X
EOH Write
X
WCL
Write
X
X
OCH Write
Ao
BC(L,H) Write WA
x16
4,5,10
Write
X
OCH Write
X
x8
3
Write
X
FBH Write
Ao
Write
X
77H Write
BA
DOH
Write
X
97H Write
X
DOH
Write
X
99H Write
X
DOH
Write
X
A7H Write
X
DOH
Lock Block/Confirm
Upload Status Bits/Confirm
2
-
Upload Device Information
Erase All Unlocked Blocks/
Confirm
WCL
8
Write
X
96H Write
X
01H
RY /BY # Pulse-On-Write
8
Write
X
96H Write
X
02H
RY /BY # Pulse-On-Erase
8
Write
X
96H Write
X
03H
RY/BY # Disable
8
Write
X
96H Write
X
04H
Sleep
Write
X
FOH
Abort
Write
X
80H
- AD = Array Data
PO = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
Write WA
Data
BCH
WCH
BC(H,L)
WCH
WD(L,H) Write WA WD(H,L)
RY /BY # Enable to LevelMode
ADDRESS
BA = Block Address
PA = Page Buffer Address
RA = Extended Register Address
WA = Write Address
X = Don't Care
Third Bus Cycle
Oper Addr
DATA
WC (L,H) = Word Count (Low, High)
BC (L,H) = Byte Count (Low, High)
WD (L,H) = Write Data (Low, High)
3-269
DD28F032SA
•
NOTES:
1. RA can be 1he GSR address or any BSR address. See Figures 4 and 5 for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3. Ao is automatically complemented to load second byte of data. BYTE# must be at VIL.
.
Ao value determines which WD/BC is supplied first: Ao = 0 looks at the WDLlBCL, Ao = 1 looks at the WDH/BCH.
4, BCH/WCH must be at OOH for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the
Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.
5. In x16 mode, only the lower byte 000.7 is used for WCl and WCH. The upper byte 008-15 is a don't care.
6. PA and PO (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.
7. This command allows the user to swap between available Page BufferS (0 or 1).
8. These commands reconfigure RY IBY # output to one of two pulse-modes or enable and disable the RY IBY # function.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer.
Refer to the 28F016SA User's Manual.
10. BCl = OOH corresponds to a byte count of 1. Similarly, WCl = OOH corresponds to a word count of 1.
5.5 Compatible Status Register
I
WSMS
7
lESS
I
6
ES
DWS
VPPS
R
5
4
3
2
R
R
o
NOTES:
CSR.7 = WRITE STATE MACHINE STATUS
1 ,;" Ready
0= Busy
RviBV # output or WSMS bit must be checked to
determine completion of an operation (Erase Suspend,
Erase or Data Write) before the appropriate Status bit
. (ESS, ES or DWS) is checked for success.
CSR.6 = ERASE-SUSPEND STATUS
1 = Erase Suspended
= Erase In Progress/Completed
o
CSR.5 = ERASE STATUS
1 = Error In Block Erasure
= Successful Block Erase
o
If DWS and ES are set to "1" during an erase attempt, an
improper command sequence was entered. Clear the
CSR and attempt the operation again.
CSR.4 = DATA-WRITE STATUS
1 = Error in Data Write
= Data Write Successful
o
CSR.3 = Vpp STATUS
1· = Vpp Low Detect, Operation Abort
0= VppOK
The VPPS bit, unlike an AID converter, does not provide
continuous indication of Vpp level. The WSM interrogates
Vpp's level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
Vpp has not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPl and VPPH.
CSR.2-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.
3-270
DD28F032SA
5.6 Global Status Register
I
WSMS
7
I
OSS
I
6
DOS
DSS
QS
PBAS
5
4
3
2
PBS
PBSS
o
NOTES:
GSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
[1] RY /BY # output or WSMS bit must be checked
to determine completion of an operation (Block
Lock, Suspend, any RY /BY # reconfiguration,
Upload Status Bits, Erase or Data Write) before the
appropriate Status bit (OSS or DOS) is checked for
success.
GSR.6 = OPERATION SUSPEND STATUS
1 = Operation Suspended
o = Operation in Progress/Completed
GSR.5 = DEVICE OPERATION STATUS
1 = Operation Unsuccessful
o = Operation Successful or Currently Running
GSR.4 = DEVICE SLEEP STATUS
1 = Device in Sleep
o = Device Not in Sleep
MATRIX = 5/4
00 = Operation Successful or Currently Running
o 1 = Device in Sleep mode or Pending Sleep
1 0 = Operation Unsuccessful
1 1 = Operation Unsuccessful or Aborted
If operation currently running, then GSR.7
If device pending sleep, then GSR.7 = O.
Operation aborted: Unsuccessful due to
Abort command.
=
o.
GSR.3 = QUEUE STATUS
1 = Queue Full
o = Queue Available
GSR.2 = PAGE BUFFER AVAILABLE STATUS
1 = One or Two Page Buffers Available
o = No Page Buffer Available
GSR.1 = PAGE BUFFER STATUS
1 = Selected Page Buffer Ready
o = Selected Page Buffer Busy
The device contains two Page Buffers.
Selected Page Buffer is currently busy with WSM
operation
GSR.O = PAGE BUFFER SELECT STATUS
1 = Page Buffer 1 Selected
o = Page Buffer 0 Selected
NOTE:
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7, or CSR.7, provides indication when all queued operations are completed.
3-271
DD28F032SA
5.7 Block Status Register
I
BS
7
I
BLS
I
6
BOS
BOAS
QS
VPPS
5
4
3
2
R
R
o
NOTES:
BSR.7 = BLOCK STATUS
1 = Ready
0= Busy
RY /BY # output or BS bit must be checked to
determine completion of an operation (Block Lock,
Suspend, Erase or Data Write) before the
appropriate Status bits (BOS, BLS) is checked for
success.
(1)
BSR.6 = BLOCK LOCK STATUS
1 = Block Unlocked for Write/Erase
o = Block Locked for Write/Erase
BSR.5 = BLOCK OPERATION STATUS
1 = Operation Unsuccessful
o = Operation Successful or Currently Running
BSR.4 = BLOCK OPERATION ABORT STATUS
1 = Operation Aborted
o = Operation Not Aborted
The BOAS bit will not be set until
BSR.7 = 1.
MATRIX 5/4
o 0 = Operation Successful or Currently Running
o 1 = Not a Valid Combination
1 0 = Operation Unsuccessful
1 1 = Operation Aborted
Operation halted via Abort command.
BSR.3 = QUEUE STATUS
1 = Queue Full
o = Queue Available
BSR.2 = Vpp STATUS
1 = Vpp Low Detect, Operation Abort
0= VppOK
BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the BSRs.
NOTE:
1. When multiple operations are queued, checking BSA. 7 only provides indication of completion for that particular block.
GSR.7, or CSA.7, provides indication when all queued operations are completed.
3-272
DD28F032SA
6.0 ELECTRICAL SPECIFICATIONS
6.1 Absolute Maximum
R~tings*
+ BO°C
+ 125°C
Temperature Under Bias ............ O°C to
Storage Temperature .......... -65°C to
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Vee = 3.3V ±O.3V Systems(5)
Notes
Min
Max
Units
Test Conditions
TA
Symbol
Operating Temperature,
Commercial
1
0
70
°C
Ambient Temperature
VCC
VCC with Respect to GND
2
-0.2.
7.0
V
Vpp
Vpp Supply Voltage with
Respect to GND
2,3
-0.2
14.0
V
V
Voltage on any Pin (except
VCc,Vpp) with Respect to GND
2
-0.5
I
Current into any Non-Supply Pin
lOUT
Output Short Circuit Current
Vee
=
Parameter
5.0V ±O.5V, Vee
Symbol
=
4
Vcc
+
0.5
V
±30
mA
100
mA
5.0V ±O.25V Systems(5,6)
Notes
Min
Max
Units
Test Conditions
TA
Operating Temperature,
Commercial
Parameter
1
0
70
°C
Ambient Temperature
VCC
Vcc with Respect to GND
2
-0.2
7.0
V
Vpp
Vpp Supply Voltage with
Respect to GND
2,3
-0.2
14.0
V
V
Voltage on any Pin (except
Vcc,Vpp) with Respect to GND
2
-2.0
I
Current into any Non-Supply Pin
lOUT
Output Short Circuit Current
4
Vcc
+ 0.5
V
±30
rnA
100
rnA
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum DC voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee + 2.0V
for periods <20 ns.
3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. AC specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
6. 5% Vee specifications refer to the 28F032SA-070 in its High Speed Test configuration.
3-273
DD28F032SA
6.2 Capacitance
For a 3.3V System:
Symbol
Notes
Typ
Max
Units
CIN
Capacitance Looking into an
Address/Control Pin
Parameter
1
12
16
pF
TA = 25°C, f = 1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
16
24
pF
TA = 25°C, f = 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing
Specifications
1
50
pF
For Vee = 3.3V
2.5
ns
500 transmission line delay
Equivalent Load Timing Circuit
Test Conditions
± 0.3V
For a S.OV System:
Symbol
Notes
Typ
Max
Units
CIN
Capacitance Looking into an
Address/Control Pin
Parameter
1
12
16
pF
TA=25°C, f = 1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
16
24
pF
TA = 25°C, f = 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing
Specifications
1
100
pF
For Vee = 5.0V ± 0.5V
30
pF
For Vee = 5.0V
Equivalent Testing Load Circuit
forVee ± 10%
2.5
ns
250 transmission line delay
Equivalent Testing Load Circuit
for Vee ± 5%
2.5
ns
830 transmission line delay
NOTE:
1. Sampled, not 100% tested.
3-274
Test Conditions
± 0.25V
DD28F032SA
6.3 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
tee
teLQV time(t) from CEx # (E) going low (L) to the outputs (a) becoming valid (V)
toe
tAee
tGLQV time(t) from OE # (G) going low (L) to the outputs (a) becoming valid (V)
tAVQV time(t) from address (A) valid (V) to the outputs (a) becoming valid (V)
tAS
tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H)
tOH
tWHOX time(t) from WE # (W) going high (H) to when the data (D) can become undefined (X)
Pin States
Pin Characters
A
Address Inputs
H
High
0
Data Inputs
L
Low
a
Data Outputs
V
Valid
E
CEx # (Chip Enable)
X
Driven, but not necessarily valid
F
BYTE # (Byte Enable)
Z
High Impedance
G
OE # (Output Enable)
W
WE# (Write Enable)
P
RP# (Deep Power-Down Pin)
R
RYIBY # (Ready Busy)
V
Any Voltage Level
Y
3/5# Pin
5V
Vee at 4.5V Minimum
3V
Vee at 3.0V Minimum
3-275
DD28F032SA
2.4 _ _I_NP_U_T_.IX:::
0.45
>
TEsT POINTS
"5
<:
2.0
OUTPUT
0.8
290490-8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing begins at
VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 6. Transient Input/Output Reference Waveform (Vee = 5.0V ± 10%) for Standard Test
Configuration(l)
::: __I_NP_U_T_.IX.5 + -
T~T
POINTS--+
1.5 OUTPUT
290490-9
AC test inputs are driven at 3.0V for a Logic "1" and O.OV for a Logic "0". Input timing begins, and output timing ends, at
1.5V. Input rise and fall times (10% to 90%) <10 ns.
Figure 7. Transient Input/Output Reference Waveform (Vee = 3.3V) and
High Speed Reference Waveform(2) (Vee = 5.0V ± 5%)
NOTES:
1. Testing characteristics for DD28F032SA-080IDD28F032SA-l00.
2. Testing characteristics for DD28F032SA-070IDD28F032SA-150.
3-276
DD28F032SA
1)
2.5 ns of 250 Transmission Une
.From Oulpul
Under Tesl
)
Tesl
Poinl·
290490-10
Total Capacitance = 100 pF
Figure 8. Transient Equivalent Testing Load Circuit (Vee = 5.0V ± 10%)
1)
2.5 ns of 500 Transmission Une
• From Oulpul
Under resl
()
Tesl
Poinl·
290490-11
Total Capacitance = 50 pF
Figure 9. Transient Equivalent Testing Load Circuit (Vee = 3.3V ± 0.3V)
1)
2.5 ns of B30 Transmission Une
• From Oulpul
Under resl
()
resl.
Poinl
290490-12
Total Capacitance = 30 pF
Figure 10. High Speed Transient Equivalent Testing Load Circuit (Vee = 5.0V ± 5%)
3-277
DD28F032SA
6.4 DC Characteristics
vee = 3.3V ± 0.3V, TA = O·C to + 70·C
3/5# = Pin Set High for 3.3V Operations
Symbol
Parameter
Notes
Min
Typ
Max
Units
Test Conditions
IlL
Input Leakage Current
1
±2
/LA
Vee = Vee Max,
VIN = Vee or GND
ILO
Output Leakage Current
1
± 20
/LA
Vee = Vee Max,
VIN = Vee or GND
Ices
Vee Standby Current
100
200
/LA
Vee = Vee Max,
CEo#,CEx#,
RP#, = Vee ± 0.2V
BYTE#, WP#, 3/5# = Vee
± 0.2V or GND ± 0.2V
2
8
rnA
Vee= Vee Max,
CEo#, CEx#, RP# = VIH
BYTE#, WP#,
3/5# = VIH or VIL
1,5,6
IceD
Vee Deep PowerDown Current
1
2
10
/LA
RP# = GND ± 0.2V
BYTE# = Vee ± 0.2V
orGND ± 0.2V
leeR1
Vee Read Current
1,4,5,
6
25
30
rnA
Vee = Vee Max
CMOS:CEo#,
CEx# = GND ± 0.2V
B.YTE# = GND ± 0.2V
or Vee ± 0.2V Inputs = GND
± 0.2V or Vee ± 0.2V
f = 6.67 MHz, lOUT = 0 rnA
26
34
rnA
TTL: CEo#, CEx# = VIL,
BYTE# = VIL or VIL
INPUTS = VIL or VIH,
f = 6.67 MHz, lOUT = 0 rnA
8
12
rnA
Word/Byte Write in Progress
leew
3-278
Vee Write Current
1,7
DD28F032SA
6.4 DC Characteristics
(Continued)
Vcc = 3.3V ± 0.3V, TA = O'C to + 70'C
3/5# Pin Set High for 3.3V Operations
Symbol
Parameter
Notes
Min
Typ
Max
Units
Test Conditions
ICCE
Vcc Block Erase Current
1,7
6
12
mA
Block Erase in Progress
ICCES
Vcc Erase
Suspend Current
1,2,
6,7
3
6
mA
CEo#, CEx# = VIH
Block Erase Suspended
IpPD
Vpp Deep PowerDown Current
1
0.4
10
p,A
RP#
IpPRS
Vpp Standby/
Read Current
1
±2
±20
p,A
Vpp::; Vcc
130
400
p,A
Vpp> Vcc
Ippw
Vpp Write Current
1
10
15
mA
Vpp = VPPH,
Word/Byte Write in Progress
IpPE
Vpp Erase Current.
1
4
10
mA
Vpp = VPPH
Block Erase in Progress
IpPES
Vpp Erase
Suspend Current
1
130
400
p,A
Vpp = VPPH,
Block Erase in Suspended
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
Vcc ± 0.3
V
VOL
Output Low
Voltage
0.4
V
VOH1
Output High
Voltage
2.4
V
VOH2
Vpp during
Normal Operations
VPPH
Vpp during
Write/Erase
Operations
Vcc Write/Erase
Lockout Voltage
3
0.0
11.4
2.0
GND ± 0.2V
Vcc = Vcc Min
and IOL = 4 mA
IOH = -2.0 mA
Vcc = Vcc Min
IOH = -100 p,A
Vcc = Vcc Min
Vcc - 0.2
VPPL
VLKO
.
=
12.0
6.5
V
12.6
V
V
NOTES:
1. All current are in RMS unless otherwise noted. Typical values at VCC = 3.3V, Vpp 12.0V, T = 2S'C. These currents are
valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when VPP = VpPL and not guaranteed in the
range between VPPH and VPPL.
4. Automatic Power Savings (APS) reduces ICCR to less than 1 mA in static operation.
5. CMOS Inputs are either VCC ± O.2V or GND ± O.2V. TTL Inputs are either VIL or VIH.
6. CEx# = CE1# orCE2#'
7. If operating with TTL levels, add 4 mA of VCC Standby Current to max Iccw. ICGE and IGGES.
3-279
DD28F032SA
6.5 DC Characteristics
vee = 5.0V ± 0.5V, TA = O°C to + 70°C
3/5# Pin Set Low for 5.0V Operations
Symbol
Max
Units
IlL
Input Leakage
Current
Parameter
1
±2
p.A
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage
Current
1
± 20
p.A
Vee = Vee Max
VIN = Vee or GND
Ices
Vee Standby
Current
200
p.A
Vee = Vee Max
CEo#, CEx#,
RP# = Vee ± 0.2V
BYTE#, WP#, 3/5# = Vee
± 0.2V or GND ± 0.2V
Notes
1,5,6
Min
Typ
100
Test Conditions
I
4
8
rnA
Vee = Vee Max
CEo#, CEx#, RP#
BYTE#, WP#,
3/5# = VIH or VIL
= VIH
IceD
Vee Deep PowerDown Current
1
2
10
p.A
RP# = GND ± 0.2V
BYTE# = Vee ± 0.2V
orGND ± 0.2V
leeR1
Vee Read Current
1,4,5,
6,7
50
60
mA
Vee = Vee Max,
CMOS:CEo#,
CEx# = GND ± 0.2V
BYTE# = GND ± 0.2V
or Vee ± 0.2V
Inputs = GND ± 0.2V
or Vee ± 0.2V
f = 10 MHz,lOUT = 0 mA
52
64
mA
TTL: CEo#, CEx# = VIL,
BYTE# = VILorVIH
Inputs = VIL or VIH,
f = 10 MHz, lOUT = 0 rnA
30
35
rnA
Vee = Vee Max,
CMOS:CEo#,
CEx# = GND ± 0.2V
BYTE# = GND ± 0.2V
or Vee ± 0.2V
Inputs = GND ± 0.2V
or Vee ± 0.2V,
f = 5 MHz, lOUT = 0 rnA
32
39
rnA
TTL:CEo#,CEx# = VIL,
BYTE# = VILorVIH
Inputs = VIL or VIH,
f = 5 MHz, lOUT = 0 rnA
25
35
rnA
Word/Byte in Progress
leeR2
leew
3-280
Vee Read Current
Vee Write Current
1,4,5,
6,7
1,7
DD28F032SA
6.5 DC Characteristics (Continued)
Vce = 5.0V ± 0.5V, T A = O°C to + 70°C
3/5# Pin Set Low for 5.0V Operations
Symbol
Parameter
Typ
Max
Units
Test Conditions
1,7
1B
25
mA
Block Erase in Progress
1,2,6,7
5
10
mA
CEo#, CEx# = VIH
Block Erase Suspended
Vpp Deep PowerDown Current
1
0.4
10
p..A
RP#
IpPRS
Vpp Standby/Read Current
1
±2
± 20
p..A
Vpp ~ Vee
130
400
p..A
Vpp> Vee
Ippw
Vpp Write Current
1
7
12
mA
Vpp = VPPH Word/
Byte Write in Progress
IpPE
Vpp Block Erase Current
1
5
10
mA
Vpp = VPPH Block
Erase in Progress
IpPES
Vpp Erase
Suspend Current
1
130
400
p..A
Vpp = VPPH
Block Erase Suspended
VIL
Input Low Voltage
-0.5
O.B
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage
IeeE
Vce Erase
Suspend Current
IceES
Vee Block
Erase Current
IpPD
Notes
Min
Vee
+ 0.5
0.45
0.B5 Vee
VPPL
Vpp during
Normal Operations
3
VPPH
Vpp during
Write/Erase
Operations
11.4
VLKO
Vec Write/Erase
Lockout Voltage
2.0
GND ± 0.2V
V
V
Vee = Vce Min
IOL = 5.BmA
V
IOH = -2.5 mA
Vee = Vce Min
IOH = -100 p..A
Vcc = Vec Min
Vce - 0.4
VOH2
=
0.0
12.0
6.5
V
12.6
V
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vee =5.0V, Vpp = 12.0V, T = 25'C. These currents
are valid for all product versions (package and speeds).
2. leeEs is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of leeEs and leeR.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when Vpp = VpPL and not guaranteed in the
range between VpPH and VpPL.
4. Automatic Power Saving (APS) reduces leeR to less than 2 mA in Static operation.
5. CMOS Inputs are either Vee ± O.2V or GND ± O.2V. TTL Inputs are either VIL or VIH.
6. CEx# = CE1 # or eE2#.
7. If operating with TTL levels, add 4 mA of Vee standby current to max leew, IeeE and leeES.
3-2B1
DD28F032SA
6.6 AC Characteristics-Read Only Operatlons(1)
vee
= 3.3V
± 0.3V, TA
= O·C to
+ 70·C
Versions (5)
Symbol
tAVAV
DD28F032SA·150
Parameter
Notes
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CEx# to Output Delay
Min
Max
150
2
Units
ns
150
ns
150
ns
750
ns
50
ns
tpHQV
RP# High to Output Delay
tGLQV
OE # to Output Delay
2
tELQX
CEx# to Output in Low Z
3
tEHQZ
CEx# to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE # to Output in High Z
3
tOH
Output Hold from Address, CEx# or OE#
Change, Whichever Occurs First
3
tFLQV
tFHQV
BYTE # to Output Delay
3
150
ns
3
40
ns
3
5
ns
Z
tFLQZ
BYTE # Low to Output in High
tELFL
tELFH
CEx# Low to BYTE # High or Low
0
ns
55
ns
40
ns
0
ns
ns
0
For Extended Status Register Reads
tAVEL
Address Setup to CEx # Going Low
3,4
0
ns
tAVGL
Address Setup to OE # Going Low
3,4
0
ns
3·282
DD28F032SA
6.6 AC Characteristics-Read Only Operations(1) (Continued)
Vee = 5.0V ± 0.5V, T A = O·C to + 70·C
Verslons(S)
Vee
±5%
DD28F032SA070(6)
DD28F032SA080(7)
Vee
± 10%
Symbol
Parameter
tAvAV
Read Cycle Time
tAVOV
Address to Output Delay
tELOV
CEx # to Output Delay
tpHQV
RP# to Output Delay
Notes
Min
Max
70
Min
80
70
2
tGLQV
OE # to Output Delay
2
tELQX
CEx# to Output in Low Z
3
Max
DD28F032SA- Units
100(7)
Min
Max
100
ns
80
100
ns
70
80
·100
ns
400
480
550
ns
40
ns
30
0
35
0
0
25
ns
35
CEx# to Output in High Z
3
OE# to Output in Low Z
3
tGHQZ
OE# to Output in High Z
3
toH
Output Hold from Address,
CEx# or OE# Change,
Whichever Occurs First
3
tFLQV
tFHQV
BYTE # to Output Delay
3
70
80
100
ns
tFLQZ
BYTE# Low to Output
in HighZ
3
25
30
30
ns
tELFL
tELFH
CEx# Low to BYTE #
High or Low
3
5
5
5
ns
0
30
ns
tEHQZ
lGLQX
0
25
0
ns
0
30
35
0
0
ns
ns
For Extended Status Register Reads
tAvEL
Address Setup to CEx #
Going Low
3,4
0
0
0
ns
tAVGL
Address Setup to OE #
Going Low
3,4
0
0
0
ns
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figures 6 and 7.
2. OE#' may be delayed up to tELQV-tc;LQV after the falling edge of CEx# without impact in tELQV.
3. Sampled, not 100% tested.
4. This timing parameter is used to latch the correct BSR data onto the outputs.
5. Device speeds are defined as:
.
70/80 ns at Vee = 5.0V equivalent to
150 ns at Vee = 3.3V
100 ns at Vee = 5.0Vequivalentto
150 ns at Vee = 3.3V
6. See.AC Input/Output ReverenCe Waveforms and AC Testing Load Circuits for High Speed Test Configuration.
7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit
3-283
DD28F032SA
OUTPUTS ENABLED
Vee POWER-UP
DATA VALID
STANDBY
Vcc POWER-DOWN
V1H
ADDRESSES STABLE
ADDRESSES (A)
V1L
....- - - - - - - tAVAV _ _ _ _ _ _ _ _-I+I
V1H
CEx# (E) ( I)
V1L
OE#(G)
VOH
HIGH Z
HIGH Z
DATA (0/0)
VOL
1+-----tAVQV-----+I
5.0V
Vee
GHD
V1H
RP# (p)
V1L
14------
)
tpHQV _ _ _ _ _ _ _ _ _ _~~'
\
290490-13
NOTES:
For 28F016SA No.1: CEX'" is defined as the latter of CEo'" or CE1'" going low. or the first of CEo'" or CE1'" going
high.
For 28F016SA No.2: CEx'" is defined as the latter of CEo'" or CE2'" going low. or the first of CEo'" or CE2'" going
high.
Figure 11. Read Timing Waveforms
3-284
DD28F032SA
VIH
ADDRESSES (A)
VIL
XXXXXXXl
---
ADDRESSES STABLE
,
V IH
CEx' (E) ( I)
VIL
---
tAy,," t,:LrL
,
t AVEl
VIH
BYTE. (F)
,.
tElQX
DATA (DQO-DQ7)
VOL
---- ~
VOL
tOH .....
'/I.
'\ \.
t AVQV
V OH
DATA (DQB-DQt5)
HIGH Z
~
trLQV =t AVQV
t GLOV
~x
HIGH Z
/
---
tElQV
VOH
/
~
~
AVGL
t
XXXXXXX
---
t AVAY
OUTPUT~~~)(
DATA
DATA
OUTPUT
~
.\\
./1
HIGH Z
trLQZ
TIl'
~\
"
DATA \
OUTPUT
I
HIGH Z
290490-14
NOTES:
For 28F016SA No.1: CEx# is defined as the latter of CEo'" or CE1# going low, or the first of CEo# or CE1# going
high.
For 28F016SA No.2: CEx# is defined as the latter of CEo# or CE2# going low, or the first of CEo# or CE2# going
high.
Figure 12. BYTE # Timing Waveforms
3-285
intel~
DD28F032SA
6.7 Power-Up and Reset Timings
Vee POWER UP
RP#
(Pl
t YHPH
3/5#
(yl
-
t YLPH
'I
....
t pLYL
~
5.0V,
" Ll
3.3V
OV
(3V,5Vl
V
t pL5V
Address
(Al
Data
XX: (XX: IX: (X:
X (X: IX.
VALID
...
(x: (X:
VALID
...
tAV~
~AVQV
. VALID
'\.
3.3V OUTPUTS f
VALID
(al
5.0V OUTPUTS
~
tpHQV
tpHQV
290490-15
Figure 13; Vee Power-Up and RP# Reset Waveforms
Symbol
Parameter
tPLYL
tpLYH
RP# Low to 3/5# Low (High)
tYLPH
tvHPH
3/5# Low (High) to RP# High
tpL5V
tPL3V
Notes
Min
Max
Units
0
p.s
1
2
p.s
RP# Low to VCC at 4.5V Minimum
(to Vee at 3.0V min or 3.6V max)
2
0
p.s
tAVQV
Address Valid to Data Valid
for Vcc = 5.0V ± 10%
3
80
ns
tpHQV
RP# High to DataValidforVcc = 5.0V
3
480.
ns
±
10%
NOTES:
CEo#, CEx#and OE# are switched low after Power-Up.
1. Minimum of 2 j.LS is required to meet the sp~ified tpHQV times.
2. The power supply may start to switch concurrently with RP# going Low.
3. The address access tie and RP# high to data valid time are shown for 5.0V Vee operation. Refer to the AC Characteristics Read Only Operations 3.3V Vee operation and all other speed options.
3-286
•
DD28F032SA
6.8 AC Characteristics for WE#-Controlled Command Write Operations(1)
vee
= 3.3V
± 0.3V, TA
= O°C to
+ 70°C
Versions
Symbol
Notes
Parameter
DD28F032SA-150
Min
Typ
Unit
Max
tAvAV
Write Cycle Time
tVPWH
VPP Setup to WE# Going High
tpHEL
RP # Setup to CEx # Going Low
tELWL
CEx # Setup to WE # Going Low
tAVWH
Address Setup to WE# Going High
2,6
tDVWH
Data Setup to WE# Going High
2,6
75
ns
tWLWH
WE # Pulse Width
75
ns
3
150
ns
100
ns
480
ns
10
ns
75
ns
tWHDX
Data Hold from WE # High
2
10
ns
tWHAX
Address Hold from WE# High
2
10
ns
tWHEH
CEx # hold from WE # High
10
ns
tWHWL
WE # Pulse Width High
75
ns
tGHWL
Read Recovery before Write
0
tWHRL
WE# High to RY/BY# Going Low
tRHPL
RP# Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY IBY # High
ns
100
3
ns
0
ns
tpHWL
RP # High Recovery to WE # Going Low
1
J.Ls
tWHGL
Write Recovery before Read
95
ns
tQWL
Vpp Hold from Valid Status Register
(CSR, GSR, BSR) Data and RYIBY # High
0
J.Ls
tWHQV1
Duration of WordlByte Write Operation
tWHQV2
Duration of Block Erase Operation
4,5
5
4
0.3
9
Note 7
J.Ls
10
sec
3-287
DD28F032SA
6.8 AC Characteristics for WE #-Controlled Command Write Operations(1)
5.0V ± 0.5V, T A = O°C to + 70°C (Continued)
vee =
Vee
Versions
± 5%
DD28F032SA·
070
DD28F032SA·
080
Vee
10%
±
Symbol
Parameter
Notes
Min
Typ
Max
Min
Typ
Max
DD28F032SA·
100
Min
Typ
Unit
Max
tAVAV
Write Cycle Time
tVPWH
VPP Setup to WE#
Going High
tpHEL
RP# Setup to CEx#
Going Low
480
480
480
ns
tELWL
CEx# Setup to WE#
Going Low
0
0
0
ns
tAvwH
Address Setup to WE #
Going High
2,6
50
50
50
ns
tOVWH
Data Setup to WE #
Going High
2,6
50
50
50
ns
tWLWH
WE # Pulse Width
40
50
50
ns
tWHOX
Data Hold from WE #
High
2
0
0
0
ns
tWHAX
Address Hold from WE #
High
2
10
10
10
ns
tWHEH
CEx# Hold from WE#
High.
10
10
10
ns
tWHwL
WE # Pulse Width High
30
30
50
ns
tGHWL
Read Recovery before
Write
0
0
0
ns
tWHRL
WE # High to RY /BY #
Going Low
tRHPL
RP# Hold from Valid
Status Register (CSR,
GSR, BSR) Data and
RY/BY# High
tpHwL
3
70
80
100
ns
100
100
100
ns
100
100
100
ns
0
0
0
ns
RP# High Recovery to
WE # Going Low
1
1
1
IJ-s
tWHGL
Write Recovery before
Read
60
65
65
ns
tOWL
VPP Hold from Valid
Status Register (CSR,
GSR, BSR) Data and
RY/BY# High
0
0
0
IJ-s
3
tWHOV1 Duration of Word/Byte
Write Operation
4,5
4.5
tWHOV2 Duration of Block Erase
Operation
4
0.3
3-288
6
Note 7
4.5
10
0.3
6
Note 7
4.5
10
0.3
6
Note 7 IJ-s
10
sec
DD28F032SA
NOTES:
For 28F016SA No.1: CEx# is defined as the latter of CEo# or CE1 # going low or the first of CEo# or CE1 # going high.
For 28F016SA No.2: CEx# is defined as the latter of CEo# or CE2# going low or the first of CEo# or CE2# going high.
1. Read timings during Write and Erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Word/Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE # for all Command Write operations.
7. This information will be available in a technical paper. Please call Intel's Application Hotline or your local sales office for
more information.
READ EXTENDED
STATUS REGISTER DATA
V,"
ADOR[SSES (A)
NOTE 2
~~Q~~
V"
_____
READ COMPATIBLE
~02~'; _____ _
STATUS REGISTER DATA
CE~# (E)
NOTE 4
0[# (G)
WEn (w)
V,H
DATA (0/0)
V"
RY leyn (R)
RP#
,,
,
(p)
~---------------------tYPWH
t QVVL
"PFH
V pPL
Vpp (V)
V,H
V"
290490-16
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRO.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRO.
3. This cycle is invalid when using CSRO for verification during Data-Write/Erase operations.
4. For 28F016SA No.1: CEx# is defined as the latter of CEo# or CE1 # going low, or the first of CEo# or CE1 # going
high. For 28F016SA NO.2: CEx# is defined as the latter of CEo# or CE2# going low, or the first of CEo# or CE2#
going high
5. RP # low transition is only to show tRHPL; not valid for above Read and Write cycles.
Figure 14. AC Waveforms for Command Write Operations
3-289
DD28F032SA
6.9 AC Characteristics for CEx #-Controlled Write Operatlons(1)
vee = 3.3V. ± 0.3V, TA ~ O·C to + 70·C
Versions
Symbol
Parameter
tAVAV
Write Cycle Time
tljPEH
VPP Setup to CEx# Going High
Notes
3
DD28F032SA-150
Min
Typ
Max
Unit
150
ns
100
ns
tpHWL
RP# Setup to WE# Going Low
480
ns
tWLEL
WE # Setup to CEx# Going Low
0
ns
tAvEH
Address Setup to CEx# Going High
2,6
75
ns
tOVEH
Data Setup to CEx# Going High
2,6
75
ns
tELEH
CEx# Pulse Width
75
ns
tEHOX
Data Hold from CEx# High
2
10
ns
tEHAX
Address Hold from CEx# High
2
10
ns
tEHWH
WE hold from CEx# High
10
ns
tEHEL
CEx# Pulse Width High
75
ns
tGHEL
Read Recovery before Write
0
ns
tEHRL
'CEx# High to RY IBY # Going Low
tRHPL
RP# Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY IBY # High
tpHEL
RP# High Recovery to CEx# Going Low
tEHGL
Write Recovery before Read
tQWL
VPP Hold from Valid Status Register
(CSR, GSR, BSR) Data and RY IBY # High
tEHQV1
Duration of Word/Byte Write Operation
tEHQV2
Duration of Block Erase Operation
3·290
100
3
ns
0
ns
1
J.ts
120
0
4,5
5
4
0.3
ns
.
J.ts
9
Note 7
J.ts
10
sec
DD28F032SA
6.9 AC Characteristics for CEx#-Controlled Command Write Operatlons(1)
5.0V ± 0.5V, T A = O·C to + 70· C (Continued)
vee =
Versions
Vee
±5%
DD28F032SA·
070
DD28F032SA·
080
Vee
± 10%
Symbol
Parameter
Notes
tAvAV
Write Cycle Time
tvPEH
Vpp Setup to CEx#
Going High
tpHWL
RP# SetuptoWE#
Going Low
tWLEL
WE# Setup to CEx#
Going Low
tAVEH
Address Setup to CEx#
Going High
tOVEH
Data Setup to CEx #
Going High
tELEH
CEx# Pulse Width
tEHOX
Data Hold from CEx#
High
2
tEHAX
Address Hold from
CEx# High
2
tEHWH
Min
Typ
Max
Min
Typ
Max
DD28F032SA·
100
Min
Typ
Unit
Max
70
80
100
ns
3
100
100
100
ns
3
480
480
480
,ns
0
0
0
ns
2,6
50
50
50
ns
2,6
50
50
50
ns
40
50
50
ns
0
0
0
ns
10
10
10
ns
WE Hold from CEx#
High
10
10
10
ns'
tEHEL
CEx# Pulse Width High
30
30
50
ns
tGHEL
Read Recovery before
Write
0
0
0
ns
tEHRL
CEx# High to RY IBY #'
Going Low
tRHPL
RP# Hold from Valid
Status Register (CSR,
GSR, BSR) Data and
RY/BY# High
tpHEL
100
100
100
ns
0
0
0
ns
RP# High Recovery to
CEx# Going Low
1
1
1
".,s
tEHGL
Write Recovery before
Read
60
65
80
ns
tawL
VPP Hold from Valid
Status Register (CSR,
GSR, BSR) Data at
RY/BY# High
0
0
0
".,s
tEHQV1
Duration of WordlBYte
Write Operation
tEHQV2 Duration of Block Erase
Operation
3
4,5
4.5
4
0.3
6
Note 7 4.5
10
0.3
6
Note 7 4.5
10
0.3
6
Note 7 ".,s
10
sec
3-291
DD28F032SA
NOTES:
For 28F016SA NO.1: CEx* is defined as the latter of CEo* or CEl * going low or the first of CEo* or CEl * going high.
For 28F016SA No.2: CEx* is defined as the latter of CEo* or CE2* going low or the first of.CEo* or CE2* gOing high.
1. Read timings during Write and Erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Data.
5. Word/Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CEx* for all Command Write Operations.
7. This information will be available in a technical paper. Please call Intel's Application Hotline or your local sales office for
more information.
DEEP
WRnE DATA-wRITE OR
POWER-DOWN [RASE SETUP COt.4t.1ANO
NOTE
1
ADDRESSES
(A)
ADDRESSES (A)
WRITE READ EXTENDED
REGISTER COhlMANO
READ EXTENDED
STATUS REGISTER DATA
VtH~~~~~~22~~t::AI:N=:)~~22~~~~2222~~~==~A:=R:A==~22~~~~~~~
vELL
tA\lAV
HOTE2
&: ~~;! r~;~~_A~~I~~~SOR AUTOhlATEO DATA-WRITE
ERASE CONFIIUI COt.lNAND
OR ERASE DELAY
t(HAX
VIH~~~~~~~~~~~;A~IN;:~~~22~~
V IL,-
_____ _____ _
~~~:
READ COt.4PATIBLE
STATUS REGISTER DATA
_
_
OE# (G)
t[HOV1,2
CEx'" (E)
NOTE"
DATA (0/0)
RY IBY'" (R)
RP# (P)
,,
~----------------------
V?P
(v)
290490-17
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. For 28F016SA NO.1: CEx* is defined as the latter of CEo* or CEl * going low, or the first of CEo* or CE 1 * going
high.
For 28F016SA No.2: CEx* is defined as the latter of CEo* or CE2* going low, or the first of CEo* or CE2* gOing
high.
5. RP * low transition is only to show tRHPL; not valid for above Read and Write cycles.
Figure 15. Alternate AC Waveforms for Command Write Operations
3-292
DD28F032SA
6.10 AC Characteristics for Page Buffer Write Operations(1)
vee = 3.3V
±0.3V, TA
= O·G to
+70·G
Versions
Symbol
Parameter
DD28F032SA·150
Notes
tAVAV
Write Cycle Time
tELWL
GEx # Setup to WE # GOing Low
tAVWL
Address Setup to WE# Going Low
3
tOVWH
Data Setup to WE# Going High
2
tWLwH
WE # Pulse Width
Min
Typ
Unit
Max
150
ns
10
ns
0
ns
75
ns
75
ns
tWHOX
Data Hold from WE # High
2
10
ns
tWHAX
Address Hold from WE# High
2
10
ns
tWHEH
GEx# Hold from WE# High
10
ns
tWHWL
WE # Pulse Width High
75
ns
tGHWL
Read Recovery before Write
0
ns
tWHGL
Write Recovery before Read
95
ns
3-293
DD28F032SA
6.10 AC Characteristics for Page Buffer Write Operatlons(1) (Continued)
Vee = 5.0V ±:0.5V. TA = O"C to
+ 70"C
DD28F032SA070
Versions
DD28F032SA
-080
DD28F032SA100
Typ Max
Unit
Parameter
Notes Min
Typ Max Min
Typ Max Min
tAVAV
Write Cycle Time
70
80
100
ns
tELWL
CEx# Setup to WEll'
Going Low
0
0
0
ns
tAVWL
Address Setup to
WE # Going Low
3
0
0
0
ns
tOVWH
Data Setup to WE #
Going High
2
50
50
50
ns
tWLWH
WEll' Pulse Width
40
50
50
ns
tWHOX
Data Hold from WE #
High
2
0
0
0
ns
tWHAX
Address Hold from
WE#High
2
10
10
10
ns
tWHEH
CEx# Hold from WEll'
High
10
10
10
ns
twHWL
WEll' Pulse Width High
30
30
50
ns
tGHWL
Read Recovery before
Write
0
0
0
ns
tWHGL
Write Recovery before
Read
60
65
65
ns
Symbol
NOTES:
F:or 28F016SA No.1: CEx# is defined as the latter of CEo# or CEl # going low or the first of CEo# or CEl # going high.
For 28F016SA No.2: CEx# is defined as the latter of CEoll' or CE2# going low or the first of Ceo # or CE2# going high.
1. These are WE#-controlled write timings. equivalent CEx#-controlied write timings apply..
2. Sampled. not 100% tested. .
.
3. Address must be valid during the entire WEll' low pulse or the entire CEx# low pulse (for CEx# - controlled write timings)
3-294
DD28F032SA
IWHEH
CEx#
(E)
WE#
I WHWL
(W)
I WLWH
I WHAX
VALID
ADDRESSES
IOVWH
DATA
(D/Q)
l
-------~
HIGH Z
"'" .11.
''"~ )----0
A..
1'ti
1'ti
1>0
A..
1'ti
I>e
A,
A,
GND
GND
I\,
I\,
Va:;
DOg
ooa
DCa
Va:;
DOg
DQ1
DQa
DCa
Ao
Ao
BYTEfj
NC
NC
OE#
/lg
A,
001
RYIBY#
Vpp
RIP#
BYTE#
WE#
22
WP#
23
DC, 3
DC;
DC, 2
24
25
D~
D~
~0
DC,o
26
D~
27
28
~
~1
Va:;
GND
NC
NC
D~
DC, 1
GND
290528-3
NOTE:
56· Lead SSOP Mechanical
Diagrams and dimensions are shown at the end of this datasheet.
Figure 3. 56-Lead SSOP Pinout Configuration
3·312
28F016SV FlashFile™ Memory
3.0 MEMORY MAPS
"120-0]
1FFFFF
1Foooo
1EFFFF
1Eoooo
1DFFFF
1DOOOO
1CFFFF
1COOOO
1BFFFF
180000
1AFFFF
1AOOOO
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
180000
15FFFF
150000
14FFFF
140000
'13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
OFFFFF
OFoooo
OEFFFF
OEoooo
OOFFFF
ODOOOO
OCFFFF
ocoooo
OBFFFF
080000
OAFFFF
OAOOOO
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFF F
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
DOFFFF
00000o
A[2Q..1J
64-Kbyte Block 31
64-Kbyte Block 30
64-Kbyte Block 29
64-Kbyte Block 29
64-Kbyte Block 'ZI
64-Kbyte Block 29
64-Kbyte Block 26
64-Kbyte Block
24
64-Kbyte Block 23
64-Kbyte Block 22
64-Kbyte Block 21
64-Kbyte Block 20
64-Kbyte Block 19
64-Kbyte Block 18
64-Kbyte Block
17
64-Kbyte Block 18
64-Kbyte Block 16
64-Kbyte Block 14
64-Kbyte Block 13
64-Kbyte Block 12
64-Kbyte Block
11
64-Kbyte Block 10
64-Kbyte Block
9
64-Kbyte BloCk
8
64-Kbyte Block
7
64-Kbyte Block
8
64-Kbyte Block
6
64-Kbyte Block
4
64-Kbyte Block
3
64-Kbyte Block
2
64-Kbyte Block
1
64-Kbyte Block
0
Byte-Wide (x8) Mode
FFFF
FBOOO
F7FFF
Foooo
EFFFF
EIlOOO
E7FF F
Eoooo
[FFFF
D8000
C7FFF
DOOOO
[FFFF
C8000
C7FFF
=00
BFFFF
B8000
B7FFF
80000
A8FF F
A6000
A7FF F
AOOOO
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
BFFFF
88000
87FFF
80000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FF F
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FF F
20000
1FFFF
18000
17FFF
10000
OFFF F
08000
07FFF
00000
32-Kword Block 31
32-Kword Block 30
32-Kword Block 29
32-Kword Block 29
32-Kword Block 'ZI
32-Kword Block 29
32-Kword Block 26
32-Kword Block 24
32-Kword Block 23
32-Kword Block 22
32-Kword Block 21
32-Kword Block 20
32-Kword Block 19
32-Kword Block 18
32-Kword Block 17
32-Kword Block 18
32-Kword Block 16
32-Kword Block 14
32-Kword Block 13
32-Kword Block 12
32-Kword Block 11
32-Kword Block 10
32-Kword Block
9
32-Kword Block
8
32-Kword Block
7
32-Kword Block
8
32-Kword Block
6
32-Kword Block
4
32-Kword Block
3
32-Kword Block
2
32-Kword Block
1
32-Kword Block
0
Word-Wide (x16) Mode
290528-4
Figure 4. 2.,F016SV Memory Maps (Byte~Wide and Word·Wide Modes)
3-313
28F016SV FlashFile™ Memory
3.1 Extended Status Registers Memory Map
x8MODE
RESERVED
GSR
RESERVED
BSR31
RESERVED
RESERVED
A[20-0]
1FOO06H
1FOO05H
1FOO04H
1FOO03H
GSR
I------------t
RESERVED
BSR31
1FOO02H
1FOOO1H
1FOOOOH
I-'------------t
RESERVED
•
•
•
•
•
00OOO6H
RESERVED
RESERVED
BSRO
RESERVED
RESERVED
F8001H
. - - - - - - - - - - - - , 08001H
RESERVED
RESERVED
GSR
F8002H
'--_ _ _
RE_S_E_R_V_E_D_ _--' F8000H
•
010002H
000005H
000004H
000003H
00OO02H
1 - - - - - - - - - - - ; 00003H
RESERVED
GSR
1 - - - - - - - - - - - ; 00002H
RESERVED
BSRO
I---------~
000001H
OOOOOOH
0OO01H
RESERVED
RESERVED
' - -_ _ _
_ _ _ _ _....J OOOOOH
290528-5
290528-6
Figure 5. Extended Status Register Memory Map
(Byte-Wide Mode)
3·314
x1G MODE
A[20-1]
. . - - - - - - - - - - . . . , F8003H
RESERVED
Figure 6. Extended Status Register Memory Map
(Word-Wide Mode)
28F016SV. FlashFile™ Memory
4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
=
4.1 Bus Operations for Word-Wide Mode (BYTE #
Mode
VIH)
Notes
RP#
CE1#
CEo#
OE#
WE#
A1
DQO-15
RY/BY#
Read
1,2,7
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
Output Disable
1,6,7
VIH
VIL
VIL
VIH
VIH
X
HighZ
X
HighZ
X
Standby
Deep Power-Down
Manufacturer ID
Device ID
Write
1,6,7
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
1,3
VIL
X
X
X
X
X
HighZ
VOH
VOH
4
VIH
VIL
VIL
VIL
VIH
VIL
0089H
4,8
VIH
VIL
VIL
VIL
VIH
VIH
66AOH
VOH
VIL
X
DIN
X
DQO_7
RY/BY#
1,5,6
VIH
VIL
VIL
VIH
4.2 Bus Operations for Byte-Wide Mode (IBYTE#
Mode
Notes
RP#
CE1#
CEo#
= Vld
OE#
WE#
Ao
Read
1,2,7
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
Output Disable
1,6,7
VIH
VIL
VIL
VIH
VIH
.X
HighZ
X
Standby
1,6,7
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
HighZ
X
1,3
VIL
X
X
X
X
X
HighZ
VOH
Deep Power-Down
Manufacturer ID
Device ID
Write
4
VIH
VIL
VIL
VIL
VIH
VIL
89H
VOH
4,8
VIH
VIL
VIL
VIL
VIH
VIH
AOH
VOH
1,5,6
VIH
VIL
VIL
VIH
VIL
X
DIN
X
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH.
2. RY IBY # output is open drain. When the WSM is ready. Erase is suspended or the device is in deep power-down mode.
RY/BY# will be at VOH if it is tied to Vce through a resistor. RY/BY# at VOH is independent of OE# while a WSM
operation is in progress.
3. RP# at GND ± O.2V ensures the lowest deep power-down current.
4. Ao and A1 at VIL provide device manufacturer codes in xB and x16 modes respectively. Ao and A1 at VIH provide device
ID codes in xB and x16 modes respectively. All other addresses are set to zero.
5. Commands for Erase, Data Write, or Lock-Block operations can only be completed successfully when Vpp = VPPH1 or
Vpp = VPPH2.
6. While the WSM is running, RY/BY# in level-mode (default) stays at VOL until all operations are complete. RY/BY# goes
to VOH when the WSM is not busy or in erase suspend mode.
7. RY/BY# may be at VOL while the WSM is busy performing various operations. For example, a Status Register read
during a Write operation.
B. The 2BF016SV shares an identical device identifier (66AOH in word-wide mode, AOH in byte-wide mode) with the
2BF016SA. See application note AP-393 for software and hardware techniques to differentiate between the 28F016SV
and 28F016SA.
3-315
28F016SV FlashFile™ Memory
4.3 28F008SA-Compatible Mode Command Bus Definitions
Command
First Bus Cycle
Notes
Read Array
Second Bus Cycle
Oper
Addr
Data
Oper
Addr
Data
Write
X
FFH
Read
AA
AD
Intelligent Identifier
1
Write
X
90H
Read
IA
ID
Read Compatible Status Register
2
Write
X
70H
Read
X
CSRD
Clear Status Register
3
WD
Write
X
SOH
Word/Byte Write
Write
X
40H
Write
WA
Alternate Word/Byte Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
BA
DOH
Erase Suspend/Resume
Write
X
BOH
Write
X
DOH
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don't Care
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the Intelligent Identifier command, two Read operations access the manufacturer and device signature codes.
2. The CSR is automatically available after device enters Data Write, Erase, or Suspend operations.
3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5, BSR.4 and BSR.2 bits. See Status Register definitions.
3-316
28F016SV FlashFile™ Memory
4.4 28F016SV-Performance Enhancement Command Bus Definitions
Command
Mode
Notes
First Bus Cycle
Second Bus Cycle
Oper Addr Data Oper Addr
Read Extended
Status Register
1
Write
X
71H
Page Buffer Swap
7
Write
X
72H
Read Page Buffer
Write
X
Single Load to
Page Buffer
Write
X
Write
X
x16
4,5,6,10 Write
x8
3,4,9,10 Write
Sequential Load to
Page Buffer
x8
4,6,10
Data
GSRD
BSRD
75H
Read
PA
PO
74H
Write
PA
PO
EOH
Write
X
BCL
Write
X
EOH
Write
X
WCL
Write
X
WCH
X
OCH
Write
Ao
BC(L,H)
Write
WA
BC(H,L)
WCL
Write
WA
WCH
WD(L,H) Write
WA
WD(H,L)
x16
4,5,10
Write
X
OCH
Write
X
x8
3
Write
X
FBH
Write
Ao
Write
X.
77H
Write
BA
DOH
Upload Status
Bits/Confirm
2
Write
X
97H
Write
X
DOH
Upload Device
Information/Confirm
11
Write
X
99H
Write
X
DOH
Write
X
A7H
Write
X
DOH
RY /BY # Enable to
Level-Mode
8
Write
X
96H
Write
X
01H
RY/BY#
Pulse-an-Write
8
Write
X
96H
Write
X
02H
RY/BY#
Pulse-an-Erase
8
Write
X
96H
Write
X
03H
RY /BY # Disable
8
Write
X
96H
Write
X
04H
RY /BY # Pulse-OnWrite/Erase
8
Write
X
96H
Write
X
05H
Sleep
Write
X
FOH
Abort
Write
X
80H
ADDRESS
BA = Block Address
PA = Page Buffer Address
RA = Extended Register Address
WA = Write Address
X = Don't Care
Data
RA
Two-Byte Write
Erase All Unlocked
Blocks/Confirm
Oper Addr
Read
Page Buffer Write
to Flash
Lock Block/Confirm
Third Bus Cycle
DATA
AD = Array Data
PO = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
X
BCH
WC (L,H) = Word Count (Low, High)
BC (L,H) = Byte Count (Low, High)
WD (L,H) = Write Data (Low, High)
3-317
28F016SV FlashFile™ Memory
NOTES:
1. RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register memory maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect
the actual lock-bit status.
3. Ao is automatically complemented to load second byte of data. BYTE# must be at VIL. Ao value determines which
WD/BC is supplied first: Ao = 0 looks at the WDL/BCL, Ao = 1 looks at the WDH/BCH.
4. BCH/WCH must be at OOH for this product because of the 256-byte (128-word) Page Buffer size, and to avoid writing
the Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future
Page Buffer expandability.
5. In x16 mode, only the lower byte 000-7 is used for WCL and WCH. The upper byte DOa_15 is a don't care.
6. PA and PO (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure RY IBY # output to one of three pulse-modes or enable and disable the RY IBY # function.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page
Buffer. Refer to the 16-Mbit Flash Product Family User's Manual.
10. BCL'= OOH corresponds to a byte count of 1. Similarly, WCL = OOH corresponds to a word count of 1.
11. After writing the Upload Device Information command and the Confirm command, the following information is output at
Page Buffer addresses specified below:
Address
06H, 07H (Byte Mode)
03H (Word Mode)
1EH (Byte Mode)
OFH (DOO_7)(Word Mode)
1FH (Byte Mode)
OFH (DOa_15)(Word Mode)
Information
Device Revision Number
Device Revision Number
Device Configuration Code
Device Configuration Code
Device Proliferation Code (01 H)
Device Proliferation Code (01 H)
A page buffer swap followed by a page buffer read sequence is necessary to access this information. The contents of
all other Page Buffer locations, after the Upload Device Information command is written, are reserved for future implementation by Intel Corporation. See Section 4.8 for' a description of the Device Configuration Code. This code also
corresponds to data written to the 28F016SV after writing the RY IBY # Reconfiguration command.
3-318
28F016SV FlashFile™ Memory
4.5 Compatible Status Register
I
WSMS
7
lESS
6
I
ES
DWS
VPPS
R
5
4
3
2
CSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
o = Busy
R
R
o
NOTES:
RY /BY # output or WSMS bit must be checked to determine
completion of an operation (Erase, Erase Suspend, or Data
Write) before the appropriate Status bit (ESS, ES or DWS) is
checked for success.
CSR.6 = ERASE-SUSPEND STATUS
1 = Erase Suspended
o = Erase In Progress/Completed
CSR.5 = ERASE STATUS
1 = Error In Block Erasure
o = Successful Block Erase
CSR.4 = DATA-WRITE STATUS
1 = Error in Data Write
o = Data Write Successful
If DWS and ES are set to "1" during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
CSR.3= Vpp STATUS
1 = Vpp Error Detect, Operation
Abort
0= VppOK
The VPPS bit, unlike an AID converter, does not provide
continuous indication of Vpp level. The WSM interrogates
Vpp's level only after the Data Write or Erase command
sequences have been entered, and informs the system if
Vpp has not been switched on. VPPS is not guaranteed to
report accurate feedback between VpPLK(max) and
VPPH1 (min), between VPPH1 (max) and VpPH2(min) and
above VpPH2(max).
CSR.2-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.
3-319
28F016SV FlashFile™ Memory
4.6 Global Status Register
I
WSMS
?
I
OSS
I
6
DOS
DSS
QS
PBAS
5
4
3
2
GSR.? = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
PBS
PBSS
o
NOTES:
[1] RY IBY # output or WSMS bit must be checked to
determine completion of an operation (Block Lock,
Suspend, any RY IBY # reconfiguration, Upload Status
Bits, Erase or Data Write) before the appropriate Status
bit (OSS or DOS) is checked for success.
GSA.6 = OPERATION SUSPEND STATUS
1 = Operation Suspended
o = Operation in Progress I
Completed
GSA.5 = DEVICE OPERATION STATUS
1 = Operation Unsuccessful
o = Operation Successful or
Currently Running
GSA.4 = DEVICE SLEEP STATUS
1 = Device in Sleep
o = Device Not in Sleep
MATRIX 5/4
o0 = Operation Successful or
Currently Running
o 1 = Device in Sleep mode or
Pending Sleep
1 0 = Operation Unsuccessful
1 1 = Operation Unsuccessful or
Aborted
If operation currently running, then GSR.? = O.
If device pending sleep, then GSA.? = O.
Operation aborted: Unsuccessful due to Abort
command.
GSA.3 = QUEUE STATUS
1 = Queue Full
o = Queue Available
GSA.2 = PAGE BUFFER AVAILABLE STATUS
1 = One or Two Page Buffers
Available
o = No Page Buffer Available
GSR.1 = PAGE BUFFER STATUS
1 = Selected Page Buffer Ready
o = Selected Page Buffer Busy
The device contains two Page Buffers.
Selected Page Buffer is currently busy with WSM
operation
GSA.O = PAGE BUFFER SELECT STATUS
1 = Page Buffer 1 Selected
o = Page Buffer 0 Selected
NOTE:
1. When multiple operations are queued, checking BSR. 7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.
3-320
28F016SV FlashFile™ Memory
4.7 Block Status Register
I
BS
I
BLS
I
BOS
BOAS
QS
VPPS
5
4
3
2
6 .
7
BSR.7 = BLOCKSTATUS
1 = Ready
0= Busy
VPPL
R
o
NOTES:
[1] RY /BY# output or BS bit must be checked to
determine completion of an operation (Block Lock,
Suspend, Erase or Data Write) before the appropriate
Status bits (BOS or BLS) is checked for success.
BSR.6 = BLOCK LOCK STATUS
1 = Block Unlocked for Write/Erase
o = Block Locked for Write/Erase
BSA.5 = BLOCK OPERATION STATUS
1 = Operation Unsuc;:cessful
= Operation Successful or
Currently Running
o
BSA.4 = BLOCK OPERATION ABORT STATUS
1 = Operation Aborted
= Operation Not Aborted
o
MATRIX 514
0 = Operation Successful or
Currently Running
o 1 = Not a Valid Combination
1 0 = Operation Unsuccessful
1 1 = Operation Aborted
The BOAS bit will not be set until BSA. 7 = 1.
o
Operation halted via Abort command.
BSA.3 = QUEUE STATUS'
1 = Queue Full
o = Queue Available
BSA.2 = Vpp STATUS
1 = Vpp Error Detect, Operation Abort
0= VppOK
BSR.1 = Vpp LEVEL
1 = Vpp Detected at 5.0V ± 10%
= Vpp Detected at 12.0V ± 5%
o
BSR.1 is not guaranteed to report accurate feedback
between the VPPH1 and VpPH2 voltage ranges. Writes
and erases with Vpp between VpPLK(max) and VpPH1
(min), between VPPH1 (max) and VpPH2(min), and above
VpPH2(max) produce spurious results and should not be
attempted.
BSR.1 was a RESERVED bit on the 28F016SA.
BSR.O = RESERVED FOR FUTURE ENHANCEMENTS
This bit is reserved for future use; mask it out when pOlling the BSRs.
NOTE:
1. When multiple operations are queued, checking BSR. 7 only provides indication of completion for that particular block.
GSR.7 provides indication when al\ queued operations are completed.
3-321
28F016SV FlashFlle™ Memory
4.8 Device Configuration Code
I
R
7
I
R
6
I
R
5
I
R
R
RB2
4
3
2
RB1
RBO
o
NOTES:
DCC.2-DCC.0 = RY/BY# CONFIGURATION Undocumented combinations of RB2-RBO are reserved by
Intel Corporation for future implementations and should not
(RB2-RBO)
001 = Level Mode (Default) be used.
010 = Pulse-an-Write
011 = Pulse-an-Erase
100 = RYIBY # Disabled
101 = Pulse-On-Writel
Erase
DCC.7-DCC.3 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when reading the Device Configuration Code. Set
these bits to "0" when writing the desired RYIBY # configuration to the device.
3-322
28F016SV FlashFile™ Memory
5.0 ELECTRICAL SPECIFICATIONS
5.1 Absolute Maximum Ratlngs*
+ sooe
+ 125°e
Temperature Under Bias ..•.......•. ooe to
Storage Temperature •...•••••• -65°e to
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Vee = 3.3V ± 0.3V Systems(5)
Symbol
Parameter
Notes
Min
Max
Units
Test Conditions
1
0
70
C
Ambient Temperature
TA ,
Operating Temperature, Commercial
Vee
Vee withRespect to GND
2
-0.2
7.0
V
Vpp
Vpp Supply Voltage with Respect to GND
2,3
-0.2
14.0
V
V
Voltage on any Pin (except Vee, Vpp) with
Respect to GND
2
-0.5
Vee
V
±30
rnA
100
rnA
Max
Units
Test Conditions
Ambient Temperature
I
Current into any Non-Supply Pin
lOUT
Output Short Circuit Current
Vee = 5.0V ± 0.5V,5.0V
Symbol
+ 0.5
4
± 0.25V Systems(5,6)
Parameter
Notes
Min
TA
Operating Temperature, Commercial
1
0
70
°C
Vee
Vee with Respect to GND
2
-0.2
7.0
V
Vpp
Vpp Supply Voltage with Respect to GND
2,3
-0.2
14.0
V
V
Voltage On any Pin (except Vce, Vpp) with
Respect to GND
2
-2.0
7.0
V
I
Current into any Non-Supply Pin
± 30
rnA
lOUT
Output Short Circuit Current
100
rnA
4
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vcc + 0.5V which, during transitions, may overshoot to Vee +
2.0V for periods <20 ns.
3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. AC specifications are valid at both voltage ranges. See De Characteristics tables for voltage range-specific specifications.
6.5% Vee specifications refer to the 28F016SV-065 and 28F016SV-070 in its high speed test configuration.
3-323
28F016SV FlashFile™ Memory
5.2 Capacitance
For a 3.3V
Symbol
± 0.3V System:
Parameter
Notes
Typ
Max
Units
Test Conditions
CIN
Capacitance Looking into an
Address/Control Pin
1
6
8
pF
TA = 25°C, f = 1.0 MHz
CC;>UT
Capacitance Looking into an
Output Pin
1
8
12
pF
TA = 25°C, f = 1.0 MHz
CI.OAD
Load Capacitance Driven by
Outputs for Timing Specifications
50
pF
1,2
For 5.0V ± 0.5V, 5.0V ± 0.25V System:
Symbol
Parameter
Notes
Typ
Max
Units
Test Conditions
CIN
Capacitance Looking into an
Address/Control Pin
1
6
8
pF
TA = 25°C, f =1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
8
12
pF
TA = 25°C, f = 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
100
pF
ForVcc = 5.0V
30
pF
ForVcc= 5.0V ± 0.25V
1,2
± 0.5V
NOTE:
1. Sampled, not 100% tested. Guaranteed by design.
2. Intel is currently developing more accurate models for the Transient Equivalent Testing Load Circuits. For more informa·
tion or to. obtain iBIS models, please contact your local Intel/Distribution Sales Office.
3-324
28F016SV FlashFile™ Memory
I_NP_U_T_JX:::
2.4 _ _
0.45
>
TEST POINTS
'5
<:
2.0
OUTPUT
O.B
290528-7
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at
VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 7. Transient Input/Output Reference Waveform for
Vee = 5.0V ± 10% (Standard Testing Configuration)(1)
::: __I_NP_U_T_JX.5 +-- T~T POINTS ---+
1.5 OUTPUT
290528-8
AC test inputs are driven at 3.0V for a Logic "1" and O.OV for a Logic "0." Input timing begins, and output timing ends, at
1.5V. Input rise and fall times (10% to 90%) <10 ns.
Figure 8. Transient Input/Output Reference Waveform for Vee = 3.3V ± 0.3V
and Vee = 5.0V ± 5% (High Speed Testing Configuration)(2)
NOTES:
1. Testing characteristics for 28F016SV·070 (Standard Testing Configuration) and 28F016SV-OBO.
2. Testing characteristics for 28F016SV-065/28F016SV-075 and 28F016SV-70 (High Speed Testing Configuration)1
28F016SV-120.
.
3-325
28F016SV FlashFile™ Memory
2.S ns of 2sn Transmission Line
.From Output
Under Test
( )
Test
Point •
290528-9
Total Capacitance = 100 pF
Figure 9. Transient Equivalent Testing Load Circuit
(28F016SV-070/-080 at Vee = s.OV ± 10%)
2.S ns of son Transmission Line
.From Output
Under Test
()
Test
Point •
290528-10
Total Capacitance = 50 pF
Figure 10. Transient Equivalent Testing Load Circuit
(28F016SV-07S/-120 at Vee = 3.3V ± 0.3V)
2.S ns of 83n Transmission Line
• From Output
Under Test
()
Test .
Point •
290528-11
Total Capacitance = 30 pF
Figure 11. High Speed Transient Equivalent Testing Load Circuit
(28F016SV-065/-070 at Vee = 5.0V ± S%) .
3-326
28F016SV FlashFlle™ Memory
5.3 DC Characteristics
vee
=
3.3V
Symbol
± 0.3V, TA =
O·C to
+ 70·C
Parameter
Notes
Max
Units
III
Input Load Current
1
1
p.A
Vee = Vee Max,
VIN = Vee or GND
ILO
Output Leakage
Current
1
10
p.A
Vee = Vee Max,
VOUT = Vee or GND
Ices
Vee Standby
Current
70
130
p.A
Vee = Vee Max,
CEo#,CE1#,RP# = Vee ±
0.2V
BYTE#, WP# = Vee ± 0.2V
orGND ± 0.2V
1
4
rnA
Vee = Vee Max,
CEo#,CE1#,RP# = VIH
BYTE#, WP# = VIH or VIL
1,5
Min
Typ
Test Conditions
IceD
Vee Deep PowerDown Current
1
2
5
p.A
RP# = GND ± 0.2V
BYTE# = Vee ± 0.2Vor
GND ± 0.2V
leeR1
Vee Read Current
1,4,5
40
50
rnA
Vee = Vee Max
CMOS: CEo#, CE1 # = GND
± 0.2V
BYTE# = GND ± 0.2Vor
Vee ± 0.2V
Inputs = GND ± 0.2V or Vee
± 0.2V
TIL: CEo #, CE1 # = VIL,
BYTE# = VILorVIH
INPUTS = VIL or VIH,
f = 8 MHz, lOUT = 0 rnA
leeR2
Vee Read Current
1,4,
5,6
20
30
rnA
Vee = Vee Max
CMOS: CEo#, CE1 # = GND
± 0.2V
BYTE# = GND ± 0.2Vor
Vee ± 0.2V
Inputs = GND ± 0.2V or Vee
± 0.2V
TIL: CEo#, CE1 # = VIL,
BYTE# = VIL or VIH
INPUTS = VIL or VIH,
f = 4 MHz, lOUT = 0 rnA
3-327
28F016SV FlashFile™ Memory
5.3 DC Characteristics (Continued)
Vee = 3.3V ± 0.3V, TA = O·C to
Symbol
leew
IeeE
Parameter
Vee Write Current
Vee Block Erase
Current
+ 70·C
Typ
Max
Units
Test Conditions
8
12
rnA
Word/Byte Write in Progress
Vpp = 12.0V ± 5%.
8
17
rnA
Word/Byte Write in Progress
Vpp = 5.0V ± 10%.
6
12
rnA
Block Erase in Progress
Vpp = 12.0V± 5%.
9
17
rnA
Block Erase in Progress
Vpp = 5.0V ± 10%.
1,2
1
4
rnA
CEo#,CE1# = VIH
Block Erase Suspended
± 1
± 10
Vpp!"': Vee
30
50
Notes
Min
1,6
1,6
leeES
Vee Erase
Suspend Current
Ipps
Vpp Standby/Read
Current
1
IpPD
Vpp Deep PowerDown Current
1
0.2
5
p.A
p.A
p.A
Ippw
Vpp Write Current
1,6
10
15
rnA
Vpp = 12.0V ± 5%.
Word/Byte Write in Progress
15
25
rnA
Vpp = 5.0V ± 10%.
Word/Byte Write in Progress
4
10
rnA
Vpp = 12.0V ± 5%
Block Erase in Progress
14
20
rnA
Vpp = 5.0V ± 10%
Block Erase in Progress
30
50
p.A
Vpp = VPPH1 or VpPH2,
Block Erase Suspended
0.8
V
Vee
V
0.4
V
IpPR
IpPE·
IpPES
Vpp Erase Current
Vpp Erase
Suspend Current
1,6
1
VIL
Input Low Voltage
6
-0.3
VIH
Input High Voltage
6
2.0
VOL
Output Low
Voltage
3-328
Vpp> Vee
RP#
=
GND ± 0.2V
+ 0.3
6
Vee'" Vee Min and
IOL = 4 rnA
28F016SV FlashFlle™ Memory
5.3 DC Characteristics (Continued)
Vee = 3.3V
Symbol
VOH 1
±
0.3V, T A = O·C to
Parameter
Output High
Voltage
VOH 2
+ 70·C
Typ
Notes
Min
Units
Test Conditions
6
2.4
V
IOH = -2.0 rnA
Vee = Vee Min
6
Vee
-0.2
V
IOH = -100 p.A
Vee = Vee Min
3,6
0.0
VPPLK
Vpp Erase/Write
Lock Voltage
VPPH1
Vppduring
Write/Erase
Operations
3
4.5
VPPH2
Vppduring ,
Write/Erase
Operations
3
11.4
VLKO
Vee Erase/Write
Lock Voltage
2.0
Max
1.5
V
5.0
5.5
V
12.0
12.6
V
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = 3.3V, Vpp = 12.0V or 5.0V, T = 25'C. These
currents are valid for all product versions (package and speeds).
2. leeEs is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of leeEs and leeR.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when Vpp s: VPPLK and not guaranteed in the
. ranges between VpPLK(max) and VpPH1(min), between VpPH1(max) and VpPH2(min) and above VpPH2(max).
4. Automatic Power Savings (APS) reduces leeR to 3.0 rnA typical in static operation.
5. CMOS Inputs are either Vee ± 0.2V or GND ± 0.2V. TIL Inputs are either VIL or VIH.
6. Sampled, but not 100% tested. Guaranteed by design.
3-329
28F016SV FlashFlle™ Memory
5.4 DC Characteristics
vee = 5.0V ± O.5V, 5.0V ± O.25V, TA = O·C to +70·C
Symbol
Parameter
Notes
III
Input Load Current
ILO
Output Leakage
Current
lees
Vee Standby
Current
Min
Typ
Max
Units
1
±1
p.A
Vee = Vec Max
VIN = Vee or GND
1
± 10
p.A
Vee = Vee Max
VOUT ,:,. Vee or GND
70
130
p.A
Vee = Vee Max
CEo#,CE1#,RP# = Vee ± 0.2V
BYTE#, WP# =Vee ± 0.2V
orGND ± Q.2V
2
4
rnA
Vee = Vee Max
CEo#,CE1#,RP# = VIH
BYTE#; WP#= VIH orVIL
1,5
Test Conditions
leeD
Vee Deep PowerDown Current
1
2
5
p.A
RP# = GND ± 0.2V
BYTE# = Vee ± 0.2Vor
GND ± 0.2V
lecR1
Vee Read Current
1,4,5
75
95
rnA
Vee = Vee Max,
CMOS: CEo#, CE1 # = GND
± 0.2V
BYTE # = GND ± 0.2V
or Vee ± 0.2V
Inputs = GND ± 0.2Vor
Vee ± O.2V
TTL: CEo#, CE1# = VIL,
BYTE# = VILorVIH.
InputS = VIL or VIH,
f = 10 MHz, lOUT
0 rnA
leeR2
Vee Read Current
1,4,
5,6
45
55
rnA
Vee = Vee Max,
CMOS:CEo#, CE1 # = GND
± 0.2V
BYTE# = GND ± 0.2V
orVee ± 0.2V
Inputs = GND ± 0.2Vor
Vee ± 0.2V
TTL: CEo#, CE1# = VIL,
BYTE # = VIL or VIH
Inputs = VIL or VIH,
f = 5 MHz, lOUT = 0 rnA
=
3-330
28F016SV FlashFile™ Memory
5.4 DC Characteristics (Continued)
Vce
=
5.0V ± 0.5V, 5.0V ± 0.25V, TA
Symbol
Iccw
ICCE
Parameter
Vee Write Current
Vee Block Erase
Current
=
Notes
O°C to + 70°C
Min
Typ
Max
Units
25
35
rnA
Word/Byte in Progress
Vpp = 12.0V ± 5%
25
40
rnA
Word/Byte in Progress
Vpp = 5.0V ± 10%
18
25
rnA
Block Erase in Progress
Vpp = 12.0V ± 5%
20
30
rnA
Block Erase in Progress
Vpp = 5.0V ± 10%
1,2
2
4
rnA
CEo#,CE1# = VIH
Block Erase Suspended
/-LA
Vpp
1,6
1,6
I
Test Conditions
lecES
Vec Erase
Suspend Current
IpPS
Vpp Standby/Read
Current
1
±1
± 10
30
50
/-LA
Vpp> Vee
IpPD
Vpp Deep PowerDown Current
1
0.2
5
/LA
RP#
Ippw
Vpp Write Current
1,6
7
12
rnA
Vpp = 12.0V ± 5%
. Word/Byte Write in Progress
17
22
rnA
Vpp = 5.0V ± 10%
Word/Byte Write in Progress
5
10
rnA
Vpp = 12.0V ± 5%
Block Erase in Progress
16
20
rnA
Vpp = 5.0V ± 10%
Block Erase in Progress
30
50
/LA
Vpp = VPPH1 or VPPH2,
Block Erase Suspended
IpPR
-.
IpPE
Vpp Block Erase
Current
1,6
IpPES
VppErase
Suspend Current
1
VIL
Input Low Voltage
6
-0.5
0.8
V
VIH
Input High Voltage
6
2.0
Vee
+0.5
V
s: Vee
=
GND ± 0.2V
3-331
28F016SV FlashFile™ Memory
5.4 DC Characteristics (Continued)
Vee = 5.0V ± 0.5V, 5.0V ± 0.25V, TA = O·C to
Symbol
VOL
VOH 1
Parameter
Min
Output Low
Voltage
6
Output High
Voltage
6
0.85
Vee
6
Vee
-0.4
3,6
0.0
VOH 2
VPPLK
Notes
+ 70·C
Vpp Write/Erase
Lock Voltage
Typ
Max
Units
Test Conditions
0.45
V
Vee = Vee Min
IOL = 5.8mA
V
IOH = -2.5mA
Vee = Vee Min
IOH = -100/-LA
Vee = Vee Min
1.5
V
VPPH1 .
Vppduring
Write/Erase
Operations
4.5
5.0
5.5
V
VPPH2
Vppduring
Write/Erase
Operations
11.4
12.0
12.6
V
Vee Write/Erase
Lock Voltage
2.0
VLKO
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, VPP = 12.0V or 5.0V, T = 25·C. These
currents are valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and I C C R . .
.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when VPP s: VPPLK and not guarant~d in the
ranges between VpPLK(max) and VpPH1(min), between VpPH1(max) and VpPH2(min) and above VpPH2(max).
4. Automatic Power Saving (APS) reduces ICCR to 1 mA typical in Static operation.
5. eMOS Inputs are .either Vcc ± 0.2V or GND ± 0~2V. TIL Inputs are either VIL or VIH .
. 6. Sampled, not 100% tested. Guaranteed by design.
3-332
28F016SV FlashFile™ Memory
5.5 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.SV.
For, S.OV systems use the standard JEDEC cross point definitions (standard testing) or from where signals
cross 1.SV (high speed testing).
Each timing parameter consists of S characters. Some common examples are defined below:
teE
toE
tELQV time(t) from CE# (E) going low (L) to the outputs (Q) becoming valid (V)
tGLQV time(t) from OE # (G) going low (L) to the outputs (Q) becoming valid (V)
tAee
tAS
tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H)
tDH
tWHDX time(t) from WE# (W) going high (H) to when the data (D) can become undefined (X)
Pin Characters
Pin States
A
Address Inputs
H
High
0
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
CE# (Chip Enable)
X
Driven, but Not Necessarily Valid
Z
High Impedance
F
BYTE # (Byte Enable)
G
OE # (Output Enable)
W
WE# (Write Enable)
P
RP# (Deep Power-Down Pin)
R
RY / BY # (Ready Busy)
V
Any Voltage Level
SV
Vee at 4.SV Minimum
3V
Vee at 3.0V Minimum
3-333
28F016SV FlashFile™ Memory
5.6 AC Characteristics-Read Only Operations(1)
vee
=
3.3V ± 0.3V, TA
=
O·C to
+ 70·C
Verslons(S)
Sym
tAVAV
Parameter
Notes
Read Cycle Time
tAvav
Address to Output Delay
tELav
CE # to Output Delay
28F016SV-075
28F016SV-120
Min
Min
Max
75
2,8
tpHQV
RP# High to Output Delay
tGLQV
OE # to Output Delay
tELQX
CE # to Output in Low Z
3,8
tEHQZ
CE # to Output in High Z
3,8
tGLQX
OE # to Output in Low Z
3
tGHQZ
OE# to Output in High Z
3
tOH
Output Hold from Address,
CE # or OE # Change,
Whichever Occurs First
2
3,8
Units
Max
120
ns
75
120
ns
75
120
ns
480
620
ns
40
45
ns
50
ns
0
0
30
0
ns
0
30
ns
30
0
0
ns
ns
BYTE # to Output Delay
3
75
120
ns
tFLQZ
BYTE # Low to Output
in HighZ
3
30
30
ns
tELFL
tELFH
CE# Low to BYTE#
High or Low
3,8
5
5
ns
tFLQV
. tFHQV
Extended Status Register Reads
tAVEL
Address Setup to CE #
GOing Low
3,4,8,9
0
0
ns
tAVGL
Address Setup to OE #
Going Low
3,4,9
0
0
ns
3-334
28F016SV FlashFile™ Memory
5.6 AC Characteristics-Read Only Operations(1) (Continued)
Vee
=
5.0V ± 0.5V, 5.0V ± 0.25V, TA
Yersions(S)
=
O°C to
+ 70°C
Yee± 5% 28F016SY·065(6) 28F016SY·070(6)
28F016SY·070(7) 28F016SY·080(7) Units
Yee ±10%
Sym
Parameter
Notes
tAVAV Read Cycle Time
Min
tAVQV Address to
Output Delay
tELQV CE # to Output Delay
2,8
2
tELQX CE # to Output in Low Z
3,8
tEHQZ CE# to Output in High Z
3,8
tGLQX OE # to Output in Low Z
3
tGHQZ OE# to Output in High Z
tOH
Output Hold from
Address, CE # or OE #
Change, Whichever
Occurs First
Min
Min
Max
80
70
ns
80
ns
65
70
80
ns
300
400(6)
300(7)
480
ns
30
30(6)
35(7)
35
ns
0
0
25
0
3
3,8
Max
70
65
tpHQV RP# to Output Delay
tGLQV OE # to Output Delay
Max
65
0
25
0
25
0
ns
30
0
25
0
ns
ns
30
0
ns
ns
tFLQV BYTE # to Output Delay
tFHQV
3
65
70
80
ns
tFLQZ BYTE # Low to Output in
HighZ
3
25
25
30
ns
3,8
5
5
5
ns
tELFL CE# Low to BYTE #
tELFH High or Low
Extended Status Register Reads
tAVEL Address Setup to CE #
GOing Low
3,4,8,9
0
0
0
ns
tAVGL Address Setup to OE#
GOing Low
3,4,9
0
0
0
ns
3-335
28F016SV FlashFile™ Memory
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figures 7 and 8.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE#, without impacting tELQV'
3. Sampled, not 100% tested. Guaranteed by design
4. This timing parameter is used to latch the correct BSR data onto the outputs.
5. Device speeds are defined as:
.
65/70 ns at Vee = 5.0V equivalent to
75 ns at Vee = 3.3V
70/80 ns at Vee = 5.0V equivalent to
120 ns at Vee = 3.3V
6. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
7. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
8. CEx,!, is defined as the latter of CEo# or CEl # going low, or the first of CEo# or CEl # going high.
9. The address setup requirement for Extended Status Registerreads must only be met referenced to the falling edge of the
last control signal to become active (CEo # , CEl # or OE#). For example, if CEo# and CEl # are activated prior to OE#
for an Extended Status Register read, specification tAVGL must be met. On the other hand, if either CEo# or CEl # (or
both) are activated after OE #, specification tAVEL must be referenced.
3-336
28F016SV FlashFile™ Memory
V cc POWER-UP
STANDBY
DEVICE AND
ADDRESS SELECTION
OUTPUTS ENABLED
STANDBY
DATA VALID
V CC POWER-DOWN
VIH
ADDRESSES STABLE
ADDRESSES (A)
VIL
1+--------
tAVAV----------t+t
V IH
CEx" (E)(')
V'L
V IH
OE" (G)
V'L
VIH
WE" (w)
V IL
VaH
HIGH Z
HIGH Z
DATA (D/O)
VOL
t+------tAvaV-----~
S.OV
Vee
GND
VIH
RP# (p)
V IL
1+------
)
t pHOV
------------+1
\
290528-12
NOTE:
GEx# is defined as the latter of GEo# or GEl # going low, or the first of GEo# or GEl # going high.
Figure 12. Read Timing Waveforms
3-337
28F016SV FlashFile™ Memory
v,"
ADDRESSES STAB.E
AODRESSSS(A)
v"
v,"
CExf(E/')
v"
v,"
OE'(G)
v"
v,"
BYTEJO(F)
V'L
VOH
DATA (DQ()..[)Q7)
HIGHZ
VOL
VOH
DATA (DQ8-OQ1S)
HIGHZ-
HGHZ
VOL
290528-13
NOTE:
CEx# is defined as the latter of CEo# or CE1 # going low, or the first of CEo# or CE1 # going high.
Figure 13. BYTE # Timing Waveforms
3-338
28F016SV FlashFile™ Memory
5.7 Power-Up and Reset Timings
V=POWER-UP
\
J
RP#
/
(P)
s.ov
L7
3.3V
Vee
(3V,SV)
ADDRESS
(A)
DATA
(a)
-OV
3.0V
~
V
tSVA-J
~
~
t3VA-J
tA-5V
1.11111
VALID
II 111111111111111
~OV
~
VALID
[llOU lX
[I [I
--
VALID
3.3VOUTPUTS
...e:.VOV
/
[+---t
4--t
tA-iOV
tA-iOV
VALID
s.OV OUTPUTS
290S28-14
Figure 14. Vee Power-Up and RP# Reset Waveforms
Symbol
tpL5V
Parameter
RP# Low to Vcc at 4.SV (Minimum)
tpL3V
RP# Low to Vcc at 3.0V (Minimum)
tAVQV
Address Valid to Data Valid for Vcc
=
=
S.OV
S.OV
± .10%
± 10%
Notes
Min
2
0
2
0
3
Max
J.l.s
J.l.s
70
3
Units
300
ns
tpHQV
RP# High to Data Valid for Vcc
t5VPH
Vcc at 4.SV (Minimum) to RP# High
1
2
J.l.s
ns
t3VPH
Vcc at 3.0V (Minimum) to RP# High
1
2
J.l.s
NOTES:
CEo # • CE1 # and OE# are switched low after Power-Up.
1. The tSVPH and/or t3VPH times must be strictly followed to guarantee all other read and write specifications for the
28F016SV.
2. The power supply may start to switch concurrently with RP# going low.
3. The address access time and RP# high to data valid time are shown for 5.0V Vee operation of the 28F016SV-070
(Standard Test Configuration). Refer to the AC Characteristics-Read Only Operations for 3.3V Vee and 5.0V Vee (High
Speed Test Configuration) values.
3-339
28F016SV FlashFile™ Memory
5.8 AC Characteristics for WE #-Controlled Command Write Operations(1)
vee =
3.3V
± 0.3V, TA =
OOG to
+ 700G
28F016SV-075
Versions
Symbol
Parameter
Notes
tAvAV
Write Cycle Time
tVPWH
VPP Setup to WE# Going High
3
tpHEL
RP# Setup to GE# Going Low
3,7
tELWL
GE # Setup to WE # Going Low
3,7
tAVWH
Address Setup to WE# Going High
2,6
tovwH
Data Setup to WE # Going High
2,6
tWLWH
WE# Pulse Width
Min
Typ
Max
28F016SV-120
Min
Typ
Units
Max
120
ns
100
100
ns
480
480
ns
0
10
ns
60
75
ns
60
75
ns
60
75
ns
75
tWHOX
Data Hold from WE# High
2
5
10
ns
tWHAX
Address Hold from WE # High
2
5
10
ns
5
10
ns
15
45
ns
tWHEH
GE# Hold from WE# High
tWHWL
WE# Pulse Width High
3,7
0
Read Recovery before Write
3
tWHRL
WE # High to RY IBY # Going Low
3
tRHPL
RP# Hold from Valid Status
Register (GSR, GSR, BSR) Data
and RY IBY # High
3
0
0
ns
tPHWL
RP# High Recovery to WE#
Going Low
3
0.480
1
,""S
tWHGL
Write Recovery before Read
3
55
95
ns
0
0
taVVL
Vpp Hold from Valid Status Register
(GSR, GSR, BSR) Data and
RY/BY# High
tWHOV1
Duration of Word/Byte
Write Operation \
tWHOV2
Duration of Block Erase Operation
3·340
3
0
ns
tGHWL
100
100
ns
,",,5
,
3,4,5
5
9
TBD
5
9
TBD
,""S
3,4
0.3
0.8
10
0.3
0.8
10
sec
28F016SV FlashFile™ Memory
5.8 AC Characteristics for WE#-Controlled Command Write Operations(1)
(Continued)
Vee
= 5.0V ± 0.5V, 5.0V ± 0.25V, TA = O°C to + 70°C
Versions(B)
Vee ± 5%
28F016SV-065(9)
Vee ± 10%
Sym
Parameter
Notes
Write Cycle
Time
28F016SV-070(9)
28F016SV-070(10)
Min
Typ
Max
Min
Typ
Max
28F016SV-080(10)
Min
Typ
Units
Max
65
70
80
ns
3
100
100
100
ns
tpHEL RP# Setup to
CE # Going Low
3,7
300
480(9)
300(10)
480
ns
tELWL CE# Setup to
WE# Going Low
3,7
0
0
0
ns
tAVWH Address Setup
toWE# Going
High
2,6
40
50(9)
40(10)
50
ns
tDvwH Data Setup
toWE# Going
High
2,6
40
50(9)
40(10)
50
ns
40
40(9)
45(10)
50
ns
tAVAV
tVPWH Vpp Setup to
WE# Going
High
tWLwH WE# Pulse
Width
tWHDX Data Hold from
WE# High
2
0
0
0
ns
tWHAX Address Hold
from WE# High
2
5
10
10
ns
tWHEH CE # Hold from
WE# High
3,7
5
10(9)
5(10)
10
ns
15
30(9)
15(10)
30
ns
0
0
0
ns
tWHWL WE# Pulse
Width High
tGHWL Read Recovery
before Write
3
tWHRL WE# High to
RY IBY # Going
Low
3
RP# Hold from
Valid Status
Register (CSR,
GSR, BSR)
Data and
RY/BY# High
3
tRHPL
100
0
100
0
100
0
ns
ns
3-341
28F016SV FlashFjle™ Memory
5.8 AC Characteristics for WE#-Controlled Command Write Operations(1)
(Continued)
Vcc
=
5.0V
±
0.5V, 5.0V
Versions(8)
Sym
±
0.25V, T A
=
O°C to
+ 70°C
Vee ± 5% 28FO 16SV·065(9)
28F016SV-070(9)
Vee ± 10%
28F016SV-070(10)
28F016SV-080(10)
Units
Parameter
Notes
Min
RP# High
Recovery to
WE # Going Low
3
0.300
tWHGL
Write Recovery
before Read
3
55
!aWL
Vpp Hold from
Valid Status
Register (CSR,
GSR,BSR)
Data and
RY/BY# High
3
0
3,4,5
4.5
6
TBD
4.5
6
TBD
4.5
6
TBD
,""S
3,4
0.3
0.6
10
0.3
0.6
10
0.3
0.6
10
sec
tPHWL
tWHQV1 Duration of
Word/Byte Write
Operation
tWHQv2 Duration of
Block Erase
Operation
Typ Max
Min
Typ Max
1(9)
Min
Typ
,""S
60
65
ns
0
0
,""S
0.300(10)
NOTES:
1. Read timings during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, not 100% tested. Guaranteed by design.
4. Write/Erase durations are measured to valid Status Register (CSR) Data. Vpp = 12.0V ± 0.6V.
5. Word/Byte Write operations are typically performed within 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE# for all Command Write operations.
7. CEx# is defined as the latter of CEo# or CE1 # gOing low, or the first of CEo# or CE1 # gOing high.
B. Device speeds are defined as:
65/70 ns at Vee = 5.0V equivalent to
75 ns at Vce = 3.3V
70/80 ns at Vee = 5.0V equivalent to
120 ns at Vee = 3.3V
9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
3-342
Max
1
28F016SV FlashFile™ Memory
AUTOtJATEODATA-WRITE
WRITE READ EXTENDED
OR ERASE DElAY
REGISTER COMWND
READ EXTENDED
_STATUS REGISTER DATA
READ COMPATIBLE
STATUS REGISTER CATA
V IH
NOTE3
ADDRESSES (A)
NOTE2 VI
_._--_ ..
V IH
CEx'(E)
VOL
NOTE 4
lWHGL
V IH
DEI (G)
VOL
t WHQV1
V IH
WE.('N)
VOL
V ,H
DATA(OIQ)
VOL
lr-___________--t-'"'-_-"JtWHRL
V OH
RYIBY'(R)
VOL
V ,H
RPf(P)
VOL
VPPH2
VppM VpPH1
VpPLK
VOL
NOTE 7
290528-15
NOTES:
1. This address string depicts Data Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data Write/ Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data Write/Erase operations.
4. CEx# is defined as the latter of CEo# or CEl # going low or the first of CEo# or CEl # going high.
5. RP # low transition is only to show tRHPL; not valid for above Read and Write cycles.
6. Vpp voltage during Write/Erase operations valid at both 12.0V and 5.0V.
7. Vpp voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 15. AC Waveforms for Command Write Operations
I
3-343
28F016SV FlashFlle™ Memory
5.9 AC Characteristics for CE#-Controlled Command Write Operations(1)
vee =
3.3V ± 0.3V, TA
=
O°C
+ 70°C
Versions
Sym
Parameter
tAVAV
Write Cycle Time
tVPEH
Vpp Setup to CE# Going High
28F016SV-075
Typ
Max
28F016SV-120
Min
Units
Notes
Min
75
120
ns
3,7
100
100
ns
Typ
Max
tpHWL
RP# Setup to WE# Going Low
3
480
480
ns
tWLEL
WE # Setup to CE # Going Low
3,7
0
0
ns
tAVEH
Address Setup to CE# Going High
2,6,7
60
75
ns
tDVEH
Data Setup to CE# Going High
2,6,7
60
75
ns
tELEH
CE # Pulse Width
7
60
75
ns
tEHDX
Data Hold from CE # High
2,7
10
10
ns
tEHAX
Address Hold from CE # High
2,7
10
10
ns
tEHWH
WE hold from CE# High
3
5
10
ns
tEHEL
CE# Pulse Width High
7
15
45
ns
tGHEL
Read Recovery before Write
3
0
0
ns
tEHRL
CE # High to RY IBY # Going Low
tRHPL
RP# Hold from Valid Status Register
(CSR, GSR, BSR) Data and
RY/BY# High
-
3,7
100
100
ns
3
0
0
ns
tpHEL
RP # High Recovery to CE #
Going Low
3,7
0.480
1
Jks
tEHGL
Write Recovery before Read
3
55
95
ns
tQWL
Vpp Hold from Valid Status Register
(CSR, GSR, BSR) Data and
RY/BY# High
3
0
0
Jks
tEHQV1
Duration of Word/Byte
Write Operation
tEHQV2
Duration of Block Erase Operation
3-344
..
3,4,5
5
9
TBD
5
9
TBD
Jks
3,4
0.3
0.8
10
0.3
0.8
10
sec
28F016SV FlashFile™ Memory
5.9 AC Characteristics for CE#-Controlled Command Write Operations(1)
(Continued)
Vee = 5.0V ± 0.5V, 5.0V ± 0.25V, T A = 0° to
Versions(B)
Vee ± 5%
+ 70°C
28F016SV-065(9)
Sym
Parameter
Notes
tAVAV Write Cycle
Time
28F016SV-070(9)
28FO16SV-070(10)
Vee ± 10%
Min
Typ
Max
Min
Typ Max
28F016SV-080(10)
Min
Typ
Units
Max
65
70
80
ns
tVPEH Vpp Setup to
CE # Going High
3,7
100
100
100
ns
tPHWL RP# Setup to
WE # Going Low
3
300
480(9)
300(10)
480
ns
tWLEL WE# Setup to
CE# Going Low
3,7
0
0
0
ns
tAVEH Address Setup
toCE# Going
High
2,6,7
40
50(9)
45(10)
50
ns
tDVEH Data Setup to
CE # Going High
2,6,7
40
50(9)
45(10)
50
ns
7
40
40(9)
45(10)
50
ns
tEHDX Data Hold from
CE# High
2,7
0
0
0
ns
tEHAX Address Hold
from CE # High
2,7
10
10
10
ns
tEHWH WE Hold from
CE# High
3,7
5
10(9)
5(10)
10
ns
tEHEL CE# Pulse
Width High
7
15
30(9)
15(10)
30
ns
tGHEL Read Recovery
before Write
3
0
0
0
ns
tEHRL CE# High to
RY IBY # Going
Low
3,7
tRHPL RP# Hold from
Valid Status
Register (CSR,
GSR, BSR)
Data and
RY/BY# High
3
tELEH
CE# Pulse
Width
100
0
100
0
100
0
ns
ns
3-345
28F016SV FlashFile™ Memory
5.9 AC Characteristics for CE #-Controlled Command Write Operations(1)
(Continued)
Vcc
=
5.0V
±
0.5V, 5.0V
Versions(8)
±
0.25V, T A
O· to
+ 70·C
Vee ± 5% 28F016SV·065(9)
Vee
Sym
=
± 10%
28F016SV-070(9)
28F016SV-070(10)
Parameter
Notes
Min
3,7
0.300
tEHGL
Write Recovery
before Read
3
55
tOVVL
Vpp Hold from
Valid Status
Register (CSR,
GSR, BSR)
Data at RY /BY #
High
3
0
3,4,5
4.5
6
TBD
4.5
6
TBD
4.5
6
TBD
,..,s
3,4
0.3
0.6
10
0.3
0.6
10
0.3
0.6
10
sec
tEHOV 1 Duration of
Word/Byte Write
Operation
tEHOV2 Duration of
Block Erase
Operation
Min
Typ Max
1(9)
Min
Typ
Units
RP# High
Recovery to
CE # Going Low
tpHEL
Typ Max
28F016SV-080(10)
,..,s
60
65
ns
0
0
,..,s
0.300(10)
NOTES:
1. Read timings during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, not 100% tested. Guaranteed by design.
4.Write/Erase durations are measured to valid Status Data. Vpp = 12.0V ± 0.6V.
5. Word/Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CE # for all Command Write Operations.
7. CEx# is defined as the latter of CEo# or CE1 # going low, or the first of CEo# or CE1 # gOing high.
8. Device speeds are defined as:
65/70 ns at Vee = 5.0V equivalent to
75 ns at Vee = 3.3V
70/80 ns at Vee = 5.0V equivalent to
120 ns at Vee = 3.3V
9. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
10. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
3·346
Max
1
28F016SV FlashFile™ Memory
DEEP
POWER-DOWN
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
WRITE VAUD ADORESS
&DATA(OATA-WRITE)OR
ERASE CONFIRM COt.O.WlO
~~
NOTE 1
AUTOMATEDDATA-WRrTE
OR ERASE DELAY
WRITE READ EXTENDED
READ EXTENDED
REGISTER COMMAND
STATUS REGISTER DATA
~~~,-------A'---lRA~~
READ COWATlBL£
STATUS REGISTER DATA
NOTEJ
V ,H
ADDRESSES (A)
NOTE 2 V"
_
HH
V ,H
_(W)
V"
t EHGL
V ,H
DEI (a)
VIL
leHQV12
ce.t(E)
V ,H
V"
NOTE.
V ,H
DATA{Oo'Q}
VIL
V OH
FWIBYI(R)
VOL
""",P)
V ,H
V"
V_
\/ppM
v Pptu
v pPLK
NOTE'
v"
NOTE7
290528-16
NOTES:
1. This address string depicts Data Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data Write/Erase operations.
4. CEx# is defined as the latter of CEo# or CE1 # going low or the first of CEo# or CE1 # gOing high.
5. RP# low transition is only to show tRHPL; not valid for above Read and Write cycles.
6. Vpp voltage during Write/Erase operations valid at both 12.0V and 5.0V.
7. Vpp voltage equal to or below VPPLK provides complete flash memory array protection.
Figure 16. Alternate AC Waveforms for Command Write Operations
3·347
28F016SV FlashFile™ Memory
5.10 AC Characteristics for WE #-Controlled Page Buffer Write Operations(1)
vee = 3.3V ± O.3V, TA = o·e to
+ 70·e
Versions
28F016SV-075
Parameter
I
I Notes
tAVWL I Address Setup to WE# Going Low I 2
Sym
Vee = 5.0V ± O.5V, 5.0V ± O.25V, T A
Verslons(8)
Vee
± 5%
=
o·e to
Min
I
o
I
Parameter
28F016SV-065(9)
!AVWL Address Setup
toWE# Going
Low
Notes
Min
2
0
I Max
Min
I
0
Typ
I
Units
Max
I
ns
Typ
Max
28F016SV-070(9)
28F016SV-070(10)
28FO'16SV-080(10)
Min
Min
Typ
Max
0
NOTES:
1. All. other specifications for WE # Controlled Write Operations can be found in Section 5.8,
2. Address must be valid during the entire WEll' low pulse.
3. Device speeds are defined as:
65170 ns at Vee = 5.0V equivalent to
75 ns at Vee = 3.3V
70/80 ns at Vee. = 5.0V equivalent to
120 ns at Vee = 3.3V
4. See the high speed AC Input/Output Reference Waveforms and AC Testing Load Circuit.
5. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
3·348
I
I
+ 70·e
Vee ± 10%
Sym
Typ
28F016SV-120
0
Typ
Units
Max
ns
infel®
28F016SV FlashFile™ Memory
~H
tWHEH
CE>tI(E)
V 1L
tELWL
~H
tWHWL
WEll (W)
V 1L
I WLWH
IWHAX
V 1H
ADCRESSES (A)
VAUD
V 1L
to\IWH
---{
~H
DATA(DIQ}
HIGHZ
V 1L
290528-17
NOTE:
1. CEx# is defined as the latter of CEo;ll or CE1;11 going low, or the first of CEo;ll or CE1;11 going high.
Flgu-:e 17. WE#-Controlled Page Buffer Write Timing Waveforms
.
(Loading Data to the Page Buffer)
3-349
28F016SV FlashFile™ Memory
5.11 AC Characteristics for CE #-Controlled Page Buffer Write Operations(1)
vcc
= 3.3V
±
0.3V; T A = OOG to
+ 700G
Versions
28F016SV-075
Sym
Parameter
Notes
Min
tAVEL
Address Setup to GE #
Going Low
2,3
0
VCC
=
5.0V
±
0.5V, 5.0V
Verslons(8)
±
0.25V, T A
±
28F016SV-120
Max
Min
Typ
=
OOG to
0
ns
+ 700G
28F016SV-065(9)
28F016SV-070(9)
28F016SV-070(10)
10%
Sym
Parameter
Notes
Min
tAVEL
Address Setup
toGE# Going
Low
2,3
0
Typ
Max
Min
0
Typ
Max
28F016SV-080(10)
Min
Typ
0
NOTES:
1.
2.
3.
4.
Ali other specifications for CE#-Controlied Write Operations can be found in Section 5.9.
Address must be valid during the entire CE# low pulse.
CEx# is defined as the laller of CEo# or CE1 # going low, or the first of CEo# or CE1 # going high.
Device speeds are defined as:
65/70 ns at Vee = 5.0V equivalent to
75 ns at Vee = 3.3V
70/80 ns al Vee = 5.0V equivalent to
120 ns at Vee = 3.3V
5. See the high speed AC Input/Output Reference Waveforms and ACTesting Load Circuit.
6. See the standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
3-350
Units
Max
,
Vee ± 5%
Vee
Typ
Units
Max
ns
intel®
28F016SV FlashFile™ Memory
'-"H
WEiI(W)
V 1L
t EHWH
tWLEL
'-"H
CEldI (E)
NOTE 1
t EHEL
V 1L
tELEH
t EHAX
V 1H
ADDRESSES (A)
VAUD
V 1L
tDVEH
'-"H
DATA (D/Q)
V 1L
HIGHZ
{
qN
J,
C
290528-18
NOTE:
1. CEx# is defined as the latter of CEo# or CE1 # going low. or the first of CEo# or CE1 # gOing high.
Figure 18. CE#-Controlled Page Buffer Write Timing Waveforms
(Loading Data to the Page Buffer)
3-351
28F016SV FlashFile™ Memory
5.12 Erase and Word/Byte Write Performance(3,5)
vee = 3.3V
Sym
± 0.3V,
vpp = 5.0V
±
Parameter
0.5V, TA = O·C to + 70·C
Typ(1) .
Notes
Min
Max
Units
Page Buffer Byte
Write Time
2
TBD
6.0
TBD
/Ls
Page Buffer Word
Write Time
2
TBD
12.1
TBD
/Ls
tWHRH1A
Byte Write Time
2
TBD
16.5
TBD
/Ls
tWHRH1B
Word Write Time
2
TBD
24.0
TBD
/Ls
tWHRH2
Block Write Time
2
TBD
1.1
TBD
sec
Byte Write Mode
tWHRH 3
Block Write Time
2
TBD
0.8
TBD
sec
Word Write Mode
Block Erase Time
2
TBD
1.4
TBD
sec
Full Chip Erase Time
2
TBD
44.8
TBD
sec
Time from Erase
Suspend Command to
WSM Ready
4 .
TBD
10
TBD
/Ls
Test Conditions
.-
Vee = 3.3V ± 0.3V, Vpp = 12.0V ± 0.6V, TA = O·C to +70·C
Notes
Min
Typ(1)
Max
Units
Page Buffer Byte
Write Time
2
TBD
2.2
TBD
/LS
Page Buffer Word
Write Time
2
TBD
4.4
TBD
/Ls
tWHRH1
Word/Byte Write Time
2
5
9
TBD
/Ls
tWHRH2
Block Write Time
2
TBD
0.6
2.1
sec
Byte Write Mode
tWHRH 3
Block Write Time
2
TBD
0.3
1.0
sec
Word Write Mode
Block Erase Time
2
0.3
0.8
10
sec
Full Chip Erase Time
2
TBD
25.6
TBD
sec
Time from Erase
Suspend Command to
WSM Ready
4
TBD
10
TBD
/Ls
Sym
3-352
Parameter
Test Conditions
28F016SV FlashFile™·Memory
5.12 Erase and Word/Byte Write Performance(3,5) (Continued)
Vee
=
5.0V ± 0.5V, 5.0V ± 0.25V, Vpp
=
5.0V ± 0.5V, T A
=
O·C to + 70·C
Notes
Min
Typ(1)
Max
Units
Page Buffer Byte
Write Time
2
TBD
6.0
TBD
)J-s
Page Buffer Word
Write Time
2
TBD
12.1
TBD
)J-s
tWHRH1A
Byte Write Time
2
TBD
11
TBD
)J-s
tWHRH1B
Word Write Time
2
TBD
16
TBD
)J-s
tWHRH2
Block Write Time
2
TBD
0.8
TBD
sec
Byte Write Mode
tWHRH3
Block Write Time
2
TBD
0.6
TBD
sec
Word Write Mode
Block Erase Time
2
TBD
1.0
TBD
sec
Sym
Vee
=
Parameter
Full Chip Erase Time
2
TBD
32.0
TBD
sec
Time from Erase
Suspend Command to
WSM Ready
4
TBD
10
TBD
)J-s
5.0V ± 0.5V, 5.0V ± 0.25V, Vpp
Sym
=
12.0V ± 0.6V, TA
=
O·C to +70·C
Notes
Min
Typ(1)
Max
Units
Page Buffer Byte
Write Time
2
TBD
2.1
TBD
)J-s
Page Buffer Word
Write Time
2
TBD
4.1
TBD
)J-s
Parameter
Test Conditions
Test Conditions
tWHRH1
Word/Byte Write Time
2
4.5
6
TBD
)J-s
tWHRH2
Block Write Time
2
TBD
0.4
2.1
sec
Byte Write Mode
tWHRH 3
Block Write Time
2
TBD
0.2
1.0
sec
Word Write Mode
Block Erase Time
2
0.3
0.6
10
sec
Full Chip Erase Time
2
TBD
19.2
TBD
sec
. Time from Erase
Suspend Command to
WSM Ready
4
TBD
10
TBD
)J-s
NOTES;
1. 25·e, and nominal voltages.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Specification applies to interrupt latency for Single Block Erase. Suspend latency for Erase All Unlocked Block operation
extends the latency time to 140 ""s (typical).
5. Sampled, but not 100% tested. Guaranteed by design.
3-353
28F016SV FlashFlle™ Memory
6.0 MECHANICAL SPECIFICATIONS
z
~ -o--------------------~0.__T
o
oU
;:::::::::::::-Dl=:::::::::::~1 I
••• ~ SEE DETAIL A
r
r
r
r
iJ~I:============~liJ
DETAIL B
290528-19
Figure 19. Mechanical Specifications of the 28F016SV 56-Lead TSOP Type I Package
Symbol
A
A1
A2
b
c
D1
E
e
D
L
N
0
Y
Z
3-354
Family: Thin Small Out-Line Package
Millimeters
Minimum
Nominal
Maximum
1.20
0.50
0.965
0.995
1.025
0.100
0.150
0.200
0.115
0.125
0.135
18.20
18.40
18.60
13.80
14.00
14.20
0.50
19.80
20.00
20.20
0.500
0.600
0.700
56
0°
3°
5°
0.100
0.150
0.250
0.350
Notes
28F016SV FlashFile™ Memory
DETAIL A
~
hn nnnnnnnnnnnn nn e : nnnnJ$:+
1:1 IHH:I 1:1 1:1 EI IHH:I 1:1 1:11:1 1:11:11:1
-II-a
1:1 1:11:11:1
-11-.,
c::J
y
'"'nC
AI
rr=4'-_ _ _ _--7(-+'rk --\:
, t-~,
SEE DETAIL A---->~--/
dJ'
290528-20
Figure 20. Mechanical Specifications of the 28F016SV 56-Lead SSOP Type I Package
Family: Shrink Small Out-Line Package
MIllimeters
Symbol
Notes
Minimum
Nominal
1.80
1.90
A1
A2
0.47
0.52
0.57
1.18
1.28
1.38
B
0.25
0.30
0.20
A
MaXimum
C
0.13
0.15
0.20
0
23.40
23.70
24.00
E
13.10
13.30
13.50
e1
He
0.80
15.70
N
16.00
16.30
56
0.45
0.50
0.55
a
2·
3·
0.10
4·
b
3·
4·
5·
R1
R2
0.15
0.20
0.25
0.15
0.20
0.25
L1
Y
3-355
28F016SV FlashFlle™ Memory
DEVICE NOMENCLATURE AND ORDERING INFORMATION
IEl2lalFlol1lalslvl-lolal51
I
=
=
DA COMMERCIAL TEMPERATURE
56-LEAD SSOP
E COMMERCIAL TEMPERATURE
56-LEAD TSOP
I
ACCESS SPEED (ns)
65 ns (SV, 30 pF), 70 ns (5V), 75 ns (3.3V)
70 ns (SV, 30 pF), 80 ns (5V), 120 ns (3.3V)
290528-21
Valid Combinations
Option
Order Code
Vee
= 3.3V ± 0.3V,
SO pF load,
1.SV I/O Levels(1)
= S.OV ± 10%,
100 pF load
TTL I/O Levels(1)
= S.OV ± S%,
30 pF load
1.SV I/O Levels(1)
Vee
Vee
1
E28F016SV 070
E28F016SV-120
E28F016SV-080
E28F016SV-070
2
E28F016SV 065
E28F016SV-075
E28F016SV-070
E28F016SV-065
3
DA28F016SV 070
DA28F016SV-120
DA28F016SV-080
DA28F016SV-070
4
DA28F016SV 065
DA28F016SV-075
DA28F016SV-070
DA28F016SV-065
NOTE:
1. See Section 5.2 for Transient Input/Output Reference Waveforms and Testing Load Circuits.
3-356
28F016SV FlashFile™ Memory
ADDITIONAL INFORMATION
Order Number
Document/Tool
297372
16-Mbit Flash Product Family User's Manual,
28F016SA/28F016SV/28F016SXS/28F016XD
292092
AP-357 "Power Supply Solutions for Flash Memory"
292123
AP-374 "Flash Memory Write Protection Techniques"
292124
AP-375 "Upgrade Considerations from the 28F008SA to the 28F016SA"
292126
AP-377 "16-Mbit Flash Product Family Software Drivers,
28F016SAl28F016SV /28F016SXS/28F016XD"
292127
AP-378 "System Optimization Using the Enhanced Features of the 28F016SA"
292144
AP-393 "28F016SV Compatibility with 28F016SA"
294016
ER-33 "ETOXTM Flash Memory Technology-Insight to Intel's Fourth
Generation Process Innovation"
290490
DD28F032SA Datasheet
290435
28F008SA Datasheet
297508
FlashBuilder Utility
Contact Intel/Distribution
Sales Offices
28F016SV iBIS Models
Contact Intel/Distribution
Sales Offices
28F016SV VHDLlVeriiog Models
Contact Intel/Distribution
Sales Offices
28F016SV Timing Designer Library Files
Contact Intel/Distribution
Sales Offices
28F016SV Orcad and ViewLogic Schematic Symbol
3-357
28F016SV FlashFile™ Memory
DATASHEET REVISION HISTORY
Number
Description
001
Original Version
002
Added 28F016SV-065/-070 at 5.0V Vee and 28F016SV-075 at 3.3V Vee.
Improved burst write transfer rate to 30.8 MB/sec.
Added 56-Lead SSOP Type 1 packaging information.
Changed VPPLK from 2.0V to 1.5V.
Increased leeR at 5.0V Vee and 3.3V Vee:
leeRlfrom 30 mA (typ)/35 mA (max) to 40 mA (typ)/50 mA (max) - Vee
leeR2 from 15 mA (typ)/20 mA (max) to 20 mA (typ)/30 mA (max) - Vee
leeR1 from 50 mA (typ)/60 mA (max) to 75 mA (typ)/95 mA (max) - Vee
leeR2 from 30 mA (typ)/35 mA (max) to 45 mA (typ)/55 mA (max) - Vee
=
=
=
=
3.3V
3.3V
5.0V
5.0V
Moved AC Characteristics for Extended Register Reads into separate table.
Increased Vpp MAX from 13V to 14V.
Added Erase Suspend Command Latency times to Section 5.12
Modified Device Nomenclature Section to include SSOP package option and Ordering
Information
3-358
28F016SA
16 MBIT (1 MBIT x 16, 2 MBIT x 8)
FlashFile 1M MEMORY
3.3V or 5V Vee
• User-Selectable
User-Configurable x8 or x16 Operation
• 70 ns Maximum Access Time
• MB/sec Burst Write Transfer Rate
• 28.6
1 Million Typical Erase Cycles per
• Block
1.2mm x 14mm x 20mm TSOP
• 56-Lead,
Package
56-Lead, 1.8mm x 16mm x 23.7mm
• SSOP
Package
Architecture
• -Revolutionary
Pipelined Command Execution
- Write During Erase
- Command Superset of Intel
28FOO8SA
rnA Typical lee in Static Mode
• 11 ,."A
Typical Deep Power-Down
• 32 Independently
Blocks
• State-of-the-Art 0.6Lockable
• Flash Technology ,."m ETOXTM IV
Intel's 2SF016SA 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for
designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative
capabilities, low-power, extended temperature operation and high read/write performance, the 2SF016SA
enables the design of truly mobile, high-performance communications and computing products.
The 2SF016SA is the highest density, highest performance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked architecture (100% compatible with the 2SFOOSSA S-Mbit
FlashFile memory), extended cycling, extended temperature operation, flexible Vcc, fast write and read performance and selective block locking provide highly flexible memory components suitable for resident flash
arrays, high-density memory cards and PCMCIA-ATA flash drives. The 2SF016SA dual read voltage enables
the design of memory cards which can interchangeably be read/written in 3.3V and 5.0V systems. Its xS/x16
architecture allows optimization of the memory-to-processor interface. Its high read performance and flexible
block locking enable both storage and execution of operating systems and application software. Manufactured
on Intel's 0.6 /Lm ETOXTM IV process technology, the 2SF016SA is the most cost effective, highest density
monolithic 3.3V FlashFile memory.
ETOXTM and FlashFile™ are trademarks of Intel Corporation.
November 1994
Order Number: 290489-002
3-359
28F016SA
16 Mbit (1 Mbit x 16, 2 Mbit
Flashfile ™ Memory
CONTENTS
PAGE
1.0 INTRODUCTION ................... 3-361
1.1 Product Overview ................ 3-361
2.0 DEVICE PINOUTIPACKAGES ..... 3-362
2.1 Lead Descriptions ............... 3-364
CONTENTS
x 8)
PAGE
5.4 DC Characteristics for
Vee = 3.3V ± O.3V .............. 3-379
5.5 DC Characteristics for
Vee = 5.0V ± O.5V .............. 3-381
5.6 AC Characteristics-'-Read Only
Operations ........................ 3-383
3.0 MEMORY MAPS ................... 3-366
5.7 Power-Up and Reset Timings .... 3-387
3.1 Extended Status Registers Memory
Map .............................. 3-367
5.B AC Characteristics for WE #Controlled Command Write
Operations ........................ 3-388
4.0 BUS OPERATIONS, COMMANDS
AND STATUS REGISTER
DEFINITIONS ....................... 3-368
4.1 Bus Operations for Word-Wide
Mode (Byte # = VIH) .............. 3-368
5.9 AC Characteristics for CE#Controlled Command Write
Operations ........................ 3-391
5.1 0 AC Characteristics for Page
Buffer Write Operations ........... 3-394
4.2 Bus Operations for Byte-Wide
Mode (Byte# = VIU .............. 3-368
5.11 Erase and Word/Byte Write
Performance ...................... 3-396
4.3 2BFOOBSA-Compatible Mode
Command Bus Definitions ......... 3-369
6.0 DERATING CURVES .............. 3-397
4.4 2BF016SA-Performance
Enhancement Command Bus
Definitions ........................ 3-370
7.0 MECHANICAL SPECIFICATIONS
FOR TSOP .......................... 3-400
4.5 Compatible Status Register ...... 3-371
8.0 MECHANICAL SPECIFICATIONS
FOR SSOP .......................... 3-401
4.6 Global Status Register ........... 3-372
4.7 Block Status Register ............ 3-373
5.0 COMMERCIAL TEMPERATURE
ELECTRICAL SPECiFiCATIONS .... 3-374
5.1 Absolute Maximum Ratings ...... 3-374
5.2 Capacitance ..................... 3-375
DEVICE NOMENCLATURE AND
ORDERING INFORMATION ......... 3-402
ADDITIONAL INFORMATION ......... 3-402
DATASHEET REVISION HiSTORy .... 3-402
5.3 Timing Nomenclature ............ 3-376
3-360
I
28F016SA
1.0
INTRODUCTION
The documentation of the Intel 28F016SA memory
device includes this data sheet, a detailed user's
manual, and a number of application notes, all of
which are referenced at the end of this data sheet.
The data sheet is intended to give an overview of
the chip feature-set and of the operating AC/DC
specifications. The 28F016SA User's Manual provides complete descriptions of the user modes, system interface examples and detailed descriptions of
all principles of operation. It also contains the full list
of software algorithm flowcharts, and a brief section
on compatibility with Intel 28F008SA.
1.1 Product Overview
The 28F016SA is a high performance 16 Mbit
(16,777,216 bit) block erasable non-volatile random
access memory organized as either 1 Mword x 16 or
2 Mbyte x 8. The 28F016SA includes thirty-two 64
KB (65,536) blocks or thirty-two 32-KW (32,768)
blocks. A chip memory map is shown in Figure 3.
The implementation of a new architecture, with
many enhanced features, will improve the device operating characteristics and results in greater product
reliability and ease of use.
Among the
28F016SA:
significant enhancements
on
the
e 3.3V Low Power Capability
• Improved Write Performance
• Dedicated Block Write/Erase Protection
A 3/5# input pin reconfigures the device internally
for optimized 3.3V or 5.0V read/write operation.
The 28F016SA is available in both a 56-lead, 1.2mm
thick, 14mm x 20mm TSOP type 1 package or a
56-lead, 1.8mm thick, 16mm x 23.7mm SSOP package. The TSOP form factor and pinout allow for very
high board layout densities.
A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation.
Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the 28F008SA 8-Mbit FlashFile™
memory.
A Superset of commands have
basic 28F008SA command-set
write performance and provide
ties. These new commands and
•
..
..
..
been added to the
to achieve higher
additional capabilifeatures include:
Page Buffer Writes to Flash
Command Queuing Capability
Automatic Data Writes During Erase
Software Locking of Memory Blocks
• Two-Byte Successive Writes in a-bit Systems
• Erase All Unlocked Blocks
Writing of memory data is performed in either byte or
word increments typically within 6 /Lsec, a 33% improvement over the 28F008SA. A Block Erase operation erases one of the 32 blocks in typically 0.6 sec,
independent of the other blocks, which is about 65%
improvement over the 28F008SA.
Each block can be written and erased a minimum of
100,000 cycles. Systems can achieve typically 1 million Block Erase Cycles by providing graceful block
retirement. This technique has already been employed in Hard Disk Drive designs. Additionally, wear
leveling of block erase cycles can be used to minimize the write/erase performance differences
across blocks.
The 28F016SA incorporates two Page Buffers of
256 Bytes (128 Words) each to allow page data
writes. This feature can improve a system write performance by up to 4.8 times over previous flash
memory devices.
.
All operations are started by a sequence of Write
commands to the device. Three Status Registers
(described in detail later) and a RY /BY # output pin
provide information on the progress of the requested
operation.
While the 28F008SA requires an operation to complete before the next operation can be requested,
the 28F016SA allows queuing of the next operation
while the memory executes the current operation.
This eliminates system overhead when writing several bytes in a row to the array or erasing several
blocks at the same time. The 28F016SA can also
perform write operations to one block of memory
while performing erase of another block.
The 28F016SA provides user-selectable block locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S or
Application Code. Each block has an associated
non-volatile lock-bit which determines the lock
status of the block. In addition, the 28F016SA has a
master Write Protect pin (WP#) which prevents any
modifications to memory blocks whose lock-bits are
set.
3-361
28F016SA
The 28F016SA contains three types of Status Registers to accomplish various functions:
• A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory's Status Register. This register, when
used alone, provides a straightforward upgrade
capability to the 28F016SA from a 28F008SAbased design.
• A Global Status Register (GSR) which informs
the system of command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
• 32 Block Status Registers (BSRs) which provide
block-specific status information such as the
block lock-bit status.
The GSR and BSR memory maps for Byte-Wide and
Word-Wide modes are shown in Figures 4.1 and 4.2.
The 28F016SA incorporates an open drain RYIBY #
output pin. This feature allows the user to OR-tie
many RYIBY # pins together in a multiple memory
configuration such as a Resident Flash Array.
Other configurations of the RY IBY # pin are enabled via special CUI commands and are described
in detail in the 28F016SA User's Manual.
The 28F016SA also incorporates a dual chip-enable
function with two input pins, CEo# and CE1 #.
These pins have exactly the same functionality as
the regular chip-enable pin CE # on the 28F008SA.
For minimum chip designs, CE1 # may be tied to
ground and use CEo# as the chip enable input. The
2BF016SA uses the logical combination of these two
signals to enable. or disable the entire chip. Both
CEo# and CE1 # must be active low to enable the
device and if either one becomes inactive, the chip
will be disabled. This feature, along with the open
drain RYIBY # pin, allows the system designer to
reduce the number of control pins used in a large
array of 16-Mbit devices.
.
The BYTE # pin allows either xB or x16 readlwrites
to the 28F016SA. BYTE# at logic low selects 8-bit
mode with address Ao selecting between low byte
3-362
and high byte. On the other hand, BYTE # at logiC
high enables 16-bit operation with address A1 becoming the lowest order address and address Ao is
not used (don't care). A device block diagram is
shown in Figure 1.
The 28F016SA is specified for a maximum access
time of 70 ns (tACC> at 5.0V operation (4.75V to
5.25V) over the commercial temperature range (O·C
to + 70·C). A corresponding maximum access time
of 120 ns at 3.3V (3.0V to 3.6V and O·C to + 70·C) is
achieved for reduced power consumption applications.
The 28F016SA incorporates an Automatic Power
Saving (APS) feature which substantially reduces
the active current when the device is in static mode
of operation (addresses not switching).
In APS mode, the typical Icc current is 1 mA at 5.0V
(0.8 mA at 3.3V).
A Deep Power-Down mode of operation is invoked
when the RP# (called PWD on the 2BF008SA) pin
transitions low. This mode brings the device power
consumption to less than 1.0 /LA, typically, and provides additional write protection by acting as a device reset pin during power transitions. A reset time
of 400 ns is required from RP# switching high until
outputs are again valid. In the Deep Power-Down
state, the WSM is reset (any current operation will
abort) and the CSR, GSR and BSR registers are
cleared.
A CMOS Standby mode of operation is enabled
when either CEo# or CE1 # transitions high and
RP# stays high with all input control pins at CMOS
levels. In this mode, the device typically draws an
Icc standby current of 50 /LA.
2.0
DEVICE PINOUTIPACKAGES
The 2BF016SA 56L-TSOP Type I pinout configuration is shown in Figure 2. The 56L-SSOP pinout configuration is shown in Figure 3.
28F016SA
00a_15
0°0_7
o
N
I
...o
_---wP#
_---RP#
Y GATING/SENSING
:t-----. RY /SY#
•••••••••
Vpp
3/5#
+--Vcc
_GNO
••••••••••••
290489-2
Figure 1. 28F016SA Block Diagram
Architectural Evolution Includes Page Buffers, Queue Registers and Extended Status Registers.
3·363
intel~
28F016SA
2.1 Lead Descriptions
Symbol
Type
Name and Function
Ao
INPUT
BYTE-SELECT ADDRESS: Selects betWeen high and low byte when
device is in x8 mode. This address is latched in x8 Data Writes. Not used
in x16 mode (i.e., the Ao input buffer is turned off when BYTE # is high).
Al-A15
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64-Kbyte
block. AS-15 selects 1 of 1024 rows, and Al_5selects 16 of 512
columns. These addresses are latched during Data Writes.
A1S-A20
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase blocks. These
addresses are latched during Data Writes, Erase and Lock-Block
operations.
DQo-DQ7
INPUTIOUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the appropriate
Read mode. Floated when the chip is de-selected or the outputs are
disabled.
DQ8-DQ15
INPUTIOUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations.
Outputs array, buffer or identifier data in the appropriate Read mode; not
used for Status register reads. Floated when the chip is de-selected or
the outputs are disabled.
CEo#, CEl #
INPUT
CHIP ENABLE INPUTS: Activate the device's control logic, input
buffers, decoders and sense amplifiers. With either CEo# or CEl # high,
the device is de-selected and power consumption reduces to Standby
levels upon completion of any current Data-Write or Erase operations.
Both CEo #, CEl # must be low to select the device.
All timing specifications are the same for both signals. Device Selection
occurs with the latter falling edge of CEo# or CEl #. The first rising edge
of CEo# or CE1 # disables the device.
,
RP#
INPUT
RESET/POWER-DOWN: RP# low places the device in a Deep PowerDown state. All circuits that burn static power, even those circuits
enabled in standby mode, are turned off. When returning from Deep
Power-Down, a recovery time of 400 ns is required to allow these circuits
to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status registers return to ready
(with all status flags cleared).
OE#
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when
low. The outputs float to tri-state off when OE # is high.
NOTE:
CEx# overridesOE#, and OE# overrides WE#.
WE#
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE # is active low, and latches
both address and data (command or array) on its rising edge.
RV/BV#
OPEN DRAIN
OUTPUT
READY/BUSY: Indicates status of the internal WSM. When low, it
indicates that the WSM is busy performing an operation. RVIBV # high
indicates that the WSM is ready for new operations (or WSM has
completed ali pending operations), or Erase is Suspended,or the device
is in deep power-down mode. This output is always active (i.e., not
floated to tri-state off when OE # or CEo#, CE1 # are high), except if a
RVIBV# Pin Disable command is issued.
3-364
28F016SA
2.1
Lead Descriptions (Continued)
Symbol
Type
Name and Function
WP#
INPUT
WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for
each block. When WP# is low, those locked blocks as reflected by the Block-Lock
Status bits (BSR.6), are protected from inadvertent Data Writes or Erases. When
WP# is high, all blocks can be Written or Erased regardless of the state of the lockbits. The WP# input buffer is disabled when RP# transitions low (deep power-down
mode).
BYTE #
INPUT
BYTE ENABLE: BYTE# low places device in x8 mode. All data is then input or output
on 000-7, and 008.15 float. Address AO selects between the high and low byte.
BYTE # high places the device in x16 mode, and turns off the Ao input buffer. Address
A1, then becomes the lowest order address.
3/5#
INPUT
3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3V operation.
3/5# low configures internal circuits for 5.0V operation.
NOTES:
Reading the array with 3/5# high in a 5.0V system could damage the device.
There is a significant delay from 3/5# switching to valid data.
Vpp
SUPPLY
ERASE/WRITE POWER SUPPLY: For erasing memory array blocks or writing words/
bytes/pages into the flash array.
Vee
SUPPLY
DEVICE POWER SUPPLY (3.3V ± 0.3V,5.0V ± 0.5V):
Do not leave any power pins floating.
GNO
SUPPLY
GROUND FOR ALL INTERNAL CIRCUITRY:
Do not leave any ground pins floating.
NC
NO CONNECT:
No internal connection to die, lead may be driven or left floating.
o
56
55
54
53
52
51
E28F016SA
56-LEAD TSOP PINOUT
1.2mm X 14mm X 20mm
TOP VIEW
50
49
46
47
46
45
290489-3
NOTE:
56-LEAD TSOP Mechanical Diagrams and Dimensions are shown at the end of this speciiication
Figure 2. TSOP Pinout Configuration
3-365
intel®
28F016SA
2SF016SV
2sr016SV
o
CEO"
A12
A13
AU
'"
RIp"
All
AIO
A'
@
Al
A2
A3
CEI"
Ne
A<
A5
A6
A19
A18
A17
DT28F016SA
56-LEAD SSOP
STANDARD PINOUT
1.8mm x 16mm,x 23. 7mm
TOP VIEW
A16
'"
eND
Das
DQ1'"
007
DO 15
.,.
.'"
Ry/BY"
0"
OND
A8
Vee
DO'
DOl
D08
DOD
AD
BYTE_
"'"'
0013
DOS
D02
0010
D03
0012
004
DOli
eND
V"
290489-31
Figure 3. SSOP Pinout Configuration
3.0
MEMORY MAPS
IFFrFF
11'0000
!EHI'F
lEOOOO
IOFFI'!'
100000
lerr!'r
ICOOOO
!8rrrr
180000
tArrrr
IADOOD
19FfTF
190000
ISFrrr
180000
171'FfF
170000
ISHl'f
160000
Isrl'!'F
150000
!4rl'rr
140000
131'rFr
130000
12rfFr
120000
IlfFrr
110000
IOFrl'r
100000
OFFFFF
01'0000
OEFF!'F
0[0000
DOHFI'
000000
ocrFrr
oeoooo
OBHrF
080000
OAFnF
DADooa
09Frrr
090000
oaFrrr
DeOOOD
07FrFr
070000
oarrrF
060000
OSHFF
050000
04FFFF
040000
03fFFF
030000
02FFFF
020000
Olrrl'r
010000
DOrFFI'
000000
64 KByte Block
31
64 KByte Block
30
64 KByte Block
29
64 KByte Block
28
64 KByte Block
27
64 KByte Block
26
64 KByte Block
25
64 KByte Block
24
64 KByte Block
23
64 KByte Block
22
64 KByte Block
21
64 KByte Block
20
64 KByte Block
19
64 KByte Block
18
,64 KByte Block
17
64 KByte Block
16
64 KByte Block
15
64 KByte Block
14
64 KByte Block
13
64 KByte Block
12
64 KByte Block
11
64 KByte Block
10
64 KByte Block
9
64 KByte Block
8
64 KByte Block
7
64 KByte Block
6
64 KByte Block
5
64 KByte Block
4
64 KByte Block
3
64 KByte Block
2
64 KByte Block
1
64 KByte Block
0
290489-30
Figure 4_ 28F016SA Memory Map (Byte-wide mode)
3-366
28F016SA
3.1
Extended Status Registers Memory Map
X8MODE
A[20:0]
RESERVED
GSR
RESERVED
BSR31
RESERVED
RESERVED
•
•
•
•
•
•
1 F0006H
1 F0005H
1 F0004H
1 F0003H
1 F0002H
1 F0001 H
1 FOOOOH
010002H
RESERVED
RESERVED
GSR
RESERVED
BSRO
RESERVED
RESERVED
,------------------------------,
A[20:1]
X16MODE
RESERVED
GSR
RESERVED
BSR31
RESERVED
RESERVED
•
•
•
•
•
•
FB003H
FB002H
FB001H
FBOOOH
OB001H
RESERVED
000006H
000005H
000004H
000003H
000002H
000001H
OOOOOOH
Figure 5.1 Extended Status Register
Memory Map (Byte-wide mode)
RESERVED
GSR
RESERVED
BSRO
RESERVED
RESERVED
00003H
00002H
00001H
OOOOOH
Figure 5.2 Extended Status Register
Memory Map (Word-wide mode)
3-367
28F016SA
4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
4.1 Bus Operations for Word-Wide Mode (BYTE # = VIH)
Mode
Read
Notes
RP#
CE1#
CEo#
OE#
WE#
A1
DQO-15
RY/BY#
1,2,7
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
HighZ
X
Output Disable
1,6,7
VIH
VIL
VIL
VIH
VIH
X
Standby
1,6,7
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
HighZ
X
1,3
VIL
X
X
X
X
X
HighZ
VOH
4
VIH
VIL
VIL
VIL
VIH
VIL
0089H
VOH
Deep Power-Down
Manufacturer ID
Device ID
Write
4
VIH
VIL
VIL
VIL
VIH
VIH
66AOH
VOH
1,5,6
VIH
VIL
VIL
VIH
VIL
X
DIN
X
4.2 Bus Operations For Byte-Wide Mode (BYTE #
= Vld
Notes
RP#
CE1#
CEo#
OE#
WE#
Ao
DQO-7
RY/BY#
Read
1,2,7
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
Output Disable
1,6,7
VIH
VIL
VIL
VIH
VIH
X
HighZ
X
Standby
1,6,7 ..
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
HighZ
X
1,3
VIL
X
X
X
X
X
HighZ
VOH
Manufacturer ID
4
VIH
VIL
VIL
VIL
VIH
VIL
89H
VOH
Device ID
4
VIH
VIL
VIL
VIL
VIH
VIH
AOH
VOH
1,5,6
VIH
VIL
VIL
VIH
VIL
X
DIN
X
Mode
Deep Power-Down
Write
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH.
2. RY IBY # output is open drain. When the WSM is ready. Erase is suspended or the device is in deep power-down mode,
RY/BY# will be at VOH if it is tied to Vee through a resistor. RY/BY# at VOH is independent of OE# while a WSM
operation is in progress.
3. RP# at GND ± O.2V ensures the lowest deep power-down current.
4. Ao andA1 at VIL provide manufacturer ID codes in xB and x16 modes repectively.
Ao and A1 at VIH provide device ID codes in xB and x16 modes repectively. All other addresses are set to zero.
5. Commands for different Erase operations. Data Write operations or Lock-Block operations can only be successfully completed when Vpp = VpPH.
.
6. While the WSM is running, RY IBY # in Level-Mode (default) stays at VOL until all operations are complete. RY IBY # goes
to VOH when the WSM is not busy or in erase suspend mode.
7. RY IBY # may be at VOL while the WSM is busy performing various operations. For example. a status register read during
a write operation.
3-368
28F016SA
4.3 28F008SA-Compatible Mode Command Bus Definitions
Command
Read Array
intelligent identifier
First Bus Cycle
Notes
1
Second Bus Cycle
Oper
Addr
Data
Oper
Addr
Data
Write
X
FFH
Read
AA
AD
Write
X
90H
Read
IA
ID
Read
X
CSRD
WD
Read Compatible Status Register
2
Write
X
70H
Clear Status Register
3
Write
X
SOH
Word/Byte Write
Write
X
40H
Write
WA
Alternate Word/Byte Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
SA
DOH
Erase Suspend/Resume
Write
X
BOH
Write
X
DOH
ADDRESS
DATA
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don't Care
AD = Array Data
eSRD = eSR Data
10 = Identifier Data
WD = Write Data
NOTES:
1. Following the intelligent identifier command, two Read operations access the manufacturer and device signature codes.
2. The eSR is automatically available after device enters Data Write, Erase, or Suspend operations.
3. Clears eSR.3, eSR.4 and eSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits.
See Status register definitions.
3-369
28F016SA
4.4 28F016SA-Performance Enhancement Command Bus Definitions
Command
Mode
Notes
First Bus Cycle
Second Bus Cycle
Oper Addr Data Oper Addr
Read Extended
Status Register
1
Write
X
71H
Page Buffer Swap
7
Write
X
72H
Read Page Buffer
Write
X
Single Load to
Page Buffer
Write
X
Write
X
x16
4,5,6,10 Write
xa
3,4,9,10 Write
Sequential Load to
Page Buffer
xa
4,6,10
Data
GSRD
BSRD
75H
Read
PA
PD
74H
Write
PA
PD
EOH
Write
X
BCL
X
EOH
Write
X
WCL. Write
X
WCH
X
OCH
Write
Ao
BC(L,H) Write
WA
BC(H,L)
Write
X
x16
4,5,10
Write
X
OCH
xa
3
Write
X
FBH Write
Ao
Write
X
77H
Write
BA
DOH
Write
X
97H
Write
X
DOH
Upload Device
Information
Write
X
99H
Write
X
DOH
Erase All Unlocked
Blocks/Confirm
Write
X
A7H
Write
X
DOH
2
WCL
WCH
WA
WD(H,L)
X
96H
Write
X
01H
RY /BY # Pulse-OnWrite
a
Write
X
96H
Write
X
02H
RY /BY # Pulse-OnErase
a
Write-
X
96H
Write
X
03H
RY /BY # Disable
a
Write
X
96H
Write
X
04H
Sleep
Write
X
FOH
Abort
Write
X
aOH
DATA
AD = Array Data
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
BCH
WA
Write
BA. = Block Address
PA = Page Buffer Address
RA = Extended Register Address'
WA = Write Address
X = Don't Care
X
Write
a
ADDRESS
Write
WD(L,H) Write
RY /BY # Enable to
Level-Mode
3-370
Data
RA
Two-Byte Write
Upload Status
Bits/Confirm
Oper Addr
Read
Page Buffer Write
to Flash
Lock Block/Confirm
Third Bus Cycle
WC (L,H) .= Word Count (Low, High)
BC (L,H) = Byte Count (Low, High)
WD (L,H) = Write Data (Low, High)
28F016SA
NOTES:
1. RA can be the GSR address or any BSR address. See Figures 4.1 and 4.2 for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3. Ao is automatically complemented to load second byte of data. BYTE# must be at VIL.
Ao value determines which WD/BC is supplied first: Ao = 0 looks at the WDLlBCl, Ao = 1 looks at the WDH/BCH.
4. BCH/WCH must be at OOH for this product because of the 256-Byte (128 Word) Page Buffer size and to avoid writing the
Page Buffer contents into more than one 256-Byte segment within an array block. They are simply shown for future Page
Buffer expandability.
5. In x16 mode, only the lower byte DOO_7 is used for WCl and WCH. The upper byte DQ8-15 is a don't care.
6. PA and PD (whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
8. These commands reconfigure RY IBY # output to one of two pulse-modes or enable and disable the RY IBY # function.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer.
Refer to the 28F016SA User's Manual.
10. BCl = OOH corresponds to a Byte count of 1. Similarly, WCl = OOH corresponds to a Word count of 1.
4.5 Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
7
6
5
4
3
2
R
R
o
NOTES:
CSR.7 =
WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
CSR.6 =
ERASE-SUSPEND STATUS
1 = Erase Suspended
=;' Erase in Progress/Completed
RY /BY # output or WSMS bit must be checked to
determine completion of an operation (Erase Suspend,
Erase or Data Write) before the appropriate Status bit
(ESS, ES or DWS) is checked for success.
o
CSR.5 =
ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Erase
CSR.4 =
DATA-WRITE STATUS
1 = Error in Data Write
o = Data Write Successful
CSR.3 =
Vpp STATUS
1 = Vpp Low Detect, Operation
Abort
0= VppOK
If DWS and ES are set to "1" during an erase attempt, an
improper command sequence was entered. Clear the
CSR and attempt the operation again.
The VPPS bit, unlike an AID converter, does not provide
continuous indication of Vpp level. The WSM interrogates
Vpp's level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
Vpp has not been switched on. VPPS is not guaranteed to
report accurate feedback between VpPl and VPPH.
CSR.2-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSR.
3-371
28F016SA
4.6 Global Status Register
WSMS
OSS
DOS
DSS
QS
PBAS
7
6
5
4
3
2
GSR.7 = WRITE STATE MACHINE STATUS
1 = Ready'
0= Busy,
PBS
PBSS
o
NOTES:
'[11 RY/BY # output or WSMS bit r:nust be'
checked to determine completion of an
operation (Block Lock, Suspend, any RY /BY #
reconfiguration, Upload Status Bits,Erase or
Data Write) before the appropriate Status bit
(OSS or DOS) is checked for success.
GSR.6 = OPERATION SUSPEND STATUS
1 = Operation Suspended
o = Operation in Progress/Completed
GSR'.5 = DEVICE OPERATION STATUS
1 = Operation Unsuccessful
o = Operation Successful or Currently
Running
GSR.4 = DEVICE SLEEP STATUS
1 = Device in Sleep
o = Device Not in Sleep
MATRIX 5/4
o 0 = Operation Successful or Currently
Running
o 1 = Device in Sleep Mode or Pending Sleep
1 0 = Operation Unsuccessful
1 1 = Operation Unsuccessful or Aborted
If operation currently tu~ning, then GSR.7 = O.
If device pending sleep; then GSR. 7 = o.
Operation aborted: Unsuccessful due to Abort
command.
GSR.3 = QUEUESTATUS
, 1 = Queue Full
o = Queue Available
GSR.2 = PAGE BUFFER AVAILABLE STATUS
1 = One or Two Page Buffers Available
o = No Page Buffer Available
GSR.1 = PAGE BUFFER STATUS
1 = Selected Page Buffer Ready
o = Se,lected Page Buffer Busy
The device contains two Page Buffers.
Selected Page Buffer is currently busy with
WSM operation
GSR.O = PAGE BUFFER SELECT STATUS
1 = Page Buffer 1 Selected
o = Page Buffer 0 Selected
NOTE:
1. WMn multiple operations are queued, checking BSR. 7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.
3-372
28F016SA
4.7 Block Status Register
BS
BLS
BOS
BOAS
QS
VPPS
7
6
5
4
3
2
R
R
o
NOTES:
BSR.7 =
BLOCK STATUS
1 = Ready
0= Busy
BSR.6 =
BLOCK-LOCK STATUS
1 = Block Unlocked for Write/Erase
o = Block Locked for Write/Erase
BSR.5 =
BLOCK OPERATION STATUS
1 = Operation Unsuccessful
o = Operation Successful or
Currently Running
BSR.4 =
BLOCK OPERATION ABORT STATUS
1 = Operation Aborted
o = Operation Not Aborted
MATRIX 5/4
o 0 = Operation Successful or
Currently Running
o 1 = Not a Valid Combination
1 0 = Operation Unsuccessful
1 1 = Operation Aborted
BSR.3 =
QUEUE STATUS
1 = Queue Full
o = Queue Available
BSR.2 =
Vpp STATUS
1 = Vpp Low Detect, Operation Abort
0= VppOK
[1] RY /BY# output or BS bit must be checked to
determine completion of an operation (Block Lock,
Suspend, Erase or Data Write) before the appropriate
Status bits (BOS, BLS) is checked for success.
The BOAS bit will not be set until BSR.7 = 1.
Operation halted via Abort command.
NOTES:
BSR.l-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the BSRs.
1. When multiple operations are queued, checking BSR. 7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.
3-373
intel®
28F016SA
5.0
ELECTRICAL SPECIFICATIONS
5.1 Absolute Maximum Ratings*
Temperature Under Bias ............ O°C to + 80°C
Storage Temperature .......... - 65°C to + 125°C
NOTICE: This data sheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a de!;ign.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
COMMERCIAL TEMPERATURE OPERATION
Vee
=
3.3V ± O.3V Systems(5)
Symbol
Parameter
Notes
Min
Max
Units
Test Conditions
Ambient Temperature
Operating Temperature, Commercial
1
0
70
°C
Vee
Vee with Respect to GND
2
-0.2
7.0
V
Vpp
Vpp Supply Voltage with Respect to GND
2,3
-0.2
14.0
V
V
Voltage on any Pin (except Vee,Vpp)
with Respect to GND
2
-0.5
Vee
+0.5
V
I
Current into any Non-Supply Pin
± 30
mA
lOUT
Output Short Circuit Current
100
mA
Max
Units
Test Conditions
Ambient Temperature
TA
4
Vee = 5.0V ± O.5V, Vee = 5.0V ± O.25V Systems(5,6)
Symbol
Parameter
Notes
Min
TA
Operating Temperature, Commercial
1
0
70
°C
2
-0.2
7.0
V
2,3
-0.2
14.0
V
2
-2.0
7.0
V
± 30
mA
100
mA
Vee
Vee with Respect to GND
Vpp
Vpp Supply Voltage with Respect to GND
V
Voltage on any Pin (except Vee,Vpp)
with Respect to GND
I
Current into any Non-Supply Pin
lOUT
Output Short Circuit Current
4
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum DC voltage on input/output pins is Vce + 0.5V which, during transitions, may overshoot to Vec + 2.0V
for periods <20 ns.
3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods <20ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Ae specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
6. 5% Vee specifications refer to the 28F016SA-70 in its High Speed Test configuration.
3-374
28F016SA
5.2 Capacitance
For a 3.3V System:
Symbol
Parameter
Note
Typ
Max
Units
1
6
8
pF
TA
=
25°C, f
=
8
=
25°C, f
= 1.0 MHz
± 0.3V
CIN
Capacitance Looking into an
Address/Control Pin
COUT
Capacitance Looking into an Output Pin
1
CLOAD
Load Capacitance Driven by Outputs
for Timing Specifications
1
Equivalent Testing Load Circuit
Test Conditions
1.0 MHz
12
pF
TA
50
pF
For Vee
2.5
ns
50n transmission
line delay
=
3.3V
For a 5.0V System:
Symbol
Note
Typ
Max
Units
CIN
Capacitance Looking into an
Address/Control Pin
Parameter
1
6
8
pF
TA
=
Test Conditions
25°C, f
=
1.0 MHz
COUT
Capacitance Looking into an Output Pin
1
8
12
pF
TA
=
25°C, f
=
1.0 MHz
CLOAD
Load Capacitance Driven by Outputs
for Timing Specifications
1
100
pF
For Vee
30
pF
For Vee
Equivalent Testing Load Circuit for
Vee ± 10%
2.5
ns
25n transmission
line delay
Equivalent Testing Load Circuit for
Vee ± 5%
2.5
ns
83n transmission
line delay
=
=
5.0V ± 0.5V
5.0V ± 0.25V
NOTE:
1. Sampled, not 100% tested.
3-375
28F016SA
5.3 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
tELQV time(t) from CE # (E) going low (L) to the outputs (Q) becoming valid (V)
tGLQV time(t) from OE # (G) going low (L) to the outputs (Q) becoming valid (V)
tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H)
tWHDX time(t) from WE # (W) going high (H) to when the data (D) can become undefined (X)
Pin States
Pin Characters
A
Address Inputs
H
High
D
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
CE# (Chip Enable)
X
Driven, but not necessarily valid
F
BYTE# (Byte Enable)
Z
High Impedance
G
OE # (Output Enable)
W
WE # (Write Enable)
P
RP# (Deep Power-Down Pin)
R
RY IBY # (Ready Busy)
V
Any Voltage Level
Y
3/5# Pin
5V
Vee at 4.5V Minimum
3V
Vee at 3.0V Minimum
3-376
28F016SA
I_NP_U_T_JX:::
2.4 _ _
0.45
> 5 <:
2.0
OUTPUT
TESST POINTS
0.8
290489-4
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0". Input timing begins
at VIH (2.0 VTTL) and VIL (O.B VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10
ns.
Figure 6. Transient Input/Output Reference Waveform (Vee
for Standard Test Configuration(1)
::: __I_NP_U_T_JX'5+--TE;T POINTS----.
1.5
=
5.0V
±
10%)
OUTPUT
290489-5
AC test inputs are driven at 3.0V for a Logic "1" and O.OV for a Logic "0". Input timing begins, and output timing
ends, at 1.5V. Input rise and fall times (10% to 90%) < 10 ns.
Figure 7. Transient Input/Output Reference Waveform (Vee = 3.3V)
High Speed Reference Waveform(2) (Vee = 5.0V ± 5%)
NOTES:
1. Testing characteristics for 2BF016SA-OBO/2BF016SA-100.
2. Testing characteristics for 28F016SA-070/28F016SA-120/28F016SA-150.
3-377
28F016SA
2.S ns of 2Sn Transmission Line
• From Output
Under Test
( )
f'
Test
Point •
290489-6
Total Capacitance = 100 pF
Figure 8. Transient Equivalent Testing Load Circuit (Vee
=
S.OV ± 10%)
2.5 ns of son Transmission Line
• From Output
Under Test
()
Test
Point •
290489-7
Total Capacitance = 50 pF
Figure 9. Transient Equivalent Testing Load Circuit (Vee = 3.3V
± 0.3V)
2.5 ns of 830. Transmission Line
• From Output
()
Under Test
Test
Point •
290489-8
Total Capacitance = 30 pF
Figure 10. High Speed Transient Equivalent Testing Load Circuit (Vee = S.OV ± S%)
3-378
28F016SA
5.4 DC Characteristics: COMMERCIAL TEMPERATURE
vee = 3.3V ± O.3V, T A = O°C to + 70°C
3/5# = Pin Set High for 3.3V Operations
Symbol
Parameter
Notes
Max
Units
IlL
Input Load Current
1
±1
p,A
Vee
= Vee Max, VIN = Vee or GND
ILO
Output Leakage
Current
1
±10
p,A
Vee
= Vee Max, VIN = Vee or GND
lees
Vee Standby Current
50
100
p,A
Vee = Vee Max,
CEo#,CE1#,RP#, = Vee ± O.2V
BYTE#,WP#,3/5# = Vee ±
0.2V or GND ± 0.2V
1
4
mA
Vee = Vee Max,
CEo#,CE1#,RP# = VIH
BYTE#, WP#, 3/5# = VIHorVIL
1
1
5
p,A
RP# = GND ± 0.2V
BYTE# = Vee ± 0.2V or GND ± O.2V
1.5
Min
Typ
Test Conditions
leeD
Vee Deep Power-Down
Current
leeR1
Vee Read Current
1,4,5
30
35
mA
Vee = Vee Max,
CMOS: CEo #, CE1 # = GND ± O.2V
BYTE# = GND ± 0.2VorVee ± 0.2V
Inputs = GND ± 0.2V or
Vee ± 0.2V,
TIL: CEo #, CE1 # = VIL,
BYTE# = VILorVIH
Inputs = VIL or VIH,
f = 8 MHz, lOUT = 0 mA
leeR2
Vee Read Current
1,4,5
15
20
mA
Vee = Vee Max,
CMOS: CEo #, CE1 # =
GND ± 0.2V, BYTE # = Vee
± 0.2V or GND ± O.2V
Inputs = GND ± 0.2Vor
Vee ± 0.2V,
TIL:CEo#,CE1# = VIL
BYTE# = VIH or VIL
Inputs = VIL or VIH,
f = 4 MHz, lOUT = 0 mA
leew
Vee Write Current
1
8
12
mA
Word/Byte Write in
Progress
IeeE
Vee Block Erase
Current
1
6
12
mA
Block Erase in Progress
leeES
Vee Erase Suspend
Current
1,2
3
6
mA
CEo#,CE1# = VIH
Block Erase Suspended
IpPS
Vpp Standby Current
1
±1
±10
p,A
Vpp';; Vee
IpPD
Vpp Deep Power-Down
Current
1
0.2
5
p,A
RP# = GND ±0.2V
3-379
intel®
28F016SA
5.4 DC Characteristics: COMMERCIAL TEMPERATURE (Continued)
+
Vcc = 3.3V ± 0.3V, T A = O°C to
70°C
3/5# = Pin Set High for 3.3V Operations
Symbol
Parameter
Notes
Min
65
Typ
Max
Units
Test Conditions
IpPR
VPP Read Current
1
200
p.A
Vpp> Vcc
Ippw
VPP Write Current
1
10
15
mA
VPP = VPPH,
Word/Byte Write in Progress
IpPE
VPP Erase Current
1
4
10
mA
VPP = VpPH,
Block Erase in Progress
IpPES
VPP Erase Suspend
Current
1
65
200
p.A
VPP = VpPH,
Block Erase Suspended
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage
Vcc
+
0.4
2.4
0.3
V
V
Vcc = Vee Min and
IOL = 4mA
V
= -2.0 mA
= Vce Min
IOH = -100 p.A
Vcc = Vee Min
IOH
Vce
Vee - 0.2
VOH2
VPPL
Vpp during Normal
Operations
VPPH
VPP during Write/
Erase Operations
11.4
VLKO
Vcc Erase/Write
Lock Voltage
2.0
3
0.0
12.0
6.5
V
12.6
V
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vec = 3.3V, VPP = 12.0V, T = 25'C. These currents
are valid for all product versions (package and speeds).
2. leeES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of leCES and ICCR.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when VPP ~ VPPL and not guaranteed in the
range between VpPH and VpPL.
4. Automatic Power Savings (APS) reduces ICCR to less than 1 mA in static operation.
5. CMOS Inputs are either VCC ± O.2V or GND ± O.2V. TIL Inputs are either VIL or VIH.
3-380
28F016SA
5.5 DC Characteristics: COMMERCIAL TEMPERATURE
5.0V ± O.5V, T A = O°C to + 70°C
vcc =
3/5# Pin Set Low for 5V Operations
Symbol
Parameter
Notes
Min
Typ
Max
Units
Test Conditions
ilL
Input Load
Current
1
±1
,...A
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage
Current
1
±10
,...A
Vee = Vee Max
VIN = Vee or GND
Ices
Vee Standby
Current
50
100
,...A
Vee = Vee Max
CEo#,CE1#,RP# =Vee±
0.2V
BYTE#, WP#, 3/5# = Vee ±
0.2V or GND ± 0.2V
2
4
rnA
Vee = Vee Max
CEo#, CE1 #, RP# = VIH
BYTE#, WP#, 3/5# = VIH or
VIL
1
1
5
,...A
RP# = GND ± 0.2V
BYTE# = Vee ± 0.2V or GND ± 0.2V
1,5
IceD
Vee Deep
Power-Down
Current
leeR1
Vee Read
Current
1,4,5
50
60
rnA
Vee = Vee Max,
CMOS:CEo#,CE1# = GND ± 0.2V
BYTE# = GND ± 0.2V or Vee ± 0.2V
Inputs = GND ± 0.2Vor
Vee ± 0.2V,
TTL: CEo#, CE1# = VIL,
BYTE# = VILorVIH
Inputs = VIL or VIH,
f = 10 MHz, lOUT = 0 rnA
leeR2
Vee Read
Current
1,4,5
30
35
rnA
Vee = Vee Max,
CMOS: CEo #, CE1 # =
GND ± 0.2V
BYTE# = Vee ± 0.2Vor
GND ± 0.2V
Inputs = GND ± 0.2Vor
Vee ± 0.2V
TTL: CEo#, CE1 # = VIL,
BYTE# = VIH or VIL
Inputs = VIL or VIH,
f = 5 MHz, lOUT = 0 rnA
leew
Vee Write
Current
1
25
35
rnA
Word/Byte in Progress
IeeE
Vee Block
Erase Current
1
18
25
rnA
Block Erase in Progress
leeES
Vee Erase
Suspend Current
1,2
5
10
rnA
CEo#, CE 1# = VIH
Block Erase Suspended
Ipps
VppStandby
Current
1
±1
±10
,...A
Vpp';; Vee
3-381
28F016SA
5.5 DC Characteristics: COMMERCIAL TEMPERATURE (Continued)
Vee = 5.0V ± O.5V, TA = O°C to + 70°C
3/5# Pin Set Low for 5V Operations
Symbol
Parameter
Notes
Min
Typ
Max
Units
Test Conditions
=
Vpp Deep PowerDown Current
1
0.2
5
/LA
RP#
IpPR
VPP Read Current
1
65
200
/LA
Vpp> Vee
Ippw
Vpp Write Current
1
7
12
mA
Vpp = VPPH
WordlByte Write in Progress
IpPE
Vpp Block Erase
Current
1
5
10
mA
VPP = VpPH
Block Erase in Progress
IpPES
Vpp Erase Suspend
Current
1
65
200
/LA
VPP = VPPH
Block Erase Suspended
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage
0.8
Vee
+ 0.5
0.45
0.85
V
V
V
Vee = Vee Min
IOL = 5.8mA
V
IOH = -2.5 mA
Vee = Vee Min
Vee
IOH = -100/LA
Vee = Vee Min
Vee - 0.4
VOH2
3
0.0
VPPL
VPP during Normal
Operations
VPPH
VPP during Erasel
Write Operations
11.4
VLKO
Vee EraselWrite
Lock Voltage
2.0
GND
± O.2V
IpPD
12.0
6.5
V
12.6
V
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = s.OV, VPP = 12.0V, T = 2S'C. These currents
are valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases, WordlByte Writes and Lock Block operations are inhibited when VPP = VPPL and not guaranteed in the
range between VpPH and VpPL.
4. Automatic Power Saving (APS) reduces ICCR to less than 2 mA in Static operation.
5. CMOS Inputs are either VCC ± O.2V or GND ± O.2V. TTL Inputs are either VIL or VIH.
3-382
28F016SA
5.6 AC Characteristics-Read Only Operations: COMMERCIAL TEMPERATURE(1)
3.3V ± 0.3V TA = 0° to + 70°C
vee =
Versions (5)
Symbol
Parameter
Notes
28F016SA-120
28F016SA-150
Min
Min
Max
Max
Units
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE # to Output Delay
tpHQV
RP# High to Output Delay
tGLQV
OE# to Output Delay
2
tELQX
CE # to Output in Low Z
3
tEHQZ
CE# to Output in High Z
3
tGLQX
OE # to Output in Low Z
3
tGHQZ
OE # to Output in High Z
3
tOH
Output Hold from Address,
CE # or OE # Change,
Whichever Occurs First
3
tFLQV
tFHQV
BYTE # to Output Delay
3
120
150
ns
tFLQZ
BYTE # Low to Output
in HighZ
3
30
40
ns
tELFL
tELFH
CE# Low to BYTE#
High or Low
3
5
5
ns
120
150
120
ns
150
ns
120
150
ns
620
750
ns
50
ns
2
45
0
0
50
ns
55
0
0
ns
40
30
0
ns
0
ns
ns
For Extended Status Register Reads
Versions (5)
Symbol
28F016SA-120
Max
28F016SA-150
Min
Max
Units
Parameter
Notes
Min
tAVEL
Address Setup to
CE # Going Low
3,4
0
0
ns
tAVGL
Address Setup to
OE# Going Low
3,4
0
0
ns
3-383
28F016SA
5.6 AC Characteristics-Read Only Operations(1) (Continued)
+ 70°C
Vcc = 5.0V ± O.5V, TA = O°C to
Verslons(S)
Vee ± 5%
28F016SA·070(6)
Vee ± 10%
Symbol
Parameter
Notes
28F016SA·080(7)
Min
Max
70
Min
Max
28F016SA·100(7)
Min
tAVAV
Read Cycle Time
tAVQV
Address to Output
Delay
tELQV
CE # to Output
Delay
tpHQV
RP# to Output
Delay
tGLQV
OE # to Output
Delay
2
tELQX
CE # to Output in
LowZ
3
tEHQZ
CE # to Output in
HighZ
3
tGLQX
OE # to Output in
LowZ
3
tGHQZ
OE # to Output in
HighZ
3
toH
Output Hold
from Address,
CE# orOE#
Change, Whichever
Occurs First
3
tFLQV
tFHQV
BYTE# to Output
Delay
3
70
80
100
ns
tFLQZ
BYTE# Lowto
Output in High Z
3
25
30
30
ns
tELFL
tELFH
CE # Low to BYTE #
High or Low
3
5
5
5
ns
2
100
Units
Max
80
\
ns
70
80
100
ns
70
80
100
ns
400
480
550
ns
30
35
40
ns
0
30
25
0
0
35
0
35
0
0
ns
ns
0
30
25
ns
0
0
ns
ns
For Extended Status Register Reads
Verslons(S)
vee ± 5%
28F016SA·070(6)
Vee ± 10%
Symbol
28F016SA·080(7)
Max
Min
Max
28FO 16SA·1 00(7)
Min
Units
Parameter
Notes
Min
Max
tAVEL
AddrllsS Setup to
CE# GOing Low
3,4
0
0
0
ns
tAVGL
Address Setup to
OE # GOing Low
3,4
0
0
0
ns
NOTES:
1. See AC Input/Output Reference Waveforms for timing measurements, Figures 6 and 7.
2. OE# may be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV.
3. Sampled, not 100% tested.
4. This timing parameter is used to latch the correct BSR data onto the outputs.
5. Device Speeds are defined as:
70/80 ns at Vee = 5.0V equivalent to
120 ns at Vee = 3.3V
100 ns at Vee = 5.0V equivalent to
150 ns at Vee = 3.3V
6. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for High Speed Test Configuration.
7. See Standard AC Input/Output Reference Waveforms and AC Testing Load Circuit.
3·384
28F016SA
OUTPUTS ENABLED
Vee POWER-UP
STANDBY
DATA VALID
VIH
ADDRESSES (A)
'Vee POWER-DOWN
ADDRESSES STABLE
VIL
14-------- IAVAV---------i+I
OE# (G)
VOH
HIGH Z
HIGH Z
DATA (0/0)
·V OL
14-----IAVQV------I~
5.0V
Vee
GND
VIH
RP#(P)
VIL
1+------ I pHQV ------------H
)
\
290489-9
NOTE:
.
1. CEx;ll is defined as the latter of CEo;ll or CE1;11 going Low or the first Of CEo;ll or CE1;11 going High.
Figure 11. Read Timing Waveforms
3·385
28F016SA
V IH
ADDRESSES (A)
VIL
XXXXXXX)l
-----
ADDRESSES STABLE
t AVAV
XXXXX!)(
V IH
'\
CExo (E)( ,)
VIL
tAm =
/
---
it:LfL
~
t AvEL
OEO (G)
'\
t AVGl
'\
---- J
tGLOV
~X
HIGH Z
t[lOX
DATA (000-007)
VOL
DATA (DaB-DO'S)
VOL
tOH
/I\ \-
t AVOV
V OH
HIGH Z
~
t FlOV -t AVOV
t[lOV
V OH
/
---
~
OUTPUT~~~)(
DATA
-t
DATA
OUTPUT
4-
.\ \
HIGH Z
.//
t FlOZ
-r1/7
-\. \ \..1
DATA \
OUTPUT
I
HIGH Z
290489-10
NOTE:
1. CExil! is defined as the latter of CEoil! or CE1 iI! going Low or the first of CEoil! or CE1 iI! gOing High.
Figure 12. BYTE # Timing Waveforms
3-S86
28F016SA
5.7 Power-Up and Reset Timings: COMMERCIAL TEMPERATURE
Vee POWER UP
RP#
(p)
t YHPH
3/5#
(y)
-
t YLPH
~
I
-.
t pLYL ~
5.0V
/
J
"'"
3.3V
Vee
OV
(3V,5V)
t pL5V
Address
(A)
Data
XXXX.
(XXX.
-+
X
VALID
txXXXX, XXX]'
tAV~
.-+
VALID
3.3V OUTPUTS
(Q)
VALID
~AVQV
VALID
"/
5.0V OUTPUTS
+---+
tpHQV
tpHQV
290489-12
Figure 13. Vee Power-Up and RP# Reset Waveforms
Symbol
Parameter
tPLYL
tPLYH
RP# Low to 3/5# Low (High)
tYLPH
tYHPH
3/5# Low (High) to RP# High
tpL5V
tpL3V
Note
Min
Max
Unit
0
JLs
1
2
JLs
RP# Low to Vcc at 4.5V Minimum
(to Vcc at 3.0V min or 3.6V max)
2
0
JLs
tAVQV
Address Valid to Data Valid
forVcc = 5V ± 10%
3
80
ns
tpHQV
RP# High to Data Valid for
Vcc = 5V ± 10%
3
480
ns
NOTES:
CEo#, CE1 # and OE# are switched low after Power-Up.
1. Minimum of 2 ,..s is required to meet the specified tpHQV times.
2. The power supply may start to switch concurrently with RP# going Low.
3. The address access time and RP # high to data valid time are shown for 5V Vee operation. Refer to the AC Characteristics Read Only Operations 3.3V Vee operation and all other speed options.
3-387
28F016SA
5.8 AC Characteristics for WE #-Controlled Command Write Operations:
COMMERCIAL TEMPERATURE(1)
Vee = 3.3V ± 0.3V
TA = ODC to
+ 70DC
Versions
Symbol
Parameter
tAVAV
Write Cycle Time
28F016SA·120
Notes
Min
Typ
Max
120
Min
Typ
Max
Unit
150
ns
100
100
ns
480
480
ns
tVPWH
Vpp Setup to WE# Going High
tpHEL
RP# Setup to CE# Going Low
tELWL
CE # Setup to WE # Going Low
10
10
ns
tAVWH
Address Setup to WE #
Going High
2,6
75
75
ns
tOVWH
Data Setup to WE# Going High
2,6
75
75
ns
tWLWH
WE # Pulse Width
75
75
ns
tWHOX
Data Hold from WE # High
2
10
10
ns
tWHAX
Address Hold from WE# High
2
10
10
ns
tWHEH
CE# Hold from WE# High
10
10
ns
tWHwL
WE # Pulse Width High
45
75
ns
tGHWL
Read Recovery before Write
0
0
ns
tWHRL
WE # High to RY IBY # Going Low
tRHPL
RP# Hold from Valid Status
Register (CSR, GSR, BSR) Data
and RY/BY# High
tpHWL
RP# High Recovery to
WE # Going Low
tWHGL
Write Recovery before Read
tOWL
Vpp Hold from Valid Status
Register (CSR, GSR, BSR) Data
and RY IBY # High
tWHOV1
Duration of Word/Byte
Write Operation
tWHOV2
Duration of Block
Erase Operation
3·388
3
28F016SA·150
100
3
100
ns
0
0
ns
1
1
J.l.s
95
120
ns
0
0
J.l.s
4,5
5
4
0.3
9
Note 7
5
10
0.3
9
Note 7
J.l.s
10
sec
28F016SA
AC Characteristics for WE#-Controlled Command Write Operations(1) (Continued)
Vcc = 5.DV ± D.5V TA = DOC to
Versions
+ 7DoC
28F016SA-070
Vee ±5%
28F016SA-080
Vee ±10%
Symbol
Parameter
tAYAY
Write Cycle Time
tYPWH
Vpp Setup to WE#
Going High
tpHEl
Notes
Min
Typ
Max
70
Min
Typ
Max
28F016SA-100
Min
Typ
Unit
Max
80
100
ns
100
100
100
ns
RP# Setup to CE#
Going Low
480
480
480
ns
tElWl
CE# SetuptoWE#
Going Low
0
C
0
ns
tAVWH
Address Setup to
WE# Going High
2,6
50
50
50
ns
tOVWH
Data Setup to WE#
Going High
2,6
50
50
50
ns
3
tWLrl~:
: WE# Pulse Width
40
50
50
ns
tWHOX
Data Hold from
WE# High
2
0
0
0
ns
tWHAX
Address Hold from
WE# High
2
10
10
10
ns
tWHEH
CE# Hold from
WE# High
10
10
10
ns
tWHWl
WE # Pulse Width
High
30
30
50
ns
tGHWl
Read Recovery
before Write
0
0
0
ns
tWHRl
WE# HightoRYI
BY # GOing Low
tRHPl
RP# Hold from
Valid Status
Register (CSR,
GSR, BSR) Data
and RY/BY# High
tPHWl
RP# High
Recovery to WE#
Going Low
tWHGl
100
100
100
ns
0
0
0
ns
1
1
1
,...s
Write Recovery
before Read
60
65
80
ns
tOWl
Vpp Hold from Valid
Status Register
(CSR, GSR, BSR)
Data and RY IBY #
High
0
0
0
,...s
tWHOy1
Duration of Wordl
Byte Write
Operation
4,5
4.5
tWHOy2
Duration of Block
Erase Operation
4
0.3
3
6
Note 7
4.5
10
0.3
6
Note 7
4.5
10
0.3
6
Note 7
,...s
10
sec
3-389
28F016SA
NOTES:
CE# is defined as the latter of CEo# or CE1 # going Low or the first of CEo# or CE1 # going High.
1. Read timings during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Register (CSR) Data.
5. Word/Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of WE# for all Command Write operations.
7. This information will be available in a technical paper. Please call Intel's Application Hotline or your local sales office for
more information.
DEEP
POWER-DOWN
WRITE DATA-WRITE OR
ERASE SETUP COI.IMAND
&: ~~I;! ~;;~~_~~I~~~SOR AUTOMATEO DATA-WRITE
ERASE CONFIRM COlrollolANO
OR ERASE DELAY
WRITE READ EXTENDEO
REGISTER COMMAND
READ EXTENDED
STATUS REGISTER DATA
__
READ COMPATIBLE
STATUS REGISTER DATA
VlHl~~~~~~~~(::~:J~~~~~~~~~~~~C=~~==~~~~~~~~
NOTE I
ADDRESSES
(Al V1L
~_~~=--i»-
V"
ADDRESSES (A) V 1H
NOTE 2
A=RA
~Ol~! ____-
_
C[x# (E)
NOTE"
0[# (G)
tWHQV1,2
W(#
(w)
DATA (O/Q)
V,H
V"
RY IBYN (R)
RP# (p)
'\.......
-----_ .......... -- -_ .. ---
t VPWH
V pPH
Vpp (v)
V pPL
V"
v"
290489-13
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. CEx# is defined as the latter of CEo# or CE1 # gOing Low or the first of CEo# or CE1 # going High.
5. RP# low transition is only to show tRHPL; not valid for above Read and Write cycles.
Figure 14. AC Waveforms for Command Write Operations
3-390
28F016SA
5.9 AC Characteristics for CE#-Controlled Command Write Operations:
COMMERCIAL TEMPERATURE(1)
vee = 3.3V ± 0.3V T A = O·C to + 70·C
Versions
Symbol
Parameter
tAVAV
Write Cycle Time
tVPEH
VPP Setup to CE# Going high
28F016SA-120
Notes
Min
Typ
Max
28F016SA-150
Min
Typ
Unit
Max
120
150
ns
100
100
ns
tPHWL
RP# Setup to WE# Going Low
480
480
ns
tWLEL
WE # Setup to CE # Going Low
0
0
ns
tAvEH
Address Setup to
CE # Going High
2,6
75
75
ns
tDVEH
Data Setup to CE # Going High
2,6
75
75
ns
tELEH
CE # Pulse Width
75
75
ns
tEHDX
Data Hold from CE# High
2
10
10
ns
tEHAX
Address Hold from CE # High
2
10
10
ns
tEHWH
WE # Hold from CE # High
10
10
ns
tEHEL
CE # Pulse Width High
45
75
ns
tGHEL
Read Recovery before Write
0
0
ns
tEHRL
CE # High to RY IBY # Going Low
tRHPL
RP# Hold from Valid Status
Register (CSR, GSR, BSR) Data
and RY IBY # High
tpHEL
RP# High Recovery to
CE # Going Low
tEHGL
Write Recovery before Read
tQVVL
VPP Hold from Valid Status
Register (CSR, GSR, BSR) Data
at RY IBY # High
tEHQV1
Duration of Word/Byte
Write Operation
tEHQV2
Duration of Block
Erase Operation
3
100
3
100
ns
0
0
ns
1
1
IL s
95
120
ns
0
0
IL s
4,5
5
4
0.3
9
Note 7
5
10
0.3
9
Note 7
IL s
10
sec
3-391
28F016SA
AC Characteristics for CE #-Controlled Command Write Operations(1) (Continued)
= 5.0V ± O.5V, TA = O· to + 70·C
VCC
Versions
28F016SA·070
Vee ±50/0
28F016SA·080
Vee ±100/0
Symbol
Parameter
Notes
Min
Typ
Max
Min
Typ
Max
28F016SA·100
Min
Typ
Unit
Max
tAVAV
Write Cycle Time
70
80
100
ns
tVPEH
Vpp Setup to CE#
Going High
3
100
100
100
ns
tPHWL
RP# SetuptoWE#
GOing Low
3
480
480
480
ns
tWLEL
WE# Setup to CE#
Going Low
0
0
0
ns
tAvEH
Address Setup to
CE# Going High
2,6
50
50
50
ns
tDVEH
Data Setup to CE #
Going High
2,6
50
50
50
ns
tELEH
CE# Pulse Width
40
50
50
ns
tEHDX
Data Hold from
CE# High
2
0
0
0
ns
tEHAX
Address Hold from
CE# High
2
10
10
10
ns
tEHWH
WE# Hold from
CE# High
10
10
10
ns
tEHEL
CE# Pulse Width
High
30
30
50
ns
tGHEL
Read Recovery
before Write
0
0
0
ns
tEHRL
CE# High to RYI
BY # Going Low
tRHPL
RP# Hold from
Valid Status
Register (CSR,
GSR, BSR) Data
and RY/BY# High
tpHEL
RP# High
Recovery to CE #
Going Low
tEHGL
Write Recovery
before Read
tOWL
Vpp Hold from Valid
Status Register
(CSR, GSR, BSR)
Data and RY IBY #
High
100
3
100
ns
0
0
0
ns
1
1
1
,...s
60
65
80
ns
0
0
0
,...s
tEHOv1
. Duration of Wordl
Byte Write
Operatipn
4,5
4.5
tEHov2
Duration of Block
Erase Operation
4
0.3
3-392
100
6
Note 7
4.5
10
0.3
6
Note 7
4.5
10
0.3
6
Note 7
,...s
10
sec
28F016SA
NOTES:
CE# is defined as the latter of CEo# or CE1 # going Low or the first of CEo# or CE1 # going High.
1. Read timings during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, but not 100% tested.
4. Write/Erase durations are measured to valid Status Data.
5. Word/Byte write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CE# for all Command Write Operations.
7. This information will be available in a technical paper. Please call Intel's Application Hotline or your local sales office for
more information.
ADDRESSES
DEEP
WRITE DAlk-WRITE OR
POWER-DOWN
ERASE SETUP COMMAND
(AJ v IH
NOTE 1
&: ~~:! ~;;~~_A~~I~~~SOR AUTOMATED DATA-WRITE
ERASE CONFIRM COMMANO
OR ERASE DELAY
REGISTER COMMAND
READ EXTENDED
STATUS REGISTER DATA
A=RA
Vll
V'H~~~~~~~~~~;;AI~";:~(J~)<0,30&'X>
ADDRESSES (A)
NOTE 2
VIL~
W[#
WRITE READ EXTENDED
A IN
_____
~c:!:'': _____ _
READ COMPATIBLE
STATUS REGISTER DATA
_
_
(w)
0[# (G)
t[HQV1.2
CEx# (E)
NOTE 4
DATA (0/0)
RY /8Y# (R)
RP# (P)
,,
,
~----------------------
Vpp (V)
290469-14
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data-Write/Erase operations.
4. CEx# is defined as the latter of CEo# or CE1 # going Low or the first of CEo# or CE1 # going High.
5. RP# low transition is only to show tRHPL; not valid for above Read and Write cycles.
Figure 15. Alternate AC Waveforms for Command Write Operations
3-393
28F016SA
5.10 AC Characteristics for Page Buffer Write Operations: COMMERCIAL
TEMPERATURE(1)
vcc
=
3.3V ± O.3V
TA
=
+ 7o·e.
o·e to
28F016SA-120
Versions
Symbol
Parameter
tAVAV
Write Cycle Time
Notes
Min
Typ
28F016SA-150
Max
Typ
Min
120
150
Unit
Max
ns
tELWL
CE # Setup to WE # Going Low
10
10
ns
tAVWL
Address Setup to WEll' Going Low
3
0
0
ns
tOVWH
Data Setup to WEll' Going High
2
75
50
ns
tWLWH
WE # Pulse Width
75
75
ns
ns
tWHOX
Data Hold from WEll' High
2
10
10
tWHAX
Address Hold from WE # High
2
10
10
ns
tWHEH
CE # Hold from WE # High
10
10
ns
tWHWL
WEll' Pulse Width High
45
75
ns
tGHWL
Read Recovery before Write
0
0
ns
tWHGL
Write Recovery before Read
95
120
ns
VCC = 5.0V
±
O.5V, T A = o·e 10
+ 70·e
Versions
Symbol
Parameter
28F016SA-070
Notes
Min
Typ
Max
28F016SA-080
Min
Typ
Max
28F016SA-100
Min
Typ
Unit
Max
tAVAV
Write Cycle Time
70
80
100
ns
tELWL
CEll' Setup to
WE # Going Low
0
0
0
ns
IAVWL
Address Setup to
WE # Going Low
3
0
0
0
ns
tOVWH
Data Setup to
WEll' Going High
2
50
50
50
ns
tWLWH
WE # Pulse Width
40
50
50
ns
tWHOX
Data Hold from
WEll' High
2
0
0
0
ns
tWHAX
Address Hold
from WE # High
2
10
10
10
ns
tWHEH
CE'" Hold from
WEll' High
10
10
10
ns
tWHWL
WE # Pulse Width
High
30
30
50
ns
tGHWL
Read Recovery
before Write
0
0
0
ns
tWHGL
Write Recovery
before Read
60
65
80
ns
NOTES:
CEll' is defined as the latter of CEo# or CEl # going Low or the first of CEo# or CEl # gOing High.
1. These are WE#-conirolled write timings, equivalent CE#-controlled write timings apply.
2. Sampled, but not 100% tested.
3. Address must be valid during the entire WE # Low pulse or the entire CE # Low pulse for CE # -controlled writes.
3-394
28F016SA
tWHEH
WE#
(W)
VIL
t WLWH
VALID
IH
DATA
V
HIGH Z
(
(0/0)--VIL
290489-15
Figure 16. Page Buffer Write Timing Waveforms
(Loading Data to the Page Buffer)
3·395
28F016SA
5.11
Vee
Erase and Word/Byte Write Performance, Cycling Performance and
Suspend Latency(f, 3)
= 3.3V ± 0.3V, vPP = 12.0V ± 0.6V, TA = O°C to +70°C
Symbol
Parameter
Notes
Typ
Max
Units
Page Buffer Byte Write Time
1,2,4
3.26
Note 6
/Ls
Page Buffer Word Write Time
1,2,4
6.53
Note 6
/Ls
Min
Test Conditions
tWHRH1
Word/Byte Write Time
1,2
9
Note 6
/Ls
tWHRH2
Block Write Time
1,2
0.6
2.1
Sec
Byte Write Mode
tWHRH3
Block Write Time
1,2
0.3
1.0
Sec
Word Write Mode
Block Erase Time
1,2
0.8
10
Sec
Full Chip Erase Time
1,2
25.6
Sec
Erase Suspend Latency Time
to Read
7.0
/Ls
Erase Suspend Latency Time
to Write
10.0
/Ls
1,000,000
Cycles
Erase Cycles
Vee
=
5.0V
Symbol
±
0.5V, VPP
5
=
12.0V
±
0.6V, TA
100,000
=
O°C to + 70°C
Parameter
Notes
Max
Units
Page Buffer Byte Write Time
1,2,4
Min
2.76 ,
Typ
Note 6
/Ls
Page Buffer Word Write Time
1,2,4
5.51
Note 6
/Ls
Test Conditions
tWHRH1
Word Byte/Write Time
1,2
6
Note 6
/Ls
tWHRH2
Block Write Time
1,2
0.4
2.1
Sec
Byte Write Mode
tWHRH3
Block Write Time
1,2
0.2
1.0
Sec
Word Write Mode
Block Erase Time
1,2
0.6
10
Sec
Full Chip Erase Time
1,2
19.2
Sec
Erase Suspend Latency Time
to Read
5.0
/Ls
Erase Suspend Latency Time
to Write
8.0
/Ls
1,000,000
Cycles
Erase Cycles
5
100,000
NOTES:
1. 25'e, Vee = 3.3V or 5V nominal, 10K cycles.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. This assumes using the full Page Buffer to Write to Flash (256 bytes or 128 words).
5. Typical 1,000,000 cycle performance assumes the application uses block retirement techniques.
6. This information will be available in a technical paper. Please call Intel's Application holline or your local sales office for
more information.
3-396
28F016SA
6.0
DERATING CURVES
90
80
"C
!
"u
..Y
~
~
50
/
40
40
./
30
.s'<
"
u
_u
-a- 85°C
~25°C
---I:r- DoC
o
25
~
15
/
10
~
10
12
14
5
16
~
,/-"
V
r.I
20
-
/
20
f
30
!
.(
35
"C
V"
~
,)
45
,~
60
10
,
./
50
Af"
70
.s'<
55
rn:)
o
~
-a- 85°C
-0- 25°C
---I:r- ooc
?
-
"
vi
10
FREQUENCY (MHz)
12
14
16
FREQUENCY (MHz)
290489-16
Figure 17. lee vs Frequency (Vee
for x8 or x16 Operation
=
290489-19
Figure 18. Ice vs Frequency (Vee = 3.6V)
for x8 or x16 Operation
5.5V)
45 rnA
,~
ICC Erase
't
I
I.
-
I..
5 mA/div
IIdlil
,,;J
.Ll.u.il
I
-5 rnA
-208 ms
792 ms
100ms/div
290489-18
Figure 19. lee during Block Erase
3·397
28F016SA
40mA
Ipp Erase
S mA/div
-- -- --- -- --- --- --- - - --- - -- - - -.
/"'1'1
.it.
'~
-lOrnA
-200 ms
~ ~ \WIlli "';1
SOOms
Oms
600 ms
100 ms/div
290489-21
Figure 20. Ipp during Block Erase
-----0
140
-0-__
120
.,
100
.s-
"
E
-
80
;::
~
""
«"
60
•
•
•
•
•
vee = 3,3V
• vee = 5.0V
o
40
Temp= 70°C
20
0
0
50
100
150
200
250
Output load Capacitance (pF)
290489-24
Figure 21. Access Time (tACC) vs Output Loading
3-398
28F016SA
- - - - - f------
--kl----I
I-
:
5 mA/div
5 mA/div
16.04
-2 J.J.s 0 J.ls
j.ls
2 J.ls/div
290489-25
Figure 22. Ipp during Word Write Operation
I---+---Ir---tl----j--+---+---I-Tt----+---l
- 10 mA '----'-__I_--'--'--'----'----'----,!-'---'----'
-9.9 ",s
40.1 J.ls
5 J.Ls/div
290489-26
Figure 23. Ipp during Page Buffer Write Operation
3-399
28F016SA
7.0
MECHANICAL SPECIFICATIONS FOR TSOP
0-1
-+J
I+-A2
,
_0
~oll
--.j,IJ
A~,-_ _ _ _ _ _~~SEE DETAIL A
r--~~----------~~
DETAil B
DETAil A
290489-28
Figure 24. Mechanical Specifications of the 28F016SA 56-L-TSOP Type 1 Package
Family: Thin Small Outline Package
Symbol
Millimeters
Minimum
Nominal
A
1.20
A1
0.50
A2
0.965
0.995
1.025
b
0.100
0.150
0.200
c
0.115
0.125
0.135
D1
18.20
18.40
18.60
E
13.80
14.00
14.20
e
0.50
D
19.80
20.00
20.20
L
0.500
0.600
0.700
56
N
0
0°
3°
0.150
0.250
Y
Z
3-400
Maximum
5°
0.100
0.350
Notes
28F016SA
8.0 MECHANICAL SPECIFICATIONS FOR SSOP
TIl
r
0
H.
nnnnnnnnnnnnnnnill
'-rrInnnnnnnI
DETAIL A
290489-32
Figure 25. Mechanical Specifications of the 56-Lead SSOP Package
Family: Shrink Small Outline Package
Symbol
Millimeters
Minimum
Nominal
1.80
1.90
0.47
0.52
0.57
A
A1
Maximum
A2
1.18
1.28
1.38
B
0.25
0.30
0.20
C
0.13
0.15
0.20
0
23.40
23.70
24.00
E
13.10
13.30
13.50
0.80
e1
He
15.70
16.00
0.45
0.50
2·
3·
N
L1
16.30
56
Y
a
Notes
0.55
0.10
4·
b
3·
4·
5·
R1
0.15
0.20
0.25
R2
0.15
0.20
0.25
3-401
28F016SA
DEVICE NOMENCLATURE AND ORDERING INFORMATION
I
ACCESS SPEED
DA = COMMERCIAL
56-LEAD SSOP
E = COMMERCIAL
56-LEAD TSOP
70 ns
100 ns
290489-29
Valid Combinations
Option
Order Code
1
E28F016SA-070
Vee
=
3.3V ± 0.3V,
50 pF Load
Vee = 5.0V ± 10%,
100pF Load
E28F016SA-120
E28F016SA-080
2
E28F016SA-100
E28F016SA-150
E28F016SA·100
3
DA28F016SA-070
DA28F016SA-120
DA28F016SA·080
4
DA28F016SA-100
DA28F016SA-150
DA28F016SA-100
Vee = 5.0V ± 5%,
30 pF Load
E28F016SA-070
DA28F016SA-070
ADDITIONAL INFORMATION
AP-393
AP-378
AP-377
AP-375
AP-357
AP-374
AP-607
ER-33
Item
Order Number
28F016SA 16-Mbit FlashFiie™ Memory User's Manual
DD28F032SA 32-Mbit FlashFile™ Memory Data Sheet
28F016SV FlashFiie™ Memory Data Sheet
28F008SA Data Sheet
"28F016$V Compatibility with 28F016SA"
"System Optimization Using the Enhanced Features of the 28F016SA"
"28F016SA Software Drivers"
"Upgrade Considerations from the 28F008SA to the 28F016SA"
"Power Supply Solutions for Flash Memory"
"Flash Memory Write Protection Techniques"
"Multi-Site Layout Planning with Intel's FlashFile™ Components Including ROM"
"Small and Low-Cost Power Supply Solution for Intel's Flash Memory Products"
"ETOXTM Flash Memory Technology-Insight to Intel's Fourth Generation
Process Innovation"
FLASH Builder Design Resource Tool
297372
290489
290528
290435
292144
292127
292126
292124
292092
292123
292159
297534
294016
..
297508
Please check With Intel Literature for availability.
DATASHEET REVISION HISTORY
Number
-002
3-402
Description
-
Added 56-Lead SSOP Package
Separated AC Read Timing Specs TAVEL, T AVGL for Extended Status Register Reads
Modified DEVICE NOMENCLATURE
Added ORDERING INFORMATION
Added Page Buffer Typical Write Performance numbers
Added Typical Erase Suspend Latencies
For Iceo (Deep Power-Down current, BYTE# must be at CMOS levels)
Added SSOP package mechanical specifications
EXTENDED TEMPERATURE 28F016SA
16 MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile™ MEMORY
• Extended Temperature Operation
- -40°C to + S5°C
•
•
User-Selectable 3.3V or 5V Vee
100 ns Maximum Access Time at 5V
(Extended Temperature Range)
•
1 Million Typical Erase Cycles per
Block
• 20 MB/sec Burst Write Transfer Rate
• User-Configurable xS or x16 Operation
• 56-Lead 1.S mm x 16 mm x 23.7 mm
SSOP Package
• Revolutionary Architecture
- Multiple Command Execution
- Write during Erase
- Command Super-Set of the Intel
2SFOOSSA
- Page Buffer Write
• 1 mA Typical lee in Static Mode
• 3,...A Typical Deep Power-Down
• 32 Independently Lockable Blocks
• State-of-the-Art 0.6 ,...m ETOXTM IV
Flash Technology
Intel's 28F016SA 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for
designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative
capabilities, low-power, extended temperature operation and high read/write performance, the 28F016SA
enables the design of truly mobile, high-performance communications and computing products.
The 28F016SA is the highest density, highest performance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked architecture (100% compatible with the 28F008SA 8-Mbit
FlashFile memory), extended cycling, extended temperature operation, flexible Vee, fast write and read performance and selective block locking provide highly flexible memory components suitable for resident flash
arrays, high-density memory cards and PCMCIA-ATA flash drives. The 28F016SA dual read voltage enables
the design of memory cards which can interchangeably be read/written in 3.3V and 5~OV systems. Its x8/x16
architecture allows optimization of the memory-to-processor interface. Its high read performance and flexible
block locking enable both storage and execution of operating systems and application software. Manufactured
on Intel's. 0.6 ,...m ETOXTM IV process technology, the 28F016SA is the most cost effective, highest density
monolithic 3.3V FlashFile memory.
290541-1
December 1994
Order Number: 290541-001
3-403
EXTENDED TEMPERATURE 28F016SA
16 MBIT (1 MBIT x 16, 2 MBIT x 8) FlashFile™ MEMORY
CONTENTS
PAGE
1.0 INTRODUCTION ................... 3-405
1.1 Product Overview ................ 3-405
2.0 DEVICE PINOUT . .................. 3-406
2.1 Lead Descriptions ............... 3-408
3.0 MEMORY MAPS ................... 3-410
3.1 Extended Status Registers Memory
Map .............................. 3-411
4.0 BUS OPERATIONS, COMMANDS
AND STATUS REGISTER
. DEFINITIONS ....................... 3-412
4.1 Bus Operations for Word-Wide
Mode (BYTE # = VIH) ............ 3-412
4.2 Bus Operations for Byte-Wide
Mode (BYTE # = Vld ............. 3-412
4.3 2SFOOSSA-Compatible Mode
Command Bus Definitions ......... 3-413
4.4 2SF016SA-Performance
Enhancement Command Bus
Definitions ........................ 3-414
4:5 Compatible Status Register ...... 3-415
4.6 Global Status Register ........... 3-416
4.7 Block Status Register ............ 3-417
CONTENTS
PAGE
5.0 ELECTRICAL SPECIFICATIONS ..
5,1 Absolute Maximum Ratings ......
5.2 Capacitance .....................
5.3 Timing Nomenclature ............
5.4 DC Characteristics ...............
5.5 DC Characteristics ...............
3-418
3-418
3-419
3-420
3-422
3-424
5.6 AC Characteristics-Read Only
Operations ........................ 3-426
5.7 Power-Up and Reset Timings .... 3-430
5.S AC Characteristics for WE#Controlled Command Write
Operations ........................ 3-431
5.9 AC Characteristics for CE#Controlled Command Write
Operations ........................ 3-434
5.10 AC Characteristics for WE # Controlled Page Buffer Write
Operations ........................ 3-437
5.11 Erase and Word/Byte Write
Performance, Cycling Performance
and Suspend Latency ............. 3-439
6.0 MECHANICAL SPECIFICATIONS .. 3-441
DEVICE NOMENCLATURE/ORDERING
INFORMATION ..................... 3-442
ADDITIONAL INFORMATION ......... 3-442
DATASHEET REVISION HiSTORy .... 3-442
3-404
I
28F016SA
1.0 INTRODUCTION
The documentation of the Intel 2SF016SA memory ,
device includes this datasheet, a detailed user's
manual, a number of application notes, all of which
are referenced at the end of this datasheet.
The datasheet is intended to give an overview of the
chip feature-set and of the operating AC/DC specifications. The 2SF016SA User's Manual provides
complete descriptions of the user modes, system interface examples and detailed descriptions of all
principles of operation. It also contains the full list of
software algorithm flowcharts, and a brief section on
compatibility with the Intel 2SFOOSSA.
1.1 Product Overview
The 2SF016SA is a high-performance, 16-Mbit
(16,777,216-bit) block erasable non-volatile random
access memory organized as either 1 MWord x 16 or
2 MByte x S. The 2SF016SA includes thirty-two
64-KB (65,536) blocks or thirty-two 32-K'A' (32,76S)
blocks. A chip memory map ,is shown in Figure 3.
The implementation of a new architecture, with
many enhanced features, will improve the device operating characteristics and results in greater product
reliability and ease of use.
Among the significant enhancements
2SF016SA:
.3.3V Low Power Capability
on
the
• Improved Write Performance
• Dedicated Block Write/Erase Protection
A 3/5# input pin reconfigures the device internally
for optimized 3.3V or 5.0V read/write operation.
The 2SF016SA will be available in a 56-lead, 1.S mm
thick, 16 mm x 23.7mm SSOP package. This form
factor and pinout allow for very high board layout
densities.
A Command User Interface (CUI) serves as the system interface between the microprocessor or microcontroller and the internal memory operation.
A Superset of commands have
basic 2SFOOSSA command-set
write performance and provide
ties. These new commands and
been added to the
to achieve higher
additional capabilifeatures include:
• Page Buffer Writes to Flash
• Command Queuing Capability
• Automatic Data Writes during Erase
• Software Locking of Memory Blocks
• Two-Byte Successive Writes in S-Bit Systems
• Erase All Unlocked Blocks
Writing of memory data is performed in either byte or
word increments typically within 6 /Ls, a 33% improvement over the 2SFOOSSA. A Block Erase operation erases one of the 32 blocks in typically 0.6 sec,
independent of the other blocks, which is about 65%
improvement over the 2SFOOSSA.
Each block can be written and erased a minimum of
100,000 cycles. Systems can achieve typically 1 million Block Erase Cycles by providing graceful block
retirement. This technique has already been employed in Hard Disk Drive designs. Additionally, wear
leveling of block erase cycles can be used to minimize the write/erase time differences across blocks.
The 2SF016SA incorporates two Page Buffers of
256 bytes (12S words) each to allow page data
writes. This feature can improve a system write performance by up to 4 times over previous flash memory devices.
All operations are started by a sequence of Write
commands to the device. Three· Status Registers
(described in detail later) and a RY IBY # output pin
provide information on the progress of the requested
operation.
While the 2SFOOSSA requires an operation to complete before the next operation can be. requested,
the 2SF016SA allows queuing of the next operation
while the memory executes the current operation.
This eliminates system overhead when writing several bytes in a row to the array or erasing several
blocks at the same time. The 2SF016SA can also
perform write operations to one block of memory
while performing Erase of another block.
Internal Algorithm Automation allows Byte/Word
Writes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the 2SFOOSSA S-Mbit FlashFile
memory.
3-405
28F016SA
The 28F016SA provides user-selectable block locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S or
Application Code. Each block has an associated
non-volatile lock-bit which determines the lock
status of the block. In addition, the 28F016SA has a
master Write Protect pin (WP#) which prevents any
modifications to memory blocks whose lock-bits are
set.
The 28F016SA contains three types of Status Registers to accomplish various functions:
• A Compatible Status Register (CSR) which is
100% compatible with the 28F008SA FlashFile
memory's Status Register. This register, when
used alone, provides a straightforward upgrade
capability to the 28F016SA from. a 28F008SAbased design.
• A Global Status Register (GSR) which informs
the system of command Queue status, Page
Buffer status, and overall Write State Machine
(WSM) status.
• 32 Block Status Registers (BSRs) which provide
block-specific status information such as the
block lock-bit status.
The GSR and BSR memory maps for Byte-Wide and
Word-Wide modes are shown in Figures 4a and 4b.
The 28F016SA incorporates an open drain RYIBY #
output pin. This feature allows the user to OR-tie
many RYIBY # pins together in a multiple memory
configuration such as a Resident Flash Array.
Other configurations of the RYIBY # pin are enabled via special CUI commands and are described
in detail in the 28F016SA User's Manual.
The 28F016SA also incorporates a dual chip-enable
function with two input pins, CEo# and CE1 #.
These pins have exactly the same functionality as
the regular chip-enable pin, CE#, on the 28F008SA.
For minimum chip deSigns, CE1 # may be tied to
ground and use CEo# as the chip enable input. The
28F016SA uses the logical combination of these two
Signals to e[lable or disable the entire chip. Both
CEo # and CE1 # must be active low to enable the
device and if either one becomes inactive, the chip
will be disabled. This feature, along with the open
drain RYIBY # pin, allows the system designer to
reduce the number of control pins used in a large
array of 16-Mbit devices.
3-406
The BYTE # pin allows either x8 or x16 readlwrites
to the 28F016SA. BYTE# at logic low selects 8-bit
mode with address Ao selecting between low byte
and high byte. On the other hand, BYTE# at logic
high enables 16-bit operation with address A1 becoming the lowest order address and address Ao is
not used (don't care). A device block diagram is
shown in Figure 1.
The 28F016SA is specified for a maximum access
time of 100 ns (tACC) at 5.0V. operation (4.5V to
5.5V) over the extended temperature range (- 45'C
to + 85'C). A corresponding maximum acesss time
of 150 ns at 3.3V (3.0V to 3.6V and -45'C to
+ 85'C) is achieved for reduced power consumption
applications.
The 28F016SA incorporates an Automatic Power
Saving (APS) feature which substantially reduces
the active current when the device is in static mode
of operation (addresses not switching).
In APS mode, the typical Icc current is 1 mA at 5.0V
(0.8 mA at 3.3V).
A Deep Power-Down mode of operation is invoked
when the RP# (called PWD on the 28F008SA) pin
transitions low. This mode brings the device power
consumption to less than 3.0 p.A, typically, and pro- .
vides additional write protection by acting as a device reset pin during power transitions. A reset time
of 550 ns is required from RP#'switching high until
outputs are again valid. In the Deep Power-Down
state; the WSM is reset (any current operation will
abort) and the CSR, GSR and BSR registers are
cleared.
A CMOS Standby mode of operation is enabled
when either CEo# or CE1 # transitions high and
RP# stays high with all input control pins at CMOS
levels. In this mode the device typically draws an Icc
'standby current of 70 p.A.
2.0· DEVICE PINOUT
The 28F016SA 56l SSOP pinout configuration is
shown in Figure 2.
28F016SA
"
N
I
'""
r.;::=::t.:::::1~ vpp
3/5#
290541-2
Figure 1. 28F016SA Block Diagram Architectural Evolution Includes Page
Buffers, Queue Registers and Extended Status Registers
3·407
28F016SA
2.1 Lead Descriptions
Symbol
Type
Name and Function
Ao
INPUT
BYTE·SELECT ADDRESS: Selects between high and low byte when
device is ir.1 x8 mode. This address is latched in x8 Data Writes. Not used in
x16 mode (i.e., the Ao input buffer is turned off when BYTE # is high).
Al-A15
INPUT
WORD-SELECT ADDRESSES: Select a word within one 64-KByte block.
AS-15 selects 1 of 1024 rows, and Al-15 selects 16 of 512 columns. These
addresses are latched during Data Writes.
A1S-A20
INPUT
BLOCK-SELECT ADDRESSES: Select 1 of 32 Erase block. These
addresses are latched during Data Writes, Erase and Lock-Block
operations.
DQo-DQ7
INPUT/
OUTPUT
LOW-BYTE DATA BUS: Inputs data and commands during CUI write
cycles. Outputs array, buffer, identifier or status data in the appropriate
Read mode. Floated when the chip is de-selected or the outputs are
disabled.
DQ8-DQ15
INPUT/
OUTPUT
HIGH-BYTE DATA BUS: Inputs data during x16 Data-Write operations.
Outputs array, buffer or identifier data in the appropriate Read mode; not
used for Status Register reads. Floated when the chip is de-selected or the
outputs are disabled.
CEo#,CE1#
I~PUT
CHIP ENABLE INPUTS: Activate the device'scontrollogic, input buffers,
decoders and sense amplifiers. With either CEo# or CEl # high, the device
is de-selected and power consumption reduces to Standby levels upon
completion of any current Data-Write or Erase operations. Both CEo# and
CEl # must be low to select the device.
All timing specifications are the same for both signals. Device Selection
occurs with the latter falling edge of CEo# or CEl #. The first rising edge of
CEo# or CEl # disables the device.
RP#
INPUT
RESET/POWER-DOWN: RP# low places the device in a Deep Power-
Dow., state. All circuits that static power, even those circuits enabled in
standby mode, are turned off. When returning from Deep Power-Down, a
recovery time of 400 ns is required to allow these circuits to power-up.
When RP# goes low, any current or pending WSM operation(s) are
terminated, and the device is reset. All Status Registers return to ready
(with all status flags cleared).
OE#
INPUT
OUTPUT ENABLE: Gates device data through the output buffers when low.
The outputs float to tri-state off when OE # is high.
NOTE:
CEx# overrides OE#, and OE# overrides WE#.
WE#
INPUT
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue
Registers and Address Queue Latches. WE# is active low, and latches
both address and data (command or array) on its rising edge.
RY/BY#
3-408
OPEN DRAIN
OUTPUT
READY IBUSY: Indicates status of the internal WSM. When low, it indicates
that the WSM is busy performing an operation. RY/BY # high indicates that
the WSM is ready for new operations (or WSM has completed all pending
operations), or Erase is Suspended, or the device is in deep power-down
mode. This output is always active (i.e., not floated to tri-state off when
OE# or CEo#, CEl # are high), except if a RY /BY # Pin Disable command
is issued.
28F016SA
2.1
Lead Descriptions
Symbol
(Continued)
Type
Name and Function
WP#
INPUT
WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for
each block. When WP # is low, those locked blocks as reflected by the Block-Lock
Status bits (BSR.6), are protected from inadvertent Data Writes or Erases. When
WP# is high, all blocks can be Written or Erased regardless of the state of the lockbits. The WP# input buffer is disabled when RP# transitions low (deep power-down
mode).
BYTE #
INPUT
BYTE ENABLE: BYTE# low places device in xB mode. All data is then input or output
on 000-7, and DOB_15 float. Address Ao selects between the high and low byte.
BYTE # high places the device in x16 mode, and turns off the Ao input buffer. Address
A1 then becomes the lowest order address.
3/5#
INPUT
3.3/5.0 VOLT SELECT: 3/5# high configures internal circuits for 3.3Voperation.
3/5# low configures internal circuits for 5.0V operation.
NOTES:
Reading thearray with 3/5# high in a 5.0V system could damage the device.
There is a significant delay from 3/5# switching to valid data.
Vpp
SUPPLY
ERASE/WRITE POWER SUPPLY: For erasing memory array blocks or writing words/
bytes/pages into the flash array
Vee
SUPPLY
DEVICE POWER SUPPLY (3.3V
floating.
GND
SUPPLY
GROUND FOR ALL INTERNAL CIRCUITRY: Do not leave any ground pins floating.
NC
± 0.3V,5.0V ± O.SV): Don't leave any power pins
NO CONNECT: No internal connection to die, lead may be driven or left floating.
28F016SV
CEO#
AI2
AI3
A 14
AIS
28F016SV
o
Vpp
Rip,
A11
A10
@
CE1#
NC
A20
AI9
AlB
AI7
AI6
Vee
GND
006
DQ14
007
0015
RY /SY#
OE'
AI
DT28FO 16SA
56-LEAD SSOP
STANDARD PINOUT
1.8mm X 16mm X 23.7mm
TOP VIEW
WE'
WP'
DQ13
DOS
0012
A2
A3
A4
AS
A6
A7
A9
AI
A2
A3
A4
AS
A6
A7
GND
AB
Vee
009
DOl
DaB
000
AD
BYTE#
NC
NC
D02
OQ10
003
D04
0011
Vee
GND
290541-3
NOTE:
.
56-Lead SSOP Mechanical Diagrams and dimensions are shown at the end of this data sheet.
Figure 2. 56-Lead SSOP Pinout Configuration
3-409
28F016SA
3.0
MEMORY MAPS
'FFrrr
'FOOOO
I[rrrr
IEOOOO
lorr.r
100000
lerrrr
lCOOOO
IOFrrr
lBOOOO
IAr.rf
IMOOO
19rrrr
190000
ISFrrr
180000
17rFrF
170000
Isrrrr
160000
ISHrr
150000
14FFrF
140000
13FrFr
130000
12rrrr
120000
IIFFrr
110000
IOFFFF
100000
OFTFrF
oro 000
DEFFFr
DEDOOO
DOFFFF
000000
ocrFrF
oeoooo
OElHrr
090000
DAFrrr
DADOOO
09rrrr
090000
oarrH
080000
07rrrr
070000
OSFrrr
060000
OSFrrr
050000
04F"Frr
040000
OJFrrr
030000
02Hrr
020000
OIFFFF
0,0000
oorFrf
000000
64 KByte Block
31
64 KByte Block
30
64 KByte Block
29
64 KByte Block
28
64KByte Block
27
64 KByte Block
26
64 KByte Block
25
64 KByte Block
24
64 KByte Block
23
64 KByte Block
22
64 KByte Block
21
64 KByte Block
20
64 KByte Block
19
64 KByte Block
18
64 KByte Block
17
64 KByte Block
16
64 KByte Block
15
64 KByte Block
14
64 KByte Block
13
64 KByte Block
12
64 KByte Block
11
64 KByte Block
10
64 KByte Block
9
64 KByte Block
8
64 KByte Block
7
64 KByte Block
6
64 KByte Block
5
64 KByte Block
4
64 KByte Block
3
64 KByte Block
2
64 KByte Block
1
64 KByte Block
0
290541-4
Figure 3. 28F016SA Memory Map (Byte-Wide Mode)
3·410
28F016SA
3.1
Extended Status Registers Memory Map
X8 MODE
X16 MODE
RESERVED
GSR
RESERVED
. BSR31
RESERVED
RESERVED
•
•
•
•
•
•
A[20:0j
A[20: 1]
I F0006H
F8003H
IF0005H
1F0004H
lF0003H
lF0002H
lF0001H
1FOOOOH
o10002H
RESERVED
RESERVED
GSR
RESERVED
BSRO
RESERVED
RESERVED
RESERVED
GSR
F8002H
RESERVED
BSR31
F800 1H
RESERVED
RESERVED
•
•
•
•
•
•
F8000H
08001H
RESERVED
000006H
000005H
000004H
000003H
000002H
000001H
OOOOOOH
290541-17
Figure 4a. Extended Status Register Memory
Map (Byte-Wide Mode)
00003H
RESERVED
GSR
00002H
RESERVED
BSRO
00001H
RESERVED
RESERVED
OOOOOH
290541-18
Figure 4b. Extended Status Register Memory
Map (Word-Wide Mode)
3-411
28F016SA
4.0
BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS
4.1 Bus Operations for Word-Wide Mode (BYTE #
Mode
Notes
RP#
CE1#
VIH
VIL
=
VIH)
CEo#
OE.#
WE#
A1
DQO-15
RY/BY#
VIL
VIL
VIH
X
DOUT
X
HighZ
X
Read
1,2,7
Output Disable
1,6,7
VIH
VIL
VIL
VIH
VIH
X
Standby
1,6,7
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
HighZ
X
1,3
VIL
X
X
X
X
X
HighZ
VOH
Manufacturer ID
4
VIH
VIL
VIL
VIL
VIH
VIL
0089H
VOH
Device ID
4
VIH
VIL
VIL
VIL
VIH
VIH
66AOH
VOH
1,5,6
VIH
VIL
VIL
VIH
VIL
X
DIN
X
DQO-7
RY/BY#
Deep Power-Down
Write
4.2 Bus Operations for Byte-Wide Mode (BYTE #
Mode
= V,d
Notes
RP#
CE1#
CEo#
OE#
WE#
Ao
VIH
VIL
VIL
VIL
VIH
X
DOUT
X
HighZ
X
Read
1,2,7
Output Disable
1,6,7
VIH
VIL
VIL
VIH
VIH
X
Standby
1,6,7
VIH
VIL
VIH
VIH
VIH
VIL
VIH
X
X
X
HighZ
X
1,3
VIL
X
X
X
X
X
HighZ
VOH
4
VIH
VIL
VIL
VIL
VIH
VIL
89H
VOH
4
VIH
VIL
VIL
VIL
VIH
VIH
AOH
VOH
1,5,6
VIH
VIL
VIL
VIH
VIL
X
DIN
X
Deep Power-Down
Manufacturer ID
Device ID
Write
NOTES:
1. X can be VIH or VIL for address or control pins except for RY/BY#, which is either VOL or VOH.
2. RY/BY# output is open drain. When the WSM is ready, Erase is suspended or the device is in deep power-down mode,
RY/BY# will be at VOH if it is tied to Vee through a resistor. RY/BY#. at VOH is independent of OE# while a WSM
operation is in progress.
3. RP# at GND ± O.2V ensures the lowest deep power-down current.
4. Ao and A1 at VIL provide device manufacturer ID codes in x8 and x16 modes respectively.
Ao and A1 at VIH provide device ID codes in x8 and x16 modes respectively. All other addresses are set to zero.
5. Commands for different Erase operations, Data Write operations or Lock-Block operations can only be successfully
completed when Vpp = VPPH.
6. While the WSM is running, RY IBY # in Level:Mode (default) stays at VOL until all operations are complete. RY IBY #
goes to VOH when the WSM is not busy or in erase suspend mode.
7. RY/BY# may be at VOL while the WSM is busy performing various operations. For example, a Status Register read
during a Write operation.
3-412
28F016SA
4.3 28F008SA-Compatible Mode Command Bus Definitions
Command
Notes
Read Array
Intelligent Identifier
1
First Bus Cycle
Second Bus Cycle
Oper
Addr
Data
FFH
Read
AA
AD
90H
Read
IA
ID
Read
X
CSRD
WD
Oper
Addr
Data
Write
X
Write
X
Read Compatible Status Register
2
Write
X
70H
Clear Status Register
3
Write
X
50H
Word/Byte Write
Write
X
40H
Write
WA
Alternate Word/Byte Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
BA
DOH
Erase Suspend/Resume
Write
X
BOH
Write
X
DOH
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don't Care
DATA
AD = Array Data
CSRD = CSR Data
ID = Identifier Data
WD = Write Data
NOTES:
1. Following the Intelligent Identifier command, two Read operations access the manufacturer and device signature codes.
2. The GSR is automatically available after device enters Data Write, Erase, or Suspend operations.
3. Glears GSR.3, GSR.4 and GSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits.
See Status Register definitions.
3-413
28F016SA
4.4 28F016SA-Performance Enhancement Command Bus Definitions
Command
Mode
Notes
First Bus Cycle
Second Bus Cycle
Oper Addr Data Oper Addr
Read Extended
Status Register
1
Write
X
71H
Page Buffer Swap
7
Write
X
72H
Read
RA
Data
Third Bus Cycle
Oper Addr
Data
GSRD
BSRD
Read Page Buffer
Write
X
75H
Read
PA
PD
Single Load to
Page Buffer
Write
X
74H
Write
PA
PD
Write
X
EOH
Write
X
BCL
x16
4,5,6,10 Write
X
EOH
Write
X
WCL
Write
X
WCH
xS
3,4,9,10 Write
X
OCH
Write
Ao
BC(L,H)
Write
WA
BC(H,L)
WCL
Write
WA
WCH
WD(L,H) Write
WA
WD(H,L)
Sequential Load
to Page Buffer
Page Buffer
Write to Flash
x8
4,6,10
x16
4,5,10
Write
X
OCH
Write
X
x8
3
Write
X
FBH
Write
Ao
Write
X
77H
Write
BA
DOH
2
Write
X
97H
Write
X
DOH
Upload Device
Information
Write
X
99H
Write
X
DOH
Erase All Unlocked
Blocks/Confirm
Write
X
A7H
Write
X
DOH
Two-Byte Write
Lock Block/Confirm
Upload Status
Bits/Confirm
RY /BY # Enable
to Level-Mode
8
Write
X
96H
Write
X
DOH
RY /BY # PulseOn-Write
8
Write
X
96H
Write
X
02H
RY /BY # PulseOn-Erase
8
Write
X
96H
Write
X
03H
RY /BY # Disable
8
Write
X
96H
Write
X
04H
Sleep
Write
X
FOH
Abort
Write
X
SOH
ADDRESS
BA = Block Address
PA = Page Buffer Address
RA = Extended Register Address
WA = Write Address
X = Don't Care
3-414
DATA
AD = Array Data
PD = Page Buffer Data
BSRD = BSR Data
GSRD = GSR Data
Write
X
BCH
WC (L,H) = Word Count (Low, High)
BC (L,H) = Byte Count (Low, High)
WD (L,H) = Write Data (Low, High)
28F016SA
NOTES:
1. RA can be the GSR address or any BSR address. See Figures 4a and 4b for Extended Status Register Memory Maps.
2. Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
3. Ao is automatically complemented to load second byte of data. BYTE# must be at VIL.
Ao value determines which WD/BC is supplied first: Ao = 0 looks at the WDl/BCl, Ao = 1 looks at the WDH/BCH.
4. BCH/WCH must be at OOH for this product because of the 256-byte (12B-word) Page Buffer size, and to avoid writing the
Page Buffer contents to more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.
5. In x16 mode, only the lower byte DOO-7 is used for WCl and WCH. The upper byte D08-15 is a don't care.
6. PA and PD (whose count is given in cycles 2 and 3) are supplied starting in the 4th cycle, which is not shown.
7. This command allows the user to swap between available Page Buffers (0 or 1).
B. These commands reconfigure RY IBY # output to one of two pulse-modes or enable and disable the RY IBY # function.
9. Write address, WA, is the Destination address in the flash array which must match the Source address in the Page
Buffer. Refer to the 2BF016SA User's Manual.
10. BCl = OOH corresponds to a Byte count of 1. Similarly, WCl = OOH corresponds to a Word count of 1.
4.5 Compatible Status Register
I
WSMS
?
lESS
I
6
ES
I
5
DWS
VPPS
R
4
3
2
R
R
o
NOTES:
CSR.?
=
WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
RY /BY # output or WSMS bit must be checked to determine
completion of an operation (Erase Suspend, Erase, or Data
Write) before the appropriate Status bit (ESS, ES or DWS) is
checked for success.
CSR.6 = ERASE-SUSPEND STATUS
1 = Erase Suspended
= Erase In Progress/Completed
o
= ERASE STATUS
Error In Block Erasure
= Successful Block Erase
CSR.5
1
o
=
CSR.4
=
o=
1
If DWS and ES are set to "1" during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
= DATA-WRITE STATUS
Error in Data Write
Data Write Successful
CSR.3 = Vpp STATUS
1 = Vpp Low Detect, Operation Abort
0= Vpp OK
The VPPS bit, unlike an AID converter, does not provide
continuous indication of Vpp level. The WSM interrogates
Vpp's level only after the Data-Write or Erase command
sequences have been entered, and informs the system if
Vpp has not been switched on. VPPS is not guaranteed to
report accurate feedback between VPPl and VpPH.
CSA.2-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the CSA.
3-415
28F016SA
4.6 Global Status Register
I
WSMS
7
I
055
6
I
DOS
DSS
QS
PBAS
5
4
3
2
GsR.7 = WRITE STATE MACHINE STATUS
1 = Ready
o = Busy
PBS
PBSS
o
NOTES:
1. RY /BY # output or WSMs bit must be checked to
determine completion of an operation (Block Lock,
Suspend, any RY IBY # reconfiguration, Upload Status
Bits, Erase or Data Write) before the appropriate Status
bit (055 or DOS) is checked for success.
GSR.6 = OPERATION SUSPEND STATUS
1 = Operation Suspended
0= Operation in Progress/Completed
GSR.5 = DEVICE OPERATION STATUS
1 = Operation Unsuccessful
o = Operation Successful or Currently
Running
GSR.4 = DEVICE SLEEP STATUS
1 = Device in Sleep
o = Device Not in Sleep
MATRIX 5/4
o 0 = Operation Successful or Currently
Running
o 1 = Device in Sleep mode or Pending
Sleep
1 0 = Operation Unsuccessful
1 1 = Operation Unsuccessful or
Aborted
If operation currently running, then GsR.7 = O.
If del(ice pending sleep, then GsR.7 = O.
Operation aborted: Unsuccessful due to Abort
'
command.
GSR.3 = QUEUE STATUS
1 = Queue Full
o = Queue Available
GsR.2 = PAGE BUFFER AVAILABLE STATUS
1 = One or Two Page Buffers Available
o = No Page Buffer Available
The device contains two Page Buffers.
GsR.1 = PAGE BUFFER STATUS
1 = Selected Page Buffer Ready
o = Selected Page Buffer Busy
Selected Page Buffer is currently busy with WsM
operation.
GsR.O = PAGE BUFFER SELECT STATUS
1 = Page Buffer 1 Selected
o = Page Buffer 0 Selected
NOTE:
1. When multiple operations are queued, checking BSR.? only provides indication of completion for that particular block.
GSR.? provides indication when all queued operations are completed.
3-416
28F016SA
4.7 Block Status Register
I
Bs
7
I
BLs
I
6
BOs
BOAS
Qs
VPPs
5
4
3
2
VPPL
R
o
NOTES:
BsR.7 = BLOCK STATUS
1 = Ready
0= Busy
1. RY /BY # output or Bs bit must be checked to
determine completion of an operation (Block Lock,
Suspend; Erase or Data Write) before the appropriate
Status bits (BOs, BLs) is checked for success.
BsR.6 = BLOCK-LOCK STATUS
1 = Block Unlocked for Write/Erase
o = Block Locked for Write/Erase
BsA.5 = BLOCK OPERATION STATUS
1 = Operation Unsuccessful
o = Operation Successful or Currently Running
BsA.4 = BLOCK OPERATION ABORT STATUS
1 = Operation Aborted
o = Operation Not Aborted
MATRIX 5/4
0 = Operation Successful or
Currently Running
o 1 = Not a Valid Combination
1 0 = Operation Unsuccessful
1 1 = Operation Aborted
The BOAS bit will not be set until BsA. 7
= 1.
o
Operation halted via Abort Command.
BsA.3 = QUEUE STATUS
1 = Queue Full
o = Queue Available
BSA.2 = Vpp STATUS
1 = Vpp Low Detect, Operation Abort
0= VppOK
NOTE:
BSR.1-0 = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use; mask them out when polling the BSRs.
1. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block.
GSR.7 provides indication when all queued operations are completed.
3-417
28F016SA
5.0
ELECTRICAL SPECIFICATIONS
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.
5.1 Absolute Maximum Ratings*
+ 8S·C
+ 12S·C
Temperature under Bias ......... - 40·C to
Storage Temperature ....•..... - 6S·C to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may· cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
EXTENDED TEMPERATURE OPERATING CONDITIONS
Vee = 3.3V ± 0.3V Systems
Symbol
Parameter
TA
Operating Temperature,
Extended Temperature
Vee
Vee with Respect to GND
Vpp
Vpp Supply Voltage with
Respect to GND
V
Voltage on any Pin (except Vee, Vpp)
with Respect to GND
I
Current into any Non-Supply Pin
lOUT
Output Short Circuit Current
Notes
Min
Max
Units
Test Conditions
1
-40
85
·C
Ambient Temperature
2
-0.2
7.0
V
2,3
-0.2
14.0
V
2
-0.5
Vee
4
+ 0.5
V
±30
rnA
100
rnA
Vee = S.OV ± O.SV Systems
Notes
Min
Max
Units
Test Conditions
TA
Operating Temperature,
Extended Temperature
1
-40
85
·C
Ambient Temperature
Vee
Vee with Respect to GND
2
-0.2
7.0
V
Vpp
Vpp Supply Voltage with Respect to GND
2,3
-0.2
14.0
V
V
Voltage on any Pin (except Vee, Vpp)
with Respect to GND
2
-2.0
7.0
V
I
Current into any Non-Supply Pin
±30
rnA
lOUT
Output Short Circuit Current
100
rnA
Symbol
Parameter
4
NOTES:
1. Operating temperature is for extended temperature product defined by this specification.
2. Minimum De voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee +
2.0V for periods < 20 ns:
3. Maximum De voltage on Vpp may overshoot to + 14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
3-418
28F016SA
5.2 Capacitance
For a 3.3V ± 0.3V System:
Symbol
Parameter
Notes
Typ
Max
Units
Test Conditions
CIN
Capacitance Looking into an
Address/Control Pin
1
6
B
pF
TA = 25°C, f = 1.0 MHz
COUT
Capacitance Looking into an
Output Pin
1
B
12
pF
TA = 25°C, f = 1.0 MHz
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
1
50
pF
For Vee = 3.3V ± 0.3V
2.5
ns
Equivalent Load Timing Circuit
50.0. Transmission
. Line Delay
For 5.0V ± 0.5V System:
Symbol
Parameter
CIN
Capacitance Looking into
an Address/Control Pin
COUT
Capacitance Looking
into an Output Pin
CLOAD
Load Capacitance Driven by
Outputs for Timing Specifications
Equivalent Testing Load Circuit
Notes
Typ
Max
Units
Test Conditions
1
6
B
pF
TA= 25°C, f = 1,0 MHz
.1
B
12
pF
TA= 25'C, f = 1.0 MHz
100
pF
For Vee = 5.0V ±0.5V
2.5
ns
25.0. Transmission
Line Delay
1
NOTE:
1. Sampled, not 100% tested.
3-419
28F016SA
5.3 Timing Nomenclature
All 3.3V system timings are measured from where signals cross 1.5V.
For 5.0V systems use the standard JEDEC cross point definitions.
Each timing parameter consists of 5 characters. Some common examples are defined below:
teE
tELQV time(t) from CE # (E) going low (L) to the outputs (Q) becoming valid (V)
tOE
tGLQV time(t) from OE# (G) going low (L) to the outputs (Q) becoming valid (V)
tAVQV time(t) from address (A) valid (V) to the outputs (Q) becoming valid (V)
tAVWH time(t) from address (A) valid (V) to WE# (W) going high (H)
tWHDX time(t) from WE # (W) going high (H) to when the data (D) can become undefined (X)
Pin Characters
3-420
Pin States
A
Address Inputs
H
High
0
Data Inputs
L
Low
Q
Data Outputs
V
Valid
E
CE # (Chip Enable)
X
Driven, but Not Necessarily Valid
Z
High Impedance
F
BYTE # (Byte Enable)
G
OE# (Output Enable)
W
WE# (Write Enable)
P
RP# (Deep Power-Down Pin)
R
RY IBY # (Ready Busy)
V
Any Volltage Level
Y
3/5# Pin (28F016SA Only)
5V
Vee at 4.5V Minimum
3V
Vee at 3.0V Minimum
28F016SA
X:: >
2.4 _ _I_NP_U_T_J
0.45
TBT POINTS
~
<:
2.0
,OUTPUT
0.8
290541-5
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at
VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends, at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
Figure 5. Transient Input/Output Reference Waveform (Vee = 5.0V ± 10%)
::: __I_NP_U_T_JX.S
+---T~T
POINTS---+
1.5
OUTPUT
290541-6
AC test inputs are driven at 3.0V for a Logic "1" and O.OV for a Logic "0." Input timing begins, and output timing ends, at
1.5V. Input rise and fall times (10% to 90%) <10 ns.
Figure 6. Transient Input/Output Reference Waveform (Vee
=
3.3V ± 0.3V)
2.5 ns of 25n Transmission Line
• From Output
Under Test
Test
Point •
( )
290541-7
Total Capacitance = 100 pF
Figure 7. Transient Equivalent Testing Load Circuit (Vee
1)
=
5.0V ± 10%)
2.5 ns of son Transmission Line
• From Output
Under Test
()
Test
Point •
290541-8
Total Capacitance
= 50 pF
Figure 8. Transient Equivalent Testing Load Circuit (Vee = 3.3V ± 0.3V)
3-421
28F016SA
5.4 DC Characteristics: EXTENDED TEMPERATURE OPERATION
Vee = 3.3V ± 0.3V, TA = -40·C to +85·C
Symbol
Max
Units
III
Input Load Current
Parameter
Notes
1
±1
p.A
Vee = Vee Max,
VIN = Vee or GND
ILO
Output Leakage Current
1
±10
p.A
Vee = Vee Max,
VIN = Vee or GND
Ices
Vee Standby
Current
250
p.A
Vee = Vee Max,
CEo#, CE1#, RP# = Vee
± 0.2V
BYTE#, WP# = Vee ± 0.2V
orGND ± 0.2V
1,5
Min
Typ
70
"
Test Conditions
1
10
rnA
Vee = Vee Max,
CEo#, CE1 #, RP# = VIH
BYTE#;WP# = VIHorVIL
IceD
Vee Deep PowerDown Current
1
3
35
p.A
RP# = GND ± 0.2V
BYTE# = Vee ± 0.2Vor
GND ± 0.2V
leeR1
Vee Read Current
1,4,5
30
40
rnA
Vee = Vee Max
CMOS: CEo#, CE1 # = GND
± 0.2V
BYTE# = GND ± 0.2Vor
Vee ± 0.2V
Inputs = GND ± 0.2Vor
Vee ± 0.2V
TIL: CEo#, CE1 # VIL,
BYTE# VIL or VIH
INPUTS = VIL or VIH,
f = 6.67 MHz, lOUT == 0 rnA
leeR2
Vee Read Current
1,4,5
15
25
rnA
Vee = Vee Max
CMOS: CEo#, CE1 # = GND
± 0.2V
BYTE# = GND ± 0.2Vor
Vee ± 0.2V
Inputs = GND ± 0.2Vor
Vee ± 0.2V
TIL: CEo#, CE1 # = VIL,
BYTE# = VIL or VIH
INPUTS = VIL or VIH,
f = 4 MHz, lOUT = 0 rnA
3-422
28F016SA
5.4 DC Characteristics: EXTENDED TEMPERATURE OPERATION
Vee = 3.3V ± 0.3V, TA = -40·C to +85·C (Continued)
Symbol
Parameter
Notes
Typ
Max
Units
Test Conditions
lecw
Vee Write Current
1
8
12
mA
Word/Byte Write in Progress
Vpp = 12.0V ± 5%
IeeE
Vee Block Erase
Current
1
6
12
mA
Block Erase in Progress
Vpp = 12.0V ± 5%
leeES
Vee Erase
Suspend Current
1,2
3
6
mA
CEo#, CE1 # = VIH
Block Erase Suspended
IpPS
IpPR
Vpp Standby/Read
Current
1
±1
±10
/LA
Vpp ~ Vee
65
200
/LA
Vpp > Vee
IpPD
Vpp Deep PowerDown Current
1
0.2
5
/LA
RP# = GND ± 0.2V
Ippw
Vpp Write Current
1
10
15
mA
Vpp = 12.0V ± 5%
Word/Byte Write in Progress
IpPE
Vpp Erase Current
1
4
10
mA
Vpp = 12.0V ± 5%
Block Erase in Progress
IpPES
Vpp Erase
Suspend Current
1
65
200
/LA
Vpp = VPPH,
Block Erase Suspended
VIL
' Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
Vee
+0.3
V
VOL
Output Low
Voltage
0.4
V
Vee = Vee Min and
IOL = 4mA
VOH(1)
Output High
Voltage
2.4
V
IOH = -2.0mA
Vee = Vee Min
Vee
-0.2
V
IOH = -100/LA
Vee = Vee Min
VOH(2)
Min
VPPL
Vpp during
Normal Operations
3
0.0
VpPH
Vpp cluring
Write/Erase
Operations
3
11.4
VLKO
Vee Erase/Write
Lockout Voltage
1.5
12.0
6.5
V
12.6
V
•
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 3.3V, VPP '7 12.0V, T = 25°e. These currents
are valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR·
.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when VPP s: VPPL and not guaranteed in the
range between VpPH(min) and VpPL(max). '
4. Automatic Power Savings (APS) reduces ICCR to < 1 mA in static operation.
5. eMOS Inputs are either VCC ± O.2V or GND ± O.2V. TTL Inputs are either VIL or VIH.
3-423
infel®
28F016SA
5.5 DC Characteristics: EXTENDED TEMPERATURE OPERATION
Vee = 5.0V ± 0.5V, TA = -40°C to +85°C
Symbol
Parameter
Notes
Max
Units
III
Input Load Current
1
±1
/LA
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage
Current
1
±10
/LA
Vee = Vee Max
VIN = Vee or GND
lees
Vee Standby
Current
70
250
/LA
Vee= Vee Max
CEo#, CE1#, RP# = Vee ± 0.2V
BYTE#, WP# = Vee ± 0.2V
orGND ± 0.2V
2
10
rnA
Vee = Vee Max
CEo#, CEl #, RP# = VIH
BYTE#, WP# = VIH or VIL
1,5
Min
Typ
' Test Conditions
leeD
Vee Deep PowerDown Current
1
10
60
/LA
RP# = GND ± 0.2V
BYTE# = Vee ± 0.2Vor
GND ± 0.2V
leeR1
Vee Read Current
1,4,5
55
70
rnA
Vee = Vee Max,
CMOS: CEo# ,CEl # == GND ± 0.2V
BYTE# = GND ± 0.2Vor
Vee ± 0.2V
Inputs = GND ± 0.2V
or Vee ± 0.2V
TTL: CEo#, CEl # = VIL,
BYTE# = VILorVIH
Inputs = VIL or VIH,
f = 10 MHz, lOUT = 0 rnA
leeR2
Vee Read Current
1,4,5
30
35
rnA
Vee = Vee Max,
CMOS: CEo#, CEl # = GND ± 0.2V
BYTE# = GND ± O.2Vor
Vee ± 0.2V
Inputs = GND ± O.2Vor
Vee ± 0.2V
TTL: CEo#, CEl # = VIL,
BYTE# = VILorVIH
Inputs = VIL or VIH,
f = 5 MHz, lOUT = 0 rnA
3-424
28F016SA
5.5 DC Characteristics
vee
= 5.0V ± 0.5V, T A = -40°C to + 85°C (Continued)
Symbol
Parameter
Notes
Min
Typ
Max
Units
Test Conditions
leew
Vee Write Current
1
25
35
mA
Word/Byte in Progress
VPP = 12.0V ± 5%
IeeE
Vee Erase
Suspend Current
1
18
25
mA
Block Erase in Progress
Vpp = 12.0V ± 5%
leeES
Vee Block Erase
Current
1,2
5
10
mA
CEo#,CE1# = VIH
Block Erase Suspended
IpPS
IpPR
Vpp Standby/Read
Current
1
±1
± 10
p.A
Vpp::;; Vee
65
200
p.A
Vpp> Vee
IpPD
Vpp Deep PowerDown Current
1
0.2
5
p.A
RP#
Ippw
Vpp Write Current
1
7
12
mA
Vpp = 12.0V ± 5%
Word/Byte Write in Progress
IpPE
Vpp Block Erase
Current
1
5
10
mA
Vpp = 12.0V ± 5%
Block Erase in Progress
IpPES
Vpp Erase
Suspend Current
1
65
200
p.A
Vpp = VPPH, Block
Erase Suspended
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
Vee
+0.5
V
VOL
Output Low
Voltage
0.45
V
Vee = Vee Min
IOL = 5.8 mA
VOH(l)
Output High
Voltage
V
IOH = -2.5 mA
Vee = Vee Min
0.85
Vee
VOH(2)
~
3
0.0
VPP during Normal
Operations
VPPH
VPP during
Write/Erase
Operations
11.4
VLKO
Vee Write/Erase
Lockout Voltage
1.5
GND ± 0.2V
IOH = -100 p.A
Vee = Vee Min
Vee
-0.4
VPPL
=
12.0
6.5
V
12.6
V
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, Vpp = 12.0V, T = 25"C. These currents
are valid for all product versions (package and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases, Word/Byte Writes and Lock Block operations are inhibited when Vpp s VPPL and not guaranteed in the
ranges between VpPH(min), and VpPL(max).
4. Automatic Power Saving (APS) reduces ICCRto <3 mA typical in Static operation.
5. CMOS Inputs are either VCC ± O.2V or GND ± O.2V. TTL Inputs are either VIL or VIH.
3-425
28F016SA
5.6 AC Characteristics-Read Only Operations(1): EXTENDED TEMPERATURE
OPERATION
Vee
=
3.3V ±0.3V, TA
=
-45°C to +85°C
Verslons(5)
Symbol
Parameter
28F016SA-150
Notes
Min
Units
Max
tAvAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE # to Output Delay
tpHQV
RP# High to Output Delay
tGLQV
OE# to Output Delay
tELQX
CE # to Output in Low Z
3,6
tEHQZ
CE# to Output in High Z
3,6
tGLQX
OE # to Output in Low Z
3
tGHQZ
OE# to Output in High Z
tOH
Output Hold from Address, CE # or OE #
Change, Whichever Occurs First
tFLOV
tFHQV
BYTE # to Output Delay
3
150
ns
tFLOZ
BYTE # Low to Output in High Z
3
40
ns
tELFL
tELFH
CE# Low to BYTE# High or Low
3,6
5
ns
150
2,6
2
ns
150
ns
750
ns
50
ns
0
ns
55
0
3
3,6
ns
150
ns
ns
40
0
ns
ns
For Extended Status Register Reads
tAVEL
Adress Setup to CE # Going Low
3,4
0
ns
tAVGL
Adress Setup to DE # Going Low
3,4
0
ns
3·426
28F016SA
5.6 AC Characteristics-Read Only Operation(1): EXTENDED TEMPERATURE
OPERATION (Continued)
Vcc = 5.0V ±0.5V, TA =
-40°C to +85°C
Versions(5)
Symbol
Parameter
28F016SA-100
Notes
tAvAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE # to Output Delay
tpHQV
RP# High to Output Delay
tGLQV
OE # to Output Delay
tELQX
CE # to Output in Low Z
3,6
tEHQZ
CE# to Output in High Z
3,6
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE # to Output in High Z
3
toH
Output Hold from Address, CE # or OE #
Change, Whichever Occurs First
tFLQV
tFHQV
BYTE # to Output Delay
tFLQZ
BYTE # Low to Output in High Z
tELFL
tELFH
CE # Low to BYTE # High or Low
Min
100
2,6
2
3,6
Units
Max
ns
100
ns
100
ns
550
ns
40
ns
ns
0
35
ns
ns
0
35
ns
ns
0
3
100
ns
3
30
ns
3,6
5
ns
For Extended Status Register Reads
tAVEL
Adress Setup to CE # GOing Low
3,4
0
ns
tAVGL
Adress Setup to DE # Going Low
3,4
0
ns
NOTES:
1.
2.
3.
4.
5.
See AC Input/Output Reference Waveforms for timing measurements, Figures 5 and 6.
OE# may be delayed up to tELQV-tGLQV after the falling edge of CE#, without impacting tELQV'
Sampled, not 100% tested.
This timing parameter is used to latch the correct BSR data onto the outputs.
Device speeds are defined as:
100 ns at Vee = 5.0V equivalent to
150 ns at Vee = 3.3V
6. CEx# is defined as the latter of CEo# or CE1 # going low, or the first of CEo# or CE1 # gOing high.
3-427
28F016SA
OUTPUTS ENABLED
Vee POWER-UP
VIH
ADDRESSES (A)
DATA VALID
STANDBY
Vee POWER-DOWN
ADDRESSES STABLE
VIL
M - - - - - - - - IAVAV---------t+I
OEH(G}
VIH
WEH(W}
VOH
HIGH Z
HIGH Z
DATA (D/a)
VOL
M-----IAVQV-----~
S.OV
Vee
GND
M - - - - - - t p H Q V - - - - - - - - - - -..
t'
VIH
RPH (P)
VIL
)
\
290541-9
NOTE:
CEx# is defined as the latter of CEo# or CEl # going low, or the first of CEo# or CE1# going high.
Figure 9, Read Timing Waveforms
3-428
28F016SA
V,H
ADDRESSES (A)
Vil
XXXXXX>a
-----
ADDRESSES STABLE
t AVAV
,
---
tAVf"L:;; trLF'L
~
J
~
\
t AVEL
OE# (G)
---
~
.J
~
t AVGl
trLQv -tAVQV
V,H
\
BYTE" (F)
t GlOY
----
t[LaV
~x
V OH
HIGH Z
tElQX
DATA (DOO-D07)
VOL
VOL
tOH ....
il
. \ \.
t AVOY
V OH
DATA (DOB-D01S)
HIGH Z
~
DATA OUTPUT
~~~)(
DATA
OUTPUT
+
.\ \
II
HIGH Z
t flOZ
t-Ih
~
DATA \
OUTPUT
HIGH Z
J
290541-10
NOTE:
GEx# is defined as the latter of GEo# or GEl # going low, or the first of GEo# or GEl # going high.
Figure 10. BYTE# Timing Waveforms
3-429
28F016SA
5.7 Power-Up and Reset Timings: EXTENDED TEMPERATURE OPERATION
Vee POWER UP
RP#
(p)
t YLPH
t YHPH
3/5#
(y)
-
If
-.
t pLYL
145.0V
4.5V
3.3V
"-
OV
(3V,5V)
J
V
t pL5V
Address
(A)
XXXXXXXXXXXXXXX :XXx.
XXXXxxxxxxm
VALID
(Xx)
.... tAV~
Dota
....
VALID
3.3V OUTPUTS
(a)
VALID
~AVQV
VALID
\.
,
5.0V OUTPUTS
~
t pHQV '
tpHQV
290541-11
Figure 11. Vee Power"Up and RP # Reset Waveforms
Symbol
Parameter
tPLYL
tpYLH
RP # Low to 3/5 # Low (High)
tYLPH
tYHPH
3/5# Low (High) to RP# High
tpL5V
tPL3V
Notes
Min
Max
Unit
0
/LS
1
2
/LS
RP# Low to Vcc at 4.5V Minimum
(to Vcc at 3.0V min or 3.6V max)
2
0
/Ls
tAVQV
Address Valid to Data Valid for Vcc = 5V ± 10%
3
100
ns
tpHQV
RP# High to Data Valid forVcc = 5V ±10%
3
550
ns
NOTES:
CEo#, CE1 # and OE# are switched low after Power-Up.
1. Minimum of 2 /los is required to meet the specified tpHQV times.
2. The power supply may start to switch concurrently with RP# going low.
3. The address access time and RP# high to data valid time are shown for 5V Vee operation. Refer to the AC Characteristics Read Only Operations 3.3V Vee operation and all other speed options.
3-430
28F016SA
5.8
AC Characteristics for WE#-Controlled Command Write Operations(1):
EXTENDED TEMPERATURE OPERATION
Vee = 303V
± 003V,
TA = -40°C to
+ 85°C
Versions
Symbol
Parameter
28F016SA·150
Notes
Min
Typ
Units
Max
tAVAV
Write Cycle Time
tVPWH
Vpp Setup to WE# Going High
3
100
ns
tpHEL
RP# Setup to CE# Going Low
7
480
ns
tELWL
CE# Setup to WE# Going Low
7
10
ns
tAVWH
Address Setup to WE # Going High
2,6
75
ns
tDvWH
Data Setup to WE# Going High
2,6
75
ns
tWLWH
WE # Pulse Width
tWHDX
Data Hold from WE# High
2
tWHAX
Adderss Hold from WE# High
2
tWHEH
CE# Hold from WE# High
7
tWHWL
WE# Pulse Width High
75
ns
tGHWL
Read Recovery before Write
0
ns
tWHRL
WE # High to RY IBY # Going Low
tRHPL
RP# Hold from Valid Status Register (CSR,
GSR, BSR) Data and RY IBY # High
tPHWL
RP# High Recovery to WE# Going Low
tWHGL
Write Recovery before Read
tQVVL
Vpp Hold from Valid Status Register (CSR,
GSR, BSR) Data and RY IBY # High
tWHQV(l)
Duration of WordlByte Write Operation
tWHQV(2)
Duration of Block Erase Operation
150
ns
75
ns
10
ns
10
ns
10
ns
100
3
ns
0
ns
1
f.Ls
120
ns
3
0
f.Ls
4,5
5
4
003
9
(Note 8)
f.Ls
12
sec
3-431
28F016SA
5.8
AC Characteristics for WE#-Controlled Command Write Operations(1):
EXTENDED TEMPERATURE OPERATION (Continued)
Vcc = 5.0V ±0.5V, TA = -40°C to +85°C
28F016SA·100
Versions
Symbol
Parameter
Notes
Min
Typ
Units
Max
tAVAV
Write Cycle Time
100
ns
tVPWH
Vpp Setup to WE# Going High
3
100
ns
tpHEL
RP# Setup to CE# Going Low
7
480
ns
tELWL
CE # Setup to WE # Going Low
7
0
ns
tAVWH
Address Setup to WE # Going High
2,6
50
ns
tDVWH
Data Setup to WE # Going High
2,6
50
ns
tWLWH
WE # Pulse Width
tWHDX
Data Hold from WE # High
50
ns
2
0
ns
tWHAX
Address Hold from WE # High
2
10
ns
tWHEH
CE# Hold from WE# High
7
10
ns
tWHWL
WE # Pulse Width High
50
ns
tGHWL
Read Recovery before Write
0
ns
tWHRL
100
. WE # High to RY IBY # Going Low
tRHPL
RP# Hold from Valid Status Register (CSR,
GSR, BSR) Data and RY IBY # High
tPHWL
RP# High Recovery to WE# Going Low
tWHGL
Write Recovery before Read
taVVL
Vpp Hold from Valid Status Register (CSR,
GSR, BSR) Data and RYIBY # High
tWHQV(1)
Duration of WordlByte Write Operation
tWHQV(2)
Duration of Block Erase Operation
3
0
1
ns
ns
/Ls
,
80
ns
3
0
/Ls
4,5
4.5
4
0.3
6
(Note 8)
/Ls
10
sec
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
Read timings during write and erase are the same as for normal read.
Refer to command definition tables for valid address and data values.
Sampled, not 100% tested.
Write/Erase durations are measured to valid Status Register (CSR) Data.
Word/Byte Write operations are typically performed with 1 Programming Pulse.
Address and Data are latched on the rising edge of WE# for all Command Write operations.
CEx# is defined as the latter of CEo# or CEl # going low, or the first of CEo# or CEl # going high.
This information will be available in a technical paper. Please call Intel's Application Hotline or your local sales office.
3-432
28F016SA
DEEP
WRITE DATA-WRnE OR
POWER-OOWN ERASE SETUP COWt.lANO
6: ~~:!
~;~~~_A:~I~~~SOR
ERASE CONF'IRM COMIIIAND
AUTOWATEO DATA-WRITE
WRITE READ EXTENDED
READ EXTENDED
OR ERASE DELAY
REGISTER COIolWAND
STATUS REGlSTER DATA
V'H~~~~~~~~22~:::A~'N::j~22~~~~~~22~~~(=~=~~)~~~22~~~~
A=-RA
NOT£ 1
ADDRESSES
(A) V 1L
READ COMPATIBLE
STATUS REGISTER DATA
--~-~-----~".!~!------
ADDRESSES (A) VIH
NOTE 2
V"
CE•• eE)
NOTE"
DE. (G)
tWHaVI,2
WE. (w)
V"
DATA (O/Q)
V"
Rr/ay. (R)
,,
,
.. ----------------------
RP. (p)
V pPH2
Vpp (V)
VpPHI
VpPLK
V"
NOTE 7
290541-12
NOTES:
1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
2. This address string depicts Data-Write/Erase cycles with corresponding verification via CSRD.
3. This cycle is invalid when using CSRD for verification during Data Write/Erase operations.
4. CEx# is defined as the latter of CEo# or CE1 # going low or the first of CEo# or CE1 # going high.
5. RP# low transition is only to show tRHPL; not valid for above Read and Write cycles.
Figure 12. AC Waveforms for Command Write Operations
I
3-433
28F016SA
5.9
AC Characteristics for CE#-Controlled Command Write Operations(1):
EXTENDED TEMPERATURE OPERATION
Vee = 3.3V ±0.3V, TA = -40·C +85·C
28F0165A-150
Versions
Symbol
Parameter
Notes
Min
Typ
Units
Max
tAVAV
Write Cycle Time
150
ns
tPHWL
RP# Setup to WE# Going Low
480
ns
tVPEH
Vpp Setup to CE# Going High
3, 7
100
ns
tWLEL
WE # Setup to CE # Going Low
7
0
ns
tAvEH
Address Setup to CE # Going High
2,6,7
75
ns
tDVEH
Data Setup to CE # GOing High
2,6,7
75
ns
tELEH
CE # Pulse Width
7
75
ns
tEHDX
Data Hold from CE# High
2, 7
10
ns
tEHAX
Address Hold from CE # High
2, 7
10
ns
tEHWH
WE # Hold from CE # High
10
ns
tEHEL
CE# Pulse Width High
tGHEL
Read Recovery before Write
tEHRL
CE# High to RY/BY# Going Low
7
tRHPL
RP# Hold fromrValid Status Register (CSR,
GSR, BSR) Data and RYIBY # High
3
0
ns
tpHEL
RP # High Recovery to CE # GOing Low
7
1
f-ts
tEHGL
Write Recovery before Read
120
ns
taVVL
Vpp Hold from Valid Status Register (CSR,
GSR, BSR) Data and RY IBY # High
0
f-ts
tEHQV(1)
Duration of Word/Byte Write Operation
tEHQV(2)
Duration of Block Erase Operation
3·434
7
75
ns
0
ns
100
4,5
5
4
0.3
9
ns
(Note 8)
f-ts
12
sec
28F016SA
5.9
Vcc
AC Characteristics for CE#-Controlled Command Write Operations(1):
EXTENDED TEMPERATURE OPERATION (Continued)
=
5.0V ± 0.5V, TA
=
-40°C +S5°C
Versions
Symbol
Parameter
28F016SA-100
Notes
Min
Typ
Units
Max
tAVAV
Write Cycle Time
100
ns
tPHWL
RP# Setup to CE# Going Low
4S0
ns
tVPEH
Vpp Setup to CE# Going High
3,7
100
ns
tWLEL
WE # Setup to CE # Going Low
7
0
ns
tAVEH
Address Setup to CE# Going High
2,6,7
50
ns
tDVEH
Data Setup to CE# Going High
2,6,7
50
ns
tELEH
CE # Pulse Width
7
50
ns
tEHDX
Data Hold from CE# High
2,7
0
ns
tEHAX
Address Hold from CE# High
2,7
10
ns
tEHWH
WE# Hold from CE# High
10
ns
tEHEL
CE# Pulse Width High
50
ns
tGHEL
Read Recovery before Write
0
ns
tEHRL
CE # High to RY IBY # Going Low
7
tRHPL
RP# Hold from Valid Status Register (CSR,
GSR, BSR) Data and RY IBY # High
3
0
ns
tpHEL
RP # High Recovery to CE # Going Low
7
1
J-Ls
tEHGL
Write Recovery before Read
tQWL
Vpp Hold from Valid Status Register (CSR,
GSR, BSR) Data and RY IBY # High
tEHQV(1)
Duration of WordlByte Write Operation
tEHQV(2)
Duration of Block Erase Operation
7
100
ns
SO
ns
0
J-Ls
4,5
4.5
4
0.3
6
(Note S)
J-Ls
10
sec
NOTES:
1. Read timings during write and erase are the same as for normal read.
2. Refer to command definition tables for valid address and data values.
3. Sampled, not 100% tested.
4. Write/Erase durations are measured to valid Status Data.
5. Word/Byte Write operations are typically performed with 1 Programming Pulse.
6. Address and Data are latched on the rising edge of CE# for all Command Write operations.
7. CEx# is defined as the latter of CEO# or CEl # going low, or the first of CEo# or CEl # going high.
8. This information will be available in a technical paper. Please call Intel's Application Hotline or your local sales office.
3-435
28F016SA
NOTE
1
ADDRESSES
(A)
DEEP
WRITE DATA-WRITE OR
a: ~~:! l~;~~~~~I~~)SOR
AUTOWATED DATA-WRITE
WRITE READ EXTENDED
READ EXTENDED
POWER-DOWN
ERASE SETUP COt.lMAND
ERASE CONfiRM CONMAND
OR ERASE DElAY
REGISTER COMMAND
STATUS REGISTER DATA
VIH1~~~~~~~~C:~A~'"::j<2~~~~~~~~~~~K==:A':R:A==~~~~~~~~~
VIL~
'AVAY
tEHAX
t AVEH
ADORESSES(A)
NOTE 2
vrH~~~~~~~~~~~;'A~IN;:J~~~~~~
VIL~
_____~~:'!
READ COMPATIBLE
STATUS REGISTER DATA
__
__
. _
__
_
WEIJ (w)
0[# (G)
tEHOV1.2
CEx. eE)
NOTE 4
DATA (D!Q)
Rr/BY# CR)
: RPM (P)
".. --- ------ -- ---- ------ ..
V pPH2
VpPHI
Vpp (V)
V pPLK
VIlIl.~QliQQ~~:&i1:&i1~f
NOTE 6
NOTE 7
290541-13
NOTES:
1.
2.
3.
4.
5.
This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD.
This address string depiCts Data-Write/Erase cycles with corresponding verification via CSRD.
This cycle is invalid when using CSRD for verification during Data Write/Erase operations.
CEx# is defined as the latter of CEo# or CEl # going low or the first of CEo# or CEl # going high.
RP# low transition is only to show tRHPL; not valid for above Read and Write cycles.
Figure 13. Alternate AC Waveforms for Command Write Operations
3-436
28F016SA
5.10
AC Characteristics for WE # -Controlled Page Buffer Write Operations(1):
EXTENDED TEMPERATURE OPERATION
Vee = 3.3V ±0.3V, TA = -40°C to +B5°C
28F016SA-150
Versions
Symbol
Parameter
Notes
Min
Typ
Units
Max
150
ns
10
ns
3
0
ns
2
50
ns
tAVAV
Write Cycle Time
tELWL
CE # Setup to WE # Going Low
4
tAVWL
Address Setup to WE# Going Low
tOVWH
Data Setup to WE # Going High
tWLWH
WE # Pulse Width
75
ns
tWHoX
Data Hold from WE # High
2
10
ns
tWHAX
Address Hold from WE# High
2
10
ns
tWHEH
CE # Hold from WE # High
4
10
ns
tWHwL
WE # Pulse Width High
75
ns
tGHWL
Read Recovery before Write
0
ns
tWHGL
Write Recovery before Read
120
ns
3-437
28F016SA
5.10 AC Characteristics for WE#-Controlled Page Buffer Write Operations(1):
EXTENDED TEMPERATURE OPERATION (Continued)
Vcc
=
5.0V ±0.5V, TA
=
-40°C to +85°C
Versions
Symbol
tAVAV
Parameter
28F016SA·100
Notes
Write Cycle Time
Min
Typ
Units
Max
100
ns
tELWL
CE # Setup to WE # Going Low
4
0
ns
tAVWL
Address Setup to WE# Going Low
3
0
ns
tOVWH
Data Setup to WE# Going High
2
50
ns
tWLWH
WE# Pulse Width
50
ns
tWHOX
Data Hold from WE # High
2
0
ns
tWHAX
Address Hold from WE# High
2
10
ns
tWHEH
CE # Hold from WE # High
4
tWHWL
WE# Pulse Width High
10
ns
50
ns
tGHWL
Read Recovery before Write
0
ns
tWHGL
Write Recovery before Read
80
ns
NOTES:
1. These are WE#-controlled write timings, equivalent CE#-controlled write timings apply.
2. Sampled, not 100% tested.
.
3. Address must be valid during the entire WE # low pulse or the entire CE # pulse for CE # -controlled writes.
4. CEx# is defined as the latter of CEo# or CE1 # going low, or the first of CEo# or CE1 # going high.
3-438
28F016SA
tWHEH
CEx#
(E)
WE#
(W)
t WLWH
VALID
ADDRESSES
DATA
t
HIGH Z
~
(D/Q) - - - - - - -....
290541-14
Figure 14. Page Buffer Write Timing Waveforms
(Loading Data to the Page Buffer)
5.11
Erase and word/Blte Write Performance, Cycling Performance and
Suspend Laten~y( ,3): EXTENDED TEMPERATURE OPERATION
vee =
3.3V ± 0.3V, Vpp
Symbol
=
12.0V ± 0.6V, TA
=
Parameter
Notes
Page Buffer Byte Write Time
1,2,4
Page Buffer Word Write Time
1,2,4
-40·C to +85·C
Min
Typ(1)
Max
Units
3.26
Note 6
JLs
6.53
Note 6
JLs
Test Conditions
twHRH(1)
Word/Byte Write Time
1,2
9
Note 6
JLs
tWHRH(2)
Block Write Time
1,2
0.6
2.1
sec
Byte Write Mode
tWHRH(3)
Block Write Time
1,2
0.3
1.0
sec
Byte Write Mode
Block Erase Time
1,2
1.5
12
sec
Full Chip Erase Time
1,2
48
sec
Erase Suspend Latency
Time to Read
7.0
JLs
Erase Suspend Latency
Time to Write
10.0
JLs
1,000,000
Cycles
Erase Cycles
5
100,000
3-439
28F016SA
5.11
Vee
Erase and Word/Byte Write Performance, Cycling Performance and
Suspend Latency('(,3): EXTENDED TEMPERATURE OPERATION (Continued)
=
S:OV
Symbol
± O.SV, vPP = 12.0V ± 0.6V, TA = -40·C to +8S·C
Typ
Max
1,2,4
2.76
Note 6
p.s
1,2,4
S.S1
Note 6
p.s
Parameter
Notes
Page Buffer Byte Write Time
Page Buffer Word Write Time
Min
Units
Test Conditions
tWHRH(1)
Word/Byte Write Time
1,2
6
Note 6
p.s
tWHRH(2)
Block Write Time
1,2
0.4
2.1
sec
Byte Write Mode
tWHRH(3)
Block Write Time
1,2
0.2
1.0
sec
Word Write Mode
Block Erase Time
1,2
1.3
10
sec
Full Chip Erase Time
1,2
41.6
sec
Erase Suspend Latency
Time to Read
S.O
p.s
Erase Suspend Latency
Time to Write
8.0
p.s
1,000,000
Cycles
Erase Cycles
S
100,000
NOTES:
1. 25°C, Vce = 3.3V or 5.0V nominal, 10K cycles.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. This assumes using the full Page Buffer to Write to Flash (256 Bytes or 128 Words).
5. Typical 1,000,000 cycles performance assumes the application uses block retirement techniques.
6. This information will be available in a technical paper. Please call Intel's Application hotline or your local sales office for
more information.
.
3-440
28F016SA
6.0
MECHANICAL SPECIFICATIONS
~/"'
•
~LJ'b
R2
0.111111.
€)
)1
See DeIIIII A ./
290541-15
Figure 15. Mechanical Specifications of the 56·Lead SSOP Package
Family: Shrink Small Outline Package
Millimeters
Symbol
Nominal
1.80
1.90
0.47
0.52
0.57
A
A1
Notes
Minimum
Maximum
A2
1.18
1.28
1.38
B
0.25
0.30
0.20
C
0.13
0.15
0.20
D
23.40
23.70
24.00
E
13.10
13.30
13.50
0.80
e1
He
15.70
N
L1
16.00
16.30
56
0.45
0.50
Y
0.55
- 0.10
a
2°
3°
b
3°
4°
5°
R1
0.15
0.20
0.25
R2
0.15
0.20
0.25
4°
3-441
28F016SA
DEVICE NOMENCLATURE/ORDERING INFORMATION
. DT = EXTENDED
56-LEAD SSOP
ACCESS SPEED
100 ns (5V). 150 ns
290541-16
Valid Combinations
Order Code
Vee
DT28F016SA 100
= 3.3V ±0.3V
DT28F016SA-150·
Vee
= 5.0V ± 10%
DT28F016SA-100
ADDITIONAL INFORMATION
Item
AP-393
AP-377
AP-378
AP-375
AP-357
AP-374
AP-607
ER-33
Order Number
Commercial Temperature 28F016SA 16 Mbit FlashFile
290489
Commercial Temperature 28F016SV SmartVoltage 16 Mbit
290528
28F008SA 8 Mbit FlashFile Memory
290429
28F016SV Compatibility with 28F016SA
28F016SA User's Manual
28F016SA Software Drivers
System Optimization Using the Enhanced Features of the 28F016SA
Upgrade Considerations from the 28F0008SA to the 28F016SA
Power Supply Solutions for Flash Memory
Flash Memory Write Protection Techniques
FLASH Builder Design Resource Utility
Multi-Site Layout Planning with Intel's FlashFile™ Components
Including ROM Capability
Small and Low-Cost Power Supply Solution for Intel's Flash Memory
Products
292144
297372
292126
292127
292124
292092
292123
297508
292159
ETOXTM Flash Memory Technology-Insight to Intel's Fourth
Generation Process Innovation
..
Please check With Intel literature for availability.
DATASHEET REVISION HISTORY
Description
Original Version
3-442
297534
294016
28F008SA
8-MBIT (1-MBIT x 8) FlashFile™ MEMORY
Extended Temperature Specifications Included
•
•
High-Density Symmetrically Blocked
Architecture
- Sixteen 64-Kbyte Blocks
•
•
Automated Byte Write and Block Erase
- Command User Interface
- Status Register
•
Extended Cycling Capability
- 100,000 Block Erase Cycles
- 1.6 Million Block Erase
Cycles per Chip
System Performance Enhancements
- RV /BV # Status Output
- Erase Suspend Capability
Read
• -Very85 High-Performance
ns Maximum Access Time
•
•
•
•
•
SRAM-Compatible Write Interface
Hardware Data Protection Feature
- Erase/Write Lockout during Power
Transitions
Industry Standard Packaging
-40-Lead TSOP, 44-Lead PSOP
ETOX III Nonvolatile Flash Technology
-12V Byte Write/Block Erase
Independent Software Vendor Support
- Microsoft* Flash File System (FFS)
Deep-Powerdown Mode
- 0.20 /LA Icc Typical
Intel's 2SFOOSSA S-Mbit FlashFile™ Memory is the highest density nonvolatile read/write solution for solid
state storage. The 2SFOOSSA's extended cycling, symmetrically blocked architecture, fast access time, write
automation and low power consumption provide a more reliable, lower power, lighter weight and higher performance alternative to traditional rotating disk technology. The 2SFOOSSA brings new capabilities to portable
computing. Application and operating system software stored in resident flash memory arrays provide instanton, rapid execute-in-place and protection from obsolescence through in-system software updates. Resident
software also extends system battery life and increases reliability by reducing disk drive accesses.
For high density data acquisition applications, the 2SFOOSSA offers a more cost-effective and reliable alternative to SRAM and battery. Traditional high density embedded applications, such as telecommunications, can
take advantage of the 2SFOOSSA's nonvolatility, blocking and minimal system code requirements for flexible
firmware and modular software designs.
The 2SFOOSSA is offered in 40-lead TSOP (standard and reverse) and 44-lead PSOP packages. Pin assignments simplify board layout when integrating multiple devices in a flash memory array or subsystem. This
device uses an integrated Command User Interface and state machine for simplified block erasure and byte
write. The 2SFOOSSA memory map consists of 16 separately erasable 64-Kbyte blocks.
Intel's 2SFOOSSA employs advanced CMOS circuitry for systems requiring low power consumption and noise
immunity. Its S5 ns access time provides superior performance when compared with magnetic storage media.
A deep powerdown mode lowers power consumption to 1 /LW typical thru Vee, crucial in portable computing,
handheld instrumentation and other low-power applications. The RP# power control input also provides
absolute data protection during s~§tem powerup/down.
Manufactured on Intel's O.S micron ETOX process, the 2SFOOSSA provides the highest levels of quality,
reliability and cost-effectiveness.
'Microsoft is a trademark of Microsoft Corporation.
November 1994
Order Number: 290429-005
3-443
28F008SA
PRODUCT OVERVIEW
The 28F008SA is a high-performance 8-Mblt
(8,388,608 bit) memory organized as 1 Mbyte
(1,048,576 bytes) of 8 bits each. Sixteen 64~Kbyte
(65,536 byte) blocks are included on the 28F008SA.
A memory map is shown in Figure 6 of this specificaticin. A block erase operation erases one of the sixteen blocks of memory in typically 1.6 seconds, independent of the remaining blocks. Each block can
be independently erased and written 100,000 cycles. Erase Suspend mode allows system software
to suspend block erase to read data or execute
code from any other block of the 28F008SA.
The 28F008SA is available in the 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and 44lead PSOP (Plastic Small Outline) packages. Pinouts are shown in Figures 2 and 4 of this specification.
The Command User Interface serves as the interface between the microprocessor or microcontroller
and the internal operation of the 28F008SA.
.
The Status Register indicates the status of the'
WSM and when the WSM successfully completes
the desired byte write or block erase operation.
The RYIBY # output gives an additional indicator of
WSM activity, providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase,
for example). Status polling using RY IBY # minimizes both CPU overhead and system power consumption. When low, RY IBY # indicates that the
WSM is performing a block erase or byte write operation. RY IBY # high indicates that the WSM is ready
for new commands, block erase is suspended or the
device is in deep powerdown mode.
Maximum access time is 85 ris (tACe) over the commercial temperature range (O·C to + 70°C) and over
Vee supply voltage range (4.5V to 5.5V and 4.75V to
5.25V). Icc active current (CMOS Read) is 20 mA
typical, 35 mA maximum at 8 MHz.
When the CE# and RP# pins are at Vee, the Icc
CMOS Standby mode is enabled.
A Deep Powerdown mode is enabled when the
Byte Write and Block Erase Automation allow
_ RP# pin is at GND, minimizing power consumption
byte write and block erase operations to be executed using a two-write command sequence to the .
and providing write protection. Icc current in deep
powerdown is 0.20 p.A typical. Reset time of 400 ns
Command User Interface. The internal Write State
is required from RP # switching high until outputs are
Machine (WSM) automatically executes the algovalid to read attempts. Equivalently, the device has a
rithms and timings necessary for byte write and
wake time of 1 p.s from RP# high until writes to the
block erase operations, including verifications;
Command User Interface are recognized by the
thereby unburdening the microprocessor or micro28F008SA. With RP# at GND, the WSM is reset
controller. Writing of memory data is performed in
and the Status Register is cleared.
.
byte increments typically within 9 p.s, an 80% improvement over current flash memory products. Ipp
byte write and block erase currents are 10 mA
typical, 30 mA maximum. Vpp byte write and
block erase voltage is 11.4V to 12.6V.
3-444
--
£
"\§)
:w
IiiiiI
IF
000 - O~
~
@
~
~
aeJ
~
"11
c"
c:
...CD
fEj
:""
III
0"
()
'"c
REGISTER
DATA
~
COMMAND
REGISTER
I
Ij
1•
CE#
WE#
OE#
RP#
iii"
~I
" r---Z---,
An -
AI9
_ .
_ _ •• LLL _ _
><
I I
RY /SY#
_
_ _ •••
•• _
•••
L
_~
_
L
_
Vpp
+- Vee
+- GNO
290429-1
I\)
CO
."
o
c.J
.;,..
(J1
"""'
o
CO
en
»
2BFOOBSA
Table 1. Pin Description
Symbol
Ao~A19
Type
INPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
INPUTIOUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during Command
User Interface write cycles; outputs data during memory array, Status
Register and Identifier read cycles. The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled. Data is internally latched during a write cycle.
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers,
decoders, and sense amplifiers. CE # is active low; CE # high deselects
the memory device and reduces power consumption to standby levels.
RP#
INPUT
RESET/DEEP POWERDOWN: Puts the device in deep powerdown
mode. RP# is active low; RP# high gates normal operation. RP# also
locks out block erase or byte write operations when active low, providing
data protection during power transitions. RP# active resets internal
automation. Exit from Deep Powerdown sets device to read-array mode.
OE#
INPUT
OUTPUT ENABLE: Gates the device's outputs through the data buffers
during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command User Interface and
array blocks. WE# is active low. Addresses and data are latched on the
rising edge of the WE# pulse.
OUTPUT
READY/BUSY #: Indicates the status of the internal Write State
Machine. When low, it indicates that the WSM is performing a block
erase or byte write operation. RY IBY # high indicates that the WSM is
ready for new commands, block erase is suspended or the device is in
deep powerdown mode. RY IBY # is always active and does NOT float
to tri-state off when the chip is deselected or data outputs are disabled.
DOo-DO?
RY/BY#
Vpp
BLOCK ERASE/BYTE WRITE POWER SUPPLY for erasing blocks of
the array or writing bytes of each block.
NOTE:
With Vpp < VpPLMAX, memory contents cannot be altered.
Vee
DEVICE POWER SUPPLY (5V
GND
GROUND
3-446
± 10%, 5V ± 5%)
intel®
28FOO8SA
Standard Pinout
A'9
NC
A'8
NC
A'7
WE#
A'6
A,S
OE#
RY/SY#
~4
A'3
A,Z
CE#
STANDARD PINOUT
E28F008SA
40 LEAD TSOP
10mmx20mm
TOP VIEW
Vee
Vpp
RP#
~,
A,O
o~
006
DOs
004
31
Vee
GNO
GNO
003
OOz
A9
DO,
As
000
A7
Ao
As
A,
Az
As
21
A4
A3
290429-2
Reverse Pinout
NC
NC
WE#
~V
0
3
40
A'9
39
A'8
38
A'7
OE#
4
37
RY/SY#
5
36
A'6
A,S
O~
006
35
A'4
7
34
DOs
8
33
~3
~z
32
CE#
31
30
Vee
Vpp
29
RP#
28
004
Vee
10
GND
II
GNO
D03
12
13
REVERSE PINOUT
F28F008SA
40 LEAD TSOP
10 mm X 20 mm
TOP VIEW
DOz
14
27
A"
A,O
DO,
15
26
Ag
DOo
16
25
A8
Ao
17
24
A7
A,
18
23
As
Az
19
22
As
A3
20
21
A4
290429-3
Figure 2. TSOP Lead Configurations
3-447
28F008SA
o
IT1
o
CD
«
en
0
0
CD
0
0
L...
tv
...,
00
en
»
IT1
«
en
tv
CD
...,
00
0
0
L...
0
0
CD
00
N
en
»
L...
«
en
...,
tv
CD
...,
«
en
00
L...
00
N
and
transient peaks produced by falling and rising edges
of CE #. Transient current magnitudes depend on
the device outputs' capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 p,F ceramic capacitor
connected between each VCC and GND, and between its Vpp and GND. These high frequency, low
inherent-inductance capacitors should be placed as
close as possible to package leads. Additionally, for
every 8 devices, a 4.7 p,F electrolytic capacitor
should be placed at the array's power supply connection between Vcc and GND. The bulk capacitor
will overcome voltage slumps caused by PC board
trace inductances.
Vpp Trace on Printed Circuit Boards
Writing flash memories, while they reside in the target system, requires that the printed circuit board
designer pay attention to the Vpp power supply
trace. The Vpp pin supplies the memory cell current
for writing and erasing. Use similar trace widths and
layout considerations given to the VCC power bus.
Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.
3-459
2BFOOBSA
Vee, Vpp, RP# Transitions and the
. Command/Status Registers
Byte write and block erase completion are not guaranteed if Vpp drops below VPPH. If the Vpp Status bit
of the Status Register (SR.3) is set to "1", a Clear
Status Register command MUST be issued before
further byte write/block erase attempts are allowed
by the WSM. Otherwise, the Byte Write (SR.4) or
Erase (SR.5) Status bits of the Status Register will
be set to "1 "s if error is detected. RP# transitions to
VIL during byte write and block erase also abort the
operations. Data is partially altered in either case,
and the command sequence must be repeated after
normal operation is restored. Device poweroff, or
RP# transitions to VIL, clear the Status Register to
initial value 10000 for the upper 5 bits.
The Command User Interface latches commands as
issued by system software and is not altered byVpp
or CE# transitions or WSMactions. Its state upon
powerup, after exit from deep powerdown or after
Vee transitions below VLKO, is Read Array Mode.
After byte write or block erase is complete, eVEln
after Vpp transitions down to VPPL, the Command
User Interface must be reset to Read Array mode via
the Read Array command if access to the memory
.
array is desired.
Power Up/Down Protection
The 28F008SA is designed to offer protection
against accidental block erasure or bYte writing during power transitions. Upon power-up, the
28F008SA is indifferent as to which power supply,
Vpp or Vee, powers up first. Power supply sequenc. ing is not required. Internal circuitry in the 28F008SA
3-460
ensures that the Command User Interface is reset to .
the Read Array mode on power up.
A system designer must guard against spurious
writes for Vee voltages above VLKO when Vpp is
active. Since both WE# and CE# must be low for a
command write, driving either to VIH will inhibit
writes. The Command User Interface architecture
provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences.
Finally, the device is disabled until RP # is brought to
VIH, regardless of the state of its control inputs. This
provides an additional level of memory protection.
Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases usable battery life, because the 28F008SA does not
consume any power to retain code or data when the
system is off.
In addition, the 28F008SA's deep powerdown mode
ensures extremely low power dissipation even when
system power is applied. For example, portable PCs
and other power sensitive applications, using an array of 28F008SAs for solid-state storage, can lower
RP# to VIL in standby or sleep modes, producing
negligable power consumption. If access to the
28F008SA is again needed, the part can again be
read, following the tpHQV and tPHWL wakeup cycles
required after RP# is first raised back to VIH. See
AC Characteristics-Read-Only and Write Operations and Figures 10 and 11 for more information .
28F008SA
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary infor·
mation on new products in production. The specifica·
tions are subject to change without notice. Verify with
your local Intel Sales office that you have the latest
data sheet before finalizing a design.
Operating Temperature
During Read .................. O'C to + 70'C(1)
During Block Erase/Byte Write .... O'C to + 70'C
Storage Temperature .......... - 65'C to
+ ao'c
+ 125'C
Voltage on Any Pin
(except Vee and Vpp)
with Respect to GND ........ - 2.0V to
+ 7.0V(2)
* WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex·
tended exposure beyond the "Operating Conditions"
may affect device reliability.
Temperature Under Bias ......... -1 O'C to
Vpp Program Voltage with
Respect to GND during
Block Erase/Byte Write ... - 2.0V to
+ 14.0V(2, 3)
Vee Supply Voltage
with Respect to GND ........ - 2.0V to
+ 7.0V(2)
Output Short Circuit Current ............. 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vcc + 0.5V which, during transitions, may overshoot to Vee + 2.0V
for periods <20 ns.
3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5.5% Vee specifications reference the 28F008SA·85 in its High Speed configuration. 10% Vee specifications reference the
28F008SA·85 in its Standard configuration, and the 28F008SA·120.
OPERATING CONDITIONS
Symbol
Parameter
Notes
Min
Max
Unit
TA
Operating Temperature
0
70
°C
Vec
Vee Supply Voltage (10%)
5
4.50
5.50
V
Vee
Vee Supply Voltage (5%)
5
4.75
5.25
V
DC CHARACTERISTICS
Symbol
Max
Unit
III
Input Load Current
Parameter
Notes
1
± 1.0
p.A
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage Current
1
±10
p.A
Vee = Vee Max
VOUT = VeeorGND
lees
Vee Standby Current
1.0
2.0
mA
Vee = Vee Max
CE# == RP# = VIH
30
100
p.A
Vee = Vee Max
CE# = RP# = Vee ±0.2V
RP# = GND ±0.2V
lOUT (RY/BY#) = 0 mA
1,3
Min
Typ
leeD
Vee Deep PowerDown
Current
1
0.20
1.2
p.A
leeR
Vee Read Current
1
20
35
mA
Test Condition
Vee Max, CE# = GND
0 mA
CMOS Inputs
Vee
f
25
50
mA
=
=
a MHz, lOUT =
= Vee Max, CE# = VIL
8 MHz, lOUT = 0 mA
TTL Inputs
Vee
f
=
3·461
28F008SA
DC CHARACTERISTICS (Continued)
Symbol
Parameter
leew
Vee Byte Write Current
IeeE
Vee Block Erase Current
leeES
Vee Erase Suspend Current
Ipps
Typ
Max
Unit
1
10
30
mA
Byte Write In Progress
Notes
Min
Test Condition
1
10
30
mA
Block Erase In Progress
1,2
5
10
mA
Block Erase Suspended
CE# = VIH
Vpp Standby Current
1
±1
±15
p,A
Vpp
IpPD
Vpp Deep PowerDown
Current
1
0.10
5.0
p,A
RP#
IpPR
Vpp Read Current
200
p,A
Vpp> Vee
Ippw
Vpp Byte Write Current
1
10
30
mA
Vpp = VPPH
Byte Write in Progress
IpPE
Vpp Block Erase Current
1
10
30
mA
Vpp = VPPH
Block Erase in Progress
IpPES
Vpp Erase Suspend
Current
1
90
200
p,A
Vpp = VPPH
Block Erase Suspended
VIL
Input Low Voltage
0.8
V
-0.5
VIH
Input High Voltage
VOL
Output Low'Voltage
3
2.0
VOH1
Output High Voltage (TTL)
3
VOH2
Output High Voltage
(CMOS)
Vee
+ 0.5
V
Vee = Vee Min
IOL = 5.8 mA
2.4
V
Vee = Vee Min
IOH = -2.5 mA
0.85 Vee
V
IOH = - 2.5 p,A
Vee = Vee Min
VPPL
Vpp during Normal
Operations
VPPH
Vpp during Erase/Write
Operations
11.4
VLKO
Vee Erase/Write Lock
Voltage
2.0
3-462
±0.2V
V
0.45
IOH = -100 p,A
Vee = Vee Min
Vee - 0.4
4
s: Vee
= GND
0.0
12.0
6.5
V
12.6
V
V
28F008SA
EXTENDED TEMPERATURE OPERATING CONDITIONS
Symbol
TA
Parameter
Notes
Operating Temperature
Min
Max
Unit
-40
+85
°C
Vee
Vee Supply Voltage (10%)
5
4.50
5.50
V
Vee
Vee Supply Voltage (5%)
5
4.75
5.25
V
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION
Symbol
Max
Unit
III
Input Load Current
Parameter
Notes
1
±1.0
p.A
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage Current
1
±10
p.A
Vee = Vee Max
VOUT = Vee or GND
lees
Vee Standby Current
1.0
2.0
mA
Vee = Vee Max
CE# = RP# = VIH
30
100
p.A
Vee = Vee Max
CE# = RP# = Vee ±0.2V
1,3
Min
Typ
Test Condition
leeD
Vec Deep PowerDown
Current
1
0.20
20
p.A
RP# = GND ±0.2V
lOUT (RY/BY#) = 0 mA
lecR
Vee Read Current
1
20
35
mA
Vee = Vee Max, CE# = GND
f = 8 MHz, lOUT = 0 mA
CMOS Inputs
25
50
mA
Vee = Vee Max, CE# = VIL
f = 8 MHz, lOUT = 0 mA
TTL Inputs
1
10
30
mA
Byte Write In Progress
1
10
30
mA
Block Erase In Progress
1,2
5
10
mA
Block Erase Suspended
CE# = VIH
leew
Vee Byte Write Current
lecE
Vec Block Erase Current
leeES
Vee Erase Suspend Current
Ipps
Vpp Standby Current
1
. ±1
±15
p.A
Vpp:O; Vee
IpPD
Vpp Deep PowerDown
Current
1
0.10
5.0
p.A
RP#
IpPR
Vpp Read Current
200
p.A
Vpp> Vee
Ippw
Vpp Byte Write Current
1
10
30
mA
Vpp = VpPH
Byte Write in Progress
IpPE
Vpp Block Erase Current
1
10
30
mA
Vpp = VPPH
Block Erase in Progress
IpPES
Vpp Erase Suspend
Current
1
90
200
p.A
Vpp = VPPH
Block Erase Suspended
= GND ±0.2V
3-463
28F008SA
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION (Continued)
Symbol
Parameter
Notes
Min
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
3
VOH1
Output High Voltage
(TIL)
3
VOH2
Output High Voltage
(CMOS)
Typ
Max
Unit
0.8
V
Vee
+ 0.5
V
V
Vee = Vee Min
IOL = 5.8mA
2.4
V
Vee = Vee Min
IOH = -2.5 mA
0.85 Vee
V
IOH = - 2.5 /kA
Vee = Vee Min
0.45
IOH = -100/kA
Vee = Vee Min
Vee - 0.4
VPPL
Vpp during Normal
Operations
VpPH
Vpp during Erase/Write
Operations
11.4
VLKO
Vee Erase/Write Lock
Voltage
2.0
CAPACITANCE(5)
Symbol
4
Test Condition
0.0
12.0
6.5
V
12.6
V
V
TA = 25°C, f = 1 MHz
Typ
Max
Unit
CIN
Input Capacitance
Parameter
6
8
pF
VIN = OV
Condition
COUT
Output Capacitance
8
12
pF
VOUT = OV
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, VPP = 12.0V, T = 25°G. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the 28F008SA is read while in Erase Suspend Mode, current draw is the
sum of ICCES and ICCR.
3. Includes RY /BY "'.
4. Block Erases/Byte Writes are inhibited when Vpp = VPPL and not guaranteed in the range between VpPH and VPPL.
5. Sampled, not 100% tested.
3·464
28F008SA
AC INPUT/OUTPUT REFERENCE WAVEFORM(1)
AC TESTING LOAD CIRCUIT(1)
1.3V
2.0
lN914
OUTPUT
0.8
290429-11
OUT
AC test inputs are driven at VOH (2.4 VnLl for a Logic "1" and VOL (0.45 VnLl for a Logic
"0". Input timing begins at VIH (2.0 VnLl and VIL (O.S VnLl. Output timing ends at VIH and
VIL. Input rise and fall times (10% to 90%) < 10 ns.
CL = 100 pF
CL Irlcludes Jig
Capacitance
RL = 3.3 kfi
HIGH SPEED
AC INPUT/OUTPUT REFERENCE WAVEFORM(2)
:.:=::x
290429-12
HIGH SPEED
AC TESTING LOAD CIRCUIT(2)
1.3Y
.5 - -
TE5~
IN914
POIHTS - _ ) ( . 5
OUTPUT
290429-17
OUT
AC test inputs are driven at 3.0V for a Logic "1" and O.OV for a Logic "0". Input timing
begins, and outpu1 timing ends, at 1.5V. Input rise and fall times (10% to 90%) < 10 ns.
CL = 30 pF
CL Includes Jig
Capacitance
RL = 3.3 kfi
290429-18
NOTES:
1. Testing characteristics for 28F008SA-85 in Standard configuration, and 28F008SA-120.
2. Testing characteristics for 28F008SA-85 in High Speed configuration.
AC CHARACTERISTICS-Read-Only Operations(1)
I
I
Versions
Symbol
VCC±5%
tAVAV
tRC
tAVQV
tACC
Address to Output Delay
Notes
Min
Max
85
Min
tCE
CE # to Output Delay
tpHQV
tpWH
RP# High to Output Delay
2
tGLQV
tOE
OE# to Output Delay
2
tELQX
tLZ
CE # to Output Low Z
3
tEHQZ
tHZ
CE # High to Output High Z
3
lGLQX
tOll
OE # to Output Low Z
3
tDF
OE # High to Output High Z
3
tOH
Output Hold from
Addresses, CE # or OE #
Change, Whichever is First
3
2BF008SA-120(5)
Min
Unit
Max
ns
120
90
120
ns
ns
85
90
120
400
400
400
ns
40
45
50
ns
0
0
0
55
0
0
30
0
ns
ns
0
30
0
ns
55
55
30
0
Max
90
85
tELQV
tGHQZ
2BFOOBSA-B5(5)
VCC± 10%
Parameter
Read Cycle Time
2BFOOBSA-B5(4)
ns
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to teE-toE after the falling edge of CE# without impact on tCE.
3. Sampled, not 100% tested.
4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
3-465
28F008SA
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTIC5-Read-Only Operations(1)
I VCC± 10%
Versions
Symbol
Parameter
Notes
tAVAV
tRc
Read Cycle Time
tAVOV
tACC
Address to Output Delay
tELQV
tCE
CE # to Output Delay
tpHQV
tPWH
RP# High to Output Delay
tGLOV
tOE
OE# to Output Delay
2
tELQX
tLl
CE # to Output Low Z
3
tEHQZ
tHZ
CE# High to Output High Z
3
28F008SA-100(5)
Unit
Min
Max
100
2
43LOX
toll
OE # to Output Low Z
3
tGHQZ
tDF
OE# High to Output High Z
3
tOH
Output Hold from Addresses, CE # or
OE# Change, Whichever is First
3
ns
100
ns
100
ns
400
ns
55
ns
0
ns
55
0
ns
30
0
ns
ns
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to tCE-tOE after the falling edge of CE# without impact on tCE.
3. Sampled, not 100% tested.
4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
3-466
-
--
'12l
aID
vee POWER-UP
Iiiiil
STANDBY
DEVICE AND
ADDRESS SELECTION
OUTPUTS ENABLED
STANDBY
DATA VALID
Vee POWER-DOWN
VIH
IF
=
ADDRESSES (A)
~
ADDRESSES STABLE
€:
®
VIL
=
~
I·
I~----------------
~
2i
~VAV - ---------------1
1 -. 11
VIH
~
CE# (E)
VIL
"I'll
iii
C
~
....
P
~
VIH
OE# (G)
VIL
~
CD
0'
...
3
VIH
WE# (w)
0'
...
VIL
::u
CD
ioH
!.
0
'a
CD
'rLOX
VaH
ill
~
HIGH Z
HIGH Z
DATA (D/O)
VALID OUTPUT
VOL
- - - - - - - tAVQV-----~
::s
III
S.OV
Vee
GND
VIH
1
~HOV
·1
\
t\)
CD
RP# (p) VIL
Co)
~
290429-13
~
Q
CD
~
28F008SA
AC CHARACTERISTICS-Write Operations(1)
I Vcc±5%
I Vcc±10%
Versions
Symbol
Parameter
Notes
28FOO8SA-85(7)
28FOO8SA-85(8)
Min
.tAVAV
twc
Write Cycle Time
tPHWL
tps
RP# High Recovery to
WE #. Going Low
tELWL
tcs
CE# Setup to WE# Going
Low
tWLWH
twp
WE# Pulse Width
40
tVPWH
tvps
Vpp Setup to WE # GOing
High
2
100
tAVWH
tAS
Address Setup to WE #
Going High
3
40
tOVWH
tos
Data Setup to WE # Going
High
4
twHOX
tOH
tWHAX
Max
Min
Max
28FOO8SA-120(8)
Min
Unit
Max
85
90
120
ns
1
1
1
",s
10
10
to
ns
40
40
ns
100
100
ns
40
40
ns
40
40
40
ns
Data Hold from WE# High
5
5
5
ns
tAH
Address Hold from WE#
High
5
5
5
ns
tWHEH
tCH .
CE# Hold from WE# High
10
10
10
ns
tWHWL
tWPH
WE # Pulse Width High
30
2
30
ns
tWHRL
tWHOVl
Duration of Byte Wriie
Operation
5,6
6
6
6
",s
tWHOV2
Duration of Block Erase
Operation
5,6
0.3
0.3
0.3
sec
twHGL
Write Recovery before
Read
0
0
0
",s
0
0
0
ns
tOWL
tVPH
Vpp Hold from Valid SRD,
RY/BY# High
100
30
WE# HightciRY/BY#
Going Low
2,6
100
100
ns
NOTES:
1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
·3. Refer to Table 3 for valid AIN for byte write or block erasure.
4. Refer to Table 3 for valid DIN for byte write or block erasure.
5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard
Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and
erase verify (block erase).
6. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY# = VOH). Vpp should be held at
VPPH until determination of byte write/block erase success (SR.3/4/5 = 0)
"1. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
8. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
3-468
28F008SA
BLOCK ERASE AND BYTE WRITE PERFORMANCE
Parameter
Notes
28FOO8SA-85
Min
28FOO8SA-120
Typ(1)
Max
Unit
Typ(1)
Max
10
1.6
10
sec
Min
Block Erase Time
2
1.6
Block Write Time
2
0.6
2.1
0.6
2.1
sec
8
(Note 3)
8
(Note 3)
J.Ls
Byte Write Time
NOTES:
1. 25°C, 12.0 Vpp.
2. Excludes System-Level Overhead.
3. Contact your Intel representative for information on the maximum byte write specification.
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS-Write Operations(1)
I Vcc±10%
Versions
Symbol
Parameter
Notes
2BFOOBSA-100(8)
Unit
Min
Max
tAVAV
twc
Write Cycle Time
tpHWL
tps
RP# High Recovery to WE# Going Low
tELWL
tcs
tWLWH
twp
tVPWH
tvps
Vpp Setup to WE# Going High
tAVWH
tAS
Address Setup to WE # Going High
4
40
ns
5
ns
100
ns
1
,..s
CE # Setup to WE # Going Low
10
ns
WE# Pulse Width
40
ns
2
100
ns
3
40
ns
2
tovwH
tos
Data Setup to WE# Going High
tWHOX
tOH
Data Hold from WE# High
tWHAX
tAH
Address Hold from WE # High
5
ns
tWHEH
tCH
CE# Hold from WE# High
10
ns
tWHWL
tWPH
WE# Pulse Width High
30
ns
tWHRL
WE# High to RY /BY # Going Low
tWHOV1
Duration of Byte Write Operation
5,6
6
,..s
tWHOV2
Duration of Block Erase Operation
5,6
0.3
sec
tWHGL
Write Recovery before Read
0
,..s
0
ns
tOWL
tVPH
Vpp Hold from Valid SRD, RY /BY # High
100
2,6
ns
NOTES:
1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte write or block erasure.
4. Refer to Table 3 for valid DIN for byte write or block erasure.
5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard
Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and
erase verify (block erase).
6. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY# = VOH). Vpp should be held at
VPPH until determination of byte write/block erase success (SR.3/4/5 = 0)
7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
B. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
3-469
28F008SA
EXTENDED TEMPERATURE OPERATION
BLOCK ERASE AND· BYTE WRITE PERFORMANCE
Parameter
Notes
28FOO8SA-100
Min
Typ(1)
Max
Unit
Block Erase Time
2
1.6
10
sec
Block Write Time
2
0.6
2.1
sec
8
(Note 3)
p.s
Byte Write Time
NOTES:
1. 25°C. 12.0 Vpp.
2. Excludes System-Level Overhead.
3. Contact your Intel representative for information on the maximum byte write specification.
3-470
-
WRITE
Vee POWER-UP WRITE BYTE WRITE OR VALID ADDRESS & DATA (BYTE WRITE) AUTOMATED BYTE WRITE
& STANDBY
ERASE SETUP COMMAND
OR ERASE CONFIRM COMMAND
OR ERASE DELAY
"i§)
2aJ
Iiiiil
READ STATUS
REGISTER DATA
--
£
WRITE READ ARRAY
COMMAND
VIH
IF
ADDRESSES (A)
~
@J
VIL
~
VIH
~
am
CEO (E)
~
VIL
"11
VIH
~.
C
jj;
OE# (G)
VIL
:-"
~
~
o-
VIH
WE# (W)
VIL
3
0...
...=E
VIH
DATA (D/a)
VIL
;:
o
"a
VOH
CD
RY /BY# (R)
o·
::J
VOL
I/)
VIH
RP# (p)
VIL
VpPH
VPP (V)
i--l
t VPWH
VpPL
VIH
N
Q)
"TI
t.)
J,..
:1
o
o
VIL
Q)
290429-14
(J)
~
28F008SA
ALTERNATIVE CE#-CONTROLLED WRITES
I Vcc±5%
I Vcc±10%
Versions
Symbol
Parameter
Notes
28FOO8SA·85(6)
28FOO8SA·85(7)
Min
tAVAV
twc
Write Cycle Time
tpHEL
tps
RP# High Recovery to
CE# Going Low
tWLEL
tws
WE# Setup to CE# GOing
Low
tELEH
tcp
CE# Pulse Width
50
tVPEH
tvps
Vpp Setup to CE# Going
High
2
100
tAVEH
tAS
Address Setup to CE#
Going High
3
40
tOVEH
tos
Data Setup to CE# Going
High
4
tEHOX
tOH
tEHAX
Max
Min
Max
28FOO8SA·120(7)
Min
Unit
Max
85
90
120
ns
1
1
1
,...s
0
0
0
ns
50
50
ns
100
100
ns
40
40
ns
40
40
40
ns
Data Hold from CE# High
5
5
5
ns
tAH
Address Hold from CE#
High
5
5
5
ns
tEHWH
tWH
WE# Hold from CE# High
0
0
0
ns
tEHEL
tEPH
CE # Pulse Width High
25
25
25
2
ns
tEHRL
CE # High to RY IBY #
Going Low
tEHOVl
Duration of Byte Write
Operation
5
6
6
6
,...s
tEHOV2
Duration of Block Erase
Operation
5
0.3
0.3
0.3
sec
tEHGL
Write Recovery before
Read
0
0
0
,...s
0
0
0
ns
!oWL
tVPH
Vpp Hold from Valid SRD,
RY/BY# High
100
2,5
100
100
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE#. In systems where
CE# defines the write pulsewidth (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be
measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte write or block erasure.
4. Refer to Table 3 for valid DIN for byte write or block erasure.
5. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY# = VOH). Vpp should be held at
VpPH until determination of byte write/block erase success (SR.3/4/5 = 0)
6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteris'
,
tics.
7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for 'testing characteristics.
3-472
28F008SA
EXTENDED TEMPERATURE OPERATION
ALTERNATIVE CE # -CONTROLLED WRITES
1Vcc±10%
Versions
Symbol
Parameter
Notes
2BFOOBSA·100(7)
Unit
Min
Max
100
ns
1
JLs
WE # Setup to CE # Going Low
0
ns
CE # Pulse Width
50
ns
2
100
ns
3
40
ns
40
ns
5
ns
tAVAV
twe
Write Cycle Time
tpHEl
tps
RP# High Recovery to CE# Going Low
tWlEl
tws
tElEH
tcp
tVPEH
tvps
Vpp Setup to CE# Going High
tAVEH
tAS
Address Setup to CE # Going High
tDVEH
tDS
Data Setup to CE# Going High
4
tEHDX
tDH
Data Hold from CE# High
tEHAX
tAH
Address Hold from CE # High
5
ns
tEHWH
tWH
WE # Hold from CE # High
0
ns
tEHEl
tEPH
CE # Pulse Width High
25
2
ns
tEHRl
CE # High to RY /BY # Going Low
tEHOV1
Duration of Byte Write Operation
5
6
JLs
tEHOV2
Duration of Block Erase Operation
5
0.3
sec
0
JLs
0
ns
Write Recovery before Read
tEHGl
tOWl
100
tVPH
Vpp Hold from Valid SRD, RY /BY # High
2,5
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE#. In systems where
CE # defines the write pulsewidth (within a longer WE # timing waveform), all setup, hold and inactive WE # times should be
measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte write or block erasure.
4. Refer to Table 3 for valid DIN for byte write or block erasure.
5. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY# = VOH). Vpp should be held at
VPPH until determination of byte write/block erase success (SR.3/4/5 = 0)
6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics.
3·473
N
011
(,)
~
WRITE
Vee POWER-UP WRITE BYTE WRITE OR VALID ADDRESS & DATA (BYTE WRITE) AUTOMATED BYTE WRITE
&: STANDBY
ERASE SETUP COMMAND
OR ERASE CONFIRM COMMAND
OR ERASE DELAY
.........
READ STATUS
REGISTER DATA
~
WRITE READ ARRAY
COMMAND
o
011
V1H
~
ADDRESSES (A)
V1l
'rHAX
V1H
WE# (w)
V1l
."
C
...
c
'rHGl
CD
....
~
OE# (G)
l>
;:...
V1l
III
V1H
'rHQV1.2
::J
;~
.1
V1H
'1
CE# (E)
V1l
~
CD
0-
3
V1H
DATA (D/a)
...0...=e
;:
o
"0
V1l
VOH
RY/BY# (R)
Val
CD
ao
'\§J
~
V1H
RP# (P)
~
V1l
Iiiiil
IF
VpPH
~
~
~
-
2:eJ
~
VPP (V)
!-----+I
t VPEH
VpPl
V1H
V1l
290429-15
-::l
c[
@
28F008SA
ORDERING INFORMATION
I
OPERATING TEMPERATURE
T = EXTENDED TEMP
BLANK
COMMERCIAL TEMP
=
VALID COMBINATIONS
E28F008SA-85
F28F008SA-85
E28F008SA-120
F28F008SA-120
IE121al,10101als1AI-la151
Ii
PACKAGE
E = STANDARD 40 LEAD TSOP
REVERSE 40 LEAD TSOP
PA = 44 LEAD PSOP
TB = 44 LEAD PSOP (EXT. TEMP)
~
L ACCESS SPEED (ns)
a5 ns
120 ns
,=
PA28F008SA-85
PA28F008SA-120
TE28F008SA-100
TF28F008SA-100
290429-16
TB28F008SA-100
ADDITIONAL INFORMATION
AP-359
AP-360
AP-364
ER-27
ER-28
28F008SA-L Datasheet
"28F008SA Hardware Interfacing"
"25F008SA Software Drivers"
"28F008SA Automation and Algorithms"
"The Intel 28F008SA Flash Memory"
"ETOX 11\ Flash Memory Technology"
Order
Number
290435
292094
292095
292099
294011
290412
REVISION HISTORY
Number
Description
002
Revised from Advanced Information to Preliminary
Modified Erase Suspend Flowchart
Removed -90 speed bin
Integrated -90 characteristics into -85 speed bin
Combined Vpp Standby current and Vpp Read
current into one Vpp Standby current spec with two
test conditions (DC Characteristics table)
Lowered VLKO from 2.2V to 2.0V.
004
PWD renamed to RP# for JEDEC standardization
compatibility.
Changed IpPS Standby current spec from ± 10 /A-A to
± 15 /A-A in DC Characteristics table.
005
Added Extended Temperature Specs for 28F008SA
Added IpPR Spec
Corrected Ipps Spec Type
Added VOHZ (Output High Voltage-CMOS) Spec
Added Byte Write Time Spec
3-475
28F008SA-L
8-MBIT (1 MBIT x 8) FLASHFILETM MEMORY
•
••
High-Density Symmetrically Blocked
Architecture
- Sixteen 64-Kbyte Blocks
Low-Voltage Operation
- -3.3V ±O.3V or 5.0V ± 10% Vee
• Extended Cycling Capability
. -10,000 Block Erase Cycles
-160,000 Block Erase
Cycles per Chip
Read
• -High-Performance
200 ns Maximum Access Time
Mode
• -Deep-Powerdown
0.20 /-tA lee Typical
Write Interface
• SRAM-Compatible
Hardware Data Protection Feature
• - Erase/Write Lockout during Power
Transitions
Industry Standard Packaging
•
Byte Write and Block Erase
- 40-Lead TSOP, 44-Lead PSOP
• -Automated
Command User Interface
III Nonvolatile Flash Technology
- Status Register
• -ETOX
12V Byte Write/Block Erase
Performance Enhancements
• -System
RY /BY Status Output
#
- Erase Suspend Capability
Intel's 2SFOOSSA-L S Mbit FlashFile™ Memory is the highest density nonvolatile read/write solution for solid
statestorage. The 2SFOOSSA-L's extended cycling, symmetrically blocked architecture, fast access time, write
automation and very low power consumption provide a more reliable, lower power, lighter weight and higher
performance alternative to traditional rotating disk technology. The 2SFOOSSA-L brings new capabilities to
portable computing. Application and operating system software stored in resident flash memory arrays provide
instant-on, rapid execute-in-place and protection from obsolescence through in-system software updates.
Resident software also extends system battery life and increases reliability by reducing disk drive accesses.
For high density data acquisition applications, the 2SFOOSSA-L offers a more cost-effective and reliable alternative to SRAM and battery. Traditional high density embedded applications, such as telecommunications, can
take advantage of the 2SFOOSSA-L's nonvolatility, blocking and minimal system code requirements for flexible
firmware and modular software designs.
The 2SFOOSSA-L is offered in 40-lead TSOP (standard and reverse) and 44-lead PSOP packages. Pin assignments simplify board layout when integrating multiple devices in a flash memory array or subsystem. This
device uses an integrated Command User Interface and state machine for simplified block erasure and byte
write. The 2SFOOSSA-L memory map consists of 16 separately erasable 64-Kbyte blocks.
Intel's 2SFOOSSA-L employs advanced CMOS circuitry for systems requiring low power consumption and
noise immunity. Its 200 ns access time provides superior performance when compared with magnetic storage
media. A deep powerdown mode lowers power consumption to 0.66 /J-W typical thru Vcc, crucial in portable
computing, handheld instrumentation and other low-power applications. The RP# power control input also
provides absolute data protection during system powerup/down.
Manufactured on Intel's O.S micron ETOX process, the 2SFOOSSA-L provides the highest levels of quality,
reliability and cost-effectiveness.
·Microsoft is a trademark of Microsoft Corporation.
3-476
November 1994
Order Number: 290435-004
28F008SA-L
PRODUCT OVERVIEW
The 2BFOOBSA-L is a high-performance 8-Mbit
(B,3BB,60B-bit) memory organized as 1 Mbyte
(1,04B,576 bytes) of B bits each. Sixteen 64-Kbyte
(65,536-byte) blocks are included on the
2BFOOBSA-L. A memory map is shown in Figure 6 of
this specification. A block erase operation erases
one of the sixteen blocks of memory in typically 2.0
seconds, independent of the remaining blocks.
Each block can be independently erased and written
10,000 cycles. Erase Suspend mode allows system software to suspend block erase to read data or
execute code from any .other block of the
2BFOOBSA-L.
The Status Register indicates the status of the
WSM and when the WSM successfully completes
the desired byte write or block erase operation.
The RYIBY # output gives an additional indicator of
WSM activity, providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase,
for example). Status polling using RY IBY # minimizes both CPU overhead and system power consumption. When low, RY IBY # indicates that the
WSM is performing a block erase or byte write operation. RY IBY # high indicates that the WSM is ready
for new commands, block erase is suspended or the
device is in deep powerdown mode.
The 2BFOOBSA-L is available in the 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and 44lead PSOP (Plastic Small Outline) packages. Pinouts are shown in Figures 2 and 4 of this specification.
Maximum access time is 200 ns (tACC) over the
commercial temperature range (O°C to + 70°C) and
over Vee supply voltage range (3.0V to 3.6V and
4.5V to 5.5V). Icc active current (CMOS Read) is
5 mA typical, 12 mA maximum at 5 MHz,
3.3V ±O.3V.
The Command User Interface serves as the interface between the microprocessor or microcontroller
and the internal operation of the 2BFOOBSA-L.
When the CE# and RP# pins are at Vee, the Icc
CMOS Standby mode is enabled.
Byte Write and Block Erase Automation allow
byte write and block erase operations to be executed using a two-write command sequence to the
Command User Interface. The internal Write State
Machine (WSM) automatically executes the algorithms and timings necessary for byte write and
block erase operations, including verifications,
thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in
byte increments typically within 11 /Ls, Ipp byte
write and block erase currents are 10 mA typical,
30 mA maximum. Vpp byte write and block erase
voltage is 11.4V to 12.6V.
A Deep Powerdown mode is enabled when the
RP# pin is at GND, minimizing power consumption
and providing write protection. Icc current in deep
powerdown is 0.20 /LA typical. Reset time of 500 ns
is required from RP# switching high until outputs are
valid to read attempts. Equivalently, the device has a
wake time of 1 /Ls from RP# high until writes to the
Command User Interface are recognized by the
2BFOOBSA-L. With RP# at GND, the WSM is reset
and the Status Register is cleared.
3-477
~
(,)
~
~
al
Q
CI
~
000 -o~
r-
:!!
co
c
;;
I
:-"
!i!!
o
n
Ij
2
7t:'
i
P' ~!~
C
iii
co
~
l§!
~
~
@
ffiiiI
iil
3
RY/BY#
Ao -
AI9
Vpp
. - Vee
. - GNO
~
'iii]
@
aID
~
~
C::J
=
@
-
~
290435-1
_.
::s
c[
@
28F008SA·L
Table 1. Pin Description
Symbol
Ao-A19
Type
INPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
INPUTIOUTPUT
DATA INPUT/OUTPUTS: Inputs data and commands during Command
User Interface write cycles; outputs data during memory array, Status
Register and Identifier read cycles. The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled. Data is internally latched during a write cycle.
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers,
decoders, and sense amplifiers. CE# is active low; CE# high deselects
the memory device and reduces power consumption to standby levels.
RP#
INPUT
RESET/DEEP POWER DOWN: Puts the device in deep powerdown
mode. RP# is active low; RP# high gates normal operation. RP# also
locks out block erase or byte write operations when active low, providing
data protection during power transitions. RP# active resets internal
automation. Exit from Deep Powerdown sets device to read-array mode.
OE#
INPUT
OUTPUT ENABLE: Gates the device's outputs through the data buffers
during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command User Interface and
array blocks. WE# is active low. Addresses and data are latched on the
rising edge of the WE # pulse.
OUTPUT
READYIBUSY #: Indicates the status of the internal Write State
Machine. When low, it indicates that the WSM is performing a block
erase or byte write operation. RYIBY # high indicates that the WSM is
ready for new commands, block erase is suspended or the device is in
deep powerdown mode. RYIBY # is always active and does NOT float
to tri-state off when the chip is deselected or data outputs are disabled.
DQo-DQ7
RY/BY#
Vpp
BLOCK ERASE/BYTE WRITE POWER SUPPLY for erasing blocks of
the array or writing bytes of each block.
NOTE:
With Vpp < VPPLMAX, memory contents cannot be altered.
Vee
DEVICE POWER SUPPLY (3.3V ± 0.3V, 5V ± 10%)
GND
GROUND
3-479
intel®
28FOO8SA·L
Standard Pinout
NC
NC
W[#
0[#
RY/BY#
0
1<,9
I<,s
1<,7
1<,6
AIS
36
35
1<,4
1<,3
, 1<,2
C[#
Vee
Vpp
RP#
1<,1
1<,0
D~
006
005
004
ST ANDARD PINOUT
E28F008SA-L
40 LEAD TSOP
10 mm X 20 mm
TOP VIEW
31
Vee
GHD
GND
003
D02
D~
As
As
000
A7
Ao
As
Al
A2
A3
As
A4
21
290435-2
Reverse Pinout
HC
NC
W[#
0[#
RY/BY#
D~
006
005
004
~V
3
4
5
6
7
8
9
Vee
GND
GND
003
002
0
REVERSE PINOUT
F28F008SA-L
40 LEAD TSOP
10 mm X 20 mm
TOP VIEW
001
000
Ao
Al
A2
A3
20
40
39
38
,37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A19
AIS
1<,7
1<,6
1<,5
1<,4
1<,3
1<,2
C[#
Vee
Vpp
RP#
All
A10
A9
As
A7
As
As
A4
290435-3
Figure 2. TSOP Lead Configurations
3-480
28F008SA·L
o
1111111111111111111111111111111111111111
~1II111.1II1111111.lllIIlIllIIglIl~'nnlUflnlln;rf1ijJ.WWIInIWWI.
11111111"- -"
I"l
co
...,
and
transient peaks produced by falling and rising edges
of CE#. Transient current magnitudes depend on
the device outputs' capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 p,F ceramic capacitor
connected between each Vee and GND, and between its Vpp and GND. These high frequency, low
inherent-inductance capacitors should be placed as
close as possible to package leads. Additionally, for
every 8 devices, a 4.7 p,F electrolytic capacitor
should be placed althe array's power supply connection between Vee and GND. The bulk capacitor
will overcome voltage slumps caused by PC board
trace inductances.
Vpp Trace on Printed Circuit Boards
Writing flash memories, while they reside in the target system, requires that the printed. circuit board
designer pay attention to the Vpp power supply
trace. The Vpp pin supplies the memory cell current
for writing and erasing. Use similar trace widths and
layout considerations given to the Vee power bus.
Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.
3-491
28F008SA-L
Vee, Vpp, RP# Transitions and the
Command/Status Registers
2BFOOBSA-L ensures that the Command User Interface is reset to the Read Array mode on power up.
Byte write and block erase completion are not guaranteed if Vpp drops below VPPH-" If the Vpp Status bit
of the Status Register (SR.3) is set to "1", a Clear
Status Register command MUST be issued before
further byte write/block erase attempts are allowed
by the WSM. Otherwise, the Byte Write (SR.4) or
Erase (SR.5) Status bits of the Status Register will
be set to "1 "s if error is detected. RP# transitions to
VIL during byte write and block erase also abort the
operations. Data is partially altered in either case,
and the command sequence must be repeated after
normal operation is restored. Device poweroff, or
RP# transitions to VIL, clear the Status Register to
initial value 10000 for the upper 5 bits.
A system designer must guard against spurious
writes for Vee voltages above VLKO when Vpp is
active. Since both WE # and CE # must be low for a
command write, driving either to VIH will inhibit
writes. The Command I,Jser Interface architecture
provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences.
The Command User Interface latches commands as
issued by system software and is not altered by Vpp
or CE # transitions or WSM actions. 'Its state upon
powerup, after exit from deep powerdown or after
Vee transitions below VLKO, is Read Array Mode.
After byte write or block erase is complete, even
after Vpp transitions down to VpPL, the Command
User Interface must be reset to Read Array mode via
the Read Array command if access to the memory
array is desired.
Power Up/Down Protection
The 2BFOOBSA-L is designed to offer protection
against accidental block erasure or byte writingduring' power transitions. Upon power-up, the
2BFOOBSA-L is indifferent as to which power supply,
Vpp or Vee, powers up first. Power supply sequencing is not required. Internal circuitry in the
3-492
Finally, the device is disabled until RP# is brought to
VIH, regardless of the state of its control inputs. This
provides an additional level of memory protection.
Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time., Flash nonvolatility increases usable battery life, because the 2BFOOBSA-L does not
consume any power to retain code or data when the
'
system is off.
In addition, the 2BFOOBSA-L's deep powerdown
mode ensures extremely low power diSSipation even
when system power is applied.' For example, portable PCs and other power, sensitive applications, using an array of 2BFOOBSA-Ls for solid-state storage,
'can lower RP# to VIL in standby or sleep modes,
producing negligable power consumption. If access
to the 2BFOOBSA-L is again needed, the part can
again be read, following the tpHQV and tPHWL wakeup cycles required after RP# is first raised back to
VIH. See AC Characteristics-Read-Only and Write
Operations and Figures 10 and 11 for more information.
28F008SA·L
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature
During Read ............... - 20·C to + 70·C(1)
During Block Erase/Byte Write .... O·C to + 70·C
Storage Temperature .......... - 65·C to
+ 80·C
+ 125·C
Voltage on Any Pin
(except Vee and Vpp) ,
with Respect to GND ........ - 2.0V to
+ 7.0V(2)
Temperature Under Bias ......... - 20·C to
Vpp Program Voltage with
Respect to GND during
Block Erase/Byte Write ... - 2.0V to
NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet before finalizing a design.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 14.0V(2, 3)
Vee Supply Voltage
with Respect to GND ........ - 2.0V to
+ 7.0V(2)
Output Short Circuit Current. .•.......... 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee + 2.0V
for periods < 20 ns.
3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods <20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. AC specifications are valid at both voltage ranges. See DC Characteristics for voltage range specific specification.
OPERATING CONDITIONS
Symbol
Parameter
Notes
Min
Max
Unit
-20
70
·C
5
3.00
3.60
V
Vec Supply Voltage
(Program/Erase)
5
3.15
3.60
V
Vee Supply Voltage
5
4.50
5.50
V
TA
Operating Temperature
Vec
Vce Supply Voltage (Read)
Vee
Vee
DC CHARACTERISTICS
Symbol
Vee
Parameter
=
3.3V ±0.3V Read, 3.15-3.6 Program/Erase
Notes
Min
Typ
Max
Unit
Test Condition
III
Input Load Current
1
±0.5
/A-A
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage Current
1
±0.5
/A-A
Vee = Vee Max
VOUT = Vee or GND
lees
Vee Standby Current
20
2.0
mA
Vee = Vee Max
CE# = RP# = VIH
30
100
/A-A
Vee = Vee Max
CE# = RP# = Vee ±0.2V
0.20
1.0
/A-A
RP# = GND ±0.2V
lOUT (RY/BY#) = OmA,
leeD
Vee Deep PowerDown
Current
1,3
1
3-493
28F008SA-L
DC CHARACTERISTICS (Continued)
Symbol
leeR
Parameter
Vee Read Current
Notes
Min
1
Unit
Test Condition
Typ
Max
5
12
mA Vee = Vee Max, CE# = GND
f = 5 MHz, lOUT = 0 mA
CMOS Inputs
5
12
mA Vee = Vee Max, CE# == VIL
f = 5 MHz, lOUT = 0 mA
TIL Inputs
mA Byte Write In Progress
leew
Vee Byte Write Current
1
6
18
IeeE
Vee Block Erase Current
1
6
18
mA Block Erase In Progress
leeES
Vee Erase Suspend
Current
1,2
3
6
mA Block Erase Suspended
CE# = VIH
IpPS
Vpp Standby Current
1
±1
±15
/A-A Vpp::;; Vee
IpPD
Vpp Deep PowerDown
Current
1
0.10
5.0
/A-A RP#
IpPR
Vpp Read Current
200
/A-A Vpp> Vee
Ippw
Vpp Byte Write Current
1
10
30
mA Vpp = VPPH
Byte Write in Progress
IpPE
Vpp Block Erase Current
1
10
30
mA Vpp = VPPH
Block Erase in Progress
IpPES
VPP Erase Suspend
Current
1
90
200
/A-A VPP = VPPH
Block Erase Suspended
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
3
VOH1
Output High Voltage (TIL)
3
VOH2
Output High Voltage
(CMOS)
0.4
V
V
V
Vee
V
Vee
V. IOH
0.85 Vee
Vee - 0.4
4
IOH
0.0
VPP during Normal
Operations
VPPH
VPP during Erase/Write
Operations
11.4
VLKO
Vee Erase/Write Lock
Voltage
2.0
Symbol
+ 0.5
2.4
VPPL
CAPACITANCE(5)
0.6
Vee
12.0
6.5
V
12.6
V
V
TA = 25°C, f = 1 MHz
Parameter
Typ
Max
Unit
Condition
CIN
Input Capacitance
6
8
pF
VIN = OV
COUT
Output Capacitance
8
12
pF
VOUT = OV
3-494
= GND ±0.2V
== Vee Min, IOL = 2 mA
= Vee Min, IOH = -2 mA
= 2.5 /A-A, Vee = Vee Min
= -100 /A-A, Vee = Vee Min
28F008SA-L
NOTES:
1. All currents are in RMS unless otherWise noted. Typical values at Vee = 3.3V, Vpp = 12.0V, T = 25'e. These currents
are valid for all product versions (packages and speeds).
2. leeEs is specified with the device deselected. If the 2BFOOBSA-L is read while in Erase Suspend Mode, current draw is
the sum of leeEs and leeR.
3. Includes RY /BY # .
4. Block Erases/Byte Writes are inhibited when Vpp = VPPL and not guaranteed in the range between VPPH and VPPL.
5. Sampled, not 100% tested.
DC CHARACTERISTICS Vee = 5.0V ±10%
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
III
Input Load Current
1
±1.0
/LA Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage Current
1
±10
Ices
Vee Standby Current
/LA Vee = Vee Max
VOUT = VeeorGND
mA Vee = Vee Max
CE# = RP# = VIH
1,3
1.0
2.0
30
100
p.A Vee = Vee Max
CE# = RP# = Vee ±0.2V
IceD
Vee Deep PowerDown
Current
1
0.20
1.2
/LA RP# = GND ±0.2V
lOUT (RY/BY#) = 0 mA
leeR
Vee Read Current
1
20
35
rnA Vee = Vee Max, CE# = GND
f = 5 MHz, lOUT = 0 rnA
CMOS Inputs
25
50
rnA Vee = Vee Max, CE# = VIL
f = 5 MHz, lOUT = 0 rnA
TIL Inputs
,
leew
Vee Byte Write Current
1
10
30
rnA Byte Write In Progress
IeeE
Vee Block Erase Current
1
10
30
rnA Block Erase In Progress
leeES
Vee Erase Suspend
Current
1,2
5
10
rnA Block Erase Suspended,
CE# = VIH
Ipps
Vpp Standby Current
1
±1
±15
IpPD
Vpp Deep PowerDown
Current
1
0.10 '
5.0
IpPR
Vpp Read Current
1
90
200
Ippw
Vpp Byte Write Current
1
10
30
IpPE
Vpp Block Erase Current
1
10
30
rnA Vpp = VPPH
Block Erase in Progress
IpPES
Vpp Erase Suspend
Current
1
90
200
/LA Vpp = VPPH
Block Erase Suspended
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
V
VOL
Output Low Voltage
3
Vee + 0.5
0.45
VOH1
Output High Voltage (TIL)
3
VOH2
Output High Voltage
(CMOS)
VPPL
Vpp during Normal
Operations
4
/LA Vpp:5: Vee
p.A RP# = GND ±0.2V
/LA Vpp> Vee
rnA Vpp = VPPH
Byte Write in Progress
V Vee = Vee Min, IOL = 5.8 rnA
2.4
V Vee = Vee Min, IOH = -2.5 rnA
0.85 Vee
Vee - 0.4
V IOH = -2.5 p.A, Vee = Vee Min
0.0
IOH = -100 /lA, Vee = Vee Min
6.5
V
3-495
28F008SA-L
DC CHARACTERISTICS (Continued) Vcc
= 5.0V ± 10%
Min
Typ
Max
Unit
VPPH
Vpp during Erase/Write
Operations
11.4
12.0
12.6
V
VLKO
Vcc Erase/Write Lock
Voltage
2.0
Symbol
Parameter
Notes
Test Condition
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, VPP = 12.0V, T =. 25°C. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the 28F008SA-L is read while in Erase Suspend Mode, current draw is
the sum of ICCES and ICCR.
3. Includes RY/BY#.
4. Block Erases/Byte Writes are inhibited when VPP = VPPL and not guaranteed in the range between VpPH and VPPL.
AC TESTING LOAD CIRCUIT(2)
AC INPUT/OUTPUT REFERENCE WAVEFORM
1.3V
-,.~~
::: --IN-P-UT-"")(.5 -
TES;: POINTS -
DEVICE
UNDER
TEST
290435-7
AC test inputs are driven at 3.0V for a Logic "I" and O.OV for a Logic "a". Input timing
begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) < 10 ns.
CL=50pF
CL Includes Jig
Capacitance
RL = 3.3 k!l
AC CHARACTERISTICs-.;..Read-Only Operations(1)
OUT
1'- 1.
-
290435-8
Unit
Notes
Min
Max
200
Read Cycle Time
tRC
tAVQV
tAcC
Address to Output Delay
tELQV
tCE
CE # to Output Delay
tpHQV
tpWH
RP# High to Output Delay
tGLQV
tOE
OE # to Output Delay
tELQX
tLZ
CE # to Output Low Z
tEHQZ
tHZ
CE # High to Output High
tGLQX
tOLZ
OE # to Output Low Z
tDF
OE# High to Output High
tOH
Output Hold from Addresses, CE # or OE #
Change, Whichever is First
2
2
3
Z
3
Z
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE # may be delayed up to tCE-toE after the falling edge of CE # without impact on tCE.
3. Sampled, not 100% tested.
200
ns
200
ns
500
ns
85
ns
ns
55
30
0
ns
ns
0
3
3
ns
0
3
NOTES:
3-496
I
28FOO8SA-L200
Parameter
tAvAV
tGHQZ
Rt.
I
VCC = 3;3V ±0.3V, 5.0V ±10%
Versions
Symbol
lN914
X,,1._5......_OU_T_PU_T_
ns
ns
-
~
§
Vee POWER-UP
~
DEVICE AND
ADDRESS SELECTION
STANDBY
~~
~
OUTPUTS ENABLED
VIH
'iiil
©
~
C:::J
=
©
~
@
tAVAV
~
~
c[
---
Iiiiil
=
:w
-~
DATA VALID
ADDRESSES STABLE
ADDRESSES (A) V
IL
©
-:::J
CE# (E)
V1l _
!!
......
---
CQ
C
CD
?
~
VIH
OE# (G)
V _
1l
0
---
~
DI
-..
<
CD
VIH
0
-..
3
W[# (w)
0
VIL
I-
:II
CD
DI
a.
VOH
0
..
!.
'tI
CD
HIGH Z
DATA (0/0)
VOL
O·
I
en
i-
lI( (( (71
I.
:::I
~LOX-I
toH
1:LOX
VALID OUTPUT
"1\\ \ \1\
HIGH Z
I AVOV
5.0V
Vee
GNO
VIH
r
lpHOV
- -----.j
\
~
I\)
CO
RP# (p)
~
o
VIL
(0)
J,..
CD
-..j
CO
290435-9
~r-
28F008SA-L
AC CHARACTERISTICS-Write Operations(1)
vcc = 3.3V ±0.3V, 5.0V ±10%
28FOO8SA-L200
Versions
Symbol
Parameter
Notes
Write Cycle Time
Min
Unit
Max
200
ns
tAvAV
twc
tPHWL
tps
RP# High Recovery to WE# Going Low
tELWL
tcs
CE# Setup toWE# Going Low
tWLWH
twp
WE # Pulse Width
tVPWH
tvps
VPP Setup to WE# Going High
2
tAVWH
tAS
Address Setup to WE# Going High
3
60
ns
tDVWH
tDS
Data Setup to WE# Going High
4
60
ns
tWHDX
tDH
Data Hold from WE# High
5
ns
tWHAX
tAH
Address Hold from WE# High
5
ns
tWHEH
tCH
CE# Hold from WE# High
10
ns
tWPH
WE# Pulse Width High
30
ns
tWHwL
2
1
Jots
20
ns
60
ns
100
ns
100
ns
tWHRL
WE# High to RY/BY# Going Low
tWHOV1
Duration of Byte Write Operation
5,6
6
Jots
tWHOV2
Duration of Block Erase Operation
5,6
0.3
sec
tWHGL
Write Recovery
before Read
0
JotS
0
ns
tOVVL
tVPH
VPP Hold from Valid SRD, RY IBY # High
2,6
NOTES:
1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte write or block erasure.
4. Refer to Table 3 for valid DIN for byte write or block erasure.
5. The on-chip Write State Machine incorporates ali byte write and block erase system functions and overhead ·of standard
Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and
erase verify (block erase).
6. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY# = VOH). VPP should be held at
VPPH until determination of byte write/block erase success (SR.3/4/5 = 0)
3-498
28F008SA-L
BLOCK ERASE AND BYTE WRITE PERFORMANCE vcc = 3.3VtoO.3V,5.0V ±10%
Parameter
Notes
2SFOOSSA-L-200
Min
Unit
Typ(1)
Max
Block Erase Time
2
2.0
12.5
sec
Block Write Time
2
0.7
2.6
sec
8
(Note 3)
p.s
Byte Write Time
NOTES:
1. 25'C, 12.0 Vpp.
2. Excludes System-Level Overhead.
3. Contact your Intel representative for information on the maximum byte write specification.
3-499
c.:>
N
en
o
WRITE
Vee POWER-UP WRITE BYTE WRITE OR VALID ADDRESS & DATA (BYTE WRITE) AUTOMATED BYTE WRITE
& STANDBY
ERASE SETUP COMMAND
OR ERASE CONFIRM COMMAND
OR ERASE DELAY
o
co
READ STATUS
REGISTER DATA
~
o
WRITE READ ARRAY
COMMAND
co
en
VIH
~
r
ADDRESSES (A)
VIL
VIH
CE# (E)
VIL
."
iii
c::
Cil
VIH
OE# (G)
VIL
:"'"
l;
I3
VIH
WE# (w)
VIL
o
.
.;:
0'
:E
~
I§J
o
'0
~ !
~ o·
CD
©
IiiiiI
~
©
VIL
VOH
RY /BY# (R)
VOL
::I
til
VIH
RP# (p)
'1iiI
VIL
~
YpPH
~
C:::J
YpPL
Ypp (V) VIH
~
VIL
~
-
VIH
DATA (D/a)
©
1--------1
_.
tYPWH
290435-10
£
@
28F008SA-L
ALTERNATIVE CE#-CONTROLLED WRITES
vcc
=
3.3V ±0.3V, 5.0V ±10%
28FOO8SA-L200
Versions
Symbol
Parameter
Notes
Min
Unit
Max
200
ns
1
/Ls
tAVAV
twc
Write Cycle Time
tpHEL
tps
RP# High Recovery to CE# GOing Low
tWLEL
tws
WE # Setup to CE # Going Low
tELEH
tcp
CE # Pulse Width
tVPEH
tvps
Vpp Setup to CE# Going High
tAvEH
tAS
tOVEH
tos
tEHOX
tOH
Data Hold from CE# High
5
ns
tEHAX
tAH
Address Hold from CE # High
5
ns
tEHWH
tWH
WE # Hold from CE # High
0
ns
tEPH
CE# Pulse Width High
25
ns
tEHEL
2
0
ns
70
ns
2
100
ns
Address Setup to CE # Going High
3
60
ns
Data Setup to CE # Going High
4
60
ns
tEHRL
CE # High to RY IBY # Going Low
tEHOV1
Duration of Byte Write Operation
5
6
/Ls
tEHOV2
Duration of Block Erase Operation
5
0.3
sec
tEHGL
Write Recovery before Read
0
/Ls
0
ns
tOVVL
tVPH
VPP Hold from Valid SRD, RY IBY # High
100
2,5
ns
NOTES:
1. Chip· Enable Controlled Writes: Write operations are driven by the valid combination of CE # and WE #. In systems where
CE# defines the write pulsewidth (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be
measured relative to the CE# waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte write or block erasure.
4. Refer to Table 3 for valid OIN for byte write or block erasure.
5. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY# = VOH). Vpp should be held at
VpPH until determination of byte write/block erase success (SR.3/4/5 = 0)
3·501
N
'"ou,
WRITE
Vee POWER-UP WRITE BYTE WRITE·OR VALID ADDRESS &: DATA (BYTE WRITE) AUTOMATED BYTE WRITE
&: STANDBY
ERASE SETUP COMMAND
OR ERASE CONFIRM COMMAND
OR ERASE DELAY
I\)
co
READ STATUS
REGISTER DATA
'TI
WRITE READ ARRAY
COMMAND
Q
Q
~r-
VIH
ADDRESSES (A)
VIL
VIH
WE# (w)
VIL
~
ca
c
trHGL
iil
....
~
VIH
OE# (G)
~
VIL
iii
...
trHQV1,2
j
~
~
i
~
@
3
...0'
J
~ -go
~
©
IiiiiI
~
CE# (E)
VIL
VIH
DATA (D/Q)
VIL
VOH
RY /BY# (R)
VOL
a0j
(/I
VIH
RP# (p)
"iii!
@
VIL
aID
VpPH
~
~
<=:I
=
-
@
~
'1
VIH
VPP (v)
I------l
t VPEH
--
VpPL
VIH
VIL
290435-11
€:
€l
28F008SA·L
ORDERING INFORMATION
I
I
L
PACKAGE
E
STANDARD 40 LEAD TSOP
F = REVERSE 40 LEAD TSOP
PA
44 LEAD PSOP
3.3V
=
=
VALID COMBINATIONS:
E2BFOOBSA·L200
F2BFOOBSA·L200
ACCESS SPEED (ns)
200 ns
290435-12
PA2BFOOBSA·L200
ADDITIONAL INFORMATION
28F008SA Datasheet
Order
Number
290429
AP-359
"28F008SA Hardware Interfacing"
292094
Ap·360
"25F008SA Software Drivers"
292095
AP·364
"28F008SA Automation and Algorithms"
292099
ER·27
"The Intel 28F008SA Flash Memory"
294011
ER·28
"ETOX III Flash Memory Technology"
290412
REVISION HISTORY
Number
Description
002
Modified Erase Suspend Flowchart
Lowered VLKO from 2.2V to 2.0V
Combined Vpp Standby Current and Vpp Read Current into One Vpp Standby Current Spec.
with Two Test Conditions (DC Characteristics Table)
Removed -250 Speed Bin
003
PWD renamed to RP# for JEDEC standardization compatibility.
Changed Ipps standby current specifications from ± 10 /LA to ± 15 /LA in DC Characteristics
tables.
004
Changed leeR test condition from f = 8 MHz to f = 5 MHz
Changed lees Max spec. from 50 /LA to 2.0 mA
Added IpPR spec.
Corrected Ipps spec. typo
Added VOHZ (Output High Voltage-CMOS) spec.
Changed Operating Temp range (read) from ODC-70DC to - 20DC-70DC.
Changed Vee range from 3.3V ± 0.3V to 3.15V-3.6V for Program/Erase.
Added Byte Write Time spec.
3·503
int'el.
AP-607
APPLICATION
NOTE
Multi-Site Layout Planning
with Intel's FlashFile™
Components, Including ROM
Compatibility
BILAL QURESHI
APPLICATIONS ENGINEER
SALIM B. FEDEL
SENIOR APPLICATIONS ENGINEER
November 1994
Order Number: 292159-001
3-504
MULTI-SITE LAYOUT PLANNING WITH INTEL'S
FlashFile™ COMPONENTS, INCLUDING ROM
COMPATIBILITY
CONTENTS
PAGE
1.0 INTRODUCTION ................... 3·506
2.0 PINOUT OPTIONS ................. 3·506
2.1 28F016SA to 28F016SV Pinout
Compatibility ...................... 3·506
3.0 AVAILABLE PACKAGES .......... 3·506
4.0 PCB LAYOUTS .................... 3·506
4.1 Compatible Layout for Upgrading
from Two 8·Mbit to One 16·Mbit
FlashFile Component ............. 3·507
4.2 Compatible Layout for Intel's
16·Mbit FlashFile Component to
16·Mbit ROM Chip ................ 3·508
4.3 Compact Layout for Intel's 16·Mbit
FlashFile Component Using
Standard 56-Lead TSOP Pinout '" 3·508
4.4 Compatible Layout for Upgrading
from Four 8-Mbit to Two 16-Mbit
FlashFile Components ............ 3·509
I
CONTENTS
PAGE
4.7 Compatible Layout for Upgrading
from Two 8-Mbit (TSOP Packaging)
to One 16-Mbit (SSOP
Packaging) ....................... 3·509
4.8 Serpentine Layout for 8·Mbit
FlashFile Component Using
Standard and Reverse 40-Lead
TSOP Pinout ...................... 3·510
4.9 Compatible Layout for Upgrading
from Eight 8-Mbit to Two 32-Mbit
FlashFile Components ............ 3·510
4.10 Compatible Layout for Upgrading
from 16-Mbit (TSOP) to 16-Mbit
(SSOP) ........................... 3·510
5.0 DECOUPLING ..................... 3·510
6.0 GENERAL GUIDELINES AND
METHODOLOGY FOR DESIGNING
COMPATIBLE/COMPACT
LAYOUT ............................ 3-511
4.5 Compatible Layout for Upgrading
from Four 8-Mbit to One 32-Mbit
FlashFile Component ............. 3·509
7.0 AVAILABILITY OF FILES .......... 3·511
4.6 Compatible Layout for Upgrading
from Two 8-Mbit (PSOP Packaging)
to One 16-Mbit (SSOP
Packaging) ....................... 3·509
9.0 ADDITIONAL INFORMATION ..... 3·516
8.0 SUMMARy ......................... 3·516
APPENDIX A. FIGURES ............... 3·517
3·505
Ap·607
1.0 INTRODUCTION
With the availability of the 28FOI6SA/SV and the
DD28F032SA, Intel offers a complete FlashFile™
memory family of components. Available in 8-, 16- and
32-Mbit capacities, these components offer flash solutions for applications ranging from mobile computing
and communications to embedded code/data storage
flash memory systems.
This application note covers the area of designing compatible and/or compact PCB layouts for FlashFile
components (see Figure 1 for example). In addition to
flexible layouts, flash-to-ROM compatible solutions are
provided.
2.1 28F016SA to 28F016SV Pinout
Compatibility
The SmartVoltage 16-Mbit 28F016SV is fully pinoutcompatible with the 28F016SA. Both SmartVoltage
16-Mbit FlashFile Memory devices use a 56-Lead
TSOP and SSOP packages.
The 28F016SA uses the 3/5# pin (pin I) to configure
the flash memory for operation at 3.3V or 5.0V Vee.
The 28FO 16SV uses an internal detector connected to
the Vee pin to accomplish this same function. The
3/5 # pin is no longer needed and pin 1 has been renamed NC (No Connect), therefore preserving compatibility between the two products. All layouts derived
for 28FOl6SA are 100% compatible with 28FOI6SV,
and can be used with no further modifications.
2.0 PINOUT OPTIONS
Whereas the 28FOO8SA is 8-bit wide, the
28FOI6SA/SV and DD28F032SA are high-performance, 16-bit wide FlashFile components, offering a
user-configurable bus width. Hence, an additional eight
I/O pins are on the 28FOI6SA/SV and DD28F032SA.
Furthermore, the implementation of additional features
such as write protect, block locking and user-selectable
3.3Vand 5.0V operation require control pins for·these
functions. Additionally, the DD28F032SA has three
chip enable pins, compared to two on the
28FOI6SA/SV, and one on the 28FOO8SA. In summary, the optimization of the 28FOI6SA/SV and the
DD28F032SA architecture, which achieves high write
performance, results in a different pinout configuration
from the 28F008SA.
3.0 AVAILABLE PACKAGES
The 28FOO8SA is offered in two packages-the 40-Lead
Thin Small Outline Packaging (TSOP), both Standard
and Reverse pinout (Figure 2), and the 44-Lead Plastic
Small Outline Package (PSOP) (Figure 3). The use of
Standard and Reverse TSOP packages arranged in a
serpentine layout. results in an optimum array density
for the 28F008SA (see Section 4.8). The 28F016SA/SV
and DD28F032SA are available in. Standard 56-Lead
TSOP package (see Figure 4). As shown in the examples, the same high density compared to a serpentine
layout is achievable with the use of Standard 56-Lead
TSOPs arranged in an upright position. The
28F016SA/SV are also available in 56-Lead Shrink
Small Outline Package (SSOP) packaging (refer to Figure 5). The 16-Mbit ROM chip used, comes in Standarc\ 44-Lead PSOP and 44-Lead TSOP packages, as
shown in Figures 6 and 7, respectively.
4.0 PCB LAYOUTS
Very high-density layouts have been made possible by
using Intel's advanced PCMCIA layout specifications.
All layouts considered use from two to three layers.
Since power and ground are generally connected to
their respective planes, Vee and GND pins have been
left unconnected.
292159-1
Figure 1. Two Layer Solution for Upgrading from
Two 28F008SA to One 28F016SA/SV, FlashFile
Component (x8 Mode)
3-506
Solutions are designed using the "PADS" software by
View logic Systems, Inc. Of course, the Gerber filesgenerated are industry-standard and can be used on any
major PCB layout tool.
Ap·607
Table 1 provides a list of layouts derived along with
diagrams and relevant information. For the schematics
of these. cases, see Section 6.0.
4.1 Compatible Layout for Upgrading
from Two 8-Mbit to One 16-Mbit
FlashFile Component
This layout deals with two 28F008SAs upgraded to one
28F016SA/SV in 8-bit and 16-bit modes. Two layers
are used, with both the 28FOO8SAs and the
28F016SA/SV residing on layer 1. Figures 8-10 show
x16 mode layout diagrams (for x8 mode, see Section
6.0)
Pins CEo#, BYTE#, 3/5# (28F016SA only) and
WP# have been left unconnected. CEo# and BYTE#
should be connected to the ground plane. In x8 mode,
BYTE# pin is grounded, while in x16 mode, it is connected to Vee. Connection of 3/5# (28F016SA only)
and WP# is dependent on system configuration. Consult Intel's 28F016SA/SV datasheets for complete description of these pins (order numbers 290489 and
290528, respectively).
The enabling of the 28F016SA/SV can either be done
directly from the system bus through a decoder or by
ANDing the 8-Mbit CE#s and connecting output to
CEI # (for schematics see file 2t8xtloh.sch (x16 mode)
and 2t8t160h.sch (x8 mode) in Section 6.0). Of course,
the final implementation is dependent on the system
designer's preference.
Important dimensions are given below (for both x8 and
x16 modes):
Dimension
Feature
Total Layout Area
0.709" sq.
(457.28 mm 2)
X,V
0.836" , 0.848"
(21.23 mm, 21.54 mm)
Trace Width
0.005" (0.127 mm)
Via Size
0.025" (0.635 mm)
Trace to Trace Spacing
0.005" (0.127 mm)
In x8 mode layout, A20 connects to CE# of the upper
8 Mbit. This is a savings of an extra address line.
Table 1. PCB Layout Diagrams and Reference Information
Case
Section
Compatible Layout for Upgrading from Two 8-Mbit (TSOP) to One 16-Mbit (TSOP) FlashFile
Component (Both x8 and x16 Cases Considered)
4.1
Compatible Layout for Intel's 16-Mbit (TSOP) FlashFile Component to 16-Mbit ROM Chip
(PSOP, TSOP)
4.2
Compact Layout for Intel's 16-Mbit FlashFile Component Using Standard 56-Lead TSOP Pinout
4.3
Compatible Layout for Upgrading from Four 8-Mbit (TSOP) to Two 16-Mbit (TSOP) FlashFile
Components (Both x8 and x16 Cases Considered)
4.4
Compatible Layout for Upgrading from Four 8-Mbit (TSOP) to One 32-Mbit (TSOP)
FlashFile Component (Both x8 and x16 Cases Considered)
4.5
Compatible Layout for Upgrading from Two 8-Mbit (PSOP) to One 16-Mbit (SSOP) (Both x8 and
x16 Cases Considered)
4.6
Compatible Layout for Upgrading from Two 8-Mbit (TSOP) to One 16-Mbit (SSOP) (Both x8 and
x16 Cases Considered)
4.7
Serpentine Layout for 8-Mbit FlashFile Component using Standard and Reverse 40-Lead TSOP
Pinout
4.8
Compatible Layout for Upgrading from Eight 8-Mbit (TSOP) to Two 32-Mbit (TSOP) FlashFile
Components
4.9
Compatible Layout for Upgrading from 16-Mbit (TSOP) to 16-Mbit (SSOP)
4.10
3-507
AP-607
4.2 Compatible Layout for Intel's
16-Mbit FlashFile Component to
16-Mbit ROM Chip
Three cases of layout are considered:
1. 28F016SA (56-Lead TSOP Package) to 16-Mbit
ROM (44-Lead TSOP Package) on the same side of
the board (see Figures 11-13).
2. Layout with components (56-Lead TSOP 28F016SA
to 44-Lead PSOP 16-Mbit ROM) on same side of the
board (see Figures 14-16).
3. Chips (56-Lead TSOP 28F016SA to 44-Lead PSOP
16-Mbit ROM) on opposite sides of the board (see
Section 6.0 for layout files).
For same side of the board:
Feature
Dimension
Total Layout Area
0.587" sq. (379.3 mm 2)
X,V
0.524",1.12"
(13.31 mm, 28.5 mm)
Trace Width
0.005" (0.127 mm)
Via Size
Trace to Trace Spacing
. 0.025" (0.635 mm)
0.005" (0.127 mm)
28F016SA (56-Lead TSOP) to 16-Mbit ROM (44-Lead
PSOP) opposite side:
All three cases use two layers.
Pins CEo#, WE#, 3/5#, RP#, WP# are left unconnected. With the exception of CEo # (which needs to be
grounded), connection of pins depends on the system
design parameters.
Since pin Dis/A_I acts as the 16th line of data bus
during xl6 operations, and the lowest address bit during x8 operations, it is connected to both Ao and DIs
pins on the 16-Mbit component.
Pins 29 and 30 (both NC) of 28F016SA overlap with
the pin 37 (A13) of 16-Mbit ROM in the same side of
board layout (see Figures 14-16). From a manufacturing point of view, solder paste stencil has to be optimized for appropriate volume of solder. This ensures
proper spacing between adjacent pins.
Important dimensions are given below:
28F016SA (56-Lead TSOP) to 16-Mbit ROM (44-Lead
TSOP) same side:
Feature
28F016SA (56-Lead TSOP) to 16-Mbit ROM (44-Lead
PSOP) same side:
Dimension
Feature
Dimension
Total Layout Area
0.582" sq.
(375.34 mm 2 )
X,V
0.524" , 1.11" .
(13.31 mm, 28.20 mm)
Trace Width
0.006" (0.1524 mm)
Via Size
0.04" (1.016 mm)
Trace to Trace Spacing
0.006" (0.1524 mm)
4.3 Compact Layout for Intel's 16-Mbit
FlashFile Component Using
Standard 56-Lead TSOP Pinout
Highly-dense flash chip array as compact as the serpentine layout of the 28FOO8SA is achievable with Standard 56-Lead TSOP package using three layers (see
Figures 17-20). Additionally, power and ground can
be routed on layer 1.
Total Layout Area
0.63" sq. (405.8 mm 2)
X,V
0.84" , 0.75"
(21.3 mm, 19.05 mm)
Trace Width
0.005" (0.127 mm)
Total Layout Area
2.015" sq. (1300 mm 2 )
Via Size
0.025" (0.635 mm)
X,V
Trace to Trace Spacing
0.005" (0.127 mm)
1.736",1.161"
(44.1 mm, 29.49 mm)
Trace Width
0.003" 0.0762 mm)
3-508
Important dimensions are given below:
Feature
. Dimension
Via Size
0.025" (0.635)
Trace to Trace Spacing
0.003" (0.0762 mm)
Minimum Annular Ring
0.01" (0.254 mm)
AP-S07
4.4 Compatible Layout for Upgrading
from Four 8-Mbit to Two 16-Mbit
FlashFile Components
4.6 Compatible Layout for Upgrading
from Two 8-Mbit (PSOP Packaging)
to One 16-Mbit (SSOP Packaging)
This section describes the layout solution for four
28F008SA to two 28FOI6SA/SV FlashFile components
in x8 and xl6 modes. Two layers are used to achieve
the desired compactness. Solution is obtained using layout discussed in Section 4.1 twice (see Section 6.0 for
layout files).
This layout deals with two 28F008SA (in PSOP packaging) upgraded to one 28FOI6SA/SV (in SSOP packaging) in 8-bit and 16-bit modes. Two layers are used,
with the 28FOO8SAs on layer I and the 28FOI6SA/SV
residing on layer 2 (see Section 6.0 for layout files).
Important dimensions are given below (for both x8 and
xl6 modes):
Feature
Dimension
For unconnected pin information and details concerning enabling of the chips, consult Section 4.1 (also see
schematic file 2t8tl6h.sch listed in Section 6.0).
Important dimensions are given below (for both x8 and
xl6 modes):
Total Layout Area
1.547" sq. (998 mm 2)
X,V
1.75" ,0.884"
(44.45 mm, 22.45 mm)
Total Layout Area
1.5" sq. (969 mm 2)
Trace Width
0.005" (0.127 mm)
X,V
Via Size
0.025" (0.635 mm)
1.341" , 1.12"
(34.06 mm, 28.45 mm)
Trace to Trace Spacing
0.005" (0.127 mm)
Trace Width
0.005" (0.127 mm)
4.5 Compatible Layout for Upgrading
from Four 8-Mbit to One 32-Mbit
FlashFile Component
Compact layout for upgrading from four 28F008SA to
one DD28F032SA FlashFile component in x8 and xl6
modes is considered in this section (see Section 6:0 for
layout files). Two layers are used.
Important dimensions are given below (for both x8 and
xl6 modes):
Feature
Dimension
Total Layout Area
1.48" sq. (956 mm 2)
X,V
1.75" ,0.847"
(44.45 mm, 21.5 mm)
Trace Width
0.005" (0.127 mm)
Via Size
0.025" (0.635 mm)
Trace to Trace Spacing
0.005" (0.127 mm)
Feature
Dimension
Via Size
0.025" (0.635 mm)
Trace to Trace Spacing
0.005" (0.127 mm)
.,
4.7 Compatible Layout for Upgrading
from Two 8-Mbit (TSOP Packaging)
to One 16-Mbit (SSOP Packaging)
This layout deals with two 28F008SA (TSOP packaging) to one 28FOI6SA/SV (SSOP package) in 8-bit and
16-bit modes. Two layers are used, with the 28F008SAs
and the 28FOl6SA on opposite sides of the board (see
Section 6.0 for layout files).
For unconnected pin information and details concerning enabling of the chip, consult Section 4.1.
3-509
AP-607
Important dimensions are given below (for both xS and
x16 modes):
Feature
Dimension
Total Layout Area
0.786" sq. (507 mm 2)
X,Y
0.836" ,0.94"
(21.23 mm, 23.9 mm)
Trace Width
0.005" (0.127 mm)
Via Size
0.025" (0.635 mm)
Trace to Trace Spacing
0.005" (0.127 mm)
4.8 Serpentine Layout for 8-Mbit
FlashFile Component Using
Standard and Reverse 40-Lead
TSOP Pinout
This section describes an S-Mbyte flash memory array
using TSOP packaged 2SFOOSSAs in Standard and Reverse configurations (see section 6.0 for layout files). A
layout like this is used in Intel's Series 2 flash memory
cards and provides optimum array density for available
Q.oard space. Additionally, two layers are used.
Important dimensions are given below:
Feature
Dimension
Total Layout Area
3.47" sq. (2240 mm 2)
X,Y
1.93",1.8"
(49 mm, 45.72 mm)
Trace Width
0.005" (0.127 mm)
Via Size
0.025" (0.635mm)
Trace to Trace Spacing
0.005" (0.127 mm)
4.10 Compatible Layout for Upgrading
from 16-Mbit (TSOP to 16-Mbit
(SSOP)
This layout enables easy upgrade from 56-TSOP package to 56-SS0P package. With the exception of NC
pins, all pins are connected between the two packages.
The layout uses two layers.
Important dimensions are given below:
Feature
Dimension
Total Layout Area
0.953" sq. (615 mm2)
Component RY/BY#s and CE#s are left unconnected.
X,Y
1.49",0.64"
(37.85 mm, 16.25 mm)
Important dimensions are given below:
Trace Width
0.005" (0.127 mm)
Via Size
0.025" (0.635 mm)
Trace to Trace Spacing
0.005" (0.127 mm)
Feature
Dimension
Total Layout Area
3.06" sq. (1974 mm 2)
X,Y
1.7",1.8"
(43.18 mm, 45.72 mm)
Trace Width
0.005" (0.127 mm)
Via Size
0.025" (0.635 mm)
Trace to Trace Spacing
0.005" (0.127 mm)
4.9 Compatible Layout for Upgrading
from Eight 8-Mbit to Two 32-Mbit
FlashFile Components
The serpentine layout described in Section 4.S, is used
in this solution with slight modifications. Besides performance increase, saving of more than twice the PCB
area are achievable when upgrading from 2SFOOSSA to
DD2SF032SA (see Section 6.0 for layout files). The
layout uses two layers.
3-510
5.0 DECOUPLING
To eliminate voltage variations, and thus insuring optimum performance in a high speed environment, use
of DECOUPLING capacitors is recommended for
FlashFile components. Both main and erase/write
power supplies need to be decoupled against DC drifts
and switching transients "noise."
For FlashFile components, a 0.1 ,..,F, or greater, multilayer ceramic capacitor per device is recommended.
Additional suggestions to obtain good decoupling performance include:
1. The lead length and bond lines (device to capacitor
to ground) must be kept to a minimum, since they
are a major source of inductance.
Ap·607
2. To increase path numbers (gridding) for reduced inductance and more effective surge-current availability, use one capacitor per chip. This also helps in
reducing the lead length and bond lines.
6.0 GENERAL GUIDELINES AND
METHODOLOGY FOR DESIGNING
COMPATIBLE/COMPACT LAYOUT
Much effort has been made to incorporate most of the
common layout combinations. However, for cases not
considered here, a set of general guidelines follow to
assist in developing solutions. Some of the key points
are:
1. Select packages to use.
2. Develop part decals based on dimensions provided
by respective vendors. Leave enough pads room to
allow for manufacturing tolerances.
3. Select the optimum placement of part decals after
trying different combinations.
4. To minimize manufacturing cost, use thick tracks
(0.005 inches minimum).
5. Keep via count to a minimum.
6. Use largest vias permitted by the area constraints
and process.
7. To reduce signal attenuation and noise, avoid 90·
bends in the track routing (instead, use two 45·
bends).
8. Use separate planes for ground and power. If limited
by number of layers, use thick tracks, two to three
times wider than signals track width.
As mentioned before, Gerber files are generated using
"PADS" software by Viewlogic Systems, Inc. However, OrCAD® package is used for schematic entry.
Each layout case considered consists of a minimum of
four Gerber files (Layer 1, Layer 2, Soldermask 1 and
Silkscreen 1) and one schematic file. Additional layers
or schematic files might be present in some cases (see
Table 2 for filename conventions used).
Table 2. Filename Conventions
Filename
Filenamea.'
Convention
Layer 1 (Gerber File)
Filenameb.'
Layer 2 (Gerber File)
Filenamec.'
Layer 3 (Gerber File)
Filenames.'
Silkscreen 1 (Gerber File)
Filenamet.'
Silkscreen 2 (Gerber File)
Filenamem.'
Soldermask 1 (Gerber File)
Filenamen.'
Soldermask 2 (Gerber File)
Filename?h. '
Page 1 (Schematic File)
FilenameL'
Page 2 (Schematic File)
7.0 AVAILABILITY OF FILES
Due to space constraints, the layout diagrams and ac~
companying schematics for all the cases are not included in this application note. However, they are available
through Intel's Bulletin Board Service (BBS) under the
FlashFile technology area. The number to dial is:
North America and Japan(\)
Europe
916-356-3600
+ 44-793-496340
1 When
calling from Japan, add "01" before the number listed above.
3-511
AP-607
The following is a complete list of fIles present on the BBS:
Index of Layouts/Schematics
FileName
DescriptIon
2tBxt16a.pho
Layout and schematic files for
4.1
2tBxt16b.pho
"two B-Mbit (TSOP) to one
4.1
2tBxt16m.pho
16-Mbit (TSOP) FlashFile
4.1
2tBxt16s.pho
component" in x16 mode.
4.1
2tBxt16h.sch
4.1
2tBxt10h.sch
4.1
2tBt16a.pho
Layout and schematic files for
4.1
2tBt16b.pho
"two B-Mbit (TSOP) to one
4.1
2tBt16m.pho
16-Mbit (TSOP) FlashFile
4.1
2tBt16s.pho
component" in xB mode.
2tBt16h.sch
4.1
4.1
2tBt160h.sch
t16t16sa.pho
4.1
Layout and schematic files for
4.2
t16t16sb.pho
"16-Mbit (TSOP) FlashFile
4.2
t16t16sm.pho
component to 16-Mbit ROM
4.2
t16t16ss.pho
(TSOP)" on the same side of the
4.2
t16t16sh.sch
board.
4.2
t16r16sa.pho
Layout and schematic files for
4.2
t16r16sb.pho
"16-Mbit (TSOP) FlashFile
4.2
t16r16sm.pho
component to 16-Mbit ROM
4.2
t16r16ss.pho
(PSOP)" on the same side of the
4.2
t16r16sh.sch
board.
4.2
t16r160a.pho
Layout and schematic files for
4.2
t16r160b.pho
"16-Mbit (TSOP) FlashFile
4.2
t16r160m.pho
component to 16-Mbit ROM
4.2
t16r160s.pho
(PSOP)" on the opposite sides of
4.2
t16r160n.pho
the board.
4.2
t16r160t.pho
4.2
t16r160h.sch
4.2
NOTE:
Other examples may be added over time.
3·512
Relevant Section
Ap·607
Index of Layouts/Schematics, Contd.
Description
Relevant Section
Layout and schematic files for
4.3
4t16b.pho
"compact 16-Mbit (TSOP)
4.3
4t16c.pho
FlashFile component layout"
4.3
FileName
4t16a.pho
4t16m.pho
4.3
4t16s.pho
4.3
4t16h.sch
4.3
4tBxt16a.pho
Layout and schematic files for
4.4
4tBxt16b.pho
"four B-Mbit (TSOP) to two
4.4
4tBxt16m.pho
16-Mbit (TSOP) FlashFile
4.4
4tBxt16s.pho
components" in x16 mode.
4.4
4tBxt16h.sch
4.4
4tBxt16i.sch
4.4
4tB2t16a.pho
Layout and schematic files for
4.4
4tB2t16b.pho
"four B-Mbit (TSOP) to two
4.4
4tB2t16m.pho
16-Mbit (TSOP) FlashFile
4.4
4tB2t16s.pho
components" in xB mode.
4.4
4tB2t16h.sch
4.4
4tB2t16i.sch
4.4
4tBxt32a.pho
Layout and schematic files for
4.5
4tBxt32b.pho
"four B-Mbit (TSOP) to one
4.5
4tBxt32m.pho
32-Mbit (TSOP) FlashFile
4.5
4tBxt32s.pho
component" in x16 mode.
4.5
4tBxt32h.sch
4.5
4tBxt32i.sch
4.5
4tBt32a.pho
Layout and schematic files for
4.5
4tBt32b.pho
"four B-Mbit (TSOP) to one
4.5
4tBt32m.pho
32-Mbit (TSOP) FlashFile
4.5
4tBt32s.pho
component" in xB mode.
4.5
4tBt32h.sch
4.5
4tBt32i.sch
4.5
NOTE:
Other examples may be added over time.
3-513
Ap·607
Index of. Layouts/Schematics, Contd.
FileName
Description
2p8xs16a.pho
Layout and schematic files for
4.6
2p8xs16b.pho
"two 8-Mbit (PSOP) to one
4.6
2p8xs16m.pho
16-Mbit (SSOP) FlashFile
4.6
2p8xs16s.pho
component" in x16 mode.
4.6
2p8xs16n.pho
4.6
2p8xs16t.pho
4.6
2p8xs16h.sch
4.6
2p8s16a.pho
Layout and schematic files for
4.6
2p8s16b.pho
"two B-Mbit (PSOP) to one
4.6
2pBs16m.pho
16-Mbit (SSOP) FlashFile
4.6
2pBs16s.pho
component" in xB mode.
4.6
2p8s16n.pho
4.6
2p8s16t.pho
4.6
2pBs 16h.sch
4.6
2tBxs16a.pho
Layout and schematic files for
4.7
2t8xs16b.pho
"two 8-Mbit (TSOP) to one
4.7
2t8xs16m.pho
16-Mbit (SSOP) FlashFile
4.7
2tBxs 16s.pho
component" in x16 mode.
4.7
2t8xs 16n.pho
4.7
2tBxs16t.pho
4.7
2tBxs 16h.sch
4.7
2t8s16a.pho
Layout and schematic files for
2t8s16b.pho
"two 8-Mbit (TSOP) to one
4.7
2t8s16m.pho
16-Mbit (SSOP) FlashFile
4.7
4.7
2t8s16n.pho
component" in x8 mode.
4.7
2tBs 16s.pho
4.7
2t8s16t.pho
4.7
2t8s16h.sch
4.7
NOTE:
Other examples may be added over time.
3-514
Relevant Section
Ap·607
Index of Layouts/Schematics, Contd.
Description
Relevant Section
Layout and schematic files for
4.B
BtBb.pho
"serpentine layout for B-Mbit
4.B
BtBm.pho
(TSOP) FlashFile component."
4.B
FileName
BtBa.pho
BtBs.pho
4.B
BtBh.sch
BtB2t32a.pho
4.B
Layout and schematic files for
4.9
BtB2t32b.pho
"eight B-Mbit (TSOP) to two
4.9
BtB2t32m.pho
32-Mbit (TSOP) FlashFile
4.9
BtB2t32s.pho
components" in xB mode.
4.9
BtB2t32h.sch
4.9
BtB2t32i.sch
4.9
Layout and schematic files for
4.10
t16s16b.pho
"one 16-Mbit (TSOP) to one
4.10
t16s16m.pho
16-Mbit (SSOP) FlashFile
4.10
t16s16s.pho
component."
t16s16a.pho
t16s16h.sch
4.10
4.10
NOTE:
Other examples may be added over time.
3-515
AP·607
8.0 SUMMARY
9.0 ADDITIONAL INFORMATION
This application note summarizes highly-dense layout
solutions, based on the design constraints such as compatibility and compactness. Different permutations of
FlashFile components and 16-Mbit ROM are provided.
Furthermore, compact layouts for 16-Mbit array are
designed and· found to be comparable in PCB layout
area to the serpentine layout. This application note,
however, does not deal with software changes associated with compatibility issues. See AP-375, "Upgrade
Considerations from the 28FOO8SA to the 28F016SA"
and AP-393, "28F016SV Compatibility with
28F016SA" for more information on the subject.
For software upgrade and additional design information, consult the referenced documents listed below:
Document
Order Number
297372
"28F016SA 16-Mbit FlashFile™ User's Manual"
290490
DD28F032SA Datasheet
290489
28FO 16SA Datasheet
290528
28F016SV Datasheet
290429
28F008SA 8-MB (1 MB x 8) FlashFile™ Memory Datasheet
292095
AP-360, "28F008SA Software Drivers"
292097
AP.362, "Implementing Mobile PC Designs using High-Density FlashFile™ Components"
292124
AP-375, "Upgrade Considerations from the 28F008SA to the. 28F016SA"
292126
AP-377, "The 28F016SA Software Drivers"
292127
AP-378, "System Optimization using Enhanced Features of the 28F016SA"
292144
AP-393, "28F016SV Compatibility with 28F016SA"
294011
ER-27, "The Intel 28F008SA Flash Memory"
294016
ER-33, "ETOXTM IV Flash Memory Technology: Insight to Intel's Fourth Generation
Process Innovation"
3-516
AP-607
APPENDIX A
FIGURES
A19
Ala
A17
A1S
A15
A14
A13
A12
CE#
Vee
Vpp
RP#
All
AlO
Ag
As
A7
As
A5
A4
NC
NC
WE#
OE#
RY/BY#
D0 7
DOs
D05
D0 4
Vee
GND
GND
D0 3
0°2
DOl
DO o
Ao
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
40
39
38
37
36
35
STANDARD PINOUT
E28FOO8SA
4O-Lead TSOP
10mm x 20 mm x 1.2mm
TOP VIEW
34
33
32
31
30
29
2S
27
26
25
24
23
22
21
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0
REVERSE PINOUT
F28FOO8SA
4D-Lead TSOP
10mm x 20 mm x 1.2mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
WE#
OE#
RY/BY#
D0 7
DOs
D0 5
D0 4
Vee
GND
GND
D0 3
D0 2
DOl
DO o
Ao
Al
A2
A3
A19
Ala
A17
A1S
A15
A14
A13
A12
CE#
Vee
Vpp
RP#
All
AlO
Ag
Aa
A7
As
A5
A4
292159-2
Figure 2. 28F008SA Standard and Reverse 40-Lead TSOP Pinout Configuration
3-517
AP-607
Vpp
RP#
A11
AlO
A9
As
A7
As
A5
A4
NC
NC
A3
A2
A,
Ao
DQ o
DQ,
DQ 2
DQ 3
GND
GND
10
2
3
4
5
Vee
18
19
20
21
CE#
A'2
A'3
A'4
A'5
A,s
A'7
A,s
A'9
NC
NC
NC
NC
WE#
OE#
RYIBY#
DQ 7
DQ s
DQ 5
DQ 4
22
Vee
6
7
8
41
PA28FOO8SA
44-Lead PSOP
9 16mm x 28mm x 3.05mm36
10
35
TOP VIEW
11
34
12
33
13
32
14
31
15
16
17
292159-3
Figure 3. 28F008SA 44-Lead PSOP Pinout Configuration
28F032SA 28F016SA
~
20
A,.
A,s
An
A,.
Vee
A,s
A,.
A'3
A'2
CEoll
Vpp
RP#
A"
A,o
A.
As
GND
A7
Aa
As
A.
Aa
A2
A,
~
'20
A,.
A,s
An
A,.
Vee
A,s
A,.
A'3
A,2
CEo#
Vpp
RP#
A"
A10
A.
As
GND
A7
Aa
As
A.
A3
A2
A,
28F016SA 28F032SA
NC
CE,#,
NC
A20
A,.
A,s
A'7
A,a
Vee
A,s
A,.
A'3
A'2
CEo'
Vpp
RP#
A"
A10
A.
As
GND
A7
A.
As
A.
A3
A2
A,
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
0
28F016SV
56-LEAD TSOP PINOUT
14mm x 20mm x 1.2mm
TOP VIEW
WP#
WEll
OE#
RY/BY#
DO,s
D07
DO'4
DO a
GND
DO'3
DOs
DO'2
DO.
Vee
GND
DO"
D03
DOlO
D02
Vee
DO.
DO,
DOs
DO o
Ao
BYTE#
NC
NC
WP#
WEI
OEII
RYIBY
DO,s
D0 7
DO,.
DOa
GND
DO'3
DOs
DO'2
DO.
Vee
GND
DO"
D03
DO,o
D02
Vee
DO.
DO,
DOs
DO o
Ao
BYTE#
NC
NC
WP#
WEI
OE#
RYIBY#
DO,s
D0 7
DO,.
DO a
GND
DO'3
DOs
DO'2
DO.
Vee
GND
DO"
DO a
DO,o
D0 2
Vee
DO.
DO,
DOs
DO o
Ao
BYTEII
NC
NC
292159-4
Figure 4. 28F016SA, 28F016SV and DD28F032SA 56-Lead TSOP Pinout Configurations
3-518
AP-607
28F016SV
cEo#
A,2
A,3
A,4
A,s
@)
0
cEo#
Vpp
RlP#
A11
A,o
A'2
A,3
A,4
A,s
As
3/5#
A,
CE,#
NC
A20
CE,#
NC
A'9
A,a
A'9
A,a
A17
A'7
28F016SV
Vpp
RIP#
A"
A,o
A9
A,
A2
A2
A3
A4
A3
A4
10
As
As
11
As
As
A7
A7
GND
GND
Aa
Vee
AB
A20
DAlDT28F016SA
56-LEAD SSOP
STANDARD PINOUT
A'6
A'6
13
Vee
Vee
14
GND
D0 6
GND
D0 6
15
16
D0 9
DOg
DO'4
D0 7
DO'4
D0 7
17
18
DO,
DO B
DO,s
DO,s
19
DO o
DQ,
DO a
DO o
RY/BY#
OE#
RY/BY#
OE#
Ao
BYTE#
Ao
BYTE#
WE#
WP#
WE#
WP#
NC
NC
NC
NC
DO'3
DO'3
DOs
D0 2
D0 2
DOs
DO'2
D04
DO'2
D04
DOlO
D0 3
DO,o
D0 3
Vee
Vee
D0 11
GND
D0 11
GND
16mm x 23.7mm x 1.8mm
TOP VIEW
31
Vee
292159-5
Figure 5. 28F016SA/SV 56-Lead SSOP Pin Configuration
3·519
Ap·607
NC
A 1S
A17
A7
Ae
As
A4
A3
A2
Al
Ao
CE#
GNO
OE#
00
Os
01
Og
O2
0 10
03
0 11
10
2
3
4
5
6
7
16-MbltROM
8
44-Lead PSOP
9 16mm X 28mm X 3mm
10
TOP VIEW
11
12
13
14
15
16
17
18
19 .
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A 19
As
Ag
A 10
All
A12
A 13
A14
A 1S
Ale
BYTE#
GNO
°ls /A _l
D7
014
Oe
013
Os
012
04
Vee
292159-6
Figure 6. 16-Mbit ROM Chip 44-Lead PSOP Pinout Configuration
NC
A 1S
A17
A7
A&
As
A4
A3
A2
Al
Ao
CE#
GNO
OE#
10
NC
2
A 19
3
4
5
,6
7
8
9
As
Ag
A 10
All
10
11
16-MbltROM
44-Lead TSOP
18.8mm x 11.7Smm
x1.2mm
TOP VIEW
A12
A 13
A14
A 1S
A 1&
BYTE#
GNO
Os
12
13
14
15
16
01
17
0&
Og
18
19
20
21
22
00
O2
0 10
03
0 11
°ls /A _l
07
014
013
05
012
04
Vee
292159-7
Figure 7. 16-Mblt ROM Chip 44-Lead TSOP Pinout Configuration
3-520
AP-607
-----------
-
E28FOO8SA
>
en
<
""
en
0
LL.
CO
N
L.&J
F28FOO8SA
111111111111111111111111111
-----------
292159-8
Figure 8. 4x Scale Topside Outline View of Two 2BFOOBSAs to One 2BF016SA/SV (x 16 Mode)
3-521
AP-607
••
.---......
-==
292159-9
Figure 9. 4x Scale Topside Trace View of Two 2BFOOBSAs to One 2BF016SA/SV (x16 Mode)
3·522
AP-607
--=
-----------
~~.I".I.I
•
_ ----.",
~
11111111111111111111111111 ~
292159-10
Figure 10. 4x Scale Bottom Side Trace View of Two 28F008SAs to One 28F016SA/SV (x 16 Mode)
3-523
AP-607
---_ ....--1========10--..;....----=
---=
=
=
-
--===
-
=
a..
0
en
I-
....
....
....
I
...
:I
0
:::E
-
--==
-=
-
_
=
CO
292159-11
Figure 11. 3x Scale Top Side Outline View of One 28F016SA/SV (56-Lead TSOP)
to One 16-Mbit ROM (44-Lead TSOP)
292159-12
Figure 12. 3x Scale Top Side Trace View of One 28F016SA/SV (56-Lead TSOP)
to One 16-Mblt ROM (44-Lead TSOP)
.
3·524
_I
•-n+'e'®
AP-607
- =
=~
-
i~1~~~~§~
=:E_~
-=
-- _.-!::::::IIC:;:='-
- -
-
-- ----
---/''/
292159-13
Figure 13. 3x Scale Bottom Side Trace View of One 28F016SA/SV(56-Lead TSOP)
to One 16-Mbit ROM (44-Lead TSOP)
3-525
AP-607
11111111111111111111111111
16M ROM
>
en
.........
<
en
~
....oco
N
.....
1111111111111111111111111111
292159-14
Figure 14. 3x Scale Top Side Outline View of One 28F016SA/SV (56-Lead TSOP)
to One 16-Mblt ROM (44-Lead PSOP)
3-526
AP-607
....
.--- .... ...-...
."
..- ..
-
.....-
~
292159-15
Figure 15. 3x Scale Top Side Trace View of One 28F016SA/SV (56-Lead TSOP)
to One 16-Mbit ROM (44-Lead PSOP)
3-527
AP-607
--
--
-----IIIIIIIIIIIIIIIIIIIIIIIIIIH---=,
=
------------=1 =
1111111111111111111111111111
292159-16
Figure 16_ 3x Scale Bottom Side Trace View of One 28F016SA/SV (56-Lead TSOP)
to One 16-Mblt ROM (44-Lead PSOP)
3-528
AP-607
-------------------
E28F016SA/SV
E28F016SA/SV
--------------------
---------------------
E28F016SA/SV
E28F016SA/SV
-------------------
292159-17
Figure 17. 3x Scale Top Side Outline View of Four 28F016SA/SVs
3·529
AP·607
=.
a..
..=
•• =
••..=
=
.
..
= ••
=
-- •• •
.•.--=--=.=-=
.-==s
-==. ..••
-==--..
-=. .
~
fl.---=:
•• .......==
;:::::;...
~.
=-. •
-=
=..
...
-:::::-=--.
..
=.
.
-=-=---.
••
-~.
-=-=-..
§r.
..
§v-. •••
~
~.
§~ •••
~
==~
•••
.• ..=.=-=
-.;;:::
•.fl. ==
•...=-=
~
292159-18
Figure 18. 3x Scale Top Side Trace View of Four 28F016SAISVs
3-530
..••..===
AP-S07
292159-19
Figure 19. 3x Scale Internal Layer View of Four 28F016SA/SVs
3-531
Ap·607
--=.
=
== ..
••..
--=
..
.
=.
=
..
==
••
--==== ••.....
= ..
• •••
- -
--
-
.....,...=--=
-=
...=
.==
••.=
...
.=
.. --=
..=.
292159-20
Figure 20. 3x Scale Bottom Side Trace View of Four 28F016SAISVs
3-532
int'et
AP-393
APPLICATION
NOTE
28F016SV
Compatibility with
28F016SA
BRIAN DIPERT
SENIOR TECHNICAL
MARKETING ENGINEER
SUJAN KAMRAN
TECHNICAL MARKETING
ENGINEER
KEN MCKEE
TECHNICAL MARKETING
ENGINEER
November 1994
1
6.\[Q)\YI6.\OO©[§ OOOIF@ImIMl6.\'U'O@OO
Order Number: 292144-002
3-533
AP-393
1.0 INTRODUCTION
2.0 COMPATIBILITY
This application note discusses compatibility between
the 28F016SV and 28F016SA FlashFile™ memory
components. It also offers recommendations for designing systems using the 28F016SA today, when future
conversion to the 28FOl6SV is planned.
The 28F016SV and 28F016SA are both manufactured
on Intel's fourth-generation 0.6 micron ETOXTM-IV
process technology. This technology enables random
access flash memory products with the highest read/
write performance and lowest power consumption.
ETOX flash memory technology also achieves very
high quality and reliability.
The 28F016SV is a member of Intel's second-generation 16-Mbit FlashFile component product family. It
improves upon the 28F016SA in the following areas:
• SmartVoltage technology
- Selectable 5.0V or 12.0V Vpp
• Faster read performance
• Higher Page Buffer write performance at 12.0V Vpp
• Enhanced device feedback after writing the Upload
Device Information command
• Enhanced 3.3V or 5.0V Vee detection
• Additional RY/BY# Configuration
- Pulse-On-Write/Erase
The following sections discuss specific areas of compatibility between' the 28F016SV and the 28F016SA.
Please reference the documentation listed in the Additional Information section of this application note fora
full description of these flash memory components.
2.1 Pinout and Package
The 28F016SV is fully pinout backwards-compatible
with the 28F016SA (see Figures 1 and 2). Both devices
will be available in 56-lead TSOP and SSOP packages.
28F016SA 28F032SA
2BF032SA 28F016SA
ij ~
C # C ,#
NC
CEo
A20
20
A,.
A,.
A,.
Am
A'7
A'7
A,.
A,.
Vee
Vee
A'5
A'5
A,.
A,.
A'3
A'3
A'2
A'2
CEo# CEo#
Vpp
Vpp
RP#
RP#
A"
A"
A10
A10
A.
A.
A.
A.
GND GND
A7
A7
A.
A.
A5
A5
A.
A.
A3
A3
A2
A2
A,
A,
NC
CE,#
NC
A20
A,.
A,.
An
A,.
Vee
A'5
A,.
A'3
A'2
CEo#
Vpp
RP#
A"
A10
A.
A.
GND
A7
A.
A5
A4
A3
A2
A,
1
2
3
4
5
6,
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
0
E28F016SV
56· LEAD TSOP PINOUT
14mmx20mm
TOP VIEW
WP#
WE#
OE#
RYIBY#
00'5
007
DO,.
DO.
GND
00'3
DO.
00'2
DO.
Vee
GND
DO"
00 3
00'0
00 2
Vee
DO.
DO,
DO.
00 0
Ao
BYTE#
NC
NC
WP#
WE#
OE#
RYIBY
00'5
007
DO,.
DO.
GND
00'3
DO.
00'2
Do..
Vee
GND
DO"
00 3
0010
00 2
Vee
DO.
DO,
DO.
00 0
Ao
WP#
WE#
OE#
RYIBY#
00'5
007
DO,.
DO.
GND
00'3
DO.
00'2
DO.
Vee
GND
DO"
00 3
0010
002
Vee
DO.
DO,
DO.
00 0
Ao
BYTE# BYTE#
NC
NC
NC
NC
292144-1
Figure 1. 28F016SV 56-Lead TSOP Pinout Compared to the 28F016SA and 28F032SA
3-534
intel®
AP-393
28F016S,
CEc,#
CEc,#
A'2
A'3
A,.
A'2
A'3
A,.
~
A
A,s
NC
CE,#
NC
A 20
CE,#
NC
A 20
28F016SA
0
v pp
vpp
RlP#
R/P#
A"
A10
Ag
A"
A10
Ag
A,
A,
A2
A3
A.
A2
A3
A4
A,g
A,g
As
As
A,s
A,s
As
As
A'7
A'7
A7
A7
A'6
Vee
GND
D0 6
A'6
Vee
GND
GND
DO,.
GND
D0 6
DO,.
D0 7
D0 7
DA28F016SV
56-LEAD SSOP
STANDARD PINOUT
16mmx23.7mm
TOP VIEW
As
As
Vce
Vec
DOg
DOg
DO,
DO o
DO,
DO a
DO o
Ao
BYTE#
Ao
BYTE#
WE#
WP#
NC
NC
NC
DO'3
DOs
DO'3
DOs
D02
D0 10
DO'2
DO.
DO'2
DO.
D0 3
DO,o
D0 3
Vee
Vee
DO"
GND
DO"
GND
DO,s
DO,s
RY/BY#
OE#
RYIBY#
OE#
WE#
WP#
DOs
NC
D02
292144-2
Figure 2. 28F016SV 56-Lead SSOP Pinout Compared to the 28F016SA
The 28F016SA uses the 3/5 # pin to configure the flash
memory for operation at 3.3V or 5.0V Vee. The
28FO 16SV uses an internal detector connected to the
Vee pin to accomplish this same function. The 3/5#
pin is no longer needed on the 28F016SV and has been
renamed NC ("no connect"). This pin may be left driven to VIL or VIH, or may be left unconnected. Therefore, a design that uses the 28F016SA today can later
convert to the 28F016SV and continue to drive the former 3/5# pin, eliminating costly system board redesigns.
3-535
AP-393
2.2 Bus Operations
The 28FOI6SV shares the same bus operations as the
28FOI6SA, and both flash memories operate identically
in these operating modes.
2.3 Command Definitions
The 28FOI6SV shares the same command set as the
28FOI6SA. All commands produce compatible internal
operations for both flash memories.
The 28FOI6SV includes an additional RY/BY# mode,
RY/BY # Pulse on WritelErase, enabled as part of the
RY/BY# Configuration (96H) command sequence.
This mode was Reserved for Future Use on the
28FOI6SA.
The 28FOI6SV also enhances the device feedback after
writing the Upload Device Information (99H) command sequence. It outputs not only the Device Revision Number (compatible with the 28FOI6SA), but the
Device Proliferation Code and Device Configuration
Code. See Section 2.5 for more information on these
topics.
2.4 Status Registers
The 28FOI6SV and 28FOI6SA both have a Compatible
Status Register (CSR), Global Status Register (GSR)
and 32 Block Status Registers (BSRs). Register address
maps for both flash memories are identical.
Compatible Status Register
CSR bits 4 _ 7 have identical functions for both the
28FOI6SV and the 28FOI6SA. CSR bits 0_2 are
marked "reserved for future use" for both the
28FOl6SV and 28FOI6SA.
3-536
CSR bit 3 (Vpp Status) has been functionally enhanced
on the 28FOI6SV, reflective of the ability to Data Write
and Erase with Vpp = 5.0V ± 10% (VPPHl) or Vpp =
12.0V ± 5% (VPPH2). See Section 2.7 for more information on 28FOl6SV Data Write and Erase. CSR.3 =
"I"js defined as "Vpp Error" on the 28FOI6SV, versus
"Vpp Low" on the 28FOI6SA. If Data Write or Erase
is initiated with Vpp = VPPH2, subsequent Vpp transitions above VpPH2(max) or below VppH2(min) will, if
detected, terminate the operation in progress and set
CSR.3 to "I" (this functionality matches the
28FOI6SA). Additionally, if Data Write or Erase is initiated with Vpp = VpPHl> subsequent Vpp transitions
above VpPHl(max) or below VpPH1(min) will, if detected, also terminate the operation in progress and set
CSR.3 to "1." See Table 1 for the 28FOI6SV's Compatibile Status Register.
Global Status Register
All GSR bits have identical functions for both the
28FOI6SV and the 28F016SA.
Block Status Registers
BSR bits 3-7 have identical functions for both the
28FOl6SV and the 28FOI6SA. BSR bit 0 is marked
"reserved for future use" for both the 28FOl6SV and
'
the 28FOI6SA.
BSR bit 2 (Vpp Status) has been functionally enhanced
on the 28FOl6SV compared to the 28F016SA. See the
earlier description of CSR.3 for more information.
BSR bit I, marked "reserved for future use" on the
28FOI6SA, is the Vpp Level bit on the 28FOI6SV.
BSR.I reflects the Vpp level applied to the 28FOl6SV
(VPPHI = "1," VPPH2 = "0"). See Table 2 for the
28FOI6SV's Block Status Register.
AP-393
Table 1. 28F016SV Compatible Status Register
WSMS
ESS
ES
DWS
VPPS
R
7
6
5
4
3
2
CSR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
R
R
o
NOTES:
The RY /BY # output or WSMS bit must be checked to
determine completion of an operation (erase suspend,
erase or data write) before the appropriate Status bit (ESS,
ES or DWS) is checked for success.
CSR.6 = ERASE-SUSPEND STATUS
1 = Erase Suspended
o = Erase In Progress/Completed
CSR.5 = ERASE STATUS
1 = Error In Block Erasure
o = Successful Block Erase
If DWS and ES are set to "1" during an erase attempt, an
improper command sequence was entered. Clear the CSR
and attempt the operation again.
CSR.4 == DATA·WRITE STATUS
1 = Error in Data Write
o = Data Write Successful
CSR.3 = Vpp STATUS
1 = Vpp Error Detect, Operation Abort
O=VppOK
The VPPS bit, unlike an A/D converter, does not provide
continuous indication of Vpp level. The WSM periodically
interrogates Vpp's level only after the data·write or erase
command sequences have been entered, and informs the
system if it detects an invalid voltage. VPPS is not
guaranteed to report accurate feedback between
VpPLK(max) and VPPH1 (min), between VPPH1 (max) and
VpPH2(min) and above VpPH2(max).
CSR.2 - CSR.O = RESERVED FOR FUTURE ENHANCEMENTS.
These bits are reserved for future use; mask them out when polling the CSR.
3·537
AP·39a
Table 2. 28F016SV Block Status Register
BS
BLS
BOS
BOAS
as
VPPS
7
6
5
4
3
2
BSR.7 = BLOCK STATUS
1 = Ready
0= Busy
VPPL
R
o
NOTES:
The RY /BY # output or BS bit must be checked to
determine completion of an operation (block lock,
suspend, erase or data write) before the appropriate
Status bits (BOS or BLS) is checked for success.
BSR.6 = BLOCK·LOCK STATUS
1 = Block Unlocked for Write/Erase
= Block Locked for Write/Erase
o
BSA.5 = BLOCK OPERATION STATUS
1 = Operation Unsuccessful
o = Operation Successful or Currently Running
BSA.4 = BLOCK OPERATION ABORT STATUS
1 = Operation Aborted
o = Operation Not Aborted
MATRIX 5/4
o 0 = Operation Successful or Currently Running
o 1 = Not a valid combination
1 0 = Operation Unsuccessful
1 1 = Operation Aborted
The BOAS bit will not be set until GSA. 7 = 1.
Operation halted via abort command.
BSR.3 = QUEUE STATUS
1 = Queue Full
o = Queue Available
BSR.2 = Vpp STATUS
1 = Vpp Error Detect, Operation Abort
0= VppOK
BSR.1 = Vpp LEVEL
1 = Vpp detected at 5.0V ± 10% (4.5V - 5.5V)
o = Vpp detected at 12.0V ± 5% (11.4V- 12.6V)
BSA. t is not guaranteed to report accurate feedback
between the VPPH1 and VPPH2 voltage ranges. Writes
and erases with Vpp between VpPLK(max) and
VpPH1(min), between VpPH1(max) and VpPH2(min),
and above VpPH2(max) produce spurious results and
should not be attempted.
BSA.1 was a RESERVED bit on the 28F016SA.
BSA.O = RESERVED FOR FUTURE ENHANCEMENTS
This bit is reserved for future use; mask it out when polling the BSR.
3-538
AP-393
Table 3. 28F016SV Device Configuration Code
R
R
R
R
R
RB2
7
6
5
4
3
2
DCC.2-DCC.0 = RY/BY# CONFIGURATION
(RB2-RBO)
001 = Level Mode (Default)
010 = Pulse·On-Write
011 = Pulse·On-Erase
100 = RY IBY # Disabled
101 = RY IBY # Pulse·on-Write/Erase
DCC.7-DCC.3 = RESERVED FOR FUTURE
ENHANCEMENTS
RB1
RBO
o
I
NOTES:
Undocumented combinations of RB2-RBO are reserved by
Intel Corporation for future implementations and should
not be used.
These bits are reserved for future use; mask them out
when reading the Device Configuration Code. Set these
bits to 0 when writing the desired RY IBY # configuration
to the device.
2.5 Device/Manufacturer IDs and
Device Configuration Cede
The 28FOl6SV shares the identical manufacturer and
device identifiers as the 28FOI6SA, for full backwardscompatibility.
The 28FOl6SV retains the Device Revision Number of
the 28FOI6SA, accessed via the Page Buffer after writing the Upload Device Information (99H) command
sequence. The 28FOl6SV adds a Device Configuration
Code, located at address IEH in byte mode and address
OFH in word mode (lower 8 bits of 16-bit word), which
allows system software to read the currently-configured
28FOl6SV RY /BY # mode. These data bits correspond
to the bits written to the 28FOl6SV when configuring
RY/BY# via the RY/BY Configuration (96H) command sequence. Unused bits of the Device Configuration Code are marked "reserved for future use" and
should be masked out. See Table 3 for the 28F016SV's
Device Configuration Code.
The 28FOl6SV also adds the Device Proliferation Code
(OIH), located at address WH in byte mode and address OFR in word mode (upper 8 bits of 16-bit word).
This code allows software identification of the
28FOl6SV versus the 28FOl6SA (described in Section
4.0).
2.6 !Flowcharts
All 28FOl6SV and 28FOl6SA flowcharts are identical.
2.7 Vpp Voltage
The 28FOI6SV's Vpp Write/Erase voltage specifications offer the choice of either 5.0V ± 10%
(4.5V-5.5V) or 12.0V ±5% (11.4V-12.6V) operation
during flash memory update. Vpp = 5.0V (VPPHl)
minimizes required chip count in designs where a suitable 12.0V supply is not already required for other system circuitry. Vpp = 12.0V (VPPH2), on the other
hand, provides significantly faster write and erase performance for applications that frequently alter flash
memory contents, such as solid-state mass storage designs.
Tables 4-7 give write and erase specifications for the
28FOl6SV at Vcc=3.3V/5.0V and at Vpp=5.0V/
12.0V. Performance numbers for erase and standard
writes at 3.3V Vccl12.0V Vpp (Table 5) and S.OV
Vccl12.0V Vpp (Table 7) match those of the
28FOI6SA. Page Buffer writes are higher performance
on the 28FOl6SV compared to the 28FOI6SA.
3-539
AP-393
Table 4. Write/Erase Performance(3,4)
Vee = 3.3V ±0.3V, Vpp = S.OV ±O.SV, TA =O·C to +70·C
Parameter
Notes
Min
Typ(1)
Max
Unit
Page Buffer Byte Write Time
2
TBD
6.0
TBD
IJ-s
Page Buffer Word Write Time
2
TBD
12.1
TBD
IJ-s
Byte Write Time
2
TBD
16.5
TBD
IJ-s
Word Write Time
2
TBD
24.0
TBD
IJ-s
Test Conditions
Block Write Time
2
TBD
1.1
TBD
sec
Byte Write Mode
Block Write Time
2
TBD
0.8
TBD
sec
Word Write Mode
Block Erase Time
2
TBD
1.4
TBD
sec
Full Chip Erase Time
2
TBD
44.8
TBD
sec
Table 5. Write/Erase Performance(3,4)
Vee = 3.3V ±0.3V, Vpp = 12.0V ±0.6V, TA = O·C to +70"C
Notes
Min
Typ(1)
Max
Unit
Page Buffer Byte Write Time
2
TBD
2.2
TBD
IJ-s
Page Buffer Word Write Time
2
TBD
4.4
TBD
IJ-s
Word/Byte Write Time
2
5
9
TBD
IJ-s
Block Write Time
2
TBD
0.6
2.1
sec
Byte Write Mode
Block Write Time
2
TBD
0.3
1.0
sec
Word Write Mode
Block Erase Time
2
0.3
0.8
10
sec
Full Chip Erase Time
2
TBD
25.6
TBD
sec
Parameter
3·540
Test Conditions
AP-393
Table 6. Write/Erase Performance(3,4)
Vee
= S.OV ±O.SV, S.OV ±0.2SV, Vpp = S.OV ± O.SV, TA = O°C to +70°C
Notes
Min
Typ(1)
Max
Unit
Page Buffer Byte Write Time
2
TBD
6.0
TBD
)Jos
Page Buffer Word Write Time
2
TBD
12.1
TBD
)Jos
Byte Write Time
2
TBD
11
TBD
)Jos
Word Write Time
2
TBD
16
TBD
)Jos
Block Write Time
2
TBD
0.8
TBD
sec
Byte Write Mode
Word Write Mode
Parameter
Block Write Time
2
TBD
0.6
TBD
sec
Block Erase Time
2
TBD
1.0
TBD
sec
Full Chip Erase Time
2
TBD
32.0
TBD
sec
Test Conditions
Table 7. Write/Erase Performance(3,4)
Vee
= S.OV ±O.SV, S.OV±O.2SV, Vpp = 12.0V ± 0.6V, TA = O°C to +70°C
Parameter
Notes
Min
Typ(1)
Max
Unit
Page Buffer Byte Write Time
2
TBD
2.1
TBD
)JoS
Page Buffer Word Write Time
2
TBD
4.1
TBD
)Jos
Word Byte/Write Time
2
4.5
6
TBD
)Jos
Block Write Time
2
TBD
0.4
2.1
sec
Byte Write Mode
Block Write Time
2
TBD
0.2
1.0
sec
Word Write Mode
Block Erase Time
2
0.3
0.6
10
sec
Full Chip Erase Time
2
TBD
19.2
TBD
sec
Test Conditions
NOTES:
1. 25'C and nominal voltages.
2. Excludes system-level overhead.
3. These performance numbers are valid for all speed versions.
4. Sampled, not 100% tested. Guaranteed by design.
2.8 Other Voltage and Current
Specifications
The 28F016SV's typical and maximum Vee read and
Vee standby (CMOS levels) currents are both higher
than those of the 28F016SA.
The 28F016SV's typical Vee Deep Power-Down current is higher than that of the 28F016SA. The
28F016SV will also exhibit higher Vee current "peaks"
in deep power-down mode at 3.3V Vee, compared to
the 28F016SA.
The 28F016SV adds the VpPHl (Vpp = S.OV) write!
erase voltage specification and Vee and Vpp write and
erase current specifications at VPP = VPPHI. Write!
erase current specifications at VPP = VPPH2 (12.0V)
match those of the 28F016SA. The 28F016SV also lowers the VPPL specification from 6.SV to l.SV (to allow
SmartVoltage operation) and renames this specification
as VpPLK, to signify the change. The 28FOI6SV's
Vee/Vpp erase suspend currents and VPP read current
(Vpp > Vec) are lower than those of the 28F016SA.
Tables 8 and 9 show added and revised (as compared to
the 28F016SA) 28F016SV DC specifications.
3-541
AP-393
Table 8. 28F016SV Added/Revised DC Characteristics for 3.3V Operations
Vee = 3.3V ±0.3V, TA = O°C to +70·C
Symbol
Typ
Max
Unit
Iccs
Vcc Standby Current
Parameter
Min
70
130
p.A
Vcc = Vcc Max,
CEo#,CE1#,RP# = Vcc ±0.2V
BYTE # , WP# = Vcc ±0.2V
orGND ±0.2V
Test Condition
ICCD
VccDeep Power-Down
Current
2
5
p.A
RP#
ICCRl
Vcc Read Current
40
50
rnA
Vcc = Vcc Max
CMOS:CEo#,CE1# = GND ±0.2V
BYTE# = GND ±0.2Vor Vce ±0.2V
Inputs = GND ± 0.2V or Vee ± 0.2V
TTL: CEo#, CEl # = VIL,
BYTE # = VIL or VIH
INPUTS = VIL or VIH,
f = 8 MHz, lOUT = 0 rnA
leeR2
Vee Read Current
20
30
rnA
Vee = Vee Max
CMOS: CEo#, CEl # = GND ±0.2V
BYTE# = GND ±0.2VorVee ±0.2V
Inputs = GND ±0.2VorVee ±0.2V
TTL: CEo#, CEl # = VIL,
BYTE# = VILorVIH
INPUTS = VIL or VIH,
f = 4 MHz, lOUT = 0 rnA
leew
Vee Write Current
8
17
rnA
Word/Byte Write in Progress
Vpp = 5.0V ±10%
lecE
Vee Block Erase Current
9
17
rnA
Block Erase in Progress
Vpp = 5.0V ± 10%
lecES·
Vee Erase Suspend
Current
1
4
rnA
CEo#, CEl # = VIH
Block Erase Suspended
=
GND ±0.2V
IpPR
Vpp Read Current
30
50
p.A
Vpp> Vee
Ippw
Vpp Write Current
15
25
rnA
Vpp = 5.0V ±10%
Word/Byte Write in Progress
IpPE
Vpp Erase Current
14
20
rnA
Vpp = 5.0V ± 10%
Block Erase in Progress
IpPES
Vpp Erase Suspend Current
30
50
p.A
Vpp = VpPHl or VPPH2,
Block Erase Suspended
VPPLK
Vpp Erase/Write Lock Voltage
0.0
1.5
V
VpPHl
Vpp during Write/Erase
Operations
4.5
5.5
V
3-542
5.0
Ap·393
Table 9. 28F016SV Added/Revised DC Characteristics for S.OV Operations
Vee = 5.0V ±0.5V, 5.0V ±0.25V, TA = O°C to +70"C
Symbol
Parameter
Min Typ
Max
Unit
Test Condition
Iccs
Vcc Standby Current
70
130
/loA
Vcc = Vcc Max
CEo#, CE1 #, RP# = Vcc ±0.2V
BYTE#, WP# = Vcc ±0.2V
orGND ±0.2V
ICCD
Vcc Deep Power· Down
Current
2
5
/loA
RP# = GND ±0.2V
ICCR1
Vcc Read Current
75
95
rnA
Vcc = Vcc Max,
CMOS: CEo#, CE1 # = GND ± 0.2V
BYTE# = GND ±0.2VorVcc ±0.2V
Inputs = GND ±0.2VorVcc ±0.2V
TTL: CEo#, CE1 # = VIL,
BYTE# = VIL or VIH
Inputs = VIL or VIH,
f = 10 MHz, lOUT = 0 rnA
ICCR2
Vcc Read Current
45
55
rnA
Vcc = Vcc Max,
CMOS:CEo#,CE1# = GND ±0.2V
BYTE# = GND ±0.2VorVcc ±0.2V
Inputs = GND ±0.2VorVcc ±0.2V
TTL: CEo #, CE1 # = VIL,
BYTE# = VIL or VIH
Inputs = VIL or VIH,
f = 5 MHz, lOUT = 0 rnA
Iccw
Vcc Write Current
25
40
rnA
Word/Byte in Progress
Vpp = 5.0V ± 10%
ICCE
Vcc Erase Suspend Current
20
30
rnA
Block Erase in Progress
Vpp =.5.0V ±10%
ICCES
Vcc Block Erase Current
2
4
rnA
CEo#, CE1 # = VIH
Block Erase Suspended
Vpp> Vcc
IpPR
Vpp Read Current
30
50
Ippw
Vpp Write Current
17
22
/loA
rnA
IpPE
Vpp Block Erase.Current
16
20
rnA
Vpp = 5.0V ± 10%
Block Erase in Progress
IpPES
Vpp Erase Suspend Current
30
50
/loA
Vpp = VpPH1 or VPPH2
Block Erase Suspended
VPPLK
Vpp Write/Erase Lock Voltage
0.0
1.5
V
VpPH1
Vpp during Write/Erase·
Operations
4.5
5.5
V
5.0
Vpp = 5.0V ±10%
Word/Byte Write in Progress
3-543
AP-393
2.9 Read Timing Specifications
The 28FOl6SV "bin I" significantly improves many
read specifications compared to the 28F016SA. At 3.3V
Vee, read performance is almost 2x that of "bin 2".
Tables 10 and II show these improved specifications.
Table 10. Improved AC Read Timing Characteristics for 3.3V Operations
Vee
= 3.3V ±0.3V, TA = O°C to +70°C
Version
Symbol
28F016SV-075
Parameter
Min
Read Cycle Time
tAVAV
Units
Max
75
ns
tAVQV
Address to Output Delay
75
ns
tELQV
CE# to Output Delay
75
ns
tpHQV
RP# High to Output Delay
480
ns
tGLQV
OE # to Output Delay
40
ns
tEHQZ
CE # to Output in High Z
30
ns
tFHQV
BYTE # High to Output Delay
75
ns
Table 11. Improved AC Read Timing Characteristics for 5.0V Operations
Vee = 5.0V ±0.5V, 5.0V ±0.25V, TA = O°C to +70°C
l
Versions
Symbol
I
Parameter
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE # to Output Delay
tpHQV
RP# High to Output Delay
tGLQV
tFHQV
3-544
Vee ±5%
28F016SV-065
28F016SV-070
Vee ±10%
Min
Max
65
Min
70
65
Units
Max
ns
70
ns
65
70
ns
300
300
ns
OE # to Output Delay
30
35
ns
BYTE # High to Output Delay
65
70
ns
AP-393
2.10 Write Timing Specifications
The 28F016SV write timing specifications have also
been improved to keep read and write cycle times
equivalent and to simplify system interface to the flash
memory. Tables 12 through IS show these improved
specifications. Both WE#- and CE#-controlled write
specifications are shown, for both commands and
writes to the page buffer, and at Vee = 3.3Vand S.OV.
Table 12. Improved AC WE#-Controlled Write Characteristics for 3.3V Operations
Vee = 3.3V ±0.3V, TA = O·C to +70·C
Version
Symbol
Min
Units
Max
tAVAV
Write Cycle Time
75
ns
tELWL
CE# Setup to WE# Going Low
0
ns
tWLWH
WE# Pulse Width
60
ns
tAVWH
Address Setup to WE # Going High
60
ns
tOVWH
Data Setup to WE # GOing High
60
ns
tWHOX
Data Hold from WE # High
5
ns
tWHAX
Address Hold from WE# High
5
ns
tWHEH
CE # Hold from WE # High
5
ns
tWHWL
WE# Pulse Width High
15
ns
480
ns
55
ns
tpHWL
tWHGL
Vee
28F016SV-075
Parameter
=
. RP # High Recovery to WE # Going Low
Write Recovery before Read
Table 13. Improved AC WE#-Controlled Write Characteristics for 5.0V Operations
S.OV ±O.SV, S.OV ±0.2SV, TA = O·C to +70·C
l
Versions
Symbol
I
Vee ±5%
28F016SV-065
28F016SV-070
Vee ±10%
Parameter
Min
Max
Min
Units
Max
Write Cycle Time
65
70
ns
tpHEL
RP# Setup to CE# Going Low
300
300
ns
tAVWH
Address Setup to WE # Going High
40
40
ns
tOVWH
Data Setup to WE# Going High
40
40
ns
tWLWH
WE# Pulse Width
40
45
ns
tWHAX
Address Hold from WE # High
5
10
ns
tWHEH
CE # Hold from WE # High
5
5
ns
tWHWL
WE# Pulse Width High
15
15
ns
tPHWL
RP# High Recovery to WE# GOing Low
300
300
ns
tWHGL
Write Recovery before Read
55
60
ns
tAVAV
3-545
AP-393
Vee
=
Table 14. Improved AC CE#-Controlled Write Characteristics for 3.3V Operations
3.3V ±0.3V, TA = O"C to +70"C
Version
Symbol
Parameter
Min
Units
Max
Write Cycle Time
75
ns
tELEH
CE # Pulse Width
60
ns
tAVEH
Address Setup to CE # Going High
60
ns
tDvEH
Data Setup to CE # Going High
60
ns
tEHWH
WE # Hold from CE # High
5
ns
tEHEL
CE # Pulse Width High
15
ns
tpHEL
RP# High Recovery to CE# GOing Low
480
ns
tEHGL
Write Recovery before Read
55
ns
tAVAV
Vee
28F016SV-075
=
Table 15. Improved AC CE#-Controlled Write Characteristics for 5.0V Operations
5.0V ±0.5V, 5.0V :!;0.25V, TA = O"C to +70"C
I
I
Versions
Symbol
tAVAV
Vee ±5%
28F016SV-065
28F016SV-070
Vee ±10%
Parameter
Write Cycle Time
Min
Max
Min
Units
Max
65
70
ns
tPHWL
RP# Setup to WE# Going Low
300
300
ns
tAVEH
Address Setup to CE # .Going High
.40
45
ns
tDVEH
Data Setup to CE # Going High
40
45
ns
tELEH
CE # Pulse Width
40
45
ns
tEHWH
WE # Hold from CE # High
5
5
ns
tEHEL
CE # Pulse Width High
15
15
ns
300
300
ns
55
60
ns
tpHEL
RP# High Recovery to CE# Going Low
tEHGL
Write Recovery before Read
3-546
AP-393
3.0 HARDWARE DESIGN FOR
FORWARDS-COMPATIBILITY
Manufacturers that wish to use the 28F016SAnow,
and move to the 28F016SV for write performance, integration or other reasons, should keep the following
focus areas in mind when completing designs:
12.0VOlJT
12.0V
CONVERTER
_ I
f---..L{Y--o
vpp
FLASH
IIEMORY
5.OVPOWER
SUPPLY
3.1 Vee Voltage
As noted in Section 2.8, the' 28F016SV's typical and
maximum read/standby currents and typical deep power-down current are higher than those of the
28F016SA. Vee power supply selection should factor
in these higher currents, as should system power consumption ,calculations. Decoupling and bypass capacitors can supply current for any of the 28F016SV Vee
deep power-down mode current "spikes" (Vee =
3.3V) with no added burden on the power supply.
If conversion to the 28F016SV will also include changing the write/erase voltage to S.OV from 12.0V, S.OV
power supply current calculations should include both
the future additional write/erase current drawn by the
28F016SV's Vee input (ifVcc = S.OV) and the future
current drawn by the 28F016SV's Vpp input (connected to S.OV).
3.2 Vpp Voltage
Conversion to the 28F016SV may be driven by the desire to write/erase at S.OV (thereby eliminating the
need for a separate 12.0V regulator). Keep in mind that
write/erase at S.OV is lower performance than at 12.0V.
Some flash memory applications (but not all) can tolerate this additional write/erase time. For these applications, a jumper on the system board that enables Vpp
pin connection either to the output of a 12.0V converter
(for the 28F0l6SA) or to the system S.OV supply (for
the 28F016SV) should be added. With the jumper connected to S.OV, the 12.0V converter and associated circuitry can be removed to lower system component
count. See Figure 3 for an example.
292144-3
Figure 3. Jumper Selection of 12.0V Converter
or 5.0V Power Supply Output for Vpp
Write Protection Via VPPLK
Switching Vpp off during normal operation is one of
several methods commonly used to prevent unwanted
alteration (data write or erase) of flash memory data.
Designs that use this technique should ensure that the
Vpp voltage transitions to GND when "off." Some
12.0V converters drop Vpp to a diode drop below Vee'
when they are placed in shutdown. This will block unwanted data write and erase on the 28F016SA but not
on the 28F016SV, which has a S.OV Vpp option. An
external pulldown resistor will pull the converter output to GND, preventing data alteration on either the
28F016SA or the 28F016SV. Other write protection
techniques (i.e., RP# and WP# control) should also
be used for full flash memory data protection.
3.3 Read/Write Performance and
Wait-State Configuration
Conversion to the 28F016SV may also be driven by its
higher read performance. Component identification in
communicating whether the 28F016SA or the high
speed 28F016SV is in system can either be accomplished via hardware or software methods (see
Sections 3.4 and 4.1). Depending which component
resides in the system, the state machine within the interface logic and/or system software can modify the
wait-state profile of the flash memory space to take advantage of the 28F016SV's higher read performance capability.
3-547
AP-393
3.4 Hardware Identification of
4.0 SOFTWARE DESIGN FOR
FORWARDS-COMPATIBILITY
28F016SA or 28F016SV
The 28F016SV is fully software backwards-compatible
with the 28F016SA. This section discusses several
28F016SV enhancements that system software can access if desired. Keep in mind that these features are not
available on the 28F016SA and their access and/or impiementation should not be attempted when using the
28F016SA.
Jumpers can be used to communicate whether the
28F016SA or 28F016SV device is,in the system, as
shown in Figure,4. As the device identifiers for the
28F016SA and the 28F016SV are identica1(see Section
4.1), software i4entification of one or the other flash
memory via reading the device ID is not feasible. See
Section 4.1 for a software method of identifying the
28F016SA or 28F016SV via the Device Proliferation
Code. Jumper identification can also be used to enable
system software usage of the 28FOI6SV's Status Register enhancements, Device Configuration Code and perblock cycle count. See Section 4 for more information.
A
'\
'\.r
CPU
l
'---V
y
ADDRESSIDATA
VF
LOGIC
OEII
FLASH
MEMORY
WFiI
eLK
.CEi_
1
READY
VO
5.0V
JPl
292144-4
Figure 4. Jumper Identification of 28F016SA or 28F016SV Presence
3-548
AP-393
4.1 Software Identification of
28F016SA or 28F016SV
The 28F016SV's device identifier 'is identical to that for
the 28FO 16SA. This enables all software written for the
28F016SA to be run on the 28F016SV unchanged.
Methods of identifying the 28F016SV in the system,
such as the jumper identification of Section 3.3 and
Figure 3, can be used in designs that can accept both
the 28F016SV and the 28FOI6SA. An alternative software method uses the Device Proliferation Code, supported on, the 28F016SV (OIR), but not on the
28FOI6SA. By initializing the Page Buffer location corresponding to this code to a known value and then executing an Upload Device Information command sequence, subsequent reads of the Page Buffer will identify the specific FlashFile memory in the system. The
Device Proliferation Code address in the Page Buffer is
IFH in x8 mode and OFH (upper 8 bits) in xI6 mode.
A pseudocode flow for this technique is shown below:
4.3 Enhanced Vpp Status Bit
Bit 2 of the Block Status Registers, functionally'identical to bit 3 of the Compatible Status Register, is enhanced on the 28FOI6SV to reflect both S.OV and
12.0V Vpp capability (see Section 2.4 and Tables 1 and
2). With Vpp = 12.0V at the beginning of data write/
erase, Vpp transitions below II.4V will, if detected, terminate datil write/erase and return error indication via
CSR.3 = BSR.2 = "I" (this is 100% compatible with
the 28F016SA function). With Vpp = S.OV at the beginning of data write/erase, Vpp transitions above S.5V
or below 4.5V will, if detected, also terminate data
write/erase and return error indication via CSR.3 =
BSR.2 = "I" (this is new to the 28FOI6SV). Accordingly; the CSR.3 = BSR.2 = "I" condition has been
renamed from "Vpp Low" (the 28FOl6SA definition)
to "Vpp Error."
4.4 RY IBY # Configuration
Initialize Device Proliferation Code address in
Page Buffer to DOH.
Execute Upload Device Information command sequence
Swap Page Buffer
Read from Device Proliferation Code address
If data = DOH. 28FOl6SA is present
If data = OIH. 28FOl6SV is present
End
4.2 Block Status Register Vpp Level
Bit
Bit 1. of the Block Status Registers, a "reserved" bit on
the 28FOI6SA, is the "Vpp Level" bit on the 28F016SV
(s.ee Section 2.4 and Table 2). System software interfacing to the 28FOI6SV can examine this bit and, by determining what Vpp voltage is in the system, gain an indication of the level of data write and erase performance
to be expected. This capability is particularly valuable
when creating software that could run either in a 12.0V
Vpp or S.OV Vpp system (such as a low-level PCMCIA
driver). Knowledge of write/erase performance allows
software to adjust the frequency and duration of events,
such as background media cleanup, to optimize system
performance.
The 28FOl6SV adds the Device Configuration Code,
accessible via the Page Buffer after first writing the Upload Device Information command sequence (see seCtion 2.5 and Table 3). This code enables system software to read the currently-configured 28FOI6SV
RY /BY # mode. The Device Configuration Code is located at Page Buffer address IEH in x8 mode, OFH
(lower 8 bits in xI6 mode).
As discussed earlier in section 2.3, the 28F016SV
includes an additional RY/BY# mode, RY/BY#
Pulse on Write/Erase, enabled as part of the RY/BY#
Configuration (96H) command sequence. This mode
was Reserved for Future Use on the 28F016SA.
5.0 CONCLUSION
This application note has summarized upgrade considerations and compatibility areas between the 28FOl6SA
and the 28FOI6SV. Consult reference documentation
for a more complete understanding of compatibility
and device capabilities. Please contact your local Intel
or distribution sales office for more information on Intel's flash memory products.
3-549
AP-393
6.0 ADDITIONAL INFORMATION
Document/Tool
Order Number
290528
28F016SV Datasheet
290489
28F016SA Datasheet
297372
"16-Mbit Flash Product Family User's Manual.
28F016SAl28F016SV/28F016XS/28F016XD"
292126
AP-377 "16~Mbit Flash Product Family Software Drivers.
28F016SAl28F016SV /28F016XS/28F016XD"
292127
AP-378 "System Optimization Using the Enhanced Features of the 28F016SA"
297508
FlashBuilder Utility
Contact Intel/Distribution
Sales Office
28F016SViBIS Models
Contact Intel/Distribution
Sales Office
28F016SV VHDLlVeriiog Models
Contact Intel/Distribution
Sales Office
28F016SV Timing Designer Library Files
Contact Intel/Distribution
Sales Office
28F016SV Orcad and ViewLogic Schematic Symbols
7.0 REVISION HISTORY
Number
-001
-002
3-550
Description
Original Version
Added new RY /BY # mode of 28F016SV (Pulse-On-Write/Erase).
Added/Revised DC/AC Characteristics based on 28F016SV Datasheet (Rev. 002)
- Increased leeR Added to Tables 8 and 9.
- Decreased leeEs. IpPR. IpPES Added to Tables 8 and 9.
- tpHQV Added to Table 10.
- tpHQV and tGLQV Added to Table 11.
- tPHWL Added to Table 12.
- tpHEL. tAVWH. tOVWH. tWLwH and tpHWL Added to Table 13.
- tpHEL Added to Table 14.
- tPHWL. tAVEH. tOVEH. tELEH and tpHEL Added to Table 15.
Tables 16 and 17 Consolidated into Tables. 12 and 13.
Added "Swap Page Buffer" to Pseudocode Example in Section 4.1.
intel.
AP-359
APPLICATION
NOTE
28F008SA
Hardware Interfacing
BRIAN DIPERT
MCD MARKETING APPLICATIONS
September 1993
laroe,
N,mOO, 292094-003
3-551
28F008SA Hardware Interfacing
CONTENTS
PAGE
CONTENTS
PAGE
1.0 INTRODUCTION ................... 3-553
ADDITIONAL INFORMATION .... ..... 3-559
2.0 HARDWARE INTERFACiNG .......
2.1 Vpp (Byte Write/Block Erase
Voltage) ..........................
Vpp Generation Circuits ..........
Controlling Vpp to 28F008SA
Component(s) .................
2.2 RY/BY# (Ready/Busy) Output ..
2.3 RP# (ResetiPowerdown) Input ..
Deep Powerdown Mode ..........
Write Protection ......' ............
APPENDIX A: Intel386TM SL PI Bus
Interface ............................ 3-560
Reset Control ....................
2.4 WE # (Write Enable) Input .. , ....
2.5 High Density/ln 2 Layout .........
2.6 Power Supply Decoupling ........
2.7 High Speed Design Techniques ..
2.8 Example Bus Interfaces .........
3-552
3-554
3-554
3-555
APPENDIX B: Intel486™ SX Local CPU
Bus Interface ....................... 3-561
3-555
3-556
3-556
3-556
3-557
3-557
3-557
3-557
3-558
3-559
3-559
I
AP-359
• Automated Byte Write and Block Erase
- Command User Interface
- Status Register
• System Performance Enhancements
- RY/BY# Status Output
- Erase Suspend Capability
1.0 INTRODUCTION
The 28FOO8SA FlashFile™ Memory is a very high
performance 8 Mbit (8,388,608 bit) memory, organized
as I Mbyte (1,048,576 bytes) of 8 bits each. The
28F008SA contains sixteen 64 Kbyte (65,536 byte)
blocks, each block separately eraseable and capable of
100,000 byte write-block erase cycles. On-chip automation dramatically simplifies software algorithms, and
frees the system microprocessor to service higher priority tasks during component data update. An enhanced
system interface allows switching the 28FOO8SA into a
deep powerdown mode during periods of inactivity, and
gives a hardware indication of the status of the internal
Write State Machine. High-speed access time allows
minimal wait-state interfacing to microprocessor buses,
and advanced packaging provides optimum density/
in 2.
• Deep Powerdown Mode
- 0.20 J.l.A IcC Typical
• Very High Performance Read
- 85 ns Maximum Access Time
• SRAM-Compatible Write Interface
• Hardware Data Protection Features
- Erase/Write Lockout during Power Transitions
• Industry Standard Packaging
- 40 Lead TSOP, 44 Lead PSOP
Features of the 28FOO8SA include:
• High-Density Symmetrically Blocked Architecture:
- Sixteen 64 Kbyte Blocks
• Extended Cycling Capability
100,000 Block Erase Cycles
1.6 Million Block Erase Cycles per Chip
I-
~
CPU
I
• ETOX III Nonvolatile Flash Memory
Technology
- 12V Byte Write/Block Erase
,..
110.
DRAM
~
~
,..
110.
CACHE
Today's Memory Paradigm
DISK
CPU
I
I
CACHE
I-
l-
...
t.:
FLASH
CACHE
I
DRAM
The Future, Using Flash Memory
292094-1
Figure 1. The 28F008SA Revolutionizes the Architecture of Computing
I
3-553
AP-359
r""""--,.f--W..L--
CEO
1+--+-+--- WEO
14-----L,,.....-rJ+------RP.
OE'
r::::}--;:===:::;-+
V-DECODER
RV/8Y#
X-DECODER
292094-2
Figure 2. 28F008SA Block Diagram
Traditional system architectures combine slow. high
density nonvolatile mass storage (such as a disk drive)
and fast, volatile memory (such as DRAM) to fully
address system requirements. As Figure 1 illustrates,
flash memory combines the best features of both the
above memory technologies, making a "disk/DRAM"
approach to system architecture unnecessary and ultimately wasteful. Flash memory is rapidly approaching
DRAM in both cost and performance (especially in
cached systems), while adding capabilities (such as nonvolatility), that DRAM cannot claim. The 28FOO8SA
will be the building block memory of choice for emerging computing markets, whether integrated in a memory card or disk drive form factor, or resident on the
system motherboard.
Figure 2 shows a block diagram of the 28F008SA and
its internal contents. The CE# (chip enable) and OE#
(output enable) inputs have comparable enable and
read functions to those of other memory technologies
such as SRAM. Similarly, Vee is the component power
supply (5V ± 10%), while GND should be connected
to system ground. Address inputs allow the system to
select a specific byte for reading or writing!erasing, and
the 8-bit data bus transfers information to and from the
28FOO8SA. The other control lines (WE#, RP#,
RY/BY# and Vpp) are discussed below.
This application note discusses hardware interfacing of
the 28F008SA, flash memory to system designs. The
28FOO8SA datasheet (order number 290429) is a valuable reference document, providing in-depth device
technical specifications, packa~e pinouts and timing
waveforms. Additionally, companion application note
AP-360, "28FOO8SA Software Drivers" (order number
292095) provides example ASM-86 and "C" routines
for controlling the 28FOO8SA. AP-364 "28F008SA Automation and Algorithms" discusses in-depth operation
of the 28FOO8SA Write State Machine and internal algorithms, emphasizing how they interface to system
software and hardware. AP-360 and AP-364 should be
reviewed in conjunction with this application note and
the 28FOO8SA datasheet for a complete understanding
of this device.
The Vpp input supplies high voltage to the 28F008SA
to enable byte write and block erase. Vpp is specified at
12V ± 5% (ll.4V -12.6V). Attempting to byte write or
block erase the 28F008SA beyond the 5% 12V tolerance is not recommended. Vpp above 12.6V can potentially result in device damage, and Vpp below ll.4V
dramatically lengthens write/erase time and compromises data reliability. The 28F008SA is guaranteed to
prevent byte write and block erase attempts with Vpp
below 6.5V, and in this situation it reports a "low Vpp
error" through the component Status Register (see
AP-360, AP-364 or the 28F008SA datasheet).
3-554
2.0
2.1
HARDWARE INTERFACING
Vpp (Byte Write/Block Erase
Voltage)
I
Ap·359
Vpp Generation Circuits
12V is often already present in systems, used to power
the hard drive, display, RS-232 circuitry, flash BIOS
update, etc. If it meets the tolerance and current capability requirements of the 28F008SA, such a power supply could be used directly as the 28F008SA update
voltage source. However, 12V is sometimes not present
or otherwise required, and in such cases, the 2SFOOSSA
Vpp must be derived from existing voltages and supplies.
Fortunately, flash memory's rapidly increasing popularity has driven ever-improving 12V converter availability in the market. These solutions derive a regulated
12V from a wide range of input voltages, and offer varied levels of integration and current delivery capability.
In general, the input for 12V converters should come
from the unregulated system power source, particularly
in battery-powered systems.
RP# is at VIL (see section 2.3). This provides data
protection during system powerup, when the minimally-loaded Vpp supply often ramps to 12V before Vee
(and therefore control inputs to the device) are stable.
For additional data protection, the system designer can
choose to make the Vpp supply switchable via a GPIO
(General Purpose Input/Output) line, enabling l2V to
the 2SFOOSSA only during byte write or block erase
attempts. A switchable Vpp also minimizes power consumption by both the flash memory components and
the 12V supply or converter (due to efficiency losses).
Many 12V converters integrate an ENABLE input,
eliminating external circuitry. If such an input is not
available, a low drain-source resistance MOSFET
switch such as the Motorola MTD4P05 can be used at
the l2V supply output. An example schematic for this
switch is shown in Figure 3. The calculations below
show that the low drain-source resistance of the
MTD4P05 will keep a l2V input within the 5% tolerance required by the 2SF008SA.
Table 1 lists and briefly describes severa! 12V generation solutions available at the time this document was
published. This is by no means an exhaustive list, and
does not reflect any specific recommendation by Intel
Corporation. For in-depth information on power supply solutions for flash memory, reference Intel application note AP-357 (order number 292092), available
through your local Intel sales office or distributor.
RoS
=
0.6l!
Ipp = 60 rnA
(worst case, two components being byte written or
block erased)
~VSWITCH
DROP = (60 rnA x 0.6l!) = 0.04V
12V
Controlling Vpp to 28F008SA Component(s)
Once 12V is available in the system, how is it controlled? One approach is to hard-wire l2V from the
supply directly to the Vpp inputs of each 2SFOOSSA in
the system. The advantage here is in design simplicity
and board space savings. The 2SFOOSSA Command
User Interface architecture and two-step byte write/
block erase command sequences provide protection
from unwanted data alteration even with high voltage
present on Vpp. All 28F008SA functions are disabled
with Vee below lockout voltage VLKO (2.2V), or when
10K
GPIO
10K
292094-3
Figure 3. Vpp Switch Schematic
Table 1. 12V Conversion Solutions for Vpp
Manufacturer
i
Part
Number
Maxim
MAX732
Linear Technology
LT1110-12
Input
(V)
Package
Current
Output
Total
Components
Needed
Est.
Cost
(10K)
4to 7.5
16 SOIC
120 mA
9
$3.93
4.5 to 5.5
S08
120 mA
11
$4.58
Linear Technology
LT1109-12
4.5 to 5.5
S08
60mA
8
$3.61
Motorola
MC34063A
4.5 to 5.5
S08
120mA
15
$2.25
Maxim
MAX667
12.1 to 16.5
S08
120 mA
4
$2.63
Linear Technology
LT1111-12
16 to 30
S08
120mA
7
$3.95
National Semiconductor
LM2940CT-12
TO-220
1A
3
$1.30
I
13 to 26
3-555
AP·359
2.2 RY IBY # (ReadyIBusy) Output
The 28FOO8SA offers similar automated byte write/
block erase capabilities to those first seen in the
28FOOIBX Bootblock flash memory family, introduced
by Intel in May of 1991. It enhances these capabilities
via the RY/BY# output, which provides hardware indication of internal Write State Machine (WSM) operation. RY /BY # is a full CMOS output, constantly driven by the 28FOO8SA and not tristated if the device
CE# or OE# inputs are brought to VIII. RY/BY#'s
default state after device powerup is VOH. It transitions
low to VOL when a byte write or block erase sequence
is initiated by system software, and RY/BY#'s rising
edge (return to VOH) alerts the system to byte write or
block erase completion. RY/BY# also goes to VOH
after the 28FOO8SA is put in Erase Suspend or Deep
Powerdown modeS.
RY/BY# is intended to interface the 28F008SA to a
system microprocessor rising-edge-triggered interrupt
input. In a multiple-chip memory array, external
EPLD logic or an interrupt controller can be used to
combine and prioritize RY/BY#s into one system interrupt (see Figure 4). The system can then, using a
flash memory "activity table" set up in RAM, poll the
individual 28F008SA Status Registers to determine
which device has returned "ready", or read. the
RY/BY# inputs directly at the EPLD, as shown.
Figure 5 provides an alternative method for connecting
multiple RY /BY # s to one interrupt input. The diode/
resistor combination converts the 28FOOSSA full
CMOS output into an open-drain "wired-OR" equivalent. Any RY/BY# at VOL will drive the interrupt
input low, and this input is pulled high by the resistors
when all RY/BY#s are at VOH. It is important in a
design like this to use diodes with low forward voltage
drops, so that the 2SFOOSSA VOL (0.45V) plus the diode voltage drop is still less than or equal to the destination input VIII (O.SV). For the schematic shown in
Figure 5, the equation is:
VOL
+ VOIOOE
= 0.45 VMAX
+ 0.3V
= 0.75V ,:; O.BV
Note that should the system connect RY/BY# to an
interrupt, disable that interrupt prior to suspending
erase, as RY /BY # will transition to VOH when the
device is suspended.
3-556
RD#--.....
WR#
CS#
An
INT
00 - 7.
292094-4
Figure 4_ EPLD·Based RYIBY # Implementation
+5V
10K
INT
MBD301
-'-"'+---1
MBD301
28F008SA
292094-5
Figure 5. "Wired·OR" RY IBY # Implementation
2.3 RP# (ResetlPowerdown) Input
Deep Powerdown Mode
The RP# input, when driven to VIL by the system,
switches the 2SFOOSSA into a deep powerdown mode
with negligable power consumption. This feature integrates the Vee power FET often used with low power
designs. Power consumption thru Vee is typically
I p.W in deep powerdown mode. RP#-low deselects
the memory, places output drivers for DO-7 in a highimpedence state and turns off a majority of internal
circuits. RY/BY# is driven to VOH while in deep
powerdown mode. Depending on the flexibility desired,
system designers can choose to put either the entire
flash device array into deep powerdown mode,. or any
individual components via selective input control. The
2SFOOSSA requires a "wakeup" time after RP # returns to VIII before it can be successfully written
(tpHwd or outputs are valid to read attempts (tpHQV)'
I
AP-359
Write Protection
Since RP# = VIL deselects the 2SFOOSSA, this input
can be used not only as a means of entering deep powerdown mode but also as an active-high "chip enable"
to block spurious writes during system power transitions. Figure 6 shows one possible RP# implementation, controlled by a GPIO line for power management
and by a system POWER GOOD for power sequencing
protection. In this design, the 5V monitoring circuit
begins functioning at Vee = IV, and will enable the
device only after Vee transitions above 4.6V (and system control signals are therefore stable). As Vee drops
below 4.6V during system powerdown, RP# protection
is again activated.
POWERGOOD
Vee
1 - - - - - - RP#(TO
GPIO
28F008SA)
292094-6
Figure 6. RP # Gating
Reset Control
RP# at VIL resets all internal automation within the
2SFOOSSA as part of the deep powerdown process.
Upon exit from deep powerdown, the 2SFOOSSA is reset to Read Array mode. This functionality is ideal
when the 2SFOOSSA is the boot memory for the system.
RP# active transitions reset the Write Status Machine
if system reset occurs during flash memory program or
erase, and allow successful CPU reboot.
2.4 WE# (Write Enable) Input
When flash memory is written, the result can range
from a 28FOOSSA that is placed in "read intelligent
identifier" or "read Status Register" modes to alteration of nonvolatile flash memory contents. System
hardware can prevent spurious writes to flash memory
by application software or an operating system by gating the system WE# to flash memory components to
enable writes only when desired.
Figure 7 shows a simple design that gates WE# with a
GPIO line, enabling writes to the 2SFOOSSA only when
the GPIO is a "0". The GPIO is initialized to "I" on
system powerup and the BIOS, a dedicated update software routine, a special keyboard sequence, switch on
the back of the system or jumper on the system motherboard can then control the GPIO. This circuit ensures
that flash memory contents are as permanent as
"ROM" unless alteration is specifically desired.
I
WR#(FROM SYSTEM)
GPIO
=D--
WE#(TO 28F008SA)
292094-7
Figure 7. WE# Gating
2.5 High Density/ln 2 Layout
Figure S shows an S Mbyte flash memory array using
TSOP (Thin Small Outline)-packaged 2SFOOSSAs in
standard (E) and reverse (F) configurations. A layout
like this is used in Intel's Series 2 flash memory cards
(in densities to 20 Mbytes) and provides optimum array
density for available board space.
Address and data lines are connected to all components
in parallel. OE# and WE,# are similarly connected.
Section 2.7 of this document discusses alternate methods of implementing these signals for highest speed
reads and writes in large memory arrays.
Component RY/BY#s are shown as not connected in
Figure S. They can be left unused, in which case the
system software will substitute polling of component
Status Registers for hardware interrupt, or RY/BY#s
can be implemented as described in section 2.2.
CE # s are also not connected, intended to be individually driven by system chip enable decoding logic. This
provides capability to read from and write to the array
on a byte-by-byte basis. In a x 16-only system, upper
and lower byte 2SFOOSSAs can have their CE#s bused
together if desired.
Finally, Vee, Vpp and RP# are connected in parallel
to all components. Section 2.6 discusses bypass capacitor filtering of supply voltage inputs, while section 2.3
provides uses for RP #. If desired, individual component, component pair, etc. selective powerdown control
can be substituted for the global control shown in
Figure S.
In space-constrained designs, a multiple-layer partial
"serpentine" trace layout at the edges of the 2SFOOSSA
array may be implemented, with a full serpentine layout within the array as in Figure S.
3-557
AP-359
VSBOO.:lBZ.:I
VSBOO.:lBZ3
o
o
o
E28F008SA
F28F008SA
292094-8
Figure 8. TSOP Serpentine Layout
2.6 Power Supply Decoupling
Both the Vee and Vpp inputs to each 28FOO8SA
should be decoupled at the package leads to provide
noise immunity and supply current for transient current spikes during read, byte write and block erase. Additional bulk capacitance for groups of flash memories
overcomes voltage slump caused by PC board trace inductances. Calculations for individual component and
bulk capacitors (one per 8 devices) are shown below.
Basic Equation:
I = C dv/dt
Assumptions:
I = 35 mA per device (Vee). therefore
I = 17.5 mA per device input (Vecl
I = 30 mA per device (Vpp)
dv = O.W (0.2V peak-peak)
dt=20ns
Per-Component-Input Decoupling Capacitor (Ved:
C = I dtldv = (17.5 mA x 20 ns)/O.W = 3.5 nF
4x margin = 4 x 3.5 nF = 14 nF
Standard Equivalent = 0.01 p.F
3-558
I
AP-359
NOTE:
Calculations above assume that each 28FOO8SA is
driving CMOS inputs (with corresponding high impedance and negligible input current requirements). If
28F008SA outputs are driving non-CMOS inputs,
larger per-component capacitance may be needed to
supply current while outputs are switching.
Bulk Capacitor (Vcd:
C
=
10
x
(Total of Decoupling Capacitors)
Bulk Capacitor (4 Mbyte array)
=
10 x (8 x 0.01 fLF)
= 0.8fLF
Standard Equivalent = 1 fLF
Per-Component Decoupling Capacitor (Vpp):
C
=
I dtldv
=
(30 mAX 20 ns)/O.1V
=
6 nF
4x margin = 4 X 6 nF = 24 nF
Standard Equivalent
=
• Minimize address bus loading from the microprocessor to the memory array. Multiple address latches
feeding subsets of the array speed address input to
each 28F008SA and CE# decoding by external logic.
• Similarly, drive the memory array with multiple
OE#s and WE#s. Most EPLD and discrete logic
timing is specified at a 30 pF load, which equates to
driving 4 28F008SA inputs at maximum input capacitance. Anything more than this may severely
impact the logic's propagation delay.
o Finally, remember that each 28F008SA, when read,
drives not only the system microprocessor or transceiver but also any other flash memory components
connected to the common data bus. Each 28F008SA
data output is specified at 12 pF, and the 28F008SA
read timings are tested at either 30 pF or 100 pF of
loading, depending on the chosen speed bin.
0.033 fLF
2.7 High Speed Design Techniques
The 28F008SA's fast read access and command write
specifications make it a natural choice for high performance memory arrays. The following tips will optimize the memory interface for optimum read/write
speed. The common recommendation in all instances
centers around minimizing fanout and capacitive bus
loading to allow highest switching speed, lowest rise
and fall times, and therefore greatest performance.
For large flash arrays where sequential data can be distributed on many devices, hardware interleaving provides additional performance.
2.8 Example Bus Interfaces
Appendix A shows hardware interface to the Intel386™SL PI bus, and Appendix B shows interface to
the Intel486™SX local CPU bus. Both interfaces incorporate techniques described in sections 2.1- 2. 7 of
this document. These designs are intended to be examples which can be modified to suit requirements of the
end system.
ADDITIONAL INFORMATION
AP-357
AP-360
AP-364
ER-27
ER-28
I
28F008SA Datasheet
28F008SA-L Datasheet
"Power Supply Solutions for Flash Memory"
"28F008SA Software Drivers"
"28F008SA Automation and Algorithms"
"The Intel 28F008SA Flash Memory"
"ETOX-III Flash Memory Technology"
Order Number
290429
290435
292092
292095
292099
294011
294012
3-559
AP-359
APPENDIX A
Intel386™SL PI BUS INTERFACE
12V
SA1-16 •
... -
LA17 - 20
SAo •
LA2 '_22
SAo_'6 •
LA17 _20
LATCH
PSTART#
80386Sl
...
.... ,,
."
."
...
.--
r+}
)"PLD
PM/IOO
PW/RO
FLSHOCS#
~
0
0
....
OJ
..".q:
WEO
OE#
::-
CS#l
RY /BY~!
..01
000-7
""
<[
Vpp
VI
OJ
0
".
".
ROO
WRO
CEO
",,
".
n:
I::
N
~
",,"3
VGACS#
VI
OJ
m008SA',
~
PROY#
<[
CS'
TO OTHER
~.
... -....
..... :::
---------~
't
PCMOO
Ao-'~:i:::::::
AO-I~:i:::::::
CEO
CSL# 1
CSH# I·
I SBHE#.
SBHE#
Vpp ;
Switch:
0
....
OJ
N
WE#
OE#
RP# RY /BY#.! ..01
000-7
""'--10
•
I
GPIO
RESET#
-_.
~::
..".H:",,
..
~
.....
:::
",,,
... V
",,
",
",
".
",
p-
RP#
... SOO_15
SOO_7
SOO_7!
INT
RY /BY#
S08_15
~
~
82360SL
~
RESET# ...
Controller
PWRGOOD ...
WR#
RY /BY#,
RY/BY#2
EPLD(s)
I;:
--}
;::
+-:
RY/BY'
FROt.! 'OTHER
2BrOO8SA',
RP#
-+} TO~:ER
::.
28FOO85A
PAIRS
292094-9
NOTE:
The DRAM interface is not shown, for graphic simplicity.
@
3·560
I
AP-359
APPENDIX B
Intel486™ SX LOCAL CPU BUS INTERFACE
lOY
lA Z_ 21
Vpp
Switch
A2- 24
t~\-L....r1___ f""\.-.J-
GPIO
RES£T#
LATCH
8E#0_3
CS#3
E~~a~
elK
Int.1486JJ,1SX
_____
RP' RP#
D/c#:
W/R#
EPLO(s)
IiI/IO#
ADSROY#
LOO_ 31
Trans-
c,iv.r
292094-10
NOTE:
The DRAM interface is not shown, for graphic simplicity.
REVISION HISTORY
Number
-003
I
Description
Renamed PWD# as RP# to match JEDEC conventions.
Updated Figure 6
Added Reset Control discussion for RP# (ResetiPowerdown) Input.
3-561
intel·
AP-360
APPLICATION
NOTE
28F008SA
Software Drivers
BRIAN DIPERT
MCD MARKETING APPLICATIONS
September 1993
3-562
I
Order Number: 292095-003
28F008SA Software Drivers
CONTENTS
PAGE
1.0 INTRODUCTION ................... 3-564
CONTENTS
PAGE
ADDITIONAL INFORMATION ......... 3-583
2.0 ASM86 ASSEMBLY DRIVERS ..... 3-565
3.0 "C" DRIVERS ..................... 3-569
I
3-563
AP-360
1.0 INTRODUCTION
This application note provides example software code
for byte writing, block erasing and otherwise controlling Intel's 28FOO8SA 8 Mbit symmetrically blocked
FlashFile™ Memory family. Two programming languages are provided; high-level "C" for multi-platform
support, and ASM-86 assembly. In many cases, the
driver routines can be inserted "as is" into the main
body of code being developed by the system software
engineer. The text accompanying each routine describes
the existing code and suggests area for possible alteration to fit specific applications. These explanations,
along with in-line commenting, minimize driver modification efforts.
3-564
Companion product datasheets for the 28FOO8SA and
28FOO8SA-L are valuable reference documents. Datasheets should be reviewed in conjunction with this application note for a complete understanding of the devices. AP-359, "28FOO8SA Hardware Interfacing" is
the hardware-oriented application note equivalent for
these devices and can also be referenced. AP-364
"28FOO8SA Automation and Algorithms", another
useful reference, discusses the details of Write State machine automation.
The internal automation of the 28FOO8SA makes software timing loops unnecessary and results in platformindependent code. This software is designed to be executed in any type of memory and with all processor
clock rates. "C" code can be used with many microprocessors and microcontrollers, while ASM-86 assembly code provides the smallest code "kernal" for Intel
microprocessors and embedded processors.
I
Ap·360
2.0
ASM·86 DRIVERS
Copyright Intel Corporation, 1992
Brian Dipert, Intel Corporation, February 8, 1992, Revision 1.0
Rev1sion History: Rev 1.0
The toll owing code controls byte write ot data to a single 2BFOOBSA (x8 write)
DS:[SI] points to the data to be'written, ES:[DI] is the location to be written
In protected mode operation, DS and ES reterence a descriptor
Register AX is mod1tied by this procedure
WRITE_SETUP
EQU
40H
READ_ID
EQU
90H
INTEL_ID
EQU
89H
DEVICE_ID
EQU
OA2H
DEVICE_ID2
EQU
OA1H
READY
EQU
80H
W_ERR_FLAG
EQU
10H
VPP_FLAG
EQU
08H
Insert code here to ramp Vpp and disable component RP# input. It a string ot bytes is
to be written at 'one time, Vpp ramp to 12V and ID check need only occur once,
berore the t1rst byte is written
MOV
AX,
'Address 0 tor target 28F008SA-segment'
; Initialize pointer to 28F0008SA address 0
MOV
ES,
AX
MOV
DI,
"Address o tor target 28FOOBSA-ottset·
BYTE PTR ES:[DI],
READ_ID
; Write Inteligent Identitier command
MOV
INTEL_ID
; Does manutacturer ID read correctly?
CM?
BYTE PTR ES:[DI],
W_BYT_ID_ERR
JNZ
MOV
DI,
'Address 1 tor target 2BF008SA-ottset'
Initialize pointer to 28F008SA address 1
CM?
BYTE PTR ES: [DI] ,
DEVICE_ID
; Does device ID read correctly?
W_BYT_ID_PASS
JZ
CM?
BYTE PTR ES:[DI],
W_BYT_ID_ERR
JNZ
W_BYT_ID_PASS:
MOV
MOV
MOV
MOV
MOV
MOV
W':'BYT_LOOP:
TEST
JZ
-Byte write destination address-segment-
ES,
DI,
BYTE PTR
AL,
ES: [DI] ,
;
AX
"Byte write destination
ES: [DI] ,
WRITE_SETUP;
DS:[SI]
;
Initia11ze pOinter to byte write dest. address
address-ottset'
Write byte write setup collllllimd
Load AL with data to write
; Write to device
AL
BYTE PTR ES: [DI] ,
W_BYT_LOOP
READY
; Read 2BF008SA Status Register
; Loop until bit 7
1
TEST
JZ
BYTE PTR ES:[DI],
W_BYT_CONi
(W_ERR_FLAG OR VPP_FLAG)
TEST
JNZ
BYTE PTR ES:[DI],
W_BYT_ERR
W_ERR_FLAG
TEST
JNZ
ES:[DI], VPP_FLAG
W_BYT_VPP
=
Success!
Check Status Register bit 4
Jump it
1, Byte Write Error
=
Check Status 'Register bit 3
Jump it
i, Vpp Low Error
=
Insert code to service improper device ID read error here.
Is 28F008SA RP# input disabled? Is Vee applied to the 28F008SA?
Insert oode to servioe byte write error here
Insert code to service byte write Vpp low error here
Code continues tram this point •••••
This routine writes a byte of data to a single 2SFOOSSA. Note the use of BYTE PTR notation to force xS accesses. If
a string of bytes is to be written at one time, the Vpp ramp up, RP# disable and device ID checks need only be done
before the first byte write attempt. Additionally, when writing multiple bytes at once, exanlination of bits other than
bit 7 (WSM Status) need only occur after the last byte write has completed. The Status Register retains any error bits
until the Clear Status Register command is written.
I
3-565
AP·360
The following code controls byte write of data to a pair of 28F008SAs (xIS write)
DS: [SI] points to the data to be written. ES: [DI] is the location to be written
In protected mode operation, DS and ES reference a descriptor
Register AX is modified by this procedure
WRITE_SETUP
EQU
40H
READ_ID
EQU
90H
INTEL_ID
EQU
89H
DEVICE_ID
EQU
OA2H
DEVICE_ID2
EQU
OAIH
READY
EQU
80H
W_ERR_FLAG
EQU
IOH
VPP _FLAG
EQU
08H
. Insert code here to ramp Vpp and disable component RP# inputs. If a string of words is
to be written at one time, Vpp ramp to 12V and ID check need only occur once,
before the first word 15 written
MOV
AX.
MOV
MOV
MOV
ES.
DI.
ES:[DI].
'Address 0 for target 28F008SA-segment"
; Initialize pointer to 28F008SA address 0
AX
'Address 0 for target 28F008SA-offset'
«READ_ID SHL 8) OR READ_ID)
; Write Inteligent Identifier command
«INTEL_ID SHL 8) OR INTEL_ID)
CMF
ES:[DI].
JNZ
MOV
W_WRD_ID_ERR
DI.
"Address I for target 28F008SA-offset'
; Initialize pointer to 28F008SA address I
ES: [DI]. «DEVICE_ID SHL 8) OR DEVICE_ID)
; Does device ID read correctly?
W_WRD_ID_PASS
ES:[DI]. «DEVICE_ID2 SHL 8) OR DEVICE_ID2)
W_WRD_ID_ERR
; Does manufacturer ID read correctly?
CMF
JZ
CMF
JNZ
W_WRD_ID_PASS:
MOV
MOV
MOV
MOV
MOV
MOV
W_WRD_LOOP:
TEST
JZ
AX.
ES.
DI.
ES:[DI].
AX.
ES:[DI].
'Byte write destination address-segment'
; Initialize pOinter to byte write dest. address
AX
"Byte write destination address-offset'
«WRITE_SETUP SHL 8) OR WRITE_SETUP)
; Write byte write setup command
DS:[SI]
; Load AX with data to write
AX
; Write to devices
ES: [DI]. «READY SHL 8) OR READY) ; Read 28F008SA Status Registers
W_WRD_LOOP
; Loop until bit 7 = I
TEST
JZ
ES: [DI]. «(W_ERR_FLAG OR VPP _FLAG) SHL 8) OR (W_ERR_FLAG OR VPP _FLAG»
W_WRD_CONT
Success!
MOV
TEST
JNZ
TEST
JNZ
AX.
ES:[DI]
AL.
W_ERR_FLAG
W_WRD_ERR
AH.
W_ERR_FLAG
W_WRD_ERR
Load Status Register data into AX
Check Status Register bit 4 (low byte)
Jump if
I
Check Status Register bit 4 (high byte)
Jump if
I
TEST
JNZ
TEST
JNZ
AL.
VPP _FLAG
W_WRD_VPP
AH.
VPP _FLAG
W_WRD_VPP
Check Status Register bit 3 (low byte)
Jump if = I
Check Status Register bit 3 (high byte)
Jump if
I
=
=
=
W_WRD_ID_ERR:
Insert code to service improper device ID read error here.
Are 28F008SA RP# inputs disabled? Is Vcc applied to the 28F008SAs?
W_WRD_ERR:
Insert code to service byte write error here
W_WRD_VPP:
Insert code to service byte write Vpp low error here
W_WRD_CONT:
Code continues from this point •••••
This routine writes a word of data to a pair of 28FOO8SAs. Note that all constants have been "OR'd" for parallel
read/write of two devices at once. If a string of words is to be written at one time, the Vpp ramp up, RP# disable
and device ID checks need only be done before the first word write attempt. Additionally, when writing multiple
words at once, examination of bits other than bit 7 (WSM Status) need only occur after the last word write has
completed. The Status Register retains any error bits until the Clear Status Register command is written.
3-566
I
AP-360
The following code controls block erase of a single 2BFOOBSA (xB block erase)
ES:[OIl points to the block to be erased
In prctected mode operation. ES references a descriptor
Register AX is modified by this prccedure
ERASE. SETUP
EQU
20H
ERASE. CONFIRM
EQU
OOOH
READ. 10
EQU
90H
INTEL. 10
EQU
B9H
OEVICE.IO
EQU
OA2H
OEVICE.I02
EQU
OA1H
READY
EQU
BOH
E.ERR.FLAG
EQU
20H
E.CMD.FLAG
EQU
30H
VPP.FLAG
EQU
OBH
Insert code here to ramp Vpp and disable component RP# input. If a string ot blocks is
to be erased at one time. Vpp ramp to 12V and 10 check need only occur once.
before the first block is erased
MOV
AX.
'Address 0 for target 2BFOOBSA·segment'
; Initialize painter to 2BFOOBSA address 0
MOV
ES.
AX
MOV
01.
'Address o for target 2BFOOBSA·offset'
READ.IO
; Write Inteligent Identifier command
MOV
BYTE PTR ES: [OIl.
CMP
BYTE- PTR ES: [OIl.
INTEL.IO
; Ooes manufacturer 10 read correctly?
JNZ
E.BYT.IO.ERR
MOV
01.
"Address 1 for target 2BFOOBSA·offset'
; Ini tial1ze pOinter to 2BFOOBSA address 1
OEVICE.IO ; Ooes device 10 read correctly?
CMF
BYTE PTR ES: [OIl.
JZ
E.BYT.IO.PASS
CMP
BYTE PTR ES:[OIl.
OEVICE.I02
JNZ
E.BYT.IO.ERR
E.BYT.IO.PASS:
MOV
MOV
MOV
MOV
MOV
E.BYT.LOOP:
TEST
JZ
'Block erase destination address.segment'
; Initialize pointer to block erase dest.address
ES.
AX
01.
'Block erase destination address·offset'
BYTE PTR ES: [OIl. 'ERASE. SETUP
; Write block erase setup command
BYTE PTR ES:[OIl.
ERASE.CONFIRM ; Write block erase confirm command
AX.
BYTE PTR ES: [OIl.
E.BYT.LOOP
READY
; Read 2BFOOOBSA Status Register
; Loop until bit 7
1
TEST
JZ
BYTE PTR ES:[OIl.
E.BYT.CONT'
(E.CMD.FLAG OR VPP.FLAG)
Success I
TEST
JNZ
BYTE PTR ES:[OIl.
E.BYT.CMD.ERR
E.CMO.FLAG
Check Status Register bits 4 and 5
Jump it 1
TEST
JNZ
BYTE PTR ES:[OIl.
E.BYT.ERR
E.ERR.FLAG
Check Status Register bit 5
Jump i f 1
TEST
JNZ
BYTE PTR ES:[OIl.
E.BYT.VPP
VPP.FLAG
Check Status Register bit 3
Jump if 1
=
=
=
=
:
Insert code to service improper device 10 read error here.
Is 2BFOOBSA RP# input disabled? Is Vcc applied to the 2BFOOBSA?
E.BYT.CMD.ERR:
Insert oode to service block erase command sequenoe error here
(setup followed by a oommand other than confirm)
E.BYT.ERR:
,E.BYT~IO.ERR
Insert code to service block erase error here
E.BYT.VPP:
Insert code to service block erase Vpp low error here
E.BYT.CONT:
Code continues from this point •••••
This routine erases a block of a single 28FOOSA. Note the use of BYTE PTR notation to force x8 accesses. If a string
of blocks is to be erased at one time, the Vpp ramp up, RP# disable and device ID checks need only be down before
the first block erase attempt. Additionally, when erasing multiple blocks at once, examination of bits other than bit 7
(WSM Status) need only occur after the last block erase has completed. The Status Register retains any error bits
until the Clear Status Register command is written.
I
3·567
AP-360
The following code controls .block erase of a pair of 28F008SAs (xIS block erase)
ES: [DIJ points to the blocks to be erased
In protected mode operation, ES references a descriptor
Register AX is modified by this procedure
ERASE_SETUP
EQU
20H
ERASE_CONFIRM
EQU
ODOH
READ_ID
EQU
90H
INTEL_ID
EQU
,89H
DEVICE_ID
EQU
OA2H
DEVICE_ID2
EQU
OAIH
READY
EQU
80H
E_ERR_FLAG
EQU
20H
E_CMD_FLAG
EQU
SOH
VPP_FLAG
EQU
08H
Insert code here to ramp Vpp and disable component RP# inputs. If a string of blocks is
to be erased at one time. Vpp ramp to 12V and ID check need only occur once,
MOV
MOV
MOV
MOV
CM?
before the first block pair is erased
AX.
'Address 0 for target 28F008SA-segment'
; Initialize pointer to 28F008SA address 0
AX
ES.
'Address 0 for target 28F008SA-offset'
DI.
ES:[DIJ. «READ_ID SHL 8) OR READ_ID)
; Write Inteligent Identifier command
ES:[DIJ. «INTEL_ID SHL 8) OR INTEL_ID)
; Does manufacturer ID read correctly?
JNZ
MOV
CMP
JZ
CM?
JNZ
E_WRD_ID_PASS:
MOV
E_WRD_ID_ERR
DI.
'Address 1 for target 28F008SA-offset'
; Initialize pointer to 28F008SA address i
ES: [DIJ • «DEVICE_ID SHL 8) OR DEVICE_ID)
Does device ID read correctly?
E_WRD_ID_PASS
ES:[DIJ. «DEVICE_ID2 SHL 8) OR DEVICE_ID2)
E_WRD_ID_ERR
AX. "
'Block erase destination address-segment'
; Initialize pointer to block erase dest. address
MOV
MOV
MOV
ES.
DI.
ES:[DIJ.
AX
MOV
ES: [DI],
ftBlock erase destination address-offset"
«ERASE_SETUP SHL 8) OR ERASE_SETUP)
Write block erase setup command
«ERASE_CONFIRM SHL 8) OR ERASE_CONFIRM)
; Write block erase confirm command
E_WRD_LOOP:
TEST
JZ
ES:[DIJ. «READY SHL 8) OR READY) ; Read 28F008SA Status Registers
E_WRD_LOOP
; Loop until bit 7
1
=
TEST
JZ
ES:[DIJ. " «(E_CMD_FLAG OR VPP_FLAG) SHL 8) OR (E_CMD_FLAG OR VPP_FLAG))
E_WRD_CONT
Success!
MOV
TEST
JNZ
TEST
JNZ
AX.
ES: [DIJ
AL.
E_CMD_FLAG
E_WRD_CMD_ERR
AH.
E_CMD_FLAG
E_WRD_CMD_ERR
Load Status Register data into AX
Check Status Reg bits 4 and 5 (low byte)
Jump i f = 1
Check Status Register bits 4 and 5 (high byte)
Jump i f = 1
TEST
JNZ
TEST
JNZ
AL.
E_ERR_FLAG
E_WRD_ERR
AH.
E_ERR_FLAG
E_WRD_ERR
Check Status Register bit 5 (low byte)
Jump i f 1
Check Status Register bit 5 (high byte)
Jump if
1
TEST
JNZ
TEST
JNZ
AL.
VPP _FLAG
E_WRD_VPP
AH.
VPP _FLAG
E_WRD_VPP
Check Status Register bit S (low byte)
Jump i f
1
Check Status Register bit S (high byte)
Jump i f 1
=
=
=
=
E_WRD_ID_ERR :
Insert code to service improper device ID read error here.
Are 28F008SA RP# inputs disabled? Is Vee applied to the 28F008SAs?
E_WRD_CMD_ERR:
Insert code to servtce block erase command sequence error here
(setup followed by a command other than confirm)
E_WRD_ERR:
Insert code to service block erase error here
E_WRD_VPP:
Insert code to service block erase Vpp low error here
E_WRD_CONT:
Code continues from this point •••••
3-568
I
AP-360
This routine erases a block pair of two 28F008SAs. Note that all constants have been "OR'd" for parallel read/write
of two devices at once. If a string of block pairs is to be erased at one time, the Vpp ramp up, RP # disable and device
ID checks need only be done before the first block pair erase attempt. Additionally, when erasing multiple block
pairs at once, examination of bits other than bit 7 (WSM Status) need only occur after the last block pair erase has
completed. The Status Register retains any error bits until the Clear Status Register command is written.
3.0
'C' DRIVERS
'*
'*
'*
*'
*'
*'
*'*'
*'*'
*'*'
*'*'
*'*'
*'*'
*'*'
*'*'
*'*'
*'*'
*'*'
*'*'
*'*'
*'*'
*'
*'
*'
"*'
*'*'
/*****************************************************************************************************/
Copyright Intel Corporation, 1992
1*
Brian Dlpert, Intel Corporation, May 7, 1992, Revision 2.1
*/
The following drivers control the Command and Status Registers of the 28F008SA Flash
/*
Memory to drive byte write, block erase, Status Register read and clear and
*/
array read algorithms. Sample Vpp and RP# control blocks are also included,
/*
as are example programs combining drivers into full algorithms
*/
1*
The functions listed below are included:
1*
erasbgn(): Begins block erasure
1*
erassusp(): Suspends block erase to allow reading data from a block of the
2BF008SA other than that being erased
erasres() : Resumes block erase if suspended
1*
end(): Polls the Write State Machine to determine if block erase or byte write
1*
have completed
1*
eraschk() : Executes full status check after block erase completion
wri tebgn (): Begins byte write
writechk(): Executes full status check after byte write completion
idread() : Reads and returns the manufacturer and device IDs of the target
1*
28F008SA
statrd(): Reads and returns the contents of the Status Register
1*
statclr(): Clears the Status Register
rdmode (): Puts the 28F008SA in Read Array mode
rdbyte (): Reads and returns a specified byte from the target 2BF008SA
vppup(): Enables high voltage Vpph
vppdown(): Disables Vpph
pwden(): Enables active low Signal RP#
pwddis(): Disables active low Signal RP#
''**
''**
'*
'*
''**
''**
''**
'''***
'*
1*
/*
/*
"
'r*
1*
Addresses are transferred to functions as pOinters to far bytes (ie long integers). An
alternate approach is to create a global array the size of the 28F008SA and
located 'over' the 28F008SA in the system memory map. Accessing specific
locations of the 28F008SA is then accomplished by passing the chosen function
an offset from the array base versus a specific address. Different
microprocessor architectures will require different array definitions; ie for
the Intel architecture, define it as 'byte eightmeg[16] [10000]' and pass each
fUnction TWO offsets to access a specific location. MCS-96 architectures are
limited to 'byte eightmeg[lOOOO]'; alternate approaches such as using port pins
for paging will be required to access the full flash array
1*
/*
/*
*/
*/
To create a far pointer, a function such as MK_FP{) can be used, given a segment and
*/
offset in the Intel architecture. I use Turbo-C; see your compiler reference
*/
manual for additional information.
/*****************************************************************************************************/
'*
'*
'*
'*
/*****************************************************************************************************/
Revision History: Rev 2.1
1*
1*
/*
/*
Changes From Revision 1.0 to Revision 2.0:
Added alternate 28F008SA device ID to routine idread()
Changes from 2.0 to 2.1: Revised the Erase Suspend algorithm to remove potential
'infinite loop' caused by the WSM gOing "ready' after the system reads the
Status Register, and before the system issues the Erase Suspend command
"
*/
*/
/***************************************************** *************************************~**********/
typedef
I
unsigned char byte;
3-569
AP-360
/"'****** '" III '" _ • • • • • • • '" '" "' • •
/'
/*
/'
/'
*. '" '" •••••••••••• "'., ••••• '" *........ "'. "' . . *•••••• '" "'."'.
III "' ..... ~ '" '"
*, "''''''' *"''''. "'' ' . . lie '" "'''' '" "'''' "'* ."'. I
Function: Main
Desoription: The following code shows examples of byte write and block
erase algorithms that can be modified to fit the specific application and
hardware design
, •••••• '" '" ***~ •••••• _._ •• *•••••••••
main()
*. *••••••••••••• ** "' .... "' •• '" "''''. '" *'" '" '" "'''''''''' . .
III '"
"'**"'. '"
11= '"
*/
*/
*/
*/
*'" "''''**''' '" * *"' . . '" '" '" '" "'*'" '" I
(
byte far 'address;
byte data,status;
/*
/*
/'
/*
/*
/*
The following code gives an example of a possible byte write algorithm.
Note that Vpp does not need to be oycled between byte writes when a string of byte
writes occurs. Ramp Vpp to 12V·before the first byte write and leave at 12V until after
completion of the last byte write. DOing so minimizes Vpp ramp up-down delay and
maximizes byte write throughput
vppup() ;
*/
*/
*/
*'
*'
'INSERT SOFTWARE DELAY FOR VPP RAMP IF REQUIRED'
*'
pwddis () ;
address
OXxxxxxL;
data
OXyy;
if (writebgn(data,address) == 1)
=
=
/*
~RECOVERY
CODE-POWER NOT APPLIED (ID CHECK FAIL)'
else
*'
[
while (end (Bcstatus) )
Switch (writechk(status))
(
case 0:
break ;
case 1:
'*
"RECOVERY CODE-VPP LOW DETEqT ERROR'
break;
case 2:
/*
'RECOVERY CODE-BYTE WRITE ERROR'
break;
*'
*'
statclr() ;
vppdown() ;
This "C" routine gives an example of combining lower-level functions (found in following pages) to complete a byte
write. Routines vppup( ) and pWddis( ) enable the 28FOO8SA for byte write. Function writebgn( ) issues a byte write
sequence to the device, end( ) detects byte write completion via Status Register bit 7, and writechk( ) analyzes Status
Register bits 3-6 to determine byte write success. If a string of bytes is to be written at one time, Vpp ramp up and
RP# disable need only be done before the first byte write attempt. Additionally, when writing multiple bytes at
once, examination of bits other than bit 7 (WSM Ready) need only occur after the last byte write has completed. The
Status Register retains any error bits until the Clear Status Register command is written.
3-570
I
AP-360
''**
'*
/*
"
1*
"
The following code gives an example of a possible block erase algorithm.
Note that Vpp does not need to be cycled between block erases when a string of block
erases occurs. Ramp Vpp to l2V before the first block erase and leave at l2V until after
completion of the last block erase. Doing so minimizes Vpp ramp up-down delay and
maximizes block erase throughput
vppup() ;
"INSERT SOFTWARE DELAY FOR VPP RAMP IF REQUIRED"
pwddis () ;
addre 55
= OXxxxxxL;
i f (erasbgn(address) == 1)
"RECOVERY CODE-POWER NOT APPLIED (ID CHECK FAIL)'
*'*'
*'*'
*'
"'
"'
else
I
while (end(ltstatus) )
switch (eraschk(status»
I
case 0:
break;
case 1:
'*
'"
'"
'RECOVERY CODE-VPP LOW DETECT ERROR"
break;
case 2:
'RECOVERY CODE-BLOCK ERASE ERROR"
break;
case 3:
'RECOVERY CODE-ERASE SEQUENCE ERROR"
break;
*'
*'
*'
statclr () ;
vppdown() ;
This "C" routine gives an example of combining lower-level functions (found in following pages) to complete a block
erase. Routines vppup( ) and pWddis( ) enable the 28FOO8SA for block erase. Function erasbgn( ) issues a block erase
sequence to the device, end() detects block erase completion via Status Register bit 7, and eraschk() analyzes Status
Register bits 3 - 6 to determine block erase success. If a string of blocks is to be erased at one time, Vpp ramp up and
RP# disable need only be done before the first block erase attempt. Additionally, when erasing multiple blocks at
once, examination of bits other than bit 7 (WSM Ready) need only occur after the last block erase has completed.
The Status Register retains any error bits until the Clear Status Register command is written.
I
3-571
AP-360
'****** ****** . . *' "''II'''''' *"''''''''''."'''' . . * * ......... *** '" '" III ****** ...... ** ** **** **** '" * * lie * ...... *** ********* *** ..... *"'* ** ••• '" *"'* "',.. "' ...... /
>/1: ...
'*
'*
'*
'*
'*
'*
'*
Function: Erasgbn
Description: Begins
Inputs:
blckaddr:
Outputs: None
Returns: 0 = Block
1 = Black
Device Read Mode on
#define
#define
ERASETUP
ERASCONF
erase of a block.
System address within the block to be erased
*'
*'
*'
*'
erase sucaessfully initiated
*'
erase not initiated (10 check error)
*'
Return: Status Register (10 if returns 1)
*'
1* *.... '" ***** III "''''.'''* "''''.'''* . . . *****************
**** * ***** ** *** ...... * * . . * "'*"'''''''''' ** ... ***** "' . . II< * *** ... '" * *** '" *'" "' . . ** '" /
11= ...... '" '"
OX20
OXDO
'*'*
Erase Setup command
Erase Confirm command
int erasbgn(blckaddr)
byte far *blckaddr;
'" blckaddr is an address within the black to be erased
*'*'
*'
byte mfgrid.deviceid;
i f (idread(&mfgrid.oI:deviceid)==l)
return (1);
*blckaddr = ERASETUP;
*blckaddr = ERASCONF;
return (0);
''**
/* ID read error; device not powered up?
Write Erase Setup command ta block address
Write Erase Confirm command to block address
*'
"'*'
Routine erasbgn( ) issues a block erase command sequence to a 28FOO8SA. It is passed the desired system address for
the block to be erased. After calling idread(). it writes the erase command sequence at the specified address. It
returns "0" if block erase initiation was successful, and "I" if the ID read fails (device not powered up or RP# not
disabled).
3-572
AP-360
'*
III III III III III III
,.
'*
'*
'*
'*
'*
,.
/.* *
* III III
It. *.
III III
III III III III III • • _ III III III III
*III III III III III III * * III * •• III III *III '" III III III III * * III **III III III * '" III III III III III III *III III III III III III III III III III III" III III III III *III. III III *III * ** III III III III III III III III I
Function: Erassusp
Description: Suspends block erase to read from another block
Inputs:
None
Outputs: None
Returns: 0= Block erase suspended
1 Error; Write State Machine not busy (block erase suspend not possible)
Device Read Mode on Return: Status Register
=
*~*
#define
#detine
*'
*'
*'
*'
*'
'0'0,
•• III • • • • • • _ • • • • • • • • • • • • • • • • • • _ • • • • • III _ • • • • • • ,• • • _ • • • • • • iii • • • _ • • • • • • • • • • • _ • • • • • • • • • • • • • • • • III *. III • • • • III III J
RDYIlASK
WSMRDY
,.,.
,0
Mask to isolate the WSM Status bit of the Status Register
Status Register value after masking, signifying that
the WSM is no longer busy
Mask to isolate the erase suspend status bit of the
Status Register
Status Register value after masking, signifying that
block erase has been suspended
Read Status Register command
constant
can be initialized to any address within
'* This
the memory map of the target 28F008SA and is
alterable depending on the system architecture
Erase· Suspend command
*'
byte far *stataddr;
1* Pointer variable used to write commands to device
*'
stataddr
°stataddr
'stataddr
,0
OX80
OX80
#detine
SUSPIIASK OX40
#detine
ESUSPIES
OX40
#define
#define
STATREAD
SYSADDR
OX70
0
#detine
SUSPCIID
OXBO
'0
,0
0,
0,0,
*'
,",.
,"
0'
,0,0
*'
'0
*'
.,
*'
*'
*'
int erassusp ()
(byte far *) SYSADDR;
,. Write Erase Suspend command to the device
Write Read Status Register command •• necessary in case
1*
erase is already completed
while « *stataddr I: RDYIlASK) != WSMRDY)
,. Will remain in while loop until bit 7 of the Status
'*
Register goes to 1, signifying that
'"
the WSM is no longer busy
if' « *stataddr I: SUSPIlASK)
ESUSPYES)
return (0);
Erase is suspended •• return code '0'
return (1);
"Erase has already completed; suspend not possible.
,.
Error code "1'
= SUSPCMD;
= STATREAD;
=
,0
*'*'
*'
.,
*'
*'
*'
"'
.,
Routine erassuspO issues the erase suspend command to a 28FOO8SA. It first makes sure the WSM is truly busy,
then issues the erase suspend command and polls Status Register bits 7 and 6 until they indicate erase suspension. It
returns ''0'' if block erase was successful, and "I" if the WSM was not busy when suspend was attempted.
I
3-573
AP-360
,"'** ••••• **** ..... "'.* •• "' •• *••••••• *.*"'.* ••••• _•• *•• ** •• ************************************************/
/*
'*
/*
/*
'*
'*
'*
Function: Erasres
Description: Resumes block erase previously suspended
Inputs:
1I0ne
Outputs: 1I0ne
Returns: 0
Block erase resumed
1 Error: Block erase not suspended when function called
Device Read Mode on Return: Status Register
#detine
#detine
RDYMASK
WSMRDY
OX80
OX80
#detine
SUSPMASK
OX40
#detine
ESUSPYES
OX40
#detine
#detine
STATREAD
SYSADDR
OX70
0
#define
RESUMCMD
OXDO
=
=
"'
*'
*'
*'
*'
*'
*'
1** "''''''' '" "'*"''''*.''''''* •.*'''''' ********* '" "' . . '" '" "'* '" "'*"''''''''''''''''''' '" ** '" '" '" ************** '" '" '" * "'* ."' •• *"''''.''' '" '" "'' ' ' '" "'."''''.''''''''''''.''' ••• * I
,.,"
,.,.
'*
,*
/*
,*
,"
,"
,"
,.
Mask to isolate the WSM Status bit of the Status Register
Status Register value atter masking, signifying that the
WSM is no longer busy
Mask to isolate the erase suspend status bit of the
Status Register
Status Register value atter masking, signifying that
block erase has been suspended
Read Status Register command
This constant can be initialized to any address within
the memory map of the target 28F008SA and is
alterable depending on the system architecture
Erase Resume command
int eraSres ()
byte far *stataddr;
/* Pointer variable used to write commands to device
=
stataddr
(byte far *)SYSADDR:
*stataddr
STATREAD:
'" Write Read Status Register command to 28F008SA
"if «*stateddr • SUSPMASK) != ESUSPYES)
return (1) ;
'" Block erase not suspended. Error code '1'
'stataddr RESUMCMD:
Write Erase Resume command to the device
while «*stataddr • SUSPMASK)
ESUSPYES)
'* Will remain in while loop until bit 6 of the Status
'*
Register goes to 0, signifying block
/*
erase resumption
while «"stataddr • RDYMASK)
WSMRDY)
'* Will remain in while loop until bit 7 or the Status
'*
Register goes to 0, signifying that the WSM is
'*
once again busy
return (0) ;
=
=
'*
=
==
.,.,
*'*'*'
"'*'
*'*'
"'*'*'
*'
*'
*'
*'
*'
"'
*'
*'
*'
"'
Routine erasres( ) issues the erase resume command to a 28FOO8SA. It first makes sure the WSM is truly suspended,
then issues the erase resume command and polls Status Register bits 7 and 6 until the indicate WSM resumption. It
returns "0" if block erase resume was successful, and "1" if the WSM was not suspended when resumption was
attempted.
3-574
I
Ap·360
*'*'
*'*'
*'
/********************************************************************************************************/
1*
'*
Function: End
Description: Checks to see if the WSM is busy (is byte write,block erase completed?)
Inputs:
None
'*
Outputs:
statdata: Status Register data read from device
Returns:
0
Byte Write,Block Erase completed
'*
1 = Byte Write,Block Erase still in progress
*'
'*
Device Read Mode on Return: Status Register
*'
,***********************************************.***************************.****** •• ********************/
#define
RDYMASK
OXBO
Mask to isolate the WSM Status bit of the Status
*'
#define
WSMRDY
OXBO
Register value after masking. signifying that the
'*
WSM is no longer busy
*'
#define
STATREAD
OX70
1* Read Status Register command
*'
#define
SYSADDR
o
'* This constant can be initialized to any address within*'
'*
the memory map of the target 2BFOOBSA and is
*'
'*
alterable depending on the system architecture *'
'*
'*
=
''**
*'
'* Allows Status Register data to be passed back to the
'*
main program for further analysis
*'
*'
'*
'*
*'
int end (statdata)
byte *statdata;
byte far *stataddr;
Pointer variable used to write commands to device
= (byte far *) SYSADDR;
= STATREAD;
Write Read Status
= *stataddr) I< RDYMASK) 1= WSMRDY)
stataddr
*stataddr
if (((*statdata
return
return (0) ;
(1);
Register command to 2BFOOBSA
*'
1* Byte write,block erasure still in progress ••• code '1' *'
1* Byte write,block erase attempt completed ••• code '0'
*'
Routine end() detects completion of byte write or block erase operations of a 28FOO8SA. It passes back the Status
Register data it reads from the device. It also returns "0" if Status Register bit 7 indicates WSM "Ready". and" I" if
indication is that the WSM is still "Busy".
I
3-575
Ap·360
************************************************1
'*'/*****************************************************
*'
''***
*'*'
''**
*'*'
*'*'
''**
=
=
*'
'/*****************************************************************"'***********************************/
*
*'
*'
",*
*'
*'
,*
*'
,*
*'
1*
/*
/*
Function: Eraschk
Description: Completes full Status Register check for block erase (proper command
sequence, Vpp low deteot, block erase success). This routine assumes that block
erase completion has already been checked in function end(), and therefore does
not check the WSM Status bit of the Status Register
Inputs:
statdata: Status Register data read in function end
Outputs: None
Returns: 0
Block erase completed suooessfully
1 Error; Vpp low detect
2 = Error; Block erase error
3 = Error; Improper command sequencing
Device Read Mode on Return: Same as when entered
#define
ESEQMASK
#define
ESEQFAIL
OX30
#define
EERRMSK
OX20
#define
ERASERR
OX20
#define
#define
VLOWMASK
VPPLOW
OXOS
OXOS
OX30
int eraschk (statdata)
byte statdata;
Mask to isolate the erase and byte write status bits of
the Status Register
Status Register value after masking if block erase
command sequence error has been detected
Mask to isolate the erase status bit of the
Status Register
1*
Status Register value after masking if block erase error
has been detected
1* Mask to isolate the Vpp status bit of the Status Register
1* Status Register value after masking if Vpp low
has been detected
"
.. I
*/
1*
,*,*
,*
,*
'*
Status Register data that has been already read from the
2SFOOSSA in function end ()
a: VLOWMASK) = VPPLOW)
/* Vpp low detect error, return code "I"
((statdata a: EERRMSK) = ERASERR)
return (2);
/* Block erase error detect, return code
((statdata a: ESEQMASK)
ESEQFAIL)
*'
"
*'
*'
*'
*'
*'*'
if ((statdata
*/
return (1);
if
if
return (3);
return (O);
"2"
1* Block erase command'sequence error, return code "3"
/* Block erase success, return code "0"
*/
*/
*/
Routine eraschk( ) takes the Status Register data read in end( ) and further analyzes it. It returns "0" if block erase
was successful, "I" ifVpp low error was detected, "2" if block erase error was reported and "3" if an erase command
sequence error was found (erase setup followed by a command other than erase confirm). This is useful after a block
or string of blocks has been erased, to check for successful completion.
3-576
I
Ap·360
/**** ** ********* *.** •• ** ... ************ ****** * .... oil" * *•••••• '" **** .. III ** * *** *•• '" **** *** *** .. '" *** III *.'" * ..... lie ...... *** .. I
,.
Function: Writebgn
"'
,.
Description: Begins byte write sequence
.,
,.
Inputs:
wdata: Data to be written into the device
.,
,.
waddr: Target address to be written
.,
1*
Outputs: None
.,
,.
Returns:. 0
Byte write successfully initiated
.,
'"
1 Byte write not initiated (ID check error)
.,
'"
Device Read Mode on Return: Status Register (ID if returns 1)
.,
/* ********* ***** * III""" *** ***** ***** ** .. *........ ************* ******** ** . . **** .. ******** *... *** * ... ** * "' ... "'.* .. *** .. I
=
=
#deflne
SETUPCMD
OX40
,. Byte Write Setup command
int writebgn(wdata,waddr)
,. Data to be written into the 2BFOOBSA
,. waddr is the destination address for the data
"
to be written
byte wdata;
byte far 'waddr;
"'
.,.,"
byte mfgrid,deviceid;
if (idread (tmfgrid,&deviceid) ==1) '" Device ID read eTror ••• powered up?
return (1);
'waddr
SETUPCMD;
,. Write Byte Write Setup oommand and destination address
'waddr
wdata;
,. Write byte write dat~ and destination address
return (0);
=
=
"'
"'
.,
/**.***************************************************************************************************/
1*
,.
1*
'"
'"
,.
,.
,.
"
,.
,.
Function: Writechk
.,
Description: Completes full Status Register check for byte write (Vpp low detect, byte
"'
write success). This routine aSSumes that byte write completion has already.
"
been checked in function end() and therefore does not check the WSM Status
"'
bit of the Status Register
"'
Inputs:
statdata: Status Register data read in function end()
Outputs: None
Returns: 0
Byte write completed successfully
1
Error; Vpp low detect
2
Error; Byte write error
"'
Device Read Mode an Return: Status Register
"'
J**************"" ********** ********* *•• *••••• * .... *** **** *** .... ********* ****** .. ** *** ******* ********** .... *' .. I
*'*'
*'*'
=
=
=
#define
WERRMSK
OXlO
#define
WRITERR
OXlO
#deflne
VLOWMASK
OXOB
#define
VPPLOW
OXOB
,.,"
,.
,","
,"
.,.,."'"'"'
"'"'
'" Status Register data that has been already read from the
,.
2BFOOBSA in function end ()
"'
"
Mask to isolate the byte write error bit of the
Status Register
Status Register value after masking if byte write error
/*
has been detected
Mask to isolate the Vpp status bit of the
Status Register
1* Status Register value after masking i f Vpp 10..
has been detected
int writechk(statdata)
byte statdata;
i t (( statdata & VLOWMASK) == VPPLOW)
return (1);
i t (( statdata & WERRMSK)
return (2);
return (0);
/* Vpp low detect error. return code "1" .
= WRITERR)
/* Byte write error detect, return code "2"
" Byte,string write success, return code '0'
"'
.,
"'"'
Routine writebgn( ) issues a byte write command sequence to a 28FOO8SA. It is passed the desired system address for
the byte to be written, as well as the data to be written there. After calling idread( ), it writes the byte write command
sequence at the specified address. It returns "0" if byte write initiation was successful, and "I" if the ID read fails
(device not powered up or RP# not disabled).
Routine writechk( ) takes the Status Register data read in end() and further analyzes it. It returns "0" if byte write
was successful, ,"I" ifVpp low error was detected, and "2" if byte write error was reported. This is useful after a byte
or string of bytes has been written, to check for successful completion.
I
3-577
AP-360
'',."'***************************************************************************************************/
**
'*
*'*'
''**
=
*'*'
,.
,.
,.
Function. Idread
Description. Reads the manufacturer and device IDs from the target 28F008SA
Inputs.
None
Outputs. mfgrid. Returned manufacturer ID
deviceid. Returned device ID
Returns. 0
ID read correct
1 = Wrong or no ID
Device Read Mode on Return. Intelligent Identifier
*'
"'
*'*'
.,
*'*'
*'*'
/*****************************************************************************************************/
Ddefine
MFGRADDR
#define
DEVICADD
1
#define
#define
#define
#def1ne
IDRDCOMM
INTELID
DVCID
DVCID2
OX90
OX89
OXOA2
OXOAl
0
'*
'*
Address '0' for the target 28F008SA ••• alterable depending .,
'*
on the system architecture
'* Address '1' for the target 28F008SA ... alterable depending .,
1*
on the system architecture
Inteligent Identifier command
'* Manufacturer ID for Intel devices
'* Device IDs for 28F008SA
int idread(mfgrid,deviceid)
,*'*
'*
byte *mfgrid;
The
manufacturer ID read by this function, to be
transferred back to the calling program
'* The device ID read by this function, to be transferred
back to the calling function
byte *deviceid;
byte far *tempaddr;
'* Pointer address variable used to read IDs
tempaddr
(byte far *) MFGRADDR ;
*tempaddr
IDRDCOMM;
'* Write Intelligent Identifier command to an address within
'*
the 28F008SA memory map (in this case 00 hex)
*mfgrid
*tempaddr;
'* Read mfgr ID, tempaddr still points at address "0'
tempaddr
(byte far *)DEVICADD; '* Point to address '1" for the device specific ID
"deviceid
*tempaddr;
'* Read device ID
i f «*mfgrid 1= INTELID)
«*deviceid 1= DVCID) &Ie (*deviceid 1= DVCID2»)
return (1);
return (0);
1* 10 read error; device powered up?
*'*'"'
*'
*'
*'
*'
*'
*'
*'
*./
Routine idread() issues the Intelligent Identifier command to a 2BFOOBSA. It passes back the manufacturer and
device· IDs it reads. In addition, it returns "0" if the IDs read· matched those expected for the 2BFOOBSA or
2BFOOBSA-L, and "I" if either the manufacturer or device IDs did not match.
3-578
I
AP-360
*'
*'*'
*'
*'*'
*'*'
1***************************************************** ************************************************/
Function: Statrd
Description: Returns contents of the target 28F008SA Status Register
*'
Inputs:
None
Outputs: ·statdata: Returned Status Register data
/*
Returns: Nothing
*/
Device Read Mode on Return: Status Register
/***************************************************** ************************************************1
#define
STATREAD OX70
Read Status Register command
#define
SYSADDR
0
This constant can be initialized to any address within
the memory map of the target 28F008SA and is
/*
al terable depending on the system architecture
1*
'*
/*
'*
'*
''**
'*
int statrd(statdata)
'*
byte *statdata;
'* Allows Status Register data to be passed back to the
calling program for further analysiS
byte far *stataddr;
/* Pointer variable used to write commands to device
=
=
stataddr
(byte far *)SYSADDR;
*stataddr
STATREAD;
/* Write Read Status Register command to 28F008SA
*statdata = *stataddr;
return;
*'*'
*'
*'
*'
*'*'
/*****************************************************************************************************/
/*
Function: Statclr
'*
Description: Clears the 28F008SA Status Register
*'
'*
Inputs:
None
*'
'*
Outputs: None
'*
Returns: Nothing
1*
Device Read Mode on Return: Array
*'
/*****************************************************************************************************/
#deflne
#define
STATCLER
SYSADDR
OX50
0
'*
'* Clear Status Register command
This constant can be initialized to any address within
the memory map of the target 28F008SA and is
alterable depending on the system architecture
'j
/* Pointer variable used to write commands to device
*'
*'
int statclr ()
byte far *stataddr;
stataddr
*stataddr
return;
= (byte far
= STATCLER;
*'*'
*'
/*
/*
*)SYSADDR;
'* Write Clear Status Register command to 28F008SA
Routine statrd( ) reads a 28FOO8SA Status Register. It issues the Read Status Register command and passes back the
data it obtains.
Routine statclr( ) issues the Clear Status Register command to a 28FOO8SA. This routine is required after analyzing
Status Register contents in routines like eraschk( ) and writechk(). The 28F008SA Status Register retains state of
bits 3-6 until they are cleared by the Clear Status Register command.
I
3·579
AP-360
1***************************************************** ************************************************/
f*
Functi on: Rdmode
*f
f*
Description: Puts the target 28F008SA in Read Array Mode. This function might be used, for *f
1*
example, to prepare the system for return to code execution out of the Flash
*1
f*
memory after byte write or block erase algorithms have been executed off-chip
*f
f*
Inputs:
None
*f
f*
Outputs: None
*f
f*
Returns: Nothing
*f
f*
Device Read Mode on Return: Array
*f
1***************************************************** ************************************************/
#define
#define
RDARRA Y
SYSADDR
OXFF
0
f*
f*
f*
f*
Read Array command
This constant can be initialized to any address within
the memory map ,of the target 28F008SA and is
alterable depending on the system architecture
*f
*f
*f
*f
f*
Pointer variable used to write commands to the device
*f
int rdmode ()
byte far *tempaddr;
tempaddr
*tempaddr
return;
(byte far *)SYSADDR;
RDARRAY;
f* Write Read Array command to 28F008SA
*f
1***************************************************** ************************************************/
/*
Function: R d b y t e '
*f
f*
Description: Reads a byte of data from a specified address and returns it to the
*f
/*
calling program
*f
Inputs:
raddr: Target address to be read from
*/
Outputs: rdata: Data at the specified address
*f
Returns: Nothing
*f
1*
Device Read Mode on Return: Array
*f
/***************************************************** ************************************************1
/*
1*
f*
#define
RDARRAY
OXFF
int rdbyte (rdata, raddr)
byte *rdata;
byte far *raddr;
*raddr
= RDARRAY;
*rdata
return;
= *raddr;
f*
Read array command
*f
f*
f*
Returns data read from the ~evice at specified address
Raddr is the target address to be read from
*f
*f
1* Write read array command to an address within the
f*
28F008SA (in this case the target address)
f* Read from the specified address and store
*f
*f
*f
Routine rdmode() simply puts a 28FOO8SA in Read Array mode. This is useful after byte write and block erase
operations, to return the 28F008SA to its "normal" mode of operation. After block erase or byte write, the
28FOO8SA will continue to output Status Register data until the Read Array command is issued to it, for example.
Routine rdbyte() not only puts the 28F008SA in Read Array mode, it also reads a byte of data. It is passed the
desired system byte address, and passes back the data at that address.
3-580
I
AP-360
'*
/********************************************************************,********************************/
,.
,.
,.
1*
1*
1*
Function: Vppup
Description: Ramps the Vpp supply to the target 28F008SA to enable byte write or block
erase. This routine can be tailored to the individual system architecture. For
purposes of this example, I assumed that a system Control Register existed' at
system address 20000 hex, with the following definitions:
.,
.,
*'*'
*'
*'*'
1*
'*
1*
1*
,.
,.
,.
/*
.,
.,
.,
.,
.,
.,
Inputs:
None
.,
Outputs: None
Returns: Nothing
.,
Device Read Mode on Return: As existed before entering the function. Part is now ready for *'
program or erase
*I
/*****************************************************************************************************/
#define
#define
VPPHIGH
SYSCADDR
OX80
OX20000
1* Bit 7
=
1, Vpp elevated to Vpph
/* Assumed system Control Register Address
.,.,
int vppup()
byte far *contaddr;
'* Pointer variable used to write data to the system
'*
Control Register
(byte far .) SYSCADDR;
*contaddr I VPPHIGH; '* Read current Control Register data, "OR' with
constant to ramp Vpp
1*
contaddr
*contaddr
return;
*'*'
*'*'
*'
/*****************************************************************************************************/
'*
'*
''**
Function: Vppdown
Description: Ramps down the Vpp supply to the target 28F008SA to disable byte write,block
erase. See above for a description of the assumed system Control Register.
Inputs:
None
Outputs: None
Returns: Nothing
Device Read Mode on Return: As existed before entering the function. Part now has high Vpp
disabled. If byte write or block erase was in progress when this function was
called, it will complete unsuccessfully with Vpp low error in the
Status Register.
#define
#define
VPPDWN
SYSCADDR
'*
1*
'*
1*
'*
'*
*'
*'
*'
*'
*'
*'*'
*'
*'
/*****************************************************************************************************/
OX7F
OX20000
'* Bit 7 = 0, Vpp lowered to Vppl
'* Assumed system Control Register Address
*'*'
'* Pointer variable used to write data to the system
'*
Control Register
*'*'
*'*'
int vppdown ( )
byte far *con,taddr;
=
contaddr
(byte far *)SYSCADDR;
*Qontaddr = *contaddr &: VPPDWN; '* Read current Control Register data, "AND" with
constant to lower Vpp
return;
'*
Functions vppup() and vppdown() give examples of how to control via software the hardware that enables or
disables l2V Vpp to a 28FOO8SA. The actual hardware implementation chosen will drive any modification of these
routines.
I
3-581
AP-360
*. *'.
/* III III * *' * If:,. ** *III *.* *' *' * *' *' *' * III * *' *' *' *' .. III ****' **' III '" **' *' *' 101 **' *',. *' *' *' *' III *' * *' .** * III *III III ** .. *' *' *' *' * III *' III'" ** ..•'. *III III **' III III" III *' III *' III If:" *' III I
Function: Pwden
"'
Description: Toggles the 28F008SA RP# pin low to·put the device in Deep PowerDown mode.
"'
See above for a description of the assumed system Control Register.
*'
'"
Inputs:
None·
.,
Outputs: None
.,
1*
Returns: Nothing
.,
Device Read Mode on Return: The part is powered down. If byte write or block erase was in .,
'*
progress when this fUnction was called, it will abort with resulting partially"
written or erased data. Recovery in the form of repeat of byte write or block
.,
erase will be required once the part transitions out of powerdown, to
"'
'*
initialize data to a known state.
*'
1* III *' *' .. *' **.... *' lie *' .... *' .. *' *' III * * III III *' *' .... III * * **' *' III" *' *.. III *' *III "".* .... * .. III III * .. *' III III. III" ~ *' III *.. III III III *' *'.., **' ***' * lie *.. *' *' III *' *' *' **' III III *. * .. III * III III *' III" I
''**
'*
'*
'*
''**
#define
#define
PWD
SYSCADDR
OX40
OX20000
=
'*
'* Bit 6 1, RP# enabled
Assumed·system Control Register Address
int pwden()
byte far *contaddr;
'*
'*
contaddr
*contaddr
Pointer variable used to write data to the system
Control Register
(byte far *)SYSCADDR;
*contaddr I PWD; '* Read current Control Register data, 'OR" with oonstant
'*
to enable Deep PowerDoyo
=
*'*'
. *'
*'
.,
return;
/********************************************************************II;c************** •• ********** •• ****/
'*
'*
'*
'*
1*
'*
''**
'*
Function: Pwddis
Description: Toggies the 28F008SA RP# pin high to transition the part out of Deep
PowerDowo. See above for a description of the assumed system Control Register.
Inputs:
None
Outputs: None
Returns: Nothing
Device Read Mode on Return: Read Array mode. Low voltage is removed from the RP# pin.
28F008SA output pins will output valid data time tPHQV after the RP# pin
transitions high (reference the datasheet AC Read Characteristics) assuming
valid states on all other control and power supply pins.
'*
/* *,!If III *... **.... III""" * *...... III .. If!: *.. * .... _* "' .... ., ...... *' III * .... * III * .... III *.. III III *.......... **........ III
#define
#define
PWDOFF
SYSCADDR
OXBF
OX20000
*.
contaddr
*contaddr
=
'* Bit 6
0, RP# disabled
'* Assumed system Control Register Address
return;
'* Pointer variable used to write data· to the system
'*
Control Register
= (byte far *) SYSCADDR;
= ocontaddr &: PWDOFF; 1*
,0·
*'*'
*'
*'
*'
* ...... III"" III III""" III"" **-*. **.. ****. ***.* *I
int pwddis (,)
byte far *contaddr;
.,
*'
.,
.,
*'
Read current Control Register data, "AND" with
constant to disable Deep PowerDoyo
*'*'
.,
*'
*'*'
Functions pwden( ) and pwddis( ) give examples of how to control via software the hardware that enables or disables
a 28FOO8SA RP # input. The actual hardware implementation chosen will drive any modification of these routines.
3·582
I
Ap·360
ADDITIONAL INFORMATION
AP-359
AP-364
ER-27
ER-28
28F008SA Datasheet
28F008SA-L Datasheet
"28F008SA Hardware Interfacing"
"28F008SA Automation and Algorithms"
"The Intel 28F008SA Flash Memory"
"ETOX-III Flash Memory Technology"
Order Number
290429
290435
292094
292099
294011
294012
REVISION HISTORY
Number
I
Description
002
Revised Erase Suspend Algorithm in "C" Drivers.
003
PWD# pin renamed RP# to match JEDEC standards.
3-583
int:et
AP-362
APPLICATION
NOTE
Implementing Mobile PC
Designs Using High Density
FlashFile™ Components
DON VERNER
SENIOR APPLICATIONS ENGINEER
March 1994
3·585
IMPLEMENTING MOBILE PC DESIGNS USING HIGH
DENSITY FlashFile™ COMPONENTS
CONTENTS
PAGE
1.0 INTRODUCTION ................... 3-587
1.1 Why A New Memory
Architecture ....................... 3-587
1.2 The Flash Memory Alternative ... 3-588
CONTENTS
PAGE
3.3 XIP GUI Implementation ......... 3-603
3.4 Chipset Considerations ., ........ 3-603
3.5 SL Based Design ................ 3-603
3.6 Schematic Overview ............. 3-604
2.0 SOFTWARE DESiGN .............. 3-589
2.1 XIP Operating System ........... 3-589
4.0 SOFTWARE UTILITIES ............ 3-605
2.2 DOS In Flash Implementation .... 3-590
2.3 Resident Flash Disk .......•..... 3-592
4.2 RFA Binary Loader .............. 3-606
2.3.1 Microsoft's Flashfile
System ........................ 3-593
2.4 Resident Flash Disk (RFD) and
ExCA Architecture ................ 3-593
2.4.1 ExCA Software Interface .... 3-594
2.4.2 RFD Socket Services ....... 3-596
4.1 RFA Diagnostic .................. 3-605
5.0 SUMMARY . ........................ 3-606
APPENDIX A: Additional
Publications ........................ 3-607
APPENDIX B: MS DOS ROM Image
Description ......................... 3-609
2.4.3 ExCA Card Services ........ 3-596
APPENDIX C: ROM DISK CONFIG.SYS
and AUTOEXEC.BAT ............... 3-611
2.4.4 iCARD29 File System
Driver .......................... 3-596
2.4.5 RFD Socket Services ....... 3-597
APPENDIX D: Windows 3.1
CONTENTS.ROM .................... 3-613
2.5 XIP Graphical Users Interface
(GUI) Overview ................... 3-597
2.6 XIP GUI Implementation ......... 3-598
APPENDIX E: EPLD Equations ........ 3-619
APPENDIX F: RFA Schematics ....... 3-631
2.7 Pen Extensions .................. 3-599
3.0 HARDWARE ....................... 3-599
3.1 Resident Flash Disk
Implementation ................... 3-599
3.2 XIP DOS Implementation ........ 3-601
3-586
I
AP-362
1.0 INTRODUCTION
As personal computers migrate to platforms that are
easily held with one hand, a revolutionary system architecture is required to meet space and power requirements.
• An architecture that is not bounded by what has
been done before with existing memory architecture,
but free to meet the demanding requirements of mobile end users.
• An architecture free to adapt and accommodate new
technological advances in software and hardware,
while protecting end-users initial base hardware investment.
Implementing this new system architecture requires
traditional PC storage media such as ROM, DRAM,
floppy disk and hard disk to move aside and make
room for the latest in memory storage, Intel's
FlashFile™ memory (see architecture comparison in
Figure 1.).
Application
A
Dete
Code
File & Code
Manipulation
Execution
Storage
DRAM
DRAM/ROM
FDD/HDD
Desktops
J!!l
Portables
Memory and I/O cards complement this new mobile
architecture by integrating many of the common but
functionally separate tasks used by today's mobile professional in either electronic or paper form. Some of
these tasks are schedule keepers, phones, address
books, checkbooks, credit cards, fax, pagers, personal
voice storage, task managers/schedulers, paperless
form reports, scratch pads, and notepads.
1.1 Why A New Memory
Architecture?
The ideal hand held memory system is:
DRAM
FLASH
FLASH
- Resident Disk
- Flash Cord
- Flash Drive
292097-1
Figure 1_ Architecture Comparison
By combining FlashFile memory with new system architecture, completely new types of computers are now
possible that fit in the palm of your hand and replace or
integrate many of the code or storage functions of other
memory types. Moreover, FlashFile memory enables
hand-held computers to last many hours on just a couple of AA batteries. FlashFile memory can be used for
storing e~ecute- !n-flace (XIP) code in the system's
memory map, while additionally functioning like a disk
for file and program storage. Since this type of design
features FlashFile memory resident on the PC's motherboard and is typically arranged in an array, it is described as a Resident Flash Array (or RFA). To further
differentiate the two tasks of an RFA, the file store task
is called a Resident ;Elash .Qisk (RFD), while the XIP
task is called Resident ;Elash for ~IP (or RFX) code
storage.
I
The FlashFile memory is also used in card form as
specified by the Personal Computer Memory Card International Association (PCMCIA). Flash memory
cards provide file and program storage similar to an
RFD, but add the feature of removability, increasing or
adding to ease-of-use for the end user. The PCMCIA
specification addresses both the memory and I/O
card's physical, electrical and mechanical characteristics, while leaving the host PC implementation relatively free for interpretation. Enhancing the PCMCIA
specification, Intel developed the Exchangeable Card
Architecture (ExCATM), which defines the host PC
system card interface. ExCA further refines the
PCMCIA specification and provides for card exchangeability and inter-operability for both memory and I/O
cards.
• Power Conscious (prolongs battery life and reduces
heat)
• Dense (stores lots of code and data in a small
amount of space but weighs very little)
• Updateable (allows in-situ code enhancements)
• Fast (lets you read and write data quickly)
• Inexpensive (low cost per megabyte)
o Reliable (retains data when exposed to extreme temperature and mechanical shock)
Since the PC's introduction over 10 years ago, designers have grappled with how to construct memory systems that met the above criteria. Portable computing
makes the system design even tougher with more stringent requirements for low power, low volume and less
weight. The best combination available for portable designs in their infancy was the same as used for the desktop; solid-state memory and magnetic storage, i.e.,
SRAMs, DRAMS plus magnetic hard disks. DRAMs
are dense and inexpensive, yet slower than the processors they serve, and they are volatile. SRAMs, although
fast enough to keep pace with processors, are relegated
to caching schemes (compensating for DRAM's slowness) due to low density and high cost while also being
volatile. Magnetic hard disks, the nonvolatile append-
3-587
AP-362
age to DRAM and SRAM, are dense, inexpensive on a
cost-per-megabyte basis and nonvolatile, but are slow,
power hungry, take up a sizable amount of volume and
are susceptible to damage from physical shock.
Fast
1.2 The Flash Memory Alternative
Don't be misled by technology-to-technology speed
comparisons. Architecting a system around FlashFile
memory bypasses the code/data bottleneck created by
connecting slow mechanical serial memory (such as
disks) to a high-performance, parallel-bussed processor
system. For example, data seek time for a 1.8" magnetic hard disk is 20 ms, plus an 8 ms average rotational
delay, while flash memory access time is less than
0.1 ms. At the chip level, read speeds for FlashFile
memory are about 85 nS. Therefore, either direct execution of code from flash memory or downloading to system RAM will dramatically enhance overall system
performance.
High Density
Nonvolatile
Mobile computing designs cannot depend on hard
drives as portable notebook PCs do. Volume (4" x 8 x
0.5" or less), power (two AAs), and shock constraints
. preclude using even the 1.3" hard drives available
today. Also, vitally important data such as credit card
numbers or transactions, signatures, or checkbook
information demands reliability of the highest order.
Intel's ETOX III Flash Memory Cell is 30% smaller
than equivalent DRAM cells; therefore it will closely
track DRAM density. Intel's 28FOO8SA FlashFile
Memory can store 8 megabits, or one megabyte, of
. data. Flash memory is more scaleable than DRAM because the flash storage cell is not sensitive to soft error
failure, therefore it can have a more simple cell structure. Thus as density increases and process lithography
continues to shrink, flash memory will pace and ultimately overtake the DRAM technology treadmill.
Updatable
ROMs and EPROMs may offer lower device costs, but
if servicing the customer or end-user is important to an
OEM, overall system cost must be factored in. Although ROMs and EPROMs are nonvolatile, changing
the code within them is either very difficult (in the case
of EPROMs) or entirely impossible (in the case of
ROMs). Whole inventories of ROMs could be lost in
the event of a catastrophic bug, while an innovative
design with FlashFile memory can be updated in the
factory or by end-users via networks, OEM Bulletin
Board Systems, or other memory cards. Updating systems could actually become a second source of income
for OEMs and Independent Software Vendors, enhancing the quality of the product while increasing end-user
satisfaction.
Power Conscious
Intel's FlashFile memory provides a deep powerdown
mode, reducing power consumption to typically less
than 0.2 JAoA. Typical read current is only 20 mA while
typical standby current (flash memory not being accessed with CE# high) is only 30 JAoA. Additionally,
FlashFile devices operating at 3.3 Vee are available for
state-of-the-art low power consumption designs.
3-588
Unlike DRAM or SRAM, FlashFile memory requires
no battery backup. Further, Intel's flash devices retain
data typically for over 100 years, well beyond th~ useful
lifetime of even the most advanced computer.
Rugged and Reliable
On average, today's hard-disk drives can withstand up
to 10 Gs of operating shock; Intel's FlashFile memory
can withstand as much as 1000 Gs. FlashFile components can operate beyond 70·C while magnetic drives
are limited to 55·C. Intel's FlashFile Memory can be
cycled 100,000 times per block or segment. Even beyond that cycle level, FlashFile does not fail or lock up
like EEPROM devices, it just tends to take longer to
erase blocks and program bytes than the times specified
in the data sheet. By employing wear-leveling techniques, a 10 KB file written every 5 minutes, 24 hours a
day to a 20 MB flash array takes 1.2 million hours or
136 years before reaching the 10,000 cycle level.
Many applications benefit from ROMed or XIP versions of code, particularly hand held personal computers, vertical application pen-based clipboards, and industrial control and data accumulation equipment.
These applications pose system design constraints requiring small form factor, low power consumption, and
ruggedized construction due to active mobile users or
harsh environments. Exposure to shock, vibration, or
temperature extremes is common, precluding the use of
rotating media. Flash memory provides an excellent
code storage choice for such system designs featuring
thin TSOP packaging, low (deep powerdown mode) or
zero (capability to shut off power without losing data)
power consumption, and 1000 G shock resistance and
extended temperature products. Additionally flash
memory provides remote or end-user update capability
over ROMs, allowing OEM's to service their products
more efficiently and add new software features and applications after the sale.
I
AP-362
The features of Intel's FlashFile memory truly enables
new, compact and portable system architecture. This
application note discusses implementing just such a design using Intel's boot block flash memory and Intel's
FlashFile (28F008SA) components for extended memory eXecute-In-Place (XIP) code store, disk-like functionality for file and program storage, and BIOS code
storage.
Related Publications
The following data books and reference manuals provide valuable information for developing an RFAbased design:
• Intel 28FOO8SA Data Sheet Order number 290429
• Microsoft MS-DOS 5.00 ROM Technical Specification and OEM Adaptation Kit (OAK)
• Microsoft Flash Filing System OAK
• Microsoft Windows 3.1 ROM Technical Specification and OAK
For additional information on flash memory, power
supply solutions and EPLDs, see Appendix A.
2.0 SOFTWARE DESIGN
Software design is considered first for solid-state designs because the software functionality desired affects
in large part how the hardware design is implemented.
Many software products exist for solid-state systems:
• DOS operating systems from Microsoft, Novell's
Palm DOS and DataIight's ROM-DOS
• A Graphical User Interface (GUI) operating system
in Windows 3.1 ROM version
• Application software from Microsoft (such as
Word, Excel and MS-Works) and Lotus 1-2-3 Version 2.2.
Because no standardization exists, implementation differs from package to package or vendor to vendor.
Therefore, this application note describes a system using MS DOS ROM Version, MS Flash Filing System,
Windows 3.1 ROM Version plus Pen extensions. All
are readily available applications today and offer the
highest inter-compatibility. However, the hardware and
software design concepts presented here work just as,
well with Novell's (formally DRI) Palm DOS and also
GO Corporation's Penpoint operating systems.
2.1
XIP Operating System
The first decision one must make for a solid-state software design is the operating system. Many alternatives
exist for small hand held computer systems. Any solution depends on what requirements are placed on desktop compatibility, software compatibility, and ease of
I
developing applications. In the pen-based market, DOS
compatibility is not necessarily a requirement. This is
evident by the multiple emerging entries of pen-based
GUI's. However, data transfer using a medium such as
memory cards between desktop systems and hand held
computers depends on an agreed file format. At least
for now, DOS is still the major operating system of
choice for the largest number of desktop systems.
Therefore, DOS compatibility is still a necessity for
many hand held computing systems and is incorporated
in this design.
To insure compatibility and easy system integration,
MS DOS 5.0 ROM Version is the easiest choice. With
this version, an XIP DOS implementation can be configured to as small as 64 KB using just the Runtime
Kernel and a minimized command interpreter. If
CONFIG.SYS and AUTOEXEC.BAT processing is required, an additional 56 KB are required plus a ROM
DISK large enough to hold AUTOEXEC.BAT,
CONFIG.SYS, and any drivers and files that are referenced by either file.
Microsoft provided the capability for additional XIP
DOS applications to be added to an MS DOS XIP implementation by providing two new DOS functions,
"Find First ROM Program" and "Find Next ROM
Program." This allows DOS-based XIP applications
(such as OEM-specific utilities and applications or Embedded DOS applications) to easily be added to the MS
DOS 5 ROM build.
Many different memory configurations MS-DOS ROM
are possible by distributing various software pieces (Microsoft refers to them as granules) between different
ROM locations below and above the 1 MB address
space. Certain restrictions exist on individual granules
requiring them to appear below 1 MB. The granules
and address location requirements are specified in a table within the MS DOS ROM 5.0 OAK. Approximately 43 KB of granules must be located below the first
1 MB of address space. Other granules can be located
either below or above 1 MB. The total size of all granules in this design is approximately 128 KB.
How MS DOS ROM Boots Up
For system startup and booting DOS without a disk,
MS DOS 5 ROM must intercept the INT 19h call made
by the BIOS. This is accomplished by locating a granule as an adapter ROM within adapter space (COOOOhEFFFFh). This granule contains the ROM scan identifier "55AAh" which must appear on a 2 KB boundary
and identifies the module as a ROM to the BIOS during Power On Self-Test (POST), and also identifies the
MS DOS 5 ROM INT 19h interceptor. When the BIOS
Post code identifies the ROM, control is turned over to
the ROM for its initialization. At this time, the MS
DOS 5 ROM redirects the INT 19h vector to the MS
DOS 5 ROM code and control returns back to the
3-589
AP-362
BIOS POST code.· When the BIOS is completely finished testing and initializing, it issues INT 19h, and the
MS DOS 5 ROM INT 19h handler gains control. The
handler loads the MS DOS 5 ROM bootstrap loader
into RAM and passes control to it. If the bootstrap
loader includes the "Multi-Boot" option, a list of menu
boot options are presented to the user if an OEM defined key is being pressed. The menu might look like
Figure 2.
Booting from a disk:
. 1.
Boot from Floppy Disk.
2.
Boot from Hard Disk
Booting from ROM:
3.
Floppy is default; process startup files.
4.
Hard drive is default; process startup files.
5.
Floppy is default; do not process startup files.
6.
Hard drive is default; do not process startup files.
7.
ROM drive is default; process startup files.
Figure 2. Multi-.Boot Menu
The menu is activated by pressing the ALT key during
the system memory scan, which is the default provided
in the OAK. Other types of keys may be selected by the
OEM for: their specific implementation. Selecting the
options under Booting from a disk will bypass the
ROM system completely. Selecting the options under
Booting from ROM will invoke MS DOS 5 ROM and
whatever the option specifies for processing the startup
files, CONFIG.SYS and AUTOEXEC.BAT.
If the Multi-Boot option is not available or is not activated by the user, the MS DOS 5 ROM bootstrap loader reads a byte from CMOS RAM to determine boot
options. The byte is defined in Figure 3.
Reserved
7104
1
Default 1 DefaUlt.1
ROM
Drive If
Drive If
CONFIG.SYS
ROM Boot
ROM Boot
ProcessIng
3
2
~_ D:o:~
f I
t
1
0
If the system is to boot from ROM by either selecting
the Multi-Boot option or reading the CMOS byte, the
MS DOS 5 ROM bootstrap loader loads BIOS (note:
not system BIOS, but the BIOS layer of MS DOS) and
DOS initialization granules into RAM, records the adc
dresses of the resident BIOS and DOS code granules in
the BIOS data area, records boot options (default drive,
CONFIG.SYS & AUTOEXEC.BAT processing) in the
BIOS data area, and passes control to BIOS initialization. Just before the end of BIOS initialization, control
is passed to SYSINIT which moves itself and DOS data
and initialization code to high memory where both
SYSINIT and DOS initialization takes place. Next
SYSINlT then reads and processes the CONFIG.SYS
file where installed drivers called in CONFIG.SYS and
additional elements of the DPB chain will be placed in
memory following the existing DOS structures as well
as system buffers allocated. At this point, system bootstrap is finished and the command interpreter is started
using the DOS call to execute ROM utilities. If a full
command processor is chosen, the user will now see
"C: >" prompt.
2.2 DOS In Flash Implementation
For this particular implementation, a full version ofMS
DOS with the full Command processor was chosen.
This configuration uses 64 KB of adapter space (upper
memory) at EOOOOh to EFFFFh for MS-DOS 5 ROM,
and a combination 64 KB XIP binary file and a 256 KB
ROM Disk binary file located in extended memory at
F90000h. See Figure 4. ROM DOS and ROM Disk
Memory Maps. This location is just after the end of the
XIP GUI code block. The 64 KB XIP Binary contains
the transient portion of COMMAND. COM and the
DOS BIOS initialization and is created during the build
of the MS DOS 5 ROM system, while the 256 K.B
ROM Drive contains the necessary files for bringing up
the system and loading the MS Flash File System drivers which is addressed in the next section.
Default Boot Bit 0:
0- Boot from ROM
1- Normal disk boot operation (first is drive 00, then drive 80)
ROM Configuration Processing Bit 1:
0- Process CONFIG.SYS and AUTOEXEC.BAT from default drive
1- Do NOT process CONFIG.SYS or AUTO EXEC. BAT files
Default Drive if ROM Boot Bits 2 & 3:
00· First Floppy Drive (Oh)
01· First Hard Drive (80h)
10- ROM Drive
Figure 3. CMOS Byte Definitions
3-590
I
AP-362
ISA Address Map
1-16 MB ISA Address Map
FFFFFh
FFFFFFh
FOOOOh
EOOOOh
CFFFFh
CCOOOh
1------1
C7FFFh
F90000h
COOOOh
1------1
BOOOOh
1------1
AOOOOh
1------1
XIP GUI
COOOOOh
1--'-----1
640 KB User RAM
00000
FFFFF L -_ _ _ _..I
292097-3
292097-2
Figure 4. ROM DOS and ROM Disk Memory Maps
The EOOOOh segment was chosen because it happens to
be free on the flash BIOS storage chip. Also, later on in
this design we will be adding an RFD, which uses up
the whole DOOOOh segment, and ExCA which requires
16 KB of adapter space that we located at CCOOOh (see
Figure 4 for a memory map). The ROM disk image
location was chosen because there was room available
in the extended XIP portion. The XIP portion is located at COOOOOh (12 MB) due to compatibility reasons·
with the 386SL processor and SL window constraints. ,
In a non-SL desigO., the ROM disk portion of MS DOS
ROM can be located anywhere in extended memory
above 1 MB.
taken for building a ROM version of DOS is taken
from the MS-DOS 5.00 ROM OAK. Please refer to the
MS-DOS 5.00 ROM OAK for specific details.
There are a set of compile options specified in the MS
DOS 5 ROM OAK that need to be defmed by the
OEM for their particular implementation and are contained in the OAK file named "VERSION.lNC". The
compile options used for this example are listed as follows:
A copy of the ROM image description file is included
in Appendix B. The following summarizes the steps
I
3-591
AP-362
ROMDOS equ TRUE
POWER equ FALSE
ROMDRIVE equ TRUE
CMOS equ TRUE
CONFIGPROC equ TRUE
For this application this means that for:
"ROMDOS"
- a ROMDOS build (as opposed
to DISK build simulation) is
used
"POWER"
- the MS DOS APM and power
management are NOT used
"ROMDRIVE" - the compiler will use the internal
ROMDRIVE drivers
"CMOS"
- forces MS DOS 5 ROM to look
at the CMOS byte if the MultiBoot option is not chosen
"CONFIGPROC" - normal CONFIG.SYS and
AUTOEXEC.BAT processing
will be used
Since we are planning to use a ROM DRIVE, MS DOS
5 ROM needs to know where the ROM DRIVE exists.
To set the ROM drive base address, the MS DOS 5
ROM OAK file ROMRDHI.ASM must be modified.
Edit the file and set the ROMDRIVERBASE_LO
equal to OOOOh and the ROMDRIVERBASE_HI
equal to OFAh, or 64 KB above the base address of the
extended memory XIP module.
Now the MS DOS ROM binaries are ready for building. Using the MS NMK utility, 3 separate binary files
are compiled based on the requirements and addresses
specified in the MS-DOS ROM Image Description file
in Appendix B. ROM binary files I and 2 can be combined into one 64 KB binary image as follows:
copy Ib ROM1.BIN + ROM2.BIN ROMDOS5.BIN
Once the XIP binaries are built, the rest of the ROM
disk needs to be built. First, specify a RAM Drive within your build or development PC using the MS DOS
RAMDRIVE.SYS device driver as follows:
This will create a 327 KB binary file with both XIP
DOS code and the ROM Disk code for a single load
into flash memory.
Loading the ROMDOS5.BIN file into the system's
flash BIOS chip requires the use of a BIOS Independent
Software Vendor's (ISV) Flash Update Utility. Most
major BIOS ISVs now offer such utilities. If your particular system design uses a BIOS developed internally,
refer to Intel's AP-341 "Designing an Updatable BIOS
Using FLASH Memory" (order number 292077) for
more information on flash BIOS designs and related
software.
Loading the ROMDISK.BIN file requires developing a
DOS-based utility to access flash memory in Protected
Mode. Creating this utility is discussed under Section
4.0, Software Utilities, subsection 4.2 Binary Loader.
2.3 Resident Flash Disk
Once a DOS-based, XIP operating system is in place,
the next area to work on is file storage for flash memo. ry. File storage is possible with either FlashFile components or FlashFile cards, since they appear the same to
file. system software. However, the characteristics of
flash memory are very unlike magnetic storage media
characteristics. File Allocation Table (FAT)-based systems rely on the fact that the operating system has unrestricted write capability and/or access to the media,
particularly when updating the FAT for a file creation,
update or deletion. Flash memory on the other hand,
does not necessarily allow write access 100% of the
time. When the flash memory media is completely
erased (all FFh's), writing data to the media can occur
at any time and at any location. Additional data writes
within the same block but at different locations can also
occur. However, once a bit is written to a zero (Ob),
erasure of the whole block is required before allowing
that particular bit to change back to one (Ib). This
asymmetrical characteristic of flash memory prevents
using a straight implementation of the FAT-based file
architecture and requires an alternative file system implementation to take advantage of Flash Memory benefits.
device=RAMDRIVE.SYS 256/e
Blocking
After rebooting your PC, copy the files needed for your
particular application. For an example of CONFIG.SYS and AUTOEXEC.BAT files, see Appendix
C. Change the drive label as per the MS DOS 5 OAK
instructions and then use the MS DOS IMGET utility
to capture the image of the RAM drive into a binary
file. Next, concatenate the ROM3.BIN binary image
created by the NMK with the ROM Disk image captured from the RAM drive by using the MS DOS copy
command as stated earlier:
Intel's FlashFile memory offers 64 KB separately erasable blocks enhancing the use of flash memory as a file
storage medium. The large block size (as opposed to
512 byte blocks or sectors) provides the system with
fewer total blocks to manage, resulting in less system
overhead used for file management. Additionally, large
blocks reduce file fragmentation since large files will
most likely be contained in one block as opposed to
several 512 byte sectors. This reduced fragmentation
copy Ib ROM3.BIN + RDISK.BIN ROMDSK.BIN
3-592
I
Ap·362
also improves read performance since files are more
likely to be intact with a Flash File System vs. a FAT
file system. These features led to the creation of Microsoft's Flash Filing System.
the block with the remainder of the space available for
directory, file control structures and file data storage.
The File System Driver also determines when de-allocated space (deleted files or directories) within a block
is reclaimed for re-use.
2.3.1 MICROSOFT'S FLASH FILING SYSTEM
The device driver portion is OEM-modifiable and needs
to be written for the specific hardware example used.
This device driver, specifically called iCARD29, is covered in more detail in the next section, ExCA Architecture, under iCARDDRV File System Driver Summary.
The only MS FlashFile System hardware requirement
is a single window available per socket in a system's
adapter space that addresses all the flash memory to be
used. Window size and base address are left to the system designer to decide, based on system design requirements. Some hardware guidelines are:
• Register-defined window size of either 4 KB, 8 KB,
16 KB, or 32 KB
• Register-defined base address in adapter space
(COOOOh to DFFFFh)
To enhance the use of flash memory as a disk, Microsoft created the Flash Filing System. This file system
operates as a list of linked lists while keeping track of
individual block erasure and file deletions, using minimal system overhead. File allocation structures use indirectly linked lists, allowing the file system to update
files and data within the files without first requiring the
area where the file is located to be erased and then
updated. During file deletion, a file's header structure is
written to mark the file as deleted, removing the file
from the file allocation listing. Once the array of flash
memory contains a majority of deleted files, the file
system performs a (background) cleanup operation and
copies good files out to free blocks and erases the blocks
with all the deleted files. This achieves the goal of the
user being able to use flash memory the same as they
would use any other mass storage media without doing
anything different.
Three distinct parts comprise the file system organization and implementation:
A File System Redirector, whose job is to intercept
the disk operations passed to MS DOS by an application and translate them into generic file operations, passing them on to the file system driver.
- A File System Driver, which accepts generic file
operations passed to it from the File System Redirector, implements the architecture and logic of the
Microsoft Flash Filing System, and passes low-level
commands such as read, write, copy, and erase to
the device driver.
A Device Driver, which accepts low-level commands from the File System Driver and interfaces
to the host system hardware implementation.
The File System Redirector performs a task analogous
to a network redirector for LAN (Local Area Network)
systems and appends itself to MS DOS. Any applications then think they are running from a networked file.
Some classes of applications and utilities will not operate via this interface. Specifically, those applications
that issue the INT 13h disk BIOS I/O call, INT 25h
DosAbsRead, or INT 26h DosAbsWrite calls will not
work properly with the Flash Filing system, just as they
would not work over a network LAN. The File System
Driver treats the flash media as a collection of large
blocks, all identical in size. Individual block statistics
are kept within a variable length structure at the top of
I
For more detailed information on Microsoft's Flash
Filing System, consult the Microsoft Flash Filing System OAK.
2.4 Resident Flash Disk (RFD) and
ExCA Architecture
Many systems which use an RFA will also want to
incorporate PCMCIA memory and I/O cards. If an
RFD uses the same software architecture used for
PCMCIA cards, less software duplication is present in
systems containing both cards· and RFDs. This section
discusses the Intel Exchangeable Card Architecture
(ExCA) as it applies to an RFD and a Flash Filing
system.
Most of this section was excerpted from the ExCA 1.1
Specification. The reader is encouraged to obtain that
document for more details not revealed in this discussion. Other documents are the PCMCIA PC Card
Standard Release 2.0, the PCMCIA Card Services Interface Specification, and the PCMCIA Socket Services
Interface Specification Release 2.0.
ExCA specifies a standard host system hardware and
software interface for 68 pin, PCMCIA/JEIDA memory and I/O cards. ExCA Release 1.10 defines the minimum hardware and software interfaces that card and
system designers can rely on for basic compatibility
across PC Cards, systems, and related software. By defining these interfaces, ExCA makes the PCMCIA goal
of PC Card inter-operability a reality.
3-593
AP-362
2.4.1 ExCA SOFTWARE INTERFACE
The primary purpose of the ExCA Software Interface is
to explicitly define a minimal set of socket control and
resource access functions upon which higher-level PC
Card Client device drivers can rely. A PCMCIA implementor may incorporate a range of functions beyond
the basic Memory Card Interface specified in PCMCIA
1.0. For PCMCIA 2.0, three primary functional extensions to the specification exist. They are: I/O devices,
L-XIP-mapped memory ("L" stands for LIM or Lotus,
Intel, Microsoft), and E-XIP-mapped memory ("E"
stands for Extended or Protected mode memory).
While basic memory requirements can be met with a
single, small memory-mapped window or even via an
I/O approach, both XIP modes require direct-mapping
interface capability, with very specific boundaries in the
L-XIP mode. Without an ExCA-like hardware and
software support for direct-mapped memory, XIP-formatted cards cannot function. The ExCA socket hard. ware .. and software specifications define basic, clear
compatibility definitions for PC cards, software drivers,
and host systems.
3-594
ExCA allows PC Cards and sockets to be accessed by
multiple PCMCIA-aware device drivers,. configuration
utilities and applications, with efficient and non-conflicting use of system resources. An architectural diagram of ExCA functionality is shown in Figure 5. The
primary components of the software interface are Socket Services and Card Services. Socket Services provides
the lowest-level function set for socket hardware adapter control. Card Services allocates resources and coordinates PC Card-related activities for higher-level client
device drivers.
I
AP-362
MS Flash Filing System
(FLASH.SYS)
DOS Device Driver
iCARD29.EXE
r----~----.-
------ ---
Card
Services
ExCA™ Defined
Software
82365SL™
Socket
Services
RFA Flash Disk
Socket Services
292097-4
Figure 5. By using the same software architecture used
for PCMCIA cards, less software duplication is present in systems
containing both cards and Resident Flash Disks.
I
3-595
Ap·362
2.4.2 ExCA SOCKET SERVICES
ExCA Socket Services is the lowest-level software interface that directly controls PC Card sockets. Socket
Services defines a software interface to manipulate
socket adapter hardware in a way that is independent of
hardware implementation. Socket Services defines several abstract resources which can be manipulated. An
Adapter is the hardware that supports connecting one
or more 68-pin PCMCIA Sockets to a host system, or
in the case of a resident flash disk, the hardware that
supports a memory interface only. A Socket is the
hardware that supports a single 68-pin PCMCIA connector. A Window is the hardware that supports mapping a region Of system memory or 1/0 address space
to a region of card memory or 1/0 address space. A
Card is a PCMCIA card that is inserted into a socket.
Example functions are: configure a socket for an 1/0 or
memory interface, control socket power voltages and
make callbacks for PC Card insertion and status changes.
Socket Services handlers use minimal RAM so that
they will fit within a ROM-BIOS. The Socket Services
interface can be used during POST, and must be ROMresident to support' booting from a PC Card. The interface is accessed via an 8086-compatible register-based
protocol, and invoked through software interrupt lAh,
with functions starting at 80h. This interrupt is shared
with the real-time CMOS Clock Driver. The Socket
Services software interrupt is called with the proper settings in the host processor's registers. The functions
returns status via the Carry flag and registers specific to
the function invoked.
Multiple hardware socket adapter interfaces can be
supported by chaining multiple Socket Services handlers. This includes providing Socket Services support
for motherboard-resident flash memory arrays by treating the control circuitry and memory array as if it were
a PC Card single socketlcard combination.
2.4.3 ExCA CARD SERVICES
Card Services is the interface used to manipulate
ExCA-related system resources. Card Services is subdivided into five functional categories: Client Services,
Resource Management, Client Utilities, Bulk Memory
Services, and Advanced Client Services. Client Services
provide for client initialization and the callback registration of clients. Resource Management provides basic
access to available system resources, combining knowledge of the current status of system resources with the
underlying Socket, Services adapter control functions.
Client Utilities perform common tasks required by clients so that functions, such as CIS (Card Information
3-596
Structure) tuple access, do not need to be duplicated in
each of the client device drivers. Bulk Memory Services provide read, write, copy, and erase memory functions for use by file systems or other generic memory
clients that need to be isolated from memory hardware
details. Advanced Client Services provide specific functions (or clients with special needs.
Card Services provide a packet-based request interface
(i.e., uses a block of RAM for passing inputs and outputs between the caller and the interface) which provides a standard protocol for PC Card client device
drivers to access cards and their required system resources. It provides separate registration and callbacks
for card insertion and card status change event notifications, allowing associated client device drivers to take
the appropriate actions. For file system read, write,
erase and copy operations, a special interface is provided forMemory Technology Drivers (MTDs) which can
handle the details of different memory technologies.
NOTE:
This interface is not used by iCARD29. Instead, the
MTD functions are built into iCARD29.
Resource Management provides a protocol for sharing
resources within an environment, where previously the
end-user was responsible for resolving resource con- ,
flicts. Resource Management resolves resource contentions without end-user interaction.
Advanced Client Services contains a RetumSSEntry
function which is essentially a direct bypass to Socket
Services. Card Services require Socket Services to manipulate PC Cards and socket hardware. ExCA client
drivers should typically interact directly with Card
Services and not Socket Services.
Card Services is typically implemented as a device driver. Card Services provides function number AFh in the
Socket Services interrupt lAh interface for real-mode
operation. During initialization, Card Services determines the state of the host environment. This includes
determining available system memory, available I/O
ports, IRQ assignments, installed PC Cards and socket
state. How this is performed is implementation specific.
2.4.4 iCARD29 FILE SYSTEM DRIVER
iCARDRV2.EXE is an Intel developed, low-level, flash
memory driver for the MS Flash Filing System. It provides read, write, copy, and erase functions within the
ExCA architecture and interfaces'to a PCMCIA standard Card Services 2.0 (which provides proper resburce
arbitration). iCARD29 is completely independent of
other peer .level drivers and performs no direct calls to
I
AP-362
Socket Services. Support for Intel's Series I and Series 2
flash memory cards and the RFA flash disk is provided. iCARD29 is also used to read ROM cards and
read/write SRAM cards.
2.4.5 RFD SOCKET SERVICES
RFD "SocketServices" functions similar to ExCA
SocketServices in that the software interface to manipulate socket adapter hardware is preserved, but an RFD
SocketServices does not control any sockets or cards or
respond to card removal and insertion events. RFD
SocketServices allows a resident flash disk implementation, through chipset logic or external logic, to appear
to ExCA software and the system as another Adapter
using a single Window mechanism, accessing permanently installed flash memory on a motherboard. All
the rest of ExCA SocketServices functions are kept as
they relate to this definition. An example of a nonworking RFD SocketServices function is using it to
configure an I/O card. If requested to complete such an
operation, RFA SocketServices will respond with
"Function not supported."
For more information on the specific hardware design
used for a Resident Flash Disk, refer to Section 3.5.
2.5 XIP Graphical Users Interface
(GUI) Overview
Many GUIs exist today, but not all are configured to
run in a minimized XIP mode for portables. Some designs may implement a simple DOS-based pen interface
on top of an XIP DOS, like Communications Intelligence Corporation's PenDOS·, and add a single application like a forms recorder. Other designs may not use
XIP DOS at all and the system design revolves around
the XIP GUI requirements alone.
Microsoft leads the rest of the software industry in XIP
GUI development, releasing the Windows 3.1 ROM
Development Kit in September of 1992 and recently
introducing the Modular Windows Development Kit in
January of 1993. Both are XIP GUI implementations
of the Windows GUI Operating System and are fully
modularized for OEM configuration. Modularization
assists OEMs by simplifying the streamlining of an
O/S's suitability to task by allowing the OEM to
choose which functions are important and required for
a particular design and which functions can be left out.
Benefits to the OEM are:
- Preserved API for using existing Windows applications or new application development
- Reduced development time and costs by using standard Windows application development tools and a
wide choice of Windows software developers
- Ease of use for end-user
I
Modular Windows
Microsoft's Modular Windows Operating System uses a
subset of the Windows 3.1 Operating System and includes extensions supporting TV-based multimedia
players. Target market is home entertainment, but
could easily be adapted for machine control on factory
floors. The differences between Modular Windows and
Windows 3.1 ROM are summarized below:
- Reduced support for the Windows 3.1 application
programming interface (API)
- Reduced support for Windows 3.1 extension libraries
- New user-interface controls (instead of pull-down
menus)
- New support for hand-control input devices
Software requirements are:
• MS DOS 5.0 in XIP form
System requirements are:
• 80286 or greater CPU
• I MB RAM minimum
• I MB of XIP memory (Flash, EPROM, or ROM)
Since the focus of this application note is personal computers, Sub-Notebooks and below, Modular Windows
implementations will not be discussed. However, many
of the principles of putting Modular Windows code in
flash memory (memory maps, software tools, flash updatability, etc.) .are the same here as the Windows 3.1
ROM example which is discussed later in this section.
Windows 3.1 ROM Version
Computers running Windows in ROM or XIP mode
are very similar to standard PC running disk-based
Windows. The only major exception is the presence of a
large amount of XIP code storage in extended memory
from which Windows executes, and a smaller amount
of XIP code storage in adapter space. For the rest of
this discussion, the Windows XIP code stored in extended memory is referred to as HIROM.BIN and the
small amount of Windows XIP code stored in Real
Mode space is referred to as LOROM.BIN.
Two modes of operation are possible for XIP Windows;
Standard and Enhanced, just as on disk-based PCs.
However, each require different system resources for
the XIP Windows version.
3-597
AP-362
For Standard Mode, Windows executes fully in ROM,
leaving almost all the system RAM available for user
programs. This means that all Windows "core code"
including DOSX.EXE, USER.EXE, GDI, the Windows kernel and all drivers run from XIP storage
space. Also, all shell programs, applets, fonts and other
Windows resources are stored in and run from XIP
storage space without being loaded into RAM.
Enhanced Mode Windows must execute partially from
RAM. Enhanced Mode components such as
WIN386.EXE and VxDs (virtual device drivers) must
be loaded into RAM from some type of disk (a flash
disk, ROM disk, or flash card) for execution, as their
code writes back to their execution location from time
to time and creates errors if loaded into XIP code storage such as flash memory. Components shared between
modes, specifically USER.EXE, GDI, the kernel and
drivers, continue to run from their stored locations in
XIP address space.
Additionally, for either Standard or Enhanced modes,
all Windows 3.1 features are supported in XIP Windows. The only limiting factors are the amounts of
available RAM, XIP storage and, in the case ,of Enhanced mode, disk space.
file directories, XIP Windows returns "Application
missing, fIle not found." Additions of other extensions
to the XIP image such as multimedia support and Pen
.Windows are added in a similar manner. .
2.6 XIP GUllmplementatlon
As mentioned earlier, XIP Windows requires two modules; a small amount of XIP storage in device adapter
space called LOROM.BIN, and a larger amount ofXIP
storage called HIROM.BIN in extended' memory
space. The LOROM.BIN file contains information
about the modules loaded in the HIROM.BIN XIP (see
Figure 6) image and must be accessed in real mode by
three modules, WIN. COM, RSWAP.EXE, and
WIN386.EXE. Additionally, portions of the DOS extender (DOSX.EXE) must be able to run in real mode
and are therefore located in the LOROM.BIN XIP
image. The information the three modules look for is
contained in the ROM Table Of Contents (ROMTOC),
also located in LOROM.BIN and contains general information aboiltboth XIP images (small and large),
entry point addresses for initialization, and Ii list of the
executables stored in theJarge XIP image.
FFFFFFh
Adding Applications
FF8000h
The Windows 3.1 ROM Development Kit (RDK) can
add, any' Windows executable program or application
into the main XIP binary image fIle HIROM.BIN. The
application must conform to the XIP application requirements specified in the Windows 3.1 Technical
Specification. Microsoft is capable of supplying XIP
versions of Word for Windows, Excel, Microsoft Mail
and Microsoft Works but must be developed between
, an OEM 'and Microsoft on a platform-by-platform basis.
F90000h
COOOOOh
FFFFFh
1-------1
CBFFFh
C8000h
OhL-_ _ _ _ _...I
Once the O/S and application functionality is determined and the build script CONTENTS.ROM edited,
the RDK produces two binary images:' the large
HIROM.BIN ,Extended mode image containing O/S
and application code, and the small Real mode
LOROM.BIN image containing the listing of all the
XIP code contained in HIROM.BIN. After both XIP
Windows binary fIles are loaded into flash memory and
the system is up and running, clicking on an application
causes the XIP Windows kernel to search its internal
listing (LOROM.BIN) for an XIP image module first.
If the image is not found within the XIP listing, the
Windows kernel then searches the fIle paths present at
runtime to try and load the application from its current
fIle directories. If the program is not found within
3-598
292097-5
Figure 6. 16 MByte XIP GUI Memory Map
The extended memory XIP image contains the bulk of
the system's code and data segments, EXE headers, and
a prototype Lqcal Descriptor Table (LDT) which is a
data structure defining the addresses; sizes and types of
segments used by 80286, Inte1386™, or Inte1486TM
processors. For. more infotmation on a Windows 3.1
XIP-based system, please refer to the Microsoft Windows 3.1 ROM Development Kit.
I
AP-362
Software Requirements
• MS DOS S.O or equivalent in XIP mode
• Software Utility to load both small and large XIP
images into flash memory
• For Enhanced Mode disk space requirements, MS
Flash Filing System 2.0 combined with ExCA software for a Resident flash disk.
lection of pen recognizer drivers come bundled in the
SDK provide for fast development of a pen-based system. In particular, the Wacom PL-l00V pen tablet and
VGA graphics card can be added to an ISA bus slot for
early debug and pen software development.
All the Pen Windows extensions are directly executable
within the HIRaM XIP image and can be added to the
CONTENTS. ROM listing.
System Requirements
• 80286 CPU or greater
• RAM: Minimum of I MB for Standard Mode or
2 MB for Enhanced mode
• XIP Store: Minimum of 2 MB for Standard Mode,
3 + MB for Enhanced mode
• Flash Disk Store: Zero for Standard Mode, 2 MB
for Enhanced mode
For this particular design example, Enhanced mode
functionality is used to show a full implementation of
Windows. An RFD is used to load WIN386.EXE,
VxDs and all the ".INI and ".GRP files. A complete
listing of the CONTENTS. ROM file used by the Windows ROM Image Builder utility to create an XIP
Windows system is shown in Appendix D. The Windows RDK Enhanced Full sample CONTENTS. ROM
file is used as a template and edited to locate the
LOROM.BIN file at C8000h and is. a total of 16 KB.
The HIROM.BIN file is located at COOOOOh and is a
total of 3.6 MB.
2.7 Pen Extensions
Microsoft's Windows for Pen Computing is an extension to Microsoft Windows version 3.1 and has its own
SDK. Pen Windows Extensions do not require any
changes to existing Windows 3.1 applications and a se-
I
3.0 HARDWARE
This section describes the general hardware requirements for an RFA design, then discusses a specific implementation using the SL architecture as an example
(primarily due to the built-in ISA Sliding Window) ..
Many of the concepts presented here can easily be incorporated into new chipsets designs to take advantage
of the benefits flash memory brings to solid-state designs.
3.1 Resident Flash Disk
Implementation
As stated in Section 2.3, the MS Flash Filing System
requires a hardware mapping window in Real Mode
address space. This window is similar in function to an
EMS mapping window, but unlike EMS this window
interfaces directly to flash memory. The SL Superset
provides an example of just such a mapping, using in
the ISA Sliding Window. The window is configured via
the SL's ISAWINDOW register and has a fixed base
address of DOOOOh and a fixed size of 64 KB. By setting
the correct address in the register, the full 16 MB ISA
address space is viewable in 64 KB increments. Additionally, the register defines access to the 16 MB flash
disk address space made available by a separate flash
disk Chipse1ect (see Figure 7).
3-599
Ap·362
FFFFFh . . . . - - - - - - - - ,
AT STD
64 K8
8105
FOOOOh
64 K8
- - - -- EOOOOh
9FFFFFh
1 - - - - - - - -.......
Flash Disk
Window
64 K8
DOOOOh...
,,
4 82365SL
Windows
16 K8
q:OOOh
16 K8
,,
200000h
1---------1"
C8000h
VGA Video BIOS
32 K8
VGA Graphics
64 KB
COOOOh
80000h
I-------~
AOOOOh
t--------I
Mono Text
64 KB
640 K8 DRAM
User Space
292097-6
Figure 7. Flash Disk Mapping
3-600
I
AP-362
· Although the built-in functionality of the ISA Sliding
Window is quite nice, the large 64 KB footprint of the
window in Real Mode address space is difficult to work
around. For a non-SL implementation, smaller, more
flexible sliding windows are possible through external
logic (FPGAs or EPLDs) or hopefully from future PC
chipsets desiring to provide the capability the flash
memory offers. The hardware requirements are simply:
1. A Window base address that appears in Real Mode
memory somewhere in adapter space (COOOOh to
DFFFFh) that is also register definable.
2. A Window size that is also register definable for
either 4 KB, 8 KB, 16 KB, or 32 KB.
These two options provide a level of flexibility for an
OEM's system implementation and reduces the memory footprint in adapter space.
The flash disk address mapping in Figure 7 shows the
flash disk and ISA bus address maps together. The SL's
ISA Sliding window allows 64 KB blocks of the flash
disk address space to be mapped into the Real mode
area from DOOOOh to DFFFFFh for access by the MS
FlashFile System. For some ideas on how to implement
an external logic flash disk implementation, see AP-343
"Solutions for High Density Applications Using Intel
Flash Memory," order number 292079. The application
note describes a complete design for an ISA Bus add-in
card. A local bus design can be derived from the ISA
Bus implementation or the SL implementation logic
discussed in Section 3.6, Schematic Overview.
3.2 XIP DOS Implementation
As stated in Section 2.2 DOS in Flash Implementation,
MS DOS 5.0 ROM Version is built assuming the
EOOOOh segment location and also consists of a ROM
Disk located in extended memory at F90000h. The only
reason for the ROM disk location is to avoid 386SL co-
I
processor errata at the 8 MB location and window base
address constraints, which must be divisible by the window size in use. In non-SL designs, the ROM Disk can
be located anywhere above 1 MB in a NON-cacheable
region. The design example uses Intel's 2 Mb,
28F002BX-T boot block flash memory. This device is
organized with varying sized blocks; a 16 KB hardware
lockable boot block, two 8 KB separately erasable Parameter Blocks, and separately erasable 96 KB .and
128 KB main code blocks. To unlock and allow programming and erasure of the boot block, an additional
12V must be applied to the PWD# pin, thereby guaranteeing hardware protection. The benefit of using boot
block architecture is that in the unlikely event that
something happens during a BIOS code update, the system can recover using the kernel code in the boot block
to iuitialize enough of the system to access a floppy
drive or memory card socket to load in BIOS update
code and a BIOS binary file.
Using a 2 Mb (256 KB) device enables the design to use
a single memory chip for 4 separate code modules: the
standard AT compatibility BIOS (64 KB), MS DOS 5.0
ROM (64 KB), Video BIOS (32 KB), and Power Management Code (32 KB). The sum of all 4 modules is
greater than 128 KB and if mapped straight down from
the top of the 1 MB address space, could cover both the
BIOS and all of the adapter space. To avoid this conflict, some chipset designs physically position the BIOS
function at the top of the 16 MB memory map, then use
64 KB mapping windows to position the correct block
between EOOOOh and FFFFFh.
The SL Superset provides a second BIOS ROM chipselect enabling only one 128 KB portion to appear at
EOOOOh to FFFFFh at a time. Additionally, the SL Superset provides an ISA Sliding Window which ~owed
windowed access into protected mode space. Figure 8
shows how each module is mapped into the boot block
flash memory.
3-601
AP·362
System
r-------.......,
Address
System
Address
OrrrrrH
128KB
LOGICALLY
LOCATED
BELOW 1 MB
128 KB Main Block
HIDDEN FROM
,1 MB VIEW,
292097-7
Figure 8. Boot Block Mapping
The boot block flash memory chip is physically located
at the top of the 16 MB address space, but the SL Superset logically locates the top 128 KB of the chip irito
Real Mode address space just below 1 MB. Additionally, an exclusive OR gate is tied to the highest order
address lirie, flipping the 2 Mb boot block chip at its
mid point. This places the locked boot block just under
the first 128 KB of the part, while the other 128 KB
containing the AT System BIOS and MS DOS 5.0
ROM appears at the top of the device. This is done to
position the boot block (which contains BIOS recovery
code) out of the IBM BIOS compatibility table area,
allowing access to the AT System BIOS and MS DOS
ROM code.
3-602
When the system boots, the processor jumps to the AT
BIOS location by default. As the system is booting, the
BIOS enables the ISA Slidirig Wiridow to access the
other 128 KB of boot block flash memory, and proceeds to copy the Power Management code to its s~
cia! location within the System Management Mode
space. Next, the BIOS copies the Video BIOS code into
shadow memory at COOOOh to C7FFFh and turns off
the ISA Sliding Window. The BIOS then scans the MS
DOS 5.0 ROM adapter code, and allows MS DOS
ROM to hook INT 19h, and finishes the rest of its
POST before turning control over to DOS by issuing
INT 19h.
I
AP-362
3.3 XIP GUI Implementation
As stated earlier, Windows 3.1 ROM Version takes up
about 3.6 MB of extended address space
(HIROM.BIN) and 16 KB of Real mode adapter address space (LOROM.BIN). HIROM.BlN can be located anywhere above 1 MB and should probably be
high enough above the DRAM address space to allow
additional DRAM to be added to the system by the
end-user. Ideally, the system design should be able to
cache the area where the Windows HIROM XIP code
is located. This allows the system to take advantage of
XIP code locality since XIP code should produce a
very high cache hit ratio. Since the 28FOO8SA FlashFile memory is a x8 device, x16 access is accomplished
by pairing two devices for a LOW Byte HIGH Byte
configuration. This creates an erasable block size of
128 KB.
The LOROM.BIN file has a couple of implementation
options. One method is to use a spare block out of the
extended memory XIP region. This method requires
external logic to decode the specific adapter space address dedicated to the LOROM function, and generate
a chipselect to the last block of flash memory. Since the
'LOROM.BIN file size is only 16 KB and the smallest
erasable block size is 128 KB, 112 KB of the block is
left unused. Given that the HIROM and LOROM files
are updated together, the HIROM file could feasibly
use the extra space if necessary.
Another option for the LOROM file is to use some free
storage space within the 2 Mb boot block flash memory
chip. The file could then be copied to the correct adapter space shadow RAM location at boot time. Copying
the LOROM.BIN file can occur at the same time that
Video BIOS and Power Management code are copied.
This method provides update capability while reducing
external logic requirements. The only hinge factor is
getting the system's BIOS code to copy the file before
or during POST.
Either option is possible. The choice is dependent on
determining which is easier, modifying hardware or
modifying a BIOS bootup process.
3.4 Chipset Considerations
Chipset designers interested in implementing an RFAready chipset should consider the following recommendations for RFA hardware requirements:
Flash BIOS> 128 KByte
• Minimally, include a Flip Bit on the highest order
address line. This allows 128 KB pages to move in
and out of the same 128 KB address space.
I
• Position the BIOS at the top of 16 MB or 32 MB
address space, keeping the flip bit and include a window mapping mechanism similar to an EMS-like
window. This window provides temporary Real
mode access of the 2nd 128 KB of BIOS code storage.
RFD Functionality
• Include a built-in Flash disk Chipselect to minimize
external logic
• Add an EMS-like mapping window
- Register defined, base address between COOOOh
and DFFFFh
Register defined window size adjustable 4 KB,
8 KB, 16 KB, and 32 KB
Register address capability to 64 MB RFD
XIP Code Functionality
o Include a built-in XIP Flash Chipselect
.. Add 2 register defined, cacheable windows
- Adjustable base address anywhere above 1 MB
- Size adjustable 2 MB, 4 MB, or 8 MB
3.5 Sl Based Design
Lacking an off-the-shelf, RFA-ready chipset and system, an SL Superset design is used as an example. To
achieve as close to local bus access times as possible, the
SL's Peripheral Interface (PI) Bus is used, The PI Bus
is asynchronous and runs a CPU cycles plus one additional wait state.
To position the FlashFile memory on the PI Bus into
the system's address map, a spare Video Window register (GABCR) is used (see Figure 9). For the design
example, a base address of COOOOOh is used combined
with a window size of 4 MB. The COOOOOh base address
avoids some conflicts with 386SL systems at the 8 MB
address location. Since the GABCRs window base address must be divisible by its size, the 12 MB address
made the most sense (avoiding the 8 MB location)
while being high enough to allow at least 8 MB of system RAM. For any other XIP system design, any base
address should be usable. Although the GABCR register positions the FlashFile memory correctly and routes
all system address map accesses to COOOOOh to
FFFFFFh to the PI Bus, by the fact that the GABCR
is a graphics window, it is defined as a non-cacheable
window.
• Include a cache enable/disable bit within the register
These requirements work for non-Intel architecture just
as well as for the Intel architecture.
3-603
AP-362
FFFFFFFFh , . . . . . - - - - - - - ,
OFFFFFFh
,,
,
I
OFFFFFFh
Windows 3.1
LOROM.BIN
Windows 3.1
LOROM.BIN
128 KB
FF8000h
.. --
....
128 KB
FF8000h
327 KB
Logical XIP
Locations
16 MByte PI-Bus
Address Plane
256 KB
F90000h
F90000h
EXECUTABLE
CODE AREA
"HIROM.BIN"
3.9 MByte
,,
,
Physical XIP
Locations
3.9 MByte
,
I
I
COO DOh
GABCR
Window
40000h
1--------1
1OOODOh
1---'------1
Extended Mode
DRAM
Real Mode
DRAM
292097-8
3.6 Schematic Overview
Appendix F contains schematics for the SL Superset
example design. This section reviews the major portions
of the schematic.
Even though the SL Superset provides a flash disk Window and Chipselect, two EPLDs are needed to decode
the flash disk Chipselect from Video Chipselects, while
the XIP flash memory required externally generated
chipselects. Additional logic is also needed to decode
the LOROM.BIN stub at CCOOOh and route the access
to the highest block of XIP Memory.
The RFA example design uses both an Intel 85C090-15
and an Intel 5AC312-25 EPLD to provide board con-
3-604
trol logic. This logic generates flash memory chip enables, flash memory control signals, ROM Stub decoding, PI bus cycle decoding and bus cycle termination,
and enables the mode registers. For details on the
EPLD equations, see Appendix E.
85C090
The Intel 85C090 also controls the mix between how
much flash memory is used for Resident Flash Disk
Memory (FDM) and how much flash Disk Memory
(RFD) and how much flash memory is used for XIP
Memory. The EPLD description files in Appendix E
show how to change the equations to obtain the desired
mix needed for any particular OEM's implementation.
I
AP-362
5AC312 Mode Registers
The SAC312 provides two registers to control Vpp,
power down, and the Ready Interrupt. The registers
are written and read with PI Bus Memory cycles to the
upper 64 KB of the Flash Disk Address Plane. This
space is otherwise unused; no flash memory resides
there. Address assignments in the flash disk plane are
as follows:
FFOOOOh Power Control Register (Wt/Rd)
FFOOO2h Interrupt Control Register (Wt/Rd)
FFOOO4h (Reserved)
FFOOO6h Clear Flash Disk Memory READY
Interrupt (Wt only)
The Clear Flash disk Memory READY Interrupt is not
used with FlashFile System 1.0. It is intended to be
used with the next file system from Microsoft. The
above assignments alias every 8 Bytes (4 words) up to
FFFFFEh.
The Power Control Register bits are defined as follows:
Bit
Enable all Flash Memory Vpp
o
(if jumper E9-E1 0 installed)
(Reserved; reads as a zero)
2
(Reserved; reads as a zero)
Power Down all flash memory
3
4-15
Undefined
The Interrupt Control Register bits are defined as follows:
Bit
o Enable Flash Memory READY Interrupt
1
Flash Memory READY Interrupt (Read only)
2
Flash Memory Any Zone Busy (Read only)
3
(Reserved; reads as zero)
4-15 Undefined
Reserved bits should be written as zeroes; they will read
as zeroes. Undefined bits should be written as zeroes;
they may read as either zeroes or ones.
Cold boot (RSTDRV) clears all defined bits in the register. Warm boot (CTRL-ALT-DEL) does not affect
the contents of the register.
A major power consumer on the RFA example design
board is the 8SC090 EPLD. This is due to using Turbo
Mode to quickly decode the PI Bus signals and minimize RFA access time. Unfortunately, this causes a
constant current draw of 160 rnA. The EPLD's Normal
mode cannot be used since there is no advance warning
of an XIP flash memory access.
PRDY # Enable Jumper
The PI Bus signal PRDY # has a very weak pull-up
resistor on the motherboard. Consequently, it has to be
driven high (inactive) for a short time at the end of each
cycle. Timing for this logic comes from the early taps
on the delay line as follows:
100 Nanosecond delay line
(SXTTLDM-121 )E4-ES
200 Nanosecond delay line
(SXTTLDM-12S)E4-E3
Power Control
The purpose of the SMOUT4 signal was to allow the
RFA Daughter board to perform a local standby, powering down various devices on the RFA Daughter
board. However, since the EPLD must remain powered
on until Global suspend, and consumes a high amount
of current compared to the FlashFile power consumption, local standby was not implemented.
4.0 SOFTWARE UTILITIES
A few software utilities need to be created to load the
binaries created for XIP code implementations.
4.1 RF A Diagnostic
It is highly recommended that system designers develop
simple diagnostic tools to test the hardware at a very
low level (i.e., write byte, write word, read word, erase
block). Such a tool proves invaluable when debugging
new hardware and software designs and resolving hardware and software conflicts.
The Flash Memory READY interrupt is cleared by
writing to address FFOOO6h in the flash disk Address
plane. The data written is not interpreted; it should be
all zeros.
I
3-605
intet®
Ap·362
4.2 RFA Binary Loader
The RFA Binary mes HIROM.BIN, LOROM.BIN,
and ROM Disk must all be loaded into Protected Mode
from Real Mode. This can be accomplished a number
of ways:
1. Use a DOS Extender. This provides a quick method
to create a utility using the tools a DOS extender
provides. However, licensing may prove to be difficult or expensive.
2. Using BIOS-based extended memory calls. These
actually worked quite nicely and reliably, but
proved to be slow and doubled the time to erase and
program HIROM.BIN.
3. Putting the processor in flat mode. This method allows for fast, direct access to the extended memory,
but cannot be done under windows.
For lab testing, our binary loader used a simple me
name plus command line parameters. A system for endusers would need a more elaborate user interface to
guide them through the software update. Some basic
software requirements outside of the basic me read!
write capabilities and command line parsing for the
flash memory Binary Loader are:
• Incorporate basic flash memory program and erasure commands. These software drivers are available
for both ASM86 and "C" in Application Note-360
"28FOO8SA" Software Drivers, order number
292095-002. This application note addresses things
like read device identifier, Vpp ramp time, x8 and
x16 parallel programming and block erasure by providing proven, tested routines for each.
3-606
• Choose a method of Protected Mode access that
makes the most sense for you.
• Allow for specific base addresses to be entered by
the user, while within the program automatically determining what block and the number of blocks to
be erased from the base address and binary me size.
5.0 SUMMARY
This application note discussed a new system architecture based on solid-state software and hardware design
concepts. This new architecture is based on using flash
memory for the following; BIOS + DOS code storage,
a nonvolatile RAM disk or RFD, and as XIP GUI
code storage or RFX. Specific flash memory component and PCMCIA card information is found in their
respective datasheets. Contact your local Intel or distribution sales office for more information or to obtain
assistance in evaluating Boot Block or FlashFile memory components, as well as Intel's product line of
PCMCIA Flash Memory Cards.
I
AP·362
APPENDIX A
ADDITIONAL PUBLICATIONS
I
>
Intel "28F008SA Hardware Interfacing" Application Note
Order number 292094
>
Intel "28F008SA Software Drivers" Application Note
Order number 292095
>
Intel "Power Supply' Solutions for Flash Memory" Application Note
Order number 292092
>
Intel 85C090 24-Macrocell CHMOS EPLD
Order number 290247
>
Intel 5AC3I2 12-Macrocell CHMOS EPLD
Order number 290247
292097-9
3-607
AP-362
APPENDIX B
MS DOS ROM IMAGE DESCRIPTION
#####################################################################
#
RFA ROM DOS Description File
# ROM image description file for 64K of ROM space at
#
EOOOO-EFFFF and one 256K ROMDISK module at F90000
#####################################################################
# Actual file sizes created: Three 32K modules
#
#
#
ROM 1=Int 19 hook and Resident DOS Code
ROM 1SIZE=8000
ROMlMAX=7FFF
ROMlTYPE=SEG
ROM I ADDR=EOOO
ROMICHKSUM=YES
ROM I NUMBLOCKS=40
ROM I FILES= ..\romhead\romboot.bin ..\dos\resdos.16
ROM2=COMMAND ROM Hdr Res. BIOS Code Bootstrap loader Resident Command Code
ROM2SIZE=8000
R0M2MAX=7FFF
ROM2TYPE=SEG
R0M2ADDR=E800
ROM2CHKSUM=YES
292097-10
R0M2NUMBLOCKS=40
ROM2FILES= ..\cmd\command\romhead.bin ..\bios\resbio.16 \
.. \romload\romload.sys ..\cmd\command\rescom.16 ..\dos\romdos.sys
ROM3=Command interpreter
ROM3SIZE";10000
ROM3MAX=FFFF
ROM3TYPE=BASE
ROM3ADDR=F90000
ROM3FILES= ..\cmd\command\command.16 ..\bios\rombio.sys
292097-11
I
3-609
AP-362
APPENDIX C
ROMDISK CONFIG.SYS AND AUTOEXEC.BAT
AUTOEXEC.BAT
@echooff
prompt$P$G
set path=c:\;d:\rdk 1O\build\disk;d:\utils;d:\diags;
c:\doskey
doskey d=dir $1 $2
d:\rdk10\build\disk\smartdrv.exe 1024 1024
set TEMP=d:\
ver Ir
echo "MS DOS ROM, Card & Flash Disk SS 2.0, MS FlashFile System 2,"
echo "and Windows 3.1 ROM"
CONFIG.SYS
DEVlCE=c:\HIMEM.SYS
break=on
buffers=40
files=40
lastdrive=H
DOS=HIGH,UMB
REM················································
REM FlashFile System Drivers
. Device=C:\rfaslss.sys
Device=C:\ss36Ssl.exe
Device=C:\cs.exe
Device=C:\rtinit.exe
Device=C:\icard29.exe
Device=C:\ms-f1ash.sYs
REM··················································
I
292097-12
3-611
AP-362
APPENDIX D
WINDOWS 3.1 CONTENTS. ROM
NOTE: Semi-colons denote a commented-out line which is NOT added to the HIROM Binary file .
•••••••••••••••••••••••••••••••••••••••••••••
; Windows 3.1 ROM Development Kit (RDK) 1.0
; Sample ROM Description File
; Copyright Microsoft Corporation, 1992
; Enhanced Mode, Full
; 10/20/92 Removed TT Fonts
ROMS
; Specifies length of ROMs and the linear addresses
; at which they are to appear.
; Name Address Length (max)
LoROM Oc8000 004000 ; 16k
Hi ROM COOOOO 3FFCOO ; 4 Mb
TABLES
; Specifies information for tables to reside in ROM:
100
LoROM
ROMTOC
NUMFILENT 14
LDT
1024 HiROM 256
; WINFLAGS
13
WINFLAGS
15
; SYSDIR
system
ROMVERSION 1000
; ROMTOC entries
; FILES entries
; Local Descriptor Table
; 286 version; Value is in HEX
; 386 version; Value is in HEX
; Windows directory on disk (optional)
; 1 = masked ROM, 000 = OEM version
MODULES
; Specifies modules to be loaded into ROM.
; Format is as follows:
ROM
Flags
; Module SEG File
Comments
; Kernel--------------------------------·
OOSX.EXE
SEG2
%ROMFILES%dosx.exe
HiROM
; Sid mode MS DOS extender
LoROM NOEXEHDR
; DXDGROUP - Copy from ext with !NT 15h
292097-13
I
3-613
AP-362
SEG 3
; KERNEL.EXE
KERNEL.EXE
H i R O M ; DXPMCODE
%ROMRLES%krnI286.exe HiROM
%ROMRLES%krnI386.exe HiROM
;286 kernel
; 386 kernel (ROM version)
; Drivers (Replaceable) - - - - - - - - - - - - ,
SYSTEM.DRV %ROMFILES%system.drv HiROM
KEYBOARD.DRV %ROMFILES%keyboard.drv HiROM
SEG 10 COMP
; Do not remove!
; Display
; VGAROM2.DRV %ROMFILES%vgarom2.drv HiROM
VGAROM3.DRV %ROMFILES%vgarom3.drv HiROM
; SVGAR2.DRV %ROMRLES%svgar2.drv HiROM
; SVGAR3.DRV %ROMFILES%svgar3.drv HiROM
; System
; Keyboard,
;.286 VGA
;386VGA
; 286 SuperVGA
; 386 SuperVGA
MOUSE.DRV %ROMFILES%mouse.drv HiROM
; Mouse
SEG 2 RAM COMP NORELOC
; Do not remove!
; NOMOUSE.DRV %ROMFILES%nomouse.drv HiROM
; No mouse
COMM.DRV
%ROMRLES%comm.drv
SEG 2 RAM COMP NORELOC
'SEG 3COMP
; COM, LPT
; Do not remove!
; Do not remove!
HiROM
MMSOUND.DRV %ROMFILES%mmsound.drv HiROM
; Sound
; Core - - - - - - - - - GDI.EXE
%ROMFILES%gdLexe
HiROM
USER.EXE
%ROMRLES%user.exe
HiROM
SEG 3 RAM COMP NORELOC
; ROM version
; ROM version
; Do not remove!
; Non-Replaceable System DLLs - - - , - - - - - - ,
SHELL.DLL %ROMRLES%shell.dll HiROM
LZEXPAND.DLL %ROMFILES%lzexpand.dll HiRbM
WIN87EM.DLL %ROMRLES%win87em.dll HiROM
; Shell APIs
; Expansion
; Math emulator
; Replaceable System DLLs - - COMMDLG.DLL %ROMFILES%commdlg.dll HiROM STUB
; Common dialogs
OLECLI.DLL %ROMFILES%olecli.dll HiROM STUB
; OLE Client
OLESVR.DLL %ROMFILES%olesvr.dll HiROM STUB
; OLE Server
TOOLHELP.DLL %ROMFILES%toolhelp.dll HiROM STUB
; Tool Help DLL
DDEML.DLL %ROMFILES%ddeml.dll HiROM STUB
; DDE
HiROM STUB
; Version DLL
VER.DLL
%ROMFILES%ver.dll
; Multimedia Extensions - - - - - - MMSYSTEM.DLL %ROMFILES%mmsystem.dll HiROM STUB
; Multimedia
292097-14
3-614
I
AP-362
SND.CPL
%RETAIL%snd.cpl
HiROM
MPLAYER.EXE %RETAIL %mplayer.exe HiROM
SOUNDREC.EXE %RETAIL %soundrec.exe HiROM
; Sound icon
; Media Player
; Sound Recorder
; Advanced Power Management (APM) - - - - - - - - - ; POWER. DRY
%RETAIL%power.drv
HiROM
;APM driver
; Shell Programs - - - - - PROGMAN.EXE %RETAIL%progman.exe HiROM
WINFILE.EXE %RETAIL%winfile.exe HiROM
TASKMAN.EXE %RETAIL%taskman.exe HiROM
WINHELP.EXE %RETAIL%winhelp.exe HiROM
WINTIITOR.EXE %RETAIL%wintutor.exe HiROM
; Control Panel
; Program Mgr
; File Manager
; Task Manager
; Windows Help
; Tutorial
-------------
DRIVERS.CPL %RETAIL%drivers.cpl HiROM
MAlN.CPL
%ROMFILES%main.cpl
HiROM
CONTROL.EXE %RETAIL%control.exe HiROM
; Drivers icon
; Main icons
; Control Panel
; Printing Support - - - - - - - - - - - - - - - - - - - - - ; PRINTMAN.EXE %RETAIL%printman.exe HiROM
; UNIDRY.DLL %ROMFILES%unidrv.dll HiROM
; DMCOLOR.DLL %ROMFILES%dmcolor.dll HiROM
; System Fonts
; Print Mgr
; Uni driver
; Uni driver
-----------------
VGASYS.FON %RETAIL%vgasys.fon
HiROM
VGAFIX.FON %RETAIL%vgafix.fon
HiROM
VGAOEM.FON %RETAIL%vgaoem.fon
HiROM
; System (VGA)
; Fixed pitch
; OEM
; Bitmap Fonts
HiROM
COURE.FON %RETAIL%coure.fon
SERIFE.FON %RETAIL%serife.fon
HiROM
HiROM
SMALLE.FON %RETAIL%smalle.fon
SSERIFE.FON %RETAIL%sserife.fon HiROM
SYMBOLE.FON %RETAIL%symbole.fon HiROM
; Courier (VGA)
; MSSerif (VGA)
; Small (VGA)
; MS Sans Serif(VGA)
; Symbol (VGA)
; Plotter Fonts -.-------------------------MODERN.FON. %RETAIL%modem.fon
HiROM
HiROM
ROMAN.FON %RETAIL%roman.fon
HiROM
SCRIPT.FON %RETAIL%scriptfon
; Modem
; Roman
; Script
; TrueType Fonts - - - .
292097-15
I
3-615
Ap·362
ARIAL.FOT %RETAIL%arial.fot
HiROM
ARIALBD.FOT %RETAIL%arialbd.fot HiROM
ARlALBI.FOT %RETAILo/oarialbi.fot HiROM
ARIALI.FOT %RETAILo/oariali.fot
HiROM
; COUR.FOT
%RETAIL%cour.fot
HiROM
; COURBD.FOT %RETAIL%courbd.fot
HiROM
; COURBI.FOT %RETAIL%courbi.fot
HiROM
; COURI.FOT %RETAIL%couri.fot
HiROM
; SYMBOL.FOT %RETAIL%symbol.fot
HiROM
HiROM
; TIMES.FOT %RETAIL%times.fot
; TIMESBD.FOT %RETAIL%timesbd.fot HiROM
; TIMESBI.FOT %RETAIL%timesbi.fot HiROM
HiROM
; TIMESI.FOT %RETAIL%timesi.fot
WINGDING.FOT %RETAIL%wingding.fot HiROM
;Arial
; Arial Bold
; Arial Bold Italic
; Arial Italic
; Courier New
; Courier New Bold
; Courier New Bold Italic
; Courier New Italic
; Symbol
; Times New Roman
; Times New Roman Bold
; Times New Roman Bold Italic
; Times New Roman Italic
; WingDings
; MS DOS App Support - - - - - - - - - - - - VGA3GR
%RETAIL%vga.3gr
HiROM
; Enh mode grabber
; Std mode MS DOS app support
WINOLDAP.MOD %RETAIL%winoldap.mod HiROM
SEG 2 RAM COMP NORELOC
; Do not remove!
WIN0A386.MOD %RETAIL%winoa386.mod HiROM
; Enh mode MS DOS app support
SEG I RAM COMP NORELOC
; Do not remove!
SEG 2 RAM COMP NORELOC
; Do not remove!
SEG 5 RAM COMP NORELOC
; Do not remove!
DOSAPP.FON %RETAIL%dosapp.fon
HiROM
EGA80WOAFON %RETAIL%ega80woa.fon HiROM
EGA40WOAFON %RETAIL%ega40woa.fon HiROM
CGA80WOAFON %RETAIL%ega80woa.fon HiROM
CGA40WOAFON %RETAIL%cga40woa.fon HiROM
; MS DOS app window fonts
; Applets - - - - - - - - CALC.EXE
%RETAIL%calc.exe
HiROM
CALENDAR.EXE %RETAIL%calendar.exe HiROM
CARDFILE.EXE %RETAIL%cardtile.exe HiROM
CHARMAP.EXE %RETAIL%charmap.exe HiROM
CLIPBRD.EXE %RETAIL%clipbrd.exe HiROM
CLOCK.EXE %RETAIL%clock.exe
HiROM
NOTEPAD.EXE %RETAIL%notepad.exe HiROM
PACKAGER.EXE %RETAIL%packager.exe HiROM
PBRUSH.DLL %RETAIL%pbrush.dll
HiROM
PBRUSH.EXE %RETAIL%pbrush.exe
HiROM
PIFEDIT.EXE %RETAIL%pifedit.exe HiROM
RECORDER.DLL %RETAIL%recorder.dll HiROM
RECORDER.EXE %RETAIL%recorder.exe HiROM
SOL.EXE
%RETAIL%sol.exe
HiROM
; TERMINAL.EXE %RETAIL%terminal.exe HiROM
; Calculator
; Calendar
; Card tile
; Character Map
; Clipboard Viewer
; Clock
; Notepad applet
; Packager applet
; for Paintbrush
; Paintbrush
; PIF Editor
; for RECORDER.EXE
; Recorder
; Solitaire
; Terminal
292097-16
3-616
I
AP-362
WINMINE.EXE %RETAIL%winmine.exe HiROM
WRITE.EXE %RETAIL%write.exe
HiROM
; WinMine
; Write
; Applications - - - - - - -
FILES
; Specifies optional files to be installed into ROM.
; TrueType TTF font files are specified in this section.
; ROM Name
Path
ROM
; TrueType Data - - - - - - - - - - - - - - - - - - - - - ARIAL.TTF %RETAIL%arial.ttf
HiROM
ARlALBD.TTF %RETAIL%arialbd.ttf HiROM
ARlALBI.TTF %RETAIL%arialbi.ttf HiROM
ARlALI.TTF %RETAIL%ariali.ttf HiROM
; COUR.TTF
%RETAIL%cour.ttf
HiROM
; COURBD.TTF %RETAIL%courbd.ttf HiROM
; COURBI.TTF %RETAIL%courbi.ttf HiROM
; COURI.TTF %RETAIL%couri.ttf
HiROM
; SYMBOL.TTF %RETAIL%symbol.ttf HiROM
; TIMES.TTF %RETAIL%times.ttf
HiROM
; TIMESBD.TTF %RETAIL%timesbd.ttf HiROM
; TIMESBI.TTF %RETAIL%timesbLttf HiROM
; TIMESI.TTF %RETAIL%timesLttf HiROM
WINGDING.TTF %RETAIL%wingding.ttf HiROM
; Arial
; Arial Bold
; Arial Bold Italic
; Arial Italic
; Courier New
; Courier New Bold
; Courier New Bold Italic
; Courier New Italic
; Symbol
; Times New Roman
; Times New Roman Bold
; Times New Roman Bold Italic
; Times New Roman Italic
; WingDings
292097-17
I
3-617
AP-362
APPENDIX E
EPLD EQUATIONS
Included below are the equations for both the 8SC090 and the SAC3 I 2 EPLDs. See the RFA Schematic
Diskette for disk-readable *.ADF and *.JED files.
8SC090 EPLD
OPTIONS: TURBO=ON
PART: N8SC090 % PLCC %
%
292097-18
I
3-619
AP-362
This EPLD provides the main control logic of the Resident Flash
Array Evaluation board. The following is included:
Flash Memory chip enables
Modes Register chip enable (RS_CElFLASH_CE5)
ROM Stub control logic
74FCT623 Data Buffer Control
74FCT373 Address Latches Gate control (HOLD#)
WT, WT#, and RD# generation
CN_REV_A - 04/06/92 Initial release
CN _SPC_A - 04/08192 Reconfigured Flash Array to provide 8 Meg
of Flash Disk and 4 Meg of Executable Memory.
CN_SPC_B - 04/29/92 Update to allow byte writes.
CN_REV_B - 06/01192 Added generalize configuration scheme.
%
INPUTS:
DL_OUT@2
% Delay line out (high edge sets PRDY t7f)
%
PM@4
% PI bus Memory or 10#
%
PCMD#@14 % PI bus Command
%
PSTART_DLY#@42 % Delayed PSTART# signal (used to create HOLD#) %
A14@5
% PIIISA bus Latched Addresses
%
A15@19
A16@20
LA17@21
% PIIISA bus Unlatched Addresses
%
LA18@26
LA19@25
LA20@27
LA21@28
LA22@29
LA23@30
MRDC#@3
% ISA bus Memory Read (All 16MByte)
%
VGACS#@13
% VGA Chip Select
%
FLASHDCS#@12 % Flash Disk Chip Select
%
L]W@41
% PI bus PWIR# (latched)
%
EN]ROY@40
% Enable PRDY# driver
%
SAOO@43
% Latched address bit 00
%
SBHE_L#@37 % Latched System Byte High Enable
%
OUTPUTS:
FLASH_CEO#@15 % Flash Memory Zone pairs Chip Selects
FLASH_CEl#@16
FLASH_CE2#@35
%
292097-19
3-620
I
AP-362
FLASH_CE3#@34
FLASH_CE4#@33
FLASH_CES#@32
RS _CE@31
% ROM Stub Chip Select
% Read Strobe
%
RD#@6
WT_L#@l0
% Write Strobe, Lower Byte
WT_U#@8
% Write Strobe, Upper Byte
WT@36
% Write Strobe (Active High for 74F623
HOLD#@7
% Hold Address Latches (close gate)
% HIGH for Sel_RS, else 3-S
SA16@11
DL_IN@38
% Delay line driver
%
PRDY#@9
% PI bus signal
PRDY@18
% D-type flf
%
%
%
enable) %
%
%
%
%
NETWORK:
PM
= INP(PM)
nPCMD
= INP(PCMD#)
nPSTART_DLY = INP(PSTART_DLY#)
Al4
= INP(A14)
AIS
= INP(AIS)
Al6
= INP(AI6)
LAI7
= INP(LA17)
LAI8
= INP(LAI8)
LAl9
= INP(LAI9)
LA20= INP(LA20)
LA21
= INP(LA2I)
LA22
= INP(LA22)
LA23
= INP(LA23)
nMRDC
=INP(MRDC#)
nVGACS
= INP(VGACS#)
nFLASHDCS = INP(FLASHDCS#)
L_PW
= INP(L_PW)
EN_PRDY = INP(EN]RDY)
DL_OUT
= INP(DL_OUT)
SAOO
= INP(SAOO)
nSBHE_L = INP(SBHE_L#)
FLASH_CEO#,nFLASH_CEO = COIFCFLASH_CEO,VCC)
FLASHJ:::EI#,nFLASH_CEl = COIF(]LASH_CEI,VCC)
FLASH_CE2#,nFLASH_CE2 = COIF(]LASH_CE2, VCC)
FLASH_CE3#,nFLASH_CE3 = COIF(]LASH_CE3,VCC)
FLASH_CE4#,nFLASH_CE4 = COIFCFLASH_CE4,VCC)
FLASH_CES#,nFLASH_CE5 = COIFCFLASH_CE5, VCC)
RS _CE,RS_ CEf
= COIF(iRS_ CE, VCC)
=CONFCRD,VCC)
RD#
WT_L#
=CONFCWT_L,VCC)
= CONFCWT_U, VCC)
WT_U#
WT
= CONF(iWT, VCC)
292097-20
I
3-621
Ap·362
HOLD#
DL IN,DL INf
PRDY,PRDYf
PRDY#
SA16
= CONFCHOLD,VCC)
= COIF(iDL_IN,VCC)
= RORF(VCC,DL_OlIT,_DL_IN,GND, VCC)
= CONFCPRDY,EN_PRDy)
= CONF(VCC,Rd_RS)
EQUATIONS:
% Internal Declarations %
PCMD
= nPCMD';
PSTART_DLY = nPSTART_DL Y';
MRDC
= nMRDC';
VGACS
= n VGACS';
FLASHDCS = nFLASHDCS';
SBHE_L = nSBHE_L';
FLASH_CEO = nFLASH_CEO';
FLASH_CEI = nFLASH_CEI';
FLASH_CE2 = nFLASH_CE2';
FLASH_CE3 = nFLASH_CE3';
FLASH_CE4 = nFLASH_CE4';
FLASH_CES = nFLASH_CES';
_DL_IN = DL_INf';
]RDY
= PRDYf';
Hold
=PSTART_DLY
+PCMD
+MRDC;
Open
= !Hold;
Closed = IOpen;
Sel]DM = FLASHDCS; % Flash Disk Memory (mem cycles only) %
SeUOP = IFLASHDCS * NGACS * PM; % Execute-in-place Memory % -
% ROM Stub, OCSOOOh through OCBFFEh %
Sel_RS = IFLASHDCS * NGACS * 1LA23 * 1LA22 * 1LA21
*1LA20* LAI9* LAIS*ILAI7*/A16* AlS*/A14;
Sel_Modes = Sel]DM * LA23 * LA22 * LA21 * LA20 % Modes Reg %
* LA19 * LAlS * LA17 * A16;
Yes=VCC;
292097-21
3-622
I
Ap·362
No =GND;
% Zone pairs 0 and I are unconditionally assigned to the Flash
Disk. Zone pair 5 is unconditionally assigned to the Executable
Memory. Zone pairs 2, 3, and 4 are assigned with the three
equations below by selecting either Yes or No for the three
Flash Disk assignments. Assignments must be in order; 3 can
be assigned to the Flash Disk only if2 is, and 4 can be assigned
to the Flash Disk only if2 and 3 is. Zone pairs not assigned
to the Flash Disk are automatically assigned to Executable
Memory. %
% Demo Configuration
Z2eqFD=No;
Z3eqFD=No;
Z4eqFD=No;
%
% Customer Configuration %
Z2eqFD = Yes;
Z3eqFD = Yes;
Z4eqFD=No;
Z2eqXIP8 = IZ2eqFD;
Z3eqXIP8 = IZ2eqXIP8 ,. IZ3eqFD;
Z3eqXIPA = Z2eqXIP8 « IZ3eqFD;
Z4eqXIP8 = IZ2eqXIP8 ,. IZ3eqXIP8
Z4eqXIPA = Z3eqXIP8 « IZ4eqFD;
Z4eqXIPC = Z3eqXIPA ... IZ4eqFD;
>I<
IZ4eqFD;
ZSeqXIP8 = IZ2eqXIP8 >I< IZ3eqXIP8 ,. IZ4eqXIP8;
ZSeqXIPA = Z4eqXIP8;
ZSeqXIPC = Z4eqXIPA;
ZSeqXIPE = Z4eqXIPC;
% Outputs %
% Zone pairs 0 and 1 are unconditionally assigned to Flash Disk. %
]LASH_CEO' = Open ... Sel]DM'" 1LA23'" 1LA22'" 1LA21
+ Closed'" FLASH_CEO;
]LASH_CEI' = Open ... Sel]DM
+ Closed'" FLASH_CEI;
>I<
1LA23" 1LA22" LA21
% Zone pairs 2, 3, and 4 are conditionally assigned to either
Flash Disk or Execute-in-Place memory. XIP starts at 800000h
to avoid conflict with ROM Stub. %
292097-22
I
3-623
AP-362
]LASH_CE2' = Open * Sel]DM * 1LA23 * LA22 * 1LA21 * Z2eqFD
+ Open * Sel_XIP * LA23 * 1LA22 * 1LA21 * Z2eqXlP8
+ Closed * FLASH_CE2;
]LASH_CE3' = Open * Sel]DM * 1LA23 * LA22 * LA2l * Z3eqFD
+Open * Sel_XIP * LA23 * 1LA22 * 1LA21 * Z3eqXlP8
+ Open * Sel_XIP * LA23 * 1LA22 * LA2l * Z3eqXIPA
+ Closed * FLASH_CE3;
_FLASH_CE4' = Open * Sel]DM * LA23 * 1LA22 * 1LA21 * ZAeqFD
+ Open * Sel_XIP * LA23 * 1LA22 * 1LA21 * ZAeqXIP8
+ Open * SetXlP * LA23 * 1LA22 * LA2l * ZAeqXIPA
+ Open * Sel_XlP * LA23 * LA22 * 1LA21 * ZAeqXlPC
+ Closed * FLASH_CE4;
% Zone pair 5 is unconditionally assigned to Execute-in-Place.
Zone pair 5 is also enabled if Rom Stub is selected. %
]LASH_ CES' = Open * SetXIP * LA23 * 1LA22 * 1LA21 * ZSeqXIP8
+ Open * Sel_XIP * LA23 * 1LA22 * LA2l * ZSeqXIPA
+ Open * Sel_XIP * LA23 * LA22 * 1LA21 * ZSeqXIPC
+ Open * Sel_XIP * LA23 * LA22 * LA2l * ZSeqXIPE
+ Open * Sel_RS
+ Closed * FLASH_CES;
% RS _ CE forces Flash Addresses IS through 20 high. This, along
with the activation ofFLASH_CES#, cause ROM Stub accesses to
go to the upper 16 KBytes of Zone pair s. %
iRS_CE
= Open * SetRS
+ Open * SetModes
+ Closed * RS_CEf,
_RD'
= PCMD * FLASH_CEO * IL]W
+ PCMD * FLASH_CEI * IL]W
+ PCMD * FLASH_CE2 * IL]W
+ PCMD * FLASH_CE3 * IL]W
+ PCMD * FLASH_ CE4 * IL]W
+ PCMD * FLASH_ CES * IL]W
+ PCMD * Modes_CE * IL]W
+ MRDC * Rd_RS;
_WT_U'
= PCMD * FLASH_CEO * L_PW*SBHE_L
+ PCMD * FLASH_CEI * L_PW * SBHE_L
+ PCMD * FLASH_CE2 * L]W * SBHE_L
+ PCMD * FLASH_CE3 * L]W * SBHE_L
+ PCMD * FLASH_CE4 * L]W * SBHE_L
+ PCMD * FLASH CES * L PW * SBHE L
+ PCMD * FLASH=CES * LJ>W * RS_CEf% RS_CE->SBHE_L 3-S %
+ PCMD * Modes_CE * L]W * SBHE,-L;
292097-23
3-624
I
AP-362
_WT_L'
= PCMD· FLASH_CEO· L]W·/SAOO
+ PCMD· FLASH_CEI • L]W· /SAOO
+ PCMD· FLASH_CE2· L]W· /SAOO
+ PCMD· FLASH_CE3· L]W· /SAOO
+ PCMD· FLASH_CE4· L]W· /SAOO
+ PCMD· FLASH_CE5· L]W· /SAOO
+ PCMD· Modes_CE • L]W· /SAOO;
iWT
= PCMD· FLASH_CEO· L_PW
+ PCMD· FLASH_CEI • L]W
+ PCMD· FLASH_CE2· L]W
+ PCMD· FLASH_CE3· L]W
+ PCMD· FLASH_CE4· L]W
+ PCMD· FLASH_CE5· L]W
+ PCMD· Modes_CE • L]W;
_HOLD'
iDL_IN
=
Hold;
= PCMD· FLASH_CEO
+ PCMD· FLASH_CEI
+ PCMD· FLASH_CE2
+ PCMD· FLASH_CE3
+ PCMD· FLASH_CE4
+ PCMD· FLASH_CE5
+ PCMD • Modes_CE;
ENDS
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
292097-24
I
3-625
AP~362
SAC312 EPLD
OPTIONS: TURBO = OFF
PART: N5AC312 % PLCC %
%
This,EPLD contains logic for the following:
Flash Array VPP control
FDM and XIP Power Down control
Flash Disk Memory READY Interrupt control
MD_REV_A - 04/08/92 Initial release
MD_REV_B - 04/29192 MODES_CE now a function for FLASH_CE5 and
RS _CEo rather than separate. This is to
save pins on the other EPLD.
%
3-626
292097-36
I
AP-362
INPUTS:
WT#@2
% Write Strobe
%
RD#@4
% Read Strobe
%
SA01@9
% BufferedlLatched Address bit 01
%
SA02@10
% BufferedlLatched Address bit 02
%
RSTDRV@16 % ISA bus Reset Driver
%
ALL_RDY@27
% All Flash ICs assigned to Flash Disk are ROY %
SMOUT4@12
% +SLOCAL ON when this is high
%
FLASH_CES#@6
RS _CE@B
% ROM Stub Chip Select
%
OUTPUTS:
% Output pins %
EN_FLASH_VPP@22 % Pwr Cntrl Reg bit 00; Enable Flash Array VPP
PWR_UP@26 % Pwr Cntrl Reg fbit 03
%
PWRD#@3
% Power control signal to entire Flash Array %
lNTR@13
% Intr Cntrl Reg bit 00; Flash Disk ROY Intr %
SDOO@17
% Internal Data Bus
%
SD01@lB
SD02@20
SD03@21
UNUSED23@23
UNUSED24@24
~
% Buried Macrocells %
CLR_INTRf
EN_INTRf
% Clear Interrupt flip-flop
%
% Modes Reg bit 02; Enable Flash Disk ROY Intr
%
NETWORK:
nWT
= INP(WT#}
nRD
= INp(RO#}
SAO 1
= INP(SA01}
SA02
= INP(SA02}
RSTDRV = INP(RSTDRV}
ALL_ROY = INP(ALL_ROY}
SMOUT4 = INP(SMOUT4)
INTR_CLK = CLKB(ALL_ROY}
nFLASH_CES = INP(FLASH_CES#}
RS_CE = INP(RS_CE)
SDOO,SDOOf
SD01,SDOlf
SD02,SD02f
=
=
=
COIF(iSDOO,CHIP_RO}
COIF(iSD01,CHIP_RO)
COIF(iSD02,CHIP_RO}
292097-25
I
3-627
AP-362
SD03,SD03f
= COIF(iSD03,CHIP_RD)
EN]LASH_VPP,EN]LASH_VPPf= RORF(iEN]LASI-(VPP,nWT,RSTDRV,GND,VCC)
PWR_UP,PWR_UPf
= RORF(iPWR_UP,n WT,GND,RSTDRV, VCC)
PWRD#
= CONFLPWRD,VCC)
EN_INTRf
= NORF(iEN_INTR,nWT,RSTDRV,GND)
INTR,INTRf
= RORF(VCC,INTR_CLK,CLR_INTR£GND,VCC)
CLR_INTRf
= NOCF(iCLR_INTR)
= CONF(GND, VCC)
UNUSED23
= CONF(GND, VCC)
UNUSED24
EQUATIONS:
% Internal declarations %
RD
=nRD';
=nWT';
WT
FLASH_CES = nFLASH_CES';
Modes_CE
= RS_CE *IFLASH_CES;
Sel]wr_Reg = Modes_CE * ISA02 * ISAOl;
SeUntr_Reg = Modes_ CE * ISA02 * SAO 1;
=/ALL- RDY',
% Outputs and buried registers %
iSDOO
= Sel]wr_Reg * EN]LASH_VPPf
+ SeUntr_Reg * EN_INTRf;
iSDOI
= SeCPwr_Reg * GND
+ SeUntr_Reg * INTRf;
iSD02
= Sel]wr_Reg * GND
+ SeUntr_Reg * FDM_Busy;
iSD03
=
Sel_Pwr_Reg *IPWR_UPf
+ SeUntr_Reg * GND;
iEN]LASH_VPP = Sel]wr_Reg* SDOOf
+ ISel]wr_Reg * EN]LASH_VPPf,
292097-26
3-628
I
AP-362
]WRO
= PWR_UPf
+SMOlTf4;
iEN_INTR
= SeUntr_Reg· SDOOf
+ /SeUntr_Reg· EN_INTRf.
iCLR_INTR
=
RSTDRV
+1EN_INTRf
+ WT • Setelr_Intr;
ENDS
292097-35
I
3-629
AP-362
APPENDIX F
RFA SCHEMATICS
I
3-631
AP-362
2
SBHE l#
DL IN
I
OlY liNE
_ _ --'-(;;I
(.5LDCAL)
J
~~'N~~T~AP~'~O~"~D~L'~~-----------------'~~~"~__~'N~PR~D~Y____- ,
YAP20
I
~
TAPlO
lAP.4D
lAPSO
lAP60
lAP70
lAP80
lAP90
lAPIOO
3
Dl2
'2 DLl
,,=
I1-:-1E4
~
2
~'~D~l4t:1~'5'~~r.I~
I'PI
I-~' ~~:
~,
1 3-.r. ~~
-
'
2
~'O~D~L'~~__~~
N85C090
1/01
~
~
It:~~~~:!::~'~~r.I~I'P~2~______l2!..2!!!________4
-
.,."";~!.2.2.r8--::D:"L1:'::0,-..;to~;;;;1=IQI~....ot"';':'--I
35
1/051-
~=
___V ..•,
.:.'''I' INI
'N2
'N'
'N'
20
'N5
21
,N.
2.
'N'
25
'N8
,.
5
~
~
0
,
PSTARTII
-
U14
._2
0
::!
U14
PSTARLDlY
P4
2
PSTART#
pelolD#
PROY#
P.
PW
14
15
VGACS"
'8
fLASHDC5#
17
20
,
,
',2
2
2
,
,
,
,
,
,
3
,
,
,
-
'N'
IH10
42
IHll
43
IN12
~
RDY_ IL
~
-
, lA(17:23)
LA23
2,'
(PRDY)
I/O'7~
I/OI8~
~12t:==:::;-1
1/019
1/0201-'3
I
, PCMD#
~V~G;AC~S~.~__________.--I
:~'~L~A5~H~DC~S~'____________~
,-
N5AC312-25
~
~
, WI-L# 2 ClK/11 1/01
,E=,-",16~ Il/ICK 1/02
RD'
,.,:::::::....-..:;·'1lIHPI
1/03
,-
~I;;-
RDL3l
:.;.
,-
D~
ROY 4U
~
....
.5A(00:20)
~
'::.
,:~!!!;;~!:t~81
R5_CE
FLASH CES#
__ SNOUT4
L1NPS
6 llNP6
~
~
(PWR_UP)
t'O:~~:~:::::::~S~D"'='0::2:-t''1.
5001.
L1NP7 1/010
1/09 r
L1NPS
50(00:15)
~'~'=;_--(EN:~S~DD~Dt
.";~!.!!l
(EN INlR)
'/0"
1/012127
.... -
~I""-
2,3
~
1/04
1/05
,...;::=:.:...--t~-':.:'2i
~
RDY_5U
.4
1/064- (ClR_INTR)
1/07 !-"'13:...-__________l.::'N::.:TR:." ,
1/08...:,2:,.'______-'S~D::;D'~
,
~
~~~-
PWRD#
3
~ L1NP2
SAO 1
E~-----+---:-:''1lINP3
5A02
·';;'~;';;~_Fi's':CE---t-'~0~lINP4
2
-
EN FlASHVPP
22
RSTDRV
D~
RDY_3U
ROY _5L
tt::::h~;::tE!!: ,
8
1/015
1/0161-9
:.;.
ROY ZL
RDY_4L
1,2,3
WT_U#
PRDY#
LA22
~ID-:ROY 2U
+-____-"".:.;,1,2,3
RD"
1/012 ...,'0'-__
HOlD#
1/013
1/014 rt;~::::t:::::~~~~: 2
1/023~
LA21
~I_""-
~
1-':'37:-__.......
WT
2
1/011 r.:3·:----H-----::::-:::~
WT L"
I/o 10
~~.;:1/.;;02:.;':.J~
Ul1
RDY_OL
~
3
3
I/08~32t:::~~~jj~: ',2
1/091- 31
I/022~
~I,;;"-
ROY lU
,
14, - _ - ,
1/021..:::
02
ROY_OU
~
"
"
,
,
-'
,
27
7406
7.406
2
3
FLASH_CE3#
FLASH_CE4#
FLASH CES#
RS CE
~ t> ~~:~ :~~: ~~~:~:::t~~~~~~~~~~
CLOUT
-
U13
40
1/02 ~
fLASH_eEO#
2
1/03 P.'5:....--H~:-:::~~~
fLASH_CE1#
2
1/04t-f'.t:::~~~~~~
FLASH CE2# ,
~U':'12:--~
ALL ROY
I
lK 2
+5LOCAL
R.
292097-28
I
3-633
AP·362
0(00:15)
1
., ,.,.
50(00:15)
74FCT623
DIS
2
3
,
D"
013
012
011
DID
DOO
DO.
Al
A2
A3
.2
.3
AS
.5
•.
5
7
•
0
AS
A7
A.
GSA
p.
,
SOt5
17
SOU·
•• "
••
••
15
S012
13
12
.7
11
SOlO
5009
5008
SOU
5011
GA.
I
,U24
74FCT623
007
006
DOS
0
8
7
•
•
00'
D03
D02
DOl
DOD
5
3
2
Al
A2
5007
S006
S005
IS
16
17
.7
18
.8
GA.
5003
5002
. ., "
A3
AS
AS
A7
A8
G••
po
RD"
1
W,
1
.,
11
12
.2
13
.3
.S
"
SOO"'
SOot
SODA
I
5A20
LA(17:23)
1
LA20
LAl0
LAIS
'-48
"
7
17
4
18
LA17
A16
AIS
1
1
11
5A18
•
SBHEtI
0'
OS
D.
07
08
1
+5LOCAL
SA16
~;~
IS
•
03
04
16'
05
5
O'
10
07
2
08
1
SA15
2
lK R9
2
II< R13
2
IK R7
2
lK RIO 1
SA17
ocEN
Dl
D2
03
2
tIC Rtf 1
SA19
74FCT373
RS_CE
1
HOLD"
1
1
,U2o
t
2
II< R8
5A20
SA19
SA18
SA17
SA16
5A15
SBHLU
1
U2S
74FCT373
1
PW
;:¢
."
13
8
A13
A12
All
AID
ADO
.08
"
,
7
17
18
•
ocEN
01
02
03
0'
OS
O.
07
D.'
01
02
03
04
05
0&
07
08
12
0
IS
•
16
S
19
2
SA14
L PW
SA13
5412
SAil
1
SAID
5A09
SA08
U22
74FCT373
"
~
13
8
AD7
AO&
A05
"
,
7
17
AD'
AD'
A02
AOI
ADO
A(00:16)
1
3-634
,,,
18
3
ocEN
01
02
D.
12
01
0
02
IS
03
0'
OS
O.
07
08
0'
16
OS
S
O'
10
07
2
08
•
SA07
5AO&
SA05
SAO"
SA03
5A02
SAOI
SAOO
U21
i"."u~(-29
I
AP-362
SO(00·15)
1.
•
1
1
1
FLASH_ Vpp
RD#
WT U#
PWRD#
11
1
E~A
37
2
SAI8
SAl?
,
SAl6
S
SA15
SAl4
SA13
13
14
SAIO
15
SA09
17
18
SAOS
19
SAOS
20
21
SA04
SA02
22
23
SAOI
24
5M3
36
BSY
A15
AU
007
A13
Da6
A12
oas
A11
DO'
Da3
AlO
16
SAC a
SA07
A19
ROY
au
1
A16
7
eE
OE
WE
29
PWO
A17
•
•
SAI2
,
3
A18
3
SAIl
~Vpp
FLASH CE1#
WE
>-4<:
SA19
1
OE
3.
SA20
30F~A
Vpp
eE
9
FLASH CEO#
A'
A.
Da2
A7
DaO
DOl
SA20
40
SAI9
SAI8
"
SAI7
37
SAI6
36
35
35
5015
SA15
34
sou
SAl.
"
5013
SA13
32
SAI2
SAIl
27
SAID
2.
5009
A.
AS
A,
A3
A2
Al
AO
A17
SAQ9
2S
SACS
2.
SA07
23
SAOS
22
SAOS
21
SAO'"'
20
SAQ3
19
5M2
18
SAO!
17
A15
30
32
~
3
SA20
SA19
SAl8
.D
3.
SAl7
37
SA16
36
SAIS
35
SAl.
34
SAI3
SAIl
"
SAil
27
SAID
26
25
SA09
SAO a
28
SAD'
24
23
SA06
22
SAOS
21
SA04
20
5A02
,.
SA01
17
5A03
F~A
•
L-¥n<
"
,.
Vpp
eE
SA20
A19
SA19
Al.
ROY OL
S
Al.
A13
DO.
A12
DOS
A11
004
Al0
Da3
A'
A8
A7
002
DOl
DOD
A.
AS
I
A4
A3
A2
Al
AO
crz-
DOS
A11
DO'
Da3
A'
A.
D02
A7
Dao
DOl
9
S015
5014
5013
S012
13
5011
14
SOlO
,.
5008
15
S009
AS
A3
A2
Al
AO
37
D07
A12
•
•
7
•
•,
7
1
SAl8
SA17
SA16
S007
SA15
5006
SA14
~
2
3
•
•
S
7
S005
SAI3
8
S004
SAI2
13
13
5003
SAIl
14
14
5002
SAID
15
,.
SOOI
SA09
5000
SAO a
15
rv;-
~eE
PWD
A14
00.
AS
3.
A15
007
A13
E28FOO8SA
WE
B'Y
ROY lU
A.
11
0,
AI',
S
~
WLL#
I
AU
AlO
u.-
1
BSY
A16
2.
5012
5011
SOlO
SOOB
Al.
"
"
27
2S
A19
3.
2.
2.
PWO
SA07
,.
,.
17
SAOS
19
SACS
20
21
SAO"
5M3
22
SA02
23
SA01
24
OE
WE
PWD
A19
Al.
A17
BSY
ROY
3.
1L
A16
A15
AU
D07
A13
DO.
A12
DOS
A11
DO.
AlO
Da3
A'
A.
002
A7
DOO
DOl
35
S007
34
5006
33
5005
32
5004
28
5003
27
5002
2.
SODI
2S
5000
A.
AS
A4
A3
A2
Al
AO
'u."'"SA(OO:20)
"
292097-30
I
3-635
AP-362
50(00'15)
2
FLASH_ Vpp
RD"
Wl UN
PWRO#
IIE~A
FLASH CE211
CE
37
SA!9
2
3
SAI7
4
SA 16
S
SA 15
SA 14
8
13
SAil
14
SAID
15
SA09
I.
SAOS
17
SA07
18
SA06
19
SAOS
20
SA04
21
SA03
22
SA02
23
SAO!
24
BSY
36
ROY 2U
I
AI.
AI'
007
A13
DO.
A12
OOS
004
AIO
003
A9
002
A8
001
A7
SA20
.0
SA!9
39
SAI8
38
SAP
"
SAt6
A15
All
OE
WE
29
'WO
A19
AI7
•
SA13
CE
4
3
AI8
7
SAI2
FLASH CE3#
WE
~
SA 18
I
OE
3B
SA20
30F~A
~Vpp
Vpp
9
000
5015
SA1S
3S
34
SOU
SAl(
34
33
S013
SAI3
33
32
28
5012
SAI2
28
5011
SAI1
27
27
SOlO
SAID
2.
5009
SA09
2S
2S
5008
SAOS
24
SA07
23
SAOS
22
AS
A4
A3
A2
AI
AO
AI8
AI7
A15
2.
SACS
21
SA04-
20
5A03
I.
5A02
18
SAO!
17
BSY
ROY 3U
S
I
AI.
3.
3S
A.
'WD
A19
A14
007
A13
DO.
A12
DOS
All
AIO
DO'
003
A9
002
A8
DOl
A7
000
•
7
8
5015
5014
5013
9
5012
13
5011
14
SOlO
15
5009
I.
5008
A.
AS
A4
A3
A2
AI
AD
~
ug--
WLL-
I
30
F~A
32
•
3
SA20
40
SA!9
39
SAIS
38
SA 17
37
SAI6
3.
SAIS
35
SA14
34
SAI2
"
SAll
27
SAIO
2.
SA09
2S
SAO a
24
SA 1.3
SA(O 1 :20)
L7o<:
28
SA07
23
SA06
22
SAOS
21
SAO'"
20
SA03
19
SM2
18
SA01
17
E2BFOOBSA
"~
~ C~p
Vpp
CE
37
38
OE
WE
'WD
A19
SA20
AI8
AI7
BSY
S
ROY 2L
AI.
A15
A14
A13
A12
All
007
DO'
DOS
DO'
AIO
003
A.
002
A8
DOl
A7
000
A.
AS
A.
A3
A2
AI
AD
us-
•
7
I
~
SA!9
2
SAIS
3
SAP
SAI6
S007
SA1S
S006
SAl'"
•
•
S
7
8
5005
SA13
8
9
sao",
SAI2
13
13
5003
SAil
14
14
5002
SAID
15
15
SOOI
SA09
I.
I.
5000
SAO
a
17
SA07
18
SAOS
19
SAOS
20
SA04
21
SA03
22
SA02
23
SAO!
24
DE
WE
'WD
AI'
AI8
AI7
BSY
ROY 3L
3.
A16
AIS
A14
007
A13
A12
DO'
DOS
All
004
AID
003
A9
D02
AS
DOl
A7
000
35
S007
34
S006
33
5005
32
5004
28
5003
27
5002
2.
SOOI
2S
SODa
A.
AS
A4
A3
A2
AI
AO
b';'o292097-31
3-636
I
AP-362
30F~A
E28FOO8SA
,
---l!r---'9
;~p
FLASH CE4"
37
,
5A19
2
3
SA 17
4
SAI6
SA15
SAI4
8
13
"
'7
SA07
SACS
'8
19
SAOS
20
SA04
21
5A03
22
SAOZ
23
SAOt
SA20
2'
40
ROY 4U
SA 19
39
SA 18
38
,
SA 17
37
SA 16
A'S
AU
'5
16
SA08
BSY
36
A16
7
SA13
SA09
A,8
5
SAI2
SAID
A19
A'7
007
A13
006
A'2
All
005
004
A'O
003
A'
A8
002
A7
00'
000
5015
SAIS
35
34
5014
SA 14
34
33
50\3
SA13
33
32
S012
SAI2
28
28
5011
SAIl
27
27
SOlO
SAID
26
2'
25
5009
SA09
25
S008
SACS
24
SA07
23
SAG6
22
SACS
21
SA04
20
SA03
19
SA02
'8
SA01
'7
A.
AS
A3
A2
A'
AD
WE
'WO
A19
A '8
A,7
A'S
I
~
Vpp
~CE
SA20
--¥o-c
40
SA 19
39
SA 18
38
SAI7
37
SA 16
36
SA 15
35
SA \4
34
SA13
33
SA 12
28
SAIl
27
SAID
26
SA09
25
SAoa
24
SA07
23
SAG6
SAOS
22
21
SA04
20
SA03
19
SA02
'8
SAOt
'7
'WO
A,8
ROY 4l
5
A16
007
A13
DO'
A12
DOS
All
004
A'O
003
A'
D02
AS
DO'
A7
DOD
A6
AS
A4
A3
A2
A'
AD
~
DOS
All
D04
AlO
003
A'
A8
002
A7
DOD
DO'
5015
SOU
8
5013
,.
5011
SOlO
,.
5008
,
'3
'5
5012
5009
A3
A2
A'
AD
-;;.aCE
SA20
A19
A14
A '2
•
7
A4
37
A15
006
AS
38
BSY
007
A13
E28FOO8SA
WE
A17
AU
11~
DE
3
ROY 5U
~
F28FOO8SA
3D
5
A6
b";"s'-
I
BSY
A16
36
35
A4
24
DE
3
,WO
•
SAIl
CE
4
WE
'2
SAIS
~Vpp
FLASH C[5#
DE
3B
SA20
,
,
~
SA 19
2
SA 18
3
SA 17
4
SAl6
5
OE
WE
'wo
A19
A'8
A '7
BSY
A15
•
,
SOO7
SA15
7
S006
SAU
8
S005
SA 13
8
S004
SA 12
13
13
5003
SAIl
14
,.
A,O
14
S002
SAID
15
003
15
saOl
SAC9
16
D02
5000
SAC a
A'
A8
'7
A7
000
'8
19
A6
SAOS
SAOS
20
SA04
21
SA03
22
SA02
23
SAOI
24
SA07
•
7
36
ROY SL
A16
A14
007
A13
006
A12
005
All
004
DO'
35
S007
34
S006
33
S005
S004
32
28
5003
27
S002
26
SOOI
25
sooo
AS
A4
A3
A2
A'
AD
~
292097-32
I
3-637
AP-362
292097-33
3-638
I
AP·362
[NJLA5HVpp
292097-34
I
3-639
intel.
AP-364
APPLICATION
NOTE
28F008SA
Automation and Algorithms
BRIAN DIPERT
Men MARKETING APPLICATIONS
September 1993
3-640
I
Order Number: 292099-003
28F008SA Automation and Algorithms
CONTENTS
PAGE
1.0 INTRODUCTION ................... 3-642
2.0 AUTOMATION AND
ALGORITHMS . ...................... 3-642
2.1 28F008SA Automation and the
Write State Machine .............. 3-642
Command User Interface
Status Register
2.2 Byte Write Algorithm ............. 3-645
CONTENTS
PAGE
2.3 Block Erase Algorithm ........... 3-647
2.4 Erase Suspend/Resume
Algorithm ......................... 3-647
2.5 Write State Machine Current/Next
State Overview ................... 3-650
Read Array
Byte Write Setup
Byte Write
Erase Setup
Erase
Erase Command Error
Erase Suspend to Status/Array
Read Status
Read Identifier
2.6 Block Erase As a Background
Task .............................. 3-652
ADDITIONAL INFORMATION ......... 3-653
I
3-641
AP-364
1.0
INTRODUCTION
The Intel 28F008SA FlashFile™ Memory is today's
optimum solution for high density solid state storage.
Flash memory, exemplified by the 28FOO8SA, is an enabling technology for today's powerful system designs
that are higher performance, more compact, lighter,
more rugged and have longer battery life.
Features of the 28FOO8SA include:
• High-Density Symmetrically Blocked Architecture:
- Sixteen 64-Kbyte Blocks
•
•
•
-
Extended Cycling Capability
100,000 Block Erase Cycles
1.6 Million Block Erase Cycles per Chip
Automated Byte Write and Block Erase
Command User Interface
Status Register
System Performance Enhancements
R Y/BY # Status Output
Erase Suspend Capability
•
•
•
•
-
Deep Powerdown Mode
0.20 J.IoA ICC Typical
Very High Performance Read
85 ns Maximum Access Time
SRAM-Compatible Write Interface
Hardware Data Protection Features
Erase/Write Lockout during Power Transitions
•
•
-
Industry Standard Packaging
40 Lead TSOP, 44 Lead PSOP .
ETOX III Nonvolatile Flash Memory Technology
12V Byte Write/Block Erase
The 28F008SA's automation is a significant enhancement to the manual algorithms of first-generation flash
memory devices. System software and hardware designs that fully understand and. exploit this automation
will greatly benefit from its versatility and capabilities.
The concepts prese~ted in this document are applicable
to such designs.
This application note discusses in-depth operation of
the 28FOO8SA FlashFile memory Write State Machine
and internal algorithms, emphasizing how they interface to system hardware and software. The 28F008SA
datasheet (order number 290429) is a valuable reference
3-642
document, providing in-depth device technical specifications, package pinouts and timing waveforms. Companion application note AP-359, "28FOO8SA Hardware
Interfacing" (order number 292094) describes supply
voltage derivation and filtering, control input/output
implementation, high density layout and high speed design techniques, as well as providing example system
interfaces to common microprocessor buses. AP-360,
"28F008SA Software Drivers" (order number 292095)
provides example ASM-86 and "C" routines for controlling the 28FOO8SA. AP-359 and AP-360 should be
reviewed in conjunction with this application note and
the 28FOO8SA datasheet for a complete understanding
of this device.
2.0
AUTOMATION AND
ALGORITHMS
Figure I shows a block diagram of the 28F008SA and
its internal contents. Although a main subject of this
application note is software interface to read and alter
memory contents, it is useful to begin with an overview
of the 28FOO8SA hardware subsections that are directly
manipulated by the system. In particular, this application note will first discuss the Write State Machine
(WSM) and Command User Interface/Status Register,
and then explain the software routines that control this
hardware.
2.1 28F008SA Automation and the
Write State Machine
When the system microprocessor reads flash memory
data from the 28FOO8SA, it uses control lines CE# and
OE#, along with address inputs, to select a byte of data
directly from the memory cell array. However, the system does not directly access the array when it writes to
the 28FOO8SA; instead it writes to the Command User
Interface, whose register contents are interpreted and
translated into WSM actions. The WSM can be
thought of as a dedicated "processor", along with companion clock-generation circuitry, integrated into the
flash memory. After receiving proper commands or
command sequences, it controls byte write and block
erase algorithms internally. The status of the WSM is
not invisible to the system; the WSM interfaces to the
outside world through a full-featured Status Register
and dedicated RY /BY # (Ready/Busy #) output. Automation has significant benefits, some of which are
more obvious than others.
I
AP-364
DOo - DO,
[=-~J"-;====::;-"" RY /ay#
Vpp
292099-1
Figure 1. 28F008SA Block Diagram
The WSM architecture dramatically simplifies the program and erase algorithms of first-generation flash
memory devices. Hardware/software timers, erase preprogramming, byte-by-byte verification and margining,
pulse repetition and limited microprocessor multitasking capability throughout data update have been eliminated,. replaced by a simple two-command write for
both block erase and byte write. The 28F008SA WSM
halts itself when its internal algorithms are complete,
and can alert the system to this completion by a hardware interrupt (using RY/BY#) or via software polling of the 28FOO8SA Status Register.
Internal automation frees the system to execute higherpriority tasks while a 28F008SA is being block erased
or byte written, and inherent in this capability is the
most powerful advantage of the WSM. Operating systems prioritize file operations in the following order:
• Read
• Write
• Erase
When an array of 28FOO8SA components is used as
solid-state storage (in a memory card, integrated in a
flash-based "hard drive' lorm factor or resident on the
system motherboard), system software can initiate
slower block erase (0.3 sec minimum) of one or several
I
28F008SAs and, by not being "tied" to the erase algorithm, execute higher priority reads (85 ns minimum)
or writes (6 fLs minimum) of other 28F008SAs as operating system requests dictate. Additionally, erase suspend/resume capability allows data retrieval from a
28F008SA currently being block erased, again enabling
"read" as the highest priority task. Block erase as a
background task is discussed in Section 2.6 of this document.
Command User Interface
Table 2 shows the various command sequences that are
accepted and interpreted by the 28FOO8SA Command
User Interface and WSM. Writes to the CUI enable
reading of device data and intelligent identifiers, reading and clearing of the Status Register, and commencement of internal byte write, block erase and erase suspend/resume algorithms. The CUI itself does not occupy a specifically addressable memory location, and contains a latch used to store the command and address/
data information needed to execute the command.
Erase Setup and Erase Confirm commands require both
appropriate command data and an address within the
block to be erased. The Byte Write Setup command
requires appropriate command data and the address of
the location to be written, while the Byte Write command consists of the data to be written and its address
location.
3-643
AP-364
Table 1. Status Register Definitions
WSMS
ESS
ES
BWS
VPPS
R
7
6
5
4
3
2
R
R
o
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
RY IBY # or the Write State Machine Status bit must
first be checked to determine byte write or block erase
completion, before the Byte Write or Erase Status bits
are checked for success.
If the Byte Write AND Erase Status bits are set to "1 "s
during a block erase attempt, an improper command
sequence was entered. Attempt the operation again.
If Vpp low status is detected, the Status Register must
be cleared before another byte write or block erase op·
eration is attempted.
The Vpp Status bit, unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM
interrogates the Vpp level only after the byte write or
block erase command sequences have been entered
and informs the system if Vpp has not been switched
on. The Vpp StatlJ!l bit is not guaranteed to report accurate feedback between VPPL and VPPH.
'
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
o = Erase in Progress/Completed
SR.S = ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Write
SR.4 = BYTE WRITE STATUS
I = Error in Byte Write
o = Successful Byte Write
SR.3 = Vpp STATUS
1 = Vpp Low Detect; Operation Abort
0= VppOK
.
SR.2-SR.O = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be masked out when polling the Status Register.
Table 2. Command Definitions
Command
Bus
First Bus Cycle
Second Bus Cycle
Cycles Notes
Req'd
Operation Address Data Operation Address Data
FFH
1
Intelligent Identifier
3
1,2,3
Write
X
90H
Read
IA
110
Read Status Register
2
2
Write
X
70H
Read
X
SRD
Write
X
50H
1
Write
BA
20H
Write
BA
DOH
Clear Status Register
1
Erase Setup/Erase Confirm
2
Write
X
Read Array/Reset
Erase Suspend/Erase Resume
2
Write
X
BOH
Write
X
DOH
Byte Write Setup/Write
2
1,2,4
Write
WA
40H
Write
WA
WD
Alternate Byte Write Setup/Write
2
1.2.4
Write
WA
10H
Write
WA
WD
NOTES:
1. IA = Identifier Address: OOH for manufacturer code. 01 H for device code.
BA = Address within the block being erased.
WA = Address of memory location to be written.
2. SRD = Data read from Status Register. See Table 4 for a description of the Status Register bits.
WD = Data to be written at location WA. Data is latched on the riSing edge of WE.
110 = Data read from intelligent identifiers.
,
3. Following the intelligent identifier command. two. read operations access manufacturer and device codes.
4. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command.
5. Commands other than those shown above are reserved by Intel for future device implementations and should not be
used.
3-644
I
AP-364
Status Register
2.2
Table 1 shows the 28F008SA Status Register and defines its various bits. Like the Command User Interface, it does not occupy a specific memory location
within the device. It functions as an output of the
WSM, informing the system when internal byte write
or block erase algorithms have completed, if these algorithms completed successfully, and whether the
28F008SA is currently in Erase Suspend mode. Bit 7
(Write State Machine Status) is replicated in the device
RY/BY# hardware output. The default state of the
upper 5 bits of the Status Register after powerup and
return from deep powerdown mode is 10000 (binary).
Figure 2 provides a graphical representation of the
28F008SA byte write algorithm. As can be seen, this
consists solely of a two-command write sequence, followed by a periodic poll of the device RY/BY# output
or Status Register. The 28F008SA automatically outputs Status Register data when read after the two-command byte write sequence (see Section 2.5). Byte write
typically completes in 9 J-Ls.
A separate Clear Status Register command allows reinitialization of Status Register data after analysis. The
Status Register is not cleared until this command is
written to the 28F008SA.
Bits 5 and 4 of the Status Register, if set by the WSM
via a byte write or block erase attempt, do not block
subsequent attempts (they need not be cleared before
another byte write/block erase command sequence is
written to the device). However, if the WSM detects a
"low Vpp" condition and subsequently sets bit 3 of the
Status Register, the Status Register MUST be cleared
before another algorithm command sequence will be
recognized by the 28F008SA.
It is important to note that the Vpp Status bit of the
Status Register DOES NOT act like an always-functional AID converter; its normal state, even with Vpp
below 6.5V, is "0". The WSM only analyzes the Vpp
level after a byte write or block erase command sequence has been written to the device, and if it detects
that Vpp is "low" it will cancel the impending byte
write or block erase operation and set the Vpp Status
bit to "I". Therefore, the Vpp Status bit cannot be used
by the system as an indication of proper Vpp level, before a byte write or block erase sequence is initiated.
The system should instead insert an appropriate software delay between turning on Vpp and writing an initial command sequence, or use external hardware as a
Vpp feedback mechanism.
I
Byte Write Algorithm
The byte write algorithm requires high voltage VpPH
(12V ± 5%) on the device Vpp input until internal algorithm completion is reported by the WSM. If byte
write is attempted while Vpp = VPPL (~6.5V), the
Vpp Status bit of the Status Register will be set to "I",
and array data will not be altered. Byte write attempts
while VpPL < Vpp < VPPH produce spurious results
and should not be attempted.
The Status Register will only report errors for "I "s that
do not write to "O"s during a byte write attempt. Erasure (see Section 2.3) is the method used to change data
"O"s to "I"s using flash technology. If the system software attempts to write "I "s to a byte at bit locations
already at value "0", no Status Register error will be
reported for those specific bits.
It is often desired to write multiple bytes of data at one
time to memory. Since the Status. Register is only
cleared after the Clear Status Register command is
written to the 28F008SA, a string of bytes can be sequentially written to the device before the "full status
check procedure" examines Status Register bits other
than SR.7.
Byte write abort occurs when the 28F008SA RP# (Reset/Powerdown) input drops to VIL (deep powerdown
mode is entered), or Vpp drops to VPPL. Although the
WSM is halted in either case, byte data is partially written at the location where aborted. A repeat byte write
sequence after system integrity is restored will complete
the desired operation, or data can be initialized to a
known value of "FF" thru block erasure.
3-645
AP-364
Bus
Operation
Command
Write
Byte Write
Setup
Data = 40H (10H)
Address = Byte to be written
Write
Byte Write
Data to be written
Address = Byte to be written
Standbyl
Read
292099-2
Comments
Check RY IBY #
VOH = Ready,VOL = Busy
or
Read Status Register
CheckSR.7
1 = Ready, 0 = Busy
ToggleOE# orCE# to update
Status Register
Repeat for subsequent bytes
Full status check can be done after each byte or after a
sequence of bytes
Write FFH after the last byte write operation to reset the
'
device to Read Array Mode
FULL STATUS CHECK PROCEDURE
Bus
Operation
Vpp Range
Command
CPU may already have read
Status Register data in WSM
Ready polling above
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
CheckSR.4
1 = Byte Write Error
Error
By to Write
Error
Comments
Optional
Read
SR.3 MUST be cleared, if set during a byte write attempt,
before further attempts are allowed by the Write State
Machine
292099-3
SR.4 is only cleared by the Clear Status Register Command,
in cases where multiple bytes are written before full status is
checked
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 2. Automated Byte Write Flowchart
3-646
I
AP-364
2.3 Block Erase Algorithm
Figure 3 provides· a graphical representation of the
28F008SA block erase algorithm, similar in its twocommand write sequence to the byte write algorithm
discussed earlier. Both the Erase Setup and Erase Confirm commands must be accompanied by an address
within the desired block to be erased to FFH. The
28F008SA automatically outputs Status Register data
when read after the two-command block erase sequence
(see Section 2.5). Block erase typically completes in
1.6 sec.
Again similar to byte write, the block erase algorithm
requires high voltage VPPH (12V ±5%) on the device
Vpp input until internal algorithm completion is reported by the WSM. If block erase is attempted while
Vpp = VPPL (:S; 6.5V), the Vpp Status bit of the Status
Register will be set to "1", and array data will not be
altered. Block erase attempts while VpPL < Vpp <
VPPH produce spurious results and should not be attempted.
If write of the Erase Setup command is followed by
write of any other command but Erase Confirm, the
WSM will decode this as an illegal sequence. It will not
attempt to erase the specified block, and will report
error back to the system by setting both the Erase
Status and Byte Write Status bits of the Status Register
to "1 ". Since the Status Register is only cleared after
the Clear Status Register command is written to the
. 28F008SA, a string of blocks within a 28F008SA can
be sequentially erased before the "full status check procedure" examines Status Register bits other than SR.7.
I
Block erase abort occurs when the 28F008SA RP#
(ResetiPowerdown) input drops to VIL (deep powerdown mode is entered) or Vpp drops to VPPL. A repeat
block erase sequence after system integrity is restored
will complete the desired operation.
2.4 Erase Suspend/Resume
Algorithm
Figure 4 gives a software flowchart for implementing
erase suspend/resume using the 28F008SA. As mentioned in Section 2.1, operating systems prioritize data
reads highest, and consequently the 28F008SA has
been designed with read as its highest performance
function. Erase suspend allows system software to postpone WSM-controlled block erase if the system requests read of data from a different block of the same
device. Although any block of the 28F008SA can be
read, the block being erased when suspended will contain unknown data.
The 28F008SA is suspended by writing the Erase Suspend command (BOH) to it while the WSM is executing
an erase algorithm. The WSM will halt block erase, set
bits 7 and 6 of the Status Register to "1" and transition
RY/BY# to VOH, after which time system software
can read data from either the array or Status Register.
Issuing the Erase Resume command (DOH) signals the
WSM to resume block erase.
Vpp must remain at VPPH throughout the erase suspend interval, even when reading from the flash memory array. The 28F008SA will detect a Vpp transition to
VPPL while suspended, and report this error via Status
Register bit 3 (set to "1") after the Erase Resume command is written to it.
3-647
AP-364
Bus
Command
Operation
Comments
Write
Erase
Setup
Data = 20H
Address = Within block to be
erased
Write
Erase
Confirm
Data = DOH
Address = Within block to be
erased
Check RYIBY #
VOH = Ready, VOL = Busy
or
Standbyl
Read
Read Status Register
CheckSA.7
1 = Ready, 0 = Busy
ToggleOE# orCE# to
update Status Register
Repeat for subsequent blocks
292099-4
Full status check can be done after each block or after a
sequence of blocks
Write FFH after the last block erase operation to reset
the device to Read Array Mode
'
Bus
Command
Operation
Vpp Rang.
Optional
Read
CPU may already have read
Status Register data in WSM
Ready polling above
Standby
CheckSA.3
1 = Vpp Low Detect
Standby
Check SR.4,5
Both 1 = Command Sequence
Error
Standby
Check SA.5
1 = Block Erase Error
Error
Command Sequ.nc.
Error
Block Eras.
Error
Comments
SA.3 MUST be cleared, if set during a block erase attempt,
before further attempts are allowed by the Write State
Machine
292099-5
SR.5 is only cleared by the Clear Status Register Command,
in cases where multiple blocks are erased before full status
is checked
If error is detected, clear the Status Register before
attempting retry or other error recovery
Figure 3. Automated Block Erase Flowchart
3-648
I
intel®
AP-364
Bus
Operation
Comments
Command
Write
Erase
Suspend
Data
=
BaH
Write
Read
Status Register
Data
=
?OH
Check RY/BY#
VOH = Ready, VOL = Busy
or Read Status Register
Standby
Read
Check SR.?
1 = Ready, a = Busy
ToggleOE# orCE# to
Update Status Register
Standby
Write
CheckSR.6
1 = Suspended
Read Array
=
FFH
Read array data from block
other than that being erased.
Read
Write
Data
Erase Resume
Data
=
DOH
292099-6
Figure 4. Erase Suspend/Resume Flowchart
I
3-649
AP-364
Since the WSM is driven by its own oscillator, internal
to the 28F008SA, it operates asynchronously to the system CPU and its clock. Therefore, the possibility exists
that the WSM could complete erase, returning to
"ready", between when the system reads "busy" from
the Status Register and writes the Erase Suspend command. Analyzing both the WSM Status and Erase Suspend Status bits of the Status Register, as shown in the
flowchart, will alert the system to such an occurrence.
2.5 Write State Machine Current/Next
State Overview
Byte write and block erase automation equate to tremendous power and capability in system implementations of the 28F008SA, if fully exploited. An in-depth
understanding of the WSM, its states and its responses
to inputs, will assist the software engineer in developing
optimized .driver routines for flash memory-based file
storage and other high-performance applications. Table
3 lists all possible WSM "current states", command
inputs and resultant "next states".
Non-shaded boxes highlight those state transitions
which will most commonly occur when reading from
and modifying 28F008SA contents, and these transitions should be understood in most depth. Shaded
boxes, on the other hand, represent lesser-used or nonsensical transitions, such as improper erase command
sequences.
Before reading the 28F008SA, if the current WSM
mode is not known (if, for example, an interrupt service
routine has potentially interacted with the device), first
write the desired output command (i.e. Read Status
Register, Read Array or Intelligent Identifier). This ensures that the 28F008SA will be in a known state when
read and will output expected data.
3-650
Read Array
The 28F008SA automatically defaults to Read Array
mode when powered up, or when it returns from Deep
Powerdown mode. As the name implies, the 28FOO8SA
outputs array data when read in Read Array mode.
Read Array is also the default mode after the Clear
Status Register command is written in most other
modes.
Byte Write Setup
The 28F008SA transitions to Byte Write Setup mode
after it receives the Byte Write Setup command. If the
28FOO8SA is read in Byte Write Setup mode, it outputs
Status Register data.
Byte Write
After the 28FOO8SA is placed in Byte Write Setup
mode, the next address/data combination written to it
transitions the WSM to Byte Write mode, where the
"Byte Write Command" is latched as desired data to
write to the array at the specified address location. Immediately, the WSM examines Vpp, and if it detects an
invalid level, it halts with Vpp error indication in the
Status Register (bit 3 = "I "). Bit 7 of the Status Register is "0", and the RY/BY# output is driven to VOL,
while the WSM is executing the internal byte write algorithm in Byte Write mode. The 28FOO8SA automatically outputs Status Register data when in Byte Write
mode.
Erase Setup
The 28F008SA transitions to Erase Setup mode after it
receives the Erase Setup command. If the 28FOO8SA is
read in Erase Setup mode, it outputs Status Register
data.
I
intel®
AP-364
Table 3. Write State Machine Current/Next States
Command Input (and Next State)
Data
Current RY/BY#
When
State
Status
Read
Read
Array
(FFH)
Byte
Erase
Erase
Erase
Erase
Read
Write
Setup Confirm Suspend Resume Status
Setup
(DOH)
(BOH)
(70H)
(20H)
(DOH)
(10/40H)
Byte
Write
Setup
Erase
Setup
Read
Array
VOH
Byte Write
Setup
VOH
Byte Write
(Not
Complete)
VOL
Byte Write
(Complete)
VOH
Erase
Setup
VOH
Erase
Command
Error
VOH
Erase
(Not
Complete)
VOL
Erase
(Complete)
VOH
Erase
Suspend
to Status
VOH
Erase
Erase
Suspend
to Array
VOH
Erase
Read
Status
VOH
Status
Read
Identifier
VOH
10
Read
Array
Read
Array
Read
Array
Read
Status
Clear
Status
(50 H)
ReadlD
(90H)
Read
Array
Read 10
Read 10
Status
Array
Write
Setup
Read
Array
Byte
Write
Setup
NOTE:
1. State transitions labeled "Reserved" are set aside by Intel Corporation for potential future device implementations. Command sequences to access these states should not be attempted.
I
3-651
AP-364
Erase
Read Status
After the 28FOO8SA is placed in Erase Setup mode,
write of the Erase Confirm command transitions the
WSM to Erase mode, where the specified address is
decoded into one of 16 blocks to be erased. Immediately, the WSM examines Vpp, and if it detects an invalid
level, it halts with Vpp error indication in the Status
Register (bit 3 = "I"). Bit 7 of the Status Register is
"0", and the RY/BY# output is driven to VOL, while
the WSM is executing the internal block erase algorithm in Erase mode. The 28FOO8SA automatically
outputs Status Register data when in Erase mode.
As the name implies, the 28FOO8SA automatically outputs Status Register contents when read in Read Status
mode. If system software writes the Clear Status command at this point, the WSM resets the Status Register
to its default value. and transitions to Read Array
mode.
Erase Command Error
This is the other possible transition mode after Erase
Setup, and occurs when an invalid command (anything
but Erase Confirm/Resume) is written to the
28FOO8SA as the second in the two-command block
erase sequence. In this mode, the WSM does not attempt a block erase, and it returns an error indication
to the system by setting both bits 4 and 5 of the Status
Register to "I". The 28FOO8SA automatically outputs
Status Register data when in Erase Command Error
mode.
Erase Suspend to StatuslArray
While the WSM is busy executing an internal block
erase algorithm, it can be placed in erase suspend by
writing the Erase Suspend command. After receiving
and decoding this command, the WSM suspends block
erase, drives the RY/BY# output to VOH, sets bits 6
and 7 of the Status Register to "I" and transitions to
"Erase Suspend to Status" mode. The 28FOO8SA automatically outputs Status Register data when in "Erase
Suspend to Status" mode.
The only valid command other than Read Status and
Erase Resume at this time is Read Array, which tran~
sitions the WSM to "Erase Suspend to Array" mode.
As the name implies, the 28FOO8SA outpu~s array data,
not Status Register contents, in this mode. While in
both Erase Suspend modes, Vpp must remain at VPPH
for erase to complete successfully when resumed.
Writing the Erase Resume (same as Erase Confirm)
command to the 28FOO8SA transitions the WSM out of
Erase Suspend and back to Erase. In conjunction with
this, the WSM returns RY/BY # to VOL and resets bits
6 and 7 of the WSM to "0".
3-652
Read Identifier
The 28FOO8SA outputs its manufacturer identifier of
89H when read from address 'OOOOOH when in Read
Identifier mode. Similarly, a read from address 0000IH
returns the device identifier A2H. Using this information, the system can automatically match the device
with its proper block erase and byte write algorithms.
Reads from addresses other than OOOOOH and OOOOlH
are not supported by Intel, and consistent results of
such reads are not documented, guaranteed or recommended.
2.6 Block Erase as a Background
Task
As mentioned earlier, the internal WSM block erase
algorithm typically takes 1.6 seconds to complete.
Proper implementation of block erase from a hardware
and software standpoint, however, can mask this delay,
by taking advantage of the 28FOO8SA's internal automation and full-featured system interface. Execution of
block erase as a background task, with higher priority
read and write functions in the foregrOlmd, is the key.
The recommended scenario includes an "intelligent"
operating system routine which can keep track of
"busy" devices in the 28FOO8SA array. After initiating
block erase on these components, the operating system
is free to concentrate on reads and writes, or any other
pending requests that demand its attention. The
28FOO8SA RY/BY# output alerts the system when
block erase completes, and the operating system acts on
this completion in the resulting interrupt service routine.
Hardware interrupt via the RY/BY# output is a recommended technique for block erase. However, this
method should be evaluated closely for alerting the system to byte write completion. The WSM typically completes a byte write attempt in 9 ,""S, a much shorter time
than that consumed in many CPU interrupt latencies.
In such cases, software polling of the 28FOO8SA Status
Register to detect WSM "ready", versus hardware interrupt, . will result in highest byte write performance.
Reference AP-359, "28FOO8SA Hardware Interfacing",
for circuit implementations that not only combine
RY/BY#s into a common INT, but also allow
RY/BY # masking if desired.
I
AP-364
ADDITIONAL INFORMATION
2BFOOBSA Datasheet
Order
Number
290429
2BFOOBSA-L Datasheet
290435
"2BFOOBSA Hardware
Interfacing"
"2BF008SA Software
Drivers"
292094
ER-27
"The Intel 28FOOBSA Flash
Memory"
294011
ER-28
"ETOX-III Flash Memory
Technology"
294012
AP-359
AP-360
292095
REVISION HISTORY
Description
PWD# pin renamed RP# to match JEDEC standards.
I
3-653
intel·
AP-375
APPLICATION
NOTE
Upgrade Considerations from
the 28F008SA to the 28F016SA
SALIM FEDEL
FLASH MEMORY APPLICATIONS ENGINEERING
March 1994
3-654
I
Order Number: 292124-001
Upgrade Considerations from the
28F008SA to the 28F016SA
CONTENTS
PAGE
1.0 PURPOSE ......................... 3-656
CONTENTS
PAGE
2.8 DC Compatibility ................. 3-660
2.9 Power Considerations ........... 3-660
2.0 SIMILARITIES AND DIFFERENCES
BETWEEN THE 28F016SA AND THE
28F008SA ........................... 3-656
3.0 HARDWARE DESIGN
CONSIDERATIONS ................. 3-661
2.1 Pinout Differences ............... 3-656
3.1 Hardware Upgradability .......... 3-661
2.1.1 Hardware Compatible
Configuration .................. 3-658
3.2 Hardware Decision Flowchart .... 3-661
2.3 Technology Comparison ......... 3-660
4.0 SOFTWARE DESIGN AND
UPGRADABILITY
CONSIDERATIONS ................. 3-662
2.4 Available Speeds ................ 3-660
4.1 Software Decision Flowchart .... 3-662
2.2 Compatible Command-Set ....... 3-659
2.5 Available Packages .............. 3-660
2.6 Operating Modes ................ 3-660
2.7 AC Compatibility ................. 3-660
5.0 COMPATIBLE SOFTWARE
ALGORITHM FLOWCHARTS ....... 3-663
6.0 SUMMARY ......................... 3-666
7.0 REFERENCES ..................... 3-666
I
3-655
AP·375
Order #
1.0 PURPOSE
The 28F016SA is the second member of Intel's
FlashFile™ memory family. Its architecture evolved
from that of the 28FOO8SA, Intel's first generation
FlashFile memory device. The 28F016SA retains the
standard 28FOO8SA's versatile capabilities and adds a
Command Superset architecture which insures compatibility with the basic command-set.
This application note shows how to upgrade an existing
28FOO8SA-based design to the new 28F016SA memory
device. Upgrades may require software modifications
depending on the desired system functionality and
straightforward hardware modifications to accommodate the new pinout.
2.0 SIMILARITIES AND DIFFERENCES
BETWEEN THE 28F016SA AND
THE 28F008SA
The 28F016SA memory is 100% command and algorithm, backward-compatible with the 28FOO8SA. It is
defined as a Superset device which brings additional
capabilities to system designs. Additional pins on the
28FO 16SA are added to define a user-selectable 8- or
16-bit wide memory, add on-chip write protection and
multiple chip select signals. Note that you do not have
to use the advanced features if you are performing a
simple upgrade to the 28F016SA.
28F008SA Data Sheet
28F016SA Data Sheet
28F016SA User's Manual
28F008SA Software Drivers
28F016SA Software Drivers
290429
290489
297372
292095
292126
2.1 Pinout Differences
Whereas the 28F008SA is 8-bit wide (40Ld-TSOP
package), the 28F016SA is a high performance 16-bit
wide flash file memory offering a user-configurable bus
width (56Ld-TSOP package). Hence an additional 8
I/O pins are on the 28F016SA. Furthermore, the implementation of additional features such as Write Protect and Block Locking and user-selectable 3.3V and
5V operation require the definition of control pins for
these functions. Finally, the optimization of the
28F016SA's architecture to achieve very high write
performance resulted in a different pinout configuration from the 28F008SA.
Both device pinouts preserve the locations of I/O pins
on the right-hand side and the sequence of pin functions of the 56Ld-TSOP package. However, it is still
required to relay out an existing PCB design in order to
accommodate the 16-Mbit chips. Table 1 lists all pin
names and their numbers, highlighting all the changes.
Before starting on your design upgrade, obtain the following specifications and application notes from Intel
Corporation Literature Sales, 1(800) 548-4725.
3-656 .
I
AP-375
Table 1. 28F008SA, 28F016SA Pin Comparison Chart
28FOO8SA 28F016SA 28FOO8SA 28F016SA
Notes
Pin Name Pin Name 40L-TSOP 56L-TSOP
Ao
24
32
A1
A1
23
28
A2
A2
22
27
A3
A3
21
26
A4
~
20,
A5
A5
19
As
As
A7
As
DOs
34
49
D07
D07
35
51
DOs
-
34
DOg
-
36
25
-
D010
24
-
D011
-
41
18
23
D012
-
45
A7
17
22
D013
16
20
Ag
Ag
15
19
-
-
47
As
-
52
A10
A10
14
18
CE#
CEo#
A11
A11
13
17
-
CE1#
-
2
2
A12
A12
8
13
RP#
RP#
12
16
3
A13
A13
7
12
RY/BY#
RY/BY#
36
53
4
A14
A14
6
11
OE#
OE#
37
54
WE#
WE#
Ao
A15
A15
5
10
A1S
A1S
4
8
A17
A17
3
7
A1S
A1S
2
6
A19
A19
1
5
-
A20
-
4
DOo
DOo
25
D01
D01
26
D02
D02
27
38
D03
D03
28
D04
D04
32
44
D05
33
46
D05
I
2BFOOBSA 2BF016SA 2BFOOBSA 2BF016SA
Notes
Pin Name Pin Name 40L·TSOP 56L-TSOP
-
DOs
-
D014
D015
14
38
55
-
31
WP#
-
56
3/5#
. Vpp
Vss
Vss
33
Vec
35
NC
40
50
BYTE #
Vpp
1
9
39
1
11
15
29,30
21,42,48
Vcc
10,31
9,37,43
NC
39,40
3,.29,30
5
6
NOTES:
1, Highest Order Address
2, Dual CEx#
3, Formerly Called PWD#
4, Open Drain for 2BF016SA
5, xB/x16 Selection
6, Selects Supply Voltage
3·657
AP-375
3/5#
2.1.1 HARDWARE COMPATIBLE
CONFIGURATION
The following is an example which shows the state of
all pins when operating in a 28FOO8SA-compatible
mode:
=
=
GND (5V operation) or Vee (3.3V oper-
ation)
5.0V or 3.3V
Vee
BYTE # = GND (8-bit mode)
RY /BY # = Level Mode (set for default) with an external pull-up resistor
=
Vee (Write Protect feature disabled)
CEI # (Chip Enable)
= -GND or Vee (selects upper/lower 1MB)
=
NOTE:
The 28FOO8SA has a CMOS driven RY/BY# output
for interrupt capability.
Vee
= 5V
5V
CE#
--t---I
RYBY#
CEo #
t - - - -.....
28F016SA
Address to Select
Between Upper and - - - - - ; A20
Lower 1 Mbyte
292124-1
Figure 1. 28F016SA Configured as a 28F008SA-Compatible Memory
3-658
I
AP-375
2.2 Compatible Command-Set
Byte Write
40H,IOH
Single Block Erase
Erase Suspend to Read
Read Array
20H
BOH
FFH
70H
ReadCSR
ClearCSR
Read Intelligent IDs
SOH
90H
Table 2. 28F008SA-Compatlble Commands
Command
Notes
Read Array
Intelligent Identifier
1
Second Bus Cycle
First Bus Cycle
Oper
Addr
Data
FFH
Read
AA
AD
90H
Read
IA
ID
Read
X
CSRD
Oper
Addr
Data
Write
X
Write
X
Read Compatible Status Register
2
Write
X
70H
Clear Status Register
3
Write
X
50H
Word/Byte Write
Write
X
40H
Write
WA
WD
Alternate Word/Byte Write
Write
X
10H
Write
WA
WD
Block Erase/Confirm
Write
X
20H
Write
BA
DOH
Erase Suspend/Resume
Write
X
BOH
Write
X
DOH
ADDRESS
AA = Array Address
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don't Care
DATA
AD = Array Data
CSR = Compatible Status Register
CSRD = CSR Data
GSR = Global Status Register
BSR = Block Status Register
ID = Identifier Data
WD = Write Data
NOTES;
1. Following the Intelligent Identifier command, two Read operations access the manufacturer and device signature codes.
2. The eSR is automatically available after device enters Data Write, Erase, or Suspend operations.
3. elears eSR.3, eSR.4 and eSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. See Status register definitions in the
28F016SA data sheet.
I
3-659
AP-375
2,3 Technology Comparison
2.7 AC Compatibility
Both the 2SFOl6SA and the 2SFOOSSA are manufactured on Intel's Flash ETOX process technology. This
technology is optimized for random access flash memory products with the highest read/write performance
and lowest power consumption. The ETOX flash technology achieves very high reliability and quality.
The 28FOl6SA specifies the output Load circuit as an
equivalent transmission line model which reflects the
timing delays more accurately. The same diode/resistor
circuit combination found in the 28FOOSSA data sheet
also applies to the 28FOI6SA.
2.4 Available Speeds
The 2SFOl6SA designed on a 0.6 /Lm ETOX IV process, achieves faster speeds than the 2SFOOSSA manufactured on O.S /Lm ETOX III process. Intel offers the
2SFOOSSA in 5V-read version with speeds at S5/90 ns
and 120 ns. The 2SFOl6SA on the other hand is offered
with a dual 3.3V and 5V read capability with speeds of
(70/S0 ns, 100 ns) and (120 ns, 150 ns) at 5V and 3.3V
respectively. Note that both devices are offered at faster
speeds (S5 ns and 70 ns) under reduced loading conditions. Please consult the data sheets referenced in this
application note.
Address and Data are latched on the rising edge of
WE# for both devices. All AC timing specifications
are similar except for the differences noted in the data
sheets. The 28FOl6SA has additional write timings describing the on-chip page buffers which do not exist on
the 28F008SA.
2.8 DC Compatibility
Whereas the 28F008SA only operates at 5V Vee and
the 28F008SA-L only operates at 3.3V Vee, the
28FOl6SA operates at both 3.3V and 5V Vee supply
voltages. In 5V mode of operation, the two devices are
similar in terms of input!output level specifications.
Consult the data sheets for differences in current consumption.
2.5 Available Packages
The 2SFOl6SA comes only in a 56Ld-Thin Small Outline Package (TSOP) optimized for its user-selectable
xS/xl6 memory architecture. The 28F008SA is offered
in 2 packages, which are the 40Ld-TSOP (both standard and reverse pinout) and the 44Ld-Plastic Small
Outline Package (PSOP).
2.9 Power Considerations
In addition to the active, standby and deep power-down
modes which exist on the 28F008SA, the 28FOl6SA
has additional current modes useful in power management applications .
.The two modes are:
2.6 Operating Modes
The 28FOl6SA behaves in the same manner as the
28F008SA. If a compatible command is written to the
device, the Compatible Status Register contents are automatically put on the data bus. With the block locking
disabled (WP# = high), the 28FOl6SA is identical to
the 28F008SA, regardless of any lock-bit settings which
define the lock state of a given block. The Command
User Interface (CUI), Write State Machine (WSM) and
Compatible Status Register (CSR) units function similarly on both devices.
The 28FOl6SA however, allows the user to issue multiple commands successively by watching the Queue bit
(GSR.3 or BSR.3), a feature which improves performance, as described in the 28FOl6SA user's manual.
Consult the 28FOl6SA data sheet and 28FOl6SA user's
manual for detail operation.
3-660
Automatic Power Saving feature which is activated
whenever the device addresses are not switching which
is equivalent to a static mode of operation on the chip is
accessed by a slowed clock. In this state, the chip typically draws less than I mA of total current.
The second low current mode of operation is enabled
through command control, using the Sleep command.
A Sleep command written to the device will put the
chip in the lowest current state (deep power-down level) after all active operations have been processed. The
device retains the value of its status registers while in
sleep mode.
Note that the AC and DC specifications mentioned
here are valid at the time this application note was written. Please reference the device data sheets for the latest
up-to-date specifications.
I
AP-375
3.0 HARDWARE DESIGN
CONSIDERATIONS
3.1
If you are considering a density upgrade to the
28FOl6SA, careful attention to certain areas must be
followed. This section is not intended to cover all potential issues related to system design, but rather as a
guideline in designing an upgrade to the 28FOI6SA.
Hardware Upgradability
The following flowchart summarizes the logical steps a
system designer must go through to complete a density
upgrade. This simple upgradability procedure allows
the 28F016SA-based system to achieve quicker time-tomarket while incorporating future expandability to take
advantage of the Superset features of the 28F016SA.
3.2 Hardware Decision Flowchart
TIE WP#
=Vee
=GNO
BLOCK LOCKING?
TIE BYTE#
TIE 3/5#
BUS WIDTH?
=GNO or Vee
RY /BY# MOOE?
CEO# tied to CE 1#
NO
USE EXTERNAL PULL -UP RESISTOR
CONfiGURE RY /BY# TO OEFAULT
LEVEL MOOE
292124-2
I
3-661
AP-375
4.0 SOFTWARE DESIGN AND
UPGRADABILITY
CONSIDERATIONS
Device Drivers for the 28FOO8SA and the 28F016SA
are provided in application notes AP-360 and AP-377
respectively.
In order to do a software upgrade to the 28F016SA, the
software designer must pay attention to a' few key areas.
They can be grouped as follows:
Software drivers written for the 28FOO8SA need torecognize the new device ID and change the memory size
boundaries in order to work on a 28F016SA-based system design.
Device Intelligent Identifier = AOH(versus A2H for
28FOO8SA)
Compatible Superset Commands
Compatible Status Register Checks only
Number of Erase Blocks
Note that ,the 28F016SA can be treated as two 8-Mbit
memory devices in a single package. The highest order
address pin A20 is used to switch between the upper
and the lower 1 Mbyte flash array. By preserving the
same basic software driver code, an upgrade to the
28F016SA enables the quickest time-to-market.
4.1 Software Decision Flowchart
">_......,~
FLASH MEMORY CHIP
NOT RECOGNIZED
YES
COMPATIBLE COMMANDS
8c
COMPATIBLE STATUS
REGISTER ONLY CHECKS
292124-3
3-662
I
Ap·375
5.0
COMPATIBLE SOFTWARE ALGORITHM FLOWCHARTS
Bus
Operation
Write
Command
Word/Byte
Write
Comments
D = 40Hor10H
A=X
Write
D=WD
A=WA
Read
Q = GSRD
Toggle GEo#, GEl #, or
OE # to update CSRD.
A=X
Standby
Check GSR.7
1 = WSMReady
0= WSM Busy
Repeat for subsequent Word/Byte Writes.
GSR Full Status Check can be done after each Word/Byte
Write, or after a sequence of Word/Byte Writes.
Write FFH after the last operation to reset device to Read
Array Mode.
See Command Bus definitions in the 28F016SA User's
Manual for description of codes.
292124-4
CSR FULL STATUS CHECK PROCEDURE
Bus
Operation
Data Write
Successful
Command
Comments
Standby
GheckGSRA
1 = Data Write Unsuccessful
o = Data Write Successful
Standby
CheckCSR.3
1 = Vpp Low Detect
0= VppOK
GSR.3/4 SHOULD be cleared, if set, before further attempts
are initiated.
Vpp Low Detect
292124-5
Figure 2. Word/Byte Writes
I
3-663
AP-375
Bus
Operation
Command
Write
Block Erase
D = 20H
A=X
Write
Confirm
D = DOH
A = BA
Comments
Read
Q = CSRD
Toggle CEo#, CEt #, or
OE # to update CSRD.
A=X
Standby
CheckCSR.7
1 = WSM Ready
0= WSMBusy
Repeat for subsequent Block Erasures.
CSR Full Status Check can be done after each Block Erase,
or after a sequence of Block Erasures.
Write FFH after t~e last operation to reset device to Read
Array Mode.
See Command Bus definitions in the 28F016SA User's
Manual for description of codes.
292124-6
CSR FULL STATUS CHECK PROCEDURE
Bus
Operation
Erase Successful
Vpp Low Detect
Command
Comments
Standby
CheckCSR.5
1 = Erase Error
o = Erase Successful
Standby
Check CSR.3
1 = Vpp Low Detect
0= VppOK
Standby
Check CSR.4, 5
Both set to 1 = Command
Se,quence Error
CSR.3/4/5 SHOULD be cleared, if set, before further attempts
are initiated.
Command, Sequence
Error
292124-7
Figure 3. Block Erase
3-664
I
AP-375
Bus
Operation
Write
Command
Erase
Suspend
Comments
0= BOH
A=X
Q = CSRD
Read
Toggle CEo#, CEl #, or OE#
to update CSRD.
A=X
Standby
Check CSR.7
1 = WSM Ready
0= WSM Busy
Standby
CheckCSR.6
1 = Erase Suspended
o = Erase Completed
Write
Read Array
D = FFH
A=X
Q = AD
Read
Read must be from block other
than the one suspended.
Write
Erase
Resume
D = DOH
A=X
See Command Bus definitions in the 28F016SA User's
Manual for description of codes.
292124-8
Figure 4. Erase Suspend to Read Array
I
3-665
AP-375
6.0 SUMMARY
This application note summarizes the upgrade considerations and compatibility areas between the 28FOl6SA
and the 28FOO8SA. It is merely intended as a simple
guideline to achieve a density and/or performance up-
grade and to point out the key issues that the hardware
and software designers must analyze during this process.
Consult the referenced documentation for a complete
understanding of compatibility and device capabilities.
7.0 REFERENCES
Document
Order Number
28F016SA Data Sheet
28F016SA User's Manual
DD28F032SA Data Sheet
AP-377 The 28F016SA Software Drivers
AP-378 System Optimization using the Enhanced Features of the 28F016SA
AP-362 Implementing Mobile PC Designs
Using High Density FlashFile™ Components
ER-33 ETOXIV Flash Memory Technology
28F008SA 8 MB (1 MB x 8) FlashFile™ Memory Data Sheet
AP-360 28F008SA FlashFile™ Software Drivers
ER-27 The Intel 28F008SA FlashFile™ Memory
290489
297372
290490
292126
292127
3-666
292097
294016
290429
292095
294011
I
AP-377
APPLICATION
NOTE
16-Mbit Flash Product Family
Software Drivers
28F016SA,28F016SV,
28F016XS, 28F016XD
TAYLOR GAUTIER
MCD.APPLICATIONS ENGINEERING
PATRICK KILLELEA
MCD APPLICATIONS ENGINEERING
SALIM FEDEL
MCD APPLICATIONS ENGINEERING
December 1994
I
oro" N"mbor. 292126-002
3-667
1S-Mbit FLASH PRODUCT FAMILY
SOFTWARE DRIVERS
CONTENTS
PAGE
INTRODUCTION .......................................................................... 3·669
28F016SA C DRIVERS ................................................................... 3·672
28F016SA ASM86 DRiVERS .......................................................... ; .. 3·694
APPENDIX A: FUNCTION CHANGES .................................................... 3·719
APPENDIX B: GLOSSARY OF TERMS ................................................... 3-720
APPENDIX C: ADDITIONAL INFORMATION ............................................. 3·721
3·66B
I
AP-377
INTRODUCTION
ABOUT THE CODE
This application note provides example software code
for word writing, block erasing, and otherwise controlling Intel's 28FOl6SA, 28F016SV, 28F016XS and
28F016XD (hereafter referred to as 28FOI6SA) 16
Mbit symmetrically blocked memory components. Two
programming languages are provided: high-level "C"
for broad platform support, and more optimized
ASM86 assembly. In many cases, the driver routines
can be inserted "as is" into the main body of code being
developed by the system· software engineer. Extensive
comments are included in each routine to facilitate
adapting the code to specific applications.
The internal automation of the 28F016SA makes soft"
ware timing loops unnecessary and results in platformindependent code. The following example code is designed to be executed in any type of memory and with
all processor clock rates. C code can be used with many
microprocessors and microcontrollers, while ASM86
assembly code provides a solution optimized for Intel
microprocessors and embedded processors.
The 28F016SA, like the 28FOO8SA, is divided into 64
Kbyte blocks. Since the GSR and BSR are defmed relative to the nearest preceding block beginning address, I
often refer to this "block base" address in the comments.
Assumptions:
• Pointers (in C) or ED! offsets (in ASM86) are four
(4) bytes long, providing a flat addressing space over
the entire 28F016SA device. This implies the use of
386 or higher machines. If the code is to be run on a
machine with a smaller address space; the code must
be modified to include some sort of "windowing"
scheme which maps segments of flash into system
memory. The Intel 82365 is commonly used for this
purpose.
• "Ints" are 16. bit and "longs" 32 bit in C.
• It is assumed that these pointers return a value equal
to what they are pointing to. In other words, even
though the pointer may be four (4) bytes long, this
does not imply that incrementing the pointer by one
will move the pointer four (4) bytes in memory. It is
entirely dependent upon what the pointer is pointing
to that determines how the increment will be effected. In the case of four (4) byte pointers and 16-bit
ints, incrementing the pointer by one will effectively
move the pointer two (2) bytes.
• There exists a function "set_pin" which can set an
individual 28FOl6SA pin, given the pin number.
I
• There exists a function "get_pin" which can return
the value of an individual 28FOl6SA pin, given the
pin number.
• The C code can access a function which derives the
corresponding block base address from any given
address.
o BYTE# pin on the device determines whether addressing refers to words or bytes. I assume word
writes/reads to a single device. With minor modifications this code can be adapted for a pair of
28F016SAs in Byte mode.
• 28F016SA commands can be written to any address
in the block or device to be affected by that command.
Both the C and ASM86 code in this document contain
the following routines, in this order:
CSR_word_byte_writes(compatiblewith 28FOO8SA)
CS~blocLerase(compatible with 28FOO8SA)
CS~erase~uspend_to.-read(compatible with
28F008SA)
lock__block
10c~tatus_uploaLto_BSR
update_data~n--..a_locked_block
add_data_in_a~ocked_block
ES~word_write
two_byte_write
ES~page_buffer_write
ES~blocLerase
ES~erase_aILunlocked_blocks
ESR_suspenLto.-read_array
ES~automatic_erase_suspend_to_write
ESR_full_status_check--..for_data_write
ES~fulLstatus_checLfor_erase
single_load_to_pagebuffer
sequentiaUoad_to_pagebuffer
upload_device~nformation
R YBY.-reconfiguration
page_buffer_swap
The names of these routines have been changed to more
closely match the algorithms presented in the
28F016SA User's Manual (Order Number 297372).
Please see Appendix A for a table documenting these
changes.
ABOUT THE 28FO.16SA
Companion product datasheets for the 28FOl6SA
should be reviewed in conjunction with this application
note for a complete understanding of the device.
The example code makes extensive use of bit-masking
when interpreting the status registers. As a quick review, note that any bit in a register can be tested by
bitwise ANDing the register with the appropriate power of two. Since all of the bits other than the one being
3-669
intel®
AP·377.
tested are masked out, testing the resulting byte for
truth is the same as testing the desired bit for truth. For
example, if a register contains 01001010, the test for bit
3 would be ANDing the register with 00001000, or hex
8, and testing the result for truth:
Binary
01001010
& 00001000
= 00001000
Hex
4A
&08
= 08
Register
Mask for bit 3
Result
GSR.7
Write State Machine
Status
1 = ready
0= busy
GSR.6
Operation-suspend
Status
1 = operation
suspended
0= operation in
progress/
completed
GSR.5
Device Operation
Status
1 = operation
unsuccessful
0= operation
successful or
running
GSR.4
Device Sleep Status
1 = device in sleep
0= device not in
sleep
GSR.3
Queue Status
1 = queue full
0= queue available
GSR.2
Page Buffer
Availability
1 = one/two page
buffers available
0= no page buffers
available
GSR.1
Page Buffer Status
1 = selected page
buffer ready
0= selected page
buffer busy
GSR.O
Page Buffer Select
Status
1 = page buffer 1
selected
0= page buffer 0
selected
BSR.7
Block Status
1 = ready
0= busy
BSR.6
Block-lock Status
1 = block unlocked
for write/erase
0= block lo_cked to
write/erase
BSR.5
Block Operation
Status
1 = error in block
operation0= successful block
operation
BSR.4
Block Operation Abort
Status
1 = block operation
aborted
0= block operation
riot aborted
BSR.3
Queue Status
1 = device queue full
0= device queue
available
BSR.2
VppStatus
1 = Vpp low detected
0= VppOKwhen
operation
occurred
BSR.1
Reserved for future
use
BSR.O
Reserved for -future
use
In this case the result byte is true, indicating that bit 3
in the register was a I.'
The meanings of the individual bits of these registers is
presented here for reference. Note that there are two
status register spaces, both of which are distinct from
the flash memory array address space. In the CSR
space, the CSR is mapped to every address. In the ESR
space, the GSR is mapped two words abovll the base of
each 64K byte block, i.e. to addresses 2,8002H,
l0002H, etc. (in word mode), while each BSR is similarly mapped one word above the base of each 64K byte
block to locations I, 800IH, looolH, etc. (in word
mode), each BSR reflecting the_status of its own block.
CSR.7 Write State Machine
Status
1 = ready
0= busy
CSR.6
Erase-suspend Status
1 = erase suspended
0= erase in progress/
completed
CSR.5
Erase Status
1 = error in block
erase
_0 = successful block
erase
CSR.4
Data-write Status
1 = error in data write
0= successful data
write
CSR.3
VppStatus
1 = Vpp low detect!
operation aborted
0= VppOKwhen
operation occurred
CSR.2
Reserved for future use
CSR.1
Reserved for future use
CSR.O
Reserved for future use
3-670
\
I
AP-377
28F016SA Commands
The 28F016SA command set is a superset of the
28FOO8SA command set, giving existing 28FOO8SA
code the ability to run on the 28F016SA with minimal
modifications.
28F008SA-Compatible Commands
00
invalid/reserved
28FO 16SA Performance-Enhancement
Commands
OC
page buffer write to flash
71
read GSR and BSRs (i.e. the ESR)
72
74
page buffer swap
single load to page buffer
75
read page buffer
77
lock block
20
single block erase
80
abort
40
wordlbyte write
96,01
RY/BY# enable to level-mode
50
clear status registers
96,02
RY /BY # pulse on write
70
read CSR
96,03
RY/BY# pulse on erase
90
read ID codes
96,04
RY /BY # pin disable
BO
erase suspend
97
upload BSRs with lock bit
DO
confirm/resume
99
upload device information
FF
read flash array
A7
erase all Unlocked blocks
EO
FO
FB
sequential load to page buffer
I
sleep
two-byte write
3-671
AP-377
"c" DRIVERS
/********"*******************************************************************/
/* Copyright Intel Corporation, 1993
/* File: stddefs.h
*/
*/
/* Standard definitions for C Drivers for the 28F016SA/SV/XS/XD Flash
*/
/* memory components
/* Author: Taylor Gautier, Intel Corporation
/* Revision 1.0, 23 September 1994
*/
*/
*/
/***************************************************************************/
/***************************************************** **********************1
/* pin values
*/
/******************~********************************** **********************/
#define LOW
#define HIGH
0
1
1***************************************************************************1
/ * error codes
*/
/***************************************************************************/
#define
#define
.define
#define
#define
#define
NO_EMOR
VPP_LOW
0
1
OP~ORTED
2
8LOCR_LOCKBD
COHNAND_SEQ_ERROR
WP_LOW
3
4
5
1***************************************************** **********************/
/* bit masks
*/
/***************************************************************************/
#define
#define
#define
#define
#define
#define
#define
#define
BIT_O
BIT_1
BIT_2
8IT_3
BIT_4
BIT_5
8IT_6
8IT_7
'define LOW_BYTE
#define HIGH_BYTE
OxOOOl
Ox0002
Ox0004
Ox0008
Ox0010
Ox0020
Ox0040
Ox0080
OxOOFF
OxFFOO
/***************************************************************************/
/* RY/BY# enable modes
*/
/***************************************************************************/
#define
#define
#define
#define
RYBY_ENABLE_TO_LEVEL
RYBY_POLSE_ON_WRITE
RYBY_POLSE_ON_ERASE
RY8Y_DISABLE
1
2
3
4
/***************************************************************************/
/ * pin numbers
*/
/***************************************************************************/
#define WPB 56
/* Write Protect pin (active low) is pin number 56 on standard
/* pinout of 28F016SA.
#define VPP 15
/* Vpp pin is pin number 15 on standard pinout of 28F016SA.
*/
*/
*/
292126-1
3-672
I
AP-377
/***************************************************** **********************1
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
1*
Copyright Intel Corporation, 1993
File: drivers.c
Example C Routines for 28FOl6SA/SV/XS/XD Flash memory components
Original Author : Patrick Killelea, Intel Corporation
Revised By : Taylor Gautier, Intel Corporation
Revision 2.0, 23 September 1994
NOTE: BYTE# pin on the device determines whether addressing
refers to words or bytes. I assume word mode.
NOTE: A 28FOl6SA command can be written to any address in the
block or device to be affected by that command.
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
/***************************************************************************/
#include
#include "stddefs.b"
void set-pin(int pin, int level)
{
1* set-pin is an implementation-dependent function which sets a
1* given pin on the standard 28FOl6SA pinout HIGH = 1 or LOW = o.
}
*1
*1
int get-pin(int pin)
{
1* get-pin is an implementation-dependent function which returns a
1* given pin on the standard 28FOl6SA pinout HIGH = lor LOW = 0
}
*1
*1
int *base(int *address)
{
1* base is an implementation-dependent function which takes an
/* address in the flash array and returns a pointer to the base
1* of that 64K byte block.
}
cbar
*byte~ase(cbar
*1
*1
*1
*address)
{
1* byte version of base function described above
*1
}
292126-2
I
3-673
int CSR_word_byte_writes(int *address, int data)
{
/* This procedure writes a byte to the 28F016SA.
*/
/* It also works with the 28F008SA.
*/
int CSR,
/* CSR variable is used to return cont.ents of CSR register.
*/
*address • OXIOIO,
/ * . Word Wri te corrunand
*address = data,
/* Actual data write to flash address.
while(I(BIT_7 & *address»,
/* Poll CSR until CSR.7 = 1 (WSM ready)
CSR = *address,
/* Save CSR before clearing it.
*address • OXS050,
/* Clear Status Registers corrunand
*address = OxFFFF,
/* Write FFH after last operation to reset device to read array mode.
return(CSR);
/* Return CSR to be checked for status of operation.
} .
*/
*/
*/
*/
*/
*/
*/
292126-3
3·674
I
AP-377
int CSR_block_erase(int *address)
(
/* This procedure erases a 64K byte block on the 2BF016SA.
*/
int CSR;
/* CSR variable is used to return contents of CSR register.
*address
*/
= OX2020;
/ * Single Block Erase corrnnand
*/
*address = OXDODO;
/* Confirm command
*/
*address = OxDODO;
/* Resume command, per latest errata update
while(I(BIT_7 & *address»
*/
/* Poll CSR until CSR.7
*/
=1
(WSM ready)
{
/* System may issue an erase suspend corrnnand (BO[BO]) here to read data
/* from a a different block.
*/
*/
};
/* At this point, CSR.7 is 1, indicating WSM is not busy.
/* Note that we are still reading from CSR by default.
CSR = *address;
/* Save CSR before clearing it.
~address = OX5050;
/* Clear Status Registers corrnnand
*address = OxFFFF;
/* Write FFH after last operation to reset device to read array mode.
*/
*/
*/
*/
*/
-return (CSR) ;
/* Return CSR to be checked for status of operation.
*/
}
/* If a write has been queued, an automatic erase suspend occurs to write
/* to a different block.
*/
*/
292126-4
I
3-675
AP-377
intel®
int CSR_erase_suspend_to_read(int *read_address, int *eraBe_addresB, int
*result)
{
1* This procedure suspends an erase operation to do a read.
int CSR,
1* CSR variable is used to return contents of CSR register.
*1
1* Assume erase is underway in block beginning at erase_address.
*eraBe_addresB • OXBOBO,
1* Erase Suspend command
while(I(BrT_7 & *erase_addresB»,
1* Poll CSR until CSR.7 = 1 (WSM ready)
if (BrT_6 & *erase_address) {
1* If CSR.6 = 1 (erase incomplete)
*eraBe_addreBs • OXPFFFI
1 * Read Flash Array command
*result • *read_addreBs,
1* Do the actual read. Any number of reads can be done here.
*eraBe_addreBB • OXDODO,
1* Erase Resume command
} else {
*erase_addreBB • OXPFFF,
1* Read Flash Array command
*result • *read_addreBsl
1* Do the actual read. Any number of reads can be done here.
*1
*erase_addreBB = Ox7070;
1* Read CSR command
CSR • *eraBe_address,
1* Save CSR before clearing it.
*eraBe_address • OX5050,
1* Clear Status Registers command
return (CSR) I
1* Return CSR to be checked for status of operation.
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
*1
}
292126-5
3-676
I
Ap·377
int lock_block(int *lock_address)
/* This procedure locks a block on the 28F016SA.
{
*/
int ESR;
/* ESR variable is used to return contents of GSR and BSR.
*/
int *block_base = base(lock_address);
/* Find pointer to base of block being locked.
*/
*lock_address Q OX7171;
/*'Read Extended Status Registers command
while (BIT_3 & *(block_base + 2»;
/* Poll GSR until GSR.3
0 (queue available) .
set-pin(WPB, HIGH);
/* Disable write protection by setting WPB high.
set-pin(VPP, HIGH),
/* Enable Vpp, wait for ramp if necessary in this system.
*lock_address = OX7777,
/* Lock Block command
*lock_address • OXDODO;
/* Confirmation command
*lock_address = OX7171;
/* Read Extended Status Registers command
while (I(BIT_7 & *(block_base + 2»),
/* GSR is 2 words above 0; poll GSR until GSR.7 = 1 (WSM ready).
=
ESR = (*(block_base + 2) « 8) + (*(block_base + 1) & LOW_BYTE);
/* Put GSR in top byte and BSR in bottom byte of return value.
*lock_address = OXSOSO;
/* Clear Status Registers command
*lock_address = OxPFFF;
/* Write FFH after last operation to reset device to read array mode.
return (ESR) ;
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
}
292126-6
I
3-677
intel
AP-377
®
iot lock_status_upload_to_BSR(iot *address)
/* This procedure uploads status information into the BSR from nOIl/* volatile status bits.
*/
*/
{
iot ESR,
/* ESR variable is used to return contents of GSR and BSR.
iot *block_base = base(address);
*/
/* Find pointer to base of 32K word block.
*/
*address a OX7171,
/* Read Extended Status Registers command
while (BIT_3 « *(block_base + 2»; .
*/
/* Poll GSR until GSR.3
*/
=a
(queue available).
*address • OX9797,
/* Lock-status Upload command
*address
a
*/
OXDODO;
/* Confirmation command
*/
*address • OX7171,
/* Read Extended Status Registers command
« *(block_base + 2»);
/* Poll GSR until GSR.7
1 (WSM not busy)
while (I (BIT_7
=
*/
*/
(*(block_base + 2) « 8) + (*(block_base + 1) « LOW_BYTE),
/* Put GSR in top byte and BSR in bottom byte of return value.
*address = OXSOSO;
/* Clear Status Registers command
*/
*address • OxPPPP,
/* Write FFH after last operation to reset device to read array mode.
return (ESR) ,
*/
ESR •
*/
}
292126-7
3-678
I
AP-377
int update_data_in_a_locked_block()
{
/* This routine is implemented as pseudo-code to provide an example of
/* impementing the flowchart Updating Data in a Locked Block from the
/* 28F016SA User's Manual
*/
*/
*/
set-pin(WPB, HIGH);
/* set WP# high
*/
block_erase_with_CSR(block_address);
/* erase block
*/
set-pin(WPB, LOW);
/* set WP# low
*/
WriteNewData();
/* Use one of Word/Byte Write, Two-Byte Write or Page Buffer Write to Flash*/
lock_block(block_address);
/* lock block if desired
*/
}
int add_data_in_a_locked_block()
{
/* This routine is implemented as pseudo-code to provide an example of
/* impementing the flowchart Updating Data in a Locked Block from the
/* 28F016SA User's Manual
*/
*/
*/
set-pin(WPB, HIGH);
/* set WP# high
*/
WriteNewData();
/* Use one of Word/Byte Write, Two-Byte Write or Page Buffer Write to
/* Flash
set-pin(WPB, LOW);
/* set WP# low
*/
*/
*/
}
292126-8
I
3·679
AP-377
int
BS~word_write(int
*write_address, int*data, int
wor~count)
/* This procedure writes a word to the 28F016SA.
*/
(
int counter, BSR,
/* counter is used to loop through data array
/* ESR variable is used to return contents of GSR and BSR.
int *bloc~ase = base(write_address),
for (counter. 0, counter < word_count, counter++)
*write_address • OX7171,
/* Read Extended Status Registers command
while (BIT_3 & *(block_base +1», ,
/* Poll BSR until BSR.3 of target address
o (queue available).
/* BSR is 1 word above base of target block in status reg space.
*write_address • OXI0I0,
/* Write word command
*write_address • data[counter],
/* Write actual data.
.*write_address • OX7171,
/* Read Extended Status Registers command
while (I (BIT_7 & *(bloc~ase + 1»),
/* Poll BSR until BSR.7 of target address = I (block ready).
BSa • (*(bloc~base + 2) « 8) + (*(block_base + 1) & LOW_BYTB),
/* Put GSR in top byte and BSR in bottom byte of return value.
*write_address = OXSOSO,
/* Clear Status Registers command
*write_address = OxPPPP,
/* Write FFH after last operation to reset device to read array mode.
return (BSR) I
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/'
)
292126-9
3-680
I
AP-377
int two_byte_write(char *address, char *data, int byte_count)
/* This routine is used when BYTE# is low, i.e. the 28FDl6SA
/* is in byte mode, to emulate a word write.
/* Because of this, commands are given as DxODXY instead of DxXYXY as in
/* the rest of the code presented here.
/* *data is a byte array containg the low byte, high byte consecutively of
/ * each word.
*/
*/
*/
*/
*/
*/
{
int counter, ESR;
/* ESR variable is used to return contents of GSR and BSR.
char *block_base = byte_base(address);
*/
/* Find pointer to base of block.
*/
for (counter = 0; counter < byte_count; counter++)
*address = OX0071;
/* Read Extended Status Registers command
*/
while (BIT_3 & *(block_base + 2»;
/* Poll BSR until BSR.3 of target address
0 (queue available).
*/
*address = OXOOFB;
/* Two-byte Write command
*address
=
*/
data[counter++];
/* Load one byte of data register; AD = 0 loads low byte, Al high
*/
*address = data[counter];
/* 28FDl6SA automatically loads alternate byte of data register
/* Write is initiated. Now we poll for successful completion.
*/
*/
*address = OX0071;
/* Read Extended Status Registers command
*/
while (I (BIT_7 & *(block_base + 2»);
/* Poll BSR until BSR.7 of target address
1 (block ready).
/* BSR is 1 word above base of target block in status reg space.
*/
*/
ESR = (*(block_base + 4) «
8) + (*(block_base + 2) & LOW_BYTE);
/* Put GSR in top byte and BSR in bottom byte of return value.
*/
*address = OXOOSO;
/* Clear Status Registers command
*/
*address a OxOOFF;
/* Write FFH after last operation to reset device to read array mode.
return(ESR);
*/
}
292126-10
I
3-681
AP-377
int ESR-pagebuffer_write(int *address, int word_count)
/* This procedure writes from page buffer to flash.
*/
{
This routine assumes page buffer is already loaded.
Address is where in flash array to begin writing.
Low byte of word count word_count must be 127 or fewer, high must be
High byte of word count exists for future Page Buffer expandability.
int ESR,
/* ESR variable is used to return contents of GSR and BSR.
int *block_base .. base(address);
/* Find pointer to base of block to be written.
/*
/*
/*
/*
o.
*/
*/
*/
*/
*/
*/
*address = OX7171,
/* Read Extended Status Registers command
*/
while (BIT_3 « *(block_base + 1»;
/* Poll BSR until BSR.3 of target address
o (queue available).
*/
*address .. OXOCOC,
/* Page Buffer Write to Flash command
*/
*address • word_count,
/* high byte is a don't care, write the low byte
*/
*address .. 0;
/* write high byte of word_count which must be 0 (reserved for future use) */
*address ~ OX7171,
/* Read Extended Status Registers command
*/
while (I (BIT_7 « *(block_base + 1»),
/* Poll BSR until BSR.7 of target address =1 (block ready).
*/
ESR .. (* (block_base + 2) « 8) + (* (block_base + 1) « LOW_BYTE};
/* Put GSR in top byte and BSR in bottom byte of return value.
*address .. OX5050,
/* Clear Status Registers command
*address .. OxFFFF;
/* Write FFH after last operation to reset device to read array mode.
return(ESR),
*/
*/
*/
}
292126-11
3·682
I
AP-377
int ESR-plock_erase(int *erase_address)
1* This procedure erases a block on the 28F016SA.
*/
(
int ESR,
1* ESR variable is used to return contents of GSR and BSR.
int *bioc~base • base(erase_address),
1* Find address of base of block being erased.
*erase_address = OX7171;
/* Read Extended Status Registers command
while (BXT_3 & *(block-pase + 1»,
1* Poll BSR until BSR.3 of erase_address = 0 (queue available) .
1* BSR is 1 word above base of target block in ESR space.
*erase_address • OX2020;
1* Single Block Erase command
*erase_address • OXDODO,
1* Confirm command
*erase_address • OxDODO,
1* Resume command, per latest errata update
*erase_address • OX7171,
1* Read Extended Status Registers command
while (I (BXT_7 & *(block-pase + 1»);
/* Poll BSR until BSR.7 of target erase_address
*/
*/
*/
*/
*/
*/
*/
*/
*/
=1
(block ready).
ESR. (*(blOCk-Pase + 2) « 8) + (*(block_base + 1) & LOW_BYTE);
1* Put GSR in top byte'and BSR in bottom byte of return value.
*erase_address • OX5050,
1* Clear Status Registers command
*erase_address = OXPPFP,
1* Write FFH after last operation to reset device to read array mode.
return (BSR),
*1
*/
*/
*/
}
292126-12
I
3-683
AP-377
int ESR_erase_all_unlocked_blocks(int *device_address, long *failure_list)
/* This procedure erases all the unlocked blocks on a 28F016SA.
*/
{
int GSR;
/* Return value will contain GSR in both top and bottom byte.
*/
/* 32 bit long pointed to by failure_list is used to return map
/* of block failures, each bit representing one block's status.
*/
*/
/* device_address points to base of chip.
*/
int block;
/* block is used to hold block count for loop through blocks.
long power - 1;
*/
*failure_list = 0;
/* Initialize all 32 bits of failure list long to O.
*device_address • OX7171;
/* Read Extended Status Registers
while (BIT_3 & *(device_address + 1»;
/* Poll BSR until BSR.3 of target address
0 (queue available).
*device_address • OXA7A7;
/* Full-chip erase command
*device~address • OXDODO;
/* Confirm command
*device_address • OX7171;
*/
*/
*/
*/
*/
'/* Read Extended Status Registers command
*/
while (I (BIT_7 & *(device_address + 2»);
/* Poll GSR until GSR.7 = 1 (WSM ready)
*/
for (block. 0; block < OX0020; block++)
{
/* Go through blocks, looking at each BSR.5 for operation failure
/* and setting appropriate bit in long pointed to by failure list.
*/
*/
if (BIT_5 & *(device_address + block * OXBOOO + 1»
/* Multiply block by 32K words to get to the base of each block.
*/
*fai1ure_list +- power;
/* If the block failed,
power • power «
set that bit in the failure list.
*/
1;
/* Increment to next power of two to access next bit.
GSR • *(device_address + 2);
*device_address • OX5050;
/* Clear Status Registers command
*device_address • OXFFFF;
/* Write FFH after last operation to reset device to read array mode.
return (GSR) ;
*/
*/
*/
}
292126-13
3-684
I
Ap·377
int ESR_suspend_to_read_array(int *address,int *resu1t)
/* This procedure suspends an erase on the 28F016SA.
*/
(
/* Address is assumed to point to location to be read.
*/
/* result is used to hold read value until procedure is complete.
*/
int ESR;
/* ESR variable is used to return contents of GSR and BSR.
int *b1ock_base
*address
=
= base(address);
*/
OX7171;
/* Read Extended Status Registers command
while (I (BIT_7 & *(b1ock_base + 1»);
*/
/* Poll BSR until BSR.7 of target address
1 (block ready).
/* BSR is 1 word above base of target block in ESR space.
*address = OXBOBO;
/* Operation Suspend command
*address = OX7171,
/* Read Extended Status Registers command
while (I (BIT_7 & *(b1ock_base + 2»);
/* Poll ~SR until GSR.7 = 1 (WSM ready).
if (BIT_6 & *(b1ock_base + 2»
{
/* GSR.6 = 1 indicates an operation was suspended on this device,
*address = OXPFFF;
*/
*/
/* Read Flash Array command
*resu1t
= *address;
/* Read the data.
*address = OXDODO;
/* Resume the operation.
} else {
*address = OXFFFF;
*/
*/
*/
*/
*/
*/
*/
/* Read Flash Array command
*/
*resu1t - *address;
/* Read the data.
*/
}
*address • Ox7171;
/* Read Extended Status Registers command
BSR = (*(block_base + 2) « 8) + (*(block_base + 1) & LOW_BYTE);
/* Put GSR in top byte and BSR in bottom byte of return value.
*address = OX5050;
/* Clear Status Registers command
return (ESR) ;
*/
*/
*/
}
292126-14
I
3-685
AP-377
int ESR_automatic_erase_suspend_to_write(int *write_address, int
*erase_address, int data)
/* 'rhis procedure writes to one block while another is erasing.
{
int ESR;
/* ESR variable is used to return contents of GSR and BSR.
int * block_base. base(erase_address);
/* Find pointer to base of block being erased.
*/
*/
*/
*erase_address • OX7171;
/* Read Extended Status Register command
while (BrT_3 « *(block_base + 1»;
/* Poll BSR until BSR.3 of target address
*/
0 (queue available) .
*/
/ * BSR is 1 word above base of target bl'ock in ESR space.
*/
*erase_address • OX2020;
/* Erase Block command
*erase_address ~ OXDODO;
*/
/ * Confirm command
*/
*erase_address • OX7171;
/* Read Extended Status Register command
while (BrT_3 « *(block_base + 1»;
/* Poll BSR until BSR.3 of target address
0 (queue available).
/* BSR is 1 word above base of target block in ESR space.
*write_address • OX4040;
/* Word Write command
*write_address = data;
*/
*/
*/
*/
/* Write actual data.
*/
/* Erase suspends, write takes place, then erase resumes.
*erase_address • OX7171;
/* Read Extended Status Registers command
while (I(BrT_7 « *(block_base + 1»);
/* Poll BSR until BSR.7 of erase address = 1 (block ready).
/* BSR is 1 word above base of target block in status reg space.
*/
8) + (*(block_base + 1) « LOW_BYTE);
/* Put GSR in top byte and BSR in bottom byte of return value.
*/
*/
*/
ESR. (*(block_base + 2) «
*block_base • OX5050;
/* Clear Status Registers command
*block_base = OxFFFF;
/* Write FFH after last operation to reset device to read array mode.
return(ESR);
*/
*/
*/
}
292126-15
3-686
I
AP-377
int
ESR_full_~tatua_check_for_data_write(int
*device_addreaa)
{
int errorcode,
*device_addreaa • Ox7171,
/* Read Extended Status Resisters command
while (J(BIT_7 & *(device_addreaa + 2»)
/* Poll GSR until GSR.7 = 1 (WSM ready)
/* to make sure data is valid
*/
*/
*/
if (*(deviee_addreaa + 1) & BIT_2) erroreode = VPP_LON;
/* BSR.2 = 1 indicates a Vpp Low Detect
e1ae if (*(deviee_addreaa + 1) & BIT_4) errore ode = OP~ORTED;
/* BSR.4 = 1 indicates an Operation Abort
e1ae if (get-pin(NPB) •• LON) erroreode = NO_ERROR;
e1ae if (*(deviee_addreaa + 1) & BIT_6) erroreode _
/* BSR.6 = 1 indicates the Block was locked
e1ae erroreode •. NO_BRROR,
"/
*/
BLOC~LOCKED;
*/
while (J(BIT_7 & *(device_addreaa + 2») ;
/* Poll GSR until GSR.7 = 1 (WSM ready)
/* make sure chip is ready to accept command
*/
*/
*device_addreaa
Ox5050;
/* Clear Status Registers
*/
return.errorcode,
}
292126-16
I
3-687
AP-377
int
BSR_full_BtatuB_ehee~for_eraBe(int *deviee~addreBB)
(
int errore ode • NO_BRROR,
*deviee_addreBB • Ox7171,
/* Read Extended Status Resisters command
while (I (BIT_7 & *(deviee_addreBB + 2»),
/* Poll GSR until GSR.7 = 1 (WSM ready)
/* make sure command completed
if (*(deviee_addreBB + 1) & BIT_2) erroreOde • VPP_UOW,
/* BSR.2 = 1 indicates a Vpp Low Detect
elBe if (*(deviee_addreBB + 1) & BIT_4) erroreode • OP~ORTBD,
/* BSR.4 = 1 indicates an Operation Abort
elBe if (get-pin(WPB) •• UOW && I (*(deviee_addreBB + 1) & BIT_6»
errorcode • BLOCK_LOCKBD,
/* BSR.6 = 0 indicates the Block was locked
if (erroreode •• NO_BRROR) (
*deviee_addreBB • Ox7070,
/* Read Compatible Status Register
if «*deviee_addreBB & BIT_4) && (*deviee_addreBB & BIT_5»
/* CSR.4 and CSR.5 == 1 indicate a command sequence error
erroreode • COMMAND~SB~BRROR,
*/
*/
*/
*/
*/
*/
*/
*/
}
while (I (BIT_7 & *(deviee_addreBB + 2»)
/* Poll GSR until GSR.7
1 (WSM ready)
/* make sure device is ready
*/
*/
*deviee_addreBB • Ox5050,
/* Clear Status Registers command
*/
=
return erroreode,
}
292126-17
3-688
I
Ap·377
void single_load_to-pagebuffer(int *device_address, char *address, int data)
/* This procedure loads a single byte or word to a page buffer.
/* device_address points to base of chip.
*/
*/
{
*device_address = OX7171;
/* Read Extended Status Registers command
*/
while (I (BIT_2 & *(device_address + 2»);
/* Poll GSR until GSR.2 = I (page buffer available)
*/
*device_address = OX7474;
/* Single Load to Page Buffer command
*/
*address = data;
/* Actual write to page buffer
/* This routine does not affect status registers.
*/
*/
*address • OxFFFF;
/* Write FFH after last operation to reset device to read array m o d e . * /
}
292126-18
I
3-689
Ap·377
void sequential_load_to-pagebuffer(int *device_address, char *start_address,
int word_count, int* data)
/* This procedure loads multiple words to a page buffer.
*/
/* device_address points to base of chip.
*/
{
/* Low byte of word_count must be 127 or fewer, high must be O.
/* word_count is zero~based counting, i.e word_count == 0 loads 1 word,
/* word_count == 1 loads 2 words etc.
/* High byte of word_count exists for future Page Buffer expandability.
char counter;
/* counter is used to keep track of words written.
*device_address = OX7171;
/* Read Extended Status Registers command
while (BIT_2 & *(device_address + 2»;
/* Poll GSR until GSR.2 = 0 (page buffer available) .
*device_address a OXEOEO;
/* Sequential Page Buffer Load command
*start_address • word_count;
*start_address = 0';
/* Automatically loads high byte of count register
for (counter ~ 0; counter <= word_count; counter++)
*(start_address + counter) = data[counter);
/* Loop through data, writing to page buffer.
/* This routine does not affect status registers.
*device_address = OxFPPP;
/* Write FFH after last operation to reset device to read array mode.
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
}
292126-19
3-690
I
AP-377
int upload_device_information(int *address)
/* This procedure uploads the device revision number to the variable DRC.
/* This implementation differs in that it does not loop as in the
/* algorithm.
This is so the calling routine can have a chance to do
/* error checking instead of looping forever waiting for the device
/* complete the operation.
*/
*/
*/
*/
*/
(
int DRC = 0;
/* DRC variable is used to return device revision status.
int *block_base = base(address);
/* Find pointer to base of 32K word block.
*/
*/
*address = OX7l71;
/* Read Extended Status Registers command
*/
while «BIT_3 & *(block_base + 2» && (I (BIT_7 & *(block_base + 2»»;
/* Poll GSR until GSR.3
0 (queue available) and GSR.7 = 1
*/
/* (WSM available).
*/
*address = OX9999;
/* Device information Upload command
*/
*address = OXDODO;
/* Confirmation command
*/
*address = OX717l;
/* Read Extended Status Registers command
*/
while (I (BIT_7 & *(block_base + 2»);
/* Poll GSR until GSR.7 = 1 (WSM not busy)
*/
if (BIT_5 & *(block_base+2» return «*(block_base+2) & HIGH_BYTE) « 8);
/* if GSR.5 = 1 operation was unsuccessful.
Return GSR and 0 in DRC
*/
*address = OX7272;
/* Swap page buffer to bring buffer with status information to top.
*/
*address = OX7575;
/* Read Page Buffer command
*/
DRC .. (*(block_base +2) & OXFFOO « 8) + (*(block_base + 3) & LOW_BYTE);
/* Put GSR in top byte of return value.
*/
/* User should check GSR for operation success
*/
/* Put device revision code in bottom byte of return value.
*/
/* Note that device revision code was read from word 3 in page buffer.
,*/
*address = Ox5050;
/* Clear Status registers command
*/
*address = OxFFFF;
/* Write FFH after iast operation to reset device to read array mode.
*/
return(DRC);
=
}
292126-20
I
3·691
AP-377
int RYBY_reconfigure(int *address, int mode)
{
/* this procedure changes the RY/BY~ configuration mode to the given mode
int GSR;
/* the GSR variable is used to return the value of the GSR
*address = Ox7l7l;
/* Read Extended Registers command
while (BIT_3 & *(address+2));
/* Poll GSR until GSR.3 = 0 (queue available)
*address = Ox9696;
/* Enable RY/BY~ configuration, next command configures RY/BY~
switch (mode) {
case RYBY_ENABLE_TO_LEVEL:
*address ~ OxOlOl;
/* Enable RY/BY~ to level mode
break;
case RYBY_PULSE_ON_WRITE:
*address = Ox0202;
/* Enable RY/BY~ to pulse on write
break;
case RYBY PULSE_ON_ERASE:
*address = Ox0303;
/* Enable RY/BY~ to pulse on erase
break;
case RYBY_DISABLE:
default:
*address = Ox0404;
/* Enable RY/BY~ to disable
break;
*address = OX7l7l;
/* Read Extended Status Registers command
while (I (BIT_7 & *(address + 2))) ;
/* Poll GSR until GSR.7 = 1 (WSM ready)
GSR = *(address+2) & LOW_BYTE;
/* put GSR intn low byte of return value
*address = Ox5050;
/* Clear Status registers command
*address = OxFFFF;
/* Write FFH after last operation to reset device to read array mode.
return (GSR);
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
}
292126-21
3-692
I
AP-377
int page_buffer_swap(int *address)
{
This routine attempts to swap the page buffers, returning the value of
the GSR before the operation in the upper byte and the value of the GSR
after the operation in the lower byte for comparison
For operation to be successful, the following must be true:
/* (before) GSR.O = (after) !GSR.O
/* (after) GSR.5 = 0
int GSR;
/* GSR variable is used to return contents of GSR before and after
/* operation
/*
/*
/*
/*
*address = Ox7171;
/* Read Extended Registers command
GSR = *(address+2) « 8;
/* Put GSR into upper byte before page buffer swap
*address = Ox72721
/* write Page Buffer Swap command
GSR 1= (*(address+2) & LOW_BYTE);
/* Put GSR after operation into low byte for comparison
*address = Ox5050;
/* Clear Status registers command
*address = OxFFFF;
/* Write FFH after last operation to reset device to read array mode.
return (GSR);
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
}
292126-22
I
3·693
AP-377
ASM86 ASSEMBLY LANGUAGE DRIVERS
.----------------------------------------------------------------------,-----------------------------------------------------------------------
Copyright Intel Corporation, 1993
EXAMPLE ASM86 Drivers for the 28F016SA Flash memory component
Original Author : Patrick Killelea, Intel Corporation
Revised By : Taylor Gautier
Revision 2.0, September 26, 1994
NOTE:
The code assumes 32-bit flat model protected mode for simplicity.
i.e. ES contains 0 and EDI accesses the entire memory space.
;=======================================================================
'l'EX'l'
segment byte
public
assume cs :'l'EX'l'
'CODE'
Following is the structure by which all parameters are passed.
params S'l'RUC'l'
erase_addr
DD
base of block or device to
?
erase
write...:addr
DD
address to write to
?
write_base
base address of block written
DD
?
to
read_addr
DD
address to read from
?
read_base
base address of block read from
DD
?
lock_addr
base address of block to lock
DD
?
data_addr
DD
address of data to write
?
data
?
data word to write
DW
pagebuffer_start_addr DB
start address in page buffer
?
word_count
DW
?
number of words for a multiple
read/write
params ENDS
i===================================================== ==================
; Defines
;=======================================================================
i===================================================== ==================
; Error Codes
j===================================================== ==================.
NO_ERROR
DW
0
VPP_LOW
DW
1
OP_ABOR'l'ED
DW
2
BLOCK_LOCKED
DW
3
COMMAND_SE~ERROR
WP_LOW
DW
DW
4
5
;=======================================================================
; Error Codes
a
______________________________________________________________________ _
,-----------------------------------------------------------------------
RYBY_BNABLE_'1'O_LBVEL DW
1
RYBY_PULSE_ON_WRI'l'E
2
DW
RYBY_PULSE_ON_ERASE
DW
3
RYBY_DISABLE
DW
4
;=======================================================================
; MACRO set-pin
; This macro pushes parameters needed for the set-pin routine, calls
292126-23
3-694
I
AP-377
set-pin, and then pops those parameters. set-pin is an implementationdependent function which sets a given pin on the standard 28FOl6SA
pinout HIGH = 1 or LOW = o.
Data needed at the beginning of this macro:
pin: 28FOl6SA pin number
level:
level to set pin
'Trashes: CX
j=======================================================================
set-pin pin, level
MACRO
pin
push
Push pin number
push
level
Push logic level of pin
call
near ptr set...pin
Call set-pin
pop
CX
Pop off parameters
pop
CX
ENDH
j=======================================================================
; MACRO J3SROFF
; 'This macro takes a pointer and increments it by two byte~. Use this
; macro for obtaining the offset to the J3SR from a block base address
j=======================================================================
MACRO BSROPP pointer
add
pointer, 2
J3SR is 2 bytes above base
address
.----------------------------------------------------------------------,-----------------------------------------------------------------------
; MACRO GSROFF
; This macro takes a pointer and increments it by four bytes. Use this
; macro for obtaining the offset to the GSR from a block base address
j===================================================== ==================
MACRO
GSROPP pOinter
add
pointer, 4.
GSR is 4 bytes above base
address
BNDM
j=======================================================================
; MACRO GSRJ3SROFF
; This macro takes a pointer and increments it by two bytes.
; macro for obtaining the offset to the GSR from the J3SR
Use this
;=======================================================================
MACRO GSRBSROPP pointer
add
pointer, 2
; GSR is 2 bytes from BSR
.----------------------------------------------------------------------,----------------------------------------------------------------------; MACRO J3SRGSROFF
; This macro takes a pointer and subtracts it by two bytes. Use this
; macro for obtaining the offset to the BSR from the GSR
i=======================================================================
MACRO
BSRGSROPP pointer
sub
pointer, 2
; BSR is 2 bytes below GSR
292126-24
I
3-695
;=======================================================================
; PROCEDURE
CSR_word_byte_writes
; This procedure writes a byte to the 2BF016SA. It also works with a the
2BFOOBSA.
Param fields needed:
params.data: data word to be ~itten
params.write_addr: offset of 28FOl6SA address to write
Output:
BX: CSR, duplicated in both high and low bytes
;=======================================================================
CSR_word_byte_wri tes
proc
near
moy
BDI,params.write_addr
moy
HS: [BDI],lOlOH
Write To Flash command
moy
HS: [BDI],params.data
; Write data to 28F016SA.
WBM_busyl:
moy
test
AX, BS: [BD:I]
AX,SOH
Read CSR
Look at CSR.7.
jz
short WSM_busyl
Loop while CSR.7
; Poll CSR until CSR.7 = 1, indicatingthat WSM is ready.
moy
ax,AX
moY
BSI [BDI] , SOSOH
moy
BS: [BD:I],PPPPH
ret
CSR_word_byte_writes
endp
O.
Return CSR in BX,
Clear Status Registers command
Reset device to read array mode
Return to calling routine.
292126-25
3-696
I
AP-377
i=======================================================================
PROCEDURE
CSR_block_erase
This procedure erases a 64K byte block on the 28FOI6SA.
It also works with a pair of 28F008SAs.
Param fields needed:
erase_address: offset of base of 28FOl6SA block to erase
Output
AX: CSR, duplicated in both high and low bytes
i===================================================== ==================
CSR_block_erase
proc
near
mov
EDI,params.erase_addr
mov
ES: [EDI] ,2020H
Block Erase command
mov
ES: [EDI] , DODOH
Erase Confirm command
mov
ES: [EDI] , DO DOH
Resume Command per latest
errata update
Note that it is not strictly necessary to write an erase command to
the base of a block; any address within the block will do.
WSJCbusy2:
mov
AX,ES: [EDI]
; Read CSR.
test
AX,80H
; If CSR.7 = 0, test sets ZF.
; System may issue an erase suspend command here to read data from a
; different block
jz
short WSM_busy2
Loop while ZF is set.
; Poll CSR until CSR.7
1, indicating that WSM is ready.
mov
mov
ret
ES:[EDI],5050H
ES: [EDI] ,PPPPH
Clear Status Registers command
Reset device to read array mode
Return to calling routine
CSR is already in AX
292126-26
I
3-697
Ap·377
;=======================================================================
PROCEDURE
CS~erase_suspen~to_read
This procedure suspends an erase operation to do a read.
It also works with a pair of 2BFOOBSAs.
It assumes that erase is underway.
Param fields needed:
params.erase_addr: offset of 2BF016SA block to erase
params.rea~addr: offset of 2BF016SA address to read
Output:
BX: CSR, duplicated in both high and low bytes
CX: data read from the address in params.read_addr
;=======================================================================
eSR_e~ase_susp~to_read
mov
mov
proc near
BDz,params.erase_addr
BSI [BDZ] ,BQBOB
Set up offset of erase address.
Erase Suspend command
WSlLbusy31
mov
test
jz
AX, BS: [BDZ]
AX,80B
sbort WSlLbusy3
Read CSR from any address.
; Poll CSR until CSR.7 =' 1, indicating that WSM is ready.
test
test CSR.6
save result for action later
AX,40B
pusbf
Set up offset of read address.
Read Flash command
mov
Do actual read; put result in
CX.
; Arbitrary number of reads can be done here.
mov
mov
BDz,params.rea~addr
BS: [BDZ] ,PPPPH
eX,BS: [BDZ]
popf
jz
mov
BS:
~EDZ]
,DODOB
no_resume_command:
mov
BS: [BDZ] ,7070B
mov
BX,E,S: [EDZ]
ret
CS~erase_suspe~to_read
get back the result of CSR.6
only resume if operation
suspended
Erase Resume command
Read CSR command
Read CSR from any address.
Return CSR in BX.
Return to calling routine.
endp
292126-27
3-698
I
AP-377
;=======================================================================
PROCEDURE
lock_block
This procedure locks a block on the 28FOI6SA.
Param fields needed:
params.lock_addr: offset of base of 28FOl6SA block to lock
Output:
BX: GSR in high byte and BSR in low byte
AX, DX: trash
;=======================================================================
1ockj)1ock
JIlOV
JIlOV
GSROP'P'
proc
near
Set up offset of address.
Read ESR command
Point ED! to GSR
EDX, parllDls .1ock_addr
BS: [BDX] ,7171H
BDX
CLunavai1ab1e:
IIIOV
test
jnz
AX,BS: [BDX]
AX,08H
short CLunavai1ab1e
; Poll GSR
whi~e
GSR.3
= 1,
indicating queue unavailable.
Disable write protection.
Enable Vpp
set...,pin 56,1
set...,pin 15,1
; Wait for ramp if necessary.
JIlOV
mov
IIIOV
BS: [BDX] ,7777H
BS:[BDX],DODOH
BS: [BDX] ,7171H
Lock Block command
Confirmation command
Read ESR command
AX,BS: [BDX]
AX,80B
short WSJCbusy4
Read GSR
WS!Lbusy&:
mov
test
jz
; Poll GSR while GSR.7
= 0,
indicating WSM_busy.
BR,AR
; Store GSR
; Look at BSR.6 to. see if block successfully locked.
BSRGSROPP'
BDX
Point ED! to BSR from GSR
mov
AX,BS: [BDX]
Read BSR
IIIOV
BL,AL
Store BSR
BS:[BDX],5050H
Clear Status Registers command
IIIOV
BS: [BDX] ,P'PP'PH
Reset device to read array mode
mov
ret
Return to calling routine.
mov
1ockj)1ock
endp
292126-28
I
3-699
AP-377
i=======================-============================= ===================
PROCEDURE
lock_status_upload_to_BSR
This procedure uploads status information into the ESR from non-volatile
status bits.
Param fields needed:
params.lock_addr: offset of 28F016SA device
Output:
BX: GSR in high byte and BSR in low byte
AX, CX, DX:. trash
;============================================~======== ==================
lock_status_upload_to_BSR proc
mov
EDI,params.lock_addr
mov
ES: [EDI] ,7171H
GSROFF EDI
near
Read ESR command.
Point EDI to GSR
Il-unavailablel:
mov
AX,ES: [EDI]
Read GSR
test
AX,OSH
jnz
short Il-unavailablel
; Poll GSR while GSR.3 = 1, indicating queue unavailable.
mov
mov
mov
ES: [EDI] , 9797H
ES: [EDI] ,DODOH
ES: [EDI] ,7171H
WSM_busyS:
mov
AX, ES: [EDI]
test
AX,SOH
jz
short WSM_busyS
; Poll GSR while GSR.7
mov
AX, ES: [EDI]
BH, AL
mov
BSRGSROFF
EDI
AX,ES:[EDI]
mov
mov
BL, AL
mov
ES:[EDI],SOSOH
mov
ES: [EDI] ,FFFFH
ret
lock_status_upload_to_BSR endp
Lock-status Upload command
Confirmation command
Read ESR command
Read GSR
0, indicating WSM_busy
Read GSR
Store in high byte of BX
Point EDI to BSR from GSR
Read BSR
Store BSR
Clear Status Registers command
Reset device to read array mode
Return to calling routine.
292126-29
3-700
I
AP-377
-----------------------------------------------------------------------,----------------------------------------------------------------------PROCEDURE
ESR_word_write
This procedure writes a word to the 28F016SA.
Param fields needed:
params.write_base: offset of base of 28F016SA block to write
params.data: data word to write
params.write_addr: offset of 28F016SA address to write
Output:
BX: GSR in high byte and BSR in low byte
AX, BX, CX, : trash
.----------------------------------------------------------------------,----------------------------------------------------------------------ESR_word_write proc
near
push
SI
mov
EDI,params.write_addr
Set up offset of write address.
ES:[EDI],7l7lH
mov
Read Extended Status Registers
command
mov
EBX, parDS. wri te_base
Get base of block to write
BSROFF EDI
mov
ex, params.word_count
mov
SI, params.data
params.data should be a pointer
to an array of data to write to
the flash array
CLunavailable2:
mov
AX, ES: [EBX]
Read BSR
test
AX,OSH
jne
short CLunavailable2
;Loop while BSR.3 of target address
1, meaning queue full.
mov
movsw
ES: [EOI] , lOlOH
loop
mov
CLunavailable2
EDI,params.write_base
mov
ES:[EOI],7l7lH
BSROFF EDI
Write Byte command
write data and increment ED1,
S1
loop until CX = 0
Set up offset of block base
in case we wrote to the end of
the device, in which case ED1
will now be 2 bytes past the
device
Read ESR command
Point ED1 to BSR
block_busy:
mov
AX,ES: [EDI]
Read BSR
test
AX,OOSOH
jz
short block_busy
; Poll BSR while BSR.7 of target address is 0, meaning block busy
mov
BL,AL
GSRBSROFF
EOI
mov
BH,ES:[EDI]
mov
ES: [EDI] ,SOSOH
mov
ES: [EDI) , OFFFFH
pop
SI
ret
ESR_word_write endp
Store BSR in
Point ED1 to
Read GSR and
Clear Status
Reset device
BL
GSR from BSR
store in BH
Registers command
to read array mode
Return to calling routine.
292126-30
I
3-701
AP·377
;=======================================================================
PROCEDURE
two_byte_write
This routine is used when BYTE# is low, i.e. the 28F016SA
is in byte mode, to emulate a word write.
Param fields needed: (assume existence of byte fields data_high and
data low)
params.write_base: offset of base of 28F016SA block to write
params.data_high: high data byte to write
params.data_Iow: low data byte to write
params.write_addr: offset of 28F016SA address to write
Output:
BX: GSR in high byte and BSR in low byte
AX, CX, OX: trash
i===============================~===================== ==================
near
mov
BDI,parama.write_baae
mov
BS:[BDI),0071H
BSROPP BDI
mov
ex, parama.word_count,
4L-unavailable31
mov
AX, BS I [BDI)
teat
AX,08H
jnz
short 4L-UDavailable3
Set up offset of address.
Read ESR command
Point EDI to BSR
use word_count as byte_count
Read BSR
; LOOp while BSR.3 of target address is 1, meaning queue full.
mov
BSI[BDI),OOPBH
Two-byte write command
; Write low byte of data word
mov
mov
mov
BDI,parama.write_addr
BS: [BDI) ,parama.datlLhigh
RS: [BDI) ,parama.datlLlow
Set up offset of address.
28F016SA automatically loads alternate byte of data register and
initiates write. Now we check for successful completion.
mov
BS: [BDI), 7171H
mov
BDI,parama.write_baae
BSROPP BDI
block_buay21
mov
teat
jz
AX,BS: [BDI)
AX,80H
short block_buay2
Read ESR command
Point EDI to BSR
, Read BSR
; Poll BSR while BSR.7 of target address is 0, meaning block busy.
mov
BR,BSI[BDI)
GSRBSROPP
BDI
mov
BL, BS I [BDI)
mov
BS: [BDI) ,5050R
ret
twoj)yte_write endp
Read BSR
Point ED! to GSR from BSR
Read and store GSR
Clear Status Registers command
Return to calling routine.
292126-31
3-702
I
Ap·377
;=======================================================================
PROCEDURE
ESR-pagebuffer_write
This procedure writes from page buffer to flash.
Param fields needed:
params.write_base: offset of base of 28F016SA block to write
params.pagebuffer_word_count: number of words to write to flash
params.write_addr: offset of 28F016SA address to write
Output:
BX: GSR in high byte and BSR in low byte of BX
AX, CX, DX: trash
.----------------------------------------------------------------------,----------------------------------------------------------------------ESR-pagebuffer_write proc
near
push
mov
SI
SI,params.word_count
Save old S1.
Use S1 to count words.
Address is where in 28F016SA flash array to begin write. The lowest
byte of this must be identical to the start address in the page buffer.
Low byte of byte_count must be 256 or fewer, high must be O.
High byte exists for future Page Buffer expandability.
mov
EDI,params.write_base
Offset of block base address.
mov
ES:[EDI],7171H
; Read ESR command
BSROFF EDI
~unavailable4:
mov
test
jne
; Loop
AX,ES: [EDI]
Read BSR
AX,B
short ~unavailable4
while BSR.3 of target address is 1, meaning queue full.
mov
ES: [EDI] , OCOCH
; Page Buffer Write command
mov
ES:[EDI],SI
; Write count
,
;Only AO valid here; low or high byte loaded depending on AO.
mov
ES: [EDI] , 0
;AO internally complemented; alternate byte loads; write starts.
mov
ES: [EDI] , 7171H
; Read ESR command
block_busy3:
mov
AX,ES: [EDI]
Read BSR
AX,BOH
test
jz
short block_busy3
;Loop while BSR.7 of target address is 0, meaning block busy.
mov
BL,ES: [EDI]
GSRBSROFF
EDI
mov
BH,ES: [EDI]
mov
ES: [EDI] ,SOSOH
mov
ES: [EDI] , OFFFFH
pop
SI
ret
ESR-pagebuffer_write endp
Read BSR
point ED1 to GSR from BSR
Read GSR
Clear Status Registers command
Reset device to read array mode
Retrieve old S1.
Return to calling routine.
292126-32
I
3-703
AP-377
i===================================================== ==================
PROCEDURE
ESR_block_erase
This procedure erases a block on the 28F016SA.
Param fields needed:
params.erase_addr: offset of base of 28F016SA block to erase
Output:
BX: GSR in high byte and BSR in low byte
AX, DX: trash
i===================================================== ==================
BSR_block_erase
proc
near
mov
BDI,params.erase_addr
Set up offset of address.
ES: [BDI] ,7171H
mov
Read ESR command
BSROPP EDI
point EDI to BSR
Cl.-unavailableS:
mov
AX,BS: [BDI]
Read BSR
test
AX,08H
jne
short ~unavailableS
; Loop while BSR.3 of target address is 1, meaning queue full.
mov
mov
mov
BS: [BDI] ,2020H
BS:[BDI],DODOH
BS: [BDI] , DO DOH
mov
BS:[BDI],7171H
;Note that EDI still points to BSR
Block'Erase command
Confirm command
Resume command, per latest
errata update
Read ESR command
bloc~bu8y4:
mov
AX,BS: [BDI]
test
AX,80H
jz
short block-pusy4
; Loop while BSR.7 of target address
mov
BL,AL
GSRBSROPF
EDI
mov
BH,BS: [BDI]
mov
BS:[EDI],SOSOH
BS:[BDI], OPFPPH
mov
ret
BSR-plock_erase
endp
Read BSR
= 0,
i.e. block busy.
Store BSR in BL.
point EDI to GSR from BSR
Read GSR, store in BH
Clear Status Registers command
Reset device to read array mode
Return to calling routine.
292126-33
3-704
I
AP-377
.----------------------------------------------------------------------,-----------------------------------------------------------------------
PROCEDURE
ESR_erase_all_unlocked_blocks
This procedure erases all the unlocked blocks on a 28F016SA.
params.erase_addr: offset of base of device to erase
Output:
CX: GSR in both high byte and low byte
BX: Failure list
AX, DX: trash
j===================================================== ==================
ESR_erase_all_unlocked_blocks proc
near
push
SI
mov
EDI,params.erase_addr
mov
ES:[EDI],7l71H
BSROFF EDI
Q...unavailable6:
mov
AX,ES: [EDI]
test
AX,08H
jnz
short Q...unavailable6
Save old S1.
erase_addr should be set to
the device address
Read ESR command
point ED1 to BSR
Read BSR
; Poll BSR while BSR.3 of target address is 1, meaning queue full.
mav
ES: [EDI] ,A7A7H
mav
ES: [EDI] , DODOH
mov
ES: [EDI] ,7171H
GSRBSROFF EDI
WSM_busy6:
mav
test
jz
AX,ES: [EDI]
AX,80H
short WSM_busy6
Full-chip Erase command
Confirm command
Read ESR command
Point ED1 to GSR from BSR
Read GSR
; loop until GSR.7 indicates WSM is ready
mov
test
jz
AX,ES: [EDI]
AX,20H
short operation_successful
; Read GSR for operation success
; I f GSR.5 = 1, meaning that the operation was unsuccessful,
; go through blocks, looking for the ones which didn't erase.
xor
SI,SI
Clear S1.
EBX, EBX
Clear EBX for failure list
xor
use EDX as mask to set failures
mav
EDX, 1
EDI, params.erase_addr
start at the beginning of the
mav
device
mav
ex, 32
32 blocks in 28F016SA
BSRGSROFF
point ED1 to BSR from GSR
EDI
look_for_bad_erase:
; Looking at each BSR.3 for operation success.
AX,ES: [EDI]
; Read BSR
mav
test
j z
AX,08H
short ok_erased
record number of bad block here
or
EBX, EDX
EDX
292126-34
I
3-705
Ap·377
add
BDJ:, 10000H
loop
loo~for~ad_erase
Increment EDI to next block
operatio~successfu1:
IIIOV
oSROJ'J'
mov
mov
mov
pop
BDJ:, paraDIs. erase_address
BDJ:
BX, BS: [BDJ:]
BS: [BDJ:] ,5050H
BS: [BDJ:], OJ'J'J'J'H
SJ:
ret
reset EDI to device address
point EDI to GSR
Clear Status Registers command
Reset device to read array mode
(l
Return to calling routine.
BS__erase_a11_un1ocke~b1ocks endp
292126-35
3·706
I
AP·377
.----------------------------------------------------------------------,----------------------------------------------------------------------PROCEDURE
ESR_suspend_to_read_array
This procedure suspends an erase on the 28F016SA.
Param fields needed:
params.erase_addr: offset of base of erasing 28F016SA block
params.read_addr: offset of 28F016SA address to read
Output:
BX: GSR in high byte and BSR in low byte (of erase block)
ex: data read from flash
AX, DX: trash
.----------------------------------------------------------------------,-----------------------------------------------------------------------
ESR_suspend_to_read_array proc
near
mov
EDI,params.erase_addr
BSROP'P' EDI
mov
ES: [EDI] ,7171H
block_busyS:
mov
test
jz
AX,ES: [EDI]
point EDI to BSR
Read ESR command
Read BSR
AX, SOH
block_busyS
; Loop if BSR.7 of target address is 0, meaning block busy.
mov
ES:[EDI],OBOBOH
GSRBSROFF EDI
WSM_busy7:
mov
test
jz
AX,ES: [EDI]
Operation Suspend command
Point EDI to GSR from BSR
Read GSR
AX, SOH
short WSM_busy7
; Poll GSR until GSR.7 indicates WSM is ready.
test
pushf
mov
mov
mov
AX,40H
EDI,params.read_addr
ES: [EDI] , P'P'P'P'H
eX,ES: [EDI]
store result for later
Set up offset of read address.
Write Read Flash Array command
Read the data
mov
popf
jz
EDI,params.erase_addr
Set up offset of erase address.
short nothing_suspended
; If GSR.6 indicates an operation was suspended on this device,
; then resume the operation.
mov
ES:[EDI],ODODOH
Resume command
nothing_suspended:
mov
BH,AH
sub
EDI, 2
mov
BL,ES: [EDI]
mov
ES:[EDI],SOSOH
mov
ES:[EDI],OFP'FP'H
ret
ESR_suspend_to_read_array endp
Store GSR in BH.
Move EDI down to read BSR.
Read BSR and store in BL
Clear Status Registers command
Reset device to read array mode
Return to calling routine.
292126-36
I
3-707
AP-377
;=======================================================================
PROCEDURE
ESR_automatic_erase_suspend_to_write
This procedure writes to one block while another is erasing.
Param fields needed:
params.data: data word to write to 28F016SA
params.erase_addr: offset of 28F016SA address to erase
params.write_addr: offset of 28F016SA address to write
Output:
BX: GSR in high byte and BSR in low byte
AX, DX: trash
i'===================================================== ==================
ESR_automatic_erase_suspend_to_write proc
near
moy
EDI,params.erase~addr
Set up offset of address.
moY
ES: [EDI] ,7171H
Read ESR command
point ED! to BSR
BSROll'lI' EDI
~unayallable7
IIIOV
test
jnz
; Loop
moy
moy
moy
moy
moy
:
AX,ES: [EDI]
. Read BSR
AX,OSH
short ~unayailable6
while BSR.3 of target address is 1, meaning queue full.
ES:[BDI],2020H
BS: [BDI] , DO DOH
EDI,params.write_addr
BS:[EDI],4040H
.
ES:[EDI],params.data
Write Erase Block command
Erase Confirm command
Set up offset of address.
Write Word command
Write actual data
Erase will suspend, write will take place, then erase resumes.
Set up offset of address.
Read ESR command
point ED! to BSR
moy
BDI,params.erase_addr
moy
BS: [BDI] ,7171H
BSROll'lI' BDI
blockJ)usy6:
moy
test
jz
; Loop
AX, BS: [BDI]
AX, SOH
short block_busy6
while BSR.7 of target address is 0, meaning block busy.
moy
BH,BS: [BDI]
GSRBSROPlI' EDI
moy
BL,BS:[EDI]
moy
ES: [EDI] ,SOSOH
moy
ES:[EDI],Oll'lI'lI'l"H
ret
BSR_automatic~erase_suspend_to_write
Read BSR
Read and store GSR
Clear Status Registers command
Reset device to read array mode
Return to calling routine.
endp
292126-37
3·708
I
AP-377
;=======================================================================
PROCEDURE
ESR_full_status_check_for_data_write
This procedure performs a full status check of the Extended Status
Register
Param fields needed:
params.write_base: offset of base of device
Output:
CX : 'errorcode
AX, BX: trash
;=======================================================================
ESR_full_status_check_for_data_write proc near
mov
EDI, params.write_base
mov
ES: [EDI], 7171H
Read ESR command
GSROFF EDI
Point EDI to GSR
WSM_busy8:
mov
AX,ES: [EDI]
test
AX,80H
jz
short WSM_busy8
; Poll GSR while GSR.7
BSRGSROFF
EDI
mov
AX,ES: [EDI]
AX, 04H
test
jz
vpp_high
mov
jmp
vpp_high:
test
jz
mov
jmp
ex,
wpb_high:
test
jz
mov
jmp
no_error:
mov
0, indicating WSM busy.
Point EDI to BSR from GSR
BSR.2 = I indicates VPP_LOW
VPP_LOW
cont
AX, 10H
op_not_aborted
ex,
BSR.4 = I indicates operation
was aborted
OPJUJORTED
cont
op_not_aborted:
get""pin WPB
cmp
BX, OOH
je
wpb_high
jmp
Read GSR
get-pin returns output in BX
no error if WPB is low
no_error
AX, 40H
no_error
ex,
BSR.6 indicates BLOCK_LOCKED
BLOCK_LOCKED
cont
ex,
NO_ERROR
cont:
GSRBSROFF
WSMJlusy9:
mov
EDI
Point EDI to GSR from BSR
AX, ES: [EDI]
292126-38
I
3-709
AP-377
test
AX, BOH
jz
W~busy9
; Poll GSR while GSR.7
mov
0, indicating WSM busy.
; Clear Status Registers command
BS: [BDI:l ,SOSOH
ret
BSR_full_status~chec~for_dat __write
endp
292126-39
3-710
I
AP-377
j=======================================================================
PROCEDURE
ESR_full_status_check_for_erase
This procedure performs a full status check of the Extended Status
Register
Param fields needed:
params.write_base: offset of base of device
Output:
CX : errorcode
AX, BX: trash
i===================================================== ==================
ESR_full_status_check_for_erase proc near
mov
ex, NO_ERROR
mov
EDI, params.write_base
mov
ES: [EDI1, 7171H
GSROFF EDI
WSM_busyl0:
mov
AX,ES: [EDIl
test
AX,SOH
jz
short WSM_busyl0
; Poll GSR while GSR.7
Read GSR
0, indicating WSM busy.
BSRGSROFF
EDI
mov
AX,ES: [EDIl
teat
AX, 04H
jz
vpp_high
1IIOV
jmp
vpp_high:
test
jz
mov
jmp
Point ED! to BSR from GSR
BSR.2 = 1 indicates VPP_LOW
ex,
VPP_LOW
cont
AX, 10H
op_not_aborted
ex,
BSR.4 = 1 indicates operation
was aborted
OP_ABORTED
cont
op_not_aborted:
get""pinWPB
amp
BX, OOH
jne
no_error
test
AX, 40H
jz
no_error
mov
jmp
Read ESR command
Point ED! to GSR
ex,
get-pin returns output in BX
BSR.6 and WPB LOW indicates
BLOCK_LOCKED
BLOCK_LOCKED
cont
no_error:
mov
test
jz
test
jz
ES: [EDI1, 7070H
AX, ES: [EDIl
AX, 10H
cont
AX, 20H
cont
1IIOV
ex,
1IIOV
ES: [EDI1, 7171H
1IIOV
Read CSR command
CSR.4 and CSR.S indicate
command sequence error
COMMAND_SE~ERROR
cont:
Read ESR command
292126-40
I
3-711
AP-377
, EDr still points to GSR
WBM_busy11:
mov
test
jz
AX, ES: [EDr]
AX, SOH
short WBM_busy11
Read GSR
; Poll GSR while GSR.7 - 0, indicating WSM busy.
mov
ES:[EDr],SOSOH
ret
ESR_full_status_check_for_erase endp
; Clear Status Registers command
292126-41
3-712
I
AP-377
j=======================================================================
PROCEDURE
single_load_to-pagebuffer'
This procedure loads a single byte or word to a page buffer.
Param fields needed:
params.write_base: offset of base of device
params.data: data to be written to page buffer
params.pagebuffer_start_addr: byte giving pb location to write
Output:
AX: trash
;===========================================~===~===== ==================
single...,pagebuffer_load proc
near
mov
BDr,params.write_base
mov
BS:[BDr],7171H
GSROPP BDr
Set up offset of base address.
Read ESR command
point EDI to GSR
wait_for...,pb:
IIIOV
test
jz
AX,ES: [EDr]
AX,04H
short wait_for...Pb
Read GSR
; Poll GSR until GSR.2 indicates that a
mov
BS: [EDr] , 7474H
p~ge
buffer is available
; Single PB Write command
; Actual write to page buffer.
add
BDr,params.pagebuffer_start_addr
IIIOV
BS: [BDr] ,params.data
Set up offset of
address.
; BP+4 is location in pb to write.
Return to calling routine.
ret
single_loa~to...,pagebuffer
endp
292126-42
I
3-713
AP-377
i=======================================================================
PROCEDURE
sequent ial_load_to-pagebuf fer
This procedure loads the page buffer.
Param fields needed:
params.write_addr: offset of origin of device
params.data_addr: pointer to data to be written to pg buffer
,
params.pagebuffer_word_count: number of words to write to pg
buffer
,
params.pagebuffer_start_addr: starting pb address of data to
write
; Output:
AX, BX, DX: trash
i===================================================== ==================
sequential_load_to-pagebuffer proc
near
Set aside room for counter.
Clear high byte of counter
word.
push
SI
Save old SI.
mov
SI,word_count
;Put
of words to write in SI.
; SP+6 must be 128 or fewer, SP+7 must be o.
; High byte exists for future Page Buffer expandability.
mov
EOI,params.write_addr
Set up offset of device
; address.
mov
ES: [EOI] ,7i7iH
; Read ESR command
; Commands to control entire 28F016SA do not need to be written to any
; particular address.
GSROFF EOI
; point EDI to GSR
sub
mov
SP,2
byte ptr [BP-i],O
*
wait_for-pb2:
mov
test
jz
AX,ES: [EOI]
AX,4
short wait_for-pb2
Read GSR
; Poll GSR until GSR.2 indicates that a page buffer is available.
; Sequential Page Buffer Load
; cmd.
; Loads high or low byte of count register, depending on AO.
mov
ES: [EOI],SI
; Write
; Automatically loads alternate byte of count register.
mov
ES: [EOI],SI
; Write
mov
ES: [EOI] , EOEOH
; Loop through data, writing to page buffer.
byte ptr [BP-i],O
; Load counter.
mov
jmp
not_done:
mov
short compare
add
cwd
mov
Put current val. of counter in
DX.
AL,params.pagebuffer_start_addr ; Get starting address in pb.
Convert it to a word.
AX, OX
Add to get abs. address in pb.
., Convert AX to a double word.
BP+12,OX
Store segment of pb address
mov
mov
mov
add
BP+i0,AX
AX,word ptr [BP-2]
EBX,params.data_addr
EBX,AX
mov
cbw
OX,word ptr [BP-2]
(0) •
Store offset of pb address.
Get current value of counter.
Get address of where data is.
Add value of counter to it.
292126-43
3-714
I
Ap·377
mov
mov
mov
inc
compare:
mov
cmp
jl
ES,word ptr [BX]
EDI,params.write_Dase
ES: [EDI] ,AX
word ptr [BP-2]
AX,word ptr [BP-2]
AX,SI
short not_done
End of loop.
pop
SI
mov
SP,BP
ret
sequential_load_to-pagebuffer endp
Put data at that address on
stack.
Set up offset of address.
Write
Increment counter.
Get current value of counter.
Compare to final value.
Retrieve old SI.
Retrieve old SP.
Return to calling routine.
292126-44
I
3-715
AP·377
i=======================================================================
PROCEDURE
upload_device_information
This procedure uploads the device revision code into the page buffer.
Param fields needed:
params.write_base: offset of 28F016SA device
Output:
DX: Device revision number
AX, CX: trash
;=======================================================================
uploa~device_information
mav
mav
inc
inc
proc
near
BDZ,parama.write_baae
BS: [BDZ] ,7171B
BDZ
BDZ
lLunavailable8 :
mov
AX,BS: [BDZ]
teat
AX, 8
jne
short lLunavailable8
;' Poll GSR while GSR.3
= 1,
'
Read ESR command.
Move EDI up to GSR.
Read GSR
indicating queue unavailable.
WS!Lbuay12 ':
mov
teat
je
;
AX,BS: [BDZ]
AX,80B
short WSM-Puay12
Poll GSR while GSR. 7
mav
mav
mav
Read GSR
0, indicating WSM busy.
BS: [BDZ], 9999B
BS: [BDZ] , DODOB
BS: [BDZ],7171B
Lock-status Upload, command "
Confirmation command
Read ESR command
AX,BS: [BDZ]
AX,80B
short WS!Lbuay13
Read GSR
WSM-Puay13:
mov
teat
jz
;
Poll GSR while GSR.7
0, indicating WSM-pusy
Swap Page Buffer command
Read Page Buffer command
mov
DX,[params.write~aae+3]
Put revision number in DX
Revision number is 3 words above write_base in page buffer space.
; GSR.5 should be checked for operation success before using revision
;, number.
ret
; Return to calling routine.
mav
mav
BS: [BDZ] ,7272B
BS: [BDZ] ,7575H
uploa~device_information
endp
292126-45
3-716
I
AP-377
;=======================================================================
PROCEDURE
RYBY_reconfiguration
This procedure reconfigures the RY/BY# output mode
Param fields needed:
params.write_base: offset of 28F016SA device
params.data: reconfiguration define
Output:
AX : GSR
j===================================================== ==================
RYBY_reconfiguration proc
near
mov
EDI, paraDis. wri te_base
mov
ES: [EDI), 7171H
GSROFF EDI
Q)
Q)
0..
:J
::E
.....:J
.....:Ja.
CSR
.----,
~~
0
t~
-'""'-
-"I1.
-y
N
r
'i
Y
Decoder
...:o!
ilL,i
--1\
;ilij[~t:! T -V
i:
X
Decoder
.. ~
Counter
T
-
i
3/5#
Log;c
BYTE#
~
Jl
-1\
:::!
ILlb -
Data
Page
Buffers
,k)r
-
~rui"
1
;..
a
t~
- •
l'
CEO #
CEI
OE#
WE#
:,~
Icompara,or 1K
Y Gating/Sensing
wp#
RP#
Fj::
··· .
=:
0
~
Address
----------
I/o
·Or-
<;:1: ,i,:i l~.!
Input
I
~::d
~
.....
Buffer
hl
~ R.d~t.r ~ f~:i~l:
L.
~
-V
Uffer
~I
:
III
X
0
L
L
.------
-
'-'---
Input
Buffer
Buffer
w
~-
"'
..
" ,.2
0
:'"
.........
I. ~~.
w
~
"'",
:
~;;;
"',
..
a0
~m
"
\
~~
::
::
~~
RY/ 8Y#
J"I
Program/Erase
vortage Switch
3/5#
:-.
;:.
~:~
t 1- ...........
....- GNO
292127-1
Architectural evolution is indicated with shaded functional blocks.
Figure 1. 28F016SA Block Diagram
3-726
I
AP·378
3.0
ENHANCED WRITE
The write performance of the 2BF016SA is far superior
to that of previous flash components. For a direct write
to flash, the 2BF016SA has a 6 J.Ls average word write
time, a 33% improvement over the 2BFOOBSA. Much
more significant, however are the on·board page buffers
and Auto Erase Suspend capability, which boost write
performance much more by reducing system overhead.
3.1 Page Buffer Writes to Flash
The 2BF016SA incorporates two page buffers of 256·
bytes each. The page buffers can be wrirten with
SRAM·like timings and will program the flash array
without any CPU overhead, providing greatly increased
write efficiencies for both short and long writes.
For example, the 2BFOOBSA writes a byte typically in
9.2 J.Ls/byte, giving a device pair an effective byte write
speed of 4.6 J.Ls since 9.2 J.Ls per byte/2 devices =
4.6 J.Ls per byte/device.
The 2BF016SA, however, can write a word typically in
3.B J.Ls from page buffer to flash memory, giving a de·
vice pair an effective byte write speed of 0.95 J.Ls since
3.B J.Ls per word12 devices = 1.9 J.Ls per word/device
= 0.95 J.Ls per byte/device.
This feature improves system write performance by up
to 4.B times over previous flash memory devices. When
interfacing four (4) 16·Mbit devices in parallel in a
32·bit system, the sustained. write speed approaches
2 MBytes/sec.
MAXIMIZING WRITE PERFORMANCE WITH PAGE BUFFERS
No Page Buffers
a-bit
One Page Buffer Active on Each Device
a-bit
a-bit
a-bit
16-bit bus
Effective Byte
Write Speed
Write Speed
4.6 J.ls
16-bit bus
0.95 J.lS
1 MB/sec
0.22 MB/sec
292127-2
Write Performance Improvement = 4.8X
292127-3
Figure 2. Page Buffer Increases Write Performance
I
3·727
AP-378
For relatively short writes (less than 512 bytes), the
CPU is free after the page buffers are loaded and the
command to write to flash is issued. The 28FOl6SA
will take care of completing the Page Buffer Write to
Flash Operation. This limited form of parallel processing allows the host system to treat flash almost exactly
as it would treat SRAM for short writes. For writes of
less than four (4) bytes, however, it is not efficient to
use the page buffers because the queue can hold three
(3) simple Write commands.
For writes of more than 512 bytes, the two page buffers
can be used to even greater advantage. The system can
fill one buffer, issue the Write command, and then immediately begin to fill the other buffer, continuing to
alternate in this way until the entire write is complete.
This sort of large block writing, known as "interleaved
page mode write", is efficient because the overhead
needed to· set up a write from the buffers to flash is
incurred only once. Also note that the write from the
buffers to flash is itself faster than a write directly from
the system to the flash array.
The load on the CPU is also dramatically reduced using
page mode writes. While a write without the page buffer requires one setup command for every byte or word
written, only 6 commands total need to be issued to set
up the write of 256 bytes to a page buffer and from the
page buffer to flash. While the actual write speed to the
flash array is approximately 35% faster from the page
buffer, there is also the benefit of huge reduction in
processor overhead, with page buffer writes more than
40 times (256 commands vs. 6 commands) less of a
burden on the CPU.
292127-4
292127-5
The two phases in the interleaved page mode write cycle.
Figure 3. Interleaved Page Mode Write
3-728
I
AP·378
3.2 Command Queuing
3.3 Command Prioritization
While the 28F008SA requires an operation to complete
before the next operation could be requested, the
28F0l6SA allows queuing of up to two (2) additional
operations while the memory executes the current operation. As a general rule, the 28FOl6SA has a 3-deep
command queue. This eliminates system overhead
when writing several bytes in a row to the array or
erasing several blocks at the same time. A subset of the
command-set can be queued, while the rest of the commands are executed immediately.
Within the 28F016SA command queue, Write commands have higher priority than Erase commands and
are executed by the WSM first, regardless of the command order. This feature helps insure that valuable
data can be captured as it arrives in real time. The
28F016SA will not, however, put a write to a block
ahead of an erase to the same block.
.
There is, however, an exception to the 3-deep command
queue rule, which has to do with mUltiple Block Erase
commands. if Single Block Erase commands are the
only queued operations, the queue then becomes virtually 32-commands deep. This allows the user to stack
many Block Erase operations very fast before a Single
Block Erase operation completes. Consult the
28FOl6SA User's Manual.
In addition, the 28F016SA prioritizes multiple Block
Erase commands when queued in conjunction with
Write commands. The CUI decodes the Write commands and if those commands affect a block which is in
the queue for erasing, it will prioritize the Block Erase
ahead of other Block Erase operations. This method
allows a complete block modification to occur as fast as
possible.
Command 3
Command 2
Command 1
Command User Interface
"'I
,..
.
I
Priority Resolver
I
Write State Machine
g
J
I
292127-6
Commands are prioritized within the CUI before being sent to the WSM.
Figure 4. Command Prioritization
I
3-729
3.4 Extended Status Registers
3.6 Block Validity and Data Integrity
The 28F016SA includes a Compatible Status Register
(CSR) which is identical to the status register on the
28F008SA, a Global Status Register (GSR), which reflects the overall device status, and 32 Block Status
Registers (BSRs), which are similar to the GSR except
that they contain information specific to their corresponding blocks, i.e., each block has its own BSR. The
value of the BSR is that it allows each block to operate
.
essentially as an independent memory device.
If a particular block becomes corrupted because of an
interrupted Erase operation, due to an Abort command, RP# reset action or the power supply turning
off, both the Block Operation Status (BOS) and Device
Operations Status (DOS) bits will be set 'to "1", indicating an invalid Block. This combination of status bit
setting can be detected when normal operating conditions are restored and after issuing a Status Upload
command, which updates certain status bits in the GSR
and BSRs. If this condition occurs (BOS = DOS = 1),
the user must re-issue a Block Erase command and insure successful erasure of the block by checking the
appropriate GSR and BSR bits.
Since the CPU does not have to control and monitor
the details of writing a word/byte and erasing a block,
it is free to perform higher priority tasks.
3.5 Automatic Erase Suspend to
Write
3.7 Erase All Unlocked Blocks
Write performance is also enhanced by an erase suspend mode which is automatically invoked when a
Write command to a block is issued during the erase of
a different block. Since the erase of a block typically
takes 600 ms to complete, suspending an erase to write
to a different block can dramatically increase write performance.
Automatic Erase Suspend to Write is important to
Microsoft's FlashFiling System (FFS) for flash memory
cards. FFS needs to perform occasional background
erases to maintain efficiency. These erases are much
less noticeable when they can be suspended whenever
the user desires access to the flash card.
2
All 32 blocks of the 28F016SA can be erased using a
single command, the Erase All Unlocked Blocks command. When this command and the Confirm command
are issued, then all of the unlocked blocks will be erased
in sequence. Locked blocks will be skipped and no error
code will be returned. The BSR Block Operation Status
bit can then be checked for each block to determine
which block failed to properly erase and the user can
re-issue single Erase commands to those particular
blocks. This method improves overall system write performance in large flash memory configurations when
extensive data cleanup or card formatting are required.
3
4
.;.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.;.:.:.:.:.:
Write
Erose
;.;.:.:.:.;.:.;.;.;.:.;.:.:.:.;.:.;.;.:.
Erase in Progress
:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.:.
Write Issued
........:.:.:.::.:.:..
Erase Suspends,
Write Takes Place
Erase Completes
292127-7
28F016SA
block erase automatically suspends if write to different block is issued.
Figure 5_ Automatic Erase Suspend to Write
3-730
I
AP-378
4.0
for mobile computing applications as well as some power-sensitive embedded applications which use the device
for infrequently updatable code storage.
LOW POWER CONSUMPTION
4.1 3.3V Operation
For Write/Erase operations such as in Resident Flash
Disk applications, the 28F016SA in 3.3V mode saves
20%/40% energy respectively, versus the 5.0V mode.
See Table 2 for detailed calculations.
For Read operations, the 28F016SA uses about 50%
less energy in the 3.3V configuration than in the 5.0V
configuration, making the 28F016SA an ideal choice
Table 2. 28F016SA Typical' Power Consumption and Energy Comparison
3.3V Operation
f = 4MHz
ICC (mA)
Ipp (mA)
Power(mW)
Icc x 3.3V + Ipp x Vpp
Energy (m.W.sec)
Power x Time
Read Current
15
65,..,A
49.7
0.41 mW. sec/Block
Write Current
8
10
146.4
32.38 mW. sec/Block
Erase Current
6
4
67.8
54.24 mW. sec/Block
ICC (mA)
Ipp(mA)
Power (mW)
. Icc x S.OV + Ipp x Vpp
s.OV Operation
f = 10 MHz
Energy (m.W.sec)
Power x Time
Read Current
50
65,..,A
250
0.82 mW. sec/Block
Write Current
25
7
209
41.09 mW. sec/Block
Erase Current
18
5
150
90 mW. sec/Block
·These numbers are based on preliminary characterization data.
Block Size = 64 KB = 32 KW
Typical word write speeds: 6 pos (5.0V); 6.75 pos (3.3V)
Typical block erase speeds: 600 ms (5.0V); 800 ms (3.3V)
Table 3. 3.3V to 12.0V Converter
Manufacturer
Maxim
Linear Technology
Input (V)
Current
Output
Total
Components
Needed
Est. Cost·
MAX732
1.8 to 5.0
30mA
13
$4.80
1109CS8-12
2.5 to 11.0
30mA
5
$4.00
Part
Number
..
·These cost estImates are based on published pricIng at the tome thIS ApplicatIon Note was written.
NOTE:
This list is intended for example only. and in no way represents all companies that produce 12.0V conversion solutions.
Since this industry develops many new solutions each year, Intel recommends that the designer contact the vendors for
their latest products. Intel will continue to work with vendors to develop optimum solutions. Intel Corporation assumes no
responsibility for circuitry. others than circuitry embodied in Intel products.
At present, there are at least tWo manufacturers of 3.3V to 12.0V converters. Their solutions are described in Table 3. These
solutions are given only for reference and may not be suitable for use in every system. Readers wishing additional information on DC to DC converters are referred to Intel's AP-357, "Power Supply Solutions for Flash Memory".
4.2 Page Buffer Write Operation
4.3 Automatic Power Savings
In addition to providing dramatically faster writes, the
page buffers also save power. While the actual power
saved depends on the size of the write from the page
buffer, savings are typically 35% of the energy it takes
to write. without the page buffer, since page buffer
writes are intrinsically about 35% faster while current
consumption is the same.
Automatic Power Savings (APS) is a low power feature
valid during active mode of operation. The 28F016SA
incorporates "Power Reduction Control" circuitry
which allows the device to put itself into a low current
state when addresses are not switching (in other words,
accessing the same memory location). After data is read
I
3-731
AP-378
from the memory array, the Power Reduction Control
logic controls the device's power consumption by entering APS mode, where the typical Icc current is 1 mA
at 5.0V and 0.8 mA at 3.3V. CPUs with a slowed clock
can take advantage of this feature which is entirely automatic and transparent to the user.
4.4 Deep Power-Down Mode
The deep power-down mode.is activated by the RP#
pin transitioning low, which turps off all device circuitry. The only current consumed is diffusion leakage,
transistor sub-threshold conduction, input leakage, and
output leakage, totaling 1 /LA. However, all register
contents are lost and the current operation terminates
upon entering deep power-down mode.
The deep power-down feature, along with the sleep
command (following section), gives the 28F016SA the
ability to increase power savings dramatically by taking
advantage of the fact that anyone flash device is accessed only occasionally. When the device is not in use,
it can be turned off so that scarce battery power is consumed only as needed. These power-saving functions
can be implemented in ways entirely transparent to the
end-user. The only change the user will notice is that
batteries last much longer with a 28F016SA-based system.
4.5 Sleep
The Sleep command is new with the 28F016SA. Unlike
deep power-down mode, during sleep mode, the status
registers, page buffers, and signature ID codes can still
be read. Once in sleep mode and with applied CMOS
input levels, the power of the device is reduced to deep
power-down current levels. The Sleep command allows
the device to complete any current or pending commands before going into sleep mode. The Device Sleep
Status (DSS) bit in the GSR will indicate that the de-·
vice is in sleep mode. Writing the Read Array command wakes up the device out of sleep mode.
4.6 Standby
With CEo # or CEI # high, the memory will be in
standby mode. This mode turns off much of the device's circuitry and reduces device power consumption.
The outputs are in a high-impedance state independent
3-732
of the state of OE# pin. If the WSM is executing a
command when the device is disabled, the operation is
allowed to continue. During this time the power
consumption remains at the non-standby level until the
operation completes. The output buffers and most of
the input buffers on the chip are disabled during standby mode.
5.0
DENSITY IMPROVEMENT/SPACE
SAVINGS
The 28F0l6SA is twice as dense as the 28FOO8SA, allowing smaller systems, lower weight, and lower power
consumption than ever before---crucial selling points in
the highly competitive mobile PC market. Flash densities are now on a par with DRAM densities, an important step toward the use of flash as non-volatile executable memory (Resident Flash Array), which provides
"instant on" boot capability and instant access to applications and data stored in flash. RFAs also reduce the
amount of necessary system DRAM.
In the removable storage market, the density of the
28F016SA will make conversion to flash the most attractive option when considered along with the properties which set flash apart from other storage media,
such as non"volatility, low power consumption, and
ruggedness. Flash-based data and code storage media
such as PCMCIA memory cards are already on the
shelf, along with PCMCIA-ATA flash drives.
PCMCIA cards in particular will open new distribution
channels for software since cards based on the
28FOl6SA now have sufficient capacity for most large
commercial programs. While cost/megabyte is not yet
competitive with magnetic media, the XIP or "eXecute
In Place" ability of flash cards provides software distributors and end-users with a compelling reason to
consider flash cards.
The density of the 28FO 16SA is also driving entirely
new applications, such as solid-state digital photography and audio recording, which require memory capacities which were not previously economical in flash.
The point to remember is that two (2) megabytes of
70 ns randomly accessible code or data can now be
stored in a rewritable nonvolatile medium of less than
three (3) square centimeters-a 30% improvement over
the 28FOO8SA.
I
AP-378
Two Devices
One Device
80 Pins Total
56 Pins
400 mm 2 Total
280 mm 2 : 30% Area Savings
16 Megabits of Flash Memory - 2 Ways
292127-8
28F016SA density enables smaller flash applications, easier manufacturing and greater reliability.
Figure 6. 28F016SA vs 28F008SA Area Comparison
6.0
FLEXIBLE SYSTEM INTERFACE
6.1 Dual Chip Enables
The 28F016SA implements a dual chip-enable function
with two input pins, CEo# and CEI #, which together
have exactly the same functionality as the regular chipenable pin on the 28FOO8SA. The 28F016SA uses the
logical combination of these two signals to enable or
disable the entire chip. Both CEo # and CEI # must be
active to enable the device .. If either one becomes inactive, the chip will be disabled. This feature allows the
system designer to reduce the number of decoding pins
used in a large array of 16-Mbit devices. For square
arrays, it can be seen that the number of lines needed to
control nXn chips is z'times n. For example, in a square
array of sixteen 28FO l6SAs, only 8 lines are needed
instead of 16 (see Figure 7). For larger memory arrays,
the reduction in decoding signals increases significantly.
I
6.2 Dual 3.3V/S.OV Operation
The portable PC market demands that components be
able to operate at 3.3V. On the other hand, most desktop systems operate at 5.0V. The 28F016SA resolves
this conflict with a dual operating voltage capability. A
3/5# input pin makes it possible to use the 28FOl6SA
in both 3.3V and 5.0V systems interchangeably. The
3/5 # signal pin from the system informs the device
about the supply voltage being used. This information
is used by the 28F016SA to optimize itself for the input
supply voltage. Data written using one supply voltage
will always be valid using the other supply voltage. A
28FOl6SA-based flash memory card is thus able to
transfer data from a 3.3V notebook or handheld PC to
a 5.0V desktop PC as is illustrated by Figure 8.
3-733
AP·378
CSyl
CSy2
CSy3
CSy4
~----_;------~----~~----,-----~~----,-------~--------CSxl
r------+------r-----~------~----~~----,_----~~--------CSx2
r------+------~----_;~----~----~~----,_----~~--------CSx3
r------+------~----_;------,_----~~----,_----~~--------CSx4
292127-9
Dual chip selects reduce the total number of select lines needed.
Figure 7. Dual Chip Selects in a Bank Configuration
3-734
I
AP-378
3.3VSystem
5.0VSystem
292127-10
Figure 8. Dual Voltage Operation Allows Inter-Operability
6.3 User-Selectable x16/x8 Bus Width
While the 28F008SA's interface to the system bus is
strictly x8, the 28FOI6SA's BYTE# pin allows either a
x8 or xl6 bus interface. The system designer now has a
choice between three (3) different configurations in
both 16-Bit and 32-Bit systems, allowing optimization
of the effective block granularity, the space required,
and the minimum memory configuration. See Table 4
for details.
The most efficient and smallest memory configuration
is obtained with the 28FOl6SA in xl6 mode in a 32·bit
system.
6.4 Open Drain RY IBY #
The RY/BY# pin is an open drain output pin to allow
the designer to Wire·OR mUltiple RY/BY# pins in a
large memory array, saving on the number of control
pins which are dedicated to this function.
Note that the smallest block granularity is obtained
with the 28FOl6SA in 16-bit mode in a xl6 system.
I
3-735
Ap·378
Table 4. Configuration Options
System
Bandwidth
Parameter
16-Bit
System
Effective Block size
32-Bit
System
Effective Block Size
28F008SA (x8 only)
Minimum Configuration
Minimum Configuration
28F016SA, x8
28F016SA, x16
i;~;;(;~;~r~:~K~',,;,
128 KB
128 KB
Two Devices: 2 MB
Two Devices: 4 MB
.'
One Device: 2 MB
256 KB
256KB
128 KB
Four Devices: 4 MB
Four Devices: 8 MB
,',twb'b:etrr~s';~fMBl
,,k,,, ,.",Y,.. ~,'
""
Vee
flO Kfl - 100 Kfl
~~~;;;;.;;---;;;;;;t;;;:;;';;--~--i---"
:::tf:gar~Jt::::::
:i :i : :; :. : 2: :': :...: ::8::;..: .:.: : :F..: ,
1::.:.::.:.::..
:1::'..
: ~ .:
:!: :.: .: : ·6:·: : ..: ::A:.
.. ..: : :.:...:'.:' ..: : :..:1: 1.
::::;o.::.:;.:·.:.:.·:::..
:
•
:1.1.:':::;:::'
CPU Interrupt
1:I!I'I I:M:~:~:~ : ;: :j: ij :!jij
,:,:,:,:
28FO 16SA :,:,:,:,
:::::::::::II::::::::::::::::::I::::::::
292127-11
Open drain RY IBY # reduces this array's interrupt lines to just one.
3-736
Figure 9. Open Drain RVIBV #
I
AP-378
Example of Pulsed Mode RY IBY # in an Array of Two Devices
RY/SY#
Device 0 - - - ,
-1
L.._ _ _ _' - -_ _ _ _ _
RY/SY#
Device 1
Array RY /SY#
----------~L-_ _ _ _ _ _ _ _ _ _.....l
I
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___l
292127-12
With devices in Level·Mode operation, this array's output does
not indicate exactly when device 0 has finished its operation.
RY/SY#
Device 0
----------------------,U~ r -------------------------------l ~t
tR
RY /SY#
Device 1
--------------------------------------.U.------------
-l~
Ur-----------,U'----------
Array RY /SY#
292127-13
tR = 250 ns typically
With devices in Pulsed·Mode operation, this array's output does
indicate exactly when Device 0 has finished its operation.
Figure 10. Pulsed Mode RY IBY #
6.5 RY IBY # Configuration Modes
(Level and Pulsed)
While the Level· Mode operation of the Ready/Busy in·
dicator pin continuously reflects the device readiness,
this type of signal will actually hinder the performance
of an array of 28FO 16SAs if the array itself has only
one ready/busy output line. This is because the array
output will indicate busy when anyone of its compo·
nent 28F016SAs is busy, obscuring transitions to ready
by any of the other devices and forcing the CPU to
continuously poll the flash array to find ready devices.
I
A more accurate indication of the array state is ob·
tained when each 28F016SA gives a pulsed output sig·
nal to the host system when it has finished its opera·
tion. The host system can then examine the Global
Status Register of each 28F016SA to find which one
has become ready and issue a Read command, or any
non·queueable command, to the ready device. in this
way, multiple devices can operate in parallel without
the burden of continuous polling to find which ones
have finished their operations.
3·737
intel®
AP-378
The 28FOl6SA incorporates a RY/BY# pin which can
be configured four ways:
• Level Mode (Default)
• Pulse-on-Write Only
• Pulse-on-Erase Only
• Disable
Level mode is the default mode. In this configuration,
the state of the WSM is continuously indicated by the
RY/BY# pin, which is an open drain output pin
pulled high through an external pull-up resistor when
the WSM is ready. This feature allows the user to
OR-tie RY/BY# pins of multiple devices together in
flash memory arrays such as Resident Flash Array or
flash drive applications, saving control logic and simplifying board design.
Pulse-on-write mode will cause RY /BY # to pulse low
at the completion of Page Buffer Write to Flash operations only. This is useful for controlling interleaved
page mode writes.
Pulse-on-erase mode will cause R YIBY # to pulse low
at the completion of Block .Erase operations, including
at the end of each Block Erase during an Erase All
Unlocked Blocks operation.
The RY IBY # pin can also be disabled so that it will
always report a READY condition. Disabling the
RY/BY# pin has no impact on the status registers.
7.0
CODE AND DATA PROTECTION
7.1 Selective Block Locking
While the 28FOO8SA provides data security through
the RP# pin (formerly PWD#) and the intrinsic nonvolatility of flash, it does not have the ability to provide
selective locking of some blocks while leaving others
available for writing and erasing. The 28FOI6SA, however, provides the ability to selectively lock any
64-Kbyte block to protect critical code or data. Each
3-738
block on the 28FOl6SA has an associated non-volatile
lock-bit which determines the lock status of that block.
7.2 Master Write Protect
A WP# (Write Protect) pin activates the block lockbits, preventing any Write or Erase of blocks which
have their lock-bits set. When the WP# pin is asserted
(low) and a block's lock-bit is set, the user is safe from
accidentally damaging or modifying the data in that
block.
7.3 Software Partitioning
The greatest benefit of the 28FO l6SA's block locking
feature is that it is possible for OEMs and software
developers to bundle applications or operating system
code in flash memory cards or in RFAs, providing an
entirely new medium for software distribution. Software distributed in this way is safe from accidental user
overwrites, and yet capable of in-system updates to accommodate new versions. When 28FOl6SA-bundled
code or data needs to be updated, raising WP # high
provides a temporary override of the block locking
mechanism so that locked blocks on the device may be
written to.
The advantage of partitioning a 28FOl6SA-based memory card into locked and unlocked sections is that a
user can keep an application and the files created with
that application together. For example, a spreadsheet
program and all of the spreadsheets a user has created
with that program can be stored on one flash card.
Such an arrangement gives the user a new kind of portability, one which allows him or her to carryall of the
work in his or her pocket with instant access to the
application and files anywhere a compatible PC is available. Hence, the data locking features of the 28FOl6SA
complements its ability to act as executable system
memory, providing the end- user with a solution which
provides portability, safety, convenience, low power
and high speed of access which no other medium can
claim.
I
Ap·378
Memory Cord Bosed on 28FO 16SA
User Data Area
Block-locking feature allows
selective write protection of
code blocks
292127-14
Figure 11. Block Locking and Code/Data Partitioning
7.4 Reset Capability
The 28F016SA provides complete protection of flash
contents through the ResetIPower-down (RP#) pin.
RP# locks the flash array from spurious writes and
places the outputs in a high impedance state. If asserted
during write/erase modes, RP# low aborts the current
operation in progress, cancels all pending WSM commands, flushes the command queue and clears the
status registers.
RP# is used both as a power conservation feature and
as a data protection feature. An example of when RP #
is useful for data protection is during power-up, when
other inputs to the 28F016SA may be in an indeterminate state. Holding RP # low until the power supplies
reach operating levels and all input signals become stable, guarantees maximum protection for the device.
The use of RP # for power conservation is discussed in
Section 4.4. The reader wishing more detail on the use
of the RP# pin is referred to the 28F016SA User's
Manual.
I
8.0
SUMMARY
This application note discusses the key features and
benefits of the revolutionary 16-Mbit device architecture and their impact on system and software designs.
End-user benefits from these enhanced features are
brought to light with respect to the wide range of new
. applications enabled by the 28F016SA chip and
28FOl6SA-based system products.
LIST OF APPENDICES
A: Command Listings
B: References
C: Revision History
3-739
infel®
AP-378
APPENDIX A
28F016SA COMMAND LISTINGS
Command
Device Mode
Codes (Hex)
28F008SACompatible
Commands
28F016SAPerformanceEnhancement
Commands
3-740
OOH
Invalid/Reserved
10H
Word/Byte Write
20H
Single Block Erase
40H
Word/Byte Write
50H
Clear Status Registers
70H
ReadCSR
90H
Read ID Codes
BOH
Erase Suspend
DOH
Confirm/Resume
FFH
Read Flash Array
OCH
Page Buffer Write to Flash
71H
Read GSR or BSRs
72H
Page Buffer Swap
74H
Single Load to Page Buffer
75H
Read Page Buffer
77H
Lock Block
80H
Abort
RY /BY # Reconfigurations
96H
01H
,
RY /BY # Enable to Level Mode
02H
Pulse-On-Write
03H
Pulse-On-Erase
04H
RY /BY # Disable
97H
Upload Status Bits
99H .
Upload Device Information
A7H
Erase All Unlocked Blocks
EOH
Sequential Load to Page Buffer
FOH
Sleep
FBH
Two-Byte Write
I
AP-378
APPENDIX B
REFERENCES
DOCUMENT
ORDER NUMBER
28F016SA 16·Mbit (\·Mbit x 16, 2·Mbit x 8) FlashFile™ Memory Data Sheet ......................... 290489
DD28F016SA 32·Mbit (2·MBit x 16, 4·MBit x 8) FlashFile™ Memory Data Sheet ..................... 290490
28F016SA 16·Mbit FlashFile™ Memory User's ManuaL ........................................... 297372
AP·357 Power Supply Solutions for Flash Memory ................................................ 292092
Ap·359 28F016SA Hardware Interfacing ......................................................... 292094
AP·360 28FOO8SA Software Drivers ............................................................. 292095
Ap·375 Upgrade Considerations from the 28F008SA to the 28F026SA ................................ 292124
AP·377 The 28F016SA Software Drivers ......................................................... 292126
ER·33 ETOX IV Flash Memory Technology ..................................................... 294016
I
3·741
AP-378
APPENDIX C
REVISION HISORY
Number
Description
1.0
Original Version
/
3-742
I
I
infel·
AP-399
APPLICATION
NOTE
Implementing Mobile
Intel486™ SX Microprocessor
PC Designs Using FlashFile™
Components
DON VERNER
SENIOR APPLICATIONS
ENGINEER
CHUCK BROWN
SENIOR APPLICATIONS
ENGINEER
RAJIV PARIKH
TECHNICAL MARKETING
ENGINEER
TONY SHABERMAN
TECHNICAL MARKETING
ENGINEER
November 1994
I
0<." Nombe, 292149-001
3-743
Implementing Mobile Intel486™ SX Microprocessor PC
Designs Using Flashfile™ Components
CONTENTS
PAGE
CONTENTS
PAGE
1.0 INTRODUCTION ................... 3·745
1.1 Why a New Memory
Architecture ...................... 3-745
3.0 HARDWARE ....................... 3-758
1.2 The Flash Memory Alternative ... 3-746
3.2 XIP DOS Implementation ........ 3-759
1.3 The FLEXlogic* PLD
Advantage ........................ 3-747
3.3 XIP GUllmplementation ......... 3-760
3.1 Resident Flash Disk
Implementation ................... 3-758
3.4 RFA Control Logic Overview ..... 3-762
1.4 Summary ............... : ........ 3-748
4.0 SOFTWARE UTILITIES ............ 3-769
2.0 SOFTWARE DESiGN .............. 3-748
4.1 Diagnostic ....................... 3-769
2.1 XIP Operating System ........... 3-748
4.2 Binary Loader ................... 3-769
2.2 DOS in Flash Implementation .... 3-750
2.3 Resident Flash Disk ............. 3-752
5.0 SUMMARY ......................... 3-769
2.3.1 MICROSOFT'S FLASH FILE
SYSTEM ...................... 3-752
6.0 ADDITIONAL PUBLICATIONS ..... 3-770
2.4 Resident Flash Disk and the
ExCATM Standard Architecture .... 3-753
APPENDIX A: MS DOS ROM Image
Description ................. : ....... 3-771
2.4.1 ExCATM STANDARD
ARCHITECTURE SOFTWARE
INTERFACE ................... 3-753
APPENDIX B: ROMDISK CONFI.G.SYS
and AUTOEXEC.BAT ............... 3-772
2.4.2 RFD SOCKET SERVICES .. 3-755
·APPENDIX C: Windows 3.1
CONTENTS.ROM .................... 3-773
2.5 XIP Graphical Users Interface
Overview ......................... 3-756
APPENDIX D: PLD EQUATIONS ...... 3-778
2.6 XIP GUllmplementation ......... 3-757
2.7 Pen Extensions .................. 3-758
3-744
I
AP-399
1.0
INTRODUCTION
As personal computers migrate to platforms that are
easily held with one hand, a revolutionary system architecture is required to meet space and power requirements.
• An architecture that is not bound by what has been
done before with existing memory architecture, but
free to meet the demanding requirements of mobile
end-users.
• An architecture free to adapt and accommodate new
technological advances in software and hardware,
while protecting end-users initial base hardware investment.
Implementing this new system architecture requires
traditional PC storage media such as ROM, DRAM,
floppy disk and hard disk to move aside and make
room for the latest in memory storage, Intel's
FlashFile™ memory (see architecture comparison in
Figure I).
Application
I
Data
Code
File & Code
Manipulation
Execution
Storage
DRAM
DRAM/ROM
DRAM
FLASH
roD/HOD
Desktops
lSi
Portables
The FlashFile memory is also used in card form as
specified by the Personal Computer Memory Card International Association (PCMCIA). Flash memory
cards provide file and program storage similar to an
RFD, but add the feature of removability, increasing or
adding to ease-of-use for the end-user. The PCMCIA
specification addresses both the memory and I/O
card's physical, electrical and mechanical characteristics, w)Iile leaving the host PC implementation relatively free for interpretation. Enhancing the PCMCIA
specification, Intel developed the Exchangeable Card
Architecture (ExCATM standard), which defines the
host PC system card interface. ExCA standard architecture further refines the PCMCIA specification and
provides for card exchangeability and inter-operability
for both memory and I/O cards.
Memory and I/O cards complement this new mobile
architecture by integrating many of the common, but
functionally separate, tasks used by today's mobile professional in either electronic or paper form. Some of
these tasks are schedule keepers, phones, address
books, checkbooks, credit cards, fax, pagers, personal
voice storage, task managers/schedulers, paperless
form reports, scratch pads, and notepads.
FLASH
- Resident Disk
- flash Cord
- flash Drive
292149-1
Figure 1. Architecture Comparison
By combining FlashFile memory with new system architecture, completely new types of computers are now
possible that fit in the palm of your hand and replace or
integrate many of the code or storage functions of older
memory types. Moreover, FlashFile memory enables
hand-held computers to last many hours on just a couple of AA batteries. FlashFile memory can be used for
storing eKecute-!n-£lace (XIP) code in the system's
memory map, while additionally functioning like a disk
for file and program storage. Since this type of design
features FlashFile memory resident on the PC's motherboard and is typically arranged in an array, it is
I
described as a Resident Flash Array (or RFA). To further differentiate the two tasks of an RFA, the file store
task is called a Resident flash Qisk (RFD), while the
XIP task is called Resident flash for KIP (or RFX)
code storage.
1.1 Why a New Memory Architecture?
The ideal hand-held memory system is:
• Power Conscious (prolongs battery life and reduces
heat)
o Dense (stores lots of code and data in a small
amount of space but weighs very little)
o Updateable (allows in-situ code enhancements)
o Fast (lets you read and write data quickly)
• Inexpensive (low cost-per-megabyte)
• Reliable (retains data when exposed to extreme temperature and mechanical shock)
Since the PC's introduction over 10 years ago, designers have grappled with how to construct memory systems that meet the above criteria. Portable computing
makes the system design even tougher with more stringent requirements for low power, low volume and less
3-745
AP-399
weight. The best combination available for portable designs in their infancy was the same as used for the desktop; solid-state memory and magnetic storage, i.e.,
SRAMs, DRAMS plus magnetic hard disks. DRAMs
are dense and inexpensive, yet slower than the processors they serve, and they are volatile. SRAMs, although
fast enough to keep pace with processors, are relegated
to caching schemes (compensating for DRAM's slowness) due to low density and high cost while also being
volatile. Magnetic hard disks, the nonvolatile appendage to DRAM and SRAM, are dense, inexpensive on a
cost-per-megabyte basis and nonvolatile, but are slow,
power hungry, take up a sizable amount of volume and
are susceptible to damage from physical shock.
Mobile computing designs cannot depend on hard
drives as do portable notebook PCs. Volume (4" x 8" x
0.5" or less), power (two AA batteries), and shock constraints preclude using even the 1.3" hard drives available today. Furthermore, vitally important data such as
credit card numbers or transactions, signatures, or
checkbook information demands reliability of the highest order.
1.2 The Flash Memory Alternative
High Density
Intel's ETOXTM III Flash Memory Cell is 30% smaller
than equivalent DRAM cells; therefore it will closely
track DRAM density.' Intel's 28FOl6SV FlashFile
memory can store 16 megabits, or two megabytes, of
data. Flash memory is more scaleable.than DRAM because the flash storage cell is not sensitive to soft error
failure; therefore it can have a more simple cell structure. Thus as density increases and process lithography
continues to shrink, flash memory will pace, and ultimately overtake, the DRAM technology treadmill.
SmartY0ltage Technology
The 28FOl6SV incorporates Intel's SmartVoltage technology, providing Vee operation at both 3.3V and 5.0V
and program and erase capability at Vpp = 12.0V or
5.0V. Operating at Vee = 3.3V, the 28FOl6SV consumes approximately one-third the power consumption
at 5.0V Vee, while 5.0V Vee provides the highest read
performance. Vpp = 5.0V operation eliminates the
need for a separate 12.0V converter, while Vpp =
12.0V maximizes write/erase performance In addition
to the flexible program and erase voltages, the dedicated Vpp gives complete code protection with Vpp ~
VPPLK·
3-746
Internal 3.3V or 5.0V Vee detection automatically configures the device for optimized 3.3V or 5.0V Read/
Write operation.
Updateable
ROMs and EPROMs may offer lower device costs, but
if time to market or servicing the customer or end-user
is important to an OEM" overall system cost must be
factored in. Although ROMs and EPROMs are nonvolatile, changing the code within them is either very
difficult (in the case of EPROMs), or entirely impossible (in the case of ROMs). Whole inventories of ROMs
could be lost in the event of a catastrophic bug, while
an innovative design with FlashFile memory can be updated in the factory or by end-users via networks, OEM
Bulletin Board Systems, or other memory cards. Updating systems could actually become a second source
of income for OEMs and Independent Software Vendors (ISVs), enhancing the quality of the product while
increasing end-user satisfaction.
Power Conscious
Intel's FlashFile memory provides a deep power-down
mode, reducing power consumption to typically less
than 0.2 fLA. Typical read current is only 20 rnA, while
typical standby current (flash memory not being accessed with CE# high) is only 30 fLA. Additionally,
FlashFile architecture devices operating at 3.3 Vee are
available for state-of-the-art low-power consumption
designs.
Fast
Don't be misled by technology-to-technology speed
comparisons. Architecting a system around FlashFile
memory bypasses the code/data bottleneck created by
connecting slow mechanical serial memory (such as
disks) to a high-performance, parallel-bussed processor
system. For example, data seek time for a 1.8" magnetic hard disk is 20 ms, plus an 8 ms average rotational
delay, while flash memory access time is less than 0.1
ms. At the chip level, read speeds for FlashFile memory
are about 85· ns. Therefore, either direct execution of
code from flash memory or downloading to system
RAM will dramatically enhance overall system performance.
Nonvolatile
Unlike DRAM or SRAM, FlashFile memory requires
no battery back-up. Further, Intel's flash devices retain
data typically for over 100 years, well beyond the useful
lifetime of even the most advanced computer.
I
AP-399
Rugged and Reliable
High Density and Flexibility
On average, today's hard-disk drives can withstand up
to 10 Gs of operating shock. Intel's FlashFile memory
can withstand as much as 1000 Gs. FlashFile components can operate beyond 70·C while magnetic drives
are limited to 55·C. Intel's FlashFile memory can be
cycled at least 100,000 times per block or segment.
Even beyond that cycle .level, FlashFile architecture
does not fail or lock up like EEPROM devices, it just
tends to take longer to erase blocks and program bytes
than the times specified in the data sheet. By employing
wear-leveling techniques, a IO-KB file written every 5
minutes, 24-hours a day to a 20-MB flash array takes
1.2 million hours, or 136 years, before reaching the
10,000 cycle level.
The EPX7S0 offers SO macro cells of logic grouped into
eight Configurable Function Blocks (CFBs). Each CFB
can be independently configured as a 24VIO-type PLD
or as a l2S-deep x 10-bit-wide bank of SRAM.
1.3 The FLEXlogic Advantage
The mobile processor market lacks the legacy that exists in the other markets. As a result, standard chipsets
are not available to help design products for the mobile
market. This situation makes the job of mobile system
designs more difficult than it might otherwise be. Many
of the same subsystems need to be designed for mobile
systems as for other markets, but no off-the-shelf components are available.
Altera's EPX7S0 FLEXlogic PLD allows the systems
designer to quickly implement and test new mobile designs. Since the EPX7S0 is a programmable device, the
design described in this application note provides a
standard building block for mobile systems that allows
customization for different memory subsystems, processor variations and applications. The RFA memory
controller requires only about 65% of the macrocells in
the EPX7S0, thus allowing additional logic functions to
be integrated with no additional space requirement.
The EPX7S0 also satisfies the needs of mobile systems
by providing:
When configured as a 24VlO logic, an identity compare
of up to 12 bits can be performed in parallel to the SOP
logic for each CFB. Each macrocell can implement registered or combinatorial logic with a variety of clocking
and control options, providing the system's designer
with greater flexibility.
In-Circuit Reconfigurable and Programmable
Although some simple PLDs offer re-programmability,
changing the logic design in-circuit is either very difficult or entirely impossible. In contrast, the EPX780
offers in-circuit reconfiguration through an industry
standard IEEE 1149.1 JTAG interface. This capability
can significantly reduce the time required for proto-typing new designs.
Instead of carrying inventory of pre-programmed
FPGAs, and incurring the risk that a device with the
incorrect pattern will be inserted in a given location,
blank FLEXlogic devices can be assembled in the design. Then it can be configured or programmed in-circuit ..
Low Power, Mixed-Voltage
The. FLEXlogic PLDs provide reduced power consumption compared with simple PLDs or other FPGA
devices. Typical operating current is only 1.5 mAl
MHz, while standby current for the EPX7S0Z is I mAo
Additionally, the outputs of the EPX7S0 can be operated at 5.0V levels or 3.3V levels. Inputs responds to 2.0V
as a logic high, regardless of the output swing. This
allows the EPX7S0 to be used in state-of-the-art 3.3V
designs or mixed voltage environments commonly
found today.
High Performance & Deterministic Timing
High 1/0
The EPX7S0 offers a fast, deterministic 10 ns tpD from
any input or I/O to any 1/0. It can be operated in-system at speeds of up to SO MHz. Unlike other field programmable gate array architectures, the FLEXlogic
family offers very deterministic timing and may reduce
the need for extensive design, simulation and timing
analysis.
I
To meet the high I/O demands of a 32-bit system, the
132-pin PQFP EPX780 offers 80 II0s and 22 dedicated
inputs for a total of 102 I/0s. This satisfies the 1/0
demands of an RFA controller, and allows support for
additional logic requirements.
3-747
Ap·399
1.4 Summary
2.0
Many applications benefit from ROMed or XIP versions of code, particularly hand-held personal computers, vertical application pen-based clipboards, and industrial control and data accumulation equipment.
These applications pose system design. constraints requiring small form factor, low-power consumption, and
rugged construction due to active mobile users or harsh
environments. Exposure to shock, vibration, or temperature extremes is common, precluding the use of rotating media. Flash memory provides an excellent code
storage choice for such system designs featuring thin
TSOP packaging, low (deep power-down mode) or zero
(capability to shut off power without losing data) power
consumption, 1000 G. shock resistance and extended
temperature products. Additionally flash memory provides remote or end-user update capability, allowing
OEM's to service their products more efficiently and
add new software features and applications after the
sale.
Software design is considered first for solid-state designs because the software functionality desired affects
in large part how the hardware design is implemented.
Many software products exist for solid-state systems:
• DOS 'operating systems from Microsoft, Novell's
Palm DOS and Datalight's ROM-DOS
• A Graphical User Interface (GUI) operating system
in Windows 3.1 ROM version
• Application software from Microsoft such as Word,
Excel and MS-Works and Lotus 1-2-3 Version 2.2.
The features of Intel's FlashFile memory and Altera's
FLEXlogic PLDs truly enable new, compact and portable system architectures. This application note discusses implementing an Inte1486TM SX CPU mobile
design using the following components: Intel's boot
block flash memory; Intel's FlashFile components
(28FOI6SV) for extended memory eXecute-In-Place
(XIP) code store, disk-like functionality for file and
program storage, and BIOS code storage; and Altera's
FLEXlogic PLD (EPX780) as a memory controller.
Related Publications
The following data books and reference manuals provide valuable information for developing an RFA-based
design:
• Intel 28F016SV 16-Mbit (1 Mbit x 16, 2 Mbit x 8)
FlashFile™ Memory Data Sheet, order number
290528
• Intel 28F016SA 16-Mbit FlashFile™ User's Manual, order number 297372
• Microsoft MS-DOS· 5.0 ROM Technical Specification and OEM Adaptation Kit (OAK)
• Microsoft Flash Filing System OAK
• Microsoft Windows· 3.1 ROM Technical Specification and OAK
For additional information on flash memory and power
supply solutions, see section. 6.0.
3-748
SOFTWARE DESIGN
Because no standardization exists, implementation differs from package to package or vendor to vendor.
Therefore, this application note describes a system using MS-DOS 5.0 ROM Version, MS Flash File System,
Windows 3.'1 ROM Version plus Pen extensions. All
are readily available applications today and offer the
highest inter-compatibility. However, the hardware and
software design concepts presented here work just as
well with Novell's (formally DRI) Palm DOS.
2.1 XIP Operating System
The first decision one must make for a solid-state software design is the operating system. Many alternatives
exist for small hand-held computer systems. Any solution depends on what requirements are placed on desktop compatibility, software compatibility, and ease of
developing applications. In the pen-based market, DOS
compatibility is not necessarily a requirement. This is
evident by the multiple emerging entries of pen-based
GUIs. However, data transfer using a medium such as
memory cards between desktop systems and hand-held
computers depends on an agreed file format. At least
for now, DOS is still the major operating system of
choice for the largest number of desktop systems.
Therefore, DOS compatibility is still a necessity for
many hand-held computing systems and is incorporated in this design.
To insure compatibility and easy system integration,
MS-DOS 5.0 ROM Version is the easiest choice. With
this version, an XIP DOS implementation can be configured to as small as 64 KB, using just the Runtime
Kernel and a minimized command interpreter. If
CONFIG.SYS and AUTOEXEC.BAT processing is required, an additional 56 KB are required, plus a ROM
DISK large enough to hold AUTOEXEC.BAT,
CONFIG.SYS, and any drivers and files that are referenced by either file.
I
AP-399
Microsoft provided the capability for additional XIP
DOS applications to be added to an MS-DOS XIP implementation by supplying two new DOS functions,
"Find First ROM Program" and "Find Next ROM
Program." This allows DOS-based XIP applications
(such as OEM-specific utilities and applications or
ROMed DOS applications) to easily be added to the
MS-DOS 5.0 ROM build.
Many different memory configurations of MS-DOS
ROM are possible by distributing various software
pieces (Microsoft refers to them as granules) between
different ROM locations below and above the I-MB
address space. Certain restrictions exist on individual
granules requiring them to appear below I MB. The
granules and address location requirements are specified in a table within the MS-DOS ROM 5.0 OAK.
Approximately 43 KB of granules must be located below the first 1 MB of address space. Other granules can
be located either below or above I MB. The total size of
all granules in this design is approximately 128 KB.
How MS-DOS ROM Boots Up
For system startup and booting DOS without a disk,
MS-DOS 5.0 ROM must intercept the INT 19h call
made by the BIOS. This is accomplished by locating a
granule as an adapter ROM within adapter space
(COOOOh-EFFFFh). This granule contains the ROM
scan identifier "55AAh" which must appear on a 2-KB
boundary and identifies the module as a ROM to the
BIOS during Power On Self-Test (POST), and also
identifies the MS-DOS 5.0 ROM INT 19h interceptor.
When the BIOS POST code identifies the ROM, control is turned over to the ROM for its initialization. At
this time, the MS-DOS 5.0 ROM redirects the INT 19h
vector to the MS-DOS 5.0 ROM code and control returns back to the BIOS POST code. When the BIOS is
completely finished testing and initializing, it issues
INT 19h, and the MS-DOS 5.0 ROM INT 19h handler
gains control. The handler loads the MS-DOS 5.0
ROM bootstrap loader into RAM and passes control to
it. If the bootstrap loader includes the "Multi-Boot"
option, a list of menu boot options are presented to the
user if an OEM~defined key is being pressed. The menu
might look like Table I:
I
Table 1. Multi-Boot Menu
Booting from a Disk
1.
2.
Boot from floppy disk.
Boot from hard disk.
3.
4.
5.
Floppy is default; process start-up files.
Hard drive is default; process start-up files.
Floppy is default; do not process start-up
files.
Hard drive is default; do not process start-up
files.
ROM drive is default; process start-up files.
Booting from ROM:
6.
7.
The menu is activated by pressing the ALT key during
the system memory scan, which is the default provided
in the OAK. Other types of keys may be selected by the
OEM for their specific implementation. Selecting the
options under "Booting from a Disk" will bypass the
ROM system completely. Selecting the options under
"Booting from ROM" will invoke MS-DOS 5.0 ROM
and whatever the option specifies for processing the
startup files, CONFIG.SYS and AUTOEXEC.BAT.
If the Multi-Boot option is not available or is not activated by the user, the MS-DOS 5.0 ROM bootstrap
loader reads a byte from CMOS RAM to determine
boot options. The byte is defined in Table 2.
If the system is to boot from ROM by either selecting
the Multi-Boot option or reading the CMOS byte, the
MS-DOS 5.0 ROM bootstrap loader loads BIOS (note:
not system BIOS, but the BIOS layer of MS-DOS) and
DOS initialization granules into RAM, records the addresses of the resident BIOS and DOS code granules in
the BIOS data area, records boot options (default drive,
CONFIG.SYS and AUTOEXEC.BAT processing) in
the BIOS data area, and passes control to BIOS initialization. Just before the end of BIOS initialization, control is passed to SYSINIT which moves itself and DOS
data and initialization code to high memory where both
SYSINIT and DOS initialization takes place. Next
SYSINIT then reads and processes the CONFIG.SYS
file where installed drivers called in CONFIG.SYS and
additional elements of the DPB chain will be placed in
memory following the existing DOS structures as well
as system buffers allocated. System bootstrap is finished
and the command interpreter is started using the DOS
call to execute ROM utilities. If a full command processor is chosen, the user will now see "C: >" prompt.
3-749
Ap·399
Table 2 CMOS Byte Definitions
Reserved
Default Drive
if ROM Boot
Default Drive
if ROM Boot
ROM
CONFIG.SYS
Processing
Default Boot
7to4
3
2
1
0
Default Boot Bit 0:
0- Boot from ROM
1- Normal disk boot operation (first is drive 00, then drive SO)
ROM Configuration Processing Bit 1:
0- Process CONFIG.SYS and AUTOEXEC.BAT from default drive
1- Do NOT Process CONFIG.SYS or AUTOEXEC.BAT files
Default Drive if ROM Boot Bits 2 & 3
00- First Floppy Drive (Oh)
01- First Hard Drive (SOh)
10- ROM Drive
2.2 DOS in Flash Implementation
For this particular implementation, a full version of
MS-DOS with the full Command processor was chosen. This configuration uses 64 KB of adapter space
(upper memory) at EOOOOh to EFFFFh for MS-DOS
5.0 ROM, and a combination 32-KB XIP binary file
and a 256-KB ROM Disk binary file located in extended memory at FB8000h. See Figure 2. ROM DOS and
ROM Disk Memory Maps. This location is just after
the end of the XIP GUI code block. The XIP Binary
contains the transient portion of COMMAND.COM
and the DOS BIOS initialization and is created during
the build of the MS-DOS 5.0 ROM system, while the
256-KB ROM Drive· contains the necessary files for
bringing up the system and loading the flash file system
drivers which are addressed in the next section.
The EOOOOh segment was chosen because it happens to
be free on the flash BIOS storage chip. Also, later on in
this design we will be adding an RFD, which takes up
16 KB of the DCOOOh segment, and the ExCA standard architecture, which requires 16 KB of adapter
space that we located at D4000h (see Figure 2 for a
3-750
memory map). The ROM disk image location was chosen because there was room available in the extended
XIP portion.. The XIP portion is located at COOOOOh
(12 MB). A copy of the ROM image description file is
included in Appendix B.
The following summarizes the steps taken for building
a ROM version of DOS is taken from the MS-DOS 5.0
ROM OAK. Please refer to the. MS-DOS 5.0 ROM
OAK for specific details.
There are a set of compile options specified in the
MS-DOS 5.0 ROM OAK that need to be defined by the
OEM for their particular implementation and are contained in the OAK file named "VERSION. INC." The
compile options used for this example are listed as follows:
ROMDOS equ TRUE
POWER equ FALSE
ROMDRIVE equ TRUE
CMOS equ TRUE
CONFIGPROC equ TRUE
I
Ap·399
o· l·MB ISA Address Map
FFFFFh
AT BIOS
FOOOOh
~~I
EOOOOh
ROM DOS
]<
1 • 16-MB ISA Address Map
J
FFFFFFh
D8000h
D4000h
C8000h
FCOOOOh
FB8000h
F98000h
ROM Win Stub Window
I
".
I-......-X-IP-C-O-M-M-A-N-D-.C-O-M--I
1--";':;:"';;'::':';;;';;;';;';';;==--1
1-_......R~O;.;;M~W.;.;in~d~ows.;;;;..S;.;t;.;ub;....._-I
PCMCIA Window
28F016SV
x4
Free
XIPGUI
Video BIOS
COOOOh
Video RAM
BOOOOh
2S6-KB ROM Disk
in Flash
;~:>;":
RFDWINDOW
DCOOOh
I
28F200BX-T
COOOOOh
1-----------1
User Flash Disk
Video RAM
800000hl-----------I
AOOOOh
64O-KB User RAM
100000h~---------~
00000
292149-2
Figure 2. ROM DOS 8. ROM Disk Memory Maps
in Appendix B. ROM binary files I and 2 can be com·
bined into one 64·KB binary image as follows:
For this application this means that for:
"ROMDOS" • a ROMDOS build (as opposed to DISK
build simulation) is used.
"POWER" • the MS· DOS APM and power manage·
ment are NOT used.
"ROMDRIVE" • the compiler will use the internal
ROMDRIVE drivers.
copy Ib ROM1.BIN + ROM2.BIN ROMDOSS.BIN
Once the XIP binaries are built, the rest of the ROM
disk needs to be built. First, specify a RAM Drive with·
in your build or development PC using the. MS· DOS
RAMDRIVE.SYS device driver as follows:
device=RAMDRIVE.SYS 256 Ie
"CMOS" • forces MS·DOS S.O ROM to look at the
CMOS byte if the Multi·Boot option is not chosen.
"CONFIGPROC" • normal CONFIG.SYS
AUTOEXEC.BAT processing will be used.
and
Since we are planning to use a ROM DRIVE, MS-DOS
S.O ROM needs to know where the ROM DRIVE ex·
ists. To set the ROM drive base address, the MS-DOS
S.O ROM OAK file ROMRDHI.ASM must be modi·
fied. Edit the file and set the ROMDRIVERBASE_
LO equal to OOOOh and the ROMDRIVERBASE_HI
equal to OFAh, or 64 KB above the base address of the
extended memory XIP module.
Now the MS-DOS ROM binaries are ready for build·
ing. Using the NMK utility, 3 separate binary files are
compiled based on the requirements and addresses
specified in the MS-DOS ROM Image Description file
I
After rebooting your PC, copy the files needed for your
particular application. For an example of CON·
FIG.SYS and AUTOEXEC.BAT files, see Appendix
C. Change the drive label as per the MS-DOS 5.0 OAK
instructions and then use the MS·DOS IMGET utility
to capture the image of the RAM drive into a binary
file. Next, concatenate the ROM3.BIN binary image
created by the NMK with the ROM Disk image cap·
tured from the RAM drive by using the MS· DOS Copy
command as stated earlier:
copy Ib ROM3.BIN + RDlSK.BIN ROMDSK.BIN
This will create a 327·KB binary file with both XIP
DOS code and the ROM Disk code for a single load
into flash memory.
3·751
AP·399
Loading the ROMDOS5.BIN file into the system's
flash BIOS chip requires the use of a BIOS Independent
Software Vendor's (ISV) Flash Update Utility. Most
major BIOS ISVs now offer such utilities. If your particular system design uses a BIOS developed internally,
refer to Intel's AP-34l "Designing an Updateable BIOS
Using Flash Memory" (order number 292077) for more
information on flash BIOS designs and related software. Loading the ROMDISK.BIN file requires developing a DOS-based utility to access flash memory in
"protected mode." Creating this utility is discussed under Section 4.0, Software Utilities, Subsection 4.2, Binary Loader.
2.3 Resident Flash Disk
Once a DOS-based, XIP operating system is in place,
the next area to work on is file storage for flash memory. File storage is possible with either FlashFile components or FlashFile memory-based cards, since they appear the same to file system software. However, the
characteristics of flash memory are very unlike magnetic storage media characteristics.
File Allocation Table (FAT)-based systems rely on the
fact that the operating system has unrestricted Write
capability and/or access to the media, particularly
when updating the FAT for a file creation, update or
deletion. Flash memory on the other hand, does not
necessarily allow write access 100% of the time. When
the flash memory media is completely erased (all
FFh's), writing data to the media can occur at any time
and at any location. Additional data writes within the
same block but at different locations can also occur.
However, once a bit is written to a zero (~b), erasure of
the whole block is required (taking the bits to a Logic 1
condition) before allowing that particular bit to change
back to zero. This asymmetrical characteristic of flash
memory prevents using a straight implementation of
the FAT-based file architecture and requires an alternative file system implementation.
2.3.1 MICROSOFT'S FLASH FILE SYSTEM
To enhance the use of flash memory as a disk, Microsoft created the flash file system. This file system operates as a list of linked lists while keeping track of individual block erasure and file deletions, using minimal
system overhead. File allocation structures use indirectly linked lists, allowing the file system to update files
and data within the files without first requiring the area
where the file is located to be erased and then updated.
During file deletion, a file's header structure is written
to mark the file as deleted, removing the file from the
3-752
file allocation listing. Once a block contains a majority
of deleted files, the file system performs a (background)
clean-up operation and copies good files out to a free
block and erases the block with all the deleted files.
This achieves the goal of user being able to use flash
memory the same as they would use any other mass
storage media without doing anything different.
Three distinct parts comprise the file system organization and implementation:
A File System Redirector, whose job is to intercept
the disk operations passed to MS-DOS by an application and translate them into generic file operations, passing them on to the File System Driver.
- A File System Driver, which accepts generic file
operations passed to it from the File System Redirector, implements the architecture and logic of the
Microsoft flash file system, and passes low-level
commands such as Read, Write, Copy, and Erase to
the device driver.
- A Device Driver, which accepts low-level commands from the File System Driver and interfaces
to the host system hardware implementation.
The File System Redirector performs a task analogous
to a network redirector for LAN (Local Area Network)
systems and appends itself to MS-DOS. Applications
then think they are running from a networked drive.
Some classes of applications and utilities will not operate via this interface. Specifically, those applications
that issue the INT 13h disk BIOS I/O call, INT 25h
DosAbsRead, or INT 26h DosAbsWrite calls will not
work properly with the flash file system, just as they
would not work over a network LAN. The File System
Driver treats the flash media as a collection of large
blocks, all identical in size. Individual block statistics
are kept within a variable length structure at the top of
the block with the remainder of the space available for
directory, file control structures and file data storage.
The File System Driver also determines when de-allocated space (deleted files or directories) within a block
is reclaimed for re-use.
The device driver portion is OEM-modifiable and needs
to be written for the specific hardware used. The only
MS flash file system hardware requirement is a single
window available per socket in a system's adapter space
that addresses all the flash memory to be used. Window
size and base address are left to the system designer to
decide, based on system design requirements.
I
AP-399
Hardware Guidelines:
• Window size of either 8, 16, or 32 KB
• Base address in adapter space (COOOOh to DFFFFh)
For more detailed information on Microsoft's flash file
system, consult the Microsoft flash file system OAK.
2.4 Resident Flash Disk (RFD) and the
ExCA Standard Architecture
Many systems which use an RFA will also want to
incorporate PCMCIA memory and I/O cards. If an
RFD uses the same software architecture used for
PCMCIA cards, less software duplication is present in
systems containing both cards and RFDs. This section
discusses the ExCA standard architecture as it applies
to an RFD and a flash file system.
Most of this section was excerpted from the "ExCA
Standard Specification." The reader is encouraged to
obtain that document for more details not revealed in
this discussion. Also refer to "PCMCIA PC Card Standard, Release 2.1," "PCMCIA Card Services Interface
Specification," and "PCMCIA Socket Services Interface Specification, Release 2.1."
The ExCA standard architecture specifies a standard
host system hardware and software interface for 68-pin,
PCMCIA/JEIDA memory and I/O cards. The "ExCA
Standard Specification" defines the minimum hardware
and software interfaces that card and system designers
can rely on for basic compatibility across PC Cards,
systems, and related software. By defining these interfaces, the ExCA standard architecture makes the
PCMCIA goal of PC Card inter-operability a reality.
I
2.4.1 ExCA STANDARD ARCHITECTURE
SOFTWARE INTERFACE
The primary purpose of the ExCA standard architecture software interface is to explicitly define a minimal
set of socket control and resource access functions upon
which higher-level PC Card Client device drivers can
rely. A PCMCIA implementor may incorporate a
range of functions beyond the basic Memory Card Interface specified in PCMCIA 1.0. For PCMCIA 2.1,
three primary functional extensions to the specification
exist. They are: I/O devices, L-XIP-mapped memory
("L" stands for LIM or Lotus, Intel, Microsoft), and
E-XIP-mapped memory ("E" stands for Extended or
protected mode memory). While basic memory requirements can be met with a single, small memory-mapped
window or even via an I/O approach, both XIP modes
require direct-mapping interface capability, with very
specific boundaries in the L-XIP mode. Without an
ExCA standard architecture-like hardware and software support for direct-mapped memory, XIP-formatted cards cannot function. The ExCA standard architecture socket hardware and software specifications define basic, clear compatibility definitions for PC cards,
software drivers, and host systems.
ExCA standard architecture allows PC Cards and
sockets to be accessed by multiple PCMCIA-aware device drivers, configuration utilities and applications,
with efficient and non-conflicting use of system resources. An architectural diagram of ExCA standard
architecture functionality is shown in Figure 3. The primary components of the software interface are Socket
Services, Card Services, and Memory Technology Drivers (MTDs). Socket Services provide the lowest-level
function set for socket hardware adapter control. Card
Services allocates resources and coordinates PC Cardrelated activities for higher-level client device drivers.
MTDs provide basic program/erase algorithms.
3-753
AP-399
OPERATING SYSTEM
J
FLASH FILE SYSTEM
t
RESOURCE
MANAGEMENT
TABLE
CARD
SERVICES
t.
82365
SOCKET
SERVICES
MEMORY
TECHNOLOGY
DRIVER
t
RFD
SOCKET
SERVICES
t
t
INTEL
ADAPTER
RFDHIW
INTERFACE
ADAPTER
t
t
82365
..-
292149-3
Figure 3. MS FFS and ExCATM Standard Architecture
Adding an RFD Requires only one Software Addition - RFD Socket Services
ExCA Standard Architecture Socket Services
ExCA standard architecture Socket Services is the lowest-level software interface that directly controls PC
Card sockets. Socket Services defines a software interface to manipulate socket adapter hardware in a way
that is independent of hardware implementation. Socket Services defines several abstract resources which can
be manipulated. An Adapter is the hardware that supports connecting one or more 68-pin PCMCIA Sockets
to a host system, or in the case of a resident flash disk,
the hardware that supports a memory interface only. A
Socket is the hardware that supports a single 68-pin
PCMCIA connector. A Window is the hardware that
supports mapping a region of system memory or I/O
address space to a region of card memory or I/O address space. A Card is a PCMCIA card that is inserted
into a socket. Example functions are: configure a socket
for an I/O or memory interface, control socket power
voltages and make callbacks for PC Card insertion and
status changes.
3-754
Socket Service's code size is small, enabling it to fit
within a ROM-BIOS. The Socket Services interface can
be used during POST, and must be ROM-resident to
support booting from a PC Card. The interface is accessed via an 8086-compatible register-based protocol,
and invoked through software interrupt IAh, with
functions starting at 80h. This interrupt is shared with
the real-time CMOS Clock Driver. The Socket Services
software interrupt is called with the proper settings in
the host processor's registers. The functions returns
status via the Carry flag and registers specific to the
function invoked.
Multiple hardware socket adapter interfaces can be
supported by chaining multiple Socket Services handlers. This includes providing Socket Services support
for motherboard-resident flash memory arrays by treating the control circuitry and memory array as if it were
a PC Card single socket/card combination.
I
AP-399
ExCA Standard Architecture Card Services
Card Services is the interface used to manipulate ExCA
standard architecture-related system resources. Card
Services is sub-divided ihto five functional categories:
Client. Services, Resource Management, Client Utilities,
Bulk Memory Services, and Advanced Client Services.
Client Services provide for client initialization and the
callback registration of clients. Resource Management
provides basic access to available system resources,
combining knowledge of the current status of system
resources with the underlying Socket Services adapter
control functions. Client Utilities perform common
tasks required by clients so that functions, such as CIS
(Card Information Structure) tuple access, do not need
to be duplicated in each of the client device drivers.
Bulk Memory Services provide read, write, copy, and
erase memory functions for use by file systems or other
generic memory clients that need to be isolated from
memory hardware details. Advanced Client Services
provide specific functions for clients with special needs.
Card Services provide a packet-based request interface
(i.e., uses a block of RAM for passing inputs and outputs between the caller and the interface) which provides a standard protocol for PC Card client device
drivers to access cards and their required system resources. It provides separate registration and callbacks
for card insertion and card status change event notifications, allowing associated client device -drivers to take
the appropriate actions. For file system Read, Write,
Erase and Copy operations, a special interface is providediQr Memory Technology Drivers (MTDs) which
can handle the details of different memory technologies.
Resource Management provides a protocol for sharing
resources within an environment, where previously the
end-user was responsible for resolving resource conflicts. Resource Management resolves resource contentions without end-user interaction.
Advanced Client Services contains a RetumSSEntry
function which is essentially a direct bypass to Socket
Services. Card Services require Socket Services to manipulate PC Cards and socket hardware. ExCA standard architecture client drivers should typically interact directly with Card Services and not Socket Services.
I
Card Services is typically implemented as a device driver. Card Services provides function number AFh in the
Socket Services interrupt IAh interface for real-mode
operation. During initialization, Card Services determines the state of the host environment. This includes
determining available system memory, available I/O
ports, IRQ assignments, installed PC Cards and socket
state. How this is performed is implementation-specific.
Memory Technology Driver
\
\
The PCMCIA standard supports many types of memory devices used in PC cards. While all PC memory
cards can be read from, writing or erasing memory
cards may require special programming algorithms.
Card Services hides these details of writing or erasing
various memory cards from Client Device drivers, like
Microsoft's Flash File System, by using a Memory
Technology Driver (MTD). Each MTD contains the
specific algorithms required by the memory card manufacturer for programming or erasing their cards. Implementation of MTD support in Card Services is recommended. It is not required for ExCA standard architecture compliance at this time.
2.4.2 RFD SOCKET SERVICES
RFD "Socket Services" functions similar to ExCA
standard architecture Socket Services in that the software interface to manipulate socket adapter hardware
is preserved, but an RFD Socket Services does not control any sockets or cards or respond to card removal
and insertion evepts. RFD Socket Services allows a resident flash disk implementation, through chip-set logic
or additional external logic, to appe.at' to ExCA standard architecture software and the system as another
Adapter using a single Window mechanism, accessing
permanently installed flash memory on a motherboard.
All the rest of ExCA standard architecture Socket Services functions are kept as they relate to this definition.
An example of a non-working RFD Socket Services
function is using it to configure an I/O card. If requested to complete such an operation, RFA Socket Services
will respond with "Function not supported."
For more information on the specific hardware design
used for a Resident Flash Disk, refer to Section 3.0.
3-755
AP-399
2.5 XIP Graphical Users Interface
(GUI) Overview
Many GUIs exist today, but not all are configured to
run in a minimized XIP mode for portables. Some designs may implement a simple DOS-based pen interface
on top of an XIP DOS, like Communications Intelligence Corporation's PenDOS·, and add a single application like a forms recorder. Other designs may not use
XIP DOS at all and the system design revolves around
the XIP GUI requirements alone.
System Requirements:
• 80286 or greater CPU
• I-MB RAM minimum
• 1 MB of XIP memory (flash, EPROM, or ROM)
Since the focus of this application note is personal computers, sub-notebooks and below, Modular Windows
implementations will not be discussed. However, many
of the principles of putting Modular Windows code in
flash memory (memory maps, software tools, flash updateability, etc.) are the same here as the Windows 3.1
ROM example which is discussed later in this section.
Microsoft'leads the rest of the software industry in XIP
GUI development, releasing the Windows 3.1 ROM
Windows 3.1 ROM Version,
Development Kit in September of 1992 and, recently,
the Modular Windows Development Kit in January of
Computers running Windows in ROM or XIP mode
1993. Both are XIP GUI implementations of the Winare very similar to standard pC running disk-based
dows GUI Operating System and are fully modularized
Windows. The only major exception is the presence of a
for OEM configuration. Modularization assists OEMs
large amount of XIP code storage in extended memory
by simplifying the streamlining of an O/S's suitability
from which Windows executes, and a smaller amount
to task by allowing the OEM to choose which functions
of XIP code storage in adapter space. For the rest of
are important and required for a particular design and
this discussion, the Windows XIP code stored in ex- '
which functions can be left out. Benefits to the OEM
tended memory is referred to as HIROM.BIN and the
are:
small amount of Windows XIP code stored in real
- Preserved API for using existing Windows applica- " mode space is referred to as LOROM.BIN.
tions or new application development
- Reduced development time and costs by using stanTwo modes of operation are possible for XIP Windows;
dard Windows application development tools and a
"standard and enhanced," just as on disk-based pcs.
wide choice of Windows software developers
However, each require different system resources for
the XIP Windows version.
- Ease of use for end-user
Modular Windows
Microsoft's Modular Windows Operating System uses a
subset of the Windows 3.1 Operating System and includes ,extensions supporting TV-based multimedia
players. Target market is, home entertainment, but
could easily be adapted for machine control on factory
floors. The differences between Modular Windows and
Windows 3.1 ROM are summarized below:
- Reduced support (or the Windows 3.1 application
programming interface (API)
- Reduced support for Windows 3.1 extension libraries
- New user-interface controls (instead of pull-down
menus)
- New support for hand-control input devices
Software Requirements:
• MS-DOS 5.0 in XIP form
3-756
For standard mode, Windows executes fully in ROM,
leaving almost all the system RAM available for user
programs.. This means that all Windows "core code"
including DOSX.EXE, USER.EXE, GDI, the Windows kernel and all drivers run from XIPstorage
space. Also, all shell programs, applets, fonts and other
Windows resources are stored in and run from XIP
storage space without being loaded into RAM.
Enhanced mode Windows must execute partially from
RAM. enhanced mode components such as
WIN386.EXE and VxDs (virtual device drivers) must be loaded into RAM from some type of disk (a flash
disk, ROM disk, or flash card) for execution, as their
code writes back to their execution location from time
to time and creates errors if loaded into XIP code storage such as flash memory. Components'shared between
modes, specifically USER.EXE, GDI, the kernel and
'drivers, continue to run from their stored locations in
XIP address space.
I
AP-399
Additionally, for either standard or enhanced modes,
'all Windows 3.1 features are supported in XIP Windows. The only limiting factors are the amounts of
available RAM, XIP storage and, in the case of enhanced mode, disk space.
contained in the ROM Table Of Contents (ROMTOC),
also located in LOROM.BIN and contains general information about both XIP images (small and large),
entry point addresses for initialization, and a list of the
'
executables stored in the large XIP image.
Adding Applications
The extended memory XIP image contains the bulk of
the system's code and data segments, EXE headers, and
a prototype Local Descriptor Table (J"DT) which is a
data structure defining the addresses, sizes and types of
segments used by 80286, Inte1386™, or Intel486 processors. For more information on a Windows 3.1 XIPbased system, please refer to the Microsoft Windows
3.1 ROM Development Kit.
The Windows 3.1 ROM }2evelopment .Kit (RDK) can
,add any Windows executable program or application
into the main XIP binary image file HIROM.BlN. The
application must conform to the XIP application requirements specified in the Windows 3.1 Technical
Specification. Microsoft is capable of supplying XIP
versions of Word for Windows, Excel, Microsoft Mail
and Microsoft Works but must be developed between
an OEM and Microsoft on a platform-by-platform basis.
Once the O/S and application functionality is determined and the build script CONTENTS. ROM edited,
the RDK produces two binary images: the large HIROM.BIN extended mode image containing O/S and
application code, ,and the small "real mode" LOROM. BIN image containing the listing of all the XIP
code contained in HIROM.BIN. After both XIP Windows binary files are loaded into flash memory and the
system is up and running, clicking on an application
causes the XIP Windows kernel to search its internal
listing (LOROM.BIN) for an XIP image module first.
If the image is not found within the XIP listing, the
Windows kernel then searches the file paths present at
runtime to try and load the application from its current
file directories. If the program is not found within file
directories, XIP Windows returns "Application missing, me not found." Additions of other extensions to
the XIP image such as multimedia support and Pen
Windows are added in a similar manner.
2.6 XIP GUllmplementation
As mentioned earlier, XIP Windows requires two modules; a small amount of XIP storage in device adapter
space called LOROM.BIN, and a larger amount of XIP
storage called HIROM.BIN in extended memory
space. The LOROM.BIN file contains information
about the modules loaded in the HIROM.BIN XIP (see
Figure 4) image and must be accessed in real mode by
three modules, WIN.COM, RSWAP.EXE, and
WIN386.EXE. Additionally, portions of the DOS extender (DOSX.EXE) must be able to run in real mode
and are therefore located in the LOROM.BIN XIP
image. The information the three modules look for is
I
System Address Map
FCOOOOh
1----------1
XIP COMMAND. COM
FBBOOOh~--------~
F9COOOh
F9BOOOh
F90000h
COOOOOh
100000h 1 - - - - - - - - - - 1
DCOOOh
DBOOOh
OhL-_ _ _ _ _ _ _ _
~
292149-4
Figure 4. 16-Mbyte XIP GUI Memory Map
Software Requirements:
• MS-DOS 5.0 or equivalent in XIP mode
., Software Utility to load both small and large XIP
images into flash memory
• For enhanced mode disk space requirements, MS
Flash File System 2.0 combined with ExCA standard architecture software for a Resident Flash
Disk.
3-757
infel~
AP·399
System Requirements:
• 80286 CPU or greater
• RAM: Minimum of 1 MB for standard mode or
2 MB for enhanced mode
• XIP Store: Minimum of 2 MB for standard mode,
3 + MB for enhanced mode
• Flash Disk Store: Zero for standard mode, 2 MB for
enhanced mode
For this particular design example, enhanced mode
functionality is used to show a full implementation of
Windows. An RFD is used to load WIN386.EXE,
VxDs and all the • .INI and • .GRP files. A complete
listing of the CONTENTS. ROM file used by the Windows ROM Image Builder utility to create an XIP
Windows system is shown in Appendix C. The Windows RDK Enhanced Full sample CONTENTS. ROM
file is used as a template and edited to locate the
LOROM.BIN file at D8000h and is a total of 16 KB.
The HIROM.BIN file is located at COOOOOh and is a
total of 3.7 MB.
2.7 Pen Extensions
Microsoft's Windows for Pen Computing is an extension to Microsoft Windows version 3.1 and has its own
SDK. Pen Windows Extensions do not require any
changes to existing Windows 3.1 applications and a selection of pen recognizer drivers come bundled in the
SDK provide for fast development of a pen-based system. In particular, the Wacom PL-l00V pen tablet and
VGA graphics card can be added to an ISA bus slot for
early debug and pen software development.
AIl the Pen Windows extensions are directly executable
within the HIROM XIP image and can be added to the
CONTENTS. ROM listing.
3.1
Resident Flash Disk
Implementation
As stated in Section 2.3, the MS flash file system requires a hardware mapping window in adapter space
that interfaces directly to flash memory. This window is
similar in function to an EMS mapping window, but
unlike EMS this window is configured via a Sliding
Window Address Register located in the I/O space and
has a fixed base address of DCOOOh and a fixed size of·
16 KB. By setting the correct address in the register,
the full 16-MB ISA memory address space is viewable
in 16-KB increments.
The hardware requirements for the Flash Disk implementation are simply:
1. A Window base address that appears in real mode
memory somewhere in adapter space (COOOOh to
DFFFFh).
2. A Window size that is either 4, 8, 16, or 32 KB.
These two options provide a level of flexibility for an
OEM's system implementation and reduces the memory footprint in adapter space.
The flash disk address mapping in Figure 5 shows the
flash disk and ISA bus address maps together. The implemented sliding window scheme allows 16-KB blocks
of the flash disk address space to be mapped into the
real mode area from DCOOOh to DFFFFh for access by
the MS flash file system.
For some ideas on how to implement an extemallogic
flash disk implementation, see Intel Application Note343, "Solutions for High Density Applications Using
Flash Memory," order number 292079. The application
note describes a complete design for an ISA Bus add-in
card. A local bus design can be derived from the ISA
Bus implementation or from design given in the Schematic Overview section.
3.0 HARDWARE
This section describes the general hardware requirements for an RFA design, then discusses a specific implementation using the Intel486 SX, FlashFile Memory
(28FOI6SV) and an EPX780 PLD architecture as an
example.
3-758
I
AP-399
System
Address
FFFFFFh
16-MB System
Address Map
l·MB Real Mode
Address Map
DDS and
Windows
XIP Storage
4MB
COOOOOh
904000h
900000h
64KB
System
Address
FFFFFh
At Standard
BIOS
FOOOOh
User Flash Disk
- - - 4.M!;l - - - - --- - --
~~-
--
EOOOOh
DCOOOh
DBOOOh
D4000h
BOOOOOh
48KB
Free
CBOOOh
32KB
COOOOh
DRAM
64KB
VGA Graphics
64KB
Mono Text
7MB
BOOOOh
AOOOOh
640-KBDRAM
User Space
OOOOOh
100000h
292149-5
Figure 5. Flash Disk Mapping
3.2 XIP .005 Implementation
As stated in Section 2.2, DOS in Flash Implementation,
MS·DOS 5.0 ROM Version is built assuming the
EOOOOh.segment location and also consists of a ROM
Disk located in extended memory at FCOOOOh.
ROM DOS Storage
This design example uses Intel's 2 Mb, 28F200BX·T
boot.block flash memory. This device is organized with
varying sized blocks starting with a 16·KB hardware
locked boot block at the top of the device, followed by
two 8 KB, separately erasable Parameter Blocks, then a
separately erasable 96·KB block followed by a 128 KB
code block. All the blocks except the boot block are
erasable/programmable when Vpp is high. The boot
I
block is unlocked by applying a second 12.0V input (in
addition to Vpp) to the RP# pin, which allows pro·
gramming and erasure within the boot block. The sec·
ond 12.0V input guarantees hardware protection of the
boot block code against unwanted or inadvertent pro·
gramming or erasure. The benefit of using the boot
block architecture is, that in the event something hap·
pens during a BIOS code update, the system can recov·
er using the code within the locked boot block to bring
up the system and initiate a BIOS code recovery from
either the floppy drive, serial port or parallel port.
Using the 2·Mb (256·KB) device enables the design to
use a single memory chip for four, separate code mod·
ules: a standard AT compatibility BIOS (64 KB), MS
DOS 5.0 ROM (64 KB), Video BIOS (32 KB) and
Power Management Code (16·32 KB). However, the
sum of all four modules is greater than 128 KB, and if
3·759
AP-399
mapped straight down from the top of the 1-MB DOS
address space, would cover the BIOS space and all
available adapter space, leaving no room for any additional upper memory space. Additionally, ROM D0S
must be placed within adapter space at boot time so it
can be scanned as an adapter ROM by the BIOS, and
hook the INT 19h system boot call. To accommodate a
2-Mbit BIOS, this design physically places the
28F200BX-T at the top of the 1-MB ISA address map,
and uses a paging mechanism created by using an XOR
gate tied to the highest address bit of the 28F200BX-T.
The other XOR gate input is a general purpose I/O line
(GPIO) named FLIP#.
At system boot time, the FLIP# signal is defaulted to
the Boot recovery mode (logic 0) placing the boot block
at the top of the 1-MB address map shown in Figure 6,
under Boot Recovery Configuration. The Boot recovery code first checks for valid video BIOS code by looking for a Video BIOS checksum. If the Video BIOS is
valid, it is copied or shadowed to DRAM at COOOOh to
C7FFFh. If the Video BIOS is invalid, the Boot recovery code will initiate a Video BIOS update. The same
scenario works for the power management code, it just
gets copied to a different location in memory.
Next, to determine if a valid Basic AT BIOS is present,
the Boot recovery code copies itself into DRAM, sets
the FLIP # bit high placing the device in the Operating
Configuration shown 'in Figure 6 with the Basic AT
BIOS and MS-DOS ROM on top in the EOOOOh to
FFFFFh memory map and the boot block positioned
out of the EOOOOh-FFFFFh memory map. The recovery code then proceeds to check the Basic AT BIOS
and ROM DOS code checksums. If valid, the recovery
code starts the normal AT BIOS boot process and
ROM DOS is scanned in as an adapter ROM during
the Power-On Self Test or POST. If the Basic AT BIOS
code is invalid, the BIOS recovery code indicates a
BIOS update by beeping or some other OEM defined
way. Next the recovery code determines if the ROM
DOS code is valid. If it is not, the BIOS recovery code
erases the whole block and initiates a BIOS plus ROM
DOS update from either the serial port or parallel port
and loads the BIOS code into the rest of the block. If
the ROM DOS code is valid, the recovery code copies it
into DRAM, erases the 128-KB block, copies the ROM
DOS code back in and initiates a BIOS update just as
before.
ROM Disk Storage
As stated earier, the ROM disk portion of MS-DOS 5.0
ROM Version uses some ofthe XIP GUI storage area
consisting ofIntel's 28F016SV FlashFile memory located at FCOOOOh (Figure 2). The ROM Disk portion required is about 256 Kbytes, and consists of CONFIG.SYS and AUTOEXEC.BAT files, and all the
PCMCIA software drivers. For a listing of contents of
CONFIG.SYS and AUTOEXEC.BAT see Appendix
C. The hardware needed to implement this is the same
listed in Section 3.3, XIP GUI Implementation.
3.3 XIP GUI Implementation
As stated eariier, Windows 3.1 ROM Version takes
up about 3.6 MB of extended address space
(HIRaM. BIN) and 16 KB of real mode adapter address space (LOROM.BIN). HIROM.BIN can be located anywhere above 1 MB and should probably be
high enough above the DRAM address space to allow
additional DRAM to be added to the system by the
end-user. Ideally, the system design should be able to
cache the area where the Windows HIRaM XIP code
is located. This allows the system to take advantage of
XIP code locality since XIP code should produce a
very high cache hit ratio. Since the 28F016SV FlashFile
memory is a x16 device, x32 access is accomplished by
pairing two devices for a LOW Word/HIGH Word
configuration. This creates an erasable block size of
128 KB.
The LOROM.BIN file has a couple of implementation
options. One method is to use a spare block out of the
extended memory XIP region. This method requires
external logic to decode the specific adapter space address dedicated to the LOROM function, and generate
a chipselect to the last block of flash memory. Since the
LOROM.BIN file size is only 16 KB and the smallest
erasable block size is 128 KB, 112 KB of the block is
left unused. Given that the HIRaM and LOROM files
are updated together, the HIROM file could feasibly
use the extra space if necessary.
By taking advantage of the boot block's locked block
architecture, a solid-state design can always accomodate a BIOS or ROM DOS code update without fear of
making the system totally inoperable.
3-760
I
Ap·399
Another option for the LOROM file is to use some free
storage space within the 2-Mb boot block flash memory
chip. The file could then be copied to the correct adapter space shadow RAM location at boot time. Copying
the LOROM.BIN file can occur at the same time that
Video BIOS and Power Management code are copied.
This method provides update capability while reducing
external logic requirements. The only hinge factor is
System
Address
OFFFFFH
OFBFFFH
OF9FFFH
OF7FFF~
8·KB Parameter Block
8-KB Parameter Block
32·KB Pwr, Mgmt Code
64·KB Basic AT BIOS
.Q
III
128KB
LOGICALLY
LOCATED
BELOW 1 MB
".b
c:
'0;
:;:
III
64·KB MS·DOS ROM
'"
System
Address
OFFFFFH
-"
u
'0
0
()
III
OPERATING
CONFIGURATION
16·KB Parameter Block
III
"
Either option is possible. The choice is dependent on
determining which is easier, modifying hardware or
modifying a BIOS boot-up process.
BOOT RECOVERY
CONFIGURATION
32 KB Free
u
""
.Q
getting the system's BIOS code to copy the file before
or during POST.
"
eX>
~
32·KB Video BIOS
OEOOOOH
OEOOOOH
'".Qu
64·KB MS·DOS ROM
III
HIDDEN
FROM
1 MBVIEW
16-KB Parameter Block
8·KB Parameter Block
8·KB Parameter Block
c:
-"
u
32 KB Free
'0;
0
iii
:;:
"0
III
'0
"~
u
32·KB Pwr, Mgmt, Code
eX>
III
".b
64·KB Basic AT BIOS
'"
32-KB Video BIOS
1-'
292149-6
Figure 6. Boot Block Mapping
I
3-761
AP-399
•
•
•
•
3.4 RFA Control Logic Overview
This section describes the logic design for the RFA
controller. Timing analysis is also provided to draw
special attention to some of the difficulties and their
resolutions. Lastly, a discussion of possible future enhancements is presented.
25 MHz 3.3V 486 SX CPU
Altera's EPX780-132 PLD
428F016SV-75 1M x 16-bit flash memory devices
32-bit Transceiver
(4 x 8-bit or 2 x 16-bit, tpD < 15 ns)
The signal names used in the diagrams are described in
Table 3
As shown in the block diagram, Figure 7, the EPX780
provides the interface between the CPU and the flash
memory. The following components are utilized in this
sub-system design:
486SX-RFA Sub-System Design
1 I
A2-A23 (ABUSi)
A2-A21 (ABUSc)
28F016SV
AOS#
M11/c#
486SX
CPU
CEO-1#(H,L)
O/C#
A
BEO-3#
4.
.- ~
28F016SV
OE#
EPX780
W/R#
WE#
ROY#
KEN#
----'J
OT/R#
00-09
00-031 (OBUS)
00-Q31
1
28F016SV
.I
TRANSCEIVER
-I
~!~~~~~~~412~r
1- ....
28F016SV
L
r
RYIBY#
00-031
(FLASH OBUS)
MSB
016-031
t
'"''
00-0151
292149-7
Figure 7. RFA Block Diagram
3-762
I
AP-399
Table 3. Signal Name Descriptions
Signal name
Signal Description
ClK
Clock input to the subsystem, assumed 25 MHz
ADS#
Address Strobe from the CPU
W/R#
Write/Read# signal from CPU
M/i/o#
Memory/i/o# signal from CPU
D/C#
Data/Code# signal from CPU
WE#
Write Enable# signal from EPX780 to flash memory
OE#
Output Enable # signal from EPX780 to flash memory
RDY#
Ready# signal from EPX780 to CPU
KEN#
Cache Enable# signal from EPX780 to CPU
DT/R#
Data TransmitiReceive# signal from EPX780 to transceiver
ABUSi
Address Bus, A23-2 from CPU to EPX780
ABUSo
Address Bus, A21-2 from EPX780 to flash memory
BSEl#
Byte Enable.# signals, BEO-3# from CPU to EPX780
CE#
Chip Enable# signals, CEHO-1 # & CElO-1 from EPX780 to flash memory
DBUS
Data Bus, D31-0 from CPU to EPX780 and transceiver
FLASH DBUS
Data Bus, D31-0 from transceiver to flash memory
ADSWREG
Sliding Window Register select
ADS1 ..4
Address Strobe delay flip-flop chain
SWREG
Sliding Window Register
NOTE:
A .. #" after the name means inverted or active low.
Logic Design
Sliding Window Address Register Interface
The logic design (see Figure 8) for the EPX780 RFA
controller was split into the following three subdivisions from a design standpoint:
The necessary address decoding for the actual loading
of the Sliding Window Address Register with the base
address of the window on the data bus is done using a
simple AND function. Similarly, allowing the address
bits to propagate out of the register to the address bus
upon access to the window is done using a 2xl mux for
each bit with the address decode as the select.
• Sliding Window Address Register interface
• ROM Stub Window mapping function
• Chip enable logic for memory devices
I
3-763
AP-399
ROM Stub Window Mapping Function
This function is also implemented using 2xl muxes.
Here, one of the inputs to the mux is tied to the destination address. Since the two muxes are in series, they are
combined into a single set of equations. These equations
are minimized taking into account the constant address
input to the second mux.
Timing diagrams for the resulting design are shown in
Figures 9, 10 and 11 for the register load cycle, a flash
read cycle and a flash write cycle. The register load
cycle requires 2 clocks, the memory read requires 4
clocks while the write cycle requires 4 clocks for command plus 4 for each word written. The acknowledgment for the write from the flash device is in the form
of an interrupt to the CPU via the RY/BY# line.
Chi" Enable Logic
Enhancing the Design
The chip enable logic and other control signals to the
flash devices are first implemented simply from a functional perspective. The timing accuracy for this logic is
derived via a flip-flop chain transferring the ADS #
pulse for three clocks, thus alIowing for the four clock
read cycle. The equations for the KEN # and the
RDY # are generated after determining the timing of
the other signals.
The design is implemented to optimize the power usage
and thus uses the 3.3V Intel486 SX CPU, a low power
CMOS transceiver and the 28FOI6SV-75. For a higher
performance design, a 5.0V Intel486 SX CPU and
28F016SV-65 memory can be used. Similar 5.0V transceivers are also available. The transceivers specified in
the diagram are high speed devices with typical delays
of about 5-6 ns; however, a 15 ns delay is alIowed for in
the design of the interface, so higher performance designs may be utilized. With 5.0V operation it is possible
to eliminate one wait state during the read and write
cycle. However, a complete timing analysis would be
required.
Byte Writes
In the current implementation, BYTE# is tied high,
putting the 28F016SV into x16 mode. In this mode, the
flash devices will only accept word writes. Byte writes
to the flash array requires software to write an [FFh] to
the unused byte in order to prevent the corruption of
data. When verifying the byte write it wiII then be necessary to ignore the unused byte after reading in the
corresponding word.
Timing Analysis
AlI the signals are analyzed for timing accuracy. Since
the flow of information is initiated by the ADS pulse, a
three flip-flop chain is connected to. the ADS line. This
chain-stores the state of the machine. The state is then
used in all the enable equations and in the two signals
that talk to the CPU (KEN# and RDY#). The two
signals, the KEN # and the R Y/BY # require further
attention. The KEN # is generated but only for code
read access to the flash disk or XIP. The RY/BY# is
actually not implemented in the EPX780. It is suggested that the system designer simply tie the RY /BY # to
an interrupt line on the CPU or polI the flash device for
the status of the Write or the Erase operation.
3-764
The EPX780 has 102 I/O and 2 clock pins of which
81 are used by the current design. Also available are
80 macrocelIs, of which 50 are utilized by the RFA
design.
Further enhancements to the design can easily be implemented using the remaining celIs and I/Os in the
EPX780. Possible improvements include making the
window size, as welI as the base address of the window
in the lower 1-MB space user-definable. The ROM
Windows Stub window can also be converted to a more
flexible mapping. The remaining resources on'the PLD
allow the designer to customize the design to the needed requirements.
I
AP-399
ClK
486 Data Bus
486
Vo Address-,'----I
WR----I
486
SWAddress
M#IVo----I
D/C·~---;
EN
ADS1---L/
OESW
486 Data Bus
486 A23-A14 _~_......
o D 8-C
0000 1101 10
DO-D31
EN
TO 486
CEO = EN * (A22# * A23)
CE1 = EN * (A22 * A23)
logic for Enables
Transceiver
CEHx = CEx*(BE3+BE2)
CELx = CEx*(BE1+BEO)
OE = EN * W#/R
WE =Mlilo# * W/R# *(ADS1+ADS2)
A21-A2
DT_R = M#lilo + W/R# +
(ADS1 #*ADS2#* ADS3#)
DO-D31
. KEN = W#/R*D#/C*M/i/o#*ADS2
RDY = W#/R*Mlilo#*ADS3
+ W/R#*M/ilo#*ADS3
+WESW
ADS1=ADS
ADS2=ADS1*(OE+WE)
ADS3=ADS2
ADS#
D16-D31
RY/BY#
DO-D15
TO 486 INT.
D
Q rA.:::DpS:..:,1-t D
DS
Q rA:::;
r:2=---i D
EN
Q
ClK
292149-8
Figure 8_ logic Diagram
The logic for the Sliding Window, the ROM Stub Window and the Chip Enable functions in the EPX780 RFA
controller is shown here along with the flash configuration.
I
3-765
Ap·399
Itn
eLK
1'(Th,
/
/
"
l--!a2O)
=-f
1-(3.20)
ADSI
I
\
I
'--------
I
"
-I
wm.
-om .,
Milici
D/C'
.
~
WE'
.-f
-10
OEI
r
ROY'
lO
~
-10
....
KEN.
DTfR.
ABUSi
i--<3.20}
"
ABUSo
BSElI
~3.20)
-
~lO
~1O
.-f
Ho ....
eE.
'~:-
~ 20}
DeuS
L
FLASHDBUS
AOSWREG
,S
--I
"
.-f
'-10
.~ ,
,
~
L......,6
ADSl
'"'
.,---1
f--
6
ADS2
ADS3
L......j6
SWREG
(
292149-9
Figure 9. Sliding window Register Load Cycle
The signals from: the CPU transition between 3 ns and 20 ns after the clock. There is a 10 ns delay for the logic to
propagate through the EPX780 to prepare for latching the data on D9-0 (DBUS). In the next clock, the ADS # is deasserted by the CPU, and the RDY # is asserted by the EPX780. During the clock that the CPU latches the RDY #
signal, the data is latched by the EPX780. Thus, RDY # is asserted before the EPX780 latches the data and the
operation requires only two clock cycles.
Note: Black areas indicate don't care. Grey areas indicate propagation delay.
3-766
I
AP-399
ISOns I
C\J(
ADS'
~~
"---------
1~(3.20)
-
~
(3.20)
~
I~
~
I~
D/C' 1 . -
~
W/RI
M/l/o#
~
YoI'I
CE#
.610
~
ROY'
r-/IO
r---IIO
I'
(3.20)
~
I
.-110
-110
!...t10
V!JiI1l!llY
..... 10
.-110
--
__
V!JiI1l!llY
---
I
,
-
DT/R.
~(3.20)
'-110
ABUSo
,
~(3.20)
85ELt
·'-110
CEI
--1(3.20)
DBUS
L-!15
FlASH D8US
ADSWREG
~6
ADSI
~6
ADS2
ADsa
SWREG
I
\
I
'--
t<
292149-11
Figure 11. Flash Memory Write Cycle
The write cycle is actually composed of two separate write requests. The first is a "write" command presented on the
data bus while the WE# is asserted and the chip enable is valid. The second bus cycle transfers the actual address
and data to be written. In the write cycle, the ROY # is latched on the risng edge of the fifth clock. The write
completion is signaled by the R Y /BY # output of the flash memory which should be connected to an interrupt line
on the CPU.
3-768
I
AP-399
4.0 SOFTWARE UTILITIES
4.1 Diagnostic
It is highly recommended that system designers develop
simple diagnostic tools to test the hardware at a very
low level (i.e., Write Byte, Write Word, Read Word,
Erase Block). Such a tool proves invaluable when debugging new hardware and software designs and resolving hardware and software conflic~s.
4.2 Binary Loader
The RFA Binary files HIROM.BIN, LOROM.BIN,
and ROM Disk must all be loaded into protected mode
from real mode. This can be accomplished a number of
ways:
1. Use a DOS Extender. This provides a quick method
to create a utility using the tools a DOS Extender
provides. However, licensing may prove to be difficult or expensive.
2. Using· BIOS-based extended memory calls. These
actually worked quite nicely and reliably, but
proved to be slow and doubled the time to erase and
program HIROM.BIN.
3. Use XMS Calls. This method depends on the existence of the MS-DOS file HIMEM.SYS to access
the XMS handler, and was the fastest of all.
For lab testing, our binary loader used a simple file
name plus command line parameters. A system for endusers would need a more elaborate user interface to
guide them through the software update. Some basic
I
software requirements outside of the basic file Read/
Write capabilities and command line parsing for the
flash memory Binary Loader are:
• Incorporate basic flash memory program and erasure commands. These software drivers are available
for both ASM86 and "C" in Intel's Application
Note-360, "28F016SA FlashFile™ Software Drivers," order number 292095. This application note
addresses things like read device identifier, Vpp
ramp time, x8 and x16 parallel programming and
block erasure by providing proven, tested routines
for each.
• Choose a method of protected mode access that
makes ,the most sense for you.
• Allow for specific base addresses to be entered by
the user, while within the program automatically determining what block and the number of blocks to
be erased from the base address and binary file size.
5.0 SUMMARY
This application note discussed a new system architecture based on solid-state software and hardware design
concepts. This new architecture is based on using flash
memory for the following; BIOS + DOS code storage,
a nonvolatile RAM disk or RFD, and as XIP GUI
code storage or RFX. Specific flash memory component and PCMCIA card information is found in their
respective data sheets. Contact your local Intel or distribution sales office for more information or to obtain
assistance in evaluating boot block or FlashFile memory components, as well as Intel's product line of
PCMCIA flash memory cards.
3-769
Ap·399
6.0 ADDITIONAL INFORMATION
Order Number
Document
292092
AP-357 "Power Supply Solutions for Flash Memory"
292094
AP-359, "28F008SA Hardware Interfacing"
292095
AP-360, "28F008SA Software Drivers"
292097.
AP-362, "Implementing Mobile PC Designs Using High Density FlashFile™
Components"
3-770
I
AP-399
APPENDIX A
MS-DOS ROM IMAGE DESCRIPTION
#1111# ##:¥II JW It It.v XNIMN.YJJ II II #111111######1111111111 U#111111 II ~ 111111 11//1111 #/1 11/111# Ii /1# 1/ #1111 ,'/11 1111 #
#
RFA ROM DOS Description File
#
# ROM image description file for 64K of ROM space at
#
#
#
EOOOO-EFFFF and one 256K ROMDISK module at F90000
111111 #N#1111 II 1/ . . 111111 It hI:\i iJ HII ,1 MMil . . #1111 #Ii II II /I UII #Ii II II 1111 # II #lilt 1111# #ilIHI######## N##1/11# NiI
# Actual file sizes created: Three 32K modules
ROM1=Int 19 hook and Resident DOS Code
ROM ISIZE=8000
ROM 1MAX=7FFF
ROM 1TYPE=SEG
ROM 1ADDR=EOOO
ROMICHKSUM=YES
ROMINUMBLOCKS=40
ROM 1FILES=,,\romhead\romboot.bin ,,\dos\resdos, 16
ROM2=COMMAND ROM Hdr Res, BIOS Code Bootstrap loader Resident Command Code
ROM2SIZE=8000
ROM2MAX=7FFF
ROM2TYPE=SEG
ROM2ADDR=E800
ROM2CHKSUM=YES
ROM2NUMBLOCKS=40
ROM2FILES=,,\cmd\command\romhead,bin ,,\bios\resbio, 16 \
,,\romload\romload,sys ,,\cmd\command\rescom, 16 ,,\dos\romdos,sys
ROM3=Command interpreter
ROM3SIZE= 10000
ROM3MAX=FFFF
ROM3TYPE=BASE
ROM3ADDR=F90000
ROM3FILES=,,\cmd\command\command,16 ,,\bios\rombio,sys
292149-12
I
3-771
AP-399
APPENDIX B
ROMDISK CONFIG.SYS AND AUTOEXEC.BAT
AUTOEXEC.BAT
@echooff
prompt$P$G
set path=c:\;d:\rdkIO\build\disk;d:\utils;d:\diags;
c:\doskey
doskey d=dir $1 $2
.
d:\rdkIO\build\disk\smartdrv.exe 1024 1024
set TEMP=d:\
ver Ir
echo "MS-DOS ROM. Card & Flash Disk SS2.0. MS FlashFileSystem 2."
echo "and Windows 3.1 ROM"
'
CONFIG.SYS
. DEVICE=c:\HIMEM.SYS
break=on
buffers=40
files=40
lastdrive=H
DOS=HIGH.UMB
R~·*****************~**************·**************
REM FlashFile Systelll Drivers
Device=C:\rfaslss.sys
Device=C:\ss365s1.exe
Device=C:\cs.exe
Device=C:\csaIloc.exe c:\csalloc.inc
Device=C:\mtddrv .exe
Device=C:\mti2p.exe
Device=C:\ms-flash.sys
Device=C:\cardid.exe
REM·······*······················***···**····*·······
3-772
292149-13
I
AP-399
APPENDIX C
WINDOWS 3.1 CONTENTS. ROM
NOTE: Semi-colons denote a commented-out line which is NOT added to the HIRaM Binary file.
;********************************************
; Windows 3.1 ROM Development Kit (RDK) 1.0
; Sample ROM Description File
; Copyright Microsoft Corporation, 1992
; Enhanced Mode, FuH
; 10/20/92 Removed TT Fonts
ROMS
; Specifies length of ROMs and the linear addresses
; at which they are to appear.
; Name Address Length (max)
; -------------------------------------'::-
LoROM QC8000 004000 ; 16k
HiRaM COOOOO 390000 ; 3.7 MB
TABLES
; Specifies information for tables to reside in ROM.
ROMTOC
100
LoROM
NUMFILENT 14
LDT
1024 HiRaM 256
; WINFLAGS
13
WINFLAGS
15
; SYSDIR
system
ROMVERSION
1000
; ROMTOC entries
; FILES entries
; Local Descriptor Table
; 286 version; Value is in HEX
; 386 version; Value is in HEX
; Windows directory on disk (optional)
;1
=masked ROM, 000 = OEM version
MODULES
Specifies modules to be loaded into ROM.
Format is as foHows:
Module SEG File ROM Flags Comments
292149-14
I
3-773
AP-399
; Kernel --------------------------------------------------------------DOSX.EXE· %ROMFILES%dosx.exe
SEG2
SEG3
; KERNEL.EXE %ROMFILES%krnI286.exe
KERNEL.EXE %ROMFILES%krn1386.exe
LoROM NOEXEHDR
; Std mode MS-DOS extender
HiROM
; DXDGROUP - Copy from ext with INT ISh
; DXPMCODE
HiROM
Hi ROM
; 286 kernel
HiROM
; 386 kernel (ROM version)
; Drivers (Replaceable) ------------------------------------------------SYSTEM.DRV %ROMFILES%system.drv
Hi ROM
KEYBOARD.DRV %ROMFILES%keyboard.drv HiROM
SEG lOCOMP
HiROM
HiROM
HiROM
HiROM
; System
; Keyboard
; Do not remove!
; Display
; 286 VGA
; 386 VGA
; 286 SuperVGA
; 386 SuperVGA
HiROM
MOUSE.DRV %ROMFILES%mouse.drv
SEG 2 RAM COMP NORELOC
; NOMOUSE.DRV %ROMFILES%nomouse.drv HiROM
; Mouse
; Do not remove!
; No mouse
; VGAROM2.DRV %ROMFILES%vgarom2.drv
VGAROM3.DRV %ROMFILES%vgarom3.drv
; SVGAR2.DRV %ROMFILES%svgar2.drv
; SVGAR3.DRV %ROMFILES%svgar3.drv
COMM.DRV
%ROMFILES%comm.drv
SEG 2 RAM COMP NORELOC
SEG 3COMP
;COM,LPT
; Do not remove!
; Do not remove!
HiROM
MMSOUND.DRV %ROMFILES%mmsound.drv HiROM
; Sound
; Core -----------------------------------------------------------------GDI.EXE
%ROMFILES%gdi.exe
USER.EXE
%ROMFILES%user.exe
SEG 3 RAM COMP NORELOC
HiROM
HiROM
; ROM version
; ROM version
; Do not remove!
; Non-Replaceable System DLLs ------------------------------------------SHELL.DLL %ROMFILES%shell.dll
LZEXPAND.DLL %ROMFILES%lzexpand.dll
WIN87EM.DLL %ROMFILES%win87em.dll
HiROM
HiROM
Hi ROM
Shell APIs
Expansion
Math emulator
; Replaceable System DLLs ----------------------------------------------COMMDLG.DLL %ROMFILES%commdlg.dll
OLECLI.DLL %ROMFILES%olecli.dll
OLESVR.DLL %ROMFILES%olesvc.dll
TOOLHELP.DLL %ROMFILES%toolhelp.dll
DDEML.DLL %ROMFILES%ddeml.dll
VER.DLL
%ROMFILES%ver.dll
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
STUB
STUB
STUB
STUB
STUB
STUB
; Common dialogs
; OLE Client
; OLE Server
; Tool Help DLL
;DDE
; Version DLL
; Multimedia Extensions -----------------------------------------------MMSYSTEM.DLL %ROMFILES%mmsystem.dll HiROM STUB
SND.CPL
%RETAIL%snd.cpl
HiROM
HiROM
MPLAYER.EXE %RETAIL%mplayer.exe
HiROM
SOUNDREC.EXE %RETAIL%soundrec.exe
; Multimedia
Sound icon
Media Player
Sound Recorder
292149-15
3-774
I
AP-399
; Advanced Power Management (APM) -------------------------------------; POWER.DRV
%RETAIL%power.drv
HiROM
; APM driver
; Shell Programs ------------------------------------------------------PROGMAN.EXE %RETAIL%progman.exe
WINFlLE.EXE %RETAIL%winfile.exe
TASKMAN.EXE %RETAIL%taskman.exe
WINHELP.EXE %RETAIL %winhelp.exe
WINTUTOR.EXE %RETAIL%wintutor.exe
HiROM
HiROM
HiROM
HiROM
HiROM
; Program Mgr
; File Manager
; Task Manager
; Windows Help
; Tutorial
; Control Panel -------------------------------------------------------DRiVERS.CPL %RETAIL%drivers.cpl
MAIN.CPL
%ROMFlLES%main.cpl
CONTROL.EXE %RETAIL%control.exe
HiROM
HiROM
Hi ROM
; Drivers icon
; Main icons
; Control Panel
; Printing Support ----------------------------------------------------; PRiNTMAN.EXE %RETAIL%printman.exe
; UNIDRV.DLL %ROMFlLES%unidrv.dll
; DMCOLOR.DLL %ROMFlLES%dmcolor.dll
HiROM
HiROM
HiROM
; Print Mgr
; Uni driver
; Uni driver
; System Fonts --------------------------------------------------------VGASYS.FON %RETAIL%vgasys.fon
VGAFlX.FON %RETAIL%vgafix.fon
VGAOEM.FON %RETAIL%vgaoem.fon
HiROM
HiROM
HiROM
; System (VGA)
; Fixed pitch
; OEM
'; Bitmap Fonts --------------------------------------------------------COURE.FON %RETAIL%coure.fon
SERIFE.FON %RETAIL%serife.fon
SMALLE.FON %RETAIL%smalle.fon
SSERIFE.FON %RETAIL%sserife.fon
SYMBOLE.FON %RETAIL%symbole.fon
HiROM
HiROM
HiROM
HiROM
HiROM
; Courier (VGA)
; MS Serif (VGA)
; Small (VGA)
; MS Sans Serif (VGA)
; Symbol (VGA)
; Plotter Fonts ----------------------------.----------------------------MODERN.FON %RETAIL%modern.fon
ROMAN.FON %RETAIL%roman.fon
SCRIPT.FON %RETAIL%script.fon
HiROM
Hi ROM
HiROM
; Modern
; Roman
; Script
; TrueType Fonts ----------------------------------------------------~-ARIAL.FOT %RETAlL%arial.fot
ARlALBD.FOT %RETAIL%arialbd.fot
ARiALBl.FOT %RETAIL%arialbLfot
ARlALI.FOT %RETAIL%ariali.fot
%RETAIL%cour.fot
; COUR.FOT
; COURBD.FOT %RETAIL%courbd.fot
; COURBl.FOT %RETAIL%courbi.fot
; COURl.FOT %RETAlL%courLfot
; SYMBOL.FOT %RETAIL%symbol.fot
; TIMES.FOT %RETAIL%times.fot
; TIMESBD.FOT %RETAIL%timesbd.fot
Hi ROM
HiROM
HiROM
HiROM
HiROM
Hi ROM
HiROM
HiROM
HiROM
HiROM
HiROM
; Arial
; Arial Bold
; Arial Bold Italic
; Ariaiitalic
; Courier New
; Courier New Bold
; Courier New Bold Italic
; Courier New Italic
; Symbol
; Times New Roman
; Times New Roman Bold
292149-16
I
3-775
Ap·399
; TIMESBI.FOT %RETAIL%timesbiJot
; TIMESI.FOT %RETAIL%timesi.fot
WINGDING.FOT %RETAIL%wingdingJot
HiROM
HiROM
HiROM
Times New Roman Bold Italic
Times New Roman Italic
WingDings
; MS-DOS App Support --------------------------------------------------VGA.3GR
%RETAIL%vga.3gr
WINOLDAP.MOD %RETAIL%winoldap.mod
SEG 2 RAM COMP NORELOC
WINOA386.MOD %RETAIL%winoa386.mod
SEG 1 RAM COMP NORELOC
SEG 2 RAM COMP NORELOC
SEG 5 RAM COMP NORELOC
HiROM
HiROM
DOSAPP.FON %RETAIL%dosappJon
EGA80WOA.FON %RETAIL%ega80woaJon
EGA40WOA.FON %RETAIL%ega40woa.fon
CGA80WOA.FON %RETAIL%ega80woa.fon
CGA40WOA.FON %RETAIL%cga40woa.fon
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
; Enh mode grabber
; Std mode MS-DOS app support
; Do not remove!
; Enh mode MS-DOSapp support
; Do not remove!
; Do not remove!
; Do not remove!
; MS-DOS app window fonts
; Applets -------------------------------------------------------------CALC.EXE
%RETAIL%calc.exe
CALENDAR.EXE %RETAIL%calendar.exe
CARDFILE.EXE %RETAIL%cardfile.exe
CHARMAP.EXE %RETAIL%charmap.exe
CLIPBRD.EXE %RETAIL%clipbrd.exe
CLOCK.EXE %RETAIL%c1ock.exe
NOTEPAD.EXE %RETAIL%notepad.exe
PACKAGER.EXE %RETAIL%packager.exe
PBRUSH.DLL %RET AIL%pbrush.dll
PBRUSH.EXE %RET AIL%pbrush.exe
PIFEDIT .EXE %RETAIL %pifedit.exe
RECORDER.DLL %RETAIL %recorder.dll
RECORDER.EXE %RETAIL%recorder.exe
SOL.EXE
%RETAIL%sol.exe
; TERMINAL.EXE %RETAIL%terminal.exe
WINMINE.EXE %RETAIL%winmine.exe
WRITE.EXE %RETAIL%write.exe
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
Hi ROM
HiROM
HiROM
HiROM
HiROM
; Calculator
; Calendar
;Cardfile
; Character Map
; Clipboard Viewer
; Clock
; Notepad applet
; Packager applet
; for Paintbrush
; Paintbrush
; PIF Editor
; for RECORDER.EXE
; Recorder
; Solitaire
; Terminal
;WinMine
; Write
; Applications ---------------------------------------------------------
FILES
; Specifies OPtional files to be installed into ROM.
; TrueType TTF font files are specified in this section .
.
; ROM Name Path ROM
; TrueType Data -------------------------------------------------------ARIAL.TTF %RETAIL%arial.ttf
ARIALBD.TTF %RETAIL%arialbd.ttf
ARIALBI.TTF %RETAIL%arialbi.tlf
HiROM
HiROM
HiROM
Arial
Arial Bold
Arial Bold Italic
292149-17
3-776
I
Ap·399
;
;
;
;
;
;
;
;
;
ARIALl.TTF %RETAIL%ariali.ttf
COUR.TTF
%RETAIL%cour.ttf
COURBD.TTF %RETAIL%courbd.ttf
COURBl.TTF %RETAIL%courbi.ttf
COURl.TTF %RETAIL%couri.ttf
SYMBOL.TTF %RETAIL%symbol.ttf
TIMES.TTF %RETAIL%times.ttf
TIMESBD.TTF %RETAIL%timesbd.ttf
TIMESBLTTF %RETAIL%timesbi.ttf
TIMESLTTF %RETAIL%timesi.ttf
WINGDING.TTF %RETAIL%wingding.ttf
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
HiROM
; Arial Italic
; Courier New
; Courier New Bold
; Courier New Bold Italic
; Courier New Italic
; Symbol
; Times New Roman
; Times New Roman Bold
; Times New Roman Bold Italic
; Times New Roman Italic
; WingDings
292149-18
I
3-777
intet@
Ap·399
APPENDIX D
PLD EQUATIONS
Included below are the equations for the EPX780.
EPX780-10 PLD
; Functional model for Simulation of Resident Flash Array design
Title
486SX RFA design
Pattern 1
Revision 4.0
Author
Rajiv Parikh
Company Intel Corporation
Date
9/20/94
=
OPTIONS DRIVE_LEVEL 3VOLT ; Default voltage is 3 Volts
CHIP Ul
NFX780_132
; Pinlist
; inputs
PIN
CLK
; Control signals from CPU
PIN
W_R
PIN
M_IO
PIN
. lADS
PIN
D_C
A[23:2]
PIN
PIN
IBE[3:0]
; Control signals from PLD to
; outputs
B[23:2]
PIN
ICEH[I:O]
PIN
ICEL[1 :0]
PIN
PIN
PIN
/WE
IOE
; Other signals
; input
PIN
RY_BY
; outputs
PIN
!RDY
IKEN
PIN
; main clock (used by register)
; Write!Read# from CPU
; Mlilo# from CPU
; ADS# from CPU
; D/C# from CPU
; Address lines from CPU, 0,1,24-31 not used
; Byte Enable lines from CPU
memory
; Address lines out of PLD to memory (23,22 NC)
; Chip enable out of PLD to memory high word
; Chip enable out of PLD to memory low word
; Write Enable# from PLD to memory
; Output Enable# from PLD to memory
; ReadylBusy# from memory to PLD/486
; Ready# from PLD to CPU
; Cache enable# from PLD to CPU
292149-19
3-778
I
AP-399
; DTIR# signal from PLD to Transceiver
PIN
; Data signals - only 10 bits go into the PLD.
; inputs
0[9:0]
; Data bus from CPU to PLD
PIN
NODE
R[9:0] REGFBK
NODE 1017 ADSWREG I
;pin#s required for prioritizing in v3.1
NODE 1039 ADSWREG2
NODE
NODE
NODE
ADSI REGFBK
ADS2 REGFBK
ADS3 REGFBK
; Registers in the ads delay chain
;STRING SUBSTITUTIONS
STRING EN '«ADS+ADSI+ADS2+ADS3)*M_IO)'
; Memory access enable
; Write Enable for sliding window reg.
;STRING SWAD '( IA23 * fA22 * IA21
IAl9 * IAI8 * IAl7 * IAI6 *
A15" AI4 * fAI3 * A12"
All * AIO * fA9 " IA8"
IA7 * IA6 * IA5 " IA4 *
IA3 "/A2 )'
* IA20 *
SW AD shows address of sliding window's
VO register (not used in equations)
STRING ADSWREG '(ADSWREG I "ADSWREG2)'
; Select sliding window register
STRING OESW '( EN *
fA23 * fA22 * fA21
AI9 * AI8 * IAI7
AI5 * A14)'
; Output Enable for sliding window reg.
; address ODCOOOh - ODPFFFh
* IA20"
* AI6 '"
STRING WSME '( EN *
IA23 * fA22 * fA21 "fA20"
AI9 * AI8 * fAI7 * Al6 *
A15 * fA14),
; MS Windows Stub Window Enable
; address OD8000h - ODBFFFh
EQUATIONS
; Setup register
; address decode logic - comparators
ADSWREG l.CMP = [A23.A22.A21.A20.A19,AI8,AI7,A 16.AI5,AI4,AI3.AI2]
==[GND.GND.GND.GND.GND.GND.GND.GND,VCC.VCC.GND.VCC]
ADSWREG2.CMP= [AII.AIO.A9. A8. A7, A6. A5. A4. A3, A2]
292149-20
I
3-779
Ap·399
==[VCC.VCC.GND,GND,GND.GND,GND,GND,GND,GND]
; Data bus feeds the register upon selection
R[9:0].D:= (ADSWREG *WESW) * D[9:0] + (IWESW+/ADSWREG) * R[9:0]
R[9:0].CLKF = CLK
; Setup the ADS delay chain
ADSI.D:= ADS
ADSI.CLKF = CLK
ADS2.D := ADS I '" (OE + WE)
ADS2.CLKF = CLK
ADS3.D := ADS2
ADS3.CLKF = CLK
; Output address
B23 = WSME + IWSME * (OESW * R9 + IOESW * A23)
B22 = WSME + IWSME * (OESW * R8 + IOESW * A22)
B21 = WSME + IWSME * (OESW * R7 + IOESW * A21)
B20 = WSME + IWSME * (OESW * R6 + IOESW * A20)
BI9 = WSME +IWSME * (OESW * R5 +IOESW * A19)
B 18 =
IWSME * (OESW * R4 + IOESW * A18)
IWSME * (OESW * R3. + IOESW * A17)
B 17 =
BI6 = WSME + IWSME * (OESW * R2 + IOESW * A16)
B 15 = WSME + IWSME * (OESW * RI + IOESW * A 15)
B14 =
IWSME * (OESW * RO + IOESW * A14)
;0
;0
;I
;I
;0
; pass through
B[13:2] = A[13:2]
; chip enable for each of four chips
CEHO = EN * ( B23 * 1822) * (BE3 + BE2)
CEHI = EN * ( B23 * B22) * (BE3 + BE2)
CELO = EN * ( B23 * 1822)
CELl = EN * ( B23 '" B22)
;I
;I
;I
;I
;I
; two pairs of high and
; low words
* (BEl + BEO)
* (BEl + BEO)
OE =EN * IW R
WE = M_IO '" W_R * (ADS I + ADS2)
; OE#formem
; WE# for mem
292149-21
3-780
I
AP-399
; Tranceiver signal
RDY= WESW
+ !W_R .. M_IO .. ADS3
+ W_R .. M_IO" ADS3
; After reg loading
; after reading
; after writing
; cache code reads only
; Simulation section
SIMULATION
VECTOR DBUS:= [D9 D8 D7 0605 D4 03 D2 01 DO]
VECTOR ABUSI:= [A23 A22 A21 A20 A19 A18 A17 A16 A15 Al4A13 A12 All AIO A9 A8 A7 A6
AS A4A3 A2]
VECTOR ABUSO:= [B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 BI2 Bll BIO B9 B8 B7 B6 B5
B4B3 B2]
VECTOR BSEL := [ BE3 BE2 BEl BEO 1
VECTOR CE := [CEHI CEHO CELl CELO 1
VECTOR SWREG:= [R9 R8 R7 R6 R5 R4 R3 R2 Rl RO 1
; Specify signals to be traced.
TRACE_ON CLK W_R M_IO ADS D_C DBUS ABUSI ABUSO BSEL CE SWREG WE OE
RY_BY ROY KEN DT_R ADSWREGI ADSWREG2
.
;Initialize inputs
SETF CLK W_R M_IO/ADS D_CIRY_BY ABUSI:= OXOOOOO BSEL :=OXO DBUS :=OXOOO
PRLDF 1R91R81R71R61R51R41R31R2IRIIR0
; Idle clocks
CLOCKFCLK
CLOCKFCLK
; Do a read from memory of two 32-bit words at 800000h
FOR READ2_32 := Ox200000 TO Ox200001 DO
BEGIN
; Validate Address
SETF ABUSI := READ2_32!W_R ADS
CLOCKFCLK
SETF lADS
; Remove ADS
CLOCKFCLK
CLOCKFCLK
CLOCKFCLK
CLOCKFCLK
END
292149-22
I
3-781
AP-399
; Sliding window load and read test:
; Write address OX800000 in swreg then try to read from
SETF DBUS := OX200 ABUSI := OX03700
SETF 1M_10 W_R ADS
CLOCKFCLK
SETF lADS
CLOCKFCLK
CLOCKFCLK
CLOCKFCLK
CLOCKFCLK
SETF M_IO /W _R ID_C ADS ABUSI := OX037000
CLOCKFCLK
SETF lADS
CLOCKFCLK
CLOCKFCLK
CLOCKF CLK
window
; OXODCOO» 2
; Validate Address
; Remove ADS
; set to memory CODE read
; Remove ADS
; read code! see cache line,etc
; now test the win stub mapping
SETF ABUSI:= OX36000
SETF ADS /W_R BSEL := OXO
CLOCKFCLK
; OXOD8000» 2
; Validate Address
SETF/ADS
; Remove ADS
CLOCKFCLK
CLOCKFCLK
; DONE!!!
TRACE_OFF
292149-23
3-782
I
infel·
ER-27
ENGINEERING
REPORT
The Intel 28F008SA
Flash Memory
ALAN BUCHECKER
JERRY KREIFELS
MEMORY COMPONENTS DIVISION
October 1993
3-783
The Intel 28F008SA Flash Memory
CONTENTS
PAGE
INTRODUCTION . ...................... 3-785
TECHNOLOGY OVERVIEW ........... 3-785
DEVICE ARCHITECTURE ............. 3-786
Array Organization ..................... 3-786
Write/Erase Automation ................ 3-786
Command User Interface (CUI) ......... 3-787
Write State Machine (WSM) ............ 3-787
Status Register ......................... 3-788
Ready/Busy Indication (RY/BY#) ...... 3-788
CONTENTS
PAGE
. DEVICE CHARACTERIZATION .... .... 3-792
AC and DC Parameters ................. 3-792
Energy/Power Consumption ............ 3-792
Byte-Writ~/Block-Erase
Times ......... 3-792
DEVICE RELIABILITY ................. 3-792
Byte-Write/Block-Erase Cycling ........ 3-792
Data Protection ........................ 3-793
SUMMARY ............................ 3-793
OTHER REFERENCES ................ 3-793
Internal Oscillator ...................... 3-788
Supply Voltage Sensing ................ 3-788
SUPPLEMENTARY INFORMATION ... 3-794
Reset/Power-Down .................... 3-789
Block Erase ............................ 3-790
Erase Suspend/Resume ............... 3-791
Byte Write .............................. 3-791
3-784
I
ER-27
INTRODUCTION
TECHNOLOGY OVERVIEW
The ETOX III (EPROM tunnel oxide) 28FOO8SA is a
high·density product offering from Intel's second gen·
eration of flash memory devices. This 1,048,576 x 8
memory with its symmetrical blocking (16 blocks x
64 Kbytes), very high cycling endurance, on·chip
write/erase automation, and erase·suspend/resume ca·
pability can be termed a block·alterable non· volatile
RAM. In addition to selective block erasure, integrated
Command User Interface (CUI), Write State Machine
(WSM), Status Register, and deep power·down capabil·
ity, the 28F008SA adds a dedicated READY/BUSY
output (RY/BY #). This new feature provides immedi·
ate hardware signaling of byte·write/block·erase com·
pletion and erase·suspend/resume actuation.
Intel's ETOX III flash memory technology incorpo·
rates advances from ETOX I and ETOX II processes
and leverages over two decades of EPROM manufac·
turing experience. Using advanced 0.8 /-Lm double·poly·
silicon N·welllP·well CMOS technology, the 1,048,576
x 8·bit flash memory employs a 2.5 /-Lm x 2.9 /-Lm sin·
gle·transistor cell affording array density equivalent to
comparable EPROM technology, and twice that of In·
tel's ETOX II process. The ETOX III flash memory
cell is identical to EPROM, with an additional source
implant which optimizes erase performance. Figure I
shows a cross·section of the flash memory cell.
Flash memories combine inherent non·volatility with
in· system alterability of device contents. Advances in
process control have allowed development of a double·
poly silicon single· transistor flash memory capable of
100,000 write/erase cycles per block. The 28FOO8SA
electrically erases all bits in a block 'via electron tunnel·
ing. The EPROM programming mechanism of hot·
electron injection is employed for high·performance
electrical byte write as required for file and data storage
applications.
High·quality tunnel oxide under the single floating
polysilicon gate promotes electrical erasure. All cells
within the selected block are simultaneously erased via
Fowler·Nordheim tunneling. Applying 12V to block
source junctions and grounding the control gates erases
all cells within that block. The internal WSM controls
the automated block·erase algorithm, including pre·
erase conditioning (i.e., pre·programming all block bits)
and margin verification, in response to user requests
relayed by the CUI. WSM·controlled block erasure, in·
cluding pre·programming, typically requires 1.6 sec·
onds.
The Command User Interface and Status Register in·
terface to power·up/down protection, address/data
latches, and the Write State Machine (which in turn
controls internal byte write, block erase, cell· margin
circuits, and the dedicated READY/BUSY status out·
put). These features augment prior flash memory cir·
cuitry to optimize Intel's 28FOO8SA for microproces·
sor·controlled byte write and block erase.
Byte write is accomplished with the standard EPROM
mechanism of channel hot·electron injection from the
cell drain junction to the floating gate. Bringing both
the control gate and the cell drain to high voltage initi·
ates programming. The WSM regulates the internal
byte·write algorithm, including margin verification, af·
ter the correct command sequence is written and de·
coded. Byte write typically requires 9 /-Ls.
Read timing parameters are comparable to those of
CMOS DRAMs, SRAMs, EPROMs, and EEPROMs.
The 85 ns access time results from a memory cell·cur·
rent of approximately 70 /-LA, low·resistance polysili·
cide wordlines strapped with metal, advanced scaled
periphery transistors, and an optimized data·out buffer.
The dense one·transistor cell structure, coupled with
high array efficiency, yields a one· megabyte die mea·
suring 539 by 286 mils.
SECOND LEVEL
POLYSILICON
+VG
~
j
......IL..--,
'1-1
FIRST LEVEL
POL YSILICON
(FLOATING)
VS
GATE OXIDE
294011-1
Figure 1. ETOX Flash Memory Cell
I
3-785
ER-27
Addresses A9-Ao select one of.l024 rows. while A19
selects upper or lower decoder. Row address lines are
decoded sequentially for selection. Row address bitmaps are listed in Table 3.
DEVICE ARCHITECTURE
Array Organization
The 28FOO8SA is a 1,048,576 x 8 memory comprised of
2048 rows by 8192 columns, Array layout is segmented
as four quadrants, each 1024 rows by 2048 columns.
Access time is reduced by limiting column length to
1024 cells. The polysilicon row is strapped in metal
every 512 columns to reduce wordline delay. Two row
decoders ·run vertically between quadrants, and column
decoders run horizontally between quadrants. Figure 2
shows block placement and array organization. A die
photo of the chip is Shown in Figure 30.
Each quadrant is subdivided into four 64-Kbyte blocks.
Each block source is electrically isolated from the
source of other blocks. This allows individual block
erase without altering data in the remaining 15 blocks.
,
Each block is further subdivided into eight Input/Out·puts. Data for 1/00 is stored in the left-most 64 columns, with the next 64 storing data forI/Ot, e~c.
Columns are numbered 0-8191 from left to right, top
to bottom. Addresses A19-A16 select one of 16 blocks,
while AlS-AIO select eight of the 512 columns within
that block. These ten address lines are also decoded
sequentially to access all 8192 columns. Block address
bitmaps are listed in Table 4; column address bitmaps
. are listed in Table 5.
Write/Erase Automation
Intel's 28FOO8SA contains an on-chip Command User
Interface, Write State Machine, Status Register, and
address/data latches to dramatically simplify user interface. This combination of functional units reduces
microprocessor control complexity of byte-write, blockerase,erase-suspend!resume, Status Register read/
clear, iD read, and array read operations. Figure 3,
shows the 28FOO8SA block diagram.
Rows in the upper quadrants are numbered 0-1023
from top to bottom; lower quadrant rows similarly
1024-2047.
.
BLOCK 0
BLOCK 1
BLOCK 2
BLOCK 3
BLOCK 4
BLOCK 5
BLOCK 6
BLOCK 7
00000OFfff
10000lffff
200002fffF
300003ffff
400004fFff
500005FFfF
600006fffF
700007Ffff
COLUMN DECODER
COLUMN DECODER
BLOCK 8
BLOCK 9
BLOCK 10
BLOCK 11
BLOCK 12
BLOCK 13
BLOCK 1'4
BLOCK 15
800008ffFF
900009ffFF
AOOOOAFFfF
BOOOOBFFfF
COOOOCFFFF
DOOOODFffF
EOOOOEFffF
fOOOOFFffF
294011-2
Figure 2. 28F008SA Block Placement and Array Organization'
3-786
I
ER-27
Command User Interface (CUI)
The CUI consists of a command decoder and command
register. User requests are decoded and latched in a
microprocessor write cycle controlled by Chip Enable
(CE#) and Write Enable (WE#). Status Register
read/clear, ID read, and array read commands are directly handled by the CUI. The CUI also accepts bytewrite, block-erase, and erase-suspend/resume commands. WE#'s rising edge latches address, command
and data-in registers, and requests WSM initiation of
the selected operation. These on-chip address, command, and data latches controlled by the CUI minimize
system interface logic, and free the system bus.
Write State Machine (WSM)
The WSM processes byte-write, block-erase, and erasesuspend/resume requests received from the CUI. The
WSM rejects byte-write and block-erase requests if the
WSM is currently busy, if Vpp is not at high voltage
(12V), or if the Low Vpp Status Register flag is set (Le.,
not cleared from a previous low-voltage condition).
The WSM consists of an integrated oscillator and control circuitry. It generates signals which control the
byte-write, block-erase, erase-suspend/resume, and verify circuits. It also receives feedback from these circuits
allowing Status Register update. The WSM and associated circuits perform the equivalent of first-generation
flash memory program and bulk-erase algorithms automatically. This eliminates the need for system timers,
and frees the microprocessor to service interrupts or
perform other functions during device byte-write or
block-erase operations.
The WSM provides feedback to the CUI to determine
when a given command is valid. Although nearly all
'commands are available when the WSM is inactive,
only status read is valid while the WSM performs a
byte-write operation. During block erase, only the readstatus and erase-suspend commands are available.
Read-array, read-status, and erase-resume commands
are valid with the WSM in an erase-suspended state.
Invalid operations are interpreted as the read-array
command when the WSM is inactive or erase-suspended, and as the read-status command when the WSM is
active in byte write or block erase.
DQO - Do-,
r""':"'--k.--l--!-J---
CEO
1+--+-4----- WE>
14--'------ OE>
~~~~j+-------RP>
,-;::====::;-+
RY/sy>
Vpp
_Vee
_GND
294011-3
Figure 3. 28F008SA Block Diagram
I
3-787
ER-27
Status Register
Internal Oscillator
The internal Status Register contains a full complement
of activity status bits. These bits and their meaning
(1,0) are:
.
The WSM is designed using clocked logic circuits. An
on-chip ring oscillator generates the clock signals. The
frequency of a standard ring oscillator varies with pro~
cessing, temperature and supply voltage. An improved
design, used on the 28FOOIBX and 28FOO8SA, minimizes these variations.
SR.7: WSM status (READY/BUSY)
SR.6: Erase~suspend status (ERASE SUSPENDEDI
ERASE IN PROGRESS OR COMPLETED)
SR.5: Block-erase status (ERROR/SUCCESS)
SR.4: Byte-write status (ERROR/SUCCESS)
SR.3: Vpp status (LOW10K)
All bits are set by the WSM, and read via the CUI. The
WSM can only set SR.3, SR.4, and SR.5; it cannot
clear them. They remain set until the CUI processes a
clear Status Register command. There are two reasons
for operating in this fashion.
First is synchronization; the WSM does not know when
the host CPU has read the Status Register, therefore
does not know when to clear it.
Secondly, allowing system software to control reset
adds flexibility to the way this device may be used. The
CPU may write several bytes or erase several blocks
back-to-back while monitoring RY/BY# or polling
SR.7 to determine when the next byte-write or blockerase command can be given. When all bytes are written, or all blocks erased, the system polls the other
status flags to determine if all operations were successful or if an error occurred. While other approaches require the controlling microprocessor to watch for noncompletion of write or erase within a specified time to
indicate an error, this implementation requires no ex"
ternal system timers or software timing loops. As such,
the system can reduce its polling overhead while still
identifying any potential error conditions.
Status Register contents are driven to device outputs on
the falling edge of CE# or Output Enable (OE#),
whichever occurs last in the read cycle. CE# or OE#
must be toggled to update Status Register contents.
The switching current of each stage in the ring oscillator is controlled by a current reference which varies
linearly with Vee. The trip point of each ring oscillator
,inverter also varies linearly with Vee. These two effects
offset each other, and the resulting oscillator period is
proportional to RC with only a small dependence on
Vee·
An on-chip resistor sets the value of R. The gate capacitance of the inverters in the ring oscillator sets the
value of C. Process variations in these values are reduced by trimming the period of each oscillator during
manufacturing. The resistor is the only source of temperature variation.
Supply Voltage Sensing
The LOWVee and LOWVpp generation circuit is
shown in Figure 4. Power supply voltages (Vee and
Vpp) are divided down and compared to a reference
voltage. IfVREF is greater than the divided power supply voltage, the LOWVee or LOWVpp signal is driven
high. The generated VREF level is supply-voltage independent to the first order.
Positive power to the circuit is supplied by Ml and M2.
Ml and M2 sources are pulled up to the higher of (Vpp
- VuJ or (Vee - Vtw). Vtn is the threshold of an
implanted N-channel device, about a.9V. Vtw is the
threshold of a native N-channel device, about av. This
scheme ensures that the circuit works regardless of the
applied supply voltages.
ReadyIBusy Indication (RYIBY #)
A dedicated output pin, RY/BY #, provides additional
indication ofWSM activity. This capability allows both
hardware signal of status andlor software polling to
determine activation, completion, or suspension of internal byte-writelblock-erase operations. Hardware signaling minimizes both CPU overhead and system power consumption.
LOW Vee
LOW Vpp
294011-4
Figure 4. Low Power Detector Circuit
3-788
I
intel®
The LOWVcc signal is used by the byte-write and
block-erase circuits, as wen as the CUI and WSM. If
LOWVcc is active, the CUI will not accept user writes
and resets to an array read condition. The WSM is
similarly reset by LOWVcc. The LOWVpp signal is
used by the WSM; if Vpp drops below the high-voltage
detector trip point during byte write or block erase, the
Status Register's low Vpp bit is set and WSM operation
halts. The system must clear the Status Register before
any subsequent byte-write or block-erase operations
can succeed.
ER-27
could cause enough subthreshold conduction in M3 to
exceed the Icc deep power-down current (ICeD) specification. This is why RP #'s input voltage is specified as
GND ±0.2V.
RP# also functions as a hardware reset to the WSM
and CUI. If RP # is driven active during byte-write,
block-erase, or erase-suspend operation, that operation
is aborted leaving the addressed memory locations in an
unknown state. The Status Register is cleared, and CUI
is set to array read. The aborted operation (byte write
or block erase) must be repeated with RP# inactive to
obtain a valid condition in the memory array.
Reset/Power-Down
The 28FOO8SA incorporates a deep power-down mode
that reduces IcC and Ipp to typically 0.20 /LA and
0.10 /LA respectively. RP# low selects deep powerdown mode. When RP # is high, the device can be
placed in an active or standby mode depending on
CE#'s state.
Deep power-down is similar to standby except that an
circuits excluding the RP# buffer are turned off. This
mode greatly reduces power consumption, but requires
more time to transition the device into an active mode.
A read wake-up time (tPHQV) is required from RP#
switching high until output and sense circuitry become
fully functional and data can be read from the part.
Similarly, a write wake-up time (tpHwd is needed before the CUI recognizes writes. After this interval, normal operation is restored; the CUI is reset to read-array
mode and the Status Register is cleared to SOH.
A diagram of the power-down circuit is shown in Figure 5. The TTL buffer formed by MI-M3 disables the
low-power detect circuits, the redundancy-address flash
bits, and the CE# TTL buffer formed by M4-M6. In
previous Intel flash devices, these circuits were always
enabled. Tum-on delays of these circuits determine
RP# access time and write specifications.
RP# functions properly with TTL-level inputs. However, to attain lowest possible power consumption, full
CMOS levels must be used. If the voltage on the gate of
M3 rises above its 0.9V threshold M3 will tum on and
draw current. Input voltages in the O. 7V -0.9V range
I
Reset using RP # should be restricted to system reset
only (as in the case of power supply failure), and should
not be used as a software means to terminate byte-write
or block-erase operations.
LOW POWER
DETECT
REDUNDANCY
CHIP INTERNAL
RESET
TO THE REST
OF
THE CHIP
294011-5
Figure 5. Power-Down and Reset Functions
3-789
ER-27
LOW Vee
BLOCK 0
SOURCE
ERASEBO
~9-~6
ERASE
BLOCK
SELECT
LATCHES
AND
DECODERS
ERASEBO
BLOCK 1
SOURCE
ERASEB14
ERASEB15
••
•
BLOCK 14
SOURCE
BLOCK 15
SOURCE
294011-6
Figure 6. Array Erase Blocking
Block Erase
Block erasure is achieved by a two-step write sequence.
The erase-setup code is written to the CUI in the first
cycle. Erase confrrm is written in the second cycle. The
address supplied with the erase-confirm command is
latched and decoded internally by the 28FOO8SA; erase
is subsequently enabled in that block. The second
WE# rising edge initiates the operation (WE#controlled write).
The WSM triggers the high-voltage flash-erase switch
connecting the 12V supply to the source of all bits in
the specified block, while all wordlines are grounded.
Figure 6 shows organization of the block source
switches. Fowler-Nordheim tunneling results in simultaneous erasure of all bits in the selected block.
The block source switch controls the source voltage of
all bits in a particular block. This circuit is shown in
Figure 7. During block erase, M2 is off and MI pulls
the source to Vpp. When not in erase, MI is off and M2
pulls the source to ground. The high-voltage latch
formed by M4-M7 converts the low-voltage ERASE
signal to a high-voltage signal that controls Ml.
The tunneling that occurs during block erase requires
only a small amount of current. However, the initial
current required to charge the block's large source capacitance to the erase voltage is significant. M I is sized
to limit this current yet still apply sufficient source voltage to achieve fast block-erase time.
The LOWVee signal protects the array from erasure
when Vpp is at a high voltage but Vee is below the
write/erase lockout voltage (VLKO)' When this occurs,
M3 pulls the block source to ground. The high-voltage
latch is forced by M8 into the state that turns Ml off.
Vpp is continually monitored during all phases of the
block-erase operation. If Vpp falls below the trip point
of its high-voltage detect circuitry, erasure will not occur (or halts) and Status Register Vpp status (SR.3),
block-erase status (SR.S) and WSM status (SR.7) bits
are set to "I".
M1
.-----.....-+
BLOCK
SOURCE
LOWVce}-~----------------~------~
ERASE }-------------------~__I ~o_------_I
294011-7
Figure 7. Block Source Switch
3-790
I
ER-27
If SR.3 (Low Vpp) is set, WSM operation is inhibited.
The WSM will not execute further byte-write or blockerasure sequences until the Status Register has been
reset by system software. Byte-write or block-erase requests with error flags SRA or SR.5 set are not inhibited, but the system loses the ability to determine success.
The clear Status Register command resets these bits.
After receiving the block-erase command sequence, the
WSM automatically controls block pre-condition (programming all bytes to OOH within the chosen block),
erase pulses and pulse repetition, timeout delays, and
byte-by-byte verification of all block addresses (sequentially checked via the address counter) using an alternative sensing reference to verify margin. The internal
erase and verify operations continue until the entire
block is erased. A read cycle applied to the part following the block-erase command sequence outputs Status
Register contents; system software can poll the Status
Register to determine when block erase is complete,
and if it was successful. Alternately, the system can
monitor RY/BY # until that output is driven high, and
then poll the Status Register to determine success. Following block erasure, the device remains in Status Register read mode; a read-array command must be written
to the device to access array data.
If the erase-setup command is followed with a command other than erase confirm, the device will not
erase. The WSM sets both byte-write status and blockerase status bits in the Status Register to indicate an
invalid sequence.
Erase Suspend/Resume
Erase suspend allows the system to interrupt block
erase to read data from another array block. The ability
to suspend erase and read data from another block offers the flexibility required for file system applications.
Upon receiving the erase-suspend command, the CUI
requests that the WSM pause at one of several predetermined points in the algorithm. Upon reaching a suspend point, the WSM sets SR.6 (erase-suspend status)
and SR.7 to "I", and drives the RY/BY# pin high.
The system must poll the Status Register to determine
if the suspend has been processed or the block erase has
actually completed. Block-erase completion is indicated
by SR.6 cleared to "0" and SR.7 set to "I". Read bus
cycles default to Status Register read after issuing the
erase-suspend command.
I
Once suspended, the WSM asserts a signal to the CUI
which allows response to the read-array, read-status,
and erase-resume commands. The system can write the
read-array command allowing read access to blocks
other than that which is suspended. The WSM continues to run idling in a suspended state, regardless of all
control inputs except RP #. RP # driven low immediately shuts down the WSM, aborting the suspended
erase operation.
.
The erase-resume command must be issued upon completion of reads from other array blocks to continue
block-erase operation. The WSM then clears SR.6 and
SR.7, drives RY/BY# low, and resumes erase operation from the suspension point. Read cycles following
the erase-resume command output Status Register
data.
Byte Write
Byte write follows a flow similar to block erase. The
byte-write setup command is first written to the CUI. A
second write cycle loads address and data latches. The
rising edge of the second WE# pulse requests that the
WSM initiate activity, applying high voltage to the
gates and drains of all bits to be written. Unlike block
erase, byte write will proceed regardless of what data is
applied on the second CUI write cycle; however, applying data FFH does not modify memory contents.
Like block erase, the WSM controls program pulses
and pulse repetition, timeout delays and byte verification. Byte write and verify (with alternate sensing reference and internally-generated verify voltage) continue
until the byte is written. Internal byte-write verify
checks that all bits written to zero have been correctly
modified; it does not check bits specified as one. Byte
write cannot change existing zeros to ones; this can
.
only be accomplished by erase.
Read bus cycles following byte write operations output
Status Register data. System software, polling the
Status Register, is informed of status through bits SR.3,
SR.4, and SR.7. The RY/BY# output can also be
monitored to determine completion. The read-array
command must 'be written to the CUI following byte
write to access array data.
In a scenario similar to that described under block erasure, byte write does not occur (or halts) if Vpp is detected low. In such a case SR.3, SR.4, and SR.7 are set
high, and no further writes can take place until the
Status Register is cleared by the clear Status Register
command.
3-791
ER-27
Table 2. Byte-Write and Block-Erase
Performance vs Previous Devices
DEVICE CHARACTERIZATION
Device
AC and DC Parameters
Figures 9 through 24 show graphs of several device
parameters as a function of temperature and supply
voltage. The graphs illustrate that the 28F008SA has
significant margin to data sheet specifications.
In particular, note Figure 9 which shows typical read
performance tAvQV (tACe) of the 28F008SA as a function of V cc and ambient temperature. tELQV (tc~ in
Figure 10 and tGLQV (tOE) in Figure 11 are also of
particular interest. Access times tAvQv, tELQV, and
tGLQV are specified and tested with an output load of
100 pF; additional output load capacitance slows device
operation.
Table 1 shows typical supply currents at room temperature for several operating modes.
Table 1. RMS Current Values
Mode
lee
Ipp
(Vee = 5.0V,
(Vpp = 12V)
CMOS Inputs)
Read
20mA
100,..,A
Byte Write
10mA
12 mA
Block Erase
10mA
12 mA
Standby
Deep Power-Down
40,..,A
100,..,A
0.20,..,A
0.07,..,A
EnergyIPower Consumption
The system designer is primarily co~cerned with power
consumption during block erase and byte write. Typical
curves for Icc and Ipp during block erase are shown in
Figure 25. ICC and Ipp for byte write are illustrated in
Figure 26.
Byte-Write/Block-Erase Times
The 28F008SA advances byte-write and block-erase
performance compared to previous flash memories. The
on-chip algorithm is improved over the 28FooIBX to
take advantage of process enhancements. This improvement is most apparent when compared to first-generation flash parts with externally controlled algorithms.
First-generation device times shown in Table 2 assume
optimal system overhead, and as such are absolute best
case.
3-792
Byte-Write Block-Erase Erase Time
Time
Time! # Bytes per Kbyte
Second-Generation Flash Memory Devices(1)
2BFOOBSA
2BF001BX
9,..,s
1B ,..,s
1.5s/64K
3.Bs/112K
2.1s/BK
2.1s/4K
23ms
34ms
256ms
513 ms
First-Generation Flash Memory Devices(2)
2BF020
16.5,..,s
6.Bs/256K
27ms
2BF010
16.5,..,s
3.9s/12BK
30ms
2BF512
16.5,..,s
2.4s/64K
37ms
2BF256A
16.5,..,s
1.6s/32K
51 ms
NOTES:
1. Typical measured time.
2. Times calculated based on typical erase and precondition pulse requirements, with minimum write timings. Calculations are described in Figure 8.
Figure 27 shows block-write and block-erase times at
O°C and 70°C over cycling.
DEVICE RELIABILITY
Byte-Write/Block-Erase Cycling
One of the most important reliability aspects of the
28F008SA is its capability of 100,000 write!erase cycles
per block. Destructive oxide breakdown has been a limiting factor in extended cycling of thin-oxide
EEPROMs. Intel's ETOX III flash memory technology extends cycling performance through:
• Improved tunnel-oxide processing that increases
charge-carrying capability tenfold.
• Significantly reduced oxide area under stress that
minimizes probability of oxide defects in the region.
• Reduced oxide stress due to a lower peak electric
field (lower erase voltage than EEPROM).
Reliable byte-writelblock-erase cycling requires proper·
selection of the maximum erase threshold voltage (Vt),
and maintenance of a tight distribution. Maximum
erase Vt is set to 3.4V via the internal block-erase algorithm and verify circuits. Tight erase Vt distribution
gives an order of magnitude of erase-time margin to the
fastest erasing cell, with virtually identical erase Vt distributions at 1 and 10,000 cycles (Figure 28). Program
Vt distribution is similarly consistent over cycling (Figure 29).
I
ER-27
28FOO8SA array architecture enhances cycling capability by reducing gate disturb conditions on cells in unrelated blocks during byte write and erase pre-conditioning. First, only one of the two row decoders is active at
any time (selected by AI9)' Rows in the other two
quadrants are grounded. Secondly, two separate internally-switched voltages supply the left and right quadrants. Only one supply (selected by block address A18)
is switched to programming voltages while the other
remains at read voltages. This A19-A18 row decoding
ensures that during byte write, 120fthe 16 blocks have
a gate voltage below that required for programming.
Data Protection
The 28F008SA offers protection against accidental
block erasure or byte write during power transitions.
Internal circuitry creates a device insensitive to Vpp/
Vee supply power-up sequencing. Vpp ~ VPPL locks
out byte-write and block-erase circuits. Vee ~ VLKO
disables CUI command writes, resets the CUI to array
read mode, and holds the WSM inactive. The system
designer must still guard against spurious command
writes for Vee> VLKO when Vpp > VpPL.
Several strategies are available to prevent data modification in the 28FOO8SA. The CUI provides a degree of
software write protection since memory alteration occurs only after successful completion of a two-step
write sequence. WE# and CE# must both go active to
perform this sequence; driving either high inhibits command/data" writes. Secondly, the system can place the
device in deep power-down mode (RP# = VIL) to
disable command writes, reset the CUI to array read
I
mode, and hold the WSM inactive, effectively protecting array data. Finally, the system designer may hardwire Vpp to VPPH, or switch it to VpPH only when
memory. updates are required. Since byte-write and
block-erase circuits are disabled by Vpp ~ VPPL, Vpp
switching adds another level of data security.
SUMMARY
The 28FOO8SA is the first flash memory with features
optimized for solid-state systems and file storage. These
features include symmetrical block-erase, automation
of byte write and block erase, erase suspend for data
read, a reset/power-down mode, a write/erase Status
Register, and a dedicated RY/BY# status pin. With
simple microprocessor interfacing and software command sequences, the 28FOO8SA is the non-volatile storage solution of choice for today's designs.
OTHER REFERENCES
Related documents of interest to readers of this engineering report:
28FOO8SA Data Sheet (order #290429)
28FOO8SA-L Data Sheet (order #290435)
AP-359 "28F008SA Hardware Interfacing"
(order #292094)
AP-360 "28F008SA Software Drivers"
(order #292095)
AP-364 "28FOO8SA Automation and Algorithms"
(order #292099)
ER-28 "ETOX III Flash Memory Technology" (order #294012)
3-793
ER-27
SUPPLEMENTARY INFORMATION
FORMULA:
100
b = # bytes in a block (256K, 128K, 64K, 32K)
n = # of erase pulses required (90 pulses)
90
w = time for a write cycle (150 ns, tAvAV)
v = time to verify (6055 ns, tWHGL + tGLQV)
p = program pulse width (10 I-ts, tWHWHI) one
pulse programming assumed
e = erase pulse width (10 ms, tWHWH2)
80
~
-5
>
g
70
-<
60
Precondition and precondition verify time is:
b(2w+p+v)
50
Erase/verify, each loop where some byte does not
pass verify:
(n - 1) (2w
+
e
+
4.5
v)
5.0
5.5
6.0
vee (v)
Last erase pulse:
(1) (2w
+
294011-8
e)
Figure 9. tAVQV (tAee) vs Vee and Temperature
Passing erase-verify, all bytes:
b (w
+
v)
Total time can be summarized as:
b (3w + P + 2v) + n (2w + e + v) - (v)
or substituting in times for write, verify, program
and erase pulse widths:
b (22.56 x 10- 6) + n (10.006355 x 10- 3)
- (6.055 x 10- 6) Seconds
Figure 8. Erase Time Calculations for
First-Generation Flash Memories
110
34
100
32
90
30
.
28
~
-5 80
g> 70
~
..!i'
-5
26
>
a
24
-'
S'
60
22
20
50
18
4.5
5.0
5.5
6.0
vee (v)
294011-9
Figure 10. teLQV (tee) vs Vee and Temperature
3-794
4.5
5.0
5.5
6.0
Vee (v)
294011-10
Figure 11. tGLQV (toe) vs Vee and Temperature
I
ER-27
24
-2
22
-4
20
.,..
18
.5
16
-6
:I:
j
~
.
-8
x
-10
~
.5
c
14
:I:
.JI' -12
12
-14
10
-16
8
-18
4.5
5.0
5.5
6.0
4.0
4.5
Vee (V)
5.0
5.5
6.0
Vee (V)
294011-11
294011-12
Figure 12. tOVWH (tos WE#)
VS Vee and Temperature
Figure 13. tEHOX (tOH CE#)
vs Vee and Temperature
28
-2
I"
'" i'o.. li5 C
24
~
22 1""'26
-4
0
.,..
.5
:I:
~
>
-<
I"
"- .........:!..OOC
20
18
16 ~
14
12
1'-0..
10
f"'.....
-6
'" ......
......... 1'-0.. ooe :-. .....
....... i'...
8
-.,.......
-55°C -
......... 1'-0..
6
4
4.0
4.5
5.0
.........
--
....... ....
.........
.........
5.5
6.0
Vee (V)
.5
-8
x
<
:I:
~
-10
-12
-14
-16
4.0
4.5
5.0
6.0
5.5
Vee (V)
294011-13
. Figure 14. tAVWH (tAS WE#)
Vs Vee and Temperature
I
..
~
294011-14
Figure 15. tWHAX (tAH WE#)
vs Vee and Temperature
3-795
ER-27·
2
24
22
0
20
-55°C
-2
18
.....
..s
...>
.....
..s
16
:I:
14
-<
12
...
-4
)(
'"
-<
10
-6
-8
8
-10
4.5
5.0
5.5
6.0
4.5
5.0
5.5
6.0
Vee (V)
Vee (V)
294011-15
294011-16
Figure 16. tAVEH (tAS CE#) vs
Vee and Temperature
Figure 17. tAHEX (tAH CE#)
VS Vee and Temperature
65
22
·20
60
18
55
16
.....
..s
14
.....
12
'"~ 10
....
~
45
~
40
'"'"
8
6
IOns IS LIIAIT
OF IAEASUREIAENT
HARDWARE
4
50
..s....
35
30
2
0
4.0
4.5
5.0
5.5
6.0
Vee (V)
3·796
5.0
5.5
6.0
Vee (V)
294011-17
Figure 18. tWLWH (twp)
vs Vee and Temperature
4.5
294011-18
Figure 19. tWHRL VS Vee and Temperature
I
ER·27
1.40
2.0
1.35
1.9
1.8
1.30
~
~
-'
>- 1.25
;>
1.7
:I:
()
()
:i 1.20
:i
...z
...
z)-
)-
Q
1.6
1.5
Q
1.15
1.4
1.10
1.3
4.5
5.0
5.5
6.0
Vee (V)
4.5
5.0
5.5
294011-19
Figure 20. Dynamic VIL
vs Vee and Temperature
I
6.0
Vee (V)
294011-20
Figure 21. Dynamic VIH
vs Vee and Temperature
3-797
ER-27
70
13
12
60
11
<-
-5
...J
1=
50
<-
-5
10
II>
40
0
::E
(.)
:J:
_0
:J:
_0
30
8
7
20
6
4.5
5.0
5.5
6.0
Vee (V)
4.5
5.0
5.5
6.0
Vee (V)
294011-21
Figure 22. IOH TTL vs Vee and Temperature
(VOH = 2.4V)
294011-22
Figure 23.IOH CMOS vs Vee and Temperature
(VOH = Vee - O.4V)
34
32
30
28
<'
-5
26
24
~
_0
22
20
18
16
4.5
5.0
5.5
6.0
Vee (V)
294011-23
Figure 24.IOL vs Vee and Temperature
(VOL = O.45V)
3-798
I
ER-27
16mA
-
I
-
2mA
/DIY
ICC ERASE
I A
i,L klrll IU."" .~
-."
MIll
-4mA
-200ms
16mA
-
INj
III
W.JIj MlJI
200ms/DIY
1.8s
294011-24
I
Ipp ERASE
ilt
2m.A
/DIY
mM
·'mn
UIII _III
I'll
-4mA
-200ms
IIII "-
-i"Ytn
200ms/DlY
1.8s
294011-25
Figure 25. Icc and Ipp under Block-Erase Operation
I
3-799
ER-27
16mA
ICC PROG'
2mA
IDIV
.IA.
f-.-- IAI
"
v~
.a .•1. IA.l ...
oI.lI.
....
-4mA
-2).....
:::;
...
'"0
90
..,'"
0-
50
>
;::
...
10
=>
u
0.1
0.01
0.001
-'
=>
:2
h
AFTER 10k PIE CYCLES I- ~/'?'
I~
II
BEFORE
CYCLING
1
'7
OcO 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.02.22.42.62.83.03.23.4
294011-29
Figure 28. Erase Vt vs Cycles
28F008SA Programmed Vt Dist. vs Cyclingj Vpp = 12Vj TA = Room
/
99.999
99.99
99.9
99
.90
/
L
./
V
/
; 50
AFTER 10k ____
10 f--- PiE CYCLES
/
-I_
I
0.1
0.01
/
I
I
I
I- -BEFORE
I
I
_
CYCLING
I
0.001
5:0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
294011-30
Figure 29. Program Vt vs Cycles
3-802
I
ER-27
294011-31
Figure 30. 2781F008SA Die Photo
I
3-803
ER-27
0
Vpp
1
RP#
2
CE#
Vee
All
3
A,2
AlO
4
A'3
Ag
5
A'A
A1S
A7
7
A'6
As
8
A17
As
9
AlB
As
A4
NC
PA28F008SA
10 44 LEAD PSOP
0.525" x 1.110"
11
TOP VIEW
AI9
NC
NC
12
NC
NC
A3
13
A2
14
AI
15
WE#
Ao
16
OE#
'DOo
17
RY/BY#
DO,
18
D~
D02
19
DOs
31
NC
D03
20
DOs
GND
21
D04
GND
22
Vee
Pin Names
Ao':'A19
DOo-D07
CE#
RP#
OE#
WE#
RY/BY#
Vpp
Vee
GND
Address Inputs
Data Inputs/Outputs
Chip Enable
Reset/Power-Down
Output Enable
Write Enable
Ready/Busy
Write/Erase Power Supply
Device Power Supply
Ground
294011-32
Figure 31. PSOP Lead Configuration
3-804
I
intel®
ER-27
Standard Pinout
NC
0
AI9
AI8
A17
A16
NC
WEn
OE#
A1S
RY/BY#
DO-,
A,4
A13
006
STANDARD PINOUT
E28F008SA
40 LEAD TSOP
10 mm X 20 mm
TOP VIEW
AI2
CE#
Vee
Vpp
RP#
All
A10
DOs
0°4
31
Vee
GND
GND
003
0°2
As
A8
0°1
000
A7
Ao
As
Al
As
A2
21
A4
A3
294011-33
Reverse Pinout
NC
NC
~V
0
WEn
40
39
A19
A18
38
An
OE#
4
37
RY/SY#
5
36
AI6
A1S
DO-,
006
7
6
DOs
8
0°4
9
Vee
10
GND
GND
003
11
12
0°2
14
0°1
000
35
REVERSE PINOUT
F28F008SA
40 LEAD TSOP
10 mm X 20 mm
TOP VIEW
A14
A13
34
33
A12
CE#
32
31
30
Vee
Vpp
29
RP#
28
27
All
A10
15
26
A9
16
25
A8
Ao
17
24
A7
AI
18
23
As
A2
19
22
As
A3
20
21
A4
13
294011-34
Figure 32. TSOP Lead Configuration
I
3-805
ER-27
Wordlines are numbered sequentially from top to bottom. Addresses A9-AO sequentially decode wordlines: block
address A19 selects between upper and lower row-decoder. Wordlines 0-1023 serve the left and right quadrants at
top of device; 1024-2047 serve the lower quadrants.
Table 3. Row Address Bitmap
A19
Ag
As
A7
As
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
As
A4
A3
A2
A1
AO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
2
0
0
0
0
0
1
1
3
Wordline
0
0
0
0
0
0
0
0
1
0
0
4
0
0
0
0
0
0
0
0
1
0
1
5
0
0
0
0
0
0
0
0
1
1
0
6
0
0
0
0
0
0
0
0
1
1
1
7
0
0
0
0
0
0
0
1
0
0
0
8
0
0
0
0
0
0
0
1
0
0
1
9
10
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
1
1
11
0
0
0
0
0
0
0
1
1
0
0
12
0
0
0
0
0
0
0
1
1
0
1
13
0
0
0
0
0
0
0
1
1
1
0
14
0
0
0
0
0
0
0
1
1
1
1
15
0
0
0
0
0
0
1
0
0
0
0
16
0
0
0
0
0
0
1
0
•
•
•
•
0
0
0
0
0
0
1
1
1
1
1
31
.
0
•
•
.
•
•
..
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
•
•
•
•
•
0
1
1
1
1
1
1
1
1
1
1
1023
1024
•
•
•
•
0
0
0
1008
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
•
•
•
•
•
1
0
0
0
0
0
0
1
1
1
1
1039
1
0
0
0
0
0
1
0
0
0
0
1040
1
•
•
•
.
0
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
2047
3-806
I
ER-27
Blocks are numbered sequentially right to left, top to bottom. Columns within a block are numbered left to right.
I/Os within a block are numbered from 0-7 left to right.
Table 4. Block Address Bitmap
A19
A18
A17
A16
Block
Columns
0
0
0
0
0
0-511
0
0
0
1
1
512-1023
0
0
1
O·
2
1024-1535
0
0
1
1
3
1536-2047
0
1
0
0
4
2048-2559
0
1
0
1
5
2560-3071
0
1
1
0
6
3072-3583
0
1
1
1
7
3584095
1
0
0
0
8
4096-4607
1
0
0
1
9
4608-5119
1
0
1
0
10
5120-5631
1
0
1
1
11
5632-6143
1
1
0
0
12
6144-6655
1
1
0
1
13
6656-7167
1
1
1
0
14
7168-7679
1
1
1
15
7680-8191
1
Columns are numbered from left to right across the top quadrants, and left to right across the bottom quadrants.
Addresses AI5-A10 sequentially count columns. Columns are listed for block 0; other blocks are counted similarly.
Table 5. Column Address Bitmap
Column In
A1S
A14
A13
A12
A11
A10
1/00
1/0 1
1/0 2
1/03
1/04
1/05
1/06
1/07
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
0
1
2
3
4
64
65
66
67
68
128
129
130
131
132
192
193
194
195
196
256
257
258
259
260
320
321
322
323
324
384
385
386
387
388
448
449
450
451
452
1
1
1
1
1
1
1
1
1
1
0
1
190
191
254
255
•
•
•
•
•
•
•
62
63
•
126
127
•
•
•
318
319
•
382
383
•
446
447
•
510
511
REVISION HISTORY
-002 -Renamed PWD as RP# to match JEDEC conventions.
I
3-807
4
Boot Block
Components
I
SaMbii (512K X 16~ ~M }{ 8)
SmartVoltage BOOT BLOCK flASH MEMORY FAMILY
Automated Word/Byte Write and Block
Erase
- industry S~andard Command User
Interrace
- S~atus Registers
- Erase Suspend Capability
•
Intel SmartVoltage Technology
- 5V or 12V Program/Erase
- 3.3V or 5V Read Operation
- 60% Faster Typical Programming at
12V Vpp
•
Very High Performance Read
•
Low Power Consumption
•
x8/x16-Selectable Input/Output Bus
- 28F800 for High Performance 16- or
32-bit CPUs
.
[lj
Automatic Power Savings Feature
- 1 mA Typical Icc Active Current in
Static Operation
•
Optimized Array Blocking Architecture
- One 16-KB Protected Boot Block
- Two 8-KB Parameter Blocks
- One 96-KB Main Block
-Seven 128-KB Main Blocks
- Top or Bottom Boot Locations
t;;J
Reset/Deep Power-Down Input
- 0.2 /LA IccTypical
- Provides Reset for Boot Operations
o
Hardware Data Protection Feature
- Erase/Write Lockout during Power
Absolute Hardware-Protection yor Boot
Block
o
Indus~rlt-StandClrd
•
•
Software EEPROM Emulation with
Parameter Blocks
•
Extended Temperature Operation
- - 40°C to + 85°C
•
Extended Cycling Capability
- 100,000 Block Erase Cycles
(Commercial Temperature)
-10,000 Block Erase Cycles
(Extended Temperature)
[lJ
G'J SRAM-Compatible Write Interface
Transi~ions
Surface Mount
Pac~{aging
- £l0-lead TSOP
- 44-lead l?SOP: JEDEC ROM
Compatible
- <;la-lead TSOP
o Irootprint Upgradable Trom 2/4 Mbit
o ETO}{TMIV Flash Technology
290539-9
December 1994
Order Number: 290539·001
4-1
8-MBIT SmartVoltage BOOT BLOCK FAMILV
1.0 PRODUCT FAMILY OVERVIEW
This datasheet contains product preview information
about the upcoming 8-Mbit SmartVoltage boot block
flash memory component.
1.1 New Features in the SmartVoltage
Products
The new SmartVoltage boot block flash memory
family offers identical operation as the current BX/
BL 12V program products, except for the differences
listed below. All other functions are equivalent to
current products, including signatures, write commands, and pinouts.
• WP# pin has replaced a DU pin. See Table 2 and
3 for details.
• 5V Program/Erase operation has been added
that uses proven program and erase techniques
with 5V ± 10% applied to Vpp.
• Enhanced circuits optimize performance at 3.3V
Vee·
If you are designing with existing BX/BL 12V Vpp
boot block products today, you should provide the
capability in your board design to upgrade to these
new SmartVoltage products.
Follow these guidelines to ensure compatibilty:
1. Connect WP # (DU on existing products) to control signal or to Vee or GND.
2. If adding a switch on Vpp for write protection,
switch to GND for complete write protection.
3. Allow for connecting 5V to Vpp and disconnect
12V from Vpp line, if desired.
1.2 Main Features
Intel's SmartVoltage technology provides the most
flexible voltage solution in the industry. SmartVoltage provides two discrete voltage supply pins, Vee
4-2
intel®
for read operation, and Vppfor program and erase
operation. Discrete supply pins allow system designers to use the optimal voltage levels for their design.
The 28F800BV provides read capability at 3.3V or
5V, and program/erase capability at 5V or 12V.
Since many designs read from the flash memory a
large percentage of the time, 3.3V Vee operation
can provide great power savings. If read performance is an issue, however, 5V Vee provides faster
read access times. For program and erase operations, 5V Vpp operation eliminates the need for in
system voltage converters, while 12V Vpp operation
provides faster program and erase for situations
where 12V is available, such as manufacturing or
designs where 12V is in-system.
The 28F800 boot block flash memory family is a very
high-performance, 8-Mbit (8,388,608 bit) flash memory family organized as either 512 Kwords of 16 bits
each or 512 Kbytes of 8 bits each.
Separately erasable blocks, including a hardwarelockable boot block (16,384 bytes), two parameter
blocks (8,192 Bytes each) and main blocks (one
block of 98,304 bytes and seven blocks of 131,072
bytes) define the boot block flash family architecture. See Figures 5 and 6 for memory maps. Each
block can be independently erased and programmed 100,000 times at commercial temperature
and 10,000 times at extended temperature.
The boot block is located at either the top (denoted
by -T suffix) or the bottom (-8 suffix) of the address
map in order to accommodate different microprocessor protocols for boot code location. The hardware-lockable boot block provides complete code
security for the kernel code required for system initialization. Locking and unlocking of the boot block is
controlled by WP# and/or RP# (see Section 2.3 for
details).
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcontroller and the internal operation of the boot block
flash memory products. The internal Write State Machine (WSM) automatically executes the algorithms
and timings necessary for program and erase operations, including verifications, thereby unburdening
the microprocessor or microcontroller of these
8-MBIT SmartVoltage BOOT BLOCK FAMILV
tasks. The Status Register (SR) indicates the status
of the WSM and whether it successfully completed
the desired program or erase operation.
Program and Erase Automation allows program and
erase operations to be executed using an industrystandard two-write command sequence to the CUI.
Data writes are performed in word or byte increments. Each byte or word in the Flash memory can
be programmed independently of other memory locations, unlike erases, which erase all locations
within a block simultaneously.
The 8-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic, Power
Savings (APS) feature which minimizes system battery current drain, allowing for very low power designs. To provide even greater power' savings, the
boot block family includes a deep power~down mode
which minimizes power consumption by turning most
of the Flash memory's circuitry off. This mode is
controlled by the RP# pin.
Additionally, the RP# pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during system
reset and power-up/down sequences. Also, when
the Flash memory powers-up" it automatically defaults to the read array mode, but during a warm
system reset, where power continues uninterrupted
to the system components, the flash memory could
remain in a non-read mode, such as erase. Consequently, the system Reset pin should be tied to RP#
to reset the memory to normal read, mOde upon activation of the Reset pin.
For the 28F800, byte-wide or word-wide input/output is controlled by the BYTE# pin. Please see Table 3 for a detailed description of BYTE # operations, especially the usage of the DQ15/A-1 pin.
The 28F800 products are' available, in a
ROM/EPROM-compatible pinout and housed in the
44-Lead -PSOP (Plastic Small Outline) package and
the 48-Lead TSOP (Thin Small Outline, 1.2 mm
thick) package.
'
The 28F008 boot block products are available in the
40-lead TSOP.
2.0 OPERATIONAL DETAILS
products that operate only at 12V Vpp. The manufacturer and device codes are read via the CUI or by
taking the As pin to VIO. Writing 90H, to the CUI
places the device, into intelligent identifier read
mode. In this mode, Ao = 0 outputs the manufacturer's identification code and Ao = 1 outputs the device code. When BYTE# is at a logic low, only the
'lower byte of the above signatures is read and
DQ15/A-1 is a "don't care" during inteliigent identifier mode. For x8 only products only the lower byte is
read. See the table, below for product signatures. A
Read Array command must be written to the memory to return to the read array mode.
Table 1. Intelligent Identifier Table
Device ID
Product
Mfr.ID
·T
(Top Boot)
·B
(Bottom Boot)
28F800
0089H
889CH
889DH
2.2 Memory Organization
2.2.1 BLOCKING
-This product family features an asymmetrically
blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100,000 times at commercial temperature or up to 10,000 times at extended
temperature. The block sizes have been chosen to
optimize their functionality for common applications
of nonvolati.le storage. For the' address locations of
the blocks, see the meniqry maps in Figures 5 and
6.
2.2.1.1 Boot Block· 1 x 16 KB
The boot block is intended to replace a dedicated
boot PROM. in a microprocessor or microcontrollerbased system. The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T suffix) or the bottom (-B.suffix) of the address map to
accommodate different microprocessor protocols
for boot code location. ,This boot block features
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
erasure. The protection of the boot block is controlled using a combination of the Vpp, RP#, and
WP# pins, as is detailed in Section 2.3.
2.1 Intelligent Identifier
The intelligent identifiers of the SmartVoltage boot
block components are identical to the boot block
4-3
8·MBIT SmartVoltage BOOT BLOCK FAMILY
2.2.1.2 Parameter Blocks· 2 x 8 KB
The boot block architecture includes parameter
blocks to facilitate storage of frequently updated
small parameters that would normally require an
EEPROM. By using software techniques, the byterewrite functionality of EEPROMscan be emulated.
These techniques are detailed in lritel's AP-604,
"Using Intel's Boot Block Flash Memory Parameter
Blocks to Replace EEPROM." Each boot block
component contains two parameter blocks of eight
Kbytes (8,192 bytes) each. The parameter blocks
are not write-protectable.
2.2.1.3 Main Blocks· 1 x 96 KB
128 KB
+ 7x
After the allocation of address space to the boot and
parameter blocks, the remainder is divided into main
blocks for data or code storage. Each 8-Mbit device
contains one 96-Kbyte (98,304 byte) block and seven 128-Kbyte (131,072 byte) blocks. See the memory maps for each device for more information.
2.3.2 WP# = VIL FOR BOOT BLOCK
LOCKING
When WP# = VIL, the boot block is locked and any
program or erase operation to the boot block will
result in an error in the Status Register. All other
blocks remain unlocked in this condition and can be
programmed or erased normally. Note that this feature is overridden and the boot block unlocked when
RP# = VHH.
2.3.3 RP# = VHH OR WP# = VIH FOR BOOT
BLOCK UNLOCKING
Two methods can be used to unlock the boot block:
1. WP#
2. RP#
2•.3.1 Vpp = VIL FOR COMPLETE
PROTECTION
For complete write protection of all blocks in the
flash device, the Vpp programming voltage can be
held low. When Vpp is below VPPLK, any program or
erase operation will result in a error in the Status
Register.
.
4-4
VHH
If both or either of these two conditions are met, the
boot block will be unlocked and can be programmed
or erased. The truth table below clearly defines the
write protection methods available.
Table 2. Write Protection Truth Table for
SmartVoltageBoot Block Family
2.3 Boot Block Locking
The boot block family architecture features a hardware-lockable boot block so that the kernel code for
the system can be kept secure while the parameter
and main blocks are programmed and erased independently as necessary. Only the boot block can be
locked independently from the other blocks. ~
= VIH
=
Write Protection
Provided
Vpp
RP#
WP#
VIL
X
X
All Blocks Locked
~ VPPLK
VIL
X
. All Blocks Locked
(Reset)
~ VPPLK
VHH
X
All Blocks Unlocked
~
VIH
VIL
Boot Block Locked
VIH
All Blocks Unlocked
VpPLK
~ VPPLK
VIH
In the 44-lead PSOP package, the WP# pin is replaced by AlB due to a lack of available pins on that
package. For this package only, the boot block can
only be unlocked by placing 12V on RP#. All other
packages retain the WP# pin for controlling boot
block locking with a logic-level signal.
intel®
8-MBIT SmartVoltage BOOT BLOCK FAMILY
3.0 PINOUTS
2BF004
AlB
A 1S
A14
A 13
A12
An
Ag
As
WE#
RP#
Vpp
~
A6
As
A4
A3
A2
Al
2BFOO2
AlB
A 1S
A14
A 13
A12
All
Ag
As
WE#
RP#
Vpp
WP#
NC
A7
As
As
A4
A3
A2
Al
AlB
A 1S
A14
A 13
A12
All
Ag
As
WE#
RP#
Vpp
WP#
AlB
A7
As
As
A4
A3
A2
Al
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
28FOO8
4G-LEAD TSOP
10mmx20mm
TOP VIEW
A17
GND
NC
~
D0 7
DOs
DOs
D0 4
Vee
Vee
NC
D0 3
D0 2
DOl
DO O
OE#
GND
CE#
AO
2BF002
2BF004
A17
GND
NC
NC
AlO
D0 7
DOs
DOs
D0 4
Vee
Vee
NC
D0 3
D0 2
DOl
DO O
OE#
GND
CE#
AO
A17
GND
NC
NC
A 10
D0 7
DOs
DOs
D0 4
Vee
Vee
NC
D0 3
D0 2
DOl
DO O
OE#
GND
CE#
AO
290539-8
Figure 1. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications
28F400
V ••
WP#
~
A6
As
A.
A3
A2
A,
Ao
CE#
GND
OE#
DO o
DQ a
DQ,
DO.
D0 2
DQ,o
DQ.
D011
28F200
V••
WP#
NC
A7
A6
As
A.
A3
A2
A,
Ao
CE#
GND
OE#
DO o
DOa
DO,
DO.
DQ 2
DO,o
DO.
DO 11
V••
§>
17
A7
A6
As
A.
A3
A2
A,
Ao
CE#
GND
OE#
DO o
DQ a
DO,
DQ.
D0 2
DO,o
D0 3
DQ 11
2
3
4
5
6
7
8
9
PA28F800
44 Lead PSOP
0.525" x 1.110"
TOP VIEW
44
43
42
41
40
39
38
37
36
35
RP#
WE#
As
A.
A,o
A11
A'2
A'3
A,.
A,s
34
A'6
BYTE#
GND
DO,s/A.,
D0 7
DO,.
DO,
DO'3
DOs
DO'2
DO.
Vee
33
32
31
30
29
2B
27
26
25
24
23
28F200
28F400
RP#
WE#
As
A.
A,o
A11
A'2
A'3
A,.
A,s
RP#
WE#
As
A.
A,o
A11
A'2
A'3
A,.
A,s
A'6
BYTE#
GND
DO,s/A.,
D0 7
DO ,.
D06
DQ '3
DOs
DO'2
DO.
Vee
A'6
BYTE#
GND
DO,s/A.,
D0 7
DO ,.
DQ 6
DO'3
DOs
DQ '2
DO.
Vee
290539-2
NOTE:
For the 8·Mbit device, pin 2 has been changed to A18 (WP# on 2/4·Mbit). Designs planning on upgrading to the 8·Mbit
density from the 2/4·Mbit density in this package should design pin 2 to control WP # functionality at the 2/4·Mbit level
and allow for pin 2 to control A18 after upgrading to the 8·Mbit density.
Figure 2. The 44-Lead TSOP Offers a Convenient Upgrade from JEDEC ROM Standards
4·5
8-MBIT SmartVoltage BOOT BLOCK FAMILY
2SF400 2SF200
A 1S
A14
A13
A12
All
AlO
Ag
AS
NC
NC
WE#
RP#
Vpp
WP#
NC
NC
A7
6
AS
A4
A3
A2
Al
A 1S
A14
A13
A12
All
AlO
Ag
AS
NC
NC
WE#
RP#
Vpp
WP#
NC
NC
NC
A7
A6
AS
A4
A3
A2
Al
2SF200
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
lS
19
20
21
22
23
24
0
2SFSOO
4S-LEAD TSoP
12mmx 20mm
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A 16
BYTE#
GND
D01s'A_ 1
007
0014
006
0013
005
0012
,
D~
Vee
0011
003
0010
002
DOg
001
DOe
000
OE#
GND
CE#
Ao
A 16
BYTE#
GND
D01S/A_l
007
0014
006
00 13
005
0012
004
Vee
0011
003
0010
002
DOg
001
DOe
000
OE#
GND
CE#
Ao
28F400
A 16
BYTE#
GND
D01S /A_ 1
007
0014
DOe
0013
005
0012
004
Vee
0011
003
gg~o
DOg
001
DOs
000
OE#
GND
CE#
Ao
290539-3
Figure 3. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation
4-6
8-MBIT SmartVoltage BOOT BLOCK FAMILY
3.1 . Pin· Descriptions
Table 3. 2BF800 Pin Descriptions
Symbol
Type
Name and Function
Ao-A18
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
Ag
INPUT
ADDRESS INPUT: When Ag is at VHH the signature mode is accessed.
During this mode, Ao decodes between the manufacturer and device IDs.
When BYTE # is at a logic low, only the lower byte of the signatures are
read. 0015/ A-1 is a don't care in the signature mode when BYTE # is low.
000- 007
INPUT /OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE # and WE # are active. Data is
internally latched during the Write cycle. Outputs array, Intelligent Identifier
and Status Register data. The data pins float to tri-state when the chip is
de-selected or the outputs are disabled.
008- 0015
INPUT /OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE # cycle during a Program command. Data is internally latched during
the Write cycle. Outputs array data. The data pins float to tri-state when
the chip is de-selected or the outputs are disabled as in the byte-wide
mode (BYTE # = "0"). In the byte-wide mode 0015/ A-1 becomes the
lowest order address for data output on 000-007'
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels. If
CE# and RP# are high, but not at a CMOS high level, the standby current
will increase due to current flow through the CE # and RP # input stages.
OE#
INPUT
OUTPUT ENABLIE: Enables the device's outputs through the data buffers
during a read cycle. OE # is active low.
WE#
INPUT
WRITIE ENABLE: Controls writes to the Command Register and array
blocks. WE# is active low. Addresses and data are latched on the rising
edge of the WE # pulse.
RP#
INPUT
RESETIDEEP POWER-DOWN: Uses three voltage levels (VIL' VIH, and
VHH) to control two different functions: reset/deep power-down mode and
boot block unlocl(ing. It is bacl(\'1ards-compatible with the BX/BL parts.
When RP# is at logic low, the device is in reset/deep powerdown
mode, which puts the outputs at High-Z, resets the Write State Machine,
and draws minimum current.
When RP# is at logic high, the device is in standard operation. When
RP# transitions from logic-low to logic-high, the device defaults to the
read array mode.
When RP# is at VHH, the boot block is unlocked and can be
programmed or erased. This overides any control from the WP# input.
4-7
8·MBIT SmartVoltage BOOT BLOCK FAMILY
Table 3. 28F800 Pin Descriptions (Continued)
Symbol
Type
WP#
INPUT
Name and Function
WRITE PROTECT: Provides a method for unlocking the boot block in a system without
a 12V supply. WP # must be driven high or low, not left floating.
When WP# is at logic low, the boot block is locked, preventing program and erase
operations to the boot block. If a program or erase operation is attempted on the boot
block when WP# is low, the corresponding status bit (bit 4 for Program, bit 5 for Erase)
will be set in the Status Register to indicate the operation failed.
When WP# is at logic high, the boot block is unlocked and can be programmed or
erased.
NOTE:
This feature is overridden and the boot block unlocked when RP# is at VHH. See
Section 2.3 for details on write protection.
BYTE #
INPUT
BYTE# ENABLE: Controls whether the device operates in the byte-wide mode (x8) or
the word-wide mode (x16). BYTE#pin must be controlled at CMOS levels to meet the
CMOS current specification in the standby mode.
When BYTE# is at logic low, the byte-wide mode is enabled, where data is read and
programmed on OOO-OO? and 0015/ A-1 becomes the lowest order address that
decodes between the upper and lower byte. 008-0014 are tri-stated during the bytewide mode.
When BYTE # is at logic high, the word·wide mode is enabled, where data is read
and programmed on 000-0015.
Vee
DEVICE POWER SUPPLY: 5.0V ± 10%, 3.3V ± 0.3V
Vpp
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5V ± 10% or 12V ± 5% must be
applied to this pin. When Vpp < VPPLK all blocks are locked and protected against
Program and Erase commands.
GNO
GROUND: For all internal circuitry.
NC
NO CONNECT: Pin may be driven or left floating.
4-8
8-MBIT SmartVoltage BOOT BLOCK FAMILY
4.0 MEMORY MAPS
2SFSOO-B
2SFSOO·T
FFFFFH
FGOOOH
FBFFFH
FAOOOH
F9FFFH
F8000H
F7FFFH
FFFFFH
16-Kbyte BOOT BLOCK
S-Kbyte PARAMETER BLOCK
12S-Kbyte MAIN BLOCK
EOOOOH
DFFFFH
S-Kbyte PARAMETER BLOCK
12S-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
GOOOOH
BFFFFH
12S-Kbyte MAIN BLOCK
AOOOOH
9FFFFH
12S-Kbyte MAIN BLOCK
aooOOH
7FFFFH
12S-Kbyte MAIN BLOCK
60000H
5FFFFH
12S-Kbyte MAIN BLOCK
40000H
3FFFFH
12S-Kbyte MAIN BLOCK
20000H
lFFFFH
EOOOOH
DFFFFH
128-Kbyte MAIN BLOCK
GOOOOH
BFFFFH
12S-Kbyte MAIN BLOCK
AOOOOH
9FFFFH
12S-Kbyte MAIN BLOCK
80000H
7FFFFH
12S-Kbyte MAIN BLOCK
60000H
5FFFFH
12S-Kbyte MAIN BLOCK
40000H
3FFFFH
96-Kbyte MAIN BLOCK
12S-Kbyte MAIN BLOCK
20000H
lFFFFH
128-Kbyte MAIN BLOCK
OOOOOH
08000H
07FFFH
O6000H
05FFFH
04000H
03FFFH
8-Kbyte PARAMETER BLOCK
S-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
OOOOOH
290539-5
NOTE:
These memory maps apply to the 2SFSOO-T IB components in Byte-Wide (xS) mode.
Figure 4. Byte-Wide x8-Mode Memory Maps
4-9
a-MBIT SmartVoltage BOOT BLOCK FAMILY
28F800-B
28F800-T
7FFFFH
7FFFFH
12S-Kbyte MAIN BLOCK
70000H
6FFFFH
12S-Kbyte MAIN BLOCK
60000H
5FFFFH
7EOOOH
7DFFFH
7DOOOH
7CFFFH
7COOOH
7BFFFH
70000H
6FFFFH
12S-Kbyte MAIN BLOCK
60000H
5FFFFH
S-Kbyte PARAMETER BLOCK
12S-Kbyte MAIN BLOCK
50000H
4FFFFH
12S-Kbyte MAIN BLOCK
40000H
3FFFFH
12S-Kbyte MAIN BLOCK
30000H
2FFFFH
96-Kbyte MAIN BLOCK
20000H
1FFFFH
12S-Kbyte MAIN BLOCK
40000H
3FFFFH
12S-Kbyte MAIN BLOCK
30000H
2FFFFH
12S-Kbyte MAIN BLOCK
20000H
1FFFFH
12S-Kbyte MAIN BLOCK
10000H
OFFFFH
OOOOOH
S-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
12S-Kbyte MAIN BLOCK
50000H
4FFFFH
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
16-Kbyte BOOT BLOCK
12S-Kbyte MAIN BLOCK
12S-Kbyte MAIN BLOCK
S-Kbyte PARAMETER BLOCK
S-Kbyte PARAMETER BLOCK
10000H
OFFFFH
12S-Kbyte MAIN BLOCK
16-Kbyte BOOT BLOCK
OOOOOH
290539-6
Figure 5_ Word-Wide x16-Mode Memory Maps
4-10
8-MBIT SmartVoltage BOOT BLOCK FAMILY
5.0 ADDITIONAL INFORMATION
5.1 Product Information
Access Speed
Operating Temperature
T = Extended Temp
Blank = Commercial Temp
(ns, v cc
=5V)
T=Top Boot
B = Bottom Boot
Package
E=TSOP
PA = 44-Lead PSOP
TB = Ext. Temp 44-Lead PSOP
Voltage Options (Vppl vcc )
V='(50r12/3.30r5)
Product line designator
for all Intel Flash products
Architecture
B = Boot Block
C = Compact 4B-Lead TSOP
Boot Block
Density I Organization
OOX = x8-only (X = 1, 2, 4, 8) .
Xoo = x81x16 Selectable ex = 2, 4, Bl
290539-10
VALID COMBINATIONS:
Commercial
Extended
40-Lead TSOP
E2BFOOBBVT60
E2BFOOBBVB60
E2BFOOBBVT80
E2BFOOBBVBBO
E2BFOOBBVT120
E2BFOOBBVB120
44-Lead PSOP
PA2BFBOOBVT60
PA2BFBOOBVB60
PA2BFBOOBVTBO
PA2BF800BVBBO
PA2BFBOOBVT120
PA2BFBOOBVB120
4B-Lead TSOP
E2BFBOOCVT60
E2BFBOOCVB60
E2BFBOOCVTBO
E2BF800CVB80
TE2BFOOBBVTBO
TE2BFOOBBVBBO
TB2BFBOOBVTBO
TB28FBOOBVBBO
TE2BFBOOCVTBO
TE2BFBOOCVBBO
Table 4. Summary of Line Items
Name
Vpp
Vee
3_3V
5V
5V
12V
28F800BV
",
",
",
",
28FOO8BV
",
",
",
",
40-
44-
48-
Lead
TSOP
Lead
PSOP
Lead
,TSOP
0·C-+70"C
",
",
",
",
",
",
",
-40·C-+85·C
4-11
8-MBIT SmartVoltage BOOT BLOCK FAMILY
5.2 References
Order Number
Document
292130
AB-57 "Boot Block Architecture for Safe. Firmware Updates"
292154
AB-60 "2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family"
292098
AP-363 "Extended Flash BIOS Concepts for Portable Computers"
292148
AP-604 "Using Intel's Boot Block Flash Memory Parameter Blocks to Replace
EEPROM"
290530
4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290531
2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
5.3 Revision History
1-001
4-12
I Initial release of datasheet
4-MBIT (256K x 16, 512K x 8)
SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
2BF400BV-TIB, 2BF004BV-TIB, 2BF400CV-TIB
• Intel SmartVoltage Technology
- 5V or 12V Program/Erase
- 3.3V or 5V Read Operation
- 60% Faster Typical Programming at
12V Vpp
lID Extended Cycling Capability
-100,000 Block Erase Cycles
(Commercial Temperature)
- 10,000 Block Erase Cycles
(E)(tended Temperature)
• Very High Performance Read
-5V: 60/80/120 ns Max. Access Time,
30/40 ns Max. Output Enable
-3V: 110/150/180 ns Max. Access
Time, 65/90 ns Max. Output Enable
III Low Power Consumption
- Maximum 60 mA Read Current at 5V
- Maximum 30 mA Read Current at 3V
[i
Cl SRAM-Compatible Write Interface
[l]
Automatic Power Savings Feature
- 1 rnA Typical Icc Active Current in
Static Operation
(;J
Reset/Deep Power-Down Inpui:
- 0.2 /-LA IccTypical
- Provides Reset for Boot Operations
III x8/x16-Selectable Input/Output Bus
- 28F400 for High Performance 16- or
32-bii CPUs
III x8-0nly Input/Output Architecture
- 28F004 for Space-Constrained 8-bit
Applications
o Hardware Data Protection Feature
-!Erase/Write Locl(out during Power
Transitions
II Optimized Array Blocking Architecture
-
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96~KB Main Block
Three 128-KB Main Blocks
Top or Bottom Boot Locations
Absolute Hardware-Protection for Boot
Block.
III Software EEPROM Emulation with
Parameter Blocks
'
[!;)
•
•
Extended Temperature Operation
- - 40°C to + 85°C
Automated Word/Byte Write and Block
Erase
-Industry Standard Command User
Interface
- Status Registers
- Erase Suspend Capability I
Industry-Standard Surface Mount
Packaging
- 40-Lead TSOP
- 44-Lead PSOP: JEDEC ROM
Compatible
- 48-Lead TSOP
- 56-Lead TSOP
o Footprint Upgradable from 2 Mbit, and
III
to 8 Mbit
ETOXTM IV Flash Technology
290530-26
December 1994
Order Number. 29053()'001
4-13
4-MBIT (256K x 16, 512K x 8)
SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
CONTENTS
PAGE
1.0 PRODUCT FAMILY OVERViEW .... 4-15
1.1 New Features in the SmartVoltage
Products ........................... 4-15
1.2 Main Features ....................
1.3 Applications ......................
1.4 Pinouts ...........................
1.5 Pin Descriptions ..................
4-15
4-17
4-19
4-22
2.0 PRODUCT DESCRIPTION .......... 4-24
2.1 Memory Organization ............. 4-24
2.1.1 BLOCKING .................. 4-24
CONTENTS
PAGE
3.5 Power Consumption .............. 4-37
3.5.1 ACTIVE POWER ............. 4-37
3.5.2 AUTOMATIC POWER
SAVINGS ....................... 4-37
3.5.3 STANDBY POWER .......... 4-37
3.5.4 DEEP POWER·DOWN
MODE .......................... 4·37
3.6 Power·Up/Down Operation ....... 4·38
3.6.1 RP # CONNECTED TO
. SYSTEM RESET ................ 4·38
3.6.2 Vee, Vpp AND RP#
TRANSITIONS .................. 4-38
3.7 Power Supply Decoupling ......... 4-38
3.0 PRODUCT FAMILY PRINCIPLES OF
OPERATION ......................... 4-26
3.1 Bus Operations ................... 4-26
3.2 Read Operations ................. 4-26
3.2.1 READ ARRAY ............... 4-26
3.2.2 INTELLIGENT
3.7.1 Vpp TRACE ON PRINTED
CIRCUIT BOARDS .............. 4-38
4.0 ABSOLUTE MAXIMUM RATINGS .. 4-40
5.0 COMMERCIAL OPERATING
IDENTIFIERS ................... 4-28
CONDITIONS . ........................ 4-41
3.3 Write Operations ................. 4-28
5.1 Switching Vee Voltages ........... 4-41
5.2 DC Characteristics
3.3.1 COMMAND USER
INTERFACE .................... 4-28
3.3.2 STATUS REGiSTER .........
3.3.3 PROGRAM MODE ...........
3.3.4 ERASE MODE ...............
3.4 Boot Block Locking ...............
3.4.1 Vpp = VIL FOR COMPLETE
4-31
4-33
4-37
3.4.2 WP#
= VIL FOR BOOT
BLOCK LOCKING ............... 4-37
VHH OR WP# = VIH
FOR BOOT BLOCK
UNLOCKING ................... 4-37
=
(Commercial) ...................... 4-46
4-32
PROTECTION .................. 4-37
3.4.3 RP#
(Commercial) ...................... 4-42
5.3 AC Characteristics
6.0 EXTENDED OPERATING
CONDITIONS ......................... 4-56
6.1 Applying Vee Voltages .. " ........ 4-56
6.2 DC Characteristics (Extended) .... 4-57
6.3 AC Characteristics (Extended) .... 4-62
7.0 ADDITIONAL INFORMATION ....... 4-66
7.1 Ordering Information .............. 4-66
7.2 References ....................... 4-67
7.3 Revision History .................. 4-67
4-14
I
4-MBIT SmartVoltage BOOT BLOCK FAMILV
1.0 PRODUCT FAMilY OVERVIEW
This datasheet comprises the specifications for the
SmartVoltage products in the 4-Mbit boot block flash
memory family. Throughout this datasheet, the
28F400 refers to all x8/x16 4-Mbit products, while
28F004 refers to all x8 4-Mbit products. Section 1
provides an overview of the flash memory family including applications, pinouts and pin descriptions.
Sections 2 and 3 describe, in detail, the specific
memory organizations and principles of operation for
these products. Finally, Sections 4 and 5 describe
the family's operating specifications. Tables 1 and 2
provide a quick reference to each product's voltage
supply capability.
1.1 New Features in the SmartVoltage
Products
The new SmartVoltage boot block flash memory
family offers identical operation as the current
BX/BL 12V program products, except for the differences listed below. All other functions are equivalent
to current products, including signatures, write commands, and pinouts.
" WP# pin has replaced a DU pin. See Table 3 and
Table 10 for details.
o 5V Program/Erase operation has been added
that uses proven program and erase techniques
with 5V ± 10% applied to Vpp.
• Enhanced circuits .optimize performance at 3.3V
Vee·
If you are deSigning with existing BX/BL 12V Vpp
boot block products today, you should provide the
capability in your board design to upgrade to these
new SmartVoltage products.
Follow these guidelines to ensure compatibilty:
1. Connect WP # (DU on existing products) to control signal or to Vee or GND.
2. If adding a switch on Vpp for write protection,
switch to GND for complete write protection.
3. Allow for connecting 5V to Vpp and disconnect
12V from Vpp line, if desired.
1.2 Main Features
Intel's SmartVoltage technology provides the most
flexible voltage
solution
in
the
industry.
SmartVoltage provides two discrete voltage supply
pins, Vee for read operation, and Vpp for program
and erase operation. Discrete supply pins allow system designers to uSe the optimal voltage levels for
their design. The 28F400/004BV provides read capability at 3.3V or 5V, and program/erase capability
at 5V or 12V. Since many designs read from the
flash memory a large percentage of the time, 3.3V
Vee operation can provide great power savings. If
read performance is an issue, however, 5V Vee provides faster read access times. For program and
erase operations, 5V Vpp operation eliminates the
need for in system voltage converters, while 12V
Vpp operation provides faster program and erase for
situations where 12V is available, such as manufacturing or designs where 12V is in-system.
The 28F400/28F004 boot block flash memory family is a very high-performance, 4-Mbit (4,194,304 bit)
flash memory family organized as either 256 Kwords
(262,144 words) of 16 bits each or 512 Kbytes
(524,288 bytes) of 8 bits each.
Separately erasable blocks, including a hardwarelockable boot block (16,384 bytes), two parameter
blocks (8,192 Bytes each) and main blocks (one
block of 98,304 bytes and three blocks of 131,072
bytes) define the boot block flash family architecture. See Figure 7 and 8 for memory maps. Each
block can be independently erased and programmed 100,000 times at commercial temperature
or 10,000 times at extended temperature.
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 1. xS/x16 Boot Block Product Family
Product Name
Vpp
12V
28F400BV-T/B
~
-
I
I
Vee
5V
5V
~
~
I
I
3V
~
Table 2. xS-only Boot Block Product Family
Product Name
Vpp
12V
28FOO4BV-T/B
~
I
I
The boot block is located at either the top (denoted
by -T suffix) or the bottom (-B suffix) of the address
map in order to accommodate different microprocessor protocols for boot code location. The hardware-lockable boot block provides complete code
security for the kernel code required for system initialization. Locking and unlocking of the boot block is
controlled by WP# and/or RP# (see Section 3.4 for
details).
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcontroller. and the internal operation of the boot block
flash memory products. The internal Write State Machine (WSM) automatically executes the algorithms
and timings necessary for program and erase operations, including verifications, thereby unburdening
the microprocessor or micro controller of these
tasks. The Status Register (SR) indicates the status
of the WSM and whether it successfully completed
the desired program or erase operation.
Program and Erase Automation allows program and
erase operations to be executed using an industrystandard two-write command sequence to the CUI.
Data writes are performed in word (28F400 family)
or byte (28F400 or 28F004 families) increments.
Each byte or word in the Flash memory can be programmed independently of other memory locations,
unlike erases, which erase all locations within a
block simultaneously.
The 4-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power
Savings (APS) feature which minimizes system
4-16
Vee
5V
5V
~
~
I
I
3V
~
battery current drain, allowing for very low power designs. To provide even greater power savings, the
boot block family includes a deep power-down mode
which minimizes power consumption by turning most
of the Flash memory's circuitry off. This mode is
controlled by the RP # pin and its usage is discussed
in Section 3.5, along with other power consumption
issues.
Additionally, the RP # pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during system
reset and power-up/down sequences. Also, when
the Flash memory powers-up, it automatically defaults to the read array mode, but during a warm
system reset, where power continues uninterrupted
to the system components, the flash memory could
remain in a non-read mode, such as erase. Consequently, the system Reset pin should be tied to RP#
to reset the memory to normal read mode upon activation of the Reset pin.
For the 28F400, byte-wide or word-wide input/output is controlled by the BYTE # pin. Please see Table 3 for a detailed description of BYTE # operations, especially the usage of the DQ151 A -1 pin.
The 28F400 products are available in a.
ROM/EPROM-compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package, the
48-Lead TSOP (Thin Small Outline, 1.2 mm thick)
package and the 56-Lead TSOP as shown in Figure
4, 5 and 6, respectively. The 28F004 products are
available in the 40-Lead TSOP package as shown in
Figure 3.
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Refer to the DC Characteristics Table, Section 4.2
(commercial temperature) and Section 5.2 (extended temperature), for complete current and voltage
specifications. Refer to the AC Characteristics Table, Section 4.3 (commercial temperature) and Section 5.3 (extended temperature), for read, write and
erase performance specifications.
1.3 Applications
The 4-Mbit boot block flash memory family combines high-density, low-power, high-performance,
cost-effective flash memories with blocking and
hardware protection capabilities. Their flexibility and
versatility reduce costs throughout the product life
cycle. Flash memory is ideal for Just-In-Time production flow, reducing system inventory and costs,
and eliminating component handling during the production phase.
When your product is in the end-user's hands, and
updates or feature enhancements become necessary, flash memory reduces the update costs by allowing user-performed code changes instead of
costly product returns or technician calls.
The 4-Mbit boot block flash memory family provides
full-function, blocked flash memories suitable for a
wide range of applications. These applications include extended PC BIOS and ROM-able applications storage, digital cellular phone program and
data storage, telecommunication boot/firmware,
printer firmware/font storage and various other embedded applications where program and data storage are required.
tication greatens the probability that a code update
will be required after the PC is shipped. For example,
the emerging of "Plug and Play" standard in desktop
and portable PCs enables auto-configuration of ISA
and PCI add-in cards. However, since the "Plug and
Play" specification continues to evolve, a flash BIOS
provides a cost-effective capability to update existing PCs. In addition, the parameter blocks are ideal
for storing the required auto-configuration parameters, allowing you to integrate the BIOS PROM and
parameter storage EEPROM into a single component, reducing parts costs while increasing functionality.
The 4-Mbit flash memory products are also excellent
design solutions for digital cellular phone and telecommunication switching applications requiring very
low power consumption, high-performance, highdensity storage capability, modular software designs, and a small form factor package. The 4-Mbit's
Kbytes of hardware-protected boot code, four main
blocks of program code and two parameter blocks
of 8 Kbytes each for frequently updated data storage and diagnostic messages (e.g., phone numbers,
authorization codes).
Intel's boot block architecture provides a flexible
voltage solution for the different design needs of
various applications. The asymmetrically blocked
memory map allows the integration of several memory components into a single Flash device. The boot
block provides a secure boot PROM; the parameter
blocks can emUlate EEPROM functionality for parameter store with proper software techniques; and
the main blocks provide code and data storage with
access times fast enough to execute code in place,
decreasing RAM requirements.
Reprogrammable systems such as personal computers, are ideal applications for the 4-Mbit flash
memory products. Increasing software sophis-
4-17
4·MBIT SmartVoltage BOOT BLOCK FAMILV
5V
GPIO~"""J"""""!
RESET#~
1
t................ j.
A[1:18]
Intel386™EX
t--------------'
A[0:17]
CS# t-----------------------.I
CE#
RD# t----I
OE#
WR#
Intel
28F400·T
~-------------'I WE#
00[0:151
0[0:151
GPIO ____..r---....
RESET#
PWRGOOO - - - ' - - '
RP#
290530-1
Figure 1. 28F400 Interface to Intel386EXTM Microprocessor
4-18
4-MBIT SmartVoltage BOOT BLOCK FAMILV
=;
A[16:18]
r
Aa-A 15
ADDRESS
LATCHES
I--
LE
:>
Ao-A1B
8OC188EB
ALE
AD(fAD7
~
/l
'\,r- ~
ADDRESS
28F004-T
:---
LATCHES
LE
UCS#
WR#
RD#
RESIN#
Vee
~
JWK!l
L
System Reset
P1.X
P1.x
Vee
DO o-D0 7
CE#
WE#
OE#
RP#
Vpp
--..::::25.
-
WP#
290530-2
Figure 2. 28F0041nterface to Intel80C188EB 8-Bit Embedded Microprocessor
1.4 Pinouts
Intel's SmartVoltage Boot Block architecture provides upgrade paths in every package pinout to the
8-Mbit density. The 28F004 40-Lead TSOP pinout .
for space-constrained designs is shown in Figure 3.
The 28F400 44-Lead PSOP pinout follows the industry standard ROM/EPROM pinout as shown in Figure 4. For designs that require x16 operation but
have space concerns, refer to the 48-Lead pinout in
Figure 5. Furthermore, the 28F400 56-Lead TSOP
pinout shown in Figure 6 provides density upgrades
to future higher density boot block memories.
Pinouts for the corresponding 2-Mbit and 8-Mbit
components are also provided for convenient reference. 4·Mbit pinouts are given on the chip illustration
in the center, with 2-Mbit and B·Mbit pinouts going
outward from the center.
4-19
intel®
4-MBIT SmartVoltage BOOT BLOCK FAMIL V
28F008 28F002
28F002 28F008
~o
3
4
5
6
7
8
9
10
11
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
28FOO4
4O-Lead TSOP
10mmx 20 mm
TOP VIEW
~E3~~
14
15
16
17
18
19
20
A17
GND
NC
NC
AlO
D07
DOs
DOS
D04
Vee
Vee
NC
D03
D02
DOl
DOo
OE#
GND
CE#
Ao
A17
GND
NC
NC
AlO
D07
DOs
DOS
D04
Vee
Vee
NC
D03
D02
DOl
DOo
OE#
GND
CE#
AO
A17
GND
~
10
D07
DOs
D05
D~
Vee
~8e
D03
D02
DOl
DOo
OE#
GND
CE#
Ao
290530-3
NOTE:
Pin 12 is DU for BX/Bl 12V Vpp Versions.
Figure 3. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications
28F800
Vpp
28F200
A7
As
As
A.
A3
A2
A,
A.
CE#
GND
OE#
Vpp
WP#
NC
A7
As
As
A.
A3
A2
A,
A.
CE#
GND
OE#
DO.
DaB
DO,
DOg
D0 2
DO,.
Do 3
DO"
DO.
DaB
DO,
DOg
D0 2
DO 10
D0 3 ,
DO"
§>
17
28F200
Vpp
WP#
~
As
As
A.
A3
A2
A,
A.
CE#
GND
DE#
DO.
DaB
DO,
DO.
D0 2
DO,.
D0 3
DO"
1
2
3
4
5
6
7
0
44
PA28F400
44·Lead PSOP
0.525" x 1.110"
TOP VIEW
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP#
WE#
AB
Ag
A,.
A"
A'2
A'3
A,.
A,s
A,s
BYTE#
GND
DO,s/A.,
D0 7
DO,.
DOs
DO '3
DOs
DO '2
DO.
Vee
RP#
WE#
AB
Ag
AlO
A"
A'2
A'3
A,.
A,s
A,s
BYTE#
GND
DO,s/A.,
D0 7
DO,.
DOs
DO'3
DOs
DO '2
DO.
Vee
28F800
RP#
WE#.
AB
Ag
AlO
A"
A'2
A'3
A,.
A,s
A,s
BYTE#
GND
' DO,s/A.,
D0 7
DO,.
DOs
DO '3
DOs
DO'2
DO,
Vee
290530-4
NOTE:
Pin 2 is DU for BX/Bl 12V Vpp Versions, but for the B·Mbit device, pin 2 has been changed to A18 (WP# on 2/4 Mbit).
Designs planning on upgrading to the B·Mbit density from the 2/4·Mbit density in this package should design pin 2 to
control WP# functionality at the 2/4·Mbit level and allow for pin 2 to control A18 after upgrading to the B·Mbit density.
Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards
4·20
4·MBIT SmartVoltage BOOT BLOCK FAMILY
28F800
28F200
28F200
1
2
3
4
5
6
7
0
B
g
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28F400
48-LEAD TSOP
12 mm x 20 mm
TOP VIEW
A 16
A 16
BYTE#
BYTE#
GND
GND
D01!,'A_1 D01S /A_ 1
D07
D0 7
D0 14
D0 14
D06
D06
D0 13
D0 13
D05
D0 5
D012
D012
D04
004
Vee
VCC
D0 11
D0 11
D03
D0 3
D0 10
D0 10
D02
002
DOg
DOg
D0 1
D0 1
DOa
DOs
000
DOo
OE#
OE#
GND
GND
CE#
CE#
Ao
Ao
28F800
A 16
BYTE#
GND
D01S/A_1
D07
D0 14
D06
D0 13
D05
D012
D04
VCC
D0 11
D03
D0 10
D0 2
DOg
D0 1
DOa
DO o
OE#
GND
CE#
Ao
290530-5
Figure 5. The 48·Lead TSOP Offers the Smallest Form Factor for )(16 Operation
28F200
28F200
NC
NC
A 1S
A14
A 13
A12
A11
A 10
Ag
As'
NC
NC
WEll
RPII
NC
NC
Vpp
WPiI
NC
NC
A7
As
As
A4
A3
A2
A1
NC
NC
NC
A 1S
A14
A 13
A12
' A11
A 10
Ag
As
NC
NC
WEll
RPi!
NC
NC
Vpp
WPII
~
A7
6
As
A4
A3
A2
A1
NC
1
2
3
4
S
6
7
0
B
g
10
11
12
13
14
lS
16
17
16
19
20
21
22
23
24
25
26
27
28
28F400
56-Load TSOP
14mmx20mm
TOP VIEW
NC
A 16
BYTE#
GND
D0 1S/A_ 1
D07
DOg
DOs
00 13
DOs
D0 12
D0 4
Vee
V~f
o 11
Da 3
Da w
Da 2
Dag
Da 1
Da s
DO o
OEII
GND
CEil
Ao
NC
NC
NC
A 1S
BYTE#
GND
D0 1S /A_ 1
00 7
DOg
DOs
00 13
DOs
00 12
00 4
VCC
Vcc
Da11
00 3
oa 10
002
oa g
Da 1
Daa
Dao
OEII
GND
CEil
Ao
NC
NC
290530-6
NOTE:
Pin 18 is DU for BX/BL 12V Vpp Versions.
Figure 6. The 56-Lead TSOP Offers Compatibility between 2 and 4 Mbits
I
4-21
4·MBIT SmartVoltage BOOT BLOCK FAMILY
1.5 Pin Descriptions
Table 3. 28F400/004 Pin Descriptions
Symbol
Type
Name and Function
Ao~Ala
INPUT
ADDRESS INPUTS for memory addresses; Addresses are internally latched
during a write cycle.The 28F400 only has Ao-A17 pins, while the 28F004 has
Ao-Ala·
A9
INPUT
ADDRESS INPUT: When A9 is at VHH the signature mode is accessed. During this
mode, Ao decodes between the manufacturer and device IDs. When BYTE# is at
a logic. low, only the lower byte of the signatures are read. 0015/ A -1 is a don't
care in the signature mode when BYTE # is low.
DOO-DO?
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the Write cycle.
Outputs array, Intelligent Identifier and Status Register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.
DOa-D015
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the Write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE # == "0"). In the bytewide mode 0015/ A-l becomes the lowest order address for data output on
000-007. The 28F004 does not include these DQa-DQ15 pins.
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE # is active low. CE # high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow through
the CE# and RP# input stages.
OE#
INPUT
OUTPUT ENABLE: Enables the device's outputs through the data buffers during a
read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register and array blocks.
WE # is active low. Addresses and data are latched on the rising edge of the WE #
pulse.
RP#
INPUT
RESET/DEEP POWER·DOWN: Uses three voltage levels (V'L, V'H, and VHH) to
control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the 28F400BX/BL.
When RP# is at logic low, the device is in reset/deep powerdown mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.
When RP# is at logic high, the device Is In standard operation. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.
When RP# is at VHH, the boot block is unlocked and can be programmed or
erased. This overides any control from the WP# input.
4-22
4-MBIT SmartVoltage BOOT BLOCK FAMILV
Table 3. 28F400/004 Pin Descriptions (Continued)
Symbol
Type
WP#
INPUT
Name and Function
WRITE PROTECT: Provides a method for unlocking the boot block in a system without
a 12V supply. WP # must be pulled to logic low or high, not left floating.
When WP# is at logic low, the boot block is locked, preventing Program and Erase
operations to the boot block. If a Program or Erase operation is attempted on the boot
block when WP# is low, the corresponding status bit (bit 4 for Program, bit 5 for Erase)
will be set in the Status Register to indicate the operation failed.
When WP# is at logic high, the boot block is unlocked and can be programmed or
erased.
NOTE: This feature is overridden and the boot block unlocked when RP# is at VHH. See
Section 3.4 for details on write protection.
BYTE#
INPUT
BYTE# ENABLE: Not available on 28F004. Controls whether the device operates in
the byte-wide mode (x8) or .the word-wide mode (x16). BYTE # pin must be controlled at
CMOS levels to meet the CMOS current specification in the standby mode.
When BYTE # is at logic low, the byte-wide mode is enabled, where data is read and
programmed on 000- 007 and 0015/ A-1 becomes the lowest order address that
decodes between the upper and lower byte. 008-0014 are tri-stated during the bytewide mode.
When BYTE# is at logic high, the word-wide mode is enabled, where data is read
and programmed on DOO-0015.
Vee
DEVICE POWER SUPPLY: 5.0V ± 10%, 3.3V ± 0.3V
Vpp
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5V ± 10% or 12V ± 5% must be
applied to this pin. When Vpp < VPPLK all bloci Vee
Ippw
Vpp
Word/Byte
Write Current
1,4
13
30
13
25
rnA
Vpp = VpPH1 (at 5V)
Word Write in Progress
8
25
8
20
Vpp Erase
Current
1,4
13
30
10
20
8
25
5
15
50
200
30
200
p.A
Vpp = VPPH
Block Erase Suspend
in Progress
IpPE
1
= GND ± 0.2V
Vpp = VPPH2 (at 12V)
Word Write in Progress
rnA
Vpp = VPPH1 (at 5V)
Block Erase in Progress
Vpp = VPPH2 (at 12V)
Block Erase in Progress
IpPES
Vpp Erase
Suspend
Current
IRP#
RP# Boot
Block Unlock
Current
1,4
500
500
p.A
RP#
110
A9 Intelligent
Identifier
Current
1,4
500
500
p.A
A9
= VHH
= VIO
4-43
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 13. DC Characteristics (Commercial) (Continued)
Symbol
Parameter
BV-60
BV-SO
BV-120
Notes
Vee
=
Min
BV-60
BV-SO
BV-120
3.3V±O.3V
Typ
Vee
Max
Min
=
Units Test Conditions
5V±10%
Typ
Max
VID
Ag Intelligent
Identifier Voltage
11.4
12.6
11.4
12.6
VIL
Input Low Voltage
-0.5
0.8
-0.5
0.8
V
VIH
Input High
Voltage
Vcc
+0.5V
2.0
Vee
+0.5V
V
VOL
Output Low
Voltage
0.45
V
Vee = Vcc MIN
IOL = 5.8 mA
VOH1
Output High
Voltage (TTL)
V,
Vcc = Vee MIN
IOH = -2.5 mA
VOH2
Output High
Voltage
(CMOS)
V
Vcc = Vcc MIN
IOH = -2.5 mA
VPPLK
Vpp Lock-Out
Voltage
VPPH1
2.0
0.45
3
2.4
2.4
0.85Vcc
0.85Vcc
Vcc
-0.4V
Vcc
-0.4V
V
Vcc = Vcc MIN
IOH = -100/loA
0.0
1.5
0.0
1.5
V
Complete Write
Protection
Vpp (Program/
Erase Operations)
4.5
5.5
4.5
5.5
V
Vppat5V
VPPH2
Vpp (Program/
Erase Operations)
11.4
12.6
11.4
12.6
V
Vpp at 12V
VLKO
VCC Erase/Write
Lock Voltage
VHH
RP# Unlock
Voltage
8
2.0
11.4
2.0
12.6
11.4
V
12.6
V
Boot Block
Write/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, T = 25°C. These currents are valid for all
product versions (packages and speeds).
.
2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
.
3. Block erases and word/byte writes are inhibited when VPP = VPPLK, and not guaranteed in the range between VpPHl
and VPPLK.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical, in sialic operation.
6. CMOS Inputs are either Vcc ± 0.2V or GND ± O.2V. TTL Inputs are either VIL or VIH.
7. For the 28F004, address pin Al0 follows the COUT capacitance numbers.
8. For all BV parts, VLKO = 2.0V for both 3.3V and 5V operations.
4-44
4-MBIT SmartVoltage BOOT BLOCK FAMILY
M
00
~5
~
_TEsHoINTs
2.4
-->
'5
- -____
INPUT
OUTPUT
: : >TESTPOINTS
045 - - - - '
<
290530-21
Figure 13. 3.3V Inputs and Measurement Points
2.0
OUTPUT
0.8
290530-13
Figure 15. 5V Inputs and Measurement Points
Vee
OUT
OUT
290530-14
290530-22
NOTE:
NOTE:
CL = 50 pF, includes Jig Capacitance.
CL = 100 pF, includes Jig Capacitance.
Figure 14. 3.3V Standard Test Configuration
Figure 16. 5V Standard Test Configuration
OUT
290530-14
NOTE:
CL = 30 pF, includes Jig Capacitance.
Figure 17. 5V High Speed Test Configuration
4-45
4-MBIT SmartVoltage BOOT BLOCK FAMILV·
5.3 AC Characteristics
Table 14. AC Characteristics: Read Only Operations (Commercial)
BV·60
Symbol
Parameter
tAVAV
Read Cycle Time
tAVOV
Address to Output Delay
tELOV
CE# to Output Delay
tpHOV
RP# to Output Delay
Vcc
5V±5%
5V±10%
Load
30 pF
100pF
Note
Min
Max
60
50pF
Max
70
60
60
450
30
2
2
3
3
3
3
3
Min
3.3±0.3V
Min
Max
Units
110
110
800
65
ns
110
70
70
450
35
ns
ns
ns
tGLOV
OE # to Output Delay
tELOX
CE# to Output in Low Z
tEHOZ
CE# to Output in High Z
tGLOX
OE # to Output in Low Z
tGHOZ
OE # to Output in High Z
tOH
Output Hold from
Address. CE#, orOE#
change, whichever
occurs first
tELFL
tELFH
CE# Low to BYTE#
High or Low
3
5
5
7
ns
tAvFL
Address to BYTE# High
or Low
3
5
5
7
ns
tFLOV
tFHOV
BYTE# to Output Delay
3,4
60
70
110
ns
tFLOZ
BYTE# Low to Output in
HighZ
3
20
25
45
ns
4-46
0
0
20
0
25
0
0
20
0
55
ns
45
ns
0
25
0
ns
ns
ns
0
ns
4-MBIT SmartVoltage BOOT BLOCK FAMILY
5.3 AC Characteristics
Table 14. AC Characteristics: Read Only Operations (Commercial) (Continued)
BV-SO
Symbol
Parameter
BV-120
Vee
5V"± 10%
3.3V±0.3V
5V±10%
Load
100 pF
50pF
100 pF
Note
Min
Max
80
Min
Max
50pF
Max
Min
Max
Units
tAVAV
Read Cycle Time
tAvOV
Address to
Output Delay
tELOV
CE # to Output
Delay
tpHOV
RP # to Output
Delay
tGLOV
OE# to Output
Delay
2
tELOX
CE # to Output
in LowZ
3
tEHOZ
CE# to Output
in HighZ
3
tGLOX
OE # to Output
in LowZ
3
tGHOZ
OE # to Output
in HighZ
3
tOH
Output Hold
from Address,
CE#,orOE#
change,
whichever
occurs first
3
tELFL
tELFH
CE# Low to
BYTE# High or
Low
3
5
10
5
10
ns
tAVFL
Address to
BYTE # High or
Low
3
5
10
5
10
ns
tFLOV
tFHOV
BYTE# to
Output Delay
3,4
80
150
120
180
ns
tFLOZ
BYTE# Lowto
Output in High Z
3
30
60
30
60
ns
2
150
Min
3.3V±0.3V
120
ns
180
80
150
120
180
ns
80
150
120
180
ns
450
800
450
800
ns
40
90
40
90
ns
0
0
30
0
0
80
0
30
0
0
30
0
60
0
ns
80
0
30
0
ns
ns
60
0
ns
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE # may be delayed up to tCE - tOE after the falling edge of CE # without impact on tCE.
3. Sampled, but not 100% tested.
4. tFLOV, BYTE# switching low to valid output delay will be equal to tAvOV, measured from the time DQ1S/A-1 becomes
valid.
5. See 5V High Speed Test Configuration.
6. See 5V Standard Test Configuration.
7. See 3.3V Test Configuration.
4-47
4-MBIT SmartVoltage BOOT BLOCK FAMILY
, V1H
ADDRESSE S (A) XXXXXXXXX
V 1L
\I,
CE# (E) IH
Device and
Address Selection
Data
Valid
•
:;tandby
..................
..................
Address Stable
[XXXXXXXXXXXX
•
t AVAV
\
.................. ---1
V 1L
....
\I,
OE#(G) IH
V1L
~ tEHQZ
.................. ---1
....
\I,
•
WE#(W)IH
1+-+ tGLQX
V 1L
VOH
DATA (D/Q )
VOL
V
RP#(P) IH
V 1L
~
tELQX
HighZ
• tGLQV
4-
•
--
t AVQV
t pHQV
t OH .... II""
tELQV
.................
Valid Output
,\
~tGHQZ
HighZ
t\
.................
"
290530-16
Figure 18. AC Waveforms for Read Operations
V1H
ADDRESSES (~
IL
V1H
CE#
V 1L
V1H
OE#
V 1L
V1H
BYTE#
V1L
VOH
DATA (D/Q)
Standby
XXXXXXXXX
Device
Address Selection
Address Stable
4-
~LFI:+
f-.
tAVFL
...
....
... tEHQZ
...
... t GHQZ
~tGLQV
tELQV
tGLQX
~
~ELQ
t OH '"
uala Uulpul
on 000-007
Dala uulpul
>On 000-007
...
HighZ
"
-itAVQV--to
HighZ
•
VOL
HighZ
Dala Outpul
n DOa-DOl
\
I"--tFLQZ
(Doa-DOI4)
(DOI5-Al)
....
.................,.---1
~
HighZ
VOL
VOH
•
.................. ---1
L\
DATA (D/Q)
..................
.................. - lXXXXXXXXXXXX
t AVAV
(000-007)
VOH
Data
Valid
HighZ
,\
,\
....
...t AVQV
[uala Uutput
~ddress Input, ,
on 0015 D--
HighZ
VOL
290530-17
Figure 19.IEIYTE# Timing Diagram for Both Read and Write Operations with Vee at S.OV
4-48
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 15. AC Characteristics: WE#-Controlled Write Operations(1) (Commercial)
BV-60
Symbol
Parameter
Vce
SV±S%
SV±100/0
Load
30pF
100pF
Note
Min
Max
Min
3.3±O.3V
SOpF
Max
Min
Max
Units
tAVAV
Write Cycle Time
60
70
110
ns
tPHWL
RP# Setup to WE#
Going Low
450
450
800
ns
tELwL
CE # Setup to WE #
GOing Low
0
0
0
ns
tpHHWH
Boot Block Lock Setup
to WE# Going High
6.8
100
100
200
ns
tVPWH
Vpp Setup to WE#
Going High
5,8
100
100
200
ns
tAvwH
Address Setup to WE #
GOing High
3
50
50
90
ns
tOVWH
Data Setup to WE #
GOing High
4
50
50
90
ns
tWLWH
WE # Pulse Width
50
50
90
ns
twHOX
Data Hold Time from
WE# High
4
0
0
0
ns
twHAX
Address Hold Time from
WE# High
3
10
10
10
ns
tWHEH
CE # Hold Time from
WE# High
0
0
0
ns
tWHWL
WE# Pulse Width High
tWHOV1
Duration of Word/Byte
Programming Operation
tWHOV2
Duration of Erase
Operation (Boot)
tWHOV3
10
20
20
ns
2,5
6
6
6
p.s
2,5,6
0.3
0.3
0.3
s
Duration of Erase
Operation (Parameter)
2,5
0.3
0.3
0.3
s
tWHOV4
Duration of Erase
Operation (Main)
2,5
0.6
0.6
0.6
s
!aWL
Vpp Hold from Valid
SRD
5,8
0
0
0
ns
!aVPH
RP# VHH Hold from
ValidSRD
6,8
0
0
0
ns
tpHBR
Boot-Block Relock
Delay
7,8
100
100
200
ns
4-49
•
4-MBIT SmartVoltage BOOT BLOCK FAMILV
Table 15. AC Characteristics: WE#-Controlled Write Operatlons(l) (Commercial) (Continued)
BV-80
Symbol
Parameter
BV-120
vee
5V± 10%
3.3±0.3V
5V± 10%
Load
100pF
50pF
100pF
Note
Min
Max
Min
Max
Min
Max
3.3±0.3V
50pF
Min
Max
Units
tAVAV
Write Cycle Time
80
150
120
180
ns
tpHWL
RP# Setup to
WE# Going Low
450
1000
450
1000
ns
tELWL
CE# Setup to
WE# Going low
0
0
0
0
ns
tPHHWH
Boot Block Lock
SetuptoWE#
Going High
6,8
100
200
100
200
ns
tVPWH
Vpp Setup to WE #
GOing High
5,8
100
200
100
200
ns
tAVWH
Address Setup to
WE# Going High
3
50
120
50
150
ns
tDVWH
Data Setup to
WE# Going High
4
50
120
50
150
ns
tWLWH
WE# Pulse Width
50
120
50
150
ns
tWHDX
Data Hold Time
from WE # High
4
0
0
0
0
ns
tWHAX
Address Hold Time
from WE # High
3
10
10
10
10
ns
tWHEH
CE # Hold Time
from WE # High
0
0
0
0
ns
tWHWL
WE# Pulse Width
High
30
30
30
30
ns
tWHQVl
Duration of Word/
Byte Programming
Operation
2,5
6
6
6
6
I1s
tWHQV2
Duration of Erase
Operation (Boot)
2,5,6
0.3
0.3
0.3
0.3
s
tWHQV3
Duration of Erase
Operation
(Parameter)
2,5
0.3
0.3
0.3
0.3
s
tWHQV4
Duration of Erase
Operation (Main)
2,5
0.6
0.6
0.6
0.6
s
tQWL
Vpp Hold from
ValidSRD
5,8
0
0
0
0
ns
taVPH
RP# VHH Hold
from Valid SRD
6,8
0
o.
0
0
ns
tpHBR
Boot-Block Relock
Delay
7,8
4-50
100
200
100
200
ns
4-MBIT SmartVoltage BOOT BLOCK FAMILY
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during read mode.
2. The on-chip WSM completely automates Program/Erase operations; Program/Erase algorithms are now controlled internally which includes verify and margining operations.
3. Refer to command definition table for valid AIN.
4. Refer to command definition table for valid DIN.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7= 1).
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes
successfully.
7. Time tpHBR is required for successful relocking of the boot block.
B. Sampled, but not 100% tested.
9. Vpp at 5.0V.
10. Vpp at 12.0V.
11. See 5V High Speed Test Configuration.
12. See 5V Standard Test Configuration.
13. See 3.3V Test Configuration.
tWHQV1.2.3,4
V1H
DATA (O/a) ......,...:::...-+-t
V 1L
6.SV V HH
V
RP#(P) IH
V 1L
WP#
V1H
V _ _ _ _ _ _JI
1L
VpPH 2
!i1i.riliJOQI~riJi),it--""':""=::;:"'------':"---100\"FJi.JWw..7iJ'iJWw..7iJ
VpPH1
vpp(V) VPPl.KRJ..~~~****Y
V 1L JjJ~\ooOLll\OOO/
290530-18
NOTES:
1. Vee Power-Up and Standby.
2. Write program or Erase Setup Command.
3. Write Valid Address and Data (Program) or Erase Confirm Command.
4. Automated Program or Erase Delay.
5. Read Status Register Data.
6.·Write Read Array Command.
Figure 20. AC Waveforms for Write and Erase Operations (WE#-Controlled Writes)
4-51
4·MBIT SmartVoltage BOOT BLOCK FAMILY
Table 16. AC Characteristics: CE#-Controlled Write Operations(1, 13) (Commercial)
BV·60
Symbol
Parameter
Vee
5V±5%
5V±10%
Load
30pF
100pF
Note
Min
Max
Min
3.3±O.3V
50pF
Max
Min
Max
Units
tAVAV
Write Cycle Time
60
70
110
ns
tpHEl
RP# High RecoverY
to CE # Going Low
450
450
1000
ns
tWlEl
WE# SetuptoCE#
Going Low
0
0
0
ns
tpHHEH
Boot Block Lock Setup
to CE # Going High
6,8
100
100
200
ns
tVPEH
Vpp Setup to CE#
Going High
5,8
100
100
200
ns
tAVEH
Address Setup to CE#
Going High
3
50
50
90
ns
tDVEH
Data Setup to CE#
Going High
4
50
50
90
ns
tElEH
CE# Pulse Width
50
50
90
ns
tEHDX·
Data Hold Time from
CE# High
4
0
0
0
ns
tEHAX
Address Hold Time from
CE# High
3
10
10
10
tEHWH
WE # Hold Time from
CE# High
0
0
0
tEHEl
CE# Pulse Width High
10
20
20
ns
tEHOVl
Duration of Word/Byte
Programming Operation
2,5
6
6
6
I-'s
tEHOV2
Duration of Erase
Operation (Boot)
2,5,6
0.3
0.3
0.3
s
tEHOV3
Duration of Erase
Operation (Parameter)
2,5
0.3
0.3
0.3
s
tEHOV4
Duration of Erase
Operation (Main)
2,5
0.6
0.6
0.6
s
tOWl
Vpp Hold from Valid
SRD
5,8
0
0
0
ns
tOVPH
RP# VHH Hold from
ValidSRD
6,8
0
0
0
ns
tpHBR
Boot-Block Relock
Delay
7,8
4-52
ns
,
100
100
ns
200
ns
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 16. AC Characteristics: CE#-Controlled Write Operations(1,13) (Commercial) (Continued)
.
Symbol
Parameter
tAVAV
Write Cycle Time
tpHEl
BV-80
BV-120
vee
5V±10%
3.3±0.3V
5V±10%
Load
100 pF
50pF
100 pF
Note
Min
Max
Min
Max
Min
Max
3.3±0.3V
50pF
Min
Max
Units
80
150
120
180
ns
RP# High Recovery
to CE # Going Low
450
1000
450
1000
ns
tWlEl
WE# Setup to CE#
Going Low
0
0
0
0
ns
tpHHEH
Boot Block Lock
Setup toCE#
Going High
6,8
100
200
100
200
ns
tVPEH
VPP Setup to CE#
Going High
5,8
100
200
100
200
ns
tAVEH
Address Setup to
CE# Going High
3
50
120
50
150
ns
tDvEH
Data Setup to CE #
Going High
4
50
120
50
150
ns
tElEH
CE # Pulse Width
50
120
50
150
ns
tEHDX
Data Hold Time
from CE# High
4
0
0
0
0
ns
tEHAX
Address Hold Time
from CE # High
3
10
10
10
10
ns
tEHWH
WE '# Hold Time
from CE# High
0
0
0
0
ns
tEHEl
CE# Pulse Width
High
30
30
30
30
ns
tEHOV1
Duration of Word!
Byte Programming
Operation
2,5
6
6
6
6
/Ls
tEHOV2
Duration of Erase
Operation (Boot)
2,5,6
0.3
0.3
0.3
0.3
s
tEHOV3
Duration of Erase
Operation
(Parameter)
2,5
0.3
0.3
0.3
0.3
s
tEHOV4
Duration of Erase
Operation (Main)
2,5
0.6
0.6
0.6
0.6
s
tOWl
VPP Hold from Valid
SRD
5,8
0
0
0
0
ns
tovPH
RP# VHH Hold from
ValidSRD
6,8
0
0
0
0
ns
tpHBR
Boot-Block Relock
Delay
7,8
100
200
100
200
ns
NOTES:
See WE # -Controlled Write Operations for notes 1 through 12.
13. Chip-Enabie controlled writes: Write operations are driven by the valid combination of CE # and WE # in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times
should be measured relative to the CE # waveform.
4-53
4-MBIT SmartVoltage BOOT BLOCK FAMILY
t EHQV1,2,3,4
V1H
DATA (D/Q)--:..;;...-t...
V 1L
} - - - - - f o H Valid
SRD
6,5V VHH
V.
RP#(P) IH
V 1L
V1H
WP#
V
1L
_ _ _ _ _- J
290530-19
NOTES:
1, Vee Power· Up and Standby,
2, Write program or Erase Setup Command,
3, Write Valid Address and Data (Program) or Erase Confirm Command,
4, Automated Program or Erase Delay,
5, Read Status Register Data,
6, Write Read Array Command,
Figure 21. Alternate AC Waveforms for Write and Erase Operations (CE#-Controlled Writes)
4·54
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 17. Erase and Program Timings (Commercial TA = O°C to
Vpp=5V ±10%
Parameter
+ 70°C)
Vpp=12V ±5%
Vee =
3.3±O.3V
Vee=
5V±10%
Vee=
3.3±O.3V
Vee=
5V±10%
Typ
Typ
Typ
Typ
Units
0.84
0.8
0.44
0.34
s
Main Block Erase Time
2.4
1.9
1.3
1.1
s
Main Block Write Time (Byte Mode)
1.7
1.8
1.6
1.2
s
Main Block Write Time (Word Mode)
1.1
0.9
0.8
0.6
s
Byte Write Time
10
10
8
8
,...s
Word Write Time
13
13
8
8
,...s
Boot/Parameter Block Erase Time
NOTES:
, 1. All numbers are sampled, not 100% tested.
2. Contact your Intel representative for information regarding maximum Byte/Word Write specifications.
4-55
4-MBIT SmartVoltage BOOT BLOCK FAMILY
6.0 EXTENDED OPERATING CONDITIONS
Table 18. Extended Temperature and Vee Operating Conditions
Symbol
Parameter
Notes
Min
Max
Units
-40
85
·C
.-
TA
Operating Temperature
Vee
3.3V Vee Supply Voltage (± 0.3V)
1
3.0
3.6
Volts
5V Vee Supply Voltage (10%)
2
4.50
5.50
Volts
NOTES:
1. Ae specifications are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
2. 10% Vcc specifications apply to 11 0 ns and 80 ns versions in their standard test configuration.
6.1 Applying Vcc Voltages
Table 19. Vee Supply Switching Timing
Parameter
Notes
Min
T5VPH
Symbol
Vee at 4.5V (minimum) to RP# High
1
2
T3VPH
Vee at 3.0V (minimum) to RP# High
1
:2
Max
Units
,...5
,...5
NOTES:
1. The TSVPH and/or TavPH times must be strictly followed to guarantee all other read and write specifications.
2. To switch between 3.3V and 5.0V operation, the system should first transition Vee from the existing voltage to GND, and
then to the new voltage. The Vee supply voltage should not be switched when the WSM is busy.
-
7
5.0V ...................................................................,,/-._ _ _--'-_ _ _ _ _ _ _ _ __
3.3V ......·····..······...... ····..···.. ···· .... ·..·..··..
GND
V1H
RP#
V1L
/
·7~ ......···...........................................................................................
-
- t5VPH
t3VPH
---.
_
290530-12
Figure 22. Vee Supply Switching Waveform
4-56
4-MBIT SmartVoltage BOOT BLOCK FAMIL V
6.2 DC Characteristics
Table 20. DC Characteristics: Extended Temperature Operation
Symbol
Parameter
Notes
JBV-80
TBV-80
Vee = 3.3 ± 0.3V
Vee = 5V ± 10%
Min
Typ
Max
Min
Typ
Unit
Test Conditions
Max
IlL
Input Load
Current
1
± 1.0
± 1.0 !LA Vee = Vee MAX
ILO
Output Leakage
Current
1
± 10
± 10 !LA Vee = Vee MAX
Ices
Vee Standby
Current
VIN = VeeorGND
VIN = Vee
orGND
1,3
0.4
1.5
0.8
2.5
mA Vee = Vee MAX
CE# = RP# =
BYTE# = VIH
60
110
70
150
!LA Vee = Vee MAX
CE# = RP# = WP#
= Vee ± 0.2V
IceD
Vee Deep
Power-Down
Current
1
0.2
8
0.2
8
!LA Vee = Vee MAX
VIN = Vee or GND
RP# = GND ± 0.2V
leeR
Vee Read
Current for
Word or Byte
1,5,6
15
30
50
65
mA CMOS INPUTS
Vee = Vee MAX
CE = GND,
OE# = Vee
f = 10 MHz (5V),
5 MHz (3.3V)
lOUT = OmA
Inputs = GND ± 0.2V
or Vee ± 0.2V
15
30
55
70
mA TTL INPUTS
Vee = Vee MAX
CE# = VIL
OE# = VIH
f = 10 MHz (5V),
5 MHz (3.3V)
lOUT = OmA
Inputs = VIL or VIH
13
30
30
50
mA Word/Byte Program
in Progress
Vpp= VpPH1 (at 5V)
10
25
30
45
mA Word/Byte Program
in Progress
Vpp = VPPH2 (at 12V)
leew
Vee Write
Current for
Word or Byte
1,4
4-57
•
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 20. DC Characteristics: Extended Temperature Operation (Continued)
TBV-80
Symbol Parameter Notes
ICCE
Vcc Erase
Current
TBV-80
Units
Test Conditions
45
rnA
Block Erase in Progress
Vpp = VPPH1 (at 5V)
18
40
rnA
Block Erase
in Progress
Vpp = VPPH2 (at 12V)
8.0
5
12.0
rnA
CE# = VIH
Block Erase Suspend
Vpp = VPPH1 (at 5V)
Vee = 3.3 ± 0.3V
Vee = 5V ± 10%
Min
Min
Typ
Max
30
22
10
25
1,2
3
1,4
Typ
Max
13
ICCES
VccErase
Suspend
Current
Ipps
Vpp Standby
Current
1
±5
± 15
±5
± 15
/LA
Vpp:S; Vcc
IpPD
Vpp Deep
Power-down
Current
1
0.2
10
0.2
10
/LA
RP# = GND ± 0.2V
IpPR
Vpp Read
Current
1
50
200
50
200
/LA
Vpp> Vcc
Ippw.
VppWrite
Current for
Word/Byte
1,4
13
30
13
30
rnA
Vpp = VPPH
Word Write in Progress
Vpp= VPPH1 (at 5V)
8
25
8
25
rnA
Vpp = VPPH
Word Write in Progress
Vpp = VPPH2 (at 12V)
13
30
15
25
rnA
Vpp = VPPH
Block Erase in Progress
Vpp = VPPH1 (at 5V)
8
25
10
20
rnA
Vpp = VPPH
Block Erase in Progress
Vpp = VpPH2(at12V)
50
200
50
200
/LA
Vpp = VPPH
Block Erase Suspend
in Progress
IpPE
IpPES
4-58
Vpp Erase
Current
Vpp Erase
Suspend
Current
1,4
1
4·MBIT SmartVoltage BOOT BLOCK FAMILY
Table 20. DC Characteristics: Extended Temperature Operation (Continued)
TBV-80
Symbol
Parameter
Notes
TBV·80
Vee = 3.3 ± 0.3V
Vee = 5V ± 10%
Min
Min
Typ
Max
Typ
Units
Test Conditions
Max
IRP#
RP# Boot
Block Unlock
Current
1,4
500
500
p.A
RP# = VHH
VPP = 12V
lID
Ag Intelligent
1,4
500
500
p.A
Ag
=
VID
Identifier
Current
VID
Ag Intelligent
11.4
12.6
11.4
12.6
V
Identifier
Voltage
VIL
Input Low
Voltage
-0.5
0.8
-0.5
0.8
V
VIH
Input High
Voltage
2.0
Vee
±0.5V
2.0
Vee
±0.5V
V
VOL
Output Low
Voltage
0.45
V
Vee = Vee MIN
IOL = 5.8 rnA (5V)
2 rnA (3.3V)
Vpp = 12V
VOH1
Output High
Voltage (TTL)
VOH2
Output High
Voltage
(CMOS)
0.45
2.4
2.4
V
Vee = Vee MIN
IOH = -2.5 rnA
0.85 x
Vee
0.85 x
Vee
V
Vee = Vee MIN
IOH = -2.5 rnA
Vee
-O.4V
Vee
-O.4V
Vee = Vee MIN
IOH = -100 p.A
0.0
1.5
0.0
1.5
V
Complete Write
Protection
VPP (Program/
Erase Operations)
4.5
5.5
4.5
5.5
V
VPP at 5V
VPP (Program/
Erase Operations)
11.4
12.6
11.4
12.6
V
VPP at 12V
VPPLK
VPP LockOut Voltage
VPPH1
VPPH2
3
4-59
4·MBITSmartVoltage BOOT BLOCK FAMILY
Table 20. DC Characteristics: Extended Temperature Operation (Continued)
TBY·80
Symbol Parameter Notes
Yee = 3.3
Min
VLKO
VCC
Erase/Write
Lock Voltage
VHH
RP# Unlock
Voltage
8
Typ
TBY·80
± 0.3Y
Max
2.0
11.4
Yee = 5Y
Min
± 10%
Typ
11.4
Test Conditions
Max
2.0
12.6
Units
12.6
V
Vpp = 12V
V
Boot Block Write/Erase
Vpp= 12V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, T = 25°C. These currents are valid for all
product versions (packages and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block erases and word/byte writes are inhibited when Vpp = VPPLK, and not guaranteed in the range between VPPH1
and VpPLK.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical, in static operation.
6. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.
7. For the 28F004 address pin A10 follows the COUT capacitance numbers.
8. For all BV parts, VLKO = 2.0V for both 3.3V and 5.0V operations.
4-60
4-MBIT SmartVoltage BOOT BLOCK FAMILY
30
0.0
~5 .--TEsHaINTs
__
~
~---~-\'r------"
15
OUTPUT
INPUT
: : >TEsTPaINTs
045 - - - - - "
<
290530-21
Figure 23. 3.3V Inputs and Measurement Points
20
OUTPUT
0.'
290530-13
Figure 25. 5V Inputs and Measurement Points
Vee
OUT
OUT
290530-14
290530-14
NOTE:
CL = 50 pF, includes Jig Capacitance.
Figure 24. 3.3V Standard Test Configuration
NOTE:
CL = 100 pF, includes Jig Capacitance.
Figure 26. 5V Standard Test Configuration
4-61
4-MBIT SmartVoltage BOOT BLOCK FAMILY
6.3 AC Characteristics
Table 21. AC Characteristics: Read Only Operations(1) (Extended Temperature}
TBV·SO
Symbol
Parameter
Notes
Vee
=
-Min-
TBV·SO
3.3 ± 0.3V(6)
Max
110
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE # to Output Delay
tpHQV
RP# to Output Delay
tGLQV
OE # to Output Delay
2
tELQX
CE # to Output in Low Z
3
tEHQZ
CE # to Output in High Z
3
tGLQX
OE# to Output in Low Z
3
tGHQZ
OE # to Output in High Z
3
toH
Output Hold from Address
CE#. or OE# change
whichever occurs first
,
3
tELFL
tELFH
CE # Low to BYTE# High or
Low
3
tAVFL
Address to BYTE# High or Low
tFLQV
tFHQV
BYTE # to Output Delay
tFLQZ
BYTE # Low to Output in High Z
Vee
Min
3
3,4
:3
5V ± 10%(5)
Units_
Max
80
110
2
=
ns
80
ns
110
80
ns
800
450
ns
40
ns
65
0
0
55
ns
30
0
0
45
ns
30
0
0
7
ns
ns
ns
5
ns
5
ns
110 •
80
ns
45
30
ns
7
NOTES:
1. See AC Input/OLitput Reference Waveform for timing measurements.
2. OE# may be delayed up to teE - toE after the falling edge ofCE# without impact on teE,
S. Sampled. but not 100% tested.
4. tFLOV. BYTE# switching low t6 valid output delay will be equal to tAVOV. measured from the time DQ1S/A-l becomes
valid.
5. 5V Standard· Test Configuration. (Figure 26)
6. See 3.SV Standard Test Configuration. (Figure 24)
)
4·62
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 22. AC Characteristics: WE#-ControlJed Write Operations(l) (Extended Temperature)
TBV·80
Symbol
Parameter
Notes Vee
=
Min
3.3
TBV·80
± 0.3V(II) Vee = 5V ± 10%(12) Units
Max
Min
Max
tAVAV
Write Cycle Time
110
80
ns
tPHWL
RP# High Recovery
to WE # GOing Low
800
450
ns
tELWL
CE# Setup to WE# Going Low
0
0
ns
tPHHWH
Boot Block Lock Setup to WE #
Going High
6,8
200
100
ns
tVPWH
Vpp Setup to WE# Going High
5,8
200
100
ns
tAVWH
Address Setup to WE# Going
High
3
90
60
ns
tDvWH
Data Setup to WE# Going High
4
90
60
ns
tWLWH
WE# Pulse Width
90
60
ns
tWHDX
Data Hold Time from WE# High
4
0
0
ns
tWHAX
Address Hold Time from WE #
High
3
10
10
ns
tWHEH
CE# Hold Time from WE# High
0
0
ns
tWHWL
WE # Pulse Width High
20
20
ns
tWHOVl
Duration of Word/Byte Write
Operation
6
7
p.s
tWHOV2
Duration of Erase Operation (Boot)
2,5,6
0.3
0.4
s
tWHOV3
Duration of Erase Operation
(Parameter)
2,5
0.3
0.4
s
tWHOV4
Duration of Erase Operation (Main)
2,5
0.6
0.7
s
tOWL
Vpp Hold from Valid SRD
5,8
0
0
ns
tOVPH
RP# VHH Hold from Valid SRD
6,8
0
0
ns
tpHBR
Boot·Block Relock Delay
7,8
2,5
200
100
ns
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations.
3. Refer to command definition table for valid AIN.
4. Refer to command definition table for valid DIN.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7 = 1)
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes
successfully.
7. Time tpHBR is required for successful relocking of tile boot block.
8. Sampled, but not 100% tested.
9. VPP at 5.0V.
10. Vpp at 12.0V.
11. See 3.3V Standard Test Configuration.
12. See 5V Standard Test Configuration.
4-63
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 23. AC Characteristics:CE#-Controlied Write Operations(1,13)
TBV-80
Symbol
Parameter
Notes
TBV-80
Vee = 3.3 ± 0.3V(11)
Min
Max
Vee = 5V ± 10%(12)
Min
Units
Max
tAvAV
Write Cycle Time
110
80
ns
tpHEL
RP# High Recovery to
CE # Going Low
800
450
ns
tWLEL
WE# Setup to CE# Going
Low
0
0
ns
tpHHEH
Boot Block Lock Setup to
CE # Going High
6,8
200
100
ns
tVPEH
Vpp Setup to CE# Going
High
5,8
200
100
ns
tAvEH
Address Setup to CE #
Going High
90
60
ns
tDVEH
Data Setup to CE # Going
High
3
90
60
ns
tELEH
CE# Pulse Width
4
90
60
ns
tEHDX
Data Hold Time from CE #
High
0
0
ns
tEHAX
Address Hold Time from
CE# High
4
10
10
ns
tEHWH
WE# Hold Time from CE#
High
3
0
0
ns
tEHEL
CE # Pulse Width High
20
20
ns
tEHQV1
Duration of Word/Byte
Write Operation
2,5
6
7
/A-s
tEHQV2
Duration of Erase Operation
(Boot)
2,5,6
0.3
0.4
s
tEHQV3
Duration of Erase Operation
(Parameter)
2,5
0.3
0.4
s
tEHQV4
Duration of Erase Operation
(Main)
2,5
0.6
0.7
s
tQWL
Vpp Hold from Valid SRD
5,8
0
0
ns
tQVPH
RP# VHH Hold from Valid
SRD
6,8
0
0
ns
tPHBR
Boot-Block Relock Delay
7,8
200
100
ns
NOTES:
See WE # Controlled Write Operations for notes 1 through 12.
13. Chip-Enable controlled writes: Write operations are driven by the valid combination of CE # and WE # in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times
should be measured relative to the CE # waveform.
4-64
4-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 24. Extended Temperature Operations-Erase and Program Timings
Vpp=SV±10%
Vpp=12V±S%
Parameter
Vee=
3.3±0.3V
Vee=
SV± 10%
Vee =
3.3±0.3V
Vee=
SV±10%
Typ
Typ
Typ
Typ
Boot/Parameter Block
Erase Time
0.84
0.8
0.44
0.34
s
Main Block Erase Time
2.4
1.9
1.3
1.1
s
Main Block Write Time
(Byte Mode)
1.7
1.4
1.6
1.2
s
Main Block Write Time
(Word Mode)
1.1
0.9
0.8
0.6
s
Byte Write Time
10
10
8
8
p,s
Word Write Time
13
13
8
8
p,s
Units
NOTES:
1. All numbers are sampled, not 100% tested.
2. Contact your Intel representative for information regarding maximum Byie/Word Write specifications.
4-65
4-MBIT SmartVoltage BOOT BLOCK FAMILY
7.0 ADDITIONAL INFORMATION
7.1 Ordering Information
Access Speed
(ns, v cc ; 5V)
Operating Temperature
T; Extended Temp
Blank; Commercial Temp
T= Top Boot
B = Bottom Boot
Package
E;TSOP
PA ; 44-Lead PSOP
TB ; Ext. Temp 44-Lead PSOP
Voltage Options (Vpp/ Vcc )
V = (5 or 12/3.3 or 5)
Product line designator
for all Intel Flash products
Architecture
B ; Boot Block
C ; Compact 48-Lead TSOP
Boot Block
Density I Organization
OOX ; x8-only (X ; 1, 2, 4, 8)
XOO ; x8/x16 Selectable (X ; 2, 4, 8)
290530-25
VALID COMBINATIONS:
40-Lead TSOP
Commercial
E28F004BVT60
E28F004BVB60
E28F004BVT80
44-Lead PSOP
PA28F400BVT60
PA28F400BVB60
PA28F400BVT80
48-Lead TSOP
E28F400CVT60
E28F400CVB60
E28F400CVT80
56-Lead TSOP
E28F400BVT60
E28F400BVB60
E28F400BVT80
E28F004BVB80
PA28F400BVB80
E28F400CVB80
E28F400BVB80
E28F004BVT120
E28F004BVB 120
PA28F400BVT120
PA28F400BVB 120
TE28F004BVT80
TE28F004BVB80
TB28F400BVT80
TB28F400BVB80
TE28F400CVT80
TE28F400CVB80
TE28F400BVT80
TE28F400BVB80
Extended
Table 25. Summary of Line Items
Name
40Lead
TSOP
Vpp
Vee
3.3V
5V
5V
12V
28F400BV
V'
V'
V'
V'
28F004BV
V'
V'
V'
V'
4-66
44Lead
PSOP
.;::':: 'J~:I~'
:::;~:,p I:';~:;
V'
V'
48Lead
TSOP
V'
56Lead
TSOP
": I,' ".,i
_,
"ri'l
cr'",.
V'
0°_+ 70°C
-400-+85°C
.·:;:~G";:":~, ~ ::~ ;I':~';:~': :: ·:=~.1
V'
V'
V'
V'
:;
4·MBIT SmartVoltage BOOT BLOCK FAMILV
7.2 References
Order Number
Document
292130
AB-57 "Boot Block Architecture for Safe Firmware Updates"
292154
AB-60 "2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family"
292098
AP-363 "Extended Flash BIOS Concepts for Portable Computers"
292148
AP-604 "Using Intel's Boot Block Flash Memory Parameter Blocks to Replace
EEPROM"
290448
28F002/200BX-T/B 2-Mbit Boot Block Flash Memory Datasheet
290449
28F002/200BL-T/B 2-Mbit Low Power Boot Block Flash Memory Datasheet
290450
28F004/400BL-T IB 4-Mbit Low Power Boot Block Flash Memory Datasheet
290451
28F0041 400BX-T IB 4-Mbit Boot Block Flash Memory Datasheet
290531
2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290539
8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
7.3 Revision History
I
-001
I
Initial release of datasheet
4-67
2-MBIT (128K x 16, 256K x 8)
SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
2BF2008V-TI8, 2BF0028V-TI8, 2BF200CV-T18
• Intel SmartVoltage Technology
- 5V or 12V Program/Erase
- 3.3V or 5V Read Operation
- 60% Faster Typical Programming at
12V Vpp
• Extended Cycling Capability
-100,000 Block Erase Cycles
(Commercial Temperature)
-10,000 Block Erase Cycles
(Extended Temperature)
• Very High Performance Read
-5V: 60/SO/120 ns Max. Access Time,
30/40 ns Max. Output Enable
-3V: 110/150 /1S0 ns Max. Access
Time 65/90 ns Max. Output Enable
• Automated Word/Byte Write and Block
Erase
-Industry Standard Command User
Interface
- Status Registers
- Erase Suspend Capability
• Low Power Consumption
- Maximum 60 mA Read Current at 5V
- Maximum 30 mA Read Current at 3V
• SRAM-Compatible Write Interface
• Automatic Power Savings Feature
- 1 mA Typical Icc Active Current in
Static Operation
• xS/x16-Selectable Input/Output Bus
- 2SF200 for High Performance 16- or
32-bit CPUs
•
• xS-Only Input/Output Architecture
- 2SF002 for Space-Constrained S-bit
Applications
Reset/Deep Power-Down Input
- 0.2 p.A Icc Typical
- Provides Reset for Boot Operations
•
Hardware Data Protection Feature
- Erase/Write Lockout during Power
Transitions
•
Industry-Standard Surface Mount
Packaging
- 40-Lead TSOP
- 44-Lead PSOP: JEDEC ROM
Compatible
- 4S-Lead TSOP
- 56-Lead TSOP
•
Footprint Upgradable to 4 or S Mbit
•
ETOXTM IV Flash Technology
• Optimized Array Blocking Architecture
- One 16-KB Protected Boot Block
- Two S-KB Parameter Blocks
- One 96-KB Main Block
-One 12S-KB Main Blocks
- Top or Bottom Boot Locations
• Absolute Hardware-Protection for Boot
Block
• Software EEPROM Emulation with
Parameter Blocks
• Extended Temperature Operation
- - 40°C to + S5°C
290531-26
4·68
December 1994
Order Number: 290531·001
2-MBIT (128K X 16, 256K x 8)
SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
CONTENTS
PAGE
1.0 PRODUCT FAMILY OVERVIEW .... 4·70
1.1 New Features in the SmartVoltage
Products ........................... 4-70
1.2 Main Features .................... 4-70
1.3 Applications ...................... 4-72
CONTENTS
PAGE
3.5 Power Consumption .............. 4-92
3.5.1 ACTIVE POWER ............. 4-92
3.5.2 AUTOMATIC POWER
SAVINGS ....................... 4-92
3.5.3 STANDBY POWER .......... 4-92
1.4 Pinouts ........................... 4-74
3.5.4 DEEP POWER-DOWN
MODE .......................... 4-92
1.5 Pin Descriptions .................. 4-77
3.6 Power-Up/Down Operation ....... 4-93
2.0 PRODUCT DESCRiPTION .......... 4-79
2.1 Memory Organization ............. 4-79
2.1.1 BLOCKING .................. 4-79
3.6.1 RP# CONNECTED TO
SYSTEM RESET ................ 4-93
3.0 PRODUCT FAMILY PRINCIPLES OF
OPERATION ......................... 4-81
3.7 Power Supply Decoupling ......... 4-93
3.6.2 Vee, Vpp AND RP#
TRANSITIONS .................. 4-93
3.1 Bus Operations ................... 4-81
3.7.1 Vpp TRACE ON PRINTED
CIRCUIT BOARDS .............. 4-93
3.2 Read Operations ................. 4-81
4.0 ABSOLUTE MAXIMUM RATINGS .. 4-95
3.2.1 READ ARRAY ............... 4-81
3.2.2 INTELLIGENT
IDENTIFIERS ................... 4-83
5.0 COMMERCIAL OPERATING
CONDITIONS ......................... 4-96
3.3 Write Operations ................. 4-83
5.1 Switching VeeVoltages ........... 4-96
3.3.1 COMMAND USER
INTERFACE .................... 4-83
5.2 DC Characteristics
(Commercial) ...................... 4-97
3.3.2 STATUS REGiSTER ......... 4-86
5.3 AC Characteristics
(Commercial) ..................... 4-101
3.3.3 PROGRAM MODE ........... 4-87
3.3.4 ERASE MODE ............... 4-88
3.4 Boot Block Locking ............... 4-92
3.4.1 Vpp = VIL FOR COMPLETE
PROTECTION .................. 4-92
3.4.2 WP# = VIL FOR BOOT
BLOCK LOCKING ............... 4-92
3.4.3 RP# = VHH OR WP# = VIH
. FOR BOOT BLOCK
UNLOCKING ................... 4-92
I
6.0 EXTENDED OPERATING
CONDITIONS ....................... 4-111
6.1 Applying Vee Voltages ........... 4-111
6.2 DC Characteristics (Extended) ... 4-112
6.3 AC Characteristics (Extended) ... 4-117
7.0 ADDITIONAL INFORMATION .....
7.1 Ordering Information .............
7.2 References ......................
7.3 Revision History .................
4-122
4-122
4-123
4-123
4-69
2-MBIT SmartVoltage BOOT BLOCK FAMILY
1.0
2. If adding a switch on Vpp for write protection,
switch to GND for complete write protection.
PRODUCT FAMILY OVERVIEW
This datasheet comprises the specifications for the
SmartVoltage products in the 2-Mbit boot block flash
memory family. Throughout this datasheet, the
28F200 refers to all x8/x16 2-Mbit products, while
28F002 refers to all x8 2-Mbit products. Section 1
provides an overview of the flash memory family including applications, pinouts and pin descriptions.
Sections 2 and 3 describe, in detail, the specific
memory organizations and principles of operation for
these products. Finally, Sections 4 and 5 describe
the family's operating specifications. Tables 1 and 2
provide a quick reference to each product's voltage
supply capability.
1.1
New Features in the SmartVoltage
Products
.
The new SmartVoltage boot block flash memory
family offers identical operation as the current
BX/BL 12V program products, except for the differences listed below. All other functions are equivalent
to current products, including signatures, write commands, and pinouts.
• WP# pin has replaced a DU pin. See Table 3 and
Table 10 for details.
• 5V Program/Erase operation has been added
that uses proven program and erase techniques
with 5V ± 10% applied to Vpp.
• Enhanced
3.3V Vee.
circuits
optimize
performance
1.2 Main Features
Intel's SmartVoltage technology provides the
most flexible voltage solution in the industry.
SmartVoltage provides two discrete voltage supply
pins, Vee for read operation, and Vpp for program
and erase operation. Discrete supply pins allow system designers to use the optimal voltage levels for
their design. The 28F200/002BV provides read capability at 3.3V or 5V, and program/erase capability
at 5V or 12V. Since many designs read from the
flash memory a large percentage of the time,
3.3V Vee operation can provide great power savings. If read performance is an issue, however, 5V
Vee provides faster read access times. For program
and erase operations, 5V Vpp operation eliminates
the need for in system voltage converters, while
12V Vpp operation provides faster program and
erase for situations where 12V is available, such as
manufacturing or designs where 12V is in-system.
The 28F200/28F002 boot block flash memory family is a very high-performance, 2-Mbit (2,097,152 bit)
flash memory family organized as either 256 Kwords
(131,072 words) of 16 bits each or 512 Kbytes
(262,144 bytes) of 8 bits each.
at
If you are designing with existing BX/BL 12V Vpp
boot block products today, you should provide the
capability in your board design to upgrade to these
new SmartVoltage products.
Follow these guidelines to ensure compatibilty:
1. Connect WP # (DU on existing products) to control signal or to Vee or GND.
4-70
3. Allow for connecting 5V to Vpp and disconnect
12V from Vpp line, if desired.
Separately erasable blocks, including a hardwarelockable boot block (16,384 bytes), two parameter
blocks (8,192 bytes each) and main blocks (one
block of 98,304 bytes and three blocks of 131,072
bytes) define the boot block flash family architecture. See Figure 7 and 8 for memory maps. Each
block can be independently erased and programmed 100,000 times at commercial temperature
or 10,000 times at extended temperature.
infel®
2-MBIT SmartVoltage BOOT BLOCK FAMIL V
Table 1. x8/x16 Boot Block Product Family
Product Name
Vpp
12V
28F200BV-T IB
~
I
I
Vee
5V
5V
Y'
~
I
I
3V
~
Table 2. x8-only Boot Block Product Family
Product Name
Vpp
12V
28FOO2BV-T/B
~
I
I
The boot block is located at either the top (denoted
by -T suffix) or the bottom (-B suffix) of the address
map in order to accommodate different microprocessor protocols for boot code location. The hardware-lockable boot block provides complete code
security for the kernel code required for system initialization. Locking and unlocking of the boot block is
controlled by WP# and/or RP# (see Section 3.4 for
details).
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcontroller and the internal operation of the boot block
flash memory products. The internal Write State Machine (WSM) automatically executes the algorithms
and timings necessary for program and erase operations, including verifications, thereby unburdening
the microprocessor or microcontroller of these
tasks. The Status Register (SR) indicates the status
of the WSM and whether it successfully completed
the desired program or erase operation.
Program and Erase Automation allows program and
erase operations to be executed using an industrystandard two-write command sequence to the CUI.
Data writes are performed in word (28F200 family)
or byte (28F200 or 28F002 families) increments.
Each byte or word in the Flash memory can be programmed independently of other memory locations,
unlike erases, which erase all locations within a
block simultaneously.
The 2-Mbit SmartVoltage boot block flash memory
family is also designed with an Automatic Power
Savings (APS) feature which minimizes system
Vee
5V
5V
~
~
I
I
3V
~
battery current drain, allowing for very low power designs. To provide even greater power savings, the
boot block family includes a deep power-down mode
which minimizes power consumption by turning most
of the Flash memory's circuitry off. This mode is
controlled by the RP # pin and its usage is discussed
in Section 3.5, along with other power consumption
issues.
Additionally, the RP# pin provides protection
against unwanted command writes due to invalid
system bus conditions that may occur during system
reset and power-up/down sequences. Also, when
the Flash memory powers-up, it automatically defaults to the read array mode, but during a warm
system reset, where power continues uninterrupted
to the system components, the flash memory could
remain in a non-read mode, such as erase. Consequently, the system Reset pin should be tied to RP#
to reset the memory to normal read mode upon a.ctivation of the Reset pin.
For the 28F200, byte-wide or word-wide input/output is controlled by the BYTE# pin. Please see Table 3 for a detailed description of BYTE # operations, especially the usage of the OQ15/ A -1 pin.
The 28F200 products are available in a
ROM/EPROM-cqmpatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package, the
48-Lead TSOP (Thin Small Outline, 1.2 mm thick)
package and the 56-Lead TSOP as shown in Figure
4, 5 and 6, respectively. The 28F002 products are
available in the 40-Lead TSOP package as shown in
Figure 3.
4-71
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Refer to the DC Characteristics Table, Section 4.2
(commercial temperature) and Section 5.2 (extended temperature), for complete current and voltage
specifications. Refer to the AC Characteristics Table, Section 4.3 (commercial temperature) and Section 5.3 (extended temperature), for read, write and
erase performance specifications.
1.3 Applications
The 2-Mbit boot block flash memory family combines high-density, low-power, high-performance,
cost-effective flash memories with blocking and
hardware protection capabilities. Their flexibility and
versatility reduce costs throughout the product life
cycle. Flash memory is ideal for Just-In-Time production flow, reducing system inventory and costs,
and eliminating component handling during the production phase.
When your product is in the end-user's hands, and
updates or feature enhancements become necessary, flash memory reduces the update costs by allowing user-performed code changes instead of
costly product returns or technician calls.
The 2-Mbit boot block flash memory family provides
full-function, blocked flash memories suitable for a
wide range of applications. These applications include extended PC BIOS and ROM-able applications storage, digital cellular phone program and
data storage, telecommunication boot/firmware,
printer firmware/font storage and various other embedded applications where program and data storage are required.
Reprogrammable systems such as personal computers, are ideal applications for the 2-Mbit flash
memory products. Increasing software sophistica-
4-72
tion greatens the probability that a code update will
be required after the PC is shipped. For example, the
emerging of "Plug and Play" standard in desktop
and portable PCs enables auto-configuration of ISA
and PCI add-in cards. However, since the "Plug and
Play" specification continues to evolve, a flash BIOS
provides a cost-effective capability to update existing PCs. In addition, the parameter blocks are ideal
for storing the required auto-configuration parameters, allowing you to integrate the BIOS PROM and
parameter storage EEPROM into a single component, reducing parts costs while increasing functionality.
The 2-Mbit flash memory products are also excellent
design solutions for digital cellular phone and telecommunication switching. applications requiring very
low power consumption, high-performance, highdensity storage capability, modular software designs, and a small form factor package. The 2-Mbit's
blocking scheme allows for easy segmentation of
the embedded code with 16 Kbytes of hardware-protected boot code, two main blocks of program code
and two parameter blocks of 8 Kbytes each for frequently updated data storage and diagnostic messages (e.g., phone numbers, authorization codes).
Intel's boot block architecture provides a flexible
voltage solution for the different design needs of
various applications. The asymmetrically blocked
memory map allows the integration of several memory components into a single Flash device. The boot
block provides a secure boot PROM; the parameter
blocks can emulate EEPROM functionality for parameter store with proper software techniques; and
the main blocks provide code and data storage with
access times fast enough to execute code in place,
decreasing RAM requirements.
2-MBIT SmartVoltage BOOT BLOCK FAMILY
5V
f······J···········i
GPIO~
!
RESET#~..................1
A[1:17]
CS#
A[0:16]
~------------------------~I
OE#
RD#
WR#
CE#
~------------~I
0[0:15]
Intel
28F200-T
WE#
00[0:15]
GPIO _ _.r-_
RESET#
PWRGOOO
RP#
--""L....--'
290531-1
Figure 1. 28F200 Interface to Intel386EXTM Microprocessor
4-73
2-MBIT SmartVoltage BOOT BLOCK FAMILY
A[16:17]
Aa-A 15
80C188EB.
ALE
ADo-AD7
=>
r
Vi F
N-1\,
ADDRESS
LATCHES
I---
LE
~
ADDRESS
LATCHES
LE
28FOO2-T
I---
.
UCS#
WR#
RD#
RESIN#
Vee
~
r~OKQ
L
System Reset
P1X
P1X
Ao-A17
DO o-D0 7
CE#
WE#
OE#
RP#
Vee
:"-7j
V pp
-
WP#
290531-2
Figure 2. 28F0021nterface to Intel80C188EB 8-Bit Embedded Microprocessor
1.4 Pinouts
Intel's SmartVoltage Boot Block architecture provides upgrade paths in every package pinout to the
8-Mbit density. The 28F002 40-Lead TSOP pinout
for space-constrained designs is shown in Figllre 3.
The 28F200 44-Lead PSOP pinout follows the industry standard ROM/EPROM pinout as shown in Figure 4. For designs that require x16 operation but
4-74
have space concerns, refer to the 48-Lead pinout in
Figure 5. Furthermore, the 28F200 56-Lead TSOP
pinout shown in Figure 6 provides density upgrades
to future higher density boot block memories.
Pinouts for the corresponding 4-Mbit and 8-Mbit
components are also provided for convenient reference. 2-Mbit pinouts are given on the chip illustration
in the center, with 4-Mbit and 8-Mbit pinouts going
outward from the center.
intel®
2BFOOB
2BF004
A 16
A 15
A14
A13
A12
A11
A9
Aa
WE#
RP#
Vpp
WP#
Ala
A7
A6
A5
A4
A3
A2
Al
A 16
A 15
A14
A 13
A12
All
Ag
A8
WE#
RP#
Vpp
~
A7
6
A5
A4
A3
A2
Al
2-MBIT SmartVoltage BOOT BLOCK FAMILY
A 16
A 15
A14
A 13
A12
All
A9
Aa
WE#
RP#
Vpp
WP#
NC
A7
A6
A5
A4
A3
A2
Al
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
28FOO2
40·LEAD TSOP
10mmx20mm
TOP VIEW
A17
GND
NC
NC
Ala
DQ7
DOs
DQ5
DQ4
Vee
Vee
NC
DQ3
DQ2
DQ 1
DQo
OE#
GND
CE#
Ao
2BF004
2BFOOB
A17
GND
NC
NC
A 10
DQ7
DQ6
DQ 5
DQ4
Vee
Vee
NC
DQ3
DQ2
DQ 1
DQo
OE#
GND
CE#
Ao
A17
GND
NC
~
10
DQ7
DOs
DQ5
DQ4
Vee
Vee
NC
DQ3
DQ2
DQ 1
DQo
OE#
GND
CE#
Ao
290531-3
NOTE:
Pin 12 is DU for BX/Bl 12V Vpp Versions.
Figure 3. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained Applications
28F800
vpp
17
A7
As
As
A.
A3
A2
A,
Ao
CE#
GND
OE#
00 0
DOe
DO,
00 9
00 2
00'0
00 3
DO"
2BF400
vpp
WP#
6V
A7
As
As
A.
A3
A2
A,
Ao
CE#
GND
OE#
00 0
DOe
DO,
00 9
00 2
DO 'A
00 3
DO"
V pp
WP#
NC
A7
As
As
A.
A3
A2
A,
Ao
CE#
GND
OE#
00 0
DOe
DO,
00 9
00 2
00'0
00 3
DO"
10
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PA28F200
44·lead PSOP
0.525" x 1.110"
44
43
42
41
40
39
38
37
TOP VIEW
32
31
29
RP#
WE#
As
A9
A,o
A"
A'2
A'3
A,.
A,s
A,s
BYTE#
GND
DO,s/A.,
00 7
DO ,.
DOs
DO '3
DOs
DO '2
DO.
Vee
28F400
28F800
RP#
WE#
As
A9
AlO
A"
A'2
A'3
A,.
A,s
A,s
BYTE#
GND
DO,s/A.,
00 7
DO,.
DOs
00'3
DOs
00'2
DO.
Vee
RP#
WE#
As
A9
A,o
A"
A'2
A'3
A,.
A,s
A,s
BYTE#
GND
DO,s/A.,
00 7
DO,.
DOs
DO '3
DOs
00'2
DO.
Vee
290531-4
NOTE:
Pin 2 is DU for BX/Bl 12V Vpp Versions, but for the 8·Mbit device, pin 2 has been changed to A181Y'1P# on 2/4 Mbit).
Designs planning on upgrading to the 8·Mbit density from the 2/4·Mbit density in this package should design pin 2 to
control WP# functionality at the 2/4·Mbit level and allow for pin 2 to control A18 after upgrading to the 8·Mbit denSity.
Figure 4. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards
4·75
,
2-MBIT SmartVoltage BOOT BLOCK FAMILY
2BFBOO
2BF400
A 1S
A14
A13
A12
A11
A 10
Ag
Aa
NC
NC
WEI
RP#
A 1S
A14
A13
A12
A11
A 10
Ag
Aa
NC
NC
WEI
RP#
A 1S
A14
A13
A12
A11
A 10
Ag
Aa
NC
NC
WEI
RP#
WP#
WP#
NC
NC
WP#
NC
NC
NC
Ar
As
As
A4
A3
A2
A1
Vpp
~
Ar
As
As
A4
A3
A2
A1
28F400
Vpp
Vpp
~
A~
As
A4
A3
A2
A1
1
2
3
4
5
6
7
a
9
.10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
0
A 16
BYTE#
GND
A 16
BYTE#
GNO
D015 /A_ 1 001!;'A.1
007
007
00 14
00 14
006
DOs
00 13
00 13
005
DOs
0012
0012
004
004
44
28F200
48·LEAD TSOP
12mmx 20mm
TOP VIEW
43
42
41
40
39
3a
37
36
35
34
33
32
31
30
29
28
27
26
2s
Vee
00 11
003
0010
002
DOg
00 1
OOa
000
OE#
GND
CE#
Ao
Vee
00 11
003 .
00 10
002
DOg
00 1
OOa
000
OE#
GND
CE#
Ao
28F800
.A- - 1S
BYTE#
GND
001s/A_1
OOr
00 14
DOs
00 13
DOs
0012
004
Vce
0011
003
0010
002
DOg
00 1
DOS
000
OE#
GND
CE#
Ao
'---
290531-5
Figure 5. The 48-LeadTSOP Offers the Smallest Form Factor for x16 Operation
28F400
28F400
NC
NC
,A 1S
A14
A 13
A12
A11
A10
Ag
A8
NC
NC
WEll
RPII
NC
NC
NC
NC
A 1S
A14
A 13
A12
A11
A 10
Aa
As.
NC
NC
WEll
RP#
NC
NC
WPII
WPII
NC
NC
Ar
A6
As
A4 .
Aa
A2
A1
NC
Vpp
~
A~
As
A4
A3
A2
A1
NC
Vpp
1
2
3
4
5
6
r
8
9
10
11
12
13
14
15
16
17
18
19
20
21
0
22
23
24
25
26
27
28
28F200
56·LEAI) TSOP
14 mm x20mm
TOP VIEW
NC
A 16
BYTE#
GND
D0 1S/A_ 1
00 7
0014
DOe
00 13
DOs
00 12
004
Vee
Vee
00 11
003
0010
002
ooa
001
DOs
000
OEII
GND
CEil
Ao
NC
NC
NC
A 16
BYTE#
GND
oo1s/A_1
DO r
00 14
00 6
00 13
DOs
00 12
00 4
Vee
Vee
00 11
00 3
00 10
00 2
ooa
00 1
DOs
00 0
OEII
GND
CEil
Ao
NC
NC
290531-6
NOTE:
Pin 18 is DU for BX/BL 12V Vpp Versions.
Figure 6. The 56·Lead TSOP Offers Compatibility between 2 Mbits and 4 Mbits
4-76
2-MBIT SmartVoltage BOOT BLOCK FAMILV
1.5 Pin Descriptions
Table 3. 28F200/002 Pin Descriptions
Symbol
Type
Name and Function
Ao-A17
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle. The 28F200 only has Ao-A16 pins, while the 28F002 has
Ao-A17·
Ag
INPUT
ADDRESS INPUT: When Ag is at VHH the signature mode is accessed. During this
mode, Ao decodes between the manufacturer and device IDs. When BYTE# is at
a logic low, only the lower byte of the signatures are read. 00151 A-1 is a don't
care in the signature mode when BYTE# is low.
INPUTI
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the Write cycle.
Outputs array, Intelligent Identifier and Status Register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.
000-007
i
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the Write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE # = "0"). In the bytewide mode 00151 A -1 becomes the lowest order address for data output on
000-007. The 28F002 does not include these DQa-DQ15 pins.
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
ata CMOS high level, the standby current will increase due to current flow through
the CE# and RP# input stages.
OE#
INPUT
OUTPUT ENABLE: Enables the device's outputs through the data buffers during a
read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register and array blocks.
WE # is ~ctive low. Addresses and data are latched on tM rising edge of the WE #
pulse.
RP#
INPUT
RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL' VIH, and VHH) to
control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the 2BF200BX/BL.
008- 0015
When RP# Is at logic low, the device is in reset/deep powerdown mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.
When RP# is at logic high, the device is in standard operation. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.
When RP# is at VHH, the boot block is unlocked and can be programmed or
erased. This overides any control from the WP# input.
4-77
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 3. 28F200/002 Pin Descriptions (Continued)
Symbol
Type
WP#
INPUT
Name and Function
WRITE PROTECT: Provides a method for unlocking the boot block in a system without
a 12V supply. WP # must be driven to logic high or low, not left floating.
When WP# Is at logic lOW, the boot block is locked, preventing Program and Erase
operations to the boot block. If a Program or Erase operation is attempted on the boot
block when WP# is low, the corresponding status bit (bit 4 for Program, bit 5 for Erase)
will be set in the Status Register to indicate the operation failed.
When WP# is at logic high, the boot block is unlocked and can be programmed or
erased.
NOTE: This feature is overridden and the boot block unlocked when RP# is at VHH. See
Section 3.4 for details on write protection.
BYTE #
INPUT
BYTE# ENABLE: Not available on 28F002. Controls whether the device operates in
the byte-wide mode (x8) or the word-wide mode (x16). BYTE # pin must be controlled at
CMOS levels to meet the CMOS current specification in the standby mode.
When BYTE # is at logic low, the byte-wide mode is enabled, where data is read and
programmed on 000-007 and 0015/A-1 becomes the lowest order address that
decodes between the upper and lower byte. 008-0014 are tri-stated during the bytewide mode.
When BYTE # Is at logic high, the word-wide mode is enabled, where data is read
and programmed on 000-0015.
± 10%, 3.3V ± 0.3V
Vee
DEVICE POWER SUPPLY: 5.0V
Vpp
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block, a voltage either of 5V ± 10% or 12V ± 5% must be
applied to this pin. When Vpp· < VpPLK all blocks are locked and protected against
Program and Erase commands.
GNO
GROUND: For all internal circuitry.
NC
NO CONNECT: Pin may be driven or left floating.
4-78
2-MBIT SmartVoltage BOOT BLOCK FAMILY
2.0
PRODUCT DESCRIPTION
2.1 Memory Organization
2.1.1 BLOCKING
This product family features an asymmetrically
blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100,000 times at commercial temperature or up to 10,000 times at extended
temperature. The block sizes have been chosen to
optimize their functionality for common applications
of nonvolatile storage. For the address locations of
the blocks, see the memory maps in Figures 7
and 8.
2.1.1.1 Boot Block-1
x 16 KB
The boot block is intended to replace a dedicated
boot PROM in a microprocessor or microcontrollerbased system. The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map to
accommodate different microprocessor protocols
for boot code location. This boot block features
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
erasure. The protection of the boot block is controlled using a combination of the Vpp, RP#, and
WP # pins, as is detailed in Section 3.4.
2.1.1.2 Parameter Blocks-2 x 8 KB
The boot block architecture includes parameter
blocks to facilitate storage of frequently updated
small parameters that would normally require an
EEPROM. By using software techniques, the byterewrite functionality of EEPROMs can be emulated.
These techniques are detailed in Intel's AP-604,
"Using Intel's Boot Block Flash Memory Parameter
Blocks to Replace EEPROM." Each boot block
90mponent contains two parameter blocks of eight
Kbytes (8,192 bytes) each. The parameter blocks
are not write-protectable.
2.1.1.3 Main Blocks-1
x 96 KB +
1 x 128 KB
After the allocation of address space to the boot and
parameter blocks, the remainder is divided into main
blocks for data or code storage. Each 2-Mbit device
contains one 96-Kbyte (98,304 byte) block and one
128-Kbyte (131,072 byte) blocks. See the memory
maps for each device for more information.
4-79
2·MBIT SmartVoltage BOOT BLOCK FAMILY
28F200·T
1FFFFH
16-Kbyte BOOT BLOCK
1~~~~~ I--B--K-b-yt-e-p-A-RA-M-E~T-E-R-B-L-O-C-K--i
1~l}'~~~ I--B--K-b":"yt-e-p-A-RA-M-E-T-E-R-B-L-O-C-K--i
11~~~~ I - - - - - . : . . - - ' - - - - - - - - l
96-Kbyte MAIN BLOCK
o19m~
1------------1
12B-Kbyte MAIN BLOCK
OOOOOH '--_ _ _ _ _ _ _ _ _ _- '
28F200·B
1FFFFH
12B-Kbyte MAIN BLOCK
10000H
OFFFFH
96-Kbyte MAIN BLOCK
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
B-Kbyte PARAMETER BLOCK
B-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
OOOOOH
290531-7
NOTE:
Address = A[17:0). In xB operation, the least significant system address should be connected to A-1. Memory maps
are shown for x16 operation.
Figure 7. 28F200-T/B Memory Maps
28FOO2-B
28F002-T
3FFFFH
3COOOH
3BFFFH
3AOOOH
39FFFH
38000H
37FFFH
16-Kbyte BOOT BLOCK
B-Kbyte PARAMETER BLOCK
12B-Kbyte MAIN BLOCK
20000H
1FFFFH
B-Kbyte PARAMETER BLOCK
, 96-Kbyte MAIN BLOCK
20000H
1FFFFH
12B-Kbyte MAIN BLOCK
OOOOOH
3FFFFH
96-Kbyte MAIN BLOCK
08000H
07FFFH
06000H
05FFFH
04000H
03FFFH
B-Kbyte PARAMETER BLOCK
B-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
OOOOOH
290531-8
NOTE:
Address = A[1B:O).
Figure 8. 28F002·T/B Memory Maps
4-80
2-MBIT SmartVoltage BOOT BLOCK FAMILY
3.0
PRODUCT FAMILY PRINCIPLES
OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The boot block
flash family utilizes a Command User Interface (CUI)
and automated algorithms to simplify write and
erase operations. The CUI allows for 100% TTL-level control inputs, fixed power supplies during erasure
and programming, and maximum EPROM compatibility.
When Vpp < VPPLK, the device will only successfully execute the following commands: Read Array,
Read Status Register, Clear Status Register and intelligent identifier mode. The device provides standard EPROM Read, Standby and Output Disable operations. Manufacturer Identification and Device
Identification data can be accessed through the CUI
or through the standard EPROM As high voltage access (VIO) for PROM programming equipment.
The same EPROM Read, Standby and Output Disable functions are available when 5V or 12V is applied to the Vpp pin. In addition, 5V or 12V on Vpp
allows write and erase of the device. All functions
associated with altering memory contents: Write and
Erase, Intelligent Identifier Read, and Read Status
are accessed via the CUI.
The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device. The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
WE # interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.
3.1
Bus Operations
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles. These bus operations are summarized in Tables 4 and 5.
3.2 Read Operations
3.2.1 READ ARRAY
When RP# transitions from VIL (reset) to VIH, the
device will be in the read array mode and will respond to the read control inputs (CE #, address inputs) and OE#) without any commands being written to the CUI.
When the device is in the read array mode, five control signals must be controlled to obtain data at the
outputs.
• WE# must be logic high (VIH)
• CE# must be logic low (VILl
• OE must be logic low (VIL)
• RP# must be logic high (VIH)
• BYTE# must be logic high or logic low.
. In addition, the address of the desired location must
be applied to the address pins. Refer to Figure 18
and 19 for the exact sequence and timing of these
signals.
·If the device is not in read array mode, as would be
the case after a program or erase operation, the
Read Mode command (FFH) must be written to the
CUI before reads can take place.
4-81
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 4. Bus Operations for Word-Wide Mode (BYTE # = VIH)
Mode
Notes
RP#
CE#
1,2,3
OE#
WE#
A9
Ao
Vpp
DQO-1S
VIH
VIL
VIL
VIH
X
X
X
DOUT
Output Disable
VIH
VIL
VIH
VIH
X
X
X
HighZ
Standby
VIH
VIH
X
X
X
X
X
HighZ
VIL
X
X
X
X
X
X
HighZ
Read
Deep Power-Down
9
Intelligent Identifier (Mfr)
4
VIH
VIL
VIL
VIH
VID
VIL
X
0089 H
4,5
VIH
VIL
VIL
VIH
VID
VIH
X
See Table 6
VIL
X
X
X
DIN
Intelligent Identifier (Device)
Write
6,7,8
VIH
VIL
VIH
Table 5. Bus Operations for Byte-Wide Mode (BYTE# = VIL>
Mode
Read
Notes RP#
1,2,3
Output Disable
Standby
CE#
OE#
WE#
A9
Ao
A-1
Vpp
DQO-7
DQS-14
X
X
X
X
DOUT
HighZ
VIH
VIL
VIL
VIH
VIH
VIL
VIH
VIH
X
X
X
X
HighZ
HighZ
VIH
VIH
X
X
X
X
X
X
HighZ
HighZ
VIL
X
X
X
X
X
X
X
HighZ
HighZ
VIH
VID
VIL
X
X
89H
HighZ
VID VIH
X
X
See Table 6
HighZ
X
X
DIN
HighZ
Deep Power-Down
9
Intelligent Identifier (Mfr)
4
VIH
VIL
VIL
4,5
VIH
VIL
VIL
VIH
6,7,8
VIH
VIL
VIH
VIL
Intelligent Identifier
(Device)
Write
X
X
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Refer to DC Characteristics.
X can be VIL, VIH for control pins and addresses, VPPLK or VPPH for Vpp.
See DC Characteristics for VPPLK, VPPH1, VpPH2, VHH, VID voltages.
Manufacturer and Device codes may also be accessed via a CUI write sequence, Al-A16 = X, Al-A17
See Table 6 of Device IDs.
Refer to Table 7 for valid DII\I during a Write operation.
Command writes for Block Erase or Word/Byte Write are only executed when Vpp = VpPH1 or VpPH2.
To Write or Erase the boot block, hold RP# at VHH or WP# at VIH.
RP# must be at GND ± O.2V to meet the maximum deep power-down current specified.
4-82
= X.
2-MBIT SmartVoltage BOOT BLOCK FAMIL V
3.2.2 INTELLIGENT IDENTIFIERS
The intelligent identifiers of the SmartVoltage boot
block components are identical to the boot block
products that operate only at 12V Vpp. The manufacturer and device codes are read via the CUI or by
taking the Ag pin to VID. Writing 90H to the CUI
places the device into intelligent identifier read
mode. In this mode, Ao = 0 outputs the manufacturer's identification code and Ao = 1 outputs the device code. When 8YTE# is at a logic low, only the
lower byte of the above Signatures is read and
DQ15/ A-1 is a "don't care" during intelligent identifier mode. For x8 only products only the lower byte is
read. See the Table 6 below for product signatures.
A Read Array command must be written to the memory to return to the read array mode.
Table 6. Intelligent Identifier Table
Device 10
Register, Erase and Program (summarized in Tables
7 and 8). For Read commands, the CUI points the
read path at either the array, the intelligent identifier,
or the Status Register depending on the command
received. For Program or Erase commands, the CUI
informs the Write State Machine (WSM) that a write
or erase has been requested. During the execution
of a Program command, the WSM will control the
programming sequences and the CUI will only respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the WSM has completed its task, it will set the
WSM Status bit to a "1," which will also allow the
CUI to respond to its full command set. Note that
after the WSM has returned control to the CUI, the
CUI will stay in the current command state until it
receives another command.
Table 7. Command Set Codes and
Corresponding Device Mode
Product
Mfr. 10
-T
(Top Boot)
-B
(Bottom Boot)
Command Codes
00
Invalid Reserved
28F200
0089H
2274H
2275 H
10
Alternate Program Set-Up
28F002
89H
7CH
7DH
20
Erase Set-Up
40
Program Set-Up
3.3 Write Operations
3.3.1 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface between the microprocessor and the internal chip controller. Commands are written to the CUI
using standard microprocessor write timings. The
available commands are Read Array, Read Intelligent Identifier, Read Status Register, Clear Status
Device Mode
50
Clear Status Register
70
Read Status Register
90
Intelligent Identifier
80
Erase Suspend
DO
Erase Resume/Erase Confirm
FF
Read Array
4-83
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 8. Command Bus Definitions
Command
Read Array
Intelligent Identifier
Notes
First Bus Cycle
Second Bus Cycle
Oper
Addr
Data
8
Write
X
FFH
Oper
Addr
Data
1
Write
X
90H
Read
IA
110
Read Status Register
2,4
Write
X
70H
Read
X
SRD
Clear Status Register
3
Write
X
50H
Write
WA
40H
Write
WA
WD
Word/Byte Write
Alternate Word/Byte Write
6,7
Write
WA
10H
Write
WA
WD
Block Erase/Confirm
6,7
Write
BA
20H
Write
BA
DOH
5
Write
X
BOH
Write
X
DOH
Erase Suspend/Resume
ADDRESS
BA = Block Address
IA = Identifier Address
WA = Write Address
X = Don't Care
DATA
SRD = Status Register Data
110 = Identifier Data
WD = Write Data
NOTES:
1. Bus operations are defined in Tables 4 and 5.
2. IA = Identifier Address: AO = 0 for manufacturer code, AO = 1 for device code.
3. SRD-Data read from Status Register.
4. 110 = Intelligent Identifier Data. Following the Intelligent Identifier command, two Read operations access manufacturer
and device codes.
.
5. BA = Address within the block being erased.
j). WA = Address to be written. WD = Data to be written at location WD.
7. Either 40H or 10H commands is valid.
8. When writing commands to the device, the upper data bus [008-00151 = X (28F200 only) which is either VIL or VIH, to
minimize current draw.
4-84
2-MBIT SmartVoltage BOOT BLOCK FAMILY
3.3.1.1 Command Function Description
Device operations are selected by writing specific
commands into the CUI. Tables 7 and 8 define the
available commands.
Invalid/Reserved
These are unassigned commands and should not be
used. Intel reserves the right to redefine these codes
for future functions.
Read Array (FFH)
This single write cycle command points the
read path at the array. If the host CPU performs a
CE # fOE # -controlled Read immediately following
two-write sequence that started the WSM, then the
device will output Status Register contents. If the
Read Array command is given after the Erase Setup
command, the device will reset to read th~ array. A
two Read Array command sequence (FFH) is required to reset to Read Array after the Program Setup command.
a
Intelligent Identifier (90H)
After this command is executed, the CUI points the
output path to the intelligent identifier circuits. Only
intelligent identifier values at addresses 0 and 1 can
be read (only address Ao is used in this mode, all
other address inputs are ignored).
Read Status Register (70H)
This is one of the two commands that is executable
while the WSM is operating. After this command is
written, a read of the device will output the contents
of the Status Register, regardless of the address
presented to the device.
The device automatically enters this mode after program or erase has completed.
'
Clear Status Register (SOH)
The WSM can only set the Program Status and
Erase Status bits in the Status Register to "1," it
cannot clear them to "0."
the WSM does not know when the host CPU has
read the Status Register, it would not know when to
clear the status bits. Secondly, if the CPU is programming a string of bytes, it may be more efficient
to query the Status Register after programming the
string. Thus, if any errors exist while programming
the string, the Status Register will return the accumulated error status.
Program Setup (40H or 10H)
This command simply sets the CUI into a state such
that the next write will load the Address and Data
registers. After this command is executed, the outputs default to the Status Register. A two Read Array command sequence (FFH) is required to reset to
Read Array after the Program Setup command.
Program
The second write after the Program Setup command, will latch addresses and data. Also, the CUI
initiates the WSM to begin execution of the program
algorithm. The device outputs Status Register data
when OE# is enabled. A Read Array command is
required after programming, to read array data.
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command.
No other action is taken. If the next command is not
an Erase Confirm command, then the CUI will set
both the Program Status and Erase Status bits of the
Status Register to a "1," place the device into the
Read Status Register state, and wait for another
command.
Erase Confirm (DOH)
If the previous command was an Erase Setup command, then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status Register and
Erase Suspend commands. While the WSM is executing, the device will output Status Register data
when OE# is toggled low. Status Register data can
only be updated by toggling either OE# or CE# low.
Two reasons exist for operating the Status Register
in this fashion. The first is synchronization. Since
4-85
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Erase Suspend (BOH)
This command is only valid while the WSM is executing an Erase operation, and therefore will only be
responded to during an Erase operation. After this
command has been executed, the CUI will set an
output that directs the WSM to suspend Erase operations, and then respond only to Read Status Register or to the Erase Resume commands. Once the
WSM has reached the Suspend state, it will set an
output into the CUI which allows the CUI to respond
to the Read Array, Read Status Register, and Erase
Resume commands. In this mode, the CUI will not
respond to any other commands. The WSM will also
set the WSM Status bit to a "1." The WSM will continue to run, idling in the SUSPEND state, regardless
of the state of all input control pins except RP#,
which will immediately shut down the WSM and the
remainder of the chip, if it is made active. During a
Suspend operation, the data and address latches
will remain closed, but the address pads are able to
drive the address into the read path.
Erase Resume (DOH)
This command will cause the CUI to clear the Suspend state and clear the WSM Status Bit to a "0,"
but only if an Erase Suspend command was previ.ously issued. Erase Resume will not have any effect
under any other conditions.
3.3.2 STATUS REGISTER
The device contains a Status Register which may be
read to determine when a Program or Erase operation is complete, and whether that operation completed successfully. The Status Register may be
read at any time by writing the Read Status command to the CUI. After writing this command, all subsequent Read operations output data from the
Status Register until another command is written to
the CUI. A Read Array command must be written to
the CUI to return to the read array mode.
4-86
The Status Register bits are output on 00[0:7],
whether the device is in the byte-wide (x8) or wordwide (x16) mode. In the word-wide mode the upper
byte, 00[8:15], is set to OOH during a Read Status
command. In the byte-wide mode, 00[8:14] are tristated and 0015/ A-1 retains the low order address
function.
Important: The contents of the Status Register are
latched on the falling edge of OE# or CE#, whichever occurs last in the read cycle. This prevents possible bus errors which might occur if the contents of
the Status Register change while reading the Status
Register. CE # or OE # must be toggled with each
subsequent status read, or the completion of a Program or Erase operation will not be evident from the
Status Register.
When the WSM is active, this register will indicate
the status of the WSM, and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation.
3.3.2.1 Clearing the Status Register
The wslv1 sets status bits "3" through "7" to "1,"
and clears bits "6" and "7" to "0," but cannot clear
status bits "3" through "5" to "0." Bits 3 through 5
can only be cleared by the controlling CPU through
the use of the Clear Status Register command.
These bits can indicate various error conditions. By
allowing the system software to control the resetting
of these bits, several operations may be performed
(such as cumulatively programming several bytes or
erasing multiple blocks in sequence). The Status·
Register may then be read to determine if an error
occurred during that programming or erasure series.
This adds flexibility to the way the device may be
programmed or erased. To clear the Status Register, the Clear Status Register command is written to
the CUI. Then, any other command may be issued to
the CUI. Note, again, that before a read cycle can be
initiated, a Read Array command must be written to
the CUI to specify whether the read data is to come
from the Memory Array, Status Register, or Intelligent Identifier.
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 9. Status Register Bit Definition
WSMS
ESS
ES
7
6
5
I
DWS
4
I
VPPS
3
I
R
R
2
R
o
SR.7 = WRITE STATE MACHINE STATUS
(WSMS)
1 = Ready
0= Busy
NOTES:
Write State Machine bit must first be checked to
determine Byte/Word program or Block Erase
completion, before the Program or Erase Status bits are
checked for success.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
o = Erase in Progress/Completed
When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to "1." ESS bit
remains set to "1" until an Erase Resume command is
issued.
SR.5 = ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Erase
When this bit is set to "1," WSM has applied the
maximum number of erase pulses to the block and is still
unable to successfully verify block erasure.
SRA = PROGRAM STATUS
1 = Error in Byte/Word Program
o = Successful Byte/Word Program
When this bit is set to "1," WSM has attempted but failed
to program a byte or word.
SR.3 = VppSTATUS
1 = Vpp Low Detect, Operation Abort
0= VppOK
The Vpp Status bit, unlike an A/D converter, does not
provide continuous indication of Vpp level. The WSM
interrogates Vpp level only after the Byte Write or Erase
command sequences have been entered, and informs
the system if Vpp has not been switched on. Vpp Status
bit is not guaranteed to report accurate feedback
between VpPLK and VpPH·
SR.2-SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
These bits are reserved for future use and should be
masked out when polling the Status Register.
3.3.3 PROGRAM MODE
Programming is executed using a two-write sequence. The Program Setup command is written to
the CUI followed by a second write which specifies
the address and data to be programmed. The WSM
will execute a sequence of internally timed events
to:
1. Program the desired bits of the addressed memory word or byte.
2. Verify that the desired bits are sufficiently programmed,
Programming of the memory results in specific bits
within a byte or word being changed to a "0."
If the user attempts to program" 1"s, there will be no
change of the memory cell content and no error occurs.
Similar to erasure, the Status Register indicates
whether programming is complete. While the program sequence is executing, bit 7 of the Status Register is a "0." The Status Register can be polled by
toggling either CE# or OE# to determine when the
program sequence is complete. Only the Read
Status Register command is valid while programming is active.
When programming is complete, the status bits,
which indicate whether the Program operation was
successful, should be checked. If the programming
operation was unsuccessful, bit 4 of the Status
4-87
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Register is set to a "1" to indicate a Program Failure. If bit 3 is set to a "1," then Vpp was not within
acceptable limits, and the WSM did not execute the
programming sequence. If the program operation
fails, bit 4 of the Status Register will be set within
1.5 ms as determined by the timeout of the WSM.
stead, bit 5 of the Status Register is set to a "1" to
indicate an Erase Failure, and bit 3 is set to a "1',' to
identify that Vpp supply voltage was not within acceptable limits. If the erase operation fails, bit 5 of
the Status Register will be set within 1.5 ms as determined by the timeout of the WSM.
The Status Register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however,
reads from the Memory Array, Status Register, or
Intelligent Identifier cannot be accomplished until
the CUI is given the Read Array command.
The Status Register should be cleared before attempting the next operation. Any CUI instruction can
follow after erasure is completed; however, reads
from the Memory Array, Status Register, or Intelligent Identifier cannot be accomplished until the CUI
is given the Read Array command.
3.3.4 ERASE MODE
3.3.4.1 Suspending and Resuming Erase
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI, along with the addresses identifying the block
to be erased. These addresses are latched internally
when the Erase Confirm command is issued. Block
erasure results in all bits within the block being set to
"1."
The WSM will execute a sequence of internally
timed events to:
1. Program all bits within the block to "0." ,
2. Verify that all bits within the block are sufficiently
programmed to "0."
3. Erase all bits within the block.
4. Verify that all bits within the block are sufficiently
erased.
Since an erase operation requires on the order of
seconds to complete, an Erase Suspend command
is provided to allow erase-sequen~ interruption in
, order to read data from another block of the memory. Once the erase sequence is started, writing the
Erase Suspend command to the CUI requests that
the WSM pause the erase sequence at a predetermined point in the erase algorithm. The Status Register must then be read to determine if the erase
operation has been suspended.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register command.
While the erase sequence is executing, bit 7 of the
Status Register is a "0."
During erase suspend mode, the chip can go into a
pseudo-standby mode by taking CE# to VIH, which
reduces active current draw.
When the Status Register indicates that erasure is
complete, the status bits, which indicate whether the
Erase operation was successful, should be checked.
If the Erase operation was unsuccessful, bit 5 of the
Status Register will be set to a "1", indicating an
Erase Failure. If Vpp was not within acceptable limits
after the Erase Confirm command is issued, the
WSM will not execute an erase sequence; in-
To resume the erase operation, the chip must be
enabled by taking CE# to VIL, then issuing the
Erase Resume command. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of a standard erase operation, the
Status Register must be read, cleared, and the next
instruction issued in order to continue.
4-88
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Bus
Operation
Command
Write
Comments
Setup
Program
Data = 40H
Addr = Word/Byte to Program
Program
Data = Data to Program
Addr = Location to Program
Write
Read
Status Register Data
Toggle CE# or OE#
to Update SRD.
Standby
Check SR.7
1 =WSM Ready
o =WSM Busy
Repeat for subsequent Word/Byte Writes.
SR Full Status Check can be done after each Word/Byte
Write, or after sequence of Word/Byte Writes.
Write FFH after the last write operation to reset device to
read array mode.
a
Word/Byte Program
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read Status Register
Data (See Above)
Command
Comments
Standby
Check SR.3
1 = V pp Low Detect
Standby
Check SR.4
1 = V pp Byte Program Error
VppRange Error
Byte Program
Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State Machine.
SR.4 is only clear by the Clear Status Register Command,
in cases where multiple bytes are programmed before full
status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
290531-9
Figure 9. Automated Word/Byte Programming Flowchart
I
4-89
2-MBIT SmartVoltage BOOT BLOCK FAMIL V
Star-rt_~)
Bus
Operation
(,-_ _
Command
Comments
Write
Erase Setup
Data = 20H
Addr = Within Block to be Erased
Write
Erase
Confirm
Data = DOH
Addr = Within Block to be Erased
Read
Status Register Data
Toggle CE# or OE#
to Update Status Register
Standby
Check SR.?
1 =WSM Ready
o =WSM Busy
Repeat for subsequent block erasures.
Full Status Check can be done after each block erase,
or after a sequence of block erasures.
Write FFH after the last operation to reset device to Read
Array mode.
Block Erase
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Standby
Check SR.3
1 = Vpp Low Detect
Standby
Check SR.4,S
Both 1 = Command
Sequence Error
Standby
CheckSR.S
1 = Block Erase Error
VppRange Error
Command Sequence
Error
Block Erase
Error
SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
SR.S is only clear by the Clear Status Register Command, in
cases where multiple blocks are erase before full status is checked.
If error is detected, clear the Status Register before attempting
retry or other error recovery.
290S31-10
Figure 10. Automated Block Erase Flowchart
4-90
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Bus
Operation
Write
Command
Erase
Suspend
Comments
Data = BaH
Addr = X
Read
Status Register Data
Toggle CE# or OE#
to Update SRD.
Addr=X
Standby
Check SR.7
1 =WSM Ready
a =WSM Busy
Standby
Check SR.6
1 = Erase Suspended
a = Erase Completed
Write
Read Array
Erase Completed
Read
Write
Data = FFH
Addr = X
Read Array Data from Block
Other Than the One Being
Erased
Erase Resume
Data = DOH
Addr=X
Erase Resumed
290531-11
Figure 11. Erase Suspend/Resume Flowchart
I
4-91
2-MBIT SmartVoltage BOOT BLOCK FAMILV
3.4 Boot Block Locking
The boot block family architecture features a hardware-lockable boot block so that the kernel code for
the system can be kept secure while the parameter
and main blocks are programmed and erased independently as necessary. Only the boot block can be
locked independently from the other blocks.
Table 10. Write Protection Truth Table for
SmartVoltage Boot Block Family
Vpp
Write Protection
Provided
RP# WP#
X
X
All Blocks Locked
~ VPPLK
VIL
X
All Blocks Locked (Reset)
~ VPPLK
VHH
X
All Blocks Unlocked
VIL FOR COMPLETE PROTECTION
~ VPPLK
VIH
VIL
Boot Block Locked
For complete write protection of all blocks in the
flash device, the Vpp programming voltage can be
held low, When Vpp is belowVpPLK, any program or
erase operation will result in a error in the Status
Register.
~ VPPLK
VIH
VIH
All Blocks Unlocked
3.4.1 Vpp
=
3.4.2 WP# = VIL FOR BOOT BLOCK
LOCKING
When WP# = VIL, the boot block is locked and any
program or erase operation to the boot block will
result in an error in the Status Register. All other
blocks remain unlocked in this condition and can be
programmed or erased normally. Note that this feature is overridden and the boot block unlocked when
RP# = VHH.
VIL
3.5.2 AUTOMATIC POWER SAVINGS (APS)
Automatic Power Savings (APS) is a low-power feature during active mode of operation. The boot block
flash memory family incorporates Power Reduction
Control (PRC) circuitry which allows the device to
put itself into a low current state when it is not being
accessed. After data is read from the memory array,
PRC logic controls the device's power consumption
by entering the APS mode where typical Icc current
is less than 1 mAo The device stays in this static
state with outputs valid until a new location is read.
3.5.3 STANDBY POWER
3.4.3 RP# = VHH OR WP# = VIH FOR BOOT
BLOCK UNLOCKING
Two methods can be used to unlock the boot block:
1. WP# = VIH
2. RP# = VHH
If both or either of these two conditions are met, the
boot block will be unlocked and can be programmed
or erased. The truth table, Table 10, clearly defines
the write protection methods.
3.5 Power Consumption
3.5.1 ACTIVE POWER
With CE# at a logic-low level and RP# at a logichigh level, the device is placed in the active mode.
Refer to the DC Characteristics table for Icc current
values.
4-92
With CE# at a logic-high level (VIH), and the CUI in
read mode, the memory is placed in standby mode.
The standby operation disables much of the device's circuitry and substantially reduces device
power consumption. The outputs (00[0:15] or
00[0:7]) are placed in a high-impedance state independent of the status of the OE # signal. When CE #
is at logic-high level during erase or program functions, the devices will continue to perform the erase
or program function and consume erase or program
active power until erase or program is completed.
3.5.4 DEEP POWER-DOWN MODE
The SmartVoltage boot block family supports a low
typical Icc in deep power-down mode, which turns
off all circuits to save power. This mode is activated
by the RP# pin when it is at a logic-low (GND
±0.2V.) (Note: BYTE# pin must be at CMOS levels
to meet the. ICCD specification.)
2-MBIT SmartVoltage BOOT BLOCK FAMILV
During read modes, the RP# pin going low deselects the memory and places the output drivers in a
high impedance state. Recovery from the deep power-down state, requires a minimum access time of
tpHQV. (See AC Characteristics table)
During erase or program modes, RP# low will abort
either erase or program operations, but the memory
contents are no longer valid as the data has been
corrupted by the RP# function. As in the read mode
above, all internal circuitry is turned off to achieve
the power savings.
RP#. transitions to VIL, or turning power off to the
device will clear the Status Register.
3.6 Power-Up/Down Operation
The device offers protection against accidental
block erasure or programming during power transitions. Power supply sequencing is not required,
since the device is indifferent as to which power supply, Vpp or Vee, powers-up first. The CUI is reset to
the read mode after power-up, but the system must
drop CE # low or present a new address to ensure
valid data at the outputs.
A system designer must guard against spurious
writes when Vee voltages are above VLKO and Vpp
is active. Since both WE# and CE# must be low for
a command write, driving either signal to VIH will inhibit writes to the device. The CUI architecture provides an additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device. is also disabled until RP# is brought to
VIH, regardless of the state of its control inputs. By
holding the device in reset (RP# connected to system PowerGood) during power,up/down, invalid bus
conditions during power-up can be masked, providing yet another level of memory protection.
3.6.1 RP# CONNECTED TO SYSTEM RESET
The use of RP# during system reset is important
with automated write/ erase devices because the
system expects to read from the flash memory when
it comes out of reset. If a CPU reset occurs without a
flash memory reset, proper CPU initialization would
not occur because the flash memory may be providing status information instead of array data. Intel's
flash memories allow proper CPU initialization following a system reset by connecting the RP# pin to
the same RESET # signal that resets the system
CPU.
3.6.2 Vee, Vpp AND RP# TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by Vpp or CE# transitions or WSM actions. Its default state upon powerup, after exit from deep power-down mode, or after
Vee transitions above VLKO (Lockout voltage), is
read array mode.
After any Word/Byte Write or Block Erase operation
is complete and even after Vpp transitions down to
VPPLK, the CUI must be reset to read array mode via
the Read Array command if accesses to the flash
memory are desired.
3.7 Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling methods. System
designers should consider three supply current issues:
1. Standby current levels (Ices)
2. Active current levels (leeR)
3. Transient peaks produced by falling and rising
edges of CE#.
Transient current magnitudes depend on the device
outputs' capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 /LF ceramic capacitor
connected between each Vee and GND, and between its Vpp and GND. These high frequency, inherently low inductance capacitors should be placed
as close as possible to the package leads.
3.7.1 Vpp TRACE ON PRINTED CIRCUIT
BOARDS
Designing for in-system writes to the flash memory
requires special consideration of the Vpp power supply trace by the printed circuit board designer. The
Vpp pin supplies the flash memory cells current for
programming and erasing. One should use similar
trace widths and layout considerations given to the
Vee power supply trace. Adequate Vpp supply
traces, and decoupling capacitors placed adjacent
to the component, will decrease spikes and overshoots.
4-93
2·MBIT SmartVoltage BOOT BLOCK FAMILY
Guide to Subsequent Tables
Operating Conditions
Table
Number
Name
Commercial Temperature
Commercial Operating Conditions
11
29
Vee Supply Switching Timing
12
29
DC Characteristics
13
30
14
34
AC Characteristics-WE # Controlled Write Operations
15
37
AC Characteristics-CE # Controlled Write Operations
16
40
Erase and Program Timings
17
43
Extended Operating Conditions
18
44
Vee Supply Switching Timing
19
44
AC Characteristics-Read Only Operations
Extended Temperature
Page
..
DC Characteristics (Vee = 5V or 3.3V)
20
45
AC Characteristics-Read Only Operations
21
50
AC Characteristics-WE # Controlled Write Operations
22
51
AC Characteristics-CE # Controlled Write Operations
23
53
Erase and Program Timings
24
54
Summary of Line Items
25
55
NOTE:
In the following tables, the topmost heading lists the line items to which the specifications in that
column apply. For space considerations, the line items have been abbreviated as shown in the following table. See Section 7.1 for more information on product naming and line items.
Abbreviation
Applicable Product Names
BV-60
E28F200BV-T60, E28F200BV-B60, E28F002BV-T60, E28F002BV-B60,
E28F200CV-T60, E28F200CV-B60, PA28F200BV-T60, PA28F200BV-B60
BV-80
E28F200BV-T80, E28F200BV-B80, E28F002BV-T80, E28F002BV-B80,
E28F200CV-T80,E28F200CV-B80,PA28F200BV-T80,PA28F200BV-B80
BV-120
E28F002BV-T120, E28F002BV-B120, PA28F200BV-T120, PA28F200BV-B120
TBV-80
TE28F200BV-T80, TE28F200BV-B80, TE28F002BV-T80, TE28F002BV-B80,
TE28F200CV-T80, TE28F200CV-B80, TB28F200BV-T80, TB28F200BV-B80
4-94
2-MBIT SmartVoltage BOOT BLOCK FAMILY
4.0
ABSOLUTE MAXIMUM RATINGS*
Commercial Operating Temperature
During Read .................... O°C to
+ 70°C
During Block Erase
and Word/Byte Write ............. O°C to
+ 70°C
Temperature Bias ............... -10°C to 80°C
Extended Operating Temperature
During Read ................. - 40°C to
+ 85°C
During Block Erase
and Word/Byte Write ........ - 40°C to
+ 85°C
+ 85°C
+ 125°C
Temperature Under Bias ....... -40°C to
Storage Temperature ....... '" -65°C to
Voltage on Any Pin
(except Vee, Vpp, Ag and RP#)
with Respect to GND ........ - 2.0V to + 7.0V(2)
Voltage on Pin RP# or Pin Ag
with Respect to GND ...... - 2.0V to
+ 13.5V(2,3)
Vpp Program Voltage with Respect
to GND during Block Erase
and Word/Byte Write ..... -2.0V to
+ 14.0V(2,3)
Vee Supply Voltage
with Respect to GND ........ - 2.0V to
+ 7.0V(2)
Output Short Circuit Current ............. 100 mA(4)
NOTICE: This document contains information on
products in the design phase of development. Do not
finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you
have the latest data sheet before finalizing a deSign.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
NOTES:
1. Operating temperature is for commercial product
defined by this specification.
2. Minimum DC voltage is -0.5V on input/output
pins. During transitions, this level may undershoot to -2.0V for periods <20 ns. Maximum
DC voltage on input/output pins is Vee + 0.5V
which, during transitions, may overshoot to Vee.
+ 2.0V for periods <20 ns.
3. Maximum DC voltage on Vpp may overshoot to
+ 14.0V for periods < 20 ns. Maximum DC voltage on RP# or Ag may overshoot to 13.5V for
periods < 20 ns.
4. Output shorted for no more than one second. No
more than one output shorted at a time.
5. 10%
Vee
specifications
reference
the
28F200/002BV-60 in their standard test configurations, and 28F200/002BV-80/120.
6. 5%
Vee
specifications
reference
the
28F200/002BV-60 in their high speed test configuration.
4-95
2-MBIT SmartVoltage BOOT BLOCK FAMIL V
5.0 COMMERCIAL OPERATING CONDITIONS
Table 11. Commercial Temperature and Vee Operating Conditions
Symbol
Parameter
Notes
TA
Operating Temperature
Vee
3.3V Vee Supply Voltage (± 0.3V)
Min
Max
Units
0
70
DC
3.0
3.6
Volts
5V Vee Supply Voltage (10%)
1
4.50
5.50
Volts
5V Vee Supply Voltage (5%)
2
4.75
5.25
Volts
NOTES:
1. 10% Vee specifications apply to the 60, 80 and 120 ns product versions in their standard test configuration.
2. 5% Vee specifications apply to the 60 ns versions in their high speed test configuration.
5.1
Switching Vcc Voltages
Table 12. Vee Supply Switching Timing
Symbol
Parameter
Notes
Min
Max
Unit
T5VPH
Vee at 4.5V (minimum) to RP# High
1
2
p.s
T3VPH
Vee at 3.0V (minimum) to RP# High
1
2
p.s
NOTES:
1. The T5VPH and/or T 3VPH times must be strictly followed to guarantee all other read and write specifications.
2. To switch between 3.3V and 5.0V operation, the system should first transition Vee from the existing voltage to GND, and
then to the new voltage. The Vee supply voltage should not be switched when the WSM is busy.
:.:~ :::::::::::::::::::::::::::::::::::::::::::::::::::::::)7 ....................................................................................................
GND
v"
RP#
V1L
/ .:;:'"
=l
/
290531-12
Figure 12. Vee Supply Switching Waveform
4·96
2-MBIT SmartVoltage BOOT BLOCK FAMILV
5.2 DC Characteristics
Table 13. DC Characteristics (Commercial)
Symbol
Parameter
BV-60
BV-80
BV-120
BV-60
BV-80
BV-120
Vee = 3.3±O.3V
Vee = 5V±10%
Notes
Min
Typ
Max
Min
Typ
Units
Test Conditions
Max
IlL
Input Load
Current
1
±1.0
± 1.0
/LA Vee = Vee MAX
VIN = Vee or GND
ILO
Output Leakage
Current
1
±10
± 10
/LA Vee = Vee MAX
VIN = Vee or GND
Ices
. Vee Standby
Current
1,3
0.4
1.5
0.8
2.0
mA Vee = Vee MAX
CE# = RP# =
BYTE# = WP# = VIH
60
110
50
130
/LA Vee = Vee MAX
CE# = RP# =
Vee ± 0.2V
IceD
Vee Deep
Power-Down
Current
1
0.2
8
0.2
8
/LA Vee = Vee MAX
VIN = Vee orGND
RP# = GND ± 0.2V
leeR
Vee Read
Current for
Word or Byte
1,5,6
15
30
50
60
mA CMOS INPUTS
Vee = Vee MAX
CE# = GND
OE# = Vee
f = 10MHz (5V),
5 MHz (3.3V)
lOUT = 0 mA
Inputs = GND ± 0.2V
or Vee ± 0.2V
15
30
55
65
mA TTL INPUTS
Vee = Vee MAX
CE# = VIL
OE# = VIH
f = 10 MHz (5V),
5 MHz (3.3V)
lOUT = OmA
Inputs = VIL or VIH
13
30
30
50
mA Word Write in Progress
Vpp = VpPH1 (at 5V)
10
25
30
45
mA Word Write in Progress
Vpp = VpPH2(at12V)
leew
Vee Write
Current for
Word or Byte
1,4
4-97
•
2·MBIT SmartVoltage BOOT BLOCK FAMILV
Table 13. DC Characteristics (Commercial) (Continued)
~ymbol
Parameter
BV·60
BV·SO
BV·120
BV·60
BV·SO
BV·120
Vee = 3.3±O.3V
Vee = 5V±10%
Notes
Min
ICCE
VCC Erase
Current
Typ
Max
13
Test Conditions
Typ
Max
30
18
35
mA Block Erase in Progress
Vpp = VPPH1 (at 5V)
10
25
18
30
rnA Block Erase in Progress
Vpp = VPPH2 (at 12V)
1,2
3
8.0
5
10
rnA CE# = VIH
Block Erase Suspend
1,4
Min
Units
ICCES
Vce Erase
Suspend
Current
IpPS
VppStandby
Current
1
±5
±15
±5
± 10
IpPD
Vpp Deep
Power-Down
Current
1
0.2
10
0.2
5.0
/LA RP#= GND ± 0.2V
IpPR
Vpp Read
Current
1
50
200
30
200
/LA Vpp> Vee
Ippw
Vpp Word/Byte
Write Current
1,4
13
30
13
25
rnA Vpp = VPPH1 (at 5V)
Word Write in Progress
8
25
8
20
Vpp = VPPH2 (at 12V)
Word Write in Progress
13
30
10
20
rnA Vpp = VPPH1 (at 5V)
Block Erase in Progress
8
25
5
15
Vpp = VPPH2 (at 12V)
Block Erase in Progress
50
200
30
200
/LA Vpp = VPPH
Block Erase Suspend
in Progress
IpPE
Vpp Erase
Current
1,4
s:
Vee
IpPES
Vpp Erase
Suspend
Current
IRP#
RP# Boot Block
Unlock Current
1,4
500
500
/LA RP# = VHH
liD
Ag Intelligent
Identifier Current
1,4
500
500
/LA Ag = VID
4-98
1
/LA Vpp
2·MBIT SmartVoltage BOOT BLOCK FAMIL V
Table 13. DC Characteristics (Commercial) (Continued)
Symbol
Parameter
BV·SO
BV·SO
BV·120
BV·SO
BV·SO
BV·120
Vee = 3.3±O.3V
Vee = 5V±100/0
Notes
Min
Max
Min
11.4
12.6
11.4
12.6
V
Input Low
Voltage
-0.5
0.8
-0.5
0.8
V
VIH
Input High
Voltage
2.0
Vee
+0.5V
2.0
Vee
+0.5V
V
VOL
Output Low
Voltage
0.45
V
Vee = Vee MIN
IOL = 5.8mA
VOH1
Output High
Voltage (TTL)
VOH2
Output High
Voltage
(CMOS)
VID
Ag Intelligent
Identifier Voltage
VIL
VpPLK
Vpp Lock-Out
Voltage
VPPH1
Typ
0.45
3
Typ
Units Test Conditions
Max
2.4
2.4
V
Vee = Vee MIN
IOH = -2.5 mA
0.85 Vee
0.85 Vee
V
Vee = Vee MIN
IOH = -2.5 mA
Vee
-O.4V
Vee
:-O.4V
Vee = Vee MIN
IOH = -100 p.A
0.0
1.5
0.0
1.5
V
Complete Write
Protection
Vpp
(Program/Erase
Operations)
4.5
5.5
4.5
5.5
V
Vpp at 5V
VpPH2
Vpp
(Program/Erase
Operations)
11.4
12.6
11.4
12.6
V
Vpp at 12V
VLKO
Vee Erase/Write
Lock Voltage
VHH
RP# Unlock
Voltage
8
2.0
11.4
2.0
12.6
11.4
V
12.6
V
Boot Block
Write/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0V, T = 25"e. These currents are valid for all
product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block erases and word/byte writes are inhibited when Vpp = VPPLK, and not guaranteed in the range between VPPH1
and VpPLK.
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical, in static operation.
6. eMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TTL Inputs are either VIL or VIH.
7. For the, 28F002, address pin A10 follows the eOUT capacitance numbers.
8. For all BV parts, VLKO = 2.0V for both 3.3V and 5V operations.
4-99
2·MBIT SmartVoltage BOOT BLOCK FAMILY
~: = : : y 5 +-TE~~OINTS
2.0
--1<5
OUTPUT
ompUT
0.'
290531-13
290531-21
Figure 13. 3.3V Inputs and Measurement Points
Figure 15. 5V Inputs and Measurement Points
Vee
9890
OUT
DEVICE
UNDER
TEST
OUT
773.0
290531-14
290531-22
NOTE:
CL = 50 pF, includes Jig Capacitance
Figure 14. 3.3V Standard Test Configuration
NOTE:
CL = 100 pF, includes Jig Capacitance
Figure 16. 5V Standard Test Configuration
Vee
5850
OUT
394n
290531-14
NOTE:
CL = 30 pF, includes Jig Capacitance
Figure 17. 5V High Speed Test Configuration
4-100
2-MBIT SmartVoltage BOOT BLOCK FAMILY
5.3 AC Characteristics
Table 14. AC Characteristics: Read Only Operations (Commercial)
BV-GO
5V±5%
Vee
30pF
Load
Symbol
Parameter
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
Note
5V±10%
Min
3.3±0.3V
100 pF
Max
60
Min
50 pF
Max
70
60
Min
Max
Units
110
ns
110
70
ns
tELQV
CE # to Output Delay
tpHQV
RP# to Output Delay
tGLQV
OE # to Output Delay
2
tELQX
CE # to Output in Low Z
3
tEHQZ
CE # to Output in High Z
3
tGLQX
OE # to Output in Low Z
3
tGHQZ
OE # to Output in High Z
3
tOH
Output Hold from
Address CE # , or OE #
change whichever
occurs first
3
tELFL
tELFH
CE# Low to BYTE#
High or Low
3
5
5
7
ns
tAVFL
Address to BYTE# High
or Low
3
5
5
7
ns
tFLQV
tFHQV
BYTE # to Output Delay
3,4
60
70
110
ns
tFLQZ
BYTE# Low to Output in
HighZ
3
20
25
45
ns
2
60
70
110
ns
450
450
BOO
ns
30
35
65
a
a
20
a
a
25
a
20
a
55
a
25
a
ns
ns
ns
ns
45
a
ns
ns
4-101
•
2·MBIT SmartVoltage BOOT BLOCK FAMIL V
5.3
AC Characteristics
Table 14. AC Characteristics: Read Only Operations (Commercial) (Continued)
Bv·ao
Symbol
Parameter
BV·120
Vec
5V±10%
3.3±0.3V
5V±10%
Load
100 pF
50pF
100pF
Note
Min
Max
80
Min
Max·
50pF
Max
120
Min
Max
Units
tAVAV
Read Cycle Time
tAVQV
Address to
Output Delay
tELQV
CE # to Output
Delay
tpHQV
RP # to Output
Delay
tGLQV
OE # to Output
Delay
2
tELQX
CE # to Output
in LowZ
3
tEHQZ
CE # to Output
in High Z
3
tGLQX
OE # to Output
in LowZ
3
tGHQZ
OE# to Output
in High Z
3
tOH
Output Hold
from Address
CE#,orOE#
change
whichever
occurs first
3
tELFL
tELFH
CE# Low to
BYTE # High or
Low
3
5
10
5
10
ns
tAVFL
Address to
BYTE # High or
Low
3
5
10
5
10
ns
tFLOV
tFHOV
BYTE# to
Output Delay
3,4
80
150
120
180
ns
tFLQZ
BYTE# Low to
Output in High Z
3
30
60
30
60
ns
2
150
Min
3.3±0.3V
180
ns
80
150
120
180
ns
80
150
120
180
ns
450
800
450
800
ns
40
90
40
90
ns
0
0
30
0
0
80
0
30
0
0
30
0
60
0
ns
80
0
30
0
ns
ns
60
0
ns
ns
NOTES:
1.
2.
3.
4.
See AC Input/Output Reference Waveform for timing measurements.
OE # may be delayed up to tCE - tOE after the falling edge of CE # without impact on tCE'
Sampled, but not 100% tested.
tFLOV, BYTE# switching low to valid output delay will be equal to tAVQV, measured from the time DQ15/A_1 becomes
valid.
5. See 5V High Speed Test Configuration.
6. See 5V Standard Test Configuration.
7. See 3.3V Test Configuration
4-102
2·MBIT SmartVoltage BOOT BLOCK fAMILY
V1H
ADDRESSE S(A)XXXXXXXXX
V 1L
V
CE# (E) IH
V1L
Device and
Address Selection
Data
Valid
..................
•
.................. --1
...
... t EHQZ
...
... t GHQZ
.................. - - J
V
•
• tGLQV
~tGLQX
WE#(W)IH
V1L
VOH
DATA (D/Q )
VOL
t OH '" ~
tELQV
~
tELQX
HighZ
- -,\
.................
Valid Output
t.
HighZ
.................
t AVQV
V
IH
V 1L
XXXXXXXXXXXX
~
•
t AvAV
V
OE#(G) IH
V1L
RP#(P)
3tandby
..........,.......
Address Stable
tpHQV
'I
290531-16
Figure 18. AC Waveforms for Read Operations
V1H
ADDRESSES
CE#
OE#
(~
Standby
XXXXXXXXX
Address Stable
IL
V1H
LFI:+
V1L
~
-lGLQV
ELQV
tGLQX
VOL
DATA (D/Q)
itELQ",
j
.~U
HighZ
VOL
(DQ15-A1)
-
.... t GHQZ
Data Output
onDQ()'DQ7
1.0-
Data Output 1"
.an DQ()'DQ71.JJL
HighZ
'J
- j tAVQV Data Output
nDQ8-DQ1
(DQ8·DQ14)
VOH
... tEHQZ
t OH _
~
HighZ
-..
................... ..-1
... r.-
(DQ()'DQ7)
VOH
IXXXXXX~ttttI.
....................-1
tAVFL
V1H
DATA (D/Q)
~
•
--
V1L
V1H
VOH
..................
..................
t AVAV
V 1L
BYTE#
Data
Valid
Device
Address Selection
•
~tFLQZ
HighZ
I uata uutput
,\
on DQ15
HighZ
...
...tAVQV
r-- ~ddress Input, I
HighZ
'I
VOL
290531-17
Figure 19. BYTE # Timing Diagram for Both Read and Write Operations with Vee at S.OV
4-103
2·MBIT SmartVoltage BOOT BLOCK FAMILY
Table 15. AC Characteristics: WE#-Controlled Write Operations(1) (Commercial)
BV-SO
Symbol
Parameter
Vce
5V±5%
5V± 10%
Load
30pF
100pF
Note
Min
Max
Min
3.3±0.3V
50 pF
Max
Min
Max
Units
60
70
110
ns
RP# Setup to WE#
Going Low
450
450
800
ns
tElWL
CE # Setup to WE #
Going Low
0
0
0
ns
tpHHWH
Boot Block Lock Setup
to WE # GOing High
6,8
100
100
200
ns
tVPWH
Vpp Setup to WE#
Going High
5,8
100
100
200
ns
tAVWH
Address Setup to WE #
Going High
3
50
50
90
ns
tDVWH
Data Setup to WE #
Going High
4
50
50
90
ns
tWLWH
WE # Pulse Width
50
50
90
ns
tWHDX
Data Hold Time from
WE# High
4
0
0
0
ns
tWHAX
Address Hold Time from
WE# High
3
10
10
10
ns
tWHEH
CE# Hold Time from
WE# High
0
0
0
ns
tWHWL
WE # Pulse Width High
tWHOV1
Duration of Word/Byte
Programming Operation
tWHOV2
Duration of Erase
Operation (Boot)
tWHOV3
tAVAV
Write Cycie Time
tpHWL
10
20
20
ns
2,5
6
6
6
JJ-s
2,5,6
0.3
0.3
0.3
s
Duration of Erase
Operation (Parameter)
2,5
0.3
0.3
0.3
s
tWHOV4
Duration of Erase
Operation (Main)
2,5
0:6
0.6
0.6
s
tOWL
Vpp Hold from Valid SRD
5,8
0
0
0
ns
toVPH
RP# VHH Hold from
ValidSRD
6,8
0
0
0
ns
tpHBR
Boot-Block Relock Delay
7,8
4-104
100
100
200
ns
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 15. AC Characteristics: WE#-Controlled Write Operations(1) (Commercial) (Continued)
BV·SO
Symbol
Parameter
tAVAV
Write Cycle Time
tPHWL
BV·120
Vce
5V±10%
3.3±0.3V
5V±10%
Load
100 pF
50pF
100pF
Note
Min
Max
Min
Max
Min
Max
3.3±O.3V
50pF
Min
Max
Units
80
150
120
180
ns
RP# SetuptoWE#
Going Low
450
1000
450
1000
ns
tELWL
CE# SetuptoWE#
Going Low
0
0
0
0
ns
tPHHWH
Boot Block Lock Setup
to WE# GOing High
6,8
100
200
100
200
ns
tVPWH
Vpp Setup to WE#
Going High
5,8
100
200
100
200
ns
tAvwH
Address Setup to WE #
Going High
3
50
120
50
150
ns
tDVWH
Data Setup to WE #
Going High
4
50
120
50
150
ns
tWLWH
WE # Pulse Width
50
120
50
150
ns
tWHDX
Data Hold Time from
WE# High
4
0
0
0
0
ns
tWHAX
Address Hold Time from
WE# High
3
10
10
10
10
ns
tWHEH
CE# Hold Time from
WE# High
0
0
_ 0
0
ns
tWHWL
WE# Pulse Width High
tWHOV1
Duration of Word/Byte
Programming Operation
tWHOV2
Duration of Erase
Operation (Boot)
tWHOV3
30
30
30
30
ns
2,5
6
6
6
6
p.s
2,5,6
0.3
0.3
0.3
0.3
s
Duration of Erase
Operation (Parameter)
2,5
0.3
0.3
0.3
0.3
s
tWHOV4
Duration of Erase
Operation (Main)
2,5
0.6
0.6
0.6
0.6
s
!aWL
Vpp Hold from Valid SRD
5,8
0
0
0
0
ns
!aVPH
RP# VHH Hold from
ValidSRD
6,8
0
0
0
0
ns
tpHBR
Boot-Block Relock Delay
7,8
100
200
100
200
ns
4-105
2-MBIT SmartVoltage BOOT BLOCK FAMILY'
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during read mode.
2. The on-chip WSM completely automates Program/Erase operations; Program/Erase algorithms are now controlled internally which includes verify and margining operations.
3. Refer to command definition table for valid AIN.
4. Refer to command definition table for valid DIN.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes
successfully.
7. Time tpHBR is required for successful relocking of the boot block.
8. Sampled, but not 100% tested.
9. Vpp at 5.0V.
10. Vpp at 12.0V.
11. See 5V High Speed Test Configuration.
12. See 5V Standard Test Configuration.
13. See 3.3V Test Configuration.
ADDRESSES(A).~~__-!~~~__~~~~~~~~~~~~~~~~
V IL -
V1H
CE#(E)
V1L
t ELWL
V
r--+--+----H-------""\
OE# (G) IH
V 1L
tWHQV1.2.3.4
V1H
WE#(W)
V 1L
V1H
DATA (0/0) --:-"---t-i
V 1L
6.5V
VHH
V
RP#(P) IH
V1L
V1H
WP#
V
1L
_ _ _ _ _ _...J
VpPH 2
V pPH1
v pp(V) V
~~~~~Nf--~~~----------~-l~~~~~~~~
PPLKRJ.**********r
V1L JJJ.:lOCIllOI[lO£lMfY
290531-18
NOTES:
1. VCC Power-Up and Standby.
2. Write program or Erase Setup Command.
3. Write Valid Address and Data (Program) or Erase Confirm Command.
4. Automated Program or Erase Delay.
5. Read Status Register Data.
6. Write Read Array Command.
Figure 20. AC Waveforms for Write and Erase Operations (WE#-Controlled Writes)
4-106
2-MBIT SmartVoltage BOOT BLOCK FAMILV
Table 16. AC Characteristics: CE#-Controlled Write Operations(1,13) (Commercial)
BV-60
Symbol
Parameter
Vce
5V±5%
5V±10%
Load
30pF
100pF
Note
Min
Max
Min
Max
3.3±O.3V
50pF
Min
Max
Units
tAVAV
Write Cycle Time
60
70
110
ns
tpHEL
RP# High Recovery to CE# Going
Low
450
450
1000
ns
tWLEL
WE # Setup to CE # Going Low
0
0
0
ns
tpHHEH
Boot Block Lock Setup to CE# Going
High
6,B
100
100
200
ns
tVPEH
Vpp Setup to CE# Going High
5,B
100
100
200
ns
tAvEH
Address Setup to CE# Going High
3
50
50
90
ns
tDVEH
Data Setup to CE # Going High
4
50
50
90
ns
tELEH
CE# Pulse Width
50
50
90
ns
tEHDX
Data Hold Time from CE # High
4
0
0
0
ns
tEHAX
Address Hold Time from CE # High
3
10
10
10
ns
tEHWH
WE # Hold Time from CE # High
0
0
0
ns
tEHEL
CE# Pulse Width High
10
20
20
ns
tEHOV1
Duration of Word/Byte Programming
Operation
2,5
6
6
6
,..s
tEHOV2
Duration of Erase Operation (Boot)
2,5,6
0.3
0.3
0.3
s
tEHOV3
Duration of Erase Operation
(Parameter)
2,5
0.3
0.3
0.3
s
tEHOV4
Duration of Erase Operation (Main)
2,5
0.6
0.6
0.6
s
tOWL
Vpp Hold from Valid SRD
5,B
0
0
0
ns
tOVPH
RP# VHH Hold from Valid SRD
6,B
0
tpHBR
Boot-Block Relock Delay
7,B
0
100
ns
0
100
200
ns
4-107
2·MBIT SmartVoltage BOOT BLOCK FAMILY
Table 16. AC Characteristics: CE#·Controlied Write Operations(1,13) (Commercial) (Continued)
BV-SO
Symbol
Parameter
BV-120
vee
5V±10o;.
3.3V±0.3V
5V±10o;.
Load
100pF
50pF
100 pF
Note
Min
Max
Min
Max
Min
Max
3.3V±0.3V
50pF
Min
Max
Units
tAVAV
Write Cycle Time
80
150
120
180
ns
tpHEl
RP# High
Recovery to CE#
Going Low
450
1000
450
1000
ns
tWlEl
WE# Setup to
CE# Going Low
0
0
0
0
ns
tpHHEH
Boot Block Lock
Setup to CE#
Going High
6,8
100
200
100
200
ns
tVPEH
Vpp Setup to CE #
Going High
5,8
100
200
100
200
ns
tAVEH
Address Setup to
CE # Going High
3
50
120
50
150
ns
tDVEH
Data Setup to CE #
Going High
4
50
120
50
150
ns
tElEH
CE # Pulse Width
50
120
50
150
ns
tEHDX.
Data Hold Time
from CE # High
4
0
0
0
0
ns
tEHAX
Address Hold Time
from CE# High
3
10
10
10
10
ns
tEHWH
WE # Hold Time
from CE# High
0
0
0
0
ns
tEHEl
CE# Pulse Width
High
30
30
30
30
ns
tEHOV1
Duration of Word/
Byte Programming
Operation
2,5
6
6
6
6
JLs
tEHOV2
Duration of Erase
Operation (Boot)
2,5,6
0.3
0.3
0.3
0.3
s
tEHOV3
Duration of Erase
Operation
(Parameter)
2,5
0.3
0.3
0.3
0.3
s
tEHOV4
Duration of Erase
Operation (Main)
2,5
0.6
0.6
0.6
0.6
s
tOWl
Vpp Hold from
ValidSRD
5,8
0
0
0
0
ns
tovPH
RP# VHH Hold
from Valid SRD
6,8
0
0
0
0
ns
tpHBR
Boot·Block Relock
Delay
7,8
100
200
100
200
ns
NOTES:
See WE # Controlled Write Operations for notes 1 through 12.
13. Chip-Enable controlled writes: Write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times
should be measured relative to the CE# waveform.
4-108
2-MBIT SmartVoltage BOOT BLOCK FAMILY
1
V,
,.--...~
2
~~
ADDRESSE;~~)= ~N
f
___________ 3
,_~
r;= t ='l:t
V1H
AVAV
WE# (E)
~N
AVEH +
4
~,~
5_________ , _____________6A..___________,
,~,
~
~~~L-,-----------.
V1L
V
tWLEL
,--t--t-----tr-------.
OE#(G) IH
V1L
t EHQV1,2,3,4
V1H
CE#(W) .
V1L
V1H
DATA (DIQ).......,-=--t-i
} - - - - - - + H Valid
SRD
V 1L
..................................................................... ~ tavPH
6.SV V HH
V
RP#(P) IH
V1L
V1H
WP#
V
1L
_ _ _ _ _--'
pPH 2 ~~~~~A.F--~~------_i~~~~~~~OV
V
V 1
pPH
V pp(V)
VpPLK I&~OOOOOOPRI
V1L .J),(J/j/'YJ/..'!IJf.'iJD.1JDJ
290531-19
NOTES:
1, Vec Power-Up and Standby,
2. Write program or Erase Setup Command.
3. Write Valid Address and Data (Program) or Erase Confirm Command.
4. Automated Program or Erase Delay.
5. Read Status Register Data,
6. Write Read Array Command.
Figure 21_ Alternate AC Waveforms for Write and Erase Operations (CE#-Controlled Writes)
4-109
2·MBIT SmartVoltage BOOT BLOCK FAMILY
Table 17. Erase and Program Timings (Commercial TA = O·C to
Vpp=5V ± 10%
+ 70·C)
Vpp= 12V ±5%
Vee = 3.3
±0.3V
Vee=5V
±10%
Vee=3.3V
±0.3V
Vee=5V
±10%
Typ
Typ
Typ
Typ
Boot/Parameter Block Erase Time
0.B4
O.B
0.44
0.34
s
Main Block Erase Time
2.4
1.9
1.3
1.1
s
Main Block Write Time (Byte Mode)
1.7
1.B
1.6
1.2
s
Main Block Write Time (Word Mode)
1.1
0.9
O.B
0.6
s
Byte Write Time
10
10
8
B
/A-s
Word Write Time
13
13
8
B
/A-s
Parameter
NOTES:
1. All numbers are sampled. not 100% tested.
2. Contact your Intel representative for information regarding maximum Byte/Word Write specifications.
4-110
Units
2-MBIT SmartVoltage BOOT BLOCK FAMILY
6.0
EXTENDED OPERATING CONDITIONS
Table 18. Extended Temperature and Vee Operating Conditions
Symbol
Parameter
Notes
Min
Max
Units
TA
Operating Temperature
-40
85
°C
Vcc
3.3V Vcc Supply Voltage (± 0.3V)
1
3.0
3.6
Volts
5V Vcc Supply Voltage (10%)
2
4.50
5.50
Volts
NOTES:
1. AC specifical;ons are valid at both voltage ranges. See DC Characteristics tables for voltage range-specific specifications.
2. 10% Vee specifications apply to 110 ns and 80 ns versions in their standard test configuration.
6.1 Applying VCC Voltages
Table 19. Vee Supply Switching Timing
Symbol
Parameter
Notes
Min
T5VPH
Vcc at 4.5V (minimum) to RP# High
1
2
,...s
T3VPH
Vcc at 3.0V (minimum) to RP# High
1
2
,...s
Max
Units
NOTES:
1. The T 5VPH and/or T3VPH times must be strictly followed to guarantee all other read and write specifications.
2. To switch between 3.3V and 5.0V operation. the system should first transition Vee from the existing voltage to GND. and
then to the new voltage. The Vee supply voltage should not be switched when the WSM is busy.
5.0V ...................................................................*._ _ _ _ _ _ _ _ _ _ _ _ __
3.3V·················································....
/
GND
RP#
V 1H
~ .................................................................................................
-I~,"
--
t 3VPH
='1
-/.
. .- - - - - -
290531-12
Figure 22. Vee Supply Switching Waveform
4-111
2·MBIT SmartVoltage BOOT BLOCK FAMILY
6.2 DC Characteristics
Table 20. DC Characteristics: Extended Temperature Operation
isymbol Parameter Notes
TBV·SO
TBV-SO
Vee = 3.3 ± 0.3V
Vee = 5V ± 10%
Min
Typ
Max
Min
Typ
Units
Test Conditions
Max
IlL
Input Load
Current
1
± 1.0
± 1.0
p.A Vee = Vee MAX
VIN == Vee or GND
ILO
Output
Leakage
Current
1
± 10
± 10
p.A Vee = Vee MAX
VIN = Vee
orGND
Ices
Vee Standby
Current
1,3
1
IceD
Vee Deep
Power-Down
Current
leeR
1,5,6
Vee Read
Current for
Word or Byte
leew
4-112
Vee Write
Current for
Word or Byte
1,4
0.4
1.5
0.8
2.5
mA Vee = VeeMAX
CE# = RP# =
BYTE# = VIH
60
110
70
150
p.A Vee = VeeMAX
CE# = RP# = WP#
= Vee ± 0.2V
0.2
8
0.2
8
p.A Vee = VeeMAX
VIN = Vee or GND
RP# = GND ± 0.2V
15
30
50
65
mA CMOS INPUTS
Vee = VeeMAX
CE# = GND
OE# = Vee
f = 10 MHz (5V),
5 MHz (3.3V)
lOUT = OmA
Inputs = GND ± 0;2V
or Vee ± 0.2V
15
30
55
70
mA TTL INPUTS
Vee = VeeMAX
CE# = VIL
OE# = VIH
f = 10 MHz (5V),
5 MHz (3.3V)
lOUT = OmA
Inputs = VIL or VIH
13
30
30
50
mA Word/Byte Program
in Progress
Vpp = VpPH1 (at 5V)
10
25
30
45
mA Word/Byte Program
in Progress
Vpp = VPPH2 (at 12V)
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 20. DC Characteristics: Extended Temperature Operation (Continued)
TBV-80
Symbol Parameter Notes
Vee = 3.3 ± 0.3V
Min
ICCE
Vcc Erase
Current
TBV-80
Max
13
Vee = 5V ± 10%
Min
Units
Test Conditions
Typ
Max
30
22
45
mA
Block Erase
in Progress
Vpp = VPPH1 (at 5V)
10
25
18
40
mA
Block Erase
in Progress
Vpp = VPPH2 (at 12V)
1,2
3
8.0
5
12.0
mA
CE# = VIH
Block Erase Suspend
Vpp = VPPH1 (at 5V)
1,4
Typ
ICCES
VCC Erase
Suspend
Current
IpPS
Vpp Standby
Current
1
±5
± 15
±5
± 15
/LA
Vpp ~ VCC
IpPD
Vpp Deep
Power-down
Current
1
0.2
10
0.2
10
/LA
RP# = GND ± 0.2V
IpPR
Vpp Read
Current
1
50
200
50
200
/LA
Vpp> Vec
Ippw
Vpp Write
Current for
Word/Byte
1,4
13
30
13
30
mA
Vpp = VPPH
Word Write in Progress
Vpp= VpPH1 (at 5V)
8
25
8
25
mA
Vpp = VPPH
Word Write in Progress
Vpp = VPPH2 (at 12V)
13
30
15
25
mA
Vpp = VPPH
Block Erase in
Progress
Vpp = VPPH1 (at 5V)
8
25
10
20
mA
Vpp = VPPH
Block Erase in
Progress
Vpp = VPPH2 (at 12V)
50
200
50
200
/LA
Vpp = VPPH
Block Erase Suspend
in Progress
IpPE
IpPES
Vpp Erase
Current
Vpp Erase
Suspend
Current
1,4
1
4-113
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 20. DC Characteristics: Extended Temperature Operation (Continued)
TBV-80
TBV-80
't,
Symbol
Parameter
Notes
Vee
Min
=
3.3
Typ
± 0.3V
Max
Vee
Min
=
5V
Typ
± 10%
Units Test Conditions
Max
IRP#
RP# Boot
Block Unlock
Current
1,4
500
500
/LA RP# = VHH
Vpp = 12V
110
Aglntelligent
Identifier
Current
1,4
500
500
/LA Ag
jIIlO
Ag Intelligent
Identifier
Voltage
11.4
12.6
11.4
12.6
V
rvlL
Input Low
Voltage
-0.5
0.8
-0.5
0.8
V
~IH
Input High
Voltage
2.0
Vee ±
0.5V
2.0
Vee ±
0.5V
V
~OL
Output Low
Voltage
0.45
V
Vee = VeeMIN
IOL = 5.8 mA (5V)
2 mA (3.3V)
Vpp = 12V
~OH1
Output High
Voltage (TTL)
tvOH2
VIO
2.4
2.4
V
Vee = VeeMIN
IOH = -2.5 mA
Output High
Voltage
0.85 x
Vee
0.85 x
Vee
V
Vee = VeeMIN
IOH = -2.5 mA
(CMOS)
VeeO.4V
VeeO.4V
Vee = VeeMIN
IOH = -100/LA
0.0
1.5
0.0
1.5
V
Complete Write
Protection
VPP (Program/
Erase Operations)
4.5
5.5
4.5
5.5
V
VPP at 5V
VPP (Program/
Erase Operations)
11.4
12.6
11.4
12.6
V
VPP at 12V
tvPPLK
VPP LockOut Voltage
tvPPH1
tvPPH2
4-114
0.45
=
3
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 20. DC Characteristics: Extended Temperature Operation (Continued)
Symbol Parameter Notes
TBV-80
TBV-80
Vee = 3.3 ± 0.3V
Vee = 5V ± 10%
Min
VLKO
VCC
Erase/Write
Lock Voltage
VHH
RP# Unlock
Voltage
10
Typ
Max
2.0
11.4
Min
Typ
Max
2.0
12.6
11.4
Units Test Conditions
12.6
V
Vpp = 12V
V
Boot Block
Write/Erase
Vpp= 12V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, T = 25'C. These currents are valid for all
product versions (packages and speeds).
2. ICCES is specified with the device de-selected. If the device is read while in erase suspend mode, current draw is the sum
of ICCES and ICCR.
3. Block erases and word/byte writes are inhibited when VPP = VPPLK, and not guaranteed in the range between VpPH1
and VPPLK.
4. Sampled, not 1000/0 tested.
,
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA typical, in static operation.
6. CMOS Inputs are either VCC ± 0.2V or GND ± 0.2V. TIL Inputs are either VIL or VIH.
7. For the 28F002 address pin Al0 follows the COUT capacitance numbers.
8. For all BV parts, VLI~O = 2.0V for both 3.3V and 5.0V operations.
4·115
2-MBIT SmartVoltage BOOT BLOCK FAMILY
u
0.0
~5
~
_TEsHoINTs
2.4------,.
-----+
1.5
INPUT
OUTPUT
:> <
0.45 - - - . - /
290531-21
Figure 23. 3.3V Inputs and Measurement Points
20
OUTPUT
TEST POINTS
0.'
290531-13
Figure 25. 5V Inputs and Measurement Points
Vee
Vee
OUT
OUT
n:m
290531-22
290531-14
NOTE:
NOTE:
CL = 50 pF. includes Jig Capacitance
CL = 100 pF. includes Jig Capacitance
Figure 24. 3.3V Standard Test Configuration
4·116
Figure 26. 5V Standard Test Configuration
2-MBIT SmartVoltage BOOT BLOCK FAMILY
6.3 AC Characteristics
Table 21. AC Characteristics: Read Only Operations(1) (Extended Temperature)
TBV~80
Symbol
Parameter
Note
Vee
=
TBV-80
3.3 ± 0.3V(S)
Min
Max
110
tAvAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE # to Output Delay
tpHQV
RP# to Output Delay
tGLQV
OE # to Output Delay
2
tELQX
CE # to Output in Low Z
3
tEHQZ
CE# to Output in High Z
3
tGLQX
OE # to Output in Low Z
3
Vee
2
tGHQZ
OE # to Output in High Z
3
Output Hold from Address
CE #. or OE # change
whichever occurs first
3
tELFL
tELFH
CE# Low to BYTE# High or
Low
3
tAVFL'
Address to BYTE # High or Low
3
tFLQV
tFHQV
BYTE# to Output Delay
tFLQZ
BYTE# Low to Output in High Z
5V ± 10%(5)
Units
Max
80
110
toH
=
Min
ns
80
ns
110
80
ns
800
450
ns
40
ns
65
0
0
55
0
ns
30
0
ns
30
45
0
0
7
ns
ns
ns
5
ns
7
5
ns
3,4
110
80
ns
3
45
30
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to teE - tOE after the falling edge of CE# without impact on tCE.
3. Sampled. but not 100% tested.
4. tFLOV. BYTE# switching low to valid output delay will be equal to tAVOV. measured from the time DQ1S/A_l becomes
valid.
.
5. See 5V Standard Test Configuration.
6. See 3.3V Standard Test Configuration.
~.
4-117
2-MBITSmartVoltage BOOT BLOCK FAMILY
Table 22. AC Characteristics: WE#-Controlled Write Operations(l) (Extended Temperature)
TBV-80
,
Symbol
Parameter
Notes
Vee
=
Min
TBV-80
3.3 ± 0.3V(11)
Max
Vee
=
Min
5V ± 10%(12)
Units
Max
tAVAV
Write Cycle Time
110
80
ns
tPHWL
RP# High Recovery to WE#
GOing Low
800
450
ns
tELWL
CE# Setup to WE# Going
Low
0
a
ns
tpHHWH
Boot Block Lock Setup to
WE # Going High
6,8
200
100
ns
tVPWH
Vpp Setup to WE# Going
High
5,8
200
100
ns
tAVWH
Address Setup to WE# Going
High
3
90
60
ns
tOVWH
Data Setup to WE# Going
High
4
90
60
ns
tWLWH
WE # Pulse Width
90
60
ns
tWHOX
Data Hold Time from WE#
High,
4
0
0
ns
tWHAX
Address Hold Time from WE#
High
3
10
10
ns
tWHEH
CE # Hold Time from WE #
High
0
0
ns
tWHWL
WE# Pulse Width High
20
20
ns
tWHQVl
Duration of Word/Byte Write
Operation
2,5
6
7
,.,.s
tWHQV2
Duration of Erase Operation
(Boot)
2,5,6
0.3
0.4
s
tWHQV3
Duration of Erase Operation
(Parameter)
2,5
0.3
0.4
s
tWHQV4
Duration of Erase Operation
(Main)
2,5
0.6
0.7
s'
4-118
2-MBIT SmartVoltage BOOT BLOCK FAMILV
Table 22. AC Characteristics: WE#-Controlled Write Operations(1)
(Extended Temperature) (Continued)
TBV-80
Symbol
Parameter
Notes
Vee = 3.3
Min
TBV-80
± O.3V(11)
Max
Vee = 5V
Min
± 10%(12)
Units
Max
tawL
Vpp Hold from Valid SRD
5,8
0
0
ns
tavPH
RP# VHH Hold from Valid
SRD
6,8
0
0
ns
tpHBR
Boot-Block Relock Delay
7,8
200
100
ns
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during read mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations.
3. Refer to command definition table for valid AIN'
4. Refer to command definition table for valid DIN.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7 = 1)
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes
successfully.
7. Time tpHBA is required for successful relocking of the boot block.
8. Sampled, but not 100% tested.
9. Vpp at 5.0V.
10. Vpp at 12.0V.
11. See 3.3V Standard Test Configuration.
12. See 5V Standard Test Configuration.
4-119
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 23. AC Characteristics: CE#-Controlled Write Operations(1,13)
TBV-80
Symbol
Parameter
Notes
Vee
=
Min
3.3
TBV-80
± 0.3V(11)
Max
Vee
=
Min
5V
±
10%(12)
Units
Max
tAVAV
Write Cycle Time
110
80
ns
tpHEL
RP # High Recovery to CE #
Going Low
800
450
ns
tWLEL
WE # Setup to CE # Going
Low
0
0
ns
tpHHEH
Boot Block Lock Setup to
CE# Going High
6,8
200
100
ns
tVPEH
Vpp Setup to CE# Going High
5,8
200
100
ns
tAVEH
Address Setup to CE # Going
High
90
60
ns
tDVEH
Data Setup to CE # Going
High
3
90
60
ns
tELEH
CE # Pulse Width
4
90
60
ns
tEHDX
Data Hold Time from CE #
High
0
0
ns
tEHAX
Address Hold Time from CE #
High
4
10
10
ns
tEHWH
WE# Hold Time from CE#
High
3
0
0
ns
tEHEL
CE # Pulse Width High
20
20
ns
tEHQV1
Duration of Word/Byte Write
Operation
2,5
6
7
IJ-s
tEHQV2
Duration of Erase Operation
(Boot)
2,5,6
0.3
0.4
s
tEHQV3
Duration of Erase Operation
(Parameter)
2,5
0.3
0.4
s
tEHQV4
Duration of Erase Operation
(Main)
2,5
0.6
0.7
s
tQWL
Vpp Hold from Valid SRD
5,8
0
0
ns
tQVPH
RP# VHH Hold from Valid
SRD
6,8
0
0
ns
tpHBR
Boot-Block Relock Delay
7,8
200
100
ns
NOTES:
See WE # Controlled Write Operations for notes 1 through 12.
13. Chip-Enable controlled writes: Write operations are driven by the valid combination of CE # and WE # in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times
should be measured relative to the CE # waveform.
4-120
2-MBIT SmartVoltage BOOT BLOCK FAMILY
Table 24. Extended Temperature Operations-Erase and Program Timings
Vpp=5V±10%
Parameter
Boot/Parameter Block Erase Time
Vpp=12V±5%
Vcc=
3.3±O.3V
Vcc=
5V±10%
Vcc=
3.3±O.3V
Vcc=
5V±10%
Typ
Typ
Typ
Typ
0.84
0.8
0.44
0.34
s
Units
Main Block Erase Time
2.4
1.9
1.3
1.1
s
Main Block Write Time (Byte Mode)
1.7
1.4
1.6
1.2
s
Main Block Write Time (Word Mode)
1.1
0.9
0.8
0.6
s
Byte Write Time
10
10
B
B
p.s
Word Write Time
13
13
B
B
p.s
NOTES:
1. All numbers are sampled, not 100% tested.
2. Contact your Intel representative for information regarding maximum Byte/Word Write specifications.
4-121
2-MBIT SmartVoltage BOOT BLOCK FAMILV
,7.0
ADDITIONAL INFORMATION
7.1 Ordering Information
Access Speed
(ns, Vcc = 5V)
Operating Temperature
T = Extended Temp
Blank = Commercial Temp
T=Top Boot
B = Bottom Boot
Package
E=TSOP
PA = 44-Lead PSOP
TB = Ext. Temp 44-Lead PSOP
Voltage Options (Vppl Vcc )
V = (5 or 12 I 3.3 or 5)
Product line designator
for all Intel Flash products
Architecture
B = Boot Block
C = Compact 4B-Lead TSOP
Boot Block
Density I Organization
OOX = xB-only (X = 1, 2, 4, B)
XOO = xB/x16 Selectable (X = 2, 4, B)
290531-25
VALID COMBINATIONS:
40·Lead TSOP
Commercial
E28F002BVT60
E28F002BVB60
E28F002BVT80
E28F002BVB80
E28F002BVT120
E28F002BVB120
TE28F002BVT80
TE28F002BVB80
Extended
44-Lead PSOP
PA28F200BVT60
PA28F200BVB60
PA28F200BVT80
PA28F200BVB80
PA28F200BVT120
PA28F200BVB120
48-Lead TSOP
E28F200CVT60
E28F200CVB60
E28F200CVT80
E28F200CVB80
56-Lead TSOP
E28F200BVT60
E28F200BVB60
E28F200BVT80
E28F200BVB80
TB28F200BVT80
TB28F200BVB80
TE28F200CVT80
TE28F200CVB80
TE28F200BVT80
TE28F200BVB80
Table 25. Summary of Line Items
Name
3.3V
40Lead
TSOP
Vpp
VCC
5V
5V
12V
28F200BV
",
",
",
",
28FOO2BV
",
",
",
",
4-122
44Lead
PSOP
f',j!"'(L2 t1j\1
",
",
48Lead
TSOP
~';"
56Lead
TSOP
",
",
Of
0°_+ 70°C
"I'
"!'!r',,'
-400-+85°c
,'\lb ClillE,k
",
",
",
",
,rl,
2-MBIT SmartVoltage BOOT BLOCK FAMILY
7.2 References
Order Number
Document
292130
AB-57 "Boot Block Architecture for Safe Firmware Updates"
292154
AB-60 "2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family"
292098
AP-363 "Extended Flash ElIOS Concepts for Portable Computers"
292148
AP-604 "Using Intel's Boot Block Flash Memory Parameter Blocks to Replace
EEPROM"
290448
28F002/200BX-T IB 2-Mbit Boot Block Flash Memory Datasheet
290449
28F002/200BL-T IB 2-Mbit Low Power Boot Block Flash Memory Datasheet
290450
28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet
290451
28F004/400BX-T IB 4-Mbit Boot Block Flash Memory Datasheet
290530
2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290539
8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
7.3 Revision History
I
-001
I
Initial release of datasheet
4-123
28F400BX-T/B,28F004BX~T/B
4 MBIT (256K x16, 512K x8) BOOT BLOCK FLASH
MEMORY FAMILY
• xS/x16 Input/Output Architecture
- 2SF400BX-T, 2SF400BX-B
- For High Performance and High
Integration 16-bit and 32-bit CPUs
•
Very High-Performance Read
- 60/S0/120 ns Maximum Access Time
- 30/40/40 ns Maximum Output Enable
Time
•
•
Low Power Consumption
- 20 rnA Typical Active Read Current
•
Reset/Deep Power-Down Input
- 0.2 p,A Icc Typical
- Acts as Reset for Boot Operations
•
Extended Temperature Operation
- - 40°C to + S5°C
•
Write Protection for Boot Block
•
Hardware Data Protection Feature
- Erase/Write Lockout During Power
Transitions
•
Industry Standard Surface Mount
Packaging
- 2SF400BX: JEDEC ROM Compatible
44-Lead PSOP
56-Lead TSOP
- 2SF004BX: 40-Lead TSOP
•
xS-only Input/Output Architecture
- 2SF004BX-T, 2SF004BX-B
- For Space Constrained S-bit
Applications
Upgradeable to Intel's Smart Voltage
Products
• Optimized High Density Blocked
Architecture
- One 16-KB Protected Boot Block
- Two S-KB Parameter Blocks
- One 96-KB Main Block
-Three 12S-KB Main Blocks
- Top or Bottom Boot Locations
•
Extended Cycling Capability
- 100,000 Block Erase Cycles
• Automated Word/Byte Write and Block
Erase
- Command User Interface
- Status Registers
- Erase Suspend Capability
• SRAM-Compatible Write Interface
•
Automatic Power Savings Feature
- 1 rnA Typical Icc Active Current in
Static Operation
4-124
II 12V Word/Byte Write and Block Erase
- Vpp = 12V ± 5% Standard
- Vpp = 12V ± 10% Option
•
ETOX III Flash Technology
-5V Read
November 1994
Order Number: 290451-004
28F400BX-T/B,28F004BX-T/B
Intel's 4-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selective erasure, automated write and erase operations and standard microprocessor interface. The 4-Mbit Flash
Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16 input/output control, very high speed, low power, an industry standard ROM compatible pinout and surface mount
packaging. The 4-Mbit flash family is an easy upgrade from Intel's 2-Mbit Boot Block Flash Memory Family.
The Intel 28F400BX-T/B are 16-bit wide flash memory offerings. These high density flash memories provide
user selectable bus operation for either 8-bit or 16-bit applications. The 28F400BX-T and 28F400BX-B are
4, 194,304-bit non-volatile memories organized as either 524,288 bytes or 262,144 words of information. They
are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industry
standard ROM/EPROM pinout.
The Intel 28F004BX-T/B are 8-bit wide flash memories with 4,194,304 bits organized as 524,288 bytes of
information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable
systems.
.
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The 28F400BX-T/28F004BX-T provide block locations compatible with
Intel's MCS-186 family, 80286, i386™, i486™, i860TM and 80960CA microprocessors. The 28F400BX-BI
28F004BX-B provide compatibility with Intel's 80960KX and 80960SX families as well as other embedded
microprocessors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum acG.9SS time of 60 ns, these 4-Mbit flash devices are very high performance memories which
interface at zero-wait-state to a wide range of microprocessors and microcontrollers. A deep power-down
mode lowers the total Vee power consumption to 1 p.W. This is critical in handheld battery powered systems.
For very low power applications using a 3.3V supply, refer to the Intel 28F400BL-T IB, 28F004BL-T IB 4-Mbit
Boot Block Flash Memory Family datasheet.
Manufactured on Intel's 0.8 micron ETOX III process, the 4-Mbit flash memory family provides world class
quality, reliability and cost-effectiveness at the 4-Mbit density level.
I
4-125
28F400BX-T IB, 28F004BX-T IB
1.0 PRODUCT FAMILY OVERVIEW
Throughout this datasheet the 28F400BX refers to
both the 28F400BX-T and 28F400BX-B devices and
28F004BX refers to both the 28F004BX-T and
28F004BX-B devices. The 4-Mbit flash memory family refers to both the 28F400BX and 28F004BX products. This datasheet comprises the specifications for
four separate products in the 4-Mbit flash memory
family. Section 1 provides an overview of the 4-Mbit
flash memory family including applications, pinouts
and pin descriptions. Sections 2 and 3 describe in
detail the specific memory organizations for the
28F400BX and 28F004BX products respectively.
Section 4 combines a description of the family's
principles of operations. Finally Section 5 describes
the family's operating specifications.
Product Family
XB/X16 Products
XB-Only Products
28F400BX-T
28F004BX-T
28F400BX-B
28F004BX-B
1.1 Designing for Upgrade to
SmartVoltage Products
Today's high volume boot block products are upgradable to Intel's SmartVoltage boot block products that provide program and erase operation at 5V
or 12V Vpp and read operation at 3V or 5V Vee.
Intel's SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this data sheet:
1. DU pin is replaced by WP# to provide a means
to lock and unlock the boot block with logic signals.
2. 5V Program/Erase operation uses proven program and erase techniques with 5V ± 10% applied to Vpp.
3. Enhanced circuits optimize performance at 3.3V
Vee·
Refer to the 2, 4 or 8 Mbit SmartVoltage Boot Block
Flash Memory Data Sheets for complete specifications.
When you design with 12V Vpp boot block products
you should provide the capability in your board design to upgrade to SmartVoltage products.
4-126
Follow these guidelines to ensure compatibility:
1. Connect DU (WP# on SmartVoltage products) to
a control signal or to Vee or GND.
2. If adding a switch on Vpp for write protection,
switch to GND for complete write protection.
3. Allow for connecting 5V to Vpp and disconnect
12V from the Vpp line, if desired.
1.2 Main Features
The 28F400BX/28F004BX boot block flash memory
family is a very high performance 4-Mbit (4,194,304
bit) memory family organized as either 256 KWords
(262,144 words) of 16 bits each or 512 Kbytes
(524,288 bytes) of 8 bits each.
Seven Separately Erasable Blocks including a
Hardware-Lockable boot blocl( (16,384 Bytes),
Two parameter blocks (8,192 Bytes each) and
Four main blocks (1 block of 98,304 Bytes and 3
blocks of 131,072 Bytes) are included on the 4-Mbit
family. An erase operation erases one of the main
blocks in typically 2.4 seconds and the boot or parameter blocl erase and programming voltage is 11.4V '10 12.6V (Vpp = 12V
± 5%) under all operating conditions. As an option, Vpp can also vary between 10.8V to 13.2V (Vpp
= 12V ± 10%) with a guaranteed number of 100
block erase cycles.
Typical Icc Active Current of 25 mA is achieved
for the X16 products (28F400BX). Typical Icc Active Current of 20 mA is achieved for tl1e X8 products (28F400BX, 28F004BX). Refer to the Icc active
current derating curves in this datasheet.
When the CE# and RP# pins are at Vcc and the
BYTE!'! pin (28F400BX-only) is at either Vec or
GND the CMOS Standby mode is enabled where
Icc is typically 50 /LA.
A Deep Power-Down Mode is enabled when the
RP# pin is at ground minimizing power consumption
and providing write protection during power-up conditions. Icc current during deep power-down mode
is 0.20 /LA typical. An initial maximum access time
or Reset Time of 300 ns is required from RP#
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 215 ns until
writes to the Command User Interface are recognized. When RP# is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature prevents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to RP# to reset the memory to normal read mode upon activation of the Reset pin.
With on-chip program/erase automation in the
4-Mbit family and the RP# functionality for data protection, when the CPU is reset and even if a program
or erase command is issued, the device will not recognize any operation until RP# returns to its normal
state.
For the 28F400BX, Byte-wide or Word-wide Input/Output Control is possible by controlling the
BYTE# pin. When the BYTE# pin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through 00[0:7]. During the bytewide mode, DO [8:14] are tri-stated and 0015/ A-1
becomes the lowest order address pin. When the
BYTE# pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through 00[0:15].
The 4-Mbit boot blocl( flash memory family is also
designed with an Automatic Power Savings (APS)
feature to minimize system battery current drain and
allows for very low power designs. Once the device
is accessed to read array data, APS mode will immediately put the memory in static mode of operation
where Icc active current is typically 1 mA until the
next read is initiated.
I
4-127
28F400BX-T/B, 28F004BX-T/B·
The 4·Mbit boot block flash memory family combines high density; high performance, cost-effective
flash memories with blocking and hardware protection capabilities. Its flexibility and versatility will reduce costs throughout the product life cycle. Flash
memory is ideal for Just-In-Time production flow, reducing system inventory and costs, and eliminating
component handling during the production phase.
This increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped. The 4-Mbit flash fTIemory
products provide an inexpensive update solution for
the notebook and handheld personal computers
while extending their product lifetime. Furthermore,
the 4-Mbit flash memory products' power-down
mode provides added flexibility for these batteryoperated portable designs which require operation
at very low power levels.
During the product life cycle, when code updates or
feature enhancements become necessary, flash
memory will reduce the update costs by allowing either a user-performed code change via floppy disk
or a remote code change via a serial link. The 4-Mbit
boot block flash memory family provides full function, blocked flash memories suitable for a wide
range of applications. These applications include
Extended PC BIOS and ROM-,able applications
storage, Digital CeHular Phone program and data
storage, Telecommunication boot/firmware, Printer firmware/font storage and various other embedded applications where both program and data storage are required.
The 4-Mbit flash memory products also provide excellent design solutions for Digital Cellular Phone
and Telecommunication switching applications requiring high performance, high density storage capability coupled with modular software designs, and a
small· form factor package (X8-only bus). The
4-Mbit's blocking scheme allows for an easy segmentation of the embedded code with; 16 Kbytes of
Hardware-Protected Boot code, 4 Main Blocks of
program code and 2 Parameter Blocks of 8 Kbytes
each for frequently updatable data storage and diagnostic messages (e.g., phdne numbers, authorization codes). Figure 2 is an example of such an application with the 28F004BX-T.
Reprogrammable systems such as personal computers, are ideal applications for the 4-Mbit flash
memory products. Portable and handheld personal
computer applications are becoming more complex
with the addition of power management software to
take advantage of the latest m!croprocessor ,technology, the availability of ROM-based application
software, pen tablet code for electronic hand writing,
and diagnostic code. Figure 1 shows an example of '
a 28F400BX-T application.
These are a few actual examples of the wide range
of applications for the 4-Mbit Boot Block flash memory family which enable system designers achieve
the best possible product design. Only your imagination limits the applicability of such a versatile product
family.
1.3 Applications
4-128
I
28F400BX-T IB, 28F004BX-T IB
12V
r1-~I
RESET#~
I
GPIO
10 _ _ .1I
Vpp
A[O:17]
CS#
1-_ _ _ _ _ _ _ _ _-'/
Processor
A[O: 17]
t-----------------------+I CE#
RD#
Intel386n, EX
Embedded
BYTE#
OE#
Intel
28F400BX-T
~-------------iiWE#
WR#
0[0:15]
00[0:15]
GPIO--_r-'
RESET#
PWRGOOD - -_ _"
RP#
290451-4
Figure 1. 28F400BX Interface to Intel386TMEX Embedded Processor
"
A,S: 18
~
Aa -A15
ADDRESS
LATCHES
LE
ALE
A
ADc-A~
80C188EB
"
l~
ADDRESS
LATCHES
LE
fll
tlJ
r-ll
DOc-DOl
UCS#
12V
L
P1.X
Vpp
GENERATOR
CE# 28FOO4BX-T
Vpp
RP#
+-
WE#
OE#
WR#
RD#
RESIN#
I
~L
Ac -A18
L
SYSTEM RESET
290451-24
Figure 2. 28F004BX Interface to INTEL 80C188EB 8-Bit Embedded Processor
I
4-129
28F400BX-T/B,28F004BX-T/B
1_4 Pinouts
The 28F400BX 44-Lead PSOP pinout follows the industry standard ROM/EPROM pinout as shown in
Figure 3. Furthermore, the 28F400BX 56-Lead
TSOP pinout shown in Figure 4 provides density upgrades to future higher density boot block memories.
The 28F004BX 40-Lead TSOP pinout shown in Figure 5 is 100% compatible and provides a density
upgrade for the 2-Mbit Boot Block flash memory or
the 28F002BX.
27C400
27C400
NC
NC
A17
A7
As
A5
A4
A3
A2
A1
Ao
CE#
GND
OE#
DQo
DQa
DQ1
DQg
DQ2
DQ10
DQ3
DQ11
RP#
W[#
Aa
Ag
AIO
'-11
'-12
'-13
'-1
Ao
C[#
GND
0[#
II
PA28F400BX
44 LEAD PSOP
0_525" X 1.110"
TOP VIEW
'-14
'-1s
'-16
BYT[#
GND
D~s/A..I
000
D~
DOa
0014
DOl
DOs
DOg
D~3
002
DQs
D~o
D~2
D~
DQ4
D~I
Vee·
290451-25
NC·
NC
Aa
Ag
A10
A11
A12
A13
A14
A15
A1S
BYTE#/Vpp
GND
DQ15/A -1
DQ7
DQ14
DQS
DQ13
DQ5
DQ12
DQ4
Vee
Figure 3. PSOP Lead Configuration for x8/x16 28F400BX
4-130
/
I
28F400BX-T IB, 28F004BX-T IB
NC
NC
A,.
NC
A'5
BYTE#
A"
GND
."
DQ 1S /A_l
A12
DO,
.
00,3
005
OQ14
A"
DO•
AlO
Aa
NC
NC
WE"
RP"
NC
NC
28F400BX
56-LEAD TSOP
14mm x 20mm
TOP VIEW
OQ 12
DO,
Vee
Vee
OQ11
DO,
Vpp
DQ,o
DU
DO,
DOg
DO,
DOa
000
OE"
NC
A"
A,
A,
A5
GND
A,
A,
A,
A,
CEO
AD
NC
NC
NC
290451-3
Figure 4. TSOP Lead Configuration for x8/x16 28F400BX
A,.
A"
GND
A'5
NC
A"
A13
NC
A12
A,o
A"
DO,
DO,
..
Aa
WE#
RP"
Vpp
DU
A,a
28F004BX
40- LEAD TSOP
10mm x 20mm
TOP VIEW
A,
A.
A5
A,
0°5
DO,
VCC
VCC
NC
DO,
DO,
DO,
000
OE"
GND
A,
A,
A,
CEO
Ao
290451-20
Figure 5. TSOP Lead Configuration for x8 28F004BX
I
4-131
28F400BX-T/B,28F004BX-T/B
1.5 28F400BX Pin Descriptions
Symbol
Type
Name and Function
Ao-A17
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write
cycle.
Ag
I
ADDRESS INPUT: When Ag is at 12V the signature mode is accessed. During this mode Ao
decodes between the manufacturer and device ID's. When BYTE # is at a logic low only the
lower byte of the signatures are read. DQ15/ A-1 is a don't care in the signature mode when
BYTE# is low.
DQO-DQ7·
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a
program command. Inputs commands to the command user interface when CE # and WE #
are active. Data is internally latched during the write and program cycles. Outputs array,
Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled.
DQa-DQ15
I/O
DATA·INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a
program command. Data is internally latched during the write and program cycles. Outputs
array data. The data pins float to tri-state when the chip is deselected or the outputs are
disabled as in the byte-wide mode (BYTE # = "0"). In the byte-wide mode DQ15/A-1
becomes. the lowest order address for data output on DQO-DQ7.
CE#
I
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense
amplifiers. CE # is active low; CE # high deselects the memory device and reduces power
consumption to standby levels. If CE# and RP# are high, but not at a CMOS high level, the
standby current will increase due to current flow through the CE # and RP # input stages.
RP#
I
RESET/DEEP POWER·DOWN: Provides three-state control. Puts the device in deep power:
down mode. Locks the boot block from program/erase.
When RP # is at logic high level and equals 6.5V maximum the boot block is locked and
cannot be programmed or erased.
When RP #
erased.
= 11.4V minimum the boot block is unlocked and can be programmed or
When RP# is at a logic low level the boot block is locked, the deep power-down mode is
enabled and the WSM is reset preventing any blocks from being programmed or erased,
therefore providing data protection during power transitions.
When RP# transitions from logic low to logic high the flash memory enters the read-array
mode.
OE#
I
OUTPUT ENABLE: Gates the device's outputs through the data buffers during a read cycle.
OE# is active low.
WE#
I
WRITE ENABLE: Controls writes to the Command Register and array blocks. WE # is active
low. Addresses and data are latched on the rising edge of the WE # pulse.
BYTE #
I
BYTE # ENABLE: Controls whether the device operates in the byte-wide mode (x8) or the
word-wide mode (x16). BYTE # pin must be controlled at CMOS levels to meet 100A CMOS
current in the standby mode. BYTE# = "0" enables the byte-wide mode, where data is read
and programmed on DQo-DQ7 and DQ15/ A -1 becomes the lowest order address that
decodes between the upper and lower byte. DQa-DQ14 are tri-stated during the byte-wide
mode. BYTE # = "1" enables the word-wide mode where data is read and programmed on
DQO-DQ15·
Vpp
,
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming
data in each block.
Note: Vpp < VPPLMAX memory contents cannot be altered.
± 10%, 5V ± 5%)
Vee
DEVICE POWER SUPPLY (5V
GND
GROUND: For all internal circuitry.
NC
NO CONNECT: Pin may be driven or left floating.
DU
DON'T USE PIN: Pin should not be connected to anything.
4-132
I
28F400BX-T IB, 28F004BX-T IB
1.6 28F004BX Pin Descriptions
Symbol
Type
Name and Function
Ao-A18
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.
Ag
I
ADDRESS INPUT: When Ag is at 12V the signature mode is accessed. During this
mode Ao decodes between the manufacturer and device ID's.
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a program command. Inputs commands to the command user interface when
CE # and WE # are active. Data is internally latched during the write and program
cycles. Outputs array, Intelligent Identifier and status register data. The data pins
float to tri-state when the chip is deselected or the outputs are disabled.
CE#
I
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE # is active low; CE # high deselects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not at
a CMOS high level, the standby current will increase due to current flow through the
CE# and RP# input stages.
RP#
I
RESET/DEEP POWERDOWN: Provides Three-State control. Puts the device in
deep power-down mode. Locks the Boot Block from program/erase.
DOo-DO?
When RP# is at logic high level and equals 6.5V maximum the Boot Block is locked
and cannot be programmed or erased.
When RP#' = 11.4V minimum the Boot Block is unlocked and can be programmed
or erased.
When RP# is at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or'erased, therefore providing data protection during power transitions.
When RP# transitions from logic low to logic high, the flash memory enters the
read-array mode.
OE#
I
OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. OE# is active low.
WE#
I
WRITE ENABLE: Controls writes to the Command Register and array blocks. WE #
is active low. Addresses and data are latched on the rising edge of the WE # pulse.
Vpp
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
NOTE: Vpp < VpPLMAX memory contents cannot be altered.
Vee
DEVICE POWER SUPPLY (5V ± 10%, 5V ±5%)
GND
GROUND: For all internal circuitry.
NC
NO CONNECT: Pin may be driven or left floating.
DU
DON'T USE PIN: Pin should not be connected to anything.
I
4-133
I~
!
UJ
./>.
N
C»
"11
~
0
0
I\)
CD
III
"TI
I~
DQo-DIJ:,
:e
0
"11
0
0
......
><
..
ii!i
c
CD
sn
BYTE#
Q)
....0
CE#
ID
W[#
::e
0[#
"TI
0
><
..
0
RP#
Co
-
ID
'<
III
:s
C
m
'V
::D
0
C
-t
Ao -
C
Y-GATING/SENSING
A17
Vpp
C
."
l>
••
•
'"
l>
.::00
",I
--<><
."
l>
l>
",00
'"
.::'"
.::-
",I
--<><
ZI
ZI
~'"
n--<
~'"
"''''
"''''
"'-<
"''''
b~
--<
--<
"'-<
~,.,
0
n
><
0
",'"
l>"'"
-00
"''''
'--'"
0-<
n--<
",,,,
.::l>,...,
Z'f
"'''
'--'"
0-<
n--<
",,,,
"'-
l>N
zf
"''''
.--'"
0-<
n--<
",,,,
+- vec
+- GND
n
><
290451-1
-
I
-I
......
en
CD
3
m
<
-t
m
0
ID
iii'
III
c:
......
..
~
I
N
CC
III
N
QI)
::D
C
"TI
~
I
-I
......
,!IJ
m
><
6'
()
><
0
m
en
0
::D
'V
-t
0Z
--
::l
c[
@>
28,F400BX·T IB, 28F004BX·T IB
2.1 28F400BX Memory Organization
2.1.1 BLOCKING
The 2BF400BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the blocl< address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 2BF400BX is
a random read/write memory, only erasure is performed by block.
2.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RP# is not at 12V. The boot block can
be erased and written when RP# is held at 12V for
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address locations of the boot block for the 28F400BX-T and
2BF400BX-B.
2.1.2 BLOCK MEMORY MAP
Two versions of the 2BF400BX product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 2BF400BX-T
memory map is inverted from the 2BF400BX-B
memory map.
2.1.2.1. 28F400BX·B Memory Map
The 2BF400BX-B device has the 16-Kbyte boot
block located from OOOOOH to 01 FFFH to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH. In the
2BF400BX-B the first B-Kbyte parameter block resides in memory space from 02000H to 02FFFH.
The second B-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96-Kbyte main block resides in memory space from
04000H to OFFFFH. The three 12B-Kbyte main
block resides in memory space from 10000H to
1FFFFH, 20000H to 2FFFFH and 30000H to
3FFFFH (word locations). See Figure 7.
(Word Addresses)
3FFFFH
12B-Kbyte MAIN BLOCK
30000H
2FFFFH
2.1.1.2 Parameter Block Operation
12B-Kbyte MAIN BLOCK
The 2BF400BX has 2 parameter blocks (B-Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that·the boot block has. The parameter blocl"-
C>
'-' z
>'-' C>
++
;;;
..,.
'"
en
'"
~ ....--t-t-..
128-KBYTE
MAIN BLOCK
128-KBYTE
MAIN BLOCK
C>
0C>
I
8C>
z
Vi
~
128-KBYTE
MAIN BLOCK
Vl
"C>
~
!;;:
C>
I
>-
96-KBYTE
MAIN BLOCK
8-KBYTE
PARAMETER BLOCK
8-KBYTE
PARAMETER BLOCK
Figure 9. 28F004BX Byte-Wide Block Diagram
I
4-137
28F400BX-T/B,28F004BX-T/B
3.1
28F004BX Memory Organization
3.1.1 BLOCKING
The 28F004BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F004BX is
a random read/write memory, only erasure is performed by block.
3.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for tfle kernel code
thal is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being programmed
or erased when RP# is not at 12V. The boot block
can be erased and programmed when RP# is held
at 12V for the duration of the erase or program operation. This allows customers to change the boot
code when necessary while still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
28F004BX-T and 28F004BX-B.
3.1.2 BLOCK MEMORY MAP
Two versions of the 28F004BX product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F004BX-T
memory map is inverted from the 28F004BX-B
memory map.
3.1.2.1 28F004BX·B Memory Map
The 28F004BX-B device has the 16-Kbyte boot
block located from OOOOOH to 03FFFH to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH. In the
28F004BX-B the first 8-Kbyte parameter block resides in memory from 04000H to OSFFFH. The second 8-Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96-Kbyte main
block resides in memory space from 08000H to
1FFFFH. The three 128-Kbyte main block reside in
memory space from 20000H to 3FFFFH, 40000H to
SFFFFH and 60000H to 7FFFFH. See Figure 10.
7FFFFH
12B·Kbyte MAIN BLOCK
60000H
5FFFFH
12B-Kbyte.MAIN BLOCK
3.1.1.2 Parameter Block Operation
The 28F004BX has 2 parameter blocks (8-Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map section for address locations of the parameter blocks
for the 28F004BX-T and 28F004BX-B.
40000H
3FFFFH
12B-Kbyte MAIN BLOCK
20000H
lFFFFH
96-Kbyte MAIN BLOCK
OBOOOH
07FFFH
06000H
05FFFH
04000H
03FFFH
B-Kbyte PARAMETER BLOCK
B-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
3.1.1.3 Main Block Operation
OOOOOH
Four main blocks of memory exist on the 28F004BX
(3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks).
See the following section on Block Memory Map for
the address location of these blocks for the
28F004BX-T and 28F004BX-B.
4-138
Figure 10. 28F004BX-B Memory Map
I
28F400BX-T IB, 28F004BX-T IB
3.1.2.2 28F004BX-T Memory Map
The 28F004BX-T device has the 16·Kbyte boot
block located from 7COOOH to 7FFFFH to accom·
modate those microprocessors that boot from the
top of the address map. In the 28F004BX-T the first
8-Kbyte parameter block resides in memory space
from 7AOOOH to 7BFFFH. The second 8·Kbyte parameter block resides in memory space from
78000H to 79FFFH. The 96-Kbyte main block resides in memory space from 60000H to 77FFFH.
The three 12B-Kbyte main blocks reside in memory
space from 40000H to SFFFFH, 20000H to 3FFFFH
and OOOOOH to 1FFFFH.
7FFFFH
16-Kbyte BOOT BLOCK
7COOOH
7BFFFH
7AOOOH
79FFFH
78000H
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
77FFFH
96·Kbyte MAIN BLOCK
60000H
5FFFFH
128-Kbyte MAIN BLOCK
4.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The 4-Mbit flash
family utilizes a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations.
The CUI allows for 100% TTL-level control inputs,
fixed power supplies during erasure and programming, and maximum EPROM compatibility.
In the absence of high voltage on the Vpp pin, the
4-Mbit boot block flash family will only successfully
execute the following commands: Read Array, Read
Status Register, Clear Status Register and Intelligent Identifier mode. The device provides standard
EPROM read, standby and output disable operations. Manufacturer Identification and Device Identification data can be accessed through the CUI or
through the standard EPROM Ag high voltage access (VID) for PROM programming equipment.
The same EPROM read, standby and output disable
functions are available when high voltage is applied
to the Vpp pin. In addition, high voltage on Vpp allows write and erase of the device. All functions associated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.
40000H
3FFFFH
128-Kbyte MAIN BLOCK
20000H
1FFFFH
128-Kbyte MAIN BLOCK
OOOOOH
Figure 11. 28F004BX-T Memory Map
The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device. The WSM will begin operation upon receipt
of a Signal from the CUI and will report status back
through a Status Register. The CUI will handle the
WE # interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.
4.1 28F400BX Bus Operations
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
I
4-139
28F400BX-T IB, 28F004BX-T IB
Table 1. Bus Operations for WORD-WIDE Mode (BYTE # = V'H)
Mode
Read
Notes
RP#
CE#
OE#
WE#
Ag
Ao
Vpp
1,2,3
VIH
VIL
VIL
VIH
X
X
X
DOUT
VIH
X
X
X
HighZ
DQO-1S
Output Disable
VIH
VIL
VIH
Standby
VIH
VIH
X
X
X
X
X
HighZ
9
VIL
X
X
X
X
X
X
HighZ
4
VIH
VIL
VIL
VIH
VID
VIL
X
0089H
4470H
4471H
Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write
Table
Mode
Read
4,5
VIH
VIL
VIL
VIH
VID
VIH
X
6,7,8
VIH
VIL
VIH
VIL
X
X
X
DIN
2. Bus Operations for BYTE-WIDE Mode (BYTE # = V,L>
Notes
RP#
CE#
OE#
WE#
Ag
Ao
A-1
Vpp
DQO-7
DQS-14
1,2,3
VIH
VIL
VIL
VIH
X
X
X
X
DOUT
HighZ
X
X
X
HighZ
HighZ
Output Disable
VIH
VIL
VIH
VIH
X
VIH
VIH
X
X
X
X
X
X
HighZ
HighZ
Deep Power-Down
9
VIL
X
X
X
X
X
X
X
HighZ
HighZ
Intelligent
Identifier (Mfr)
4
VIH
VIL
VIL
VIH
VID
VIL
X
X
89H
HighZ
4,5
VIH
VIL
VIL
VIH
VID
VIH
X
X
70H
71H
HighZ
6,7,8
VIH
VIL
VIH
VIL
X
X
X
X
DIN
HighZ
Standby
Intelligent
Identifier (Device)
Write
NOTES:
1. Refer to DC Characteristics.
2. X can be VL. VIH for control pins and addresses. VPPL or VpPH for Vpp.
3. See DC Characteristics for VPPL. VPPH. VHH, VID voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A1-A17 = X.
5. Device 10 = 4470H for 28F400BX-T and 4471H for 28F400BX-B.
6. Refer to Table 4 for valid DIN during a write operation.
7. Command writes for Block Erase or Word/Byte Write are only executed when VPP = VPPH.
8. To write or erase the boot block, hold RP# at VHH.
9. RP# must be at GND ±O.2V to meet the 1.2 /LA maximum deep power-down current.
4·140
I
28F400BX·T /B, 28F004BX·T /B
4.2 28F004BX Bus Operations
Table 3. Bus Operations
Mode
Notes
RP#
CE#
OE#.
WE#
Ag
Ao
Vpp
X
X
DOUT
DQO-7
VIH
VIL
VIL
VIH
X
Output Disable
VIH
VIL
VIH
VIH
X
X
X
HighZ
Standby
VIH
VIH
X
X
X
X
X
HighZ
VIL
X
X
X
X
X
X
HighZ
89H
Read
1,2,3
Deep Power-Down
9
Intelligent Identifier (Mfr)
4
VIH
VIL
VIL
VIH
VID
VIL
X
4,5
VIH
VIL
VIL
VIH
VID
VIH
X
78H
79H
6,7,8
VIH
VIL
VIH
VIL
X
X
X
DIN
Intelligent Identifier (Device)
Write
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VPPL or VpPH for Vpp.
3. See DC Characteristics for VPPL, VPPH, VHH, VID voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A1-A18 = X.
5. Device ID = 78H for 28F004BX-T and 79H for 28F004BX-B.
6. Refer to Table 4 for valid DIN during a write operation.
7. Command writes for Block erase or byte program are only executed when Vpp = VPPH.
6. Program or erase the Boot block by holding RP# at VHH.
9. RP# must be at GND ±O.2V to meet the 1.2 p.A maximum deep power-down current.
4.3 Read Operations
4.3.1.2 Input Control
The 4-Mbit boot block flash family has three user
read modes; Array, Intelligent Identifier, and Status
Register. Status Register read mode will be discussed in detail in the "Write Operations" section.
With WE# at logic-high level (VIH), input to the device is disabled. Data Input!Output pins (DO[O:15]
or DO[O:7]) are controlled by OE#.
During power~up conditions (VCC supply ramping), it
takes a maximum of 600 ns from when VCC is at
4.5V minimum to valid data on the outputs.
.
4.3.2 INTELLIGENT IDENTIFIERS
4.3.1 READ ARRAY
If the memory is not in the Read Array mode, it is
necessary to write the appropriate read mode command to the CUI. The 4-Mbit boot block flash family
.has three control functions, all of which must be
logically active, to obtain data at the outputs.
Chip-Enable CE # is the device selection control.
Power-Down RP# is the device power control. Output-Enable OE# is the DATA INPUTIOUTPUT
(DO[O:15] or DO[O:7]) direction control and when
active is used to drive data from the selected memory on to the 1/0 bus:
28F400BX PRODUCTS
The manufacturer and device codes are read via the
CUI or by taking the A9 pin to 12V. Writing 90H to
the CUI places the device into Intelligent Identifier
read mode. A read of location OOOOOH outputs the
manufacturer's identification code, 0089H, andlocation 00001 H outputs the device code; 4470H for
28F400BX-T, 4471H for 28F400BX-B. When
BYTE # is at a logiC low only the lower byte of the
above signatures is read and D01S/A-1 is a "don't
care" during Intelligent Identifier mode. A read array
command must be written to the memory to return to
the read array mode.
28F004BX PRODUCTS
4.3.1.1 Output Control
With OE# at logic-high level (VIH), the output from
the device is disabled and data input! output pins
(DO[O:15] or DO[O:7] are tri-stated. Data input is
then controlled by WE#.
I
The manufacturer and device codes are also read
via the CUI or by taking the A9 pin to 12V. Writing
90H to the CUI places the device into Intelligent
Identifier read mode. A read of location OOOOOH outputs the manufacturer's identification code, 89H,
and location 00001 H outputs the device code; 78H
for 28F004BX-T, 79H for 28F004BX-B.
4-141
28F400BX-T IB, 28F004BX-T IB
4.4 Write Operations
Commands are written to the CUI using standard microprocessor write timings. The CUI serves as the
interface between the microprocessor and' the inter~
nal chip operation. The CUI can decipher Read Array, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program commands. In the event of a read command, the CUI
simply points the read path at either the array, the
Intelligent Identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state mao,
chine that a write or erase has been requested. During a program cyCle, the Write State Machine will
control the program sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Machine has completed its
task, it will allow the CUI to respond to its full command set. The CUI will stay in the current command
state until the microprocessor issues another command.
The CUI will successfully initiate an erase or write
operation only when Vpp is within its voltage range.
Depending upon the application, the system designer may choose to make the Vpp power supply
switchable, available only when memory updates
are desired. The system designer can also choose
to "hard-wire" Vpp to 12V. The .4-Mbit boot block
flash family is deSigned to accommodate-either design practice. It is recommended that RP# be tied to
logical Reset for data protection during unstable
CPU reset function as described in the "Product
Family Overview" section.
However, if RP# is not at VHH when a program or
erase operation of the boot block is attempted, the
corresponding status register bit (Bit 4 for Program
and Bit 5 for Erase, refer to Table 5 for Status Register Definitions) is set to indicate the failure to complete the operation.
4.4.2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a "1", which will also allow the CUI to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.
4.4.2.1 Command Set
Command
Codes
Device Mode
00
10
20
40
50
70
90
BO
DO
FF
Invalid/Reserved
Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
Erase Res'ume/Erase Confirm
Read Array
4_4.1 BOOT BLOCK WRITE OPERATIONS
4.4.2.2 Command Function Descriptions
In the case of Boot Block modifications (write and
erase), RP# .is set to VHH = 12V typically, in addition to Vpp at high voltage.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the 4-Mbit
boot block flash family commands.
4-142
I
28F400B){-T IB, 28F004BX-T IB
Table 4. Command Definitions
Command
Bus Notes
Second Bus Cycle
First Bus Cycle
Cycles
Req'd
8
Operation Address Data Operation Address Data
Read Array
1
1
Write
X
FFH
Intelligent Identifier
3
2,4
Write
X
90H
Read
IA
110
3
Write
X
70H
Read
X
SRD
Write
X
50H
Read Status Register
2
Clear Status Register
1
Erase Setup/Erase Confirm
2
5
Write
BA
20H
Write
BA
DOH
Word/Byte Write Setup/Write
2
6, 7
Write
WA
40H
Write
WA
WD
Erase Suspend/Erase Resume
2
Write
X
BOH
Write
X
DOH
Alternate Word/Byte
Write Setup/Write
2
6,7
Write
WA
10H
Write
WA
WD
NOTES:
1. Bus operations are defined in Tables 1, 2, 3.
2. IA = Identifier Address: OOH for manufacturer code, 01 H for device code.
3. SRD = Data read from Status Register.
4. liD = Intelligent Identifier Data.
Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.
5. BA = Address within the block being erased.
6. WA = Address to be written.
WD "" Data to be written at location WD.
7. Either 40H or 10H commands is valid.
8. When writing commands to the device, the upper data bus [DQe-DQ15] = X (28F400BX-only) which is either Vee or Vss
to avoid burning additional current.
Invalid/Reserved
Read Status Register (70H)
These are unassigned commands. It is not recommended that the customer use any command other
than the valid commands specified above. Intel reserves the right to redefine these codes for future
functions.
This is one of the two commands that is executable
while the state machine is operating. After this command is written, a read of the device will output the
contents of the status register, regardless of the address presented to the device.
Read Array (FFH)
The device automatically enters this mode after program or erase has completed.
This single write command pOints the read path at
the array. If the host CPU performs a CE#lOE#
controlled read immediately following a two-write sequence that started the WSM, then the device will
output status register contents. If the Read Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup.
Intelligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address Ao is used in this mode, all
other address inputs are ignored).
I
Clear Status Register (SOH)
The WSM can only set the Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchronization. The WSM does not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after programming the string. Thus, if any errors exist while
programming the string, the status register will return
the accumulated error status.
4-143
28F400BX·T IB, 28F004BX·T IB
Program Setup (40H or 10H)
This command simply sets the CUI into a state such
that the next write will load the address and data
registers. Either 40H or 10H can be used for Program Setup. Both commands are included to accommodate efforts to achieve an industry standard
command code set.
Program
The second write after the program setup command,
will latch addresses. and data. Also, the CUI initiates
the WSM to begin execution of the' program algorithm. While the WSM finishes the algorithm, the device will output Status Register contents. Note that
the WSM cannot be suspended during programming.
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command.
No other action is taken. If the next command is not
an Erase Confirm command then the CUI will set
both the Program Status and Erase Status bits of the
Status Register to a "1", place the device into the
Read Status Register state, and wait for another
command.
Erase Confirm (DOH)
If the previous command was an Erase Setup command, then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status Register and
Erase Suspend commands. While the WSM is executing, the device will output Status Register data
when OE# is toggled low. Status Register data can
only be updated by toggling either OE # or CE # low.
Erase Suspend (BOH)
This command only has meaning while the WSM is
executing an Erase operation, and therefore will only
be responded to during an erase operation. After
this command has been executed, the CUI will set
an output that directs the WSM to suspend Erase
operations, and then return to responding to only
Read Status Register or to the Erase Resume commands. Once the WSM has reached the Suspend
state, it will set an output into the CUI which allows
the CUI to respond to the Read Array, Read Status
Register, and Erase Resume commands. In this
mode, the CUI will not respond to any other commands. The WSM will also set the WSM Status bit to
a "1". The WSM will continue to run, idling in the
SUSPEND state, regardless of the state of all input
4-144
control pins, with the exclusion of RP #. RP # will
immediately shut down the WSM and the remainder
of the chip. During a suspend operation, the data
and address latches will remain closed, but the address pads are able to drive the address into the
read path.
Erase Resume (DOH)
This command will cause the CUI to clear the Suspend state and set the WSM Status bit to a "0", but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.
4.4.3 STATUS REGISTER
The 4-Mbit boot block flash family contains a status
register which may be read to determine when a program or'erase operation is complete, and whether
that operation completed successfully. The status
register may be read at any time by writing the Read
Status command to the CUI. After writing this command, all subsequent Read operations output data
from the status register until another command is
written to the CUI. A Read Array command must be
written to the CUI to return to the Read Array mode.
The status register bits are output on 00[0:7]
whether the device is in the byte-wide (x8) or wordwide (x16) mode for the 28F400BX. In the word-wide
mode the upper byte, 00[8:15] is set to OOH during
a Read Status command. In the byte-wide mode,
00[8:14] are tri-stated and D015/A-1 retains the
low order address function.
It should be noted that the contents of the status
register are latched on the falling edge of OE # or
CE# whichever occurs last in the read cycle. This
prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register. CE # or OE # must be toggled
with each subsequent status read, or the completion
of a program or erase operation will not be evident.
The Status Register is the interface between the microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate
the status of the WSM, and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation. The WSM sets
status bits "Three" through "Seven" and clears bits
"Six" and "Seven", but cannot clear status bits
"Three" through "Five". These bits can only be
cleared by the controlling CPU through the use of
the Clear Status Register command.
I
28F400BX-T IB, 28F004BX-T IB
4.4.3.1 Status Register Bit Definition
Table 5. Status Register Definitions
IWSMSI ESS
7
6
ES
5
PS I VPPS I
4
3
R
2
I
R
I
R
I
o
NOTES:
SR.? = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
Write State Machine Status bit must first be checked to
determine byte/word program or block erase comple- .
tion, before the Program or Erase Status bits are
checked for success.
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
o = Erase in Progress/Completed
When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to "1". ESS bit remains set to "1" until an Erase Resume command is
issued.
SR.5 = ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Erase
When this bit is set to "1". WSM has applied the maximum number of erase pulses to the block and is still
unable to successfully perform an erase verify.
SR.4 = PROGRAM STATUS
1 = Error In Byte/Word Program
o = Successful Byte/Word Program
When this bit is set to "1", WSM has attempted but
failed to Program a byte or word.
SR.3 = Vpp STATUS
1 = Vpp Low Detect; Operation Abort
0= Vpp OK
The Vpp Status bit unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM
interrogates the Vpp level only after the byte write or
block erase command sequences have been entered
and informs the system if Vpp has not been switched
on. The Vpp Status bit is not guaranteed to report accurate feedback between VPPL and VpPH.
SR.2-SR.O = RESERVED FOR
FUTURE ENHANCEMENTS
These bits are reserved for future use and should be
masked out when polling the Status Register.
4.4.3.2 Clearing the Status Register
4.4.4 PROGRAM MODE
Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure conditions. By allowing the system software to control
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in sequence). The status register may then be read to
determine if an error occurred during that programming or erasure series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other
command may be issued to the CUI. Note again that
before a read cycle can be initiated, a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array,
status register, or Intelligent Identifier.
Program is executed by a two-write sequence. The
Program Setup command is written to the CUI followed by a second write which specifies the address
and data to be programmed. The write state machine will execute a sequence of internally timed
events to:
1. Program the desired bits of the addressed memory word (byte), and
2. Verify that the desired bits are sufficiently programmed.
I
Programming of the memory results in specific bits
within a byte or word being changed to a "0".
If the user attempts to program "1 "s, there will be no
change of the memory cell content and no error occurs.
4-145
28F400BX-T/B,28F004BX-T/B
Similar to erasure, the status register indicates
whether programming is complete. While the program sequence is executing, bit 7 of the status register is a "0". The status register can be polled by
toggling either CE # or OE # to determine when the
program sequence is complete. Only the Read
Status Register command is valid while programming is active.
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, Bit 4 of the status register is set to a "1" to indicate a Program Failure. If
Bit 3 is set then Vpp was not within acceptable limits,
and the WSM will not execute the programming sequence.
The status register should be cleared. before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 12 shows a system software flowchart for device byte programming operation. Figure 13 shows a
similar flowchart for device word programming operation (28F400BX-only).
4.4.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI, along with the addresses, A[12:17j for the
28F400BX or A[12:18j for the 28F004BX, identifying
the block to be erased. These addresses are latched
internally when the Erase Confirm command is issued. Block erasure results in all bits within the block
being set to "1".
The WSM will execute a sequence of internally
timed events to:
1. Program all bits within the block
2. Verify that all bits within the block are sufficiently
programmed
3. Erase all bits within the block and
While the erase sequence is executing, Bit 7 of the
status register is a "0".
When the status register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.
If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a "1" to indicate an
Erase Failure. If Vpp was not within acceptable limits
after the Erase Confirm command. is issued, the
WSM will not execute an erase sequence; instead,
Bits of the status register is set to a "1" to indicate
an Erase Failure, and Bit 3 is set to a "1" to identify
that Vpp supply voltage was not within acceptable
limits.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 14 shows a system software flowchart for
Block Erase operation.
4.4;5.1 Suspending and Resuming Erase
Since an erase operation typically requires 1 to 3
seconds to complete, an Erase Suspend command
is provided. This allows erase-sequence interruption
in order to read data from another block of the memory. Once the erase sequence is started, writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase sequence at a predetermined point in the erase algorithm. The status register must be read to determine
when the erase operation has been suspended.
At this pOint, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
Figure 15 shows a system software flowchart detailing the operation.
4. Verify that all bits within the block are sufficiently
erased
4-146
I
28F400BX-T IB, 28F004BX-T IB
During Erase Suspend mode, the chip can go into a
pseudo-standby mode by taking CE# to VIH and the
active current is now a maximum of 10 mA. If the
chip is enabled while in this mode by taking CE# to
VIL, the Erase Resume command can be issued to
resume the erase operation.
Upon completion of reads from any block other than
the block being erased, the Erase Resume command must be issued. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of erase, the status register must be
read, cleared, and the next instruction issued in order to continue.
I
4.4.6 EXTENDED CYCLING
Intel has designed extended cycling capability into
its ETOX III flash memory technology. The 4-Mbit
boot block flash family is designed for 100,000 program/ erase cycles on each of the seven blocks. The
combination of low electric fields, clean oxide processing and minimized oxide area per memory cell
subjected to the tunneling electric field, results in
very high cycling capability.
4-147
28F400BX-TIB, 28F004BX-TIB
Bus
Operation
Command
Comments
Write
Setup
Program
Data = 40H
Address = Byte to be
programmed
Write
Program
Data to be programmed
Address = Byte to be
programmed
Read
Status Register Data.
Toggle OE # or CE # to update
Status Register
Standby
CheckSR.7
1 = Ready, 0 = Busy
Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
290451-6
Full Status Check Procedure
Bus
Operation
Vpp Range
Error
Byte Program
Error
Comments
Command
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
CheckSR.4
1 = Byte Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290451-7
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.
If error is detilcted, clear the Status Register before
attempting retry or other error recovery.
Figure 12. Automated Byte Programming Flowchart
4-148
I
28F400BX·T IB, 28F004BX·T IB
Bus
Operation
Command
Comments
Write
Setup
Program
Data = 40H
Address = Word to be
programmed
Write
Program
Data to be programmed
Address = Word to be
programmed
Read
Status Register Data.
Toggle OE # or CE # to update
Status Register
Standby
CheckSR.7
1 = Ready, 0
= Busy
Repeat for subsequent words.
Full status check can be done after each word or after a
sequence of words.
290451-8
Write FFH after the last word programming operation to
reset the device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Vpp Range,
Error
Word Program
Error
Command
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
Check SR.4
1 = Word Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290451-9
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other errorrecovery.
Figure 13. Automated Word Programming Flowchart
I
4·149
28F400BX·T IB, 28F004BX·T IB
Bus
Operation
Command
Comments
Write
Setup
Erase
Data = 20H
Address = Within block to be
erased
Write
Erase
Data = DOH
Address = Within block to be
erased
Read
Status Register Data.
ToggleOE# orCE# to update
Status Register
Standby
Check SR.?
1 = Ready, 0
= Busy
Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.
290451-10
Write FFH after the last block erase operation to reset the
device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Vpp Range
Command
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Error
Standby
Check SR.4,S
Both 1 = Command Sequence
Error
Block Erase
Error
Standby
CheckSR.S
1 = Block Erase Error
Error
Command Sequence
SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
290451-11
SR.S is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 14. Automated Block Erase Flowchart
4-150
I
intel®
28F400BX-T IB, 28F004BX-T IB
Bus
Operation
Write
Command
Erase
Suspend
Comments
Data
= BOH
Read
Status Register Data.
ToggleOE# orCE# to
update Status Register
Standby
Check SR.7
1 = Ready
Standby
Check SR.6
1 = Suspended
Write
Read Array
= FFH
Read array data from block
other than that being
erased.
Read
Write
Data
Erase Resume
Data = DOH
290451-12
Figure 15. Erase Suspend/Resume Flowchart
4.5 Power Consumption
4.5.1 ACTIVE POWER
With CE# at a logic-low level and RP# at a logichigh level, the device is placed in the active mode.
The device Icc current is a maximum 60 mA at
10 MHz with TIL input signals.
4.5.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low pwer feature during active mode of operation. The 4-Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the device to put itself into a low current state when it is
not being accessed. After data is read from the
memory array, PRC logic controls the device's power consumption by entering the APS mode where
I
maximum Icc current is 3 mA and typical Icc current
is 1 mAo The device stays in this static state with
outputs valid until a new location is read.
4.5.3 STANDBY POWER
With CE# at a logic-high level (VIH), and the CUI in
read mode, the memory is placed in standby mode
where the maximum Icc standby current is 100 /LA
with CMOS input signals. The standby operation disables much of the device's circuitry and substantially
reduces device power consumption. The outputs
(DO[0:15) or 00[0:7)) are placed in a high-impedance state independent of the status of the OE#
signal. When the 4-Mbit boot block flash .family is
deselected during erase or program functions, the
devices will continue to perform' the erase or program function and consume program or erase active
power until program or erase is completed.
4-151
28F400BX-T/B,28F004BX-T/B
4.5.4 RESETIDEEP POWERDOWN
The 4-Mbit boot block flash family supports a typical
lee of 0.2 p..A in deep power-down mode. One of the
target markets for these devices is in portable equipment where the power consumption of the machine
is of prime importance. The 4-Mbit boot block flash
family has a RP# pin which places the device in the
deep powerdown mode. When RP# is at a logic-low
(GND ±0.2V), all circuits are turned off and the device typically draws 0.2 p..A of Vee current.
During read modes, the RP# pin going low deselects the memory and places the output drivers in a
high impedance state. Recovery from the deep power-down state, requires a maximum of 300 ns to access valid data (tpHQV).
During erase or program modes, RP# low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
corrupted by the RP# function. As in the read mode
above, all internal circuitry is turned off to achieve
the 0.2 p,A current level.
RP# transitions to VIL or turning power off to the
device will clear the status register.
This use of RP# during system reset is important
with automated write/erase devices. When the system comes out of reset it expects to read from the
flash memory. Automated. flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel's
Flash Memories allow proper CPU initialization following a system reset through the use of the RP#
input. In this application RP# is controlled by the
same RESET# signal that resets the system CPU.
4.6 Power-up Operation
The 4-Mbit boot block flash family is designed to
offer protection against accidental block erasure or
programming during power transitions. Upon powerup the 4-Mbit boot block flash family is indifferent as
to which power supply, Vpp or Vee, powers-up first.
Power supply sequencing is not required.
The 4~Mbit boot block flash family ensures the CUI is
reset to the read mode on power-up.
In addition, on power-up the user must either drop
CE # low or present a new address to ensure valid
data at the outputs.
A system designer must guard against spurious
writes for Vee voltages above VLKO when Vpp is
4-152
active. Since both WE # and CE # must be low for a
command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides
an added level of protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. Finally
the device is disabled until RP# is brought to VIH,
regardless of the state of its control inputs. This feature provides yet another level of memory protection.
4.7 Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling methods. System
designers are interested in 3 supply current issues:
• Standby current levels (lees)
• Active current levels (leeR)
• Transient peaks produced by falling and rising
edges of CE # .
Transient current magnitudes depend on the device
,outputs' capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 p..F ceramic capacitor
connected between each Vee and GND, and between itsVpp and GND. These high frequency, lowinherent inductance capacitors should be placed as
close as possible to the package leads.
4.7.1 Vpp TRACE ON PRINTED CIRCUIT
BOARDS
Writing to flash memories while they reside in the
target system, requires special consideration of the
Vpp power supply trace by the printed circuit board
designer. The Vpp pin supplies the flash memory
cells current for programming and erasing. One
should use similar trace widths and layout considerations given to the Vee power supply trace. Adequate Vpp supply traces and decoupling will decrease spikes and overshoots.
4.7.2 Vee. Vpp AND RP# TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by Vpp or CE# transitions or WSM actions. Its state upon power-up, after exit from deep power-down mode or after Vee
transitions below VLKO (Lockout voltage), is Read
Array mode.
After any word/byte write or block erase operation is
complete and even after Vpp transitions down to
VPPL, the CUI must be reset to Read Array mode via
the Read Array command when accesses to the
flash memory are desired.
I
28F400BX-T IB,
ABSOLUTE MAXIMUM RATINGS*
28F004BX~T IB
.NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Commercial Operating Temperature
During Read ..•....•.....•...... O°C to 70°C(1)
During Block Erase
and Word/Byte Write ............... O°C to 70°C
Temperature Under Bias ....... -10°C to + 80°C
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Extended Operating Temperature
. During Read .•.....•.....•... -40°C to + 85°C
During Block Erase
and Word/Byte Write .•.•..... -40°C to + 85°C
Temperature Under Bias ....... - 40°C to + 85°C
Storage Temperature ...•..••.. - 65°C to + 125°C
Voltage on Any Pin
(except Vee, Vpp, Ag and RP#)
,
with Respect.to GND ..•.. : .. -2.0V to +7.0V(2)
Voltage on Pin RP# or Pin Ag
with Respect to GND ....• - 2.0V to + 13.5V(2, 3)
Vpp Program Voltage with Respect
to GND during Block Erase
and Word/Byte Write ..... - 2.0V to + 14.0V(2, 3)
Vee Supply Voltage
with Respect to GND .•..•... - 2.0V to + 7.0V(2)
Output Short Circuit Current. ...•......•. 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns.
Maximum De voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee + 2.0V for
periods <20 ns.
3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods <20 ns. Maximum De voltage on RP# or As may
overshoot to 13.5V for periods < 20 ns.
4. Output shorted for no more than one second. No more than ·one output shorted at a time.
5. 10% Vee specifications reference the 28F400BX-SO/28F004BX-SO in their standard test configuration, and the
28F400BX-BO/2BF004BX-BO.
S. 5% Vee specifications reference the 2BF400BX-SO/2BF004BX-SO in their high speed test configuration.
OPERATING CONDITIONS
Symbol
Parameter
Notes
Min
Max
Units
°C
TA
Operating Temperature
0
70
Vee
Vee Supply Voltage ~1 0%)
5
4.50
5.50
V
Vee
Vee Supply Voltage (5%)
6
4.75
5.25
V
DC CHARACTERISTICS
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
III
Input Load Current
1
±1.0
/LA
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage Current
1
±10
/LA
Vee = Vee Max
VOUT = VeeorGND
I
I
4-153
28F400BX-T/B,28F004BX-T/B
DC CHARACTERISTICS
Symbol
Ices
(Continued)
Parameter
Vee Standby Current
Notes Min Typ
1,3
Max
Unit
Test Conditions
1.5
rnA Vee = Vee Max
CE# = RP# = VIH
100
p.A Vee = Vee Mroc
CE# = RP# = Vee ±0.2V
28F400BX:
BYTE# = Vee ±0.2VorGND
leeo
Vee Deep Powerdown Current
leeR
Vee Read Current for
28F400BX Word-Wide
and Byte-Wide Mode
and 28F004BX
Byte-Wide Mode
1
0.20
1.2
p.A RP# = GND ±0.2V
1,5,
6, 10
20
55
rnA Vee = Vee Max, CE# = GND
f (Max) = 10 MHz, f (Typ) = 5 MHz
lOUT = o rnA
CMOS Inputs
20
60
rnA Vee = Vee Max, CE# = VIL
f (Max) = 10 MHz, f (Typ) = 5 MHz
lOUT = o rnA
TTL Inputs
lecw
Vee Word/Byte Write Current
1,4
65
rnA Word or Byte Write in Progress
IeeE
Vee Block Erase Current
1,4
30
rnA Block Erase in Progress
leeES
Vee Erase Suspend Current
1,2
10
rnA Block Erase Suspended,
CE# = VIH
Ipps
Vpp Standby Current
1
±15
p.A Vpp
IpPD
Vpp Deep PowerDown Current
1
5:0
p.A RP# = GND ±0.2V
IpPR
Vpp Read Current
1
200
p.A Vpp> Vee
Ippw
VppWord Write Current
1,4
40
rnA Vpp = VPPH
5
s:
Vee
Word Write in Progress
Ippw
Vpp Byte Write Current
1,4
30
rnA Vpp = VPPH
Byte Write in Progress
IpPE
Vpp Block Erase Current
1,4
30
rnA Vpp = VPPH
Block Erase in Progress
IpPES
Vpp Erase Suspend Current
1
200
p.A Vpp = VPPH
Block Erase Suspended
IRP#
RP# Boot Block Unlock
Current
1,4
liD
Ag Intelligent Identifier Current 1,4
VIO .
Ag Intelligent Identifier Voltage
11.5
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
4-154
500
p.A RP# = VHH
500
p.A Ag= VIO
13.0
V
0.8
V
Vee
+ 0.5
0.45
V
V Vee = Vee Min
IOL = 5.8 rnA
I
28F400BX-T IB, 28F004BX-T IB
DC CHARACTERISTICS
Symbol
(Continued)
Parameter
VOH1
Output High Voltage (TTL)
VOH2
Output High Voltage (CMOS)
Notes
Min
Typ Max Unit
Test Conditions
2.4
V
Vee = Vee Min
IOH = -2.5 mA
0.85 Vee
V
IOH = -2.5 mA
Vee = Vee Min
IOH = -100 fLA
Vee = Vee Min
Vee - 0.4
VPPL
Vpp during Normal Operations
3
0.0
VpPH
Vpp during Erase/Write Operations
7
11.4
12.0 12.6
V
VPPH
Vpp during Erase/Write Operations
8
10.8
12.0 13.2
V
VLKO
Vee Erase/Write Lock Voltage
2.0
VHH
RP# Unlock Voltage
11.5
V
6.5
V
13.0
V
Boot Block Write/Erase
EXTENDED TEMPERATURE OPERATING CONDITIONS
Symbol
Parameter
TA
Operating Temperature
Vee
Vee Supply Voltage (10%)
Notes
Min
Max
Unit
5
-40
85
°C
4.50
5.50
V
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION
Symbol
III
ILO
Ices
IceD
I
Parameter
Input Load Current
. Output Leakage Current
Vee Standby Current
Vee Deep Power-Down Current
Notes Min Typ
Test Conditions
Max
Unit
1
±1.0
fLA
Vee = Vee Max
VIN = Vee or GND
1
±10
fLA
Vee = Vee Max
VOUT = VeeorGND
1,3
1.5
mA
Vee = Vee Max
CE# = RP# = VIH RP#
100
fLA
Vee = Vee Max
CE# = RP# = Vee ±0.2V
28F400BX:
BYTE# = Vee ±0.2Vor GND
20
fLA
RP# = GND ±0.2V
1
0.20
4-155
28F400BX-T/B,28F004BX-T/B
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION (Continued)
Symbol
ICCR
Parameter
Vcc Read Current for 28F400BX
Word-Wide and Byte-Wide Mode
28F004BX Byte-Wide Mode
Notes Min Typ Max Unit
1,5,
6,10
•
Test Conditions
60
rnA
Vcc = Vcc Max, CE# = GND
f = 10 MHz, lOUT = 0 rnA
CMOS Inputs
65
rnA
Vcc = Vcc Max, CE# = VIL
f = 10 MHz, lOUT = 0 rnA
TIL Inputs
Iccw
Vcc Word Write Current
1
70
rnA
Word Write in Progress
ICCE
Vcc Block Erase Current
1
40
rnA
Block Erase in Progress
ICCES
Vcc Erase Suspend Current
10
rnA
Block Erase Suspended,
CE# = VIH
Ipps
Vpp Standby Current
1
±15
/-LA
Vpp
IpPD
Vcc Deep Power-Down Current
1
5.0
/-LA
RP#
IpPR
Vpp Read Current
1
200
/-LA
Vpp >Vcc
Ippw
Vpp Word Write Current
1
40
rnA
Vpp = VPPH
Word Write in Progress
IppW
Vpp Byte Write Current
1
30
rnA
Vpp = VPPH
Byte Write in Progress
4-156
1,2
5
s:
Vcc
=
GND ±0.2V
I
28F400BX·T IB, 28F004BX·TIB
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION
Symbol
Parameter
Notes
Min
Typ
Max
(Continued)
Test Conditions
Unit
IpPE
Vpp Block Erase Current
1
30
mA Vpp = VPPH
Block Erase in Progress
IpPES
Vpp Erase Suspend Current
1
200
p,A Vpp = VPPH
Block Erase Suspended
IRP#
RP# Boot Block Unlock
Current
1,4
500
p,A RP#
500
p,A Ag
110
Ag Intelligent Identifier Current
VIO
Ag Intelligent Identifier Current
11.5
13.0
V
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage (TTL)
VOH2
Output High Voltage (CMOS)
1
Vee
+ 0.5
= VIO
V
Vee = Vee Min
IOL = 5.8 mA
2.4
V
Vee = Vee Min
IOH = -2.5mA
0.85 Vee
V
IOH = -2.5 mA
Vee = Vee Min
VPPL
Vpp during Normal Operations
3
0.0
VpPH
Vpp during Erase/Write Operations
7
11.4
VPPH
Vpp during Erase/Write Operations
8
10.8
VLKO
Vee Erase/Write Lock Voltage
2.0
VHH
RP# Unlock Voltage
11.5
Symbol
VHH
V
0.45
IOH = -100 p,A
Vee = Vee Min
Vee - 0.4
CAPACITANCE(4)
=
6.5
V
12.0
12.6
V
12.0
13.2
V
13.0
V
V
Boot Block Write/Erase
TA = 25°C, f = 1 MHz
Parameter
Typ
Max
Unit
Conditions
CIN
Input Capacitance
6
8
pF
VIN = OV
COUT
Output Capacitance
10
12
pF
VOUT = OV
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vce = 5.0V, Vpp = 12.0V, T = 25'e. These currents
are valid for all product versions (packages and speeds).
2. leeES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
of leeEs and leeR.
3. Block Erases and Word/Byte Writes are inhibited when Vpp = VpPL and not guaranteed in the range between VPPH and
VPPL·
4. Sampled .. not 100% tested.
5. Automatic Power Savings (APS) reduces leeR to less than 1 mA typical in static operation.
6. CMOS Inputs are either Vee ±0.2V or GND ±0.2V. TTL Inputs are either VIL or VIH.
7. Vpp = 12.0V ± 5% for applications requiring 100,000 block erase cycles.
8. Vpp = 12.0V ± 10% for applications requiring wider Vpp tolerances at 100 block erase cycles.
g. For the 28F004BX address pin A10 follows the eOUT capacitance numbers.
10. leeR typical is 20 mA for X16 Active Read Current.
I
4-157
28F400BX-T IB, 28F004BX-T IB
STANDARD TEST CONFIGURATION(1)
STANDARD
AC INPUT/OUTPUT REFERENCE WAVEFORM
STANDARD
AC TESTING LOAD CIRCUIT
1.3V
X::: > TESTlroINlS<
I
Vee
-I
......
GND
VIH
I
1
!PHDV
~1lI
- -----------·1
\
."
o
o
~
RP# (p)
!
~
I\)
CC)
III
><
VIL
I
290451-15
-I
......
III
28F400BX-T IB, 28F004BX-T IB
75
75
70
65
:t'
60
55
50
<-5
u
2
45
60
V
<-
20
,/
~
u
2
-0- ODC
-0- 25 DC
-I>- 70 DC
I
I
5
1 2 3
4 5
-5
/
25
6 7 8
/
50
V'
30
L..-'
55
,
35
10
65
I(
40
15
70
/
......
45
40
35
f--
30
c-c--
25
it"
20
V'
15
I I
I
10
5
9 10 11 12 13 14 15 16
I I
I I
t'"
•1
2 3 4 5
FREQUENCY (MHz)
f-c-0- ODC
-0- 25 DC f - -I>-70 DC c--
6
7 8
I I
I I
9 10 11 12 1314 15 16
FREQUENCY (MHz)
290451-27
290451-26
Figure 18. Icc (RMS) vs Frequency
(Vee = 5.5V) for x8 Operation
Figure 17. ICC (RMS) vs Frequency
{Vee = 5.5V for x16 Operation
100
95
~
90
85
"i,;'
..5
u
u
....'"
,/
80
75
70
~
65
60
/
~
C
./V
/
. /V
......-' r
./
-0- 28F400BX/28F004BX-60
-0- 28F400BX/Z8F004BX-80
55
50
30 50
100
150
200
250
OUTPUT CAPACITANCE (pF)
290451-28
Figure 19. T Ace vs Output Load Capacitance
4-162
I
-
DEVICE
ADDRESS SELECTION
STANDBY
"'II
~
c
;
II)
VIH
ADDRESSES (A)
DOa -D014
'll'I'/YY'X'l
....-
I AVAV
VIH
CE# (c)
'Ij,
....
VIL
I
3"
5"
CQ
C
iii"
CQ
OE# (G)
iil
VIL
0
VIH
.....,
IAVFL. : hFL
VIH
3
IJI
0
:T
...
:II
8YTE# (F)
VIL
ID
\cLOY
1
D!
C.
D!
:::s
c.
=E
~"
CD
0
"..,ID
...0"
:::s
.....,
VIH
DATA (DOa-D~)
VIL
HIGH Z
DATA OUTPUT
ON DQo-D<
DATA (DOa-DOI .)
I
-I
0
......
,Pl
II)
CD
IAVOV
"'II
~
I\)
CD
0
0
IJI
X
!
0>
Co)
D01S/A.. 1
ADDRESS
INPUT
."
0
0
HIGH Z
.j:o.
OJ
290451-29
><
I
-I
......
OJ
28F400BX-T IB, 28F004BX-T IB
AC CHARACTERISTICS-WE # Controlled Write Operations(1)
Vee
± 5%
Vee
± 10%
28F400BX-60(9)
28F004BX-60(9)
Versions
Symbol
Parameter
tAVAV
twe
Write Cycle Time
tpHWL
tps
RP# High
28F400BX-60(10) 28F400BX-80(10) 28F400BX-120(10) Unit
28F004BX-60(10) 28F004BX-80(10) 28F004BX-120(10)
Notes
Min
Max
Min
Max
Min
Max
Min
Max
60
70
80
120
ns
215
215
215
215
ns
0
0
0
0
ns
Recovery to
WE# Going Low
tELWL
tes
CE# Setup to WE#
Going Low
tPHHWH tpHS RP# VHH Setup to
WE# Going High
6,8
100
100
100
100
ns
tVPWH
tvps VPP Setup to WE#
Going High
5,8
100
100
100
100
ns
tAVWH
tAS
3
50
50
50
50
ns
4
50
50
50
50
ns
Address Setup to
WE# GOing High
tOVWH
tos
Data Setup to WE#
Going High
tWLWH
twp
WE# Pulse Width
tWHOX
tOH
Data Hold from
50
50
60
60
ns
4
0
0
0
0
ns
3
10
10
10
10
ns
10
10
10
10
ns
10
20
20
20
ns
2,5
6
6
6
6
",s
2,5,6
0.3
0.3
0.3
0.3
s
2,5
0.3
0.3
0.3
0.3
s
2,5
0.6
0.6
0.6
0.6
s
WE# High
tWHAX
tAH
Address Hold from
WE# High
tWHEH
tcH
CE# Hold from
WE# High
tWHWL tWPH WE# Pulse
Width High
tWHOV1
Duration of
Word/Byte
Programming
Operation
tWHOV2
Duration of Erase
Operation (Boot)
tWHOV3
Duration of Erase
Operation
tWHOV4
Duration of Erase
(Parameter)
Operation (Main)
tOWL
tVPH VPP Hold from
ValidSRD
5,8
0
0'
0
0
ns
tOVPH
tpHH RP# VHH Hold
from Valid SRD
6,8
0
0
0
0
ns
tpHBR
Boot-Block
7,8
100
100
100
100
ns
Relock Delay
4-164
I
28F400BX-T /8, 28F004BX-T /B
AC CHARACTERISTICS-WE # Controlled Write Operations(1) (Continued)
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during Read Mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations.
3. Refer to command definition table for valid AIN.
4. Refer to command definition table for valid DIN.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For Boot Block Program/Erase, RP# should be held at VHH until operation completes successfully.
7. Time tpHBR is required for successful relocking of the Boot Block.
B. Sampled but not 100% tested.
9. See High Speed Test Configuration.
10. See Standard Test Configuration.
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE Vpp = 12.0V ±5%
Parameter
28F400BX-60
28FOO4BX-60
Notes
Min
28f400B}(-120
28FOO4B)(-120
28F400BX-80
28FOO4B}(-80
Typ(1)
Mal(
Min
Typ(1)
Mal~
Min
Unit
TVp(1)
Male
Boot/Parameter
Block Erase Time
2
1.0
7
1.0
7
1.0
7
s
Main Block
Erase Time
2
2.4
14
2.4
14
2.4
14
s
Main Block Byte
Program Time
2
1.2
4.2
1.2
4.2
1.2
4.2
s
Main Block Word
Program Time
2
0.6
2.1
0.6
2.1
0.6
2.1
s
NOTES:
1. 25'C
2. Excludes System-Level Overhead.
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE Vpp = 12.0V ±10%
Parameter
28F400B}(-60
28FOO4BX-60
Notes
Min
28F400B)(-120
28FOO4BX-120
28F4008)(-80
28FOO4B){-80
Typ(1)
Mal(
Min
Typ(1)
Malt
Min
Typ(1)
Mal(
Unit
Boot/Parameter
Block Erase Time
2
5.8
40
5.8
40
5.8
40
s
Main Block
Erase Time
2
14
60
14
60
14
60
s
Main Block Byte
Program Time
2
6.0
20
6.0
20
6.0
20
s
Main Block Word
Program Time
2
3.0
10
3.0
10
3.0
10
s
NOTES:
1. 25'C
2. Excludes System-Level Overhead.
I
4-165
28F400BX·T IB, 28F004BX·T IB
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS-WE # Controlled Write Operations(1)
T2SF400BX·SO(9)
T2SFOO4BX·SO(9)
Versions(4)
Symbol
Parameter
Notes
Min
Unit
Max
80
ns
220
ns
0
ns
100
ns
tAVAV
twc
Write Cycle Time
tPHWL
tps
RP# High Recovery to
WE # Going Low
tELWL
tcs
CE# Setup to WE# Going Low
tpHHWH
tpHS
RP# VHH Setup to WE#
Going High
6,8
tVPWH
tvps
Vpp Setup to WE# Going High
5,8
100
ns
tAVWH
tAS
Address Setup to WE #
Going High
3
60
ns
tOVWH
tos
Data Setup to WE# Going High
4
60
ns
tWLwH
twp
WE# Pulse Width
60
ns
tWHOX
tOH
Data Hold from WE# High
4
0
ns
tWHAX
tAH
Address Hold from WE # High
3
ns
tWHEH
tCH
CE# Hold from WE# High
10
'10
tWPH
WE# Pulse Width High
20
ns
2,5
7
IJ-s
tWHWL
tWHOV1
Duration of Word/Byte
Programming Operation
ns
tWHOV2
Duration of Erase Operation (Boot)
2,5,6
0.4
s
'tWHOV3
Duration of Erase Operation
(Parameter)
2,5
0.4
s
tWHOV4
Duration of Erase Operation (Main)
2,5
0.7
s
tOWL
tVPH
Vpp Hold from Valid SRD
5,8
0
ns
tOVPH
tpHH
RP# VHH Hold from Valid SRD
6,8
0
ns
Boot-Block Relock Delay
7,8
tpHBR
4-166
100
ns
I
28F400BX·T IB, 28F004BX·T IB
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS-WE #: Controlled Write Operations(1) (Continued)
NOTES:
1. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during Read Mode.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally which includes verify and margining operations.
3. Refer to command definition table for valid AIN.
4. Refer to command definition table for valid DIN.
5. Program/Erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For Boot Block Program/Erase, RP# should be held at VHH until operation completes successfully.
7. Time tpHBR is required for successful relocking of the Boot Block.
8. Sampled but not 1000/0 tested.
9. See Standard Test Configuration.
EXTENDED TEMPERATURE OPERATION
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE Vpp
Parameter
= 12.0V ±5%·
T28F400BX·80
T28FOO4BX-80
Notes
Min
Unit
Typ(1)
Max
Boot/Parameter
Block Erase Time
2
1.5
10.5
s
Main Block
Erase Time
2
3.0
18
s
Main Block Byte
Program Time
2
1.4
5.0
s
Main Block Word
Program Time
2
0.7
2.5
s
NOTES:
1. 25°C
2. Excludes System-Leliel Overhead.
I
4-167
I\)
!
(l)
(l)
vee
fl...
.
POWER-UP
& STANDBY
WRITE PROGRAM OR
ERASE SETUP COMMAND
WRITE
VALID ADDRESS & DATA (PROGRAM)
OR ERASE CONFIRM COMMAND
011
AUTOMATED PROGRAM
OR ERASE DELAY
READ STATUS
REGISTER DATA
"T1
WRITE READ ARRAY
·COMMAND
""oo
m
VIH
ADDRESSES (A)
~N
XI
><
.!.t
.....
~
VIL
~m
I\,)
I\)
~I~
011
VIH
"T1
o
CE# (E)
o
""
VIL
-
m
><
CD
!I
~
VIH
m
OE# (G)
....
:e
VIL
III
I-
tWHQY1,2,3,4
-I
VIH
tl...
WE# (W)
VIL
a.
m
III
1/1
II
VIH
DATA (D/Q)
VIL
o·
::I
1/1
~
VHH
'110
6.SV
VIH
m
0
0
RP# (p)
::I
...
e.
VIL
CD
tYPWH
a.
II
,f~~~-·------------------------
VpPH
v
PP
--
(v) VPPL
VIH
VIL
290451-16
€:
@
28F400BX-T/B,28F004BX-T/B
AC CHARACTERISTICS-CE#-CONTROLLED WRITE OPERATIONS(1,9)
28F400BX-60(10)
Vee ± 5%
28F004BX-60(10)
Versions
28F400BX-60(11) 28F400BX-80(11) 28F400BX-120(11) Unit
28F004BX-60(11) 28F004BX-80(11) 28F004BX-120(11)
Vee ± 10%
Symbol
Parameter
Notes
Min
tAVAV
twc Write Cycle Time
60
tpHEl
tps
RP# High
Recovery
tWlEl
tws WE# Setup to
CE# Going Low
Max
Min
Max
Min
Max
Min
Max
70
80
120
ns
215
215
215
215
ns
0
0
0
0
ns
6,8
100
100
100
100
ns
5,8
100
100
100
100
ns
to CE# Going Low
tpHHEH tPHS RP# VHH Setup to
CE # Going High
tVPEH
tvps Vpp Setup to CE#
Going High
tAVEH
tAS
Address Setup to
CE# Going High
3
50
50
50
50
ns
tOVEH
tos
Data Setup to
CE# Going High
4
50
50
50
50
ns
tElEH
tcp
CE# Pulse Width
50
50
60
60
ns
tEHOX
tOH
Data Hold from
CE# High
4
0
0
0
0
ns
tEHAX
tAH
Address Hold
3
10
10
10
10
ns
10
10
10
10
ns
10
20
20
20
ns
2,5
6
6
6
6
,..s
Duration of Erase
Operation (Boot)
2,5,6
0.3
0.3
0.3
0.3
s
Duration of Erase
2,5
0.3
0.3
0.3
0.3
s
2,5
0.6
0.6
0.6
0.6
from CE# High
tEHWH tWH WE# Hold from
CE# High
tEHEl
tEHOV1
tCPH CE# Pulse
Width High
Duration of Word/
Byte Programming
Operation
tEHOV2
tEHOV3
Operation
(Parameter)
tEHOV4
Duration of Erase
Operation (Main)
S
\
tOWl
tVPH Vpp Hold from
ValidSRD
5,8
0
0
0
0
ns
tOVPH
tpHH RP# VHH Hold
from Valid SRD
6,8
0
0
0
0
ns
tpHBR
I
Boot-Block
Relock Delay
7
100
100
100
100
ns
4-169
28F400BX-T IB, 28F004BX-T IB
AC CHARACTERISTICS-CE # -CONTROLLED WRITE OPERATIONS(1, 9) (Continued)
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE # waveform.
2, 3, 4, 5, 6, 7, 8: Refer to AC Characteristics notes for WE # -Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See High Speed Test Configuration.
11. See Standard Test Configuration.
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS-CE # -CONTROLLED WRITE OPERATIONS(1,9)
T28F400BX-80(10)
T28FOO4BX-80(10)
Versions
Symbol
Parameter
Notes
tAvAV
twc
Write Cycle Time
tpHEL
tps
RP# High Recovery to CE# Going Low
tWLEL
tws
WE # Setup to CE # GOing Low
tpHHEH
tpHS
RP# VHH Setup to CE # Going High
tVPEH
tvps
Vpp Setup to CE# Going High
tAVEH
tAS
Address Setup to CE # Going High
3
tOVEH
tos
Data Setup to CE# Going High
4
tELEH
tcp
CE # Pulse Width
tEHOX
tOH
Data Hold from CE # High
4
tEHAX
tAH
Address Hold from CE # High
3
tEHWH
tWH
WE# HoldfromCE# High
tCPH
CE # Pulse Width High
tEHEL
tEHOV1
Duration of Word/Byte Programming
Operation
tEHOV2
Duration of Erase Operation (Boot)
tEHOV3
Duration of Erase Operation (Parameter)
Duration of Erase Operation (Main)
lEHOV4
IOWL
tVPH
Vpp Hold from Valid SRD
IOVPH
tpHH
RP# VHH Hold from Valid SRD
lpHBR
Boot-Block Relock Delay
6,8
5,8
2,5
2,5,6
2,5
2,5
5,8
6,8
7
Min
Unit
Max
80
220
0
100
100
60
60
60
0
10
10
20
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/-Ls
0.4
0.4
0.7
0
0
s
s
s
ns
ns
100
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE# in systems where
CE # defines the write pulse-width (within a longer WE # timing waveform), all set-up, hold and inactive WE # times should
be measured relative to the CE# waveform.
2,3,4, 5, 6, 7, 8: Refer to AC Characteristics for WE#-Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See Standard Test Configuration.
4-170
I
-
Yee POWER-UP
WRITE PROGRAM OR
&: STANDBY
ERASE SETUP COMMAND
!!
..
CD
C
CD
'"
~
i
;31
:.-
p
II
WRITE
YALID ADDRESS &: DATA (PROGRAM)
OR ERASE CONFIRM COMMAND
AUTOMATED PROGRAM
OR ERASE DELAY
READ STATUS
REGISTER DATA
€:
WRITE READ ARRAY
COMMAND
YIH
ADDRESSES (A)
~N
@>
YI.
'rHAX
YIH
WE# (W)
YI.
YIH
OE# (G)
YI.
3
i-
III
il
--
'rHQY1,2,3,4
-i
YIH
CE# (E)
YI.
CD
11\
~
a.
!0~I
YIH
DATA (D/a)
YI.
'a
CD
iii
c!:
0
YHH
III
6.5Y
YIH
RP# (P)
~
nIII
'110
00
YI.
2-
YpPH
...
~
1,f:~H~--
____ ----------------
..g
N
CII
"TI
m
~
tYPEH
.!D
N
CII
CD
a.
E
a:
CD
:!:
:t
.!!.
..
;!J
Y (Y) YpP •
PP
YIH
o
YI •
290451-17
m
><
.....!tm
28F400BX-T/B,28F004BX-T/B
ORDERING INFORMATION
OPERATING TEMPERATURE
T
= EXTENDED TEMP
BLANK = COMMERCIAL TEMP
PACKAGE
E = STANDARD 56 LEAD TSOP
PA = 44 LEAD PSOP
TB = 44 LEAD PSOP, EXTENDED TEMP
60 ns
80 ns
120 ns
290451-18
VALID COMBINATIONS:
E28F400BX-T60
E28F400BX-B60
E28F400BX-T80
E28F400BX-B80
E28F400BX-T120
E28F400BX-B120
PA28F400BX-T60
PA28F400BX-B60
PA28F400BX-T80
PA28F400BX-B80
PA28F400BX-T120
PA28F400BX-B120
TE28F400BX-T80
TE28F400BX-B80
TB28F400BX-T80
TB28F400BX-B80
IIE12181F1010141Blxl-IT16101
,---------" T
OPERATING TEMPERATURE
T
EXTENDED TEMP
BLANK = COMMERCIAL TEMP
=
PACKAGE
E
STANDARD 40 LEAD TSOP
L....---J
L
=
ACCESS SPEED (ns)
60 ns
80ns
120 ns
290451-30
VALID COMBINATIONS:
E28F004BX-T60
E28F004BX-B60
4-172
E28F004BX-T80
E28F004BX-B80
TE28F004BX-T80
TE28F004BX-B80
E28F004BX-T120
E28F004BX-B120
I
28F400B}{-T /B, 28F004BX-T /B
ADDITIONAL INFORMATION
Order Number
Document
292130
AB-57 "Boot Block Architecture for Safe Firmware Updates"
292154
AB-60 "2/4/8-Mbit SmartVoltage BootBlack Flash Memory Family"
292098
AP-363 "Extended Flash BIOS Concepts for Portable Computers"
292148
AP-604 "Using Intel's Boot Block Flash Memory Parameter Blocks to Replace
EEPROM"
290448
28F002/200BX-T IB 2-Mbit Boot Block Flash Memory Datasheet
290449
28F002/200BL-T IB 2-Mbit Low Power Boot Block Flash Memory Datasheet
290450
28F0041 400BL-T IB4-Mbit Low Power Boot Block Flash Memory Datasheet
290531
2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290530
4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290539
8-Mbit SmartVoltage Boot Blocl< Flash Memory Family Datasheet
REVISION HISTORY
Number
I
Description
-001
Original Version
-002
Removed -70 speed bin.
Integrated -70 characteristics into -60 speed bin.
Added Extended Temperature characteristics.
Modified BYTE# Timing Diagram.
-003
PWD renamed to RP# for JEDEC standardization compatibility.
Combined Vcc Read current for 28F400BX Word-Wide Mode and Byte-Wide Mode and
28F004BX Byte-Wide Mode in DC Characteristics tables.
Added Boot Black Unlock Current specifications in DC Characteristics tables.
Improved ICCR and Iccw in DC Characteristics: Extended Temperature Operation table.
Improved tAVAV, tAVQV, tELQV, tGLQV, tEHQZ, tGHQZ, tFHQV and tFLQZ specifications for
Extended Temperature Operations AC Characteristics-Read and Write Operations.
-004
Added specifications for 120 ns access time product version; 28F400BX-120 and
28F004BX-120.
Included permanent change on write timing parameters for -80 ns product versions. Write
pulse width (twp and tcp) increases from 50 ns to 60 ns. Write pulse width high (tWPH and
tCPH) decreases from 30 ns to 20 ns. Total write cycle time (twd remains unchanged.
Added ICCR test condition note for typical frequency value in DC Characteristics table.
Added IOH CMOS specification.
Added 28F400BX interface to Intel386™EX Embedded Processor block diagram.
Added description of how to design for upgrading to SmartVoltage Boot Block products.
4-173
28F400BL-T IB, 28F004BL-T IB
4-MBIT!{256K x 16, 512K x 8) LOW POWER BOOT BLOCK
FLASH MEMORY FAMILY
• Low Voltage Operation for Very Low
Power Portable Applications
- Vee = 3.0V-3.6V Read
- Vee = 3.15V-3.6V Program/Erase
• SRAM-Compatible Write Interface
• Automatic Power Savings Feature
- O.S mA typical lee Active Current in
Static, Operation
• Expanded Temperature Range
- - 20°C to 70°C
•
• xS/x16 Input/Output Architecture
- 2SF400BL-T, 2SF400BL-B
- For High Performance and High ,
Integration 16-bit and 32-bit CPUs
Very High-Performance Read
-150 ns Maximum Access Time
- 65 ns Maximum Output Enable Time
•
Low Power Consumption
- 15 mA Typical Active Read Current
•
Reset/Deep Power-Down Input:
- 0.2 p.A lee Typical
- Acts as Reset for Boot Operations
• xS-only Input/Output Architecture
- 2SF004BL-T, 2SF004BL-B
- For Space Constrained S-bit
Applications
• Upgradeable to Intel's SmartVoltage
Products
• Optimized High Density Blocked
Architecture
-One 16-KB Protected Boot Block
- Two S-KB Parameter Blocks
- One 96-KB Main Block
-Three 12S-KB Main Blocks
- Top or Bottom Boot Locations
• Extended Cycling Capability
-10,000 Block Erase Cycles'
• Automated Word/Byte Write and Block
Erase
- Command User Interface
- Status Registers
- Erase Suspend Capability
4-174
• Write Protection for Boot Block
•
Hardware Data Protection Feature
- Erase/Write Lockout During Power
Transitions
•
Industry Standard Surface Mount
Packaging
- 2SF400BL: JEDEC ROM
Compatible
44-Lead PSOP
56-Lead TSOP
- 2SF004BL: 40-Lead TSOP
•
12V Word/Byte Write and Block Erase
- Vpp = 12V ± 5% Standard
• ETOX III Flash Technology
-3.3V Read
November 1994
Order Number: 290450-004
28F400BL-T IB, 28F004BL-T IB
Intel's 4-Mbit Low Power Flash Memory Family is an extension of the Boot Block Architecture which includes
block-selective erasure, automated write and erase operations and standard microprocessor interface. The
4-Mbit Low Power Flash Memory Family enhances the Boot Block Architecture by adding more density and
blocks, x8/x16 input/output control, very low power, very high speed, an industry standard ROM compatible
pinout and surface mount packaging. The 4-Mbit low power flash family opens a new capability for 3V batteryoperated portable systems and is an easy upgrade to Intel's 2-Mbit Low Power Boot Block Flash Memory
Family.
The Intel 28F400BL-T IB are 16-bit wide low power flash memory offerings. These high density flash memories
provide user selectable bus operation for either 8-bit or 16-bit applications. The 28F400BL-T and 28F400BL-B
are 4, 194,304-bit non-volatile memories organized as either 524,288 bytes or 262,144 words of information.
They are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the
industry standard ROM IE PROM pinout. The Intel 28F004BL-T IB are 8-bit wide low power flash memories
with 4,194,304 bits organized as 524,288 bytes of information. They are offered in a 40-Lead TSOP package,
which is ideal for space-constrained portable systems.
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
wordlbyte write and block erasure. The 28F400BL-T 128F004BL-T provide block locations compatible with
Intel's Low Voltage MCS-186 family, i386™, i486™ microprocessors. The 28F400BL-B/28F004BL-B provide
compatibility with Intel's 80960KX and 80960SX families as well as other low voltage embedded microprocessors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 150 ns; these 4-Mbit low power flash devices are very high performance memories at
3.3V which interface to a wide range of low voltage microprocessors and microcontrollers. A deep powerdown mode lowers the total Vee power consumption to 0.66 p.W which is critical in handheld battery powered
systems such as Handy Cellular Phones. For very high speed applications using a 5V supply, refer to the Intel
28F400BX-T IB, 28F004BX-T IB 4-Mbit Boot Block Flash Memory family datasheet.
Manufactured on Intel's 0.8 micron ETOX III process, the 4-Mbit flash memory family provides world class
quality, reliability and cost-effectiveness at the 4 Mbit density level.
I
4-175
28F400BL-T IB, 28F004BL-T IB
1.0 PRODUCT FAMILY OVERVIEW
Throughout this datasheet 28F400BL refers to both
the 28F400BL-T and 28F400BL-B devices and
28F004BL refers to both the 28F004BL-T and
28F004BL-B devices. The 4-Mbit flash family refers
to both the 28F400BL and 28F004BL products. This
datasheet comprises the specifications for four separate products in the 4-Mbit flash family, Section 1
provides an overview of the 4-Mbit flash family including applications, pinouts and pin descriptions.
Sections 2 and 3 describe in detail the specific memory organizations for the 28F400BL and 28F004BL
products respectively, Section 4 combines a description of the family's principles of operations. Fi. nallysection 5 describes the family's operating
specifications.
1.2 Main Features
The 28F400BLl28F004BL boot block flash memory
family is a very high performance 4-Mbit (4,194,304
bit) memory family organized as either 256 KWords
(262,144 words) of 16 bits each or 512 Kbytes
(524,288 bytes) of 8 bits each.
Seven Separately Erasable Blocks including a
Hardware-Lockable boot block (16,384 Bytes),
two parameter blocks (8,192 Bytes each) and four
main blocks (1 block of 98,304 Bytes and 3 blocks
of 131,072 Bytes) are included on the 4-Mbit family.
An erase operation erases one of the main blocks in
typically 3.4 seconds and the boot or parameter
blocks in typically 2.0 seconds, independent of the
remaining blocks. Each block can be independently
erased and programmed 10,000 times.
Product Family
xB/x16 Products
xB-Only Products
28F400BL-T
28F004BL-T
28F400BL-B
28F004BL-B
1.1 Designing for Upgrade to
SmartVoltage Products
Today's high volume boot block products are upgradeable to Intel's SmartVoltage boot block products that provide program and erase operation at 5V
or 12V Vpp and read operation at 3V or 5V Vee.
Intel's SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this datasheet:
1. DU pin is replaced by WP # to provide a means to
lock and unlock ,the boot block with logic signals.
2. 5V Program/Erase operation uses proven program and erase techniques with 5V ± 10% applied to Vpp.
3. Enhanced circuits optimize performance at 3.3V
Vee·
Refer to the 2, 4 or 8Mbit SmartVoltage Boot Block
Flash Memory datasheets for complete specifications.
When you design with 12V Vpp boot block products
you should provide the capability in your board design to upgrade to SmartVoltage products.
Follow these guidelines to ensure compatibility:
1. Connect DU (WP # on SmartVoltage products) to
a control signal or to Vee or GND.
2. If adding a switch on Vpp for write protection,
switch to GND for complete write protection.
3. Allow for connecting 5V to Vpp and disconnect
12V from the Vpp line, if desired.
4-176
The Boot Block is located at either the top (-T) or
the bottom (-B) of the address map in order to accommodate different microprocessor protocols for
boot code location. The hardware lockable boot
block provides the most secure code storage. The
boot block is intended to store the kernel code required for booting-up a system. When the RP# pin is
between 11.4V and 12.6V the boot block is unlocked
and program and erase operations can be performed. When the RP# pin is at or below 4.1V the
boot block is locked and program and erase operations to the boot block are ignored.
The 28F400BL products are available in the
ROM/EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package and
the 56-Lead TSOP (Thin Small Outline, 1.2mm thick)
package as shown in Figures 3 and 4, The
28F004BL products are available in the 40-Lead
TSOP (1.2mm thick) package as shown in Figure 5.
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcontroller and the internal operation of the 28F400BL
and 28F004BL flash memory products.
Program and Erase Automation allow program
and erase operations to be executed using a twowrite command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, there.
by unburdening the microprocessor or microcontroller. Writing of memory data is performed in word or
byte increments for the 28F400BL family and in byte
increments for the 28F004BL family typically within
11 /Ls.
I
28F400BL-T IB, 28F004BL-T IB
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.
Maximum Access Time of 150 ns (TACC) is
achieved over the commercial temperature range
(O·C to + 70·C), Vee supply voltage range (3.0V to
3.6V, 4.5V to 5.5V) and 50 pF output load.
Ipp Program current Is 40 mA for x16 operation
and 30 mA for x8 operation. Ipp Erase current is
30 mA maximum. Vpp erase and programming
voltage is 11.4V to 12.6V (Vpp = 12V ±5%) under all operating conditions.
Typical Icc Active Current of 15 mA is achieved
for the x16 products and the xS products.
The 4-Mbit flash family is also designed with an Automatic Power Savings (APS) feature to minimize
system battery current drain and allow for very low
power designs. Once the device is accessed to read
the array data, APS mode will immediately put the
memory in static mode of operation where Ice active
current is typically O.S mA until the next read is initiated.
When the CE# and RP# pins are at Vee and the
BYTE# pin (2SF400BX-L-only) is at either Vee or
GND the CMOS Standby mode is enabled where
lee is typically 45 p.A.
A Deep Power-Down Mode is enabled when the
PWD pin is at ground minimizing power consumption
and providing write protection during power-up conditions. Icc current during deep power-down mode
is 0.20 p.A typical. An initial maximum access time
or Reset Time of 600 ns is required from RP #
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 1 p.s until
writes to the Command User Interface are recognized. When RP# is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature prevents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to RP# to reset the memory to normal read mode upon activation of the Reset pin.
When the CPU enters reset mode, it expects to read
the contents of a memory location. Furthermore,
with on-chip program/erase automation in the
4-Mbit family and the RP# functionality for data protection, when the CPU is reset and even if a program
or erase command is issued, the device will not recognize any operation until RP# returns to its normal
state.
I
For the 2SF400BL, Byte-wide or Word-wide Input/Output Control is possible by controlling the
BYTE # pin. When the BYTE # pin is at a logic low
the device is in the byte-wide mode (xS) and data is
read and written through DO[0:7]. During the bytewide mode, DO[S:14] are tri-stated and D015/A-1
becomes the lowest order address pin. When the
BYTE# pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DO[0:15].
1.3 Applications
The 4-Mbit low power boot block flash memory family combines high density, very low power, high performance, cost-effective flash memories with blocking and hardware protection capabilities. Its flexibility
and versatility will reduce costs throughout the product life cycle. Flash memory is ideal for Just-In-Time
production flow, reducing system inventory and
costs, and eliminating component handling during
the production phase. During the product life cycle,
when code updates or feature enhancements become necessary, flash memory will reduce the update costs by allowing either a user-performed code
change via floppy disk or a remote code change via
a serial link. The 4-Mbit flash family provides full
function, blocked flash memories suitable for a wide
range of applications. These applications include
Extended PC BIOS and ROM-able applications
storage, Handy Digital Cellular Phone program
and data storage and various other low power embedded applications where both program and data
storage are required.
Portable systems such as Notebook/Palmtop computers, are ideal applications for the 4-Mbit low power flash products. Portable and handheld personal
computer applications are becoming more complex
with the addition of power management software to
take advantage of the latest microprocessor technology, the availability of ROM-based application
software, pen tablet code for electronic hand writing,
and diagnostic code. Figure 1 shows an example of
a 28F400BL-T application.
This increase in software sophistication augments
the probability that a code update will be required
after the Notebook is shipped. The 4-Mbit flash
products provide an inexpensive update solution for
the notebook and handheld personal computers
while extending their product lifetime. Furthermore,
the 4-Mbit flash products' deep power-down mode
provides added flexibility for these battery-operated
portable designs which require operation at very low
power levels.
4-177
28F400BL-T IB, 28F004BL-T IB
The 4-Mbit low power flash products also provide
excellent design solutions for Handy Digital Cellular
Phone applications requiring low voltage supply,
high performance, high density storage capability
coupled with modular software designs, and a small
form factor package (xB-only bus). The 4-Mbit's
blocking scheme allows for an easy segmentation of
the embedded code with; 16-Kbytes of HardwareProtected Boot code, 4 Main Blocks of program
code and 2 Parameter Blocks of B-Kbytes each for
frequently updatable data storage and diagnostic
messages (e.g., phone numbers, authorization
codes). Figure 2 is an example of such an application with the 2BF004BL-T.
These are a few actual examples of the wide range
of applications for the 4-Mbit low power Boot Block
flash memory family which enable system designers
achieve the best possible product design. Only your
imagination limits the applicability of such a versatile
low power product family.
==D----irt'l
12V
GPIO
RESET#
I
I
I
10-
..
A[O: 17] t - - - - - - - - - - - , /
CS#
1-----------..
RD#
Inlel
Inlel386™ EX
28F400BL-T
Embedded
WR#
Processor
D[0:15]
290450-7
Figure 1. 28F400BL Interface to Intel386™ .EX Embedded Processor
I\.
~6:18
ADDRESS
LATCHES
~LE
A8-~5
ALE
A
ADo -AD7
80L188EB
T I\.
~ru
ADDRESS
LATCHES
LE
51
~
III
DQo-D~
UCS#
12V
CL
P1.X
Vpp
GENERATOR
WR#
RD#
RESIN#
I
{7
Ao-A t8
CE# 28FOO4BL-T
Vpp
RP#
+-
WE#
OE#
L
SYSTEM RESET
290450-23
Figure 2. 28F004BL Interface to INTEL 80L 188EB Low Voltage 8-bit Embedded Processor
4-17B
I
28F400BL-T IB, 28F004BL-T IB
1.4 Pinouts
pinout shown in Figure 4 provides density upgrades
to future higher density boot block memories.
The '28F400BL 44-Lead PSOP pinout follows the
industry standard ROM/EPROM pinout as shown
in Figure 3 and provides an upgrade for the
28F200BL Low Power Boot Block flash memory
family. Furthermore, the 28F400BL 56-Lead TSOP
The 28F004BL 40-Lead TSOP pinout shown in Figure 5 is 100% compatible and provides a density
upgrade for the 28F002BL 2-Mbit Low Power Boot
Block flash memory family.
27C4OO
27C4OO
NC
vpp
RP#
NC
DU
WE#
NC
A17
~7
As
As
A7
A7
Ag
Ag
As
As
A-.
As
As
~o
Ala
~1
All
A4
~2
A12
A3
A3
~3
A13
A2
A2
A14
A14
Al
A,
~s
AIS
Ao
Au
CEO'
eE#
GND
GND
28F400BL
44 LEAD PSOP
0.525" .1.110·
TOP VIEW
~6
8YTE#
GND
31
NC
AIS
BYTEO'/Vpp
GND
OEO'
OE#
000
000
D~
007
DOa
DOs
00,4
0014
Do,s/A-l
D01S/A-l
001
DO,
DOs
DOs
DOg
DOg
0013
0013
002
002
DOs
DOs
0010
00,0
00,2
0012
003
003
004
004
0011
00,1
Vee
Vcc'
290450-24
Figure 3. PSOP Lead Configuration for xS/x16 2SF4OOBL
I
4-179
intel®
28F400BL·T IB, 28F004BL·T IB
NC
NC
A15
A14
A13
A12
All
A10
Ag
AS
NC
NC
WE#
RP#
NC
NC
0
28F400BL
56-LEAD TSOP
14mm x 20mm
TOP VIEW
Vpp
DU
NC
A17
A7
AS
A5
A4
A3
A2
Al
NC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
A1S
BYTE#
GND
D015/ A-l
D~
D014
DOS
D013
D05
D012
D04
Vee
Vee
DOll
D03
DOlO
D02
DOg
DOl
DOs
DOO
OE#
GND
CE#
AO
NC
NC
290450-S
Figure 4. TSOP Lead Configuration for x8 28F400BL
~o
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28F004BL
40-LEAD TSOP
10mm X 20mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
NC
NC
A10
D07
DOs
D05
D04
Vee
Vee
NC
D03
D02
DOl
DOo
OE#
GND
CE#
Ao
290450-5
Figure 5. TSOP Lead Configura,tion for x8 28F004BL
4·180
I
28F400BL·T IB, 28F004BL·T IB
1.5 Pin Descriptions for x8/x16 28F400BL
Symbol
Type
Ao- A 17
I
Ag
I
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle.
ADDRESS INPUT: When Ag is at 12V the signature mode is accessed. During this
mode Ao decodes between the manufacturer and device ID's. When BYTE # is at
a logic low only the lower byte of the signatures are read. DQ1S/ A-l is.a don't
care in the signature mode when BYTE # is low.
DQo-DQ7
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a program command. Inputs commands to the command user interface
when CE# and WE# are active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and status register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.
DQa- DQls
I/O
DATA INPUT/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a program command. Data is internally latched during the write and program
cycles. The data pins float to tri-state when the chip is deselected or the outputs
are disabled as in the byte-wide mode (BYTE# = "0"). In the byte-wide mode
DQ1S/ A-l becomes the lowest order address for data output on DQo-DQ7.
CE#
I
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE # is active low; CE # high deselects the memory device and
reduces power consumption to standby levels. If CE # and RP # are high, but not
at a CMOS high level, the standby current will increase due to current flow through
the CE# and RP# input stages.
RP#
I
RESETIDEEP POWER·DOWN: Provides Three-State control. Puts the device in
deep power-down mode. Locks the boot block from program/erase.
When RP # is at logic high level and equals 4.1V maximum the boot blocl< is
locked and cannot be programmed or erased.
When RP#
or erased.
=
11.4V minimum the boot block is unlocked and can be programmed
When RP# is at a logic low level the boot block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RP# transitions from logic low to logic high, the flash memory
enters the read-array mode.
OE#
I
OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. OE# is active low.
WE#
I
WRITE ENABLE: Controls writes to the Command Register and array blocks.
WE # is active low. Addresses and data are latched on the rising edge of the WE #
pulse.
I
4-181
28F400BL-T IB, 28F004BL-T IB
1.5 Pin Descriptions for x8/x16 28F400BL (Continued)
Symbol
Type
Name and Function
BYTE#
I
BYTE# ENABLE: Controls whether the device operates in the byte-wide mode (x8) or
the word-wide mode (x16). BYTE # = "0" enables the byte-wide mode, where data is
read and programmed on OOO-OO? and 0015/A-1 becomes the lowest order
address that decodes between the upper and lower byte. 008-0014 are tri-stated
during the byte-wide mode. BYTE # = "1" enables the word-wide mode where data is
read and programmed on 000-0015.
Vpp
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
Note: Vpp < VPPLMAX memory contents cannot be altered.
Vee
DEVICE POWER SUPPLY (3.3V ±0.3, 5V ± 10%)
GNO
GROUND: Fo~ all internal circuitry.
NC
NO CONNECT: Pin may be driven or left floating.
OU
DON'T USE PIN: Pin should not be connected to anything.
4-182
I
28F400BL·T IB, 28F004BL·T IB
1.6 Pin Descriptions for x8 28F004BL
Symbol
Type
Name and Function
Ao-A1B
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.
As
I
ADDRESS INPUT: When As is at 12V the signature mode is accessed. During this
mode Ao decodes between the manufacturer and device ID's.
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a program command. Inputs commands to the command user interface
when CE # and WE # are active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and status register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.
CE#
I
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE # is active low; CE # high deselects the memory device and
reduces power consumption to standby levels.
RP#
I
RESET/DEEP POWER·DOWN: Provides Three-State control. Puts the device in
deep power-down mode. Locks the Boot Block from program/erase.
DQo-DQ7
When RP # is at logic high level and equals 4.1 V maximum the Boot Block is locked
and cannot be programmed or erased.
When RP #
or erased.
= 11.4V minimum the Boot Block is unlocked and can be programmed
When RP# is at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RP# transitions from logic low to logic high, the flash memory
enters the read-array mode.
OE#
I
OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. OE# is active low.
WE#
I
WRITE ENABLE: Controls writes to the Command Register and array blocks. WE #
is active low. Addresses and data are latched on the rising edge of the WE # pulse.
Vpp
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
Note: Vpp < VPPLMAX memory contents cannot be altered.
Vee
DEVICE POWER SUPPLY (3.3V ±0.3V, 5V ± 10%)
GND
GROUND: For all internal circuitry.
NC
NO CONNECT: Pin may be driven or left floating.
DU
DON'T USE PIN: Pin should not be connected to anything.
I
4-183
I~
!
CD
"""
N
CD
."
~
0
0
I\)
Q)
m
"
18
DQO-Do.,
0
m
r-
I"'"
I
-I
....
.!l'
N
CD
."
0
0
."
::D
0
"'II
~
C
m
I"'"
0
....-Im
c:
US"
c
...CD
I
-t
en
~
N
CD
BYTE#
C
m
"'II
en
"""
0
0
m
r
COMMAND
USER
INTERFACE
...==a.0
.....
m
CE#
0
::D
WEN
."
OE#
-t
(5
RP#
Z
'S.
'P
==
c:
CD
m
0"
()
Ao -
AI7
Y-DECODER
Y-GATING/SENSING
:0;-
~~
C
iii"
IQ
iil
3
)-0
X-DECODER
'"u0
~
~'"
'"0
I I
~
~'"
~g
w'"
... u
)-0
'" ~
"'~
"''''
"'rW... "''"rW...w ",'"
rz
~~
",0
N «
_0
"":::.
« "":::.
« '"
'" '"«"- «'""- "'~ -:::.
~~
r ...
)-",
"'w
"·~:~~U~~';.Il-
1+-+1 ~~~~~~~/~~~;~~ I+- Vpp
u
)-'"
w'"
...
u
w'"
... u
)-0
>-0
N «
N«
'" ~
"''''
"''''
~~
ch~
-:::.
"'~
-:::.
290450-1
-::s
c[
@
28F400BL-T IB, 28F004BL-T IB
2.1 28F400BL Memory Organization
2.1.1 BLOCKING
The 28F400BL uses a blocked array architecture to .
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F400BL is
a random read/write memory, only erasure is performed by block.
2.1.1-1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RP# is not at 12V. The boot block can
be erased and written when RP# is held at 12V for
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address locations of the boot block for the 28F400BL-T and
28F400BL-B.
2.1.2 BLOCK MEMORY MAP
Two versions of the 28F400BL product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F400BL-T
memory map is inverted from the 28F400BL-B memory map.
2.1.2.1 28F400BL-B Memory Map
The 28F400BL-B device has the 16-Kbyte boot
block located from OOOOOH to 01 FFFH to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH. In the
28F400BL-B the first 8-Kbyte parameter block resides in memory space from 02000H to 02FFFH.
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96-Kbyte main block resides in memory space from
04000H to OFFFFH. The three 128-Kbyte main
block resides in memory space from 10000H to
1FFFFH, 20000H to 2FFFFH and 30000H to
3FFFFH (word locations). See Figure 7.
(Word Addresses)
3FFFFH
128-Kbyte MAIN BLOCK
30000H
2FFFFH
2.1.1.2 Parameter Block Operation
128-Kbyte MAIN BLOCK
The 28F400BL has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. The parameter blocks provide for more efficient memory utilization when dealing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for address locations of the parameter blocks for the
28F400BL-T and 28F400BL-B.
10000H
OFFFFH
2.1.1.3 Main Block Operation
02000H
01FFFH
20000H
1FFFFH
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
04000H
03FFFH
03000H
02FFFH
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
Four main blocks of memory exist on the 28F400BL
(3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks). See
the following section on Block Memory Map for the
address location of these blocks for the 28F400BL-T
and 28F400BL-B products.
I
16·Kbyte BOOT BLOCK
OOOOOH
Figure 7. 28F400BL-B Memory Map
4-185
28F400BL·T IB, 28F004BL·T IB
2.1.2.2 28F400BL·T Memory Map
The 28F400BL-T device has the 16-Kbyte boot
block located from 3EOOOH to 3FFFFH to accommodate those microprocessors that boot from the top
of the address map. In the 28F400BX-T the first
8-Kbyte parameter block· resides in memory space
from 3DOOOH to 3DFFFH. The second 8-Kbyte pa-.
rameter block resides in memory space from
3COOOH to 3CFFFH. The 96-Kbyte main block resides in memory space from 30000H to 3BFFFH.
The three 128-Kbyte main blocks reside in memory
space from 20000H to 2FFFFH, 10000H to 1FFFFH
and OOOOOH to OFFFFH as shown in Figure 8.
(Word Addresses)
3FFFFH
16-Kbyte BOOT BLOCK
3EOOOH
3DFFFH
3DOOOH
3CFFFH
3COOOH
3BFFFH
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
30000H
2FFFFH
128-Kbyte MAIN BLOCK
20000H
1FFFFH
128-Kbyte MAIN BLOCK
10000H
OFFFFH
128-Kbyte MAIN BLOCK
OOOOOH
Figure 8. 28F400BL·T Memory Map
4-186
I
Co)
(:)
N
CD
"T1
0
0
DQO-D~
,j:Io
m
r-
--
::l
«
®
"tJ
~
0
C
C
!!
ce
...
0
c
-I
C1I
en
!D
C
N
CD
m
~
en
o
....
CE#
r-
WE#
"tJ
OE#
0Z
ID
III
:::J
a.
-
~
POWER
REDUCTION
CONTROL
C1I
RP#
1----1
0
~
-I
a:
==
C1I
ID
0'
()
;0\"
c
iii'
ce
Dl
3
An -
Y-GATING!SENSING
A,B
Vpp
'"3u
'"
u
3
wu
'"
~m
~m
.... 0
1£5
~5
~m
"',w....
"'~
'"
;t
>-~
'",w
.... '20
",::> "'4'
;;; m::>
w'"
.... u
w><
1£3
",m
.... u
~g
",m
~2!:
~?::
N'"
-::>
N
'"
-::>
w'"
N
.... u
OIl
~g
'T1
",m
""oo
'20
'"<-<'"
-
-::>
m
;t
~
......
~m
N
OIl
290450-3
'T1
o
o
""
!CX>
-..J
m
r
!t
......
m
28F400BL-T IB, 28F004BL-T 18
3.1 28F004BL Memory Organization
3.1.1 BLOCKING
The 28F004BL uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F004BL is
a random· read/write memory, only erasure is performed by block.
3.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being programmed
or erased when RP# is not at 12V. The boot block
can be erased and programmed when RP# is held
at 12V for the duration of the erase or program operation. This allows customers to change the boot
code when necessary while still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
28F004BL-T and 28F004BL-B.
3.1.2 BLOCK MEMORY MAP
Two versions of the 28F004BL product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F004BL-T
memory map is inverted from the 28F004BL-B memory map.
3.1.2.1 28F004BL-B Memory Map
The 28F004BL-B device has the 16-Kbyte boot
block located from OOOOOH to 03FFFH to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH. In the
28F004BL-B the first 8-Kbyte parameter block resides in memory from 04000H to OSFFFH. The second 8-Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96-Kbyte main
block resides in memory space from 08000H to
1FFFFH. The three 128-Kbyte main blocks reside in
memory space from 20000H to 3FFFFH, 40000H to
SFFFFH and 60000H to 7FFFH. See Figure 10.
7FFFFH
12S-Kbyte MAIN BLOCK
60000H
5FFFFH
12S-Kbyte MAIN BLOCK
3.1.1.2 Parameter Block Operation
The 28F004BL has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map section for address locations of the parameter blocks
for the 28F004BL-T and 28F004BL-B.
40000H
3FFFFH
12S-Kbyte MAIN BLOCK
20000H
1FFFFH
96-Kbyte MAIN BLOCK
OSOOOH
07FFFH
06000H
05FFFH
04000H
03FFFH
S-Kbyte PARAMETER BLOCK
S-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
3.1.1.3 Main Block Operation
OOOOOH
Two main blocks of memory exist on the 28F004BL
(3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks). See
the following section on Block Memory Map for the
address location of these blocks for the 28F004BL-T
and 28F004BL-B.
4-188
Figure 10. 28F004BL-B Memory Map
I
28F400BL·T IB, 28F004BL· T IB
3.1.2.2 28F004BL·T Memory Map
The 28F004BL-T device has the 16-Kbyte boot
block located from 7COOOH to 7FFFFH to accommodate those microprocessors that boot from the
top of the address map. In the 28F004BL-T the first
8-Kbyte parameter block resides in memory space
from 7AOOOH to 7BFFFH. The second 8-Kbyte parameter block resides in memory space from
78000H to 79FFFH. The 96-Kbyte main block resides in memory space from 60000H to 77FFFH.
The three 128-Kbyte main blocks reside in memory
space from 40000H to 5FFFFH, 20000H to 3FFFFH
and OOOOOH to 1FFFFH.
7FFFFH
16-Kbyte BOOT BLOCK
7COOOH
7BFFFH
7AOOOH
79FFFH
78000H
8·Kbyte PARAMETER BLOCK
8·Kbyte PARAMETER BLOCK
77FFFH
96-Kbyte MAIN BLOCK
60000H
5FFFFH
128·Kbyte MAIN BLOCK
4.0
PRODUCT FAMILY PRINCIPLES
OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical write anderas8. The 4-Mbit flash
memory family utilizes a Command User Interface
(CUI) and internally generated and timed algorithms
to simplify write and erase operations.
The CUI allows for fixed power supplies during erasure and programming, and maximum EPROM compatibility.
In the absence of high voltage on the Vpp pin, the
4-Mbit flash family will only successfully execute the
following commands: Read Array, Read Status Register, Clear Status Register and Intelligent Identifier
mode. The device provides standard EPROM read,
standby and output disable operations. Manufacturer Identification and Device Identification data can
be accessed through the CUI or through the standard EPROM A9 high voltage access (VID) (for
PROM programmer equipment).
The same EPROM read, standby and output disable
functions are available when high voltage is applied
to the Vpp pin. In addition, high voltage on Vpp allows write and erase of the device. All functions associated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.
40000H
3FFFFH
128·Kbyte MAIN BLOCK
20000H
lFFFFH
128·Kbyte MAIN BLOCK
OOOOOH
The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device. The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
WE # interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.
4.1
28F400BL Bus Operations
Figure 11. 28F004BL·T Memory Map
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
I
4-189
28F400BL-T IB, 28F004BL-T IB
Table 1. Bus Operations for WORD-WIDE Mode (BYTE# = VIH)
Mode
Read
Notes
RP#
CE#
OE#
WE#
Ag
Ao
Vpp
1,2,3
VIH
VIL
VIL
VIH
X
X
X
DOLJT
X
X
HighZ
DQO-15
Output Disable
VIH
VIL
VIH
VIH
X
Standby
VIH
VIH
X
X
X
X
X
HighZ
9
VIL
X
X
X
X
X
X
HighZ
Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write
4
VIH
VIL
VIL
VIH
VID
VIL
X
0089H
4,5,10
VIH
VIL
VIL
VIH
VID
VIH
X
4470H
4471H
6,7,8
VIH
VIL
VIH
VIL
X
X
X
DIN
Table 2. Bus Operations for BYTE-WIDE Mode (BYTE # = Vld
Mode
Read
Notes
1,2,3
Output Disable
RP#
CE#
OE#
WE#
Ag
X
Ao
A-1
Vpp
DQO-7
DQS-14
X
X
X
DOUT
HighZ
VIH
VIL
VIL
VIH
VIH
VIL
VIH
VIH
X
X
X
X
HighZ
HighZ
X
X
X
X
X
HighZ
HighZ
X
X
X
X
X
HighZ
HighZ
X
89H
HighZ
Standby
VIH
VIH
X
Deep Power-Down
VIL
X
X
Intelligent Identifier
(Mfr)
4
VIH
VIL
VIL
VIH
VID
VIL
X
Intelligent Identifier
(Device)
4,5,10
VIH
VIL
VIL
VIH
VID
VIH
X
X
70H
71H
HighZ
6,7,8
VIH
VIL
VIH
VIL
X
X
X
X
DIN
HighZ
Write
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VpPL or VPPH for Vpp.
3. See DC Characteristics for VPPL. VPPH. VHH. VID voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A1-A17 = VIL.
5. Device 10 = 4470H for 28F400BL-T and 4471H for 28F400BL-B.
6. Refer to Table 4 for valid DIN during a write operation.
7. Command writes for Block Erase or Word/Byte Write are only executed when Vpp = VPPH.
8. To write or erase the boot block, hold RP# at VHH.
9. RP# must be at GND ±0.2V to meet the 1.2 /LA maximum deep power·down current.
10. The device 10 codes are identical to those of the 28F400BX.5V version and SmartVoltage equivalent.
4-190
I
28F400BL-T IB, 28F004BL-T IB
4.2 28F004BL Bus Operations
Table 3. Bus Operations
Mode
Notes
RP#
CE#
OE#
WE#
Ag
Ao
Vpp
Read
1,2,3
VIH
VIL
VIL
VIH
X
X
X
DOUT
Output Disable
VIH
VIL
VIH
VIH
X
X
X
HighZ
Standby
VIH
VIH
X
X
X
X
X
HighZ
DQO-7
Deep Power-Down
9
VIL
X
X
X
X
X
X
HighZ
Intelligent Identifier (Mfr)
4
VIH
VIL
VIL
VIH
VID
VIL
X
89H
Intelligent Identifier (Device)
4,5,10
VIH
VIL
VIL
VIH
VID
VIH
X
78H
79H
Write
6,7,8
VIH
VIL
VIH
VIL
X
X
X
DIN
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VPPL or VPPH for Vpp.
3. See DC Characteristics for VPPL, VPPH, VHH, VIO voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A1-AS, A1Q-A1S = VIL.
5. Device ID ~ 78H for 28F004BL-T and 79H for 28F004BL-B.
6. Refer to Table 4 for valid DIN during a write operation.
7. Command writes for Block erase or byte program are only executed when Vpp = VPPH.
8. Program or erase the Boot block by holding RP # at VHH.
9. RP# must be at GND ±O.2V to meet the 1.2 p.A maximum deep power-down current.
10. The device ID codes are identical to those of the 2BF004BX 5V version and SmartVoltage equivalent.
4.3 Read Operations
4.3.1.2 Input Control
The 4-Mbit flash family has three user read modes;
Array, Intelligent Identifier, and Status Register.
Status Register read mode will be discussed in detail
in the "Write Operations" section.
With WE# at logic-high level (VIH), input to the device is disabled. Data Input/Output pins (DO[0:15]
or DO[O:71) are controlled by OE #.
During power-up conditions (VCC supply ramping), it
takes a maximum of 600 ns from VCC at 3.0V minimum to obtain valid data on the outputs.
4.3.1 READ ARRAY
If the memory is not in the Read Array mode, it is
necessary to write the appropriate read mode command to the CUI. The 4-Mbit flash family has three
control functions, all of which must be logically active, to obtain data at the outputs. Chip-Enable CE #
is the device selection control. Power-Down RP# is
the device power control. Output-Enable OE# is the
DATA INPUT/OUTPUT (DO[0:15] or DO[0:71) direction control and when active is used to drive data
from the selected memory onto the I/O bus.
4.3.2 INTELLIGENT IDENTIFIERS
28F400BL PRODUCTS
The manufacturer and device codes are read via the
CUI or by taking the A9 pin to 12V. Writing 90H to
the CUI places the device into Intelligent Identifier
read mode. A read of location OOOOOH outputs the
manufacturer's identification code, 0089H, and location 00001 H outputs the device code; 4470H for
28F400BL-T, 4471 H for 28F4001 BL-B. When
BYTE # is at a logic low only the lower byte of the
above signatures is read and D01S/A-l is a "don't
care" during Intelligent Identifier mode. A read array
command must be written to the CUI to return to the
read array mode.
4.3.1.1 Output Control
With OE# at logic-high level (VIH), the output from
the device is disabled and data input/output pins
(DO[0:15] or DO[0:7] are tri-stated. Data input is
then controlled by WE # .
I
4-191
28F400BL-T IB, 28F004BL-T IB
28F004BL PRODUCTS
4.4.1 BOOT BLOCK WRITE OPERATIONS
The manufacturer and device codes are also read
via the CUI or by taking the A9 pin to 12V. Writing
90H to the CUI places the device into Intelligent
Identifier read mode. A read of location OOOOOH outputs the manufacturer's identification code, 89H,
and location 00001 H outputs the device code; 78H
for 28F004BL-T, 79H for 28F004BL-B.
In the case of Boot Block modifications (write and
erase), RP# is set to VHH = 12V typically, in addition to Vpp at high voltage.
4.4 Write Operations
Commands are written to the CUI using standard microprocessor write timings. The CUI serves as the
interface between the microprocessor and the internal chip operation. The CUI can decipher Read Array, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program commands. In the event of a read command, the CUI
simply points the read path at either the array, the
Intelligent Identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state machine that a write or erase has been requested. During a program cycle, the Writt;; State Machine will
controUhe program sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Machine has completed its
task, it will allow the CUI to respond to its full command set. The CUI will stay in the current command
state until the microprocessor issues another command.
The CUI will successfully initiate an erase or write
operation only when Vpp is within its voltage range.
Depending upon the application, the system designer may choose to make the Vpp power supply
switchable, available only when memory updates
are desired. The system designer can also choose
to "hard-wire" Vpp to 12V. The 4-Mbit flash memory
family is designed to accommodate either deSign
practice. It is recommended that RP # be tied to logical Reset for data protection during unstable CPU
reset function as described in the "Product Family
Overview" section.
4-192
However, if RP# is not at VHH when a program or
erase operation of the boot block is attempted, the
corresponding status register bit (Bit 4 for Program
and Bit 5 for Erase, refer to Table 5 for Status Register Definitions) is set to indicate the failure to complete the operation.
4.4.2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a "1", which will also allow the CUI to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.
4.4.2.1 Command Set
Command
Codes
Device Mode
00
10
20
40
50
70
90
BO
DO
FF
Invalid/Reserved
Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
Erase Resume/Erase Confirm
Read Array
4.4.2.2 Command Function Descriptions
Device operations are selected by writing specific
commands into the CUI. Table 4 below defines the
4-Mbit flash memory family commands.
I
28F400BL-T IB, 28F004BL-T IB
Table 4. Command Definitions
Command
Bus
Notes
First Bus Cycle
Second Bus Cycle
Cycles
Req'd
8
Operation Address Data Operation Address Data
Read Array
1
1
Write
X
FFH
Intelligent Identifier
3
2,4
Write
X
90H
Read
IA
110
Read Status Register
2
3
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Erase Setup/Erase Confirm
2
5
Write
BA
20H
Write
BA
DOH
Word/Byte Write
Setup/Write
2
6,7
Write
WA
40H
Write
WA
WD
Erase Suspend/Erase Resume
2
Write
X
BOH
Write
X
DOH
Alternate Word/Byte Write
Setup/Write
2
2,3,7
Write
WA
10H
Write
WA
WD
NOTES:
1. Bus operations are defined in Tables 1, 2, 3.
2. IA = Identifier Address: OOH for manufacturer code, 01 H for device code.
3. SRD = Data read from Status Register.
4. liD = Intelligent Identifier Data.
Following the Intelligent Identifier command, two read operations access manufacturer and device codes.
5. BA = Address within the block being erased.
6. WA = Address to be written.
WD = Data to be written at location WA.
7. Either 40H or 10H commands is valid.
B. When writing commands to the device the upper data bus [D08-D015] = X (2BF400BL-only) which is either Vee or Vss
to avoid burning additional current.
Invalid/Reserved
Read Status Register (70H)
These are unassigned commands. It is not recommended that the customer use any command other
than the valid commands specified above. Intel reserves the right to redefine these codes for future
functions.
This is one of the two commands that is executable
while the state machine is operating. After this command is written, a read of the device will output the
contents of the status register, regardless of the address presented to the device.
Read Array (FFH)
The device automatically enters this mode after program or erase has completed.
This single write command points the read path at
the array. If the host CPU performs a CE#lOE#
controlled read immediately following a two-write sequence that started the WSM, then the device will
output status register contents. If the Read Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to Read Array
after Program Setup.
Intelligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address AO is used in this mode, all
other address inputs are ignored).
I
Clear Status Register (SOH)
The WSM can only set the Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchronization. The WSM does not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after programming the string. Thus, if any errors exist while
programming the string, the status register will return the accumulated error status.
4-193
28F400BL-T IB, 28F004BL-.TIB
Program Setup (40H or 10H)
This command simply sets the CUI into a state such
that the next write will load the address and data
registers. Either 40H or 10H can be used for Program Setup. Both commands are included to accommodate efforts to achieve an industry standard
command code set.
Program
The second write after the program setup command,
will latch addresses and data. Also, the CUI initiates
the WSM to begin execution of the program algorithm. While the WSM finishes the algorithm, the device will output Status Register contents. Note that
the WSM cannot be. suspended during programming.
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command.
No other action is taken. If the. next command is not
an Erase Confirm command then the CUI will set
both the Program Status and Erase Status bits of the
Status Register to a "1", place the device into the
Read Status Register state, arid wait for another
command.
Erase Confirm (DOH)
If the previous command was an Erase Setup command,then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status Register and
Erase Suspend commands. While the WSM is executing, the device will output Status Register data
when OE# is toggled low. Status Register data can
only be updated by toggling either OE # or CE # low.
Erase Suspend (BOH)
This command only has meaning while the WSM is
executing an Erase operation, and therefore will only
be responded to during an erase operation. After
this command has been executed, the CUI will initiate the WSM to suspend Erase operations, and then
return to responding to only Read Status Register or
to the Erase Resume commands. Once the WSM
has reached the Suspend state, it will set an output
into the CUI which allows the CUI to respond to the
Read Array, Read Status Register, and Erase Resume commands. In this mode, the CUI will not respond to any other commands. The WSM will also
set the WSM Status bit to a "1". The WSM will con-
4-194
tinue to run, idling in the SUSPEND state, regardless
of the state of all input control pins, with the exclu,sion of RP#. RP# low will immediately shut down
the WSM and the remainder of the Chip.
.Er~se
Resume (DOH)
This command will cause the CUI to clear the Suspend state and set the WSM Status bit to a "0", but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.
4.4.3 STATUS REGISTER
The 4 Mbit flash family contains a status register
which may be read to determine when a program or
erase operation is complete, and whether that operation completed successfully. The status register
may be read at any time by writing the Read Status
command to the CUI. After writing this command, all
subsequent Read operations output data from the
status register until another. command is written to
the CUI. A Read Array command must be written to
the CUI to return to the Read Array mode.
The status register bits are output on 00[0:7]
whether the device is in the byte-wide (xS) or wordwide (x16) mode for the 2SF400BL. In the word-wide
mode the upper byte, 00[S:15] is set to OOH during
a Read Status command. In the byte-wide mode,
00[S:14] is tri-stated and 0015/A-1 retains the
low order address function.
It should be noted that the contents of the status
register are latched on the falling edge of OE# or
CE # whichever occurs last in the read cycle. This
prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register. CE # or OE # must be toggled
with each subsequent status read, or the completion
of a program or erase operation will not be evident.
The Status Register is the interface between the microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate
the status of the WSM, and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation. The WSM sets
status bits "Three" through "Seven" and clears bits
"Six" and "Seven", but cannot clear status bits
"Three" through "Five", These bits can only be
cleared by the controlling CPU through the use of
.
the Clear Status -Register command.
I
28F400BL-T /B, 28F004BL-T /B
4.4.3.1 Status Register Bit Definition
Table 5. Status Register Definitions
I
WSMS lESS
7'
6
ES
PS
vpPs
5
4
3
I
R
2
R
R
o
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
o = Erase in Progress/Completed
SR.5 = ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Erase
SR.4 = PROGRAM STATUS
1 = Error in Byte/Word Program
o = Successful Byte/Word Program
SR.3 = Vpp STATUS
1 = Vpp Low Detect; Operation Abort
0= Vpp OK
Write State Machine Status bit must first be checked to
determine byte/word program or block erase completion,
before the Program or Erase Status bits are checked for
success.
When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to "1". ESS bit remains set to "1" until an Erase Resume command is issued.
When this bit is set to "1". WSM has applied the maximum number of erase pulses to the block and is still unable to successfully perform an erase verify.
When this bit is set to "1", WSM has attempted but failed
to Program a byte or word.
The Vpp Status bit unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM interrogates the Vpp level only after the byte write or block
erase command sequences have been entered and informs the system if Vpp has not been switched on. The
Vpp Status bit is not guaranteed to report accurate feedback between VPPL and VPPH.
SR.2-SR.O = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be masked out when polling the Status Register.
4.4.3.2 Clearing the Status Register
4.4.4 PROGRAM MODE
Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure conditions. By allowing the system software to control
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in sequence). The status register may then be read to
determine if an error occurred during that programming or erasure series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other
command may be issued to the CUI. Note again that
before a read cycle can be initiated, a Read command must be written to the CUI to specify whether
the read data is to come from the array, status register, or Intelligent Identifier.
Program is executed by a two-write sequence. The
Program Setup command is written to the CUI followed by a second write which specifies the address
and data to be programmed. The write state machine will execute a sequence of internally timed
events to:
1. program the desired bits of the addressed memory word (byte), and
2. verify that the desired bits are sufficiently programmed.
I
Programming of the memory results in specific bits
within a byte or word being changed to a "0".
If the user attempts to program "1"s, there will be no
change of the memory cell content and no error occurs.
4-195
28F400BL-T /B, 28F004BL-T/B
Similar to erasure, the status register indicates
whether programming is complete. While the program sequence is executing, bit 7 of the status register is a "0". The status register can be polled by
toggling either CE # or OE # to determine when the
program sequence is complete. Only the Read
Status Register command is valid while programming is active.
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, Bit 4 of the status register is set to a "1" to indicate a Program Failure. If
Bit 3 is set then Vpp was not within acceptable limits,
and the WSM will not execute the programming sequence.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 12 shows a system software flowchart for device byte programming operation. Figure 13 shows a
similar flowchart for device word programming operation (28F400BL-only).
4.4.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI, along with the addresses; A[12:17] for the
28F400BL or A[12:18] for the 28F004BL, identifying
the block to be erased. These addresses are latched
internally when the Erase Confirm command is issued. Block erasure results in all bits within the block
being set to "1 ".
The WSM will execute a sequence of internally
timed events to:
1. program all bits within the block
2. verify that all bits within the block are sufficiently
programmed
3. erase all bits within the block and
4. verify that all bits within the block are sufficiently
.
erased
While the erase sequence is executing, Bit 7 of the
status register is a "0".
4-196
When the status register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.
If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a "1" to indicate an
Erase Failure. If Vpp was not within acceptable limits
after the Erase Confirm command is issued, the
WSM will not execute an erase sequence; instead,
Bit 5 of the status register is set to a "1" to indicate
an Erase Failure, and Bit 3 is set to a "1" to identify
that Vpp supply voltage was not within acceptable
limits.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory conterits can be read. .
Figure 13 shows a system software flowchart for
Block Erase operation.
4.4.5.1 Suspending and Resuming Erase
Since an erase operation typically requires 2 seconds to 5 seconds to complete, an Erase Suspend
command is provided. This allows erase-sequence
interruption in order to read data from another block
of the memory. Once the erase sequence is started,
writing the Erase Suspend command to the CUI requests that the Write State Machine (WSM) pause
the erase sequence at a predetermined point in the
erase algorithm. The ~tatus register must be read to
determine when the erase operation has been suspended.
At this point,a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
Figure 14 shows a system software flowchart detailing the operation.
During Erase Suspend mode, the chip can go into a
pseudo-standby mode by taking CE# to VIH and the
active current is now a maximum of 6 mA. If the chip
is enabled while in this mode by taking CE# to VIL,
the Erase Resume command can be issued to resume the erase operation.
I
28F400BL-T IB, 28F004BL-T IB
Upon completion of reads from any block other than
the block being erased, the Erase Resume command must· be issued. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of erase, the status register must be
read, cleared, and the next instruction issued in order to continue.
I
4.4.6 EXTENDED CYCLING
Intel ,has designed extended cycling capability into
its ETOX III flash memory technology. The 4-Mbit
low voltage flash memory family is designed for
10,000 program/erase cycles on each of the seven
blocks. The combination of low electric fields, clean
oxide processing and minimized oxide area per
memory cell subjected to the tunneling electric field,
results in very high cycling capability.
4-197
28F400BL-T IB, 28F004BL-T IB
Bus
Operation
Command
Comments
Write
Setup
Program
Data = 40H
Address = Byte to be
programmed
Write
Program
Data to be programmed
Address = Byte to be
programmed
Read
Status Register Data.
ToggleOE# orCE# to update
Status Register
Standby
CheckSR.7
1 = Ready, 0 = Busy
Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
290450-9
Full Status Check Procedure
Bus
Operation
Command
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
Check SR.4
1 = Byte Program Error
Vpp Range
Error
Byte Program
Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290450-10
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 12. Automated Byte Programming Flowchart
4-198
I
28F400BL-T IB, 28F004BL-T IB
Bus
Operation
Command
Comments
Write
Setup
Program
Data = 40H
Address = Word to be
programmed
Write
Program
Data to be programmed
Address = Word to be
programmed
Read
Status Register Data.
Toggle OE# or CE# to update
Status Register
Standby
CheckSR.7
1 = Ready, 0
=
Busy
!
Repeat for subsequent words.
Full status check can be done after each word or after a
sequence of words.
290450-11
Write FFH after the last word programming operation to
reset the device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Error
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
CheckSR.4
1 = Byte Program Error
Vpp Ronge
Error
Word Program
Command
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290450-12
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 13. Automated Word Programming Flowchart
I
4-199
28F400BL-T IB, 28F004BL-T IB
Bus
Operation
Command
Comments
Write
Setup
Erase
Data = 20H
Address = Within block to be
erased
Write
Erase
Data = DOH
Address = Within block to be
erased
Read
Status Register Data.
Toggle OE# or CE# to update
Status Register
Standby
CheckSR.7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.
290450-13
Write FFH after the last block erase operation to reset the
device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Vpp Range
Error
Command Sequence
Error
Command
Comments
Standby
Check SR.3
1 = V pp Low Detect
Standby
Check SR.4.5
Both 1 = Command Sequence
Error
Standby
CheckSR.5
1 = Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
290450-14
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
.
If err!Jr is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 14. Automated Block Erase Flowchart
4-200
I
intel®
28F400BL-T IB, 28F004BL-T IB
Bus
Operation
Write
Command
Erase
Suspend
Comments
Data
= BOH
Read
Status Register Data.
ToggleOE# orCE# to
update Status Register
Standby
CheckSR.7
1 = Ready
Standby
CheckSR.6
1 = Suspended
Write
Read Array
= FFH
Read array data from block
other than that being
erased.
Read
Write
Data
Erase Resume
Data
=
DOH
290450-15
Figure 15. Erase Suspend/Resume Flowchart
4.5 Power Consumption
4;5.1 ACTIVE POWER
With CE# at a logic-low level and RP# at a logichigh level, the device is placed in the active mode.
The device Icc current is a maximum of 22 mA at
5 MHz.
4.5.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low power feature during active mode of operation. The 4-Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the device to put itself into a low current state when it is
. not being accessed. After data is read from the
memory array, PRC logic controls the device's power consumption by entering the APS mode where
I
typical Icc current is 0.8 mA and maximum Icc c~r
rent is 2 mAo The device stays in this static state with
outputs valid until a new memory location is read.
4.5.3 STANDBY POWER
With CE# at a logic-high level (VIH), and the CUI
read mode, the memory is placed in standby mode
where the maximum Icc standby current is 120 p.A
with CMOS input signals. The standby operation disables much of the device's circuitry and substantially
reduces device power consumption. The outputs
(DO[0:151 or DO[0:71 are placed in a high-impedance state independent of the status of the OE #
signal. When the 4-Mbit flash family is deselected
during erase or program functions, the devices will
continue to perform the erase or program function
and consume program or erase active power until
program or erase is completed.
4-201
28F400BL-T IB, 28F004BL-T IB
4.5.4 RESET/DEEP POWER-DOWN
The 4-Mbit flash family supports a typical lee of
0.2 /LA in deep power-down mode. One of the target
markets for these devices is in portable equipment
where the power consumption of the machine is of
prime importance. The 4-Mbit flash family has a
RP# pin which places the device in the deep powerdown mode. When RP# is at a logic-low (GND
± 0.2V), all circuits are turned off and the device typically draws 0.2 /LA of Vee current.
During read modes, the RP# pin going low deselects the memory and places the output drivers in a
high impedance state. Recovery from the deep power-down state, requires a maximum of 600 ns to access valid data (tpHQV)'
During erase or program modes, RP# low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
corrupted by the RP# function. As in the read mode
above, all .internal circuitry is turned off to achieve
the 0.2 /LA current level.
RP# transitions to VIL or turning power off to the
device will clear the status register.
This use of RP# during system reset is important
with automated write/erase devices. When the system comes out of reset it expects to read from the
flash memory. Automated flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel's
Flash Memories allow proper CPU initialization following a system reset through the use of the RP#
input. In this application RP# is controlled by the
same RESET# signal that resets the system CPU.
4.6 Power-up Operation
The 4-Mbit flash memory family is designed to offer
protection against accidental block erasure or programming during power transitions. Upon power-up
the 4-Mbit flash memory family is indifferent as to
which power supply, Vpp or Vee, powers-up first.
Power supply sequencing is not required.
The 4-Mbit flash memory family ensures the CUI is
reset to the read mode on power-up.
In addition, on power-up the user must either drop
CE # low or present a new address to ensure valid
data at the outputs.
A system deSigner must guard against spurious
writes for Vee voltages above VLKO when ~pp is
4-202
active. Since both WE # and CE # must be low for a
command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides
an added level of protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. Finally
the device is disabled until RP# is brought to VIH,
regardless of the state of its control inputs. This feature provides yet another level of memory protection.
4.7 Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling methods. System
designers are interested in 3 supply current issues:
• Standby current levels (lees)
• Active current levels (leeR)
• Transient peaks produced by falling and rising
edges of CE # .
Transient current magnitudes depend on the device
outputs' capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 /LF ceramic capacitor
connected between each Vee and GND, and between its Vpp and GND. These high frequency, lowinherent inductance capacitors should be placed as
close as possible to the package leads.
4.7.1 Vpp TRACE ON PRINTED CIRCUIT
BOARDS
Writing to flash memories while they reside in the
target system, requires special consideration of the
Vpp power supply trace by the printed circuit board
deSigner. The Vpp pin supplies the flash memory
cell's current for programming and erasing. One
should use similar trace widths and layout considerations given to the Vee power supply trace. Adequate Vpp supply traces and decoupling will decrease spikes and overshoots.
4.7.2 Vee, Vpp AND RP# TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by Vpp or CE# transitions or WSM actions. Its state upon power-up, after exit from deep power-down mode or after Vee
transitions below VLKO (Lockout voltage), is Read
Array mode.
After any word/byte write or block erase operation is
complete and even after Vpp transitions down to
VpPL, the CUI must be reset to Read Array mode via
the Read Array. command when accesses to the
flash memory are desired.
I
28F400BL-T IB, 28F004BL-T IB
5.0 OPERATING SPECIFICATIONS
NOTICE: This is a production data sheet. The specifications are subject to change without notice .
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
During Read ............... - 20°C to + 70°C(1)
During Block Erase/Byte Write .... O°C to + 70°C
Storage Temperature .......... -65°C to
+ BO°C
+ 125°C
Voltage on any Pin
(except Vee, Vpp, Ag and RP#)
with Respect to GND ........ - 2.0V to
+ 7.0V(2)
Temperature Under Bias ......... -20°C to
Voltage on Pin RP# or Pin Ag
with Respect to GND ..... - 2.0V to
+ 13.5V(2, 3)
Vee Program Voltage with
Respect to GND
during Block Erase and
Word/Byte Write ......... - 2.0V to
+ 14.0V(2, 3)
Vee Supply Voltage
with Respect to GND ..... " . -2.0V to
+ 7.0V(2)
Output Short Circuit Current. ............ 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vcc + 0.5V which during transitions may overshoot to Vee + 2.0V
for periods < 20 ns.
3. Maximum De voltage on Vpp may overshoot to + 14.0V for periods <20 ns. Maximum DC voltage on RP# or Ag may
overshoot to 13.5V for periods < 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. Ae specifications are valid at both voltage ranges. See De Characteristics tables for voltage range-specific specifications.
OPERATING CONDITIONS
Symbol
Parameter
TA
Operating Temperature
Vcc
Vec Supply Voltage
Vce
Vec Supply Voltage
DC CHARACTERISTICS
Symbol
Notes
Min
Program/Erase
Read
5
Max
Unit
-20
70
°C
3.15
3.60
V
3.00
3.60
V
4.50
5.50
V
Vce = 3.3V +0
- .3V Read, 3 15V-3.6V Program/Erase
Parameter
Max
Unit
III
Input Load Current
1
±1.0
)J-A
Vce = Vee Max
VIN = VCC or GND
ILO
Output Leakage Current
1
±10
)J-A
Vee = Vce Max
VOUT = VccorGND
I
Notes
Min
Typ
Test Conditions
4-203
28F400BL-T IB, 28F004BL-T/B
DC CHARACTERISTICS
Symbol
Ices
vee = 3.3V ±0.3V Read, 3.15V-3.6V Program/Erase (Continued)
Parameter
Vee Standby Current
Notes Min Typ
1,3
Max
Unit
Test Conditions
45
120
p.A Vee = Vee Max
CE# = RP# = VIH
45
120
p.A Vee = Vee Max
CE# = RP# = Vee ±0.2V
28F400BX:
BYTE# = Vee ±0.2VorGND
IceD
Vee Deep Power-Down Current
. 1
0.20
1.2
p.A RP#
leeR
Vee Read Current for
28F400BX-L Word-Wide and
Byte-Wide Mode and
28F004BX-L Byte-Wide Mode
1
5,6
15
25
mA Vee = Vee Max, CE# = GND
f = 5 MHz, lOUT = 0 mA
CMOS Inputs
15
25
mA Vee = Vee Max, CE# = VIL
f = 5 MHz, lOUT = 0 mA
TTL Inputs
1
30
mA Word Write in Progress
leew
Vee Word Write Current
=
GND ±0.2V
leew
Vee Byte Write Current
1
30
mA Byte Write in Progress
IeeE
Vee Block Erase Current
1
20
mA Block Erase in Progress
leeES
Vee Erase Suspend Current
6
mA Block Erase Suspended,
CE# = VIH
Ipps
Vpp Standby Current
1
±15
p.A Vpp::;; Vee
IpPD
Vpp Deep Power-Down Current
1
5.0
p.A RP#
IpPR
Vpp Read Current
1,4
200
p.A Vpp> Vee
Ippw
Vpp Word Write Current
1,4
40
mA Vpp = VPPH
Word Write in Progress
Ippw
Vpp Byte Write Current
1,4
30
mA Vpp = VPPH
Byte Write in Progress
IpPE
Vpp Block Erase Current
1,4
30
mA Vpp = VPPH
Block Erase in Progress
IpPES
VPP Erase Suspend Current
1
200
p.A VPP = VPPH
Block Erase Suspended
1,2
3
IRP#
RP# Boot Block Unlock Current
1,4
500
p.A RP#
110
Ag Intelligent Identifier Current
1,4
500
p.A Ag
VID
Ag Intelligent Identifier Voltage
11.4 12.0
13.0
V
VIL
Input Low Voltage
-0.5
0.6
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
4-204
Vee
+ 0.5
0.4
=
=
=
GND ±0.2V
VHH
VID
V
V
Vee = Vee Min
IOL = 2mA
I
28F400BL-T IB, 28F004BL-T IB
DC CHARACTERISTICS
Symbol
Vee = 3.3V ±0.3V Read, 3.15V-3.6V Program/Erase (Continued)
Parameter
VOH1
Output High Voltage (TTL)
VOH2
Output High Voltage
(CMOS)
Notes
Min
Typ Max Unit
2.4
V
Vee = Vee Min
IOH = -2mA
0.85 Vee
V
IOH = -2.5mA
Vee = Vee Min
IOH = -100/LA
Vee = Vee Min
Vee -0.4
VPPL
VPP during Normal Operations
VPPH
VPP during Erase/Write Operations
VLKO
Vee Erase/Write Lock Voltage
2.0
VHH
RP# Unlock Voltage
11.4
CAPACITANCE(4) TA =
Symbol
25°C, f
=
Test Conditions
3
0.0
11.4
4.1
12.0 12.6
V
V
V
12.0 13.0
V
Boot Block Write/Erase
1 MHz
Parameter
Typ
Mal(
Unit
Condition
=
CIN
Input Capacitance
6
8
pF
VIN
COUT
Output Capacitance
10
12
pF
VOUT
OV
=
OV
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, VPP = 12.0V, T = 25°C. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
of ICCES and ICCR.
3. Block Erase and Word/Byte Writes are inhibited when VPP = VPPL and not guaranteed in the range between VpPH and
VPPL·
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces ICCR to less than 1 mA in static operation.
6. CMOS Inputs are either VCC ±0.2V or GND ±0.2V. TTL Inputs are either VIL or VIH.
I
4-205
28F400BL-T IB, 28F004BL-T IB
DC CHARACTERisTICS(4)
Symbol
vee = 5.0V ±10%
Parameter
Notes Min
Unit
Input Load Current
1
±1.0
/J- A
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage Current
1
±10
/J- A
Vee = Vee Max
VOUT = VeeorGND
lees
Vee Standby Current
1
1.5
mA
Vee = Vee Max
CE# = RP# = VIH
100
/J- A
Vee = Vee Max
CE# = RP# = Vee ±0.2V
1
1.2
/J- A
1
40
rnA
leCD
Vee Deep Power-Down Current
leeR
Vee Read Current for
28F400BX-L Word-Wide Mode
and Byte Wide Mode
and 28F004BX-L
Typ
Test Conditions
Max
III
= GND ±0.2V
= 0 mA
Vee = Vee Max, CE# =
f = 5 MHz, lOUT = 0 rnA
RP#
lOUT
CMOS Inputs
40
rnA
Vee = Vee Max, CE# = VIL
f = 5 MHz, lOUT = 0 rnA
TTL Inputs
leew
Vee Word Byte Write Current
1,4
70
rnA
Word Write in Progress
IeeE
Vee Block Erase Current
1,4
30
rnA
Block Erase in Progress
leeES
Vee Erase Suspend Current
1,2
10
rnA
Block Erase Suspended,
CE# = VIH
IpPS
Vpp Standby Current
1
±10
/J- A
Vpp ~ Vee
Ippo
Vpp Deep Power-Down Current
1
5.0
/J- A
RP#
IpPR
Vpp Read Current
1
200
/J- A
Vpp> Vee
Ippw
Vpp Word Write Current
1,4
40
rnA
Vpp = VPPH
Word Write in Progress
Ippw
Vpp Byte Write Current
1,4
30
rnA
Vpp = VPPH
Byte Write in Progress
IpPE
Vpp Block Erase Current
1,4
30
rnA
Vpp = VPPH
Block Erase in Progress
IpPES
VPP Erase Suspend Current
1
200
/J- A
Vpp = VPPH
Block Erase Suspended
IRP#
RP# Boot Block
Unlock Current
1,4
500
/J- A
RP#
110
Ag Intelligent
Identifier Current
1,4
500
/J-A
Ag
VIO
Ag Intelligent
Identifier Voltage
13.0
V
4-206
GND
11.4 12.0
=
=
=
GND ±0.2V
VHH
VID
I
28F400BL·T IB, 28F004BL·T IB
DC CHARACTERISTICS(4) vee = 5.0V ±10% (Continued)
Symbol
Parameter
Notes
Typ
Min
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOHl
Output High Voltage (TIL)
VOH2
Output High Voltage
(CMOS)
VIL
Max
Unit
0.8
V
Vee
+ 0.5
V
V
Vee = Vee Min
IOL = 5.8 rnA
2.4
V
Vee = Vee Min
IOH = -2.5 rnA
0.85 Vee
V
IOL = -2.5 rnA
Vee = Vee Min
0.45
IOL = -100 fJ-A
Vee = Vee Min
Vee -0.4
3
Test Condition
VPPL
VPP during Normal Operations
VPPH
VPP during Erase/Write Operations
VLKO
Vee Erase/Write Lock Voltage
2.2
VHH
RP# Unlock Voltage
11.4
6.5
V
12.0
12.6
V
12.0
13.0
V
0.0
11.4
V
Boot Block Write/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, VPP = 12.0V, T = 25°C. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected" If the device is read while in Erase Suspend Mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases and Word/Byte Writes are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and
VpPL·
4. All parameters are sampled, not 100% tested.
AC INPUT/OUTPUT REFERENCE WAVEFORM
AC TESTING LOAD CIRCUIT
1.3V
-~
~~lN914
S_
3.0 --I-NP-U-T"'X1.
0.0
TESTI ~INTS
II
_
X1.S
OUTPUT
Rt.
290450-16
Ae test inputs are driven at 3.0V for a Logic "1" and 0.0 for a Logic "0".
Input timing begins, and output timing ends at 1.5V. Input rise and fall times
(10% to 90%) < 3 ns.
DEVICE
UNDER
TEST
OUT
i~
--
290450-17
eL=50pF
eL Includes Jig Capacitance
RL = 3.3 KO
I
4-207
28F400BL"T IB, 28F004BL-T IB
AC CHARACTERISTICS-Read-Only Operations(1) vcc
= 3.3V ±0.3V, 5.0V ±10%
28F400BL-150
28FOO4BL-150
Versions
Parameter
Symbol
Notes
Min
Unit
Max
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
tELQV
tCE
CE # to Output Delay
tpHQV
tpWH
RP# High to Output Delay
tGLQV
tOE
OE # to Output Delay
2
tELQX
tLZ
CE # to Output Low Z
3
tEHOZ
tHZ
CE# High to Output High Z
3
tGLQX
tOLZ
OE # to Output Low Z
3
tDF
OE# High to Output High
tOH
Output Hold from Addresses, CE # or OE #
Change, Whichever is First
3
tELFL
tELFH
CE # to BYTE # Switching
Low or High
3
5
ns
tFHQV
BYTE# Switching High
to Valid Output Delay
3,4
150
ns
tFLQZ
BYTE# Switching Low
to Output High Z
3
45
ns
tGHQZ
150
2
Z
ns
150
ns
150
ns
600
ns
65
ns
ns
0
55
0
3
ns
ns
45
0
ns
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE # may be delayed up to tCE·toE after the falling edge of CE # without impact on tCE.
3. Sampled, not 100% tested.
4. tFLQV, BYTE# switching low to valid output delay will be equal to tAVQV, measured from the time DQ1S/A.1 becomes
valid.
4·208
I
_.
Vee POWER-UP
DEVICE AND
ADDRESS SELECTION
STANDBY
OUTPUTS ENABLED
DATA VALID
STANDBY
Vee POWER-DOWN
V1H
ADDRESSES (A)
ADDRESSES STABLE
€:
@)
V1l
I' .
1'1
t AVAV
V1H
CE# (E)
V1l
"II'
IE
C
iil
V1H
....
PI
l;
OE# (G)
V1l
:::e
......~
ID
V1H
0
3
WE# (w)
......
III
V1l
0
'oH
:II
ID
III
V1H
a.
0
'a
ID
HIGH Z
VALID OUTPUT
l
V1l
iilC!:
0------ tAVQV
0
:J
III
HIGH Z
DATA (D/a)
I\)
'1
CO
~
5.0V
Vee
GND
V
1H
o
1
m
~
IpHQV
,!II
~
.,
;!I
RP# (p)
o
.&loo
m
Vll -
~
~
co
290450-18
~m
28F400BL-T /B, 28F004BL-T/B
V,H
ADDRESSES STABLE
ADDRESSES (A)
V,L
1-----------
IAVAV
---------+--1
V,H
CE# (C)
V,L
IAVFL = 'rLFL
V,H
OE# (G)
V,L
V,H
BYTE# (F)
V,L
"'LOV
V,H
HIGH Z
DATA OUTPUT
ON OQO-O
CE# (E)
::E
DI
-...
-...
READ STATUS
REGISTER DATA
ADDRESSES (A)
III
0
AUTOMATED PROGRAI.I
OR ERASE DELAY
-:::J
VIH
~."
IE
WRITE
VALID ADDRESS & DATA (PROGRAM)
OR ERASE CONFIRM COMMAND
V1L
<
III
0
3
Ul
VIH
OE# (G)
VIL
0
...::E;:;:
III
DI
VIH
WE# (w)
~
VIL
Q.
...m
DI
Ul
III
VIH
0
"tI
III
...
DATA (D/a)
VIL
!!l.
o·
~
Ul
=em
VHH
~
0
...'2-3-"'
~
~
aI
VIL
~
......
j---..J tVPWH
iii
...::E;:;:
."
o
o
RP# (p)
Q.
III
I\)
Q)
6.SV
VIH
Vpp (V)
VpPH
jJl
VpPL
VIH
."
VIL
aI
I\)
Q)
o
o
~
.j>.
~
w
290450-19
~
......
aI
28F400BL-T IB, 28F004BL-T IB
AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS
vcc = 3.15V-3.6V, 5.0V ±10%
28F400BL-150
28FOO4BL-150
Versions
Symbol
Parameter
Notes
Min
Unit
Max
tAVAV
twc
Write Cycle Time
150
ns
tPHEl
tps
RP# High Recovery to
CE # Going Low
1.0
p:s
tWlEl
tws
WE# Setup to CE# Going Low
0
ns
tpHHEH
tpHS
RP# VHH Setup to CE# Going High
6,8
200
ns
tVPEH
tvps
VPP Setup to CE # Going High
5,8
200
ns
tAVEH
tAS
Address Setup to CE# Going High
3
95
ns
tOVEH
tos
Data Setup to CE# Going High
4
100
ns
tElEH
tcp
CE # Pulse Width
100
ns
tEHOX
tOH
Data Hold from CE # High
4
0
ns
3
10
ns
10
ns
tEHAX
tAH
Address Hold from CE# High
tEHWH
tWH
WE# Hold from CE# High
tEHEl
tCPH
CE# Pulse Width High
50
ns
tEHOV1
Duration of Programming
Operation Word/Byte
2,5,6
6
p:s
tEHOV2
Duration of Erase Operation (Boot)
2,5,6
0.3
s
tEHOV3
Duration of Erase
Operation (Parameter)
2,5,6
0.3
s
2,5,6
0.6
s
5,8
0
ns
0
Duration of Erase Operation (Main)
tEHOV4
tOWl
tVPH
VPP Hold from Valid SAD
tOVPH
tpPH
RP# VHH Hold from Valid SRD
6,8
Boot-Block Relock Delay
7,8
tpHBR
I
ns
200
ns
NOTES:
1. Chip·Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE# waveform.
2,3,4,5,6,7,8. Refer to AC Characteristics for WE#·Controlied Write operations.
9. Read timing characteristics during write and erase operations are the same as during read·only operations. Refer to AC
Characteristics during Read Mode.
4-214
I
vee POWER-UP
"11
iFi
" STANDBY
...
c:
...
!"
CD
WRITE PROGRAM OR
ERASE SETUP COMMAND
WRITE
VALID ADDRESS" DATA(PROGRAM)
OR ERASE CONFIRM COMMAND
--
AUTOMATED PROGRAM
OR ERASE DELAY
READ STATUS
REGISTER DATA
€:
WRITE READ ARRAY
COMMAND
V1H
ADDRESSES (A)
AtN
@
V1L
l>
~HAX
;:;
CD
V1H
!I
WE# (W)
V1L
0
II
V1H
OE# (G)
V1L
3
I•
1/1
~HQV 1.2.3.4
-I
V1H
;1
CE# (E)
V1L
CD
DI
j
c.
!I
V1H
DATA (0/0)
V1L
"0
CD
...
!!l.
O·
VHH
j
1/1
If-tp~H~
. ____ -----------------
N
QI)
."
6.SV
V1H
RP# (p)
'0
In
'fI,
(,
""oo
OJ
V1L
~
0
...!2.3-
tYPEH
VpPH
~OJ
(v) VPPL
."
N
CD
c.
...;:;:::E
CD
.j>.
~
C.11
..!!!.
v
PP
QI)
o
V1H
o
""OJ
V1L
290450-20
~
......
OJ
28F400BL-T IB, 28F004BL-T IB
ORDERING INFORMATION
T'
IE121s1F1410101Blll-ITI qslol
'I
PACKAGE
E = STANDARD 56 lEAD TSOP
PA = 44 lEAD PSOP
LACCE~S
SPEED (ns)
150 ns
BOOT BLOCK lOCATION
T = TOP BOOT
B = BOTTOM BOOT
290450-21
VALID COMBINATIONS:
E28F400BL-T150
E28F400BL-B150
PA28F400BL-T150
PA28F400BL-B150
T'
IE 121s1 Flo I 0 141 Bill-I T ,1,5,0 I
'I
PACKAGE
E
= STANDARD 40
lEAD TSOP
LACCE~S
SPEED (ns)
150 ns
BOOT BLOCK lOCATION
T = TOP BOOT
B = BOTTOM BOOT
290450-22
VALID COMBINATIONS:
E28F004BL-T150
E28F004BL-B150
ADDITIONAL INFORMATION
Order
Number
Document
292130
AB-57 "Boot Block Architecture for Safe Firmware Updates"
292154
AB-60 "2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family"
292098
AP-363 "Extended Flash BIOS Concepts for Portable Computers"
292148
AP-604 "Using Intel's Boot Block Flash Memory Parameter Blocks to Replace EEP.ROM"
290448
28F002/200-T IB Mbit Boot Block Flash Memory Datasheet
290449
28F002/200BL-T/B 2 Mbit Low Power Boot Block Flash Memory Datasheet
290451
28F0041 400BX-TIB 4-Mbit Boot Block Flash Memory Datasheet
290531
2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290530
4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290539
8-~bit
4-216
SmartVoltage Boot Block Flash Memory Family Datasheet
I
28F400BL·T IB, 28F004BL·T IB
REVISION HISTORY
Number
Description
-001
Original Version
-002
Modified BYTE # Timing Waveforms
Modified tDvwH parameter for AC Characteristics for Write Operations
-003
PWD renamed to RP# for JEDEC standarization compatibility.
Combined Vcc Read Current for 28F400BX-L Word-Wide and Byte-Wide Mode
and 28F004BX-L Byte Wide Mode in DC Characteristics tables.
Changed Ipps current spec from
± 10 p..A to ± 15 p..A in DC Characteristics table.
Added Boot Block Unlock current spec in DC Characteristics tables.
Improved tpWH spec to 600 ns (was 700 ns).
Changed ICCR maximum spec from 20 mA to 25 mA, and added 15 mA typical spec
in DC Characteristics Table.
-004
Added IOH CMOS specification,
Expanded temperature operating range
from 0·C-70·C to - 20·C-70·C
Product naming changed:
28F400BX-TL/BL changed to 28F400BL-T IB
28F004BX-TL/BL changed to 28F004BL-T IB
Typographical errors corrected.
Added 28F400BX interface to Intel386TM EX
Embedded Processor block diagram.
Added upgrade considerations for
SmartVoltage Boot Block products.
Previously specified Vcc tolerance of 3.0V to 3.6V for Read,
Program and Erase has been changed to 3.15V to 3.6V for
Program and Erase while Read remains 3.0V to 3.6V
I
4-217
infel®
28F200BX-T/B,28F002BX-T/B
2-MBIT (128K x 16, 256K x 8) BOOT BLOCK
FLASH MEMORY FAMILY
• x8/x16 Input/Output Architecture
- 28F200BX-T, 28F200BX-B
- For High Performance and High
Integration 16-bit and 32-b!t CPUs
• x8-only Input/Output Architecture
- 28F002BX-T 28F002BX-B
- For Space Constrained 8~bit
Applications
• Upgradable to Intel's SmartVoltage
Products
• Optimized High Density Blocked
Architecture
- One 16-KB Protected Boot Block
- Two 8-KB Parameter Blocks
- One 96-KB Main Block
- One 128 KB Main Block
- Top or Bottom Boot Locations
• Extended Cycling Capability
-100,000 Block Erase Cycles
• Automated Word/Byte Write and
Block Erase
- Command User Interface
..,.... Status Registers
- Erase Suspend Capability
• SRAM-Compatible Write Interface
• Automatic Power Savings Feature
- 1 mA Typical Icc Active Current in
Static Operation
4-218
• Hardware Data Protection Feature
- Erase/Write Lockout during Power
Transitions
• Very High-Performance Read
- 60/80/120 ns Maximum Access Time
-30/40/40 ns Maximum Output Enable
Time
•
Low Power Consumption
- 20 mA Typical Active Read Current
• Reset/Deep Power-Down Input
- 0.2 /-tA Icc Typical
- Acts as Reset for Boot Operations
• Extended Temperature Operation
- - 40°C to + 85°C
• Write Protection for Boot Block
• Industry Standard Surface Mount
Packaging
- 28F200BX: JEDEC ROM Compatible
44-Lead PSOP
56-Lead TSOP
- 28F002BX: 40-Lead TSOP
•
12V Word/Byte Write and Block Erase
-Vpp = 12V ±5% Standard
- Vpp = 12V ± 10% Option
• ETOX III Flash Technology
-5V Read
• Independent Software Vendor Support
November 1994
Order Number: 290448-004
28F200BX-T IB, 28F002BX-T IB
Intel's 2-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selective erasure, automated write and erase operations and standard microprocessor interface. The 2-Mbit Flash
Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16 input/output control, very high speed, low power, an industry standard ROM compatible pinout and surface mount
packaging. The 2-Mbit flash family allows for an easy upgrade to Intel's 4-Mbit Boot Block Flash Memory
Family.
The Intel 28F200BX-T/B are 16-bit wide flash memory offerings. These high density flash memories provide
user selectable bus operation for either 8-bit or 16-bit applications. The 28F200BX-T and 28F200BX-B are
2,097, 152-bit non-volatile memories organized as either 262,144 bytes or 131 ,072 words of information. They
are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industry
standard ROM/EPROM pinout.
The Intel 28F002BX-T/B are 8-bit wide flash memories with 2,097,152 bits organized as 262,144 bytes of
information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable
systems.
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The 28F200BX-T/28F002BX-T provide block locations compatible with
Intel's MCS-186 family, 80286, i386™, i486™, i860TM and 80960CA microprocessors. The 28F200BX-BI
2BF002BX-B provide compatibility with Intel's 80960KX and B0960SX families as well as other embedded
microprocessors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 60 ns, these 2-Mbit flash devices are very high performance memories which
interface at zero-wait-state to a wide range of microprocessors and microcontrollers. A deep power-down
mode lowers the total Vee power consumption to 1 IlW typical. This is critical in handheld battery powered
systems. For very low power applications using a 3.3V supply, refer to the InteI2BF200BX-TL/BL, 2BF002BXTL/BL 2-Mbit Boot Block Flash Memory Family datasheet.
Manufactured on Intel's O.B micron ETOXIII process, the 2-Mbit flash memory family provides world class
quality, reliability and cost-effectiveness at the 2-Mbit density level.
I
4-219
28F200BX-T/B,28F002BX-T/B
1.0 PRODUCT FAMILY OVERVIEW
1.2 Main Features
Throughout this datasheet the 28F200BX refers to
both the 28F200BX-T and 28F200BX-B devices and
28F002BX refers to both the 28F002BX-T and
28F002BX-B devices. The 2-Mbit flash memory family refers to both the 28F200BX and 28F002BX products. This datasheet comprises the specifications for
four separate products in the 2-Mbit flash memory
family. Section 1 provides an overview of the 2-Mbit
flash memory family including applications, pinouts
and pin descriptions. Sections 2 and 3 describe in
detail the specific memory organizations for the
28F200BX and 28F002BX products respectively.
Section 4 combines a description of the family's
principles of operations. Finally Section 5 describes
the family's operating specifications.
The 28F200BX/28F002BX boot block flash memory
family is a very high performance 2-Mbit (2,097,152
bit) memory family organized as either 128 KWords
(131,072 words) of 16 bits each or 256 Kbytes
(262,144 bytes) of 8 bits each.
Five Separately Erasable Blocks including a hardware-lockable boot block (16,384 Bytes), two parameter blocks (8,192 Bytes each) and two main
blocks (1 block of 98,304 Bytes and 1 block of
131,072 Bytes) are included on the 2-Mbit family. An
erase operation erases one of the main blocks in
typically 2.4 seconds, and the boot or parameter
blocks in typically 1.0 second. Each block can be
independently erased and programmed 100,000
times.
PRODUCT FAMIL V
x8/x16 Products
x8-0nly Products
28F200BX-T
28F002BX-T
28F200BX-B
28F002BX-B
1.1 Designing for Upgrade to
SmartVoltage Products
Today's high volume boot block products are upgradable to Intel's SmartVoltage boot block products that provide program and erase operation at 5V
or 12V Vpp and read operation at 3V or 5V Vee.
Intel's SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this data sheet:
1. DU pin is replaced by WP# to provide a means
to lock and unlock the boot block with logic signals.
2. 5V Program/Erase operation uses proven program and erase techniques with 5V ± 10% applied to VPP.
3. Enhanced circuits optimize performance at 3.3V
Vee·
Refer to the 2, 4 or 8 Mbit SmartVoltage Boot Block
Flash Memory Data Sheets for complete specifications.
When you design with 12V Vpp boot block products
you should provide the capability in your board design to upgrade to SmartVoltage products.
Follow these guidelines to ensure compatibility:
1. Connect DU (WP # on SmartVoltage products) to
a control signal or to Vee or GND.
2. If adding a switch on Vpp for write protection,·
switch to GND for complete write protection.
3. Allow for connecting 5V to Vpp and disconnect
12V from the Vpp line, if desired.
4-220
The Boot Block is located at either the top
(28F200BX-T, 28F002BX-T) or the bottom
(28F200BX-B, 28F002BX-B) of the address map in
order to accommodate different microprocessor protocols for boot code location. The hardware lockable boot block provides the most secure code storage. The boot block is intended to store the kernel
code required for booting-up a system. When the
RP# pin is between 11.4V and 12.6V the boot block
is unlocked and program and erase operations can
be performed. When the RP# pin is at or below 6.5V
the boot block is locked and program and erase operations to the boot block are ignored.
The 28F200BX products are available in the ROM/
EPROM compatible pinout and housed in the 44Lead PSOP (Plastic Small Outline) package and the
56-Lead TSOP (Thin Small Outline, 1.2mm thick)
package as shown in Figures 3 and 4. The
28F002BX products are available in the 40-Lead
TSOP (1.2mm thick) package as shown in Figure 5.
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcontroller and the internal operation of the 28F200BX
and 28F002BX flash memory products.
Program and Erase Automation allows program
and erase operations to be executed using a twowrite command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in word or
byte increments for the 28F200BX family and in byte
increments for the 28F002BX family typically within
9 fLs which is a 100% improvement over current
flash memory products.
I
28F200BX-T IB, 28F002BX-T IB
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.
Maximum Access Time of 60 ns (TACC) is achieved
over the commercial temperature range (O°C to
70°C), 5% Vcc supply voltage range (4.75V to
5.25V) and 30 pF output load. Refer to Figure 19;
TACC vs Output Load Capacitance for larger output
loads. Maximum Access Time of 80 ns (TACC) is
achieved over the commercial temperature range,
10% Vcc supply range (4.5V to 5.5V) and 100 pF
output load.
Ipp maximum Program current is 40 rnA for x16
operation and 30 rnA for x8 operation. Ipp Erase
current is 30 mA maldmum. Vpp erase and programming voltage Is 11.4V to 12.6V (Vpp = 12V
±5%) under all operating conditions. As an option, Vpp can also vary between 1O.BV to 13.2V (Vpp
= 12V ± 10%) with a guaranteed number of 100
block erase cycles.
Typical Icc Active Current of 25 mA is achieved
for the x16 products (2BF200BX), typical Icc Active
Current of 20 rnA is achieved for the xB products
(2BF200BX, 2BF002BX). Refer to the Icc active current derating curves in this datasheet.
The 2-Mbit boot block flash family is also designed
with an Automatic Power Savings (APS) feature to
minimize system battery current drain and allow for
very low power designs. Once the device is accessed to read array data, APS mode will immediately put the memory in static mode of operation
where ICC active current is typically 1 mA until the
next read is initiated.
When the CE # and RP # pins are at Vcc and the
BYTE# pin (2BF200BX-only) is at either VCC or
GNO the CMOS Standby mode is enabled where
ICC is typically 50 JJ-A.
A Deep Power-Down Mode is enabled when the
RP# pin is at ground minimizing power consumption
and providing write protection during power-up conditions. ICC current during deep power-down mode
is 0.20 JJ-A typical. An initial maximum access time
or Reset Time of 300 ns is required from RP#
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 215 ns until
writes to the Command User Interface are recognized. When RP # is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature prevents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to RP# to reset the memory to normal read mode upon activation of the Reset pin.
With on-chip program/erase automation in the
2-Mbit family and the RP# functionality for data pro-
I
tection, when the CPU is reset and even if a program
or erase command is issued, the device will not recognize any operation until RP# returns to its normal
state.
For the 28F200BX, Byte-wide or Word-wide Input/Output Control is possible by controlling the
BYTE# pin. When the BYTE# pin is at a logic low
the device is in the byte-wide mode (xB) and data is
read and written through 00[0:7]. During the bytewide mode, 00[B:14] are tri-stated and 0015/A-1
becomes the lowest order address pin. When the
BYTE# pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through 00[0:15].
1.3 Applications
The 2-Mbit boot block flash family combines high
density, high performance, cost-effective flash memories with blocking and hardware protection capabilities. Its flexibility and versatility will reduce costs
throughout the product life cycle. Flash memory is
ideal for Just-In-Time production flow, reducing system inventory and costs, and eliminating component
handling during the production' phase. During the
product life cycle, when code updates or feature enhancements become necessary, flash memory will
reduce the update costs by allowing either a userperformed code change via floppy disk or a remote
code change via a serial link. The 2-Mbit boot block
flash family provides full function, blocked flash
memories suitable for a wide range of applications.
These applications include Extended PC BIOS,
Digital Cellular Phone program and data storage,
Telecommunication boot/firmware, and various
other embedded applications where both program
and data storage are required.
Reprogrammable systems such as personal computers, are ideal applications for the 2-Mbit flash
products. Portable and handheld personal computer
applications are becoming more complex with the
addition of power management software to take advantage of the latest microprocessor technology,
the availability of ROM-based application software,
pen tablet code for electronic hand writing, and diagnostic code. Figure 1 shows an example of a
2BF200BX-T application.
This increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped. The 2-Mbit flash products
provide an inexpensive update solution for the notebook and handheld personal computers while extending their product lifetime. Furthermore, the
2-Mbit flash products' power-down mode provides
added flexibility for these battery-operated portable
designs which require operation at very low power
levels.
4-221
28F200BX-T/B,28F002BX-T/B
messages (e.g. phone numbers, authorization
codes). Figure 2 is an example of such an application with the 2BF002BX-T.
The 2-Mbit flash products also provide excellent design solutions for Digital Cellular Phone and Telecommunication switching applications requiring high
performance, high density storage capability coupled with modular software designs, and a small
form factor package (xB-only bus). The 2-Mbit's
blocking scheme allows for an easy segmentation of
the embedded code with; 16 Kbytes of HardwareProtected Boot code, 2 Main Blocks of program
code and 2 Parameter Blocks of B Kbytes each for
frequently updatable data storage and diagnostic
These are a few actual examples of the wide range
of applications for the 2-Mbit Boot Block flash memory family which enable system designers to achieve
the best possible product design. Only your imagination limits the applicability of such a versatile product
family.
12V
GPIO
RESET#
=D--i,,-rt~.
1
1
1
Vpp
A[0:16J
CS#
1-----------,/
t-----------..
RO#
Inla1386" EX
Embeddad
Processor
A[0:16J
CE#
OE#
Inial
28F200BX-T
t--------1~ WE#
WR#
O[O:ISJ
v OQ[O: ISJ
-I..:T..:.;rc::.:.":sc:e;..:,ive.::,r.J-_ _ _
GPIO--r-_
RESET#
. PWRGOOO
--L._
RP#
290448-4
Figure 1. 28F200BX Interface to Intel386™ EX Embedded Processor
A'6: '7
a I5
A -A
ALE
t----,/I
1-:===t-====:-i
I-
80C188EB
USC# 1 - - - - - - - - - - - - - - - + l C E # 28F002BX-T
Vpp
P1.X
1-----+1
RP#
WR#I-------------~WE#
RO#
RESIN#
OE#
t---_------------------'
SYSTEM RESET
290448-24
Figure 2. 28F002BX Interface to INTEL 80C188EB 8-Bit Embedded Microprocessor
4-222
I
28F200BX-T/B,28F002BX-T/B
1.4 Pinouts
The 28F200BX 44-Lead PSOP pinout follows the industry standard ROM/EPROM pinout as shown in
Figure 3 with an upgrade to the 28F400BX (4-Mbit
flash family). Furthermore, the 28F200BX 56-Lead
TSOP pinout shown in Figure 4 provides density upgrades to the 28F400BX and to future higher density
boot block memories.
The 28F002BX 40-Lead TSOP pinout shown in Figure 5 is 100% compatible and provides a density
upgrade to the 28F004BX 4-Mbit Boot Block flash
memory.
28F400BX
Vpp
DU
A17
A7
A6
A5
A4
A3
A2
A1
Ao
CE#
GND
OE#
DOO
DOs
D01
DOg
D02
D010
D03
D011
28F400BX
vpp
RP#
DU
WE#
NC
AB
41
A7
As
As
A,a
As
A"
A.
A'2
A'3
A3
A2
A,
Ao
CE#
GND
OE#
000
PA28F200BX
44 lEAD PSOP
0.525" )( 1.110"
TOP VIEW
A,.
A,S
A'6
BYTE#
GND
31
DO'S/A-,
DO,
DOB
D0,.
0o,
006
DOs
0°,3
0°2
DOs
0°'0
003
0°'2
D0.
DO"
Vee
RP#
WE#
As
Ag
A10
A11
A12
A13
A14
A15
A16
BYTE#
GND
D015/A-1
D07
D014
D06
D013
D05
D012
D04
Vee
290448-25
Figure 3. PSOP Lead Configuration for x8/)(16 28F200BX
I
4-223
intel®
28F200BX-T/B,28FOO2BX-T/B
28F400BX
NC
NC
A1S
A14
A13
A12
All
Al0
Ag
A8
NC
NC
WE#
RP#
NC
NC
Vpp
DU
NC
A17
A7
A6
As
A4
A3
A2
Al
NC
NC
NC
A,S
A'4
A,3
A'2
~O
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A"
A,o
Ag
Aa
NC
NC
WE#
RP#
NC
NC
Vpp
DU
NC
NC
A7
As
As
A4
A3
A2
A,
NC
28F200BX
56- LEAD TSOP
14mm X 20mm
TOP VIEW
28F400BX
NC
A'6
BYTE #
GND
D01S/A_l
007
0014
DOe
0013
DOs
0012
004
56
55
54
53
52
51
50
49
48
47
46
45
NC
A,S
BYTE#
GND
DO,S/A_,
D07
DO'4
DOS
0°,3
DOs
0°,2
0°4
44
Vee
Vee
Vee
Vee
DO"
003
DO, 0
0°2
DOg
DO,
DOa
000
OE#
GND
CE#
Ao
NC
NC
0011
003
DOlO
002
DOg
001
DOa
000
OE#
GND
CE#
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Ao
NC
NC
290448-3
Figure 4. TSOP Lead Configuration for x8/x16 28F200BX
28FOO4BX
A16
A,s
A14
A13
A12
All
Ag
A8
WE#
RP#
vPP
DU
Aa
A7
A6
As
A4
A3
A2
Al
28FOO4BX
A,s
A,s
A'4
A'3
A'2
A"
Ag
Aa
WE#
RP#
Vpp
DU
NC
A7
As
As
A4
A3
A2
A,
~O
3
4
5
6
7
8
11
12
13
14
15
16
17
18
19
20
28F002BX
40- LEAD TSOP
10mm X 20mm
TOP VIEW
40
39
3a
37
36
35
34
33
32
31
30
29
28
27
26
25
24.
23
22
21
A'7'
GND
NC
NC
A,o
DOs
DOs
DO"
A17
GND
NC
NC
Al0
007
006
DOs
004
Vee
Vee
Vee
Vee
D~
NC
D03
D02
DO,
DOo
OE#
GND
CE#
Ao
NC
003
002
001
DOo
OE#
GND
CE#
Ao
290448-20
Figure 5. TSOP Lead Configuration for x8 28FOO2BX
4·224
I
28F200BX-T /B, 28F0028X-T /8
1.5 Pin Descriptions for the xS/lt16 28f'200BX
Symbol
Type
Name and Function
Ao-A16
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle.
Ag
I
ADDRESS INPUT: When Ag is at 12V the signature mode is accessed. During this
mode Ao decodes between the manufacturer and device 10's. When BYTE # is at
a logic low only the lower byte of the signatures are read. 0015/ A-1 is a don't
care in the signature mode when BYTE# is low.
000- 007
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and Status Register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.
008- 0015
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CE # and WE # cycle
during a program command. Data is internally latched during the write and program
cycles. Outputs array data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled as in the byte-wide mode (BYTE # = "0").
In the byte-wide mode 0015/ A-1 becomes the lowest order address for data
output on 000-007.
CE#
I
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE # is active low; CE # high deselects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow through
the CE# and RP# input stages.
RP#
I
RESET/DEEP POWER·DOWN: Provides three-state control. Puts the device in
deep power-down mode. Locks the boot block from program/erase.
When RP# is at logic high level and equals 6.5V maximum the boot block is
locked and cannot be programmed or erased.
When RP# = 11.4V minimum the boot block is unlocked and can be programmed
or erased.
When RP# is at a logic low level the boot block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RP # transitions from logic low to logic high the flash memory
enters the read array mode.
OE#
I
OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. OE # is active low.
WE#
I
WRITE ENABLE: Controls writes to the Command Register and array blocks.
WE# is active low. Addresses and data are latched on the rising edge of the WE#
pulse.
BYTE #
I
BVTE# ENABLE: Controls whether the device operates in the byte-wide mode
(x8) or the word-wide mode (x16). BYTE # pin must be controlled at CMOS levels
to meet 100 /LA CMOS current in the standby mode. BYTE # = "0" enables the
byte-wide mode, where data is read and programmed on 000-007 and
0015/ A-1 becomes the lowest order address that decodes between the upper
and lower byte. 008-0014 are tri-stated during the byte-wide mode.
BYTE # = "1" enables the word-wide mode where data is read and programmed
on 000-0015.
Vpp
PROGRAM/ERASE POWER SUPPlV: For erasing memory array blocks or
programming data in each block.
Note: Vpp < VPPLMAX memory contents cannot be altered.
Vee
GNO·
DEVICE POWER SUPPLY (5V
NC
NO CONNECT: Pin may be driven or left floating.
OU
DON'T USE PIN: Pin should not be connected to anything.
I
± 10%, 5V ± 5%)
GROUND: For all internal circuitry.
4-225
28F200BX·T IB, 28F002BX·T IB
1.6 Pin Descriptions for x8 28F002BX
Type
Name and Function
Ao-A17
Symbol
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.
Ag
I
ADDRESS INPUT: When Ag is at 12V the signature mode is accessed. During this
mode Ao decodes between the manufacturer and device ID's.
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CE # and WE # cycle
during a program command. Inputs commands to the command user interface
when CE # and WE # are active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and status register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.
000- 00 7
CE#
I
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE # is active low; CE # high deselects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not at
a CMOS high level, the standby current will increase due to current flow through the
CE# and RP# input stages.
#RP#
I
RESET/DEEP POWER DOWN: Provides Three-State control. Puts the device in
deep powerdown mode. Locks the Boot Block from program/erase.
When RP# is at logic high level and equals 6.5V maximum the Boot Block is locked
and cannot be programmed or erased.
When RP# = 11.4V minimum the Boot Block is unlocked and can be programmed
or erased.
When RP# is at a logic low level the Boot Block is locked, the deep powerdown
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When R P # transitions from logic low to logic high, the flash memory
enters the read-array mode.
OE#
I
OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. OE# is active low.
WE#
I
WRITE ENABLE: Controls writes to the Command Register and array blocks. WE #
is active low. Addresses and data are latched on the rising edge of the WE # pulse.
Vpp
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
Note: Vpp < VPPLMAX memory contents cannot be altered.
Vee
DEVICE POWER SUPPLY (5V ± 10%, 5V ± 5%)
GND
GROUND: For all internal circuitry.
NC
NO CONNECT: Pin may be driven or left floating.
DU
DON'T USE PIN: Pin should not be connected to anything.
4-226
I
I\)
(:)
I\)
CD
."
I\)
0
0
DQO-D~
_.
::l
c[
@J
IXJ
><
=E
0
:lJ
C
IXJ
'TI
~i
.
r:::
'"-<
CI)
!»
-I
N
CD
8YTE#
'TI
m
I
:!1C
N
0
0
tEl
><
CE#
:e0
..
WE#
m
'U
:lJ
CL
OE#
0
tEl
'<
RP#
c:
......
...
:eis:
J
-I
(f)
CI)
tEl
0'
C'I
..
iii"
IQ
1\1
3
C
m
Y-GATING/SENSING
AO - A16
:0:'
C
C
0
CI)
••
••
~g
CD~
",CD
"
1>",0
-Q
'"
u
0
~
~CD
'"9u
"'CD
>,..'" ,..'"
CD",
"'>-
I'"
I'"
«
;;:'"
12:
",,,,
>-u
,..0
CD...J
",CD
~=
«
++-
Vpp
(f)
Vee
:lJ
'U
-I
GND
N
-::E
0
0
Z
I\)
CI)
"TI
N
0
0
m
><
-I
.....
J
~m
N
CI)
"TI
290448-1 I
0
0
N
....
N
I\)
"'-I
m
><
-I
.....
J
m
28F200BX-T IB, 28F002B?C-T IB
2.1 28F200BX Memory Organization
2.1.1 BLOCKING
The 28F200BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F200BX is
a random read/write memory. only erasure is performed by block.
2.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RP# is not at 12V. The boot block can
be erased and written when RP# is held at 12V for
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address
locations of the boot block for the 28F200BX-T
and 28F200BX-B.
2.1.1.2 Parameter Block Operation
The 28F200BX has 2 parameter blocks (8 Kbytes
each). The parameter blocks are ,intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The pa~
rameter blocks can also be used to store additional
boot or main code. The parameter blocks however.
dQ not have the hardware write protection' feature
that the boot block has. The parameter blocks provide for more efficient memory utilization when dealing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for address locations of the parameter blocks for the
28F200BX-T and 28F200BX~B.
2.1.1.3 Main Block Operation
Two main blocks of memory exist on the 28F200BX .
(1 x 128 Kbyte block and 1 x 96-Kbyte block). See
the following section on Block Memory Map for the
address location of these blocks for the 28F200BX-T
and 28F200BX-B products.
2.1.2 BLOCK MEMORY MAP
Two versions, of the "28F200BX product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
. protocols for boot code location. The 28F200BX-T
memory map is inverted from the 28F200BX-B
memory map.
2.1.2.1 28F200BX·B Memory Map
The 28F200BX-B device has the 16-Kbyte boot
block located from OOOOOH to 01 FFFH to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH: In the
28F200BX-B the first 8-Kbyte parameter block resides in memory space from 02000H to 02FFFH.
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96-Kbyte main block resides in memory space from
04000H to OFFFFH. The 128-Kbyte main block resides in memory space from 10000H to 1FFFFH
(word locations). See Figure 7.
.(Word Addresses)
lFFFFH
12B-Kbyte MAIN BLOCK
10000H
OFFFFH
9B·Kbyte MAIN BLOCK
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
B-Kbyte PARAMETER BLOCK
B-Kbyte PARAMETER BLOCK
16·Kbyte BOOT BLOCK
OOOOOH
Figure 7. 28F200BX·B Memory Map
4-228
I
28F200BX-T IB, 28F002BX-T IB
2.1.2.2 28F200BX-T Memory Map
The 28F200BX·T device has the 16-Kbyte boot
block located from 1EOOOH to 1 FFFFH to accommodate those microprocessors that boot from the top
of the address map. In the 28F200BX-T the first
8-Kbyte parameter block resides in memory space
from 1DOOOH to 1DFFFH. The second 8-Kbyte parameter block resides in memory space from
1COOOH to 1CFFFH. The 96-Kbyte main block resides in memory space from 10000H to 1BFFFH.
The 128-Kbyte main block resides in memory space
from OOOOOH to OFFFFH as shown in Figure 8.
(Word Addresses)
1FFFFH
16·Kbyte BOOT BLOCK
1EOOOH
1DFFFH
WOOOH
1CFFFH
1COOOH
1BFFFH
8·Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
10000H
OFFFFH
128-Kbyte MAIN BLOCK
OOOOOH
Figure 8. 28F200BX-T Memory Map
I
4-229
"""
ro
c.:>
(0)
I\)
b
"TI
~
0
0
."
><
CD
I\)
0
.
CO
tD
0
0
DQO-D~
....-I
~
m
><
m
-<
-t
~tD
~
><
I\)
CD
"TI
0
0
I\)
m
I
"11
6'
...cCD
m
!D
."
01)
::D
CE#
"11
C
C
WE#
ID
N
OE#
><
-.
RP#
0
C
C
0
-t
ID
en
CD
C
'<
ID
0'
()
~
C
iii'
...
Ie
III
3
I
....-ItD
C
N
c:CD==
tD
m
An -
en
Y-GATINGjSENSING
A17
0
~
Vpp
'"g
u
'"g
~'" ~'"
~ffi iiiffi
,w .,,.
,w
.,,.
"'~
~
;;:
"'~
~
;;:
w'"
~g
",'"
'2
~~
."
w'"
>:g
-t
(5
"'--'
"''''
c!:,~
Z
N""
-,.
290448-19
_.
::J
c[
@
28F200BX-T IB, 28F002BX-T IB
3.1 28F002BX Memory Organization
3.1.1 BLOCKING
The 2SF002BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 2SF002BX is
a random read/write memory, only erasure is performed by block.
3.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot blocl( from being programmed
or erased when RP# is not at 12V. The boot block
can be erased and programmed when RP# is held
at 12V for the duration of the erase or program operation. This allows customers to change the boot
code when necessary while still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
2SF002BX-T and 2SF002BX-B.
3.1.1.3 Main Block Operation
Two main blocks of memory exist on the 2SF002BX
(1 x 12S-Kbyte block and 1 x 96-Kbyte block). See
the following section on Block Memory Map for
address location of these blocks for the
2SF002BX-T and 2SF002BX-B.
3.1.2 BLOCK MEMORY MAP
Two versions of the 2SF002BX product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 2SF002BX-T
memory map is inverted from the 2SF002BX-B
memory map.
3.1.2.1 28F002BX-B Memory Map
The 2SF002BX-B device has the 16-Kbyte boot
block located from OOOOOH to03FFFH to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH. In the
2SF002BX-B the first S-Kbyte parameter block resides in memory from 04000H to 05FFFH. The second S-Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96-Kbyte main
block resides in memory space from OSOOOH to
1FFFFH. The 12S-Kbyte main block resides in memory space from 20000H to 3FFFFH. See Figure 10.
3FFFFH
3.1.1.2 Parameter Block Operation
The 2SF002BX has 2 parameter blocks (S Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The parameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map section for address locations of the parameter blocks
for the 2SF002BX-T and 2SF002BX-B.
12a·Kbyte MAIN BLOCK
20000H
lFFFFH
9S·Kbyte MAIN BLOCK
OBOOOH
07FFFH
OSOOOH
a·Kbyte PARAMETER BLOCK
05FFFH
04000H
03FFFH
a.KbY1e PARAMETER BLOCK
lS·Kbyte BOOT BLOCK
OOOOOH
Figure 10. 28F002BX-B Memory Map
I
4-231
28F200BX-T IB, 28F002BX-TIB
3.1.2.2 28F002BX-T Memory Map
The 28F002BX·T device has the 16-Kbyte boot
block located from 3COOOH to 3FFFFH to accommodate those microprocessors that boot from the
top of the address map. In the 28F002BX-T the first
8-Kbyte parmeter block resides in memory space
from 3AOOOH to 3BFFFH. The second 8-Kbyte parameter block resides in memory space from
38000H to 39FFFH. The 96-Kbyte main block resides in memory space from 20000H to 37FFFH.
The 128-Kbyte main block resides in memory space
from OOOOOH to 1FFFFH.
3FFFFH
16-Kbyte BOOT BLOCK
3COOOH
3BFFFH
3AOOOH
39FFFH
38000H
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
37FFFH
96-Kbyte MAIN BLOCK
20000H
1FFFFH
128-Kbyte MAIN BLOCK
OOOOOH
Figure 11. 28F002BX-T Memory Map
4.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION
Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The 2-Mbit flash
4-232
family utilizes a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations.
The CUI allows for 100% TTL-level control inputs,
fixed power supplies during erasure and programming, and maximum EPROM compatibility.
In the absence of high voltage on the Vpp pin, the
2-Mbit boot block flash family will only successfully
execute the following commands: Read Array, Read
Status Register, Clear Status Register and Intelligent Identifier mode. The device provides standard
EPROM read, standby and output disable operations. Manufacturer Identification and Device Identification data can be accessed through the CUI or
through the standard EPROM A9 high voltage access (VIO) for PROM programming equipment.
The same EPROM read, standby and output disable
functions are available when high voltage is applied
to the Vpp pin. In addition, high voltage on Vpp allows write and erase of the device. All functions associated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.
The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
device. The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
WE# interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.
.
4.1 28F200BX Bus Operations
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
I
28F200BX-T IB, 28F002BX-T IB
Table 1. Bus Operations for WORD-WIDE Mode (BYTE # = VI H)
Mode
Read
Notes
RP#
CE#
OE#
WE#
Ag
Ao
Vpp
1,2,3
VIH
VIL
VIL
VIH
X
X
X
DOUT
X
X
HighZ
000-15
Output Disable
VIH
VIL
VIH
VIH
X
Standby
VIH
VIH
X
X
X
X
X
HighZ
9
VIL
X
X
X
X
X
X
HighZ
4
VIH
VIL
VIL
VIH
VID
VIL
X
0089H
2274H
2275H
DIN
Deep Power-Down
Intelligent Identifier (Mfr)
4,5
VIH
VIL
VIL
VIH
VID
VIH
X
6,7,8
VIH
VIL
VIH
VIL
X
X
X
Intelligent Identifier (Device)
Write
Table 2. Bus Operations for BYTE-WIDE Mode (BYTE # = VIL>
Mode
Read
Notes
RP#
CE#
OE#
WE#
Ag
Ao
A-1
Vpp
000-7
008-14
1,2,3
VIH
VIL
VIL
VIH
X
X
X
X
DOUT
HighZ
X
X
X
X
High Z
HighZ
Output Disable
Standby
Deep Power-Down
Intelligent Identifier (Mfr)
Intelligent Identifier
(Device)
Write
VIH
VIL
VIH
VIH
VIH
VIH
X
X
X
X
X
X
HighZ
HighZ
9
VIL
X
X
X
X
X
X
X
HighZ
HighZ
4
VIH
VIL
VIL
VIH
VID
VIL
X
X
89H
HighZ
X
74H
75H
HighZ
X
DIN
HighZ
4,5
VIH
VIL
VIL
VIH
VID
VIH
X
6,7;8
VIH
VIL
VIH
VIL
X
X
X
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
g.
Refer to DC Characteristics.
X can be VIL or VIH for control pins and addresses, VPPL or VPPH for Vpp.
See DC characteristics for VpPL, VpPH, VHH. VIO voltages.
Manufacturer and Device codes may also be accessed via a CUI write sequence. A1-A17 = X.
Device 10 = 2274H for 28F200BX-T and 2275H for 28F200BX·B.
Refer to Table 4 for valid DIN during a write operation.
Command writes for Block Erase or Word/Byte Write are only executed when Vpp = VPPH.
To write or erase the boot block, hold RP# at VHH.
RP# must be at GND ±O.2V to meet the 1.2 /J-A maximum deep power-down current.
I
4-233
28F200BX-T IB, 28F002BX-T IB
4.2 28F002BX Bus Operations
Table 3. Bus Operations
Mode
Read
Notes
RP#
CE#
OE#
WE#
A9
Ao
VPI!
DQO-7
1,2,3
VIH
VIL
VIL
VIH
X
X
X
DOUT
Output Disable
VIH
VIL
VIH
VIH
X
X
X
HighZ
Standby
VIH
VIH
X
X
X
X
X
HighZ
Deep Power-Down
9
VIL
X
X
X
X
X
X
HighZ
Intelligent Identifier (Mfr)
4
VIH
VIL
VIL
VIH
VID
VIL
X
89H
4,5
VIH
VIL
VIL
VIH
VID
VIH
X
7CH
7DH
6,7,8
VIH
VIL
VIH
VIL
X
X
X
DIN
Intelligent Identifier (Device)
Write
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VpPL or VPPH for Vpp.
3. See DC characteristics for VPPL, VpPH, VHH, VIO voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. Al-A16 = X.
5. Device ID = 7CH for 28F002BX-T and 7DH for 28F002BX-B.
6. Refer to Table 4 for valid DIN during a write operation.
7. Command writes for Block Erase or byte program are only executed when Vpp = VPPH.
8. Program or erase the Boot block by holding RP# at VHH.
g. RP# must be at GND ±O.2V to meet the 1.2 /LA maximum deep power-down current.
4.3 Read Operations
(DQ[0:15] or DQ[0:7]) are tri-stated. Data input is
then controlled by WE # .
The 2-Mbit boot block flash family has three user
read modes; Array, Intelligent Identifier, and Status
Register. Status Register read mode will be dis'cussed in detail in the "Write Operations" section.
4.3.1.2 Input Control
During power-up conditions (VCC supply ramping), it
takes a maximum of 600 ns from when VCC is at
4.5V minimum to valid data on the outputs.
With WE # at logic-high level (VIH), input to the device is disabled. Data Input!Output pins (DQ-[0:15]
or DQ[0:7]) are controlled by OE#.
4.3.2 INTELLIGENT IDENTIFIERS
4.3.1 READ ARRAY
If the memory is not in the Read Array mode, it is
necessary to write the appropriate read mode command to the CUI. The 2-Mbit boot block flash family
has three control functions, all of which must be logically active, to obtain data at the outputs. Chip-Enable CE# is the device selection control. PowerDown RP# is the device power control. Output-Enable OE# is the DATA INPUTlOUTPUT (DQ[0:15]
or DQ[0:7]) direction control and when active is
used to drive data from the selected memory on to
the 1/0 bus.
28F200BX Products
The manufacturer and device codes are read via the
CUI or by taking the Ag pin to 12V. Writing 90H to
the CUI places the device into Intelligent Identifier
read mode. A read of location OOOOOH outputs the
manufacturer's identification code, 0089H, and location 00001H outputs the device code; 2274H for
28F200BX-T, 2275H for 28F200BX-B. When
BYTE# is at a logic low only the lower byte of the
above signatures is read and DQ151 A-1 is a "don't
care" during Intelligent Identifier mode. A read array
command must be written to the CUI to return to the
read array mode.
4.3.1.1 Output Control
With OE# at logic-high level (VIH), the output from
the device is dis~bled and data input! output pins
4-234
I
28F200BX-T IB, 28F002BX-T IB
28F002BX Products
4.4.1 BOOT BLOCK WRITE OPERATIONS
The manufacturer and device codes are also read
via the CUI or by taking the AS pin to 12V. Writing
SOH to the CUI places the device into Intelligent
Identifier read mode. A read of location OOOOOH outputs the manufacturer's identification code, 8SH,
and location 00001 H outputs the device code; 7CH
for 28F002BX-T, 7DH for 28F002BX-B.
In the case of Boot Block modifications (write and
erase), RP# is set to VHH = 12V typically, in addition to Vpp at high voltage. However, if RP# is not at
VHH when a program or erase operation of the boot
block is attempted, the corresponding status register
bit (Bit 4 for Program and Bit 5 for Erase, refer to
Table 5 for Status Register Definitions) is set to indicate the failure to complete the operation.
4.4 Write Operations
Commands are written to the CUI using standard microprocessor write timings. The CUI serves as the
interface between the microprocessor and the internal chip operation. The CUI can decipher Read Array, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and' Program commands. In the event of a read command, the CUI
simply points the read path at either the array, the
intelligent identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state machine that a write or erase has been requested. During a program cycle, the Write State Machine will
control the program sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Machine has completed its
task, it will allow the CUI to respond to its full command set. The CUI will stay in the current command
state until the microprocessor issues another command.
The CUI will successfully initiate an erase or write
operation only when Vpp is within its voltage range.
Depending upon the application, the system designer may choose to make the Vpp power supply
switchable, available only when memory updates
are desired. The system designer can also choose
to "hard-wire" Vpp to 12V. The 2 Mbit boot,block
flash family is designed to accommodate either design practice. It is recommended that RP# be tied to
logical Reset for data protection during unstable
CPU reset function as described in the "Product
Family Overview" section.
I
4.4.2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a "1", which will also allow t,he CUI to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.
4.4.2.1 Command Set
Command
Codes
00
10
20
40
50
70
SO
BO
DO
FF
Device Mode
Invalid/Reserved
Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
Erase Resume/Erase Confirm
Read Array
4.4.2.2 Command Function Descriptions
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the 2-Mbit
boot block flash family commands.
4-235
28F200BX-T/B,28F002BX-T/B
Table 4. Command Definitions
Command
Bus
Notes
Cycles
Req'd
8
First Bus Cycle
Second Bus Cycle
Operation Address Data Operation Address Data
Read Array/Reset
1
1
Write
X
FFH
Intelligent Identifier
3
2,4
Write
X
90H
Read
IA
110
3
Write
X
70H
Read
X
SRD
Write
X
50H
Read Status Register
2
Clear Status Register
1
Erase Setup/Erase Confirm
2
5
Write
BA
20H
Write
SA
DOH
Word/Byte Write Setup/Write
2
6, 7
Write
WA
40H
Write
WA
WD
Write
X
BOH
Write
X
DOH
Write
WA
10H
Write
WA
WD
Erase Suspend/Erase Resume
2
Alternate Word/Byte Write Setup/Write
2
6, 7
NOTES:
1. Bus operations are defined in Tables 1, 2, 3.
2. IA = Identifier Address: OOH for manufacturer code, 01 H for device code.
3. SRD = Data read from Status Register.
4. liD = Intelligent Identifier Data.
Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.
5. BA = Address within the block being "erased.
6. PA = Address to be programmed.
PD = Data to be programmed at location PA.
7. Either 40H or 10H command is valid.
B. When writing commands to the device, the upper data bus [DOB-DOI5] = X (28F200BX-only) which is either Vee or
Vss "to avoid burning additional current.
Invalid/Reserved
Read Status Register (70H)
These are unassigned commands. It is not recommended that the customer use any command other
than the valid commands specified above. Intel reserves the right to redefine these codes for future
functions.
This is one of the two commands that is executable
while the state machine is operating. After this command is written, a read of the device will output the
contents of the status register, regardless of the address presented to the device.
Read Array (FFH)
The device automatically enters this mode after program or erase has completed.
This single write command points the read path at
the array. If the host CPU performs a CE#lOE#
controlled read immediately following a two-write sequence that started the WSM, then the device will
output status register contents. If the Read Array ,
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset to. Read Array
after Program Setup.
Intellgent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addr~sses 0 and 1 can
be read (only address AO is used in this mode, all
other address inputs are ignored).
4-236
Clear Status Register (SOH)
The WSM can only set)he Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchronization. The WSM does not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after programming the string. Thus, if any errors exist while
programming the string, the status register will return .
the accumulated error status.
I
28F200BX-T/B,28F002BX-T/B
Program Setup (40H or 10H)
This command simply sets the CUI into a state such
that the next write will load the address and data
registers. Either 40H or 10H can be used for Program Setup. Both commands are included to accommodate efforts to achieve an industry standard
command code set.
Program
The second write after the program setup command,
will latch addresses and data. Also, the CUI initiates
the WSM to begin execution of the program algorithm. While the WSM finishes the algorithm, the device will output Status Register contents. Note that
the WSM cannot be suspended during programming.
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command.
No other action is taken. If the next command is not
an Erase Confirm command then the CUI will set
both the Program Status and Erase Status bits of the
Status Register to a "1", place the device into the
Read Status Register state, and wait for another
command.
Erase Confirm (DOH)
If the previous command was an Erase Setup command, then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status Register and
Erase Suspend commands. While the WSM is executing, the device will output Status Register data
when OE# is toggled low. Status Register data can
only be updated by toggling either OE # or CE # low.
Erase Suspend (BOH)
This command only has meaning while the WSM is
executing an Erase operation, and therefore will only
be responded to during an erase operation. After
this command has been executed, the CUI will set
an output that directs the WSM to suspend Erase
operations, and then return to responding to only
Read Status Register or to the Erase Resume commands. Once the WSM has reached the Suspend
state, it will set an output into the CUI which allows
the CUI to respond to the Read Array, Read Status
Register, and Erase Resume commands. In this
mode, the CUI will not respond to any other commands. The WSM will also set the WSM Status bit to
a "1 ". The WSM will continue to run, idling in the
SUSPEND state, regardless of the state of all input
I
control pins, with the exclusion of RP#. RP# will
immediately shut down the WSM and the remainder
of the chip. During a suspend operation, the data
and address latches will remain closed, but the address pads are able to drive the address into the
read path.
Erase Resume (DOH)
This command will cause the CUI to clear the Suspend state and set the WSM Status bit to a "0", but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.
4.4.3 STATUS REGISTER
The 2-Mbit boot block flash family contains a status
register which may be read to determine when a program or erase operation is complete, and whether
that operation completed successfully. The status
register may be read at any time by writing the Read
Status command to the CUI. After writing this command, all subsequent Read operations output data
from the status register until another command is
written to the CUI. A Read Array command must be
written to the CUI to return to the Read Array mode.
The status register bits are output on 00[0:7]
whether the device is in the byte-wide (x8) or wordwide (x16) mode for the 28F200BX. In the word-wide
mode the upper byte, 00[8:15] is set to OOH during
a Read Status command. In the byte-wide mode,
00[8:14] are tri-stated and 0015/ A -1 retains the
low order address function.
It should be noted that the contents of the status
register are latched on the falling edge of OE# or
CE# whichever occurs last in the read cycle. This
prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register. CE# or OE# must be toggled
with each subsequent status read, or the completion
of a program or erase operation will not be evident.
The Status Register is the interface between the microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate
the status of the WSM, and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation. The WSM sets
status bits "Three" through "Seven" and clears bits
"Six" and "Seven", but cannot clear status bits
"Three" through "Five". These bits can only be
cleared by the controlling CPU through the use of
the Clear Status Register command.
4-237
28F200BX·T IB, 28F002BX·T IB
4.4.3.1 Status Register Bit Definition
Table 5. Status Register Definitions
I
WSMS lESS
7
6
ES
PS
vpPs
4
3
I
R
2
R
R
o
NOTES:
SR.? = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
Write State Machine Status bit must first be checked to
determine byte/word program or block erase completion,
before the Program or Erase Status bits are checked for
success.
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
o = Erase in Progress/Completed
When Erase Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to "1". ESS bit remains set to "1" until an Erase Resume command is issued.
SR.5 = ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Erase
When this bit is set to '''1 ". WSM has applied the maximum number of erase pulses to the block and is still unable to successfully perform an erase verify.
SR.4 = PROGRAM STATUS
1 = Error in Byte/Word Program
o = Successful Byte/Word Program
When this bit is set to "1", WSM has attempted but failed
to Program a byte or word.
SR.3 = Vpp STATUS
1 = Vpp Low Detect; Operation Abort
0= Vpp OK
The Vpp Status bit, unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM in~
terrogates the Vpp level only after the byte write or block
erase command sequences have been entered and informs the system if Vpp has not been switched on. The
Vpp Status bit is not guaranteed to report accurate feedback between VpPL and VpPH.
SR.2-SR.O
MENTS
These bits are reserved for future use and should be
masked out when polling the Status Register.
RESERVED FOR. FUTURE ENHANCE·
4.4.3.2 Clearing the Status Register
4.4.4 PROGRAM MODE
Certain bits in the status register are set by the write
state machine, and can only be reset by the system
software. These bits can indicate various failure conditions. By allowing the system software to cOntrol
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in sequence). The status register may then be read to
determine if an error occurred during that program·
ming or erasure series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear .Status Register
command is written to the CUI. Then, any other
command may be issued to the CUI. Note again that
before a read cycle can be initiated, a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array,
status register, or Intelligent Identifier.
Program is executed by a two-write sequence. The
Program Setup command is written to the CUI followed by a second write which specifies the address
and data to be programmed. The write state machine will execute a sequence of internally timed
events to:
1. Program the desired bits of the addressed memory word (byte), and
2. Verify that the desired bits are sufficiently programmed
Programming of the memory results in specific bits
within a byte or word being changed to a "0".
If the user attempts to program "1 "s, there will be no
change of the memory cell content and no error occurs.
Similar to erasure, the status register indicates
whether programming is complete. While the program sequence is executing, bit 7 of the status register is a "0". The status register can be polled by
4-238
I
28F200BX-T IB, 28F002BX-T IB
toggling either CE# or OE# to determine when the
program sequence is complete. Only the Read
Status Register command is valid while program·
ming is active.
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, Bit 4 of the status regis·
ter is set to a "1" to indicate a Program Failure. If Bit
3 is set then Vpp was not within acceptable limits,
and the WSM will not execute the programming se·
quence.
The status register should be cleared before at·
tempting the next operation. Any CUI instruction Can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot be ac·
complished until the CUI is given the appropriate
command. A Read Array command must first be giv·
en before memory contents can be read.
Figure 12 shows a system software flowchart for de·
vice byte programming operation. Figure 13 shows a
similar flowchart for device word programming oper·
ation (28F200BX·only).
4.4.5 ERASE MODIE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI, along with the addresses, A[12:16] for the
28F200BX or A[12:17] for the 28F002BX, identifying
the block to be erased. These addresses are latched
internally when the Erase Confirm command is is·
sued. Block erasure results in all bits within the block
being set to "1".
The WSM will execute a sequence of internally
timed events to:
1. Program all bits within the block
2. Verify that all bits within the block are sufficiently
programmed
3. Erase all bits within the block and
4. Verify that all bits within the block are sufficiently
erased
While the erase sequence is executing, Bit 7 of the
status register is a "0".
When the status register indicates that erasure is
complete, the'status bits, which indicate whether the
erase operation was successful, should be checked.
If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a "1" to indicate an
Erase Failure. If Vpp was not within acceptable limits
after the Erase Confirm command is issued, the
WSM will not execute an erase sequence; instead,
Bit 5 of the status register is set to a "1" to indicate
I
an Erase Failure, and Bit 3 is set to a "1" to identify
that Vpp supply voltage was not within acceptable
limits.
The status register should be cleared before at·
tempting the next operation. Any' CUI instruction can
follow after erasure is completed; however, it must
be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be ac·
complished until the CUI is given the appropriate
command. A Read Array command must first be giv·
en before memory contents can be read.
Figure 14 shows a system software flowchart for
Block Erase operation.
4.4.5.1 Suspending and Resuming Erase
Since an erase operation typically requires 1 to 3
seconds to complete, an Erase Suspend command
is provided. This allows erase·sequence interruption
in order to read data from another block of the mem·
ory. Once the erase sequence is started, writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase se·
quence at a predetermined point in the erase algo·
rithm. The status register must be read to determine
when the erase operation has been suspended.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
Figure 15 shows a system software flowchart detail·
ing the operation.
During Erase Suspend mode, the chip can go into a
pseudo·standby mode by taking CE# to VIH and the
active current is now a maximum of 10 mA. If the
chip is enabled while in this mode by taking CE# to
VIL, the Erase Resume command can be issued to
resume the erase operation.
Upon completion of reads from any block other than
the block being erased, the Erase Resume com·
mand must be issued. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of erase, the status register must be
read, cleared, and the next instruction issued in or·
der to continue.
4.4.6 EXTENDED CYCLING
Intel has designed extended cycling capability into
its ETOX III flash memory technology. The 2·Mbit
boot block flash family is designed for 100,000 pro·
gram/erase cycles on each of the five blocks. The
combination of low electric fields, clean oxide pro·
cessing and minimized oxide area per memory cell
subjected to the tunneling electric field, results in
very high cycling capability.
4·239
28F200BX-T/B,28F002BX-T/B
Bus
Operation
Write
Write
Command
Comments
Setup
Program
Data = 40H
Address = Byte to be
programmed
Program
. Data to be programmed
Address = Byte to be
programmed
I
Read
Status Register Data.
ToggleOE# orCE# to update
Status Register
Standby
Check SR,7
1 = Ready, 0
=
Busy
Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
290448-6
Full Status Check Procedure
Bus
Operation
Vpp Range
Error
Byte Program
Error
Command
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
CheckSR.4
1 = Byte Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290448-7
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 12. Automated Byte Programming Flowchart
4-240
I
28F200BX-T IB, 28F002BX-T IB
Bus
Operation
Command
Comments
Write
Setup
Program
Data = 40H
Address = Word to be
programmed
Write
Program
Data to be programmed
Address = Word to be
programmed
Read
Status Register Data.
Toggle OE# or CE# to update
Status Register
Standby
Check SR.7
1 = Ready, 0
=
Busy
Repeat for subsequent words.
Full status check can be done after each word or after a
sequence of words.
290448-8
Write FFH after the last word programming operation to
reset the device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Vpp Range
Error
Byte Program
Error
Command
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
CheckSR.4
1 = Word Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290448-9
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
"
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 13. Automated Word Programming Flowchart
I
4-241
28F200BX-T/B,28F002BX-T/B
Bus
Operation
Command
Comments
Write
Setup
Erase
Data = 20H
Address = Within block to be
erased
Write
Erase
Data = DOH
Address = Within block to be
erased
Read
Status Register Data.
ToggleOE# orCE# toupdata
Status Register
Standby
CheckSR.7'
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.
290448-10
Write FFH after the last block erase operation to reset the
device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Vpp Range
Error
Command Sequence
- Error
Block Erase
Error
Command
Comments
Standby
CheckSR.3
1 = Vpp low Detect
Standby
Check SR.4,5
Both 1 = Command Sequence
Error
Standby
CheckSR.5
1 = Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
290448-11
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error Is detected, ciear the Status Register before
attempting retry or other error recovery.
Figure 14. Automated Block Erase Flowchart
4-242
I
intel®
28F200BX-T/B,28FOO2BX-T/B
Bus
Operation
Write
Command
Erase
Suspend
Comments
Data
= BOH
Read
Status Register Data.
Toggle OE# or CE# to
update Status Register
Standby
CheckSR.7
1 = Ready
Standby
CheckSR.6
1 = Suspended
Write
Read Array
Read
Write
Data
= FFH
Read array data from block
other than that being
erased.
.
Erase Resume
Data = DOH
290448-12
Figure 15. Erase Suspend/Resume Flowchart
4.5 Power Consumption
4.5.1 ACTIVE POWER
With CE # at a logic-low level and RP # at a logichigh level, the device is placed in the active mode.
The device Icc current is a maximum of 60 mA at
10 MHz with TTL input signals.
4.5.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low power feature during active mode of operation. The 2-Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the device to put itself into a low current state when it is
not being accessed. After data is read from the
memory array, PRC logic controls the device's power consumption by entering the APS mode where
I
maximum Icc current is 3 mA and typical Icc current
is 1 mAo The device stays in this static state with
outputs valid until a new location is read.
4.5.3 STANDBY POWER
With CE# at a logic-high level (VIH), and the CUI in
read mode, the memory is placed in standby mode
where the maximum Icc standby current is 100 /LA
with CMOS input signals. The standby operation disables much of the device's circuitry and substantially
reduces device power consumption. The outputs
(00[0:15] or 00[0:7]) are placed in a high-impedance state independent of the status of the OE#
signal. When the 2-Mbit boot block flash family is
deselected during erase or program functions, the
devices will continue to perform the erase or program function and consume program or erase active
power until program or erase is completed.
4-243
28F200BX-T/B,28F002BX-T/B
4.5.4 RESETIDEEP POWER-DOWN
The 2·Mbit boot block flash family supports a typical
lee of 0.2 p.A in deep power·down mode. One of the
target markets for these devices is in portable equip·
ment where the power consumption of the machine
is of prime importance. The 2-Mbit boot block flash
family has a RP# pin which places the device in the
deep power-down mode. When RP# is at a logiclow (GND ± 0.2V), all circuits are turned off and the
device typically draws 0.2 p.A of Vee current.
During read modes, the RP# pin going low deselects the memory and places the output drivers in a
high impedance state. Recovery from the deep power-down state, requires a maximum of 300 ns to access valid data (tpHQV).
During erase or program modes, RP# low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
corrupted by the RP# function. As in the read mode
above, all internal circuitry is turned off to achieve
the 0.2 p.A current level.
RP# transitions to VIL or turning power off to the
device will clear the status register.
This use of RP# during system reset is important
with automated write/erase devices. When the system comes out of reset it expects to read from the
flash memory. Automated flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel's
Flash Memories allow proper CPU initialization following a system reset through the use of the RP#
input. In this application RP# is controlled by the
same RESET# signal that resets the system CPU.
4.6 Power-Up Operation
The 2-Mbit boot .block flash family is designed to
offer protection against accidental block erasure or
programming during power transitions. Upon power·
up the 2-Mbit boot block flash family is indifferent as
to which power supply, Vpp or Vee, powers-up first.
Power suppy sequencing is not required.
The 2-Mbit boot block flash family ensures the CUI is
reset to the read mode on power-up.
In addition, on power-up the user must either drop
CE# low or present a new address to ensure valid
data at the outputs.
A system designer must guard against spurious
writes for Vee voltages above VLKO when Vpp is
4-244
active. Since both WE # and CE # must be low for a
command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides
an added level of protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. Finally, the device is disabled until RP# is brought to VIH,
regardless of the state of its control inputs. This feature provides yet another level of memory protection.
4.7 Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling methods. System
designers are interested in 3 supply current issues:
• Standby current levels (Ices)
• Active current levels (leeR)
• Transient peaks produced by falling and rising
edges of CE # .
Transient current magnitudes depend on the device
outputs' capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 p.F ceramic capacitor
connected between each Vee and GND, and between its Vpp and GND. These high frequency, lowinherent inductance capacitors should be placed as
close as possible to the package leads.
4.7.1 Vpp TRACE ON PRINTED CIRCUIT
BOARDS
Writing to flash memories while they reside in the
target system, requires special consideration of the
Vpp power supply trace by the printed circuit board
designer. The Vpp pin supplies the flash memory
cell's current for programming and erasing. One
should use similar trace widths and layout considerations given to the Vee power supply trace. Adequate Vpp supply traces and decoupling will decrease spikes and overshoots.
4.7.2 Vee, Vpp AND RP# TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by Vpp or CE # transitions or WSM actions. Its state upon power-up, after exit from deep power-down mode or after Vee
transitions below VLKO (Lockout voltage), is Read
Array mode.
After any word/byte write or block erase operation is
complete and even after Vpp transitions down to
VPPL, the CUI must be reset to Read Array mode via
the Read Array command when accesses to the
flash memory are desired.
I
28F200BX·T IB, 28F002BX·T IB
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Commercial Operating Temp'erature
During Read .................... O·C to 70·C(1)
During Block Erase
and Word/Byte Write ............... O·C to 70·C
Temperature Under Bias ....... -1 O·C to + 80·C
Extended Operating Temperature
During Read ................. - 40·C to
During Block Erase
and Word/Byte Write ......... - 40·C to
Temperature Under Bias ....... -40·C to
Storage Temperature
• WARNING: StreSSing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 85·C
+ 85·C
+ 85·C
.......... -65·C to + 125·C
Voltage on Any Pin
(except Vee, Vpp, A9 and RP#)
with Respect to GND ........ - 2.0V to
+ 7.0V(2)
Voltage on Pin RP# or Pin A9
with Respect to GND ..... - 2.0V to
+ 13.5V(2, 3)
Vpp Program Voltage with Respect
to GND during Block Erase
and Word/Byte Write ..... - 2.0V to
+ 14.0V(2, 3)
Vee Supply Voltage
with Respect to GND ........ - 2.0V to
+ 7.0V(2)
Output Short Circuit Current .•..........• 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -0.5V on input/output pins. During transitions, this level may undershoot .to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee + 2.0V
for periods < 20 ns.
3. Maximum De voltage on Vpp may overshoot to +14.0V for periods <20 ns. Maximum De voltage on RP# or Ag may
overshoot to 13.5V for periods < 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. 10% Vee specifications reference the 28F200BX-60/28F002BX-60 in their standard test configuration, and the
28F200BX-80/28F002BX-80.
6. 5% Vee specifications reference the 28F200BX·60/28F002BX-60 in their high speed test configuration.
OPERATING CONDITIONS
Symbol
TA
Parameter
Notes
Operating Temperature
Min
Max
Units
0
70
·C
Vee
Vee Supply Voltage (10%)
5
4.50
5.50
V
Vee
Vee Supply Voltage (5%)
6
4.75
5.25
V
DC CHARACTERISTICS
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
III
Input Load Current
1
±1.0
/J- A
Vee = Vee Max
VIN == Vee or GND
ILO
Output Leakage Current
1
±10
/J- A
Vee = Vee Max
VOUT = Vee or GND
I
4-245
28F200BX-T/B,28F002BX-T/B
DC CHARACTERISTICS
Symbol
Ices
(Continued)
Parameter
Vee Standby Current
Notes Min Typ
1,3
Max
Unit
1.5
rnA
Vee = Vee Max
CE# = RP# = VIH
100
p.A
Vee = Vee Max
CE# = RP# = Vee ±0.2V
28F200BX:
BYTE# = Vee ±0.2VorGND
p.A
rnA
IceD
Vee Deep Power-Down Current
1
0.20
1.2
leeR
Vee Read Current for
28F200BX Word-Wide and
Byte-Wide Mode and
28F002BX Byte-Wide Mode
1,5,
6, 10
20
55
20
60
Vee Word Byte Write Current
1,4
IeeE
Vee Block Erase Current
1,4
leeES
Vee Erase Suspend Current
1,2
leew
65
30
5
10
Test Condition
= GND ±0.2V
= Vee Max, CE# = GND
f(max) = 10 MHz, f(typ) = 5 MHz
lOUT = 0 rnA, CMOS Inputs
rnA Vee = Vee Max, CE# = GND
f(max) = 10 MHz, f(typ) = 5 MHz
lOUT = 0 rnA, TTL Inputs
rnA
rnA
rnA
RP#
Vee
Word Write in Progress
Block Erase in Progress
Block Erase Suspended,
CE# = VIH
IpPR
Vpp Read Current
1
200
Ippw
Vpp Word Write Current
1,4
40
p.A
p.A
p.A
rnA
Ippw
Vpp Byte Write Current
1,4
30
rnA
Vpp = VPPH
Byte Write in Progress
IpPE
Vpp Block Erase Current
1,4
30
rnA
Vpp = VPPH
Block Erase in Progress
IpPES
Vpp Erase Suspend Current
1
200
p.A
Vpp = VPPH
Block Erase Suspended
IRP#
RP# Boot Block Unlock Current
1,4
500
110
1,4
VIO
Ag Intelligent Identifier Current
Ag Intelligent Identifier Voltage
p.A RP# = VHH
p.A Ag = VIO
VIL
IpPS
Vpp Standby Current
1
±t5
Ippo
Vpp Deep Power-Down Current
1
5.0
500
11.5
13.0
Input Low Voltage
-0.5
0.8
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
4-246
Vee
+ 0.5
0.45
Vpp
RP#
s:
Vee
=
GND ±0.2V RP#
Vpp> Vee
Vpp = VpPH
Word Write in Progress
V
V
V
V
Vee = Vee Min
IOL = 5.8 rnA
I
28F200BX·T IB, 28F002BX·T IB
DC CHARACTERISTICS
Symbol
(Continued)
Parameter
VOH1
Output High Voltage (TIL)
VOH2
Output High Voltage (CMOS)
Notes
Min
Typ Max Unit
Test Condition
2.4
V
Vee ~ Vee Min
IOH = -2.5 mA
0.85 Vee
V
Vee = Vee Min
IOH = -2.5 mA
Vee = Vee Min
IOH = -100 /-LA
Vee - 0.4
VpPL
Vpp during Normal Operations
VPPH
Vpp during Erase/Write Operations
7
11.4
12.0 12.6
V
VpPH
Vpp during Erase/Write Operations
8
10.8
12.0 13.2
V
VLKO
Vee Erase/Write Lock Voltage
2.0
VHH
RP# Unlock Voltage
11.5
13.0
V
3
0.0
V
6.5
V
Boot Block Write/Erase
EXTENDED TEMPERATURE OPERATING CONDITIONS
Symbol
Parameter
TA
Operating Temperature
Vee
Vee Supply Voltage (10%)
Notes
5
Min
Max
Units
-40
+85
·C
4.50.
5.50
V
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION
Symbol
Parameter
Notes Min Typ
Max
Unit
Test Condition
III
Input Load Current
1
±1.0
/-LA
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage Current
1
±10
/-LA
Vee = Vee Max
VOUT = Vee or GND
Ices
Vee Standby Current
1,3
1.5
mA
Vee = Vee Max
CE# = RP# = VIH
100
/-LA
Vee = Vee Max
CE# = RP# = Vee ±0.2V
28F200BX:
BYTE# = Vee ±0.2Vor GND
IceD
Vee Deep Power-Down Current
leeR
Vee Read Current for
28F200BX Word-Wide and
Byte-Wide Mode and
28F002BX Byte-Wide Mode
1
1,5,
6
0.20
=
20
/-LA
RP#
60
mA
Vee = Vee Max, CE# = GND
f = 10 MHz, lOUT = 0 mA
CMOS Inputs
GND ±0.2V
65
mA
Vee = Vee Max, CE# = VIL
f = 10 MHz,lOUT = 0 mA
TTL Inputs
4-247
28F200BX-T/B,28F002BX-T/B
DC CHARACTERISTICS: EXTENDED TEMPERATURE OPERATION (Continued)
Symbol
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
Iccw
Vcc Word Byte Write Current
1
70
mA Word Write in Progress
ICCE
Vcc Block Erase Current
1
40
mA Block Erase in Progress
ICCES
Vcc Erase Suspend Current
10
rnA Block Erase Suspended
CE# = VIH
1,2
5
Ipps
Vpp Standby Current
1
±15
p.A Vpp
IpPO
Vpp Deep Power-Down Current
1
5.0
p.A RP#
S;
Vee
=
GND ±0.2V
IpPR
Vpp Read Current
1
200
p.A Vpp> Vec
Ippw
Vpp Word Write Current
1,4
40
mA Vpp = VPPH
Word Write in Progress
Ippw
Vpp Byte Write Current
1,4
30
mA Vpp = VpPH
Byte Write in Progress
IpPE
Vpp Block Erase Current
1,4
30
mA Vpp = VpPH
Block Erase in Progress
IpPES
Vpp Erase Suspend Current
1
200
p.A Vpp == VPPH
Block Erase Suspended
1,4
500
p.A RP# = VHH
500
p.A A9
IRP#
RP# Boot Block Unlock Current
110
A9 Intelligent Identifier Current
1
VIO
A9 Intelligent Identifier Voltage
11.5
13.0
V
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0
VOL
Output LowVoltage
VOH1
Output High Voltage (TTL)
VOH2
Output High Voltage (CMOS)
Vce
+ 0.5
V
Vec = Vce Min
IOL= .5.8mA
2.4
V
Vee = Vee Min
IOH = -2.5 mA
0.85Vec
V
Vee = Vee Min
IOH = -2.5 mA
Vee - 0.4
VPPL
Vpp during Normal Operations
VPPH
Vpp during Erase/Write Operations
7
11.4
VpPH
Vpp during Erase/Write Operations
8
10.8
VLKO
Vce Erase/Write Lock Voltage
2.0
VHH
RP# Unlock Voltage
11.5
4-248
VIO
V
0.45
3
=
Vec = Vee Min
IOH = -100 p.A
0.0
6.5
V
12.0
12.6
V
12.0
13.2
V
13.0
V
V
Boot Block Write/Erase
I
28F200BX·T /B, 28F002BX·T /B
CAPACITANCE(4,9)
Symbol
TA = 25°C, f = 1 MHz
Parameter
Condition
Typ
Max
Unit
CIN
Input Capacitance
6
8
pF
VIN = OV
COUT
Output Capacitance
10
12
pF
VOUT = OV
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T = 25'C. These currents
are valid for all product versions (packages and speeds).
2. leeES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
of leeES and leeR.
3. Block Erases and Word/Byte Writes are inhibited when Vpp = VPPL and not guaranteed in the range between VPPH and
VPPL·
4. Sampled, not 100% tested.
5. Automatic Power Savings (APS) reduces leeR to less than 1 mA typical in siatic operation.
6. CMOS Inputs are either Vee ±0.2V or GND ±0.2V. TTL Inputs are either VIL or VIH.
7. Vpp = 12.0V ±5% for applications requiring 100,000 block erase cycles.
S. Vpp = 12.0V ± 10% for applications requiring wider Vpp tolerances at 100 block erase cycles.
9. For the 2SF002BX, address pin A10 follows the COUT capacitance numbers.
10. leeR typical is 25 mA for X16 active read current.
STANDARD TEST CONFIGURATION(1)
. STANDARD AC INPUT/OUTPUT REFERENCE WAVEFORM
STANDARD AC TESTING
LOAD CIRCUIT
2.4 - - " " " ' " ·-..::----11---"'" ~"!:"":"--
INPUT
2.0
TEST POINTS
2.0 OUTPUT
0.45 _ _ _.1/\"0.8
./\,.'\,;,;0.;;,.8_ _ __
V
-1.3V,....
~~ lN914
290448-14
AC test inputs are driven at VOH (2.4 VnLl for a Logic "1" and VOL
(0.45 VnLl for a logic "0". Input timing begins at VIH (2.0 VnLl and VIL
(O.S VnLl. Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) < 10 ns.
Rc
DEVICE
UNDER
TEST
OUT
f~
290448-13
CL = 100 pF
CL Includes Jig Capacitance
RL = 3.3 Kfi
HIGH SPEED TEST CONFIGURATION(2)
HIGH SPEED AC INPUT/OUTPUT REFERENCE WAVEFORM
3.0
0.0
--IN-P-UT""XI.5_TES!~INTS-X
I .5
HIGH SPEED AC TESTING
LOAD CIRCUIT
OUTPUT
.!.:.~
51
~~
290448-22
AC test inputs are driven at 3.0V for a Logic "1" and O.OV for a logic "0".
Input timing begins, and output timing ends, at 1.5V. Input rise and fall times
(10% to 90%) < 10 ns.
NOTES:
1. Testing characteristics for 2SF200BX-60/2SF002BX-60 in standard test configuration and 2SF200BX-SO/2SF002BX-SO.
2. Testing characteristics for 2SF200BX-60/2SF002BX-60 in high speed test configuration.
I
lN914
Rc
DEVICE
UNDER
TEST
OUT
i~
-290448-21
CL=30pF
CL Includes Jig Capacitance
RL = 3.3 Kfi
4-249
28F200BX-T/B,28F002BX-T/B
AC CHARACTERISTICS-Read Only Operations(1)
Vee
Vee ±5%
Versions
Symbol
Parameter
AVAV tRC
Read Cycle Time
Notes
Min
CE # to Output Delay
2
GLQV tOE
OE # to Output Delay
2
ELQX tLZ
CE # to Output Low Z
3
EHQZ tHZ
CE # High to Output
HighZ
3
GHQZ tOF
OE # High to Output
HighZ
Min
3
10%
Min
Max
80
Min
80
70
Max
120
ns
120
ns
60
70
80
120
ns
300
300
300
300
ns
30
35
40
40
ns
0
0
20
0
3
Max
70
60
PHQV tpWH RP# High to
Output Delay
GLQX tOLZ OE # to Output Low Z
Max
60
AVQV tACC Address to
Output Delay
ELQV tCE
±
28F200BX·60(4) 28F200BX·60(5) 28F200BX·80(5) 28F200BX·120(5)
Unl
28F002BX-60(4) 28F002BX·60(5) 28F002BX·80(5) 28F002BX·120(5)
0
25
0
20
30
0
25
ns
0
30
0
ns
30
30
ns
ns
tOH Output Hold from
Addresses,
CE# orOE# Change,
Whichever is First
3
ELFL
ELFH
CE# to BYTE#
Switching
Low or High
3
5
.5
5
5
ns
FHQV
BYTE # Switching
High to
Valid Output Delay
3,6
60
70
80
120
ns
FLQZ
BYTE # SWitching
Low to
Output High Z
3
20
25
30
30
ns
0
0
0
0
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to tCE-tOE after the falling edge of CE# without impact on teE,
3. Sampled, not 100% tested.
4. See High Speed Test Configuration.
5. See Standard Test Configuration.
6. tFLQV, BYTE# switching low to valid output delay, will be equal to tAVQV, measured from the timeDQ1S/A-l becomes
valid.
4-250
I
28F200BX-T IB, 28F002BX-T IB
EXTENDED TEMPERATURE OPERATIONS
AC CHARACTERISTICS-Read Only Operations(1):
T2SF200BX-SO(4)
T2SFOO2BX-SO(4)
Versions
Symbol
Parameter
tAVAV
tRC
Read Cycle Time
tAVQV
tAce
Address to
Output Delay
Notes
Min
80
2
tELQV
teE
CE # to Output Delay
tpHQV
tPWH
RP# High to
Output Delay
tGLQV
tOE
OE # to Output Delay
2
tELQX
tLZ
CE # to Output Low Z
3
tEHQZ
tHZ
CE# High to Output
HighZ
3
tGLQX
tOLZ
OE# to Output Low Z
3
Unit
Max
ns
80
ns
80
ns
300
ns
40
ns
0
ns
30
a
ns
ns
30
tOF
OE# High to Output
HighZ
3
toH
Output Hold from
Addresses,
CE # or OE # Change,
Whichever is First
3
tELFL
tELFH
CE# to BYTE#
Switching
Low or High
3
5
ns
tFHQV
BYTE # Switching
High to
Valid Output Delay
3,5
80
ns
tFLQZ
BYTE # Switching
Low to
Output High Z
3
30
ns
tGHQZ
a
ns
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. CEll' may be delayed up to tCE-tOE after the falling edge of CEll' without impact on tCE.
3. Sampled. not 100% tested.
4. See Standard Test Configuration.
5. tFLQV. BYTE" switching low to valid output delay. will be equal to tAVQV. measured from the time OQs/A-1 becomes
valid.
I
4-251
/II)
;t
CD
U1
I\)
Vee POWER-UP
.~'=., '.
VIL
STANDBY
><>OO(
"TI
/II)
DEVICE AND
ADDRESS SELECTION
OUTPUTS ENABLED
DATA VALID
STANDBY
---
0
0
Vee POWER-DOWN
m
><
~
ADDRESSES STABLE
---
•
.!D
/II)
tAVAV
VIH
CE#(E)
VIL
!!
IQ
...CCD
....
PI
)0
(')
V1L
CD
1/1
m
><
.!oj
....m
---
VIH
VIL
t",nv
CD
DI
--l
VIH
a.
VIL
I-
tttttt
HIGH Z
DATA (D/O)
i
::::I
1/1
1
/II)
---
.....I
:D
0
0
0
WE# (w)
...0'
"C
CD
"TI
OE# (G)
0
3
I
VIH
~
<
-...
j
CD
I,
taH
VALID OUTPUT
1r\ \ \1\
HIGH Z
tAVQV
S.OV
Vee
_.:s
-
c[
I!!
28F200BX·T IB, 28F002BX·T IB
75
75
70
65
V
60
70
./
65
60
55
55
50
50
';?
45
-5
40
0
_0
35
./~
V
30
25
20
15
10
~
~
4 5
45
-5
40
0
_0
35
r--r-r--r--
30
~25OC
-6-70 o C
r--r-
20
-0- OOC
I I
I I I
5
1 2 3
V
';?
./
J
~
.)
t'"
25
~25OC
./
15
I
I
It"
10
-r-r-
-6-70 o C - I -
I
I
5
6 7 8 9 10 11 12 13 14 15 16
-0- OOC
I
I
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
fREQUENCY (MHz)
fREQUENCY (MHz)
290448-26
290448-27
Figure 18. Icc (RMS) vs Frequency
(Vee = 5.5V) for x8 Operation
Figure 17. Icc (RMS) vs Frequency
(Vee = 5.5V) for x16 Operation
100
95
90
85
'in'
..s
0
0
80
75
...< 70
65
60
~
/
/"
....... V
~~
/
/"
...,.-A V
./'
.....V
-0- 28f200BX/28f002BX-60
~ 28f200BX/28f002BX-80
55
50
30 50
100
150
200
250
OUTPUT CAPACITANCE (pf)
290448-28
Figure 19. TAee vs Output Load
Capacitance (Vee = 4.5V, T = 70·C)
I
4·253
N
ten
Q)
~
DEVICE
ADDRESS SELECTION
STANDBY
vlH
ADDRESSES STABLE
ADDRESSES (A)
"1'1
iii
c
V,L
N
V,H
iil
?
m
-I
V,H
......
ca
0
-
m
,0
STANDBY
UJ
><
.!t
.....
JD
t
N
Q)
"II
0
0
t
CE# (c)
V,L
3"
:;
DATA VALID
AVAV
~
m
...,
"II
0
0
N
N
UJ
><•
-I
AVfL = irLfL
.....
UJ
OE# (G)
V,L
V,H
::T
:D
BYTE# (r)
CD
DI
a.
V,L
DI
:::J
'<
VIL
I
!VPWH
VpPH
V (v) VPPL
PP
VIH
V1L
)
J
R
0
0
XT
1
-I
......
I---j IovVL
VX.
~m
X
)<
X
)<
I\)
CD
'11
0
0
I\)
m
><
290448-16
I
-I
......
m
28F200BX-T/B,28F002BX-T/B
AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS(1,9)
Vee ± 10%
Vee ±5%
Versions
Symbol
Parameter
tAVAV
twc Write Cycle Time
PHEL
tps
28F200BX-60(10) 28F200BX-60(11) 28F200BX-80(11) 28F200BX-12Q(11)
Unl
28F002BX-60(10) 28FOO2BX-60(11) 28F002BX-80(11) 28F002BX-12Q(11)
Notes
RP# High Recovery
to CE # Going Low
tWLEL tws WE# Setup to CE#
Going Low
Min
Max
Min
Max
Min
Max
Min
Max
60
70
80
120
ns
215
215
215
215
ns
0
0
0
0
ns
tpHHEH tpHS RP# VHH Setup to
CE # Going High
6,8
100
100
100
100
ns
VPEH
tvps Vpp Setup to CE#
Going High
5,8
100
100
100
100
ns
AVEH
tAS Address Setup to
CE # Going High
3
50
50
50
50
ns
4
60
60
60
60
ns
tovEH tos Data Setup to CE#
Going High
50
50
60
60
ns
tEHOX tOH Data Hold from
CE# High
4
0
0
0
0
ns
tEHAX tAH Address Hold
from CE # High
3
10
10
10
10
ns
10
10
10
10
ns
10
20
20
20
ns
2,5
6
6
6
6
/-,S
tELEH
tcp CE# Pulse Width
tEHWH tWH WE # Hold from
CE# High
tEHEL
tcPH CE# Pulse
Width High
tEHOV1
Duration of
Word/Byte
Programming
Operation
tEHOV2
Duration of Erase
Operation (Boot)
2,5,6
0.3
0.3
0.3
0.3
s
EHOV3
Duration of Erase
Operation
(Parameter)
2,5
0.3
0.3
0.3
0.3
s
tEHOV4
Duration of Erase
Operation (Main)
2,5
0.6
0.6
0.6
0.6
s
5,8
0
0
0
0
ns
6,8
0
0
0
0
ns
!oWL
tVPH Vpp Hold from
ValidSRD
OVPH tpHH RP# VHH Hold
from Valid SRD
PHBR
Boot-Block Relock
Delay
7
100
100
100
100
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# time should be
measured relative to the CE# waveform.
2,3,4,5,6,7,8: Refer to AC Characteristics notes for WE#-Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See High Speed Test Configuration.
11. See Standard Test Configuration.
4-260
I
28F200BX-T IB, 28F002BX-T IB
EXTENDED TEMPERATURE OPERATION
AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS(1,9)
T28F200BX-80(10)
T28FOO2BX-80(10)
Versions
Symbol
Parameter
Notes
Min
Unit
Max
tAVAV
twc
Write Cycle Time
80
ns
tpHEl
tps
RP# High Recovery
to CE # Going Low
220
ns
tWlEl
tws
WE # Setup to CE #
Going Low
0
ns
tpHHEH
tpHS
RP# VHH Setup to
CE# Going High
6,8
100
ns
tVPEH
tvps
V PP Setup to CE #
Going High
5,8
100
ns
tAVEH
tAS
Address Setup to
CE# Going High
3
60
ns
tOVEH
tos
Data Setup to CE#
Going High
4
60
ns
tElEH
tcp
CE # Pulse Width
60
ns
tEHOX
tOH
Data Hold from
CE# High
4
0
ns
tEHAX
tAH
Address Hold
from CE # High
3
10
ns
tEHWH
tWH
WE # Hold from CE # High
10
ns
tCPH
CE# Pulse
Width High
20
ns
2,5
7
J.Ls
2,5,6
0.4
s
tEHEl
tEHOV1
Duration of Word/Byte
Programming
Operation
tEHOV2
Duration of Erase
Operation (Boot)
tEHOV3
Duration of Erase
Operation (Parameter)
2, 5
0.4
s
tEHOV4
Duration of Erase
Operation (Main)
2, 5
0.7
s
5,8
0
ns
6,8
0
ns
!OWl
!VPH
Vpp Hold from
Valid SRD
tOVPH
tpHH
RP# VHH Hold
from Valid SRD
!PHBR
Boot-Block Relock Delay
-
7
100
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# time should be
measured relative to the CE # waveform.
2,3,4,5,6,7,8: Refer to AC Characteristics for WE#-Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See Standard Test Configuration.
I
4-261
I\)
1"
I\)
co
m
vee
I\)
POWER-UP
WRITE PROGRAM OR
ERASE SETUP COMMAND
& STANDBY
"TI
..
Ifi
C
ID
N
WRITE
VALID ADDRESS & DATA (PROGRAM)
OR ERASE CONFIRM COMMAND
."
AUTOMATED PROGRAM
OR ERASE DELAY
READ STATUS
REGISTER DATA
I\)
WRITE READ ARRAY
COMMAND
o
o
m
VIH
ADDRESSES (A)
~
:to
AtN
XI
><
.!t
.....
AtN
VIL
~m
VIH
CO
."
;:;
I\)
ID
!I
o
o
I\)
WE" (W)
m
><
VIL
0
II
~
m
VIH
DE" (G)
VIL
3
1/1
il
II
~HQV1,2,3,4
1•
-I
VIH
CE" (E)
VIL
ID
II)
::::I
a.
VIH
DATA (D/O)
VIL
"0
ID
2l
O·
VHH
::::I
1/1
6.SV
VIH
"0
m
....
-
CD
.!!.
. --------------------,
.
VIL
0
::::I
::e
:::!.
f:~~
RP# (p)
~
(,
2iii
a.
I
t VPEH
VpPH
v (v)
PP
-::::J
VPPL
VIH
VIL
290448-17
c[
@>
28F200BX-T IB, 28F002BX-T IB
ORDERING INFORMATION
OPERATING TEMPERATURE
T
= EXTENDED TEMP
8LANK = COMMERCIAL TEMP
Valid Combinations:
E28F2008X-T60
E28F2008X-860
E28F2008X-T80
E28F2008X-880
E28F2008X-T120
E28F2008X-8120
PACKAGE
E = STANDARD 56 LEAD TSOP
PA = 44 LEAD PSOP
T8 = 44 LEAD PSOP, EXTENDED TEMP
PA28F2008X-T60
PA28F2008X-860
PA28F2008X-T80
PA28F2008X-880
PA28F2008X-T120
PA28F2008X-8120
OPERATING TEMPERATURE
T
EXTENDED TEMP
BLANK COMMERCIAL TEMP
=
=
TE28F2008X-T80
TE28F2008X-880
60 ns
80 ns
120 ns
290448-18
T828F2008X-T80
T828F2008X-880
PACKAGE
E
STANDARD 40 LEAD TSOP
=
60 ns
80 ns
120 ns
290448-23
Valid Combinations:
E28F0028X-T60
E28F0028X-860
E28F002BX-T80
TE28F0028X-T80
E28F0028X-880
TE28F0028X-880
E28F002BX-T120
E28F0028X-8120
ADDITIONAL INFORMATION
Order
Number
292130
Document
AB-57 "Boot Block Architecture for Safe Firmware Updates"
292154
AB-60 "2/4/8-Mbit SmartVoltage Boot Block Flash Memory Family"
292098
AP-363 "Extended Flash BIOS Concepts for Portable Computers"
292148
AP-604 "Using Intel's Boot Block Flash Memory Parameter Blocks to Replace EEPROM"
290449
28F002/200BL-T IB 2-Mbit Low Power Boot Block Flash Memory Datasheet
290450
28F004/400BL-T IB 4-Mbit Low Power Boot Block Flash Memory Datasheet
290451
28F004/400BX-T IB 4-Mbit Boot Block Flash Memory Datasheet
290531
2-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290530
4-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
290539
8-Mbit SmartVoltage Boot Block Flash Memory Family Datasheet
I
4-263
28F200BX-T/B, 28F002BX-T IB
REVISION HISTORY
Number
Description
-002
Removed - 70 speed bin
Integrated -70 characteristics into -60 speed bin
Added Extended Temperature characteristics
Modified BYTE# Timing Diagram
Improved tpHQV. RP# High to Output Delay and tPHEL. RP# High Recovery to CE# going low
specifications
-003
PWD changed to RP# for JEDEC standardization compatibility.
Combined Vcc Read current for 28F200BX Word-wide mode and Byte-wide mode. and
28F002BX Byte-wide mode in DC Characteristics tables.
Change IPPS current spec from ± 10 /LA to ± 15 /LA in DC Characteristics tables.
Improved ICCR and Iccw in DC Characteristics: Extended Temperature Operation table.
Improved tAvAV. tAVQV. tELQV. tGLQV. tEHQZ. tGHQZ. tFHQV and tFLQZ specifications for
Extended Temperature Operations AC Characteristics-Read and Write Operations.
-004
Added specifications for 120 ns access time product version; 28F200BX-120 and
28F002BX-120.
Included permanent change on write timing parameters for -80 ns product versions. Write
pulse width (twp and tcp) increases from 50 ns to 60 ns. Write pulse width high (tWPH and
tCPH) decreases from 30 ns to 20 ns. Total write cycle time (twc) remains unchanged.
Added ICCR test condition note for typical frequency value in DC characteristics table.
Added IOH CMOS specification.
Added 28F400BX interface to Intel386TMEX Embedded Processor block diagram.
Added description of how to upgrade to SmartVoltage Boot Block products.
4-264
I
28F200BL-T IB, 28F002BL-T IB
2-MBIT (128K x 16, 256K x 8) LOW POWER BOOT ·BLOCK
FLASH MEMORY FAMILY
• Low Voltage Operation for Very Low
Power Portable Applications
-Vcc = 3.0V-3.6V
• Expanded Temperature Range
- - 20·C .to + 70·C
• xS/x16 Input/Output Architecture
- 2SF200BL-T, 2SF200BL-B
- For High Performance and High
Integration 16-bit and 32-bit CPUs
• xS-only Input/Output Architecture
- 2SF002BL-T, 2SF002BL-B
- For Space Constrained S-bit
Applications
• Upgradeable to Intel's SmartVoltage
Products
• Optimized High Density Blocked
Architecture
-- One 16-KB Protected Boot Block
- Two S-KB Parameter Blocks
- One 96-KB Main Block
-One 12S-KB Main Block
- Top or Bottom Boot Locations
• Extended Cycling Capability
-10,000 Illock Erase Cycles
• Automated Word/Byte Write and Block
'
Erase
- Command User Interface
- Status Registers
- Erase Suspend Capability
November 1994
Order Number: 290449-004
• SRAM-Compatible Write Interface
• Automatic Power Savings Feature
- O.S rnA Typical Icc Active Current in
Static Operation
• Very High-Performance Read
-150 ns Maximum Access Time
- 65 ns Maximum Output Enable Time
• Low Power Consumption
-15 rnA Typical Active Read Current
• Reset/Deep Power-Down Input
- 0.2 p.A Icc Typical
...:.. Acts as Reset for Boot Operations
II
II
Write Protection for Boot Block
Hardware Data Protection Feature
- Erase/Write Lockout during Power
Transitions
• Industry Standard Surface Mount
Packaging
- 2SF200BL: JEDEC ROM Compatible
44-Lead PSOP
56-Lead TSOP
- 2SF002BL: 40-Lead TSOP
•
12V Word/Byte Write and Block Erase
-Vpp = 12V ±5% Standard
II ETOX III Flash Technology
-3.3V Read
II Independent Software Vendor Support
4·265
28F200BL-T IB, 28F002BL-T IB
Intel's 2-Mbit Low Power Flash Memory Family is an extension of the Boot Block Architecture which inCludes
block-selective erasure, automated write and erase operations and standard microprocessor interface. The
2-Mbit Flash Memory Family enhances the Boot Block Architecture by adding more density and blocks,
xB/x16 input/output control, very low power, very high speed, an industry standard ROM compatible pinout
and surface mount packaging. The 2-Mbit Low Power Flash Family opens a new capability for 3V battery-operated portable systems and allows for an easy upgrade to Intel's 4-Mbit Low Power Boot Block Flash Memory
Family.
The Intel 2BF200BL-T /B are 16-bit wide flash memory offerings. These high density flash memories provide
user selectable bus operation for either B-bit or 16-bit applications. The 2BF200BL-T and 28F200BL-B are
2,097,152-bit non-volatile memories organized as either 262,144 bytes or 131,072 words of information. They
are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The xB/x16 pinout conforms to the industry
standard ROM/EPROM pinout.
The Intel 2BF002BL-T/B are 8-bit wide flash memories with 2,097,152 bits organized as 262,144 bytes of
information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable
systems.
These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The 28F200BL-T /28F002BL-T provide block locations compatible with
Intel's low voltage MCS-186 family, i386™, i486TM microprocessors. The 28F200BL-B/28F002BL-B provide
compatibility with Intel's 80960KX and 80960SX families as well as other low voltage embedded microprocessors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 150 ns, these 2-Mbit flash devices are very high performance low power memories
which interface to a wide range of low power microprocessors and microcontrollers. A deep power-down mode
lowers the total Vee power consumption to 0.66 p.W. This is critical in handheld battery powered systems such
as Handy Phones. For very high speed applications using a 5V supply, refer to the Intel 28F200BX-T/B,
28F002BX-T/B 2-Mbit Boot Block Flash Memory Family datasheet.
Manufactured on Intel's 0.8 micron ETOX III process, the 2-Mbit low power flash memory family provides world
class quality, reliability and cost-effectiveness at the 2-Mbit density level.
4-266
I
28F200BL·T IB, 28F002BL·T IB
1.0 PRODUCT FAMILY OVERVIEW
Throughout this datasheet 28F200BL refers to both
the 28F200BL-T and 28F200BL-B devices and
28F002BL refers to both the 28F002BL-T and
28F002BL-B devices. The 2-Mbit flash family refers
to both the 28F200BL and 28F002BL products. This
datasheet comprises the specifications for four separate products in the 2-Mbit flash memory family.
Section 1 provides an overview of the 2-Mbit flash
memory family including applications, pinouts and
pin descriptions. Sections 2 and 3 describe in detail
the specific memory organizations for the 28F200BL
and 28F002BL products respectively. Section 4
combines a description of the family's principles of
operations. Finally, section 5 describes the family's
operating specifications.
PRODUCT FAMILY
x8/x16 Products
x8-0nly Products
28F200BL-T
28F200BL-B
28F002BL-T
28F002BL-B
1.1 Designing for Upgrade to
SmartVoltage Products
Today's high volume boot block products are upgradable to Intel's SmartVoltage boot block products that provide program and erase operation at 5V
or 12V Vpp and read operation at 3V or 5V Vee.
Intel's SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this data sheet:
1. DU pin is replaced by WP # to provide a means
to lock and unlock the boot block with logic signals.
2. 5V Program/Erase operation uses proven program and erase techniques with 5V ± 10% applied to Vpp.
3. Enhanced circuits optimize performance at 3.3V
Vee·
Refer to the 2, 4 or 8 Mbit SmartVoltage Boot Block
Flash Memory Data Sheets for complete specifications.
When you design with 12V Vpp boot block products
you should provide the capability in your board design to upgrade to SmartVoltage products.
I
Follow these guidelines to ensure compatibility:
1. Connect DU (WP # on SmartVoltage products) to
a control signal or to Vee or GND.
2. If adding a switch on Vpp for write protection,
switch to GND for complete write protection.
3. Allow for connecting 5V to Vpp and disconnect
12V from line Vpp line, if desired.
1.2 Main Features
The 28F200BLl28F002BL low power boot block
flash memory family is a very low power and very
high performance 2-Mbit (2,097,152 bit) memory
family organized as either 128 Kwords (131,072
words) of 16 bits each or 256 Kbytes· (262,144
bytes) of 8 bits each.
Five Separately Erasable Blocks including a Hardware-Lockable boot block (16,384 Bytes), two parameter blocks (8,192 Bytes each) and two main
blocks (1 block of 98,304 Bytes and 1 block of
131,072 Bytes) are included on the 2-Mbit family. An
erase operation erases one of the 5 blocks in typically 3.4 seconds and the boot or parameter blocks
in typically 2.0 seconds, independent of the remaining blocks. Each block can be independently erased
and programmed 10,000 times.
The Boot Block is located at either the top
(28F200BL-T, 28F002BL-T) or the bottom
(28F200BL-B, 28F002BL-B) of the address map in
order to accommodate different microprocessor protocols for boot code location. The hardware lockable boot block provides the most secure code storage. The boot block is intended to store the kernel
code required for booting-up a system. When the
RP# pin is between 11.4V and 12.6V the boot block
is unlocked and program and erase operations can
be performed. When the RP # pin is at or below 4.1 V
the boot block is locked and program and erase operations to the boot block are ignored.
The 28F200BL products are available in the
ROM/EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package and
the 56-Lead TSOP (Thin Small Outline, 1.2 mm
thick) package as shown in Figures 3 and 4. The
28F002BL products are available in the 40-Lead
TSOP (1.2 mm thick) package as shown in Figure 5.
The Command User Interface (CUI) serves as the
interface between the microprocessor or microcontroller and the internal operation of the 28F200BL
and 28F002BL flash memory products.
4-267
28F200BL-T IB, 28F002BL-T IB
Program and Erase Automation allow program
and erase operations to be executed using a twowrite command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in word or
byte increments for the 2SF200BL family and in byte
increments for the 2SF002BL family typically within
11 ,...s.
The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.
Maximum Access Time of 150 ns (TACc) is
achieved over the commercial temperature range
(O°C to + 70°C), over Vee supply voltage range
(3.0V to 3.6V, 4.SV to S.SV) and SO pF output load.
Ipp Program current Is 40 mA for x16 operation
and 30 mA for x8 operation. Ipp Erase current is
30 mA maximum. Vpp erase and programming
voltage is 11.4V to 12.6V (Vpp = 12V ±5%) under all operating conditions.
Typical Icc Active Current of 15 mA is achieved
for the x16 products and the xS products.
The 2-Mbit flash family is also designed with an Automatic Power Savings (APS) feature to minimize
system battery current drain and allow for extremely
low power designs. Once the device is accessed to
read the array data, APS mode will immediately put
the memory in static mode of operation where Icc
active current is typically O.S mA until the next read
is initiated.
When the CE# and RP# pins are at Vee and the
BYTE# pin (2SF200BL-only) is at either Vee or GND
the CMOS Standby mode is enabled where Icc is
typically 40 ,...A.
A Deep Power-down Mode is enabled when the
RP# pin is at ground minimizing power consumption
and providing write protection. during power-up conditions. ICC current during deep power-down mode
is 0.20 ,...A typical. An initial maximum access time
or Reset Time of 600 ns is required from RP#
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 1 ,...S until
writes to the Command User Interface are recognized. When RP# is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature prevents data corruption and protects 'he code stored
in the device during system reset. The system Reset
pin can be tied to RP# to reset the memory to nor-
4-26S
mal read mode upon activation of the Reset pin.
When the CPU enters reset mode, it expects to read
the contents of a memory location. Furthermore,
with on-chip program/erase automation in the
2-Mbit family and the RP# functionality for data protection, after the CPU is reset and even if a program
or erase command is issued, the device will not recognize any operation until RP# returns to its normal
state.
For the 28F200BL, Byte-wide or Word-wide input/Output Control is possible by controlling the
BYTE # pin. When the BYTE # pin is at a logic low
the device is in the byte-wide mode (xS) and data is
read and written through 00[0:7]. During the bytewide mode, DO[S:14] are tri-stated and D01S/A-1
becomes the lowest order address pin. When the
BYTE# pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DO[O:1S].
1.3 Applications
The 2-Mbit low power boot block flash memory family combines high density, 3V operation, high performance, cost-effective flash memories with blocking and hardware protection capabilities. Its flexibility
and versatility will reduce costs throughout the product life cycle. Flash memory is ideal for Just-In-Time
production flow, reducing system inventory and
costs, and eliminating component handling during
the production phase. During the product life cycle,
when code updates or feature enhancements become necessary, flash memory will reduce the update costs by allowing either a user-performed code
change via floppy disk or a remote code change via
a serial link. The 2-Mbit boot block flash mernory
family provides full function, blocked flash memories
suitable for a wide range of applications. These applications include Extended PC BIOS, Handy Digital Cellular Phone program and data storage and
various other portable embedded applications where
both program and data storage are required.
Reprogrammable systems such as Notebook and
Palmtop computers, are ideal applications for the
2-Mbit low power flash products. Portable and handheld personal computer applications are becoming
more complex with the addition of power management software to take advantage of the latest microprocessor technology, the availability of ROM-based
application software, pen tablet code for electronic
handwriting, and diagnostic code. Figure 1 shows an
example of a 2BF200BL-T application.
.
This increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped. The 2-Mbit low power flash
memory products provide an inexpensive update so-
I
28F200BL·T IB, 28F002BL·T IB
lution for the notebook and handheld personal computers while extending their product lifetime. Furthermore, the 2-Mbit flash memory products' deep
power-down mode provides added flexibility for
these battery-operated portable designs which require operation at extremely low power levels.
Blocks of program code and 2 Parameter Blocks of
B Kbytes each for frequently updatable data storage
and diagnostic messages (e.g., phone numbers, authorization codes). Figure 2 is an example of such an
application with the 2BF002BL-T.
These are a few actual examples of the wide range
of applications for the 2-Mbit Low Power Boot Block
flash memory family which enables system designers to achieve the best possible product design.
Only your imagination limits the applicability of such
a versatile low power product family.
The 2-Mbit low power flash products also provide
excellent design solutions for Handy Digital Cellular
Phone applications requiring high density storage,
high performance capabilities coupled with low voltage operation, and a small form factor package (xBonly bus). The 2-Mbit's blocking scheme allows for
an easy segmentation of the embedded code with:
16 Kbytes of Hardware-Protected Boot code, 2 Main
12V
GPIO
RESET#
A[O:17]
CS#
I
I
1-----------,/
1-----------+1
RO#
CE#
OE#
Into1386," EX
Embedded
r-~-~I
=D---i"-_.I
1-------+1 WE#
WR#
Processor
0[0:15]
Transceiver
GPIO-_-'
RESET#
PWRGOOO--1--'
Intel
28F2008L-T
OQ[0:15]
RP#
290449-6
Figure 1_ 28F200BL-T Interface to Intel386TM EX Embedded Processor
A,6:17
A8 -A,
ALE5
1----,/
""====+---:===:::::;,
t-
AOo-A~
80L188EB
UCS#
1-------------+1
CE# 28F002BX-TL
Vpp
P1.XI----+I
WR#
RO#
RE5IN#
RP#
1 - - - - - - - - - - - -...... WE#
OE#
1 - - -.....- - - - - - - - - - - - - - - -...
SYSTEM RESET
290449-22
Figure 2_ 28F002BL-T Interface to INTEL 80L 188EB, Low Voltage 8-Bit Embedded Microprocessor
I
4-269
28F200BL·T IB, 28F002BL·T IB
1.4 Pinouts
Figure 4 provides density upgrades to the 28F400BL
and to future higher density boot block memories.
The 28F200BL 44-Lead PSOP pinout follows the industry standard ROM/EPROM pinout as shown in
Figure 3 with an upgrade to· the 28F400BL
(4-Mbit low power flash family). Furthermore,
the 28F200BL 56-Lead TSOP pinout shown in
The 28F002BL 40-Lead TSOP pinout shown in Figure 5 is 100% compatible and has a density upgrade to the 28F004BL 4-Mbit Low Power Boot
Block flash memory.
28F400BL
28F400BL
Vpp
DU
Vpp
RP#
DU
WE#
A17
A?
As
A5
A4
A3
A2
Al
Ao
NC
As
A7
Ag
As
A,o
As
A11
A.
A'2
A3
A2
A,
CE#
CE#
GND
GND
OE#
OE#
DOo
DOs
DOr
DOg
D02
D010
D03
DOll
000
A13
PA28F200BL
44 LEAD PSOP
0.525" X 1.110"
TOP VIEW
A,.
A,s
A,s
RP#
WE#
As
Ag
A10
All
A12
A13
A14
A15
A1S
8YTE#
BYTE#
GND
GND
DO,s/A_,
D015/A-l
DO?
D014
DOs
D013
D0 5
D012
D04
Vee
DO,
DOs
0°14
DO,
DOs
DO,
OQ13
D02
DOs
OQ10
OQ12
D03
DO.
OQ11
Vee
290449-24
Figure 3. PSOP Lead Configuration for x8/x16 28F200BL
4-270
I
intel®
28F200BL-T IB, 28F002BL-T IB
28F400BL
NC
NC
AIS
A14
A13
A12
All
Al0
Ag
As
NC
NC
WE#
RP#
NC
NC
Vpp
DU
NC
A17
A7
As
As
~
A3
A2
Al
NC
28F400BL
NC
NC
AIS
A14
A13
A12
All
A10
Ag
AS
NC
NC
WE#
RP#
NC
NC
Vpp
DU
NC
NC
A7
As
As
A4
A3
Az
Al
NC'
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
0
28F200BL
56-LEAD TSOP
14mm X 20mm
TOP VIEW
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
3.1
30
29
NC
A16
8YTE#
GND
DOl 5 /A_ l
DO?
DOl 4
D06
DOl 3
DOS
DOl 2
D04
NC
AlB
BYTE #
GND
DOIS/A-l
D07
D014
D06
D013
DOs
D012
D04
Vee
Vee
Vee
Vee
DOll
D03
DOlO
D02
DOg
DOl
DOs
DOo
OE#
GND
CE#
Ao
NC
NC
0011
D03
DOlO
D02
DOg
DOl
DOs
DOo
OE#
GND
CE#
Ao
NC
NC
290449-4
Figure 4. TSOP Lead Configuration for x8/x16 28F200BL
28FOO4BL
28FOO4BL
A16
AIS
A14
A13
A12
All
Ag
As
WE#
RP#
A14
A13
A12
All
Ag
As
WE#
RP#
Vpp
Vpp
DU
AIS
A7
A6
As
A4
A3
A2
Al
DU
NC
A7
A6
As
A4
A3
Az
Al
A1S
A1S
~O
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28FOO2Bl
40-lEAD TSOP
10mm X 20mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
NC
NC
A10
DO?
DOs
DOs
D04
A17
GND
NC
NC
Al0
007
006
DOs
004
Vee
Vee
Vee
Vee
NC
D03
DOz
DOl
DOo
OE#
GND
CE#
Ao
NC
003
002
001
000
OE#
GND
CE#
Ao
A17
290449-5
Figure 5. TSOP Lead Configuration for x8 28FOO2BL
I
4-271
28F200BL-T IB, 28F002BL-T IB
1.5 Pin Descriptions for x8/x16 28F200BL
Symbol
Type
Name and Function
Ao-A16
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle.
Ag
I
ADDRESS INPUT: When Ag is at 12V the signature mode is accessed. During this
mode Ao decodes between the manufacturer and device ID's.When BYTE# is at
a logic low only the lower byte of the signatures are read. 0015/ A-1 is a don't
care in the signature mode when BYTE # is low.
DOO-D07
I/O
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a program command. Inputs commands to the command user interlace
when CE# and WE# are active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and Status Register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.
D08-D015
I/O
DATA INPUT/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a program command. Data is internally latched during the write and program
cycles. Outputs array data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled as in the byte-wide mode (BYTE # = "0").
In the byte-wide mode 0015/ A-1 becomes the lowest order address for data
output on DOO-D07.
CE#
I
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE# is active low; CE# high deselects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow through
the CE# and RP# input stages.
RP#
I
RESET/DEEP POWER·DOWN: Provides Three-State control. Puts the device in
deep power-down mode. Locks the boot block from program/erase.
When RP # is at logic high level and equals 4.1 V maximum the boot block is
locked and cannot be programmed or erased.
When RP# = 11.4V minimum the boot block is unlocked and can be programmed
or erased.
When RP# is at a logic low level the boot block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RP# transitions from logic low to logic high, the flash memory
enters the read-array mode.
OE#
I
OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. OE # is active low.
WE#
I
WRITE ENABLE: Controls writes to the Command Register and array blocks.
WE # is active low. Addresses and data are latched on the rising edge of the WE #
pulse.
4-272
I
28F200BL-T /B, 28F002BL-T /B
1.5 Pin Descriptions for x8/x16 28F200BL (Continued)
Symbol
Type
Name and Function
BYTE#
I
BYTE # ENABLE: Controls whether the device operates in the byte-wide mode (x8) or
the word-wide mode (x16). BYTE# = "0" enables the byte-wide mode, where data is
read and programmed on OOO-OO? and 0015/A-1 becomes the lowest order
address that decodes between the upper and lower byte. 008-0014 are tri-stated
during the byte-wide mode. BYTE # = "1" enables the word-wide mode where data is
read and programmed on 000-0015.
Vpp
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
Note: Vpp
< VpPLMAX memory contents cannot be altered.
Vee
DEVICE POWER SUPPLY (3.3V ±0.3V, 5V
± 10%)
GNO
GROUND: For all internal circuitry.
NC
NO CONNECT: Pin may be driven or left floating.
OU
DON'T USE PIN: Pin should not be connected to anything.
I
4-273
28F200BL-T IB, 28F002BL-T IB
1.6 Pin Descriptions for x8 28F002BL
Symbol
Type
Name and Function
Ao-A17
I
ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.
As
I
ADDRESS INPUT: When As is at 12V the signature mode is accessed. During this
mode Ao decodes between the manufacturer and device ID's.
110
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a program command. Inputs commands to the command user interface
when CE# and WE# are active. Data is internally latched during the write and
program cycles. Outputs array Intelligent Identifier and status register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled .
DOo-D07
CE#
I
.CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE # is active low; CE # high deselects the memory device and
reduces power consumption to standby levels.
RP#
I
RESET/DEEP POWER·DOWN: Provides Three-State control. Puts the device in
deep power-down mode. Locks the Boot Block from program/erase.
When RP# is at logic high level and equals 4.1V maximum the Boot Block is locked
and cannot be programmed or erased.
When RP# = 11.4V minimum the Boot Block is unlocked and can be programmed
or erased.
When RP # is at.a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RP# transitions from logic low to logic high, the flash memory
enters the read-array mode.
OE#
I
OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. OE # is active low.
WE#
I
WRITE ENABLE: Controls writes to the Command Register and array blocks. WE#
is active low. Addresses and data are latched on the rising edge of the WE # pulse.
Vpp
PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.
Note: Vpp
< VPPLMAX memory contents cannot be altered.
Vee
DEVICE POWER SUPPLY (3.3V
GND
GROUND: For all internal circuitry
± 0.3V, 5V ± 10%)
NC
NO CONNECT: Pin may be driven or left floating
DU
.DON'T USE PIN: Pin should not be connected to anything
4-274
I
-
N
b
N
C»
"11
N
0
0
m
r-
_.
::J
€:
®
"U
:D
0
0
C
0
"TI
~
...III
c::
-t
!»
II.)
CD
8YTE#
"TI
II.)
0
0
en
0
m
en
0
m
r
=e
0
...
Q.
.....
m
.. I
-
'<
COMMAND
USER
INTERFACE
t
C[#
~
W[#
-t
OE#
RP#
POWER
"U
0
Z
III
a:==
III
m
0'
()
Ao -
A16
Y-DECODER
Y-GATING/SENSING
Vpp
~
C
i»
...III
U2
3
X-DECODER
••
••
~~
>-0
",-'
",'"
,
0-
",0
--0
'"U
0
-'
'"0
U
-'
::'''' ::''''
>-0:
>-0:
' " 0-
' " 0-
'"
,,,, '"",,,,
,2
III",
",2
«
0:
;t
«
0:
;t
",'"
~g
",'"
'"'z
-
"'2'
"''''
>-0
o-U
'" -'
",III
ch~
N«
1'1)
+- Vee
+- GND
CD
."
1'1)
Q
Q
m
-2
r
I
-t
.....
.JD
I\)
290449-1 I
CD
."
Q
Q
I\)
m
f'
1\)
-oJ
01
--_._---
~
.....
m
28F200BL·T IB, 28F002BL·T IB
2.1 28F200BL Memory Organization
2.1.1 BLOCKING
The 28F200BL uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F200BL is
a random read/write memory, only erasure is performed by block.
2.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RP# is not at 12V. The boot block can
be erased and written when RP# is held at 12V for
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address locations of the boot block for the 28F200BL-T and
28F200BL-B.
2.1.1.2 Parameter Block Operation
The 28F200BL has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide storage for frequently updated system parameters and configuration or diagnostic information. The
parameter blocks can also be used to store additional boot or main code. The parameter blocks however, do not have the hardware write protection feature
that the boot block has. The parameter blocks provide for more efficient memory utilization when dealing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for address locations of the parameter blocks for the
28F200BL-T and 28F200BL-B.
2.1.1.3 Main Block Operation
Two main blocks of memory exist on the 28F200BL
(1 x 128-Kbyte block and 1 x 96-Kbyte blocks). See
the following section on Block Memory Map for the
address location of these blocks forthe 28F200BL-T
and 28F200BL-B products.
2.1.2 BLOCK MEMORY MAP
Two versions of the 28F200BL product exist to support two different memory maps of the array blocks
in order to accommodate different micropro- cessor
protocols for boot code location. The 28F200BL-T
memory map is inverted from the 28F200BL-B memory map.
2.1.2.1 28F200BL-B Memory Map
The 28F200BL-B device has the 16-Kbyte boot
block located from OOOOOH to 01 FFFH to accommodate those microprocessors that boot from the
bottom of the address map at OOOOOH. In the
28F200BL-B the first 8-Kbyte parameter block resides in memory space from 02000H to 02FFFH.
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96-Kbyte main block resides in memory space from
04000H to OFFFFH. The 128-Kbyte main block resides in memory space from 10000H to 1FFFFH
(word locations). See Figure 7.
(Word Addresses)
lFFFFH
12B-Kbyte MAIN BLOCK
10000H
OFFFFH
96-Kbyte MAIN BLOCK
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
B-Kbyte PARAMETER BLOCK
B-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
OOOOOH
Figure 7. 28F200BL·B Memory Map
4-276
I
28F200BL-T IB, 28F002BL-TIB
2.1.2.2 28F200BL-T Memory Map
The 28F200BL-T device has the 16-Kbyte boot
block located from 1EOOOH to 1FFFFH to accommodate those microprocessors that boot from the top
of the address map. In the 28F200BL-T the first
8-Kbyte parameter block resides in memory space
from 1DOOOH to 1DFFFH. The second 8-Kbyte parameter block resides in memory space from
1COOOH to 1CFFFH. The 96-Kbyte main block resides In memory space from 10000H to 1BFFFH.
The 128-Kbyte main block resides in memory space
from OOOOOH to OFFFFH as shown below in Figure
8.
(Word Addresses)
1FFFFH
16.Kbyte BOOT BLOCK
1EOOOH
1DFFFH
1DOOOH
1CFFFH
1COOOH
1BFFFH
8·Kbyte PARAMETER BLOCK
8·Kbyte PARAMETER BLOCK
96·Kbyte MAIN BLOCK
10000H
OFFFFH
12B-Kbyte MAIN BLOCK
OOOOOH
Figure 8. 28F200BL-T Memory Map
I
4-277
N
Co)
"""
ro
co
C
-..j
ex>
"TI
N
1'1)
Q
Q
co
.
m
"11
0
0
DOo-D~
r-
-I
.....
1'1)
m
r-
,!lI
::D
N
CO
"TI
C
N
"U
Q
Q
0
.
c::
m
iEi
c
-I
-I
.....
CD
C
r-
0
'TI
.
en
!D
m
m
en
I\)
(II
0
'TI
0
0
CE#
I\)
COMMAND
USER
INTERFACE
III
r
-::
III
'<
CD
WE#
:!!
"U
-I
OE#
(5
RP#
Z
a:CD
III
0"
0
~
Y-DECODER
AO - AI7
iii'
CQ
DI
3
Y-GATING/SENSING
-~
~
0
..
~
L1\
-.I
'"g'-'
'-'
'"
g
>-0:
"'~
>-0:
~
I~
I~
~ '" ~'" ~'"
•• ~'"
. "' .... "''" ....
"":::. "":::.
~'-'
.... 0
>-~
X-DECODER
~
""0:
;:t
""0:
;:t
~'"
'-'
....
>-0
....
>-0
",'"
IZ
"''''
cb~
<'I""
"'~
'".:::.
",""
I I
"'~~~~u~~~'~
1+-+1 ~'~~~~~~/<:~~~~~"- Vpp
~'"
'-'
"'~
-'"
290449-2
-
_.
:l
c[
@
28F200BL-T IB, 28F002BL-T IB
3.1 28F002BL Memory Organization
See the following section on Block Memory Map for
the address location of these blocks for the
28F002BL-T and 28F002BL-B.
3.1.1 BLOCKING
The 28F002BL uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block address range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F002BL is
a random read/write memory, only erasure is performed by block.
3.1.1.1 Boot Block Operation and Data
Protection
The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of power failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being programmed
or erased when RP# is not at 12V. The boot block
can be erased and programmed when RP # is held
at 12V for the' duration of the erase or program operation. This allows customers to change the boot
code when necessary while still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
28F002BL-T and 28F002BL-B.
3.1.1.2 Parameter Block Operation
The 28F002BL has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide storage for frequently updated system parameters and configuration or diagnostic information. The
parameter blocks can also be used to store additional boot or main code. The parameter blocks however, do not have the hardware write protection feature
that the boot block has. Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map section for address locations of the parameter blocks
for the 28F002BL-T and 28F002BL-B.
3.1.2 BLOCK MEMORY MAP
Two versions of the 28F002BL product exist to support two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F002BL-T
memory map is inverted from the 28F002BL-B memory map.
3.1.2.1 28F002BL-B Memory Map
The 28F002BL-B device has the 16-Kbyte boot
block located from OOOOOH to 03FFFH to accommodate those microprocessors that boot from the bottom of the address map at OOOOOH. In the
28F002BL-B the first 8-Kbyte parameter block resides in memory from 04000H to OSFFFH. The sec, ond 8-Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96-Kbyte main
block resides in memory space from 08000H to
1FFFFH. The 128~Kbyte main block resides in memory space from 20000H to 3FFFFH. See Figure 10.
3FFFFH
128-Kbyte MAIN BLOCK
20000H
1FFFFH
96-Kbyte MAIN BLOCK
08000H
07FFFH
06000H
05FFFH
04000H
03FFFH
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16·Kbyte BOOT BLOCK
OOOOOH
Figure 10. 28F002BL-B, Memory Map
3.1.1.3 Main Block Operation
Two main blocks of memory exist on the 28F002BL
(1 x 128-Kbyte block and 1 x 96-Kbyte block).
I
4-279
28F200BL·T IB, 28F002BL·T IB
3.1.2.2 28F002BL·T Memory Map
The 2BF002BL·T device has the 16-Kbyte boot
block located trom 3COOOH to 3FFFFH to accom- .
modate those microprocessors that boot from the
top of the address map. In the 2BF002BL-T the first
B-Kbyte parameter block resides in memory space
from 3AOOOH to 3BFFFH. The second B-Kbyte parameter block resides in memory space from
38000H to 39FFFH. The 96-Kbyte main block resides in memory space from 20000H to 37FFFH.
The 12B-Kbyte main block resides in memory space
from OOOOOH to 1FFFFH.
3FFFFH
16·Kbyte BOOT BLOCK
3COOOH
3BFFFH
3AOOOH
39FFFH
38000H
8·Kbyte PARAMETER BLOCK
8·Kbyte PARAMETER BLOCK
37FFFH
96·Kbyte MAIN BLOCK
20000H
1FFFFH
128·Kbyte MAIN BLOCK
OOOOOH
4.0
In the absence of high voltage on the Vpp pin, the
2-Mbit flash family will only successfully execute the
following commands: Read Array, Read Status Register, Clear Status Register and Intelligent Identifier
mode. The device provides standard EPROM read,
standby and output disable operations. Manufacturer Identification and Device Identification data can
be accessed through the CUI or through the standard EPROM A9 high voltage access (VIO) (for
PROM programmer equipment).
The same EPROM read, standby and output disable
functions are available when high voltage is applied
to the Vpp pin. In addition, high voltage on Vpp allows write· and erase of the device. All functions associated with altering memory contents: write and
erase, Intelligent Identifier read and Read Status are
accessed via the CUI.
The purpose of the Write State Machine (WSM) is to
completely automate the write and erasure of the
- device. The WSM will begin operation upon receipt
of a signal from the CUI and will report status back
through a Status Register. The CUI will handle the
WE # interface to the data and address latches, as
well as system software requests for status while the
WSM is in operation.
Figure 11. 28F002BL-T Memory Map
4.1 28F200BL Bus Operations
PRODUCT FAMILY PRINCIPLES
OF OPERATION
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
Flash memory augments EPROM functionality with
in-circuit electrical write and erase. The 2-Mbit flash
family utiliz.es a Command User Interface (CUI) and
internally generated and timed algorithms to simplify
write and erase operations.
4-2BO
The CUI allows for fixed power supplies during erasure and programming, and maximum EPROM compatibility.
I
28F200BL-T IB, 28F002BL-T IB
Table 1. Bus Operations for WORD-WIDE Mode (BYTE# = VIH)
Notes
Mode
RP#
OE#
CE#
WE#
Ag
Ao
Vpp
X
X
DOUT
DQO-15
VIH
VIL
VIL
VIH
X
Output Disable
VIH
VIL
VIH
VIH
X
X
X
HighZ
Standby
VIH
VIH
X
X
X
X
X
HighZ
Read
1,2,3
Deep Power-Down
9
VIL
X
X
X
X
X
X
HighZ
Intelligent Identifier (Mfr)
4
VIH
VIL
VIL
VIH
VIO
VIL
X
0089H
4,5,
10
VIH
VIL
VIL
VIH
VIO
VIH
X
2274H
2275H
6,7,8
VIH
VIL
VIH
VIL
X
X
X
DIN
Intelligent Identifier (Device)
Write
Table 2. Bus Operations for BYTE-WIDE Mode (BYTE # = VIL)
Mode
Read
Notes
1,2,3
Output Disable
Standby
RP#
CE#
OE#
WE#
Ag
Ao
A-1
Vpp
DQO-7
DQS-14
X
X
X
VIH
VIL
VIL
VIH
X
DOUT
HighZ
VIH
VIL
VIH
VIH
X
X
X
X
HighZ
HighZ
VIH
VIH
X
X
X
X
X
X
HighZ
HighZ
VIL
X
X
X
X
X
X
X
HighZ
HighZ
X
89H
HighZ
Deep Power-Down
9
Intelligent Identifier
(Mfr)
4
VIH
VIL
VIL
VIH
VIO
VIL
X
Intelligent Identifier
(Device)
4,5
VIH
VIL
VIL
VIH
VIO
VIH
X
X
74H
75H
HighZ
6,7,8
VIH
VIL
VIH
VIL
X
X
X
X
DIN
HighZ
Write
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VPPL or VPPH for Vpp.
3. See DC characteristics for VPPL, VPPH, VHH, VID voltages.
4. Manufacturer and Device codes may also be accessed via a CPU write sequence. A1-A16 = VIL.
5. Device 10 = 2274H for 28F200BL-T and 2275H for 28F200BL·B.
6. Refer to Table 4 for valid DIN during a write operation.
7. Command writes for Block Erase or Word/Byte Write are only executed when Vpp = VpPH.
8. To write or erase the boot block, hold RP# at VHH.
9. RP# must be at GNO ±0.2V to meet the 1.2 p.A maximum deep power-down current.
10. The device 10 codes are identical to those of the 28F2100BX 5V versions and SmartVoltage equivalents.
I
4-281
28F200BL-TlB. 28F002BL-T IB
4.2 28F002BL BuS Operations
Table 3. Bus OperatIons
Mode
Read
Notes
RPf
CE#
OE#
WE#
As
Ao
Vpp
DQO-7
1,2,3
VIH
VIL
VIL
VIH
X
X
X
DOUT
.Output Disable
VIH
VIL
VIH
VIH
X
X
X
HighZ
Standby
VIH
VIH
X
X
X
X.
X
HighZ
Deep Power·Down
S
VIL
X
X
X
X
X
X
HighZ
Intelligent Identifier (Mfr)
4
VIH
VIL
VIL
VIH
VID
VIL
X
8SH
4,5
VIH
VIL
VIL
VIH
'itID
VIH
X
7CH
7DH
6,7,8
VIH
VIL
VIH
'itIL
X
X
X
DIN
Intelligent Identifier (Device)
Write
:
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL or VIH for control pins and addresses, VPPL or VPPH for Vpp.
3. See DC characteristics for VPPL, VPPH, VHH, VIO voltages.
.
4. Manufacturer and Device codes may also be accessed via a CUI .write sequence. Al-A17. = VIL..
5. Device 10 = 7CH for 2BF002BL·T and 7DH for 28F002BL·B.
6. Refer to Table 4 for valid DIN during a write operation.
7. Command writes for Block erase or byte program are only executed when Vpp = VPPH.
8. Program or erase the Boot bloCk by holding RP# at VHH.
g. RP # must be at GND' ± 0.2V to meet the 1.2 p.A maximum deep power·down current.
10. The device 10 codes are. identical to those of the 28F002BX 5V versions and SmartVoltage equivalents.
4.3 Read Operations
4.3.1.2 Input Control
The 2·Mbit flash family has three user read modes;
Array, Intelligent Identifier, and Status Register.
Status Register read mode will be discussed in detail
in the "Write Operations" section.
With WE # at logic-high level (VIH), input to the device is disabled. Data Input/Output pins (00[0:15]
or 00[0:7]) are controlled by OE#.
During power-up conditions(Vcc supply ramping), it
takes a maximum Cif 600 ns from VCC at 3.0V minimum to obtain valid data on the outputs.
4.3.2 INTELLIGENT IDENTIFIERS
4.3.1 READ ARRAY
If the' memory is not in the Read Array mode, it is
necessary to write the appropriate read mode command to the CUI. The 2-Mbit flash family has three
control functions, all of which must· be logically active, to obtain data at the outputs. Chip-Enable CE #
is the device selection control. Power-Down RP# is
the device power control. Output-Enable OE# is the
DATA INPUT/OUTPUT(DO[0:15] or 00[0:7]) direction control' and when active is used to drive data
from the selected memory on to the 110 bus.
28F200BL Products
The manufacturer and device codes are read via the
CUI or by taking the Ag pin to 12V. Writing SOH to
the CUI. places the device into Intelligent Identifier
read mode. A read of location OOOOOH outputs the
manufacturer's identification code; 008SH, and location 00001 H outputs the device code; 2274H for
28F200BL-T, 2275H for 28F200BL-B. When BYTE#
is at a logic low: only the lower byte of the above
signatures is' read and D01S/A-1 is a"don't care"
during Intelligent. Identifier mode. A read array command must be written to the CUI to return to the
read array mode. .
4.3.1.1 Output Control
With OE# at logic-high level (V1I.i), the output from
the'device is disabled and data input/output pins
(00[0:15] 'or 00[0:7]) aretri-stated. Data input is
then controlled by WE#.
4-282
I
28F200BL·T IB, 28F002BL·T IB
28F002BL Products
4.4.1 BOOT BLOCK WRITE OPERATIONS
The manufacturer and device codes are also read
via the CUI or by taking the A9 pin to 12V. Writing
90H to the CUI places the device into Intelligent
Identifier read mode. A read of location OOOOOH
outputs the manufacturer's identification code, 89H,
and location 00001H outputs the device code; 7CH
for 28F002BL-T, 7DH for 28F002BL-B.
In the case of Boot Block modifications (write and
erase), RP # is set to VHH = 12V typically, in addition to Vpp at high voltage. However, if RP# is not at
VHH when a program or erase operation of the boot
block is attempted, the corresponding status register
bit (Bit 4 for Program and Bit 5 for Erase, refer to
Table 5 for Status Register Definitions) is set to indicate the failure to complete the operation.
4.4 Write Operations
Commands are written to the CUI using standard microprocessor write timings. The CUI serves as the
interface between the microprocessor and the internal chip operation. The CUI can decipher Read Array, Read Intelligent Identifier, Read Status Register,
Clear Status Register, Erase and Program commands. In the event ofa read command, the CUI
simply points the read path at either the array, the
Intelligent Identifier, or the status register depending
on the specific read command given. For a program
or erase cycle, the CUI informs the write state machine that a write or erase has been requested. During a program cycle, the Write State Machine will
control the program sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase suspend.
After the Write State Machine has completed its
task, it will allow the CUI to respond to its full command set. The CUI will stay in the current command
state until the microprocessor issues another command.
The CUI will successfully initiate an erase or write
operation only when Vpp is within its voltage range.
Depending upon the application, the system designer may choose to make the Vpp power supply
switchable, available only when memory updates
are desired. The system designer can also choose
to "hard-wire" Vpp to 12V. The 2-Mbit flash family is
designed to accommodate either design practice. It
is recommended that RP# be tied to logical Reset
for data protection during unstable CPU reset function as described in the "Product Family Overview"
section.
I
4.4.2 COMMAND USER INTERFACE (CUI)
The Command User Interface (CUI) serves as the
interface to the microprocessor. The CUI points the
read/write path to the appropriate circuit block as
described in the previous section. After the WSM
has completed its task, it will set the WSM Status bit
to a "1", which will also allow the CU I to respond to
its full command set. Note that after the WSM has
returned control to the CUI, the CUI will remain in its
current state.
4.4.2.1 Command Set
Command
Codes
Device Mode
00
10
20
40
50
70
90
BO
DO
FF
Invalid/Reserved
Alternate Program Setup
Erase Setup
Program Setup
Clear Status Register
Read Status Register
Intelligent Identifier
Erase Suspend
Erase Resume/Erase Confirm
Read Array
4.4.2.2 Command Function Descriptions
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the 2-Mbit
flash family commands.
4-283
28F200BL-T IB, 28F002BL-T IB
Table 4 Command Definitions
Command
Bus
Notes
First Bus Cycle
Second Bus Cycle
Cycles
Req'd
8
Operation Address Data Operation Address Data
Write
X
2,4
Write
X
90H
Read
IA
liD
3
Write
X
70H
Read
X
SRD
50H
Read Array
1
1
Intelligent Identifier
3
Read Status Register
2
FFH
Clear Status Register
1
Write
X
Erase Setup/Erase Confirm
2
5
Write
BA
20H
Write
BA
DOH
Word/Byte Write
Setup/Write
2
6, 7
Write
WA
40H
Write
WA
WD
Erase Suspend/Erase Resume
2
Write
X
BOH
Write
X
DOH
Alternate Word/Byte Write
Setup/Write
2
Write
WA
10H
Write
WA
WD
2,3,7
NOTES:
1. Bus operations are defined in Tables 1, 2, 3..
2. IA = Identifier Address: OOH for manufacturer code, 01 H for device code.
S. SRD = Data read from Status Register.
4. 110 = Intelligent Identifier Data.
Following the Intelligent Identifier Command, two read operations access manufacturer and device codes.
5. BA = Address within the block being erased.
6. WA= Address to be written.
WD = Data to be written at location WA.
7. Either 40H or 10H commands is valid.
8. When writing commands to the device, the upper data bus [008-0015] = X (28F200BL-only) which is either Vee or Vss
to avoid burning additional current.
Invalid/Reserved
Read Status Register (70H)
These are unassigned commands. It is not recommended that the customer use any command other
than the valid commands specified above. Intel reserves the right to redefine these codes for future
functions ..
This is one of the two commands that is executable
while the state machine is operating. After this command is written, a read of the device will output the
contents of the status register, regardless of the address presented to the device.
Read Array (FFH)
The device automatically enters this mode after program or erase has completed.
This single write command points the read path at
the array. If the host CPU performs a CE#lOE#
controlled read immediately following a two-write sequence that started the WSM, then the device will
output status register contents. If the Read Array
command is given after Erase Setup the device is
reset to read the array. A two Read Array command
sequence (FFH) is required to reset t6 Read Array
after Program Setup.
Intelligent Identifier (90H)
After this command is executed, the CUI points the
output path to the Intelligent Identifier circuits. Only
Intelligent Identifier values at addresses 0 and 1 can
be read (only address AO is used in this mode, all
other address inputs are ignored).
4-284
Clear Status Register (SOH)
The WSM can only set the Program Status and
Erase Status bits in the status register, it can not
clear them. Two reasons exist for operating the
status register in this fashion. The first is a synchronization. The WSM does not know when the host
CPU has read the status register, therefore it would
not know when to clear the status bits. Secondly, if
the CPU is programming a string of bytes, it may be
more efficient to query the status register after programming the string. Thus, if any errors exist while
programming the string, the status register will return
the accumulated error status.
I
28F200BL·T IB, 28F002BL·T IB
Program Setup (40H or 10H)
This command simply sets the CUI into a state such
that the next write will load the address and data
registers. Either 40H or 10H can be used for Program Setup. Both commands are included to accommodate efforts to achieve an industry standard
command code set.
Program
The second write after the program setup command,
will latch addresses and data. Also, the CUI initiates
the WSM to begin execution of the program algorithm. While the WSM finishes the algorithm, the device will output Status Register contents. Note that
the WSM cannot be suspended during programming.
Erase Setup (20H)
Prepares the CUI for the Erase Confirm command.
No other action is taken. If the next command is not
an Erase Confirm command then the CUI will set
both the Program Status and Erase Status bits of the
Status Register to a "1", place the device into the
Read Status Register state, and wait for another
command.
Erase Confirm (DOH)
If the previous command was an Erase Setup command, then the CUI will enable the WSM to erase, at
the same time closing the address and data latches,
and respond only to the Read Status Register and
Erase Suspend commands. While the WSM is executing, the device will output Status Register data
when OE # is toggled low. Status Register data can
only be updated by toggling either OE# or CE# low.
Erase Suspend (BOH)
This command only has meaning while the WSM is
executing an Erase operation, and therefore will only
be responded to during an erase operation. After
this command has been executed, the CUI will initiate the WSM to suspend Erase operations, and then
return to responding to only Read Status Register or
to the Erase Resume commands. Once the WSM
has reached the Suspend state, it will set an output
into the CUI which allows the CUI to respond to the
Read Array, Read Status Register, and Erase Resume commands. In this mode, the CUI will not respond to any other commands. The WSM will also
I
set the WSM Status bit to a "1". The WSM will continue to run, idling in the SUSPEND state, regardless
of the state of all input control pins, with the exclusion of RP#. RP# low will immediately shut down
the WSM and the remainder of the chip.
Erase Resume (DOH)
This command will cause the CUI to clear the Suspend state and set the WSM Status bit to a "0", but
only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.
4.4.3 STATUS REGISTER
The 2-Mbit flash family contains a status register
which may be read to determine when a program or
erase operation is complete, and whether that operation completed successfully. The status register
may be read at any time by writing the Read Status
command to the CUI. After writing this command, all
subsequent Read operations output data from the
status register until another command is written to
the CUI. A Read Array command must be written to
the CUI to return to the Read Array mode.
The status register bits are output on 00[0:7]
whether the device is in the byte·wide (x8) or wordwide (x16) mode for the 28F200BL. In the word-wide
mode the upper byte, 00[8:15] is set to OOH during
a Read Status command. In the byte-wide mode,
00[8:14] are tri-stated and D015/A-1 retains the
low order address function.
It should be noted that the contents of the status
register are latched on the falling edge of OE# or
CE # whichever occurs last in the read cycle. This
prevents possible bus errors which might occur if the
contents of the status register change while reading
the status register. CE# or OE# must be toggled
with each subsequent status read, or the completion
of a program or erase operation will not be evident.
The Status Register is the interface between the microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate
the status of the WSM, and will also hold the bits
indicating whether or not the WSM was successful in
performing the desired operation. The WSM sets
status bits "Three" through "Seven" and clears bits
"Six" and "Seven", but cannot clear status bits
"Three" through "Five". These bits can only be
cleared by the controlling CPU through the use of
the Clear Status Register command.
4-285
28F200BL-T IB, 28F002BL-T IB
4.4.3.1 Status Register Bit Definition
Table 5. Status Register Definitions
I WSMS lESS
7
6
ES
5
R
4
3
2
R
o
NOTES:
SR.? = WRITE STATE MACHINE STATUS
1 = Ready
o = Busy
Write State Machine Status bit must first be checked to
determine byte/word program or block erase completion,
before the Program or Erase Status bits are checked for
success.
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
o = Erase in Progress/Completed
When Erase -Suspend is issued, WSM halts execution
and sets both WSMS and ESS bits to "1 ". ESS bit remains set to "1" until an Erase Resume command is issued.
SR.5 = ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Erase
When this bit is set to "1". WSM has applied the maximum number of erase pulses to the block and is still unable to successfully perform an erase verify.
SRA = PROGRAM STATUS
1 = Error in Byte/Word Program
o = Successful Byte/Word Program
When this bit is set to "1", WSM has attempted but failed
to Program a byte or word.
SR.3 = Vpp STATUS
1 = Vpp Low Detect; Operation Abort
0= Vpp OK
The Vpp Status bit unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM interrogates the ypp level only after the byte write or block
erase command sequences have been entered and informs the system if Vpp has not been switched on. The
Vpp Status bit is not guaranteed to report accurate feedback between VPPL and VPPH.
SR.2-SR.O = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be masked out when polling the Status Register.
4.4.3.2 Clearing the Status Register
4.4.4 PROGRAM MODE
Certain bits in the status register are set by the write
state machine,and can only be reset by the system
software. These bits can indicate various failure conditions. By allowing the system software to control
the resetting of these bits, several operations may
be performed (such as cumulatively programming
several bytes or erasing multiple blocks in sequence). The status register may then be read to
determine if an error occurred during that programming or erasure series. This adds flexibility to the
way the device may be programmed or erased. To
clear the status register, the Clear Status Register
command is written to the CUI. Then, any other command may be issued to .the CUI. Note again that
before a read cycle can be initiated, a Read Array
command must be written to the CUI to specify
whether the read data is to come from the array,
status register, or Intelligent Identifier.
Program is executed by a two-write sequence. The
Program Setup command is written to the CUI followed by a second write which specifies the address
and data to be programmed. The write state machine will execute a sequence of internally timed
events to:
1. program the desired bits of the addressed memory word (byte), and
2. verify that the desired bits are sufficiently programmed.
4-286
Programming of the memory results in specific bits
within a byte or word being changed to a "0".
If the user attempts to program "1 "s, there will be no
change of the memory cell content and no error occurs.
I
28F200BL-T IB, 28F002BL-T IB
Similar to erasure, the status register indicates
whether programming is complete. While the program sequence is executing, bit 7 of the status register is a "0". The status register can be polled by
toggling either CE # or OE # to determine when the
program sequence is complete. Only the Read
Status Register command is valid while programming is active.
When programming is complete, the status bits,
which indicate whether the program operation was
successful, should be checked. If the programming
operation was unsuccessful, Bit 4 of the status register is set to a "1" to indicate a Program Failure. If
Bit 3 is set then Vpp was not within acceptable limits,
and the WSM will not execute the programming sequence.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, it
must be recognized that reads from the memory,
status register, or Intelligent Identifier cannot be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 12 shows a system software flowchart for device byte programming operation. Figure 13 shows a
similar flowchart for device word programming operation (28F200BL-only).
4.4.5 ERASE MODE
Erasure of a single block is initiated by writing the
Erase Setup and Erase Confirm commands to the
CUI, along with the addresses, A[12:16] for the
28F200BL or A[12:17] for the 28F002BL, identifying
the block to be erased. These addresses are latched
internally when the Erase Confirm command is issued. Block erasure results in all bits within the block
being set to "1".
The WSM will execute a sequence of internally
timed events to:
1. program all bits within the block
2. verify that all bits within the block are sufficiently
programmed
3. erase all bits within the block and
4. verify that all bits within the block are sufficiently
erased
While the erase sequence is executing, Bit 7 of the
status register is a "0".
When the status register indicates that erasure is
complete, the status bits, which indicate whether the
erase operation was successful, should be checked.
I
If the erasure operation was unsuccessful, Bit 5 of
the status register is set to a "1" to indicate an
Erase Failure. If Vpp was not within acceptable limits
after the Erase Confirm command is issued, the
WSM will not execute an erase sequence; instead,
Bit 5 of the status register is set to a "1" to indicate
an Erase Failure, and Bit 3 is set to a "1" to identify
that Vpp supply voltage was not within acceptable
limits.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after erasure is completed; however, it must
be recognized that reads from the memory array,
status register, or Intelligent Identifier can not be accomplished until the CUI is given the appropriate
command. A Read Array command must first be given before memory contents can be read.
Figure 14 shows a system software flowchart for
Blocl< Erase operation.
4.4.5.1 Suspending and Resuming Erase
Since an erase operation typically requires 2 to 5
seconds to complete, an Erase Suspend command
is provided. This allows erase-sequence interruption
in order to read data from another block of the memory. Once the erase sequence is started, writing the
Erase Suspend command to the CUI requests that
the Write State Machine (WSM) pause the erase sequence at a predetermined point in the erase algorithm. The status register must be read to determine
when the erase operation has been suspended.
At this point, a Read Array command can be written
to the CUI in order to read data from blocks other
than that which is being suspended. The only other
valid command at this time is the Erase Resume
command or Read Status Register operation.
Figure 15 shows a system software flowchart detailing the operation.
During Erase Suspend mode, the chip can go into a
pseudo-standby mode by taking CE# to VIH and the
active current is now a maximum of 6 mA. If the chip
is enabled while in this mode by taking CE# to VIL,
the Erase Resume command can be issued to resume the erase operation.
Upon completion of reads from any block other than
the block being erased, the Erase Resume command must be issued. When the Erase Resume
command is given, the WSM will continue with the
erase sequence and complete erasing the block. As
with the end of erase, the status register must be
read, cleared, and the next instruction issued in order to continue.
4-287
28F200BL·T IB, 28F002BL·T IB
4.4.6 EXTENDED CYCLING
Intel has designed extended cycling capability into
its ETOX III flash memory technology. The 2-Mbit
low voltage flash family is designed for 10,000 pro-
gram/erase cycles on each of the five blocks. The
combination of low electric fields, clean oxide processing and minimized oxide area per memory cell
subjected to the tunneling electric field, results in
very high cycling capability.
Bus
Operation
Command
Comments
Write
Setup
Program
Data = 40H
Address = Byte to be
programmed
Write
Program
Data to be programmed
Address = Byte to be
programmed
Read
Status Register Data.
Toggle OE # or CE #, to update
Status Register
Standby
,CheckSR.7
1 = Ready, 0
= Busy
Repeat for subsequent bytes.
Full status cl1eck can be done after each byte or after a
sequence of bytes.
290449-8
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
CheckSR.4
1 = Byte Program Error
Vpp Range
Error
Byto Program
Error
Commsnd
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290449-9
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 12. Automated Byte Programming Flowchart
4-288
I
28F200BL·T IB, 28F002BL·T IB
Bus
Operation
Command
Comments
Write
Setup
Program
Data = 40H
Address = Word to be
programmed
Write
Program
Data to be programmed
Address = Word to be
programmed
Read
Status Register Data.
Toggle DE;!! or CE;!! to update
Status Register
Standby
CheckSR.7
1 = Ready, 0 = Busy
Repeat for subsequent words.
Full status check can be done aiter each word or aiter a
sequence of words.
290449-10
Write FFH aiter the last word programming operation to
reset the device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Vpp Range
Error
Word Program
Error
Command
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
Check SR.4
1 = Word Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290449-11
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 13. Automated Word Programming Flowchart
I
4-289
28F200BL-T IB, 28F002BL-T IB
Bus
Operation
Comments
Command
Write
Setup
Erase
Data = 20H
Address = Within block to be
erased
Write
Erase
Data = DOH
Address = Within block to be
erased
Read
Status Register Data.
Toggle OE# or CE# to update
Status Register
Standby
CheckSR.7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.
290449-12
Write FFH after the last block erase operation to reset the
device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Vpp Range
Error
Command
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Error
Standby
Check SR.4,5
Both 1 = Command Sequence
Error
Block Erase
Standby
CheckSR.5
1 = Block Erase Error
Command Sequence
Error
SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
290449-13
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 14. Automated Block Erase Flowchart
4-290
I
intel®
28F200BL-T /B, 28F002BL-T /B
Bus
Operation
Write
Command
Erase
Suspend
Comments
Data = BOH
Read
Status Register Data.
ToggleOE# orCE# to
update Status Register
Standby
Check SR.7
1 = Ready
Standby
Check SR.6
1 = Suspended
Write
Read Array
Read array data from block
other than that being
erased.
Read
Write
Data = FFH
Erase Resume
Data
=
DOH
290449-14
Figure 15. Erase Suspend/Resume Flowchart
4.5 Power Consumption
4.5.1 ACTIVE POWER
With CE# at a logic-low level and RP# at a logichigh level, the device is placed in the active mode.
The device Icc current is a maximum of 22 rnA at
5 MHz.
4.5.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low powerfeature during active mode of operation. The 2-Mbit
flash family of products incorporate Power Reduction Control (PRC) circuitry which basically allows
the device to put itself into a low current state when
it is not being accessed. After data is read from the
I
memory array, PRC logic controls the device's power consumption by entering the APS mode where
typical Icc current is 0.8 rnA and maximum ICC current is2 rnA. The device stays in this static state with
outputs valid until a new memory location is read.
4.5.3 STANDBY POWER
With CE# at a logic~high level (VIH), and the CUI in
read mode, the memory is placed in standby mode
where the maximum ICC standby current is t 20 /LA
with CMOS input signals. The standby operation disables much of the device's circuitry and substantially
reduces device power consumption. The outputs
(DO[0:151 or DO[0:7]) are placed in a high-impedance state independent of the status of the OE #
signal. When the 2-Mbit flash family is deselected
during erase or program functions, the devices will
4-291
28F200BL-T IB, 28F002BL-T IB
continue to perform the erase or prvgram function
and consume program or erase active power until
program or erase is completed.
4.5.4 RESETIDEEP POWER-DOWN
The 2-Mbit flash family supports a typical Icc of
0.2 p.A in deep power-down mode. One of the target
markets for these devices is in portable equipment
where the power consumption of the machine is of
prime importance. The 2·Mbit flash family has a
RP# pin which places the device in the deep powerdown mode. When RP# is at a logic-low (GND
± 0.2V), all circuits are turned off and the device typically draws 0.2 p.A of Vee current.
During read modes, the RP# pin going low deselects the memory and places the output drivers in a
high impedance state. Recovery from the deep power-down state, requires a maximum of 600 ns to access valid data (tpHQV)'
During erase or program modes, RP# low will abort
either erase or program operation. The contents of
the memory are no longer valid as the data has been
corrupted by the RP# function. As in the read mode
above, all internal circuitry is turned off to achieve
the 0.2 p.A current level.
RP# transitions to VIL or turning power off to the
device will clear the status register.
The use of RP# during system reset is important
with automated writel erase devices. When the system comes out of reset, it expects to read from the
flash memory. Automated flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel's
Flash Memories allow proper CPU initialization following a system reset through the use of RP# input.
In this application, RP# is controlled by the same
RESET # signal that resets the system CPU.
A system designer must guard against spurious
writes for Vee voltages above VLKO when Vpp is
active. Since both WE # and CE # must be low for a
command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides
an added level of protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. Finally
the device is disabled until RP# is brought to VIH,
regardless of the state of its control inputs. This feature provides yet another level of memory protection.
4.7 Power Supply Decoupling
Flash memory's power switching characteristics require careful device decoupling methods. System
designers are interested in 3 supply current issues:
• Standby current levels (Ices)
• Active current levels (leeR)
• Transient peaks produced by falling and rising
edges of CE # .
Transient current magnitudes depend on the device
outputs' capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 p.F ceramic capacitor
connected between each Vee and GND, and between its Vpp and GND. These high frequency, lowinherent inductance capacitors should be placed as
close as possible to the package leads.
4.7.1 Vpp TRACE ON PRINTED CIRCUIT
BOARDS
Writing to flash memories while they reside in the
target system, requires special consideration of the
Vpp power supply trace by the printed circuit board
designer. The Vpp pin supplies the flash memory
cell's current for programming and erasing. One
should use similar trace widths and layout considerations given to the Vee power supply trace. Adequate Vpp supply traces and decoupling will decrease spikes and overshoots.
4.6 Power-Up Operation
The 2-Mbit flash family is designed to offer protection against accidental block erasure or programming during power transitions. Upon power-up the
2-Mbit flash family is indifferent as to which power
supply, Vpp or Vee, powers-up first. Power supply
sequencing is not required.
The 2-Mbit flash family ensures the CUI is reset to
the read mode on power-up.
In addition, on power-up the user must either drop
CE # low or present a new address to ensure valid
data at the outputs.
4-292
4.7.2 Vee. Vpp AND RP# TRANSITIONS
The CUI latches commands as issued by system
software and is not altered by Vpp or CE# transitions or WSM actions. Its state upon power-up, after exit from deep power·down mode or after Vee
transitions below VLKO (Lockout voltage), is Read
Array mode.
After any word/byte write or block erase operation is
complete and even after Vpp transitions down to
VPPL, the CUI must be reset to Read Array mode via
the Read Array command when accesses to the
flash memory are desired.
I
28F200BL-T IB, 28F002BL-T IB
5.0
OPERATING SPECIFICATIONS
NOTICE: This is a production data sheet. The specifications are subject to change without notice .
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Absolute Maximum Ratings
Operating Temperature
During Read ............... - 20·C to + 70·C(1)
During Block Erase and
Word/Byte Write ................... O·C to 70·C
Temperature Under Bias ........ - 200·C to
+ BO·C
Storage Temperature .......... - 65·C to + 125·C
Voltage on Any Pin
(except Vee, Vpp, Ag and RP#)
with Respect to GND ........ -2.0V to +7.0V(2)
Voltage on Pin RP# or Pin Ag
with Respect to GND ....... - 2.0V to 13.5V(2, 3)
Vpp Program Voltage with Respect
to GND during Block Erase
and Word/Byte Write ..... - 2.0V to + 14.0V(2, 3)
Vee Supply Voltage
with Respect to GND ........ -2.0V to +7.0V(2)
Output Short Circuit Current ............. 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vee + 0.5V which, during transitions, may overshoot to Vee + 2.0V
for periods < 20 ns.
3. Maximum DC voltage on Vpp may overshoot to + 14.0V for periods <20 ns. Maximum DC voltage on RP# or As may
overshoot to 13.5V for periods < 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
5. AC Specifications are valid at both voltage ranges. See DC Characteristics table for voltage range-specific specifications.
OPERATING CONDITIONS
Symbol
Parameter
Notes
Min
Max
Unit
+70
·C
TA
Operating Temperature
-20
Vce
VCC Supply Voltage
3.00
3.60
V
Vee
Vee Supply Voltage
4.50
5.50
V
DC CHARACTERISTICS
Symbol
5
Vcc = 3.3V ±0.3V Read, 3.15V-3.6V Program/Erase
Parameter
Notes
Min
Typ
Max
Unit
Test Condition
III
Input Load Current
1
±1.0
/LA
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage Current
1
±10
/LA
Vee = Vec Max
VOUT = Vee or GND
lees
Vec Standby Current
45
120
/LA
Vee = Vee Max
CE# = RP# = Vee ±0:2V
45
120
/LA
Vee = Vee Max
CEil = RP# = VIH
0.20
1.2
/LA
RP#
leeD
I
Vee Deep Power-down Current
1,3
1
= GND ±0.2V
4-293
28F200BL-T IB, 28F002BL-T IB
DC CHARACTERISTICS
Symbol
leeR
Vee = 3.3V ±0.3V Read, 3.15V-3.6V Program/Erase (Continued)
Parameter
Notes
Vee Read Current for
28F200BX-L Word-Wide and
Byte-Wide Mode and
28F002BX-L Byte-Wide Mode
1,5,
6
Min
Typ
Max
Unit
Test Condition
15
25
mA Vee = Vee Max, CE# = GND
f = 5 MHz, lOUT = 0 mA
CMOS Inputs
15
25
mA Vee = Vee Max, CE# = VIL
f = 5 MHz, lOUT = 0 mA
TTL Inputs
leew
Vee Word/Byte Write Current
1,4
30
mA Word/Byte Write in Progress
IeeE
Vee Block Erase Current
1,4
20
mA Block Erase in Progress
leeES
Vee Erase Suspend Current
1,2
6
mA Block Erase Suspended,
CE# = VIH
3
Ipps
Vpp Standby Current
1
±15
p.A Vpp ~ Vee
Ippo
Vpp Deep
Power-down Current
1
5.0
p.A RP#
IpPR
Vpp Read Current
1
200
p.A Vpp
Ippw
Vpp Word Write Current
1,4
40
mA Vpp = VPPH
Word Write in Progress
Ippw
Vpp Byte Write Current
1,4
30
mA Vpp = VPPH
Byte Write in Progress
IpPE
Vpp Block Erase Current
1,4
30
mA Vpp = VPPH
Block Erase in Progress
IpPES
Vpp Erase Suspend Current
1
200
p.A Vpp = VPPH
Block Erase Suspended
IRP#
RP# Boot Block
Unlock Current
1,4
500
p.A RP#
1,4
500
p.A Ag
110
Ag Intelligent Identifier Current
VIO
Ag Intelligent Identifier Voltage
11.4
VIL
Input Low Voltage
VIH
Input High Voltage
V.QL
Output Low Voltage
VOH1
Output High Voltage (TTL)
VOH2
Output High Voltage
(CMOS)
12.0
= VHH
= VID
V
-0.5
0.6
V
2.0
Vee + 0.5
V
0.4
V
Vee = Vee Min
IOL = 2 mA
2.4
V
Vee = Vee Min
IOH = -2mA
0.85 Vee
V
IOH = -2.5 mA
Vee = Vee Min
VPPL
Vpp during Normal Operations
VPPH
Vpp during Erase/Write
Operations
VLKO
Vee Erase/Write Lock Voltage
2.0
VHH
RP# Unlock Voltage
11.4
4-294
> Vee
13.0
IOH = -2.5 mA
Vee = Vee Min
Vee- O.4 .
3
= GND ±0.2V
0.0
11.4
4.1
V
12.0
12.6
V
12.0
13.0
V
V
Boot Block Write/Erase
I
28F200BL-T IB, 28F002BL-T IB
CAPACITANCE(4) TA = 25°C,f = 1 MHz
Symbol
Typ
Max
Unit
CIN
Input Capacitance
6
8
pF
VIN = OV
COUT
Output Capacitance
10
12
pF
VOUT = OV
Parameter
Condition
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 3.3V, VPP = 12.0V, T = 25'e. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the device is read while in Erase Suspend Mode, current draw is the sum
of ICCES and ICCR.
3. Block Erases and Word/Byte Writes are inhibited when Vpp = VPPL and not guaranteed in the range between VPPH and
VPPL·
.
4. Sampled, not 100% tested.
. 5. Automatic Power Savings (APS) reduces ICCR to less than 1 rnA in static operation.
6. CMOS Inputs are either Vcc ±0.2V or GND ±0.2V. TTL Inputs are either VIL or VIH.
DC CHARACTERISTICS Vee
= 5.0V ±10%(4)
Mal(
Unit
III
Input Load Current
1
±1.0
}J-A
Vee = Vee Max
VIN = Vcc or GND
ILO
Output Leakage Current
1
±10
}J-A
Vce = Vce Max
VOUT = Vec or GND
Ices
Vee Standby Current
1.5
rnA
Vec = Vee Max
CE# = RP# = VIH
100
}J-A
Vec = Vee Max
CE# = RP# = Vec ±0.2V
Symbol
Parameter
Notes
Min
Typ
Test Condition
=
ICCD
Vce Deep Power-down
Current
1
1.2
}J-A
RP#
ICCR
Vcc Read Current for
28F200BL Word-Wide and
Byte-Wide Mode and
28F002BL
1
40
rnA
Vce = Vce Max, CE# = GND
f = 5 MHz, lOUT = 0 rnA
CMOS Inputs
40
rnA
Vee = Vec Max, CE# = VIL
f = 5 MHz, lOUT = 0 rnA
TIL Inputs
rnA
rnA
rnA
Word or Byte Write in Progress
}J-A
}J-A
Vpp:5: Vcc
lecw
Vcc Word-Byte Write Current
1,4
70
lecE
Vee Block Erase Current
1,4
30
lecES
Vee Erase Suspend Current
1,2
10
Vpp Standby Current
1
±15
Vpp Deep Power-down
Current
1
5.0
.Ipps
IpPD
I
GND ±0.2V
Block Erase in Progress
Block Erase Suspended,
CE# = VIH
RP#
=
GND ±0.2V
4-295
.28F200BL-T IB, 28F002BL-TIB
DC CHARACTERISTICS vee
Symbol
= 5.0V
Parameter
± 10% (Continued)
Notes
Min
Typ
Max
Unit
Test Condition
IpPR
VPP Read Current
1
200
p.A Vpp> Vee
Ippw
Vpp Word Write Current
1,4
40
mA Vpp = VpPH
Word Write in Progress
Ippw
Vpp Byte Write Current
1,4
30
mA Vpp = VPPH
Byte Write in Progress
IpPE
VPP Block Erase Current
1,4
30
mA VPP = VPPH
Block Erase in Progress
IpPES
VPP Erase Suspend Current
1
200
p.A VPP = VpPH
Block Erase Suspended
IRP#
RP# Boot Block Unlock Current
1,4
500
p.A RP#
1,4
500
p.A A9
110
A9 Intelligent Identifier Current
VIO
A9 Intelligent Identifier Voltage
11.4
VIL
Input Low Voltage
Input High Voltage
VIH
. VOL
12.0
Output High Voltage (TTL)
VOH2
Output High Voltage
(CMOS)
V
-0.5
0.8
V
2.0
Vee + 0.5
V
0.45
V
Vee = Vee Min
IOL = 5.8mA
2.4
V
Vee = Vee Min
IOH = -2.5 mA
0.85 Vee
V
IOH = -2.5 mA
Vee = Vee Min
IOH = -100 p.A
Vee = Vee Min
Vee- 0.4
-.
3
= VIO
13.0
Output Low Voltage
VOH1
= VHH
0.0
VPPL
VPP during Normal Operations
VPPH
Vpp during Erase/Write
Operations
VLKO
Vee Erase/Write Lock Voltage
2.2
VHH
RP# Unlock Voltage
11.4
11.4
6.5
V
12.0
12.6
V
12.0
13.0
V
V
Boot Block Write/Erase
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, VPP = 12.0V. T = 25·e. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the device is read while in Erase Suspend Mode, currerit draw is the sum
of ICCES and ICCR.
3. Block Erase/Byte Writes are inhibited when VPP = VPPL and not guaranteed in the range between VpPH andVpPL.
4. All parameters are sampled, not 100% tested.
4·296
I
28F200BL-T /B, 28F002BL-T /B
AC INPUT/OUTPUT REFERENCE WAVEFORM
AC TESTING LOAD CIRCUIT
1.3V
-r-
-fJ~
lN914
.
fCt
Rt.
DEVICE
UNDER
TEST
290449-15
AC test inputs are driven at 3.0V for a Logic "1" and O.OV for a logic "0".
Input timing begins, and output timing ends, at 1.5V. Input rise and fall times
(10% to 90%) < 10 ns.
OUT
-
290449-16
CL = 50 pF
CL Includes Jig Capacitance
RL = 3.3 Kn
AC CHARACTERISTICS-Read-Only Operations(1)vcc
28F200BL-150
28FOO2BL-150
Versions
Symbol
Parameter
Notes
tAVAV
tRC
Read Cycle Time
tAVQV
tAcc
Address to Output Delay
tCE
CE # to Output Delay
tELQV
= 3.3V ±0.3V, 5.0V ±10%(3)
Min
150
2
Unit
Max
ns
150
ns
150
ns
600
ns
65
ns
tpHQV
tpWH
RP# High to Output Delay
tGLQV
tOE
OE # to Output Delay
2
tELQX
tLZ
CE # to Output Low
Z
3
tEHQZ
tHZ
CE# High to Output High Z
3
tGLQX
tOLZ
OE # to Output Low Z
3
tGHQZ
tOF
OE# High to Output High
tOH
Output Hold from Addresses,
CE # or OE # Change,
Whichever is First
3
tELFL
tELFH
CE# to BYTE# Switching
LoW to High
3
5
ns
tFHQV
BYTE # Switching High
to Valid Output Delay
3,4
150
ns
tFLQZ
BYTE # Switching Low
to Output High Z
3
45
ns
.
Z
0
ns
55
0
3
ns
ns
45
0
ns
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE # may be delayed up to tCE-tOE after the falling edge of CE # without impact on tCE'
3. Sampled, not 100% tested.
4. tFLQV, BYTE# switching low to valid output delay will be equal to tAVQV, measured from the time OQ1s/A-1 becomes
valid.
.
I
4-297
N
.j>.
N
Q)
CD
VCC POWER-UP
'00","" 'M :,:
,H
CE# (E) V
...!71
(I
)0
OUTPUTS ENABLED
DATA VALID
STANDBY
Q
Q
Vec POWER-DOWN
---
>
0
I\)
::eDI
<
....
0
CE# (E)
en
....
0
OE# (G)
eD
WE# (w)
o
o
I\)
VIL
OJ
~OJ
II)
...3
VIH
...DI
::e
:l.
VIL
VIH
DI
VIL
:::J
Q.
...DI
m
en
II)
0
"!....
II)
VIH
DATA (0/0)
VIL
o·
:::J
en
im
00""
-..
VHH
6.SV
VIH
RP# (p)
:::J
VIL
2-
iD
Q.
VpPH
.::e
;::;:
II)
.!.
-
VPP (V)
!--c---l
_.
\YPWH
VpPL
VIH
VIL
.290449-18
cf
®
28F200BL-T IB, 28F002BL-T IB
AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS
vcc = 3.15V-3.6V, 5.0V ±10%
28F200BL·150
28FOO2BL·150
Versions
Symbol
Parameter
Notes
Min
Unit
Max
tAVAV
twc
Write Cycle Time
150
ns
tpHEl
tps
RP# High Recovery to CE# Going Low
1
J-Ls
tWlEl
tws
WE# Setup to CE# Going Low
0
ns
tpHHEH
tpHS
RP# VHH Setup to CE# Going High
6,8
200
ns
tVPEH
tvps
VPP Setup to CE# Going High
5,8
200
ns
tAVEH
tAS
Address Setup to CE# Going High
3
95
ns
tOVEH
tos
Data Setup to CE# Going High
4
100
ns
tELEH
tcp
CE # Pulse Width
100
ns
tEHOX
tOH
Data Hold from CE# High
4
0
ns
tEHAX
tAH
Address Hold from CE# High
3
10
ns
tEHWH
tWH
WE# Hold from CE# High
10
ns
tEHEl
tCPH
CE# Pulse Width High
50
ns
tEHOV1
Duration of Word/Byte Programming
Operation (Boot)
2,5,6
6
J-Ls
tEHOV2
Duration of Erase Operation (Boot)
2,5,6
0.3
s
tEHOV3
Duration of Erase Operation (Parameter)
2,5,6
0.3
s
tEHOV4
Duration of Erase Operation (Main)
2,5,6
0.6
s
tOWl
tOVPH
tpHBR
tVPH
VPP Hold from Valid SRD
5,8
0
ns
tpPH
RP# VHH Hold from Valid SRD
6,8
0
ns
Boot-Block Relock Delay
7
200
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE# in systems where
CE# defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# time should be
measured relative to the CE # waveforms.
2, 3, 4, 5, 6, 7, 8: Refer to AC characteristics for WE # -controlled write operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
characteristics during read mode.
I
4-303
"'0c'.":,
"'"
N
CD
Vee POWER-UP
WRITE PROGRAM OR
& STANDBY
ERASE SETUP COMMAND
"'1'1
iFi
.,C
CD
-"
!D
>
;:;
CD
!I
WRITE
VALID ADDRESS & DATA (PROGRAM)
OR ERASE CONfiRM COMMAND
AUTOMATED PROGRAM
OR ERASE DELAY
READ STATUS
REGISTER DATA
~
o
o
WRITE READ ARRAY
COMMAND
m
V1H
ADDRESSES (A)
~N
XI
~
~N
V1L
,!II
V1H
N
CD
"TI
o
o
WE# (w)
N
m
V1L
0
II
3
~
.....
V1H
m
OE# (G)
V1L
til
~I
CD
,-
%:HQVI.2.3.4
-,
V1H
CE# (E)
V1L
III
::J
Q.
iil
til
ml
CD
0
-a
V1H
DATA (0/0)
V1L
.,
CD
III
=:
0
::J
til
'0
m
~
00
.,3-
2-
f" "'HHEH
VHH
6.5V
V1H
RP# (p)
-I
.
V1L
t VPEH
VpPH
--
iii
Q.
=e
:::!.
CD
~
V (V) VpPL
PP
V1H
:l
V1L
290449-19
c[
@)
28F200BL-T IB, 28F002BL-T IB
ORDERING INFORMATION
IE121alr1210101BILI-IL1115101
~KAGE
E = STANDARD 56 LEAD TSOP
PA = 44 LEAD PSOP
Y~ESS
I
SPEED (ns)
150ns
BOOT BLOCK LOCATION
T TOP BOOT
B = BOTTOM BOOT
IE121alr1010121BILI-IL1115101
~KAGE
E = STANDARD 40 LEAD TSOP
=
Order
Number
SPEED (ns)
150 ns
BOOT BLOCK LOCATION
T = TOP BOOT
B BOTTOM BOOT
=
290449-20
VALID COMBINATIONS:
E28F200BL-T150 PA28F200BL-T150
E28F200BL-B150 PA28F200BL-B150
Y~ESS
I
290449-21
VALID COMBINATIONS:
E28F002BL-T150
E28F002BL-B 150
Document
292130
AB-57 "Boot Block Architecture for Safe Firmware Updates"
292154
AB-60 "2/4/8- Mbit smartVoltage Boot Block Flash Memory Family"
292098
AP-363 "Extended Flash BIOS Concepts for Portable Computers"
292148
AP-604 "Using Intel's Boot Block Flash Memory Parameter Blocks to Replace EEPROM"
290448
28F002/200BX-T IB 2-Mbit Boot Block Flash Memory Datasheet
290450
28F004/400BL-T/B 4-Mbit Low Power Boot Block Flash Memory Datasheet
290451
28F004/400BX-T IB 4-Mbit Boot Block Flash Memory Datasheet
290531
. 2-Mbit smartVoltage Boot Block Flash Memory Family Datasheet
290530
4-Mbit smartVoltage Boot Block Flash Memory Family Datasheet
290539
8-Mbit smartVoltage Boot Block Flash Memory Family Datasheet
I
4-305
28F200BL-T IB, 28F002BL-T IB
REVISION HISTORY
Number
Description
-001
Original Version
-002
Modified BYTE # AC Timings
Modified tOVWH parameter for AC Characteristics for Write Operations
-003
PWD renamed toRP# for JEDEC standardization compatibility.
Combined Vee Read Current for 28F200BX-L Word-Wide and Byte-Wide Mode and
28F002BX-L Byte-Wide Mode in DC Characteristics tables.
Changed Ipps current spec from ± 10 pA to ± 15 p.A in DC Characteristics table.
Added Boot Block Unlock current spec in DC Characteristics tables.
Improved tpwHspec to SOO ns (was 700 ns)
Changed ICCR current spec from 20 mA maximum to 25 mA maximum and added typical spec
to DC Characteristics table.
-004
Added IOH CMOS Specification.
Expanded temperature operating range, from 0·C-70·C to - 20· - + 70·C.
Product naming changed:
28F200BX-TL/BL changed to 28F200BL-TIB
28F002BX-TLlBL chang'8d to 28F002BL-T IB
Typographical errors corrected.
Added 28F400BX interface to Intel38STM EX Embedded Processor Block Diagram.
Added upgrade considerations for SmartVoltage Boot Block products.
Previously specified Vcc tolerance of 3.0V to 3.SV for Read, Program and Erase has been
changed to 3.15V to 3.SV for Program and Erase operation, while the Read operation remains
3.0V to 3.SV.
4-30S
"
I
28F001 BX-T128F001 BX-B
1M (128K x 8) CMOS FLASH MEMORY
•
High Integration Blocked Architecture
-One 8 KB Boot Block w/Lock Out
- Two 4 KB Parameter Blocks
- One 112 KB Main Block
•
High-Performance Read
-70175 ns, 90 ns, 120 ns, 150 ns
Maximum Access Time
-5.0V ± 10% Vee
•
100,000 Erase/Program Cycles Per
Block
•
•
•
Hardware Data Protection Feature
- Erase/Write Lockout during Power
Transitions
•
Extended Temperature Options
Program and Erase
• -Simplified
Automated Algorithms via On-Chip
Write State Machine (WSM)
•
•
•
SRAM-Compatible Write Interface
Deep-Powerdown Mode
- 0.05 p,A lee Typical
- 0.8 p,A Ipp Typical
12.0V ± 5% Vpp
Advanced Packaging, JEDEC Pinouts
- 32-Pin PDIP
- 32-Lead PLCC, TSOP
ETOX II Nonvolatile Flash Technology
- EPROM-Compatible Process Base
- High-Volume Manufacturing
. Experience
Intel's 28F0018X-8 and 28F001 8X-T combine the cost-effectiveness of Intel standard flash memory with
features that simplify write and allow block erase. These devices aid the system designer by combining the
functions of several components into one, making boot block flash an innovative alternative to EPROM and
EEPROM or battery-backed static RAM. Many new and existing designs can take advantage of the
28F001 8X's integration of blocked architecture, automated electrical reprogramming, and standard processor
interface.
The 28F0018X-B and 28F001BX-T are 1,048,576 bit nonvolatile memories organized as 131,072 bytes of
8 bits. They are offered in 32-pin plastic DIP, 32-lead PLCC and 32-lead TSOP packages. Pin assignment
conform to JEDEC standards for byte-wide EPROMs. These devices use an integrated command port and
state machine for simplified block erasure and byte reprogramming. The 28F001 8X-T's block locations provide compatibility with microprocessors and microcontrollers that boot from high memory, such as Intel's
MCS-186 family, 80286, i386™, i486™, i860TM and 80960CA. With exactly the same memory segmentation,
the 28F001 BX-8 memory map is tailored for microprocessors and microcontrollers that boot from low memory,
such as Intel's MCS-51, MCS-196, 80960KX and 80960SX families. All other features are identical, and unless
otherwise noted, the term 28F0018X can refer to either device throughout the remainder of this document.
The boot block section includes a reprogramming write lock out feature to guarantee data integrity. It is
deSigned to contain secure code which will bring up the system minimally and download code to the other
locations of the 28F0018X. Intel's 28F0018X employs advanced CMOS circuitry for systems requiring highperformance access speeds, low power consumption, and immunity to noise. Its access time provides
no-WAlT-state performance for a wide range of microprocessors and microcontrollers. A deep-powerdown
mode lowers power consumption to 0.25 p.W typical through Vee, crucial in laptop computer, handheld instrumentation and other low-power applications. The RP# power control input also provides absolute data protection during system powerup or power loss.
Manufactured on Intel's ETOX process base, the 28F001 8X builds on years of EPROM experience to yield the
highest levels of quality, reliability, and cost-effectiveness.
November 1994
Order Number: 290406-006
4-307
28F001BX-T/28F001BX-B
r ......--l.---l-l-l.---
CE.
L,r--rJ+------
RP#
1+-+-4---- WE#
1+-......- - - - OE#
"o-At.
Y-DECODER
X-DECODER
Y-GATING
••
••
""
~~
~ffi
, ....
0
,,~
.. ::0
Ol
"
~"
~g
.,,"
~b
"'g
it.
Vpp
"
~"
'III- Vee
_GND
z
"
::0
290406-1
Figure 1. 28F001BX Block Diagram
Table 1. Pin Description
Symbol
Type
Name and Function
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally latched during
a write cycle.
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs data and commands during memory write
cycles; outputs data during memory, Status Register and Identifier read cycles. The
data pins are active high and float to tri-state off when the chip is deselected or the
outputs are disabled. Data is internally latched during a write cycle.
Ao-A16
DOo-D07
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers, decoders and
sense amplifiers. CE # is active low; CE # high deselects the memory device 'and
reduces power consumption to standby levels.
RP#
INPUT
POWERDOWN~ Puts the device in deep powerdown mode. RP# is active low;
RP# high gates normal operation. RP# = VHH allows programming of the boot
block. RP # also locks out erase or write operations when active low, providing data
protection during power transitions. RP# active resets internal automation. Exit
fromdeep powerdown sets device to Read Array mode.
OE#
INPUT
OUTPUT ENABLE: Gates the device's outputs through the data buffers during a
read cycle. OE # is active low. OE # = VHH (pulsed) allows programming of the·
boot block.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register and array blocks. WE #
is active low. Addresses and data are latched on the rising edge of the WE # pulse.
Vpp
I
ERASE/PROGRAM POWER SUPPLY for erasing blocks of the array or
programming bytes of 6ach block. Note: With Vpp < VPPL max, memory contents
cannot be altered.
Vee
DEVICE POWER SUPp,LY: (5V ± 10%)
GND
GROUND
4-308
I
28F001BX-T/28F001BX-B
28F010
Vpp
A'6
A,S
28F010
Vpp
Vee
A,.
WE'
A15
RPO
A'2
A7
A6
As
A4
A'2
A7
A3
A2
A,
A,
Ao
000
00,
002
GND
A,.
A"
A.
.
As
A,
A.
A"
DE'
VCC
WE#
NC
A'4
A'3
As
Ag
A11
OE#
A,
AIO
A,D
A,
CEO
CE#
007
006
DOS
004
003
Ao
DO-,
000
DO,
002
DO,
GND
DO,
DO,
DO.
290406-2
Figure 2. DIP Pin Configuration
28F010
A"
A.
A.
A'3
A14
NC
A"
A.
A.
28F010
o
4"
A'4
RP'
WE#
WE'
STANDARD PINOUT
Vee
Vee
32 LEAD TSO?
Bmm x 20mm
TOP VIEW
Vpp
Vpp
A15
4"
4"
A,.
A"
A7
A.
A,
A4
DE'
A,O
CEO
DO-,
DO,
DO,
DO.
DO,
GND
DO,
DO,
000
Ao
A,
E2aFO01 BX
A"
A7
As
A,
A4----~~
______________________________________________________________
~r_---
A,
A,
DE'
A10
CEO
D07
D06
DO,
D04
D03
GND
DO,
DO,
DOO
Ao
A,
A,
A3
290406-3
Figure 3. TSOP lead Configuration
I
4-309
28F001 BX·T/28F001 BX·B
28F010
28F001BX(128Kx8)
N28F001BX
32 LEAD PLCC
0.450"xO.550"
TOP VIEW
Ag -
1.,1OE#-
1.,0CE#-
DCJ----I>i
AI6
---1>1
28F001BX-T
DOo -D~
SYSTEM RESET#
RP#
WR#
WE#
RD#
OE#
UCS#
CE#
As - AIS
BOCSI
SYSTEM BUS
ZBFOO lBX-B
ADo - AD7
+--6-----1>1 DQo
SYSTEM RESET
RP#
- D07
-----.....,1>1 WE#
RD# -->..-------..
WR#
As-A,s
PSEN#
As - A, 5
Vee
_'1-_
)---I~OE#
-ooO-----M As - AI5
!
CE#
Vee
MCS#
A - A,
2 KxB
S
0 SRAM
CS#
WR#
WE#
RD#
OE#
Ao -A7
ADo - AD.,
*
'------+I
WR#
Do - D7
PSEN#
290406-5
Figure 5. 28F001BX-T in a 80C188 System
ADo - AD7
------1)1
As - AIO
WE#
;RK:~
Ao - A7
OE#
Do - D7
290406-6
Figure 6. 28F001BX-B in a 80C51 System
I
4-311
28F001BX·T/28F001BX·B
PRINCIPLES OF OPERATION
Data Protection
The 28F0018X introduces on-chip write automation
to manage write and erase functions. The write state
machine allows for: 100% TTL-level control inputs;
fixed power supplies during erasure and programming; minimal processor overhead with RAM-like
write timings, and maximum EPROM compatiblity.
Depending on the application, the system deSigner
may choose to make the Vpp power supply switchable (available only when memory updates are required) or hardwired to VPPH. When Vpp = VPPL,
memory contents cannot be altered. The 28F001 BX
Command Register architecture provides protection
from unwanted program or erase operations even
when high voltage is applied to Vpp. Additionally, all
functions are disabled whenever Vee is below the
write lockout voltage VLKO, or when RP# is at V,L.
The 28F001 BX accommodates either design practice and encourages optimization of the processormemory interface.
After initial device powerup, or after return from
deep powerdown mode (see Bus Operations), the
28F001 BX functions as a read-only memory. Manipulation of external memory-control pins yield standard EPROM read, standby, output disable or Intelligent Identifier operations. Both Status Register and
Intelligent Identifiers can be accessed through the
Command Register when Vpp = VpPL.
This same subset of operations is also available
when high voltage is applied to the Vpp pin. In addi- .
tion, high voltage on Vpp enables successful erasure
and programming of the device. All functions associated with altering memory contents-program,
erase, status, and inteligent Identifier-are accessed
via the Command Register and verified through the
Status Register.
Commands are written using standard microprocessor write timings. Register contents serve as input to
the WSM, which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for programming or erase
operations. With the appropriate command written to
the register, standard microprocessor read timings
output array data, access the intelligent identifier
codes, or output program and erase status for verification.
Interface software to initiate and poll progress of internal program and erase can be stored in any of the
28F001 BX blocks. This code is copied to, and executed from, system RAM during actual flash memory
update. After successful completion of program
and/ or erase, code execution out of the 28F001 BX
is again possible via the Read Array command.
Erase suspend/resume capability allows system
software to suspend block erase and read data/execute code from any other block.
The two-step program/ erase write sequence to the
Command Register provides additional software
write protection.
1FFFF
a-KByle BOOT BLOCK
1EOOO
1DFFF
1DOOO
1CFFF
1COOO
1BFFF
4-312
4-KByle PARAMETER BLOCK
112-KByte MAIN BLOCK
00000
Figure 7_ 28F001BX·T Memory Map
1FFFF
112-KByte MAIN BLOCK
Command Register and Write
Automation
An on-chip state machine controls block erase and
byte program, freeing the system processor for other
tasks. After receiving the erase setup and erase
confirm commands, the state machine controls
block pre-conditioning and erase, returning progress
via the Status Register. Programming is Similarly
controlled, after destination address and expected
data are supplied. The program algorithm of past Intel Flash Memories is now regulated by the state
machine, including program pulse repetition where
required and internal verification and margining of
data.
4-KBy1e PARAMETER BLOCK
04000
03FFF
03000
02FFF
02000
01FFF
4-KBy1e PARAMETER BLOCK
4-KByte PARAMETER BLOCK
a-KByte BOOT BLOCK
00000
Figure 8_ 28F001BX·B Memory Map
I
28F001 BX-T/28F001 BX-B
BUS OPERATION
Standby
Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
CE # at a logic-high level (VIH) places the 28F001 ex
in standby mode. Standby operation disables much
of the 28F001 ex's circuitry and substantially reduces device power consumption. The outputs (000007) are placed in a high-impedance state independent of the status of OE#. If the 28F001BX is deselected during erase or program, the device will
continue functioning and consuming normal active
power until the operation is completed.
Read
The 28F001 ex has three read modes. The memory
can be read from any of its blocks, and information
can be read from the Intelligent Identifier or the
Status Register. Vpp can be at either VPPL or VPPH.
Deep Power-Down
The first task is to write the appropriate read mode
command to the Command Register (array, Intelligent Identifier, or Status Register). The 28F001 ex
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown.
The 28F001 ex has four control pins, two of which
must be logically active to obtain data at the outputs.
Chip Enable (CE#) is the device selection control,
and when active enables the selected memory device. Output Enable (OE#) is the data input/output
(000-007) direction control, and when active
drives data from the selected memory onto the I/O
bus. RP# and WE# must also be at VIH. Figure 12
illustrates read bus cycle waveforms.
The 28F001 ex offers a 0.25 /J-W Vcc power-down
feature, entered when RP# is at VIL. During read
modes, RP# low deselects the memory, places output drivers in a high-impedance state and turns off
all internal circuits. The 28F001 ax requires time
tpHQV (see AC Characteristics-Read Only Operations) after return from power-down until initial mem, ory access outputs are valid. After this wakeup interval, normal operation is restored. The Command
Register is reset to Read Array, and the Status Register is cleared to value 80H, upon return to normal
operation.
During erase or program modes, RP# low will abort
either operation. Memory contents of the block being altered are no longer valid as the data will be
partially programmed or erased. Time tPHWL after
RP# goes to logic-high (VIH) is required before another command can be written.
Output Disable
With OE # at a logic-high level (VIH), the device outputs are disabled. Output pins (000-007) are
placed in a high-impedance state.
Table 2. 28F001BX Bus Operations
Mode
Read
Notes
1,2,3
RP#
CE#
OE#
WE#
Ag
Ao
Vpp
X
X
DOUT
DQO-7
VIH
VIL
VIL
VIH
X
Output Disable
VIH
VIL
VIH
VIH
X
X
X
HighZ
Standby
VIH
VIH
X
X
X
X
X
HighZ
VIL
X
X
X
X
X
X
HighZ
X
89H
Deep Power Down
Intelligent Identifier (Mfr)
Intelligent Identifier (Device)
Write
4
VIH
VIL
VIL
VIH
VID
VIL
4,5
VIH
VIL
VIL
VIH
VID
VIH
X
94H,95H
VIL
X
X
X
DIN
6,7,8
VIH
VIL
VIH
NOTES:
1. Refer to DC Characteristics. When Vpp = VPPL, memory contents can be read but not programmed or erased.
2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for Vpp.
3. See DC Characteristics for VPPlo VPPH, VHH and VID voltages.
4. Manufacturer and device codes may also be accessed via a Command Register write sequence. Refer to Table 3. Al-AS,
Al0-A16 = VIL·
5. Device ID = 94H for the 28F001BX-T and 95H for the 28F001BX-B.
6. Command writes involving block erase or byte program are successfully executed only when Vpp = VpPH.
7. Refer to Table 3 for valid DIN during a write operation.
8. Program or erase the boot block by holding RP# at VHH or toggling OE# to VHH. See AC Waveforms for program/erase
operations.
.
I
4-313
28F001BX-T/28F001BX-B
The use of RP# during system reset is important
with automated write/erase devices. When the system comes out of reset it expects to read from the
flash memory. Automated flash memories provide
status information when accessed during write/
erase modes. If a CPU reset occurs with no flash
memory reset, proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data. Intel's
Flash Memories allow proper CPU initialization following a system reset through the use of the RP#
input. In this application RP# is pontrolled by the
same RESET# signal that resets the system CPU.
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code, 89H; and the device code, 94H for the
28F001 BX-T and 95H for the 28F001 BX-B. Programming equipment or thl3 system CPU can then
automatically match the device with its proper erase
and programming algorithms.
PROGRAMMING EQUIPMENT
CE# and OE# at a logic low level (V,Ll, with A9 at
high voltage VID (see DC Characteristics) activates
this operation. Data read from locations OOOOOH and
00001 H represent the manufacturer's code and the
device code respectively.
IN-SYSTEM PROGRAMMING
The manufacturer- and device-codes can also be
read via the Command Register. Following a write of
90H to the Command Register, a read from address
location OOOOOH outputs the manufacturer code
(89H). A read from address 00001 H outputs the device code (94H forthe 28F001 BX-T and 95H for the
28F001 BX-B). It is not necessary to have high voltage applied to VPP to read the Intelligent Identifiers
from the Command Register.
Write
Writes to the Command Register allow read of device data and Intelligent Identifiers. They also control inspection and clearing of the Status Register.
Additionally, when Vpp = VPPH, the Command Register controls device erasure and programming. The
contents of the register serve as input to the internal
state machine.
The Command Register itself does not occupy an .
addressable memory location. The register is a latch
used to store the command and address and data
information needed to execute the command. Erase
4-314
Setup and Erase Confirm commands require both
appropriate command data and an address within
the block to be erased. The Program Setup Command requires both appropriate command data and
the address of the location to be programmed, while
the· Program command consists of the data to be
written and the address of the location to be programmed.
The Command Register is written by bringing WE #
to a logic-low level (VILl while CE# is low. Addresses and data are latched on the rising edge of WE # .
Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the AC Waveform for Write Operations, Figure 13, for specific timing parameters.
COMMAND DEFINITIONS
When VpPL is applied to the VPP pin, read operations from the Status Register, intelligent identifiers,
or array blocks are enabled. Placing VpPH on VPP
enables successful program and erase operations
as well ..
Device operations are selected by writing specific
commands into the Command Register. Table 3 defines these 28F001 BX commands.
Read Array Command
Upon initial device powerup and after exit from
deep-powerdown mode, the 28F001 BX defaults to
Read Array mode. This operation is also initiated by
writing FFH into the Command Register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the Command Register contents are altered. Once the internal write
state machine has started an erase or program operation, the device will not recognize the Read Array
command; until the WSM has completed its operation. The Read Array command is functional when
VPP = VPPL or VPPH·
Intelligent Identifier Command for
In-System Programming
The 28F001 BX contains an Intelligent Identifier operation to supplement traditional PROM-programming methodology. The operation is initiated by writing 90H into the Command Register. Following the
command write, a read cycle from address OOOOOH
retrieves the manufacturer code of 89H. A read cycle from address 00001 H returns the device code of
94H (28F001 BX-T) or 95H (28F001 BX-B). To terminate the operation, it is necessary to write another
valid command into thtl register. Like the Read Array
command, the intelligent Identifier command is functional when VPP = Vpp,_ or VPPH.
I
28FOO 1BX-T 128F001 BX-B
Table 3. 28F001BX Command Definitions
Command
Bus
Second Bus Cycle
First Bus Cycle
Cycles Notes
Req'd
Operation Address Data Operation Address Data
Write
X
2,3,4
Write
X
90H
Read
IA
110
3
Write
X
70H
Read
X
SRD
Write
X
SOH
Write
BA
20H
Write
BA
DOH
Write
X
BOH
Write
X
DOH
Write
PA
40H
Write
PA
PO
. Read Array/Reset
1
1
Intelligent Identifier
3
Read Status Register
2
Clear Status Register
1
Erase Setup/Erase Confirm
2
Erase Suspend/Erase Resume
2
Program Setup/Program
2
2
2,3
FFH
NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier Address: OOH for manufacturer code, 01 H for device code.
BA = Address within the block being erased.
PA = Address of memory location to be programmed.
3. SRD = Data read from Status Register. See Table 4 for a description of the Status Register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
liD = Data read from Intelligent Identifiers.
4. Following the Intelligent Identifier command, two read operations access manufacture and device codes.
5. Commands other than those shown above are reserved by Intel for future device implementations and should not be
used.
Read Status Register Command
The 28F001 BX contains a Status Register which
may be read to determine when a program or erase
operation is complete, and whether that operation
completed successfully. The Status Register may be
read at any time by writing the Read Status Register
command (70H) to the Command Register. After
writing this command, all subsequent read operations output data from the Status Register, until another valid command is written to the Command
Register. The contents of the Status Register are
latched on the falling edge of OE # or CE #, whichever occurs last in the read cycle. OE# or CE#
must be toggled to VIH before further reads to update the Status Register latch. The Read Status
Register command functions when Vpp = VPPL or
reset by the Clear Status Register command. These
bits indicate various failure conditions (see Table 4).
By allowing system software to control the resetting
of these bits, several operations may be performed
(such as cumulatively programming several bytes or
erasing multiple blocks in sequence). The Status
Register may then be polled to determine if an error
occurred during that series. This adds flexibility to
the way the device may be used.
Additionally, the Vpp Status bit (SR.3), when set to
"1 ", MUST be reset by system software before further byte programs or block erases are attempted.
To clear the Status Register, the Clear Status Register command (SOH) is written to the Command Register. The Clear Status Register command is functional when Vpp = VPPL or VPPH.
VPPH·
Clear Status Register Command
The Erase Status and Program Status bits are set to
"1" by the Write State Machine and can only be
I
4-315
28F001 BX-T128F001 BX-B
Table 4. 28F001BX Status Register Definitions
WSMS
ESS
ES
PS
VPPS
R
7·
6
5
4
3
2
SR.? = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
o = Erase In Progress/COmpleted
SR.5 = ERASE STATUS
1 = Error in Block Erasure
o = Successful Block Erase
SR.4 = PROGRAM STATUS
1 = .Error in Byte Program
o = Successful Byte Program
SR.3 = Vpp STATUS
1 = Vpp Low Detect; Operation Abort
0= Vpp OK
R
R
o
NOTES:
The Write State Machine Status Bit must first be checked
to determine program or erase completion, before the
Program or Erase Status bits are checked for success.
If the Program AND Erase Status bits are set to "1 s" .during an erase attempt, an improper command sequence
was entered. Attempt the operation again.
.
If Vpp low status is detected, the Status Register must be
cleared before another program or erase operation is attempted.
The Vpp Status bit, unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM interrogates the Vpp level only after the program or .erase
command sequences have been entered and informs the
system if Vpp has not been switched on. The Vpp Status
bit is not guaranteed to report accurate feedback between VPPL and VpPH·
SR.2-SR.O = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be
masked out when polling the Status Register.
Erase Setup/Erase Confirm
Commands
Erase is executed one block at a time, initiated by a
. two-cycle command sequence. An Erase Setup
command (20H) is first written to the Command
Register, followed by the Erase Confirm command
(DOH). These commands require both appropriate
command data and an address within the block to
be erased. Block preconditioning, erase and verify
are all handled internally by the Write State Machine,
invisible to the system. After receiving the two-command erase sequence, the 28F001 BX automatically
outputs Status Register data when read (see Figure
10; Block Erase Flowchart). The CPU can detect the
completion of the erase event by checking the WSM
Status bit of the Status Register (SA. 7).
When the Status Register indicates that erase is
complete, the Erase Status bit should be checked. If
. erase error is detected, the Status Register should
be cleared. The Command Register remains in Read
Status Register Mode until further commands are issued to it.
This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, block erasure can only occur
when Vpp = VPPH. In the absence of this high voltage, memory contents are protected against erasure. If block erase is attempted while Vpp = VPPL,
4-316
the Vpp Status bit will be set to "1". Erase attempts
while VpPL < Vpp < VPPH produce spurious results
and should not be attempted.
Erase Suspend/Erase Resume
Commands
The Erase Suspend Command allows erase sequence interruption in order to read data from another block of memory. Once the erase sequence is
started, writing the Erase Suspend command (BOH)
to the Command Register requests that the WSM
suspend the erase sequence at a predetermined
point in the erase algOrithm. The 28F001 BX continues to output Status Register data when read, after
the Erase Suspend command is written to it. Polling
the WSM Status and Erase Suspend Status bits will
determine when the erase operation has been suspended (both will be set to "1s").
At this point, a Read Array command can be written
to the Command Register to read data from blocks
other than that which Is suspended. The only other valid commands at this time are Read Status Register (70H) and Erase Resume (DOH), at which time
the WSM will continue with the erase sequence. The
Erase Suspend Status and WSM Status bits of the
. Status Register will be cleared. After the Erase Resume command is written to it, the 28F001 BX automatically outputs Status Register data when read
(see Figure 11; Erase Suspend/Resume Flowchart).
I
28F001BX-T/28F001BX-B
Program Setup/Program Commands
Programming is executed by a two-write sequence.
The program Setup command (40H) is written to the
Command Register, followed by a second write
specifying the address and data (latched on the rising edge of WE#) to be programmed. The WSM
then takes over, controlling the program and verify
algorithms internally. After the two-command program sequence is written to it, the 28F001 BX automatically outputs Status Register data when read
(see figure 9; Byte Program Flowchart). The CPU
can detect the completion of the program event by
analyzing the WSM Status bit of the Status Register.
Only the Read Status Register command is valid
while programming is active.
When 'the Status Register indicates that programming is complete, the Program Status bit should be
checked. If program error is detected, the Status
Register should be cleared. The internal WSM verify
only detects errors for "1s" that do not successfully
program to "Os". The Command Register remains in
Read Status Register mode until further commands
are issued to it. If byte program is attempted while
Vpp = VPPL, the Vpp Status bit will be set to "1".
Program attempts while VPPL < Vpp < VPPH produce spurious results and should not be attempted.
The 28F001BX-B and 28F001BX-T are capable of
100,000 program/erase cycles on each of the two
parameter blocks, main block and boot block.
ON-CHIP PROGRAMMING
ALGORITHM
The 28F001 BX integrates the Quick Pulse programming algorithm of prior Intel Flash Memory devices
on-chip, using the Command Register, Status Register and Write State Machine (WSM). On-chip integration dramatically simplifies system software and
provides processor-like interface timings to the
Command and Status Registers. WSM operation, internal program verify and Vpp high voltage presence
are monitored and reported via appropriate Status
Register bits. Figure 9 shows.a system software
flowchart for device programming. The entire sequence is performed with Vpp at VPPH. Program
abort occurs when RP# transitions to VIL, or Vpp
drops to VPPL. Although the WSM is halted, byte
data is partially programmed at the location where
programming was aborted. Block erasure or a repeat of byte programming will initialize this data to a
known value.
ON-CHIP ERASE ALGORITHM
EXTENDED ERASE/PROGRAM
CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubled; an
expensive solution.
Intel has designed extended cycling capability into
its EJOX flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electrical field is onetenth that of common EEPROMs, minimizing the
probability of oxide defects in the region. Finally, the
peak electric field during erasure is approximately 2
Mv/cm lower than EEPROM. The lower electric field
greatly reduces oxide stress and the probability of
failure; increasing time to wearout by a factor of
100,000,000.
I
As above, the Quick Erase algorithm of prior Intel
Flash Memory devices is now implemented intern,alIy, including all preconditioning of block data. WSM
operation, erase success and Vpp high voltage presence are monitored and reported through the Status
Register. Additionally, if a command other than
Erase Confirm is written to the device after Erase
Setup has been written, both the Erase Status and
Program Status bits will be set to "1". When issuing
the Erase Setup and Erase Confirm commands, they
should be written to an address within the address
range of the block to be erased. Figure 10 shows a
system software flowchart for block erase.
Erase typically takes 1 -4 seconds per block. The
Erase Suspend/Erase Resume command sequence
allows interrupt of this erase operation to read data
from a block other than that In which erase Is
being performed. A system software flowchart is
shown in Figure 11.
The entire sequence is performed with Vpp at VPPH.
Abort occurs when RP# transitions to VIL or Vpp
falls to VpPL, while erase is in progress. Block data is
partially erased by this operation, and a repeat of
erase is required to obtain a fully erased block.
4-317
28F001 BX-T128F001 BX-B
BOOT BLOCK PROGRAM AND
ERASE
The boot block is intended to contain secure code
which will minimally bring up a system and control
programming and erase of other blocks of the device, .if needed. Therefore, additional "lockout" protection is provided to guarantee data integrity. Boot
block program and erase operations are enabled
through high voltage VHH on either RP# or OE#,
and the normal program and erase command sequences are used. Reference the AC Waveforms for
Program/Erase.
tion being attempted and indicating boot block lock.
Program/erase attempts while VIH < RP# < VHH
produce spurious results and should not be attempted.
In-System Operation
For on-board programming, the RP# pin is the most
convenient means of altering the boot block. Before
issuing Program or Erase confirms commands, RP#
must transition to VHH. Hold RP# at this high voltage throughout the program or erase interval (until
after Status Register confirm of successful completion). At this time, it can return to VIH or VIL.
If boot block program or erase is attempted while
RP# is at VIH, either the Program Status or Erase
Status bit will be set to "1", reflective of the opera-
Bus
Operation
Command
Comments
Write
Program
Setup
Data = 40H
Address = Byte to be
Programmed
Write
Program
Data to be programmed
Address =. Byte to be
Programmed
Status Register Data.
ToggleOE# orCE# to
update Status Register
CheckSR.7
1 = Ready, 0 = Busy
Read
Standby
Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Standby
Check SR.3
1 = Vpp Low Detect
Standby
Check SR.4
1 = Byte Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
290406-7
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are.
programmed before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 9. 28F001BX Byte Programming Flowchart
4-318
I
28FOO 1BX-T /28F001 BX-B
Bu.
Operation
Comments
Command
Write
Erase
Setup
Data ~ 20H
Address = Within Block to be erased
Write
Erase
Data ~ DOH
Address = Within Block to be erased
Status Register Data.
Toggle DE" or CE" to update Status
Register
Read
Standby
CheckSR.7
1 ~ Ready, 0
~
Busy
Repeat for subsequent blocks.
Full status check can be done after each block or after a sequence of
blocks.
Write FFH after the last block erase operation to reset the device to
Read Array Mode.
FULL STATUS CHECK PROCEDURE
Bus
Operation
Vpp Rcngo
Error
Block Erase
Error
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
Check SRA, 5
Both 1 = Command Sequence Error
Standby
Check SR.5
1 = Block Erase Error
Error
Command Sequenco
Command
SR.3 MUST be cleared, if set during an erase attempt, before further
attempts are allowed by the Write State Machine.
290406-8
SR.5 is only cleared by the Clear Status Register Command, in cases
where multiple blocks are erased before full status is checked.
If error is detected, clear the Status Register before attempting retry or
other error recovery.
Figure 10. 28F001BX Block Erase Flowchart
I
4-319
28F001 BX-T128F001 BX-B
Bus
Operation
Comments
Command
Write
Erase
Suspend
Data
=
BOH
Write
Erase
Status Register
Data
=
70H
Standby/
Read
Read Status Register
Check SR.7
1 = Ready, 0 = Busy
Toggle OE# or CE# to
Update Status Register
Standby
CheckSR.6
1 = Suspended
Write
Read Array
Read array data from
block other than that
being erased.
Read
Write
Data = FFH
Erase Resume
Data
=
DOH
290406-9
Figure 11. 28F001BX Erase Suspend/Resume Flowchart
Programming Equipment
For PROM programming equipment that cannot
bring RP# to high voltage, OE# provides an alternate boot block access mechanism. OEl!> must transition to VHH a minimum of 480 ns before the initial
program/erase setup command and held at VHH at
least 480 ns after program or erase confirm commands are issued to the device. After this interval,
OE # can return to normal TTL levels.
DESIGN CONSIDERATIONS
Three-Line Output Control
Flash memories are often used in larger memory arrays. Intel provides three control inputs to accommo4-320
date multiple memory connections. Three-line control provides for:
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will
not occur
To efficiently use these control inputs, an address
decoder should enable CE#, while OE# should be
connected to all memory devices and the system's
READ# control line. This assures that only selected
memory devices have active outputs while deselected memory devices are in Standby Mode. RP#
should be connected to the system POWERGOOD
signal to prevent unintended writes during system
power transitions. POWERGOOD should also toggle
during system reset.
I
28FOO 1BX-T /28FOO 1BX-B
Power Supply Decoupling
Flash memory power switching characteristics re·
quire careful device coupling. System designers are
interested in 3 supply current issues; standby current
levels (Iss), active current levels (IcC> and transient
peaks producted by falling and rising edges of CE #.
Transient current magnitudes depend on the device
outputs' capacitive and inductive loading. Two·line
control and proper decoupling capacitor selection
will suppress transient voltage peaks. Each device
should have a 0.1 J-I-F ceramic capacitor connected
between its Vee and GND, and between its Vpp and
GND. These high frequency, low inherent·induc·
tance capacitors should be placed as close as pos·
sible to the device. Additionally, for every B devices,
a 4.7 J-I-F electrolytic capacitor should be placed at
the array's power supply connection between Vee
and GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductances.
Vpp T~alC~ Oil
P~ill1~ercl Cill'ICOJi·~ [31O~,do
Programming flash memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the Vpp power sup·
ply trace. The Vpp pin supplies the memory cell cur·
rent for programming. Use similar trace widths and
layout considerations given to the Vee power bus.
Adequate Vpp supply traces and decoupling will de·
crease Vpp voltage spikes and overshoots.
Vee, Vpp, RP# Transitions and the
Command/Status Regis1ers
Programming and erase completion are not guaran·
teed if Vpp drops below VPPH. If the Vpp Status bit of
the Status Register (SR.3) is set to "1", a Clear
Status Register command MUST be issued before
further program/erase attempts are allowed by the
WSM. Otherwise, the Program (SR.4) or Erase
(SR.5) Status bits of the Status Register will be set
to "1" if error is detected. RP# transitions to VIL
during program and erase also abort the operations.
Data is partially altered in either case, and the com·
mand sequence must be repeated after normal op·
eration is restored. Device poweroff, or RPfft tran·
sitions to VIL, clear the Status Register to initial val·
ue BOH.
The Command Register latches commands as is·
sued by system software and is not altered by Vpp
or CE# transitions or WSM actions. Its state upon
. powerup, after exit from Deep·Powerdown or after
Vee transitions below VLKO, is FFH, or Read Array
Mode.
I
After program or erase is complete, even after Vpp
transitions down to VPPL, the Command Register
must be reset to read array mode via the Read Array
command if access to the memory array is desired.
Power Up/Down Protection
The 2BF001 BX is designed to offer protection
against accidental erasure or programming during
power transitions. Upon power·up, the 28F001 BX is
indifferent as to which power supply, Vpp or Vee,
powers up first. Power supply sequencing is not re·
quired. Internal circuitry in the 2BF001 BX ensures
that the Command Register is reset to Read Array
mode on power up.
A system designer must guard against spurious
writes for Vee voltages above VLKO when Vpp is
active. Since both WE# and CE# must be low for a
command write, driving either to VIH will inhibit
writes. The Command Register architecture provides
an added level of protection since alteration of mem·
ory contents only occurs after successful completion
of the two·step command sequences.
Finally, the device is disabled, until RP# is brought
to VIH, regardless of the state of its control inputs.
This provides an additional level of protection ..
28IF001BX I?OW~i' Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases us·
able battery life because the 2BFOOi BX does not
consume any power to retain code or data when the
system is off.
In addition, the 28F001 BX's Deep·Powerdown mode
ensures extremely low power dissipation even when
system power is applied. For example, laptop and
other PC applications, after copying BIOS to DRAM,
can lower RP# to VIL, producing negligible power
consumption. If access to the boot code is again
needed, as in case of a system RESET #, the part
can again be accessed, following the tpHAV wakeup
cycle required after RP# is first raised back to VIH.
The first address presented to the device while in
powerdown requires time tpHAV, after RP# tran·
sitions high, before outputs are valid. Further ac·
cesses follow normal timing. See AC Characteris·
tics-Read·Only Operations and Figure 12 for more
information .
4·321
intel®
28F001 BX-T/28F001 BX-B
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Operating Temperature
During Read .................... O°C to 70°C(1)
During Erase/Program ........... O°C to 70°C(1)
Operating Temperature
During Read ............... - 40°C to
During Erase/Program ...... - 40°C to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 85°C(2)
+ 85°C(2)
Temperature under Bias ......... -10°C to 80°C(1)
Temperature under Bias ....... - 20°C to
+ 90°C(2)
Storage Temperature ............. - 65°C to 125°C
Voltage on Any Pin
(except Ag, RP#, OE#, Vee and Vpp)
with Respect to GND .......... -2.0Vto 7.0V(3)
Voltage on Ag, RP#, and OE#
with Respect to GND ....... - 2.0V to 13.5V(3, 4)
Vpp Program Voltage
with Respect to GND
During Erase/Program ...... - 2.0V to 14.0V(3, 4)
Vee Supply Voltage
with Respect to GND .......... - 2.0V to 7.0V(3)
Output Short Circuit Current. ............ 100 mA(5)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Operating temperature is for extended temperature product defined by this specification.
3. Minimum De voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods
<20 ns. Maximum De voltage on input/output pins is Vcc +0.5V which, during transitions, may overshoot to Vee + 2.0V
for periods < 20 ns.
4. Maximum De voltage on Ag or Vpp may overshoot to + 14.0V for periods <20 ns.
5. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
TA
Operating Temperature(l)
0
70
°C
TA
Operating Temperature(2)
-40
85
°C
Vee
Supply Voltage
4.50
5.50
V
DC CHARACTERISTICS
Symbol
Vee
=
5.0V ±10%, TA
Parameter
O°Cto
Max
Unit
Input Load Current
1
± 1.0
p.A
Vee = Vee Max
VIN = Vee or GND
ILO
Output Leakage Current
1
±10
p.A
Vee = Vee Max
VOUT = VeeorGND
Ices
Vee Standby Current
1.2
2.0
rnA
Vee = Vee Max
CE# = RP# = VIH
30
100
p.A
Vee = Vee Max
CE# = RP# = Vee ±0.2V
0.05
1.0
p.A
RP#
IceD
4-322
Vee Deep-Powerdown Currerit
1
Typ
+ 70°C
IlL
Notes
Min
=
Test Conditions
=
GND ±0.2V
I
28F001B}{-T /28F001BX-B
DC CHARACTERISTICS
Symbol
vee = 5.0V ± 10%, TA = O°C to
Parameter
Notes Min Typ
1
+ 70°C (Continued)
Max
13
Unit
Test Conditions
mA Vee = Vec Max, CE# = VIL
f = 8 MHz, lOUT = 0 rnA
leeR
Vee Read Current
30
Iccp
Vee Programming Current
1
5
20
mA Programming in Progress
IceE
Vcc Erase Current
1
6
20
mA Erase in Progress
ICCES
Vcc Erase Suspend Current
1,2
5
10
mA Erase Suspended
CE# = VIH
IpPS
Vpp Standby Current
1
±1
±10
/LA Vpp s Vee
90
200
/LA Vpp> Vee
=
IpPD
Vpp Deep-Powerdown Current
1
0.80
1.0
/LA RP#
Ippp
Vpp Programming Current
1
6
30
mA Vpp = VPPH
Programming in Progress
IpPE
Vpp Erase Current
1
6
30
mA Vpp = VPPH
Erase in Progress
IpPES
Vpp Erase Suspend Current
1
90
300
/LA Vpp = VPPH
Erase Suspended
110
Aglntelligent Identifier Current
1
90
500
/LA Ag
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
0.8
Vec
2.4
Ag Intelligent Identifier Voltage
VPPL
VPP during Normal Operations
3
Vce = Vcc Min
IOH = 2.5mA
V
V
12.6
V
VLKO
2.5
VHH
RP#, OE# Unlock Voltage
11.4
V
12.6
Vec = 5.0V ±10%, TA = -40°C to
Notes
V
6.5
11.4 12.0
Parameter
Vce = Vcc Min
IOL = 5.8mA
13.0
VPP during Prog/Erase Operations
Symbol
V
0.0
Vee Erase/Write Lock Voltage
DC CHARACTERISTICS
V
11.5
VPPH
Min
VID
V
+ 0.5
0.45
VID
=
GND ±0.2V
Typ
V
Boot Block Prog/Erase
+ 85°C
Max
Unit
Test Conditions
IlL
Input Load Current
1
±1.0
/LA
Vec = Vec Max
VIN = Vec or GND
ILO
Output Leakage Current
1
±10
/LA
Vcc = Vcc Max
VOUT = Vce or GND
Iccs
Vee Standby Current
1.2
2.0
rnA
Vcc = Vcc Max
CE# = RP# = VIH
30
150
/LA
Vee = Vce Max
CE# = RP# = Vee ±0.2V
0.05
2.0
/LA
RP#
lecD
I
Vec Deep-Powerdown Current
1
=
GND ±0.2V
4-323
28F001 BX·T/28F001 BX·B
DC CHARACTERISTICS vcc = 5.0V ± 10%, TA = -40·C to + 85·C (Continued)
Symbol
Parameter
Notes
ICCR
Vcc Read Current
1
Iccp
Vcc Programming Current
1
ICCE
Vcc Erase Current
ICCES
Vcc Erase Suspend Current
Ipps
Vpp Standby Current
Min
Typ
Max
13
35
mA Vcc = Vcc Max, CE# = VIL
f = 8 MHz, lOUT = 0 mA
5
20
mA Programming in Progress
Unit
Test Conditions
1
6
20
mA Erase in Progress
1,2
5
10
mA Erase Suspended
CE# = VIH
1
±1
±15
p.A Vpp s.Vcc
90
400
p.A Vpp> Vcc
= GND ±0.2V
Ippo
Vpp Deep-Powerdown Current
1
0.80
1.0
p.A RP#
Ippp
Vpp Programming Current
1
6
30
p.A Vpp = VPPH
Programming in Progress
IpPE
Vpp Erase Current
1
6
30
mA Vpp = VPPH
Erase in Progress
IpPES
Vpp Erase Suspend Current
1
90
400
p.A Vpp = VPPH
Erase Suspended
110
Ag Intelligent Identifier Current
1
90
500
p.A Ag
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage (TTL)
VOH2
Output High Voltage (CMOS)
0.8
= VIO
V
Vcc+ 0.5 V
0.45
V Vcc = Vcc Min
IOL = 5.8mA
2.4
V Vcc = Vcc Min
IOH = 2.5mA
0.85Vcc
V IOH = - 2.5 p.A
Vcc = Vcc Min
Vcc- O.4
IOH = -100 p.A
Vcc = Vcc Min
11.5
13;0
V
0.0
6.5
V
12.6
V
VID
Ag Intelligent Identifier Voltage
VPPL
VPP during Normal Operations
~PPH
VPP during Prog/Erase Operations
VLKO
Vcc Erase/Write Lock Voltage
2.5
VHH
RP #, OE # Unlock Voltage
11.4
3
11.4
12.0
V
12.6
V Boot Block Prog/Erase
CAPACITANCE(4) TA = 25·C, f = 1 MHz
Symbol
Parameter
Max
Unit
Conditions
CIN
Input Capacitance
8
pF
VIN
COUT
Output Capacitance
12
pF
VOUT
=
OV
=
OV
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, TA = 25'C. These currents
are valid for all product versions (packages and speeds).
2. ICCES is specified with the device deselected. If the 28F001 BX is read while in Erase Suspend mode, current draw is the
sum of IceEs and lecR.
3. Erase/Programs are inhibited when Vpp = VPPL and not guaranteed in the range between VPPH and VPPL.
4. Sampled, not 100% tested.
4-324
I
28F001BX-T/28F001BX-B
AC INPUT/OUTPUT REFERENCE WAVEFORM
X~:~ > TEST:~OINTS
i < X~:~
2.4 ___
IN_P_UT_ _
0.45
OUTPUT
290406-10
A.C. test inputs are driven at VOH (2.4 Vnu for a Logic "1" and VOL (0.45 Vnu for a Logic "0". Input timing begins at
VIH (2.0 Vnu and VIL (0.8 Vnu. Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) < 10 ns.
STANDARD TEST CONFIGURATION
AC TESTING LOAD CIRCUIT
HIGH SPEED TEST CONFIGURATION
AC TESTING LOAD CIRCUIT
1.3V
1;.:~
~~
I
DEVICE
UNDER
TEST
I
lN914
lN914
RL
It-~~-o OUT
i--+--OOU
.x,CL
290406-11
CL = 100 pF
CL Includes Jig Cap'lcitance
RL = 3.3 kO
I
290406-23
CL = 30 pF
CL Includes Jig Capacitance
RL = 3.3 kO
4-325
28F001 BX-T/28F001 BX-B
AC CHARACTERISTICS-Read-Only Operations(1)
28FOO1BX-70
vee
Symbol
Parameter
= 5V
±5%
30pF
Notes
Min
Max
70
tAVAV
Read Cycle Time
tAVQV
Address to Output Delay
tELQV
CE # to Output Delay
tpHQV
RP# to Output Delay
tGLQV
OE # to Output Delay
2
tELQX
CE # to Output in Low Z
3
tEHQZ
CE # to Output in High Z
3
tGLQX
OE # to Output in Low Z
3
tGHQZ
OE # to Output in High Z
3
tOH
Output Hold from
Address CE#, or OE#
Change, Whichever
Occurs First
3
vee
= 5V
±10%
100pF
Min
= 5V
±10%
100pF
Min
Units
Max
90
75
ns
90
ns
70
75
90
ns
600
600
ns
35
ns
27
30
0
55
55
0
0
0
35
30
30
ns
0
0
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. OE# may be delayed up to teE-toE after the falling edge of CE# without impact on teE.
3. Sampled, but not 100% tested.
4. See High Speed Test Configuration.
5. See Standard Test Configuration.
4-326
vee
600
0
0
Max
75
70
2
28FOO1BX-90
ns
30
0
ns
ns
ns
28F001BX-T/28F001BX-B
AC CHARACTERISTIC5-Read-Only Operations(1)
vee
Versions(2)
Symbol
tAVAV
tRC
tAVOV: tACC
E28FOO1BX-120
N28FOO1BX-120
P28FOO1BX-120
±10%
Parameter
Notes
Read Cycle Time
Min
Max
120
Address to Output Delay
-
E28FOO1BX-150
TE28FOO1BX-150
N28FOO1BX-150
TN28FOO1BX-150
P28FOO1BX-150
Min
tELOV
tCE
CE # to Output Delay
tpHOV
tPWH
RP;!! High to Output Delay
3
tGLOV
tOE
OE # to Output Delay
3
tELOX
tLZ
CE # to Output Low Z
4
tEHOZ
tHz
CE # High to Output High Z
4
tGLOX
toLZ
OE;!! to Output Low Z
4
tGHOZ
tOF
OE;!! High to Output High Z
4
toH
Output Hold from
Addresses, CE # or OE #
Change, Whichever is First
4
ns
150
ns
120
150
ns
600
600
ns
50
0
55
55
55
30
0
ns
ns
0
30
ns
ns
0
0
0
Max
150
120
Unit
ns
ns
NOTES:
1. See AC Input/Output Reference Waveform for timing measurements.
2. Model Number Prefixes: E = TSOP (Standard Pinout), N = PLCC, P = PDIP, T = Extended Temperature. Refer to
.standard test configuration.
3. OE# may be delayed up to teE-toE after the falling edge of CE# without impact on tCE.
4. Sampled, not 100% tested.
I
4-327
~
t
;g
I\)
CD
STANDBY
DEVICE AND
ADDRESS SELECTION
....
Q
OUTPUTS ENABLED
DATA VALID
STANDBY
V,H
Vec POWER-DOWN
III
ARAAAAAJ
~
ADDRESSES STABLE
ADDRESSES (A)
~
g....
V,L
I'
1'1
IAVAV
V,H
III
~
CE# (C)
III
:!II
V,L
(Q
C
iii
....
~
>
n
V,H
OE# (G)
V,L
~
<
-...
CD
V,H
0
-...
3
WE# (w)
!rLQV
0
DI
a.
0
'a
...
CD
DI
IoH
V,H
HIGH Z·
DATA (D/Q)
VALID OUTPUT
HIGH Z
V,L
c!:
0
:::I
1/1
·1
V,L
::u
CD
! - - - - - - IAVQV
·1
5.0V
.~
Vee
GND
I'
RP#(p)VI H J
IpHQV
.
.
.,
.
--
~
V,L
-
290406-12
€:
@
28F001BX-T/28F001BX-B·
AC CHARACTERISTICS-Write/Erase/Program Operations(1,9)
28F001BX-70
Symbol
Parameter
Vee = SV
± 10%(11)
100 pF
Min
Min
Max
Max
Vee = SV
± 10%(11)
100pF
Min
Units
Max
2
70
480
75
480
90
480
RP # VHH Setup to WE # Going
High
2
10
35
100
10
40
100
10
40
100
2
3
100
35
100
40
100
40
ns
4
40
10
10
10
35
15
40
10
10
10
35
15
ns
/Ls
tAVAV
twe
Write Cycle Time
tPHWL
tps
RP# High Recovery to WE#
Going Low
tELWL
tes
CE# Setup to WE# Going Low
tWLWH
twp
WE # Pulse Width
tPHHWH tpHS
Notes
28F001BX-90
Vee = SV
± S%(10)
30pF
tVPWH
tvps
VPP Setup to WE# Going High
tAVWH
tAS
Address Setup to WE# Going
High
tDvwH
tDS
Data Setup to WE# Going High
tWHDX
tDH
Data Hold from WE # High
tWHAX
tAH
Address Hold from WE# High
tWHEH
tcH
CE # Hold from WE # High
tWHWL
tWPH WE# Pulse Width High
ns
ns
ns
ns
ns
ns
tWHOV1
Duration of Programming
Operation
.5,6,7
35
10
10
10
35
15
tWHOV2
Duration of Erase Operation
(Boot)
5,6,7
1.3
1.3
1.3
sec
tWHOV3
Duration of Erase Operation
(Parameter)
5,6,7
1.3
1.3
1.3
sec
tWHOV4
Duration of Erase Operation
(Main)
5,6,7
3.0
3.0
3.0
sec
tWHGL
Write Recovery before Read
0
0
0
0
0
0
0
0
/Ls
tOWL
tVPH Vpp Hold from Valid SRD
tOVPH
tpHH RP# VHH Hold from Valid SRD
tpHBR
Boot-Block Relock Delay
2,6
2, 7
2
0
100
100
ns
ns
ns
ns
ns
ns
100
ns
NOTES:
1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte programming or block erasure.
4. Refer to Table 3 for valid DIN for byte programming or block erasure.
5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel
Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase
verify (erasing).
6. Program and erase durations are measured to completion (SR.7 = 1). Vpp should be held at VPPH until determination of
program/erase success (SR.3/4/5 = 0).
7. For boot block programming and erasure, RP# should be held at VHH until determination of program/erase success
(SR.3/4/5 = 0).
8. Alternate boot block access method.
9. Erase/Program Cycles on extended temperature products is 10,000 cycles.
10. See high speed test configuration.
11. See standard test configuration.
I
4-329
. 28F001BX-T/28F001BX-B
AC CHARACTERISTICS-Write/Erase/Program Operations(1,9)
I
Versions
Symbol
Vee ± 10%(10)
Parameter
28FOO1BX-120
Max
28FOO1BX-150
Min
Unit
Notes
Min
Max
120
150
ns
2
480
480
ns
tAvAV
twc
Write Cycle Time
tPHWL
tps
RP# High Recovery to WE# GOing Low
tELWL
tcs
CE # Setup to WE # GOing Low
10
10
ns
tWLWH
twp
WE # Pulse Width
50
50
ns
tPHHWH
tpHS
RP# VHH Setup to WE# Going High
2
100
100
ns
tVPWH
tvps
Vpp Setup to WE# Going High
2
100
100
ns
tAvWH
tAS
Address Setup to WE# Going High
3
50
50
ns
tDvwH
tDS
Data Setup to WE# Going High
4
50
50
ns
tWHDX
tDH
Data Hold from WE # High
10
10
ns
tWHAX
tAH
Address Hold from WE# High
10
10
ns
tWHEH
tCH
CE # Hold from WE # High
10
10
ns
tWHWL
tWPH
WE # Pulse Width High
50
50
ns
,
tWHQV1
Duration of Programming Operation
5,6,7
15
15
p.s
tWHQV2
Duration of Erase Operation (Boot)
5,6,7
1.3
1.3
sec
tWHQV3
Duration of Erase Operation (Parameter)
5,6,7
1.3
1.3
sec
tWHQV4
Duration of Erase Operation (Main)
5,6,7
3.0
3.0
sec
tWHGL
Write Recovery before Read
0
0
p.s
tQVVL
tQVPH
tVPH
Vpp Hold from Valid SRD
2,6
0
0
ns
tpHH
RP# VHH Hold from Valid SRD
2,7
0
0
ns
100
2
Boot-Block Relock Delay
tpHBR
100
ns
PROM Programmer Specifications
Versions
Symbol
tGHHWL
tWHGH
I
I
I
28FOO1BX-120
Vee ±10%
Parameter
Max
28FOO1BX-150
Min
Unit
Notes
Min
Max
OE # VHH Setup to WE # Going Low
2,8
480
480
ns
OE# VHH Hold from WE# High
2,8
480
480
ns
NOTES:
. 1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to
AC Characteristics for Read-Only Operations.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte programming or block erasure.
4. Refer to Table 3 for valid DIN for byte programming or block erasure.
5. The on-chip Write State Machine incorporates all program and erase system functions and overhead of standard Intel
Flash Memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase
verify (erasing).
6. Program and erase durations are measured to completion (SR.7 = 1). Vpp should be held at VPPH until determination of
program/erase success (SR.3/4/S = 0).
7. For boot block programming and erasure, RP# should be held at VHH until determination of program/erase success
(SR.3/4/S = 0).
8. Alternate boot block access method.
9. Erase/Program Cycles on extended temperature products is 10,000 cycles.
10. See standard test configuration.
4-330
I
28F0018X-T 128F001 8X-8
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Notes
28FOO1BX-120
Min
Typ(1)
28FOO1BX-150
Max
Min
Typ(1)
Max
Unit
Boot Block Erase Time
2
2.10
14.9
2.10
14.9
Sec
Boot Block Program Time
2
0.15
0.52
0.15
0.52
Sec
Parameter Block Erase Time
2
2.10
14.6
2.10
14.6
Sec
Parameter Block Program Time
2
0.07
0.26
0.07
0.26
Sec
Main Block Erase Time
2
3.80
20.9
3.80
20.9
Sec
Main Block Program Time
2
2.10
7.34
2.10
7.34
Sec
Chip Erase Time
2
10.10
65
10.10
65
Sec
Chip Program Time
2
2.39
8.38
2.39
8.38
Sec
NOTES:
1. 2SoC, 12.0 Vpp.
2. Excludes System-Level Overhead.
Q
I
4-331
28F001BX-T/28F001BX-B
99.9
vV
,/.
, ,","
"
/
/
95
~'
/
90
80
{
-/"",
,
V ,#'
/
,
70
, ,,
60
50
L
40
30
~"",
,,/,,
99
,
"
"
"
j ,"
20
.
Il"
10
I
o. 1
2
2.5
3
3.5 4 4.5 5
15
10
20
Chip Program Time (Sec)
- - - 12V; 10 kc; 23C
.. - - - - - .. 11.4V; 10 kc: 70e
- - - - 12V; 100 kc; 23C
290406-19
Figure 13. 28F001BX Typical Programming Capability
7.5
I
,I
;
I
6.5
I
/
/
I
5.5
I
I
I
I
/
4.5
,-
..
"~
.1-- •
3.5
I
I
/
I
J
JV
I
I
I
,I
I
I
2.5
o
10
20
."
/
I
I
/
2
.'
I
/
30
40
50
,,
60
,/
70
80
90
100
110
120
130
TEMP (C)
- _ l k Cycles
- - - .. 10k Cycles
-
- -
lOOk Cycles
290406-20
Figure 14. 28F001BX Typical Programming Time at 12V
I
28F001BX·T/28F001BX·B
99.9
r---r--.----,----.-..-..--.-rrr.r---:-r--,
,'/.'
,,~/
99r--+-+---~-+--r-r~rr+F/~-~-_1
I
I,
I,
95r--+-+---~-+--h~+7~++--~-_1
90r--+-+---~-+.~~~rr++--~-_1
80r--+--+-----~~~~~+-rr++----~--_1
70~-+-+---~1-+i~_r+-~++--_4-_i
50r--+-+----~--~-r-r+-~++----~--_1
50~-+-+--~~~~_r_r+-~++--_4--_i
40~-+-+---~/~/~'+__r_r+_~++----_4--_i
30r--+--+----+-/~~~'_+--r-r+-r+++-----~~
20r--+--+-,~/~/~~--r-~~hH------r--1
1/1
lor--+--+-#I'lr~~--+--r-r+-~++----~---1
1:1
./
1r--+--~'~i--~--_+--r-r+-r+++-----~~
"
11
0.1 '---'-_"-____-'-_.L-...J......J....l-J-'-J....L..____- ' - _ - - '
30
0.5 0.7
2
3
4 5 6 78910
20
MAIN BLOCK ERASE TIME (SEC)
12V; 10 kCj23C
11.4V; 10 kCjOC
12V;100kcj23C
.-----
290406-21
Figure 15. 28F001BX Typical Erase Capability
3.2
3.0
\
\
2.8
\
2.&
,
\
2.4
,
. 2.2
2.0
1.8
1.&
,
~
\
\
,,
,,
,
,
,
"
,,
" ,,
,
i'- r-.... "
.......
1.2
1.0
"
,,
,
r-.... l"- I--.
"
'.'.
,,
r- :-
-
o 10 20 30 40 SO 50 70 80 90 100 110 120 130 140
TEMP
(Oc)
--lkCycles
.. - _ .. 10k Cycles
- - - lOOk Cycles
290406-22
Figure 16. 28F001BX Typical Erase Time at 12V
I
4-333
~
N
c',.,
(,)
~
Vee POWER-UP
& STANDBY
WRITE PROGRAM OR
ERASE SETUP COMMAND
WRITE
VALID ADDRESS & DATA (PROGRAM)
OR ERASE CONFIRM COMMAND
AUTOMATED PROGRAM
OR ERASE DELAY
READ STATUS
REGISTER DATA
co
~
Q
WRITE READ ARRAY
COMMAND
....
VIH
aJ
><
ADDRESSES (A)
~
N
VIL
co
"II
VIH
Q
....oaJ
CE# (E)
><•
aJ
VIL
."
VIH
iQ'
C
;;
....
OE# (G)
VIL
:"I
~
i
VIH
WE# (W)
VIL
3
.,0~
VIH
DATA (0/0)
VIL
it
o
'i
I,
a
0'
i
RP# (p)
6.~V
-I
r----
VHH
lpHHWH
/
IH
VIL
tYPWH
VpPH
VPP (v) VpPL
VIH
-
-c[
:J
VIL
290406-13
®
28F001BX-T/28F001BX-B
WRITE PROGRAM OR
ERASE SETUP COMMAND
YHH
OE# (G)
YIH
YIL
WE# (W)
YIH
YIL
DATA (O/Q)
WRITE
VALID ADDRESS AND DATA (PROGRAM)
OR ERASE CONFIRM COMMAND
AUTOMATED PROGRAM
OR ERASE DELAY
READ STATUS
REGISTER DATA
~-U ~
:~
U
------~(~
___O_IN__
-J}----{~---~-N---J)~----------~\rl----~(~--S-~A_~_I~_A_J}---290406-15
Figure 18. Alternate Boot Block Access Method Using OE#
I
4-335
28F001BX-T/28F001BX-B
ALTERNATE CE#-CONTROLLED WRITES(1)
28F001BX-70
I.
Symbol
Parameter
Notes
vee = 5V
± 10%(9)
vee = 5V
± 10%(9)
30 pF
100pF
100 pF
Min
twc
Write Cycle Time
tpHEL
tps
RP# High Recovery to CE#
Going Low
tWLEL
tws
WE# Setup to CE# Going Low
tELEH
tcp
CE # Pulse Width
tAVAV
tpHHEH tPHS RP# VHH Setup to CE# Going
High
tVPEH
tvps Vpp Setup to CE# Going High
2
28F001BX-90
vee = 5V
± 5%(8)
Max
Min
Max
Min
Units
Max
70
75
90
ns
480
480
480
ns
0
0
10
"
ns
50
55
55
ns
2
100
100
100
ns
2
100
100
100
ns
40
ns
40
ns
3
35
40
4
35
40
tAVEH
tAS
Address Setup to CE# Going
High
tDvEH
tDS
Data Setup to CE # Going High
tEHDX
tDH
Data Hold from CE# High
10
10
10
ns
tEHAX
tAH
Address Hold from CE # High
10
10
10
ns
tEHwH
tWH
WE# Hold from CE# High
tEHEL
tEPH CE# Pulse Width High
0
0
0
ns
20
20
20
ns
tEHQV1
Duration of Programming
Operation
5,6
15
15
15
JLs
tEHQV2
Duration of Erase Operation
(Boot)
5,6
1.3
1.3
1.3
sec
tEHQV3
Duration of Erase Operation
(Parameter)
5,6
1.3
1.3
1.3
sec
tEHQV4
Duration of Erase Operation
(Main)
5,6
3.0
3.0
3.0
sec
0
0
0
JLs
tQVVL
tVPH Vpp Hold from Valid SRD
2,5
0
0
0
ns
tQVPH
tpHH RP# VHH Hold from Valid SRD
2,6
0
tpHBR
Boot-Block Relock Delay
2
tEHGL
Write Recovery before Read
0
100
0
100
ns
100
ns
NOTES:
1. Chip-Enable Controlled Writes: Write op~ions are driven by the valid combination of CE # and WE #. In systems where
CE# defines the write pulse width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE # waveform.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte programming or block erasure.
4. Refer to Table 3 for valid DIN for byte programming or block erasure.
5. Program and erase durations are measured to completion (SR.7 = 1). Vpp should be held at VPPH until determination of
program/erase success (SR.3/4/S = 0).
6. For boot block programming and erasure, RP# should be held at VHH until determination of program/erase success
(SR.3/4/S = 0).
7. Alternate boot block access method.
8. See high speed test configuration.
9. See standard text configuration.
4-336
I
28F001 BX·T/28F001 BX·B
ALTERNATE CE #-CONTROLLED WRITES(1)
I
Versions
Symbol
28FOO1BX·120
Vee ±10%
Parameter
Notes
tAVAV
twc
Write Cycle Time
tpHEL
tps
RP # High Recovery to CE # Going Low
tWLEL
tws
WE# Setup to CE# Going Low
tELEH
tcp
CE # Pulse Width
tpHHEH
tpHS
RP# VHH Setup to CE# Going High
tVPEH
tvps
tAVEH
tOVEH
2
Min
28FOO1BX·150
Max
Min
Unit
Max
120
150
ns
480
480
ns
0
0
ns
70
70
ns
2
100
100
ns
Vpp Setup to CE# Going High
2
100
100
ns
tAS
Address Setup to CE# Going High
3
50
50
ns
tos
Data Setup to CE# Going High
4
50
50
ns
tEHOX
tOH
Data Hold from CE# High
10
10
ns
tEHAX
tAH
Address Hold from CE# High
15
15
ns
tEHWH
tWH
WE# Hold from CE# High
0
0
ns
tEHEL
tEPH
CE# Pulse Width High
.,
25
25
ns
tEHOV1
Duration of Programming Operation
5,6
15
15
ILs
tEHOV2
Duration of Erase Operation (Boot)
5,6
1.3
1.3
sec
tEHOV3
Duration of Erase Operation (Parameter)
5,6
1.3
1.3
sec
tEHOV4
Duration of Erase Operation (Main)
5,6
3.0
3.0
sec
tEHGL
Write Recovery before Read
0
0
ILs
taWL
tVPH
Vpp Hold from Valid SRD
2,5
0
0
ns
taVPH
tpHH
RP# VHH Hold from Valid SRD
2,6
0
0
ns
tpHBR
2
Boot-Block Relock Delay
100
100
ns
PROM Programmer Specifications
Versions'
Symbol
tGHHEL
tEHGH
I
28FOO1BX·120
Vee ±10%
Min
Unit
Notes
Min
OE# VHH Setup to CE# GOing Low
2, 7
480
480
ns
OE# VHH Hold from CE# High
2, 7
480
480
ns
Parameter
Max
28FOO1BX·150
Max
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE#. In systems where
CE# defines the write pulse width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should
be measured relative to the CE # waveform.
.
2. Sampled, not 100% tested.
3. Refer to Table 3 for valid AIN for byte programming or block erasure.
4. Refer to Table 3 for valid DIN for byte programming or block erasure.
5. Program and erase durations are measured to completion (SR.7 = 1). Vpp should be held at VPPH until determination of
program/erase success (SR.3/4/S = 0).
S. For boot block programming and erasure, RP# should be held at VHH until determination of program/erase success
(SR.3/4/S = 0).
7. Alternate boot block access method.
I
4-337
~
."
o
....o
.l>-
eu
C..:l
Vee POWER-UP
& STANDBY
(X>
WRITE PROGRAM OR
ERASE SETUP COMMAND
WRITE
VALID ADDRESS & DATA (PROGRAM)
OR ERASE CONFIRM COMMAND
AUTOMATED PROGRAM
OR ERASE DELAY
READ STATUS
REGISTER DATA
WRITE READ ARRAY
COMMAND
V,H
OJ
~
ADDRESSES (A)
V"
N
CD
V,H
....o
~
WE# (W)
OJ
."
C
iil
....
!D
»
;::;
><
m
V,L
c
V,H
OE# (G)
V,L
CD
3
~
l!)
V,H
CE# (E)
f
V,L
0'
3
.,0'
V,H
DATA (0/0)
V,L
~
CD
!5CD
iil
0'
I.
RP# (p) 6.5V
V,H
-I
r----
VHH
l
!PHHEH
11
:J
1/1
V,L
tVPEH
VpPH
--
VPP (v) VpPL
V,H
V,L
290406-16
€:
@
28F001 BX-T/28F001 BX-B
ORDERING INFORMATION
ITlp121Sl
r
1010111Bl
x l-IT11121 0 1
r
PACKAGE
E STANDARD 32 LEAD TSOP
N 32 LEAD PLCC
P 32-PIN PLASTIC DIP
TEMPERATURE RANGE
T EXTENDED (-40 a C ta +S5 a C)
BLANK COMMERCIAL (oac ta +70 a C)
=
=
l,
[
I
ACCESS SPEED (ns)
70 ns
90 ns
120 ns
150 ns
TOP BOOT DEVICE
B BOTTOM BOOT DEVICE
290406-18
VALID COMBINATIONS:
Commercial
Extended
32-Lead TSOP
32-Lead PLCC
E28FOOl BX-T70
N28FOOl BX-T70
P28FOOl BX-T70
32-PlnPDIP
E28FOOl BX-T90
N28FOOl BX-T90
P28FOOl BX-T90
E28FOOl BX-T120
N28FOOl BX-T120
P28FOOl BX-T120
E28FOO1BX-T150
N28FOOl BX-T150
P28FOOl BX-T150
E28FOOl BX-B70
N28FOOl BX-B70
P28FOOl BX-B70
E28FOOl BX-B90
N28FOOl BX-B90
P28FOOl BX-B90
E28FOOl BX-B120
N28FOOl BX-B120
P28FOOl BX-B120
E28FOOl BX-B150
N28FOOl BX-B150
P28FOOl BX-B150
TE28FOOl BX-T90
TN28FOOl BX-T90
TP28FOOl BX-T90
TE28FOOl BX-T150
TN28FOOl BX-T150
TP28FOOl BX-B90
TE28FOOl BX-B90
TN28FOOl BX-B90
TE28FOOl BX-B150
TN28FOOl BX-B150
ADDITIONAL ,I,NFORMATION
ER-20 "ETOX II Flash Memory
Technology"
RR-60 "ETOX II Flash Memory
Reliability Data Summary"
I
Order
Number
294005
293002
AP-316 "Using Flash Memory for InSystem Reprogrammable
Nonvolatile Storage"
AP-341 "Designing an Updatable BIOS
Using Flash Memory"
Order
Number
292046
292077
4-339
28F001BX-T 128F001 BX-B
REVISION HISTORY
Number
-004
Description
Removed Preliminary classification.
Latched address A16 in Figure 5.
Updated Boot Block Program and Erase section: "If boot block program or erase is attempted
while RP# is at VIH, either the Program Status or Erase Status bit will be set to "1",
reflective of the operation being attempted and indicating boot block lock."
Updated Figure 11, 28F001 BX Erase Suspend/Resume Flowchart
Added DC Characteristics typical current values
Combined Vpp Standby current and Vpp Read current into one Vpp Standby current spec with
two test conditions (DC Characteristics table)
Added maximum program/erase times to Erase and Programming Performance table.
Added Figures 13-16
Added Extended Temperature proliferations
-005
PWD changed to RP# for JEDEC standardization compatibility
Revised symbols, I.e.; CE, OE, etc. to CE#, OE#, etc.
-006
Added specifications for -90 and -70 product versions.
Added VOH CMOS Specification.
4-340
I
int:el.
AP-604
APPLICATION
NOTE
Using Intel's Boot Block Flash
Memory Parameter Blocks to
Replace EEPROM
PETER HAZEN
SENIOR TECHNICAL
MARKETING ENGINEER
November 1994
I
lPrru~lbo~o~~rruw
Order Number: 292148-001
4-341
USING INTEL'S BOOT BLOCK FLASH MEMORY
PARAMETER BLOCKS TO REPLACE EEPROM
CONTENTS
PAGE
CONTENTS
PAGE
1.0 INTRODUCTION ................... 4-343
8.0 SYSTEM REQUiREMENTS ........ 4-345
2.0 REVIEW OF FLASH MEMORY
FUNDAMENTALS ................... 4-343
9.0 POWER LOSS ..................... 4-346 .
10.0 INITIALIZATION .................. 4-347
3.0 SYSTEM OPERATION ............. 4-343
11.0 BIT MANIPULATION ............. 4-347
4.0 SOFTWARE SCHEME FOR
EMULATING BYTE
ALTERABILITY ..................... 4-344
12.0 TIMING ........................... 4-347
13.0 CYCLING ......................... 4-348
5.0 PARAMETER DATA
STRUCTURE ........................ 4-344
6.0 BLOCK TRANSFERS .............. 4-345
7.0 ERASING THE PARAMETER
BLOCK .............................. 4-345
4-342
14.0 CONCLUSiON .................... 4-348
15.0 ADDITIONAL INFORMATION .... 4-348
15.1 References .................... 4-348
I
AP-604
1.0 INTRODUCTION
Intel's Boot Block Flash Memories provide updatable
code and data storage for a wide range of applications
including cellular phones, modems, PC BIOS, automobile engine control and many others. System designers
reduce system cost and improve reliability by using
Intel's flash memory parameter blocks to replace
EEPROM for parameter data storage.
Using software techniques described in this paper, designers can replace EEPROM with Intel's flash memory parameter blocks in many applications that previously used EEPROM for parameter data storage. For
example, cellular phone designs use Intel's flash memory parameter blocks to store data such as telephone
numbers, time of use and user identification information. Automobile manufacturers use Intel's parameter
blocks in engine control applications to store fault
codes and engine optimization parameters. In each of
these cases, manufacturers save both EEPROM component and inventory costs by using Intel's Boot Blpck
Flash Memory for parameter storage in· addition to
storing application code. Additionally, improved reliability is achieved with lower system device and pin
counts. Finally, the amount and frequency of parameter storage is improved.
This paper describes a linked-list data structure for
storing parameters in Intel's flash memory parameter
blocks using a scheme that emulates byte a1terablility.
A review of flash memory fundamentals shows how
flash is used in a system and defmes the constraints for
implementing the software scheme. Reference source
code will be available from Intel in the near future.
Figure 1. When a block is erased, all address locations
within a block are erased in parallel, independent of
other blocks in the flash memory device.
Intel's Flash Memory Boot Block products are specified to work over 100,000 cycles when operating at SV
Vee. A cycle is defined as an Erase operation. For example, if each of the 8 Kbytes in one of the parameter
blocks are successively programmed and then the block
erased, 1 cycle has completed. This specification is important in determining how many parameters can be
stored and how many times those parameters can be
updated.
Since flash memory cannot be re-written to the same
address location without first erasing an entire block of
memory, software techniques are used to emulate byte
alterability using the two 8-KB parameter blocks
shown in Figure 1.
Table 1. Flash Memory Read,
Write and Erase Operations'
Operation
Read
Min
Segmen~
Typical
Time
Max
Time
Byte
60 ns
60ns
Write
Byte
10/ks
160/ks
Erase
Block
(8 KB)
0.8 sec
4.4 sec
·Specifications for Intel's SmartVoltage 4-M boot block
product operating in x8 mode at 5.0V Vee and 5.0V Vpp.
Refer to the SmartVoltage 2/4-M Datasheets.
3.0 SYSTEM OPERATION
2.0 REVIEW OF FLASH MEMORV
FUNDAMENTALS
Flash technology brings unique attributes to system
memory. Like RAM, flash memory is electrically modified in-system. Like ROM, flash is nonvolatile, retaining data after power is removed. However, unlike
RAM, flash cannot be rewritten on a byte basis. Flash
memory reads and writes on a byte-by-byte basis, and
adds a new requirement: it must be erased before it can
be rewritten. Table I shows each flash memory operation, the size of data, and the time it takes for each
operation.
Writing (or programming) flash is the process of changing "1 "s to "O"s. Erasing flash is the process of changing "O"s to "1"s Flash memory is erased on a block-byblock basis. Blocks are defined by a fixed address range
as shown in Intel's 4-M Boot Block Memory Map in
In addition to storing parametric data, Intel's boot
block flash memory is often used to store updatable
application code. In many systems, the hardware-lockable boot block storeS the kernel code necessary to initialize the system and invoke a recovery routine if code
is lost. The boot block also typically stores the code
necessary to program and erase the flash memory.(\)
Today, flaSh memory products do not provide the capability to read from one address location in the flash
device while writing to another address in the same
device. This means any code that writes to flash must
be downloaded to RAM.
1 Program and Erase code for Intel's boot block flash
memory products is available on the Intel BBS.
4-343
Ap·604
4.0 SOFTWARE SCHEME FOR
EMULATING BYTE
ALTERABILITY
(Word Addresses)
3FFFFH
16-Kbyte BOOT BLOCK
3EOOOH
3DFFFH
3DOOOH
3CFFFH
8-Kbyte PARAMETER BLOCK
B-Kbyte PARAMETER BLOCK
3COOOH
3BFFFH
96-Kbyte MAIN BLOCK
30000H
2FFFFH
12B-Kbyte MAIN BLOCK
20000H
1FFFFH
12B-Kbyte MAIN BLOCK
10000H
OFFFFH
12B-Kbyte MAIN BLOCK
OOOOOH
292148-1
Figure 1_lntel's Boot Block Flash Memory Map
5.0 PARAMETER DATA STRUCTURE
A linked-list data structure provides an arrangement of
data that is well-suited to the needs of flash memory.
For example, suppose we want to store three parameters that will be updated. We store each parameter in a
record. Each record has two fields: parameter_value
and next_record. The first field contains the value of
the parameter. The second field is a pointer containing
the address. of the, next record for that parameter. ParameterX is a pointer variable that contains the address
of the first record for that parameter. So Parameter!
represents an address. Stored at that address is the address of the first record of Parameter!. The first record
contains the first Parameter! value and the address of
the second Parameter! record. The second record con~
tains the latest value for that parameter and the address
.of the third record, and so on. In the last record, the
next-I'ecord field contains FFH to indicate there are
no more records. FFH is used here to indicate no more
records, since this is the default state of an erased byte
in flash memory. Each time a parameter is updated, the
code searches for the first available address location in
the parameter block, writes the new value in the value
field of the new record, and then updates the next-I'ecord field of the previous record. So, each record includes a value and a pointer, or link to the next record.
Such a data structure is called a linked list. By using a
linked list the system can quickly find the latest value
for a given parameter.
an
CPU
292148-2
Figure 2. For In-System Write to Flash, Code Is
Executed out of RAM
4-344
By using the two parameter blocks in Intel's boot block
components along with software' techniques, data can
. be stored' a byte at a time and the Erase operation of
flash can be completed as a background task, to emulate byte alterability.
example of the linked-list structure.
Figure 3 shows
To simplify the example, a one-byte field is used for
both parameter_value and next-I'ecord. In an actual
implementation, at least two bytes would be needed for
next-I'ecord, which points to another location in the
parameter block. The number of bytes required for parameter_value will depend on the specific parameter
information being stored.
AP-604
7.0 ERASING THE PARAMETER
BLOCK
Address
Content
Parameter1
D1H
Parameter 1 Pointer variable
Parameter2
D3H
Parameter 2 Pointer variable
Parameter3
D5H
Parameter 3 Pointer variable
D1H
FSH
Parameter 1 value = F8H
D2H
D7H
Parameter 1 nexCrecord
D3H
22H
Parameter 2 value = 22H
=07H
04H
D9H
Parameter 2 nexLrecord = 09H
D5H
44H
Parameter 3 value = 44H
OBH
FFH
Parameter 3 nexUecord = FFH
D7H
55H
Parameter 1 value = 55H
DSH
DBH
Parameter 1 nextJ8COl'd
D9H
F2H
Parameter 2 value
=latest
=aBH
=F2H
OAH
FFH
Paramet... 2 next.reconl = FFH = latest
DBH
F4H
Parameter 1 value
OCH
FFH
Parameter 1 nexUecord
=F4H
=FFH =latest
292148-3
Figure 3. A Linked Ust Parameter Record
Includes Two Fields: Parameter_Value and
NexLRecord
An alternative approach to using a linked-list structure,
is to define a parameter ID field and a parameter status
field that indicates whether the current parameter record is the latest. In this alternate scheme, to retrieve the
latest parameter, the system reads through every parameter instance until it finds the latest value for a given parameter.
.
6.0 BLOCK TRANSFERS
Parameters are stored until the parameter block is filled
or until there is not enough memory in the parameter
block to store another complete record. When this
point is reached, the latest value for each parameter is
transferred to the second parameter block, and the
linked-list data structure continues in the second parameter block.
A BlocLHeader record at the beginning of each parameter block indicates the status of the block. That is,
information such as which parameter block is the active
block, if the block is transferring data, and if the block
is erased.
After the valid parameters are transferred from the first
parameter block to the second, the first parameter
block is erased. Recall that flash memory requires approximately half a second to erase each parameter
block. Since this much time may not be available during system operation, Intel's flash memory products
feature an Erase Suspend command. With this command, the Erase operation can be suspended to allow
the system to read from another block in the device.
When an Erase Suspend command is given to the flash
memory, the Erase operation is suspended and the
memory enters an erase suspend state where the system
can read from another block in the flash memory.
When time is available again for erasure, the Erase Resume command instructs the flash memory to continue
erase from the point where it previously suspended
erase. This allows the Erase operation to be implemented within a finite software loop time, by using multiple
calls. Once the first parameter block is completely
erased, it is ready to store parameter records after the
second parameter block is filled. It is important to note
that no new parameters may be writ~en until the Block
Erase operation completes. Current boot block flash
memories do not allow writes while erase is suspended.
See Figure 4 for a review of the parameter storage
scheme.
8.0 SYSTEM REQUIREMENTS
As described earlier, RAM is required to execute code
during program and erase operations. The amount of
RAM required depends on the complexhy of the parameter storage data base. The code that must be
downloaded to RAM includes the flash memory read,
write and erase routines. The size of this code is in the
range of 512 bytes to 1 Kbyte. In addition, Flash'memory space will be necessary to store the program code.
Reference code that will be available from Intel, is approximately 15 KB in size. Only a small subset if this,
approximately 1 KB, is downloaded to RAM.
Another system requirement is an adequate Vpp voltage for write and erase. Many of today's flash memory
products require 12V to write and erase in-system. Intel's new SmartVoltage products feature 5V Write and
Erase operation when 12V is not available.
4-345
AP·604
Step 1: Store parameter records in Parameter Block 1.
PARAMETER BLOCK 1
PARAMETER BLOCK 2
block_status record
block_status record
parameter records
erased
Step 2: When Parameter Block 1 fills up, transfer the latest parameter records to
Parameter Block 2, and change the block_status records
PARAMETER BLOCK 1
PARAMETER BLOCK 2
block_status record
block_status record
parameter records
.....
Step 3: Store parameter records in Parameter Block 2. Erase Parameter Block 1, using
the Erase Suspend command to return to reading flash, when necessary.
PARAMETER BLOCK 1
PARAMETER BLOCK 2
block_status record
block_status record
erased
parameter records
292148-4
Figure 4. Using Two Parameter Blocks to Emulate Byte Alterability
9.0 POWER LOSS
What if power is lost in the iniddle of an erase or in the
process of updating parameter values? Power loss can
be reliably handled by defining additional fields in both
the parameter and block records. For example, in addition to the parameter_value and next~ecord fields
'. that we defined for our parameter record, we can define
4-346
a parameter_status field. One status field bit indicates
that a parameter update is beginning and another that
the parameter update has completed. So, if we lose
power in the process of updating a parameter, we know
the status of each parameter entry when power is restore". For example, when power is restored, if we find
that the status bit reflects that a parameter update began but did not finish, we know that record is invalid
and should be discarded. The same concept can be
AP-604
applied to the block_status record to handle Erase operations that may be interrupted by power failure as
well as parameter transfers between blocks.
10.0 INITIALIZATION
An initialization process determines the state of the parameter blocks. By reading the blocLstatus record
you can determine which block is the active block and
whether the other block must be erased. Upon the first
initialization, the parameter blocks can be erased and
the blocLstatus records created.
11.0 BIT MANIPULATION
Earlier, we reviewed how flash memory is read and
programmed on a byte-by-byte basis, and erased on a
block basis. Intel's flash memory actually has the capability to be programmed one bit (or multiple bits) at a
time. Recall flash memory programming is the process
of changing "1 "s to "O"s. Single bits can be programmed by masking the other bits in a byte or word
with "1"s as shown in Figure 5. By taking advantage of
this feature, you can minimize the memory space necessary for the various status fields.
Example 1:
11111111
0111 1111
Memory Contents
Program Data
0111 1111
Resultant Memory Contents
Example 2:
01111111
1011 1111
Memory Contents
Program Data
0011 1111
Resultant Memory Contents
Example 3:
0011 1111
0001 1111
Memory Contents
Program Data
0001 1111
Resultant Memory Contents
292148-5
FIgure 5. Flash Memory can be Programmed
a Bit at a Time by Masking all
Other Bits in a Byte with "1"s
12.0 TIMING
System timing analysis is required to determine the
amount of time available for:
• Reading parameters
• Downloading write/erase code to RAM
• Writing parameters
• Transferring parameters to a new block
• Erasing a parameter block
Precise timing will depend on the specific system implementation. In addition to the device timing, software
overhead timing should be considered.
The time required for reading parameters will depend
on the size of each parameter record and the number of
parameter record instances that must be read before
reaching the valid parameter record. Multiply the number of byte or word reads by the system read cycle time
to determine the total time for reading a valid parameter.
Each time a Write or Erase operation is executed on the
flash memory, a sub-routine containing the program
and erase drivers must first be downloaded to RAM.
The time required for downloading this code to RAM
depends on the size of the code, which is likely to be
I KB or less. Multiplying the code size by the write
cycle time determines the time for downloading the
code to RAM.
To determine the maximum time required for writing a
parameter, the worst case word or byte write time is
needed for the flash memory component. By multiplying the worst-case word write time by the number of
words per parameter record, the worst-case parameter
write time can be determined.
The time for transferring valid parameters from one
parameter block to the other will, of course, depend on
the number of parameters stored. If this operation is
completed as a foreground task, a block of time will be
required that includes the time to read the valid parameters and write these parameters to the new parameter
block. This operation can also be treated as a background task which is often necessary. For applications
with a defined main software loop time, the transfer
operation can be executed by determining the available
time in the main loop, beginning the transfer of parameters and then suspending this task before the main
loop time expires. Multiple calls of the main loop are
required to completely transfer all parameters to the
new block. Total time to complete the task will depend
4-347
Ap·604
on the amount of time available in each loop and the
number of calls necessary to complete the operation.
Like parameter transfers, block erase can be treated as
a foreground or background operation. When treating
erase as a background operation, total erase time will
depend on the amount of time available in the software
loop. Determine the number of calls required by dividing the total erase time by the amount of time available
in each call. Multiply the number of calls by the total
time per loop to determine the total time for erasing a
parameter block.
13.0 CYCLING
Intel's flash memory boot block products are specified
at 100,000 erase cycles. To determine how this affects
your parameter storage, use the equation shown in Figure 6. The equation can be solved for either the number
of parameter records or the parameter_record size, depending on which variables are known. This implementation provides improved cycling endurance, as compared to EEPROM,
100,000 _
8 KB - (block_record size)
Cycles -
parameter_record size
x number of
parameter_records
292148-6
Figure 6. Parameter Storage EquatloJ)
14.0 CONCLUSION
This paper describes software techniques for emulating
byte alterability using two flash memory parameter
blocks. System designers reduce system cost and improve reliability by using Ip.tel's boot block parameter
blocks for parameter data storage, replacing EEPROM.
15.0 ADDITIONAL INFORMATION
15.1 References
Order Number
4-348
Document
290530
2-Mbit SmartVoltage Boot Block Flash Memory Family
290531
4-Mbit SmartVoltage Boot Block Flash Memory Family
290539
8-Mbit SmartVoltage Boot Block Flash Memory Family
292130
AB-57 "Intel's Boot Block Architecture for Safe Firmware Updates"
intel·
AB-60
APPLICATION
BRIEF
2/4/8-Mbit SmartVoltage
Boot Block Flash Memory
Family Overview
COLLIN K. ONG
TECHNICAL MARKETING
ENGINEER
December 1994
4·349
AB-60
1.0 INTRODUCTION
This document includes a feature overview, pinouts,
and memory maps for Intel's SmartVoltage boot block
family, including 2/4/B-Mbit densities. These products
offer feature and function compatibility, including the
SmartVoltage technology (SVT) outlined below. Follow
the design steps in Section S.O to upgrade today's designs to SVT.
2.0 BOOT BLOCK ARCHITECTURE
Intel's current boot block architecture products offer
the familiar features that optimize it for updatable firmware storage. These features include:
• Hardware-lockable boot block for secure kernel
code storage
• Parameter blocks for' parameter storage
• Main blocks for modular code updates, facilitating
updatable firmware
• xB or x16 user-selectable I/O operation
• RP # for reset and write protection
• PSOP and TSOP packages
Intel is now integrating its SmartVoltage technology
into the boot block family in order to increase the flexibility of these components.
4.0 NEW SMARTVOLTAGE
TECHNOLOGY FEATURES
SmartVoltage offers the following new features:
1. Voltage Flexibility
• Vee = 3.3V or SV with enhanced circuits to optimize low-voltage performance when low power consumption is critical.
• Program/Erase operation with Vpp = SV for convenient in-system writes without a DC-DC converter or Vpp = 12V when write/erase performance
is a concern, such as during production.
2. Write Protection
• WP# pin replaces a DU pin and is used in conjunction with the Vpp and RP # pins, as detailed in the
table below, to control write protection of the boot
block (see note on PSOP pinout diagram).
Vpp
RP# WP#
Write Protection
X
X
All Blocks Locked
2 VPPLK
VIL
X
All Blocks Locked (Reset)
2 VPPLK
VHH
X
All Blocks Unlocked
2 VPPLK
VIH
VIL
Boot Block Locked
2 VPPLK
VIH
VIH
All Blocks Unlocked
VIL
>
5.0 UPGRADING FROM 12V TO SVT
3.0 PINOUT. COMPATIBLE DENSITY
UPGRADES
In addition, Intel is committed to providing density upgrades with pinout compatibility for the 2-Mbit,
4-Mbit, and B-Mbit densities. The pinouts in Figures 2,
3, and 4 illus~rate these compatible upgrade paths.
If you are designing with 12V Vpp products today, you
must adhere to the following design steps to ensure you
can upgrade to SVT:
1. If using SV Program/Erase, allow for connecting
Vpp to SV and disconnecting Vpp from 12V.
2. If adding a switch on Vpp for write protection,
switch to GND instead of Vee.
3. Connect WP# (DU on existing products) to Vee,
GND, or a control signal. This pin cannot be left
floating..
292154-1
Figure 1. The SmartVoltage Technology Boot
Block Line Features a Pinout-Compatible
Upgrade Path
4-350
I
intel®
AB-EiD
6.0 PACKAGE PINOUTS
28FOO8
28FOO4
A 16
A 1S
A14
A 13
A12
All
Ag
Aa
WEn
RP#
Vpp
WP#
Ala
Ay
A6
As
A4
A3
A2
Al
A 16
A 1S
A14
A 13
A12
All
Ag
Aa
WEn
RP#
Vpp
~
Al
y
A6
As
A4
A3
A2
Al
A 16
A 1S
A14
A 13
A12
All
Ag
Aa
WEn
RP#
Vpp
WP#
NC
Ay
A6
As
A4
A3
A2
Al
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
28FOO2
4D-LEAD TSOP
10mmx20mm
TOP VIEW
A17
GND
NC
NC
AlO
DOy
D0 6
DOS
D04
Vee
Vee
NC
D03
D02
DOl
DOc
OE#
GND
CE#
Ao
28F004
28F008
A17
GND
NC
NC
AlO
DOy
D06
DOS
D04
Vee
Vee
NC
D03
D02
DOl
DOo
OE#
GND
CE#
Ao
A17
GND
NC
~
DOy
D06
DOS
D04
Vee
Vee
NC
D03
D02
DOl
DOo
OE#
GND
CE#
Ao
292154-2
Figure 2. The 40-Lead TSOP Offers the Smallest Form Factor Tor Space-Constrained Applications
28F800
Vpp
§>
'7
A7
A6
As
A.
A3
A2
A,
AD
CE#
GND
OE#
DOD
DO.
DO,
DO.
D0 2
DO,o
D0 3
DO"
28F400
Vpp
WP#
~
A7
A6
As
A.
A3
A2
A,
AD
CE#
GND
OE#
DOD
DO.
DO,
DO.
D0 2
DO,o
D0 3
DO"
Vpp
WP#
NC
A7
A6
As
A.
A3
A2
A,
AD
CE#
GND
OE#
DOD
DO.
DO,
DO.
D0 2
DO,o
D0 3
DO"
10
2
3
4
5
6
7
8
9
10
11
14
15
16
17
18
19
20
21
22
44
43
PA2BF200
44·Lead PSOP
0.525" x 1.110"
TOP VIEW
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RP#
WEn
A.
A9
AlO
A"
A'2
A'3
A,.
A,s
A'6
BYTE#
GND
DO,s/A.,
D0 7
DO,.
D0 6
DO'3
DOs
DO'2
DO.
Vee
28F400
2BFBOO
RP#
WEn
A.
A.
AlO
A"
A'2
A'3
A,.
A,s
RP#
WEn
A.
Ag
AlO
A"
A'2
A'3
A,.
A,s
A'6
BYTE#
GND
DO,s/A.,
D0 7
DO,.
D0 6
DO '3
DOs
DO'2
DO.
Vee
A'6
BYTE#
GND
DO,s/A.,
D07
DO,.
DOs
DO'3
DOs
DO'2
DO.
Vee
2921S4-3
NOTE:
For the 8·Mbit device, pin 2 has been changed to AlB r,yvp # on 2/4·Mbit). Designs planning on upgrading to
the 8·Mbit density from the 2/4·Mbit density in this package should design pin 2 to control WP# functionality
at the 2/4·Mbit level and allow for pin 2 to control Al B after upgrading to the 8·Mbit density.
Figure 3. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM Standards
I
4·351
AB·60
28F400
28F800 28F400
A,s
A'4
Ala
A'2
A"
A,o
Ag
As
NC
NC
WEll
RPII
Vpp
WP#
A,s
A'4
A 13
A'2
A11
A,o
Ag
As
NC
NC
WE#
RP#
Vpp
WP#
NC
~~
.A 7
As
As
A4
A3
A2
A,
A7
6
As
A4
A3
A2
A,
A,s
A'4
A 13
A'2
A"
A,o
Ag
A8
NC
NC
WE#
RPI!
Vpp
WP#
NC
NC
NC
A7
A6
As
A4
A3
A2
A,
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A,s
BYTE#
GND.
DO,s/A. ,
0
D~
00,4
DOa
00,3
DOs
00,2
004
Vee
DO"
003
00,0
002
DOg
0.0,
DOs
000
CE#
GND
CE#
Ao
28F200
48-LEAD TSOP
12mmx 20mm
TOP VIEW
A,S
BYTE#
GND
DOu(A.,
D07
DO'4
D06
DO, 3
DOs
DO, 2
D04
Vee
DO"
D03
gg!O
DOg
DO,
DOs
DOo
CE#
GND
CE#
Ao
28F800
-:--A,a
BYTE#
GND
oo,s/A.,
007
DO'4
OOe
DO'3
DOs
DO'2
D04
Vee
DO"
D03
D010
CO2
DOg
DO,
DOs
DOo
OE#
GND
CE#
Ao
292154-4
Figure 4. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation
28f.4OO
NC
NC
A,s
A14
A'3
A12
A'l
A,o
Ag
A8
NC
NC.
WEI
RP#
NC
NC
Vpp
WP#
~
. Ae
As
A4
A3
A2
A,
NC
28F400
NC
NC
A,s
A14
A'3
A'2
A"
A,o
Ag
A8
NC
NC
WEI
RPI
NC
NC
Vpp
WP#
NC
NC
A7
As
As
A4
Aa
A2
A,
NC
1
2
3
4
5
a
7
8
9
10
11
12
13
14
15
18
17
18
19
20
21
22
23
24
25
26
27
26
0
28F200
68-LEAD TSOP
.14mmx2Omm
TOP VIEW
NC
A,a
BYTEI
GND
OO,s/A.,
00 7
00'4
OOe
00'3
OOs
00'2
00 4
Vee
~,
OOa
0010
002
OOg
00,
OOs
000
CEil
GND
CEil
~8
NC
NC
A'6
BYTE#
GND
OO,s/A.,
007
~~
00 13
00 5
00'2
004
Vee
~,
003
00'0
002
OOg
00,
OOs
000
CEil
GND
CE.
~8
NC
292154-5
Figure 5. The 56-Lead TSOP Offers Compatibility between 2 and 4 Mbits
4-352
I
AB-60
7.0 MEMORY MAPS
28F002-T
3FFFfH
3COOOH
3BFFFH
3AOOOH
39FFFH
38000H
31FFFH
28FOO4-T
FFFFFH
1FFFfH
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
7COOOH
78FFFH
7AOOOH
79FFfH
7BOOOH
nFFfH
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
COOOOH
40000H
OOOOOH
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
EOOOOH
OFFFFH
60000H
5FFFFH
1FFFFH
_ FCOOOH
FBFFFH
FAOOOH
F9FFFH
FBOOOH
F1FFFH
96-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
20000H
2BFBOCI-T
BFFFFH
3FFFFH
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
AOOOOH
9FFFfH
20000H
lFFFFH
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
80000H
1FFFFH
OOOOOH
128-Kbyte MAIN BLOCK
60000H
5FFFFH
128-Kbyte MAIN BLOCK
4OOO0H
3FFFFH
NOTE:
128-Kbyte MAIN BLOCK
These memory maps apply to the 2BF002/004/00B-T components,
or the 2BF200/400/BOO-T components in Byte-Wide (xB) mode_
20000H
lFFFFH
128-Kbyte MAIN BLOCK
OOOOOH
292154-6
Figure 6. Byte·Wide x8·Mode Memory Maps (Top Boot)
FFFFFH
128-Kbyte MAIN BLOCK
EOOOOH
OFFFFH
128-Kbyta MAIN BLOCK
COOOOH
BFFFFH
128-Kbyte MAIN BLOCK
AOOOOH
9FFFFH
128-Kbyte MAIN BLOCK
80000H
7FFFFH
7FFFFH
128-Kbyta MAIN BLOCK
128-Kbyta MAIN BLOCK
80000H
60000H
5FFFFH
5FFFFH
128-Kbyte MAIN BLOCK
40000H
3FFFFH
3FFFfH
20000H
1FFFFH
96-Kbyte MAIN BLOCK
08000H
07FFfH
OBOOOH
OSFFFH
04000H
03FFfH
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
18-Kbyte BOOT BLOCK
20000H
1FFFFH
28FOO2-B
96-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
O8OOOH
07FFFH
06000H
05FFFH
04000H
OSFFFH
B-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyta BOOT BLOCK
OOOOOH
OOOOOH
128-Kbyta MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyta MAIN BLOCK
20000H
lFFFFH
128-Kbyte MAIN BLOCK
40000H
3FFFFH
OBOOOH
07FFFH
OBOOOH
OSFFFH
04000H
03FFFH
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
OOOOOH
28F004-B
2BFBOII-B
292154-7
NOTE:
These memory maps apply to the 2BF002/004/00B-B components, or the 2BF200/400/BOO-B components in Byte-Wide
(xB) mode.
Figure 7. Byte-Wide x8-Mode Memory Maps (Bottom Boot)
I
AB-60
28F200-T
lFFFFH
16-Kbyte BOOT BLOCK
lEOOOH
1DFFFH
l0000H
1CFFFH
lCOOOH
lBFFFH
6-Kbyte PARAMETER BLOCK
6-Kbyte PARAMETER BLOCK
28f400.T
3FFFFH
3EOOOH
3DFFFH
3IlOOOH
3CFFFH
3COOOH
3BFFFH
96-Kbyte MAIN BLOCK
l0000H
OfFFFH
6-Kbyte PARAMETER BLOCK
6-Kbyte PARAMETER BLOCK
126-Kbyte MAIN BLOCK
16-Kbyte BOOT BLOCK
7EOOOH
7DFFFH
7DOOOH
7CFFFH
7COOOH
7BFFFH
6-Kbyte PARAMETER BLOCK
6-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
70000H
6FFFFH
30000H
2FFFFH
128·Kbyte MAIN BLOCK
12!1-Kbyte MAIN BLOCK
6OODOH
20000H
lFFFFH
OOOOOH
28I'8OO-T
7FFFFH
16-Kbyte BOOT BLOCK
5f7FfFH
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
50000H
l0000H
OFFFFH
4FFFFH
12!1-Kbyte MAIN BLOCK
126-Kbyte MAIN BLOCK
40000H
3FFFFH
OOOOOH
126-Kbyte MAIN BLOCK
3OODOH
2FFFFH
126-Kbyte MAIN BLOCK
20000H
(Word addresses shown)
1FFFFH
NOTE:
These membry maps apply to the denoted 28F200/400/800-T components in Word-Wide (x16) mode.
100000H
OFFFFH
128·Kbyte MAIN BLOCK"
128·K\>yIe MAIN BLOCK
OOOOOH
292154-8
Figure 8. Word-Wide x16-Mode Memory Maps (Top Boot)
7FFFFH
12!1-Kbyte MAIN BLOCK
70000H
6FFFFH
12!1-Kbyte MAIN BLOCK
6OODOH
SFFFFH
128-Kbyte MAIN BLOCK
SOOOOH
4FFFFH
128-Kbyte MAIN BLOCK
40000H
3FFFFH
3FFFFH
128-Kbyte MAIN BLOCK
12!1-Kbyte MAIN BLOCK
3OODOH
2FFFFH
30000H
2FFFFH
128-Kbyte MAIN BLOCK
lFFFFH
128·Kbyte MAIN BLOCK
l0000H
OFFFFH
128-Kbyte MAIN BLOCK
01FFFH
6-Kbyte PARAMETER BLOCK
6-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
OOOOOH
96-Kbyte MAIN BLOCK
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
6-Kbyte PARAMETER BLOCK
6-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
OOOOOH
28f2OO.11
128-Kbyte MAIN BLOCK
100000H
OFFFFH
l0000H
OFFFFH
96-Kbyte MAIN BLOCK
04000H
03FFFH
03000H
02FFFH
O2OOOH
126-Kbyte MAIN BLOCK
20000H
lFFFFH
20000H
lFFFFH
96-Kbyte MAIN BLOCK
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
6-Kbyte PARAMETER BLOCK
6-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
OOOOOH
28F4IJO.B
28F8oo-B
292154-9
(Word addresses shown) "
NOTE:
These memory maps apply to the denoted 28F200/400/800-B components in Word-Wide (x16) mode.
Figure 9. Word-Wide x16-Mode Memory Maps (Bottom Boot)
4-354
I
AB·60
8.0 PRODUCT OFFERINGS
Existing Boot Block Products
Product
Density x Org.
28F001BX
1 Mb, 128Kx8
28F200BX
2 Mb, 256Kx8/128Kx16
28F002BX
2 Mb, 256Kx8
28F200BL
2 Mb, 256Kx8/128Kx16
28FQ02BL
2 Mb, 256Kx8
28F400BX
4 Mb, 512Kx8/256Kx16
28F004BX
4 Mb, 512Kx8
28F400BL
4 Mb, 512Kx8/256Kx16
28F004BL
4 Mb, 512Kx8
Pkg.
P,N,E
PA,E
E
PA, E
E
PA,E
E
PA,E
E
Speed (ns)
(Vee = 5V)
Speed (ns)
(Vee =3.3V)
Extended
Temp.
v
v
v
70,90,120,150
60,80,120
60,80,120
(1)
150
v(2)
(1)
150
v(2)
v
v
60,80,120
60,80,120
(1)
150
v(2)
(1)
150
v(2)
Avail.
Now
Now
Now
Now
Now
Now
Now
Now
Now
NOTES:
1. The BL products also operate at 5V Vee for programmer compatibility.
2. - 20'C- + 70'C operating range for Read-Only available Q4'94.
I
4-355
AB·SO
SmartVoltage Boot Block Products
Product
Density x Org.
Pkg.
Speed (ns)
(Vee = SV)
Speed (ns)
(Vee = 3.3V)
28F200BV
2 Mb, 256Kx8/128Kx16
44,56
60,80,120
110,150,180
".,
28F200CV
2 Mb, 256Kx8/128Kx16
48
60,80,120
110,150,180
".,
28F002BV
2 Mb, 256Kx8
40
60,80,120
110, 150, 180
".,
28F400BV
4 Mb, 512Kx8/256Kx16
44,56
60,80,120
110, 150, 180
".,
28F400CV
4 Mb, 512Kx8/256Kx16
48
60,80,120
110,150,180
".,
28F004BV
4 Mb, 512Kx8
40
60,80,120
110, 150,
Hio
".,
28F800BV
8 Mb, 1024Kx8/512Kx16
44
TBD
TBD
".,
28F800CV
8 Mb, 1024Kx8/512Kx16
48
TBD
TBD
".,
28F008BV
8 Mb, 1024Kx8
40
TBD
TBD
".,
Extended
Temp.
NOTE:
1. BV products also operate at 5V Vee for programmer compatibility.
Access Speed
(ns. Vee = 5V)
Operating Temperature
T = Extended Temp
Blank = Commercial Temp
Package
E = TSOP
PA = 44-Lead PSOP
TB = Ext. Temp 44-Lead PSO!,
T=Top Boot
B = Bottom Boot
Voltage Options (Vpp! Vee)
V = (5 or 12!3.3 or 5)
Product line designator
for all Intel Flash products
Density I Organization
OOX x8-only (X 1. 2. 4. 8)
XOO = x8/x16 Selectable (X = 2. 4. 8)
=
=
Architecture
B = Boot Block
C = Compact 4B-Lead TSOP
Boot Block
292154-10
Figure 10. Decoding the Product Names
4-356
I
intel·
AP-341
APPLICATION
NOTE
Designing an Updatable BIOS
Using FLASH Memory
BRIAN DIPERT
DON VERNER
MCD MARKETING APPLICATIONS
October 1993
I
0"'0' N"mba, 292077-005
4-357
Designing an Updatable BIOS Using Flash Memory
CONTENTS
PAGE
1.0 INTRODUCTION ................... 4-359
2.0 FLASH MEMORY ..................
2.1 EPROM Roots; Review of Flash
Process vs. EPROM & EEPROM ..
2.2 Program and Erase Automation ..
2.3 Blocked Architecture ............
2.4 Deep Powerdown Mode .........
2.5 28F001 BX Pinouts, Physical
Layout and Upgrade ..............
Plastic Dual-In Line
Plastic Leaded Chip Carrier
Thin Small Outline Package
2.6 Vpp Specifications ...............
Fixed Vpp and Vee
RP#, Vee and Vpp Lockout
Protection
4-359
4-359
4-359
4-360
4-361
4-362
4-365
3.0 HARDWARE DESIGN
CONSIDERATIONS ................. 4-366
3.1 BIOS Boot Code Requirements
and System Configurations ........ 4-367
Address Shift Configuration
Address Inversion Configuration
3.2 Vpp Generation .................. 4-369
Using System 12V Directly
Pumping 5V to 12V
Security
Using a MOSFET Switch
3.3 Modifying an Existing
Motherboard ...................... 4-370
EPROM/ROM Designs
28F010 Flash Memory Designs
3.4 In-System Write vs. On-Board
Programming ..................... 4-371
3.5 Ideas for Using Extra Adaptor
Space ............................ 4-372
4-358
CONTENTS
PAGE
4.0 SOFTWARE DESIGN
CONSIDERATIONS ................. 4-372
4.1 Update Software for a Modified
System ........................... 4-373
4.2 Pseudo-Code Overview .......... 4-374
Pseudo-Code for Flash Update
Routine
4.3 Initializing the System ............ 4-374
Checking Power
4.4 Code Loader Routine ............ 4-374
4.5 Flash Reprogramming Routines .. 4-375
On-Chip Erase Algorithm
Erase Suspend/Resume
On-Chip Programming Algorithm
Full Status Checks
4.6 Recovery Routine Overview ..... 4-379
4.7 Power Management ............. 4-379
5.0 SUMMARY ......................... 4-380
5.1 Traditional BIOS Storage and
Disadvantages .................... 4-380
5.2 Advantages of an Updatable
BIOS ............................. 4-380
5.3 Advantages of Adding DOS in
FLASH ........................... 4-380
5.4 Advantages of Adding 1 MB-4 MB
of Resident Code Storage ......... 4-380
APPENDIX A-Software Routines .... 4-381
APPENDIX B-MS-DOS ROM Version
Overview ........................... 4-397
APPENDIX C-BIOS Vendor
Information ......................... 4-398
APPENDIX D-Microprocessor/ Microcontroller Compatibility
Chart ................................ 4-399
I
AP-341
1.0
INTRODUCTION
As PC computing platforms increase in complexity, so
does the associated BIOS code. Sophisticated hardware
and BIOS software increase the potential for revisions.
Time-to-market goals require faster completion of designs from conception to production, leaving less time
for new-peripheral BIOS support. As an example,
many 80286-based PC/ATs lack BIOS support for
3'/2" floppy drives! Once a computer is out the door,
code revisions are far more difficult and costly. Code
revisions with EPROM require either a service call or
sending EPROMs to the end user, assuming nothing
else goes wrong in the process. The alternative to BIOS
update is a prematurely obsolete system, unable to support new industry standards and peripheral systems.
Flash memory offers the same nonvolatile storage as
EPROM, but additionally offers in-system write capability. Using Intel's 28FOO1BX for BIOS storage, code
updates are done quickly in the factory during test and
debug, while allowing cost-effective field updates to end
users via floppy disks or modem BBS.
This application note. describes various methods of implementing a flash memory BIOS using the 28FOO1BX.
Design targets are both laptop and desktop systems.
The primary emphasis is on application of flash memory for BIOS and ROM executable software applications. Detailed 28FOO1BX information is covered in the
datasheet, available through your local sales office.
2.0
!FLASH MEMORV
This section' provides a brief overview of Intel's Flash
Memory and in particular, Intel's 28FOO1BX blocked
flash memory family. It covers the following:
o Flash memory's EPROM roots
o Program and Erase Automation
.. Blocked Architecture
o Deep Powerdown Mode
.. Pinouts, physical layout and upgrade for different
packages
.. Vpp specifications
Major features of the 28FOO1BX are in-system write,
selective block erase, program/erase automation,
SRAM-like command interface, deep powerdown capability, fixed Vee and Vpp supplies and hardware lockout protection.
2.1
EPROM Roots; Review of fla.sh
Process vs EPROM & !E!EPROM
Intel's ETOX II (EPROM Tunnel OXide) flash memory is a single-transistor cell providing nonvolatile
I
storage like EPROM, with electrical erase similar to
EEPROM. Reprogramming flash memory entails electrically erasing all data bits in parallel, then randomly
programming data into any byte in the array. The programming operation is achieved via channel hot electron injection (CRE), just like EPROMs. Flash electrical erasure, however, is accomplished through FowlerNordheim (FN) tunneling. Using separate program and
erase methods (CRE vs. FN Tunneling), in different
cell locations, drain vs. source, permits process optimization for high cycling endurance-the number of
complete erase and re-writes. Traditional low-density
EEPROMs tunnel through the same memory cell junction for both programming and erasure. Because
EEPROMs erase before programming each byte, these
processes must occur very fast. Therefore, internal voltages used to program or erase 5V-only EEPROM
memory cells are high (e.g., 18V -30V). The combination of higher voltage with programming and erasing
through the same junction contributes to EEPROM's
oxide breakdown, poor data retention and reduced cycling capability.
Intel's flash memory erasure (tunneling) voltage is below the critical oxide breakdown voltage. By using
block erasure instead of EEPROM's byte erasure, erase
times are relaxed, reducing tunneling voltages. Programming Intel's Flash Memory is non-destructive to
the floating gate oxide compared to EEPROM's use of
tunneling for programming. These features for erase
and programming provide Intel's Flash Memory with
the highest endurance (typically over lOOK cycles)
compared to that of traditional EEPROM cycling. Furthermore, flash memory exhibits lower failure rates at
any given cycle count.
2.2 Pmgram andilEra.se Automation
The 28FOO1BX integrates a Write State Machine
(WSM) on-chip to internally implement program and
erase algorithms. Operations are initiated through command sequence writes to the Command Register, and
progress is reported back to the user through Status
Register bits. Software timers are no longer required, as
timing is now regulated through the on-chip oscillator.
System software requirements are decreased in comparison to past algorithms, minimizing overhead and development effort, and allowing code execution and interrupt servicing while simultaneously programming or
erasing the device.
The Erase Suspend command halts block erase to execute code or read data from any other block. This feature gives the system the capability to service higher
level interrupts requiring data from the 28FOO1BX during the erase interval. After issuing the Erase Resume
command,' the WSM continues erase where it left off
when suspended.
4-359
AP-341
1FFFF
1FFFF
8 Kbyte BOOT BLOCK
1 EOOO
10FFF
r-------------------------~
4 Kbyte PARAMETER BLOCK
10000
1CFFF
r-------------------------~
112 Kbyte,MAIN BLOCK
4 Kbyte PARAMETER BLOCK
1COOO
1BFFF
r-------------------------~
112 Kbyte MAIN BLOCK
04000
~-------------~
03FFF
4 Kbyte PARAMETER BLOCK
03000
~-------------~
02FFF
4 Kbyte PARAMETER BLOCK
02000
~-------------~
01FFF
8 Kbyte BOOT BLOCK
00000
00000
L -________________________- "
28F001BX-T
28F001BX-B
Figure 1_ 28F001BX Memory Maps
2.3 Blocked Architecture
The 28FOOIBX family combines the safety of a hardware-protected 8 Kbyte "boot" block with the flexibility of two 4 Kbyte "parameter" blocks and one
112 Kbyte main block. Each block can be individually
erased and programmed without affecting code stored
in another block, ensuring data integrity. The boot
block is intended to contain secure code which minimally will bring up the system and download code to
the other blocks of the 28FOOIBX if required. Once
programmed, it is hardware-locked from further alteration, guaranteeing true non-volatility.
The 28FOOIBX-T's lockable block location provides
compatibility with microprocessors and microcontrollers that boot from the top of the memory map, such as
many of Intel's microprocessor familie~. The seg-
4-360
mentation of the 28FOOIBX-B is identical. Its lockable
block location provides compatibility with microprocessors that boot from low memory, such as Motorola
and AMD products. See Figure 1 for illustrations of the
two memory maps available in the 28FOOIBX family.
The two 4 Kbyte parameter blocks have multiple uses
in BIOS environments. They can be used to back up the
CMOS setup parameters such as floppy and hard disk
type, processor speed, system memory size, graphic display type and presence of a coprocessor. Today, should
the system battery fail, the user loses information in
battery-backed SRAM. The non-volatile parameter
blocks provide the system capability to automatically
back up and recover this information. Also, EISA systems can store software variable information such as
add-in board addresses, DMA channels and interrupt
values/levels.
I
infel®
AP-341
28F010
28F010
vee
Vee
A16
WE#
A15
A1S
RP#
WE#
NC
A12
A12
A14
A14
A7
A7
A13
A13
A6
A6
As
As
A5
As
vpp
Vpp
A16
Ag
A4
A4
"'A11"
A3
A3
OE#
A2
A2
A10
AlO
Al
A1
CE#
CE#
A11
OE#
Ao
Aa
DO-,
007
000_
DQo
DQ6
006
001
DQ1
DQs
005
002
DQ 2
DQ4
004
GND
GND
DQ3
003
292077-1
Figure 2. 28F001BX DIP Pin Configuration
2.4 Deep Powerdown Mode
Market analysts predict that the high-growth segments
of the PC industry for the next several years will be in
the laptop, palmtop and handheld product lines. Power
management software is becoming an integral part of
PC system BIOS as manufacturers attempt to squeeze
the maximum amount of system operation time from
their battery pack power supplies. A key indicator of
this trend is Intel's i386™SL microprocessor superset,
which adds hardware power management to the Intel
386 architecture and answers the needs of low-power
applications.
I
The 28FOOlBX family features deep powerdown capability and is ideally suited for these same battery-operated systems. Powerdown is entered through low voltage on the RP # pin. Typical power consumption
through Vee in powerdown is 0.25 J.L W, regardless of
power supply voltages and activity on the external bus.
Once BIOS is shadowed to system DRAM for highspeed execution, the 28FOOlBX can be shut down for
minimal current drain.
This same pin, with 12V present on it, gates program
and erase of the boot block. Such a hardware lockout
preserves the system boot code once initially programmed and protects it from inadvertent alteration or
computer virus compromise.
4-361
AP-341
28ra I a
28raa 18X (128Kxa)
292077-2
Figure 3. 28F001BX PLCC Lead Configuration
2.5 28F001BX Pinouts, Physical
Layout and Upgrade
Intel's 28FOO IBX is offered in three standard 32-pin
packages: Plastic Dual In-line Package (PDIP), Plastic
Leaded Chip Carrier (PLCC), and Thin Small Outline
Package (TSOP). All three pinouts provide backward
compatibility with Intel's 28FOIO bulk-erase flash. See
Figures 2, 3, and 4 for pinout details.
Plastic Dual In-Line Package
PDIPs with sockets provide an excellent way to prototype and debug new designs. The 28FOOIBX is backward pin-compatible with 1 Mbit standard flash and
EPROMs.
4-362
Plastic Leaded Chip Carrier
Most system designs today require surface mount technology (SMT) due to shrinking board real estate and
portable form factors. PLee is one SMT component
that uses as little as 35% of the overall board space
compared to PDIP. Its small size is attributed to the
center-to-center lead spacing of 50 mils versus 100 mils,
as well as its four-sided pinout. The J-lead design allows
the PLee to be directly soldered to the circuit board.
Most SMT manufacturing equipment can easily handle
the PLCe's 50-mil lead pitch. PLee SMT sockets such
as that offered by AMP (PIN 821977-1) have an identical foot-print for 32-pin devices. Such sockets can be
used in place of directly soldering a PLCe for prototype build and code testing. Once the reprogramming
code is tested and debugged, flash PLees can then be
surface-mounted without socketing during production
runs.
I
AP-341
of pins on both ends of the package allows traces for
TSOP to be routed underneath the chip, reducing
board layers. TSOP for the 28FOOIBX is available in
the standard (E) pin configuration. For multiple chip
flash systems, Intel's bulk-erase 28FOlO flash memory
is available in both standard (E) and reverse (F) pin
configurations (see Figure 5) allowing components to
be laid out end-to-end and side-to-side for highest
board density (see Figure 6). Note how pins 32-17 on
the standard pinout match pins 1-16 on the reverse
pinout, and how pins 1-16 on the standard pinout
match pins 32-17 on the reverse pinouts.
Thin Small Outline Package
TSOP is the package of choice for hand-held equipment
or palmtop/laptop computers. These compact systems
require minimal height and area for all components, for
which TSOP excels. TSOP height measures 1.2mm versus 3.Smm for PLee. TSOP area is 8mm x 20mm compared to PLee's 11.43mm x 13.97mm. Therefore,
TSOP has significantly less total volume: TSOP =
172.8mm3, while PLee = 6S6.3mm 3, and DIP =
1872.3mm3 . State-of-the-art center-to-center terminal
spacing of 20 mils yields a smaller package with narrower conductor traces than PLee or PDIP. Location
2BF010
28F010
All
A9
As
A'3
A,.
NC
WE#
Vcc
Vpp
A'6
A'5
A'2
A7
As
A5
A4
A"
Ag
AS
Au
A'4
RP#
W[#
Vee
Vpp
A,S
A,S
04,2
A7
AS
As
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
E28FOO 1BX
32 LEAD TSOP
8mm
X
20mm
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
0[#
A'0
C[#
D~
DOs
DOs
D04
D03
GND
D02
DO,
DOo
Ao
A,
A2
A3
OE#
A'D
CE#
007
DOs
005
DO.
003
GND
D02
DO,
DOD
AD
A,
A2
A3
292077-3
Figure 4. 28F001BX TSOP Lead Configuration
I
4-363
Ap·341
~1
Ag
As
A13
A14
RP#
WE#
Vee
Vpp
A16
~s
A1Z
A7
A6
As
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
:2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
E28FO 10
STANDARD PINOUT
32 LEAD TSOP
8mm
X
20mm
TOP VIEW
OE#
Ala
CE#
D07
D06
DOs
D04
D03
GND
DOz
DOl
DOa
Aa
~
Az
A3
292077-4
OE#
Ala
CE#
D~
D06
DOs
D04
D03
GND
DOz
DO,
DOa
Aa
Al
Az
A3
~V
4
5
6
7
8
9
10
11
12
13
14
15
16
F28F010
0
REVERSE PINOUT
32 LEAD TSOP
8mm
X
20mm
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
~1
As
A13
A14
RP#
WE#
Vee
Vpp
A16
A1S
~z
A7
As
As
A4
292077-5
Figure 5. 28F010 Standard and Reverse TSOP Lead Configurations
4-364
I
Ap·341
E1
§
~
~
~
~
OIO.:lBZ.:I
I0
OlO.:lBZ3
r----= r---r--
0
6.
~
=
i
~
0
-=
F"28F"010
~
~
r - ::0'
~
ill
~
II
~
OIO.:lBZ.:I
~
~
~
:::::
0
~
~ 0
~~
~
LE§
~
=
=
e
11
OlO.:lBZ3
I
;::
I
E28F"OOlBX
Ir;=.
J
..== §l
~
..6.
~
~
~
§l
E§
V
E28F"010
~
~
I
=
=
L1
IV
0
F"28F"010
E§
§l
§l
~
~
I
~
~
I::::::l
292077 -6
Figure 6. 28F001BX and 28F010's in Serpentine Layout Using TSOPs
2.6 Vpp Specifications
Fixed Vpp and Vee
Flash memories, like EPROMs, require Ii 12V programming power supply. Unlike EPROMs, however,
the Vpp for flash memory is a fixed, standard I~vel.
When combined with the Command Regtster
erase/program control, Intel flash memories use a si~
pie, SRAM-like hardware interface with standard mIcroprocessor timings.
Intel's Flash Memory Vpp specification is 12.0V
±O.6V (5%), compatible with most off-the-shelf system power supplies. The IBM PC technical reference
manual specifies the 12V power supply at 12.0V, + 5%
and -4%. Additionally, some hard and floppy drives
require 12V ± 5%. Therefore, most PC power suppli~s
have 12V supplies with ± 5% or better tolerance. POSSI-
I
ble exceptions to this are laptop and/or palmtop PCs.
Some of these require 5V-only designs, in which case
5V is charge-pumped to 12V. It is essential to use the
specified Vpp when programming and erasing flash.
Once the commands to program or erase are issued, the
device internally derives the required voltage references
from the Vpp supply. Therefore, an improper Vpp level
degrades the performance of the part.
The Write State Machine automatically monitors the
voltage present on the Vpp pin, beginning when program or erase setup commands are issued and continuing throughout the internal algorithm interval. If low
Vpp is detected, the WSM automatically aborts the
program or erase attempt and reports an intproper voltage error to the user through the Stat~s Register. The
hardware design section discusses vanous methods of
Vpp generator if your 12V power supply does not meet
the proper tolerances or 12V is not available.
4-365
AP-341
RP#,
vee and Vpp Lockout Protection
3.0
The RP# (Resert/Powerdown) pin provides hardware
write protection for 28FOOIBX flash memories. Until
this pin transitions to TTL-level VIR, write attempts to
the device Command Register are ignored, regardless
of power supply levels or activity on the system bus and
control inputs. Typically, the system designer will gate
this signal with a system POWER GOOD indicator
output to ensure system stability before memory accesses begin.
The 28FOOIBX family provides additional protection
for designs that tie 12V directly to the device. Since the
l2V supply is less capacitively loaded than the SV supply, the 12V power supply reaches full value faster during power-on. If Command Register lockout protectjon
was not provided, a finite possibility exists that inadvertent writes may occur during power-on. For this case,
Intel's 28FOOIBX flash memory supplies Command
Register lockout protection when Vee is below 2.SV,
preventing writes to flash memory from occurring.
Since CMOS logic is valid at 2.0V, a O.SV margin of
protectiori exists, providing extra time for control signals to settle before the Command Register is activated.
Program/erase inhibit is guaranteed with Vpp below
6.5V, with corresponding Vpp low reported through
the Status Register. Once Vee reaches 2.5V, the Command Register begins processing valid commands, and
program/erase attempts may initiate with Vpp greater
than 6.5V. At this point, the system is responsible for
write control.
HARDWARE DESIGN
CONSIDERATIONS
The system level hardware requirements for implementing BIOS and application storage in flash are:
• Write Enable available to all of the flash memory
• 12V routed to flash locatiori '~r generated on-board
• CMOS control-signal interface, or RP# gated by a
power-good signal
• Data buffer or transceiver that works in both write
and read directions
• Space in memory map allocated for each application's size
Intel's i386SL microprocessor superset was chosen for
the design example, shown in Figure 7. The Inte1386SL
microprocessor superset integrates all major components of a Inte1386 based design on two chips, including
bus memory, cache controllers and the ISA peripheral
subsystem. Additionally, it consolidates hardware power management for battery-operated designs such as
laptop, handheld and palmtop computers.
Note the clean interface between the superset and
28FOOIBX-T. Flash memory was comprehended early
in the design of the Inte1386SL microprocessor superset, to ensure a minimal-chip interface. Transceivers for
the system bus, as well as a flash memory CE# signal,
are integrated on the Inte1386SL.
When the 28FOOIBX Vee powers up, or after the RP#
pin transitions to VIL and back to VIR, the Command
Register is automatically initialized to Read Array
mode.
12V
82360SL
Controller
.
I Vpp
I Switch
I
I
L _
vce -
X07
XOEN#
XOIR
1
1
.... SA
"'1
0-16
.... SO[o:6] ..
80386SL
~-\~
_
GP'OD
RESET#
X-BUS
XCEIVER
1
I ...
I. .
vee
G P I 0 D - Monitoring
Circuitry
RESET#
000- 7 ~
,.
CE# ,..
MEMRO#
OE#
ROM 16/8#
~
~
RP#
Vpp
AO- 16 ~
ROMCSI#
MEMWR#
rt
28FOO1BX-T
WE#
GPIO
292077-7
Figure 7. Intel386SL Microprocessor Superset with 28F001BX-T Flash BIOS
4-366
I
AP-341
The RP # pin is gated by a power good signal to ensure
control logic integrity before writes to the 28FOOIBX-T
are allowed. It is also gated by System Reset, to abort
program or erase if required for CPU reboot, and by a
separate General Purpose Input-Output (GPIO) line to
power down the device once BIOS is shadowed to
RAM. CMOS logic will guarantee lowest power dissipation.
Similarly, system 12V is gated both by System Reset
and a GPIO line. Software can switch 12V to the
28FOOIBX-T only when programming or erasing it,
minimizing system power consumption. Vpp generation and switching methods are discussed in Section
3.3.
Application code, assuming a ROM in the BIOS socket, is sometimes designed to write to BIOS locations to
generate software timing delays (versus using NOPs).
Gating WR# to the flash memory with a GPIO line
disables writes until desired by BIOS update software.
3.1
BIOS Boot Code Requirements
and System Configurations
The previous design assumed that shadow RAM was
available in the system. Referencing Figure 8, we see
that the BIOS is actually stored in the main block of the
28FOOIBX, from system address EOOOOH-FBFFFH.
In this scenario, the processor jump vectors, BIOS
checksum and recovery code are stored in the 8 Kbyte
boot block. This is the area the processor will jump to
on powerup or after reset. The boot block code will
execute a checksum check of the main block for a valid
BIOS. If successful, the processor will check system
RAM, copy the main block code -to high memory
DRAM and jump to this area for the remainder of
Power On Self Test (POST), as well as further BIOS
calls. Optionally, the 28FOOIBX can then be disabled
for power savings.
If BIOS checksum determines an invalid BIOS, the sys-
tem RAM and floppy drive (or possibly modem) are
initialized using the boot block recovery code. The system requests (through screen display or speaker
"beeps") that the user install the BIOS update floppy
disk. A search of the floppy disk is made for a specific
file name, and once found, update code is used to re-initialize the main BIOS block. System reboot restores
normal operation. Alternatively, the BIOS recovery
code can contain specific, non-DOS sector/track information pertaining to the location of the new BIOS update file. Thus, the filds protected and not readable to,
basic DOS users.
If ROM BIOS disable is overriden by system software
or the user (through setup utility), the design must
compensate for the altered BIOS location to prevent
BIOS calls jumping to incorrect code locations. The
following two methods provide alternative solutions for
the system designer.
Address Shift Configuration
In this scenario, after BIOS initialization is complete, a
write to a latch, register or flip-flop shifts addresses for
future BIOS code fetches by 16 Kbytes. This allows the
system to correctly access the main block and bypass
parameter and boot blocks. A system reset or loss of
power clears this latch, allowing booting from the boot
block once again. Figure 9 shows the input and output
signals required for a p.PLD address shifter. It shifts
addresses in the range FFFFFH-E4000H (112 Kbytes)
to FBFFFH - EOOOOH.
1 Mby\a OOS Map
FFFFFH
28FOO 18X-T Memory Map
64K
810S Location
64K
Additional BIOS Space
MS-OOS ROM Var. 3.22
232K
Adopter Space
640K
User Area
/
16 Byte Jump Vector
800t Kernel,
8K
Reeal/ory Code
4K
Parameter Block
4K
Parameter Block
112K
Main BIOS Area
optionally
including
Power Management,
OOOOH
Video Drivers,
ROM-Executable DOS,
otc.
292077-8
Figure 8. 28F001B}{-T in 1 Mbyte DOS Memory Map
I
4-367
AP-341
S~6
S~5
SA14
RESET#
PWRGOOD
85C220
},PLD
16K 'Address
Shifter
~6
~5
~4
GPIO
292077-9
Figure 9. Address Shift Circuitry
If power loss aborts a BIOS update, the main array
block will be partially programmed/erased and the
code in this block unusable. The system will "hang" or
not boot at all. To boot from the boot recovery block,
restore address A16 polarity, producing the memory
map shown in Figure II. A keyboard sequence, switch
on the back of the PC or jumper on the motherboard
can toggle A16 restore logic and."un-invert" it. After
reconfiguration, the processor boots from the boot
block and executes its recovery algorithm to restore
main array block contents. Re-inverting A16 reinstates
normal system bootup and operation.
Address Inversion Configuration
Figure 10 presents an alternative approach to configuring the 28FOOIBX in the system memory map. Simple
inversion of address line A16 to the 28FOOlBX moves
the boot block to the lower half of flash memory as seen
by the system. .In normal operation, the processor. boots
and executes from the main array areas, which store the
system BIOS, video BIOS and/or DOS in ROM.
FFFFF
Recovery Code
FEOOO
FDFFF
Parameter Block
FDOOO
FCFFF
Parameter Block
FFFFF
BIOS
BIOS
FOOOO
EFFFF
Recovery Code
EEOOO
EOOOO
EDFFF
Parameter Block
EDOOO
ECFFF
Parameter Block
ECOOO
EBFFF
BIOS
Figure 11. Inversion Configuration (Recovery)
Since standard BIOS code does not support boot block
recovery, your BIOS software engineers must design
the recovery code for the 8 Kbyte block. See Section 4.6
for a flowchart of an example' recovery algorithm.
Third-party BIOS vendors, working with Intel, have
also developed recovery code for the 28FOOIBX (see
Appendix C), With the exception of this recovery section, the rest of the BIOS remains the same.
EOOOO
Figure 10. Inversion Configuration (Normal)
4-368
I
AP-341
3.2 Vpp Generation
For flash BIOS designs, the 12V Vpp can be provided
by:
1. Using the existing 12V supply from PC Power Supply, or
2. Generating 12V using a charge pump or DC-DC
converter from the 5V supply.
Flash typically requires only 10 rnA for program or
erase (30 rnA max); otherwise only 10 !LA is drawn in
standby mode, and 0.8 !LA in deep powerdown mode.
Using System 12V Directly
As stated earlier, the IBM PC technical reference manual specifies the 12V supply as + 5% and -4%, which
meets the Intel Flash Memory Vpp requirement. If
your power supply meets this condition and has CMOS
logic, 12V from the PC power supply can be tied directly to flash memory, eliminating the need to add extra
circuitry for Vpp generation. This is possible due to the
RP #, Vee and Vpp write lockout protection offered in
the 28FOOIBX.
Pumping 5V to 12V
If your system does not provide 12V or does not meet
flash memory specifications, several 5-to-12V converters are available, including surface-mount versions. Application Note AP-316, available from your local Intel
Sales Office, lists several Vpp solutions which offer
on/off control of Vpp and provide a steady Vpp rise
and little overshoot. Figure 12 shows one example. On
power-up, system reset or when Vee is below 4.5V,
Vpp is forced off. It is enabled (or disabled) by writing
to the VppEN # I/O port address. On/off capability is
essential for battery-operated equipment and eliminates
the need for WE# filtering. The VppEN# signal
"OR'ed" with the system memory write (MEMWR#)
functions as the clock signal for the 74FC74 D-flipflop. The D-input is latched when MEMWR# goes
high. Writing a one or a zero turns Vpp on or off,
respectively.
VppEN#
MEMRD#
Read to Determine
Vpp Status
...-----~
Vee
Vee
74F125
PR
10 DATA LINE
Q
Vpp
. . . - - - . - + - - ( 1 2 V , 200mA)
74F74
T
270K
VppEN#
MEMWR#
elK
Cl
Q
100"F
GND
1.24K
RESET#
(Vpp Off at Pawerup)
120K
GND
. . . - - - - - - - - - - - - - - RESET#
(from system bus)
RESET#
+--.....~O<
292077-10
Figure 12. Vpp Generation with Write Protection
I
4-369
AP-341
Linear Technology's LTl072, a switching regulator, is
used as a 5V to 12V charge pump. The 10.7K and
1.24K resistors are used' to establish the correct reference voltage to obtain 12V. The 100 ,...F capacitor at the
output can handle up to 200 rnA. For a single- or double-chip BIOS design, this capacitor value can' be
halved or even quartered to allow selection of a SMT
capacitor value, since the maximum Ipp current per
device is only 30 mA (10 mA typical). Allow sufficient
time when switching Vpp on, letting the charge pump
level out and enabling the Command Register to receive - program or erase commands. The diode,
MUR120, keeps the inductor from absorbing current
from the charged output capacitor.
Vpp SWitch Schematic
12V
GPIO
VppOUT
RESET#
10K
T10l'F
292077.-11
Figure 13. Vpp Switch Using MTD4P05
Using a MOSFET Switch
Security
Controlling Vpp provides the benefit of system hardware security. Beyond this, you can design for even
higher security levels. The first level could be the design
- of a simple software password routine that would only
turn on Vpp when a correct password is given. Alternatively, you can provide a jumper to allow 12V to the
part for a BIOS update and then return it when reprogramming is fmished. The system should check this pin
to see if the jumper was left in the programming position and remind the user to move it. Unless Vpp is at
12V, the flash memory contents cannot be changed and
acts just like ROM. Disabling Vpp until voltages have
stabilized provides additional power-up protection.
The Motorola component, MC34064, is an under-voltage sensing circuit that begins functioning when VCC is
above-IV. Between IV and 4.6V, the RESET# output
is active. This (or a system RESET#) clears the
74FC74, keeping Vpp off. Alternatively, if you use
CMOS logic, you could make use of Intel's flash memory Vcc and Vpp lockout functions. While Vcc is below
2.5V, the Command Register is locked out. Since
CMOS control logic is active at 2.0V, a 0.5V safety
margin exists for control logic to settle down before the
part becomes active. Program and erase attempts are
inhibited with Vpp below 6.5V. For both CMOS and
non-CMOS designs (i.e., control logic active at 2.0V),
gate RP# with the power supply's "Power Good" signal or the MC34064's RESET# output (Figure 13).
Until RP# transitions to VIH, the part ignores all write
attempts, regardless of power supply voltages and bus
, activity.
4-370
For laptops or palmtops, an always-active 12V may not
provide acceptable power management. For these systems, a MOSFET switch will toggle 12V to the flash
memory, minimizing current draw when not needed.
Several DC switches exist, but there are a few issues to
consider in your selection. Choose a switch with low
"ON" resistance to keep the Vpp'voltage within flash
memory tolerances. The system 12V power supply
must be specified to a tighter range to allow for any
voltage drop through the switch. Allocate an I/O line
(Vpp enable) to turn the switch on and off. To handle
"warm RESETS", the Vpp enable must be gated with
the system RESET # line. The Motorola MTD4P05 is
one example of a surface-mount switch with low drainsource resistance. Assuming a 12V + 5% and -4%
supply:
Rns =
O.6!l
Ipp =
30 rnA (Worst Case)
aVSWITCHDrop = (30 mA x 0.6!l) = 0.02V,
-< (4%ofVpp =)0.48V.
Figure 13 shows a schematic of a Vpp switch design.
3.3 Modifying an Existing
Motherboard
EPROM/ROM Designs
If you are modifying an existing motherboard design
for a flash memory BIOS, there are a few things you
should consider. First, check the logic design to determine if WR # is decoded and connected to the BIOS
EPROM location. Typical motherboard .logic designs
do not allow writes to the EPROM locations and treat
EPROM writes as invalid (e.g., ROMCS# not generated with MEMWR #). This is overcome by generating
the BIOS location's WR # externally by either adding
the necessary discrete logic or adding a 3-to-8 decoder
(see Figure 14 for: an example). In either case, tap into
the M/IO# and WR# control lines and configure the
decoder to provide a logic low for the M "AND"
WR # "AND" BIOS address condition.
AP-341
Discrete Flash WE # Solution
WR#------------~
FLASHWR#
Decoder Flash WE # Solution
SA19
A2
SA18
Al
SA17
Ao
WR#
E2#
1.4/10#
E3
07
74x138
E1#
1.4/10#
292077-13
292077-12
Figure 14. Discrete and Single-Chip Decoder WE # Solutions
Secondly, check to see if the BIOS code transceiver or
buffer for the EPROM location works in both directions. The transceiver may need a special BIOS call to
unlock it in the "write" direction, or you may have to
reprogram the logic for that portion of your board. If
your chip set data buffer works only in one direction, a
transceiver and direction logic must be added to the
CPU bus to pass data to and from flash memory.
Your system must also be capable of routing 12V to the
BIOS socket for program and erase. Control RP# with
system RESET # and POWERGOOD (see Section 3.0)
and optionally provide capability for deep powerdown
mode via an I/O line. Finally, address inversion or shift
mechanisms outline in Section 3.1 can optionally be
added for recovery capability with the 28FOO1BX.
28F010 Flash Memory Designs
If your design currently incorporates Intel's 28FOlO
flash memory, hardware upgrade to the 28FOOIBX is
simple. Transceiver, BIOS write and Vpp requirements
will have already been considered in the original design.
Control RP# as described in Section 3.0. Finally, invert or shift the system addresses as in Section 3.1 if
BIOS "ROM" access after shadowing to DRAM is anticipated.
I
3.4 In-System Write vs On-Board
Programming
When devices are soldered directly to a printed circuit
board, one of two sources control flash memory reprogramming:
I. the system's own processor, or
2. a PROM programmer connected to the board.
These options are called In-System Write (ISW) and
On-Board Programming (OBP), respectively. Their respective benefits are discussed in detail in AP-316.
With ISW, the system drives the reprogramming pro-.
cess and generates Vpp locally. Under this scenario, the
board manufacturer will initially program at least the
boot block in a PROM programmer. This removes the
need for circuitry on-board to unlock the boot block,
guaranteeing boot code integrity throughout system
life. A good design practice for ISW-type designs is to
socket the first few flash BIOS prototypes. SMT-only
designs can also socket using PLCC SMT sockets.
Socketing enables the system designer to easily work
out any bugs with in-system flash reprogramming by
allowing the removal of a flash part for external reprogramming in a PROM programmer. Once ISW reprogramming is fully debugged, pre-programmed flash
parts can be soldered directly to the circuit board without a socket. All flash memory components are exposed
to a data-retention bake testing and checked for any
data loss before shipping. It is extremely unlikely that
data in a production flash device can be corrupted from
heat by a production-run soldering application.
4-371
AP·341
OBP uses an external board programmer to supply Vpp
and Vffir and control the programming process. Certain design considerations must be evaluated prior to
laying out the design. Some manufacturers using TSOP
may also want to remove a handling step from the manufacturing process by providing the capability to program flash for the first time after being soldered directly onto the circuit board. OBP can accomplish this if
the design is first laid out correctly to support OBP.
External circuitry generates voltages needed to unlock
and program/erase the boot block.
3.5 Ideas for Using Extra Adaptor
Space
Laptop and palmtop systems may have adaptor space
available in the system memory map since there typically isn't much room for add-in boards. Additionally,
they may not use up the entire l28K of BIOS space due
to their fixed feature set and limited upgrade capability.
This extra memory space can hold ROM executable
programs like Lotus 123, WordPerfect, Microsoft
Works, etc. Using Intel's flash TSOPs, a small application cache can reduce a laptop's disk access and increase battery life.
Additionally, ROM-Executable DOS can be placed
anywhere in adapter space. For example, MS-DOS
ROM Version 3.22 requires 62 KB of adaptor space
today (this may change on subsequent revisions). One
location for MS-DOS ROM Version 3.22 is directly un-
der the BIOS (again see Figure 8). Today's typical
BIOS consumes 64 KBor less; consequently, both the
BIOS and MS-DOS ROM Version 3.22 could reside in
a single 28FOOlBX (128 Kbytes), yielding reduced
chipcount. However, if power management code is added to the BIOS, system BIOS code could grow to
80 KB or more; Therefore, designs that include both
power management and MS-DOS ROM Version 3.22
should consider using both a 28FOOlBX and 28FOlO
flash device (or two 28FOOlBX's). This leaves extra
space for BIOS and MS-DOS ROM to grow in the design, while providing additional storage for the video
BIOS.
4.0 SOFTWARE DESIGN
CONSIDERATIONS
Intel's Flash Memory provides a cost-effective, updatable, nonvolatile code storage medium. The 28FOOlBX
integrates the Quick-Pulse Programming and QuickErase algorithms of prior Intel Flash Memories onchip, using the Command Register, Status Register and
Write State Machine (WSM). On-chip integration dramatically reduces system overhead, simplifies system
software.creation and debug and provides SRAM-like
timings to the Command and Status Registers. WSM
operation, internal program/erase verify and Vpp high
voltage presence are monitored and reported via appropriate Status Register bits. Table 1 Iists the 28FOOIBX
command set, while Table 2 details the Status Register
bits and their meanings.
Table 1. 28F001BX Command Definitions
Command
Bus Notes
Second Bus Cycle
First Bus Cycle
Cycles
Req'd
1,2 Operation Address Data Operation Address Data
Read Array/Reset
1
Write
X
FFH
Intelligent Identifier
3
1,2,3
Write
X
90H
Read
IA
liD
Read Status Register
2
2
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Write
BA
20H
Write
BA
DOH
Write
X
BOH
Write
X
DOH
Write
PA
40H
Write
PA
PD
Erase Setup/Erase Confirm
2
Erase Suspend/Erase Resume
2
Program Setup/Program
2
1
1,2
NOTES:
1. IA = Identifier Address; OOH for manufacturer code, 01 H for device code.
SA = Address within the block being erased.
PA = Address of memory location to be programmed.
2. SRD = Data read from Status Register. See Table 2 for a description of Status Register bits.
PO = Data to be programmed at location PA. Data is latched on the rising edge of WE#.
110 = Data read from intelligent identifier.
.
3. Following the intelligent identifier command, two read operations access the manufacturer and device codes.
4. Commands other than shown above are reserved by Intel for future device implementations and should not be used.
4-372
I
Ap·341
Table 2. 28F001BX Status Register Definitions
WSMS
ESS
ES
PS
VPPS
R
7
6
5
4
3
2
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0= Busy
SR.6 = ERASE SUSPEND STATUS
1 = Erase Suspended
o = Erase In Progress/Completed
SR.5 = ERASE STATUS
1 = Error In Block Erase
o = Successful Block Erase
SR.4 = PROGRAM STATUS
1 = Error In Byte Program
o = Successful Byte Program
SR.3 = Vpp STATUS
1 = Vpp Low Detect; Operation Abort
0= Vpp OK
R
R
o
NOTES:
The Write State Machines Status Bit must first be
checked to determine program or erase completion, before the Program or Erase Status bits are checked for
success.
If the Program AND Erase Status bits are set to 1's during an erase attempt, an improper command sequence
was entered. Attempt the operation again.
If Vpp low status is detected. the Status Register must be
cleared before another program or erase operation is attempted.
The Vpp Status bit, unlike an AID converter, does not
provide continuous indication of Vpp level. The WSM interrogates the Vpp level only after the program or erase
command sequences have been entered and informs the
system if Vpp has not been switched on. The Vpp Status
bit is not guaranteed to report accurate feedback between VPPL and VPPH.
SR.2-SR.O = RESERVED FOR FUTURE ENHANCEMENTS
These bits are reserved for future use and should be masked out when polling the Status Register.
The WSM on-chip oscillator internally times the program/erase algorithms, making software ~imers unnecessary. Block precondition is also controlled by the
WSM as part of the erase algorithm. Block data programming to "O's" before erasing is no longer needed.
Intel's high quality design, manufacturing and testing
result in outstanding reliability and performance
throughout device life. Although Program Status and
Erase Status bits are provided for Status Register completeness, errors will probably not be encountered, if
proper Vpp levels and software sequences are implemented.
Intel offers standard software drivers, written in "C",
to assist software engineers implementing 28FOOIBX
reprogramming for update utilities. These high-level
routines, found in Appendix A, are adaptable to a wide
range of ~P and ~C platforms and system architectures.
Covered in this section are the major software steps for
a flash BIOS update utility:
• Update software for a modified system
• Pseudo-Code overview
I
o Initializing the system
.. Code loader routine
to Flash re-programming
• Recovery routines
• Power management
4.1 Update Software for a Modified
System
The design example of Section 3.0 assumes BIOS shadowing for BIOS code execution while allowing BIOS
writes to the flash socket. Many systems provide a register which enables BIOS writes and reads. Some systems may not allow BIOS reads from RAM while performing BIOS writes to the flash socket, or vice versa.
The reasons may be simple; no shadow RAM exists in
the system (8088 or 8086 systems), or system logic
treats "ROM writes" as an invalid operation. In these
cases, perform all your required BIOS calls before you
erase and program the flash memory. But keep in mind,
to update the user on the progress of flash programming and indicate when programming is finished, you
should add some basic screen or speaker "beep" routines to your update utility.
4-373
AP-341
4.2 Pseudo-Code Overview
The following pseudo-code for an update utility provides a brief description of the process of updating a
BIOS in-situ. It is based on software developed by a
customer for a PC platform with BIOS update capability. This Inte1386-33 ·MHz system uses the 28FOOIBX
for BIOS storage. Modify the flowchart below, if needed, for your particular chipset and hardware environment.
Pseudo-Code for Flash Update Routine
,
\
.
Initialize system (set up user screen, check battery power, check device ID)
Get BIOS file options (from floppy or modem)
If no file present
Send error message to insert BIOS update floppy, or press ESC to exit
Display BIOS update files, prompt user for choice and
load to memory
If file invalid,
Prompt for file or exit
Inform user what is about to happen, with option to
continue or exit
If user continues, inform them to not turn off the
power or soft-reboot (CNTL-ALT-DEL)
Erase 28FOOIBX main/parameter blocks
If system interrupt occurs
Suspend erase if flash memory access is required
Resume Erase
Write fi~e[sl into flash memory
Indicate to user that flash reprogramming is over
Reboot the system
4.3 Initializing the System
Checking Power
If your application is' a laptop or palmtop computer,
first check the battery to make sure there is enough
power to do the update. If not, inform the user to recharge the system before continuing the update and exit
the update program. This ensures that the system won't
stop in the middle of an update. Next, Initialize access
to flash for reads and writes, then try reading the device
ID through the Command Register. Checking the device ID before programming or erasing helps determine
4-374
if'reads and 'writes work correctly and that the flash
memory in the system matches your code before starting to reprogram the part. The manufacturer ID for
Intel flash memories is 89H (10001001). located at device address oooooH. Device IDs are located at address
OOOOIH; the 10 for the 28FOOIBX-T is 94H
(10010100), and the 28FOOIBX-B device 10 is. 95H
(10010101). These device addresses, in the DOS memory map, correspond to system addresses EOOOOH (mfgr.
10) and EOOOIH (device 10). If A16 inversion is used
as described in Section 3.1, system addresses for mfgr.
ID and device. ID under normal operation are FOOOOH
and FOOOIH.
NOTE:
During the initialization, you can also perform,a scan
of the adaptor space to ascertain if there is more flash
in the system. Other Intel Flash Memories share common manufacturer IDs but have unique device IDs,
listed below:
Device
Device
ID (Hex)
DevicelD
(Binary)
28F256A
28F512
28F010
28F020
28F001BX-T
28F001BX-B
B9H
B8H
B4H
BOH
94H
95H
10111001
10111000
10110100
10111101
10010100
10010101
4.4 Code Loader Routine
The update utility described in the previous section
provides an optional mouse-driven color graphical user
interface (GUI) and allows not only BIOS update to
the main block but also update of the parameter blocks,
and copy/compare of block data to a DOS file. These
types of features convey to the end user the ease and
simplicity of performing a BIOS update. For example,
the main block update utility lists all possible BIOS
files in the selected drive and directory, and prompts
the user for the desired file. System OEMs may want to
encode a specific BIOS file name into the generic loader
utility ".COM" or ".EXE" file. This allows automatic
reading of the new BIOS file into a program buffer.
bypassing the user prompt.
Once the file is loaded into RAM, the routine informs
the user of the impending BIOS update and provides
the option to exit if desired. If continued, it warns the
user to not turn off power or reboot during the BIOS
update procedure. It then erases and reprograms the
main block with new BIOS data. notifies the user of
successful update and reboots.
I
AP-341
4.5 Flash Reprogramming·Routines
On-Chip Erase Algorithm
The 28FOOlBX system erase algorithm is shown in Figure 15. Note that the actual device erase algorithm
(Quick-Erase) is controlled internally, including all timing and block preconditioning. This provides the same
high level of reliability proven on Intel's ETOX II technology, while reducing system debug efforts. Erase
progress is reported to system software thru specific
Status Register bits. The 28FOOlBX erases all bits of a
block in parallel. Minimum and typical erase times for
each block are listed below:
I
Block
Minimum
Time (Sec)
Typical
Time (Sec)
Parameter (ea.)
Main
Boot
1.3
3.0
1.3
2.1
3.8
2.1
The actual erase time depends on the Vpp voltage level
(ll.4V -12.6V), temperature and the number of erase
cycles already completed on the part. System software
must comprehend adequate time for Vpp, after enabled,
to ramp to l2V before erase is attempted. Capacitors on
the Vpp bus, in addition to the intrinsic pump nature of
many 12V solutions, cause an RC ramp. Systems that
direct-wire 12V need not worry about this delay.
Erase Suspend/Resume
Erase suspend gives the user the ability, while erasing a
block of the 28FOOIBX, to read data or execute code
from another block. This capability, in conjunction
with the minimal system overhead provided by the
WSM, makes disabling of interrupts during block erase
unnecessary. Once given the erase suspend command,
the WSM halts, reports suspend status to the Status
Register and allows array reads. When issued erase resume, it proceeds at the point where it was suspended.
Figure 16 details the system code flowchart that suspends and resumes erase.
4-375
AP·341
Bus
Command
Comments
Write
Erase
Setup
Write
Erase
Data = 20H
Address = Within Block
to be erased
Data = DOH
Address = Within Block
to be erased
Operation
Read
Status Register Data.
ToggleOE# orCE# to
update Status Register
CheckSR.7
1 = Ready, 0 = Busy
Standby
Repeat for subsequent blocks.
Full status check can be done after each block or after
a sequence of blocks.
Write FFH after the last block erase operation to reset
the device to Read Array Mode.
292077-14
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
Check SR.4, 5
Both 1 = Command
Sequence Error
Standby
CheckSR.5
1 = Block Erase Error
vpp Range"
Error
Command Sequence
Error
Block Erase
Error
292077-15
SR.a MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 15. 28F001BX Block Erase Algorithm
4-376
I
intel®
Ap·341
Bus
Operation
Command
Comments
Wfite
Erase
Suspend
Data = BOH
Write
Read
Status Register
Data = 70H
Standbyl
Read
Read Status Register
Check SR.7
1 = Ready. 0 = Busy
Toggle OE# or CE#
to update Status
Register
Standby
CheckSR.6
1 = Suspended
Write
Read Array
Read array data from
block other than that
being erased.
Read
Write
Data = FFH
Erase Resume
Data = DOH
292077-16
Figure 16. 28F001BX Erase Suspend/Resume Algorithm
I
4-377
AP-341
Bus
Operation
Command
Write
Program
Setup
Write
Program
Comments
Data.= 40H
Address = Byte to
be programmed
Data to be Programmed
Address '" Byte to
be programmed
Read
Status Register Data.
ToggleOE# orCE# to
update Status Register
Standby
CheckSR.7
1 = Ready, 0 = Busy
Repeat for subsequent bytes.
Full status check can be done after each byte or after
a sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
292077-17
FULL STATUS CHECK PROCEDURE
Bus
Operation
Command
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
CheckSR.4
1 = Byte Program Error
SR.3 MUST be cleared, if set during a program
attempt, before further attempts are allowed by the
Write State Machine.
292077-18
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are
programmed before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 17. 28F001BX Byte Programming Algorithm
4-378
I
AP-341
On-Chlp Programming Algorithm
As with 28FOOIBX erase, the Intel flash Quick-Pulse
algorithm is internally controlled by the WSM. Figure
17 shows a system software flowchart for the Command Register/Status Register interface. Minimum
and typical programming times (per byte) are 15 /Ls
and 18 /Ls, respectively. Actual time varies with Vpp,
temperature and cumulative programming cycles on
the device. Ensure that stable 12V is applied to the
device before attempting byte programming.
Full Status Checks
After polling the Status Register and determining that
the WSM is again READY, system software should
further analyze the Status Register to ensure that program or erase has successfully completed. The WSM
will return to READY status after program or erase
. command sequences under any of the following conditions:
• Program/erase completed successfully,
• Vpp transition below specification during the program/erase attempt,
• Improper sequence of erase setup/confirm commands to the WSM, or
• Inability to erase the specified block, or program the
desired byte.
Figures 15 and 17 detail the additional Status Register
data analysis to ensure that program or erase have successfully occurred.
4.6 Recovery Routine Overview
Unsuccessful BIOS update can occur for any of the
reasons listed below:
1. Vpp transitions out of specified tolerance during
program or erase.
2. Incorrect code in the update BIOS disk file, or damaged BIOS disk.
3. Loss of system power during program or erase.
4. System reset (such as reboot) during program or
erase.
The Status Register, through bit 3, reports VpPH loss to
system software. The BIOS update utility can detect
scenario 1 and recover by simply re-attempting block
update.
A checksum of update BIOS code after copy from disk
to RAM, before flash erase and reprogram, will eliminate error caused by scenario 2.
I
PC motherboard logic should gate the 28FOOIBX RP#
pin with both POWER GOOD and RESET # signals,
to abort program or erase attempts if either scenario 3
or 4 were to occur. This allows the processor to execute
code out of the 8 Kbyte boot block upon system recovery. System reset or loss of system power will clear the
Status Register to value 80H, leave the block being updated partially programmed or erased and reset the
28FOOIBX to Read Array mode. As detailed previously
in Section 3.1, a checksum of the main block will alert
the system to an incomplete BIOS. Recovery is
achieved by the following or similar steps:
• Initialize CPU and system logic.
• Initialize the system floppy disk.
• Prompt the user to insert a BIOS diskette, through
speaker "beep".
• Erase and reprogram the main and/or parameter
blocks with file data.
• Reboot
4.7 Power Management
Battery-powered PCs incorporate a variety of techniques to prolong system life between recharges. Typically, power management software senses user inactivity and shuts off power-intensive sections of the system.
Options include:
•
•
•
•
Display powerdown
Disk/hard drive powerdown
System clock slowdown or suspend, and
Powerdown of non-volatile circuitry in the system.
The 28FOOIBX fits the latter description. When the
RP# pin transitions to GND,the device enters an ultra-low power mode, typically consuming 0.25 /LW
thm Vee. This technique can also be used to power
down the BIOS memory after BIOS code has been
shadowed to DRAM, if available in the system. When
not programming or erasing the 28FOOIBX; the system
should shut off 12V Vpp to the part to minimize current draw through this supply.
User inactivity is typically detected if the keyboard has
not been used, or the disk drive has not been accessed,
for a predetermined interval (this is often user-programmable). Power management software must ensure
that a BIOS update is not occurring, before powering
down the 28FOOlBX, to prevent incomplete update.
For more information on power management techniques, consult datasheets and application notes on the
Intel386SL microprocessor superset.
4-379
AP·341
5.0
SUMMARY
5.1 Traditional BIOS Storage and
Disadvantages
Traditional BIOS storage has been in EPROM, which
offers non volatility and factory programming capability. In earlier PCs, the BIOS code was fairly simple (relative to today's software) and updates were infrequent,
so EPROMs or ROMs were an acceptable BIOS storage medium. Today's systems are much more sophisticated, with many designs supporting the Intel
i386/i486TM microprocessors and new bus architectures like MCA and EISA for the first time. These new
buses allow peripherals to take control of. the system
bus ... it is difficult to guess what new system configurations might emerge. Therefore, the potential for a
change in the BIOS code is much greater and the frequency of change is likely to increase.
A system designer may use EPROMs for BIOS storage
to reduce initial system (component) costs, but the
long-term update cost is much more than the difference
between EPROM and flash memory components. A
major manufacturer of PCs has estimated that a service
call for a BIOS update with EPROMs can cost upwards of $300.00 for ONE update at ONE site.
EPROMs are also susceptible to bent leads during insertion by the technician, or more likely, the end user.
Service is becoming a key differentiator between the
multitudes of PC makers. Reducing the number of
times a PC has to be opened for any reason and providing improved service increases customer confidence and
promotes a reliable image.
5.2 Advantages of an Updatable BIOS
Using flash memory for BIOS storage provides a flexible code medium that allows the BIOS code to adapt to
changing hardware and software conditions. BIOS updates in flash are inexpensive, via a floppy disk or modem. They remove EPROM inventories, reduce packaging requirements, reduce total postage costs and
eliminate service cost for BIOS code updates by removing the need for a technician to do the update. A company that supports mutiple OEMs can improve version
management control by using a flash BIOS and floppies
or a BBS for updates. An additional benefit is that not
only the BIOS, but DOS itself can be stored in the same
flash memory device.
5.3 Advantages of Adding DOS in
FLASH
Once the requirements for flash memory BIOS are met,
the capability is also in place for adding DOS in
FLASH. Why put DOS in FLASH? For laptop and
4-380
palmtop PCs, battery longevity is of paramount concern, followed closely by weight and increasing user
RAM (640KB) space. Extra user RAM is needed for
applications that require more than the typical
570 Kbytes (640 KB- 70 KB) available with disk-based
DOS. Digital Research Incorporated and Microsoft
both make "DOS-in-ROM" products that address
these needs. MS-DOS ROM version 3.22 is an example.
Microsoft's MS-DOS ROM Version 3.22 is a full-function version of MS-DOS 3.2. It features instant-on and
employs only 15 KB of the 640 KB DOS RAM user
space, leaving the rest for applications. Since MS-DOS
ROM Version 3.22 loads from adaptor space, both disk
access and DOS loadtime are reduced. For laptops,
anything that can reduce disk access equates to battery
longevity. Laptops can reduce weight by using MSDOS ROM Version 3.22 and replacing the floppy drive
with an IC card. Adding MS-DOS ROM Version to
desktops also liberates additional user RAM for the
same above reasons, but may not be optimal for high
speed 32-bit systems.
All future versions of MS-DOS will be supported with
equivalent versions of MS-DOS ROM. See Appendix B
for more information.
5.4 Advantages of Adding
1 MB-4 MB of Resident Code
Storage
There is a growing need for systems to be able to provide a small suite of bundled applications. Benefits to
the user are faster application execution thru reduced
hard or floppy disk access, no power used to store the
resident code, and instant-on. No time is wasted transferring data over a disk I/O interface. The code is
instead loaded to RAM with a simple memory copy
function or procedure. In some cases, code is directly
executed by the processor. Tandy's Deskmate is an example of such a system. Future versions of Deskmatelike user interfaces could easily be made flash-updatable. SRAM is too expensive and requires power to just
store files. Furthermore, battery backup is not a reliable
means of achieving nonvolatility. Intel's Flash Memory
can provide user configurability for 1 MB-4 MB of
code storage for just 2x-3x the cost of EPROMs and
less than half the cost of SRAM. Applications such as
Lotus 123, WordPerfect and Microsoft Works also
come in either a direct-execute "ROM" version or a
load-from-ROM format. Many other ROM application
software packages are in development, servicing the
successful and growing needs of the laptop/palmtop
computers. Therefore, if an application can be stored or
runs from ROM, it can be stored and run from flash.
As software packages are periodically updated, flash
memory provides the capability of updating these
"ROM" applications at little cost to the software vendor and with no system disassembly required.
I
AP-341
APPENDIX A
SOFTWARE ROUTINES
/*************************************************************************************/
/* Copyright Intel Corporation, 1991
*/
/* Brian Dipert, Intel Corporation, July 14, 1991, Revision 1.4
*/
/* The following drivers control the Command and Status Registers of
*/
/*
the 28F001BX Flash Memory to drive byte program, block erase, Status
*/
/*
Register read and clear and array read algorithms.
*/
/*
Sample Vpp and RP# control blocks are' also included.
*/
/* The functions listed below are included:
*/
/*
erasbgn(): Begins block erasure
*/
/*
erassusp(): Suspends erase to allow reading data from a block of the
*/
/*
28F001BX other than that being erased
*/
/*
erasres(): Resumes erase if suspended
*/
/*
end() :
Polls the Write State Machine to determine if block erase or
*/
/*
byte program have completed
*/
/*
eraschk(): Executes full status check after erase completion
*/
/*
progbgn(): Begins byte programming
*/
/*
progchk(): Executes full status check after byte program completion
*/
/*
idread() :
Reads and returns the manufacturer and device IDs of the
*/
/*
target 28F001BX
*/
/*
statrd() :
Reads and returns the contents of the Status Register
*/
/*
statclr(): Clears the Status Register
*/
/*
rdmode():
Puts the 28F001BX in Read Array mode
*/
/*
rdbyte():
Reads and returns a specified byte from the target 28F001BX
*/
/*
vppup() :
Enables high voltage Vpph
*/
/*
vppdown(): Disables Vpph
*/
/*
pwdon() :
Ramps the RP# pin to high voltage Vhh, enabling boot block
*/
/*
program/erase
*/
/*
pwdoff():
Disables high voltage Vhh on RP#, disabling program
*/
/*
and erase of boot block
*/
/*
*/
/* Addresses are transferred to functions as pointers to far bytes (ie long
*/
/*
integers). An alternate approach 1s to create a global array the size of the
*/
/*
28F001BX and locate "over" the 28F001BX in the system memory map. Accessing
*/
/*
specific locations of the 28F001BX is then accomplished by paSSing the chosen
*/
/*
function an offset from the array base versus a specific address. Different
*/
/*
microprocessor architectures will require different array definitions; ie for
*/
/*
the Intel architecture, define it as "byte boot [2][10000]" and pass each
*/
/*
function TWO offsets to access a specific location. MCS-51 architectures
*/
/*
are limited to "byte boot [10000] " ; alternate approaches such as writing to
*/
/*
control bits will be required to access the full flash array
*/
/*
*/
/* To create a far pointer, a function such as MK_FP() can be used, given
*/
/*
a segment and offset in the Intel architecture. I use Turbo-C; see your
*/
/*
compiler reference manual for additional information.
*/
/***************************************************** ********************************1
I
4-381
AP-341
/***********************************************************************************/
/* Revision History: Rev 1.4
*/
/*
*/
/* Changes from 1.0 to 1.1: Added typedef for "byte" to accurately reflect
*/
/*
this x8 device. Altered variable definitions accordingly. Combined
*/
/*
functions progend() and erasend() into function end().
*/
/*
*/
/* Changes from 1.1 to 1.2: Added this revision history block. Added above
*/
/*
comments on alternate addressing methods.
*/
/*
*/
/* Changes from 1.2 to 1.3: Added pass/fail error return from idread(),
*/
/*
idread() at beginning of progbgn() and erasbgn(), pass/fail error
*/
/*
return from progbgn() and erasbgn().
*/
/*
*/
/* Changes from 1.3 to 1.4: Revised code to reflect simplified program and
*/
/*
erase algorithms. 28FOOIBX automatically transitions to Read Status Register */
/*
mode after program command sequence, erase command sequence and remains in
*/
/*
Read Status Register mode after Erase Suspend is issued. Address OOOOH is no */
/*
longer required to read or clear the Status Register.
*/
/***************************************************** ******************************1
typedef unsigned char byte;
/***************************************************** ******************************1
/* Function: Main
*/
/* Description: Included only to omit errors when attempting to compile code.
*/
/* The end customer would insert their main program here.
*/
/***********************************************************************************/
main()
(
)
/~**************************************************** ******************************1
/*
/*
/*
/*
1*
/*
/*
Function: Erasgbn
Description: Begins erase of a block.
Inputs: blckaddr: System address within the block to be erased
Outputs: None
Returns: 0 = Erase successfully initiated
1 = Erase not initiated (ID check error)
Device Read Mode on Return: Status Register (ID if returns 1)
*/
*/
*/
*/
*/
*/
*/
/******************************.********************** **************************~****I
#define ERA SETUP
#define ERASCONF
OX20
OXDO
/* Erase Setup command
/* Erase Confirm command
*/
*/
/* blckaddr is an address within the block to be
erased
/*
*/
*/
/* ID read error; device not powered up?
*/
/* Write Erase Setup command to block address
/* Write Erase Confirm command to block address
*/
*/
int erasbgn(blckaddr)
byte far *blckaddr;
if (idread()==l)
return (1);
*blckaddr = ERASETUP;
*blckaddr = ERASCONF;
return (0);
l
4-382
I
AP-341
/************************************************************************************/
1* Function: Erassusp
*1
1*
Description: Suspends block erase to read from another block
*1
1*
Inputs: None
*I
1*
Outputs: None
*I
1*
Returns: 0 = Erase suspended
*1
1*
1 = Error; Write State Machine not busy (erase suspend not possible) *1
1*
Device Read Mode on Return: Read Status Register
*1
/***************************************************** *************************~*****I
#define RDYMASK
OX80
#define WSMRDY
OX80
#define SUSPMASK
OX40
1* Mask to isolate the WSM Status bit of the
Status Register
1*
1* Status Register value after masking, signifying
that the WSM is no longer busy
1*
I*Mask to isolate the Erase Suspend Status bit of the
Status Register
/* Status Register value after masking, signifying
/*
that erase has been suspended
/* Read Status Register command
/* This constant can be initialized to any address
/*
within the memory map of the target 28F001BX
/*
and is alterable depending on the system
/*
architecture
/* Erase Suspend command
1*
#define ESUSPYES
OX40
#define STATREAD
#define SYSADDR
OX70
#define SUSPCMD
o
OXBO
*1
*1
*/
*1
*1
*1
*1
*/
*/
*/
*1
*1
*/
*/
int erassusp ()
byte far *stataddr;
/* Pointer variable used to write commands to device
stataddr
(byte far *)SYSADDR;
*stataddr = SUSPCMD;
/* Write Erase Suspend command to the device
*stataddr = STATREAD;
/* Write Read Status Register command to 28F001BX
while (( *stataddr 3: RDYMASK) != WSMRDY)
1* Will remain in while loop until bit 7 of the
/*
Status Register goes to 1, signifying that the
/*
WSM is no longer busy
if ((*stataddr 3: SUSPMASK) -- ESUSPYES)
return(O) ;
/* Erase is suspended ••• return code "0"
1* Erase has already completed; suspend not possible.
return(l) ;
/*
Error code "1"
I
*/
*1
*1
*/
*/
*/
*/
*/
*/
4-383
Ap·341
/**********************************************************************************/
/* Function: Erasres
*/
/*
Desoription: Resumes block erase. previously suspended
*/
/*
Inputs: None
*/
/*
Outputs: None
*/
/*
Returns: 0 = Erase resumed
*/
/*
1 = Error; Erase not suspended when function called
*/
/*
Device Read Mode on Return: Status Register
*/
/**********************************************************************************/
#define RDYMASK
oxeo
#define WSMRDY
OX80
#define SUSPIMSK
OX40
#define ESUSPYES
OX40
#define STATREAD
#define SYSADDR
OX70
.0
#define RESUMCMD
OXDO
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
Mask to isolate the WSM Status bit of the
Status Register
Status Register value after masking, signifying.
that the WSM is no longer busy
Mask to isolate the Erase S~spend Status bit
of the Status Register
Status Register value after masking, signifying
that erase has been suspended
Read Status ,Register Command
This constant can be initialized to any
address within the memory map of the target
28F001BX and is alterable depending on the
system architecture
Erase Resume Command
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
~/
*/
*/
int erasres( )
byte far *stataddr;
/* Pointer variable used to write commands to device
stataddr = (byte far *)SYSADDR,
*stataddr = STATREAD.;
/* Write Read Status Register command to'28F001BX
if «*stataddr & SUSPMASK) != ESUSPYES)
return (1);
/* Erase not suspended. Error oode "1"
. *stataddr = RESUMCMD;
/* Write Erase Resume command to the device
while «*stataddr & SUSPMASK) = ESUSPYESl,
/* Will remain in while loop until bit 6 of the
/*
Status Register goes to 0, signifying
/*
erase resumption
while «*stataddr & RDYMASK)
WSMRDY)
/* Will remain in while loop until bit 7 of the
/*
Status Register goes to 0, signifying
/*
that the WSM is once again busy
return (0);
==
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
1
4·384
I
AP-341
/**********************************************************************************/
/* Function: End
*/
/*
Description: Checks to see if the WSM is busy
*/
/*
(is program/erase completed?)
*/
/*
Inputs: None
*/
/*
Outputs: statdata: Status Register data read from device
*/
/*
Returns: 0 = Program/Erase completed
*/
/*
1
Program/Erase still in progress
*/
/*
Device Read Mode on Return: Status Register
*/
/**********************************************************************************/
=
#define RDYMASK
OX80
#define WSMRDY
OX80
#define STATREAD
#define SYSADDR
OX70
0
1*
/*
1*
/*
1*
1*
Mask to isolate the WSM Status bit of the
Status Register
Status Register value after masking, signifying
that the WSM is no longer busy
Read Status Register command
This constant can be initialized to any
address within the memory map of the target
/*
28F001BX and is alterable depending on the
/*
system architecture
/*
*/
*/
*/
*/
*/
*/
*/
*/
*/
/* Allows Status Register data to be passed back
/*
to the main program for further analysis
*/
*/
int end (statdata)
byte *statdata;
byte far *stataddr;
/* Pointer variable used to write commands to
/*
device
stataddr
(byte far*)SYSADDR;
*stataddr = STATREAD;
/* Write Read Status Register command to 28F001BX
i f (( (*statdata = *stataddr) Ilc RDYMASK) != WSMRDY)
return (1);
1* Program/erasure still in progress ••• code "1"
return (0);
/* Program/erase attempt completed ••• code "0"
=
*/
*/
*/
*/
*/
J
I
4-385
AP-341
1**********************************************************************************1
1* Function: Eraschk
~I
1*
Description: Completes full Status Register check for erase (proper
*1
1*
command sequence, Vpp low detect, erase success). This routine assumes
*1
1*
that erase completion has already been checked in function end() and
*1
1*
therefore does not check the WSM Status bit of the Status Register
*1
1*
Inputs: statdata: Status Register data read in function end
*1
1*
Outputs: None
*1
1*
Returns: 0 = Erase completed successfully
*1
1*
1 =Error; Vpp low detect
*1
1*
2 = Error; 'Block erase error
*1
1*
3 = Error; Improper command sequencing
*1
1*
Device Read Mode on Return: Same as when entered
*1
1**********************************************************************************1
#define ESEQMASK
OX30
#define ESEQFAIL
OX30
#define ERRMSK
OX20
#define ERASERR
OX20
#define VLOWMASK
OX08
#define VPPLOW
OX08
1* Mask to isolate the Erase and Program
Status bits of the Status Register
1*
1* Status Register value after masking if erase
command sequence error has been detected
1*
1* Mask to isolate the Erase Status bit of the
Status Register
1*
1*
1*
1*
1*
1*
1*
*1
*1
*1
*1
*1 '
*1
Status Register value after masking if erase error *1
has been detected
*1
Mask to isolate the Vpp Status bit of the Status
*1
Register
*1
Status Register value after masking i f Vpp low
*1
has been detected
*1
int eraschk(statdata)
1* ,Status Register data that has been already read
byte stat data ;
1*
if «statdata & VLOWMASK)
return (1) ;
if «statdata & ERRMSK)
return (2);
if '«statdata & ESEQMASK)
return (3);
return (0);
from the 28F001BX in function end()
== VPPLOW)
1* Vpp low detect error, return code "1"
== ERASERR)
1* Block erase
== ESEQFAIL)
error detect, return code "2"
1* Erase command sequence error, return code "3"
1* Block erase success, return code ·0"
*1
*1
*1
*1
~I
*1
}
4-386
I
AP-341
/********************************************************************************/
1* Function: Progbgn
1*
Description: Begins byte program sequence
1*
Inputs: pdata: Data to be programmed into the device
1*
paddr: Target address to be programmed
1*
Outputs: None
1*
Returns: 0 = Program successfully initiated
1*
1 = Program not initiated (ID check error)
1*
Device Read Mode on Return: Status Register (ID if returns 1)
*1
*1
*1
*I
*I
*1
*1
*1
/********************************************************************************/
#define SETUPCMD
I*Program Setup command
*1
byte pdata;
byte far *paddr;
1* Data to be programmed into the 28FOOIBX
1* paddr is the destination address for the data
1*
to be programmed
*1
*1
*1
if (ldread(,) = 1)
return (1);
*paddr
SETUPCMD;
1* Device ID read error ••• powered up?
*1
1* Write Program Setup command and
1*
destination address
*paddr = pdata;
1* Write program data
and destination address
1*
*1
*1
*1
*1
OX40
int progbgn (pdata,paddr)
return (0);
I
I
4-387
AP-341
/**********************************************************************************/
/* Function: Progchk
*/
Description: Completes full Status Register check for byte program (Vpp low */
detect, programming success). This routine assumes that byte program
*/
completion has already been checked in function end() and
*/
/*
therefore does not check the WSM Status.bit of the Status Register
*/
/*
Inputs: statdata: Status Register data read in function end
*/
/*
Outputs: None
*/.
/*
Returns: 0 = Byte programming completed successfully
*/
/*
1 = Error; Vpp low detect
*I
/*
2 = Error; Byte program error
*/
/*
Device Read Mode on Return: Status Register
*/
/***************************************************** *****************************1
/*
/*
/*
OXlO /* Mask to isolate the-Program Status bit of the
/*
Status Register
#define PROGERR OX10 /* Status Register value after masking if program
/*
error has been detected
#define VLOWMASK OXOS /* Mask to isolate the Vpp Status bit of the Status
/*
Register
#define VPPLOW
OXOS 1* Status Register value after masking if Vpp low
/*
has been detected
#define PERRMSK
*/
*/
*/
*/
*/
*/
*/
*/
int progchk (statdata)
byte stat data ;
/* Status Register data that has been already read
/*
from the 2SF001BX in function end()
==
==
if «statdata & VLOWMASK)
VPPLOW)
return (1);
/* Vpp low detect error, return code "1"
if «statdata & PERRMSK)
PROGERR)
return (2);
/* Byte program error detect, return code "2"
return (0);
1* Byte/string p~ogram success, return code "0"
*/
*/
*/
*/
*/
J
4-388
I
AP-341
/************************************************************************************/
/* Function: Idread
*/
/*
Description: Reads the manufacturer and device IDs from the target 28F001BX
*/
/*
Inputs: None
*/
/*
Outputs: mfgrid: Returned manufacturer ID
*/
/*
deviceid: Returned device ID
*/
/*
Returns: 0 = ID read correct
*/
1*
1 = Wrong or no ID
*/
/*
Device Read Mode on Return: Intelligent Identifier
*/
/************************************************************************************/
#define MFGRADDR
0
#define DEVICADD
1
#define IDRDCOMM
#define INTELID
#define DVCIDBT
OX90
OX89
OX94
1* Address "0" for the target 28F001BX •••
alterable depending on the system
/*
architecture
/*
/* Address "1" for the target 28F001BX •••
alterable depending on the system
1*
architecture
1*
/* Intelligent Identifier command
/* Manufacturer ID for Intel devices
/* Device ID for 28F001BX-T: change to 95H if
using 28F001BX-B!!!
/*
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
/* The manufacturer ID read by this function, to
be transferred back to the calling
program
/*
/* The device ID read by this' function, to be
transferred bacle to the calling function
/*
*/
*/
*/
*/
*/
/* Pointer address variable used to read IDs
*/
int idread(mfgrid,deviceid)
byte *mfgrid:
1*
byte *deviceid:
byte far *tempaddr:
tempaddr = (byte far*)MFGRADDR:
*tempaddr= IDRDCOMM:
/* Write intelligent identifier command to an
/*
address within the 28F001BX memory map
/*
(in this case, OOH)
*mfgrid = *tempaddr;
/* Read mfgr ID, tempaddrstill points at address "0"
tempaddr = (byte far*)DEVICADD:/* Point to address "1" for the device specific ID
*deviceid= *tempaddr:
/* Read device ID
if (( *mfgrid != INTELID) II (*deviceid != DVCIDBT))
return (1):
/* ID read error: device powered up?
return (0):
*/
*/
*/
*/
*/
*/
*/
I
I
4-389
Ap·341
/********************************************************************************/
/* Function: Statrd
*/
/*
Description: Returns contents of the target 28F001BX Status Register
*/
/*
Inputs: None
*/
/*
Outputs: statdata: Returned Status Register data
*/
/*
Returns: Nothing
*/
/*
Device Read Mode on Return: Status Register
*/
/***************************************************** ***************************1
#define STATREAD
#define SYSADDR
OX70
0
/* Read Status Register command
/* This constant can be initialized
to any address within the
/*
memory map of the target 28FOO1BX
1*
and is alterable depending on
1*
the system architecture
/*
*/
*/
*/
*/
*/
*/
/* Allows Status Register data to
be passed back to the calling program
/*
for further analysis
1*
*/
*/
*/
int statrd(statdata)
byte *statdata;
byte far *stataddr;
stataddr
*stataddr
*statdata
return;
/* Pointer variable used to write
/*
commands to device
= (byte far*)SYSADDR;
= STATREAD;
/* Write Read Status Register
/*
command to 28F001BX
*stataddr:
=
*/
*/
,*/
*/
)
4-390
I
AP-341
/**********************************************************************************/
/*
/*
,.
/*
/*
/*
Function: Statclr
Description: Clears the 28FOOlBX Status Register
Inputs: None
Outputs: None
Returns: Nothing
Device Read Mode on Return: Status Register
*/
*/
*/
*/
*/
*/
/**********************************************************************************/
#define STATCLER
#define SYSADDR
OX50
o
/* Clear Status Register command
*/
/* This constant can be initialized to any
*/
/*
address ~ithin the memory map of the target*/
/*
28FOOlBX and is alterable depending on
*/
/*
the system architecture
*/
int statclr ()
byte far *stataddr;
/* Pointer variable used to write commands to
/*
device
stataddr = (byte far*)SYSADDR;
*stataddr = STATCLER;
/* Write Clear Status Register command to
/*
28FOOlBX
return;
*/
*/
*/
*/
I
/**********************************************************************************/
1* Function: Rdmode
*/
/*
Description: Puts the target 28FOOlBX in Read Array Mode. This function
*/
/*
might be used, for example, to prepare the system for return to code
*/
/*
execution out of the flash memory after program or erase algorithms
*/
/*
have been executed off-chip
*/
/*
Inputs: None
*/
,.
Outputs: None
*/
,.
Returns: Nothing
*/
,.
Device Read Mode on Return: Array
*/
/***************************************************** ****************************1
#define RDARRAY
#define SYSADDR
OXFF
0
1* Read Array command
/* This constant can be initialized to any
address within the memory map of the target
/*
28FOOlBX and is alterable depending on
1*
the system architecture
/*
*/
*/
*/
*/
*/
int rdmode ( )
/* Pointer variable used to write commands to
/*
device
(byte far*)SYSADDR;
RDARRAY;
/* Write Read Array command to 28FOOIBX
byte far *tempaddr;
tempaddr
*tempaddr
=
*/
*/
*/
return;
I
I
4-391
AP-341
1***************************************************** *****************************/
/* Function: Rdbyte
*/
/*
Description: Reads a byte of data from a specified address and
*/
/*
returns it to the calling program
*/
/*
Inputs: raddr: Target address To be read from
*/
/*
Outputs: rdata: Data at the specified address
*/
/*
Returns: Nothing
*/
/*
Device Read Mode on Return: Array
*/
/**********************************************************************************/
#define RDARRAY
OXFF
/* Read array command
*/
/* Returns data read from the device at
/*
specified address
/* Raddr is the target address to be read from
*/
*/
*/
/* Write read array command to an address within
the 28F001BX memory map (in this case the
/*
target address)
1*
/* Read from the specified address and store
*/
*/
*/
*/
int rdbyte (rdata. raddr'j
byte
~rdata;
byte far *raddr;
*raddr = RDARRAY;
*rdata = *raddr;
return;
I
4·392
I
Ap·341
/**********************************************************************************/
/* Function: Vppup
*/
Description: Ramps the Vpp supply to the target 28FOOIBX to enable
*/
1*
programming or erase. This routine can be tailored to the individual
*/
1*
system architecture. For purposes of this example, I assumed that a
*/
1*
system Control Register existed at system address 20000 hex.
*/
1*
with the following definitions:
*/
/*
/*
*/
Bit 7: Vpph Control:
1 = Enabled
*/
1*
o Disabled
*/
/*
Bit 6: PWD Control:
1
PowerDown Enabled
/*
*/
o = PowerDown Disabled
*/
1*
Bits 5-0: Undefined
*/
1*
Inputs: None
/*
*/
Outputs: None
*/
1*
Returns: Nothing
/*
*/
Device Read Mode on Return: As existed before entering the function.
/*
*/
Part is now ready for program or erase command sequence
*/
/*
/**********************************************************************************/
#define VPPHIGH
#define SYSCADDR
OX80
OX20000
=
/* Bit 7
1, Vpp elevated to Vpph
*/
/* Assumed system Control Register Address */
int vppup()
byte far *contaddr;
contaddr
*contaddr
= (byte far*)SYSCADDR;
= *contaddr I VPPHIGH;
/* Pointer variable used to write data
/*
to the System Control Register
*/
/* Read current Control Register data,
/*
nORn with constant to ramp Vpp
*/
*/
*/
return;
l
I
4-393
Ap·341
/***********************************************************************************/
/* Function: Vppdown
*/
/*
Description: Ramps down the Vpp supply to the target 28F001BX to
*/
/*
disable programming/erase. See above for a description of the
*/
/*
assumed system Control Register.
*/
1*
Inputs: None
*/
/*
Outputs: None
*/
1*
Returns: Nothing
*/
/*
Device Read Mode on Return: As existed before entering the function. Part
*/
/*
now has high Vpp disabled. If program or erase was in progress when
*/
/*
this function was called, it will complete unsuccessfully with Vpp low error */
/*
in the Status Register.
*/
I********·*******~************************************ ******************************/
#define VPPDWN
OX7F
/* Bit 7 = 0, Vpp lowered to Vppl
*/
#define SYSCADDR
OX20000 /* Assumed system Control Register Address
*/
int vppdown ()
byte far *contaddr;
contaddr
/* Pointer variable used to write data to the
/*
system Control Register
(byte far*)SYSCADDR;
*contaddr = *contaddr & VPPDWN;
/* Read current Control Register data, "AND" with
/*
constant to lower Vpp
return;
*/
*/
*/
*/
I
4-394
I
AP-341
/**********************************************************************************/
/* Function: Pwdon
*/
/*
Description: Toggles the 28F001BX RP# pin low to put the device in Deep
*/
/*
PowerDown mode. See above for a description of the assumed
*/
1*
system Control Register.
*/
/*
Inputs: None
*/
1*
Outputs: None
*/
/*
Ret urns: Nothing
*/
/*
Device Read Mode on Return: The part is powered down. If program or erase
*/
/*
was in progress when this function was called, it will abort with
*/
/*
resulting partially programmed or erased data. Recovery in the form of
*/
/*
repeat of program or erase will be required once the part
*/
/*
transitions out of powerdown, to initialize data to a known state.
*/
/***************************************************-*******************************/
#define PWD
#define SYSCADDR
OX40
OX20000
/* Bit 6 = 1, RP# enable
/* Assumed system Control Register Address
*/
*/
/* Pointer variable used to write data to the
1*
system Control Register
*/
int pwdon()
byte far *contaddr;
contaddr = (byte far*)SYSCADDR;
*contaddr = *contaddr I PWD; /* Read current Control Register data, nORn with
/*
constant to enable Deep PowerDown
return;
*/
*/
*/
l
I
4-395
AP-341
1***************************************************** *******************************/
/*
Function: Pwdoff
*/
Description: Toggles the 28F001BX RP# pin high to transition the part
*/
out of Deep PowerDown. See above for a description of the assumed system
*/
Control Register.
*/
/*
Inputs: None
*/
/*
Outputs: None
*/
/*
Returns: Nothing
*/
/*
Device Read Mode on Return: Read Array mode. Low voltage is removed
*/
/*
from RP#. 28F001BX output pins will output valid data time tPHQV
*/
/*
after the RP# pin transitions high (reference the datasheet AC
*/
/*
Read Characteristics) assuming valid states on all other control
*/
/*
and power supply pins.
*/
1***************************************************** *******************************/
/*
/*
/*
#deUne PWDOFF
#define SYSCADDR
OXBF
OX20000
/* Bit 6 = O. RP# disabled
/* Assumed system Control Register Address
*/
*/
/* Pointer variable used to write data to the
/*
system Control Register
*/
*/
int pwdoff ( )
byte far *contaddr;
contaddr = (byte far*)SYSCADDR;
*contaddr = *contaddr Be PWDOFF; /* Read current Control Register data. "AND" with
/*
constant to disable Deep PowerDown
return;
*./
*/
}
4-396
I
AP-341
APPENDIX B
MS-DOS ROM VERSION OVERVIEW
Technical Highlights
(Taken from Microsoft Product Overview)
RAM Economy
Because MS-DOS ROM Version executes from ROM,
only 15 KB of system RAM space is required for MSDOS. For a typical user, this will result in a savings of
about 40 KB of RAM over disk-based MS-DOS. As a
result of this savings, the user is able to run more programs and work with larger data files with the ROM
Version than with disk-based MS-DOS. Instant-On
MS-DOS ROM Version provides a significant reduction in "boot time", or the amount of time it takes from
the completion of the power-on self test until a DOS
prompt appears. With the ROM Version, this typically
takes one second.
No End-User Installation
MS-DOS ROM Version is pre-installed by the OEM
(original equipment manufacturer) in the system, thus
freeing end users from the task of installing MS-DOS.
Adaptable to OEM Hardware Platforms
MS-DOS ROM Version is structured such that it allows the OEM to include a specific routine to determine which drive to boot from and any specific parameters if booting from the ROM drive. This makes it
possible to easily port the ROM Version to a wide variety of hardware environments. MS-DOS ROM Version
I
is also positioned independent, in that it can reside anywhere in the "reserved" space (the area between
640 KB and 1 MB). This provides an additional Version to the specific requirements of the OEM's hardware platform.
ROM Economy
MS-DOS ROM Version occupies only 62 KB of ROM
space, thus minimizing the amount of ROM that an
OEM must include in the system. Three modules reside
in the reserved space: COMMAND.COM, IO.SYS and
the DOS Kernel. All three are position independent, so
an OEM can decide where to place these modules in the
reserved area.
National Language Support
Microsoft offers a full compliment of localized version
of MS-DOS ROM Version, including Kanji and Chinese translations.
Ease of Development
As PCs become the engines for many embedded applications, manufacturers would like to develop new applications utilizing existing PC software tools. MS-DOS
ROM allows manufacturers to take full advantage of
these tools. For instance, a programmer can develop
and debug an application onto a PC subsystem which
may be embedded into a larger system. This benefit
translates into a cost savings when developing a solution for vertical markets.
4-397
AP-341
APPENDIX C
BIOS VENDOR INFORMATION
American Megatrends Inc. (AMI)
1346 Oakbrook Drive, Suite 120
Norcross, GA 30093
(404) 263-8181
Award Software Inc.
130 Knowles Drive
Los Gatos, CA 95030
(408) 370-7979
This list is intended for example only, and in no way
represents all companies that support BIOS software.
Since this industry developes many new solutions each
year, Intel recommends that the designer contact the
vendors for their latest products. Intel will continue to
work with BIOS vendors to develop optimum solutions.
Intel Corporation assumes no responsibility for circuitry or software other than circuitry embodied in Intel
products. No software patent licenses are implied.
Phoenix Technologies, LTD.
40 Airport Parkway
San Jose, CA 95110
(408) 452-6500
Systemsoft Corporation
313 Speen Street
Natick, MA 01760
(508) 651-0088
4-398
I
AP-341
APPENDIX D
MICROPROCESSOR/MICROCONTROLLER
COMPATIBILITY CHART
28FOO1BX-T
28FOO1BX-B
x86 Family
i960 KA/KB Microprocessor
i860™ Family
i960 SA/SB Microprocessor
i960 CA Microprocessor
MCS®-51 Family
MCS®-96 Family
REVISION HISTORY
Number
-005
Description
Changed PWD# to RP# to match JEDEC naming conventions.
Updated RP# control circuitry of Figure 7.
I
4-399
int:et
AP-363
\
APPLICATION
NOTE
Extended Flash Bios Concepts
For Portable Computers
SALIM FEDEL
SENIOR APPLICATIONS ENGINEER
October 1993
4-400
I
Order Number: 292098-003
Extended Flash Bios Concepts
for Portable Computers
CONTENTS
PAGE
CONTENTS
PAGE
1.0 INTRODUCTION ................... 4-402
5.0 SOFTWARE DESIGN
CONSIDERATIONS ................. 4-411
2.0 PC BIOS TODAY AT THE
128 KBYTE CODE SIZE LIMIT ...... 4-402
5.1 16 Kbyte Recovery Code ........ 4-413
5.2 28F200BX Reprogramming ... : .. 4-413
3.0 WHY BIOS CODE WILL GROW
BEYOND 128 KBYTES .............. 4-402
5.3 Power Management ............. 4-413
3.1 Advanced Power Management .. 4-404
6.0 DESIGNING A 3.3V SySTEM ...... 4-414
3.2 Optimizing New Portable
Applications ...................... 4-404
6.1 Low Voltage Chips ............... 4-414
6.2 Power Savings and Improved
Battery Life ....................... 4-414
3.3 Putting Microsoft* MS-DOS 5.0
Operating System ROM Version into
the BIOS Chip .................... 4-404
7.0 CONCLUSiONS ......... : .......... 4-414
3.4 Relocated Resident VGA Code:
VIDEO BIOS ...................... 4-404
7.1 Benefits of Extended Flash
BIOS ............................. 4-414
4.0 HARDWARE DESIGN FOR A
256·KBYTE BIOS ................... 4-405
REFERENCES ......................... 4-414
4.1 Intel 28F200BX/002BX Boot Block
Flash Memory Family ............. 4-405
4.2 Extended Flash BIOS Design
Example .......................... 4-406
APPENDIX A .......................... 4-415
APPENDIX B .......................... 4-416
APPENDIX C .......................... 4-421
4.3 The ISA Sliding Window ......... 4-411
4.4 The 28F200BX-T/28F002BX-T in
the 1 Mbyte DOS Memory Map .... 4-411
·Microsoft is a registered trademark of Microsoft Corporation.
I
4-401
Ap·363
1.0
INTRODUCTION
PC BIOS has been migrating to flash-based designs
with the introduction of highly optimized flash memory
architectures. The first phase of this shift in paradigm
was from ROM/EPROM-based BIOS to Bulk Erase
Flash memory-based BIOS to provide for in-system updatable BIOS and hence an easy update capability
when BIOS changes are required.
The second phase improved the basic flash design to
migrate towards boot block flash memory architecture
with the Intel 28FOOIBX Flash Memory. This im'provement enabled the implementation of additional
features and provided a true design capability for portable PC BIOS.
The third phase of this paradigm shift now starting to
evolve, deals with the need to grow beyond the traditional BIOS space limit of 128 Kbytes imposed by the
original PC architecture to accommodate the advanced
features of today's portable and desktop systems.
This application note describes in detail this third phase
in BIOS hardware and software implementation. Specifically it will investigate why BIOS needs to grow beyond the 128 Kbyte code size. Then, a design example
using the Intel 28F200BX Boot Block Flash Memory
will be explained in terms of both hardware and software. Finally, low voltage PC BIOS designs incorporating 3.3V components are described.
2.0
PC BIOS TODAY AT THE
128 KBYTE CODE SIZE LIMIT
The Basic Input/Output System (BIOS) code is the
lowest system level software which manages the interaction between all hardware components (CPU, ChipSets and 1/0) with all software modules (Operating
Systems and Applications Code). BIOS manages many
functions in a PC, such as Power-On Self Test (POST),
input vector creation, 1/0 services and system initialization. Therefore BIOS is the essential interface layer
for full system functionality and compatibility.
The original PC architecture, developed in 1981, put
restrictions on the size and mapping of the BIOS code
which was then a very simple piece of software (on the
order of 32 Kbytes for the original BIOS code). It was
located at the top of the PC's (8088) memory map
which at the time was a maximum of 1 Mbyte.
4-402
Then in 1984, the PC AT (80286) BIOS was expanded
another 32 Kbytes for a total of 64 Kbytes. Subsequently, towards the late 1980s, more elaborate BIOS set-up
utilities started to be an integral part of the BIOS code.
In addition, personal computer manufacturers designed
custom features into their BIOS code to offer more system flexibility. This increase in code complexity expanded the AT BIOS' code another 64 Kbytes (for a
total of 128 Kbytes) To occupy the total BIOS reserved
space in the I Mbyte memory map.
In the DOS memory map, BIOS is mapped down from
the top of the I-Mbyte address space (FOOOOH to
FFFFFH). Additional BIOS code space is available for
future enhancements from EOOOOH to EFFFFH. The
next 256 Kbytes in the DOS memory map are reserved
for adapter space to accommodate add-in boards (for
enhanced graphics cards for instance). Finally the remaining 640 Kbytes are reserved for the user to load
hislher applications for execution. See Figure 1 for a
graphical description.
3.0
WHY BIOS CODE WILL GROW
BEYOND 128 KBYTES
As advances in computer design affect both desktop
systems (with the addition of EISA, pcl and on-board
SCSI capabilities) and portable systems (with the addition of advanced power management capability and II
o cards), the need for larger amounts of non-volatile
memory space becomes evident.
A Notebook or a Palmtop computer design, for instance, may put the operating system, the system management code, set-up or utility programs into the nonvolatile memory area to conserve precious RAM space
for applications.
Additionally, Video BIOS can also be mapped into the
Flash BIOS area.
Therefore, to implement advanced capabilities and provide new features (as described above) into powerful
mobile computers, the 128 Kbyte BIOS code size limit
had to be removed as it shall be explored in the next
section.
The BIOS of today and the future must adapt to the
new requirements of portable PC designs and take advantage of the new capabilities of low power PC chipsets and I/O devices to achieve the highest performance
and longest battery life at the lowest system cost.
I
AP-363
(1024K)
1 MBYlE DOS MAP
FFFFFH . - - - - - - - - - - - - , . ....
BIOS CODE
(960K)
EFFFFH
.... ....
1----------1
.... ....
.... ....
ADDITIONAL BIOS SPACE
(896K)
EOOOOH
DFFFFH
1----------1. "
ADAPTER SPACE
AND GRAPHIC SPACE
(640K)
AOOOOH
1----------1
,,
,,
,,
.... ....
....
INTEL 28FOO 1BX-T
BOOT BLOCK FLASH
MEMORY MAP
·8K
BOOT RECOVERY CODE
.... ....
,,
"
,,
4K
PARAMETER BLOCK
4K
PARAMETER BLOCK
112K
,
MAIN BIOS CODE
USER AREA
OOOOOH~
________
~
292098-1
Figure 1. 128 Kbyte BIOS Code Segmentation in 1-Mbyte DOS Memory Map
I
4-403
AP-363
3.1 Advanced Power Management
High integration CPUs and chip-sets allow for the design of light, small form factor portable computers with
long battery life.
BIOS is the ideal place for implementing the power
management"teChniques pioneered with the Intel386SL
Microprocessor Superset. BIOS software vendors have
implemented APM code for the latest generation of
Notebook PCs.
This added level of functionality imposed on the BIOS
code increases the need for larger code space beyond
the traditional 128 Kbyte BIOS implementations seen
in today's portable systems.
APM code typically requires an additional 32 Kbyte of
code space beyond the basic 64 Kbyte standard BIOS.
Therefore, with the addition of APM, BIOS code grows
to 96 Kbytes.
3.2 Optimizing New Portable
Applications
With the implementation of PCMCIA cards for nonvolatile file storage (with flash memory cards) and the
ability to communicate over a telephone line (with modem cards), mobile computers have truly become powerful tools on the road.
and character recognition interface code. These new
features require the implementation of additional BIOS
code (may be 16 Kbytes to 32 Kbytes).
To take full advantage of Desktop system capabilities
and performance while still having a portable computer
to take on the road, docking station designs were conceived. This added level of complexity for the portable
computer increases the code required in a basic system
BIOS.
3.3 Putting Microsoft MS-DOS 5.0
Operating System ROM Version
into the BIOS Chip
Additionally, MS-DOS 5, ROM version is now becoming a standard in virtually all diskless sub-notebook,
notebook and pen PC implementations. Many factors
contribute to this approach. Chief among them is the
reduced disk access and the resulting longer battery
life. Another factor is the instant boot capability which
is essential in certain applications.
Today's MS-DOS 5, ROM version occupies 64 Kbytes
of code space as specified from the Microsoft Product
Description.
3.4 Relocated Resident VGA Code:
VIDEO BIOS
The establishment of a common PC card standard for
full system compatibility is described in the PCMCIA
Standard release 2.0 (personal Computer Memory
Card International Association). Intel has developed a
similar set of specifications fully compatible with the
PCMCIA release 2.0 standard called the Exchangeable
Card Architecture (ExCA). In order to implement card
capability in a portable computer, additional BIOS
code called Socket Services is minimally required to
manage the system card functionality. To implement
the specifications, socket services needs an additional
16 Kbyte of code space.
As described above in section 3.0, video BIOS can also
be mapped into the system Flash BIOS memory allow-;
ing the entire system non-volatile storage requirements
to be satisfied with one Flash device. Resident VGA
BIOS code takes approximately another 32 Kbytes of
memory space.
Furthermore, in the pen-based PC applications, there
are even greater BIOS requirements to design-in unique
features such as: pen extensions, touchscreen capability
There are already portable designs today which have
filled a 256 Kbyte code space to accommodate some of
the above mentioned needs.
4-404
In summary, adding all the above code size requirements, the resulting BIOS storage area increases from
the initial 128 Kbyte requirement to somewhere between 208 Kbytes (without pen extensions) to 240
Kbytes (including a pen input capability).
I
AP-363
4.0
HARDWARE DESIGN FOR A
256 KBYTE BIOS
4.1
Intel 28F200BX/002BX Boot Block
.
Flash Memory Family
Building upon the wide acceptance of the
Intel28FOOIBX 1 Mbit flash memory for BIOS designs,
a new family of higher density flash components is now
available to solve the PC designer's need of implementing extended BIOS code beyond 128 Kbytes.
These new flash memories at the 2 Megabit density levels are structured around the same boot block architectu;e as the Intel 28FOOIBX and are therefore compatible. They provide block erasure capability, boot code
hardware protection and very low power consumption
as in the case of the 28FOOIBX.
In addition, they incorporate new features to simplify
the device interface and allow the system designer to
. optimize platform designs.
These new features are summarized as follows:
• User selectable 8-bit or 16-bit read/write operation
(28F200BX)
• 60ns access time performance
• 16 Kbytes Boot Block space which is hardware protected
• Two, 8 KBytes Parameter Blocks
• One, 96 KByte Main Block
One, 128 KByte Main Block
• v-bit only operation and packaging for space sensitive applications (28FOO2BX)
In this section, we will describe these new features in
more detail and discuss their system applicability.
The blocking scheme, while still of the boot block type,
is expanded by defining additional blocks (2 main
blocks) to allow for software modularization and a selfcontained design.
As the size of the BIOS code stored in anyone device
grows due to the complexity and high integration of
chip-sets, so does the "kernel" code stored in the boot
section. The boot and parameter blocks were accordingly doubled in size in comparison to the 28FOOIBX
device. The two parameter blocks of 8 KBytes each
allow the PC designer to store BIOS extensions or Battery-Backed SRAM configuration data (CMOS RAM,
EISA configuration parameters). The two main blocks
are used to store the main BIOS code in modular fashion if so desired for future easy updates. These main
blocks can also be used to store ROM-executable Operating System software such as MS-DOS 5, ROM version or drivers and .utilities. Refer to' Figure 2 for the
block locations for both the 28F200BX-T and
28FOO2BX-T.
(Word Addresses)
(Word Addresses)
lFFFFH
3FFFFH
16-Kbyte BOOT BLOCK
1EOOOH
1DFFFH
1DOOOH
lCFFFH
lCOOOH
lBFFFH
16-Kbyte BOOT BLOCK
3COOOH
3BFFFH
B-Kbyte PARAMETER BLOCK
3AOOOH
39FFFH
B-KByte PARAMETER BLOCK
B-Kbyte PARAMETER BLOCK·
B-Kbyte PARAMETER BLOCK
3BOOOH
37FFFH
96-Kbyte MAIN BLOCK
10000H
OFFFFH
96-Kbyte MAIN BLOCK
20000H
lFFFFH
12B-Kbyte MAIN BLOCK
12B-Kbyte MAIN BLOCK
OOOOOH
OOOOOH
Valid Addresses in X16 Mode (BYTE# = 1): AO-A16
Valid Addresses' in X8 Mode (BYTE# = 0):
A-1 (lowest order address) and AO-A 16
28F200BX-T Top Boot Map
28F002BX-T Top Boot Map
Figure 2. 28F200BX-T/002BX-T Memory Maps
I
4-405
AP-363
In addition, the 28F200BX/OO2BX devices incorporate
new capabilities desired by today's sophisticated PC designers.
The byte-wide or word-wide feature available as a designer-selectable option gives the ability to interface to
an 8-bit or 16-bit wide bus. The performance and hardware goals of some systems may require 16-bit BIOS
data bus. A system with a small amount of RAM and a
large amount of flash memory-based operating system
code for example, may require a 16-bit BIOS data bus
to maintain a high performance level of operation.
The high access speed of these new devices, which for
the first time break the 60 ns barrier at the 2M and 4M
densities, is another big advantage the PC designer can
fully exploit to increase system performance and acceptance in the marketplace. For example, a PC designer may choose to execute BIOS directly out of flash
memory instead of shadowing to system RAM as well
as execute MS-DOS 5, ROM version out of flash for
instant-on capability and to achieve better overall system performance.
Block erasure allows independent modification of code
and data and maximum flexibilty in production as well
as after the system is shipped. The boot block, which is
hardware protected, insures that minimal BIOS code is
present to always boot up the system successfully. The
16 Kbyte boot block is protected from alteration during
system power excursions by a high voltage pin. This
write protection pin called RP# has to transition to
12V with the normal Vpp voltage pin to allow for boot
block write and erase operations.
If systems' are designed with the ability to jumper or
switch RP# to high voltage (12V), guaranteed full nonvolatility of the boot code is achieved. This feature always guarantees system recovery from power failure
and provides the security needed for the end user when
performing BIOS code updates.
To meet the crucial needs of lower power consumption,
the 28F200Bx/OO2BX devices incorporate a deep-power down current mode activated through the RP# pin
under the TTL/CMOS level control. When this pin
transitions to ground the device typically consumes
1 microwatt through the Vee supply pin.
In addition, the 28F200BX/OO2BX devices include an
Automatic Power Savings feature during active mode
of operation. This feature allows the memory chip to
put itself in a very low current state when it is enabled
but not accessing a new memory location.
The 28F200BX/OO2BX devices incorporate an internal
Write State Machine, Command User Interface and a
Status Register to fully control the program and erase
operations and greatly simplify the user write and erase
algorithms and hence the update code procedure. They
also include an erase suspend feature which allow the
system to service interrupts and access the device during BIOS code updates (refer to Appendix B).
Finally, the 28F200Bx/OO2BX, 2-Megabit devices
have an equivalent 4-Megabit boot block flash memory
family of devices called the 28F400Bx/OO4BX, allowing for easy density upgrade and total compatibility between systems using both types of memories. Refer to
the documentation mentioned in the reference section
of this application note.
Figure 3 is a block diagram description of the
28F200BX/OO2BX products.
4.2 Extended Flash BIOS Design
Example
This design example focuses primarily on how to interface the Intel 28F200BX-Tor 28FOO2BX-T Boot Block
flash memories to the Intel386SL MiCroprocessor Superset in a 16-bit wide or an 8-bit wide configuration
respectively. This is an extended BIOS design example
which demonstrates how' the barrier of the 128-Kbyte
BIOS size memory is eliminated. The design principles
in this example apply to designs incorporating chip sets
interfaced to SL Enhanced CPUs. Figure 4 shows an
interface diagram of the Intel 28F200BX-T Boot Block
Flash memory (128 K x 16) to the Intel386SL Microprocessor superset. Figure 5 shows an eqUivalent interface diagram of the Intel 28FOO2BX-T Boot Block flash
memory (256 K x 8) to the Intel386SL Microprocessor
Superset.
The Inte1386SL Microprocessor Superset Flash BIOS
interface supports up to 256 Kbytes of flash memory
BIOS (a 2 Megabit flash memory device) to enable the
system designer to meet specific design goals as described in section 3 above.
The Inte1386SL Microprocessor Superset supports the
following features:
•
•
•
•
Up to 256 Kbytes flash memory BIOS
VGA BIOS mapping into system BIOS
8-bit or 16-bit BIOS interface
Programmable number of flash memory wait states
for read access (from zero to fifteen Wait-States to
optimize the system performance)
• BIOS shadowing mechanism
4-406
I
_.
c£
@
. . . - - - - - - DQB-DQ1S/ A_I (28F200BX-ONLY)
"TI
cEo
I:
Cil
!'l
m
BYTE#
(2BF200BX-ONLY)
0"
n
~
C
.
iii"
CQ
~I+-I:-+-1~~-
DI
3
9.
CE#
~~:#
~
:::T
III
N
(XI
"TI
N
o
o
m
><
.....
N
(XI
"TI
o
o
N
m
><
Y-GATING/SENSING
AO - A16
A17 (28F002BX-ONLY)
Vpp
'"u
u
'"
g
...EnE; ~~
'",w...
w",
>-0::.
'~." W
",::>
I
UJ
;'2 co~
~
~
w'"
~g
... u
'"
I Z
<.0 _
"''''
c!:.~
ID~
cn~
?I;
3
N<
~'"
292098-2
.!>-
.f,..
o
-.J
»
'lJ
I
Co)
en
Co)
AP-363
Flash BIOS size configurations in the Inte1386SL Microprocessor Superset system are controlled by programming certain registers located in the normal I/O
address space.
When a 256 Kbyte Flash BIOS configuration is programmed into the Intel386SL Microprocessor Superset,
128 Kbytes are directly accessible in the EOOOOHFFFFFH address range. The other 128 Kbytes are decoded at the top of the 16th or 32nd Megabyte of the
Inte1386SL superset address space, i.e., either:
FCOOOOH-FDFFFFH or 1FCOOOOH-1FnFFFFH.
This extra ROM space is accessed by programming the
ISA sliding control register to point to one of these two
areas and then accessing the ISA sliding window in the
DOOOOH-DFFFFH address range (64 Kbytes). This
mechanism allows complete access of the 256 Kbytes of
BIOS code without having to enter the Inte1386SL protected mode.
The BIOS code size is used to internally decode the
ROM address space and generate two chip select signals: ROMCSO# and ROMCS1 #, to control the Flash
4-408
intel®
BIOS device. In the case of a single Flash BIOS device,
only ROMCSO# is needed to drive the CE# chip select signal of the flash memory.
In the diagram of Figure 4 note the following:
• BYTE# signal is set high to enable 16-bit operation
of the flash device.
• The highest order system address line SA16 is inverted when FLIP# signal becomes active at bootup time to relocate the boot kernel code at the top of
the 1 Mbyte memory map for the system to boot
from it. (See section 4.5).
• ROM16/8# is set high to enable 16-bit bus operations.
• RP# signal is gated by the PWRGOOD signal (for
reset when power fails) and by system RESET signal.
• Vpp supply voltage is switched to the flash device
only when BIOS updates are required.
In addition to the above considerations, note the following in Figure 5:
• The highest order system address line SA 17 is also
inverted when FLIP# signal becomes active at system boot-up time.
• ROM16/8# is set low to enable 8-bit only bus operations.
I
AP-363
+12V
INTEL
82360SLThI
ISA
PERIPHERAL
SMOUTl
XD7
-+:P\:.:
Vpp
I/o
INTEL
80386SLThI
CPU
+5V
ROMCSO#
CE#
MEMR#
0[#
MEMW#
W[#
+5V
BYTE#
+5V
ROM16/S#
292098-3
LEGEND:
XDEN# = X-BUS DATA ENABLE
XDIR = X-BUS DATA DIRECTION
SMOUT1,2 = SYSTEM MANAGEMENT OUTPUT CONTROLS
ROMCSO# = ROM CHIP SELECT FOR SYSTEM FLASH BIOS
MEMR# = MEMORY READ
MEMW# = MEMORY WRITE
FLlP# = BOOT BLOCK MEMORY MAPPING SIGNAL
ROM 16/8# = ROM 16 BITS OR 8 BITS
SD[6:0]' SD[15:8) = SYSTEM DATA BUS
SAO-16 = SYSTEM ADDRESS BUS
XD7 = X-BUS DATA BIT 7
PWRGOOD = POWER SUPPLY POWER GOOD SIGNAL
Figure 4. Key Attributes of this Optimized BIOS Interface
should be Incorporated in BIOS Designs> 128 Kbytes,
I
4-409
AP-363
+12V
INTEL
82360SLTM
ISA
PERIPHERAL
~
-.
SMOUT 1 ...; \ :
XD7
I
..
XDEN#
I/o
I
Vpp
Switch
Vpp
INTEL
80386SLTM
CPU
+5V
ROMCSO#
CE#
MEMR#
OE#
MEMW#
WE#
ROM16/S#
GND
292098-4
LEGEND:
XDEN# = X·BUS DATA ENABLE
XDIR = X·BUS DATA DIRECTION
SMOUT1,2 = SYSTEM MANAGEMENT OUTPUT CONTROLS
ROMCSO# = ROM CHIP SELECT FOR SYSTEM FLASH BIOS
MEMR# = MEMORY READ
MEMW#. = MEMOFWWRITE
FLlP# = .BOOT BLOCK MEMORY MAPPING SIGNAL
ROM 16/8# = ROM 16 BITS OR 8 BITS
SD[6:0] = SYSTEM DATA BUS
SAO-17 = SYSTEM ADDRESS BUS
XD7 = X·BUS DATA BIT 7
PWRGOOD = POWER SUPPLY POWER GOOD SIGNAL .
Figure 5. Key Attributes of this Optimized BIOS Interface
should be Incorporated In BIOS Designs> 128 Kbytes.
4·410
I
AP-363
4.3 ISA Sliding Window
An ISA sliding window mechanism is similar to the
Expanded Memory System or EMS mechanism. It allows the access of extended memory on the ISA bus in
real mode. Hence, there is no conflict in memory al1ocation when the BIOS chip is accessed during system
power-up. This is a straightforward method of implementing a 256 Kbyte extended Flash BIOS. Figure 6
shows how extended memory is accessed with the ISA
sliding window. This capability is designed into Intel's
386SL CPU and should be defined into chip sets supporting SL enhanced CPUs.
Therefore to use a 256 Kbyte Flash device the fol1owing steps are specified as an example:
Example:
Enable support of256 Kbyte Flash BIOS
Enable Flash BIOS write access
One BIOS Flash Bank used
Program zero Flash wait states (for 16 MHz
Intel386SL with a 60 ns Intel 28F200BX-T or
28FOO2BX-T).
Program the ISA Sliding Window to access memory
between FCOOOOH and FDFFFFH.
if ROM Chip-select decode register is not enabled
enable ROM chip-select decode register
4.4 The 28F200BX-T128F002BX-T in
the 1 Mbyte DOS Memory Map
In addition, due to the above mapping considerations
when interfacing a 256 Kbyte flash BIOS chip to any
chip set or the Inte1386SL Microprocessor Superset, it
is necessary to flip the 256 Kbyte flash memory device
in half at boot time to relocate the Boot Block in the
correct physical address at FFFFFH for the
Inte1386SL CPU to boot from it. This is due to the fact
that the Inte1386SL Microprocessor Superset uses the
bottom 128 Kbytes of the 256 Kbyte Flash chip to map
down to the real mode 128 Kbyte allocated BIOS
space.
Figure 7 shows how the Intel 28F200BX-T flash memory device fits in the DOS 1 MByte memory map. The
same memory map applies to the 28F002BX-T device
when designing an 8-bit only system.
5.0
SOFTWARE DESIGN
CONSIDERATIONS
The subject of BIOS code update is already discussed
extensively in references [1] and [3]. Appendix A of
this application note is an example of a flash BIOS update routine. In this section, we mainly discuss considerations of code segmentation and describe how the system handles the different pieces of code under various
conditions.
enable ISAWINDOW control register
"77. H
16 MBYTE
(1000000H)
OFDFFFFH
~
OFCOOOOH
8
KB
ISA SLIDING
WINDOW
DOS MAP
.--------,
OOOOOOOH
ISA- BUS
ADDRESS SPACE
292098-8
Figure 6. ISA Sliding Window and Extended Memory Maps
I
4-411
AP-363
FFFFFH
(1024K)
1 MBYlE DOS MAP
BIOS CODE
.... ....
.... ....
EFFFFH
(960K)
EOOOOH
DFFFfH
DOOOOH
COOOOH
(896K)
ADDITIONAL BIOS SPACE
MS ROM-DIS
~'~~~~
~-~_~_:~I~!~:_!,!~~~-~
ADAPTER SPACE
AND GRAPHIC SPACE
BOOOOH
,...
,,"""
.... ....
(640K)
USER AREA
........
....
....
"
INTEL 2BF200BX-T
BOOT BLOCK FLASH
MEMORY MAP
16K
BOOT RECOVERY CODE
BK
PARAMETER BLOCK
BK
PARAMETER BLOCK
.
' ' ,"""
,, ... "'
,, ,
"',', , '
,, ,,
, .at
,
,
AOOOOH
.... ....
",
96K
MAIN BIOS CODE
WITH
ADVANCED POWER
MANAGEMENT CODE
.at
12BK
MAIN BIOS CODE
OR
ROM O/S. UTILITIES. DRIVERS
OOOOOH
29209B-12
Figure 7. 28F200BX-T/28F002BX-T in the 1 Mbyte DOS Memory Map
4-412
I
AP·363
As explained in section 3, advanced notebook designs
require a large ROM space to conserve valuable RAM
space for applications. In addition to the boot kernel
code and standard BIOS code, one may put the following code modules:
•
•
•
•
APM code
VGA BIOS
ExCA socket services
Operating Systems such as Microsoft MS-DOS 5.0
ROM version
When designing a 256 Kbyte BIOS system as described
in this application note using Intel's 28F200BX/
002BX, proper code segmentation is essential to
achieve optimum system performance.
We can divide the system's operating environment into
either:
BOOT-TIME CONDITIONS (when system powersup or is rebooted)
or RUN-TIME CONDITIONS (after boot-up is com·
plete)
5.1
16 Kbyte Recovery Code
The 16 Kbyte recovery code is critical when a BIOS
update does not successfully complete. The reasons for
this failure can be divided into two categories:
1. System power failure during BIOS update
2. System reset (soft boot) during BIOS update
The processor will execute recovery code out of the 16
Kbyte boot block when either power is restored or
when the system boots up after the reset function.
The 16 Kbyte size recovery code allows the software
designer, to incorporate as many BIOS system checks as
possible to implement basic system functionality.
For instance, these checks may include:
Cursor Positioning
Keyboard services
Time of day service
Basic System services
5.2 28F200BX Reprogramming
The code modules described above are used at different
times during normal system operation. Hence, a segregation of the code stored in the flash memory is necessary for proper system operation.
Three basic algorithms allow the system designer to
reprogram the Flash BIOS chip and perform the neces·
sary tasks for a BIOS update. These algorithms are:
BOOT·TIME EXECUTION
Automated Byte/Word·wide programming
Automated Block erase
Erase Suspend and Resume
The system requires the boot kernel to be present at the
FFFFFH segment during this portion of the cycle.
When using the 28F200BX/OO2BX flash memory, the
first page present will be the top 128 Kbyte. The rest of
the first page is used to store APM code, VGA BIOS
code or ExCA socket services. These code modules are
then copied from their location below the boot block to
system RAM for later initialization after the standard
BIOS has started.
Once all code modules are copied into RAM, this first
128 Kbyte page of flash can be swapped out or exchanged with the 2nd 128 Kbyte page which is required
for run· time execution.
RUN·TIME EXECUTION
Standard BIOS code is required to be present from
EOOOOH to FFFFFH segment during this time period
to handle any BIOS calls and maintain proper system
operation.
Microsoft MS· DOS 5.0 ROM version code is also required to be present so the BIOS can "SCAN" it in as
an adapter.
I
For a description of these algorithms, the reader is encouraged to study reference [5]. Appendix B in this
application note includes the four flowcharts associated
with the algorithms.
To obtain the software drivers necessary to control the
device reprogramming operations, consult your local
Intel sales office.
5.3 Power Management
Power management is an essential part of any true portable PC design. The design of sophisticated power
management techniques is becoming a key differentiator between different machines, and hence is a competitive advantage for the system integrator.
To help the system designer with this often difficult
task of optimizing system performance and battery life,
the 28F200BX family of products includes three distinct low power modes of operation. These are:
• Standby Current Mode, where the device typically
consumes 50 /LA
4·413
AP·363
• Automatic Power Savings Feature, where the device
typically consumes 1 mA
• Deep powerdown Mode, where the device typically
consumes 0.2 p.A
7.0
CONCLUSIONS
7.1
Benefits of Extended Flash BIOS
For a detailed description of these modes of operation;
consult reference [8].
This application note deals with the concepts of extended BIOS implementations in portable PC designs, but it
can also be easily adapted to desktop PC systems for
which BIOS code requirements can easily exceed
128 Kbytes.
6.0
DESIGNING A 3.3V SYSTEM
The ability to design 3.3V systems used to be a future
consideration. Longer battery life and lighter weight
portable computers are some of the key objectives for
any portable design. Now, thanks to the increasing
availability of low voltage components, true low power
machines are possible to realize in practice.
6.1 Low Voltage Chips
The list of 3.3V components available to build the essential parts of a portable computer is becoming longer
every day. Semiconductor manufacturers have recognized the urgent need to supply low voltage chips to the
portable marketplace.
The Intel 28F200BX/OO2BX Boot Block Flash Memories are available in 3.3V versions. These low voltage
versions of the 28F200BX/002BX are functionally
equivalent to their 5V counterparts and are 100% pinout compatible. So a system converting to 3.3V operation can substitute low voltage 2 Mbit chips
(28F200BX-L/OO2BX-L) when desired without any
circuit board modification.
6.2 Power Savings and Improved
Battery. Life
The 28F200BX/OO2BX 3.3V chips reduce the total
power drawn during normal read operation to less than
25% of the total power in 5V mode. This is a substantial savings in current which translates to 25% less battery drain and hence longer battery life.
Similarly, low voltage version of the most popular microprocessors reduce the total power dissipated by a
substantial amount.
The combination of these current savings plus the other
system components current reductions improve battery
life dramatically and allow the mobile PC user to benefit from weight reduction, longer operating time, lower
system cost and higher performance.
We have attempted to explain the requirements and the
needs of today's advanced portable BIOS designs which
have to meet many difficult and often conflicting requirements.
Boot Block flash memory is the ideal storage solution
to implement the above mentioned features. Furthermore, as the cost of solid state non-volatile flash memory keeps decreasing, the need to switch to these types of
media for storing extended BIOS, operating system
software, utilities, and in the future application code,
becomes more evident and perhaps the only way a PC
manufacturer can effectively compete by producing the
best engineered, most optimally· designed notebooks,
palmtop PCs and pen-based computers.
REFERENCES
For more information on the concepts presented in this
application note, the reader is encouraged to reference
the following documents.
[1] Technical Paper: "Flash: The Optimum BIOS Storage Device" by Brian Dipert, 1991 SVPC - Order
Number 297003
[2] "ROM BIOS: The best place for portable PC Power-Management features" by Lance Hansche, 1991
SVPC
[3] AP-341: "Designing an Updatable BIOS Using
Flash Memory"-Order Number 292077
[4] AP-357: "Power Supply Solutions for Flash Memory,"-Order Number 292092
[5] Intel 28F200BX/OO2BX Datasheet-Order Number 290448
[6] Intel 2SF400BX/004BX Datasheet-Order Number 290451
[7] Intel 2SF200BX-L/002BX-L Datasheet-290449
[S] Intel 2SF400BX-L/OO4BX-L Datasheet-290450
4-414
I
AP-363
APPENDIX A
Example of a Flash Update Utility
Pseudo-Code
This example is for a standard BIOS code and APM
code update using the 28F200BX/002BX flash device.
Modify this utility, if required, to suit your particular
system needs.
Initialize system (set-up user screen, check battery power, check device ID)
Get BIOS/APM file Options (from floppy or through
modem)
If no file present
Send error message to insert BIOS update floppy, or
press ESC to exit
Display BlOS/APM update files, prompt user for
choice and load to memory
Inform user of upcoming event, provide option to continue or exit
If user continues, inform user not to turn off the
power or soft-reboot system (CNTL-ALT-DEL)
Erase 28F200BX/002BX device 96-Kbyte main block
If system interrupt occurs
Suspend erase operation if flash memory access is
required
Resume erase operation of 96-Kbyte main block
Write new file(s) into flash memory 96-Kbyte main
block
Indicate to user that flash reprogramming is complete
Prompt user to reboot the system to continue normal
operation
If file is invalid
Prompt for correct file or exit
I
4-415
Ap·363
APPENDIX B
28F200BX-T 128F002BX-T Programming Flowcharts
4-416-
I
AP-363
Bus
Operation
Command
Comments
Write
Setup
Program
Data ~ 40H
Address ~ Byte to be
programmed
Write
Program
Data to be programmed
Address ~ Byte to be
programmed
Read
Status Register Data.
Toggle OE# or CE# to update
Status Register
Standby
CheckSR.7
1 ~ Ready, 0
~
Busy
Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
292098-13
Full Status Check Procedure
Bus
Operation
Command
Comments
Ypp Rang.
Error
Standby
Check SR.3
1 ~ Vpp Low Detect
Byt. Program
Standby
Check SRA
1 ~ Byte Program Error
Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
292098-14
SRA is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Automated Byte Programming Flowchart
I
4-417
AP-363
Bus
Operation
Comments
Command
Write
Setup
Program
Data = 40H
Address = Word to be
programmed
Write
Program
Data to be programmed
Address· = Word to be
programmed
Read
Status Register Data.
Toggle OE# or CEll' to update
Status Register
Standby
Check SR.7
1 = Ready, 0 = Busy
Repeat for subsequent words.
Full status check can be done after each word or after a
sequence of words.
292098-15
Write FFH after the last word programming operation to
reset the device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Vpp Range
Error
Word Program
Error
Command
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Standby
CheckSR.4
1 = Word Program Error
SR~3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
292098-16
SR.4 Is only cleared by the Clear Status Register
Command, in cases where multiple words are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Automated Word Programming Flowchart
4-418
I
AP·363
Bus
Operation
Command
Comments
Write
Setup
Erase
Data = 20H
Address = Within block to be
erased
Write
Erase
Data = DOH
Address = Within block to be
erased
Read
Status Register Data.
Toggle OE# or CE# to update
Status Register
Standby
CheckSR.7
1 = Ready, 0 = Busy
Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.
292098-17
Write FFH after the last block erase operation to reset the
device to Read Array Mode.
Full Status Check Procedure
Bus
Operation
Vpp Range
Error
Command
Comments
Standby
CheckSR.3
1 = Vpp Low Detect
Error
Standby
Check SRA,5
Both 1 = Command Sequence
Error
Block Erase
Standby
Check SR.5
1 = Block Erase Error
Command Sequence
Error
SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
292098-18
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Automated Block Erase Flowchart
I
4-419
intel®
AP-363
Bus
Operation
Write
Command
Erase
Suspend
Comments
Data
= BOH
Read
Status Register Data.
Toggle OE# or CEll' to
update Status Register
Standby
CheckSR.7
1 = Ready
Standby
CheckSR.6
1 = Suspended
Write
Read Array
= FFH
Read array data from block
other than that being
erased.
Read
Write
Data
Erase Resume
Data = DOH
292098-19
Erase Suspend/Resume Flowchart
4-420
I
AP-363
APPENDIX C
List of BIOS software vendors already supporting or announcing their future support for the 28F200BX/002BX
flash BIOS chips:
SystemSoft Corporation
Contact: Cliff Sharin
508-651-0088
313Speen Street
Natick, MA 01760
American Megatrends, Incorporated
Contact: Tom Rau
404-246-8612
1346 OakBrook Drive, Suite 120
Norcross, GA 30093
Phoenix Technologies Ltd.
Contact: Howard Cohen
408-452-6529
40 Airport Parkway
San Jose, CA 95110
Quadtel
Contact: Dale Buscaino
714-754-4422 (ext. 250)
3190-J Airport Loop
Costa Mesa, CA 92626
Award Software, Inc.
Contact: Jeffry Flink
408-370-7979 (ext. 214)
130 Knowles Drive
Los Gatos, CA 95030-1832
I
4-421
infel·
ER-26
ENGINEERING
REPORT
The Intel 28FOOIBX-T and
28FOOIBX-B Flash Memories
BRIAN DIPERT
OWEN JUNGROTH
MEMORY COMPONENTS DIVISION
October 1993
4-422
I
Order Number: 294010-003
The Intel 28F001BX-T and 28F001BX-B Flash Memories
CONTENTS
PAGE
INTRODUCTION . ...................... 4-424
CONTENTS
PAGE
Programming ........................... 4-428
Reset-Power Down ..................... 4-428
TECHNOLOGY OVERVIEW ........... 4-424
DEVICE ARCHITECTURE ............. 4-425
Write State Machine and
Command/Status Registers .......... 4-425
Internal Oscillator ...................... 4-426
DEVICE RELIABILITY ................. 4-429
Cell Margining .......................... 4-429
Erase/Program Cycling ................. 4-430
SUMMARY ............................ 4-430
Supply Voltage Sensing ................ 4-426
Erasure ................................ 4-427
I
4-423
ER-26
INTRODUCTION
Intel's 28FOOIBX ETOX (EPROM tunnel oxide) flash
memories add selective block erasure, an integrated
Write State Machine and powerdown capability to Intel's standard flash memory product line. Flash memory enhances EPROM non-volatility and ease of use
through electrical erasure and reprogramming. Advances in tunnel oxides and photolithography have
made it possible to develop a double-polysilicon singletransistor read/write random access nonvolatile memory, capable of greater than 100,000 reprogramming cycles. The 28FOOIBX flash memories electrically erase
all bits in a block matrix via electron tunneling. The
EPROM programming mechanism of hot electron injection is employed for electrical byte programming.
advanced 1.0 /Lm double-polysilicon n-well CMOS
technology, the 131,072 x 8 bit flash memories employ
a 3.8 /Lm x 4.0 /Lm single transistor cell, affording
equivalent array density as comparable EPROM technology. The flash memory cell structure is identical to
the EPROM structure, except for the thinner gate (tunnel) oxide. Figure 1 compares the flash memory Cell to
the EPROM cell.
EPROM Cell
SECOND, LEVEL
POL YSI LICON
~
I
Y
VS
A Command Register/Status Register interface to a
Write State Machine, internal margin voltage generation, power up/down protection and address/data
latches augment standard EPROM circuitry to optimize Intel's 28FOOIBX family formicroprocessor-controlled reprogramming.
Read timing parameters are equivalent to those of
CMOS EPROMs, EEPROMs and SRAMs. The 120 ns
access time results from a memory cell current of approximately 50 /LA, low resistance poly-silicide wordlines, advanced scaled periphery transistors and an optimized data-out buffer.
+VG
FIRST LEVEL
POLYSILICON
(FLOATING)
+VD
GATE OXIDE
N+
P-SUBSTRATE
294010-1
Flash Memory Cell
SECOND LEVEL
POLYSILICON
+VG
~
I
Y
FIRST LEVEL
POL YSILICON
(FLOATING)
The, dense one-transistor cell structure, coupled with ,
high array efficiency, yields a one megabit die measuring 235 by 268 mils.
294010-2
TECHNOLOGY OVERVIEW
Figure 1. EPROM Cell vs. Flash Memory Cell
Intel's ETOX flash memory technology is derived from
its standard CMOS EPROM process base. Using
4-424
I
ER-26
High quality tunnel oxide under the single floating
polysilicon gate promotes electrical erasure. All cells of
a given block are simultaneously erased via FowlerNordheim tunneling. Applying l2V on the block
source junctions and grounding the select gates erases a
given block. The internal Write State Machine (WSM)
controls the erase algorithm, including block pre-programming before erasure. WSM-controlled erasure, including internal pre-programming, takes 2.1 seconds
typical for each parameter block and the boot block,
and 3.8 sec. typical for the main block.
Programming is accomplished with the standard
EPROM mechanism of hot electron injection from the
cell drain junction to the floating gate. Programming is
initiated by bringing both the select gate and the cell
drain to high voltage. The internal WSM regulates the
internal program algorithm after the correct command
sequence is written to the 28FOOIBX. Typical program
time is 18 /-Ls per byte.
DEVICE ARCHITECTURE
Write State Machine and Commandl
Status Registers
Intel's 28FOOlBX flash memories contain an on-chip
Write State Machine that automatically controls erase
and program algorithms, dramatically simplifying user
interface. Figure 2 shows the 28FOOIBX block diagram.
r-~~--~-!-!-!-------CE"
1+--1-.....--------- WE"
1+-.....----------- OE"
L-~--r_r--------------RP#
Vpp
294010-3
Figure 2. 28F001BX Block Diagram
I
4-425
ER·26
The WSM simpifies microprocessor control of the
erase, program, Status Register read/clear, ID read and
array read operations, without the need for additional
control pins or the multiplexing of high voltage with
control functions. The WSM, with its integrated oscillator, performs a majority of the standard flash memory program and erase algorithms automatically. This
makes system timers no longer necessary and frees the
system to service interrupts or perform other functions
during device erase or program. On-chip address and
data latches minimize system interface logic and free
the system bus. The Write State Machine accepts array
read, ID read and Status Register read and clear commands whenever power is applied to the 28FOO1BX.
High voltage (12V) on Vpp additionally enables successful program and erase.
The WSM consists of a Command Register, Status
Register, State Machine, oscillator, command decoder,
data latch and address latch. The command decoder
output feeds the State Machine, enabling the high voltage flash-erase switch, program voltage generator and
erase/program verify voltage generator.
Functions are selected via the Command Register in a
microprocessor write cycle controlled by the Chip Enable (CE#) and Write Enable (WE#) pins. The rising
edge of WE# latches the address and data-in registers,
and initiates an operation. Status Register contents are
driven to the outputs on the falling edge of CE# or
Output Enable (OE#), whichever occurs last in the
read cycle.
Internal Oscillator
Fignre 3 shows how the oscillator period varies with
temperature and supply voltage. The circuit works for
supply voltages outside the normal operating conditions and for military temperatures.
700
.
650
c
600
~
-5
0
..,a:a.
.....:'"
550
0
...J
...J
500
(3
'"0
4.0
4.5
5.0
5.5
6.0
6.5
Vee (Volt.)
294010-4
Figure 3. Internal Oscillator Frequency
vs Supply Voltage and Temperature
Supply Voltage Sensing
The circuit that generates LOWVee and LOWVpp is
shown in Figure 4. Power supply voltages Vee and
Vpp are divided down and compared to a reference
voltage. If the reference voltage is greater than the divided power supply voltage, the LOWVee or
LOWVpp signal will be pulled high. The VREF level
generated by the voltage reference is independent of the
supply voltage to the first order.
The Write State Machine is designed using clocked logic circuits. An on chip ring oscillator generates the
clock signals. The frequency of a standard ring oscillator varies with processing, temperature and supply voltage. The improved design used on the 28FOOIBX minimizes these variations.
The switching current of each stage in the ring oscillator is set by a current reference. This reference current
varies linearly with Vee. The trip point of each ring
oscillator inverter also varies linearly with Vee. These
two effects essentially cancel each other out and the
resulting oscillator period is proportional to RC, with
only a small dependence on Vee.
The value of R is set by an on chip resistor. The value
of C is set by the gate capacitance of the inverters in the
ring oscillator. Process variations in the values are reduced by trimming the period of each oscillator during
manufacturing: The resistor is the only source of temperature variation.
4-426
LOW Vee
LOW Vpp
294010-5
Figure 4. Low Power Detector Circuit
I
ER-26
The positive power supply to the circuit is provided by
MI and M2. The source of MI and M2 will be pulled
up to the maximum of (VPP-VTN) and (VCC-VTW).
VTN is the threshold of an implanted N channel device,
about O.9V. VTW is the threshold of a native N channel
device, about OV. This scheme ensures that the circuit
will work regardless of the applied supply voltages.
The LOWV cc signal not only goes to the erase circuits,
but also to the programming circuits and to the control
logic to prevent any accidental writes to the array. The
LOWVpp signal goes to the Write State Machine. If
Vpp is detected as being low during a write, the low
Vpp bit will be set in the Status Register.
Erasure
Erasure is achieved through a two-step write sequence.
The erase setup code is written to the Command ~egis
ter in the first cycle. The erase confirm code is written
in the second cycle. The block to be erased is specified
by writing both commands to any address within the
block. The address is latched and decoded internally by
the 28FOOIBX, and erase of the desired block is subsequently enabled. The rising edge of this second WE#
pulse initiates the erase operation. The boot block will
not erase unless the RP# or OE# signal is brought to
high voltage VHH.
The State Machine triggers the high voltage flash-erase
switch, connecting the 12V supply to the source of all
bits in the specified block, while all wordlines are
grounded. The organization of the block source
switches is shown in Figure 5. Fowler-Nordheim tunneling results in. the simultaneous erasure of all bits in
the addressed block.
The block source switch controls the source voltage of
the bits in a particular block. This circuit is shown in
Figure 6. During erase, M2 is off and MI pulls the
source to Vpp. When not in erase, MI is off and M2
pulls the source to ground. The high voltage latch
formed by M4-M7 converts the low voltage ERASE
signal to a high voltage signal that turns MI off or on.
LOWVee)---------------------~
. - - - . . , ERASEMB
BLOCK 1-----1---1
SELECT
A, 2 -A'6 >-----f LATCHES
AND
DECODERS·
ERASEBB
MAIN BLOCK
SOURCE
PARAMETER I
SOURCE
PARAMETER 2
SOURCE
BOOT BLOCK
SOURCE
RP#
OE#
294010-6
Figure 5. Array Erase Blocking
toll
LOW Vee )---<1....---------+------1
ERASE)------------~~ ~o----~
294010-7
Figure 6. Block Source Switch
I
4-427
ER-26
The tunneling that occurs during erase requires only a
small amount of current. However, the grounded gate
initial erase currerit that occurs on the source of every
bit in the array is large. Ml is made large enough to
supply this current and still keep the voltage on the
source high enough for fast erase.time.
The LOWVcc signal protects the array from being
erased when Vpp is at a high voltage but Vee is a low
voltage. When this occurs, M3 will pull the block
source to ground. The high voltage latch will be forced
into the state that turns Ml off by M8.
After receiving the erase command sequence, the WSM
automaticany controls block precondition (programming of all bytes to OOH within the chosen block), erase
pulses and pulse repetition, timeout delays and byte-bybyte verification of all block addresses using the internally-generated erase margin voltage. The internal
erase and verify operations continue until the entire
block is erased. System software need only poll the
Status Register to determine when the WSM has suc-·
cessfully completed the erase algorithm.
Programming
Programming follows a similar flow. The program setup .command is written to the Command Register on
the first cycle. The second cycle loads the address and
data latches. The rising edge ofthe second WE# pulse
initiates programming by applying high voltage to the
gates and drains of the bits to be programmed.
As with erasure, the WSM controls program pulses and
pulse repetition, timeout delays and byte verification.
Program and program verify (at the internally-generated verify voltage) continue until the byte is programmed. System software, polling the Status Register,
is informed of programming state thru specific status
bits.
4-428
Reset-Power Down
The 28FOOIBX has a deep power down mode that reduces ICC and Ipp to typically 0.05 p.A and 0.8 p.A,
respectively. When RP# is low, the part is in deep
power down mode. When RP# is.high, the part can be
placed in an active or standby mode by state of the
CE# pin.
.
The deep power down mode is similar to the standby
mode except that more circuits are turned off. This
means that much less power is consumed; it also means
that it takes longer for the part to transition into the
active mode.
A diagram of the power down circuit is shown in Figure 7. The TTL buffer formed by MI-M3 enables the
low power detect circuits, the redundancy address flash
bits and the CE# TTL buffer formed by M4-M6. In
previous Intel flash chips these circuits were always enabled. The time for these circuits to turn on determines
the RP # access time and write specifications.
RP# will function properly with TTL level inputs.
However, to get the lowest possible power consumption, full CMOS levels should be used. If voltage on the
gate ofM3 raises above its threshold voltage ofO.9V, it
will turn on and draw current. fuput voltages in the
0.7-0.9 range could cause enough subthreshold conduction in M3 to exceed the deep power down current
specification. This is why the input voltage for RP# is
specified as GND ±0.2V.
The use of RP # during system reset is important with
automated write/erase devices. When the system comes
out of reset it expects to read from the flash memory.
Automated flash memories provide status information
when accessed during write/erase modes. If a CPU reset occurs with no flash memory reset, proper CPU
initialization would not occur because the flash memory would be providing the status information instead of
array data. Intel's Flash Memories allow proper CPU
initialization following a system reset through the use
of the RP# input. In this application RP# is controlled by the same RESET # signal that resets the system CPU.
ER-26
DEVICE RELIABILITY
Cell Margining
LOW POWER
DETECT
REDUNDANCY
TO THE REST
OF
THE CHIP
Erase and program verification ensure the data retention of the newly altered memory bits. The cell margining performed by the WSM during the verify phase of
the automated algorithms is more reliable than historical EEPROM schemes, as margining tests the amount
of charge stored on the floating gate.
Intel's 28FOOIBX flash memories employ a unique circuit to internally generate the erase and program verify
voltages. Figure 8 shows a simplified version of the circuit. The circuit consists of a high voltage switch and
the verify voltage generator. Transistors Ml through
M4 constitute the high voltage switch which disconnects Vpp from the resistor when the device is not in
the verify mode. The verify voltage generator includes a
resistor divider and a buffer. Internal margin voltage
generation maintains microprocessor .compatibility by
eliminating the need for external reference voltages.
294010-8
Figure 7. Power Down Circuits
p------------------------~---------------~
VERIFY
VOLTAGE
ENABLE
>-----..1
HIGH VOLTAGE SWITCH
VERIFY GENERATOR
------------------------~----------------
294010-9
Figure 8. Erase/Program Verify Generator
I
4-429
ER-26
Erase/Program Cycling
One of the most significant aspects of 28FOOlBX flash
memories is their capability for 100,000 erase/program
cycles per block. Destructive oxide breakdown has been
a limiting factor in extended cycling of thin oxide
EEPROMs. Intel's ETOX flash memory technology
extends cycling performance through:
• Improved tunnel oxide processing that increases
charge carrying capability tenfold;
• Reduced oxide area under stress minimizing probability of oxide defects in the region; and
• Reduced oxide stress due to a lower peak electric
field (lower erase voltage than EEPROM).
A typical cell erase/program margin (V0 is shown as a
function of reprogramming cycles in Figure 9. After
100,000 reprograming cycles, a 2.5V program read
margin exists, ensuring reliable data retention.
105
9_0
7.5
-
SUMMARY
Intel's ETOX flash memory technology is a breakthrough in adding electrical chip-erasure to high-density EPROM technology. Intel's 28FOOlBX family enhances Intel's standard flash memory line by adding
block erase capability, Write State Machine-controlled
program and erase and deep powerdown mode. Microprocessor-compatible specifications, straightforward interfacing and in-circuit selective alterability using simple software command sequences allow designers to
easily augment memory flexibility and satisfy the need
for nonvolatile storage in today's designs.
fI-f-
PROGRAM Vt MAX
ffI-fffI-f-
-
PROGRAM READ MARGIN
Vee MAX
--
Vee MIN
> 4.5 -
3.0 1.5 0.0
-
PROGRAM Vt MIN
---. 6.0 -
>
.........
Reliable erase/program cycling also requires proper selection of the erase Vt maximum and maintenance of a
tight Vt distribution. The maximum erased Vt is set to
3.2V via the internal erase algorithm and erase verify
circuits. Superior oxide quality gives an erased Vt distribution width that improves slightly with cycling
(Figure 10). The tight erase Vt distribution gives an
order of magnitude of erase time margin to the fastest
erasing cell.
ERASE READ MARGIN
ERASE Vt MAX
ERASE Vt MIN
I
I
I
I
I
I
I
10
100
1000
10000
100000
1M
NUMBER OF CYCLES
294010-11
Figure 9. Block Vt vs Cycles
4-430
I
ER-26
99.99
r....
~
'-'
Cl
99.9
99
w
f/)
4:
c::
w
f/)
..I
..I
90
50
w
10
w
1.0
i=
4:
0.1
:::>
~
0.01
u
0.001
u
>
ERASE Vt
@
1 CYCLES
..I
:::>
0.0
1.5
1.75
2.0
2.25
2.5
2.75
3.0
3.25
ERASE Vt (V)
294010-10
Figure 10. Erase Vt Distribution vs Cycling
7.5
6.5
6
5.5
5
'"
!3
0
4.5
~
,:- 3.5
w
'"
g
2.5
2
1.5
0.5
1000
2000
3000
4000
ERASE T1ME (mS)
5000
294010-25
Figure 11. Block Erase Vt vs Erase Time
I
4-431
ER-26
294010-15
Figure 12. 28F001BX Die Photograph
4-432
I
ER-26
Pin Names
~vcc
vppC 1
32
A1S C 2
31 ~WE#
A1S C 3
~'12C 4
A7C 5
AsC 6
AsC 7
A4C 8
A3C 9
A2 C 10
AtC 11
DOO-D07
Data Inputs/Outputs
30 PRP#
CE#
Chip Enable
29 PAt4
28 pA13
RP#
Power Down
OE#
Output Enable
WE#
Write Enable
Vpp
Program/Erase Power Supply
27 pAs
P28F001BX
26 pAg
32-PIN
POIP
25 pAll
0.62" x 1.64"
24 pOE#
TOP VIEW
23 PAto
22 pCE#
AoC 12
Address Inputs
Ao-AIS
21
Vee
Device Power Supply
GND
Ground
pO~
OQoC 13
20 POQs
OQl C 14
19POQs
OQ2 C 15
18POQ4
GNOC 16
17POQ3
294010-12
Atl
Ag
As
At3
At4
RP#
WE#
Vee
Vpp
A16
Ats
At2
A7
As
As
A4
1
2
3
4
5
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
0
E2BFOO 1BX
'6
7
8
9
10
11
12
13
14
15
16
32 LEAD TSOP
Bnim
X
20mm
TOP VIEW,
OE#
A10
CE#
O~
DOs
DQs
OQ4
OQ3
GNO
OQ2
DO,
000
Ao
At
A2
A3
294010-13
Figure 13. 28F001BX Pinout Configurations
A7
0
As
As
A4
A3
A2
A14
A13
As
N28F001BX
32 LEAD PLCC
0.450" x 0.550"
TOP VIEW
Al
Ag
Atl
OE#
Ato
CE#
Ao
000
D~
o~~ &' 0" c!f Cf
c c C> o c c c
294010-14
Figure 14. 28F001BX Pinout Configurations
I
4-433
ER-26
Columns are number 0 through 511 beginning with the column nearest the X-decoder. Outputs are grouped as
follows:
Left Half Array
100 101 102 103
BL511- BLs4
Array Organization
(Main Block):
Address
Right Half Array
.104 105 106 107
BLs4 -+ BL511
Bltllnes
A16
A15
A14
A13
A12
A1
Ao
100& 107
101 &106
102& 105
103& 104
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
B400
B401
B402
B403
B404
B40s
B406
B407
BL288
BL289
BL290
BL291
BL292
BL293
BL294
BL29S
BL176
BLl77
BL178
BL179
BL180
BL181
BL182
BL183
BLs4
BLss
BL66
BL67
BL68
BL69
BL70
BL71
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
BLs08
BLs09
BLs10
BLs11
BL396
BL397
BL398
BL399
BL284
BL28S
BL286
BL287
BL172
BL173
BL174
BL17S
•
•
•
•
•
•
•
•
•
•
•
Figure 15. Bitllne Decoding (Main Block, 28F001BX-T)
Array Organization
(Parameter Block 1):
Right Half Array
100-107
BLo-+ BL31
Address
Bitlines
A16
A15
A14
A13
A12
A1
Ao.
100
101
102
103
IQ4
105
106
107
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
BLe
BLl
BL2
BL3
B4
BLs
BL6
BL7
BLa
BL9
BL10
BLll
BL12
BL13
BL14
BL1S
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
BL24
BL2S
BL26
BL27
BL28
BL29
BL30
BL31
1
1
1
Figure 16. Bltline Decoding (Parameter Block 1, 28F001BX-T)
Right Half Array
100- 107
BL32 -+ BLs3
Array Organization
(Parameter Block 2):
Address
A16
1
1
1
1
Bitlines
A15
A14
A13
A12
A1
Ao
100
101
102
103
104
105
106
107
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
BL32
BL33
BL34
BL3S
BL36
BLa7
BL38
BL39
B40
B41
B42
BL43
BL44
B4s
B46
BL47
B48
B49
BLso
BLsl
BLs2.
BLs3
BLs4
BLss
BLs6
BLs7
BLS8
BLs9
BL60
BL61
BL62
BLs3
Figure 17. Bitline Decoding (Parameter Block 2, 28F001BX-T)
NOTES:
1. Bitline decoding listed is for 2BF001BX-T. To convert to 2BF001BX-B, invert polarity of addresses A1S-A12 (i.e. 0000000
becomes 1111100).
4-434
I
ER-26
left Half Array
107- 100
BlO -+ Bl63
Array Organization
(Boot Block):
Address
Bitlines
A16
A1S
A14
A13
A12
A1
Ao
107
106
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
BLo
BL1
BL2
BL3
BL4
BL5
BLs
BL7
BL8
BL9
BL10
BL11
BL12
BL13
BL14
BL15
105
BL16
BL17
BL18
BL19
BL20
BL21
BL22
BL23
104
BL24
BL25
BL26
BL27
BL28
BL29
BL30
BL31
103
BL32
BL33
BL34
BL35
BL36
BL37
BL38
BL39
10 2
BL40
BL41
BL42
B43
BL44
BL45
BL46
BL47
10 1
100
BL48
BL49
BL50
BL51
BL52
BL53
BL54
BL55
BL56
BL57
BL58
BL59
BL60
BL61
BL62
BLs3
Figure 18. Bitline Decoding (Boot Block, 28F001BX-T)
NOTE:
1. Bitline decoding listed is for 28F001 BX-T. To convert to 28F001 BX-B, invert polarity of addresses A16-A12 (i.e. 0000000
becomes 1111100).
X Address
Row
A11
A10
Ag
As
A7
As
As
A4
A3
A2
Wl
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0,
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
XLo
XL1
XL2
XL3
X4
XLs
XL6
XL7
XL8
XL9
XL10
XL11
XL12
XL13
XL14
XL15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
XL16
XL17
XL18
XL19
XL20
XL21
XL22
XL23
XL24
XL25
XL26
XL27
XL28
XL29
XL30
XL31
Figure 19. Wordline Decoding (28F001BX-T and 28F001BX-B)
I
4-435
ER-26
X Address
A11
A10
Ag
0
0
b
•
0
0
P
•
Row
A7
A6
As
A4
A3
A2
WL
o·
•
1
0
0
0
0
0
XLa2
0
0
1
0
1
1
1
1
X47
0
·0
•
•
0
1
1
1
1
1
1
X4a
0
0
0
0
1
1
0
0
0
0
X4>3
o·
0
0
1
0
0
0
0
0
0
XLS4
0
0
0
·1
0
0
1
1
1
1
XL79
0
0
0
1
0
1
1
1
1
1
XLao
0
0
0
1
0
1
0
0
0
0
XL95
1
1
1
1
1
0
0
0
0
XL992
0
0
•
0
0
1
1
1
0
1
1
1
1
XL1007
1
1
1
1
1
XL100a
0
0
•
1
0
1
0
0
0
•
•
•
•
•
•
•
•
0
1
•
•
1
. 1
As
•
•
•
•
•
•
•
•
1
1
0
0
0
•
1
1
1
1
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•••
•••
•••
**0
•••
0
**0
0
XL1023
Figure 19. Word line Decoding (28FOO 1BX-T and 28F001BX-B) (Continued)
,
,
Array Organization
~
w
-J
w
U)
0
0==
Main
Block
100
Main
Block
101
Main
Block
102
Main
Block
103
Boot
Block
100-7
Param Param
1 Block 2. Block
100-7
100-7
Main
Block
104
Main
Block
105
Main
Block
lOs
Main
Block
107
IX:
COLUMN SELECTS
Figure 20. Array Organization
REVISION HISTORY
Number
4-436
Description
002
Swapped Figures 9 and 10
Added Figure 11
003
PWD changed to RP#
for JEDEC standard compatibility.
I
intel·
ER-29
ENGINEERING
REPORT
The Intel 2/4-Mbit Boot Block
Flash Memory Family
ALAN BUCHECKER
PETER HAZEN
MEMORY COMPONENTS DIVISION
October 1993
4-437
The Intel 2/4 Mbit Boot Block Flash Memory Family'
CONTENTS
PAGE
INTRODUCTION . ...................... 4-439
Word/Byte-Wide Versions .............. 4-439
Byte-Wide Versions .................... 4-439
TECHNOLOGY OVERVIEW ........... 4-439
DEVICE ARCHITECTURE ............. 4-440
Array Organization ..................... 4-440
Block Memory Maps ................... 4-441
Write/Erase Automation ................ 4-441
Command User Interface (CUi) ......... 4-441
Write State Machine (WSM) ............ 4-444
Status Register ......................... 4-445
Internal Oscillator ...................... 4-446
Supply Voltage Sensing ................ 4-446
Deep Power-Down and Device Reset ... 4-446
Automatic Power Savings ..... , ........ 4-447
Block Erase ............................ 4-447
Erase Suspend/Resume ............... 4-449
Word/Byte Write ....................... 4-449
4-438
CONTENTS
PAGE
DEVICE CHARACTERIZATION . ....... 4-449
A.C. and D.C. Parameters .............. 4-449
Energy/Power Consumption ............ 4-450
Word/Byte-Write and Block-Erase
Times ......." ........................ 4-450
DEVICE RELIABILITY ................. 4-450
Word/Byte-Write and Block-Erase
Cycling .............................. 4-450
Data Protection ........................ 4-451
SUMMARY ............................ 4-451
OTHER REFERENCES ................ 4-451
I
ER-29
INTRODUCTION
The ETOX III (EPROM tunnel oxide) 2/4-Mbit family of Intel boot block Flash Memories are a continuation of boot-top and boot-bottom architectures first introduced in the I-Mbit 28FOOIBX-T and 28FooIBX-B
devices. Top (-T) and bottom (-B) boot block offeringsprovide compatibility for microprocessors that boot
from high or low memory addresses.
All versions of this new family provide a 16-Kbyte
hardware-protected boot block, two 8-Kbyte parameter
blocks and a 96-Kbyte main block. The 2-Mbit products have an additional 128-Kbyte main block, while
4-Mbit offerings contain three additional 128-Kbyte
main blocks.
Flash memories combine inherent non-volatility with
in-system alterability of device contents. Selective block
erasure allows manipulation of data contents within
one of the seven (or five) mini-array segments without
affecting data stored in the other six (or four). Advances in process control have allowed development of
a double-polysilicon single-transistor flash memory capable of 100,000 write/erase cycles per block. The
2/4-Mbit boot block family electrically erases all bits in
a block via electron tunneling. The EPROM programming mechanism of hot-electron injection is employed
for high-performance electrical wordlbyte write as required for computing and embedded applications.
An integrated Command User Interface (CUI) simplifies microprocessor control of device operations (word/
byte write, block erase, erase suspend/resume, Status
Register read/clear, array read and device identifier
read). The internal Write State Machine (WSM) controls all functions and circuits associated with word/
byte-write and block-erase operations, including pulse
widths and repetition, timeout delays, erase preconditioning and margined verifications. The WSM continually updates the internal Status Register during these
functions. The Status Register is read via outputs
DQo-D(h providing feedback ofWSM activities.
The CUI and Status Register interface to power-up/
down-protection circuitry, address/data latches and the
WSM. This interface augments first-generation flash
memory circuitry to optimize Intel's 2/4-Mbit boot
block family for microprocessor-controlled wordlbyte
write and block erase.
A deep-power-down mode enables extremely low power consumption to augment reduced-power standby operation. An automatic power savings feature reduces
Icc during read mode.
I
A 60 ns access time (tACc) results from a memory cell
current of approximately 70 p.A, low-resistance polysilicide wordlines strapped with metal, advanced scaled
periphery transistors and improVed circuit techniques.
The dense one-transistor cell structure, coupled with
high array efficiency, yields a 4-Mbit die measuring 295
by 331 mils and a 2-Mbit die measuring 295 by 221
mils.
Word/Byte-Wide Versions
Intel's 28F400BX is a 4,194,304-bit non-volatile memory organized as either 262,144 words (256K x 16) or
524,288 bytes (512K x 8). A dedicated BYTE# control
input provides selection of the desired input/output
(110) configuration (either x16 or x8)for read operations and data writes.
Intel's 28F200BX is a 2,097,152-bit non-volatile memory organized as either 131,072 words (128K x 16) or
262,144 bytes (256K'x 8). This device also provides
BYTE# control of I/O configunition.
The 28F400BX and 28F2ooBX are available in the 44lead Plastic Small Outline Package (PSOP) and the 56lead Thin Small Outline Package (TSOP).
Byte-Wide Versions
Intel's 28FOO4BX is a 4,194,304-bit non-volatile memory arranged as 524,288 bytes (512K x 8). Intel's
28F002BX is a 2,097,152-bit non-volatile memory arranged as 262,144 bytes (256K x 8).
With lower pin counts compared to their x8/x16 equivalents, the 28FOO4BX and 28FOO2BX allow housing in
the smaller 40-lead TSOP.
TECHNOLOGY OVERVIEW
Intel's ETOX III Flash Memory technology incorporates advances from ETOX I and ETOX II processes, .
and leverages over two decades of EPROM manufacturing experience. Using advanced 0.8 p.m double-polysilicon N-well/P-well CMOS technology, the 2/4-Mbit
boot block flash memories employ a 2.5 p.m x 2.9 p.m
single-transistor cell affording array density equivalent
to comparable EPROM technology, and twice that of
Intel's ETOX II process. The ETOX III flash memory
cell is identical to 0.8 p.m EPROM, except for an additional source implant which optimizes erase performance. Figure 1 shows a cross-section of the flash memory cell.
4-439
ER·29
SECOND LEVEL
POL YSILICON
FIRST LEVEL
POLYSILICON
(FLOATING)
+Vo
GATE OXIDE
294013-1
Figure 1. Flash Memory Cell
High-quality tunnel oxide under the single floating
polysilicon gate promotes electrical erasure. All cells
within the selected block are simultaneously erased via
Fowler-Nordheim tunneling. Applying 12V to block
source junctions and grounding the select gates erases
all cells within that block. The internal WSM controls
the automated block-erase algorithm, including preerase conditioning (i.e. pre-programming all block bits)
and margin verification, in response to user requests
relayed by the CUI. WSM-controlled block erasure, including pre~programming, typically ranges from 1.0 to
2.4 seconds depending on the size of the block selected.
Word/byte write is accomplished with the standard
EPROM mechanism of channel hot-electron injection
from the cell drain junction to the floating gate. Bringing both the select gate and the cell drain to high voltage initiates programming. The WSM regulates the internal word/byte-write algorithm, including margin
verification, after the correct command sequence is
written and decoded. Word/byte write typically requires 9 p.s.
DEVICE ARCHITECTURE
Array Organization
Layout of the 2/4-Mbit boot block family is segmented
as two array planes (see Figure 2). This organization
allows improved access times via minimal internal busing, thus balancing the need for high. speed with the
requirement of small die size for cost-effective solutions. In the 4-Mbit family, each array plane is 1024
rows by 2048 columns. For the 2-Mbit family, each
array plane is 1024 rows by 1024 colum~s. Access time
4-440
is reduced by limiting column length to 1024 cells. The
polysilicon row is strapped in metal every 512 columns
to reduce wordline delay. Two row decoders run vertically along the array plane sides, and column decoders
run horizontally between array plane~. Figure 36 shows
a die photo of the 4-Mbit family.
Each array plane is divided into eight I/Os for the
28F400BX/200BX. The upper plane consistS of the
high-byte I/Os (DQs-DQIS), while the.lower plane
consists of the low-byte I/Os (DQO-DQ7). During
byte-wide operation (BYTE# = "0") the high-byte
I/Os are multiplexed through the low-byte I/Os via
A-I decoding. Data for 1/00 is stored in the left-most
256 columns (or 128 columns. for the 28F200BX) of the
lower plane, with the next 256 columns (or 128) storing
data for 1/01, etc. Data for I/Os is.stored in the leftmost 256 (or 128) columns of the upper plane, with the
next 256 (or 128) columns storing data for 1/09, etc.
For the dedicated byte-wide products (28FOO4BX/
002BX), data fora given I/O is divided between the
upper and lower array planes as decoded by AIO. Data
for 1/00 is stored in the left-most 256 columns (or 128
columns for the 28FOO2BX) of both the upper and lower planes, with the next 256 columns (or 128) in each
plane storing data for I/OJ, etc.
Since each I/O is a grouping of adjacent columns (256
or 128), the independently-erasable blocks (sev~n .or
five) are segmented within each I/O. Each I/O ill the
4-Mbit family is divided into seven' blocks; including a
16,Kbyte boot block, two 8-Kbyte parameter blocks,
one 96-Kbyte main block and three 128-Kbyte main
blocks. Each I/O in the 2-Mbit family is divided into
five blocks; including a 16-Kbyte boot block, two
8-Kbyte parameter blocks, one 96-Kbyte main block
and one 128-Kbyte main block. Each block sour~ is
electrically isolated from the sources of the other six (or
four) blocks .. This allows individual block erase without
altering data in the other blocks.
Addresses A9-Ao select one of 1024 rows. Row address lines are decoded sequentially for selection. Table
3 lists row address bitmaps.
Columns are decoded by AIs-AIO for the 28FOO4BX,
A17-AIO for the 28F400BX and 28FOO2BX, and A16AIO for the 28F200BX. 4-Mbit family columns are
numbered 0-255 for each I/O, and 2-Mbit columns are
numbered 0-127 for each I/O. Table 4 and 5 lists col.
umn address bitmaps.
I
ER-29
I/O 8
I/o 9
I/o 10
I/o 11
I/o 12
I/O 13
I/O 14
I/O 15
(I/O 0)·
(I/o 1)·
(I/o 2)·
(I/O 3)·
(I/O 4)·
(I/O 5)·
(I/O 6)·
(I/O 7)·
COLUMN DECODER
I/O 0
I/O 1
I/o 2
I/O 3
I/o 4
I/O 5
I/o 6
I/O 7
(I/O 0)·
(I/o 1)·
(I/O 2)·
(I/O 3)·
(I/O 4)·
(I/o 5)·
(I/o 6)·
(I/o 7).
294013-2
Figure 2. 2/4-Mbit Boot Block Family Array Organization ((1/0#)* Denotes 28F004BX/002BX I/0s)
Block Memory Map
Top (-T) and bottom (-B) boot block offerings have
block address maps which are inverted from one another to provide compatibility for microprocessors that
boot from high or low memory addresses. Figures 3, 4,
5 and 6 show 28F400BX-T/B, 28F200BX-T/B,
28FOO4BX-T/B and 28FOO2BX-T/B memory maps.
The addresses shown in Figures 3 and 4 for the
28F400BX-T/B and 28F200BX-T/B, decode two bytes
of data. A-I decodes between the two bytes when
BYTE# is low.
Write/Erase Automation
Intel's 2/4-Mbit boot block Flash Memories contain an
on-chip Command User Interface. Write State Machine, Status Register and address/data latches to dramatically simplify user interface. This combination of
functional units reduces microprocessor control
I
complexity of wordlbyte-write block-erase, erase-suspend/resume, Status Register-read/clear, ID-read and
array-read operations. Figures 7 and 8 show
28F400BX/200BX and 28FOO4BXlOO2BX block diagrams.
Command User Interface (CUI)
The CUI consists of a command decoder and command
register. User requests are decoded and latched in a
microprocessor write cycle controlled by Chip Enable
(CE#) and Write Enable (WE#). Status Registerread/clear, ID-read and array-read commands are di. recdy handled by the CUI. The CUI also accepts
wordlbyte-write, block-erase and erase-suspend/resume commands. WE#'s rising edge latches address,
command and data-in registers, and requests WSM initiation of the selected operation. These on-chip address,
command and data latches, controlled by the CUI,
minimize system interface logic and free the system
bus.
4-441
28F400BX·T
28F400BX·B
3FFFFH
3FFFFH
16-Kbyte BOOT BLOCK
3EOOOH
3DFFFH
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
30000H
2FFFFH
3DOOOH
3CFFFH
3COOOH
3BFFFH
8-Kbyte PARAMETER BLOCK
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
20000H
1FFFFH
30000H
2FFFFH
128-Kbyte MAIN BLOCK.
128-Kbyte MAIN BLOCK
10000H
OFFFFH
20000H
1FFFFH
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
04000H
03FFFH
8-Kbyte PARAMETER BLOCK
10000H
OFFFFH
03000H
02FFFH
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
02000H
01FFFH
16-Kbyte BOOT BLOCK
OOOOOH
OOOOOH
Figure 3. 28F400BX·TIB Memory Maps
28F200BX·T
28F200BX·B
1FFFFH
1FFFFH
16-Kbyte BOOT BLOCK
1EOOOH
. 1DFFFH
1DOOOH
1CFFFH
1COOOH
1BFFFH
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
10000H
OFFFFH
96-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
10000H
OFFFFH
04000H
03FFFH
03000H
02FFFH
128-Kbyte MAIN BLOCK
02000H
01FFFH
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
OOOOOH
OOOOOH
Figure 4. 28F200BX·T/B Memory Maps
4-442
I
ER·29
28F004BX·T
28F004BX·B
7FFFFH
7FFFFH
16-Kbyte BOOT BLOCK
7COOOH
7BFFFH
7AOOOH
79FFFH
78000H
77FFFH
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
60000H
5FFFFH
12B-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
40000H
3FFFFH
60000H
5FFFFH
128-Kbyte MAIN BLOCK
12B-Kbyte MAIN BLOCK
20000H
1FFFFH
40000H
3FFFFH
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
OBOOOH
07FFFH
8-Kbyte PARAMETER BLOCK
20000H
1FFFFH
06000H
05FFFH
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
04000H
03FFFH
16-Kbyte BOOT BLOCK
OOOOOH
OOOOOH
Figure 5. 28F004BX·T IB Memory Maps
28FOO2BX·T
28FOO2BX·B
3FFFFH
3FFFFH
16-Kbyte BOOT BLOCK
3COOOH
3BFFFH
3AOOOH
39FFFH
38000H
37FFFH
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
20000H
1FFFFH
96-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
08000H
07FFFH
8-Kbyte PARAMETER BLOCK
20000H
1FFFFH
06000H
05FFFH
8-Kbyte PARAMETER BLOCK
128-Kbyte MAIN BLOCK
04000H
03FFFH
16-Kbyte BOOT BLOCK
OOOOOH
OOOOOH
Figure 6. 28F002BX·T/B Memory Maps
I
4-443
ER·29
Write State Machine (WSM)
The WSM processes word/byte-write, block-erase and
erase-suspend/resume requests received from the CUI.
The WSM rejects word/byte-write and block-erase requests if the WSM is currently busy, if Vpp is not at
high voltage (12V) or if the Low Vpp Status Register
flag is set (i.e. not cleared from a previous low-voltage
condition).
'The WSM consists of an integrated oscillator and control circuitry. It generates signals which control the
word/byte-write, block-erase, erase-suspend/resume
and verify circuits. It also receives feedback from these
circuits, allowing Status Register updates. The WSM
and associated circuits perform the. equivalent of firstgeneration flash memory program and bulk-erase algorithms automatically.
This eliminates the need for system timers, and frees
the microprocessor to service interrupts or perform
other functions during device word/byte-write or
block-erase operations.
The WSM provides feedback to the CUI to determine
when a given command is valid. Although nearly all
commands are available when the WSM is inactive,
only status read is valid while the WSM performs a
word/byte-write operation. During block erase, only
the read-status and erase-suspend commands are available. Read-array, read-status, and erase-resume commands are valid with the WSM in an erase-suspended
state. Invalid operations are interpreted as the read-array command when the WSM is inactive or erase suspended, and as the read-status command when the
WSM is active in word/byte write or block erase.
BYTE#
r~-'I--W.l.--CE.
1+---,l1-4---- WE"
I+-~>----- OE"
L.-.....,.J~------ RP·
... - A" (28,.008X)
.... - ... (28F2008X)
v,,
294013-3
Figure 7. 28F400BX/200BX Block Diagram
4-444
I
ER·29
Status Register
The internal Status Register contains a full complement
of activity status bits. These bits and their meaning,
"1/0" are:
SR.7: WSM status (READY/BUSY#)
SR.6: Erase-suspend status (ERASE SUSPENDED/
ERASE IN PROGRESS # or
COMPLETED#)
SR.5: Block-erase status (ERROR/SUCCESS#)
SR.4: Word/byte-write status (ERROR/SUCCESS#)
SR.3: Vpp status (LOW/OK#)
All bits are set by the WSM, and read via the CUI. The
WSM can only set SR.3, SR.4 and SR.5; it cannot clear
them. They remain set until the CUI processes a clear
Status Register command. There are two reasons for
operating in this fashion. First is synchronization; the
WSM does not know when the host CPU has read the
Status Register, therefore does not know when to clear
it.
Secondly, allowing system software to control reset
adds flexibility to the way this device may be used. The
CPU may write several words/bytes, or erase several
blocks back-to-back, while polling SR.7 to determine
when the next word/byte-write or block-erase command can be given. When all words/bytes are written,
or all blocks erased, the system polls the other status
flags to determine if all operations were successful, or if
an error occurred. While other approaches require the
controlling microprocessor to watch for non-completion of write or erase within a specified time to indicate
an error, this implementation requires no external system timers or software timing loops. As such, the system can reduce its polling overhead while still identifying any potential error conditions.
Status Register contents are driven to device outputs on
the falling edge of CE# or Output Enable (OE#),
whichever occurs last in the read cycle. CE# or OE#
must be toggled to update Status Register contents.
.r--''''-I~-4-4-l--- CEO
t+--Ir--<>-----
WE>
1+---<>------ DE>
L:r-~._Jr------- RP>
'0 Ao -
A" (2BF004ex)
A17 (28F002BX)
294013-4
Figure 8. 28F004BX/002BX Block Diagram
I
4-445
ER-29
Internal Oscillator
The WSM is designed using clocked logic circuits. An
on-chip ring oscillator generates the clock signals. The
frequency of a standard ring oscillator varies with processing, temperature and supply voltage. A proven design used on the 28FOOI BX-T/B, 28FOO8SA and
2/4-Mbit boot block family minimizes these variations.
The switching current of each stage in the ring oscillator is controlled by a current reference which varies
linearly with Vee. The trip point of each ring oscillator
inverter also varies linearly with Vee. These two effects
offset each other, and the resulting oscillator period is
proportional to RC with only a small dependence on
Vee· '
An on-chip resistor sets the value of R. The gate capacitance of the inverters in the ring oscillator sets the
value of C. Process variations in these values are reduced by trimming the period of each oscillator during
manufacturing. The resistor is the only source of temperature variation.
Supply Voltage Sensing
Figure 9 shows the LOWVee and LOWVpp generation circuits. Power supply voltages (Vee and Vpp) are
divided down and compared to a reference voltage. If
VREF is greater than the divided power supply voltage,
the LOWVee or LOWVpp signal is driven high. The
generated VREF level is supply-voltage independent to
the first order.
Positive power to the circuit is supplied by MI and M2.
M I and M2 sources are pulled up to the higher of
(Vpp - Vrn) or (Vee - Vtw)· Vtn is the threshold of
an implanted N-channei device, about 0.9V., Vtw is the
threshold of a native N-channel device, about OV. This
scheme ensures that the circuit works regardless of the
applied supply voltages.
If LOWVee is active, the CUI will not accept user
writes and resets to an array-read condition. The WSM
is similarly reset by LOWVee. The LOWVpp signal is
used by the WSM; if Vpp drops below the high-voltage
detector trip point during word/byte write or block
erase, the Status Register's low Vpp bit is set and WSM
operation halts. The system must clear the Status Register before any subsequent word/byte-write or blockerase operations can succeed.
Deep Power-Down and Device Reset
The 2I4-Mbit boot block family incorporates a deeppower-down mode that reduces Icc and Ipp to typically 0.20 p.A and 0.07 p.A respectively. RP# low selects
deep power-down. When RP # is high, the device can
be placed in an active or standby mode depending on
CE#state.
Deep power-down is similar to standby except that a!l
circuits excluding the RP # buffer are turned off. ThiS
mode greatly reduces power consumption, but requires
more time to transition the device into an active mode.
A read wake-up time (tPHQV) is required from RP#
switching high until output and sense circuitry become
fully functional and data can be read from the part.
Similarly, a write wake-up time (tPHWV is needed before the CUI recognizes writes. After this interval norIiJal operation is restored; the CUI is reset to read-array
mode and the Status Register is cleared to 80H.
Figure 10 shows a diagram of the power-down circuit.
The TTL buffer formed by MI-M3 disables the lowpower detect circuits, the redundancy-address .flash bits
and the CE# TTL buffer formed by M4-M6. These
circuits were always enabled in first-generation Intel
flash architectures. Tum-on delays of these circuits determine RP # access time and write specifications.
The LOWVee signal is used by the word/byte-write
and block-erase circuits, as weII as the CUI and WSM.
LOW POWER
DETECT
REDUNDANCY
CHIP INTERNAL
RESET
N2
LOW Vee
LOW Vpp
294013-5
Figure 9. Low-Power Detector Circuit
4-446
294013-6
'Figure 10. Power-Down and Reset Functions
I
ER-29
RP# functions properly with TTL-level inputs. However, to attain lowest possible power consumption, full
CMOS levels must be used. If the voltage on the gate of
M3 rises above its 0.9V threshold, M3 will turn on and
draw current. Input voltages in the 0.7V -0.9V range
could cause enough current conduction in M3 to exceed the ICC deep-power-down current (IceD) specification. This is why RP # 's input voltage is specified as
GND ±0.2V.
RP# also functions as a hardware reset to the WSM
and CUI. If RP # is driven low ("0") during wordibyte
write, block erase, or erase suspend, that operation is
aborted leaving the addressed memory locations in an
unknown state. The Status Register is cleared, and CUI
is set to array read. The aborted operation (wordlbyte
write or block erase) must be repeated with RP# inactive to obtain a valid condition in the memory array.
RP # reset should be restricted to system reset only (as
in the case of power supply failure), and should not be
used as a standard means to terminate wordlbyte-write
or block-erase operations. NOTE: Use the erase-suspend command to read another block (see the "Erase
Suspend/Resume" section).
This use of RP # during system reset is important with
automated write/erase devices. When the system comes
out of reset it expects to read from the flash memory.
Automated flash memories provide status information
when accessed during write/erase modes. If a CPU reset occurs with no flash memory reset, proper CPU
initialization would not occur because the flash memory would be providing the status information instead of
array data. Intel's Flash Memories allow proper CPU
initialization following a system reset through the use
of the RP# input.
Automatic Power Savings
The 2/4-Mbit boot block flash memories include an
automatic power-savings feature that reduces IcC during read mode. Within one access time (tAee or teE)
after an address or CE# switches, Icc automatically
powers down from the 60 rnA Icc CMOS specification
(or 65 rnA TTL specification) to less than 1 rnA. Icc
remains below 1 rnA until either CE# or an address is
switched, or until the device is taken out of read mode.
This feature provides significant power savings for applications that access the device slower than their specified read access times.
Block Erase
Block erasure is achieved by a two-step write sequence.
The erase-setup code is written to the CUI in the first
cycle. Erase confirm is written in the second cycle. The
address supplied with the erase-confirm command is
latched and decoded internally by the device; erase is
subsequently enabled in that block. The second WE#
rising edge initiates the operation (WE#-controlled
write).
The WSM triggers the high-voltage flash-erase switch
connecting the 12V supply to the source of all bits in
the specified block, while all wordlines are grounded.
Figure 12 shows organization of the block source
switches. Fowler-Nordheim tunneling results in simultaneous erasure of all bits in the selected block.
The block source switch (shown in Figure 11) controls
the source voltage of all bits in a particular block. During block erase, M2 is off and M 1 pulls the source to
Vpp. When not in erase, Ml is off and M2 pulls the
source to ground. The high-voltage latch formed by
M4-M7 converts the low-voltage ERASE signal to a
high-voltage signal that controls Ml.
1.41
BLOCK
r---~p-. SOURCE
LOW Vee )-....- - - - - - - - - 1 1 - - - - - 1
ERASE>------------------~--~ ~~----~
294013-7
Figure 11. Block Source Switch
I
4-447
ER·29
r--------------------------------IP-------------------------------
-.------------------------~~
BOOT BLOCK
SOURCE
PARAMETER BLOCK 0
SOURCE
PARAMETER BLOCK 1
SOURCE
MAIN BLOCK 0
SOURCE
MAIN BLOCK 1
SOURCE
2Mb
MAIN BLOCK 2
SOURCE
MAIN BLOCK 3
SOURCE
1 4 M bI
~---------------------------------.
294013-8
Figure 12. Array Erase Blocking
The tunneling that occurs during block erase requires
only a small amount of current. However, the initial
current required to charge the block's cumulative
source capacitance to the erase voltage is large. Supply
decoupling design practices minimize the system impact of the source charging.
The LOWVcc signal protects the array from erasure
when Vpp is at a high voltage, but Vee is below the
write/erase lockout voltage (VLKO). When this occurs,
M3 pulls the block source to ground. The high-voltage
latch is forced by M8 into the state that turns MI off.
Vpp is continually monitored during all phases of the
block-erase operation. If Vpp falls below the trip point
of its high-voltage detect circuitry, erasure will not occur (or halts) and Status Register Vpp status (SR.3),
block-erase status (SR.5) and WSM status (SR.7) bits
are set to "I".
If SR.3 is set (Low Vpp), WSM operation is inhibited.
The WSM will not execute further wordlbyte-write or
block-erasure sequences until the Status Register has
been reset by system software. Wordlbyte-write or
block-erase requests with error flags SRA or SR.5 set
are not inhibited, but the system loses the ability to
determine success. The clear Status-Register command
resets these bits.
4-448
After receiving the block-erase command sequence, the
WSM automatically controls block pre-condition (programming all words to OOOOH within the chosen block),
erase pulses and pulse repetition, timeout delays, and
word-by-word verification of all block addresses (sequentially checked via the address counter) using an
alternative sensing reference to verify margin. The internal erase and verify operations continue until the entire block is erased. A read cycle applied to the part
following the block-erase command sequence outputs
Status Register contents; system software can poll the
Status Register to determine when block erase has successfully completed. Following block erasure, the device remains in Status Register read block erasure, the
device remains in Status Register read mode; a read-array command must be written to the device to access
array data.
If the erase-setup command is followed with a command other than erase confirm, the device will not
erase. The WSM sets both wordlbyte-write status and
block-erase status bits in the Status Register to indicate
an invalid sequence..
I
ER-29
Erase Suspend/Resume
Erase suspend allows the system to interrupt block
erase to read data from another array block. The ability
to suspend erase and read data from another block offers the flexibility required for embedded applications.
Upon receiving the erase-suspend command. the CUI
requests that the WSM pause at one of several predetermined points in the algorithm. Upon reaching a suspend point, the WSM sets SR.6 (erase-suspend status)
and SR.7 to "I". The system must poll the Status Register to determine if the suspend has been processed or
the block erase has actually completed. Block-erase
completion is indicated by SR.6 cleared to "0" and
SR.7 set to "1". Read bus cycles default to Status Register read after issuing the erase-suspend command.
Once suspended, the WSM asserts a signal to the CUI
which allows response to the read-array, read-status,
and erase-resume commands. The system can write the
read-array command allowing read access to blocks
other than that which is suspended. The WSM continues to run, idling in a suspended state, regardless of all
control inputs except RP #. RP # driven low immediately shuts down the WSM, aborting the suspended
erase operation.
The erase-resume command must be issued upon completion of reads from other array blocks to continue
block-erase operation. The WSM then clears SR.6 and
SR.7, and resumes erase operation from the suspension
point. Read cycles following the erase-resume command output Status Register data.
Word/Byte Write
Wordlbyte write follows a flow similar to block erase.
The wordlbyte-write-setup command is first written to
the CUI. A second write cycle loads address and data
latches. The rising edge of the second WE# pulse requests that the WSM initiate activity, applying high
voltage to the gates and drains of all bits to be written.
Unlike block erase, wordlbyte write will proceed regardless of what data is applied on the second CUI
write cycle; however writing data FFFFH (or FFH)
does not modify memory contents.
Like block erase, the WSM controls program pulses
and pulse repetition, timeout delays and wordlbyte verification. Wordlbyte write and verify (with alternate
sensing reference and internally-generated verify voltage) continue until the wordlbyte is written. Internal
wordlbyte-write verify checks that all bits written to
zero have been correctly modified; it does not check
I
bits specified as one. Wordlbyte write cannot change
existing zeros to ones; this can only be accomplished by
erase.
Read bus cycles following wordlbyte-write operations
output Status Register data. System software, polling
the Status Register, is informed of status through bits
SR.3, SR.4, and SR.7. The read-array command must
be written to the CUI following wordlbyte write to
access array data.
In a scenario similar to that described under block erasure, wordlbyte write does not occur (or halts) ifVpp is
detected low. In such a case SR.3, SR.4, and SR.7 are
set high, and no further writes can take place until the
Status Register is cleared by the Clear Status Register
command.
DEVICE CHARACTERIZATION
AC and DC Parameters
Figures 14 through 35 show graphs of several device
parameters as a function of temperature and supply
voltage.
In particular, note Figure 14 which shows typical read
performance tAVQV (tACe) of the 28F400BX, which is
representative of the 2/4-MBit boot block flash memory family, as a function of Vcc and ambient temperature. tELQV (tCE) in Figure 15 and tGLQV (tOE) in
Figure 16 are also of particular interest. Access times
tAVQV, tELQV, and tGLQV are specified and tested with
an output load of 100 pF; decreased output load capacitance improves device operation.
Table 1 shows typical supply currents f9r several operating modes.
Table 1. RMS Current Values
Mode
lee
(Vee = 5.0V,
CMOS Inputs)
x8
x16
Ipp
(Vpp = 12V)
Read (6 MHz)
23mA
25mA
100/LA
Write
20mA
22mA
10mA
Block Erase
15mA
15mA
12mA
Standby
50/LA
50/LA
100/LA
Deep Power-Down 0.20/LA 0.20/LA
0.07/LA
4-449
ER-29
Energy/Power Consumption
DEVICE RELIABILITY
The system designer may be concerned with power consumption during block erase and wordlbyte write. Figure 32 shows Icc and Ipp during block erase. Figure 33
shows Icc and Ipp during wordlbyte write.
Word/Byte-Write and Block-Erase
Cycling
Word/Byte-Write and Block-Erase
Times
The 2/4-Mbit boot block family and 28F008SA advance wordlbyte-write and block-erase performance
compared to previous flash memories. The on-chip algorithm is improved over the 28FOOIBX to take advantage of process enhancements. This improvement is
most apparent when compared to first-generation flash
memory parts with externally controlled algorithms.
First-generation device times shown in Table 2 assume
optimal system overhead, and as such are absolute best
case.
One of the most important reliability aspects of the
2/4-Mbit boot block family is its capability of 100,000
write/erase cycles per block. Destructive oxide breakdown has been a limiting factor in extended cycling of
thin-oxide EEPROMs. Intel's ETOX Flash Memory
technology extends cycling pefrormance through:
• Improved tunne1-oxi4e processing that increases
charge-carrying capability tenfold.
• Significantly reduced oxide area under stress that
minimizes probability of oxide defects in the region.
• Reduced oxide stress due to a lower peak electric
field (lower erase voltage than EEPROM).
Table 2. Word/Byte-Write and Block-Erase
Performance vs Previous Devices
Device
Word/ByteWrite Time
Block-Erase
Time/ # Bytes
Erase Time
per Kbyte
SECOND-GENERATION FLASH MEMORY DEVICES(1)
2.4s/12SKB
2.2s/96KB
1.0s/16KB
1.0s/SKB
19 ms
23ms
63 ms
125 ms
2SF400BX
2SF004BX
2SF200BX
2SF002BX
9,..,s
9,..,s
9,..,s
9,..,s
2SFOOSSA
9,..,s
1.5s/64KB
23ms
1B,..,s
3.Bs/112KB
2.1s/BKB
2.1s/4KB
34ms
256ms
513 ms
2BF001BX
FIRST-GENERATION FLASH MEMORY DEVICES(2)
2BF020
16.5,..,s
6.Bs/256KB
27ms
2BF010
16.5 ,..,s
3.9s/12BKB
30ms
2BF512
16.5 ,..,s
2.4s/64KB
37ms
2BF256A
16.5,..,s
1.6s/32KB
51 ms
NOTES:
1. Typical measured time.
.
2. Times calculated based on typical erase and precondition pulse requirements,
with minimum write timings. Calculations are described in Figure 13.
4-450
I
ER-29
Reliable wordlbyte-write and block-erase cycling requires proper selection of the maximum erase threshold
voltage (Vt), and maintenance of a tight distribution.
Maximum erase Vt is set to 3.4V via the internal blockerase algorithm and verify circuits. Tight erase Vt distribution gives an order of magnitude of erase-time
margin to the fastest erasing cell, with virtually identical erase Vt distributions at I and 10,000 cycles (Figure
34). Program Vt distribution is similarly consistent over
cycling (Figure 35).
Data Protection
The 2/4-Mbit boot block family offers protection
against accidental block erasure or wordlbyte write
during power transitions. Internal circuitry creates a
device insensitive to Vpp/Vee supply power-up/down
sequencing.
Vpp S; VPPLMAX locks out wordlbyte-write and
block-erase circuits. Vee S; VLKO disables CUI command writes, resets the CUI to array-read mode, and
holds the WSM inactive. The system designer must still
guard against spurious command writes for Vee >
VLKO when Vpp < VpPLMAX.
Several strategies are available to prevent data modification in the 2/4-Mbit family. The CUI provides a degree of software write protection since memory alteration occurs only after successful completion of a twostep write sequence. WE# and CE# must both go active to perform this sequence; driving either high inhibits command/data writes. Secondly, the system can
place the device in deep-power-down mode (RP# =
Vld to disable command writes, reset the CUI to array-read mode, and hold the WSM inactive, effectively
protecting array data and providing a way to reset the
flash memory during system reset conditions. Finally,
the system designer may switch Vpp to VPPH when
memory updates are required.
I
SUMMARY
Intel's 2!4-Mbit boot block Flash Memory family contains features that optimize this product group for computing and embedded applications. These features include hardware-implemented write/erase protection of
the boot block, specialized array blocking, dedicated
x8 and xS/16 user-configurable versions, automation
of wordlbyte write and block erase, erase suspend for
data read, deep-power-down/automatic-power-savings
modes, reset capability, and a write/erase Status Register. With simple microprocessor interfacing and software command sequences, this family is the non-volatile computing and embedded solution of choice for today's designs.
OTHER REFERENCES
Related documents of interest to readers of this engineering report:
2SF400BX-T/B, 28F004BX-T/B; "4-Mbit Flash Memory Family" Data Sheet (Order #290450)
2SF400BX-TL/BL, 2SFOO4BX-TL/BL; "4-Mbit Flash
Memory Family" Data Sheet (Order #290451)
28F200BX-T/B, 28F002BX-T/B; "2-Mbit Flash Memory Family" Data Sheet (Order #29044S)
28F200BX-TL/BL, 2SF002BX-TL/BL; "2-Mbit Flash
Memory Family" Data Sheet (Order #290449)
ER-28 "ETOX III Flash Memory Technology" Engineering Report (Order #294012)
AP-341 "Designing an Updatable BIOS Using Flash
Memory" (Order #292077)
AP-363 "Extended Flash BIOS for Portable Computers" (Order #292098)
4-451
ER-29
SUPPLEMENTARY INFORMATION
FORMULA:
b =
n =
# bytes in
w=
Time for a write cycle (150 ns, tAVAV)
v=
p=
Time to verify (6055 ns, tWHGL + tGLQV)
Program pulse width (10 j.Ls, tWHWHl)
one pulse programming assumed
Erase pulse width (10 ms, tWHWH2)
e
=
75
~
block (256K, 128K, 64K, 32K)
# of erase pulses required (90 pulses)
~-40oc
70
65
60
Vl
'""
..s
0
0
-<
Precondition and precondition verify time is:
b (2w + P + v)
55
'"
""-
45
I".....
40
Erase/verify, each loop where some byte
does not pass verify:
(n - 1) (2w
+
e
+
+
e)
~
1\~
50
I~
~
i"'- i'B. "E .........
'"""'l
~
, ...re-
:-
r-
-e-:- r-..
"t:t-
r--i
Vee (V)
294013-9
Passing erase-verify, all bytes:
b (w
--
:::-r-- ......
30
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
Last erase pulse:
(1) (2w
~ '-..,
~
......
35
v)
-0- DoC
--I:r- 85°C
-111- !OOOC
Figure 14. tAVQV (tACC)
vs VCC and Temperature
+ v)
Total time can be summarized as:
b (3w
+
P
+
2v)
+
+
n (2w
e
+ v)
- (v)
or substituting in times for write, verify,
program and erase pulse widths:
b (22.56 X 10- 6) + n (10.006355 x 10- 3) (6.055 x 10- 6) Seconds
Figure 13. Erase Time Calculations for
First-Generation Flash Memories
80
28
26
~
24
,\"
~-40oC
75
70
~
"'~~ t'....
65
Vl
'""
..s
60
55
'" 50
..9
45
40
-0- DoC
--I:r- 85°C
-II1-100 o C
22
I"A ~ r-.
20
-~
.........
["..
"'&..,
"
'1::L
~~
-.::I~
,,
35
.:::- I'---........
18
~
16
14
~
~
fa. .,...
~
"--tp
30
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
12
~-40OC
~
-0-: DoC
--I:r- 85°C
-111- !OOOC
If::
I"l ~
"""-"- I&- '"
. . . r-s, - "
~
~ tl'-
~~
"l:I --t
~ ""- ....;:;
10
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
Vee (V)
Vee (V)
294013-11
294013-10
Figure 15. tELQV (tCE)
vs VCC and Temperature
4-452
Figure 16. tGLQV (tOE)
vs VCC and Temperature
I
ER-29
46
--0- -40°C
44
-0- OOC
42
--A- 85°C
40
~
~100oC
38
...... ."q
36
~
34
Ul
~
32
.5
I&30
U1
~
$'
~
28
......,
I"s..
26 .........
'E
24
22
"""'E3
"" ;;;;::.:::: I--.
20
......... Is..
18
16
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
l'-
r-....
'"-"
'"
"'"
-....
f'-...
rs..
r-
-14
1--8"
-16
jt-"f"'
-18
La- ""'"
-20
-~
V
.-' ~
-22
~
IB'"
,...., -24
. / I'"
Vl
-26
.5 -28 . /
::t:
. /V
$' -30
;...--IN- V
-32
,.....
./
-34
./
-36
.....
rv
....
/,
-38
V/
-40
Ii
-42
-44 L
-46
4.0 4.2 4.4 4.6 4.8 5.0 5.2
te-
r-
-
~
--0- -40°C
-0- OOC
--A- 85°C
~100oC
5.4 5.6 5.8 6.0
Vee (V)
Vee (V)
294013-13
294013-12
Figure 18. tWHO)( (tOH WE#)
vs Vee and Temperature
Figure 17. tOVWH (tos WE#)
vs Vee and Temperature
40
38
36
34
30
U1
26
-<
28
"'
I'-.
i'.t. I'-..
~ J'-.,
18
16
"'"I-l::t---......
IB.....
.........
...... i'A,
'""S
r--.....
-
,....,
Vl
.5
r-::'
-~
f&. t--
-16
::t:
-< -18
-22
-24
~
-I--tb
14
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
V
I---"'"
./
[....e V
~
~
J....- ~
~
i /~
Ik'"
V
~ t:.-
eV
l..A ~ VI'"
~ I--""T
V; V
--0- -40°C
-0- OOC
--A- 85°C
V
~100oC
/
-26
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
Vee (V)
Vee (V)
294013-14
Figure 19. tAVWH (tAS WE#)
vs Vee and Temperature
I
-14
~
IV
-20
"J..........
j-s ......
..,..Iii-- ~
-10
-12
.............
22 i....
-8
~100oC
-"1'-.,
24
20
--0- -40°C
-0- OOC
--A- 85°C
I'..
32
,....,
U1
.5
-
-6
r-...
c-
294013-15
Figure 20. tWHAX (tAH WE#)
vs Vee and Temperature
4-453
ER-29
46
-0- -40°C
44 l'..
-0- OOC
42 I'..
-IJr- 85°C
40
....Ii/-l00oC
38
~
36
"li
34
.....,
VI
'"'
'32
-5
I'..: Mt.
~
VI 30
$I
~
~
..........
28
"s..
26
""Eh
..........
24
........
.......
22
--e..
'""'-Is
20
Ie..
18
go.
16
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
"" ." l'...
t'-.
:---..
r-....
- -
--.
-14
j...8'"
-16
P
~
...t:
-18
b- f-eIa'"
-20
V
V
-22
~
-24 III'"
~
....... f"'1
Vi' -26
-5 -28 . /
V
:I:
V Ir"'
$I -30
k
-32
j ' Jr
-34
/p'"
-36
J
-38
-0- -40°C
1/
-40
-0- OOC
-42
-IJr- 85°C
-44 /
....Ii/-l00oC
-46
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
t:=::
Vee (V)
Vee (V)
294013-17
294013-16
Figure 22. tEHOX (tOH CE # )
vs Vee and Temperature
Figure 21. tOVEH (tos CE#)
vs Vee and Temperature
-6
40
38
36
34
'-.'-.."
32
VI
'"'
30
-5
28
VI
26
_c(
24
22
20
18
16
-0- -40°C
-0- OOC
"
'- ."
...........
rs..
ra" t-...
A..
""S
~
-
~
r-....
.......,
re- I--
--
:I:
_c(
"--I
V
V
V
II""
~
-20
/
l/.:V
re--
~
~
f-C"
V
~~
It"
-18
-24
Vee (V)
~
V ~
~~
1/'1'
-0- -40°C
-0- ooe
-IJr- 85°C
....Ii/-l00oC
V
-26
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
Vee (V)
294013-18
4-454
-5 -16
-22
14
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
Figure 23. tAVEH (tAS CE#)
vs Vee and Temperature
VI
'"'
-14
./ ~
la"
-12
~ t--
'151 r-....
.- ~
-10
....Ii/-l00 o C
~ Iw..
r-s.
-8
-IJr- 85°C
.........
-
294013-19
Figure 24. tEHAX (tAH CE #)
vs Vee and Temperature
I
ER-29
60
-55
-0- -40°C
-<>- OOC
-I!r- 85°C
-V-100oC
55
r" ~
50
"-
45
-t: t'v.
"'&
c..
~
40
35
~
30
'"&..
"B25
r-e.
r-. ~ ~
r-s
~ '--~
........
-
......
-45
«
'""'
ra.... ~ ::::::
~ .........
-50
'&..
~
-0- -40°C
-<>- OOC
-I!r- 85°C
-V-100oC
-35
...J
lI-
-30
-25
-20
-15
is- --s- I--
I--tb
20
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
....e
/~
:I:
:--r-
;a'
-40
-5
..9
./
~
va
./
,/'
V
V~
4
-10
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
Vee (V)
294013-20
294013-21
Figure 25. tWLWH (twp)
vs Vee and Temperature
Figure 26. IOH TTL
vs Vee and Temperature
23
<-
-5
....I
..9
18
is'"'
t'""""
17
~
15 ~
14
13
12
-
----
,...k
~
r-
'""'
-7.5
4:
-5
~
..9 -5.5
A.-I-""""
-5.0
e::. :....-
-
10
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
Vee (V)
ct".....a
~
:::E
u -6.0
:I:
-4.5
-4.0
---' t'""""
...-V
~ -6.5
-~
...- ~
~
~
........
~
~
-
~
IAr-:: ~
.k- ~ ~
t--:: i - r>r
-3.5
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
Vee (V)
294013-22
Figure 27. IOL vs Vee and Temperature
(VOL = O.45V)
I
-7.0
-0- -40oC-<>- OOC
-I!r- 85°C -V-100oC ...,
-
--' k -
i..-'a
~
~~
.sY I-"
16
11
-0- -40°C
-<>- OOC
-8.5 -I!r- 85°C
-8.0 -V-100oC
-9.0
"",,......-Iii!"""
20
19
-9.5
....... b
II::!-" ...e--
21
V
1P
~
k::::
Vee (V)
22
V
i"J p'
,,/ ./"
...6~ ~
7
'I"'" ~
~
/'
V
294013-23
Figure 28. IOH CMOS vs Vee and Temperature
4-455
ER-29
75
7!\
70
65
60
55
)r
50
~
-5
u
.P
45
35
Jr
30
25
20
10
'"
r
~
V
./
J.
70
65
60
./
55
/
50
~
./
40
15
V
~
v
-5
V
u
_u
----, r-o-ooC
-0- 25°C - f-I:Jt- 70°C - r--
45
40
~
35
~
30
25
)~
20
..)~
15
10
5
'"
'"
~
- -0- OOC
-0- 25°C - -I:Jt- 70°C - -
't'"
j
5
1 2 3 4 5 6 7
B 9 10 11 12 13 14 15 16
1 2 3
4 5 6 7 B 9 10 11 12 13 14 15 16
FREQUENCY (MHz)
FREQUENCY (MHz)
294013-25
294013-24
Figure 29. Icc (RMS) vs Frequency
x16 Operation
Figure 30. Icc (RMS) vs Frequency
x8 Operation
100
95
90
85
"
-5
1l
/'
80
75
-< 70
65
60
V
/'
".,.,.
/'
/'
./
V
. /V
".,.,.~
~~
-0- 2BF400BX/2BFOO4BX-60
--0- 2BF400BX/2BFOO4BX-BO
55
50
30 50
100
150
200
250
OUTPUT CAPACITANCE (pF)
294013-26
Figure 31. Access Time vs Output Loading
4-456
I
ER-29
4SmA
SmA
/DIV
-SmA
-200mS
200mS/DIV
loBS
294013-27
36mA
Ipp ERASE
4mA
/DIV
.1111
tf,
-4mA .
-200mS
r---
I--.
lMl.,
200mS/DIV
loBS
294013-28
Figure 32. Icc and Ipp during Block-Erase Operation
I
4-457
ER-29
180mA
I
ICC WRITE
20mA
/DIV
I'
I 1\
\.
I
-
./
I\.
'v
~
-20mA
-1 j.LS
1 j.LS/DIV
9j.LS
294013-29
45m A
I
Ipp WRITE
5m A
/D IV
L.
\
111
k
\J""
.. -
A
1 j.LS/DIV
9 j.LS
294013-30
Figure 33. Icc and Ipp during Word-Write Operation
4·458
I
ER-29
Erased Vt Dist. vs Cycling; Vpp = 12V; TA = Room
99.999
99.99
>I99.9
-l
99
ID
I
I
I J
I II
50
AFTER 10k __
~
PiE CYCLES
i=
:::E
::::>
u
10
1
0.1
0.001
J!!'!'
-
~
l
P
VI~ V-
I,
I'--- BEFORE
CYCLING
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
V (V)
294013-31
Figure 34. Typical Process Data for Erase Vt vs Cycles
Programmed Vt Dist. vs Cycling; Vpp = 12V; TA = Room
/
99.999
>- 99.99
I99.9
-l
99
ID
(
90
50
-l
::::>
:::E
::::>
u
AFTER 10k
P
CYCLES--
IE
10
/
rl
I~ _
I
)
1
0.1
0.001
II
5.5
6.0
BEFORE
CYCLING -
I
I
.I
J
0.0
,/
/'
I
I--
I-
D.. >0
"....30
.
....
A14
A13
A7
AS
AS
Ag
AS
1<,1
A4
OE#
A3
1<,0
A2
0
A14
A13
N28F020
32 - LEAD PLCC
0.450" x 0.550"
TOP VIEW
AS
Ag
All
OE#
CE#
Al
A10
D~
Ao
CE#
DOs
000
007
DOS
D04
0" ~ ~ r5' o"'lt Cf OlD
c c > c c c c
D03
290245-3
290245-2
I
5-3
28F020
APPLICATIONS
The 28F020 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These features make the 28F020 an innovative alternative to
disk, EEPROM, and battery-backed static RAM.
Where periodic updates of code and data-tables are
required, the 28F020's reprogrammability and nonvolatility make it the obvious and ideal replacement
for EPROM.
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption - a consideration particularly important in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and application code. With updatable code, system manufacturers can easily accommodate last-minute changes as
revisions are made.
In diskless workstations and terminals, network traffic reduces to a minimum and systems are instanton. Reliability exceeds that of electromechanical
media. Often in these environments, power interruptions force extended re-boot periods for all networked terminals. This mishap is no longer an issue
if boot code, operating systems, communication protocols and primary applications are flash-resident in
each terminal.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F020 flash memory offers a solid
state alternative in a minimal form factor. The
28F020 provides higher performance, lower power
consumption, instant-on capability, and allows an
"execute in place" memory hierarchy for code and
data taDle reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause .
disk-based systems to fail.
The need for code updates pervades all phases of a
system's life - from prototyping to system manufacture to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F020 allows incircuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexibility.
5-4
Material and labor costs associated with code
changes increases at higher levels of system integration ---' the most costly being code updates after
sale. Code "bugs", or the desire to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the removal of EPROM components or entire boards. With
the 28F020, code updates are implemented locally
via an edge-connector, or remotely over a communcations link.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Flash memory's electrical chip erasure, byte programmability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a "blank slate" in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new "blank slate".
A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 4 depicts two 28F020s tied to the 80C186 system bus.
The 28F020's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mm thickness. With standard and reverse pin configurations, TSOP reduces
the number of board layers and overall volume necessary to layout multiple 28F020s. TSOP is particularly suited for portable equipment and applications
requiring large fimounts of flash memory. Figure 3
illustrates the TSOP Serpentine layout.
With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility,
the 28F020 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today's designs.
I
28F020
nnnnnnnnnnnnnnn[)-
Innnr -nnnni
IlL ~II
0
nnnnnnnnnnnnnnnr
0
0
N
0
rT1
I\)
0
N
0
rT1
I\)
..,co
LL.
..,co
I\)
N
I\)
N
LL.
0
LL.
ao
0
0
1>
LL.
ao
0
I\)
N
a..J
0
0 0
-6>
r'- r-
0
N
0
N
ao
r-
, while Chip-Enable is
low.. Addresses are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/
Programming' Waveforms for specific timing
parameters.
COMMAND DEFINITIONS
When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only ,operations.
Placing high voltage on the Vpp pin enables read/
write operations. Device operations are selected by
writing specific data patterns into the command register. 'Table 3 defines these 28F020 register
commands,
Table 3. Command Definitions
Command
The command register itself does not occupy an addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.
Bus
First Bus Cycle
Second Bus Cycle
Cycles
Req'd Operation(1) Address(2) Data(3) Operatlon(1) Address(2) Data(3)
Read Memory
1
Write
X
OOH
Read Intelligent Identifier Codes(4)
3
Write
X'
90H
Read
(4)
(4)
Set-up Erase/Erase(S)
2
Write
X
20H
Write
X
20H
Erase Verify(S)
2
Write
EA
AOH
Read
X
EVD
Set-up Program/Program(S)
2
Write
X
40H
Write
PA
PD
Program Verify(S)
2
Write
X
COH
Read
X
PVD
Reset(?)
2
Write
X
FFH
Write
X
FFH
NOTES:
1. Bus operations are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. ID = Data read from location IA during device identification (Mfr = 89H, Device = BDH).
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes.
5. Figure 6 illustrates the Quick-Erase Algorithm.
6. Figure 5 illustrates the Quick-Pulse Programming Algorithm.
7. The second bus cycle must be followed by the desired command register write.
5-8
I
28F020
Read Command
While Vpp is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.
The default contents of the register upon Vpp power-up is OOH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 28F020, the device powers-up and
remains enabled for reads until the command-register contents are changed. Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters.
Intelligent Identifier Command
Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a desired system-design practice.
The 28F020 contains an Intelligent Identifier operation to supplement traditional PROM:programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address OOOOH retrieves the manufacturer code of 89H. A read cycle
from address 0001 H returns the device code of
SDH. To terminate the operation, it is necessary to
write another valid command into the register.
of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.
Erase-Verify Command
The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing AOH into the command register. The address
for the byte to be verified must be supplied as it is
latched on the falling edge of the Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse.
The 28F020 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resiJmes from the
address of the last-verified lJyte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 6, the Quick-Erase algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F020.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.
Set-up Program/Program Commands
Set-up Erase/Erase Commands
Set-up· Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.
To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (Le., Erase-Verify Command).
This two-step sequence of set-up followed byexecution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pin. In the absence
I
Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.
Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising
edge of the Write-Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
parameters.
5-9
28F020
Program-Verify Command
The 28F020 is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F020 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 5,
the 28F020 Quick-Pulse Programming algorithm, illustrates how commands are combined with bus operations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.
Reset Command
A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.
EXTENDED ERASE/PROGRAM CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubledan expensive solution.
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately
2 MV/cm lower than EEPROM. The lower electric
5-10
field greatly reduces oxide stress and the probability
of failure-increasing time to wearout by a factor of
100,000,000.
The 28F020 is capable of 100,000 program/erase
cycles. The device is programmed and erased using
Intel's Quick-Pulse Programming and Quick-Erase
algorithms. Intel's algorithmic approach uses a series of operations (pulses), along with byte verification, to completely and reliably erase and program
the device.
For further information, see Reliability Report RR-60.
QUICK-PULSE PROGRAMMING ALGORITHM
The Quick-Pulse Programming algorithm uses programming operations of 10 J.Ls duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with Vpp at high voltage. Figure 5 illustrates the Quick-Pulse Programming algorithm.
QUICK-ERASE ALGORiTHM
Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F020 is erased when shipped from the factory.
Reading FFH data from the device would immediately be followed by device programming.
For devices being erased and reprogrammed, uniform and reliable erasure is ensured by first programming all bits in the device to their charged state
(Data = OOH). This is accomplished, using the
Quick-Pulse Programming algorithm, in approximately four seconds.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in two seconds. Figure 6 illustrates the Quick-Erase algorithm.
I
28F020
Bus
Operation
Command
Standby
Comments
Wait for Vpp Ramp to VPPH(1)
Initialize Pulse-Count
Set-up
Program
Data
Write
Program
Valid Address/Data
Duration of Program
Operation (tWHWH1)
Standby
Write
Program(2)
Verify
Data = COH; Stops Program
Operation(3)
Standby
tWHGL
Read
Read Byte to Verify
Programming
Standby
Compare Data Output to Data
Expected
Write
Standby
290245-7
NOTES:
1. See DC Characteristics for the value of VpPH and
VPPL·
2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command.
= 40H
Write
Read
Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to Vppd1)
3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de·
vice.
Figure 5. 28F020 Quick·Pulse Programming Algorithm
I
5-11
intet®
28F020
Bus
Operation
Command
Comments
Entire Memory Must
Before Erasure
=
OOH
Use Quick-Pulse
Programming Algorithm
(Figure 5)
Standby
Wait for Vpp Ramp to VPPH(1)
Initialize Addresses and
Pulse-Count
Write
Set-up
Erase
Data
=
20H
Write
Erase
Data
=
20H
Standby
Duration of Erase Operation
(tWHWH2)
Standby
Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(3)
tWHGL
Read
Read Byte to Verify Erasure
Standby
Compare Output to FFH
Increment Pulse-Count
Write
Write
Erase(2)
Verify
Read
Standby
290245-8
1. See DC Characteristics for the value of VPPH and
VPPL·
2. Erase Verify is performed only after chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
Data = OOH, Resets the
Register for Read Operations
Wait for VPP Ramp to VppL!1)
3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.
Figure 6. 28F020 Quick-Erase Algorithm
5-12
I
28F020
DESIGN CONSIDERATIONS
Two-Line Output Control
Flash-memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an address-decoder output should drive chip-enable,
while the system's read signal controls all flashmemories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power standby condition.
Power Supply Decoupling
Flash-memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current (Ieel issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 /LF ceramic capacitor
connected between Vee and Vss, and between Vpp
and Vss.
Place the high-frequency, low-inhere nt-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 /LF electrolytic capacitor should be placed at the array's power supply
connection, between Vec and Vss. The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.
Vpp Trace on Printed Circuit Boards
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the Vpp power supply trace. The Vpp pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given the Vee power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.
I
Power Up/DownProtection
The 28F020 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 2BF020 is indifferent
as to which power supply, Vpp or Vee, powers up
first. Power supply sequencing is not required.
Internal circuitry in the 28F020 ensures that the
command register is reset to the read mode on power up.
A system designer must guard against active writes
for Vee voltages above VLKO when Vpp is active.
Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes.
The control register architecture provides an added
level of protection since alteration of memory contents only occurs after successful completion of the
two-step command sequences.
28F020 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F020 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F020.
Table 4. 28F020 Typical
Update Power Dissipation(4)
Operation
Notes
Power Dissipation
(Watt-Seconds)
Array Program/Program Verify
1
0.34
Array Erase/Erase Verify
2
0.37
One Complete Cycle
3
1.05
NOTES:
1. Formula to calculate typical Program/Program Verify
Power = [Vpp x # Bytes x typical # Prog Pulse
(tWHWH1 x IpP2 typical + tWHGL X IpP4 typical)) + [Vcc
x # Bytes x typical # Prog Pulses (tWHWH1 x ICC2 typical + tWHGL X ICC4 typical)].
2. Formula to calculate typical Erase/Erase Verify Power
= [Vpp (lPP3 typical x tERASE typical + IpP5 typical x
tWHGL X # Bytes)] + [VCC (ICC3 typical x tERASE typical
+ ICC5 typical x tWHGL X # Bytes)].
3. One Complete Cycle = Array Preprogram + Array
Erase + Program.
4. "Typicals" are not guaranteed but based on a limited
number of samples from 28F020-150 production lots.
5-13
28F020
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature
During Read .................. o·C to + 70·C(1)
During Erase/Program ......... o·c to + 70·C(1)
Operating Temperature
During Read ............... - 40·C to + 85·C(2)
During Erase/Program ...... - 40·C to + 85·C(2)
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
Temperature Under Bias ....... -10·C to + 80·C(1)
Temperature Under Bias ....... - 50·C to + 95·C(2)
Storage Temperature .......... - 65·C to + 125·C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Voltage on Pin Ag with
Respect to Ground ....... - 2.0V to + 13.5V(2. 3)
Vpp Supply Voltage with
Respect to Ground
During Erase/Program .... - 2.0V to + 14.0V(2. 3)
Vee Supply Voltage with
Respect to Ground ..... ; .... -, 2.0V to + 7.0V(2)
Output Short Circuit Current. ............ 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Operating temperature is for extended temperature product as defined by this specification.
3. Minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for
periods less than 20 ns.
.
4. Maximum DC voltage on Agor Vpp may overshoot to + 14.0V for periods less than 20 ns.
5. Output shorted for no more than one second. No more than one output shorted at a time.
6. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
7. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for
testing characteristics.
OPERATING CONDITIONS
Symbol
Limits
Parameter
Unit
Min
Max
0
70
·C
TA
Operating Temperature(1)
TA
Operating Temperature(2)
-40
+85
·C
Vee
Vee Supply Voltage (10%)(6)
4.50
5.50
V
Vee
Vee Supply Voltage (5%)(7)
4.75
5.25
V
DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Commercial Products
Symbol
Parameter
Limits
Notes
Min
III
Input Leakage Current
1
ILO
Output Leakage Current
1
-
.5-14
Typ(4)
Unit
Test Conditions
Max
±1.0
/LA
Vee = Vee Max
VIN = VeeorVss
±10
/LA
Vee = Vee Max
VOUT = Vee or Vss
I
28F020
DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Commercial
Products (Continued)
Symbol
Parameter
Notes
Limits
Min Typ(4)
Unit
Test Conditions
Max
lees
Vee Standby Current
1
0.3
1.0
mA Vee = Vee Max
CE# = VIH
lee1
Vee Active Read Current
1
10
30
mA Vee = Vee Max, CE# = VIL
f = 6 MHz, lOUT = 0 mA
lee2
Vee Programming Current
1,2
1.0
10
mA Programming in Progress
lee3
Vee Erase Current
1,.2
5.0
15
mA Erasure in Progress
lee4
Vee Program Verify Current
1,2
5.0
15
mA Vpp = VPPH,
Program Verify in Progress
lee5
Vee Erase Verify Current
1,2
5.0
15
mA Vpp = VpPH,
Erase Verify in Progress
IpPS
Vpp Leakage Current
1
IpP1
Vpp Read Current, ID Current
or Standby Current
1
90
±10
).LA Vpp ~ Vee
200
).LA Vpp
IpP2
Vpp Programming Current
1,2
8
> Vee
Vpp ~ Vee
±10
30
mA Vpp = VPPH
Programming in Progress
IpP3
Vpp Erase Current
1,2
10
30
mA Vpp = VPPH
IpP4
Vpp Program Verify Current
1,2
2.0
5.0
mA Vpp = VpPH,
Program Verify in Progress
IpP5
Vpp Erase Verify Current
1,2
2.0
5.0
mA Vpp = VPPH,
Erase Verify in Progress
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage
VID
Ag Intelligent Identifer
Voltage
liD
Ag Intelligent Identifier
Current
VPPL
Vpp during Read-Only
Operations
0.00
6.5
V
VpPH
Vpp during Read/Write
Operations
11.40
12.60
V
VLKO
Vee Erase/Write Lock Voltage
I
0.8
Vee
+ 0.5
0.45
2.4
11.50
1,2
13.00
90
2.5
200
V
V
V
IOL = 5.8mA
Vee = Vee Min
V
IOH = -2.5 mA
Vee = Vee Min
V
).LA Ag = VID
NOTE: Erase/Program are
Inhibited when Vpp = VpPL
V
5-15
28F020
DC CHARACTERISTIC8-CMOS COMPATIBLE-Commercial Products
Symbol
Parameter
Notes
,
Limits
Min
Typ(4)
Max
Test Conditions
Unit
III
Input Leakage Current
1
±1.0
p.A Vee = Vee Max
VIN = VeeorVss
ILO
Output Leakage Current
1
±10
p.A Vee = Vee Max
VOUT = Vee or Vss
lees
Vee Standby Current .
1
50
100
p.A Vee = Vee Max
CE# = Vee ±0.2V
lee1
Vee Active Read Current
1
10
30
rnA Vee = Vee MaX, CE# = VIL
f = 6 MHz, lOUT = 0 rnA
lee2
Vee Programming Current
1,2
1.0
10
rnA Programming in Progress
ICC3
Vee Erase Current
1,2
5.0
15
rnA Erasure in Progress
lee4
Vee Program Verify Current
1,2
5.0
15
rnA Vpp = VPPH, Program
Verify in Progress
lee5
Vee Erase Verify
Current
1,2
5.0
15
rnA Vpp = VPPH,
Erase Verify in Progress
s:: Vee
> Vee
Vpp s:: Vee
±10
p.A Vpp
200
p.A Vpp
Ipps
Vpp Leakage Current
1
IpP1
Vpp Read Current,
10 Current or
Standby Current·
1
IpP2
Vpp Programming
Current
1,2
8
30
rnA Vpp = VPPH,
Programming in Progress
IpP3
Vpp Erase Current
1,2
10
30
rnA Vpp = VPPH,
Erasure in Progress
IpP4
Vpp Program Verify
Current
1,2
2.0
5.0
rnA Vpp = VPPH,
Program Verify in Progress
IpP5
Vpp Erase Verify
Current
1,2
2.0
5.0
rnA Vpp = VPPH,
Erase Verify in Progress
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
0.7 Vee
VOL
Output LowVoltage
90
±10
0.8
Vee
I
+ 0.5
0.45
VOH1
V
V
V
0.85 Vee
Output High Voltage
V
VOH2
IOH = -2.5 rnA,
Vee = Vee Min
IOH = -100 p.A,
Vee = Vee Min
Vee - 0.4
VID
A91ntelligent Identifer
Voltage
11.50
liD
A9 Intelligent Identifier
Current
13.00
VPPL
Vpp during Read-Only
Operations
0.00
6.5
V
VpPH
V pp during Read/Write
11.40
12.60
V
90
1,2
IOL = 5.8 rnA
Vee = Vee Min
200
V
p.A A9
=
VID
NOTE: Erase/Programs are
Inhibited when Vpp = VPPL
Operations
VLKO
5-16
Vee Erase/Write Lock
Voltage
2.5
V
I
28F020
DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Extended Temperature
Products
Symbol
Parameter
Notes
Limits
Min Typ(4)
Unit
Test Conditions
Max
III
Input Leakage Current
1
±1.0
p.A Vee = Vee Max
VIN = Vee or Vss
ILO
Output Leakage Current
1
±10
p.A Vee = Vee Max
VOUT = Vee or Vss
lees
Vee Standby Current
1
0.3
1.0
mA Vee = Vee Max
CE# = VIH
leel
Vee Active Read Current
1
10
30
mA Vee = Vee Max, CE# = VIL
f = 6 MHz, lOUT = 0 mA
lee2
Vee Programming Current
1,2
1.0
30
mA Programming in Progress
lee3
Vee Erase Current
1,2
5.0
30
mA Erasure in Progress
lee4
Vee Program Verify Current
1,2
5.0
30
mA Vpp = VPPH,
Program Verify in Progress
lee5
Vee Erase Verify Current
1,2
5.0
30
mA Vpp = VPPH,
Erase Verify in Progress,
Ipps
Vpp Leakage Current
1
IpPl
Vpp Read Current, 10 Current
or Standby Current
1
90
±10
p.A Vpp:O;: Vee
200
p.A Vpp> Vee
±10
Vpp:O;: Vee
30
mA Vpp = VPPH
Programming in Progress
10
30
mA Vpp
2.0
5.0
mA Vpp = VPPH,
Program Verify in Progress
5.0
mA Vpp = VPPH,
Erase Verify in Progress
IpP2
Vpp Programming Current
1,2
IpP3
Vpp Erase Current
1,2
IpP4
Vpp Program Verify Current
1,2
IpP5
Vpp Erase Verify Current
1,2
2.0
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOHl
Output High Voltage
VID
Ag Intelligent Identifer
Voltage
liD
Ag Intelligent Identifier
Current
VPPL
Vpp during Read-Only
Operations
0.00
6.5
V
VPPH
Vpp during Read/Write
Operations
11.40
12.60
V
VLKO
Vee Erase/Write Lock Voltage
I
8
0.8
Vee
+ 0.5
0.45
2.4
11.50
1,2
13.00
90
2.5
500
=
VPPH
V
V
V
IOL = 5.8 mA
Vee = Vee Min
V
IOH = -2.5 mA
Vee = Vee Min
V
p.A Ag
=
VID
NOTE: Erase/Program are
Inhibited when Vpp = VpPL
V
5-17
28F020
DC CHARACTERISTICS-CMOS COMPATIBLE-Extended Temperature
Products
Symbol
Parameter
Limits
Notes
Min
Typ(4)
Max
Unit
Test Conditions
III
Input Leakage Current
1
± 1.0
IJ-A Vee = Vee Max
VIN = Vee or Vss
ILO
Output Leakage Current
1
±10
IJ-A Vee = Vee Max
VOUT = Vee or Vss
Ices
Vee Standby Current
1
50
100
IJ-A Vee = Vee Max
CE# = Vee ±0.2V
lee1
Vee Active Read Current
1
10
50
mA Vee = Vee Max. CE# = VIL
f = 6 MHz. lOUT = 0 mA
lee2
Vee Programming Current
1.2
1.0
10
mA Programming in Progress
lee3
Vee Erase Current
1.2
5.0
30
mA Erasure in Progress
lec4
Vce Program Verify Current
1.2
5.0
30
mA VPP = VPPH. Program
Verify in Progress
lec5
Vce Erase Verify
Current
1.2
5.0
30
mA VPP = VPPH.
Erase Verify in Progress
Ipps
VPP Leakage Current
1
IpP1
VPP Read Current.
ID Curre(lt or
Standby Current
1
IpP2
VPP Programming
Current
1.2
8
30
mA Vpp= VpPH.
Programming in Progress
IpP3
VPP Erase Current
1.2
10
30
mA VPP = VpPH.
Erasure in Progress
IpP4
VPP Program Verify
Current
1.2
2.0
5.0
mA VPP = VPPH.
Program Verify in Progress
IpP5
VPP Erase Verify
Current
1.2
2.0
5.0
mA VPP = VPPH.
Erase Verify in Progress
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
90
-0.5
±10
IJ-A VPP::;; Vee
200
IJ-A Vpp> Vcc
±10
VPP::;; Vcc
0.8
Vec
0.7Vce
+ 0.5
0.45
V
V
V
,
VOH1
0.85Vce
Output High Voltage
V
VOH2
VID
Ag Intelligent Identifer
Voltage
110
Ag Intelligent Identifier
Current
VpPL
VPP during Read-Only
Operations
0.00
6.5
V
VPPH
VPP during Read/Write
Operations
11.40
12.60
V
VLKO
Vee Erase/Write Lock
Voltage
2.5
5-18
IOH = - 2.5 mAo
Vee = Vee Min
IOH = -100 IJ-A.
Vee = Vce Min
Vee - 0.4
11.50
13.00
90
1.2
IOL = 5.8mA
Vee = Vce Min
500
V
IJ-A Ag = VIO
NOTE: Erase/Programs are
Inhibited when VPP = VPPL
V
I
28F020
CAPACITANCE T A
Symbol
=
25°C, f
=
1.0 MHz
Parameter
Limits
Notes
Min
Unit
Conditions
Max
CIN
Address/Control Capacitance
3
8
pF
VIN = OV
COUT
Output Capacitance
3
12
pF
VOUT = OV
NOTES for DC Characteristics and Capacitance:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T = 25°C. These currents
are valid for all product versions (packages and speeds).
2. Not 100% tested: Characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots.
TESTING INPUT/OUTPUT WAVEFORM(1)
HIGH SPEED AC TESTING INPUT/OUTPUT
WAVEFORMS(2)
2.0
OUTPUT
0.6
::: -IN-P-U-T-,""'.5X-TEST
~OINTS-X;'5
OUTPUT
290245-21
AC test inputs are driven at VOH (2.4 Vnu for a Logic
"1" .and VOL (0.45 Vnu for a Logic "0". Input timing
begins at VIH (2.0 Vnu and VIL (0.8 Vnu. Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) ,;:10 ns.
.
AC TESTING LOAD CIRCUIT(1)
290245-22
AC test inputs are driven at 3.0V for a Logic "1" and
O.OV for a Logic "0". Input timing begins, and output
timing ends, at 1.5V. Input rise and fall times (10% to
90%) ,;:10 ns.
HIGH SPEED AC TESTING LOAD CIRCUIT(2)
-~~
-
1.3V
1.3V
~ ..
DEVICE
UNDER
TEST
lN914
Rt.
t----+---o OUT
DEVICE
UNDER
TEST
Rt.
t----+---o OUT
290245-23
CL = 100 pF
CL includes Jig Capacitance
RL = 3.3 kD.
lN914
290245-24
CL = 30 pF
CL includes Jig Capacitance
RL = 3.3 kD.
AC TEST CONDITIONS(1)
HIGH SPEED AC TEST CONDITIONS(2)
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................... 0.45 and 2.4
Input Pulse Levels .................... 0.0 and 3.0
Input Timing Reference Level .......... 0.8 and 2.0
Input Timing Reference Level ................. 1.5
Output Timing Reference Level ......... 0.8 and 2.0
Output Timing Reference Level ................ 1.5
Capacitive LoadCI ........................ 100 pF
Capacitive Load CI ........................ 30 pF
NOTES:
1. Testing characteristics for 28F020-70 in standard configuration, and 28F020-90 and 28F020-150.
2. Testing characteristics for 28F020-70 in high speed configuration.
I
5-19
01
N
o
N
AC CHARACTERISTICS-Read Only Operations-Commercial and Extended Temperature Products
Versions
Vee+ 5%
28F020-70(4)
Vee +10%
Symbol
Characteristics
tAVAV/tRC·
Read Cycle Time
tELQV/tCE
Chip Enable
Access Time
Notes
CD
;;g
Min
Max
70
N
28F020-70(5)
28F020-90(5)
28F020-150(5)
Min
Min
Min
Max
80
Max
90
70
80
o
Unit
Max
150
ns
90
120
ns
tAVQv/tACC
Address AcCess Time
70
80
90
120
ns
tGLQV/tOE
Output Enable
Access Time
28
30
35
50
ns
tELQXltLZ
Chip Enable to
Output in Low Z
2,3
tEHQZ
Chip Disable to
Output in High Z
2
tGLQxltOLZ
Output Enable to
Output in Low Z
2,3
tGHQZ/tDF
Output Disable to
Output in High Z
2
tOH
Output Hold from
Address, CE #, or
OE# Change
1,2
tWHGL
Write Recovery Time
before Read
0
0
35
ns
40
0
0
30
45
55
0
30
0
0
6
6
6
---
ns
30
0
ns
30
ns
ns
6
fJ-s
. -
NOTES:
1. Whichever occurs first.
2. Sampled, not 100% tested.
3. Guaranteed by design.
4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
-
-::J
c[
@
-
--
::J
c(
@
Vee POWER-UP
STANDBY
DEVICE AND
ADDRESS SELECTION
ADDRESSES
Vee POWER-DOWN
ADDRESS STABLE
'AVAV
"'1'1
.
STANDBY
DATA VALID
OUTPUTS ENABLED
(;,e)
IE
c
(1)
eE# (E#)
;-I
~
~
(1)
0'
OE# (G#)
3
1/1
.
'WHGL
0'
J3
-ti------:---i
WE# (w#)
(1)
'oLOV ('0,)
III
Co
"LOV
o
'oLOX
'C
(1)
~
ci"
('oLZ)
('e,)
----I
'oH
"'ax ('ez)
HIGH Z
HIGH Z
DATA (DO)
:::I
1/1
~J
Vee
L
VALID OUTPUT
'Avav ('Ace)
~
OV
290245-11
N
01)
01
~
."
o
N
o
t11
N
I\)
Versions
Vee +5%
Symbol
Characteristics
Notes
C
28F020-70(5)
Min
Max
Min
Max
28F020-90(5)
Min
tAVAV/tWC
Write Cycle Time
70
80
90
tAVWL/tAS
Address Set-Up Time
0
0
tWLAX/tAH
Address Hold Time
40
40
Data Set-Up Time
Max
28F020-150(5)
Min
Unit
Max
150
ns
' 0
0
ns
40
40
ns
55
6
tOVWH/toS
"TI
C
I\)
28F020-70{2,4)
Vee +10%
40
40
40
40
ns
55
6
tWHOX/tOH
Data Hold Time
10
10
10
10
ns
tWHGL
Write Recovery Time
before Read
6
6
6
6
/-,S
tGHWL
Read Recovery Time
before Write
0
0
0
0
ns
tELWL/
tcs
Chip Enable Set-Up
Time before Write
15
15
15
15
ns
tWHEH/
tCH
Chip Enable Hold Time
0
0
0
0
ns
tWLWH/twP
Write Pulse Width
40
40
40
60
2
ns
55
6
-
I\)
Q)
AC CHARACTERISTICS-Write/Erase/Program Only Operations(1)-Commercial and Extended Temperature
Products
20
20
20
20
ns
3
10
10
10
10
/-,S
Duration of Erase
Operation
3
9.5
9.5
9.5
9.5
ms
Vpp Set-Up Time to
Chip Enable Low
2
1
1
1
1
/-,S
tWHWL/
tWPH
Write Pulse Width High
tWHWH1
Duration of Programming
Operation
tWHWH2
tVPEL
NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification.
4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
6. Minimum Specification for Extended Temperature product.
_.
€:
@
28F020
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Limits
Notes
Min
Unit
Typ
Max
Chip Erase Time
1,3,4
2
30
Sec
Chip Program Time
1,2,4
4
25
Sec
NOTES:
1. "Typicals" are not guaranteed, but based on a limited number of samples from production lots. Data taken at 25'C, 12.0V
Vpp at 0 cycles.
•
2. Minimum byte programming time excluding system overhead is 16 fLsec (10 fLsec program + 6 fLsec write recovery),
while maximum is 400 fLsec/byte (16 fLsec x 25 loops allowed by algorithm). Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.
3. Excludes OOH Programming prior to Erasure.
4. Excludes System-Level Overhead.
5. Refer to RR-60, 69 "ETOX Flash Memory Reliability Data Summaries" for typical cycling data and failure rate calculations.
I
5-23
28F020
99.9
V
L
99
C
u
m
90
80
(
P
0
/
I
/
70
b
a
b
I
I
I
t
Y
~
60
50
/
40
I
30
I
/,
20
,
,
IL
,,
,(
, ,
,(,'/
V
95
~ ,,"
/
/'/
,
./",
,,
V ,,,
, -' , ,
;' , ,
/
,
" ,,
,,
",,, ,
I
I
10
"
5
0.1
4
5
6
7
8
9
10
20
30
40
Chip Program TIme (Sec)
- - - 12V: 10kc: 23C
- - - - - - - 11.4v: 10kc: 70C
- - - - 12V; 100kc; 23C
290245-12
Figure 8. 28F020 Typical Programming Capability
5-24
I
intel®
28F020
15
14
• 13
,/
12
V
C
h
11
P
I
P
0
10
9
T
I
m
e
9
/"
8
S
e
c
7
i
6
I
.--
IV
--
V. . .
, "
,
,.1
,,
5
4
o
10
20
30
40
..- "
50
....
.- ......
,
,,-
,
...
/
It'/:
r
a
m
/
v
,
,
,,
,, ,
,
-
V
/
I
V
/
/
./
"
60
,
,,
,, ,
,
/
70
80
90
100
110
120
130
Temp (C)
- - - 1k Cycles
- ••••• -10k Cycles
- - - - lOOk Cycles
290245-13
Figure 9. 28F020 Typical Program Time at 12V
I
5-25
28F020
99.9
/,/
99
90
C
u
m
p
0
b
J
80
70
I
a
50
J
J
J
40
t
Y
30
II
J
't"
I,'
, V
' ,1
/ ,, "v
"
, ,
/ ,/ I
60
b
/
" ./
,',"1'
V
, ,,
,
,
II
,
V , , ,I
;J
95
V"
,. l
,'1'
"j
' l
" 1
/ ," ,I
20
j:, /
Ii
10
/ ,... ,!
II !I
5
1/
if
,,
I:
0.1
1
2
3
4
5
6
7 8 910
20
30
40
50
Chip Erose Time (Sec)
- - - - 12V; 10kc; 23C
.-----. 12V; 100kc; 23C
- - - - 11.4V; 10kc; OC
290245-14
NOTE:
Does not include Pre-Erase Program.
Figure 10. 28F020 Typical Erase Capability
5-26
I
intel®
28F020
5.2
5.0
4.8
1\
\
\,
4.S
\.
4.4
C
\
4.2
'\
h
1
P
4.0
E
r
3.8
a
s
e
i
S
e
c
",,
,,
3.S
T
m
e
,,
3.4
,
t\.
"'-
3.2
3.0
,,
\.
,
,,
""'~
,,
,
...
...
'"
"" '"
"
r--....
2.8
2.6
2.4
,
.. . .
1',
"
1"- ..
. .
..
"""'- .. .,
. . .. .
~ r-.....
...
............
"
. .. .. ..
............
2.2
2.0
o
10
20
30
40
50
SO
70
80
90
100
110
~
.-
--r120
130
Temp (C)
- - - 1k Cycles
.- ••••• 10k Cycles
- - - - lOOk Cycles
290245-15
NOTE:
Does not include Pre-Erase Program.
Figure 11. 28F020 Typical Erase Time at 12.0V
I
5-27
c.n
iii)
ro
Oil
(Xl
SET-UP PROGRAM
COMMAND
Vee POWER-UP 8<
STANDBY
PROGRAM COMMAND
LATCH ADDRESS 8< DATA
PROGRAMMING
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
"'o~"
STANDBY!
Vee POWER-DOWN
ADDRESSES
~I
CE# (E#)
..,C
...
CD
!"
J>
0
:EI
III
OE# (G#)
<
CD
....
0..,
3
I/)
....
~I
WE# (w#)
..,'V
0
IQ
iil
3
3
:i"
IQ
DATA (DQ)
0
"..iil
CD
O·
5.0V
:I
I/)
Vee
OV
-'
tVPEl
""'
Vpp
VpPl
-
~
290245-16
--
:l
c[
@
-
SET -UP ERASE
COMMAND
Vee POWER-UP &
STANDBY
ERASE COMMAND
ERASING
ERASE
VERIFY
COMMAND
_"
ERASE
VERIFICATION
STANDBY I
VCC POWER-DOWN
ri
J1
ADDRESSES
c(
@J
CE# (E#)
."
ca'
e::
.....
CD
....
~
~I
OE# (G#)
::E
III
<
CD
0
.....
3
UJI
WE# (w#)
0
.....
In
.....
III
UJ
CD
0
'gl
..
DATA (DO)
.....
III
0'
::::I
UJ
5.0V
Vee
OV
t VPEL
1--0
12.0V
Vpp
VpPL
(11
r\,
(0
---./
"---
290245-17
I\)
CO
"11
0
I\)
0
(J1
c:.,
AC CHARACTERISTICS-Alternate CE # Controlled Writes-Commercial and Extended Temperature Products
o
Versions
Vee +5%
Characteristics
Notes
"II
28F020-70(2,4)
Vee +10%
Symbol
Min
Max
N
28F020-70(5)
28F020-90(5)
28F020-150(5)
Min
Min
Min
Max
Max
tAVAV
70
80
90
150
ns
tAVEL
Address Set-Up Time
0
0
0
0
ns
tELAX
Address Hold Time
50
50
50
55
6
60
ns
40
40
Data Hold Time
10
10
10
10
ns
tEHGL
Write Recovery Time
before Read
6
6
6
6
/Ls
tGHWL
Read Recovery Time
before Write
0
0
0
0
ns
tWLEL
Write Enable Set-Up Time
before Chip Enable
0
0
0
0
ns
tEHWH
Write Enable Hold Time
0
0
0
0
ns
tELEH
Write Pulse Width
50
50
50
70
ns
tEHEL
Write Pulse Width High
20
20
20
20
ns
tEHEH1
Duration of Programming
Operation
3
10
10
10
10
/Ls
tEHEH2
Duration of Erase Operation
3
9.5
9.5
9.5
9.5
ms
Vpp Set-Up Time to
Chip Enable Low
2
1
1
1
1
/Ls
Data Set-Up Time
tEHDX
6
2
tVPEL
40
45
ns
50
6
-
Max
C)
Unit
Write Cycle Time
tDvEH
N
C»
C)
60
-
-
NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification.
4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteritics.
5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
6. Minimum specification for Extended Temperature product.
_.
c(
@
-
_.
»z
;:;:0
!!l ....
:::1m
1»"
~
~I
g>
'TI
~.
c
Vee POWER-UP &
STANDBY
SET -UP PROGRAM
COMMAND
PROGRAM COMMAND
LATCH ADDRESS & OAT A
PROGRAMMING
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
STANDBY I
Vee POWER-DOWN
ADDRESSES
€:
@l
~CD
c.
...iil ~
::!
WE# (E#)
~
~
..it
::J
~.
:::I
I»
~ i3
.@l
"C
~ '<
f
a-
3
!II
i!!l-
OE# (G#)
CD
i3' m
..
CE# (w#)
i3' o·
:::I
'1J
a
fI'
CI:I
~
DATA (DO)
3
~.
o
'0
CD
a0'
::J
!II
5.0V
Vee
OV
12.0V
Vpp
~
VpPL
U1
~
290245-18
CCI
."
Q
~
Q
28F020
ORDERING INFORMATION
JL
TEMPERATURE RANGE
T = EXTENDED (-<10°C TO +55 0 C)
BLANK
COMMERCIAL (OOC TO HOOC)
=
~
L
PACKAGE
'
P = 32-PIN PLASTIC DIP
N
32-LEAD PLCC
E
STANDARD 32-LEAD TSOP
F = REVERSE 32-LEAD TSOP
=
=
I
LPROLIFERATION CODE
ACCESS SPEED (no)
,
80 ns
90ns
150no
200ns
290245-19
VALID COMBINATIONS:
P28F020-70
P28F020-90
P28F020-150
N28F020-70
N28F020-90
N28F020-150
TN28F020-90
E28F020-70
E28F020-90
E28F020-150
F28F020-70
F28F020-90
F28F020-150
TE28F020-90
TF28F020-90
ADDITIONAL INFORMATION
REVISION HISTORY
Order
Number
294005
ER-20, -
"ETOX Flash Memory
Technology"
ER-24,
"Intel Flash Memory"
294008
ER-2B,
"ETOX III Flash Memory
Technology"
294012
RR-60,
"ETOX Flash Memory
Reliability Data Summary"
293002
AP-316,
"Using Flash Memory for InSystem Reprogrammable
Nonvolatile Storage"
292046
AP-325
"Guide to Flash Memory
Reprogramming"
292059
5-32
Number
Description
-004
Removed Preliminary
Classification_ Clarified AC and DC
test conditions. Added "dimple" to F
TSOP package. Corrected
serpentine layout.
.-005
Added -BOV05, -90 ns speed grades.
Added extended temperature
devices. Corrected AC Waveforms.
-006
Added -70 ns speed.
Deleted -80V05 speed.
Revised symbols, I.e., CE, OE, etc.
to CE#, OE#, etc.
I
28F010
1024K (128K x 8) CMOS FLASH MEMORY
., Flash Electrical Chip-Erase
- 1 Second Typical Chip-Erase
•
Quick Pulse Programming Algorithm
-10 JJ-s Typical Byte-Program
- 2 Second Chip-Program
•
•
•
100,000 Erase/Program Cycles
II 12.0V ±5% Vpp
•
High-Performance Read
- 65 ns Maximum Access Time
CMOS Low Power Consumption
- 10 mA Typical Active Current
- 50 JJ-A Typical Standby Current
- 0 Watts Data Retention Power
•
•-
Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
Noise Immunity Features
± 10% Vee Tolerance
- Maximum Latch-Up Immunity
through EPI Processing
•
ETOX Nonvolatile Flash Technology
- EPROM-Compatible Process Base
- High-Volume Manufacturing
Experience
•
JEDEC-Standard Pinouts
- 32-Pin' Plastic Dip
- 32-Lead PLCC
- 32-Lead TSOP
Integrated Program/Erase Stop Timer
(See Packaging Spec" Order # 231369)
~
Extended Temperature Options
Intel's 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F010 increases
memory flexibility, while contributing to time and cost savings.
The 28F010 is a 1024 kilobit nonvolatile memory organized as 131,072 bytes of 8 bits. Intel's 28F010 is
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel's ETOX (EPROM Tunnel Oxide) process
technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to
extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V Vpp supply, the 28F010 performs
100,000 erase and program cycles well within the time limits of the Quick Pulse Programming and Quick Erase
algorithms.
Intel's 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption"and immunity to noise. Its 65 nanosecond access time provides no-WAlT-state performance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 p.A translates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 rnA
.
on address and data pins, from -1V to Vee + 1V.
With Intel's ETOX process base, the 28F010 levers years of EPROM experience to yield the highest levels of
quality, reliability, and cost-effectiveness.
November 1994
Order Number: 290207-009
5-33
28F010
DQO-D~
c-s-
"IERASE VOLTAGE
SWITCH
I
p
WE'
----.
CEO
, OE'
r
STATE
CONTROL
COMMAND
REGISTER
INTEGRATED
STOP TIMER
i I
11
I
J INPUT/OUTPUT
BUffERS
'"
TO ARRAY
SOURCE
'--
,.
-
A
~[PGM
VOLTAGE
SWITCH
CHIP ENABLE
OUTPUT ENABLE
LOGIC
...
An-A 16
"v
3'"
'"'"w
""«'"
DATA
LATCH
~
Y-DECODER
STB
7STB
~
Y-GATING
~
•
X-DECODER
•
•
•
--+
1,048,576 BIT
CELL MATRIX
:+290207-1
Figure 1. 28F010 Block Diagram
Table 1. Pin Description
Symbol
Name and Function
Type
Ao-A16
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
DOo-DO?
INPUT/OUTPUT
DATA INPUTIOUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled. Data is internally latched during a write cycle.
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers,
decoders and sense amplifiers. CE # is active low; CE # high
deselects the memory device and reduces power consumption to
standby levels.
OE#
INPUT
OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WE # pulse.
Note: With Vpp ::;; 6.5V, memory contents cannot be altered.
Vpp
ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.
Vee
DEVICE POWER SUPPLY (5V
Vss
GROUND
NC
NO INTERNAL CONNECTION to device. Pin may be driven or left
floating.
5-34
± 10%)
I
intel®
28F010
28F010
vpp
vee
A'6
WE#
.A'5
NC
A'2
A'4
A7
A7
A,3
As
A6
A8
A5
N
A5
Ag
A4
A4
A"
OE#
A3
A3
A2
Ao
D~
DOo
D06
DO,
D05
D02
DQ4
Vss
DQ3
ID
c..
~
U
0
A'4
A'3
N28FO'O
32 - LEAD PLCC
0.450" x 0.550"
TOP VIEW
A2
A,o
CE#
A,
II)
«<>c...>03,: uz
27
A8
26
Ag
24
A"
OE#
A,
A,o
Ao
CE#
DOo
DQ7
ggN>~gg"gglD
290207-3
290207-2
DE-
0
A"
As
A8
"'"',,
3'
A"
CEO
0,
D.
STANDARD PINOUT
E28FO 10
32-LEAD TSOP
0.31" X 0.72"
TOP VIEW
NC
WEO
Vee
Vpp
"'.
"'5
"'2
05
0,
0,
Vss
O2
11
2'
""
A.
As
A,
Do
Ao
A,
A2
A,
290207-17
DE'
"'0
~V
0
CEo
0,
Os
05
0,
0,
Vss
O2
'0
0,
11
Do
Ao
'2
13
14
A,
A2
A3
REVERSE PINOUT
F28F010
32-LEAD TSOP
0.31" X 0.72"
TOP VIEW
32
A"
"
A8
'0
2"
28
27
As
"'"',,
NC
WE'
Vee
.Vpp
"'.
"'5
2'
A'2
""As
'5
'8
As
16
17
A,
290207-16
Figure 2. 28F010 Pin Configurations
I
5-35
28F010
APPLICATIONS
The 28F010 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These features make the 28F010 an innovative alternative to
disk, EEPROM, and battery-backed static RAM.
Where periodic updates of code and data-tables are
required, the 28F010's reprogrammability and nonvolatility make it the obvious and ideal replacement
for EPROM.
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption - a consideration particularly important in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and application code. With updatable code, system manufacturers can easily accommodate last-minute changes as
revisions are made.
In diskless workstations and terminals, network traffic reduces to a minimum and systems are instanton. Reliability exceeds that of electromechanical
media. Often in these environments, power interruptions force extended re-boot periods for all networked terminals. This mishap is ho longer an issue
if boot code, operating systems, communication protocols and primary applications are flash-resident in
each terminal.
:i
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F010 flash memory offers a solid.
state alternative in a minimal form factor. The
28F010 provides higher performance, lower power
consumption, instant-on capability, and allows an
"execute in place" memory hierarchy for code and
data table reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail.
The need for code updates pervades all phases of a
system's life - from prototyping to system manufacture to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F010 allows incircuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexibility.
5-36
Material and labor costs associated with code
changes increases at higher levels of system integration - the most costly being code updates after
sale. Code "bugs", or the desire to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the removal of EPROM components or entire boards. With
the 28F010, code updates are implemented locally
via an edge-connector, or remotely over a communcation link.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminates the
need· for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost. advantage
over static RAM.
Flash memory's electrical chip erasure, byte programmability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a "blank slate" in
which to log or record data. Data can .be periodically
off-loaded for analysis and the flash memory erased
producing a new "blank slate" ..
A high degree of on-chip feature. integration simplifies memory-to-processor interfacing. Figure 4 depicts two 28F010s tied to the 80C186 system bus.
The 28F010's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mmthickness. With standard and reverse pin configurations, TSOP reduces
the number of board layers and overall volume necessary to layout multiple 28F010s. TSOP is particularly suited for portable equipment and applications
requiring large amounts of flash memory. Figure 3
illustrates the TSOP Serpentine layout.
With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility,
the 28F010 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today's designs.
I
28F010
on nnnnnrumn an am
o
nu,u.ur.~~ln.,..,...mny..u,1[}--r-urIln.Dl. . I.a................~~
II L
I(
,...,
~ II
D
co
......
Vee
±10.0
,0:
Vee
vpp,o: Vee
IpP2
Vpp Programming Current
1,2
8.0
30
mA Vpp = VPPH
Programming in Progress
IpP3
VPP Erase Current
1,2
6.0
30
mA VPP = VpPH
Erasure in Progress
IpP4
VPP Program Verify Current
1,2
2.0
5.0
mA Vpp = VpPH, Program'
Verify in Progress
IpP5
VPP Erase Verify Current
1,2
2.0
5.0
mA VPP = VpPH, Erase
Verify in Progress
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage
VID
Ag Intelligent Identifer Voltage
liD
Ag Intelligent Identifier Current
VPPL
VPP during Read-Only
Operations
0.00
6.5
V
VpPH
VPP during Read/Write
Operations
11.40
12.60
V
VLKO
Vee Erase/Write Lock Voltage
0.8
Vee
+
V
0.5
0.45
2.4
11.50
1,2
13.00
90
V
V
IOL = 5.8 mA
Vee = Vee Min
V
IOH = -2.5 mA
Vee = Vee Min
V
200
p.A Ag
2.5
= VID
NOTE: Erase/Program are
Inhibited when VPP = VPPL
V
DC CHARACTERISTICS-CMOS COMPATIBLE-Commercial Products·
Symbol
Parameter
Limits
Notes
Min
Typical(4)
Unit
Test Conditions
Max
III
Input Leakage Current
1
±1.0
p.A
Vee = Vee Max
VIN = Vee or Vss
ILO
Output Leakage Current
1
±10
p.A
Vee = Vee Max
VOUT = Vee or Vss
lees
Vee Standby Current
1
50
100
p.A
Vee = Vee Max
CE# = Vee ±0.2V
leel
Vee Active Read Current
1
10
30
mA
Vee = Vee Max, CE# = VIL
f = 6 MHz, lOUT = 0 mA
I
5-47
28F010'
DC CHARACTERISTIC5-CMOS COMPATIBLE-Commercial Products (Continued)
Symbol
Parameter
Limits
Notes
Min
Unit
Typlcal(4)
Max
Test Conditions
lee2
Vee Programming Current
1.2
1.0
10
mA Programming in Progress
leC3
Vee Erase Current
1.2
5.0
15
mA Erasure in Progress
leC4
Vee Program Verify Current
1.2
5.0
15
mA VPP = VPPH. Program
Verify in Progress
lee5
Vee Erase Verify Current
1.2
5.0
15
mA VPP = VPPH. Erase
Verify in Progress
Ipps
VPP Leakage Current
1
IpP1
VPP Read Current. ID
Current or Standby Current
1
90
±10
"A
Vpp';: Vee
200
p.A
Vpp> Vee
±10
Vpp';: Vee
IpP2
VPP Programming
Current
1.2
8.0
SO
mA VPP = VpPH
Programming in Progress
IpP3
VPP Erase Current
1.2
6.0
SO
mA VPP = VpPH
Erasure in Progress
IpP4
VPP Program Verify
Current
1.2
2.0,
5.0
mA VPP = VPPH. Program
VEirify in Progress
IpP5
VPP Erase Verify
Current
1.2
2.0
5.0
mA VPP = VPPH. Erase
Verify in Progress
VIL
,Input Low Voltage
-0.5
VIH
Input High Voltage
0.7 Vee
VOL
Output Low Voltage
VOH1
+ 0.5
0;45
0.85 Vee
Output High Voltage
V
V
V
V
VID
Ag Intelligent Identifer
Voltage
110
Ag Intelligent Identifier
Current
VPPl
VPP during Read-Only
Operations
YPPH
VPP during Read/Write
Operations
VlKO
Vee Erase/Write Lock
Voltage
1S.00
V
200
p.A
0.00
6.5
V
11;40
12.60
V
11.50
90
1.2
2.5
IOl = 5.8mA
Vee = Vee Min
IOH = -2.5 mAo Vee = Vee Min
IOH = -100 p.A. Vee = Vee Min
Vee - 0.4
VOH2
5-48
0.8
Vee
Ag =VID
NOTE: Erase/Programs are
Inhibited when VPP = VPPl
V
,
,
I
28F010
DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Extended Temperature
Products
Symbol
Parameter
Limits
Notes
Min Typical(4)
Unit
Test Conditions
Max
III
Input Leakage Current
1
±1.0
/-LA Vee = Vee Max
VIN = Vee or Vss
ILO
Output Leakage Current
1
±10
/-LA Vee = Vee Max
VOUT = Vee or Vss
Ices
Vee Standby Current
1
0.3
1.0
mA Vee = Vee Max
CE# = VIH
lee1
Vee Active Read Current
1
10
30
mA Vee = Vee Max, CE# = VIL
f = 6 MHz, lOUT = 0 mA
lee2
Vee Programming Current
1,2
1.0
30
mA Programming in Progress
lee3
Vee Erase Current
1,2
5.0
30
mA Erasure in Progress
lee4
Vee Program Verify Current
1,2
5.0
30
mA Vpp = VpPH, Program
Verify in Progress
lee5
Vee Erase Verify Current
1,2
5.0
30
mA Vpp = VPPH, Erase
Verify in Progress
IpPS
Vpp Leakage Current
1
IpP1
Vpp Read Current
or Standby Current
1
90
±10
/-LA Vpp ~ Vee
200
/-LA Vpp> Vee
Vpp ~ Vee
±10.0
IpP2
Vpp Programming Current
1,2
8.0
30
mA Vpp = VPPH
Programming in Progress
IpP3
Vpp Erase Current
1,2
6.0
30
mA Vpp = VpPH
Erasure in Progress
IpP4
Vpp Program Verify Current
1,2
2.0
5.0
mA Vpp = VPPH, Program
Verify in Progress
IpP5
Vpp Erase Verify Current
1,2
2.0
5.0
mA Vpp = VpPH, Erase
Verify in Progress
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage
VID
Ag Intelligent Identifer Voltage
110
Ag Intelligent Identifier Current
VPPL
Vpp during Read-Only
Operations
0.00
6.5
V
VPPH
Vpp during Read/Write
Operations
11.40
12.60
V
VLKO
Vee Erase/Write Lock Voltage
I
0.8
Vee
+ 0.5
0.45
2.4
11.50
1,2
13.00
90
2.5
500
V
V
V
IOL = 5.8mA
Vee = Vee Min
V
IOH = -2.5mA
Vee = Vee Min
V
/-LA Ag
=
VIO
NOTE: Erase/Program are
Inhibited when Vpp = VPPL
V
5-49
28F010
DC CHARACTERISTICS-CMOS COMPATIBLE-Extended Temperature
Products
Symbol
Parameter
Limits
Notes
Min
Unit
Typlcal(4)
Test Conditions
Max
III
Input Leakage
Current
1
±1.0
,...A Vee = Vee Max
VIN = VeeorVss
ILO
Output Leakage
Current
1
±10
,...A Vee = Vee Max
VOUT = Vee or Vss
Ices
Vee Standby
Current
1
50
100
,...A Vee = Vee Max
CE# = Vee ±0.2V
leel
Vee Active Read
Current
1
10
30
mA Vee = Vee Max, CE# = VIL
f = 10 MHz, lOUT = 0 mA
lee2
Vee Programming
Current
1,2
1.0
10
mA Programming in Progress
leca
Vee Erase Current
1,2
5.0
30
mA Erasure in Progress
leC4
Vee Program Verify
Current
1,2
5.0.
30
mA VPP = VpPH, Program
Verify in Progress
lee5
Vee Erase Verify
Current
1,2
5.0
30
mA VPP = VPPH, Erase
Verify in Progress
Ipps
VPP Leakage Current
1
IpPl
VPP Read Current,
10 Current or
Standby Current
1
IpP2
VPP Programming
Current
1,2
8.0
30
mA Vpp = VpPH
Programming in Progress
IpP3
VPP Erase Current
1,2
6.0
30
mA VPP = VPPH
Erasure in Progress
IpP4
VPP Program Verify
Current
1,2
2.0
5.0
mA VPP = VPPH, Program
Verify in Progress
IpP5
VPP Erase Verify
Current
1,2
2.0
5.0
mA VPP = VPPH, Erase
Verify in Progress
90
,...A VPP
200
p.A Vpp> Vee
±10
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
0.7 Vee
VOL
Output Low Voltage
.0.8
Vee
+ 0.5
0.45
VPP
V
VIO
Ag'lntelligent Identifer
Voltage
110
Ag Intelligent Identifier
Current
5-50
V
Vee - 0.4
VOH2
13.00
11.50
1,2
90
500
Vee
V
0.85 Vee
Output High Voltage
s:
Vee
V
'I
VOHl
s:
±10
IOL = 5.8mA
Vee = Vee Min
IOH = - 2.5 mA,
Vee = Vee Min
IOH = -100,...A;
Vee = Vee Min
V
,...A Ag
=
VIO
I
28F010
DC CHARACTERISTICS-CMOS COMPATIBLE-Extended Temperature
Products (Continued)
Symbol
Parameter
,
Limits
Notes
Min
Typical(4)
Unit
Test Conditions
NOTE: Erase/Programs are
Inhibited when Vpp = VPPL
Max
VPPL
Vpp during Read-Only
Operations
0.00
6.5
V
VPPH
Vpp during Read/Write
Operations
11.40
12.60
V
VLKO
Vcc Erase/Write Lock
Voltage
2.5
CAPACITANCE TA
Symbol
=
25 C, f
Q
=
V
1.0 MHz
Parameter
Limits
Notes
Min
Unit
=
CIN
Address/Control Capacitance
3
8
pF
VIN
COUT
Output Capacitance
3
12
pF
VOUT
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vee = 5.0V, Vpp = 12.0V, T
are valid for all product versions (packages and speeds).
2. Not 100% tested: characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots.
I
Conditions
Max
OV
=
OV
= 25°C. These currents
5-51
28F010
HIGH SPEED AC TESTING INPUT/OUTPUT
WAVEFORM(2)
AC TESTING INPUT/OUTPUT
WAVEFORM(1)
X ~:~> ptf~is
<
~
VI--IN-P-U""'T
0.45
2.0 OUTPUT
0.8
:::--IN-P-U""'T~.5 - TES~:POINTS - ~.5
290207-8
290207-7
AC test inputs are driven at VOH (2.4 VnLl for a Logic
"1" and VOL (0.45 VnLl for a Logic "0". Input timing
begins at VIH (2.0 VnLl and VIL (0.8 VnLl. Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) <10 ns.
AC test inputs are driven at 3.0V for a Logic "1" and
O.OV for a Logic "0". Input timing begins, and output
timing ends, at 1.5V. Input rise and fall times (10% to
90%) <10 ns.
HIGH SPEED AC TESTING LOAD CIRCUIT(2)
AC TESTING LOAD CIRCUIT(1)
.!:~
.!:~
A II. lN914
,h.1N914
I
DEVICE
UNDER
TEST
OUTPUT
I
,1--+-0 OUT
Cl = 100 pF
CL Includes Jig Capacitance
RL = 3.3 Kn
.I.G.
290207-22
CL = 30pF
CL includes Jig Capacitance
RL = 3.3 Kn
290207-23
AC TEST CONDITIONS(1)
HIGH-SPEED AC TEST CONDITIONS(2)
Input Rise and Fall Times (10% to 90%) .....• 10 ns
Input Pulse Levels ............•..• 0.45V and 2.4V
Input Timing Reference Level •.•.... O.BV and 2.0V
Output Timing Reference Level .•.... O.BV and 2.0V
Capacitive Load .......•................•. 100 pF
Input Rise and Fall Times (10% to 90%) •.•... 10 ns
Input Pulse Levels ........•.......• 0.OVand 3.0V
Input Timing Reference Level .........•...•.• 1.5V
Output Timing Reference Level ....•......... 1.5V
Capacitive Load ..•........................ 30 pF
NOTES:
1. Testing characteristics for 28F010-65 in standard configuration, and 28F010-90, 28F01 0-120, and 28F010-150.
2. Testing characteristics for 28F010-65 in high speed configuration.
5-52
I
-
Vee
Versions
Vee
Symbol
Characteristic
± 5%
± 100/0
Notes
28F010-65(4)
Min
Max
28F010-65(5)
28F010-90(5)
Min
Min
Max
tAvAV/tRC
Read Cycle Time
tELOV/tcE
Chip Enable Access Time
65
70
70
65
Max
28F010-120(5)
Min
Max
Min
Unit
Max
150
120
90
28FO 10-150(5)
ns
c;j~
3C')
"C')
CD::I:
Al~
-:::D
90
120
150
ns
5;~
CDC')
Address Access Time
65
70
90
120
150
ns
... m
Output Enable Access Time
25
28
35
50
55
ns
0.-
tELOXItLZ
Chip Enable to Low Z
ns
0_
tEHOZ
Chip Disable to Output
in HighZ
tGLOXItOLZ
Output Enable to Output
in LowZ
2,3
tGHOZItDF
Output Disable to Output
in HighZ
2
tOH
Output Hold from Address,
CE # , or OE # Change
tWHGL
Write Recovery Time
before Read
0
2
0
35
0
40
45
55
55
0
0
ns
ns
€:
@
-0'"
tAVOVItACC
tGLOVItOE
2,3
_.
O:::D
c~
-C')
(l)j
:::D
CD
II)
30
1,2
-
-
------_
.. -
30
30
0
0
0
6
6
6
--- -
NOTES:
1. Whichever occurs first.
2. Sampled, not 100% tested.
3. Guaranteed by design.
4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
30
35
ns
ns
6
6
I's
0.
o
::::J
-<
~
CD
Al
O·
::::J
h
o
3
3
...oCD
~
II)
::::J
0.
;r
CD
::::J
0.
CD
0.
(11
&.
c.l
N
CC)
.."
....o
o
PI)
0)
Y'
~
;;g
....o
Vce POWER-UP
STANDBY
DEVICE AND
ADDRESS SELECTION
ADDRESSES
OUTPUTS ENABLED
DATA VALID
STANDBY
Vee POWER-DOWN
ADDRESS STABLE
t AvAV (~e)
'TI.
-ijj"
c
CE# (E#)
~
:'"
l;
i
OE# (G#)
3In
0'
...
:D
I_
1 t WHGL 1
WE# (w#)
Z
o
telQV (toE)
a.
I - hQV
tGlQX (toll)
l
a6"
:I
-I
\:lQX
(teE)
-.J
HIGH Z
HIGH Z
DATA (DO)
L
In
5.0V
Vee
OV
j- -
toH
(b)
VALID OUTPUT
t AVQV
(tACC )
\.290207-9
-
--
€:
@
0)10
Versions
Symbol
Characteristic
Vee
± 5%
Vee ± 10%
Notes
Write Cycle Time
tAVAV/tWC
28F010-65(4)
Min
Max
28FO 10_65(5)
28F010-90(5)
28F010-120(5)
28F010-150(5)
Min
Min
Min
Min
Max
Max
Max
70
90
120
150
ns
ns
. Address Set-Up Time
0
0
0
0
0
tWLAX/tAH
Address Hold Time
40
40
40
40
40
40
40
6
40
40
ns
tWHOX/tOH
Data Hold Time
10
10
10
10
10
ns
tWHGL
Write Recovery Time
before Read
6
6
6
6
6
fLs
tGHWL
Read Recovery Time
before Write
0
0
0
0
0
ns
2
15
15
15
tELWL/tcS
Chip Enable Set-Up Time
before Write
tWHEH/tcH
Chip Enable Hold Time
0
0
0
tWLWH/tWP
Write Pulse Width
40
40
40
ns
ns
20
20
ns
3
10
10
10
10
10
fLs
Duration of Erase
Operation
3
9,5
9.5
9.5
9.5
9.5
ms
Vpp Set-Up Time to
~hip Enable Low
2
1
1
1
1
1
fLs
Duration of Programming
Operation
tWHWH2
-
0
60
20
tWHWH1
--
0
60
20
Write Pulse Width High
--
ns
20
tWHWL/tWPH
-
15
55
6
tVPEL
15
NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification.
4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
6. Minimum specification for Extended Temperature product.
U1
U,
U1
€:
@)
11)-1
o.:a
men
-><-1
55
6
ri:a
-')10
!2. 0
_.
:::Jm
ns
55
40
Data Set-Up Time
3%
CD)Io
'Max
65
tAVWL/tAS
tovWH/tos
Unit
00
3 0
CDo
:::J en
g.1
o.=e
-I:::!.
CD-
3~
'ern
CD "I
"III)
II)UI
c-CD
......
"I."
CD "I
.,,0
"I co
0"1
0.11)
c3
2.0
UI:::J
-<
o
'e
CD
"I
!!.
o·
:::J
!!.
....
r
N
CCI
."
o....
o
28F010
99.9
/v
/~
.
99
'/
95
,/,/
V
' "
/
90
80
I
70
././
.
//
/
,
60
,
50
40
/
30
"",
,
.,
,,
,,
.
,
1/:"
20
./'
10
0.1
2
2.5
3
3.5 4 4.5 5
15
10
20
Chip Program TIme (Sec)
----12V; 10 kc; 23C
------, 11.4V; 10 kc: 70C
- - - - 12V; 100 kc; 23C
290207-13
Figure 8. Typical Programming Capability
7;;
/
V
V
6;;
I
5;;
/
45
,
II
25
2
..... ..... ~
10
V
,,
,
30
40
50
60
70
/V
I
,l"
",
20
,
... ... ..
,~
J
o
V
I
V
III
90
100
110
120
130
TEWP (c)
--1k Cycles
---- 10k Cycles
-._.- lOOk Cycles
290207-14
Figure 9. Typical Program Time at 12V
5-56
I
28F010
99.9
II
99
I
V
,
95
90
/
80
70
..,.'"
'"0
:::>
u
I
60
50
40
I',·'
I',·
" ,.
. .'
, '.
,'' .,
,,. ,
'
/
I
I
I 'i"
30
L'
20
//i
10
1:1
5
/",.
'i"
28F010-200
28FOl 0- 120/1 50
f-
"
U
0.1
0.5
0.7
2
3
4
5 6 78910
20
30
CHIP ERASE TIME (SEC)
12V,10 kc,23C
11.4V,10 kc,OC
12V,100 kc,23C
------
290207-15
Figure 10. Typical Erase Capability
3.2
3.0
\.
~
2.8
r\
2.6
Irl
II>
..,,.
..,;::
..,~'"
..
,
2.2
2.0
:;:
u
I\.
2.4
1'..
~
"I,
'\
.....
1.8
~
1.6
,
......
........
1.4
.... .... ""
, , -.
.......
'"
1.2
1.0
o
10
20
30
40
50
60
70
80
~
1"-..
"
.....
~i'
..... .
r-
f"'.
I-
90 100 110 120 130 140
TEt.lP (Oc)
- - 1 k Cycles
---- 10k Cycle•
• _-_. 100k Cycles
290207-16
Figure 11. Typical Erase Time at 12V
I
5-57
c.n
8:
SET -UP PROGRAM
COMMAND
Vee POWER-UP '"
STANDBY
PROGRAM COMMAND
LATCH ADDRESS'" DATA
PROGRAMMING
PROGRAM
VERIFY.
'COMMAND
PROGRAM
VERIFICATION
~
~
STANDBYI
Vee POWER-DOWN
lot
0
-"
Q
A
ADDRESSES
~I
...C
CE# (E#)
...
CD
~
:I>
0
~I
-...
OE# (G#)
<
CD
0
3
(/I
...01
"U
WE# (w#)
(;
co
iil
3
3
~'I
DATA (DQ)
0
"U
...
CD
III
II
S.OV
Vee
OV
t VPEL
""J
Vpp
. VpPL
L
290207-10
--
:J
<£
@>
_.
Vee POWER-UP II<
STANDBY
ADDRESSES
SET-UP ERASE
COMMAND
ERASE COMMAND
ERASING
ERASE
VERIFY
COMMAND
ERASE
" VERIFICATION
STANDBY/
Vee POWER-DOWN
€:
@l
C11
en
o
Versions
Vee ± 5%
28F010-65(2,4)
Vee ± 10%
Symbol
Characteristic
tAVAV
Write Cycle TIme
tAVEL
Address Set-Up Time
tELAX
Address Hold Time
Notes
Min
Max
28F010-65(5)
28FO 10-90(5)
28F010-120(5)
28F010-150(5)
Min
Min
Min
Min
65
0
45
0
45
35
35
Max
70
6
Max
Max
Unit
Max
90
0
45
60
120
0
55
150
0
35
50
10
6
45
45
10
6
10
ns
6
,.,.s
ns
ns
55
ns
m3>
~o
CD O
-I
r::::"'0
tEHDX
Data Hold Time
10
tEHGL
Write Recovery Time
before Read
6
10
6
. tGHWL
Read Recovery Time
before Write
0
0
0
0
0
ns
0
0
0
0
0
ns
0
45
0
45
0
70
0
70
ns
m
ns
0
20
10
20
10
20
10
ns
3
20
10
0
45
60
20
10
,.,.s
9.5
9.5
9.5
ms
1
1
1
,.,.s
2
tWLEL
Write Enable Set-Up Time
before Chip Enable
tEHWH
Write Enable Hold Time
tELEH
Write Pulse Width
tEHEL
Write Pulse Width High
tEHEH1
Duration of
Operation
tEHEH2
Duration of Erase
Operation
3
9.5
9.5
tVPEL
Vpp Set-Up Time to Chip
Enable Low
2
1
1
CDj
3>
;:;:
...:::JCD
I»
c..J:J
-13>
CDO
3-1
'am
CDJ:J
jilCii
Data Set-Up Time
6
co
....00
:::J:::J:
tDvEH
ns
I\)
-
---
--
---
--
----
---
_ ..
--
-
--
---
-
NOTE:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read:Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification.
4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
6. Minimum specification for Extended Temperature product.
"'•*'
0
.:::J..
2-
i"
c..
...::e;::;:
CD
i0
0
3
3
...nCD
![
I»
:::J
c..
-::J
c[
@
28F010
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Notes
Min
1,3,4
Chip Erase Time
1,2,4
Typical
Max
2
4
30
25
Unit
Sec
Sec
NOTES:
1. "Typicals" are not guaranteed, but based on samples from production lots. Data taken at 25°C, 12.0V Vpp.
2. Minimum byte programming time excluding system overhead is 16 ,,"sec (10 ,,"sec program + 6 ,,"sec write recovery),
while maximum is 400 ,,"sec/byte (16 ,,"sec x 25 loops allowed by algorithm). Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.
3. Excludes OOH programming prior to erasure.
4. Excludes system level overhead.
I
5-61
01
m
N
>z
~~
a··
<.
I\)
::Jm
Vee POWER-UP &
STANDBY
co
0
m
(-,
a
"11
eg'
..,c
a
Q.
CD
c.
/D
::E
....
"'.
~
m
~
iD
..,
--I
3·
:::J
:i"
co
I\)
en
/D
U>
0
.",
... '"
l> a
:e
"0
"0
<
/D
0
co
I\)
..,0
OE# (G#)
'<
OJ
en
0
co
a
"0
co
0
fI'
3
III
WE# (E#)
CE# (w#)
.., ~
..,'tI ::Ja
ca
..,
I\)
3
3
S'
ca
DATA (DO)
0
'0
/D
s.OV
!.
Vee
:::J
OV
..,
0'
III
--
12.0V
Vpp
YpPL
290207-19
€:
@
28F010
ORDERING INFORMATION
ITlp1Zl s 1FI 0 111 0 1-111Z1 0 1
JL
TEMPERATURE
T = EXTENDED (-40°C to +S50C)
BLANK
COMMERCIAL (OOC to +70 0 C)
=
~
L
PACKAGE
P = 3Z-PIN PLASTIC DIP
N
3Z-LEAD PLCC
E
STANDARD 3Z-LEAD TSOP
F = REVERSE 3Z-LEAD TSOP
=
=
VALID COMBINATIONS:
P28F010-65
N28F01O-65
P28F010-90
N28F010-90
P28F010-120
N28F010-120
P28F010-150
N28F010-150
E28F010-65
E28F010-90
E28F010-120
E28F010-150
F28F010-65
F28F010-90
F28F010-120
F28F010-150
ACCESS SPEED
1Z0 ns
150 ns
(ns)
290207-20
TN28F010-90
TE28F010-90
TF28F010-90
ADDITIONAL INfORMATION
Order
Number
294005
ER-20,
"ETOX Flash Memory
Technology"
ER-24,
"Intel Flash Memory"
294008
ER-28,
"ETOX III Flash Memory
Technology"
294012
RR-60,
"ETOX Flash Memory
Reliability Data Summary"
293002
AP-316,
"Using Flash Memory for
In-System
Reprogrammable
Nonvolatile Storage"
292046
AP-325
"Guide to Flash Memory
Reprogramming"
292059
REVISION HISTORY
Number
I
Description
007
Removed 200 ns Speed Bin
Revised Erase Maximum Pulse Count for Figure 5 from 3000 to 1000
Clarified AC and DC Test Conditions
Added "dimple" to F TSOP Package
Corrected Serpentine Layout
008
Corrected AC Waveforms
Added Extended Temperature Options
009
Added 28F01 0-65 and 28F01 0-90 speeds
Revised Symbols, i.e., CE, OE, etc. to CE#, OE#, etc.
5-63
28F512
512K (64K x 8) CMOS FLASH MEMORY
•
•
•
•
•
•
•
Flash Electrical Chip-Erase
- 1 Second Typical Chip-Erase
Quick-Pulse Programming Algorithm
- 10 p,s Typical Byte-Program
- 1 Second Chip-Program
•
•
100,000 Erase/Program Cycles
12.0V ±5% Vpp
High-Performance Read
-120 ns Maximum Access Time
CMOS Low Power Consumption
-10 mA Typical Active Current
- 50 p,A Typical Standby Current
- OW Data Retention Power
Integrated Program/Erase Stop Timers
•
Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
Noise Immunity Features
- ± 10% Vee Tolerance
- Maximum Latch-Up Immunity
through EPI Processing
ETOX II Nonvolatile Flash Technology
- EPROM-Compatible Process Base
- High-Volume Manufacturing
Experience
Pinouts
• -JEDEC-Standard
32-Pin Plastic Dip
- 32-Lead PLCC
(See Packaging Spec., Order #231369)
•
Extended Temperature Options
Intel's 28F512 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F512 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F512 increases
memory flexibility, while contributing to time- and cost-savings.
The 28F512 is a 512-kilobit nonvolatile memory organized as 65,536 bytes of 8 bits. Intel's 28F512 is offered
in 32-pin plastic dip or 32-lead PLCC packages. Pin assignments conform to JEDEC standards for byte-wide
EPROMs.
Extended erase and program cycling capability is designed into Intel's ETOX II (EPROM Tunnel Oxide) process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V Vpp supply, the 28F512
performs 100,000 erase and program cycles well within the time limits of the Quick-Pulse Programming and
Quick-Erase algorithms.
Intel's 28F512 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption, and immunity to noise. Its 120 nanosecond access time provides no-WAlT-state performance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 p,A translates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins, from - 1V to Vee + 1V.
With Intel's ETOX II process base, the 28F512 levers years of EPROM experience to yield the highest levels of
quality, reliability, and cost-effectiveness.
5-64
November 1994
Order Number: 290204-008
28F512
U
c~
s--'
I ERASE
l
p
WE# ~
,.
STATE
CONTROL
COMMAND
REGISTER
INTEGRATED
STOP
TIMER
VOLTAGj
SWITCH
i I
I
TO ARRAY
SOURCE
INPUT jOUTPUT
BUFFERS
-
'"
-
A
~
~r
PGM VOLTAGE
SWITCH
I
CE#
CHIP ENABLE
OUTPUT ENABLE
LOGIC
7'
STB
DATA
LATCH
OE#
..
I
-!
Y-DECODER
STB
An-A15
"
X-DECODER
r----+
r----+
•
•
•
•
r---+
Y-GATING
524,288 BIT
CELL MATRIX
+-
290204-1
Figure 1. 28F512 Block Diagram
I
5-65
28F512
~
~
(J
« « z
, A7
Q.
<.> "
>0.. >0 ~ ztJ
0
A14
~3
As
A5
A4
A3
N2BF512
32 - LEAD PLCC
0.450" x 0.550"
TOP VIEW
AS
fig
~1
A2
10
~
11
~O
Ao
000
12
CE#
13
DO]
OE#
Graphic Not to Scale
290204-3
290204-2
•
Figure 2. 28F512 Pin Configurations
Table 1. Pin Description
Symbol
Type
Name and Function
Ao-A15
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
DQo-DQ7
INPUT/OUTPUT
DATA INPUT/OUTPUT: Inputs data during memory write cycles;
latched during a write cycle.
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled. Data is internally latched during a write cycle.
CE#
INPUT
CHIP ENABLE: Activates the device's control logic, input buffers,
decoders and sense amplifiers. CE # is active low; CE # high
deselects the memory device and reduces power consumption to
standby levels.
OE#
INPUT
WE#
INPUT
OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE# is active low.
WRITE ENABLE: Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WE # pulse.
Note: With Vpp ~ 6.SV, memory contents cannot be altered.
Vpp
ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.
Vee
DEVICE POWER SUPPLY (SV ± 10%)
Vss
GROUND
NC
NO INTERNAL CONNECTION to device. Pin may be driven or left
floating.
S-66
I
28F512
APPLICATIONS
The 28F512 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These features make the 28F512 an innovative alternative to
disk, EEPROM, and battery-backed static RAM.
Where periodic updates of code and data-tables are
required, the 28F512's reprogrammability and nonvolatility make it the obvious and ideal replacement
for EPROM.
Primary. applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption - a consideration particularly important in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and application code. With updatable BIOS, system manufacturers can easily accommodate last-minute changes as
revisions are made.
In diskless workstations and terminals, network traffic reduces to a minimum and systems are instanton. Reliability exceeds that of electromechanical
media. Often in these environments, power interruptions force extended re-boot periods for all networked terminals. This mishap is no longer an issue
if boot code, operating systems, communication protocols and primary applications are flash-resident in
each terminal.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F512 flash memory offers a solid
state alternative in a minimal form factor. The
28F512 provides higher performance, lower power
consumption, instant-on capability, and allows an
"execute in place" memory hierarchy for code and
data table reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail.
The need for code updates pervades all phases of a
system's life - from prototyping to system manufacture to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F512 allows in-
I
circuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexibility.
Material and labor costs associated with code
changes increases at higher levels of system integration - the most costly being code updates after
sale. Code "bugs", or the desire to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the removal of EPROM components or entire boards. With
the 28F512, code updates are implemented locally
via an edge-connector, or remotely over a communcation link.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Flash memory's electrical chip erasure, byte programmability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a "blank slate" in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new "blank slate".
A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 3 depicts two 28F512s tied to the 80C186 system bus.
The 28F512's architecture minimizes interface circuitry needed for complete in·circuit updates of
memory contents.
With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility.
the 28F512 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today's designs.
5-67
28F512
BOClBS
SYSTEM BUS
Vee
Al -A16 - - - - - - - - -..... AO-AI5
+---------.....
DQo-D~
. 2BFSl2
MCSl# _ _ _ _ _ _ _ _ _...... CE#
BHE#
'}-----.t
2BFSl2
1---+1
CE#
WE#
WR#
WE#
AO
RD#
----------+1
OE#
OE#
290204-5
Figure 3. 28F512 in a 80C186 System
PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F512 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility.
In the absence of high voltage on the Vpp pin, the
28F512 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and Intelligent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp
enables erasure and programming of the device. All
functions associated with altering memory contents-Intelligent Identifier, erase, erase verify, program, and program verify-are accessed via the
command register.
Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also. internally latch addresses and data
needed for programming or erase operations. With
the appropriate command written to the register,
5-68
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or output data for erase and program verification.
Integrated Stop Timer
Successive command write cycles define the duration of program and erase operations; specifically,
the program· or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simpli~
fied timing control over these operations; thus eliminating the need fOf/Tlaximum program/erase timing
specifications. Programming and erase pulse
durations are minimums only. When the stop timer
terminates a program or erase operation, the device
enters an inactive state and remains inactive until
receiving the appropriate verify or reset command.
Write Protection
The command register is only active when Vpp is at
high voltage. Depending upon the application, the
system designer may choose to make the Vpp power supply switchable-available only when memory
updates are desired. When Vpp = VPPL, the contents of the register default to the read command,
making the 28F512 a read-only memory. In this
mode, the memory contents cannot be altered.
I
28F512
Table 2. 28F512 Bus Operations
Pins
Vpp(1)
Ao
A9
CE#
OE#
WE#
Read
VpPL
Ao
A9
VIL
VIL
VIH
Data Out
Output Disable
VPPL
X
X
VIL
VIH
VIH
Tri·state
Standby
VpPL
X
X
VIH
X
X
Tri-state
DQo-DQ7
Operation
READ-ONLY
READ/WRITE
Intelligent Identifier (Mfr)(2)
VPPL
VIL
VID(3)
VIL
VIL
VIH
Data = 89H
Intelligent Identifier (Device)(2)
VpPL
VIH
VID(3)
VIL
VIL
VIH
Data = B8H
Read
VPPH
Ao
Ag
VIL
VIL
VIH
DataOut(4)
Output Disable
VPPH
X
X
VIL
VIH'
VIH
Tri-state
standby(5)
VpPH
X
X
VIH
X
X
Tri-state
Write
VpPH
Ao
Ag
VIL
VIH
VIL
Data In(6)
NOTES:
1. Refer to DC Characteristics. When V PP = V PPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VIO is the Intelligent Identifier high voltage. Refer to DC Characteristics.
4. Read operations with Vpp = VPPH may access array data or the Intelligent Identifier codes.
5. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH.
Or, the system designer may choose to "hardwire"
Vpp, making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited whenever VCC is below the write
lockout voltage VLKO. (See Power Up/Down Protection). The 28F512 is designed to accommodate either design practice, and to encourage optimization
of the processor.-memory interface.
The two-step program/erase write sequence to the
Command Register provides additional software
write protection.
BUS OPERATIONS
Read
The 28F512 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip-Enable (CE#) is the power control and
should be used for device selection. Output-Enable
(OE#) is the output control and should be used
to gate data from the output pins, independent of
device selection. Refer to AC read timing
waveforms.
Output Disable
With Output-Enable at a logic-high level (VIH), output
from the device is disabled. Output pins are placed
in a high-impedance state.
Standby
With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F512's circuitry
and substantially reduces device power consumption. The outputs are placed in a high-impedance
state, independent of the Output-Enable signal.
If the 28F512 is deselected during erasure, programming, or program/erase verification, the
device draws active current until the operation is
terminated.
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code (89H) and device code (B8H). Programming equipment automatically matches the device with its proper erase and programming algorithms.
When Vpp is high (VpPH), the read operation can be
used to access array data, to output the Intelligent
Identifier codes, and to access data for program/
erase verification. When Vpp is low (VppL>, the read
operation can only access the array data.
I
5-69
28F512
With Chip-Enable and Output-Enable at a logic low
level, raising A9 to high voltage VID (see DC Chiuacteristics) activates the operation. Data read from locations OOOOH and 0001 H represent the manufacturer's code and the device code, respectively.
The manufacturer- and device-codes can also be .
read via the command register, for instances where
the 28F512 is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location OOOOH
outputs the manufacturer code (89H). A read from
address 0001 H outputs the device code (B8H).
used to store the command, along with address and
data information needed to execute the command.
The command register is written by bringing WriteEnable to a logic-low level (VILl, while Chip-Enable is
low. Addresses are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erasel
Programming Waveforms for specific timing
parameters.
Write
COMMAND DEFINITIONS
Device erasure and programming are accomplished
via the command register, when high voltage is applied to the Vpp pin. The contents of the register
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the
device.
When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only operations.
The command register itself does not occupy an addressable memory location. The register is a latch
Placing high voltage on the Vpp pin enables readl
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F512 register
commands.
Table 3. Command Definitions
Command
Bus
First Bus Cycle
Second Bus Cycle
Cycles
Req'd Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)
Read Memory
1
Write
X
OOH
Read Intelligent Identifier Code(4)
3
Write
X
90H
Read
(4)
Set-up Erase/Erase(5)
2
Write
X
20H
Write
X
20H
Erase Verify(5)
2
Write
EA
AOH
Read
X
EVD.
Set-up Program/Program(S)
Write
PA
PD
(4)
2
Write
X
40H
Program Verify(S)
2
Write
X
COH
Read
X
PVD
Reset(7)
2
Write
X
FFH
Write
X
FFH
NOTES:
1. Bus operations are defined 'in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. ID = Data read from location IA during device identification (Mfr = 89H, Device = B8H).
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes.
5. Figure 5 illustrates the Quick-Erase algorithm.
S. Figure 4 illustrates the Quick-Pulse Programming algo~ithm.
7. The second bus cycle must be followed by the desired command register write.
5-70
I
28F512
Read Command
While Vpp is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.
The default contents of the register upon Vpp power-up is OOH. This default value ensures that no spurious alteration of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 28F512, the device powers-up and
remains enabled for reads until the command-register contents are changed. Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters.
Intelligent Identifier Command
Flash-memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible whil~ the device resides in the target system. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a desired system-design practice.
The 28F512. contains an Intelligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address OOOOH retrieves the manufacturer code of 89H. A read cycle
from address 0001 H returns the device code of
B8H. To terminate the operation, it is necessary to
write another valid command into the register.
of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.
Erase-Verify Command
The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing AOH into the command register. The address
for the byte to be verified must be supplied as it is
latched on the falling edge of the Write-Enable
pulse. The register write terminates the erase operation with the rising edge of its Write-Enable pulse.
The 28F512 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure· 5, the Quick-Erase algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F512.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.
Set-up Program/Program Commands
Set-up Erase/Erase Commands
Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.
To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
Write-Enable pulse and terminates with the rising
edge of the next Write-Enable pulse (i.e., Erase-Verify Command).
This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pin. In the absence
I
Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H ,
into the command register performs the set-up
operation.
Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the rising
edge of the Write-Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
parameters.
5-71
28F512
Program-Verify Command
The 28F512 is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F512 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 4,
the 28F512 Quick-Pulse Programming algorithm, illustrates how commands are combined with bus operations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.
greatly reduces oxide stress and the probability of
failure-increasing time to wearout by a factor of
100,000,000.
The 28F512 is capable of 100,000 program/erase
cycles. The device is programmed and erased using
Intel's Quick-Pulse Programming and Quick-Erase
algorithms. Intel's algorithmic approach uses a series of operations (pulses), along with byte verification, to completely and reliably erase and program
the device.
For further information, see Reliability Report RR-60
(ETOX-II Reliability Data Summary).
QUICK-PULSE PROGRAMMING ALGORITHM
The Quick-Pulse Programming algorithm uses programming operations of 10 /ks duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with Vpp at high voltage. Figure 4 illustrates the Quick-Pulse Programming algorithm.
Reset Command
QUICK-ERASE ALGORITHM
A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.
Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming algorithm, to simultaneously remove charge from all bits in the array.
EXTENDED ERASE/PROGRAM CYCLING
Erasure begins with a read of memory contents. The
28F512 is erased when shipped from the factory.
Reading FFH data from the device would immediately be followed by device programming.
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubledan expensive solution.
Intel has designed extended cycling capability into
its ETOX II flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately 2 MV /
cm lower than EEPROM. The lower electric field
5-72
For devices being erased and reprogrammed, uniform and reliable erasure is ensured by first programming all bits in the device to their charged state
(Data = OOH). This is accomplished; using the
Quick-Pulse Programming algorithm, in approximately one second.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 5 illustrates the Quick-Erase algorithm.
I
28F512
Bus
Operation
Command
Standby
Comments
Wait for VPP Ramp to VpPH(1)
Initialize Pulse-Count
Write
Set-up
Program
Data = 40H
Write
Program
Valid Address/Data
Duration of Program
Operation (tWHWH1)
Standby
Write
Program(2)
Verify
Data = COH; Stops Program
Operation(3)
Standby
tWHGL
Read
Read Byte to Verify
Programming
Standby
Compare Data Output to Data
Expected
Write
Standby
Read
Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to Vppd1)
290204-6
NOTES:
1. See DC Characteristics for value of VPPH and VPPL.
2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command.
3. Refer to principles of operation.
4_ CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.
Figure 4. 28F512 Quick-Pulse Programming Algorithm
I
5-73
intel®
28F512
Bus
Operation
Command
Comments
Entire memory must
before erasure
= OOH
Use Quick-Pulse
Programming Algorithm
(Figure 4)
Standby
Wait for Vpp Ramp to VpPH(1)
Initialize Addresses and
Pulse-Count
Write
Set-up
Erase
Data
= 20H
Write
Erase
Data
= 20H
Standby
Write
Duration of Erase Operation
(tWHWH2)
Erase(2)
Verify
Standby
tWHGL
Read
Read Byte to Verify Erasure
Standby
Compare Output to FFH
Increment Pulse-Count
Write
Read
Standby
290204-7
NOTES:
1. See DC Characteristics for value of VPPH and VPPL'
2. Erase Verify is performed only after chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
Addr = Byte to Verify;
Data = AOH; Stops Erase
Operation(3)
Data = OOH, Resets the
Register for Read Operations
Wait for Vpp Ramp to Vppd1)
3. ReIer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.
Figure 5. 28F512 Quick-Erase Algorithm
5-74
I
28F512
DESIGN CONSIDERATIONS
Two-Line Output Control
Flash-memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an address-decoder output should drive chip-enable,
while the system's read signal controls all flashmemories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power standby condition.
Power Supply Decoupling
Flash-memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current (Ieel issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 fLF ceramic capacitor
connected between Vee and Vss, and between Vpp
and Vss.
Place the high-frequency,. low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 fLF electrolytic capacitor should. be placed at the array's power supply
connection, between Vee and Vss. The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.
Vpp Trace on Printed Circuit Boards
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the Vpp power supply trace. The Vpp pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given the Vee power bus. Adequate Vpp supply traces and decoupling will decrease Vpp voltage spikes and overshoots.
I
Power Up/Down Protection
The 28F512 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F512 is indifferent
as to which power supply, Vpp or Vee, powers up
first. Power supply sequencing is not required. Internal circuitry in the 28F512 ensures that the command register is reset to the read mode on power
up.
A system designer must guard against active writes
for Vee voltages above VLKO when Vpp is active.
Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes.
The control register architecture provides an added
level of protection since alteration of memory contents only occurs after successful completion of the
two-step command sequences.
28F512 Power Dissipation
When designing portable systems, designers must
Gonsider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash memory nonvolatility increases the usable battery life of your system because the 28F512 does not consume any power to
retain code or data when the system is off. Table 4
illustrates the power dissipated when updating the
28F512.
Table 4. 28F512 Typical Update
Power Dissipation(4)
Notes
Power DiSSipation
(Watt-Seconds)
Array Program/
Program Verify
1
0.085
Array Erase/
Erase Verify
2
0.092
One Complete Cycle
3
0.262
Operation
NOTES:
1. Formula to calculate typical Program/Program Verify
Power = [Vpp x # Bytes x Typical # Prog Pulses
(tWHwH1 x IpP2 Typical + tWHGL x IpP4 Typical)] +
[Vcc x # Bytes x Typical # Prog Pulses (tWHWH1 x
ICC2 Typical + tWHGL x ICC4 Typical).
2. Formula to calculate typical Erase/Erase Verify Power
= [VPP(lpP3 Typical x tERASE Typical + Ipps Typical x
tWHGL x # Bytes)] + [VCC(lCC3 Typical x tERASE Typical + Iccs Typical x tWHGL x # Bytes)].
3. One Complete Cycle = Array Preprogram + Array.
Erase + Program.
4. "Typicals" are not guaranteed, but based on a limited
number of samples from production lots.
5-75
28F512
Vpp Supply Voltage with
Respect to Ground
During Erase/Program .... - 2.0V to + 14.0V(2, 3)
ABSOLUTE MAXIMUM RATINGS*
Operating Temperature
During Read .................. O°C to + 70°C(1)
During Erase/Program ......... O°C to + 70°C(1)
Vee Supply Voltage with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Operating Temperature
During Read ............... - 40°C to + 85°C(2)
During Erase/Program ...... -40°C to +85°C(2)
Output Short Circuit Current ............. 100 mA(4)
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Temperature Under Bias ....... -10°C to + 80°C(1)
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
, Temperature Under Bias ....... - 50°C to + 95°C(2)
Storage Temperature .......... - 65°C to
+ 125°C
Voltage on Any Pin with
Respect to Ground .......... - 2.0V to + 7.0V(2)
Voltage on Pin Ag with
Respect to Ground ....... - 2.0V to + 13.5V(2, 3)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Operating temperature is for extended temperature product defined by this specification.
3. Minimum De input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum De voltage on output pins is Vee + 0.5V, which may overshoot to Vee + 2.0V for periods less than 20 ns.
4. Maximum De voltage on Ag or Vpp may overshoot to + 14.0V for periods less than 20 ns.
5. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING CONDITIONS
Symbol
Limits
Parameter
Unit
Min
Max
Comments
TA
Operating Temperature(1)
0
70
°C
For Read-Only and
Read/Write Operations
for Commercial Products
TA
Operating Temperature(2)
.".40
+85
°C
For Read-Only and
Read/Write Operations
for Extended Temperature Products
Vee
Vee Supply Voltage
4.50
5.50
V
DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Commercial Products
Symbol
Parameter
Limits
Notes
Min
Typ(4)
Unit
Test Conditions
Max
III
Input Leakage Current
1
±1.0
/LA
Vee = Vee Max
VIN = Vee or Vss
ILO
Output Leakage Current
1
±10.0
/LA
Vee = Vee Max
VOUT = Vee or Vss
Ices
Vcc Standby Current
1
0.3
1.0
rnA
Vec = Vcc Max
CE# = VIH
ICC1
V cc Active Read Current
1
10
30
rnA
Vec
f
=
= Vcc Max, CE# = VIL
6 MHz, lOUT = 0 rnA
Ice2
Vcc Programming
Current
1,2
1.0
10
rnA
Programming in Progress
ICC3
Vec Erase Current
1,2
5.0
15
rnA
Erasure in Progress
ICC4
Vec Program Verify
Current
1,2
5.0
15,
rnA
Vpp = VpPH
Program Verify in Progress
5-76
I
28F512
DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Commercial Products
(Continued)
Symbol
Parameter
Limits
Notes
Min
Ices
Vee Erase Verify Current
1,2
Ipps
VPP Leakage Current
1
IpP1
VPP Read Current, Standby
Current, or 10 Current
1
Unit
Test Conditions
Typ(4)
Max
5.0
15
rnA
VPP = VPPH
Erase Verify in Progress
±10.0
p.A
VPP ~ Vee
200
p.A
Vpp> Vee
90
Vpp ~ Vee
±10.0
IpP2
Vpp Programming Current
1,2
B.O
30
rnA
Vpp = VPPH
Programming in Progress
IpP3
VPP Erase Current
1,2
4.0
30
rnA
VPP = VPPH
Erasure in Progress
IpP4
VPP Program Verify Current
1,2
2.0
5.0
rnA
VPP = VPPH
Program Verify in Progress
Ipps
VPP Erase Verify Current
1,2
2.0
5.0
rnA
Vpp = VPPH
Erase Verify in Progress
VIL
Input Low Voltage
-0.5
O.B
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage
"VID
Ag Intelligent Identifier Voltage
110
Ag Intelligent Identifier Current
VPPL
VPP during Read-Only
Operations
VPPH
VPP during Read/Write
Operations
VLKO
Vee Erase/Write Lock Voltage
Vee
+ 0.5
0.45
2.4
11.50
V
V
IOL = 5.BmA
Vee = Vee Min
V
IOH = -2.5mA
Vee = Vee Min
13.00
V
200
p.A
0.00
6.5
V
11.40
12.60
V
1,2
90
2.5
Ag = VID
NOTE: Erase/Program are
Inhibited when VPP = VPPL
V
DC CHARACTERISTICS-CMOS COMPATIBLE-Commercial Products
Symbol
Parameter
Limits
Notes
Min
Typ(4)
Unit
Test Conditions
Max
III
Input Leakage Current
1
±1.0
p.A
Vee = Vee Max
VIN = Vee or Vss
ILO
Output Leakage Current
1
±10.0
p.A
Vee = Vee Max
VOUT = Vee or Vss
Ices
Vee Standby Current
1
50
100
p.A
Vee = Vee Max
CE# = Vee ±0.2V
lee1
Vee Active Read Current
1
10
30
rnA
Vee = Vee Max, CE# = VIL
f = 6 MHz, lOUT = 0 rnA
I
5-77
- 28F512
DC CHARACTERISTICS-CMOS COMPATIBLE-Commercial Products (Continued)
Symbol
Parameter
Limits
Notes
Min
Test Conditions
Unit
Typ(4)
Max
lee2
Vee Programming
Current
1,2
1.0
10
mA
Programming in Progress
lee3
Vee Erase Current
1,2
5.0
15
mA
Erasure in Progress
lee4
Vee Program Verify
Current
1,2
5.0
15
mA
VPP = VPPH
Program Verify in Progress
Ices
Vee Erase Verify Current
1,2
5.0
15
mA
VPP = VPPH
Erase Verify in Progress
IpPS
VPP Leakage Current
1
±10.0
,."A
Vpp';::; Vee
IpP1
VPP Read Current,lD
Current, or Standby
Current
1
200
,."A
Vpp> Vee
90
±10.0
Vpp';::; Vee
IpP2
Vpp Programming
Current
1,2
8.0
30
mA
Vpp = VPPH
Programming in Progress
IpP3
VPP Erase Current
1,2
4.0
30
mA
VPP = VPPH
Erasure in Progress
IpP4
VPP Program Verify
Current
1,2
2.0
5.0
mA
VPP = VPPH
Program Verify in Progress
Ipps
VPP Erase Verify Current
1,2
2.0
5.0
mA
VPP = VPPH
Erase Verify in Progress
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
0.7 Vee
VOL
Output Low Voltage
VOH1
Output High Voltage
+ 0.5
0.45
0.85 Vee
V
V
V
IOL = 5.8mA
Vee = Vee Min
IOH = - 2.5 mA,
Vee = Vee Min
IOH = -100,."A,
Vee = Vee Min
Vee - 0.4
VOH2
13.00
V
Ag
= VIO
200
jJ.A
As
= VIO
0.00
6.5
V
VPP during Read/Write
Operations
11.40
12.60
V
Vee Erase/Write Lock
Voltage
2.5
VIO
Ae Intelligent Identifier
Voltage
110
Ae Intelligent Identifier
Current
VpPL
VPP during Read-Only
Operations
VP~H
VLKO
5-78
Vee
11.50
1,2
90
NOTE: Erase/Program
are Inhibited when
VPP = VPPL
V
I
28F512
DC CHARACTERISTICS-TTL/NMOS COMPATIBLE-Extended Temperature
Products
Symbol
Parameter
Notes
Limits
Min Typ(4)
Mal(
Unit
Test Conditions
III
Input Leakage Current
1
± 1.0
f.LA Vee = Vee Max
ILO
Output Leakage Current
1
±10.0
f.LA Vee = Vee Max
lees
Vee Standby Current
1
0.3
1.0
rnA Vee = Vee Max
CE# = VIH
lee1
Vee Active Read Current
1
10
30
rnA Vee = Vee Max, CE# = VIL
f = 6 MHz, lOUT = 0 rnA
lee2
Vee Programming Current
1,2
1.0
30
mA Programming in Progress
lee3
Vee Erase Current
1,2
5.0
30
rnA Erasure in Progress
lee4
Vee Program Verify Current
1,2
5.0
30
rnA Vpp = VPPH
Program Verify in Progress
lees
Vee Erase Verify Current
1,2
5.0
30
rnA Vpp = VPPH
Erase Verify in Progress
Ipps
Vpp Leakage Current
1
IpP1
Vpp Read Current, Standby
Current, or ID Current
1
VIN
= Vee or VSS
VOUT
90
= Vee or Vss
±10.0
f.LA Vpp s Vee
200
f.LA Vpp > Vee
± 10.0
Vpp s Vee
IpP2
Vpp Programming Current
1,2
8.0
30
rnA Vpp = VPPH
Programming in Progress
IpP3
Vpp Erase Current
1,2
4.0
30
rnA Vpp = VPPH
Erasure in Progress
IpP4
Vpp Program Verify Current
1,2
2.0
5.0
rnA Vpp = VPPH
Program Verify in Progress
IpP5
Vpp Erase Verify Current
1,2
2.0
5.0
rnA Vpp = VPPH
Erase Verify in Progress
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage
VID
Aglntelligent Identifier Voltage
0.8
Vee
+ 0.5
0.45
2.4
11.50
13.00
V
V
V
IOL = 5.8 mA
Vee = Vee Min
V
IOH = -2.5 rnA
Vee = Vee Min
V
liD
Ag Intelligent Identifier Current
500
f.LA Ag = VID
VPPL
Vpp during Read-Only
Operations
0.00
6.5
V
VPPH
Vpp during Read/Write
Operations
11.40
12.60
V
VLKO
Vee Erase/Write Lock Voltage
I
1,2
90
2.5
NOTE: Erase/Program are
Inhibited when Vpp = VpPL
V
5-79
28F512
DC CHARACTERISTICS-CMOS COMPATIBLE-Extended Temperature
Products
Symbol
Parameter
Limits
Notes
Min
Typ(4)
Unit
Test Conditions
Max
III
Input Leakage Current
1
±1.0
/LA
Vee = Vee Max
VIN = VeeorVss
ILO
Output Leakage Current
1
±10.0
/LA
Vee = Vee Max
VOUT = Vee or Vss
lees
Vee Standby Current
1
50
100
/LA
Vee = Vee Max
CE# = Vee ±0.2V
lee1
Vee Active Read Current
1
10
50
mA
Vee = Vee Max, CE# = VIL
f = 6 MHz, lOUT = 0 mA
ICC2
Vee Programming Current
1,2
1.0
10
mA
Programming in Progress
leC3
Vee Erase Current
1,2
5.0
15
mA
Erasure in Progress
ICG4
Vee Program Verify
Current
1,2
5.0
30
mA
Vpp = VPPH
Program Verify in Progress
lee5
Vee Erase Verify Current
1,2
5.0
30
mA
VPP = VPPH
Eras~ Verify in Progress
Ipps
VPP Leakage Current
1
±10.0
/LA
Vpp:S; Vee
IpP1
VPP Read Current, ID
Current, or Standby
Current
1
200
/LA
Vpp> Vee
90
±10.0
Vpp:S; Vee
IpP2
Vpp Programming Current
1,2
8.0
30
mA
Vpp = VPPH
Programming in Progress
IpP3
VPP Erase Current
1,2
4.0
30
mA
VPP =,VPPH
Erasure in Progress
IpP4
VPP Program Verify
Current
1,2
2.0
5.0
mA
VPP = VPPH
Program Verify in Progress
IpP5
VPP Erase Verify Current
1,2
2.0
5.0
mA
Vpp = VPPH
Erase Verify in Progress
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
0.7 Vee
VOL
Output Low Voltage
5-80
Vee
+ 0.5
0.45
V
V
IOL = 5.8mA
Vee = Vee Min
I
28F512
DC CHARACTERISTICS-CMOS COMPATIBLE-Extended Temperature
Products (Continued)
.
Symbol
Parameter
Limits
Notes
Min
VOH1
Output High Voltage
Typ(4)
Unit
Test Conditions
V
IOH = - 2.5 mA,
Vee = Vee Min
Max
0.85 Vee
IOH = -100 fLA,
Vee = Vee Min
Vee - 0.4
VOH2
VIO
Ag Intelligent Identifier Voltage
110
Ag Intelligent Identifier Current
VpPL
Vpp during Read-Only Operations
VPPH
Vpp during Read/Write Operations
VLKO
Vee Erase/Write Lock Voltage
13.00
V
Ag = VIO
500
fLA
Ag = VID
0.00
6.5
V
11.40
12.60
11.50
gO
1,2
NOTE: Erase/
Program
are Inhibited
when
Vpp = VpPL
V
V
2.5
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol
Parameter
Limits
Notes
Min
Unit
= OV
CIN
Address/Control Capacitance
3
8
pF
VIN
COUT
Output Capacitance
3
12
pF
VOUT
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at Vee c= 5.0V, Vpp
12.0V, T =
currents are valid for all product versions (packages and speeds).
2. Not 100% tested: characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots.
I
Conditions
Max
= OV
+ 25°C.
These
5-81
28F512
AC TESTING INPUT/OUTPUT WAVEFORM
AC TESTING LOAD CIRCUIT
2.4
1.3V
INPUT
0.45
lN914
~:~
>
3.3K
TEST POINTS
1--+-0 OUT
I
290204-B
AC Testing: Inputs are driven at 2.4V for a logic "I" and 0.45V for
a logic "0". Testing measurements are made at 2.0V for a logic
"I" and O.BV for a logic "0". Rise/Fall time,; 10 ns.
CL
=100pF
290204-9
CL~100pF
CL includes Jfg Capacitance
AC TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................ 0.45Vand 2.4V
Input Timing Reference Level ....... 0.8V and 2.0V
Output Timing Reference Level ...... 0.8V and 2.0V
AC CHARACTERISTICS-Read-Only Operations
Versions(1)
Notes
Symbol
Characteristic
N28F512-120
TN28F512-120
P28F512-120
TP28F512-120
N28F512-150
P28F512-150
Min
Min
Max
120
Unit
Max
tAYAy/tRC
Read Cycle Time
tELQy/tCE
Chip Enable Access Time
120
150
ns
tAYQy/tACC
Address Access Time
120
150
ns
tGLQy/tOE
Output Enable Access Time
50
55
ns
tELQXltLZ
Chip Enable to Output in Low Z
2,3
tEHQZ
Chip Disable to Output in High Z
2
tGLQXltOLZ
Output Enable to Output in Low Z
2,3
tGHQZltDF
Output Disable to Output in High Z
2
tOH
Output Hold from Address, C,E #, or
OE# Change
2,4
tWHGL
Write Recovery Time before Read
150
0
0
55
0
ns
•
ns
55
ns
35
ns
0
30
ns
0
0
ns
6
6
/Ls
NOTES:
1. Model number prefixes: N = PLCC. P = PDIP, T = Extended Temperature.
2. Sampled, not 100% tested.
3. Guaranteed by design.
4. Whichever occurs first.
5-82
I
-
_.
Vee POWER-UP
DEVICE AND
ADDRESS SELECTION
STANDBY
OUTPUTS ENABLED
Vee POWER-DOWN
€:
@!
ADDRESSES
ADDRESS STABLE .
I·
~
c
;;
STANDBY
DATA VALID
.
t AVAV (~e)
CE# (E#)
sn
~
ii
..
0'
:u
CD
OE# (G#)
I.
1 t WHGL 1
WE# (W#)
8.
I----- '
40
"
30
//
//
I ,, ,
I ""
//
/f
0. 1
0.3
,
J 1/
I ,-/
20
10
)1,, ,/V' ,
2TTrn
,Ii
05 0.7
1
3
4
1F-2OO
5 6 78910
20
CHIP ERASE TIME (.ec)
- - - 12V; 10 kc; 230C
_ •• 11.4V; 10 kc; OOC
······-12V; 100 kc; 230C
NOTE:
Does not include Pre-Erase program.
290204-17
Figure 10. 28F512 Typical Erase Capability
5-86
I
SET-UP PROGRAM
COMMAND
Vee POWER-UP &
.
STANDBY
PROGRAM COMMAND
LATCH ADDRESS & DATA
PROGRAMMING
PROGRAM VERIFY
COMMAND
PROGRAM
VERIFICATION
STANDBY /
Vee POWER-DOWN
V'H
ADDRESSES
_.
::l
c[
®
VIL
V'H
."
IQ"
CE#
iil
V'L
r:::
....
....
»
o
:e
~
3
III
V'H
OE#
V'L
o
-...
~
V'H
WE#
"tI
o
cc
iil
3
3
5"
cc
o
"0
..
V'L
V'H
DATA
V'L
CD
iil
0"
S.OV
::J
III
Vee
OV
tVP£l
12.0V
I-
Vpp
VpPL
290204-19
tTl
0,
-.J
N
CO
."
U1
.....
N
28F512
ALTERNATIVE CE #-CONTROLLED WRITES
Versions
Symbol
Characteristic
tAVAV
Write Cycle
Time
tAVEL
Notes
28F512-120
Min
Max
28F512-150
Min
Max
Unit
120
150
ns
Address SetUpTime
0
0
ns
tELAX
Address Hold
Time
80
80
ns
tDVEH
Data Set-Up
Time
50
50
ns
tEHDX
Data Hold
Time
10
10
ns
tEHGL
Write
Recovery Time
before Read
6
6
f.ts
tGHEL
Read
Recovery Time
before Write
0
0
f.ts
tWLEL
Write Enable
Set-UpTime
before Chip
Enable
0
0
ns
tEHWH
Write Enable
Hold Time
0
0
ns
tELEH
Write Pulse
Width
70
70
ns
tEHEL
Write Pulse
Width High
20
20
ns
tVPEL
Vpp Set-Up
Time to Chip
Enable Low
1.0
1.0
f.ts
2
1
2
NOTE:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the write pulse width (within a longer Write-Enable timing waveform) all set-up, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
2. Guaranteed by design.
5-88
I
--
SET-UP ERASE
COMMAND
Vee POWER-UP &:
STANDBY
V,H
ERASE COMMAND
ERASING
ERASE VERIFY
COMMAND
ERASE
VERIFICATION
J:
€:
STANDBY/
@l
Vee POWER-DOWN
1.. Ja """
11
ADDRESSES
v"
V,H
"
iii
c
iil
.....
~
1;
f
3
-...
0'
CEo
v"
V,H
DE'
V,L
V,H
III
WE_
o
v"
m
ii1
Ill'
CD
o
'2
~
:::I
III
V,H
DATA
V,L
5.0V
Vee
OV
tvPEL
12.0V
Vpp
VpPL
290204-20
N
0)
U1
cP
CD
...
."
U1
N
~
'"
III
SET -up PROGRAM
COMMAND
Vee POWER-UP &:
STANDBY
PROGRAM COMMAND
LATCH ADDRESS &: DATA
PROGRAMMING
PROGRAM VERifY
COMMAND
PROGRAM
VERifiCATION
~
....
STANDBYI
Vee POWER-DOWN
'"
V'H
ADDRESSES
V'L
:!!
ID
C
V'H
....
WE#
i
So'
>
V'L'
i
III
3
V'H
CD
OE#
l;
I
I
V'L
~
V'H
CE#
1/1
...0'
a"
ID
;3
s-
V'L
V'H
DATA
V'L
ID
o
~
io
:::II
1/1
S.OV
Vee
OV
t VPEL
12.0V
f--o
--
Vpp
VpPL
290204-21
€:
@J
28F512
Ordering Information
ITlplzlslFl511lzl-lllzl01
I
lpACKAGE
IL__
-ACCESS SPEED (n.)
P = 3Z-PIN PLASTIC DIP
N = 32-LEAD PLCC
120 n.
150 n.
TEMPERATURE
T EXTENDED (-40 0 C TO +S5 0 C)
8LANK COMMERCIAL (cOe TO +70 0e)
=
=
290204-13
Valid Combinations:
P28F512-120
N28F512-120
TP28F512-120
P28F512-150
N28F512-150
TN28F512-120
ADDITIONAL INFORMATION
Order Number
ER-20, "ETOX II Flash Memory Technology"
294005
ER-24, "Intel Flash Memory"
294008
RR-60, "ETOX II Flash Memory Reliability Data Summary"
293002
AP-316, "Using Flash Memory for In-System Reprogrammable
Nonvolatile Storage"
292046
AP-325 "Guide to Flash Memory Reprogramming"
292059
REVISION HISTORY
Number
I
Description
006
Removed 200 ns speed bin
Revised Erase Maximum Pulse Count for Figure 5 from 3000 to 1000
Clarified AC and DC test conditions
007
Corrected AC Waveforms
Added Extended Temperature devices; TP28F512-120, TN28F512-120
008
Revised symbols; i.e., CE, OE, etc. to CE#, OE#, etc.
5-91
28F256A
256K (32K x 8) CMOS FLASH MEMORY
•
•
Flash Electrical Chip-Erase
- 1 Second Typical Chip-Erase
Quick-Pulse Programming Algorithm
-10 p,s Typical Byte-Program
- 0.5 Second Chip-Program
•
• High-Performance Read
•
•
•
•
100,000 Erase/Program Cycles
12.0V ±5% Vpp
-120 ns Maximum Access Time
CMOS Low Power Consumption
- 10 mA Typical Active Current
- 50 p,A Typical Standby Current
- OW Data Retention Power
•
Integrated Program/Erase Stop Timer
Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
Noise Immunity Features
- ± 10% Vee Tolerance
- Maximum Latch-Up Immunity
through EPI Processing
" Flash Nonvolatile Technology
• -ETOX
EPROM-Compatible Process Base
- High-Volume Manufacturing
Experience
•
JEDEC-Standard Pinouts
- 32-Pin PDIP
- 32-Lead PLCC
(See Packaging Spec., Order #231369)
Intel's 28F256A CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F256A adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F256A increases
memory flexibility, while contributing to time and cost savings.
The 28F256A is a 256-kilobit nonvolatile memory organized as 32,768 bytes of 8 bits. Intel's 28F256A is
offered in 32-pin plastic dip and 32-lead PLCC. Pin aSSignments conform to JEDEC standards.
Extended erase and program cycling capability is designed into Intel's ETOX II (EPROM Tunnel Oxide) process technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V Vpp supply, the 28F256A
performs a minimum of 10,000 erase and program cycles well within the time limits of the Quick-Pulse Programming and Quick-Erase algorithms.
Intel's 28F256A employs advanced CMOS circuitry for systems requiring high-performance access speeds,
low power consumption, and immunity to noise. Its 120 ns access time provides no-WAlT-state performance
for a wide range of microprocessors and microcontrollers. Typical standby current of 50 /LA translates into
power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved
through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on address
and data pins, from -1V to Vee + 1V.
With Intel's ETOX II process base, the 28F256A levers years of EPROM experience to yield the highest levels
of quality, reliability, and cost-effectiveness.
5-92
October 1993
Order Number: 290243-006
28F256A
11
---.
Vee
---.
vss
J
J ERASE VOLTAGE
L
SWITCH
vpp
J l
STATE
CONTROL
J INPUT/OUTPUT
BUFFERS
I
TO ARRAY
SOURCE
. r-
I--
t---
WE# ~
COMMAND
REGISTER
r
CE#
INTEGRATED PROGRAM
/ERASE STOP TIMER
~
PGM VOLTAGE
SWITCH
J
CHIP ENABLE
OUTPUT ENABLE
LOGIC
:;STB
DATA
LATCH
OE#
+
- Po,4
!
~
Y-DECODER
STB
7
••
-'"
~
X-DECODER
•
~
.~
Y-GATING
262,144 BIT
CELL MATRIX
~
290243-1
Figure 1. 28F256A Block Diagram
28F256A
vpp
Graphic Not to Scale
...~
vee
u
z
u
z
u"
0.
~ >0 ~ uz
NC
WE#
NC
NC
A7
Po,z
As
A'4
A'3
A7
A'4
A'3
A5
As
As
As
A4
Ag
A5
Ag
A3
A4
A, ,
Az
Po, 1
OE#
A3
OE#
Po,
A,a
Az
A,a
Ao
CE#
DOa
A,
CE#
Ao
007
000
DOs
DO,
005
D~
16 17 18 19 20
O&-rJ,~d&'&>
o c > c c c c
290243-3
002
Vss
290243-2
Figure 2. 28F256A Pin Configurations
I
5·93
intel®
28F256A
•
Table 1. fJin Description
Symbol
,
Type
Name and Function
Ao-A14
INPUT
ADDRES~
OQO-DQ7
INPUT/
OUTPUT
DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs
data during memory read cycles. The data pins are active high and float to
tri-state OFF when the chip is deselected or the outputs are disabled. Data
is internally latched during a write cycle.
CE#
INPUT
CHIP ENABLE activates the device's control logic, input buffers,
decoders, and sense amplifiers. CE # is active low; CE # high deselects
the memory device and reduces power consumption to standby levels.
OE#
INPUT
OUTPUT ENABLE gates the devices output through the data buffers
during a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE# pulse. Note: With Vpp :5: 6.5V,
memory contents cannot be altered.
INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
Vpp
ERASE/PROGRAM POWER SUPPLY for writing the command register,
erasing the entire array, or programming bytes in the array.
Vee
DEVICE POWER SUPPLY (5V ± 10%).
Vss
GROUND.
NC
NO INTERNAL CONNECTION to device. Pin may be driven or left floating.
APPLICATIONS
The 28F256A flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These features make the 28F256A an innovative alternative to
disk, EEPROM, and battery-backed static RAM.
Where periodic updates of code and data-tables are
required, the 28F256A's reprogrammability and nonvolatility make it the obvious and ideal replacement
for EPROM.
Primary applications and operating systems stored
in flash eliminate the slow disk-DRAM download process. This results in a dramatic enhangement of performance and substantial reduction of power consumption-considerations particularly important in
portable equipment. Flash memory increases .flexibility with electrical chip-erasure and in-system update capabilitY of operating systems and application
code. With updatable BIOS, system'manufacturers
can easily accommodate last-minute changes as revisions are made.
In diskless workstations and terminals, network traffic reduces to a minimum and systems become Instant-on. Reliability exceeds that of electromechani-
5-94
cal media. Often in these environments, power interrupts force extended re-boot periods for all networked terminals. This mishap is no longer an issue
if boot code, operating systems, communications
protocols and primary applications are flash-resident
in each terminal.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F256A provides higher performance,
lower power consumption, instant-on capability, and
allows an "execute in place" memory hierarchy for
code and data table reading. Additionally, the flash
memory is more rugged and reliable in harsh environments where extreme temperatures and shock
can cause disk-based systems to fail.
The need for code updates pervades all phases of a
system's life-from prototyping to system manufacturing to after-sale serviqe. The electrical chip-erasure and reprogramming ability of the 28F256A allows in-circuit alterability; this eliminates unnecessary handling arid less-reliable socketed connections, while adding greater test, manufacture, and
update flexibility.
Material and labor costs associated with code
changes increases at higher levels of system inte-
I
28F256A
gration-the most costly being code updates after
sale. Code "bugs", or the desire to augment system
functionality, prompt after-sale code updates. Field
revision to EPROM-based code requires the removal of EPROM components or entire boards. With the
28F256A, code updates are implemented locally via
an edge-connector, or remotely over a communications link.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Flash memory's electrical Chip-erasure, byte programmability and complete nonvolatility fit well with
data accumUlation and recording needs. Electrical
chip-erasure gives the designer a "blank slate" in
which to log or record data:. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new "blank slate".
A high degree of on-chip feature integration Simplifies memory-to-pfocessor interfacing. Figure 3 depicts two 28F256As tied to the 80C186 system bus.
The 28F256A's architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.
With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility, the
28F256A is a functional superset of one or more of
the alternatives: EPROMs, EEPROMs, battery
backed static RAM, or disk. EPROM-compatible
read specifications, straightforward interfacing, and
in-circuit alterability offer designers unlimited flexibility to meet the high standards of today's designs.
Vee
BOC 1B6
SYSTEM BUS
A, -A,s
---------~ AO -A, 4
Ao -A, 4
DQo-D~
DQO-D~
..----------1
DQo-D~
2BF256A
MCSO# ---------I~ CE#
BHE# - - - - - \
28F256A
CE#
WE#
WR#
Ao---I
RD# ---------~ OE#
WE#
OE#
290243-4
Figure 3. 28F256As in a 80C186 System
I
5-95
28F256A
PRINCIPLES OF OPERATION
Write Protection
Flash memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F256A introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power supply during erasure and programming; 'and maximum
EPROM compatibility.
The command register is only active when Vpp is at
high voltage. Depending upon the application, the
system designer may choose to make the Vpp power supply switchable-available only when memory
updates are desired. When Vpp = VPPL, the contents of the register default to the read command,
making the 28F256A a read-only memory. In this
mode, the memory contents cannot be altered.
In the absence of high voltage on the Vpp pin, the'
28F256A is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and Intelligent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the Vpp pin. In addition, high voltage on Vpp
enables erasure and programming of the device. All
functions associated with altering memory contents-Intelligent Identifier, erase, erase verify, program, and program verify-are accessed via the
command register.
Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
control the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for programming and erase operations. With
the appropriate command written to the register,
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or output data for erase and program verification.
Integrated Program/Erase Stop Timer
Successive command write cycles define the duration of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate verify or reset command.
Or, the system designer may choose to "hardwire"
Vpp, making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited whenever Vee is below the write.
lockout voltage VLKO. (See Power Up/Down Protection). The 28F256A is designed to accommodate either design practice, and to encourage optimization
of the processor-memory interface.
The two-step program/erase write sequence to the
Command Register provides additional software
write protection.
BUS OPERATIONS
Read
The 28F256A has two control functions, both of
which must be logically active, to obtain data at the
outputs. Chip-Enable (CE #) is the power control and
should be used for device selection. Output-Enable
(OE#) is the output control and should be used to
gate data from the output pins, independent of device selection. Refer to AC read timing waveforms.
When Vpp is high (VpPH), the read operations can
be used to access array data, to output the Intelligent Identifier codes, and to access data for program/erase verification. When Vpp is low (VppLl, the
read operation can access only the array data.
Output Disable
With Output-Enable at a logic-high level (VI H)' output
from the device is disabled. Output pins are placed
in a high-impedance state.
Standby
With Chip-Enable at a logic-high level, the standby
operation disables most of the 28F256A's Circuitry
and substantially reduces device power consumption. The outputs are placed in a high-impedance
5-96
I
28F256A
state, independent of the Output-Enable signal. If
the 28F256A is deselected during erasure, programming, or program/erase verification, the device
draws active current until the operation is terminated.
plied to the Vpp pin. The contents of the register
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the device.
The command register itself does not occupy an addressable memory location. The register is a latch
used to store the command, along with address and
data information needed to execute the command.
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code (89H) and device code (89H). Programming equipment ·automatically matches the device with its proper erase and programming algorithms. With Chip-Enable and Output-Enable at a
logic low level, rising A!l to high voltage VIO (see
D.C. Characteristics) activates the operation. Data
read from locations OOOOH and 0001 H represent the
manufacturer's code and the device code, respectively.
The command register is written by bringing WriteEnable to a logic-low level (VIU, while Chip-Enable is
low. Addresses are latched on the falling edge of
Write-Enable, while data is latched on the rising
edge of the Write-Enable pulse. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing parameters.
The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F256A is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address IGcation OOOOH
outputs the manufacturer code (89H). A read from
address 0001 H outputs the device code (89H).
COMMAND DEFINITIONS
When low voltage is applied to the Vpp pin, the contents of the command register default to OOH, enabling read-only operations.
Placing high voltage on the Vpp pin enables read/
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F256A register commands.
Write
Device erasure and programming are accomplished
via the command register, when high voltage is ap-
Table 2. 28F256A Bus Operations
Pins
Vpp(1)
Ao
Ag
CE#
OE#
WE#
VPPL
Ao
X(7)
A9
X
VIL
VIL
VIH
Data Out
VIL
VIH
VIH
Tri-State
Tri-State
DQo-DQ7
Operation
~
Read
Output Disable
VPPL
Standby
VPPL
X
X
VIH
X
X
Intelligent ID Manufacturer(2)
VPPL
VIL
VI 0(3)
VIL
VIL
VIH
Intelligent ID Device(2)
VPPL
VIH
VI0(3)
VIL
VIL
VIH
Data = 89H
Read
VPPH
Ao
A9
VIL
VIL
VIH
DataOut(4)
Ow
Output Disable
VPPH
X
X
VIL
VIH
VIH
Tri-State
II:~
Standby(5)
VPPH
X
X
VIH
X
X
Tri-State
Write
VPPH
Ao
A9
VIL
VIH
VIL
z
~
C
w
II:
......
~!::
Data = 89H
Data In (6)
NOTES:
1. Refer to DC Characteristics. When Vpp = VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence.
Refer to Table 3. All other addresses low.
3. VIC is the Intelligent Identifier high voltage. Refer to D.C. Characteristics.
4. Read operations with Vpp = VPPH may access array data or the Intelligent Identifier codes.
5. With Vpp at high voltage, the standby current equals Icc + Ipp (standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH.
I
5-97
intel®
.28F256A
Table 3. Command Definitions
Command
Read Memory
Second Bus Cycle
First Bus Cycle
Bus
Cycles
Req'd Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)
1
Write
X
OOH
Read Intelligent 10 Codes
3
Write
X
90H
Read
(4)
(4)
Set-Up Erase/Erase(6)
2
Write
X
20H
Write
X
20H
Erase Verify(6)
2
Write
EA
AOH
Read
X
EVO
Set-Up Program/Program(5)
2
Write
X
40H
Write
PA
PO
Program Verify(5)
2
Write
X
COH
Read
X
PVO
ReseW)
2
Write
X
FFH
Write
X
FFH
NOTES:
1. Bus operation are defined in Table 2.
2. IA = Identifier address: OOH for manufacturer code, 01 H for device code.
EA = Address of memory location to be read during erase verify.
PA = Address of memory location to be programmed.
Addresses are latched on the falling edge of the Write-Enable pulse.
3. ID = Data read from location IA during device identification. (Mfr = 89H, Device = B9H).
EVD = Data read from location EA during erase verify.
PD = Data to be programmed at location PA. Data is latched on the rising edge of the Write-Enable.
PVD = Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read Intelligent ID command, tWo read operations access manufacturer and device codes.
5. Figure 4 illustrates the Quick-Pulse Programming Algorithm.
6. Figure 5 illustrates the Quick-Erase Algorithm.
7. The second bus cycle must be followed by the desired command register write.
Read Command
While Vpp is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
OOH into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.
The default contents of the register upon Vpp power-up is OOH. This default value ensures that no spurious alternation of memory contents occurs during
the Vpp power transition. Where the Vpp supply is
hard-wired to the 28F256A, the device powers-up
and remains enabled for reads until the command
register contents are changed. Refer to the AC
Read Characteristics and Waveforms for specific
timing parameters.
Intelligent Identifier Command
Flash memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, mul-
5-98
tiplexing high voltage onto address lines is not a desired system-design practice.
The 28F256A contains an Intelligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address OOOOH retrieves the manufacturer code 89H. A read cycle
from address 0001 H returns the device code 89H.
To terminate the operation, it is necessary to write
another valid command into the register.
Set-Up Erase/Erase Commands
Set-up Erase is a command-only operation .that
stages the device for electrical erase of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register. To commence chip-erasure, the erase command (2QH)
must again be written to the register. The erase operation begins. with the rising edge of the Write-Enable pulse and terminate with the rising edge of the
next Write-Enable pulse (i.e., Erase-Verify Command).
This two-step sequence of set-up followed byexecution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the Vpp pin. In the absence
I
28F256A
of this high voltage, memory contents are protected
. against erallure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.
program-verify command. Refer to AC Programming
Characteristics and Waveforms for specific timing
parameters.
Erase-Verify Command
Program Verify Command
The erase command erases all of the bytes of the
array in parallel. After each erase operation, all bytes
must be verified. The erase verify operation is initiated by writing AOH into the command register. The
address for the byte to be verified must be supplied
as it is latched on the falling edge of the Write-Enable pulse. The register write terminates the erase
operation with the rising edge of its Write-Enable
pulse.
The 28F256A is programmed on a byte-by-byte basis. Byte programming may occur sequentially or at
random. Following each programming operation, the
byte just programmed must be verified.
The 28F256A applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-Up
Erase/Erase.) Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g., Program Set-Up) to the command
register. Figure 5, the Quick-Erase algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F256A.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.
Set-Up Program/Program Commands
Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up operation.
Once the program set-up operation is performed,
the next Write-Enable pulse causes a transition to
an active programming operation. Addresses are internally latched on the falling edge of the Write-Enable pulse. Data is internally latched on the riSing
edge of the Write-Enable pulse. The rising edge of
Write-Enable also begins the programming operation. The programming operation terminates with the
next rising edge of Write-Enable, used to write the
I
The program-verify operation is initiated by writing
COH into the command register. The register write
terminates the programming operation with the rising edge of its Write-Enable pulse. The program-verify operation stages the device for verification of the
byte last programmed. No new address information
is latched.
The 28F256A applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 4,
the 28F256A Quick-Pulse Programming algorithm, illustrates how commands are combined with bus operations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.
Reset Command
A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH wili safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.
EXTENDED ERASE/PROGRAM
CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubledan expensive solution.
Intel has designed extended cycling capability into
its ETOX II flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
5-99
28F256A
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately
2 MV/cm lower then EEPROM. The lower electric
field greatly reduces oxide stress and the probability
of failure-increasing time to wear out by a factor of
100,000,000.
The 28F256A is capable of 100,000 program/erase
cycles. The device is programmed and erased using
Intel's Quick-Pulse Programming and Quick-Erase
algorithms. Intel's algorithmic approach uses a series of operations (pulses), along with byte verification, 'to completely and reliably erase and program
the device.
For further reliability information, see Reliability Report RR-60 (ETOX II Reliability Data Summary).
QUICK-PULSE PROGRAMMING
ALGORITHM
The Quick-Pulse Programming algorithm uses programming operations of 10 ,..,s duration. Each opera~
tion is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
5-100
performed with Vpp at high voltage. Figure 4 illustrates the Quick-Pulse Programming algorithm.
QUICK-ERASE ALGORITHM
Intel's Quick-Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick-Pulse Programming algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F256A is erased when shipped from the factory.
Reading FFH data from the device would immediately be followed by device programming. '
For devices being erased and reprogrammed, uniform' and reliable erasure is ensured by first pro"
gramming all bits in the device to their charged state
'(data = OOH). This is accomplished, using the
Quick-Pulse Programming algorithm, in approximately one-half second.
Erase execution then continues with an initial erase
operation. Erase verification (data = FFH) begins at
address OOOOH and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the .next
erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 5 illustrates the Quick-Erase algorithm.
I
28F256A
Bus
Operation
Command
Standby
Comments
Wait for Vpp ramp
to VpPH (= 12.0V)(1)
Initialize pUlse-count
Write
Set-Up
Program
Data = 40H
Write
Program
Valid address/data
Program(2)
Verify
Duration of Program
operation (tWHWH1)
Data = COH; Stops (3)
Program Operation
Standby
Write
Standby
tWHGL
Read
Read byte to verify
programming
Standby
Compare data output
to data expected
Write
Read
Standby
Data = OOH, resets the
register for read
operations.
Wait for Vpp ramp
toVppd1)
290243-5
NOTES:
1. See DC Characteristics for the value of VPPH and VPPL.
2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional)
after the register is written with the Read command.
3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Figure 4. 28F256A Quick-Pulse Programming Algorithm
I
5-101
28F256A
Bus
(!)peration
Command
Standby
Comments
Wait for Vpp ramp
to VpPH (= 12.0V)(1)
Use Quick-Pulse
Programming (Fig. 4)
Initialize Addresses,
Erase Pulse Width,
and Pulse Count
Write
Set-Up
Erase
Data = 20H
Write
Erase
Data = 20H
Erase
Verify(2)
Duration of Erase
operation (tWHWH2)
Addr = Byte to verify;
Data =i' AOH; Stops
Erase Operation (3)
tWHGL
Standby
Write
Standby
Read
Read byte to verify
erasure
Standby
Compare output to FFH
increment pulse count
Write
Standby
Read
Data = OOH, resets the
register for read
operations.
Wait for Vpp ramp
to Vppd1)
290243-6
NOTES:
1. See DC Characteristics for the value of VPPH and VpPL.
3. Refer to principles of operation.
2. Erase Verify is p~rformed only after Chip-erasure. A final
4. CAUTION: The algorithm MUST BE FOLLOWED to enread/compare may be performed (optional) after the regissure proper and reliable operation of the· device.
ter is written with the Read command.
Figure 5. 28F256A Quick-Erase Algorithm
5-102
I
28F256A
DESIGN CONSIDERATIONS
Vpp Trace on Printed Circuit Boards
Two-Line Output Control
Programming flash memories, while they reside in
the target smith, requires that the printed circuit
board designer pay attention to the Vpp pin power
supply trace. Use similar trace widths and layout
considerations given the Vee power bus. Adequate
Vpp supply traces and decoupling will decrease Vpp
voltage spikes and overshoots.
Flash memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power dissipation,
and
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control units, an address-decoder output should drive chip-enable,
while the system's read signal controls all flash
memories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power standby condition.
.
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current (Ieel issuesstandby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 fLF ceramic capacitor
connected between Vee and Vss, and between Vpp
and Vss.
Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 p.F electrolytic capacitor should be placed at the array's power supply
connection, between Vee and Vss. The bulk capacitor will overcome voltage slumps caused by printedcircuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.
Power Up/Down Protection
The 28F256A is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F256A is indifferent as to which power supply, Vpp or Vee, powers
up first. Power supply sequencing is not required.
Internal circuitry in the 28F256A ensures that the
command register is reset to the read mode upon
power up.
A system designer must guard against active writes
for Vee voltages above VLKO when Vpp is active.
Since both WE # and CE # must be low for a command write, driving either to VIH will inhibit writes.
The control register architecture provides an added
level of protection since alteration of memory contents only occurs after successful completion of the
two-step command sequences.
28F256A Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F256A does not consume any power to retain
code or data when the system is off. Table 4 illustrates the power dissipated when updating the
28F256A.
Table 4_ 28F256A Typical Update Power Dissipation(4)
Operation
Power DiSSipation
Notes
(Watt-Seconds)
Array Program/Program Verify
0.043
1
Array Erase/Erase Verify
0.083
2
One Complete Cycle
0.169
3
NOTES:
1. Formula to calculate typical Program/Program Verify Power = [Vpp x # Bytes x typical # Prog Pulses (tWHWH1 x
IpP2 typical + tWHGL X IpP4 typical)] + [Vcc x # Bytes x typical # Prog Pulses (tWHWH1 x ICC2 typical + tWHGL X
ICC4 typical)].
. .
.
2. Formula to calculate typical Erase/Erase Verify Power = [V (lpP3 tYPical x tERASE tYPical + Ipps typical x tWHGL X
# Bytes)] + [V CC(lCC3' typical x tERASE typical + Iccs typica x tWHGL X # Bytes)].
3. One Complete Cycle = Array Preprogram + Array Erase + Program.
4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots.
rp
I
5-103
28F256A
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Operating Temperature
During Read .................. O°C to + 70°C(1)
During Erase/Program ........... O°C to + 70°C
Temperature Under Bias ......... -10°C to
+ BO°C
Storage Temperature .......... - 65°C to
+ 125°C
Voltage on Any Pin with
Respect to Ground .......... -2.0V to
+ 7.0V(2)
Voltage on Pin Ag with
Respect to Ground ....... - 2.0V to
• WARNING: Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions"
may affect device reliability.
+ 13.5V(2, 3)
Vpp Supply Voltage with
Respect to Ground
During Erase/Program ..... - 2.0V to
+ 14.0(2, 3)
Vee Supply Voltage with
Respect to Ground .......... - 2.0V to
+ 7.0V(2)
Output Short Circuit Current ............. 100 mA(4)
NOTES:
1. Operating temperature is for commercial product defined by this specification.
2. Minimum De input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods less than 20 ns.
Maximum De voltage on output pins is Vee +0.5V, which may overshoot to Vee +2.0V for periods less than 20 ns.
3. Maximum De voltage on Ag or Vpp may overshoot to + 14.0V for periods less than 20 ns.
4. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING CONDITIONS
Symbol
TA
Vee
5-104
Limits
Parameter
Operating Temperature
. Vee Supply Voltage
Unit
Comments
70
°c
For Read-Only and
Read/Write Operations
5.50
V
Min
Max
0
4.50
I
28F256A
DC CHARACTERISTICS-TTL/NMOS COMPATIBLE
Symbol
Parameter
Limits
Notes
Min Typical(4)
Unit
Test Conditions
Max
III
Input Leakage Current
1
± 1.0
/-LA Vee = Vee max
VIN = Vee or Vss
ILO
Output Leakage Current
1
±10.0
/-LA Vee = Vee max
VOUT = Vee or Vss
lees
Vee Standby Current
1
0.3
1.0
mA Vee = Veemax
CE# = VIH
lee1
Vee Active Read Current
1
10
30
mA Vee = Veemax CE# = VIL
f = 6 MHz, lOUT = 0 mA
lee2
Vee Programming Current
1,2
1.0
10
mA Programming in Progress
lee3
Vee Erasure Current
1,2
5.0
15
mA Erasure in Progress
lee4
Vee Program Verify Current
1,2
5.0
15
mA Vpp = VPPH
Program Verify in Progress
lees
Vee Erase Verify Current
1,2
5.0
15
I)lA Vpp = VPPH
Erase Verify in Progress
IpPS
Vpp Leakage Current
1
IpP1
Vpp Read Current, 10 Current,
or Standby Current
1
90
IpP2
Vpp Programming Current
1,2
8.0
30
mA Vpp = VPPH
Programming in Progress
IpP3
Vpp Erase Current
1,2
4.0
20
mA Vpp = VPPH
Erasure in Progress
IpP4
Vpp Program Verify Current
1,2
2.0
5.0
mA Vpp = VPPH
Program Verify in Progress
Ipps
Vpp Erase Verify Current
1,2
2.0
5.0
mA Vpp = VPPH
Erase Verify in Progress
VIL
Input Low Voltage
-0.5
VIH
Input HighVoltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage
VID
Ag Intelligent Identifier
Voltage
liD
Ag Intelligent Identifier
Current
VPPL
Vpp During Read-Only
Operations
0.00
6.5
V
VPPH
Vpp During Read/Write
Operations
. 11.40
12.60
V
VLKO
Vee Erase/Write Lock Voltage
I
±10.0
200
/-LA VPP:S Vee
/-LA
±10.0
0.8
Vee
+
0.5
2.4
1,2
13.00
90
2.5
Vpp:S Vee
V
0.45
11.50
Vpp> Vee
200
V
V
IOL = 5.8mA
Vee = Vee min
V
IOH = -2.5 mA
Vee = Veemin
V
/-LA Ag
= VID
Note: Erase/Program are
Inhibited when Vpp = VPPL
V
5-105
28F256A
DC CHARACTERISTICS-CMOS COMPATIBLE
Symbol
Parameter
Limits
Notes
Min
Typical(4)
Test Conditions
Unit
Max
III
Input Leakage Current
1
±1.0
ILO
Output Leakage Current
1
±10.0
/LA Vee = Vee max
VOUT = VeeorVss
lees
Vee Standby Current
1
50
100
/LA Vee = Veemax
CE# = Vee ±0.2V
lee1
Vee Active Read Current
1
10
30
rnA Vee = Veemax CE# = VIL
f = 6 MHz, lOUT = 0 rnA
lee2
Vee Programming Current
1,2
1.0
10
mA Programming in Progress
lee3
Vee Erase Current
1,2
5.0
15
mA Erasure in Progress
lee4
Vee Program Verify Current 1,2
5.0
15
rnA Vpp = VPPH
Program Verify in Progress
lee5
Vee Erase Verify Current
1,2
5.0
15
rnA Vpp = VPPH
Erase Verify in Progress
Ipps
Vpp Leakage Current
1
IpP1
Vpp Read Current, ID
Current, or Standby Current
1
±10.0
90
200
/LA Vee = Vee max
VIN = Vee or Vss
/LA Vpp ~ Vee
/LA
Vpp >Vee
Vpp ~ Vee
±10.0
IpP2
Vpp Programming Current
1,2
8.0
30
mA Vpp = VPPH
Programming in Progress
IpP3
Vpp Erase Current
1,2
4.0
20
mA Vpp = VPPH
Erasure in Progress
IpP4
Vpp Program Verify Current
1,2
2.0
5.0
rnA Vpp = VPPH
Program Verify in Progress
IpP5
Vpp Erase Verify Current
1,2
2.0
5.0
rnA Vpp = VPPH
Erase Verify in Progress
VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
0.7Vee
VOL
Output Low Voltage
VOH1
Output High Voltage
0.8
V
+
0.5 V
Vee
0.45
V IOL = 5.8 rnA
Vee = Vee min
V IOH = - 2.5 rnA,
Vee = Vee min
0.85Vee
VOH2
IOH = 100 /LA,
Vee = Vee min
Vee -0.4
VID
Ag Intelligent Identifier
Voltage
110
Ag Intelligent Identifier
Current
5-106
,
11.50
1,2
13.00
90
200
V
/LA Ag
= VIO
I
28F256A
DC CHARACTERISTICS-CMOS COMPATIBLE (Continued)
Symbol
Parameter
Limits
Notes
Typical(4)
Min
Unit
Test Conditions
Note: Erase/Program are
Inhibited when Vpp = VPPL
Max
VPPL
Vpp During Read-Only
Operations
0.00
6.5
V
VPPH
Vpp During Read/Write
Operations
11.40
12.60
V
VLKO
VCC Erase/Write Lock Voltage
CAPACITANCE(3)
Symbol
2.5
V
T = 25°C, f = 1.0 MHz
Parameter
Limits
Notes
Min
Unit
Conditions
Max
CIN
Address/Control
Capacitance
3
6
pF
VIN = OV
COUT
Output Capacitance
3
12
pF
VOUT = OV
NOTES FOR DC CHARACTERISTICS AND CAPACITANCE:
1. All currents are in RMS unless otherwise noted. Typical values at Vcc = 5.0V, VPP = 12.0V, T
are valid for all product versions (Packages and Speeds).
2. Not 100% tested: characterization data available.
3. Sampled, not 100% tested.
4. "Typicals" are not guaranteed, but based on a limited number of samples from production lots.
AC TESTING INPUT/OUTPUT WAVEFORM
= 25°C. These currents
AC TESTING LOAD CIRCUIT
2..:3.!
..,..... 1 N914
2.4
INPUT
0.45
OUTPUT
__...x. . . . .x_t~ ~:~ :>
3.3k
TEST POINTS
290243-7
AC Testing: Inputs are driven at 2.5V for a logic "I" and 0.45 for a
logic "a". Testing measurements are made at 2.0 for a logic "I"
and 0.8 for a logic "0". Rise/Fall time,; 10 ns.
DEVICE
UNDER
TEST
CL ~ 100 pF
CL includes Jig Capacitance
i
--
OUT
cL =
100pF
290243-8
AC Test Conditions
Input Rise and Fall Times (10% to 90%) ...... 10 ns
Input Pulse Levels ................... 0.45 and 2.4
Input Timing Reference Level .......... 0.8 and 2.0
Output Timing Reference Level ......... 0.8 and 2.0
I
5-107
28F256A
AC CHARACTERISTICS
Read-Only Operations
Versions
28F256A-120
Notes
Symbol
Characteristic
Min.
Max
120
28F256A-150
Min
Unit
Max
150
tAYAy/tRC
Read Cycle Time
tELQy/tCE
Chip Enable Access Time
120
150
ns
tAYQy/tACC
Address Access Time
120
150
ns
tGLQy/tOE
Output Enable
Access Time
50
55
ns
tELQX/tLZ
Chip Enable to Output
in LowZ
2,3
tEHQZ
Chip Disable to Output
in High Z
2
tGLQX/tOLZ
Output Enable to Output
in LowZ
2,3
tGHQZ/tDF
Output Disable to Output
in High Z
2
tOH
Output Hold from Address,
CE # , or OE # Change
tWHGL
Write Recovery Time
before Read
0
0
55
ns
55
ns
0
0
30
1,2
ns
ns
35
ns
0
0
ns
6
6
p.s
NOTES:
1. Whichever occurs first.
2. Sampled, not 100% tested.
3. Guaranteed by design.
DEVIC[AND
Vee POWER-UP
STANDBY
ADDRESS SELECTION
ADDRESSES
OUTPUTS ENABLED
STANDBY
Vee POWER DOWN
ADDRESSES STABLE
/--------
er#
DATA VALID
t AVAV
(~c)
(E#)
tCLOV
(tOE)
~LOV (t CE )
(~~~)
---oj
t(LOX (~z)
DATA (DO)
s.ov
Vce
_ _H~IG;;.;.H.:.Z- - - : . . - - - - - - ( f ( f f i ( 1
J
L
'AVOV
VALID OUTPUT
(lAce)
OV
290243-9
Figure 6. AC Waveform for Read Operations
5-108
I
28F256A
AC CHARACTERISTICS-For Write/Erase/Program Operations(1)
Versions
28F256A-120
Notes
Symbol
Characteristic
Min
Max
28F256A-150
Min
Unit
Max
120
150
ns
0
0
ns
60
60
ns
50
50
ns
tAVAV/twc
Write Cycle Time
tAVWL/tAS
Address Set-Up Time
tWLAX/tAH
Address Hold Time
tOVWH/tOS
Data Set-Up Time
tWHOX/tOH
Data Hold Time
10
10
ns
tWHGL
Write Recovery Time
before Read
6
6
jLs
tGHWL
Read Recovery Time
before Write
0
0
p.s
tELWL/tCS
Chip Enable Set-Up
Time before Write
20
20
ns
tWHEH/tCH
Chip Enable Hold Time
0
0
ns
tWLWH/twp
Write Pulse Width
60
60
ns
tWHWL/twPH
Write Pulse Width High
20
20
ns
tWHWH1
Duration of
Programming Operation
3
10
10
p.s
tWHWH2
Duration of
Erase Operation
3
9.5
9.5
ms
tVPEL
Vpp Set-Up Time to
Chip Enable Low
2
1.0
1.0
p.s
2
NOTES:
1. Read timing parameters during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thereby eliminating the need for a maximum
specification.
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
28F256A-120
Notes
Min
28F256A-150
Typ
Max
Min
Unit
Typ
Max
Chip Erase Time
1,3,4
1
10
1
10
sec
Chip Program Time
1,2,4
0.5
3
0.5
3
sec
NOTES:
1. "Typicals" are not guaranteed, but based on a limited number of samples taken from production lots. Data taken at 25°C,
12.0V Vpp, at 0 cycles.
.
2. Minimum byte programming time excluding system overhead is 16 p.s program + 6 p.s write recovery), while maximum is
400 p.s/byte (16 p.s x 25 loops allowed by algorithm). Max chip programming is specified lower than the worst case allowed
by the programming algorithm since most bytes program significantly faster than the worst case byte.
3. Excludes OOH Programming Prior to Erasure.
4. Excludes System-Level Overhead.
5. Refer to RR-60 "ETOX" .II Flash Memory Reliability Data Summary for typical cycling data and failure rate calculations.
I
5-109
28F256A
99.9
,IV
/~
99
/
95
V
..f.l
..'
./ l
/
90
80
I
70
//
.
:
10
.,
/
.
/
20
. ..
//
/
60
50
40
30
"t'
o. 1
0.63 0.75 0.881.01.1 1.3
0.5
2.5
3.8
5.0
Chip Program Time (sec)
- - - 1 2 V : 10 kc; 23°C
..... _--_. 11.4V; 10 kc; 70°C
_
...... -
12V; 100 kc; 230(;
290243-10
Figure 7. 28F256A Typical Programming Capability
;
lB
/
1.6
,
.'
/
/
;
....- -'
1
~
5
1.0
/
fo· ...
;
/
0.75
,,
I
I
0.6
,
03
.'
/
os
o
10
20
30
40
50
I
,,
,
,,
,
,,
"
"
/
,-
V
J
,,
/
V
60
70
TE~P
(OC)
eo
90
100
110
120
130
- - l k Cycles
---- .. 10k Cycles
•• _- lOOk Cycles
290243-11
Figure 8. 28F256A Typical Program Time at 12V
5·110
I
28F256A
99.9
1/
99
1/, ,,' ..
I ,.
90
80
70
'"
"
=>
u
,
,'/
/ ,, .
/
95
~
/
/ ,
/
60
50
40
V
I
20
,.
,'.'
/
30
'/
I
,'/
'
.
V .~"
/ '.
10
I
j,,' ;
I'
//
28F256A-120/150
I.
,'/
I I III
I'
0.1
~-200
0.3
0.5
0.7
2
345678910
20
CHIP ERASE TIME (sec)
- - - 12V; 10 kc; 23°C
- _ ... -
11.4V; 10 kc; DOC
-- ...... ---12V: 100 kc; 23°C
290243-12
Figure 9. 28F256A Typical Erase Capability
1.8
1.6
\
,
,
1.4
.!
I',
1.2
,
""'>= 1.0 ,
"''"
g
a.
:;: 0.8
u
,,
,,
"- r---.. "
,,
......
,,
,
"
"
"- "- "
0.6
"t'-.
"
............... , "
"
r-.... ........ ........
r-:: -.
0.4
0.2
o
10
20
30
40
"
50
60
70
80
90 100 110 120 130 140
TEMP (OC)
- - l k Cyclos
.... --. 10k Cycles
....--- lOOk Cycles
290243-13
Figure 10. 28F256A Typical Erase Time at 12.0V
I
5-111
'!:.
N
(XI
."
N
~
I\)
Vee POWER-UP &
STANDBY
SET-UP PROGRAM
COMMAND
PROGRAM COMMAND
LATCH ADDRESS & DATA
PROGRAMMING
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
en
en
STANDBY/
VCC POWER-DOWN
»
ADDRESSES
"TI
cO·
...
1
CE# (E#)
C
4150H, loop and wait
for host (the link probably went down during
update);
4. When "HOST_INT" is active, vector to
host interaction code.
(See next section.)
292046-9
Figure 6. Example of ISW Integration to the Boot Sequence
An alternative to storing these routines in a separate
boot device is storing them in the flash memory containing the program code. Prior to erasure, the CPU
would transfer the ISW routines to system RAM and
execute from there. This type of approach is suitable for
battery-operated equipment or systems with back-up
power supplies.
The communication link could be disrupted during reprogramming, leaving the device in an unknown configuration. Therefore, the boot code should reset the flash
memory and check two ISW flags. The following section discusses the flag check concept.
4.1.1 ISW FLAG CHECK
After resetting the flash memories and initializing other
system components, the CPU should check the communications link for a host interrupt. We will call this
the HOST_INT flag. Had the communication link
gone down prior to completion of downloading, then
the host would have to re-establish contact to complete
the task.
Assuming no HOST_INT request has been made, the
boot protocol then checks a data sequence in the flash
memory signifying a valid application (VALID~P).
You program this sequence into the memory array after
confirmation of a successful download. If a download is
interrupted midway through erasure or programming,
then the VALID~P flag locations will not contain
the VALID~P code. On the next system bootstrap
the CPU recognizes this and holds up system boot until
valid code is programmed. In Figure 6 an example flag
protocol uses the VALID~P sequence of 4150H
(ASCII codes for "AP").
4.2 Communication Protocols and
Flash Memory ISW
structions and program code. This protocol can be as
simple as a read-back technique or as complex as an
error-free transmission protocol. (See Figure 7 for possible system-level flash memory instructions.)
A simple read-back technique optimizes download for
boot code memory needs and ease of implementation.
The embedded CPU echoes the flash memory instruction (i.e., Erase or Program) to the host, and waits for a
confirmation prior to execution. After programming
the update, the remote system checks the update by
transmitting it back to the host for confirmation. The
remote system then programs the VALID_AP sequence. Note that programming and reading back
64 Kbytes at 19.2K baud takes about 0.57 minutes per
direction:
(65,536 bytes) • (10 bits/byte) • (1 sec/19.2 Kbits) •
(1 min/60 sec) = 0.57 minutes.
Implementing either soft~are- or hardware-based error-free communications protocol improves transmission efficiency. It eliminates the possibility of errant
data being programmed if not buffered and checked,
and optimizes the download process for transmission
time. Additionally, file compression and decompression
routines can improve the transmission rate.
General ISW Instructions Include:
STATUS CHECK
INITIATE REPROGRAMMING
MOVE ISW ROUTINES FROM FLASH MEMORY TO RAM
(If not resident In separate boot memory)
Data accumulation-specific commands Include:
RETRIEVE DATA
ERASE FLASH MEMORY
Figure 7. Sample System-Level
ISW Instruction Set
The remote download. communications protocol must
guarantee accurate transmission of flash memory in-
5-128
I
AP-316
Status Check
The host should request a status update from the remote system prior to sending a reprogramming instruction. Depending on the response, the host may break
the link and reconnect later, or it may send an erasure
or data-upload command. This type of handshaking is
necessary when system downtime for reprogramming
might not be acceptable. An example of this is an automated factory where robots handle caustic chemicals.
4.3 Data Accumulation Software
Techniques
Data can be accumulated in a remote environment with
flash memory and then uploaded to a host computer for
manipulation. You can adapt various standard datalogging techniques for use with flash memory. With
any technique, you determine the next available memory location by reading for erased data (OFFH). This
address would only be located once on system bootstrap and then recalled from RAM and incremented as
needed.
Given a repeating data string of known length and
composition, program start and stop codes at either end
of the string. Do not pick ooH or OFFH data for these
codes because they are used during erasure. The start
and stop codes enable the CPU to differentiate between
available memory for logging and logged data equal to
ooH orOFFH.
For non-regular data input, you can address this same
issue by programming the logged data followed by the
variable identifier. Again, do not pick DOH or OFFR
data for the variable identifiers.
With any technique, the host computer separates and
manipulates the data after the uploading operation.
4.4 Reprogramming Routines
Intel's ETOX flash memories provide a cost-effective
updatable, non-volatile code storage medium. The reliability and operation of the device is based on the use of
specified erasure and programming algorithms.
Intel offers reprogramming software drivers to make it
easy for you to design and implement flash memory
applications. The software is designed around the CPUfamily architectures and requires minimal modification
to defme your system parameters. For example, you
supply the memory width (8-bit, 16-bit, or 32-bit), system timing, and a subroutine for control of Vpp.
I
NOTE:
Contact your nearest sales office for details.
If you prefer to implement the algorithms yourself, they
are outlined in the device data sheets. Command register instructions required for the various operations are
included in the data sheet flow charts.
The following sections describe both single-device and
multiple-device parallel reprogramming implementations.
4.4.1 Quick-Erase Algorithm
Flash memories chip-erase all bits in the array in parallel. The erase time depends on the Vpp voltage level
(ll.4V -12.6V), temperature, and number of erase/
write cycles. on the part. See the device data sheets for
specific parametric influences on reprogramming times.
Note that prior to erasing a flash memory device the
processor must program all locations to OOH. This equalizes the charge on all memory cells insuring uniform and
reliable erasure.
Algorithm Timing Delays
The Quick-Erase algorithm has three different time delays:
1) The fIrSt is an assumed delay when Vpp first turns
on. The capacitors on the Vpp bus cause an RC
ramp. After switching on Vpp, the delay required is
proportional to the number of flash memory devices
times 0.1 ,....F/device. Vpp must reach its final value
100 ns before the CPU writes to the command register. Systems that hardwire Vpp to the device can
eliminate this delay.
.
2) The second delay is the "Time Out TEW" function,
where TEW is the erase timing width. The function
occurs after writing the erase command (the second
time) and before writing the erase-verify command.
The erase-verify command or the integrated stop
timer internally stops erasure.
TEW for ETOX II flash memories is a minimum of
10 ms. This delay can be either software or hardware controlled. Either way, the minimum nature of
the timing specification allows for interrupt-driven
timeout routines. Should the interrupt latency be
longer than the minimum delay specification, the
stop timer halts erasure.
3) The third delay in the erase algorithm is a 6 ,....S time
out between writing the erase verify command and
reading for OFFR. During this delay, the internal
voltages of the memory array are changing from the
5-129 .
AP-316
erase levels to the verify levels. A read attempt prior
to waiting 6 /ks will give false data-it will appear
that the chip does not erase. Repeatedly trying to
erase verify the device without waiting 6 /kS will
cause over-erasure. This delay is short enough that
it is best handled with software timing. Again, note
that the delay specification is a minimum.
High Performance Parallel Device Erasure
In applications containing more than one flash memory, you can erase each device serially or you can reduce
total erase time by implementing a parallel erase algorithm.7 You save time by erasing all devices at the same
time. However, since flash memories may erase at different rates, you must verify each device separately.
This can be done in a word-wise fashion with the command register Reset command and a special masking
algorithm.
Take for example the case of two-device (parallel) erasure. The CPU first writes the data word erase command 2020h twice in succession. This starts erasure.
After 10 ms, the CPU writes the data word verify command AOAOh to stop erasure and setup erase verifica-
tion. If both bytes are erased at the given address, then
the CPU increments the address (by 2) and then writes
the verify command AOAOh again. If neither byte is
erased, then the CPU issues the erase sequence again
without incrementing the address.
Suppose at the given address only the low byte verifies
FFh data? Could the whole chip be erased? The answer
is yes. Rather than check the rest of the low byte addresses independently of the high byte, simply use the
reset command to mask the low byte from erasure and
erase verification on the next erase loop. In this example the erase command would be 20FFh and the verify
command would be AOFFh. Once the high byte verifies
at that address, the CPU modifies the command'back
to the default 2020h and AOAOh, increments the address by 2, and writes the verify command to the next
address.
See Figure 8 for a conceptual view of the parallel erase
flow chart and Appendix D for the detailed version.
These flow charts are for l6-bit systems and can be
expanded for 32-bit designs.
RAISE Vpp
PROGRAM ALL DEVICES TO OOh
RESET ALL VARIABLES
ISSUE ERASE COMMAND - - - - - - - - - - ,
TIME OUT
VERIFY COMMAND
[
.
BOTH DEVICES ERASED
I
Y
N LAST ADDRESS
IY
DONE
~
MASK'
HI-OR LO-BYTE
COMMANDS
LAST PULSE
.!:!-
IY
ERROR
'YOU MASK THE DEVICE BY SUBSTITUTING A RESET COMMAND
FOR THE ERASE & VERIFY COMMANDS. THAT WAY THE
ERASED BYTE IDLES THROUGH THE NEXT ERASE LOOP.
292046-28
Figure 8. High Performance Parallel Erasure (Conceptual Overview)
7. Parallel Erasure and Programming require appropriate choice of Vpp supply to support the increased power consumption.
5-130
I
AP-316
4.4.2 Quick-Pulse Programming Algorithm
Flash memories program with a modified version of the
Quick-Pulse Programming algorithm used for U.V.
EPROMs. It is an optimized closed-loop flow consisting of JO /Ls program pulses followed by byte verification. Most bytes verify after the first pulse, although
some may require more passes through the pulse/verify
loop. As with U.V. EPROMs, this algorithm guarantees a minimum of ten years data retention. See the
device data sheets for more details on the programming
algorithm.
Algorithm Timing Delays
The Quick-Pulse Programming algorithm has three different time delays:
• The first and third-Vpp set-up and verify set-up
delays-are the same as discussed in the erasure section. In this case the third delay is for the transition
between writing the Program Verify command and
readiti.g for valid data.
• The second delay is the "Time Out JO /Ls" function,
which occurs after writing the data and before writing the program-verify command. This write command internally stops programming. The section entitled "Pulse Width Timing Techniques" gives 86family assembly code for generating a JO /Ls timer
routine.
High Performance Parallel Device Programming
Software for word- or double-word programming can
be written in two different manners. The first method
offers simplicity of design and minimizes software overhead by using a byte programming routine on each device independently. Here you increment the address by
2 or 4 when addressing 1 of 2 or 4 devices, respectively.
The second method offers higher performance by programming the word or double-word data in parallel.
This method manipulates the command register instructions for independent byte control. See Figure 9
for conceptual 2-device parallel programming flow
chart and Appendix E for the detailed version.
Ad:r~::/~a'la
Get
Word
Reset Command and
Counter Variables
Program Data
Word
~
+_-----_-----.,
1
Timeofl0"'s
Stop Programming with
Program Verily command
1
N
Mask HI or Lo Byte
Data Word Programmed?--+Increment Pulse Counter
y Last Pulse?
N
1
"' ':'r' I
Write Read command Write Read command
Lower Vpp
Lower Vpp
Programming Complete
Program Error
292046-1t
'You mask the device by substituting a Reset command for the Program and Verify commands. That way, the programmed bytes do not get further programmed on subsequent pulses.
Figure 9. Parallel Programming Flow Chart (Conceptual Overview)
I
5-131
AP-316
NOTE:
Word or double-word programming assumes 2 or 4
8-bit flash memory devices.
LOOP instruction takes 16 clock cycles to execute per
pass. It decrements the CX register on each pass and
jumps to the specified operand until CX equals zero.
Parallel Programming Algorithm Summary:
When writing a delay loop consider all instructions be·
tween the start and end of the delay. If a macro is
written that delays 10 ,...s, add the clock cycles for all
instructions in the macro.
• Decreases programming time by programming 2
flash memories (16 bits) in parallel. The algorithm
can be expanded for 32-bit systems.
• Eliminates tracking of high/low byte addresses and
respective number of program pulses by directing
the CPU to write data-words (16-bit) to the command register.
• Maintains word write and word read operations.
Should a byte on one device program prior to a byte
on the other, the CPU continues to write word-commands to both devices. However, it deselects the
verified byte with software commands. An alternative is to independently program high and low bytes
using hardware select capability.
Here is an example of a 10 ,...S delay and the calculation
of the constant required for a 10 MHz 80C186.
WAIT_1O ,...s:
push cx
mov cX,DELAY
loop $
pop ex
1. Start to End
10 ,...s/cycle time
10 ,...s/Ioo ns
100 cycles
4.4.3 Pulse Width Timing Techniques
Software or hardware methods can be used to generate
the timing required for erasure and programming. With
either method you should use an in·circuit emulator
(ICETM) and an oscilloscope to verify proper timing.
Also remove the flash memory device from the system
during initial algorithm testing.
; 10 clock cycles
;4 clock cycles
;see calculation
; 10 clock cycles
2. Loop Instruction = 100-24 cycles
= 76 cycles
3. Loop Cycles
= 76
=
(IS X [DELAY -1]
4. Solving for DELAY
=
+ 5)
6
Software Methods and Examples
Software loops are easily constructed using a number of
techniques. Timing loops need to be done in assembly
language so that the number of clock cycles can be
obtained from the instructions.
In order to calculate a delay loop three things are neededI) processor clock speed,
2) clock cycles per instruction, and
3) the duration of the delay loop.
As an example, the 80Cl86 divides the input clock by
2. With a 20 MHz input clock the processor's internal
clock runs at 10 MHz. This translates to a 100 ns cycle
time. Delays can be made by loading the CX register
with a count and using the LOOP instruction. The
5-132
Hardware Methods
Using an Internal TimerMany microcontrollers and some microprocessors have
on-chip timers. At higher input clock speeds these internal timers have a resolution of I ,...S or better. The
timers are loaded with a count and then enabled. The
timer starts counting and when it reaches the terminal
count a bit is set. The CPU executes a polling algorithm
that checks the timer status. Alternatively, a timer-controlled interrupt can be used. After the timer has been
set and the interrupt enabled, the CPU can be programmed to wait in idle mode or it could continue executing until the timed interrupt.
I
AP-316
One thing to take into account when using interrupts is
the time required for the CPU to recognize and interrupt request (interrupt latency). This is important when
figuring the timer value, because the time seen by the
part will be the programmed delay plus the minmum
interrupt latency time.
The 80CI86 has three 16-bit timers on-chip. Timer #2
can be a prescaler for the other two timers, which extends timers #0 and # I range out to 2 A 32. By using
two timers, 10 /los pulses and 10 ms pulses can be easily
achieved.
Using an External TimerExternal timers can take many fonns. One popular example is the 82C54 (CHMOS Programmable Interval
Timer) which has three 16-bit timers on-chip. One timer can be used as a prescaler for the others so that a
count of 2'32 can be achieved as with the 80CI86 internal timers.
5.0 SYSTEM DESIGN EXAMPLE:
AN 80C186 DESIGN
A general purpose controller and/or data acquisition
system was built to demonstrate 86-based ISW. The
80CI86 CPU drives the system, which contains
16 Kbytes of EPROM (two 27C64's), 64 Kbytes of
flash memory (two 28F256A's), 64 Kbytes of SRAM
(two 32K x 8's) three 8-bit ports (82C55A), one serial
port (82510), and a 5V to 12.0V DC/DC converter.
Three 74HC573's demultiplex the address/data bus
and latch the byte high enable line (BHE#) and the
status lines (if needed). Two data transceivers
(74HC245) simulate the worst case data path for a system requiring added drive capability. If the transceivers
are not needed they can be replaced with wired headers.
See Appendix F for detailed schematics parts list, and
changes for the 28F512 or 28FOlO.
The 80CI86 reset (output) drives the reset input on the
82510, 82C55A, and the OE# inputs on the address
latches and data transceivers. The reset line goes inactive 5 clock cycles before the first code fetch. Also, the
CPU's write signal is split into byte-write-high and
byte-write-low to allow for byte or word writes.
The 80CI86 has on-chip memory and peripheral chip
selects. Two of the memory chip selects are dedicated.
One is the Upper Chip Select (UCS#, dedicated for the
boot area) and the second is the Lower Chip Select
(LCS #, for the interrupt vector table area). See the
memory map in Figure 10.
I
Boot
UCS
FCOOOH
Application
MCSO
Version update code,
Data Accumulation storage,
etc.
40000H
RAM
LCS
Initialize H/W, Comm,
flash memory algo's, etc.
Vector table, Stack,
Buffers, etc.
0000
Figure 10. 80C186 Memory Map
The pennanent code was placed in an EPROM in the
UCS memory segment; this code includes routines for
hardware initialization, communications, data uploading and downloading, erasure and programming algorithms, I/O drivers, ASCII to binary conversion tables,
etc. This would be useful for systems reconfigured for
different communication protocols as the last step prior
to shipment.
Code and constants that might change are placed in the
64 Kbytes of flash memory. Application examples include operating systems, code for rapidly advancing
biomedical technologies such as blood test software, engine-control code and parameters, character fonts for
printers, postage rates, etc. The RAM is used for the
interrupt table, stack, variable data storage, and buffers.
The three 8-bit ports on the 82C55A peripheral controller can be used for control and/or data acquisition.
It powers-up with all port pins high. Similarly, all port
pins go high after wann resets as well. Because the pins
are high after a power-up/reset, an open collector invertor was used to control the MOSPOWER switch
which in turn controls Vpp. You must drive the FET
switch to one rail or the other to guarantee its low onresistance. Vpp is turned off during power-up or reset
as a hardware write protection solution. The DC/DC
converter supplies Vpp.
The 82510 is a flexible single channel CHMOS UART
offering high integration. The device off-loads the system and CPU of many tasks associated with asynchronous serial communications.
5-133
Ap·316
The part can be used as a basic serial port for the host
serial link, or can be configured to support high speed
modern applications. For more information on the
82510 see the 82510 data sheet and AP-401 "Designing
with the 82510 Asynchronous Serial Controller".
Software was written to download code and data pa- .
rameters (code updates) from a PC to the demo board
through the PC's COMI port (serial port). The system
also can upload data (remote data acquisition) to the
PC via the same link.
Once the download code and data has been programmed it can not be lost, even if power should fail.
This is because Intel's ETOX II flash memory technology is based on EPROM technology and does not need
power to retain data.
.
6.0 SUMMARY
Intel's flash memories offer designers cost-effective al"
ternatives for remote version updates or for reliable
data accumulation in the field or factory. Designers will
also benefit from time savings in any kind of code development-no 15 minute waits for U.V. EPROM erasure.
This application note covers the basics of in-system
writing to flash memories and can be used as a check
list for systems other than the 80C186 design shown.
The basic concepts remain the same: a CPU controls
the reprogramming operations; a 12V supply must be
applied to the flash memory for erasure and programming; and a communications link connects the host to
the remote system and supplies the code to be programmed.
The end result: rugged, solid state, low power nonvolatile storage.
5-134
I
AP-316
APPENDIX A
ON-BOARD PROGRAMMING DESIGN
CONSIDERATIONS
I
5-135
AP-316
INTRODUCTION
On-board programming! (OBP) with Intel's flash
memory provides designers with cost reduction capabilities for alterable code storage designs. When used in
conjunction with on-board programming, flash memory presents opportunities for savings in two areas:
greater testability in the factory, which translates to
improved outgoing quality and reduced return rate; and
quicker, more reliable field updates, which translates to
decreased product support cost.
This appendix:
• outlines the design considerations associated with
on-board programming, and the improvements afforded by Intel's flash memory;
• offers guidelines for converting current 64K
EPROM OBP designs;
• designs an 8-bit system for on-board programming;
• suggests some l6-bit flash design considerations;
and offers information on OBP equipment and vendors.
1. With on-board programming, non-volatile memory is programmed while socketed or soldered on the application board,
rather than before hand as a discrete component. This programming method is also called in-module or in-circuit programming, and has been practiced by some major corporations since 1981. See sidebar on following pages for more information
on U.v. EPROM OSP usage.
HOST APPLICATION
(Printer Shown Here)
BOARD-PROGRAMMER
< )
292046-29
On-Board Programming Manufacturing Example-A printer is customized via OBP for international markets:
1. printer assembly completed, diagnostics code programmed and tested, and unit stored in inventory; 2. order
arrives for printer with foreign language font; 3. diagnostics code flash-erased, and desired font programmed; 4.
printer ships to customer.
INTEL'S FLASH MEMORY-DESIGNED
TO MEET YOUR OBP NEEDS
5 Volt Vee Erasure and Programming
Verification
Intel's flash memory simplifies OBP code updates by
offering designers the command register architecture.
As described in section 2.2, this architecture offers the
full reliability of EPROM off-board programming
without the hassles of elevating Vee.
Unlike EPROM OBP, flash memory enables Vcc to
remain at 5.0V throughout all operations. Internal circuitry derives the erasure and programming verification
levels from the voltage on Vpp rather than from Vcc.
These verify modes enable use of a single Vcc bus for
the entire board, as opposed to the two buses needed for
U.V. EPROM OBP. (See sidebar entitled EPROM
OBP).
5-136
I
AP·316
REPLACING CURRENT EPROM OSP
DESIGNS WITH FLASH MEMORY
WE# lines can be common if the board programmer
can give the appropriate timings to either type of device.
Hardware Considerations
Software Considerations
A slight hardware modification is required to adapt
most of the current EPROM OBP designs for use with
Intel's flash memory. Simply convert the EPROM
memory sites from 28 to 32 pins. All other board-design cirteria used for EPROM OBP apply to flash
memory as well. (For discussions of these criteria see
section entitled New OBP Designs).
Standard EPROM OBP requires the board designer to
bus PGM # to the edge connector. With flash memories' command register architecture, this same trace enables electrical erasure and programming, only now the
line is called Write Enable (WE#). The timing for
WE# is similar to that of read accesses, although that
is handled via software changes.
Another potential hardware change is on the board
programmer side of the design-the Vpp supply. Many
EPROMs program with l2.S-13.0V Vpp supplies. Intel's ETOX II flash memory requires llA-l2.6V Vpp.
This change should not be an issue since the Vpp supply on many board programmers is programmable.
Mixed memory systems containing both conventional
U.V. EPROM and flash memories require special consideration. This type of memory design requires separation of the Chip Enable (CE#) control lines between
the EPROM and flash devices to allow for independent
reprogramming control and access. The PGM # and
Manufacturers who program EPROMs on-board today
will need new board-programmer software to take advantage of flash memory's feature set, specifically software for the Quick-Erase and Quick-Pulse Programming algorithms.
Benefits of Converting Your EPROM OBP
Design to Flash
The most pressing reason to convert from a standard
EPROM to flash memory is the total cost savings. To
appreciate this, you must consider your way of doing
business at the board and system levels-from the factory to installation and repair in the field. In the factory, boards can be tested with a diagnostics program in
the flash memory and then erased and reconfigured for
shipment in the same step. Improved testing will decrease the probability of field failures and costly customer returns. Simplified test and rework methods will
decrease your inventory holding costs. Also, if in the
process of converting to flash memory you include the
ability to OBP via a cable-connector, service calls for
code updates will be quicker, more reliable, and cost
less money. Your serviceman would simply connect the
programming equipment to the system without dismantling it to remove the EPROMs. (See section entitled
The System/Board-Programmer HIW Connection for
details.)
EPROMOBP(Corif'c:i)
i~volves
traceS'~o,the bOa~d's ed~e connector~ne for,EPRO¥:
. this'jssue
running separate Vcc
and one~f~~powering up the rest of the' board.
,A
' , . "'.' '
secibnd;consideratjQri'wh¢ri'qe~ignmgf~r EPROM OBPhaSbe~accessing m~ufacturer aild'devicecodes.
:t
~
,'(,I'"
'
\
,,'
,.
,
'
;
,
,
The'iite~tffi~r mode ~e4uiresforCing A9 to 12V.Thist~anslai.:sJo ,adding extra isolation; which implies tIili'"
,incr~;;~9sts of buffe.rs atld.e;xtra board space.
I
5-137
AP-316
NEW OSP DESIGNS
Design Considerations
As with EPROM in-circuit programming, flash memory board programming requires the use of a board-programmer. Unlike U.V. erasure for standard EPROM
OBP, electrical erasure enables flash memory OBP
without removing the board from the system.
We will look at designing a board that is to remain powered-up in the system during erasure and reprogramming. The key concept is to design the board in such a
way that the programmer can take control of the system
during code updates. The implementation of such a design is straightforward, easy, and suited to automated
production assembly.
Taking Control
The board-programmer needs to take control of the
system's address bus, data bus, control lines, etc. to
update the code without damaging the system. (See
Figure 2. System to Board-Programmer Interface.)
Taking control simply means isolating the rest of the
system from these lines.
Various methods of isolating the memory from the system include using tristate buffers, latches, or even the
capabilities designed into microprocessors (/LP) and microcontrollers (/LC). For example, Intel's 86-based /LP
family has HLD/HLDA signals that were set-up for
multiprocessor system designs where bus control is a
major concern. The HLD signal, when acknowledged,
tristates the address, data, and control lines. Although
not designed for multiprocessor environments, Intel's
MCS®-51 and MCS-96 microcontroller families have
Reset capabilities to help simplify this same task.
One issue to be aware of when using a CPU's reset
control function is that it may switch from the reset to
active condition at a non-standard logic level. This only
presents a problem if the addressldata buffer takes
longer to activate than the CPU, and the CPU attempts
to fetch code from a memory device isolated from it.
One approach to insure successful programming takeover (i.e. without bus contention) is to have the boardprogrammer's lines in a high impedance state during
connection to the system. Once connection to the system has been secured, the serviceman could hit a button
on the board-programmer to start the system takeover
procedure. Then when total control has been established, the programmer would commence with erasure
and reprogramming.
Aside from the flash device's isolation from the system,
various CPU control lines (MEMRD#, WE#,
PSEN #, etc.) may need isolation as well. If active during Reset, these lines may put the CPU into an upspecified state. When designing a board for OBP, check the
/LCI/LP data sheets carefully for any special reset conditions.
Printed Circuit Board Guidelines for
Vee and Vpp
Programming conventional EPROM and flash memories takes 30 rnA of current on Vee and Vpp, due to
the nature of hot-electron injection. Most of the charge
transfers to the memory cell's floating gate in a short
current spike during the first pulse. You should design
both the Vee and Vpp traces with A.C. current spikes
in mind. Wherever possible, limit the inductance by
widening the two traces. Bypass capacitors (0.1 /LF)
should be placed as close as possible to the memory
device's Vee and GND pins, as well as the devices Vpp
and GND pins. The capacitor on Vcc decreases the
power supply droop. The capacitor on Vpp supplies
added charge, and filters and protects the memory from
high frequency over-voltage spikes2.
2. For a complete discussion of electrical noise, grounds, power supply distribution and decoupling see Ap-74-High Speed
Memory System Design Using the 2147H, and AP-125-Designing Microcontroller Systems for Electrically Noisy Environments.
Oii~ SUbtl~col1trefn\:;ith £PRGM.OBPfthht' d~sigh~;9{tehoverlQl)k isp.V; bOar~'~1\~~c ..
-tr.v; ~pkOM';d ·~ur~ ~;qJr~ '~:o;n:d'fr9m'i~· sr.s~$tetn::TI1i~ inc~
or:. . ;. ,
.' ility risks
a s'y'$tem. ..
. .'
., decteasesthesecosts'byenabliiiga' gftiater :degrek! oftiiCro¥y automation, :andincreases,the flmbilify1lffol'ded.bY:
: cOsts'.orlabOt, lower yieldS duetb41ari1tling;:and ,thel
, bu~ isolation control of PSEN# and the data bus.
5-140
I
--
RESET
n
PSI
I I
MEMEN#
I
CE#
i
€:
®
II
J.
II
CE#
AO-A14
A15
AO-~4
28F256A
IWE#
DO-~
I Vpp
1 ~MEMWR
PS2
MEMRD#
OE#
I
CE#
~-+---II AO -A14
OE#
WE#
Programmer
--4-----1
Edge
1-1
Connector
Vpp
28F256A
/
•
I--..--
11
IDo-~
DO-D7
r-=
~
~
GND
....
292046-31
»
...enl'
c.:I
Ap·316
This is accomplished as illustrated. When AI5 is low,
the lower 32K bytes are selected. The output of the
inverter drives the other 28F256A's chip enable. This
type of memory architecture promotes power savings
by disabling all memories but the one being addressed.
To accomplish this two-line memory control architecture, route the inverter's input AI5 to the 80C31 and to
the programmer ip.terface connector. 8 The board-programmer controls the inverter's output enable with
MEMEN#.9 The MEMEN# line performs the function normally performed by CE# in component programming. When driven to a logic "I" level
MEMEN # pulls the inverter's output high. This deselects all memory devices controlled by that I.C. During
normal read and standby operations, the pull-down on
MEMEN # keeps the decoder enabled.
Era~ure
and Programming Control Circuitry
In this design, Vpp and WE# are active only during
reprogramming. At other times, the two inputs would
be inactive. Simply tie the WE# line to Vee through a
pull-up resistor. The pull-up limits the current to the
board programmer during reprogramming. (Recall that
WE# is active low.) Flash memories allow Vpp to be at
12V, Vee or ground for read operations. This design
ties Vpp to Vee through a diode and resistor to allow
for EPROM OBP compatibility. If this option is not
required, simply tie Vpp to ground through a currentlimiting pull-down resistor.
Returning Control to the Host System
The board-programmer should return system-control
to the host processor in an organized manner. First it
should lower Vpp from 12V to 5V, or ground. Then the
board programmer should place its address and data
buses into a high impedance state. Next PS2, which
controlsMEMWR should be tristated thus disabling
the PSEN # / Address latch isolation. Finally the boardprogrammer should" switch PSI, which drives the RESET line to reactivate the ,...C. This sequence guarantees that the ,...C will begin operation at a known program code location.
16-BIT BUS DESIGN
CONSIDERATIONS
An example of an On-Board programmable 16-bit system board would be an 80CI86 microprocessor, two
28FOlO flash memories, RAM, and some glue chips.
The basic hardware design considerations would be the
same as those in the previously discussed 8-bit bus example.
There are a few issues with 16-bit designs that do not
arise in 8-bit designs. For the programmer to take control of the system, it must tristate and reset the ,...p as
well as tristate the bus buffers and latches. The HOLD
and RESET lines of Intel's 86-based family of microprocessors have been designed with bus isolation in
mind for use in multiprocessor systems.
The designer has two options 'for erasing and programming the high and low bytes of the flash memory array
independently.
'
1) The designer can route two WE# lines to the programmer connector-BYTE HIGH WE#' and BYTE
LOWWE#.
2) The reprogramming software can follow the masking
procedure shown in section 4.4. This method' allows a
common WE# line for the high and low bytes.
S. Note the lack of isolation buffers between the SOC31 's high order addresses (Port 2) and the board-programmer interface,
compared to the latch separating the low order addresses (Port 0) and the interface. In this design example, we make,use of
the SOC31's ability to tristate these ports, so no isolation is needed for any of the addresses. The latch on Port 0 is for the
time-multiplexed address/data architecture of this microcontroller, and not specifically for isolation.
9. MEMEN = memory enable, active low.
5-142'
I
AP-316
'"co
I
~
_
__
0",,,,,
... _
,,, _
• .,
I')
NN
___
_
r~,
- •••• ,II
~I
~
~,!!~"rfrf'ftf
.,'"g
~..
a;><
'a
~
j
J'
U
Decreased board costs and improved reliability
from elimination of EPROM sockets;
< > Decreased manufacturing costs from elimination
of board eraser depreciation costs, recurring U.V.
light bulb and energy expenses;
< > Decreased inventory expense from simplified test
and rework methods (one-step diagnostics, erasure, and board configuration);
< > Decreased product costs based on decreased
board-handling loss;
< > Improved board diagnostics and testability leading
to higher quality and decreased customer returns;
and
< > Quicker, more reliable field code updates.
I
Ap·316
APPENDIX B
Vpp GENERATION CIRCUITS
Circuit
Circuit
Circuit
Circuit
Circuit
Circuit
# I-Regulation from a higher voltage
#2-Regulation from a higher voltage
# 3-Regulation from a higher voltage
#4-5V to I2V Boost
#5-5V to I2V Boost
# 6-Monolithic DC/DC Convertor
For more detailed information on Vpp generation circuits, see AP-357 titled Power Supply Solutions for Flash
Memory (Order Number 292092).
Circuit.#1
Down Conversion
(From 14.0V-26.0V to 12.00V)
Vln)-~Hln
Vee
Out
H,....-.....-o
LM2391CT
Rl
R3
OnlOff
VPP •
Gnd
Vout
Ad]
J.+--=:r--r--""""[I::
. ;:: ::::'C2
-
Enabler
R2
"== Lr-V~~t-;;'-1~20;(RliR2-:;-1)-1
_____________________________
.J
292046-12
COMPONENTS
COST"
LM2391CT
R1 = 20 K!1, 1%
R2= 180 K!1, 1 %
R3 = 10K!1
C1 = 0.1/-,F
C2 = 100/-,F
$0.75
0.045
0.045
0.02
0.02
0.15
$1.03
NOTES:
-The LM2391 offers an enable pin for added data protection.
-The drop out voltage is O.BV.
""':R3 is NOT required if Vpp enable is driven by a CMOS device.
"Cost approximations assume 10,000 piece quantity.
I
5-145
AP-316
Circuit #2
Down Conversion
(From 16.00V -26.00V to 12.00V)
,Vln ) - - _ . - - 1 In
LM-317
Cl
Adj
voul
OuII--.....- .....-'"'O
Voltage Regulator
~ Rl
"> 1% C2
=~
I
='=
292046-13
COMPONENTS
COST"
LM-317
R1 = 1240,1%
R2 = 10700,1%
C1 = 0.1 /LF
C2 = 100/LF
0.40
0.045
0.045
0.02
0.15
$0.66
NOTES:
LM-317 requires a minimum VIN-VOUT = 3.0V
'Cost approximations assume 10,000 piece quantity.
Circuit #3
Down Conversion
(From 15.0V-40.0V to 12.00V)
Vln>---.--1ln
LT1085
Cl
Adj
Youl
Oulf--.....- .....-O'"'
Voltage Regulator
~ Rl
==
I
[~~~!:~::i;~~~:~~~~~~:i:~~
i
:~ =~
1%
C2
J292046-14
COMPONENTS
COST"
LT-1085
R1 = 1240,1%
R2 = 10700,1 %
C1=10/LF
C2 = 10 /LF
2.50
0.045
0.045
0.10
0.10
$2.79
NOTES:
LT-1085 requires a minimum VIN-VOUT = 1.5V
"Cost approximations assume 10,000 piece quantity.
5-146
I
AP-316
Circuit #4
Up Conversion
(From 5V to 12.0V)
5V
Vpp
,..--+--......- - - 0 OUTPUT
200mA MAX
Vpp
COMMAND
292046-33
COMPONENTS
COST·
LT1072
R1 = 10.7k, 1 %
R2 = 1.24k, 1 %
R3 = 1k,5%
R4 = 120k, 5%
R5 = 270k,5%
C1 = 1 JIoF
C2 = 1 JIoF
C3 = 10 JIoF
L1 = 150JloH
Q1 = 2N3904
1.82
0.045
0.045
0.02
0.02
0.02
0.10
0.10
0.15
1.00
0.10
VppOUT
12.0V
R1
R2
10.7k 1.24k
Resistor
Tolerance
1%
$3.42
NOTES:
Drive Vpp COMMAND low to turn on the circuit.
·Cost approximations assume 10,000 piece quantity.
I
5-147
Ap·316
Circuit #5
Up Conversion Circuit
(From 5.0V to 12.0V)
S.OOv
+5v
24 +5v
~I
Valor
PM7006
GND GND
12
V+
V+
vv-
11
vppOut
14
10
15
13
-
D
r--" ,
,,,
,,
Gi
! Buz11A
--I
Vpp
Enable )-_-+,_...J
____ J
292046-16
COMPONENTS
COST'
PM7006
C1 = 0.1 ""F
Buz11A
$6.25
0.05
2.59
$8.89
NOTES:
1. The capacitor decreases output noise to' 140 mV pk-pk.
.
2. We added the Buz11A Mospower nFET to enable/disable the converter. This control minimizes power consumption
which under full load can reach 600 mAo
3. The voltage drop across the switch is 0.1V. Due to this drop the PM7006wili not maintain the Vpp spec with 10%
fluctuations in Vee supply.
'Cost approximations assume 10,000 piece quantity.
5-148
I
AP-316
APPENDIX C
LlST* OF DC-DC CONVERTER COMPANIES
AT&T MICROELECTRONICSt
3000 Skyline Drive
Mesquite, TX 75149
Tel: (800) 526-7819
Fax: (214) 284-2317
CORP.~
SHINDENGEN AMERICA, INC. t
2649 Townsgate Rd., Suite 200
Westlake Village, CA 91361
Tel: (800) 634-3654
Fax: (805) 373-3710
BURR-BROWN CORP. t
P.O. Box 11400
Tucson, AZ 85734
Tel: (800) 548-6132
Fax: (602) 741-3895
LINEAR TECHNOLOGY
1630 McCarthy Blvd.
Milpitas, CA 95035
Tel: (408) 432-1900
Fax: (408) 434-0507
MAXIM INTEGRATED
120 San Gabriel Drive
Sunnyvale, CA 94086
Tel: (408) 737-7600
Fax: (408) 737-7194
NATIONAL SEMICONDUCTOR
Mt. Prospect, IL 60056
Tel: (800) 628-7364
Fax: (800) 888-5113
CORP.~
PRODUCTS~
MOTOROLA INC.~
2100 E. Elliot Rd.
Tempe, AZ 85284
Tel: (800) 845-6686
SILICONIX INC.~
2201 Laurelwood Rd.
Santa Clara, CA 95056
Tel: (800) 554-5565
Fax: (408) 727-5414
TOKO AMERICA, INC. t
1250 Feehanville Drive
Mount Prospect, IL 60056
Tel: (708) 297-0070
Fax: (708) 699-7864
VALOR ELECTRONICSt
6275 Nancy Ridge Dr.
San Diego, CA 92121
Tel: (619) 458-1471
"This list is intended for reference only, and in no way represents all companies that support power conversion
products. Since this industry develops many new solutions each year, Intel recommends that the designer contacts
the vendors for the latest products. Intel will continue to work with the industry to develop optimum solutions for
power conversion. Intel Corporation assumes no responsibilities for circuitry other than circuitry embodied in Intel
products. No other circuit patent licenses are implied.
tMonolithic Solutions
Il.Discrete DC to DC Converter Solutions
I
5-149
AP-316
APPENDIX D
PARALLEL ERASE FLOW CHART
COMMENTS
Wait for Vpp to stabilize.
Use Quick-Pulse Programming
algorithm.
Initialize Variables:
PLSCNT_HI"= HI Byte Pulse
Counter
PLSCNT_LO = Low Byte Pulse
Counter
FLAG = Erasure Error Flag
ADRS = Address
LCOM = Erase Command
V_COM = Verify Command
INITIALIZE:
PLSCNT_HI 0
PLSCNT _LO = a
flAG;;: a
ADRS = 0
E_COM = 2020H
=
V_COM
= AOAOH
Erase Set-up Command
Start Erasing
Duration of Erase Operation.
Erase Verify Command stops
erasure.
See next page for subroutine.
When both devices at ADRS are
erased, F_DATA = FFFFH.
If not equal, increment the pulse
counter and check for last pulse.
Reset commands to default
(E_COM = 2020H,
V_COM = AOAOH)
before verifying next ADRS.
Reset devices for read operation.
Turn off Vpp.
292046-34
5-150
I
AP-316
Device Erase Verify and Mask Subroutine
COMMENTS
This subroutine reads the data word
(F_OAT A). It then masks the H I or
La Byte of the Erase and Verify
commands from executing during
the next operation.
If both HI and La bytes verify, then
return.
Mask- the HI Byte with DOH.
eCOM = (eCOM OR OOffH)
V_COM = (V_COM OR OOffH)
If the La Byte verifies erasure, then
mask' the next erase and verify
commands with FFH (Reset).
If the La Byte does not verify,
increment its pulse counter and
check for max count. FLAG ~ 1
denotes a La Byte error.
Repeat sequence for the HI Byte
FLAG ~ 2 denotes a HI Byte error.
FLAG ~ 3 denotes both HI and La
Byte errors.
292046-35
NOTE:
'Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming flash
data (F_DATA), the erase commands and the verify commands. Then manipulate the HI or La register contents.
I
5-151
Ap·316
APPENDIX E
PARALLEL PROGRAMMING FLOW CHART
COMMENTS
Start Program
Wait for Vpp ramp to VPPH
ApplyVPPH
Get ADRS/P_OAT
ADRS = address to program
P_DAT = data word to program
Initialize:
PLSCNT_HI = 0
PLSCNT_La = 0
FLAG = 0
V_OAT = P_DAT
P_COM = 4040H
V_COM = COCOH
Initialize Data Word Variables:
PLSCNT_HI = HI Byte Pulse
Counter
PLSCNT_La = La Byte Pulse
Counter
FLAG = Program Error Flag
V_DAT = valid data
P_COM = Program Command
V_COM = Verify Command
Program Set-up Command
xx = Address don't care
Program
High/Low Byte
Compare & Mask
Subroutine
See next page for subroutine
Program Verify Command
F_DAT = flash memory data
y
Compare flash memory data
to valid data (word compare). If not
equal, check for program error
flag. If flag not set, compare High
and Low Byte in subroutine.
Check buffer or 1/0 port for
more data to program.
Write READ_COM
Apply VPPL
Reset device for read operation.
Apply VpPL
Turn off Vpp.
Program Error
Program Complete
292046-19
5-152
I
AP-316
Program Verify and Mask Subroutine
COMMENTS
To look at the LO Byte, mask"
the HI Byte with 00.
p_co ... = (p _COM OR OOFFH)
. LOAT (V_OAT OR OOFFH)
V_COM = (V_COM OR OOFFH)
=
If the LO Byte Verifies, mask
the LO Byte commands with
the reset command (FFH).
If the LO Byte does not verify,
then increment its pulse
counter and check for max
count. FLAG = 1 denotes a
LO byte error.
Repeat the sequence for the
HI Byte.
P_COM = (P _COI.t OR FFOOH)
V_OAT = (V_OAT OR FFOOH)
LCOM = (V_COM OR FFOOH)
FLAG = 2 denotes a HI Byte
error. FLAG = 3 denotes both
HI and LO Byte errors. FLAG
= 0 denotes no max count
errors; continue with algorithm.
292046-40
NOTE:
"Masking can easily and efficiently be done in assembly languages. Simply load word registers with the incoming data
(F-DAn, the program commands and the verify commands. Then manipulate the HI or LO register contents.
I
5-153
Ap·316
APPENDIX F
DETAILED SYSTEM SCHEMATICS
~
...
v""
v""
T/8
SROY
AROV
8HEI ..
Q6
as
604
A.6iS3
v••
v"
00
--
WA#IR..'1
RD'
~
Cu.
GNO
7
eon
AD1S
A014
AD13
A012
ADt1
AOtO
A09
A08
x•
OE_
A.8
A17
A'
.
A'S
v""
07 f-I
07
06
05
06
A••
A'3
A.2
A11
A.O
A9
AS
aS
g;02 131 02~
A.
D.
co
~LE GNO~
00
'--ues.l34
-
LC$#
A07
A06
ADS
A04
A03
A02
AD.
AOO
v""
Q7
07
06
05
ues#
#
~
A7
AS
AS
A.
A3
A2
A.
Q6
as
g; I')~02
02
D.
00
m
L-uLE
A.
co
DE_
GNO~
'--Meso# 3B
T
-
Meso.
MCS1#
'::"
V
'--~ A7
BOC186
~~A3
I')
A4
Bi
RESET
15) B3
-
7
I7J
9
DEN#
39
PCSO#125
PCS1#
PCS2#
D9
06
~
-=
Vee
87
A7
~ A.
AS
'0
PCS3#
82.
B1
80
--111 OE_GNO~
r
INTO
INT •
INT 2
INT 3
0.5
D••
0.3
0.2
011
0.0
B4 1
AO
OIR
OT/R 40
t
:
~A2
A1
psw.
'2:S~
-
OE# 1
.L e.
~
r?'~'~
.0-
v""
•
~
~3WE'HIG>
~
O~¥--
-
osc-.
t=
itLE GNO~
'--
ALE~
MNI
HOLD
04
D3 121 03
.02
02 17'-D.
A.
Al9/S6I ••
A18/SS
A17/54
J
v""
07 ~
07
B D.
705
.
8
~
~
.0-
1-1
B6
B5
M.
~ ~
A.
AO
OIR
16)
RESET
~
8'
80
07
DB
05
04
03
02
D.
00
L.:=:i ~~
12:18
19:6
292046-21
5-154
I
AP-316
UCS#
120
120
CEo
Vee
Vpp
~
~4
~
~
~
~
~
PGM# 27
A12
All
Al0
A9
AS
A7
A6
A5
A4
A3
A2
Al
AO
DE# 22
07 19
06
0517
D4
03
02 1
01
DO 11
[8l)
GNO~
CEo
I
~
A12
All
Al0
A9
AS
A7
A6
A5
A4
A3
A2
Al
AO
Vee
~
Vpp
.L..
PGM#
E....
DE# 22
07 19
06
05
04
031
021
01 1
00 11
[8H)
.GNO
q
DE#
Vpp
WE HIGH.
WElDW#
MCSO#
L f32
A18
A17
A16
A15
A14
A13
A12
All
Al0
MJ
AS
A7
A6
AS
A4
A3
A2
Al
A16
A15
A14
Al3
A12
All
Al0
A9
A8
A7
A6
7 A5
A4
A3
A2
Al
AO
122
Vee
30 A17 CE #
WE#~
vpp
r!--
DE# 24
0721
D6 0
05
04
03 17
02
01
DO
[9L)
GNO~
-
~
~
;
A17 CE #
A16
A15
A14
A13
A12
All
Al0
A9
AS
A7
A6
A5
A4
A3
A2
Al
[9H)
AO
i32
Vee
WE#
Vpp
~
r!--
DE# 24
0721
06 20
05
0418
0317
02
01 14
00
GN0q.
-
DO
01
02
03
04
05
06
07
08
D9
010
011
012
013
014
015
292046-22
I
5-155
Ap·316
OE#
WEHIGH#
WElOW#
lCS#
20
CE#
AIS
AI.
A13
A12
A11
Al0
Ag
As
A7
AS
AS
1 AI.
A13
A12 '
2J All
21 Al0
Ag
25 As
A7
A3
A2
Al
0719
OJ; 18
0517
0.16
031
D213
Dl
DO 11
As
As
A3
A2
9 Al
1
Ao
F!--
OE# 22
6~
Ao
VCC~
WE#
[lOll
20
CE.
"'-d
~
~
~
q
GND~
-
~
AI.
A13
A12
Al1
Al0
Ag
As
A7
AS
As
A.
A3
A2
Al
Ao
VCC~
WE#
~
OE# 22
07 119
D6 18
Os 17
D.16
D3 1
02 13
01
Do 11
[10HI
GND~
-
Do
01
D2
D3
D.
Os
OJ;
D7
DS
09
0 10
OIl
012
D13
0 1•
DIS
292046-23
5-156
I
AP-316
35 RESET#
CS#
RO#
WR#
RESET #
1:27
OE#
WRLOW #
4:1 7 A
4:1 8
PA7 7
PAS
PAS
P,,"
PA3
8 AI
o7
270 7
28 O.
Os
o6
o5
o4
o3
o2
B2C55A
[15]
D.
31 0,
D.
o1
0,
o0
Do
PAo 4
PB7 25
PBs
PBs
PB. 22
PB,
PB.
PB,
PB.
PC7 10
PC. 1
PCs
PC. 13
PC, 17
PC.
PC,
PC.
~ Vee
-F
1
PA.
PA,
Ao
GN~
lh24
Vee
Vpp
14
L.!.
Vee
+V
+V
OCIOC
S/12.00±S%
F'
15 -V
-
[16]
GNO 12
16
GN013
~
0
Fl
;--7
f--
~
5
-::'::-
I
R2
"-3
1
~
2""'"
[1:
1
292046-24
5-157
Ap·316
+'2V
~ ~"'-. ~
7 GND Vee
_
,
-r,4
2,A Vee+ 1Y 3
2A
2Y
26 '488
3A ('2J 3Y 8
36
Vee- GND
.~
8
X2
,8 CS.
RESET'
RD.
WR.
1:25
RESE T.
OE.
WELO W'
~u
A3
A2
A,
24 A2
A,
AD
D7
Os
05
D4
03
D2
0,
Do
4 07
J Ds
~ 05
D4
03
D2
0,
Do
~
-
'"
RxD. ,3
CTS.
RI. WL
DSR.
14
3 1Y Vee ,A ,
~ ~~
,489 ~~
L!.!!
, 4Y ('3J 4A ~
-
JI:3
J':5
J':22
J,:6
GND
~
1,4
3 'Y Vee ,A ,
DCO. ,2
8
"
7 GND
~
GND
J1:7
....c-::-
9
X'TxD 6
DTR.
RTS.
5 INT
':45
J':4
,ci
OUI
8
:&
Vee
J, :2
J,:20
ri
825,0
("J
~~
'489 ~~ '0
4Y ('4J 4A ,3
J':8
GND
~
292046-25
5-158
I
AP-316
256K FLASH MEMORY DEMO PARTS LIST
Device
Component
[1]
[2,3,4]
[5,6]
[7]
[8L,8H]
[9L,9H]
[10L,10H]
[11]
[12]
[13,14]
[15]
[16]
[17]
C1
01
F1
J1
OSC-1
OSC-2
R1
R2
SW1
80C186
74HC573
74HC245
74HC32
27C64
28F256A
32Kx8 SRAM
82510
14C88
14C89
82C55A
PM7006
7406
20 fLF
1N914
BUZ11A
DB-25
20 MHz
18.432 MHz
10 Kn
1 Kn
Description
Pins
68
20
20
14
28
32
28
28
14
14
40
24
14
2
2
3
25
14
14
2
2
3
16-bit high integration CPU
Latch
Transceiver
OR gate
16 Kbyte EPROM
64 Kbyte flash memory
64 Kbyte SRAM
Asynchronous Serial Controller
RS-232 Line Driver
RS-232 Line Receiver
Programmable Peripheral Controller
DC/DC Convertor (5V -12.00V)
Invertor-Open Collector (O.C.)
Capacitor for CPU reset
Diode for CPU reset
MOSPOWER nFET
Connector (male)
CPU Oscillator
Serial Controller Oscillator
%W, 10% Resistor for CPU reset
%W, 10% Resistor for O.C. pull-up
Momentary Push Button for CPU reset
NOTES:
1. Place a 0.1 J.tF bypass capacitor at the Vee input of each IC.
2. Place a 0.1 J.tF bypass capacitor on the Ypp input of each 28F256 flash memory.
28F512 UPGRADE FOR THE
80C186/FLASH MEMORY DESIGN
To upgrade the 80C186/Flash memory design to handle 28F512's, the range of the CE# signal has to be
increased. There are a number of ways to generate a
CE# signal that will span the 128 Kbyte address range
of two 28F512 devices.
1. AND two of the current MCS lines together (defined
for 64 Kbytes each); or
I
2. Change the MCS individual block-select size from
64 Kbytes:
MMCS_VALUE = 41F8H,
MPCS_VALUE = OAOB8H
to 128 Kbytes:
MMCS_VALUE = 0IFEH,
MPCS_VALUE = OCOBEH
Also, cut the CE# trace to the RAM sockets. Then
wire MCSO# to the RAM CE#. This eliminates the
MCSO# and LMCS# range overlap caused by increasing the MCS range to 128 Kbytes. See 80C186
Data Sheet page 21 and 22 (Order # 270354).
5-159
AP-316
28F010 UPGRADE TO THE
80C186/FLASH MEMORY DESIGN
To upgrade the 80C186/flash memory design to handle
28FOlO's, a CE# signal has to be generated. There are
a number of ways to generate a CE#. signal that will
span the 256 Kbyte address range of two 28FO 10 devices.
1. AND two of the MCS lines together (defined for 128 .
Kbytes each as noted in the 28F512 modifications):
Cut the LMCS. trace to the RAM sockets. Connect
MCSO# to CE# on the RAM sockets (UlOL,UH).
Cut the MCS2# trace to the flash memory. Add an
AND gate. Connect MCS2# (cut trace) and
MCS3# to the inputs of the AND gate. Then wire
the AND gate output to the CE # of the flash memories.
Also, change the onboard memory MCS register to:
. MMCS_VALUE=OlFEH, MPCS_
VALUE = OCOBEH [128K blocks]'
and delete:
LMCS_REG and LMCS_Value.
2. Add a decoder;
Add a decoder (74HC138). Connect address lines
A18 and A19 to the Band C inputs of the decoder.
Tie the A input of the decoder low, and enable all the
enables. By using outputs YO, Y2, Y4, and Y6, you
have four CE# lines decoding 256 Kbyte blocks
each.
Cut the MCS2# trace to the flash memories. Connect the Y2 output from the decoder to the CE#
input of the flash memory.
RESET
3. Replace the address latch (U2) with a PLD that
latches and decodes.
Program a 5C032 as an integrated latch and decoder.
Replace the upper address latch [U2l with the Intel
5C032 EPLD. Cut the CE# trace to the flash memories. Connect the flash memories' CE# to the
5C032 pin 12. This maps the address space 40000H
to 7FFFFH. See Figures 1 and 2 for a comparison of
the 74HC573 (U2) and programmed 5C032 pin outs.
Figure 3 is the source code for the EPLD.
Also, change the value of the MMCS and MPCS
registers to 64 Kbyte blocks so that the MCSO#
range does not overlap the LMCS range.
MMCS_VALUE=41F8H, MPCS_
VALUE = OAOB8H.
RESET
LA16
AI?
LAn
AlB
LA18
A19
LA19
BHE#
LSo
Sl
LSI
S2
LS 2
GND
ALE
Figure 1. Latch Pinout
Vee
LA 16
An
LA1?
A18
LA 18
A19
LA19
LBHE#
So
CE# (40000H-OBFFFFH)
Sl
CE# (BOOOOH-OBFFFFH)
S2
CE# (40000H-7FFFFFH)
GND
LBHE#
So
292046-36
A16
BHE#
Vee
A16
ALE
292046-37
Figure 2. Integrated Latch and Decoder
5-160
I
AP-316
Thom Bowns - PLFG Applications
Intel
January 13, 19B9
EPLD HOTLINE: l-BOO-323-EPLD
002
5C032
Custom Latched Decoder
OPTIONS: TURBO=:,ON
PART: 5C032
INPUTS: ALE@ll, RESET@l, A19@5, A1B@4, A17@3, A16@2, nBHE@6
OUTPUTS:
LA1B@17, LA17@lB, LA16@19, LnBHE@15, nCE3@14, LA19@16,
nCE2@13, nCE1@12
NETWORK:
ALE = IN (ALE)
RESET = INP (RESET)
nRESET= NOT (RESET)
A19 = INP (A19)
AlB = INP (AlB)
A17 = INP (A17)
A16 = INP (A16)
nBHE = INP (nBHE)
LA19, LA19 = COIF (LA19d, DRESET)
LA1B, LA1B = COIF (LA1Bd, nRESET)
LA17, LA17 = COIF (LA17d, nRESET)
LA16, LA16 = COIF (LA16d, nRESET)
LnBHE, LnBHE = COIF (LnBHE, nRESET)
nCE3, nCE3 = COIF (nCE3, nRESET)
nCE2, nCE2 = COIF (nCE2, nRESET)
nCE1, nCEl = COIF (nCE1, nRESET)
EQ,UATIONS:
LA19d = A19 * ALE + LA19 * !ALE;
LA1Bd = AlB * ALE + LA18 * !ALE;
LA17d = A17 * ALE + LA17 * !ALE;
LA16d = A16 * ALE + LA16 * !ALE;
LnBHEd = nBHE * ALE + LnBHE * !ALE;
nCE3d = nCE3EQ,N * ALE + nCE3 * !ALE
nCE2d = nCE2EQ,N * ALE + nCE2 * !ALE
nCEld = nCE1EQ,N * ALE + nCEl * !ALE
nCE2EQ,N = ! (A19 * !A18);
nCE1EQ,N = ! (!A19 * AlB) ;
nCE3EQ,N = !(!A19 * A18 + A19 * !A1B);
ENDS
Figure 3. Source Code for the Integrated Latch and Decoder
I
5-161
intet
AP-325
APPLICATION
NOTE
Guide to First Generation
Flash Memory
Reprogramming
APPLICATIONS ENGINEERING STAFF
March 1994
5-162
I
Order Number: 292059-002
GUIDE TO FLASH MEMORY REPROGRAMMING.
CONTENTS
PAGE
INTRODUCTION TO
REPROGRAMMING ................. 5-164
You Are in Control ...................... 5-164
FUNDAMENTALS OF FLASH
OPERATION ........................ 5-164
CONTENTS
PAGE
DEBUGGING YOUR CODE AND OTHER
TIPS ON TESTING .................. 5-174
Software Drivers Save You Time ........ 5-174
Timers, Test Loops and Assembly Level
Programming ........................ 5-174
Adaptive vs. Brute Force Algorithms .... 5-164
Programming-The Key to Proper
Erasure .............................. 5-174
Moving Charge & Other Factors You
Should Know ........................ 5-165
16- and 32-Bit Systems ................. 5-175
ERASURE-THE GOLDEN RULE ..... 5-168
Margin for Error ........................ 5-168
Most Common Development Issues .... 5c169
Device Initialization and Reset .......... 5-169
The Erase Algorithm Interpreted ........ 5-171
The Program Algorithm Illuminated ..... 5-173
Logic Analyzers and In-Circuit
Emulators ............................ 5-175
Testing Your Software-One More
Time .... ; ............................ 5-175
Watchdog Timer Debug Circuit ......... 5-176
TROUBLE SHOOTING GUiDE ......... 5-177
Determining the Root Cause ............ 5-177
Ramifications of the Golden Rule ....... 5-173
I
5-163
Ap·325
INTRODUCTION TO
REPROGRAMMING
You Are in Control
Rewriting any type of memory requires hardware or
software control. Traditional EEPROM designers combined all control functions into each chip's periphery.
This provided a highly functional chip but at a high
price. On the other hand, DRAM designers provided a
bulk memory with little integrated peripheral circuitry.
Each system designer then accommodated the DRAM
with external refresh signals and learned quickly that
failure to refresh yielded non-functioning memory
boards. Initially, software drivers controlled DRAM
refresh; today controllers provide the same function.
Similarly, early disk drives required every user to write
software to manipulate drive head movement. Failure
to follow drive specifications and algorithms caused irreversible head crashes. Leading-edge engineers faced
these challenges and triumphed, as evidenced by the
sophisticated systems available today.
Since 1988, thousands of engineers have written software to direct flash memory reprogramming. With first
generation flash memories, one sends a control signal to
a device to begin and end programming or erasure. It is
a simple process implemented on more than 40 million
units, however care must be taken. If algorithms are
not properly followed, a device may be rendered inoperable. This document discusses proper software and
debug technique, which yields dependable first generation flash memory operation. First generation products
include the 28F256A, 28F512, 28FOlO and 28F020. All
second and third generation Intel Flash Memories contain automated program and erase routines.
FUNDAMENTALS OF FLASH MEMORY
OPERATION
Adaptive vs Brute Force Algorithms
Manydesigners use EPROMs regularly. Few.consider
the programming algorithms because the PROM programmer vendors take care of that function.
Two types of algorithms are in use today:
• Adaptive Algorithms
• Brute Force Algorithms
One simply adds the net effects of Vee and temperature variations, and superimposes on those factors the
normal EPROM charge leakage to obtain the answer.
The next question is how can these factors be checked?
NOTE:
EPROM and EEPROM charge leakage occurs over a
very long time-typically 100 years. Reliability papers
often discuss charge leakage in terms of the memory's
data retention characteristic.
If you look at EPROM programming algorithms, you
will notice that Vee is elevated during programming.
The elevated Vee acts as the feedback mechanism for
the adaptive algorithm. Reading the device and checking for program completion is called verification, or
margining. (One is checking the margin to Vee fluctuations.) For example, if the part can be verified at 6.25V,
then it can withstand the fluctuations and normal
charge leakage.
During the past few years most major EPROM manufacturers have converted to adaptive algorithms. The
algorithm loops back and programs a byte again if the
first program operation does not verify' at the elevated
voltage.
Brute force algorithms simply program each byte multiple, times, typically with long program durations. This
type of algorithm has no in-system margin verification.
That is they assume but never verify program margin to
the typical environment effects.
Many flash memories that specify a brute force algorithm may fail to retain data for 10 years. Additionally,
they may not read the data correctly even at specified
Vee and temperature extremes.
Intel's flash memory program and erase algorithms are
both adaptive. They offer margin verification without
requiring users to elevate Vee in-system. When issued
a command to program verify, the memory's command
register logic taps an internally-generated elevated Vee
from the user-supplied external Vpp (12V). This is why
it is essential that you provide the specified Vpp voltage
and follow the given adaptive algorithms. Intel's adaptive algorithms, combined with the command register
architecture, assures reliable code and data storage and
dependable system operation.
Figure 1 shows an example of an adaptive byte programming algorithm. Appendix A compares the algorithm in Figure 1 to a brute force approach.
Adaptive algorithms such as Intel's Quick-Pulse Programming and Quick-Erase algorithms reduce programming time. A feedback .'mechanism recognizes
when each byte has been programmed sufficiently. You
may ask how is the point of sufficiency determined?
5-164
I
AP-325
level discussions were last heard in college. We may
recall that DRAM consists of a storage capacitor and a
transistor. We remember this clearly because failure to
refresh that capacitor causes systems to malfunction. In
like fashion, one should understand the fundamentals
of flash memory reprogramming. The understanding
will enable error-free memory operation and reliable
system performance.
.
In simplest terms, each data bit equates to a memory
cell. Intel's flash memory uses one transistor per cell
with the smallest possible architecture. This delivers
the lowest cost per bit and highest capacity, levering
system software (rather than bulky, complex cells) for
reprogramming control.
292059-1
Figure 1. The flow chart shows the fundamental
nature of an adaptive algorithm. Based on the
outcome of program verification, the flow may
loop back for another program operation.
Moving Charge and Other Factors You
Should Know
This section discusses the mechanics of flash memory
programming. For most system designers, transistor-
Figure 2 shows a simplified cross section of Intel's flash
memory transistor. Note the structure; the cell is a
stacked gate MOS transistor. An isolated floating gate
stores the memory charge. The floating gate consists of
a layer of (conductive) polysilicon surrounded by (nonconductive) oxide layers.
On a DRAM cell, each transistor connects to a capaci-
tor which stores the memory charge. The major difference between flash memory and DRAM derives from
their cell structure. The DRAM cell loses its charge if
not refreshed within a few milliseconds. On the other
hand, the flash memory floating gate maintains its
charge for typically 100 years. The structure is isolated
and insulated by the field and gate oxides-hence the
.name "floating" gate.
ETOX Flash Memory Cell·
Control Gate
Floating Gate
( Source
)
)
l__
Dral~n
(
Substrate
. oo-u(
/
S
Floating Gate
)
292059-2
'Patented Intel Processes
Figure 2. Simplicity of design assures Increasing densities, manufacturability and reliability.
These are the attributes that drive mainstream memories.
I
5-165
AP-325
Changing the memory contents is simple. Figure 3
shows two memory cells-one being erased and one
being programmed. Erasure removes charge from all
bits simultaneously. Programming adds charge to selected bits. During erasure, not all charge is removed.
The erase verify operation tells the system when
enough charge has been removed. At that point, the
flash memory behaves like a U.V.-erased EPROM.
Removing too much charge by erasing too long renders
the memory unprogrammable. Excessive erasure lowers
the cell threshold to the point where the transistor is
always on and always reads data "I". (Recall that the
cell threshold, Vto determines when the transistor turns
on or off.> You must control the erase timing within the
algorithm specifications on ill'st generation flash memories.
5-166
A second erase consideration relates to the first. Prior
to erasing the chip, you must blanket program all bytes
to data OOh, regardless of the previous data.· This step
equalizes the charge on all transistors.
If you skip this step and proceed directly to erasure, an
interesting thing happens. Consider a typical byte programmed with data OAAh (1010 10l0b). While programming this data, bits with data "I" remain erased
(charge removed), and bits with data "0" are programmed (charged added). Following programming,
normal read operations sense whether a memory transistor has more or less charge and drives the outputs
accordingly.
I
AP-325
Erasure
Removes Charge from Floating Gate
I
CG
OV
292059-3
Field from Vgs forces electrons from floating gate.
Programming
Adds Charge to Floating Gate
ICG
12V
292059-4
Vgs > VI turns transistor on creating source-drain channel (Ids);
Field from Vgd attracts electrons from channel current towards floating gate.
Figure 3. Flash memory cells during erasure and programming. Note the
movement of charge on and off the floating gate. The charge adjusts the
cell threshold, which tells the outputs whether a bit (transistor) is on or off.
I
5-167
AP-325
Erasure then removes charge from all bits. The bits that
have had charge added (data "0") have some quantity
of charge removed; bits with less charge (data "1 ")
have charge removed as well. This is akin to excessively
erasing the data "1" bits. Pre-programming all bits to
data "0" equalizes the charge which allows for controlled, uniform erasure of all bits in the device (i.e., all
1,048,576 bits in a 28FOlO).
long? Figure 4 shows the margin for error of a typical
device. Following the algorithm would have stopped
erasure after 1 second. Cell depletion occurred after 10
seconds giving a lOx margin for error. This lOx margin
exists if the erased cell erases in 1 second or 10 seconds
(i.e., within the algorithm limits). This chart shows one
typical example where the device happened to take I
second to erase.
The sections' entitled "Margin for Error" and the
"Erase Algorithm Interpreted, Program all Bytes to
OOh" discuss this concept in greater detail.
Flash memory has generous margin for error over the
stopping point defined by the algorithm. The stopping
point is defined as the point when all bytes in the chip
verify to FFh data. The erase operation duration
(Twhwh2) is specified at 10 ms ± 500 p,s. Five hundred microseconds offers substantial allowance for system latency during erasure and even for slop in the
timer generation. Processors or controllers can execute
many lines of code in 500 p,s, and the margin for error
simply adds another guardband.
ERASURE-THE GOLDEN RULE
Erasure removes charge from all memory cells in paralleL This lowers the cells' threshold voltages from the
programmed level (6.5V) below Vee to the erased level
(3.2V) The device continues erasing until told to stop
by the verify command or until the integrated stop-timer counts down.
Margin for Error
Proper software and system design will never rely on
the additional margin for error. Remember, you control
the program code and system operation during erasure.
Once you have fully debugged your driver code, the
issue of software control disappears entirely.
Allowing erasure to continue too long depletes the
charge in floating gates. So you ask-how long is too
(Volts)
CELL
THRESHOLD
I
ERASE TIME
I
:. MARGIN rOR ERROR
•:
292059-5
Figure 4. The logarithmic-decaying nature of erasure allows for 10x
error in erase time before a device becomes inoperable. Remember,
each device has its own erase time, thus the use of an adaptive algorithm.
5-168
I
AP-325
Most Common Development Issues
Case 1. The System Controls Vpp with a Switch
Having covered the fundamentals of flash memory reprogramming, let's move on to the system's hardware
and software perspectives_ The following list of. questions might have occurred to you •••
Assuming Vee is stable with Vpp switches on, then the
command register defaults to the read mode. No power-on reset is required.
• You have defined a system power supply with regulated 5V and 12V outputs (Vee and Vpp). Due to
the smaller capacitive load on the Vpp supply, Vpp
powers up much faster than the Vee supply. Will
this affect the device?
• How does the flash command register architecture
reset?
• Suppose your code sends a signal to start erasure,
and never tells it to stop?
.. Suppose your software delay timers are not calibrated. Instead of stopping erasure after ten milliseconds, the code issues the stop command after 10
seconds?
.. Suppose your 6 J.Ls timer used between the erase and
erase verify modes is only 2 J.Ls?
.. Suppose you decide to skip the first erase operation
(program all bytes to zero) because the device is already programmed with data?
It Suppose you are programming and erasing devices
in a 16- or 32-bit system?
The answer to all these questions can be found in the
following sections. The questions and the reasons all
relate to the discussion of how the cell works.
Device Initialization and Reset
Many logic devices which contain command or control
registers also have a reset pin. This pin serves two purposes: it resets the device's internal logic; and it synchronizes the device's clock to the system clock.
Intel's first generation flash memory command register
and reprogramming circuitry reset to the read mode by
three means:
I. raising or lowering Vpp with Vee == 5V;
2. raising Vee with Vpp = 12V;
3. issuing the reset command twice in succession.
NOTE:
Method 3 stops erasure or programming as well as resets the chip.
A few cases require closer consideration.
I
Designers might opt to include the Vpp switch for
either (or both) of two reasons. The first reason is power minimization. Depending on the technology used, a
voltage regulator or pump's efficiency can range from
40%-85%. Switching off the Vpp supply minimizes
system power consumption. See Appendix B for an example Vpp generation circuit with ON/OFF control
capability.
The second reason is absolute data protection. This feature is not available to 5V-only EEPROM because the
reprogramming voltages are generated internally. On
that class· of memory device, logic glitches can spuriously change data during system power up or power
down. Flash memory's 12V power requirement offers
absolute control over these concerns; with Vpp below
Vee + 2V, data protection is guaranteed. Internally,
the electric fields are simply too weak to spuriously
write data.
Case 2. Vpp Powers Up before Vee
Systems with Vpp hardwired to a regulated transformer
might encounter this case. Typically, Vee will charge
many more bypass capacitors than Vpp. Vee will
therefore power up much more slowly.
The flash memory power-down (Vee = OV) default
state blocks Vpp from disturbing the array. These conditions hold while Vee is below ~ 2V. Once Vee rises
above ~ 2V, the internal logic kicks in and resets the
device to the read mode. (This is analogous to the internal Vpp reset condition described in Case 1.)
Should the three control pins glitch during the powerup phase (CElow, WElow, and OEhigh), then the command register acts to filter the data. The command port
will only react to the correct command sequence.
Designers might opt to hardwire Vpp for a number of
reasons. The first reason is cost minimization. A regulated 12V secondary from a transformer is commonly
available. Adding a switch or a power supply sequencer
adds cost and complexity. The second reason involves
consideration of the end application. Using the flash
memory as a read/write memory requires optimization
for the write cycle. Powering Vpp on before each write
would waste considerable time.
AP-325
Bus
Command
Operation
Standby
Comments
Wait for Vpp Ramp to
VPPH (= 12.0V)(I)
Use Quick-Pulse
Programming
Initialize Addresses,
Erase Pulse Width, and
Pulse Count
Write
Set-Up
Erase
Data
=
20H
Write
Erase
Data
=
20H
Standby
Write
Duration of Erase
Operation (Twhwh2)
Erase
Verify
Standby
Read
Standby
Write
Standby
Addr = Byte to Verify;
Data = AOH; Stops
Erase Operation
tWHGL
Read Byte to Verify
Erasure
Compare Output to
FFH, Increment Pulse
Count
Read
Data = OOH, Resets
the Register for Read
Operations.
Wait for Vpp Ramp to
Vpp 1(1)
292059-6
NOTES:
1. The Vpp power supply can be hard-wired to the device or switchable. When Vpp is switched, Vpp 1 may be ground,
no-connect with a resistor tied to ground, or less than Vee + 2.0V.
2. Erase verify is performed after chip-erasure. A final read/compare may be performed (optional) after the register is
written with the read command.
3. CAUTION: The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Figure 5. Quick-Erase Algorithm for Intel's First Generation Product Line
5-170
I
AP-325
Case 3. Warm Resets
Warm resets, where the system maintains power while
rebooting, requires closer inspection. Consider the situation where the system is reprogramming the flash
memory and a hardware or software reset occurs.
The boot software would not realize that programming
or erasure is ongoing and would not know to stop the
reprogramming operation. Therefore safeguard against
this condition with one of two means: 1) ensure that
control logic switches Vpp off during reset; or 2) reset
the flash memory before resetting the processor. For a
software reset, simply add the flash memory reset command to the interrupt sequence. For hardware resets,
wire the reset switch to the interrupt controller instead
of directly to the reset input. Hardware resets would
then execute the software interrupt sequence. Intel's
second and third generation flash memories all include
a H/W reset pin (RP #) formally called PWD #. This
pin is essential for any device with automation or embedded algorithms.
The Erase Algorithm Interpreted
The following section offers a block by block explanation of the Quick-Erase algorithm shown in Figure S.
Understanding the reasons behind a function will enable you to appreciate the importance of following the
algorithm explicitly. Deviations will negatively affect
the part's performance and should not be attempted.
Note: the effect may not be immediately apparent.
Apply VpPH (Optional, see Discussion on Device Initialization)
Switch on the local Vpp supply prior to erasure and
programming. The time required for Vpp to reach its
steady state 12 ± 0.6V depends on the capacitive load
and the impedance of the printed circuit board trace. If
you measure this delay on a wire-wrapped prototype
system, remember that temperature, printed circuit
traces and the board's layout change the load seen by
the Vpp generator. Allow Vpp sufficient time to ramp
before proceeding with the next step.
I
Program All Bytes to OOh
~
Data
=
OOh?
Prior to erasure, blanket program all addresses in the
flash memory to OOh (charge state), regardless of the
previous data. Verify that each address equals OOh before proceeding to the next address. If you use only part
of the memory array, you still need to pre-program the
entire array for erasure. An example where this is an
issue is using a 5 12K in a 2S6K socket. A second example is a system where internal microcontroller memory
overlaps the external flash memory space.
Programming data OOh equalizes the charge on every
bit in the array. This is necessary because erasure removes charge from all cells regardless of their previous
state.
For example, reconsider the byte containing AAh data
(1010 1010b). If you skip the pre-program step, then
during erasure when the data "0" bits get charge removed,the previously erased bits (data "1") lose additional charge. This drives the cell threshold a little lower. The next time you erase the chip and change the
code, the threshold will drop to 2.8V.
If the memory transistor is not pre-programmed to data
"0" before the next erasure, then its threshold will drop
on successive reprogramming cycles (denoted by E3,
E4, etc. in Figure 6). Repeated violations of the blanket
programming requirement drives the threshold to the
point where the transistor is stuck on (data = "I").
Variable Initialization
Initialize two variables and a constant: ADDR (address), PLSCNT (pulse count), and TEW (erase pulse
width). The pulse count increments from 0 to a maximum of 1000 erase tries. The erase pulse width remains
constant at 10 ms. The address increments from the
flash memory starting address to the ending address
during verification.
5-171
AP-325
(Volts)
Program 8
Level .--- -.
(Data "0") 7
6
CELL
THRESHOLD
5
Erasure 4
Level .---(Data "I") 3
2
l' 2 3 4 5 6 7 8 9 10 11 (Seconds)
CUMULATIVE ERASE TIME
292059-7
Figure 6. Successful erasure requires blanket programming all bytes to
the data "0" level first. This prevents threshold decline on successive erase
cycles (E2, E3, etc.). Very low thresholds cause the chip to malfunction.
Write Erase Set·Up Command
Write the erase set-up command (20h) to any flash
memory address. This prepares the selected device for
erasure, but does not activate the process. A second
erase command (20h) is required. Any other data written to the flash memory between the set-up and erase
commands will abort the sequence. Once the process is
started, it will not stop until told to do so. The correct
stop erasure command is Erase Verify (AOh). However,
any command including the Reset command is an illegal sequence and will stop erasure as well.
Write Erase Command
The erase command starts the erase process. Internally,
the device switches the voltages on all memory cell
drains, gates, and sources to the erase configuration.
Time Out Tew (10 ms)
Start your software or hardware timer. Until commanded to verify or until the integrated stop-timer
counts down, the flash memory continues the erase process. Therefore, assign a high priority to the' timer in·
terrupt. If a higher priority interrupt occurs, stop the
erase process and switch contexts (store all variables,
registers, etc.). This will allow reentry into the erase
procedure in a controlled fashion.
5-172
Write Erase Verify Command
Write the erase verify command (AOh) to the flash
memory at the address given by the ADDR variable.
The erase verify command performs many tasks. Internally, the device stops erasure and latches the given
address for verification. Additionally, the command
changes the voltages on the memory' cell drains, gates
and sources to the erase verify configuration.
Time Out 6 jLs
This time out accounts for the internal slew rate of
switching the memory array from the erase to the erase
verify configuration. Do not attempt to read from the
device before 6 jLs has passed; the device will appear to
still be programmed. This is because you have not al"
lowed sufficient time for the memory to change configurations. Your code will then interpret this as a need
for extra erase operations, and will continue erasing the
device.
NOTE:
6 jLs is a mlmmum specification. You can use the
10 jLs timer developed for the programming algorithm.
I
AP-325
Read Data from Device
Read the data at the address given by the ADDR variable. This should be the same address driven with the
erase verify command.
Data = FFh?
Compare the output data at address ADDR to FFh. If
the data equals FFh, then that address has been erased.
Continue verification until the last address has been
verified or until the maximum erase pulse count (1000)
has been reached. Typically, most devices will fully
erase within 50-100 erase loops.
Last Address -+ Increment Address
Check the ADDR variable to see if the last address has
been verified. If not, increment the ADDR variable and
re-write the erase verify command. Remember to write
the erase verify command to address ADDR, since the
verify command latches the address. Also, if your system has 64K byte segment boundaries, be sure to incre-·
ment the base pointer every 64K byte addresses.
Write Read Command
After full chip verification, write the read command
(OOh) to switch the device to read mode. If you plan to
reprogram the device immediately, this step is not necessary.
Apply VPPL (Optional)
Switch Vpp off. With Vpp left on, the command register offers data protection by requiring a precise sequence to initiate programming or erasure. However,
Vpp controls overall command register operation.
Turning Vpp off disables the command register, thus
providing absolute data protection. Without the high
voltage, the reprogramming mechanisms cannot occur
and the component becomes a read only memory
(ROM).
Abort/Reset
Whenever a system error condition occurs (reset or reboot), write the Reset command (FFh) to each flash
memory twice in succession. This is a good initialization practice in systems leaving Vpp at 12V. The processor would be unaware if prior to the reset, it had been
in the middle of erasure, and this sequence aborts erasure.
The Program Algorithm Illuminated
The full algorithm. will not be interpreted here, although a few items should be noted. You can find a
conceptual version of the Quick-Pulse Programming algorithm in Chapter 2, Figure I, and the complete flow
chart in Appendix C.
I
First, similar to erasure, a two-write sequence starts
programming. The first write is the Program Set-Up
Command which primes the chip for programming.
The chip then latches the address and data to be programmed on the second write. You can abort programming by writing the Reset Command twice in succession instead of the data to be programmed.
Second, the device continues programming until commanded to stop by the Program Verify Command.
Similar to the Erase Verify Command, this command
performs a couple of functions. Internally, it halts programming and latches the given address for verification. Additionally, the command changes the voltages
on the memory array's drains, gates, and sources to the
program verify configuration.
The cell programming mechanism is self-limiting.
However, do not assume that programming all twentyfive 10 JA-s operations in one pass is the best way to
attain reliable operation. To a certain degree, programming stresses the memory cell. The stress is considerably lower than that applied to EEPROM (2 MV/cm
lower to be specific). But why stress a component without cause? The adaptive Quick-Pulse Programming algorithm with its fast program operations, minimizes all
stresses and affords the greatest reliability.
Finally, after writing the Program Verify Command to
the device, wait a minimum of 6 JA-s before reading the
device. The time out accounts for the internal slew rate
of switching the memory array from the program to
program verify configuration. Do not attempt to read
from the device before 6 JA-s has passed; the device may
appear unprogrammed. Your code will then interpret
this as a need for extra program operations. It may
needlessly reach the 25 operation limit, even though the
byte most probably programmed on the first pass.
Ramifications of the Golden Rule
Always follow the erase command with an erase verify
command to stop erasure. Interrnpt-driven systems
must give high priority to servicing the reprogramming
timer interrupts. Systems that reset upon a watchdog
time-out must reset the flash memory device before rebooting. (See discussion on device initialization.) Likewise any non-maskable interrupt should software- or
hardware-reset the flash memory before performing a
context switch.
Use an oscilloscope to calibrate all time delays before
attempting erasure. The delay modules include the
6 JA-s, 10 JA-S, and 10 ms timer routines.
Blanket program all addresses to OOh data before erasing. Verify correct implementation of the programming
algorithm with a PROM programmer before attempting erasure. (Chapter 4 explains how this can be done.)
5-173
AP-325
16- and 32-bit systems require special attention. Each
flash device has its own erase characteristic. Do riot
assume that if the low byte of a data word is not erased,
then the high byte must not be either.
timers' also present some risk if there is a frequency
upgrade change on the controlling processor. Regenerate and check your timer routines whenever the system
clock rate changes.
Always follow the listed guidelines and take care while
developing your code to eliminate the erase control
issue. Consider it similar to implementing any control
function. Once the code is debugged and stable, the
issue goes away.
Timers, Test Loops and Assembly
Level Programming
You might ask, is it not possible to control erasure
through hardware? The alternative to software control
is integrated hardware control or an external controller.
Intel ofers a complete line of high density, cost-effective
products with integrated hardware control, often called
automation. Whether software or hardware controlled,
Intel's ETOX Flash Memory offers the most reliable,
dense, manufacturable, and fastest read/write nonvolatile memory. Other EEPROM approaches have drawbacks of multiple transistors per memory cell. This
property negatively affects all those attributes offered
by Intel's ETOX flash memory.
DEBUGGING YOUR CODE AND
OTHER TIPS ON TESTING
As with any software checkout, a few simple principles
enable complete flash memory algorithm debug. The
following sections offer some hints to make your job
easier.
Timing circuits or software play the most crucial role in
flash memory reprogramming. Good timers precisely
control their function; sloppy timers produce faults. An
example of a sloppy timer is one produced by a compiler. Each time high-level languages recompile, the lowlevel object coding may change. Thus, a timing loop
may be lO ms one compilation, and much longer or
shorter the next time.
You can check your timing method with the following
simple technique. Develop test loops which call the various timers' routines. For example, implement the 6 ,""s,
10 ,""s, and 10 ms timers used with the 28FS12 and
28FOlO. If you have a spare port or peripheral output,
use it to trigger an oscilloscope. Follow the trigger call
with the timer routines. If you do not have a spare port,
write to the flash memory address space before and
after each timer call. You can trigger the oscilloscope
off of the flash memory CE# signal. Remember to
power-down the system and remove the flash memory
before attempting these methods.
Once the timer code has been verified, you can link and
locate it to a higher-level erase/program algorithm implementation.
Software Drivers Save You Time
Intel saves you time by offering various processor-family flash memory drivers. You simply edit the files to
suit your system. Then assemble the driver, link, and
locate it, and you are ready for debug.
These drivers offer the framework for successful flash
memory reprogramming, and require some customization to fit your particular system. If your processor's
driver is not available, you may use the available driver
software as an example. One caution in advance: The
drivers have been written in assembly language to give
the most speed- and memory- efficient code. However,
most people prefer high-level programming.
High-level programming can be used for everything except software-timer generation. Compilers may give
different routines with different object code on each
compilation. Therefore, the timers must be either hardware-based or coded in assembly language. Software
5-174
Programming-The Key to Proper
Erasure
Earlier sections described the importance of programming oo's prior to erasure. This procedure equalizes the
charge on all memory cells; following this step all bits
erase in unison.
A conclusive debug technique can check your programming software. Simply use your software to program
zeroes into the flash memory and then verify this step
using a conventional PROM programmer. Load the
PROM programmer's buffer with all zeroes and compare the buffer to the flash memory. If your programmer does not service the flash memory, call the company for the latest software upgrade. Alternatively, one
can easily rig the S12K flash memory to look like a
S12K EPROM. Simply jumper Vee on a 32-pin socket
I
AP-325
to a few pins. Note that the 27512 EPROM and
28F512 flash memory have different intelligent identifier codes. Override the identifier code check to use this
method. See Figure 7 for socket details.
Some microcontrollers have limited address space or
internal memory that masks certain external address
space. Even if you do not use sections of the flash memory, you must still access these sections to program zeroes before erasure. Map and decode port bits to access
unused address space, and verify that all bytes are programmed to zero before proceeding with erasure.
+5V
Of course it could be; every device erases at a different
rate and the algorithm has only checked up to address
07C5h.
You can take advantage of the data rate of wider data
buses by utilizing the command register, the reset command and an analysis of erasure. Each erase operation
is 10 ms. Each byte verification takes 6 J-Ls. Therefore,
erasure takes three orders of magnitude longer than
verification. Optimization for erasure yields the optimum performance because verification is a second
order effect.
Let us reconsider the previous example. At address
07C5h, the data word does not verify. On the next erase
operation edit the erase (and erase verify) command
word such that only the high byte gets the erase command, and the low byte gets a reset command. (i.e.,
change the command word from 2020h to 20FFh).
See Application Note AP-316 for a detailed flow chart
for this approach. Note this document is based on the
28F256; however, most concepts carry through to the
higher density devices. (Literature Order number
292046).
292059-8
Figure 7. A 28F512 can be read in a PROM
programmer as a 27512 by jumpering the
appropriate pins to Vee. The same method
applies to the 28F010.
16- and 32-Bit SystemsAchieving Optimum Reprogramming
Throughput
Erasing flash memory in 16- and 32-bit systems requires special consideration. One could implement the
program and erase algorithms in a byte-wise fashion,
but this is time-consuming. Alternately, one can treat
the multiple flash memory as a data word, and gain
optimum performance.
The primary consideration with the latter approach is
that one device may program or erase faster than the
other(s). Subsequent programming or erasure of a slower device compromises the functionality of the faster
device by subjecting it to the slow-device timing.
Consider an example of erasure in a 16-bit system. After 10 passes through the erase operations, both devices
verify through address 07C3h. Then at address 07C5h,
the processor reads data word 83FFh.
Logic Analyzers and In-Circuit
Emulators
Many programmers use logic analyzers and in-circuit
emulators to debug code. These approaches are fine for
flash memory algorithm debug if certain conditions are
met.
1. Check timing routines with an oscilloscope; there is
no alternative.
2. Know your code and set breakpoints intelligently.
One designer had the bad luck of throwing in a
breakpoint in the middle of the program OO's loop.
After stepping through a couple of byte program 00
loops, he called the erase flow routine. Can you identify the problem?
3. Single step through your reprogramming code, if and
only if, the flash memory device is removed from the
system.
Testing Your Software-One More
Time
Some flash memories specify 100 erase/program cycles.
This is a minimum specification; Intel Flash Memories
cycle 100,000 times. With this in mind, feel free to
check and recheck reprogramming operations. There is
no reliability risk in doing so.
Since erase data is FFFFh, a few bits in the upper byte/
device have not erased. The natural flow of the algorithm would dictate another erase operation. But what
about the lower device? Could it be completely erased?
I
5-175
AP-325
One confidence-raising test is similar to that done on
systems: stress the system/software by executing test
code numerous times consecutively. Set the reprogramming drivers in a loop, and let them run 20-40 times.
On each consecutive pass, use a constant data pattern
such as OAAh. This tests the reprogramming code from
a quasi-static perspective. Missing is the true system
environment. In the true system environment, multiple
inputs compete with the flash memory for interrupt priority. Also, RF noise from motors can cause spikes and
glitching on Vpp or Vee. Additionally, fully loaded
systems or partially loaded systems might have different Vpp response characteristics or noise levels. Signals
that look clean in the lab, might not be all that clean in
the true operating environment. Therefore, flash reprogramming tests should be done in the true system environment as a final test.
Watchdog Timer Debug Circuit
This section describes.a simple tool you can build for
debugging your' code. Since Intel's first generation
Flash Memories contain integrated stop-timers, this
tool offers no real benefit. It is simply shown in case a
designer is debugging code for alternate sources. An
EPLD watches the flash memory data bus and control
signals for the erase sequence-erase set_up, erase, and
erase verify commands. Once the CPU initiates erasure,
the debug tool starts a 15 ms timer.· Should the timer
count down prior to receiving the erase verify command, then the circuit switches Vpp off.
This tool does not check for the other items discussed
in the Tips on Testing section; you must still check
those yourself.
Figure 8 shows the circuit schematic. The EPLD
source code and the name of an Intel EPLD applications engineer is located in Appendix D.
{{
3
28
4
25
23
26
27
5
6
7
8
9
10
11
12
A14
A13
WE
A12 28FXXX
All
OE
A10
A9
07
A8
06
A7
05
04
A6,
A5
03
A4
02
A3
01
A2
DO
Al
AO
GNO
11 WE
24
31
30
19
18
17
15
14
13
10
9
8
7
6
5
4
3
07
06
05
04
03
02
01
DO
5AC312
(EPLD) ClK
RESET
AHR
TIMClR
TIMST
TIMER_IN
GNO
GNO
GNO
GNO
8
Vee
12 GNO
292059-9
Figure 8. Watchdog Timer Debug Circuit
5-176
I
AP-325
TROUBLE SHOOTING GUIDE
Determining the Root CauseSoftware Error vs Device Damage
The three major indications of a flash memory problem
are labeled in the following section. The subsequent
paragraphs define potential root causes to investigate.
I. The Device Does Not Program
Did it program before?
A.No.
1. Trigger your oscilloscope on CE# while probing Vpp. Verify that Vpp has reached a steadystate l2V when the device is first written.
~et the time-base to 10 ,...s/division (the duration of the program operation). Trigger on
CE# and probe WE# (look at both traces).
C~eck ~he duration of the 10 ,...S program operatIOn time delay. Also, check the duration of
the. 6 ,...S delay between writing the program
venfy command and read.
3. Look for ringing on Vpp when Vpp has been
switched on. Over-voltage stress on Vpp (ringing with amplitude greater than l3V) will destroy Vpp's silicon structure.
4. Power the system down and back up. Look for
destructive glitches on Vee or Vpp (greater
than 7V and 13V respectively).
5. Verify erasure and programming on a PROM
programmer (if available). Fill the programmer
buffer first with OOh data and program the buffer to the flash memory. Then erase the device,
and repeat with AAh data. Repeat the last step
with 55h data. This sequence fully exercises the
array, the input buffers and the output buffers.
If all tests pass then check for a hardware or
software error.
2.
I
B. Yes.
1. Have you done anything that may have ESD
zapped the devices (i.e., touched the devices
while not being grounded, re-wired the protoc
board with the components socketed, etc.)? If
yes, check part as outlined in section I.A.S.
2. Have you attempted erasure? If yes, verify
~our algorithm as outlined in Chapter 4. Also,
Implement the' in-system intelligent identifier
mode. If the device outputs an incorrect code
then either an output has been zapped or th;
golden rule has been violated. Section I.A.S
describes a method of checking for ESD damage.
II. The Device Does not Erase
Did it erase before?
A.No.
Follow steps 1-5 outlined in section I. When
performing step 2, adjust the oscilloscope time
base to 10 ms/div.
B. Yes.
Has the board design, clock rate or software
changed? System clock rates directly affect the
accuracy of software timers. See AP-3l6 for a
discussion on software timing versus clock rate.
III. The Device Erases Spuriously
Exercise all system functions while monitoring the
flash memory chip selects. Verify that I/O mapped
addresses or logic are not accidentally selecting the
flash memory. For example, the space bar character sent from a keyboard controller happens to be
20h. If the flash memory is accidentally selected
while this data is on the bus, then erasure will commence on the following cycle when the condition
occurs again.
5-177
AP-325
APPENDIX
A
TWO APPROACHES TO ALGORITHMS
Adaptive
Brute Force
292059-10
y
y
o EfficientMax Time = (10 + 6 /Ls) • 25
= 400 /Ls
Typ Time = (10 + 6 /Ls) • I
= 16/Ls
o ReliableVerify Command slews internal voltages to simulate elevated Vee.
o SlowMax Time = (100 /Ls • 12)
+
3 ms
= 4200 /Ls
Typ Time = (100 /Ls • 10) + 1.5 ms
= 2.5 ms
o QuestionableUnknown margin to Vee and temperature
swings, as well as cell leakage;
Figure 9. Left and right flow charts compare Intel's (adaptive) Quick-Pulse Programming
algorithm and another company's (brute force) approach.to flash memory programming.
5-178
I
AP-325
APPENDIX B
SV
.--_. . .
_~--o()
Vpp
OUTPUT
200mA MAX
Vpp
COMMAND
292059-12
Figure 10. Basic flash memory Vpp voltage supply with ON/OFF control.
When Vpp COMMAND goes low, the Linear Technology LT1072 switching regulator produces 12V.
This circuit is just one example of a Vpp supply.
I
5-179
AP·325
APPENDIX C
QUICK-PULSE PROGRAMMING ALGORITHM
Bus
Operation
Command
Standby
Comments
Wait for Vpp Ramp
to VpPh (=12.0V)(1)
Initialize Pulse-Count
Write
Set-Up Program' Data = 40H
Write
Program
Standby
Duration of Program
Operation (tWHWH1)
Program(2) Verify Data = COH; Stops
Program Operation
tWHGL
Write
Standby
Valid Address/Data
Read
Read Byte to Verify
Programming
Standby
Compare Data
Output to Data
Expected
Write
Standby
Read
Data = OOH, Resets
the Register for
, Read Operations.
Wait for Vpp Ramp
to VPPI (1)
292059-13
NOTES:
1. The Vpp power supply can be hard-wired to the device or switchable. When Vpp.is switched, Vpp I may be ground,
no-connect with a resistor tied to ground. or less than Vee + 2.0V.
2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the
register Is written with the Read command.
3. CAUTION: The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
5-180
I
AP-325
APPENDIX D
WATCHDOG TIMER CIRCUIT
EPLD Source Code and Applications Contact Person
Thom Bowns_PLFG Applications
Intel
January 5, 1989
Rev. 008
5AC312
Watchdog timer to cut Vpp from FLASH if erase cycle too long.
OPTIONS: TURBO
ON
PART: 5AC312
=
INPUTS:
CLK, DO@3, Dl@4, D2@5, D3@S, D4@7, D5@8, DS@9, D7@10,
nCE@2, nWE@ll, TIMER_IN@13, RESET@14, AHR@15
OUTPUTS:
TIMCLR@23, TIMST@22, LED@21, VPP@20
NETWORK:
CLK = INP (CLK)
DO = INP (DO)
Dl = INP (Dl)
D2
INP (D2)
D3
INP (D3)
D4 = INP (D4)
D5 = INP (D5)
DS = INP (DS)
D7 = INP (D7)
nCE = INP (nCE)
nWE = INP (nWE)
TIMER_IN
INP (TIMER_IN)
RESET = INP (RESET)
% RESET active high if AHR is high
AHR = INP (AHR)
CONDI = NOCF (Cld)
% Conditions 1-4 are routed
% through combinatorial feedbacks
COND2 = NOCF (C2d)
COND3 = NOCF (C3d)
% to reduce product term count.
COND4
NOCF (C4d)
%
CLR
NOCF (CLRd)
=
=
=
=
EQUATIONS:
CLRd = RESET * AHR + !RESET * !AHR;
TIMEOUT = ITIMER_IN;
% Write
Cld = (/nCE * InWE * 20H) ;
% Write
C2d = (/nCE * InWE * aOH) ;
% Write
C3d = (/nCE * InWE * 120H) ;
% Write
C4d
(/nCE * InWE * IAOH) ;
20H = ID7 * IDS * ID5 * ID4 * ID3 * ID2
AOH
ID7 * IDS * ID5 * ID4 * ID3 * ID2
=
=
I
=
20 %
AO %
other
other
* IDI
* IDI
%
%
%
%
%
than 20 %
than AO %
* IDO;
* IDO;
5-181
intel®
AP-325
MATCHING:
CLOCK:
STATES:
START
Sl
S2
S3
S4
S5
S6
S7
WATCHDOG
CLK
1
1
1
1
1
1
LED
0
0
0
0
0
0
0
0
1
VPP
0
TIMST
0
0
1
1
TIMCLR
0
0
0
1
1
1
0
1
1
1
0
0
XSB
0
0
0
0
0
1
1
0
% TRANSITION STATEMENTS %
START: Sl
Sl:
IF CONDl
S2:
IF /CONDl
IF CLR
IF CONDl
S3:
IF COND3
IF CLR
S4:
S5
S5:
IF COND2
IF TIMEOUT
S6:
S7:
IF COND4
Sl
IF CLR
THEN
THEN
THEN
THEN
THEN
THEN
% From power up, go to Sl right away %
% If write 20, go to next state
%
% Until not write 20, hold
%
S2
S3
Sl
S4
S7
Sl
THEN S6
THEN S7
THEN S7
THEN Sl
% If
another write 20, start timer
% If write other than 20, error
%
%
% Trigger timer then go to S5 loop
% If write AO, stop timer
% If timer times out,
go to error state
% If write other than AO, error
% Stop timer and go back to Sl
% Error state. wait for a RESET.
%
%
%
%
%
%
END$
EPLD Pinout
5AC312
ClK
nCE
DO
01
vee
TIMClR
TIMST
lED
02
Vpp
03
GND
GND
GNO
GNO
AHR
RESET
TIMER_IN
04
05
06
07
nwt
GND
292059-14
5-182
I
AP-325
APPENDIX E
Checklist:
•
•
•
•
Most Common Mistakes that May Lead to Excessive Erasure
not programming all bytes to 00 data prior to erasure;
not observing the 6 J-LS set-up times between programming or erasure and verification;
attempting to program before Vpp is at 12V (Capacitive Load)
not latching the erase verify address with the erase verify command, or changing the address on the subsequent
read cycle;
Chapters three and four discuss the correct methods of developing and debugging code to diminish the possibility of
making these mistakes.
I
5-183
int:et
ER-24·
ENGINEERING
REPORT
Intel Flash Memory
28F256A
28F512
28FOIO·
28F020
October 1993
5-184
I
Order Number: 294008-007
Intel Flash Memory
28F256A, 28F512,28F010, 28F020
CONTENTS
PAGE
CONTENTS
PAGE
INTRODUCTION ....................... 5-186
DEVICE RELIABILITy ................. 5-187
TECHNOLOGY OVERViEW ........... 5-186
SUMMARy ............................ 5-188.
DEVICE ARCHITECTURE ............. 5-186
I
5-185
ER-24
INTRODUCTION
Intel's ETOX (EPROM tunnel oxide) Flash Memory
adds electrical chip erasure and reprogramming to
EPROM non-volatility and ease of use. Advances in
tunnel oxides and photolithography have made it possible to develop a double-polysilicon single-transistor
read/write random access nonvolatile memory, capable
of greater than 100,000 reprogramming cycles. Intel
Flash Memory electrically erases all bits in the array
matrix via electron tunneling. The EPROM programming mechanism of hot electron injection is employed
for electrical byte programming.
A command port interface, internal margin voltage
generation, power up/down protection and address and
data latches augment standard EPROM circuitry to
optimize Intel's Flash Memory for microprocessor-controlled reprogramming.
Read timing parameters on Intel's 28F256A, 28F512,
28FOIO and 28F020 are equivalent to those of CMOS
EPROMs, EEPROMs, 'and SRAMs. Access times as
fast as 65 ns result from a memory cell current of approximately. 50/kA, low' resistance poly-silicide wordlines, advanced scaled periphery transistors, and an optimized jIata-out buffer.
DEVICE ARCHITECTURE
Command Port
One feature which differentiates Intel's Flash Memory
is the command port architecture, illustrated in Figure
2.
The command port simplifies microprocessor control of
the erase, erase verify, program, program verify, and
read operations, without the need for additional control
pins or the multiplexing of high voltage with ~~nt:ol
functions. On-chip address and data latches mlmmlze
system interface logic and free the system bus during
erase and program operations. High voltage (12V) on
the Vpp pin enables the command port. In the absence
of this high voltage, the command port defaults to the
read operation, inhibiting erasure or programming of
the device.
EPROM Cell
SECOND LEVEL
POLYSILICON '\. '"
VG
~
.
.
Vs
TECHNOLOGY OVERVIEW
6+
... '.at.
,
Yl *I Ik
High quality tunnel oxide under the single floating
polysilicon gate promotes electrical erasure. All cells in
the array are simultaneously erased via FowlerNordheim tunneling. Applying 12V on the source junctions and grounding the select gates erases the entire
array in one second (typical). Programming is accomplished with the standard EPROM mechanism of hot
electron injection from the cell drain junction to the
floating gate. Programming is initiated by bringing both
the select gate and the cell drain to high voltage. Programming occurs at a rate of 10 /ks pulses per byte.
+Vo
GATE OXIDE
325A
N+
Intel's ETOX flash memory technology is derived from
its standard CMOS EPROM process base. Using advanced 1.0 /km and 0.8 /km double-polysilicon n-well
CMOS technology, Intel Flash Memory employs a
3.8 /km x 4.0 /km single transistor cell (1.0 /km) technology and a 2.5 /km x 2.9 /km single transistor cell
(0.8 /km technology), affording equivalent array density
as comparable EPROM technology. The flash memory
cell structure is identical to the EPROM structure, except for the thinner gate (tunnel) oxide. Figure 1 compares the flash memory cell to the EPROM cell.
FIRST LEVEL
POLYSILICON
(FLOATING)
N+
P-SUBSTRATE
294008-1
Flash Memory Cell
P-SUBSTRATE
294008-2
Figure 1. EPROM Cell vs. Flash Memory Cell
The command port consists of a command register,
command decoder and state latch, the data-in latch,
and the address latch. The command decoder output
directs the operation of the high voltage flash-erase
switch, program voltage generator, and the erase/program verify voltage generator.
Functions are selected via the command port in a microprocessor write cycle controlled by the Chip-Enable
and Write-Enable pins. Contents of the address latch
are updated on the falling edge of Write-Enable. The
rising edge of Write-Enable latches the command and
data registers, and initiates operations.
5-186
I
ER-24
Erasure
Erasure is achieved through a two-step write sequence.
The erase set-up code is written to the command register in the first cycle. The erase confirmation code is
written in the second cycle. The rising edge of this second Write-Enable pulse initiates the erase operation.
The command decoder triggers the high voltage flasherase switch, connecting the 12V supply to the source
of all bits in the array, while all wordlines are grounded. Fowler-Nordheim tunneling results in the simultaneous erasure of all bits.
The array source switch, shown in Figure 3, switches
high voltage onto the source junctions. During erasure,
the high voltage latch formed by Ms through Ms enables transistor MIs. Transistor MIS pulls the array
source up to 12V. Transistor M 16 pulls the source to
ground during read and program operations.
To obtain fast erase times, the device must supply the
grounded gate breakdown current which occurs on the
sources of the memory array. The upper boundary for
current sourcing capability of MIS is set by the maxi~
mum allowable substrate current. If Vpp is raised to
12V before Vee is above approximately 1.8V, the low
Vee detect circuit formed by transistors M 1 to ~
drives the node LOW Vee to 9V. Transistors M9 to
Mil then force the erase circuit into a non-erase state
with MIS off and M16 on. When Vee rises above 1.8V,
the chip will be reset into the read state.
Writing the erase verify code into the command register
terminates erasure, latches the address of the byte to
verify, and sets the internally-generated erase margin
voltage. The microprocessor then accesses the output
from the addressed byte using standard read timings.
The verify procedure repeats for all addresses. Should a
byte require more time to reach the erased state, another erase operation is applied. The erase and verify operations continue until the entire array is erased.
Programming
Programming follows a similar flow. The program setup command is written to the command register on the
first cycle. The second cycle loads the address and data
latches. The rising edge of the second Write-Enable
pulse initiates programming by applying high voltage to
the gates and drains of the bits to be programmed.
I
Writing the program verify command to the register
terminates the programming operation and applies the
program verify voltage to the newly programmed byte.
Again, the addressed byte can be read using standard
microprocessor read timings. Should the addressed byte
require more time to reach the programmed state, the
programming operation and verification are repeated
until the byte is programmed.
DEVICE RELIABILITY
Cell Margining
Erase and program verification ensure the data retention of the newly altered memory bits. The cell margining performed in the Quick-Pulse Programming and
Quick-Erase algorithms is more reliable than historical
overpulsing schemes as margining tests the amount of
charge stored on the floating gate.
Intel's 28F256A through 28F020 Flash Memories employ a unique circuit to internally generate the erase
and program verify voltages. Figure 4 shows a simplified version of the circuit. The circuit consists of a high
voltage switch and the verify voltage generator. Transistors M 1 through M4 constitute the high voltage
switch which disconnects Vpp from the resistor when
the device is not in the verify mode. The verify voltage
generator includes a resistor divider and a buffer. Internal margin voltage generation maintains microprocessor compatibility by eliminating the need for external
reference voltages.
Erase/Program Cycling
One of the most significant aspects of Intel Flash Memory is its capability for greater than 100,000 erase/program cycles. Destructive oxide breakdown has been a
limiting factor in extended cycling of thin oxide
EEPROMs. Intel's ETOX flash memory technology
extends cycling performance through: improved tunnel
oxide processing that increases charge carrying capability ten-fold; reduced oxide area under stress minimizing
probability of oxide defects in the region; and reduced
oxide stress due to a lower peak electric field (lower
erase voltage than EEPROM).
5-187
infel®
ER-24
A typical ceil erase/program margin (Vt) is shown as a
functiOn. of reprogramming cycles in Figure 5. After
100,000 reprogramming cycles, a 2.5V program read
margin exists, ensuring reliable data retention.
Reliable erase/program cycling also requires proper selection of the erase Vt maximum and maintenance of a
tight Vt distribution. The maximum erased Vt is set to
3.2V via the erase algorithm and the internal erase verify circuits. Superior oxide quality gives an erased Vt
distribution width that improves slightly with. cycling
(Figure 6). The tight erase Vt distribution gives an order of magnitude of erase time margin to the fastest
erasing cell (Figure 7).
SUMMARY
Intel's ETOX flash memory technology is a breakthrough in adding electrical chip-erasure to high-density EPROM technology. Intel's CMOS Flash Memory
offers the most cost-effective and reliable alternative for
read/write random access non-volatile memory. Microprocessor-compatible specifications, straightforward interfacing, and in circuit alterability allow designers to
easily augment memory flexibility and satisfy the need
for nonvolatile storage in today's designs.
FIXED OR GATED
Vpp
C E # - -__
~::::::l
WE#--~~;::=J
DATA
REPROGRAMMING
CONTROL CIRCUITS
ADDRESS
2940,08-4
Figure 2. Command Port Block Diagram
5-188
I
ER-24
ARRAY
SOURCE
ERASE--~------------+---------------~
294008-5
Figure 3. Array Source Switch
Vpp
Vpp
....._~Verlfy
Voltage
Enable>--------..a
High Voltage Switch
Verify Generator
294008-6
Figure 4. Erase/Program Verify Generator
I
5-189
ER-24
10.5
-
9
-
7.5
-
.....
!S
0
2::>
6
-
4.5
-
3
-
1.5
-
PROGRAM Vt MAX
-
PROGRAM Vt MIN
-
PROGRAM READ MARGIN
Vee MAX
Vee MIN
ERASE READ MARGIN
ERASE Vt MAX
ERASE Vt MIN
0
10
100
1000
10000
NUMBER OF CYCLES
100000
1M
294008-7
Figure 5. 1M Array Vt vs Cycles
99.99
99.9
g
99
c
!oJ
III
90
'"
III
50
<.l
10
..:
!oJ
..J
..J
!oJ
!oJ
~
:s::>
:::E
::>
0.1
u
0.01
0.001
0
ERASE Vt (VOLTS)
294008-8
Figure 6. Erase Vt Distribution vs Cycling
5-190
I
ER-24
8
7.5
7
6.5
6
5.5
5
en
>4.5
...J
0
4
~
3,5
3
en
..:
a:: 2.5
2
1.5
1
0.5
~
>
...
ERASE CELL Vt VERIFY LEVEL
...
FAST ERASE BIT
a
ERASE TIME (mS)
294008-9
Figure 7. Array Erase Vt vs Erase Time
I
5-191
294008-3
Figure 8. 28F256A Die Photograph
5-192
I
ER-24
294008-10
Figure 9. 28F512 Die Photograph
I
5-193
294008-11
Figure 10. 28F010 (1.0p,) Die Photograph
5-194
I
ER-24
294008-12
Figure 11. 28F020 Die (1.0/L) Photograph
I
5-195
ER-24
Byte-Wide Flash Memory in 32-Pin DIP
~
Vpp e
+ A16 +
+- r- A,s
2M
(256K x 8)
1M
(128Kx8)
512K
(64K x 8)
256K
(32K x 8)
~
1
32 :::I Vee
NC e
2
31 :::IWE#
NC e
3
30 :::I NC
A12 e
4
29 :::I A14
A7 e
5
28 :::I A13
A6e 6
As e
7
A4 e 8
A3
_c:
9
26 :::I Ag
0.800" WIDE
25 :::I All
TOP VIEW
24 :::I OE#
23 :::I A10
Al
e
11
22 :::I CE#
Ao
e 12
21 :::I D07
13
A,7
27 :::I As
32 PIN DIP
A2 e 10
DOO e
I - f-
20 :::I D06
DOle 14
19
:::1_ DOs
D02 e
15
18
::J
Vss e
16
17 :::I D03
D04
294008;-17
Figure 12. Flash Memory Pinouts
5-196
I
ER-24
Byte-Wide Flash Memory in 32·Pin PLCC
2M (256K X B)
lM(12BKXB)
512K (64K X B)
256K (32K X B)
NC
Vpp
Vee
WE#
Ag
OE#
CE#
D~
294008-18
Figure 13. Flash Memory Pinouts
I
5-197
intel®
ER-24
Byte-Wide Flash Memory in 32-Lead TSOP
E28F020
E28F010
A"
A,
As
A"
A,.
A17
WE"
Vee
Vpp
A"
A'5
A"
A,
A.
A5
A.
A"
A,
As
A"
A,.
NC
3'
STANDARD PINOUT
Ole Up "E"
32 LEAD TSOP
a mm x 20 mm
TOP VIEW
Vee
vpp
A,.
A'5
A"
A,
A,
A5
A,
2'
OE"
A,o
CEO
00.,
00,
005
DO,
DO,
GND
DO,
DO,
000
..
Ao
A,
A,
DE"
A,o
CEo
Do.,
DO,
005
DO,
DO,
GND
DO,
DO,
000
Ao
A,
A,
A,
294008-19
F28F020
F28F010
OE"
AIO
CEO
Do.,
DO.
005
DO,
DO,
GND
DO,
DO,
000
Ao
A,
A,
'A,
DE"
"0
CEo
Do.,
DO.
005
DO,
DO,
GND
DO,
DO,
000
Ao
A,
A,
A,
0
V
REVERSE PINOUT
Ole Down "F"
32 LEAD TSOP
8 mm X 20 mm
TOP VIEW
3'
.. ,
A,
As
A"
A,.
Ne
WE"
vee
vpp
...
"'5
A"
A,
As
A5
A,
A"
A,
As
"',
.. ,
A"
WE"
vee
Vpp
A"
A'5
A"
A,
A,
A5
A,
294008-20
Figure 14. Flash Memory Pinouts
5-198
I
ER-24
Columns are number 0 through 511 beginning with the column nearest the X-decoder.
Outputs are grouped as follows:
Left Half Array
100 101 102103
BL384 +- BLO
Array Organization:
Right Half Array
104 105 lOs 107
BLo~ BL384
Bitlines
Address
A14
A12
A10
A2
A1
Ao
A3
100& 107
101 & lOs
102 & 105
103& 104
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bl384
Bl385
Bl386
Bl387
Bl388
Bl389
Bl390
Bl391
Bl256
Bl257
Bl258
Bl259
Bl260
Bl261
Bl262
Bl263
Bl128
Bl129
Bl130
Bl131
Bl132
Bl133
Bl134
Bl135
Blo
Bl1
Bl2
Bl3
Bl4
Bl5
Bl6
Bl7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Bl508
Bl509
Bl510
Bl511
Bl380
Bl381
Bl382
Bl383
Bl252
Bl253
Bl254
Bl255
Bl124
Bl125
Bl126
Bl127
•
•
1
1
1
1
•
•
•
•
•
•
•
•
•
Figure 15. 28F256A Bitline Decoding
X Address
Row
..
A13
An
Ag
A8
WL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Xlo
Xl1
Xl2
Xl3
Xl4
Xl5
Xl6
Xl7
Xl8
Xl9
Xl10
Xln
Xl12
Xl13
Xl14
Xl15
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Xl16
Xl17
Xl18
Xl19
Xl20
Xl21
Xl22
Xl23
Xl24
Xl25
Xl26
Xl27
Xl28
Xl29
Xl30
Xl31
A7
As
A5
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
'0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Figure 16. 28F256A Wordlme Decodmg
I
5-199
•
ER-24
X Address
Row
A7
A6
As
A4
A13
A11
Ag
As
WL
0
0
1
0
0
0
0
0
XL32
0
0
1
0
•
•
1
1
1
XL47
0
0
1
1
1
1
XL48
•
•
•
•
•
•
..
1
1
•
•
1
0
0
0
0
XL63
0
0
0
0
XL64
0
0
0
1
0
0
•
•
•
•
0
1
•
•
•
•
•
•
•
•
1
XL80
1
0
•
1
0
0
0
0
XL95
1
1
1
0
0
0
0
0
XL234'
•
•
1
1
1
1
1
1
•
•
•
•
1
1
1
1
XL79
•
•
1
•
•••
1
•
•
1
•
1
0
1
•
1
1
•••
0
0
1
•
•••
0
1
1
•
1
0
0
1
1
•
•
•
•••
XL249
1
1
XL250
•
•
1
1
1
•
•
0
•
•••
1
1
0
•
0
0
•••
XL255
Figure 16. 28F256A Wordline Decoding (Continued)
Bit Map for
One Output
Array Organization
r---.---.---.-~,
,---r--~--~---.
R
wLo
°
WL1
WL2
WL3
W
S
E 1/00 1/01 1/02 1/03
L
E
C
T
S L -_ _L -__L -__
1/04 1/05 1/06 1/07
•
•
•
WL252
WL253
WL254
WL255
L-~
COLUMN SELECTS
BLO BL1 BL2 ... BL127
Figure 17. 28F256A Bit Map
5-200
I
ER-24
Columns are numbered 0 through Sl1 beginning with the column nearest the X-decoder.
Outputs are grouped as follows:
Left Half Array
02 03
00 01
Address
Right Half Array
04 05
06 07
Bitlines
A14
A15
A3
A10
A2
A1
AO
10017
101/06
102/05
103/04
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
BL384
BL385
BL386
BL38?
BL388
BL389
BL390
BL391
BL256
BL25?
BL258
BL259
BL260
BL261
BL262
BL263
BL128
BL129
BL130
BL131
BL132
BL133
BL134
BL135
BLO
BL1
BL2
BL3
BL4
BL5
BL6
BL?
1
1
1
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
BL508
BL509
BL510
BL511
BL380
BL381
BL382
BL383
BL252
BL253
BL254
BL255
BL124
BL125
BL126
BL12?
•
o·
•
•
•
•
•
•
•
•
•
•
Figure 18. 28F512 Bitline Decoding
X-DECODING: Wordlines are numbered 0 through Sl1 beginning at the top of the array.
X Address
Row
A12
A7
A6
A5
A4
A13
A11
A9
A8
WL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
XLO
XL1
XL2
XL3
XL4
XL5
XL6
XL?
XL8
XL9
XL10
XL11
XL12
XL13
XL14
XL15
XL16
XL1?
XL18
XL19
XL20
XL21
XL22
XL23
XL24
XL25
XL26
XL2?
XL28
XL29
XL30
XL31
0
0
0
0
0
0
0
0
0
0
Figure 19. 28F512 Wordline Decoding
I
5-201
ER-24
X-DECODING: Wordlines are number 0 through 511 beginning at the top of the array.
X Address
Row
A12
A7
AS
AS
A4
A13
A11
A9
A8
WL
0
0
0
1
0
0
0
0
0
XL32
0
0
0
1
1
1
0
0
0
1
•
•
•
1
0
0
0
0
XL63
1
0
0
0
0
0
XL64
•
•
0
•
1
1
XL79
1
1
1
XL80
•
•
•
•
0
0
0
0
•
0
0
0
0
1
•
1
1
•
1
•
0
•
0
•
•
1
•
0
0
1
0
1
•
1
1
1
1
1
1
1
XL47
1
1
XL48
•
1
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
0
0
0
0
XL95
1
0
0
0
0
XL480
•
•
0
•
1
1
1
1
XL495
1
1
1
1
1
XL496
0
0
0
XL511
0
1
•
1
•
1
1
•
1
•
0
1
•
•
1
0
•
1
1
1
1
1
•
•
•
•
•
•
0
•
1
1
•
•
•
•
0
•
•
•
•
•
Figure 19. 28FS12 Wordline Decoding (Continued)
Bitmap for
One Output
Array Organization
R
WLO
WL1
WL2
WL3
°
W
S
E 1/00 1/01
•
1/02
1/03
1/04
1/05 1/06
•
•
1/07
L
E
C
T
S
~
__L -__
L-~L-~
WL508
WL509
WL510
WL511
BLO BL1 BL2 ... BL127
Column Selects
Figure 20. 28FS12 Bit Map
5-202
I
ER-24
Columns are number 0 through 511 beginning with the column nearest the X-decoder.
Outputs are grouped as follows:
Right Half Array
104 105 lOs 107
BLo - - BL384
Left Half Array
100 10 1 10 2 103
BL384 ~ BLo
Array Organization:
Address
Bitlines
A16
A15
A10
A2
A1
Ao
A3
100& 107
101 & lOs
102 & 105
10 3 & 104
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
BL384
BL385
BL386
BL387
BL388
BL389
BL390
BL391
BL256
BL257
BL258
BL259
BL260
BL261
BL262
BL263
BL128
BL129
BL130
BL131
BL132
BL133
BL134
BL135
BLo
BL1
BL2
BL3
BL4
BL5
BL6
BL7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
BL508
BL509
BL510
BL511
BL380
BL381
BL382
BL383
•
0
.
"
1
1
1
1
..
..
..
"
"
0
.
BL252
BL253
BL254
BL255
BL124
BL125
BL126
BL127
Figure 21. 28F010 Bitline Decoding
X Address
Row
A14
A12
A7
As
As
A4
A13
A11
Ag
A8
WL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
XLo
XL1
XL2
XL3
XL4
XL5
XL6
XL7
XL8
XL9
XL10
XL11
XL12
XL13
XL14
XL15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
XL16
XL17
XL18
XL19
XL20
XL21
XL22
XL23
XL24
XL25
XL26
XL27
XL28
XL29
XL30
XL31
Figure 22. 28F010 Wordline Decoding
I
5-203
ER·24
X Address
Row
A14
A12
A7
As
As
A4
A13
A11
Ag
As
WL
0
0
0
0
1
0
0
0
0
XL32
•
0
•
•••
0
0
0
•
0
1
1
XL47
0
0
0
0
1
XL48
•
•
•
•
•
•
•
1
1
•
•
0
1
•
•
•
•
1
1
1
1
•
1
•
•
•
•••
0
0
0
0
1
1
0
0
0
0
XL63
0
0
0
1
0
0
0
0
0
0
XL64
•
•
•
•
•
•
0
0
0
0
0
0
•
•
•
0
1
1
0
1
1
0
0
0
XL95
1
0
0
0
0
0
XL992
1
XL1007
1
XL1008
0
XL1023
1
1
•
1
1
1
1
1
1
•
•
1
XL80
0
•
•
1
1
8
1
•
•
•
XL79
0
1
1
1
1
•
•••
1
1
•
•
1
•
1
1
1
•
0
1
•
•
0
0
1
•
1
•
0
•
•
•
1
0
1
1
1
1
1
•
•
•
1
•
1
•
•
1
0
1
1
•
0
0
•
•
•
•••
•••
•••
Figure 22. 28F010 Wordline Decoding (Continued)
Bit Map for
One Output
Array Organization
,---,--,,--,~-.
,---,--,,--,,--.
R
WLO
WL1
WL2
WL3
°
W
•
•
•
S
E 1/00 1/01
L
1102 1/03
E
C
WL1020
WL1021
WL1022
WL1023
T
S
COLUMN SELECTS
BLO BL 1 BL2 ... BL 127
Figure 23. 28F010 Bit Map
5-204
I
ER-24
Columns are number 0 through 511 beginning with the column nearest the X-decoder.
Outputs are grouped as follows:
Left Half Array
100101 102 103
BL384 +- BLO
Array Organization:
Right Half Array
104 105 lOs 107
BLO- BL384
Address
Bitlines
A1S
A10
A2
A1
Ao
A3
100 & 107
101 & 106
102 & 105
103& 104
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
BL384
BL385
BL386
BL387
BL388
BL389
BL390
BL391
BL128
BL129
BL130
BL131
BL132
BL133
BL134
BL135
BLo
BL1
BL2
BL3
BL4
BL5
BL6
BL7
0
0
.
BL256
BL257
BL258
BL259
BL260
BL261
BL262
BL263
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
BL508
BL509
BL510
BL511
BL380
BL381
BL382
BL383
. BL252
BL253
BL254
BL255
BL124
BL125
BL126
BL127
A16
o·
•
•
•
•
•
.
•
•
Figure 24. 28F020 Bitline Decoding
Row
X Address
A17
A14
A12
A7
A6
As
A4
A13
Al1
Ag
A8
WL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
XLo
XLl
XL2
XL3
XL4
XL5
XL6
XL7
XLB
XL9
XLlO
XL11
XL12
XL13
XL14
XL15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
XL16
XL17
XL1B
XL19
XL20
XL21
XL22
XL23
XL24
XL25
XL26
XL27
XL2B
XL29
XL30
XL31
Figure 25. 28F020 Word line Decoding
I
5-205
ER-24
X Address
Row
A17
A14
A12
A7
As
A5
A4
A13
All
Ag
0
0
0
0
0
1
0
0
•
0
0
•
•
•
•
0
0
0
0
0
0
0
0
•
0
0
•
•
•
•
0
0
0
0
0
0
0
•
•
0
1
•
•
•
0
0
0
0
0
0
0
•
•
0
0
0
•
•
0
1
1
1
1
XL47
1
1
1
..
1
1
XL48
•
•
1
0
XL63
0
0
0
0
0
0
XL64
•
•
•
•
•
•
0
1
0
1
•
•
1
•
0
•
1
0
0
0
0
XL95
0
0
0
0
XL992
1
1
1
1
1
1
1
0
•
•
•
•
•
1
1
•
•
•
1
1
1
1
1
•
•
•
•
•
1
1
1
1
•
•
1
0
1
1
1
1
1
•
1
1
1
1
1
•
•
1
•••
0
0
1
•••
0
1
0
1
•••
0
0
1
1
•
•
0
1
•
•
•
1
1
0
•
0
•
•
•
0
WL
XL32
1
•
•
AS
.0
1
1
1
1
1
•
•
1
1
1
1
1
•
•
1
1
0
1
•
1
1
1
1
•
•
1
•
•
1
1
•
•
1
XL79
1
1
XL80
•
•
•••
•
•
1
XL1007
1
1
XL1008
•
•
•••
•••
1
0
0
0
0
XL1023
1
0
0
0
0
XL2016
0
1
1
1
1
1
•
•
1
•
•
1
•
•
1
XL2031
1
1
XL2032
0
0
XL2047
•
•
0
•
0
•
•••
•••
Figure 25. 28F020 Wordline Decoding (Continued)
Bit Map for
One Output
Array Organization
,---,--,,--,~-,
,---,---,--,,--,
R
WLO
WL1
WL2
WL3
o
W
•
S
E
L
E
C
T
S
1/00 1/01
1/02 1/03
1104 1/05 II0s 1/07
•
•
WL2043
WL2045
WL2046
WL2047
L-__L-~L-~L-~
COLUMN SELECTS
BLO BL1 BL2 ... BL127
Figure 26. 28F020 Bit Map
5-206
I
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.6 Linearized : No Create Date : 2016:08:05 13:15:21-08:00 Modify Date : 2016:08:05 15:42:47-07:00 XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Metadata Date : 2016:08:05 15:42:47-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:7cc7ab62-d8d6-7640-960a-c82d0c910c14 Instance ID : uuid:46a1984a-ae59-224d-8d22-df80373232d6 Page Layout : SinglePage Page Mode : UseNone Page Count : 1602EXIF Metadata provided by EXIF.tools