1995_Micron_DRAM_Data_Book 1995 Micron DRAM Data Book
User Manual: 1995_Micron_DRAM_Data_Book
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ORRM
ORTR
BOOH
'
EDO DRAMs .................................................... . .
FPM DRAMs .................................................... . .
~c:JRAM ............................................................ ~
DRAM ~IMMs .................................................. _ _
DRAM DIMMs ..... ............................................. _ _
DRAM CARD~ .................. ... ......... ........... ..... ... _ _
TECHNICAL NOTE~ ........................................ . .
PRODUCT RELIABILITy................................. . .
PACKAc:JE INFORMATION .............................. . .
~ALE~ AND ~ERVICE INFORMATION ........... . . .
MICRON DATAFAX INDEX ..............................
II1II
DRAM DATA BOOK
2805 East Columbia Road
P.O. Box 6
Boise, Idaho 83707-0006
Telephone: 208-368-3900
Fax: 208-368-4431
Micron DataFaxsM : 208-368-5800
Customer Comment Line:
U.s.A. 800-932-4992
IntI. 01-208-368-3410
Fax 208-368-3342
©1995, Micron Technology, Inc.
Printed in the U.s.A.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Micron is a trademark of Micron Technology, Inc.
Micron DataFax is a service mark of Micron Technology, Inc.
ABOUT THE COVER:
Front - A variety of features highlight Micron's DRAM
product line. Shown at left, a circuitry backdrop rendered
from a scanning electron microscope. Bottom right, the
intricate memory of a 4 Meg DRAM wafer, etched in silicon,
which reflects the many hues of the natural color spectrum.
Back - Micron's Boise, Idaho, headquarters.
MIr-r""IIICN
1-· --.....
,
c
PREFACE
GENERAL INFORMATION
IMPORTANT NOTICE
Micron Technology, Inc. (Micron), reserves the
right to change products or specifications without notice. Customers are advised to obtain the
latest versions of product specifications, which
should be considered in evaluating a product's
appropriateness for a particular use. There is no
assurance that Micron's semiconductor products are appropriate for any application by a
customer.
MICRON MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, INCLUDING ANY
IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
PURPOSE, OTHER THAN COMPLIANCE
WITH MICRON'S SPECIFICATION SHEET
FOR THE PRODUCT AT THE TIME OF DELIVERY. IN NO EVENT SHALL MICRON BE
LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES AS A RESULT OF THE PERFORMANCE,ORFAILURETOPERFORM,OFANY
MICRON PRODUCT.
ANY CLAIM AGAINST MICRON MUST BE
MADE WITHIN 90 DAYS FROM THE DATE
OF SHIPMENT BY MICRON AND MICRON
HAS NO LIABILITY THEREAFTER. Micron's
PREFACE
Rev. 2195
liability is limited to replacement of defective
product or either Customer orMicron may elect
refund of amounts paid in lieu of replacement.
The warranty covers only defects arising under
normal use and not malfunctions resulting from
misuse, abuse, modification, or repairs by anyone other than Micron.
MICRON'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF
MICRON. Life support devices or systems are
those which are intended to support or sustain
life and whose failure to perform can be reasonably expected to result in a significant injury or
death to the user. Critical components are those
whose failure to perform can be reasonably
expected to cause failure of a life support device
or system or affect its safety or effectiveness.
MICRON DOES NOT WARRANT PRODUCT
TO BE FREE OF CLAIMS OF PATENT INFRINGEMENT BY ANY THIRD PARTY AND
DISCLAIMS ANY SUCH WARRANTY OR
INDEMNIFICATION AGAINST PATENT INFRINGEMENT.
Micron Technology, Inc., reserves the rlg~11o change p(Qducts or specifications without notice.
@1995,MicronTechnology,lnc.
PREFACE
GENERAL INFORMATION
I'IIIC::I=U?,N
PREFAQE,
Rev. 2195
ii
Micron Technology, Inc., reserves the right to change products:=~=~=~::
\
MICRON
1-·
PREFACE
GENERAL INFORMATION
","",w"""
Dear Customer:
Micron Technology, Inc., is dedicated to the design,
manufacture and marketing of high-quality, highly reliable
memory components. Our corporate mission is:
"To be a world-class team.
developing advantages for our customers."
. At Micron, we are investing time, talent and resources
to bring you the finest DRAMs, SRAMs and other specialty
memory products. We have developed a unique intelligent
burn-in system, AMBYX®, which evaluates and reports the
quality level of each and every component we produce.
We are dedicated to continuous improvement of all our
products and services. This means continual reduction of
electrical and mechanical defect levels. It also means the
addition of new services such as "just-in-time" delivery
and electronic data interchange programs. And when you
have a design or application question, you can get the
answers you need from one of Micron's applications
engineers.
We're proud of our products, our progress and our
performal1ce. And we're pleased that you're choosing
Micron as your memory supplier.
The Micron Team
PREFACE
Rev. 2195
iii
Micron Technology, Inc., reserves the nght to change products or speCifications without notice.
©1995,MicronTachnology, Inc.
AMBYX is a registered trademark of Micron Technology, Inc.
UII::::I=ICN
1-·
PREFACE
GENERAL INFORMATION
'"''MOO'''
ADVANTAGES
MICRON DATAFAxsM
Micron Technology brings quality, productivity and
innovation together to provide advantages for our customers. Our products feature some of the industry's
fastest speeds. And we establish delivery standards based
on customer expectations, including JIT programs, made
possible by ever-increasing product reliability.
When you can't afford to wait for critical product
information or specifications, Micron offers a convenient
solution available 24 hours a day, every day. Micron
DataFax enables you to make automated requests for
data sheets, product literature, and other information
from your fax machine. Just dial 208-368-5800 from your
fax machine and Micron DataFax will give you instructions on how to order documents, including an index of
documents. Once your order is placed, Micron DataFax
will process your order, faxing up to two documents per
call to your fax machine.
COMPONENT INTEGRATED CIRCUITS
Micron entered the memory market in 1978, first designing, then manufacturing dynamic random access
memory (DRAM). From there, we developed high-performance fast static RAM (SRAM) and a variety of other
memory products.
QUALITY
Quality is the most important thing we provide to
Micron customer with each Micron shipment. That's
because we believe that quality must be internalized
consistently at each level of our company. We provide
every Micron team member with the training and motivation needed to make Micron's quality philosophy a
reality.
One way we have measurably improved both productivity and product quality is through our own quality
improvement program formed by individuals throughout the company. Micron quality teams get together to
address a wide range of issues within their areas. We
consistently and regularly perform a company-wide selfassessment based on the Malcolm Baldrige National
Quality Award criteria. We've also implemented statistical process controls to evaluate every facet of the memory
design, fabrication, assembly and shipping process. And
our AMBYXintelligent burn-in and test system** gives
Micron a unique edge in product reliability.
These quality programs have resulted in Micron becoming one of the first U.S. semiconductor manufacturers to receive ISO 9001 certification: ISO 9001 is the most
comprehensive level of certification in the internationally
recognized ISO family of specifications. The certification
implies that Micron's systems for accepting orders, reviewing customers' specifications, manufacturing and
testing products, and delivering those products to its
customers are quality controlled and produce consistent
results.
~very
SPECIALTY MEMORY PRODUCTS
Beyond our standard component memory, Micron is
introducing many new products, including nonvolatile
flash memory, 64 Meg DRAM, and synchronous graphics
RAM, and continues to offer the broadest line of 3.3V
SRAMs available. Micron is forging ahead into new and
exciting frontiers by evaluating 8-inch wafer development and its processing capabilities.
We are pleased to be first to market with our compact,
easy-to-install 88-pin DRAM card. Ideal for laptop, notebook and other portable systems, Micron's DRAM Card
offers both high density and low power within JEDEC
and JEIDA specifications.*
DIE SALES
In addition to our durable packaging, Micron leads the
industry in bare die procurement and the testing of
Micron's KGDPlu,® (known good die). Demand for these is
increasing for use in highly specialized applications.
Micron's bare die products are available both in 6" wafers
and wafflepacks.
CUSTOM MANUFACTURING SERVICES
For total project management, Micron offers valueadded services. These include both standard contract
manufacturing services for system-level products include
ing design, assembly, customer kitted assembly, comprehensive quality testing or shipping as well as complete
turnkey services covering all phases of production. Our
component and system-level manufacturing facilities
are located in Boise, Idaho, so the component products
you need are readily available.
*See NOTE, page v.
**For more information on AMBYX, see Section 8.
PREFACE
Aev.2195
iv
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
KGDPIus is a registered trademark of Micron Technology, Inc.
Micron DataFax is a service mark of Micron Technology, Inc.
MIC:RON
1-·
PREFACE
GENERAL INFORMATION
'","'cco","
DATA SHEET SEQUENCE
Data sheets in this book are ordered first by width and
second by depth.· For example, the EDO DRAM section
begins with the 1 Meg x 4 followed by all other x4 configurations in· order of ascending depth. Next come the x8
products, etc., as applicable to the specific product family.
ABOUT THIS BOOK
CONTENT
The 1995 DRAM Data Book from Micron Technology
provides complete specifications on Micron's standard
DRAMs, synchronous graphics RAM (SGRAM), DRAM
modules and DRAM cards.
The DRAM Data Book is one of three product data books
Micron currently publishes. Its two companion volumes
include our SRAM Data Book and Flash Memory Data Book.
DATA SHEET DESIGNATIONS
As detailed. in the. table below, each Micron product
data sheet is classified as either Advance, Preliminary (indicated on the top of each data sheet) or Final (final data
sheets have no marking). In addition, new product data
sheets that are new additions are deSignated with a "New"
indicator in the tab area of each page.
SECTION ORGANIZATION
Micron's 1995 DRAM Data Book contains a detailed Table
of Contents with sequential and numerical indexes of products as well as a complete product selection guide. The Data
Book is organized into twelve sections:
•
•
•
•
•
•
SURVEY
We have included a removable, postage-paid survey
form in the front of this book. Your time in completing and
returning this survey will enhance our efforts to continually
improve our product literature.
For more information on Micron product literature, or to
order additional copies of this publication, contact:
Sections 1-6: Individual product families. Each
contains a product selection guide followed by
data sheets.
Section 7: Technical notes.
Section 8: Summary of Micron's unique
quality and reliability programs ,and testing
operation, including our AMBYX intelligent
burn-in and test system.*
Section 9: Packaging information.
Section 10: Customer service notes and sales
information, including a list of sales representatives and distributors worldwide.
Section 11: Micron DataFax index.
Micron Technology, Inc.
2805 East Columbia Road
P.O. Box 6
Boise, ID 83707-0006
Phone: 208-368-3900
Fax: 208-368-4431
Micron DataFax: 208-368-5800
Customer Comment Line:
U.s.A. 800-932-4992
Intl. 01-208-368-3410
Fax 208-368-3342
DATA SHEET DESIGNATIONS
DATA SHEET MARKING
DEFINITION
Advance
This data sheet contains initial descriptions of products still under development.
Preliminary
This data sheet contains initial characterization limits that are subject to change upon full
characterization of production devices.
No Marking
This data sheElt contains minimum and maximum limits specifiedoverthe complete power
supply and temperature range for production devices. Although considered final, these
specifications are subject to change, as further product development and data characterization sometimes occur.
New
This data sheet (which may be either Advance, Preliminary or Final) is a new addition to
the data book.
NOTE:
Micron uses acronyms to refer to certain industry-standard-setting bodies. These are defined below:
EIAIJEDEC-Electronics Industry Association/Joint Electron Device Engineering Council
JEIDA-Japanese Electronics Industry Development Association
PCMCIA-Personal Computer Memory Card International Association
'Micron's Quality/Reliability Handbook is available by calling 208-368-3900.
PREFACE
Rev. 2/95
v
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©t 995, Micron Technology, Inc.
MICRON
1-·
PREFACE
PRODUCT NUMBERING
"'~"wc,,"
EXPANDED COMPONENT NUMBERING SYSTEM
AA BS CC DODD
I
-Ll..-L
FFF -GG
zzzz
-L-L -L
TIT··.11--,---c...__
MT4C40010J-7
MDRicAroMn
CMOS
1 Meg x 4
I
-
-
Processing Codes
lOns Access Time
SOJ Package
I
AA - PRODUCT LINE IDENTIFIER
FFF - PACKAGE CODES
Micron Product ................................................................ MT
PLASTIC
DIP ............................................................................ Blank
DIP (Wide Body) """"""".""""""""""""""""""""""". W
ZIP .................................................................................... Z
BB - PRODUCT FAMILY
DRAM .................................................................................. 4
SRAM .................................................................................. 5
~ •.....••.•••...•.•••.......•••........••.•.....•.•••........••••••....••••••..... ~
SOP/SOIC ...................................................................... SG
Q~ ................................................................................. ~
TSOP (Type I) ."""""""""""""""""""""""""""""""" VG
TSOP (Type I, Reversed) ............................................... XG
TSOP (Type II) ............... :................................................ TG
TSOP (Reversed) ........................................................... RG
TSOP (Longer) .. ;............................................................ TL
SOJ ................................................................................. OJ
SOJ (Reversed) ............................................................. DR
SOJ (Longer) """"""""""""" .. """"""""""""""""."". DL
CC - PROCESS TECHNOLOGY
CMOS .................................................................................. C
Low Voltage CMOS ............................................................ LC
DODD - DEVICE NUMBER
(Can be modified to indicate variations)
DRAM ............................................................. Width, Density
TPDRAM ......................................................... Width, Density
SRAM .......................................................... Total Bits, Width
Synchronous SRAM ....................................... DenSity, Width
E - DEVICE VERSIONS
(Alphabetic characters only; located between D and F when
required.)
JEDEC Test Mode (4 Meg DRAM) ....................................... J
Errata on Base Part .............................................................. Q
PREFACE
Rev. 2/95
vi
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
UU::::RCN
1-·
,","00,0"
PREFACE
PRODUCT NUMBERING
cc
EXPANDED COMPONENT NUMBERING SYSTEM (continued)
AA BB CC DODD
C~M~AOroMSn
FFF -GG
zzzz
-L 1.. -1.
I
....L....L ---L
MT4C40010J-7
I
TT
I
1TL.._-----c....
__ ~~~~e~~~:s;~::
-
SOJ Package
1 Meg x 4 - - - - - - - '
DRAMs
Low Power (Extended Refresh) ........................................ L
Low Power (Self Refresh/Extended Refresh) .................... S
SRAMs
Low Volt Data Retention ............................... :................... L
Low Power ....................................................................... P
Low Power, Low Volt Data Retention ............................. LP
EPI Wafer· ............................................................................ E
Operating Temperature Range
O°C to +70°C ............................................................. Blank
-40°C to +85°C ................................................................ IT
-40°C to +125°C ............................................................. AT
-55°C to +125°C ............................................................. XT
Special ProceSSing
Engineering Sample ........................................................ ES
Mechanical Sample ....................................................... MS
Sample Kit* .................................................................... SK
Tape-and-Reel* .............................................................. TR
Bar Code * ....................................................................... BC
GG - ACCESS TIME
-5 ...................................................................... 5ns or 50ns
-6 ...................................................................... 6ns or 60ns
-7 ...................................................................... 7ns or 70ns
-8 ...................................................................... 8ns or 80ns
-10 .................................................................. iOns or 100ns
-12 .................................................................. 12ns or 120ns
-15 .................................................................. 15ns or 150ns
-17 ................................................................................. 17ns
-20 ................................................................................. 20ns
-25 ................................................................................. 25ns
-35 ................................................................................. 35ns
-45 ................................................................................. 45ns
-53 ................................................................................. 53ns
-55 ................................................................................. 55ns
zz ZZ -
PROCESSING CODES
(Multiple processing codes are separated by a space and are
listed in hierarchical ordeL)
Example:
A DRAM supportIng low power, extended refresh (L); low voltage
(V) and the IndustrIal temperature range (IT) would be indicated as
V LIT.
*Used in device order codes; this code is not marked on device.
Interim .................................................................................. I
Low Voltage .......................... c•••••••••••••••••••••••••••••••••••••••••••••• V
PREFACE
Rev. 2195
vii
Micron Technology, Inc., reserves the- right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PREFACE
PRODUCT NUMBERING
'''''"'co"'''
NEW COMPONENT NUMBERING SYSTEM
AA BB CC DDDDDD EE FFF ·GG ZZ ZZ
I
~.....L-L---.L
111
---.l......L 1.
Micron
DRAM
CMOS
1 Meg x 16
TJ
MT4C1 M16A 1 DJ-8 VL
I
I
~
-
-
M ............................................................................. Megabits
AA - PRODUCT LINE IDENTIFIER
G............................................................................... Gigabits
Micron Product .............................................:.................. MT
Flash ................................................... Density, Configuration
BB - PRODUCT FAMILY
EE - DEVICE VERSIONS
Flash (Dual Supply) ........................................................... 28
DRAM .................................................................................. 4
SGRAM .............................................................................. 41
Synchronous DRAM .......................................................... 48
SRAM .................................................................................. 5
Synchronous SRAM .......................................................... 58
(The first character is an alphabetic character only; the
second character is a numeric character only.)
Specified by individual data sheet.
FFF - PACKAGE CODES
Plastic
DIP ............................................................................ Blank
DIP (Wide Body) .............................................................. W
CC - PROCESS TECHNOLOGY
CMOS .................................................................................. C
Low Voltage CMOS ............................................................ LC
BiCMOS ............................................................................... B
Low Voltage BiCMOS ........................................................ LB
Flash CMOS ......................................................................... F
Low Voltage Flash CMOS .................................................. LF
AP Flash CMOS ................................................................. AF
~P
SOP/SOIC ...................................................................... SG
OFP ................................................................................. LG
TSOP (Type II) ............................................................,... TG
TSOP (Reversed) ........................................................... RG
TSOP (Longer) ......................................... ;..................... TL
SOJ ................................................................................. DJ
SOJ (Wide) ................................................................... DW
SOJ (Reversed) ............................................................. DR
SOJ (Longer) .................................................................. DL
Depth, Width
~
.................................................................................... Z
~ ................................................................................. ~
DDDDDD - DEVICE NUMBER
Example:
lM16 ~ 1 megabit deep by 16 bits wide
memory.
Low Voltage, L~w Power (Extended Refresh)
70ns Access Time
SOJ Package
Data Sheet Defined
16 megabits of total
No Letter ......................................................................... Bits
K................................................................................ Kilobits
PREFACE
Rev. 2195
viii
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
PREFACE
PRODUCT NUMBERING
"'~"'wc,"'
1-·
NEW COMPONENT NUMBERING SYSTEM (continued)
AA BB CC DDDDDD
I
- L 1- 1.
TJ
EE
FFF -GG 11 11
11T.
--..L -L.-L ----.L
MT4C1M16A1DJ-8VL
Micron
DRAM
CMOS
1 Meg x 16
.I
-
I.
-
~
.
DRAMs
Low Power (Extended Refresh) ........................................ L
Low Power (Self Refresh/Extended Refresh) .................... S
SRAMs
Low Volt Data Retention ......•........................ :................... L
Low Power ....................................................................... P
Low Volt Data Retention, Low Power ............................. LP
Flash
3.3V Read (AP) ................................................................. V
Bottom Boot Block ........................................................... B
Top Boot Block ................................................................. T
EPI Wafer ................................................................:........... E
Commercial Testing
O°C to +70°C ............................................................. Blank
-40°C to +85°C ............................................................... IT
-40°C to +125°C ............................................................. AT
-55°C to +125°C .................................................:........... XT
Special Processing
Engineering Sample .............. :..................... :................... ES
Mechanical Sample ....................................................... MS
Sample Kit* .................................................................... SK
Tape-and-Reel* ........................................•..................... TR
Bar Code * ....................................................................... BC
GG - ACCESS TIME
-5 ...................................................................... 5ns or 50ns
-6 ...................................................................... 6ns or 60ns
-T ...................................................................... 7ns or 70ns
-8 ...................................................................... 8ns or 80ns
-9 ...................................................................... 9ns or 90ns
-10 .................................................................. iOns or 100ns
-12 ...............•.................................................. 12ns or 120ns
-15 .................................................................. 15ns or 150ns
-17 ................................................................................. 17ns
'20 ................................................................................. 20ns
-25 .................................................................................. 25ns
-35 ................................................................................. 35ns
-45 ................................................................................. 45ns
-53 ................................................................................. 53ns
-55 ................................................................................. 55ns
zz ZZ -
PROCESSING CODES
(Multiple processing codes are separated by a space and are
listed in hierarchical order.)
Example:
A DRAM supporting low power, extended refresh (L); low voltage
(V) and the industrial temperature range (IT) would be indicated as
V LIT.
* Used in device order ,?odes; this code is not marked on device,.
Interim .................................................................................. I
Low Voltage ......................................................................... V
PREFACE
Rev. 2195
Low Voltage, L~w Power (Extended Refresh)
70ns Access Time
SOJ Package
Data Sheet Defined
ix
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
MIC:RON
1-·
PREFACE
PRODUCT NUMBERING
"'"'0"","
MODULE NUMBERING SYSTEM
AA
BB CDDDEEEFFF GG HH JJ KK
---L ---.L L L.l-L -L -..L.' --L .-L
MT12LD136xxG-7 L
Micron
12 Components
3.3 Volt
DRAM Module
1 Meg
-==r-2fr11T~T
L-.
..
I
DRAM Low Power
70ns ACcess Time
Gold Plating
Device Version
1'--_ _ _ _ _ _ x36
JJ - ACCESS TIME
-10 ................................................................................. 10ns
-12 ................................................................................. 12ns
-15 ................................................................................. 15ns
-17 ................................................................................. 17ns
-20 ................................................................................. 20ns
-25 ................................................................................. 25ns
AA - PRODUCT LINE IDENTIFIER
Micron Product ................................................................ MT
BB - NUMBER OF MEMORY COMPONENTS
C - PROCESS TECHNOLOGY
LOW VOLTAGE (3.3V) ......................................................... L
DOD - RAM FAMILY
~ ...•............................................................................. ~~
DRAM .................................................................................. D
DRAM TSOP ...................................................................... DT
SRAM .................................................................................. S
SRAM TSOP ...................................................................... ST
SYNCHRONOUS SRAM ..................................................... SY
SYNCHRONOUS SRAM TQFP .......................................... SYT
-6 ................................................................................... 60ns
-7 ................................................................................... 70ns
~ ................................................................................... 8~s
KK - MODULE SPECIAL DESIGNATOR
SRAM
2V data retention .............................................................. L
Low Power ....................................................................... P
Low Power, 2V data retention ........................................ LP
DRAM
Low Power (Extended Refresh) ........................................ L
ECC ................................................................................... C
Extended Data Out ............................................................ X
Self Refresh ...................................................................... S
16 Meg DRAM 4,096 Refresh ........................................... A
EEE-DEPTH
FFF-WIDTH
GG - DEVICE VERSIONS
Specified by individual data sheet (Synchronous SRAM only)
HH - PACKAGE CODE
Gold Plated SIMM/DIMM .................................................... G
~P
....................................................................................... Z
SIP ...................................................;.................................. N
SIMM/DIMM ....................................................................... M
Small Outline DIMM ............................................................ H
Small Outline Gold DIMM ................................................. HG
Double-Sided SIMM (1 or 4 Meg x 36 Only) ................... DM
Double-Sided SIMM (Gold 1 or 4 Meg x 36 Only) ............ DG
PREFACE
Rev. 2/95
x
Micron Technology, Inc., reserves the right to change products or specifications without'notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PREFACE
PRODUCT NUMBERING
'"''''''00'''
DRAM CARD NUMBERING SYSTEM
AA BB
ecce
DOD EE
FF -G H
----L.l
I
.1-L -L....L -.L
MT8D88C132VH-8S
----=::r-T I IT~L
L.-
Micron
8 Components
.88-Pin DRAM Card - - - - - - - ' .
1 Meg _ _ _ _ _ _--...J
AA - Product Line Identifier
Special Designator
80ns Access Time
Special Designator
x32
G - ACCESS TIME
-5 ................................................................................... 50ns
-6 ................................................................................... 60ns
-7 ......................................................... ,......................... 70ns
-8 ................................................................................... 80ns
Micron Product ................................................................ MT
BB - NUMBER OF MEMORY COMPONENTS
CCCC - DRAM CARD DESIGNATOR AND PIN COUNT
88-Pin DRAM Card ....................................................... D88C
H- SPECIAL DESIGNATOR
Self Refresh ......................................................................... S
DDD-DEPTH
EE-WIDTH
FF - SPECIAL DESIGNATOR
3.3 Volts .............................................................................. V
Reduced length (2") ............................................................. H
PREFACE
Rev. 2195
xi
Micron Technology, Inc., rese!ves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PREFACE
PRODUCT NUMBERING
",","we,,,,,
DIE PRODUCT NUMBERING SYSTEM
AA BBCC 000000
I
----L .1...1..
EEEE
F GG·HH
I . . L -L ...L
MT4C4001J D30ADC2-7
Micron
DRAM
CMOS
1 Meg x 4
~TTTTL1
70ns Access Time
Hot Speed Probe
Die Form (individual)
1 ' - - - - - - - - D30A Die Data Base
AA - PRODUCT LINE IDENTIFIER
Component Product ......................................................... MT
EEEE - DIE DATA BASE REVISION
F-FORM
Die Form .............................................................................. 0
Wafer Form (6" Wafer) .................... :.................................. W
BB - PRODUCT FAMILY
SRAM .................................................................................. 5
DRAM .................................................................................. 4
Synchronous SRAM .......................................................... 58
GG - TESTING LEVELS
Standard Probe (0 0 to 70°C) ............................................. C1
Hot Speed Probe (0 0 to 70°C) ........................................... C2
Known Good Die (0 0 to 70°C) ........................................... C3
KG DPlus® ............................................................................ C7
CC - PROCESS TECHNOLOGY
CMOS .................................................................................. C
Low Voltage CMOS ............................................................ LC
000000 - DEVICE NUMBER
HH - ACCESS TIME
When no alpha character appears as part of this section, the
section is defined as:
DRAM ............................................................. Width, Density
SRAM .......................................................... Total Bits, Width
Synchronous SRAM ......................................... Depth, Width
(Applicable for C2 and C3 only)
·5 ............................................................. 5ns or 50ns
·6 ............................................................. 6ns or 60ns
·7 ............................................................. 7ns or 70ns
·8 ............................................................. 8ns or 80ns
·9 ............................................................. 9ns or 90ns
·10 ........................................................ 1Ons or 100ns
·12 ........................................................ 12ns or 120ns
·15 ........................................................ 15ns or 150ns
·17 ....................................................................... 17ns
·20 ....................................................................... 20ns
·25 ....................................................................... 25ns
·35 ....................................................................... 35ns
·45 ....................................................................... 45ns
·50 (SRAM only) .................................................. 50ns
·SS (C2 only) .......................................... speed sorted
When an alpha character occurs as part of this section, the
section is defined as:
Depth, Width
Example:
IM16 = 1 megabit deep by 16 bits wide = 16 megabits of total
memory.
No Letter ......................................................................... Bits
K................................................................................ Kilobits
M ............................................................................. Megabits
G............................................................................... Gigabits
PREFACE
Rev. 2195
xii
Micron Technology, Inc., reserves the right to change products or specJficalions without nolice.
©1995, Micron Technology, Inc.
KGD .... is a registered trademark of Micron Technology, Inc,
MICRON
1-·
PREFACE
TABLE OF CONTENTS
",","owe,,",
EDODRAMs
PAGE
MT4C4007J ............................................................. 1 Meg x 4
MT4C4007J s .......................................................... 1 Meg x 4
MT4LC4007J .......................................................... 1 Meg x 4
MT4LC4007J s ....................................................... 1 Meg x 4
MT4LC4M4ES ....................................................... 4 Meg x 4
MT4LC4M4ES S .................................................... 4 Meg x 4
MT4LC16M4G3 ................................................... 16 Meg x 4
MT4LC16M4H9 .................................................. 16 Meg x 4
MT4LC2MSE7 ....................................................... 2 Meg x S
MT4LC2MSE7 S .................................................... 2 Meg x S
MT4LCSMSP4 ....................................................... S Meg x S
MT4LCSMSC2 ....................................................... S Meg x S
MT4C16270 ............................................................. 256K x 16
MT4LC16270 .......................................................... 256K x 16
MT4LCIM16E5 ..................................................... 1 Meg x 16
MT4LCIMI6E5 S .................................................. 1 Meg x 16
5V................................................................................
5V,S ............................................................................
3.3V.............................................................................
3.3V,S .........................................................................
3.3V,2KR ....................................................................
3.3V, 2KR, S ...............................................................
3.3V, SKR....................................................................
3.3V, 4KR ....................................................................
3.3V,2KR ....................................................................
3.3V, 2KR, S ...............................................................
3.3V, SKR....................................................................
3.3V, 4KR....................................................................
5V, DC ........................................................................
3.3V, DC .....................................................................
3.3V, DC, lKR............................................................
3.3V, DC, lKR, S ........................................................
DC ..... .
lKR
4KR
2KR ................................................ .
BKR .... .
5V ..
.......................... Dual CAS
.. ..................... 2,048 Refresh
.. .............. 8,192 Refresh
........................ 5 volt Vee
5 ...
3.3V ......
.................................................. 1,024 Refresh
.......... 4,096 Refi:esh
..... SELF REFRESH
.3.3 volt Vee
FPMDRAMs
PAGE
MT4CI004J ............................................................ 4 Meg x 1
MT4C1004J s ......................................................... 4 Meg x 1
MT4C400lJ ............................................................. 1 Meg x 4
MT4C400lJ s .......................................................... 1 Meg x 4
MT4LC4001J .......................................................... 1 Meg x 4
MT4LC4001J s ....................................................... 1 Meg x 4
MT4C4004J ............................................................. 1 Meg x 4
MT4C4M4Bl .......................................................... 4 Meg x 4
MT4LC4M4Bl ....................................................... 4 Meg x 4
MT4LC4M4Bl S .................................................... 4 Meg x 4
MT4LC16M4A7 ................................................... 16 Meg x 4
MT4LC16M4TS ................................................... 16 Meg x 4
MT4LC2MSBI ....................................................... 2 Meg x S
MT4LC2MSBI S .................................................... 2 Meg x S
MT4LCSMSEI ....................................................... S Meg x S
MT4LCSMSB6 ....................................................... S Meg x S
MT4C16257 .............................................................. 256K x 16
MT4LC16257 ........................................................... 256K x 16
MT4LC16257 S ........................................................ 256K x 16
MT4C1MI6C3 ....................................................... 1 Meg x 16
MT4LC1M16C3 ..................................................... 1 Meg x 16
MT4LCIM16C3 S .................................................. 1 Meg x 16
DC
lKR.
4KR .. ..
5 .... ..
3.3V ..................... .
PREFACE
Rev. 2195
1-1
1-1
1-15
1-15
1-31
1-31
1-47
1-47
1-63
1-63
1-77
1-77
1-91
1-107
1-123
1-123
............ Dual CAS
.. .... 1,024 Refresh
... 4,096 Refresh
...... SELF REFRESH
.. ...... 3.3 volt Vee
xiii
5V................................................................................
5V, S ............................................................................
5V ................................................................................
5V, S .. :.........................................................................
3.3V .............................................................................
3.3V, S .........................................................................
5V, QC ........................................................................
SV,2KR.......................................................................
3.3V, 2KR ....................................................................
3.3V, 2KR, S ...............................................................
3.3V, SKR....................................................................
3.3V, 4KR ....................................................................
3.3V,2KR....................................................................
3.3V, 2KR, S ...............................................................
3.3V, SKR....................................................................
3.3V,4KR ....................................................................
5V, DC ........................................................................
3.3V, DC ................................................................ :....
3.3V, DC,S.................................................................
5V, DC, lKR...............................................................
3.3V, DC, 1KR............................................................
3.3V, DC, 1KR, S ........................................................
QC .. .
2KR .. ..
BKR .... ..
5V .... .
2-1
2-1
2-15
2-15
2-29
2-29
2-41
2-53
2-65
2-65
2-79
2-79
2-91
2-91
2-105
2-105
2-117
2-131
2-131
2-147
2-163
2-163
..... QuadCAS
......... 2,048 Refresh
.. 8,192 Refresh
.................................. " .......... 5 volt Vee
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, !nco
MIC:RON
1-·
PREFACE
TABLE OF CONTENTS
'''",cccc""
SGRAM
PAGE
MT41LC256K32D4 ................................................. 256Kx32
MT41LC256K32D4 5 .............................................. 256K x 32
S ...... .
.................... SELF REFRESH
3.3V .............................................................................
3.3V, 5 .........................................................................
3.3V ......
......................... . ............................... 3.3 volt Vee
DRAM SIMMs
PAGE
MT2D18 .................................................................. 1 Meg x 8
MT2D48 .................................................................. 4 Meg x 8
MT8D48 .................................................................. 4 Meg x 8
MT3D49 .................................................................. 4 Meg x 9
MT9D49 .................................................................. 4 Meg x 9
MT2D25632 .............................................................. 256K x 32
MT4D51232 .............................................................. 512K x 32
MT8D132 ................................................................ 1 Meg x 32
MT8D132 5 ............................................................. 1 Meg x 32
MT8LD(T)I32 ........................................................ 1 Meg x 32
MT8LD(T)I32 5 ..................................................... 1 Meg x 32
MT8LD(T)I32 X .................................................... 1 Meg x 32
MT8LD(T)I32 XS .................................................. 1 Meg x 32
MT16D232 .............................................................. 2 Meg x 32
MT16D232 5 ........................................................... 2 Meg x 32
MT16LD(T)232 ...................................................... 2 Meg x 32
MT16LD(T)232 5 ................................................... 2 Meg x 32
MT16LD(T)232 X .................................................. 2 Meg x 32
MT16LD(T)232 XS ................................................ 2 Meg x 32
MT4LD232 ............................................................. 2 Meg x 32
MT4LD232 5 .......................................................... 2 Meg x 32
MT4LD232 X .......................................................... 2 Meg x 32
MT4LD232 XS ....................................................... 2 Meg x 32
MT8D432 ................................................................ 4 Meg x 32
MT8D432 5 ............................................................. 4 Meg x 32
MT8LD432 ............................................................. 4 Meg x 32
MT8LD432 5 .......................................................... 4 Meg x 32
MT8LD432 X .......................................................... 4 Meg x 32
MT8LD432 XS ....................................................... 4 Meg x 32
MT16D832 .............................................................. 8 Meg x 32
MT16D832 5 ........................................................... 8 Meg x 32
MT16LD832 ........................................................... 8 Meg x 32
MT16LD832 5 ........................................................ 8 Meg x 32
MT16LD832 X ........................................................ 8 Meg x 32
MT16LD832 XS ..................................................... 8 Meg x 32
MT9D136 ................................................................ 1 Meg x 36
MT18D236 .............................................................. 2 Meg x 36
MT12D436 .............................................................. 4 Meg x 36
MT12D436 5 ........................................................... 4 Meg x 36
MT24D836 .............................................................. 8 Meg x 36
MT24D836 5 ........................................................... 8 Meg x 36
S .............. .
5V ........................................................................
PREFACE
Rev. 2195
3-1
3-1
.................... SELF REFRESH
.. .. 5 volt Vee
xiv
5V................................................................................
5V................................................................................
5V ................................................................................
5V ................................................................................
5V ................................................................................
5V ................................................................................
5V ................................................................................
5V ................................................................................
5V,S ............................................................................
3.3V .............................................................................
3.3V, 5 .........................................................................
3.3V, EDO ..................................................................
3.3V, EDO, 5 ..............................................................
5V ................................................................................
5V, 5 ............................................................................
3.3V .............................................................................
3.3V, 5 .........................................................................
3.3V, EDO ..................................................................
3.3V, EDO, 5 ..............................................................
3.3V .............................................................................
3.3V, 5 .........................................................................
3.3V, EDO ..................................................................
3.3V, EDO, 5 ..............................................................
5V................................................................................
5V,S ............................................................................
3.3V.............................................................................
3.3V, 5 .........................................................................
3.3V, EDO ..................................................................
3.3V, EDO, 5..............................................................
5V................................................................................
5V,S ............................................................................
3.3V .............................................................................
3.3V,S.........................................................................
3.3V, EDO ..................................................................
3.3V, EDO, 5..............................................................
5V................................................................................
5V .................................................................................
5V................................................................................
5V,S............................................................................
5V................................................................................
5V,S ............................................................................
EDO
3.3V ..........
4-1
4-11
4-21
4-31
4-41
4-51
4-51
4-63
4-63
4-77
4-77
4-77
4-77
4-63
4-63
4-77
4-77
4-77
4-77
4-99
4-99
4-99
4-99
4-119
4-119
4-133
4-133
4-133
4-133
4-119
4-119
4-133
4-133
4-133
4-133
4-155
4-155
4-167
4-167
4-167
4-167
.. .......... Extended Data-Out
.. ............................ 3.3 volt Vee
Micron Technology, Inc., reserves the right to change products or spec ltications wilhout notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PREFACE
TABLE OF CONTENTS
'CC","w", '"
DRAMDIMMs
PAGE
MT2LD(T)132H ..................................................... 1 Meg x 32
MT2LD(T)132H 5 .................................................. 1 Meg x 32
MT4LD(T)232H ..................................................... 2 Meg x 32
MT4LD(T)232H 5 .................................................. 2 Meg x 32
MT8LD(T)432H ..................................................... 4 Meg x 32
MT8LD(T)432H 5 .................................................. 4 Meg x 32
MT16D(T)164 ......................................................... 1Megx64
MT16D(T)164S ..................................................... 1 Meg x 64
MT16LD(T)164 ...................................................... 1 Meg x 64
MT16LD(T)164S ................................................... 1 Meg x 64
MT8LD(T)264 ........................................................ 2 Meg x 64
MT8LD(T)264 5 ..................................................... 2 Meg x 64
MT8LD(T)264 X .................................................... 2 Meg x 64
MT8LD(T)264 XS .................................................. 2 Meg x 64
MT16D(T)464 ......................................................... 4 Meg x 64
Mf16LD(T)464 ...................................................... 4 Meg x 64
MT16LD(T)464S ................................................... 4 Meg x 64
MT16LD(T)464 X .................................................. 4 Meg x 64
MT16LD(T)464 XS ................................................ 4 Meg x 64
MT18D(T)172 ......................................................... 1 Meg x 72
MT18D(T)172 5 ..................................................... 1 Meg x 72
MT18LD(T)172 ...................................................... 1 Meg x 72
MT18LD(T)172 5 ................................................... 1 Meg x 72
MT9LD(T)272 ........................................................ 2 Meg x 72
MT9LD(T)272 5 ..................................................... 2 Meg x 72
MT9LD(T)272 X .................................................... 2 Meg x 72
MT9LD(T)272 XS .................................................. 2 Meg x 72
MT18D(T)472 ......................................................... 4 Meg x 72
MT18LD(T)472 ...................................................... 4 Meg x 72
MT18LD(T)472 5 ................................................... 4 Meg x 72
MT18LD(T)472 X .................................................. 4 Meg x 72
MT18LD(T)472 XS ................................................ 4 Meg x 72
3.3V .............................................................................
3.3V, 5 ............... "........................................................
3.3V .............................................................................
3.3V, 5 .........................................................................
3.3V .............................................................................
3.3V, 5 .........................................................................
5V ................................................................................
5V, 5 ............... ;.......................... ,..................................
3.3V .. ;..........................................................................
3.3V, 5 .........................................................................
3.3V .............................................................................
3.3V, 5 .........................................................................
3.3V, EDO ..................................................................
3.3V, EDO, 5 ..............................................................
5V ................................................................................
3.3V .............................................................................
3.3V, 5 .........................................................................
3.3V, EDO ..................................................................
3.3V, EDO, 5 ..............................................................
5V ........................................ ;.......................................
5V, 5 ............................................................................
3.3V .............................. ,..............................................
3.3V,S.........................................................................
3.3V .............................................................................
3.3V, 5 .........................................................................
3.3V, EDO ..................................................................
3.3V, EDO, 5..............................................................
5V ................................................................................
3.3V .............................................................................
3.3V, 5 .........................................................................
3.3V, EDO ..................................................................
3.3V, EOO, 5 .............................................. ,...............
S ....................................................................................................... SELF REFRESH
5V ............................................................................................................. 5 volt Vee
EDO ,............................................................................. ,......... Extended Data-Out
3.3V ..................................................................................................... 3.3 volt Vee
DRAM CARDS
5-1
5-1
5-1
5-1
5-15
5-15
5-29
5-29
5-47
5-47
5-69
5-69
5-69
5-69
5-29
547
5-47
5-47
547
5-91
5-91
5-109
5-109
5-131
5-131
5-131
5-131
5-91
5-109
5-109
5-109
5-109
PAGE
MT8D88C132(S) .................................................... 1 Meg x 32
MT8D88C132H(S) ................................................. 1 Meg x 32
MT8D88C132V(S) ................................................. 1 Meg x 32
MT8D88C132VH(S) .............................................. 1 Meg x 32
MT16D88C232(S) .................................................. 2 Meg x 32
MT16D88C232H(S) ............................................... 2 Meg x 32
MT16D88C232V(S) ......................, ........................ 2 Meg x 32
MT16D88C232VH(S) ............................................ 2 Meg x 32
MT8D88C432V(S) ................................................. 4 Meg x 32
MT8D88C432VH(S) .............................................. 4 Meg x 32
MT16D88C832V(S) ............................................... 8 Meg x 32
MT16D88C832VH(S) ............................................ 8 Meg x 32
5V ............................................................ ,...................
5V................................................................................
3.3V ............... ;.............................................................
3.3V .............................................................................
5V ................................................................................
5V ................................................................................
3.3V .............................................................................
3.3V ..................................................... ::......................
3.3V .............................................................................
3.3V .............................................................................
3.3V ..............................................................................
3.3V .............................................................................
5V ............................................................................................................... 5 volt Vee
3.3V ....................................................................................................... 3.3 volt Vee
PREFACE
Rev. 2195
xv
6-1
6-17
6-33
6-49
6-1
6-17
6-33
649
6-33
6-49
6-33
6·49
Micron Technology, Inc., reserves the right to change products or specifICations without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PREFACE
TABLE OF CONTENTS
"'""'00'"
TECHNICAL NOTES
TN-OO-Ol
TN-00-02
TN-00-03
TN-04-0l
TN-04-06
TN-04-12
TN-04-15
TN-04-16
TN-04-19
TN-04-20
TN-04-21
TN-04-22
TN-04-23
TN-04-24
TN-04-26
TN-04-28
TN-04-29
TN-04-30
TN-04-31
TN-04-32
TN-41-01
TN-88-0l
PAGE
Moisture Absorption in Plastic Packages .................................................................................................
Tape-and-Reel Procedures ..........................................................................................................................
Using Gel-Pak®Packaging With Micron Die ............ ;..............................................................................
DRAM Power-Up and Refresh Constraints .............................................................................................
OE-Controlled/LATE WRITE Cycles (DRAM) .......................................................................................
LPDRAM Extended Refresh Current vs. RAS Active Time (4 Meg) ....................................................
DRAM Considerations for PC Memory Design ......................................................................................
16 Meg DRAM-2K vs. 4K Refresh Comparison ....................................................................................
Low-Power DRAMs vs. Slow SRAMs for Main Memory ......................................................................
SELF REFRESH DRAMs .............................................................................................................................
Reduce DRAM Cycle Times with Extended Data-Out ..........................................................................
256K x 16 DRAM Typical Operating Curves ...........................................................................................
4 Meg DRAM Typical Operating Curves .................................................................................................
4 Meg DRAM-Access Time vs. Capacitance .........................................................................................
256K x 16-Access Time vs. Capacitance .................................................................................................
DRAM Soft Error Rate Calculations ..........................................................................................................
Maximizing EDO Advantages at the System Level................................................................................
Various Methods of DRAM Refresh .........................................................................................................
PCB Layout for 4 Meg x 4 300 Mil or 400 Mil SOJ ...................................................................................
Reduce DRAM Memory Cost with Cache................................................................................................
Decrement Bursting with the SGRAM ...... ....... ...... ................................. ........ ......... ................... .......... ....
88-Pin DRAM Cards ....................................................................................................................................
PRODUCT RELIABILITY
7-1
7-3
7-9
7-11
7-13
7-15
7-17
7-23
7-25
7"27
7-29
7-37
7-39
7-45
7-47
7-49
7-53
7-65
7-69
7-71
7-75
7-79
PAGE
Overview .............................................. ... ... ....... ....... .......... ...... ....... ........ ..... .......................... ........... ...... ............... ................. 8-1
Process Flow Chart ........................... ............... .................. .......... ......... ...... .......................... ................. ............................ .... 8-8
PACKAGE INFORMAnON
PAGE
Package Drawings .................................................................................................................................................................
SALES AND SERVICE INFORMAnON
PAGE
CSN-Ol
Standard Shipping Bar Code Labels ........................................................................................................
CSN-02
Individual Box and Container Bar Code Labels .....................................................................................
CSN-03
Surface-Mount Product Labeling ..............................................................................................................
CSN-04
Box and Tape-and-Reel Quantity and Weight Chart .............................................................................
CSN-05
Environmental Programs ...........................................................................................................................
CSN-06
Electronic Data Interchange ......................................................................................................................
Return Material Authorization (RMA) Procedures ...............................................................................
CSN-07
CSN-08
ISO 9001 Certification ..................................................................................................................... :...........
Micron DataFax ...........................................................................................................................................
CSN-09
CSN-lO
Customer Comment Line ...........................................................................................................................
CSN-ll
Part Marking ................................................................................................................................................
CSN-12
Product Change Notification (PCN) System ...........................................................................................
Product Numbering System ...............................................................................................................................................
Ordering Information and Examples ................................................................................................................................
North American Sales Representatives and Distributors ......................................... :.................... ;................................
International Sales Representatives and Distributors .....................................................................................................
MICRON DATAFAX INDEX
lOcI
10-2
10-3
10-4
10-6
10-8
10-9
10-10
10"12
10-13
10-14
10-15
10-16
10-23
10-24
10-36
PAGE
Document Index for Micron DataFax ................................................................................................................................
PREFACE
Rev. 2/95
9-1
xvi
11-1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
Gel-Pak is a registered trademark of Vichem Corporation.
MIc: ........ CN
1-·
~
00"
PREFACE
TABLE OF CONTENTS
,
PAGE
NUMERICAL INDEX
Part#,MT:
12D436 .............................................................. DRAM SIMM
.: ........ ;............................................................................ 4-167
12D436 5 ........................................................... DRAM SIMM
..................................................................................... 4-167
16D(T)164 ........................................................ DRAM DIMM
..................................................................................... 5-29
16D(T)164 5 ..................................................... DRAM DIMM
....................................................................................... 5-29
16D(T)464 ........................................................ DRAM DIMM
...................................................................................... 5-29
..................................................................................... " 4-63
16D232 .............................................................. DRAM SIMM
..................................................................................... 4-63
16D232 5 ........................................................... DRAM SIMM
16D832 .............................................................. DRAM SIMM
..................................................................................... 4-119
16D832 5 ........................................................... DRAM SIMM
..................................................................................... 4-119
16D88C232(S) .................................................. DRAM CARD
..................................................................................... '6='{'"
16D88C232H(S) ............................................... DRAM CARD
...................................................................................... 6-17
..................................................................................... 6-33
16D88C232V(S) ............................................... DRAM CARD
16D88C232VH(S) ............................................. DRAM CARD
..................................................................................... 6-49
16D88C832V(S) ............................................... DRAM CARD
.•.................................................................................•. 6-33
16D88C832VH(S) ...........•................................ DRAM CARD
..................................................................................... 6-49
16LD(T)164 ..................................................... DRAM DIMM
..................................................................................... 5-47
16LD(T)164 5 .................................................. DRAM DIMM
..................................................................................... 5-47
16LD(T)232 ...................................................... DRAM SIMM'
..................................................................................... 4-77
16LD(T)232 5 ................................................... DRAM SIMM
..................................................................................... 4-77
..................................................................................... 4-77
16LD(T)232 X .................................. c••••••••••.•••••• DRAM SIMM
..................................................................................... 4-77
16LD(T)232 XS .............................................•... DRAM SIMM'
16LD(T)464 ..................................................... DRAM DIMM
..................................................................................... 5-47
..................................................................................... 5-47
16LD(T)464 5 .................................................. DRAM DIMM
...................................................................................... 5-47
16LD(T)464 X ................................................... DRAM DIMM
..................................................................................... 5-47
16LD(T)464 XS ................................................ DRAM DIMM
..................................................................................... 4-133
·16LD832 ........................................................... DRAM SIMM
.16LD832 5 ........................................................ DRAM SIMM:
...................................................................................... 4-133
..................................................................................... 4-133
16LD832 X ........................................................ DRAM SIMM
..................................................................................... 4-133
16LD832 XS ...................................................... DRAM SIMM
..................................................................................... 5-91
18D(T)172 ........................................................ DRAM DIMM
18.o(T)172 5 ..................................................... DRAM DIMM
..................................................................................... 5-91
18D(T)472 ........................................................ DRAM DIMM
..................................................................................... 5"91
'18D236 .............................................................. DRAM SIMM
..................................................................................... 4-155
18LD(T)172 ..................................................... DRAM DIMM
..................................................................................... 5-109
18LD(T)172 5 .................................................. DRAM DIMM
..................................................................................... 5-109
..................................................................................... 5-109
18LD(T)472 ..................................................... DRAM DIMM
18LD(T)472 5 .................................................. DRAM DIMM . ...................................................................................... 5-109
18LD(T)472 X .................................................. DRAM DIMM '..................................................................................... 5-109
18LD(T)472 XS'................................................ DRAM DIMM
..................................................................................... 5c109
24D836 .............................................................. DRAM SIMM
..................................................................................... 4-167
24D836 5 ........................................................... DRAM SIMM
..................................................................................... , 4-167
..................................................................................... 4-1
, '2D18 .................................................................. DRAM SIMM
..................................................................................... 4-51
2D25632 ............................................................ DRAM SIMM
................................................................................... ,. 4-11
2D48 .................................................................. DRAM SIMM
..................................................................................... 5-1
2LD(T)132H .................................................... DRAM DIMM
..................................................................................... 5-1
2LD(T)132H S ................................................. DRAM DIMM
..................................................................................... ',4-31
3D49 .................................................................. DRAM SIMM
..................................................................................... 3-1
41LC256K32D4 .......................................................... SGRAM
..................................................................................... 3el
41LC256K32D4S ....................................................... SGRAM
..................................................................................... 2-1
4CI004J ................................................................ FPM DRAM
PREFACE
Rev.2195
xvii
Mlcmll Tochnology. Inc., reserves the right to change pmclllt;lll or specifications without notice.
01995, Micron Technology,lnc.
MICRON
1-·
PREFACE
TABLE OF CONTENTS
"""",,eoc,",,"
NUMERICAL INDEX (continued)
PAGE
Part#,MT:
4C1004J S ............................................................. PPM DRAM
4C16257 ............................................................... PPM DRAM
4C16270 ............................................................... EDO DRAM
4C1M16C3 ........................................................... FPM DRAM
4C4001J ................................................................ FPM DRAM
4C400lJ S ............................................................. FPM DRAM
4C4004J ................................................................ FPM DRAM
4C4007J ................................................................ EDO DRAM
4C4007J s ............................................................. EDO DP,,-,A:t.:r-v1
4C4M4B1 ............................................................. FPM DRAM
4D51232 ............................................................ DRAM SIMM
4LC16257 ............................................................. FPM DRAM
4LC16257 S .......................................................... PPM DRAM
4LC16270 ............................................................. EDO DRAM
4LC16M4A7 ........................................................ FPM DRAM
4LC16M4G3 ........................................................ EDO DRAM
4LC16M4H9 ........................................................ EDO DRAM
4LC16M4T8 ........................................................ PPM DRAM
4LC1M16C3 ........................................................ PPM DRAM
4LC1M16C3 S ..................................................... FPM DRAM
4LC1M16E5 ......................................................... EDO DRAM
4LC1M16E5 S ..................................................... EDO DRAM
4LC2M8B1 ........................................................... PPM DRAM
4LC2M8B1 S ....................................................... PPM DRAM
4LC2M8E7 ........................................................... EDO DRAM
4LC2M8E7 S ....................................................... EDO DRAM
4LC4001} ............................................................. FPM DRAM
4LC4001} S .......................................................... PPM DRAM
4LC4007J ............................................................. EDO DRAM
4LC4007} S .......................................................... EDO DRAM
4LC4M4Bl ........................................................... PPM DRAM
4LC4M4Bl S ....................................................... FPM DRAM
4LC4M4EH ........................................................... EDO DRAM
4LC4M4EH S ....................................................... EDO DRAM
4LC8M8B6 ........................................................... PPM DRAM
4LC8M8C2 .......................................................... EDO DRAM
4LC8M8El ........................................................... FPM DRAM
4LC8M8P4 ........................................................... EDO DRAM
4LD{T)232H .................................................... DRAM DIMM
4LD{T)232H S ................................................. DRAM DIMM
4LD232 ............................................................. DRAM SIMM
4LD232 S .......................................................... DRAM SIMM
4LD232 X .......................................................... DRAM SIMM
4LD232 XS ........................................................ DRAM SIMM
80132 ................................................................ DRAM SIMM
80132 S ............................................................. DRAM SIMM
80432 ................................................................ DRAM SIMM
80432 S ............................................................. DRAM SIMM
8048 .................................................................. DRAM SIMM
8D88C132(S) .................................................... DRAM CARD
PREFACE
Rev. 2195
xviii
2-1
2-117
1-91
2-147
2-15
2-15
2-41
1-1
.....................................................................................
1-1
2-53
4-51
2-131
2-131
H07
2-79
1-47
1-47
2-79
2-163
2-163
1-123
1-123
2-91
2-91
1-63
1-63
2-29
2-29
1-15
1-15
2-65
2-65
1-31
1-31
2-105
1-77
2-105
1-77
5-1
5-1
4-99
4-99
4-99
4-99
4-63
4-63
4-119
4-119
4-21
6-1
Micron Technology, Inc .. reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PREFACE
TABLE OF CONTENTS
",<"w,",,,
NUMERICAL INDEX (continued)
PAGE
Part#,MT:
8D88C132H(S) ................................................. DRAM CARD
8D88C132V(S) ................................................. DRAM CARD
8D88C132VH(S) .............................................. DRAM CARD
8D88C432V(S) ................................................. DRAM CARD
8D88C432VH(S) .............................................. DRAM CARD
8LD(T)132 ........................................................ DRAM SIMM
8LD(T)132 5 ..................................................... DRAM SIMM
8LD(T)132 X ..................................................... DRAM SIMM
8LD(T)132 XS ................................................... DRAM SIMM .
8LD(T)264 ....................................................... DRAM DIMM
8LD(T)264 5 ................................ :................... DRAM DIMM
8LD(T)264 X .................................................... DRAM DIMM
8LD(T)264 XS .................................................. DRAM DIMM
8LD(T)432H .................................................... DRAM DIMM
8LD(T)432H 5 ................................................. DRAM DIMM
8LD432 ............................................................. DRAM SIMM
8LD432S .......................................................... DRAM SIMM
8LD432 X .......................................................... DRAM SIMM
8LD432 XS ........................................................ DRAM SIMM
9D136 ................................................................. DRAM SIMM
9D49 .................................................................. DRAM SIMM
9LD(T)272 ....................................................... DRAM DIMM
9LD(T)272 5 .................................................... DRAM DIMM
9LD(T)272 X .................................................... DRAM DIMM
9LD(T)272 XS .................................................. DRAM DIMM
PREFACE
,I
Rev. 2195
xix
6-17
6-33
6-49
6-33
6-49
4-77
4-77
4-77
4-77
5-69
5-69
5-69
5-69
5-15
5-15
4-107
4-107
4-107
4-107
4-155
4-41
5-131
5-131
5-131
5-131
Micron Technology, Inc .. reserves the right to change products or specifications without nolfce.
©1995, Micron Technology, Inc.
MICRON
1-·
PREFACE
PRODUCT SELECTION
",""oeoo,",
EDODRAM PRODUCT SELECTION GUIDE
Memory
Optional
Configuration Access Cycle
3.3V EDO DRAMs
Part
Number
Access
Time (ns)
Typical Power Dissipation Package/No. of Pins
Standby
Active
TSOP
SOJ
Page
1 Meg x 4
EDO
MT4LC4007J
60,70,80
1mW
11SmW
20/26
EDO,S
MT4LC4007J S
60,70,80
0.2SmW
11SmW
20/26
-
1-1S
1 Meg x 4
4Megx4
EDO,2KR
MT4LC4M4E8
60, 70
1mW
1S0mW
24/26
24/26
1-31
4 Meg x4
EDO, 2KR. S
MT4LC4M4E8 S
........
An , 7n
.....
1'\ A ........ \AI
V."1"IIIVV
150rnVv
24i26
24i26
1-31
SO,60,70
1mW
16SmW
34
34
1-47
1-1S
EDO,8KR
. MT4LC16M4G3
16 Meg x 4
EDO,4KR
MT4LC16M4H9
SO,60,70
1mW
16SmW
34
34
1-47
2Megx8
EDO,2KR
MT4LC2M8E7
60, 70
1mW
1S0mW
28
28
1-63
2 Meg x 8
EDO, 2KR, S
MT4LC2M8E7 S
60, 70
0.3mW
1S0mW
28
28
1-63
8Megx 8
EDO,8KR
MT4LC8M8P4
SO,60,70
1mW
170mW
34
34
1-77
8 Meg x8
EDO,4KR
MT4LC8M8C2
SO,60,70
1mW
170mW
34
34
1-77
1-107
16 Meg x 4
EDO, DC
MT4LC16270
60,70,80
1mW
8SmW
40
40/44
1Meg x 16
EDO, DC, 1KR
MT4LC1 M16ES
60, 70
0.9mW
180mW
44/S0
1-123
1 Megx 16
EDO, DC, 1KR, S
MT4LC1M16ES S
60, 70
0.3mW
180mW
-
44/S0
1-123
2S6Kx 16
5VEDO DRAMs
1 Meg x 4
EDO
MT4C4007J
60, 70
3mW
17SmW
20/26
-
1 Meg x4
EDO,S
MT4C4007J S
60, 70
0.8mW
17SmW
20/26
-
1-1
EDO,DC
MT4C16270
60,70,80
3mW
300mW
40
40/44
1-91
2S6K x 16
EDO = Extended Data-Out, DC = Dual CAS, 1KR
8KR = 8,192 Refresh, S = SELF REFRESH
PREFACE
Rev. 2195
1-1
= 1,024 Refresh, 2KR =2,048 Refresh, 4KR = 4,096 Refresh,
xx
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PREFACE
PRODUCT SELECTION
'''"",co", ,"c
FPM DRAM PRODUCT SELECTION GUIDE
Memory
Optional
Configuration Access Cycle
3.3V FPM DRAMs
Part
Number
Access
Time (ns)
Typical Power Dissipation Package/No. of Pins
Standby
Active
SOJ
TSOP
1 Meg x4
FPM
MT4LC4001J
60,70,80
1mW
100mW
20/26
1 Meg x 4
FPM, S
MT4LC4001J S
60,70,80
0.3mW
100mW
4 Meg x4
FPM,2KR
MT4LC4M4B1
60, 70
1mW
180mW
4 Meg x4
FPM, 2KR, S
MT4LC4M4B1 S
60, 70
0.3mW
180rhW
20/26
24/26
24/26
16 Meg x4
FPM,8KR
MT4LC16M4A7
50,60,70
1mW
165mW
16 Meg x 4
FPM,4KR
MT4LC16M4T8
50,60,70
1mW
2 Meg x 8
FPM,2KR
MT4LC2M8B1
60, 70
2 Meg x8
FPM,2KR,S
MT4LC2M8B1 S
60, 70
8 Meg x 8
FPM,8KR
MT4LC8M8E1
50,60,70
8 Meg x8
FPM,4KR
MT4LC8M8B6
256K x 16
FPM, DC
256K x 16
FPM, DC, S
Page
20/26
20/26
24/26
.2-29
2-29
24/26
2-65
34
34
2-79
225mW
34
34
2-79
1mW
200mW
28
28
2-91
0.3mW
200mW
28
28
2-91
1mW
170mW
34
34
2-105
50,60,70
1mW
230mW
34
34
2-105
MT4LC16257
60,70,80
3mW
150mW
40
2-131
MT4LC16257 S
60,70,80
0.3mW
150mW
40
40/44
40/44
44/50
44/50
2-163
20/26
20/26
2-1
20/26
20/26
2-15
1 Meg x 16
FPM, DC, 1KR
MT4LC1 M16C3
60, 70
3mW
250mW
-
1 Meg x 16
FPM, DC, 1KR, S
MT4LC1M16C3 S
60, 70
0.3mW
250mW···
-
4 Meg x 1
FPM
MT4C1004J
60, 70
20/26
FPM, S
MT4C1004JS
60, 70
3mW
0.8mW·
225mW
4 Megx 1
225mW
1 Meg x 4
FPM
MT4C4001J
60, 70
3mW
225mW
1 Meg x 4
1 Meg x 4 ..
FPM, S
MT4C4001J S
60, 70
0.8mW
225mW
FPM, QC
MT4C4004J
60, 70
3mW
225mW
4 Meg x4
FPM,2KR
MT4C4M4B1
60, 70
3mW
250mW
20/26
20/26
20/26
24/26
24/26
FPM,DC
MT4C16257
60,70,80
3mW
375mW
FPM, DC, 1KR
MT4C1M16C3
60, 70
1mW
350mW
2-65
2-131
2-163
5V FPMDRAMs
256K x 16
1 Meg x 16
2-1
2-15
-
2-41
2-53
40
24/26
40/44
42
-
2-147
2-117
FPM= FAST PAGE MODE, DC = Dual CAS, QC = Quad CAS, 1KR = 1,024 Refresh, 2KR= 2,048 Refresh,
4KR = 4,096 Refresh, 8KR = 8,192 Refresh, S = SELF REFRESH
SGRAM PRODUCT SELECTION GUIDE
Memory
Configuration
256K x 32
256K x 32
1
I
Power Dissipation
Standby
Active
No, of Pins
TQFP
Part
Number
Speed
Grade (ns)
3.3V
MT41 LC256K32D4
10,12,15
TBD
TBD
100
3-1
3.3V
MT41 LC256K32D4 S
10,12,15
TBD
TBD
100
3-1
Page
S = SELF REFRESH
PREFACE
Rev. 2195
xxi
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PREFACE
PRODUCT SELECTION
,,,""CO,,,,,,
DRAM SIMM PRODUCT SELECTION GUIDE
Memory
Configuration
3.3V SIMMs
1 Meg x 32
1 Meg x 32
1 Meg x 32
1 Meg x 32
2 Megx32
2Megx32
2Megx32
2 Meg x 32
2 Meg x 32
2Megx32
2 Meg x 32
2 Meg x32
4 Megx32
4 Meg x 32
4 Megx32
4 Meg x 32
B Megx32
B Meg x 32
BMegx32
B Megx32
5VSIMMs
1 Meg x B
4 Meg x B
4 Meg x B
4 Megx 9
4 Meg x 9
256K x 32
512K x 32
1 Megx32
lMegx32
2 Meg x 32
2 Meg x 32
4Megx32
4Megx32
8 Meg x 32
8 Meg x 32
1 Megx36
2Megx36
4 Meg x 36
4Megx36
B Meg x 36
B,Megx36
S
Pari
Number
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
MTBLD(T)132
MTBLD(T)132 S
MTBLD(T)132 X
MTBLD(T)132 XS
MT16LD(T)232
MT16LD(T)232 S
MT16LD(T)232 X
MT16LD(T)232 XS
MT4LD232
MT4LD232 S
MT4LD232 X ..
MT4LD232 XS
MTBLD432
MTBLD432S
MTBLD432 X
MTBLD432 XS
MT16LDB32
MT16LDB32 S
MT16LDB32X
MT16LDB32 XS
MT2D1B
MT2D4B
MTBD4B
MT3D49
MT9D49
MT2D25632
MT4D51232
MTBD132
MTBD132 S
MT16D232
MT16D232 S
MTBD432
MTBD432 S
MT16DB32
MT16DB32 S
MT9D136
MT1BD236
MT12D436
MT12D436 S
MT24DB36
MT24DB36 S
Optional
Access Cycle
S
EDO
EDO,S
S
EDO
EDO,S
S
EDO
E:DO, S
S
EDO
EDO,S
S
EDO
EDO,S
S
S
S
S
S
S
Access
Time (ns)
Typical Power Dissipation
Standby
Active
60,70,BO
60, 70,BO
60,70,BO
60,70,BO
60,70,BO
60,70,80
60,70,BO
60,70,BO
60, 70
60, 70
60, 70
60, 70
60, 70
60, 70
60, 70
60, 70
60, 70
60, 7.0
60, 70
60, 70
9.6mW
2.4mW
BmW
2mW
19.2mW
4.8mW
BOOmW
BOOmW
920mW
920mW
B10mW
16mW
4mW
4mW
1.2mW
4mW
1.2mW
BmW
2.4mW
BmW
3.2mW
16mW
4.BmW
16mW
6.4mW
92BmW
922mW
BOOmW
BOOmW
600mW
600mW
1,440mW
1,440mW
1,200mW
1,200mW
1,40BmW
1,442mW
1,20BmW
1,203mW
6mW
6mW
24mW
gmW
450mW
500mW
1,BOOmW
725mW
2,025mW
750mW
756mW
1,BOOmW
1,BOOmW
1,B24mW
1,B24mW
2,000mW
1,440mW
2,024mW
30
30
30
30
30
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
4-1
4-11
4-21
4-31
4-41
4-51
4-51
4-63
4-63
4-63
4-63
4-119
4-119
4-119
4-119
4-155
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
70
27mW
6mW
12mW
24mW
24mW
4BmW
4BmW
24mW
2.4mW
4BmW
4.BmW
21mW
54mW
36mW
3.6mW
72mW
7.2mW
0'"·)
....... \'''
UU.c..IIIVV
1,443mW
2,025mW
2,052mW
2,500mW
2,340mW
2,536mW
2,348mW
No. of Pins
SIMM
Page
72
72
72
72
72
4-77
4-77
4-77
4-77
4-77
72
4-//
72
72
72
72
72
72
72
72
72
72
72
72
72.
72
4,77
4-77
4-99
4-99
4-99
4-99
4-133
4-133
4-133
4-133
4-133
4-133
4-133
4-133
4"155
4-167
4-167
4-167
4-167
=SELF REFRESH; EDO =Extended Data-Out
PREFACE
Aev.2195
xxii
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
UU:::I=ICN
1-·
PREFACE
PRODUCT SELECTION
",",owe,,",
DRAM DIMM PRODUCT SELECTION GUIDE
Memory
Configuration
3.3V DlMMs
I
i
I
I
!
I
i
:
Part
Number
1 Meg x 32
3.3V
MT2LD(T) 132H
1 Meg x 32
3.3V
MT2LD(T)132H S
2 Meg x32
3.3V
MT4LD(T)232H
2 Meg x32
3.3V
MT4LD(T)232H S
4 Meg x32
3.3V
MT8LD(T)432H
41111eg x 32
3.3V
MT8LD(T)432H S
1 Meg x 64
3.3V
MT16LD(T) 164
Optional
Access Cycle
Access
Typical Power Dissipation No. of Pins
Time (ns)
Standby
Active
DlMM
Page
60, 70
6mW
500mW
72
5-1
S
60, 70
.6mW
500mW
72
5-1
60, 70
12mW
506mW
72
5-1
S
60, 70
1.2mW
501mW
72
5-1
60, 70
8mW
1,440mW
72
5-15
S
60;70
2.4mW
1,440mW
72
5-15
60, 70
19.2mW
1,600mW
168
5-47
60, 70
4.8mW
1,600mW
168
5-47
60, 70
8mW
1,600mW
168
5-69
1 Meg x 64
3.3V
MT16LD(T) 164 S
2 Meg x 64
3.3V
MT8LD(T)264
2 Meg x64
3.3V
MT8LD(T)264 S
S
60,70
2.4mW
1,600mW
168
5-69
2 Meg x 64
3.3V
MT8LD(T)264 X
EDO
60, 70
8mW
1,200mW
168
5-69
2 Megx64
3.3V
MT8LD(T)264 XS
EDO,S
4 Megx64
3.3V
MT16LD(T)464
4 Meg x64
3.3V
MT16LD(T)464 S
4 Meg x 64
3.3V
MT16LD(T)464 X
4 Meg x 64
3.3V
MT16LD(T)464 XS
1 Meg x 72
3.3V
MT18LD(T)172
1 Meg x 72
3.3V
MT18LD(T) 172 S
S
60, 70
2.4mW
1,200mW
168
5-69
60, 70
16mW
2,880mW
168
5-47
S
60, 70
4.8mW
2,880mW
168
5-47
EDO
60, 70
16mW
2,400mW
168
5-47
EDO,S
60, 70
6.4mW
2,400mW
168
5-47
60, 70
21.6mW
1,800mW
168
5-109
60, "70
5.4mW
1,800mW
168
5-109
S
2 Meg x72
3.3V
MT9LD(T)272
60, 70
9mW
1,800mW
168
5-131
2 Meg x 72
3.3V
MT9LD(T)272 S
S
60, 70
2.7mW
1,800mW
168
5-131
2 Megx72
3.3V
MT9LD(T)272 X
EDO
60, 70
9mW
1,350mW
168
5-131
2 Meg x72
3.3V
MT9LD(T)272 XS
EDO, S
60, 70
2.7mW
1,350mW
168
5-131
4 Meg x72
3.3V
MT18LD(T)472
60, 70
18mW
3,240mW
168
5-109
4Megx72
3.3V
MT18LD(T)472 S
S
60, 70
5.4mW
3,240mW
168
5-109
4 Meg x 72
3.3V
MT18LD(T)472 X
EDO
60, 70
18mW
2,700mW
168
5-109
4 Meg x 72
3.3V
MT18LD(T)472 XS
EDO,S
60, 70
5.4mW
2,700mW
168
5-109
60, 70
48mW
3,600mW
168
5-29
60, 70
12.8mW
3,600mW
168
5-29
5-29
5V DlMMs
1 Meg x 64
5V
MT16D(T)164
1 Meg x 64
5V
MT16D(T)164 S
4 Megx64
5V
MT16D(T)464
60, 70
48mW
4,000mW
168
1 Meg x 72
5V
MT18D(T) 172
60, 70
54mW
4,050mW
168
5-91
1 Meg x 72
5\1
MT18D(T)172 S
60, 70
14.4mW
4,050mW
168
5-91
4 Meg x 72
5V
MT18D(T)472
60, 70
54mW
4,500mW
168
5-91
EDO
PREFACE
Rev. 2195
S
S
=Extended Data-Out; S = SELF REFRESH
xxiii
Micron Technology, inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PREFACE
PRODUCT SELECTION
'''""''00' "'
DRAM CARD PRODUCT SELECTION GUIDE
Memory
Configuration
3.3V DRAM Cards
Part
Number
Access
Time (ns)
Number of Pins
Card
Page
1 Meg x 32
3.3V
4 Megabytes
MT8D88C132V(S)
60,70,80
88
6-33
1 Meg x 32
3.3V
4 Megabytes
MT8D88C132VH(S)
60,70,80
88
6-49
2 Megx32
3.3V
8 Megabytes
MT16D88C232V(S)
60,70,80
88
6-33
2 Meg x32
3.3V
8 Megabytes
MT16D88C232VH(S)
60,70,80
88
6-49
4 Meg x 32
3.3V
16 Megabytes
MT8D88C432V(S)
60,70,80
88
6-33
4 Meg x32
3.3V
16 Megabytes
MT8D88C432VH(S)
60,70,80
88
6-49
8 Meg x 32
3.3V
32 Megabytes
MT16D88C832V(S)
60,70,80
88
6-33
8 Meg x32
3.3V
32 Megabytes
MT16D88C832VH(S)
60,70,80
88
6-49
1 Meg x 32
5V
4 Megabytes
MT8D88C132(S)
60, 70
88
6-1
1 Meg x 32
5V
4 Megabytes
MT8D88C132H(S)
60, 70
88
6-17
2 Meg x 32
5V
8 Megabytes
MT16D88C232(S)
60, 70
88
6-1
2 Meg x32
5V
8 Megabytes
MT16D88C232H(S)
60, 70
88
6-17
5V DRAM Cards
PREFACE
Rev. 2195
xxiv
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1--·
PREFACE
TABLE OF CONTENTS
'""" , ,
TECHNICAL NOTE SELECTION GUIDE
Technical Note
Title
Page
TN-00-01
Moisture Absorption in Plastic Packages
7-1
TN-00-02
Tape-and-Reel Procedures
7-3
TN-00-03
Using Gel-Pak® Packaging With Micron Die
7-9
TN-04-01
DRAM Power-Up and Refresh Constraints
7-11
TN-04-06
OE-ControlledlLATE WRITE Cycles (DRAM)
7-13
7-15
TN-04-12
LPDRAM Extended Refresh Current vs. RAS Active Time (4 Meg)
TN-04-15
DRAM Considerations for PC Memory Design
7-17
TN-04-16
16 Meg DRAM-2K vs. 4K Refresh Comparison
7-23
7-25
TN-04-19
Low-Power DRAMs vs. Slow SRAMs for Main Memory
TN-04-20
SELF REFRESH DRAMs
7-27
TN-04-21
Reduce DRAM Cycle Times with Extended Data-Out
7-29
TN-04-22
256K j( 16 DRAM Typical Operating Curves
7-37
TN-04-23
4 Meg DRAM Typical Operating Curves
7-39
TN-04-24
4 Meg DRAM-Access Time vs. Capacitance
7-45
TN-04-26
256K x 16--Access Time vs. Capacitance
7-47
7-49
TN-04-28
DRAM Soft Error Rate Calculations
TN-04-29
Maximizing EDO Advantages at the System Level
7-53
TN-04-30
Various Methods of DRAM Refresh
7-65
TN-04-31
PCB Layout for 4 Meg x 4 300 Mil or 400 Mil SOJ
7-69
TN-04-32
Reduce DRAM Memory Cost with Cache
7-71
TN-41-01
Decrement Bursting with the SGRAM
7-75
TN-88-01
88-Pin DRAM Cards
7-79
For the latest technical information on Micron products, read our quarterly technical newsletter Design Line.
Call 208-368-3900 to be added to our mailing list.
PREFACE
Rev. 2195
xxv
""rcron T~hnology. Inc., reserve&; the right to change. products or spectflcaUons without,no~,
,
@1995.MicronTechnology, Inc.
Gel-Pak is a registered trademark of Vichem Corporation.
PREFACE
TABLE OF CONTENTS
I'IIIC:F=lg~
PREFACE
Rev. 2/95
xxvi
EDO DRAMs ....................................................
I
I
EDO DRAM PRODUCT SELECTION GUIDE
Memory
Optional
Configuration Access Cycle
3.3V EDO DRAMs
Part
Number
Access
Time (ns)
Typical Power Dissipation Package/No. of Pins
Standby
Active
TSOP
SOJ
Page
1 Meg x 4
EDO
MT4LC4007J
60, 70, 80
1mW
115mW
20/26
1 Meg x 4
EDO,S
MT4LC4007J S
60,70,80
0.25mW
115mW
20/26
-
4 Megx4
EDO,2KR
MT4LC4M4E8
60, 70
1mW
150mW
24/26
24/26
1-31
4 Meg x4
EDO, 2KR, S
MT4LC4M4E8 S
60, 70
OAmW
150mW
24/26
24/26
1-31
1-15
1-15
16 Meg x 4
EDO,8KR
MT4LC16M4G3
50,60,70
1mW
165mW
34
34
1-47
16 Meg x4
EDO,4KR
MT4LC16M4H9
50,60,70
1mW
165mW
34
34
1-47
2 Meg x 8
EDO,2KR
MT4LC2M8E7
60, 70
1mW
150mW
28
28
1-63
2 Megx8
EDO, 2KR, S
MT4LC2M8E7 S
60, 70
0.3mW
150mW
28
28
1-63
8Meg x8
EDO,8KR
MT4LC8M8P4
50,60,70
1mW
170mW
34
34
1-77
8Meg x 8
EDO,4KR
MT4LC8M8C2
50,60,70
1mW
170mW
34
34
1-77
EDO,DC
MT4LC16270
60,70,80
1mW
85mW
40
40/44
1-107
1 Meg x 16
EDO, DC, 1KR
MT4LC1M16E5
60, 70
0.9mW
180mW
-
44/50
1-123
1 Meg x 16
EDO, DC, 1KR, S
MT4LC1M16E5S
60, 70
0.3mW
180mW
-
44/50
1-123
256Kx 16
5V EDO DRAMs
1 Meg x 4
EDO
MT4C4007J
60, 70
3mW
175mW
20/26
-
1 Megx4
EDO,S
MT4C4007J S
60, 70
0.8mW
175mW
20/26
-
1-1
EDO,DC
MT4C16270
60,70,80
3mW
300mW
40
40/44
1-91
256Kx 16
EDO = Extended Data-Out, DC = Dual CAS, 1KR
8KR =8,192 Refresh, S =SELF REFRESH
= 1,024 Refresh, 2KR =2,048 Refresh, 4KR =4,096 Refresh,
1-1
PRELIMINARY
z
m
1 MEG x4DRAM
DRAM
5V, EDO PAGE MODE,
OPTIONAL SELF REFRESH
FEATURES
PIN ASSIGNMENT (Top View)
•
•
•
•
•
Single +5V ±10% power supply
JEDEC-standard pinout and packages
High-performance CMOS silicon-gate process
All inputs, outputs and clocks are TTL-compatible
Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN; optional Extended and SELF REFRESH
modes
• Extended Data-Out (EDO) PAGE MODE access cycle
• 1,024-cycle Extended Refresh distributed across 16ms
or 128ms
• EDO PAGE MODE cycle times, 25-35ns
OPTIONS
20/26-Pin SOJ
(DA-1)
MARKING
• Timing
60ns access
70ns access
1
2
3
4
5
26
25
24
23
22
AO
9
A1
10
11
12
13
18
17
16
15
14
A2
-6
-7
• Refresh Rate
Standard 16ms period
SELF REFRESH and 128ms period
A3
Vee
None
S
• Packages
Plastic SOJ (300 mil)
Vss
OQ4
OQ3
CAS
DE
AS
A7
A6
A5
A4
as the results are not predictable. When WE goes LOW prior
to CAS going LOW (EARLY WRITE cycle), the output pins
remain open (High-Z) until the next CAS cycle.
The four data inputs and four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by WE and OE.
DJ
• Part Number Example: MT4C4007JDJ-7
KEY TIMING PARAMETERS
PAGE ACCESS
SPEED
tRC
tRAC
tpc
tAA
tCAC
tCAS
-6
-7
110ns
l30ns
60ns
70ns
25ns
33ns
30ns
35ns
l8ns
22ns
10ns
l5ns
PAGE operations allow faster data operations (READ or
WRITE) within a row-address-defined (AO-A9) page
boundary.
The PAGE cycle is always initiated with a row-address
strobed-in by RAS followed by a column-address
strobed-in by CAS. CAS may be toggled-in by holding
RAS LOW and strobing-in different column-addresses,
thus executing faster memory cycles. Returning RAS
HIGH terminates PAGE operation.
GENERAL DESCRIPTION
The MT4C4007J(S) is a randomly accessed solid-state
memory containing 4, 194,304 bits organized in a x4 configuration with optional SELF REFRESH. During READ or
WRITE cycles, each of the 4 memory bits (1 bit per DQ) is
uniquely addressed through the 20 address bits, which are
entered 10 bits (AO-A9)ata time. RAS latches the first 10 bits
and CAS latches the latter 10 bits.
A READ or WRITE cycle is selected with the WE input.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last, however, only EARLY WRITE cycles
are supported. LATE WRITE cycles should not be attempted
MT4C4007J(S}
D23.pm5 - Rev. 2/95
OQ1
OQ2
WE
RAS
A9
EDO PAGE MODE
The MT4C4007J provides EDO PAGE MODE, which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
CAS goes back HIGH. EDO provides for CAS precharge
time (ICP) to occur without the output data going invalid.
This elimination of CAS output control provides for pipeline READs.
PAGE MODE DRAMs have traditionally turned the output buffers off (High-Z) with the rising edge of CAS. EDO
1-1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
:e
•
m
c
o
C
::D
»
s:
PRELIMINARY
z
m
MICRON
1-·
c
"
MT4C4007J(S)
1 MEG x 4 DRAM
"
:e
•
m
c
o
C
Jl
l>
3:
EDOPAGE MODE (c:ontinued)
HIGH for a minimum of tOEP anytime during the CAS
HIGH period and the DQs will tristate and remain tristate,
regardless of OE, until CAS falls again (please reference
Figure 1 for further detail on the toggling OE condition).
During cycles other than PAGE-MODE READ, the outputs
are disabled at tOFF time after RAS and CAS are HIGH, or
twHZ after WE transitions LOW. The toFF time is referenced from the rising edge of RAS .or CAS, whichever
occurs last. WE can also perform the function of turning off
the output drivers under certain conditions, .as shown in
Figure 2.
operates as any DRAM READ or FAST7 PAGE-MODE
READ, except data will be held valid after CAS gees HIGH,
as long as RAS and OEare held LOW alld WE is held HIGI::I.
OE can be brought LOW or HIGH while CAS and RAS are
LOW, and the DQs will transition between valid data and
High-Z. Using OE, there are two methods to disable the
outputs and keep them disabled, during .the CAS HIGH
time. The first method is to have OE HIGH when CAS
transitions HIGH and keep OE HIGH for toEHC. This will
tristate the DQs and they will reJnain tristate, regardless of
OE, until CAS falls again. The second method is to have
OE LOW when CAS tra.nsitions HIGH. Then OE can pulse
RAs ~:~:~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
~..
-
~
(l
!
('
('
~ff////ffffff///ff/~/ff///ffrff///,@(q'\~~<~.~N~.(C~1~~W4~~W<'.~\~~\~""~N(~DI)~~Wl2
:' -~4 _.. ~ ~,-____'__VAU_D-f~~I'
The
I
!
DOs go back to
The DOs remain High-Z
untillhe next CAS cyCle
if IOEHC is met.
Low-Z if toES Is met.
--.
!
The DOs remain High-Z
until the next CAS cycle
if\'QEP is met.
~
DON'TeARE
~
UNDEFINED
'Figure 1
OUTPUT ENABLE AND DISABLE
MT4C4007J(S)
023.pm5 - Rev. 2/95
1-2
Micron Technology, Inc., reserves the right to change products or sp6(lificatiOllS without notice.
@1995,MlcronTechn%gy,lnc.
PRELIMINARY
MICRON
1-·
MT4C4007J(S)
1 MEG x 4 DRAM
'''"M"", "'
z
m
::e
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS cycle (READ, WRITE) or RAS
refresh cycle (RAS ONLY, CBR, or HIDDEN) so that all
1,024 combinations ofRAS addresses (AO-A9) are executed
within tREF max, regardless of sequence. The CBR and
SELF REFRESH cycles will invoke the internal refresh
counter for automatic RAS addressing.
An optional SELF REFRESH mode is also available on
the MT4C4007J S. The "s" version allows the user the choice
of a fully static low-power data retention mode, or a dynamic refresh mode at the extended refresh period of 128ms.
The optional SELF REFRESH feature is initiated by performing a CBR REFRESH cycle, and holding RAS LOW for
the specified tRASS. Additionally, the "s" version allows
for an extended refresh period of 128ms, or 125Jls per row
if using distributed CBR REFRESH. This refresh rate can be
applied during normal operation, as well as during a standby
or BATTERY BACKUP mode.
RAs ~:r:~,--
00
:
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS HIGH time.
VALID DATA (A)
_ _ _
VALID DATA (B)
-----+~_~WPZ
-I--- ------+--1_--+---c
-+
-----r--I
/_/_
r
The DOs go to High-Z if WE falis, and if IWPZ is met,
will remain High-Z until CAS goes LOW with
iiiiE HIGH {Le., until a READ cycle is initiated).
I
WE may be used to disable the DOs to prepare
for input data in an EARLY WRITE 'CYcle. Th'e DOs
will remain High-Z until CAS goes LOW with
WE HIGH (Le., until a READ cycle 'is'initiated).
~
DON'T CARE
~
UNDEFINED
Figure 2
OUTPUT ENABLE AND DISABLE USING WE
MT4C4007J(S)
D23.pm5 - Rev. 2/95
1-3
•
m
c
o
C
::D
l>
S
STANDBY
__________________~_______~_____________
~lgr:----~
~:~:
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum time of IRpS. This delay allows for
the completion of any internal refresh cycles that may be in
process at the time ofthe RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting SELF REFRESH. However, if the DRAM controller utilizes RAS
ONLY or burst refresh sequence, all 1,024 rows must be
refreshed within the average internal refresh rate, prior to
the resumption of normal operation.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc,
PRELIMINARY
z
:E
m
•
FUNCTIONAL BLOCK DIAGRAM
EDO PAGE MODE
m
c
o
c~~:~--~----------------------_,
DOl
D02
D03
D04
C
::D
L---------------------~~----~OE
l>
s:
AO
Al
A2
A3
A4
AS
A6
A7
A8
1024 x 1024 x 4
A9
MEMORY
ARRAY
Vee
RAS
Vss
TRUTH TABLE
ADDRESSES
IR
IC
DATA-IN/OUT
FUNCTION
liAS
"CAs-
WE
Of
Standby
H
H-X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
DQ1-DQ4
L
L
L
X
ROW
COL
Data-In
EDO-PAGE-MODE
1st Cycle
L
H-'+L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H-L
H
L
n/a
COL
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H-L
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd Cycle
L
H-L
L
X
n/a
COL
Data-In
L
H
X
X
ROW
n/a
High-Z
L
H
L
ROW
COL
Data-Out
RAS-ONLY REFRESH
HIDDEN
READ
L-H-L
REFRESH
WRITE
L'-+H-L
L
L
X
ROW
COL
Data-In
CSR REFRESH
H-L
L
H
X
X
X
High-Z
SELF REFRESH
H-L
L
H
X
X
X
High-Z
MT4C4007J(S)
D23.pm5 - Rev. 2/95
1-4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
z
m
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Vss ................. -1.0V to +7V
Operating Temperature, TA (ambient) .......... DoC to +70°C
Storage Temperature (plastic) .................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
:e
•
m
c
o
C
lJ
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
=+5V +10%)
-
(Notes: 1,6, 7) (Vee
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
Vee+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
PARAMETER/CONDITION
INPUT LEAKAGE CURRENT
Any input OV ::;; VIN ::;; 6.5V (All other pins not under test =OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV ::;; VOUT::;; 5.5V)
TTL OUTPUT LEVELS
MT4C4Q07J{S)
D23.pm5-Rev.2f95
I
I
=-5mA)
Low Voltage (lOUT =4.2mA)
High Voltage (lOUT
1-5
II
-2
2
~A
loz
-10
10
~A
VOH
2.4
VOL
NOTES
V
0.4
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
l>
3:
PRELIMINARY
z
m
~------~------------------------------
•
m
c
o
C
JJ
»
3:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DCOPERATfNG CONDITIONS
(Notes: 1, 6, 7) (Vcc = +5V ±1 0%)
MAX
SYMBOL
-6
-7
ICC1
2
2
mA
ICC2
ICC2
(S only)
1
200
1
200
!1A
!1A
OPERATING CURRENT: Random READIWRITE
AVeiage power supply curreni
(RAS, CAS, address cycling: IRC = IRC [MIN])
ICC3
110
100
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
(RAS = VIL, CAS, address cycling: IpC = IpC [MIN])
ICC4
80
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS cycling, CAS = VIH: IRC = IRC [MIN])
Iccs
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, address cycling: IRC = IRC [MIN])
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
STANDBY CURRENT: (CMOS)
(RAS = CAS = Other Inputs = Vcc -0.2V)
REFRESH CURRENT: Extended (S version only)
Average power supply current during Extended Refresh:
CAS = 0.2V or CBR cycling; RAS = IRAS (MIN); WE= Vcc -0.2V;
AO-A9 and DIN = Vcc -0.2V or 0.2V (DIN may be left open);
IRC = 12511S (1,024 rows at 12511S = 128ms)
REFRESH CURRENT: SELF (S version only)
Average power supply current during SELF REFRESH:
CBR cycle with IRAS ~ IRASS (MIN) and CAS held LOW;
WE = Vcc -0.2; AO-A9 and DIN = Vcc -0.2V or 0.2V
(DIN may be left open)
UNITS NOTES
I
mA
3,4,
30
70
mA
3,4,
30
110
100
mA
3,30
ICC6
110
100
mA
3,5
Icc?
(S only)
300
300
!1A
3,5,
28
Icca
(S only)
300
300
I1A
5,29
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: AO-A9
CI1
5
pF
2
Input Capacitance: RAS, CAS, WE, OE
CI2
7
pF
2
Input/Output Capacitance: DO
CIO
7
pF
2
MT4C4Q07J(S)
D23.pm5 - Rev. 2195
1-6
Micron Technology, Inc., reselVes the right to change products or specifications without-notice.
©1995, Micron Technology, Inc.
PRELIMINARY
z
m
=e
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vee
=+5V ±1 0%)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address setup to CAS precharge during WRITE
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Access time from CAS
Column-address hold time
CAS pulse width
RAS LOW to "don't care" during SELF REFRESH cycle
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
Data output hold after CAS LOW
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable time
OE HIGH hold time from CAS HIGH
OE HIGH pulse width
OE LOW to CAS HIGH setup time
Output buffer turn-off delay
OE setup prior to RAS during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
MT4C4007J(S)
D23.pm5~Rev.2I95
MIN
tAA
tACH
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCHD
tCHR
tCLZ
tCOH
tcp
tCPA
tCRP
tCSH
tCSR
tCWL
tDH
tDHR
tDS
MIN
30
10,000
10
50
10
15
10
45
0
15
15
10
10
3
5
10
tRAC
tRAD
tRAH
tRAL
15
10
30
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10,000
40
10
55
10
20
13
55
0
15
15
10
10
5
3
0
25
UNITS
22
35
tOEHC
tOEP
tOES
tOFF
tORD
tpc
MAX
15
50
0
0
18
toD
tOE
1-1'
MAX
15
45
0
0
10
10
10
10
3
5
10
m
-7
-6
SYM
15
60
30
20
20
10
10
5
3
0
33
15
10
35
II
20
70
35
NOTES
c
o
C
Jl
15
28
5
16
5
22
22
26
23
20
14
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnoiogy, Inc.
l>
S
PRELIMINARY
z
m
=e
III
m
c
o
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vee
=+5V ±1 0%)
PARAMETER
RAS pulse width
-7
·6
AC CHARACTERISTICS
SYM
tRAS
MIN
MAX
MIN
60
60
10,000
100,000
70
70
MAX
10,000
UNITS
RAS pulse width (EDO PAGE MODE)
tRASP
C
Jl
RAS pulse width during SELF REFRESH cycle
Random READ or WRITE cycle time
tRASS
tRC
100
100
~s
110
130
ns
RAS to CAS delay time
tRCD
20
s::
Read command hold time (referenced to CAS)
tRCH
0
Read command setup time
Refresh period (1,024 cycles)
tRCS
tREF
0
Refresh period (1,024 cycles) S version
tREF
tRP
40
50
ns
tRPC
tRPS
0
110
0
130
ns
RAS" hold time
tRRH
tRSH
0
15
0
20
ns
ns
Write command to RAS lead time
l>
RAS precharge time
RAS to CAS precharge time
RAS precharge time during SELF REFRESH cycle
Read command hold time (referenced to RAS)
15
IT
2
Write command hold time
tWCH
Write command hold time (referenced to RAS)
tWCR
twcs
10
45
Write command pulse width
WE pulse width for output disable when CAS HIGH
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT4C4007J(S)
D23.pms- Rev. 2/95
WPZ
WRH
tWRP
1-8
0
2
ns
ms
128
ms
ns
17
19
28
19
ns
9,10
ns
ns
55
0
3
28
ns
50
15
15
ns
ns
16
20
50
0
3
50
0
128
tRWL
WHZ
twp
20
16
Transition time (rise or fall)
WE command setup time
Output disable delay from WE (CAS HIGH)
45
100,000
NOTES
ns
ns
ns
20
21,26
ns
ns
10
10
15
10
10
10
ns
25
10
10
ns
25
ns
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
z
m
:e
NOTES
1.
2.
3.
4.
All voltages referenced to Vss.
This parameter is sampled. Vee = +SV; f = 1 MHz.
Ice is dependent on cycle rates.
Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
S. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100/1s is reqUired after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume tT = 2.5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and'
VIL (or between VIL and VIH) in a monotonic martner.
11. If CAS and RAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that IRCD < tRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
IS. Assumes that IRCD 2: tRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for tcP.
17. Operation within the IRCD (MAX) limit ensures that
lRAc (MAX) can be met. IRCD (MAX) is specified as
MT4C4007J{S)
023.pmS - Rev. 2195
a reference point only; if IRCD is greater than the
specifiedIRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
18. Operation within the tRAD (MAX) limit ensures that
tRCD (MAX) can be met. lRAD (MAX) is specified as
a reference point only; if lRAD is greater than the
specified lRAD (MAX) limit, access time is controlled
exclusively by IAA.
19. Either tRCH or IRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. If the cycle is a READ-MODIFY-WRITE, the state of
data-out is indeterminate. OE held HIGH and WE
taken LOW after CAS goes LOW results in a LATE
WRITE (OE-controlled) cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
23. Even if OE is HIGH, LATE WRITE or READMODIFY-WRITE operations are not permissible and
should not be attempted.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE= LOW and OE=HIGH.
2S. tWTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of IWRP and IWRH in the
CBR REFRESH cycle.
26. The DQs open during READ cycles once taD or IOFF
occur.
27. Extended refresh current is reduced as lRAS is
reduced from its maximum specification during the
extended refresh cycle.
28. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
29. Column-address changed once each cycle.
1-9
Micron Technology, 1m:., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
m
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C
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s:
PRELIMINARY
z
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MICRON
1-·
MT4C4007J(S)
1 MEGx 4 DRAM
,""""0,"'"
~--------------------------
II
READ CYCLE
RC
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ICSH
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ROW
I
tRAG
I
'CAG
I~NOTE 2
~I.
DO
~gr -=---~-~-OPEN ___----~~~VAl~IDD~AT~Aj~OPEN.. I.
DE
I.
tOE
~:~ -_T.fj;=W/;TTT~/;TTT%777fj;777///;7Ti7l/;'Tr,1I/;77C7//;,"@TTT7I/;TT71//;7771j;Tn1//;"'1//;=1//;=1//;rrTTl/!?>J,
too
!/;CTT.1//;'"1/J;TT71//;7771//;7771j;Tn1/!;"'1//;=1//;=1/J;'"1//;n-T1//;TTn1j;
EARLY WRITE CYCLE
RC
tRP
'RAS
I
\
d::
tCSH
=f--~
tRCD
1
r
tAR
I
'RAD
I~I
I~ ~I
ADDR
~:r
_~
ROW
~ :r 7~
I
~:gr
tRAl
COLUMN
I
I
1
I~!
I
I
tACH
I
~
ROW
'CWL
'RWl
'WGR
!,;,///J I I ~
~_tDSi i--=--~
_
~ ~
DO
J0Z0t
I
~I
I~
twp
I
VALID DATA
fZI DON'T CARE
I:I2Jl UNDEFINED
NOTE:
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for 'WRP and 'WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
2. 'OFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MT4C4007J(S)
D23.pmS - Rev, 2195
1-10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron TechnologY,lnc.
PRELIMINARY
MIC:RON
1-·
MT4C4007J(S)
1 MEG x 4 DRAM
<,
<
z
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~~~--~----------------------------~
•
EDO-PAGE-MODE READ CYCLE
1________________________t~AA~SP~·_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~
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RAS
~:~=~'
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CAS
AODR
~:~ =J
~:~
I
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ROW
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tpc
1_I-7:tRs~H_ _
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too
COWMN
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I
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f'
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II
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ROW
'ewL
II
OE
~:~, 1I!I!!III/(I/II!I!I!!!11///I/I!I!!/I!II!!II//1!1!!1!1!I!!II/!$/I!I!//!!11//I!I!!/I/I!!II!II1!!!III!IIII!#III!!1/I!/Ih
~
DON'T CARE
!88S UNDEFINED
NOTE:
t Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE). the system designer
.... should implement WE HIGH for WRP and .WRH. This design implementation .will facilitate compatibility with
future EDO DRAMs.
MT4C4007J(S)
D23.pm5:- Rev. 2/95
1-11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995, MlcrorrTeclmology, Inc-.
PRELIMINARY
z
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II
EDO-PAGE-MODE READ-EARL Y-WRITE CYCLE
(Pseudo READ-MODI FY-WRITE)
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!RASP
AAS
VIHVIL-
tCSH
Ipe
Ipe
C
teRP
:D
CAS
~
tRCD
~
lep
lep
VIHVIl-
l>
S
lAR
DQ
~:gt=----- OPEN ---~-t=~VA~LlD~DA~TA~{A~)=jt~~)
IDE
0.
~:t= W;1@'$$$$$$;1#MiHIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
(REFRESH)
(READ)
I RAS
tRSH
IRCD
'1
l'
_,,.,j
- .'I
~IH-~
"~~~M~
I'
II'
I~
_J
,
tCHR
Ji
IAR
•
II t~1
tRAD
tRAH
:IAse.ll~
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IL-
IRAe
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r-------i
I~'
ADDR
f----=----I '
~gr:::::------OPEN
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:
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>---OPEN-
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NOTE:
~
DON'T CARE
~
UNDEFINED
1. Although WE is a"don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4C4007J(S}
D23.pm5 - Rev. 2/95
1-12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
z
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--------------------------------------~
II
CBR REFRESH CYCLE
(Addresses and OE =DON'T CARE)
tRAS
'RP
-1."~
=J'
cp
~
CAS
DO
WE
'CHR
~:t-
'RP
2
'RPC~~
II
'WRP
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.
'WRP
Ib
~:t -W'/$/ffO- -Wff/$ffffff/ff$$-
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RAS-ONLY REFRESH CYCLE
NOTE:
~
DON'TCARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for WRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4C4007J(S)
D23.pmS - Rev. 2/95
1-13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
l>
S
PRELIMINARY
z
m
MICRON
1-·
MT4C4007J(S)
1 MEG x 4 DRAM
,,,","coene
~--------------------------------------
II
SELF REFRESH CYCLE
(Addresses and OE DON'T CARE)
=
m
NOTE 1
lAP
c
tRASS
((
tAPS
: :;)~ ~~/_#ff/$/';~#;J~jr~
o
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lWRP
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II
I
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tWAP
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READ CYCLE
(with WE-controlled disable)
RAS
VIH
:--------,~
VIL_
tCSH
CAS VIH -
tCRP . =:==========tR:CD=====t:CA:S====:
.1
tC?
r+------.J.
V IL -
r-----
ADDR
WE
DO
IH
V _.7TTj'?TT;'777:!,------;---,I:rn;'777",,.,r--;----i-----'----,J
VIL -.LLL.LLLL.LI~
~gt --------OPEN--------1~~~~~~
tOE
.!
1_
too
~OPEN-
~
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NOTE:
~
DON'T CARE
12221
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
3. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tvvRH: This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4C4007J(S)
D23.pmS-Rev.2195
1-14
Micron
Techn~ogy,
Inc., reserves the right
to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC4007 J(S)
1 MEG x 4 D6AM
"'<",ce",,",
1 MEG x 4 DRAM
DRAM
3.3V, EDO PAGE MODE,
OPTIONAL SELF· REFRESH
FEATURES
•
•
•
•
•
•
•
•
•
•
Single +3.3V ±O.3V power supply
Low power, 0.25mW standby; 115mW active, typical
JEDEC-standard pinout and packages
High-performance CMOS silicon-gate process
All inputs, outputs and clocks are LVTTL-compatible
Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN; optional Extended and SELF REFRESH
modes
Extended Data-Out (EDO) PAGE MODE access cycle
1,024-cycle Extended Refresh distributed across 16ms
or 128ms
Low SELF REFRESH current, lOOIlA typical, 150llA
(MAX)
EDO PAGE MODE cycle times, 25-35ns
OPTIONS
MARKING
• Timing
60ns access
70ns access
80ns access
-6
-7
-8
• Refresh Rate
Standard 16ms period
SELF REFRESH and 128ms period
PIN ASSIGNMENT (Top View)
20/26-Pin SOJ
(DA-1)
KEY TIMING PARAMETERS
tRC
tRAC
tpc
tAA
teAc
tCAS
110ns
l30ns
l50ns
60ns
70ns
80ns
25ns
30ns
33ns
30ns
35ns
40ns
l8ns
22ns
22ns
10ns
l2ns
12ns
10
11
12
13
b Vss
26
25
24
23
P D04
PD03
P CAS
18
PA8
22P DE
17p A7
P
16 A6
15 PA5
14 PA4
time. RAS latches the first 10 bits and CAS latches the latter
10 bits.
A READ or WRITE cycle is selected with the WE input. A
logic HIGH on WE dictates READ mode while a logic LOW
on WE dictates WRITE mode. During a WRITE cycle, datain (D) is latched by the falling edge of WE or CAS, whichever occurs last. If WE goes LOW prior to CAS going LOW,
the output pins remain open (High-Z) until the next CAS
cycle, which is an EARLY WRITE cycle.
The four data inputs and four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by WE and OE.
• Part Number Example: MT4LC4007JDJ-7 S
-6
-7
-8
9
A1
A2
A3
Vee
DJ
TG
SPEED
AO
D02
None
S
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
WE
RAS
A9
1
2
3
4
5
DOl
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-addressdefined (AO-A9) page boundary.
The PAGE cycle is always initiated with a row-address
strobed-in by RAS followed by a column-address
strobed-in by CAS. CAS may be toggled-in by holding
RAS LOW and strobing-in different column-addresses,
thus executing faster memory cycles. Returning RAS
HIGH terminates PAGE operation.
GENERAL DESCRIPTION
I
The MT4LC4007J(S) is specially designed to operate from
3.0V to 3.6V for low-voltage memory systems. It is a randomly accessed solid-state memory containing 4,194,304
bits organized in a x4 configuration with optional SELF
REFRESH. During READ or WRITE cycles, each of the 4
memory bits (1 bit per DQ) is uniquely addressed through
the 20 address bits, which are entered 10 bits (AO-A9) at a
MT4LG40Q7J(S}
D12.pmS- Rev. 2/95
1-15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
m
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C
lJ
»
s:
PRELIMINARY
•
m
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»
s
EDO PAGE MODE
The MT4LC4007J provides EDO PAGE MODE, which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
CAS goes back HIGH. EDO provides for CAS precharge
time (tcP) to occur without the output data going invalid.
This elimination of CAS output control provides for pipeline READs.
PAGE MODE DRAMs have traditionally turned the output buffers off (High-Z) with the rising edge of CAS. EDO
operates as any DRAM READ or FAST-PAGE-MODE
READ, except data will be held valid after CAS goes HIGH,
as long as RAS and OE are held LOW and WE is held HIGH.
OE can be brought LOW or HIGH while CAS and RAS are
LOW, and the DQs will transition between valid data and
High-Z. Using OE, there are two methods to disable the
outputs and keep them disabled during the CAS HIGH
RAs ~:~=~L
_____________________________________
~:t~///41/////////#~/////////////////,@G~;;:A7lll2~WZ7lll2~~~f!l1l:ZZ
"0"
'" ,
DO
time. The first method is to have OE HIGH when CAS
transitions HIGH and keep OE HIGH for tOEHC. This will
tristate the DQs and they will remain tristate, regardless of
OE, until CAS falls again. The second method is to have
OE LOW when CAS transitions HIGH. Then OE can pulse
HIGH for a minimum of toEP anytime during the CAS
HIGH period and the DQs will tristate and remain tristate,
regardless of OE, until CAS falls again (please reference
Figure 1 for further detail on the toggling OE condition).
During cycles other than PAGE-MODE READ, the outputs
are disabled at toFF time after RAS and CAS are HIGH, or
twHZ after WE transitions LOW. The tOFF time is referenced from the rising edge of RAS or CAS, whichever
occurs last. WE can also perform the function of turning off
the output drivers under certain conditions, as shown in
Figure 2.
~:gt
DE
.'
'.ALI~IDD:~:(AJ
I
I
------~LJi~
I
"'"
'''I'~";,
"UODm('1
A
~:r-
I
The DOs go back to
Low-Z if tOES is met.
VALID DATA (C)
VALID DATA (D)
II~
'-----------+A;}~-------
The DOs remain High-Z
untillhe next CAS cycle
jf toEHC is mel.
I
The DOs remain High-Z
until the next CAS cycle
iftOEP is met.
~
Oo"N'T CARE
~
UNDEFINED
Figure 1
OUTPUT ENABLE AND DISABLE
MT4lC4007J(S)
D12.pm5-Rev.2195
1-16
Micron Technology, Inc., reserves Ihe right to change products or specifications wftholJt notice.
©1995, Micron Technology, Inc
PRELIMINARY
REFRESH
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum time of tRPS. This delay allows for
the completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence,
a burst refresh is not required upon exiting SELF REFRESH. However, if the DRAM controller utilizes RAS
ONLY or burst refresh sequence, all 1,024 rows must be
refreshed within the average internal refresh rate, prior to
the resumption of normal operation.
Preserve correct memory cell data by maintaining power
and executing any RAS cycle (READ, WRITE) or RAS
refresh cycle (RAS ONLY, CBR, or HIDDEN) so that all
1,024 combinations ofRAS addresses (AO-A9) are executed
within tREF max, regardless of sequence. The CBR and
SELF REFRESH cycles will invoke the internal refresh
counter for automatic RAS addressing.
An optional SELF REFRESH mode is also available on
the MT4LC4007J S. The "5" version allows the user the
choice of a fully static low-power data retention mode, or a
dynamic refresh mode at the extended refresh period of
128ms. The optional SELF REFRESH feature is initiated by
performing a CBR REFRESH cycle, and holding RAS LOW
for the specified tRASS. Additionally, the "5" version allows for an extended refresh perio
s:
PRELIMINARY
MICRON
1-·
•
MT4LC4007J(S)
1 MEG x 4 DRAM
"'""0""""
FUNCTIONAL BLOCK DIAGRAM
EDO PAGE MODE
m
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001
002
003
004
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~--------------------~~----~OE
l>
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AO
A1
A2
A3
A4
AS
A6
A7
AS
1024 x 1024 x 4
A9
MEMORY
ARRAY
Vee
RAS
Vss
TRUTH TABLE
ADDRESSES
IR
IC
DATA-IN/OUT
FUNCTION
RAS
"CAS"
WE"
OE
Standby
H
H-X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
L-H
ROW
COL
Data-Out, Data-In
READ WRITE
DQ1-DQ4
L
L
H-L
EDO-PAGE-MODE
1st Cycle
L
H-L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H-L
H
L
n/a
COL
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H-L
L
X
ROW
COL
Data-In
EARLY WRITE
2nd Cycle
L
H-L
L
X
n/a
COL
Data-In
EDO-PAGE-MODE
1st Cycle
L
H-L
H-L
L-H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H-L
H-L
L-H
rVa
COL
Data-Out, Data-In
L
H
X
X
ROW
n/a
High-Z
H
L
ROW
COL
Data-Out
RAS-ONLY REFRESH
HIDDEN
READ
L-H-L
L
REFRESH
WRITE
L-H-L
L
L
X
ROW
COL
Data-In
CBR REFRESH
H-L
L
H
X
X
X
High-Z
SELF REFRESH
H-->L
L
H
X
X
X
High-Z
MT4LC40Q7J(S)
D12.pm5 - Rev. 2195
1-18
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
I ~.
~BSOLUTE
MT 4LC4007 J(S)
1 MEG x 4 DRAM
"'""'"00""
*Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
MAXIMUM RATINGS*
loltage on Any Pin Relative to Vss .............. -l.OV to +4.6V
Jperating Temperature, TA (ambient) .......... O°C to +70°C
;torage Temperature (plastic) .................... -55°C to +150°C
'ower Dissipation ............................................................. lW
;hort Circuit Output Current ..................................... 50mA
m
C
o
C
:::D
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes' 1 , 6 7) (Vee = +3 3V +0 .3V)
~
PARAMETER/CONDITION
I
SYMBOL
MIN
Supply Voltage
Vee
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
Vec+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
INPUT LEAKAGE CURRENT
Any input OV ~ VIN ~ Vce+0.5V (All other pins not under test
=OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV ~ VOUT ~ Vcc+0.5V)
TTL OUTPUT LEVELS
MT4LC4007J(S)
I D12.pm5-Rev.2195
= -2mA)
I
Low
Voltage
(lOUT
=
2mA)
I
High Voltage (lOUT
1-19
MAX
UNITS
Ii
-2
2
IlA
loz
-10
10
VOH
2.4
IlA
V
0.4
V
VOL
NOTES
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology,' Inc.
»
s:
PRELIMINARY
-
m
c
o
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +3.3V ±0.3V)
MAX
PARAMETER/CONOITION
-6
-7
-8
UNITS
NOTES
.lcc1
1
1
1
mA
Icc2
Icc2
(S only)
500
100
500
100
500
100
~
SYM
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
C
STANDBY CURRENT: (CMOS)
(RAS = CAS = Other Inputs = Vcc -0.2V)
»
s:
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, address cycling: tRC = tRC [MIN])
Icc3
80
70
60
mA
3,4,
30
OPERATING CURRENT: EDG PAGE iv10DE
Average power supply current
(RAS = VIL, CAS, address cycling: tpc = tpc [MIN])
Icc4
60
50
40
mA
3,4,
30
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS cycling, CAS = VIH: tRC = tRC [MIN])
Iccs
80
70
60
mA
3,30
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, address cycling: tRC = tRC [MIN])
Iccs
80
70
60
mA
3,5
Icc?
(S only)
150
150
150
~
3,5,
28
Icc8
(S only)
150
150
150
~
5,29
::D
REFRESH CURRENT: Extended (S version only)
Average power supply current during Extended Refresh:
CAS = 0.2V or CBR cycling; RAS = tRAS (MIN); WE= Vcc -0.2V;
AO-A9, OE, and DIN = Vcc -0.2V or 0.2V (DIN may be left open);
IRC = 12511S (1,024 rows at 12511S = 128ms)
REFRESH CURRENT: SELF (S version only)
Average power supply current during SELF REFRESH:
CBR cycle with IRAS <': IRASS (MIN) and CAS held LOW;
WE = Vcc -0.2; AO-A9,OE, and DIN = Vcc -0.2V or 0.2V
(DIN may be left open)
~
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: AO-A9
CI1
5
pF
2
Input Capacitance: RAS, CAS, WE, OE
CI2
7
pF
2
InpuVOutput Capacitance: DO
CIO
7
pF
2
MT4LC4007J(S)
D12.pm5- Rev. 2195
1-20
Micron Technology, inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC4007J(S)
1 MEG x 4 DRAM
",""CCO,",
::LECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address setup to CAS precharge
during WRITE
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulsewidth
RAS lOW to "don't care" during
SELF REFRESH cycle
CAS hold time (CBR REFRESH)
CAS to output in low-Z
Data output hold after CAS lOW
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable time
OE hold time from WE during
READ-MODIFY-WRITE cycle
OE HIGH hold time from CAS HIGH
OE HIGH pulse width
OE lOW to CAS HIGH setup time
Output buffer turn-off delay
OE setup prior to RAS during
HIDDEN REFRESH cycle
EDO-PAGE-MODE
READ or WRITE cycle time
EDO-PAGE-MODE
READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
,IMT4LC4007J(S)
b12.pm5 - Rev. 2/95
-6
-7
MIN
MAX
SYM
tAA
MIN
tACH
15
15
20
tAR
45
0
0
55
50
0
0
65
55
0
0
70
tASC
tASR
tAWD
tCAC
tCAH
tCAS
MAX
-8
30
tcHD
tcHR
tClZ
tCOH
tcp
10
3
5
10
10,000
22
15
15
10
10,000
10
3
5
10
MAX
40
35
18
10
10
10
MIN
22
15
15
10
10,000
10
3
5
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOEH
15
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOEHC
tOEP
toES
tOFF
tORD
10
10
5
3
0
10
10
5
3
0
10
10
5
3
0
ns
ns
ns
ns
ns
tpc
25
33
35
ns
tpRWC
85
100
105
ns
tRAC
tRAD
tRAH
tRAl
tRAS
15
10
30
60
tCPA
tCRP
tCSH
tCSR
tCWD
tCWl
tDH
tDHR
tDS
40
35
10
50
10
40
15
10
45
0
10
55
10
50
20
15
55
0
15
15
toD
tOE
15
60
30
10,000
1-21
45
10
65
10
50
20
15
60
0
20
20
15
10
35
70
20
70
35
10,000
20
20
15
10
40
80
20
80
40
10,000
ns
ns
ns
ns
ns
NOTES
m
c
o
C
::D
21
15
29
5
16
5
21
22
22
27
23
26
20
14
18
Micron Technology, Inc., reserves the right to change pToducts or specifications without notice.
©1995, Micron Technology, Inc.
»
s:
PRELIMINAR'Y
MICRON
1-·
-
m
c
o
C
JJ
l>
s:
"'""'00'
MT4LC4007J(S)
1 MEG x 4 DRAM
K
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vee
=+3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
'.,
AAS pulse width
(EDO PAGE MODE)
RAS pulse width during
SELF REFRESH cycle
RimdomREAD or WRITE cycle time
RAS to CAS delay time
tRASP
tRASS
tRC
Read command hold time (referenced to CAS)
tRCD
tRCH
Read command setup time
Refresh period (1,024 cycles)
tRCS
tREF
Refresh period (1,024 cycies) S version
'REF
tRP
RAS precharge time
RAS to CAS precharge time
tRPC
RAS precharge time during
SELF REFRESH cycle
tRPS
Read command hold time (referenced to RAS)
tRRH
RAS hold time
READ WRITE cycle time
tRSH
RAS to WE delay time
tRWC
tRWD
Write command to RAS lead time
Transition time (rise or fall)
tRWL
tT
Write command hold time
twCH
tWCR
Write command hold time (referenced to RAS)
WE command setup time
Output disable delay from WE (CAS HIGH)
twcs
tWHZ
Write command pulse width
WE pulse width for output
disable when CAS HIGH
twP
twpz
WE hold time (CBR REFRESH)
tWRH
WE setup time (CBR REFRESH)
tWRP
MT4lC4007J(S)
D12.pmS - Rev. 2/95
-7
-6
SYM
MIN
60
100
MAX
100,000
110
20
0
0
45
MIN
70
100
130
20
-8
MAX
100,000
50
0
0
MIN
80
100
150
20
0
0
16
128
16
128
50
0
130
60
0
150
0
15
150
85
15
2
10
45
0
3
10
10
0
20
180
100
20
2
15
55
0
3'
15
10
0
20
200
110
20
2
15
60
0
3
15
10
15
50
15
UNITS
NOTES
ns
~s
29
ns',
60
16
128
40
0
110
50
MAX
100,000
ns
17
ns
ns
19
ms
ms
".
ns
ns
ns
29
ns
ns
19
ns
50
ns
21
ns
ns
9,10
ns
ns
ns
15
21,27
ns'
ns
ns
i
10
10
10
10
1-22
10
10
ns
ns
25
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
i
I
PRELIMINARY
MICRON
1-·
MT 4LC4007 J(S)
1 MEG x 4 DRAM
"'"'0",","
~UTES
specified IRAD (MAX) limit, access time is controlled
exclusively by IAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. IWCS, tRWD, IAWD and ICWD are restrictive
operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. If twCS? twcs (MIN),
the cycle is an EARLY WRITE cycle and the data
output will remain an open circuit throughout the
entire cycle. IftRWD? IRWD (MIN), IAWD? IAWD
(MIN) and tCWD ? ICWD (MIN), the cycle is a
READ-MODIFY-WRITE and the data output will
contain data read from the selected cell. If neither of
the above conditions is met, the state of data-out is
indeterminate. OE held HIGH and WE taken LOW
after CAS goes LOW results in a LATE WRITE (OEcontrolled) cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. If OE is tied permanently LOW, LATE WRITE or
READ"MODIFY-WRITE operations are not permissible and should not be attempted.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE =LOW and OE =HIGH.
25. IWTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of IWRP and twRH in the
CBR REFRESH cycle.
26. LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. If OE is
taken back LOW while CAS remains LOW, the DQs
will remain open.
27. The DQs open during READ cycles once tOD or IOFF
occur.
28. Extended refresh current is reduced as IRAS is
reduced from its maximum specification during the
extended refresh cycle.
29. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
30. Column-address changed once each cycle.
All voltages referenced to Vss.
, This parameter is sampled. Vee = +3.3V ±O.3V;
f= 1 MHz.
\. Ice is dependent on cycle rates.
L Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
J. Enables on-chip refresh and address counters.
J. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOlls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
3. AC characteristics assume IT = 2.5ns.
9. VlH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS and RAS = VlH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
I
and 100pF. Output reference voltages are 0.8V for a
low level and 2.0V for a high level.
'14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
: than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
I
exceeds the value shown.
15. Assumes that IRCD? IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
. maintained from the previous cycle. To initiate a new
I
cycle and clear the data-out buffer, CAS must be
. pulsed HIGH for ICp.
\17. Operation within the IRCD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
Operation within the lRAD (MAX) limit ensures that
IRCD (MAX) can be met. IRAD (MAX) is specified as
a reference point only; if IRAD is greater than the
1
~I
t:~;4LC4007J(S)
.
,
f
~
~ D12.pm5 - Rev. 2/95
1-23
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Ino•
m
c
o
C
JJ
l>
S
PRELIMINAR'J
•
READ CYCLE
m
c
RC
tRP
tRAS
RAS
0
C
::xJ
V ,H
V"
\
leSH
1
'RSH
'CRP
CAS
»
s:
V,H
V"
=---.1
tAR
I~
ADDR
V,H
V"
.
~
i
IRAD
lAse.]
tRAH~1
~W!j'II!f
ROW
V,H
V"
NOTE 1
I.
V!!IIIfI
,I
I
i'
COLUMN
~I
tRCS
\
~I
Y
I tRAL • [
~l
~
~),{
I~ tWRP.:I· tWRH~1
WE
tCAS
'ACD
[.
I
tAA
I
'RAG
ROW
\
NOTE 2
~
tCAG
DO
~gt ::::-------OPEN------~~~VA~LlD~DA~TAj_--OPEN---
DE
777
TT7
TT7
TT7
~:t =7T;1//'7TW/
W/;
1/;7Ti
W/;77011/;'7TW/;777W/
0j7TiW/7Ti
W/;""1!/7771!/777W/
1;j77lW/;770W/'7TTW
;0lWIIIIII/1/1/11111/I/lIIIINII/I/;
1-
J
tOE
too
EARLY WRITE CYCLE
RC
'RP
'RAS
\
'oSH
J~
tRCD
'AR
ADDR
~I
I~ ~I
~i~ .w~
ROW
f ~::
I
tRAD
W/#~
I
I
IRAl
f
I
I~I
tACH
K0@';
COLUMN
ROW
'oWL
I
~ ~
I
I
~I
I
I
'RWl
'WeR
I~
'WP
~
DONTCARE
tIl&l UNDEFINED
NOTE:
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and 'WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
2. tOFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MT4LC4007J(S)
D12.pm5 - Rev. 2/95
1-24
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc
PRELIMINARY
IC::I=ICN
'"
MT4LC4007J(S)
1 MEG x 4 DRAM
,
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
00
OE
~igr :~--------OPEN--:--4lm~~~~~;j
OPEN---
~:~ :J/"w/$$/ffllffll//$/$/$.1'lM"ffllr
EDO-PAGE-MODE READ CYCLE
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAStime during an accesscycIEi·~REAOor WRITE), the system designer
should implement WE HIGH fot 'WRP and'WRH: This'desigh implementation will facilitatacompatibility with
future EDO DRAMs.
1-25
Micron TechnolOgy, Inc., reserves the rightto change products or specifications Without notice.
Cl1995. Micron Technology, 1nc.
PRELIMINAR
MIC:RON
1-·
MT4LC4007J(S)
1 MEG x 4 DRAM
'" "
-
EDO-PAGE-MODE EARLY-WRITE CYCLE
m
C
o
C
::D
»
s:
~:~
OE
='#I!!//I!I!II!!I!!I!I!III!/i/i/ii/i/i/i1/i/iI!ll!!I1!///i/i/i/l/II!I!!/ill!!////II!/iIII!/i/iII!/i/i/i//11/!I!I!!II!!/ih
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
_
vIH------.
RAS VIL -
1}------;:'c=sH:----------;:,PC-:-;/r.::'PR=wc::-:N""oT""'E'-----.:'R=SH------1
~H----'-_'=RCO"---_I--""CA"'-S_ _I ~
'cAs
~11_----",tcAS"----_1
00 ~:gr ::-~_-_
NOTE:
OPEN-
~
DON'T CARE
~
UNDEFINED
1.lpC is fo; LATE WRITE cycles only.
2. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE}. the system designer
should implement WE HIGH for IWRP e8ncl 'WRI·( This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC4007J(S)
D12.pm5 - Rev. 2195
1-26
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, MicrQn Technology, Inc
~
PRELIMINARY
-
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
m
c
'RASP
RAS
o
V1H_
VILtCSH
tpc
~
CAS
tpc
1l===tC=P==l ~ r-':t--,[
'ACD
VIH-
V1L-
C
JJ
»
S
ADDR
DQ
OE
~:r
~\gt
-----OPEN
----:=-C~V~AL~ID~DA~TA~IAI==:jC~~j
~:r= ~/&/$$//$j;lffii~
HIDDEN REFRESH CYCLE 24
(WE =HIGH; OE = LOW)
IREAD)
(REFRESH)
tRAS
l~
.
IRCD
:~
~
ADDR
~IHIL-~lr---I~
tRAH
tRAS
1
IRSH
tAR
tRAD
.~
~II
II t~LI
~II~
tCHR
_.j
~
__
too
}$$//$$i
r-.lOTE:
I
I
I:ZZJ
DON'T CARE
~
UNDEFINED
1~ Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and twRH~ This design implementation will facilitate compatibility with
future EDO DRAMs~
I
~T4LC4007J('S)
I 12.pm5-Rev. 2195
1-27
Micron Technology, inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINAR't
-
CBR REFRESH CYCLE
(Addresses and OE = DON'T CARE)
m
o
o
o
RP
----.1
:IJ
»
s:
CAS
..-I
0:;:~~ 1
RAS
,I
~~
OPEN---fIIC----------
I~II~I
I~II~I
'o//j////II////////J///J}
)'/////////////-
.
Y
II
DO
,
~r29~
~:~_
~:~
RP
III
1
'RPC
WE
RAS
WII/I!IIIII!IIIII/J///II//I////2
RAS-ONL Y REFRESH CYCLE
(WE = DON'T CARE)
:::d
ADDR
DQ
~:t ::wd
~gt
'w
•
'ASR
'RAH
ROW'
tWRP
WE
"~
!"
II(I
"~ "~
'~;///////m/;lm/;l;/$U/////$;I//////,..0(
OPEN
'WRH
'WAP
ROW
III
\
tWRH
~:t Ju;@///,d----:T;;--Wmm;///01///01;1;///$$;/'/;1///01)- - .
~
DON'T CARE
m
UNDEFINED
NOTE:
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC4007J{S)
D12.pm5 - Rev, 2195
1-28
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1995, Micron Technology, Inc.
PRELIMINARY
-
SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
m
c
o
C
::D
l>
S
~
DON'TCARE
~
UNDEFINED
I
I
I
!NOTE:
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed .
.1
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: D12.pm5 - Rev. 2f95
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©1995, Micron Technology, Inc,
PRELIMINARY
-
READ CYCLE
(with WE-controlled disable)
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IZZI DON'T CARE
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NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and IWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4lC4007J(S)
D12.pm5- Rev. 2195
1-30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC4M4E8(S)
4 MEG x 4 DRAM
'"'"""""'''
DRAM
4 MEG x 4 DRAM
24/26-Pin SOJ
(DA-2)
24/26-Pin TSOP
(DB-2)
Vee
Vss
Vee
Vss
DQ1
DQ2
DQ4
DQ3
CAS
DQ1
DQ2
DQ4
DQ3
CAS
OE
RAS
NC
WE
RAS
NC
OPTIONS
MARKING
• Timing
60ns access
70ns access
AlO
AD
A1
A2
A3
-6
Vee
A9
AS
A7
A6
AS
A4
Vss
WE
OE
A9
A1D
AD
A1
A2
A3
Vee
-7
• Packages
Plastic SOl (300 mil)
Plastic TSOP (300 mil)
DJ
TG
• Refresh Rate
Standard 32ms period
SELF REFRESH and 128ms period
None
S
• Part Number Example: MT4LC4M4E8DJ-7 S
If WE goes LOW after CAS goes LOW, data-out (Q) is
activated and retains the selected cell data as long as OE
remains LOW and RAS or CAS remains LOW (regardless of
WE). This late WE pulse results in a READ WRITE cycle. If
WE toggles LOW after CAS goes back HIGH, the output
pins will open (High- Z) until the next CAS cycle, regardless
ofOE.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by WE and OE.
KEY TIMING PARAMETERS
I
I
SPEED
tRC
tRAC
tpc
tAA
tCAC
tCAS
I
-6
-7
110ns
130ns
60ns
70ns
25ns
30ns
30ns
35ns
15ns
20ns
10ns
12ns
GENERAL DESCRIPTION
The MT4LC4M4E8(S) is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x4 configuration. The MT4LC4M4E8(S) RAS is used to latch the
first 11 bits and CAS the latter 11 bits. READ and WRITE
cycles are selected with the WE input. A logic HIGH on
WE dictates READ mode while a logic LOW on WE dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of WE or CAS, whichever occurs last. If
WE goes LOW prior to CAS going LOW, the output pins
remain open (High- Z) until the next CAS cycle, regardless
ofOE.
MT4LC4M4E8(S)
D24.pmS - Rev. 2/95
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-addressdefined page boundary. The PAGE cycle is always initiated
with a row-address strobed-in by RAS followed by a column-address strobed-in by CAS. CAS may be toggled-in
by holding RAS LOW and strobing-in different columnaddresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the PAGE MODE of operation.
1-31
:e
•
c
o
PIN ASSIGNMENT (Top View)
• Industry-standard x4 pinout, timing, functions and
packages
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• Low power, O.4mW standby; 150mW active, typical
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN and SELF
2,048-cycle (11 row-,ll column-addresses)
• Optional SELF REFRESH, Extended Refresh rate (4x)
• Extended Data-Out (EOO) PAGE access cycle
• 5Vtolerant I/Os (5.5V maximum VIH level)
m
m
3.3V, EDO PAGE MODE,
OPTIONAL SELF REFRESH
FEATURES
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Micron Technology, Inc" reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
C
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PRELIMINARY
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s:
EDO PAGE MODE
REFRESH
TheMT4LC4M4E8(S) provides EDOPAGE MODE which
is an accelerated FAST PAGE MODE cycle, The primary
advantage of EDO is the availability of data-out.even after
CAS returns HIGH. EDO allows CAS precharge time (tcP)
to occur without the output data going invalid. This elimination of CAS output control allows pipeline READs.
FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS. EDO-PAGE-MODE DRAMs operate Similarly to
FAST-PAGE-MODE DRAMs, except data will remain valid
or become valid after CAS goes HIGH during READs,
provided RAS and OE are held LOW. If OE is pulsed while
RAS and CAS are LOW, data will toggle from valid data to
High-Z and back to the same valid d~ta. If OE is toggled or
pulsed after CAS goes HIGH while RAS remains LOW,
data will transition to and remain High-Z (refer to Figure 1).
WE can also perform the function of disabling the output
devices under certain conditions, as shown in Figure 2.
If the DQ outputs are wire OR'd, OE must be used to
disable idle banks of DRAMs. Alternatively, pulsing WE to
the idle banks during CAS high time will also High-Z the
outputs. Independent of OE control, the outputs will disable after tOFF, which is referenced from the rising edge of
RAS or CAS, whichever occurs last.
Preserve correct memory cell data by maintaining power
and executing a RAS cycle (READ, WRITE) or RAS refresh
cycle (RAS ONLY, CBR, or HIDDEN) so that all 2,048
combinations of RAS addresses are executed at least every
32ms, regardless of sequence. The CBR REFRESH cycle will
invoke the refresh counter for automatic RAS addreSSing.
An optional SELF REFRESH mode is also available on the
MT4LC4M4E8 S. The "5" version allows the user the choice
of a fully static low-power data retention mode, or a dynamic refresh mode at the extended refresh period of 128ms
four times longer than the standard 32ms specification.
The optional SELF REFRESH feature is initiated by
performing a CBR REFRESH cycle, and holding RAS LOvV
for the specified tRASS. Additionally, the "S" version allows for an extended refresh rate of 62.5f..ls per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby or BATTERY
BACKUP mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH fora minimum timeoftRPS(~tRC). This delay allows
for the completion of any internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not reqUired upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all 2,048 rows must
be refreshed within 300f..ls prior to the resumption of normal
operation.
MT4lC4M4E8(S)
D24.pmS- Rev. 2195
1-32
Micron Technology, Inc., reserves the righllo change products or specifications wH:hout notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MIC:RON
I~·
MT4LC4M4E8(S)
4 MEG x 4 DRAM
"'""'''"''''
~:~=~~
RAs
____________________________-'-_______________
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OE
~:~-
II
\COLUMN{C)
VAU~D : :(B)
VAUD DATA (A)
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COLUMN (D)
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VAUODATAlD)
-
~_ _ _ _ _ _ _---;I toE; ~--------
!
The DOs go back to
Low-Z if tOES is met.
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!
The DOs remain High-Z
until the next CAS cycle
if tOEHC is met.
The DOs remain High-Z
until the next
cycle
if tOEP is met.
CAs
Figure 1
OUTPUT ENABLE AND DISABLE
~
~i~:~~
_______________________________________________
ADDR
DO ~:g~-
______
VALID DATA (Al
VALID DATA (8)
6E ~:t:--------
,--------+--1_~, I~I'
t.WPZ
~
tWHZ
~ ,I
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I
/
/ /
____-_-_--_
+-----__
_
-+--_________I-______-T_'--_ _ _ _ _ __
I
WE may be used to disable the DOs to prepare
The DOs go to High-Z if \iVE falis, and if twpz is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
for input data in an EARLY WRITE cycle. The DOs
will remain High-Z until GAS goes LOW with
WE HIGH (Le., until a READ cycle is initiated).
~
DON'TCAHE
!&&\l
UNDEFINED
Figure 2
WE CONTROL OF DOs
MT4LC4M4E8(S)
D24.pm5 - Rev. 2/95
1-33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, InC.
»
s::
PRELIMINARY
z
m
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MICRON
1-·
•
MT4LC4M4E8(S)
4 MEG x 4 DRAM
",""",00"",
FUNCTIONAL BLOCK DIAGRAM
WE~------------------------------~--------------+l----~
m
DQ1
DQ2
DQ3
DQ4
CAS~~----------------------------1-~----------~
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AO~~~~
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A1
A2
A3
'------""-"".,
A4
AS
A6
A7
AS
A9
A10
RAS
TRUTH TABLE
ADDRESSES
IC
DATA-IN/OUT
RAS
CAS
WE
Of
tR
Standby
H
H--+X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
READ WRITE
L
L
H--+L
L--+H
ROW
COL
Data-Out, Data-In
FUNCTION
DQ1-DQ4
EDO-PAGE-MODE
1st Cycle
L
H--+L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H--+L
H
L
n/a
COL
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H--+L
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd Cycle
L
H--+L
L
X
n/a
COL
Data-In
EDO-PAGE-MODE
1st Cycle
L
H--+L
H--+L
L--+H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H--+L
H--+L
L--+H
n/a
COL
Data-Out, Data-In
L
H
X
X
ROW
n/a
High-Z
L
H
L
ROW
COL
Data-Out
RAS-ONLY REFRESH
HIDDEN
READ
L--+H--+L
REFRESH
WRITE
L--+H-L
L
L
X
ROW
COL
Data-In
CBR REFRESH
H-L
L
H
X
X
X
High-Z
SELF REFRESH
H-L
L
H
X
X
X
High-Z
MT4LC4M4E8(S)
D24.pm5 - Rev. 2195
1-34
Micron Technology, Inc., reserves the right to change products or specilicatlons without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
'"
MT4LC4M4E8(S)
4MEGx4DRAM
W
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'Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sectionS of this speCification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. -
A.BSOLUTE MAXIMUM RATINGS*
Voltage on Vee pin Relative to Vss ................. -IV to +4.6V
Voltage on Inputs or I/O pins
Relative to Vss ........ :............................................ -IV to +S.5V
Operating Temperature, TA(ambient) .......... O°C to +70°C
Storage Temperature (plastic) ................... -SsoC to +IS0°C
Power Dissipation ............................................................. IW
Short Circuit' OutputCurrent ..................................... SOmA
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ELECtRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vce = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
Supply Voltage
Vee
3.0
3.6
V
Input High (Logie 1) Voltage, all inputs (including NC pins)
VIH
VILo
2.0
-1:0
5.5
V
0.8
V
II
-2
2
IlA
10
!lA
Inpllt Low (Logic 0) Voltage, all inputs (including f\jC pins)
INPUT LEAKAGE CURRENT
-Any input OV ::; VIN ::; 5.5V
(All other pins not under test = OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV < VOUT < 5.5V)
loz
I- -10
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
VOH
'2,.4
MT4LC4M4E8(S),
D24.pm5 - Rev. 2/95
VOL
1-35
UNITS NOTES
V
0.4
V
Micron Technology, Inc., reserves the right to change prOducts or specifications without notice.
@1995,MicronTechnology,Inc.
l>
-=:
PRELIMINARY
z
m
MICRON
1-·
MT4LC4M4E8(S)
4 MEG x 4 DRAM
,~,
~--------------------------------------
-
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:s::
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc= +3.3V±0.3V)
,"
"
MAX
SYMBOL
-6
-7
UNITS
ICC1
,2
2
mA
ICC2
Icc2
(S only)
500
150
500
150
).lA'
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS; CAS, Address Cycling:,IRC= IRC[MIN])
ICC3
120
110
mA
3,4,12
OPERAT!NG CURRENT: fDO PAGE MODE
.l\verage power supply ~urrent
(RAS = VIL, CAS, Address Cycling: IpC = IpC[MIN)
ICC4
110
100
rnA
3,4,12
REFRESH CURRENT: RAS ONLY
Average powersupplycurrent
(RAS Cycling, PAS", VIH:,iRC = IRC [MIN)
'ICC5
120
110
mA
3, 12
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
Iccs
120
110
mA
3,5
REFRESH CURRENT: Extended (S version only)
Average power supply current, CAS = 0.2Vor CBR cycling;
RAS = IRAS (MIN); WE = Vcc -0.2V; AO-A10, OE and DIN =
Vcc -0.2V orO.2V(DIN may be iaft open); IRC = 62.5J.1.S
ICC7
(Sonly)
300
300
~
3,5
REFRESH CURRENT: SELF (S version only)
Average power supply current, CBR cycling with RAS ~ IRASS(MIN)
and CAS held LOW; WE = Vcc -0.2V; AO-A10,
OE and DIN = Vcc -0.2V or 0.2V(DIN may be left open)
ICC8
(Sonly)
300
300
~
5
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
,
"
"
STANDBY CURRENT: (CMOS)
(RAS = CAS = Other Inputs = Vcc -0.2V)
MT4lC4M4Ea(S)
D24.pmS - Rev. 2195
NOTES
1-36
~
Micron Technology, Inc., reserves the right to change products or specllk:atlons without notice.
@1995,MicronTechnology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC4M4E8(S)
4 MEG x 4 DRAM
"'""'w,'"'
CAPACITANCE
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: Address pins
Cit
5
pF
Input Capacitance: RAS, CAS, WE, OE
CI2
7
pF
Input/Output Capacitance: DO
CIO
7
pF
2
2
2
PARAMETER
z
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, to, 11, 12) (Vcc =+3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address set-up to CAS precharge during WRITE
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Accesstime from CAS
Column-addresS hold time
CAS pulse width
CAS LOW to "don't care" during SELF REFRESH cycle
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
Data output hold after next CAS LOW
CAS precharge time
. Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
.
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable
OE hold time from WE during READ'MODIFY-WRITE cycle
OE HIGH hold from CAS HIGH
MT4LC4M4E8(S)
D24.pm5 - Rev. 2195
-7
-6
SYM
MIN
tAA
tACH
tAR
tASC
tASR
tAWD
tCAC
tcAH
tCAS
tCHD
tCHR
tcLZ
tCOH
tcp
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDHR
IDS
tOD
tOE
IOEH
IOEHC
1-37
MAX
MIN
30
15
45
0
0
55
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10,000
20
12
12
15
12
0
5
10
15
15
10,000
40
35
5
50
5
35
15
10
45
0
0
UNITS
35
15
55
0
0
65
15
10
10
15
10
0
5
10
MAX
5
55
5
40
15
12
55
0
0
12
10
15
15
NOTES
20
14
25
5
15
5
20
21
21
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
l>
S
PRELIMINARY
z
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MICRON
1- •
MT4LC4M4E8(S)
4 MEG x 4 DRAM
m~'occ" '"
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
OE HIGH pulse width
OE LOW to CAS HIGH setup time
Output buffer turn-off delay
OE setup prior to RAS during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hoid time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (EDO PAGE MODE)
RAS pulse width during SELF REFRESH cycle
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (2,048 cycles)
Refresh period (2,048 cycles) S version
RAS precharge time
RAS to CAS precharge time
RAS precharge time during SELF REFRESH cycle
Read commaod hold time (referenced to RAS)
RAS hold time
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WE command setup time
Output disable delay from WE
Write command pulse width
WE pulse to disable at CAS HIGH
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT4lC4M4E8(S)
D24.pm5- Rev. 2/95
-7
-6
SYM
tOEP
tOES
tOFF
'ORD
tpc
tpRWC
tRAC
tRAD
tRAH
'RAL
'RAS
'RASP
'RASS
'RC
'RCD
'RCH
'RCS
'REF
'REF
tRP
'RPC
'RPS
'RRH
'RSH
tRWC
'RWD
tRWL
'T
tWCH
tWCR
twcs
twHz
twp
WPZ
tWRH
'WRP
1-38
MIN
10
5
3
0
25
75
12
10
30
60
60
100
110
14
MAX
15
60
30
10,000
125,000
45
0
0
MIN
10
5
3
0
30
85
12
10
35
70
70
100
130
14
15
70
35
10,000
125,000
50
0
0
32
128
40
0
110
0
10
150
80
15
2
10
45
0
0
10
10
10
10
MAX
50
13
32
128
50
0
130
0
12
177
90
15
2
12
55
0
0
12
12
10
10
50
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
J.lS
25
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
17
16
18
25
18
20
20
24
24
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
@1995,MicronTechnology,lnc.
PRELIMINARY
UII::::I=ICN
1-·
MT 4LC4M4E8(S)
4 MEG x 4 DRAM
,ec~"OCOC""
NOTES
18. Either tRCH or tRRH must be satisfied for a READ
cycle.
19. tOFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL. It is referenced from the
rising edge of RAS or CAS, whichever occurs last.
20. twcs, IRWD, tAWD and tCWD are not restrictive
operating parameters. twcs applies to EARLY
WRlTE cycles. tRWD, tAWD and tcWD apply to
READ-MODIFY-WRlTE cycles. If tWCS;:: twcs
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If twcs < twcs (MIN) and tRWD ;::
tRWD (MIN), tAWD;:: tAWD (MIN) and tCWD;::
tCWD (MIN), the cycle is a READ-MODIFY-WRlTE
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE held HIGH
and WE taken LOW after CAS goes LOW results in n
LATE WRITE (OE-controlled) cycle. twcs, tRWD,
tCWD and tAWD are not applicable in a LATE
WRITE cycle.
21. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRlTE or READ-MODIFY-WRITE cycles.
22. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRlTE operations are not permissible and should not be attempted. Additionally, WE
must be pulsed during CAS HIGH time in order to
place I/O buffers in High-Z.
23. A HIDDEN REFRESH may also be performed after a
WRlTE cycle. In this case, WE =LOW and OE =HIGH.
24. twTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of twRP and IWRH in the
CBR REFRESH cycle.
25. Refresh must be completed within the time of three
external refresh rate periods prior to active use of the
DRAM (provided distributed CBR REFRESH is used
when in the active mode). Alternatively, a complete
set of row refreshes must be executed when exiting
SELF REFRESH prior to active use of the DRAM if
anything other than distributed CBR REFRESH is
used in the active mode.
1.
2.
3.
4.
All voltages referenced to Vss.
This parameter is sampled. Vee = +3.3V; f = 1 MHz.
Ice is dependent on cycle rates.
Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOlls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume tT = 2.5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. Column address changed once each cycle.
12. Measured with a load equivalent to two TTL gates,
100pF and VOL = 0.8V and VOH = 2.0V.
13. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that IRCD
exceeds the value shown.
14. Assumes that IRCD;:: IRCD (MAX).
15. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
16. Operation within the IRCD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified tRCD (MAX) limit, then access time is
controlled exclusively by tCAC, provided lRAD is not
exceeded.
17. Operation within the IRAD (MAX) limit ensures that
tRAC (MIN) and ICAC (MIN) can be met. lRAD
(MAX) is specified as a reference point only; if IRAD
is greater than the specified lRAD (MAX) limit, then
access time is controlled exclusively by IAA, provided
tRCD is not exceeded.
MT4LC4M4E8(S)
D24.pmS - Rev. 2195
1-39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
z
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~--------------------------------------
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READ CYCLE
'RC
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~:gt
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~I
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'WP
VALID DATA
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
2. tOFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MT4LC4M4E8(S)
D24l
T77
)~I
~
W//$$$/"$;)2
.
EDO-PAGE-MODJ: READ CYCLE
rz:I DON'T CARE
!2\ll UNDEFINED
NOTE:
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and twRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC4M4E8(S}
D24.pm5 - Rev. 2/95
1-41
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology,lnc.
PRELIMINARY
z
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~-------------------------
•
EDO-PAGE-MODE EARLY-WRITE CYCLE
A-
RASP
m
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ROW
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~:~ ~
NOTE
lAse
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'Ase
iI
IRAL
leAH
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---=---
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(LATE WRITE and READ-MODIFY-WRITE cycles)
RASP
RP
IpC /IPRWC NOTE 1
teSH
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tRCD
=J
IAR
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ADDR
~:~
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lRAH"
tASR
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VALID
~
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DOUl
VALID
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UNDEFINED
1. IpC is for LATE WRITE cycles only.
2. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC4M4E8(S)
D24.pmS - Rev. 2/95
1-42
Micron Technology, Inc., reserves the right to change products or specificatioris without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
z
m
~
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EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODI FY-WRITE)
m
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RAS
CAS
ADDR
V,H
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~:~-.:=0
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tASR
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Vil _
DO VOH VOL
WE
teRP
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ROW
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,
111
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NOTE:
I
D24.pmS _ Rev. 2/95
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibilitywith
future EDO DRAMs.
MT4LC4M4E8(S)
1-43
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
z
m
~------~-------------------------------
•
CBRREFRESH CYCLE
(Addresses and OE = DON'T CARE)
m
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tRPC
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SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
NOTE:
~
DON'TeARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH. mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT4LC4M4E8{S)
D24.pm5 - Rev. 2/95
1-44
Micron Technology, Jnc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC4M4E8(S)
4 MEG x 4 DRAM
" ,
z
m
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•
READ CYCLE
(with WE-controlled disable)
RAs
VIH
VIL _
,
CAS
'cRP
VIH VIL -
.~:
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r-------1
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC4M4EB(S)
D24.pm5 - Rev. 2/95
1-45
Micron Technology. Inc., reserves the rightltl Ch~ products or specifications without notice.
'.
@1995,MicronTechnology,lnc.
PRELIMINARY
z
m
MICRON
1-·
MT4LC4M4E8(S)
4 MEG x 4 DRAM
c,
~--------~------------~-
•
HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE=LOW)
m
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.
(REFRESH)
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• 1----"'---1
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~:~ :1/!/!//////!///l/////////////////////1iO
:-:0 .
m
DON'T CARE
~
MT4~M4E8(S)
D24.pm5 - Rev. 2195
1-46
UNDEFINED
Micron Technology. Inc., reserves the rJgIlt to change products or specifications without notloe.
@1995,MlcronTechnology,lnc.
ADVANCE
MICRON
1-·
MT4LC16M4G3/H9
16 MEG x 4 DRAM
'''""'c'"''"'
m
~
DRAM
16 MEG x4 DRAM_
m
3.3V, EDO PAGE MODE
c
o
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x4 pinout, timing, functions and
packages
• 13 row-addresses, 11 column-addresses (G3) or
12 row-addresses, 12 column-addresses (H9)
• High-performance CMOS silicon-gate process
• All inputs and outputs are LVTTL-compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS-BEFORE-RAS (CBR) REFRESH
distributed across 64ms
OPTIONS
MARKING
• Timing
SOns access
60ns access
70ns access
-5
-6
PIN ASSIGNMENT (Top View)
Vee
DQ1
DQ2
NC
NC
NC
NC
RAS
NC
AD
A1
A2
A3
-7
DW
TW
A4
• Part Number Example: MT4LC16M4G3DW"7
A5
Vee
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tpc
tAA
tCAC
tCAS
-5
-6
-7
90ns
110ns
130ns
50ns
60ns
70ns
20ns
25ns
30ns
25ns
30ns
35ns
13ns
15ns
20ns
8ns
10ns
12ns
1•
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2D
19
18
S
Vss
DQ4
DQ3
NC
NC
NC
CAS
OE
NC
A12/NC
A11
A1D
A9
A8
A7
A6
Vss
34-Pin TSOP*
Vee
DQ1
DQ2
NC
NC
NC
NC
GENERAL DESCRIPTION
The MT4LC16M4G3 andMT4LC16M4H9 are high-speed
CMOS dynamic random accessmemory devices containing
67,108,864 bits, and designed to operate from 3.0V to 3.6V.
The MT4LC16M4G3 and MT4LC16M4H9 are functionally
organized as 16,777,216Iocations containing4bits each. The
16,777,216 memory locations are arranged in 8,192 rows by
2,048 columns for the MT4LC16M4G3 or 4,096 rows by
4,096 columns for the MT4LC16M4H9. During READ or
WRITE cycles, each location is uniquely addressed via the
address bits. First, the row address is latched by the RAS
signal, then the column address by CAS. Both devices
provide EDO PAGE MODE operation, allowing for fast
successive data operations (READ, WRITE or READMODIFY-WRITE) within a given row.
The MT4LC16M4G3 and MT4LC16M4H9 must be refreshed periodically in order to retain stored data.
WE
RAS
NC
AD
A1
A2
A3
A4
A5
Vee
Vss
DQ4
DQ3
NC
NC
NC
CAS
OE
NC
A12/NC
A11
A10
A9
A8
A7
A6
Vss
'C6nsult factory for dimensions and availability.
1-47
C
lJ
l>
34-Pin SOJ
(DA-6)
WE
• Packages
Plastic SOJ (500 mil)
Plastic TSOP (500 mil)
MT4LC16M4G3IH9
D22.pmS ~ Rev. 2/95
z
Micron Technology, Inc., reserves the right to change products or specifications without notlCe.
©1995, Micron Technology, Inc.
ADVANCE
z
m
:E
MICRON
MT 4LC16M4G3/H9
16 MEG x 4 DRAM
"c~"ocoo"c
1-·
•
FUNCTIONAL BLOCK DIAGRAM
MT4LC16M4G3 (13 row-addresses)
m
c
o
c
WEO
DOl
D02
D03
D04
CASO~-,r--------------------r==~~;.;~__~________~
XI
L-----------------------~~------~OE
l>
3:
A3
A4
A5
A6
A7
AB
A9
8192x2048x4
Al0
MEMORY
ARRAY
<>----~~~~iJ.~•••~
A 12 <>---"'"¥~I.!
All
Vee
RAS
Vss
FUNCTIONAL BLOCK DIAGRAM
MT4LC16M4H9 (12 row-addresses)
WEO
DQl
DQ2
DQ3
DQ4
CAS~o--~--------------------------.
L-------------------------~~~~--~OE
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
4096 x 4096 x 4
All
ARRAY
MEMORY
RAS
MT4lCl SM4G3JH9
D22.pm5 - Rev. 2/95
1-48
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LC16M4G3/H9
16MEGx4DRAM
,,'
FUNCTIONAL DESCRIPTION
The functional description for the MT4LC16M4G3 and
MT4LC16M4H9 is divided into the two areas described
below (DRAM access and DRAM refresh). Relevant timing
diagrams are included in this data sheet, following the
timing specifications tables.
DRAM ACCESS
Each location in the DRAM is uniquely addressable as
mentioned in the General Description. The data for each
location is accessed via the four I/O pins (DQl-4). The WE
signal must be activated to execute a write operation, otherwise a read operation will be performed. The OE signal
must be activated to enable the DQ output drivers for' a read
access and can be deactivated to disable output data if
necessary.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS. If
CAS went HIGH, and OE was LOW (active), the output
buffers would be disabled. The MT4LC16M4G3 and
MT4LC16M4H9 offer an accelerated PAGE MODE cycle'by
eliminating output disable from CAS HIGH. This option is
called EDO and it allows CAS precharge time (tcP) to occur
without the output data going invalid (see READ and EOOPAGE-MODE READ waveforms).
EDO operates as any DRAM READ or FA5T-PAGEMODE READ, except data will be held valid after CAS
goes HIGH, as long as RAS and OE are held' LOW and
WE is held HIGH. OE can be brought LOW or HIGH while
CAS and RAS are LOW, and the DQs will transition between valid data and High-Z. Using OE, there are two
methods to disable the outputs and keep them disabled
during the CAS HIGH time. The first method is to have
OE HIGH when CAS transitions HIGH and keep OE
HIGH for tOEHC thereafter. This will disable the DQs and
they will remain disabled (regardless of the state of OE after
that point) until CAS falls again~ The second method is to
MT4LC16M4G3JH9
022.pm5 - Rev: 2195
have OE LOW when CAS transitions HIGH. Then bringing
OE HIGH for a minimum of toEP anytime during the
CAS HIGH period will disable the DQs; the DQs will
remain disabled (regardless of the state of OE after that
point) until CAS falls again (please refer to Figure 1).
During other cycles, the outputs are disabled at tOFF time
after RAS and CAS are HIGH, or twHzafter WE transitions
LOW. The tOFF time is referenced from the rising edge of
RAS or CAS, whichever occurs last. WE can also perform
the function of disabling the output drivers under certain
conditions, as shown in Figure 2:
'
EDO PAGE MODE operations are always initiated with
a row-address strobed-in by the RAS signal, followed by
a column-address strobed-in by CAS, just like for single
location accesses. However, subsequent column locations
within the row may then be accessed atthe page mode cycle
time. This is accomplished by cycling CAS while holding
RAS LOW, and entering new column addresses with each
CAS cycle. Returning RAS HIGH terminates the EOO
PAGE MODE operation.
DRAM REFRESH
The supply voltage must be maintained at the specified
levels, and the refresh requirements must be met in order to
retain stored data in the DRAM. The refresh requirements
are met by refreshing all 8,192 rows (G3) or all 4,096 rows
(H9) in the DRAM array at least once every 64ms. The
recommended procedure is to execute4,096 CBRREFRESH
cycles, either uniformly spaced or grouped in bursts, every
64rns. The MT4LC16M4G3 internally refreshes two rows
for every CBR cycle, whereas the MT4LC16M4H9 refreshes
one row for every CBR cycle. So with either device, executing 4,096 CBR cycles covers all rows. Alternatively,
RAS-ONLY REFRESH capability is inherently provided.
However, with this method only one row is refreshed at
a time, so for the MT4LC16M4G3, 8,192 RAS-ONLY
REFRESH cycles must be executed every 64ms to cover all
rows.
Micron Technology, Inc., reserves the right to chan;l8 products or specifications withOut DOtIce.
@1995,MlcronTeohnology,lnc.
z
m
:e
•
m
c
o
C
:IJ
l>
s:
ADVANCE
z:
m
MIC:I=ICN
1-·
cc,
MT4LC16M4G3/H9
16MEGx4DRAM
c
=e
•
~:~:~L____________________________________________
RAi
m
C
o
c
AboJl
: COLUMN (A)
\
\POl.UMN{C)
COLUMN (D)
:c
»
s::
OQ
~lgr
-----
"',
VAUO DATA (e)
VAUDDATA(A)
I
~~L
VALlO DATA (O)
I~
~
OE ~i~:C---------
____________
I
I
The DOs go back to
low-Z If toES is met.
_ _ _ _ _ _ _ _ _ _ _ __
I
The DOs, remain High-Z
until the next CAS cycle
The DOs remain High·Z
until the next CAS cycle
if toEHC is met.
if tOEP Is met.
Figure 1
OE CONTROL OF DQs
~ ~lr:~L~
____________________________________________
1 iW'$'~/'@< 1 Y#t7~#t7+
/'\'----~
AOOR
DC
~:r:~ (~UMN(A) >Wt7#lt7!1l$t7#&WffY
COLUMN (B)
COLUMN{Cj
I
-'--.
I
~:gr:---~--OPEN '---'--~~!::=~~~~=~"-~----~![==~~~===f
~ ~:r:
VALIOOATA(A)
I
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VAUDDAT.A(B)
I
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q
"
INPUT DAT~ (0)
I "I
Z
/
__________________-+______-+_________-+_~___~_______
I
The DOs go to Hlgh-Z if WE faJls. and If twpz is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e.• until a READ cycle is in1tiated).
7
WE may be used to disable the DOs to prepare
for input data In an EARLY WRITE cycle. The DOs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle il;! initiated).
~DON'TCARE
~
UNDEF(NED
Figure 2
WE CONTROL OF DQs
MT4lCt6M.f.G3JH9
D22.pm5 ~ Rev. 2/95
1-50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
I-a
MT4LC16M4G3/H9
16 MEG X 4 DRAM
",""ococne
z
m
~
ABSOLUTE MAXIMUM RATINGS*
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximUJ;n rating conditions
for extended periods may affect reliability.
Voltage on Vee Relative to Vss ..................... -l.OV to +4.6V
Voltage on Inputs or I/O Pins
Relative to Vss ................................................. -l.OV to +S.5V
Operating Temperature, TA (ambient) .......... O°C to +70°C:
Storage Temperature (plastic) .................... -SsoC to +ISO°C
Power Dissipation ............................................................. IW
Short Circuit Output Current ..................................... SOmA
•
m
c
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C
:::D
l>
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vee
=+3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
O.B
V
Ii
-2
2
)lA
loz
-10
10
~A
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV :s; VIN :s; 5.5V
(All other pins not under test = OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV < VOUT < 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
MT4LC16M4G3JH9
D22.pmS - Rev. 2195
VOL
1-51
NOTES
V
0.4
V
Micron Technology, Inc., reserves the right to change products or specifications without !,\otiee.
©1995, Micron Technology, Inc.
s:
ADVANCE
z
m
MICRON
1-·
MT 4LC16M4G3/H9
16 MEG x 4 DRAM
,<,~'c'c,,"
~-------------------------
•
m
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:s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +3.3V ±0.3V)
MAX
VERSION
SYMBOL
-5
-6
-7
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
MT4LC16M4G3
MT4LC16M4H9
ICCl
ICCl
1
1
1
1
1
1
STANDBY CURRENT: (CMOS)
(RAS = CAS;>: Vcc -0.2V, DOs may be left open,
Other inputs: VIN ;>: Vcc -0.2V or VIN :0; 0.2V)
MT4LC16M4G3
MT4LC16M4H9
Icc2
Icc2
500
500
500
500
500
500
~
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC= tRC [MIN])
MT4LC16M4G3
MT4LC16M4H9
Icc3
Icc3
130
170
120
160
110
150
mA
3,4,
29
OPERATING CURRENT: EDO PAGE iviODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: tpc = tpc [MIN])
fviT4LCi6M4G3
MT4LC16M4H9
Icc4
Icc4
150
150
120
120
100
100
mA
3,4,
29
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: tRC = tRC [MIN])
MT4LC16M4G3
MT4LC16M4H9
Iccs
Iccs
130
170
120
160
110
150
mA
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIN])
MT4LC16M4G3
MT4LC16M4H9
Icc6
Icc6
140
170
.130
160
120
150
mA
PARAMETER/CONDITION
MT4lC16M4G3IH9
D22.pm5 - Rev. 2195
1-52
UNITS NOTES
mA
3,26
3,5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
z
m
:e
CAPACITANCE
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: Address pins
CI1
5
pF
2
Input Capacitance: RAS, CAS, WE, OE
CI2
7
pF
2
Input/Output Capacitance: DQ
CIO
9
pF
2
PARAMETER
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address set-up to CAS
going HIGH during WRITE
Column-address hold time
(referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
Data output hold after CAS LOW
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable time
OE hold time from WE during
READ-MODIFY-WRITE cycle
OE HIGH hold time from CAS HIGH
OE HIGH pulse width
OE LOW to CAS HIGH setup time
MT4lC16M4G31H9
D22.pm5 - Rev. 2195
-5
-7
-6
MIN
MAX
tAA
MIN
25
MAX
MIN
30
MAX
UNITS
35
tACH
15
15
15
ns
ns
tAR
40
45
55
ns
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHR
tCLZ
0
0
48
0
0
55
0
0
65
toEH
8
10
12
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tOEHC
tOEP
tOES
7
7
4
10
10
5
10
10
5
ns
ns
ns
tCOH
tcp
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDHR
tDS
tOD
tOE
13
8
8
10,000
8
0
5
8
10
10
10
0
5
10
28
5
44
5
30
8
8
40
0
0
1-53
13
13
20
15
10,000
12
12
12
0
5
10
40
35
5
50
5
35
15
10
45
0
0
15
15
10,000
5
55
5
40
15
12
55
0
0
15
15
o
»
:s:
=+3.3V ±0.3V)
SYM
m
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vcc
•
NOTES
21
15
5
16
5
21
22
22
27,28
28
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology. Inc.
ADVANCE
z
m
MIC:RON
I ~.
MT4LC16M4G3/H9
16 MEG x 4 DRAM
",""cecc,",
:e
•
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vee
AC CHARACTERISTICS
PARAMETER
=+3.3V ±0.3V)
-7
-6
-5
MAX
15
UNITS
tpc
20
25
30
ns
EDO-PAGE-MODE
READ-WRITE cycle time
tpRWC
71
75
85
ns
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
tRAC
tRAD
tRAH
tRAL
tRAS
tRASP
tRC
RAS pulse width
RAS pulse width (EDO PAGE MODE)
Random READ or WRITE cycle time
RAS to CAS" delay time
Read command hold time
(referenced to CAS)
tRCD
tRCH
Read command setup time
Refresh period
RAS precharge time
RAS to CAS" precharge time
Read command hold time
(referenced to RAS)
tRCS
tREF
tRP
RAS hold time
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
Write command hold time
(referenced to RAS)
tRSH
tRWC
tRWD
tRWL
WE command setup time
WE to outputs in High-Z
Write command pulse width
WE pulse width to disable outputs
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
twcs
tWHZ
twp
MT4LC16M4G3IH9
D22.pmS- Rev. 2195
tRPC
tRRH
'T
tINCH
tWCR
twpz
tWRH
tWRP
9
8
25
50
50
90
11
0
50
25
10,000
125,000
37
0
MIN
0
0
MIN
0
0
tOFF
tORD
EDO-PAGE-MODE
READ or WRITE cycle time
MAX
13
MAX
15
MIN
0
0
Output buffer turn-off delay
OE setup prior to RAS during
HIDDEN REFRESH cycle
SYM
12
10
30
60
60
110
14
0
60
30
10,000
125,000
45
12
10
35
70
70
130
14
0
70
35
10,000
125,000
50
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
0
0
40
0
0
50
0
0
ns
ms
ns
ns
ns
8
126
73
8
1
8
40
10
150
80
15
2
10
45
12
177
90
15
2
12
55
ns
ns
ns
ns
ns
ns
ns
64
64
50
0
8
1-54
13
10
10
10
10
50
0
0
10
7
7
8
50
64
15
12
12
10
10
ns
ns
ns
ns
ns
ns
NOTES
20,27
14
18
17
19
26
19
21
21
25
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
© 1995, Micron Technology. Inc.
ADVANCE
MICRON
1-·
MT4LC16M4G3/H9
16 MEG x 4 DRAM
"'e"""","
z
m
~
NOTES
1.
2.
3.
4.
All voltages referenced to Vss.
This parameter is sampled. Vee = +3.3V; f = 1 MHz.
Ice is dependent on cycle rates.
Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
S. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100~s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
8. AC characteristics assume tTof 2ns for -S and 2.5ns for
-6 and -7.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input Signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS and RAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates,
100pF and VOL = 0.8V and VOH = 2.0V.
14. Assumes that tRCD < IRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that tRCD
exceeds the value shown.
IS. Assumes that tRCD 2: tRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, output data
will be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS must
be pulsed HIGH for tcP.
17. Operation within the tRCD (MAX) limit ensures that
tRAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified tRCD (MAX) limit, then access time is
controlled exclusively by tCAe.
18. Operation within the tRAD (MAX) limit ensures that
tRAC (MIN) and tCAC (MIN) can be met. tRAD
(MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, then
access time is controlled exclusively by tAA.
MT4lC16M4G3/H9
D22.pm5 - Rev. 2/95
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL.
21. twcs, tRWD, tAWD and tCWD are not restrictive
operating parameters. twcs applies to EARLY WRITE
cycles. If twcs > twcs MIN, the cycle is an EARLY
WRITE cycle and the data output will remain an open
circuit throughout the entire cycle. tRWD, tAWD and
tCWD define READ-MODIFY-WRITE cycles. Meeting
these limits allows for reading and disabling output
data and then applying input data. OE held HIGH and
WE taken LOW after CAS goes LOW results in a LATE
WRITE (OE-controlled) cycle. twcs, tRWD, tCWD and
tAWD are not applicable in a LATE WRITE cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and
OE = HIGH.
2S. twTS and tWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of tWRP and tWRH in the
CBR REFRESH cycle.
26. RAS-ONLY REFRESH requires that all 8,192 rows of
the MT4LC16M4G3, or all 4,096 rows of the
MT4LC16M4H9, be refreshed at least once every
64ms. CBR REFRESH, for either device, requires that
at least 4,096 cycles be completed every 64ms.
27. The DQs open during READ cycles once tOD or toFF
occur. If CAS stays LOW while OE is brought HIGH,
the DQs will open. If OE is brought back LOW (CAS
still LOW), the DQs will provide the previously read
data.
28. LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. If OE is
taken back LOW while CAS remains LOW, the DQs
will remain open.
29. Column-address changed once each cycle.
1-55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
m
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C
lJ
»
3:
ADVANCE
z
m
MICRON
1-·
MT4LC16M4G3/H9
16 MEG x 4 DRAM
",",CW,,,,,
;e
•
READ CYCLE
m
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RAS
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CAS
Vil -
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V,H
Vil
WE
V,H
Vil
ROW
NOTE 2
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;/
EARLY WRITE CYCLE
RC
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ICSH
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ROW
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ROW
tCWL
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~:g~ _
~
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twp
VALID DATA
~777i'77T,~'777:.77TT77.
77777777777777.77n77T,
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and twRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
2. tOFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MT4L~16M4G3IH9
D22.pmS - Rev. 2/95
1-56
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT 4LC16M4G3/H9
16 MEG x 4 DRAM
"'""00"""
z
m
~
•
READ WR1TE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
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NOTE:
~UNDEFINED
1. tpc ill for LATl= WRITE cycles only.
2. Although WE is a "don't care" atRAS time during an access cycle (READ or WRITE). the system designer
should implement WE HIGH for twRP and twRH. This design implementation will. facilitate compatibility with
future EDO DRAMs.
1-58
Micron Technology, Inc., reserves the right to change produas or specifications without notice.
@1995.MIcronTechnology,lnc.
ADVANCE
MICRON
1-·
MT4LC16M4G3/H9
16MEGx4DRAM
,,,""oeoc,,,
z
m
--------------------------~
•
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODI FY-WRITE)
m
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tpc
tpc
~
'RCD
tcp
~
IRSH
teAs
tcp
tcp
l>
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tRAL
II
I~
ADDR
tACH
~!I~
COLUMN (A)
COLUMN (N)
tAAl
1~
IWHZ_
VALID DATA (A)
OPEN
tOE
OE
~:t= W/$///;@//$$///;/';@/mRAS-ONL Y REFRESH CYCLE
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m
UNDEFINED
NOTE:
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and 'WRH. This design implementation will facilitate compatibility with
.
future EDO DRAMs.
MT4LC16M4G3IH9
D22.prn5 - Rev. 2/95
1-59
C
:rJ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
z
m
MIC:RON
1-·
MT 4LC16M4G3/H9
16 MEG x 4 DRAM
"C"'"''""'''
~-------------------------
•
CBR REFRESH CYCLE
(Addresses and OE = DON'T CARE)
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~
MT4lCtSM4G3/H9
D22.pm5- Rev. 2/95
1-60
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII::::RCN
MT4LC16M4G3/H9
16 MEG x 4 DRAM
"c~"'oc"c
1-·
z
m
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•
READ CYCLE
(with WE-controlled disable)
RAS
V,H
V,L _
tCRP
CAS
VIH VIL -
.~:
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tCSH
teAs
!
I
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tASR
ADDR
WE
I
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DO ~gt ---------OPEN-------~~t~~~=t
~
DON'T CARE
~
UNDEFINED
I
I
I
I
I NOTE:
I
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and 'WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC16M4G3JH9
D22.pmS - Rev. 2195
1-61
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
z
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MICRON
1-·
MT4LC16M4G3/H9
16 MEG x 4 DRAM
","",cO'",
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MT4LC16M4G31H9
D22.pm5- Rev. 2/95
1-62
Micron Technology, !nc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
DRAM
x 8 DRAM
2 MEG
3.3V, EDOPAGE MODE,
OPTIONAL SELF REFRESH
FEATURES
28-Pin SOJ
(DA-5)
Vee [ 1
DOl [ 2
D02 [3
D03 [ 4
D04 [ 5
WE [ 6
7
8
9
10
11
12
13
Vee [ 14
RAS [
NC [
Al0 [
AO [
Al [
A2 [
A3 [
MARKING
OPTIONS
• Timing
60ns access
70ns access
-6
-7
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
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PIN ASSIGNMENT (Top View)
• Industry-standard x8 pinout, timing, functions and
packages
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• Low power, 0.3mW standby; 150mW active, typical
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN and SELF
• 2,048-cycle refresh (11 row-, 10 column-addresses)
• Optional SELF REFRESH, Extended Refresh rate (4x)
• Extended Data-Out (EDO) PAGE access cycle
• 5V tolerant I/Os (5.5V maximumVIH level)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-Pin TSOP
(DB-3 )
Vss
Vee
Vss
DOB
D07
D06
D05
CAS
DOl
D02
D03
DQ4
DOB
D07
DOS
D05
CAS
OE
RAS
OE
A9
NC
Al0
AO
Al
A9
WE
A2
AB
A7
A6
A5
A4
A3
A4
Vss
Vee
Vss
AB
A7
A6
A5
OJ
TG
• Refresh Rate
Standard 32ms period
SELF REFRESH and 128ms periods
None
S
• Part Number Example: MT4LC2M8E7DJ-7 S
If WE goes LOW after CAS goes LOW, data-out (Q) is
activated and retains the selected cell data as long as OE
remains LOW and RAS or CAS remains LOW (regardless of
WE). This late WE pulse results in a READ WRITE cycle.
If WE toggles LOW after CAS goes )Jack HIGH, the output
pins will open (High- Z) until the next CAS cycle, regardless
ofOE.
The eight data inputs and the eight data outputs are
routed through eight pins using common I/O, and pin
direction is controlled by WE and OE.
KEY TIMING PARAMETERS
I
SPEED
tRC
tRAC
tpc
tAA
tCAC
tCAS
·6
·7
110ns
130ns
60ns
70ns
25ns
30ns
30ns
3.5ns
15ns
20ns
10ns
12ns
GENERAL DESCRIPTION
I
I
The MT4LC2M8E7(S) is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x8 con~
figuration. The MT4LC2M8E7(S) RAS is used to latch the
first 11 bits and CAS the latter 10 bits (AI0 is ignored during
CAS falling edge.) READ and WRITE cycles are selected
with the WE input. A logic HIGH on WE dictates READ
mode while a logic LOW on WE dictates WRITE mode.
During a WRITE cycle, data-in (D) is latched by the falling
edge of WE or CAS, whichever occurs last. If WE goes LOW
prior to CAS going LOW, the output pins remain open
(High-Z) until the next CAS cycle, regardless of OE.
MT4LC2M8E7(S)
W09.pmS - Rs,V. 2/95
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-addressdefined page boundary. The PAGE cycle is always initiated
with a row-address strobed-in by RAS followed by a column-address strobed-in by CAS. CAS may be toggled-in
by holding RAS LOW and strobing-in different columnaddresses, thus executing faster memory cycles. Returning
RAS HIGHterminates the PAGE MODE of operation.
1-63
•
Micron Technology, Inc., reserves the right 10 change products or specifications without notice,©1995, Micron TechnOlogy, Inc,
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PRELIMINARY
MIC:RON
1-·
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MT4LC2M8E7(S)
2 MEG x 8 DRAM
HC~~O"''''
EDO PAGE MODE
The MT4LC2M8E7(S) provides EDOPAGE MODE, which
is an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
CAS returns HIGH. EDO provides for CAS precharge time
(tcP) to occur without the output data going invalid. This
elimination of CAS output control provides for pipeline
READs.
FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS. EDO-PAGE-MODE DRAMs operate similar to FASTPAGE-MODE DRAMs, except data will remain valid or
become valid after CAS goes HIGH during READs, provided RAS and OE are held LOW. If OE is pulsed while
RAS and CAS are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If OE is toggled or
pulsed after CAS goes HIGH while RAS remains LOW,
data will transition to and remain High-Z (refer to Figure 1).
If the DQ outputs are wire OR'd, OE must be used to
disable idle banks of DRAMs. Alternatively, pulsing WE to
the idle banks during CAS HIGH time will also High-Z the
outputs. Independent of OE control, the outputs will disable after toFF, which is referenced from the rising edge of
RAS or CAS, whichever occurs last.
refresh cycle (RAS ONLY, CBRor HIDDEN) so that all 2,048
combinations of RAS addresses are executed at least every
32ms, regardless of sequence. The CBR REFRESH cycle will
invoke the refresh counter for automatic RAS addressing.
An optional SELF REFRESH mode is also available on
the MT4LC2M8E7 S. The "5" version allows the user the
choice of a fully static low-power data retention mode or a
dynamic refresh mode at the extended refresh period of
128ms, four times longer than the standard 32ms
specification.
The optional SELF REFRESH feature is initiated by performing a CBR REFRESH cycle and holding RAS LOW for
the specified tRASS. Additionally, the "5" version allows
for an extended refresh rate of 62.5~s per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby or BATTERY
BACKUP mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum timeoftRPS (~tRC). This delay allows
for the completion of any internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all 2,048 rows must
be refreshed within 300~s prior to the resumption of normal
operation.
REFRESH
Preserve correct memory cell data by maintaining
power and executing a RAS cycle (READ, WRITE) or RAS
RAs ~:~=~~
____________________________________
The DOs go back to
Low-Z if tOES is met.
The DOs remain High-Z
until the next CAS cycle
jf 'OEHC is met.
The DOs remain High-Z
until the next CAS cycle
if to,EP is met.
~
DON'T CARE
~
UNDEFINED
Figure 1
OUTPUT ENABLE AND DISABLE
MT4LC2M8E7(S)
W09.pm5 - Rev. 2195
1-64
Micron Technology, Inc., reserves the right to change products or specifications without nolies.
©1995, Micron Technology, fnc.
PRELIMINARY
-
FUNCTIONAL BLOCK DIAGRAM
m
WE~--~~--------------------,
c
001
••
008
OE
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
RAS
2048 x 1024 X 8
MEMORY
ARRAY
0-------1
.---....0
Vee
+----0
Vss
TRUTH TABLE
ADDRESSES
FUNCTION
Standby
CAS
WE
OE
IR
IC
DQ1-DQ4
H
H~X
X
X
X
X
High-Z
Data-Out
READ
L
L
H
L
ROW
COL
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
READ WRITE
L
L
H~L
L~H
ROW
COL
Data-Out, Data-In
EDO-PAGE-MODE
1st Cycle
L
H~L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H~L
H
L
n/a
COL
Data-Out
EDO-PAGE-MODE
1st Cycle
L
H~L
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd Cycle
L
H~L
L
X
n/a
COL
Data-In
EDO-PAGE-MODE
1st Cycle
L
H~L
H~L
L~H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H~L
H~L
L~H
n/a
COL
Data-Out, Data-In
L
H
X
X
ROW
n/a
High-Z
RAS-ONLY REFRESH
I
DATA-IN/OUT
RAS
HIDDEN
READ
L~H~L
L
H
L
ROW
COL
Data-Out
REFRESH
WRITE
L~H~L
L
L
X
ROW
COL
Data-In
CBR REFRESH
H~L
L
H
X
X
X
High-Z
SELF REFRESH
H~L
L
H
X
X
X
High-Z
I
I
i
MT4LC2M8E7(S)
W09.pmS- Rev. 2195
1-65
Micron Technology, Inc., reserves the right to change products or specifIcations without notice.
©1995, Micron Technology, Inc.
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PRELIMINARY
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*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RA TINGS*
Voltage on Vee pin Relative to Vss ................. -IV to +4.6V
Voltage on Inputs or I/O pins
Relative to Vss .................................................... -IV to +S.SV
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) ................... -SsoC to +ISO°C
Power Dissipation ............................................................. lW
Short Circuit Output Current ..................................... SOmA
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:s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vee
=+3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs (including NC pins)
VIH
2.0
5.5
V
VIL
-1.0
0.8
V
II
-2
2
f.lA
loz
-10
10
f.lA
VOH
2.4
Input Low (Logic 0) Voltage, all inputs (including NC pins)
INPUT LEAKAGE CURRENT
Any input OV :s; VIN :s; 5.5V
(All other pins not under test = OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV:S; VOUT :s; 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
MT4lC2M8E7(S)
W09.pm5 - Rev. 2f95
VOL
1-66
NOTES
V
0.4
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
:Notes: 1, 6, 7) (Vcc
=+3.3V ±0.3V)
MAX
SYMBOL
-6
-7
UNITS
Icc1
2
2
mA
Icc2
Icc2
(S only)
500
150
500
150
f.lA
I1A
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC =IRC [MIN])
Icc3
130
120
mA
3,4,12
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC =IpC [MIN])
Icc4
120
110
mA
3,4,12
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS =VIH: IRC =IRC [MIN])
Icc5
130
120
mA
3, 12
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS,Address Cycling: IRC
Icc6
130
120
mA
3, 5
Icc7
(S only)
300
300
I1A
3, 5
Icc8
(S only)
300
300
f.lA
5
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS =CAS =VIH)
STANDBY CURRENT: (CMOS)
(RAS =CAS =Other Inputs =Vcc -0.2V)
i
=IRC [MIN])
REFRESH CURRENT: Extended (S version only)
Average power supp'ly current, CAS =0.2V or CBR cycling;
RAS =IRAS(MIN); WE =Vcc -0.2V; AO-A10, OE and
DIN =Vcc - 0.2V or 0.2V (DIN may be left open); IRC = 62.511S
REFRESH CURRENT: SELF (S version only)
Average power supply current, CBR cycling with RAS :2: IRASS(MIN)
,
and CAS held LOW; WE = Vcc -0.2V; AO-A 10,
I OE and DIN = Vcc -0.2V or 0.2V (DIN may be left open)
I
NOTES
T4LC2M8E7(S)
W09,pr'llS-Rev.2J95
I
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1-67
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology, Inc.
»
S
PRELIMINARY
MICRON
1-·
•
MT4LC2M8E7(S)
2 MEG X 8 DRAM
',,"",coon,
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
5
7
7
pF
2
pF
2
pF
2
MAX
UNITS
NOTES
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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AND RECOMMENDED AC OPERATING CONDITIONS
s ELECTRICAL CHARACTERISTICS
=
Inpot Capacitance: Address pins
CI1
Input Capacitance: RAS, CAS, WE, OE
CI2
Input/Output Capacitance: DO
CIO
(Notes: 6, 7, 8, 9, 10, 11, 12) (Vee
+3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address set-up to CAS precharge during WRITE
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulse width
CAS LOW to "don't care" during SELF REFRESH cycle
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
Data output hold after next CAS lOW
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to F'lAS")
Data-in setup time
Output disable
Output Enable
OE hold time from WE during READ-MODIFY-WRITE cycle
OE HIGH hold from CAS HIGH
MT4LC2M8E7{S)
W09.pm5 -"Rev. 2195
-6
SYM
MIN
tAA
tACH
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHD
ICHR
IClZ
ICOH
ICp
ICPA
ICRP
ICSH
ICSR
ICWD
ICWl
IDH
IDHR
IDS
10D
10E
tOEH
10EHC
1-68
-7
MAX
MIN
30
15
45
0
0
55
15
55
0
0
65
15
10
10
15
10
0
5
10
10,000
20
12
12
15
12
0
5
10
35
5
50
5
35
15
10
45
0
0
12
10
15
15
10,000
40
5
55
5
40
15
12
55
0
0
12
10
15
15
I
I
20
14
25
5
15
5
20
21
21
22
Micron Technology, Inc., reserves the right to change products or specifications without notice'
©1995, Micron Technology, Inc
I
PRELIMINARY
UII=I=ICN
1-·
MT4LC2M8E7(S)
2 MEG x 8 DRAM
'''""'co"' '"'
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12) (Vee
=+3.3V ±0.3V)
PARAMETER
OE HIGH pulse width
SYM
tOEP
MIN
10
OE LOW to CAS HIGH setup time
tOES
5
Output buffer turn-off delay
OE setup prior to RAS during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS
3
0
25
tpRWC
75
RAS to column-address delay time
tRAC
tRAD
12
Row-address hold time
tRAH
10
Column-address to RAS lead time
tRAL
30
RAS pulse width
tRAS
60
tRASP
tRASS
tRC
60
100
RAS pulse width (EDO PAGE MODE)
RAS pulse width during SELF REFRESH cycle
Random READ or WRITE cycle time
RAS to CAS delay time
tRCD
110
14
Read command hold time (referenced to CAS)
tRCH
0
Read command setup time
tRCS
tREF
0
Refresh period (2,048 cycles) S version
Refresh period (2,048 cycles)
MIN
MAX
10
3
15
70
ns
ns
13
35
ns
17
10
10,000
125,000
35
70
70
100
ns
ns
10,000
125,000
ns
ns
25
50
/-ls
ns
ns
ns
18
130
45
14
0
0
16
ns
128
128
32
ms
ms
RAS precharge time
40
50
ns
RAS to CAS precharge time
tRPC
0
RAS precharge time during SELF REFRESH cycle
tRPS
110
0
130
ns
ns
25
Read command hold time (referenced to RAS)
RAS hold time
tRRH
tRSH
0
10
ns
18
READ WRITE cycle time
RAS to WE delay time
tRWC
tRWD
150
0
12
177
Write command to RAS lead time
tRWL
80
15
32
ns
ns
90
ns
15
ns
IT
2
Write command hold time
Write command hold time (referenced to RAS)
tWCH
tWCR
10
45
WE command setup time
twcs
0
Output disable delay from WE
Write command pulse width
tvvHZ
tvvp
twpz
0
10
10
12
ns
ns
tWRH
10
10
10
10
ns
ns
WE pulse to disable at CAS HIGH
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
Mi4LC2M8E7(S)
W09.pmS - Rev. 2195
tvvRP
1-69
50
2
12
50
55
0
12
15
20
ns
ns
ns
ns
0
13
o
o
o
::0
ns
85
12
ns
ns
0
30
60
30
NOTES
ns
ns
5
15
UNITS
tREF
tRP
Transition time (rise or fall)
I
tOFF
tORD
tpc
MAX
•
m
-7
-6
AC CHARACTERISTICS
20
ns
24
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
»
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PRELIMINARY
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~~~:~tages
referenced to Vss.
2. This parameter is sampled. Vee = +3.3V; f = 1 MHz.
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100~s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume ty = 2.5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. Column address changed once each cycle.
12. Measured with a load equivalent to two TTL gates,
100pF and VOL = 0.8V and VOH = 2.0V.
13. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
14. Assumes that IRCD <': IRCD (MAX).
15. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous. cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
16. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe, provided lRAD is not
exceeded.
17. Operation within the lRAD (MAX) limit ensures that
!RAc (MIN) and ICAC (MIN) can be met. IRAD
(MAX) is specified as a reference point only; if IRAD
is greater than the specified IRAD (MAX) limit, then
access time is controlled exclusively by IAA, provided
IRCD is not exceeded.
MT4LC2M8E7(S)
W09.pm5 - Rev. 2195
18. Either IRCH or IRRH must be satisfied for a READ
cycle.
19. 10FF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL. It is referenced from the
rising edge of RAS or CAS, whichever occurs last.
20. twcs, IRWD, IAWD and ICWD are not restrictive
operating parameters. twcs applies to EARLY
WRITE cycles. IRWD, IAWD and ICWD apply to
READ-MODIFY-WRITE cycles. If twcs <': twcs
(MIN), the cycle is an EARLY WRITE cycle and
the data output will remain an open circuit throughout the entire cycle. If twcs < IWCS (MIN) and
IRWD <': IRWD (MIN), IAWD <': IAWD (MIN) and
ICWD <': ICWD (MIN), the cycle is a READ-MODIFYWRITE and the data output will contain data read
from the selected cell. If neither of the above
conditions is met, the state of data-out is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. twcs, IRWD, ICWD and IAWD are not
applicable in a LATE WRITE cycle.
21. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
22. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permissible and should not be attempted. Additionally, WE
must be pulsed during CAS HIGH time in order to
palce I/O buffers in High-Z.
23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and OE = HIGH.
24. twTS and IWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of IWRP and IWRH in the
CBR REFRESH cycle.
25. Refresh must be completed within the time of three
external refresh rate periods prior to active use of the
DRAM (provided distributed CBR REFRESH is used
when in the active mode). Alternatively, a complete
set of row refreshes must be executed when exiting
SELF REFRESH prior to active use of the DRAM if
anything other than distributed CBR REFRESH is
used in the active mode.
1-70
Micron Technology, Inc., reservaslhe nghtto change products orspeciflcalions without notice.
©Hl95, Micron Technology, Inc.
PRELIMINARY
READ CYCLE
tRe
RAS
=----.1
tCAS
I
ADDR
WE
V,H
VIL
WJ7PJ
ROW
I
-I
tRAL
ROW
)
COLUMN
~
tRCS
:1///#////"NOTE'I. VLl!Uff
C
lJ
I
i~l~
tWRH~1
I'" tWRP
~I
Y
~
tAR
1~~1
_
'1
'RSH
tRCD
tRAD
V,H
V IL
c
o
\
teRP
V,H
V IL
m
I
-tCSH
CAS
-
tRP
'RAS
V ,H
VIL
I.
II
'M
tRAG
NOTE 2
I~
~
'CAG
~g~ =:---------OPEN-------~~r~--;;VA~LI~D;;-,:D~AT~A.J_r--OPEN--I. tOE
I. too
DE ~:t =7Til!!J'TT.0'!J=1I!JTT711j;7771;;TT7m7Ti1l!JrTr.1I!J=1I!JTT70'!J777~TT7W!J7Ti1(!J'TT.0'j;""Wj;TT7
W777
11!J777J02i
/##;//;//#M1//////;/#////#,0
DO
EARLY WRITE CYCLE
'RC
'RP
'RAS
\
teSH
1
j~:
tRCO
'AR
'RAD
I~~I
ADDR
~:r
WAt
~
ROW
ff:::
I
I~I
=
~
I
tAAL
f
1
I~I
tACH
~
DO
~lg~
I!
'WRH
I
I
I
ROW
-I
'eWL
I
I
~A2
COLUMN
'RWl
'weR
~! !~
'WP
I
1
~_'DS I-~!<--J~
=
VALID DATA
-, "
lilll DON'T CARE
~
I
NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and WRH. This design implementation will facilitate compatibility. with
future EDO DRAMs.
.
i tOFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MT4LC2MSE7(S)
W09.pm5,",," Rev. 2195
Micron Technology, Inc., reserves the right to change products or specifications wrthout notice.
©1995, Micron Technology, Inc.
»
s:
PRELIMINARY
•
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
m
c
o
leSH
C
JJ
»
s:
ADDR
I
tRAG •
ICAC
I
teLl---
DQ
i5E
-
~:g~ ----------OPEN---4~~~~~~-.-'--"
OPEN---
~:t 4$###/;I$##$#$#/;I/;I/;I#$/;I#/;Id~
EDO-PAGE-MODE READ CYCLE
RASP
fZ1 DON'T CARE
~
NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and twRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC2M8E7(S)
W09.pm5 - Rev. 2195
1-72
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
•
EDO-PAGE-MODE EARLY-WRITE CYCLE
t
RASP
-
tpe
tep
leSH
I'"
tRCD
teRP
=~
ADDR
~It
~i
ROW
:{Wi
~I.~
tRAD
t RAH _)
W//M
ll~
leAS
I
'RAL
1_
'Ase
I~II 'eAH~1
'leAH_)
COLUMN
COLUMN
I tewL
~II~
twp
m
C
o
I~I
~
If
COLUMN
I
'RSH
If
I I~
tAR
1_ 'ASR
tCAS
P
r==L
--
I
C
::D
»
s:
ROW
~~
I
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ~MODIFY-WRITE cycles)
tRP
IpC
leSH
1_
=~
1_
ADDR
~:t
::j'/;0t
\cAS
'RCo
teRP
tAR
'RAD
tRAH~1
tASR
ROW
~'i
I I~
fl I
, 1_ tWRP
=w#NOTEZI
t WRH"
1
YIiII
tAA
NOTE:
'!
"
I
~lgt
I
'RWD
t::d
IAWD
_I
~Il'
Ii
..L
'CWl--IWp ___
'AWD
I~
I
!OH---
\cPA
leAH
Ii
..L
I
I
I
~I
IAWD
--
--
ROW
II-t RwL
-- 'CWl
-twp
l~
~II~
'DH---
F=L
t=l
'CAS
COLUMN
~JI~
I
I
leAH
COLUMN
I~
tRAG
00
I
'RSH
~
f--
~
COLUMN
I
ICAS
tRAL
~
WI;;)
!PRWC NOTE 1
~
f--
'CPA
-
--.tOH
OPEN-
::::'-------OPEN
~
DON'T CARE
~
UNDEFINED
1. tpc is for LATE WRITE cycles only.
2. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and twRH. This.designimplementation will facilitate compatibility with
future EDO DRAMs.
MT4LC2M8E7(S)
W09.pm5 - Rev. 2/95
1-73
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC2M8E7(S)
2 MEG x 8 DRAM
,"""",00'",
•
EDO-PAGE-MODE READ-EARL Y-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
m
I RASP
C
o
tCSH
tpc
C
:0
tpc
'CRP
»
s:
ADDR
WE
DQ
~[~_
VIHVIL-
~lg~-----OPEN ---~-t~V~ALI~DD~ATA~(A~)~"-----"='--"
tOE
OE
~:~= all#11//#////#$##$1#;01-
RAS-ONL Y REFRESH CYCLE
RAS
CAS
ADDR
NOTE:
V,H
VJL -
d'
tCAP
~:t ~
V
V1L I
_ H-_
IASA
tRC
.~
,II.
ROW
tAP
tRAS
tRAH
~
'k/~$#/####//$~$$tf/;1#~tk(
:~
II
ROW
~
DON'TCARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for 'WRP and 'WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC2M8E7(S)
W09.pmS- Rev. 2/95
1-74
Micron Technology, Inc., r9S9JV9S the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
•
CBR REFRESH CYCLE
(Addresses and OE = DON'T CARE)
.
----.i
tRP
..
tRAS
.. J
1
tRPC
:J:;:~~
..
tCHR
2
II
DO
tWRP
II
tRP
III
..
~~~
tRAS
!CHR
m
c
o
c
,I
:c
1
OPEN----;-,II.------------
tWRH
tWRP
II
tWRH
~:~ --W$M/!j-:T~W;/m;/m;/$;/mJ- --'W$§/!!;!;//$;/U;/;//;/;2
WE
SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
NOTE 2
tRP
tRASS
(( ' ,
tRPS
::;A~ ~~~$ff#!Iff$ff$ff!ff;rtr~~
DO
VOH -
WE
NOTE:
.
I
()-
II
OPEN
II
II
~:t 4#/#//;J--:TE-:-~f;@///;I$/;IM'/;I#/#//;I$###//J- -~$j/M/M/4
VOL
tWRP
IWRH
)
tWRP
IWRH
fZ;:l
DON'T CARE
~
UNDEFINED
1. IWRP and twRH are for system design reference only. The WE signal is actually a "don't care" at RAS time
during aCBR REFRESH. However, WE should be held HIGH at RAS time during a CBR REFRESH to
ensure compatibility with other DRAMs that require WE HIGHat RAS time during a CBR REFRESH.
2. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
3. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT4LC2M8E7(S)
W09.pm5 - Rev. 2195
1-75
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
»
s
PRELIMINARY
UU:::I=ICN
MT4LC2M8E7(S)
2 MEG x 8 DRAM
m~",co""
1-·
•
READ CYCLE
(with WE-controlled disable)
m
~
C
o
'eSH
,11-:------'R-CD-----"e"'As"-----1
'eRP
C
'ep
.'
r+------J
::D
»
s:
ADDR
WE
V IH
_TTT77d,----------'-'------,L rTTTT;'A r--'---'------,[.'TT777TTrl-n7"T71'77T" Jr----'-'------
V,L
-liLI.:LJ,'---------;c-~,.-;cc:c_:_----' "-'u..LLul'--;--_,------,----_~'CLLLL1.LI.CLfLLLLLLLLJ~l'--_,erOL-UM-N--
V,H __7TTTTT77"T71.r----;.----bTTTJ77Tk--:-------;--------'-------J
v IL
-LLLLCLLLLLLJ
DO ~gt -'------------OPEN-------~~r____;;;:;;;-;;;;:;:;;:-__j
HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
(READ)
~:
:--'
~
}---
(REFRESH)
RAS
tRCD
'I'
'AR
.m.
'RAH
1t-II IR:LI
:tAsc.I!~
tRSH
'F=r
RAS
tCHR
I
-,I
I2ZI DON'T CARE
~
NOTE:
UNDEFINED
1. AlthOugh WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC2MSE7(S)
W09.pm5 -Rev. 2195
1-76
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©199S, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LC8M8P4/C2
8 MEG x 8 DRAM
"'""oco"""
8 MEG x 8 DRAM
DRAM
PIN ASSIGNMENT (Top View)
• Timing
SOns access
60ns access
70ns access
Vss
D08
DQ?
D06
DOS
VSS
CAS
OE
NC
RAS
NC
AO
A1
A2
A3
-5
-6
-7
• Packages
Plastic SOJ (500 mil)
Plastic TSOP (500 mil)
Vee
D01
D02
D03
D04
NC
Vee
WE
DW
TW
A12/NC
A11
A10
A9
A8
A?
A6
A4
AS
• Part Number Example: MT4LC8M8P4DW-7
Vss
Vee
KEY TIMING PARAMETERS
I
SPEED
-5
-6
-?
tRC
90ns
110ns
130ns
tRAC
50ns
60ns
?Ons
tpc
20ns
25ns
30ns
tAA
25ns
30ns
35ns
tCAC
13ns
15ns
20ns
tCAS
8ns
10ns
12ns
34-Pin TSOP*
GENERAL DESCRIPTION
The MT4LC8M8P4 and MT4LC8M8C2 are high-s Peed
CMOS dynamic random access memory devices containing
67,108,864 bits, and designed to operate from 3.0V to 3.6V.
The MT4LC8M8P4 and MT4LC8M8C2 are functionally
organized as 8,388,608 locations containing 8 bits each. The
I 8,388,608 memory locations are arranged in 8,192 rows by
I 1,024 columns for the MT4LC8M8P4 or 4,096 rows by 2,048
i columns for the MT4LC8M8C2. During READ or WRITE
I cycles, each location is uniquely addressed via the address
I bits. First, the row address is latched by the RAS signal, then
I the column address by CAS . Both devices provide EDO
I PAGE MODE operation, allowing for fast successive data
I operations (READ, WRITE or READ-MODIFY-WRITE)
: within a given row.
The MT4LC8M8P4 and MT4LC8M8C2 must be refreshed
I periodically in order to retain stored data.
,I
MT4LC8M8P4IC2
D20.pmS - Rev. 2/95
Vee
Vss
D01
D02
D03
D04
NC
D08
DO?
D06
DOS
Vee
WE
RAS
NC
AO
A1
A2
A3
A4
AS
Vee
Vss
CAS
OE
NC
A12/NC
A11
A10
A9
A8
A?
A6
Vss
'Consult factory for dimensions and availability.
1-77
c
::c
»
s:
34-Pin SOJ
(OA-6)
MARKING
•
c
o
FEATURES
OPTIONS
:e
m
3.3V, EDO PAGE MODE
• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions and
packages
• 13 row-addresses, 10 column-addresses (P4) or
12 row-addresses, 11 column-addresses (C2)
• High-performance CMOS silicon-gate process
• All inputs and outputs are LVTTL-compatible
• Extended Data-Out (EDO) PAGE MODE access
• 4,096-cycle CAS-BEFORE-RAS (CBR) REFRESH
distributed across 64ms
z
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
z
m
=e
•
FUNCTIONAL BLOCK DIAGRAM
MT4LC8M8P4 (13 row-addresses)
m
c
WE
0
CASO~~r---------------------j===~~~~____l-______~
o
D01DOB
c
:c
»
L-----------------------1I11~----~
OE
s:
ADA12
8192x8
~
5a:
~
8192x1024x8
MEMORY
ARRAY
Vee
Vss
FUNCTIONAL BLOCK DIAGRAM
MT4LC8M8C2 (12 row-addresses)
WE
0
CASo~--~------------------------~
D01D08
-------<> OE
ADAll
4096x8
~
~
~
RAS
4096 x 2048 x 8
MEMORY
ARRAY
Vee
Vss
MT4LC8M8P4/C2
D20.pm5- Rev. 2/95
1-78
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
z
m
~
FUNCTIONAL DESCRIPTION
The functional description for the MT4LC8M8P4 and
MT4LC8M8C2 is divided into the two areas described
below (DRAM access and DRAM refresh). Relevant timing
diagrams are included in this data sheet, following the
timing specification tables.
have OE LOW when CAS transitions HIGH. Then bringing
OE HIGH for a minimum of tOEP anytime during the
CAS HIGH period will disable the DQs; the DQs will
remain disabled (regardless of the state of OE after that
point) until CAS falls again (see Figure 1). During other
cycles, the outputs are disabled at tOFF time after RAS and
CAS are HIGH, or twHZ after WE transitions LOW. The
tOFF time is referenced from the rising edge of RAS or
CAS, whichever occurs last. WE can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 2.
EDO PAGE MODE operations are always initiated with
a row-address strobed-in by the RAS signal, followed by a
column-address strobed-in by CAS, just like for single locationaccesses. However, subsequent column locations within
the row may then be accessed at the page mode cycle time.
This is accomplished by cycling CAS while holding RAS
LOW, and entering new column addresses with each CAS
cycle. Returning RAS HIGH terminates the EOO PAGE
MODE operation.
DRAM ACCESS
Each location in the DRAM is uniquely addressable as
mentioned in the General Description. The data for each
location is accessed via the eight I/O pins (DQl-8). The
WE signal must be activated to execute a write operation,
otherwise a read operation will be performed. The OE
signal must be activated to enable the DQ output drivers for
a read access and can be deactivated to disable output data
if necessary.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the output buffers off (High-~ith the rising edge of CAS. If
CAS went HIGH, and OE was LOW (active), the output
buffers would be disabled. The MT4LC8M8P4 and
MT4LC8M8C2 offer an accelerated PAGE MODE cycle by
eliminating output disable from CAS HIGH. This option is
called EDO and it allows CAS precharge time (tcP) to occur
without the output data going invalid (see READ and EDOPAGE-MODE READ waveforms in the noted appendix).
EDO operates as any DRAM READ or FAST-PAGEMODE READ, except data will be held valid after CAS
goes HIGH, as long as RAS and OE are held LOW and WE
is held HIGH. OE can be brought LOW or HIGH while
CAS and RAS are LOW, and the DQs will transition between valid data and High-Z. Using OE, there are two
methods to disable the outputs and keep them disabled
during the CAS HIGH time. The first method is to have
OE HIGH when CAS transitions HIGH and keep OE
HIGH for tOEHC thereafter. This will disable the DQs and
they will remain disabled (regardless of the state of OE after
that point) until CAS falls again. The second method is to
MT4lC8M8P4/C2
D20.pm5 - Rev. 2/95
DRAM REFRESH
The supply voltage must be maintained at the specified
levels, and the refresh requirements must be met in order to
retain stored data in the DRAM. The refresh requirements
are met by refreshing all 8,192 rows (P4) or all 4,096 rows
(C2) in the DRAM array at least once every 64ms. The
recommended procedure is to execute 4,096 CBR REFRESH
cycles, either uniformly spaced or grouped in bursts, every
64ms. The MT4LC8M8P4 internally refreshes two rows for
every CBR cycle, whereas the MT4LC8M8C2 refreshes one
row for every CBR cycle. So with either device, executing
4,096 CBR cycles covers all rows. Alternatively, RASONLY REFRESH capability is inherently provided. However, with this method only one row is refreshed at a time,
so for the MT4LC8M8P4, 8,192 RAS-ONLY REFRESH
cycles must be executed every 64ms to cover all rows.
1-79
Micron Technology, Inc., reserves the right to change products or specifications Without notice:
©1995, Micron Technology, Inc.
m
c
o
C
:::D
»
S
ADVANCE
z
m
M
1-·
:e
•
liAS
II::I=ICN
;~
~:r:~,--
c
MT4LC8M8P4/C2
8 MEG x 8 DRAM
;
______________________________,-____-,--,-__~____
m
c
o
C
::D
l>
s::
DQ~:8t':-----
The DOs go back to
The DOs remain High-Z
until the next CAs cycle
ift()EP Is met.
The DOs remain High-Z
until the next CAS cycle
If tOEHC Is met.
Low-Z if toES Is met.
Figure 1
OE CONTROL OF DQs
~ ~l~:~,--___________________~_________~~____________________
CAS
ADDR
DQ
~:r-
/)\
f'
l' /
I
I
1
J.
/L
~~:~,-f(~-\U-MN-(A)~WI/I !/kl$l I !l/lI!l/ / J);(r- :C Dl:C U:'c-MN- :C(.)- -;·X'#II!$///$$I/,0(r-'CDl--.JuLMN-'-(C)'>WI#J71$/~
. . ~ VALIDDA.L. ~r------I~~~=-=V~AlIO~DAT~A(.)C~-=~
"~
~~-------OP.EN
lvoaj.
IWHZ.I
I
/
:~:~~========~+--' --+-1----+5--'-,.-!--r-7Z~._
twPZ_.
The DOs go to High-Z if WE falls, and if IWPZ is mel,
will remain High-Z until CAS goes LOW with
WE HIGH (Le., until a READ cyCle is initiated).
WE may be used to disable the DOs to prepare
for Input data in an EARLY WRITE cycle. The DOs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initialed).
I2Zl DON'T CARE
~
UNDEFINED
Figure 2
WE CONTROL OF DQs
MT4LC8MSP4IC2
D20.pmS-Rev.2195
1-80
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995.MlcronTechnology.lnc
ADVANCE
MICRON
1-·
MT4LC8M8P4/C2
8MEGx8DRAM
,~,~,
zm
--~--------------------------------~~
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under"Absohlte Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and function,!l operation of the
device at these or any other conditions ,above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Voltage on Vee Relative to Vss ..................... -1.0V to +4.6V
Voltage on Inputs or I/O Pins
Relative to Vss ...........................•.................•... -1.0V to +S.5V
Operating Temperature, TA (ambiep.t) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SsoC to +1S0°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... SOmA
•
m
C
o
C
::D
:J>
s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +3.3V ±0.3V)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
PARAMETER/CONDITION
Vcc
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5
V
Input Low (Logic 0) Voltage, all Inputs
VIL
-1.0
O.B
V
-2
2
~
loz
-10
10
'VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV,:::; VIN :::; 5.5V
(All other pins not under test = OV)
II
.;
OUTPUT LEAKAGE CURRENT (0 is disabled; OV :;; VOUT :;; 5.5V)
OUTPUT lEVELS
Output High Voltage (lOUT = -2rnA)
Output Low Voltage (lOUT =2rnA)
VOL
'.
. PAIlAMETfR/CONDITION
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
..
VERSION
..... SYMBOL
MT4LCBMBP4
MT4LCBM8C2 ;
ICCl
Icel
0.4
.
-5
1
1
j.iA
.V
MAX
-6
1
. 1
V
UNITS. NOTES
~7
1
rnA
1
'.
';'
STANDBY CURRENT: (CMOS)
(RAS = CAS ~ Vec -0.2V, POs rnay Qe .Ieft open,
Other inputs: VI!'l~ Vec ..o.2V orVIN :::;0.2,,) .
MT4LCBMBP4
MT4LCBM8C2
OPERATING CURRENT: RandornREAPIWRITE
Average power supply current
(RAS, CAS, Adc;lresl:! Cycling: tRC = tRC [MIN])
MT4LCBMBP4
MT4LCBM8C2
ICC3
.lcc3
1-35
175
125
165
115
155
rnA
OPERATING CIJRRENT: EDO PAGE MODE
Average power supply current
."
(RAS = VIL, CAS, Address Gycling: tpc =tpc [MIN])
MT4LC8M8P4
MT4LCBM8C2
lCC4
ICC4
155
155
125
105
125 . 105
rnA
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRc = tRC [MIN])
MT4LC8M8P4
MT4LC8M8C2
1CC5
Ices
135
175
125
165
115
155
rnA
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIN])
MT4LC8M8P4
MT4LC8M8C2
Icc6
Icc6
145
175
135
165
125
155
rnA
MT4LCSME!p4lG2
D20.proS- Rev. zt95
NQTES
.IC.C2
Icc2
500
500
500
. 500
500.
500
~.
"
,
-=
1-81
"3,-4..
29
3,.4;
2,9
3,26
3,5
Micron Technology, Inc., rEiselVea the right to change prod~ or spacificationa without notice.
@1995,MlcronTeehnology,lnc.
ADVANCE
z
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:s
•
m
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C
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s:
MIC:RON
1-·
MT4LC8M8P4/C2
8MEGx8DRAM
,'"
CAPACITANCE
,
: PARAMETER
SYMBOL
MAX
5
UNITS
NOTES
CI1
pF
2
Input Capacitance: RAl:l; CAS, WE, OE
CI2
7
pF
2
InpuVOutput Capacitance: DO
Cia
9
pF
2
Input Capacitance: Address pins
"
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vee = +3.3V ±0.3V)
-5
AC CHARACTERISTICS
PARAMETER
Acc~ss tim~
from
column-addr~ss
Column-addr~ss s~t-up to CAS"
going HIGH during WRITE
Column-addr~ss
hold tim~
-7
-6
SYM
'M
MIN
MAX
25
MIN
MAX
30
MIN
"ACH
15
15
15
ns
ns
IAR
40
45
55
ns
IASC
'ASR
'AWD
'CAC
'CAH
'CAS
'CHR
0
0
48
0
0
55
0
0
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns·
ns.
ns
os
ns
(ref~r~hc~d to RAS)
Column-addr~ss·s~tup tim~
Row-addr~ss s~iup
time
Column-addr~ss to WE d~lay tim~
Ac~ss iim~ from CAS"
Column-addr~sshold tim~
CAS puls~ width
CAS hold tim~ (CBR REFRESH)
. CAS to outPut in Low-Z
Data output hold aft~r CAS LOW
CAS pr~harg~ tim~
Acc~ss tim~ from CAS pr~charg~
CAS to RAS pr~liarg~ tim~
CAS'hc;>ld tim~
CAS setup time (CBR REFRESH)
CAS to WE d~lay tim~
Writ~ command to CAS" I~ad tim~
Data-in hold tim~
Data-in hold tim~ (rej~r~ncooto RAS)]
Data-in s~tup tim~
Output disabl~
Output Enabl~ tim~
OJ: hold tim~ from WE dl'Jring
READ-MODIFY-WRITEcycl~
OJ: HIGH hold tim~ from CAS' HIGH
OJ: HIGH puls~ width
. OJ: LOW to CAS HIGH s~tup tim~
MT4LCBM8P4I02
D20.pm5 - Rev. 2195
'eLZ
'COH
ICp
.'
-
'CPA
'CRP
'CSH
'CSA.
'CWD
'CWL
'DH
'DHR
'DS
'OD
tOE
'OEH
13
8
8
8
0
5
8
10,000
15
10
10
10
0
5
10
28
5
44
5
30
8
8
40
0
0
8
13
13
20
12
12
12
0
5
10
10,000
35
5
50
5
35
15
10
45
0
0
10.
MAX
35
10,000
40
5
55
5
40
15
12
55
0
0
15
15
.:
12
,
15
15
UNITS
NOTES
21
15
5
16
5
21 .
22 :
22
27,.28
28
.,
'OEHG
'OEP
'OES
7
7
4
1-82
10
10
5
10
10
5
ns
ns
ns
Micron Technology, Inc., reserves the right 10 change products or specifications witHout notice.
1l:I1995, MIcron Technology,lnc.
:
ADVANCE
z
=E
m
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vee = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
-6
-5
MIN
MAX
MIN
MAl(
MIN
MAX
UNITS
NOTES
tOFF
tORD
0
0
13
0
0
15
0
0
15
ns
ns
20,27
tpc
20
25
30
ns
EDO-PAGE-MODE
READ-WRITE cycle time
tpRWC
71
75
85
ns
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (EDO PAGE MODE)
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time
(referenced to CAS)
tRAC
tRAD
tRAH
tRAL
tRAS
tRASP
tRC
tRCD
tRCH
Read command setup time
Refresh period
RAS precharge time
RAS to CAS precharge time
Read command hold time
(referenced toRAS)
tRCS
tREF
tRP
Output buffer turn-off delay
OE setup prior to RAS during
HIDDEN REFRESH cycle
EDO-PAGE-MODE
READ or WRITE cycle time
tRPC
tRRH
9
8
25
50
50
90
11
0
10,000
125,000
45
0
12
10
35
70
70
130
14
0
70
35
10,000
125,000
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
0
0
40
0
0
50
0
0
8
126
73
8
1
8
40
10
150
80
15
2
10
45
12
177
90
15
2
12
55
ns
ns
ns
ns
ns
ns
ns
twcs
lWHZ
0
twp
7
7
8
8
MT4LC8M8P4!C2
D20.pm5 - Rev. 2/95
60
30
ns
ms
ns
ns
ns
WE command setup time
WE to outputs in High-Z
Write command pulse width
WE pulse widths to disable outputs
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
twpz
tWRH
tWRP
37
12
10
30
60
60
110
14
0
64
tRSH
tRWC
tRWD
tRWL
IT
10,000
125,000
0
RAS hold time
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
Write command hold time
(referenced to RAS)
twCH
twCR
50
25
50
64
0
10
1-83
50
64
10
10
10
10
50
0
15
13
12
12
10
10
•
m
-7
SYM
ns
ns
ns
ns
ns
ns
c
o
C
JJ
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14
18
17
19
26
19
21
21
25
25
Micron Technology. Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
S
ADVANCE
z
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•
m
c
o
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::D
l>
s:
~~Jr;~tages
referenced to Vss.
2. This parameter is sampled. Vee = +3.3V; f = 1 MHz.
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOf.l,s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
S. AC characteristics assume IT = 2ns for -5 and 2.5ns for
-6 and -7.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS and RAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates,
100pF and VOL = O.SV andVoH = 2.0V.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, iRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, output data
will be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS must
be pulsed HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
IS. Operation within the IRAD (MAX) limit ensures that
IRAC (MIN) and ICAC (MIN) can be met. IRAD
(MAX) is specified as a reference point only; if IRAD
is greater than the specified lRAD (MAX) limit, then
access time is controlled exclusively by IAA.
MT4LC8MBP4/C2
D20.pm5':" Rev, 2195
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL.
21 twcs, IRWD, IAWD and ICWD are not restrictive
operating parameters. twcs applies to EARLY WRITE
cycles. If twcs > twcs MIN, the cycle is an EARLY
WRITE cycle and the data output will remain an open
circuit throughout the entire cycle. IRWD, IAWD and
ICWD define READ-MODIFY-WRITE cycles. Meeting
these limits allows for reading and disabling output
data and then applying input data. OE held HIGH and
WE taken LOW after CAS goes LOW results in a LATE
WRITE (OE-controlled) cycle. IWCS, IRWD, ICWD and
IAWD are not applicable in a LATE WRITE cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and
OE=HIGH.
25. twTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of twRP and IWRH in the
CBR REFRESH cycle.
26. RAS-ONLY REFRESH requires that allS,192 rows of
the MT4LCSMSP4, or all 4,096 rows of the
MT4LCSMSC2, be refreshed at least once every 64ms.
CBR REFRESH, for either device, requires that at least
4,096 cycles be completed every 64ms.
27. The DQs open during READ cycles once IOD or IOFF
occur. If CAS stays LOW while OE is brought HIGH,
the DQs will open. If OE is brought back LOW (CAS
still LOW), the DQs will provide the previously read
data.
2S. LATE WRITE and READ-MODIFY-WRITE cycles
must have both IOD and IOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. If OE is
taken back LOW while CAS remains LOW, the DQs
will remain open.
29. Column-address changed once each cycle.
1-84
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc,
ADVANCE
MICRON
1-·
,"
MT 4LC8M8P4/C2
8 MEG x 8 DRAM
,
READ CYCLE
,"p
'cSH
V,H 1T7=J~.""...,.4J:~~-{ m"""'rd:...---'-.........i--if777Tn7Tn"Ti-n'777;'77T,,J,.n
AOOR
DO
VH..
r,...-------
-.4l!~1~~::cT1"i::::::,...---J'U..l.LLI.;u}-c:.,-::--T=;'-c-;-_'Y.LlLLLlLLLLtfLLLf!:LlL.l'fLU'---._ _
RO_W_ _
~: =:_ _~~_~_OPEN _ _ _ _ _--j~~~~~~-_OPEN
__-
EARLY WRITE CYCLE
ADDR
~:t:
COLUMN
.'
I
:
I
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I
::
~ ~:_:'I;;~(1n
'r-~
... '
I-"'~i i :~:R
DQ~:ge~.·.
OE
NOTE:
':1
VALiDD!>A
.
_
~:r
~
DON'T CARE
~
UNDEFINED
1. Although WE i$ a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for~WRP and 'WRH. Tbis.design implementation will facilitate compatibility with,.
future EDO DRAMs: .
. "
.
2. tOFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MT4LC8M8P4lC2
D20~-Rev.~ <
h85
Micron Technology, Inc., reserves the right to change products or specifications Wiih()tJtnotlce;
C1995, Micron Technology, Inc.
ADVANCE
z
m
MII:::F=lCN
1-·
MT 4LC8M8P4/C2
8MEGx8DRAM
,
-
==
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
m
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s:
EDO-PAGE-MODE READ CYCLE
RAS
-j
'RASP
,----=",-------EFl.'cp'RP.
~:r: .~ '-:--.;-CS::-H--.R-CD---------;.PC=---------,~~::::----k~
"----1
CAs
II
'~I.
V,H v"
_
ADDR
NOTE:
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC8MBP4/C2
D20.pmS-Rev.2J95
1-86
Micron Tactinology. Inc., reserves the right to change products or specifications without notice.
@1995, Micron Technology, Inc.
ADVANCE
z
m
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•
EDO-PAGE-MODE EARLY-WRITE CYCLE
m
c
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~:~ :Z2t=jt=iWJC:::CO~l~UM~N=~~W~~~~~WC~~=kw4(zz~
ADDR
I 'eWl
I
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'WP
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EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
~
RASP
-
I~I
leSH
=-.1
!~
ADDR
~:~
::;J;2\
tRAH~!
'ASR
ROW
W,0
I I~
:{!dffNOTE21
I
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t WRH
I
2§£\!
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tcWl-twp-l
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ROW
COLUMN
)
'AWD
'RAL
1
IWp __
IAWD
I
'AWD
--
,l.1-'RWl
--'CWL
_twp
I~
~II~ ~ II~'M
I
I
~- l
I
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-- -
~~
-~-I J; -
1:-
OPEN~
'OE-
NOTE:
'RWD
A
'CAS
r---,
COLUMN
I~
'cLz -
-
I~ lAse
COLUMN
IRSH
~
r---,
~
I
teAS
~
~i
'AR
'RAO
.t'WRP
IpC / tpRWC NOTE 1
tCAS
IRCD
VAUD
Dour
-
.0.-
'eLZ
~~
VAUO
DIN
-~-I 1:-
'eLZ
VAU~p
"'W'~~
OOlIT
___ too
__ '00
toE- --
VALID ! , - - O P E N 01111
_;'12'00
'OE-
-
tOEH
~
DON'T CARE
~
UNDEFINED
1. tpc is for LATE WRITE cycles only.
2. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WEHIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC8M8P4IC2
D20.pm5- Rev. 2/95
1-87
Micron Technoiogy, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
»
s:
ADVANCE
z
m
~-------------------------
•
EDO-PAGE~MODE
READ-EARL Y-WRITE CYCLE
(Pseudo READ-MODiFY-WRiTE)
m
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tAASP
o
tCSH
C
::xJ
teAP
tpc
~
tRCD
»
:s::
tpc
tcp
tcp
leAS
I~
ADDR
COLUMN (Al
WE
tAAC
DO
~:gr
-----
OPEN
tePA I
~
I
I
~
-----:f----;V;;;;AL;,D;;;;DAT:;;;-A;;;;(A)-~
tWHZ_
VALID
DATA (8
tOE
GE
~:~= W/;"/////$////$//;"$//;"//MJ,-
RAS-ONL Y REFRESH CYCLE
AAS
CAS
MOO
NOTE:
~:t _ __--"'tc=AP_.li~·_~
'll~R~b'W :l _____
___
tRA_S_ _ _ _ _ _
~:t _-d---1~·----~··~-;--------------,----jl-.~--l:-------;~----;~-;------::t
=- ', " ±.~
"kw#/#M###$ff#$/###ffa'!0<
II
"~
.~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and IWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC8M8P4/C2
D20.pm5 - Rev. 2/95
1-88
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
z
m
--------------------------------------~
•
CBR REFRESH CYCLE
(Addresses and OE = DON'T CARE)
.
'RP
., .
. . 'RAS
=ie:~l
'RPC
II
-
'CSR
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-~--
CAS ~:t-
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.~
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..
'RP
.
'wRPll'WRH
.
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HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
(READ)
.
tRAS
J
~.
IRSH
tRCO
i
II
II
'AR
tRAD
H
---,..-
.
.
(REFRESH)
'R AS
tCHR
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~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
l>
s:
ADVANCE
z
m
MICRON
1-·
MT 4LC8M8P4/C2
8 MEG x 8 DRAM
,""00>00'"
~--------------------------------------
•
READ. CYCLE
(with WE-controlled disable)
m
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ADDR
I_
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NOTE:
~:t ]I!//!!I!!II!/!/I//!/////!/////!!I!//!//!!I///!I/I!M-
'OE
~
DON'T CARE
12221
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and twRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4lC8M8P4IC2
D20.pm5- Rev. 2/95
1-90
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995,MlcronTechnology,lnc.
UII::::I=ICN
MT4C16270
256K x 16 DRAM
m~,occc,"c
1-·
256K x 16 DRAM
DRAM
•
m
5V, EDO PAGE MODE
C
FEATURES
PIN ASSIGNMENT (Top View)
• Industry-standard x16 pinouts, timing, functions
and packages
• High-performance CMOS silicon-gate process
• Single +5V ±10% power supply*
• Low power, 3mW standby; 300mW active, typical
• All device pins are TTL-compatible
• 512-cycle refresh in 8ms (nine rows and nine columns)
• Refresh modes: RASONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
• Extended Data-Out (EDO) PAGE MODE access cycle
• BYTE WRITE and BYTE READ access cycles
OPTIONS
V"
001
002
003
DO'
V"
DOS
DO'
DO?
008
NC
NC
MARKING
• Timing
60ns access
70ns access
80ns access
WE
AAS
NC
AO
A1
-6*
-7
-8
• Write Cycle Access
BYTE or WORD via CAS
A2
A3
V"
Vco
001
002
003
DO'
are limited to a Vee range of ±5%. Contact factory for
',KEY TIMING PARAMETERS
SPEED
-6
I
I -7
-8
I
I
I
tRC
110ns
130ns
150ns
tRAC
60ns
70ns
80ns
tpc
25ns
30ns
33ns
IAA
30ns
35ns
40ns
ICAC
15ns
20ns
20ns
ICAS
10ns
12ns
12ns
W06.pm5 - Rev. 2195
I
5
36
35
34
33
,
,
7
8
9
10
11
12
13
14
15
16
17
18
19
20
38
37
Vso
0016
0015
D014
OQ13
Vso
0012
0011
32
31
OQ10
30
29
2B
27
NC
liE
26
A8
25
24
A7
23
22
21
DO'
CASl
CASH
A6
AS
A4
V"
V"
DQ16
0015
D01.
0013
V"
DOS
D06
007
DOS
OQ12
0011
DQlO
DQ9
NC
NC
The MT4C16270 is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x16 con,figuration. The MT4C16270 has both BYTE WRITE and
: I WORD WRITE access cycles via two CAS pins.
'I The MT4C16270 offers an accelerated cycle access called
IEDO PAGE MODE.
, The MT4C16270 CAS function and timing are deterImined by the first CAS (CASL or CASH) to transition LOW
: and by the last to transition back HIGH. CASL and CASH
} MT4C16270
39
Vc<
WE
GENERAL DESCRIPTION
,
40
40/44-Pin TSOP
(DB-4)
DJ
TG
Part Number Example: MT4C16270DJ-7
I *60ns specifications
I availability of 6Ons.
1
2
3
16270
• Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
I'
40-Pin SOJ
(DA-7)
NC
CASL
CASH
AAS
NC
AO
A1
A2
A3
liE
Vco
V"
A.
A7
A'
AS
A'
function in an identical manner to CAS in that either CASL
or CASH will generate an internal CAS. Use of only one of
the two results in a BYTE WRITE cycle. CASL transitioning
LOW selects a WRITE cycle for the lower byte (DQ1-DQ8)
and CASH transitioning LOW selects a WRITE cycle for the
upper byte (DQ9-DQ16). BYTE READ cycles are achieved
through CASL or CASH in the same manner.
1-91
Micron Technology, Inc., reserves the right to change products or speclflcations without notice.
©1995,MlcronTechnology, Inc.
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MICRON
1-·
MT4C16270
256K x 16 DRAM
,",",ocoon,
FUNCTIONAL BLOCK DIAGRAM
WE -+-f---'---------,
CASL o-l.....f,--'<5i0
CASH
~~~---~
CONTROL
LOGIC
DATA-IN BUFFER
001
••
0016
1+-----oOE
AD
A1
A2
A3
A4
A5
A6
A7
AS
512x512x16
MEMORY
ARRAY
MT4C16270
W06.pm5 - Rev. 2/95
1-92
-----0
Vee
+------0
Vss
Micro"n Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc.
FUNCTIONAL DESCRIPTION
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. Taking WE LOW will initiate a
WRITE cycle, selecting DQl through DQI6. If WE goes
LOW prior to CAS going LOW, the output pin(s) remain
open (High- Z) until the next CAS cycle. If WE .goes LOW
after CAS goes LOW and data reaches the output pins, dataout (Q) is activated and retains the selected cell data as long
as CAS and OE remain LOW (regardless of WE or RAS).
This late WE pulse results in a READ WRITE cycle.
The 16 data inputs and 16data outputs are routed through
16 pins using common I/O, and pin direction is controlled
by OE , WE and RAS.
EDO PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined (AO-AS) page boundary. The EDO
PAGE MODE cycle is always initiated with a row-address
strobed-in by RAS followed by a column-address strobedin by CAS. CAS may be toggled by holding RAS LOW and
strobing-in different column-addresses, thus executing
faster memory cycles. Returning RAS HIGH terminates
the EDO PAGE MODE operation.
Each bit is uniquely addressed through the IS address
bits during READ or WRITE cycles. These are entered 9 bits
(AO-AS) at a time. RAS is used to latch the first 9 bits and
CAS the latter 9 bits.
The CAS control also determines whether the cycle will
be a refresh cycle (RAS ONLY) or an active cycle (READ,
WRITE or READ WRITE) once RAS goes LOW. The
MT4C16270 has two CAS controls, CASL and CASH.
The CASL and CASH inputs internally generate a CAS
signal functioning in an identical manner to the single
CAS input on the other 256K x 16 DRAMs. The key difference is that each CAS controls its corresponding DQ tristate
logic (in conjunction with OE and WE and RAS). CASL
controls DQl through DQS and CASH controls DQ9 through
DQI6.
The MT4C16270 CAS function is determined by the first
CAS (CASL or CASH) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give
the MT4C16270 both byte READ and byte WRITE cycle
capabilities.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
I
+ - - - - WORD WRITE _______________ [ ••- - - - L O W E R BYTE WRITE
RAS~
I
\
\~
\ ! c - . - - - - _I
\'--+-_--+-_ _~I
WE
STORED
DATA
UPPER BYTE
(009·0016)
OF WORD
r____r-
\~--~/
CASH
LOWER BYTE
(001·008)
OF WORD
~I
~
~
INPUT
INPUT
STORED! STORED
~ D~r D~r
DATA
1----
o -
DATA.:
-»
0
0
0
0
0
0
,.
0
0
-
-;i>
,.
•••
---:0>
0>
---;,.
'"","~0
0
t
0
-----3>
.-----»
-----;0>
1
0
---?;>
1·-----;,.
1·-----;:.
1 -----;,..
1
1
1
---3>
1------3>
1
---3>
---3>
---~
ADDRESSO
~
INPUT
INPUT
STORED
DATA
DATA
DATA
::~'
~ :::.:
x ----- --X
X
..
--
--3>
0
--»
1
--3>
--3>
1
1
--;>
1
--3>
1
::~'
•• _._._...
••
,.
1
0
----------
--
3>
1
-
-3>
---?
1
.0>
1
1
.0>
~ ••- - - - - ADDRESS 1
-------+1
X", NOT EFFECTIVE (DON'T CARE)
Figure 1
WORD AND BYTE WRITE EXAMPLE
MT4C16270
W06.pm5 - Rev. 2195
1-93
Micron Technology, Inc.• reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
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1-·
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MT4C16270
256K x 16 DRAM
"'"'"CC""'''
BYTE ACCESS CYCLE
The BYTE WRITE cycle is determined by the use· of
CASL and CASH. Enabling CASL will select a lower BYTE
WRITE cycle (DQI-DQ8) while enabling CASH will select
an upper BYTE WRITE cycle (DQ9-DQ16). Enabling both
CASL and CASH selects a WORD WRITE cycle.
The MT4C16270 can be viewed as two 256K x 8 DRAMs
which have common input controls. Figure 1 illustrates the
MT4C16270 BYTE WRITE and WORD WRITE cycles. The
BYTE READ is accomplished in the same manner.
going invalid (see READ and EDO-PAGE-MODE READ
waveforms).
EDO operates as any DRAM READ or FAST-PAGEMODE READ, except data will be held valid after CAS
goes HIGH, as long as RAS and OE are held LOW and WE
is held HIGH. OE can be brought LOW or HIGH while
CAS and RAS are LOW, and the DQs will transition between valid data and High-Z. Using OE, there are two
methods to disable the outputs and keep them disabled
during the CAS HIGH time. The first method is to have
OE HIGH when CAS transitions HIGH and keep OE
HIGH for tOEHC. This will tristate the DQs and they will
remain tristate, regardless of OE, until CAS falls again. The
second method is to have OE LOW when CAS transitions
HIGH. Then OE can pulse HIGH for a minimum of tOEP
anytime during the CAS HIGH period and the DQs will
tristate and remain tristate, regardless ofOE, until CAS falls
again (please reference Figure 2 for further detail on the
EDO PAGE MODE
DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS. If
CAS goes HIGH, and OE is LOW (active), the output
buffers will be disabled. The MT4C16270 offers an accelerated PAGE MODE cycle by eliminating output disable
from CAS HIGH. This option is called EDO and it allows
CAS precharge time (tcP) to occur without the output data
RAs
~i~=~~_______________________________________
-
VIH
CAS
VIL-
--------~
\
)\
1
:
:
ADDR
~:t:
. \ _ _-.-.1
1
=>@~OO~~~~~~~~~>C~\C~OL~UM~N~{B)0<:~~~~~KJ"~~OL~UM~N£{C;::))fZ~~~~~~{(\
COLUMN (D)
XZM.
I
DQ '110H
VIOL
6E
-----.:~~~:a
I
~~~~~~~~~_O'_'N ~
i:~:, I
,...,..
~I-·r:!
~:~_
,
~··lsTA{c)
too
__
~
t
_o~,
________
!
r-9
~
L _ _ _ _ _ _~I
!
VALID DATA (D)
tm; - - - - - - - -
!
The DOs go back to
The DOs remain High-Z
The DOs remain High-Z
Low-Z if toES is met.
until the next CAS cycle
if tOEHC is met
until the next CAs cycle
if tOEP is met.
~
DON'TeARE
~
UNDEFINED
Figure 2
OUTPUT ENABLE AND DISABLE
MT4C16270
W06.pm5- Rev. 2195
1-94
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
toggling OE condition). During other cycles, the outputs are
disabled at tOFF time after RAS and CAS are HIGH, or
tWHZ after WE transitions LOW. The tOFF 'time is referenced from the rising edge of RAS or CAS, whichever
occurs last. WE can also perform the function of turning off
the output drivers under certain conditions, as shown in
Figure 3.
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby leveL
The chip is also preconditioned for the next cycle during the
RAS HIGH time. Memory cell data is retained in its correct
state by maintaining power and executing any RAS cycle
(READ, WRITE) or RAS refresh cycle (RAS ONLY,
CBR, or HIDDEN) so that all 512 combinations of RAS
addresses (AD-A8) are executed at least every 8ms, regardless of sequence. The CBR REFRESH cycle will also invoke
the refresh counter and controller for row-address controL
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VALID DATA (A)
~:~
VALID DATA (B)
fi1+--tW~wpz_--+-I_ _~-,---+/z_/~
+---
: ____
r
The DOs go to High-Z if WE falls, and if twpz is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
/
WE may be used to disable the DOs to prepare
for input data in an EARLY WRITE cycle. The DOs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
!tZ1 DON'TCAA.E
~
UNDEFINED
Figure 3
OUTPUT ENABLE AND DISABLE WITH WE
MT4C16270
W06.pmS ~ Rev. 2195
Micron TechnologY,lnc.,
r~serves the right to change products or specifications withollt notice.
©1995, Micron Technology, Inc.
MICRON
1-·
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MT4C16270
256K X 16 DRAM
,,"""",00,"'
TRUTH TABLE
ADDRESSES
IR
IC
FUNCTION
RAs-
CASl
CASH
WE
or
Standby
H
H~X
H~X
X
X
X
READ: WORD
L
L
L
H
L
ROW
COL
Data-Out
READ: LOWER BYTE
L
L
H
H
L
ROW
COL
Lower Byte, Data-Out
Upper Byte, High-Z
READ: UPPER BYTE
L
H
L
H
L
ROW
COL
Lower Byte, High-Z
Upper Byte, Data Out
WRiTE: WORD
(EARLY WRITE)
L
L
L
L
X
ROW
COL
Data-In
WRITE: LOWER
BYTE (EARLY)
L
L
H
L
X
ROW
COL
Lower Byte, Data-In
Upper Byte, High-Z
WRITE: UPPER
BYTE (EARLY)
L
H
L
L
X
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-In
X
DOs
NOTES
High-Z
L
L
L
H-'+L
L~H
ROW
COL
Data-Out, Data-In
1,2
EDO-PAGE-
1st Cycle
L
H~L
H~L
H
L
ROW
COL
Data-Out
2
MODE READ
2nd Cycle
L
H~L
H-+L
H
L
n/a
COL
Data-Out
2
EDO-PAGE-
1st Cycle
L
H-+L
H~L
L
X
ROW
COL
Data-In
1
MODE WRITE 2nd Cycle
L
H-+L
H~L
L
X
n/a
COL
Data-In
1
EDO-
L
H.,..L
H-+L
H~L
L~H
ROW
COL
Data-Out, Data-In
1,2
L
H~L
H~L
H-+L
L-+H
n/a
COL
Data-Out, Data-In
1,2
READ WRITE
1st Cycle
PAGE-MODE 2nd Cycle
READ-WRITE
HIDDEN
READ
L~H~L
L
L
H
L
ROW
COL
Data-Out
2
REFRESH
WRITE
L~H~L
L
L
L
X
ROW
COL
Data-In
1,3
L
H
H
X
X
ROW
n/a
High-Z
H~L
L
L
X
X
X
X
High-Z
RAS-ONLY REFRESH
CBR REFRESH
NOTE:
1.
2.
3.
4.
MT4C16270
W06.pm5 - Rev. 2/95
4
These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active).
These READ cycles may also be BYTE READ cycles (either CASL or CASH active).
EARLY WRITE only.
At least one of the two CAS signals must be active (CASL or CASH).
1-96
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc
MICRON
1-·
MT4C16270
256K X 16 DRAM
"'"",WGne
*Stresses greater than those listed under" Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee Supply Relative to Vss .............. -IV to +7V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55°C to +150°C
Power Dissipation ....................................................... :.. 1.2W
Short Circuit Output Current ..................................... 50mA
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +5V ±1 0%)**
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Vcc'*
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
Ii
-2
2
iJ A
loz
-10
10
VOH
2.4
iJ A
V
0.4
V
Supply Voltage
INPUT LEAKAGE CURRENT
Any input OV ~ VIN ~ Vcc
(All other pins not under test = OV)
OUTPUT LEAKAGE CURRENT (0 is disabled; OV ~ VOUT ~ 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT = -2.5mA)
Output Low Voltage (lOUT = 2.1 mAl
VOL
NOTES
MAX
PARAMETER/CONDITION
SYMBOL
-6*'
·7
-8
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
Icc1
2
2
2
UNITS NOTES
mA
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
Icc2
1
1
1
mA
25
.
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIND
Icc3
.195
175
160
mA
3,4,40
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
(RAS = VIL, CAS, AddressCycling: tpc = tpG[MIN]; tcp, tASC = 10ns)
ICC4
130
125
120
mA
3,4,40
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS=VIH: tRC = tRC[MIND
Icc5
195
175
160
mA
3
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIN])
Icc6
180
160
140
mA
3,5
**60ns specifications are limited to a Vcc range of ±5%.
MT4C16270
WOS.pmS - Rev. 2/95
1-97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
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MT4C16270
256K x 16 DRAM
m~"co"""
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
c
o
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:c ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
»
s
Input Capacitance: AO-A8
Cll
5
pF
2
Input Capacitance: RAS, CASL, CASH, WE, OE
CI2
7
pF
2
Input/Output Capacitance: DQ
Cia
7
pF
2
(Notes: 6, 7, 8, 9,10, 11, 12, 13) (Vcc
AC CHARACTERISTICS
PARAMETER
=+5V ±1 0%)*
-6'
-7
MIN
tACH
15
15
20
ns
tAR
40
40
55
ns
tAse
tASR
0
0
0
0
0
ns
Row-address setup time
0
55
ns
ns
Access time from column-address
Column-address setup to CAS
precharge during WRITE
Column-address hold time
(referenced to RAS)
Column-address setup time
Column-address to WE delay time
tAWD
Access time from CAS
Column-address hold time
tCAC
tCAH
CAS pulse width
tCAS
CAS hold time (CBR REFRESH)
last CAS going lOW to first CAS
returning HIGH
CAS to output in low-Z
Data output hold after CAS lOW
MAX
MIN
-8
SYM
tAA
30
MAX
35
60
15
MAX
UNITS
40
ns
65
20
12
10
MIN
ns
ns
10,000
ns
29
37
15
10
10
ns
5,30
10
10
10
ns
32
tClZ
3
5
10
3
5
10
3
5
10
ns
ns
31,41
ns
ns
16,34
ns
30
ns
ns
30
5,29
45
ns
21,29
12
15
ns
26,30
ns
22,31
60
0
ns
ns
22,31
ns
ns
28,39,41
23,31
27
tCPA
CAS to RAS precharge time
CAS hold time
tCRP
5
5
tCSH
40
10
40
CAS setup time (CBR REFRESH)
35
10,000
12
40
45
5
60
110
CAS to WE delay time
tCSR
tCWD
Write command to CAS lead time
Data-in hold time
tCWl
tDH
10
10
Data-in hold time (referenced to RAS)
Data-in setup time
tDHR
tDS
40
tOD
tOE
3
tOEH
15
20
20
ns
tOEHC
tOEP
tOES
10
10
10
10
ns
10
5
10
5
ns
ns
tOFF
3
OE LOW to CAS HIGH setup time
Output buffer turn-off delay from
CASorRAS
15,31
tCHR
12
CAS precharge time
OE hold time from WE during
READ-MODIFY-WRITE cycle
OE HIGH hold time from CAS HIGH
OE HIGH pulse width
21
20
tClCH
10,000
Access time from CAS precharge
Output Enable time
29
10
10
tCOH
tcp
Output disable time
NOTES
10
45
40
12
15
40
0
15
0
3
15
3
20
15
5
15
3
15
15
20
3
15
ns
31
20,28,31,
41
*60ns speCifications are limited to a Vcc range of ±5%.
MT4C16270
W06.pm5-Rev.2195
1-98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
256K
,",""coon,
MT4C16270
X 16 DRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +5V ±10%)*
PARAMETER
OE setup prior to RAS during
HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE
cycle time
EDO-PAGE-MODE READ-WRITE
cycle time
Access time from RAS
RAS to columnaddress delay time
Row-address hold time
Column-address to
RAS lead time
-7
-6*
AC CHARACTERISTICS
MAX
MIN
MAX
MIN
0
0
0
ns
tpc
25
30
33
ns
33
tpRWC
72
79
84
ns
33
ns
ns
14
18
10
10
10
ns
22
27
30
ns
60
10,000
70
10,000
60
100,000
70
100,000
Random READ or WRITE cycle time
110
RAS to CAS delay time
tRCD
20
Read command hold time
(referenced to CAS)
tRCH
0
Read command setup time
Refresh period (512 cycles)
tRCS
0
RAS precharge time
RAS to CAS precharge time
Read command hold time
(referenced to RAS)
UNITS
tRAH
tRAL
15
tRAS
RAS pulse width (EDO PAGE MODE)
MAX
15
70
35
tRASP
tRC
RAS pulse width
MIN
tRAC
tRAD
60
30
tREF
tRP
tRPC
tRRH
20
50
0
ns
ns
60
ns
ns
20
ns
0
0
0
8
10,000
100,000
150
130
45
80
40
15
80
80
8
8
ns
ms
NOTES
17,29
19,26,30
26,29
35
10
40
60
10
10
ns
ns
0
0
0
ns
19
38
RAS hold time
tRSH
10
15
15
ns
READ WRITE cycle time
140
157
187
ns
RAS to WE delay time
tRWC
tRWD
85
95
105
ns
21
Write command to RAS lead time
Transition time (rise or fall)
tRWL
tT
10
12
12
2
ns
ns
26
9, 10
Write command hold time
tvvCH
tvvCR
10
ns
40
ns
26,38
26
twcs
0
ns
21,26,29
tWHZ
twp
3
10
Write command hold time
(referenced to RAS)
Write command setup time
Output disable delay from WE
Write command pulse width
2
50
2
50
10
40
3
10
50
10
60
0
15
0
15
3
10
15
ns
ns
26
*60ns specifications are limited to a Vcc range of ±5%.
I
MT4C1~270
WOS.pm5 - Rev. 2f95
1-99
m
-8
SYM
tORD
Micron Technology. Inc., reserves the right
to change products or specifications without notice.
©1995, Micron Technology, Inc.
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MIC:RON
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~~~~~tages
MT4C16270
256K x 16 DRAM
'c'"""", "
referenced to Vss.
2. This parameter is sampled. Vee = 5V ±10%; f = 1 MHz.
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C ~ TA ~ 70°C) is assured.
7. An initial pause of lOOf.ls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR) before proper device operation is assured. The
eight RAS cycle wake-ups should be repeated any
time the IREF refresh requirement is exceeded.
8. AC characteristics assume IT = 2.5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS and RAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to one TTL gate and
SOpF, VOL = 0.8V and VOH = 2.0V.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the Q buffer, CAS and RAS must be
pulsed HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if tRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by tCAe.
18. Operation within the lRAD limit ensures that tRCD
(MAX) can be met. tRAD (MAX) is specified as a
reference point only; if tRAD is greater than the
specified tRAD (MAX) limit, access time is controlled
exclusively by tAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition; it is not a
reference to VOH or VOL.
MT4C16270
W06.pmS-Rev.2195
21. IWCS, tRWD, tAWD and tCWDare restrictive
operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. If IWCS ~ twcs (MIN),
the cycle is an EARLY WRITE cycle and the data
output will remain an open circuit throughout the
entire cycle. If tRWD ~ tRWD (MIN), tAWD ~ tAWD
(MIN) and ICWD ~ tCWD (MIN), the cycle is a
READ-WRITE and the data output will contain data
read from the selected celL If neither of the above
conditions is met, the state of Q (at access time and
until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW result in a LATE WRITE (OE-controlled)
cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. During a READ cycle, if OE is LOW then taken HIGH
before CAS goes HIGH, Q goes open. If OE is tied
permanently LOW, a LATE WRITE or READMODIFY-WRITE operation is not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and OE = HIGH.
25. All other inputs at Vcc -O.2V.
26. Write command is defined as WE going LOW.
27. LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide the previously written data if CAS
remains LOW and OE is taken back LOW after tOEH
is met.
28. The DQs open during READ cycles once tOD or tOFF
occur.
29. The first CASx edge to transition LOW.
30. The last CASx edge to transition HIGH.
31. Output parameter (DQx) is referenced to corresponding CAS input, DQI-DQ8 by CASL and DQ9-DQI6
by CASH.
32. Last falling CASx edge to first rising CASx edge.
33. Last rising CASx edge to next cycle's last rising CASx
edge.
34. Last rising CASx edge to first falling CASx edge.
35. First DQs controlled by the first CASx to go LOW.
36. Last DQs controlled by the last CASx to go HIGH.
37. Each CASx must meet minimum pulse width.
38. Last CASx to go LOW.
39. All DQs controlled, regardless CASL and CASH.
40. Column-address changed once each cycle.
41. The 3ns minimum is a parameter guaranteed by
design.
1-100
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC::RON
1-·
MT4C16270
256K x 16 DRAM
,,,",,,,,,,,,
•
READ CYCLE
tRAS
m
IRP
~I
IRSH
I~
r-"'--i
J
ADDR
V,H
VIL
ij'///~
tRCD
telcH
'CAS
IAR
I
~
tRAL
I
I
~1
lAse ~I
~1
ROW
I
I
tRAD
ROW
COLUMN
~
I
j'///////////////////////////////
DE
c
:c
1\
IRCS
DQ
c
o
\
leSH
I
1M
I
'RAG
'\2
I
NOTE 1
I 'CAG
~I,
~g~-
OPEN
~
I~
~OPEN--
VAUDDATA
~
~:~ -I1U//U/U/U/jijU/U/U//UU/jijU///UU///uml
EARLY WRITE CYCLE
RC
IRP
'RAS
-
fr
\
le8H
~J~
tRCD
IAR
I
tRAD
ADDR
I~~I
~:~ :w-"x
~
ROW
I
~I
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I~I
f
tACH
ROW
tCWL
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V1H
v"
tRAL
'CLCH
COLUMN
tt~'~i
WE
I
I
I
I
I
'RWL
'WCR
I~
IWp
I
I
~OHR
~_'DSII~~
DO
i NOTE:
~:g~ ~
VALID DATA
~
DON'T CARE
~
UNDEFINED
1. toFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
)
MT4C16270
I
W06.pm5 - Rev. 2195
1-101
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©199S, Micron Technology, Inc.
»
s:
MICRON
1-·
MT4C16270
256K x 16 DRAM
"'""'w"' '"
•
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
m
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IRWD
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'AWD
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I
tACH
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'CLCH
'RAl I
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'cSH
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tRCD
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tRAG
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I
'CAG
'Cl2- .~
-
~~,
-tOD:l' -VALID DOUT
OPEN
~
VALID DIN
OPEN--
IOEH
EDO-PAGE-MODE READ CYCLE
'RASP
'CSH
I~
J
~:~
j,,//x
tASR
'AR
II 'RAD
~I
'RAH
ROW
Wla
I
f'$II_II~
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COLUMN
'RCS
I
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I
'AA
I
'RAG
'ClZ-
Killilia
'CP
I
I
I
I
'CPA
'cOH_
VALID
I
I
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J//;@II/;@MIII!;0?/$##/ml~
DATA
'AA
'CPA
I 'CAC
1_
~
,I
VALID
DATA
ROW
I'RC~!~
I
I
'AA
I
COLUMN
I 'CAC
1:'OE
WIIIII,1
I
I
~ll tCAH~1
leAH"1
COLUMN
'CAG
OPEN
NOTE:
II
'RAL
~
I
I
I
'RSH
_'_CP_ 'cAS, 'C'Cl;!.y
ICAS, tCLC~\
~
~I I~
I
~=L
(NOTE 1)
_'C_P_
teAS, tCLCt!1
~:i
II
I~
ADDR
IpC
tRCD
I
'CLZ toEH2
1:tOE
~
~
VALID
DATA
--tOFF
t--- OPEN
;;~/$~
~
DON'T CARE
~
UNDEFINED
1,tpc can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising
edge of CAS, Both measurements must meet the tpc specification,
MT4C16270
W06.pmS-Rev.2195
1-102
Micron Technology, Inc., reserves the right to change prcducts or spe ciflcations W1thout notice.
©1995, MicrcnTechnology, Inc.
UII:::I=ICN
MT4C16270
256K x 16 DRAM
"'~'cco,,'"
1-·
•
EDO-PAGE-MODE EARLY-WRITE CYCLE
m
CASLand CASH
V,H
c
o
_c-i---ii-------,,,
'---+---1
V,L -
C
:XJ
»
5
DE
~:~
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EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
RASP
----.
1CASLandCASH
VIH
V"
~
=J
I~II ::::
ADDR
~1~
1//M
'Ipe !lpRWC NOTE 1
tOSH
tRCD
teRP
ROW
lASe
r&'.bi
~
teAS tCLCH
~1
l.r-----c
I I~I
I
I
-1"'1 I ,~i:y
I~
tRAC
I'M
--
I
II
telz --
~
'05-
r-
OPEN~ ~ALlD
_
NOTE:
,:~:
ll~
I
~' I
1- I----"""ftePA
f-
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VAllO
-~ -
t CLZ
):-
~ALIO
~-~
IUJ
--
tOE-
COLUMN
I
-
ROW
II-'Rwl
1
--~
1 - - '05tePA
-~--I !:-
teLz
VALID
I~ I-E..!!L
-'aD
-
~
-
I~
~ll~
- I
'05-
:I
[ :(
==rr
I~
-'00
toE-
'RAL
~II tCPJi'~1
WI/llllih
COLUMN
~
'RWO I
I
ICAS, tcLCH
r----J
l~ ~I
WI/II///t?
COLUMN
PL
vY==l
IRSH
'ep
leAs tCLCH
~AlI ~OPEN-
:v:u'~tf;:
-too
tOE
-
I~
~
DON'TCAAE
~
UNDEFINED
1. tpc can be measured from falling edge to falling edge of CAS, or from rising edge to rising edge of CAS.
Both measurements must meet the tpc specification.
MT4C16270
W06.pm5- Rev. 2195
1-103
Micron Technology, Inc., resetves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
256K
"'"""C,,""'
•
MT 4C16270
x 16 DRAM
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Psuedo READ-MODiFY-WRiTE)
m
c
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'RASP
tRP
C
:II
l>
3:
DQ
~~g~=:
_ _ _ _ OPEN
RAS-ONL Y REFRESH CYCLE
(OE, WE = DON'T CARE)
RAS
CASL ,M CASH
V,H
VIL _
~IH
IL
-
d
IcRP
1
tASR
AOOR
NOTE:
~IH-~
IL
_
'RC
IRAS
IRP
't7ir------'----h-r.,..,.,-,.,..,-J,---'----'-------'---------,J
VlL -u..u-"-,-,-,<.LLJ
DQ ~gt ---------OPEN-------~~M--~~;:;:_~
I:tZI DON'T CARE
~
NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for 'WRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4C16270
W06.pm5 - Rev. 2/95
1-106
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
ADVANCE
256K x 16 DRAM
DRAM
3.3V, EDO PAGE MODE
FEATURES
PIN ASSIGNMENT (Top View)
• Single +3.3V ±O.3V power supply*
• Industry-standard x16 pinouts, timing, functions
and packages
• High-performance CMOS silicon-gate process
• Low power, 1mW standby; 85mW active, typical
• All device pins are TTL-compatible
• 512-cycle refresh in 8ms (nine rows and nine columns)
• Refresh modes: RAS ONLY,CAS-BEFORE-RAS (CBR)
and HIDDEN
• Extended Data-Out (EDO) PAGE MODE access cycle
• BYTE WRITE and BYTE READ access cycles
OPTIONS
-7
-8
6
7
8
OQ12
,
34
33
32
10
31
NC
11
30
DQ'
NC
CASL
V"
0011
0010
NC
12
29
WE
13
28
CASH
RAS
27
26
DE
NC
14
15
AO
16
25
A7
A1
A2
17
18
24
23
22
21
A6
A5
Vee
Vee
IRAC
IpC
IliA
ICAC
ICAS
DOS
D06
D07
DOS
60ns
70ns
80ns
25ns
30ns
33ns
30ns
35ns
40ns
i5ns
20ns
20ns
iOns
i2ns
i2ns
WE
NC
NC
The MT4LC16270 is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x16 configuration. The MT4LC16270 has both BYTE WRITE and
WORD WRITE access cycles via two CAS pins.
The MT4LC16270 offers an accelerated access cycle called
EDO PAGE MODE.
The MT4LC16270 CAS function and timing are determined by the first CAS (CASL or CASH) to transition LOW
and by the last to transition back HIGH. CASL and CASH
MT4LCl6270
OQ13
Vee
D01
D02
D03
D04
GENERAL DESCRIPTION
W07.pm5 - Rev. 2laS
0015
DQ14
"20
A8
A4
V"
40/44-Pin TSOP
(D8-4)
KEY TIMING PARAMETERS
ii0ns
i30ns
i50ns
DQ16
D05
V"
*60ns specifications are limited to a Vee range of ±O.lSV. Contact factory for
availability of 60ns.
-6
-7
-8
36
35
V"
5
A3
DJ
TG
40
39
38
37
D04
D06
D07
DOS
• Part Number Example: MT4LC16270DJ-7
SPEED
2
-6*
• Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
IRC
D01
D02
D03
MARKING
• Timing
60nsaccess
70ns access
80ns access
1
V"
0016
0015
D014
DQ13
V"
DQ12
DQ11
DQW
DO,
NC
CASL
CASH
RAS
DE
NC
AO
A1
A2
A3
A8
A7
A6
AS
A4
Vee
V"
function in an identical manner to CAS in that either CASL
or CASH will generate an internal CAS. Use of only one of
the two results in a BYTE WRITE cycle. CASL transitioning
LOW selects a WRITE cycle for the lower byte (DQ1-DQ8)
and CASH transitioning LOW selects a WRITE cycle for the
upper byte (DQ9-DQ16). BYTE READ cycles are achieved
through CASL or CASH in the same manner.
1-107
m
c
o
C
:D
40-Pin SOJ
(DA-7)
Vee
•
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
»
s:
ADVANCE
MICRON
MT 4LC16270
256K X 16 DRAM
~"
I-a
II
FUNCTIONAL BLOCK DIAGRAM
m
c
WE
0
C
JJ
CASL
CASH
CONTROL
LOGIC
pATA·IN BUFFER
l>
001
••
s:
0016
!+---........,OE
AO
A1
A2
A3
M
A5
A6
A7
AS
512 X 512 X 16
MEMORY
ARRAY
RAS
O--'"-IL.:~~~J::====~____.J
MT4LC16270
W07.p1n5 - Rev. 2195
1-108
_--:.0'0 Vee
+-----0
Vss
Micron Technology, Inc., reserves the right to change products or specHicallons wIthout nOtlce.' ,
@1995,MicronTechnology,lnc:
ADVANCE
MICRON
1-·
MT4LC16270
256K x 16 DRAM
""""C,,""
FUNCTIONAL DESCRIPTION
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs . last. Taking WE LOW will initiate a
WRITE cycle, selecting DQl through DQ16. If WE goes
LOW prior to CAS going LOW, the output pines) remain
open (High- Z) until the next CAS cycle. If WE goes LOW
after CAS goes LOW and data reaches the output pins, dataout (Q) is activated and retains the selected cell data as long
as CAS and OE remain LOW (regardless of WE or RAS).
This late WE pulse results in a READ WRITE cycle.
The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O, and pin direction is controlled
by OE , WE and RAS.
EDO P AGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined (AO-AS) page boundary. The EDO
PAGE MODE cycle is always initiated with a row-address
strobed-in by RAS followed by a column-address strobedin by CAS. CAS may be toggled by holding RAS LOW
and strobing-in different column-addresses, thus executing faster memory cycles. Returning RAS 111(;1 [tl'rminatl's
the EDO PAGE MODE operation.
Each bit is uniquely addressed through the IS address
bits during READ or WRITE cycles. These are entered 9 bits
(AO-AS) at a time. RAS is used to latch the first 9 bits and
CAS tl).e latter 9 bits.
The CAS control also determines whether the cycle will
be a refresh cycle (RAS ONLY) or an active cycle (READ,
WRITE or READ WRITE) once RAS goes LOW. The
MT4LC16270 has two CAS controls, CASL and CASH.
The CASL and CASH inputs internally generate a CAS
signal functioning in an identical manner to the single
CAS input on the other 256K x 16 DRAMs. The key difference is that each CAS controls its corresponding DQ tristate logic (in conjunction with OE and WE and RAS).
CASL controls DQl through DQS and CASH controls DQ9
through DQI6.
~e MT4LC16270 CAS function is determined by the first
CAS (CASL or CASH) transitioning LOW and' the last
transitioning back HIGH. The two CAS controls give the
MT4LC16270 both BYTE READ and BYTE WRITE cycle
capabilities.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
I
+ - - WORD WRITE
-----------l-·---
LOWER BYTEWR!TE
--------..1
RAS
~
\
CASl
\
CASH
LOWER BYTE
(DQi·DQS)
OF WORD
,I
:1
UPPER BYTE
(DQ9·DQi6)
OF WORD
STORED
INPUT
INPlJr
DATA
DATA
DATA
~
~
0
I--~
1
I
STORED STORED
DATA
DATA
~
'I t
~
-----------------?;> 0
...........•
-----------------?;>
-----------------3>
1
-----------------:;>-
0
0
0
0
-----------------:;>-
0
-----------------3>-
-----------------;;>
;--
\
!
\
WE
INPUT
DATA
INPUT
DATA
~..
--
-- --
:~'
-~ -: ~
.--7 0
-
--
--
STORED
DATA
--
- 7
1
--
7
1
-
7
1
---;0.
0
---:0>-
1
X
----->
0·· ---3>
0
L" ".. ~I;
x
-----;;:..
---3>
1
x -
7
1
X
-----3>-
---".
1
1 .----~3>-----;... 1 -----3>-
1
X
-
7
1
1
1
X
-
7
1
X
--
7
1
, ..
-----",.
X
ADDRESSO - - -.- - - - ADDRESS1
---~I
X", NOT EFFECTIVE (DON'T CARE)
,I
I
Figure 1
WORD AND BYTE WRITE EXAMPLE
MT4LCI6270
W07.pm5- Rev.,2195
1-109
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron'Technology, Inc.
•
m
o
o
o
JJ
l>
s:
ADVANCE
MICRON
1-·
•
m
C
o
C
:::D
l>
S
MT4LC16270
256Kx 16 DRAM
"'~"'CO"""
BYTE ACCESS CYCLE
The BYTE WRITE cycle is determined by the use of
CASL and CASH. Enabling CASL will select a lower BYTE
WRITE cycle (DQI-DQ8) while enabling CASH will select
an upper BYTE WRITE cycle (DQ9-DQ16). Enabling both
CASL and CASH selects a WORD WRITE cycle.
The MT4LCI6270 can be viewed as two 256K x 8 DRAMs
which have common input controls. Figure 1 illustrates the
MT4LC16270 BYTE WRITE and WORD WRITE cycles. The
BYTE READ is accomplished in the same manner.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS. If
CAS goes HIGH, and OE is LOW (active), the output
buffers will be disabled. The MT4LC16270 offer an accelerated PAGE MODE cycle by eliminating output disable
from CAS HIGH. This option is called EDO and it allows
CAS precharge time (ICP) to occur without the output data
RAS
ADDR
~:t=~~
going invalid (see READ and EDO-PAGE-MODE READ
waveforms).
Extended data-out operates as any DRAM READ or
FAST-PAGE-MODE READ, except data will be held valid
after CAS goes HIGH, as long as RAS and OE are held LOW
and WE is held HIGH. OE can be brought LOW or HIGH
while CAS and RAS are LOW, and the DQs will transition
between valid data and High-Z. Using OE, there are two
methods to disable the outputs and keep them disabled
during the CAS HIGH time. The first method is to have
OE HIGH when CAS transitions HIGH and keep OE
HIGH for IOEHC. This will tristate the DQs and they will
remain tristate, regardless of OE, until CAS falls again. The
second method is to have OE LOW when CAS transitions
HIGH. Then OE can pulse HIGH for a minimum of IOEP
anytime during the CAS HIGH period and the DQs will
tristate and remain tristate, regardless of OE, until CAS
falls again (please reference Figure 2 for further detail on the
_______________________________________
~:r=.Z;ZK~~~Z;ZW~~~=>
S
ADDR
~:~:~ ~COLUMN(A)
i
COLUMN (B)
I
I
)0'/j'////j'/$j'I$/P/$/;/'C%<:
VALID DATA (A)
r
I
tWHZ
I
/
)0Ml/PII/W'/$h<
COLUMN (C)
/
.L
)fj'!§//;W~
I
"
INPUT DATA (C)
VALID DATA (B)
tWHZ
L
7
I
The DOs go to High-Z if WE falls, and if twpz is met,
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is ,initiated).
9
I
/
/
/
/
WE may be used to disable the DOs to prepare
for input data in an EARLY WRITE cycle. The DOs
will remain High-Z until CAS goes LOW with
WE HIGH (i.e., until a READ cycle is initiated).
~ DON'TeARE
~
UNDEFINED
Figure 3
OUTPUT ENABLE AND DISABLE WITH WE
MT4LC16270
WD7.pm5 - Rev. 2/95
1-111
Micron Technology. Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
•
m
c
o
C
:D
»
s:
MT4LC16270
256K x 16 DRAM
",,,,coc,,"'
TRUTH TABLE
ADDRESSES
IR
IC
FUNCTION
RAS
CAS[
tASH
WE
ar
Standby
H
H-X
H-X
X
X
X
X
DOs
NOTES
High-Z
READ: WORD
L
L
L
H
L
ROW
COL
Data-Out
READ: LOWER BYTE
L
L
H
H
L
ROW
COL
Lower Byte, Data-Out
Upper Byte, High-Z
READ: UPPER BYTE
L
H
L
H
L
ROW
COL
Lower Byte, High-Z
Upper Byte, Data Out
WRITE: WORD
(EARLY-WRITE)
L
L
L
L
X
ROW
COL
Data-In
WRITE: LOWER
BYTE (EARLY)
L
L
H
L
X
ROW
COL
Lower Byte, Data-In
Upper Byte, High-Z
WRITE: UPPER
BYTE (EARLY)
L
H
L
L
X
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-In
READ WRITE
L
L
L
H-L
L-H
ROW
COL
Data-Out, Data-In
1,2
EDO-PAGE-
1st Cycle
L
H-L
H-L
H
L
ROW
COL
Data-Out
2
MODE READ
2nd Cycle
L
H-L
H-L
H
L
n/a
COL
Data-Out
2
EDO-PAGE-
1st Cycle
L
H-L
H-L
L
X
ROW
COL
Data-In
1
L
H-L
H-L
L
X
n/a
COL
Data-In
1
MODE WRITE 2nd Cycle
EDO-PAGEMODE
1st Cycle
READ-WRITE 2nd Cycle
L
H-L
H-L
H-L
L-H
ROW
COL
Data-Out, Data-In
1,2
L
H-L
H-L
H-L
L-H
n/a
COL
Data-Out, Data-In
1,2
HIDDEN
READ
L-H-L
L
L
H
L
ROW
COL
Data-Out
2
REFRESH
WRITE
L->H-L
L
L
L
X
ROW
COL
Data-In
1,3
L
H
H
X
X
ROW
n/a
High-Z
H-L
L
L
X
X
X
X
High-Z
RAS-ONLY REFRESH
CBR REFRESH
NOTE:
1.
2.
3.
4.
MT4lC16270
W07.pmS - Rev. 2/95
4
These WRITE cycles may also be BYTE WRITE cycles (either CASt or CASH active).
These READ cycles may also be BYTE READ cycles (either CASL or CASH active).
EARLY WRITE only.
At least one of the two CAS signals must be active (CASL or CASH).
1-112
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, 'Inc.
ADVANCE
MICRON
1-·
'"'
C
MT 4LC16270
256K x 16 DRAM
K
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under "Absolute. Maxi"
mum Ratings" may cause permanent damage to the <;ievice.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability. '
Voltage on Vee Supply Relative to Vss ........... -IV to +4.6V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SsoC to +IS0°C
Power Dissipation ............................... ;.......................... 1.2W
Short Circuit Output Current ........................ ;............ SOmA
•
m
c
o
C
:D
»
s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +3.3V ±O.3V)"
pARAMETER/CONDITION
SYMBOL
Supply Voltage
Vcc"
MIN
MAX
UNITS
3.0 '
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
Vcc-f;l
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
II
-2
2
~
Ol)TPUT LEAKAGE CURRENT (Q is disabled; OV ~ VOUT ~ Vcc+.5V)
loz
-10
10
~.
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV ~ VIN ~ Vcc
(All other pins not under test = OV)
i
VOL
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS = CAS = V1H)
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
NOTES
V
0.4
I·
...
V
-8
1
MAX
-7
1
1'
mA
ICC2
500
500
500
IJA
25
ICC3
120
110
100
mA
3,4,40
ICC4
70
60
50
mA
3;4,40
Icc5
120
,'hO
,100
mA
3
Icc6
120
110
100
rnA
3,5
SYMBOL
-6""
ICC1
UNITS NOTES
..
OPERATING CURRENT: Random READIWRITE.
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIN])
I.
OPERAT1NG CURRENT: EDO PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: tpc =tpc [MIN]; tcp, tASC
"
\.
=10ns)
REFRESH CURRENT: RAS ONLY
Averag~ power supply current.
(RAS Cycling, CAS=VIH: tRC
=tRC [MIN])
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIN])
.'
"1·"
'*60ns specifications are limited to a Vcc range of ±0.15V.
MT4LC16270
>.
W07.pm5- Rev. 2195
Micron Technology, Inc., r811E1l"Ve8 the right to change products or specifications without notrce.
@1995,MicronTechnoIogy,toe.
ADVANCE
MICRON
1--
•
m
c
o
MT4LC16270
256K x 16 DRAM
,''"",co",,,,
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: AO-A8
Cll
pF
2
Input Capacitance: RAS, CASL, CASH, WE, OE
CI2
pF
2
Input/Output Capacitance: DQ
Cia
5
7
7
pF
2
C
:rJ
»
s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vec:'" +3,3V ±O.3V)*
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address setup to CAS
precharge during WRITE
Column-address hold time
(referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time (CBR REFRESH)
Last CAS going LOW to first CAS
returning HIGH
CAS to output in Low-Z
Data output hold after CAS LOW
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable time
Output Enable time
OE hold time from WE during
READ-MODIFY-WRITE cycle
OE HIGH hold time from CAS HIGH
OE HIGH pulse width
OE LOW to CAS HIGH setup time
-7
-6'
SYM
MIN
tAA
MAX
MIN
-8
MAX
MIN
35
30
MAX
UNITS
40
tACH
15
15
20
ns
ns
tAR
40
40
55
ns
tASC
tASR
tAWD
tCAC
tCAH
0
0
0
0
60
0
0
65
ns
ns
ns
ns
ns
ns
ns
ns
55
15
tCLCH
10
10
10
10
tCLZ
tCOH
tcp
3
5
10
tCAS
tCHR
10,000
20
12
12
10
10
10,000
20
15
12
10
10
10,000
3
5
10
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDHR
tDS
too
5
40
10
40
10
10
40
0
3
toE
tOEH
15
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
toEHC
tOEP
tOES
10
10
5
10
10
5
10
10
5
ns
ns
ns
3
5
10
40
35
15
15
5
40
10
45
12
15
40
0
3
45
5
60
110
45
12
15
15
20
60
0
3
15
20
NOTES
29
21
15,31
29
37
5,30
32
31,41
16,34
31
30
30
5,29
21,29
26,30
22,31
22,31
28,39,41
23,31
27
'60ns specifications are limited to a Vcc range of ±0.15V.
MT4LC16270
W07.pm5 - Rev. 2/95
1-114
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, inc.
ADVANCE
MICRON
I-a
MT4LC16270
256K X 16 DRAM
","""CO","
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+3.3V ±O.3V)*
-7
-6*
AC CHARACTERISTICS
SYM
tOFF
MIN
OE setup prior to RAS during
HIDDEN REFRESH cycle
tORD
0
0
0
ns
tpc
25
30
33
ns
33
tpRWC
72
79
84
ns
33
EDO-PAGE-MODE READ or WRITE
cycle time
EDO-PAGE-MODE READ-WRITE
cycle time
3
MAX
15
Access time from RAS
tRAC
RAS to column-address delay time
15
Row-address hold time
tRAD
tRAH
Column-address to RAS lead time
RAS pulse width
tRAL
tRAS
22
60
RAS pulse width (EDO PAGE MODE)
Random READ or WRITE cycle time
tRASP
tRC
60
110
100,000
RAS to CAS delay time
tRCO
20
45
Read command hold time
(referenced to CAS)
tRCH
0
Read command setup time
Refresh period (512 cycles)
tRCS
0
RAS precharge time
RAS to CAS precharge time
Read command hold time
(referenced to RAS)
10
MAX
MIN
MAX
UNITS
3
15
3
15
ns
70
15
35
10
10,000
10,000
70
100,000
50
130
0
30
80
80
150
100,000
ns
20
60
40
60
to
10
tRRH
0
0
0
tRSH
10
140
15
157
187
85
10
95
12
tRWD
tRWL
IT
tWCH
2
10
Write command hold time
(referenced to RAS)
tWCR
40
Write command setup time
Output disable delay from WE
twcs
tWHZ
twp
0
3
10
50
2
10
40
3
10
17,29
ns
19,26,30
ns
26,29
ms
ns
19
ns
ns
38
105
ns
21
12
ns
ns
26
ns
ns
26,38
26
ns
21,26,29
2
10
50
0
15
ns
ns
ns
60
0
15
8
15
50
18
ns
0
8
NOTES
20,28,31,
41
ns
ns
ns
10
RAS to WE delay time
ns
10,000
35
Write command to RAS lead time
14
0
0
8
ns
40
10
27
70
20
80
15
tRPC
tRWC
Write command pulse width
MIN
tREF
tRP
RAS hold time
READ WRITE cycle time
Transition time (rise or fall)
Write command hold time
60
30
3
10
15
ns
ns
26
*60ns specifications are limited to a Vcc range of ±0.15V.
MT4LC16270
W07.pm5 ~ Rev. 2/95
1-115
•
m
-8
PARAMETER
Output buffer turn-off delay from
CAS or RAS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
c
o
C
JJ
:l=-
s::
ADVANCE
MIC:RON
1-·
•
m
c
o
C
:II
l>
3:
~~~~~ltageS
referenced to Vss.
2. This parameter is sampled. Vee = +3.3V; f = 1 MHz.
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C ~ TA ~ 70°C) is assured.
7. An initial pause of lOOils is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR) before proper device operation is assured. The
eight RAS cycle wake-ups should be repeated any
time the IREF refresh requirement is exceeded.
8. ACcharacteristics assume IT ~ 2.5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS and RAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to one TTL gate and
50pF, VOL = O.8V and VOH = 2.0V.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table,IRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the Q buffer, CAS and RAS must be
pulsed HIGH for !CP.
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. fRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by ICAe.
18. Operation within the IRAD limit ensures that IRCD
(MAX) can be met. lRAD (MAX) is specified as a
reference point only; if IRAD is greater than the
specified lRAD (MAX) limit, access time is controlled
exclusively by IAA.
19. Either IRCH or tRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition; it is not a
reference to VOH or VOL.
MT4LC1627Q,
W07.pm5--Rev.2I95
MT4LC16270
256K X 16 DRAM
",""we,",
21. IWCS, IRWD, IAWD and ICWD are restrictive
operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. If twcs ~ IWCS (MIN),
the cycle is an EARLY WRITE cycle and the data
output will remain an open circuit throughout the
entire cycle. IfIRWD ~ IRWD (MIN), IAWD ~ IAWD
(MIN) and ICWD ~ ICWD (MIN), the cycle is a READ
WRITE and the data output will contain data read
from the selected cell. If neither of the above
conditions is met, the state of Q (at access time and
until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW result in a LATE WRITE (OE-controlled)
cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. During a READ cycle, if OE is LOW then taken HIGH
before CAS goes HIGH, Q goes open. If OE is tied
permanently LOW, a LATE WRITE or READMODIFY-WRITE. operation is not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and
OE=HIGH.
25. All other inputs at Vee -0.2V.
26. Write command is defined as WE going LOW,
27. LATE WRITE and READ-MODIFY-WRITE cycles
must have both laD and IOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide the previously written data if CAS
remains LOW and OE is taken back LOW after tOEH
is met.
28. The DQs open during READ cycles once IOD or IOFF
occur.
29. The first CASx edge to transition LOW.
30. The last CASx edge to transition HIGH.
31. Output parameter (DQx) is referenced to corresponding CAS input, DQ1-DQ8 by CASL and DQ9-DQ16
by CASH.
32. Last falling CASx edge to first rising CASx edge.
33. Last rising CASx edge to next cycle'S last rising CASx
edge.
34. Last rising CASx edge to first falling CASx edge.
35. First DQs controlled by the first CASx to go LOW.
36. Last DQs controlled by the last CASx to go HIGH.
37. Each CASx must meet minimum pulse width.
38. Last CASx to go LOW.
39. All DQs controlled, regardless CASL and CASH.
40. Column-address changed once each cycle.
41. The 3ns minimum is a parameter guaranteed by
design.
1-116
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LC16270
256K x 16 DRAM
",,"oc,,n,
•
READ CYCLE
m
tRP
tRAS
c
o
\
tCSH
~I
'RSH
I~
J
I
IAR
ADDR
VIL
'l"//!t)it
I
lAse ~!
W////,0
ROW
~
I
tRAD
I~~!
V,H
leAS
tRCD
tCLCH
I
I
'RAL
~I
ROW
COLUMN
~~
tRCS
WE
DQ
VIH
VIL
II
I
I
lAA
I
tRAG
NOT"
~
iCAC
~If
~g~
C
::D
OPEN
~OPEN----
VALID DATA
~
_IO_E_
EARLY WRITE CYCLE
C
IRP
tRAS
\
tCSH
CASL and CASH
V IH
VIL
'-Tf=
-J~
tAR
tRAD
~I
I~ ~I
ADDR
~:~
~M
ROW
I
K::'0",0
I
tRAL
'CLCH
-~I
I~I
tACH
f
I
ROW
COLUMN
'CWL
I
I
'RWL
I
I I 'WCR
I~I I~
IWp
J
W/~
I I
I I
~_IDSII~~
tOHR
DQ
~:g~
='
VALID DATA
'mJ DON'T CARE
~
NOTE:
UNDEFINED
1. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
MT4lC16270
W07.pm5- Rev. 2/95
1-117
Micron Technology, Inc., reserves the right to chang€ products or specifications without notice.
©1995, Micron Technology, Inc.
»
s:
ADVANCE
IUIIIC:I=ICN
MT4LC16270
256K X 16 DRAM
,oc~""c,,"
1-·
•
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
m
c
o
tCSH
C
lJ
CASL and CASH
l>
s:
ADDR
WE
~:~
ROW
_
V,H ~~~~rrr!-7770~7""77>rt-+-_ _---,I_ _ _ _- - - - { 1
V IL
I
-
l'----'CI.L.U:L.LLULLLLLLL.LL.ULLt.LL
IAA
I
'CAe
'CL2-
-
DO ~:gt -_----------OPEN---@W~~~t~~;j:----OPEN - - EDO-PAGE-MODE READ CYCLE
RASP
RAs
CASH, CASL
V,H
VIL
V,H
V!L
-
~
I~I
=~
ADDR
WE
V,H
VIL
:J//?t
Ipe
tRCD
I
I~
V,H
VIL
'cSH
tASR
~~
IAR
IRAD
~I
tAAH
ROW
WI/)
COLUMN
!j'/;!/II$I/;!/$
I
I
I
I
I
I
~g~ -
lAA
I
tRAC
I
I
/{IIIIII/)
WIIIIIII
I
I
I
I
~11·tCAH"1
leAH.!
COLUMN
I
b
ICOH_
OPEN
~.I
I
I
'CPA
VALID
DATA
tOES
l@
I
lAA
I
tePA
I
,I 'cLZ-
[_
ROW
IIRC~!~
I
I
lAA
I
COLUMN
I 'CAC
'CAG
:WII/II/$$)!)!;WI)!)!I#/Igj
NOTE:
II
tRAL
~
I
'CLZDQ
ICp
ICAs,ICLCl
~
~
~I I~
tRCS
I
PL
IRSH
(NOTE I)
teAs, felCH
__'c_,p_
tCAS. 'CLCH
VALtD
DATA
~I
toEHC
tCAC
1:-
-
[ - - OPEN
~
toES
-tOFF
VALID
DATA
112£
!I////I/!$iL
~
DON'T CARE
~
UNDEFINED
1. tpc can be measured from falling edge to falling edge of CAS, or from rising edge to rising edge of CAS.
Both measurements must meet the tpc specification.
MT4LCI6270
W07.pmS- Rev. 2195
1-118
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
"c~'oco"
1-·
MT4LC16270
256K X 16 DRAM
'K
•
EDO-PAGE-MODE EARLY-WRITE CYCLE
'RASP
m
c
o
tCSH
teAS. 'CLCH
CASl and CASH
V1H
1--,,'cP'--~1
_.---j,----7+-----~
'----t---{
Vil -
C
:D
l>
3:
WE
V1H JTT7TT7TT77:m-r,'777A
Vil
-LLLLLLLLLLLflLLLlLLL"--~-:-+--:-----fLt.LLl!.-----H--.:it..LhOLLt-----*----;----'k~.
RAS-ONL Y REFRESH CYCLE
(OE, WE = DON'T CARE)
RAS
CASLaodCASH
V,H
VIL _
~IH
IL -
d
'CRP
'ABR
ADDR
NOTE:
VIH-_
VIL _
tRC
~.
·11·
ROW
tRAS
tRAH
'~-b :~
tRP
'k//#/##/#/#/#///II///&,@'$$~
II
ROW
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH; This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC16270
W07.pIl)5- Rev. 2195
1.. 120
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
MT4LC16270
256K X 16 DRAM
"'""0"" "'
•
CBR REFRESH CYCLE
(Addresses; OE = DON'T CARE)
"
'RP
,
"
tRAS
'RP
I
"1 "
-~
,
"
'RAS
~
'RPe
~~ ~
1
C
~ ~
:D
QPEN-----------
DQ
WE
m
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I
~:t
]$II//I/!III1/1////II/11/1/1/11/I/I//!////1/11/II!!I1///1/1/1//11/////II!!/III!Imil/I1&
HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
)~'-------:-:
~'RSH
'R-CD
VIHV'll_
ADDR
'Fl.".'- - -;- -:
(REFRESH)
(READ)
tRAS
tRP
tRAS
'CH--------'R
1..----
~:t::::
NOTE 1
-'OFF
DQx ~gt ------OPEN----~22X===~V~AL~IDD~AT~A==~
CE
NOTE:
OPEN~
too
'OE
~:r -Wlllml#/!u!I/!!$/m!/lllld;;r
_111/11#;/
~
DON'T CARE
~
UNDEFINED
1. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last.
MT4LC16270
1,1 W07.pmS-Rev.2195
1-121
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
»
3:
ADVANCE
II
READ CYCLE
(with WE-controlled disable)
m
C
RAS
VIH
VIL _
0
tCSH
teAP
C
JJ
CAS
tRCD
teAs
tcp
VIH VIL -
l>
3:
tAR
AODR
DQ
NOTE:
::---------OPEN--------1''lN'VX
VALID DATA
['-----,------1
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC16270
W07.pm5~
~g~
Rev. 2/95
1-122
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
MT4LC1M16E5(S)
1 MEG x 16 DRAM
m~"co",,,
1-·
DRAM
C
0
PIN ASSIGNMENT (Top View)
• JEDEC- and industry-standard x16 timing, functions,
pinouts and packages
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All device pins are TTL-compatible
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN and SELF
• BYTE WRlTE and BYTE READ access cycles
• 1,024-cycle refresh (10 roWe, 10 column-addresses)
• Low power, O.3mW standby; 180mW active, typical
• Optional SELF REFRESH mode, with Extended
Refresh rate (8x)
• Extended Data-Out (EDO) PAGE access cycle
• 5V tolerant lias (5.5V maximum VIH level)
OPTIONS
-6
-7
s:
Vee
DOl
D02
D03
D04
Vee
DOS
D06
DOl
D08
NC
1
2
3
4
5
6
7
8
9
10
11
50
49
48
47
46
45
44
43
42
41
40
Vss
D016
D01S
D014
D013
Vss
D012
DOll
DOlO
D09
NC
NC
NC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASL
CASH
• Refresh Rate
Standard 16ms period
SELF REFRESH and 128ms period
• Packages
Plastic TSOP (400 mil)
WE
RAS
NC
NC
AO
A1
A2
A3
Vee
None
S
6E
A9
A8
A7
A6
A5
A4
Vss
TG
• Part Number Example: MT4LCIMI6E5TG-7 S
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tpc
tAA
tCAC
tCAS
-6
-7
110ns
130ns
60ns
70ns
25ns
30ns
30ns
35ns
15ns
20ns
10ns
12ns
GENERAL DESCRIPTION
I
I
The MT4LCI MI6E5(S) is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x16 configuration. The MT4LCIMI6E5(S) has both BYTE WRITE
and WORD WRITE access cycles via two CAS pins (CASL
and CASH). These function in an identical manner to a
single CAS of other DRAMs in that either CASL or CASH
will generate an internal CAS.
The MT4LCIMI6E5(S) CAS function and timing are
determined by the first CAS (CASL or CASH) to transition
MT4lC1M16E5(S)
DI8.pm5-Rev, 2/95
LOW and the last CAS to transition back HIGH. Use of only
one of the two results in a BYTE access cycle. CASL
transitioning LOW selects an access cycle for the lower byte
(DQI-DQ8) and CASH transitioning LOW selects an access
cycle for the upper byte (DQ9-DQI6).
Each bit is uniquely addressed through the 20 address bits
during READ or WRITE cycles. These are entered 10 bits
(AD -A9) at a time. RAS is used to latch the first 10 bits and
CAS the latter 10 bits. The CAS function also determines
whether the cycle will be a refresh cycle (RAS ONLY) or an
active cycle (READ, WRITE or READ WRITE) once RAS
goes LOW.
1-123
C
:D
l>
44/50-Pin TSOP
(D8-5)
MARKING
• Timing
60ns access
70nsaccess
'I
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FEATURES
I
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1 MEG x 16 DRAM •
3.3V, EDO PAGE MODE,
OPTIONAL SELF REFRESH
I
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Micron Technology, Inc., reserves the nght to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
z
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MICRON
1-·
MT4LC1 M16ES(S)
1 MEG x 16 DRAM
,",""COO,,"
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GENERAL DESCRIPTION (continued)
The CASL and CASH inputs internally generate a CAS
signal functioning in an identical manner to the single
CAS input of other DRAMs. The key difference is each
CAS input ( CASL and CASH) controls its corresponding
DQ tristate logic (in conjunction with OE and WE). CASL
controls DQ1 through DQ8 and CASH controls DQ9 through
DQ16. The two CAS controls give the MT4LC1M16E5(S)
both BYTE READ and BYTE WRITE cycle capabilities.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. Taking WE LOW will initiate a WRITE
cycle, selecting DQ1 through DQ16.IfWE goes LOW prior
to CAS going LOW, the output pin(s) remain open (HighZ) until the next CAS cycle. If WE goes LOW after CAS goes
LOW and data reaches the output pins, data-out (Q) is
activated and retains the selected cell data as long as CAS
and OE remain LOW (regardless of WE orRAS). This late
WE pulse results in a READ WRITE cycle.
The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O. Pin direction is controlled by
OEand WE.
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row-addressdefined page boundary. The PAGE cycle is always initiated
with a row-address strobed-in by RAS followed by a column-address strobed-in by CAS. CAS may be toggled-in
by holding RAS LOW and strobing-in different column-
MT4lC1M16E5(S)
DI8.pmS-Rev.2195
addresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the PAGE MODE of operation.
EDO PAGE MODE
The MT4LC1M16E5(S) provides EDO PAGE MODE
which is an accelerated FAST PAGE MODE cycle. The
primary advantage of EDO is the availability of data-out
even after CAS returns HIGH. EDO provides for CAS
precharge time (tcP) to occur without the output data going
invalid. This elimination of CAS output control provides
for pipeline READs.
FAST-PAGE-MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS. EDO-PAGE-MODE DRAMs operate similar to
FAST-PAGE-MODE DRAMs, except data will remain valid
or become valid after CAS goes HIGH during READs,
provided RAS and OE are held LOW. If OE is pulsed while
RAS and CAS are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If OE is toggled or
pulsed after CAS goes HIGH while RAS remains LOW, data
will transition to and remain High-Z (refer to Figure 1).
WE can also perform the function of disabling the output
drivers under certain conditions, as shown in Figure 2.
If the DQ outputs are wire OR'd, OE must be used to
disable idle banks of DRAMs. Alternatively, pulsing WE to
the idle banks during CAS HIGH time will also High-Z the
outputs. Independent of OE control, the outputs will disable after tOFF, which is referenced from the rising edge of
RAS or CAS, whichever occurs last.
1-124
Micron Technology, !nc., reserves the right to change products or specifications without notrce.
©1995, Micron Technology, Inc.
PRELIMINARY
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RAs
~:~=~~--------------------------------------------------------------
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DQ ~:g~-
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_____
!
The DOs go back to
Low-Z if tOES is met.
The DOs remain High-Z
The DOs remain High-Z
until the next CAS cycle
if toEHC is met.
until the next CAS cycle
if tOEP is met.
Figure 1
OUTPUT ENABLE AND DISABLE
RAs
~:~:~'-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _'--_ _ _ _ _ _ _ _ _ _ _ _ __
CAs
::~-
,:/\
i
1----'1
1~1
::t=~~7T7/;!~7T7W7T71#;mr#;7nWj;7/;!TO~'770Wj;=W~=W~=Wj;'7n%<~_COL'--T-'BI~)(I/;i/$//;IdW,J//I0< COT'CI >w//;I$/$~
DQ
i5E
~:g~-------OPEN ---~K=~VA~LI~DD~AT~A~IA}==}------~«==~VA~LI~DD~AT~A~IB}~==) GI~NP~UT~DA~TA~IC~I)------~~
'.~' _;-+--I-~i:~/;
~
I
/
//
~:~------------------~-I--------I----------f--------7'-~-------
r
r
The DOs go to High-Z if WE falls, and if twpz is met,
will remain High-Z until CAS go~s LOW with
WE HIGH (i.e., until a READ cycle.is initiated).
/
WE may be used to disable the DOs to prepare
for input data in an EARLY WRITE cycle. The DOs
will remain High-Z until CAS goes LOW with
WE HIGH (Le., until a READ cycle is initiated).
~
DON'T CARE
~
UNDEFINED
Figure 2
WE CONTROL OF DOs
I
MT4LC1M16E5(S}
D18.pm5-Rev.2/95
1-125
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
z
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MICRON
F·
MT4LC1 M16ES(S)
1 MEG x 16 DRAM
"'"'c'"''''
:E
•
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BYTE ACCESS CYCLE
The BYTE WRITEs and BYTE READs are determined by
the use of CASL and CASH. Enabling CASL will select a
lower BYTE access (DQI-DQ8). Enabling CASH will select
an upper BYTE access (DQ9-DQ16). Enabling both CASL
and CASH selects a WORD WRITE cycle.
C
:xJ
»
s:
1.'--RAS
WORD WRITE
The MT4LCIM16E5(S) may be viewed as two 1 Meg x 8
DRAMs that have common input controls, with the exception of the CAS inputs. Figure 3 illustrates the BYTE WRITE
and WORD WRITE cycles. Figure 4 illustrates BYTE READ
and WORD READ cycles.
---1 ..----
\~---~/
\~-----';-----
\--~/
\'---:---l----1/
WE
STORED
DATA
UPPER BYTE
(009-0016)
OFWORO
---··1
\'-_ _ _ _ _-.J!; -
CASH
LOWER BYTE
(001-008)
OFWORO
LOWER BYTE WAITE
/
--~\_ _ _ _ _ _ _~
~
~
INPUT
DATA
INPUT
DATA
STORED STORED
DATA
DATA
--0>
--0>
----3:-
0
---- -- --
0>
0>
-- ------3:- --- --- ------3>
- --------------3:-
X
-----:;:.
1-----
I~
>~
-----3>
X -----3>
.-----3>
X .-----3:-----3>
X
X -----;:.. 1 -----3>
X -----3> 1 .-----::>
X -- --0> 1 -----p.
X -----3>- 1 -----3>
INPUT
DATA
0
1
0
1
1
1
1
~
1
INPUT
DATA
STORED
DATA
::::::::::::::::::~'
-----------------3> 0
-----------------;;>
1
-----------------3> 1
-----------------3>
-----------------;>
1
1
-----------------3> 1
~ ~ __ ~ ____ -_: ~'
_
x
- -
X -- --- ---
-
3>
-
-3>
X ------ ----------3>
1
X
1
-
-
--
--?
X --------------X --- --- - --
ADDRESSO - - - . + - - - -
1
0
-:;>
1
----:;>
1
ADDRESS 1
x " NOT EFFECTIVE (DON'T CARE)
Figure 3
WORD AND BYTE WRITE EXAMPLE
MT4LC1M18E5(S)
D18.pm5-Rev.2195
1-126
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995.MlcronTechnology.lnc.
PRELIMINARY
MICRON
1-·
MT 4LC1 M16E5(S)
1 MEG x 16 DRAM
.,,""'co"""
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REFRESH
lows for an extended refresh rate of 125fls per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby or BATTERY
BACKUP mode.
The SELF REFRESH mode is terminated by driving RAS
Preserve correct memory cell data by maintaining power
and executing a RAS cycle (READ, WRITE) or RAS refresh
cycle (RAS ONLY, CBR, or HIDDEN) so that all 1,024
combinations of RAS addresses are executed at least every
16ms, regardless of sequence. The CBR REFRESH cycle will
invoke the refresh counter for automatic RAS addressing.
An optional SELF REFRESH mode is also available on the
MT4LC1M16E5 S. The "5" version allows the user the
choice of a fully static low-power data retention mode, or a
dynamic refresh mode at the extended refresh period of
128ms four times longer than the standard 16ms specification.
The optional SELF REFRESH feature is initiated by
performing a CBR REFRESH cycle, and holding RAS LOW
for the specified tRASS. Additionally, the "5" version al-
I-
RAS
UPPER BYTE
(D09-D016)
OF WORD
-I-
WORD READ
\
;-
\
/
~
~
"--------/
STORED
OUTPUT
DATA
DATA
OUTPUT
DATA
1
--3>- 1
-----3>. -
0
-----3>-
-----3;-
0
1
1
1
1
1
-----::;>
1
Z
.-----3>-
0
1
-----3>-
1
-----::>
-----3>
Z
----3>
z
-----3>
Z -----3>Z -----3>Z .-----;,-
z
. ----;,.
Z
-----:;>
ADDRESS 0
0
1
0
0
0
0
.1
!
\
I
r
~
~
LOWER BYTE READ - - -
I
CASH
LOWER BYTE
(D01-D08)
OF WORD
for the completion of any internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all 1,024 rows must
be refreshed within 300fls prior to the resumption of normal
operation.
~
CASL
WE
HIGHforaminimumtimeoftRPS(~tRC).Thisdelayallows
STORED STORED
DATA
DATA
~~
i. ~
-
OUTPUT
OUTPUT
DATA
1
» 1
o .-----3>- 0
-----;;:.. 1
1 -----3>- 1
DATA
--3>-
-----3>-
1
-----3>-
1
----::> Z
Z
Z -----3>- Z
Z .-----3>- Z
Z -----3> Z
Z -----3> Z
z
z
Z
-----;0.-
z
- ---3> Z
-----3>
ADDRESS 1
Z
STORED
DATA
~
~
Z "" High-Z
Figure 4
WORD AND BYTE READ EXAMPLE
1-127
Micron Technology, Inc., reSeN€S the right to change products or specifications without notice.
©1995. Micron TechnologY,lnc.
•
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PRELIMINARY
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MICRON
1-·
MT4LC1M16E5(S)
1 MEG x 16 DRAM
","",CO",,,
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FUNCTIONAL BLOCK DIAGRAM
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WE ~~------------------------------~
CASL~~~0)~~~____________________ft~=::~~~~~=:~~II~1I
c
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CASH
~---4--<)I J
DQ1
••
l>
DQ16
s:
1----.,---0 OE
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
1024 x 1024 x 16
MEMORY
ARRAY
~
~vcc
____--I
+--------<> Vss
MT4LC1M16E5(S)
D18.pm5- Rev. 2/95
1-128
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MIC:RON
1-·
MT4LC1 M 16ES(S)
1 MEG X 16 DRAM
,,,",we,,,,,,
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m
--------------------------~
TRUTH TABLE
ADDRESSES
IR
IC
FUNCTION
RAS
CASL
CASH
WE
OE
Standby
H
H~X
H~X
X
X
X
X
HighcZ
READ: WORD
L
L
L
H
L
ROW
COL
Data-Out
READ: LOWER BYTE
.L
L
H
H
L
ROW
COL
Lower Byte, Data-Out
Upper Byte, High-Z
READ: UPPER BYTE
L
H
L
H
L
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-Out
WRITE: WORD
(EARLY WRITE)
L
L
L
L
X
ROW
COL
Data-In
WRITE: LOWER
BYTE (EARLY)
L
L
H
L
X
ROW
COL
Lower Byte, Data-In
Upper Byte, High-Z
WRITE: UPPER
BYTE (EARLY)
L
H
L
L
X
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-In
READ WRITE
L
L
L
H~L
L~H
ROW
COL
Data-Out, Data-In
1,2
DOs
NOTES
l>
:s:
L
H~L
H-L
H
L
ROW
COL
Data·Out
2
READ
2nd Cycle
L
H~L
H~L
H
L
n/a
COL
Data·Out
2
EDO-PAGE-MODE
1st Cycle
L
H~L
H~L
L
X
ROW
COL
Data-In
1
WRITE
2nd Cycle
L
H~L
H~L
L
X
n/a
COL
Data-In
1
EDO-PAGE-MODE
1st Cycle
L
H~L
H~L
H~L
L~H
ROW
COL
Data-Out, Data-In
1,2
READ-WRITE
2nd Cycle
L
H~L
H~L
H~L
L~H
n/a
COL
Data-Out, Data-In
1,2
HIDDEN
READ
L~H~L
L
L
H
L
ROW
COL
Data·Out
2
REFRESH
WRITE
L~H~L
L
L
L
X
ROW
COL
Data-In
1,3
High-Z
L
H
H
X
X
ROW
n/a
H~L
L
L
H
X
X
X
High-Z
SELF REFRESH
H~L
L
L
H
X
X
X
High-Z
NOTE:
1.
2.
3.
4.
MT4LC1M16E5(S)
D1S.pmS-Rev.2195
4
4
These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active).
These READ cycles may also be BYTE READ cycles (either CASL or CASH active).
EARLY WRITE only.
Only one CAS must be active (CASL or CASH).
1-129
c
C
JJ
1st Cycle
RAS-ONLY REFRESH
m
o
EDO-PAGE-MODE
CBR REFRESH
•
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology, Inc.
PRELIMINARY
z
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UII:::I=ICN
1-·
MT4LC1M16E5(S)
1 MEG x 16 DRAM
,,,"",co",,",
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'Stresses greater than those listed under" Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
deviee at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RA TINGS*
Voltage on Vee pin Relative to Vss .................. -IV to +4.6V
Voltage on Inputs or II 0 pins
Relative to Vss .................................................... -IV to +S.5V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SsoC to +ISO°C
Power Dissipation ............................................................. lW
Short Circuit OutputCurrent ..................................... SOmA
l>
:s:: ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vee
=+3.3V ±0.3V)
PARAMETER/CONDITION .
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs (including NC pins)
VIH
2.0
5.5
V
Input Low (Logic 0) Voltage, all inputs (including NC pins)
VIL
-1.0
0.8
V
II
-2
2
IlA
loz
-10
10
IlA
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV :0; VIN :0; 5.5V
(All other pins not under lest =OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV < VOUT < 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT =-2.0mA)
Output Low Voltage· (lOUT =2.0mA)
MT4LC1M16E5(S)
D18.pm5 - Rev. 2/95
VOL
1-130
NOTES
V
0.4
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, MlcronTechnology,Jnc.
PRELIMINARY
MIC:RON
1-·
MT4LC1M16E5(S)
1 MEG x 16 DRAM
m~"con,,,
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +3.3V ±0.3V)
MAX
SYMBOL
-6
-7
UNITS
Icct
2
2
mA
Icc2
Icc2
(S only)
500
150
500
150
~
~
25
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS Address Cycling: IRC = IRC [MIN])
Icc3
170
155
mA
3,4,26
OPERATING CURRENT: EDO PAGE MODE
Average power supply current
(RAS =VIL, CAS, Address Cycling: IpC = IpC [MIN]; ICP, IASC = 10ns)
Icc4
140
130
mA
3,4,26
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS=VIH: IRC =IRC [MIN])
Iccs
160
145
mA
3,26
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS Address Cycling: IRC = IRC [MIN])
Icc6
150
140
mA
3,5
Icc7
(S only)
300
300
~
3,5
Icca
(S only)
300
300
~
5,27
PARAMETER/CONDITION
STANDBY CURRENT: (TTL) (RAS
=CAS = VI H)
STANDBY CURRENT: (CMOS)
(RAS =CAS = Vcc -0.2V)
REFRESH CURRENT: Extended (S version only)
Average power supply current during BBU REFRESH:
CAS =0.2V or CBR cycling; RAS =IRAS (MIN); WE = Vcc -0.2V;
OE, AO-A9 and DIN = Vcc -0.2V or 0.2V (DIN may be left open);
IRC = 125J.1S (1,024 rows at 125J.1S = 128ms)
REFRESH CURRENT: SELF (S version only)
Average power supply current during SELF REFRi::SH: CBR cycle with
RAS :2: IRASS (MIN) and CAS held LOW; WE = Vcc -0.2V; AO-A9, OE,
and DIN = Vcc -0.2V or 0.2V (DIN may be left open)
MT4LC1M16ES{S)
018.pm5-Rev.2195
1-131
NOTES
•
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Micron Technology, Inc., reseTVes the right to change products or specifications without nOtice.
©1995, Micron Technology, Inc.
»
s::
PRELIMINARY
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II
ftIIIlC:I=ICN
1-·
MT4LC1 M16ES(S)
1 MEG x 16 DRAM
","",eo,,",
CAPACITANCE
SYMBOL
m
PARAMETER
Input Capacitance: Addresses
CI1
o
Input Capacitance: RAS, CASL,CASH, WE, OE
CI2
Input/Output Capacitance: DO
Cia
c
MAX
5
7
7
UNITS
NOTES
pF
2
pF
2
pF
2
C
:IJ
»
s::
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
SYM
Access time from column-address
tAA
Column-address set-up to CAS precharge during WRITE
Column-address hold time (referenced to RAS)
tACH
tAR
Column-address setup time
tASC
Row-address setup time
tASR
tAWD
Column-address to WE delay time
Access time from CAS
ICAH
ICAS
CAS LOW to "don't care" during SELF REFRESH cycle
tCHD
CAS hold time (CBR REFRESH)
tCHR
Last CAS going LOW to first CAS to return HIGH
CAS to output in Low-Z
tCLCH
tCLZ
Dala output hold after next CAS LOW
CAS precharge time
ICOH
tcp
Access time from CAS precharge
CAS to RAS precharge time
ICPA
CAS hold time
ICSH
CAS setup time (CBR REFRESH)
Data-in hold time
tCSR
ICWD
tCWL
IDH
Data-in hold time (referenced to RAS)
Data-in setup time
tDHR
tDS
Output disable
Output Enable
OE hold time from WE during READ-MODIFY-WRITE cycle
OE HIGH hold from CAS HIGH
MT4LC1M16E5(S)
D18.pmS-Rev.2195
ICRP
tOD
IOE
tOEH
IOEHC
1-132
MAX
30
15
45
0
0
55
tCAC
Column-address hold time
CAS pulse width
CAS to WE delay time
Write command to CAS lead time
-7
-6
MIN
MIN
MAX
35
15
55
0
0
65
10,000
12 '
12
15
12
10
0
5
10
ns
ns
ns
20
ns
10,000
ns
ns
10
10
15
15
ns
ns
ns
ns
ns
ns
40
35
5
50
5
35
15
10
45
0
0
NOTES
ns
ns
ns
15
10
10
15
10
10
0
5
10
UNITS
5
55
5
40
15
12
55
0
0
ns
ns
ns
ns
ns
ns
ns
15
15
12
10
Micron Technology, Inc., reserves the right
ns
ns
ns
ns
ns
ns
to
30
30
21
15,32
30
38
5,31
33
32
35
32
31
31
5,30
21,30
26,31
22,32
22,32
29,41
32
28
28
change products or specifications without I'!otice.
©1995, Micron Tachnology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC1 M16ES(S)
1 MEG x 16 DRAM
",""CW,,,",
z
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~
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
OE HIGH pulse width
OE LOW to CAS HIGH setup time
Output buffer turn-off delay
OE setup prior to RAS during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-addreSS hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (EDO PAGE MODE)
RAS pulse width during SELF REFRESH cycle
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read commandsetup time
Refresh period (1,024 cycles)
Refresh period (1,024 cycles) S version
RAS precharge time
RAS to CAS precharge time
RAS precharge time during SELF REFRESH cycle
Read command hold time (referenced to RAS)
RAS hold time
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WEbommand setup time
Output disable delay ·from WE
Write command pulse width
WE pulse width to disable at GAS HIGH
WE hold lime (CBR REFRESH)
WE setup time (CBR REFRESH)
-6
SYM
toEP
tOES
toFF
tORD
tpc
tpRWC
tRAC
tRAD
tRAH
tRAL
tRAS
tRASP
tRASS
tRC
tRCD
tRCH
tRCS
tREF
tREF
tRP
tRPC
tRPS
tRRH
tRSH
tRWC
tRWD
tRWL
IT
twCH
tWCR
twcs
tWHZ
twp
twpz
tWRH
tWRP
MIN
10
5
0
0
25
75
12
10
30
60
60
100
110
14
0
15
60
30
10,000
125,000
45
MIN
10
5
0
0
30
85
12
10
35
70
70
100
130
14
16
128
40
0
110
0
10
150
80
15
2
10
45
0
0
10
10
10
to
MAX
15
70
35
10,000
125,000
50
0
0
0
50
10
16
128
50
0
130
0
12
177
90
15
2
12
55
0
0
12
12
10
10
50
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ils
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
20,32
34
34
14
18
27
17,30
19,26,31
26,30
28
28
27
19
39
21
26
26,39
26
21,26,30
26
26
26
I
MT4LC1M16E5{S)
D18.pmS- Rev. 2195
1-133
•
m
-7
MAX
Micron Technology, Inc., reserves the right to change products or specifications withoutnotice.
©1995, Micron Technology, Inc.
c
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PRELIMINARY
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MICRON
1-·
~~~~~ltages
referenced to Vss.
2. This parameter is sampled. Vee = +3.3V;f = 1 MHz.
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading. Specified values
.are obtained with minimum cycle time and the output
open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C $ TA $ 70°C) is assured. '
7. An initial pause of lOOl1s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR) before proper device operation is assured. The
eight RAS cycle wake-ups should be repeated any
time the lREF refresh requirement is exceeded.
8. AC'characteristics assume IT = 2.5ns.
9, VIH (MIN) and VIL (MAX) are reference levels for.
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VlH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or betweenVIL and VlH) in a monotonic manner.
11. If CAS = VlH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to one TTL gate,
50pF and VOL = 0.8V and VOH = 2.0V.
14. Assumes that tRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in
this table, tRAC will increaseby the amount that
IRCD exceeds the value shown.
15. Assumes that IRCD ~ tRCD (MAX).
16. If CAS is LOW at the falling edge of RAS; Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the Q buffer, CAS must be pulsed
HIGH for tcP.
17. Operation within the tRCD (MAX) limit ensures that
lRAC (MAX) can be met. tRCD (MAX) is specified as
a refetenclT point only; if tRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by ICAe.
18. Operation within the lRAD limit ensures that IRCD
(MAX) can be met. IRAD (MAX) is specified as a
reference point only; if IRAD is greater than the
specified IRAD (MAX) limit, access time is controlled
exclusively by tAA.
MT4lC1M16E5(S)
D18.pm5 - Rev. 2/95
MT4LC1M16E5(S)
1 MEG x 16 DRAM
'CC~"OW" '"
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. 10FF (MAX) defines the time at which the output
achieves the open circuit condition; it is not a
reference to VOH or VOL.
21. twcs, IRWD, IAWD and ICWD are restrictive
operating parameter!, in LATE WRITE and READMODIFY-WRITE cytles only. IfIWCS ~ twcs (MIN),
the cycle is an EARLY WRITE cycle and the data
output will remain an open circuit throughout the
entire cycle. IflRWD ~ IRWD (MIN), IAWD ~ IAWD
(MIN) and ICWD ~ leWD (MIN), the, cycle is a READ
WRITE and the data output will contain data read
from the selected cell. If neither of the above
conditions is met, the state of Q (at access time and
until CAS or OE goes back to VlH) is indeterminate.
OE held HIGH and WE taken LOW after CAS goes
LOW results in a LATE WRITE (OE-controlled) cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. During a READ cycle, if OE is LOW then taken HIGH
before CAS goes HIGH, Q goes open. If OR is tied
permanently LOW, LATE WRITE and READMODIFY-WRITE operations are not permissible and
should not be attempted.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE =LOW and OE =' HIGH.
25. All other inputs at O.2V or Vee -0.2V.
26. Column-address changed once each cycle,
27. When exiting the SELF REFRESH mode, a complete
set of row refreshes should be executed in order to
ensure that the DRAM will be fully refreshed.
Alternatively, distributed refreshes may be utilized,
provided CBRREFRESH cycles are employed.
28. LATE WRITE and READ-MODIFY-WRITE cycles
must have both 10D and toEH met (OE HIGH during
WRITE cycle) in order to ensure thaf the output
buffers will be open during the WRITE cyCle. The
DQs will provide the previously read data if CAS
remains LOW and OE is taken back LOW after 10EH
is met. If CAS goes HIGH prior to OE going back
LOW, the DQs will remain open.
29. The DQs open during READ cycles once taD or 10FF
occur.
1-134
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, fnc.
PRELIMINARY
z
m
~
NOTES (continued)
30. The first CASx edge to transition LOW.
31. The last CASx edge to transition HIGH.
32. Output parameter (DQx) is referenced to corresponding CAS input; DQ1-DQ8 by CASL and DQ9-DQ16
by CASH.
33. Last falling CASx edge to first rising CASx edge.
34. Last rising CASx edge to next cycle's last rising CASx
edge.
35. Last rising CASx edge to first falling CASx edge.
36. First DQs controlled by the first CASx to go LOW.
37. Last DQs controlled by the last CASx to go HIGH.
38. Each CASx must meet minimum pulse width.
39. Last CASx to go LOW.
40. All DQs controlled, regardless CASL and CASH.
•
m
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MT4LC1M16E5(S)
:
D1S.pmS-Rev.2!95
1-135
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
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MICRON
1-·
MT4LC1 M16ES(S)
1 MEG x 16 DRAM
,,,""oceo",,,
•
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'RP
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V,H
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CASL and GASH
V,H
VIL
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tRCD
'AR
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IRAD
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ADDR
V,H
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ROW
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'WCR
I~
'WP
EZI DON'T CARE
~
NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and twRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
2. IOFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MT4LC1MI6E5(S}
DI8.pmS-Rev.2195
1-136
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC1M16E5(S)
1MEGx16DRAM
cc"cC,
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READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
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V1H-
VIL _
CASL and CASH
ADDR
NOTE,;
~ylr
t. Although WE is:a "don't bare" at RAS time'during an access cycle (READ or WRITE),the. system designer
should implementWE'i-iIGH,for,IWRP andtwRH'. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC1M16E!;i(S) ,
D18.pm5,...Rev.2195
'
1-137
Micron Technology, Inc., reserves the right to chal'OlJ products or specificatiOnS without notice.
@1995,MICronTechnology.lne.
PRELIMINARY
z
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MICRON
1-·
MT4LC1 M16E5(S)
1 MEGx16DRAM
e,ce,
~-------------------------
•
EDO-PAGE-MODE .EARLY-WRITE CYCLE
m
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II IRAL
~II 'eAH~1
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ADDR
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COLUMN
COLUMN
COLUMN
ROW
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY~WRITEcycles)
NOTE:
~
DON'T CARE
~
UNDEANED
1. tpc is for LATE WRITE cycles only.
2. Although WE is a "don't care" at RAS time during an access cycle (READ. or WRITE), lhesystem designer
.shouldimplementWE HIGH fortWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC1M16E5(S)
D18.pmS-Rev.2195
>
1-138
Micron Technology, Inc., reservesihe right to change proc:kJcts or specifications without notice.
@1995,MIcronTechnology,Ir:c.
PRELIMINARY
MU::F=lCN
1-·
MT4LC1 M16ES(S)
1 MEGx 16 DRAM
hkC'
z
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•
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
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tpc
tACO
tCAS,tcLCH
tcp
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__:::0 _. '~II'~'~'RAS_LG '~II'---_''7''''=R_
ADDR
Q
~:~ :.J
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ROW
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NOTE:
'RAH
II
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~
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mI
UNDEFINED
1. Although WE isa "dori'fears" ~fRAStimeduringan abcesscycle (READ or WRITE), the system designer
shOuld implerMnt WE HIGH for'WRPand WRH. This design implementation wifl facilitate compatibility with
future EDO DRAMs.
MT4LC1M'UlE5(S)
D18.~-Rev.2/95
1-139
Micron Technology. Inc., reserves the right to change products or specifications wl\hQlJt notice.
@1995, Micron T~hnology. Inc.
PRELIMINARY
z
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MU::I=ICN
1-·
MT4LC1M16E5(S)
1MEGx16DRAM
F""
~--------------------------------------
•
CBR REFRESH CYCLE
(Addresses and OE =DONT CARE)
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(Addresses and OE = DON'T CARE)
NOTE:
MT4lC1M16E5(S)
D18.pm5-Rev.2/95
~
DON'T CARE
~
UNDEFINED
1. 'WRP and 'WRH are for system deSign reference only. The WE signal is actually a "don't care" at RAS time
during a CBR REFRESH. However, WE shoUld be held HIGH at RAS time during a CBR REFRESH to
ensure compatibility with other DRAMs tl1~trequire WE HIGHat RAS time during aCBR R~FRESH.
2, Once 'RASS (MIN) is met and RAS remains LOW, theDAAM,wi,1I enter SELF Al;f~ESH mode.
3. Once tRPS is satisfied, a compete burst of all rows should be executed.
1-140
, MIcron Technology, Inc., reserves the right to change products or specificationS witIiout notice.
4:11995, Micron Technology,. Inc.
PRELIMINARY
MU:: 1=1CN
1-·
MT4LC1 M16E5(S)
1 MEG x 16 DRAM
"'"
(with WE-controlled disable)
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NOTE:
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LC1MtSE5(S)
018.pm5-Rev.2195
1-141
Micron Technolosw, Inc., reserves the right to chal)ge prowdts or speoolCatiOnswithoUt nOtice.
©1995, Micron.Teehr:!ology';Inc.
s:
PRELIMINARY
z:
m
MICRON
1-·
MT4LC1 M16E5(S)
1 MEGx 16 DRAM
, '"
~--------~--~------------------------
•
HIDDEN REFRESH CYCLE 24
(WE == HIGH; OE ="LOW)· .
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(REFRESH)
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MT4LCt~16E5(S)
01S.pmS .. Rev. 2195
.
.
--
...... IOFF
~:gr :::-.-----OPEN-----~~t====~V~AL~ID~DA~TAC===1
I'OE
OE
,
~:r $~//;@dff///$///$/#~To:
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DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or speclflcatlor;ls without notice.·
@1995,MlcronTechnology,(nc.
FPM· 'DRAMs ................. ~ '.......
INFORMATION
,MICRON
ill •••••••••••••••••••••••••••
FPM DRAM PRODUCT SELECTION GUIDE
Optional
Memory
Configuration Access Cycle
3.3V FPM DRAMs
Pari
Number
Access
Time (ns)
Typical Power Dissipation Package/NO. of Pins
Standby
Active
SOJ... TSOP
Page
..
1 Megx4
FPM
MT4LC4001J
60, 70, SO
1mW
100mW
20/26
20/26
2-29
1 Megx4
FPM,S
MT4LC4001J S
60, 70, SO
0.3mW
100mW
20/26
20/26
2-29
4 Megx4
FPM,2KR
MT4LC4M4B1
60, 70
1mW
lS0mW
24/26
24/26
2-65
4 Megx4
FPM,2KR, S
MT4LC4M4B1 S
60, 70
0.3mW
lS0mW
24/26
24/26
2-65
16 Meg x 4
FPM, SKR
MT4LC16M4A7
50, 60, 70
1mW
165mW
34
34
2-79
16 Meg x4
FPM,4KR
MT4LC16M4TS
50,60,70
1mW
225mW
34
34
2-79
2 MegxS
FPM,2KR
MT4LC2MSB1
60, 70
1mW
200mW
2S
2S
2-91
2 Meg x S
FPM,2KR, S
MT4LC2MSB1 S
60, 70
0.3mW
200mW
2S
2S
2-91
S Meg xS
FPM, SKR
MT4LCSMSE1
50,60,70
1mW
170mW
34
34
2-105
S MegxS
FPM,4KR
MT4LCSMSB6
50,60,70
1mW
230mW
34
34
2-105
256Kx 16
FPM,DC
MT4LC16257
60, 70, SO
3mW
150mW
40
40/44
2-131
256K x 16
FPM, DC, S
MT4LC16257 S
60, 70, SO
0.3mW
150mW
40
40/44
2-131
1 Megx16
FPM, DC, 1KR
MT4LC1M16C3
60, 70
3mW
250mW
44/50
2-163
1 Meg x 16
FPM, DC, 1KR, S
MT4LC1M16C3S
60, 70
0.3mW
250mW
-
44/50
2-163
5V FPM DRAMs
4Megx1
FPM
60, 70
3mW
225mW
20/26
20/26
2-1
4 Meg xl
FPM,S
MT4C1004J S
60, 70
O.SmW
225mW
20/26
20/26
2-1
1 Meg x 4
FPM
MT4C400:1J
60, 70
3mW
225mW
20/26
20/26
2-15
1 Meg x 4
FPM, S
MT4C4001J S
60, 70
O.SmW
225mW
20/26
20/26
2-15
1 Meg x 4
FPM,QC
MT4C4004J
60, 70
3mW
225mW
24/26
-
2-41
4 Megx4
FPM,2KR
MT4C4M4B1
60, 70
3mW
250mW
24/26
24/26
2-53
FPM,DC
MT4C16257
60, 70, SO
3mW
375mW
40
40/44
2-117
FPM, DC, 1KR
MT4C1M16C3
60, 70
1mW
350mW
42
-
2-147
256Kx 16
1 Megx16
=
=
. MT4C1004J
FPM FAST PAGE MODE, DC = Dual CAS, QC = Quad CAS, 1KR = 1,024 Refresh, 2KR = 2,04S Refresh,
4KR 4,096 Refresh, SKR = S,192 Refresh, S = SELF REFRESH
4 MEGx1 DRAM
DRAM
5V, STANDARD OR SELF REFRESH •
'TI
"tJ
FEATURES
• 1,024-cycle refresh distributed across 16ms
(MT4CI004J) or 128ms (MT4CI004J S only)
• Industry-standard pinout, timing, functions and
packages
• High-performance CMOS silicon-gate process
• Single +5V ±10% power supply
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN; optional Extended and SELF REFRESH
modes (MT4CI004J S only)
• FAST PAGE MODE access cycle
• Low power, 0.8mW standby; 225mW active, typical
(MT4CI004J S)
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
PIN ASSIGNMENT (Top View)
20/26-Pin SOJ
(OA-1)
D
AO
A1
A2
A3
Vee
-7
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
9
10
11
12
13
18
17
16
15
14
CAS
NC
A9
A8
A7
A6
AS
A4
DC! 1
WED
RASD
NCo
'A10D
2
3
4
5
AOD 9
A10 10
A2 [.J 11
A3 n 12
Vee !.I 13
In
26
Vss
25
24 inCAS
23 fo NC
22
A9
poo
In
18
17
fo A8
In A7
16 !"IA6
l!i liAS
14
II
A4
data reaches the output pin, data-out (Q) is activated and
retains the selected cell data as long as CAS remains LOW
(regardless of WE or RAS). This late WE pulse results in a
READ WRITE cycle.
None
S
FAST PAGE MODE
• Part Number Example: MT4C1004JDJ-6 S
FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined (AO-AI0) page boundary. The FAST
PAGE MODE cycle is always initiated with a row-address
strobed-in by RAS followed by a column-address strobed-in
by CAS. CAS may be toggled-in by holding RAS LOWand
strobing-indifferent column-addresses, thus executing faster
memory cycles. Returning RAS HIGH terminates the FAST
P AGE MODE operation.
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby
level. Also, the chip is preconditioned for the next cycle
during the RAS HIGH time. Memory cell data isretained in
its correct state by maintaining power and executing any
RAS cycle (READ, WRITE) or RAS refresh cycle (RAS
ONLY, CBR, or HIDDEN) so that all 1,024 combinations of
RAS addresses (AO-A9) are executed at least every 16ms for
the MT4CI004J and every 128ms for the MT4CI004J S,
regardless of sequence. The CBR and extended refresh
cycleswill invoke the internal refresh counter for automatic
RAS addressing.
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tpc
tAA
tCAC
tRP
-6
-7
110ns
130ns
60ns
70ns
35ns
40ns
30ns
35ns
15ns
20ns
40ns
50ns
GENERAL DESCRIPTION
The MT4CI004J(S) is a randomly accessed solid-state
memory containing 4, 194,304 bits organized in a xl configuration. During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits, which are entered 11
bits (AO-AI0) at a time. RAS is used to latch the first 11 bits
and CAS the latter 11 bits. READ and WRITE cycles are
selected with the WE input. A logic HIGH on WE dictates
READ mode while a logic LOW on WE dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
falling edge of WE or CAS, whichever occurs last. If WE goes
LOW prior toCAS going LOW, the output pin remains open
(High-Z) until the next CAS cycle. If WE goes LOW after
MT4C1004J{S)
D03.pmS - Rev. 2195
23
22
Vss
a
'Address not used for RAS·ONL Y REFRESH
DJ
TG
• Refresh Rate
Standard 16ms period
SELF REFRESH and 128ms period
26
25
24
WE
RAS
NC
'A10
3:
20/26-Pin TSOP
(OB-1)
2-1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
c
:::JJ
l>
s:
MICRON
1-·
MT4C1004J(S)
4 MEG x 1 DRAM
,,,""occon,
REFRESH
•"
""C
s:
C
:rJ
An optional SELF REFRESH mode is also available. The
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum timeoflRpS (~tRC). This delay allows
for the completion of any internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS-ONLY REFRESH or burst refresh sequence, all rows
must be refreshed within 300l1s prior to the resumption of
normal operation.
"s" version allows the user the choice of a fully static lowpower data retention mode, or a dynamic refresh mode at
the extended refresh period.
The optional SELF REFRESH feature is initiated by
per£orming a CBR REFRESH cycle and holding RAS LOW
for the specified lRASS. Additionally, the "s" version allows for an extended refresh rate of 12511s per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby mode.
»
s:
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
WE~------------------~--------~~~r-
______-'I~~:-~----~
D
)----.r==l----f---o
Q
CAS~--~--------------------+-----4r----~~~
AD
Al
A2
A3
A4
AS
A6
A7
AS
A9
A10
RAS
2048 x 2048
MEMORY
ARRAY
~...,----i
"NOTE:
+---0
Vee
+---0
Vss
1. It WE goes LOW prior to CAS going LOW, EW detection circuit output is a HIGH (EARLY WRITE).
2. If CAS goes LOW prior to WE going LOW, EW detection circuit output is a LOW (LATE WRITE).
MT4C1004J(S)
D03.pm5 - Rev. 2195
2-2
Micron Technology, Inc.. reservsslhe right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
<"
C
MT4C1004J(S)
4 MEG x 1 DRAM
K
TRUTH TABLE .
ADDRESSES
iR
IC
DATA
FUNCTION
ms:'
~
WE"
Standby
H
H-+X
X
X
X
"don't care"
READ
L
L
H
ROW
COL
. "don't care"
EARLY WRITE
L
L
L
ROW
COL
Data-In
High-Z
READ WRITE
L
L
H-+L
ROW
COL
Data-In
Data-Out
L
H-+L
H
ROW
COL
"don't care"
Data-Out
H
COL
"don't care"
, Data-Out
FAST-PAGE-MODE
1st Cycle
Q (Data,Out)
D (!Ja~,ln)
..
High~Z
Data-Out
READ
2nd Cycle
L
" H-"L
FAST-PAGE-MODE
1st Cycle
L
H-+L
L
ROW
COL
Data-In
High-Z
EARLY-WRITE
2nd Cycle.
L
H-+L
L
nla
COL
Data-ln ..
High-Z
FAST-PAGE-MODE
1st Cycle
L
H-+L
H-+L
ROW
COL
READ-WRITE '
2nd Cycle
L
H-+L
H-+L
nla
COL
"'il/a
,
Data-In
Data-Out
Data-In
Data.-Out
L
H
X
ROW
nla
"dol1'tcare"
High-Z
HIDDEN
READ
L-+H-+L
L
H
ROW
COL
"don't care"
Data-Out
REFRESH
WRITE
RAS-ONLY REFRESH
L-+H-+L
L
L
ROW
COL
Data"ln
High-Z
CBRREFRESH
H-+L
L
H
X
X
"don't care"
High-Z
SELF REFRESH
(MT4C1004J S only)
H-+L
L
X
X
"dOA't care"
MT4CWD4J{S)
OOO.pm5 -
R~.
2195
....
H
' .
"
2-3
..
High-Z
,'"
Micron Technology, Inc., r8S61Vesthe right to change products or specifications without notice.'
@1995,Mlcron. Technology.{no.
•
."
"'0
==
C
:lJ
l>
3:
MICRON
1-·
'c
MT4C1004J(S)
4 MEG x 1 DRAM
,
'Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the'operational sections of this specification is ;riot
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability .
ABSOLUTE MAXIMUM RATINGS*
•
."
Voltage on Any Pin Relative to Vss ................. -IV to +7V
Operating Temperature, TA (ambient) ........•O°C to +70°C
Storage Temperature (plastiC) :.......... ,..... -SsoC to +IS0°C
Power. DiSsipation ................ ;.. ,............... :......... :.............. lW
?hort Cireu,t, Output Current........ ,.....•..................... SOmA
."
s:
C
::a
»
3:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED
PC OPERATING CONDITIONS
(Notes: 1, 3, 4, 6, 7) (Vee = +5V f1 0%)
SYMBOL
PARAMETER/CONDITION
.
MIN
MAX
,UNITS
Supply Voltage
Vee
4.5
5.5
V
Input High '(Logie 1) Voltage, all inputs
VIH
2.4
Vec+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
II
-2.
2
IlA
loz
-10
10
IlA
VOH
2.4
INPUT LEAKAGE CURRENT
Any input,OV S;VIN S; 6.5V •
(All otherpinsnot under test = OV)
OUT~UT
".
,
LEAKAGE CURRENT (0 is disabled; OV S; You; S; 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT = -5mA)
Output Low Voltage (lOUT = 4.2mA)
MT4G1004J(S) ";
D03.pinS - Rev. 2J95
NOTES
VOL
2-4
V
0.4
V
Micron Technology, Inc., reserves the right to change products or specifications WIthoUt notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT4C1004J(S)
4 MEG x 1 DRAM
,"
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +5V ±10%)
MAX
SYMBOL
-6
-7
Icc!
2
2
mA,
ICC2
ICC2
(Sonly)
1
200
1
200
mA
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Single Address Cycling: tRC =IRC [MIN])
ICC3
110
100
mA
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS,'Address Cycling: IpC = IpC [MIN])
ICC4
80
70
mA
3,4,
27
REFRESH CURRENT; RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: tRC = IRC [MIN])
Icc5
110
100
mA
3,27
Icc6
110
100
mA
3,5
Icc7
(S.only)
300
300
!1A
'9,5,
7,25
!1A
5,28
PARAMETER/CONDITION
STANDj3Y CURRENT: (TTL)
(RAS = CAS = VIH)
STANDBY CURRENT: (CMOS)
(RAS '" CAS = Vcc -0.2V)
,REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
REFRESH CURRENT: extended (S version only)'
power supply current during Extended Refresh:
,CAS = 0.2V'br CI3R cycling; RAS= IRAS (MIN); WE = Vcc -0.2V;
AO-A:! 0 and DIN = Vcc-0.2V or 0.2V (DIN may be left open); IRC ;: 125jlS
(1 ,024 rows at 125jlS';: 128ms)
,
'
..
UNITS NOTES
."
."
s:
!1A
3,4,
27,
Avera~
REFRESH CURRENT: SELF (S version only)
Average power SUpply current during SELF REFRESH:
CBR cycle with tRAS ~ tRASS(MIN) and CAS held LOW;
WE = Vcc -0.2; AO-A 10 and DIN = Vcc -0.2V or 0.2V
(DIN may be left open)
I'
Ices
(Sonly)
300
300
CAPACITANCE
.
SYMBOL
MAX
UNITS
NOTeS
Input Capacitance:AO-A10, 0
CI1
5
pF
2
Input Capacitance: RAS, ~, WE
CI2
7
pF
2
Output Capacitance: Q
Co
7
pF
2
PARAMETER
MI401004J(S)
D03.pm5 - Rev. 2195 '
2-5
•
Micron Teclvlology. Inc., reserves the right to change products or specifications w{thoutnotioe.
@1995, Micron TechnOlogy, Inc.
C
Jl
»
==
MU::::I=ICN
1-·
MT4C1004J(S)
4 MEG x 1 DRAM
'c,
ELECTRICAL CHARACTERISnCS AND RECOMMENQED AC OPERATING CONDITIONS
•
'TI
-a
s:
c
JJ
»
3:
(Notes: 6, 7, 8, 9,10,11,12,13) (Vee = +5V±10%)
At CHARACTERISTICS.
PARAMETER
-6
'"
Access time from column-address
Column-addresl? hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAB" pulse width
RAS" LOW to "don't care" during SELF REFRESH cycle
;,
CAB" hold 'time (CBR'REFRESH)
CAB" to output in L.ow-Z
CAB" precharge time
Access time from CAS precharge
CAS" to RAS precharge time
"CAS hold time
"CAS setup time (CBR REFRESH)
CAS" to WEdelay time
Wr~e command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
D!lta-in setup time
,
Output buffer turn-off delay
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to-RAS lead time
1lAS pulse width
1lAS pulse width (FAST PAGE MODE)
RAS pulse width during SELF REFRESH cycle
Random READ or WRITE cycle time
'RAS to CAS delaytim,e
Read command hold. time (referenced
Read command setup time.
MT4C1004J(S)
D03.pm5, - Rev. 2/95
to CAS)
MIN
SYM
tAA
tAR
MAX
30
45
0
0
30
tASC
tASR
tAWD
tCAC
.
-7
MIN
MAX
35
10
15
10
10
0
10
10,000
20
15
20
10 .
10
0
10
10,000
35
tePA
tCRP
tCSH
tCSR
teWD
tCWL
tDH
tDHR
tDS
tOFF
tpc
tpRWC
tRAC
tRAD
tRAH
tRAL:
tRAS
tRASP
tRASS
tRC
tRCD
tRCH.
tRCS
-
10
60
10
15
15
10
45
0,
3
35
60
15
10
30
60
60
100
110
20
0
0
15
60
30
40
10 '
70
10
20
20
15
55
0
3
40
70
"
20
70
35
15
10
45
70
70
100
130
20
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns'
21
15
28
5
16
5
21
22
22
20,26
ns
ns
ns
14
18
nS
35
10,000
100,000
NOTES
ns
ns
ns
50
0
0
35
15
teAH
tCAS
tCHD
tCHR
tCLZ
tcp
UNITS
10,000
100,000
ns
ns
ns
50
IJ.S
ns
. ns
ns
ns' _
"
,
25
25
28
17
19
"
Micron Technology, Inc., reserves the right to change products Of specifications wittl!lUt notice.
@1995,MlcronTechnology,lnc.
MICRON
1-·
, "
MT4C1004J(S)
4 MEG x 1 DRAM
,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+5V ±1 0%)
AC CHARACTERISTICS
PARAMETER
·6
SYM
Refresh period (1,024 cycles)
Refresh period (1,024 cycles) S version
RAS precharge time
RAS to "CAS precharge time
RAS precharge time during SELF REFRESH cycle
Read command hold time (referenced to RAS)
RAS hold· time
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or faU)
WE command setup time
Write command hold time
Write'commandhold time (referenced to RAS)
IREF
IREF
IRP
IRPC
IRPS
IRRH
tRSH
IRWC
IRWD
IRWL
Write cOmmand pulse width
WE hold time (CBR REFRESHj
WE setup time (CBRREFRESH)
IWP
twRH
twRP
MT4C1004J(S)
D03.pmS - Rev. 2195
IT
twcs
twCH
IWCR
MIN
·7
MAX
MIN
16
128
40
0
110
0
15
130
60
15
3
0
10
45
10
10
10
50
50
0
130
0
20
155
70
20
3
0
15
55
15
10
10
MAX
UNITS
16
128
ms
ms
ns
ns
ns
ns
ns
ns
ns'·
,ns
50
NOlES
."
."
28
19
21
ns
ns
ns
ns
ns
ns
ns
•
21
24
24
Micron Technology. Inc., reserves the right to change products or specificatlonBAI!llhout notice.
@1995, Micron Technology, Inc.
s:
C
:0
l>
s:
MICRON
1-·
mH"'
K
MT4C1004J(S)
4 MEG x 1 DRAM
NOTES'
•
."
~
3:
c
:c
»
s:
1.
2.
3.
4.
All voltages referenced to Vss.
This parameter is sampled. Vee = 5V ±10%;f = 1 MHz.
Ice is dependent on cycle rates.
Ice is depei::tden,t orioutput loading and cycle rates.
Specified values are obtained with minirp.um cycle
time and the output open,
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C::; TA ::; 70°C) is assured.
7. An initiai pause of 100~ is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WEHIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREFrefresh reqUirement is
exceeded.
8. AC characteristics assume IT = 5ns.
9. VIII (MIN) and VIL (MAX) are reference levels for'
measuring timing ofinput signals. Transition times
are measured between Vm and VIL (or between VIL
and Vm).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and Vm) in a monotonic manner.
11. If CAS = Vm, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, !RAc will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for tcP.
17. Operation within the IRCD (MAX) limit ensures that
!RAc (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAC.
MT4C1004J(S)
003.pm5 - Rev. 2/95
18. Operation within the lRAD (MAX) limit ensures that
!RAe (MIN) and ICAC (MIN) can be met. !RAD
(MAX) is, specified as a reference point only; if IRAD
is greater than the specified!RAD (MAX) limit, then
access time is controlled exclusively by IAA.
19. ,Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circUit condition and is, not, ,
referenced to VOH or VOL.
21. twcs, IRWD, IAWD and tcWD are restrictive
operating parameters in LATE WRITE, READ
WRITE and READ-MODIFY-WRITE cycles only. If
twcs ~ twcs (MIN), the cycle is an EA-RLY WRITE
cycle and the data output will remain anopen circuit
through-out the entire cycle. If IRWD ~ IRWD (MIN),
IAWD ~ IAWD (MIN) and tcWD 2: ICWD (MIN), the
cycle is a READ WRITE and the data output will
contain data read from the selected celL If neither of
the above conditions is met, the cycle is aLATE
WRITE and the state of data-out is indeterminate (at
access time and until CAS goes back to Vm).
22. These parameters are referenced to CAS leading edge
in early WRITE cycles and WE leading edge in late
WRITE or READ WRITE cycles.
23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.
24. twrs and twTH are set up and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of twRP and twRH in the
CBR REFRESH cycle.
25. Extended refresh current is reduced as lRAS is
reduced from its maximum specification during the
extended refresh cycle.
26. The 3ns minimum is a parameter guaranteed by
design.
27. Column-address changed once each cycle.
28. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
Micron Technology. Inc., reserves the right to change products or specifications without notice.
@1995,MicronTechnology,lnc.
READ CYCLE
•
______________~tR~A~S_________________ I~.~--~tR~P-----I
tCSH
"'T1
ICRP
"tJ
S
c
::c
»
s
ADDR
WE
Q
~gt -'---------~-------OPEN------------------~~(~~~~}_-----OPEN -------
EARLY WRITE CYCLE
tRC
------------.,1
VIH
VIL _
'oSH
tCRP
CAS
V,H
VIL
'RCD
-~~
~I'-~~~----~~.
- 1~::~tASR
ADDR
~:t
ROW
ROW
a ~gt-'---------------------~--~-----OPEN~--~-----------------------------
MT4Cl004J{S)
D03.pm5 - Rev. 2/95
2-9
~
DON'T CARE
~
UNDEFINED
Micron Technology. Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
•
-n
"tJ
tCSH
s:
leAS
leRP
C
J]
»
s:
FAST-PAGE-MODE READ CYCLE
------------------------~tRA~S~P------------------------I~
CAS
ADDR
MT4C1004J(S)
D03.pm5 - Rev. 2195
2-10
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
FAST-PAGE-MODE EARLY-WRITE CYCLE
'RP
'RASP
RAs
V,H
VIL
'pc
teSb!
1~Bf-CAs
=J
I
I~
ADDR
tRCD
V,H
VIL
V,H
VIL
::;;/;,x
'AR
tRAD
tRAH~1
!ASR
ROW
tCAS
~
W/;,x
V,H
VIL
~
_'e_P_ _
~
I~I
!
{
I
1
COLUMN
'eWL
I ::~H
II
I~II~I
COLUMN
'eWL'
II
'eWL
~II~I ~II~I
II
~
II
I
II
ROW
II
I
II
tWCR
IRWL
I
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
*tpc / tpRWC
•
1_--,'R",,6,,-H_ _ _ I
~ I--,,'c,,-P_--I ~
1-+-""---_1
OPEN--
"NOTE:
1. tpc is for LATE WRITE only.
MT4C1004J(S}
D03.pm5-Rev.2195
2-11
c
l>
S
~l~ - ' - - . - - - - - - - - - - - - - - - O P E N - - - - - - - - - - - - - -
Ie?
'T1
"'0
:c
I--""'-------Ifm),'
1-+-----+
1
•
S
IRAl.
t CAH _
1_ 'Ase
COLUMN
I
Q
IRSH
_'e_p_ _
I~I I~
~I
WE
~
~
~
DON'T CARE
~
UNDEFINED
MIcron Technology, Inc., reserves the right to change products or specifications without mrtioo.
©1995, Micron Technology, Inc.
RAS-ONLY REFRESH CYCLE
(WE and A 10 = DON'T CARE)
•
."
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s:
~:t~0
CAS
c
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»
s:
~.~
V'H
V1L _
RAS
V'H-~
ADDR
VIL
Q
~g~
tCRP
,II.
tASR
tR_P_~:t~
l~b
_______
tR_AS_ _ _ _ _ _ _ _ _ _ _
,
__
_ _ __
'RAH
ROW
_
-_ - - - - - - - - - - - - - - - - - - - - - - O P E N - - - - - - - - - - - - - - - - - - - - - - -
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
'pc
tCSH
ADDR
tRSH
1-'-='-'--~I
~:t "-!.LLL,, '--__-,-~< 'lLl.'l'-----,------,---------" Y..l.L;'~/ ' -__--,-;-;---' '
s:
REFRESH
•
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C
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s:
lows for an extended refresh rate of 1251ls per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby or extended
refresh mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum timeoftRPS(~tRC). This delay allows
for the completion of any internal refresh cycles that may
be in process at the time of the RAS LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR REFRESH sequence, a burst refresh is not required upon
exiting SELF REFRESH mode. However, if the DRAM
controller utilizes RAS ONLY or burst refresh sequence, all
1,024 rows must be refreshed within 300llS prior to the
resumption of normal operation.
Preserve correct memory cell data by maintaining power
and executing a RAS cycle (READ, WRITE) or RAS refresh
cycle (RAS ONLY, CBR, or HIDDEN) so that all 1,024
combinations of RAS addresses are executed at least every
16ms, regardless of sequence. The CBR REFRESH cycle will
invoke the refresh counter for automatic RAS addressing.
An optional SELF REFRESH mode is also available on
the MT4C4001J(S). The "S" version allows the user the
choice of a fully static low-power data retention mode, or
a dynamic refresh mode at the extended refresh period
of 128ms, eight times longer than the standard 16ms
specifications.
The optional SELF REFRESH feature is initiated by
performing a CBR REFRESH cycle and holding RAS LOW
for the specified lRASS. Additionally, the "S" version al-
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
WE~------------------------~~----------~~~
r-----------~
CAS
DOl
D02
D03
D04
L-________________
~~~----~
OE
AO
Al
A2
SELF REFRESH
OSCILLATOR
and TIMER
A3
A4
AS
A6
A7
A8
A9
RAS
1024 x 1024 x 4
MEMORY
ARRAY
0----1
"NOTE:
-+----0
Vee
.......---0
Vss
1. If WE goes LOW prior to CAS going LOW, EW detection circuit output is a HIGH (EARLY WRITE).
2. If CAS goes LOW prior to WE going LOW, EW detection circuit output is a LOW (LATE WRITE).
MT4C4001J(S)
D09.pm5 - Rev. 2/95
2-16
Micron Technology, Inc., reserves the right to change products or speclflcafions without notice
©1995, Micron Technology, Inc.
TRUTH TABLE
ADDRESSES
IR
IC
DATA-IN/OUT
FUNCTION
RAS
"CAS
WE
nt
Standby
H
H~X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
READ WRITE
L
L
H-L
L~H
ROW
COL
Data-Out, Data-In
DQ1-DQ4
FAST-PAGE-MODE
1st Cycle
L
H-L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H-L
H
L
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H-L
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd Cycle
L
H-L
L
X
n/a
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H-L
H-L
L-H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H-L
H-L
L-H
n/a
COL
Data-Out, Data-In
RAS-ONLY REFRESH
L
H
X
X
ROW
n/a
High-Z
HIDDEN
READ
L-H~L
L
H
L
ROW
COL
Data-Out
REFRESH
WRITE
L-H~L
L
L
X
ROW
COL
Data-In
CBR REFRESH
H-L
L
H
X
X
X
High-Z
SELF REFRESH
(MT4C4001J S only)
H-L
L
H
X
X
X
High-Z
MT4C4001J(S)
D09.pm5 - Rev. 2/95
2-17
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc,
-"
"tJ
s:
C
:xJ
»
s:
MIC:RON
1-·
MT4C4001J(S)
1 MEG x 4 DRAM
"'"'ow",,,
*Stresses greater than those listed under" Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
•
."
\J
Voltage on Any Pin Relative to Vss .................... -IV to +7V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SsoC to + ISO°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... SOmA
s:
C
lJ
»
s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vee = +SV ±1 0%)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
4.S
S.S
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
Vee+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
II
-2
2
flA
loz
-10
10
flA
VOH
2.4
PARAMETER/CONDITION
INPUT LEAKAGE CURRENT
Any input OV ~ VIN S 6.SV
(All other pins not under test OV)
=
OUTPUT LEAKAGE CURRENT (Q is disabled; OV
~
VOUT ~ S.SV)
OUTPUT LEVELS
Output High Voltage (lOUT -SmA)
Output Low Voltage (lOUT 4.2mA)
=
=
MT4C40()1J(S)
D09.pm5-Rev.2I95
VOL
2-18
NOTES
V
0.4
V
Micron Technology, Inc., reserves the right to change products or specFfications without notice,
©1995, Micron Technology, Inc.
MICRON
1-·
MT4C4001 J(S)
1 MEG x 4 DRAM
"'"'OW"""
ELECTRICAL, CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc
=+5V ±10%)
MAX
SYMBOL
-6
-7
Icc1
2
2
mA
Icc2
Icc2
(S only)
1
200
1
200
mA
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Single Address Cycling: IRC =IRC [MIN])
Icc3
110
100
mA
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS =VIL, CAS, Address Cycling: IpC =IpC [MIN])
Icc4
80
70
mA
3,4,
30
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS =VIH: IRC =IRC [MIN])
Iccs
110
100
mA
3,30
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC
Icc6
110
100
mA
3, 5
Icc7
(S only)
300
300
~A
3,5,
28
Icc8
(Sonly)
300
300
~A
5,31
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS =CAS = VIH)
STANDBY CURRENT: (CMOS)
(RAS =CAS = Vcc -0.2V)
=IRC [MIN])
REFRESH CURRENT: Extended (S version only)
Average power supply current during Extended Refresh:
CAS =0.2V or CBR cycling; RAS = tRAS (MIN); WE =Vcc -0.2V;
OE, AO-A9 and DIN =Vcc -0.2V or 0.2V; (DIN may be
left open); tRC = 125~s (1,024 rows at 125~s = 128ms)
REFRESH CURRENT: SELF (S version only)
Average power supply current during SELF REFRESH:
CBR cycle with tRAS ~ tRASS (MIN) and CAS held
LOW; WE =Vcc -0.2; AO-A9, OE and DIN = Vcc -0.2V or 0.2V
(DIN may be left open)
UNITS NOTES
."
"'C
s:
J.lA
3,4,
30
CAPACITANCE
PARAMETER
UNITS
CI1
5
pF
2
Input Capacitance: RAS, CAS, WE, OE
CI2
7
pF
2
Input/Output Capacitance: DQ
CIO
7
pF
2
MT4C4001J(S)
D09.pm5-Rev.2/95
2-19
MIN
NOTES
MAX
Input Capacitance: AO-A9
SYMBOL
-
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995,MicronTechnology,lnc.
C
Jl
l>
s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
•"
'"tJ
s:
C
::D
»
s:
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vee
=+5V ±1 0%)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
-6
SYM
tAA
tAR
Row-address setup time
tASC
tASR
Column-address to WE delay time
tAWD
Access time from CAS
tCAC
Column-address hold time
CAS pulse width
RAS LOW to "don't care" during SELF REFRESH cycle
tCAH
tCAS
Column-address setup time
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
CAS precharge time
Access time from CAS precharge
CAS to
RAS precharge time
CAS hold time
tCHD
tCHR
tCLZ
tcp
tCPA
tCRP
tCSH
CAS to WE delay time
tCSR
tCWD
Write command to CAS lead time
Data-in hold time
tCWL
tDH
Data-in hold time (referenced to RAS)
tDHR
tDS
CAS setup time (CBR REFRESH)
Data-in setup time
Output disable
Output Enable
OE setup prior to RAS during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
tORD
tpc
Access time from RAS
MT4C4001J(S)
D09,pm5-Rev.2!95
45
0
0
55
tpRWC
tRAC
2-20
MIN
10
15
10
10
0
10
10,000
15
20
10
10
0
10
35
10
60
10
40
15
10
45
0
UNITS
35
ns
ns
ns
ns
20
ns
10,000
ns
ns
ns
ns
ns
10
70
10
50
20
15
55
0
15
60
ns
ns
21
15
31
5
16
ns
ns
ns
ns
ns
ns
ns
20
20
20
3
0
40
100
NOTES
ns
40
15
15
15
3
0
35
85
MAX
50
0
0
65
15
tOE
tOEH
tOFF
-7
MAX
30
tOD
OE hold time from WE during READ-MODIFY-WRITE cycle
Output buffer turn-off delay
FAST-PAGE-MODE READ-WRITE cycle time
MIN
20
ns'
ns
ns
ns
ns
ns
5
21
22
22
27
23
26
20,29
ns
ns
70
ns
14
Micron Technology, Inc., reserves the right to change products or specifications without notIce.
©1995, Micron Technology, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, B, 9, 10, 11, 12, 13, 23) (Vee = +5V ±1 0%)
PARAMETER
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
RAS pulse width during SELF REFRESH cycle
Random READ or WRITE cycle time
RAS to CAS delay time
-7
-6
AC CHARACTERISTICS
SYM
tRAD
tRAH
MIN
MAX
MIN
MAX
UNITS
NOTES
15
10
30
15
10
35
ns
ns
18
tRAL
tRAS
30
tRASP
60
60
100
tRASS
tRC
110
IRCD
20
Read command hold time (referenced to CAS)
tRCH
0
Read command setup time
tRCS
0
35
10,000
70
100,000
70
45
100
130
20
10,000
100,000
ns
~s
50
ns
0
0
Refresh period (1,024 cycles)
tREF
16
16
ms
tREF
tRP
128
128
RAS to CAS precharge time
RAS prechargetime during SELF REFRESH cycle
tRPC
ms
ns
ns
Read command hold time (referenced to RAS)
40
50
tRPS
0
110
0
130
tRRH
0
0
ns
15
150
20
ns
ns
RAS hold time
tRSH
READ WRITE cycle time
RAS to WE delay time
tRWC
tRWD
Write command to RAS lead time
tRWL
Transition time (rise or fall)
IT
20
3
< 10
50
3
ns
ns
50
31
19
21
ns
ns
ns
45
55
0
15
ns
ns
21,27
IWRH
0
10
10
tWRP
10
10
ns
ns
ns
25
twCH
tWCR
WE commanq setup time
Write command pulse width
twcs
twp
WE hold time (CSR REFRESH)
WE setup time (CSR REFRESH)
MT4C4001J(S)
15
17
19
15
Write command hold time
Write co
I
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s:
AOW
DO
BE
~~g~ -:-----~--OPEN-~~~~~~~~j---OPEN-
~:t :W//a1/##/$/#//;Iff/;l/;l$#ffi1//##d~
FAST-PAGE-MODE READ CYCLE
I_ _ _ _ _ _ _ _ _ _=IM=SP_ _ _ _ _ _ _ _ _ _ I~
AA
I
'RAG
1
ICAG
'CLZ--OPEN
r-
AA
-
'OFF
ICLZ-
VALID
.~; ~
~
1
tCPA
1_
!CAG
-r-
AA
I
tOFF'
I'
-ICLZVALID
DATA
~ ~
tCPA
'CAG
'I~
-
-'OFF
VALID
DATA
(---
~ ~
~
DDN'TCARE
I2§l UNDEFINED
MT4C4001J(S)
009.pmS - Aev. 2/95
2-24
Micron Technology, Inc., reserves the right to change products or specrficalions without notice.
©i995, Micron Technology, Inc.
MICRON
;C~,
1-'
MT 4C4001 J(S)
1 MEG x 4 DRAM
K
,
FAST-PAGE-MOD£EARLY-WRITECYCLE
•
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FAST-PAGE-MODEREAD-WRITE CYCLE
(LATE WRITE
and READ-MODIFY-WRITE
cycles)
."
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=~
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~:t
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teAS
'RAc
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'0._
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IWp_
,~
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IAWD
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~II~
~-~ - I
los-
I
tCPA
VAUD
VAUD
~~
_ _ too
toe
-
, .' ~"N1~
V~I~l VAUD
_ _ too
toE- -
---
VAUD
~
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lew,
-twp
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:~~ t==-~~~~t==,=- ~~I:- -
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tAWO'~
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~ , teAH"1
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lewD
teAS
~
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COLUMN
. I
tpRWC
~
~1
'ASCI I~
r
--
*tpc
".
'tRCo
1
VALID R : - - - 0 P E N -
_ _ too
~~L
.toE- . -
toEH
~ OON'TCARE
*NOTE:
~
1. IpC is for LATE WRITE only.
MT4C4001J{S) ;
009.pm5 - Rev. 2/95
2-25
UtiDE;l'!NED
Micron Technology, Inc., reserves the right to charQe product& or specifications without notice>
~1995, MiCrOn Technology,lnc.
MICRON
1-·
MT4C4001J(S)
1 MEG x 4 DRAM
"'
RAS-ONLY REFRESH CYCLE
(WE =DON'T CARE)
~ ~r,',
'
_-'t:b
'RP
l,'----'_
,---"'_AS
II '
,
,\'
'ASR
•
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,
'1-
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ADDR
DO
.~,~,---'
t,
~:~ ~=--.;
CAS
"'c
~g~
--
-_-,- - - - - - - - - - - O P E N - - - - - - - - - - - - -
'FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
ADDR'"
,
~I~ _77777-d,----'----'---,l~rnJ._----'---'----,[,7TrT777"'>,.Ir_-'"'--~,[H7l'rrn'7in7T77\
IL
--uLUJ~~--;---"'~CLUl'----.----.---- 'u.LfUJ.LI'''---;-;--;-::::-::--'''4!-'-:L..£Lt.,fLLLLU
D
o ~~::----+--OPEN~---,--~~n------OPEN-----
OE
~I~
::7llA.!L.f.LL.L;""-------'--------------------
f0j DON'T C~RE
~
NOTE:
UNDEFINED
1. Do not drive data prior to tristate.
MT4C4Q01J(S)
D09.pm5 - Rev. 2195 '
2-26
Micron TechnOlogy, Inc., reserves the right to change products or specifications Without notice.
@1995,MiCrohT&Ghnology,lnc.
CBR REFRESH CYCLE
(Addresses and OE DON'T CARE)
=
.
=i'' l
---.!
CAS
~:~_
DO
-
'RP
,
'RPC
<'" • •
II
'WRP
WE
,
II
'RAS
,~" 1
,
'RP
._1 •
1
'RAS
,
•
,I
Y
'RPC
'CSR
'CHR
."
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s:
--~~---
OPEN~·-7i-II______- -
;WRJ1
'WRI'
II
'WRH
~:t -00/$///IJr-- .tw///I&@;1$I;/;)- -\1III//;///$II$lP/;WI//4
SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
NOTE:
f28j
DON'T CARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT4C40Q1J(S}
D09.pm5 - Rev: 2195
2-27
Micron Technology, Inc., reserves the right to change products or specilications without notice.
©1995, Micron Technology, Inc.
C
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UII::I=ICN
1-·
•"
"'0
s:
MT4C4001J(S)
1 MEG x 4 DRAM
"'""oco"'''
HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
(REFRESH)
(READ)
tRAS
tRAS
~:~= ~1
~.~:
.:. __ ~
tc..:;RC=D_ __
C
:a
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ADDR
DO
~:g~
- - - - - - - OPEN-~---_'\IIl()oorn
~:~ 4!/!III!I!!I/!1!!1!!11!!/II/III/II!!/1/&-:=
1_
OE
MT4C4D01J(S)
D09.pm5 -Rev. 2/95
tOE
2-28
VALID DATA
~~--------~
tOD
OPEN-
.1
_&;@Iffi
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the righllo change products or specifications without nolice.
©1995, Micron Technology, Inc.
MIC:RON
1-·
MT4LC4001 J(S)
1 MEG x 4 DRAM
"'" ,
1 MEG x 4 DRAM
DRAM
3.3V, FAST PAGE MODE
OPTIONAL SELF REFRESH
• Single +3.3V ±0.3V power supply
• Low power, 0.3mW standby; 100mW active, typical
• Industry-standard x4 pinout, timing, functions and
packages
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN; optional Extended and SELF REFRESH
modes
• FAST PAGE MODE access cycle
• 1,024-cycle Extended Refresh distributed across 16ms
or128ms
• Low SELF REFRESH current, 100llA tYpical, 150llA
OPTIONS
20/26-Pin SOJ
(DA-1)
D01 ::J-±---~~ Vss
D02
D04
WE
D03
RAS
CAS
A9
20/26-Pin TSOP
(DB-1)
DOl
D02
WE
RAS
A9
Vss
D04
D03
CAS
OE
Vee
-7
-8
None
S
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
DJ
TG
CAS, whichever occurs last. IfWE goes LOW prior to CAS
going LOW, the output pins remain open (High-Z) until the
'
next CAS cycle.
lfWE goes LOW after data reaches the output pins, dataout (Q) is activated and retains the selected cell data as long
as CAS remain,S LOW (regardles~ of WE or RAS). This late
WE pulse results in a READ WRJTEqrcle. The four data
inputs'and four data outputs ru:e rputed through four ~
using common I/O and pin direction is controlled by WE
andOE.
• Part Number Example: MT4LC4001JDF S
KEY TIMING PARAMETERS
,
IRC
110ns
130ns
1SOns
A8
A7
A6
AS,
A4
i:
-6
• Refresh Rate
Standard 16ms period
SELF REFRESH and 128ms period
-6
-7
-8
OE
AO
A1
A2
A3
Vee '"'-'''--_~:..:.r
MARKING
• Timing
60ns access
70ns access
80ns access,
."
PIN ASSIGNMENT (Top View)
(MAX)
SPEED
!RAC
60ns
70ns
80ns
fpC,
3Sris
40ns
4Sns
IAA
30ns
3Sns
40ns
teAC
1Sns
20ns
20ns
IRp
40ns
SOns
60ns,'
FJ\STPAGE M0DE
FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRJTE) within a
row-address-defined page boundary: ThE'! FAST PAGE
MODE cycle is always initiatedwith a row-address strobedin by RAS followed by a column-address strobed-in by
CAS. CAS may be toggled-in by holding RAS LOW and
strobing-indifferent column-addresses, thus executing faster
memory cycles. Returning RAS HIGH terminates the FAST
PAGE MODE operation.
GENERAL DESCRIPTION
TheMT4LC4001J(S) is a randomly accessed solid-state
memorycontaining4,194,304bitsorganizedinax4configuration. RASis used to latch the first 10 bits and CAS the latter
10 bits. READ and WRIT~cles are selected with the WE
input. A logic HIGH on WE dictates READ mode while a
logic LOW 011. WE dictateS WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE or
MT4LC4001J(S)
010.pm5 - Rey: 2(9S
."
FEATURES
2-29
Micron Technology, Inc., reserves the right to change products or specifications wtthout notice,
©1995, Micron Technology, Inc.
c
::c
»
s:
MICRON
MT4LC4001J(S)
1 MEG x 4 DRAM
,,~""
1-·
REFRESH
•
."
"tJ
s:
C
:D
l>
s:
for the specified IRASS. Additionally, the "s" version allows for an extended refresh rate of 12511s per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby or extended
refresh mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum time oftRPS (",IRC). This delay allows
for the completion of any internal refresh cycles that may
be in process at the time of the RAS LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR REFRESH sequence, a burst refresh is not required upon
exiting SELF REFRESH mode. However, if the DRAM
controller utilizes RAS ONLY or burst refresh sequence, all
1,024 rows must be refreshed within 300l1s prior to the
resumption of normal operation.
Preserve correct memQry cell data by maintaining power
and executing a RAS cycle (READ, WRITE) or RAS refresh
cycle (RAS ONLY, CBR, or HIDDEN) .so that all
1,024 combinations of RAS addresses are executed at least
every 16rns, regardless of sequence. The CBR REFRESH
cycle will invoke the refresh counter for automatic RAS
addressing. ,
An optional SELF REFRESH mode is also available on
the MT4C4001 J(S). The "S" version allows the user the
choice of a fully static low-power data retention mode, or
a dynamic,refresh mode at the extended refresh period of
128ms, eight times longer than the standard 16ms specifications.
The optional SELF REFRESH feature is initiated by
performing a CBR REFRESH cycle and holding RAS LOW
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
WE~--------------------~--~----------'-~~
CAS
r---------~
DQ1
DQ2
DQ3
DQ4
~----------------~rm~------~OE
AD
A1
A2
A3
A4
AS
A6
A7
AS
A9
1024 x 1024 x 4
MEMORY
ARRAY
---.0
RAS' <>-_--1
,Vee'
- - - 0 Vss
"NOTE:
1. If WE goes LOW prior to CAS going LOW, EW detection circuit output is a HIGH (EARLY WRITE).
2. If CAS goes LOW prior to WE going LOW,EW detection circuit output is a LOW (LATE WRITE).
MT41..C4001J(S)
010.pm5-Rev.2195
2-30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
TRUTH TABLE
ADDRESSES
IR
IC
DATA-IN/OUT
DQ1-DQ4
!{AS""
"CAS""
WE
or
Standby
H
H----X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
READ WRITE
L
L
H----L
L----H
ROW
COL
Data-Out, Data-In
FUNCTION
FAST-PAGE-MODE
1st Cycle
L
H----L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H----L
H
L
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H----L
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd Cycle
L
H----L
L
X
n/a
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H----L
H----L
L----H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H----L
H----L
L----H
n/a
COL
Data-Out, Da!acln
RAS-ONLY REFRESH
L
H
X
X
ROW
n/a
High-Z
HIDDEN
READ
L----H----L
L
H
L
ROW
COL
Data-Out
REFRESH
WRITE
L----H----L
L
L
X
ROW
COL
Data-In
CBR REFRESH
H----L
L
H
X
X
X
High-Z
SELF REFRESH
H----L
L
H
X
X
X
High-Z
MT4LC4001J(S)
D10.pmS- Rev. 2/95
2-31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•"
"tJ
3:
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:::D
»
s:
*Stresses greater than those listed under "Absolute Maximum Ratings"may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
•
."
""0
s:
C
:rJ
»
s:
Voltage on Any Pin Relative t<;> Vss .............. -1.0V to +4.6V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55°C to +150°C
Power Dissipation ............. ;............................................... lW
Short Circuit Output Current ..................................... 50mA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
V
Supply Voltage
Vcc
3.0
3.6
Input High (Logic 1) Voltage, all inputs
VIH
2.0
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
O.B
V
!1A
!1A
INPUT LEAKAGE CURRENT
Any input OV ~ VIN ~ Vcc+0.5V (All other pins not under test = OV)
II
-2
2
10l
-10
10
High Voltage (lOUT == -2mA)
VOH
2.4
Low Voltage (lOUT = 2mA)
VOL
OUTPUT LEAKAGE CURRENT (0 is disabled; OV
TIL OUTPUT LEVELS
I
I
~
VOUT
~
Vcc+0.5V)
NOTES
V
0.4
V
MAX
SYM
-6
-7
-8
UNITS
Icct
1
1
1
mA
Icc2
Icc2
(S only)
500
100
500
100
500
100
!1A
!1A
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC =IRC [MIN])
Icc3
BO
70
60
mA
3,4,30
OPERATING CURRENT: FAST PAGE MODE
Average power supply current (RAS =VIL, CAS,
Address Cycling: IpC =IpC [MIN])
Icc4
60
50
40
mA
3,4,30
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, cAs = VIH: IRC =IRC [MIN])
Iccs
BO
70
60
mA
3,30
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC
ICC6
BO
70
60
mA
3,5
REFRESH CURRENT: Extended (S version only)
Average power supply current during Extended Refresh:
CAS = 0.2V or CBR cycling; IRAS = IRAS (MIN);
Icc?
WE = Vcc - 0.2V; AO-A9,OE, and DIN = Vcc - 0.2V or 0.2V
(S only)
(DIN may be left open); IRC = 125f.Ls (1,024 rows at 125f.Ls = 12Bms)
150
150
150
!1A
3,5,
REFRESH CURRENT: SELF (S version only)
Average power supply current during SELF REFRESH:
CBR cycle with IRAS ~ IRASS (MIN) and CAS held LOW;
WE = Vcc - 0.2V; AO-A9,OE, and DIN = Vcc - 0.2V or 0.2V
(DIN may be left open)
150
!1A
5,29
PARAMETER/CONDITION
STANDBY CURRENT: (TTL) (RAS
=CAS =VIH)
STANDBY CURRENT: (CMOS)
(RAS =CAS =Other Inputs = Vcc -0.2V)
MT4LC4001J(S)
D10.pmS-Rev.2I95
=IRC [MIN])
2-32
Icc8
(S only)
150
150
NOTES
2B
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
@1995, Micron Technology, Inc.
MICRON
1-·
MT4LC4001J(S)
1MEGx4DRAM
'"
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
Cll
5
pF
2
CI2
7
pF
2
CIO
7
'pF
2
Input Capacitance: AO-A9
,
Input Capacitance: RAS, CAS, WE, OE
.,,"'
,:.
Input/Output Capacitance: DQ
•"
"'C
i:
ELE:CTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS'
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23)(Vcc = +3.3V ±O.3V)
AC CHARACTERISTICS.
PARAMETER
SYM
CAS" hold time (CBR REFRESH)
Output buffer turn-off delay
OE setup prior to AAS during
.,
-6
Access time from column-address
Column-address hold time (referenced to AAS)
.column-address setup time
Row-address setup time
.. Column-address to WE delay time
Access time from CAS
Column-ad<:iress hold.time
CAl) pulse width
AAS LOW to "dori't care" during' j
SELF REFRESH cycle
CAS to outpulln Low-Z ...
CAS .precharge time
.Access time from ~ precharge
CAS to RAS precharge time
CAS.nold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
wrij~ command to CAS lead time
Data-in hold time
Data-in hold time (referenced to AAS)
Data-in setup time
Output disable
Output Enable time
OE hold time from WE during
READ-MODIFY-WRITE cycle
.. '
-'C':.
..
'AA
'AR
'ASC
'ASR
'AWD
'CAC
'CAH
teAS ..
'CHD
MIN
15
10
15
10
10
3
10
'CRP
'CSH
10
60
10
40
15
10
45
0
'CSR
MAX
35
.•.
MAX ...
40 .:.
55
0
0
70
15
20
' 10
10,000
. 10'
'3 '
10...
35
MIN
20
10,000
.,
20
15
20
10
10,000
10
3
.10
45
40
10
.70
10
80
10
lo
.50 .
20
15
55
0
15
15
)It
-8
50
0
0
65
45
0
0
55
'CHR
'CLl
'CP.
'CPA.
'CWO
'CWL
'DH
'DHR
'DS
'OD
tOE
MIN
MAX
30
-7
50
20
15
60
0
20
20
/
20
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
nil
ns
hs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
'OEH
15
'OFF
'ORD
3
0
'PC
35
40
45
ns
'PRWC
85
100
105
ns
20
15
3
0
20
20
3
0
20
ns
ns
. NOTES
21
15
29
5.
16
5
21
22
22
27
23
26
20
HIDDEN REFRESH cycle
FAST-PAGE-MODE
READ or WRITE cycle time
FAST-PAGE-MODE
READ-WRITE cycle time
Access time from AAS
MT4LC4001J(S)
DtO.pm5-Rev.2/95(" '
60
'RAC
2-33
70
C
::D
80
ns
14
Micron Technology, Inc., reserves the right to change products orspecificatlons without notice.
01995, MIcron Technology,lnc.
i:
MICRON
1-
B
"
c
MT4LC4001J(S)
1 MEG x 4 DRAM
w
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
•""
s::
C
:D
~
s::
(Notes: 6, J;
~,9;
10, 1.1,12,13, ?3) (Vee = ;t3.3V to.3V)
AC CHARACTl;illSTICS
PARAMETER
RAS" to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS" pulse width
RAS pulse width (FAST PAGE MODE)
RAS pulse width during
SELF REFRESH cycle
Random READ or WRITE cycle time
RAS to CAS delay time
Readeommand hold timEl(referenqed 10 CAS)
Reaa co·mmand setLip time
Refresh period (1,024 cycles)
Refresh period (1 ;024 cycles) S version
RAS" precharge time
"RPS to CAS precharge time
"RPS prechargelime during
SELF REFRESH cycle
Read command hold, time (referenced to MS)
RAS hold lime
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold tim~
Write command hold lime (referenced to RAS)
WE command setup time
Write command pulse width
..
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT41.£4001J(S)
D10.pm5 -.Rev. 2195
-7
-6
-8
SYM
MIN
MAX
MIN
MAx
MIN
MAX
UNITS
NOTES
'RAD'
'RAH
15
10
30
60
60
100
30
15
10
35
70
70
35
15
10
40
40
18
10,000
100,000
80
80
100
10,000
100,000
ns
ns
ns
ns
ns
IJ.S
29
'RAL
'RAS
'RASP
'RASS
'RC
'RCD
·tRCH
110
20
'RCS
'REF
'REF
'RP
'RPC
'RPS
0
'RRH
'RSH
'RWC
'RWD
'RWL
'T
'WCH
'WCR
'wcs
'WP
'WRIf
'WRP
10,000
100,000
1.00
45
O.
130
20
0
0
40
0
110
50
0
130.
0
15
150
85
15
3
10
45
0
20
180
100
20
3
15
55
0
15
10
10
0
10
10
10
2-34
150
20
0
0
16 .
128
16
128
50
50
60
16
128
60
v
0
150
0
20
50
200
110
20
3
15
60
0
15
10
10
50
ns
ns
ns
ns
ms
ms
ns
ns
.ns
ns
ns
ns
ns
ns
ns
ns·
ns
ns
ns
ns
ns ...
17
19
29
19.
21
21,27
25
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995,MlcronT-echnology, Int:
NOTES
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. 10FF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. twcs, tRWD, tAWD and ICWD are restrictive
operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. If twcs 2: IWCS (MIN),
the cycle is an EARLY WRITE cycle and the data
output will remain an open circuit throughout the
entire cycle. If IRWD 2: IRWD (MIN), IAWD 2: IAWD
(MIN) and ICWD 2: ICWD (MIN), the cycle is a
READ-MODIFY-WRITE and the data output will
contain data read from the selected cell. If neither of
the above conditions is met, the state of data-out is
indeterminate. OE held HIGH and WE taken LOW
after CAS goes LOW results in a LATE WRITE (OEcontrolled) cycle.
22. These parameters are referenced tll C AS'leading edge
in EARLY WRITE cycles and WE leading l'dgl' in
LATE WRITE or READ-MODIFY-WRITE eyell·s.
23. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permissible and should not be attempted.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE =LOW and OE =HIGH.
25. twTS and IWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of twRP and IWRH in the
CBR refresh cycle.
26. LATE WRITE and READ-MODIFY-WRITE cycles
must have both 10D and 10EH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. If OE is
taken back LOW while CAS remains LOW, the DQs
will remain open.
27. The. DQs open during READ cycles once 10D or 10FF
occur. If CAS goes HIGH before OE, the DQs will
open regardless of the state of OE. If CAS stays LOW
while OE is brought HIGH, the DQs will open. If OE
is brought back LOW (CAS still LOW), the DQs will
provide the previously read data.
28. Refresh current increases ifIRAS is extended beyond
its minimum specification.
29. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
30, Column-address changed once each cycle.
1. All voltages referenced to Vss.
2. This parameter is sampled. Vee = +3.3V ±0.3V;
f= 1 MHz.
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100~s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume IT = Sns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured wi.th a load equivalent to two TTL gates
and 100pF. Output reference voltages are 0.8V for a
low level and 2.0V for a high level.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD 2: IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
18. Operation within the IRAD (MAX) limit ensures that
IRCD (MAX) can bemet.tRAD (MAX) is specified as
a reference point only; if IRAD is greater than the
specified lRAD (MAX) limit, then access time is
controlled exclusively by tAA.
MT4LC4001J{S)
D10.pmS- Rev. 2195
2-35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
-n
"0
:s:
C
:rJ
»
s:
NlIC:I=ICN
1-·
MT 4LC4001 J(S)
1 MEG x 4 DRAM
c,"
READ CYCLE
IRC
IRP
tRAS
II
VIH VIL _
RAS
teSH
'"11
IFIRH
tRSH
""tJ
leRP
s::
leAs
tRCD
VIH -
CAS
VIL -
C
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»
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s::
Vu-i -
WE
VIL _
~tgt -'--~-----OPEN------~~~~~}--OPEN---
DO
~:~ -W!/!/!!I!//I/§IIJ/!/I//$$/!$II!///I////JJd
DE
EARLY WRITE CYCLE
lRAe
_
VIH
RAS
VIL
_,-------,jJ
I}----------;-----'[
tCSH
.
CAS
MT4LC4001J(S)
D10.pm5 - Rev. 2195 "
tRCD
--i-~---------+i-----.,-
V,H __
Vil
~~
WE ~t~·-
DE
leRP
"----f-----1
I
IRWL
I
'weR
I I
I I
IWCH
'WP
~:~
2~36
~
DON';-eARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995,MlcronTechnology,lnc.
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRAS
•"
'RP
""C
d=
'CSH
J~
tRCD
:,AR
ADDR
~:r
- 1-"'-.1
::!III/;?t
I
tRAD
~I
~)
ROW
I
WillA
tRAL
ROW
I
IRwn
Irl
II
leWD
II
I
I~II
::~L '1.
tAWD
'AA
IL
tRAC
~AC
I~
'Cl2-
-
C
::D
COLUMN
I
I
tI
I
I~I
I
s:
VALIDDoUT
OPEN
K
~I
~
cl
VALID DIN
OPEN
~
)
FAST-PAGE-MODE READ CYCLE
A
I
I
~LZOPEN
I
tRAQ
tCAC
1:--
~
VALID
DATA
MT4lC4001J(S)
k
"
'VALiD'
tCPA
j~
tCLZ
1:-
2-37
~ ~
VALID
DATA
DATA
~ ~
Dl0.prn5 - Rev. 2/95
I
tCPA
I~ 2t
ICl2-
~
_IOFF
~
1..'2Q..
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Microh Technology, Inc.
l>
s:
FAST-PAGE-MODE EARLY-WRITE CYCLE
•"
RASP
AAS ~[~ -
Ipe
leSH
I~
tRCD
tCRP
CAs ~:r
""tJ
I
=J
s:
I~
C
II
ADDA
~I~
~
IAR
tRAD
IRAH ....
tASR
1
ROW
WII,1i
I
»
s:
WE
COLUMN
I
I
~I
I
~:r
~i
I~I I~
I II
II~
~
l---k-I
!
II
tRAl
1- 'Ase
leAH
COLUMN
eWL
II
I~
'WP
I
DQ
I
F=L
IRSH
_Iep_~
ICAS
I
"I
I~II~I
COLUMN
eWL
II
~
W&
II
ROW
eWL
~!I ~~H ~I'II
~!I ::~H "I
lWCR
I
I.
II
II
'AWL
.1
~:gt
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
RASP
t=L
A
*tPC/tpAWG
leSH
I~
I
=J
1_ IASR
ADDR
~:r
111M
teAs
tACO
~1
'~I I~
IAR
tRAQ
IRAH .... \
ROW :WII/,)
I
I
tRAC
I
2§£
=1
;:d Ii I
1
'AWD
!~
leAH ....
1
COLUMN
-I
1 Ii
ICWl ___
twp' ___
IAWD
ROW
11-'RwL
-- 'CWL
--.twp
IAWD
I~
~ II~IAA
I
I lAAI
II
tRAL
~II
COLUMN
IAWD
I
~
teAS
~
~
COLUMN
~I
-
~
'RSH
tCAS
I~
~ II~
WlUfILIPIUL
--i - -- - --- 1-"
tcLZ-t
OPEN~
~':1~ ~~": T~ l--""t "~
leLZ_
VALID
____ too
=~~
tOE-
--
t~~
VAlI~} VALID
VAUD
____ 'aD
~~I_~
tOE-
-
'eLZ_II:
VALID
VALID
r---- 0PEN -
_ _ _ too
'~~'T
'OE-
--
IOEH
l2:3 DONT CARE
~
"NOTE:
UNDEFINED
1. tpc is for LATE WRITE cycles only.
MT4lC4001J(S)
D10.pm5 -Rev. 2/95
2-38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
CBR REFRESH CYCLE
(Addresses and OE = DON'T CARE)
tRAS
RP
---1'~~
=J
-I-'=-l
=
tcp
~:t
CAS
tCSR
tCHR
-
DQ
'1 '
•
tRAS
RP
"T1
"'C
tRPC~~~t
II
s::
II
OPEN-i-i---------
tWRP IltWRH
tWRP IltWRH
~:t -0'#,@/ffg- -~!IJ//§/!IJ§/$j- --'W/#$/#/$$#/ff#$~
WE
RAS-ONL Y REFRESH CYCLE
(WE = DON'T CARE)
_~
RAS~:~_
CAS
ADDR
DQ
~:~ -.:=0
~:~
~gt
tCRP
tASR
~
'~'
_tRAS_tRC
:1.,
~
~b
'II
,
tRP
.
,tRAH
---"kW/##/!IJ/;/'$/!;I/////////#/a1/#/#;)(~--'---RO-W--
=_,-----RO-W
-.----------OPEN----------
SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
NOTE:
E'Zl
DON'T CARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT4lC4001J(S)
D10.pm5 - Rev. 2195
2-39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
C
:D
»
s::
HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
•
(READ)
(REFRESH)
tRAS
."
RAS
V'H
VIL_
CAS
VIHV'L_
ADDA
~:t::::
"tJ
s:
tRP
tRAS
~:~IRC-D~~IR-'"'~-:~IC-HR--
C
::c
l>
s:
I
tOFF
DQ
~:gr -'----------OPEN'--------d~M--'---------;V;;;;AL:rr;'D"D:DA;:;:TA-;----1
'OE
DE
MT4LC;4001J(S)
D10.pmS-Rev.2I95
~:t -WjltW'j1j1#$j1##$j1j1#j1j1/d~
2-40
OPEN-
10D
J1M####J0
~
DON'TeARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC::RON
"C~"OCOC,,"
1-·
MT 4C4004J
1 MEG x 4 DRAM
,
z
m
1 MEG x 4 DRAM =e
5V, QUAD CAS PARITY,
DRAM
FAST PAGE MODE
FEATURES
• Four independent CAS controls, allowing individual
manipulation to each of the four data input/ output
ports (DQ1 through DQ4).
• Offers a single chip solution to byte-level parity for
36-bit words when using 1 Meg x 4 DRAMs for
memory
• Emulates WRITE-PER-BIT at design-in level, with
simplified timing constraints
• High-performance CMOS silicon-gate process
• Single +5V ±10% power supply
• Low power, 3mW standby; 225mW active, typical
• All inputs, outputs and clocks are TTL-compatible
• 1,024-cycle refresh in 16ms
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
-7
• Packages
Plastic SOJ (300 mil)
DJ
PIN ASSIGNMENT (Top View)
24/26-Pin SOJ
(DA-2)
1
2
WE 3
RAS 4
CAS1 [ 5
CAS2 [ 6
DQ1
DQ2
A9
AD
A1
A2
A3
Vee
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
] Vss
] DQ4
j DQ3
] CAS4
] OE
] CAS3
J
NC
J
AS
]
]
]
]
A7
A6
A5
A4
• Part Number Example: MT4C4004JDJ-7
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
Ipt
-6
-7
nOns
130ns
60ns
70ns
35ns
40ns
tAA
tCAe
tRP
30ns
35ns
15ns
20ns
40ns
50ns
its corresponding DQ tristate logic (in conjunction with OE
and WE) on the Quad CAS DRAM.
During READ or WRITE cycles, each bit is uniquely
addressed through the 20 address bits, which are entered 10
bits (AO-A9) at a time. RAS is used to latch the first 10 bits,
and the first CAS is used to latch the latter 10 bits. READ and
WRITE cycles are selected with the WE input. A logic HIGH
on WE dictates READ mode while a logic LOW on
WE dictates WRITE mode.
During a WRITE cycle, data-in (Dx) is latched by the
falling edge of WE or the first CAS, whichever occurs last.
If WE goes LOW pdor to the first CAS going LOW, the
output pines) remain open until the next CAS cycle. If WE
goes LOW after data reaches the output buffer, data-out (Q)
is activated and retains the selected cell data until the
trailing edge of its corresponding CAS occurs (regardless of
WE or RAS). This late WE pulse results in a READ-WRITE
cycle (OE switching the device from a READ to a WRITE
function). The four data inputs and four data outputs are
routed through four pins using common I/O, with pin
direction controlled by WE and OE.
GENERAL DESCRIPTION
The MT4C4004J is a randomly accessed solid-state
memory containing 4,194,304 bits organizt;d in a x4 configuration. This 1 Meg x 4 DRAM is unique in that each
CAS (CASI through CAS4) controls its corresponding data
I/ a port in conjunction with OE (thatis, CAS 1 controls DQl
I/O port, CAS2 controls DQ2, CAS3 controls DQ3 and
CAS4 controls DQ4).
The best way to view the Quad CAS function is to
imagine the CAS inputs going into an OR gate to obtain an
internally generated CAS signal functioning in an identical
manner to the single CAS input on a standard 1 Meg x 4
DRAM device. The key difference is that each CAS controls
MT4C4004J
D17-.pm5 - Rev. -2/95
2-41
Micron Technology, Inc., reserves the right to change products or specificatlons without notice.
©1995, Micron Technology, Inc.
•"
"'C
s:
C
lJ
l>
s:
MICRON
MT4C4004J
1 MEG x 4 DRAM
m~",co""
1-·
z
m GENERAL DESCRIPTION (continued)
:e
•
."
."
s:
C
:IJ
reduced standby leveL Also, the chip is preconditioned for
the next cycle during the RAS HIGH time. Memory cell data
is retained in its correct state by maintaining power and
executing any RAS cycle (READ, WRITE) or RAS refresh
cycle (RAS ONLY, CBR, or HIDDEN) so that all 1,024
combinations of RAS addresses (AO-A9) are executed at
least every 16ms, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for
automatic RAS addressing.
FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined (AO-A9) page boundary. The FAST
PAGE MODE cycle is always initiated with a row-address
strobed-in by RAS followed by a column-address strobedin by the first CAS. CAS may be toggled-in by holding
RAS LOW and strobing-in different column-addresses,
thus executing faster memory cycles. Returning RAS HIGH
terminates the FAST PAGE MODE operation.
Returning RAS and all four CAS controls HIGH terminates a memory cycle and decreases chip current to a
»
s:
FUNCTIONAL BLOCK DIAGRAM
QUAD CAS
WE
CAS1
DQ1
DQ2
DQ3
DQ4
CAS2
CAS3
CAS4
OE
1024 x 1024 x 4
MEMORY
ARRAY
'NOTE:
--0
Vee
--0
Vss
1. WE LOW prior to first CAS LOW, EW detection circuit output is a 1.
2. First CAS LOW while WE HIGH, EW detection circuit output is a 0; (OE will now determine 1/0).
MT4C4004J
D17.pmS-Rev.2/95
2-42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
z
m
TRUTH TABLE
H~X
X
X
X
X
High-Z
L
H
H
L
ROW
COL
Data-Out
L
H
L
X
ROW
COL
Data-In
L
L
H
H~L
L~H
ROW
COL
Data-Out, Data-In
L
H~L
H
H
L
ROW
COL
Data-Out
CASy
Standby
H
H~X
READ
L
EARLY WRITE
L
READ-WRITE
FAST-PAGE-MODE
1st Cycle
DOx
(DOy always High-Z)
or
CASx
FUNCTION
ADDRESSES
tR
IC
WE
RAS
READ
2nd Cycle
L
H~L
H
H
L
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H~L
H
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd Cycle
L
H~L
H
L
X
nla
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H~L
H
H~L
L~H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H~L
H
H~L
L~H
n/a.
COL
Data-Out, Data-In
L
H
H
X
X
ROW
n/a
High-Z
HIDDEN
RAS-ONLY REFRESH
READ
L~H~L
L
H
H
L
ROW
COL
Data-Out
REFRESH
WRITE
L~H~L
L
H
L
X
ROW
COL
Data-In
H~L
L
H
H
X
X
X
High-Z
CBR REFRESH
MT4C4004J
D17.pmS-Rev.2195
2-43
Micron Technology, Inc., reserves the right to change products or specifications without nollce.
©1995, Micron Technology, Inc.
=E
•
'TI
"'D
:s:
c
JJ
»
:s:
z
m ABSOLUTE MAXIMUM RATINGS*
~
•"
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above thoseindicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Voltage on Any Pin Relative to Vss .................... -IV to +7V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SsoC to +ISO°C
Power Dissipation ............................................................. IW
Short Circuit Output Current ...................................... SOmA
"tJ
3:
C
:ll
»
3:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1,6,7) (Vee = 5V ±10%)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vcc
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
II
-2
2
IJA
10
IJA
INPUT LEAKAGE CURRENT
Any input OV :s; VIN :s; 6.5V
(All other pins not under test = OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV :s; VOUT :s; 5.5V)
NOTES
102
-10
OUTPUT LEVELS
Output High Voltage (lOUT = -5mA)
Output Low Voltage (lOUT = 4.2mA)
VOH
2.4
PARAMETER/CONDITION
SYMBOL
-6
-7
STANDBY CURRENT: (TTL)
(RAS = CAS = VI H)
Icc1
2.5
2.5
mA
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
Icc2
1
1
26
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Single Address Cycling: IRC= IRC [MIN])
Icc3
110
100
mA
3,4,
39
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL; CAS, Address Cycling: IpC= IpC [MIN])
Icc4
80
70
mA
3,4,
39
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC= IRC [MIN])
Icc5
110
100
mA
3,
39
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC= IRC [MIN])
Icc6
110
100
mA
3,5
VOL
V
0.4
V
MAX
MT4C4004J
D17.pm5-Rev.2/95
2-44
UNITS NOTES
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology. Inc.
z
m
CAPACITANCE
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Input Capacitance: AO-A9
CI1
5
pF
2
Input Capacitance: RAS, CAS1-4, WE, OE
CI2
pF
2
Input/Output Capacitance: DO
Cia
7
7
pF
2
:e
•
."
""C
s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9,10,11,12,13,23,25) (Vee =5V ±10%)
AC CHARACTERISTICS
PARAMETER
-6
SYM
MIN
Access time from column-address
Column-address hold time (referenced teRAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time (CBR REFRESH)
Last CAS going LOW to first CAS to return HIGH
CAS to output in low-Z
CAS prechargetime
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable
OE hold time from WE during
READ-MODIFY-WRITE cycle
tAA
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHR
tClCH
tClZ
tcp
toE
tOEH
15
Output buffer turn-off delay
OE setup prior to RAS during
HIDDEN REFRESH cycle
tOFF
tORD
3
0
tpc
35
FAST-PAGE-MODE READ or WRITE cycle time
MT4C4004J
D17.pm5-Rev.2i95
tCPA
tCRP
tCSH
tCSR
tCWD
tCWl
tDH
tDHR
tDS
taD
2-45
-7
MAX
30
45
0
0
55
MIN
50
0
0
65
15
10
15
10
10
0
10
MAX
35
10,000
20
15
20
10
10
0
10
40
35
10
60
10
40
15
10
45
0
10,000
10
70
10
50
20
15
55
0
15
15
20
20
20
15
3
0
40
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
27
21
15,29
27
35
5,25,28
30
29
16,32
29
28
28
5,25,27
21,27
28
22,29
22,29
38
23
37
ns
ns
20,29,38
ns
31
Micron Technology, Inc., reserves the right to change products or specifications witheM notice.
©1995,MicronTechnology, Inc.
C
:::D
»
s:
MICRON
1-·
MT4C4004J
1 MEG x 4 DRAM
"'""''""' "
z
~ ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
'<
•"
-C
3:
c
lJ
»
3:
(Notes: 6, 7, 8, 9, 10, 11, 12, 13,23, 2S) (Vee
AC CHARACTERISTICS
PARAMETER
=SV ±1 0%)
-6
-7
SYM
MIN
tpRWC
tRAC
85
tRAD
15
10
Column-address to RAS lead time
tRAH
tRAL
30
RAS pulse width
tRAS
60
10,000
70
10,000
ns
RASpulse width (FAST PAGE MODE)
Random READ or WRII E cycle time
tRASP
tRC
60
110
100,000
70
130
100,000
ns
ns
RAS to CAS delay time
Read command hold time (referenced to CAS)
tRCD
20
45
20
50
tRCH
0
0
ns
ns
tRCS
tREF
0
0
ns
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Read command setup time
Refresh period (1,024 cycles)
MAX
MIN
MAX
UNITS
NOTES
70
ns
ns
31
14
ns
ns
18
100
60
30
15
35
10
35
16
ns
16
17,27
19,28
27
ms
ns
RAS precharge time
tlAS to CAS precharge time
Read command hold time (referenced to RAS)
tRP
40
50
tRPC
tRRH
0
0
ns
ns
19
RASholdtime
tRSH
0
0
15
20
ns
36
READ-WRITE cycle time
tRWC
150
RAS to WE delay time
tRWD
tRWL
90
15
180
100
ns
ns
21
20
ns
t-r
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
'WCH
3
10
Write command hold time (referenced to RAS)
WE command setup time
'WCR
45
'wcs
Write command pulse width
WE hold time (CBR REFRESH)
'WP
'WRH
WRP
0
10
WE setup time (CBR REFRESH)
MT4C4004J
D17.pm5 -Rev. 2195
2-46
10
10
50
3
15
55
50
ns
ns
36
ns
0
ns
15
10
ns
ns
10
ns
21,27
Micron Technology, Inc., reserves the right to change products or spe lieations without notice.
©1995, Micron Technology, Inc.
NOTES
1.
2.
3.
4.
All voltages referenced to Vss.
This parameter is sampled. Vee = 5V ±10%;f = 1 MHz.
Icc is dependent on cycle rates.
Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial100~s pause is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR) before proper device operation is assured. The
eight RAS cycle wake-ups should be repeated any
time the IREF refresh requirement is exceeded.
8. AC characteristics assume IT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification,
all input signals must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
11. If CASx = VIH, data output is High-Z.
12. If CASx = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that IRCD < tRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that tRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If at least one CAS is LOW at the falling edge of RAS,
Q will be maintained from the previous cycle. To
initiate a new cycle and clear the Q buffer, all four
CAS controls must be pulsed HIGH for tcP.
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by tCAe.
18. Operation within the lRAD (MAX) limit ensures that
IRAC (MIN) and ICAC (MIN) can be met. IRAD
(MAX) is specified as a reference point only; if tRAD is
greater than the specified tRAD (MAX) limit, then
access time is controlled exclusively by tAA.
I
MT4C4OO4J
D17.pm5 ~ Rev. 2/95
19. Either tRCH or IRRH must be satisfied for a READ
cycle.
20. 10FF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL. The 3ns minimum is a
parameter guaranteed by design.
21. IWCS, IRWD, IAWD and tCWD are not restrictive
operating parameters. twcs applies to EARLY
WRITE cycles. If twcs ~ IWCS (MIN), the cycle is an
EARLY WRITE cycle and the data output will remain
an open circuit throughout the entire cycle. If
tRWD ~ IRWD (MIN), tAWD ~ IAWD (MIN) and
ICWD ~ ICWD (MIN), the cycle is a READ-MODlFYWRITE, and the data output will contain data read
from the selected celL If neither of the above
conditions is met, the state of data-out is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. IWCS, IRWD, IAWD and ICWD arc not
applicable in a LATE WRITE cycle.
22. These parameters are referenced to CASx leading
edge in EARLY WRITE cycles and WE leading Cdgl'
in LATE WRITE or READ-MODIFY-WRITE cycles.
23. If OE is tied permanently LOW, READ-WRITE or
READ-MODIFY-WRITE operations are not permissible and should not be attempted.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and OE = HIGH.
25. One to three CAS controls may be HIGH throughout
any given CAS cycle, even though the timing waveforms show all CAS controls going LOW. If one goes
LOW, it must meet all the timing requirements listed or
the data for that I/O buffer may be invalid. At least one
of the four CAS controls must be LOW for a valid CAS
cycle to occur.
26. All other inputs at Vee -0.2V.
27. The first CASx edge to transition LOW.
28. The last CASx edge to transition HIGH.
29. Output parameters (DQx) are referenced to corresponding CASx input; DQ1 by CAS1, DQ2 by CAS2,
etc.
30. Last falling CASx edge to first rising CASx edge.
31. Last rising CASx edge to next cycle's last rising CASx
edge.
32. Last rising CASx edge to first falling CASx edge.
33. First DQx controlled by the first CASx to go LOW.
34. Last DQx controlled by the last CASx to go HIGH.
2-47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
z
m
=E
•""
s:
C
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»
s:
z
m NOTES (continued)
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38. The DQs open during READ cycles once laD or IOFF
occur. If CASx goes HIGH before OE, the DQs will
open regardless of the state of OK If CASx stays LOW
while OE is brought HIGH, the DQs will open. IF OE
is brought back LOW (CASx still LOW), the DQswill
provide the previously read data.
39. Column-address changed once each cycle.
35. Each CASx must meet minimum pulse width.
36. Last CASx to go LOW .
37. LATE WRITE andREAD-MODIFY-WRITE cycles
must have both laD and IOEH met (OEHIGH during
WRITE cycle) in order to ensure thatthe output
buffers will be open during the. WRITE cycle. If OE is
taken back LOW while CAS remains LOW, the DQs
will remain open;
C
::D
»
s:
MT4C4OO4J
D1'7.pmS-Rev.2195
2·48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron TechnologY,lnc.
--------------------------------------------------------READ CYCLE
RC
IRAS
IRP
~I
~
VIH
V 1L _
ROW
•"
I
~I
~
I
IIIRAL
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s:
'W///////////////////////;//
l>
ROW
s::
tRCH
I
I lAA
I
__--------~I=AA-c~~tl~~===:
,
C
:D
I
II~I
COLUMN
I
J~I-I
~:r 4M"$I/;/#I#j,1!I$$#/k I
~I
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IAR
IRAQ
'RCS
WE
leAS
'CLCH
I~~
ADDR
I
IRSH
I
'RCD
~~CAi~
0"11$$##I$;/;
~
EARLY WRITE CYCLE
\'-------
CAS,
ADDR
IRSH
~:r
_7~~I
~i~
'RAD
II III'RAL I
1~~I~~III::leAH·1
=W";0t
W#/a
ROW
I
l :~:~H ~
!t\1}i
II_~
-------------
IReD 'AR
COLUMN
,
'WGR
II
II
II
II
II
II
leWL
I
I
ROW
II
IAWL
EZ1 DON'T CARE
~
UNDEFINED
FIRST TO LAST CAS TO TRANSITION
(minimum of 1, maximum of 4)
T4C4004J
17.pmS-Rev.2I95
m
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-I
\
ICSH
~
Micron Technology, Inc., reserves the nght to change products or specif!cations without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT 4C4004J
1 MEG x 4 DRAM
>C'«"CCC'"'
~ ------------------~-----------------------------------
m
READ-WRITE CYCLE
(LATE-WRITE and READ-MODIFY-WRITE cycles)
•
==
'Rwe
'RP
'RAS
'TI
""C
V
-II
tCSH
s:
)~
I
'RAD
I~~I
l>
s:
ADDR
~:~
::w?;[
~
tRCD
C
::D
ROW
'AR
I
~
I
II
II
~:g~
-
'RWD
I
'eWL
leWD
I
I
'RWL
'AWD
ROW
I
'WP'I
'AA
I
tRAG
I
'ClZ---
DQx
I
,I
COl.UMN
I
I
~
ICAS
tCLCH
II 'RAL
I: ~AH
~I
Irl
I
IRSH
'CAG
1:-
OPEN
VALID DOUT
r
K.
~I
VALID DIN
~I
~
OPEN--
~
FAST-PAGE-MODE READ CYCLE
_
VIH
_c---..,
RAS
VIL
-
11'----:-'e8-H- - - - - - - - : - - ' p e - - - - - - , - - - : - - - - - ' [ I
AA
'RAG
!
ICLZ--DQx
~:g~
=:---
AA
AA
,
tCPA
r-
'CAG
~
~
r- -
IICAC
'CLZ-
VALID
OPEN
I
I~TA
~
tCPAI
-1:- -
I
'OFF
'eLZ -
VALID
'CAG
VALID
to";: ~
~
~ I~
~
-'OFF
>--- OPEN-
DON'T CARE
!8211 UNDEFINED
FIRST TO LAST CAS TO TRANSITION
(minimum of 1, maximum of 4)
MT4C4004J
D17.pm5-Rev.2J95
2-50
Micron Technology, Inc., reserves the right to change products or specifications witho ulnotice
©1995, Micron Technology, Inc
MICRON
1-·
MT4C4004J
1 MEG x 4 DRAM
",'""",0"'"
z
m
FAST-PAGE-MODE EARLY-WRITE CYCLE
RAs
V,H -V
CASx
V,H -V
:e
•"
IL
~
ADDR
"'C
IL
S
IL
II..'=-- ~IIII ::~H·I ~1111::~H _ 1
I.
@Jh
II
I
I I
~
~II
WE
c
:::c
V,H
V
V,H
Vil.
IWCR
j
'WP
II
I
tRWL
I
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE-WRITE and READ-MODIFY·WRITE cycles)
ELl DON'T CARE
!2211
UNDEFINED
FIRST TO LAST CAS TO TRANSITION
(minimum of 1, maximum of 4)
I MT4C4004J
I D17.pm5 - Rev. 2(95
2-51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
»
s
~----------------------------------------------------
m
RAS-ONL Y REFRESH CYCLE
(WE and OE = DON'T CARE)
=e
•
tRe
."
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C
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s:
CBR REFRESH CYCLE 25
(Addresses and OE = DON'T CARE)
HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
(READ)
we
~~tReD
II
~
A~:t:H~SR~
-----.::::-:--_
1-J
(REFRESH)
tAR
'RAD
'RAH
1:-
1IIIj'RAL J II
~ll ~
leAH
'ClCH
I
~~
I
r:zJ
DON'T CARE
~
UNDEFINED
FIRST TO LAST CAS TO TRANSITION
(minimum of 1, maximum of 4)
MT4C4004J
D17.pm5-Rev.2195
2-52
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
4 MEG x 4 DRAM
DRAM
5V, FAST PAGE MODE
FEATURES
• JEDEC- and industry-standard x4 pinout, timing,
functions and packages
• High-performance CMOS silicon-gate process
• Single +5.0V ±10% power supply
• Low power, 3mW standby; 250mW active, typical
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
• 2,048-cycle (11 row-, 11 column-addresses)
OPTIONS
24/26-Pin SOJ
(DA-2)
MARKING
• Timing
60ns access
70ns access
-6
-7
tpc
35ns
40ns
lAA
30ns
35ns
tCAC
l5ns
20ns
tRP
40ns
50ns
DOl
D02
D04
D03
CAS
RAS
NC
A9
Al0
AO
Al
A2
A3
A8
A7
A6
A5
OE
A4
Vss
WE
RAS
NC
OE
A9
Al0
AO
Al
A2
A3
Vee
FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined page boundary. The FAST PAGE
MODE cycle is always initiated with a row-address strobedin by RAS followed by a column-address strobed-in by CAS.
CAS may be toggled-in by holding RAS LOW and strobingin different column-addresses, thus executing faster
memory cycles. Returning RAS HIGH terminates the FAST
PAGE MODE operation.
TheMT4C4M4Blisrandomlyaccessedsolid-statememories containing 16,777,216 bits organized in a x4 configuration. RAS is used to latch the first 11 bits and CAS the latter
11 bits. READ and WRITE cycles are selected with the WE
input. A logic HIGH on WE dictates READ mode while a
logic LOW on WE dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE or
CAS, whichever occurs last. If WE goes LOW prior to CAS
going LOW, the output pins remain open (High- Z) until the
next CAS cycle.
If WE goes LOW after data reaches the output pins, dataout (Q) is activated and retains the selected cell data as long
as CAS remains LOW (regardless of WE or RAS). This late
014.pm5-Rev.2195
D04
D03
CAS
FAST PAGE MODE
GENERAL DESCRIPTION
MT4C4M4B1
DOl
D02
WE pulse results in a READ WRITE cycle. The four data
inputs and the four data outputs are routed through four
pins using common I/O, and pin direction is controlled by
WE and OE.
KEY TIMING PARAMETERS
IRAC
60ns
70ns
Vss
None
• Part Number Example: MT4C4M4BIDJ-6
IRC
nOns
l30ns
Vee
DJ
TG
• Refresh Rate
Standard at32ms period
SPEED
-6
-7
Vss
Vee
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
24/26-Pin TSOP
(DB-2)
Vee
WE
REFRESH
Preserve correct memory cell data by maintaining power
and executing a RAS cycle (READ, WRITE) or RAS refresh
cycle (RAS ONLY, CBR, or HIDDEN) so that all 2,048
combinations of RAS addresses are executed at least
every 32ms, regardless of sequence. The CBR REFRESH
cycle will invoke the refresh counter for automatic RAS
addressing.
2"53
•
'"T1
'"C
PIN ASSIGNMENT (Top View)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
3:
c
:D
l>
3:
PRELIMINARY
•
FUNCTIONAL BLOCK DIAGRAM
(11 row-addresses)
WE~----------------------~~--------~--~~
~--------~
CAS
DQ1
DQ2
DQ3
DQ4
"TI
"tJ
s:
C
:IJ
»
s:
-------oOE
AO
A1
A2
A3
A4
A5
A6
A7
AS
A9
A10
RAS 0-----1
'NOTE:
1. If WE goes LOW prior to CAS going LOW, EW detection circuit output is a HIGH (EARLY WRITE).
2. If CAS goes LOW prior to WE going LOW, EW detection circuit output is a LOW (LATEWRITE).
MT4C4M4B1
D14.pmS-Rev.2/95
2-54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
UII::::I=ICN
1-·
MT4C4M481
4 MEG x 4 DRAM
"'""'00""
TRUTH TABLE
RAs-
CAS
WE
DE
ADDRESSES
tR
IC
Standby
H
H-X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
READ WRITE
L
L
H-L
L-H
ROW
COL
Data-Out, Data-In
FUNCTIDN
DATA-IN/DUT
DQ1-DQ4
FAST-PAGE-MODE
1st Cycle
L
H-L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H-L
H
L
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H-L
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd Cycle
L
H-L
L
X
n/a
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H-L
H--+L
L-H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H-L
H-L
L-H
n/a
COL
Data-Out, Data-In
RAS-ONLY REFRESH
L
H
X
X
ROW
n/a
High-Z
HIDDEN
READ
L-H-L
L
H
L
ROW
COL
Data-Out
REFRESH
WRITE
L-H--+L
L
L
X
ROW
COL
Data-In
H-L
L
H
X
X
X
High-Z
CBR REFRESH
MT4C4M4Bl
D14pmS-Rev.2!95
2-55
Micron Technology, Inc., reserves the right 10 change products or specifications without notlca.
©1995, Micron Technology, Inc.
•
."
."
s:
C
:c
l>
s:
PRELIMINARY
*Stresses greater than those listed under" Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
•
."
"tJ
Voltage on Any Pin Relative to Vss ............. -l.OV to +7.0V
Operating Teinperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SsoC to + lSO°C
Power Dissipation ............................................................. lW
Short Circuit Output Current ...................................... SOmA
s: ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
C
::xJ
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s:
(Notes: 1,6, 7) (Vcc = +5.0V ±1 0%)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vcc
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs (including NC pins)
VIH
2.4
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs (including NC pins)
VIL
-1.0
0.8
V
II
-2
2
IlA
loz
-10
10
IlA
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV S; VIN S; 5.5V
(All other pins not under test =OV)
OUTPUT LEAKAGE CURRENT (0 is disabled; OV S; VOUT S; 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT =-5.0mA)
Output Low Voltage (lOUT =4.2mA)
NOTES
V
VOL
0.4
V
MAX
PARAMETER/CONDITION
SYMBOL
·6
-7
UNITS
STANDBY CURRENT: (TTL)
(RAS =CAS = VI H)
ICC1
2
2
mA
STANDBY CURRENT: (CMOS)
(RAS = CAS = Other Inputs =Vcc -O.2V)
Icc2
1
1
mA
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC =tRC [MIN])
ICC3
120
110
mA
3,4,
28
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS =VIL, CAS, Address Cycling: tpc =tpc [MIN])
Icc4
90
80
mA
3,4,
28
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS =VIH: tRC =tRC [MIN])
Iccs
120
110
mA
3,28
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC
Icc6
120
110
mA
3,5
MT4C4M4B1
D14.pm5 - Rev. 2/95
=tRC [MIN])
2-56
NOTES
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
UII:::RCN
1-·
MT4C4M481
4 MEG x 4 DRAM
"'"'oco"',,,
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: Address pins
CI1
5
pP
2
Input Capacitance: RAS,.CAS,WE, OE
CI2
7
pF
2
Input/Output Capacitance: DQ
Cia
7
pF
2
•"
"tJ
s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vcc
=+5.0V ±1 0%)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay t1me
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time (CBR REFRESH)
CAS to output in low-Z
CAS precharge time (FAST PAGE MODE)
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable
OE hold time from WE during READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OE setup prior to RAS during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle tirne
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
MT4C4M4B1
D14.pmS - Rev. 2/95
-6
SYM
tAA
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHH
tClZ
tcp
tePA
tCRP
tCSH
tCSR
tCWD
tCWl
tDH
tDHR
IDS
IOD
tOE
tOEH
tOFF
tORD
tpc
tpRWC
tRAC
tRAD
2-57
MIN
50
0
0
55
MIN
10,000
20
15
20
15
3
10
35
5
60
5
40
15
10
45
0
3
15
3
0
35
85
15
MAX
35
55
0
0
60
15
10
15
15
3
10
l>
-7
MAX
30
15
15
15
60
30
10,000
40
5
70
5
45
20
15
55
0
3
15
3
0
40
95
15
C
:c
20
20
20
70
35
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
21
15
5
7
16
5
21
22
22
23
20,27
14
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995, Micron Technology, Inc.
s:
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
•
-n
"'CJ
S
C
::rJ
l>
S
(Notes: 6, 7, 8, 9, 10, 11, 12, 13,23) (Vee
=+S.OV ±1 0%)
AC CHARACTERISTICS
PARAMETER
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (2,048 cycles)
RAS precharge time
RAS to CAS precharge time
Read command hold time (referenced to RAS)
RAS hold time
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transistion time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT4C4M4Bl
D14.pm5- Rev. 2/95
-7
-6
SYM
MIN
tRAH
10
30
60
60
110
'RAL
'RAS
tRASP
'RC
tRCD
'RCH
tRCS
'REF
tRP
tRPC
tRRH
tRSH
'RWC
tRWD
'RWL
'T
IWCH
WCR
WCS
'WP
'WRH
tWRP
2-58
20
0
0
MAX
10,000
100,000
45
MIN
10
35
70
70
130
20
0
0
10,000
100,000
50
32
32
40
0
0
15
150
85
15
3
10
45
0
10
10
10
MAX
50
0
0
20
180
95
20
50
3
15
55
0
15
10
10
50
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
17
19
26
21
21
25
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MIC:I=ICN
1-·
c~"
MT4C4M481
4 MEG x 4 DRAM
c
NOTES
1.
2.
3.
4.
All voltages referenced to Vss.
This parameter is sampled. Vee = 5.0V; f = 1 MHz.
Icc is dependent on cycle rates.
Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100~s is required after power-up
followed by eight RAS refresh cycles. (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the lREF refresh requirement is
exceeded.
8. AC characteristics assume IT = Sns.
9. VIR (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIR).
.
10. In addition to meeting the transition rate specification,
all input Signals must transit between VIR and VIL (or
between VIL and VIR) in a monotonic manner.
11. If CAS = VIR, data output is High-Z.
12. If CAS = VIL, data output may contain data from the .
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and lOOpF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAc will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for tcP.
17. Operation within the IRCD (MAX) limit ensUres that
lRAc (MAX) can be met. IRCD (MAX) is specified as.a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by tcAe.
MT4C4M4B1
D14.prn5-Rev.2195
18. Operation within the lRAD (MAX) limit ensures that
lRAc (MIN) and tcAC (MIN) can be met. lRAD
(MAX)is specified as a reference point only; if IRAD is
greater than the specified lRAD (MAX) limit, then
access time is controlled exclUSively by IAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition, and 'is not
referenced to VOH or VOL.
21. twCS,IRWD/AWD and tcWD are not restrictive
operating parameters. twcs applies to EARLY WRITE
cycles. IRWD,tAWD andlCWD apply to READMODIFY-WRITE cycles. If twcs ~ twcs (MIN), the
cycle is an EARLY WRITE CyCle and the data output
will remain an open circuit throughout the entire
cycle. If IRWD ~ IRWD (MIN), IAWD ~ tAWD (MIN)
and ICWD ~ ICWD (MIN), the cycle is a READMODIFY-WRITE and the data output will contain
data read from the selected celL If neither of till' "how
conditions is met, the state of data-out is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. twcs, IRWD, ICWD and IAWD are not
applicable in a LATE WRITE cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE orREAD-MODIFY-WRITE cycles.
23. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permissible and should not be attempted.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle_ In this case, WE = LOW and OE = HIGH.
25. twTs and twTHare setup. and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters arethe inverts of twRP and twRH in the
CBR REFRESH cycle.
.
26. 32ms is 2,048-cycle refresh.
. 27. The 3nsminimum is a parameter guaranteed by
design.
28. Column-address changed once each cycle.
2-59
Micron Technology, Inc., reS6Nes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
."
"'C
s:
C
:lJ
»
s:
PRELIMINARY
MICRON
1-·
"
MT4C4M4B1
4 MEG x 4 DRAM
n,
READ CYCLE
•
'RC
'RP
'RAS
'VIH -
VIL _
RAS
-n
tCSH
tRRH
IRSH
"tJ
leRP
s:
tACO
teAs
V1H VIL -
CAS
'I
C
XI
l>
ROW
ADDR
s::
WE
DO,.
~:~ ---------OPEN-_-----~~~~~~--OPEN--I.
oe
~:t -'1////1/I!II!I!///1//II!!III!J!l!1I1!!/II/!1111I!/I1M-
IOE
EARLY WRITE CYCLE
RAS
V,H
V,L
leSH
tCRP
MT4C4M4Bl
DI4.pm5-Rev.2195
CAS
V,H
V,L
ADDR
V,H
V,L
tACO
teAS
--
ROW
2-60
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves !he right ID change products or speclflcallons wlthout notice'.
@1995,MittonTed'lnology,lnc.
PRELIMINARY
MICRON
1-·
MT 4C4M4B 1
4MEGx4DRAM
'"
,:, READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
•
""S
_,-----'--'-1
-
V,H
RAS
Vil -
,."
"tJ
1'-'-----------;----------1
teSH
'ASH
teRP
3:
teAS
c
:rJ
3>
3:
FAST-PAGE-MODE READ CYCLE
~
P
-
, ·I~ !~RP
'Reo
:Jj
1_
ADDR
~:r
7//M
\
tRP
1
,
tRAS
,
,I
lr
~r~~
~k
OPEN_-:-:-II_________
II
I
!WRr ;WRtl
!WRI' !WRtl
W/I///$III!##I;$
tw/$///$/$/////////IIIIIf:
HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
(READ)
(REFRESH)
tRAS
'RAS
ADOR
DQ
MT4C4M4B1
014.pm5-Rev.2195
2-64
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications withOut notice.
.
Cl1995, Micron Technology, Inc.
MIC::RON
1-·
MT4LC4M481 (S)
4 MEG X 4 DRAM
em Co'"
DRAM
4 MEG x 4 DRAM
3.3V, FAST PAGE MODE,
OPTIONAL SELF REFRESH
FEATURES
• JEDEC- and industry-standard x4 pinout, timing,
functions and packages
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• Low power, 0.3mW standby; 180mW active,
.
typical
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN and SELF
• 2,048-cycle (11 row-, 11 column-addresses)
• Optional SELF'REFRESH mode, with Extended
Refresh rate (4x)
• 5V tolerant I/Os (5.5V maximum VIH level)
OPTIONS
MARKING
• Timing
60ns' access
70ns access
-6
24/26-Pin SOJ
(DA-2)
24/26-Pin TSOP
(DB~2
Vee
Vss
Vee
DOl
D02
D04
D03
CAS
DOl
D02
WE
WE
RAS
NC
RAS
NC
OE
Al0
AO
Al
A2
A3
AS
A7
A6
A5
A4
Al0
AO
Al
Vee
Vss
Vee
A9
)
Vss
DQ4
D03
CAS
OE
A9
A2.
A3
DJ
TG
• Refresh Rate
Standard 32ms period
None
SELF REFRESH and 128ms p e r i o d S
• Part Number Example: MT4LC4M4BIDJ-7 S
KEY TIMINGPARAMETER.S
SPEED
'RC
'RAC
'PC
'AA
'CAC
-6
-7
110ns
l30ns
60ns
70ns
.35ns
40ris
30ns
35ns
l5ns
20ns
'RP
40ns .
50ns
.:
IfWE' goes LOw after data reaches the output pins, dataout (Q) is activated and retains the selected celldata as long
as CAS remains LOW (regardless of WE or RAS). This late
WE· pulse results in a READ WRITE cycle. The four data
inputs and the four data outputs are routed through four
pins using common I/O, and pin direction is controlled by
. ~andOE.
GENERAL DESCRIPTION
The MT4LC4M4B1(S) is a randomly ac~essedsJlid-state
memory containirig 16,777,216 bits qrganized in a x4 configuration. RA$ is used to latch the first 11 bits and CAS the
latter 11 bits. READ and WRITE cycles are selected with the
WE input. A logic' HIGH on WE dictates READ mode
while a logic LOW on WE dictates WRITE mode. During a
WRITE cycle, data-in (D) is latched by the falling edge of
WE or CAS, whichever OCcurs last. If WE goes LOW prior
to CAS going LOW,the outputpirts remain open (High-Z)
until the next CAS cycle.
MT4lC4M4B1(S)
015.pm5 - Rev. 2/95
s:
C
:D
-7
• Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
•"
"'tJ
PIN ASSIGNMENT (Top View)
FAST PAGE MC)DE
FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-definedpage boundary. The FAST PAGE
MODE cycle is always initiated with a row-address strobedin by RAS followed by a column-address strobed-in by
CAS. CAS may be toggled-in by holding RAS LOW and
strobing-indifferentcolumn':addresses, thus executing faster
memory cycles. Returning RASHlGH terminates the FAST
PAGE MODE operation.
Micron Technology, Inc., reserves the right to change products or spec;flqatlona withOUt notice.
@1995,Micri:)nTecnnology,lnc.
l>
s:
UI[::r=lCN
1-·
MT4LC4M481 (5)
4MEGx4DRAM
"
REFRESli
lows for an extended refresh rate of 62.5l1s per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby or extended
refresh mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum time of IRPs (",t&C). This delay allows
for the completion ofany internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all 2,048 rows must
be refreshed within 300l1s prior to the resumption of normal
operation.
Preserve'correct memory cell data oy maintaining power
and executing a RAS cycle (READ, WRITE) or RAS refresh
cycle (RAS ONLY, CBRpr HIDDEN) so that all 2,048
combinations of RAS addresses are executed at least every
32ms, regardless of sequence. The CBRREFRESH cycle will
invoke the refresh counter for automatic RAS addressing.
An optional SELF REFRESH mode is also available on
the MT4LC4M4Bl (S). The "s" version allows the user the
choice of a fully static low-power data retention mode,
or a dynamic refresh mode at the extended refresh period
of 128ms four times longer than the standard 32ms
specification.
The dptional SELF REFRESH feature is initiated by
performing a CBR REFRESH cycle and holding RAS LOW
for the specified !&ASS. Additionally, the "S" version al-
FUNCTIONAL BLOCK DIAGRAM
MT4LC4M481 (11 row-addresses)
WE
D01
D02
D03
DQ4
CAS
OE
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
*NOTE:
t. It WE goes LOW prior to CAS going LOW, EW detection circuit output is a HIGH (EARLY WRITE).
2. It CAS goes 'LOW prior to WE going LOW, EW detection circuit output is a LOW (LATE WRITE).
3. SELF REFRESH oscillator and timer (S version only).
MT4LC4M4B1(S)
D15..pm5,.... Rev. 2195
2-66
Micron Technology. Inc., reserves the right to change products or speclflcatlons without notlce.
©1995, Micron Technology, Inc.
TRUTH TABLE
ADDRESSES
FUNCTION
}lg
"CAS
wt
Of
IR
IC
DATA-IN/OUT
D01-D04
Standby
H
H-X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
READ WRITE
L
L
H-L
L-H
ROW
COL
Data-Out, Data-In
FAST-PAGE-MODE
1st Cycle
L
H-L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H-L
H
L
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H-L
L
X
ROW
COL
Data-In
EARLY-WRITE
2nd Cycle
L
H-L
L
X
n/a
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H-L
H-L
L-H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H-L
H-L
L-H
n/a
COL
Data-Out, Data-In
RAS-ONLY REFRESH
L
H
X
X
ROW
n/a
High-Z
HIDDEN
READ
L-H-L
L
H
L
ROW
COL
Data-Out
REFRESH
WRITE
L-H---+L
L
L
X
ROW
COL
Data-In
CBR REFRESH
H-L
L
H
X
X
X
High-Z
SELF REFRESH
H-L
L
H
X
X
X
High-Z
MT4LC4M4B1(S)
015.pm5 - Rev. 2195
2-67
Micron Technology, Inc" reserves the right to change products or sPecifications without notice.
©1995, Micron Technology, Inc.
•"
."
35:
c
:::D
l>
35:
MIC:RON
1-·
MT4lC4M4B1 (S)
4 MEG x 4 DRAM
"'""ow,""
*Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc supply Relative to Vss ........ -1.0V to +4.6V
Voltage on Inputs or I/O Relative to Vss .... -1.0V to +S.5V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... "SsoC to +lS0°C
Power Dissipation ..................................:........................... lW
Short Circuit Output Current ..................................... SOmA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vee = +3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vcc
3.0
3.6
V
Input High (Logic 1) Voltage, ali inputs (including NC pins)
VIH
2.0
5.5V
V
Input Low (Logic 0) Voltage, ali inputs (including NC pins)
VIL
-1.0
0.8
V
Ii
-2
2
J.LA
102
-10
10
J.LA
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV $; VIN $ 5,5V
(All other pins not under test =OV)
OUTPUT LEAKAGE CURRENT (0 is disabled; OV < VOUT < 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
MT4LC4M481(S)
D15.pm5 - Rev. 2/95
VOL
2-68
NOTES
V
0.4
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC:I=ICN
1-·
MT4LC4M481 (5)
4 MEG x 4 DRAM
, "
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1;6, 7) (Vcc = +3.3V ±0.3V)
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS=' CAS = VIH)
STANDBY CURRENT: (CMOS)
(RAS = CAS = Other Inputs = Vee -0.2V)
OPE~ATING CURRENT: Random READIWRITE
Average poWer supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
OPERATING CURRENT: FAST PAGE MODE
. Average power supply current
(RAS = V1L, CAS, Address Cycling: IpC = IpC [MIN])
MAX
SYMBOL
lcci
-6
-7
2
2
Icc2
Icc2
(S only)
500
150
500
150
jlA
Ic03
120
110
mA
3,4,
29
ICC4
90
80
mA
1··,3,4,
29
UNITS
mA
NOTES
."
!'tJ
s:
IJA
..
REFRESH CURRENT: RAS ONLY
Average pOwer supply current
(RAS Cycling, CAS = VIH: IRC = IRC [MIN])
ICC5
120
110
mA
3,29
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
ICC6
120
110
mA
3,5
ICC7
(Sonly)
300
300
IJA
,3,5
ICC8
(S only)
300
300
M
5
REFRESH CURRENT: Extended (Sversion only)
AVerage pow~r supply current, CAS ~ 0.2V or CBR cycling;
RAS = IRAs (MIN); WE = Vcc -O.2V; AO-A10,OE and
DIN = Vcc - 0.2V or 0.2V (DIN may bf,lleft open); IRC = 62.5J.1S
REFRESH CURRENT: SELF (S version only)
Average power supply current, CBRcycling with RAS ~ IRASS (MIN)
,.and CAS hf,lld LOW; WE = Vcc ~0.2V; AQ-A10,
OE, and DIN = Vec - 0.2V or 0.2V (DIN may be left open)
MT4LC4M4B1(S)
D15.pmS-Aev.2195
•
Micron Technology, Inc., reserves the right to change products or !;IpeciflcatiOfl$ without notipJl.
C>1995, Micron Technology, Inc.
o
:tJ
l>
3:
MU:::r=aCN
1-·
MT4LC4M481 (5)
4MEGx4DRAM
~CC'
CAPACITANCE
•
."
1::J
PARAMETER ..
NOTES
CI1
MAX
5
UNITS
Input Capacitance: Address pins
pF
2
Input Capacitance: RAS, CAS, WE, OE
CI2
7
pF
2
InpuVOutput Capacitance: DO
Cia
7
pF
2
SYMBOL
s:
C
::c
»
s:
ELECtRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vcc = +3.3V ±O.3V)
AC CHARACTERISTICS
PARAMETER
Access time from colLll'Tln-address
Column-address hold time (referenced to RAS)
Column-address setup time .
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time entering SELP,REFRESH
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable
OE hold time from WE during READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OE setup prior to RAS during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
MT4LC4M4B1(S)
D15.pn15 - Rev. 2195
-6
SYM
MIN
lAA
IAR
IASC
IASR
IAWD
teAC
teAH
teAS
ICHD
ICHR
tell
ICp
tePA
ICRP
teSH
teSR
ICWD
ICWL
IDH
IDHR
IDS
toD
IOE
toEH
IOFF
lORD
IpC
IpRWC
lRAC
2-70
-7
MAX
MIN
30
50
0
0
55
15
3
0
35
85
ns
ns'
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nil
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10,000
20
15
20
15
15
3
10
35
5
60
5
40
15
10
45
0
3
UNITS
35
55
0
0
60
15
10
15
15
15
3
10
MAX
15
15
15
60
10,000
40
5
70
5
45
20
15
55
0
3
15
3
0
40
95
20
20
20
70
NOTES
21
15
:
28
5
28
16
5
21
22
22
28
23
20,27
14
Micron Technology, Inc., reserves the right to change products or speclfications without notice.
@1995,MicronTechnofogy,lnc.
MICRON
1-·
MT4LC4M481 (5)
4 MEG x 4 DRAM
,''"''co",,,,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vee = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
-7
-6
SYM
MIN
MAX
MIN
RAS to column-address delay time
Row-address hold time
tRAD
15
30
15
tRAH
10
10
Column-address to RAS lead time
IRAL
tRAS
30
10,000
35
70
10,000
ns
100,000
70
100,000
ns
50
ns
ns
17
19
RAS pulse width
MAX
35
UNITS
NOTES
ns
ns
18
ns
tRASP
60
60
RAS pulse width entering SELF REFRESH
Random READ or WRITE cycle time
tRASS
tRC
100
110
RAS to CAS delay time
tRCD
20
Read command hold time (referenced to CAS)
IRCH
0
0
ns
Read command setup time
tRCS
0
0
ns
Refresh period (2,048 cycles)
Refresh period (2,048 cycles) S version
RAS precharge time
tREF
tREF
tRP
40
50
ms
ns
RAS to CAS precharge time
RAS precharge'time exiting SELF REFRESH
tRPC
tRPS
0
110
0
130
ns
ns
28
Read command hold time (referenced to RAS)
IRRH
0
0
ns
19
RAS hold time
READ WRITE cycle time
tRSH
15
ns
tRWC
tRWD
150
85
15
20
180
RAS to WE delay time
Write command to RAS lead time
tRWL
IT
Transition time (rise or fall)
Write command hold time
IWCH
Write command hold time (referenced to RAS)
IWCR
WE command setup time
Write command pulse width
twcs
twp
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT 4LC4M4Bl (3)
D15.pmS - Rev. 2/95
45
20
32
128
3
10
~
32
128
ns
ns
ns
95
20
50
3
15
ms
50
28
26
21
ns
ns
55
ns
ns
ns
21
10
0
15
tWRH
10
10
ns
25
tWRP
10
10
ns
25
2-71
45
0
."
'"tJ
:s:
RAS pulse width (FAST PAGE MODE)
100
130
•
Micron Technology, Inc .. reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
C
::D
»
s:
NOTES
•
."
-c
s:
c
::D
»
s:
19. Either tRCH or tRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL .
21. twcs, tRWD, tAWD and tCWD are not restrictive
operating parameters. twcs applies to EARLY
WRITE cycles. tRWD, tAWD and tcWD apply to
READ-MODIFY-WRITE cycles. If twcs ~ twcs
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If tRWD ~ tRWD (MIN), tAWD ~
tAWD (MIN) and tCWD ~ tCWD (MIN), the cycle is a
READ-MODIFY-WRITE and the data output will
contain data read from the selected cell. If neither of
the above conditions is met, the state of data-out is
indeterminate. OE held HIGH and WE taken LOW
after CAS goes LOW results in a LATE WRITE (OEcontrolled) cycle. twcs, tRWD, tCWD and tAWD are
not applicable in a LATE WRITE cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permissible and should not be attempted.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE =LOW arid OE =HIGH.
25. twTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of twRP and tWRH in the
CBR REFRESH cycle.
26. 32ms is a 2,048-cycle refresh.
27. The 3ns minimum is a parameter guaranteed by
design.
28. Refresh must be completed within the time of three
external refresh rate periods prior to active use of the
DRAM (provided distributed CBR REFRESH is used
when in the active mode). Alternatively, a complete
set of row refreshes must be executed when exiting
SELF REFRESH prior to active use of the DRAM if
anything other than distributed CBR REFRESH is
used in the active mode.
29. Column-address changed once each cycle.
All voltages referenced to Vss.
This parameter is sampled. Vee = +3.3V; f = 1 MHz.
lee is dependent on cycle rates.
lee is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOfts is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
8. AC characteristics assume tT = Sns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates,
100pF and VOL = 0.8V and VOH = 2.0V.
14. Assumes that IRCD < tRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that tRCD
exceeds the value shown.
15. Assumes that tRCD ~ tRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for tcP.
17. Operation within the tRCD (MAX) limit ensures that
tRAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if tRCD is greater than the
specified tRCD (MAX) limit, then access time is
controlled exclusively by tCAe.
18. Operation within the tRAD (MAX) limit ensures that
IRAC (MIN) and tCAC (MIN) can be met. tRAD
(MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, then
access time is controlled exclusively by tAA.
1.
2.
3.
4.
MT4LC4M4Bl(S)
D1S.pmS-Rev.2/95
2-72
Micron Technology, Inc., reserves the right to change products or specifications Without nolice.
©1995, Micron Technology, !nc.
MICRON
1-·
MT4LC4M481 (5)
4 MEG x 4 DRAM
"'"'ocoo"",
READ CYCLE
•"
,I
tRP
tRAS
ICSH
tRRH
IRSH
J'
teRp
tRCD
ADDR
~:l2
.
.
I~ ~I ~rTTT7A
~
ROW
I
.-
~
I
I
tRAL
~I
lAse -]
,I
~
COLUMN
I
1
ROW
~
tRCS
/1111/
I
I
.V&'I7II7/I;7I&'I71111
tAA
I
tRAG
1
teAe
~
~k
OPEN
OPEN-
VALID DATA
~
DE
s:
1
IRAO
V,H
VIL
"tJ
tCAS
~
~:t. W,1#/#$ ,1#$1$1111,1/$#/$11111ijjijJ?l
EARLY WRITE CYCLE
tRC
,'----1
leSH
ADDR
~:~
-
,,-_R--;OW_ _~''LLLLL/M
I'
MT4LC4M4Bl(S)
D1S.pmS - Rev. 2/95
~;0(,-----_R_OW_ _
COLUMN
tCWL
I
I
IRWL
I
I
tweR
2-73
~
DONTCARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology,lnc
C
::tJ
»
s:
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
•
tRAS
."
-
'RP
d::
."
ICSH
5
~J'
cJ]
»
ADDR
5
~:t
'CRP
~
'ACD
'AR
'AAD
I
~!
r-rrrn!~~1
7////M
W////;,l
ROW
1
I
.1
IRCS
I
ROW
I
~II
'AWD
.~I
-"I
leWD
I
'AWD
'WP
I
I
'AA
'RAG
J
I
'CAG
~
'elZ
-
I
I
-
I
'RAl
COLUMN
I
I
~
I
I~I
I
_!~~I
VALID DOUT
OPEN
K
~I
I~
VAUDD 1N
OPEN--
~
FAST-PAGE-MODE READ CYCLE
l----------------~'R=Asp~---------------I~
AA
I
I
'CLZOPEN
AA
I
tRAC
'CAG
1:-
I~
2i.
'CLZVALID
DATA
MT4LC4M4B1(S)
b.
'OFF
-
2-74
I
'CLZ-
~
DATA
~ ~
D15.pmS- Rev. 2/95
AA
I
tCPA
~ ~
'CPA
'CAG
1:--
VALID
DATA
~ ~
-tOFF
f--c--
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
FAST-PAGE-MODE EARLY·WRITE CYCLE
."
"C
s:
ROW
WE
~:~
l>
"~~~W=~_ _+I~I~~-R~~--~--~~--*-~~~~==
I
I
10HR
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
~- ~1
tCSH
I IAR
=J
IRAQ
)" 'ASR
ADDR
~:e
7,@t
!RAH~I
ROW YW
'RAe
I
I
~
~
~-r
QPEN -------@
~
c-,
tRAL
~
~II
~I
leAH
COLUMN
I
'RWD
1~pLl
'AWD
Ii
i
I
II
leAH'-1
ROW
II-IRWL~
COLUMN
!cWL--
'wp--
'AWD
I~
Ii
i
.-.tCWl
I
=1
IAWO
__ twp
I~
~II~ ~II~
m':1c 1-1~ ,,':1.
m-1-~
-
VALID
~-r
VAliD
-
VALID
~-r
VALID
~~
i
tRAG
I :~~ -l
s:
OPEN
t-OPEN-
VAUDDATA
~
I~
OE
~I~ :$/$#////////$/////P'P'P'///$//"d
I
I~
lORD
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
RAS
v,H-------.. 1
V'L 1 1 - - - - - - - - - - - - - - = : - - - -lASH
---1
ICp
teAS
ADDR
~:~
I
o
~:~
Q
VQH_
VOL
IIICWL
.
."
::1;'///////////////1/////////////////////////////////#//;,;
~&
l
OPEN
I
NOTE:
VAL'ODATA
'"'
W////////////////////I&
NOTE 1
VALID
DATA
OPEN----
lAA
tRAC
-~lt :7llIA'-LI'-LL.U>.._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
1. Do not drive data prior to tristate.
MT4LC4M4B1(S)
D15.pm5 - Rev. 2195 ,
L
J
~ ~
~~~_~J=r~~~~r~~-~~~r~~~
,____+I,.,.ACS,-! ••
DE
teAS
2-76
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the rlghtto change products orspectncat\ons without notiOe.
@1995,MlcronTechnology,lnc.
RAS-ONL Y REFRESH CYCLE
(WE = DON'T CARE)
: ::0 '"' '~II--------l"b
l~
I'
ADDR
OQ
'MS
'RP
l
'------
'ASR , ,'RAH
~:~ ::~'---RO-W---,'k/j'j'//$/#j'j'/j'//#/#//j'/#/M"$~r---RO-W- ~g~
-,---------------OPEN---------
CBR REFRESH CYCLE
(Addresses and OE = DON'T CARE)
,
~ .~~
'RP
=J:'cp:~
CAS
DO
~:~_
-
,
tRAS
1
II
.. I ..
1
tRAS
,I
~t
OPEN-i-i-"- - - - - - -
II
MT4LC4M4B1(S}
D15.pmS - Rev. 2/95
, ,
~r~~
II
'WRP 'WRH
WE
'RP
'WRP 'WRH
~:~ -Wd$$/U- -~$IIIff/$$j;/j- --'iw;///;/$$$/$;J/J///;/;2
2-77
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MlcronTechnology, Inc.
•"
"tJ
s:
C
::c
l>
s:
SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
•
NOTE 1
'TI
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s:
C
~
»
s:
~
m
NOTE:
DON'T CARE
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT4LC4M4Bl{S)
01S.pmS-Aev.2195
2-78
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LC16M4A71T8
16 MEG x 4 DRAM
"'""CO" '"'
DRAM
16 MEG x4 DRAM
m
3.3V, FAST PAGE MODE
:.
FEATURES
PIN ASSIGNMENT (Top View)
• Single +3.3V ±0.3V power supply
• Industry-standard x4 pinout, timing, functions and
packages
• 13 row-addresses, 11 column-addresses (A7) or
12 row-addresses, 12 column-addresses (T8)
• High-performance CMOS silicon-gate process
• All inputs and outputs are LVTTLccompatible
• FAST PAGE MODE access
• 4,096-cycle CAS-BEFORE-RAS (CBR) REFRESH
distributed across 64ms
34-Pin SOJ
(DA-6)
Vee
D01
D02
NC
NC
NC
NC
MARKING
OPTIONS
• Timing
50ns access
60ns access
70ns access
WE
-5
RAS
NC
AO
A1
A2
A3
-6
-7
• Packages
Plastic SOJ (500 mil)
Plastic TSOP (500 mil)
DW
TW
A4
• Part Number Example: MT4LCI6M4A7DW-7
A5
Vee
KEY TIMING PARAMETERS
SPEED
tRe
tRAC
tpc
tAA
tCAC
-5
-6
-7
90ns
110ns
130ns
50ns
60ns
70ns
30ns
35ns
40ns
25ns
30ns
35ns
13ns
15ns
20ns
1•
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vee
D01
D02
NC
NC
NC
NC
The MT4LC16M4A7 and MT4LC16M4T8 are high-speed
CMOS dynamic random access memory devices containing
67,108,864 bits, and designed to operate from 3.0V to 3.6V.
The MT4LC16M4A7 and MT4LC16M4T8 are functionally
organized as 16,777,216 locations containing 4 bits each. The
16,777,216 memory locations are arranged in 8,192 rows by
2,048 columns for the MT4LC16M4A7 or 4,096 rows by
4,096 columns for the MT4LCI6M4T8. During READ or
WRITE cycles, each location is uniquely addressed via the
address bits. First, the row address is latched by the RAS
signal, then the column address by CAS. Both devices
provide FAST PAGE MODE operation, allowing for fast
successive data operations (READ, WRITE or READMODIFY-WRITE) within a given row.
The MT4LC16M4A7 and MT4LC16M4T8 must be refreshed periodically in order to retain stored data.
MT4LC16M4A7rra
D21.pmS- Rev. 2195
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
WE
RAS
NC
AO
A1
A2
A3
A4
A5
Vee
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
s:
C
Vss
D04
D03
NC
NC
NC
CAS
OE
NC
A12/NC
A11
A10
A9
A8
A7
A6
Vss
Vss
D04
D03
NC
NC
NC
CAS
OE
NC
A12/NC
A11
A10
A9
A8
A7
A6
Vss
'Consult factory for dimensions and availability.
2-79
."
"'C
:D
34-Pin TSOP*
GENERAL DESCRIPTION
z
Micron Technology, Inc., reserves the right to change products or specifications wtthout notice.
©1995, Micron Technology, Inc.
l>
s:
ADVANCE
MIC:RON
1-·
MT4LC16M4A71T8
16 MEG x 4 DRAM
",",oen",,",
z
m
FUNCTIONAL BLOCK DIAGRAM
MT4LC16M4A7 (13 row-addresses)
:e
•
WEO
DOl
CASo~~~------------------------~
DQ2
DQ3
DQ4
"T1
"tJ
S
L-________________________
C
:II
AD
~~-------o
OE
~~IIIIfIIIIIIIfIIIIIIIfIII~
Al~tT~=~~
A2~
l>
A3
s::
A4
A5
A6
A7
AS
A9
A1D
8192 x 2048 x 4
MEMORY
ARRAY
All ~~~~I ~~~~JI~~IIIIII~
A12 O-----"IWI~
Vee
RAS
Vss
FUNCTIONAL BLOCK DIAGRAM
MT4LC16M4T8 (12 row-addresses)
WE
°
DOl
D02
D03
D04
CAS~o--~---------------------------.
L-------------------------~~~------oOE
AO
Al
A2
A3
A4
AS
A6
A7
AS
A9
4096 x 4096 x 4
Al0
All
MEMORY
o--m~m&~~~~~JI~~IIIIII~~
ARRAY
Vee
RAS
..--0
MT4lC16M4A71T8
D2t .pmS - Rev. 2195
2-80
Vss
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
MT4LC16M4A71T8
16 MEG x 4 DRAM
"'""'''''"'
z
m
FUNCTIONAL DESCRIPTION
LOW, and entering new column addresses with each CAS
cycle. Returning RAS HIGH terminates the FAST PAGE
MODE operation.
The functional description for the MT4LC16M4A7 and
MT4LC16M4T8 is divided into the two areas described
below (DRAM access and DRAM refresh). Relevant timing
diagrams are included in this data sheet following the
timing specifications tables.
DRAM REFRESH
The supply voltage must be maintained at the specified
levels, and the refresh requirements must be met in order to
retain stored data in the DRAM. The refresh requirements
are met by refreshing all 8,192 rows (A7) or all 4,096 rows
(T8) in the DRAM array at least once every 64ms. The
recommended procedure is to execute 4,096 CBR REFRESH
cycles, either uniformly spaced or grouped in bursts, every
64ms. The MT4LC16M4A7 internally refreshes two rows
for every CBR cycle, whereas the MT4LC16M4T8 refreshes
one row for every CBR cycle. So with either device, executing 4,096 CBR cycles covers all rows. Alternatively, RASONLY REFRESH capability is inherently provided.
However, with this method only one row is refreshed at a
time, so for the MT4LC16M4A7, 8,192 RAS-ONLY REFRESH cycles must be executed every 64ms to cover all
rows.
DRAM ACCESS
Each location in the DRAM is uniquely addressable as
mentioned in the General Description. The data for each
location is accessed via the four II 0 pins (DQl-4). The WE
signal must be activated to execute a write operation, otherwise a read operation will be performed. The OE signal
must be activated to enable the DQ output drivers for a read
access and can be deactivated to disable output data if
necessary.
FAST PAGE MODE operations are always initiated with
a row-address strobed-in by the RAS signal, followed by a
column-address strobed-in by CAS, just like for single locationaccesses. However, subsequent column locations within
the row may then be accessed at the page-mode cycle time.
This is accomplished by cycling CAS while holding RAS
MT4LC16M4A7/T8
D21.pmS-Rsv.2f95
2-81
Micron Technology, Inc., reserves the right to change products or specifiCations without notice
©1995, Micron Technology, Inc.
:e
•"
"tJ
S
c
::c
»
s
ADVANCE
MICRON
1-·
MT4LC16M4A71T8
16 MEG x 4 DRAM
"'","CO"""
z
m ABSOLUTE MAXIMUM RATINGS*
~
."
Voltage on Vee Relative to Vss ..................... -1.0V to +4.6V
Voltage on Inputs or I/O Pins
Relative to Vss ................................................ -1.0V to +S.5V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .....................-SSOC to + ISO°C
Power Dissipation ............................................................. IW
Short Circuit Output Current ..................................... SOmA
C
lJ
(Notes: 1, 6, 7) (Vcc
•
."
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
S
»
S
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
=+3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vcc
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
O.S
V
II
-2
2
~
loz
-10
10
VOH
2.4
~
V
0.4
V
INPUT LEAKAGE CURRENT
Any input OV :s; VIN :s; 3.6V
(All other pins not under test =OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV :s; VOUT:S; 3.6V)
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
VOL
NOTES
MAX
VERSION
SYMBOL
-5
-6
-7
STANDBY CURRENT: (TTL)
(RAS =CAS = VI H)
MT4LC4M16A7
MT4LC4M16TS
Icc1
Icc1
1
1
1
1
1
1
STANDBY CURRENT: (CMOS)
(RAS =CAS :2: Vcc -0.2V, DQs may be left open,
Other inputs: VIN :2: Vcc -0.2V or VIN :s; 0.2V)
MT4LC4M16A7
MT4LC4M16TS
Icc2
Icc2
500
500
500
500
500
500
~
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC =IRC [MIN])
MT4LC4M16A7
MT4LC4M 16TS
Icc3
Icc3
130
170
120
160
110
150
mA
3,4,
29
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC = tpc [MIN])
MT4LC4M16A7
MT4LC4M16TS
Icc4
Icc4
100
100
90
90
SO
80
mA
3,4,
29
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: tRC =tRC [MIN])
MT4LC4M16A7
MT4LC4M16T8
Iccs
Iccs
130
170
120
160
110
150
mA
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC
MT4LC4M16A7
MT4LC4M 16T8
ICG6
Icc6
140
170
130
160
120
150
mA
PARAMETER/CONDITION
MT4LC16M4A71T8
D21.pm5 - Rev. 2/95
=IRC [MIN])
2-82
UNITS NOTES
mA
3,26
3,5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LC16M4A71T8
16 MEG x 4 DRAM
","",CO",",
z
m
CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: Address pins
CI1
2
CI2
5
7
pF
Input Capacitance: RAS, CAS, WE, OE
pF
2
Input/Output Capacitance: DQ
CIO
9
pF
2
=E
•"
-C
s:
C
::IJ
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vcc = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
SYM
Access time from column-address
Column-address hold time (referenced to RAS)
tAR
-5
tASC
Column-address to WE delay time
tAWD
Access time from CAS
tCAC
Column-address hold time
tCAH
CAS pulse width
CAS hold time (CBR REFRESH)
tCAS
CAS to output in Low-Z
CAS precharge time (FAST PAGE MODE)
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
tASR
tCHR
tCLZ
tcp
tCRP
13
MT4LC16M4A7/TS
D21.pm5 - Rev. 2/95
MAX
30
45
0
0
55
10,000
2-83
13
13
MIN
10
15
15
0
10
10,000
15
20
15
0
10
35
5
60
5
40
15
10
45
0
0
15
MAX
35
55
0
0
65
15
30
toE
toEH
tDHR
tDS
Output Enable time
OE hold time from WE during
READ-MODIFY-WRITE cycle
8
13
15
0
8
too
Data-in hold time (referenced to RAS)
Data-in setup time
MIN
13
5
50
5
36
13
8
40
0
0
tCSH
tCSR
tCWD
tCWL
tDH
Output disable
40
0
0
48
tCPA
Data-in hold time
Write command to CAS lead time
MAX
25
tAA
Column-address setup time
Row-address setup time
-7
-6
MIN
15
15
20
NOTES
ns
ns
ns
ns
ns
21
15
20
ns
ns
10,000
ns
ns
5
ns
ns
16
40
5
70
5
50
20
15
55
0
0
UNITS
ns
ns
ns
ns
ns
5
21
ns
ns
22
ns
ns
22
27,28
ns
ns
28
ns
20
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, MicrcnTechnology, Inc.
»
s:
ADVANCE
z
~ ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
<
•
."
"tJ
s:
C
:IJ
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s:
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vee = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Output buffer turn-off delay
OE setup prior to RAS during
HIDDEN REFRESH cycle
FAST-PAGE-MODE
READ or WRITE cycle time
FAST-PAGE-MODE
READ-WRITE cycle time
-5
SYM
30
35
40
ns
tpRWC
76
85
100
ns
tRAC
tRAD
Column-address to RAS lead time
tRAH
tRAL
RAS pulse width
tRAS
RAS pulse width (FAST PAGE MODE)
Random READ or WRITE cycle time
RAS to CAS delay time
tRASP
tRC
Read command hold time (referenced to CAS)
tRCH
Read command setup time
tRCS
tREF
tRP
tRCD
RAS to CAS precharge time
tRPC
Read command hold time (referenced to RAS)
RAS hold time
tRRH
READ WRITE cycle time
tRWC
RAS to WE delay time
Write command to RAS lead time
tRWD
tRWL
tRSH
13
8
25
50
50
90
18
0
0
IT
1
tWCH
Write command hold time (referenced to RAS)
WE command setup time
tWCR
8
40
0
8
10
10
WE setup time (CBR REFRESH)
MT4LC16M4A7fT8
021 .pm5 - Rev. 2/95
twRH
tWRP
37
30
0
0
13
131
73
13
Write command hold time
Write command pulse width
WE hold time (CBR REFRESH)
10,000
125,000
15
10
30
60
60
110
20
0
0
64
Transition time (rise or fall)
twcs
twp
50
25
MIN
0
0
2-84
50
MAX
15
60
30
10,000
125,000
45
15
10
35
70
70
130
20
0
0
64
40
0
0
15
155
85
15
1
10
45
0
10
10
10
50
MAX
20
UNITS
tpc
RAS to column-address delay time
Row-address hold time
MAX
13
MIN
0
0
tOFF
tORD
Access time from RAS
Refresh period
RAS precharge time
-7
-6
MIN
0
0
70
35
ns
ns
ns
NOTES
20,27
14
18
ns
10,000
125,000
ns
ns
50
ns
ns
17
ns
19
ns
64
50
0
0
20
185
100
20
1
15
55
0
15
10
10
ns
ns
ms
ns
26
ns
ns
19
ns
ns
ns
ns
50
21
ns
ns
ns
ns
ns
ns
ns
21
25
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology, Inc.
ADVANCE
MICRON
1-·
MT4LC16M4A7ITS
16 MEG x 4 DRAM
"'""oco"'''
z
m
NOTES
1.
2.
3.
4.
All voltages referenced to V55.
This parameter is sampled. Vee = +3.3V; f = 1 MHz.
Ice is dependent on cycle rates.
Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOlls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
8. AC characteristics assume IT = Sns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates,
100pF and VOL = 0.8V and VOH = 2.0V.
14. Assumes that IRCD < tRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that tRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, output data
will be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS must
be pulsed HIGH fortCP.
17. Operation within the tRCD (MAX) limit ensures that
IRAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified tRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
18. Operation within the lRAD (MAX) limit ensures that
tRAC (MIN) and tcAC (MIN) can be met. tRAD
(MAX) is specified as a reference point only; if lRAD
is greater than the specified IRAD (MAX) limit, then
access time is controlled exclusively by IAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
MT4LC16M4A7fT8
D21.pmS - Rev. 2195
20. 10FF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL.
21. IWCS, IRWD, IAWD and ICWD are not restrictive
operating parameters. twcs applies to EARLY WRITE
cycles. IfIWCS > twcs MIN, the cycle is an EARLY
WRITE cycle and the data output will remain an open
circuit throughout the entire cycle.IRWD, IAWD and
ICWD define READ-MODIFY-WRITE cycles. Meeting
these limits allows for reading and disabling output
data and then applying input data. The values shown
were calculated for reference allowing IOns for the
external latching of read data and application of write
data. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. twcs, IRWD, tCWD and IAWD are not
applicable in a LATE WRITE cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and
OE = HIGH.
25. tWTS and IWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of twRP and twRH in the
CBR REFRESH cycle.
26. RAS-ONLY REFRESH requires that all 8,192 rows of
the MT4LC16M4A7, or all 4,096 rows of the
MT4LC16M4T8, be refreshed at least once every
64ms. CBR REFRESH, for either device, requires that
at least 4,096 cycles be completed every 64ms.
27. The DQs open during READ cycles once 10D or tOFF
occur. If CAS goes HIGH before OE, the DQs will
open regardless of the state of OE. If CAS stays LOW
while OE is brought HIGH, the DQs will open. If OE
is brought back LOW (CAS still LOW), the DQs will
provide the previously read data.
28. LATE WRITE and READ-MODIFY-WRITE cycles
must have both taD and tOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. If OE is
taken back LOW while CAS remains LOW, the DQs
will remain open.
29. Column-address changed once each cycle.
2-85
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
:e
'T1
"'C
s:
C
II
»
s:
ADVANCE
UII::I=ICN
1-·
MT4LC16M4A71T8
16 MEG x 4 DRAM
"'"""'" '"'
z----------------------------------------------
m
READ CYCLE
:e
•
~lt ==
___
RAS
~Il'-
IRC
______
IRA_S_ _ _ _ _ _----'
_--_:
I
\
tCSH
"TI
"tJ
'-----
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II
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ADDR
DO
~:gt -'-----------OPEN--------1Q;~!!.VA':"'.LlD~DAT~A j - - - - O P E N - -
~1t
DE
~
~
IOE
IOD
_,1/11//l1/li///11///1//m
WI/I/II//I///I//Jl/jl//;/;/;/!II!111$//1//;/$'---
EARLY WRITE CYCLE
IRC
ADDR
~:t-
ROW
ROW
I
I
tWCR
twcs
tWCH
·1
WE ~:t-
1
I I
.
I
I
IWp
'DHR'~
I~~II~
DQ~:gt~
VALIDDATA~
DE ~:t
[Z;J DON'T CARE
~
MT4LCI6M4A7JT8
D21.pm5-Rev.2/95
2-86
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995,MicronTechnology. Inc.
ADVANCE
MICRON
0.-·
MT4LC16M4A71T8
16 MEG x 4 DRAM
,""'00"'0""'
----------------------------------------------------~
m
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
F
tRAS
-
~
'L
tRP
ICRP
=J
dI
tAR
I
tRAD
tl~ ::;/~
W////1
ROW
I~I
I
'RCS
II
I
II
'cwo
I
tM
c
:IJ
/'///////////IY.
.~II
IRWD
ROW
tRWL
.~.
IAWD
I
I.
I
ICLZ-
-
tI
tAAL
COLUMN
I
I'
I.
I
~I
l~~ ~I
ADDR
i:
tCAS
tACO
tRAG
I~
~
OPEN
I~~I
VALID DOUT
K
~!
~
OPEN~~
VALID DIN
~
FAST-PAGE-MODE READ CYCLE
1----------"tR""ASP~--------I~·
AA
I
AA
I
'RAG
!~
'cLZ-1
DO
MT4LC16M4A7fT8
D21.pmS - Rev. 2195
~ig~
::::-.--
1:-
I
tOFF
-
'CLZ-
VALID
OPEN
t~
'CPA
'CAG
1:-
AA
I
-
'OFF.
I
'CPA
'CAG
~
tcLz-
1,-
VALID
DATA
~~
~ I~
2-87
-"
"'tJ
tCSH
lASH
-""-
-
--'OFF
VALID
DATA
~
~
~
DON'T CARE
~
UNDEFINED
Micron Technology. Inc., reserves the right to change products or speciJications without notice.
©1995, Micron Technology, Inc.
l>
i:
ADVANCE
MIC:RON
1-·
~
m
MT 4LC16M4A71T8
16 MEG x 4 DRAM
"'""''"''''
------------------------------------------------------FAST-PAGE-MODE EARLY-WRITE CYCLE
:e
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'RASP
tCSH
'TI
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ADDR
~:~
I
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I~I
I
-
eWl
eWl
I I
I
I
I
Wl
~II ~:~H ~I
I~
'WP
~II ::~H ~
WM II I.
II
fl/l))
II
'WGR
I 'OHR
IRWL
I
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
RAs
'RASP
~:t _
I~
CAS
~:~ =.-1
1~----~'e~sH----------~·'~pe~/'p~RW~e------~'R~SH---
~.
1___'=Reo'----_I~-----"'e=As___I ~ 1_'=eAs'---_1 .-"e",-
s:
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
,RAS P
, p
't=L
IRSH
'pc [,
tCSH
J~
I_,'ASR,
ADDR
WE
~\t_
l///M
tRCD
t
~
~
~:~Ij I/ I/;.7,(/,(,(J
I
COLUMN
I
1"Ase
~
'Res.
I '
'RAL
'(:AH'j
IWCS -
1
tWCH
I
I
~$~/'(/'('(/'(M
,
~-
I
I
I
I
I,
II
~[[~
~ ~TI
l
~g~ =~---CI-OPEN
II,
II 'eWL
II
'RWL'
II 'wp
. :
D~:~ J1#1/;/III$11&Iffi!#fWI###;/;I~~#/11/;11/11~
Q
,I
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~~
1
'ep
I
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'RAD
RAH _[
ROW
'AJ~~-
'I,
~
'ep
VALID DATA
.
b=1//;=W=WW/;T7T
WWTTT1//;TTT:2
rlT
TTT
NOTE 1
'AA
---OPEN
'RAe
NOTE:
IL8
DON'T CARE
~
UNDEFINED
1. Do not drive input data prior to output data going High-Z.
MT4LC16M4A7ITa
D21.pm5 - Rev. 2195
2-89
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LC16M4A71T8
16 MEG x 4 DRAM
","'ceo",,",
z
m
CBR REFRESH CYCLE
(Addresses and OE = DON'T CARE)
:e
•
.
'RP
RAS
."
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S
CAS
C
:::rJ
DO
l>
.~
VIH
VIL -
s:
1
'RPC
:::J"
s:
FAST PAGE MODE (continued)
•
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dynamic refresh mode at the extended refresh period of
128ms, four times longer than the standard 32ms
specification.
The optional SELF REFRESH feature is initiated by performing a CBR REFRESH cycle and holding RAS LOW for
the specified IRASS. Additionally, the "S" version allows
for an extended refresh rate of 62.5J.ls per row if using
distributed CBRREFRESH. This refresh rate can be applied
during normal operation or during a standby or BATTERY
BACKUP mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum timeoftRPS(~tRC). This delay allows
for the completion of any internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all 2,048 rows must
be refreshed within 300J.ls prior to the resumption of normal
operation.
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is also preconditioned for the next cycle during the
RAS HIGH time. Memory cell data is retained in its correct
state by maintaining power and executing any RAS cycle
(READ, WRITE) or RAS refresh cycle (RAS ONLY, CBR, or
HIDDEN) so that all 2,048 combinations of RAS addresses
(AO-AlO) are executed at least every 32ms, regardless of
sequence. The CBR REFRESH cycle will also invoke the
refresh counter and controller for row-address control.
REFRESH
Preserve correct memory cell data by maintaining
power and executing a RAS cycle (READ, WRITE) or RAS
refresh cycle (RAS ONLY, CBR or HIDDEN) so that all 2,048
combinations of RAS addresses are executed at least every
32ms, regardless of sequence. The CBR REFRESH cycle will
invoke the refresh counter for automatic RAS addressing.
An optional SELF REFRESH mode is also available on
the MT4LC2M8Bl S. The "S" version allows the user the
choice of a fully static low-power data retention mode or a
FUNCTIONAL BLOCK DIAGRAM
2,048 ROWS
WE~----~-----------------------.
DATA-IN BUFFER
CAS~---r-------------r--r---t-----------L______~____~
D01
••
D08
OE
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
RAS
x 1024 x 8
MEMORY
ARRAY
2048
~-----t
MT4LC2M8B1(S)
W02.pm5 - Rev. 2195
2-92
....--.-.0
Vee
-+-------0
V ss
Micron Technology, inc., reseIVes the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT4LC2M881 (5)
2 MEG x 8 DRAM
""" "
TRUTH TABLE
FUNCTION
1m""
'CR"
WE"
lJt
Standby
H
H-'X
X
X
READ
L
L
H
EARLY WRITE
L
L
L
ADDRESSES
IR
IC
DOs
X
X
High-Z
L
ROW
COL
Data-Out
X
ROW
COL
Data-In
L
L
H~L
L~H
ROW
COL
Data-Out, Data-In
FAST-PAGE-MODE
1st Cycle
L
H~L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H~L
H
L
nJa
coL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H~L
L
COL
Data-In
WRIT,E
!-
H~L
L
X
X
ROW
2nd Cycle
nfa
COL
Dat?ln
FAST-PAGE-MODE
1st Cycle
L
H~L
H~L
L~H
ROW
COL
Data-Out, Data-In
READ.:WRITE
2nd Cycle
L
H~L
H~L
L-H
nfa
COL
Data~Out,
L
H
L
ROW
COL
Data-Out
X
X
X
X
READ WRITE
HIDDEN
READ
L~H-+L
REFRESH
WRITE
L-+H-+L
L
L
L
H
X
CSR REFRESH
H-+L
L
H
SELF REFRESH
H-+L
L
H
RAS-ONLY REFRESH
MT4LC2M881(S)
W02.pm5 - Rev. 2/95'
Data-In
ROW
COL
Data-In
ROW
nfa
High-Z
X
X
X
X
. High-Z
High-Z
Micron Technology, Inc., reserves the right to challg& products or specifications without n'otIce.
©1995, Micron Technology,.lrIc.
•
"T1
"'0
:s:
C
:D
»
:s:
MIC:RON
1-·
;~'c;
MT 4LC2M8B 1(5)
2MEGx8DRAM
,
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
,for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
'"'0
Voltage on Vcc Supply RelativetoVss ........... -IV to +4.6V
Voltage on Inputs or I/O Pins
Relative toVss .......................................... ::.,....... -IV to +S.SV
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plasti<;:) .................... -SsoC to + ISO°C
Power Dissipation ......•................................
1W
Short Circuit Output Current ....... ,'.............'................ SOmA
C
JJ
(Notes: 1, 6,,7) (Vee = +3.3V ±0.3V)
•
."
s:
»
s:
0<" ••••••••••••••••••••
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
3.0
3.6
V
InputHigh (Logic 1) Voltage, all inputs (including NC pins)
VIH
2.0
5.5V
V
Input Low (Logic 0) Voltage, all inputs (including NC pins)
VIL
-1.0
0.8
V
II
-2
2
!LA
loz
-10
10
!LA
VOH
2.4
INPUT LEAKAGE CURRENT
. Any input OV :s; VIN :s; 5.5V
(All other pins not under test OV)
=
OUTPUT LEAKAGE CURRENT (Q is disabled; OV :s; VOUT < 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT -2mA)
Output Low Voltage (lOUT 2mA)
=
=
MT4LC2M8B1(S)
W02.pmS - Rev. 2195
VOL
2-94
NOTES
V
0.4
V
Mlcroo Technology, Inc., l'98erves the right to change products or specifications wfItlout notice.
©1995, Micron Technology, Inc.
I
MICRON
1-·
,~,
MT 4LC2M88 1 (S)
2 MEG x 8 DRAM
10
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) 01cc = +3.3V ±0.3V)
MAX
PARAMETER/CONDITION
STANDBY CURRENT: TTL(RAS
STANDBY CURRENT: CMOS
(RAS = CAS =Vcc -0.2V)
= CAS =VIH)
-6
Icc!
2
,
,,'
Icc::!
-7
2
500 ' ·500
150
150
Icc2
Icc2
(S only)
OPERATING CURRENT: Random READIWRITE
AverlMlepower supply current
(RAS, CAS, Address Cycling: IRC =IRC [MIN])
OPERATING CURRENT: FAST PAGE MODE
Average,power supply current
(RAS =\(II-, CAS, Address Cycling: IpC= IpC [MIN]; ICp, IASC
SYMBOL
I,
130
120
UNITS NOTES
mA
,mA
"'tJ
s::
3,4,27
I
90
80
mA
3,4,21
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC = IRC [MIN])
Icc5
130
120
mA
3,27
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC[MIN])
Iccs
130
120
mA
3,5
Icc7
(Sonly)
300
300
~
3,5
Icca
(S only)
300
300
~
5
REFRESH CURRENT: Extended (S version only)
Average power supply current during BBU REFRESH:
CAS =0,2Vur CBRcycling; RAS =IRAS (MIN) to 300ns;
WE =Vcc -0.2V,OE, AO-A10 and DIN =Vcc -0.2Vor 0,2V
(DIN may be left open), IRC =62.51lS (2,048 rows at 62.5J.ls = 128ms)
REFRESH QURRENT:SELF(S version only)
Average power supply current during SELF REFRESH: CBR cyple
with RAS ~ IRASS (MIN) and CAS held LOW; WE =Vce - 0.2V;
AO~A10,OE and DIN =Vcc - 0.2V or 0.2V (DIN may bElleltopen)
MT4Ly2MBB1(S)
W02.pm5 - Rev. 2195
C
::JJ
Icc4
= 10ns)
•
."
~
~
Micron Technology. Inc., reserves the right to change prodLlCls or specifications without 'notice.
s::
MIC:RON
1-·
"
MT4LC2M8B1 (S)
2 MEG x 8 DRAM
C,,,
CAPACITANCE
•"
-n
PARAMETER
SYMBOL
Input Capacitance: Addresses
Cll
Input Capacitance: RAS, CAS, WE, OE
CI2
Input/Output Capacitance: DO
C,O
MAX
5
UNITS
NOTES
pF
2
7
7
pF
2
pF
2
3:
C ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
:a
=
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vcc
l>
3:
+3.3V ±O.3V)
AC CHARACTERISTICS
PARAMETER
SVM
Access time from column-address
tAA
Column-address hold time (referenced to RAS)
tAR
Column-address setup time
Row-address setup time
tASC
tASR
Column-address to WE delay time
tAWD
Access time from CAS
Column-address hold time
tcAC
tCAH
~ pulse width
tCAS
tCHD
CAS hold time entering SELF REFRESH
CAS hold time (CSR REFRESH)
CAS precharge time
tCHR
tCLZ
tcp
Access time from CAS precharge
tCPA
CAS to RAS precharge time
CAS hold time
tCRP
tCSH
CAS setup time (CSR REFRESH)
Write command to CAS lead time
Data-in hold time
tcSR
tCWD
tCWL
tDH
Data-in hold time (referenced to RAS)
Data-in setup time
tDHR
tDS
CAS to output in Low-Z
CAS to WE delay time
Output disable
Output Enable
taD
tOEH
OE setup prior to RAS during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
tORD
tpc
FAST-PAGE-MODE READ-WRITE cycle time
RAS to column-address delay time
MT4LC2M8B1(S)
W02.pm5 - Rev. 2/95
tOFF
tpRWC
tRAC
tRAD
MAX
30
50
0
0
55
MIN
10
15
15
15
3
10
10,000
5
15
3
0
35
85
15
UNITS
35
ns
15
20
15
15
3
10
15
15
15
60
30
ns
ns
15
3
0
40
95
15
ns
21
15
ns
10,000
ns
ns
ns
ns
ns
40
5
70
5
45
20
15
55
0
3
NOTES
ns
ns-
20
35
5
60
40
15
10
45
0
3
MAX
55
0
0
60
15
tOE
OE hold time from WE during READ-MODiFY-WRITE cycle
Output buffer turn-off delay
Access time from RAS
·7
·6
MIN
26
5
28
16
ns
ns
ns
ns
ns
5
21
ns
ns
ns
22
ns
ns
20
20
ns
22
28
23
20
ns
ns
20,28
ns
ns
ns
70
35
ns
ns
14
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995,MlcronTechnology,Jnc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vee = +3.3V to 0.3V)
-6
AC CHARACTERISTICS
PARAMETER
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
RAS pulse width entering SELF REFRESH
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (2,048 cycles)
Refresh period (2,048 cycles) S version
RAS precharge time
RAS to ~ precharge time
RAS precharge time exiting SELF REFRESH
Read command hold time (referenced to RAS)
RAS hold time
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transistion time (rise or fall)
Write command hold time
Write command hold time (referepcedto RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT4lC2M8B1(S)
W02.pm5 - Rev. 2195
SYM
MIN
IRAH
IRAL
tRAS
IRASP
IRASS
IRC
10
30
60
60
100
110
20
0
0
IRCD
IRCH
IRCS
IREF
IREF
IRP
IRPC
IRPS
IRRH
IRSH
tRWC
IRWD
IRWL
IT
..
IWCH
IWCR
IWCS
IWp
IWRH
tWRP
2-97
-7
MAX
10,000
100,000
45
MIN
10
35
70
70
100
130
20
0
0
50
UNITS
10,000
100,000
ns
ns
ns
ns
>Ls
50
32
128
32
128
40
0
110
0
15
150
85
15
3
10
45
0
10
10
10
MAX
50
0
130
0
20
180
95
20
3
15
55
0
15
10
10
50
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
•"'"
."
26
17
19
26
26
19
21
21
25
25
Micron Technology, inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
s:
C
J:J
»
s:
NOTES
•
"T1
-0
5
C
:II
»
s:
1.
2.
3.
4.
All voltages referenced to Vss.
This parameter is sampled. Vee = +3.3V; f = 1 MHz.
Icc is dependent on cycle rates.
Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of wails is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume IT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gate,
100pF and VOL =0.8V and VOH =2.0V.
14. Assumes that tRCD < IRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD:2: IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICP.
17. Operation within the tRCD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
18. Operation within the tRAD (MAX) limit ensures that
IRAC (MIN) and tCAC (MIN) can be met. IRAD
(MAX) is specified as a reference point only; if lRAD
MT4LC2M8B1(S)
W02.pm5 -Rev. 2/95
is greater than the specified tRAD (MAX) limit, then
access time is controlled exclusively by IAA.
19. Either tRCH or IRRH must be satisfied for a READ"
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL.
21. twcs, IRWD, IAWD and ICWD ate not restrictive
operating parameters. twcs applies to EARLY
WRITE cycles. IRWD, IAWD and ICWD apply to
READ-MODIFY-WRITE cycles. If tWCS:2: twcs
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If tRWD:2: tRWD (MIN), IAWD:2:
tAWD (MIN) and tCWD:2: ICWD (MIN), the cycle is a
READ-MODIFY-WRITE and the data output will
contain data read from the selected cell. If neither of
the above conditions is met, the state of data-out is
indeterminate. OE held HIGH and WE taken LOW
after CAS goes LOW results in a LATE WRITE (OEcontrolled) cycle. twcs, IRWD, ICWD and tAWD are
not applicable in a LATE WRITE cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITEoperations are not permissible and should not be attempted.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE =LOW and OE =HIGH.
25. twTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of twRP and tWRH in the
CBR refresh cycle.
26. Refresh must be completed within the time of three
external refresh rate periods prior to active use of the
DRAM (provided distributed CBR REFRESH is used
when in the active mode). Alternatively, a complete
set of row refreshes must be executed when exiting
SELF REFRESH prior to active use of the DRAM if
anything other than distributed CBR REFRESH is
used in the active mode.
27. Column-address changed once each cycle.
28. The 3ns minimum is guaranteed by design.
2-98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
READ CYCLE
•
IRC
VIH -
RAs
V\L _
-n
tOSH
teAs
tCRP
'"tJ
V1H VIL -
CAs
s:
,I
C
ROW
ADDA
_
I~
!CAG
DQ
~:g~ -'----------OPEN---------t~:=V~ALI~DD~ATA0--0PEN----
1
OE
I-
10E
laD
1//;=1
/ /;=V/j;rrT///777///;TT71/;7771
/j;=V/j;=///;rrT///;TT7('IW&
~:~ _.rn'@TTi~/'7T,~/;rrT~/TT71/j;TT71/777mTTi~/'7T,///;rT7V/j;TTTmTT71/777
1~TTim7T.m'77~/;7770'/;TT71101
EARLY WRITE CYCLE
RC
IRP
tRAS
'I
--
\
tCSH
tCRP
~J
~
tRCD
IAR
I~ ~I
ADDR
~:t
::W0i
ROW
f ~::
I
I
'RAL
~!
14
leAH
tRAD
.~
I
twcs
I
'CWL
I
I
'AWL
I
I
tWCR
I I
I
I
I
fl
ROW
1
tWGH
IWp
~
I I
W;//l'#;//I'~//'
1
~I
}
COLUMN
1
'I
tOHR
I
OE~:~.
MT4lC2M8B1(S)
W02.pmS - Rev. 2/95
2-99
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
::c
»
s:
u II::::1=1CN
MT4LC2MBB1 (5)
2 MEG x B DRAM
m~"OCOG'"
1-·
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
•
tRP
tAAS
."
RAS
~:~
II
~
d:::
tCSH
"tJ
s:
CAS
C
~:~
~J'
::c
l>
s:
ADDR
~!t
'cRP
~
'RCD
I
tRAl
~! I~I
I~ ~!
ROW
COLUMN
J@W
JW!u!uilml!u!uiU~~~
~>t
I
WE
I
~I
I
tAR
tRAD
I
V,H
VIL
I
I I·
I.
I.
I
tRCS
!
I_
leWD
II
'RWL
•
twp
I
I
_I
tAA
I
I
ROW
~II
tAWD
telz-
-
I
'RWD
tRAG:
teAe
~
VALID DOUT
OPEN
_I~~!
X
VALlDD JN
~!
~
OPEN--
~
FAST-PAGE-MODE READ CYCLE
1__- -_______________t=RA=SP_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I~
ADDR
~!r :=
I
+-'----------+---I-'?-te""-Ae-I
~-
DO
tRAG
-
I
~
tePA
I~ ~
~-
-
I
tePA
I~
_
-'OFF
~--
~:gt -------OPEN-----~~Jl\]D---____1W.9(V:@D~~['R)---~W{]~1M~R~
OPEN-
r:z:J DON'T CARE
~
MT4LC2M881(S)
W02.pmS - Rev. 2195
2-100
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
MIC:RON
MT4LC2M881(S)
2 MEG x 8 DRAM
"'~""'O" "
1-·
FAST-PAGE-MODE EARLY-WRITE CYCLE
RASP
-
i-
tCSH
I~
'RCD
ICRP
=--'
I
'PC
'OP
'CAS
~ I_ 'ASR 'RA:~I l~1 I~I
ADDR
~:~
::II/A
WI/Ji
ROW
~
f---
~
'AR
F==L
lASH
_'_CP_
~,
'RAL
'CAH·I ~ I~II 'CAH·I
WI;': I'll/IX
I~
VI/II///,&{
COLUMN
COLUMN
I~I
!
•"
."
II
s:
ROW
COLUMN
C
::D
»
s:
OE
~:~ $j$!;I;1;1$;1;1;1//;1///$/;1;1;1$/;1;1$;1;1////;1/;1;1///$$$$;1;1;1$/;1/1//;1$/!/$$/7!&'EJ
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODiFY-WRITE cycles)
RASP
*tPC/tPRWC
tCSH
1_
'CRP.I
I
=J
I"
ADDR
~:r
::t//;Ii
tRCD
~~
'AR
IRAQ
'ASci
tRAH~1
'ASR
ROW
~
tCAS
X"//;)
I~
fl I
I
'RAc
l
~
I
;:Ll J.~
~
I
I
IAWD
I -~":1-
~~~
-m': 1-
~'m;o
_
toE-
ROW
i
I
~
'AWD
II-'RWL
__ tCWL
__ twp
,I~
~ II~
iIO(YDOUT
___ __ too
·NOTE:
'wp~
I~
DOUT~
---
It
tCWL~
'AWD
~-II~
~-r
OPEN------@~ ""0
II
COLUMN
'RWD
-- 1-""1--'OE-
/
~)I~I
~I
COLUMN
'AA!
l~
'CAS
'RAL
COLUMN
I
lASH
'CP
r----
'CAS
r----
I~
-
PL
~
-
---
-1-+ 1-~
m_
-~~-r
""0 :"t~:O;f___OPEN-
DIN
POUT
__ too
__
'OE-
-
J
too
IOEH
mJ
DON'T CARE
~
UNDEFINED
1. Ipe is for LATE WRITE only.
MT4LC2M881(S)
W02.pm5 - Rev. 2/95
2-101
Micron Technology, Inc., rese!Ves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1- •
MT4LC2M8B1 (5)
2 MEG x 8 DRAM
,
HIDDEN REFRESH CYClE.24
(WE = HIGH; OE = LOW)
•
(REFRESH)
(READ)
IRA S
IAAS
I~
~
ir-----i
."
"tJ
~
IRCD
"--J
s:
~
IAA
IRAD
~ .~
WIAt
~
C
::D
ROW
»
s:
tCHR
IRSH
. I:
IRA'
I .1
IAscll~l·
I
COLUMN
J~
1M
IRAe
'cAe
~l
OPEN
t- 0PEN -
VAliD DATA
~
I
~
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
Q
~gr
::---+I-.
OPEN
•
OE
}----OPON----
I,
t
1_.-,--"",M'--_f
tRAC
~:~ ~'_" _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~ DOIlf'TCA~E
~
NOTE:
UNDEFINED
1. Do not drive data prior to High-Z.
MT4LC2M.8B1(S)
W02.pmS - Rev. 2195
2-102
Micron Technology, Inc., reserves the right 10 change products or speclHcations Without notice.
@1995.MicronTechnology,lnc.
RAS-ONLY REFRESH CYCLE
(OE and WE DON'T CARE)
=
"~ ::r _~. _~_'____
'Rc_l~b'RP l'--___
'R_As_ _ _ _
CAs
ADDR
~:t ~~
___ I~~
~:t::~
II
!-,-.:;'R=AH_
ROW
'Jw;/W///m/#m//#/////$;I/IW$;J/$~--RO-W- -
DO ~gt - - - - - - - - - - - - - O P E N - - - - - - - - - - -
MT4LC2M8B1(S)
W02.pm5~Rev.2195
2-103
~
DON'TeARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
."
""C
:s:
C
::D
l>
3:
CBR REFRESH CYCLE
(Addresses and OE = DON'T CARE)
•,..
.
--"
"tJ
tRP
..
tRAS
'I
'~~
CAS
C
::0
DO
~:t-
-
III
tWRP
l>
s:
WE
..
tRP
,
tRAS
oJ'
0·tCP·~1
s:
.
II
tRPC
tCSR
tCHR
V
-~--
II
OPEN---i-7-----------
tWRH
tWRP
II
tWRH
~:t J;/;//$#m4-:T::-~!/;W$////m/l/$--- ---*w;####$###d#;/P~
SELF REFRESH CYCLE ("SLEEP MODE")
(Addresses and OE = DON'T CARE)
LATE
NOTE 1
(~
RASS
l _ t R P_ 1 - -,---\t
]
tRPS
2
'~!lm!l$!I!I$;~$~lll .YV~
tt
VOH DO
WE
VOL
tWRP
I!
( \ - OPEN
tWRH
tt
)
tWRP
iI
tWRH
~:t ~00/$/@----:T:-~W#$//$;//,@//,@/ij////ij/#ffJ~ ~Vm/&Ijj$///§;
NOTE:
MT4lC2M8Bl(S}
WD2.pm5 - Rev. 2/95
~
DON'T CARE
t888j
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a compete burst of all rows should be executed.
3. tWRP and tWRH are for system design reference only. The WE signal is actually a "don't care" at RAS time
during a CSR REFRESH. However, WE should be held HIGH at RAS time during a CSR REFRESH to
ensure compatibility with other DRAMs which require WE HIGH at RAS time during a CSR REFRESH.
2-104
Micron Technology, Inc., reserves the nghttochange products orsp ecificatlons wilhout notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LC8M8E1/B6
8 MEG x 8 DRAM
He<",coo,,",
8 MEG x8 DRAM
DRAM
3.3V, FAST PAGE MODE
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x8 pinout, timing, functions and
packages
• 13 row-addresses, 10 column-addresses (El) or
12 row-addresses, 11 column-addresses (B6)
• High-performance CMOS silicon-gate process
• All inputs and outputs are LVTTL-compatible
• FAST PAGE MODE access .
• 4,096-cycle CAS-BEFORE-RAS (CBR) REFRESH
distributed across 64ms
OPTIONS
MARKING
• Timing
SOns access
60ns access
70ns access
-5
-6
-7
• Packages
Plastic SOJ (500 mil)
Plastic TSOP (500 mil)
III
s:
34-Pin SOJ
(DA-6)
Vee
D01
D02
D03
D04
NC
Vee
WE
RAS
NC
AO
A1
A2
A3
A4
A5
Vee
• Part Number Example: MT4LC8M8EIDW-7
1•
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
C
:D
Vss
D08
D07
D06
D05
VSS
CAS
OE
NC
A12/NC
A11
A10
A9
A8
A7
A6
Vss
KEY TIMING PARAMETERS
tRC
tRAC
tpc
tAA
tCAC
-5
90ns
50ns
30ns
25ns
13ns
-6
110ns
60ns
35ns
30ns
15ns
-7
130ns
70ns
40ns
35ns
20ns
34-Pin TSOP*
Vee
D01
D02
D03
D04
NC
Vee
WE
RAS
NC
AO
A1
A2
A3
GENERAL DESCRIPTION
The MT4LC8M8El and MT4LC8M8B6 are high-speed
CMOS dynamic random access memory devices containing
67,108,864 bits, and designed to operate from 3.0V to 3.6V.
The MT4LC8M8E1 and MT4LC8M8B6 are functionally organized as 8,388,608 locations containing 8 bits each. The
8,388,608 memory locations are arranged in 8,192 rows by
1,024 columns for the MT4LC8M8El or 4,096 rows by 2,048
columns for the MT4LC8M8B6. During READ or WRITE
cycles, each location is uniquely addressed via the address
bits. First, the row address is latched by the RASsignal, then
the column address by CAS. Both devices provide FAST
PAGE MODE operation, allowing for fast successive data
operations (READ, WRITE or READ-MODIFY-WRITE)
within a given row.
The MT4LC8M8E1 and MT4LC8M8B6 must be refreshed
periodically in order to retain stored data.
MT4LC8M8E1JB6
D19.pm5 - Rev. 2/95
~
~----------------------~-n
'"tJ
PIN ASSIGNMENT (Top View)
DW
TW
SPEED
z
m
A4
A5
Vee
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
Vss
D08
D07
D06
D05
Vss
CAS
OE
NC
A12/NC
A11
A10
A9
A8
A7
A6
Vss
'Consult factory for dimensions and availability.
2-105
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
)It
s:
ADVANCE
z
m
FUN9TIONAL BLOCK DIAGRAM
MT4LC8M8E 1 ( 13 row-addresses)
~
II
WE
0
CAS~O---r----------------------r===~~~~__~________~
DQ1DQS
."
"'C
s:
~------------------------ffirifr------~ OE
C
:D
»
3:
ADA12
t;
~
8192x8
~
8192 x 1024 x 8
MEMORY
ARRAY
~
RAS
Vee
Vss
FUNCTIONAL BLOCK DIAGRAM
MT4LC8M8B6 (12 row-addresses)
WE
0
CAS~o--~--------------------------~
DQ1DQS
'-------------------------IIHI!I--------o
OE
ADA11
4096x8
~
UJ
en,
4096 x 2048 x 8
MEMORY
ARRAY
~
Vee
Vss
MT4LC8M8El/B6
D19.pmS-Rev.2195
2-106
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, inc.
ADVANCE
z
m
FUNCTIONAL DESCRIPTION
The functional description for the MT4LC8M8El and
MT4LC8M8B6 is divided into the two areas described
below (DRAM access and DRAM refresh). Relevant timing
diagrams are included in this data sheet, following the
timing specification tables.
DRAM ACCESS
Each location in the DRAM is uniquely addressable as
mentioned in the General Description. The data for each
location is accessed via the eight I/O pins (DQl-8). The
WE signal must be activated to execute a write operation,
otherwise a read operation will be performed. The OE
signal must be activated to enable the DQ output drivers for
a read access and can be deactivated to disable output data
if necessary.
FAST PAGE MODE operations are always initiated with
a row-address strobed-in by the RAS signal, followed by a
column-address strobed -in by CAS, just like for single locationaccesses. However, subsequent column locations within
the row may then be accessed at the page-mode cycle time.
This is accomplished by cycling CAS while holding RAS
MT4LC8M8E1IB6
019.pm5 - Rev. 2/95
LOW, and entering new column addresses with each CAS
cycle. Returning RAS HIGH terminates the FAST PAGE
MODE operation.
DRAM REFRESH
The supply voltage must be maintained at the specified
levels, and the refresh requirements must be met in order to
retain stored data in the DRAM. The refresh requirements
are met by refreshing all 8,192 rows (E1) or all 4,096 rows
(B6) in the DRAM array at least once every 64ms. The
recommended procedure is to execute 4,096 CBR REFRESH
cycles, either uniformly spaced or grouped in bursts, every
Mms. The MT4LC8M8El internally refreshes two rows for
every CBR cycle, whereas the MT4LC8M8B6 refreshes one
row for every CBR cycle. So with either device, executing
4,096 CBR cycles covers all rows. Alternatively, RAS-ONLY
REFRESH capability is inherently provided. However, with
this method only one row is refreshed at a time, so for the
MT4LC8M8El, 8,192 RAS-ONLYREFRESH cycles must hl'
executed every 64ms to cover all rows.
~-107
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Teci1nology, Inc.
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m ABSOLUTE MAXIMUM RATINGS*
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'Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
U
Voltage on Vee Relative to Vss ..................... -1.0V to +4.6V
Voltage on Inputs or I/O Pins
Relative to Vss ................................................. -1.0V to +S.5V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SsoC to +IS0°C
Power Dissipation ............................................................. IW
Short Circuit Output Current ..................................... SOmA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vee
=+3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
O.S
V
II
-2
2
IlA
loz
-10
10
IlA
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV :s; VIN :s; 3.6V
(All other pins not under test = OV)
OUTPUT LEAKAGE CURRENT (0 is disabled; OV :s; VOUT :s; 3.6V)
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
VOL
NOTES
V
0.4
V
MAX
VERSION
SYMBOL
-5
-6
-7
STANDBY CURRENT: (TTL)
(RAS = CAS = VI H)
MT4LCSMSE1
MT4LCSMSB6
ICCl
lecl
1
1
1
1
1
1
STANDBY CURRENT: (CMOS)
(RAS = CAS ~ Vee -0.2V, DOs may be left open,
Other inputs: VIN ~ Vce -0.2V or VIN :s; 0.2V)
MT4LCSMSE1
MT4LC8M8B6
Icc2
Icc2
500
500
500
500
500
500
IlA
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIND
MT4LC8M8E1
MT4LC8M8B6
Icc3
Icc3
135
175
125
165
115
155
mA
3,4,
29
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC = IpC [MIND
MT4LC8M8E1
MT4LC8M8B6
lee4
Ice4
105
105
95
95
85
85
mA
3,4,
29
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC = IRC [MIND
MT4LC8M8E1
MT4LC8M8B6
Iccs
Iccs
135
175
125
165
115
155
mA
3,26
REFRESHCURREN~CBR
MT4LC8M8E1
MT4LC8M8B6
Icc6
ICC6
145
175
135
165
125
155
mA
3,5
PARAMETER/CONDITION
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIND
MT4lC8M8E1/Be
D19.pmS-Rev.2I95
2-108
UNITS NOTES
mA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII::I=ICN
1-·
MT4LC8M8E1/B6
8 MEG x 8 DRAM
"'~"coo,,"
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CAPACITANCE
PARAMETER
SYMBOL
MAX
UNITS
NOTES
CI1
5
pF
2
Input Capacitance: Address pins
Input Capacitance: RAS, CAS, WE, OE
CI2
7
pF
2
Input/Output Capacitance: DQ
Clo
9
pF
2
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vcc = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time
(referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
CAS precharge time (FAST PAGE MODE)
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold Jime
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable time
OE hold time from WE during
READ-MODIFY-WRITE cycle
MT4lC8M8El/B6
D19.pmS - Rev. 2/95
-7
-6
-5
SYM
MIN
MAX
25
tAA
MIN
MAX
30
MIN
tAR
40
45
55
tASC
tASR
0
0
48
0
0
55
0
0
65
tAWD
tCAC
tCAH
tCAS
tCHR
tCLZ
tcp
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDHR
tDS
toD
tOE
tOEH
13
8
13
15
0
8
10,000
15
10
15
15
0
10
30
5
50
5
36
13
8
40
0
0
13
2-109
13
13
10,000
15
20
15
0
10
15
15
15
20
NOTES
ns
ns
r1S
10,000
40
5
70
5
50
20
15
55
0
0
UNITS
ns
ns
20
35
5
60
5
40
15
10
45
0
0
MAX
35
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
21
15
5
16
5
21
22
22
27,28
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
l>
S
ADVANCE
MICRON
1-·
MT4LC8M8E1/B6
8 MEG x 8 DRAM
W'"",COGn,
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~ ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
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(Notes: 6, 7, 8, 9, 10, 11, 12, 13, 23) (Vee
=+3.3V ±0.3V)
-5
AC CHARACTERISTICS
PARAMETER
Output buffer turn-off delay
OE setup prior to RAS during
HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
0
0
13
0
0
15
0
0
20
ns
ns
20,27
tpc
30
76
tpRWC
Access time from RAS
tRAC
RAS to column-address delay time
Row-address hold time
tRAD
tRAH
Column-address to RAS lead time
tRAL
Random READ or WRITE cycle time
tRAS
tRASP
tRC
RAS to CAS delay time
Read command hold time (referenced to CAS)
tRCD
tRCH
Read command setup time
tRCS
tREF
HAS pulse width
RAS pulse width (FAST PAGE MODE)
Refresh period
RAS precharge time
RAS to CAS precharge time
Read command hold time (referenced to RAS)
RAS hold time
tRP
tRPC
tRRH
tRSH
READ WRITE cycle time
tRWC
RAS to WE delay time
tRWD
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
tRWL
Write command hold time (referenced to RAS)
tr
tWCH
tWCR
Write command pulse width
twcs
twp
WE hold time (CBR REFRESH)
tWRH
WE setup time (CBR REFRESH)
tWRP
WE command setup time
MT4LC8M8E11B6
D19,pm5 - Rev. 2/95
-7
-6
SYM
tOFF
tORD
13
8
25
50
50
90
18
0
0
35
85
50
25
10,000
125,000
37
15
10
30
60
60
110
20
0
0
64
30
0
0
13
131
73
13
1
8
40
0
8
10
10
2-110
50
40
100
60
30
10,000
125,000
45
15
10
35
70
70
130
20
0
0
64
40
0
0
15
155
85
15
1
10
45
0
10
10
10
50
ns
ns
70
35
ns
ns
14
18
ns
10,000
125,000
50
ns
ns
ns
ns
ns
ns
64
50
0
0
20
185
100
20
1
15
55
0
15
10
10
ns
ms
17
19
26
ns
ns
ns
19
ns
ns
ns
21
ns
50
ns
ns
ns
ns
ns
ns
ns
21
25
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
MT4LC8M8E1/B6
8 MEG x 8 DRAM
,,,","coo,,,,
z
m
NOTES
All voltages referenced to Vss.
This parameter is sampled. Vee = +3.3V; f = 1 MHz.
Icc is dependent on cycle rates.
Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100~s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
S. AC characteristics assume IT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates,
100pF and VOL = O.SV and VOH = 2.0V.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, output data
will be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS must
be pulsed HIGH for tcP.
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
IS. Operation within the IRAD (MAX) limit ensures that
lRAC (MIN) and !CAC (MIN) can be met. IRAD
(MAX) is specified as a reference point only; if IRAD
is greater than the specified lRAD (MAX) limit, then
access time is controlled exclusively by tAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
1.
2.
3.
4.
MT4LC8M8El!B6
D19.pm5- Rev. 2/95
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition, and is not
referenced to VOH or VOL.
21. IWCS, IRWD, IAWD and ICWD are not restrictive
operating parameters. twcs applies to EARLY WRITE
cycles. If IWCS > twcs MIN, the cycle is an EARLY
WRITE cycle and the data output will remain an open
circuit throughout the entire cycle. tRWD, IAWD and
ICWD define READ-MODIFY-WRITE cycles. Meeting
these limits allows for reading and disabling output
data and then applying input data. The values shown
were calculated for reference allowing IOns for the
external latching of read data and application of write
data. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. IWCS, tRWD, ICWD and IAWD are not
applicable in a LATE WRITE cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
24. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE = LOW and
OE = HIGH.
25. twTS and IWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of IWRP and IWRH in the
CBR REFRESH cycle.
26. RAS-ONLY REFRESH requires that allS,192 rows of
the MT4LCSMSE1, or all 4,096 rows of the
MT4LCSMSB6, be refreshed at least once every 64ms.
CBR REFRESH, for either device, requires that at least
4,096 cycles be completed every 64ms.
27. The DQs open during READ cycles once IOD or IOFF
occur. If CAS goes HIGH before OE, the DQs will
open regardless of the state of OE. If CAS stays LOW
while OE is brought HIGH, the DQs will open. If OE
is brought back LOW (CAS still LOW), the DQs will
provide the previously read data.
2S. LATE WRITE and READ-MODIFY-WRITE cycles
must have both IOD and tOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. If OE is
taken back LOW while CAS remains LOW, the DQs
will remain open.
30. Column-address changed once each cycle.
2-111
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
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D19.pm5 - Rev. 2/95
2-113
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
MT4LC8M8E1/B6
8 MEG x 8 DRAM
","",CO"""
~-----------------------------------------------------
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D19.pm5- Rev. 2195
2-114
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
-------------------------------------------------------~
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MT4lC8M8E1/B6
019.pm5 - Rev. 2/95
2-115
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII:::I=ICN
1-·
MT4LC8M8E1/B6
8 MEG x 8 DRAM
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CBR REFRESH CYCLE
(Addresses and OE::;; DON'T CARE)
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HIDDEN REFRESH CYCLE 24
(WE::;; HIGH; OE ::;; LOW)
(READ)
(REFRESH)
~~___tM_S__t~RSH_·r===J-:--~t:-:--~
I~I~~I
ADDR
~:~::::
~~~
I
~~~~~~~~~~~~
OPEN-
too
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MT4LCBM8El/B6
DI9.pm5- Rev. 2/95
2-116
~
DON'TeARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC:RON
1-·
MT4C16257
256K x 16 DRAM
"'""""'"
256K x 16 DRAM
DRAM
5V, FAST PAGE MODE
• Industry-standard x16 pinouts, timing, functions
and packages
• High-performance CMOS silicon-gate process
• Single +5V ±10% power supply*
• Low power, 3mW standby; 375mW active, typical
• All device pins are fully TTL-compatible
• 512-cycle refresh in 8ms (nine rows and nine columns)
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
• FAST PAGE MODE access cycle
• BYTE WRITE access cycle
• BYTE READ access cycle
OPTIONS
40-Pin SOJ
(DA-7)
Vee
D01
-6*
-7
-8
1
40
D02
D03
2
3
4
D04
Vee
D05
5
6
7
39
38
37
36
35
34
D06
D07
DOS
NC
NC
8
9
10
11
12
13
14
15
16
17
18
19
20
WE
Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
""D
PIN ASSIGNMENT (Top View)
MARKING
• Timing
60ns access
70ns access
80ns access
RAS
NC
AO [
A1 [
A2 [
A3 [
Vee [
DJ
TG
• Part Number Example: MT4C16257DJ-7
*60ns specifications are limited to a Vee range of ±5%.
33
32
31
30
29
28
27
26
25
24
23
22
21
5
40/44-Pin TSOP
(DB-4)
Vss
D016
D015
D014
D013
Vss
D012
D011
D010
D09
NC
CASL
CASH
DE
AS
A7
A6
A.5
A4
Vss
Vee
D01
D02
D03
D04
Vee
D05
D06
D07
DOS
Vss
D016
D015
D014
D013
NC
NC
NC
CASL
WE
CAsH
DE
RAS
NC
AO
A1
A2
A3
Vee
AS
A7
A6
A5
A4
Vss
KEY TIMING PARAMETERS
SPEED
-6
-7
-8
tRC
110ns
130ns
150ns
tRAC
60ns
70ns
80ns
tpc
35ns
40ns
45ns
tAA
30ns
35ns
40ns
tCAC
15ns
20ns
20ns
tRP
40ns
50ns
60ns
GENERAL DESCRIPTION
The MT4C16257 is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x16 configuration. The MT4C16257 has both BYTE WRITE and
WORD WRITE access cycles via two CAS pins.
The MT4C16257 CAS function and timing are determined by the first CAS ( CASL or CASH)to transition LOW
and by the last to transition back HIGH. Use of only one of
MT4C16257
W03.pmS - Rev. 2195
•
."
FEATURES
the two results in a BYTE WRITE cycle. CASL transitioning
LOW selects a WRITE cycle for the lower byte (DQI-DQ8)
and CASH transitioning LOW selects a WRITE cycle for the
upper byte (DQ9-DQ16). BYTE READ cycles are achieved
through CASL or CASH in the same manner during READ
cycles for the MT4C16257.
2-117
Micron Technology, Inc., reserves the right
to change products or specifications without notice.
©1995, Micron Technology. Inc.
c
:rJ
»
5
MICRON
1-·
MT4C16257
256K x 16 DRAM
"'""'''''"'
FUNCTIONAL BLOCK DIAGRAM
•
WE
."
'"'C
S
DATA-IN BUFFER
C
::D
D01
••
l>
D016
3:
1+------0 OE
AO
A1
A2
A3
A4
A5
A6
A7
AS
512x512x16
MEMORY
ARRAY
RAS
o------I~~~~J====------.-J
~Vcc
-------..0
MT4C16257
W03.pm5 - Rev. 2195
2-118
Vss
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc
MICRON
1-·
MT4C16257
256K X 16 DRAM
",",owe,,",
FUNCTIONAL DESCRIPTION
Each bit is uniquely addressed through the IS address
bits during READ or WRITE cycles. These are entered 9 bits
(AO-AS) at a time. RAS is used to latch the first 9 bits and
CAS the latter 9 bits.
The CAS control also determines whether the cycle will
be a refresh cycle (RAS ONLY) or an active cycle (READ,
WRITE or READ WRITE) once RAS goes LOW.
The CASL and CASH inputs internally generate a CAS
signal functioning in an identical manner to the single
CAS input on the other 256K x 16 DRAMs. The key difference is each CAS controls its corresponding DQ tristate
logic (in conjunction with OE and WE). CASL controls DQl
through DQS and CASH controls DQ9 through DQI6.
The MT4C16257 CAS function is determined by the first
CAS (CASL or CASH) to transition LOW and the last one
to transition back HIGH. The two CAS controls give the
MT4C16257 both BYTE READ and BYTE WRITE cycle
capabilities.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. Taking WE LOW will initiate a
WRITE cycle, selecting DQl through DQI6. If WE goes
LOW prior to CAS going LOW, the output pints) remain
open (High- Z) until the next CAS cycle. If WE goes LOW
after CAS goes LOW and data reaches the output pins, dataout (Q) is activated and retains the selected cell data as long
as CAS and OE remain LOW (regardless of WE or RAS).
This late WE pulse results in a READ WRITE cycle.
The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O and pin direction is controlled
byOE.
MT4C16257
W03.pm5 - Rev. 2195
FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined (AO-AS) page boundary. The FAST _
PAGE MODE cycle is always initiated with a row-address
strobed-in by RAS followed by a column-address strobed- . "
in by CAS. CAS may be toggled by holding RAS LOW and
strobing-in different column-addresses, thus executing
faster memory cycles. Returning RAS HIGH terminates the
FAST PAGE MODE operation.
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby leveL
The chip is also preconditioned for the next cycle during the
RAS high time. Memory cell data is retained in its correct
state by maintaining power and executing any RAS cycle
(READ, WRITE) or RAS refresh cycle (RAS ONLY, CBR, or
HIDDEN) so that all 512 combinations of RAS addresses
(AO-AS) are executed at least every Sms, regardless of
sequence. The CBR REFRESH cycle will also invoke the
refresh counter and controller for row-address controL
1:::J
s:
0
:IJ
»
s:
BYTE ACCESS CYCLE
The BYTE WRITE mode is determined by the use of
CASL and CASH. Enabling CASL will select a lower BYTE
WRITE cycle (DQI-DQS) while enabling CASH will select
an upper BYTE WRITE cycle (DQ9-DQI6). Enabling both
CASL and CASH selects a WORD WRITE cycle.
The MT4C16257 can be viewed as two 256K x S DRAMS
which have common input controls, with the exception
of the CAS inputs. Figure 1 illustrates the MT4C16257
BYTE WRITE and WORD WRITE cycles.
The MT4C16257 also has BYTE READ and WORD READ
cycles. Figure 2 illustrates the MT4C16257 BYTE READ
and WORD READ cycles.
2-119
Micron Technology, Inc., reserves the right to change products or specifications Without notice.
©1995, Micron Technology, Inc.
MICRON
F·
MT 4C16257
256K x 16 DRAM
m~'mco,,,,,
1-------
•
WORD WRITE
---+-1------------
--I
LOWER BYTE WRITE
\~~~~~;-~
L-.J
."
""C
:s:
INPUT
STORED
DATA
C
:xl
LOWER BYTE
(D01-DQ8)
OFWQRD
l>
s:
UPPER BYTE
(009-0016)
OF WOAD
~
~
DATA
STORED STORED
DATA
---:.-
:
:
---3>
DATA
DATA
~o
~
~
1
--"0>
0
0
0
0
---3>
0
--,.;;,.
-_.3>
-: ;-:~:
--+
-----3>
-----'"
0
------".
1
1 -----'"
1 -----;..
1
1
-----J>
1
INPUT
INPUT
DATA
STORED
-->Dr~TA
--3>
1
--:;:-
0
--3>
1
--".
1
-+
1
--3>
1
--3>
1
ADDRESSO _ _ ••- - - -
x'" NOT EFFECTIVE (DON'T CARE)
Figure 1
WORD AND BYTE WRITE EXAMPLE
I
+ - - - - - WORD READ
----1...-----
LOWER BYTE READ
-I
RAS
STORED
DATA
OUTPUT
DATA
OUTPUT
DATA
LOWER BYTE
(DQ1-0Q8)
QFWORD
UPPER BYTE
(009-0016)
OF WORD
r
~
----;0.
1
--·".1
---3>
1
1
---3>
- ---3>
0
----3>
1
---'"
1
---3>
0
STORED STORED
DATA
STORED
OATA
DATA
~~
~~
-----3>
1
ADDRESS 0 - - - - - - J o o . ~---~
ADDRESS 1 ----~I
Z .. High-Z
Figure 2
WORD AND BYTE READ EXAMPLE
MT4C16257
W03.pm5 - Rev. 2195
2-120
Micron Technology, Inc., reserves the right to change products or spectfications without notice.
©1995, Micron Technology, Inc.
TRUTH TABLE
ADDRESSES
IR
IC
FUNCTION
RAS
CASL
CASH
WE
OE
Standby
H
H-X
H-X
X
X
X
X
DOs
READ: WORD
L
L
L
H
L
ROW
COL
Data-Out
READ: LOWER BYTE
L
L
H
H
L
ROW
COL
Lower Byte, Data-Out
Upper Byte, High-Z
READ: UPPER BYTE
L
H
L
H
L
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-Out
WRITE: WORD
(EARLY WRITE)
L
L
L
L
X
ROW
COL
Data-In
WRITE: LOWER
BYTE (EARLY)
L
L
H
L
X
ROW
COL
Lower Byte, Data-In
Upper Byte, High-Z
WRITE: UPPER
BYTE (EARLY)
L
H
L
L
X
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-In
READ WRITE
NOTES
High-Z
'tJ
s:
C
JJ
»
s:
L
L
L
H-L
L-H
ROW
COL
Data-Out, Data-In
1,2
PAGE-MODE
1st Cycle
L
H-L
H~L
H
L
ROW
COL
Data-Out
2
READ
2nd Cycle
L
H-L
H-L
H
L
n/a
COL
Data-Out
2
PAGE-MODE
1st Cycle
L
H-L
H-L
L
X
ROW
COL
Data-In
1
WRITE
2nd Cycle
L
H-L
H-L
L
X
n/a
COL
Data-In
1
PAGE-MODE
1st Cycle
L
H-L
H-L
H-->L
L-->H
ROW
COL
Data-Out, Data-In
1,2
L
H-L
H-L
H-->L
L-H
n/a
COL
Data-Out, Data-In
1,2
2
1,3
READ-WRITE 2nd Cycle
HIDDEN
READ
L-H-L
L
L
H
L
ROW
COL
Data-Out
REFRESH
WRITE
L-H-L
L
L
L
X
ROW
COL
Data-In
L
H
H
X
X
ROW
n/a
High-Z
H-->L
L
L
X
X
X
X
High-Z
RAS-ONLY
REFRESH
CBR REFRESH
NOTE:
1.
2.
3.
4.
MT4C16257
W03.pmS - Rev. 2195
4
These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active).
These READ cycles may also be BYTE READ cycles (either CASL or CASH active).
EARLY WRITE only.
At least one of the two CAS signals must be active (CASL or CASH).
2-121
•"
Micron Technology, Inc., reseIVes the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT4C16257
256K x 16 DRAM
"'""""""
ABSOLUTE MAXIMUM RA TINGS*
Voltage on Vee Supply Relative to Vss .............. -IV to +7V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55°C to +150°C
Power Dissipation .......................................................... I.2W
Short Circuit Output Current ..................................... 50mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vee = +5V ±1 0%**)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
Ii
-2
2
IlA
loz
-10
10
!lA
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV ,;; VIN ,;; Vcc
(All other pins not under test = OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV ,;; VOUT ,;; 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT = -5mA)
Output Low Voltage (lOUT = 4.2mA)
NOTES
V
VOL
0.4
V
MAX
SYMBOL
-6**
-7
-8
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
Icc1
2
2
2
mA
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
Icc2
1
1
1
mA
25
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIND
Icc3
195
175
160
mA
3,4,41
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: tpc = tpc [MIN]; tcp, tASC = 10ns)
Icc4
120
110
100
mA
3,4,41
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS=VIH: tRC = tRC [MIND
Iccs
195
175
160
mA
3,41
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIND
Icc6
180
160
140
mA
3,5
PARAMETER/CONDITION
UNITS NOTES
**60ns specifications are limited to a Vcc range of ±5%.
MT4C16257
W03.pmS - Rev. 2195
2-122
Micron Technology, Inc., reseIV6S the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT4C16257
256K X 16 DRAM
","'Ow,",",
CAPACITANCE
PARAMETER
SYMBOL
Input Capacitance: AO-AB
CI1
Input Capacitance: RAS, CASL, CASH, WE, OE
CI2
Input/Output Capacitance: DQ (SOJ, TSOP)
CIO
MAX
5
7
7
UNITS
NOTES
pF
2
pF
2
pF
2
•"
"tJ
3:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
AC CHARACTERISTICS
PARAMETER
-6'
-8
-7
SYM
MIN
Access time from column-address
Column-address hold time
(referenced to RAS)
tAA
tAR
50
55
60
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time (CBR REFRESH)
last CAS going lOW to first CAS
returning HIGH
tASC
tASR
tAWD
tCAC
tCAH
0
0
55
0
0
60
0
0
65
tClZ
tcp
3
10
tCPA
tCRP
tCSH
tCSR
tCWD
Data-in hold time (referenced to RAS)
Data-in setup time
tDHR
tDS
Output disable time
Output Enable time
OE hold time from WE during
READ-MODIFY-WRITE cycle
toD
tOE
tOEH
Output buffer turn-off delay
tOFF
teWl
tDH
MIN
10,000
15
20
10
10
15
3
10,000
3
10
15
15
UNITS
40
ns
ns
20
15
20
10
10
40
10,000
45
10
10
70
10
45
20
15
45
20
15
55
0
3
60
0
3
3
MAX
3
10
80
10
15
20
20
15
MIN
20
35
10
60
10
40
15
10
45
0
3
MAX
35
15
tClCH
CAS to output in low-Z
CAS precharge time
Access time from CAS precharge
CAS to. RAS precharge time
CAS hold time
CAS setuptime (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
MAX
30
10
15
10
10
teAS
tCHR
15
20
20
15
3
15
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
29
21
15,31
29
37
5,30
32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
31
16,34
31
30
30
5,29
21,29
26,30
22,31
ns
20,28,31
22,31
28,39
31
27
*60ns specifications are limited to a Vce range of ±5%.
MT4C16257
W03.pm5 - Rev. 2195
c
JJ
(Notes: 6, 7, B, 9, 10, 11,12,13) (Vee = +5V ±10%*)
2-123
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
»
:s:
MICRON
1-·
MT 4C16257
256K x 16 DRAM
,,,","wO'"'
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
•
(Notes: 6, 7, 8, 9,10,11,12,13) (Vee = +5V ±10%*)
AC CHARACTERISTICS
PARAMETER
tORD
0
0
0
ns
tpc
35
40
45
ns
33
tpRWC
85
95
100
ns
33
Access time from RAS
RAS to columnaddress delay time
tRAC
tRAD
15
ns
ns
14
18
Row-address hold time
tRAH
10
10
Column-address to
RAS lead time
tRAL
30
35
60
Random READ or WRITE cycle time
tRAS
tRASP
tRC
60
110
-n
s:
FAST-PAGE-MODE READ or WRITE
cycle time
C
:D
»
S
FAST-PAGE-MODE READ-WRITE
cycle time
RAS pulse width
RAS pulse width (PAGE MODE)
MAX
MIN
-8
MIN
OE setup prior to RAS during
HIDDEN REFRESH cycle
"'0
-7
-6'
SYM
60
RAS to CAS delay time
tRCD
20
Read command hold time
(referenced to CAS)
Read command setup time
tRCH
0
tRCS
0
Refresh period (512 cycles)
tREF
tRP
30
10,000
100,000
15
70
70
MAX
70
35
20
80
40
UNITS
ns
10,000
80
10,000
ns
80
150
100,000
ns
ns
50
20
60
0
0
0
8
NOTES
ns
100,000
0
8
15
MAX
10
40
130
45
MIN
8
ns
17,29
ns
19,26,30
ns
26,29
ms
40
10
50
tRPC
10
60
10
Read command hold time
(referenced to RAS)
tRRH
0
0
0
ns
ns
19
RAS hold time
tRSH
tRWC
15
20
20
ns
38
150
175
ns
85
15
95
195
105
ns
21
20
20
ns
26
ns
ns
26,38
RAS precharge time
RAS to CAS precharge time
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
Write command hold time
(referenced to RAS)
Write command setup time
Write command pulse width
tRWD
tRWL
IT
twCH
tvvCR
3
10
45
twcs
twp
0
10
50
3
10
50
3
10
ns
50
55
60
ns
26
0
10
0
10
ns
21,26,29
ns
26
*60ns specifications are limited to a Vcc range of ±5%_
MT4C16257
W03.pm5-Rev.2195
2-124
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT4C16257
256K x 16 DRAM
",,""e"",,"
NOTES
1.
2.
3.
4.
All voltages referenced to Vss.
This parameter is sampled. Vee = SV ±lO%;f = 1 MHz.
Ice is dependent on cycle rates.
Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (DoC :S TA :S 70°C) is assured.
7. An initial pause of 100~s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR) before proper device operation is assured. The
eight RAS cycle wake-ups should be repeated any
time the tREF refresh requirement is exceeded.
8. AC characteristics assume IT = Sns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF, VOL = 0.80 and VOH = 2.0V.
14. Assumes that tRCD < lRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that tRCD
exceeds the value shown.
15. Assumes that tRCD ~ tRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the Q buffer, CAS must be pulsed
HIGH for tcP.
17. Operation within the tRCD (MAX) limit ensures that
tRAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if lRCD is greater than the
specified tRCD (MAX) limit, access time is controlled
exclusively by tCAe.
18. Operation within the tRAD limit ensures that tRCD
(MAX) can be met. tRAD (MAX) is specified as a
reference point only; if tRAD is greater than the
specified tRAD (MAX) limit, access time is controlled
exclusively by tAA.
MT4C16257
W03.pm5 - Rev. 2195
19. Either tRCH or tRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition; it is not a
reference to VOH or VOL. The 3ns minimum is a
parameter guaranteed by design.
21. twcs, lRWD, tAWD and tcWD are restrictive
operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. If twcs ~ twcs (MIN),
the cycle is an EARLY WRITE cycle and the data
output will remain an open circuit throughout the
entire cycle. IflRWD ~ tRWD (MIN), tAWD ~ tAWD
(MIN) and tCWD ~ tCWD (MIN), the cycle is a READ
WRITE and the data output will contain data read
from the selected cell. If neither of the above
conditions is met, the state of Q (at access time and
until CAS or OE goes back to VIH) is indeterminate.
OE held HIGH and WE taken LOW after CAS goes
LOW results in a LATE WRITE (OE-controlled) cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. During a READ cycle, if OE is LOW then taken HIGH
before CAS goes HIGH, Q goes open. If OE is tied
permanently LOW, a LATE WRITE or READMODIFY-WRITE operation is not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and
OE = HIGH.
25. All other inputs at Vee -0.2V.
26. Write command is defined as WE going LOW.
27. LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide the previously written data if CAS
remains LOW and OE is taken back LOW after tOEH
is met. If CAS goes HIGH prior to OE going back
LOW, the DQs will remain open.
28. The DQs open during READ cycles once tOD or tOFF
occur. If CAS goes HIGH before OE, the DQs will
open regardless of the state of the OE. If CAS stays
LOW while OE is brought HIGH, the DQs will open.
If OE is brought back LOW (CAS still LOW), the DQs
will provide the previously read data.
2-125
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
-n
""0
S
C
Jl
»
S
MIC:RON
F·
MT4C16257
256K x 16 DRAM
",""OU",,"'
NOTES (continued)
•"
"tJ
s:
29. The first CASx edge to transition LOW.
30. The last CASx edge to transition HIGH .
31. Output parameter (DQx) is referenced to corresponding CAS input, DQI-DQ8 by CASL and DQ9-DQ16
by CASH.
32. Last falling CASx edge to first rising CASx edge.
33. Last rising CASx edge to next cycle's last rising CASx
edge.
34. Last rising CASx edge to first falling CASx edge.
35. First DQs controlled by the first CASx to go LOW.
36. Last DQs controlled by the last CASx to go HIGH.
37. Each CASx must meet minimum pulse width.
38. Last CASx to go LOW.
39. All DQs controlled, regardless CASL and CASH.
40. Column-address changed once each cycle.
C
lJ
l>
s:
MT4C16257
W03.pm5 - Rev. 2/95
2-126
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT4C16257
256K x 16 DRAM
"'~"coc,"
READ CYCLE
•
IRP
tRAS
\
ICSH
I~
IAR
-! 1-""
;wzt
leAS
tRCD
.1
tRAD
I
KW";0
tRAL
I
iCLCH
ROW
COLUMN
~
'ACS
!/IIIIIIIII/;
I
I
I
~g~-
VlIIIIIIIIIIIIIIIIIII/;
1NOTE I
1M
tRAC
I
'CAG
10FF
~t
DO
s:
I
1
~I
~I
~I
ROW
~I
"TI
"tJ
'RRH
'ASH
OPEN
~I
OPEN--
VALID DATA
~I
_IO_E_
EARLY WRITE CYCLE
IRP
tRAS
-
----
d::
tCSH
CASLandCASH
VIH
VIl
~J~:
tRCD
IAR
I . I
IRAD
~:~ ::w'~
ROW
'CLCH
1
I~I I~I
[~ ~I
ADDR
IRAL
1
~;;:)i
COLUMN
'CWL
I
I
'RWl
r
I
ROW
.1
I I
I
I~I I~
'WCR
IWp
,I
I I
I
I
tDHR
1:221 DON'T CARE
~
MT4C16257
W03.pm5 - Rev. 2/95
2~127
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©199S, Micron Technology, Inc.
C
lJ
»
s:
MICRON
1-·
MT4C16257
256K x 16 DRAM
"'"",w", '"'
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
•"
R
, we
'RP
tRAS
tCSH
f~
~
~I
~:~ ~,---_R--,ow_--,jl,--------,-,-.=:-b-///I;I/////I;I$////I;II;I/J$//I;I~
'"tJ
IRSH
:s:
J~
CASL and CASH
IRCD
'CLCH
'CAS
V IH
VIL _
'AR
C
'RAD
1
~
:tJ
»
:s:
ADDR
~I
•
WE
1
I
tRAL
I~
I
1
Irl
I
I
'e WL
'R'VO
I'I
~
leWD
IAWD
'WP
1
l
VIH
VIL
I
I
I 'AA
I 'CAG
tCLZ-~
tRAC
1
VALID DOUT
OPEN
~
JI~~I
K
OPEN--
VALID DIN
~I
~
FAST-PAGE-MODE READ CYCLE
'RASP
CASLBnd CASH
VIH
_:-+-T.--------,~
VIL
-
'---1'-----'1
1
AA
'cPA
\
'CAG
AA
'eLZOQ
~:g~
OPEN
1
tRAC
j
'CAG
1:-
tOFF
-
'eLZ-
VALID
DATA
~ ~
1:-
-
tOFF
-~
I-
'CAG
tCLZ-
1:-
VALID
VALID
'~
~
~
-
~
,~
---tOFF
f---
~
tz23 DON'T CARE
~
MT4C16257
W03.pm5 - Rev. 2195
2-128
UNDEFINED
Micron Technology, Inc"reservesthe nghlto change producls or spec iflcationswlthoutnotice.
©1995, Micron Technology, Inc.
MIC:RON
1-·
MT4C16257
256K X 16 DRAM
",",oeoo,,",
FAST-PAGE-MODE EARLY-WRITE CYCLE
tCSH
CAsLandCASH
VIH
_,--J,--++---------r~
'-1'-----1
VIL -
ROW
DE
~:~
-1///lI///!!III!1/IIII//!/1////III!I!/I/I/II//!/1///1/1/I/1/1$//I$//I/I/////$//I//I!III//I//$/1/$//ImwElt0
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
RASP
RP
~
DONTCARE
; ] UNDEFINED
'NOTE:
IpCis for LATE WRITE only.
MT4C16257
W03.pmS - Rev. 2/95
2-129
Micron Technology, Inc., reserves the right to change products or specifications without notioo.
©1995, Micron Technology, Inc.
MIr::~CN
1-·
MT4C16257
256K x 16 DRAM
r-I;;"
RAS-ONLY REFRESH CYCLE
(Addresses; OE, WE = DON'T CARE)
•
~:~ :·---,e-RP---"~
RAS
."
~=
-
~---
eAbd~ ~:~ ~:J
II
'------l
~:~ :WJd~ROW~k$//$//$I$//$I$$#$I/$#,1;(r---ROW--
"'tJ
s::
ADDR
C
JJ
~g~
Q
::-----------OPEN'----------
l>
s:
CBR REFRESH CYCLE
(Addresses and OE DON'T CARE)
=
'RAS
'AP
.~
CASL and CASH
~:~:
DQ
-
WE
'RP
'RAS
Y
1
1
II
tRPC~
teSR
'e"R
k
..
~Ib
~:~ WI/f/f1//;7)
NOTE t
OPEN-7.II-----~II~
WI!!III/f1/ffflffM~
~/fl/lllll/fff1II/f1!!1!!/f/f~
HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
(READ)
(REFRESH)
'RAS
tCHR
ADOR
~:t:wa~~~~ll2§l8t=~~~~~~W1W1~~~W1~~~~
J
VALID DATA
-'OFF
OPEN-
~
DON'T CARE
~UNDEFINED
NOTE:
MT4C16257
W03.pm5 - Rev. 2195
1. WRP and WRH are for system design reference only. The WE signal is actually a "don't care" at RAS time
during a CSR REFRESH. However, WE should be held HIGH at RAS time during a CSR REPRESH to
ensure compatibility with other DRAMs which require WE HIGH at RAS time during a CSR REFRESH.
2~130
Micron Technology, bro., reserves the right to change products or speclflcatlons without notice.
©1995, Micron Techndogy, Inc.
ADVANCE
MICRON
1-·
CCH'
MT4LC16257(S)
256K x 16 DRAM
'"
256K ,x 16 DRAM
DRAM
3.3V, FAST PAGE MODE,
OPTIONAL SELF REFRESH
II
."
"tJ
FEATURES
• Industry-standard x16 pinouts, timing, functions
and packages
• High-performanc~ CMOS silicon-gate process
• Single +3:3V ±O.3V power supply*
• Low power, O.3mW standby; 150mW active, typical
• All device pins are fully LVTTL-compatible
• 512-cycle refresh in 8ms (MT4LC16257) or 64ms
(MT4LC16257 S)
• Refresh modes: RAS ONLY, CA5-BEFORE-RAS (CBR),
HIDDEN and optional Extended and SELF
• FAST PAGE MODE access cycle
• BYTE WRITE access cycle
• BYTE READ access cycle
• Symmetrical addressing (nine tows, nine columns)
C
40-Pin SOJ
(OA-7)
40
39
0016
38
37
001'5
0014
0013
002
003
3
DQ4
Vee
6
~6'
DOB
'NC
-7
-8
• Refresh Rate
None
512-cycle refresh in 8IRS
512-cycle refresh in 64ms, SELF REFRESH
S
9
10
33
32.
Vss
.OQI2
0011
31
0010
009
NC
CASL
DQl
DQ2
'DQ3
DQ4
Vee
Vss
0016
0015
D014
DQ13
Vss
DQ5
DQ6
DQ7.
DaB
0012
0011
DQ10
000
NC
NC
WE'
NC
CASL
CASH
NC
11
12
30
29
WE
RAS
13
14
;28
27
CASH
OE
NC
15
16
26
25
AB
A?
17
18
24
'23
A6
AS
A3
A?
A6
AS
A4
19.
22
21
A4
Vec
Vss
Vss
AD
AI
A2
A3
Vee
• Packages
Plastic SOJ (400 mil)
Plastic TSOP (400 mil)
34
006
DQ?
36
'35
40/44-Pin TSOP
(OB-4)
Vee
Vee
MARKING
• Timing
60ns access
70nsaccess
80ns access
V__
001
DQ5
OPTIONS
s::
PIN ASSIGNMENT (Top View)
20
RAS·
OE
.NC.
Aa
46
Al
A2
DJ
TG
• Part Number Example: MT4LC16257DJ-7 S
'60ns specifiCations are limited to a Vee range of ±O.ISV.
KEY TIMING PARAMETERS
SPEED
-6
-7
-8
'RC
110ns
130ns
150ns
'RAC
60ns
70ns
80ns
'PC
35ns
40ns
45ns
'AA
30ns
35ns
40ns
'CAC
15ns
20ns
20ns
'RP
40ns
50ns
60ns
GENERAL DESCRIPTION
The MT4LC16257(S) is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x16 configuration. The MT4LC16257(S) has both BYTE WRITE and
WORD WRITE access cycles via two CAS pins. CASL and
CASH function in an identical manner to CAS in that either
CASL or CASH will generate an internal CAS.
MT4LCl6257(S)~
W04.pm5 - Rev. 2/95
The MT4LC16257(S) CAS function and timing are determined by the first CAS ( CASL or CASH) to transition LOW
and by the last to transition back HIGH. Use of only one of
the two results in a BYTE WRITE cycle. CASL transitioning
LOW selects a WRITE cycle for the lower byte (DQI-DQ8)
and CASH transitioning LOW selects a WRITE cycle for the
upper byte (DQ9-DQ16). BYTE READ cycles are achieved
through CASL or CASH in the same manner during READ
cycles for the MT4LC16257(S).
2-131
Micron Technology, Inc., reS9NeS the right to change products Of specifications without nQtlce.
@1995, Micron Technology, Inc.
:c
»
s::
ADVANCE
MU::::I=ICN
I-I
c"
MT 4LC16257(S)
256K x 16 DRAM
,
. FUNCTIONAL BLOCK DIAGRAM
WE
DATA-IN BUFFER
001
••
0016
!-----oOE
AD
A1
k2.
A3
A4
AS
A6
A7
AS
512x512x16
MEMORY
ARRAY
MT4LC16257(S)
W04.pm5 - Flev. 2195
2-132
+----0
Vee
+----0
Vss
Micron Technology, Inc., reserves the right to change products or specifications without notice.
01995, MIcron Technology,lnc.
ADVANCE
MICRON
1-·
MT4LC16257(S)
256K x 16 DRAM
,ec~"ocoo""'
FUNCTIONAL DESCRIPTION
Each bit is uniquely addressed through the lS address
bits during READ or WRITE cycles. These are entered 9 bits
(AO-AS) at a time. RAS is used to latch the first 9 bits and
CAS the latter 9 bits.
The CAS control also determines whether the cycle will
be a refresh cycle (RAS ONLY) or an active cycle (READ,
WRITE or READ WRITE) once RAS goes LOW.
The CASL and CASH inputs internally generate a CAS
signal functioning in an identical manner to the single
CAS input on the other 256K x 16 DRAMs. The key difference is each CAS controls its corresponding DQ tristate
logic (in conjunction with OE and WE). CASL controls DQ1
through DQS and CASH contr()ls DQ9 through DQ16.
The CAS function is determined by the first CAS (CASL
or CASH) to transition LOW and the last one to transition
back HIGH. The two CAS controls provide BYTE READ
and BYTE WRITE cycle capabilities.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. Taking WE LOW will initiate a
WRITE cycle, selecting DQ1 through DQ16. If WE goes
LOW prior to CAS going LOW, the output pin(s) remain
open (High- Z) until the next CAS cycle. If WE goes LOW
after CAS goes LOW and data reaches the output pins, data-
1--------
WORD WRITE
out (Q) is activated and retains the selected cell data as long
as CAS and OE remain LOW (regardless of WE or RAS).
•
This late WE pulse results in a READ WRITE cycle.
The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O and pin direction is controlled "
byOE.
FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODiFY-WRITE) within a
row-address-defined (AO-AS) page boundary. The FAST
PAGE MODE cycle is always initiated with a row-address
strobed-in by RAS followed by a column-address strobedin by CAS. CAS may be toggled by holding RAS LOW and
strobing-in different column-addresses, thus executing ):>
faster memory cycles. Returning RAS HIGH terminates the
FAST PAGE MODE operation.
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is also preconditioned for the next cycle during the
RAS high time. Memory cell data is retained in its correct
state by maintaining power and executing any RAS cycle
(READ, WRITE) or RAS refresh cycle (RAS ONLY, CBR, or
HIDDEN) so that all 512 combinations of RAS addresses
(AO-AS) are executed at least every Sms, regardless of
sequence. The CBR REFRESH cycle will also invoke the
refresh counter and controller for row-address control.
'"tJ
:s:
C
:c
:s:
~I------ LOWER BYTE WRITE
------+1
RAS~~~
\~----~/
CASH
WE
STORED
DATA
LOWER BYTE
(001-008)
OF WORD
UPPER BYTE
(009-0016)
OF WORD
~
I
INPUT
INPUT
STORED STORED
'.'-"~~' ~.io,TA
0·--,
-----:'i>
1 -----?<>1 -----;;>
1
1
I;::
INPUT
1
-----------------3> 1
-----------------71
-----------------3>-
- - - - - - - - - ----;;>
1
x-::::::r'·
-------------".
1
-------- •.• --",.
0
-------------".1
-------------;;>
-----3>-
1 -----;;>
1
X
-----;;>
1
1
X - -
-----3>-
STORED
T.. {~r
DATA.•
mm
• • •~ j-~~:
-----r
INPUT
-
------------.3'-
1
1
-----------3'-
1
I~-- ADDRESSO ~- - - - - - ADDRESS1
----I
x = NOT EFFECTIVE (DON'T CARE)
Figure 1
WORD AND BYTE WRITE EXAMPLE
MT4LC16257(S)
W04.pm5 - Rev. 2/95
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII:::::I=ICN
F·
MT4LC16257(S)
256Kx 16 DRAM
,cc"",coe",,,
BYTE ACCESS CYCLE
The .BYTE WRITE mode is determined by the use of
CASL and CASH. Enabling CASL will select a lower BYTE
WRITE cycle (DQI-DQ8) while enabling CASH will select
an upper BYTE WRITE cycle (DQ9-DQ16). Enabling both
CASL and CASH selects a WORD WRITE cycle.
The MT4LC16257(S) can be viewed as two 256K x 8
DRAMS which have common input controls, with the
exception of the CAS inputs. Figure 1 illustrates the
MT4LC16257(S) BYTE WRITE and WORD WRITE cycles.
The MT4LC16257(S) also has BYTE READ and WORD
READ cycles, since it uses two CAS inputs to control its
byte accesses. Figure 2 illustrates the MT4LC16257(S) BYTE
READ and WORD READ cycles.
power data retention mode or a dynamic refresh mode at
the extended refresh period.
The optional SELF REFRESH feature is initiated by
performing a CBR REFRESH cycle and holding RAS LOW
for the specified tRASS. Additionally, the "5" version allows for an extended refresh rate of 1251ls per row if
using distributed CBR REFRESH. This refresh rate can be
applied during normal operation or during a standby mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum time oftRPS (=tRC). This delay allows
for the completion of any internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all rows must be
refreshed within 300lls prior to the resumption of normal
operation.
REFRESH
An optional SELF REFRESH mode is also available. The
"5" version allows the user the choice of a fully static low-
1----
WORD READ
---
~I""
LOWER BYTE READ
--------------I
RAS
\~----~/
CASL
\c------'
CASH
WE
LOWER BYTE
(OQ1-0Q8)
OF WORD
UPPER BYTE
(OQ9-0Q16)
OF WORD
-.-J
STORED
OUTPUT
OUTPUT
DATA
DATA
DATA
~
~
L
\-.--/
--:;:..
----:;:..
1
1
-----:;:..
-----:;:..
-----:;:..
0
1
1
1
-----:;:..
1
-----:;:..
0
1
._-_._:;:..
----:;:..
0
1
0
-----:;:..
0
--
0
0
----:;:..
Z
--:;:..
----3>-
STORED STORED
DATA
DATA
~~
[~
ADDRESS 0 _____________
,
OUTPUT
OUTPUT
STORED
DATA
DATA
DATA
-----:;>
.,.
1
1
-"---p
0
-----?;>
1
1
1
-- .
---p
---»
- ---;;>
--.?
1
1
---_.",.
Z
-----p z
---:;;. z
z
-----:;:.
-----;>
Z
--9
Z
Z
- ---;>
ADDRESS 1
~
~
Z",High-Z
Figure 2
WORD AND BYTE READ EXAMPLE
MT4LC16257(S)
W04.pm5 - Rev. 2f9~
2~134
Micron Technology, l'le., reserves the righllo change products or specifications without notice.
©1995, Micron Technology. Inc.
ADVANCE
MICRON
1-·
MT4LC16257(S)
256Kx 16 DRAM
","",,,,,,
TRUTH TABLE
ADDRESSES
tR
IC
RAS
CASL
CASH
WE
OE
Standby
H
H~X
H~X
X
X
X
READ: WORD
L
L
L
H
L
ROW
COL
Data-Out
READ: LOWER BYTE
L
L
H
H
L
ROW
COL
Lower Byte, Data-Out
Upper Byte, High-Z
READ: UPPER BYTE
L
H
L
H
L
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-Out
WRITE: WORD
(EARLY WRITE)
L
L
L
L
X
ROW
COL
Data-In
WRITE: LOWER
BYTE (EARLY)
L
L
H
L
X
ROW
COL
Lower Byte, Data-In
Upper Byte, High-Z
WRITE: UPPER
BYTE (EARLY)
L
H
L
L
X
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-In
FUNCTION
X
DOs
NOTES
High-Z
."
"tJ
s:
C
::c
l>
s:
L
L
L
H~L
L~H
ROW
COL
Data-Out, Data-In
1,2
PAGE-MODE
1st Cycle
L
H~L
H~L
H
L
ROW
COL
Data-Out
2
READ
2nd Cycle
L
H~L
H~L
H
L
nla
COL
Data-Out
2
PAGE-MODE
1st Cycle
L
H~L
H~L
L
X
ROW
COL
Data-In
1
WRITE
2nd Cycle
L
H~L
H~L
L
X
nla
COL
Data-In
1
PAGE-MODE
1st Cycle
L
H~L
H~L
H~L
L~H
ROW
COL
Data-Out, Data-In
1,2
1,2
READ WRITE
READ'WRITE 2nd Cycle
L
H~L
H~L
H~L
L~H
nla
COL
Data-Out, Data-In
L
L
H
L
ROW
COL
Data-Out
2
1,3
HIDDEN
READ
L~H~L
REFRESH
WRITE
L~H~L
L
L
L
X
ROW
COL
Data-In
L
H
H
X
X
ROW
nla
High-Z
CBR REFRESH
H~L
L
L
X
X
X
X
High-Z
SELF REFRESH
(MT4C16257 S only)
H~L
L
X
X
X
X
X
High-Z
RAS-ONLY
REFRESH
NOTE:
1.
2.
3.
4.
MT4lC162S7(S)
W04.pmS - Rev. 2/95
4
These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active).
These READ cycles may also be BYTE READ cycles (either CASL or CASH active)..
EARLY WRITE only.
At least one of the two CAS signals must be active (CASL or CASH).
2-135
•
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
'Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
•
."
Voltage on Vee Supply Relative to Vss ........... -IV to +4.6V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SsoC to +ISO°C
Power Dissipation .......................................................... 1.2W
Short Circuit Output Current ..................................... SOmA
'"C
s:
C
:xJ
l>
s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (O°C $ T A $ 70°C; Vee = +3.3V ±O.3V**)
PARAMETER/CONDITION
Supply Voltage
SYMBOL
MIN
MAX
UNITS
V
Vee**
3.0
3.6
Input High (Logic 1) Voltage, all inputs
VIH
2.0
Vec+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
II
-2
2
fJA
loz
-10
10
fJA
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV $ VIN $ Vcc
(All other pins not under test =OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV $ VOUT < 3.6V)
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT =2mA)
VOL
NOTES
V
0.4
V
**60ns specifications are limited to a Vce range of ±0.15V.
MT4LC16257(S)
W04.pm5 - Rev. 2/95
2-136
Micron Technology, Inc., reserves the right to change products or speCifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UU:::RCN
1-·
MT4LC16257(S)
256K X 16 DRAM
,,,","coe,,",
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc
=+3.3V ±0.3V**)
PARAMETER/CONDITION
SYMBOL
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
-6""
MAX
-7
-8
Icc1
1
1
1
mA
UNITS NOTES
STANDBY CURRENT: (CMOS)
Icc2
500
500
500
IlA
25
=CAS =Vcc -0.2V)
Icc2
(S only)
100
100
100
!-!A
25
Icc3
120
110
100
mA
3,4,40
Icc4
70
60
50
mA
3,4,40
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS =VIH: IRC =IRC [MIN])
Icc5
120
110
100
mA
3
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC
Icc6
120
110
100
mA
3,5
REFRESH CURRENT: Extended (S version only)
Average power supply current, CAS =0.2V or CBR cycling;
IRAS =tRAS (MIN); WE, AO-A8 and DIN =Vcc-0.2V or 0.2V
(DIN may be left open)
Icc7
(S only)
150
150
150
!-!A
3,5
REFRESH CURRENT: SELF (S version only)
Average power supply current, CBR cycling with tRAS ~ IRASS (MIN)
and CAS held LOW; WE =Vcc-0.2V; AO-AS and
DIN =Vcc-0.2V or 0.2V (DIN may be left open)
Icca
(S only)
150
150
150
IlA
5,41
(RAS
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC =IRC [MIN])
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS =VIL, CAS, Address Cycling:
IpC =IpC [MIN]; ICp, IASC = 10ns)
=IRC [MIN])
**60ns specifications are limited to a Vcc range of ±0.15V.
MT4LC16257(S)
W04.pm5- Rev. 2/95
2-137
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, IIlC.
•
-n
"tJ
s:
C
:D
»
s:
ADVANCE
MICRON
1-·
MT4LC16257(S)
256K X 16 DRAM
,""'0'0,"'"
CAPACITANCE
•
-n
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: AD-A8
Cll
pF
Input Capacitance: RAS, CASL, CASH, WE, OE
CI2
InpuVOutput Capacitance: DO (SOJ, TSOP)
CIG
5
7
7
2
2
2
PARAMETER
pF
pF
"tJ
s:
C
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
»
s:
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
::c
=+3.3V ±D.3V*)
-7
-6'
-8
AC CHARACTERISTICS
PARAMETER
SYM
Access time from column-address
tAA
Column-address hold time
(referenced to RAS)
tAR
50
55
60
ns
Column-address setup time
Row-address setup time
tASC
tASR
0
0
0
ns
0
0
0
ns
55
MIN
MAX
MIN
30
MAX
MIN
35
Column-address to WE delay time
tAWD
Access time from CAS
tCAC
Column-address hold time
CAS pulse width
tCAH
tCAS
10
15
CAS hold time entering
SELF REFRESH
CAS hold time (CBR REFRESH)
tCHD
10
10
20
10
10,000
20
15
20
UNITS
40
ns
29
ns
21
ns
15,31
10,000
ns
ns
29
37
ns
41
15
10,000
NOTES
20
65
60
15
MAX
tCHR
10
10
10
ns
5,30
tCLCH
10
10
10
ns
32
tCLZ
tcp
3
10
3
10
3
10
ns
ns
CAS to RAS precharge time
tCPA
tCRP
8
CAS hold time
tCSH
60
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
tCSR
tCWD
10
40
15
Last CAS going LOW to first CAS
returning HIGH
CAS to output in
Low-Z
CAS precharge time
Access time from CAS preeharge
Data-in hold time
tCWL
tDH
Data-in hold time (referenced to RAS)
Data-in setup time
tDHR
tDS
Output disable time
Output Enable time
OE hold time from WE during
READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OE setup prior to RAS during
HIDDEN REFRESH cycle
tOD
tOE
35
40
45
ns
10
ns
10
45
80
10
45
ns
ns
ns
21,29
20
20
26,30
22,31
10
70
10
15
15
ns
ns
45
55
60
ns
0
3
0
3
0
3
15
15
tOFF
tORD
0
3
15
20
15
tOEH
20
15
31
16,34
31
3
0
15
ns
ns
22,31
28,39
20
ns
ns
31
27
ns
20,28,31
20
15
3
0
30
30
5,29
15
ns
*60ns specifications are limited to a Vee range of ±0.15V.
MT4LC16257{S)
W04.pmS ~ Rev. 2195
2-138
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology, Inc.
ADVANCE
MICRON
1-·
MT 4LC16257(S)
256K x 16 DRAM
"'"""0"""'
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +3.3V ±0.3V*)
PARAMETER
FAST-PAGE-MODE READ or WRITE
cycle time
FAST-PAGE-MODE READ-WRITE
cycle time
-8
-7
-6*
AC CHARACTERISTICS
SYM
tpc
MIN
UNITS
NOTES
35
40
45
ns
33
tpRWC
85
95
100
ns
33
MAX
MIN
MAX
MIN
MAX
.
Access time from RAS
tRAC
RAS to columnaddress delay time
tRAD
60
15
30
70
15
15
35
80
40
ns
14
ns
18
Row-address hold time
tRAH
10
10
10
ns
Column-address to
RAS lead time
IRAL
30
35
40
ns
RAS pulse width
RAS pulse width (PAGE MODE)
tRAS
IRASP
tRASS
60
60
100
RAS pulse width entering
SELF REFRESH
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time
(referenced to CAS)
Read command setup time
Refresh period (512 cycles)
MT4LC16257 / MT4LC16257 S
..
IRC
110
tRCD
tRCH
20
tRCS
tREF
0
10,000
100,000
70
70
100
130
45
20
40
10
50
10
110
Read command hold time
(referenced to RAS)
tRRH
0
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
Write command hold time
(referenced to RAS)
Write command setup time
Write command pulse width
20
ns
ns
~
41
ns
60
0
8/64
8/64
IRP
10,000
100,000
0
0
8/64
IRPC
tRPS
RAS hold time
READ WRITE cycle time
80
80
100
150
50
0
0
RAS to CAS precharge time
RAS precharge time exiting
SELF REFRESH
RAS precharge time
10,000
100,000
ns
17,29
ns
19,26,30
ns
26,29
ms
60
ns
130
10
150
~s
41
0
0
ns
19
ns
tRSH
15
20
150
85
175
95
20
195
105
ns
ns
ns
38
tRWC
tRWD
tRWL
IT
15
20
20
ns
26
twCH
tWCR
10
45
ns
26,38
55
60
ns
26
twcs
twp
0
10
0
10
0
ns
21,26,29
10
ns
26
3
50
3
10
50
3
10
50
21
ns
*60ns specifications are limited to a Vee range of ±0.1.5V.
MT4LCI6257(S)
W04,pm5 -'- Rev, 2/95
2-139
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
."
"'C
s:
C
:a
»
s:
ADVANCE
MICRON
1-·
MT4LC16257(S)
256Kx 16 DRAM
"'""0,"","
NOTES
•"
'"C
s:
C
::D
»
s:
1.
2.
3.
4.
All voltages referenced to Vss.
This parameter is sampled. Vee = +3.3V; f = 1 MHz .
Icc is dependent on cycle rates.
Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C ~ TA ~ 70°C) is assured.
7. An initial pause of lOOlls is required after power-up
followed by eight RAS refresh cycles ( RAS ONLY or
CBR) before proper device operation is assured. The
eight RAS cycle wake-ups should be repeated any
time the IREF refresh requirement is exceeded.
8. AC characteristics assume IT = Sns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to one TTL gates
and SOpF, VOL = 0.80 and VOH = 2.0V.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD;:: IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the Q buffer, CAS must be pulsed
HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by ICAe.
18. Operation within the lRAD limit ensures that IRCD
(MAX) can be met. IRAD (MAX) is specified as a
reference point only; if lRAD is greater than the
specified lRAD (MAX) limit, access time is controlled
exclusively by IAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
MT4LCI6257(S)
W04.pm5 - Rev. 2195
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition; it is not a
reference to VOH or VOL. The 3ns minimum is a
parameter guaranteed by design.
21. IWCS, IRWD, IAWD and ICWD are restrictive
operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. IfIWCS;:: twcs (MIN),
the cycle is an EARLY WRITE cycle and the data
output will remain an open circuit throughout the
entire cycle. If IRWD;:: IRWD (MIN), IAWD;:: IAWD
(MIN) and leWD;:: leWD (MIN), the cycle is a
READ-WRITE and the data output will contain data
read from the selected cell. If neither of the above
conditions is met, the state of Q (at access time and
until CAS or OE goes back to VIH) is indeterminate.
OE held HIGH and WE taken LOW after CAS goes
LOW results in a LATE WRITE (OE-controlled) cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. During a READ cycle, if OE is LOW then taken HIGH
before CAS goes HIGH, Q goes open. If OE is tied
permanently LOW, a LATE WRITE or READMODIFY-WRITE operation is not possible.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and
OE=HIGH.
25. All other inputs at Vee -0.2V.
26. Write command is defined as WE going LOW on the
MT4LCI62S7(S).
27. LATE WRITE and READ-MODIFY-WRITE cycles
must have both IOD and IOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide the previously written data if CAS
remains LOW and OE is taken back LOW after IOEH
is met. If CAS goes HIGH prior to OE going back
LOW, the DQs will remain open.
28. The DQs open during READ cycles once IOD or IOFF
occur. If CAS goes HIGH before OE, the DQs will
open regardless of the state of the OE. If CAS stays
LOW while OE is brought HIGH, the DQs will open.
If OE is brought back LOW (CAS still LOW), the DQs
will provide the previously read data.
29. The first CASx edge to transition LOW.
30. The last CASx edge to transition HIGH.
31. Output parameter (DQx) is referenced to corresponding CAS input, DQI-DQ8 by CASL and DQ9-DQI6
by CASH.
2-140
Micron Technology, Inc., reserves the righllo change products or specificauons without notice.
©1995,MicronTechnology,lnc.
ADVANCE
MIC::RON
1-·
MT4LC16257(S)
256K X 16 DRAM
'''"'"c,,''""
NOTES (continued)
32. Last falling CASx edge to first rising CASx edge.
33. Last rising CASx edge to next cycle's last rising CASx
edge.
34. Last rising CASx edge to first falling CASx edge.
35. First DQs controlled by the first CASx to go LOW.
36. Last DQs controlled by the last CASx to go HIGH.
37. Each CASx must meet minimum pulse width.
38. Last CASx to go LOW.
39. All DQs controlled, regardless of CASL and CASH.
40. Column-address changed once while RAS = VIL and
CAS=VIH.
41. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
•"
"tJ
s:
C
:xJ
l>
s:
MT4LC16257(S)
W04.pm5 _Hev. 2/95
2.;141
Micron Technology, Inc., reserves the right to change products or specifications without notjce.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LC16257(S)
256Kx16 DRAM
"'e","",'"
READ CYCLE
•
'RC
'RP
'RAS
\
ICSH
."
-C
~I
'RSH
I~
s:
'RCD
J
'AR
'RAD
C
I~ ~I
:c
!;IIII/;{
»
:s:
~I
I
tAAL
I
I
~I
lAse ..I
wlilia
ROW
'ClCH
'CAS
ROW
COLUMN
~
'RCS
&'&'£&1&&/#/&&1#
DQ
II
I
I
V#/#/#//#/////&'/;
'M
'RAG
I~
NOTE!
'CAC
~l
~gr-
OPEN
~-OPEN---
VALID DATA
I~
~
EARLY WRITE CYCLE
'RC
'RAS
RAs
CASL and CASH
V1L
_
-=:J
IRCD
'CRP
V,H _
Vil
'AR
'RAD
ADDR
'RP
V1H -
V,H
V"
'CLCH
f
ROW
ROW
I
I
twes
WE
V,H
V"
I I
'WCH
'WP
I I
IZZ1 DON'T CARE
!l8@ UNDEFINED
MT4LCI6257(S)
W04.pm5- Rev. 2195
2-142
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII::RCN
1-·
MT4LC16257(S)
256K X 16 DRAM
"'"""00""
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
CAslandCASH
VIH
~
-~--
VIL~~
~
•
}~:=
tCLCH
1-'-:,,'A,,--R- - - - + 1--+-1-'-'RA-L I
~1~:=
ADDR
ROW
VIH _~7777777T,7777rn'n'TT7T77777~-+-------,---------l1
WE
}---'it.LlLLLLlLLLL!.J.LLL.
3:
ADVANCE
MICRON
1-·
MT4LC16257(S)
256K x 16 DRAM
",,"",ceen,
SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
-"
"T1
S
C
::D
l>
S
HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
(READ)
(REFRESH)
tRAS
RAS
VIH
VIL_
tRP
~:-----------.-.~tR-SH-:~--~.------~tCH-R------IReD
CASL and CASH
VIHVIL_
tRAS
Iy-------
I------"""-~I_______++___c'_""'__+__I
tAR
ADDR
-tOFF
OPEN-
too
}$#/!m&&
NOTE:
MT4LC16257(S)
W04.pm5 - Rev. 2195
E2ZI
DON'T CARE
~
UNDEFINED
1. tWRP and tWRH are for system design reference only. The WE signal is actually a "don't care" at RAS time
during a CSR REFRESH. However, WE should be held HIGH at RAS time during a CSR REFRESH to
ensure compatibility with other DRAMs which require WE HIGH at RAS time during a CSR REFRESH.
2. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
3. Once tRPS is satisfied, a compete burst of all rows should be executed.
2-146
Micron Technology, Inc., reserveslhe right to change producls ors pecificationswlthoutnollC(l.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
MT4C1 M16C3
1 MEG x 16 DRAM
"'~"'oo,,'
1-·
1 MEG x 16 DRAM
m
5V, FAST PAGE MODE
:.
DRAM
."
FEATURES
• JEDEC- and industry-standard x16 timing, functions,
pinouts and packages
• High-performance CMOS silicon-gate process
• Single +5V ±1O% power supply
• All device pins are TTL-compatible
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
• BYTE WRITE and BYTE READ access cycles
• 1,024-cycle refresh (10 row-, 10 column-addresses)
• Low power, 1mW standby; 350mW active, typical
PIN ASSIGNMENT (Top View)
42-Pin SOJ
(DA-8)
Vee
D01
D02
D03
D04
Vee
DOS
D06
OPTIONS
DQ7
MARKING
• Timing
60ns access
70ns access
D08
NC
NC
-6
-7
• Refresh Rate
Standard 16ms period
1
Ii
9
AO
A1
10
11
12
13
14
15
16
17
18
A2
19
A3
Vee
20
21
WE
RAS
NC
NC
None
• Packages
Plastic SOJ (400 mil)
42
Vss
41p OQ16
40
OQ15
39 P DQ14
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P,OQ13
D012
P OQ11
OQ10
DOg
NC
CASL
CASH
DE
P A9
A8
A7
A6
AS
A4
Vss
DJ
KEY TIMING PARAMETERS
-6
-7
tRC
110ns
130ns
tRAC
60ns
70ns
tpc
35ns
40ns
tM
30ns
35ns
teAC
15ns
20ns
tRP
40ns
50ns
GENERAL DESCRIPTION
The MT4C1M16C3 is a randomly accessed solid-state
memory containing 16,777,216 bits organized in a x16 configuration. The MT4C1M16C3 has both BYTE WRITE and
WORD WRITE access cycles via two CAS pins (CASL and
CASH). These function in an identical manner to a single
CAS of other DRAMs in that either CASL or CASH will
generate an internal CAS.
The MT4C1M16C3 CAS function and timing are determined by the first CAS (CASL or CASH) to transition LOW
and the last CAS to transition back HIGH. Use of only one
of the two results in a BYTE access cycle. CASL transitioning
LOW selects an access cycle for the lower byte (DQ1-DQ8)
and CASH transitioning LOW selects an access cycle for the
upper byte (DQ9-DQ16).
MT4C1M1I3C3
W11.pm5 - Rev, 2195
Each bit is uniquely addressed through the 20 address
bits during READ or WRITE cycles. These are entered 10
bits (AO-A9) at a time. RAS is used to latch the first 10 bits
and CAS the latter 10 bits. The CAS function is determined
by the first CAS (CASL or CASH) to transition LOW and the
last one to transition back HIGH. The CAS function also
determines whether the cycle will be a refresh cycle (RAS
ONLY) or an active cycle (READ,WRITE or READ WRITE)
. once RAS goes LOW.
The CASL and CASH inputs internally generate a CAS
signal functioning in an identical manner to the single
CAS input of other DRAMs. The key difference is each
CAS input (CASL and CAStO controls its corresponding
DQ tristate logic (in conjunction with OE and WE). CASL
controls DQ1 through DQ8 and CASH controls DQ9 through
DQ16. The two CAS controls give the MT4C1M16C3 both
BYTE READ and BYTE WRITE cycle capabilities.
A logic HIGH on WE dictates READ mode while a logic
LOW on WEdictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. Taking WE LOW will initiate a
WRITE cycle, selecting DQ1 through DQ16. If WE goes
LOW prior to CAS going LOW, the output pin(s) remain
2-147
"tJ
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C
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• Part Number Example: MT4C1M16C3DJ-7
SPEED
z
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
»
s:
ADVANCE
MICRON
1-·
MT4C1 M16C3
1 MEG x 16 DRAM
,"~'ow" '"
z
m GENERAL DESCRIPTION (continued)
=E
•
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open (High- Z) until the next CAS cycle. If WE goes LOW
after CAS goes LOW and data reaches the output pins, dataout (Q) is activated and retains the selected cell data as long
as CAS and OE remain LOW (regardless of WE or RAS).
This late WE pulse results in a READ WRITE cycle.
The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O. Pin direction is controlled by
OEand WE
in by CAS. CAS may be toggled-in by holding RAS LOW
and strobing-in different column-addresses, thus executing faster memory cycles. Returning RAS HIGH terminates
the FAST PAGE MODE operation.
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby
level. The chip is also preconditioned for the next cycle
during the RAS HIGH time. Memory cell data is retained in
its correct state by maintaining power and executing any
RAS cycle (READ, WRITE) or RAS refresh cycle(RAS
ONLY, CBR, or HIDDEN) so that all 1,024 combinations of
RAS addresses (AO-A9) are executed at least every 16ms,
regardless of sequence. The CBR REFRESH cycle will also
invoke the refresh counter and controller for row-address
control.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined (AO-A9) page boundary. The FAST
PAGE MODE cycle is always initiated with a row-address
strobed-in by RAS followed by a column-address strobed-
!\
RAS
UPPER BYTE
(DQ9-DQ16)
OFWORD
STORED
INPUT
INPUT
DATA
DATA
DATA
!
-4----
STORED STORED
DATA
o::::::::::::::::::
-----------------3> 1
0
1
----------------->
-----------------3>
-----------------3>
-----------------3>
-----------------3>
INPUT
INPUT
STORED
DATA
DATA
DATA
DATA
I:o~
1
1
0
a
-----------------3> 1
-----------------3> 1
-----------------3> 1
-----------------;;> 1
0
----------'-------;;:..
0
1
~ ::::::::::::::::.::.1
1
-----3>
1
x
-------------~---;;:..
1
-----------------;;:..
-----------------;;:..
-----------------;;:..
-----------------;;:..
0
1
1
1
-----------------;;:..
1
-----3>
.-----3>
0
X .-----3>
1 .-----3>
1
X
X
-----3>
1 ----"-3>
-----3>
.-----3>
1
1
X
X
X
X
X
-----;:.
-----3>
1
X
X
::::::::::::::::::1
-----------------3>
0
0
~:::::: ~ . ::.:::: 11 1~ 1
X .-.----3>
;--
\
/
\
I
;-
\
/
\
CASH
WE
;-
/
\
-!
LOWER BYTE WRITE
\
/
CASL
LOWER BYTE
(DQ1-DQ8)
OF WORD
-!-
WORD WRITE
ADDRESSO - - -_ _- - - - ADDRESS 1
------+
x = NOT EFFECTIVE (DON'T CARE)
Figure 1
WORD AND BYTE WRITE EXAMPLE
MT4C1M16C3
W11.pmS - Rev. 2/9S
2-148
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©199S, Micron Technology, Inc.
ADVANCE
BYTE ACCESS CYCLE
The BYTE WRITEs and BYTE READs are determined by
the use of CASL and CASH. Enabling CASL will select a
lower BYTE access (DQI-DQ8). Enabling CASH will select
an upper BYTE access (DQ9-DQ16). Enabling both CASL
and CASH selects a WORD WRITE cycle.
The MT4CIM16C3 may be viewed as two 1 Meg x 8
DRAMs that have common input controls, with the exception of the CAS inputs. Figure 1 illustrates the BYTE WRITE
and WORD WRITE cycles. Figure 2 illustrates BYTE READ
and WORD READ cycles.
z
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I-
RAS
~
STORED
OUTPUT
OUTPUT
DATA
DATA
DATA
UPPER BYTE
(009-0016)
OFWORO
Z
= High-Z
\
'L-I
-.!
~
~
;-
/
\
LOWER BYTE
(001-008)
OFWORO
;-
\
/
CASH
-I
LOWER BYTE READ
/
\
CASL
WE
-I-
WORD READ
----3>
0
1
1
-".
1
-----3>-
0
------3>-
1
------3>
1
-----?;>
-----;;>
Z
-----:;>
1
-----3>-
0
Z
-----3>-
1
z
-----3>
0
Z
-----3>-
z
-----;:..
---_.;::.-
Z
-----3>-
ADDRESS 0
0
STORED STORED
DATA
DATA
~~
~~
--
~
OUTPUT
OUTPUT
STORED
DATA
DATA
DATA
-----;>
1
1
-----:3>-
1
------3>-
0
.---~-3>
"--.---3>-
.-----3>
1
-----;;:..
1
.-----;;>
1
-----3>-
Z
.-----3>- Z
Z
Z
z -----3;> Z
Z .-----3> Z
Z
Z
-----3>
Z
-----3>-
-----3>
Z
Z ------3> Z
ADDRESS 1
~
i
Figure 2
WORD AND BYTE READ EXAMPLE
MT4C1MI6C3
W11.pm5-Aev.2/95
2-149
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
C
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l>
s:
ADVANCE
MICRON
1-·
MT4C1M16C3
1 MEG x 16 DRAM
,","",'0",,,0
z
m
FUNCTIONAL BLOCK DIAGRAM
~
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WE
CASL
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CASH
DOi
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i-----oOE
AO
A1
A2
A3
A4
AS
A6
A7
AS
A9
---1024x 16-----
1024 X 1024 X 16
MEMORY
ARRAY
+----0
RAS 0-------1
Vee
+---<> VSS
MT4C1M16C3
W11.pm5-Rev.2195
2-150
Micron Technology, Inc" reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC::RON
1-·
MT4C1M16C3
1 MEG x 16 DRAM
,,,""ce"",",
----------------------------------------------------=z
m
TRUTH TABLE
FUNCTION
RAS
CAS[
Standby
H
H~X
:e
ADDRESSES
IR
IC
CASH
WE
lIE
H~X
X
X
X
X
DOs
NOTES
High-Z
READ: WORD
L
L
L
H
L
ROW
COL
Data-Out
READ: LOWER BYTE
L
L
H
H
L
ROW
COL
Lower Byte, Data-Out
Upper Byte, High-Z
READ: UPPER BYTE
L
H
L
H
L
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-Out
WRITE: WORD
(EARLY WRITE)
L
L
L
L
X
ROW
COL
Data-In
WRITE: LOWER
BYTE (EARLY)
L
L
H
L
X
ROW
COL
Lower Byte, Data-In
Upper Byte, High-Z
WRITE: UPPER
BYTE (EARLY)
L
H
L
L
X
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-In
READ WRITE
"s:"tJ
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L
L
L
H~L
L~H
ROW
COL
Data-Out, Data-In
1,2
PAGE-MODE
1st Cycle
L
H~L
H~L
H
L
ROW
COL
Data-Out
2
READ
2nd Cycle
L
H-L
H~L
H
L
n/a
COL
Data-Out
2
PAGE-MODE
1st Cycle
L
H~L
H~L
L
X
ROW
COL
Data-In
1
WRITE
2nd Cycle
L
H~L
H~L
L
X
n/a
COL
Data-In
1
PAGE-MODE
1st Cycle
L
H~L
H~L
H~L
L~H
ROW
COL
Data-Out, Data-In
1,2
1,2
L
H~L
H~L
H~L
L~H
n/a
COL
Data-Out, Data-In
HIDDEN
READ
L~H~L
L
L
H
L
ROW
COL
Data-Out
2
REFRESH
WRITE
L~H~L
L
L
L
X
ROW
COL
Data-In
1,3
L
H
H
X
X
ROW
n/a
High-Z
H~L
L
L
H
X
X
X
High-Z
READ-WRITE 2nd Cycle
RAS-ONLY REFRESH
CBR REFRESH
NOTE:
1.
2.
3.
4.
MT4C1M16C3
W11.pmS-Rev.2195
4
These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active).
These READ cycles may also be BYTE READ cycles (either CASL or CASH active).
EARLY WRITE only.
Only one CAS must be active (CASL or CASH).
2-151
III
Micron Technology, Inc., reserves the right to change products or specl/ications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1- •
MT4C1M16C3
"'""""' ' " , 1 MEG x 16 DRAM
z
ABSOLUTE MAXIMUM RATINGS*
m Voltage
on a Pin Relative to Vss ........................ -IV to 7.0V
:e
II
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability .
Operating Temperature, TA (ambient}, ......... DoC to +70°C
Storage Temperature (plastic) .................... -SsoC to + ISO°C
Power Dissipation ............................................................. IW
Short Circuit Output Current .................. ;.................. SOmA
."
"'0
S
C
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»
S
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +5.0V ±1 0%)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vcc
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs (including NC pins)
VIH
2.0
Vcc + 1V
V
Input Low (Logic 0) Voltage, all inputs (including NC pins)
VIL
-1.0
0.8
V
II
-2
2
-10
10
IlA
VOH
2.4
PARAMETER/CONDITION
INPUT LEAKAGE CURRENT
Any input OV ~ VIN ~ Vcc
(All other pins not under test = OV)
OUTPUT LEAKAGE CURRENT (Q is disabled; OV ~ VOUT > 5V)
loz
OUTPUT LEVELS
Output High Voltage (lOUT = -5.0mA)
Output Low Voltage (lOUT = 4.2mA)
NOTES
fJA
V
VOL
0.4
V
MAX
SYMBOL
-6
-7
ICC1
2
2
mA
ICC2
1
1
mA
25
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS Address Cycling: IRC = IRC [MIN])
ICC3
180
165
mA
3,4,26
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC = IpC [MIN]; ICp, IASC = 10ns)
ICC4
100
90
mA
3,4,26
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS=VIH: IRC = IRC [MIN])
Iccs
160
145
mA
3
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS Address Cycling: IRC = IRC [MIN])
Icc6
150
140
mA
3,5
PARAMETER/CONDITION
STANDBY CURRENT: (TTL) (RAS = CAS = VIH)
.
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
MT4C1M16C3
W11.pm5 - Rev. 2/95
2-152
UNITS NOTES
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©199S, Micron Technology, Inc.
ADVANCE
z
m
CAPAC ITANCE
SYMBOL
MAX
Input Capacitance: Addresses
CI1
5
pF
2
Input Capacitance: RAS, CASL, CASH, WE, OE
CI2
7
pF
2
Input/Output Capacitance: DQ
CIO
7
pF
2
PARAMETER
UNITS
NOTES
~
•
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s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vcc
=+5.0V ±1 0%)
AC CHARACTERISTICS
PARAMETER
SYM
Access time from column-address
tAA
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
tAR
tASC
tASR
tAWD
Access time from CAS
Column-address hold time
tCAC
CAS pulse width
tCAS
CAS hold time (CBR REFRESH)
last CAS going lOW to first CAS to return HIGH
CAS to output in low-Z
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
tCAH
tCHR
tClCH
tClZ
tcp
CAS hold time
tCSH
CAS setup time (CBR REFRESH)
CAS to WE delay time
tCSR
tCWD
Write command to CAS lead time
tCWl
tDH
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
tDHR
tDS
tOD
tOE
Output Enable
OE hold time from WE during READ-MODIFY-WRITE cycle
tOEH
Output buffer turn-off delay
OE setup prior to RAS during HIDDEN REFRESH cycle
toRD
MT4C1M16C3
W11.pm5-Rev.2I95
50
0
0
55
tOFF
..
2-153
MIN
15
3
0
UNITS
35
ns
10,000
15
15
15
ns
ns
ns
ns
20
15
20
15
10
3
10
5
70
5
45
20
15
55
0
3
15
3
0
ns
ns
10,000
ns
ns
ns
ns
ns
40
35
5
60
5
40
15
10
45
0
3
MAX
55
0
0
60
15
tCPA
tCRP
MAX
30
10
15
15
10
3
10
l>
-7
-6
MIN
C
::c
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
ns
20
ns
ns
ns
ns
NOTES
31
21
15.33
31
39
5,32
34
33,30
16,36
33
32
32
5, 31
21,31
26,32
22,33
22,33
29,30,41
33
28
20,30,33
Micron Technology, Inc., reserves the right to change products or speCifications without notice.
©1995, Micron Technology, Inc.
s:
ADVANCE
MIC::RON
1-·
MT4C1M16C3
1 MEG x 16 DRAM
"'"""co",,",
z
~ ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
<
II
"s:
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s:
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+S.OV ±1 0%)
-6
AC CHARACTERISTICS
PARAMETER
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
SYM
tpc
tpRWC
tRAC
tRAD
MIN
-7
MAX
35
85
60
15
30
10
tRAL
30
60
10,000
60
Random READ or VVRfTE cycle time
tRASP
tRC
110
RAS to CAS delay time
tRCD
20
Read command hold time (referenced to CAS)
tRCH
0
Read command setup time
Refresh period (1,024 cycles)
tRCS
tREF
0
MAX
40
95
tRAH
tRAS
MIN
15
10
NOTES
35
ns
35
70
ns
35
ns
14
18
ns
ns
100,000
35
70
70
10,000
100,000
45
130
20
50
ns
ns
ns
0
0
16
UNITS
ns
16
ns
17,31
ns
19,26,32
ns
ms
26,31
28
tRP
40
50
ns
RAS to CAS precharge time
Read command hold time (referenced to RAS)
tRPC
0
0
tRRH
0
ns
ns
RAS hold time
tRSH
READ WRITE cycle time
RAS to WE delay time
tRWC
tRWD
15
150
0
20
Write command to RAS lead time
tRWL
tT
RAS prechargetime
85
15
3
Transition time (rise or fall)
Write command hold time
tWCH
10
Write command hold time (referenced to RAS)
tWCR
45
WE command setup time
Write command pulse width
twcs
twp
0
10
WE hold time (CBR REFRESH)
tWRH
WE setup time (CBR REFRESH)
tWRP
MT4C1M16C3
W11.pm5-Rev.2/95
2-154
50
19
40
180
ns
ns
95
20
ns
ns
21
3
15
50
26
ns
ns
55
0
ns
ns
10
15
10
ns
ns
10
10
ns
26,40
26
21,26,31
Micron Technology, Inc., reserves the right to change products or speciflcalions without noti ceo
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4C1M16C3
1 MEG x 16 DRAM
",""OW",,,
z
m
NOTES
1.
2.
3.
4.
All voltages referenced to Vss.
This parameter is sampled. Vee = +5.0V; f = 1 MHz.
Icc is dependent on cycle rates.
Icc is dependent on output loading. Specified values
are obtained with minimum cycle time and the output
open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C :0; TA :0; 70°C) is assured.
7. An initial pause of 100J.ls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR) before proper device operation is assured. The
eight RAS cycle wake-ups should be repeated any
time the tREF refresh requirement is exceeded.
8. AC characteristics assume IT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gate,
100pF and VOL = 0.8V and VOH = 2.0V.
14. Assumes that IRCD < IRCD (MAX). If tRCD is greater
than the maximum recommended value shown in
this table, IRAC will increase by the amount that
IRCD exceeds the value shown.
15. Assumes that IRCD ~ tRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the Q buffer, CAS must be pulsed
HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
IRAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by tCAe.
18. Operation within the lRAD limit ensures that IRCD
(MAX) can be met. lRAD (MAX) is specified as a
reference point only; if tRAD is greater than the
specified IRAD (MAX) limit, access time is controlled
exclusively by tAA.
MT4C1M16C3
W11.pm5 -,Rev. 2195
19. Either tRCH or tRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition; it is not a
reference to VOH or VOL.
21. twcs, tRWD, IAWD and ICWD are restrictive
operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. If twcs ~ IWCS (MIN),
the cycle is an EARLY WRITE cycle and the data
output will remain an open circuit throughout the
entire cycle. If tRWD ~ IRWD (MIN), IAWD ~ IAWD
(MIN) and tCWD ~ ICWD (MIN), the cycle is a READ
WRITE and the data output will contain data read
from the selected cell. If neither of the above
conditions is met, the state of Q (at access time and
until CAS or OE goes back to VIH) is indeterminate.
OE held HIGH and WE taken LOW after CAS goes
LOW results in a LATE WRITE (OE-controlled) cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. During a READ cycle, if OE is LOW then taken HIGH
before CAS goes HIGH, Q goes open. If OE is tied
permanently LOW, LATE WRITE and READMODIFY-WRITE operations are not permissible and
should not be attempted.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and OE = HIGH.
25. All other inputs at 0.2V or Vee -O.2V.
26. Column-address changed once each cycle.
27. When exiting the SELF REFRESH mode, a complete
set of row refreshes should be executed in order to
ensure that the DRAM will be fully refreshed.
Alternatively, distributed refreshes may be utilized,
provided CBR REFRESH cycles are employed.
28. LATE WRITE and READ-MODIFY-WRITE cycles
must have both 10D and tOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide the previously read data if CAS
remains LOW and OE is taken back LOW after 10EH
is met. If CAS goes HIGH prior to OE going back
LOW, the DQs will remain open.
29. The DQs open during READ cycles once 10D or 10FF
occur.
2-155
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
:e
•
'T1
\l
s:
C
JJ
»
s:
ADVANCE
z
m NOTES (continued)
:e
•
-n
"tJ
s:
30. The .3ns minimum is a parameter guaranteed by
design .
31. The first CASx edge to transition LOW.
32. The last CASx edge to transition HIGH.
33. Output parameter (DQx) is referenced to corresponding CAS input; DQI-DQ8 by CASL and DQ9-DQ16
by CASH.
34. Last falling CASx edge to first rising CASx edge.
35. Last rising CASx edge to next cycle's last rising CASx
edge.
36. Last rising CASx edge to first falling CASx edge.
37. First DQs controlled by the first CASx to go LOW.
38. Last DQs controlled by the last CASx to go HIGH.
39. Each CASx must meet minimum pulse width.
40. Last CASx to go LOW.
41. All DQs controlled, regardless CASL and CASH.
C
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»
s
MT4C1M16C3
W11.pm5~
Rev. 2195
2-156
Micron Technology, Inc" reserves the right to change products Of specifications without notice.
©1995, Micron Technology. Inc.
ADVANCE
MICRON
1-·
MT4C1 M16C3
1 MEG x 16 DRAM
, '"
-------------------------------------------------------~
m
READ CYCLE
~
-
'RP
'RAS
\
leSH
I
'RSH
I~
CAS!.. and CASH
VIH
VII.. -
IRCD
J~ ~I
•
ADDR
VIH VII.._
1///,11.
'AR
tRAO
~
I
./W/ff.o
ROW
'cAS
felCH
tRAL
~ ~
C
ROW
COWMN
~
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CYCLE
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!l88I UNDEFINED
MT4C1M16C3
W11,pm5-Rev.2195
MicrOn Technology. Inc., reBerves the right to change products or speclflcations wlthO\Jt notice.
@1995,MicronTechnGlegy,lnc.
:D
»
:s:
ADVANCE
MICRON
1-·
MT4C1M16C3
, 1 MEG x 16 DRAM
,,,",,wO""'
~-----------------------------------------------------
m
READ WRITE CYCLE
(LATE WRiTE and READ-MODiFY-WRiTE cycles)
:e
•
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."
VIH __- - - - , [ 1
VIL _
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~:g~
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VALID DOUT
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CASLandCAsH
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MT4C1M16C3
W11.pm5 - Rev. 2/95
r-
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DATA
DATA
2-158
'OFF
'CAG
VALID
~ ~
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~
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r-
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-
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VALID
r---
DATA
~ ~~
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
ADVANCE
MICRON
MT4C1 M16C3
1MEGx16DRAM
"~,,~,,
1-·
---------------------------------------------------~
m
FAST-pAGE-MODE EARLY-WRITE CYCLE
CASlandCASH
VIH
:e
-n
_c-+---++----~
1'--+------1
VIL -
"0
s:
C
::c
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s:
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~:~:1!I/!11///111I/!II/II/!IIIII/!IIII!III!&'IIII!11/1///IIII!#IIII!IIII!III/!IIII!I/II!I/&'II/!IIIIII/!III/!M'1/!2I,@
FAST..;PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
'RAsP
CASlWldCASH
VIH
---±---++--------,,,
'.IlL -
00
~\g~
1'--t------11
:,-------
I?Zl DON'T CARE
m
UNDEFINED
"NOTE:
1. tpe is for LATE WRITE only.
MT4C1M16C3
W11.pmS-Rev.2!95
2-159
~icron
Technology, hlO., reserves the right to change products or specifications with01,lt r;KrtIce.
©1995, MIcron Technology. loc.
ADVANCE
MICRON
1-·
MT4C1 M16C3
1 MEG x 16 DRAM
, "'""U,
~ ~--------------------------~-------------------------
m
HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
:e
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(READ)
"TI
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~
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VALID DATA
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FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
r=L
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~SH
I~
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ICpp
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VALID
OPEN
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'AA
1
tRAC
~ ~lr
NOTE:
:7lllA
tLLJ.LLL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~
DON'T CARE
~
UNDEFINED
1. Do not drive data prior to High-Z.
MT4C1M16C3
W11.prr\5--Rev.2J95
2-160
Micron Technology. Inc., reserves the rit;tlt to change products or SpecifICatiOns without nolice.
@1995,MicronTechnology,lnc.
ADVANCE
MICRON
1-·
MT4C1M16C3
1 MEG x 16 DRAM
"'""OCOG""
--~~-------------------------------------------------~
m
RAS-ONL Y REFRESH CYCLE
(OE and WE = DON'T CARE)
.
,F"_tRAS~
tCRP
CASL aod CASH
ADDR
Q
tRC
:E
'r b
~
---' _tRP_l
RPC
~:t _=:J
II
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_tR_AH
~gt
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-.------------OPEN------------
CBR REFRESH CYCLE
(Addresses and OE = DON'T CARE)
.
.~
CASl and CASH
RP
..
II
MT4C1M16C3
Wl1.pmS - Rev. 2/95
I
•
1
:J:~":~ -"'''1
'WRP
NOTE:
~_ I
'RPC
DQ
WE
RAS
RP
,
RAS
,.1
Y
~~~~k
_
'WRH
OPEN-----+-ill~~~~~~
'WRP
II
'WRH
~:t -W"ffi@D-:T::-Wffff!$/$/;0'////J-~ ---'W;jiJ#$/#$!$#$##d
~
DON'TeARE
~
UNDEFINED
1. lWRP and tWRH are for system design reference only. The WE signal is actually a "don't care" at RAS time
during a CBR REFRESH. However, WE should be held HIGH at RAS time during a CBR REFRESH to
ensure compatibility with other DRAMs which require WE HIGH at RAS time during a CBR REFRESH.
2-161
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
•"
"tJ
s:
C
::D
l>
s:
ADVANCE
MIC::RON
1-·
"C
C
MT4C1 M16C3
1 MEG x 16 DRAM
,
~'~~--~--~--------------------~~----------~----
m
=e-
•
."
"'tJ
SO
~
:s:
MT4C1M1"6C3
W11.pm5-;-Bev.2195
2-162
Micron Technology, Inc., reserves the right to change products or speciflcaUons without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
un::I=ICN
1-·
MT4LC1M16C3(S)
1 MEG x 16 DRAM
","",co,,,,,
1 MEG x 16 DRAM
DRAM
3.3V, FAST PAGE MODE,
OPTIONAL SELF REFRESH
• JEDEC- and industry-standard x16 timing, functions,
pinouts and packages
• High-performance CMOS silicon-gate process
• Single +3.3V ±O.3V power supply
• All device pins are TTL-compatible
• Refresh modes: RAS ONLY,CAS-BEFORE-RAS (CBR),
HIDDEN and SELF
• BYTE WRITE and BYTE READ access cycles
• 1,024-cycle refresh (10 row-, lOcolumn-addresses)
• Low power, 0.3mW standby; 250mW active, typical
• Optional SELF REFRESH mode, with Extended
Refresh rate (8x)
• 5V tolerant I/O (5.5V maximum VIH level)
OPTIONS
RAS
NC
NC
AO
A1
A2
A3
None
S
tRAC
60ns
70ns
Vee
1
2
3
4
5
6
7
8
9
10
11
50
Vss
49
OQ16
48
OQ15
47
0014
46
DQ13
45
Vss
44
0012
43
0011
42 _lDQ10
41 TJ Doe
40 Tl NC
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
NC
CASl
CASH
DE
A9
A8
A7
A6
A5
A4
Vss
TG
KEY TIMING PARAMETERS
IpC
35ns
40ns
IAA
30ns
35ns
ICAC
15ns
20ns
tRP
40ns
50ns
GENERAL DESCRIPTION
The MT4LC1M16C3(S) is a randomly accessed solid-sta te
memory containing 16,777,216 bits organized in a x16 configuration. The MT4LC1M16C3(S) has both BYTE WRITE
and WORD WRITE access cycles via two CAS pins (CASL
and CASH). These function in an identical manner to a
single CAS of other DRAMs in that either CASL or CASH
will generate an internal CAS.
The MT4LC1M16C3(S) CAS function and timing are
determined by the first CAS (CASL or CASH) to transition
LOW and the last CAS to transition back HIGH. UseDf orily
MT4LC1MI6C3(S}
NC
NC
WE
• Part Number Example: MT4LC1M16C3TG-7 S
wos - Rev. 2/95
Vee
005
D06
007
D08
NC
-6
• Packages
Plastic TSOP (400 mil)
tRC
110ns
130ns
Vee
D01
D02
D03
D04
one of the two results in a BYTE access cycle. CASL
transitioning LOW selects an access cycle for the lower byte
(DQ1-DQ8) and CASH transitioning LOW selects an access
cycle for the upper byte (DQ9-DQ16).
Each bit is uniquely addressed through the 20 address
bits during READ or WRITE cycles. These are entered 10
bits (AO-A9) at a time. RAS is used to latch the first 10 bits
and CAS the latter 10 bits. The CAS function is determined
by the first CAS (CASL or CASH) to transition LOW and the
last one to transition back HIGH. The CAS function also
determines whether the cycle will be a refresh cycle (RAS
ONLY) or an active cycle (READ, WRITE or READ WRITE)
once RAS goes LOW.
The CASL and CASH inputs internally generate a CAS
signal functioning in an identical manner to the single
CAS input of other DRAMs. The key difference is each
CAS input (CASL and CASH) controls its corresponding
DQ tristate logic (in conjunction with OE and WE). CASL
controls DQ1 through DQ8 and CASH controls DQ9 through
DQ16. The two CAS controls give the MT4LC1M16C3(S)
both BYTE READ and BYTE WRITE cycle capabilities.
2-163
"'0
:s:
C
:::D
44/50-Pin TSOP
(DB-5)
-7
• Refresh Rate
Standard 16ms period
SELF REFRESH and 128ms period
-6
-7
PIN ASSIGNMENT (Top View)
MARKING
• Timing
60ns access
70ns access
SPEED
•
."
FEATURES
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
»
:s:
PRELIMINARY
MICRON
1-·
MT4LC1 M16C3(S)
1 MEG x 16 DRAM
","'",00,"'
GENERAL DESCRIPTION (continued)
II
"s:"tJ
C
:IJ
»
s:
ing faster memory cycles. Returning RAS HIGH terminates
the FAST PAGE MODE operation.
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby
level. The chip is also preconditioned for the next cycle
during the RAS HIGH time. Memory cell data is retained in
its correct state by maintaining power and executing any
RAS cycle (READ, WRITE) or RAS refresh cycle (RAS
ONLY, CBR, or HIDDEN) so that all 1,024 combinations of
RAS addresses (AO-A9) are executed at least every 16ms
(128ms on the S version), regardless of sequence. The CBR
REFRESH cycle will also invoke the refresh counter and
controller for row-address control.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. Taking WE LOW will initiate a
WRITE cycle, selecting DQl through DQI6. If WE goes
LOW prior to CAS going LOW, the output pines) remain
open (High- Z) until the next CAS cycle. If WE goes LOW
after CAS goes LOW and data reaches the output pins, dataout (Q) is activated and retains the selected cell data as long
as CAS and OE remain LOW (regardless of WE or RAS).
This late WE pulse results in a READ WRITE cycle.
The 16 data inputs and 16 data outputs are routed through
16 pins using common I/O. Pin direction is controlled by
OEand WE.
BYTE ACCESS CYCLE
FAST PAGE MODE
The BYTE WRITEs and BYTE READs are determined by
the use of CASL and CASH. Enabling CASL will select a
lower BYTE access (DQI-DQ8). Enabling CASH will select
an upper BYTE access (DQ9-DQI6). Enabling both CASL
and CASH selects a WORD WRITE cycle.
The MT4LCIM16C3 may be viewed as two 1 Meg x 8
DRAMs that have common input controls, with the exception of the CAS inputs. Figure 1 illustrates the BYTE WRITE
FAST PAGE MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a
row-address-defined (AO-A9) page boundary. The FAST
PAGE MODE cycle is always initiated with a row-address
strobed-in by RAS followed by a column-address strobedin by CAS. CAS may be toggled-in by holding RAS LOW
and strobing-in different column-addresses, thus execut-
I
+ - - - - WORD WRITE
--+1 +.
- - - l O W E R BYTE WRITE
RAS~
/
~
CASH
LOWER BYTE
(001-008)
OF WORD
UPPER BYTE
(009-0016)
OF WORD
/
STORED
INPUT
INPUT
DATA
DATA
DATA
~
~
DATA
;--
\
STORED STORED
DATA
INPUT
INPUT
DATA
DATA
'~
~
'~
~
.
---»
0
--;>
--?
1
1
1
--",.
1
---3>
---0>
0
0
---3>
0
0
0
---3>
0
-----0>-
1
--3>-----3>-
0
1 -----:3>
0
1
-----:3>-
0 -----:3>
0
-----p
-----3>
1
--0>
1 -----:;>
."
1 .-----3>
1
1
-----3>
1 .-----3>
1
ADDRESS 0
'~
0
1
--:;,.
---3>-
0
1
STORED
DATA
---3>
b
X
;--
\
/
\
WE
;--
/
\
CASL
~I
\
-----0>
~
-cO>
--;;,..
--;,.
x
X
X
X
X
X
-
-
-
1
0
1
'~
--0>
0
--3>
1
--".
0
--".
1
--3>
--:3>
1
1
--]i>
1
ADDRESS 1
X == NOT EFFECTIVE (DON'T CARE)
Figure 1
WORD AND BYTE WRITE EXAMPLE
MT 4LC1 M16C3{S}
WOS - Rev. 2195
2-164
Micron Technology. Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC1M16C3(S)
1 MEG x 16 DRAM
,,,""oeo,,,,,
BYTE ACCESS CYCLE (continued)
for the specified tRASS. Additionally, the "5" version allows for an extended refresh rate of 12511s per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby or BATTERY
BACKUP mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum time oftRPS (ztRC). This delay allows
for the completion of any internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all 1,024 rows must
be refreshed within 300l1s prior to the resumption of normal
operation.
and WORD WRITE cycles. Figure 2 illustrates BYTE READ
and WORD READ cycles.
REFRESH
Preserve correct memory cell data by maintaining power
and executing a RAS cycle (READ, WRITE) or RAS refresh
cycle (RAS ONLY, CBR, or HIDDEN) so that all 1,024
combinations of RAS addresses are executed at least every
16ms, regardless of sequence. The CBR REFRESH cycle will
invoke the refresh counter for automatic RAS addressing.
An optional SELF REFRESH mode is also available on
the MT4LC1M16C3 s. The "5" version allows the user the
choice of a fully static low-power data retention mode,
or a dynamic refresh mode at the extended refresh period
of 128ms four times longer than the standard 16ms
specification.
The optional SELF REFRESH feature is initiated by
performing a CBR REFRESH cycle, and holding RAS LOW
I-
_I + - - - -
WORD READ
Ms ~
/
;----
\
CASL
\
CASH
WE
LOWER BYTE
(001-008)
OFWORO
UPPER BYTE
(009-0016)
OFWORO
;-
;-
\
/
~
"-------l
STORED
OUTPUT
OUTPUT
DATA
DATA
DATA
~
~
-I
LOWER BYTE READ
\
--::>
._----y
- ---p
1
1
0
1
1
1
1
1
-----?>
0
-----y
----;>
-:>
---;;:,.
---;,..
Z
-----3---3>-
Z
-----3>
Z
-----;>
ADDRESS 0
1
0
0
STORED STORED
DATA
DATA
~~
~~
~
OUTPUT
OUTPUT
STORED
DATA
DATA
DATA
-----;;:.
1
-----3>-
1
1
0
1
1
1
1
1
-----y
z
-----;:0.-
Z
--
--y
- ---3>-
-:>
1 .-----:;>
- ---0>
-:>
Z
.-----3>
Z
- ---3>-
Z
- ---3>
Z
-----3>
Z
-----;;:.
Z
Z
ADDRESS 1
~
~
Z", High-Z
Figure 2
WORD AND BYTE READ EXAMPLE
MT4LC1M16C3{S)
W05- Rev. ·2/95
2-165
Micron Technology, Inc., reserves the right to change products or speCifications without notice.
©1995, Micron Te'chnology, Inc,
•
."
'lJ
3:
C
'"'1"'1
~
rJI'
3:
PRELIMINARY
MICRON
1-·
MT4LC1 M16C3(S)
1 MEG x 16 DRAM
""",,,,,,,
FUNCTIONAL BLOCK DIAGRAM
•
WE
."
"tJ
CASL
CASH
3:
D01
••
C
D016
:IJ
»
5
1+-----oOE
AO
A1
A2
A3
A4
AS
A6
A7
AS
A9
RAS
1024 x 1024 x 16
MEMORY
ARRAY
o------j
MT4lC1M16C3(S)
W05- Rev. 2/95
2-166
-----..0
Vee
+---0
Vss
Micron Technology, Inc., reselVeSlhe right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC1 M16C3(S)
1 MEGx 16 DRAM
","",we,",
rRUTH TABLE
RAS
CASL
CASH
WE
lJf
Standby
H
H-X
H-X
X
X
X
X
READ: WORD
L
L
L
H
L
ROW
COL
Data-Out
READ: LOWER BYTE
L
L
H
H
L
ROW
COL
Lower Byte, Data-Out
Upper Byte, High-Z
READ: UPPER BYTE
L
H
L
H
L
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-Out
WRITE: WORD
(EARLY WRITE)
L
L
L
L
X
ROW
COL
Data-In
WRITE: LOWER
BYTE (EARLY)
L
L
H
L
X
ROW
COL
Lower Byte, Data-In
Upper Byte, High-Z
WRITE: UPPER
BYTE (EARLY)
L
H
L
L
X
ROW
COL
Lower Byte, High-Z
Upper Byte, Data-In
OQs
NOTES
High-Z
-n
S
c
JJ
l>
S
L
L
L
H-L
L-H
ROW
COL
Data-Out, Data-In
1,2
1st Cycle
L
H-L
H-L
H
L
ROW
COL
Data-Out
2
READ
2nd Cycle
L
H-L
H-L
H
L
n/a
COL
Data-Out
2
PAGE-MODE
1st Cycle
L
H-L
H-L
L
X
ROW
COL
Data-In
1
WRITE
2nd Cycle
L
H-L
H-L
L
X
n/a
COL
Data-In
1
PAGE-MODE
1st Cycle
L
H-L
H-L
H-L
L-H
ROW
COL
Data-Out, Data-In
1,2
1,2
READ-WRITE 2nd Cycle
L
H-L
H-L
H-L
L-H
n/a
COL
Data-Out, Data-In
HIDDEN
READ
L-H-L
L
L
H
L
ROW
COL
Data-Out
2
REFRESH
WRITE
L-H-L
L
L
L
X
ROW
COL
Data-In
1,3
RAS-ONLY REFRESH
L
H
H
X
X
ROW
n/a
High-Z
CBR REFRESH
H-L
L
L
H
X
X
X
High-Z
4
SELF REFRESH
H-L
L
L
X
High-Z
4
NOTE:
MT4LC1M16C3(S)
W05-Rev'.2195
1.
2.
3.
4.
H
X
X
These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASH active).
These READ cycles may also be BYTE READ cycles (either CASL or CASH active).
EARLY WRITE only.
Only one CAS must be active (CASL or CASH).
2-167
-a
PAGE-MODE
READ WRITE
I
ADDRESSES
IR
IC
FUNCTION
Micron Technology, Inc., reserveslhe right to change products or specifications wlttloul notice.
©1995, Micron Technology, Inc
PRELIMINARY
MICRON
1-·
MT4LC1 M16C3(S)
1 MEG x 16 DRAM
'''''"'0"' '"
'Stresses greater than those listed under" Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc pin Relative to Vss ................... -IV to 4.6V
Voltage on Inputs or I/O pins
Relative to Vss .................................................... -IV to +S.SV
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SsoC to + ISO°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... SOmA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vee = +3.3V ±0.3V)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs (including NC pins)
VIH
2.0
5.5V
V
Input Low (Logic 0) Voltage, all inputs (including NC pins)
VIL
-1.0
0.8
V
II
-2
2
/lA
102
-10
10
/lA
VOH
2.4
PARAMETER/CONDITION
INPUT LEAKAGE CURRENT
Any input OV :s; VIN :s; 5.5V
(All other pins not under test =OV)
OUTPUT LEAKAGE CURRENT(Q is disabled; OV:s; VOUT < 5.5V)
OUTPUT LEVELS
Output High Voltage (lOUT = -2.0mA)
Output Low Voltage (lOUT = 2.0mA)
MT4lC1M16C3(S}
wos - Rev. 2195
VOL
2-168
NOTES
V
0.4
V
Micron Technology, Inc., reserves the right to change products or specifications without notica.
©1995, Micron Technology, Inc,
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
:Notes: 1, 6, 7) (Vcc = +3.3V ±0.3V)
MAX
SYMBOL
-6.
-7
Icc1
2
2
mA
Icc2
Icc2
(S only)
500
150
500
150
IlA
Icc3
170
155
mA
3,4,26
Icc4
100
90
mA
3;4,26
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS=VIH: tRC = tRC [MIN])
Icc5
160
145
mA
3
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS Address Cycling: tRC = iRC [MIN])
Icc6
150
140
mA
3,5
Icc7
(S only)
300
300
IlA
3,5
Icc8
(S only)
300
300
Il A
5, 27
PARAMETER/CONDITION
STANDBY CURRENT: (TTL) (RAS = CAS
= VIH)
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS Address Cycling: tRC = tRC [MIN])
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS= VIL, CAS, Address Cycling: tpc '" tpc [MIN]; tcp, tASC
REFRESH CURRENT: SELF (S version only)
Average power supply current during SELF REFRESH: CBR cycle with
RAS ;:: tRASS (MIN) and CAS held LOW; WE = Vcc - 0.2V; AO-A9, OE
and DIN = Vcc - 0.2V or 0.2V (DIN may be left open)
W05-Rev.2/95
2-169
!1A
25
•
."
"'0
i:
= iOns)
REFRESH CURRENT: Extended (S version only)
Average power supply current during BBU REFRESH:
CAS = 0.2V or CBR cycling; RAS = tRAS (MIN); WE = Vcc -0.2V;
AO-A9, OE and DIN = Vcc - 0.2V or 0.2V (DIN may be left open);
tRC = 1251ls (1,024. rows at 125JlS '" 128ms)
MT4LC1 M16C3(S)
UNITS NOTES
Micron Technology, Inc., reserves the right to change products or specifications witho~t notice
©1995, MI1;tonTechnalogy, Inc.
o:0
»
i:
PRELIMINAR'
MICRON
.-.
MT4LC1M16C3(S)
1 MEG x 16 DRAM
m~'''co",,,
CAPACITANCE
-
."
PARAMETER
SYMBOL
MAX
UNITS
NOTES
Input Oapacitance: Addresses
011
pF
2
Input Oapacitance: RAS, OASL, OASH, WE, OE
012
pF
2
Input/Output Oapacitance: DQ
010
5
7
7
pF
2
'"C
s:
C ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
::c
»
s:
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +3.3V ±O.3V)
AC CHARACTER!STICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulse width
CAS LOW to "don't care" during SELF REFRESH cycle
CAS hold time (CBR REFRESH)
Last CAS going LOW to first CAS to return HIGH
CAS to output in Low-Z
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable
OE hold time from WE during READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OE setup prior to RAS during HIDDEN REFRESH cycle
MTf1.LC1 M16C3(S)
WOS - Rev. 2/95
-6
SYM
MIN
tAA
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHD
tCHR
tCLCH
tCLZ
tcp
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDHR
tDS
tOD
tOE
tOEH
tOFF
tORD
2-170
-7
MAX
MIN
30
50
0
0
55
15
3
0
ns
ns
ns
ns
10,000
15
15
15
nS
20
15
20
15
15
10
3
10
10,000
40
35
5
60
5
40
15
10
45
0
3
UNITS
35
55
0
0
60
15
10
15
15
15
10
3
10
MAX
5
70
5
45
20
15
55
0
3
15
3
0
15
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
31
21
15,33
31
39
5,32
34
33,30
16,36
33
32
32
5,31
21,31
26,32
22,33
22,33
29,30,41
33
28
20,30,33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC1M16C3(S)
1 MEG x 16 DRAM
,"<"'00""
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODEREAD-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RASpulse width (FAST PAGE MODE)
RAS pulse width during SELF REFRESH cycle
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (1,024 cycles)
Refresh period (1,024 cycles) S version
RAS precharge time
flAS to CAS precharge time
RAS precharge time. during SELF REFRESIl cycle
Read command hold time (referenced to RAS)
RAS hold time
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT4LC1M16C3{S)
W05 - Rev. 2195
-7
-6
SYM
MIN
tpc
35
85
tpRWC
tRAC
IRAD
tRAH
tRAL
tRAS
tRASP
tRASS
tRC
tRCD
tRCH
tRCS
tREF
tREF
tRP
tRPC
tRPS
tRRH
tRSH
tRWC
tRWD
tRWL
tT
tWCH
tWCR
twcs
twp
twRH
twRP
2-171
15
10
30
60
60
100
110
20
0
0
MAX
MIN
60
30
10,000
100,000
45
15
10
35
70
70
100
130
20
0
0
16
128
40
85
15
0
10
10
10
70
35
10,000
100,000
50
16
128
50
0
130
0
0
110
0
15
150
.3
10
45
MAX
40
95
50
20
180
95
20
3
15
55
0
15
10
10
50
UNITS
NOTES
ns
ns
ns
ns
ns
ns
ns
ns
35
35
14
18
~
27
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
•
."
""0
s:
C
::D
17,31
19,32
31
28
28
27
19
40
21
40
21,31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
l>
s:
PRELIMINARY
NOTES
•
."
'"'D
:s:
C
:c
l>
:s:
All voltages referenced to Vss.
This parameter is sampled. Vee = +3.3V;f = 1 MHz.
Icc is dependent on cycle rates.
Icc is dependent on output loading. Specified values
are obtained with minimum cycle time and the output
open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C ~ TA ~ 70°C) is assured.
7. An initial pause of IOOf.ls is required after power-up
fonowed by eight RAS refresh cycles (RAS ONLY or
CBR) before proper device operation is assured. The
eight RAS cycle wake-ups should be repeated any
time the tREF refresh requirement is exceeded.
S. AC characteristics assume tT = 5ns.
9. VlH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VlH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VlH and
VIL (or between VIL and VlH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gate,
100pF and VOL = O.SV and VOH = 2.0V.
14. Assumes that tRCD < tRCD (MAX). If IRCD is greater
than the maximum recommended value shown in
this table, tRAC will increase by the amount that
IRCD exceeds the value shown.
15. Assumes that IRCD;:: IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the Q buffer, CAS must be pulsed
HIGH for tcP.
17. Operation within the IRCD (MAX) limit ensures that
tRAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if tRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively bytCAC.
IS. Operation within the lRAD limit ensures that tRCD
(MAX) can be met. IRAD (MAX) is specified as a
reference point only; if IRAD is greater than the
specified lRAD (MAX) limit, access time is controlled
exclusively by tAA.
1.
2.
3.
4.
MT4LC1M16C3(S)
W05- Rev. Zt95
19. Either IRCH or tRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition; it is not a
reference to VOH or VOL.
21. twcs, tRWD, tAWD and tCWD are restrictive
operating parameters in LATE WRITE and READMODIFY-WRITE cycles only. IftWCS;:: twcs (MIN),
the cycle is an EARLY WRITE cycle and the data
output will remain an open circuit throughout the
entire cycle. If tRWD;:: tRWD (MIN), IAWD;:: IAWD
(MIN) and ICWD;:: tCWD (MIN), the cycle is a READ
WRITE and the data output will contain data read
from the selected cell. If neither of the above
conditions is met, the state of Q (at access time and
until CAS or OE goes back to VlH) is indeterminate.
OE held HIGH and WE taken LOW after CAS goes
LOW results in a LATE WRITE (OE-controlled) cycle.
22. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
23. During a READ cycle, if OE is LOW then taken HIGH
before CAS goes HIGH, Q goes open. If OE is tied
permanently LOW, LATE WRITE and READMODIFY-WRITE operations are not permissible and
should not be attempted.
24. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and OE =HIGH.
25. All other inputs at 0.2V or Vee -0.2V.
26. Column-address changed once each cycle.
27. When exiting the SELF REFRESH mode, a complete
set of row refreshes should be executed in order to
ensure that the DRAM will be fully refreshed.
Alternatively, distributed refreshes may be utilized,
provided CBR REFRESH cycles are employed.
2S. LATE WRITE and READ-MODIFY-WRITE cycles
must have both taD and tOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide the previously read data if CAS
remains LOW and OE is taken back LOW after 10EH
is met. If CAS goes HIGH prior to OE going back
LOW, the DQs will remain open.
29. The DQs open during READ cycles once taD or 10FF
occur.
2-172
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology. Inc.
PRELIMINARY
UII::I=ICN
1-·
MT4LC1M16C3(S)
1 MEG x 16 DRAM
"'""0"'"""
NOTES (continued)
30. The 3ns minimum is a parameter guaranteed by
design.
31. The first CASx edge to transition LOW.
32. The last CASx edge to transition HIGH.
33. Output parameter (DQx) is referenced to corresponding CAS input; DQ1-DQ8 by CASL and DQ9-DQ16
by CASH.
34. Last falling CASx edge to first rising CASx edge.
35. Last rising CASx edge to next cycle's last rising CASx
edge.
36. Last rising CASx edge to first falling CASx edge.
37. First DQs controlled by the first CASx to go LOW.
38. Last DQs controlled by the last CASx to go HIGH.
39. Each CASx must meet minimum pulse width.
40. Last CASx to go LOW.
41. All DQs controlled, regardless CASL and CASH.
•
."
"'tJ
S
c
::c
l>
s
MT4LC1M16C3(S)
W05-Rev.2J95
2-173
Micron Technology, Inc., reserves the right to change products or specifications without noUce.
©1995, Micron Technology, Inc.
PRELIMINARY
MU::::I=ICN
1-·
MT 4LC1 M16C3(S)
1MEGx16DRAM
"'~"w""
READ CYCLE
•
'RC
tRAS
'RP
\
ICSH
-n
d~
'"'C
s:
I
~ ~D f ~
I
'RAD
I~ ~117TTT77\ ~_
C
JJ
ADDR
=~
ROW
~4-
I
J
tASH
'CAS
'CLCH
~
'RAl
leAH
1
I
pi
ROW
COLUMN
I~II
l>
s:
1-'=-1
~
l~
I
I
I
'AA
1
I
tRAG
'CAG
~I.
OPEN
VALID DATA
_'_OE_
IIII//!/;
r----- OPEN - - -
~
}$/;/////"/"$///////////$/"/;};
EARLY WRITE CYCLE
'RC
I:iZJ DON'T CARE
~
MT4LC1MI6C3(S)
W05-Aev.2I95
2-174
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron TMhnology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC1 M16C3(S)
1 MEG x 16 DRAM
,,,"",we,,",
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
'RAS
•
'RP
."
"tJ
-
'CSH
J~
ADDR
~:~
I-'~-!
4Wl
f~
IRCD
'AR
I
IRAO
~I
ROW
~
t1
I
tRAL
I~"--I
COLUMN
I
Iii
I
IRWD
1I
'cwo
I
I
I
s:
'CLCH
'CAS
I
1-'=--1
I
'RSH
'eWL
'RWL
IAWD
'WP
l
ROW
II
'CAe
,.c~1
1.:-
'CLZ-
l
100:1
-
VALID DOUT
OPEN
~
VALlDD 1N
OPEN~-
tOEH
~-
FAST-PAGE-MODE READ CYCLE
CASLandCASH
VIH _--+-CT-----~
VIL_
~_~I
A
I
tRAG
I~
tcLzOPEN
1:-
-
I
tCLZ-
VALID
DATA
~ ~
MT4LC1M16C3(S)
W05-Rev.2195
2-175
tePA
- 1:-
I
tOFF
tCAC
~
VALID
DATA
~ ~
I
'cPA
I
I~--
-'OFF
VALID
DATA
!----
'eLZ-
l>
s:
'AA
tRAC
I
I
C
:::D
t.J
~!~~
~
DON'TeARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
u II:::1=1CN
1-·
MT 4LC1 M 16C3(S)
1 MEG x 16 DRAM
"'~"oco"'''
FAST-PAGE"MODE EARLY-WRITE CYCLE
•
RAs
VIH VIL _
ICSH
'RSH
~
"T1
'"C
CASL and CASH
s:
ADDR
V1H -
VIL _
V,H
VIL
0
JJ
WE
l>
VIH VIL
_
s:
DQ
DE
~:g~
~:~:II/I!III!IIII!IIII!I//II/!IIIIIIIIII/II!III!/!/fll/II$III/$/!III!//111/$/111/1111_1////1111////1111##11#ffi
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRiTE and READ-MODiFY-WRiTE cycles)
"NOTE:
MT4LC1M16C3(S)
wos - Rev. 2195
~
DON'T CARE
~
UNDEFINED
1. Ipe is for LATE WRITE only.
2-176
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC1 M16C3(S)
1 MEG x 16 DRAM
,,,",,,oc,",
HIDDEN REFRESH CYCLE 24
(WE = HIGH; OE = LOW)
(READ)
-
(REFRESH)
."
'"t:J
s:
C
:::D
:t>
DQx
~:g~
s:
:::::---
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODI FY-WRITE)
tpc 1_---"R=8H'-----_1
tCSH
~
Q
1_._--",'R=cD_ _1
~g~ ='-------+-oPEN-I,_-_-_---"-c--_-_-fl~'i3!=ii[1----oPEN
._
IAA
tRAC
5E
~:t
=I!/m'LLLLUL-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
lZ:l DON'T CARE
0ISJ UNDEFINED
NOTE:
MT4LC1M16C3(S)
W05 - Rev. 2195
1. Do not drive data prior to High-Z.
2-177
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT4LC1 M16C3(S)
1 MEG x 16 DRAM
",'",",0",'",
RAS-ONL Y REFRESH CYCLE
(OE and WE = DON'T CARE)
•
."
-a
s:
o
:tJ
»
S
~gt - : - - - - - - - - - - - - O P E N - - - - - - - - - -
Q
CBR REFRESH CYCLE
(Addresses and OE = DON'T CARE)
iRAS
'RP
I
~:~_=7~~~l
-----.J
CASL and CASH
~I
'RPC
'RPC~~
II
DQ
OPEN
'WRP !!'WRH
WE
tRAS
'RP
~~
11.--------
'WRP !!'WRH
~:~ 4@///////J-:T::-WM//;/M;/$#g- ---'V&ff//;//$$;///"/;//;//J;
SELF REFRESH CYCLE ("SLEEP MODE")
(Addresses and OE = DON'T CARE)
RAS
CAhdCASH
.~ .. - ~=
'"i;,
:~o~
~:~= ~I,
~:~ )~~~ ~;;~#$/////$/_//;;#$jil
WE
NOTE:
MT4LC1M16C3(S)
WOS-Aev.2!95
rOTE'
~
!
_
VOHDO
'"
'RPC
VOL
tWAP
III
'\-OPEN
tWRH
J
twRP
III
tWRH
~:r _~---:T:;-~./I$$///$#$/I4W#$$- -W$/$#/#///J;
~
DON'T CARE
~
UNDEFINED
1. IWRP and WRH are for system design reference only. The WE signal is actually a "don't care" at RAS time
during a CSR REFRESH. However, WE should be held HIGH at RAS time during a CSR REFRESH to
ensure compatibility with other DRAMs which require WE HIGH at RAS time during a CSR REFRESH.
2. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
3. Once tRPS is satisfied, a compete burst of all rows should be executed.
2-178
Micron Technology, Inc., reserves the right
to change products or specilications without notice.
©1995, Micron Technology, Inc.
!)C3iFl~~
.•...•....•..•...••...•.••••......••..•..........•....•.....
SGRAM PRODUCT SELECTION GUIDE
Memory
Configuration
256Kx 32
256K x 32
I
I
S = SELF REFRESH
Part
Number
Speed
Grade (ns)
Power Dissipation
Standby
Active
No. of Pins
TQFP
3.3V
MT41 LC256K32D4
10,12,15
TBD
TBD
100
3-1
3.3V
MT41 LC256K32D4 S
10,12,15
TBD
TBD
100
3-1
Page
ADVANCE
UU::::I=ICN
1-·
MT41 LC256K32D4(S)
256K X 32 SGRAM
,""","OO'"C
256K x 32 SGRAM
SYNCHRONOUS
GRAPHICS RAM
PULSED RAS, DUAL BANK,
PIPELINED, 3.3V OPERATION
~
•
FEATURES
PIN ASSIGNMENT (TOP VIEW)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Dual internal banks for hiding row access / precharge;
dual 128K x 32 architecture
• Programmable burst lengths: 2, 4, 8 or full page
• BLOCK WRITE and WRITE-PER-BIT modes
• Independent byte operation via DQMO-3
• AUTO PRECHARGE and AUTO REFRESH modes
• 17ms, 1,024-cycle refresh (16.6Ils/row)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±O.3V power supply
• Timing
IOns access
12ns access
15ns access
(:::;100 MHz clock rate)
(:::;83 MHz clock rate)
(:::;66 MHz clock rate)
• Self Refresh
VssQ
DQ6
DQ?
VecQ
-10
-12
-15
SET-UP
TIMES
HOLD
TIMES
-10
-12
-15
100 MHZ
83 MHZ
66 MHZ
9ns
11ns
13ns
3ns
3.5ns
4ns
1ns
1.5ns
2ns
VecO
VecO
DaM3
WE
TheMT41LC256K32D4(S) SGRAM is a high-speed CMOS
dynamic random access memory containing 8,388,608 bits.
It is internally configured as a dual 12SK x 32 DRAM with
a synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the 128K x
32 bit banks is organized as 512 rows by 256 columns by 32
bits. Read and write accesses to the SGRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
G01.pmS - Rev. 2195
NC
DQM1
CAS
RAS
ClK
CKE
CS
DSF
NC
A8
sequence. Accesses begin with the registration of an ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA selects the bank, AO-AS select the
row). Then the address bits registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.
The SGRAM provides for programmable READ or
WRITE burst lengths of 2, 4 or Slocations, or the full page,
with burst terminate option. An AUTO PRECHARGE
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst sequence.
GENERAL DESCRIPTION
MT41 LC256K32D4(S)
0011
D010
OQ23
BA
ACCESS
TIME
VssQ
OQ12
VecQ
Vss
Vee
DQMO
DQM2
NC
CLOCK
FREQUENCY
V(,{J
VssQ
DQ9
DQ8
0022
KEY TIMING PARAMETERS
VSfiO
OO?!i
00;'4
0013
VSS
Part Number Example: MT41 LC256K32D4LG -15
0026
OQ18
OQ19
Vee
LG
0028
VecQ
OQ27
DQI!!
OQ14
OQ20
D021
VssQ
SPEED
GRADE
»
s:
0016
D017
VssQ
VecQ
S
• Plastic Packages
100-pin TQFP (0.65mm lead pitch)
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8~o88uouooooooo~8§~§
o>oo>zzzzzzzzzz>oo>o
MARKING
OPTIONS
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100-Pin TQFP
(OC-1)
DQ3
Veca
DQ4
DQS
3-1
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m
Micron Technology, Inc" reserves the right to change products or specifications without notice.
©1995.MicronTechno\ogy, Inc.
ADVANCE
MICRON
I-a
MT41 LC256K32D4(S)
256K X 32 SGRAM
"'""",0",'"
GENERAL DESCRIPTION (continued)
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The MT41 LC256K32D4(S) uses an internal pipelined architecture to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but it
also allows the column address to be changed on every clock
cycle to achieve a high-speed fully random access.
Precharging one bank while accessing the alternate bank
will hide the precharge cycles, and provide seamless highspeed random access operation.
Synchronous graphics RAMs (SGRAMs) differ from synchronous DRAMs (SDRAMs) by providing an eight-column BLOCK WRITE function and a MASKED WRITE (or
WRITE-PER-BIT) function to accommodate high-performance graphics applications. The BLOCK WRITE and
MASKED WRITE functions may be combined with individual byte enables (DQ mask, or DQM, pins).
The CMOS dynamic memory structure of the
MT41 LC256K32D4(S) is designed to operate in 3.3V, low-
MT41 LC256K32D4(S)
G01.pm5 - Rev. 2195
power memory systems. An AUTO REFRESH mode is
provided along with a power saving POWER-DOWN mode.
All inputs and outputs are LVTTL-compatible.
The two-bank synchronous DRAM and x32 configuration provided by the SGRAM are well suited for applications requiring high memory bandwidth, and when combined with special graphics functions result in a device
particularly well suited to high performance graphics applications.
SGRAMs offer substantial advances in dynamic memory
operating performance, including the ability to synchronouslyburstdataatahighdataratewithautomaticcolumnaddress generation, the ability to interleave between internal banks in order to hide precharge time, the capability to
randomly change column addresses on each clock cycle
duringaburstaccess,and special functions suchas MASKED
WRITEs and BLOCK WRITEs.
3-2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MlcronTechnology, Inc.
ADVANCE
MICRON
1-·
MT41 LC256K32D4(S)
256K X 32 SGRAM
,""',"00""
FUNCTIONAL BLOCK DIAGRAM
--
:---------------------------------------------------_.-_.---.--------.----.----.----.----------------------------------------------------------- ..
~
(S12 x256 x 32)
.------+----------b.--OQMO.3
eLK
cs
WE
--+9-----:
GJiS.......o-
w
o
LOGIC
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BANKO
MEMORY
ARRAY
CKE4-
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DaM & 110
WPB
GATING
MASK LOGIC
BLOCK WRITE COUBYTE MASK LOGIC
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SENSE AMPLIFIEAS
110 GATING
DaM & WPB MASK LOGIC
BLOCK WRITE COUBYTE MASK LOGIC
AO-AB, BA
ROW·
ADDRESS
MUX
~
~~
00
~~
0
-512
..--.:-..
BANK!
MEMORY
ARRAY
(512 x256x 32)
DQO-
DQ31
MT41 LC256K32D4(S)
G01.pmS- Rev. 2/95
3-3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology, Inc.
ADVANCE
MICRON
1-·
z
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MT41 LC256K32D4(S)
256 K X 32 SG RAM
",,,,,we, "'
PIN DESCRIPTIONS
•
TQFP
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
55
ClK
Input
Clock: ClK is driven by the system clock. All SGRAM input signals are
sampled on the positive edge of ClK. ClK also increments the internal
burst counter and controls the output registers .
54
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (lOW) the ClK signal.
Deactivating the clock provides POWER-DOWN mode (all banks idle) and
SELF REFRESH mode (all banks idle). CKE is synchronous except after
the device enters POWER-DOWN and SELF REFRESH modes, where
CKE becomes asynchronous until after exiting the same mode. The input
buffers, including ClK, are disabled during POWER-DOWN and SELF
REFRESH modes providing low standby power.
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28
CS
Input
Chip Select: CS enables (registered lOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS is registered
HIGH. CS provides for external bank selection on systems with multiple
banks. It is considered part of the command code.
27,26
53,25
RAS,CAS
DSF, WE
Input
Command Inputs: RAS, WE, CAS, and DSF define the command being
entered.
23,56,24,57
DOMODOM3
Input
Input/Output Mask: DOMO-DOM3 are byte specific, nonpersistent I/O buffer
controls. The I/O buffers are placed in a High-Z state when DOM is sampled
HIGH. Input data is masked when DOM is sampled high during a WRITE
cycle. Output data is masked (two-clock latency) when DOM is sampled
HIGH during a READ cycle. DOMO masks 000-007, DOM1 masks 0080015, DOM2 masks 0016-0023, and DOM3 masks 0024-0031.
29
BA
Input
Bank Address: BA defines to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied. BA is also used to program the
10th bit of the MODE and SPECIAL MODE registers.
31-34,47-50,51
AO-A8
Input
Address Inputs: AO-A8 are sampled during the ACTIVE command (rowaddress AO-A8) and READIWRITE command (column-address AO-A7 with
A8 defining AUTO PRECHARGE) to select one location out of the 128K
available in the respective bank.A8 is sampled during a precharge command determining if both banks are to be precharged (A8 HIGH). The
address inputs also provide the op-code during a lOAD MODE REGISTER
or lOAD SPECIAL MODE REGISTER command.
97,98,100,1,3,4,
6,7,60,61,63,64,
68,69,71,72,9,10,
12,13,17,18,20,21,
74,75,77,78,80,
81,83,84
30,36-45,52,
58,86-95
0000031
2,8, 14,22,59,
67, 73, 79
5, 11, 19, 62, 70,
76,82,99
VccO
Supply DO Power: Provide isolated power to DOs for improved noise immunity.
VssO
Supply DO Ground: Provide isolated ground to DOs for improved noise immunity.
15,35,65,96
Vcc
Supply Power Supply: +3.3V ±0.3V.
16,46,66,85
Vss
Supply Ground
MT41 LC256K32D4(S)
G01.pm5 - Rev. 2195
NC
Input/ Data I/O: Data bus. The I/Os are byte-maskable during READs and
Output WRITEs. The DOs also serve as column/byte mask inputs during BLOCK
WRITEs.
-
No Connect: These pins should be left unconnected.
3-4
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT41 LC256K32D4(S)
256K X 32 SGRAM
",<",,,0,,,,
FUNCTIONAL DESCRIPTION
Register Definition
In general, the SGRAM is a dual 12SK x 32 DRAM with
graphics features (BLOCK WRITE and MASKED WRITE)
which operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the
clock signal, CLK). Each of the 12SK x 32 bit banks is
organized asS12 rows by 256 columns by 32 bits.
Read and write accesses to the SGRAM are burst oriented;
accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE
command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be
accessed (BA selects the bank, AO-AS select the row). Then
the address bits (AO-A7) registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.
BLOCK WRITE accesses are performed in a manner
similar. to WRITEs,. except that BLOCK WRITEs are not
burst oriented, and always apply to the eight column locations selected by A3-A7.
MASKED WRITEs or MASKED BLOCK WRITEs are
similar to the unmasked versions except that the write-perbit mask enabled with the ACTIVE command is applied to
the data being written.
Prior to normal operation, the SGRAM must be initialized. The following sections provide detailed information
covering device ini tializa tion, register definition, command
descriptions and device operation.
MODE REGISTER
The mode register is used to define the specific mode of
operation of the SGRAM. This definition includes the selection of a burst length, a burst type, a read latency and an
operating mode, as shown in Figure 1. The mode register is
programmed via the LOAD MODE REGISTER command,
and will retain the stored information until it is programmed
again or the device loses power.
Mode register bits MO through M2 specify the burst
length, M3 specifies the type of burst (sequential or interleaved), M4 through M6 specify the READ latency, and M7
through M9 specify the operating mode.
The mode register must be loaded when both banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of
these requirements may result in unknown operation.
Burst Length
Read and write accesses to the SGRAM are burst oriented, with the burst length being programmable, as shown
in Figure 1. The burst length determines the maximum
number of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 2, 4, or S
locations are available for both the sequential and the
interleaved burst types, and a full-page burst is available for
the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate
arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is defined by A1-A7 when the burst
length is set to two, by A2-A7 when the burst length is set
to four and by A3-A7 when the burst length is set to eight.
The lower order address bit(s} are used to select the starting
location within the block. Full page bursts wrap within the
page if the boundary is reached.
Initialization
SGRAMs must be powered-up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation. Once power is
applied to Vee and VeeQ (simultaneously) the SGRAM
requires a lOOIlS delay prior to activating CKE. All other
inputs should be held HIGH during this phase of powerup.
Once the lOOlls delay has been satisfied, the CKE pin
must be driven HIGH ICKS before a positive clock edge,
after meeting tCKH from the previous clock edge. The first
command. will be registered on the clock edge following
ICKS.
Both banks must then be precharged, thereby placing the
device in the "all bank idle" state. Once in the idle state, two
AUTO REFRESH cycles must be performed. Once the AUTO
REFRESH cycles are complete, the SGRAM is ready for
mode register programming. Because the mode register
will power-up in an unknown state, it should be loaded
prior to performing any operational command.
MT41 LC256K32D4(S)
G01.pm5 - Rev. 2/95
Burst Type
Accesses within a given burst may be programmed to be
either sequential or "interleaved"; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
3-5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©199S, Micron Technology, Inc.
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ADVANCE
MICRON
MT41 LC256K32D4(S)
256K x 32 SGRAM
"'~'"'oo,,"'
1-'
Table 1
BURST DEFINITION
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Burst length
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Order of Accesses within a Burst
Burst
Length
Mode Register (Mx)
Starling Column
Address:
1
I
M2 M1MO
o
o
o
o
I
I
M3=O
M3=1
Reserved
Reserved
0 1
2
2
1 0
4
4
1 1
8
8
Reserved
Reserved
1 0 1
Reserved
Reserved
1 1 0
Aeserved
Reserved
111
Full Page
Reserved
M3
Burst Type
0
Sequential
1
Interleave
M6 M5M4
Type
=Interleaved
0-1
1-0
0-1
AU
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
2-3-0-1
3-0-1-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
A1
0 0
1 0 0
~
I
=Sequential
0
1
2
Burst Length
I
Type
AU
I
0
,
4
8
1-0
1
0
1
A2
A1
AU
0
0
0
0
0
1
0
0
1
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
1
0
1
1
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
0
1
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
1
Full
Page
n =AO -A7
(256)
(location 0 - 255)
Cn, Cn+ 1, Cn+2
Cn+3, Cn+4 ...
... Cn-l (Cn+256),
Not supported
Cn (Cn+257) ...
READ Latency
o
o
0 0
Reserved
0 1
Reserved
o
1 0
2
o
1 1
3
1 0 0
Reserved
1 0 1
Reserved
1 1 0
Reserved
111
Reserved
NOTE:
1. For a burst length of two, Al-A7 select the block of
two burst; AO selects the starting column within the
block.
2. For a burst length of four, A2-A7 select the block of
four burst; AO-Al select the starting column within
the block.
3. For a burst length of eight, A3-A7 select the block of
eight burst; AO-A2 select the starting column within
the block.
M9
M8
M7
M6- MO
Defined
4. For a full-page burst, the full row is selected and
AO-A7 select the starting column.
Operating Mode
Standard operation
5. Whenever a boundary of the block is reached within
All other states reserved
a given sequence above, the following access wraps
within the block.
Figure 1
MODE REGISTER DEFINITION
MT4tlC256K3:"J4(S)
G01.pm5-Rev.2/95
3-6
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII:::RCN
1-·
MT41 LC256K32D4(S)
256K X 32 SGRAM
,""","","0
Read Latency
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability of
the first piece of output data. The latency can be set to 2 or
3 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n + m. The DQs will start driving as a result of the clock edge
one cycle earlier (n + m -1) and, provided that the relevant
access times are met, the data will be valid by clock edge
n + m. For example, assuming that the clock cycle time is
such that all relevant access times are met, if a read command is registered at TO, and the latency is programmed to
2 clocks, the DQs will start driving afterTl and the data will
be valid byT2, as shown in Figure 2. Table 2 below indicates
the operating frequencies at which each READ latency
setting can be used.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
are "0" during a LOAD SPECIAL MODE REGISTER cycle,
the color register will be loaded with the data on the DQs.
Similarly, when input A5 is "1", and all other address
inputs are "0" during a LOAD SPECIAL MODE REGISTER
cycle, the mask register will be loaded with the data on the
DQs. Applying a "1" to both A5 and A6 (when all other
address inputs are "0") or applying a ''1'' to any address
input other thanA5 orA6,duringa LOAD SPECIAL MODE
REGISTER cycle is illegal and unknown operation may
result.
The special mode register can be loaded when one or
both banks are either active or idle. Successive LOAD
SPECIAL MODE REGISTER cycles to load the same register can be performed by applying a "1" to either A5 or A6,
even if a "1" was previously written to that bit (i.e., the bits
do not need to be cleared between loads).
COLOR REGISTER
The color register is a 32-bit register which supplies the
data during BLOCK WRITE cycles. The color register is
loaded via a LOAD SPECIAL MODE REGISTER cycle
(described in the previous section) and will retain data until
loaded again or until power is removed from the SGRAM.
Operating Mode
In normal operation (M7 - M9 = 0), the programmed
burst length applies to both read and write bursts.
M7 = 1 is used for vendor specific testing. Test modes and
reserved states should not be used because unknown operation or incompatibility with future versions may
result.
MASK REGISTER
The mask register (or write-per-bit mask register) is a 32bit register which acts as a per-DQ mask during MASKED
WRITE and MASKED BLOCK WRITE cycles. This operation is described under the respective headings later in this
data sheet. The mask register is loaded via a LOAD SPECIAL MODE REGISTER cycle (described previously, under the Special Mode Register heading) and will retain data
until loaded again or until power is removed from the
SGRAM.
SPECIAL MODE REGISTER
The special mode register is used to load the color and
mask registers, which are used in BLOCK WRITE and
MASKED WRITE cycles. The control information being
written to the special mode register is applied to the address
inputs and the data to be written to either the color register
or the mask register is applied to the DQs. As shown in
Figure 3, when input A6 is "1", and all other address inputs
TO
T1
T2
Table 2
READ LATENCY
T3
elK
ALLOWABLE OPERATING
FREQUENCY (MHz)
READ
LATENCY
DQ
Read latency
Figure 2
TWO CLOCK READ LATENCY EXAMPLE
MT41 LC256K32D4(S)
G01.pm5-Rev.2/95
3-7
READ
LATENCY
SPEED
=2
=3
-10
< 66
< 100
-12
< 55
~83
-15
<44
< 66
Micron Technology, lnc., reserves the righllo change products or specifications without notice.
©199S, Micron Technology, Inc.
z
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ADVANCE
MICRON
1-·
MT41 LC256K32D4(S)
256K x 32 SGRAM
"'»"'"''''
z
Address Bus (Ax)
m
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•
Special Mode Register (Mx)
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M4
M3
M2
M1
MO
o
o
o
o
o
Standard operation
All other states reserved
M5
Mask Register
o
Leave Unchanged
Load New Data
M6
Color Register
o
Leave Unchanged
Load New Data
M9
M8
M7
Operating Mode
All other states reserved
Figure 3
SPECIAL MODE REGISTER DEFINITION
MT41 LC256K32D4(S)
G01.pm5 - Rev. 2/95
3-8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT41 LC256K32D4(S)
256K x 32 SGRAM
"'""''''''''
Commands
the Operation section; these tables provide current state/
next state information.
Truth Table 1 provides a quick reference of available
commands. This is followed by a verbal description of each
command. Two additional Truth Tables appear following
:e
TRUTH TABLE 1 - Commands and DaM Operation
NAME (FUNCTION)
-cs-
RAS CAS
WE
DSF
DOM
ADDR
H
x
X
x
x
x
x
DOs
X
NOTES
COMMAND INHIBIT (NaP)
NO OPERATION (NaP)
L
H
H
H
L
X
X
X
13
ACTIVE (Select bank and activate row)
L
L
H
H
L
X
bank/row
X
3
ACTIVE with WPB (Select bank,
activate row and WPB)
L
L
H
H
H
X
bank/row
X
3, 11
X
4, 13
READ (Select bank & column and start READ burst)
L
H
L
H
L
X
bank/col
WRITE (Select oank& column and
start WRITE burst)
L
H
L
L
L
X
bank/col VALID
4
BLOCKWRITE (Select bank & column and
start BLOCK WRITE access)
L
H
L
L
H
X
bank/col MASK
4, 12
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
L
X
Code
X
5, 13
BURST TERMINATE
L
H
H
L
L
X
X
Active
13
AUTO REFRESH or
SELF REFRESH (enter SELF REFRESH mode)
L
L
L
H
L
X
X
X
6,7,
LOAD MODE REGISTER
L
L
L
L
L
X
OpCode
X
LOAD SPECIAL MODE REGISTER
L
L
L
L
H
X
OpCode VALID
10
Write enable/output enable
-
-
-
L
Active
S
-
-
-
-
-
Write inhibit/output High-Z
-
H
High-Z
S
NOTE:
13
2
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. AO through AS and BA define the op,code written to the mode register.
3. AO through AS provide row-address andBA determines which bank is made active (BA LOW = Bank O.and
BA HIGH = Bank 1).
4. AO through A7 provide column-address; AS HIGH enables the AUTO PRECHARGE feature (nonpersistent)
while AS LOW disables the AUTO PRECHARGE feature; BA determines which bank is being read from or
written to (BA LOW = Bank 0 and BA HIGH = Bank 1) ..
5. AS LOW: BA determines bank being precharged (BA LOW = Bank 0 and BA HIGH= Bank 1). AS HIGH:
both banks precharged and BA is a "don't care."
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "don't care" except for CKE.
S. Activates or deactivates the DOs during WRITEs (zero-clock delay) and READs (two-clock delay).
9. Illegalon non-S version.
10.. DOs contain either color data or WPB mask data.
11. Any WRITE or BLOCK WRITE cycles to the selected bank/row while active will be masked according to the
contents of the masklegister, in addition to the DOM signals and the column/byte mask iflformation(the latter
for BLOCK WRITEs only).
12, DOs contain the column/byte mask, data for the BLOCK WRITE.
13. DSF is actually "don't care", but it is recommended to be LOW for compatibility with future devices.
MT41lC256K32D4(S)
G01.pm5- Rev. 2/95
3-9
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
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ADVANCE
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MT41 LC256K32D4(S)
256K x 32 SGRAM
"'""'co"'"'
starting column location. The value on input AS determines
whether or not AUTO PRECHARGE is used. If AUTO
PRECHARGE is selected, the row being accessed will be
precharged at the end of the read burst; if it is not selected,
the row will remain open for subsequent accesses. READ
data appears on the DQs subject to the values on the DQM
inputs two clocks earlier. If a particular DQM signal was
registered HIGH, the corresponding DQs will be High-Z
two clocks later; if the DQM signal was registered LOW, the
DQs will provide valid data.
COMMAND INHIBIT
The COMMAND INHIBIT function prevents commands
from being executed by the SGRAM, regardless of whether
the eLK signal is enabled. The SGRAM is effectively deactivated, or deselected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SGRAM which is selected (CS is LOW).
This prevents unwanted commands from being registered
during idle or wait states.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA input selects the
bank, and the address provided on inputs AO-A7 selects the
starting column location. The value on input AS determines
whether or not AUTO PRECHARGE is used. If AUTO
PRE CHARGE is selected, the row being accessed will be
precharged at the end of the write burst; if it is not selected,
the row will remain open for subsequent accesses. Input
data appearing on the DQs is written to the memory array
subject to the DQM signals registered coincident with the
data. If a particular DQM signal is registered LOW, the
corresponding data will be written to memory (subject also
to the write-per-bit mask, if activated); if the DQM signal is
registered HIGH, the corresponding data inputs will be
ignored, and the write will not be executed to that byte
location.
LOAD MODE REGISTER
The mode register is loaded via inputs AO-AS and BA.
See Mode Register heading in Register Definition section.
The LOAD MODE REGISTER command can only be issued
when both banks are idle, and a subsequent executable
command cannot be issued until tMTC is met.
LOAD SPECIAL MODE REGISTER
This command is used to load either the color register or
mask register by activating the appropriate bit in the special
mode register. The control information is provided on
inputs AO-AS and BA, while the data for the color or mask
register is provided on the DQs. See Special Mode Register
heading in Register Definition section. The LOAD SPECIAL MODE REGISTER command can be issued when
both banks are idle, or one or both are active, but with no
READ, WRITE or BLOCK WRITE accesses in progress. A
subsequent executable command cannot be issued until
tSML is met.
BLOCK WRITE
The BLOCK WRITE command is used to write a single
data value to the block of eight consecutive column locations addressed by inputs A3-A7. The source of the data is
the color register, which must be loaded prior to the BLOCK
WRITE. The information on the DQs which is registered
coincident with the BLOCK WRITE command is used to
mask specific column/byte combinations within the block,
as described in the Operation section of this data sheet. The
DQM signals operate as for WRITE cycles, but are applied
to all eight columns.
ACTIVE
The ACTIVE command IS used to open (or activate) a row
in a particular bank for a subsequent access. The value on
the BA input selects the bank, and the address provided on
inputs AO-AS selects the row. This row remains active (or
open) for accesses until a precharge command is issued to
that bank. A PRECHARGE command must be issued before opening a different row in the same bank.
ACTIVE WITH WPB
This command is similar to the ACTIVE command, except that the write-per-bit mask is activated. Any WRITE or
BLOCK WRITE cycles to the selected bank/row while
active will be masked according to the contents of the mask
register, in addition to the DQM signals, and the column/
byte mask information (the latter for BLOCK WRITEs only).
PRECHARGE
The PRE CHARGE command is used to deactivate the
open row in a particular bank, or the open row in both
banks. The bank(s) will be available for a subsequent row
access some specified time (tRP) after the precharge command is issued. Input AS determines whether one or both
banks are to be precharged, and in the case where only one
bank is to be precharged, input BA selects the bank. Otherwise BA is treated as a "don't care". Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ, WRITE or BLOCK WRITE commands being
issued to that bank.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA input selects the bank,
and the address provided on inputs AO-A7 selects the
MT41 LC256K32D4{S)
G01.pmS -Rev. 2195
3-10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII:::RCN
1-·
MT41 LC256K32D4(S)
256K X 32 SGRAM
",",owo,,",
AUTO PRE CHARGE
AUTO PRECHARGE is a nonpersistent feature which
performs all of the same individual-bank precharge functions as previously described. The AUTO PRECHARGE
feature allows the user to issue a READ, WRITE or BLOCK
WRITE command that automatically performs a precharge
upon the completion of the BLOCK WRITE access or READ
or WRITE burst, except in the full-page burst mode, where
it has no effect.
The use of this feature eliminates the need to "manually"
issue a PRECHARGE command during the functional operation of the SGRAM. AUTO PRECHARGE ensures that
the precharge is initiated at the earliest valid stage within a
burst. The user must not issue another command until the
precharge time (tRP) is completed. This is determined as if
a manual PRECHARGE command was issued at the earliest possible time, as described for each burst type in the
Operation section of this data sheet.
AUTO REFRESH command. The MT41LC256K32D4(S)
requires all of its 1,024 rows to be refreshed every 17ms
(tREF). Providing a distributed AUTO REFRESH command
every 16.6~s will meet the refresh requirement and ensure
that each row is refreshed. Alternatively, all 1,024 AUTO
REFRESH commands can be issued in a burst at the minimum cycle rate (tRC) once every 17ms.
SELF REFRESH
The SELF REFRESH command (on the "S" version) can
be used to retain data in the SGRAM, even if the rest of the
system is powered down. When in the SELF REFRESH
mode, the SGRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW). Once
the SELF REFRESH command is registered, all the inputs to
the SGRAM become "don't cares" with the exception of
CKE, which must remain LOW.
Once SELF REFRESH mode is engaged, the SGRAM
provides its own internal clocking, causing it to perform its
own auto refresh cycles. The SGRAM may remain in SELF
REFRESH mode for an indefinite period.
The procedure for exiting SELF REFRESH requires a
sequence of commands. First, the system clock must be
stable prior to CKE going back HIGH. Once CKE is HIGH,
the SGRAM must have NOP commands issued for tXSR,
because time is required for the completion of any bank
currently being internally refreshed.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
either fixed-length or full-page bursts.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
SGRAM and is analagous to CAS-BEFORE-RAS (CBR)
REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is
required.
The addressing is generated by the internal refresh controller. This makes the address bits a "don' t care" during an
MT41 LC256K32D4(S}
G01.pm5 - Rev. 2195
3-11
Micron Tachnology, Inc., reserves the nght to change products or specifications without notice
©1995, Micron Technology, Iilc.
ADVANCE
MIC:RON
1-·
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",",",c'"
MT41 LC256K32D4(S)
256K X 32 SGRAM
"
Operation
BANKJROWACTIVATION
Before any READ or WRITE commands can be issued to
a bank within the SGRAM, a row in that bank must be
"opened." This is accomplished via the ACTIVE command,
which selects both the bank and the row to be activated.
The ACTIVE command is also used to determine whether
or not the write-per-bit mask is to be applied duringWRITE
and BLOCK WRITE cycles within that row (see Figure 4).1£
DSF is HIGH at the time the ACTIVE command is registered (ACTIVE with WPB) then the mask will be applied to
all WRITE and BLOCK WRITE cycles to that row until the
row is "dosed"(precharged).
After opening a row (issuing an ACTIVE command) a
READ or WRITE command may be issued to that row,
subject to the IRCD specification. IRCD MIN should be
divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after the
ACTIVE command on which a READ or WRITE command
can be entered. For example, a IRCD specification of 30ns
with a 90 MHz clock (11.11ns period) results in 2.7 docks
rounded to 3. This is reflected in Figure 5, which covers any
case where 3 > IRCD MIN lICK> 2. (The same procedure is
used to convert other specification limits from time units to
clock cycles).
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active row
has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same
bank is defined by IRe.
A subsequent ACTIVE command to the other bank can be
issued while the first bank is being accessed, which results
in a reduction of total row access overhead. The minimum
time interval between successive ACTIVE commands to
.
different banks is defined by IRRD.
CLK~
CKE
HIGH
cs ~$$l@~
/#/1/1/1&1,
RAS
0'Z0'I$&~
M///;I//&
CAS
WI$$I//!
'?&I//#/~
WE
DSF
'11/$/111II!1/1
WI//II/;/';0(
W$&~
,
ENABLE WPB
~
DISAB~E
,
WPB
AO-AS
1j/j1l!/1I1I/~!II!IIffi
BA
W/$/#II/~/##Ij'm;
BANK 1
BANKO
Ez:;l DON'T CARE
Figure 4
ACTIVATING A SPECIFIC ROW IN A
SPECIFIC BANK
T1
TO
T2
T3
T4
CLK
COMMAND
~
+"
)@(
NOP
X0<
NOP
)@(
:t~~
~
4
IRCD
Figure 5
EXAMPLE: MEETING tRCD MIN WHEN 2 < tRCD MINJfCK < 3
MT41 LC256K32D4(S)
G01.pmS - Rev. 2195
3-12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
F·
MT41 LC256K32D4(S)
256K x 32 SGRAM
"",cco",,,
READs
READ bursts are initiated with a READ command, as
shown in Figure 6.
The starting column and bank addresses are provided
with the READ command and AUTO PRECHARGE is
either enabled or disabled for that burst access. If AUTO
PRECHARGE is enabled, the row being accessed is
precharged at the completion of the burst. For the generic
READ commands used in the following illustrations, AUTO
PRECHARGE is disabled.
During READ bursts, the valid data-out elementfrom the
starting column address will be available following the
READ latency after the READ corrimand. Each subsequent
data-out element will be valid by the next positive clock
edge. Figure 7 shows the case where the READ latency is set
to two, and Figure 8 shows a READ latency of three.
CKE
L
f
ClK
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A fullpage burst will continue until terminated (at the end of the
page it will wrap to column 0 and continue).
A fixed-length READ burst may be followed by, or truncated with, a subsequent READ burst (provided that AUTO
PRECHARGE is not activated) and a full-page READ burst
can be truncated with a subsequent READ burst. In either
case, a continuous flow of data can be maintained. The first
data element from the new burst follows either the last
element of a completed burst, or the last desired data
element of a longer burst which is being truncated. The new
READ command should be issued x cycles before the clock
edge at which the last desired data element is valid, where
TO
T1
T2
T3
ClK
HIGH
COMMAND
CS
RAS
CAS
WE
DSF
AD-A?
~II1/1//1//$A
$I!!II&M
7i/I!///1#/l1;J
V!I!IIII/IilL
W!$////lIIA
!/I/I&/hiL
DQ
Read Latency
Figure 7
READ BURST WITH READ
LATENCY OF TWO
W;J#//lm
Willi!I///I!J7
lII/!////I!li,
711/I/1////11£
WI///III//3/ fg~~~s~ WIll/lid
TO
I
I
T4
T3
COMMAND
ENABLE AUTO PRE CHARGE
A8
T2
T1
ClK
1j/;;"TTT71/~=W;JIIIIffi
TTT7
TTT771/1!1
DO---t--------------~~~~~~
DISABLE AUTO PRECHARGE
I
BANK 1
SA
Read Latency
7!l/l1I111I//~/II/I/1/li,
BANKO
Figure 6
READ COMMAND
MT41 LC256K32D4(S)
G01.pm5-Aev,2/95
~
DON'T CARE
~
UNDEFINED
Figure 8
READ BURST WITH READ LATENCY
OF THREE
3-13
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©1995, Micron Technology, Inc.
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MT41 LC256K32D4(S)
256K x 32 SGRAM
","",CO"""
READ command can be initiated on any clock cycle following a previous READ command. Full speed random read
accesses within a page can be performed as shown in
Figures 11 and 12.
x equals the read latency minus one. This is shown in
Figure 9 for a read latency of two and Figure 10 for a read
latency ofthree; data element n + 3 is either the last of a burst
of four, or the last desired of a longer burst. The SGRAM
does not require the 2n rule of prefetch architectures, so a
II
TO
en
T1
T2
T4
T3
T5
T6
ClK
C)
:::D
»
COMMAND
,
S
,
I"
" I
ADDRESS
DO
NOTE: Covers either successive READs to the active row in a given bank,
or to the active rows in different banks. DOMs are all active (lOW).
Figure 9
CONSECUTIVE READ BURSTS, READ LATENCY OF TWO
TO
T1
T2
T3
T4
T5
T6
T7
ClK
COMMAND
,
,
x= 2 cycles
"
ADDRESS
DO
NOTE: Covers either successive READs to the active row in a given bank,
or to the active rows in different banks. DOMs are all active (lOW).
~
DON'TCARE
Figure 10
CONSECUTIVE READ BURSTS, READ LATENCY OF THREE
MT41lC256K32D4(S)
G01.pm5-Aev.2195
3-14
Micron Technology, Inc., reserves the right to change products orspectficatlonswlthout notic e.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT41 LC256K32D4(S)
256K X 32 SGRAM
,""'.owe""
TO
T1
T2
T3
T4
T5
Z
ClK
m
COMMAND
~
READ
K
READ
ADDRESS
~
BANK,
COLn
K
BANK,
COLa
,
X
READ
><
I
I
><
Nap
X
:e
•
K
I
I
I
BANK,
Calm
Nap
en
~
m
I
I
(
DO
X
BANK,
Calx
X
READ
X:
DO~T
I
X
DOaUT
I
DOUT
x
X:
DOUT
m
:xJ
l>
t
s::
NOTE: Covers either successive READs to the active row in a given bank,
or to the active rows in different banks. DOMs are all active (lOW).
Figure 11
RANDOM READ ACCESSES WITHIN A PAGE, READ LATENCY OF TWO
TO
T1
T2
T3
T4
T5
T6
ClK
COMMAND
~
READ
K
READ
X
READ
X
X X X
Nap
READ
I
I
ADDRESS
-\
BANK,
Cal n
Nap
Nap
>C
I
I
K ~ANK' X~ANK' X ~ANK' wP~
COla
COL x
COlm
,
\
DO
DOUT
n
X
DOUT
X
DOUT
x
X
DOUT
m
)-
NOTE: Covers either successive READs to the active row in a given bank,
or to the active rows in different banks. DOMs are all active (lOW).
tZ2 DON'T CARE
Figure 12
RANDOM READ ACCESSES WITHIN A PAGE, READ LATENCY OF THREE
MT41 LC256K32D4(S)
G01.pm5 - Rev. 2195
3-15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII:::r=lCN
1-·
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MT41 LC256K32D4(S)
256K X 32 SGRAM
m",",,,,,,
A fixed-length READ burst may be followed by, or truncated with, a WRITE burst or BLOCK WRITE command
(provided that AUTO PRECHARGE was not activated)
and a full page READ burst may be truncated by a WRITE
burst or BLOCK WRITE command. The WRITE burst may
be initiated on the clock edge immediately following the
last (or last desired) data element from the READ burst,
provided that I/O contention can be avoided. If the specifications for a given speed grade do not allow for contention
to be avoided at a particular operating frequency, a single
cycle delay must occur between the last READ data and the
WRITE command.
TO
T1
T2
T3
The DQM inputs are used to avoid I/O contention as
shown in Figures 13 and 14. The DQMs must be asserted
(HIGH) at least two clocks (DQM latency is two clocks for
output buffers) prior to the WRITE command to suppress
data-out from the READ. Once the WRITE command is
registered, the DQs will go High-Z (or remain High-Z)
regardless ofthe state of the DQM signals. The DQM signals
must be de-asserted (DQM latency is zero clocks for input
buffers) prior to the WRITE command to ensure that the
written data is not masked. Figure 13 shows the case where
the clock frequency allows for bus contention to be avoided
without adding a NOP cycle, and Figure 14 shows the case
where the additional NOP is needed.
TO
T4
T1
T2
T3
T4
T5
CLK
CLK
,
DOM
LL0,'-;--~r---';n'----r--r----
COMMAND
DOM
COMMAND
ADDRESS
ADDRESS
DO
DO
NOTE: A READ LATENCY of 3 is used for illustration. A BLOCK WRITE
can be substituted for the WRITE, in which case column/byte mask
data would be applied to the data inputs.
fz:;1 DON'T CARE
NOTE: A READ LATENCY of 3 is used for illustration. A BLOCK WRITE
can be substituted for the WAITE, in which case column/byte mask
data would be applied to the data inputs.
Figure 14
READ TO WRITE (OR BLOCK WRITE)
WITH EXTRA CLOCK CYCLE
Figure 13
READ TO WRITE (OR BLOCK WRITE)
MT41 LC256K32D4(S)
G01.pm5- Rev. 2195
3-16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT41 LC256K32D4(S)
256K X 32 SGRAM
"'"","0",,"'
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank
(provided that AUTO PRECHARGE was not activated)
and a full-page burst may be truncated with a PRECHARGE
command to the same bank. The PRECHARGE command
should be issued one cycle before the clock edge at which
the last desired data element is valid. This is shown in
Figure 15 for a read latency of two and Figure 16 for a read
latency of three; data element n + 3 is either the last of a burst
TO
T1
T2
of four, or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the
same bank cannot be issued until t:RPis met. Note that part
of the row precharge time is hidden during the access of the
last data element.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed.,length burst
T3
T4
T5
T6
T7
ClK
COMMAND
ADDRESS
DQ--~------~--~
NOTE: DOMs are all active (LOW).
Figure 15
READ TO PRECHARGE, READ LATENCY OF TWO
TO
T1
T2
T3
T4
T5
T6
T7
TB
ClK
COMMAND
ADDRESS
DQ
~ DON'TCARE
NOTE: DQMs are all active (LOW).
Figure 16
READ TO PRECHARGE, READ LATENCY OF THREE
MT41 LC256K32Q4(S)
G01.pmS - Rev. 2/95
3-17
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
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MT41 LC256K32D4(S)
256K x 32 SGRAM
'''"'''''''"'
with AUTO PRE CHARGE. The disadvantage of the
PRECHARGE command is it requires that the command
and address busses be available at the appropriate time to
issue the command, but the advantage of the PRECHARGE
command is that it can be used to truncate fixed-length or
full-page bursts. The AUTO PRECHARGE command does
not truncate fixed-length bursts and does not apply to full
page bursts.
Full-page READ bursts can be truncated with the BURST
TERMINATE command, and fixed-length READ bursts
may be truncated with a BURST TERMINATE command,
provided that auto-precharge was not activated. When
truncating a READ burst, the BURST TERMINATE command should be issued 1 cycle before the clock edge at
which the last desired data element is valid. This is shown
in Figure 17 for a read latency of two and Figure 18 for a read
latency of three; data element n + 3 is either the last of a burst
of four, or the last desired of a longer burst.
C)
:D
TO
»
3:
T1
T3
T2
T4
T5
T6
COMMAND
ADDRESS
DQ
Dour
Dour
n
n+3
NOTE: DOMs are all active (lOW).
Figure 17
TERMINATING A READ BURST, READ LATENCY OF TWO
TO
T1
T2
T3
T4
T5
T6
T7
ClK
COMMAND
ADDRESS
DO
~
NOTE: DQMs are all active (LOW).
DONTCARE
Figure 18
TERMINATING A READ BURST, READ LATENCY OF THREE
MT41 LC256K32D4(S)
G01.pmS - Rev. 2195
3-18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT41 LC256K32D4(S)
256K x 32 SGRAM
"'"'oco"',,,
WRITEs
WRITE bursts are initiated with a WRITE command, as
shown in Figure 19.
The starting column and bank addresses are provided
with the WRITE command, normal or BLOCK WRITE is
selected, and AUTO PRECHARGE is either enabled or
disabled for that access. If AUTO PRECHARGE is enabled,
the row being accessed is precharged at the completion of
the burst. BLOCK WRITEs are covered later in this section.
For the generic WRITE commands used in the following
illustrations, AUTO PRECHARGE is disabled, and all
WRITEs are normal WRITEs unless noted.
During WRITE bursts, the first valid data-in element will
be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length
burst, assuming no other commands have been initiated,
the DQs will remain High-Z, and any additional input data
will be ignored (see Figure 20). A full-page burst will
continue until terminated (at the end ofthepage it will wrap
to column 0 and continue).
A fixed-length WRITE burst may be followed by, or
truncated with, a subsequent WRITE burst or BLOCK
WRITE command (provided that AUTO PRECHARGE
was not activated) and a full page WRITE burst can be
truncated with a subsequent WRITE burst or BLOCK WRITE
command. The new WRITE or BLOCK WRITE command
can be issued on any clock following the previous WRITE
command, and the data provided coincident with the new
command applies to the new command. An example is
shown in Figure 21. Data n + 1 is either the last of a burst of
two, or the last desired of a longer burst. The SGRAM does
TO
T1
T3
T2
ClK
ADDRESS
DO
NOTE: Burst length = 2.
DOMs are all active (LOW).
HIGH
TO
cs
W/!/$#;%
$###lM
RAS
W/#I#//I/!l
'WI;W#m;
W$h'#$!/2i,
1$$/#;l2
CAS
WE
AQ·A7
0'11/!#$i7X
W#/#/#IA\
I
I
ADDRESS
I
I
I
~$I/III$J<
I
I
~
I
I
~
~
NOTE: DQMs are all active (LOW). The second
WRITE can be a BLOCK WRITE, in which
case column/byte mask data would be
applied to the data inputs.
~
DISABLE AUT(j)-PRECHARGE
BANk 1
BA
I
DQ -~
ENABLE AUTO-PRECHARGE
AS
I
~ 17777771},!BANK.\ r;
I
'I!!ll7llllJ
NORMA1L WRITE
COLUMN
ADDRESS
T2
COMMAND~
BLOCK WRITE
DSF
T1
CLKJULrL
iI#/I/I//~
W/$$#;0.
~
Y$/!/!##mc=J07$/!#&
DON'T CARE
BANKO
Figure 21
WRITE TO WRITE (OR BLOCK WRITE)
Figure 19
WRITE COMMAND
MT41LC256K32D4(S)
G01.pmS - Rev. 2195
3-19
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»
s
COMMAND
Figure 20
WRITE BURST
eKE
z
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
z
m
:e
•
MT41 LC256K32D4(S)
256K x 32 SGRAM
.,,""'''''"'
not require the 2n rule of prefetch architectures, so a
WRITE command can be initiated on any clock cycle
following a previous WRITE command. Full speed random
write accesses within a page can be performed as shown in
Figure 22.
A fixed-length WRITE burst may be followed by, or
truncated with, a subsequent READ burst (provided that
AUTO PRECHARGE was not activated) and a full-page
WRITE burst can be truncated with a subsequent READ
burst. Once the READ command is registered, the data
inputs will be ignored, and writes will not be executed. An
example is shown in Figure 23. Data n + 1 is either the last
of a burst of two, or the last desired of a longer burst.
A fixed-length WRITE burst may be followed by, or
truncated with, a PRECHARGE command to the same bank
(provided that AUTO PRECHARGE was not activated)
and a full-page WRITE burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued y cycles after the
clock edge at which the last desired input data clement is
registered, where y equals tWR/tCKrounded up to the next
,"vhole number. In addition, the DQ~1 signals Hlust be used
to mask input data, starting with the clock edge following
the last desired data element and ending with the clock
edge on which the PRECHARGE command is entered. An
example is shown in Figure 24. Data n + 1 is either the last
of a burst of two, or the last desired of a longer burst.
Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst
with AUTO PRECHARGE. The disadvantage of the
PRECHARGE command is it requires that the command
and address busses be available at the appropriate time to
issue the command, but the ad vantage of the PRECHARGE
command is that it can be used to truncate fixed-length or
full-page bursts. The AUTO PRECHARGE command does
not truncate fixed-length bursts and does not apply to full
page bursts.
en
C)
TO
:D
T1
T2
T3
l>
S
COMMAND
ADDRESS
DO
NOTE: Covers either successive WRITEs to the active row
in a given bank, or to the active rows in different banks.
DOMs are all active (LOW).
Figure 22
RANDOM WRITE CYCLES WITHIN A PAGE
TO
TO
T1
T2
T3
T4
T5
T1
T2
T3
T4
T5
T6
ClK
DQM
COMMAND
COMMAND
ADDRESS
DO
NOTE: Covers either a WRITE and READ to the active row in a given bank, or to the
active rows in different banks. DQMs are all active (LOW).
READ LATENCY = 2 for illustration.
MT41 LC256K32D4(S)
G01.pmS - Rev. 2/95
NOTE: The DaMs could remain low in this example
if the WRITE burst is a fixed length of 2.
~
Figure 23
Figure 24
WRITE TO READ
WRITE TO PRECHARGE
3-20
DONTCARE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology, Inc.
ADVANCE
MICRON
1-·
MT41 LC256K32D4(S)
256K x 32 SGRAM
'''"",co,""'
DRAM
CELLS
MASK
Fixed-length or full-page WRITE bursts can be truncated
with the BURST TERMINATE command. When truncating
1 WRITE burst, the input data applied one clock edge prior
to the BURST TERMINATE command will be the last data
written. This is shown in Figure 25, where data n + 1 is either
the last of a burst of two, or the last desired of a longer burst.
REGISTER
,--
---~
MR3l
I--
0030
f-
OQ29
MR30
:
=-r-
fMR28
DO"
I--
DQ27
I--
T1
T2
I--
--.J
ff-
MR29
1
0""
MR26
T3
I--
f-
~
MR27
TO
r-
OQ31
f-
OQ25
I--
0024
=-r-
J
fI--
MR25
ClK
1
MR24
~
~
DRAM
CELLS
MASK
REGISTER
COMMAND
r-
,--
ADDRESS
~
f-
DO'"
I--
OQ21
fI--
MR'"
I--
I--
=-r--1
MR'"
DQ
f-
OQ19
I--
0018
MRt9
~
-,
I--
DON'T CARE
ff----
f--
I--
'--
~
MRt6
'--
Figure 25
TERMINATING A WRITE BURST
DRAM~
OOM1
MASK
CELLS
REGISTER
,--
rOQ15
f-
~
f--
===!O- -.J
I--
MASKED WRITES
Any WRITE performed to a row that was opened via an
ACTIVEwithWPB command is a MASKED WRITE (WritePer-Bit). Data is written to the 32 cells (bits) at the selected
column location subject to the mask stored in the WPB mask
register. If a particular bit in the WPB mask register is a "0",
the data appearing on the corresponding DQ input will be
ignored, and the existing data in the corresponding DRAM
cell will remain unchanged. If a mask bit is a "I", the data
appearing on the correspondingDQ input will be written to
the corresponding DRAM cell.
The overall WRITE mask consists of a combination of
the DQM inputs, which mask on a per-byte basis, and the
WPB mask register, which masks on a per-bit basis. This is
shown in Figure 26. If a particular DQM signal was registered HIGH, the corresponding byte will be masked. A
given bit is written only if the corresponding DQM signal
registered is "0" and the corresponding WPB mask register
bitis "I".
I--
I--
f---
f-
,~
r-
0010
i-
DO'
=-r--1
OO,
'-DRAM
DOMO
MASK
REGISTER
CELLS
r-
,-MR'
I--
1
I--
.J
f-
DO,
I--
r-
=
s:
ADVANCE
MIC:RON
1-·
MT41 LC256K32D4(S)
256K x 32 SGRAM
'''"",co", '"'
BLOCK WRITES
BLOCK WRITEs are non-burst accesses that write to
eight column locations simultaneously. A single data value,
which was previously loaded in the color register, is written
to the block of eight consecutive column locations addressed by inputs A3-A7. The information on the DQs
which is registered coincident with the BLOCK WRITE
command is used to mask specific column/byte combinations within the block. The mapping of the DQ inputs to the
column/byte combinations is shown in Table 3.
When a "0" is registered on a particular DQ signal coincident with a BLOCK WRITE command, the write to the
corresponding coiumn/byte combination is masked (the
existing data in the corresponding DRAM cells will remain
unchanged). When a "1" is registered, the color register
data will be written to the corresponding DRAM cells,
subject to the DQM and WPB masking.
The overall BLOCK WRITE mask consists of a combination of the DQM Signals, the WPB mask register and the
column/byte mask information, as shown in Figure 27. The
DQM and WPB mask register masking operates as for
normal WRITEs, with the exception that the mask information is applied simultaneously to all eight columns. Therefore, in a BLOCK WRITE, a given bit is written only if a "0"
was registered for the corresponding DQM signal, a ''1''
was registered for the corresponding DQ signal, and the
corresponding bit in the WPB mask register is "1".
A BLOCK WRITE access requires a time period of IBWC
to execute, so in general, the cycle after the BLOCK WRITE
command should be a NOP. However, ACTIVE or
PRE CHARGE commands to the other bank are allowed.
When following a BLOCK WRITE with a PRECHARGE
command to the same bank, IBPL (instead of IBWC) must be
met.
MT41 LC256K32D4(S)
G01.pm5 -Rev. 2/95
Table 3
MAPPING OF DQs TO COLUMN/BYTE
LOCATIONS WITHIN A BLOCK
3-22
DQINPUTS
COLUMNADDRESS
CONTROllED
A2
A1
AD
DOO
D01
D02
D03
D04
D05
D06
D07
D08
D09
D010
D011
D012
D013
D014
D015
D016
D017
D018
D019
D020
D021
D022
D023
D024
D025
D026
D027
D028
D029
D030
D031
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DQ PLANES
CONTROllED
.~
0-7
0-7
0-7
0-7
0-7
0-7
0-7
0-7
8-15
8-15
8-15
8-15
8-15
8-15
8-15
8-15
16-23
16-23
16-23
16-23
16'23
16-23
16-23
16-23
24-31
24-31
24-31
24-31
24-31
24-31
24-31
24-31
Micron Technology, Inc., reserves the right to change products or specifications wlthbut notice.
©1995, Micron Techno[ogy, Inc.
ADVANCE
MICRON
I~·
MT41 LC256K32D4(S)
256K X 32 SGRAM
,"""0",",'"
z
m
I
DQ24...oi!
DQ2S.....t:
OQ26...o1!
0027....01
DQ28~W
0029
OQ30
OQ31
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:s:
0016
0017
0018
,:,~~~~~~~~
<;K;'r;u;>;>; X;>; f~ltj ~"~R~'6ij~~~~
I
~:::""'-L.Jco=
0019
r
::::,,! )
BLOCK OF COLUMNS
,
MA19I-+'LJCOr-r;",
(SELECTED BY
AS-A7 REGISTERED
COINCIDENT WITH
MR20W:!D+irl-t-il.1
MR21
BLDCKWRITE
I-->-''LJ-,-,-,-,-n;"
MR22W:!D+irH+i"l!l.1
COMMAND)
MR23~!()+t+t+++b.
DQM2
ROWIN BANK
(SELECTED BY
AD-AS, AND SA
REGISTERED
COINCIDENT
WITH ACTIVE
COMMAND)
MASK
REGISTER
(PREVIOUSLY
LOADED
FROM
CORRESPONDING
DQ INPUTS)
COLOR REGISTER
(PREVIOUSLY LOADED FROM
CORRESPONDING DO INPUTS)
Figure 27
BLOCK WRITE MASKING - FUNCTIONAL REPRESENTATION
MT41 LC256K32D4(S)
G01.pm5-Rev.2I95
3-23
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©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
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MT 41 LC256K32D4(S)
256K x 32 SGRAM
",",",,"e,,,,
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank, or the open row in both
banks. The bank(s) will be available for a subsequent row
access some specified time (lRp) after the precharge command is issued. Input A8 determines whether one or both
banks are to be precharged, and in the case where only one
bank is to be precharged, input BA selects the bank. Otherwise BA is treated as a "don't care". Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ, WRITE or BLOCK WRITE commands being
issued to that bank.
POWER-DOWN
POWER-DOWN occurs when both banks are in the
idle state (precharged) and CKE is registered LOW (see
Figure 29). Entering POWER-DOWN deactivates the input
and output buffers, excluding CKE, for maximum power
savings while in standby. The device may not remain in
the POWER-DOWN state longer than the refresh period
(17ms) since the command does not perform any refresh
operations.
The POWER-DOWN state is exited by taking CKE back
HIGH. CKE must go HIGH ICKS before a positive clock
edge, after meeting ICKH from the previous clock edge. The
first command after exiting POWER-DOWN will be registered on the clock edge following tcKS.
ClK
CKE
HIGH
CS
WIll//II/!1£
/!1/11III/Ih
RAS
~III//II!//I/lL1
!l/IIIIII/M
CAS
WE
DSF
7jj/I1/II/l!!/$
'WI/II/1M
WI!//II/!II£
7Jl!1/!!///I/!A
II/!1//1/!!l2
!l!/l/l1I/1!/;
AD-A?
7//1///I//IIdI//!/!!III!M1I!/llIh
AS
111/11/111/;0(~;;--;-X1lUllJZ
Input buffers gated off
Enter POWERDOWN mode
Exit POWERDOWN mode
tRC
Figure 29
POWER-DOWN
BANKQ and 1
BANKOor1
I
I
BANK 1
BA
7I!I/!!IIII//~II!/I!l2
BANKO
~
DON'T CARE
Figure 28
PRECHARGECOMMAND
MT41 LC25 6K 32D4(S)
GOt.pm5- Rev. 2/95
3-24
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©1995, Micron Technology, Inc.
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MICRON
MT41 LC256K32D4(S)
256K x 32 SGRAM
"'~'oco,,'"
1-·
TRUTH TABLE 2 - CKE
(Notes 1-4)
CKE n-1
CKEn
L
L
H
L
H
L
H
H
CURRENT STATE
COMMAND n
NOTES
POWER-DOWN
X
Maintain POWER-DOWN
SELF REFRESH
X
Maintain SELF REFRESH
POWER-DOWN
COMMAND INHIBIT or NOP
Exit POWER-DOWN
7
SELF REFRESH
COMMAND INHIBIT or NOP
Exit SELF REFRESH
6,8
Both Banks Idle
COMMAND INHIBIT or NOP
POWER-DOWN Entry
AUTO REFRESH
SELF REFRESH Entry
Both Banks Idle
NOTE:
ACTION n
6
5
See Truth Table 3
1.
2.
3.
4.
5.
6.
7.
CKEn is the logic state of CKE at clock edge n; CKE n_1 was the state of CKE at the previous clock edge.
CURRENT STATE is the state of the SGRAM immediately prior to clock edge n.
COMMAND n is the command registered at clock edge nand ACTION n is a result of COMMAND n .
All states and sequences not shown are illegal or reserved.
Illegal on non "S" devices.
Not available on non "S" devices.
Exiting POWER-DOWN at clock edge n will put the device in the "all banks idle" state in time for clock
edge n+1.
8. Exiting SELF REFRESH at clock edge n will put the device in the "all banks idle" state once tXSR is
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occuring during the
IXSR period.
MT41 LC256K32D4(S)
G01.pmS- Rev. 2/95
3-25
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©199s, Micron Technology, Inc.
z
m
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•
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C)
:a
»
s:
ADVANCE
AJIIICI=ICN
1-·
Z
m
•
==
en
C)
MT41 LC256K32D4(S)
256K X 32 SGRAM
"'""OCOC,,,,,
TRUTH TABLE 3 - Current State
(Notes 1-3; notes appear on next page)
CURRENT STATE
CS
Any
H
Idle
:lJ
l>
s:
Row Active
RAS CAS
X
X
WE
X
DSF
X
COMMAND/ACTION
NOTES
COMMAND INHIBIT (NOP/ continue previous operation)
L
H
H
H
L
NO OPERATION (NOP/ continue previous operation)
L
L
H
H
L
ACTIVE (Select bank and activate row)
L
L
H
H
H
ACTIVE w/wPB (Select bank, activate row and WPB)
L
L
L
H
L
AUTO REFRESH
5
L
L
L
L
L
LOAD MODE REGISTER
L
L
L
L
H
LOAD SPECIAL MODE REGISTER
5
6
L
H
L
H
L
RE1f.,D (Select bank and column and start READ bUist)
7
L
H
L
L
L
WRITE (Select bank and column and start WRITE burst)
7
L
H
L
L
H
BLOCK WRITE (Select bank & column and start BLOCK
WRITE access
7
L
L
H
L
L
PRECHARGE (Deactivate row in bank or banks)
8
L
L
L
L
H
LOAD SPECIAL MODE REGISTER
6
L
H
L
H
L
READ (Select bank and column and start new READ burst)
7
7
READ
L
H
L
L
L
WRITE (Select bank and column and start WRITE burst)
(AUTOPRECHARGE
L
H
L
L
H
BLOCK WRITE (Select bank & column and start BLOCK
WRITE access)
7
DISABLED)
L
L
H
L
L
PRECHARGE (Truncate READ burst, start precharge)
8
L
H
H
L
L
BURST TERMINATE
9
L
H
L
H
L
READ (Select bank and column and start READ burst)
7
WRITE
L
H
L
L
L
WRITE (Select bank and column and start new WRITE burst)
7
(AUTOPRECHARGE
L
H
L
L
H
BLOCK WRITE (Select bank & column and start BLOCK
WRITE access)
7
DISABLED)
L
L
H
L
L
PRECHARGE (Truncate WRITE burst, start precharge)
8
L
H
H
L
L
BURST TERMINATE
9
MT41 LC256K3204(S)
G01.pm5 - Rev. 2/95
3·26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC::RON
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NOTE:
MT41 LC256K32D4(S)
256K x 32 SGRAM
"'""'''"'"'
1. This table applies when CKE n_1 was HIGH and CKEn is HIGH (see Truth Table 2) and after IXSR has been
met (if the previous state was SELF REFRESH).
2. This table is bank specific, except where noted; Le., the CURRENT STATE is for a specific bank and the
commands shown are those allowed to be issued to that bank, when in that state. Exceptions are covered in
the notes below.
3. CURRENT STATE definitions:
Idle: the bank has been precharged and IRP has been met.
Row Active: a row in the bank has been activated and IRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read: a READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet
terminated or been terminated.
Write: a WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or
NOP commands, or allowable commands to the other bank should be issuedon any clock edge occuring
during these states. Allowable commands to the other bank are determined by it's CURRENT STATE; refer
to Truth Table 3 and these notes.
Precharging: Starts with registration of a PRECHARGE command and ends when IRPis met. Once
IRP is met, the bank will be in the Idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when IRCD is met. OnCe
tRCD is met, the bank will be in the Row Active state.
Read/Precharge: Starts with registration of a READ command with AUTO PRECHARGE enabled, and
ends when tRP has been met. Once tRP is met, the bank will be in the Idle state.
Write/Precharge: Starts with registration of a WRITE command with AUTO PRECHARGE enabled, and
ends when tRP has been met. Once tRP is met, the bank will be in the Idle state.
Block Write/
Precharge: Starts with registration of a BLOCK WRITE command with AUTO PRECHARGE
enabled, and ends when tRP has been met. Once IRP is met, the bank will be in the
Idle state.
Block Write: Starts with registration of a BLOCK WRITE command and ends when either IBPL or
tBWC has been met. tBPL applies when the BLOCK WRITE is to be followed by a
PRECHARGE and IBWC applies when it is to be followed by any other allowable
command. Once IBWC is met, the bank will be in the Row Active state.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when IRC is met.
Once tRC is met, the SGRAM will be in the "all banks idle" state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command, and ends when IMTC
has beeh met. Once IMTC is met, the SGRAM will be in the "all banks idle" state.
Accessing Special
Mode Register: Starts with registration of a LOAD SPECIAL MODE REGISTER command, and ends
when ISMLhas been met.
5. Requires that both banks are idle.
6. Requires that the other bank is either idle or in the Row Active state.
7. READ, WRITE and BLOCK WRITE accesses will interact between banks as they do within a bank.
8. If both banks are to be precharged, both must be in a valid state for precharging.
9. BURST TERMINATE is not bank specific; it affects the most recent READ or WRITE burst, regardless of
bank.
MT41 LC256K32D4(S)
G01.pm5 - Rev. 2195
3-27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
z
m
~
•
en
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:xJ
»
S
ADVANCE
MIC:RON
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z
m
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•
MT41 LC256K32D4(S)
256K x 32 SGRAM
",","co",,,
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability .
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vcc/VccQ supply relative to Vss. -IV to +4.6V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55°C to +150°C
Power Dissipation ............................................................. IW
Short Circuit Output Current ..................................... 50mA
~
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
WI
(Note: 1) (O°C
:D
l>
s::
0;
TAO; 70°C; VccNcco
=+3.3V ±0.3V)
SYMBOL
MIN
MAX
UNITS
VccNcco
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-0.5
0.8
V
II
-1
1
j.!A
loz
-2
2
j.!A
VOH
2.4
PARAMETER/CONDITION
Supply Voltage
INPUT LEAKAGE CURRENT
Any input OV 0; VIN 0; Vcc
(All other pins not under test = OV)
OUTPUT LEAKAGE CURRENT (DOs are disabled; OV
0;
VOUT
0;
3.6V)
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
VOL
NOTES
V
0.4
V
Icc SPECIFICATIONS AND CONDITIONS
(Note: 1) (O°C
0;
TAO; 70°C; VccNcco = +3.3V ±0.3V)
MAX
PARAMETER/CONDITION
SELF REFRESH CURRENT: CKE
0;
0.2V (S version only)
STANDBY CURRENT: POWER-DOWN mode,
CKE 0; VIL (MAX), both banks idle
SYMBOL
-10
-12
-15
Icct
(S only)
TBD
TBD
TBD
j.LA
Icc2
TBD
TBD
TBD
TBD
TBD
TBD
mA
j.LA
ICC2
UNITS NOTES
5
(S only)
STANDBY CURRENT: CS:2: VIH (MIN),
tCK :2: ICK (MIN), CKE :2: VIH (MIN), both banks idle
Icc3
TBD
TBD
TBD
mA
3,4,13
STANDBY CURRENT: CS:2: VIH (MIN),
ICK:2: ICK (MIN), CKE :2: VIH (MIN), both banks active after IRCD met
Icc4
TBD
TBD
TBD
mA
3,4,13
AUTO REFRESH CURRENT
(IRC = 16.6j.!S)
Iccs
TBD
TBD
TBD
mA
4
OPERATING CURRENT: ACTIVE mode,
burst =2, READ or WRITE, IRC :2: IRC (MIN), one bank active
Icc6
TBD
TBD
TBD
mA
3,4
OPERATING CURRENT: ACTIVE mode,
burst = 2, READ or WRITE, IRC :2: IRC (MIN), two banks active
Iccl
TBD
TBD
TBD
mA
3,4
Iccs
TBD
TBD
TBD
mA
3,4
OPERATING CURRENT: BURST mode,
full-page burst after IRCD met READ or WRITE,
ICK:2: tCK (MIN), other bank idle
MT41 LC256K32D4(S}
G01.pm5-Rev.2I95
3-28
Micron Technology, Inc., reserves the right to change products or speCifications without nolice.
©1995,MlcronTechnology,ln'c.
ADVANCE
MICRON
1-·
MT41 LC256K32D4(S)
256K x 32 SGRAM
m~",'oc""
CAPACITANCE
SYMBOL
MAX
UNITS
NOTES
Cli
5
pF
2
Input Capacitance: RAS, CAS, WE, DQM, ClK, CKE, CS, DSF
CI2
5
pF
2
Input/Output Capacitance: DQs
CIO
7
pF
2
PARAMETER
Input Capacitance: AO-AS, SA
z
m
=E
•
en
C)
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
:rJ
(Notes: 6, 8, 9, 10, 12) (O°C :::; T A:::; +70 C C) Listed alphabetically by symbol subscript.
AC CHARACTERISTICS
PARAMETER
-10
SYM
Access time from ClK (pos. edge)
Address hold time
Address setup time
BLOCK WRITE to PRECHARGE delay
BLOCK WRITE cycle time
CS, RAS, CAS, WE, DSF, DaM hold time
ClK high level width
System clock cycle time
CKE hold time
CKE setup time
ClK low level width
CS, RAS, CAS, WE, DSF, DaM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
Data-out low-impedance time
lAC
IAH
tAS
tBPl
tBWC
tCH
lOAD MODE REGISTER command to command
Data-out hold time
ACTIVE to PRECHARGE command period
AUTO REFRESH and ACTIVE to ACTIVE
command period
tMTC
ACTIVE to READ, WRITE or BLOCK WRITE delay
Refresh period (1,024 cycles)
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B Command period
lOAD SPECIAL MODE REGISTER
command to command
IRCD
tREF
tRP
Transition time
Write recovery time
Exit SELF REFRESH to ACTIVE command
MT41 LC256K32D4{S)
G01.pmS - Rev. 2196
tCHI
tCK
tCKH
tCKS
tCl
tcs
tDH
tDS
tHZ
tlZ
toH
tRAS
tRC
tRRD
ISMl
IT
MIN
-12
MAX
9
MIN
3
3.5
3
1
3
4
3
2
4
60
100
1.5
3.5
36
24
1.5
4
12
1.5
3.5
4
3.5
1.5
3.5
4
10
120K
3
2
4
72
100
17
1
15
tXSR
100
3-29
10
120K
30
1
15
100
MAX
13
5
15
2
4
5
4
2
4
4
3
2
4
90
110
10
120K
45
17
17
45
45
2
36
36
2
30
30
2
MIN
2
4
45
30
2
36
30
tWR
MAX
11
1
3
30
20
1
3.5
10
1
l>
-15
30
1
15
110
30
UNITS NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
11
ns
ns
ns
ns
ms
ns
ns
ICK
7
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
s:
ADVANCE
MIC:RON
1-·
z
m
=e
•
MT41 LC256K32D4(S)
256K X 32 SGRAM
>cc",moo,,",
NOTES
1. All voltages referenced to Vss.
2. This parameter is sampled. Vcc/VccQ = +3.3Vt0.3V;
f= 1MHz.
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle.time at which proper operation over the full
temperature range (O°C ~ TA ~ 70°C) is assured.
7. An initial pause of 100~s is reqUired after power-up,
followed by two AUTO REFRESH commands before
proper device operation is assured. The two AUTO
REFRESH command wake-ups should be repeated
any time the IREF refresh requirement is exceeded.
8. AC characteristics assume IT = Ins.
MT41 LC256K32D4(S)
G01.pm5 - Rev. 2/95
9. In addition to meeting the transition rate specification,
the clock and CKE must transit between VIH and VIL
(or between VIL and VlH) in a monotonic manner.
10. Outputs measured at 1.4V with equivalent load:
Q1 =500i
Zo
~50Q ±3~F
VT = 1.4V
11. 1HZ defines the time at which the output achieves the
open circuit condition; it is not a reference to VOH or
VOL.
12. AC timing tests have VIL = OV and VIH = 3.0V with
timing referenced to 1.4V crossover point.
13. All other inputs at CMOS levels.
3-30
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT41 LC256K32D4(S)
256K x 32 SGRAM
m"'"Wcnc
INITIALIZE AND LOAD MODE REGISTER
z
m
ClK
::E
•
COMMAND
en
C)
ADDRESS
DO
::D
High-Z
II
T=100~s I
l
l=-
II
tMTC
I
Power-up:
Vcc and
elK stable
l
Precharge
all banks.
l
l
AUTO REFRESH
(Bank 0)*
AUTO REFRESH
(Bank 1)'
l
I
Program mode register"
*Starts at Bank 0 and alternates banks.
**The mode register may be loaded prior to the AUTO REFRESH cycles if desired.
POWER-DOWN MODE
CLK
CKE
COMMAND
ADDRESS
DQ ____________-+__________________________~~----------~I(~--------~--_+--------~--------
gat~~
Precharge
active banks.
_t-R-p----------------------_I.lnput buffers
while in
) POWER-DOWN mode.
All banks idle, enter·
POWER-DOWN mode
Exit POWER-DOWN mode
NOTE: Violating refresh requirements during power-down
may result in a loss of data.
MT41lC256K32D4(S)
G01.pmS - Rev. 2195
3-31
JI
All banks idle
~
DONTCARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
Si:
ADVANCE
MICRON
z
m
AUTO REFRESH MODE
ClK
=E
•
en
G)
~~~fL---fL-I
I \\ I
(/)
I
I/\--)_ _ _ _--;-1_ _ _ __
CKE
COMMAND
:c
ADDRESS
s:
DQ
l>
MT41 LC256K32D4(S)
256K x 32 SGRAM
m~",coc""
1-·
'v-mnm~111777T7
~UL~ULULULUL~~ULULULUL~ULULUL~~
~---------7--4\__--~------4\__------~------~~;\--}-------II~-----IRC
.
IRC
AUTO REFRESH
SELF REFRESH MODE
lLLLLL.L.LL
S
NOTE: Forlhis example, the BURST LENGTH == 4, the READ LATENCY == 2 and the READ burst is followed bya "manual" PRECHARGE.
READ - WITH AUTO PRECHARGE
NOTE: For this example, the BURST LENGTH = 4, and the READ LATENCY;:: 2.
IZ] DON'T CARE
[!lllll UNDEFINED
MT41 LC256K32D4(S}
G01,pm5 - Rev. 2195
3-33
Micron Technology, Inc., reserves the right to change products or specifications WRhout notice.
©1995,MicronTechnology, Inc.
ADVANCE
READ - FULL-PAGE BURST
COMMAND
~J~1«2< 1
'lX
ACTIVE
NOP
i/)
~
READ
'j.(J')(
NOP
'j(j)(
Y//X
NOP
NOP
XlJX.
NOP
-YPJ/
-w
NOP
Xl;X.BURST TERM)o/.J:(
)0/){
NOP
-
NOP
ICH
ICS
DaM
lAS
AO-A7
(X
A8
IJ...
,,/AS
8A
IAH
COLUMNm
~,--------'
ROW
tAH
[(
ROW
d
[(
lAH
BANKO
BANKO
I
DO
~I
lui
~I I~
...'2'1
~
"
tOH~!!
~~I,
lAC
IOH~I,
~I
IO~I.
1HZ
256 locations within same row
Full page completed
tRCD (Bank 0)
IO~1
~.
DOOlm~,"lm'~","I;~DOOlmJlll0@'f mm,1
j
Full-page burst does not self-terminate.
Can use BURST TERMINATE command.
READ LATENCY
tRAS (Bank 0)
NOTE: For this example, BANK 0 is lJ.eing accessed and the READ LATENCY
~
~I
--
I
J
2.
READ - DQM OPERATION
NOTE: For this example, the BURST LENGTH = 2 and the READ LATENCY = 2.
MT41LC256K32D4(S)
G01.pm5-Rev.2f95
3-34
~
DON'TeARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technotogy, Inc.
ADVANCE
MICRON
1-·
MT41 LC256K32D4(S)
256K x 32 SGRAM
c"
WRITE .... WITHOUT AUTO PRECHARGE
z
m
:e
•
COMMAND
DOM
en
C)
rmmrm77T.m77m777n777ThI-J
::D
AG-A7
»
s:
SA
DO
--+-------(
NOTE: For this example, the BURST LENGl'H
= 4 and the WRIT~ burst is followed by a ''manual" PRECHARGE.
WRITE - WITH AUTO PRECHARGE
CLK
'CK
COMMAND
00 --+------~
NOTE: For this example, the BURST LENGTH = 4.
~DON'TCARE
~
MT41 LC256K32D4(S)
G01.pm5 - Rev. 2195
3-35
UNDEFINED
Micron Technology, l!'\(l., reserves the right to change products or specifications wiltloutnotice.
~1995, Micron Technology, Inc.
ADVANCE
MICRON
1-'
"
MT41 LC256K32D4(S)
256K x 32 SGRAM
,
WRITE - FULL-PAGE BURST
z
m
:e
III
en
C)
::J]
l>
s:
DO
-+--------(
256 locations within
same row
tWR
J
Full page completed
Full~page burst does not )
self·terminate.
tRCD (Bank 0)
tRAS (Bank 0)
I
Can use BURST TERMINATE)
command.
NOTE: For this example, BANK 0 Is being aooessed.
WRITE - DQM OPERATION
ClK
CKE
COMMAND
DQM
AO-A7
BA
DQ--~----~--~~~l
NOTE: For this example, the BURST lENG1H
MT41 LC256K32D4(S)
G01.pm5 - Rev. 2/95
=2.
@ DON'T CARE
I1l8il UNDEFINED
3-36
Micron Technology, inc., reserves the right to change products or specifications wlthoUl notice.
«:11995, Micron Technology,lnc.
ADVANCE
MU::I=ICN
1-·
MT41 LC256K32D4(S)
256K X 32 SGRAM
",
BLOCK WRITE
z
m
CLK
=e
•
CKE
COMMAND
en
C)
DaM
::D
l>
AO-A7
s:
AS
SA
DQ
MT411.,.C2S6K32D4(S)
G01.pm5· .... Rev. 2195
3-37
~
DON'T CARE
~
UNDEFINED
Micron Technology. Inc., reserves the right to cha.nge products or spe~tions without notice.
@1995, Mlci'on TechnolOgy', lnG,
ADVANCE
MU::RCN
1-·
,
CCc
MT41 LC256K32D4(S)
256K X 32 SGRAM
,
z
m
:e
II
en
C)
:::D
l>
3:
MT41I.C2561<3204(S)
G01.pm5 - Rev. 2/95
-
3-38
Micron Ted1nology, Inc., reserves the right to change products or specificationsWilhout notlc&.
©1995, Micl'tn Technology, Inc.
I'IIU:::RCN
DRAM SIMM,s ..................................................~.
DRAM
TECHN
PRODUCT
KAG
I FORMATION
MICRON
onun ....
DRAM SIMM PRODUCT SELECTION GUIDE
Memory
Conliguration
3.3VSIMMs
1 Megx32
1 Megx32
1 Meg x 32
1 Megx32
2Megx32
2Megx32
2Megx32
2Megx32
\.2Megx32
2Megx32
2Megx32
2Megx32
4Megx32
4Megx32
4Megx32
4 Meg x 32
SMegx32
SMegx32
SMegx32
SMegx32
Part
Number
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
MTSLD(T)132
MTSLD(T)132 S
MTSLD(T)132 X
MTSLD(T)132 XS
MT16LD(T)232
MT16LD(T)232 S
MT16LD(T)232 X
MT16LD(T)232 XS
MT4LD232
MT4LD232S
MT4LD232X
MT4LD232XS
MTSLD432
MTSLD432 S
MTSLD432X
MTSLD432. XS
MT16LDS32
MT16LD832S
MT16LD832X
MT16LDS32 XS
Optional
Access Cycle
S
EDO
EDO,S
S
EDO
EDO,S
S
EDO
EDO,S
S
EDO
EDO,S
S
EDO
EDO,S
Access
Time (ns)
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
60,
70,
70,
70,
70,
70,
70,
70,
70,
70
70
70
70
70
60,
60,
60,
60,
60,
60,
60,
70
70
70
70
70
70
70
SO
SO
SO
SO
SO
SO
SO
SO
I
Typical Power Dissipation
Standby
Active
9.6mW
2.4mW
SmW
2mW
19.2mW
4.SmW
16mW
4mW
4mW
1.2mW
4mW
1.2mW
SmW
2.4mW
SOOmW
SOOmW
920mW
920mW
S10mW.
S02mW
92SmW
922mW
SOOmW
SOOmW
600mW
600mW
l,440mW
I
No. of Pins
SIMM
72
72
72
72
72
72
72
72
72
SmW
3.2mW
16mW
4.SmW
16mW
6.4mW
1,440mW
l,200mW
l,200mW
1,40SmW
l,442mW
l,20SmW
l,203mW
72
72
72
72
72
72
72
72
72
72
72
6mW
6mW
24mW
9mW
27mW
6mW
12mW
24mW
24mW
48mW
4SmW
24mW
2.4mW
48mW
4.SmW
27mW
54mW
36mW
3.6mW
72mW
7.2mW
450mW
500mW
l,SOOmW
725mW
2,025mW
750mW
756mW
l,SOOmW
l,SOOmW
l,S24mW
l,S24mW
2,000mW
1,440mW
2,024mW
1,443mW
2,025mW
2,052mW
2,500mW
2,340mW
2,536mW
2,34SmW
30
30
30
30
30
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
72
Page
4-77
4-77
4-77
4-77
4-77
4-77 .
4-77
4-77
4-99
4-99
4-99
'4-99
4-133
4-133
4-133
4-133
4-133
4-133
4-133
4-133
4-1
4-11
4-21
4-31
4-41
4-51
4-51
4-63
4-63
4-63
4-63
4-119
4-119
4-119
4-119
4-155
4-155
4·167
4-167
4-167
4-167
5V,SIMMs
1 MegxS
4 Meg xS
4 Meg x8
4 Meg x 9
4 Meg x 9
256Kx32
512Kx32
1 Megx32
1 Megx32
2Megx32
2 Megx32
4 Megx32
4Megx32
SMegx32
SMegx32
1 Meg x 36
2 Meg x36
4Megx36
4Megx36
SMegx36
SMegx36
S
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
MT2D1S
MT2D48
MTSD4S
MT3D49
MT9D49
MT2D25632
MT4D51232
MTSD132
MTSD132S
MT16D232
MT16D232 S
MT8D432
MTSD432 S
MT16DS32
MT16DS32S
MT9D136
MT1SD236
MT12D436
MT12D436 S
MT24DS36
MT24DS36 S
=SELF REFRESH; EDO =Exlended Data-Out
S
S
S
S
S
S
60, 70
60, 70
.60,70
60, 70
60, 70
60, 70
60, 70
60, 70
60, 70
60, 70
60, 70
60, 70
60, 70
60, 70
60,70
60, 70
60, 70
60, 70
60, 70
60, 70
60, 70
UII:::F=lCN
MT2D18
1 MEG x 8 DRAM MODULE
m~'oco"",
1-·
DRAM
MODULE
1 MEG x8
1 MEGABYTE, 5V,
FAST PAGE MODE
FEATURES
• JEDEC- and industry-standard pinout in a 30-pin,
single-in-line memory module (SIMM)
• High-performance CMOS silicon-gate process
• Single 5V ±10% power supply
• Low power, 6mW standby; 450mW active, typical
• All device pins are TTL-compatible
• FAST PAGE MODE (FPM) access cycle
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
• Low profile
• 1,024-cycle refresh distributed across 16ms
OPTIONS
PIN ASSIGNMENT (Front View)
30-Pin SIMM
(DD-1 )
0
Vee 1
CAS 2
D01
3
AD 4
A1 S
D02 6
A2 7
A3 8
Vss 9
D03 10
A4 11
AS 12
D04 13
A6 14
A7 15
DOS 16
A8 17
A9 18
NC 19
D06 20
WE 21
Vss 22
D07 23
NC 24
D08 25
NC 26
RAS .27
NC 28
NC 29
Vee 30
MARKING
• Timing
60ns access
70ns access
-6
-7
• Packages
30-pin SIMM
M
• Part Number Example: MT2DI8M-6
KEY TIMING PARAMETERS
SPEED
-6
-7
tRe
110ns
130ns
tRAC
60ns
70ns
tpc
35ns
40ns
tM
30ns
35ns
tCAC
15ns
20ns
tRP
40ns
50ns
D
0
o
GENERAL PESCRIPTION
The MT2D18 is a randomly accessed solid-state memory
containing 1,048,576 words organized in a x8 configuration.
During READ or WRITE cycles, each word is uniquely
addressed through 20 address bits, which are entered 10
bits (AO-A9) at a time. RAS is used to latch the first 10 bits
and CAS the latter 10 bits . READ or WRITE cycles are
selected with the WE input. A logic HIGH on WE dictates
READ mode while a logic LOW on WE dictates WRITE
mode. During a WRITE cycle, data-in (D)islatchedby the
falling edge of WE or CAS, whichever occurs last. Early
WRITE occurs when WE goes LOW prior to CAS going
LOW, and the output pins remain open (High-Z) until the
next CAS cycle.
MT2D18
DM01.pm5 -·Rev. 2195
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined
(AO-A9) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed-in by CAS. CAS
may be toggled-in by holding RAS LOW and strobing-in
different column-addresses, thus executing faster memory
cycles.
4-1
Micron Technology. Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
C
:D
»
s:
en
-s:
s:
MIC:RON
1-·
c
"c
MT2D18
1 MEG x 8 DRAM MODULE
c
REFRESH
.Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RASHIGH time. Memory cell data is retained in its
correct state by maintaining power and executing any
RAS cycle (READ, WRITE) or RAS refresh cycle (RAS
ONLY, CBR or HIDDEN) so that all 1,024 combinations of
RAS addresses (AO-A9) are executed at least every 16ms
regardless of sequence.
FUNCTIONAL BLOCK DIAGRAM
•
C
JJ
»
s:
en
:s:
:s:
DQl·004
OQ5-0OB
Ul-U2 = MT4C4001JOJ
TRUTH TABLE
ADDRESSES
IR
IC
DATA-IN/OUT
DQ1-DQa
FUNCTION
1m"
-en
Standby
H
H-X
X
X
READ
L
L
H
ROW
EARLY WRITE
L
L
ROW
COL
Data-Out
' Data-In
H
H
L
L
X
ROW
n/a
ROW
n/a
ROW
COL
COL
COL
COL
n/a
Data-Out
Data-Out
Data-In
Data-In
High-Z
H
RPW,
ROW
X
COL
COL
X
Data-Out
Data-In
High-Z
FAST-PAGE-MODE
READ
FAST-PAGE-MODE
WRITE
RAS-DNLY REFRESH
1st CYC;le
2nd Cycle
1st Cycle·
2nd Cyole
HIDDEN
REFRESH
CBR REFRESH
READ
WRITE
MT2D18
OM01.pm5 - Rev. 2/95
L
L
L
L
L
L-H-L
L-H-L
H-L
L
, H-L
H-L
H-L
H-L
H
L
L
L
WE"
,L
H
4-2
X.
. COL
c.,
High-Z
Micron Technology, Inc., reserves the righllD change products orspeclflcalions wlthout nbtIce.
@1995,MiCronTechnology,lnc.
UII::::I=ICN
1-·
MT2D18
1 MEG x 8 DRAM MODULE
,"""'w,,'"
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability .
U
Voltage on Vee Supply Relative to Vss .............. -IV to +7V
Operating Temperature, TA (ambient) .......... DoC to +70°C
Storage Temperature ................................... -SsoC to +12SoC
Power Dissipation ............................................................. 2W
Short Circuit Output Current ..................................... SOmA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 6) (Vcc
=+5V ±1 0%)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vcc
4.5
5.5
V
Hig~
(Logic 1) Voltage, all inputs
VIH
2.4
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
Ii
-4
4
Il A
loz
-10
10
IlA
VOH
2.4
Input
INPUT LEAKAGE
Any input OV :0; VIN :0; 6.5V
(All other pins not under test
AO-A9, RAS, CAS, WE
=OV)
OUTPUT LEAKAGE
(Q is disabled; OV :0; VOUT :0; 5.5V)
DQ1-DQ8
OUTPUT LEVELS
Output High (Logic 1) Voltage (lOUT = -SmA)
Output Low (Logic 0) Voltage (lOUT = 4.2mA)
NOTES
0.4
V
:s:
MAX
-6
-7
UNITS
STANDBY CURRENT: (TTL)
(RAS = CAS = VI H)
Icct
4
4
mA
STANDBY CURRENT: (CMOS)
(RAS =CAS = Other Inputs = Vcc -0.2V)
Icc2
2
2
mA
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC =IRC [MIN])
ICC3
220
200
mA
2,26,
28
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC =IpC [MIN])
Icc4
160
140
rTiA
2,26,
28
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC =IRC [MIN])
Iccs
220
200
mA
26,28
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC
Icc6
220
200
mA
19,26
MT2D18
DMI}1.pm5:"': Rev. 2/95
=tRC [MIN])
4-3
»
S
-35:
SYMBOL
PARAMETER/CONDITION
C
JJ
en
V
VOL
•
NOTES
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, 'Inc.
MIC:F=lCN
1-·
" """,
MT2D18
1 MEG x 8 DRAM MODULE
K
CAPACITANCE
PARAMETER
MAX
UNITS
Input Capacitance: AO-A9
SYMBOL
CI1
13
pF
17
Input Capacitance: RAS, CAS, WE
CI2
CIO
17
pF
17
10
pF
17
InpuVOutput Capacitance: DQ1-DQ8
•
C
:xJ
»
s:
-ens:
s:
MIN
NOTES
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16) (Vee =+5V ±1 0%)
AC CHARACTER!ST!CS
PARAMETER
SYM
Access time from column-address
tAA
tAR
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
tASC
tASR
Access time from CAS
tCAC
Column-address hold time
tcAH
tCAS
CAS pulse width
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
tCHR
tCLZ
tcp
CAS precharge time
Access time from CAS precharge
Data-in hold time
.
Output buffer turn-off delay
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Row-address hold time
Column-address to RAS lead time
~ pulse width
~ pulse width (FAST PAGE MODE)
MT2D18
DM01.pm5 ~ Rev. 2/95
tDHR
tDS
tRAC
tRAD
tRAH
tRAL
tRAS
tRASP
4-4
15·
10
30
60
60
MAX
UNITS
35
ns
50
0
0
10,000
15
ns
15
20
10
0
10
20
s
ns
10,000
ns
40
10
70
10
20
15
55
0
3
40
10,000
100,000
15
10
35
]0
70
9
ns
ns
19
ns
18
ns
ns
ns
ns
19
ns
ns
15
ns
ns
20
ns
ns
n/a
nla
60
30
NOTES
ns
ns
35
n/a
tCSR
tCWL
tDH
RAS to column-address delay time
10
15
10
0
10
tpRWC
CAS setup time (CBR REFRESH)
Write command to CAS lead time
MIN
15
toFF
tpc
tCSH
Access time from RAS
45
0
0
10
60
10
15
10
45
0
3
35
tCRP
CAS hold time
MAX
30
tCPA
CAS toRAS precharge time
Data-in hold time (referenced to RAS)
Data-in setup time
-7
-6
MIN
,70
35
ns
ns
15
12,27
21
8
?2
ns
I
10;000
100,000
ns
ns
ns
Micron TechnolOgy, Inc., reserves the righllO change products OJ specifications withoUl; nqtlce.
©1995, Micron Tectlnology,lrI9_
MICRON
1-·
MT2D18
1 MEG x 8 DRAM MODULE
"'"""'"''
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vee = +5V ±1 0%)
SYM
MIN
Random READ or WRITE cycle time
tRC
110
RAS to "CAS" delay time
tRCD
20
Read command hold time (referenced to CAS)
tRCH
tRCS
0
Read command setup time
Refresh period (1,024 cycles)
RAS precharge time
-7
-6
AC CHARACTERISTICS
PARAMETER
MAX
40
MAX
130
45
20
50
0
16
16
UNITS
NOTES
ns
0
0
tREF
tRP
MIN
ns
13
ns
ns
24
III
ms
ns
ns
RAS to CAS precharge time
Read command hold time (referenced to RAS)
tRPC
0
50
0
tRRH
tRSH
0
15
0
20
ns
RAS hold time
READ WRITE cycle time
tRWC
nfa
nfa
nfa
Write command to RAS lead time
Transition time (rise or fall)
tRWL
15
ty
Write command hold time
tWCH
3
10
Write command hold time (referenced to RAS)
45
55
0
0
Write command pulse width
WE hold time (CBR REFRESH)
tWCR
twcs
twp
10
ns
23
WE setup time (CBR REFRESH)
twRP
10
10
15
10
ns
tWRH
10
ns
23
WE command setup time
MT2D18
DMQ1.pmS - Rev. 2/95
4-5
20
50
3
15
24
ns
21
ns
50
ns
ns
c
JJ
»
:s::
en
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
s:
s:
MICRON
1-·
MT2D18
1 MEG x 8 DRAM MODULE
,,,""coo,,",
NOTES
II
c
:D
»
s:
-CJ)s:
s:
14. IRCH is referenced to the first rising edge of RAS or
CAS.
15. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
16. In addition to meeting the transition rate specification, all input signals must transit between VlH and
VIL (or between VIL and VIH) in a monotonic manner.
17. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 301.2.1 (1 MHz AC,
Vee = 5V, DC bias = 2.4V at 15mV RMS).
18. If CAS is LOW at the falling edge uf RAS, data-out
(Q) will be maintained from the previous cycle. To
initiate a new cycle and clear the Q buffer, CAS must
be pulsed HIGH for ICP.
19. On-chip refresh and address counters are enabled.
20. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.
21. LATE WRITE, READ WRITE or READ-MODIFYWRITE cycles are not available due to OE being
grounded on UI and U2.
22. Operation within the IRAD (MAX) limit ensures that
IRAC (MIN) and ICAC (MIN) can be met. lRAD
(MAX) is specified as a reference point only; if IRAD
is greater than the specified lRAD (MAX) limit, then
access time is controlled exclusively by IAA.
23. IWTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of twRP and twRH in the
CBR REFRESH cycle.
24. Either IRCH or IRRH must be satisfied for a READ
cycle.
25. All other inputs at Vee -0.2V.
26. Ice is dependent on cycle rates.
27. The 3ns minimum is a parameter guaranteed by
design.
28. Column-address changed once each cycle.
1. All voltages referenced to Vss.
2. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
3. An initial pause of 100~s is required after power-up
followed by any eight RAS refresh cycles (RAS ONLY
or CBR with WE HIGH) before proper device
operation is assured. The eight RAS cycle wake-ups
should be repeated any time the IREF refresh
requirement is exceeded.
4. AC characteristics aSSUITLe tT = 5ns.
5. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VlH).
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C ::; TA ::; 70°C) is assured.
7. Measured with a load equivalent to two TTL gates
and 100pF.
8. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
9. Assumes that IRCD:2: IRCD (MAX).
10. If CAS = VIH, data output is High-Z.
11. If CAS = VIL, data output may contain data from the
last valid READ cycle.
12. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
13. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
MT2D18
DM01.pm5 - Rev, 2/95
4-6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
I'IIII=I=II;!,~
MT2D18
1 MEG x 8 DRAM MODULE
.
READ CYCLE
tRC
RAS
VIH -
VIL _
tCSH
leRP
V1H - CAS
VIL -
II
ROW
ADDR
WE
toFF
DQ
~:g~
------------OPEN
L
VALlO:-
OPEN - - -
EARLY WRITE CYCLE
tRC
leSH
ICRP
AODR
MT2D1"8
DM01.pm5 - Rev. 2195
~:t
•
ROW
ROW
4-7
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products:~;~;,c~~~~~n;e~~~~~;~t:~~:
c
JJ
»
s:
en
-s:
s:
MICRON
F"
MT2D18
1 MEG x 8 DRAM MODULE
,,,"",coo,,,,
FAST-PAGE-MODE READ CYCLE
------------------------------2tR~A~SP~-----------------------------I~
FAST-PAGE-MODE EARLY-WRITE CYCLE
tCSH
ADDR
WE
~:r
-:---c__~__-4LLLL=_____:_:_------=iLL'_f__----_C7_------1!LLLfLLLLLLLLLLLLLLLL..
-:LiLLiLLiLLUfLLLLLLLL.1l'---____
~I
VALID DATA
8Z] DON'T CARE
~
MT2D18
DM01,pm5-RiW.2/95
4-8
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT2D18
1 MEG x 8 DRAM MODULE
,,,"",coo,,,,
RAS-ONlY REFRESH CYCLE
(WE = DON'T CARE)
'RC
,_
CAS
.~~'_'RAs~r_b'RP.
:l,-----
~IH ~0--:1r------i+11·--------------C-----jt-------r------
_C---
IL
ADDR
~:~
DQ
~gt
-
tASR
•
•
RO-W
tRAH
----,·~$////$uj'$uMu$/M$u$"xr---RO-W- -
-'--------------OPEN-----------
•
C
:D
»
3:
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY -WRITE)
-3:
CJ)
3:
1-'
'PC
_'-,-,=RS",-H- - I
I_ _--~'C=SH~--_.I I_'_ _~~~_~_I
~
ADDR
•
tReD
leAS
~:t:=
COLUMN
-!.Lf..L.
V
VOL
PARAMETER/CONDITION
MT2D48
DM02.pm5 - Rev. 2/95
C
SYMBOL
PARAMETER/CONDITION
NOTES
Micron Techno!ogy, Inc., reservssthe right to change products or specificatlons without notic e
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT2D48
4 MEG x 8 DRAM MODULE
"'e,cc","'
CAPACITANCE
PARAMETER
•
C
:Ii
l>
S
en
S
S
MAX
UNITS
NOTES
Input Capacitance: AO-A 10
SYMBOL
CI1
MIN
13
pF
2
Input Capacitance: RAS, CAS, WE
CI2
17
pF
2
Input/Output Capacitance: OQ1-0Q8
CIO
10
pF
2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +5V ±1 0%)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
MIN
tAA
tAR
Row-address setup time
tASC
tASR
Access time from CAS
tCAC
Column-address hold time
tCAH
CAS pulse width
CAS hold time (CBR REFRESH)
tCAS
tCHR
CAS to output in Low-Z
50
0
0
10
15
15
3
10
CAS precharge time
tCPA
tCRP
CAS hold time
CAS setup time (CBR REFRESH)
tCSH
tCSR
Write command to CAS lead time
Data-in hold time
tCWL
tDH
Data-in hold time (referenced to RAS)
Data-in setup time
tDHR
tDS
Output buffer turn-off delay
FAST-PAGE-MODEREAD or WRITE cycle time
tOFF
tpc
5
60
5
15
10
45
0
3
35
tpRWC
n/a
tRAC
tRAD
Row-address hold time
tRAH
Column-address to RAS lead time
RAS pulse width
tRAL
tRAS
RAS pulse width (FAST PAGE MODE)
MT2D48
DM02.pm5 - Rev. 2195
tRASP
4-14
MIN
10,000
15
20
15
3
10
35
15
10
30
60
60
MAX
UNITS
35
ns
55
0
0
15
Access time from CAS precharge
CAS to RAS precharge time
Access time from RAS
RAS to column-address delay time
MAX
30
tCLZ
tcp
FAST-PAGE-MODE READ-WRITE cycle time
-7
-6
SYM
15
ns
ns
ns
20
ns
ns
10,000
ns
ns
ns
ns
40
5
70
5
20
15
55
0
3
40
10,000
100,000
15
10
35
70
70
15
5
25
16
ns
ns
ns
ns
ns
5
ns
21
ns
ns
20
n/a
60
30
NOTES
70
35
ns
ns
ns
ns
ns
21
20,25
22
14
18
ns
ns
10,000
100,000
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc
ADVANCE
MICRON
1-·
MT2D48
4 MEG x 8 DRAM MODULE
""e",,,n,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+5V ±1 0%)
AC CHARACTERISTICS
PARAMETER
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (2,048 cycles)
RAS precharge time
RAS to CAS precharge time
Read command hold time (referenced to RAS)
RAS hold time
READ WRITE cycle time
Write command to RAS lead time
Transition tillie (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT2D48
DM02.pm5 - Rev. 2/95
-7
-6
SYM
MIN
IRC
IRCD
IRCH
IRCS
IREF
IRP
IRPC
IRRH
IRSH
IRWC
IRWL
110
20
0
0
IT
IWCH
IWCR
IWCS
IWP
WRH
IWRP
4-15
MAX
MIN
45
130
20
45
0
10
10
10
50
0
0
32
32
40
0
0
15
n/a
15
3
10
MAX
50
0
0
20
n/a
20
50
3
15
55
0
15
10
10
50
UNITS
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
17
19
19
22
24
24
Micron Technology. Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
~CR~
1-·
"'~"OCO,,'"
~~
4 MEG x 8 DRAM MODULE
NOTES
•
C
lJ
»
s:
en
s:
s:
-
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICP.
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
18. Operation within the IRAD (MAX) limit ensures that
lRAC (MIN) and ICAC (MIN) can be met. IRAD
(MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, then
access time is controlled exclusively by tAA.
19. Either IRCH or tRRH must be satisfied for a READ
cycle.
20. toFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
22. OE is tied permanently LOW; LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and OE = HIGH.
24. tWTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of tWRP and tWRH in the
CBR REFRESH cycle.
25. The 3ns minimum is a parameter guaranteed by
design.
26. Column-address changed once each cycle.
1. All voltages referenced to Vss.
2. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 3012.1 (1 MHz AC,
Vcc = 5V, DC bias = 2.4Vat 15mV RMS).
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters .
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100jls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume IT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
MT2D48
DM02.pm5 - Rev. 2/95
4-16
Micron Technology. Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
,,~,
I-a
" '"
4 MEG
X
MT2D48
8 DRAM MODULE
READ CYCLE
V,H -~--------'[I
VIL _
teSH"
ADDR
DO
EARLY WRITE CYCLE'
~
DON'TeARE
!88a UNDEFINED
MT2D48
DM{)2.pm5 - Rev, 2f95
4-17
Micron Technology, Inc., reserves the righl to chan\19 products or specifications ~thout notice.
©1995, Micron Technology, Inc;
ADVANCE
I"IIC:F=lCN
4 MEG x 8 DRAM
M~T~8~~
FAST-PAGE-MODE READ CYCLE
----------------------------t~RA~S~P--------------------------~~
tcSH
~ 1~,---------tR"'C""D--_.1 ~.
•
C
:0
l>
s:
en
-s:
s:
WE
tcp
• ~ 1~'-tc""P--1
~:r $/;1//$/;1/,d'
I,
DO
~lg~ -=---------- OPEN
FAST-PAGE-MODE EARLY-WRITE CYCLE
MT2D4,
0M02.pm5 - Rev. 2/95
4-18
~
DON'T CARE
~
UNDEFINED
M1cron Technology, Inc., reserves the right to change products or specifications without notice.
©1995. Micron Technology,dnc.
ADVANCE
MIC:RON
; ~'H
I-I
MT2D48
4 MEG x 8 DRAM MODULE
,
RAS-ONLY REFRESH CYCLE
(WE DON'T CARE)
=
DO
~gr -~----------OPEN_----------
•
C
JJ
l>
s:
en
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
-
RAS
s:
VIH-
VIL _
'PC
'CSH
~:t
COLUMN
.
'RCS.
I
.
I
II 'CWL
II "RWL
II 'WP
,'WCS'II
'WCH ,
J7TT1'77'"TT7n7777TT7T7Tn
r""'LlW'l'$#$$ffJff#4:
SL:Jr
I
I
'cAS
COLUMN
'7'Tn'7TT77TTT7'"Tl-r.rnIr----:----!------+--.
.. :1:
I__'=RS,-,-H- - I
tCP
'CAS
ADDR
-s:
I .. I
, II~ :W,01#/$$//$$#/##/$,01#$/#/$$/#J "."~,,
~
'CAC
I'i1-.
OPEN
I.
NOTE:
I.
VALID
NOTE 1
G"~
'M
'RAC
:
OPEN-----
~
DON'T CARE
~
UNDEFINED
1. Do not drive data prior to tristate.
MT2D48
DM02.pm5 - Rev. 2/95
Micron Technology, Inc., reserves the right
to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
CBR REFRESH CYCLE
(Addresses = DON'T CARE)
tRP
tRAS
!
RAS
......--1
•
k
CAS
C
tAPe
.
. twRP
»
s:
WE
~:r
tcHA
L
II
DO
:c
tAP
I.
II
-:s:
tn
tAAS
• I
y
~~~ ~K
OPEN--;-;-II--_______
!wAH.
. !wAP
7)-I_~
$II!III!//IIf
..
II
!wAH
~II---'~
JII!///II!IIIIIIIIII!I@IIII!IIIIIIIII////III!I!/Ilt
HIDDEN REFRESH CYCLE 23
(WE = HIGH)
:s:
(REFRESH)
(READ)
__
~~---tRA-S_.,~-:----~:-~-R------·~Ir-----I
DO
~:g~ -'------:----OPEN---:---,--;~t====~V§AL~IO~DA~TA~==:}
~
OPEN-
DON'T CARE
1\88! UNDEFINED
MT2D4B
DM02.pm5 - Rev. 2!95
4-20
Micron Technology, Inc., reserves the right to change products or specifications without-notice.
@1995,MicronTechnology, Inc.
M~RCN
1-·
m~"ocoo'"C
Mrn~
4 MEG x 8 DRAM MODULE
DRAM
MODULE
4 MEG x8
4 MEGABYTE, 5V,
FAST PAGE MODE
FEATURES
• JEDEC- and industry-standard pinout in a 30-pin
single-in-line memory module (SIMM)
• High-performance CMOS silicon-gate process
• Single 5V ±10% power supply
• All device pins are TTL-compatible
• Low power, 24mW standby; I,SOOmW active, typical
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
• 1,024-cycle refresh distributed across 16ms
• FAST PAGE MODE (FPM) access cycle
OPTIONS
PIN ASSIGNMENT (Front View)
30-Pin SIMM
(00-3)
~
MARKING
• Timing
60ns access
70ns access
-6
-7
• Packages
30-pinSIMM
-6
-7
S
9
10
11
12
13
14
15
16
17
lS
'RAC
60ns
70ns
tpc
35ns
40ns
'AA
30ns
35ns
*A10
19
DOS
20
21
22
23
24
25
26
27
28
29
30
Vss
D07
NC
D06
~
'CAC
15ns
20ns
RAS
NC
NC
Vee
tRP
40ns
50ns
~o
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ· or WRITE) within a row:address-defined
4-21
»
en
s:
s:
~o
0
~D
p
• Address no' used for RAS-ONL Y REFRESH
The MTSD4S is a randomly accessed solid-state memory
containing 4,194,304 words organized in a xS configuration.
During READ or WRITE cycles, each.bit is uniquely addressed through the 22 address bits which are entered 11
bits(AO -AI0) at a time. RAS is used to latch the first 11 bits
and CAS the latter 11 bits. A READ or WRITE cycle is
selected with the WE input. A logic HIGH on WE dictates
READ mode, while a logic LOW on WE dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
falling edge of WE or CAS, whichever occurs last. If WE
goes LOW prior to CAS going LOW, the output pin(s)
remain open (High-Z) until the next CAS cyde. EARLY
WRITE occurs when WE goes LOW prior to CAS going .
LOW, and theouput remains open(High-Z) until the next
CAS cycle.
C
::D
i:
Do
0
GENERAL DESCRIPTION
MT8D48
DM03,pm5 - Rev. 2/95
A3
Vss
D03
A4
A5
OQ4
A6
A7
D05
AS
WE
KEY TIMING PARAMETERS
'RC
110ns
130ns
1
2
3
4
5
6
7
A9
M
• Part Number Example: MTSD48M-6
SPEED
Vee
CAS
DOl
AO
Al
D02
A2
•
(AO-AID) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed-in by CAS, CAS
may be toggled-in by holding RAS LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning RAS HIGH terminates the FAST PAGE
MODE operation.
REFRESH
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
theRAS HIGH time. Memory cell data is retained in its
correct state by maintaining power and .executing any
RAS cycle (READ, WRITE) or RAS refresh cycle (RAS
ONLY, CBR or HIDDEN) so that all 1,024 combinations of
RAS addresses (AO-A9) are executed at least every16ms
regardless of sequence.
Micron Technology, Inc., reserves the right to change products or specifications without' notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT8D48
4 MEG x 8 DRAM MODULE
",,,",co",,,,
FUNCTIONAL BLOCK DIAGRAM
•
D01
DOS
D02
D06
D03
D07
C
:c
»
S
en
s:
S
D04
----ri
DOB - - - - - - , - I
Vee _ _ _ _~t=~~
Vss
------~
_____~=t~~
_ _ _ _ _ _ _ _____'
U1-U8 = MT4C1 004JDJ
TRUTH TABLE
ADDRESSES
IR
IC
DATA-IN/OUT
DQ1-DQa
liAS
CAS
WE
Standby
H
H-X
X
X
X
High-Z
READ
L
L
H
ROW
COL
Data-Out
FUNCTION
EARLY WRITE
L
L
L
ROW
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H-L
H
ROW
COL
Data-Out
READ
2nd Cycle
L
H-L
H
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H-L
L
ROW
COL
Data-In
WRITE
2nd Cycle
L
H-L
L
n/a
COL
Data-In
L
H
X
ROW
n/a
High-Z
H
ROW
COL
Data-Out
RAS-ONLY REFRESH
HIDDEN
READ
L'-+H-L
L
REFRESH
WRITE
L-H-L
L
L
ROW
COL
Data-In
H-L
L
H
X
X
High-Z
CBR REFRESH
MT8048
DM03.pm5 - Rev. 2195
4-22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC::RON
1-·
MT8D48
4 MEG x 8 DRAM MODULE
,""""'''''
'Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability .
ABSOLUTE MAXIMUM RATINGS*
U
Voltage on Vee Supply Relative to Vss .............. -IV to +7V
Operating Temperature, TA (ambient) .......... DoC to +70°C
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ............................................................. 8W
Short Circuit Output Current ..................................... 50mA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc
=+5V ±1 0%)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vcc
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
II
-16
16
!lA
loz
-10
10
!lA
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV::; VIN ::; 6.5V
(All other pins not under test =OV)
OUTPUT LEAKAGE CURRENT
(0 is disabled; OV ::; VOUT ::; 5.5V)
AO-A 10, WE, CAS, RAS
D01-D08
OUTPUT LEVELS
Output High Voltage (lOUT =-5mA)
Output Low Voltage (lOUT =4.2mA)
NOTES
0.4
en
S
S
V
MAX
SYMBOL
-6
·7
mA
UNITS NOTES
STANDBY CURRENT: (TTL)
(RAS = CAS = VI H)
Icc1
16
16
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
Icc2
8
8
mA
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIN])
Icc3
880
800
mA
3,4,
26
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: tpc = tpc [MIN])
ICC4
640
560
mA
3,4,
26
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: tRC = tRC [MIN])
Iccs
880
800
mA
3,26
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIN])
Icce
880
800
mA
3,5
4-23
::D
l>
S
V
VOL
PARAMETER/CONDITION
MT8D48
DM03.pm5 - Rev. 2/95
•
C
PARAMETER/CONDITION
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MlI::::r=lCN
1-'
MT8D48
4 MEG x 8 DRAM MODULE
'c~"
CAPACITANCE
SYMBOL
MAX
UNITS
NOTES
Input Capacitance: AO-A10
CI1
51
pF
2
Input Capacitance: RAS, WE, CAS
CI2
pF
2
InpuVOutput Capacitance: OQ1-0Q8
CIO
67
15
pF
2
DESCRIPTION
•
C
:D
»
==
en
-==
s:
ELECTRICAL CHARACTERISTICS AND RECOMMENDED ACOPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee =+5V ±10"lo)
AC CHARACTERISTiCS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
CAS precharge time
Access time from CAS" precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output buffer turn-off delay
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS_
RAS to column-address delay time
c.
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
MT8D48
DM03.pm5- Rev. 2/95
-7
-6
SYM
MIN
tAA
45
0
tcLZ
tcp
a
a
a
15
10
15
10
10,000
20
15
20
10
10,000
a
10
10
40
35
10
60
10
15
10
45
10
70
10
20
15
55
a
a
toFF
tpc
3
35
tpRWC
tRAC
tRAD
tRAH
tRAL
tRAS
tRASP
n/a
4-24
MAX
35
50
0
tCPA
tDHR
tDS
MIN
30
tAR
IASC
tASR
tCAC
tCAH
tCAS
tCHR
tcRP
tcSH
tcSR
tCWL
tDH
MAX
15
10
30
60
60
15
10,000
100,000
15
10
35
70:
70
Micron Technology, Inc., reserves the
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns'
ns
ns
ns
ns
. ns
ns
3
40
20
n/a
60
30
UNITS
ns.
ns
n/a
70
35
10,000
100,000.
ri~t
ns
mo-
NOTES
15
5
16
5
21
21
20,25
23
14
18
ns
ns
ns
ns
to change products or specifications without notice,
©1995, Micr:on- Technology, Inc.
MICRON
1-·
MT8D48
4 MEG x 8 DRAM MODULE
"'"'"oco"'""
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +5V ±1 0%)
AC CHARACTERISTICS
PARAMETER
-7
-6
SYM
MIN
tRC
Random READ or WRITE cycle time
RAS to CAS delay time
tRCD
110
20
Read command hold time (referenced to CAS)
tRCH
0
Read command setup time
tRCS
0
Refresh period (1,024 cycles)
MAX
MIN
45
130
20
tREF
tRP
40
50
tRPC
tRRH
0
0
RAS hold time
tRSH
15
0
0
20
READ WRITE cycle time
tRWC
Write command to RAS lead time
tRWL
tT
n/a
15
16
3
15
45
55
0
Write command pulse width
twcs
twp
0
15
WE hold time (CBR REFRESH)
tWRH
WE setup time (CBR REFRESH)
twRP
MTBD48
DM03.pm5 - Rev. 2195
4-25
17
ns
19
ns
50
ms
ns
ns
ns
19
ns
n/a
20
twCR
10
10
50
n/a
tWCH
10
NOTES
ns
ns
16
3
10
Write command hold time (referenced to RAS)
WE command setup time
UNITS
0
0
RAS precharge time
RAS to CAS precharge time
Read command hold time (referenced to RAS)
Transition time (rise or fall)
Write command hold time
MAX
23
ns
50
ns
ns
ns
ns
ns
10
ns
24
10
ns
24
Micron Technology, Inc., reselVes the right to change products or specH'ications without notice.
©1995, Micron Technology, Inc.
•
C
::D
l>
:s:
en
:s:
:s:
UIC:RCN
1-·
","",C"",,"'
MT8D48
4 MEG x 8 DRAM MODULE
•
NOTES
•
C
::D
»
:s:
-en:s:
:s:
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
18. Operation within the lRAD (MAX) limit ensures that
tRAC (MIN) and tCAC (MIN) can be met. IRAD
(MAX) is specified as a reference point only; if tRAD
is greater than the specified IRAD (MAX) limit, then
access time is controlled exclusively by IAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
22. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.
23. LATE WRITE, READ WRITE or READ-MODIFYWRITE cycles are not available due to the common
DQ configuration of UI-U8.
24. twTS and twTH are set up and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CER timing constraints). These two
parameters are the inverts of twRP and IWRH in the
CER REFRESH cycle.
25. The 3ns minimum is a parameter guaranteed by
design.
26. Column--address changed once each cycle.
1. All voltages referenced to Vss.
2. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 3012.1 (1 MHz AC,
Vee = 5V, DC bias = 2.4V at 15mV RMS).
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5 . Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C S TA S 70°C) is assured.
7. An initial pause of IOOfls is required after power-up
foHowed by any eight RAS refresh cycles (RAS ONLY
or CER with WE HIGH) before proper device
operation is assured. The eight RAS cycle wake-ups
should be repeated any time the IREF refresh
requirement is exceeded.
8. AC characteristics assume IT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load eqUivalent to two TTL gates
and lOOpF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
MT8D48
DM03.pm5- Rev. 2/95
4-26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MT8D48
4 MEG x 8 DRAM MODULE
I"IIC:I=II;~N
READ CYCLE
tAC
AAS
tCSH
•
C
ADDR
::D
l>
DQ
~:gt ----------OPEN---------1Q<'&')'L~~:".:.':_'D---- OPEN---~
EARLY WRITE CYCLE
MT8D48
DM03.pm5 - Rev. 2/95
CAS
~lr
ADDR
~l~
AOW
ROW
4-27
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products~;:~;.c~~c~~~n~e~~~~~;~t:::
s:
en
-s:
s:
MICRON
1-·
MT8D48
4 MEG x 8 DRAM MODULE
'"<,"e,,,,"
FAST-PAGE-MODE READ CYCLE
tRASP
IRP
____~I----------------------~~------------------------'I
---~
RAS
V'H
V'L
--
tCSH
~
CAS
•
ADDR
C
:r:J
V'H
VIL
--
~:t1
l>
S
WE
11--'----7-'-""'--
~:t =1$$$1)/;/;;)
I.
en
-
DQ ~[g~ =:------OPEN------OOOOOi
S
S
OPEN--
FAST-PAGE-MODE EARLY-WRITE CYCLE
. t=:=j
tRP
RAS
RAS
V'H
V'L
tpc
ICSH
(~
CAS
V'H
VIL
=~
tAR
14 tASA
V'H
VIL
~
tRAH
ROW
tcp
'CAS
II
IRAD
ADDR
tcp
teAS
"'1
WI/){
~
COLUMN
I~I
~---+--c-"l
teAS
~ 1~~I~~lkll~1
COLUMN
'-4.0-
II
COLUMN
I
~l
WE
VtH
ViL
DO
VrOH
VIOL
VALID DATA
~
DON'T CARE
IQ2lJ UNDEFINED
MT8D48
DM03.pm5 - Rev. 2/95
4-28
Micron Technology, Jne., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, Inc.
RAS-ONlY REFRESH CYCLE
(ADDR = AO-A9; A10 and WE = DON'T CARE)
~~
CAS
~IH
_
DO
.
--'---------+--r------
~ir _
~g~
tRC_'~~btRP :l~___
____
tRAS
____
·,-d---1----7+II-,--:-.
IL -
ADDR
~ .~,-'
tASR
•
f
I
tRAH
ROW
-
bt'$$t'!$j'$/t'$/j'$$/$/J?(r---Ro-w - OPEN----------
•
C
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l>
s:
en
s:
s:
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
VIH
RAS
V1L -
Q
NOTE:
_:-------..1
_
r---------------:-tRS-H--'I
,
teSH
tpc 1--"""''-----1
teAS
~~,-._=tRc~D_~_~~~I_~te~P~
~8t'-=---+I,-OPEN-+I-tAA-C-tAA--&~n----OPEN
~
DON'T CARE
~
UNDEFINED
1. Do not drive data prior to tristate.
MTBD48
DMOS.pm5 - Rev. 2/95
Micron Technology, Inc., f&8EIrves the right to change products or speclf\catlons without notice.
@1995,MictonTechnology,lnc.
UII:::I=ICN
1-·
4 MEG
"we'
X
MT8D48
8 DRAM MODULE
, CBR REFRESH CYCLE
(Addresses DON'T CARE)
=
tRP
:Jy.
----./
•
C
CAS
s:
en
-s:
s:
tRAS
.
tCHR
1
~,tcSR
1
II
, tWRP
II
.
,
tRP
.1 •
tRPC
DO
::D
l>
.
~CHR
,
tRAS
.1
·k
OPEN-.-;-:II--------tWRH
tWRP
II
tWRH
~:~ J/!///!/////lJ---' --'W$/$#//#I$/;;)- --'WighW//#/$!IIIJ#//////~
WE
HIDDEN REFRESH CYCLE 22
(WE HIGH)
=
(READ)
tRAS
RAS
CAS
~:r-~+--____++___:-t-Rc-D--_,~f'
~:r::
'A'
'RP
tRS<
(REFRESH)
tRAS
::=======tcH;:::R=======___:r_ __
1J.
1-:---='--1-::--*--:'=-+-1
ADDR
DO
~:gr -------OPEN-----~@sr---~WVI>J.,;U;ID;CD;;;ATrAA---_j
MT8048
0M03.pm5-Rew2/95
OPEN-
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves tile righlro change products Of specifications without notice.
©1995, Micron TechflOlogy, Inc.
ADVANCE
MICRON
1-·
"'""''""'''''
4 MEG
' MT3D49
x 9 DRAM MODULE
4 MEG x9
DRAM
MODULE
4 MEGABYTE, 5V,
FAST PAGE MODE
FEATURES
• JEDEC- and industry-standard pinout in a 30-pin,
single-in-line memory module (SIMM)
• High-performance CMOS silicon-gate process
• Single 5V ±10% power supply
• Low power, 9mW standby; 725mW active, typical
• All device pins are TTL-compatible
• FAST PAGE MODE (FPM) access cycle
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
• 2,048-cycle refresh distributed across 32ms
• Low profile
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
-7
• Packages
30-pinSIMM
M
PIN ASSIGNMENT (Front View)
30-Pin SIMM
(00-2)
A2
A3
Vss
D03
A4
A5
D04
A6
A7
D05
A8
A9
NC
D06
WE
Vss
DQ7
NC
D08
09
RAS
CAS9
D9
Vee
• Part Number Example: MT3D49M-6
KEY TIMING PARAMETERS
SPEED
-6
-7
tRe
110ns
130ns
tRAC
60ns
70ns
tpc
35ns
40ns
tAA
30ns
35ns
tCAC
15ns
20ns
tRP
40ns
50ns
D
D
D
en
-
S
s:
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed-in by CAS. CAS
may be toggled-in by holding RAS LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning RAS HIGH terminates the FAST PAGE
MODE operations.
The MT3D49 is a randomly accessed solid -state memory
containing 4,194,304 words organized in a x9 configuration.
During READ or WRITE cycles, each word is uniquely
addressed through 22 address bits, which are entered 11
bits (AO-AlO) at a time. RAS is used to latch the first 11 bits
and CAS the latter 11 bits. READ or WRITE cycles are
selected with the WE input. A logic HIGH on WE dictates
READ mode while a logic LOW on WE dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
falling edge of CAS. Since WE goes LOW prior to CAS
going LOW, the output pins remain open (High-Z) until
the next CAS cycle.
REFRESH
Returning RASand CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS HIGH time. Memory cell data is retained in its
correct state by maintaining power and executing any
RAS cycle (READ, WRITE) or RAS refresh cycle (RAS
ONLY, CBR or HIDDEN) so that all 2,048 combinations of
RAS addresses (AO-Al0) are executed at least every 32ms,
regardless of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic RAS addressing.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within arow-address-defined (AOAl0) page boundary. The FAST PAGE MODE cycle is
OMOS.pm5 - Rev. 2195
»
s
0
GENERAL DESCRIPTION
MT3D49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
4-31
Micron Technology, Inc., reserves the right
•
c
::c
0
Vee
CAS
DOl
AO
Al
D02
to change products or specifications without notice.
©1995, Micron Technology, Inc,
ADVANCE
UIC:I=ICN
1-·
4 MEG
","",coon,
X
MT3D49
9 DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
RAS --~-----,
CAS - - - - - - - ,
WE - - - - - - - - - ,
D01-D04
•
C
:II
»
s:
en
s:
s:
AD-A1D
DOS-DOS
CAS9 ------++---~
D9 ------+---~
Vee
Vss
------+-------'
--------4--------'
U1-U2 = MT4C4M4B1DJ
U3 = MT4C1004JDJ
TRUTH TABLE
,
WE"
ADDRESSES
IR
IC
DATA-IN/OUT
FUNCTION
"\lAS"
'CAS"
"CAS9
Standby
H
H~X
H~X
X
X
X
High-Z
READ
L
L
L
H
ROW
COL
Data-Out
001-008,09,09 .
L
L
L
L
ROW
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H~L
H~L
H
ROW
COL
Data-Out
Data-Out
EARLY WRITE
READ
2nd Cycle
L
H~L
H~L
H
n/a
COL
FAST-PAGE-MODE
1st Cycle
L
H~L
H~L
L
ROW
COL
Data-In
WRITE
2nd Cycle
L
H~L
H~L
L
n/a
COL
Data-In
RAS-ONLY REFRESH
L
H
H
X
ROW
n/a
High-Z
HIDDEN
READ
L~H~L
L
L
H
ROW
COL
Data-Out
REFRESH
WRITE
L~H~L
L
L
L
ROW
COL
Data-In
H~L
L
L
H
X
X
High-Z
CBR REFRESH
MT3D49
DMOS.pmS - Rev. 2/95
4-32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII:::I=ICN
1-·
4 MEG
",""we,",
X
MT3D49
9 DRAM MODULE
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee Supply Relative to Vss .............. -lV to +7V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature ................................... -SsoC to +12SoC
Power Dissipation ............................................................. 3W
Short Circuit Output Current ..................................... SOmA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc
=+5V ±1 0%)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
,UNITS
Supply Voltage
Vcc
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
Vcc+1
V
VIL
-1.0
0.8
V
Ii
-2
2
flA
f.lA
f.lA
Input Low (Logic 0) Voltage, all inputs
INPUT LEAKAGE
Any input OV :s: VIN :s: 5.5V
(All other pins not under test
OUTPUT LEAKAGE
(0 is disabled; OV :s: VOUT
09, CAS9
=OV)
AO-A 10, RAS, WE
001-008,09
Ii
-6
6
loz
-10
10
VOH
2.4
:s: 5.5V)
OUTPUT LEVELS
Output High (Logic 1) Voltage (lOUT =' -5mA)
Output Low (Logic 0) Voltage (lOUT =4.2mA)
V
MAX
-6
-7
UNITS
STANDBY CURRENT: (TTL)
(RAS =CAS = VIH)
Icc1
6
6
mA
STANDBY CURRENT: (CMOS)
Average power supply current
(RAS =CAS = 'Other Inputs =Vcc -0.2V)
Icc2
3
3
mA
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS and CAS =Cycling; IRC =IRC [MIN])
ICC3
350
320
mA
3,4,
26
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS =VIL; CAS = Cycling; tpc =IpC [MIN])
Icc4
260
230
mA
3,4,
26
REFRESH CURRENT: RAS ONLY
(RAS = Cycling; CAS =VIH; IRC =IRC [MIN])
Icc5
350
320
mA
3,26
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling =IRC
Icc6
350
320
mA
3,5
MT3D49
OM05.pm5 - Rev. 2/95
NOTES
=IRC [MIN])
4-33
»
s
3:
SYMBOL
PARAMETER/CONDITION
c
::c
-en3:
V
0.4
VOL
NOTES
II
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©199S, Micron Technology. Inc.
ADVANCE
MICRON
1-·
MT3D49
4 MEG x 9 DRAM MODULE
,"""'''"''"'
CAPACITANCE
PARAMETER
MAX
UNITS
Input Capacitance: AO-A10
SYMBOL
CI1
MIN
19
pF
2
Input Capacitance: RAS, CAS, WE
CI2
25
pF
2
Input/Output Capacitance: DQ1-DQ8
CIO
10
pF
2
Input Capacitance: DQ9
CI3
10
pF
2
Output Capacitance: Q9
Co
10
pF
2
NOTES
II
c::c ELECTR!CAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
l>
s:
en
s:
s:
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
= +5V ±1 0%)
-6
AC CHARACTERISTICS
PARAMETER
SYM
Access time from column-address
tAA
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Access time from CAS"
Column-address hold time
tAR
tASC
tASR
tCAC
tCAH
CAS pulse width
tCAS
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
tCHR
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
tCLZ
tcp
MIN
50
0
0
10
15
15
3
10
tCPA
CAS setup time (CBR REFRESH)
tCSR
Write command to CAS lead time
Data-in hold time
tCWL
tDH
Data-in hold time (referenced to RAS)
Data-in setup time
tDHR
tDS
Output buffer turn-off delay
tOFF
tpc
5
60
5
15
10
45
0
3
35
tpRWC
n/a
RAS to column-address delay time
Row-address hold time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
Column-address to RAS lead time
MT3D49
DMQ5.pm5 - Rev. 2/95
tRAC
tRAD
tRAH
tRAS
tRASP
tRAL
4-34
15
10
60
60
30
MAX
35
55
0
0
10,000
15
20
15
3
10
15
10,000
10,000
100,000
15
10
70
70
35
ns
ns
15
ns
ns
ns
ns
ns
ns
5
25
16
ns
ns
5
ns
20
ns
ns
21
ns
ns
21
20,25
ns
n/a
60
30
NOTES
ns
ns
40
5
70
5
20
15
55
0
3
40
UNITS
ns
ns
20
35
tCRP
tCSH
FAST-PAGE-MODE READ or WRITE cycle time
MIN
15
CAS hold time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RA.S"
-7
MAX
30
ns
70
35
ns
ns
10,000
100,000
ns
ns
22
14
18
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT3D49
4 MEG x 9 DRAM MODULE
no,""co", ,,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+5V ±1 0%)
-6
AC. CHARACTERISTICS
PARAMETER
Random READ or WRITE cycle time
RAS to
SYM
tRC
MIN
MIN
45
130
20
110
. tRCD
20
Read command setup time
Read command hold time (referenced to CAS)
tRCS
0
tRCH
0
Refresh period (2,048 cycles)
tREF
tRP
CAS delay time
-7
MAX
MAX
UNITS
NOTES
50
ns
ns
17
ns
0
0
32
..
ns
32
19
ms
40
50
ns
0
0
15
READ WRITE cycle time
tRWC
n/a
20
n/a
ns
ns
ns
19
RAS hold time
tRRH
tRSH
0
0
ns
22
Write command to RAS lead time
tRWL
15
20
IT
RAS precharge time
RAS to CAS precharge time
Read command hold time (referenced to RAS)
tRPC
Transition time (rise or fa\l)
Write command hold time
tWCH
3
10
Write command hold time (referenced to RAS)
tWCR
45
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
twcs
.twp
0
10
tWRH
10
WE setup time (CBR REFRESH)
tWRP
10
10
MT3D49
DMOS.pm5 - Rev. 2/95
4-35
50
3
15
ns
ns
55
0
ns
15
ns
10
ns
ns
c
::c
l>
s:
ns
50
•
-enS
ns
24
24
Micron Technology, Inc., reserves the right to change products or specifications without-notice.
©1995, Micron Technology, Inc.
s:
ADVANCE
MICRON
1-·
",e',w""
MT3D49
4 MEG x 9 DRAM MODULE
NOTES
•
C
:D
l>
3:
en
3:
3:
1. All voltages referenced to Vss.
2. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 3012.1 (1 MHz AC,
Vee = SV, DC bias = 2.4V at 15mV RMS).
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters .
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOlls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
8. AC characteristics assume tT = Sns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input Signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that tRCD < tRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
MT3D49
DM05.pmS - Rev. 2/95
15. Assumes that IRCD:2: IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
18. Operation within the IRAD (MAX) limit ensures that
IRAC (MIN) and ICAC (MIN) can be met. IRAD
(MAX) is specified as a reference point only; if Ir,V,D
is greater than the specified IRAD (MAX) limit, then
access time is controlled exclusively by IAA.
19. Either tRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
22. OE is tied permanently LOW; LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
23. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and OE = HIGH.
24. twTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of twRP and IWRH in the
CBR REFRESH cycle.
25. The 3ns minimum is a parameter guaranteed by
design.
26. Column-address changed once each cycle.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology,lnc.
ADVANCE
MT3D49
4 MEG x 9 DRAM MODULE
I"IIC:Rgc~
READ CYCLE
tRC
tRAS
tRP
VIH -
Vil _
RAS
tCSH
tRAH
leRP
,I
tRCD
JIH-J
CAS
VIL -
II
tAR
ROW
ADDR
»
s:
WE
I
DO
VIOH -
tRAC
en
OPEN-----
OPEN
VIOL
EARLY WRITE CYCLE
RAS
V1H -
VIL _
teRP
CAS
VIH-J
V1L -
tRAD
ADDR
V,V,HL
ROW
r:z::J
DON'TeARE
!8&l UNDEFINED
MT3D49
DMOS.pm5 - Rev. 2/95
4-37
C
:rJ
s:
s:
ADVANCE
MICRON
1-·
MT3D49
4 MEG x 9 DRAM MODULE
;,'""'c'"""
FAST-PAGE-MODE READ CYCLE
------------------------------~IR~A~SP~-------------------------------I~
III
ADDR
C
:c
l>
WE
VIH VIL _
h
I I'
~:~ !ilIl/l/l///!/!1lJ
en
s:
DQ
VIOH VIOL -
ILIRCS
I
1
IRCH- h-
lAA
tRAG
I.
1
-I
ILIRCS
I
'WJI
t@)'
I.
S
I-I
lAA
tCPA
I~.-+1/-=------1
OPEN---
OPEN
S
FAST-PAGE-MODE EARLY-WRITE CYCLE
I-----------------------------I~RA~S~----------------------------~·I~
tpc
tCSH
tRSH
===',ICR_P-7~---------I-RC-D,,:'_+--I-CA-S--~I~--IC-P----i~-IC-AS-~~_lc_p_~~_tc_A_S__-+~~+-----~
ROW
DO
~:gt
VALID DATA
VALID DATA
VALID DATA
f:Z2 DON'T CARE
~
MT3D49
DMOS.pm5 - Rev. 2/95
4·38
UNDEFINED
Micron Technology, Inc., reserves the right to change products orspecificatiorts without notice:
©1995, Micron Technology, Inc.
ADVANCE
MU:::I=ICN
1-·
MT3D49
4 MEG x 9 DRAM MODULE
"'"oow"""
RAS-ONlY REFRESH CYCLE
(WE = DON'T CARE)
::::d '"' ~II-'
_'RAS
--L~ l~
•
'ASR . . 'RAH
ADDR
DO
~:~ =~~--RO-W--'kwd1$/#$#$#U/$////////#$#;)<~--RO-W- ~g~
-
C
JJ
OPEN----------
l>
3:
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODI FY-WRITE)
en
-3:
3:
tpc
tCSH
~
!_.---"'R=sH'---_1
I_._ _'=RC,,-D_ _I
'RCS
.1
~II~
I
I I
/TTTTTTTTT7TT7777777777
~:~::
I ...
~II~
.
" ::t _//###$#////_#//##j;iW#/$#/0'#~ ".'"~" lw=w~r r:w~r r1l)7T 1I)7T 1I~7T @T Tw)r r:2
WE
·1
I'~:c I~TI
Q
~gt =~---71-.
OPEN
•
NOTE:
NOTE 1
I.
}-----OPEN---'AA
tRAG
~
DON'TeARE
~
UNDEFINED
1. Do not drive data prior to tristate.
MT3D49
DM05.pm5 - Rev. 2f95
4-39
Micron Tachnology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
~CRCN
I ~.
m~",wo",c
Mn~
4 MEG x 9 DRAM MODULE
CBR REFRESH CYCLE
(Addresses = DON'T CARE)
.
RP
,
RAS
~ '"~4
•
-
C
JJ
'RPC~~
IIII
~~
II
QPEN---i-.;-.- - - - - - - - -
~~
I~II~I
~:~ -W1,1ffiJ0f)
~#u#;//#$u;/I}
*\!#;/$m$;l$/mWffff/li2
WE
l>
'Y
l
~:r-
DQ
RAS
1
=J"cp:~ ~I
CAS
RP
s:
en
s:
s:
HIDDEN REFRESH CYCLE 23
(WE = HIGH)
(REFRESH)
(READ)
r~'RP9
__~~j~J:',
__--~~n_______~~,I---'RAS .
'RCD
CAS
v __
I~ ~."
V:~~
ROW.
I,
II
II
'I
I
~.'"'I-""{~l
~
::
'RAl
COLUMN
:~:C ~
i
I
MT3D49
DMQ5.pm5 - Rev. 2/95
I
iCAG
•
~I
DO
----:--'CHR
11
~:~_
I-:--~'RAD
ADDR
.~.:
-'~
-.----=~-----Ir---
'RSH '. -
'RAS
I
-
-'OFF
t:gr :=.----- OPENI----~~C===~VA~LlD~D~ATA~==j
4-40
OPEN-
~
DON'TeARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT9D49
4 MEG x 9 DRAM MODULE
","",coe""
4 MEG x 9
DRAM
MODULE
4 MEGABYTE, 5V,
FAST PAGE MODE
FEATURES
• JEDEC- and industry-standard pinout in a 30-pin
single-in-line memory module (SIMM)
• High-performance CMOS silicon-gate process
• Single 5V ±10% power supply
• All device pins are TTL-compatible
• Low power, 27mW standby; 2,025mW active, typical
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
• 1,024-cycle refresh distributed across 16ms
• FAST PAGE MODE (FPM) access cycle
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
-7
• Packages
30-pin SIMM
M
PIN ASSIGNMENT (Front View)
30-Pin SIMM
(00-4)
-"0
KEY TIMING PARAMETERS
tRC
110ns
130n5
tRAC
60ns
70ns
tpc
35ns
40ns
tM
30ns
35ns
tCAG
15n5
20ns
tRP
40ns
50ns
GENERAL DESCRIPTION
The MT9D49 is a randomly accessed solid-state memory
containing 4,194,304 words organized in a x9 configuration.
During READ or WRITE cycles, each bit is uniquely addressed through the 22 address bits which are entered 11
bits (AOcAI0)at a time. RAS is used to latcl:l the first 11 bits
and CAS the latter 11 bits. A READ or WRITE cycle is
selected with the WE input. A logic HIGH on WE dictates
READ mode while a logic LOW on WE dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
falling edge of WE or CAS, whichever occurS last. If WE
goes LOW prior to CAS going LOW, the output pines)
remain open (High-Z) until the next CAS cycle. EARLY
WRITE occurs when WE goes LOW prior to CAS going
LOW, and the ouput rE'mains open (High~Z) until the next
CAS cycle.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row"address-defined (AOMT9D49
DM06.pm5 - Rev. 2/95
1
D01
2
3
CAS
• Part Number Example: MT9D49M-6
SPEED
-6
-7
Vee
AO
4
A1
D02
A2
A3
Vss
D03
A4
A5
D04
A6
A7
D05
A8
A9
*A10
D06
WE
Vss
D07
NC
D08
09
RAS
5
CAS9
6
D
0
7
8
9
10
11
12
13
14
15
16
17
18
21
22
23
24
25
26
27
28
D9
29
Vee
30
C
::D
»
s:
en
S
-
0
i:
0
19
20
•
0
0
0
• Address not used for RAS-ONLY REFRESH
A10) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed-in by CAS. CAS
may be toggled-in by holding RAS LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning RAS HIGH terminates the FAST PAGE
MODE operation.
REFRESH
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standbyleveL
Also, the chip is preconditioned for the next cycle during
the RAS HIGH time. Memory cell data is retained in its
correct state by maintaining power and executing any
RAS cycle (READ, WRITE) or RAS refresh cycle (RAS
ONLY, CBR or HIDDEN) so that all 1,024 combinations of
RAS addresses (AO-A9) are executed at least every 16ms
regardless of sequence.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT9D49
4 MEG x 9 DRAM MODULE
"W",CO" "
FUNCTIONAL BLOCK DIAGRAM
•
C
lJ
DQl
DQ5
DQ2
DQ6
DQ3
DQ?
DQ4
DQB
l>
s:
en
s-:
s:
CAS9---------t_+--------r---~
D9---------+-+--------~--~
Q9
Vee
Vss
Vee ________~_+----------------l
________________-1
~
Vss __________
U1-U9 = MT4C1 004JDJ
TRUTH TABLE
ADDRESSES
IR
IC
DATA-IN/OUT
001-008, 09, 09
FUNCTION
l{g
"CAS""
mg
wt
Standby
H
H-X
H-X
X
X
X
High-Z
READ
L
L
L
H
ROW
COL
Data-Out
L
L
L
L
ROW
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H-L
H--L
H
ROW
COL
Data-Out
READ
2nd Cycle
L
H-L
H-L
H
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H-L
H-L
L
ROW
COL
Data-In
WRITE
2nd Cycle
L
H-L
H:-+L
L
n/a
COL
Data-In
L
H
H
X
ROW
n/a
High-Z
EARLY WRITE
RAS-ONLY REFRESH
HIDDEN
REFRESH
CBR REFRESH
MT9D49
DM06.pm5 - Rev. 2195
READ
L-H-L
L
L
H
ROW
COL
Data-Out
WRITE
L-H-L
L
L
L
ROW
COL
Data-In
H-L
L
L
H
X
X
High-Z
4-42
Micron Technology, Inc" reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
MICRON
1-·
MT9D49
4 MEG x 9 DRAM MODULE
;cc~'"'cc,,"
"Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above tho~eindi
cated in the operational sections of this specification i~ not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee Supply Relative toVss .............. -IV to +7V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SsoC to +12SoC
Power Dissipation .......................... ;.................................. 9W
Short Circuit Output Current ..................................... SOmA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1,6,7) (Vcc = +5V ±10%)
PARAMETER/CONDITION
Supply VOltage
Input High (Logic 1) Voltage, all inputs
SYMBOL
MIN
MAx
UNITS
Vcc
4.5
5.5
V
YIH
2.4
Vcc.tl
V
NOTES
VIL
-1.0
0.8
V
INPUT LEAKAGE CURRENT
Any input OV ~ VIN ~ 6.5V '
(All other pins not under test = OV)
09, CAS9
II
-2
2
JJA
AO-A 10; WE, CAS, RAS
II
-18
OUTPUT LEAKAGE CURRENT
09
loz
(0 is disabled; OV ~ VOUT ~ 5.5V)
001-008
OUTPUT LEVELS
Output High Voltage (~oUT = -5mA)
Output Low Voltage (lOUT = 4.2mA)
'~
18
JJA
-10
"(10
IlA
loz
-12
12
!lA
VoH
2.4
-3:
(J)
i:
V
'VI
,0.4
VOL
,-
MAX
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
,
",
ST ANDBYGURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
OPERATING CURRENT: Random READIWRITE
Average power siJpplycurrent,
(RAS, CAS; AddressCycling: IRC.= IRC [MIN))
SYMBOL
-6
-7
UNITS
Icc1
18
18
mA
Icc2
9
9
mA
NOTES
.
,
;'
IcC3
990
900
'rnA
3,4,
2f>
"
OPERATING CURRENT: FAST PAGE MODE
Average poirer supply current
(RAS = VIL, CAS, Address Cycling: IpC = tpC[MINJ)
1004
720
630
mA
. 3,4,
, 26
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC = IRC [MIN])
Icc5
990
900
mA
3,26
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
Icc6
990
900
mA
3,5
MT9D49
,
DMOS:pm5 - Rev. 2/95
4'-43
C
:0
l>
3:
,0,.
Input Low (Logic 0) Voltage, all ihputs
•
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
".
MT9D49
4 MEG x 9 DRAM MODULE
c.
CAPACITANCE
PARAMETER
•
C
::D
»
s:
en
s-:
!:
MAX
UNITS
Input-Capacitance: AO-A10
SYMBOL
Cll
MIN
55
pF
NOTES
2
Input Capacitance: RAS, WE, CAS
CI2
73
pF
2
2
Input Capacitance: 09, CAS9
CI3
10
pF
Input/Output Capacitance: 001-008
Cia
15
pF
2
Output Capacitance: 09
Co
10
pF
2
El,.E<;TRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7,8, 9, 10, 11; 12, 13) (Vee = +5V ±10%)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Column-address hold time
Access time· from CAS
CAS pulse width
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
CASprecharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output buffer turn-off delay
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
-RASpulse width (FAST PAGE MODE)
MT9049.
DM06.prn5- Rev. 2/95
-7
-6
SYM
tAA
tAR
tASC
tASR
tCAH
tCAC
tCAS
tCHR
tCLZ
tcp
tCPA
MIN
50
a
a
a
0
10
15
10
10
nla
4-44
20
10
0
10
10
70
10
20
15
55
a
15
3
40
20"
nla
60
15
10
30
60
60
20
10,000
40
35
tpRWC
MAX
35
15
15
10,000
a
toFF
tpc
tRAC
tRAD
tRAH
tRAL
tRAS
tRASP
MIN
45
10
60
10
15
10
45
0
3
35
tcRP
tCSH
tCSR
tCWL
tDH
tDHR
tDS
MAX
30
SO
10,000
100,000
15
fO
35
70
70
70
35
10,000
100,000
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nla
ns
ns
ris
ns
ns
ns
NOTES
15
5
·16
5
21
21
20,25
23
.'. 14
18
Micron Technology, Inc., reserves the right to change products or specifications without notloe;
©1995, Micron Technology,lnc.
UII::::I=ICN
1-·
MT9D49
4 MEG x 9 DRAM MODULE
,,,""'coo,,,,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+5V ±1 0%)
-6
AC CHARACTERISTICS
-7
PARAMETER
Random READ or WRITE cycle time
SYM
IRC
MIN
110
MAX
MIN
RAS to CAS delay time
Read command hold time (referenced to CAS)
tRCD
20
45
130
20
MAX
UNITS
NOTES
50
ns
ns
tRCH
Read command setup time
Refresh period (1,024 cycles)
tRCS
tREF
0
0
17
0
ns
19
0
ns
16
16
IRP
40
50
ms
ns
tRPC
tRRH
0
Read command hold time (referenced to RAS)
0
0
ns
ns
RAS hold time
tRSH
ns
READ WRITE cycle time
Write command to RAS lead time
tRWC
tRWL
n/a
20
n/a
15
20
IT
3
10
RAS precharge time
RAS to CAS precharge time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT9D49
DM06.pm5 - Rev. 2195
twCH
0
15
twCR
twcs
twp
45
tWRH
10
tWRP
10
4-45
0
10
50
3
15
n/a
50
19
23
ns
ns
ns
•
C
:0
l'>
S
en
s-:
55
0
15
ns
ns
10
10
ns
24
ns
24
ns
Micron Technology, Inc., reserves the right to change products or speCifications without notice.
©1995, Micron Technology, Inc.
3:
IUIIIC:I=ICN
1-·
MT9D49
4 MEG x 9 DRAM MODULE
"'""'c'"""
NOTES
•
C
JJ
l>
s::
en
s:
s:
15. Assumes that IRCD 2 IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
lS. Operation within the lRAD (MAX) limit ensures that
IRAC (MIN) and ICAC (MIN) can be met.tRAD
C~l{P.-,-X) is specified as a reference point only; if tRAD
is greater than the specified IRAD (MAX) limit, then
access time is controlled exclusively by IAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
22. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.
23. LATE WRITE, READ WRITE or READ-MODIFYWRITE cycles are not available due to the common
DQ configuration of UI-US.
24. twTS and IWTH are set up and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of IWRP and twRH in the
CBR REFRESH cycle.
25. The 3ns minimum is a parameter guaranteed by
design.
26. Column-address changed once each cycle.
1. All voltages referenced to Vss.
2. This parameter is sampled. Capacitance is measured
using MIL-STD-883C Method 3012.1 (1 MHz AC
Vee = 5V,DC bias = 2.4V at 15mV RMS).
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
5. Enables on-chip refresh and address counters .
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C :::; TA :::; 70°C) is assured.
7. An initial pause of lOOlls is required after powercup
followed by any eight RAS refresh cycles (RAS ONLY
or CBR with WE HIGH) before proper device
operation is assured. The eight RAS cycle wake-ups
should be repeated any time the IREF refresh
requirement is exceeded.
8. AC characteristics assume IT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that 'RCD
exceeds the value shown.
MT9D49
DM06.pm5 - Rev. 2195
4-46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
I"IIC:F=lg,~
MT9D49
4 MEG x 9 DRAM MODULE
.
READ CYCLE
'RC
teSH
•
C
ADDR
::D
»
S
en
DQ
~lgr
' - - - - - - - - - OPEN
----------j~~L- ; .!.-; ~; ;:":~-; ; :;:-~;-- >1>-----
OPEN - - - -
EARLY WRITE CYCLE
'RC
'RP
teRP
ADDR
~lr
•
ROW
ROW
twcs
_I
I 'weR
I_ tWCH
'WP
WE
II
~:~ V,OH
•
~
'OS
I I.:~:R:I
-------:ALlDDATA
DQVIOL~.
MT9D49
DM06.pm5 - Rev. 219&
4-47
_
~
DON'TeARE
~
UNDEFINED
-
S
S
FAST-PAGE-MODE READ CYCLE
V,H
VIL
RAS
_----~~
;__----------__:_-RA-S-P---------:__-----·_1I'=1
!
L
I' _ _
tpc
tCSH
•
C
tRSH
ADDR
II
:l=-
s::
en
-s::
s::
DO
~:g~ -'------OPEN-----~XXXX'lf
OPEN--
FAST-PAGE-MODE EARLY-WRITE CYCLE
RAS
~:t
=
ICSH
CAS
ADDR
~:~
VALID DATA
MT9D49
DM06.pm5 - Rev. 2195
VALID DATA
4-48
VAllO DATA
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or speci licalionswithoulnolice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT9D49
4 MEG x 9 DRAM MODULE
"'"""0"""
RAS-ONLY REFRESH CYCLE
(A 10 and WE = DON'T CARE)
DQ
~gt
-
-----------OPEN------_----
•
C
:::D
»
s:
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODI FY-WRITE)
en
-s:
3:
~l
~
Q
~g~-
OPEN
I.
,oF:I~
1~IN~TE1
VAllO
I.
W~
OPEN-----
'M
tRAC
~
DON'T CARE
m
UNDEFINED
NOTE:
1. Do not drive data prior to tristate.
MT9D49
DM06.pm5 - Rev. 2/95
4-49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc
UU:::RCN
.-.
MT9D49
4 MEG x 9 DRAM MODULE
,,,",,oeoc,,,,
CBR REFRESH CYCLE
(Addresses = DON'T CARE)
.
'AP
tRAS
AAS
.---./
•
CAS
tRPC
Y1~
0
tWAP
WE
»
s:
1
1
.
tRAS
.
~~~ ~K
IIII _
DQ
:c
• 'CHA
'AP
• I •
II
II - - - - - - - - - - -
OPEN---77
II 'WAH
'WAP
I
'WAH
~:~ --W/l/m&J~ ~W/lEi@lI&zz{;~ ~~W////!tW//;W0ZWffil&
en
-s:
HIDDEN REFRESH CYCLE 22
(WE = HIGH)
s:
(AEAD)
;J~:
(AEFAESH)
tRAS
tRP
'f9-------:---:
'ACD--C--,_
ADDR
tRAS
'CH-----'A
v,H __7TTn Jc----'----i ,,,,,,,,,",,,, Jc-----'----i 1T777TT777:'77?777777TTT.7TTi'7777777TT777:rn7777TT7777:TT;
V ,L --LL..UCL/lI._-----,_---"'MAl""l'-_--,---,----"'.LL£,'-'-'-<'"-"-'.LLL.E.L-4.LL£..CL.L..<.LLL.LLLLLL..'-'-'-
:s:
:s:
CJ)
:s:
AO-AS
- - - - - I WE
CASO
- - - - - I CASL
CAS1
- - - - - I CASH
RAsa
----iRAS
U1
DQ1DQ16
OE
AO-AS
WE
DQ1-DQ32
AO-A8
~------IWE
CAS3
-----------1 CASL
-------------1 CASH
RAS2
-----------;RAS
U2
DQ17DQ32
OE
U1-U2 = MT4C16257DJ
MT2D25632, MT4D51232
DM29.pm5 - Rev. 2/95
4-52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,Micron Technology, Inc.
MICRON
1-·
MT2D25632, MT4D51232
256K, 512K x 32 DRAM MODULE
.,,"'0'00""
FUNCTIONAL BLOCK DIAGRAM
MT4D51232 (2MB)
AD-AS
WE
CASD
CASL
CASl
CASH
U1
•
D01D016
RAS
RASD
C
::rJ
OE
D01-D032
-ens:
AD-A8
WE
s:
CAS2
CAS3
RAS2
AD-AS
AD-AS
_
WE
U3
CASL
D01D016
RAS
RASl
OE
~D01-Dq32
••••
AD-AS
'---------!WE
L-_ _ _ _- j CASL
'---------1
RAS3
U4
D017D032
CASH
- - - - - - - - - - - - i RAS
OE
U1-U4 = MT4C16257DJ
MT2D25632, MT4D51232
DM29.pm5 - Rev. 2195
l>
s:
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc,
MICRON
1-·
MT2D25632, MT4D51232
256K , 512K x 32 DRAM MODULE
,,,"",we,,"e
TRUTH TABLE
ADDRESSES
•
DATA-IN/OUT
RM
"C}S
WE""
IR
IC
Standby
H
H-X
X
X
X
High-Z
READ
L
L
H
ROW
COL
Data-Out
FUNCTION
001-0032
L
L
L
ROW
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
L-H
H
ROW
COL
Data-Out
Data-Out
EARLY-WRITE
READ
2nd Cycle
L
L-H
H
n/a
COL
FAST-PAGE-MODE
1st Cycle
L
L-H
L
ROW
COL
Data-In
C
WRITE
2nd Cycle
L
L-H
L
n/a
COL
Data-In
»
s:
RAS-ONLY REFRESH
L
H
X
ROW
n/a
High=Z
::D
en
s:
s:
HIDDEN
READ
L-H-L
L
H
ROW
COL
Data-Out
REFRESH
WRITE
L-H-L
L
L
ROW
COL
Data-In
H-L
L
X
X
X
High-Z
CBR REFRESH
JEDEC DEFINED
PRESENCE-DETECT - MT2D25632 (1 MB)
SYMBOL
PRD1
PRD2
PRD3
PRD4
PIN#
-6
-7
67
68
69
70
Vss
Vss
NC
NC
NC
Vss
NC
NC
JEDEC DEFINED
PRESENCE-DETECT - MT4D51232 (2MB)
SYMBOL
PRD1
PRD2
PRD3
PRD4
MT2D25632, MT4D51232
DM29.pm5-Rev.2/95
PIN#
-6
-7
67
68
69
70
NC
NC
Vss
Vss
NC
Vss
NC
NC
4-54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT2D25632, MT4D51232
256K, 512K x 32 DRAM MODULE
"'"''"00''''
*Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee Supply Relative to Vss .............. -IV to +7V
Operating Temperature, T A (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ............................................................. 2W
Short Circuit Output Current ...................................... 50mA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 6) (Vcc = +5V ±1 0%**)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vcc
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
Vcc+1
V
InpulLow (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
2
PARAMETER/CONDITION
NOTES
INPUT LEAKAGE CURRENT
Any input OV :0; VIN :0; Vcc
(All other pins not under test = OV) for each package input
RASO- RAS3
AO-A8, WE
CASO-CAS3
111
1i2
1i3
-2
-8
-4
8
4
j.!A
j.!A
j..IA
27
27
OUTPUT LEAKAGE CURRENT
(Q is disabled; OV:O; VOUT :0; 5.5V) for each package input
"OQ1-DQ32
loz
-20
20
j.!A
27
VOH
2.4
OUTPUT LEVELS
Output High Voltage (lOUT = -5mA)
Output Low Voltage (lOUT = 4.2mA)
V
VOL
0.4
V
MAX
SYMBOL
SIZE
-6**
-7
UNITS
STANDBY CURRENT: (TTL)
(RAS =CAS = VIH)
Icc1
1MB
2MB
4
8
4
8
rnA
STANDBY CURRENT: (CMOS)
(RAS = CAS = Other Inputs = Vcc -0.2V)
ICC2
1MB
2MB
2
4
2
4
mA
Icc3
1MB
2MB
380
384
340
344
mA
2,22,
25
Icc4
1MB
2MB
240
244
220
224
mA
2,22,
25
REFRESH CURRENT: RAS ONLY
Average power supply cmrent
(RAS Cycling, CAS = VIH: IRC = IRe [MIN])
Iccs
1MB
2MB
380 ..
384
340
344
mA
22,25
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling; IRC
Icc6
1MB
2MB
360
364
320
324
mA
19,22
PARAMETER/CONDITION
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC =IRC [MIN])
OPERATING CURRENT: FASTPAGEMODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC = IpC [MIN];
ICp, IASC = iOns)
=IRC [MIN])
NOTES
**60ns specifications are limited to a Vcc range of ±5%.
MT2D25632, MT4DS1232
DM29.pmS - Rev. 2/95
4-55
Micron Technology. Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
C
::D
»
s:
en
s:
s:
MICRON
1-·
MT2D25632, MT4D51232
256K, 512K x 32 DRAM MODULE
m~",'cc,,,>c
CAPACITANCE
PARAMETER
•
C
:::D
l>
s:
en
s:
s:
SYMBOL
MAX
1MB
2MB
UNITS
NOTES
Input Capacitance: AO-A8
Cit
12
24
pF
17
Input Capacitance: WE
CI2
16
32
pF
17
Input Capacitance: RASO, RAS1, RAS2, RAS3
Ci3
10
10
pF
17
Input Capacitance: CASO, CAS1, CAS2, CAS3
CI4
10
20
pF
17
InpuVOutput Capacitance: D01-D032
ClOt
10
18
pF
17
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7,10,11,16) (Vcc
=+5V ±10%*)
AC CHARACTERISTICS
PARAMETER
SYM
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Access time from CAS
'AA
'AR
'ASC
'ASR
'CAC
Column-address hold time
CAS pulse width
CAS hold time (CBR REFRESH)
Last CAS going LOW to first CAS to return HIGH
CAS to output in Low-Z
CAS precharge time
Access time from CAS" precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output buffer turn-off delay
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS"
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
Random READ or WRITE cycle time
-6'
'CAH
'CAS
'CHR
'CLCH
'CLZ
'CP
'CPA
'CRP
'CSH
'CSR
'CWL
'DH
'DHR
'DS
'OFF
'PC
'PRWC
'RAC
'RAD
'RAH
'RAL
'RAS
'RASP
'RC
MIN
-7
MAX
MIN
30
50
°
°
10
15
15
10,000
10
3
10
°
°
15
20
10
10
3
10
15
10
30
60
60
110
ns
ns
ns
ns
ns
ns
20
10,000
40
35
8
60
10
15
10
45
3
35
n/a
UNITS
35
55
10
°
MAX
10
70
10
20
15
55
15
60
30
°
15
15
70
35
3
40
n/a
10
10,000
100,000
35
70
70
130
10,000
100,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
9
19
26
24
18
19
15
15
12,24
21
8
23
'60ns specifications are limited to a Vcc range of ±5%.
MT2D25632, MT4D51232
DM29.pm5- Rev. 2/95
4-56
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT2D25632, MT4D51232
256K, 512K x 32 DRAM MODULE
"'~"'oo'"'
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7,10,11,16) (Vee =+5V ±10%*)
AC CHARACTERISTICS
SYM
tRCD
MIN
Read command hold time (referenced to CAS)
tRCH
0
Read command setup time
tRCS
tREF
0
Refresh period (512cycles)
-7
-6*
PARAMETER
RAS to CAS delay time
20
MAX
45
MIN
MAX
20
50
0
0
8
8
UNITS
ns
ns
tRP
40
50
ns
tRPC
tRRH
10
0
10
ns
ns
RAS hold time
READ WRITE cycle time
tRSH
15
0
20
tRWC
tRWL
tT
n/a
n/a
Write command to RAS lead time
Transition time (rise or fall)
15
3
ns
Write command hold time
tWCH
10
Write command hold time (referenced to RAS)
tWCR
45
55
ns
WE command setup time
twcs
0
10
0
10
ns
tyvP
50
21
ns
ns
3
10
Write command pulse width
14
ns
20
50
13
14
ns
ms
RAS to CAS precharge time
Read command hold time (referenced to RAS)
RAS precharge time
NOTES
ns
ns
*60ns specifications are limited to a Vcc range of ±5%.
MT2D25632, MT4D51232
DM29.pm5- Rev. 2/95
4-57
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
C
:D
»
3:
en
s:
s:
M
II:::1=1CN
1-·
MT2D25632, MT4D51232
256K, 512K x 32 DRAM MODULE
""""00""
NOTES
•
C
::D
l>
S
en
-S
S
1. All voltages referenced to Vss.
2. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
3. An initial pause of lOOlls is required after power-up
followed by any eight RAS cycles before proper
device operation is assured. The eight RAS cycle
wake-ups should be repeated any time the IREF
refresh requirement is exceeded.
4. AC characteristics assume IT = Sns.
5. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signab. Transition times
are measured between VIH and VIL.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C ~ TA ~ 70°C) is assured.
7. Measured with a load equivalent to two TTL gates
and lOOpP.
8. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
9. Assumes that IRCD ~ IRCD (MAX).
10. If CAS = VIH, data output is High-Z.
11. If CAS = VIL, data output may contain data from the
last valid READ cycle.
12. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
13. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
MT2D25632, MT4D51232
DM29.pmS - Rev. 2/95
14. Either IRCH or IRRH must be satisfied for a READ
cycle.
15. These parameters are referenced to CAS leading edge
in EARLY-WRITE cycles.
16. In addition to meeting the transition rate specification, all input signals must transit between VlH and
VIL (or between VIL and VIH) in a monotonic manner.
17. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 3012.1 (1 MHz AC,
Vee = SV, DC bias = 2.4V at lSmV RMS).
18. If CAS is LOW at the falling edge of RAS, data-out
(Q) will be maintained from the previous cycle. To
initiate a new cycle and clear the data-out buffer, CAS
must be pulsed HIGH for !CP.
19. On-chip refresh and address counters are enabled.
20. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.
21. LATE-WRITE, READ-WRITE or READ-MODIFYWRITE cycles are not available due to OE being
grounded on UI-U2/U4.
22. Ice is dependent on cycle rates.
23. Operation within the lRAD (MAX) limit ensures that
IRCD (MAX) can be met. lRAD (MAX) is specified as
a reference point only; if lRAD is greater than the
specified IRAD (MAX) limit, then access time is
controlled exclusively by lAA.
24. The 3ns minimum is a parameter guaranteed by
design.
25. Column-address changed once each cycle.
26. Last falling CASx edge to first rising CASx edge.
27.1MB module values will be half of those shown.
4-58
Micron Technology, Inc., reserves the right to change products or speCifications without notica.
©1995, Micron Technology, Inc.
MICRON
1-·
MT2D25632, MT4D51232
256K, 512K x 32 DRAM MODULE
"'"""'"'"'
READ CYCLE
tAP
V,H
_,-------------ll
VIL _
tCSH
•
C
AODR
::rJ
»
s:
en
DO
~:g~ -:---------OPEN----------i~M=:~~~J_---OPEN----
EARLY WRITE CYCLE
AAS
VIH VIL _
CAS
V,H
VIL _
-J
teRP
tRAD
ADDR
V,H
V,L
ROW
CZJ DON'T CARE
!l22l UNDEFINED
MT2D25632, MT4D51232
DM29.pm5 - Rev. 2/95
4-59
Micron Technology, Inc., reserves the right
to change products or specifications without notice.
©1995,MicronTechnalogy, Inc.
-5
5
MIC:RON
1-·
MT2D25632, MT4D51232
256K, 512K x 32 DRAM MODULE
,""'CW'''''
FAST-PAGE-MODE READ CYCLE
-------------------------------I~RA~S~P------------------------------~I~
RAS
VIH
V,L
tCSH
~
•
CAS
-
ADDA
C
:D
»
VIH
V,L
,.
WE
~i~
s:
~/I!/II!/;)/I,@
I
I.
-s:
en
-I I
I~
Wzj
I
ILIRCS
tRCH-
I
I
I
I
I
tCLZOPEN
I
lAA
I
tRAC
ICAC
!~
10F~1
I
I
tePA
tCLZ-
VALID
DATA
I
IAA
I~
1:-
I·
:OFF:I
I
I
lAA
I' 1:tePA
ICAC :
tCLZVALID
DATA
-
J-IOFF
VALID
DATA
OPEN--
s
FAST-PAGE-MODE EARLY-WRITE CYCLE
leSH
ADDA
OQ
~:gt
MT2D25632, MT4051232
DM29.pm5 - Rev. 2195
-..u====!.LL!.LL!.LLflL_____
VA_L_'D_D_AT_A__--1f·VJ.U'-.____________Jr\!.LLf'-____________.Jf'<.LLLLLLLLLLLLLLLLLLLLL
4-60
fill
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
MT2D25632, MT4D51232
256K, 512K x 32 DRAM MODULE
m~"oco"'"
1-·
RAS-ONlY REFRESH CYCLE
(WE = DON'T CARE)
~ "~_._'AAS_~"Lb'AP
CAS
ADDA
DQ
~:t ==0
'ASA
II
l'-----_
'AAH
--iw/j;I/"$//"/$$//"/"//"///"/$//,,;//!;X--AO-W- -
~:t =~r---AO-W
~gr
------------QPEN----------
•
c
:c
l>
S
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
en
-
S
s:
ICSH
ADDR
~:t =:
I_---c--"A"""CS'--
II 'CWL
II 'AWL
II 'WP
I
I
WE
o
~:t =
'wcs
I.
I
I.
I
'CAC
I
OPEN
I.
I.
1W ~
tAA
tRAC
""om
!w$,w'$$//#$h
'°11
In.. '\iALi[)' NOTE 1
~gt-
/TTT7CrT777"O'7TTT777TT7T77
'-;--~-!+-.:-II~---1fU.LLLLLL.LLLLlLLLLL
s:
en
-s:
s:
HIDDEN REFRESH CYCLE 20
(WE = HIGH)
(READ)
RAS
VIH
VtL_
CAS
VIHVIL-
(REFRESH)
tRAS
tAP
tRAS
~-~t-RC-D-----~tR-S--"·~-:---~t-CH-R------
~:
ADDR
-tOFF
DO
~:gt
-'---------- OPEN------~i22lm.
_____
~V~AL~ID~D~AT~A~_ _ ___.i
OPEN-
I2Z1 DON'T CARE
~
MT2D25632, MT4D51232
DM29.pm5 - Rev. 2/95
4-62
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT8D132(S), MT16D232(S)
1 MEG,2 MEG x 32 DRAM MODULE
"'""ococ"'"
1 MEG, 2 MEG x 32
DRAM
MODULE
4,8 MEGABYTES, 5V, FAST PAGE MODE,
OPTIONAL SELF REFRESH
FEATURES
PIN ASSIGNMENT (Front View)
• JEDEC- and industry-standard pinout in a 72-pin,
single-in-line memory module (SIMM)
• High-performance CMOS silicon-gate process.
• Single 5V ±10% power supply
• All device pins are TTL-compatible
• Low power, 48mW standby; 1,824mW active, typical
(8MB)
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN; optional Extended and SELF Refresh
• Multiple RAS lines allow x16 or x32 width
• 1,024-cycle refresh distributed across 16ms or
1,024-cyc1e Extended Refresh distributed across 128ms
• FAST PAGE MODE (FPM) access cycle
OPTIONS
MARKING
• Timing
60ns access
70ns access
-7
• Packages
72-pinSIMM
72-pin SIMM (gold)
M
G
~[J[J[JlJ
1
tRC
tRAC
tpc
tAA
tCAC
tRP
110ns
60ns
35ns
30ns
l5ns
40ns
-7
l30ns
70ns
40ns
35ns
20ns
50ns
MT8D132M-xx
1 Meg x 32, Gold
·1 Meg x 32, S", Gold
1 Meg x 32, Tin/Lead
1 Meg x 32, S**, Tin/Lead
MT16D232G-xx
2 Meg x 32, Gold
MT16D232G-xx S
2 Meg x 32, S**, Gold
MT16D232M-xx
2 Meg x 32, Tin/Lead
MT16D232M-xx S
2 Meg x 32, S**, Tin/Lead
SYMBOL
OQ12
0028
0013
0029
Vee
0030
0014
0031
0015
0032
0016
NC
PROl
PR02
PR03
PR04
NC
Vss
The MT8D132(S) and MT16D232(S) are randomly accessed 4MB and 8MB solid-state memories organized in a
x32 configuration. During READ or WRITE cycles each bit
is uniquely addressed through the 20 address bits, which
are entered 10 bits (AO -A9) at a time. RAS is used to latch the
first 10 bits and CAS the latter 10 bits. A READ or WRITE
cycle IS selected with the WE input. A logic HIGH on WE
dictates READ mode while a logic LOW on WE dictates
WRITE mode. Ouring a WRITE cycle, data-in (D) is latched
by the falling edge of WE. or CAS, whichever occurs last.
EARLY WRITE occurs when WE goes LOW prior to CAS
going LOW, the output pin(s) remain open (High-Z) until
the next CAS cycle.
DESCRIPTION
MT8D132M-xx S
**S = SELF REFRESH
MT8D132(S), MT16D232(S)
DM43.pm5 - Rev. 2195
72
GENERAL DESCRIPTION
VALID PART NUMBERS
MT8D132G-xx S
37
we
-6
MT8D132G-xx
36
SYMBOL PIN # SYMBOL PIN # SYMBOL PIU
1
Vss
19
NC
37
NC
55
2
001
20
005
38
NC
56
21
0021
3
0017
39
Vss
57
4
002
22
006
40
l:ASO
58
0018
23
0022
41
5
D\S2
59
OQ3
6
24
007
42
1:AS3
60
0023
7
0019
25
43
CASf
61
D04
26
008
44
8
ro\SO
62
9
0020
27
0024
45 NCiRAScP 63
Vee
46
10
28
A7
NC
64
11
NC
29
NC
47
65
12
AO
30
Vee
48
NC
66
13
Al
31
A8
49
D09
67
14
A2
32
0025
A9
50
68
15
A3
33 NC/RJlS3* 51
DOlO
69
34
0026
16
A4
RAS2
52
70
17
A5
0011
71
35
NC
53
18
A6
36
NC
54
0027
72
"8MB version only
KEY TIMING PARAMETERS
PART NUMBER
lJDoqj »en
PIN #
Blank
S
SPEED
C
::D
III lin 11m lin nlll I1111 IIIlmt'IT1 ~TOTrrr'ffIOTIIITm"lTiO
-6
• Power/Refresh
Normal Power /16ms
SELF REFRESH/128ms
•
72-Pin SIMM
(00-7) 1 Megx 32
(00-8) 2 Meg x 32
4-63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
S
-
S
S
MICRON
1-·
MT8D132(S), MT16D232(S)
1 MEG, 2 MEG x 32 DRAM MODULE
",""ceo",,""
FAST PAGE MODE
•
C
:IJ
»
s:
en
-s:
s:
extended refresh period of 128ms. The module's SELF REFRESH mode is initiated by executing a CBR REFRESH cycle
and holding RAS LOW for the specified tRASS. Additionally,
the "S" version allows for an extended refresh period of
128ms, or 125ms per row if using distributed CBRREFRESH.
This refresh rate can be applied during normal operation, as
well as during a standby or extended refresh mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for the time minimum tRPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence, a
burst refresh is not required upon exiting SELF REFRESH
mode. However, if the DRAM controller utilizes burst
refresh sequence, all 1,024 rows must be refreshed within
300~s, prior to the resumption of normal operation.
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined
(AO-A9) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed-in by CAS. CAS
may be toggled-in by holding RAS LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning RAS HIGH terminates the FAST PAGE
MODE operation.
REFRESH
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS HIGH time. Memory cell data is retained in its
correct state by maintaining power and executing any
RAS cycle (READ, WRITE) or RAS refresh cycle (RAS
ONLY, CBR or HIDDEN) so that all 1,024 combination of
RAS addresses (AO-A9) are executed at least every 16ms
(128ms on S version), regardless of sequence.
An additional SELF REFRESH mode is also available. The
"S" version allows the user the option of a fully static low
power data retention mode, or a dynamic refresh mode at the
x16 CONFIGURA nON
For x16 applications, the corresponding DQ and CAS
pins must be connected together (DQ1 to DQ17, DQ2 to
DQ18 and so forth, and CASO to CAS2 and CAS 1 to
CAS3). Each RAS is then a bank select for the x16 memory
organization.
FUNCTIONAL BLOCK DIAGRAM
MT8D132 (4MB)
001 ··························008
OOg ·························0016
ott
! tt!
! tt!
WE
WE
OQ1-4
WE
RASO
--+---1 CAS
--+----1
CASl
--4-----i
CASO
001-4
U1
DOl -4
U2
CAS
! tt!
OQ1-4
WE
U,
U3
CAS
CAS
RAS
WE
0017 ....................... 0024
0025 ·················· .. ····0032
!! tr
tttl
OQl-4
CAS2
------I
AAS2
------I
ttt t
DQl -4
001 -4
t tt t
DQ1-4
U8
CAS3 - - - - - -
1
AO-A9 • • • • •
U1·U8 = MT4C4001JOJ
U1·U8 = MT4C4001JOJ S (S version)
MT8D132(S), MT16D232(S)
DM43.pm5 - Rev. 2/95
4-64
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT8D132(S), MT16D232(S)
1 MEG, 2 MEG x 32 DRAM MODULE
"'"'"'""'''
FUNCTIONAL BLOCK DIAGRAM
MT16D232 (8MB)
D01 ...•...................... D08
DOg ·························D016
ttt t
tttt
ttt t
001-4
OQ1-4
WE
RASa
---+........----l CAS
---++----l RAS
CAS1
---1-.+----
CASO
WE
t tt t
OQ1-4
f----iWE
U3
•
U4
CAS
CAS
f----iCAS
RAS
f - - - I - - - I RAS
f----iRAS
-
C
:0
D017 ....................... D024
0025 ......•................. D032
tl! t
ttt t
OQ1-4
WE
f------IWE
U2
U1
=
001-4
---+++----1 WE
tt! t
001-4
OQ1-4
f----jWE
U5
U6
CAS2
CAS
f----iCAS
RAS2
---++++-----l RAS
f----iRAS
- - - - I WE
s:
-ens:
s:
001-4
f----jWE
U8
U7
-1'----1
l>
t tt t
CAS
f----iCAS
RAS
f----iRAS
CAS3=iiiiii
Ao-A9 . .
D01 .........................• 008
DOg ·························0016
ttl!
tttl
001-4
ttl t
001-4
WE
f----IWE
U10
U9
f----ICAS
RAS1
001-4
DQ1-4
WE
U12
U11
CAS
----'H+t----j
t tt t
CAS
RAS
RAS
BE
0017
·······················0024
!!! t
001-4
WE
t tt t
D01-4
WE
U13
RAS3
AO-A9
D025 ························0032
ttt t
001-4
D01-4
WE
WE
U14
! ttt
U16
U15
CAS
CAS
CAS
CAS
RAS
RAS
RAS
RAS
U1·U16 = MT4C4001J or
U1·U16 = MT4C4001J S (S version)
MT8D132(S), MT16D232(S)
DM43.pm5 - Rev. 2/95
4-65
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT8D132(S), MT16D232(S)
1 MEG , 2 MEG x 32 DRAM MODULE
,""cwe""
TRUTH TABLE
1iKS"
FUNCTION
•
C
:0
l>
3:
en
-3:
m
"Wf
ADDRESSES
IR
IC
DATA-IN/OUT
001-0032
Standby
H
H~X
X
X
X
High-Z
READ
L
L
H
ROW
COL
Data-Out
EARLY WRITE
L
L
L
ROW
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H~L
H
ROW
COL
Data-Out
READ
2nd Cycle
L
H~L
H
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H~L
L
ROW
COL
Data-In
WRITE
2nd Cycle
L
H~L
L
n/a
COL
Data-In
L
H
X
ROW
n/a
High-Z
H
ROW
COL
Data-Out
RAS-ONLY REFRESH
HIDDEN
READ
L~H~L
L
REFRESH
WRITE
L~H~L
L
L
ROW
COL
Data-In
CBR REFRESH
H~L
L
H
X
X
High-Z
SELF REFRESH (S version)
H~L
L
H
X
X
High-Z
I
s:
JEDEC DEFINED
PRESENCE-DETECT - MTSD132 (4MB)
-6
-7
Vss
Vss
PRD2
PIN #
67
68
Vss
Vss
PRD3
69
NC
Vss
PRD4
70
NC
NC
SYMBOL
PRD1
JEDEC DEFINED
PRESENCE-DETECT - MT16D232 (SMB)
-6
-7
NC
NC
PRD2
PIN #
67
68
NC
NC
PRD3
69
NC
Vss
PRD4
70
NC
NC
SYMBOL
PRD1
MT8D132(S). MT160232(S)
DM43.pmS - Rev. 2195
4-66
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
cc,
MT8D132(S), MT16D232(S)
1 MEG, 2 MEG x 32 DRAM MODULE
,
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee Supply Relative to Vss .............. -IV to +7V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55 C to +125°C
Power Dissipation ... '.................................'......................... 8W
Short Circuit Output Current ..................................... 50mA
Q
'Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicatedin the operational sections oUhis specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ELECTRICAL CHARACTERI~TICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 6) (Vc,c = +SV ±1 '0%)
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, all inputs
Input Low (Logic '0) Voltage, all inputs
SYMBOL
Vcc
VIH
VIL
INPUT LEAKAGE CURRENT
Any input 'OV ~ VIN ::;; 6.SV
(All other pins not under test ='OV) for each package input
CAS'O-CAS3
AO-A9, WE
RAS'O-RAS3
OUTPUT LEAKAGE CURRENT
(0 is disabled; OV ::;; VOUT ~ 5.iW) for each package input
OQ1-0Q32
OUTPUT.LEVELS
Output High Voltage (lOUT =-SmA)
Output LowVoltage (lOUT =4.2mA)
MT8D132(S), MT160232(S)
DM43.pm5 - Rev. QJ95
MAX
Mitt
4.5
2.4
' -1:'0
-8'
5.5
Vcc+1
0.8
:
8
UNITS
"
V
V
V
112
~32
32
Il A
IlA
li3
-8
loz
c2'O
8
2'0
IlA
IlA
VOH
,2.4
111
• VOL
-
NOTES
C
:x:J
l>
29
29
29
V,
'0.4
•
V
Micron Technology, Inc., reserves the right to change products or speclficatfons wltI\out ho1fce.
@1995,MicronTechnoldgy;lrii::.
s:
en
-s:
s:
MIC:RON
1-·
""
MT8D132(S), MT16D232(S)
1 MEG , 2 MEG x 32 DRAM MODULE
c"
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 6) (Vcc =+5V ±1 0%)
'MAX
SYMBOL
SIZE
-6
-7
STANDBY CURRENT: (TTL)
(RAS = CAS = VI H)
ICCI
4MB
8MB
16
32
16
32
mA
STANDBY CURRENT: (CMOS)
(RAS = CAS = Other Inputs = Vcc -0.2V)
Icc2
4MB
8MB
4MB
8MB
8
16
1.6
3.2
8
16
1.6
3.2
mA
PARAMETER/CONDITION
•
ICC2
(S only)
UNITS NOTES
mA
C
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
Icc3
4MB
8MB
880
896
800
816
mA
2,22,
26
l>
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC = IpC [MIN])
Icc4
4MB
8MB
640
656
560
576
mA
2,22,
26
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC = IRC[MIN])
ICC5
4MB
8MB
880
896
800
816
mA
22,26
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
ICC6
4MB
8MB
880
896
800
816
mA
19,22
Icc7
(S only)
4MB
8MB
2
3.6
2
3.6
mA
19,22
24
Icca
(S only)
4MB
8MB
2
3.6
2
3.6
mA
19,27
SYMBOL
4MB
MAX
8MB
UNITS
NOTES
Input Capacitance: AO-A9
Cit
48
95
pF
17
Input Capacitance: WE
CI2
64
127
pF
17
17
:rJ
s:
en
-s:
s::
REFRESH CURRENT: Extended (S version only)
Average power supply current
CAS = 0.2V or CBR cycling; RAS = IRAS (MIN); WE = Vcc -0.2V;
AO-A9 and DIN = Vcc -0.2V or 0.2V (DIN may be left open);
IRC = 125j.lS (1,024 rows at 125j.lS = 128ms)
REFRESH CURRENT: SELF (S version only)
Average power supply current during SELF REFRESH
CBR cycling with RAS ~ IRASS (MIN) and CAS held LOW;
WE = Vcc -0.2V; AO-A9 and DIN = Vcc -0.2V or 0.2V
(DIN may be left open)
CAPACITANCE
PARAMETER
Input Capacitance: RASO-RAS3
CI4
32
32
pF
Input Capacitance: CASO-CAS3
CIS
16
32
pF
17
Input/Output Capacitance: 001-0032
CIO
10
18
pF
17
.
MTSD132(S). W,SD2.32(S)
DM4$.pm5,- Rev. 2195
4-68
,.,'
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995,MicronTechnology,I/'!C.
MU:::I=ICN
1-·
MT8D132(S), MT16D232(S)
1 MEG , 2 MEG x 32 DRAM MODULE
""" "
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7,10,11,16) (Vee
=+5V ±10%)
AC CHARACTERISTICS
PARAMETER
SYM
Access time from column-address
Column-address hold time (referenced to RAS)
tAA
tAR
Column-address setup time
Row-address setup time
Access time from CAS"
Column-address hold time
CAS" pulse width
••
RAS LOW to "don't care" during SELF REFRESH cycle
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time'
CAS setup time (CBR REFRESH)
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output buffer turn-off delay
FAST-PAGE-MODE READ or WRITE cycle time
FAsT-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
RAS pulse width during SELF REFRESH cycle
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (1,024 cycles)
Refresh period (1,024 cycles) S version
.
MT8Dt32(S). MT16D232(S)
DM43.pm5 - Rev. 2f95
-7
-6
tAse
tASR
tCAC
tCAH
tCAS
tCHD
tCHR
tCLl .
tcP
tCPA
tcRP
tCSH
tCSR
tCWL
tDH
MIN
45
0
0
n/a
tRASP
tRASS
tRC
tRCD
tRCH
tRCS
tREF
tREF
4-69
15
10
30
60
60
100
110
20
0
0
UNITS
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ms
ms
10,000
20
15
20
10
10
10,000
0
10
40
35
tpRWC
MAX
50
0
0
15
10
15
10
10
0
10
toFF
tpc
tRAC.
tRAD
tRAH
tRAL
tRAS
MIN
30
10
60
10
15
10
45
0
3
35
tDHR
tDS
MAX
10
70
10
20
15
15
60
30
10,000
100,000
45
55
0
3
40
n/a
15
10
35
70
70
100
130
20
20
70
35
10,000
100,000
50
0
0
16
128
16
128
NOTES
.'
9
27
19
18
19
15
15
12,25
21
8
23
27
13
14
Micron Tectmology, Inc., reserves the right tochange products or spedHcaUdOs wJthoutnotioo.
©1995, MiCron Technology, Inc.
MICRON
1-·
e
,
,
MTBD132(S), MT16D232(S)
1 MEG, 2 MEG x 32 DRAM MODULE
,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16) (Vee = +5V ±1 0%)
AC CHARACTERISTICS
PARAMETER
•
C
lJ
l>
s:
en
-s:
s:
RAS precharge time
RAS to CAS precharge time
"RAS" precharge time during SELF REFRESH cycle
Read command hold time
RAS hold time
READ WRITE cycle time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to tlAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (GBR REFRESH)
MTBOI32(S). MT16D232(S)
DM43.pm5 - Rev. 2/95
-7
-6
SYM
tRP
tRPC
tRPS
'RRH
'RSH'
'RWC
'RWL
'T
"NCH
'WCR
'WCS
'WP ,
'WRH
'WRP
MIN
40
0
110
0
15
MAX
n/a
15
3
50
MIN
50
0
130
0
20
nfa
20
3
10
15
45
0
10
10
10
55
0
15
10
10
MAX
UNITS
NOTES
ns
50
ns'
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
27
14
21
28
28
Micron Technology, Inc., reserves the right to change products or speCifications without notice.
@199S, MIcron Technology, Inc.
u II:::1=1CN
1-·
"'""OCOG""
MT8D132(S), MT16D232(S)
1 MEG,2 MEG x 32 DRAM MODULE
NOTES
16. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
17. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 3012.1 (1 MHz AC,
Vee = 5V, DC bias = 2.4V at 15mV RMS).
18. If CAS is LOW at the falling edge of RAS, data-out
(Q) will be maintained from the previous cycle. To
initiate a new cycle and clear the data-out buffer, CAS
must be pulsed HIGH for tcP.
19. On-chip refresh and address counters are enabled.
20. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.
21. LATE WRITE, READ WRITE or READ-MODIFYWRITE cycles are not available due to OE being
grounded on UI-U8/UT6.
22. Ice is dependent on cycle rates.
23. Operation within the tRAD (MAX) limit ensures that
IRCD (MAX) can be met. tRAD (MAX) is specified as a
reference point only; if IRAD is greater than tl\('
specified lRAD (MAX) limit, then access time is
controlled exclusively by tAA.
24. Applies to S version only.
25. The 3ns minimum is a parameter guaranteed by
design.
26. Column-address changed once each cycle.
27. Refresh must be completed within the time of three
external refresh rate periods prior to active use of the
DRAM (provided distributed CBR REFRESH is used
when in the active mode). Alternatively, a complete
set of row refreshes must be executed when exiting
SELF REFRESH prior to active use of the DRAM if
anything other than distributed CBR REFRESH is
used in the active mode.
28. twTs and tWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of tWRP and twRH in the
CBR REFRESH cycle.
29.4MB module values will be half of those shown.
1. All voltages referenced to Vss.
2. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
3. An initial pause of lOOl-1s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
4. AC characteristics assume IT = 5ns.
5. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (O°C s TA S 70°C) is assured.
7. Measured with a load equivalent to two TTL gates
and 100pF.
8. Assumes that IRCD < IRCD (MAX).lf IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that tRCD
exceeds the value shown.
9. Assumes that IRCD 2: tRCD (MAX).
10. If CAS = VIH, data output is High-Z.
11. If CAS = VIL, data output may contain data from the
last valid READ cycle.
12. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
13. Operation within the IRCD (MAX) limit ensures that
tRAC (MAX) can be met. tRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
14. Either tRCH or tRRH must be satisfied for a READ
cycle.
15. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
MT8D132(S), MT16D232(S)
DM43.pm5 - Rev. 2/95
4-71
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
III
c
::D
»
s:
en
S
-
s:
MIC:RON
MT8D132(S), MT16D232(S)
1 MEG , 2 MEG x 32 DRAM MODULE
m~"occ,,",
1-·
READ CYCLE
'RC
tRAS
RAS
'RP
V 1H -
VrL _
tCSH
tRRH
tRSH
II
C
:D
l>
s:
en
s-:
s:
CAS
teAs
tRCD
tCRP
VrH V1L -
ROilv
ADDA
WE
I
tRAC
I
'CAC
~
~
DQ
VrOH VIOL
OPEN
VALID DATA
OPEN
EARLY WRITE CYCLE
RAS
V,H - - - - - - - - {
V 1l _
teAP
ADDR
~:t
ROW
ROW
~
DON'T CARE
!l22l UNDEFINED
MT8D132(S), MT16D232(S)
DM43.pm5 - Rev. 2/95
4-72
Micron TechnoJogy, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
MT8D132(S), MT16D232(S)
1 MEG, 2 MEG x 32 DRAM MODULE
"'~"OCOO,'"C
1-·
FAST-PAGE-MODE READ CYCLE
1~
______________________________~tR~A~S~P______________________________~~
•
C
::D
l>
3:
I.
DO
en
-s:
~:g~ -~--------- OPEN------------4S~{~)f}_------~~(~[t__------~~C~O
FAST-PAGE-MODE
ADDR
~:~
DO
~:g~
EARLY~WRITE
s:
CYCLE
CLLl/K-____, -__..Jr .'-L.l.l.l,____, - - - ,__, - - J
~I
MT8D132(S), MT16D232(S)
OM43. pm5 - Rev. ·2/95
VAllO DATA
VALID DATA
4-73
VALID DATA
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications 'without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
",",",ceO'
MT8D132(S), MT16D232(S)
1 MEG,2 MEG x 32 DRAM MODULE
'"
RAS-ONl Y REFRESH CYCLE
(WE = DON'T CARE)
l~
C
lJ
'RPi
:1:_d~_'C_RP- - '~ IC+-I-"_-_-_-_-_- -'-_-_
:
•
'RAS
·_~ '_'A-P~Cb====~-\'------_-_-_-
-_-_-_---_-_---_----"
ADDR
~:~
DQ
~g~
'ASA
, 'RAH
=~r---RO-W----,'.J;iJ;i$IJ;iJ;iJ;iJ;iI,!$$§$"$!$JJ(r---Ro-w - -
»
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s-:
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OPEN----------
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
tCSH
ADDR
~rr
-
COLUMN
II
II
II
I
I_---:---:"R""'cs--'.'I
I
I I I
'TTT7C77TTT77777Trrnr--;---;---.--'-____
WE
D
Q
~:t =
I
VOL
----1-,
'--,-I~-H
l~ul'OFF~.-1
VALID DATA
/7777CTTTTT;'77TTi'77T7777"i
----'LLL.LLL£.,'"-LLLLLL.L..LL.,!..LL.LLL
~/11111111#1111111111;2
I
NOTE 1
OPEN-t----~,/(&KV[£A~Ll2DU-------OPEN---1_._--'-"AA-'----_'_~II~.
_
NOTE:
~II~
'--I_-'--'Ds---'-I
~:t ::/'11111111111111111111111111111111111111/11111111111111I~
VOH -
'CWL
'RWL
'WP
tRAC
~
DON'T CARE
~
UNDEFINED
1. Do not drive data prior to tristate.
MT8D132(S), MT160232(S)
DM43.pmS - Rev. 2/95
4-74
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT8D132(S), MT16D232(S)
1 MEG,2 MEG x 32 DRAM MODULE
"'""'"'"""'
CBR REFRESH CYCLE
(Addresses = DON'T CARE)
·
tRP
..
tRAS
.
tCHR
.~ "~~
CAS
=i':
~:t-
-'=-
DO
WE
.. I ..
~
II
..
~~~
2
II
tWRP
tRP
~CHR
tRAS
•
1
l
oPEN----;-I-;--1_ _------,-_ __
tWRH
tWRP
II
tWRH
~:~ $'/$##Irr- "'---W/##//$##//#d-- --'W///;j///$/#$/;j//J//#/J;
EXTENDED CBR REFRESH CYCLE 24
(Addresses = DON'T CARE)
·
·
-----1'
.
125~s
tRP
..
.
tRAS
.
..
tRAS
._1
'RPC
l~ 2
.
tCHR
~~~
II
DO
-
tRP
tWRP
II
JCHR
.~
II
OPEN--'-'---------tWRH
.
tWRP
II
tWRH
WE~:~ !$;I//$///lr--- -W//;j#$##/$/;J- -t&;j//$//$$$$$/#h
~
DON'TeARE
@2l UNDEFINED
MT8DI32(S). MTI6D232(S)
DM43.pm5 - Rev. 2/95
4-75
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
•
C
::D
»
s:
en
s:
s:
UU::::I=ICN
1-·
MTBD132(S), MT16D232(S)
1 MEG , 2 MEG x 32 DRAM MODULE
"'""'c,,"'''
HIDDEN REFRESH CYCLE 20
(WE = HIGH)
(REFRESH)
(READ)
•
c
::c
»
s:
(J)
s:
s:
ADDR
~:g~
DQ
VALID
: : : - - - - - O P E N - - - - - ' > i ' M ' l ML -_ _ _ _
_DATA
____
SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
NOTE 1
_
V,H _
RAS
VIL -
CAS
WE
NOTE:
VOL
•
• 'RASS
Ii;)
,
•
II
;~~
•
(r
NOTE
'""
tRPe.
V
~
OPEN-
; -
'---1
I
II
I \ - OPEN
~II~)
~:t ::l/////!//II!
~II~
~W#$I;I#$$/////$$/;I$/;I$/J
~///;W///$/4
~
DON'T CARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT8D132(S), MTI6D232(S)
DM4~,pm5
'RP
~:~ -F~~~bl4~////$//!IIII!!I///;///~J///!!W2-l
VOH
DO
•
~
~
- Rev. 2/95
4-76
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII::::I=ICN
1-·
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG x 32 DRAM MODULES
"'''''''co,",
1 MEG, 2 MEG x 32
DRAM
MODULE
4,8 MEGABYTE, 3.3V, OPTIONAL SELF
REFRESH, FAST PAGE OR EDO PAGE
MODE
FEATURES
• JEDEC-standard pinout in a 72-pin single-in-line
memory module (SIMM)
• High-performance CMOS silicon-gate process
• Single +3.3V ±O.3V power supply
• All device pins are TTL-compatible
• Low power, 9.6mW standby; 800mW active, typical
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN; optional Extended and SELF REFRESH
• 1,024-cycle refresh distributed across 16ms or
1,024-cycle Extended Refresh distributed across 128ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• 5V tolerant IIOs (5.5V maximum VIH leveD
• 3.3V mechanical key
OPTIONS
MARKING
• Timing
60ns access
70ns access
80ns access
-6
-7
-8
• Components
SOJ
TSOP
D
DT
• Packages
72-pinSIMM
72-pin SIMM (gold)
M
G
• Access Cycle
FAST PAGE MODE
EDO PAGE MODE
Blank
X
• Refresh
Standard/16ms
SELF REFRESH/128ms
Blank
S
PIN ASSIGNMENT (Front View)
72-Pin SIMM
(DD-14) TSOP, (DD-16) SOJ - 1 Meg x 32
(DD-15) TSOP, (DD-17) SOJ - 2 Meg x 32
C
JJ
l>
S
PIN# SYMBOL
1
Vss
2
001
3
0017
4
002
5
0018
6
003
7
0019
OQ4
8
0020
9
10
Vee
11
P05
12
AO
13
A1
14
A2
15
A3
16
A4
17
A5
18
A6
8MB version only
PIN #
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SYMBOL
NC
005
0021
006
0022
007
0023
008
0024
A7
NC
Vee
A8
A9
NC
NC
NC
NC
PIN#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
SYMBOL
NC
NC
Vss
CASO
CAS2
CAS3
"CASf
RASO
RAS1'
or
WE
PO ECC
009
0025
0010
0026
0011
0027
PIN# SYMBOL
55
0012
56
0028
57
0013
58
0029
59
Vee
60
0030
61
0014
62
0031
63
0015
64
0032
65
0016
66
POEDO
67
P01
68
P02
69
P03
70
P04
71 PO refresh
72
Vss
KEY TIMING PARAMETERS
EDO option
SPEED
tRC
tRAC
tpc
tAA
tCAC
tCAS
-6
·7
-8
110ns
l30ns
150ns
60ns
70ns
80ns
25ns
30ns
35ns
30ns
35ns
40ns
l8ns
22ns
22ns
10ns
l5ns
15ns
FPM option
MT8LD{T)132(X)(S). MT16LD(T}23Z(X)(S}
DM35.pmS - Rev. 2/95
•
4-77
SPEED
tRC
tRAG
tpc
tAA
tGAG
tRP
·6
-7
·8
110ns
l30ns
l50ns
60ns
70ns
80ns
35ns
40ns
45ns
30ns
35ns
40ns
l5ns
20ns
25ns
40ns
50ns
60ns
Micron Technology, Inc.) reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
en
-
S
S
ADVANCE
MICRON
1-·
,ec""""",,
MTBLD(T)132(X)(S), MT1SLD(T)232(X)(S)
1 MEG, 2 MEG x 32 DRAM MODULES
EDO PAGE MODE
VALID PART NUMBERS
PART NUMBER
•
C
J:J
:l=-
s:
I
MT8LDT132G-xx
1 Meg x 32 FPM, TSOP, Gold
MT8LDT132G-xx S
1 Meg x 32 FPM, S', TSOP, Gold
MT8LD132G-xx X
MT8LD132G-xx XS
1 Meg x 32 EDO, SOJ, Gold
1 Meg x 32 EDO, S', SOJ, Gold
MT8LDT132M-xx
1 Meg x 32 FPM, TSOP, Tin/Lead
MT8LDT132M-xx S
1 Meg x 32 FPM, S', TSOP, Tin/Lead
MT8LD 132M-xx X
MT8LD132M-xx XS
1 Meg x 32 EDO, SOJ, Tin/Lead
MT16LDT232G-xx
1 Meg x 32 EDO, S', SOJ, Tin/Lead
2 Meg x 32 FPM, TSOP, Gold
MT16LDT232G-xx S
MT16LD232G-xx X
2 Meg x 32 FPM, S', TSOP, Gold
2 Meg x 32 EDO, SOJ, Gold
MT16LD232G-xx XS
2 Meg x 32 EDO, S', SOJ, Gold
MT16LDT232M-xx
MT16LDT232M-xx S
2 Meg x 32 FPM, TSOP, Tin/Lead
en
MT16LD232M-xx X
2 Meg x 32 FPM, S', TSOP, Tin/Lead
2 Meg x 32 EDO, SOJ, Tin/Lead
MT16LD232M-xx XS
2 Meg x 32 EDO, S', SOJ, Tin/Lead
s:
'S = SELF REFRESH
-s:
EDO PAGE MODE, deSignated by the "X" option, is an
accelerated FAST PAGE MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS
goes back HIGH. EDO provides for CAS precharge time
(ICP) to occur without the output data going invalid. This
elimination of CAS output control provides for pipeline
READs.
FAST PAGE MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS. EDO operates as any DRAM READ or FAST-PAGEMODE READ, except data will be held valid after CAS
goes HIGH, as long as.RAS and OE are held LOW and WE
is held HIGH. OE can be broue:ht LOW or HIGH while
CAS and RAS are LOW, and the DQs will transition between valid data and High-Z (reference MT4LC4007J(S)
DRAM data sheet for additional information on EDO
functionality).
DESCRIPTION
REFRESH
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during the
RAS HIGH time. Preserve correct memory cell data.by
maintaining power and executing any RAS cycle (READ,
WRITE) or RAS refresh cycle (RAS ONLY, CBR or HIDDEN) so that all 1,024 combinations of RAS addresses (AOA9) are executed at least every 16ms (128ms on "5" version),
regardless of sequence. TheCBR and SELF REFRESH cycles
will invoke the internal refresh counter for automatic RAS
addressing.
An optional SELF REFRESH mode is also available. The
"5" version allows the user the option of a fully static low
power data retention mode, ora dynamic refresh mode at the
extended refresh period of 128ms. The module's SELF REFRESH mode is initiated by executing a CBR REFRESH cycle
and holding RAS LOW for the specified lRASS. Additionally,
the "5" version allows for an extended refresh period of
128ms, or 1251ls per row if using distributed CBR REFRESH.
This refresh rate can be applied during normal operation, as
well as during a standby or extended refresh mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for the time minimum IRPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all 1,024 rows must
be refreshed within 300lls, prior to the resumption of normal operation.
GENERAL DESCRIPTION
The MT8LD(T)132(X)(S) and MT16LD(T)232(X)(S) are
randomly accessed 4MB and 8MB solid-state memories
organized in a x32 configuration with optional SELF REFRESH. They are specially processed to operate from 3.0V to
3.6V for low voltage memory systems.
During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits, which are entered 10
bits (AO-A9) at a time. RAS latches the first 10 bits and
CAS latches the latter 10 bits.
READ and WRITE cycles are selected with the WE input.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. EARLY WRITE occurs when WE
goes LOW prior to CAS going LOW, the output pines)
remain open (High-Z) until the next CAS cycle.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined page
boundary. The FAST PAGE MODE cycle is always initiated
with a row-address strobed-in by RAS followed by a column-address strobed-in by CAS. CAS may be toggled-in by
holding RAS LOW and strobing-in different column-addresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the FAST PAGE MODE operation.
MTSLO(T)132(X)(S), MT16!-D(T)232(X}(S)
DM3S.pm5 - Rev., 2195
4-78
Micron Technology, Inc., resetvesthe right to change products,or specifications withoul notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
MTBLD(T)132(X)(S), MT16LD{T)232(X)(S)
1 MEG,2 MEG x 32 DRAM MODULES
'"~'''"'''''
1-·
FUNCTIONAL BLOCK DIAGRAM
MT8LD(T)132 (4MB)
001 .....•.............•...•.. 008
OQ1-4
WE
WE
OQ1-4
OQ1-4
WE
U1
DOg ························-0016
WE
OQ1-4
WE
U3
U5
U7
CASO
CAS
CAS
CAS
CAS
RASO
RAS
RAS
RAS
RAS
c
:a
OE
l>
CAS1
S
0017 ······················-0024
0025 ·······················-0032
-enS
S
OQ1-4
1 - - - - ; WE
WE
CAS2 --1--+-1 CAS
RAS
OQ1-4
U2
1 - - - - ; CAS
1 - - - - ; WE
- - - - I WE
U4
r - - - ; CAS
1 - - - - ; RAS
-+---IRAS
U6
1------1 CAS
us
1 - - - - ; RAS
CAS3---AO·A9
1 Meg x 32 EOO PAGE MODE
U1-U8 = MT4LC4007J(S)
1 Meg x 32 FAST PAGE MODE
U1-U8 = MT4LC4001J(S)
NOTE:
1. See package drawing for U1-U8 placement locations.
2. OE must be tied to Vss if notrequired.
MT8lD(T)132(X)(S), MT16LD(T)232(X)(S)
DM35.pmS - Rev. 2/95
4-79
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG x 32 DRAM MODULES
",""",co,,",
FUNCTIONAL BLOCK DIAGRAM
MT16LD(T)232 (8MB)
001 ··························OQ8
OOg ·························0016
tt tt
tt tt
D01-4
WE
•
AASO
---.--+---1 CAS
---1-
s:
-s:
CJ)
INPUT LEAKAGE CURRENT
$;
C
:xJ
Supply Voltage
PARAMETER/CONDITION
•
V
Micron Technology, Inc., reserves the right to change products or $pecifications without notice.
©1995, Micron Technology, Inc.
s:
ADVANCE
MICRON
1-·
"'""OC,,""
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG x 32 DRAM MODULES
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes· 1 3 , 6) (Vcc - +3 3V +0
- .3V)
•
C
II I
»
s:
-ens:
s:
-6
MAX
-7
-8
4MB
8MB
8
16
8
16
8
16
mA
4MB
8MB
Icc2
4MB
(S only) 8MB
4
8
0.8
1.6
4
8
0.8
1.6
4
8
0.8
1.6
mA
SYMBOL SIZE
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
Icc1
STANDBY CURRENT: (CMOS)
(RAS = CAS =Other Inputs = Vcc -0.2V)
Icc2
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC =tRC [M!N))
Icc3
1
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: tpc = tpc [MIN])
4MB
640
560
480
8MB
648
568
488
4MB
480
400
320
8MB
488
408
328
4MB
Icc5
(X only) 8MB
480
400
320
488
408
328
4MB
640
560
480
8MB
648
568
488
4MB
640
560
480
8MB
648
568
488
4MB
1.2
1.2
1.2
8MB
2.0
2.0
2.0
REFRESH CURRENT: SELF (S-version only)
4MB
Iccg
Average power supply current during SELF REFRESH; CBR cycling
with RAS :2: tRASS (MIN) and CAS held LOW; WE = Vcc -0.2V; OE, (S only)
8MB
AO-A9 and DIN = Vcc -0.2V or 0.2V (DIN may be left open)
1.2
1.2
1.2
2.0
2.0
2.0
Icc4
OPERATING CURRENT: EDO PAGE MODE (X-version only)
Average power supply current
(RAS = VIL, CAS, Address Cycling: tpc = tpc [MIN])
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: tRC = tRC [MIN])
Icc6
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIN])
Icc?
REFRESH CURRENT: Extended (S-version only)
Average power supply current
CAS = 0.2V or CBR cycling; RAS = tRAS (MIN); WE = Vcc -0.2V;
OE, AO-A9 and DIN =Vcc -0.2V or 0.2V
(DIN may be left open); tRC = 125/ls (1,024 rows at 125/ls = 128ms)
Iccs
(S only)
CAPACITANCE
UNITS NOTES
mA
mA
mA
mA
1 2 ,22,
26
2,22,
26
2,22,
26
mA
22,26
mA
22, 19
mA
19,22
mA
19
MAX
SYMBOL
4MB
8MB
UNITS
Input Capacitance: AO-A9
CI1
48
95
pF
17
Input Capacitance: WE
CI2
64
127
pF
17
Input Capacitance: RASO-RAS1
CI3
64
64
pF
17
Input Capacitance: CASO-CAS3
CI4
16
32
pF
17
Input/Output Capacitance: D01-D032
CIO
10
18
pF
17
PARAMETER
MT8LD(T)132(X)(S), MT16LD(T)232(X)(S)
DM35.pm5 - Rev. 2/95
4-84
NOTES
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicrcnTechnology,lnc.
ADVANCE
MIC:RON
1-·
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG,2 MEG x 32 DRAM MODULES
","",CO"""
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDlT10NS
(Notes: 3, 4, 5, 6, 7, 10, 11,16,21) (Vee = +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
SYM
Access time from column-address
tAA
Column-address hold time (referenced to RAS)
tAR
45
0
0
55
tASC
Row-address setup time
Column-address to WE delay time
tASR
tAWD
Access time from CAS
Column-address hold time
tCAC
tCAH
CAS pulse width
tCAS
tCHD
10
15
10
tCHR
tCLZ
tcp
10
3
10
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable Time
tCPA
tCRP
tCSH
tCSR
tCWD
tCWL
tDH
tDHR
tDS
MAX
MIN
30
Column-address setup time
RAS LOW to "don't care" during
SELF REFRESH cycle
-7
-6
MIN
-8
MAX
35
50
0
0
65
15
10,000
20
15
20
10
tOD
tOE
10,000
15
20
10
10
70
10
50
20
15
55
0-
ns
ns
ns
20
ns
ns
10,000
ns
ns
19
24
18
ns
ns
ns
ns
ns
ns
ns
15
ns
15
24,31
21
ns
ns
tOEH
15
Output buffer turn-off delay
toFF
tORD
3
0
tpc
35
40
45
ns
tpRWC
85
100
105
ns
FAST-PAGE-MODE
READ or WRITE cycle time
FAST-PAGE-MODE
READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
MTSLO(T)132{X}(S), MT16LD{T)232(X)(S}
DM35.pm5 ~ Rev. 2/95
tRAC
tRAD
tRAH
15
15
10
4-85
60
30
20
20
3
0
15
10
70
35
3
0
15
10
19
29
ns
20
20
ns
20
ns
ns
80
40
ns
ns
ns
•
o
::D
27
OE hold time from WE during
READ-MODIFY-WRITE cycle
OE setup prior to RAS during HIDDEN
REFRESH cycle
29
9
ns
ns
ns
10
80
10
50
20
15
60
0
20
NOTES
ns
ns
45
20
20
15
15
UNITS
40
10
3
10
40
35
MAX
55
0
0
70
10
3
10
10
60
10
40
15
10
45
0
MIN
12,24,32
12
8
23
Micron Technology, Inc., reserves the fight to change products or spedflcalions witllout notice.
©1995, Micron Technology, Inc.
l>
s:
en
s:
s:
ADVANCE
~IC:I=ICN
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG x 32 DRAM MODULES
"'""'w,""
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vee
= +3.3V ±0.3V)
SYM
MIN
Column-address to RAS lead time
tRAL
30
MAX
MIN
tRAS
60
10,000
70
60
100,000
RAS pulse width during SELF REFRESH cycle
Random READ or WRITE cycle time
tRASS
tRC
100
110
70
100
C
RAS to CAS delay time
Read command hold time (referenced to CAS)
tRCD
tRCH
20
»
S
Read command setup time
tRCS
tREF
-
RAS to CAS precharge time
RAS precharge time during
SELF REFRESH cycle
tRPC
tRPS
Read command hold time (referenced to RAS)
tRRH
0
RAS hold time
tRSH
15
READ WRITE cycle time
RAS to WE delay time
tRWC
tRWD
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
twCH
tWCR
::D
en
S
S
Refresh period (1,024 cycles)
Refresh period (1,024 cycles) S version
RAS pre charge time
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MTBLD(T)132(X)(S), MT16LO(T)232{X)(S)
DM35.pm5 - Rev. 2{95
tREF
tRP
10,000
100,000
130
45
0
0
MIN
MAX
UNITS
80
10,000
ns
ns
80
100
150
100,000
20
0
60
ns
ns
16
ms
128
ms
40
tRASP
•
MAX
35
RAS pulse width (FAST PAGE MODE)
RAS pulse width
-8
-7
-6
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
20
50
0
0
16
128
128
ns
27
~s
ns
I
13
14
ns
0
16
NOTES
50
60
0
130
0
150
ns
ns
ns
27
0
20
ns
14
ns
150
85
0
20
180
100
200
110
ns
ns
tRWL
15
20
20
ns
tr
3
10
twcs
twP
tWRH
tWRP
40
0
110
50
3
15
50
15
3
50
ns
ns
29
45
55
60
ns
0
10
0
15
10
0
15
ns
ns
29,31
10
ns
28
10
10
ns
28
10
10
4-86
Micron Technology, Inc., reserves the nght to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG X 32 DRAM MODULES
me"",,",
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vee = +3.3V ±0.3V)
SYM
Access time from column-address
IAA
Column-address setup to CAS
precharge during WRITE
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
ns
tASR
tAWD
tCAC
tCHD
tCHR
tClZ
tCSH
CAS setup time (CBR REFRESH)
tCSR
CAS to WE delay time
tCWD
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
tCWl
tDH
OE lOW to CAS HIGH setup time
Output buffer turn-off delay
OE setup prior to RAS during
HIDDEN REFRESH cycle
EDO-PAGE-MODE
READ or WRITE cycle time
EDO-PAGE-MODE
READ-WRITE cycle time
MTBLD(T)132(X)(S), MTI6lD(T)232(X)(S)
DM35.prn5-Rev.2/95
ns
55
0
0
70
CAS hold time
OE HIGH pulse width
UNITS
40
50
0
0
65
tCPA
tCRP
OE HIGH hold time from CAS HIGH
MAX
45
0
0
55
CAS precharge time
OE hold time from WE during
READ-MODIFY-WRITE cycle
35
tAR
tASC
Access time from CAS precharge
CAS to RAS precharge time
Output Enable Time
MIN
ns
ICOH
tcp
Output disable
30
-8
MAX
20
tCAS
Data-in setup time
MIN
15
tCAH
Data output hold after CAS lOW
MAX
15
CAS pulse width
RAS lOW to "don't care" during
SELF REFRESH cycle
CAS to output in low-Z
MIN
tACH
Column-address hold time
CAS hold time (CBR REFRESH)
-7
-6
AC CHARACTERISTICS - EOO PAGE MODE OPTION
PARAMETER
tDHR
tDS
22
18
10
10
10
10,000
10
3
5
10
15
15
10
10,000
10
3
5
10
35
10
50
10
40
15
10
45
0
40
15
15
tOE
ns
ns
ns
ns
ns
ns
ns
10
65
10
50
20
15
60
0
ns
ns
20
20
ns
ns
15
ns
15
31
21
ns
ns
20
ns
tOEHC
10
10
5
3
0
10
10
5
3
0
ns
tORD
10
10
5
3
0
tpc
25
33
35
ns
tpRWC
85
100
105
ns
4-87
20
19
29
ns
20
15
18
ns
15
tOFF
19
24
ns
ns
tOEH
tOEP
tOES
27
ns
45
20
20
ns
29
9
ns
10,000
10
3
5
10
10
55
10
50
20
15
55
0
tOD
ns
22
15
15
10
NOTES
ns
ns
20
ns
ns
12,24,32
MicronTechnologY,tnc., reserves the righl 10 change product8 or specifications Without notice.
©1995, Micron Technology, Inc.
•
c
:::c
l>
s:
en
-s:
s:
ADVANCE
I'IIIC:F=lCN
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG,2 MEG x 32 DRAM MODULES
",""eo",,,,,
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vee
=+3.3V ±0.3V)
PARAMETER
C
:D
l>
s:
-s:
en
s:
-7
-6
AC CHARACTERISTICS - EDO PAGE MODE OPTION
MIN
Access time from RAS
SYM
tRAC
RAS to column-address delay time
tRAD
15
MAX
MIN
60
30
-8
MAX
MIN
70
15
35
15
MAX
UNITS
80
ns
8
40
ns
23
Row-address hold time
tRAH
10
10
10
Column-address to RAS lead time
tRAL
30
35
40
RAS pulse width
tRAS
60
10,000
70
10,000
80
10,000
RAS pulse width (EDO PAGE MODE)
tRASP
60
100,000
70
100,000
80
100,000
RAS pulse width during SELF REFRESH cycle
tRASS
tRC
100
100
100
IlS
110
130
150
ns
Random READ or WRITE cycle time
NOTES
ns
ns
ns
ns
27
RAS to CAS delay time
tRCD
20
ns
13
Read command hold time (referenced to CAS)
tRCH
0
0
0
ns
14
Read command setup time
tRCS
0
0
0
ns
Refresh period (1,024 cycles)
tREF
16
16
16
ms
Refresh period (1,024 cycles) S version
tREF
128
128
128
ms
45
20
50
20
60
tRP
40
50
60
ns
RAS to CAS precharge time
tRPC
0
0
0
ns
RAS precharge time during
SELF REFRESH cycle
tRPS
110
130
150
ns
27
14
RAS precharge time
Read command hold time (referenced to RAS)
tRRH
0
0
0
ns
RAS hold time
tRSH
15
20
20
ns
READ WRITE cycle time
tRWC
150
180
200
ns
RAS to WE delay time
tRWD
85
100
110
ns
Write command to RAS lead time
tRWL
15
20
20
ns
Transition time (rise or fall)
Write command hold time
IT
tWCH
2
10
Write command hold time (referenced to RAS)
tWCR
45
WE command setup time
twcs
tWHZ
0
Output disable delay from WE (CAS HIGH)
50
2
50
15
50
ns
15
15
ns
55
60
ns
0
3
2
3
0
15
3
ns
15
29
29,31
ns
twp
twpz
10
15
15
ns
10
10
10
ns
WE hold time (CBR REFRESH)
tWRH
10
10
10
ns
28
WE setup time (CBR REFRESH)
tWRP
10
10
10
ns
28
Write command pulse width
WE pulse width for output
disable when CAS HIGH
MTSLD(T)132(X)(S}, MT16LD(T)232(X){S)
DM35.pm5 - Rev. 2/95
4-88
Micron Technology, Inc., reserves the right to change products or specifications Without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
,,,,,"cco,,",
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG x 32 DRAM MODULES
NOTES
1. All voltages referenced to Vss.
2. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
3. An initial pause of lOOl1s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
4. AC characteristics assume tT = 5ns for FPM and 2.5ns
forEDO.
5. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. Measured with a load equivalent to two TTL gates
and 100pF. Output reference voltages are 0.8V for a
low level and 2.0V for a high level.
8. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
9. Assumes that IRCD;:: IRCD (MAX).
10. If CAS and RAS = VIH, data output is High-Z.
11. If CAS = VIL, data output may contain data from the
last valid READ cycle.
12. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
13. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclUSively by ICAe.
14. Either IRCH or IRRH must be satisfied for a READ
cycle.
15. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
16. In addition to meeting the transition rate specification,
all input signals must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
17. This parameter is sampled. Vee = +3.3V ±0.3V;
f= 1 MHz.
MTSLD(T)132(X)(S), MT16LD(T)232(X)(S)
DM35.pm5 - Rev, 2/95
18. If CAS is LOW at the falling edge of RAS, data-out
(Q) will be maintained from the previous cycle. To
initiate a new cycle and clear the data-out buffer, CAS
must be pulsed HIGH for ICp.
19. On-chip refresh and address counters are enabled.
20. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and
OE = HIGH.
21. If OE is tied permanently LOW, LATE WRlTE or
READ-MODIFY-WRlTE operations are not possible.
22. Ice is dependent on cycle rates.
23. Operation within the IRAD (MAX) limit ensures that
IRCD (MAX) can be met. IRAD (MAX) is specified as a
reference point only; if IRAD is greater than the
specified lRAD (MAX) limit, then access time is
controlled exclusively by IAA.
24. The 3ns minimum is a parameter guaranteed by
design.
25. Refresh current increases if lRAS is extended beyond
its minimum specification.
26. Column-address changed once each cycle.
27. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
28. twTs and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of IWRP and twRH in the
CBR REFRESH cycle.
29. IWCS, IRWD, IAWD and ICWD are not restrictive
operating parameters. twcs applies to EARLY
WRITE cycles. IRWD, IAWD and ICWD apply to
READ-MODIFY-WRITE cycles. If tWCS;:: twcs
(MIN), the cycle is an EARLY WRITE cycle and
the data output will remain an open circuit throughout the entire cycle. If twcs < twcs (MIN) and
IRWD;:: IRWD (MIN), IAWD;:: IAWD (MIN) and
ICWD;:: ICWD (MIN), the cycle is a READ-MODIFYWRITE and the data output will contain data read
from the selected cell. If neither of the above
conditions is met, the state of data-out is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. IWCS, IRWD, tCWD and IAWD are not
applicable in a LATE WRITE cycle.
Micron Technology, Inc., reserves the right to change products or specifications'without notice.
©1995, Micron TechnologY,'lnc.
•
c
::c
»
s:
en
-s:
s:
ADVANCE
MICRON
1-·
",",we,",,,,,
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG X 32 DRAM MODULES
NOTES (continued)
•
C
:D
30. LATE WRITE and READ-MODIFY-WRITE cycles
must have both 10D and 10EH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. The
DQs will provide the previously read data if CAS
remains LOW and OE is taken back LOW after 10EH
is met. If CAS goes HIGH prior to OE going back
LOW, the DQs will remain open.
31. The DQs open during READ cycles once taD or 10FF
occur. If CAS goes HIGH before OE, the DQs will
open regardless of the state of OE. If CAS stays LOW
while OE is brought HIGH, the DQs will open. If OE
is brought back LOW (CAS still LOW), the DQs will
provide the previously read data.
32. For FAST-PAGE-MODE option, 10FF is determined
by the first RAS or CAS signal to transition HIGH. In
comparison, 10FF on an EDO option is determined by
the latter of the RAS and CAS signal to transition
HIGH.
33.4MB modules will have values half of those shown .
34. Applies to both EDO and FAST PAGE MODEs.
»
s:
en
-s:
s:
MTBLO(T)I32(X){S), MT16LD(T)232(X}{S)
DM35,pm5 - Rev. 2/95
4-90
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MTSLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG x 32 DRAM MODULES
",",ocoo,,",
READ CYCLE 34
RC
tRAS
RAs
V,H
VIL
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CAS
V,H
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WE
V,H
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NOTE 2
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OPEN
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I
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NOTE:
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....
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tWCR
I~
twp
~
DON'TeARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation wilUacilitate compatibility with
future EDO DRAMs.
2. tOFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MTSLO(T)132(X).(S), MT16LD(T)232{X)(S)
DM35,pm5 - Rev. 2195
4-91
Micron Technology, Inc., reserves the right to change products or specifications without'notice.
©1995, Micron Technology, Inc,
•
C
:xJ
»
s::
en
-s::
s::
ADVANCE
MICRON
1-·
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG x 32 DRAM MODULES
;0'<'"'00'"'
READ WRITE CYCLE 34
(LATE WRITE and READ-MODIFY-WRITE cycles)
'RP
tRAS
V,H
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------
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W//////////////////////////;
COLUMN
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NOTE:
'CAS
I
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~
W/////;~
I
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I
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COLUMN
I
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~
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~
UNDiO:FINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MTSLD(T)1S2(X)(S), MT16LD(T)232(X)(S)
DM35.pmS - Rev. 2/95
4-92
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology., Inc.
ADVANCE
MIC:RON
1-·
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG,2 MEG x 32 DRAM MODULES
"'""w"""
FAST-PAGE-MODE READ CYCLE
•
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:D
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tRAG
'CAG
~
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I~
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1-
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OPEN
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'CPA
'CAG
'CLZ-
VAllO
VALID
DATA
DATA
~ ~
--'OFF
~ ~
~ OPEN ----".".
DATA
~ ~
»
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3:
EDO-PAGE-MODE EARLY-WRITE CYCLE
RASP
-
,"CD
tCSH
I~
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I~
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~
NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT8LD{T)132(X)(S), MT16LD(T)232(X)(S)
DM3S.pmS - Rev. 2/95
4-93
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-'
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG x 32 DRAM MODULES
,",",ocoon,
FAST-PAGE-MODE EARLY-WRITE CYCLE
RASP
tCSH
t
•
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ROW
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I
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~:t =_IJ/$I$#$I#I/$/$I$$/;/#$$$I;Wl///;/$/$/#$/$I$$/$$$!$/$/$!;0W§h
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(LATE WRITE and READ-MODIFY-WRITE cycles)
'RASP
R-
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'CSH
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~
NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT8LD(T)132(X)(S), MT16LD(T)232(X}(S)
DM35.pm5 - Rev. 2/95
4-95
Micron Technology, Inc., reserves the rlght to change products or specifications without nOtice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MTSLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG x 32 DRAM MODULES
","",COO""
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
'RASP
tpc
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•
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ADDR
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RAS-ONL Y REFRESH CYCLE 34
(WE = DON'T CARE)
H
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ADDR
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NOTE:
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•
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DON'T CARE
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UNDEFINED
1. Do not drive data prior to tristate.
MT8LD(T}132{X)(S), MT16LD(T)232(X)(S)
DM35.pm5 - Rev. 2195
4-96
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
ADVANCE
UU:::I=ICN
1-·
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG, 2 MEG x 32 DRAM MODULES
,,,"",wene
HIDDEN REFRESH CYCLE 20, 34
(WE = HIGH; OE = LOW)
(READ)
,
CAS
I~
Jj
VtH
VfL_
(REFRESH)
tAAS
tRAS
'H
l
tRSH
tRCD
tAR
~II
tCHR
tRAD
II tRAL I
~:tAsc,ll~
Jc---
•
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-·1
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t8#1#//;/
SELF REFRESH CYCLE 34
(Addresses and OE = DON'T CARE)
tRP
tRASS
NOTEi
(~
]
tRPS
lA:TE 2
=: -~ ~~/$ff$ffff$ffffff/;:ff#~11 'VV-;
VOH DQ
WE
NOTE:
VOL
II
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~
DON'TCARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT8LO(T)132(X)(S), MTI6lD(T)232(X)(S)
DM35.pm5 - Rev. 2/95
4-97
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
»
s:
en
-s:
s:
ADVANCE
MICRON
1-·
MTBLD(T)132(X)(S), MT16LD(T)232(X)(S)
1 MEG,2 MEG x 32 DRAM MODULES
"'""""'"
CBR REFRESH CYCLE 34
(Addresses and OE = DON'T CARE)
.
RAS
--"
,
tRP
.~~
tRAS
•
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C
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EDO READ CYCLE
(with WE-controlled disable)
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V,H V,L -
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tcp
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ADDR
,
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NOTE:
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tOD
6
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MTBlO(T)132(X)(S), MTI6LD(T)232{X)(S)
DM35.pmS - Rev. 2/95
4-98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, !nc.
ADVANCE
MICRON
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
m~"co",,,
1-·
2 MEG
DRAM
MODULE
x 32
8 MEGABYTE, 3.3V, OPTIONAL SELF
REFRESH, FAST PAGE OR EDO PAGE
MODE
z
m
FEATURES
• JEDEC-standard pinout in a 72-pin single-in-line
memory module (SIMM)
• High-performance CMOS silicon-gate process
• Single +3.3V ±O.3V power supply
• All device pins are TTL-compatible
• Low power, 4mW standby; 800mW active, typical
• Refresh modes: RAS ONLY, CAS-BEFORE"RAS (CBR)
and HIDDEN; optional Extended and SELF REFRESH
modes
• 2,048-cycle refresh distributed across 32ms or
2,048-cycle Extended Refresh distributed across 128ms
• FAST PAGE. MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• 5V tolerant 1/0s (5.5V maximum VIH level)
• 3.3V mechanical key
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
-7
• Packages
72-pinSIMM
72-pin SIMM (gold)
M
• Access Cycle
FAST PAGE MODE
EDO PAGE MODE
Blank
G
X
• Refresh
Standard/32ms
SELF REFRE.SH/128ms
:e
PIN ASSIGNMENT (Front View)
•
72-Pin SIMM
(00-18)
kJLJlli
PIN # SYMBOL
1
Vss
2
001
3
0017
4
002
0018
5
6
003
0019
7
004
8
0020
9
10
Vee
11
P05
12
AO
13
Al
14
A2
15
A3
16
A4
17
A5
18
A6
PIN # SYMBOL
19
Al0
20
005
0021
21
22
006
0022
23
24
007
25
0023
26
008
27
0024
28
A7
NC
29
Vee
30
31
AS
32
A9
33
NG
34
NG
35
NG
36
NG
PIN#
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
SYMBOL
NC
NC
Vss
CA50
CAS2
CA~
.Ci\S1
RASa
NC
DE
WF
PO EGG
009
0025
0010
0026
0011
0027
c
:D
o
PIN # SYMBOL
0012
55
56
0028
57
0013
0029
58
59
Vee
60
0030
0014
61
62
0031
63
0015
64
0032
65
0016
PO EOO
66
67
POl
P02
68
69
P03
70
P04
PO refresh
71
72
Vss
VALID PART NUMBERS
Blank
S
KEY TIMING PARAMETERS
EDO option
PART NUMBER
DESCRIPTION
MT4L.D232G-xx
MT4LD232G-xx S
2 Meg x 32 FPM, SOJ, Gold
2 Meg x 32 FPM, S*, SOJ, Gold
tRAC
tpc
tru\
tCAC
tCAS
MT 4LD232G-xx X
MT4LD232G-xx XS
2 Meg x 32EDO, SOJ, Gold
2 Meg x 32EDO, S*, SOJ, Gold
110ns
60ns
30ns
35ns
2 Meg x 32 FPM, SOJ, Tin/Lead
20ns
10ns
12ns
MT4LD232M-xx
70ns
25ns
30ns
15ns
130ns
MT4LD232M-xx S
2 Meg x 32 FPM, S*, SOJ, Tin/Lead
MT4LD232M-xx X
MT4LD232M-xx XS
2 Meg x 32 EDO, SOJ, Tin/Lead
2 Meg x 32 EDO, S*, SOJ, Tin/Lead
SPEED
tRC
-6
-7
FPM option
SPEED
tRe
tRAC
tpc
tAA
teAc
tRP
-6
-7
110ns
130ns
60ns
70ns
35ns
30ns
15ns
40ns
40ns
35ns
20ns
50ns
MT4LD232(X)(S}
DM36.pmS ~ Rev. 2/95
*S = SELF REFRESH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
l>
S
en
-
S
S
ADVANCE
MICRON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
",",",co",",
GENERAL DESCRIPTION
z
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The MT4LD232 (X)(S) is a randomly accessed 16MB and
32MB solid-state memory organized in a x32 configuration
with optional SELF REFRESH. It is specially processed to
operate from 3.0V to 3.6V for low voltage memory systems.
During READ or WRITE cycles each bit is uniquely
addressed through the address bits, RAS latches the first 11
bits and CAS latches the latter 10 bits (AlO is ignored during
CAS falling edge). READ and WRITE cycles are selected
with the WE input. A logic HIGH on WE dictates READ
mode while a logic LOW on WE dictates WRITE mode.
During a WRITE cycle, data-in (D) is latched by the falling
edge of WE or CAS, whichever occurs last. EARLY WRITE
occurs when WE goes LOW prior to CAS going LOW, the
output pin(s) remain open (High-Z) until the next CAS
cycle.
If WE goes LOW after CAS goes LOW, data-out (Q) is
activated and retains the selected cell data as long as OE
remains LOW and RAS and CAS remains LOW (regardless
of WE). This late WE pulse results in a READ WRITE cycle.
If WE toggles LOW after CAS goes back HIGH, the output
pins will open (High-Z) until the next CAS cycle, regardless
ofOE.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined page
boundary. The FAST PAGE MODE cycle is always initiated
with a row-address strobed-in by RAS followed by a column-addressstrobed-in by CAS. CAS may be toggled-in
by holding RAS LOW and strobing-in different columnaddresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the FAST PAGE MODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the "X" option, is an
accelerated FAST PAGE MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS
goes back HIGH. EDO provides for CAS precharge time
(tcP) to occur without the output data going invalid. This
elimination of CAS output control provides for pipeline
READs.
FAST PAGE MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
MT4LD232(X)(S)
DM36.pmS ~ Rev. 2195
CAS. EDO operates as any DRAM READ or FAST-PAGEMODE READ, except data will be held valid after CAS
goes HIGH, as long as RAS and OE are held LOW and WE
is held HIGH. OE can be brought LOW or HIGH while
CAS and RAS are LOW, and the DQs will transition between valid data and High-Z (reference the MT4LC2M8E7(S)
DRAM data sheet for additional information on EDO
functionality).
REFRESH
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a red uced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS HIGH time. Preserve correct memory cell data by
maintaining power and executing any RAS cycle (READ,
WRITE) or RAS refresh cycle (RAS ONLY, CBR or HIDDEN) so that all 2,048 combinations of RAS addresses are
executed at least every 32ms (128ms on "S" version), regardless of sequence. The CBR and SELF REFRESH cycles
will invoke the internal refresh counter for automatic RAS
addressing.
An optional SELF REFRESH mode is also available. The
"S" version' allows the user the option of a fully static low
power data retentionmode,ora dynamic refresh mode at the
extended refresh period of 128ms. The module's SELF REFRESH mode is initiated by executing a CBR REFRESH cycle
and holding RAS LOW for the specified lRASS. Additionally,
the "s" version allows for an extended refresh rate of 62.5l1s
per row if using distributed CBR REFRESH. This refresh rate
can be applied during normal operation, as well as during a
standby or extended refresh mode.
The SELF REFRESH mode is terminated by drivingRAS
HIGH for the time minimum tRPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW -to-HIGH transition. If
the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all 2,048 rows must
be refreshed within 300l1s, prior to the resumption of nor"
mal operation.
4-100
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology. Inc.
ADVANCE
MIC:RON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
",,,,.ow,,,,,
FUNCTIONAL BLOCK DIAGRAM
8MB
Z
m
AD-A1O
U1
=e
WE
•
D01DOB
CAS
CASD
RAS
RAS
OE
OE
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en
-s:
s:
AD-A1O
U2
WE,
DQ9D016
CASl
AD-A1O
D01-DQ32
AD-A1O
WE
U3
CAS
CAS2
D017D024
RAS
DE
AO-A1D
'-----~WE
--+-+-----~ CAS
'-------1
'--------1
U4
D02SD032
RAS
DE
EDO PAGE MODE
U1-U4 = MT4LC2M8E7DJ(S)
NOTE:
1. OE must be tied to Vss if not required.
MT4LD232(X)(S)
OM36.pm5 - Rev. 2195
FAST PAGE MODE
U1-U4 =MT4LC2M8B1DJ(S)
4-101
Micron Technology, Inc.. reserves the right to change products or specifications withoot notice.
©1995, Micron Technology, Inc,
ADVANCE
MIC:RON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
<>,",oeoo""
TRUTH TABLE
ADDRESSES
z
m
=e
•
DATA-IN/OUT
FI/is-
"CAS
WE
lJE
IR
IC
001-0032
Standby
H
H~X
X
X
X
X
High-Z
READ
L
L
H
L
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
ROW
COL
Data-In
READ WRITE
L
L
H~L
L~H
ROW
COL
Data-Out, Data-In
FUNCTION
EDO/FAST-PAGE-MODE
1st Cycle
L
H~L
H
L
ROW
COL
Data-Out
c
READ
2nd Cycle
L
H~L
H
L
n/a
COL
Data-Out
EDO/FAST-PAGE-MODE
1st Cycle
L
H~L
L
X
ROW
COL
Data-In
»
s:
EARLY \'VRITE
2nd Cycie
L
H~L
L
X
n/a
COL
Data-In
EDO/FAST-PAGE-MODE
1st Cycle
L
H~L
H~L
L~H
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
Data-Out, Data-In
:tJ
en
-s:
s:
RAS-ONLY REFRESH
L
H~L
H~L
L~H
n/a
COL
L
H
X
X
ROW
n/a
High-Z
HIDDEN
READ
L~H~L
L
H
L
ROW
COL
Data-Out
REFRESH
WRITE
L~H~L
L
L
X
ROW
COL
Data-In
CSR REFRESH
H~L
L
H
X
X
X
High-Z
SELF REFRESH (S version)
H~L
L
H
X
X
X
High-Z
MT4LD232(X)(S)
DM36.pm5 - Rev. 2195
4-102
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron TechnologY,lnc.
ADVANCE
MICRON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
","'OCO,"',
PRESENCE-DETECT TRUTH TABLE
z
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-ens:
s:
Refresh Detect
Fast Page ModeJEDO Detect
ECC/Parity Detect
NOTE:
Vss = ground.
MT4LD232(X}(S)
DM36.pmS - Rev. 2/95
4-103
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©199S, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
"'""'c,,'"''
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
z
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=E
Voltage on Vee Pin Relative to Vss ................. -IV to +4.6V
Voltage on Inputs or I/O Pins
Relative to Vss .............................................. ,..... -IV to +5.5V
Operating Temperature, TA (ambient) .......... ooe to +70 oe
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ............................................................. 4W
Short Circuit Output Current ..................................... 50mA
III
C
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
Jl
(Notes: 1, 2, 3, 6, 22) (Vec
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PARAMETER/CONDITION
s:
en
s:
s:
-
=+3.3V ±0.3V)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
INPUT LEAKAGE CURRENT
CASO-CAS3
111
-2
2
Any input OV
AO-A9, WE, OE
112
-8
8
(All other pins not under test = OV) for each package input
RASO
113
-8
8
OUTPUT LEAKAGE CURRENT
(0 is disabled; OV $; VOUT $; 5.5V) for each package input
001-0032
loz
-10
10
JlA
JlA
JlA
JlA
VOH
2.4
0.4
V
$;
VIN
$;
5.5V
TTL OUTPUT LEVELS
MT4LD232(X}(S)
DM36.pmS - Rev. 2f95
I High Voltage (lOUT = -2mA)
I Low Voltage (lOUT = 2mA)
4-104
VOL
NOTES
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc,
ADVANCE
MII:::I=ICN
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
""'"'"00""
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes' 1, 3 , 6) (Vcc - +3 3V +0
- .3V)
MAX
SYMBOL
SIZE
-6
-7
Icc1
8MB
8
8
mA
Icc2
Icc2
(S only)
8MB
8MB
2
.6
2
.6
mA
mA
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC =tRC [MIN])
Icc3
8MB
520
480
mA
2,22,
26
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: tpc =tpc [MIN])
Icc4
8MB
360
320
mA
2,22,
26
ICC4
(X only)
8MB
480
440
mA
2,22,
26
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: tRC =tRC [MIN])
Iccs
8MB
520
480
mA
22, 26
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC
ICC6
8MB
520
480
mA
22,19
Icc?
(S only)
8MB
1.2
1.2
mA
19,22
Iccs
(S only)
8MB
1.2
1.2
mA
19
MIN
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS =CAS = VIH)
STANDBY CURRENT: (CMOS)
(RAS =CAS = Other Inputs =Vcc -0.2V)
OPERATING CURRENT: EDO PAGE MODE (X version only)
Average power supply current
(RAS =VIL, CAS, Address Cycling: tpc =tpc [MIN])
=tRC [MIN])
REFRESH CURRENT: Extended (S version only)
Average power supply current
CAS =0.2V or CBR cyclig; RAS = tRAS (MIN); WE
OE, AO-A 10 and DIN =Vcc -0.2V or 0.2V
(DIN may be left open); IRC =62.5~s
=Vcc -0.2V;
REFRESH CURRENT: SELF (S version only)
Average power supply current during SELF REFRESH;
CBR cycling with RAS ~ IRASS (MIN) and CAS held LOW;
WE =Vcc -0.2V; OE,AO-A10 and DIN =Vcc -0.2V or 0.2V
(DIN may be left open)
UNITS NOTES
m
~
CAPACITANCE
PARAMETER
MAX
UNITS
Input Capacitance: AO-A 10
CI1
24
pF
17
Input Capacitance: WE
CI2
32
pF
17
Input Capacitance: RASO
CI3
32
pF
17
Input Capacitance: CASO-CAS3
CI4
10
pF
17
Input/Output Capacitance: D01-D032
Clo
10
pF
17
MT4LD232(X)(S)
DM36.pm5 - Rev. 2/95
SYMBOL
4-105
z
NOTES
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
C
::rJ
»
s:
en
s:
s:
ADVANCE
MICRON
F·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
m~"'oo""
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vee
z
m
~
III
=+3.3V ±O.3V)
-6
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
SYM
tAA
MIN
tAR
50
0
0
55
tASC
Column-address to WE delay time
tASR
tAWD
c
Access time from CAS
Column-address hold time
tCAC
tCAH
»
s:
CJ)
-s:
s:
C,A,S pulse width
teAs
RAS lOW to "don't care" during SELF REFRESH cycle
tCHD
CAS hold time (CBR REFRESH)
CAS to output in low-Z
CAS precharge time
tCHR
tClZ
tcp
::D
Access time from CAS precharge
tCPA
CAS to RAS precharge time
tCRP
CAS hold time
CAS setup time (CBR REFRESH)
tCSH
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable Time
OE hold time from WE during READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OE setup prior to RAS during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
tCSR
tCWD
tCWL
tDH
tDHR
tDS
tOD
tOFF
tORD
tpc
tpRWC
tRAC
RAS to column-address delay time
tRAD
Row-address hold time
tRAH
MT4LD232{X)(S)
DM36.pmS - Rev. 2195
4-106
MIN
30
10
i5
15
15
3
10
55
0
0
60
10,000
15
20
15
15
3
10
15
3
0
35
85
15
10
15
15
15
60
30
15
3
0
40
95
15
10
NOTES
ns
ns
ns
ns
29
9
ns
10,000
ns
ns
ns
ns
ns
40
5
70
5
45
20
15
55
0
3
UNITS
ns
ns
20
35
5
60
5
40
15
10
45
0
3
MAX
35
15
tOE
tOEH
-7
MAX
27
19
24
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
ns
ns
19
29
15
15
24
21
ns
20
ns
ns
12,24,31
12
ns
70
35
ns
ns
ns
8
23
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
"'""oco"''",
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vee = +3.3V ±0.3V)
-7
-6
AC CHARACTERISTICS - FAST PAGE MOOE OPTION
PARAMETER
SYM
MIN
Column-address to RAS lead time
tRAL
30
RAS pulse width
tRAS
MAX
MIN
MAX
60
10,000
35
70
10,000
ns
tRASP
60
100,000
70
100,000
ns
tRASS
tRC
100
110
100
~s
27
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
tRCD
20
130
20
50
ns
ns
13
tRCH
0
0
ns
14
Read command setup time
tRCS
0
0
ns
Refresh period (2,048 cycles)
tREF
Refresh period (2,048 cycles) S version
RAS precharge time
tREF
tRP
RAS to CAS precharge time
tRPC
RAS precharge time during SELF REFRESH cycle
Read command hold time (referenced to RAS)
tRPS
tRRH
RAS hold time
RAS pulse width (FAST PAGE MODE)
RAS pulse width during SELF REFRESH cycle
45
NOTES
128
ms
ms
...
50
0
110
0
130
ns
ns
ns
27
0
ns
14
tRSH
0
15
20
ns
READ WRITE cycle time
RAS to WE delay time
tRWC
tRWD
150
85
180
ns
ns
Write command to RAS lead time
Transition time (rise or fall)
tRWL
tT
15
50
3
15
50
Write command hold time
tWCH
Write command hold time (referenced to RAS)
tWCR
45
55
ns
WE command setup time
Write command pulse width
twcs
twp
0
10
ns
ns
WE pulse width for output disable when CAS HIGH
10
WE hold time (CBR REFRESH)
WPZ
tWRH
0
15
10
10
10
ns
WE setup time (CBR REFRESH)
tWRP
10
10
ns
MT4LD232(X)(S)
DM36.pmS - Rev. 2/95
4-107
c
JJ
l>
en
-s:
s:
29
ns
ns
3
10
•
S
40
95
20
z
m
:e
ns
32
32
128
UNITS
ns
29
ns
28
28
Micron Technology, Inc., reserves the right to change products or specifications 'without nolic1'i.
©1995, Micron Technolog"y, Inc.
ADVANCE
MICRON
1-·
MT4LD232(X)(S}
2 MEG x 32 DRAM MODULE
","",CO"""
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vee
z
m
=e
•
c
:D
l>
35:
-35:
en
s:
=+3.3V ±0.3V)
PARAMETER
Access time from column-address
SYM
tAA
MIN
Column-address setup to CAS precharge during WRITE
tACH
15
45
0
0
55
Column-address hold time (referenced to RAS)
tAR
Column-address setup time
Row-address setup time
tASC
Coiumn-address to WE delay time
iAWD
Access time from CAS
Column-address hold time
tCAC
CAS pulse width
RAS LOW to "don't care" during SELF REFRESH cycle
CAS hold time (CSR REFRESH)
CAS to output in Low-Z
Data output hold after CAS LOW
tASR
tCAH
tCAS
tCHD
tCHR
tCLZ
CAS precharge time
'COH
tcp
Access time from CAS precharge
tCPA
CAS to RAS precharge time
'CRP
CAS hold time
CAS setup time (CSR REFRESH)
'CSH
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output Enable Time
OE hold time from WE during READ-MODIFY-WRITE cycle
OE HIGH hold time from CAS HIGH
OE HIGH pulse width
OE LOW to CAS HIGH setup time
'CSR
'CWO
'CWL
'DH
tDHR
'OS
too
'OEHC
tOEP
tOES
tOFF
OE setup prior to RAS during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
tORD
tpc
MT4LD232(X)(S)
DM36.pm5
~
Rev. 2/95
tpRWC
4-108
MAX
MIN
30
10
10
15
10
0
5
10
12
10
10
5
3
0
25
75
UNITS
35
ns
10,000
12
12
15
12
0
5
10
15
15
15
ns
ns
ns
ns
12
10
10
5
3
0
30
85
ns
29
9
ns
10,000
ns
ns
ns
27
19
ns
ns
ns
40
5
55
5
40
15
12
55
0
0
NOTES
ns
20
35
5
50
5
35
15
10
45
0
0
MAX
15
55
0
0
65
15
tOE
'OEH
Output buffer turn-off delay
EDO-PAGE-MODE READ-WRITE cycle time
-7
-6
AC CHARACTERISTICS - EDO PAGE MODE OPTION
18
ns
ns
ns
ns
ns
19
29
ns
15
15
ns
15
ns
ns
15
ns
ns
ns
21
ns
ns
ns
15
ns
12,24,31
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technorogy, Inc.
ADVANCE
MICRON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
",",OW"""
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vee
=+3.3V ±0.3V)
-6
AC CHARACTERISTICS - EDO PAGE MODE OPTION
PARAMETER
Access time from RAS
SYM
tRAC
MIN
RAS to column-address delay time
tRAD
tRAH
12
Row-address hold time
10
Column-address to RAS lead time
IRAL
30
-7
MAX
MIN
MAX
70
UNITS
NOTES
ns
8
35
ns
ns
23
10
35
ns
60
30
RAS pulse width
RAS pulse width (EDO PAGE MODE)
tRAS
60
10,000
tRASP
125,000
RAS pulse width during SELF REFRESH cycle
Random READ or WRITE cycle time
tRASS
IRC
60
100
RAS to CAS delay time
tRCD
14
Read command hold time (referenced to CAS)
IRCH
0
Read command setup time
Refresh period (2,048 cycles)
tRCS
tREF
0
Refresh period (2,048 cycles) S version
RAS precharge time
IREF
tRP
RAS toCAS precharge time
tRPC
12
70
70
10,000
125,000
100
130
110
45
14
ns
ns
~
50
ns
32
32
ns
ns
ms
128
128
ms
0
0
40
50
ns
0
RAS precharge time during SELF REFRESH cycle
IRPS
0
110
130
ns
ns
Read command hold time (referenced to RAS)
RAS hold time
READ WRITE cycle time
tRRH
tRSH
0
10
0
12
ns
ns
tRWC
tRWD
150
177
80
15
90
15
ns
ns
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or fall)
tRWL
IT
Write command hold time
Write command hold time (referenced to RAS)
WE command setup "time
IWCH
Output disable delay from WE (CAS HIGH)
Write command pulse width
tWHZ
tvvCR
IWCS
twp
twpz
2
0
10
tvvRH
10
10
WE setup time (CBR REFRESH)
tvvRP
10
MT4LD232(K)(S)
4-109
2
50
0
12
27
14
29
ns
ns
ns
ns
0
13
13
14
ns
12
55
0
WE pulse width for output disable when CAS HIGH
WE hold time (CBR REFRESH)
DM36.pm5- Rev. 2f95
50
10
45
27
ns
15
29
ns
12
ns
ns
10
10
ns
ns
28
28
Micron Technology, Inc., reserves the right to cllange products or specifications-without notice.
©1995, Micron TecRnology, Iflc.
z
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•
c
::a
»
s
en
s:
-s:
ADVANCE
MICRON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
"''"'''""''c
NOTES
Z
m
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•
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:c
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en
s:
s:
1. All voltages referenced to Vss.
2. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
3. An initial pause of 100/-1s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
4. AC characteristics assume IT = 2.5ns for EDO and 5ns
for FPM.
5. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. Measured with a load equivalent to two TTL gates
and 100pF. Output reference voltages are 0.8V for a
low level and 2.0V for a high level.
8. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
9. Assumes that IRCD ~ IRCD (MAX).
10. If CAS and RAS = VIH, data output is High-Z.
11. If CAS = VIL, data output may contain data from the
last valid READ cycle.
12. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
13. Operation within the IRCD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
14. Either tRCH or IRRH must be satisfied for a READ
cycle.
15. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
16. In addition to meeting the transition rate specification,
all input signals must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
17. This parameter is sampled. Vee = 3.3V ±0.3V;
f= 1 MHz.
18. If CAS is LOW at the falling edge of RAS, data-out
(Q) will be maintained from the previous cycle. To
initiate a new cycle and clear the data-out buffer, CAS
must be pulsed HIGH for ICp.
19. On-chip refresh and address counters are enabled.
MT4LD232{X)(S}
DM36,pm5 - Rev. 2/95
20. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and
OE=HIGH.
21. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
22. Ice is dependent on cycle rates.
23. Operation within the IRAD (MAX) limit ensures that
IRCD (MAX) can be met. lRAD (MAX) is specified as a
reference point only; if IRAD is greater tha~ the
specified IRAD (MAX) limit, then access time is
controlled exclusively by IAA.
24. The 3ns minimum is a parameter guaranteed by
design.
25. Refresh current increases if lRAS is extended beyond
its minimum specification.
26. Column-address changed once each cycle.
27. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
28. twTS andtWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
. mode (with CBR timing constraints). These two
parameters are the inverts of twRP and twRH in the
CBR REFRESH cycle.
29. IWCS, IRWD, IAWD and ICWD are not restrictive
operating parameters. twcs applies to EARLY
WRITE cycles. IRWD, IAWD and ICWD apply to
READ-MODIFY-WRITE cycles. If twcs ~ twcs
(MIN), the cycle is an EARLY WRITE cycle and
the data output will remain an open circuit throughout the entire cycle. If twcs < twcs (MIN) and
IRWD ~ IRWD (MIN), IAWD ~ IAWD (MIN) and
ICWD ~ ICWD (MIN), the cycle is a READ-MODIFYWRITE and the data output will contain data read
from the selected cell. If neither of the above
conditions is met, the state of data-ouf is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. twcs, IRWD, ICWD and IAWD are not
applicable in a LATE WRITE cycle.
30. LATE WRITE and READ-MODIFY-WRITE cycles
must have both IOD and tOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. If OE is
taken back LOW while CAS remains LOW, the DQs
will remain open.
31. The maximum current ratings are based with the
memory operating or being refreshed in the x72
mode. The stated maximums may be reduced by
approximately one-half when used in the x36 mode.
32. Applies to both EDO and FAST PAGE MODEs.
4-110
Micron Technology. Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
"'"",CO"""
READ CYCLE 32
tRAS
V ,H
VIL
RAs
\
leSH
<
'RSH
tCRP
V ,H
VIL
CAS
tRCD
IRAD
tASR
V,H
VIL
.. tWAH_
I.
ROW
'Rcs
1
~
I
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II
I
ifIIlllll/,
'AA
tRAG
NOTE 2
~gt =_------OPEN---:------m~V~AL~ID~DA~TA~--OPEN--
OE
IOE
1_
1_
~:r ==:;'/;=1j/;"'1j/'=1//;7771;jTn1/;j=II/;=;i
,.0'77/1/;TTT1j/;777~/;Tn~=11/;=;;,.0TTTW/;TTTII/;7771j/;7T7;i;;>J,
100
//;=11/;""'[1/;""'11/;=/1/;'11
77/;=11/;=m=11/,T7Tj,.0=11/;=W=1;
EARLY WRITE CYCLE 32
'RC
tRAS
'RP
\
rr:
leSH
J~:
tRCD
'AR
I
'RAD
I~I
I~ ~I
ADDR
~:~
W;,>A
ROW
J@!LJt
I
'1
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f
1
tRAL
I~I
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I
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ROW
ICWL
I
~ ~
NOTE:
I
I
~I
I
I
'RWL
tWCR
I~
'Wp
~
DON'TeARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and twRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
2. 'OFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MT4LD232(X}(S)
DM36.pmS - Rev, 2/95
4-111
•
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ICAC
DQ
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1
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ROW
::1111111111;lNOTE 1
tRAL
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tRAH
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I' twRP
WE
I
- - -p@ill,&i ~.
I'"
V ,H
VIL
m
Y
~I
=~
z
~I
1
tCAS
'AR
ADDR
.I
'RP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
en
s:
s:
ADVANCE
MICRON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
"'"'"c,"""
READ WRITE CYCLE 32
(LATE WRITE and READ-MODiFY-WRITE cycles)
z
tRAS
m
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=1
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-
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ff=
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III
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tACH
~II
IRWD
leWD
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~
IAWD
iCAC
----=---
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----------OPEN---4~~~~x~~j
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~:~ ::'$/##$##$####$#$$$#I$#m1~
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RASP
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j~
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tAR
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ADDR
~i~
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ROW
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I
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~
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~
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'RCS
I
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f------J
f--- -
I~I I~
I I
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tRAC
I
I
I
II
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VALID
OPEN
DATA
I:
~ ~s
tOE
NOTE:
~IJ~I
~I
~
COLUMN
I
!
A-
IRSH
'PC
__
'CP_~
_'_CP_
I
'AA
COLUMN
I
I
1
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I
tePA
'CP
II
I
I
I
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ROW
~
'AA
tePA
'CAG
'c~-T
tCAC
tco~1
t OFF"
'oEHC
m
VALID
DATA
1..'2P..
A
1
VALID
DATA
~
OPEN
I_
'00.1
toES
toEP
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and IWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LD232(X)(S)
DM36.pm5 - Rev. 2195
4-112
Micron Technology, Inc., reserves the right to change products or specffications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII:::r=aCN
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
"'<"'"""'"
FAST-PAGE-MODE READ CYCLE
----------------------'=RAS~P--------------------~I~
z
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•
c
::D
»
S
DO
-ens:
~:g~ ='------OPEN-------~~~D_---~OC~D_---~K~:)
3:
EDO-PAGE-MODE EARLY-WRITE CYCLE
RAs
V,H
V"
-
tCSH
~
CAS
V,H
V"
ADDR
V,H
V"
We
V,H
V"
DO
~lgt
DE
~:t
--
~I
NOTE:
VAllO DATA
1111I/$/$II!/$11//1/1/$I/I#II!II!I/I/II!/III!1//11/$1/1/1/1/1/1/11////II/$#I$llll!1/#1#III/I/II!1/III!
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LD232(X)(S)
DM36.pm5 - Rev. 2/95
4-113
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
"'""'''"''''
FAST-PAGE-MODE EARLY-WRITE CYCLE
_----~:---------------~R~AS~P-------------------I~
RAs ~:~_
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-
ADDR
tCSH
~:~
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!$I1###I1;/"//;/#I//f##;$//////###/#I#/#########&'#hW'###/#///;$;$$/#//$//##;0
EDO/FAST PAGE-MODE READ-WRITE CYCLE 32
(LATE WRITE and READ-MODIFY-WRITE cycles)
-RAS
-~L
VIH _
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RA_sp--;:-:~:::-;;;;;;c:_-----;:=--~I:=J
t
L
---;::c-,-----________
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ADDR
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I
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~,'OOLH -- _________ OPEN~~ALlD ~
VALID
rr::/Y"
JI__
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I
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---
.
_'OD
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0--'00
tJ5lI
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DOUT
---.
DIN
I~
~
I2ZJ DON'T CARE
NOTE:
~
UNDEFINED
1. tpc is for LATE WRITE cycles only.
2. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4L0232(X)(S)
DM36.pm5 - Rev. 2195
4-114
Micron Technology, Inc., reserves the right to change products or specifications without nolice
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
"'""""'"''
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
'RASP
RAS
z
VIHVIL_
tCSH
__~~'P~C1-~____ I_ _ _ _ _'~PC~~_____ II.___'~RS~H___
tCRP
CAS
VIHVIL-
ADDR
~tr-
tRCD
~ 1_-''''CP___ 1 ~ 1_ _ _-"'C"-P____ 11_''''CA'''S_ _ _ 1
m
:E
•
C
:xJ
WE
I~
DO
~igr----------- OPEN -------~{:=~V~Al~ID~DA~TA~IA~)= j '-----"'''=LJ1.
'OE
OE
NOTE:
~:t= WuMI/"$$/"$//"I/;W'h1-.
1. Although WE is a ."don't care" at RAS time during an access Cycie(READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4lD232(X)(S}'
DM36.pmS - Rev. 2/95
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
»
s:
en
s:
s:
ADVANCE
MIC:RON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
Ne"CC'","'
FAST-PAGE-MODE READ-EARL V-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
z
m
tpc I,_-""'Rs,,,-H- I
tCSH
:e
•
C
ADDR
~:~:=
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WE
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-
~:~
1
1
I
1
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~:~ ::'tJ$#//////#/#//#//#/////////$##//#///;/$~' VALID DATA ki$;/$#////////#/d
I,~:.~
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(WE = DON'T CARE)
_
CAS
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ADDR
I
~:t ~~
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-l~_
------"l,------'RPCb-'RP
_'R_AS
~:~ ::~--RO-W---"b/;!/;!//;!$/$/;!///;!/;!/;!/;!/#/$/;!#$hXr--'ASR
,
,'RAH
Ro-w - -
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NOTE:
~
DON'T CARE
~
UNDEFINED
1. Do not drive data prior to tristate.
MT4LD232(X)(S)
OM36.pm5 - Rev. 2/95
4-116
Micron Technology, Inc., reserves the right to change products or specifications wfthout notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
,,,",
DO
~gt - c - - - - - - -
too
'DE
OE
~:t --W;l;/;l///&'//#JJM!1;l#;/U";ld~D
)7i&J;l;//J/
SELF REFRESH CYCLE 32
(Addresses and OE = DON'T CARE)
NOTE 1
::
:::)~ ~~///ffff#//ff///ff/ff///!/I/ff;;,{r~
VOH - .
DQ
WE
VOL
II
.(\-
OPEN·
~II~:.
~:t :W;/mm!
II
~I~
~W;#!I;//;/;/;/II!I!///II!/;//;/;/!I!uJ
~;/1I!/1I!//$4
~
DON'TCARE
m
UNDEFINED
NOTE:
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT4LD232(X)(S)
DM36.pmS - Rev. 2195
4-117
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
s:
en
s:
:s:
ADVANCE
MICRON
1-·
MT4LD232(X)(S)
2 MEG x 32 DRAM MODULE
",",OCOO,,",
CBR REFRESH CYCLE 32
(Addresses and OE = DON'T CARE)
.
Z
RAS
m
RP
.
~ '"~~
=J:'cp:~
=e
•
.1
RAS
• tCHR
CAS
1
tRPC
RP
'CSR
.
tCHR
RAS
'y
Y
-~--
DO
C
::c
»
s:
WE
en
-s:
s:
DO
NOTE:
~gt
--------.
OPEN - - - - - - - - - - 1 V I M ' l < I
~
DON'T CARE
I2l&1
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for 'WRP and 'WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT4LD232{X)(S)
DM36.pm5 - Rev. 2/95
4-118
Micron Technology, Inc., reserves the right to change products or spacrfications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MIC:RON
1-·
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
,,,"",coo,,,,
4 MEG,S MEG x32
DRAM
MODULE
16,32 MEGABYTE, 5V, FAST PAGE
MODE, OPTIONAL SELF REFRESH
FEATURES
PIN ASSIGNMENT (Front View)
• JEDEC- and industry-standard pinout in a 72-pin,
single-in-line memory module (SIMM)
• High-performance CMOS silicon-gate process
• Single 5V ±10% power supply
• All device pins are TTL-compatible
• Low power, 48mW standby; 2,024mW active, typical
(32MB)
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN; optional Extended and SELF REFRESH
• 2,048-cycle refresh distributed across 32ms or
2,048-cycle Extended Refresh distributed across 128ms
• FAST PAGE MODE (FPM) access cycle
• Multiple RAS lines allow x16 or x32 width
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
72-Pin SIMM
(00-7) 4 Meg x 32
(00-8) 8 Meg x 32
~o~QQQ[!lo
PIN # SYMBOL PIN# SYMBOL PIN # SYMBOL PIN # SYMBOL
1
Vss
19
Al0
37
NC
55
0012
0028
2
001
20
005
38
NC
56
0017
21
Vss
57
0013
3
0021
39
002
22
40
58
0029
4
006
"CASO
0018
23
0022
41
CAS2
59
Vee
5
0030
6
003
24
007
42
CAS3
60
0019
25
0023
43
-cAS1
61
0014
7
0031
004
26
008
44
RASa
62
8
45 NC/RJ\Sf* 63
0015
9
0020
27
0024
Vee
28
A7
46
NC
64
0032
10
NC
29
NC
47
WE"
65
0016
11
12
AO
30
Vee
48
NC
66
NC
67
PROl
13
Al
31
A8
49
009
A2
A9
50
0025
68
PR02
14
32
PR03
15
A3
33 NClf!AS3' 51
0010
69
RAS2
52
0026
70
PR04
16
A4
34
A5
NC
53
0011
71
NC
17
35
A6
36
NC
54
0027
72
Vss
18
'32MB version only
-7
• Packages
72-pinSIMM
72-pin SIMM (gold)
M
G
• Refresh
Standard/32ms
SELF REFRESH/128ms
Blank
S
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tpc
tM
tCAC
tRP
-6
-7
110ns
l30ns
60ns
70ns
35ns
40ns
30ns
35ns
l5ns
20ns
40ns
50ns
GENERAL DESCRIPTION
VALID PART NUMBERS
PART NUMBER
DESCRIPTION
MT8D432G-xx
MT8D432G- xx S
MT8D432M-xx
MT8D432M- xx S
MT16D832G-xx
MT16D832G-xx S
MT16D832M-xx
MT16D832M-xx S
4 Meg x 32, Gold
4 Meg x 32, Gold, S..
..S = SELF REFRESH
MT8D432(S). MT.160832(S)
DM44.pm5 - Rev. 2/95
4 Meg
4 Meg
8 Meg
8 Meg
8 Meg
8 Meg
x
x
x
x
x
x
32,
32,
32,
32,
32,
32,
Tin/Lead
Tin/Lead, S ..
Gold
Gold, S'·
Tin/Lead
Tin/Lead, S*·
The MT8D432(S) and MT16D832(S) are randomly accessed 16MB and 32MB solid-state memories organized in
a x32 configuration.
During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits, which are entered 11
bits (AO-AI0) at a time. RAS is used to latch the first 11 bits
and CAS the latter 11 bits. READ and WRITE cycles are
selected with the WE input. A logic HIGH on WE dictates
READ mode while a logic LOW on WE dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by
the falling edge of CAS. Since WE goes LOW prior to CAS
going LOW, the output pin(s) remain open (High-Z) until
the next CAS cycle.
4-119
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technoiogy, Inc.
•
C
:xJ
»
s:
en
s:
s:
PRELIMINARY
MICRON
1-·
MTBD432(S), MT16DB32(S)
4 MEG, B MEG x 32 DRAM MODULES
'""'00"'''''
FAST PAGE MODE
•
o
:::D
»
3:
en
-S
S
FRESH mode is initiated by executing a CBR REFRESH
cycle and holding RAS LOW for the specified tRASS. Additionally, the "S" version allows for an extended refresh rate
of 62.511s per row if using distributed CBR REFRESH. This
refresh rate can be applied during normal operation, as well
as during a standby or extended refresh mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for the time minimum of an operation cycle, typically
tRPS. This delay allows for the completion of any internal
refresh cycles that may be in process at the time of the
RAS LOW-to-HIGH transition. If the DRAM controller uses
a distributed CBR REFRESH sequence, a burst refresh is not
required upon exiting SELF REFRESH mode. However, if
the DRAM controller utilizes RAS ONLY or burst refresh
sequence, all 2,048 rows must be refreshed within 300l1s
prior to the resumption of normal operation.
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined
page boundary. The FAST PAGE MODE cycle is always
initiated with a row-address strobed-in by RAS followed by
a column-address strobed-in by CAS. CAS may be toggledin by holding RAS LOW and strobing-in different columnaddresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the FAST PAGE MODE operation.
REFRESH
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cvcle durin!! the
RAS HIGH tim~. Memory cell data is retain~d in its co~rect
state by maintaining power and executing any
RAS cycle (READ, WRITE) or RAS refresh cycle (RAS
ONLY, CBR or HIDDEN) so that all 2,048 combinations of
RAS addresses are executed at least every 32ms, regardless
of sequence. The CBR REFRESH cycle will invoke the
refresh counter for automatic RAS addressing.
An additional SELF REFRESH mode is also available.
The "S" version allows the user the option of a fully static
low power data retention mode, or a dynamic refresh mode
at the extended refresh period. The module's SELF RE-
x16 CONFIGURA nON
For x16 applications, the corresponding DQ and CAS
pins must be connected together (DQ1 to DQ17, DQ2 to
DQ18 and so forth, and CASO to CAS2 and CAS1 to
CAS3). Each RAS is then a bank select for the x16 memory
organization.
FUNCTIONAL BLOCK DIAGRAM
MT8D432 (16MB)
DOl .......................... D08
tttt
001-4
WE
CASQ
- + - - - 1 CAS
RASO
--+----1
CAS1
--+-----1
t tt t
OQl-4
WE
U1
U2
CAS
009 ........................ ·0016
tt t t
DQl -4
WE
tttt
OQ1-4
WE
U3
U4
CAS
CAS
WE
0017 ....................... 0024
t tt t
OQ1-4
L-----1WE
CAS2
- - - - - I CAS
RAS2
-----1
t!! t
DQl-4
WE
0025 •...................... ·0032
t tt t
001-4
WE
U7
U5
CAS
t tt t
001-4
WE
U'
CAS
RAS
DE
CAS3-----AO-Al0 • • • • • •
Ul·U8 = 4 Meg x 4 DRAMs
MT8D432(S), MT16D832(S)
DM44.pm5 - Rev. 2195
4-120
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
""""CO,,,",
FUNCTIONAL BLOCK DIAGRAM
MT16D832 (32MB)
001 .------------------------- OOB
DQ1-4
.-----1iNE
DOg ---------------------.--- 0016
D01-4
/-----\iNE
U1
U2
U3
U4
CASO --f---..------l CAS
/-----\CAS
CAS
f - - - - - - l CAS
RASO - - l - + - - - - - - l RAS
/-----iRAS
/ - - - - f - - - - - - l RAS
f - - - - - - l RAS
0017 ----------------------- D024
WE CAS2
RAS2
0025·-------------------·--- D032
-
S
s:
DOg --------------------.---- D016
un
0017
---------------------,- 0024
f-----iiNE
U12
/--------lCAS
0025·------------------·---- 0032
DQ1-4
iNE
U13
-t-------1
-----liNE
U14
U15
U16
CAS
CAS
CAS
f--------1 CAS
RAS
RAS
-If-------1 RAS
f--------1 RAS
U1-U16 = 4 Meg x 4 DRAMs
MT8D432{S). MT16D832(S)
DM44.pm5 - Re\!. 2195
l>
S
en
......# - - - - - - l
--..-t-H------j
--+t-H------j
001 .------------------------- DOB
RAS3
•
C
:IJ
CAS1 - - l f f l - - - - -
4-121
Micron Technology, Inc., reserves the righllochange products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
"'"",'00""'
TRUTH TABLE
FUNCTION
Standby
•
C
JJ
»
S
en
S
ID{S
cg
WE
H
H~X
X
ADDRESSES
tR
te
X
DATA-IN/OUT
001-0032
X
High-Z
Data-Out
READ
L
L
H
ROW
COL
EARLY WRITE
L
L
L
ROW
COL
Data-In
ROW
COL
Data-Out
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H~L
H
READ
2nd Cycle
L
H~L
H
n/a
COL
FAST-PAGE-MODE
1st Cycle
L
H~L
L
ROW
COL
Data-In
WRITE
2nd Cycle
L
H~L
L
n/a
COL
Data-In
L
n
LJ
X
ROW
n/a
High-Z
H
ROW
COL
Data-Out
RAS-ONLY REFRESH
HIDDEN
READ
L~H~L
L
REFRESH
WRITE
L~H~L
L
L
ROW
COL
Data-In
CSR REFRESH
H~L
L
H
X
X
High-Z
SELF REFRESH (S version)
H~L
L
H
X
X
High-Z
S
JEDEC DEFINED
PRESENCE-DETECT - MT8D432 (16MB)
SYMBOL
PRD1
PRD2
PRD3
PRD4
PIN#
-6
-7
67
68
69
70
Vss
Vss
NC
NC
NC
Vss
NC
NC
JEDEC DEFINED
PRESENCE-DETECT - MT16D832 (32MB)
SYMBOL
PRD1
PRD2
PRD3
PRD4
MTBD432(S), MTI6D832(S)
DM44.pm5 - Rev. 2195
PIN#
-6
-7
67
68
69
70
NC
NC
Vss
Vss
NC
Vss
NC
NC
4-122
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
",'"",co",,",
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Vss .................... -IV to +7V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ............................................................. 8W
Short Circuit Output Current ...................................... 50mA
*Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability .
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vee
=+5V ±1 0%)
C
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
5.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
INPUT LEAKAGE CURRENT
RASO-RAS3
111
-8
8
IlA
Any input OV :'> VIN :'> 5.5V
AO-A10, WE
112
-32
32
!lA
!lA
!lA
(All other pins not under test
= OV) for each package input
OUTPUT LEAKAGE CURRENT
(0 is disabled; OV :'> VOUT :'> 5.5V) for each package input
CASO-CAS3
113
-8
8
001-0032
loz
-20
20
VOH
2.4
OUTPUT LEVELS
Output High Voltage (lOUT = -5mA)
Output Low Voltage (lOUT =4.2mA)
MT8D432{S), MT16D832(S)
DM44.pm5 - Rev. 2195
•
VOL
4~123
NOTES
»
s:
en
28
28
28
V
0.4
::tJ
V
Micron Technology, Inc., reserves the fight to change products or specifications without notice.
©1995, Micron Technology, Inc.
-s:
s:
PRELIMINARY
MICRON
1-·
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
"""''coo,,",
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1,6,7) (Vcc
=+5V ±10%)
MAX
SYMBOL
SIZE
-6
-7
UNITS
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
Icct
16MB
32MB
26
52
26
52
mA
STANDBY CURRENT: (CMOS)
(RAS = CAS =Other Inputs =Vcc -0.2V)
Icc2
16MB
32MB
Icc2
16MB
(S only) 32MB
14
28
12
24
14
28
12
24
mA
PARAMETER/CONDITION
•
NOTES
mA
C
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC =IRC [MIN])
ICC3
16MB
32MB
960
986
800
826
mA
3,4,
26
»
s:
OPERATiNG CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC =IpC [MIN])
Icc4
16MB
32MB
720
746
640
666
mA
3,4,
26
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC =IRC [MIN])
Icc5
16MB
32MB
960
986
800
826
mA
3,26
Icc6
16MB
32MB
960
986
800
826
mA
3,5
Icc?
16MB
(S only) 32MB
2.4
4.8
2.4
4.8
mA
3,5
Icc8
16MB
(S only) 32MB
2.4
4.8
2.4
4.8
mA
5,27
::xJ
-s:
en
s:
REFRESHCURREN~CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC
=IRC [MIN])
REFRESH CURRENT: Extended (S version only)
Average power supply current
CAS =O.2V or CBR cycling; RAS =IRAS (MIN); WE
AO-A10 and DIN = Vcc -0.2V or 0.2V
(DIN may be left open); IRC =62.51-1s
=0.2V;
REFRESH CURRENT: SELF (S version only)
Average power supply current during SELF REFRESH
CBR cycling with RAS ;:: IRASS (MIN) and CAS held LOW;
WE =Vcc -0.2V; AO-A 10 and DIN =Vcc -0.2V or 0.2V
(DIN may be left open)
MT8D432(Sj, MT16D832(S)
DM44.pmS - Rev. 2/95
4-124
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
e~",c,
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
CAPACITANCE
MAX
SYMBOL 16MB 32MB
PARAMETER
UNITS
NOTES
Input Capacitanoe: AO-A10
CI1
48
95
pF
2
Input Capacitance: WE
CI2
64
127
pF
2
Input Capacitance: RASO, RAS1, RAS2, RAS3
CI3
32
32
pF
2
Input Capacitance: CASO, CAS1, CAS2, CAS3
CI4
16
32
pF
Input/OutPutCapacitance: 001-0032
CI01
10
16
pF
2
2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
.:
Access time from column-address
Column-address hold time (referenced to RAS)
NOTES
15
3:
SYM
tAR
IASC
Rdw-address setup time
tASR
AcCess time from CAS
'CAC
Column-address hold time
CAS pulse width
'CAH
ICAS
RAS LOW to "don't care" during SELF REFRESH cycle
'CHO
CAS hold time (CSR REFRESH)
'CHR
tCLl
'CP
Access time from CAS precharge
CAS to RAS precharge time
'CPA
ICRP
CAS hold time
ICSH
CAS setup time (CSR REFRESH)
Write command to CAS lead time
Data-in hold time
'CSR
tCWL
tDH
Data-in hold time (referenced to RAS)
tDHR
Data-in setup time
Output buffer turn-off delay
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS 10 column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
RAS pulse width during SELF REFRESH cycle
Random READ or WRITE cycle time
MT8D432(S). MT160882(S)
DM44'.pm5 -Rev. 2/95
MIN
IAA
Column-address1letup time
CASto output in Low-Z
CAS precharge time
-7
-6
50
0
0
nla
tRAH
tRAL
IRAS
tRASP
tRASS
tRC
4-125
15
10
30
60
60
100
110
UNITS
35
ns
ns
10,000
15
ns
20
15
20
15
15
3
10
35
tpRWC
MAX
55
0
0
15
10
15
15
15
3
10
toFF
tpc
tRAC
tRAD
MIN
30
5
60
5
15
10
45
0
3
35
tos
MAX
ns
10,060
ns
ns
10,000
100;000
15
10
35
70
70
100
130
ns
ns
ns
27
5
25
. . 16
ns
ns
5
ns
20
ns
ns
21
ns
ns
21
20,25
ns
n/a
60
30
ns
ns
40
5
70
5
20
15
55
0
3
40
ns
ns
70
35
ns
ns
ns
22
14
18
ns
ns
10,000
100,000
ns
ns
IJS
C
:%J
»
s:
(Notes: 6, 7, 8, 9,10,11,12,13) 01cc =+5V ±10%)
AC CHARACTERISTICS
PARAMETER
•
27
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
en
s:
PRELIMINARY
UII:::I=ICN
1-·
,
,n
''"
MTBD432(S), MT16DB32(S)
4 MEG, B MEG x 32 DRAM MODULES
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (VQc=+5V±10%)
AC CHARACTERISTICS
PARAMETER
•
C
::D
»
s:
en
-s:
s:
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (2,048 cycles)
Refresh period (2,048 cycles) S version
RAS precharge time
RAS to CAS precharge time
RAS precharge time during SELF REFRESH cycle
Read command hold time (referenced to RAS)
RAS hold time
READ WRITE cycle lime
Write command to RAS lead time
Transition time (rise or fall)
MIN
MAX
MIN
MAX
UNITS
NOTES
'RCD
'RCH
'RCS
'REF
'REF
'RP
'RPC
'RPS
tRRH
20
0
0
45
20
0
0
50
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
19
'RSH
'RWC
'RWL
IT
Write command hold time
'WCH
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
'WCR
'YVCS
'WP
'WRH
'WRP
MT8D432(S), MT16p832(S)
DM44.pm5 ~ Rev. 2195
·7
·6
SYM
4-126
32
128
32
128
40
0
110
0
15
nfa
15
3
10
45
0
10
10
10
50
50
0
130
0
20
nfa
20
3
15
55
0
15
10
10
50
ns
ns
ns
ns
ns
27
19
22
24
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995,MiCl'OllTechnology,lnc.
PRELIMINARY
UII:::RCN
1-·
"'""'"'"''"'
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
NOTES
1. All voltages referenced to Vss.
2. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 3012.1 (1 MHz AC,
Vee = 5V, DC bias = 2.4V at 15mV RMS).
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100~s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume IT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VTH).
10. In addition to meeting the transition rate specification,
all input signals must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD;::: IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICP.
MT8D432(S), MT16D832(S)
DM44.pmS - Rev. 2/95
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
18. Operation within the lRAD (MAX) limit ensures that
IRCD (MAX) can be met. lRAD (MAX) is specified as a
reference point only; if lRAD is greater than the specified lRAD (MAX) limit, then access time is controlled
exclusively by IAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
22. OE is tied permanently LOW; LATE WRITE or READMODIFY-WRITE operations are not permissible and
should not be attempted.
23. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE = LOW and
OE=HIGH.
24. twTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of twRP and twRH in the
CBR REFRESH cycle.
25. The 3ns minimum is a parameter guaranteed by
design.
26. Column-address changed once each cycle.
27. Refresh must be completed within the time of three
external refresh rate periods prior to active use of the
DRAM (provided distributed CBR REFRESH is used
when in the active mode). Alternatively, a complete
set of row refreshes must be executed when exiting
SELF REFRESH prior to active use of the DRAM if
anything other than distributed CBR REFRESH is
used in the active mode.
28. 16MB module values will be half of those shown.
4-127
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
C
JJ
........
",.
S
CJ)
-
S
,
:::::.
PRELIMINARY
MICRON
1-·
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
"';,'"w"""
READ CYCLE
iRAS
'RP
'I
\
tCSH
I_
teRP
•
C
lJ
tRCD
•
I,
'ASH
~1
'AR
'Ii - l
'RAD
I
'ASR
'
'AAH
1
1
--I
AOW
~
~
ADDR
~
~:t =f$@'/§/$/$&W§ff~
l>
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en
s:
_
'Ase
I 'Aes
1
I
~
1
:~
IRRH
tCAS
tRAL
1
I
I 'eAH
1-
o///////////////////////i?J(
COLUMN
,I
1
'AeH
I
tRAG
~
W#$##/////#4
i--_----+-'=-AA_ _I
I--
AOW
I
I~L
IOFF'
1
DO
s:
~:gr =_-------OPEN-------~'fi'l::NK~V~AL~ID~DA~TA=:}---OPEN---
EARLY WRITE CYCLE
'Re
tRAS
RAS
VIH VIL
_
tCSH
teAP
CAS
ADDA
IRCD
VIH-J
VIL _
V,H
Vrl _
:
tRAD
AOW
ROW
1
twcs
WE
VIH VIL
,I
I
'RWL
I
tweA
1
IWp
tWCH
I
Ilrn".~
~)
I_'D_H_
DO
MT8D432(S), MTI6D832(S)
DM44.pmS - Rev. 2195
~:gt ~
VALID DATA
4-128
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
,
c
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
c
FAST-PAGE-MODE READ CYCLE
'ReD
•
C
::D
l>
s::
DC
~:g~ =:-----OPEN--~--,----'-...;~K~D--_i~(j~~--1~C~)
OPEN--
FAST-PAGE-MODE EARLY-WRITE CYCLE
~
DON'T CARE
IQ28 UNDEFINED
MT8D432(S), MT1~(S)
DM44.pm5 - Rev. 2195
4-129
Micron Technology, Inc., reserves the right to cilange products or specifications without notice.
@1995, Mk:ron Technology. Inc.
en
-s:
s:
PRELIMINARY
MICRON
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
'CC~"OCOC,,"
1-·
RAS-ONl Y REFRESH CYCLE
(WE = DON'T CARE)
_
•
CAS
:~
VV'H
'~II'---'
_
C
DO
JJ
'AP
/
l_
_::-~---:Ir------iT----------+---r-----
IL~~
IASA
AOOA
-~,tb
_IAAS
,
,IAAH
~:t =~"'---AO-W---,'b//#/#/#$#$/#$$$$I###mc=A_OW_ _
~gt ~
»
s:
en
s:
s:
OPEN----------
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
tCSH
~.
ADDR
~]r
tRCD
::
COLUMN
COLUMN
I
1_----i--"A""'eSc.-.
WE
~IHIL -
o
~:t
I
I
I
I
I
II
leWL
II
II
'WP
tAWL
~II~
~"--'-c-~----,"-SII_-,----'OH
LLLLLLLLLULLLLLL..UCLLLL
---ILl
4$//ffi.1I!$//////////111$//;.WIIIII#/;.1#!I!//1//It
I;~~:e
, I:mT
VALID DATA
iW'7T7W/;77T11/;77TiW'7T7o/l/;77T;J/;77Tij/ ;77T;1;2
NOTE 1
Q
~gr =.-----;--OPEN---;-------iXlll.
I,
NOTE:
!-----OPEN_-~-
tZ] DON'T CARE
!l22I UNDEFINED
1. Do not drive data prior to tristate.
MTBD432(S), MTI6D832(S)
DM44.pmS - Rev. 2/95
4-130
Micron Technology, Inc., reserves the right to change products or specifications without,notice.
©1995, Micron Technology, Inc
PRELIMINARY
UII:::RCN
1-·
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
","",COO""
CBR REFRESH CYCLE
(Addresses = DON'T CARE)
'AP
tRAS
--1~~
=J,'ep,~
CAS
DQ
'1
L
'WAP
II
'RAS
'APe~~
leHA
-k
OPEN-~II--------
II
-
WE
'eH"
~:r-
'AP
'WRH
'WAP
II
'WAH
~:t $/"$ffffg- -W$ffff/"//W//"$j- -~#//"//"/"//"/"/"$/$$;2
-f-O::::'AeC"::-D-------;::c,,---
CAS
~:r=~
tAR
-s:
(REFRESH)
- :"J'"
C/J
s:
tCHR
~------
'AAD
-'OFF
DQ
===1
~:gt :::::---- OPEN----i~C==~VA~LlD~DAT~A
OPEN-
SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
NOTE:
f0;3
DON'T CARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT8D432(S), MT16D832(S)
DM44.pmS - Rev. 2195
4-131
C
lJ
»
s::
HIDDEN REFRESH CYCLE 23
(WE = HIGH)
(READ)
•
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MII:::RCN
1-·
m~'oco",",
MT8D432(S), MT16D832(S)
4 MEG, 8 MEG x 32 DRAM MODULES
•
c
::c
»
s:
-ens:
s:
MT8D432(S), "'1160832(5)
DM44.pm5 - Rev. 2/95
4-132
Micron Technology, Inc., reserves the rlght to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
"'""'"''''
4 MEG, 8 MEG x 32
DRAM
MODULE
16,32 MEGABYTE, 3.3V, OPTIONAL SELF
REFRESH, FAST PAGE OR EDO PAGE
MODE
FEATURES
PIN ASSIGNMENT (Front View)
72-Pin SIMM
• JEDEC-standard pinout in a 72-pin single-in"line
memory module (SIMM)
• High-performance CMOS silicon-gate process
• Single +3.3V ±O.3V power supply
• All device pins are TTL-compatible
• Low power, 16mWstandby; 1,408mW active, typical
(32MB)
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN; optional Extended and SELF REFRESH
• 2,048-cycle refresh distributed across 32ms or
2,048-cycle Extended Refresh distributed across 128ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• 5V tolerant II as (5.5V maximum VIH level)
• 3.3V mechanical key
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
(00-16) 4 Meg x 32, (00-17) 8 Meg x 32
\o~11Q~L J!!]gol
PIN# SYMBOL
1
Vss
2
001
3
0017
4
D02
0018
5
6
003
0019
7
8
004
9
0020
10
Vee
P05
11
12
AD
13
A1
14
A2
15
A3
16
A4
17
A5
18
A6
'32MB version only
-7
• Packages
72-pinSIMM
72-pin SIMM (gold)
M
G
• Refresh
Standard/32ms
SELF REFRESH/128ms
Blank
S
• Access Cycle
FAST PAGE MODE
EDO PAGE MODE
Blank
X
SYMBOL
AID
005
0021
006
0022
007
0023
008
0024
A7
NG
Vee
A8
A9
NG
NG
NG
NG
PINt
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
SYMBOL
NG
NG
Vss
rASlJ
CIi~2
CAS3
CIiSl
rii'iSO
ro\"ST'
DE
WE
PO EGG
009
OQ25
0010
0026
0011
0027
PIN # SYMBOL
55
0012
56
0028
57
0013
58
0029
59
Vee
60
1J030
61
DOH
62
0031
63
0015
64
0032
65
0016
66
PO EOD
67
P01
P02
68
69
P03
P04
70
71
PO refresh
72
Vss
VALID PART NUMBERS
KEY TIMING PARAMETERS
SPEED
IRC
tRAC
tpc
tAA
tCAC
tCAS
-6
-7
110ns
130ns
60ns
70ns
25ns
30ns
30ns
35ns
15ns
20ns
10ns
12ns
FPM option
SPEED
tRC
tRAC
tpc
tAA
tCAC
tRP
-6
-7
110ns
60ns
70ns
35ns
40ns
30ns
35ns
15ns
20ns
40ns
50ns
PART NUMBER
DESCRIPTIOK
MT8LD432G-xx X
4 Meg x 32 EDO, SOJ, Gold
4 Meg x 32 EDO, S*', SOJ, Gold
4 Meg x 32 EDO, SOJ, Tin/Lead
4 Meg x 32 EDO, S*', SOJ, Tin/Lead
4 Meg x 32 FPM, SOJ, Gold
4 Meg x 32 FPM, S", SOJ, Gold
4 Meg x 32 FPM, SOJ, Tin/Lead
4 Meg x 32 FPM, S", SOJ, Tin/Lead
8 Meg x 32 EDO, SOJ, Gold
8 Meg x 32 EDO, S", SOJ, Gold
8 Meg x 32 EDO, SOJ, Tin/Lead
8 Meg x 32 EDO, S", SOJ, Tin/Lead
8 Meg x 32 FPM, SOJ, Gold
8 Meg x 32 FPM, S*', SOJ, Gold
8 Meg x 32 FPM, SOJ, Tin/Lead
8 Meg x 32 FPM, S*', SOJ, Tin/Lead
MT8LD432G-xx XS
MT8LD432M-xx X
MT8LD432M-xx XS
MT8LD432G-xx
MT8LD432G-xx S
MT8LD432M-xx
MT8LD432M-xx S
MT16LD832G-xx X
MT16LD832G-xx XS
MT16LD832M-xx X
MT16LD832M-xx XS
MT16LD832G-xx
MT16LD832G-xx S
MT16LD832M-xx
MT16LD832M-xx S
EOO option
130ns
PIN #
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
"S = SELF REFRESH
MT8lD432(X)(S), MT16lD832(X}(S)
DM37.pmS - Rev. 2195
4-133
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
C
JJ
l>
s:
en
-3:
s::
ADVANCE
I'llIC:1=1CN
"'""0W","'
MTBLD432(X)(S), MT16LDB32(X)(S)
4 MEG, B MEG x 32 DRAM MODULE
GENERAL DESCRIPTION
III
c
JJ
»
3:
en
s:
s:
The MT8LD432 (X)(S) and MT16LD832 (X)(S) are randomly accessed 16MB and 32MB solid-state memories organized in a x32 configuration with optional SELF REFRESH. They are specially processed to operate from 3.0V
to 3.6V for low voltage memory systems.
During READ or WRITE cycles each bit is uniquely addressed through the address bits, RAS latches the first 11
bits and CAS latches the latter 11 bits. READ and WRITE
cycles are selected with the WE input. A logic HIGH on
WE dictates READ mode while a logic LOW on WE dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of WE or CAS, whichever occurs last.
EARLY WRITE occurs when WE goes LOW prior to CII..S
going LOW, the output pines) remain open (High-Z) until
the next CAS cycle.
If WE goes LOW after CAS goes LOW, data-out (Q) is
activated and retains the selected cell data as long as OE
remains LOW and RAS and CAS remains LOW (regardless
of WE). This late WE pulse results in a READ WRITE cycle.
If WE toggles LOW after CAS goes back HIGH, the output
pins will open (High-Z) until the next CAS cycle, regardless
ofOE.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-ad dress-defined page
boundary. The FAST PAGE MODE cycle is always initiated
with a row-address strobed-in by RAS followed by a column-address strobed-in by CAS. CAS may be toggled-in by
holding RAS LOW and strobing-in different column-addresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the FAST PAGE MODE operation.
EDO PAGE MODE
EDO PAGE MODE, deSignated by the "X" option, is an
accelerated FAST PAGE MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS
goes back HIGH. EDO provides for CAS precharge time
(ICP) to occur without the output data going invalid. This
elimination of CAS output control provides for pipeline
READs.
FAST PAGE MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS. EDO operates as any DRAM READ or FAST-PAGE-
MT8LD432(X)(S), MTI6LD832(X)(S)
DM37.pm5 ~ Rev. 2/95
MODE READ, except data will be held valid after CAS
goes HIGH, as long as RAS and OE are held LOW and WE
is held HIGH. OE can be brought LOW or HIGH while
CAS and RAS are LOW, and the DQs will transition between valid data and High-Z (reference the MT4LC4M4E8(S)
DRAM data sheet for additional information on EDO
functionality).
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS cycle (READ, WRITE) or RAS
refresh cycle (RAS ONLY, CBR or HIDDEN) so that all 2,048
combinations of RAS addresses are executed at least every
32ms (l28ms on "S" version), regardless of sequence. The
CBR and SELF REFRESH cycles will invoke the internal
refresh counter for automatic RAS addressing.
An optional SELF REFRESH mode is also available. The
"S" version allows the user the option of a fully static low
power data retention mode, or a dynamic refresh mode at the
extended refresh period of 128ms. The module's SELF REFRESH mode is initiated by executing a CBR REFRESH cycle
and holding RAS LOW for the specified lRASS. Additionally,
the "S" version allows for an extended refresh period of
62.5fls per row if using distributed CBR REFRESH. This
refresh rate can be applied during normal operation, as well
as during a standby or extended refresh mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for the time minimum IRPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the RAS LOW-to-HIGH transition. If
the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all 2,048 rows must
be refreshed 300flS, prior to the resumption of normal
operation.
STANDBY
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS HIGH time.
4-134
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
""'""00'"'
FUNCTIONAL BLOCK DIAGRAM
MT8LD432 (16MB)
DQ9 -------------------------DQ16
DQ1 .------------------------- DQ8
DQ1-4
WE
WE
DQ1-4
DQ1-4
t------iWE
f------iWE
WE
U1
DQ1-4
U3
U5
U7
CASO
CAS
CAS
.-----1 CAS
t - - - - - - i CAS
RASO
RAS
RAS
I-----if-----; RAS
f - - - - - - i RAS
»
s:
CAS1
DQ25 .----------------------- DQ32
DQ1-4
--l--H CAS
RAS
U2
1 - - - - - ; CAS
----iWE
i-----iWE
U4
f----iRAS
U6
U8
,-----1 CAS
i-----iCAS
-I----iRAS
i-----iRAS
CAS3
AO-A10
1 Meg x 32 EDO PAGE MODE
U1-U8 = MT4LC4M4E8DJ(S)
1 Meg x 32 FAST PAGE MODE
U1-U8 = MT4LC4M4B1DJ(S)
NOTE:
1. See package drawing for U1-U8 placement locations.
2. OE must be tied to Vss if not required.
MT8LD432(X)(S}, MT16L0832(X)(S}
DM37.pm5 - Rev. 2/95
-sen:
s:
DQ1-4
f----iWE
WE
CAS2
•
C
:0
OE
4-135
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
"'~"'oo,,"
FUNCTIONAL BLOCK DIAGRAM
MT16LD832 (32MB)
001 ··························008
DOg ·························0016
t ! t!
tttt
DOl-4
WE
!t!t
OQl-4
WE
U1
II
c
DQl-4
DOl-4
WE
WE
U3
! t!!
U5
U7
CASO --~-+-.., CAS
CAS
CAS
CAS
RASO
---+<~.., RAS
RAS
RAS
RAS
CAS1
--t++t-t--=
::D
l>
s:
en
-
0017 ·······················0024
0025························0032
tt!t
t t! t
DQ1-4
WE
s:
s:
CAS2
-....-,H-H--I.., CAS
DQ1-4
WE
WE
CAS
RAS
tttt
DOl-4
WE
UB
UB
CAS
CAS
RAS
RAS
001··························008
DOg ·························0016
! ttt
ttt t
DOl-4
WE
t! tt
DOl-4
WE
U16
RAS1
OQl-4
U,
U2
RAS
WE
tt!!
DQl -4
001-4
WE
WE
U14
ttt t
U12
U10
CAS
CAS
CAS
CAS
RAS
RAS
RAS
RAS
DE
0017 ·······················0024
0025························0032
tttt
! tt t
001-4
WE
t tt t
001-4
WE
U15
DQ1-4
001-4
WE
WE
U13
! t! t
Ull
U9
CAS
CAS
CAS
CAS
RAS
RAS
RAS
RAS
1
AO-AlO • • • • •
8 Meg x 32 EOO PAGE MODE
U1·U16 = MT4LC4M4E80J(S)
NOTE:
1. See package drawing for U 1-U 16 placement locations.
2. OE must be tied to Vss if not required.
MT8LD432(X)(S), MT16LD832{XXS)
DM37.pm5 ~ Rev. 2/95
4-136
8 Meg x 32 FAST PAGE MODE
U1·U16 = MT4LC4M4B1DJ(S)
Micron Technology, Inc., reserves the nghtto change products or specifica!ions Wllhout noUc 6.
©1995,MicronTechnology, Inc.
ADVANCE
MICRON
1-·
","",c"ne
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
PRESENCE-DETECT TRUTH TABLE
•
c
::c
-+----N!I'I''*'
»
s
en
-s:
3:
Refresh Delecl
Fast Page Mode/EDO Detect
ECC/Parity Detect
NOTE: Vss = ground.
'This addressing includes a redundant address to allow mixing 12/10 and 11/11 DRAMs. The modules in this data sheet use
11/11 DRAMs.
MT8LD432{X)(S), MT16LD832(X)(S)
DM37.pmS - Rev. 2/95
4-137
Micron Technology, Inc., reserves the right to change products or speCifications without notice.
©1995,MlcrOT1Technology, Inc.
ADVANCE
MICRON
1-·
MTSLD432(X)(S), MT16LDS32(X)(S)
4 MEG, S MEG x 32 DRAM MODULE
"'""co",'"'
'Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee Pin Relative to Vss ................. -IV to +4.6V
Voltage on Inputs or I/O Pins
Relative to Vss .................................................... -I V to +5.5V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ............................................................. 8W
Short Circuit Output Current ..................................... 50mA
III
TRUTH TABLE
c
FUNCTION
RAS
CAS
»
Standby
H
READ
L
EARLY WRITE
L
L
READ WRITE
L
L
:xJ
3:
-ens:
s:
ADDRESSES
IR
IC
DATA-IN!OUT
001-0032
WE
Of
H~X
X
X
X
X
High-Z
L
H
L
ROW
COL
Data-Out
L
X
ROW
COL
Data-In
H~L
L~H
ROW
COL
Data-Out, Data-In
EDO/FAST-PAGE-MODE
1st Cycle
L
H~L
H
L
ROW
COL
Data-Out
READ
2nd Cycle
L
H~L
H
L
n/a
COL
Data-Out
EDO/FAST-PAGE-MODE
1st Cycle
L
H~L
L
X
ROW
COL
Data-In
EARLY WRITE
2nd Cycle
L
H~L
L
X
n/a
COL
Data-In
EDO/FAST-PAGE-MODE
1st Cycle
L
H~L
H~L
L~H
ROW
COL
Data-Out, Data-In
L
H~L
H~L
L~H
n/a
COL
Data-Out, Data-In
L
H
X
X
ROW
n/a
High-Z
H
L
ROW
COL
Data-Out
READ-WRITE
2nd Cycle
RAS-ONLY REFRESH
HIDDEN
READ
L~H~L
L
REFRESH
WRITE
L~H--+L
L
L
X
ROW
COL
Data-In
CSR REFRESH
H--+L
L
H
X
X
X
High-Z
SELF REFRESH (S version)
H~L
L
H
X
X
X
High-Z
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 2, 3, 6, 22) (Vee = +3.3V ±0.3V)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
PARAMETER/CONDITION
Vee
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5
V
Input Low (Logie 0) Voltage, all inputs
VIL
-1.0
0.8
V
INPUT LEAKAGE CURRENT
CASO-CAS3
111
-8
8
Any input OV :s; VIN :s; 5.5V
AO-A9, WE, OE
112
-32
32
J.lA
J.lA
RASO-RAS1
113
-16
16
(.tA
D01-D032
loz
-20
20
J.lA
VOH
2.4
(All other pins not under test
=OV) for eaeh package input
OUTPUT LEAKAGE CURRENT
(0 is disabled; OV:s; VOUT :s; 5.5V) for eaeh package input
TTL OUTPUT LEVELS
MT8LD432(X)(S), MT16LD832(X)(S)
DM37.pm5 - Rev, 2/95
I High Voltage (lOUT =-2mA)
I Low Voltage (lOUT =2mA)
4-138
VOL
NOTES
32
32
32
V
0.4
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
",",oeo",",
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 6) (Vcc
= +3.3V ±0.3V)
MAX
PARAMETER/CONDITION
-6
.-7
16MB
32MB
16
32
16
32
mA
16MB
32MB
ICC2
16MB
(S only) 32MB
4
8
1.2
2.4
4
8
1.2
2.4
mA
16MB
32MB
960
976
880
896
mA
2,22,
26
16MB
ICC4
32MB
(X only)
880
896
800
816
mA
2,22,
26
720
736
640
656
mA
2,22,
26
SYMBOL SIZE
STANDBY CURRENT: (TTL)
(RAS = CAS = VI H)
ICC1
STANDBY CURRENT: (CMOS)
(RAS =CAS =Other Inputs =Vcc -0.2V)
Icc2
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC =tRC [MIN])
ICC3
OPERATING CURRENT: EDO PAGE MODE (X version only)
Average power supply current
(RAS = VIL, CAS, Address Cycling: tpc = tpc [MIN])
UNITS NOTES
mA
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: tpc =tpc [MIN])
ICG5
16MB
32MB
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: tRC = tRC [MIN])
ICC6
16MB
32MB
960
976
880
896
mA
22,26
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC
Icc?
16MB
32MB
960
976
880
896
mA
22, 19
ICC8
16MB
(S only) 32MB
2.4
3.6
2.4
3.6
mA
19,22
REFRESH CURRENT: SELF (S version only)
Iccg 16MB
Average power supply current during SELF REFRESH; CBR cycling
with RAS 2 tRA8S (MIN) and CAS held LOW; WE =Vcc -0.2V; OE, (8 only) 32MB
AO-A 10 and DIN =Vcc -0.2V or 0.2V (DIN may be left open)
2.4
3.6
2.4
3.6
mA
19
=tRC [MIN])
REFRESH CURRENT: Extended (S version only)
Average power supply current
CAS = 0.2V or CBR cycling; RAS = tRAS (MIN); WE
OE, AO-A 10 and DIN =Vcc -0.2V or 0.2V
(DIN may be left open); tRC =62.51ls
MTSLD432(X)(S), MT16L0832(X)(S)
OM37.pm5 - Rev. 2/95
=Vcc -0.2V;
4-139
Micron Technology, Inc., reserves the right to change products or specifications wit houtnollCB.
©1995, Micron Technoiogy, Inc.
•
C
:D
l>
s:
en
-s:
s:
ADVANCE
I"IIC::I=ICN
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
"'"'"co,,"c
CAPACITANCE
•
C
MAX
16MB 32MB
SYMBOL
PARAMETER
UNITS
NOTES
17
Input Capacitance: AO-A10
Cit
48
95
pF
Input Capacitance: WE
CI2
64
127
pF
17
Input Capacitance: RASO-RAS1
CI3
64
64
pF
17
Input Capacitance: CASO-CAS3
CI4
16
32
pF
17
Input/Output Capacitance: 001-0032
CIO
10
18
pF
17
II
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
s:
en
i!
s:
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vcc
l>
=+3.3V ±0.3V)
-6
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
SYM
tAA
MIN
tAR
50
0
0
55
tASC
Column-address setup time
Row-address setup time
Column-address to WE delay time
tASR
tAWD
Access time from CAS
tCAC
Column-address hold time
tCAH
CAS pulse width
tCAS
RAS LOW to "don't care" during SELF REFRESH cycle
CAS precharge time
tCHD
tCHR
ICLZ
tcp
Access time from CAS precharge
tCPA
CAS to RAS precharge time
tCRP
CAS hold time
CAS setup time (CBR REFRESH)
tCSH
tCSR
CAS to WE delay time
tCWD
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
Data-in hold time
tCWL
tDH
Data-in hold time (referenced to RAS)
tDHR
Write command to CAS lead time
Data-in setup time
Output disable
Output Enable Time
tDS
tOD
tOEH
Output buffer turn-off delay
tOFF
tORD
tpc
OE setup prior to RAS during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
MT8LD432(X}(S), MTI6L0832(X)(S)
DM37.pm5 - Rev. 2195
tpRWC
4-140
MIN
30
10
15
15
15
3
10
15
3
0
35
85
UNITS
35
ns
10,000
15
20
15
15
3
10
15
15
15
ns
ns
ns
15
3
0
40
95
ns
29
9
ns
10,000
ns
ns
ns
ns
ns
40
5
70
5
45
20
15
55
0
3
NOTES
ns
20
35
5
60
5
40
15
10
45
0
3
MAX
55
0
0
60
15
tOE
OE hold time from WE during READ-MODIFY-WRITE cycle
-7
MAX
27
19
24
18
ns
ns
ns
ns
ns
19
29
ns
ns
15
ns
ns
20
20
ns
ns
15
24
21
ns
20
ns
ns
12,24,33
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
I"IICI=ICN
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
,,,"",coe,,,,
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vee
=+3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
Access time from RAS
RAS to column-address delay time
MIN
tRAC
15
Row-address hold time
Column-address to RAS lead time
tRAL
tRAS
tRASP
60
60
Random READ or WRITE cycle time
tRASS
tRC
100
110
RAS to CAS delay time
tRCD
20
Read command hold time (referenced to CAS)
Read command setup time
tRCH
a
a
RAS pulse width during SELF REFRESH cycle
Refresh period (2,048 cycles)
Refresh period (2,048 cycles) S version
tRCS
tREF
tREF
MAX
MIN
60
tRAD
tRAH
RAS pulse width
RAS pulse width (FAST PAGE MODE)
-7
-6
SYM
30
15
10
10
30
10,000
35
70
100,000
70
MAX
UNITS
70
ns
8
35
ns
23
ns
ns
10,000
100,000
100
130
45
20
50
a
a
32
128
ns
ns
Ils
ns
27
ns
13
ns
14
32
ns
ms
128
ms
tRP
40
50
ns
a
a
RAS precharge time during SELF REFRESH cycle
tRPC
tRPS
110
130
ns
ns
Read command hold time (referenced to RAS)
RAS hold time
tRRH
tRSH
a
a
15
20
ns
ns
READ WRITE cycle time
tRWC
150
180
ns
RAS to WE delay time
tRWD
Write command to RAS lead time
Transition time (rise or fall)
tRWL
tT
85
15
95
20
Write command hold time
Write command hold time (referenced to RAS)
tWCH
twCR
3
10
45
WE command setup time
Write command pulse width
twcs
twp
a
a
ns
ns
ns
10
15
ns
WE hold time (CBR REFRESH)
tWRH
10
10
ns
WE setup time (CBR REFRESH)
twRP
10
10
ns
RAS precharge time
RAS to CAS precharge time
MT8LD432(X)(S), MT1SLD832{X)(S)
DM37.pm5~
Rev. 2195
50
3
15
55
NOTES
ns
27
14
29
ns
!
50
ns
29
28
28
Micron Technology, Inc., reselVes the right to change products'or specifications without notice.
©1995, Micron Technology, Inc.
•
C
JJ
»
s:
en
s-:
s:
ADVANCE
MICRON
1-·
MTSLD432(X)(S), MT16LDS32(X)(S)
4 MEG, S MEG x 32 DRAM MODULE
m~~oc"""
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 16, 26) (Vee = +3.3V ±O.3V)
•
C
Jl
»
s:
en
s:
s:
SYM
Access time from column-address
tAA
Column-address set-up to CAS
precharge during WRITE
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
MAX
UNITS
35
ns
tAR
45
0
55
0
0
65
ns
tASC
tASR
tCAH
CAS lOW to "don't care" during SELF REFRESH cycle
tCAS
tCHD
CAS hold time (CBR REFRESH)
tCHR
t ......
0
55
A""
i5
·v!-\\.I
CAS to output in Low-Z
tClZ
Data output hold after next CAS LOW
CAS precharge time (EDO PAGE MODE)
tCOH
tcp
Access time from CAS precharge
tCPA
CAS to RAS precharge time
CAS hold time
tCSH
tCRP
CAS setup time (CBR REFRESH)
tCSR
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
tCWD
tCWL
tDH
Data-in hold time (referenced to RAS)
Data-in setup time
tDHR
tDS
MT8LD432(X)(S), MT1SLD832(X)(S)
DM37.pm5 - Rev. 2/95
30
ns
CAS pulse width
OE HIGH hold from CAS HIGH
MIN
15
Column-address hold time
Output Enable
MAX
15
tAWD
OE hold time from WE during READ-MODIFY-WRITE cycle
MIN
tACH
Column-address to WE delay time
,,d,ccess time from CAS
Output disable
-7
-6
AC CHARACTERISTICS - EOO PAGE MODE OPTION
PARAMETER
tOD
10
10
15
10
0
5
10
5
50
5
35
15
10
45
0
0
tOEHC
4-142
10
10
15
15
ns
ns
20
12
12
15
12
0
5
10
35
tOE
tOEH
10,000
12
10
ns
ns
29
9
ns
10,000
ns
ns
ns
27
19
ns
ns
40
5
55
5
40
15
12
55
0
0
NOTES
ns
ns
18
ns
ns
ns
ns
19
29
ns
15
15
ns
ns
15
ns
ns
15
ns
21
ns
ns
Micron Technology, Inc., reserves the right to change products or specificatIOns without notice.
©1995, Micron Technology, Inc.
ADVANCE
u II:::1=1CN
1-·
MTSLD432(X)(S), MT16LDS32(X)(S)
4 MEG, S MEG x 32 DRAM MODULE
",""co,",,,
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 16, 26) (Vee
=+3.3V ±O.3V)
AC CHARACTERISTICS - EDD PAGE MDDE DPTION
PARAMETER
MIN
OE HIGH pulse width
OE LOW to CAS HIGH setup time
Output buffer turn-off delay
tOES
tOFF
5
OE setup prior to RAS during HIDDEN REFRESH cycle
tORD
tpc
0
25
75
EDO-PAGE-MODE READ or WRITE cycle time
EDO-PAGE-MODE READ-WRITE cycle time
-7
-6
SYM
tOEP
tpRWC
MAX
10
3
MIN
MAX
10
5
15
3
UNITS
ns
ns
15
0
30
ns
85
tRAC
RAS to column-address delay time
tRAD
Row-address hold time
tRAH
10
10
ns
Column-address to RAS lead time
RAS pulse width
tRAL
30
tRAS
tRASP
60
60
100
35
70
ns
ns
RAS pulse width (EDO PAGE MODE)
RAS pulse width during SELF REFRESH cycle
12
10,000
125,000
12
70
100
12,24,33
ns
ns
ns
Access time from RAS
60
30
NOTES
70
ns
35
ns
10,000
125,000
8
23
ns
Random READ or WRITE cycle time
tRASS
tRC
RAS to CAS delay time
tRCD
14
ns
13
Read command hold time (referenced to CAS)
tRCH
0
0
ns
14
Read command setup time
Refresh period (2,048 cycles)
tRCS
tREF
0
0
Refresh period (2,048 cycles) S version
tREF
tRP
40
50
RAS precharge time during SELF REFRESH cycle
tRPC
tRPS
0
110
0
130
ns
27
Read command hold time (referenced to RAS)
RAS hold time
tRRH
tRSH
0
10
0
12
ns
ns
14
RAS precharge time
RAS to CAS precharge time
110
130
45
14
50
fls
ns
27
32
32
ns
ms
128
128
ms
ns
ns
READ WRITE cycle time
tRWC
150
177
ns
RAS to WE delay time
tRWD
80
90
ns
Write command to RAS lead time
tRWL
tT
15
15
ns
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WCH
tWCR
2
10
50
2
12
45
55
0
0
50
29
ns
ns
ns
Write command pulse width
twcs
tWHZ
twp
0
10
WE pulse to disable at CAS HIGH
WE hold time (CBR REFRESH)
WPZ
WRH
10
10
12
10
ns
ns
28
WE setup time (CBR REFRESH)
WRP
10
10
ns
28
WE command setup time
Output disable delay from WE
MT8LD432(X)(S}, MT16LD832(X)(S)
DM37.pmS - Rev. 2/95
4-143
13
0
12
15
ns
ns
29
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, inc.
•
c
:c
»
:s:
-en:s:
3:
ADVANCE
I"IIC:I=ICN
'''"",coo,,",
MTSlD432(X)(S), MT16lDS32(X)(S)
4 MEG, S MEG x 32 DRAM MODULE
NOTES
•
c
::c
»
s
en
-
S
S
1. All voltages referenced to Vss.
2. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
3. An initial pause of 100fls is required after power-up
followed by eight RAS REFRESH cycles (RAS ONLY
or CBR with WE HIGH) before proper device
operation is assured. The eight RAS cycle wake-ups
should be repeated any time the IREF refresh
requirement is exceeded.
4. AC characteristics assume IT = 2.5ns for EDO and 5ns
for FPM.
5. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. Measured with a load equivalent to two TTL gates
and 100pF. Output reference voltages are 0.8V for a
low level and 2.0V for a high level.
8. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
9. Assumes that IRCD ~ IRCD (MAX).
10. If CAS and RAS = VIH, data output is High-Z.
11. If CAS = VIL, data output may contain data from the
last valid READ cycle.
12. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
13. Operation within the IReD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is speCified as a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
14. Either IRCH or IRRH must be satisfied for a READ
cycle.
15. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
16. In addition to meeting the transition rate specification,
all input signals must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
17. This parameter is sampled. Vee = 3.3V ±O.3V;
f= 1 MHz.
MT8LD432(X)(S), MT16LD832(X)(S)
OM37.pmS - Rev. 2/95
18. If CAS is LOW at the falling edge of RAS, data-out
(Q) will be maintained from the previous cycle. To
initiate a new cycle and clear the data-out buffer, CAS
must be pulsed HIGH for ICP.
19. On-chip refresh and address counters are enabled.
20. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE = LOW and
OE=HIGH.
21. If OE is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not possible.
22. Ice is dependent on cycle rates.
23. Operation within the lRAD (MAX) limit ensures that
IRCD (MAX) can be met. IK4.D (MAX) specified as a
reference point only; if lRAD is greater than the
specified IRAD (MAX) limit, then access time is
controlled exclusively by IAA.
24. The 3ns minimum is a parameter guaranteed by
design.
25. Refresh current increases if lRAS is extended beyond
its minimum specification.
26. Column-address changed once each cycle.
27. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
28. IWTS and IWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of IWRP and twRH in the
CBR REFRESH cycle.
29. IWCS, IRWD, IAWD and ICWD are not restrictive
operating parameters. IWCS applies to EARLY
WRITE cycles. IRWD, IAWD and ICWD apply to
READ-MODIFY-WRITE cycles. If IWCS ~ IWCS
(MIN), the cycle is an EARLY WRITE cycle and
the data output will remain an open circuit throughout the entire cycle. If twcs < IWCS (MIN) and
IRWD ~ IRWD (MIN), IAWD ~ IAWD (MIN) and
ICWD ~ ICWD (MIN), the cycle is a READ-MODIFYWRITE and the data output will contain data read
from the selected cell. If neither of the above
conditions is met, the state of data-out is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. twcs, IRWD, ICWD and IAWD are not
applicable in a LATE WRITE cycle.
is
4-144
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
","",w,n"
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
NOTES (continued)
30. LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE HIGH during
WRITE cycle) in order to ensure that the output
buffers will be open during the WRITE cycle. If OE is
taken back LOW while CAS remains LOW, the DQs
will remain open.
31. The maximum current ratings are based with the
memory operating or being refreshed in the x72
mode. The stated maximums may be reduced by
approximately one-half when used in the x36 mode.
32. 16MB module will be half of the values shown.
33. For FAST -PAGE-MODE option, tOFF is determined
by the first RAS or CAS signal to transition HIGH. In
comparison, tOFF on an EDO option is determined by
the latter of the RAS and CAS signal to transition
HIGH.
34. Applies to both EDO and FAST PAGE MODEs.
•
C
::rJ
l>
s:
en
s:
-
3:
MTSL0432(X)(S), MT1SL0832(X)(S)
DM37.pm5 - Rev. 2/95
4-145
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG X 32 DRAM MODULE
",""owe,,,
READ CYCLE 34
tRC
tRP
tRAS
RAS
V,H
V"
--
\
tCSH
lASH
•
V ,H
VIL
=-'
tAR
tAAD
C
ADDR
V"
::tI
»
s:
CJ)
-s:
s:
WE
lASe ..
~
ROW
1 tWRP.1
~I
V,H
V"
:WII&IJNOTEti
~I
!
!~ ~l
V ,H
1
I
tRAl
I
1
~I
W$;/o
COLUMN
1
~I
ICAS
tRCD
tCRP
CAS
1
ROW
~
tRCS
~ I
II
W#/$//#/ll/$&
tAA
tRAG
NOTE 2
I~
~
tCAC
DQ
~g~ =:------OPEN-----~~~VA~LlD~DA~TAj_--OPEN--
OE
~:~ -7Ti0'j;'77:o/iJT77o/j;7771iJ7Tlo/iJ770@'7T/, /j;T77o/iJ777l;j77io/iJ'77:/, /j;'7T/, /iJ777l;j7j/;770@'77:Wj;T77@7777M'hi//;1//I///I///;1/1/1/1/;1//;1/1/1//iJ
TIji
I_
I_
tOE
too
EARLY WRITE CYCLE 34
RC
tRP
'RAS
\
leSH
J~
'RCD
tAR
I
'RAD
I~I
I~ ~I
ADDR
~l~
@'l){
ROW
~,1t
I
~ ~
d::: ~
I
tRAL
~I
I
I
tACH
1
~
COLUMN
I
I
1
I~I
'CWL
'RWl
ROW
.1
'WCR
I~
twP
CZl DON'T CARE
~
NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
2. tOFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MTBLD432(X)(S), MT16l0832(X)(S)
DM37.pm5 - Rev. 2195
4-146
Micron Technology, Inc., reserves the right to change products or specificaHons without notice.
©1995, Micron Technology, Inc.
ADVANCE
I"IIC:I=ICN
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
"'~"'oc,,"
READ WRITE CYCLE 34
(LATE WRITE and READ-MODIFY-WRITE cycles)
W
'R C
'RP
tRAS
J
kf
tCSH
-J~l:
ADDR
~:t
d
'RCD
'AR
'RAD
I
I
II :WR~I
~NOTE11
I
tRCS
I
I
I
I
I I
t
I
tRAL
W&1I
-
.::;L.~
'AWD
I
I
'AA
I
tRAC
I~
L
I~ ~I
VAUDD OUT
OPEN
M
VAlIDD 1N
~I
~
OE
ROW
.~II
IF'l.WD
'cWD
I
'CLZ-
~:gt
tCAS
~I !~I
tACH I
I~ ~I
ROW
COLUMN
W//////////////////////////;
~/;2>
~
I_ 'WRP
DO
IRSH
~:t ::i///;l;l//;l;l;l/;l//;l//;l///;l//m;l;l////m&l
,r----OPEN--
~
)
EDO-PAGE-MODE READ CYCLE
RASP
'PC
~~~ _'e_p_
tCSH
I~
tRCD
tCAS
~~
J
~:~
'AR
'
R
AD
I~ 'ASR
'RAH _I
~
~
~ leAH_j
~11,tCAH"1
(!jilt
ROW
~
COLUMN
I(I//////f COLUMN W/////;? COLUMN
'WRP "RH
I 'Res
II
NOTE 1
1
b)
I I
I
.
I
I
I
iCLZ-
I
'AA
tRAC
I
1:-
~.I
I
I
ROW
! 'RCH~
I
~
1
'AA
I
'CPA
I
tCPA
II
'RAL
I
I
'AA
tco~1
VALID
DATA
O/I!$;lI!!$/;0'/,0W!$/!I/l!ffA~
I
I
I 'CAe
'CAG
OPEN
I
I
'ep
~~
I I
ADDR
FL
IRSH
'CAG
,e~-T
-'
toFtl
tOEHC
j~
VALID
DATA
VALID
I~
J[
OPEN'
DATA
~
I_
'oD_1
tOES
tOEP
~DON'TCARE
~UNDEFINED
NOTE:
t. Although WEis a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP andtvvRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MTBLD432{X){S), MT1SLDB32(X){S)
DM37.pmS - Rev. 2/95
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995. Micron Technology. Inc.
•
C
:D
»
s:
en
s:
s:
ADVANCE
I"IIC:I=ICN
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
",e,,""''""
FAST-PAGE-MODE READ CYCLE
I~~~~~~~~~~I~RAS~P~~~~~~~~___I~
III
c
XI
»
s:
-ens:
s
RAs
~:~,'::::
ADDR
~:t::::
WE
~:t J!II/I/III!IIliPJ'
IAA
I_~~--------t+I~I:-",RA,,-C'I
'CAG
I tcLZDO
a,
~:gt
::
OPEN
6~~R
OPEN-
~:t 1I$j;I//j;I$/j;lj;lj;I$$j;lj;I/$J~ ~#j;I/&l~ £:/#/j;I/~~ ~j;lj;lj;lI;0'j;lj;lM
EDO-PAGE-MODE EARLY-WRITE CYCLE
E3 DON'T CARE
~
NOTE:
UNDEFINED
1, Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP andWRH, This design implementation will facilitate compatibility with
future EDO DRAMs,
MTBLD432{X)(S), MT16L0832(X)(S)
DM37.pm5 - Rev. 2/95
4-148
Micron Technology, Inc., resetves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
ADVANCE
UII=RCN
1-·
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
"'"""'"""
FAST-PAGE-MODE EARLY-WRITE CYCLE
RAS
~:~
_----~I~--------------~R=AS~P------------------I~I
~
_
ICSH
ROW
•
c
::c
l>
OE
~:~
;J##,@'#$(I$#$$!I/,1'!I/;/,###I$;lJl#$/I;W'##/i#/$$;l#;J1/$I$/I/I#!I/JI//1$/$#jj
EDO/FASTPAGE-MODE READ-WRITE CYCLE 34
(LATE WRITE and READ-MODIFY-WRITE cycles)
RASP
t=L
-IpC /lpRWC NOTE 1
tCSH
I~
=-.-1
~
f-----
leAS
tRCD
~1
'RAD
I I~ --ROW :WII;)
II
I
Ii
t~:~l
II I
I
IRSH
~
f-----
tCAS
A
'CAS
'AR
I~
~:~
ADDR
~
'ASR
tRAH~1
~
~ll~1
leAH ~I
'Ase
~
COLUMN
tRAL
'RWD
1AWD
l~twRP
~NOTE21
t WRH__
'WI [
'RAG
DO
~:g~
I~
I
1
'M
II
'CWL--
i
'wp--
'AWO
I~
__
'c
COLUMN
Ii
'OH---
i
-..
I -'RWL
-- (,:;L
ROW
~
I
IAWD
\~
~I[~'AAI
~I[~~I
tOH'_
II
~
COLUMN
'c
-
__ tOH
=:---------
r;zj DON'T CARE
~
NOTE:
UNDEFINED
1. tpe is for LATE WRITE cycles only.
2. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP andtvvRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT8LD432(X)(S). MTI6LD832(X)(S)
DM37.pm5 - Rev. 2195
4-149
Micron Technology, Inc., reserves the nghtto change productsorspecifications without notice
©1995, Micron Tachnology,!nc.
s::
en
-s::
s::
ADVANCE
MICRON
1-·
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
","'mcoo"",,
EDO-PAGE-MODE READ-EARL Y-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
I RASP
•
'CP
I~
Ipc
lASH
I_ _---"C::..P_ _ I _'.::;.CA=-8_ _
,----!1r--~1
c
:::a
ADDR
l>
s:
en
s:
s:
I~
~
I~
DO
~:g~------- OPEN ----~-t=~V~AL~ID~DA~TA~(A~)=jK-Ir-_~"'-=~"'"",-"--'Jil
'OE
DE
NOTE:
~:~= :J////////#/////////#/////////d~
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MTBLD432(X)(S), MT16lD832(X)(S)
DM37.pm5 -Rev. 2195
4-150
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
MT8LD432(X}(S}, MT16LD832(X}(S}
4 MEG, 8 MEG x 32 DRAM MODULE
m",oco",",
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
tCSH
ADDR
~~t =:
II
" ::t Wff&/ffffffffJ
I
o
Q
I""
I
~gt
=-----71-0PEN
I
I
hi~///;ff/ff/&//ffll
~II~
~:t :1////////////#////////////////////#/$~;#///////J~
I~ 12E_)
VALID DATA
b////////////////////m;
NOTE 1
}-----OPEN----
I
_ _'=AA_ _
___
'=RAe~
DE
I
'eWL
I
_ _1
~:t 57llA{f,!LLL2.._ _ _ _ _ _ _ _,--_ _ _ _ _ _ _ __
IZ1 DON'T CARE
r0ll UNDEFINED
NOTE:
1. Do not drive data prior to tristate.
MTBLD432(X){S), MT16L0832(X}(S)
DM37.pm5- Rev. 2/95
4-151
Micron Technology, Inc., reserves the right to change products o'r specifications without notice.
©1995, Micron Technology, Inc.
•
C
:D
l>
s:
en
-3:
s::
ADVANCE
MICRON
1-·
MTSLD432(X)(S), MT16LDS32(X)(S)
4 MEG, S MEG X 32 DRAM MODULE
",",we",,,",
HIDDEN REFRESH CYCLE 20, 34
(WE = HIGH; OE = LOW)
(REFRESH)
(READ)
RAS
t
.~
Jj
•
IRSH
tRCD
..
tAR
tRAD
~~
~
RAS
tCHR
~Ii
II tR:LI
~Ij~
I
C
J]
»
s:
-ens:
s:
~II/I//m
EDO READ CYCLE
(with WE-controlled disable)
RAS
V,H
VIL _
teRP
CAS
VIH VIL -
l
tCSH
tRCO
:
teAs
tcp
I
tAR
ADDA
WE
DO
V,H
_77T;'7T70>777:I,-----;-----,W77777±--+------;------'----------J
vIL
-ULLLLLLLD
~g~ -:-------OPEN------~:ooo;~____;.;~;:;:;;:_4
I_
DE
tOE
~:t W/M/I;/II!//IIII!;W//$ffi!P//M//;WdJA-
OPE:C~
b
~ too
o/;////II$II!II///!ll!1I!1I
l22!l DON'T CARE
~
NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT8LD432(X)(S), MT16LD832(X)(S)
DM37.pmS - Rev, 2/95
4-152
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc,
ADVANCE
MIC:RON
1-·
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
",""",,,,,
CBR REFRESH CYCLE 34
(Addresses and OE = DON'T CARE)
RAS
'RP
-1m~
0'cp~
CAs ~:t-
DO
WE
,'CHR
II
'WRP
II
RP
l
RAS
2 =tl--k
'RPC
'CSR
'CHR
OpEN--:-:II-----'WRH
'WRP
II
'WRH
~:t $/#/$#g- -~/$mI##/$ff)- -tr$/#/$#//#/$$$/;I/;%
~:t -~---'CR-P-.~-'--------.C'R=AS---'RC-~.'RPCb'RP
~:t -.:0
CAS
II
l___
• 'RAH
~:t =~r---RO-W------,b//;IffiW$/$#$//##$!0"###ar---
ADDR
DO
'ASR
RO-W - -
~gt
-'----------------OPEN----------
SELF REFRESH CYCLE 34
(Addresses and OE = DON'T CARE)
NOTE:
~
DON'T CARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT8LD432(X)(S), MT16L0832{X)(S)
DM37.pm5 - Rev. 2/95
4-153
C
:xJ
»
s:
RAS-ONLY REFRESH CYCLE 34
(WE = DON'T CARE)
RAS
•
Micron Technology, Inc., reserves the right to change products or specilfcations without notice.
©1995, Micron Technology, Inc.
-ens:
s:
ADVANCE
MICRON
1-·
,,,"",we,,,,
MT8LD432(X)(S), MT16LD832(X)(S)
4 MEG, 8 MEG x 32 DRAM MODULE
•
c
:c
»
:s:
en
s:
:s:
-
MTBL0432(X)(S), MT16LD832(X){S)
DM37.pm5 - Rev. 2195
4-154
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC:RON
m~,occ","
1-·
1 MEG , 2 MEG
MT9D136, MT18D236
x 36 DRAM MODULE
1 MEG, 2 MEG x 36
DRAM
MODULE
4,8 MEGABYTE, 5V,
FAST PAGE MODE
FEATURES
MARKING
• Timing
60ns access
70ns access
-6
-7
• Packages
72-pinSIMM
72-pin SIMM (gold)
•
~~IIIU'WWO
72-Pin SIMM
(DO-g) 1 Meg x 36, (DD-10) 2 Meg x 36
c
::D
1
PIN#
KEY TIMING PARAMETERS
tRC
tRAC
tpc
tAA
-6
110ns
35ns
40ns
15ns
40ns
130ns
60ns
70ns
30ns
-7
35ns
20ns
50ns
tCAC
tRP
PART NUMBER EXAMPLES
VALID PART NUMBERS
DESCRIPTION
MT9D136G-xx
MT9D136M-xx
1 Meg x 36, Gold
1 Meg x 36, Tin/Lead
MT18D236G-xx
MT18D236M-xx
2 Meg x 36, Tin/Lead
2 Meg x 36, Gold
3.
SYMBOL
Vss
1
2
001
0019
3
4
002
5
0020
6
003
7
0021
8
004
9
0022
10
Vee
11
NC
12
AO
13
Al
A2
14
A3
15
16
A4
17
A5
A6
18
-8MB versiorionly
M
G
SPEED
:e
PIN ASSIGNMENT (Front View)
• Common RAS control per side pinout in a 72-pin,
single-in-line memory module (SIMM)
• High-performance CMOS silicon-gate process.
• Single 5V ±10% power supply
• All device pins are TTL-compatible
• Low power, 54mW standby; 2,052mW active, typical
(8MB)
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN
• I,024-cycle refresh distributed across 16ms
• FAST PAGE MODE (FPM) access cycle
OPTIONS
z
m
PIN #
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
72
SYMBOL· PIN # SYMBOL
PIN#
SYMBOL
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
0013
0031
0014
D03?
NC
005
0023
006
0024
007
OQ25
008
0026
A7
NC
Vee
A8
A9
NC/RAS1RASO
0027
009
0018
0036
Vss
c",
3:
en
s-:
s:
UNITS
NOTES
ELECTRICAL CHARACTERIST!CS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3,4, 5, 6, 7, 10, 11, 16, 21) (Vee = +5V ±1 0%)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time (CBR REFRESH)
last CAS going lOW to first CAS to return HIGH
CAS to output in low-Z
CAS precharge time
Access time frorn CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output buffer turn-off delay
FAST-PAGE-MODE READ or WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
MT9D136, MT1BD236
DM41.pmS- Rev. 2/95
-7
-6
SYM
tAA
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCHR
tClCH
tClZ
tcp
tCPA
tCRP
tCSH
tCSR
tCWl
tDH
MIN
45
0
0
15
10
30
60
UNITS
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10,000
20
15
20
10
10
0
10
15
60
30
10,000
10,000
40
35
tRAC
tRAD
tRAH
tRAl
tRAS
MAX
50
0
0
15
10
15
10
10
0
10
tOFF
tpc
4-160
MIN
30
10
60
10
15
10
45
0
3
35
tDHR
tDS
MAX
10
70
10
20
15
55
0
3
40
15
10
35
70
20
70
35
10,000
NOTES
9
19
18
19
15
15
12,25
8
24
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
"'""''''''''
1 MEG, 2 MEG
MT9D136, MT18D236
x 36 DRAM MODULE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vee
=+5V ±10%)
AC CHARACTERISTICS
PARAMETER
RAS pulse width (FAST PAGE MODE)
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (1,024 cycles)
RAS precharge time
RAS to CAS precharge time
Read command hold time (referenced to RAS)
RAS hold time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT9D136, MT18D236
DM41.pm5-'Rev.2I95
-6
-1
SYM
MIN
MAX
MIN
MAX
UNITS
tRASP
tRC
60
110
20
0
0
100,000
70
130
20
100,000
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRCD
tRCH
tRCS
tREF
tRP
tRPC
tRRH
tRSH
tRWL
tT
tWCH
tWCR
twcs
WP
tWRH
WRP
4-161
45
a
0
16
40
0
0
15
15
3
10
45
a
10
10
10
50
50
16
50
0
0
20
20
3
15
55
0
15
10
10
50
NOTES
z
m
13
14
:e
•
c
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
JJ
l>
S
en
-s:
s:
lUll C:I=I CN
1- •
;,
NOTES
1. All voltages referenced to Vss.
2. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output.open.
3. An initial pause of 100/-1s is required after power-up
followed by any eight RAS refresh cycles (RAS-ONLY
or CBR with WE HIGH) before proper device
operation is assured. The eight RAS cycle wake-ups
should be repeated any time the tREF refresh
requirement is exceeded.
4. AC characteristics assume IT = Sns.
5. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between Vllf and VIL.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (DoC:::; TA :::; 70°C) is assured.
7. Measured with a load equivalent to two TTL gates
and 100pF.
8. Assumes that t;RCD < tRCD (MAX). HIRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that tRCD
exceeds the value shown.
9. Assumes that tRCD ~ IRCD (MAX).
10. If CAS = Vllf, data output is High-Z.
11. If CAS =VIL, data output may contain data from the
last valid READ cycle.
12. toFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
13. Operation within the IRCD (MAX) limit ensures that
lRAc (MAX) can be met. IRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
~D136,
MT19D236
0M41.pm5-Rev.2(95
MT9D136, MT18D236
1 MEG, 2 MEG x 36 DRAM MODULE
~pecifiedtRCD (MAX) limit, then access time is
controlled exclusively by tCAe.
14. Either tRCH or lRRH must be satisfied for a READ
cycle.
15. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
16. In addition to meeting the transition rate specification,
all input signals must transit between Vllf and VIL (or
between VIL and Vllf) in a monotonic manner.
17. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 3012.1 (1 MHz AC,
Vee =SV, DC bias =2.4V at 15mV RMS).
18. If CAS is LOW at the falling edge of RAS, data-out
(Q) will be maintained from the previous cycle. T~
initiate a new cycle and clear the data-out buffer, CAS
must be pulsed HIGH for tcP.
19. On-chip refresh and address counters are enabled.
20. A HIDDEN REFRESH may also be performed after a
. WRITE cycle. In this case, WE =LOW.
21. LATE-WRITE,READ-WRITEor READ-MODIFYWRITE cycles are not available due to OE being
grounded on Ul-U9/Ul8.
22. Last falling CASx edge to first rising CASx edge.
23. Ice is dependent on cycle rates.
24. Operation within the tRAD (MAX) limit ensures that
IRCD (MAX) can be met. lRAD (MAX) is specified as a
reference point only; if lRAD is greater than the
specified lRAD (MAX) limit, then access time is
controlled exclusively by tAA.
25. The 3ns minimum is a parameter guaranteed by
design.
26.4MB module values will be half of those shown.
4-162
Micron Technology, inc., reserves the right to change products or specifications WithOUt notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT9D136, MT18D236
1 MEG, 2 MEG x 36 DRAM MODULE
m~"w"'"
READ CYCLE
tRe
tRP
z
m
tCSH
:e
•
CASx
c
::c
ADOR
»
s::
en
DQx
~:g~ -c---------OPEN-------~~~~~~j_---OPEN---
EARLY WRITE CYCLE
tRP
tRAS
I
\
tCSH
I~'
1--J
1_
ADDR
~:t
:::wx.
IASR
teAs
'CLCH
IT'-
tAR
•
I
lASH
I
tACO
II
tRAD
~
III tRAl
1··tAse··11
I~
~I
COLUMN
~J<
~
ROW
I:
II
tweR
twcs
,I
-.----
II
II
II
tRWl
IIII~
twp
I I
tOHR
I
I
f:Z2l
DON'T CARE
~
UNDEFINED
•
MT9D136, MT18D236
DM41.pm5-Rev.2195
ROW
ICWL
4-163
FIRST TO LAST CAS TO TRANSITION
(minimum of 1, maximum of 4)
Micron Technology, Inc., reseNe$ the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
-s:
s:
MICRON
1-·
MT9D136, MT18D236
1 MEG, 2 MEG x 36 DRAM MODULE
'"'''",w," "
FAST-PAGE-MODE READ CYCLE
1~~~~~~~~~~~~~~~~tR~AS~P~~~~~~~~~~~~~~~I~
z
m
=E
V,H
VIL
RAS
CASx
V,H
VIL
-
ADDR
V,H
VIL
-
WE,
V,H
VIL
-
:Ii
l>
s:
en
s:
s:
tpc
'CSH
~ 1~~~~2tR~eD~~~1 ~
~
II
c
-
OQx
~I~
~
iAT----w
~:gt -,--~~~~~ OPEN~~~~~----'~~:]~}~~~i~O~j~~~-i122l)(~O
FAST-PAGE-MODE EARLY-WRITE CYCLE
~
'RASP
RAS
V1H VIL
_
tpe
tCSH
tep
'Reo
CASx
VIH VIL _
ADDR
V,L
WE
V,H
VIL
tep
VIH -
tWCR
'DHR
~I
DO, VIOH
VIOL
I
I
I~
VALID DATA
tDS
VALID DATA
~
~
DON'T CARE
UNDEFINED
FIRST TO LAST CAS TO TRANSITION
(minimum of 1, maximum of 4)
MT9D136, MT18D236
DM41.pmS-Rev.2/95
4-164
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology, Inc.
MIC:RON
1-·
MT9D136, MT18D236
1 MEG,2 MEG x 36 DRAM MODULE
"'"',"00""
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY -WRITE)
z
m
tCSH
~
~ -·----'-"R=co--
ADDR
~ ::c -0'FFFFIIIFj
J: : "'%~L~
<"
I
I
I
I
o
Q
•
C
~:t-
I
-""'-ii-::::"~FII~FIFIIIF/,I,tI,
~II~
~:~ :ij////////$////////////////////////////~:~//////////~ VALID DATA b//////////////////a2
h~"i,
~ge =·-----71-0PEN-+I~~~'=A-A=~~la"oA~ALi~[}----OPEN---tRAG
I!ZJ DON'T CARE
I22llI
NOTE:
UNDEFINED
1. Do not drive data prior to tristate.
MT9D136, MTt8D236
DM41.pmS- Rev. 2/95
4-165
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
:D
l>
s:
en
s:
s:
MICRON
1-·
MT9D136, MT18D236
1 MEG , 2 MEG x 36 DRAM MODULE
m~"oc",,",
RAS-ONLY REFRESH CYCLE
(WE = DON'T CARE)
z
m
=E
II
c
:::c
»
CBR REFRESH CYCLE
(Addresses = DON'T CARE)
s::
en
-s::
s::
HIDDEN REFRESH CYCLE 20
(WE = HIGH)
(READ)
(REFRESH)
tclCH
J
:---
tAR
IRAD
tRAH
I
III tRAL
~111.'cAH.
I
~!r
_I
I I
I
OQx ~rgt :::::------OPEN'-----i2OC===~V~ALlD~DA~TA~==J
~
OPEN-
DON'T CARE
Il88! UNDEFINED
•
MT90136, MT18D236
DM41.pm5 - Rav. 2/95
4-166
FIRST TO LAST CAS TO TRANSITION
(minimum of 1, maximum of 4)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc
PRELIMINARY
MICRON
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
",",ceo"""
4 MEG, 8 MEG x 36
DRAM
MODULE
16,32 MEGABYTE, 5V, FAST PAGE
MODE, OPTIONAL SELF REFRESH
FEATURES
• JEDEC- and industry-standard pinout in a 72-pin,
single-in-line memory module (SIMM)
• High-performance CMOS silicon-gate process
• Single 5V ±10% power supply
• All device pins are TTL-compatible
• Low power, 72mW standby; 2,536mW active, typical
(32MB)
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN; optional Extended and SELF REFRESH
• 2,048-cycle refresh distributed across 32ms or
2,048-cycle Extended Refresh distributed across 128ms
• FAST PAGE MODE (FPM) access cycle
• Multiple RAS lines allow x18 or x36 widths
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
-7
• Packages
72-pin SIMM
72-pin SIMM (gold)
72-pin SIMM low profile (1.00")
72-pin SIMM (gold) low profile (1.00")
• Refresh
Standard/32ms
SELF REFRESH/128ms
PIN ASSIGNMENT (Front View)
72-Pin SIMM
(00-11) 4 Meg x 36
(00-12) 8 Meg x 36
(00-13) 4 Meg x 36 Low Profile
~~~I -en
PIN # SYMBOL PIU SYMBOL PIN # SYMBOL PIN
1
Vss
19.
AID
37
0018
55
2
001
20
005
38
56
0036
3
0019
21
0023
39
Vss
57
4
002
22
DOG
40
CASO
58
23
0024
41
59
5
0020
CAS2
6
003
24
007
42
CAS3
60
7
43
61
0021
25
0025
CASf
8
004
26
008
44
RASO
62
9
0022
27
0026
45 NC/RAS1* 63
NC
64
10
Vee
28
A7
46
11
47
NC
29
NC
wr
65
12
AD
30
Vee
48
NC
66
13
AI
31
A8
49
DOlO
67
14
0028
68
A2
32
A9
50
15
A3
33 NC/RJ\S3* 51
0011
69
70
16
A4
34
RAS2
52
0029
17
A5
53
0012
71
35
0027
18
A6
36
009
54
0030
72
*32MB version only
Blank
S
KEY TIMING PARAMETERS
tRC
tRAC
tpc
tAA
tCAC
tRP
-6
110ns
1300s
60ns
70ns
35ns
30ns
15ns
40ns
40ns
35n5
20ns
50ns
-7
VALID PART NUMBERS
PART NUMBER
DESCRIPTION
MTI2D436DG-xx
4 Meg x 36, Gold
MTI2D436DG- xx S
MTI2D436DM-xx
MTI2D436DM- xx S
MT24D836G-xx
4 Meg x 36, Gold, S**
4 Meg x 36, Tin/Lead
4 Meg x 36, Tin/Lead, S**
8 Meg x 36, Gold
MT24D836G-xx S
8 Meg x 36, Gold, S**
MT24D836M-xx
8 Meg x 36, Tin/Lead
8 Meg x 36, Tin/Lead, S**
MT24D836M-xx S
**S = SELF REFRESH
MT12D436(S}, MT24D836(S}
OM45.pmS- Rev, 2195
C
::D
»
:s:
M
G
DM
DG
SPEED
•
*
SYMBOL
0013
0031
0014
0032
Vee
0033
0015
0034
0016
0035
0017
NC
PROI
PR02
PR03
PR04
NC
Vss
GENERAL DESCRIPTION
The MT12D436(S) and MT24D836(S) are randomly accessed 16MB and 32MB solid-state memories organized in
a x36 configuration.
During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits, which are entered
11 bits (AO -AI0) at a time. RAS is used to latch the first 11
bits and CAS the latter 11 bits. A READ or WRITE cycle is
selected with the WE input. A logic HIGH on WE dictates
READ mode while a logic LOW on WE dictates WRITE
mode. During a WRITE cycle, data-in (D) is latched by the
falling edge of CAS. Since WE goes LOW prior to CAS
going LOW, the output pin(s) remain open (High-Zl until
the next CAS cycle.
4-167
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
3:
i:
PRELIMINARY
MICRON
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
",""O'co""
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined (AOAIO) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed-in by CAS. CAS
may be toggled-in by holding RAS LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning RAS HIGH terminates the FAST PAGE
MODE operation.
at the extended refresh period. The module's SELF REFRESH mode is initiated by executing a CBR REFRESH
cycle and holding RAS LOW for the specified tRASS. Additionally, the "S" version allows for an extended refresh rate
of 62.5J.Ls per row if using distributed CBR REFRESH. This
refresh rate can be applied during normal operation, as well
as during a standby or extended refresh mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for the time minimum of an operation cycle, typically
tRPS. This delay allows for the completion of any internal
refresh cycles that may be in process at the time of the
RAS LOW-to-HIGH transition. If the DRAM controller uses
a distributed eRR REFRESH sequence, a burst refresh is not
reqUired upon exiting SELF REFRESH mode. However, if
the DRAM controller utilizes RAS ONLY or burst refresh
sequence, all 2,048 rows must be refreshed within 300J.Ls
prior to the resumption of normal operation.
II REFRESH
c
:c
l>
s:
en
-s:
s:
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS HIGH time. Memory cell data is retained in its
correct state by maintaining power and executing any
RAS cycle (READ, WRITE) or RAS refresh cycle (RAS
ONLY, CBR or HIDDEN) so that all 2,048 combinations of
RAS addresses (AO-A10) are executed at least every 32ms,
regardless of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic RAS addressing.
An additional SELF REFRESH mode is also available.
The "S" version allows the user the option of a fully static
low power data retention mode, or a dynamic refresh mode
xI8 CONFIGURATION
For x18 applications, the corresponding DQ and CAS
pins must be connected together (DQl to DQ19, DQ2
to DQ20 and so forth, and CASO to CAS2 and CASl to
CAS3). Each RAS is then a bank select for the x18 memory
organization.
FUNCTIONAL BLOCK DIAGRAM
MT12D436 (16MB)
D01 .•...•......•...••..•...•...•...•...•..•...••.•• DOg
11 tt
OQl-4
WE
--+---1 CAS
RASO --+---1
CAS1
1t tt
ttll
DQl-4
U1
DQH
WE
WE
U2
CAS
CASO
D010 •••.••.•.•.•••.•..••.•••.•.•.................. DQ18
CAsa
WE
U9
t t tt
DOl-4
WE
U6
U5
RAS
CAS
CAS
RAS
RAS
-=
--+----
WE
D028 """""""""""""""""""""""'.'
t! tt
DOl-4
WE
CAS
DOl-4
001-4
WE
U3
CAS2
tt t1
t t tt
WE
U4
!ttl
001-4
WE
U7
CAS
CAS
RAS2
D03~
us
Q
WE
U12
CAS
CAS
RAS
RAS
DE
AO-Al0
AO-Al0
CAS3
AO-AlO
U1-U8 = 4 Meg x 4 DRAMs
U9·U12 = 4 Meg x 1 DRAMs
MTI2D436(S), MT24D836(S)
DM45.pmS - Rev. 2/95
4-168
Micron Technology, Inc., reseNes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MII::::I=ICN
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
"'""''''""'
FUNCTIONAL BLOCK DIAGRAM
MT24D836 (32MB)
D01 ------------------------------------------------ DOg
t tt t
ttt t
OQ1-4
.------jWE
Ul
CASO
- - I....--__{
RASO
--I-+--__{
CAS1
--+.-t-----
CAS
DOW ------------------------------------------------- D018
f------IWE
U2
OQ1-4
OQ1-4
r----IWE
/ - - - - 1 CAS
tll t
t tt t
OQ1-4
r----IWE
U5
1-----1
CAS
/----1
U6
CAS
1-----1
II
c
J:J
tt t!
tttt
WE -~+t--__{ WE
CAS
RAS2
-+l+t--__{
CAS3
-1>-1+++-----
/----1
CAS
----iWE
u' 1-----1
:s:
!ttl
DOl -4
OQ1-4
i----iWE
U3
CAS2
ttt t
001-4
D01-4
l>
en
/----iWE
U7
CAS
/----1
U8
CAS
1------1
f-----IRAS
1
AO-A10 • • • • • •
t t! t
DQ1-4
H1i---IWE
tt t t
---~IWE
U16
CAS
f-----ICAS
---IH-f+------I RAS
f-----IRAS
1tt!
OQ1-4
WE
RAS
RAS
CAS
f-----ICAS
-+-----1 RAS
f-----IRAS
D01-4
----iWE
WE
CAS
DQ1 -4
f-----IWE
tttt
D01-4
CAS
tllt
Ull
1----1
ttt t
U13
RAS3
OQ1-4
f-----IWE
U15
RASl
l! t t
DQ1-4
1----1
t!! !
DQ1 -4
i----iWE
Ul0
U9
Ul'
U12
CAS
i----lCAS
-+-----1 RAS
f-----IRAS
1------1
U1-U16 = 4 Meg x 4 DRAMs
U17-U24 =4 Meg x 1 DRAMs
MT12D436(S), MT24D836(S)
DM45.pm5 - Rev. 2/95
4-169
Micron Technology, Inc., reserves the right to change products or specifications wilhout notice.
©1995, Micron Technology, Inc.
s:
:s:
PRELIMINARY
MICRON
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
"'""COM'"'
TRUTH TABLE
RA'S""
'CAS"
WE"
Standby
H
H~X
X
READ
L
L
EARLY WRITE
L
FUNCTION
III
c
::D
»
3:
-3:
en
ADDRESSES
IR
IC
DATA-IN/OUT
001-0036
X
X
High-Z
H
ROW
COL
Data-Out
L
L
ROW
COL
Data-In
ROW
COL
Data-Out
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H~L
H
READ
2nd Cycle
L
H~L
H
n/a
COL
FAST-PAGE-MODE
1st Cycle
L
H~L
L
ROW
COL
Data-In
WRITE
2nd Cycle
L
H~L
L
n/a
COL
Data-In
L
H
X
ROVV
Illd
_1-
High-Z
H
ROW
COL
Data-Out
RAS-ONLY REFRESH
HIDDEN
READ
L~H~L
L
REFRESH
WRITE
L~H~L
L
L
ROW
COL
Data-In
CSR REFRESH
H~L
L
H
X
X
High-Z
SELF REFRESH (S version)
H~L
L
H
X
X
High-Z
s:
JEDEC DEFINED
PRESENCE-DETECT - MT12D436 (16MB)
SYMBOL
PRD1
PRD2
PRD3
PRD4
PIN#
-6
-7
67
68
69
70
Vss
Vss
NC
NC
NC
Vss
NC
NC
JEDEC DEFINED
PRESENCE-DETECT - MT24D836 (32MB)
SYMBOL
PRD1
PRD2
PRD3
PRD4
MT12D436{S}, MT240836(S)
DM45.pm5 - Rev. 2/95
PIN #
-6
-7
67
68
69
70
NC
NC
Vss
Vss
NC
Vss
NC
NC
4-170
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MIC:RON
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
,,,""oeoc,,,,
'Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability .
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Vss .................... -IV to +7V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ........................................................... I2W
Short Circuit Output Current ..................................... 50mA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +5V ±1 0%)
SYMBOL
PARAMETER/CONDITION
MIN
MAX
UNITS
Supply Voltage
Vee
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
5.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
INPUT LEAKAGE CURRENT
RASO-RAS3
111
-12
12
IlA
Any input OV ::; VIN ::; 5.5V
AO-AlO, WE
112
-48
48
CASO-CAS3
113
-12
12
D01-D036
loz
-20
20
IlA
IlA
IlA
VOH
2.4
(All other pins not under test
=OV) for each package input
OUTPUT LEAKAGE CURRENT
(0 is disabled; OV ::; VOUT ::; 5.5V) for each package input
OUTPUT LEVELS
Output High Voltage (lOUT =-5mA)
Output Low Voltage (lOUT =4.2mA)
MT12D436(S). MT240836(S)
DM45.pm5 - Rev. 2/95
VOL
4~171
NOTES
o
:D
l>
28
28
28
V
0.4
•
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Ino.
s:
en
s:
-
3:
PRELIMINARY
MICRON
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
m<",coo,,",
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc
= +5V ±1 0%)
MAX
PARAMETER/CONDITION
•
C
:tJ I
»
s:
en
-s:
s
SYMBOL
SIZE
-6
-7
UNITS
STANDBY CURRENT: (TTL)
(RAS =CAS =VIH)
Icc1
16MB
32MB
34
68
34
68
mA
STANDBY CURRENT: (CMOS)
(RAS = CAS =Other Inputs =Vcc -0.2V)
Icc2
16MB
32MB
Icc2
16MB
(S only) 32MB
18
36
13
26
18
36
13
26
mA
1,200
1,234
mA
3,4,
26
mA
3,4,
26
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC =tRC [MIND
I
Icc3
I32MB
i6MB I 1,400 I
1,434
NOTES
mA
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS =VIL, CAS, Address Cycling: tpc =IpC [MIN])
Icc4
16MB
32MB
1,040
1,074
920
954
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: tRC =tRC [MIN])
Icc5
16MB
32MB
1,400
1,434
1,200
1,234
mA
3,26
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC
Icc6
16MB
32MB
1,400
1,434
1,200
1,234
mA
3,5
Icc7
16MB
(S only) 32MB
3.6
7.2
3.6
7.2
mA
3,5
Icca
16MB
(S only) 32MB
3.6
7.2
3.6
7.2
mA
5
=tRC [MIN])
REFRESH CURRENT: Extended (S version only)
Average power supply current
CAS =0.2V or CBR cycling; RAS =tRAS (MIN); WE
AO-A 10 and DIN = Vcc -0.2V or 0.2V
(DIN may be left open); tRC = 62.5!!s
=0.2V;
REFRESH CURRENT: SELF (S version only)
Average power supply current during SELF REFRESH;
CBR cycling with RAS ~ tRASS (MIN) and CAS held LOW;
WE =Vcc -0.2V; AO-A 10 and DIN = Vcc -0.2V or 0.2V
(DIN may be left open)
MT12D436(S), MT240836(S)
OM4S.pm5 - Rev. 2/95
4-172
Micron Technology, Inc., reserves the right to change products or speCifications without notice,
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
"""0",0' '"
CAPACITANCE
MAX
PARAMETER
SYMBOL 16MB
32MB
UNITS
Input Capacitance: AO-A 1O
CI1
70
140
pF
2
Input Capacitance: WE
CI2
94
188
pF
2
Input Capacitance: RASO, RAS1, RAS2, RAS3
03
50
50
pF
2
Input Capacitance: CASO, CAS1, CAS2, CAS3
CI4
25
50
pF
2
InpuVOutput Capacitance: 001-008, 0010-0017, 0019-0026, 0028-0035
CI01
10
18
pF
2
InpuVOutput Capacitance: 009, 0018, 0027, 0036
CI02
16
28
pF
2
NOTES
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+5V ±1 0%)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
SYM
tAA
tAR
tASC
Row-address setup time
Access time from CAS
tCAC
Column-address hold time
tCAH
CAS pulse width
RAS lOW to "don't care" during SELF REFRESH cycle
tCAS
tCHD
CAS hold time (CBR REFRESH)
tCHR
CAS to output in low-Z
CAS precharge time
tClZ
tcp
Access time from CAS precharge
tCPA
CAS to RAS precharge time
tCRP
CAS hold time
CAS setup time (CBR REFRESH)
tCSH
tASR
MIN
10
15
15
15
3
10
tDS
tpRWC
n/a
tDHR
Access time from RAS
tRAC
RAS to column-address delay time
Row-address hold time
tRAD
tRAH
Column-address to RAS lead time
tRAl
RAS pulse width
tRAS
Random READ or WRITE cycle time
MT12D436(S), MT24D836(S)
DM4S.pmS - Rev. 2195
tRASP
tRASS
tRC
4-173
15
10
30
60
60
100
110
MAX
UNITS
35
ns
55
0
0
10,000
15
20
15
15
3
10
15
ns
ns
10,000
10,000
100,000
15
10
35
70
70
100
130
15
ns
ns
ns
ns
ns
ns
27
5
25
16
ns
ns
ns
5
ns
20
n/a
60
30
ns
ns
40
5
70
5
20
15
55
0
3
40
NOTES
ns
20
35
tOFF
tpc
Data-in hold time (referenced to RAS)
MIN
15
Data-in setup time
tCSR
tCWl
tDH
MAX
50
0
0
Output buffer turn-off delay
Write command to CAS lead time
Data-in hold time
-7
30
5
60
5
15
10
45
0
3
35
RAS pulse width (FAST PAGE MODE)
RAS pulse width during SELF REFRESH cycle
C
:0
l>
-6
Column-address setup time
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
•
70
35
ns
ns
21
ns
21
20,25
ns
ns
ns
ns
ns
22
14
18
ns
ns
10,000
100,000
ns
ns
~
27
ns
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
@1995,MlcronTechnology,"lnc.
S
en
-
S
S
PRELIMINARY
UIC:RON
I-a
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG X 36 DRAM MODULES
"'~"coo,,'
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+5V ±1 0%)
-6
AC CHARACTERISTICS
PARAMETER
RAS to CAS delay time
Read command hold lime (referenced to CAS)
•
c
:c
»
s
en
-S
S
SYM
tRCD
tRCH
Read command setup time
tRCS
Refresh period (2,048 cycles)
tREF
Refresh period (2,048 cycles), S version
RAS precharge time
tREF
tRP
RAS to CAS precharge time
RAS precharge time during SELF REFRESH cycle
tRPC
-7
MIN
MAX
MIN
MAX
20
0
0
45
20
0
0
50
32
128
UNITS
ns
ns
NOTES
17
19
ns
32
128
ms
ms
ns
tRPS
40
0
110
50
0
130
Read command hold time (rafeienced to RAS)
tRRH
0
a
ns
27
19
RAS hold time
tRSH
tRWC
15
20
n/a
n/a
ns
ns
22
15
3
10
45
0
10
10
10
20
3
15
55
0
15
10
10
READ WRITE cycle time
Write command to RAS lead time
Transition time (rise or fall)
tRWL
Write command hold time
Write command hold time (referenced to RAS)
twCH
tWCR
WE command setup time
twcs
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MTI2D436{S), MT24D836(S)
DM45.pm5 - Rev. 2/95
t-r
twP
twRH
tWRP
4-174
50
ns
ns
50
ns
ns
ns
ns
ns
ns
ns
ns
24
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technoiogy, Inc.
PRELIMINARY
MICRON
1-·
,,,,,",ecoo,,,,,
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
NOTES
1. All voltages referenced to Vss.
2. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 3012.1 (1 MHz AC,
Vee = 5V, DC bias = 2.4V at 15mV RMS).
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100~s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume IT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input Signals. Transition times
are measured between VIH and VIL (or between VIL
andVIH).
10. In addition to meeting the transition rate speCification,
all input signals must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD :2: IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
MT12D436(S), MT24D836(S)
DM45.pm5 - Rev. 2/95
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
18. Operation within the IRAD (MAX) limit ensures that
IRCD (MAX) can be met. IRAD (MAX) is specified as a
reference point only; if lRAD is greater than the specified lRAD (MAX) limit, then access time is controlled
exclusively by IAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
22. OE is tied permanently LOW; LATE WRITE or READMODIFY-WRITE operations are not permissible and
should not be attempted.
23. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE = LOW and
OE=HIGH.
24. twTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of twRP and twRH in the
CBR REFRESH cycle.
25. The 3ns minimum is a parameter guaranteed by
design.
26. Column-address changed once each cycle.
27. Refresh must be completed within the time of three
external refresh rate periods prior to active use of the
DRAM (provided distributed CBR REFRESH is used
when in the active mode). Alternatively, a complete
set of row refreshes must be executed when exiting
SELF REFRESH prior to active use of the DRAM if
anything other than distributed CBR REFRESH is
used in the active mode.
28. 16MB module values will be half of those shown.
4-175
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
C
:rJ
l>
s:
-ens:
s:
PRELIMINARY
MICRON
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
","",CO"""
READ CYCLE
'RC
'RP
tRAS
RAS
VIH -
VIL _
tCSH
tRRH
tRSH
•-
CAS
teAs
IRCD
tCRP
=-'
~:t
C
"'l'I
»
s:
en
-s:
s:
ROW
ADDR
.1
WE
I
'AA
tRAG
~
'CAC
~
DO
VIOH -
VALID DATA
OPEN
VIOL
OPEN
EARLY WRITE CYCLE
'RC
tCSH
leAP
CAS
V,L
ADDR
MT12D436(S), MT24D836(S)
DM45.pm5 -' Rev. 2195
tRCD
-~-±------'---7+------------y-;
V,H __
~[t
-~
'--------'1'-------
ROW
ROW
4-176
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Mic(on Technology, Inc.
PRELIMINARY
MICRON
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
"'""oco"',,,
FAST-PAGE-MODE READ CYCLE
-------------------------------'R~A~S~P------------------------------I~
RAS
V'H
V'l
-
CAS
V'H
V'l
-
~
-
•
C
:D
»
s:
en
s:
s:
FAST-PAGE-MODE EARLY-WRITE CYCLE
'PC
'RCD
----+--~---~~i·
WE
II'
~
I~~'~~. ~
V~
,'RAD,
ADDR
'CAS.
V:~
YII,X
ROW
WII/)
•
COLUMN
I
~\
~:~
I
'CWl
'CAS, "
L,
~
'CP
I~I
'CAS
I
I
I~~'I~~ hll~1 I'
~~
~IIIIIIIM
:WIIIIIIII)
Wllllllilla:
'RAl
,I
I. ::~H .
I I
'CP
.
COLUMN
II
'CWl
II
'WP
~II~
.
.1
.
COLUMN
II
'eWl
II
'WP
ROW
~II~
•
~~-----'------:-'WC-----'I'LL1R~II~---'-;--II~~
tOHR
DQ
~lg~
MTI2D436(S), MT24D836(S)
DM45.pm5 - Rev. 2/95
VALID ,DATA
VALID DATA
4-177
VALID DATA
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
"'""'''"'"'
RAS-ONlY REFRESH CYCLE
(WE = DON'T CARE)
•
C
:r.J
DO
~gt
-
OPEN----------
l>
s:
en
s:
s:
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODiFY-WRiTE)
tCSH
=1
~I-.--~'A=CD~--~I-~-1
CAS
ADDR
~IH
IL -
'CP
~-----J
~:t::::
COLUMN
II
I
I
'77TTT77TTTT7T77-r-rnIr--------'---'--------------,
~:t =
I
I
'CWL
II
'AWL
II 'wP
1_----7---"A"""-CS_1
WE
~_-+--'
I
I
~~II~
'---:-~-'+--:--II~-----'LLL.LLL..'-LLLLLLLLLLLLLLLLL
rTT7TT"TTTT.rrTTT>7TTT77n
" :: :///$/$/'@/$$/$'@/$/$$//jl///$//jlj "'OM" bjl/&/$/&/jI/,i
I-'-T
'CAC
~~
.
---
~
OPEN
I.
I.
~.
'AA
'RAG
NOTE 1
VALID
~
OPEN----
tzZJ DON'T CARE
~
NOTE:
UNDEFINED
1. Do not drive data prior to tristate.
MT12D436(S), MT240836(S)
DM4S.pmS - Rev. 2/95
4-178
Micron Technology, Inc., reserves the right to change products or specilica~ons without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
"'""''"""''''
CBR REFRESH CYCLE
(Addresses = DON'T CARE)
.
.-----.I
RP
..
RAS
J9~ . 2
~:t::
DQ
WE
RP
..
RAS
• I
tRPC
tCHR
CAS
.t.
II
tWRP
II
~~~
;CHR
l
OPEN----;-;.-II------
tWRH
tWRP
II
tWRH
~:t 4//$//J/o- -w///i/l////ild/i/i$- -*W/i/$$/!d/i##/i;1//jJ;
•
C
:II
l>
S
en
-:s:
SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
NOTE:
s:
~
DON'T
~
UNDEFINED
CARE
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT120436(S), MT240836(S)
DM45,pm5 - Rev. 2/95
4-179
Micron Technology, Inc., reserves the right to change products or specifications wlthout notice.
©1995, Micron Technology, Inc.
PRELIMINARY
UII:::I=ICN
1-·
MT12D436(S), MT24D836(S)
4 MEG, 8 MEG x 36 DRAM MODULES
","",CO"""
HIDDEN REFRESH CYCLE 23
(WE = HIGH)
(REFRESH)
(READ)
•
C
Jl
l>
ADDR
is:
en
s:
s:
~~.
DQ
~:gt
::------
MT12D436(S), MT24D836(S)
DM4S.pmS - Rev. 2195
OPEN
1':iOOQ(Y.
4-180
-
-'OFF
~
VALID DATA
OPEN-
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
DRAM DIMMs ..................................................
DRAM DlMM PRODUCT SELECTION GUIDE
Memory
Configuration
3.3VOIMMs
Part
Number
1 Meg x 32
3.3V
MT2LD(T)132H
1 Meg x 32
3.3V
MT2LD(T)132H S
2 Meg x 32
3.3V
MT4LD(T)232H
2 Meg x 32
3.3V
MT4LD(T)232H S
4 Meg x 32
3.3V
MT8LD(T)432H
4Megx32
3.3V
MT8LD(T)432H S
1 Megx64
3.3V
MT16LD(T)164
1 Meg x 64
3.3V
MT16LD(T)164 S
2Megx64
3.3V
MT8LD(T)264
2 Meg x 64
3.3V
MT8LD(T)264 S
2Megx64
3.3V
2 Meg x 64
Optional
Access Cycle
S
S
S
S
Access
Typical Power Dissipation No. of Pins
Time (ns)
Standby
Active
OIMM
Page
60. 70
6mW
500mW
72
5-1
60, 70
.6mW
500mW
72
5-1
60, 70
12mW
506mW
72
5-1
60, 70
1.2mW
501mW
72
5-1
60, 70
8mW
1,440mW
72
5-15
60, 70
2.4mW
1,440mW
72
60, 70
19.2mW
1.600mW
168
5-15
5:47
60, 70
4.8mW
1,600mW
168
5-47
60, 70
8mW
1,600mW
168
5-69
S
60, 70
2.4mW
1,600mW
168
5-69
MT8LD(T)264 X
EDO
60, 70
8mW
1,200mW
168
5-69
3.3V
MT8LD(T)264 XS
EDO,S
60, 70
2.4mW
1,200mW
168
5-69
4Megx64
3.3V
MT16LD(T)464
60, 70
16mW
2,880mW
168
5-47
4Megx64
3.3V
MT16LD(T)464 S
S
60, 70
4.8mW
2,880mW
168
5-47
4 Meg x 64
3.3V
MT16LD(T)464 X
EDO
60, 70
16mW
2,400mW
168
5-47
EDO, S
60, 70
6.4mW
2,400mW
168
5-47
60, 70
21.6mW
1,800mW
168
5-109
60, 70
5.4mW
1,800mW
168
5-109
60, 70
9mW
1,800mW
168
5-131
4 Meg x 64
3.3V
MT16LD(T)464 XS
1 Meg x 72
3.3V
MT18LD(T)172
1 Meg x 72
3.3V
MT18LD(T)172 S
2 Meg x 72
3.3V
MT9LD(T)272
2 Meg x 72
3.3V
MT9LD(T)272 S
S
60, 70
2.7mW
1,800mW
168
5-131
2 Meg x 72
3.3V
MT9LD(T)272 X
EDO
60, 70
9mW
1,350mW
168
5-131
2 Meg x 72
3.3V
MT9LD(T)272 XS
EDO, S
60, 70
2.7mW
1,350mW
168
5-131
4 Meg x 72
3.3V
MT18LD(T)472
60, 70
18mW
3,240mW
168
5-109
4 Meg x 72
3.3V
MT18LD(T)472 S
S
60, 70
5.4mW
3,240mW
168
5-109
4 Meg x 72
3.3V
MT18LD(T)472 X
EDO
60, 70
18mW
2,700mW
168
5-109
4 Meg x 72
3.3V
MT18LD(T)472 XS
EDO,S
60, 70
5.4mW
2,700mW
168
5-109
60, 70
48mW
3,600mW
168
5-29
60, 70
12.8mW
3,600mW
168
5-29
60, 70
48mW
4,000mW
168
5-29
60, 70
54mW
4,050mW
168
5-91
60, 70
14.4mW
4,050mW
168
5-91
60, 70
54mW
4,500mW
168
5-91
S
5V OIMMs
1 Meg x 64
5V
MT16D(T) 164
1 Meg x 64
5V
MT16D(T)164 S
4 Meg x 64
5V
MT16D(T)464
1 Meg x 72
5V
MT18D(T)172
1 Meg x 72
5V
MT18D(T)172 S
4 Meg x 72
5V
MT18D(T)472
EDO = Extended Data-Out; S = SELF REFRESH
S
S
ADVANCE
MIC:RON
1-·
MT2LD(T)132H(S), MT4LD(T)232H(S)
1 MEG, 2 MEG x 32 DRAM MODULE
",""co", '"
1 MEG, 2 MEG x 32
SMALL-OUTLINE
DRAM MODULE
4, 8 MEGABYTE, 3.3V, FAST PAGE MODE,
OPTIONAL SELF REFRESH
FEATURES
• JEDEC- and industry-standard pinout in a 72-pin,
small-outline, dual-in-line memory module (DIMM)
• High-performance CMOS silicon-gate process.
• Single +3.3V ±O.3V power supply
• All device pins are TTL-compatible
• Low power, 12mW standby; 506mW active, typical
(8MB)
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN; optional Extended CBR and SELF
• 1,024-cycle refresh distributed across 16ms or
1,024-cycle extended refresh distributed across 128ms
• FAST PAGE MODE (FPM) access cycle
OPTIONS
PIN ASSIGNMENT (Front View)
72-Pin Small-Outline DIMM
(DE-4) SOJ, (DE-1) TSOP 1 Meg x 32
(DE-6) SOJ, (DE-2) TSOP 2 Meg x 32
~
-6
-7
• Components
SOJ
TSOP
D
DT
• Packages
72-pin Small-Outline DIMM (gold)
• Refresh
Standard/16ms
SELF REFRESH/128ms
1
PIN#
1
3
5
7
9
11
13
15
G
17
19
21
23
25
27
29
31
33
35
Blank
S
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tpc
tAA
tCAC
tRP
-6
110ns
35ns
30ns
15ns
40ns
-7
130ns
60ns
70ns
40ns
35ns
20ns
50ns
PART NUMBER
DESCRIPTION
MT2LDT132HG-xx
MT2LDT132HG-xx S
1 Meg x 32, SELF REFRESH, TSOP
MT2LD132HG-xx
MT2LD132HG-xx S
MT4LDT232HG-xx
MT4LDT232HG-xx S
2 Meg x 32, TSOP
MT4LD232HG-xx S
2 Meg x 32, SELF REFRESH, SOJ
MT2LD(T)132H(S), MT4LD(T)232H(S)
DM40.pm5 - Rev. 2195
RJ\S2
NC
PIN# FRONT PIU
37
0016
38
39
Vss
40
CASl'.
41
42
43
CAS"f
44
45 NCiRASP 46
47
WE
48
49
0018
50
51
0020
52
OQ22
53
54
55
NC
56
57
0025
58
0027
60
59
61
Vee
62
64
63
0030
NC
66
65
PR03
67
68
69
PRD5
70
PRD7
71
72
BACK
0017
~o
CAS3
ro\SO
NC
NC
DatU
D(l2t
OQ23
0024
0026
0028
0029
0031
PR02
PR04
PRD6
Vss
The MT2LD(T)132H(S) and MT4LD(T)232H(S) are randomly accessed 4MB and 8MB solid-state memories organized in a small outline x32 configuration. They are specially processed to operate from +3.0V to 3.6V for low
voltage memory systems. The modules have optional FAST
PAGE MODE, which allows faster data operations (READ
or WRITE) within a row-address-defined (AO-A9) page
boundary.
The wider voltage range on these modules allows them to
be used in +3.3V ±O.3V memory designs. On the SELF
REFRESH version, the refresh period is also extended from
the standard 16ms to 128ms to provide maximum power
1 Meg x 32, SOJ
1 Meg x 32, SELF REFRESH, SOJ
2 Meg x 32, SELF REFRESH, TSOP
2 Meg x 32, SOJ
BACK
000
002
004
006
Vee
AO
A2
A4
A6
NC
009
0011
OQ13
A7
Vee
A9
GENERAL DESCRIPTION
1 Meg x 32, TSOP
MT4LD232HG-xx
FRONT PIN #
Vss
2
001
4
003
6
005
8
007
10
PRDI
12
AI
14
16
A3
A5
18
NC
20
008
22
0010
24
0012
26
0014
28
NC
30
A8
32
NC/RAS3' 34
0015
36
5-1
C
:tJ
»
s:
'8MB version only
VALID PART NUMBERS
:E
•
0 0
J
o rIDnOmIlnnmOODDDDDoormmmUD 1 .2-
MARKING
• Timing
60ns access
70ns access
z
m
Micron Technology, Inc., reserves the right to change products or specifications Without notice.
©1995, Micron Technology. Inc.
-!c:
3:
ADVANCE
MICRON
1-·
z
m
:e
•
c
:D
l>
3:
-sc::
s::
MT2LD(T)132H(S), MT4LD(T)232H(S)
1 MEG, 2 MEG x 32 DRAM MODULE
"'>me",,"",
GENERAL DESCRIPTION (continued)
REFRESH
savings. The SELF REFRESH cycle allows the module to
perform the extended refresh by itself. This eliminates the
need to toggle the RAS clock during a sleep mode.
During READ or WRITE cycles, each bit is uniquely
addressed through the 20 address bits which are entered 10
bits (AO -A9) at a time. RAS is used to latch the first 10 bits
and CAS the latter 10 bits.
READ and WRITE cycles are selected with the WE input.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. If WE goes LOW prior to CAS going
LOW, the output pines) remain open (High-Z) until the next
CAS cycle.
Memory cell data is retained in its correct state by maintaining power and executing any RAS cycle (READ, WRITE)
or RAS refresh cycle (RAS ONLY, CBR or HIDDEN) so that
all combinations of RAS addresses (AO-A9) are executed at
least every tREF, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for
automatic RAS addressing.
An additional SELF REFRESH mode is also available.
The "5" version allows the user the option of a fully static
low power data retention mode, or a dynamic refresh mode
at the extended refresh period. The module's SELF REFRESH mode is initiated by executing a CBR REFRESH
cycle and holding RAS LOW for the specified tR,.I..5S.
The SELF REFRESH mode is terminated by driving
RAS HIGH for the time minimum of an operation cycle,
typically tRPS. This delay allows for the completion of any
internal refresh cycles that may be in process at the time of
the RAS LOW-to-HIGH transition. If the DRAM controller
uses a distributed CBR REFRESH sequence, a burst refresh
is not required upon exiting SELF REFRESH mode. However, if the DRAM controller utilizes burst refresh sequence,
all 1,024 rows must be refreshed within 300/-ts, prior to the
resumption of normal operation.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined
(AO-A9) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed-in by CAS. CAS
may be toggled-in by holding RAS LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning RAS HIGH terminates the FAST PAGE
MODE operation.
FUNCTIONAL BLOCK DIAGRAM
MT2LD(T)132H (4MB)
AO·A9
U1
CASO
CAS1
RASO
AO·A9
-111••
WE
---------1
DOO·D031
RAS
OE
=
U1-U2 = MT4LC1M16C3 (S)
MT2LD(T)132H(S), MT4LO(T)232H(S)
DM40.pm5 - Rev. 2/95
5-2
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT2LD(T)132H(S), MT4LD(T)232H(S)
1 MEG,2 MEG x 32 DRAM MODULE
"'"''''''''
STANDBY
x16 CONFIGURAnON
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS HIGH time.
For x16 applications, the corresponding DQ and CAS
pins must be connected together (DQO to DQ16, DQl to
DQ17 and so forth, and CASO to CAS2 and CASl to CAS3).
Each RAS is then a bank select for the x16 memory
organization.
FUNCTIONAL BLOCK DIAGRAM
MT4LD(T)232H (8MB)
z
m
~
•
CASO
C
lJ
CAS1
RASO
»
• • • • 000.0031
AO·A9
RAS1
• • • • 000.OQ31
=
MT2LD(T)132H(S}, MT4lD(T)232H(S)
OM40.pm5 - Rev. 2195
U1·U4 = MT4LC1M16C3 (8)
5-3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
s:
-cs:
s:
ADVANCE
MIC:RON
1-·
MT2LD(T)132H(S), MT4LD(T)232H(S)
1 MEG, 2 MEG x 32 DRAM MODULE
",""0""'"'
TRUTH TABLE
ADDRESSES
z
m
:E
•
o
:IJ
»
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o
s:
s:
DATA-IN/OUT
FUNCTION
MS
CAS
WE
IR
IC
Standby
H
H-X
X
X
X
High-Z
READ
L
L
H
ROW
COL
Data-Out
EARLY WRITE
L
L
L
ROW
COL
Data-In
000-0031
FAST-PAGE-MODE
1st Cycle
L
H-L
H
ROW
COL
Data-Out
READ
2nd Cycle
L
H-L
H
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H-L
L
ROW
COL
Data-In
WRITE
2nd Cycle
L
H-L
L
n/a
COL
Data-In
RAS-ONLV REFRESH
L
H
X
ROW
n/a
High-Z
HIDDEN
READ
L-H-L
L
H
ROW
COL
Data-Out
REFRESH
WRITE
L-H-L
L
L
ROW
COL
Data-In
CBR REFRESH
H-L
L
H
X
X
High-Z
SELF REFRESH (S version)
H-L
L
H
X
X
High-Z
JEDEC DEFINED
PRESENCE-DETECT - MT2LD(T)132H (4MB)
PINfi
-6
-7
PR01
11
NC
NC
PR02
66
Vss
Vss
PR03
67
Vss
Vss
PR04
68
NC
NC
PROS
69
NC
Vss
PR06
70
NC
NC
PR07
71
X'
X'
SYMBOL
• NC= Normal Refresh I Vss = S version only
JEDEC DEFINED
PRESENCE-DETECT - MT4LD(T)232H (8MB)
PINfi
-6
-7
PR01
11
NC
NC
Vss
SYMBOL
PR02
66
Vss
PR03
67
Vss
Vss
PR04
68
Vss
Vss
PROS
69
NC
Vss
PR06
70
NC
NC
PR07
71
X'
X'
• NC= Normal Refresh I Vss = S version only
MT2LD(T)132H(S), MT4LD(D232H(S)
DM40.pm5 - Rev. 2/95
5-4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology, Inc.
ADVANCE
MICRON
1-·
MT2LD(T)132H(S), MT4LD(T)232H(S)
1 MEG, 2 MEG x 32 DRAM MODULE
m<",c"""
'Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee supply relative to Vss ............ -IV to +4.6V
Voltage on Inputs or I/O pins
relative to Vss ..................................................... -1 V to +5.5V
Operating Temperature, TA (ambient) .......... DoC to +70°C
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ............................................................. 4W
Short Circuit Output Current ..................................... 50mA
z
m
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 6) (Vee
=+3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
NOTES
:0
l>
RASO-RAS3
AO-A9, WE
CASO-CAS3
iii
112
113
-2
-8
2
8
IlA
uA
-4
4
ilA
29
29
OUTPUT LEAKAGE CURRENT
(Q is disabled; OV ,,; VOUT ,,; 5.5V) for each package input
DQO-DQ31
loz
-20
20
J.lA
29
VOH
2.4
MT2LD(T}132H(S), MT4l0(T}232H(S)
DM40.pm5 - Rev. 2/95
VOL
5-5
V
0.4
•
C
INPUT LEAKAGE CURRENT
Any input OV ,,;VIN"; 5.5V
(All other pins not under test = OV) for each package input
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
~
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MlcronTechnology, Inc.
s:
-Cs:
s:
ADVANCE
I'IIIC:I=ICN
MT2LD(T)132H(S), MT 4LD(T)232H(S)
1 MEG,2 MEG x 32 DRAM MODULE
,,,""ow",,,,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 2, 3, 6, 22) (Vcc
=+3.3V ±0.3V)
MAX
PARAMETER/CONDITION
z
m
=E
•
C
lJ
l>
s:
-s::C
s::
-6
-7
UNITS
4
8
4
8
mA
1
2
0.3
0.6
1
2
0.3
0.6
mA
14MBI
8MB
340
344
310
314
mA
mA
2,22,
26
SYMBOL SIZE
STANDBY CURRENT: (TIL)
(RAS = CAS = VIH)
Icc1
STANDBY CURRENT: (CMOS)
(RAS =CAS = Vcc -0.2V)
ICC2
4MB
8MB
4MB
8MB
iCC2
4MB
(S only) 8MB
NOTES
30
mA
OPERATING CURRENT: Random READIWRITE
Average power supply curreni
(RAS, CAS, Address Cycling: IRC =IRC [MIN])
ICC3
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS =VIL, CAS, Address Cycling: IpC =IpC [MIN])
Icc4
4MB
8MB
200
204
180
184
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS =VIH: IRC =IRC [MIN])
Iccs
4MB
8MB
320
324
290
294
mA
22,26
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC
ICC6
4MB
8MB
300
304
280
284
mA
19,22
REFRESH CURRENT: Extended (S version only)
Average power supply current; CAS =0.2V or CBR cycling;
RAS =IRAS (MIN); WE =Vcc -2V, AO-A9 and DIN =Vcc -0.2V
(DIN may be left open); IRC = 12Sj.ls
Icc?
4MB
(S only) 8MB
0.6
1.2
0.6
1.2
mA
19,22
REFRESH CURRENT: SELF (S version only)
Average power supply current; CBR cycling with RAS ~ IRASS
(MIN) and CAS held LOW; WE = Vcc -0.2V; AO-A9 and
DIN = Vcc -0.2V or 0.2V (DIN may be left open)
Iccs
4MB
(S only) 8MB
0.6
1.2
0.6
1.2
mA
19
MT2LD(T)I32H(S). MT4LD(T)232H(S)
DM40.pm5 - Rev. 2/95
=IRC [MIN])
5-6
I
12'2~2'
I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©199S, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT2LD(T)132H(S), MT4LD(T)232H(S)
1 MEG,2 MEG x 32 DRAM MODULE
,",""OW,"",
CAPACITANCE
PARAMETER
SYMBOL
4MB
8MB
UNITS
NOTES
Input Capacitance: AO-A9
Cll
14
26
pF
17
Input Capacitance: WE
CI2
18
34
pF
17
Input Capacitance: RASO - RAS3
CI3
10
10
pF
17
Input Capacitance: CASO - CAS3
CI4
10
20
pF
17
Input/Output Capacitance: 000-0031
Cia
10
18
pF
17
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16) (Vee
=+3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
tAA
tAR
Column-address setup time
tASC
Row-address setup time
tASR
Access time from CAS
Column-address hold time
tCAC
CAS pulse width
RAS lOW to "don't care" during SELF REFRESH
tcAH
tCAS
tCHD
CAS hold time (CBR REFRESH)
tCHR
CAS to output in low-Z
CAS precharge time
tClZ
tcp
Access time from CAS precharge
CAS to RAS precharge time
tCPA
tCRP
CAS hold time
tCSH
tCSR
CAS setup time (CBR REFRESH)
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output buller turn-oil delay
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
RAS pulse width during SELF REFRESH
Random READ or WRITE cycle time
MIN
50
0
0
10
15
15
15
3
10
n/a
tRAC
tRAD
tRAH
tRAl
tRAS
tRASP
tRASS
tRC
tRCD
Read command setup time
tRCS
tRCH
5-7
15
10
30
60
60
100
110
20
0
0
MAX
UNITS
35
ns
55
0
0
10,000
15
20
15
15
3
10
15
10,000
40
5
70
5
20
15
55
0
3
40
10,000
100,000
45
15
10
35
70
70
100
130
20
0
0
ns
ns
ns
ns
ns
ns
9
ns
27
19
25
ns
18
ns
ns
ns
20
n/a
60
30
NOTES
ns
ns
20
35
tpRWC
tDHR
tDS
MIN
15
tOFF
tpc
tCWl
tDH
MAX
30
5
60
5
15
10
45
0
3
35
RAS to CAS delay time
Read command hold time (referenced to CAS)
MT2LD(T)132H(S), MT4LO(T)232H(S)
DM40.pm5 - Rev. 2/95
-7
-6
SYM
ns
ns
19
ns
ns
15
ns
15
12,25
ns
ns
ns
70
35
21
ns
8
ns
ns
23
ns
10,000
100,000
ns
ns
).IS
50
ns
ns
ns
27
13
14
ns
Micron Technology, Inc., reserves the right to c~ange products or speoifications without notice.
©1995, Micron Technology, Inc.
z
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•
c
:c
»
s:
-sc:
s
ADVANCE
MICRON
1-·
MT2LD(T)132H(S), MT 4LD(T)232H(S)
1 MEG, 2 MEG x 32 DRAM MODULE
"'""'"''''
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7,10,11,16) (Vee =+3.3V ±0.3V)
z
m
::e
•
c
:c
»
s:
-sc:
-6
AC CHARACTERISTICS
PARAMETER
SYM
Refresh period (1,024 cycles)
Refresh period (1,024 cycles) S version
tREF
tREF
MIN
-7
MAX
MIN
16
128
MAX
UNITS
16
128
ms
ms
NOTES
tRP
40
50
ns
RAS to CAS precharge time
tRPC
0
ns
RAS precharge time during SELF REFRESH
tRPS
0
110
130
ns
27
Read command hold time (referenced to RAS)
tRRH
tRSH
IRWC
0
20
ns
ns
14
RAS hold time
READ-WRITE cycle time
Write command to RAS lead time
0
15
n/a
n/a
ns
21
15
20
ns
RAS precharge time
Transition time (rise or fall)
tRWL
IT
Write command hold time
twCH
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
twCR
twcs
twp
WE hold time (CBR REFRESH)
IWRH
WE setup time (CBR REFRESH)
tWRP
3
10
50
3
50
ns
15
ns
45
55
0
10
a
ns
ns
10
15
10
ns
ns
28
10
10
ns
28
s:
MT2LD(T)132H(S}. MT4LO(T)232H(S}
DM40,pm5 ~ Rev. 2195
5-8
Micron Technology, Inc., reserves the tight to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC::RON
1-·
,"",
s:
-Cs:
s:
ADVANCE
I"IIC=F=lCN
MT2LD(T)132H(S), MT 4LD(T)232H(S)
1 MEG,2 MEG x 32 DRAM MODULE
,,,"'OCCC,,,,,
READ CYCLE
'Ae
tCSH
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I
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I
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ADDR
V,H -
:~
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V,L_
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.
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EARLY WRITE CYCLE
'AC
'AP
tCSH
ICAP
CAS
tRCD
~IH ---J---+-----77----------,;:-
-t-------l
'AA
IL -
'AAD
I
I
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WE ~:t
-
I
tWGR
I_
twCH
'WP
I I
[:Zj DON'T CARE
~
MT2LD(D132H(S). MT4LO(T)232H(S)
DM40.pm5 - Rev. 2/95
5-10
UNDEFINED
Micron Technology, Inc., reserves the nght to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT2LD(T)132H(S), MT 4LD(T)232H(S)
1 MEG,2 MEG x 32 DRAM MODULE
"'""'00""
FAST-PAGE-MODE READ CYCLE
----------------------------~tR~A~SP------------------------------I~
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-C3:
FAST-PAGE-MODE EARLY-WRITE CYCLE
3:
ADDR
DO
~lgt
~~~lill~lill~~
VALID DATA
__________
J~LU~
________
-A~
[Z2 DON'T CARE
~
MT2lD(T)132H{S), MT4LD(T)232H(S)
DM40.pm5- Rev. 2195
5-11
UNDEFINED
Micron Technology, Inc., reserves the tight to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT2LD(T)132H(S), MT 4LD(T)232H(S)
1 MEG,2 MEG x 32 DRAM MODULE
>c"mcco",'"
FAST-PAGE-MODE READ-EARL Y~WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
z
tCSH
I~
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tRCD
J
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•
IAJ
II
"tASR
IRAO
tRAH
'I~t·
~
I I ICAH'I
'1 IASC
~I:=:I~I_I-I
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-s:c
s:
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I-I I
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;
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I
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tRAL
11
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1
1.1
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COLUMN
i ::~~L
:,
I
~ll-IWC-Hk////P/////////1JZZ
•
~II~
I
1~1,1
VALID DATA
~/////////////////////h;
.k.~NOTEl
=-----:--OPEN-+---~1
s:
-s:C
s:
DQ
~:gt
: : : - - - - OPEN----~!2m'---
__
---*
_.__:V~AL~IDD~AT~A_ _
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SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
NOTE 1
=: :- +-_tRP--i'------'-7_tR~ASS~,';$Dff#$/mff!ff/ff;Ar~~
VOH DQ
WE
NOTE:
VOL
tWRP
II
II
(\-tWRH
OPEN
)
tWRP
II
II
tWRH
~:t =7,1/,1///;1)- -~W$M///$//////$///$///#///g)- -W//;I/#$//;I,1/~
~
DON'TCARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT2LD(T)132H(S}, MT4LD(T)232H(S)
DM40.pm5 - Rev. 2195
5-14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
MTBLD(T)432H(S)
4 MEG x 32 DRAM MODULE
"'""'c'"""
4 MEG x 32
SMALL-OUTLINE
DRAM MODULE
16 MEGABYTE, 3.3V, FAST PAGE
MODE, OPTIONAL SELF REFRESH
FEATURES
PIN ASSIGNMENT (Front View)
• JEDEC- and industry-standard pinout in a 72-pin,
small-outline, dual-in-line memory module (DIMM)
• High-performance CMOS silicon-gate process.
• Single +3.3V ±3V power supply
• All device pins are TTL-compatible
• Low power, 2.4mW standby; 1,440mW active, typical
Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN; optional Extended and SELF REFRESH
• 2,048-cycle refresh distributed across 32ms or
2,048-cycle extended refresh distributed across 128ms
• FAST PAGE MODE (FPM) access cycle
:e
•
UNQL]j
c
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1
OPTIONS
MARKING
• Timing
60ns access
70ns access
PIN #
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
-6
-7
• Components
SOJ
TSOP
D
DT
• Packages
72-pin Small-Outline DIMM (gold)
• Refresh
Standard/32ms
SELF REFRESH/128ms
G
Blank
S
KEY TIMING PARAMETERS
SPEED
IRe
tRAC
IpC
lAA
ICAG
IRP
-6
110ns
15ns
40ns
130ns
35ns
40ns
30ns
-7
60ns
70ns
35ns
20ns
50ns
PART NUMBER
4 Meg x 32, SOJ
4 Meg x 32, S*, SOJ
4 Meg x 32, TSOP
MT8LDT432HG- xx S
4 Meg x 32, S*, TSOP
*S = SELF REFRESH
MT8LD(D432H(S)
DM34.pm5 - Rev. 2195
PIN #
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
BACK
000
002
004
006
Vee
AO
A2
A4
A6
NC
009
0011
0013
A7
Vee
A9
RAS2
NC
PIN #
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
FRONT
0016
v'S!;
CAS2
"CAST
NC
wt
0018
0020
0022
NC
0025
0027
Vee
0030
NC
PR03
PR05
PR07
PIN #
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
BACK
!JOII
CASO
CAS3
RAsa
NC
NC
0019
0021
0023
0024
0026
0028
0029
0031
PR02
PR04
PR06
Vss
The MT8LD(T)432 is a randomly accessed 16MB solidstate memory organized in a small outline x32 configuration. It is specially processed to operate from 3.0V to 3.6V for
low voltage memory systems. The module has an optional
FAST PAGE MODE, which allows faster data operations
(READ or WRITE) within a row-address-defined (AO-A10)
page boundary.
The wider voltage range on this module allows them
to be used in +3.3V ±O.3V memory designs. On the SELF
REFRESH version, the refresh period is also extended from
the standard 32ms to 128ms to provide maximum power
savings.
During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits which are entered
DESCRIPTION
MT8LD432HG- xx S
MT8LDT432HG-xx
FRONT
Vss
001
003
005
007
P01
A1
A3
A5
A10
008
0010
0012
0014
NC
AS
NC
0015
GENERAL DESCRIPTION
VALID PART NUMBERS
MT8LD432HG-xx
z
m
72-Pin Small-Outline DIMM
(DE-5) SOJ version
(DE-3) TSOP version
5-15
Micron Technology, Inc., reserves the right to change products or specifj~ations Without notice.
©1995, Micron Technology, Inc
s:
-Cs:
s:
ADVANCE
MICRON
1-·
z
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•
==
C
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»
s:
-s:c
s:
MTSLD(T)432H(S)
4 MEG x 32 DRAM MODULE
",,,mo",,,,
GENERAL DESCRIPTION (continued)
11 bits (AO-AlO) at a time. RAS is used to latch the first 11
bits and CAS the latter 11 bits.
READ and WRITE cycles are selected with the WE input.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. If WE goes LOW prior to CAS going
LOW, the output pines) remain open(High-ZJ until the next
CAS cycle.
An additional SELF REFRESH mode is also available.
The "S" version allows the user the option of a fully static
low power data retention mode, or a dynamic refresh mode
at the extended refresh period. The module's SELF REFRESH mode is initiated by executing a CBR REFRESH
cycle and holding RAS LOW for the specified tRASS.
The SELF REFRESH mode is terminated by driving RAS
HIGH for the time minimum of an operation cycle, typically
tRPS. This delay allows for the completion of any internal
refresh cycles that may be in process at the time of the
RAS LOW-to-HIGH transition. If the DRAM controller
uses a distributed CBR REFRESH sequence, a burst refresh
is not required upon exiting SELF REFRESH mode. However, if the DRAM controller utilizes burst refresh sequence,
all 2,048 rows must be refreshed within 300l1s, prior to the
resumption of normal operation.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined
(AO -AlOJ page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed-in by CAS. CAS
may be toggled-in by holding RAS LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning RAS HIGH terminates the FAST PAGE
MODE operation.
STANDBY
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS HIGH time.
REFRESH
Memory cell data is retained in its correct state by maintainingpower and executing anyRAS cycle (READ, WRITE)
or RASrefresh cycle (RAS ONLY, CBR or HIDDEN) so that
all combinations of RAS addresses (AO-AlO) are executed
at least every tREF, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for
automatic RAS addressing.
MT8LD(T)432H(S)
DM34.pmS - Rev. 2/95
x16 OPERATION
For x16 applications, the corresponding DQ and CAS
pins must be connected together (DQl to DQI7, DQ2 to
DQ18 and so forth, and CASO to CAS2 and CASI to
CAS3). Each RAS is then a bank select for the x16 memory
organization.
5-16
Micron Technology, Inc., reserves tha right to change products or specifications without notice.
©1995,MicronTechnology, Inc.
ADVANCE
MICRON
1-·
MTBLD(T)432H(S)
4 MEG x 32 DRAM MODULE
",,""oeocn,
FUNCTIONAL BLOCK DIAGRAM
MT8LD(T)432H (16MB)
RiiS
CAs
-
DOO
WE
81
D07
.R_
-RiiS-
CAS
> - - - - WE
82
~
kL
D08
..h,.
.
D 015
D 016
83
D 023
=
R""A§'-CAS
> - - - WE
D024
84
~
ADDRESS
NOTE:
D031
=
1. B1 - B4 are x8 memory blocks consisting of 2-MT4C4M4B1 (8) DRAMs each.
MT8LD(T}432H{S)
DM34.pmS - Rev. 2/95
5-17
c
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s:
RiiS
.K,--
III
l>
-
RAS2
CAS
> - - - WE
WE
m
~
=
=
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron TechMlogy, Inc.
-C3:
3:
ADVANCE
MICRON
1-·
MTBLD(T)432H(S)
4 MEG x 32 DRAM MODULE
,ec~'MOcnc
TRUTH TABLE
ADDRESSES
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DATA-IN/OUT
~
m
WE"
IR
IC
Standby
H
H--+X
X
X
X
High-Z
READ
L
L
H
ROW
COL
Data-Out
FUNCTION
000-0031
L
L
L
ROW
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H-L
H
ROW
COL
Data-Out
EARLY WRITE
READ
2nd Cycle
L
H--+L
H
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H--+L
L
ROW
COL
Data-In
WRITE
2nd Cycle
L
H--+L
L
n/a
COL
Data-In
L
H
X
ROW
n/a
High-Z
RAS-ONLY REFRESH
HIDDEN
READ
L--+H--+L
L
H
ROW
COL
Data-Out
REFRESH
WRITE
L--+H--+L
L
L
ROW
COL
Data-In
CBR REFRESH
H--+L
L
H
X
X
High-Z
SELF REFRESH (S version)
H--+L
X
High-Z
-cs:
H
L
X
--
JEDEC DEFINED
PRESENCE-DETECT - MT8LD(T)432H (16MB)
s:
SYMBOL
PRD1
-7
NC
PRD2
NC
NC
PRD3
Vss
Vss
PRD4
NC
NC
PROS
NC
Vss
PRD6
NC
NC
PRO?
X'
X'
• NC
MTBLD(T)432H(S)
DM34.pm5 - Rev. 2195
-6
NC
= Normal Refresh I Vss = S version only
5-18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MTBLD(T)432H(S)
4 MEG x 32 DRAM MODULE
,,,",,co,n,
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee supply relative to Vss ............ -IV to +4.6V
Voltage on Inputs or II 0 pins
relative to Vss ..................................................... -IV to +5.5V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ............................................................. 8W
Short Circuit Output Current ..................................... 50mA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 2, 3, 6, 22) (Vee = +3.3V ±0.3V)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
8
PARAMETER/CONDITION
INPUT LEAKAGE CURRENT
Any input OV :s; VIN :s; 5.5V
(All other pins not under test = OV) for each package input
RASO,RAS2
AO-A10, WE
CASO-CAS3
111
112
113
-8
-16
-4
4
IJA
pA
pA
OUTPUT LEAKAGE CURRENT
(0 is disabled; OV :s; VOUT < 5.5V) for each package input
001-0032
loz
-10
10
IJA
VOH
2.4
OUTPUT LEVELS
Output High Voltage (lOUT =-2mA)
Output Low Voltage (lOUT =2mA)
MTSLO(f)432H(S)
DM34,pm5 - Rev. 2/95
VOL
5-19
16
NOTES
V
0.4
V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
z
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•
C
:D
):l-
s:
c
-3:
3:
ADVANCE
MICRON
1-·
MTSLD(T)432H(S)
4 MEG x 32 DRAM MODULE
"""'"''''
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1; 3, 6) (Vcc == +3.3V ±0.3V)
MAx
SYMBOL
SIZE
-6
-7
UNITS
STANDBY CURRENT: (TTL)
(RAS == CAS == VIH)
ICCl
16MB
16
16
rnA
STANDBY CURRENT: (CMOS)
Icc2
16MB
4
4
mA
Icc2
(S oniy)
16MB
1.2
1.2
mA
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC == tRC [MiN])
Icc3
16MB
960
880
mA
2,22,
26
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS == VIL, CAS, Address Cycling: IpC == IpC [MIN])
Icc4
16MB
720
640
mA
2,22,
26
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS == VIH: IRC == IRC [MIN])
Iccs
16MB
960
880
mA
22,26
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC
Iccs
16MB
960
880
mA
19,22
16MB
2.4
2.4
mA
19,22
16MB
2.4
2.4
mA
19
PARAMETER/CONDITION
z
m
:IE
II
c
:c
»
s:
-s:c
s:
(RAS
=CAS = other inputs =Vcc -0.2V)
=IRC [MIN])
REFRESH CURRENT: EXTENDED (S version only)
Average power supply current; CAS == 0.2V or CBR cycling;
Icc?
RAS== IRAS (MIN); WE == Vcc -0.2V; AO-A10 and DIN == Vcc -0.2V (S only)
or 0.2V (DIN may be left open); IRC == 62.5J..1S
REFRESH CURRENT: SELF (S version only)
Average power supply current; CBR cycling with RAS ~ IRASS
(MIN) and CAS held LOW; WE == Vcc -0.2V; AO-A10 and
DIN =Vcc -0.2V or 0.2V (Din may be left open)
MT8LD{T)432H(S)
DM34.pm5-Aev.2/95
5-20
Icc?
(S only)
Micron Technology, Inc., reserves the right to change products or
NOTES
specificati~ns
without notice.
©1995,MicronTechnology, Inc.
ADVANCE
MIC:RON
1-·
"'"'"""'"'
4 MEG
MTBLD(T)432H(S)
x 32 DRAM MODULE
CAPACITAN CE
SYMBOL
MAX
16MB
UNITS
Input Capacitance: AO-A 10
Cll
48
pF
17
Input Capacitance: WE
CI2
64
pF
17
Input Capacitance: RASO, RAS2
CI3
32
pF
17
Input Capacitance: CASO, CAS1, CAS2, CAS3
CI4
16
pF
17
InpuVOutput Capacitance: DOO-D031
CIO
10
pF
17
PARAMETER
NOTES
z
m
:e
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vcc = +3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Access time from CAS
Column-address hold time
CAS pulse width
RAS LOW to "don't care" during SELF REFRESH
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output buffer turn-off delay
FAST-PAGE-MODE READ or WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
RAS pulse width during SELF REFRESH
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
MTBLO(T)432H(S)
DM34.pmS - Rev. 2/95
-6
SVM
MIN
tAA
tAR
tASC
tASR
tCAC
ICAH
tCAS
tCHD
tCHR
tCLZ
tcp
tCPA
tCRP
tCSH
tCSR
tCWL
tDH
tDHR
tDS
tOFF
tpc
tRAC
tRAD
tRAH
tRAL
tRAS
tRASP
tRASS
tRC
tRCD
tRCH
tRCS
5-21
MAX
MIN
30
50
0
0
10
15
15
15
3
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10,000
20
15
20
15
15
3
10
35
10,000
40
5
70
5
20
15
55
a
15
10
30
60
60
100
110
20
0
0
UNITS
35
a
5
60
5
15
10
45
3
35
MAX
55
0
15
a
15
60
30
10,000
100,000
45
3
40
15
10
35
70
70
100
130
20
a
a
•
c
'7
20
70
35
10,000
100,000
50
lls
ns
ns
ns
ns
NOTES
9
27
19
25
18
19
15
15
12,25
8
23
27
13
14
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
::tJ
»
s:
-:cs::
:s::
ADVANCE
MICRON
1-·
MTBLD(T)432H(S)
4 MEG x 32 DRAM MODULE
",",,,0",,,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 3, 4, 5, 6, 7, 10, 11, 16, 21) (Vee
=+3.3V ±0.3V)
AC CHARACTERISTICS
PARAMETER
z
m
:e
II
c
::D
»
s:
Refresh period (2,048 cycles)
Refresh period (2,048 cycles) S version
RAS precharge time
RAS to CAS precharge time
RAS precharge time during SELF REFRESH
Read command hold time (referenced to RAS)
RAS hold time
Write command to RAS lead time
Transition time (rise' or fa!!)
Write command hold time
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CSR REFRESH)
WE setup time (CSR REFRESH)
-7
-6
SYM
tREF
tREF
tRP
tRPe
tRPS
tRRH
tRSH
tRWL
tT
tWCH
WCR
twcs
WP
tWRH
WRP
MIN
MAX
MIN
32
128
40
50
0
110
0
130
0
20
20
0
15
15
3
10
45
0
10
10
10
50
3
15
55
0
15
10
10
MAX
UNITS
32
128
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
NOTES
27
14
28
28
-s:c
s:
MT8LD(T)432H(S)
DM34.pm5 - Rev. 2{95
5-22
Micron Technology, Inc" reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MTBlD(T)432H(S)
4 MEG x 32 DRAM MODULE
"'""OC'"' '"
NOTES
1. All voltages referenced to V55.
2. Icc is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the output open.
3. An initial pause of lOOlls is required after power-up
followed by any eight RAS refresh cycles (RAS ONLY
or CBR with WE HIGH) before proper device
operation is assured. The eight RAS cycle wake-ups
should be repeated any time the IREF refresh
requirement is exceeded.
4. AC characteristics assume IT = 5ns.
5. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. Measured with a load equivalent to two TTL gates
and 100pF and VOL = O.S and VOH = 2.0V.
S. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
9. Assumes that IRCD ~ IRCD (MAX).
10. If CAS = VIH, data output is High-Z.
11. If CAS = VIL, data output may contain data from the
last valid READ cycle.
12. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
13. Operation within the IRCD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, then access time is
controlled exclusively by ICAe.
14. Either IRCH or IRRH must be satisfied for a READ
cycle.
MTSLO(T)432H(S)
DM34.pm5 - Rev. 2/95
15. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
16. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VII. and VIH) ina monotonic manner.
17. This parameter is sampled. Vee = +3.3V ±0.3V;
f=lMHz.
IS. If CAS is LOW at the falling edge of RAS, data-out
(Q) will be maintained from the previous cycle. To
initiate a new cycle and clear the data out buffer, CAS
must be pulsed HIGH for ICp.
19. On-chip refresh and address counters are enabled.
20. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.
21. LATE WRITE, READ-WRITE or READ-MODIFYWRITE cycles are not available due to OE being
grounded on UI-US.
22. Icc is dependent on cycle ra tes,
23. Operation within the IRA!) (MAX) limit ensures that
IRCD (MAX) can be ml'1. IRAIl (MAX) is sp""ifi,'d ,IS
a reference point only; if IRAJ) is greilter th,11I tl1<'
specified IRAD (MAX) limit, then access tinw is
controlled exclusively by t AA.
24. Applies to S version only.
25. The 3ns minimum is a parameter guaranteed hy
design.
26. Column-address changed Olin' ,'arh eyel,"
27. If the DRAM controller uses ,\ burst rl'frl'sh, iI burst
refresh must be executed upon exiting SELF REFRESH.
2S. IWTS and IWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverts of IWRP and IWRH in the
CBR REFRESH cycle.
5-23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, MiC10n Technology, Inc.
z
m
:E
III
c
:c
»
s::
-sc:
s:
ADVANCE
MIC:RON
MTBLD(T)432H(S)
4 MEG x 32 DRAM MODULE
"'~""oc,,"
1-·
READ CYCLE
'RC
RAS
VIH------~
V!L _
:~:t==LII---"R-"'R'-'-H
z
:E
I
------~~
m
•
_
__~~__ II------'~RC~D~-----,I ~ _____
r-r-----~-------------
ROY.".
,...,DDR
C
WE
::tI
»
:s:
c
s:
s:
-
Q
VIH_7T,7T,ryT,ryT,nTn7h7n7n7n7Tn±-~---~-------~--~~nTnTn7n7n7n7n7
V IL -===='-LL-'-LL-!fLLLLLLLllLLLIJ
~gr ----------OPEN---------~@t~~~j}-----OPEN----
EARLY WRITE CYCLE
'RC
tRAS
AAS
VIH VIL _
tCSH
leRP
CAS
IReD
V
V,L I _H - J
tRAD
ADDR
V,H
V,L
ROW
ROW
I
I
twcs
I
WE
VIH -
V,L
I
tRWL
'WCR
tWCH
'WP
I I
~
DON'T CARE
t883 UNDEFINED
MT8LD(T)432H(S)
DM34.pm5 - Rev. 2195
5-24
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MTBLD(T)432H(S)
4 MEG x 32 DRAM MODULE
","",CO",",
FAST-PAGE-MODE READ CYCLE
leSA
~
I_ _ _ _ _'-"Rc"'o'--_I
'PC
1____'C,,-P__1
~
I_-,,'c,,-P_ _ I
I
'RSH
~
CAS
z
m
=E
ADDR
II
c
::D
~g~
»
s
-'-------
-c3:
3:
FAST-PAGE-MODE EARLY-WRITE CYCLE
RAS
~:t =:
tpc
tCSH
tRSH
~ 1_ _ _ _ _ _tR"'c"'DC-_I_-"tc"'As"-_II_-'tc"--P_ _II_-"tc"'As'---_II_-='c"-P-_11_t-",cA",s'--_1
ADDR
~I
D
~:t
Q
~:t
MT8LO(1)432H(S)
DM34.pm5 - Rev, 2195
VALID DATA
VALID DATA
~~~~~ilU~_ _~~~~"~"L-~~~~·~'~
-.--------------------
OPEN
5-25
__
__
VALID DATA
~~
~-~~ilililililil~
----------~----~----
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notiCe.
©1995, Micron Technology, Inc.
ADVANCE
UU::::RCN
MTBLD(T)432H(S)
4 MEG x 32 DRAM MODULE
"C~"o
s:
-s:C
s:
D
:~
~:~
II
tAR
tRAD
!~.~
_
-
II
Jllllllllllillij$
I
~~
I~
!wi
i
I
~.
tpc
teAs
II
teAs
tcp
tcP
1
=:J
Ll
r==L-
lASH
I
~
1,1
wJw,g$~
--,
tAAL
-"
I-
lAse
leAH
I ::: '"7;"
I
I
,I
I
I
I
f-ii"::;;"'k////;/;/$&1///,?;
~II~
~:~ 4'111111111111111111;0"111111§1111111111~~IIIIIIIII~
VALID DATA
~IIIIIIIIIIIIIIIIIIIIj2
kri.
Q
I ""-I !
~g~ _--------;--OPEN---:---------i~X»1~!--'---OPEN----
I,
NOTE:
~
DON'TeARE
~
UNDEFINED
1. Do not drive data prior to tristate.
MT8LO(T)432H(S)
DM34.pm5 - Rev. 2/95
5-26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc
ADVANCE
UII:::RCN
1- ~
MTBLD(T)432H(S)
4 MEG x 32 DRAM MODULE
"',,",co,,,,,
RAS-ONL Y REFRESH CYCLE
(WE = DON'T CARE)
~,--------tRAS~~,------tRP_l~
%
"
CAs
~IH =:J~teRP II
~b
I~'
=~
ROW
ADDR
~:t
Q
~g~
z
tRAHI
IL-
W&7M//$$/j'//j'$/#/$/$/j'/i;X~--RO-W- -
-"---------OPEN---------
~m~
=JtcP.~
CAS
DQ
~:r-
-
teHR
II
tRAS
'==--9- ~k
tRPC
II
-
tWRP
WE
tRP
tRAS
»
3:
-J
-cs:
tCSR
OPEN-;.;-II-------tWRH
tWRP
I
tWRH
~:~ 4/'/$////0- --'W$;JW'/$//$/j- -*&/;1/$////$/;1$$$/&
SELF REFRESH CYCLE 24
(Addresses = DON'T CARE)
NOTE:
C'Zl
DON'T CARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT8LD(T)4..12H(S)
DM34.pm5- Rev. 2/95
5-27
•
==
C
Jl
CBR REFRESH CYCLE
(Addresses = DON'T CARE)
tRP
m
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
:s:
ADVANCE
MIC:RON
MTBLD(T)432H(S)
4 MEG x 32 DRAM MODULE
m~'mco",",
1-·
HIDDEN REFRESH CYCLE 20
(WE = HIGH)
(READ)
(REFRESH)
z
m
:E
•
C
ADDR
::rJ
»
s:
c
-
Q
~g~ : : - - - - - - O P E N - - - - - - 4 / I i ' M M
VALID DATA
OPEN-
~--------------------~
S
S
MTSLO(T)432H(S)
DM34.pm5 - Rev. 2/95
5-28
~
DON'T CARE
I2l2lI
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
",",ow",,,
1 MEG, 4 MEG x 64
DRAM
MODULE
8, 32 MEGABYTE, 5V, FAST PAGE
MODE, OPTIONAL SELF REFRESH
FEATURES
PIN ASSIGNMENT (Front View)
• JEDEC- and industry-standard pinout in a 168-pin,
dual-in-line memory module (DIMM)
• High-performance CMOS silicon-gate process
• Single +5V ±10% power supply
• All device pins are TTL-compatible
• Low power, 12.8mW standby; 3,600mW active, typical
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS(CBR)
and HIDDEN; optional Extended and SELF REFRESH
• All inputs are buffered except RAS
• 1,024-cycle refresh distributed across 16ms or
1,024-cycleExtended Refresh distributed across 128ms
(1 Meg x 64)
• 2,048-cycle refresh distributed across 32ms
(4 Meg x 64)
• FAST PAGE MODE (FPM) access cycle
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
-7
• Components
SO}
TSOP
16B-Pin DIMM
(DE-7) SOJ version
(DE-8) TSOP version
PIN #
1
3
4
5
6
7
12
13
14
11
1
G
• Refresh
Standard/16ms or 32
SELFREFRESH/128ms
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Blank
5
KEY TIMING PARAMETERS
SPEED
IRC
tRAC
tpc
tAA
tCAC
tRP
-6
110ns
130ns
60ns
35ns
35ns
20ns
40ns
70ns
40ns
40ns
25ns
50ns
-7
PART NUMBER
DESCRIPTION
1 Meg x 64, SOJ
MT16D164G-xx S
MT16DT164G-xx
1 Meg x 64, S*, SOJ
1 Meg x 64, TSOP
MT16DT164G-xx S
1 Meg x 64, S*, TSOP
MT16D464G-xx
4 Meg x 64, SOJ
4 Meg x 64, TSOP
MT16DT464G-xx
*S = SELF REFRESH
MT16D(T)164(S), MT16D(T)464
DM46.pm5- Rev. 2/95
[ l~
[ l3
46
47
48
4!
Vee
004
43
'ss
54
00855
009
56
0010
12
0013
0014
0015
NC
Vss
NC
NC
Vee
WED
CASO
CI\S2
11 \SO
EO
61
62
63
64
65
66
2
68
69
70
71
72
73
'ss
74
3~
\075
34
A2
76
35
A4
77
36
A6
78
37
A8
7!
38 NC/A1W' 81
39
NC
8'
40
Vee
8:
41
RFU
83
42
RFU
84
.. 4 Meg x 64 version only
VALID PART NUMBERS
MT16D164G-xx
I PIN #
SYMBOL
Vss
E2
,52
I ~
PIN # SYMBOL
0156
WE2
89
90
V"
)1
)2
5-29
[J 17
Vss
0018
0019
0020
l21
'ee
l22
RFU
RFU
RFU
RFU
0(23
24
96
97
98
103
104
105
106
107
108
109
110
0025
0026
C l27
[ l28
'ee
l29
l30
0031
111
112
113
11
115
116
1
118
119
120
'03
'05
'07
100
Vee
Vee
l36
17
131
132
133
125
126
C:5
CAS7
POE
Vee
48
49
Vss
0050
0051
0052
0053
0(
Vss
0040
0041
0042
D043
0044
lee
D045
0046
0047
NC
Vss
NC
NC
138
139
140
141
142
143
144
145
146
147
148
149
150
RFU
153
154
155
156
157
158
159
160
161
162
163
164
165
166
Vee
0054
RFU
RFU
RFU
0055
NC
056
15~
NC
RFU
Vss
A'
A3
A5
A7
A9
NC
NC
Vee
,RFU
80
•
C
:D
l>
1
)5
Iss
NC
Vss
'01
132
01133
01134
OQ35
SY IBOl
19
16
D
DT
• Packages
168-pin DIMM (gold)
SYMBOL
v's
lO
0057
0058
0059
0060
Vee
0061
0062
OQ61
NC
Vss
P02
P04
P06
P08
168
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
s:
-s:C
s:
ADVANCE
MIC::RON
1-·
•
c
:c
):-
s:
c
s-:
s:
"'""'"00""
MT16D(T)164(S), MT16D(T)464
1 MEG , 4 MEG x 64 DRAM MODULES
GENERAL DESCRIPTION
REFRESH
The MT16D(T)164(S) and MT16D(T)464 are randomly
accessed 8MB and 32MB solid-state memories organized in
a x64 configuration.
During READ or WRITE cycles, each bit is uniquely
addressed through the 20/22 address bits, which are entered 10/11 bits (AD /BO-AIO) at a time. Two copies of
address 0 (AD and BO) are defined to allow maximum
performance for 4-byte applications which interleave between two 4-byte banks. AD is common to the DRAMs used
for DQO-DQ31, while BO is common to the DRAMs used for
DQ32-DQ63. RAS is used to latch the first 10/11 bits and
CAS the latter 10/11 bits.
READ and WRITE cycles are selected with the WE input.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. EARLY WRITE occurs when WE
goes LOW prior to CAS going LOW, and the output pines)
remain open (High-Z) until the next CAS cycle.
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS HIGH time. Correct memory cell data is preserved
by maintaining power and executing any RAS cycle (READ,
WRITE) or RAS refresh cycle (RAS ONLY, CBR or
HIDDEN) so that all combinations of RAS addresses (AD /
BO-AlO) are executed at least every tREF, regardless of
sequence. The CBR REFRESH cycle will invoke the internal
refresh counter for automatic RAS addressing.
An additional SELF REFRESH mode is also available. The
"5" version allows the user the option of a fully static low
power data retention mode, or a dynamic refresh mode at
the extended refresh period. The module's SELF REFRESH
mode is initiated by executing a CBR REFRESH cycle and
holding RAS LOW for the specified tRASS. Additionally,
the "5" version allows for extended refresh rates of 1251ls
(8MB) per row if using distributed CBR REFRESH. This
refresh rate can be applied during normal operation, as well
as during a standby or extended refresh mode.
The SELF REFRESH mode is terminated by driving
RAS HIGH for the time minimum of an operation cycle,
typically tRPS. This delay allows for the completion of any
internal refresh cycles that may be in process at the time of
the RAS LOW-to-HIGH transition. If the DRAM controller
uses a distributed CBR REFRESH sequence, a burst refresh
is not required upon exiting SELF REFRESH mode. However, if the DRAM controller utilizes RAS ONLY or burst
refresh sequence, all 1,024 rows must be refreshed within
300lls prior to the resumption of normal operation.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined page
boundary. The FAST PAGE MODE cycle is always initiated
with a row-address strobed-in by RAS followed by a column-address strobed-in byCAS. CAS may be toggled-in by
holding RAS LOW and strobing-in different column-addresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the FAST PAGE MODE operation.
MT160(T)164(S), MT16D(T)464
DM46.pm5 -Rev. 2/95
5-30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
"'"'","',",
FUNCTIONAL BLOCK DIAGRAM
DOO"D03
D04" DQ7
D08" DOll
D012" D015
D016" D019
D020 .. D023
D024 .- D027
D028" D03l
AO 1D::~---iAO
WED
-1D:>---iViE
OEO 1D::,..,....---i5E
RASa - - - - - i R A S
CASO
~1D:>---iCASA1-Al0r----j
C:ASA1
CAS1,D)----'"
CAS2
-1D)----
CAS3
1D)-----
•
A10-A1
C
JJ
80
l>
WE2
s:
OE2
RAS2
-Cs:
CAS4
CASS
CAS6
s:
CAS?
1 Mall' U4
Ul·U16 1 MO!I' 4 aIiAM •
• • • • PD1.PD8
4Megx64
Ul-U16 = 4 Meg x 4 DRAMs
PDE - - - - - - - '
NOTE:
1. All inputs with the exception of RAS are redriven.
2. 0 = line buffers.
MT16D(T)t64(S), MT16D(T)464
DM46.pmS - Rev. 2/95
5-31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
ADVANCE
MICRON
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
m~"'oo""
1-·
PIN DESCRIPTIONS
•
PIN NUMBERS
SYMBOL
TYPE
30,45
RASO, RAS2
Input
Row-Address Strobe: RAS is used to clock-in the 10/11
row-address bits. Two RAS inputs allow for one x64 bank
or two x32 banks.
28,29,46,47,112,
113,130,131
CASO-7
Buffered Input
Column-Address Strobe: CAS is used to clock-in the 101
11 column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles. Eight CAS
inputs allow byte access control for any memory bank
configuration.
27,48
WEO,WE2
Buffered Input
Write Enable: WE is the REAOIWRITE control for the DO
pins. WEO controls 000-0031. WE2 controls 00320063. If WE is LOW prior to CAS going LOW, the access
is an EARLY WRITE cycle. If WE is HIGH while CAS is
LOW, the access is a READ cycle, provided OE is also
LOW. If WE goes LOW after CAS goes LOW, then the
cycle is a LATE WRITE cycle. A LATE WRITE cycle is
generally used in conjunction with a READ cycle to form a
READ-MODIFY-WRITE cycle.
31,44
OEO,OE2
Buffered Input
Output Enable: OEis the input/output control for the DO
pins. OEO controls 000·0031. OE2 controls 0032-0063.
These signals may be driven, allowing LATE WRITE
cycles.
33-38, 1.17-121, 126
AO-A1O, BO
Buffered Input
Address Inputs: These inputs are multiplexed and clocked
by RASand CAS. AO is common to the DRAMs used for
000-0031, while BO is common to the DRAMs used for
0032-0063.
2-5,7-10,13-17,19-21,
52-53, 55-58, 60, 65,
67,69-72,74-76,
86-89,91-94,97-101,
103-105, 136-137,
139-142,144,149,151,
153-156,158-160
000-0063
Input/
Output
79-82, 163-166
P01-P08
Buffered
Output
41-42,61-64,111,115,
125,128,145-148
RFU
-
6,18,26,40,49,59,73,
84,90,102,110,124,
133,143,157,168
Vcc
Supply
Power Supply: +5V ± 10%
1,12,23,32,43,54,68,
78,85,96,107,116,127,
138, 152, 162
Vss
Supply
Ground
DESCRIPTION
c
::c
»
s:
c
s:
s:
-
MT16D(T)164(S),. MT16D(T)464
DM46.pm5 - Rev. 2/95
I
Data 1/0: For WRITE cycles, 000-0063 act as inputs
to the addressed DRAM location. BYTE WRITEs
may be performed by using the corresponding CAS
select (x64 mode only). For READ access cycles,
000-0063 act as outputs for the addressed DRAM
location.
Presence-Detect: These pins are read by the host system
and tell the system the OIMM's personality. They will be
either driven to VOH (1) or they will be driven to VOL (0).
RFU: These pins should be left unconnected
(reserved for future use).
5-32
Micron Technology, Inc" reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
"'""""''''
PIN DESCRIPTIONS (continued)
PIN NUMBERS
SYMBOL
TYPE
83,167
IDO,ID1
Output
132
PDE
Input
11, 22, 24-25, 38-39,
50-51,66,77,95,106,
108-109,114,122-123,
129, 134-135, 150, 161
NC
DESCRIPTION
ID bits: IDO = DIMM type. ID1 = Refresh Mode. These
pins will be either left floating (NC) or they will be
grounded (Vss).
Presence-Detect Enabte: PDE is the READ control for the
buffered presence-detect pins.
-
No connect.
•
C
lJ
TRUTH TABLE
ADDRESSES
tR
IC
l>
DATA-IN/OUT
1m"
~
WE
TIE
"PilE
Standby
H
H~X
X
X
X
X
X
High-Z
READ
L
L
H
L
X
ROW
COL
Data-Out
FUNCTION
s:
DOO-63
~~"."
~"'-
EARLY WRITE
L
L
L
X
X
ROW
COL
Data-In
READ WRITE
L
L
H~L
L~H
X
ROW
COL
Data-Out, Data-In
L
X
ROW
COL
Data-Out
Data-Out
.~-
FAST-PAGE-MODE
1st Cycle
L
H~L
H
..------....
READ
2nd Cycle
L
H~L
H
L
X
nla
COL
FAST-PAGE-MODE
1st Cycle
L
H~L
L
X
X
ROW
COL
Data-In
EARLY,WRITE
2nd Cycle
L
H~L
L
X
X
nla
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H"""L
H~L
L~H
X
ROW
COL
Data-Out, Data-In
READ-WRITE
2nd Cycle
L
H~L
H~L
L~H
X
nla
COL
Data-Out, Data-In
H
X
X
X
X
ROW
nla
High-Z
Data-Out
Data-In
RAS-ONLY REFRESH
..
HIDDEN
READ
L~H~L
L
H
L
X
ROW
COL
REFRESH
WRITE
L~H~L
L
L
X
X
ROW
COL
CSR REFRESH
H~L
L
H
X
X
X
X
High-Z
SELF REFRESH (S version)
H~L
L
H
X
X
X
X
High-Z
X
X
X
X
L
X
X
Not Affected
READ PRESENCE-DETECTS
MT16D(T)164(S), MTI6D(T)464
DM46.pmS - Rev, 2/95
5-33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
-C3:
3:
ADVANCE
MICRON
1-·
m~'oco","'
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
PRESENCE-DETECT TRUTH TABLE
•
C
JJ
»
S
s:
C
Access Timing
s:
Refresh Control
Data Width, Parity
NOTE: Vss = ground; 0 = VOL; 1 = VOH.
* This addressing includes a redundant address to allow mixing of 12/10 and 11/11 DRAMs with the same presence-detect
setting. The MT16D(T)464 uses 11/11 DRAMs.
MT16D(T)164(Sj. MT16D(T)464
DM46.pm5 ~ Rev. 2/95
5-34
Micron Technology, Inc., rsservesthe right to change products or spe cificationswithoutnotice
©1995, Micron Technology, Inc
ADVANCE
MICRON
1-·
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
""'''0",'",
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1,6,7) (Vcc = +5V ±1 0%)
PARAMETER/CONDITION
SYM
MIN
MAX
UNITS
Supply Voltage
Vcc
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
Vcc+0.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-0.5
0.8
V
ill
-2
2
flA
RASO,2
112
-16
16
flA
000-0063
P01-P08
loz
-10
10
flA
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV :; VIN :; 5.5V
(All other pins not under test = OV) for each package input
OUTPUT LEAKAGE CURRENT
(0 is disabled; OV :; VOUT:; 5.5V) for each package input
CASO-CAS7
AO-A 10, BO, POE
WEO,2,OEO,2
OUTPUT LEVELS
Output High Voltage (lOUT = -5mA)
Output Low Voltage (lOUT = 4.2mA)
NOTES
•
c
:c
V
VOL
0.4
V
l>
s:
MAX
PARAMETER/CONDITION
-7
32
52
32
52
mA
28
8MB
32MB
Icc2
8MB
(S only) 32MB
16
28
3.2
16
28
3.2
-
mA
28
mA
3,4,
28,32
mA
3,4,
28,32
mA
3,28,
ICCI
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
ICC2
OPERATING CURRENT: Random REAOIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIN])
ICC3
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS =VIL, CAS, Address Cycling: tpc =tpc [MIN])
ICC4
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: tRC = tRC[MIN])
Icc5
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MIN])
Icc6
REFRESH CURRENT: Extended (S version only)
Average power supply current; CAS = 0.2V or CBRcycling;
RAS = tRAS (MIN); WE= Vcc -0.2V; AO/BO-A10 and DIN = Vcc -0.2V
or 0.2V (DIN may be left open); tRC = 1251ls (8MB)
Icc7
(S only)
REFRESH CURRENT: SELF (S version only)
Average power supply current; CBR cycling with RAS ~ tRASS (MIN)
and CAS held LOW; WE = Vcc -0.2V; AO/BO-A 1o and
DIN =Vcc -0.2V or 0.2V (DIN may be left open)
Iccs
(S only)
MT16D(T)164(S), MT16D(T)464
DM46.pm5 - Rev. 2195
5-35
UNITS NOTES
-6
8MB
32MB
SYMBOL SIZE
STANDBY CURRENT: (TTL)
(RAS = CAS = VI H)
-
8MB
1,760
1,600
32MB
1,920
1,760
8MB
1,280
1,120
32MB
1,440
1,280
8MB
1,760
1,600
32MB
1,920
1,760
8MB
1,760
1,600
32MB
1,920
1,760
8MB
4.8
4.8
32MB
-
-
8MB
4.8
4.8
32MB
-
-
32
mA
3,5,
28
mA
3,5,
31
mA
5,36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
-Cs:
s:
ADVANCE
MICRON
1-·
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
"'""0"",'"
*Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RA TINGS*
U
Voltage on Vee Supply Relative to Vss .............. -IV to +7V
Operating Temperature, TA (ambient) .......... DoC to +70°C
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ........................................................... I6W
Short Circuit Output Current ...................................... SOmA
CAPACITANCE
•
C
::D
l>
s:
-s:
C
s:
MAX
UNITS
NOTES
Input Capacitance: AO-A 10. 80
SYMBOL
C!1
9
pF
2
Input Capacitance: WEO, WE2, OEO, OE2
CI2
9
pF
2
Input Capacitance: RASO, RAS2
CI3
64
pF
2
Input Capacitance: CASO - CAS7
CI4
9
pF
2
Input/Output Capacitance: 000-0063
Cio
10
pF
2
Output Capacitance: P01-P08
Co
10
pF
2
PARAMETER
MIN
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9,10,11,12,13) (Vcc
=+5V ±10%)
-6
AC CHARACTERISTICS
PARAMETER
SYM
Access time from column-address
tAA
Column-address hold time (referenced to RAS)
tAR
Column-address setup time
Row-address setup time
tASC
tASR
Column-address to WE delay time
tAWD
Access time from CAS
tCAC
.Column-address hold time
CAS pulse width
tCAH
RAS lOW to "don't care" during SELF REFRESH
CAS hold time (CBR REFRESH)
tCHD
tCHR
CAS to output in low-Z
tClZ
tcp
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
tCAS
tCRP
tCSH
tCSR
tCWD
Write command to CAS lead time
tCWl
tDH
Output disable
tDHR
tDS
too
Output enable
OE hold time from WE during READ-MODIFY-WRITE cycle
tOEH
Output buffer turn-off delay
tOFF
MT16D(T)164(S), MT16D(T)464
DM46.pm5 - Rmy. 2f95
48
2
5
57
MIN
15
15
15
13
5
10
UNITS
NOTES
40
ns
25
24
23
25
23,30
15,25
25
10,000
15
58
12
42
15
15
45
-2
ns
ns
ns
ns
25
20
20
15
13
5
10
40
10,000
ns
ns
ns
ns
ns
ns
ns
36
5,24
23,33
16
25
25
24
5,23
23,30
ns
ns
ns
ns
-2
20
ns
ns
ns
15
68
12
52
20
20
55
20
20
20
5
ns
ns
45
15
15
15
5
MAX
53
2
5
67
20
tOE
5-36
-7
MAX
35
tCPA
CAS to WE delay time
Data-in hold time
Data-in hold time (referenced to ~)
Data-in setup time
MIN
24,29
ns
ns
ns
25
25,29
ns
24
20,27
Micron Technology, Inc., reserves the right to change products or specilications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
m~"OCOG'"'
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10,11,12, 13) (Vee = +5V ±1 0%)
-6
AC CHARACTERISTICS
PARAMETER
OE setup prior to RAS during HIDDEN REfRESH cycle
fAST-PAGE-MODE READ or WRITE cycle time
PDE to valid presence-detect data
PDE inactive to presence-detects inactive
FAST·PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-addresshold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
RAS pulsewidth during SELf' REFRESH
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (1,024 cycles) - 1 Meg x 64
Refresh period (2,048 cycles) - 4 Meg x 64
Refresh period (2,048 or 1,024 cycles) S version
RAS precharge time
RAS to CAS precharge time
RAS precharge time during SELF REFRESH
Read command hold time (referenced to RAS)
RAS hold time
READ WRITE cycle time
RAS to WE delay time
MT160(n164(S), MT16D(T)464
OM46.pm5 - Rev. 2/95
MIN
tORD
tpc
tpD
0
35
tpDOFF
tpRWC
2
87
tRAC
tRAD
tRAH
tRAL
tRAS
c
Write command toRAS I.ead time
Transition time (rise or fali)
.'
Write command hold time
Write command hold time (referenced to RAS)
WE comma.nd setup time
Write command pulse width
WE holiJ'time (CBRREFRESH)
WE setup time (CBRREFRESH)
...
SYM
tRASP
tRASS
tRC
tRCD
tRCH
tRCS
tREF
tREF
tREF
tRP
tRPC
tRPS
tRRH
tRSH
tRWC
tRWD
tRWL
IT
tWCH
twCR
twcs
twp
,
twRH
twRP
-7
MAX
MIN
10
13
8
35
60
60
100
110
18
2
2
MAX
0
40
10
2
97
60
25
10,000
100,000
40
13
8
40
70
70
100
130
18
2
2
16
32
128
40
0
110
0
20
155
92
20
3
15
43
2
10
8
12
,
50
70
30
10,000
100,000
45
16
32
128
". 50
0
130
0
25
185
102
25
3
20
53
2
15
8
12
50
UNITS
NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
Ils
ns
ns
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
34
23
14
18,26
24
25
C
::D
36
17,26
19.23
23
l>
3:
---
i:
36
19
25
25
23,30
25
25
24
23
22,24
22,23
..
5-37
-i:c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, 'Inc.
ADVANCE
MICRON
1-·
"'""''"'"
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
NOTES
•
C
:D
»
3:
-3:c
3:
1. All voltages referenced to Vss.
2. This parameter is sampled. Vee = +SV ±lO%;
f= 1 MHz.
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading. Specified values
are obtained with minimum cycle time and the
outputs open.
S. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOO!!s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
8. AC characteristics assume tT = Sns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification,
all input signals must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS =VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and lOOpF.
14. Assumes that tRCD < tRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, tRAC will increase by the amount that tRCD
exceeds the value shown.
IS. Assumes that tRCD ~ tRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for tcP.
17. Operation within the tRCD (MAX) limit ensures that
tRAC (MAX) can be met. tRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by tCAe.
18. Operation within the tRAD (MAX) limit ensures that
tRAC (MIN) and tCAC (MIN) can be met. tRAD
(MAX) is specified as a reference point only; if tRAD is
greater than the specified tRAD (MAX) limit, access
time is controlled exclusively by tAA.
MT16D(T)164(S), MTI6D(T)464
DM46.pm5 -Rev. 2/95
19. Either tRCH or tRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE = LOW and
OE = HIGH.
22. twTs and tWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverse of twRP and twRH in the
CBR REFRESH cycle.
23. A +2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
24. A -2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
2S. A +Sns timing skew from the DRAM to the module
resulted from the addition of line drivers.
26. A -2ns (MIN) and a -Sns (MAX) timing skew from the
DRAM to the module resulted from the addition of
line drivers.
27. A +2ns (MIN) and a +Sns (MAX) timing skew from
the DRAM to the module resulted from the addition
of line drivers.
28. The maximum current ratings are based with the
memory operating or being refreshed in the x64
mode. The stated maximums may be reduced by
approximately one-half when used in the x32 mode.
29. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
30. twcs, IRWD, tAWD and tCWD are not restrictive
operating parameters. twcs applies to EARLY WRITE
cycles. tRWD, tAWD and tCWD apply to READMODIFY-WRITE cycles. IftwCS~ IWCS (MIN), the
cycle is an EARLY WRITE cycle and the data output
will remain an open circuit throughout the entire
cycle. If IRWD ~ IRWD (MIN), IAWD ~ IAWD (MIN)
and ICWD ~ ICWD (MIN), the cycle is a READMODIFY-WRITE and the data output will contain
data read from the selected cell. If neither of the above
conditions is met, the state of data-out is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. twcs, IRWD, ICWD and IAWD are not
applicable in a LATE WRITE cycle.
5-38
Micron Technology, Inc., reserves the right to change products or specfj'icalions without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
"'"'0,""'''
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
NOTES (continued)
31. Refresh current increases if tRAS is extended beyond
its minimum specification.
32. Column-address changed once each cycle.
33. The 3ns minimum parameter guaranteed by design.
34. tpDOFF MAX is determined by the pull-up resistor
value. Care must be taken to ensure adequate
recovery time prior to reading valid up-level on
subsequent DIMM position.
35. Measured with the specified current load and 100pf.
36. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
•
c
::c
»
:s
-:sc
s:
MT16D(T)164(S), MT16D(T)464
DM46.pm5 - Rev. 2/95
5-39
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
"'~~oco,,"
1-·
READ CYCLE
RAS
VIH VIL _
--c';=CSH"---_1
1_ _ _ _ _ _
CAs
•
VIH-J
.r::
'CRP
V1L -
tRRH
ROW
ADDR
C
:D
WE
~:t $$#/////$;;Jr#/#/$
i-._-+1
-c"'RA'--C_ I
_'CAG
I~
»
s:
DO
-cs:
DE
~:gt -'---------OPEN----~~~V~AlID~DA~TAj_--OPEN-~:t
I
ml
I~ too
'DE
PIIIIIIIIIIII1//1//11//1&1/11&/;
=.7T.1j/;'7T/'j/;T771//;777/j/777/j;7Ti0'j;=0'/;'7T0'/;T77;/
#;7771//;777//;7Ti0'/;=;/
#;'7T1//;T77m7770'/;777~7TTW
s:
EARLY WRITE CYCLE
tRP
'RAS
-
fr:
\
tCSH
~J
AODR
~I~
'CRP
~
tRCD
tAR
I
tRAD
I
I
·t
I~ ~I
I~I I~I
ROW
COLUMN
~J(
~
~
I
I·
ROW
'CWL
I
I
'wes
I
I
I I
II II
MT16D(T)164{S), MT16D(T)464
DM46.pm5 - Rev. 2195
tRAL
5-40
'AWL
IWGR
'WCH
twp
tOHA
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves Ihe right to change products or specifications without notice.
©1995,MlcronTechnology,lnc.
ADVANCE
MICRON
1-·
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
","",COO""
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
Rwe
r-====L
lCSH
d~
I : '"
I~ ~I
I
tRAD
ADDR
~1~
=
~.::
'RCD
ROW
t
I
'RAL
I
I'RWO
I'ewo
I~I
I
WI/I//II////I/////;j
COLUMN
~
I
I
. ~I I~~--!
___
I
I_'RP
'RAS
I
I
'AWO
W~d'i
I
:::e
I
'eAe
~
~~ffi
•
C
lJ
»
1:-
'CLZ-
ROW
lewlil
I~
VALID DOUT
OPEN
K
~I
~
s:
~\
VALID DIN
-cs:
01'1 N
~
s:
FAST-PAGE-MODE READ CYCLE
'RP
Ipe
tCSH
I~ tCRP ,
·J1.J
AODR
~:r ~
ROW
'cAS
tRCD
tRAH~1
~I I~
.KiW
COLUMN
IRCS
- -i'6l/!Z0
WII;/;::1;'>
~
I
'RCH-
I 1:I
-
I
tCPA
I~
2!.
tCLZ-
tcLZOPEN
tRCH
1:-
4-'-'
-
I~
~ ~
I
I
ROW
COLUMN
-I
~
-- IL'RCS
I
I
'eLZ-
VALID
bATA
VALID
DATA
~ ~
II
IRAL
~Il tCAH~1
celUMN
__ IL'RCS
tRAC
'CAG
leAH.1
'Ase
lop
~y
t~
'AR
tRAD
~
'RSH
_'c_P_~ _'_ep~
'CPA
'CAG
1:--
-
_IOFF
VALID
~
DATA
--tRRH
~ ~
liZ] DON'T CARE
~
MTI60(T)I64(S), MTI60(T)464
DM46.pm5 - Rev. 2/95
5-41
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
"'"",coo",,
MT16D(T)164(S), MT16D(T)464
1 MEG,4 MEG x 64 DRAM MODULES
FAST-PAGE-MODE EARLY-WRITE CYCLE
•
C
Jl
»
s:
-:s::c
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODiFY-WRITE cycles)
:s::
[ZJ DON'T CARE
188lI UNDEFINED
MT16D{T}164(S), MT16D(T)464
DM46.pm5 - Rev. 2/95
5-42
Micron TechnOlogy, Inc., rssetv9sthe right to change prodLJcts orspecificationswithou\ no tice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
"'"'''''''''
RAS-ONl Y REFRESH CYCLE
(WE = DON'T CARE)
DQ
~gt
-,-------------OPEN--------
•
c
:c
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODiFY-WRITE)
»
s:
-sc:
ICSH
s:
ADDR
Q
~:~::::
~gt = - - - - 7
- , OPEN
I.
NOTE 1
1-----0PEN
'RAG 'AA
- - -
"
1
5E
~:~
fi'..LLLL;"'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~
DON'T CARE
PZ
:s:
-c3:
3:
PRESENCE-DETECT READ CYCLE
PD1-PD8
NOTE:
i1
lt~,
PD
, - - - VAL_'DPRESENCE.DETE_"
t
~
DON'T CARE
~
UNDEFINED
1. PO pins must be pulled HIGH at next level of assembly.
MT16D(T)164(S), MT16D(T)464
DM46.pm5 - Rev. 2/95
5·45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
UII:::I=ICN
1-·
",""coo,,",
MT16D(T)164(S), MT16D(T)464
1 MEG, 4 MEG x 64 DRAM MODULES
II
c
:c
l>
s:
-sC:
s:
MT16D(T)164(S), MTI6D(T)464
DM46.pm5 - Rev, 2195
5-46
Micron Technology, Inc" reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc,
PRELIMINARY
1"I1r:::I=ICN
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
"'"""oe""
1 MEG, 4 MEG x 64
DRAM
MODULE
8, 32 MEGABYTE, 3.3V, OPTIONAL SELF
REFRESH, FAST PAGE OR EDO PAGE
MODE
FEATURES
• JEDEC and industry-standard pinout in a 168-pin,
dual-in-line memory module (DIMM)
• High-performance CMOS silicon-gate process
• Single +3..3V ±O..3V power supply
• All device pins are TTL-compatible
• Low power, 16mW standby; 2,880mW active, typical
(32MB)
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN; optional Extended and SELF REFRESH
• All inputs are buffered except RAS
• 1,024-cycle refresh distributed across 16ms or
1,024-cycle Extended Refresh distributed across 128ms
(1 Meg x 64)
• 2,048-cycle refresh distributed across 32ms or
2,048-cycle Extended Refresh distributed across 128ms
{4 Meg x 64)
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• 5V tolerant I/Os (5.5V maximum VIH level)
PIN ASSIGNMENT (Front View)
168-Pin DIMM
(DE-g) SOJ Version
(DE-10) TSOP Version
t:QQDD DDDDJ
PIN# SYMBOL PIN # SYMBOL
Vss
1
Vss
43
2
000
44
N2
45
"RAS2
3
001
4
002
46
GAS4
47
5
003
GAS6
WE'[
Vee
48
6
7
004
49
Vee
8
005
50
NC
NC
9
006
51
10
007
52
0016
11
NC
53
0017
Vss
12
Vss
54
13
008
55
0018
14
009
56
0019
57
15
0010
0020
16
0011
58
0021
17
0012
59
Vee
18
Vee
60
0022
19
61
RFU
0013
20
0014
62
RFU
RFU
21
0015
63
64
RFU
NC
22
23
Vss
65
0023
24
NC
66
NC
0024
25
Nc
67
26
Vee
68
Vss
27
WED
69
0025
OQ26
28
CASO
70
29
71
0027
CAS2
OQ28
30
RASO
72
Vee
31
OEO
73
74
32
Vss
0029
33
AO
75
0030
0031
34
A2
76
35
A4
77
NC
36
A6
78
Vss
POl
37
A8
79
NC/A10'
P03
38
80
NC
81
P05
39
P07
40
Vee
82
41
RFU
100
83
42
RFU
84
Vee
•4 Meg x 64 version only
MARKING
OPTIONS
• Timing
60ns access
70ns access
• Components
SOJ
TSOP
• Packages
168-pin DIMM (gold)
• Access Cycle
FAST PAGE MODE
EDO PAGE MODE (4 Meg x 64 only)
• Refresh
Standard/16ms or 32ms
SELFREFRESH/128ms
-6
-7
D
DT
G
Blank
X
Blank
S
KEY TIMING PARAMETERS
EDO option
SPEED
-6
·7
IRC
110ns
l30ns
IRAC
60ns
70ns
IpC
25ns
30ns
1M
35ns
40ns
ICAC
20ns
25ns
ICAS
10ns
l2ns
IRAC
60ns
70ns
IpC
35ns
40ns
1M
35ns
40ns
ICAC
20ns
25ns
tRP
40ns
50ns
FPM option
SPEED
-6
-7
IRe
110ns
l30ns
MT16LD{T)164(S), MT16lD(T)464(X){S)
DM47.pm5 - Rev. 2195
5-47
PIN # SYMBOL
85
Vss
0032
86
87
0033
88
0034
89
0035
90
Vee
91
0036
92
0037
93
0038
94
0039
NC
95
96
Vss
97
0040
98
0041
99
0042
0043
100
0044
101
102
Vee
0045
103
0046
104
0047
105
106
NC
Vss
107
108
NC
109
NC
110
Vee
111
RFU
112
CAS1
113
CAS3
11
NC
115
RFU
116
Vss
117
Al
118
A3
119
A5
120
A7
121
A9
122
NC
123
NC
124
Vee
125
RFU
126
BO
PIN # SYMBOL
127
Vss
128
RFU
129
NC
130
"CAS5
131
CAS7
13?
PDr
Vet:
133
134
NC
135
NC
136
0048
137
0049
138
Vss
139
0050
140
0051
141
0052
142
0053
143
Vee
0054
144
145
RFU
146
RFU
147
RFU
148
RFU
149
0055
NC
150
151
0056
152
Vss
0057
153
154
0058
155
0059
156
0060
157
Vee
158
0061
159
0062
160
0063
NC
161
Vss
162
163
P02
164
P04
P06
165
166
P08
167
101
168
Vee
Micron Technology, Inc., reserves the right to change products or specifications vyithout notice,
©1995, Micron Technology, Inc.
•
C
::D
l>
5
c
-
3:
s:
PRELIMINARY
MICRON
1-·
,,,","COO,,,,
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
VALID PART NUMBERS
PART NUMBER
1 Meg x 64 FPM, SOJ
MT16LD164G-xx S
MT16LDT164G-xx
1 Meg x 64 FPM, SOJ, S*
MT16LDT464G-xx
MT16LDT464G-xx X
MT16LDT464G-xx S
II I
c
lJ
»
3:
c
s:
s:
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined page
boundary. The FAST PAGE MODE cycle is always initiated
with a row-address strobed-in by RAS followed by a column-address strobed-in by CAS. CAS may be toggled-in by
holding RAS LOW and strobing-in different column-addresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the FAST PAGE MODE operation.
DESCRIPTION
MT16LD164G-xx
MT16LDT164G-xx S
FAST PAGE MODE
1 Meg x 64 FPM, TSOP
1 Meg x 64 FPM, TSOP, S*
4 Meg x 64 FPM, TSOP
4 Meg x 64 EDO, 1S0P
4 Meg x 64 FPM, TSOP, S*
MT16LDT464G-xx XS
4 Meg x 64 EDO, TSOP, S*
EDO PAGE MODE - 4 Meg x 64 only
MT16LD464G-xx
MT16LD464G-xx X
4 Meg x 64 FPM, SOJ
4 Meg x 64 EDO, SOJ
MT16LD464G-xx S
4 Meg x 64 FPM, SOJ, S*
MT16LD464G-xx XS
4 Meg x 64 EDO, SOJ, S *
EDO PAGE MODE, designated by the "X" version, is an
accelerated FAST PAGE MODE cycle. The primary advanta~e of EDO is the availability of data-out even after CAS
g;es back HIGH. EDO provides for CAS precharge time
(tcP) to occur without the output data going invalid. This
elimination of CAS output control provides for pipeline
READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS. EDO-PAGE-MODE DRAMs operate similar to FASTPAGE-MODE DRAMs, except data will remain valid or
become valid after CAS goes HIGH during READs, provided RAS and OE are held LOW. If OE is pulsed while
RAS and CAS are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If OE is toggled or
pulsed after CAS goes HIGH while RAS remains LOW,
data will transition to and remain High-Z.
If the DQ outputs are wire OR'd, OE must be used to
disable idle banks of DRAMs. Alternatively, pulsing WE to
the idle banks during CAS HIGH time will also High-Z the
outputs. Independent of OE control, the outputs will disable after tOFF, which is referenced from the rising edge of
RAS or CAS, whichever occurs last (reference the
MT4LC4M4E8(S) DRAM data sheet for additional information on EDO functionality).
*S = SELF REFRESH
GENERAL DESCRIPTION
The MT16LD(T)164(S) and MT16LD(T)464(X)(S) are randomlyaccessed 8MB and 32MB solid-state memories organized in a x64 configuration. They are specially processed to
operate from 3.0V to 3.6V for low voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 20/22 address bits, which are entered 10/11 bits (AD /BO-AID) at a time. Two copies of
address 0 (AD and BO) are defined to allow maximum
performance for 4-byte applications which interleave between two 4-byte banks. AD is common to the DRAMs used
for DQO-DQ31, while BO is common to the DRAMs used for
DQ32-DQ63. RAS is used to latch the first 10/11 bits and
CAS the latter 10/11 bits.
READ and WRITE cycles are selected with the WE input.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. EARLY WRITE bccurs when WE
goes LOW prior to CAS going LOW, and the output pin(s)
remain open (High-Z) until the next CAS cycle.
MT16LD(T)164(S), MT16LD(T)464(X)(S)
DM47.pm5 - Rev, 2195
5-48
Micron Technology, Inc., reserves the right to change products or specillcationswithoutnotice.
©1995, Micron Technology. Inc.
PRELIMINARY
MICRON
1-·
,MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
"',,,,,,,,,,
REFRESH
the "s" version allows for extended refresh rates of 625fls
(32MB) and l25fls (8MB) per row if using distributed CBR
REFRESH. This refresh rate can be applied during normal
operation, as well as during a standby or extended refresh
mode,
The SELF REFRESH mode is terminated by driving RAS
HIGH for the time minimum of an operation cycle, typically
IRps, This delay allows for the completion of any internal
refresh cycles that may be in process at the time of the
RAS LOW-to-HIGH transition, If the DRAM controller uses
a distributed CBR REFRESH sequence, a burst refresh is not
required upon exiting SELF REFRESH mode, However, if
the DRAM controller utilizes RAS ONLY or burst refresh
sequence, all 1,024/2,048 rows must be refreshed within
300fls prior to the resumption of normal operation,
Returning RAS and CAS HIGH terminates a memory
cycle, and decreases chip current to a reduced standby leveL
Also, the chip is preconditioned for the next cycle during
the RAS HIGH time, Correct memory cell data is perserved
by maintaining power and executing any RAS cycle (READ,
WRITE) or RAS refresh cycle (RAS ONLY, CBR or HIDDEN) so that all combinations of RAS addresses (AO/BOAlO) are executed at least every IREF, regardless of sequence. The CBR REFRESH cycle will invoke the internal
refresh counter for automatic RAS addressing.
An optional SELF REFRESH mode is also available, The
"S" version allows the user the option of a fully static, lowpower, data-retention mode, or a dynamic refre'sh mode at
the extended refresh period, The module's SELF REFRESH
mode is initiated by executing a CBR REFRESH cycle and
holding RAS LOW for the specified tRASS, Additionally,
000" 003
004" 007
008"0011
0012" 0015
0016" 0019
0020" D0?3
[)rl?< .. IJO?!
D()?I1·· [)O:i\
t tt!
tttt
tt! t
tt t t
ttt t
!! !!
!! II
It! !
DQ1-4
AD
001-4
AO
OQ1-4
WE
U2
DQ1-4
-------1
DE
AD
OQ1-4
WE
WE
U3
OE
RAsa
AD
U4
DE
AO DCJ1""
RAS
DE
AO D01-4
U6
RAS
CASO
DE
AO
D01-4
WE
WE
WE
U5
U7
U8
DE
RAS
RAS
CASA1-AtO
CAS A1-AtD
0056" 0059
0060" 0063
AtD-A1
ttt I
AO OQ1-4
WE
WE2
DE
RAS2
RAS
AD
WE
WE
U9
OQ1-4
Ull
U12
OE
DE
RAS
RAS
CAS4
tit t
AD
001-4
WE
DE
U13
!lit
AO 001-4
Ill!
t ttt
An 001-4
AO
WE
WE
U15
DE
DE
D01-4
U16
RAS
RAS
CAS Al-AlD
CASA1-AtD
'CAS6
1 Meg x 64 - MT16L0T164G(S)
U1-U16 = MT4LC400IJ(S) FAST PAGE MODE
• • • • PD1-PD8
4 Meg x 64 . MT16LO(T)464G(S)
UI-U16 = MT4LC4M4B1(S) FAST PAGE MODE
POE - - - - - '
NOTE:
4 Meg x 64 - MTI6LO(T)464G XIS)
U1-U16 = MT4LC4M4E8(S) EOO PAGE MODE
1, All inputs with the exception of RAS are redriven,
2, 0 = line buffers.
MT16LD(T)164(S), MT16lD(T)4B4(X)(S)
DM47.pm5- Rev. 2/95
5-49
C
:0
»
s:
FUNCTIONAL BLOCK DIAGRAM
AO
•
Micron Technology, Inc., reserves the right to cI1ange products or specifications witho!Jt notice.
©1995, Micron Technology, Inc.
c
3:
s:
-
PRELIMINARY
1"'1IC:I=ICN
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
"'""'"''''
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
30,45
RASO,RAS2
Input
Row-Address Strobe: RAS is used to clock-in the 10/11
row-address bits. Two RAS inputs allow for one x64 bank
or two x32 banks.
28,29,46,47,112,
113,130,131
CASO-7
Buffered Input
Column-Address Strobe: CAS is used to clock-in the 10/
11 column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles. Eight CAS
inputs allow byte access control for any memory bank
configuration.
74.8
2.,
IAI
11 \NE2
.. E_,
31,44
OEO,OE2
Buffered Input
Output Enable: OE is the input/output control for the DO
pins. OED controls 000-0031. OE2 controls 0032-0063.
These signals may be driven, allowing LATE WRITE
cycles.
33-38,117-121,126
AO-Al0, BO
Buffered Input
Address Inputs: These inputs are multiplexed and
clocked by RAS and CAS. AD is common to the DRAMs
used for 000-0031, while BO is common to the DRAMs
used for 0032-0063.
2-5,7-10,13-17,19-21,
52-53, 55-58, 60,65, 67,
69-72,74-76,86-89,
91-94,97-101,103-105,
136-137,139-142,144,
149,151,153-156,
158-160
000-0063
Input/
Output
Data I/O: For WRITE cycles, 000-0063 act as inputs
to the addressed DRAM location. BYTE WRITEs may
be performed by using the corresponding CAS select
(x64 mode only). For READ access cycles, 000-0063
act as outputs for the addressed DRAM location.
79-82, 163-166
PD1-PD8
Buffered
Output
41-42, 61-64, 111, 115,
125, 128, 145-148
RFU
6,18,26,40,49,59,73,
84, 90, 102, 110, 124,
133,143,157,168
Vcc
Supply
Power Supply: +3.3V ± 0.3V
1,12,23,32,43,54,68,
78,85,96,107,116,127,
138,152,162
Vss
Supply
Ground
MT16LD(T)1641S), MT16LD(ll464(X)(S)
DM47.pm5 - Rev. 2/95
,
I:!
~uf,ered
I
DESCRIPTION
I, ,put
~
-
I Write. Enable. WE
'
.-
..
IS the READIWRII E control TOr the DO
pins. WED controls 000-0031. WE2 controls 0032DQ63. if WE is LOW prior to CAS going LOW, the access
is an EARLY WRITE cycle. If WE is HIGH while CAS is
LOW, the access is a READ cycle, provided OE is also
LOW. If WE goes LOW after CAS goes LOW, then the
cycle is a LATE WRITE cycle. A LATE WRITE cycle is
generally used in conjunction with a READ cycle to form a
READ-MODIFY-WRITEcycle.
Presence-Detect: These pins are read by the host system
and tell the system the DIMM's personality. They will be
either driven to VOH (1) or they will be driven to VOL (0).
RFU: These pins should be left unconnected
(reserved for future use).
5-50
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc
PRELIMINARY
MIC:RON
1-·
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
"'"",co,,,",
PIN DESCRIPTIONS (continued)
PIN NUMBERS
SYMBOL
TYPE
83,167
IDO,ID1
Output
132
PDE
Input
11, 22, 24-25, 38-39,
50-51, 66, 77, 95, 106,
108-109,114,122-123,
129,134-135,150,161
NC
DESCRIPTION
ID bits: IDO = DIMM type. ID1 = Refresh Mode. These
pins will be either left floating (NC) or they will be
grounded (Vss).
Presence-Detect Enable: PDE is the READ control for the
buffered presence-detect pins.
-
No connect.
III
c
TRUTH TABLE
lJ
ADDRESSES
IR
IC
RAS"
"CAS"
WE
or
POE
Standby
H
H---X
X
X
X
X
X
High-Z
READ
L
L
H
L
X
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
X
ROW
COL
Data-In
FUNCTION
--------.000-63
L
L
H-L
L-H
X
ROW
COL
Data-Out, Data-In
EDO/FAST-PAGE-
1st Cycle
L
H-L
H
L
X
ROW
COL
Data-Out
MODE READ
2nd Cycle
L
H-L
H
L
X
n/a
COL
Data-Out
EDO/FAST-PAGE-
1st Cycle
L
H-L
L
X
X
ROW
COL
Data-In
L
H-L
L
X
X
n/a
COL
Data-In
COL
Data-Out, Data-In
COL
Data-Out, Data-In
READ WRITE
l>
S
C
DATA-IN/OUT
-3:
3:
MO_.
MODE EARLY-WRITE 2nd Cycle
EDO/FAST-PAGE-
1st Cycle
L
H-L
H-+L
L-H
X
ROW
MODE READ-WRITE
2nd Cycle
L
H-'L
H-L
L-+H
X
n/a
H
X
X
X
X
ROW
n/a
High-Z
HIDDEN
READ
L-H-L
L
H
L
X
ROW
COL
Data-Out
REFRESH
WRITE
Data-In
RAS-ONLY REFRESH
L-+H-L
L
L
X
X
ROW
COL
CBR REFRESH
H-L
L
H
X
X
X
X
High-Z
SELF REFRESH (S version)
H-L
L
H
X
X
X
X
High-Z
X
X
X
X
L
X
X
Not Affected
READ PRESENCE-DETECTS
MT16LO(T)i64(S), MT16LD{T)464{X)(S)
DM47.pmS - Rev. 2195
5-51
Micron Technology, Inc., reselVes the right to change products or specifications without notice,
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
F·
""'OW"""
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
PRESENCE-DETECT TRUTH TABLE
II
c
lJ
»
s::
-3:C
Access Timing
3:
Refresh Control
Data Width, Parity
NOTE: Vss = ground; 0 = VOL; 1 = VOH.
* This addressing includes a redundant address to allow mixing of 12110 and 11/11 DRAMs with the same presence-detect
setting. The MT16LD(T)464 uses 11/11 DRAMs.
MT16LO(T)164(S), MT16LD(T)464(X}(S)
DM47.pm5 - Rev. 2195
5-52
Micron Technology, Inc., reserves !he right to change produclsor specilicalionswithoutnotice.
©1995,MlcronTechnology,lnc.
PRELIMINARY
MICRON
1-·
,,,""CO,,,,,
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +3.3V ±0.3V)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
PARAMETER/CONDITION
Vcc
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
111
-2
2
/lA
RASO,2
112
-16
16
/lA
DOO-D063
loz
-10
10
/lA
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV 0; VIN 0; 5.5V
(All other pins not under test = OV) for each package input
OUTPUT LEAKAGE CURRENT
(a isdisabled; OV 0; VOUT 0; 5.5V) for each package input
CASO-CAS7
AO-A10, BO
WEO,2,OEO,2
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
NOTES
II
c
V
VOL
0.4
:::c
»
s:
V
MAX
PARAMETER/CONDITION
-6
-7
8MB
32MB
16
32
16
32
mA
28
Icc2
ALL
Icc2
8MB
(S only) 32MB
8
1.6
2.4
8
1.6
2.4
mA
28
8MB
1,280
1,120
mA
32MB
1,920
1,760
3,4,
28,32
mA
3,4,
28,32
mA
3,4,
28,32
mA
3,28,
32
mA
3,5,
28
mA
3,5,
31
mA
5,36
SYMBOL SIZE
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
Icct
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc ·0.2V)
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC = 'RC [MIN])
Icc3
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: 'PC = 'PC [MIND
ICC4
OPERATING CURRENT: EDO PAGE MODE (X version only)
Average power supply current
(RAS = VIL, CAS, Address cycling: IpC = IpC [MIND
Ice5
(X only)
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC = IRC [MIN])
IceG
REFRESH CURRENT:CBR
Average power supply current
.
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
Iccl
REFRESH CURRENT: Extended (S version only)
Average power supply current; CAS = 0.2V or CBR cycling; RAS =
IRAS (MIN); WE= Vcc -0.2V; AO/BO-Al0, OE and DIN = Vce -0.2V
or 0.2V (DIN may be left open); IRC = 62.5/ls (32MB)/125/lS (8MB)
Icca
(S only)
REFRESH CURRENT: SELF (S version only)
Average power supply current; CBR cycling with RAS 2 tRASS
(MIN) and CAS held LOW; WE = Vcc -0.2V; AO/BO-Al0, OE and
DIN = Vcc -0.2V or 0.2V (DIN may be left open)
lecg
(S only)
MTI6lD(T)164(S}, MT16LO(T)464(X)(S)
DM47.pmS - Rev. 2195
5-53
8MB
960
800
32MB
1,440
1,280
8MB
-
-
32MB
1,760
1,600
8MB
1,280
1,120
32MB
1,920
1,760
8MB
1,280
1,120
32MB
1,920
1,760
8MB
2.4
2.4
32MB
4.8
4,8
8MB
2.4
2.4
32MB
4.8
4.8
UNITS NOTES
.'
,-
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
-c3:
3:
PRELIMINARY
AIIU:: 1=1CN
1-·
","",coo,,"e
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
*Stresses greater than those listed under "Absolute Maxi"
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RA TINGS*
Voltage on Vee Pin Relative to Vss ................. -lV to +4.6V
Voltage on Inputs or I/O Pins
Relative to Vss .................................................... -lVto +S.5V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ........................................................... 16W
Short Circuit Output-Current ,.................................... SOmA
CAPACITANCE
SYMBOL
PARAMETER
II
Input Capacitance: AO-A 10, BO
CI1
Input Capacitance: WEO, WE2, OED, OE2
Ci2
MIN
MAX
9
UNITS
NOTES
pF
2
"
pF
,.,
2
c
::D
>
s: FAST PAGE MODE
c ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
CI3
Input Capacitance: RASO, RAS2
-3:
s:
64
pF
2
2
Input Capacitance: CASO - CAS7
CI4
9
pF
InputJOutputCapacitance: 000-0063
CIO
10
pF
2
Output Capacitance: PD1-PD8
Co
10
pF
2
MAX
UNITS
NOTES
40
ns
25
24
23
25
23, 30
15,25
25
(Noles: 6, 7, 8, 9, 10, 11, 12, 13) (Vcc = +3.3V ±0.3V)
SYM
Access time from column-address
tAA
Column-address hold time (referenced to RAS)
Column-address setup time
tAR
tASC
tASR
Row-address setup time
Column-address to WE delay time
tAWD
Access time from CAS
tCAC
Column-address hold time
tCAH
CAS pulse width
RAS LOW to "don't care" during SELF REFRESH
tCAS
tCHD
CAS hold time (CBR REFRESH)
ICHR
tCLZ
tcp
CAS to output in Low-Z
CAS precharge time
Access time from CAS precharge
tCPA
CAS to RAS precharge time
CAS hold time
tCRP
tCSH
CAS setup time (CBR REFRESH)
CAS to WE delay time
tCSR
tCWD
Write command to CAS lead time
Data-in hold time
tCWL
tDH
Data-in hold time (referenced to RAS)
Data-in setup time
tDHR
tDS
MIN
48
2
5
57
tOEH
Output buffer turn-off delay
tOFF
5-54
MIN
53
2
5.
67
20
15
15
15
8
5
10
10,000
ns
ns
20
ns
ns
ns
ns
ns
45
ns
ns
ns
ns
ns
ns
20
20
18
5
ns
ns
10,000
15
68
12
47
20
20
55
-2
15
15
13
5
ns
ns
25
20
20
15
8
5
10
40
15
58
12
42
15
15
45
-2
tOE
OE hold time from WE during READ-MODIFY-WRITE cycle
MAX
35
too
Output disable
Output enable
MT16LD(T)164(S), MT16LD(T)464(X)(5)
DM47.pmS - Rev. 2195
-7
-6
AC CHARACTERISTICS - FAST PAGE MOOE OPTION
PARAMETER
25
36
5,24
23
16
25
25
24
5,23
23,30
ns
25,29
ns
ns
24,29
ns
.
ns
ns·
ns
24
20,27,38
Micron Technology, Inc., reserves the right to change products or specifications Without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
"'""'W"''"'
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+3.3V ±0.3V)
-6
AC CHARACTERISTICS - FAST PAGE MOOE OPTION
PARAMETER
SYM
tORD
tpc
OE setup prior to RAS during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
PDE to Valid Presence-Detect Data
MIN
0
35
tpD
tpDOFF
tpRWC
PDE Inactive to Presence-Detects Inactive
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
10
RAS to column-address delay time
tRAD
13
tRAH
8
Column-address to RAS lead time
tRAL
35
RAS pulse width
RAS pulse width (FAST PAGE MODE)
tRAS
60
60
100
RAS pulse width during SELF REFRESH
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (1,024 or 2,048 cycles) S version
18
tRCH
2
2
tRCS
tREF
Refresh period (2,048 cycles) - 4 Meg x 64
Refresh period (1,024 cycles) - 1 Meg x 64
10
70
13
30
8
40
10,000
70
10,000
100,000
70
100
100,000
40
18
UNITS
' NOTES
ns
20
ns
ns
ns
35
34
ns
ns
23
14
ns
18,26
ns
24
ns
25
ns
ns
IlS
130
45
ns
17,26
ns
ns
19,23
32
16
ms
ms
128
50
ms
ns
16
128
36
ns
2
2
32
tREF
tREF
.'
25
110
tRCD
MAX
2
97
60
Row-address hold time
Random READ or WRITE cycle time
RAS to CAS delay time
MIN
0
40
2
87
tRAC
tRASP
tRASS
tRC
~7
MAX
23
40
tRPC
tRPS
tRRH
0
0
ns
RAS precharge time during SELF REFRESH
Read command hold time (referenced to RAS)
110
130
0
ns
ns
36
19
RAS hold time
READ WRITE cycle time
25
ns
tRWC
185
97
ns
25
25
ns
23,30
ns
ns
25
ns
ns
25
ns
23,30
RAS to 'CAS precharge time
tRSH
tRWD
tRWL
tT
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
twCH
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT16LD(T)164(S), MT16LD(T)464(X)(S)
DM47.pmS- Rev. 2f95
5-55
0
20
155
87
20
3
15
·25
50
3
20
50
.'
twCR
twcs
twp
43
53
2
10
2
15
tWRH
tWRP
8
12
8
12
C
:rJ
l>
s:
-3:
C
3:
tRP
RAp precharge time
•
24
ns
ns
22,24
ns
22,23
Micron Technology, Inc., reserves the right to change products or specifications without notice..
©1995, Micron Technology, Inc,
PRELIMINARY
MICRON
1-'
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
""",CO"",,
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
=+3.3V ±0.3V)
C
:II
l>
s:
-s:C
s:
Access time from column-address
Column-address setup to CAS precharge during writes
Column-address hoid time (referenced to RAS)
tACH
tAR
Column-address setup time
IASC
Row·address setup time
Column-address to WE delay time
tASR
tAWD
15
43
2
5
57
Access time from CAS
tCAC
Column-address hold time
tCAH
CAS pulse width
RAS LOW to "don't care" during SELF REFRESH
tCAS
-7
MAX
MIN
35
MAX
UNITS
NOTES
40
ns
25
15
53
2
5
67
20
ns
ns
ns
ns
ns
CAS'hold time (CBR REFRESH)
CAS to output in Low-Z
Data output hold ·after CAS lOW
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
tCHD
tCHR
tClZ
tCOH
tcp
tCPA
tCRP
ICSH
CAS to WE delay time
ICSR
ICWD
Write command to CAS lead time
Data-in hold time
ICWl
tDH
Data·in hold time (referenced to RAS)
Data·in setup time
tDHR
IDS
Output disable
Output enable
OE hold time from WE during READ-MODIFY-WRITE cycle '.
OE HIGH hold time from CAS HIGH
tOD
tOE
tOEH
tOEHC
OE HIGH pulse width
OE lOW to CAS HIGH setup time
tOEP
IOES
Output buffer turn-off delay
tOFF
tORD
tpc
tpD
OE setup prior to RAS during HIDDEN REFRE:SH cycle
EDO-PAGE-MODE READ or WRITE cycle time
PDE to valid presence-detect data
PDE inactive to presence-detects inactive
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
IpDOFF
IpRWC
tRAC
tRAD
Row-address hold time
Column-address to RAS lead time
IRAH
RAS pulse width
RAS pulse width (EDO PAGE MODE)
IRAS
IRASP
RAS pulse width during SELF REFRESH
IRASS
tRC
Random READ or WRITE cycle time
RAS to CAS delay time
MT16LD(T)164(S), MT16LD(T)464(X)(S)
DM47.pm5 - Rev. 2/95
15
10
15
8
2
7
10
25
tRAl
IRCD
10,000
17
12
15
10
2
7
10
ns
40
10
48
7
37
15
15
45
-2
0
8
10
10
5
5
0
25
15
15
20
10
10
10
5
5
0
30
10
2
60
25
10,000
125,000
40
10
8
40
70
70
100
130
12
24
23
25
23,30
15,25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
36
5,24
23
23
16
25,37
25
24
5,23
23,30
ns
15
15
ns
25,29
ns
ns
24,29
ns
ns
. ns
24
ns
20
ns
ns
ns
ns
20,27,38
20
ns
10
ns
ns
70
30
ns
ns
2
87
77
10
8
35
60
60
100
110
12
ns
10,000
45
10
53
7
42
15
17
55
-2
0
~
MIN
_
•
-6
SYM
tAA
_
AC CHARACTERISTICS - EDDPAGE MODE OPTION
PARAMETER
T
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
ns
ns
10,000
125,000
45
ns
ns
35
34
23
14
18,26
24
25
ns
~
36
ns
ns
17,26
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc
PRELIMINARY
UII::::FlCN
1-·
'''~'''oo,''
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +3.3V ±0.3V)
-6
AC CHARACTERISTICS - EDD PAGE MODE OPTION
PARAMETER
SYM
MIN
Read command hold time (referenced to CAS)
tRCH
Read command setup time
tRCS
2
2
Refresh period (2,048 cycles) - 4 Meg x 64
Refresh period (2,048 cycles) S version
tREF
tREF
RAS precharge time
RAS to CAS precharge time
tRPC
tRP
tRPS
tRRH
RAS precharge time during SELF REFRESH
Read command hold time (referenced to RAS)
RAS hold time
tRSH
READ WRITE cycle time
RAS to WE delay time
tRWC
tRWD
Write command to RAS lead time
Transition time (rise or fall)
tRWL
Write command hold time
twCH
tWCR
IT
Write command hold time (referenced to RAS)
twcs
WE command setup time
Output disable delay from WE (CAS HIGH)
tWHZ
twp
Write command pulse width
WE pulse width for output disable when CAS HIGH
twpz
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
tWRH
tWRP
MT16LD(T)1,64(5), MTI6LD(T)464(X)(S)
DM47.pm5 - Rev. 2/95
5-57
-7
MAX
MIN
MAX
2
2
32
128
50
50
18
19,23
23
ms
ms
ns
ns
0
130
0
17
182
92
20
2
17
53
2
2
12
12
8
12
NOTES
ns
ns
32
128
40
0
110
0
15
155
82
20
2
15
43
2
2
10
10
8
12
UNITS
ns
ns
ns
ns.
ns
ns
50
ns
ns
20
,
36
19
25
25
23,30
25
25
ns
ns
24
ns
ns
ns
--
ns
ns
23
27
22.24
22,23-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995, Micron Technology, Inc.
•
C
::D
»
s:
-sc:
s:
PRELIMINARY
MICRON
1-·
","'ow",,,
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
NOTES
II
C
::D
l=-
s:
-Sc
S
1. All voltages referenced to Vss.
2. This parameter is sampled. Vee = +3.3V ±0.3V;
f=IMHz.
3. Icc is dependent on cycle rates.
4. Icc is dependent on output loading. Specified values
are obtained with minimum cycle time and the
outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOlls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume IT = 5ns for FPM and 2.5ns
forEDO.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification,
all input signals must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by ICAe.
18. Operation within the lRAD (MAX) limit ensures that
lRAC (MIN) and ICAC (MIN) can be met. IRAD
(MAX) is specified as a reference point only; if lRAD is
greater than the specified IRAD (MAX) limit, access
time is controlled exclusively by IAA.
MT16LD(T)164(S), MTI6LD(T)464(X)(S)
DM47.pmS- Rev, 2195
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE = LOW and
OE = HIGH.
22. IWTS and IWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverse of twRP and IWRH in the
CBR REFRESH cycle.
23. A +2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
24. A -2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
25. A +5ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
26. A -2ns (MIN) and a -5ns (MAX) timing skew from the
DRAM to the module resulted from the addition of
line drivers.
27. A +2ns (MIN) and a +5ns (MAX) timing skew from
the DRAM to the module resulted from the addition
of line drivers.
28. The maximum current ratings are based with the
memory operating or being refreshed in the x64
mode. The stated maximums may be reduced by
approximately one-half when used in the x32 mode.
29. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
30. IWCS, IRWD, IAWD and ICWD are not restrictive
operating parameters. twcs applies to EARLY WRITE
cycles. IRWD, IA WD and ICWD apply to READMODIFY-WRITE cycles. If twcs ~ IWCS (MIN), the
cycle is an EARLY WRITE cycle and the data output
will remain an open circuit throughout the entire
cycle. {fIRWD ~ IRWD (MIN), IAWD ~ IAWD (MIN)
and ICWD ~ ICWD (MIN), the cycle is a READMODIFY-WRITE and the data output will contain
data read from the selected cell. If neither of the above
conditions is met, the state of data-out is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. twcs, IRWD, ICWD and IAWD are not
applicable in a LATE WRITE cycle.
5-58
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
"'""'''"''"'
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
NOTES (continued)
37. tCAC (MIN), tCPA (MIN) and tAA (MIN) are for
reference only to help aid the user as to when to
expect the earliest data to be accessed. Only tCAC
(MAX), tCPA (MAX) and tAA (MAX) are guaranteed.
38. For FAST PAGE MODE option, IOFF is determined
by the first RAS or CAS signal to transition HIGH. In
comparison, tOFF on an EDO option is determined by
the latter of the RAS and CAS signal to transition
HIGH.
39. Applies to both EDO and FAST PAGE MODEs.
31. Refresh current increases if tRAS is extended beyond
its minimum specification.
32. Column-address changed once each cycle.
33. The 3ns minimum parameter guaranteed by design.
34. IpDOFF MAX is determined by the pull-up resistor
value. Care must be taken to ensure adequate
recovery time prior to reading valid up-level on
subsequent DIMM position.
35. Measured with the specified current load and 100pf.
36. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
•
c
:c
»
s
-s:c
s:
MT16lD(T)164(S), MT16LD(T)464(X)(S}
DM47.pm5 - Rev. 2/95
5-59
Micron Technology, Inc., reserves the right to changeproducls or speciiicalions without notlce.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
m"",c"o""
READ CYCLE
39
'RC
I
'RP
V,H
RAS
_-----,[1
VIL_
'CSH
CAS
~:~ =~
'CRP
I
'RAD
•
VIL
~7777A}
..//////,14
ROW
I
c
:c
IRCD
1\
'AR
II
ill/7IIIA
Nil/II!
tWRP~II..tWRH I
~!±---;------
'CAS
I
~I~I
,
1~li~1
V,H
ADDR
'I, ~I
'RSH
I
VnTTTTT;IIIIIII~IIIIIIIITTTTTTTlllllllhnIIN
I
tRCS
I
WIIIIIIIIIIIIIIIIIIIIIIII/\
!~!
COLUMN
I
,
'RAL
!_ _ _ _ _ _-+_IC"'RA"--C_ _
I
ROW
NOTE 2
~
l>
s:
-s:C
DO
~g~ =_------OPEN-----~~PVA~LlD~DA~TA0--0PEN--
JWi///////////////////////////////;j
'00
EARLY WRITE CYCLE
s:
39
RC
'AP
'RAS
\
tCSH
J~
tRCD
d~:
'AR
I
'RAD
I~I
ADDR
I~ ~I
~:~_W;;:1{
ROW
~,1i
I
COLUMN
tCWL
WE
~:~
I
I
~
~ ~
--NOTEtI
I
~I
I
I
t
I
tRAL
I~I
I
~
tACH
'RWL
tWCR
~
I~
'WP
II II
tDHR
_'DS_I I_'DH_I
DQ~:g~ ~
ROW
VALID DATA
~
I2Zl DON'T CARE
!il&l UNDEFINED
NOTE:
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
2. tOFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MfI6LD(T)164(S}, MTI6LD(T)464(X)(S)
DM47.pm5 -Rev. 2(95
5-60
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
""'''0"''''
FAST-PAGE-MODE READ CYCLE
1~
_______________________t~RA~SP~________________________ I~
ADDR
AA
I
I
~!gt
=:'-------
I
-
1:-
ICLZ-
'CAG
tCLZ-
~
'CAG
~
DATA
~ ~
~ ~
c
tePA
-r- 1~-tOFF
I
'OFF
~
VALID
DATA
OPEN
III
AA
I
tePA
-- -
I
'OFF
tCAG
'eLZDO
AA
tRAG
~
VALID
DATA
JJ
»
s:
-s:c
s:
• OPEN
..'2i:1
EDO-PAGE-MODE READ CYCLE
RAS
V,H
VIL
- ______
-
~~--------------------------t-RA-S-P
.f,-~tP.L
______________-,-_________
ICSH
~
CAS
V,H
VIL
-
ADDR
---=-
I
ICLZ-
DQ
ICAC
~g~ -'--------OPEN---------~~~~~==j~~[;r_--+~~=~~==l
OPEN
OE
[Zj DON'T CARE
~
NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRPand WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MTI6LD(T)I64(S), MTI6LD{T)464(X)(S)
DM47.pm5- Rev. 2/95
5-61
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
","",co",,",
FAST-PAGE-MODE EARLY-WRITE CYCLE
---L~-==---IRASP~I_IRP
RAs
~:~ = I~[ [=-"C=SH-C-RCD-----,-----fCpC'----~-1
CAs
~:t
=
ADDR
~:~
'-:"
I_---+I--+-"""~
I
_IWC~S!:---+-==----
I
II
WE
~:~
c
'RSH
:Jj7TT;lffiTTT.@=wmW/=;:;;j;7777;1J;0J,
I~------:---+--'''''''--
:II
l>
s:
-s:
C
EDO-PAGE-MODE EARLY-WRITE CYCLE
s:
'RASP
tCSH
IpC
~I_·~~~IR=CD'---~I_I=CA~S_ _ II~IC~P--I
ICp
[ZJ DON'T CARE
~
NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT16LD(TI164(S). MT16LD(T)464(X)(S)
DM47.pm5 ~ Rev. 2195
5-62
Micron Technology, Inc., reserves the right to change products orspecificalions without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
"'"'OCoo""
READ WRITE CYCLE 39
(LATE WRITE and READ-MODIFY-WRITE cycles)
'ewe
•
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DQ
~:gr
:D
l>
-------
['"
Dc
:rr ::JjTTT1/;;TTT1j;;TTT1//TTT1j;;TTT1j;;TTT1j;;rrf0'/TTT1Jj;TTT1j;;TTT1j;;TTT1//TTT1//TTT/I/TyTT//=1Jj;=1/&l
s:
)'oD
. -.- - - - - I n c
-C3:
EDO/PAGE-MODE READ-WRITE CYCLE 39
(LATE WRITE and READ-MODIFY-WRITE cycles)
3:
IPC/tpRWC NOTE 1
11 _ _--"""'-_~I __'=eAs'--_II~
DQ
NOTE:
~igt
teAS
:::::-----
OPEN-
~
DON'T CARE
~
UNDEFINED
1. IpC is for LATE WRITE cycles only.
2. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT16LD(T)164(S), ·MT16LD(T)464(X)(S)
DM47.pmS- Rev. 2195
5-63
Micron Technology, Inc., reserves the right tc change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
,""",co,,,,,
RAS-ONL Y REFRESH CYCLE
(WE = DON'T CARE)
: :: d
•
DO
tASR
~:r ::~
ADDR
V
WE
~
tRAH
~o~
»
s:
II
ROW
II
I::I'I----------7-:-----
- - - - V ....
~II~
~:r Jffi!$$}
.~ :~
'kv$ffi!///M/ljI&Ju/////////;/##~ZX
II
_
\I<2~
'VL
C
::D
'~I '
'm,
tRC
39
~II~
~//I!!/#/!I!I!I!I!I!/!I!I!I!II!!I!!/////#/;}
_
EDO-PAGE-MODE READ-EARL Y-WRITE CYCLE
(Pseudo READ-MODiFY-WRITE)
c
-
S
S
tpc
j'
CAS
tR=CD=-----jI:--I-='tCA=S~
1_ _ _
tCRP
~:r=J
~
I~
ADDR
~:~_
tRAD
tRAH
ROW
~
_
~:~-!////t
-I.LLLI NOTE 1 I
I I
~
COLUMN (A)
I~I
1(///////$
Y.L.L1.Lf!!
1
~ I_----..-:tc"--P_ _ II_t-=CA-=----S_1
t_
I'------J
~
I~II~I
WE
tpc
l_t...:.ccP_1
tRAC
I
tAA I
/TT77-rrr.
T,I
COLUMN(8)
I~
~II~I
,w~////rrTT7/////TT>~
COLUMN(N)
I
~1T77TT777777TT\
ROW
tRCH-II~ ~11~r----I tAA
I
I
II tACH
~ ~CAH:I
I
tCPA
1\\
II
1
I~
tCOH
tWHZ_
1_
I~II~I
1=1
DO 't:8t=-----OPEN ----r-;,VA~LlD~DA:;::;-TAWIA)--y~D~~9t~~CBi~tVVAALLlI'D?I'NPDAATPTA'l-_ _ _ __
~
DE
~:r= /1///;//;/$/;//;//;/////;////;///////#A
~
DON'T CARE
~ UND~INED
NOTE:
1. Although WE is a "don't care" at RAS, time during an access cycle (READ or WRITE}, the system designer
should implement WE HIGH for tWRPand tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT16LD(T)164(S). MT16LD(T)464\X)(S)
DM47.pm5- Flav. 2/95
5-64
Micron Technology, Inc., reserves the right to change products or specifications wlthoot notice.
©1995, Micron Technology, Inc,
PRELIMINARY
UII::::I=ICN
1-·
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
"'"'oco"',,,
HIDDEN REFRESH CYCLE21,
(WE = HIGH; OE = LOW)
(READ)
39
(REFRESH)
tRAS
tRAS
-'~
'------tCHR
CAS
~lr::::
ADDR
DO
~:gt ------OPEN-----~WL_--~V~AL~ID~DA~TA'-----.
'" ::t $$$$#iff##$$##I$j'I/'[.!- .1
MT16lD(T)164(S), MT16LD(T)464{X)(S)
DM47.pm5 - Rev. 2/95
5-65
I
fe.,
'OFF
;;/W_
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
C
l:J
l>
S
-C3:
s:
PRELIMINARY
MICRON
1-·
""""CO"'
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
'c
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
tCSH
•
IASR
I
RAD
kA:
----II~
ADDR
~:t-
r,
C
:D
ROW_
»
s::
-cs::
WE
o
~:~ ::'0"//////////////$
I
IA~:R
,
I
-1
00'
I-
'I
I
,r .~J': ii::.1 J
~I
I
leAH
I
I
~11~k////P//;/u////////~
~II~
~:~ ::1'/////;/u///////////////////////////////~://////////~
~~i,
:s:
Q
VALID DATA
k1/////;l////;/uu////,0;
~g~------TI-DPEN-t-I:~~IAA::=:'~~IUL~H~U~i-----OPEN---tRAC
BE
NOTE:
~lt
B'.LI.L.U'""---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
~
DON'T CARE
~
UNDEFINED
1. Do not drive data prior to tristate.
MT16LD(T)164(S}, MT16LD(T)464(X)(S)
DM47.pmS - Aev. 2195
5-66
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
PRELIMINARY
MICRON
1-·
",",ccc,,,,,
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
CBR REFRESH CYCLE 39
(Addresses, OE = DON'T CARE)
•
C
:D
l>
SELF REFRESH CYCLE 39
(Addresses and OE = DON'T CARE)
s:
-3:C
3:
NOTE:
~
DON'TCARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT16LD{T)164(S), MT16LO(T)464(X)(S)
DM47.pm5 - Rev. 2/95
5-67
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc,
PRELIMINARY
1"I1t::I=ICN
MT16LD(T)164(S), MT16LD(T)464(X)(S)
1 MEG, 4 MEG x 64 DRAM MODULES
'''"'OeO",'",
EDO READ CYCLE
(with WE-controlled disable)
•
RAS
V,H
VIL _
CAS
VIH -:-
VIL
r
tCRP
----.J
ADDR
C
::rJ
I
WE
I
»
s:
I
tAA
tRAG
tCLZ
-Sc
DQ
~g~ --------OPEN-------~~-~~~____f op~N-·b
I.
S
OE
~:r ::'l;J//Jl§////#§l;0'u/;i/ff//;i/$/;1/mu/;1///;2A'
1_
tOE
ti!;/;I//;I$;;;;////////;I/lm
PRESENCE-DETECT READ CYCLE
,~ :::---~L~,e>
p01-poa
NOTE:
V,L _
too
39
~~
i____
f
V_AL_'O_PR_ES_EN_C_E-O_ET_EC_T_ _ _ _
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for 'WRP and 'WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
2. PD pins must be pulled HIGH at next level.
MT16LD{T)164(S), MT16LD(T)464(X)(S}
DM47.pm5 - Rev. 2/95
5-68
Micron Technology, Inc., reserves the right to change products or specrrications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1--
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
"c,,"
DRAM
MODULE
2 MEG x64
16 MEGABYTE,3.3V, FAST PAGE OR EDO
PAGE MODE, qPTIONAL SELF REFRESH
FEATURES
• JEDEC- and industl3'-standard pinout in a 168-pin,
dual-in-line memory module (DlMM)
• High-performance CMOS silicon-gate process
• Single +3.3V ±O.3Vpower supply
• All device pins are TIL-compatible' .
• Lo,w power, BmW standby;~,600mW active, typical
• Refresh modes: RAS ONLY, CAS-BEFOREcRAS (CBR),
HIDDEN; Extended and SELF REFRESH
.
• All inputs are buffered except RAS
• 2,048-cyc1e refresh distributed across 32msor
2,048-cyc1e Extended Refresh distributed across 128ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(Eoo) PAGE MODE access cycles
• 5V tolerant l/Os(5.5V maximum VIR level) .
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
-7
• Components
SOl,
TsaP
DT
D
• Packages
168-pin DIMM (gold)
G
• Refresh
Standard/32ms
SELF REFRESH/128ms
Blank
S
KEY TIMING PARAMETERS
EDO option
SPEED
,'RC
'RAC
'PC
'AA
'CAC
'CAS.
-6
-7
110ns
1:30ns
60ns
70ns
25ns
:30ns
:35ns
40ns
20ns
25ns
10ns
12ns
FPMoption
SPEED
'RC
IfIAC
'PC
'M
'CAC
,6,
-7
110ns
130ns
60ns
70ns
:35ns
40ns
350s
40n9.
20ns
25ns
IfIp
40ns
50ns .
.'
MT8L0(T)264(X)(S)
DM32.pm5 - Rev. 2/95
PIN ASSIGNMENT.(Front View)
1G8-Pin DIMM
(DE- t 1) SOJ Version
(OE-12) TSOP Version
z
m
=E
•
~ QQ"g"Qnmm"Q,Q J C
PINt SYMBOL PiNt SYMBOL PiNt SYMBOL
. Vss
1
Vss
43
Vss
85
000
44
0032
2
0E2
86
3
001
45
RAS2
87
0033
4
002·.
46
88
0034
l:Jl.S4
OQ3b
5
003
47
89
'CAS6
6
Vee
WE2
90
Vcc
48
'49
7
004
Vee
91
0036
NC
.
8
005
50
92
0037
9
006
51
NC
93
0038
94
10
007
52
0016
0039
11
NC
0017
95
NC
53
'96
12
Vss
54
Vss
Vss
97
0040
13
008
55
0018
14
009
56
0019
98
0041
15
0010
57
0020
99
0042
,58
100
0011
0021
0043
16
0012
Vcc
101
0044
17
59
18
Vcc
60
0022
102 , Vce
61
103
0045
19
0013
RFU
DQ46
104
20
0014
62
RFO
105
0047
21
0015
63
RFU
64
106
22
NC
RFU
NC
Vss
65
0023
107
Vss
23
108
NC
NC
66
NC
24
109
NC'
NC
67
0024
25
Vee 0
26
Vcc
Vss
110
68
111
RFU
27
69
0025
WED"
112
"CASf
28.
70
0026
UASO"
29
71
0027
113
W\Sf
~
,lViSQ
DQ28
NC
30
72
11
,115
'. Vce
31
RFU
UEO
73
OQ29 ' 116
32
74
Vss
VsS
OQ30
11,7
Al
33
AO
75
118,
34
0031
A3
A2
76
119
"
AS
35
A4
NC
77
120
A7
·36 I', A6
78
Vss
37
A8
POI
121
A9
79
38
AID
80
122
NC
PD3
123
NC
39
NC
81
P05
1'24
Vee
40
Vee
82
P07
RfU:
RFU
41
100
125'
83
42.
126.
BO
RFU
84
Vee·
PIN# SYMBOL
127
Vss
128
RFU
129
NC
130
'CASO
131
132
l'lJt
133
Vee
134
NC
135
NC
136
0048
137
0049
138
Vss
139
0050
140
!lOS 1
141
1J052
142
0053
143
Vee
DQ54
144
RFU
145
146
RFU
147
RFU
148.
RFU
149
0055
150
NC
fSl
0056
. Vss
152
153
0057
154
0058
155
0059
156
0060
157
Vee
158
0061
159
0062
DQ63
160
'. NC
161
162
Vss
163
P02
164
PD4
165
P06
P08
166
167
1D1
Vee
168
mr
Micron Technology, Inc., raserves the fight to change products or specifications without notice.
©1995, Micron-Technology, Inc.
:D
l>
s:
-3:C
3:
ADVANCE
MICRON
1-·
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
,"",,"00"",
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS. EDO-PAGE-MODE DRAMs operate similar to FASTPAGE-MODE DRAMs, except data will remain valid or
become valid after CAS goes HIGH during READs, provided RAS and OE are held LOW. If OE is pulsed while
RAS and CAS are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If OE is toggled or
pulsed after CAS goes HIGH while RAS remains LOW,
data will transition to and remain High-Z.
If the DQ outputs are wire OR'd, OE must be used to
disable idle banks of DRAMs. Alternatively, pulsing WE to
the idle banks during CAS HIGH time will also High-Z the
outputs. Independent of OE control, the outputs will disable after tOFF, which is referenced from the rising edge of
RAS or CAS, whichever occurs last (reference the
MT4LC2M8E7(S) DRAM data sheet for additional information on EDO functionality).
VALID PART NUMBERS
z
m
:E
•
C
lJ
l>
s:
-s:C
s:
PART NUMBER
DESCRIPTION
MT8LDT264G-xx
MT8LDT264G-xx S
MT8LDT264G-xx X
MT8LDT264G-xx XS
MT8LD264G-xx
MT8LD264G-xx S
MT8LD264G-xx X
MT8LD264G-xx XS
2
2
2
2
2
2
2
2
Meg
Meg
Meg
Meg
Meg
Meg
Meg
Meg
x 64,
x 64,
x 64,
x 64,
x 64,
x 64,
x 64,
x 64,
FPM, TSOP
FPM, S*, TSOP
EDO, TSOP
EDO, S*, TSOP
FPM, SOJ
FPM, S*, SOJ
EDO, SOJ
EDO, S*, SOJ
*S = SELF REFRESH
GENERAL DESCRIPTION
The MT8LD(T)264(X)(S) is a randomly accessed solidstate memory containing 2,097,152 words organized in a
x64 configuration. It is specially processed to operate from
3.0V to 3.6V for low voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 21 address bits. The address is
entered first by RAS latching 11 bits and then CAS latching
10 bits. Two copies of address 0 (AO and BO) are defined to
allow maximum performance for4-byte applications which
interleave between two 4-byte banks. AO is common to the
DRAMs used for DQO-DQ31, while BO is common to the
DRAMs used for DQ32-DQ63.
READ and WRITE cycles are selected with the WE input.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. EARLY WRITE occurs when WE
goes LOW prior to CAS going LOW, and the output pines)
remain open (High-Z) until the next CAS cycle.
REFRESH
Returning RAS and CAS HIGH terminates a memory
cycle, and decreases chip current to a reduced standby
level. Also, ,the chip is preconditioned for the next cycle
during the RAS HIGH time. Correct memory cell data is
preserved by maintaining power and executing any RAS
cycle (READ, WRITE) or RAS refresh cycle (RAS ONLY,
CBR or HIDDEN) so that all 2,048 combinations of RAS
addresses (AO-A 10) are executed at least every 32ms (128ms
"S" version), regardless of sequence. The CBR REFRESH
cycle will invoke the internal refresh counter for automatic
RAS addressing.
An additional SELF REFRESH mode is also available.
The "S" version allows the user the choice of a fully static,
low-power, data-retention mode, or a dynamic refresh
mode at the extended refresh period of 128ms, four times
longer than the standard 32ms specifications. The module's
SELF REFRESH mode.is initiated by performing a CBR
REFRESH cycle and holding RAS LOW for the specified
IRASS. Additionally, the "S" version allows for an extended
refresh rate of 62.5/ls per row if using distributed CBR
refresh. This refresh rate can be applied during normal
operation, as well as during a standby or extended refresh
mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for the time minimum of an operation cycle, typically
IRPS. This delay allows for the completion of any internal
refresh cycles that may be in process at the time of the
RAS LOW-to-HIGH transition. If the DRAM controller
uses a distributed CBR REFRESH sequence, a burst refresh
is not required upon exiting SELF REFRESH mode. However, if the DRAM controller utilizes RAS ONLY or burst
refresh sequence, all 2,048 rows must be refreshed within
300/ls prior to the resumption of normal operation.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined
page boundary. The FAST PAGE MODE cycle is always
initiated with a row-address strobed-in by RAS followed by
a column·address strobed-in by CAS. CAS maybe toggledin by holding RAS LOW and strobingcin different columnaddresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the FAST PAGE MODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the "X" version/is an
accelerated FAST PAGE MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS
goes back HIGH. EDO provides for CAS precharge time
(ICP) to occur without the output data going invalid. This
elimination of CAS output control provides for pipeline
READs.
MT8LD(T)264(X)(S)
DM32.pm5 - Rev. 2195
5-70
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
2 MEG
'''"'''0"''''
MTBLD(T)264(X)(S)
x 64 DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
OQO ,- OQ7
v-----I
OQB- OQ15
OQ16'- OQ23
!l ttl} tll-----i! ttJ,lstl t f-------f!o tlJ,t} tll---~!o~tlJ;;-:-;-,lst~t1
WEO
1 - - - - - 1 WE
U'
I------IOE
I-----/WE
1-------jOE
U2
U3
1 - - - - - / RAS
1-----'--1 RAS
RASO - - - - /
CASO
CAS1
OQ24'- OQ31
CAS
1------jWE
I-----/OE
U4
I - - - - - - j RAS
A1-A10
CAS
A1-A10
:e
•
iO>-----:
CAS2
c
A10-Al
OQ32-0Q39
OQ40- 0047
OQ4B- OQ55
OQ56'- OQ63
ttl tIt tt
tt tt!ttl
tlttttlt
ttltl!ll
AO
DQ1 "8
WE
WE2
OE
RAS
U5
1-_ _ _--1 AD
1 - - - - - 1 WE
I-----IOE
1 - - - - - - 1 RAS
DQ1 ·8
I--.,------j
AD
OQ1 "8
I - - - - - - - j WE
U6
I-----/OE
I - - - - - - - j RAS
U7
1------jAO
1-----/i'iE
1------jOE
fl011\
U8
I-----/RAS
CAS
CAS4
A1-A10
CAS6
2 Meg x 64 - MT8LDT264G(S)
U1-U8 = MT4LC2M8B1(S) FAST PAGE MODE
~PD1-P08
••••
2 Meg x 64 - MT8LD(T)264G X(S)
U1-U8 = MT4LC2M8E7(S) EDO PAGE MODE
POE - - - - - - '
NOTE:
z
m
1. All inputs with the exception of RAS are redriven.
2. D =line buffers.
MTSlO(T)264(X)(S)
DM32.pm5 - Rev. 2/95
5-71
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
II
»
s:
c-
3:
3:
ADVANCE
MIC::RON
cc~'"
1-·
,
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
"
PIN DESCRIPTIONS
PIN NUMBERS
z
SYMBOL
TYPE
DESCRIPTION
Row-Address Strobe: RAS is used to clock-in the 11 rowaddress bits. Two RAS inputs allow for one x64 bank or
two x32 banks.
30,45
RASO,RAS2
Input
28,29,46,47,112,
113,130,131
CASO-7
Buffered Input
Column-Address Strobe: CAS is used to clock-in the 10
column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles. Eight CAS
inputs allow byte access control for any memory bank
configuration.
27,48
WEO, WE2
Buffered Input
Write Enable: WE is the READIWRITE control for the DO
pins. WEO controls 000-0031. WE2 controls 00320063. If WE is LOW prior to CAS going LOW, the access
is an EARLY WRITE cycle. If WE is HIGH while CAS is
LOW, the acceSs is a READ cycle, provided OE is also
LOW. If WE goes LOW after CAS goes LOW, then the
cycle is a LATE WRITE cycle. A LATE WRITE cycle is
generally used in conjunction with a READ cycle to form a
READ-MODIFY-WRITE cycle.
31,44
OEO,OE2
Buffered Input
Output Enable: OE is the input!output control for the DO
pins. OEO controls 000-0031. OE2 controls 00320063. These signals may be driven, allowing LATE
WRITE cycles.
33-38,117-121,126
AO-A10, BO
Buffered Input
Address Inputs: These inputs are multiplexed
and clocked by RAS and CAS. AO is common to the
DRAMl) used for 000-0031, while BO is common to the
DRAMs used for 0032-0063.
2-5,7-10,13-17,19-21,
52-53, 55-58, 60, 65, 67,
69-72,74-76,86-89,
91-94,97-101,103-105,
136-137,139-142,144,
149,151,153-156,158-160
000-0063
Input!
Output
Data 1/0: For WRITE cycles, 000-0063 act as
inputs tothe addressed DRAM location. BYTE
WRITEs may be performed by using the corresponding
CAS select (x64 mode only). For READ access cycles,
000-0063 act as outputs for the addressed DRAM
location.
79-82,163-166
PD1-PD8
Buffered
Output
41-42, 61-64, 111, 115,
125,128,145-148
RFU
-
6,18,26,40,49,59,73,
84,90,102,110,124,
133, 143, 157, 168
Vec
Supply
Power Supply: +3.3V ± 0.3V
1,12,23,32,43,54,68,
78,85,96,107,116,127,
138,152,162
Vss
Supply
Ground
m
:e
•
c
::D
l>
s:
-Cs:
s:
MT8LD(T)264(X)(S)
OM82.pm5 - Rev. 2/95
Presence-Detect: These pins are read by the
host system and tell the system the DIMM's personality.
They will be either driven to VOH (1) or they will be driven
to VOL (0).
RFU: These pins should be left
unconnected (reserved for future use).
5-72
Micron Technology, Inc., reserves the right to mange products or specifications without notice.
C1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
-c 'u, "
PIN DESCRIPTIONS (continued)
PIN NUMBERS
SYMBOL
TYPE
83, 167
100,101
Output
132
POE
Input
11, 22, 24-25, 38-39,
50"51, 66, 77, 95, 106,
108-109,114,122-123,
129, 134-135, 150,161
NC
-
OESCRIPTION
10 bits: 100 = DIMM type. 101 = Refresh Mode. These
pins will be either left floating (NC) or they will be
grounded (Vss).
Presence-Detect Enable: POE is the READ control for tl"1e
buffered presence-detect pins.
:e
•
c
:xJ
TRUTH TABLE
FUNCTION
"
I
Standby
HS"
.W
"Or
'PDt
H
H-+X
X
X
L
L'
H
L
WE":
EDO/FASt~PAGE-
1st Cycle
L
H-+L.
MODE READ
2nd Cycle
L
H-+L
H
L
EDO/FAST"PAGE','
.'
1st Cycle
L
H.,.-l,
L
X
X
X
X
X
X
X
X
MODE EARLYcWRITE 2nd Cycle
L
H-'>L
L
X
X
EDO/FASTcPAGI;:-
1st Cycle
L
H-+L
H-+L
L-+H
X
2nd Cycle
L
H-+L
H~L'
L-+H
,
,READ
EARLY WRITE
L
L
:1.:
X
READ WRITE
L
L
H-;L
L-+H
:He
L
. ' .~.
,MODE READ-WRITE
H
X
X
X
HIDDEN
READ
L-+H-+L
L
H
L
REFRESH
WRITE
X
X
High-Z
ROW
COL
Data-Out
ROW
COL
Data-In
ROW
COL
Data-Out, Data-In
ROW
COL
Data~Out,
n/a
COL
Data-Out
ROW
COL
Data-In'
.. li/a
Data-In
COL
Data-Out, Data-In
X
n/a
COL
Data-Out, Data-In
ROW
n/a
High-Z
ROW
COL
Data-Out
ROW
COL
Data-In
X
X
X
X
High-Z
X
X
Not Affected
L-+H-+L
L
L
H-+L
L
H
X
X
SELF REFRESH (S version)
H-+L
L
H
X
X
X
X
X
L
5-73
DATA-IN/OUT
000-63
ROW
CBR REFRESH
READ PRESENCE-DETECTS
ADDRESSES
IR
IC
COL
X
X
X
X
X
RAS-ONLY REFRESH
MT8l0(T)264(X)(S)
DM32.pm5-Rev.2195
z
m
No connect.
.'.
High-Z
Micron Technology. Inc., reserves the right to change products or speclflcatrons without notlc&.
@1995,MicronTechnology.lnc.
»
s:
-c3:
3:
ADVANCE
MICRON
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
"c~",oonc
1-·
PRESENCE-DETECT TRUTH TABLE
z
m
:E
•
C
::D
l>
s:
C
-
Access Timing
S
S
Refresh Control
Data Width, Parity
=
=
=
NOTE: Vss ground; 0 VOL; 1 VOH.
* This addressing includes a redundant address to allow mixing of 12110 and 11/11 DRAMs with the same presence-detect
setting.
MTBlO(T)264(X)(S)
DM32.pmS - Rev. 2/95
5-74
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
""""
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee Pin Relative to Vss ................. -IV to +4.6V
Voltage on Inputs or I/O Pins
Relative to Vss .................................................... -IV to +S.SV
pperating Temperature, TA (ambient) .......... Oo~ to +70°C
Storage Temperature (plastic) .................... -SSOC to +12SoC
Power Dissipation ............................................................. 8W
Short Circuit Output Current ................................. ;... SOmA
"Stresses greater than those listeP under" Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum ratii:tg conditions
for extended periods may affect reliability:
z
m
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +3.3V ±O.3V)
, SYMB,OL
MIN'
MAX
UNITS
Supply Voltage
Vce
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
CASO - CAS7
AO-A10, BO
WEO,2, OEO,2
111
-2
2
~
RASO,2
112
-8
8
IlA
loz
-10
10
~
VOH
2.4
PARAMETER!CONDITION
INPUT LEAKAGE CURRENT
Any input DV S; Wi s 5.5V
. (All other pins not under test = OV) lor each package input
OUTPUT LEAKAGE CURRENT
(0 is disabled; OV < VOUT < 5.5V) for each package input
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
MT8LD[r)264(XXs)
DM32.pm5 - Rev. 2195
000 - 0063
.
NOTES
.,
VOL
V
0.4
V
Micron Technology, Inc., reserves the right to change products or speciflcations,wlthout notice.
@1995, Micron TeChnology. Inc.
:e
•
c
::rJ
:a=-
s:
c
-3:
3:
ADVANCE
MICRON
1-·
MTSLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
'''~"owm'",
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +3.3V ±0.3V)
MAX
SYMBOL
SIZE
-6
-7
Icc1
16MB
16
16
mA
28
Icc2
Icc2
(S only)
16MB
16MB
4
1.2
4
1.2
mA
mA
28
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC [MiND
ICC3
16MB
1,040
960
mA
OPERATING CURRENT: FAST PAGE MODE
Average power supply Current
(RAS = VIL, CAS, Address Cycling: tpc = tpc [MIN])
ICC4
16MB
720
640
mA
Iccs
(X only)
16MB
960
880
mA
c
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: tRC =tRC [MIN])
ICC6
16MB
1,040
960
mA
3,32,
28
S
S
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC
Icc?
16MB
1,040
960
mA
3,5,
28
Iccs
(S only)
16MB
2.4
2.4
mA
3,5,
28
16MB
2.4
2.4
mA
5,28
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
z
m
~
II
c
:D
»
s:
-
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
OPERATING CURRENT: EDO PAGE MODE (X version only)
Average power supply current
(RAS = VIL, CAS, Address Cycling: tpc =tpc [MIN])
= tRC [MIN])
REFRESH CURRENT: Extended CBR (S version only)
Average power supply current
CAS = 0.2V or CBR cycling; RAS =tRAS (MIN);
WE = Vcc -0.2V; AO-AlO, OE and DIN = Vcc -O.2V or 0.2V (DIN may
be left open); tRC = 62.5/lS (2,048 rows at 62.5/lS = 128ms)
REFRESH CURRENT: SELF (S version only)
Iccg
Average power supply current during SELF REFRESH; CBR cycling
with RAS ~ tRASS (MIN) and CAS held LOW; WE = Vcc -0.2V;
(S only)
AO-A10, OE and DIN = Vcc -0.2V or 0.2V (DIN may be left open)
MT8LD(T)264(X)(S)
DM32.pm5 - Rev. 2/95
UNITS NOTES
5-76
3,4,
28,32
3,4,
28, 32
3,4,
28,32
Micron Technology, Inc., reserves the light to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
"'"
CAPACITANCE
PARAMETER
SYMBOL
MIN
MAX
UNITS' NOTES
2
Input Capacitance: AO-A 10, 80
Cll
9
pF
Input Capacitance: WEO, WE2, OEO, OE2
Input Capacitance: RASO, RAS2
CI2
9
40
pF
pF ,,'
Input Capacitance:CASO - CAS7
CI4
pF
2
Input/Output Capacitance: DOO - 0063
Cia
9
10
pF
2
Output Capacitance: PD1-PD8
Co
10
pF
2
CI3
,;
2
2
z
m
•
==
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10,11,12, 13) (Vcc '" +3.3V ±O.3V)
AC CHARACTERISTICS - FAST PAGE MOOE OPTION
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulse width
RAS LOWlo "don't care" during SELF REFRESH
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
CAS precnarge time
Access time from CAS precharge
CAS to RAS precharge time
CAS" hold time
CAS setup time (CI;lR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output enable
OE hold time from WE during
READ-MODIFY-WRITE cycle
MTSLD{T)264(X)(S)
DM32.pm5 - Rev. 2/95
-6
SYM
MIN
tM
tAR
tAse
tASR
tAWD
teAC
teAH
tCAS
tCHD
teHR
tCLl
tcp
tePA
tCRP
teSH
tCSR
tCWD'
tCWL
tDH
tDHR
tDS
toD
toE
toEH
5-77
-7
MAX
35
48
2
5
57
MIN
13
NOTES
25
24
23
25
23,30
'" 15,25
('Is.
25
ns
ns
ns
ns
'ns
,'ns
25
10,000
20
20
15
13
5
10
40
10
58
,7
,42
15
15
45
-2
3
UNITS
53
2
5
62
20
15
15
15
13
5
10
MAX
40
15
15
10;000
ns
ns
ns
ns
ns
ns
' ns
ns
ns
ns
ns
45
10
68
7
47
,20
20
55
-2
3
13
,;
20
20
'ns
ns
ns
ns
ns
ns
31
5;24
23,33
16
25
25
24
5,23
,23,30
25,29
24,29
33
24
Micron Technology, Inc., reserves the right to dlange products or specifications wlthouthOtlCe.
@1995, Micron TEichnology, Inc.
C
::0
»
3:
-c3:
3:
ADVANCE
MIC::RON
1-·
"H'"
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
H
FAST PAGE MODE
ELECTRICAL. CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
z
m
:e
•
c
JJ
l>
s:
-s:C
s:
Output buffer turn-off delay
()E setup prior to RAS during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
POE to valid presence-detect data
PDE inactive to presence:.ctetects inactive
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
RAS' pulse width during SELF REFRESH
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (2,048 cycles) - 2 Meg x 64
Refresh period (2,048 cycles) - 2 Meg x 64 S version
RAS precharge time
RAS to CAS precharge time
RAS precharge time during SELF REFRESH
Readcommand hold time (referenced to RAS)
RAS hold time
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transition time (rise.or fall)
Write command hold time
Write command hold time (referenced to RAS)
WE" command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE" setup time (CBR REFR~SH)
MT8LD(T)264(X)(S)
DM32.pm5 - Rev. 2195
-7
-6
SYM
MIN
MAX
MIN
MAX
UNITS
NOTES
tOFF
tORD
tpc
tpD
5
0
35
20
5
0
40
25
20,27,36
tpDOFF
tpRWC
tRAC
tRAD
2
87
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
!15
31
tRAH
tRAL
tRAS
tRASP
tRASS
tRC
tRCD
tRCH
tRCS
tREF
tREF
tRP
tRPC
tRPS
tRRH
tRSH
tRWC
tRWD
tRWL
tT
twCH
twCR
twcs
twP
tWRH
twRP
5-78
10
10
2
97
60
13
8
35
60
60
100
110
18
2
2
25
10,000
100,000
40
13
8
40
70
70
100
130
18
2
2
32
128
40
10,000
100,000
45
32
128
50
0
130
0
25
185
97
25
0
110
0
20
155
87
20
3
15
43
2
10
8
12
70
30
50
3
20
53
2
15
8
12
50
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns'
ns
ns
ns
ns
ns
20
35
34
23
14
18,26
24
25
17,26
19,23
23
31
19
25
25
23,30
25
25
24
23,30
22,24
22,23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995,MicronTechnology,lnc.
ADVANCE
MICRON
1-·
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
","",co",,",
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+3.3V ±0.3V)
AC CHARACTERISTICS - EDD PAGE MODE OPTION
PARAMETER
AccesS time from column-address
Column-address setup to CAS precharge during writes
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulse width
RAS lOW to "don't care" during SELF REFRESH
CAS hold time (CBR REFRESH)
CAS to output in low-Z
Data output hold after CAS lOW
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output enable
OE hold time from WE during READ-MODIFY-WRITE cycle
OE HIGH hold time from CAS HIGH
OE HIGH pulse width
OE lOW to CAS HIGH setup time
Output buffer turn-off delay
OE setup prior to RAS during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
PDE to Valid Presence-Detect Data
PDE Inactive to Presence-Detects Inactive
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS I.ead time
RAS pulse width
RAS pulse width (EDO PAGE MODE)
RAS pulse width during SELF REFRESH
Random READ or WRITE cycle time
MT8LD(T)264(X)(S)
DM32.pmS - Rev. 2195
-6
SYM
MIN
tAA
tACH
tAR
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHD
tCHR
tClZ
tCOH
tcp
tCPA
tCRP
tCSH
tCSR
tCWD
tCWl
tDH
tDHR
tDS
toD
tOE
tOEH
tOEHC
tOEP
tOES
tOFF
tORD
tpc
tpD
tpDOFF
tpRWC
tRAC
tRAD
tRAH
tRAl
tRAS
tRASP
tRASS
tRC
5-79
-7
MAX
MIN
35
15
43
2
5
57
10
10
10
5
5
0
25
10,000
15
15
20
25
10,000
45
10
53
7
42
15
17
55
-2
0
10
10
10
5
5
0
30
15
15
20
10
10
2
2
87
77
10
8
35
60
60
100
110
NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
17
12
15
10
2
7
10
40
10
48
7
37
15
15
45
-2
0
UNITS
40
15
53
2
5
67
20
15
10
15
8
2
7
10
MAX
60
25
10,000
125,000
10
8
40
70
70
100
130
70
30
10,000
125,000
JlS
24
23
25
23,30
15,25
25
31
5,24
23
23
16
25
25
24
5,23
23,30
25,29
24,29
24
20,27,36
20
35
34
23
14
18,26
24
25
31
ns
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, Inc.
z
m
:e
•
c
JJ
l>
3:
-c3:
3:
ADVANCE
MICRON
1-·
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
",""COO,,"
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +3.3V ±0.3V)
AC CHARACTERISTICS - EDD PAGE MODE OPTION
PARAMETER
z
m
=E
II
c
:0
:t>
3:
-c
s:
s:
-6
-7
SYM
MIN
MAX
MIN
MAX
UNITS
NOTES
RAS to CAS delay time
IRCD
12
40
12
45
ns
17,26
Read command hold time (referenced to CAS)
IRCH
2
2
ns
19,23
Read command setup time
tRCS
2
2
ns
23
Refresh period (2,048 cycles) - 2 Meg x 64
Refresh period (2,048 cycles) - 2 Meg x 64 S version
IREF
32
IREF
32
128
128
ms
ms
IRP
40
50
ns
RAS to CAS precharge time
RAS precharge tlme dUiing SELF REFRESH
IRPC
0
0
ns
tHPs
110
130
ns
Read command hold time (referenced to RAS)
IRRH
0
0
ns
19
RAS hold time
IRSH
15
17
ns
25
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
IRWC
IRWD
155
182
92
ns
ns
25
23,30
ns
25
RAS precharge time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WE command setup time
Output disable delay from WE (CAS HIGH)
Write command pulse width
WE pulse width for output disable when CAS HIGH
WE hold time (CBR REFRESH)
WE setup time (GBR REFRESH)
MTBLD{T)264(X)(S)
DM32.pm5 - Rev. 2/95
IRWL
IT
IWCH
IWCR
IWCS
tWHZ
twp
82
20
2
20
50
2
50
31
ns
15
17
ns
25
43
53
ns
24
ns
ns
23,30
2
2
18
2
2
20
27
IWPZ
10
10
12
12
ns
ns
'WRH
tWRP
8
12
8
12
ns
22,24
ns
22,23
5-80
Micron Technology, Inc., reserves the right to change products or spec1fications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
;00<"'"''''
NOTES
19. Either tRCH or tRRH must be satisfied for a READ
cycle.
20. toFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE = LOW and
OE=HIGH.
22. tWTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverse of twRP and twRH in the
CBR REFRESH cycle.
23. A +2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
24. A -2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
25. A +Sns timing skew from the DRAM to the module
resulted from the addition of line drivers.
26. A -2ns (MIN) and a -Sns (MAX) timing skl'w from t 111'
DRAM to the module resulted from the addition ot
line drivers.
27. A +2ns (MIN) and a +Sns (MAX) timing skew from
the DRAM to the module resulted from the addition
of line drivers.
28. The maximum current ratings are based with the
memory operating or being refreshed in the x64
mode. The stated maximums may be reduced by onehalf when used in the x32 mode.
29. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
30. twcs, tRWD, tAWD and tCWD are not restrictive
operating parameters. twcs applies to EARLY
WRITE cycles. tRWD, tAWD and leWD apply to
READ-MODIFY-WRITE cycles. If twcs ~ twcs
(MIN), the cycle is an EARLY WRITE cycle and
the data output will remain an open circuit throughout the entire cycle. If tRWD ~ !RWD (MIN),
tAWD ~ tAWD (MIN) and tCWD ~ tCWD (MIN), the
cycle is a READ-MODIFY-WRITE and the data output
will contain data read from the selected cell. If neither
of the above conditions is met, the state of data-out is
indeterminate. OE held HIGH and WE taken LOW
after CAS goes LOW results in a LATE WRITE (OEcontrolled) cycle. twcs, tRWD,tCWD and tAWD are
not applicable in a LATE WRITE cycle.
1.
2.
3.
4.
All voltages referenced to Vss.
This parameter is sampled. Vee = +3.3V; f = 1 MHz.
Ice is dependent on cycle rates.
Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOlls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
8. AC characteristics assume IT = Sns for FPM and 2.5ns
forEDO.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF and VOL = 0.8V and VOH = 2.0V.
14. Assumes that tRCD < tRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, !RAC will increase by the amount that tRCD
exceeds the value shown.
15. Assumes that tRCD ~ tRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for tCPN.
17. Operation within the tRCD (MAX) limit ensures that
tRAC (MAX) can be met. tRCD (MAX) is speCified as
a reference point only; if tRCD is greater than the
specified tRCD (MAX) limit, access time is controlled
exclusively by tCAe.
18. Operation within the tRAD (MAX) limit ensures that
tRAC (MIN) can be met. tRAD(MAX) is specified as a
reference point only; if !RAD is greater than thespecified tRAD (MAX) limit, access time is controlled
exclusively by tAA.
MT8LO(T)264(X)(S)
DM32.pm5 - Rev. 2/95
5-81
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
z
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II
c
JJ
»
s:
-c3:
3:
ADVANCE
UII:::: 1=1CN
1-·
0'"''
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
,
NOTES (continued)
z
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31. Refresh must be completed within the time of three
external refresh rate periods prior to active use of the
DRAM (provided distributed CBR REFRESH is used
when in the active mode.) Alternatively, a complete
set of row refreshes must be executed when exiting
SELF REFRESH prior to active use of the DRAM if
anything other than distributed CBR REFRESH is
used in the active mode.
32. Column-address changed once each cycle.
33. The 3ns minimum is a parameter guaranteed by
design.
34. tpDOFF MAX is determined by the pullup resistor
value. Care must be taken to ensure adequate
recovery time prior to reading valid up-level on
subsequent DIMM position.
35. Measured with the specified current load and lOOpf.
36. For FAST PAGE MODE option, toFF is determined
by the first RAS or CAS signal to transition HIGH. In
comparison, IOFF on an EDO option is determined by
the latter of the RAS and CAS signal to transition
HIGH.
37. Applies to both EDO and FAST PAGE MODEs.
II
c
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3:
-c3:
3:
M:T8LD(T)
100
//;=1//;=1//=1//=1//;7771//;7771/;777111####$$;
EARLY WRITE CYCLE
ADDR
:D
~gt --------OPEN-----~~~VA~lID~DA~TAj~OPEN ..
I.
DE
c
NOTE'
~
iCAC
m
=E
II
~
I~L
DQ
z
I
COLUMN
'RCS
VJjjjjjJ
~NOTE1
ICAS
I
~!
tRAH __
~I
1
~ 'i
I
~-
ROW
_14tWR~1
I
IRCD
=~
'RSH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-'
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
,,,""',,,,,,
FAST-PAGE-MODE READ CYCLE
-----------------------'~RA~SP~---------------------I~
z
m
:E
II
c
RAs
V,H
VIL
-
CAS
V,H
VIL
-
ADDR
V,H
VIL
-
WE
V,H
VIL
-
ROW
1
II 'C1:-AC -
DQ
l>
=:-----
~:g~
1:-
VALID
DATA
~
s:
1:-
tell ---
VALID
OPEN
tePA
I~
'CAe
tcLZ-
iCLZ---
I
tePA
I~- 2!.
tOFF
:IJ
,
=
tRAG
~- ~
-'2'l
-
-'OFF
VALID
DATA
r--
~ ~
-'2'l
-S
C
S
EDO-PAGE-MODE READ CYCLE
37
RASP
CAs
teAS'
~:t -~J--i,----'CT---------'A-R----,~"~- ~-I.,'ASR
ADDR
'RCO
~:~
!;lInt
WI,&.
'wRPII'wRHu-r
WE
~:t ~NOTE11
1
WEI I
yVOOlH ----- - - - - OPEN
-
OE
~II~I
W/////;jJ.
I 'AA
't:'
I
I~ I DATA
"tf:.MN
VALID
~:t -$77770@770lI;)=lI/;=lI/;'7T.///;'7T.W/;'7T.1!/;TTTWTTT1!/;TTT1!/;777w/;TT7Tw>r--~1
'e~;~
I
I
1______-:-1-,te""P,-,-A_I
-
PL-
1---,"R""SH'------1
'CP
'CAS
'RAl
II
I
I
ROW
COLUMN
I
I
I
I ,'ARAAe
_I
'eAH'_1
COLUMN
I
I
.
telZ
DQ
WI/I//;#!
COLUMN
l
~-- ~-'ep
-
hi .~I I~ ~ '" ~
ROW
'CAS
tpc
'ep
'CSH
1 'eRP
I
I ::A
I
!
'RCH~
~
.
tCAC
,,~~~- I~
~ ~~ ----+~W---',v~Alill'o,----l'--OPEN
..JfV~
Wr-----T'O"'-AT'-"-A---1_,,-o-'f' .
At=;'OE~P=Jt==='OE=S=l.-.--lwz~
[Zj DON'T CARE
!22l UNDEFINED
NOTE:
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and IWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MTBLD(T)264(X)(S)
DM32.pmS - Rev. 2195
5-84
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
2 MEG
,,,"",wen,
X
MTBLD{T)264(X)(S)
64 DRAM MODULE
FAST-PAGE-MODE EARLY-WRITE CYCLE
z
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~:~
~=
%
!III///!III/////////IIII////////II!II/IIII/////!i///II/11/111111/1111///III///I///I/I/!!II11//11/////////II$//!@////;
'RASP
'CSH
NOTE:
ADDR
~I~
DQ
~:gt
tpc
'RSH
______~IRC~D~.I~IC~AS~~II~~lc~p___ II_~IC~~~.II_~~~P___ II_~lc=~~_1
-~~illlliU~~-L-
DATA
_ _VALID
_ _ DATA
_ _ _ _X~UL_ _ _VALID
_ _DATA
_ _ _~~~l~_ VALID
___
_ _-X'~illlilllliU~
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system deSigner
should .implement WE HIGH for WRP and tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT8LD(T)264(X)(S)
DM32.pm5 - Rev. 2/95
5-85
s:
-:Cs:
:s:
EDO-PAGE-MODE EARLY-WRITE CYCLE
~1
::D
l>
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MU::F=lCN
I-a
2 MEG
'''"'0"'"''''
X
MTBLD(T)264(X)(S)
64 DRAM MODULE
READ WRITE CYCLE 37
(LATE WRITE and READ-MODIFY-WRITE cycles)
tRAS
'RP
tCSH
tRSH
z
m
:E
II
c
t
leRP
tRCD
'CAS
I
I
--
-
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-cs:
"'
~:t :1////$,@//PP//$ffiW'P/P/$//#i/;0'd~
)c-'O_D------I77T77i==770
EDO/FAST-PAGE-MODE READ-WRITE CYCLE 37
(LATE WRITE and READ-MODIFY-WRITE cycles)
s:
NOTE:
~
DON'T CARE
~
UNDEFINED
1. 'PC is for LATE WRITE cycles only.
2. Although WE is a "don't care" ilt RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and IWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MTBLD(T)264(X)(S)
DM32.pm5 - Rev. 2/95
5c86
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
RAS-ONLY REFRESH CYCLE
(WE = DON'T CARE)
AAS
CAS
ADDR
~:t
_
IL
DQ VOH
-
tCRP
IASR
II.
ROW
-
\\-
t~
tRAS
'RAH
b///;1;1U$$/U$#$$$;1/@&(
:~
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ROW
\1
OPEN
~\I~
~:t -~
37
'RC
~'
_
VOL
WE
d
~IH
~IH -~
IL
MTSLD(T)264(X)(S)
x 64 DRAM MODULE
2 MEG
""'"""'''
~I~
~$//ull/l///$I/!///;1;1/////////////I/II/J
~
c
:c
»
s:
EDO-PAGE-MODEREAD-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
-c3:
tRASP
~:~=
RAS
3:
tCSH
tpc
teRP
I_ _---"'R""CD'---+-_~ I_-"c,,-P_ I
tpe
IRSH
~ 1_--"c,,-p_ _ I_'_CA_S__
WE
I~
DQ
'~:g~=-_~~_ OPEN ----:--i=~V~AL~ID~DAT~A~(A)=~~~~
'OE
DE
NOTE:
~:t= W'$$;I////$ffi!$#$#lm-~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementation will facilitate compatibility With··
future EDO DRAMs.
.
MT8lD(T)264(X)(S)
DM32.pmS - Rev. 2195
5-87
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-'
2 MEG
",,,,wee",,,,,
MTBLD(T)264(X)(S)
x 64 DRAM MODULE
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODiFY-WRiTE)
tCSH
z
~.
tRCD
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c
"
~:t :w/ / / / /~ J'~l l
'00' .1"'1"
f
s:
s:
Q
DE
H~////~/I1////I1///?'
~II~
I
o
1
~:r 4///////////////////////////////////////~//////////~
I=l~i
VALID DATA
b//,M/////////////,0;
~gr ::--~--+I-OPEN--+-I.--tAA----i1\lVX»r·~}-----OPEN
~i~
=7lllA
tRAC
ULCL.L.L.A._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
PRESENCE-DETECT READ CYCLE
POl-poe
NOTE:
~
DONTCARE
~
UNDEFINED
37
~_tPD_l~~,
VALID PRESENCE-DETECT
1 .. [)O not drive data prior to tristate.
2. PD pins must be pulled HIGH at next level.
MTSLD(T)264(X)(S)
OM32.pm5 - Rev. 2195
5-88
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MTBLD(T)264(X)(S)
2 MEG x 64 DRAM MODULE
""'ow"",,,
EDO READ CYCLE
(with WE-controlled disable)
RAS
V,H
----~~
Vll_
==========t:RC:D==~'-I-.
tCSH
tCRP , =:
-"'tCA"'S--1
tcp
CAS V,H - . I·.---c;--------~
r±------,[
VIL
~~
z
'--f~--~LJ
V,H __
ADDR
WE
TTT:'7\.l:---LL---,l n7TT.'" jr--'----'------,['TTT:'7TTm-r77T7TTAjr---''----VIL -lLLLLrK_-c---,,--;:-~-' '<-LLLLL/ l--,--_,---,---_-"~lLLLLLLLf-LL''-LLLlLL/1L---,Cr_0L-UM-N-VIH __TTT.rTTTTl7Ziz---'----tn7777-,--rl:-;-----;-----'-----.J
~g~
-_------
OPEN-------1iZ~~~~~_f OPE~W '6
. I. tOE
OE
~:~ -W!/I/////////////////111///J/////!II$I!////II&),-
I. taD
II/;;;III$;;/!II///IIIII///;
HIDDEN REFRESH CYCLE21,37
(WE = HIGH; OE= LOW)
(READ)
I~
tRCD
J
ADDR
tAR
1-
- ~~
~:~C
I
OE
NOTE:
'V
tAAH
I
DO
tCHR
~~~
~I~
~IHI:
IL~~
-
tRAS
tASH
1
:~~ ~k.
- t~
~:gt ='-------OPEN-----~~t~===V~AL~ID~DA~TA~===:j~ OPEN-
~:~ -W$I//#I//###/#&0"<W#ml~
,I
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and tWRH. This design implementatioh will facilitate compatibility with
future EDO DRAMs.
MTSLD(T)264(X)(S)
DM32.pm5 - Rev. 2195
5-89
::D
l>
s:
-C3:
3:
(REFRESH)
-
tRAS
I~
•
C
V IL -LLL..L,u..LL
Vv lH
IL -
.~
..
RP
~
tRPC
ICSR
~~
RAS
.
• I
1
WCHR
II
OPEN---;-I;-I- - - - - - - - tWRH
tWRP
II
tWRH
~:r $/$$@- -W;///$;//$;/////;)- -W/;//;//////;///$/;/;//$/a
3:
c
s:
s:
SELF REFRESH CYCLE 37
(Addresses and OE = DON'T CARE)
NOTE,
'RP
'RASS
: :::
DO
WE
'RPS
;~ffffffffffffffff/$ff;~/;rlr~
IllY-oPEN
VOHVOL
II
tWRP
II
tWRH
II
'.
-
tWRP
If
tWRH
~:~ :J$/$!IlJ- ~W4~//$ff/#//$J#$$$$$$#;)-~W;$J$/#$&
~
DON'TCARE
m
UNDEFINED
NOTE:
MT8LD(T)264(X)(S)
DM32.pm5 - Rev. 2195
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a compete burst of all rows should be executed.
5-90
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, tnc.
PRELIMINARY
UII::::I=ICN
1-·
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
","'"coo,",
1 MEG, 4 MEG x 72
DRAM
MODULE
8,32 MEGABYTE, ECC, 5V, FAST PAGE
MODE, OPTIONAL SELF REFRESH
FEATURES
PIN ASSIGNMENT (Front View)
• JEDEC- and industry-standard ECC pinout in a 168pin, dual-in-line memory module (DIMM)
• High-performance CMOS silicon-gate process
• Single +5V ±10% power supply
• All device pins are TTL-compatible
• Low power, 54mW standby; 4,050mW active, typical
(8MB)
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN; optional Extended and SELF REFRESH
• All inputs are buffered except RAS
• 1,024-cycle refresh distributed across 16ms or
1,024-cycle Extended Refresh distributed across 128ms
(1 Meg x 72)
• 2,048-cycle refresh distributed across 32ms
(4 Meg x 72)
• FAST PAGE MODE (FPM) access cycle
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
-7
• Components
SOJ
TSOP
G
Blank
S
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
IpC
tAA
tCAC
tRP
-6
-7
110ns
l30ns
60ns
70ns
35ns
40ns
35ns
40ns
20ns
25ns
40ns
50ns
VALID PART NUMBERS
PART NUMBER
DESCRIPTION
MT18DT172G-xx
MT18DT172G-xx S
MT18D172G-xx
MT18D172G-xx S
MT18DT472G-xx
MT18D472G-xx
1 Meg
1 Meg
1 Meg
1 Meg
4 Meg
4 Meg
x 72
x 72
x 72
x 72
x 72
x 72
EGG,
EGG,
EGG,
EGG,
EGG,
EGG,
TSOP
S", TSOP
SOJ
S", SOJ
TSOP
SOJ
"S = SELF REFRESH
MT18D(T)172(S), MT18D(T)472
OM52.pm5 - Rev. 2195
SYMBOL
Vss
000
001
D02
003
Vee
004
005
006
007
DOS
Vss
009
0010
0011
0012
0013
Vee
0014
0015
0016
0017
Vss
NC
NC
Vee
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
WED
28
C7iSO
29
RFU
30
RASO
31
OEO
32
Vss
AO
33
34
A2
A4
35
36
A6
37
A8
NC/A10'
38
39
NC
40
Vee
41
RFU
42
RFU
• 4 Meg x 72 version
D
• Refresh
Standard Refresh/16ms or 32ms
SELFREFRESH/128ms
m
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•
illY~s:~q,g"rnJ J c
PINt
DT
• Packages
168-pin DIMM (gold)
z
168-Pin DIMM
(DE-13) SOJ version
(DE-14) TSOP version
5-91
PIN #
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
only
SYMBOL
Vss
TIE2
RAS2
CAS4
RFU
WE2
Vee
NC
NC
0018
0019
Vss
0020
0021
0022
0023
Vee
0024
RFU
RFU
RFU
RFU
0025
0026
0027
Vss
0028
0029
0030
0031
Vee
0032
0033
0034
0035
Vss
P01
PD3
P05
PD7
100
Vee
PINt
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SYMBOL
Vss
0036
0037
DQ38
0039
Vee
0040
0041
0042
0043
0044
V",;
U04b
D046
0047
0048
0049
Vee
0050
0051
0052
0053
Vss
NC
NC
Vee
RFU
NC
RFU
NC
RFU
Vss
A1
A3
A5
A7
A9
NC
NC
Vee
RFU
80
PIN #
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
Vss
RFU
NC
NC
RFU
POE
Vee
NC
NC
0054
0055
V""
UO~U
D057
0058
OQ59
Vee
0060
RFU
RFU
RFU
RFU
0061
0062
0063
Vss
0064
0065
0066
0067
Vee
0068
0069
0070
0071
Vss
P02
P04
P06
P08
1D1
Vee
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
::D
»
S
-sc:
3:
PRELIMINARY
UIl::RCN
1-·
z
m
:e
•
c
::D
l>
s:
-s:
C
s:
ce'"",COG""
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
GENERAL DESCRIPTION
REFRESH
The MT18D(T)172(S) and MT18D(T)472 are randomly
accessed 8MB and 32MB solid-state memories organized in
a x72 configuration.
During READ or WRITE cycles, each bit is uniquely
addressed through the 20/22 address bits, which are entered 10/11 bits (AO /BO-AIO) at a time. Two copies of
address 0 (AO and BO) are defined to allow maximum
performance for 4-byte applications which interleave between two 4-byte banks. AO is common to the DRAMs used
for DQO-DQ35, while BO is common to the DRAMs used for
DQ36-DQ71. RAS is used to latch the first 10/11 bits and
CAS the latter 10/11 bits.
READ and WRITE cycles are selected with the WE input.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. EARLY WRITE occurs when WE
goes LOW prior to CAS going LOW, and the output pin(s)
remain open (High-Z) until the next CAS cycle.
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during the
RAS HIGH time. Correct memory cell data is preserved by
maintaining power and executing any RAS cycle (READ,
WRITE) or RAS refresh cycle (RAS ONLY, CBR or HIDDEN) so that all combinations of RAS addresses (AO/BOA9 / AIO) are executed at least every tREF, regardless of
sequence. The CBR REFRESH cycle will invoke the internal
refresh counter for automatic RAS addressing.
An additional SELF REFRESH mode is also available on
the 1 Meg x 72. The "5" version allows the user the option of
a fully static low power data retention mode.. or a dynamic
refresh mode at the extended refresh period. The module's
SELF REFRESH mode is initiated by executing
a CBR REFRESH cycle and holding RAS LOW for the
specified tRASS. Additionally, the "5" version allows for
extended refresh rate of 125fls (8MB) per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation, as well as during a standby or
extended refresh mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for the time minimum of an operation cycle, typically
tRPS. This delay allows for the completion of any internal
refresh cycles that may be in process at the time of the
RAS LOW-to-HIGH transition. If the DRAM controller uses
a distributed CBR REFRESH sequence, a burst refresh is not
reqUired upon exiting SELF REFRESH mode. However, if
the DRAM controller utilizes RAS ONLY or burst refresh
sequence, all 1,024 rows must be refreshed within 300fls,
prior to the resumption of normal operation.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined
page boundary. The FAST PAGE MODE cycle is always
initiated with a row-address strobed-in by RAS followed
by a column-address strobed-in by CAS. CAS may be
toggled-in by holding RAS LOW and strobing-in different
column-addresses, thus executing faster memory cycles.
Returning RAS HIGH terminates the FAST PAGE MODE
operation.
MT18D(T)172(S), MT18D(T)472
DM52.pm5 - Rev. 2/95
5-92
Micron Technology, Inc., reserves the right to change products or speCifications Without notice.
©1995,Micron Technology, Inc.
PRELIMINARY
MICRON
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
"'~"'co,,'"
1-·
FUNCTIONAL BLOCK DIAGRAM
DOD· 003
till
AO l6>---IAO
OQl-4
WE
WED
RAS
RAsa
CASO
ttt!
AD OQl-4
WE
U1
OED i o > - - - I O E
004 '. DO?
DOS
,~
0011
ttll
AO OQl-4
WE
U'
OE
RAS
-Jv---j
DE
0012 - 0015
0016 - OQ19
OQ20 ,. OQ23
DQ24 '. 0027
ttl!
AO OQl-4
AO OQl-4
tttt
AO DOl-4
AO DOl-4
AD 001-4
WE
WE
ttl!
AD DOl-4
WE
U3
DE
WE
U4
DE
WE
U5
DE
U6
tttt
OE
OQ28·· OQ31
U7
DQ32 ,. OQ35
WE
U8
UO
DE
RAS
RAS
RAS
RAS
RAS
RAS
RAS
CA"§Al-Al
CASAl-Ala
CASA1-Al
CASA1-Al0
CASA1-Al
CASA1-A1D
CASA1-Al0
z
m
:e
0044 ,. D047
ntl
AO 001-4
WE'
WE
6E2
OE
D048 ,. 0051
0052 ,. DOSS
tt n
AD DOl-4
WE
U12
OE
U13
0056 ,. 0059
D060 ,. 0063
DQ64 - 0067
ttl!
AO DOl-4
WE
OE
DQ68, D071
o
ttl!
AO DQl-4
WE
U17
RAS2
!lA~
CAS4
CASAl AIO
UlO
01
CI\:,f.. \ 1'110
•
c
:D
»
S
-c3:
3:
1 Meg x 72 . MT18D(T)172G (S)
U1-U18=1 Megx4DRAMs
~~PD1-PD8
4 Meg x 72 -,MT18D(T)472G
U1-U1B = 4 Meg x4 DRAMs
•••
PDE _ _ _ _ _--1
NOTE:
1. All inputs with the exception of RAS are red riven.
2. 0 = line buffers.
MT180(T)172(S), MT18D(T)472
DM52.pm5 - Rev. 2/95
5-93
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
,,,,,",cee,,,,,
MT18D(T)172(S), MT18D(T)472
1 MEG , 4 MEG x 72 DRAM MODULES
,
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
30,45
RASO, RAS2
Input
28,46
CASO, CAS4
Buffered Input
27,48
WEO, WE2
Buffered Input
Row-Address Strobe: RAS is used to clock-in the 10/11
row-address bits, Two RAS inputs allow for one x72 bank
or two x36 banks.
Column-Address Strobe: CAS is used to clock-in the 101
11 column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles.
Write Enable: WE is the REAOIVVRITE control for the DO
pins. WEO controls 000-0035. WE2 controls 00360071. If WE is LOW prior to CAS going LOW, the access
is an EARLY WRITE cycle, If WE is HIGH while CAS is
LO\A/, the access i~ a READ cycle, provided OE is also
LOW. If WE goes LOW after CAS goes LOW, then the
cycle is a LATE WRITE cycle. A LATE WRITE cycle is
generally used in conjunction with a READ cycle to form a
READ-MODI FY -WRITE cycle.
Output Enable: OE is theinput!output control for the DO
pins. OEO controls 000-0035, OE2 controls 00360071. These signals may be driven, allowing LATE
WRITE cycles.
z
m
:e
III
I
c
:IJ
»
:s:
c
s:
s:
31,44
OEO, OE2
Buffered Input
33-38,117-121,126
AO-A10, BO
Buffered Input
Address Inputs: These inputs are multiplexed and clocked
by RAS and CAS. AO is common to the DRAMs used for
000-0035 while BO is common to the DRAMs used for
0036-0071
2-5,7-11,13-17,19-22,
52-53, 55-58, 60, 65-67,
69-72,74-77,86-89,
91-95,97-101,103-106,
136-137,139-142,
144,149-151,153-156,
158-161
79-82, 163-166
000-0Q71
Input!
Output
Data 1/0: For WRITE cycles, 000-0071 act as inputs to
the addressed DRAM location. For READ access cycles,
000-0071 act as outputs for the addressed DRAM
location.
P01-P08
Buffered
Output
Presence-Detect: These pins are read by the host system
and tell the system the OIMM's personality. They will be
either driven to VOH (1) or they will be driven to VOL (0).
29,41-42,47,61-64,111,
113,115,125,128,131,
145-148
6,18,26,40,49,59,73,
84,90,102,110,124,
133,143,157,168
RFU
MT18D(T)172(S),
MT18D(T~72
DM52.pm5 - Rev. 2/95
Vcc
-
Supply
I
RFU: These pins should be left unconnected
(reserved for future use).
Power Supply: +5.0V ± 10%
5-94
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc
PRELIMINARY
MIC:RON
1-·
MT18D(T)172(S), MT18D(T)472
1 MEG,4 MEG x 72 DRAM MODULES
","",,,,,,,
PIN DESCRIPTIONS (continued)
PIN NUMBERS
SYMBOL
TYPE
1,12,23,32,43,54,
68,78,85,96,107,116,
127, 138, 152, 162
Vss
Supply
Ground
83, 167
IDO,ID1
Output
ID bits: IDO = DIMM type. ID1 = Refresh Mode. These
pins will be either left floating (NC) or they will be
grounded (Vss).
132
PDE
24-25, 39, 50-51,
108-109,112,114,
122-123,129,130,
134-135,150,161
NC
DESCRIPTION
Presence-Detect Enable: PDE is the READ control for the
buffered presence-detect pins.
Input
-
No connect
z
m
:e
c
:c
TRUTH TABLE
ADDRESSES
IR
IC
DATA-IN/OUT
RAS
CAS
WE
or
POE
Standby
H
H~X
X
X
X
X
X
High-Z
READ
L
L
H
L
X
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
X
ROW
COL
Data-In
READ WRITE
L
L
H~L
L-H
X
ROW
COL
Data-Out, Data-In
FUNCTION
000-71
FAST-PAGE-
1st Cycle
L
H~L
H
L
X
ROW
COL
Data-Out
MODE READ
2nd Cycle
L
H~L
H
L
X
n/a
COL
Data-Out
FAST-PAGE-
1st Cycle
L
H~L
L
X
X
ROW
COL
Data-In
MODE EARLY-WRITE 2nd Cycle
L
H-L
L
X
X
n/a
COL
Data-In
FAST-PAGE-
1st Cycle
L
H~L
H~L
L~H
X
ROW
COL
Data-Out, Data-In
MODE READ-WRITE
2nd Cycle
Data-Out, Data-In
RAS-ONLY REFRESH
L
H~L
H~L
L~H
X
n/a
COL
H
X
X
X
X
ROW
n/a
High-Z
H
L
X
ROW
COL
Data-Out
Data-In
HIDDEN
READ
L~H-L
L
REFRESH
WRITE
L~H~L
L
L
X
X
ROW
COL
CBR REFRESH
H~L
L
H
X
X
X
X
High-Z
SELF REFRESH (S version)
H-L
L
H
X
X
X
X
High-Z
X
X
X
X
L
X
X
Not Affected
READ PRESENCE-DETECTS
VlT18D(T)172(8), MT1S0(T)472
JM52.pm5 - Rev. 2f95
5-95
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
»
s:
c
s:
s:
PRELIMINARY
MICRON
1-·
"'"",co",'"'
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
PRESENCE-DETECT TRUTH TABLE
z
:E
m
- ..-...
c
~s::
Page Mode
-:s:C
Access Timing
:s:
Refresh Control
Data Width, Parity
NOTE: Vss = ground; 0 =VOL; 1 = VOH .
• This addressing includes a redundant address to allow mixing of 12/10 and 11/11 DRAMs with the same presence-detect
setting. TheMT18D(T)472 uses 11/11 DRAMs.
MT18D(T)172(S), MT18D(T)472
DM52.pm5- Rev, 2/95
5-96
Micron Technology, tne., resetves the right to change products or specifications without notice.
©1995, Micron Technology, Inc
PRELIMINARY
MICRON
1-·
MT18D(T)172(S), MT18D(T)472
1 MEG , 4 MEG x 72 DRAM MODULES
,,,"",we,,,,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +5V ±1 0%)
PARAMETER/CONDITION
SYM
MIN
MAX
UNITS
Supply Voltage
Vcc
4.5
5.5
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-0.5
0.8
V
111
-2
2
jlA
RASO, RAS2
112
-18
18
jlA
000-0071,
PD1-PD8
loz
-10
10
jlA
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV ~ VIN ~ 5.5V
(All other pins not under test = OV) for each package input
OUTPUT LEAKAGE CURRENT
(0 is disabled; OV ~ VOUT ~ 5.5V) for each package input
CASO, CAS4
AO-A 10, BO, POE
WEO,2,OEO,2
OUTPUT LEVELS
Output High Voltage (lOUT = -5mA)
Output Low Voltage (lOUT = 4.2mA)
NOTES
z
m
==
C
:IJ
V
VOL
0.4
»
:s:
V
MAX
-6
-7
8MB
32MB
36
56
36
56
8MB
32MB
Icc2
8MB
(S only) 32MB
18
29
3.6
18
29
3.6
SYMBOL SIZE
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS = CAS = VI H)
Icc1
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
ICC2
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
Icc3
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC = tpc [MIN])
Icc4
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC = IRC [MIN])
Icc5
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
Icc6
REFRESH CURRENT: Extended (S version only)
Average power supply current; CAS = 0.2V or CBR cycling;
RAS = IRAS (MIN); WE= Vcc -0.2V; AO/BO-A10, OE and
DIN =Vcc -0.2V or 0.2V (DIN may be left open);
IRC = 125jlS (8MB)
REFRESH CURRENT: SELF (S version only)
Average power supply current; CBR cycling with RAS ~
IRASS (MIN) and CAS held LOW; WE = Vcc -0.2V; AO/BO-A10,
OE and DIN = Vcc-0.2V or 0.2V (DIN may be left open)
MT1SD(T)172(S), MT180(T)472
DMS2.pmS - Rev. 2/95
5-97
-
UNITS NOTES
mA
28
mA
28
mA
3,4,
28, 32
mA
3,4,
28,32
mA
3,28
32
mA
3,5,
28
-
8MB
1,980
1,800
32MB
2,160
1,980
8MB
1,440
1,260
32MB
1,620
1,440
8MB
1,980
1,800
32MB
2,160
1,980
8MB
1,980
1,800
32MB
2,160
1,980
Icc?
(S only)
8MB
5.4
5.4
mA
3,5,
28, 31
Iccs
(S only)
8MB
5.4
5.4
mA
5,28
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc
c
s:
s:
-
PRELIMINARY
MICRON
1-·
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
'''",0'00,,"'
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Vss .................... -IV to +7V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SsoC to +12SoC
Power Dissipation ........................................................... I8W
Short Circuit Output Current ..................................... SOmA
z
m CAPACITANCE
:e
•
c
:c
»
s:
-sc:
s:
PARAMETER
MAX
UNITS
NOTES
Input Capacitance: AO-A 10, BO, POE
SYMBOL
CI1
MIN
9
pF
2
Input Capacitance: WED, WE2, OEO, OE2, CASO, C/'\,S4
Cl2
9
pF
2
Input Capacitance: RASO, RAS2
CI3
70
pF
2
Input/Output Capacitance: 000-0071
CIO
10
pF
2
Output Capacitance: P01-P08
Co
9
pF
2
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7,8, 9, 10, 11, 12, 13) (Vce =+5V ±1 0%)
MIN
Access time from column-address
SYM
tAA
Column-address hold time (referenced to RAS)
tAR
48
2
5
57
Column-address setup time
tASC
Row-address setup time
tASR
tAWD
Column-address to WE delay time
Access time from CAS
tCAH
tCAS
CAS pulse width
RAS LOW to "don't care" during SELF REFRESH
CAS hold time (CBR REFRESH)
..
tCHD
CAS precharge time
tCHR
tCLZ
tcp
Access time from CAS precharge
tCPA
CAS to RAS precharge time
tCRP
CAS hold time
CAS setup time (CBR REFRESH)
tCSH
tCSR
CAS to output in Low-Z
,
tCWD
Write command to CAS lead time
Data-in hold time
tCWL
Data-in hold time (referenced to RAS")
tDHR
Data-in setup time
Output disable
Output enable
tDH
tDS
too
tOEH
Output buffer turn-off delay
tOFF
MT180{T)172(S), MT18D(T)472
DM52.pm5 - Rev. 2/95
5-98
MIN
13
5
UNITS
NOTES
40
ns
25
24
23
25
23,30
15,25
25
10,000
15
15
20
ns
ns
ns
ns
25
20
20
10
8
5
10
40
15
58
12
42
15
15
45
-2
3
MAX
53
2
5
67
20
15
15
10
8
5
10
tOE
OEhold time from WE during READ-MODIFY-WRITE cycle
MAX
35
tCAC
Column-address hold time
CAS to WE delay time
-7
-6
AC CHARACTERISTICS
PARAMETER
ns
10,000
18
5
ns
ns
ns
ns
ns
45
15
68
12
52
20
20
55
-2
3
ns
ns
ns
ns
ns
ns
36
5,24
23,33
16
25
25
24
5,23
23,30
ns
ns
25,29
ns
20
20
ns
ns
ns
ns
25
24,29
33
ns
24
20,27
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc
PRELIMINARY
MICRON
1-·
MT18D(T)172(S), MT18D(T)472
1 MEG,4 MEG x 72 DRAM MODULES
m~,,,o",",
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+5V ±1 0%)
AC CHARACTERISTICS
PARAMETER
OE setup prior to RAS during HIDDEN REFRESH cycle
FAST"PAGE-MODE READ or WRITE cycle time
PDE to valid presence-detect data
PDE inactive to presence-detects inactive
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
RAS pulse width during SELF REFRESH
Random READ or WRITE cycle time
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (2,048 cycles) - 4 Meg x 72
Refresh period (1,024 cycles) - 1 Meg x 72
Refresh period (1,024 cycle.s) -.1 Meg x 72 S version
RAS precharge time
RAS to CAS prechargetime
RAS precharge time during SELF REFRESH
Read command hold time (referenced to RAS)
RAS hold time
READ WRITE cycle time
RAS to WE delay time
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MTI8D(T)172(S), MTI8D(T)472
DM52.pm5 - Rev. 2/95
-6
SYM
tORD
tpc
tpD
MIN
0
35
tpDOFF
tpRWC
tRAC
tRAD
tRAH
tRAL
IRAS
IRASP
IRASS
IRC
2
87
IRCD
IRCH
IRCS
IREF
IREF
IREF
IRP
IRPC
IRPS
IRRH
IRSH
IRWC
IRWD
IRWL
IT
IWCH
twCR
twcs
IWp
twRH
tWRP
5-99
-7
MAX
MIN
10
13
8
35
60
60
100
110
18
2
2
10
2
97
60
25
10,000
100,000
40
13
8
40
70
70
100
130
18
2
2
32
16
128
40
0
110
0
20
155
87
20
3
15
43
2
10
8
12
MAX
0
40
50
70
30
10,000
100,000
45
32
16
128
50
0
130
0
25
185
97
25
3
20
53
2
15
8
12
50
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
20
~
36
ns
ns
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
35
34
23
14
18,26
24
25
z
m
=e
c
17,26
19,23
23
36
19
25
25
23,30
25
25
24
23,30
22,24
22,23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
lJ
l>
s:
-s:C
s:
PRELIMINARY
MIC:RON
1-·
"""CO,,",
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
NOTES
Z
m
=E
•
C
::D
»
s:
-cs:
s:
1. All voltages referenced to Vss.
2. This parameter is sampled. Vee = +SV ±10%;
f= 1 MHz.
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading. Specified values
are obtained with minimum cycle time and the
outputs open.
S. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pau~e uf 100/-ts is reqUired after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CoR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume IT = Sns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification,
all input signals must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
IS. Assumes that IRCD;:>: IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by ICAe.
18. Operation within the lRAD (MAX) limit ensures that
IRAC (MIN) and ICAC (MIN) can be met. IRAD
(MAX) is specified as a reference point only; if IRAD is
greater than the specified tRAD (MAX) limit, access
time is controlled exclusively by IAA.
MT18D(T)172(S}, MT18D(T)472
DM52.pm5 - Rev. 2/95
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE = LOW and
OE=HIGH.
22. twTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverse of twRP and twRH in the
CBR REFRESH cycle.
23. A +2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
24. A -2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
2S. A +Sns timing skew from the DRAM to the module
resulted from the addition of line drivers.
26. A -2ns (MIN) and a -Sns (MAX) timing skew from the
DRAM to the module resulted from the addition of
line drivers.
27. A +2ns (MIN) and a +Sns (MAX) timing skew from
the DRAM to the module resulted from the addition
of line drivers.
28. The maximum current ratings are based with the
memory operating or being refreshed in the x72 mode.
The stated maximums may be reduced by approximately one-half when used in the x36 mode.
29. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
30. twcs, IRWD, tAWD and ICWD are not restrictive
operating parameters. twcs applies to EARLY WRITE
cycles. IRWD, IAWD and ICWD apply to READMODIFY-WRITE cycles. IftwCS;:>:twcs (MIN), the
cycle is an EARLY WRITE cycle and the data output
will remain an open circuit throughout the entire
cycle. IfIRWD;:>: IRWD (MIN), IAWD;:>:IAWD (MIN)
and tcWD;:>: ICWD (MIN), the cycle is a READMODIFY-WRITE and the data output will contain
data read from the selected cell. If neither of the above
conditions is met, the state of data-out is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. IWCS, IRWD, ICWD and IA WD are not
applicable in a LATE WRITE cycle.
5-100
Micron Technology, Inc., reserves the righllo change products or spec!#ications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
IIUIIICI=ICN
1-·
m~",'oc,,,
MT18D(T)172(S), MT18D(T)472
1 MEG,4 MEG x 72 DRAM MODULES
NOTES (continued)
31. Refresh current increases if lRAS is extended beyond
its minimum specification.
32. Column-address changed once each cycle.
33. The 3ns minimum parameter guaranteed by design.
34. tpDOFF MAX is determined by the pull-up resistor
value. Care must be taken to ensure adequate
recovery time prior to reading valid up-level on
subsequent DIMM position.
35. Measured with the specified current load and 100pf.
36. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
37. tCAC(MIN), tCPA (MIN) and tAA(MIN)arefor
reference only to help aid the user as to when to
expect the earliest data to be accessed. Only tCAC
(MAX), tCPA (MAX) and tAA (MAX) are guaranteed.
z
m
~
•
C
:0
l>
3:
c
-s:
3:
MT1SD{T)172(S), MT180{T)472
DM52.pm5 - Rev. 2/95
5-101
Micron Technology, Inc., reseIVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MIC:RON
1-·
MT18D(T)172(S), MT18D(T)472
1 MEG , 4 MEG x 72 DRAM MODULES
",",''co,,,,
READ CYCLE
~
RC
______=tRA~S_________ II_~tRP____1
I------=~::"---II
1
z
m
I~~I
•
==
ADDA
~\~ ::::~
ROW
~
I
tRRH
I
~\~I
~-
COLUMN
I
I~!
tRCS
C
:D
»
:s:
-cS
S
EARLY WRITE CYCLE
_c------il
_
VIH
RAS
V 1L -
CAS
1"1'----------------4
~:t =J---'~'"eI'
leSH
tRCD
l---;-tRA-D----""'---+-+---:--
ROW
I:iZ1 DON'TeARE
Il88l UNDEFINED
MT18D(T)172(S), MT18D(T)472
DM52.pm5 - Rev. 2/95
5-102
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
"'"'''0"''''
READ WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
tAAS
'RP
d: : :
tCSH
J~
ADDR
~:t
rJ
VIII;)!
~
•
tRCD
'AR
ROW
I
~I
~1
K01&
J
I
W///;II//m/'//m/'!I//&//l
I
I
'RCS
I
II
I
I
I
I
~lgt
-
•
ROW
I~II
:::L_~
IRWD
leWD
IAWD
I
'cczDO
:e
I
COLUMN
~I-
I
~
tRAl I
I~I
I
tRAD
z
m
c
lJ
l>
'AA
s:
-sC:
s:
tRAC
tCAC
I~~I
~
VALIDD OUT
OPEN
~
M
VALID DIN
~I
OPEN
~--
~
FAST-PAGE-MODE READ CYCLE
tRAC
[
tCAC
'CLZOPE:N
I
I
1:-
I~
I
tePA
I
'CAG
'CLZVALID
DATA
~ ~
1:-
I
tCLZ-
VAllO
DATA
~ ~
'cPA
1:- - Jl-toFF
I~
,2f.
VAliD
DATA
~I~I
I:Z:J DON'T CARE
[22l! UNDEF1NED
MT1SD(T)172(S), MT18D(T)472
DM52.pm5 - Rev. 2195
5-103
Micron Technology, Inc., reserves the righllo change products or specifications without notice..
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
m""oc,",",
FAST-PAGE-MODE EARLY-WRITE CYCLE
, RAS P
I_
~I
'CRP
=J
z
m
:e
•
~:t
tRCD
=wt
'AR
'RAD
tP.AH'-
'ASrl
1
ROW
'pc
tCSH
I
I~
ADDR
R-
i
-
'cAS
~i
I I~
~I_~
W//,)i;
COLUMN
'RSH
_'CP_~ _ ' C P _
~
I~
!
l'f
I' 'Ase
I
tCAH~1
COLUMN
IRAL
I~II~I
II
ROW
COLUMN
~
cl ]
l>
s:
-s:C
s:
FAST-PAGE-MODE READ-WRITE CYCLE
(LATE WRiTE and READ-MODiFY-WRiTE cycles)
@DONTCARE
~
'NOTE:
UNDEFINED
1. IpC is for LATE WRITE cycle only.
MT18D(T)172(S), MT18D(T)472
DMS2.pmS - Rev. 2/95
5-104
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, MiCron Technology, Inc.
PRELIMINARY
MICRON
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
, ~
1-·
RAS ONLY REFRESH CYCLE
(WE DON'T CARE)
=
_
CAS
ADDR
~
~:r ..:=0'
~:r
~,----'
,_
II
_'RAS
'RC
~'~~''''PCb_'RP-----Jl,---_
::atr-'--Row-----,'lw////$I!I!/$/I!I!/&t'I!I!M'$##a~--RO-W- 'ASR
,
,;RAH
DO ~g~ - ' - - - - ' - - - - - - - - - O P E N I - - - - - , - - - - - - -
V,L -
'PC
s:
-cs:
tRSH
I'
tep
•
):i-
1l-----------'-------:----:iJ
tCSH
:e
::tJ
-------..1
V,H
RAS
m
c
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
_
z
teAS
s:
ADDR
~:~-
..
.,
~r -W$/////$/,IJI
I
I
F
jf:~!;l;;l$!I;lIl!l$,
IIICWL
~'RCS'1
----;,
_"
-I
-
'-I
.
'RWL~
I
I
,
~II~
~~ :w//Ilj'!l,I//!l,I//d!I$#;i'd$'T~;W;i'//~ "~~" kw;W$$///!0',@
'CLZ
IOFF
TI
NOTE 1
a ~gr:'---------'--OPEN-+---~~n-----OPEN----
I.
DE
NOTE:
~:r
s..W'-LLLA_ _ _ _ _ _--,--_ _ _ _ _ _ _ _ _ _ __
~
DONTCARE
~
UNDEFINED
1. Do not drive data prior to tristate.
MT180(T)172(S), MT18D(T)472
OM52.pm5-R..,..2195
5-105
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995, Micron Technology. lnc.
PRELIMINARY
MICRON
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
"'~""oc,,"
1-·
CBR REFRESH CYCLE
(Addresses and OE = DON'T CARE)
.
tRP
..
tRAS
._1
~
m
=E
•
:~.tcP. '~II'
-
DQ
WE
II
.
..
1_____________
tCSR
tRP~~
/
IIII
1CHR
tRAS
~I
'v
II - - - - - - - - II
II
OPEN-7.-
~:~ -W'U'lI/ffO- -.§U'§U'/II/U'//ir--- -~W§ff/II//I!$II//$///ff;a
tWRP
C
Jl
tCHR
~:t-
CAS
tRP
1
-~
z
II
l>
3:
tWRH
tWRP
tWRH
SELF REFRESH CYCLE
(Addresses and OE = DON'T CARE)
c
s-:
s:
NOTE:
~
DON'TCARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT180(T)172(S), MT18D(T)472
DMS2.pmS - Rev. 2/95
5-106
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
,,,",,eo,,,,,
HIDDEN REFRESH CYCLE 21
(WE = HIGH; OE = LOW)
(READ)
(REFRESH)
tRAS
RAS
VIH
VIL-
CAS
VIHVIL_
tRP
tRAS
~:--~tR-CD------.-.~tR-SH-:~-:------~tCH-R-------
Ir------
m
:E
•
I
C
:xJ
tOFF
DQ
~:gt
-'----------- OPEN-----~W~-,---~V,~AL~ID~DA~TA~---
OPEN-
tOE
OE
~:~ -WU$$&1&%Ij//#///#////d~
.1
PRESENCE-DETECT READ CYCLE
PD1-PD8
NOTE:
~,----tPD
t~e
------,i
_VALIDPRESEN_CE-DETECT
~
DON'T CARE
~
UNDEFINED
1. PO pins must be pulled HIGH at next level of assembly.
MT18D(T)172(S), MT18D{T)472
DM52.pm5 - Rev. 2/95
5-107
z
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
l>
s::
-:s:C
:s:
PRELIMINARY
MICRON
1-·
'''"'''''' "
MT18D(T)172(S), MT18D(T)472
1 MEG, 4 MEG x 72 DRAM MODULES
z
m
:e
•
c
::D
l>
s:
-Cs:
s:
MT18D(T)172(S), MT18D(T)472
DM52.pm5 - Rev. 2195
5-108
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc.
PRELIMINARY
MIC:RON
1-·
HH
CcC
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG,4 MEG x 72 DRAM MODULES
K
1 MEG,4 MEG x72
DRAM
MODULE
8, 32 MEGABYTE, ECC;3.3V, OPTIONAL
SELF REFRESH, FAST PAGE OR EDO
PAGE MODE
FEATURES
PIN ASSIGNMENT (Front View)
168~Pin DIMM
• JEDEC- and industry-standard ECC pinout in a 168pin, dual-in-line memory module (DIMM)
• High-performance CMOS silicon-gate process
• Single +3.3V ±O.3V power supply
• All device pins are TTL-compatible
• Low power, 18mW standby; 3,24OmW active, typical
Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR),
HIDDEN; optional Extended and SELF REFRESH
• All inputs are buffered except RAS
• 1,024-cycle refresh distributed across 16ms or
1,024-cycie Extended Refresh distributed across 128ms
(1 Meg x 72)
• 2,048-cycle refresh distributed across 32ms or
2,048-cycle Extended Refresh distributed across 128ms
(4 Meg x 72)
• FAST PAGE MODE (FPM) or Extended Data-Out
, (EDO) PAGE MODE access cycles
• 5V tolerant 1/ as (5.5V maximum VIH level)
OPTIONS
(DE~15) SOJ version
(DE-16) TSOP version
l[O];,Q",Q,eQ"Q,Q"QJ·
PIU SYMBOL PiNt SYMBOL PIN If SYMBOL
1
Vss
43
Vss
Vss
85
2
000
44
llE2
86
0036
001
45
3
ro\S2
87
0037
0Q2
4
46
"CJ\S4.
88
0038
003
5
47
RFU
89
0039
48
6
Vee
90
Vee
~
7
004
49
Vee
91
0040
0041
8
005
50
NC
92
9
006
51
93
0042
NC '
10
007
00)8
94
0043
52
11
008
0019
95
0044
53.
Vss
12
Vss
54
Vss
96
13
0'09
97
0045
55
0020
'14
0010
0021
98
0046'
56
15
00:11
Dan 99 0047
57
16
58
100
0048
0012
0023
0013
Vee
101
0049
17
59
18
Vee
60
0024
102
Vee
19
0014
61
RFU
103
0050
20
0015
RFU
104
0051
62
21
0016
63
RFU
105
0052
22
0053
0017
64
RFU
10.6
Vss
23
Vss.
65
·.0025
107
,NC
NC
24
66
0026
108
"0027
25
NC
67
109
-NC
Vee
26
Vee
68
110
Vss
27
111
RFU
69
0028
28
70
0029
112
NC
~
29
RFU
113
RFU
71
0030
30
~
72
0031
114
NC
31
UElf
73
Vee
115
RFU
32
Vss
74
0032
116
Vss
A1
33
AO
75
0033
117
34
0034
118
A3
A2
76
35
A4
77
0035
119
AS
A7
36
A6
78
Vss
120
37
121
A9
A8
79
P01
P03
122
NC
38
NC/A1O'
80
39
NC
81
P05
123
NC
Vee
40
Vee
82
P07
124
41
RFU
100
125
RFU
63
80
42
RFU
84
Vee
126
'4 Meg x 72 version only
MARKINC
• Timing
60m3 access
" . 70ns access
• Components
-6
-7
Sal
D
DT
TSOP
• Packages
168-pin DIMM (gold)
• Access Cycle
.
FAST PAGE MODE
EDO PAGE MODE (4 Meg x 72 only)
• Refresh
Standard/16ms or 32rns
SELF REFRESH/128rns
G
Blank
X
wen-
Blank
S
KEY TIMING PARAMETERS
EDO option
SPEED
-6
-7
IRC
110ns
130n5
IRAC
60ns
70ns
IpC
25ns
30ns
IAA
35ns
40n5
teAC
20ns
25ns
ICAS
10ns
12ns
IRAC
60ns
70ns
IpC
35ns
40ns
IAA
35ns
40ns
ICAC
20ns
25ns
IRP
40ns
50ns
FPM option
SPEED
-6
-7
IRC
110ns
130ns
MT18LD(1)172(S), MT18LD(T)472(X)(S)
DM46.pm5-Rev.2195
5-109
PIN If SYMBOL
127
Vss
128
RFU
129
NC
130
NC
131
HlU
por
132
Ve,
133
134
NC
135
NC
136
0054
137
0055·
Vss
138
139
0056
140
0057
141
0058
142
0059
143
Vee
144
0060
145
RFU
146
RFU
147
RFU
148
RFU
149
0061
150
0062
0063 '
151
152
Vss
153
0064
154
0065
155
0066
156
0067
157
Vee
158
0068
159
0069
160
0070
161
0071
162
Vss
163
P02
164
P04
165
P06
166
P08
167
1D1
168
Vee
Micron Technology. Inc•• reserves tile right ID cllang'e products or specifIcations withOut'notlce.
©1995, Micl'QnoTechnoloQY.lnc.
•
C
:D
l>
s:
-3:
C
s:
PRELIMINARY
MI[:::I=ICN
1-·
,~" "
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
goes LOW prior to CAS going LOW, and the output pints)
remain open (High-Z) until the next CAS cycle.
VALID PART NUMBERS
•
C
:r:J
PART NUMBER
DESCRIPTION
MT18L0172G-xx
MT18L0172G-xx S
1 Meg x 72 EGG, FPM; SOJ
1 Meg x 72 EGG, FPM, SOJ, S'
MT18LDT172G-xx
MT18LOT172G-xx S
1 Meg x 72 EGG, FPM, TSOP
1 Meg x 72 EGG, FPM, TSOP, S'
MT18LDT472G-xx
MT18LOT472G-xx X
4 Meg x72 EGG, FPM, TSOP
MT18LOT472G-xx S
4 Meg x 72 EGG, FPM, TSOP, S'
MT18LOT472G-xx XS
4 Meg x 72 EGG, EOO, TSOP, S'
MT18L0472G-xx
MT18L0472G-xx X
4 Meg x 72 EGG, FPM, SOJ
4 Meg x 72 EGG, EOO, SOJ
MT18LD472G-xx S
4 Meg x 72 EGG, FPM, SOJ, S'
4 Meg x 72 EGG, EOO, SOJ, S'
MT18LD472G-xx XS
'S
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined
page boundary. The FAST PAGE MODE cycle is always
initiated with a row-address strobed-in by RAS followed by
a column-address strobed-in by CAS. CAS may be toggledin by holding RAS LOW and strobing-in different columnaddresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the FAST PAGE MODE operation.
4 Meg x 72 EGG, EOO, TSOP
EDO PAGE MODE - 4 Meg x 72 only
=SELF REFRESH
»
:s:: GENERAL DESCRIPTION
-:s::c
:s::
The MT18LD(T)172(S) and MT18LD(T)472(X)(S) are randomlyaccessed 8MB and 32MB solid-state memories organizedin a x72 configuration. They are specially processed to
operate from 3.0V to 3.6V fo~ low-voltage memory systems.
During READ or WRITE cycles,each bit is uniquely
addressed through the 20/22 address bits, which are entered 10/11 bits (AD /BO-AIO) at a time. Two copies of
address 0 (AD and BO) are defined to allow maximum
performance for 4-byte applications which interleave between two 4-byte banks. AD is common to the DRAMs used
for DQO-DQ35, while BO is common to the DRAMs used for
DQ36-DQ71. RAS is used to latch the first 10/11 bits and
CAS the latter 10/11 bits.
READ and WRITE cycles are selected With the WE input.
A logiC HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the faIling edge of WE or CAS,
whichever occurs last. EARLY WRITE occurs when WE
MT18LD(T)172(S), MT18lD(T)472(X)(S).,
0M48.pm5 - Rev. 2195
EDO PAGE MODE, designated by the "X" version, is an
accelerated FAST PAGE MODE cycle. The primary advantage of Eoo is the availability of data-out even after CAS
goes back HIGH. Eoo provides for CAS precharge time
(ICP) to occur without the output data going invalid. This
elimination of CAS output control provides for pipeline
READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS. EDO-PAGE-MODE DRAMs operate similar to FASTPAGE-MODE DRAMs, except data will remain valid or
become valid after CAS goes HIGH during READs, provided RAS and OE are held LOW. If OE is pulsed while
RAS and CAS are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If OE is toggled or
pulsed after CAS goes HIGH while RAS remains LOW,
data will transition to and remain High-Z.
If theDQ outputs are wire OR'd, OE must be used to
disable idle banks of DRAMs. Alternatively, pulsing WE to
the idle banks during CAS HIGH time will also High-Z the
outputs. Independent of OE control, the outputs will disable after IOFF, which is referenced from the rising edge of
RAS or CAS, whichever occurs last (reference the
MT4LC4M4E8(S) DRAM data sheet for additional information on Eoo functionality).
5-110
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995,MlcronTechnology,lnc.
PRELIMINARY
MICRON
1-·
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
"'"'0"'0""0
REFRESH
Returning RAS and CAS HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS HIGH time. Correct memory cell data is preserved
by maintaining power and executing any RAS cycle (READ,
WRITE) or RAS refresh cycle (RAS ONLY, CBR or HIDDEN) so that all combinations of RAS addresses (AO/BOA9 1AIO) are executed at least every tREF, regardless of
sequence. The CBR REFRESH cycle will invoke the internal
refresh counter for automatic RAS addressing.
An additional SELF REFRESH mode is also available.
The "S" version allows the user the option of a fully static
low power data retention mode, or a dynamic refresh mode
at the extended refresh period. The module's SELF REFRESH mode is initiated by executing a CBR REFRESH
cycle and holding RAS LOW for the specified tRASS. Addi-
tionally, the "S" version allows for extended refresh rates of
62.5l1s (32MB) and 12511s (8MB) per row if using distributed
CBR REFRESH. This refresh rate can be applied during
normal operation, as well as during a standby or extended
refresh mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for the time minimum of an operation cycle, typically
tRPS. This delay allows for the completion of any internal
refresh cycles that may be in process at the time of the
RAS LOW-to-HIGH transition. If the DRAM controller uses
a distributed CBR REFRESH sequence, a burst refresh is not
required upon exiting SELF REFRESH mode. However, if
the DRAM controller utilizes RAS ONLY or burst refresh
sequence, all 1,024/2,048 rows must be refreshed within
300l1s prior to the resumption of normal operation.
FUNCTIONAL BLOCK DIAGRAM
DOD - D03
tt tt
AD j [ j > - - - j A O OQ1 - 4
WE
WEo
~O>---jOE
RASO
DOS - oQ11
ttt t
AQ
t t t!
AO
D01·4
OQl-4
WE
U1
----jRAs
i5ASo
D04 - D07
OQ12 - 0015
0016 - OQ19
tt! t
AD
0024 - OQ27
!ttl
OQ1-4
AD
U'
U2
OE
OQ20 - 0023
DQ1·4
AQ
WE
WE
OE
U7
RAS
no"S---o''=~='"T-,CAS At-A1D
CASAl-Ala
tttt
AO D01-4
U6
RAS
DQ28 - 0031
OE
DQ1-4
0032 - ()()3ti
!t t t
AO OQ1·4
WE
U6
OE
U9
RAS
RAS
CASA1-A1D
CASA1-A1D
Ala,M-A1
OQ40 - OQ43
0044 - OQ47
OQ48 - 0051
OQ52 - OQ55
0056 - D059
0060 - 0063
DQ64 - 0067
0068 - OQ71
Utt
AO 001-4
WE
OE
U11
RAs2--.-I
Ms
CAS4
CASA1-Al0
1 Meg x 72 - MT18LD172G(S)
U1-U16", MT4LC4001J{S) FAST PAGE MODE
4 M.g x 72 - MT18LD(T)472G(S)
U1-U18 = MT4LC4M4B1(S) FAST PAGE MODE
• • • • PD1.PD8
POE
NOTE:
4 Meg x 72 - MT1SLD(T)472GX(S)
U1·U18 = MT4LC4M4E8(S) EDO PAGE MODE
_ _ _ _----'
1. All inputs with the exception of RAS are redriven.
2. D = line buffers.
MT18lD(T)172(S), MT18LD(T)472(X){S)
DM48.pm5 - Rev. 2/95
5-111
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
C
:D
:l=-
s::
-sC::
s::
PRELIMINARY
MICRON
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
m~"oco","
1-·
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
30,45
RASO, RAS2
Input
28,46
CASO,CAS4
Buffered Input
Row-Address Strobe: RAS is used to clock-in the 10/11
row-address bits. Two RAS inputs allow for one x72 bank
or two x36 banks.
Column-Address Strobe: CAS is used to clock-in the 10/11
column-address bits, enable the DRAM output buffers and
strobe the data inputs on WRITE cycles.
27,48
WEO,WE2
Buffered Input
II I
I LOVV, the access is a READ cycle, provided OE is aiso
LOW. If WE goes LOW after CAS goes LOW, then the
cycle is a LATE WRITE cycle. A LATE WRITE cycle is
generally used in conjunction with a READ cycle to form a
READ-MODIFY-WRITE cycle.
c
:IJ
l>
s:
-SC
Write Enable: WE is the READIWRITE control for the DO
pins. WED controls DOO-D035. WE2 controls D036D071. if WE is LOW prior to CAS going LOW, the access
is an EARLY WRITE cycle. If WE is HIGH while CAS is
31,44
OEO,OE2
Buffered Input
Output Enable: OE is the input/output control for the DO
pins. OED controls DOO-D035. OE2 controls D036-D071 .
These signals may be driven, allowing LATE WRITE
cycles.
33-38,117-121,126
AO-Ai0, BO
Buffered Input
Address Inputs: These inputs are multiplexed and clocked
by RAS and CAS. AD is common to the DRAMs used for
DOO-D035 while BO is common to the DRAMs used for
D036-D071
2-5,7-11,13-17,19-22,
52-53,55-58,60,65-67,
69-72,74-77,86-89,
91-95,97-101,103-106,
136-137,139-142,
144,149-151,153-156,
158-161
DOO-D071
Input/
Output
79-82, 163-166
PD1-PD8
Buffered
Output
29,41-42,47,61-64,111,
113,115,125,128,131,
145-148
RFU
-
6,18,26,40,49,59,73,
84,90,102,110,124,
133, 143, 157, 168
Vcc
Supply
S
MT18LO(T)172(S), MT18LD(T)472(X)(S)
DM48.pmS - Rev. 2195
Data I/O: For WRITE cycles, DOO-D071 act as inputs to
the addressed DRAM location. For READ access cycles,
DOO-D071 act as outputs for the addressed DRAM
location.
Presence-Detect: These pins are read by the host system
and tell the system the DIMM's personality. They will be
either driven to VOH (1) or they will be driven to VOL (0).
RFU: These pins should be left unconnected
(reserved for future use).
Power Supply: +3.3V ± 0.3V
5-112
Micron Techndogy, Inc., reserves the right to change products or specificauons without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
m~"o,""""
1-·
PIN DESCRIPTIONS (continued)
PIN NUMBERS
SYMBOL
TYPE
1,12,23,32,43,54,
68,78,85,96,107,116,
127, 138, 152, 162
Vss
Supply
Ground
83,167
100,101
Output
10 bits: 100 = DIMM type. 101 = Refresh Mode. These
pins will be either left floating (NC) or they will be
grounded (Vss).
132
POE
Input
24-25, 39, 50-51,
108-109,112,114,
122-123, 129, 130,
134-135,150,161
NC
DESCRIPTION
Presence-Detect Enable: POE is the READ control for the
buffered presence-detect pins.
-
No connect
III
c
::D
»
s:
TRUTH TABLE
m
'CAS"
Standby
H
READ
L
EARLY WRITE
L
L
L
READ WRITE
L
L
H---L
L
H---L
H
H
FUNCTION
EDO/FAST-PAGE-
1st Cycle
ADDRESSES
IR
IC
DATA-IN/OUT
WE
or
H---X
X
X
X
X
X
High-Z
L
H
L
X
ROW
COL
Data-Out
X
X
ROW
COL
Data-In
L---H
X
ROW
COL
Data-Out, Data-In
L
X
ROW
COL
Data-Out
L
X
n/a
COL
Data-Out
P1iE
DOO-71
MODE READ
2nd Cycle
L
H---L
EDO/FAST-PAGE-
1st Cycle
L
H-L
L
X
X
ROW
COL
Data-In
L
H-L
L
X
X
n/a
COL
Data-In
MODE EARLY-WRITE 2nd Cycle
EDO/FAST-PAGE-
1st Cycle
L
H-L
H-L
L-H
X
ROW
COL
Data-Out, Data-In
MODE READ-WRITE
2nd Cycle
L
H-L
H-L
L-H
X
nla
COL
Data-Out, Data-In
H
X
X
X
X
ROW
n/a
High-Z
H
L
X
ROW
COL
Data-Out
Data-In
RAS-ONLY REFRESH
HIDDEN
READ
L-H-L
L
REFRESH
WRITE
L-H-L
L
L
X
X
ROW
COL
CBR REFRESH
H-L
L
H
X
X
X
X
High-Z
SELF REFRESH (S version)
H-L
L
H
X
X
X
X
High-Z
X
X
X
X
L
X
X
Not Affected
READ PRESENCE-DETECTS
MT18LD(T}172(S), MT18LO(T)472(X)(S)
DM48.pm5 - Rev. 2/95
5-113
Micron Technology, Inc., reserves the right to change products or specifications wrthout notice,
@1995,MicronTechnology, Inc.
-s:c
:s:
PRELIMINARY
UII::::I=ICN
1-·
,,,"",coo,,",
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
PRESENCE-DETECT TRUTH TABLE
III
c
$!s:: . . . .
Page Mode
-sC:
Access Timing
s:
Refresh Control
Data Width, Parity
NOTE: Vss = ground; 0 = VOL; 1 =VOH.
* This addressing includes a redundant address to allow mixing of 12/10 and 11/11 DRAMs with the same presence-detect
setting. The MT18LD(T)472 uses 11/11 DRAMs.
MT18LD(T)172(S), MT18lD(T)472(X)(S)
DM48.pm5 - Rev. 2195
5-114
Micron Technology, Inc., reserves the right to change products or specifications withoul notice.
©1995, Micron Technology, Inc
PRELIMINARY
MICRON
1-·
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
m""",,,,,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc = +3.3V ±0.3V)
PARAMETER/CONDITION
SYM
MIN
MAX
UNITS
Supply Voltage
Vcc
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
111
-2
2
).lA
INPUT LEAKAGE CURRENT
Any input OV S VIN S 5.5V
(All other pins not under test = OV) for each package input
CASO, CAS4
AO-A 10, BO, PDE
WEO,2,OEO,2
RASO,RAS2
112
-18
18
~A
OUTPUT LEAKAGE CURRENT
(Q is disabled; OV S VOUT S 5.5V) for each package input
DQO-DQ71,
loz
-10
10
~A
VOH
2.4
NOTES
•
PD1~PD8
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
c
:a
V
VOL
0.4
V
l>
s:
MAX
PARAMETER/CONDITION
-6
-7
8MB
32MB
18
32
18
32
mA
28
Icc2
ALL
Icc2
8MB
(S only) 32MB
9
1.8
2.7
9
1.8
2.7
mA
28
8MB
1,440
1,260
mA
32MB
2,160
1,980
3,4,
28,32
8MB
1,080
900
mA
32MB
1,620
1,440
3,4,
28,32
Icc4
8MB
(X only)
32MB
mA
1,980
3,4,
28,32
mA
3,28
32
mA
3,5,
28
mA
3,5,
28,31
mA
5,28
SYMBOL SIZE
STANDBY CURRENT: (TTL)
(RAS = CAS = VI H)
ICCI
STANDBY CURRENT: (CMOS)
(RAS = CAS = Vcc -0.2V)
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC = IRC [MIN])
Icc3
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: tpc = tpc [MIN])
Icc4
OPERATING CURRENT: EDO PAGE MODE (X version only)
Average power supply current
(RAS = VIL,CAS, Address Cycling: tpc = tpc [MIN])
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC = tRC [MIN])
Iccs
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: tRC = tRC[MIN])
Icc6
REFRESH CURRENT: Extended (S version only)
Average power supply current; CAS '= 0.2V or CBR cycling; RAS=
tRAS (MIN); WE= Vcc -0.2V; AO/BO-Al0, OE and DIN = Vce -0.2V
or 0.2V (DIN may be left open); tRC:, 62.5~s (32MB)/125~s (8MB)
Icc?
(S only)
REFRESH CURRENT: SELF (S version only)
Average power supply current; CBR cycling with RAS :2: IRASS
(MIN) and CAS held LOW; WE =Vcc -0.2V; AO/BO-A10, OEand
DIN =Vcc -0.2V or 0.2V (DIN may be left opep)
Iccs
(S only)
MTI8LD(T}172(S), MTI8LD(T)472(X)(S)
DM48.pm5 - Rev. 2/95
5-115
-
-
UNITS NOTES
1,800
8MB
1,440
1,260
32MB
2,160
1,980
8MB
1,440
1,260
32MB
2,160
1,980
8MB
2.7
2.7
32MB
5.4
5.4
8MB
2.7
2.7
32MB
5.4
5.4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
-s:
C
:s:
PRELIMINARY
MIC:RON
1-·
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
"'''"''""'''''
'Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RA TINGS*
U
Voltage on Vee Pin Relative to Vss ................. -IV to +4.6V
Voltage on Inputs or I/O Pins
Relative to Vss .................................................... -1 V to +S.5V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -SSOC to +12S0C
Power Dissipation ........................................................... I8W
Short Circuit Output Current ..................................... SOmA
CAPACITANCE
•
C
::D
l>
s:
C
s::
s:
PARAMETER
MAX
UNITS
NOTES
Input Capacitance: AO-A10, BO, POE
SYMBOL
Cll
MIN
9
pF
2
input capacitance: WEO, WE2, OEO, OE2, CASO, CAS4
CI2
9
pF
2
Input Capacitance: RASO, RAS2
CI3
70
pF
2
Input/Output Capacitance: 000-0071
Cia
10
pF
2
Output Capacitance: P01-PD8
Co
9
pF
2
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vcc
=+3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MOOE OPTION
PARAMETER
SYM
Access time from column-address
tAA
Column-address hold time (referenced to RAS)
tAR
Column-address setup time
Row-address setup time
Column-address to WE delay time
tASC
tASR
tAWD
Access time from CAS
tCAC
Column-address hold time
tCAH
tCAS
CAS pulse width
RAS LOW to "don't care" during SELF REFRESH
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
tCHD
tCHR
tCLl
tcp
tCPA
tCRP
tCSH
CAS to WE delay time
tCSR
tCWD
Write command to CAS lead time
Data-in hold time
tCWL
tDH
Data-in hold time (referenced to RAS)
tDHR
tDS
Data-in setup time
Output disable
Output buffer turn-off delay
MTI8LD(T)172(S), MTI8LD(T)472(X)(S)
DM48.pm5 - Rev. 2/95
48
2
5
57
5-116
MIN
15
15
15
8
5
10
UNITS
NOTES
40
ns
25
24
23
25
23,30
15,25
25
10,000
15
58
12
42
15
15
45
-2
ns
ns
ns
25
20
20
15
8
5
10
40
20
ns
ns
ns
ns
15
68
12
47
20
20
55
-2
ns
ns
ns
ns
ns
ns
36
5,24
23,33
16
25
25
24
5,23
23,30
ns
20
20
18
5
ns
ns
ns
10,000
45
15
15
13
5
MAX
53
2
5
67
20
tOE
tOEH
tOFF
MAX
35
tOD
Output enable
OE hold time from WE during READ-MODIFY-WRITE cycle
-7
-6
MIN
ns
ns
25,29
ns
ns
24,29
ns
ns
25
ns
24
20,27,38
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology. Inc.
PRELIMINARY
MICRON
1-·
,,,"",co",",
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MOOE OPTION
PARAMETER
OE setup prior to RAS during HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
POE to valid presence-detect data
POE inactive to presence-detects inactive
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS
-6
SYM
MIN
tORD
tpc
tpD
0
35
tpDOFF
2
tpRWC
87
-7
MAX
MIN
MAX
0
40
10
10
2
97
UNITS
NOTES
ns
ns
20
ns
35
ns
34
ns
ns
23
14
RAS to column-address delay time
tRAC
tRAD
13
ns
18,26
Row-address hold time
tRAH
8
8
ns
24
Column-address to RAS lead time
tRAL
35
40
ns
25
RAS pulse width
RAS pulse width (FAST PAGE MODE)
tRAS
60
60
100
RAS pulse width during SELF REFRESH
Random READ or WRITE cycle time
RAS to CAS delay time
tRASP
tRASS
tRC
tRCD
Read command hold time (referenced to CAS)
tRCH
Read command setup time
Refresh period (2,048 cycles) - 4 Meg x 72
Refresh period (1,024 cycles) - 1 Meg x 72
tRCS
tREF
60
110
18
25
10,000
100,000
70
13
70
70
100
40
2
2
17,26
19,23
2
23
32
16
ns
ms
ms
128
ms
50
RAS to CAS precharge time
tRPC
0
RAS precharge time during SELF REFRESH
Read command hold time (referenced to RAS)
tRPS
tRRH
110
0
130
128
tRSH
tRWC
155
RAS to WE delay time
Write command to RAS lead time
tRWD
tRWL
tT
87
20
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT18LD(T)172(S), MT18LO(T)472(X)(S)
DM48.pm5 - Rev. 2195
twCH
tWCR
twcs
twp
tWRH
twRP
5-117
3
15
45
ns
ns
ns
ns
ns
0
25
185
97
25
50
36
ns
40
RAS hold time
W;
ns
ns
RAS precharge time
READ WRITE cycle time
ns
ns
2
18
32
16
0
20
10,000
100,000
130
tREF
tREF
tRP
Refresh period (1,024 or 2,048 cycles) S version
30
3
20
50
36
19
25
ns
25
ns
ns
23,30
ns
ns
25
25
43
53
ns
24
2
ns
23,30
10
2
15
8
12
8
12
ns
ns
ns
22,24
22,23
Micron Technology, Inc., reserves the right to change products or"speciflcations without notice.
©1995,MicronTechnology, Inc.
PRELIMINARY
MICRON
1-·
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
"'"'"""""
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+3.3V ±0.3V)
-6
AC CHARACTERISTICS - EDD PAGE MODE OPTION
PARAMETER
SYM
Access time from column-address
tAA
Column-address setup to CAS precharge during writes
tACH
tAR
Column-address hold time (referenced to RAS)
Column-address setup time
•
C
::tJ
»
s:
c
s:
s:
tASC
Row-address setup time
tASR
Column-address to WE delay time
tAWD
Access time from CAS
tCAC
Column-address hoid iirne
ICAH
CAS pulse width
RAS LOW to "don't care" during SELF REFRESH
tCAS
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
tCHD
tCHR
tCLZ
CAS" precharge time
tCOH
tcp
Access time from CAS precharge
tCPA
CAS to RAS precharge time
tCRP
CAS hold time
CAS setup time (CBR REFRESH)
tCSH
CAS to WE delay time
Write command to CAS lead time
tCWD
Data output hold after CAS LOW
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
tCSR
tCWL
tDH
tDHR
tDS
tOD
Output disable
Output enable
OE hold time from WE during READ-MODIFY-WRITE cycle
OE HIGH hold time from CAS HIGH
tOEHC
OE HIGH pulse width
tOEP
tOES
Output buffer turn-off delay
tOFF
OE setup prior to RAS during HIDDEN REFRESH cycle
tORD
tpc
PDE to valid presence-detect data
PDE inactive to presence-detects inactive
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (EDO PAGE MODE)
RAS pulse width during SELF REFRESH
tRAC
tRAD
tRAH
tRAL
tRAS
tRASP
Random READ or WRITE cycle time
tRASS
tRC
RAS to CAS delay time
tRCD
MT18LD[f)172(S), MT18LD{T)472(X){S)
DM48.pm5 -Rev. 2195
15
43
2
5
57
5-118
MIN
10,000
17
12
15
10
2
7
10
40
10
48
7
37
15
15
45
-2
0
8
10
10
5
5
0
25
UNITS
NOTES
40
ns
25
15
15
20
2
ns
ns
ns
ns
ns
25
ns
ns
10,000
ns
ns
ns
ns
ns
ns
45
10
53
7
42
15
17
55
-2
0
10
10
10
5
5
0
30
10
60
25
ns
ns
ns
10,000
125,000
40
24
23
25
23,30
15,25
~
36
5,24
23
23
16
25,37
25
24
5,23
23,30
ns
15
15
ns
25,29
ns
ns
24,29
ns
ns
ns
24
ns
ns
ns
20
ns
ns
20,27,38
20
ns
10
10
8
40
70
70
100
130
12
ns
ns
2
87
77
10
8
35
60
60
100
110
12
MAX
15
53
2
5
67
20
15
10
15
8
2
7
10
tpD
tpDOFF
tpRWC
-7
MAX
35
tOE
tOEH
OE LOW to CAS HIGH setup time
EDO-PAGE-MODE READ or WRITE cycle time
MIN
ns
ns
ns
70
30
ns
ns
ns
ns
10,000
125,000
35
34
23
14
18,26
24
25
ns
ns
!lS
36
ns
45
ns
17,26
Micron Technology. Inc., reserves the right to change products or specifications without nollce.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
",,,61,,,,,,
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee = +3.3V ±0.3V)
-6
-7
AC CHARACTERISTICS - EDD PAGE MODE OPTION
PARAMETER
SYM
MIN
UNITS
NOTES
Read command hold time (referenced to CAS)
tRCH
2
2
ns
19,23
Read command setup time
tRCS
2
2
ns
23
Refresh period (2,048 cycles) - 4 Meg x 72
Refresh period (2,048 cycles) S version
tREF
tREF
RAS precharge time
RAS to CAS precharge time
128
ms
ms
50
0
110
0
130
0
0
17
ns
19
ns
25
182
ns
ns
ns
25
23,30
tRSH
READ WRITE cycle time
RAS to WE delay time
tRWC
tRWD
tRWL
tT
15
155
82
Write command hold time
Write command hold time (referenced to RAS)
tWCH
tWCR
WE command setup time
Output disable delay from WE (CAS HIGH)
Write command pulse width
twcs
tWHZ
twp
10
ns
50
2
50
36
25
ns
17
ns
25
43
53
2
ns
ns
24
2
ns
ns
27
2
WE pulse width for output disable when CAS HIGH
twpz
10
WE hold time (CBR REFRESH)
tWRH
8
WE setup time (CBR REFRESH)
WRP
12
5-119
ns
ns
92
20
20
2
15
MT18LD(T)172(S), MT18LD(T)472(X)(S)
DM48.pmS - Rev. 2/95
32
128
tRPC
RAS hold time
Write command to RAS lead time
32
MAX
40
tRPS
tRRH
Transition time (rise or fall)
MIN
tRP
Read command hold time (referenced to RAS)
RAS precharge time during SELF REFRESH
MAX
18
2
12
12
8
12
20
ns
ns
ns
23
-.--
22.24
22,23
Micron Technology, Inc., reserves the right 10 change products or specifications without nollce.
©1995, Micron Technology, Inc.
•
C
::rJ
»
S
-c3:
3:
PRELIMINARY
MICRON
1-·
","",w", ,,
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
NOTES
•
o
J:I
l>
s:
-So
s:
1. All voltages referenced to Vss.
2. This parameter is sampled. Vee = +3.3V ±O.3V;
f=IMHz.
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading. Specified values
are obtained with minimum cycle time and the
outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of JOOlls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before pr~per device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
S. AC characteristics assume tT = Sns for FPM and 2.5ns
for EDO.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
andVIH).
10. In addition to meeting the transition rate specification,
all input signals must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and JOOpF.
14. Assumes thatlRCD < IRCD (MAX). IflRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. IRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by ICAe.
IS. Operation within the lRAD (MAX) limit ensures that
lRAC (MIN) and ICAC (MIN) can be met. lRAD
(MAX) is specified as a reference point only; if IRAD is
greater than the specified lRAD (MAX) limit, access
time is controlled exclusively by IAA.
MT18LD(T)172(S), MT18LO(T)472(X)(S)
DM48.pm5 - Rev. 2/95
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE = LOW and
OE=HIGH.
22. IWTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverse of twRP and IWRH in the
CBR REFRESH cycle.
23. A +2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
24. A -2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
25. A +Sns timing skew from the DRAM to the module
resulted from the addition of line drivers.
26. A -2ns (MIN) and a -Sns (MAX) timing skew from the
DRAM to the module resulted from the addition of
line drivers.
27. A +2ns (MIN) and a +Sns (MAX) timing skew from
the DRAM to the module resulted from the addition
of line drivers.
2S. The maximum current ratings are based with the
memory operating or being refreshed in the x72 mode.
The stated maximums may be reduced by approximately one-half when used in the x36 mode.
29. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
30. twcs, IRWD, IAWD and ICWD are not restrictive
operating parameters. IWCS applies to EARLY WRITE
cycles. IRWD, IAWD and ICWD apply to READMODIFY-WRITE cycles. IftWCS ~ twcs (MIN), the
cycle is an EARLY WRITE cycle and the data output
will remain an open circuit throughout the entire
cycle. IfIRWD~IRWD (MIN), IAWD~IAWD (MIN)
and ICWD ~ tCWD (MIN), the cycle is a READMODIFY-WRITE and the data output will contain
data read from the selected cell. If neither of the above
conditions is met, the state of data-out is indeterminate. OE held HIGH and WE taken LOW after CAS
goes LOW results in a LATE WRITE (OE-controlled)
cycle. twcs, tRWD, ICWD and IAWD are not
applicable in a LATE WRITE cycle.
5-120
Micron Tachnology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MIC::RON
1-·
'''"'C"'"''"'
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
NOTES (continued)
31. Refresh current increases if tRAS is extended beyond
its minimum specification.
32. Column-address changed once each cycle.
33. The 3ns minimum parameter guaranteed by design.
34. tpDOFF MAX is determined by the pull-up resistor
value. Care must be taken to ensure adequate
recovery time prior to reading valid up-level on
subsequent DIMM position.
35. Measured with the specified current load and 100pf.
36. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
37. tCAC (MIN), tCPA (MIN) and tAA (MIN) are for
reference only to help aid the user as to when to
expect the earliest data to be accessed. Only tCAC
(MAX), tCPA (MAX) and tAA (MAX) are guaranteed.
38. For FAST PAGE MODE option, tOFF is determined
by the first RAS or CAS signal to transition HIGH. In
comparison, toFF on an EDO option is determined by
the latter of the RAS and CAS signal to transition
HIGH.
39. Applies to both EDO and FAST PAGE MODEs.
•
C
JJ
»
s:
-c3:
3:
MT18LD(l)172(S), MT18LD(T)472(X)(S)
DM48.pm5 - Rev. 2195
5-121
Micron Technology, Inc., reserves the right to change products or specifications without notice,
©1995, Micron Technology; Inc.
PRELIMINARY
UII:::RCN
F·
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
,,,<"ow",'"'
READ CYCLE 39
'RC
'RP
'RAS
RAs
V,H
Vil
ICSH
'I. ~I
Y
'ASH
tRCD
'CRP
CAS
V,H
Vil
=.-1
'AR
tRAD
•
ADDR
ViH
Vil
I~ ~I
ROW
~
~
ItWAPp-I~1
'CAS
~I
I
,I
1
ROW
COLUMN
'RCS
I
l~l
!
~'~'
C
tRAL
~I
Vlllih
lAse ...1
::D
NOTE 2
»
~
S
DQ
~g~ -:-------OPEN-----~mpVA~Llo~oA~TAQ--OPEN-1
-
C
OE
I.
'OE
~:r =.7T~/;TTT0"/;TT70"/;7nI/;TT>1
#;=1//;=0"/;TTT0"/;7770"/;7TI1/;=W/;TTTW/;TTT0'j;TT7t'#;7TIj/;"'1//;=W/;TTT7W,0!
S
S
too
//;7'-1/j;=1//;'77:/
#;=1//;TTT1//;TTT/#;7771/j;7n/;j777/
/ /;7771//;7771//;777/;j
EARLY WRITE CYCLE 39
RC
tRAS
'RP
fr l
\
tCSH
J~
tRCD
'AR
I
tRAD
ADDR
~lr
I
tRAL
1
I~I I~IIACH I
I~ ~I
ROW
COLUMN
;:/./';,}t
~.Ji
~
ROW
tCWL
I
I
~W!ll
~ ~
M
,,,mw)'_'1
I
~I
I
I
'RWL
'WCR
!! ,_
_'08_1 I_'DH_I
OQ~:g~_~
~d%!iY,w'~
I~
'WP
VALID DATA
~
t:ZJ DON'T CARE
~
NOTE:
UNDEFINED
1, Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and WRH, This design implementation will facilitate compatibility with
future EDO DRAMs,
2, tOFF is referenced from rising edge of RAS or CAS, which ever occurs last.
MT18LD(TJ172(S), MT18LO(T)472(X)(S)
DM48.pmS - Rev. 2195
5-122
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
"'"""""""
FAST-PAGE-MODE READ CYCLE
V,H
-
~:~
-
RAS VIL -
~
CAs
ADDR
W$/#/!;W[
II
I
I
'AA
tRAC
I
-
'CAC
1:-
tClZ-
I
I.
I
'CLZ-
VALID
DATA
OPEN
r- -
'CPA
II
'CLZ-
•
'AA
C
lJ
'CPA
1:- -
I-~
'CAC
~ ~
~:t 4///;/;@$$//af/////$;I//mi
EDO-PAGE~MODE
I·
'OFF
VALID
DATA
~ ~
OE
'AA
I-~
'CAC
'OFF
~
VALID
DATA
---'OFF
r---
OPEN - -
~
-s:c
READ CYCLE
--------------------------~'~RA~SP~--~------------~-------I~
RAS
V,H
VIL
tCSH
~
CAS
ADDR
WE
V,H
V,L
-
,~:~
=:
-
~~II~~U~I
~:t ~
NOTE 1
I
I.
Wl7J I~.____-+-;'''''AA'-:--I
'RAC
DE
NOTE:
~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRPand tWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MTI8lD(T)172(S), MTI8LD(T)472(X}(S)
DM4B.pmS - Rev. 2195
5-123
»
S
Micron Technology, Inc., reserves the right to change products or specifications without notice,
©1995, Micron Technology, Inc.
s:
PRELIMINARY
UU::F=lCN
1-·
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
"'"""00""
FAST-PAGE-MODE EARLY-WRITE CYCLE
IpC
'cSH
IRSH
~ 1_ _ _---""Rc=D_-1_'=cAs"--_II_-"'cP'--_II_-"'cA=s- I 1---,,'CP'--_11_-,,'cA=8_ I
•
ADDR
~:~
DE
~:~
RDW
C
:rJ
l>
s:
-s:
C
:!##I;I//I//I//I/////////$$//I/////##//I/1///I///I/$/$/$M1//$//$I;I#$/I/ff$//$////I/1//#$/I/a
EDO-PAGE-MODE EARLY-WRITE CYCLE
s:
ADDR
~:t
I~
VAUDDATA
DE
~:~
VALID DATA
!/$//////////1////////!1111!//!//////////ffi///////!$//;@////////////////#$//!///#/$I;1///#/I;1$//////$/m
rzl
DON'T CARE
~
NOTE:
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for 'WRP and 'WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT18LD(T)172(S), MT18lD(T)472(X)(S)
DM48.pmS - Rev. 2195
5-124
Micron Technology, Inc., reserves the righllo change products or spectfications without notice
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
""'"0''"''''
READ WRITE CYCLE 39
(LATE WRITE and READ-MODfFY-WRITE cycles)
tCSH
_~__~____"_CD__~}~i~~_S:_____
I
I
tRAL
I
•
C
I
tCLZ-
:D
tCAC
1-
EDO/FAST PAGE MODE-PAGE-MODE READ-WRITE CYCLE 39
(LATE WRITE and READ-MODIFY-WRITE cycles)
NOTE:
DO
~:g~
DE
~:~
a-
=:-----
_'OD ___'o~E-~'oD
'D'-I --J-'OD
~___'o~E- - .~
I~~
!$$'ffJffffffi'ff@ffffffffi'ffU
~
~
DON'TeARE
~
UNDEFINED
1. IpC is for LATE WRITE cycles only.
2. Althoi.Jgh WE is a "don't care"at HAS time during an access cycle (READ or WRITE), the system designer
should implementWE HIGH for IWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT18LO(T)172(S), MT1BLO(n472{X)(S)
DM48.pm5 -' Rev. 2195
5-125
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
»
s:
-s:c
s:
PRELIMINARY
UII::::I=ICN
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG X 72 DRAM MODULES
"'~'wco,,'"
I-a
RAS-ONL Y REFRESH CYCLE 39
(WE = DON'T CARE)
'RC
l~
"1_
:: :::_d_+__'C_RP_'- :-:~I _-'===================~_·~_.'R_pc·-+b_--r_--:·~-: '----
•
ADDR
~:~
'ASR
•
'RAS
'RP
II
• 'RAH
--'kwzw##//aJ//;WI#aJ//////#/M~-'---RO-W- -
=_C----'RO-'-W
c
::c
»
s:
-s:c
s:
EDO-PAGE-MODE READ-EARL Y-WRITE CYCLE
(Pseudo READ-MODiFY-WRiTE)
tRASP
tCSH
'PC
~ I_ _--'-"RC""D_-+-_I~
'PC
tcp
~
1_ _'_cP_ _ 11_'-,-CA-,,-S_ _
'CP
ADDR
I~
DO
~:gr------ OPEN ----1'-----~VA~LlD'..":DA~TA~(AIi...)_-.J'----"!O.=~
'OE
OE
NOTE:
~:~= W/##//$//$///##/#//#a~
DON'T CARE
~
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for tWRP and WRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
MT18LD(T)172(S), MT18lD(T)472(X)(S)
DM48.pm5- Rev. 2195
5-126
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
",",cco",,,
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY -WRITE)
C
J]
l>
l5:
-Cl5:
~I
Q
DE
~gt-
~IUY
1\1\.
l5:
NOTE.
OPEN
VALID
I.
'lOf ~
tAA
OPEN--
.
I
~:~ =WlA?LL.L£.L-A---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
tRAC
~
DON'T CARE
IQQij UNDEFINED
NOTE:
1. Do not drive data prior to tristate.
MT18lD(T)172(S), MT18l0(T)472(X)(S)
DM48.pmS - Rev. 2/95
5-127
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
I"IU::I=ICN
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
"'«MOO'"'
CBR REFRESH CYCLE 39
(Addresses, OE = DON'T CARE)
.
.
,
=:):''': f-""-.
.
RP
~ "eo~
-
tCHR
~:~_
CAS
DQ
c
:c
RAS
II .
tWRP
WE
II
'1'
1
RP
.
,
~~~
~CHR
RAS
.-1
'k
OPEN---;-;"---------
!WRH
lWRP
II
lWRH
~:~ -WI//!IU&)-- --W§§I//!I§/#Iu;)-- ---'V§I//!//!I/I!I/IIII//§I§$~
s»
SELF REFRESH CYCLE 39
(Addresses and OE = DON'T CARE)
c
-
S
S
NOTE:
~
DON'T CARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT18LD(T)172(S), MT18LD(T}472(X)(S)
DM48.pm5- Rev. 2/95
5-128
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MII::I=ICN
1-·
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
,",",owon,
HIDDEN REFRESH CYCLE21,39
(WE = HIGH; OE = LOW)
(READ)
RAS
~:r-
J'
(REFRESH)
tRAS
tRAS
1~lf====t=Rc;;::D=====-------;--
CAS
•
ADDR
c
:c
DQ
tOE
OE
too
~:r !!$;I$/$!!##$#$/!;0Wd~
JWV///#$!;;
PRESENCE-DETECT READ CYCLE 39
PDt-PD8
VALID PRESENCE-DETECT
fZ:] DON'T CARE
~ UNDEFINED
NOTE:
1. PD pins must be pulled HIGH at next level of assembly.
MT18LO{T)172(S), MTI8LD(T)472(X)(S)
DM48.pmS - Rev. 2195
5-129
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
»
s:
-s:c
s:
PRELIMINARY
MIC::RON
MT18LD(T)172(S), MT18LD(T)472(X)(S)
1 MEG, 4 MEG x 72 DRAM MODULES
m~'
s:
-SC
S
PART NUMBER
DESCRIPTION
MT9LDT272G-xx
2 Meg x 72, FPM, TSOP
MT9LDT272G-xx S
2 Meg x 72, FPM, S*, TSOP
MT9LDT272G-xx X
MT9LDT272G-xx XS
2 Meg x 72, EDO, TSOP
2 Meg x 72, EDO, S*, TSOP
MT9LD272G-xx
MT9LD272G-xx S
2 Meg x 72, FPM, S*, SOJ
2 Meg x 72, FPM, SOJ
MT9LD272G-xx X
2 Meg x 72, EDO, SOJ
MT9LD272G-xx XS
2 Meg x 72, EDO, S*, SOJ
*8 = SELF REFRESH
GENERAL DESCRIPTION
The MT9LD(T)272(X)(S) is a randomly accessed solidstate memory containing 2,097,152 words respectively organized in a x72 configuration. It is specially processed to
operate from 3.0V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 21 address bits. The address is
entered first by RAS latching 11 bits and then CAS latching
10 bits. Two copies of address 0 (AO and BO) are defined to
allow maximum performance for 4-byte applications which
interleave between two 4-byte banks. AO is common to the
DRAMs used for DQO-DQ35, while BO is common to the
DRAMs used for DQ36-DQ71.
READ and WRITE cycles are selected with the WE input.
A logic HIGH on WE dictates READ mode while a logic
LOW on WE dictates WRITE mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS,
whichever occurs last. EARLY WRITE occurs when WE
goes LOW prior to CAS going LOW, and the output pines)
remain open (High-Z) until the next CAS cycle.
MT9LD(T)272(X)(S)
DM33 - Rev. 2/95
' MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
","",w,,,,,
FAST PAGE MODE
FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined
page boundary. The FAST PAGE MODE cycle is always
initiated with a row-address strobed -in by RAS followed by
a column-address strobed-in by CAS. CAS may be toggledin by holding RAS LOW and strobing-in different columnaddresses, thus executing faster memory cycles. Returning
RAS HIGH terminates the FAST PAGE MODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the "X" version, is an
accelerated FAST PAGE MODE cycle. The primary advantage of EDO is the availability ofdata-out even after CAS
goes back HIGH. EDO provides for CAS precharge time
(ICP) to occur without the output data going invalid. This
elimination of CAS output control provides for pipeline
READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS: EDO-PAGE-MODE DRAMs operate similar to FASTPAGE-MODE DRAMs, except data will remain valid or
become valid after CAS goes HIGH during READs, provided RAS and OE are held LOW. If OE is pulsed while
RAS and CAS are LOW, data will toggle from valid data to
High-Z and back to the same valid data. If OE is toggled or
pulsed after CAS goes HIGH while RAS remains LOW,
data will transition to and remain High-Z.
If the DQ outputs are wire OR'd, OE must be used to
disable idle banks of DRAMs. Alternatively, pulsing WE to
the idle banks during CAS HIGH time will also High-Z the
outputs. Independent of OE control, the outputs will disable after IOFF, which is referenced from the rising edge of
RAS or CAS, whichever occurs last (reference the
MT4LC2M8E7(S) DRAM data sheet for additional information on EDO functionality).
5-132
Micron Technology, Inc, reser\les the right to change products or specifications without notice
©1995,MicronTechnology, Inc,
ADVANCE
MIC:RON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
"'""'00""'
REFRESH
Returning RAS and CAS HIGH terminates a memory
cycle, and decreases chip current to a reduced standby
level. Also, the chip is preconditioned for the next cycle
during the RAS HIGH time. Correct memory cell data is
preserved by maintaining power and executing any RAS
cycle (READ, WRITE) or RAS refresh cycle (RAS ONLY,
CBR or HIDDEN) so that all 2,048 combinations of RAS
addresses (AO-AlO) are executed at least every 32ms (128ms
"S" version), regardless of sequence. The CBR REFRESH
cycle will invoke the internal refresh counter for automatic
RAS addressing.
An additional SELF REFRESH mode is also available.
The "5" version allows the user the choice of a fully static,
low-power, data-retention mode, or a dynamic refresh
mode at the extended refresh period of l28ms, four times
longer than the standard 32ms specifications. The module's
SELF REFRESH mode is initiated by performing a CBR
REFRESH cycle and holding RAS LOW for the specified
tRASS. Additionally, the "S" version allows for an extended
refresh rate of 62.5~s per row if using distributed CBR
refresh. This refresh rate can be applied during normal
operation, as well as during a standby or extended refresh
mode.
The SELF REFRESH mode is terminated by driving RAS
HIGH for the time minimum of an operation cycle, typically
lRrs. This delay allows for the completion of any internal
refresh cycles that may be in process at the time of the
RAS LOW-to-HIGH transition. If the DRAM controller uses
a distributed CBR REFRESH sequence, a burst refresh is not
required upon exiting SELF REFRESH mode. However, if
the DRAM controller utilizes RAS ONLY or burst refresh
sequence, all 2,048 rows must be refreshed within 300~s
prior to the resumption of normal operation.
tiltilt!
IT""
"I>'
I>'
D01 "8
AO
WE
I>'
tttttt!!
D01-8
AO
WE
CAs
...
DE
OE
At AlO
CAS
DOt ·8
At A10
OQ32 - DQ39
ttltltll
AO
DOt -8
WE
U4
RAs
RAS
... ...
ltltltlt
AO
WE
U3
RAS
~l,...Al~
8
WE
OE
..
DOl
U'
OE
0024'· 0031
OQ16'· DQ23
tttilttt
AO
U'
RAS
""
D08 - OQ15
OF
U5
hAS
~l-Al~
I:A:;
At A1U
Al
""
Ata-A1
am
[9}
"
DQ40 -OQ47
DQ48 ·DQ55
OQ56'· 0063
ttllltll
lltlttlt
ttltt!!l
M
"""
,,"
I>'
""
17
001-8
WE
AO
DOl-8
AO
WE
U6
Dot
8
OQ64 - DQ71
llllllll
AO
U7
US
OE
OE
OE
DE
RAS
RAS
RAS
RAS
CAs
..
Al-Al0
""
~l-Al~
...
CAS
DOl-8
WE
WE
At A10
...
U9
~l-Al~
""
2 Meg x 72 - MT9LDT272G(S)
U1-U9 = MT4LC2M8B1(S) FAST PAGE MODE
• • • • PD1-PD8
2 Meg x 72 - MT9LD(T)272G X(S)
U1-U9 = MT4LC2M8E7(S) EDO PAGE MODE
POE - - - - - - '
NOTE:
MT9LD{T)272(X)(S)
DM33-Rev.2/95
1. All inputs with the exception of RAS are redriven.
2. D =line buffers.
5-133
m
:e
•
c
::D
l>
3:
FUNCTIONAL BLOCK DIAGRAM
DOO'-DQ7
z
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MlcronTechnology, Inc.
-cs:
s:
ADVANCE
MICRON
1-·
2 MEG
",",me"""
X
MT9LD(T)272(X)(S)
72 DRAM MODULE
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
30,45
RASO,RAS2
Input
Row-Address Strobe: RAS is used to clock-in the 11 rowaddress bits. Two RAS inputs allow for one x72 bank or
two x36 banks.
28,46
CASO, CAS4
Buffered Input
Column-Address Strobe: CAS is used to clock-in the 10
column-address bits, enable the DRAM output buffers and
strobe the data inputs on WRITE cycles.
27,48
WEO, WE2
Buffered Input
Write Enable: WE is the READIWRITE control for the DO
pins. WEO controls 000-0035. WE2 controls 00360071. If WE is LOW prior to CAS going LOW, the access
is an EARLY WRITE cycle. If WE is HIGH while CAS is
LOW, the access is a READ cycle, provided OE is also
LOW. If WE goes LOW after CAS goes LOW, then the
cycle is a LATE WRITE cycle. A LATE WRITE cycle is
generally used in conjunction with a READ cycle to form a
READ-MODIFY-WRITE cycle.
31,44
OEO,OE2
Buffered Input
Output Enable: OE is the input/output control for the DO
pins. OEO controls 000-0035. OE2 controls 00360071. These signals may be driven, allowing LATE
WRITE cycles.
33-38,117-121,126
AO-AlO, BO
Buffered Input
Address Inputs: These inputs are multiplexed and clocked
by RAS and CAS. AO is common to the DRAMs used for
000-0035, while BO is common to the DRAMs used for
0036-0071.
2-5,7-11,13-17,19-22,
52-53,55-58,60,65-67,
69-72,74-77,86-89,
91-95,97-101,103-106,
136-137,139-142,144,
149-151,153-156,
158-161
000-0071
Input/
Output
79-82, 163-166
PD1-PD8
Buffered
Output
29,41-42,47,61-64,
111,113,115,125,
128,131,145-148
RFU
6,18,26,40,49,59,73,
84,90,102,110,124,
133, 143, 157, 168
Vcc
z
m
=E
•
I
I
I
C
::D
»
s:
-cs:
s:
MT9LD(T)272(X)(S)
DM33-Rey.2195
-
Supply
Data 1/0: For WRITE cycles, 000-0071 act as inputs to
the addressed DRAM location. For READ access cycles,
000-0071 act as outputs for the addressed DRAM
location.
Presence-Detect: These pins are read by the host system
and tell the system the DIMM's personality. They will be
either driven to VOH (1) or they will be driven to VOL (0).
RFU: These pins should be left unconnected
(reserved for future use).
Power Supply: +3.3V ± 0.3V
5-134
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MIC:RON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
,,,,,"ceo,,,,,
PIN DESCRIPTIONS (continued)
PIN NUMBERS
SYMBOL
TYPE
1,12,23,32,43,54,
68,78,85,96,107,116,
127,138,152,162
Vss
Supply
Ground
DESCRIPTION
83,167
IDO,IDI
Output
ID bits: IDO = DIMM type. ID1 = Refresh Mode. These
pins will be either left floating (NC) or they will be
grounded (Vss).
z
132
PDE
Input
24-25, 39, 50-51,
108-109,112,114,
122-123,129,130,
134-135,150,161
NC
Presence Detect-Enable: PDE is the READ control for the
buffered presence-detect pins.
No connect
:e
-
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•
c
lJ
»
s:
TRUTH TABLE
~
FUNCTION
m
WE
lIE
PIJE
ADDRESSES
IR
IC
DATA-IN/OUT
DOO-71
Standby
H
H~X
X
X
X
X
X
High-Z
READ
L
L
H
L
X
ROW
COL
Data-Out
EARLY WRITE
L
L
L
X
X
ROW
COL
Data-In
READ WRITE
L
L
H~L
L~H
X
ROW
COL
Data-Out, Data-In
EDO/FAST-PAGE-
1st Cycle
L
H~L
H
L
X
ROW
COL
Data-Out
MODE READ
2nd Cycle
L
H~L
H
L
X
n/a
COL
Data-Out
EDO/FAST-PAGE-
1st Cycle
L
H~L
L
X
X
ROW
COL
Data-In
MODE EARLY-WRITE 2nd Cycle
L
H~L
L
X
X
n/a
COL
Data-In
EDO/FAST-PAGE-
L
H~L
H~L
L~H
X
ROW
COL
Data-Out, Data-In
L
H~L
H~L
L~H
X
n/a
COL
Data-Out, Data-In
High-Z
1st Cycle
MODE READ-WRITE 2nd Cycle
RAS-ONLY REFRESH
H
X
X
X
X
ROW
n/a
HIDDEN
READ
L~H~L
L
H
L
X
ROW
COL
Data-Out
REFRESH
WRITE
L~H~L
L
L
X
X
ROW
COL
Data-In
CBR REFRESH
H~L
L
H
X
X
X
X
High-Z
SELF REFRESH (S version)
H~L
L
H
X
X
X
X
High-Z
X
X
X
X
L
X
X
Not Affected
READ PRESENCE-DETECTS
MT9LD(T)272(X)(S)
DM33-Rev.2195
5-135
Micron Technology. Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology,lnc.
-c3:
3:
ADVANCE
MICRON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
""",w"""
PRESENCE-DETECT TRUTH TABLE
z
m
=E
II
C
::c
»
s:
-s:C
Access Timing
s: r-------------------Refresh Control
Data Width, Parity
=
=
=
NOTE: Vss ground; 0 VOL; 1 VOH.
* This addressing includes a redundant address to allow mixing of 12/10 and 11/11 DRAMs with the same presencedetect setting.
MT9LD(T)272(X)(S)
DM33 - Rev. V95
5-136
Micron Technology, Inc., reserves the nght to change products orspecificatioos without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
'''""'''''"'
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee Pin Relative to Vss ................. -IV to +4.5V
Voltage on Inputs or I/O Pins
Relative to Vss .................................................... -IV to +5.5V
Operating Temperature, TA (ambient) .......... O°C to +70°C
Storage Temperature (plastic) .................... -55°C to +125°C
Power Dissipation ............................................................. 9W
Short Circuit Output Current ..................................... 50mA
*Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
z
m
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vee
=+3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vee
3.0
3.6
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
5.5V
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
CASO, CAS4
AO-A10, BO
WEO,2,OEO~2
1i1
-2
2
~
RASO,RAS2
1i2
-10
10
~A
DOO-D071
loz
-10
10
~
VOH
2.4
INPUT LEAKAGE CURRENT
Any input OV :0; VIN :0; 5.5V
(All other pins not under test = OV) for each package input
OUTPUT LEAKAGE CURRENT
(0 is disabled; OV :0; VOUT :0; 5.5V) for each package input
OUTPUT LEVELS
Output High Voltage (lOUT = -2mA)
Output Low Voltage (lOUT = 2mA)
MT9lD(T)272(X)(S)
DM33-Rev.2/95
VOL
5-137
NOTES
V
0.4
V
Micron Technology, Inc, reserves the right to change products or speCifications without notice.
©1995,MicronTechnology, Inc.
•
==
c
:c
l>
s:
-:s:C
:s:
ADVANCE
UII::::F=lCN
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
","",CO"""
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (Vcc
=+3.3V :!;0.3V)
MAX
SYMBOL
SIZE
-6
-7
Icc1
16MB
18
18
mA
28
ICC2
Icc2
(S only)
16MB
16MB
4.5
1.3
4.5
1.3
mA
mA
28
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cyciing: IRC =IRC [MIN])
Icc3
16MB
1,170
1,080
mA
3,4,
28, 32
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC =IpC [MIN])
ICC4
16MB
810
720
mA
3,4,
28,32
Iccs
16MB
(X only)
1,080
990
mA
3,4,
28,32
PARAMETER/CONDITION
STANDBY CURRENT: (TTL)
(RAS =CAS = VIH)
z
m
=E
•
C
::D
l>
S
STANDBY CURRENT: (CMOS)
(RAS =CAS = Vcc -0.2V)
OPERATING CURRENT: EDO PAGE MODE (X version only)
Average power supply current
(RAS =VIL, CAS, Address Cycling: IpC = tpc [MIND
UNITS NOTES
C
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: tRC =IRC [MIND
ICC6
16MB
1,170
1,080
mA
3,28,
32
S
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC
Icc7
16MB
1,170
1,080
mA
3,5,
28
Iccs
(S only)
16MB
2.7
2.7
mA
3,5,
28, 31
16MB
2.7
2.7
mA
5,28
-S
=tRC [MIN])
REFRESH CURRENT: Extended CBR (S version only)
Average power supply current
CAS =0.2V or CBR cycling; RAS =tRAS (MIN);
WE = Vcc -0.2V; AO-A 10, OE and DIN =Vcc -0.2V or 0.2V (DIN
may be left open); IRC = 62.5~s (2,048 rows at 62.5~s = 128ms)
REFRESH CURRENT: SELF (S version only)
Average power supply current during SELF REFRESH; CBR cycling
ICC9
(S only)
with RAS ~ tRASS (MIN) and CAS held LOW; WE =Vcc -0.2V;
AO-AlO, OE and DIN =Vcc -0.2V or 0.2V (DIN may be left open)
MT9LD(T)272{X)(S)
DM33 - Rev. 2195
5-138
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995,MicronTechnology, Inc
ADVANCE
MICRON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
,CO""",""",
CAPACITANCE
SYMBOL
PARAMETER
MIN
MAX
UNITS
Input Capacitance: AO-A 10, 80
Cit
9
pF
NOTES
2
Input Capacitance: WEO, WE2, OEO, OE2
CI2
9
pF
2
Input Capacitance: RASO, RAS2
CI3
40
pF
2
Input Capacitance: CASO, CAS4
CI4
9
pF
2
Input/Output Capacitance: 000-0071
Cia
10
pF
2
Output Capacitance: P01-P08
Co
10
pF
2
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vcc = +3.3V ±0.3V)
-6
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
SYM
Access time from column-address
Column-address hold time (referenced to RAS)
tAA
tAR
Column-address setup time
Row-address setup time
Column-address to WE delay time
Access time from CAS
Column-address hold time
CAS pulse width
RAS LOW to "don't care" during SELF REFRESH
CAS hold time (CBR REFRESH)
CAS to output in Low-Z
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
CAS to WE delay time
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output disable
Output enable
OE hold time from WE during READ-MODIFY-WRITE cycle
MT9lD(T)272(X)(S)
DM33 - Rev. 2/95
tASC
tASR
tAWD
tCAC
tCAH
tCAS
tCHD
tCHR
tCLZ
tcp
tCPA
tCRP
tCSH
tcSR
tCWD
tCWL
tDH
tDHR
tDS
tOD
tOE
tOEH
5-139
MIN
-7
MAX
MIN
35
20
13
NOTES
40
ns
ns
ns
ns
ns
ns
25
24
23
25
23,30
15,25
25
10,000
25
20
20
15
13
5
10
40
10
58
7
42
15
15
45
-2
3
UNITS
53
2
5
62
48
2
5
57
15
15
15
13
5
10
MAX
15
15
10,000
45
10
68
7
47
20
20
55
-2
3
13
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
31
5,24
23, 33
16
25
25
24
5,23
23,30
25,29
24,29
33
24
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc.
z
m
:e
•
c
::D
»
3:
-s:c
s:
ADVANCE
MICRON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
,,,""CO,,,",
FAST PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
z
m
:e
•
c
JJ
»
s:
c
-s:
s:
=+3.3V ±0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
PARAMETER
SYM
MIN
MAX
Output buffer turn-off delay
tOFF
20
OE setup prior to RAS during HIDDEN REFRESH cycle
lORD
IpC
IpD
5
0
35
tpDOFF
2
IpRWC
87
FAST-PAGE-MODE READ or WRITE cycle time
PDE to valid presence-detect data
PDE inactive to presence-detects inactive
FAST-PAGE-MODE READ-WR!TE cycle time
-6
-7
MIN
5
MAX
UNITS
NOTES
25
ns
20,27,36
ns
20
0
40
10
ns
10
2
97
ns
ns
ns
35
34
23
ns
ns
18,26
R/\,S to column-address delay till Ie
IRAC
fRAD
Row-address hold time
IRAH
8
8
ns
24
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
tRAL
35
ns
25
tRAS
60
60
100
40
70
Access time from RAS
i3
70
60
25
13
10,000
30
10,000
14
ns
ns
tRASP
tRASS
tRC
110
RAS to CAS delay time
Read command hold time (referenced to CAS)
tRCD
18
ns
17,26
tRCH
2
2
ns
19,23
Read command setup time
Refresh period (2,048 cycles) - 2 Meg x 72
IRCS
tREF
2
2
ns
ms
23
Refresh period (2,048 cycles) - 2 Meg x 72 S version
tREF
RAS pulse width during SELF REFRESH
Random READ or WRITE cycle time
100,000
70
100
100,000
~s
130
40
18
32
128
31
ns
45
32
128
ms
tRP
40
50
RAS to CAS precharge time
tRPC
0
RAS precharge time during SELF REFRESH
Read command hold time (referenced to RAS)
RAS hold time
tRPS
110
0
130
tRRH
tRSH
0
20
0
25
READ WRITE cycle time
tRWC
155
185
RAS to WE delay time
87
20
Transition time (rise or fall)
tRWD
tRWL
tT
Write command hold time
IWCH
3
15
Write command hold time (referenced to RAS)
tVVCR
43
53
ns
24
WE command setup time
twcs
twp
2
10
2
15
ns
ns
23,30
RAS precharge time
Write command to RAS lead time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT9LO(T)272(X)(S)
DM33-Rev.2f95
50
ns
ns
ns
ns
31
19
ns
25
ns
25
97
ns
23,30
25
ns
25
ns
ns
25
3
20
50
twRH
8
8
ns
22,24
twRP
12
12
ns
22,23
5-140
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MlcronTechnology, Inc
ADVANCE
MICRON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
'""'0''"'''''
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+3.3V ±0.3V)
-6
AC CHARACTERISTICS - EOO PAGE MODE OPTION
PARAMETER
SYM
Access time from column-address
tAA
Column-address setup to CAS precharge during writes
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
tACH
tAR
tASC
Column-address to WE delay time
tASR
tAWD
Access time from CAS
tCAC
Column-address hold time
tCAH
CAS pulse width
RAS LOW to "don't care" during SELF REFRESH
CAS hold time (GBR REFRESH)
CAS to output in Low-Z
Data output hold after CAS LOW
tCAS
tCHD
tCHR
tCLl
CAS precharge time
tCOH
tcp
Access time from CAS precharge
tCPA
CAS to RAS precharge time
CAS hold time
tcRP
CAS setup time (CBR REFRESH)
tcSH
tCSR
CAS to WE delay time
tCWD
Write command to CAS lead time
Data-in hold time
tCWL
tDH
Data-in hold time (referenced to RAS)
Data-in setup time
tDHR
tDS
Output disable
Output enable
OE hold time from WE during READ-MODI FY-WRITE cycle
OE HIGH hold time from CAS HIGH
OE HIGH pulse width
OE LOW to CAS HIGH setup time
Output buffer turn-off delay
OE setup prior to RAS during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
PDE to Valid Presence-Detect Data
PDE Inactive to Presence-Detects Inactive
EDO-PAGE-MODE READ-WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
tOD
tOEHC
tOEP
tOES
tOFF
tORD
tpc
tpD
tpDOFF
tpRWC
tRAC
tRAD
tRAH
tRAL
RAS pulse width
tRAS
Random READ or WRITE cycle time
MT9lD{T)272(X)(S)
OM33-Rev,2/95
tRASP
tRASS
tRG
5-141
-7
MAX
MIN
35
15
43
2
5
57
15
10
15
8
2
,7
10
10
10
10
5
5
0
25
10,000
17
12
15
10
2
7
10
NOTES
ns
25
ns
ns
ns
ns
ns
10,000
ns
ns
ns
ns
15
15
20
10
10
10
5
5
0
30
ns
60
25
15
15
10.000
125,000
ns
25,29
ns
ns
ns
24,29
ns
ns
24
ns
ns
ns
20
ns
ns
10
10
8
40
70
70
100
130
31
5,24
23
23
16
25,37
25
24
5,23
23,30
ns
2
87
2
77
ns
ns
ns
ns
7
24
23
25
23,30
15,25
25
ns
ns
10
53
42
15
17
55
-2
0
ns
ns
45
10
10
8
35
60
60
100
110
UNITS
40
25
40
10
48
7
37
15
15
45
-2
0
MAX
15
53
2
5
67
20
tOE
tOEH
Column-address to RAS lead time
RAS pulse width (EDO PAGE MODE)
RAS pulse width during SELF REFRESH
MIN
ns
ns
ns
70
30
ns
ns
ns
ns
ns
10,000
125,000
20,27,36
20
35
34
23
14
18,26
24
25
ns
ns
!is
31
ns
Micron Technology, Inc., rese!V9slhe right to change products or specifications without notice.
©1995, Micron TechnOlogy, InC.
z
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•
c
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»
3:
-c3:
3:
ADVANCE
MICRON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
"",","COO""
EDO PAGE MODE
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (Vee
=+3.3V ±0.3V)
AC CHARACTERISTICS - EOO PAGE MOOE OPTION
PARAMETER
z
m
=E
•
C
:D
»
s::
-cs::
s::
RAS to CAS delay time
Read command hold time (referenced to CAS)
Read command setup time
Refresh period (2,048 cycles) - 2 Meg x 72
Refresh period (2,048 cycles) - 2 Meg x 72 S version
RAS precharge iime
RAS to CAS precharge time
RASprecharge time during SELF REFRESH
Read command hold time (referenced to RAS)
RAS hold time
READ WRITE cycle time
RAS to WE delay time
WrITe command. to RAS lead time
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
WE command setup time
Output disable delay from WE (CAS HIGH)
Write command pulse width
WE pulse width for output disable when CAS HIGH
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT9LO(T)272(X)(S)
DM33 - Rev. 2/95
-7
-6
SYM
MIN
MAX
MIN
MAX
UNITS
NOTES
tRCD
tRCH
tRCS
tREF
tREF
tRP
12
2
2
40
12
2
2
45
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
17,26
19,23
23
tRPC
tRPS
tRRH
tRSH
tRWC
tRWD
tRWL
40
0
110
twpz
0
15
155
82
20
2
15
43
2
2
10
10
tWRH
tWRP
8
12
IT
twCH
tWCR
twcs
tWHZ
twp
32
128
32
128
50
18
50
0
130
0
17
182
92
20
2
17
53
2
2
12
12
8
12
50
20
31
19
25
25
23,30
25
25
24
23
27
22,24
22,23
Micron Technology, Inc., resetves the right to change products or specifications wlliiout notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
"'"''''00''"'
NOTES
1. All voltages referenced to Vss.
2. This parameter is sampled. Vee = +3.3V; f = 1 MHz.
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOlls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume IT = Sns for FPM and 2.Sns
forEDO.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
andVIH).
10. In addition to meeting the transition rate specification,
all input signals must transit between VIH and VIL (or
between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF and VOL = 0.8Vand VOH = 2.0V.
14. Assumes that iRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICPN.
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. iRCD (MAX) is specified as a
reference point only; if IRCD is greater than the
specified tRCD (MAX) limit, access time is controlled
exclusively by ICAe.
18. Operation within the lRAD (MAX) limit ensures that
IRAC (MIN) can be met. iRAD (MAX) is specified as a
reference point only; if iRAD is greater than the specified IRAD (MAX) limit, access time is controlled
exclusively by IAA.
MT9LD(T}272{X)(S)
DM33 - Rev. 2/95
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW and·
OE = HIGH.
22. IWTS and lWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDECtest
mode (with CBR timing constraints). These two
parameters are the inverse of twRP and IWRH in the
CBR REFRESH cycle.
23. A +2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
24. A -2ns timing skew from the DRAM to the module
resulted from the addition of line drivers.
2S. A +Sns timing skew from the DRAM to the module
resulted from the addition of line drivers.
26. A -2ns (MIN) and a -Sns (MAX) timing skew from t1w
DRAM to the module resulted from the addition of
line drivers.
27. A +2ns (MIN) and a +Sns (MAX) timing skew from
the DRAM to the module resulted from the addition
of line drivers.
28. The maximum current ratings are based with the
memory operating or being refreshed in the x72
mode. The stated maximums may be reduced by onehalf when used in the x36 mode.
29. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles and WE leading edge in
LATE WRITE or READ-MODIFY-WRITE cycles.
30. IWCS, IRWD, IAWD and ICWD are not restrictive
operating parameters. twcs applies to EARLY
WRITE cycles. IRWD, tAWD and ICWD apply to
READ-MODIFY-WRITE cycles. If IWCS ~ twcs
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If IRWD ~ iRWD (MIN), IAWD ~
IAWD (MIN) and ICWD ~ !CWD (MIN), the cycle is a
READ-MODIFY-WRITE and the data output will
contain data read from the selected cell. If neither of
the above conditions is met, the state of data-out is
indeterminate. OE held HIGH and WE taken LOW
after CAS goes LOW results in a LATE WRITE (OEcontrolled) cycle. IWCS, tRWD, ICWD and IAWD are
not applicable in a LATE WRITE cycle.
5-143
Mieron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technalogy, Inc.
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III
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3:
-3:c
3:
ADVANCE
UICRON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
"'~"OCOC'"O
NOTES (continued)
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31. Refresh must be completed within the time of three
external refresh rate periods prior to active use of the
DRAM (provided distributed CBR REFRESH is used
when in the active mode.) Alternatively, a complete
set of row refreshes must be executed when exiting
SELF REFRESH prior to active use of the DRAM if
anything other than distributed CBR REFRESH is used
in the active mode.
32. Column-address changed once each cycle.
33. The 3ns minimum is a parameter guaranteed by
design.
34. tpDOFF MAX is determined by the pullup resistor
value. Care must be taken to ensure adequate
recovery time prior to reading valid up-level on
subsequent DIMM position.
35. Measured with the specified current load and 100pf.
36. For FAST PAGE MODE option, tOFF is determined
by the first RAS or CAS signal to transition HIGH. In
comparison, toFF on an EDO option is determined by
the latter of the RAS and CAS signal to transition
HIGH.
37. Applies to both EDO and FAST PAGE MODEs.
II
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MT9LO(T)272{X)(S)
DM33 - Rev. 2195
5-144
Micron Technology, Inc., reserves !he righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
"'~""O"'"
1-·
READ CYCLE 37
RC
tRAS
RAS
V ,H
VIL
tRP
I
leSH
I
tRSH
IRCD
'CRP
CAS
V,H
Vil
=~
tAR
tRAD
AODR
V,H
Vil
WE
V,H
Vil
:::I1111Ji[
~,1
ROW
NOTE 1
I
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III
~
tRCS
II
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JJ
NOTE 2
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~
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DQ
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EARLY WRITE CYCLE 37
3:
tRC
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tRCD
'AR
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ADDR
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..
tCWL
~'''.~
II
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VALID DATA
~
:
~
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~
NOTE:
MT9LD(T)272(X)(S)
DM33 - Rev. 2/95
UNDEFINED
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for twRP and twRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
2. tOFF is referenced from riSing edge of RAS or CAS, which ever occurs last.
5-145
Micron Technology, Inc., reserves the right
to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MII::::I=ICN
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
,","",coo,,,
FAST-PAGE-MODE READ CYCLE
RASP
'PC
tCSH
_I~
'AR ~~
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ADDR
II
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WE ~!~
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tASR
ROW
tRAH~1
WIIJ
'RCS• I
I
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'CLZ-
l>
DQ
s:
-s:C
s:
~
~II~
1
1I
WIIIIIII
COLUMN
I
ROW
COLUMN
~
1
-11(((1111111/_1_1/,_'
::tJ
tCAH _
Rcs
Rcs I -I r'RRH
'RCH-I Ii -'-I IL
I 'RCH-II Ii-I ILI
I
I
tRAL
WIIIIIIJ
COLUMN
I
I
II
K
~I I~
'RAD
FL
'CP
'RSH
~ ~~ ~ ~
'RCD
-
AA IYf
I 'f'--+-I--:"'CI'ACCc-,
1
I
t(1
Ii',
'1!
,
NOTE:
MT9LD(T)272(X)(S)
DM33 - Rev. 2195
'pc
Icp
teAS
COLUMN
-11_.
I~I
teAS
tcp
!
f
'AR
'RAD
ADDR
teAS
IRCD
IRSH
'CAH'
I~ 'Ase
leAH
COLUMN
"'1
I~II :::~-I
1,1
COLUMN
I
~
DON'TeARE
~
UNDEFINED
1, Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WEHIGH ·for !WRP and tWRH, This design implementation will facilitate compatibility with
future EDO DRAMs,
5-147
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
l>
s::
-s::C
s::
ADVANCE
MICRON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
,,,"",we,,",
READ WRITE CYCLE 37
(LATE WRITE and READ-MODIFY-WRITE cycles)
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EDO/FAST-PAGE-MODE READ-WRITE CYCLE 37
(LATE WRITE and READ-MODIFY-WRITE cycles)
ADDR
~[~ :wt=:$:=:)~~~~~~;x:~~j@~~:::$~j@~~~~
1
1-'RwL
_tCWL
DO
_)_'00
tOE __ 1 ---
OE
NOTE:
MT9LD(T)272(X)(S)
DM33 - Rev, 2195
tJ '00 tJ
~:g~ =~----OPEN
~:t
-f$;W'$$,J/,J$,0/##/i/Mi
toE--
---
toE
OPEN-
---
~~-
~
DON'TeARE
~
UNDEFINED
1. IpC is for LATE WRITE cycles only.
2. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and IWRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
5-148
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc
ADVANCE
UII:::RCN
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
"'~"co,,"
1-·
RAS-oNlY REFRESH CYCLE 37
(WE = DON'T CARE)
RAS
CAS
ADDR
V,H
V1l _
~:~ ~=J
VIH-~
'CRP
tASR
tRC
~.
II,
t
s::
-s:C
s:
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY~WRITE)
'RASP
tCSH
tpc
tpc
'RSH
11_ _-'-tcP'---_1 ~--
~
ADDR
DO
~:gt
----tOE
OE~:~= W;//;1/;1a1;1/;0';1;/'/$J;ll:X~
DON'T CARE
~ UNDEFINED
NOTE:
MT9LD(T)272(X}(S)
DM33 - Rev. 2/95
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for IWRP and twRH. This design implementation will facilitate compatibility with
future EDO DRAMs.
5-149
Micron Technology,·lnc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
ecce'''''''' '"
FAST-PAGE-MODE .READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
'F=L
RASP
ICSH
I~'
.-./
'RCD
~
'AA}
'PC
I'
~:~ ::~
ROW
i .)
II
tRAL
COLUMN
IRCS
II 'cWL"~.1
II
IRWL
II 'WP
•
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WE~:t::
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~
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ADDR
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VALID DATA
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PRESENCE-DETECT READ CYCLE 37
~ :~ -------,L~+
PD1-PD8
No.TE:
MT9LD(T)272(X)(S)
DM33 - Rev. 2/95
V,L -
~,--
tt-
---f
__
VA_LlD_PR_ES_EN_CE-_DE_TEC_T
~
DON'T CARE
~
UNDEFINED
1.Do not drive data prior to tristate.
2. PD pins must be pulled HIGH at next level of assembly.
5-150
Micron Technology, Inc" reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
ADVANCE
MICRON
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
"c~"coc,,"
1-·
CBR REFRESH CYCLE 37
(Addresses, OE = DON'T CARE)
.
.--1
RP
, ,
RAS
'RPe
=j~:~l
1
'WRP
II
RP
.
,
RAS
,I
~r~~
~k
oPEN---;-,II~_ _ _ _-
II
DO
WE
._1 •
'WRH
'WRP
II
'WRH
~:t W//jI/jln- -~//jI/jljI//lIijjl/j- -W/jI#$ijjl;@//lI$/;//a
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EDO READ CYCLE
(with WE-controlled disable)
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3:
.. '
COLUMN
ADDR
tWHZ
DQ
~gt --------OPEN------~~r~V;;;:;:AL;,D;;;;DAT;:A~
I_
tcLZ
oP:N-'6
'00
11//1///1$;;/1111///1///1j/;
~
DON'T CARE
f222I UNDEFINED
NOTE:
MT9LO(T)272(X)(S)
OM33 - Rev. 2/95
1. Although WE is a "don't care" at RAS time during an access cycle (READ or WRITE), the system designer
should implement WE HIGH for 'WRP and WRH. This design implementation wiil facilitate compatibility with
future EDO DRAMs.
5-151
Micron Technology, Inc., reserves the right to change products or specifications WithOut notiCe.
©1995, Micron teChnology, Inc.
ADVANCE
MICRON
1-·
MT9LD(T)272(X)(S)
2 MEG x 72 DRAM MODULE
,,,,,"ow",,,
HIDDEN REFRESH CYCLE 21,37
(WE = HIGH; OE = LOW)
(READ)
(REFRESH)
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ADDR
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-s:C
s
DO
~:gr
::-----
OPEN
~
too
tOE
DE
~:r !@'$$$/#$j'$/;l//;l/$//,d~
.1
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SELF REFRESH CYCLE 37
(Addresses and OE = DON'T CARE)
RAS
CAS
DQ
~:r::
VOH-
t RPC
I~II
~:r -J.
VOL
WE
tRASS
~
_
tCSH.
..
tWRP
t.
~.
NOTE 1
\~:)
• _I
.
~I
)
•
tRPS
•
~OTE 2
~
tRPC
I~I
W~W/1111/1/I!III!//I//////////I/II///////;) \ II
111\--oPEN
II
tWAH
.
J
;-
II
tWRP
II
tWRH
~:~ :'i//I/////O- -W4r/////////;1iW$///ffff##///I/j;0Ij- -¢W/$/;1mu//&
NOTE:
MT9LD(T)272(X){S)
DM33 - Rev, 2/95
~
DON'T CARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a compete burst of all rows should be executed.
5-152
Micron Technology, Inc., reserves the right to change products or specifications wilhout nOlice.
©1995, Micron Technology, Inc,
DRAM CARDS ................................................ .
DRAM CARD PRODUCT SELECTION GUIDE
Memory
Configuration
3.3V DRAM Cards
Pari
Number
Access
Time (ns)
Number of Pins
Card
Page
1 Meg x 32
3.3V
4 Megabytes
MT8D88C132V(S)
60,70,80
88
6-33
1 Meg x32
3.3V
4 Megabytes
MT8D88C132VH(S)
60,70,80
88
6-49
2 Meg x 32
3.3V
8 Megabytes
MT16D88C232V(S)
60,70,80
88
6-33
2 Meg x 32
3.3V
8 Megabytes
MT16D88C232VH(S)
60,70,80
88
6-49
4 Meg x 32
3.3V
16 Megabytes
MT8D88C432V(S)
60,70,80
88
6-33
4Meg x 32
3.3V
16 Megabytes
MT8D88C432VH(S)
60,70,80
88
6-49
8Meg x 32
3.3V
32 Megabytes
MT16D88C832V(S)
60,70,80
88
6-33
8 Meg x 32
3.3V
32 Megabytes
MT16D88C832VH(S)
60,70,80
88
6-49
1 Meg x 32
5V
4 Megabytes
MT8D88C132(S)
60, 70
88
6-1
1 Meg x 32
5V
4 Megabytes
MT8D88C132H(S)
60, 70
88
6-17
2 Meg x 32
5V
8 Megabytes
MT16D88C232(S)
60, 70
88
6-1
2 Meg x 32
5V
8 Megabytes
MT16D88C232H(S)
60, 70
88
6-17
5V DRAM Cards
MICRON
""" ,
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
DRAM CARD
4, 8 MEGABYTES
1-·
1 MEG, 2 MEG x 32; 5V, FAST PAGE
MODE, OPTIONAL SELF REFRESH
FEATURES
~ Lowpower
• JEDEC~standard 88-pin DRAM card pinout
• Polarized receptacle connector
• Industry-standard DRAM FAST PAGE MODE
operation
• High reliability, gold-plated connector
• All outputs fully TTL-compatible
• Multiple RAS inputs for x16 or x32 selectability
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN; optional SELF REFRESH mode
• FAST PAGE MODE (FPM) access cycle
• Single +5V ±5% power supply
• Extended Refresh
OPTIONS
MARKING
• Timing
60ns access
70ns access
-6
o
::D
»
i:
o
-7
• Refresh
Extended Refresh
SELF REFRESH
»
::D
Blank
S
0'
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tpc
tM
tCAC
tRP
-6
-7
110n5
130n5
60n5
70ns
35n5
40ns
37n5
42ns
22n5
27n5
40n5
50n5
VALID PART NUMBERS
PART NUMBER
DESCRIPTION
MT8D88C132-xx
MT8D88C132-xx S
MT16D88C232-xx
MT16D88C232-xx S
1 Megx32
1 Meg x 32, SELF REFRESH
2Megx32
2 Meg x 32, SELF REFRESH
I
GENERAL DESCRIPTION
The MT8D88C132(S) and MT16D88C232(S) comprise a
family of JEDEC standard DRAM cards organized in x32bit memory arrays. The cards may also be configured as
xl6-bit memory arrays, provided the corresponding DQs
on the host system are made common, and memory bank
control procedures are implemented. Four separate CAS
inputs allow byte accesses.
MT8D88C132(S), MT16D88C232(S)
OC01.pm5 - Rev. 2195
6-1
Micron Technology, Inc., reserves lI1e right to change products or specifidatioos wiltlout notice.
©1995, Micron Technology, Inc.
MICRON
1-·
MT8D88C132(S); MT16D88C232(S)
4MB, 8MB DRAM CARDS
m~"'oo,,"c
GENERAL DESCRIPTION (continued)
Eight presence-detect pins may be read by the host to
identify the card's organization, number of banks, access
time and refresh operation. These extensive presence-detect functions allow systems to take full advantage of the
card's advanced power-saving features.
These Micron DRAM Cards are built with 3.370-inchlong static dissipative plastic frames covered by metal
panels. Packages containing 88-pin receptacle connectors
are keyed to prevent improper installation or insertion into
other types of IC card sockets.
These cards are designed for low-power operation using
low-power, extended refresh DRAMs. Standard component DRAM refresh modes are supported as well.
Multiple RAS inputs conserve power by allowing individual bank selection. In the x32 organization, the memory
is a single array that may be divided into four separate bytes.
In the x16 organization, up to two banks, each with 2
separate bytes, may be independently selected. One bank is
activated by each RAS selection; the others not selected
remain in standby mode, drawing minimum power.
FUNCTIONAL BLOCK DIAGRAM
(4MB - MT8D88C132)
•
RASO
RA§
C
::D
l>
CASO
D'>-------------~C>3
We
B1
s:
....
DOD
:
DOl
o
l>
::D
C
=
CAS3
Di>---"I--+---\
D024
WE
D031
=
ADDRESS
NOTE:
1. B1 through B4 = x8 memory blocks.
2. D = 74AC11244 line drivers.
MT8D88CI32(S), MT16D88C232(S)
DC01.pm5 - Rev. 2195
6-2
Micron Technology, Inc., reserves the nght 10 change produc\s or specliications without nolice.
©1995, Micron Technology, Inc
MICRON
1-·
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
"'""'0"""
FUNCTIONAL BLOCK DIAGRAM
(8MB - MT16D88C232)
RAsa
RAS1
RAS
CAsa
D
RAS
CAS
CAS
••
•
-
RAS
CAS1
RAS
CAS
CAS
•
-
RAS2
RAS3
RAS
CAS2
-
»
JJ
CAS
C
••
•
-
RAS
CAS3
RAS
CAS
CAS
••
•
-
WE
-
ADDRESS
NOTE:
1. B1 through B8
=x8 memory blocks.
2. D= 74AC11244 line drivers.
MT6D88C132(S), MT16D88C232(S)
DC01.pm5 - Rev. 2/95
6-3
»
3:
0
RAS
CAS
C
JJ
••
Micron Technology, Inc., reserveslhe righl 10 change products or specifications without notice.
©1995, Micron Technology, Inc.
UU:::I=ICN
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
m~wcoc""
1-·
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
22,26,65,69
RASO,RAS2
RAS1, RAS3
Input
Row-Address Strobe: RAS is used to latch the rowaddress. Two RAS inputs allow for a single x32 bank or
two x16 banks.
23,24,66,68
CASO-CAS3
Input
Column-Address Strobe: CAS is used to latch the
column-address, enable the DRAM output buffers and
strobe the data inputs on WRITE cycles. Four CAS
inputs allow byte access control for any memory bank
configuration.
70
WE
Input
Write Enable: WE is the READIWRITE control for the DO
pins. If WE is LOW prior to CAS going LOW, the access
e
•
c
::c
>
o
>
::c
Si:
c
I
DESCRIPTION
is a VvRITE cycle. Ii vVE is HIGH during the CAS LOvV
transition, the access is a READ cycle .
Address Inputs: These inputs are multiplexed
and clocked by RAS and CAS.
13,57,14,58,16,59,
18,60,19,61
AO-A9
Input
2-8, 10, 34, 36,
38-43, 46-53,
80-87
000-0031
Input!
Output
71, 28, 72, 29,
74,30,75,76
PD1-PD8
-
Presence-Detect: These pins are read by the
host system and tell the system the card's personality.
They will be either left floating (NC) or grounded (Vss).
11,12,17,20,21,25,
31,32,33,35,54,55,
62,64,65,69,77,78,
79
NC
-
No Connect: These pins should be left unconnected
(reserved for future use).
Pins 12, 31-33, 54, 77-79 reserved forx36/x40 DOs.
Pins 11, 17, 25, 35 reserved for 3.3V Vce.
Pin 55 reserved for x40 OE.
9,15,27,37
Vee
Supply
Power Supply: +5V ±5%
1, 44, 45, 56,
63,67,73,88
Vss
Supply
Ground
MT8D88C132(S). MT16D88C232(S)
DC01.pmS - Rev. 2/95
Data 1/0: For WRITE cycles, 000-0031 act as
inputs to the addressed DRAM location. BYTE
WRITEs may be performed by using the corresponding
CAS select. For READ access cycles, 000-0031 act as
outputs for the addressed DRAM location.
6-4
Micron Technology, inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
I"IIC:I=ICN
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
",e,,,,,,,,
FUNCTIONAL DESCRIPTION
The MT8D88C132(S) and MT16D88C232(S) comprise a
family of DRAM cards organized in x32-bit memory arrays
~RASO = RAS2). They also may be configured as x16-bit
memory arrays provided the corresponding DQs on the
flOst are connected and memory bank control procedures
~re implemented by interleaving both RAS lines.
Most x32-bit applications use the same signal to control
the CAS inputs. RASO and RAS1 control the lower 16 bits
and RAS2 and RAS3 control the upper 16 bits to obtain a x32
memory array. For x16 applications, the corresponding DQ
and CAS pins must be connected (DQO to DQ15, DQ1 to
DQ16 and so forth, CASO to CAS2 and CAS1 to CAS3). Each
RAS is then a bank select for the x16 memory organizations.
FAST PAGE MODE operation allows faster data operations (READ or WRITE) within a row-address-defined
(AO-A9) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed·in by CAS. CAS may
be toggled-in by holding RAS LOW and strobing-in different column-addresses, thus executing faster memory cycles.
ReturningRAS HIGH terminates the FAST PAGE MODE
operation. Returning RAS and CAS HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the next
cycle during the RAS HIGH time.
REFRESH
DRAM OPERATION
An optional SELF REFRESH mode is also available. The _
"5" version allows the user the choice of a fully static lowpower data retention mode, or a dynamic refresh mode at
the extended refresh period.
The optional SELF REFRESH feature is initiated by
performing a CBR REFRESH cycle and hold ing RASI.OW ......
for the specified tRASS. Additionally, the "S" Vt'fsion .11- rJI'
lows for an extended refresh rate of 125flS per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby mode. _ _
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum time ofiRPS (ztRC). This delay allows
for the completion of any internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all rows must be
refreshed within 300flsprior to the resumption of normal
operation.
DRAM REFRESH
Memory cell data is retained in its correct state by maintaining power and executing any RAS cycle (READ,
WRITE) or RAS refresh cycle (RAS ONLY, CBR, extended
CBRor HIDDEN) so that all combinations ofRAS addresses
(AO-A9) are executed at least every lREF, regardless of
sequence. The CBR REFRESH cycle will invoke the internal
refresh counter for automatic RAS addressing.
The implied method of choice for refreshing the memory
card is the extended CBR cycle. This is a very low-current,
data retention mode made possible by using the CBR REFRESH cycle over the extended refresh range (lcC7).
The memory card may be used with the other refresh
modes common to standard DRAMs. This allows the
memory card to be used on existing systems that do not
utilize the extended CBR REFRESH cycle. However, the
memory card will draw more current in the standbymode.
C
:::D
:s:
0
l>
:::D
C
DRAM READ AND WRITE CYCLES
During READ or WRITE cycles, each bit is uniquely
addressed through the 20 address bits, which are entered
10 bits (AO-A9) ala time. RAS is used to latch the first 10 bits,
and CAS latches the latter 10 bits. READ or WRITE cycles
are selected with the WE input.. A logic HIGH on WE
dictates READ mode while a logic LOW on WE dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of CAS. WE must fall prior to CAS
(EARLY WRITE). The data inputs and data outputs are
routed through pins using common I/O and pin direction
is controlled by WE.
MT8D88C132(S), MT16D88C232(S)
DC01.pmS - Rev. 2195
PHYSICAL DESIGN
These Micron DRAM Cards are constructed with a 3.370inch-long static dissipative plastiC frame covered by metal
panels. Inside, thin small-outline package (TSOP) DRAMs
are mounted on. an ultrathin printed circuit board. The
board is attached to· a high-insertion, 88-pin receptacle
connector. Thepackage is keyed to prevent improper installation, including insertion into other types of IC card sockets. The DRAM cards operate reliably up to 55°C.
6-5
Micron Technology, Inc" reserves the right to change products or speCifications wilhol.lt notice.
©1995, Micron Technology, Inc.
MIC:RON
1-·
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
,""'"w"""
MEMORY TRUTH TABLE
ADDRESSES
~
WE
IR
IC
Standby
H
H-X
X
X
X
High-Z
READ
L
L
H
ROW
COL
Data-Out
EARLY WRITE
L
L
L
ROW
COL
Data-In
L
L
H-L
ROW
COL
Data-In
READ WRITE
•
C
:l1
»
s:
o
DATA IN/OUT
RAS"
FUNCTION
000-0031
FAST-PAGE-MODE
1st Cycle
L
H-L
H
ROW
COL
Data-Out
READ
2nd Cycle
L
H-L
H
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H-L
L
ROW
COL
Data-In
EARLY-WR!TE
2nd Cycle
L
H-L
L
Ilia
~/~
1"'''''''
VVL.
Data-In
FAST-PAGE-MODE
1st Cycle
L
H-L
H-L
ROW
COL
Data-Out
READ-WRITE
2nd Cycle
L
H-L
H-L
n/a
COL
Data-Out
L
H
X
ROW
n/a
High-Z
HIDDEN
READ
L-H-L
L
H
ROW
COL
Data-Out
REFRESH
WRITE
RAS-ONLY REFRESH
L-H-L
L
L
ROW
COL
Data-In
CBR REFRESH
H-L
L
H
X
X
High-Z
SELF REFRESH (S version)
H-L
L
H
X
X
High-Z
PRESENCE-DETECT TRUTH TABLE
»~--------------------------~----------------~
:l1
C
~--~------~--r-~~--~--~--~~~~~~--~~~~
Refresh Control
NOTE:
Vss
=ground.
MT8D88Cl32(S}, MT16D88C232(S)
DeDI.pOlS - Rev. 2f95
6-6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc
MICRON
1-·
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
"'"""CC,"
*Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
U
Voltage on Vee Supply Relative to Vss ........... -1.0V to +7V
Operating Temperature TA (ambient) .............. O°C to SsoC
Storage Temperature ..................................... -40°C to +70°C
Power Dissipation ............................................................. 8W
Short Circuit Output Current ..................................... SOmA
Card Insertions (connector's life cycle) ..................... 10,000
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 4, 6, 7) (O°C
0;
TAO; 55°C; Vcc
=+5V ±5%)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vcc
4.75
5.25
V
Input High (Logic 1) Voltage, all inputs
VIH
2.4
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
PARAMETER/CONDITION
INPUT LEAKAGE CURRENT
Any input: OV 0; VIN 0; 6.5V
(All other pins not under test =OV) for each package input
RASO-RAS3
111
-8
8
IlA
Buffered
112
-2
2
Il A
OUTPUT LEAKAGE CURRENT
(0 is disabled, OV 0; VOUT 0; 5.5V) for each package input
DOO-D031
102
-20
20
!lA
VOH
2.4
OUTPUT LEVELS
Output High Voltage (lOUT =-5 mAl
Output Low Voltage (lOUT =4.2 mAl
MT8DSBC132(S), MT16D88C232(S)
DC01.pm5- Rev. 2195
VOL
NOTES
o
::xl
»
33
V
0.4
•
V
3:
o
»
::xl
o
6-7
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
1"I1t:F=lCN
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
"""'00""
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (O°C :;:; TA:;:; 55°C; Vcc = +5V ±5%)
MAX
PARAMETER/CONOITION
SYMBOL
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: tRC =tRC [MIN])
Icc1
STANDBY CURRENT: (TTL)
(RAS =CAS = VI H)
Icc2
OPERATING CURRENT: FAST PAGE MODE
Aveiage power supply current
(RAS = VIL, CAS, Address Cycling: tpc =tpc [MIN])
•
ICC3
STANDBY CURRENT: (CMOS)
(RAS = CAS =Other Inputs = Vcc -0.2V)
Icc4
REFRESH CURRENT: RAS ONLY
c
Average power supply current
l>
Average power supply current
o
l>
REFRESH CURRENT: Extended CBR
Average power supply current during extended CBR; CAS =0.2V
or CBR cyc'ling; RAS =tRAS (MIN); tRC = 12511S; WE = Vcc-0.2V;
AO-A9 and DO =Vcc -0.2V or 0.2V (DO may be left open)
C
Average power supply current; CBR cycling with
:::c
s:
:::c
(RAS Cycling, CAS
Iccs
=VIH: tRC =tRC [MIN])
REFRESH CURRENT: CBR
(RAS, CAS, Address Cycling: tRC
Icc6
=tRC [MIN])
Icc?
SIZE
-6
-7
4MB
880
800
8MB
896
816
4MB
8MB
16
32
16
32
4MB
640
560
8Msi
656
576
4MB
8MB
1.6
3.2
1.6
3.2
4MB
880
800
8MB
896
816
4MB
880
800
8MB
960
880
4MB
2.4
2.4
8MB
4.8
4.8
4MB
2.4
2.4
8MB
4.8
4.8
UNITS NOTES
mA
3,4,30
mA
mA
3,4, 30 1
mA
mA
3,30
mA
3,5
mA
3, 5
mA
5,31
REFRESH CURRENT: SELF (S version only)
RAS;:>: tRASS (MIN) and CAS held LOW; WE = Vcc-0.2V; AO-A9
and DIN = Vcc - 0.2V or 0.2V (DIN may be left open)
MT8D88C132(S), MT16D88C232(S)
DC01.pm5 - Rev. 2/95
6-8
Icca
(S only)
Micron Technology. Inc., reserves the right 10 change products or speCifications without notice.
©1995, Micron Technology, Inc.
I"IICRCN
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
'''"'ow","
CAPACITANCE
MAX
SYMBOL
4MB
8MB
UNITS
NOTES
Input Capacitance: CASO-CAS3
CI1
9
9
pF
2
Input Capacitance: WE
CI2
13
13
pF
2
Input Capacitance: RASO-RAS3
CI3
34
34
pF
2
Input/Output Capacitance: DOO-D031
CIO
10
18
pF
2
Input Capacitance: Addressess
CI3
9
9
pF
2
PARAMETER
I
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (O°C
~
T A ~ 55°C; Vcc = +5V ±5%)
-6
AC CHARACTERISTICS
PARAMETER
SYM
Access time from column-address
tAA
Column-address hold time (referenced to RAS)
tAR
Column-address setup time
Row-address setup time
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time entering SELF REFRESH
CAS hold time (CBR REFRESH)
CAS to output in low-l
tASC
tASR
tCAC
tCAH
tCAS
tCHD
tCHR
tCll
tcp
CAS precharge time
Access time from CAS precharge
tCPA
CAS to RAS precharge time
tCRP
CAS hold time
tCSH
tCSR
CAS setup time (CBR REFRESH)
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output buffer turn-off delay
FAST-PAGE-MODE
READ or WRITE cycle time
Access time from RAS
RAS to column-address delay time
Row-address hold time
tCWl
tDH
tDHR
tDS
tOFF
tpc
tRAC
tRAD
Column-address to RAS lead time
tRAH
tRAL
RAS pulse width
tRAS
RAS pulse width (FAST PAGE MODE)
RAS pulse width entering SELF REFRESH
MT8D88C132(S}, MT16D88C232{S)
DC01.pm5 - Rev. 2195
iRASP
tRASS
6-9
MIN
-7
MAX
MIN
37
22
17
13
8
37
60
60
100
NOTES
ns
25
24
23
25
15,25
25
10,000
22
60
23
10,000
100,000
ns
ns
27
22
20
10
8
5
10
42
17
58
12
15
17
45
-2
5
35
UNITS
42
48
2
7
43
2
7
15
10
8
5
10
MAX
10,000
13
8
42
70
70
100
ns
ns
ns
ns
47
17
68
12
20
22
55
-2
5
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
27
31
5,24
23,32
16
25
25
24
5,23
ns
ns
25
ns
24
19,27
ns
ns
70
28
ns
ns
ns
ns
10,000
100,000
14
18,26
24
25
ns
ns
JlS
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron TechnologY,lnc.
C
:II
l>
s:
o
l>
:II
C
MICRON
1-·
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
'''~"O'OO,,"C
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (DOC :s; TA :s; 55°C; Vee = +5V ±5%)
SYM
MIN
Random READ or WRITE cycle time
RAS to CAS delay time
tRC
tRCD
Read command hold time (referenced to CAS)
tRCH
110
18
2
Read command setup time
tRCS
tREF
2
Refresh period (1,024 cycles)
RAS precharge time
•
c
::c
»
s:
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»
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tRP
40
tRPC
IRPS
0
Read command hold time (referenced to RAS)
tRRH
RAS hold time
IRSH
IRWL
IT
IWCH
Write command pulse width
tWCR
twcs
IWp
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
IWRH
tWRP
Write command hold time (referenced to RAS)
WE command setup time
MAX
UNITS
NOTES
43
ns
ns
17,26
2
ns
19,23
2
ns
23
MAX
MIN
38
130
18
128
RAS to CAS precharge time
RAS precharge time exiting SELF REFRESH
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
-7
-6
AC CHARACTERISTICS
PARAMETER
50
0
130
110
0
22
22
3
17
43
2
128
ms
ns
ns
ns
19
ns
25
ns
25
ns
ns
ns
25
ns
23
10
8
12
8
ns
12
ns
50
50
31
ns
0
27
27
3
22
53
2
15
24
ns
22,24
22,23
c
MTBD88C132(S), MTI6D88C232(S)
DC01.pm5 - Rev. 2195
6-10
Mlcton Technology, Inc., reserves the right to change products or specifications without nolice
©1995, Micron Technology, Inc.
MICRON
1-·
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
'''"''co",'"'
NOTES
18. Operation within the IRAD (MAX) limit ensures that
IRCD (MAX) can be met. tRAD (MAX) is specified as
a reference point only; if IRAD is greater than the
specified IRAD (MAX) limit, access time is controlled
exclusively by IAA.
19. Either IRCH or tRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.
22. IWTS and IWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverse of twRP and twRH in the
CBR REFRESH cycle.
23. A +2ns timing skew from the DRAM to the DRAM
card resulted from the addition of line drivers.
24. A -2ns timing skew from the DRAM to the DRAM
card resulted from the addition of line drivers.
25. A +7ns timing skew from the DRAM to the DRAM
card resulted from the addition of line drivers.
26. A -2ns (MIN) and a -7ns (MAX) timing skew from the
DRAM to the DRAM card resulted from the addition
of line drivers.
27. A +2ns (MIN) and a +7ns (MAX) timing skew from
the DRAM to the DRAM card resulted from the
addition of line drivers.
28. The maximum current ratings are based on one of the
two banks operating or being refreshed in a x32
mode. The stated maximums may be reduced by onehalf when used in the x16 mode.
29. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
30. Column-address changed once each cycle.
31. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
32. The 3ns minimum is a parameter guaranteed by
design.
33.4MB version is half of values shown.
1. All voltages referenced to Vss.
2. This parameter is sampled. Vee = +SV ±10%;
f=lMHz.
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 1OOl1s is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
8. AC characteristics assume IT = Sns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICP.
17. Operation within the IRCD (MAX) limit ensures that
lRAC (MAX) can be met. tRCD (MAX) is specified as
a reference point only; if tRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by ICAe.
MT8D88G132(S), MTI6D88Ca32(S)
DC01.pm5-Aev.2/95
6-11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
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MIC:RON
1-·
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
,"","0",'"
READ CYCLE
1
1
tCSH
-I
ADDA
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EARLY WRITE CYCLE
IRC
C
'RAS
'I
tCSH
ADDR
MT8D88CI32(S), MTI6D88C232(S)
DC01.pm5 - Rev. 2/95
ROW
6-12
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC:RON
1-·
MT8D88C132(S), MT16D88C232(S)
4MB, 8MB DRAM CARDS
,"""'co"'''''
FAST-PAGE-MODE READ CYCLE
-------------------------------'~R~~P------------------------------~~
tCSH
~I----------~~~-I
ADDR
VIH V,L
-'-'.LU,,____-;-__---"'<.LlCL/l~___;__.----nLLLfLLLIl'_--__,_;_---'C.=fLLill'_----..___-----"\LLlLL'_';L_LLLLLf;LLL.#
'RCS
WE
DO
•
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~:gt
-.----------
OPEN
o
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-----------1X)(1OO
s:
CAS
-
DOO
WE
B1
o
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l>
DQ7
-=
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RASCAS
~'2
~
~r
"
.•
DOS
~D 015
RAS2
~
CAS2
CAS
t--
WE
B3
IA
"D 016
I~
"D 023
.
"D 024
&§..-
-=
r-RA§-
t--
CAs
WE
B4
'0.
WE
ADDRESS
NOTE:
1. 81 through 84
MT8D88CI32H(S). MTf6D8BC232H{S)
DC02.pm5 - Rev. 2/95
D031
-=
=x8 memory blocks.
6-18
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc.
I'IIIC:I=ICN
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
","",co",,,
o
FUNCTIONAL BLOCK DIAGRAM
(8MB - MT16D88C232H)
RAS1
RAsa
RAS
RAS
-
CAS
CAS
WE
1\
B1
~:-
:.4
l>.
I~
r
D~a
•
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DQ7
WE
.4
I!.
~
r
B5
_I~
l-
'-~
-"
RAS
CAS
CAS
WE
B2
A
.
r D~15"q
r
t.
.d
D~8
•
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-
t.D~16.4
A
•
r D~23 ~
fk-
..
RA's
.. WE
B4
DE
WE
l>
B7
.4
~
RAS
CAS
CAS
t. D~24.4
A
•
r D~31 ~
I~
-
1\
rl
B8WE
A
DE
-
ADDRESS
NOTE:
1. B1 through B8
MT8D88C132H(S), MT16D88C232H(S)
DC02.pm5 - Rev. 2195
=x8 memory blocks.
6-19
3:
:0
WE
r
l>
o
CAS
WE
CAS3
-
RAS
RAS
B3
C
:0
DE
RAS3
CAS
..
WE,/
B6
--
--
RAS2
CAS2
•
-,,~
",-
RAS
h
I
'.4
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
C
MICRON
1-·
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
'"'"'"w"""
PIN DESCRIPTIONS
•
PIN NUMBERS
SYMBOL
TYPE
22,26,65,69
RASO,RAS2
RAS1,RAS3
Input
Row-Address Strobe: RAS is used to latch the rowaddress. Two RAS inputs allow for a single x32 bank or
two x16 banks.
23,24,66,68
CASO-CAS3
Input
Column-Address Strobe: CAS is used to latch the
column-address, enable the DRAM output buffers and
strobe the data inputs on WRITE cycles. Four CAS
inputs allow byte access control for any memory bank
configuration.
70
WE
Input
Write Enable: WE is the READtWRITE control for the DO
pins. If WE is LOW prior to CAS going LOW, the access
is a WRiTE cycie. if WE is HIGH during the CAS LOW
transition, the access is a READ cycle .
Address Inputs: These inputs are multiplexed
and clocked by RAS and CAS.
I
I
I
DESCRIPTION
13,57,14,58,16,59,
18,60,19,61
AO-A9
Input
C
:D
2-8, 10, 34, 36,
38-43, 46-53,
80-87
DOO-D031
Input!
Output
o
71, 28, 72, 29,
74,30,75,76
PD1-PD8
-
Presence-Detect: These pins are read by the
host system and tell the system the card's personality.
They will be either left floating (NC) or grounded (Vss).
NC
-
C
9,11,12,15,17,20,21,
25,27,31,32,33,35,37,
54,55,62,64,65,69,77,
78, 79
No Connect: These pins should be left unconnected
(reserved for future use).
Pins 12, 31-33, 54,77-79 reserved for x36/x40 DOs.
Pins 11, 17, 25, 35 reserved for 3.3V Vcc.
Pin 55 reserved for x40 OE.
9,15,27,37
Vee
Supply
Power Supply: +5V ±5%
1, 44, 45, 56,
63,67,73,88
Vss
Supply
Ground
»
S
»
:D
MT8oasCI32H(S), MT16D88C232H(S)
DC02.pm5 - Rev. 2195
Data 1/0: For WRITE cycles, DOO-D031 act as
inputs to the addressed DRAM location. BYTE
WRITEs may be performed by using the corresponding
CAS select. For READ access cycles, DOO-D031 act as
outputs for the addressed DRAM location.
6-20
Micron Technology, Inc., reserves the right to change produds or specifications without notice.
©1995,MlcronTechnology. Inc.
MIC:RON
1-·
"'""'c,,""
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
FUNCTIONAL DESCRIPTION
TheMT8D88C132H(S) andMT16D88C232H(S) comprise
a family of DRAM cards organized in x32-bit memory
arrays (RASO = RAS2). They also may be configured as x16bit memory arrays provided the corresponding DQs on the
host are connected and memory bank control procedures
are implemented by interleaving both RAS lines.
Most x32-bit applications use the same signal to control
the CAS inputs. RASO and RAS1 control the lower 16 bits
and RAS2 and RAS3 control the upper 16 bits to obtain a x32
memory array. For x16 applications, the corresponding DQ
and CAS pins must be connected (DQO to DQ15, DQ1 to
DQ16 and so forth, CASO to CAS2 and CAS1 toCAS3). Each
RAS is then a bank select for the x16 memory organizations.
FAST PAGE MODE operation allows faster data operations (READ or WRITE) within a row-address-defined
(AO -A9) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed-in by CAS. CAS
may be toggled-in by holding RAS LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning RAS HIGH terminates the FAST PAGE
MODE operation. Returning RAS and CAS HIGH terminates a memory cycle and decreases chip current to a
reduced standby level. Also, the chip is preconditioned for
the next cycle during the RAS HIGH time.
REFRESH
DRAM OPERATION
An optional SELF REFRESH mode is also available. The •
"S" version allows the user the choice of a fully static lowpower data retention mode, or a dynamic refresh mode at
the extended refresh period.
The optional SELF REFRESH feature is initiated by
performing a CBR REFRESH cycle and holding RAS LOW -.....
for the specified tRASS. Additionally, the "S" version al- ~
lows for an extended refresh rate of 125j.ls per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby mode. _ _
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum time oftRPS (~tRC). This delay allows
for the completion of any internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all rows must be
refreshed within 300j.ls prior to the resumption of normal
operation.
DRAM REFRESH
Memory cell data is retained in its correct state by maintaining power and executing any RAS cycle (READ,
WRlTE) or RAS refresh cycle (RAS ONLY, CBR, extended
CBR or HIDDEN) so that all combinations of RAS addresses
(AO-A9) are executed at least every tREF, regardless of
sequence. The CBR REFRESH cycle will invoke the internal
refresh counter for automatic RAS addressing.
The implied method of choice for refreshing the memory
card is the extended CBR cycle. This is a very low-current,
data retention mode made possible by using the CBR REFRESH cycle over the extended refresh range (IcC7).
The memory card may be used with the other refresh
modes common to standard DRAMs. This allows the
memory card to be used on existing systems that do not
utilize the extended CBR REFRESH cycle. However, the
memory card will draw more current in the standby mode.
C
JJ
s:::
0
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JJ
C
DRAM READ AND WRITE CYCLES
During READ or WRITE cycles, each bit is uniquely
addressed through the 20 address bits, which are entered 10
bits (AO -A9) at a time. RAS is used to latch the first 10 bits,
and CAS latches the latter 10 bits. READ or WRITE cycles
are selected with the WE input. A logic HIGH on WE
dictates READ mode while a logic LOW on WE dictates
WRlTE mode. During a WRlTE cycle, data-in (D) is latched
by the falling edge of CAS. WE must fall prior to CAS
(EARLY WRlTE). The data inputs and data outputs are
routed through pins using common I/O and pin direction
is controlled by WE.
MT8D88C132H(S). MT16D88C232H(S)
De02.pmS - Rev. 2/95
PHYSICAL DESIGN
These Micron DRAM MiniCards are constructed with a
2-inch-Iong static dissipative plastic frame covered by metal
panels. Inside, thin small-outline package (TSOP) DRAMs
are mounted on an ultrathin printed circuit board. The
board is attached to a high-insertion, 88-pin receptacle
connector. The package is keyed to prevent improper installation, including insertion into other types of IC card sockets. The DRAM cards operate reliably up to 55°C.
6-21
Micron Technology. Inc., r&serves the right to change products or specifications without notica.
©1995, Micron Technology, Inc.
UIC:F=lCN
1-·
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
'''""cw"'"'
MEMORY TRUTH TABLE
•
C
JJ
»
ADDRESSES
IR
IC
DATA IN/OUT
000-0031
FUNCTION
1m"
"CAS"
WE""
Standby
H
H-X
X
X
X
High-Z
READ
L
L
H
ROW
COL
Data-Out
EARLY WRITE
L
L
L
ROW
COL
Data-In
READ WRITE
L
L
H-L
ROW
COL
Data-In
H-L
H
ROW
COL
Data-Out
Data-Out
FAST-PAGE-MODE
1st Cycle
L
READ
2nd Cycle
L
H->L
H
n/a
COL
FAST-PAGE-MODE
1st Cycle
L
H-L
L
ROW
COL
Data-In
EARLy~\AJRITE
2nd Cycle
L
H~L
L
nia
COL
Data-In
FAST-PAGE-MODE
1st Cycle
L
H-L
H-L
ROW
COL
Data-Out
L
H-L
H-L
n/a
COL
Data-Out
L
H
X
ROW
n/a
High-Z
H
ROW
COL
Data-Out
READ-WRITE
2nd Cycle
RAS-ONLY REFRESH
HIDDEN
READ
L-H-L
L
REFRESH
WRITE
L-H-L
L
L
ROW
COL
Data-In
CBR REFRESH
H-L
L
H
X
X
High-Z
SELF REFRESH (S version)
H-L
L
H
X
X
High-Z
s:
o PRESENCE-DETECT TRUTH TABLE
~~~==~~~~~~~~~~~~~
C
Refresh Control
NOTE:
Vss = ground.
MT8D88CI32H(S), MT16D88C232H(S)
DCOZ.pm5 - Rev. 2/95
6-22
Micron Technology, Inc., reserves the righl to change products or specifIcalionswithoutnotice.
©1995, Micron Technology, Inc
UICRON
1-·
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
"''''"""''''
'Stresses greater than those listed under" Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee Supply Relative to Vss ........... -1.0V to +7V
Operating Temperature TA (ambient) .............. O°C to 55°C
Storage Temperature ..................................... -40°C to +70°C
Power Dissipation ............................................................. 8W
Short Circuit Output Current ..................................... 50mA
Card Insertions (connector's life cycle) ..................... 10,000
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 4, 6, 7) (O°C :s; TA :s; 55°C; Vcc = +5V ±5%)
PARAMETER/CONDITION
Supply Voltage
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
SYMBOL
MIN
MAX
Vcc
4.75
5.25
UNITS
V
VIH
2.4
Vcc+1
V
VIL
-1.0
O.S
V
INPUT LEAKAGE CURRENT
RASO-RAS3
111
-S
8
Il A
Any input: OV :s; VIN :s; 6.5V
AO-A9, WE
1i2
-10
10
Il A
(All other pins not under test =OV) for each package input
CASO-CAS3
1i3
-S
8
Il A
OUTPUT LEAKAGE CURRENT
(0 is disabled, OV :s; VOUT :s; 5.5V) for each package ihput
000-0031
loz
-20
20
IlA
VOH
2.4
OUTPUT LEVELS
Output High Voltage (lOUT =-5 mAl
Output Low Voltage (lOUT =4.2 mAl
VOL
NOTES
C
::D
»
29
V
0.4
•
V
3:
o
»
::D
C
MT8D88C132H{S), MT16D88C232H(S)
DC02.pmS - Rev. 2195
6-23
Micron Technology, Inc., reserves the right to cha~ge products or specifications without nolice.
©1995, Micron Technology, Inc.
I'IIIC:RCN
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
"'""'''''"'
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes· 1 , 6 7) (O°C <
- TA <
- 55°C·, Vcc - +5V +5%)
MAX
SYMBOL
PARAMETER/CONDITION
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC =IRC [MIND
l>
s:
l>
:D
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC = IRC [MIND
Iccs
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC
Icc6
=IRC [MIND
REFRESH CURRENT: SELF (S version only)
Average power supply current; CBR cycling with
RAS ~ IRASS (MIN) and CAS held LOW; WE = Vcc-0.2V; AO-A9
and DIN = Vcc - 0.2V or 0.2V (DIN may be left open)
C
880
800
8MB
896
816
4MB
8MB
16
32
16
32
4MB
640
560
8MB
656
576
4MB
8MB
1.6
3.2
1.6
3.2
Icc?
Iccs
(S only)
4MB
880
800
8MB
896
816
4MB
880
800
8MB
896
816
4MB
2.4
2.4
8MB
4.8
4.8
4MB
2.4
2.4
8MB
4.8
4.8
CAPACITANCE
I
I
PARAMETER
UNITS NOTES
3,4,27
mA
mA
Icc4
REFRESH CURRENT: Extended CBR
Average power supply current during extended,CBR; CAS = 0.2V
orCBR cycling; RAS =IRAS (MIN); IRC = 125f!~; WE = Vcc-0.2V;
AO-A9 and DO = Vcc -0.2V or 0.2V (DO may be left open)
o
4MB
ICC3
STANDBY CURRENT: (CMOS)
(RAS = CAS = Other Inputs = Vcc -0.2V)
:D
-7
mA
Icc2
OPERATING CURRENT: FAST PAGE MODE
Average povv'er supply current
(RAS = VIL, CAS, Address Cycling: IpC =IpC [MIND
C
-6
Icct
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
•
SIZE
3,4,27
mA
mA
3,27
mA
3, 5
mA
3,5
mA
5,29
MAX
[
[
[
SYMBOL
4MB
8MB
UNITS
NOTES
2
Input Capacitance: CASO-CAS3
Cit
17
32
pF
Input Capacitance: WE
CI2
66
66
pF
2
Input Capacitance: RASO-RAS3
CI3
34
34
pF
2
InpuVOutput Capacitance: 000-0031
CIO
10
18
pF
2
Input Capacitance: Addresses
CI3
51
90
pF
2
MT8D88C132H{S), MT16088C232H(S)
DC02.pm5- Rav. 2195
6-24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
UII::::I=ICN
1-·
"'""'C"",,,
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (ODC 0;; TAO;; 55 DC; Vee = +5V ±5%)
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time entering SELF REFRESH
CAS hold time (CBR REFRESH)
CAS to output in low-Z
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output buffer turn-off delay
FAST-PAGE-MODE READ or WRITE cycle time
Access time from RAS
RAS to column-address delay lime
Row-address hold time
Column-address to RAS lead time
RAS pulse width
RAS pulse width (FAST PAGE MODE)
RAS pulse width entering SELF REFRESH
MT8D88C132H(S), MT16D88C232H(S)
DC02.pm5 - Rev. 2195
-7
-6
SYM
tAA
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCHD
tCHR
tClZ
tcp
tCPA
tCRP
MIN
45
0
0
15
10
30
60
60
100
6-25
UNITS
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
10,000
15
20
10
10
3
10
35
tRAC
tRAD
tRAH
tRAl
tRAS
tRASP
tRASS
MAX
50
0
0
15
10
15
10
10
3
10
tOFF
tpc
tDHR
tDS
MIN
30
10
60
10
15
10
45
0
3
35
tCSH
tCSR
tCWl
tDH
MAX
15
60
30
10,000
100,000
10,000
40
10
70
10
20
15
55
0
3
40
15
10
35
70
70
100
20
70
35
10,000
100,000
IlS
NOTES
15
28
5
26
16
•
C
5
24
24
20,26
14
18
28
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
::D
»
s::
o
»
::D
C
1'41C:I=ICN
,""","00,,"'
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (DOC $; TA$; 55°C; Vee
AC CHARACTERISTICS
PARAMETER
Random READ or WRITE cycle time
RAS to CAS" delay time
C
:D
»
:s:
o
»
:D
MIN
tRC
110
20
tRCD
Read command setup time
Refresh period (1,024 cycles)
RAS precharge time
tREF
tRP
RAS to CAS precharge time
RAS precharge time exiting SELF REFRESH
tRPC
Read command hold time (referenced to RAS)
tRRH
RAS hold time
tRSH
Write command to RAS lead time
Transition time (rise or fall)
Write command hold time
tRWL
tT
tWCH
Write command hold time (referenced to RAS)
tWCR
WE command setup time
twcs
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
·7
·6
SYM
tRCH
tRCS
Read command hold time (referenced to CAS)
•
=+5V ±5%)
tRPS
twp
tWRH
tWRP
MAX
MIN
45
130
20
MAX
UNITS
NOTES
50
ns
ns
17
19
0
0
ns
0
0
ns
ms
128
128
ns
40
0
110
50
0
130
ns
ns
28
0
15
15
3
10
45
0
10
10
10
0
ns
19
20
20
ns
ns
50
3
15
50
ns
ns
55
0
ns
15
ns
10
10
ns
ns
ns
22
22
C
MT8088C132H(S), MT16D88C232H(S)
DC02.pm5 - Rev. 2/95
6-26
Micron Technology, Inc., reseIV9S the right to change products or specifications without notice
©1995, Micron Technology. Inc
MICRON
1-·
"'""""""
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
NOTES
1. All voltages referenced to Vss.
2. This parameter is sampled. Capacitance is measured
using MIL-STD-883C, Method 3012.1. Vee = +5V ±5%;
f= 1 MHz.
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outTJuts open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100J,ls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
8. AC characteristics assume IT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VlH and VIL (or between VIL
and VlH).
10. In addition to meeting the transition rate specification, all input signals must transit between VlH and
VIL (or between VIL and VlH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and lOOpF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD ~ IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
MT8D88C132H(S). MT16D88C232H(S)
DC02.pm5 ~ Rev. 2195
17. Operation within the IRCD (MAX) limit ensures that
IRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by ICAe.
18. Operation within the IRAD (MAX) limit ensures that
IRCD (MAX) can be met. lRAD (MAX) is specified as
a reference point only; if IRAD is greater than the
specified IRAD (MAX) limit, access time is controlled
exclusively by IAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. toFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.
22. twTS and twTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). Thl'sl' two
parameters are the inverse of tWRI' and tWRl1 in lhl'
CBR REFRESH cycle.
23. The maximum current ratings are based on till'
memory operating or being refreshed in the x:l2
mode. The stated maximums may be reducl'd by 0Ill'half when used in the x16 mode.
24. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
25. LATE WRITE, READ WRITE or READ-MODIFYWRITE cycles are not available due to OE being tied
permanently LOW on all 4 Meg DRAMs.
26. The 3ns minimum is a parameter guaranteed by
design.
27. Column-address changed once each cycle.
28. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
29.4MB version is half of values shown.
6·27
Micron Technology, !nc., reserves the right to change products or specifiCations without notice.
©1995, Micron Technology, Inc.
•
C
JJ
l>
s:
o
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JJ
C
MIC:RON
1-·
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
"'"",'OG'''O
READ CYCLE
tAAS
:1
1
'RP
\
tCSH
'I
IRSH
:-'
I~
I'
'AR
'RAD
~I
ROW
LL.LLL/
•
s:
'Ase
~
I
Y
I
--l
COLUMN
,I
tRAL -)
tCAH
~!
r
Ric: 1//tiIL!///////!;;
I
'ReH
/
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W#/#/&1/#$/4
C
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.(
teAs
IReD
ICRP
1
tRRH
DO
~blr----J
~:gr ::::-------OPEN-----------<~~'!!.VA='-'LlD'.':DA~TA~r--OPEN---
o
EARLY WRITE CYCLE
l>
::D
C
d'
'eRP
I~~I
~~l--L-L--~n~~~~nn7A
MTS088C132H(S), MT16D88C232H(S)
DC02.pm5 - Rev. 2195
6-28
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, Jnc.
MICRON
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
~,"
1-·
FAST-PAGE-MODE READ CYCLE
I______________________~----~'AA~SP----------------------------~~
•
C
::D
»
s:
o
»
::D
FAST-PAGE-MODE EARLY-WRITE CYCLE
C
I~,~---"'C,,,S,,-,H__-;-______--:-_ _ _
'I
I". teRP •
CAS
~:r
tRCD.
=---.!
,
v
•
•
tpc
•
I~''''''''::'C'-P_~'~II~,,......::le,,,AS'--~'~li :.. tcp
~
vir 7/;0t
~
'AAD
:'AAH"I
'AR
WI/,9i
~
twcs
I•
•
I·.'ASC,
~~
KlIIIIIII'&{
COLUMN
I
'ewL
I
'WCR
~
II~
~11.'CAH"r
,leAH"1
rrrr~
COLUMN
VIIIIIII;0
'ewL
::~H
~,
'I
I
r
W/;//;//////;X
COLUMN
II
'CP
!
'RAL
,leAH,
I
teAs
~
I' I '
'~
~
ROW
••
t.-----------,I
1\
I• .'ASR,
ADDR
teAS
'CWL' ,II
ROW
'----
~IIII~
WE ~:~
'77-;'7T]'7N'7T]'7T.'7T.>7
I
,
II
,
I
tDHR.!
VALID DATA
MT8DBBC132H(S). MT16D88C232H(S)
0C02.pm5 - Rev. 2195
6-29
~
DON'T CARE
~
UNDEFINEC,
Micron Te<:hnology, tnc., reserves the right 10 change products or specifications without notice.
@1995,MlcrohTechnokigy,lnc.
MICRON
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
"~"
1-·
RAS-ONLY REFRESH CYCLE
(WE = DON'T CARE)
'RC
_
~:r ~=:J
CAS
~
.:l
.
~<11'-------------'.
b '------'RAB
~:r
RAe
'CRP
'RPC
'ASR
'RAH
~:r _-~RO'-W--~;/'//ff/$!ff//$$$;/'$j'!$;/'/;JXr---RO-W- -
ADDR
DQ
. 'RP
~gt
II
-:----------OPEN----------
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
c
::D
»
s:
tRASP
-
V,H - - - - - - . , .
RAS
VIL -
r---------------:-'A-SH--1
o
'PC 11--"""'----1
'O$H
»
::D
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ADDR
~:~
~~~
_
_.~r~~~I_,-~~~=·-~I~I~~~~
II
II
1_---7-"'A"""O$'-
WE
o
I
~i~::..
'AWL
'wP
~I~
I
I
I
I
I·
~I~
:r :J/II//II/I;1IMMJZlM,wd'//,w/M/MIII//llj "~M,.IwMM//!i0''@
~s
~IIE1
, FF
~
VALID
OPEN
I
~,
OPEN----
'M
I
NOTE:
'RAC
~
QON'TCARE
~
UNDEFINED
1. Do not drive data prior to tristate.
MTaD88C132H(S), MT.16D88C232H(S)
DC02.pm5 - Rev. 2195
6-30
Micron Technology, Inc., reserves the right 10 change products or speclflcatJons without notice.
Cl1995, Micron Technology,lnc.
MICRON
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
m~"ococ""
1-·
CBR REFRESH CYCLE
(Addresses = DON'T CARE)
.
~~
..
tRP
tRAS
..-'
tRPC
=:J:;:~ .""" . . 2
DQ
~:~_
-
WE
II
..
tRAS
•~ I
~~~ ~t
II
II
tWRP
tRP
1
tCHR
CAS
.
OPEN--i-i----------
tWRH
tWRP
II
tWRH
~:~ 4!1/J//;1/;1&-- -Wffl/$/$/!;@,;$- -tw/!I/I$//$/I/M;/$//h
.
.
.---.J
tRP
..
..
tRAS
tRP
..
::D
:l=-
s:
tRAS
o
.1
l>
::D
tRPC
~
DO
tWRP
WE
.
1251..15
.
tCHR
II
II
2
C
~~~~~
II
OPEN--'-'---------tWRH
tWRP
II
tWRH
~:~ !ij///I//I//$-- --~I//I/#$$$n- -~////$//;I$ffm////////m
tz2 DON'T CARE
~
MTBD68C132H(S), MT16D88C232H(S)
DC02.pm5 - Rev. 2195
6-31
•
C
EXTENDED CBR REFRESH CYCLE
(Addresses = DON'T CARE)
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology, Inc.
I'IIIC:F=lCN
MT8D88C132H(S), MT16D88C232H(S)
4MB, 8MB DRAM CARDS
,
,,~'"
HIDDEN REFRESH CYCLE 21
(WE = HIGH)
(REFRESH)
tRAS
•
C
:D
»
s:
ADDR
DO
o
SELF REFRESH CYCLE (S VERSION ONLY)
(Addresses = DON'T CARE)
»
:D
c
NOTE 1
:: :~ ;;~!M#Iff#!ff#ff#;:;;Ar~
DO
WE
NOTE:
VOHVOL
.
' ..0 0
II
·11
~
~:~ ::1f!I!!//////)
twRH.
(())
OPEN.
...._-
IIII
~
~W////$#ff//////I!!II!!////I!!/$//;)
twRH.
~//I!!//I!!////~
rz2l
DON'T CARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied. a complete burst of all rows should be executed.
MT8D88CI32H(S), MT16088C232ti(S)
DC02.pm5 - Rev. 2195
6-32
Micron Technology, Inc., reserves the right to change products or speclflcaUons without nollce.
@1995,MicronTechnology,lnc.
PRELIMINARY
MIC:RON
1-·
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
","",COO""
4,8,16*,32* MEGABYTES
DRAM CARD
1 MEG, 2 MEG, 4 MEG, 8 MEG x 32;
3.3V, FAST PAGE MODE,
OPTIONAL SELF REFRESH
//,
FEATURES
PIN ASSIGNMENT (End View)
88-Pin Card (DF-3)
• JEDEC-standard 88-pin DRAM card
• Polarized receptacle connector
• Industry-standard DRAM FAST PAGE MODE
operation
• High reliability, gold-plated connector
• All outputs fully TTL-compatible
• All inputs buffered except RAS inputs
• Multiple RAS inputs for x16 or x32 selectability
• Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN; optional SELF REFRESH mode
• FAST PAGE MODE (FPM) access cycle
• Single +3.3V ±O.3V power supply
• Lowpower
• Extended Refresh
OPTIONS
%
~
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
-7
-8
Blank
S
KEY TIMING PARAMETERS
SPEED
tRC
tRAC
tpc
tAA
tCAC
tRP
-6
-7
-8
110ns
l30ns
l50ns
60ns
70ns
80ns
35ns
40ns
45ns
4lns
46ns
5lns
26ns
3lns
3lns
40ns
50ns
60ns
VALID PART NUMBERS
PART NUMBER
MT8D88C132V-xx
MT8D88C132V-xx S
MT16D88C232V -xx
MT16D88C232V -xx S
MT8D88C432V-xx
MT8D88C432V-xx S
MT16D88C832V-xx
MT16D88C832V-xx S
DESCRIPTION
1 Megx32
1 Meg x 32,
2Megx32
2 Meg x 32,
4Megx32
4 Meg x 32,
8Megx32
8 Meg x 32,
1
©©©©©©©©©©©©©©©©©©©©©©©©©©©©@©©©©©©©©©©©©©©©
©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©©
88
-6
• Refresh
Extended Refresh
SELF REFRESH
. /
.r:
44
MARKING
• Timing
60ns access
70ns access
80ns access
~
//.
/
/
/.
SELF REFRESH
SELF REFRESH
SELF REFRESH
SELF REFRESH
~
45
4MB
8MB 16MB 32MB
Vss
-->
-->
-->
000
001
-->
002
003
-->
->
004
-->
-->
005
-->
->
006
->
->
NC
->
->
007
->
-->
->
3.3VVcc -->
->
NC
-->
-->
-->
AO
-->
->
->
A2
-->
-->
-->
NC
-->
-->
-->
A4
-->
-->
3.3VVcc -->
->
A6
-->
A8
-->
->
NC
AID
-->
-->
NC
RASO
->
-->
"CASO
-->
->
CJl.Sl -->
3.3VVcc -->
RAS2
-->
-->
NC
->
P02
-->
-->
P04
-->
->
P06
-->
->
->
NC
-->
-->
NC
-->
NC
-->
->
008
->
-->
-->
3.3VVcc ->
009
->
->
-->
NC
->
0010
-->
->
-->
0011
-->
->
0012
->
-->
-->
0013
-->
->
->
OQ14
->
->
-->
0015
->
-->
Vss
-->
-->
->
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
.... ....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
....
PIN #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
4111B
Vss
0016
0017
0018
0019
0020
0021
0022
0023
NC
NC
Vss
Al
A3
A5
A7
A9
NC
Vss
NC
NC
l:i\S2
Vss
...Q\S3
NC
WE"
PDl
PD3
Vss
PD5
PD7
PD8
NC
NC
NC
0024
0025
0026
0027
0028
0029
OQ30
OQ31
Vss
8MB
16MB 32MB
....
....
....
)
)
....
)
,
,
...,
)
...,
->
->
....
->
....
-->
->
-->
->
->
-->
....
-->
....
....
RAS1
....
->
-->
RAS3
....
....
....
-->
....
-->
-->
->
->
....
->
->
->
....
-->
->
-->
-->
....
....
....
-->
->
->
....
....
-->
-->
-->
....
....
)
.-:~
!)
-->
....
....
-->
....
->
-->
-->
-->
....
-->
.... ....
....
-->
NC
-->
-->
-->
-->
RAS1
-->
....
....
....
NC
-->
RAS3
....
-->
-->
-->
-->
->
....
-->
....
-->
....
-->
....
....
-->
-->
....
-->
....
....
-->
-->
-->
->
->
->
->
-->
->
-->
->
-->
->
-->
-->
....
....
'Contact factory for availability.
MT8D88CI32V/432V(Sj, MT16D88C232V/832V(S)
DC03.pm5 - Rev. 2/95
6-33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MlcronTechnology, Inc.
•
c
:c
»
3:
o
»
:c
c
PRELIMINARY
MIC:I=ICN
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
1-·,
GENERAL DESCRIPTION
•
The MT8D88C132V /432V(S) and MTl6D88C232V /
832V(S) comprise a family ofJEDEC-standard DRAM cards
organized in x32-bit memory arrays. The card~ may also be
configured as xl6-bit memory arrays, provided the corresponding DQs on the host system are made common, and
memory bank control procedures are implemented. Four
separate CAS inputs allow byte accesses.
These 3.3V cards are designed for low-power operation
using 3.3V, low-power, extended refresh DRAMs. Standard component DRAM refresh modes are supported as
well.
Multiple RAS inputs conserve power by allowing individual bank selection. In the x32 organization, the memory
is a single array that maybe divided into four separate bytes.
In the x16 organization, up to two banks, each with 2
separate bytes, may be independently selected. One bank is
activated by each RAS selection; the others not selected
remain in standby mode, drawing minimum power.
Eight presence-detect pins may be read by the host to
identify the card's organization, number of banks, access
time and refresh operation. These extensive presence-detect functions allow systems to take full advantage of the
advanced power-saving features.
These Micron DRAM Cards are built with 3.370-inchlong static dissipative plastic frames covered by metal
panels. Packages containing 88-pin receptacle c<;mnectors
are keyed to prevent improper installation or insertion into
other types of IC card sockets.
FUNCTIONAL BLOCK DIAGRAM
(4MB - MT8D88C132V, 16MB - MT8D88C432V)
C
lJ
RASO
l>
s:
CASO
D~----------~
DQO
o
D07
l>
lJ
C
DOS
D015
D016
D023
D024
0031
NOTE:
=
1. 81 through 84 x8 memory blocks.
2. D =74AC11244 line drivers.
MT8D88C132Vi432V(S), MT16D88C232V1832V(S)
DC03.pm5 - Rev. 2195
6-34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995,MicronTechnology, Inc.
PRELIMINARY
MICRON
1-·
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
0" '"
FUNCTIONAL BLOCK DIAGRAM
(8MB - MT16D88C232V, 32MB - MT16D88C832V)
RASO
RAS1
RAS
CASO
CAS·
D
•
••
-
-=
RAS
CAS1
•
RAS
CAS
CAS
•
••
-
RAS3
RAS2
-=
•
••
C
-
RAS
RAS
CAS3
CAS
CAS
•
••
WE
ADDRESS
NOTE:
=
1. 81 through 88 x8 memory blocks.
2. D = 74AC11244 line drivers.
MTBD88C132V1432V(S), MT16D88C232V!832V(S)
DC03.pm5- Rev. 2195
6-35
3:
»
:II
CAS
CAS
»
0
RAS
RAS
CAS2
C
:II
Micron Technology, Inc., reserves the right to change P.toducls QrspedHcatiOflS without notice.
©1'995, Micron 1;echnology, 11)0.
PRELIMINARY
MICRON
1-·
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
""
PIN DESCRIPTIONS
II
c
:D
»
s:
o
»
:D
C
DESCRIPTION
PIN NUMBERS
SYMBOL
TYPE
22,26,65,69
RASO,RAS2
RAS1, RAS3
Input
Row-Address Strobe: RAS is used to latch the rowaddress. Two RAS inputs allow for a single x32 bank or
two x16 banks.
23,24,66,68
CASO-CAS3
Input
Column-Address Strobe: CAS is used to latch the
column-address, enable the DRAM output buffers and
strobe the data inputs on WRITE cycles. Four CAS
inputs allow byte access control for any memory bank
configuration.
70
WE
Input
Write Enable: WE is the READIWRITE control for the DO
pins. If WE is LOW prior to CAS going LOW, the access
is a WRITE cycle. If WE is HIGH during the CAS LOW
transition, the access is a READ cycle.
13,57,14,58,16,59,
18,60,19,61
AO-Al0
Input
Address Inputs: These inputs are multiplexed
and clocked by RAS and CAS.
2-8, 10, 34, 36,
38-43, 46-53,
80-87
000-0031
Input!
Output
71, 28, 72, 29,
74,30,75,76
PD1-PD8
-
Presence-Detect: These pins are read by the
host system and tell the system the card's personality.
They will be either left floating (NC) or grounded (Vss).
9, 12, 15, 21,27,
31,32,33,37,54,55,
62,64,65,69,77,78,
79
NC
-
No Connect: These pins should be left unconnected
(reserved for future use).
Pins 12, 31-33, 54, 77-79 reserved for x36/x40 DOs.
Pins 9, 15, 27, 37 reserved for 5V Vcc.
Pin 55 reserved for x40 OE.
11, 17, 25, 35
Vcc
Supply
Power Supply: +3.3V ±0.3V
1, 44, 45, 56,
63,67,73,88
Vss
Supply
Ground
MTBD88C132V/432V(S), MT16D88C232VI832V(S)
DC03.pm5-Rev.2/95
Data I/O: For WRITE cycles, 000-0031 act as
inputs to the addressed DRAM location. BYTE
WRITEs may be performed by using the corresponding
CAS select. For READ access cycles, 000-0031 act as
outputs for the addressed DRAM location.
6-36
Micron Technology. Inc., reserves the right to change products or specifications without notice.
@1995,MlcronTechnoiogy, Inc.
PRELIMINARY
I"IIC:I=ICN
"'"",coo,,",
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
FUNCTIONAL DESCRIPTION
The MT8D88C132V /432V(S) and MT16D88C232V /
832V(S) comprise a family of DRAM cards organized in
x32-bit memory arrays (RASO = RAS2). They also may be
configured as x16-bit memory arrays provided the corresponding DQs on the host are connected and memory bank
control procedures are implemented by interleaving both
RASlines.
Most x32-bit applications use the same signal to control
the CAS inputs. RASO and RAS1 control the lower 16 bits
and RAS2 and RAS3 control the upper 16 bits to obtain a x32
memory array. For x16 applications, the corresponding DQ
and CAS pins must be connected (DQO to DQ15, DQ1 to
DQ16 and so forth, CASO to CAS2 and CAS 1 to CAS3). Each
RAS is then a bank select for the x16 memory organizations.
outputs are routed through pins using common 1/ 0 and pin
direction is controlled by WE.
FAST PAGE MODE operation allows faster data operations (READ or WRITE) within a row-ad dress-defined (AOA9/ AID) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed-in by CAS. CAS
may be toggled-in by holding RAS LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning RAS HIGH terminates the FAST PAGE
MODE operation. Returning RAS and CAS HIGH terminates a memory cycle and decreases chip current to a
reduced standby leveL Also, the chip is preconditioned for
the next cycle during the RAS HIGH time.
DRAM OPERATION
REFRESH
DRAM REFRESH
Memory cell data is retained in its correct state by maintaining power and executing any RAS cycle (READ,
WRITE) or RAS refresh cycle (RAS ONLY, CBR, extended
CBR or HIDDEN) so that all combinations of RAS addresses (AO-A9 / AlO) are executed at least every tREF,
regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS addressing.
The implied method of choice for refreshing the memory
card is the extended CBR cycle. This is a very low-current,
data retention mode made possible by using the CBR REFRESH cycle over the extended refresh range (Icc7).
The memory card may be used with the other refresh
modes common to standard DRAMS. This allows the
memory card to be used on existing systems that do not
utilize the extended CBR REFRESH cycle. However, the
memory card will draw more current in the standby mode.
C
:xl
s:
0
l>
C
DRAM READ AND WRITE CYCLES
During READ or WRITE. cycles, each bit is uniquely
addressed through the 20/22 address bits, which are entered 10/11 bits (AO-A9/ A10)ata time. RAS is used to latch
the first 10/11 bits, and CAS latches the latter 10/11 bits.
READ or WRITE cycles are selected with the WE input. A
logic HIGH on WE dictates READ mode while a logic LOW
on WE dictates WRITE mode. During a WRITE cycle, datain (D) is latched by the falling edge of CAS. WE must fall
prior to CAS (EARLY WRITE). The data inputs and data
MT8D88C132Vf432V(S}. MT16D88C232Vi832V(S)
DC03.pm5 - Rev. 2195
-
An optional SELF REFRESH modeis also available. The
"S" version allows the user the choice of a fully static lowpower data retention mode, or a dynamic refresh mode at
the extended refresh period.
.....
The optional SELF REFRESH fl'ilturc b initiatt'd by ~
performing a CBR REFRESH cycle and holding lri\s"Low
for the specified !RASS. Additionally, the "S" version allows for an extended refresh rate of 125/-Ls per row if using
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby mode. _ _ ...
The SELF REFRESH mode is terminated by driving RAS ,.AJ
HIGH for a minimum time oftRPS (~tRC). This delay allows
. for the completion of any internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all rows must be
refreshed within 300/-Ls prior to the resumption of normal
operation.
PHYSICAL DESIGN
These Micron 3.3V DRAM Cards are constructed with a
3.370-inch long static dissipative plastic frame covered by
metal panels. Inside, thin small-outline package (TSOP)
DRAMs are mounted on an ultrathin printed circuit board.
The board is attached to a high-insertion, 88-pin receptacle
connector. The package is keyed to' prevent improper
installation, including insertion into other types of IC card
sockets. The DRAM cards operate reliably up to 55°C.
6-37
Micron Technology, inc., reserves the rlghllo change prodocts or specifications without notice.
©1995,MicronTechnology, Inc.
PRELIMINARY
I"IIC:I=ICN
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
"'"""00""
MEMORY TRUTH TABLE
ADDRESSES
'RAS'"
m
WE
Standby
H
H-X
X
X
X
High-Z
READ
L
L
H
ROW
COL
Data-Out
EARLY WRITE
L
L
L
ROW
COL
Data-In
READ WRITE
L
L
H-L
ROW
COL
Data-In
L
H-L
H
ROW
COL
Data-Out
FUNCTION
•
C
:IJ
l>
3:
~
DATA IN/OUT
IR
IC
000-0031
FAST-PAGE-MODE
1st Cycle
READ
2nd Cycle
L
H-L
H
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H-L
L
ROW
COL
Data-In
I EARLV-WRITE
"-11'-'1 ""'YVlv
')nrl ('\I",ln
L
H->L
L
n/a
COL
Data-in
FAST-PAGE-MODE
1st Cycle
L
H-L
H-L
ROW
COL
Data-Out
READ-WRITE
2nd Cycle
L
H-L
H-L
n/a
COL
Data-Out
L
H
X
ROW
n/a
High-Z
H
ROW
COL
Data-Out
RAS-ONLY REFRESH
HIDDEN
READ
L-H-L
L
REFRESH
WRITE
L-H-L
L
L
ROW
COL
Data-In
CSR REFRESH
H-L
L
H
X
X
High-Z
SELF REFRESH (S version)
H-L
L
H
X
X
High-Z
I
PRESENCE-DETECT TRUTH TABLE
~~----------------------------~----------------~
:IJ~~____~~~~~~__~~~~~~~~
C
tRAC Max
Refresh Control
NOTE:
Vss = ground.
MTB088C132V/432V(Sj, MT16D88C232V/832V(S)
DC03.pm5- Rev. 2/95
6-38
Micron Technology, Inc., reserves the right to change products or spectflcalions without notice.
©1995,MicronTechnology, Inc.
PRELIMINARY
MICRON
1-·
"'"","00,,",
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
'Stresses greater than those listed under"Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Vee Supply Relative to Vss ........ -l.OV to +4.5V
Operating Temperature TA (ambient) .............. O°C to 55°C
Storage Temperature ..................................... -40°C to +70°C
Power Dissipation ............................................................. 8W
Short Circuit Output Current ..................................... 50mA
Card Insertions (connector's life cycle) ..................... 10,000
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 4, 6, 7) (O°C
s T A S 55°C; Vcc =+3.3V ±0.3V)
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vcc
3.15
3.45
V
Input High (Logic 1) Voltage, all inputs
VIH
2.1
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
il1
-8
8
!-\A
PARAMETER/CONDITION
INPUT LEAKAGE CURRENT
Any input: OV S VIN S Vcc
(All other pins not under test =OV) for each package input
RASO-RAS3
Buffered
il2
-2
2
~IA
OUTPUT LEAKAGE CURRENT
(0 is disabled, OV S VOUT S Vcc) for each package input
000-0031
loz
-20
20
!-\A
VOH
2.0
OUTPUT LEVELS
Output High Voltage (lOUT =-2.0 mAl
Output Low Voltage (lOUT =2.0 mAl
VOL
NOTES
C
JJ
35
V
0.4
-
V
»
s:
o
»
JJ
C
MT8D88C132V/432V(S), MT16D88C232V1832V(S)
DC03.pm5 - Rev. 2/95
6-39
Micron Technology, Inc., reserves the right to change products or spectfications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
I"IIC:I=ICN
"'"'C"C""
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (O°C :s; T A :s; 55°C; Vcc= +3.3V ±0.3V)
PARAMETER/CONOITION
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
c
:c
-6
MAX
-7
4MB
8MB
16MB
32MB
640
648
960
968
560
568
880
888
480
488
4MB
8MB
16MB
32MB
8
16
8
16
8
16
8
16
8
16
4MB
8MB
16MB
32MB
480
488
720
728
400
408
640
648
320
328
4MB
8MB
16MB
32MB
4
8
4
8
4
8
4
8
4
8
mA
4MB
8MB
16MB
32MB
640
648
960
968
560
568
880
888
480
488
mA
3,30
4MB
8MB
16MB
32MB
640
648
960
968
560 480
568 488
880
888
mA
3,5
4MB
8MB
16MB
32MB
1.2
2.4
2.4
4.8
1.2
2.4
2.4
4.8
mA
3,5
4MB
Icca
8MB
(S only) 16MB
32MB
1.2
2.4
2.4
4.8
1.2
2.4
2.4
4.8
rnA
5, 31
UNITS
NOTES
Icct
STANDBY CURRENT: (TTL)
(RAS = CAS = VIH)
•
SIZE
SYMBOL
Icc2
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC = IpC [MIN])
Icc3
STANDBY CURRENT: (CMOS)
(RAS = CAS = Other Inputs = Vcc -0.2V)
Icc4
l>
s:
o
l>
:c
c
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH:. IRC = IRC [MIN])
Iccs
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
Icc6
REFRESH CURRENT: Extended CBR
Average power supply current during extended CBR; CAS = 0.2V
or CBR cycling; RAS = IRAS (MIN); IRC = 125j..lS; WE = Vcc -0.2V;
AO-AlO and DO = Vcc -0.2V or 0.2V (DO may be left open)
REFRESH CURRENT: SELF (S version only)
Average power supply current; CBR cyclinQ with
RAS ~ IRASS (MIN) and CAS held LOW; WE = Vcc-0.2V; AO-A10
and DIN = Vcc - 0.2V or 0.2V (DIN may be left open)
Icc?
CAPACITANCE
PARAMETER
SYMBOL
-8
UNITS NOTES
mA
3,4,30
-
mA
mA
3,4,30
-
-
-
1.2
2.4
2.4
4.8
1.2
2A
2.4
4.8
MAX
4,16MB 8, 32MB
Input Capacitance: CASO-CAS3
Cit
9
9
pF
2
Input Capacitance: WE
CI2
13
13
pF
2
Input Capacitance: RASO-RAS3
CI3
34
34
pF
2
Input/Output Capacitance: 000-0031
CIO
10
18
pF
2
Input Capacitance: Addresses
CI3
9
9
pF
2
MT8D88C132V/432V(Sj, MT16D88C232V1832V(S)
DCOg.pm5- Rev. 2/95
6-40
Micron Technology, Inc., reserves the right to change products or specifications without notjce.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
"'e"we,,"
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (ODC :s; T A:S; 55 DC; Vee
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
Column-address setup time
Row-address setup time
Access time from CAS
Column-address hold time
CAS pulse width
CAS hold time entering SELF REFRESH
CAS hold time (CBR REFRESH)
CAS to output in low-Z
CAS precharge time
Access time from CAS precharge
CAS to RAS precharge time
CAS hold time
CAS setup time (CBR REFRESH)
Write command to CAS lead time
Data-in hold time
Data-in hold time (referenced to RAS)
Data-in setup time
Output buffer turn-off delay
FAST-PAGE-MODE
READ or WRITE cycle time
=+3.3V ±0.3V)
-7
-6
SYM
tAA
tAR
tASC
tASR
tCAC
tCAH
tCAS
tCHD
tCHR
tClZ
tcp
tCPA
tCRP
tCSH
tCSR
tCWl
tDH
tDHR
tDS
tOFF
tpc
MIN
MAX
MIN
31
10,000
15
20
15
13
5
10
46
21
58
12
15
21
45
-2
5
35
26
UNITS
NOTES
51
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
24
23
25
15,25
25
10,000
31
15
20
15
13
5
10
51
21
68
12
20
26
55
-2
5
40
MAX
53
2
7
53
2
7
26
10
15
15
13
5
10
MIN
46
41
48
2
7
-8
MAX
31
10,000
56
21
78
12
20
26
60
-2
5
45
31
31
5,24
23,32
16
25
25
24
5, 23
25
24
20,27,32
•
C
:Xl
»
:s:
o
»
:Xl
C
MT8D88C132V/432V(S), MT16D88C232VJ832V(S)
DC03.pm5 - Rev. 2/95
6-41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
","",co,,,,,
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (DOC
•
C
:D
»
S
o
»
:D
C
S;
TA
S;
55°C; Vee
= +3.3V ±0.3V)
-7
-6
AC CHARACTERISTICS
PARAMETER
SYM
Access time from RAS
RAS to column-address delay time
tRAC
tRAD
MAX
60
19
13
70
24
46
70
10,000
80
10,000
ns
70
100,000
80
100
100,000
ns
MAX
13
Row-address hold time
tRAH
Column-address to RAS lead time
tRAL
8
41
RAS pulse width
tRAS
60
10,000
RAS pulse width (FAST PAGE MODE)
RAS pulse width entering SEU- REFRESH
Random READ or WRITE cycle time
tRASP
60
100
110
100,000
RAS to CAS delay time
tRCD
tRCH
18
34
Read command hold time (referenced to CAS)
Read command setup time
tRCS
2
Refresh period (1,024 cycles)
Refresh period (2,048 cycles)
tREF
tREF
tRP
RAS precharge time
RAS to CAS precharge time
tRASS
tRC
tRPC
tRPS
Read command hold time (referenced to RAS)
RAS hold time
tRRH
0
tRSH
tRWL
tT
26
26
Write command to RAS lead time
Write command hold time (referenced to RAS)
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
WE setup time (CBR REFRESH)
MT8D88CI32V!432V{S), MTI60B8C232V/832V(S)
DC03.pm5 - Rev. 2195
tWCH
100
130
39
18
3
26
twCR
twcs
twp
43
53
2
10
2
15
twRH
tWRP
8
12
8
12
6-42
NOTES
13
ns
ns
14
18,26
ns
24
ns
25
~s
18
49
[IS
17,26
2
ns
19,23
2
ns
23
ms
ms
34
33
128
128
ns
ns
0
50
31
ns
60
0
31
31
50
UNITS
80
29
128
128
50
0
130
3
21
MAX
150
2
2
40
MIN
8
51
128
128
RAS precharge time exiting SELF REFRESH
Transition time (rise or fall)
Write command hold time
8
2
0
110
-8
MIN
MIN
150
0
ns
ns
19
31
31
ns
ns
25
25
3
26
58
2
15
8
12
50
31
ns
25
ns
ns
24
ns
23
ns
ns
22,24
ns
22,23
Micron Technology, Inc., reserves the righllo change products or specifications withoul notice
©1995, Micron Technology, Inc.
PRELIMINARY
MIC:RON
1-·
"'~"OCO"'''OC
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
~"oTES
18. Operation within the IRAD (MAX) limit ensures that
IRCD (MAX) can be met. IRAD (MAX) is specified as
a reference point only; if lRAD is greater than the
specified IRAD (MAX) limit, access time is controlled
exclusively by IAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. IOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.
22. IwrS and twrH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverse of twRP and IWRH in the
CBR REFRESH cycle.
23. A +2ns timing skew from the DRAM to the DRAM
card resulted from the addition of line drivers.
24. A -2ns timing skew from the DRAM to till' DRAM
card resulted from the addition of line drivers.
25. A +11ns timing skew from the DRAM to the DRAM
card resulted from the addition of line drivers.
26. A -2ns (MIN) and a -llns (MAX) timing skew from
the DRAM to the DRAM card resulted from the
addition of line drivers.
27. A +2ns (MIN) and a +l1ns (MAX) timing skew from
the DRAM to the DRAM card resulted from the
addition of line drivers.
28. The maximum current ratings are based on the
memory operating or being refreshed in the x32
mode. The stated maximums may be reduced by onehalf when used in the x16 mode.
29. These parameters are referenced to CAS leading edge
in EARLY WRITE cycles.
30. Column-address changed once each cycle.
31. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
32. The 3ns minimum is a parameter guaranteed by
design.
33. 16MB and 32MB only.
34.4MB and 8MB only.
35.4MB is half of values shown.
All voltages referenced to Vss.
, This parameter is sampled. Vee = +3.3V ±0.3V;
f= 1 MHz.
\. Ice is dependent on cycle rates.
L Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
i. Enables on-chip refresh and address counters.
J. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of 100J..ls is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the IREF refresh requirement is
exceeded.
3. AC characteristics assume IT = 5ns.
~. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and lOOpF.
14. Assumes that IRCD < IRCD (MAX). If IRCD is greater
than the maximum recommended value shown in this
table, lRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD;:: IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data.cout buffer, CAS must be
pulsed HIGH for ICp.
17. Operation within the IRCD (MAX) limit ensures that
IRAe (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclusively by ICAe.
MT808aC132V/432V(S), MT16D88C232Vi832V(S)
DC03.pm5 - Rev. 2195
6-43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
C
::D
»
s::
o
l>
::D
C
PRELIMINARY
I'IIIC:I=ICN
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
","",we,,",
READ CYCLE
tRC
tRAS
RAS
tRP
VIH -
V1L _
tCSH
tRRH
IRSH
leAP
CAS
tCAS
tRCD
VIH VIL -
r-,wi
tAAD
-
ADDR
WE
VIH -
VIL _
ROW
:~ :~W!/IIIIIIIIII/h~//II
.,,~ ·1
I
I
I
I
i
C
lJ
:t>
tAA
tRAC
tCAC
:
DO
V 10H VIOL
tClZ
OPEN
;
~
.~
OPEN
VALID DATA
"!>YiY.
S
0
:t>
EARLY WRITE CYCLE
lJ
tRC
C
tRAS
RAS
V,H
Vil _
tRP
.1
1
tRCD
CAS
tAR
ADDR
V,H
VIL
ROW
I
I
twcs
WE
MT8D88C132V1432V{S), MT16D88C232V/832V{Sj
DC03.pm5 - Rev. 2/95
·1 I·
I I
6·44
tWGR
tWCH
twp
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specf/ications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MIC::RON
1-·
c,
U
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
K
FAST-PAGE-MODE READ CYCLE
----------------------------~I~~p----------------------------I~
ADDR
DO
C
::D
~:g~ -,.----------OPEN-----------1~)(~O------~~(]~)_--------.;~~
l>
3:
o
FAST-PAGE-MODE EARLY-WRITE CYCLE
l>
::D
C
MT8088C132V1~V(S),
DC03.pm5- Rev, 2195
MT16088C232VI832V{S) .
6-45
~
DON'TeARE
~
UNDEFINED
Micron Technology, Inc., reselV8S the right to cl1ange produds or specifications wilhOl,II notice.
c>1995. Micron Technology. Inc.
PRELIMINAR'I
r'l1C::I=ICN
me
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
'c" ,
RAS~ONL Y
REFRESH CYCLE
(WE = DON'T CARE)
_
CAS
ADDR
DO
~:t _~.
'"'
=-.
.~_ _ ~'RC_'Lb'RP
'RA_S
II
~:~ ~~
~ir
~gr
'ASR
• 'RAH
l'----_
b;/I$/I#/$$/I/1/1/1/1/1/1/1/1$/M~-RO-W- -
RCW
-'------------OPEN----------
•
FAST-PAGE-MODE READ-EARLY-WRITE CYCLE
c
(Pseudo READ-MODIFY-WRITE)
::c
»
s:
o
»
::c
~1_.
_ _'=RCD~
__
~-=~II
__~te~P_ _1
teAS
c
ADDR
~l~
-
COLUMN
COLUMN
I
I
WE
~it :::.77.7777777771,.,.,rr,7"7"k--:--~I-'-----;I----'
1
I
o
II
'CWL
11
'WP
II
I_--+-",'R"",-CS--I.
~II·'WCH:
I
I·
'RWL
'T7T77TTTT77T77T77777C777
I~
:~ :»'/ff,J'/,@//,@/#$//,@//#$/'@'@'@,J'ff/f~" !w,@//,@/,J'$/i1J2
~
~
'os
~
NbTE1
OPEN
1
NOTE:
I.
VALID
IO?~
'AA
'RAC
:
OPEN----
~
DON'T CARE
~
UNDEFINED
1. Do not drive data prior to tristate.
MT8D660132V/432V(S), MT1608BC232VI832V(S)
DC03.p1n5 - Rev. 2195
6-46
Micron Technology, Inc., reserves the ri{flt to change.products or speclflCations without notice.
@1995,MlcronTechnology,lnc.
PRELIMINARY
I"'IIE::RCN
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
,"~'ow"'"
CBR REFRESH CYCLE
(Addresses =DON'T CARE)
·
~~
..
tRP
RAS
tRPC
=:J:;:~~ . 2
II
~
DO
WE
~:~_
tWRP
II
..
~~~
tCHR
CAS
tRP
.J •
~CHR
tRAS
.~ I
1
OPEN_-;-;.-II_ _ _ _ _ _ __
tWRH
tWRP
II
tWRH
~:~ $/;l;l;l;/"j-- ---'_//;//;//;/#/#$- ---'V#$/;/;l$;lm;W'&J~
C
JJ
EXTENDED CBR REFRESH CYCLE
(Addresses =DON'T CARE)
·
..
·
.~
~
-.
tRP
tCSR
CAS
DO
~:~
WE
tCHR
II
tWRP
II
..
tRAS
=
-
.
125~s
2
tRP
..
tRAS
»
s:
o
»JJ
.1
C
~r~~
!CHR
1
OPEN--;-;.-II--------
tWRH
tWRP
II
tWRH
~:~ =W';/#/#j- -W/;//;/##;l/;///#U- -W;/#;l;l;l;l/$;l/;l/!/;l/h
MT8D88G132VJ432V(S), MT16088C232V!832V(3)
DC03.pm5 - Rev. 2/95
6-47
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the ngt>t to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
MT8D88C132V/432V(S), MT16D88C232V/832V(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
'"~'''oo,,'''
1-·
HIDDEN REFRESH CYCLE 21
(WE =HIGH)
(READ)
•
~tcLZ
C
:D
»
s:
(REFRESH)
DO
~:g~
:::----OPEN
'_I
'
. .
-
-tOFF
~ OPEN-
VALID DATA
,~
o
SELF REFRESH CYCLE (S VERSION ONLY)
(Addresses = DON'T CARE)
»
:D
c
NOTE:
~
DON'T CARE
~
UNDEFINED
1. Once 'RASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once 'RPS is satisfied, a complete burst of all rows should be executed.
MT8D88Cl32V/432V(S), MT16D88C232V/832V(S)
DC03.pm5- Rev. 2195
6-48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
PRELIMINARY
UU::::I=ICN
1-·
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
,,,",ow",,,,,
4,8, 16*, 32* MEGABYTES
DRAM MINICARD
1 MEG, 2 MEG, 4 MEG, 8 MEG
3.3V, FAST PAGE MODE,
OPTIONAL SELF REFRESH
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
PIN ASSIGNMENT (End View)
SS-Pin Card (DF-4)
JEDEC-standard 88-pin DRAM card pinout
2-inch (50.8mm)-long nonbuffered DRAM cards
Polarized receptacle connector
Industry-standard DRAM FAST PAGE MODE
operation
High reliability, gold-plated connector
All outputs fully TTL-compatible
Multiple RAS inputs for x16 or x32 selectability
Refresh modes: RAS ONLY, CAS-BEFORE-RAS (CBR)
and HIDDEN; optional SELF REFRESH
FAST PAGE MODE (FPM) access cycle
Single +3.3V ±O.3V power supply
Lowpower
Extended Refresh
OPTIONS
44
~
88
1
45
--.
--.
-.
-6
-7
-8
• Refresh
Extended Refresh
SELF REFRESH
<> •
@@@©@©@@@@©©©@©©©©©©©©©©©©©@@©©©©©©©©©©@©©©©~
@©©©©©©©©©©©@©@©©©©©©©©@©©@©©@©©©©©©©©©©©©©©
PIN # 4MB
8MB 16MB 32MB
--;
1
Vss
--.
--;
--;
--;
2
000
--;
--;
--;
001
3
--;
4
002
-->
-->
--;
--;
003
5
004
6
-->
-->
->
005
7
-->
->
->
006
8
->
->
->
NC
9
->
->
10
007
-->
-->
->
11 3.3VVee -->
->
->
12
NC
->
->
->
--;
13
AO
-->
-->
--;
--;
14
A2
-->
15
NC
-->
-->
-->
--;
--;
--;
A4
16
--;
--;
17 3.3V Vee -->
18
A6
-->
-->
-->
19
A8
-->
-->
-->
20
NC
Ala
-->
->
21
NC
-->
-->
-->
22
RASO
->
-->
-->
23 000
-->
-->
->
24
CASI
-->
-->
25 3.3V Vee -->
-->
->
26
RAS2
->
->
27
NC
-->
-->
->
28
P02
-->
->
PD4
29
-->
30
PD6
-->
-->
->
NC
31
->
->
->
NC
32
->
->
-->
33
NC
-->
-->
-->
34
008
->
->
->
35 3.3VVcc ->
-->
-->
DOg
36
->
->
->
37
NC
-->
-->
38
0010
-->
-->
->
39
0011
->
->
40
0012
->
-->
-->
41
0013
-->
-->
-->
42
0014
-->
-->
-->
43
0015
-->
-->
-->
44
Vss
-->
-->
-->
MARKING
• Timing
60ns access
70ns access
80ns access
Blank
S
KEY TIMING PARAMETERS
SPEED
tRe
tRAC
tpc
tAA
tCAC
tRP
-6
-7
-8
110ns
130ns
150ns
60ns
70ns
80ns
35ns
40ns
45ns
30ns
35ns
40ns
15ns
20ns
20ns
40ns
50ns
60ns
VALID PART NUMBERS
--.
PART NUMBER
DESCRIPTION
MT8D88C132VH·xx
MT8D88C132VH-xx S
MT16D88C232VH·xx
MT16D88C232VH·xx S
MT8D88C432VH·xx
MT8D88C432VH·xx S
MT16D88C832VH-xx
MT16D88C832VH-xx S
1 Megx32
1 Meg x 32,
2 Meg x 32
2 Meg x 32,
4 Meg x32
4 Meg x 32,
8Megx32
8 Meg x 32,
x 32;
SELF REFRESH
SELF REFRESH
--.
--.
--.
--.
--.
SELF REFRESH
--.
SELF REFRESH
PIN #
45
46
47
48
49
50
51
52
53
54
5!)
56
4MB
Vss
0016
0017
0018
51
At
A3
A5
A7
A9
NC
Vss
MC
NC
CAS2
Vss
CAS3
NC
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
0019
0020
0021
OQ22
0023
MC
NC
V~!1
WE
POI
P03
Vss
P05
P07
P08
NC
NC
NC
0024
0025
0026
0027
0028
OQ29
0030
0031
Vss
8MB
16MB 32MB
--;
--;
--;
--;
--;
--;
,
>
,
>
>
,
,
-.
->
-->
->
-)
-)
,
>
--)
.
..,
.
->
-->
->
->
.->
,
,
,
.,-)
,
,
,
->
->
-->
->
->
->
>
>
>
->
-->
-->
-->
-->
RASI
--;
--;
-->
-->
-->
-->
RASI
-->
-->
-->
-->
-->
-->
NC
-->
-->
--.
-->
->
RAS3
-->
-->
-->
-->
-->
NC
RJ\S3
-->
-->
-->
->
-->
-->
->
-->
->
-->
-->
-->
-->
-->
-->
-->
->
-->
->
->
-->
->
-->
-->
-->
-->
-->
->
-->
-->
-->
->
->
->
->
-->
-->
-->
-->
-->
-->
-->
-->
--.
--.
--.
--.
-->
--.
--.
--.
-->
--.
--.
'Contact factory for availability.
MT8D88C132VH/432VH(S), MT16D88C232VH!832VH(Sj
DC04.pm5 - Rev. 2/95
6-49
Micron Technology, Inc" reserves the right to change products' or specifications without notice.
©1995. Micron Technology, Inc.
C
:::D
»
~
o
»
:::D
C
PRELIMINARY
MICRON
1-·
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
"",moo,,",
GENERAL DESCRIPTION
•
Multiple RAS inputs conserve power by allowing individual bank selection. In the x32 organization, the memory
is a single array that may be divided into 4 separate bytes.
In the x16 organization, up to two banks, each with two
separate bytes, may be independently selected. One bank is
activated by each RAS selection; the others not selected
remain in standby mode, drawing minimum power.
Eight presence-detect pins may be read by the host to
identify the card's organization, number of banks, access
time and refresh operation. These extensive presence-detect functions allow systems to take full advantage of the
advanced power-saving features.
These Micron DRAM Cards are built with 2-inch-long
static dissipative plastic frames covered by metal panels.
Packages containing88-pin receptacle connectors are keyed
to prevent improper installation or insertion into other
types of IC card sockets.
The MT8D88C132VH/432VH(S), MTl6D88C232VH/
832VH(S) comprise a family of DRAM cards organized in
x32-bit memory arrays. These DRAM cards are 2-inch-Iong
bufferless versions of the JEDEC-standard 3.37-inch
(85.6mm), 88-pin x32 DRAM cards. Buffers are not included
on these cards, so the on-board timing delays have been
eliminated. Redrive circuitry may be implemented on the
system board.
The cards may also be configured as x16-bit memory
arrays, provided the corresponding DQs on the host system
are made common, and memory bank control procedures
are implemented. Four separate CAS inputs allow byte
accesses.
These 3.3V MiniCards are designed for low-power operation using 3.3V, low-power, extended refresh DRAMs.
Standard component DRAM refresh modes are supported
as well.
C
::D
FUNCTIONAL BLOCK DIAGRAM
(4MB - MT8D88C132VH, 16MB - MT8D88C432VH)
»
s:
o
»
::D
CASD ------~------~
DQD
DOl
C
CAS1
DQ8
DQ15
RAS2
CAS2
DQ16
DQ23
DQ24
DQ31
WE -----1l1li---'
fIIl
ADDRESS • •
NOTE:
1.81 through 84 = x8 memory blocks.
MT8D88C132VHf432VH(S), MT16D88C232VHJ832VH(S)
DC04.pm5 - Rev, 2/95
6-50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
UII:::I=ICN
1-·
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
","",co",,,
FUNCTIONAL BLOCK DIAGRAM
(8MB - MT16D88C232VH, 32MB - MT16D88C832VH)
RAsa
RAS1
RAs
RAs
,-----
CAs
WE
CAS
D~a
A
D;7
~
·
81
1'~c-
ViiE-
85
-~
'--,2!'
-=
-=
r-RA§-
CAs
r------;: WE82
A
-
--
CAS2
D~8 A
•
·
DQ15
c2L..-
-=
h..
RAS
CAS
WE
A
... D~16A
··
l!.
DQ23
WE87
-=
~~S
84 LA
NOTE:
1. B1 through B8
C
R~~
CAS
WE
-
o
>
:D
-..Qg
RA§-
ADDRESS
>
s:
RAs
CAS
-=
-
C
:D
RAS3
illt_
WE
•
WE
86
y~
RAS2
83
~+CAS
h..
-fk-
b.. D~24A
··
DQ31
-
b
WE
88
4
-
=x8 memory blocks.
MTBD8BC132VH/432VH(S), MT16D88C232VH/832VH(S)
DC04.pm5 - Rev. 2/95
6-51
Micron Technology, Inc., reserves the righttochaoge products ors pecificaUons withoul notice.
©1995,MlcronTechnology, Inc.
PRELIMINARY
I"IIC:I=ICN
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
","",we,"c
PIN DESCRIPTIONS
•
C
:D
»
s:
o
»
:D
C
PIN NUMBERS
SYMBOL
TYPE
22,26,65,69
RASO, RAS2
RAS1, RAS3
Input
Row-Address Strobe: RAS is used to latch the rowaddress. Two RAS inputs allow for a single x32 bank or
two x16 banks.
23,24,66,68
CASO-CAS3
Input
Column-Address Strobe: CAS is used to latch the
column-address, enable the DRAM output buffers and
strobe the data inputs on WRITE cycles. Four CAS
inputs allow byte access control for any memory bank
configuration.
70
WE
Input
Write Enable: WE is the READNliRITE conirol for ihe DO
pins. If WE is LOW prior to CAS going LOW, the access
is a WRITE cycie. ii 'vVE is HiGH during the CAS LOW
transition, the access is a READ cycle .
Address Inputs: These inputs are multiplexed
and clocked by RAS and CAS.
I
I
I
DESCRIPTION
13,57,14,58,16,59,
18,60,19,61,20
AO-A10
Input
2-8, 10, 34, 36,
38-43,46-53,
80-87
DOO-D031
IripuV
Output
71, 28, 72, 29,
74,30,75,76
PD1-PD8
-
Presence-Detect: These pins are read by the
host system and tell the system the card's personality.
They will be either left floating (NC) or grounded (Vss).
9,12,15,21,27,
31,32,33,37,54,55,
62,64,65,69,77,78
79
NC
-
No Connect: These pins should be left unconnected
(reserved for future use).
Pins 12, 31-33, 54, 77-79 reserved forx36/x40 DOs.
Pins 9,15,27,37 reserved for 5V Vee.
Pin 55 reserved for x40 OE.
11,17,25,35
Vee
Supply
Power Supply: +3.3V ±0.3V
1, 44, 45, 56,
63,67,73,88
Vss
Supply
Ground
MT6D88C132VHl432VH(8), MT16D88C232VHl832VH(S)
DC04.pm5 - Rev. 2195
Data I/O: For WRITE cycles, DOO-D031 act as
inputs to the addressed DRAM location. BYTE
WRITEs may be per/ormed by using the corresponding
CAS select. For READ access cycles, DOO-D031 act as
outputs for the addressed DRAM location.
6-52
Micron Technology, Inc., reserves the right
to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MIC:RON
1-·
"'""'w"""'
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
FUNCTIONAL DESCRIPTION
The MT8D88C132VH/432VH(S), MT16D88C232VH/
832VH(S) comprise a family of DRAM cards organized in
x32-bit memory arrays (RASO = RAS2). They also may be
configured as x16-bit memory arrays provided the corresponding DQs on the host are connected and memory bank
control procedures are implemented by interleaving both
RASlines.
Most x32-bit applications use the same signal to control
the CAS inputs. RASO and RAS1 control the lower 16 bits
and RAS2 and RAS3 control the upper 16 bits to obtain a x32
memory array. For x16 applications, the corresponding DQ
and CAS pins must be connected (DQO to DQ15, DQ1 to
DQ16 and so forth, CASO to CAS2 and CAS1 to CAS3). Each
RAS is then a bank select for the x16 memory organizations.
FAST PAGE MODE operation allows faster data operations (READ or WRITE) within a row-address-defined (AOA9 / AlO) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by RAS
followed by a column-address strobed-in by CAS. CAS
may be toggled-in by holding RAS LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning RAS HIGH terminates the FAST PAGE
MODE operation. Returning RAS and CAS HIGH terminates a memory cycle and decreases chip current to a
reduced standby level. Also, the chip is preconditioned for
the next cycle during the RAS HIGH time.
REFRESH
An optional SELF REFRESH mode is also available. The •
"S" version allows the user the choice of a fully static lowpower data retention mode, or a dynamic refresh mode at
the extended refresh period.
The optional SELF REFRESH feature is initiated by
performing a CBR REFRESH cycle and holding RAS I >OW .....
for the specified lRASS. Additionally, tlw "S" version al- tI'
lows for an extended refresh rate of 1251ls per row if lIsing
distributed CBR REFRESH. This refresh rate can be applied
during normal operation or during a standby mode. _ _
The SELF REFRESH mode is terminated by driving RAS
HIGH for a minimum time of tRPS (=tRC). This delay allows
for the completion of any internal refresh cycles that may be
in process at the time of the RAS LOW-to-HIGH transition.
If the DRAM controller uses a distributed CBR REFRESH
sequence, a burst refresh is not required upon exiting SELF
REFRESH mode. However, if the DRAM controller utilizes
RAS ONLY or burst refresh sequence, all rows must be
refreshed within 300llS prior to the resumption of normal
operation.
DRAM OPERATION
C
::JJ
DRAM REFRESH
Memory cell data is retained in its correct state by maintainingpower and executing any RAS cycle (READ,
WRITE) or RAS refresh cycle (RAS ONLY, CBR, extended
CBR or HIDDEN) so that all combinations ofRAS addresses
(AO-A9, A10) are executed at least every tREF, regardless of
sequence. The CBR REFRESH cycle will invoke the internal
refresh counter for automatic RAS addressing.
The implied method of choice for refreshing the memory
card is the extended CBR cycle. This is a very low-current,
data retention mode made possible by using the CBR REFRESH cycle over the extended refresh range (IcC7).
The memory card may be used with the other refresh
modes Common to standard DRAMs. This allows the
memory card to be used on existing systems that do not
utilize the extended CBR REFRESH cycle. However, the
memory card will draw more current in the standby mode.
3:
0
l>
::JJ
C
DRAM READ AND WRITE CYCLES
During READ or WRITE cycles, each bit is uniquely
addressed through the 20/22 address bits, which are enC
tered 10/11 bits (AO~A9 / A10) at a time. RAS is used to latch
the first 10/11 bits, and CAS latches the latter 10/11 bits.
READ or WRITE cycles are selected with the WE input. A
logic HIGH on WE dictates READ mode while a logic LOW
on WE dictates WRITE mode. During a WRITE cycle, datain (D) is latched by the falling edge of CAS. WE must fall
prior to CAS (EARLY WRITE). The data inputs and data
outputs are routed through pins using common II a and pin
direction is controlled by WE.
MT8D88C132VHJ432VH(S), MTtS088C232VHl832VH(SJ
DC04.pm5 - Rev. 2/95
PHYSICAL DESIGN
These Micron DRAM MiniCards are constructed with a
2-inch-Iong static dissipative plastic frame covered by metal
panels. Inside, thin small-outline package (TSOP) DRAMs
are mounted on an ultrathin printed circuit board. The
board is attached to a high-insertion, 88-pin receptacle
connector. The package is keyed to prevent improperinstal!ation, including insertion into other types of IC card sockets. The DRAM cards operate reliably up to 55°C.
6-53
Micron Technology, Inc., reseIV6S the right 10 change products or specifications without nOlice.
©1995, Micron Technology, Inc.
PRELIMINARY
I"IIC:I=ICN
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
,,,""'w"',"'
MEMORY TRUTH TABLE
•
C
II
»
s:
t?
ADDRESSES
IR
IC
DATA IN/OUT
100"
'CAS"
WE"
Standby
H
H~X
X
X
X
High-Z
READ
L
L
H
ROW
COL
Data-Out
EARLVWRITE
L
L
L
ROW
COL
Data-In
READ WRITE
L
L
H~L
ROW
COL
Data-In
FUNCTION
DQD-DQ31
FAST-PAGE-MODE
1st Cycle
L
H~L
H
ROW
COL
Data-Out
READ
2nd Cycle
L
H~L
H
n/a
COL
Data-Out
FAST-PAGE-MODE
1st Cycle
L
H~L
L
ROW
COL
Data-In
EARLV-WRITE
2nd Cycle
L
H-"L
L
_lI lief.
eal
Data-in
FAST-PAGE-MODE
1st Cycle
L
H~L
H~L
ROW
COL
Data-Out
READ-WRITE
2nd Cycle
L
H~L
H~L
n/a
COL
Data-Out
RAS-ONLV REFRESH
L
H
X
ROW
n/a
High-Z
HIDDEN
READ
L~H~L
L
H
ROW
COL
Data-Out
REFRESH
WRITE
ROW
COL
Data-In
L~H~L
L
L
CSR REFRESH
H~L
L
H
X
X
High-Z
SELF REFRESH (S version)
H~L
L
H
X
X
High-Z
PRESENCE-DETECT TRUTH TABLE
~~--------~----------------~----------------~
II r---~----------~--~--~--~---r~~~~~--~~~~
C
Refresh Control
NOTE:
Vss = ground.
MT8D88CI32VH/432VH(S), MTI6D88C232VH/832VH(S)
DC04.pm5 - Rev. 2195
6-54
Micron Technology, Inc., reserves the nght to change products or specifications without notice.
©1995, Micron Technology, Inc
PRELIMINARY
MICRON
1-·
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
"""c"""
ABSOLUTE MAXIMUM RATINGS*
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Voltage on Vee Supply Relative to Vss ........ -1.0V to +4.5V
Operating Temperature TA (ambient) .............. DoC to 55°C
Storage Temperature ..................................... -40°C to +70°C
Power Dissipation ............................................................. 8W
Short Circuit Output Current " ................................... 50mA
Card Insertions (connector's life cycle) ..................... 10,000
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 3, 4, 6, 7) (O°C :::; T A:::; 55°C; Vce
=+3.3V ±0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
Supply Voltage
Vcc
3.15
3.45
V
Input High (Logic 1) Voltage, all inputs
VIH
2.0
Vcc+1
V
Input Low (Logic 0) Voltage, all inputs
VIL
-1.0
0.8
V
INPUT LEAKAGE CURRENT
RASO-RAS3
111
-8
8
J.lA
Any input: OV :::; VIN :::; Vcc
AO-A10, WE
112
-10
1D
J.lA
CASO-CAS3
113
-8
8
J.lA
000-0031
loz
-20
20
J.lA
VOH
2.0
(All other pins not under test
= OV) for eaeh package input
OUTPUT LEAKAGE CURRENT
(0 is disabled, OV :::; VOUT :::; Vec) for each package input
OUTPUT LEVELS
Output High Voltage (lOUT = -2.0 rnA)
Output Low Voltage (lOUT = 2.0 rnA)
VOL
0.4
NOTES
•
C
::D
l>
31
3:
V
o
V
::D
l>
C
MT8D88C132VHf432VH{S), MT16D88C232VH/832VH(S)
OC04.pm5 - Rev. 2195
6-55
Micron Technology, Inc., reserves the right
to change products or speCifications without notice
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
"'"''"'"'"
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(Notes: 1, 6, 7) (O°C ::;; T A :s; 55°C; Vcc = +3.3V ±0.3V)
PARAMETER/CONDITION
OPERATING CURRENT: Random READIWRITE
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
c
-6
MAX
-7
4MB
8MB
16MB
32MB
640
648
960
968
560
568
880
888
480
488
mA
4MB
8MB
16MB
32MB
8
16
8
16
8
16
8
16
8
16
mA
4MB
8MB
16MB
32MB
480
488
720
728
400
408
640
648
320
328
mA
4MB
8MB
16MB
32MB
4
8
4
8
4
8
4
8
4
8
mA
4MB
8MB
16MB
32MB
640
648
960
968
560
568
880
888
480
488
mA
3,27
4MB
8MB
16MB
32MB
640
648
960
968
560
568
880
888
480
488
mA
3, 5
4MB
8MB
16MB
32MB
1.2
2.4
2.4
4.8
1.2
2.4
2.4
4.8
1.2
2.4
2.4
4.8
mA
3, 5
4MB
Iccs
8MB
(8 only) 16MB
132MB
1.2
2.4
1.2
2.4
1.2
2.4
mA
5, 28
2.4
2.4
2.4
UNITS
NOTES
Icc1
STANDBY CURRENT: (TTL)
(RAS = CAS = VI H)
II
SIZE
SYMBOL
Icc2
OPERATING CURRENT: FAST PAGE MODE
Average power supply current
(RAS = VIL, CAS, Address Cycling: IpC = IpC [MIN])
Icc3
STANDBY CURRENT: (CMOS)
(RAS = CAS = Other Inputs = Vcc -0.2V)
Icc4
:D
»
s:
o
»
:D
C
REFRESH CURRENT: RAS ONLY
Average power supply current
(RAS Cycling, CAS = VIH: IRC = IRC [MIN])
Icc5
REFRESH CURRENT: CBR
Average power supply current
(RAS, CAS, Address Cycling: IRC = IRC [MIN])
ICC6
REFRESH CURRENT: Extended CBR
Average power supply current during extended CBR; CAS = 0.2V
or CBR cycling; RAS = tRAS (MIN); tRC = 12511S; WE = Vcc -0.2V;
AO-A 10 and DO = Vcc -0.2V or 0.2V (DO may be left open)
REFRESH CURRENT: SELF (S version only)
Average power supply current; CBR cycling with
RAS;:: tRASS (MIN) and CAS held LOW; WE = Vcc-0.2V; AO-A10
and DIN =Vcc - 0.2V or 0.2V (DIN may be left open)
CAPACITANCE
Icc?
-8
-
-
3,4,27
3,4,27
-
I 4.8 I 4.8 I 4.8 I
MAX
SYMBOL 4,16MB 8, 32MB
PARAMETER
UNITS NOTES
Input Capacitance: CASO-CAS3
CI1
17
34
pF
2
Input Capacitance: WE
CI2
66
66
pF
2
Input Capacitance: RASO-RAS3
CI3
34
34
pF
2
Input/Output Capacitance: 000-0031
CIO
10
18
pF
2
Input Capacitance: Addresses
CI3
51
90
pF
2
MT8D88C132VH/432VH(S), MT16D88C232VHf832VH(S)
DC04.pmS - Rev. 2/95
6-56
Micron Technology, Inc., reserves the right 10 change productsors pecificationswithoutnotice.
©1995,MicronTechnology,lnc.
PRELIMINARY
MICRON
1-·
,cc~,w,oc,",
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 10, 11, 12, 13) (O°C
0; TAO;
AC CHARACTERISTICS
PARAMETER
Access time from column-address
Column-address hold time (referenced to RAS)
55°C; Vee = +3.3V ±0.3V)
-6
SYM
tAA
tAR
Column-address setup time
Row-address setup t:me
tASC
Access time from CAS
Column-address hold time
tCAC
tCAH
CAS pulse width
CAS hold time entering SELF REFRESH
tCAS
tCHD
CAS hold time (CBR REFRESH)
tCHR
CAS to output in low-Z
tClZ
tcp
CAS precharge time
Access time from CAS precharge
~ to RAS precharge time
tASR
tCPA
tCRP
CAS hold time
CAS setup time (CBR REFRESH)
tCSH
Write command to CAS lead time
Data-in hold time
tCWl
tDH
Data-in hold time (referenced to RAS)
Data-in setup time
tDHR
tDS
Output buffer turn-off delay
FAST-PAGE-MODE
READ or WRITE cycle time
tOFF
tpc
MT8D88C132VH/432VH(S), MT16D88C232VHl832VH(S)
DC04.pm5 - Rev. 2195
tCSR
MIN
50
0
0
MIN
MAX
35
55
0
0
15
10
15
15
15
3
10
-8
-7
MAX
30
10,000
15
10,000
20
NOTES
ns
ns
ns
15
ns
10,000
ns
ns
ns
ns
ns
45
10
80
10
20
15
60
0
3
45
UNITS
ns
ns
20
15
20
15
15
3
10
40
10
70
10
20
15
55
0
3
40
MAX
40
55
0
0
20
15
20
15
15
3
10
35
10
60
10
15
10
45
0
3
35
MIN
28
5
26
16
ns
ns
ns
ns
c
5
20
ns
ns
::xJ
24
l>
24
20,26
o
ns
ns
ns
ns
II
3:
»
::xJ
C
6-57
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
"",ceoo",,,
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 6, 7, 8, 9, 1D, 11, 12, 13) (DoG,,; T A"; 55°G; Vee
AC CHARACTERISTICS
PARAMETER
I
II
c
lJ
l>
s:
o
l>
lJ
C
=+3.3V ±D.3V)
-6
SYM
MIN
-7
MAX
MIN
-8
MAX
MIN
MAX
UNITS
NOTES
80
40
ns
ns
ns
14
18
Access time from RAS
RAS to column-address delay time
Row-address hold time
tRAC
tRAD
tRAH
10
Column-address to RAS lead time
tRAL
30
RAS pulse width
tRAS
60
RAS pulse width (FAST PAGE MODE)
tRASP
RAS pulse width entering SELF REFRESH
Random READ or WRITE cycle time
RAS to CAS delay time
tRASS
tRC
60
100
110
tReD
20
Read command hold time (referenced to CAS)
tRCH
0
Read command setup time
Refresh period (1,024 cycles)
tRCS
tREF
0
Refresh period (2.048 cycles)
RAS precharge time
tREF
tRP
40
50
60
ns
RAS to CAS precharge time
tRPC
0
tRPS
110
0
150
ns
Rl\S" precharge time exiting SELF REFRESH
0
130
Read command hold time (referenced to RAS)
RAS hold time
Write command to RAS lead time
tRRH
0
15
15
0
0
ns
ns
20
20
20
20
ns
ns
Transition time (rise or fall)
Write command hold time
Write command hold time (referenced to RAS)
tRSH
tRWL
tT
tWCH
tWCR
60
15
10,000
100,000
70
tWRH
WE setup time (CBR REFRESH)
tWRP
10
35
15
10
10,000
100,000
80
10,000
80
100
100,000
40
35
70
100
130
45
20
50
128
128
6-58
50
3
60
ns
ns
28
17
19
ns
128
128
3
ns
ns
0
0
0
50
20
ns
ns
~s
150
0
45
0
10
10
MT8D88C132VH/432VH(S), MT16D88C232VHl832VH(Sj
15
10
3
10
twcs
DC04.pm5 -Rev. 2/95
30
128
128
WE command setup time
Write command pulse width
WE hold time (CBR REFRESH)
twp
70
50
ms
ms
30
29
28
19
ns
15
15
ns
55
0
60
ns
15
10
0
15
10
ns
ns
ns
10
10
ns
22
22
Micron Technology, Inc., reserves the right to change products or specilicabons without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
"'"",COG""
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
NOTES
1. All voltages referenced to Vss.
2. This parameter is sampled. Capacitance is
measured using MIL-STD-883C, Method 3012.1.
Vee = +3.3V ±5%; f = 1 MHz.
3. Ice is dependent on cycle rates.
4. Ice is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range is assured.
7. An initial pause of lOOfts is required after power-up
followed by eight RAS refresh cycles (RAS ONLY or
CBR with WE HIGH) before proper device operation
is assured. The eight RAS cycle wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
8. AC characteristics assume tT = 5ns.
9. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input Signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
10. In addition to meeting the transition rate specification, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
11. If CAS = VIH, data output is High-Z.
12. If CAS = VIL, data output may contain data from the
last valid READ cycle.
13. Measured with a load equivalent to two TTL gates
and 100pF.
14. Assumes that IRCD < IRCD (MAX). If tRCD is greater
than the maximum recommended value shown in this
table, IRAC will increase by the amount that IRCD
exceeds the value shown.
15. Assumes that IRCD 2: IRCD (MAX).
16. If CAS is LOW at the falling edge of RAS, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS must be
pulsed HIGH for ICp.
MT8D88CI32VH!432VH(S). MT16D88C232VH/832VH(Sj
DC04.pm5 - Rev. 2195
17. Operation within the IRCD (MAX) limit ensures that
tRAC (MAX) can be met. IRCD (MAX) is specified as
a reference point only; if IRCD is greater than the
specified IRCD (MAX) limit, access time is controlled
exclUSively by ICAe.
18. Operation within the tRAD (MAX) limit ensures that
IRCD (MAX) can be met. tRAD (MAX) is specified as
a reference point only; if lRAD is greater than the
specified IRAD (MAX) limit, access time is controlled
exclUSively by IAA.
19. Either IRCH or IRRH must be satisfied for a READ
cycle.
20. toFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL.
21. A HIDDEN REFRESH may also be performed after a
WRITE cycle. In this case, WE = LOW.
22. twTS and tWTH are setup and hold specifications for
the WE pin being held LOW to enable the JEDEC test
mode (with CBR timing constraints). These two
parameters are the inverse of tWRP and twR11 in tIll'
CBR REFRESH cycle.
23. The maximum current ratings "fl' haSl'd on tIll'
memory operating or being rcfn'slll'd in tl1<' x:l2
mode. The stated maximums may he redun'd hy olH'half when used in the x16 mode.
24. These parameters are referenced to CAS-leading edge
in EARLY WRITE cycles.
25. LATE WRITE, READ WRITE orREAD-MODIFYWRITE cycles are not available due to OE being tied
permanently LOW on all 4 Meg DRAMs.
26. The 3ns minimum is a parameter guaranteed by
design.
27. Column-address changed once each cycle.
28. If the DRAM controller uses a burst refresh, a burst
refresh of all rows must be executed upon exiting
SELF REFRESH.
29. 16MB and 32MB versions only.
30.4MB and 8MB versions only.
31.4MB version is half of values shown.
6-59
Micron Technology, Inc., reserves the right to change products or speCIfications without nolice.
©1995, Micron Technology, Inc.
•
C
::D
l>
3:
o
l>
::D
C
PRELIMINARY
1'41C:I=ICN
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
","",co",,,
READ CYCLE
.
'Re
-
tRAS
:I
I
'RP
ICSH
I
'RSH
I
:~
ADDR
III
WE
I~II:
VIH-
V,L -
II:
-'
t
'AR
'RAD
'RAH
ROW
~,
'I.:
~
1
'Ase
y
tRAL
I'
• ICAH
.~I
1
,·1
COLUMN
,~
I,
I 'Res
r;,
~!I{{,,"(("((llfll({
»
s:
DO
'ReH
ROW
'!!,
~
~Wlllllllj;lj;llillm;
tRAG
I~I
lJ
I
'11-'
I
'I
.1
~:t :fll/;,WIIIIM£ff$IIJlIJ _---;-----;"-"AA_~
___
c
~I
tRAH
leAS
tRCO
'CRP
:f--__
tO_FF-J'
~:gt:::---- - ' - - - - - OPEN-------c1~(fiij~VA':":'LlD~DA~TA____t--OPEN--
o
»
lJ
EARLY WRITE CYCLE
'Re
C
tCSH
ADDR
\'-----.I
~:t
MT8D88CI32VHl432VH(S). MTI6D88C232VH/832VH(S)
DC04.pm5-Rev.2195
~I
I
ROW
6-60
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
MICRON
1-·
me",,,,"",
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
FAST-PAGE-MODE READ CYCLE
------------------------------~'R~AS~P-------------------------------I~
RAS
'cSH
ADDR
WE
I.
I
III
'AA
'~P<
II- - tCAG
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-----
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-
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ADDR
WE
VIH
VIL
DQ
VIOH
VIOL
~I
VALID DATA
~
DON'T CARE
[i§j UNDEFINED
MT8D88C132VH/432VH(S), MT16D88C232VH!832VH(S)
DC04.pm5 - Rev.
~95
6-61
JJ
»
s:
FAST-PAGE-MODE EARLY-WRITE CYCLE
tCSH
c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
PRELIMINARY
MICRON
1-·
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
""'c"'o,,'
RAS-ONL Y REFRESH CYCLE
(WE = DON'T CARE)
DO
II
~gr
-'-----,----------OPEN-------------
FAST-PAGE-MODE READ-EARL Y-WRITE CYCLE
(Pseudo READ-MODI FY-WRITE)
c
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ADDR
WE
NOTE 1
o ~gr :-,----i-OPEN-----;-------i'X»J:
I.
}------OPEN-----
I!:Zl DON'T CARE
~
NOTE:
UNDEFINED
1. Do not drive data prior to tristate.
MT8088C132VH/432VH(S), MTI6D88C232VHl832VH(S)
DC04,pm5 - Rev. 2/95
6-62
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
PRELIMINARY
UI[:::I=ICN
1-·
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
",""C,,,,,,
CBR REFRESH CYCLE
(Addresses = DON'T CARE)
.
.~
CAS
..
tRP
J9~
~:t-
II
..
~~~
2
II
tWRP
WE
1
tCHR
..
tRP
._1 ..
tRPC
DQ
tRAS
~CHR
tRAS
.1
1
OPEN----;-;II_ _ _ _ __
tWRH
tWRP
II
tWRH
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C
::D
EXTENDED CBR REFRESH CYCLE
(Addresses = DON'T CARE)
.
.
tRP
..
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CAS
~:t-
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.
1
.
tRP
..
tRAS
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tWRH
tWRP
II
tWRH
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MT8D88C132VH!432VH(S), MTI6D88C232VH/832VH(S}
DC04.pm5 - Rev. 2195
1CHR
II
tWRP
WE
..
125~s
tRAS
6-63
•
~
DON'T CARE
~
UNDEFINED
Micron Technology, Inc., reserves the nght to change products or specifications without notice
©1995, Micron Technology, Inc
PRELIMINARY
I'IIIC::I=ICN
,m"mc,,"'
MT8D88C132VH/432VH(S), MT16D88C232VH/832VH(S)
4MB, 8MB, 16MB, 32MB DRAM CARDS
HIDDEN REFRESH CYCLE 21
(WE = HIGH)
(READ)
tRAS
(REFRESH)
tRP
tRAS
--~tRCD---.-.~tR-~:~~:---t~CHR----·~~
•
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ADDR
-tOFF
C
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::xJ
OPEN-
»
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SELF REFRESH CYCLE (S VERSION ONLY)
(Addresses = DON'T CARE)
»
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c
NOTE:
~
DON'TCARE
~
UNDEFINED
1. Once tRASS (MIN) is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
MT8D88C132VHJ432VH(S), MT1608eC232VH/832VH(S)
DC04.pmS - Rev. 2195
6-64
Micron Technology, Inc., reserves the right to change products or specifications without notics.
©1995, Micron Technology. Inc.
TECHNICAL NOTES ...................................... ..
TECHNICAL NOTE SELECTION GUIDE
Technical Note
Tille
Page
TN-00-01
Moisture Absorption in Plastic Packages
7-1
TN-00-02
Tape-and-Reel Procedures
7-3
TN-00-03
Using Gel-Pal<® Packaging With Micron Die
7-9
TN-04-01
DRAM Power-Up and Refresh Constraints
7-11
TN-04-06
OE-Controlled/LATE WRITE Cycles (DRAM)
7-13
TN-04-12
LPDRAM Extended Refresh Current vs. RAS Active Time (4 Meg)
7-15
TN-04-15
DRAM Considerations for PC Memory Design
7-17
TN-04-16
16 Meg DRAM-2K vs. 4K Refresh Comparison
7-23
TN-04-19
Low-Power DRAMs vs. Siow SRAMs for Main Memory
7-25
TN-04-20
SELF REFRESH DRAMs
7-27
TN-04-21
Reduce DRAM Cycle Times with Extended Data-Out
7-29
TN-04-22
256K x 16 DRAM Typical Operating Curves
7-37
TN-04-23
4 Meg DRAM Typical Operating Curves
7-39
TN-04-24
4 Meg DRAM-Access Time vs. Capacitance
7-45
TN-04-26
256K x 16-Access Time vs. Capacitance
7-47
TN-04-28
DRAM Soft Error Rate Calculations
7-49
TN-04-29
Maximizing EDO Advantages at the System Level
7-53
TN-04-30
Various Methods of DRAM Refresh
7-65
TN-04-31
PCB Layout for 4 Meg x 4 300 Mil or 400 Mil SOJ
7-69
TN-04-32
Reduce DRAM Memory Cost with Cache
7-71
TN-41-01
Decrement Bursting with the SGRAM
7-75
TN-88-01
88-Pin DRAM Cards
7-79
For the latest technical information on Micron products, read our quarterly technical newsletter Design Line.
Call 208-368-3900 to be added to our mailing list.
Gel-Pak IS a registered trademark of Vichem Corporation
MICRON
1-·
TN-OO-01
MOISTURE ABSORPTION
""",CO"",,
TECHNICAL
NOTE
MOISTURE ABSORPTION
IN PLASTIC PACKAGES
INTRODUCTION
DEVICE STORAGE
All plastic integrated-circuit packages have a tendency to
absorb moisture. During surface-mount assembly, this
moisture can vaporize when subjected to the heat associated
with solder reflow operations. Vaporization creates internal
stresses that can cause the plastic molding compound to
crack. Cracks in the package allow contamination to
penetrate to the die and potentially reduce the reliability of
the semiconductor device. The cracking process associated
with surface-mountable devices is commonly referred to as
the "popcorn effect."
Cracks in the plastic pose several reliability concerns. The
moisture path to the die is shortened, allowing ion migration
or corrosion to occur more readily. Minor cracks which
might not be harmful initially could propagate with time,
reSUlting in a longer-term functional failure.
Since plastic packages absorb moisture, care must be
taken to prevent exposure for any long period prior to
surface-mounting the devices on the printed circuit board.
If exposed to excessive moisture, the devices should be
baked to remove moisture prior to solder reflow operations.
This technical note describes the shipping procedures
that ensure Micron's customers will receive memory devices
that do not exhibit the popcorn effect. It also discusses
Micron's recommendations for baking the devices if they
are exposed to excessive moisture.
To prevent device failure due to the popcorn effect, store
plastic surface-mount packages carefully before PCB
assembly. Micron has run tests on devices that have been
exposed to 50 percent humidity outside of their shipping
containers for time intervals from six months to one year,
and no failures have been recorded.
Any concerns about the moisture absorption can be
eliminated by storing the devices in Micron's shipping
bags. We designed these containers to prevent the passage
of water vapor for long periods of time.
DEVICE BAKING
If devices have been removed from tlwir shipping
containers and exposed to high levels of moist 1I r1', Micron
recommends a device bake-out procedure beforc surfacc
mounting. This bake-out may be accomplished by placing
the parts in a tray and baking them in an oven for 160 hours
at 40° C. Any moisture is driven out of the devices during
the exposure to the heat.
Moisture maybe removed faster by baking at 1000 C for
24 hours.
SUMMARY
1. All plastic packages absorb moisture when exposed
to high levels of humidity for long time intervals.
2. Micron devices have not exhibited any popcorn
effect when exposed to 50 percent humidity for
long time periods.
3. Micron ships all surface-mount packages in
containers that prevent absorption of moisture.
4. If devices have been removed from their shipping
containers and exposed to excessive moisture, they
should be baked before being surface-mounted.
ABSORPTION CHARACTERISTICS
Micron's extensive testing empirically characterizes the
moisture absorption characteristics of plastic packages. As
the plastic takes on moisture, the weight of the device
increases. Micron employs a standard procedure for
weighing the device before and after it is exposed to
moisture. We calculate the percentage of weight gain to
:ietermine the relative efficiency of different packaging
:echniques used for shipping devices.
REFERENCES
"Moisture Absorption and Mechanical Performance of Surface
Mountable Plastic Packages": Bhattacharyya, B. K., et al.: 1988
Proceedings of the 38th Electronics Components Conference.
MICRON PROCEDURES
Micron has eliminated any chance of having popcorn
:ailures with surface-mount packages by shipping all
mrface-mount devices in sealed bags containing a desiccant.
)evices stored in these bags show no measurable weight
;ain when subjected to a high-humidity environment for
ong time periods.
N-DO-01
)T-1.pm5 - Aev. 2/95
"Analysis of Package Cracking During Reflow Soldering Process":
Kitano, M., et al. :26th Annual Proceeding, Reliability Physics, 1988.
"Moisture Induced Package Cracking in Plastic Encapsulated Surface
Mounted Components Ouring Solder Reflow Process": Lin, R, et
al.: 26th Annual Proceeding, Reliability Physics, 1988.
7-1
Micron Technology, Inc., reserves the right to change products or speCifications withoLiI notice.
©1995, Micron Technology, Inc.
-I
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TN-OO-01
MOISTURE ABSORPTION
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TN-OO-01
OT-1.pmS- Rev. 2/95
7-2
MICRON
1-·
TN-OO-02
TAPE-AND-REEL
","",c,", '"
TAPE-AND-REEL
PROCEDURES
TECHNICAL
NOTE
GENERAL DESCRIPTION
Micron supports the Electronic Industries Association's
(EIA) standardization of tape-and-reel specifications number 481A. The intent of this technical note is to describe
Micron's status in support of the EIA standard.
Tape-and-reel is becoming the packaging and shipment
method of choice for Micron's surface-mounted memory
devices. Tape-and-reel minimizes the handling of components by directly interfacing with automatic pick-and-place
machines.
Table 1*
MICRON TAPE SIZES AND DEVICES PER REEL
DEVICES PER
13-INCH REEL
TAPE WIDTH
(W)mm
PITCH
(P)mm
PLCC
18 Pin
32 Pin
52 Pin
24
24
32
12
16
24
1,000
500
500
SOJ (300 mil)
20/26 Pin
24 Pin
28 Pin
32 Pin
24
24
24
32
12
12
12
12
1,000
1,000
1,000
1,000
COMPONENT
SOJ (400 mil)
28 Pin
32 Pin
40 Pin
32
44
44
16
16
16
500
500
500
TSOP (300 mil)
20/26 Pin
24
12
1,000
TSOP (400 mil)
40/44 Pin
32
16
1,000
'These are examples of tape-and-reel sizes available. Please contact Micron for all
available options.
TN,OO-02
OT02.pm5 - Rev. 2/95
7-3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
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1-·
TN-OO-02
TAPE-AND-REEL
"'""OC"'""
Top cover
tape thickness (t1)
0.10
(0.004) MAX
/
RMIN
Embossed - - - - -___
carrier
See Table 2
NOTE 2
Figure 2
BENDING RADIUS
Figure 1
REEL
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100mm _ _ _ _ _ _ _1
(3.937)
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Round Holes
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1mm
(0.039) MAX
1___- - - - -_ _ _ _ _ _ _ _ _ _ _
250mm ___________________________1
(9.843)
Allowable camber to be1 mm/1 OOmm nonaccumulative over 250mm.
Figure 3
CAMBER
(top view)
TN-OO-02
OT02.pm5- Rev. 2/95
7-4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-OO-02
TAPE-AND-REEL
",,<'W,,"",
r pO-1
•
USER DIRECTION OF FEED
-[
P2-
1
81
-/-
10 pitches
cumulative
tolerance on tape
±O.2
(±O.008)
w
KO
See Note 1
Table 2
For machine reference
only, include draft and radii
concentric around BO.
Embossment
Center
lines of
cavity
D1 lor components
2.0mm x 1.2mm
and larger
•
Figure 4
EMBOSSED CARRIER DIMENSIONS
(24mm tape only)
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24mm EMBOSSED TAPE DIMENSIONS3
TAPE SIZE
24mm
E
PO
t(MAX)
AO,BO, KO
1.75
(0.069 ±0,004)
4
(0.157 ±0.004)
0.400
(0.16)
Note 1
0
1.5 ~g6g
(0.59) :gg:
B1 (MAX)
01 (MIN)
F
K(MAX)
P2
R(MIN)
W
24mm
20.1
(0,791)
1.5
(0.059)
11.5 ±0.10
(0.453 ±0.004)
6.5
(0.256)
2 ±0.10
(0.079 ±0.004)
50
(1.969)
24 ±0.30
(0.945 ±0.012)
P
24mm
NOTE:
4±D.10
(0.157 ±D.004)
8±D.10
(0.315 ±D.004)
12 ±D.10
(0.472 ±D.004)
16 ±D.10
(0.630 ±D.004)
20±D.10
(0.787 ±D.004)
24±D.10
(0.945 ±D.004)
x
x
x
x
1. AO, BO and KO are determined by component size. The clearance between the component and the cavity
must be within 0.05 (0.002) MIN to 1.00 (0.039) MAX for 24mm tape. The component cannot rotate more
than 20° within the determined cavity.
2. Tape and components shall pass around radius "R" without damage.
3. All dimensions in millimeters, (inches).
TN-OO-02
OT02.pm5 - Rev. 2/95
»r
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TAPE SIZE
TAPE SIZE
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7-5
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
o-t
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MlIC::I=ICN
1-·
TN-OO-02
TAPE-AND-REEL
,"~"","""
D-Round
holes this side
B1 is for machine reference
only, including draft and radii
concentric around BO.
PO 10 pitches cumulative
tolerance on tape ±0.2 (±0.008)
Top cover
tape
KO
K
D1
NOTE 1
_ _ _ _ _ _ _ _ _... See Table 3
USER DIRECTION OF FEED
•
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EMBOSSED CARRIER DIMENSIONS
(32 and 44mm tape only)
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Figure 6
DETAIL ELONGATED HOLE
TN-OO-02
OT02.pm5- Rev. 2/95
7-6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC:RON
TN-OO-02
TAPE-AND-REEL
"'~"co,,"
1-·
Table 3
32 AND 44mm EMBOSSED TAPE 3
TAPE SIZE
D
D1 (MIN)
E
K(MAX)
PO
t (MAX)
32 and 44mm
1.5 :8Jg
(0.059) :~ggri
2
(0.079)
1.75±0.10
(0.069 ±0.004)
10
(0.394)
4 ±0.10
(0.156 ±0.004)
0.500
(0.20)
F
AD, BO,
KD
NOTE 1
W
R (MIN)
32mm
23
(0.906)
14.2 ±0.10
2 ±0.10
28.4 ±0.10
(0.559 ±0.004) (0.079 ±0.004) (1.118 ±0.004)
32 ±0.30
(1.26 ±0.O12)
50
(1.973)
44mm
35
(1.378)
20.2 ±0.15
2 ±0.15
40.4 ±0.10
(0.795 ±0.006) (0.079 ±0.006) (1.591 ±0.004)
44.8 ±0.30
(1.732 ±0.12)
50
(1.973)
TAPE SIZE
TAPE SIZE
44mm
P2
S
P
16 ±O.10
20 ±O.10
24±O.10
28 ±O.10
32 ±O.10
36 ±O.10
40 :1:0.10
44 ±O.10
(0.630 ±O.004) (0.787 ±O.004) (0.945 ±O.O04) (1.102 ±O.OO4) (1.26 ±O.O04) (1.417 ±O.004) (1.575 ±O.OO4) (1.732 ±O.O04)
x
32mm
NOTE:
B1 (MAX)
x
x
x
x
x
x
x
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x
x
1. AO, 80 and KO are determined by component size. The clearance between the component and the cavity
must be within 0.05 (0.002) MIN to 1.00 (0.039) MAX for 24mm tape. The component cannot rotate more
than 20° within the determined cavity.
2. Tape and components shall pass around radius "R" without damage.
3. All dimensions in millimeters (inches).
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TN·OO-02
OT02.pm5 - Rev. 2195
7-7
Micron Technology, inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
TN-OO-02
TAPE-AND-REEL
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TN-OO-Q2
OT02.pm5- Rev. 2/95
7-8
MICRON
1-·
m~"w"'"
TN-OO-03
USING GEL-PAK® PACKAGING WITH MICRON DIE
TECHNICAL
NOTE
USING GEL-PAK® PACKAGING
WITH MICRON DIE
INTRODUCTION
STORAGE REQUIREMENTS
In order to provide a robust packaging environment
when shipping die products, Micron uses Gel-Pak® packages. This Technical Note describes the Gel-Pak package,
the advantages it has over other forms of packaging and
how customers can store and use die from this package.
Micron die are packaged for shipping within a cleanroom
environment and packaged in a vacuum sealed bag to
minimize exposure to humidity. Upon receipt, the customer should transfer the Gel-Pak package to a similar
environment for storage. Micron recommends the die be
maintained in a filtered nitrogen atmosphere until removed for assembly. The moisture content of the storage
facility should be maintained at 30% ±10% relative humidity. ESD damage precautions are necessary during handling. The die must be in an ESD-protected environment at
all times during inspection and assembly.
THE GEL-PAK
The Gel-Pak was chosen because of its advantages over
other methods of packaging. Although die can be stored in
traditional waffle-packs or chip trays, these packages cannot be used for shipping die. In these packages, the die may
easily move within the storage cavity during shipment.
This movement can be abrasive to the die and can cause
chipping or breakage.
The Gel-Pak eliminates these problems. Figure 1 shows a
side view of a Gel-Pak containing die. Right below the die
is a gel membrane that uses surface tension to rigidly hold
the die in place. Because the die cannot move, the chances
of damage are greatly reduced. In addition, the topside of
the die which contains the device circuitry is not in contact
with any surface that could damage the die.
Micron uses conductive Gel-Paks. The plastic used in the
construction of the tray and cover is electrically conducting
and protects the die from harmful static electricity. We still
recommend that ESD precautions be taken whenever handling or moving the Gel-Pak tray.
USING GEL-PAKS
Figure 2 shows a Gel-Pak being lIs,-d wlll'1l die <1n-lwing
removed during an assembly process. Undenll'ath the gel
membrane is a release pattern formed of fabric mesh or
molded pattern which defines a series of voids underneath
the die. When a vacuum is applied to the tray, the gel
membrane is deformed and the amount of surface area in
contact with the die is greatly redun-d. II holding fixtunshould be provided for positive positioning of tl\(' tl\ly so
that a leak-free vacuum can be delivered to the underside
of the tray. Empirical tests show that the surface tension
force is reduced by over two orders of magnitude allowing
the die to be easily removed.
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L.
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Va,""ffi
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Figure 2
VACUUM APPLIED TO GEL-PAK
Figure 1
CROSS-SECTIONAL VIEW OF A GEL-PAK
TN-OO-03
OT03.pm5 - Rev. 2195
Plo""p Tool-O
7-9
Micron Technology, Inc., reserves the nght to change products or specifications without notice.
©1995, Micron Technology, Inc.
Gel-Pak is a registered trademark of Vichem Corporation.
MICRON
1-·
z
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"'"""'"""
TN-OO-03
USING GEL-PAK® PACKAGING WITH MICRON DIE
Once the vacuum is applied to the container, it is recommended that a vacuum pickup tool be used to remove and
place the die. This will minimize the risk of breakage or
chipping. Replaceable rubber tips for pickup tools may
provide for a more positive device removal from vacuum
release trays. The maximum tip size compatible with the
device should be used.
With some pick and place machines, the vacuum is
activated by the contact pressure of the pickup tool on the
die. This may result in the die being pushed slightly into the
gel, which in turn reduces the ease with which the die can
be picked from the geL Some equipment manufacturers
have indicated that their pick and place machines can be
easily modified to automatically activate the vacuum with
very jow contact pressure, or manually by the operator with
essentially no contact pressure.
Vacuum Work Stations are available from Gel-Pak which
provide an easy way to apply the vacuum to the Gel-Pak.
Micron uses 2- and 4-inch Gel-Paks. The 4-inch Vacuum
Work Station can be used with both types.
Figure 3 shows a typical orientation of die in a Gel-Pak.
All die are placed in the Gel-Pak with identical orientation.
Refer to individual die data sheets for the exact orientation
for a particular die and part number.
CONCLUSION
By using the methods outlined above, customers will be
able to use Micron die shipped in Gel-Paks. Following these
guidelines will ensure minimum breakage and ease of use.
=E
•
Bond Pad #1
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ORIENTATION OF DIE IN GEL-PAK
TN-OO-03
OT03.pm5- Rev. 2195
7-10
Micron Technology, Inc., reserves the right to change products or specifications without notice,
©1995, Micron Technotogy, Inc.
MICRON
1-·
TN-04-01
DRAM POWER-UP AND REFRESH CONSTRAINTS
",",cw"""
TECHNICAL
NOTE
DRAM POWER-UP AND
REFRESH CONSTRAINTS
INTRODUCTION
POWER-UP
The JEDEC 4 Meg DRAM introduces two potential
incompatibilities compared to the previous generation
1 Meg DRAM. The incompatibilities involve refresh and
power-up. Understanding and addressing these incompatibilities and providing for them will offer designers and
system users greater compatibility between the 1 Meg and
4 Meg.
The 4 Meg JEDEC test mode constraint may introduce
another problem. The 1 Meg POWER-UP cycle requires a
lOOlls delay followed by any eight RAS cycles. The 4 Meg
POWER-UP cycle is more restrictive in that eight RAS
ONLY or CBR REFRESH (WE held HIGH) cycles must be
used. The restriction is needed since the 4 Meg may powerup in the JEDEC-specified test mode and must exit out of
the TEST MODE. The only way to exit the 4 Meg JEDEC
TEST MODE is with either a RAS ONLY ora CBRREFRESH
cycle (WE held HIGH).
REFRESH
The most commonly used refresh mode of the 1 Meg is
the CAS-BEFORE-RAS (CBR) REFRESH cycle. The CBR for
the 1 Meg specifies the WE pin as a "don't care." The 4 Meg,
on the other hand, specifies the CBR REFRESH mode with
the WE pin held at a voltage HIGH level.
A CBR cycle with WE LOW will put the 4 Meg into the
JEDEC-specified test mode (WCBR). In contrast, the 1 Meg
test mode is entered by applying a HIGH signal to the test
pin (pin 4 on DIPs, pin 5 on SOJs and pin 8 on ZIPs). This
HIGH signal is usually a "super voltage" (VIN 2 7.5V), so
normal TTL or CMOS HIGH levels will not cause the part
to enter TEST MODE.
~~t =:
CAS
~:t:::-
{CPN.
•
The 1 Meg and 4 Meg are compalibll', with tIll' following
exceptions:
1. For standard TEST MODE, thl' I Meg requires a vaild
HIGH on the test pin while the 4 Meg requires a CI:lR
cycle with WE LOW.
2. The 1 Meg CBR REFRESH allows the WE pin to be a
"don't care" while the 4 Meg CllR requires WE to bl'
HIGH.
3. The eight RAS wake-up cycles on tl1l' I Megillaybl·,ull'..
valid RAS cycle while the 4 Meg may only use ({AS
ONLY or CBR REFRESH cycles (WE held HIGH).
RAS
f ~-
RAS
SUMMARY
"1
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1
~W~B--
WE
~k
4 Meg {
DRAM
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tWRP
CBR REFRESH WE
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-
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II
tWRH
tWRP
- -
tWRH
~:t --11/!;///I/!;/I111!;////11!1;/!W;W;/;W///$///;/IIII!!W///////$;////ffilffill;
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DON'T CARE
COMPARISON OF 4 MEG TEST MODE AND WCBR TO 1 MEG CBR
TN-04-01
DT01.pm5 - Rev. 2/95
7-11
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Micron Technology, Inc., reserves the right to change products or specffications without notice.
©1995, Micron Technology. Inc.
MICRON
1-·
"'"",CO"""
TN-04-01
DRAM POWER-UP AND REFRESH CONSTRAINTS
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TN-04-01
DT01.pm5 - Rev. 2f95
7-12
Micron Technology. Inc., reserves the ngh! to change products or specifications without notice.
©1995,MicronTechnology, Inc.
MICRON
1-·
_
TN-04-06
OE-CONTROLLED/LATE WRITE CYCLES (DRAM)
"'~"wc,,~,
OE-CONTROLLED/LATE
WRITE CYCLES (DRAM)
TECHNICAL
NOTE
INTRODUCTION
There are three cycles available to write to a DRAM:
EARLY WRITE cycles, READ-MODIFY-WRITE cycles and
LATE WRITE cycles. The industry-standard definitions for
DRAM WRITE cycles are fairly consistent for both the
EARLY WRITE and READ-MODIFY-WRITE cycles. An
exception exists for the LATE WRITE cycle.
This condition may be viewed as an EARLY WRITE with
twcs "sliding" past the CAS time and violating the Ons
setup time (WE going LOW prior to CAS going LOW).
However, since the output buffers are not being used (OE is
HIGH), twcs and ICWD are no longer required.
If WE transitions LOW after CAS transitions LOW, do not
bring OE LOW (a noise spike may occur), because the
output buffers could turn on and cause contention with the
data bus, which could corrupt input data.
The term used for such a WRITE cycle varies throughout
the industry. The use of "OE-controlled WRITE," "delayed
WRITE" and "LATE WRITE" all signify the same WRITE •
cycle described.
COMMON DQ DRAM (x4, x8, etc.)
A LATE WRITE cycle is a READ-MODIFY-WRITE (see
Figure 1) except that the READ portion is not utilized. This
is accomplished by keeping the output enable pin (OE)
HIGH throughout the cycle. The timing parameters IRWD,
IAWD and tcWD no longer apply since OE is HIGH.
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Figure 1
READ-MODIFY-WRITE (MULTIPLE DQ) TIMING
TN-04-06
DTOS.pm5 - Rev. 2195
7-13
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Micron Technology, Inc., reserves the right to change products or specifications without notiCtl.
©1995, Micron Technology, Inc.
MICRON
I~·
"'e,"co"""
_
TN-04-06
OE-CONTROLLED/LATE WRITE CYCLES (DRAM)
SPLIT D AND Q DRAM (xl)
A LATE-WRITE cycle is a READ-MODIFY-WRITE,
except the READ portion is not guaranteed and the D and
Q pins are separate paths (D and Q cannot be connected).
This is accomplished by ignoring the timing parameters
IRWD, IAWD and ICWD.
This condition can be viewed as an EARLY WRITE with
twcs "sliding" past the CAS time and violating the Ons
setup time (WE going LOW prior to CAS going LOW).
However, since the output buffers are "don't care," IWCS
and ICWD are no longer required.
This cycle is not available on applications that have the D
and Q connected together, because the output will contend
with the input.
SUMMARY
A LATE WRITE cycle is most useful on common DQ
DRAMs. Use caution to ensure that the output enable pin is
properly controlled.
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TN-04-0S
DT06.pm5 - Rev. 2/95
7-14
Micron Technology, Inc., reserves the right to change products or specificatIOns without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
."",cco,,,",
TN-04-12
LPDRAM EXTENDED REFRESH CURRENT (4 MEG)
lPDRAM EXTENDED
REFRESH CURRENT vs. RAS
ACTIVE TIME (4 MEG)
TECHNICAL
NOTE
INTRODUCTION
One of the most significant features of the low-power
extended refresh DRAM (LPDRAM) is its cycle. Extended
refresh is essentially a CAS-BEFORE-RAS (CBR) REFRESH
at an extended refresh rate of 125J.ls per cycle.
RAS pulse width (MS) affects the extended refresh
current and should be considered when designing a lowpower system. The longer RAS is held LOW, the more
current an LPDRAM will consume while in the extended
refresh mode. Therefore, keeping tRAS at a minimum will
maximize power savings.
Extended
Refresh
(lJA)
650
600
550
500
450
400
350
300
250
200
150
100
Figure 1, a typical curve of Micron's 4 Meg LPDRAM
(MT4C4001J Sand MT4C1004J S), shows the relationship
between its extended refresh standby current and the width
oftRAS.
SUMMARY
The MS time should be kept as short as possible when
designing memory array timing. This will result in lower
standby currents, especially for the extended refresh cycle.
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300
500
1000
3000
5000
tRAS (ns)
Figure 1
TYPICAL EXTENDED REFRESH CURRENT AS A FUNCTION OF tRAS
TN-04-12
DT12.pm5 - Rev. 2/95
7-15
Micron Technology, Inc., reserves the right
to change products or specifications without notice.
©1995, Micron Technology, Inc.
I"IIC:F:::If;;1~
TN-04-12
LPDRAM EXTENDED REFRESH CURRENT (4 MEG)
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TN-04-12
DT12.pm5 - Rev. 2195
7-16
MICRON
1-·
TN-04-15
DRAM DESIGN CONSIDERATIONS
"'""'00""
TECHNICAL
NOTE
DRAM CONSIDERATIONS
FOR PC MEMORY DESIGN
INTRODUCTION
PARITY (OR NO PARITY)
The demand for DRAM memory in personal co;mputers
(PCs) has been mainly for desktop personal computers.
When designing main memory, PC designers have primarily focused on three requirements: availability, cost and
speed.
The new and growing field of portable personal computers has introduced seven additional issues:
There is a growing trend to build notebook and low-end
to mid-range desktop PCs without parity. Within a few
years, most parity-based systems will switch to either
nonparity-based systems (as in most PCs) or error detection
and correction (EDAC) based systems (high-end PCs).
Some of the reasons for this trend away from parity are
listed below:
•
•
•
•
•
•
•
1. Parity does not significantly improve reliability.
2. DRAMs from a quality manufacturer now have
very low soft error rates (SERs).
3. Parity increases memory costs 10 to 15 percent.
4. Some chipsets allow turning (Iff the parity bit.
5. Parity requires extra bo,lrd SP,Il'" as wl'll as
previous generation d,'vic,'s or kss ilvililnbk
parity chips,
6. Some software does not use parity,
Parity
Lower power (Extended Refresh)
SELF REFRESH
Package size
Operating current
3.3V operating voltag~
DRAM cards (88-pin)
The first three issues (availability, cost and speed) are
well understood. This technical note discusses the remaining issues in order to help memory designers choose the
best solution for their portable or desktop system designs.
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To design main memory, five basic offerings of DRAM
are or will be available in the near future:
(plus 1 Meg x 4 Quad CAS for parity)
(512K x 9 for parity)
(4 Meg x 1 for parity)
(256K x 18 for parity)
(1 Meg x 4 Quad CAS for parity)
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The first offering is referred to as "standard DRAMs,"
and the remaining are referred to as "wide DRAMs." Generally, standard DRAMs are more readily available and
have more sources. Wide DRAM development is usually a
generation behind the standard DRAM and is not expected
to catch up until the third generation of 16 Meg DRAMs and
the first generation of 64 Meg DRAMs.
Past, Present and Future Trends
TN-04-15
DT15.pm5 - Rev. 2/95
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OFFERINGS
1 Megx4
512Kx8
2Megx8
256Kx 16
1 Meg x 16
III
7-17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-04-15
DRAM DESIGN CONSIDERATIONS
"'<"OW'''''
The most important of these factors is the memory system's
reliability. In the early days of semiconductor DRAM
memories, the high SER of 4K and 16K DRAMs, coupled
with the high cost of implementing EDAC (8-bit buses),
made implementing parity critical. DRAM manufacturers,
however, have significantly reduced SER during the last
five generations (Fig. 1). For example, the SER on a 16K
DRAM was approximately 1 to 5 FITs per bit, whereas the
SER on a 4 Meg DRAM is closer to 0.0002 to 0.0004 FITs per
bit-a 10,000x improvement. (FIT is a failure in time, where
time is 1 billion device hours.)
Typical MTSF Due to Soft Errors
10
1,000
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Historical Industry SER in DRAMs
10~----------~----------~----
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100,000
1.000.000
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jjj
256K
1 Meg
4 Meg
16 Meg
DRAM Density
0.1
Figure 2
MTBF FOR 2MB MEMORY SYSTEM
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Another way to look at this same data is to calculate the
number of SER hits a user would see after ten years of
continuous use (Fig. 3). As expected, the SER is negligible
after ten years of continuous use when using today's highquality DRAMs.
0.001 +-------'-------'-------'---'
Soft Errors over Ten Years of Continuous Use
0.0001 -'--____--'-____--'-____--'--____--'--____--L____.....l
16K
Z
64K
256K
1 Meg
4 Meg
16 Meg
DRAM Density
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HISTORICAL DRAM SER
By taking these industry SER averages and applying
them to a 2MB, 16-bit wide memory system, meaningful
benchmarks for PCs can be obtained. Most systems measure errors in mean time between failures (MTBF). Applying the SER numbers from the previous figure, the improvement in MTBF for a typical 2MB, 16-bit wide memory
system can be demonstrated (Fig. 2).
It is obvious why parity was instituted in the 16K DRAM
days. A memory system made of 16K DRAMs would
experience a SER hit every 60 to 70 hours. Because of this, it
has been standard operating procedure to design in parity.
But changes are ahead. System designers are starting to ask,
"Why?" Using today's high-quality 4 Meg DRAMs rather
than yesterday's 16K DRAMs extends the MTBF from
approximately 60 hours to an MTBF of 30 to 35 years on a
2MB by 16-bit wide memory system.
TN-04-15
DT15.pm5 - Rev. 2195
100
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16K
64K
256K
1 Meg
4 Meg
16 Meg
DRAM Density
Figure 3
2MB MEMORY SYSTEM SER
7-18
Micron Technology, Inc., reserves Ihe righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-04-1S
DRAM DESIGN CONSIDERATIONS
'''""0'''''"'
It is important to note that the SER and MTBF must be
carefully calculated for any given system and its application. The DRAM's SERis dependent on Vee (power supply
voltage), operating speed (cycle rate) and memory configuration. By taking the previous 2MB example and doubling
it to 4MB, the SER will either increase slightly or double. If
the width of the memory system is increased to 32 bits, the
SER would double since all DRAM bits are active. If, on the
other hand, the memory is interleaved and the bus remains
16 bits wide, the SER increases only slightly. This is because
the bank not being accessed is in standby mode and is much
less susceptible to SER hits. (The faster the cycle rate,
the more susceptible a DRAM is to SER.) Technical note
TN-04-28 provides an in-depth analysis to determine system MTBF to soft error.
rather than parity, decreases substantially as the bus width
increases. In fact, the DRAM memory cost is the same for a
64-bit wide bus (Table 1). Besides detecting two errors for a
given word, EDAC will also correct any single bit error.
Most applications with buses no more than 32 bits wide
do not require parity, whereas applications using bus widths
of 32 bits or more may require some kind of bit-checking for
errors. The choice is usually EDAC rather than parity.
Table 2
SELECTION FOR ERROR CHECKING
ERROR
CHECKING
Nonparity
Parity
Table 1
PARITY AND EDAC OVERHEAD
BUS SIZE (BITS)
8
16
32
64
EXTRA BITS
REQUIRED
PARITY
EDAC
1
5
2
6
4
8
8
8
EDAC
BUS SIZE (BITS)
16
1 Meg x 4
n/a
n/a
32
64
1 Meg x4
1 Meg x 4
1 Meg x 4
1 Meg x 4
1 Meg x 4
1 Meg x 4
Table 2 summarizes which DRAM would 11l' the optimum choice, considering prin', f1l'rfOl"m.IIH·(· .111.1 span'.
It takes into account the typic'." I'C whkh ships with iI
minimum of 4MB of memory. The 64-bit bus choice of
1 Meg x 4 DRAMs is based on memory size increase from
4MB to 8MB.
The 1 Meg x 16 will be the part of choice once the premium reaches 10 percent above [our 1 Ml'g X 4 DRAMs. I\s
the minimum memory requirements jnnl'.lsl', tl", 2 Mq-\ x
8 will offer the optimum support: 16- .1I1e1 :l2-bit busl's at
8MB and 64-bit buses at 16MB.
BUS WIDTH
INCREASE
PARITY
EDAC
12.5%
62.5%
12.5%
37.5%
12.5%
25%
12.5%
12.5%
Although the need for parity would appear to be greater
for wider buses, the additional cost to implement EDAC,
NOTE 1
RAS
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Figure 4
SELF REFRESH OPERATION
NOTE:
1. Once 'RASSmin is met and RAS remains LOW, the DRAM will enter SELF REFRESH mode.
2. Once 'RPS is satisfied, a complete burst refresh of all rows should be executed. Distributed refreshes at the
specified refresh rate are acceptable, provided CBR REFRESH cycles are utilized.
TN-04-15
DT15.pm5-Rev.2i95
7-19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•
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1-·
TN-04-15
DRAM DESIGN CONSIDERATIONS
"'""""'"'
LOW-POWER, EXTENDED REFRESH
These are also available in a thin, small-outline, gull-lead
package (TSOP). The length and width of a TSOP are the
same as the corresponding SOJ package (same board area)
except that the x16 length TSOP is reduced because of a
smaller lead pitch (50mil to 32mil). The TSOP's key attraction is that it is one-third the thickness of the SOJ (47 mils
compared to 142 mils), as illustrated below:
A low-power, extended refresh DRAM (LPDRAM) has a
reduced CMOS standby current limit (typically from 1mA
to 200flA) and refresh interval eight times longer (from 15fls
per row to 62.5fls or 125fls per row). The extended refresh
offers an extended mode, which is a low-current, dataretention cycle. Each of the five DRAM options in this
technical note have low power, extended refresh versions
available.
On a per-bit basis, the 1 Meg x 16 (1K refresh version)
generally offers the best standby and refresh power savings
compared to the other four DRAM organizations. The
DRAM standby current is important in battery-operated
svstems. since DRAMs usuallv draw a large percentage (50
t~ 70 pe~cent) of the total system current ~hen the system
is in sleep or suspend mode.
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TSOP
Notebooks and other compact designs which have height
or layout restrictions can sometimes justify the current cost
premium required to use TSOPs. Additionally, in TSOP, the
x16 does not impose as severe a board space penalty, as does
a x16 SOJ. Table 3 lists the dimensions (length and width)
for the various packages.
SELF REFRESH
III
~
The SELF REFRESH feature built into some DRAMs is
usually indicated by an LL orS suffix. This feature performs
an extended refresh mode, with the exception that no
external clocking is required; that is, the DRAM will refresh
itself via its own internal refresh clock (Fig. 4).
Control of SELF REFRESH is defined by JEDEC and the
following defacto standard timing specifications: tRASS =
1OOfls, tRPS = tRC, tCHD = IOns.
Table 3
PACKAGE DIMENSIONS (in mils)
Device Type
1 Meg x 4
512K x 8
2 Meg x8
256K x 16
1 Meg x 16
PACKAGE SIZE
Conserving board space is always an important design
consideration, especially for laptop and notebook computers. Functionally, DRAMs require more board space than
most other devices. The size between the five options in
small outline J-lead package (SOJ) vary greatly. The 512K x
8 DRAM requires approximately 50 percent more area than
a 1 Meg x 4 DRAM. The 256K x 16 requires approximately
110 percent more area than a 1 Meg x 4 DRAM and 44
percent ITlore area than a 512K x 8. Use of 16 Meg DR_A.Ms
result in significant space savings: 1 Meg x 16 equals 2.5
times and 2 Meg x 8 equals 4 times space savings over
use of 1 Meg x 4. Full-sized outlines are shown here for
comparison:
SOJ
Length
Width
340
445
340
445
679
729
729
1029
n/a
n/a
TSOP
Width
Length
367
467
340
467
467
677
727
727
727
827
OPERATING CURRENT
Operating current is usually of less importance in system
design. When a PC is in the active mode, the DRAM's
portion of current draw is minimal (typically from four to
six percent) compared to the total system current consumption. Wider DRAMs generally offer lower operating currents (10 to 20 percent) in most applications, since fewer
devices are active for a given access, but generally not
enough to outweigh the cost increase, board space increase
and performance reduction they impose.
3.3 VOLTS
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TN-04-15
DT1S.pmS-Rev.2/95
Personal computers are also starting to employ 3.3V
DRAMs. A low-voltage (3.3V) DRAM consumes approximately half the power of a 5V version. The choice of whether
touse5V or3.3V DRAMs is dictated by the voltage platform
selected, which is determined by the CPU and chipset
specifications. Systems requiring memory support beyond
a few years are employing 3.3V DRAMs to ensure long term
support.
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7-20
Micron Technology, Inc., reserves the right
to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
TN-04-1S
DRAM DESIGN CONSIDERATIONS
"'~"OCO,,'"
1-·
FUTURE FEATURES
System deSigns should control WE HIGH at RAS time
during READ and WRITE cycles (see Figure 6) in today's
FAST-PAGE-MODE and EDO designs. Such controlling of
WE will facilitate compatibility with future EDO DRAMs.
The synchronous DRAM is a radical change from the
standard DRAM. Rather than being dependent on time
delays, the synchronous DRAM's inputs will all be clockedin on the positive edge of the system clock. The synchronous DRAM is expected to provide the speed performance
required for 100 MHz and above systems.
Many new features will be available in the near future.
Some of the more important features will be extended
data-out (EDO) and synchronous DRAMs. The EDO DRAM
is a FAST PAGE DRAM with the exception that the data
outputs (DQ) are not tristated by CAS.
The key advantage with EDO is a PAGE-MODE READ
cycle up to 30 percent faster. Since CAS does not tristate the
DQs, tCAS can be minimized and CAS precharge can occur
while the output data is being latched. EDO is considered a
bridge for performance increase until synchronous DRAMs
are a cost effective solution for the very high-end performance system.
CAS
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Micron Technology, Inc., reserves the righlto change produGts or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
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TN-04-16
16 MEG DRAM -2K vs. 4K REFRESH COMPARISON
",",ccce","
MODULES
Modules may use both 2K and 4K refresh depending on
whether orrtotthey have twelve address inputs. If a module
uses parity, such as the 4 Meg x 9 or the 4 Meg x 36, it
probablymixes4Megx4and4Megx 1 DRAMs on the same
module. Because the 4 Meg x 1 DRAM requires symmetric
addressing (11 row-addresses and 11 column-addresses),
using a 4K refresh 4 Meg x 4 DRAM requires that the DRAM
controller support both addressing decodes simultaneously.
This is possible using "redundant addressing," whereby
one of the address bits is duplicated as both a row-address
and as a column-address. Most modules that have parity
will simply use the 2K refresh 4 Meg x 4 DRAM in order to
avoid changes to existing controllers. As shown in Figure 3,
when a 4 tv1eg x 4 with 2K refresh is employed, the numbers
of rows and columns match the 4 Meg x 1, allowing use of
the 4 Meg x 1 for parity.
If the 4 Meg x 4 with 4K rows is implemented, redundant
addressing must be employed, or use of the 4 Meg x 1 for
parity becomes impossible because the number of rows and
col umns does not match. The shaded areas shown in Figure
4 are the portions of the DRAM that can't be used because
of the difference in the number of rows and columns. Table
1 shows an example of redundant addressing. If bit 23 is set
to equal bit 22, it can serve as both the 12th row-address on
the 16 Meg and the 11th column-address on the 4 Meg.
SUMMARY
1. JEDEC has approved two refresh standards at the 16Meg
level, 2K and 4K.
2. 2K refresh is 2,048 cycles in 32ms; 4K refresh is 4,096
cycles in 64ms.
3. Devices with 4K refresh cut current consumption by
20mA under worst-case operating conditions.
4. Devices with 4K refresh have half the page depth of a 2K
device.
S. Existing SV standard modules generally wi1luse the 2K
refresh standard DRAM.
1,024
Columns
1,024
Columns
2,048 Columns
-------- --------
~
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2,048 Columns
2,048 Columns
~~
4 Meg x 4
(2K)
2,048 Rows
4 Meg x 4
(2K)
Z
o
Figure 3
-I
Figure 4
m
Table 1
ADDRESS MULTIPLEXING ASSIGNMENT FOR DRAM ROWS AND COLUMNS
DRAM Adress
Memory
Controller
Address
TN-04-16
DTI6.pm5-Aev.2/95
AD
1
A1
A2
A3
Column
2
3
4
Row
10
11
12
13
A4
A5
A6
5
6
7
14
15
16
7-24
A7
A8
A9
A1D
8
9
20
23
17
18
19
21
A11
22
Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995,MlcronTechnology, Inc.
UII::::I=ICN
1-·
,","",,,,,,,
LPDRAMS
VS.
TN-04-19
SLOW SRAMS FOR MAIN MEMORY
LOW-POWER DRAMS
vs. SLOW SRAMS FOR
MAIN MEMORY
TECHNICAL
NOTE
INTRODUCTION
The market for portable computers such as notebooks,
laptops and palmtops is extremely competitive and fastpaced. Designers of these systems are continually trying to
minimize power, cost and size without compromising
performance. One of the most challenging areas is memory
design. To meet their design constraints, manufacturers are
using either low-power DRAMs or slowSRAMs for memory.
This technical note discusses memory design and the tradeoffs associated with each of these types of memory.
Of course, the size of a chip can be increased only so far
before yield drops. When 4 Meg DRAMs were the highest
density DRAM being manufactured, only 1 Meg SRAMs
were available. A designer would only need one-fourth the
number of 4 Meg DRAM parts over 1 Meg SRAMs. Table 1
compares the relative cost of several arrays; DRAMs always
have the cost advantage.
SIZE AND WEIGHT
Typically, DRAMs are a generation ahead of SRAMs and
are thus a factor of four ahead in density. This is because
SRAMs take up much more silicon die area for a given
memory density. Fora typical nwmory si~.,', SRAMs rCljuire
four times as many devices ilnd four linH's 111<' board areil
(see Table 1).
DRAMs use multip1cxed row and column addressing
whereas SRAMs use unmultip1cxed addressing. For an
identical size of memory, DRAM packages use less pins and
are smaller. This contributes 10 their effectiveness in minimizing space.
A designer should be cautious in "hoosing a slow SRAM
fora portable application due to thc board spiln' n'quired to
implement the memory system. Similarly, the increased
number of devices will make the portable heavier.
LPDRAMs AND SLOW SRAMs
Users of portable devices want long battery life. Reducing power consumption to meet this need is critical. This is
why portables use low-power extended refresh DRAMs
(LPDRAMs) instead of standard DRAMs. A standard DRAM
has standby currents of 3mA at a 1511s refresh cycle.
LPDRAMs have standby currents ranging from 1mA to
200I1A, and a refresh interval of 12511s (extended refresh).
LPDRAMs offer a very low-power standby power mode
called BATTERY BACKUP (BBU) mode. BBU is the lowest
DRAM power mode possible that still retains data. It consists of a CAS-BEFORE-RAS (CBR) REFRESH cycle at the
slowest possible cycle rate.
Some designers have used slow SRAMs in their designs
since they offer low standby currents. Slow SRAMs are
usually defined as SRAMs with a cycle speed of 80ns or
slower. They have low standby currents when compared to
standard DRAMs.
A standard memory configuration was chosen in order to
compare the two types of memory. In portables, a 2MB
memory in a x16 configuration is quite common. Memory
will typically be a 4 Meg DRAM (x4 or x8) or a 1 Meg SRAM
(x8). These memory arrays are compared in the following
paragraphs and in Table 1 on the next page.
POWER
One of the main problems with notebook computers
today is thatthe battery life is too short. Even with the large
batteries used today, battery life can be less than two hoursusers are demanding eight hours or more.
Slow SRAMs have an advantage in standby and active
currents (typical). As you can see from Table 1, slow SRAM
standby current can be much lower than that of DRAMs.
This is because only a portion of the memory is accessed at
any given time, so much of the memory is in standby mode.
COST
In the highly competitive notebook market, reduction of
cost is crucial. Because an SRAM bit cell uses four times as
many transistors as a DRAM, the amount of silicon area
used is much larger. Cost is proportional to silicon area, so
for a given amount of memory the SRAM takes up more
area and costs more. This is clearly seen in the marketplace
since 256K SRAMs are more expensive than 256K DRAMs,
1 Meg SRAMs are more expensive than 1 Meg DRAMs, etc.
TN-04-19
DT19.pm5- Rev. 2195
SUMMARY
The portable market is so competitive that cost is usually
the overriding consideration. Even if battery time can be
extended slightly with slow SRAMs, cost and increased
board space usually prohibit their use. DRAMs have been
and will likely continue to be the part of choice in portable
applications.
7-25
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc.
•
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MICRON
1-·
TN-04-19
LPDRAMS vs. SLOW SRAMS FOR MAIN MEMORY
"'""'COG""
Table 1
2MB, 16-BIT-WIDE MEMORY
1 MEG x4
DRAMS
PART TYPES
Number of Devices Required
Total Cost'
Active Icc Current2 , 3
I
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128K x 8
SLOW SRAM4
128K x 8
SLOW SRAM5
UNITS
4
4
16
16
No. of Devices
1.0
1.1
4.3
4.3
Relative Cost
70
70
85
85
ns
1.2
1.2
1.6
0.8
mA
(Typical)
600
600
32
32
fLA
(MAX)
240
160
140
140
mA
(Typical)
Minimum Speed
Standby/BBU Current2
512K x 8
DRAMS
(MAX)
141
94
90
90
mA
Minimum Board Space Used
0.9
1.3
7.4
7.4
(TSOP) in2
Weight6
1.0
1.4
5.8
5.8
Relative Weight
NOTE:
1.
2,
3.
4.
5.
6.
Costs are relative to the 1 Meg x 4 DRAM.
Assumes an 80ns part in FAST PAGE MODE for DRAMs, 85ns part for SRAMs.
For the x8 devices, only a portion of the array is active at anyone time.
Standard slow SRAMs
Low-power slow SRAMs
Weight is relative tei the 1 Meg x 4 DRAM.
:J:
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TN-04-19
DT19.pm5 - Rev. 2195
7-26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
UII::::I=ICN
1-·
TN-04-20
SELF REFRESH DRAMS
"'"",COG""
SELF REFRESH
DRAMS
TECHNICAL
NOTE
INTRODUCTION
DRAM memories targeted for the low-power, portable
market are providing several new features to help maximize power savings. One of these new features is the SELF
REFRESH mode. DRAMs having this new feature are referred to as SELF REFRESH DRAMs and provide the user
with a very low-current, data-retention mode.
This mode has been approved by JEDEC and is quickly
becoming an industry-standard feature. Most 3.3VDRAMs
will be offered with this feature, as will many future 5V
DRAMs.
(sleep or suspend). It is similar to the extended refresh
mode of an LPDRAM except the SELF REFRESH DRAM
utilizes an internally generated refresh clock while in the
SELF REFRESH mode.
During a system's suspend mode, the internally generated refresh clock on the DRAM replaces the DRAM controller refresh Signals. Therefore, it is no longer necessary to
power-up the DRAM controller while the system is in the
suspend mode. Consulting the devices' data sheets will
determine the power savings achieved.
SELF REFRESH DRAMs vs LPDRAMs
USING SELF REFRESH
Low-power, extended-refresh DRAMs (LPDRAMs) have
the same functionality as a standard DRAM, except they
have been tested to meet the lower CMOS standby current
and the extended refresh specifications. SELF REFRESH
DRAMs, on the other hand, require additional circuitry be
added to the standard DRAM to perform the SELF REFRESH function.
SELF REFRESH introduces the m'w paranwll'rs tRASS,
tCHD and tRPS. These new paraml'll'rs an' shown in
Figure 1. The DRAM's SELF REFRESH modI' is iniliall'd by
executing a CAS-BEFORE~RAS (CBR) REFRESH cycle and
holding both RAS and CAS LOW for a specified period.
The industry standard for this value is 100~s minimum
(tRASS). The DRAM will remain in the SELF REFRESH
mode while RAS and CAS remain LOW. Once CAS has
been held LOW for tCHD, CAS is no longer required to
remain LOW and becomes a "don't care."
SELF REFRESH MODE
SELF REFRESH mode provides the DRAM with the
ability to refresh itself while in an extended standby mode
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EXITING SELF REFRESH
READ CYCLE
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~ OPEN~~~~~~~~~----++---------tWRP
WE
tWRH
'WRP
'WRH
~:~ :ij/0'/#/J- ~~_//#/#//#$//$/##//$$/J- -./#/M#//#J
~
DON'T CARE
~
UNDEFINED
Figure 1
SELF REFRESH CYCLE UTILIZING DISTRIBUTED CBR REFRESH
TN-04-20
DT20.pm5 - Rev. 2195
7-27
Micron Technology, Inc., reserves the right to change products or specilications without notice.
©1995, Micron Technology, Inc.
MIC:RON
TN-04-20
SELF REFRESH DRAMS
m~"ocoo"c
1-·
The SELF REFRESH mode is terminated by taking RAS
HIGH for lRPS (the minimum time of an operation cycle).
Once the SELF REFRESH mode has been terminated, the
user can access the DRAM normally.
a row at regular intervals, a circuit would sense when the
array needs to be refreshed and then sequence through the
rows until all had been refreshed. When exiting a burst type
SELF REFRESH, the entire array must be refreshed before
any accesses are allowed, regardless of the type of refresh
used (see Figure 2). This full burst is necessary because you
may have exited SELF REFRESH just before the entire array
was going to be refreshed. If the burst is not performed
when exiting this type of SELF REFRESH, you may violate
refresh requirements and lose data.
Micron's devices allow you to access the DRAM as soon
as SELF REFRESH is exited, while other manufacturers'
devices may require a full burst when exiting, regardless of
the refresh used. To prevent possible compatibility problems, you may want to design the controller to perform the
burst when exiting SELF REFRESH.
HOW IS SELF-REFRESH DONE?
•
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SELF REFRESH can be implemented on the device in two
ways. One method utilizes a distributed method and the
second uses a wait and burst method. Micron devices use
the distributed method.
Devices that utilize the distributed method will refresh
the rows at a regular rate, utilizing the CBR REFRESH
counter to turn on,ows. In a system that utilizes distributed
CBR REFRESH as the standard refresh, accesses to the
DRAM can begin as soon as SELF REFRESH is exited. The
first CBR pulse should occur within the time of the external
refresh rate prior to active use of the DRAM to ensure
maximum data integrity and must be executed within three
external refresh rate periods, Since CBR REFRESH is commonly implemented as the standard refresh, this ability to
access the DRAM immediately after exiting SELF REFRESH
is a big benefit over the burst scheme described later. If
anything other than CBR REFRESH is used as the standard
refresh, a burst of all rows needs to be executed when
exiting SELF REFRESH. This is because the CBR counter
and the DRAM controller counter will not likely be at the
same count. If they're not at the same count and both are
being used in the distributed method, then refresh will be
violated and data will eventually be lost.
An alternative way to implement SELF REFRESH is to
use an internal burst refresh scheme. Instead of turning on
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RAS
~:t::::
DO
~gr::::
EXITING SELF REFRESH
________
.I~
COMPLETE BURST REFRESH OF
ALL ROWS MUST BE EXECUTED
~~FORE
_ _'_RP_S_ _
ACCrSING THE DRAM
JL
)-- O P E N - - - - - - - - - - - - - H - - - - - 'WAP
WE
I~.-'R-A-SS---I()I-()
SUMMARY
1. SELF REFRESH mode allows additional power savings
for portable applications since the DRAM controller is no
longer required to remain powered-up while the system
is in the suspend mode.
2. The mode is initiated by executing a CBR REFRESH with
RAS and CAS remaining LOW forat least lOOlls.
3. The SELF REFRESH mode remains active until RAS is
taken HIGH.
4. You may access the DRAMas soon as SELF REFRESH has
been exited, provided you use distributed CBR REFRESH
as the standard refresh.
'WRH
'WRP
'WRH
~:~ =1';/###&- -W4~$;/$;/$;////;/$//;/;//;1;1g- -W;1$;/ffi:
~
DON'T CARE
~
UNDEFINED
Figure 2
SELF REFRESH CYCLE UTILIZING BURST REFRESH SCHEME
TN-04-20
DT20.pm5 - Rev. 21'95
7-28
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc.
MICRON
1-·
TN-04-21
EXTENDED DATA-OUT
",","CO,,,,,
REDUCE DRAM CYCLE
TIMES WITH EXTENDED
DATA-OUT
TECHNICAL
NOTE
INTRODUCTION
As system speeds increase, DRAM manufacturers are
developing methods to decrease the cycle times of
DRAMs. The most common version of DRAM is FAST
PAGE MODE (FPM) but the addition of a feature known
as extended data-out (EDO) may become more common
because it allows shorter page cycle times with only a
minor functional change from FP. Because the device with
EDO doesn't turn off the output drivers when CAS goes
HIGH, it can have a shorter cycle time than FP.
•
This article first covers some basic differences between
FPM and EDO during a PAGE READ cycle. Then a comparison of cycle times between FPM and EDO is done,
followed by a few examples under different address setup
conditions. When moving from a PAGE READ into a
PAGE WRITE, the timing differs slightly between FPM
and EDO; this difference is discussed. Finally, the issues
involved when replacing an FPM device with iln EDO
device are addressed.
EDO OFFERS ADVANTAGES
•
It has a shorter PAGE READ cycle time than FPM
devices.
• Data is valid on the falling edge of CAS, so the
designer can use that edge to strobe data.
• A 70ns EDO device has the same PAGE READ cycle
time as a 40/50ns FPM DRAM.
RAS
~~ =
CAS
~~ =
Implementing EDO in place of FPM devices in a
system can be as easy as knowing when the bus
needs to be deactivated and using OE or WE instead
of CAS to accomplish it.
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UNDEFINED
Figure 1
FPM READ CYCLE
TN-04-21
DT21.pm5 - Rev. 2/95
7-29
Micron Technology, inc., reserves the righllo change products or specifications without notice,
©1995, Micron Technology, Inc
MICRON
1-·
TN-04-21
EXTENDED DATA-OUT
"'""oco"',,,
BASIC DESCRIPTION
EDO
FPM and EDO allow fast data operations within a row.
The differences are in the deactivation of data-out when
CAS goes HIGH and the operation of OE and WE. The
following section highlights differences between the FPM
and EDO when reading within a page.
Characteristics:
• The column-address is latched when CAS falls.
• The output drivers are not turned off when CAS
goes HIGH.
• Minimum EDO read cycle time is determined by
the greater of the two equations below.
FPM
•
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Equation 1: tpc = tCAS + tcp + 2tT
Equation 2: tpc = tcp A - (tcp + tT)
Characteristics:
• The column-address is latched when CAS falls.
• The output drivers are turned off when CAS goes
HIGH.
• Minimum FPM READ cycle time is tpc = tcp A + tT,
(tCPA = tAA + tT)
OE and CAS work together to enable and disable
the outputs.
• 'AlE can disable the outputs.
The cycle begins with RAS strobing-in a row address,
followed by CAS strobing-in a column-address. To continue to access columns within that row, CAS is toggled as
addresses change.
Figure 1 shows a typical FPM READ cycle. The columnaddress is latched into the part when CAS falls, so columnaddress setup and hold times are referenced to the falling
edge of CAS. Notice tOFF; this specification tells you that
CAS going HIGH turns off the output drivers.
EDO allows fast access within a row and uses CAS to
latch the column-address, as does FP, but does not turn off
the output when CAS goes HIGH. This last feature allows
EDO to cycle faster than FPM because the user does not
have to wait for valid data to appear before starting the
next access. In other words, data can appear after CAS has
been pulled HIGH, and it will stay valid for 5ns after
CAS transitions LOW again (tCOH), as shown in Figure 2.
The output will deactivate when both RAS and CAS are
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tpc
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tCPAI
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tcp
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ROW
COLUMN (C)
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tAA
tCPAI
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tCAC
VALID DATA (8)
_iRRH
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~
~
VALID DATA (A)
OPEN
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= I ~Rcf'l
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teAs ~I
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tRASP
tCSH
Z
Data is not disabled I.J
after CAS goes HIGH.
are latched.
tT
VALID DATA (C)
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UNDEFINED
Figure 2
FPM READ WITH EDO
TN-04-21
DT21.pm5 - Rev. 2/95
7-30
Micron Technology, Inc" reserves the right to change products or specifications without notice.
@1995,MicronTechnology,lnc
UII::::RCN
TN-04-21
EXTENDED DATA-OUT
"'~"'oc, "
1-·
HIGH, so IOFF will now be referenced from the rising
edge of RAS or CAS, whichever occurs last. OE will also
deactivate the outputs, as shown in Figure 3. In order to
RAs
~:~=~'-
accomodate systems where OE is tied LOW, WE now
has the ability to turn off the output drivers as well (see
Figure 4).
__________________________________________
VALID DATA (D)
The DOs go back to
Low-Z if tOES is met.
The DOs remain Hlgh-Z
until the next CAS cycle
if IOEP is met.
The DOs remain High-Z
until the next
cycle
CAs
if toEHC is met.
~:~=~'-
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~
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00
OE
~:g~
VAUDOATA(A)
VALIDDATA(8)
INPUTDATA(C)
~:~~-----------------c-.~I-------+--------+------T'--------r
We may be used to disable the DOs to prepare
The DOs go to High-Z if WE falls, and if twpz is met,
will remain High-Z until CAS goes LOW with
for input dala in an EARLY WAITE cycle. The DOs
will remain High-Z until CAS goes LOW with
WE HIGH (Le., until a READ cycle is initiated).
~
DON'T CARE
~
UNDEFINED
Figure 4
OUTPUT DISABLE USING WE
TN-04-21
DT21.pm5 - Rev. 2195
7-31
»
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WE HIGH (Le., until a READ cycle is initiated).
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Figure 3
OUTPUT ENABLE AND DISABLE USING OE
RAs
-
Micron Technology. Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
,
1-·
TN-04-21
EXTENDED DATA-OUT
'''"''''00'"''
25n8
10n$
-
_2.5n$
10n$
25n8
_ _ 2.5n$ _
25n8
_ 2.5n$
10n$
--f
COL ADDR
VIHVIL -
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D
P<
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>= 35n$
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>= 35n$
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UNDEFINED
Figure 5
EDO MINIMUM FAST-PAGE-MODE READ CYCLE TIME
AVAILABLE ON 60ns DRAMs
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READ CYCLE TIMES
o PAGE
This section examines the different cycle times of FPM
l> and EDO to see how they are generated. Figure 1 shows that
r- CAS must stay LOW until data-out becomes valid (if CAS
Z
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sition time and the tHL is the CAS HIGH-to-LOW transition time.
goes HIGH before valid data, then the output buffers would
turn off). The longest access time specified for the device is
from CAS HIGH to data-out (tCPA). CAS can't go HIGH
before tcpA, or data-out will not fire. Add a transition time
to pull CAS HIGH and vou have the cvcle time tpC"."" =
tCPA + tT.
"m
EDO works a bit differently. tcpA is still the longest
access time, but is no longer the limiting parameter in cycle
time. This is because some of this access time includes
CAS precharge (CAS HIGH time). In FP j you can't bring
CAS HIGH before data is valid because CAS HIGH turns
data off. Since CAS HIGH doesn't turn off data in the EDO
device, you can bring CAS HIGH before data is valid and
begin precharging CAS while you wait for data-out. This
overlap of CAS precharge and getting data-out means
tcpA is no longer the limiting parameter.
The theoretical minimum page-mode cycle time is determined by one of the two equations below, whichever is
greater (see Figure 2). tLH is the CAS LOW-to-HIGH tran-
TN-04~21
DT21.pmS- Rev. 2/95
Equation 1:
Equation 2:
The minimun1_ cycle is achieved by providing valid coluIT'.n
addresses early enough that tAA is not limiting. In the past,
transition times were assumed to be 5ns each for the purpose of specifying cycle times. However, in many cases, the
transitions between 0_8 and 2.4 volts do not require 5ns, so
the EDO devices allow for 2ns transitions.
For example, a page-mode cycle time of 25ns can be
achieved when using Micron 60ns EDO DRAMs with a
tCPA of 35ns when transitions are 2.5ns or less (see Figure
5). This represents a 40 to 60 percent improvement over the
same cycle times provided by 60ns devices with conventional FAST PAGE MODE operation. Similar improvements are provided on the SOns and 70ns speed grades,
which have theoretical minimum cycle times of 20ns and
30ns, respectively.
7-32
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-04-21
EXTENDED DATA-OUT
"C~"ocoo'"c
EXAMPLES: EDD AND FP
The table below compares page READ cycles of FPM and
EDO under two different conditions: minimum columnaddress setup and maximum column-address setup time.
The timing diagrams for the following examples assume
that RAS is already LOW, WE is HIGH and OE is LOW. A
70ns DRAM is used with the following timing:
DESCRIPTION
IpC (MIN)
ICAS (MIN)
ICLZ (MIN)
IOFF
FP
EDO
45
30
20
12
0
0
0-20
0-20
5
5
IT
Figures 6 and 7 show FPM and EDO cycles with plenty of
address setup time. On an FPM device with plenty of
address setup time, we can operate at IpC = 45ns (the
minimum allowed), and data is valid for 5ns.
EDO under the same address setup time looks different
(see Figure 5). Now the minimum cycle time is 32ns. Notice
that data doesn't appear on the bus until you are already
into the second access (8ns of CAS precharge for the next
cycle is already completed when data appears). This is the
overlap that allows the shorter cycle time. IpC is 32ns and
data is valid for 12ns.
Under these conditions, EDO cuts the cycle time over a
FPM device by 29 percent, or increases burst rate by 41 percent (22 MHz to 31 MHz). In addition, even with the shorter
cycle time, data-out is valid for 12ns onthe EDO as opposed
•
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DATA3 '
THIRD ACCESS
Figure 6
FPM PAGE READ CYCLE WITH MAXIMUM ADDRESS SETUP
tpc = 45ns; DATA VALID FOR 5ns
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RAS vlL
m
Column-address is latched when CAS falls.
:::·~::;:;:;;=~~~L5.5~~~~\I---_
THIRD ACCESS
~ DON'T CARE
~
UNDEFINED
Figure 7
EDO-PAGEREAD CYCLE WITH MAXIMUM ADDRESS SETUP
tpc = 32ns; DATA VALID FOR 12ns
TN-04-21
DT21.pm5 - Rev. 2/95
7-33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-04-21
EXTENDED DATA-OUT
","",,,n,
to only 5ns on the FPM device. We could get more performance by using shorter transition times on the EDO device,
but we used 5ns to make the comparison between FPM and
EDO easily understandable.
Figures 8 and 9 show FPM and EDO cycles with minimum address setup time. In this case, the address becomes
valid coincident with CAS falling. For FP, data won't be
valid for tAA(35ns}, so CAS must be held LOW until that
time (see Figure 8). Since the minimum CAS HIGH time is
IOns, the cycle time is 50ns (tAA + tcp + tT). Data-outis valid
for 5ns.
-
Looking at EDO under the same conditions, (Figure 9) it
still takes tAA (35ns) after the addresses are valid to get
valid data-out, but now you don't have to wait before
pulling CAS HIGH. Notice that CAS has been pulled HIGH
and precharge has been completed for the next cycle, before
Data 1 appears on the bus. Just before data becomes valid,
CAS drops and the second address is latched. Again, there
is an overlap of starting one cycle and finishing the other.
Now tpc = 32ns, and data-out is valid for 7ns.
In this case, EDO cycle time is 36 percent less than the
FPM cycle time (providing a 55 percent improvement in
burst rate); EDO data is valid 2ns longer.
30
ADDR
-I
m
o
DQ
~~=~~,~yt~~~~~~~~~~~~~~~~==~~~
,
~g~ =-:--OPEN --4lixlN ~-----'(I)/.i¢
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m
CAS
\/"'-
\tiL -
ADDR
DQ
~
DON'TeARE
~
UNDEFINED
Figure 9
EDO-PAGE READ CYCLE WITH MINIMUM ADDRESS SETUP
tpc =32ns; DATA VALID FOR 7ns
TN-Q4-21
DT21.pm5- Rev. 2195
7-34
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology. Inc
MICRON
F·
TN-04-21
EXTENDED DATA-OUT
"'""OC,,'"
These examples should point out another big advantage
ofEDO. Not only can you operate at a shorter cycle time, but
data is available longer for the system to sample. Since data
is guaranteed to be valid as CAS falls, that edge may be used
to sample data.
EDO device must have the correct combination of RAS,
CAS, OE and WE to deactivate the output. This means that
any time the designer is counting on CAS by itself to turn off
the output drivers, bus contention may occur if something
else tries to drive the bus. This may occur in the following
situations:
• PAGE interleave memory banks
• Moving from PAGE READ directly into a PAGE
WRITE (within the same page)
• Whenever anything other than the DRAM is
driving the bus, and OE and RAS are LOW while
CAS is HIGH
(This last case is uncommon and should not mandate a
change for most systems.) Interleaved memory need only
make use of OE or WE instead of CAS when turning off the
output drivers; then EDO can be used in place of FPM
DRAMS.
70ns EDO INSTEAD OF 40/S0ns DRAMs
EDO can provide the FPM READ speed of a 40/50ns
DRAM. Even though a 40/50ns DRAM has a 40/50ns
tRAC, the FPM READ cycle time is 30-35ns, which is the
same page READ cycle time as that of a 70ns EDO device.
EASY TO IMPLEMENT
An additional benefit of EDO is the ease of implementation. PAGE READ or WRITE cycle time is cut but the major
difference between FPM and EDO is that the FPM device
will stop driving data-out when CAS goes HIGH and the
RAS
CAS
FP
ADDR
~t =
CAS deactivates output.
tpc= 45ns
DQ
~gt =
:J:
EDO
o»
Z
PAGE READ
CYCLE
ADDR
FIRST
EARLY WRITE
CYCLE
SECOND
EARLY WRITE
CYCLE
r-
Z
V,H
VIL -
: 20
VIH _
WE V1L -
DO
-
~gt =
,
EA:~WRITE :
CYCLE
SECOND
EARLY WRITE
CYCLE
[Zl DON'T CARE
m
UNDEFINED
Figure 10
EXAMPLE FPM AND EDO READ TO WRITE CYCLES
tpc = 45ns
TN-04-21
OT21 ,pm5 - Rev. 2195
o
~
m
VIL VIH -
DE ~H
L
~
o
VIH _
~t =
•
m
VIL -
WE
CAS
F===='------""'PC-~7.45CCns,-
VIH VIL -
7-35
Micron Technology, Inc., reserves the nght to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-04-21
EXTENDED DATA-OUT
;,,~"'oo'"'
READ TO WRITE CYCLES
SUMMARY
Since CAS doesn't turn off the output devices on an EDO
device, caution should be used when turning the bus around
on a shared 10 device. To demonstrate the difference,
Figure 8 shows the transition from a PAGE READ to a
PAGE EARLY WRITE on the same page. When using the
FPM version, OE can be tied LOW and CAS can be used to
deactivate the output. Notice that OE is also tied low on the
EDO device and this cycle is still possible .
EDO is simply a modified FPM cycle and can be used in
systems to increase performance. It allows system designers to improve their cycle times and system performance
since data is present for a much longer time, even during
short cycle times. Because each generation device has different timing limitations, be sure to consult the data sheet
for exact timing.
•
-I
m
o
::I:
-oZ
»
r
Z
o
-I
m
TN-04-21
DT21 .pm5 - Rev. 2195
7-36
Micron Technology, Inc., reserves the right to change products or speclfications without nolleD.
@1995, Micron Technology, Inc
MICRON .
1-·
TN-04-22
256K x 16 DRAM
",""ceon,
256K x 16 DRAM
TYPICAL OPERATING
CURVES
TECHNICAL
NOTE
[NTRODUCTION
system. For worst-case design limits, the system designer
should refer to the individual data sheets.
These curves represent the typical operating characterisics of Micron's 70ns256Kx 16 DRAMs. They maybe used
o calculate the typical operating parameters of a memory
256K X 16 OPERATING CURVES
tRAC vs. Temperature
65
.,
0 62
61
59
/
5.5V
..:
60
/'
5.0V
--V
63
c
9=
4.5V
-*""
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/
~
l-J..------ ~
V/ V
~jIt
V
.,
13
0 12
~
/"
o
W
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10
M
100
1m
1~
jr
/'
11
9
m
l.---
c
i.JI
-
!-II
14
fA
V
/"
V
tCAC vs. Temperature
15
va'
L0
~
V
V
J.;.-.---- ~ V
--yV
m
W
~
Temperature (Oe)
I--
V
---
-*""
......
V
o
V
M
100
---
-I
m
i-'"
4.5V
5.0V
I-I--
5.5V
1m
1~
Temperature (Oe)
o
:::r::
z
-
o
l>
rZ
j..II
V
,...
--- v
t-...
/
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1....--
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1/
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V./
m
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100
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4. SV
5.0V
TN·04·22
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V
V
V
~
v
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......
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m
1~
~
'/
---
./
I........
/
S.SV
1m
~_
/'
j.e"
V
W
M
100
4. SV
5.0V
S.5V
1m
1~
Temperature ee)
Temperature (Oe)
DT22.pm5 - Rev. 2/95
V
V
---
/
V
o
f.JI
V/ ~
./
~
/
23
22
21
20
19
tRP vs. Temperature
tAA vs. Temperature
31
30
29
28
27
., 26
25
o
-I
m
7-37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-04-22
256K x 16 DRAM
,CO""""'''
256K x 16 OPERATING CURVES (continued)
tRCDmin vs. Temperature
4
tClZ vs. Temperature
11
10
3
k
~
-
r--t-- '....-~
-
1--
9
f-e
!
~
8
N
..J
Y
~
I --5.0V
I --.oi-l
-+1--1-1
-+---+.:
==1r==5=t=5~
~II
o
M
00
00
100
1M
4.5V
~
-
o
1~
0
Temperature (OC)
Operating Current vs. Cycle Time O°C
Refresh vs. Temperature
-----.-
1000
----
o-
........
........
Z
Z
•
:1
200
2000
J:
»
r
6
Temperature (OC)
-I
m
7
50
o
-I
m
55
60
100
g
5.0V
~
II --.----
::::---..
~~
65
70
75
Temperature (OC)
~
80
1
~~
~
8.
III
o 10
~
85
5.0V
""*- 5.5V
-----r
c
4.5V
I!!
5
o
g>
""" ~
100
~
""*- 5.5V
........
r--::::--
4.5V
~
I
5
90
100
1000
10000
Cycle Time (ns)
100000
Icc Operating Current vs. Temperature
-
-----.-
160
155
~
150
~ 145
~ 140
-; 135 ~
c
~ 130
8. 125
~ 120
.l! 115 ~ I.....
110
105
100
TN-04-22
DT22.pm5 - Rev. 2/95
o
20
-..- ----.t.
40
-
""*- 5.5V
r-.
r-- f.e
60
80
100
Temperature (OC)
7-38
4.5V
5.0V
r120
140
Micron Technology, Inc., reserves the right to change products or specifications without notic.,
©1995, Micron Technology, Inc.
MICRON
.-.
TN-04-23
4 MEG DRAM
m"",coe, ""
4 MEG DRAM TYPICAL
OPERATING CURVES
TECHNICAL
NOTE
INTRODUCTION
system. For worst-case design limits, the system designer
should refer to the individual data sheets.
These curves represent the typical operating characteristics of Micron's 70ns 4 Meg DRAMs. They may be used to
calculate the typical operating parameters of a memory
5V PRODUCT DC AND AC PARAMETER PERFORMANCE
Access Time from RAS vs. Temperature
Access Time from CAS vs. Temperature
14
70
--II- 4.5V
65
~
.....- 5.5V
60
/ ~
~
./'~ ~
45
--II- 4.5V
/.
....... 5.0V
/'
;:::-
~~
y
13
~
V
·15
-:::
10
I-
9
40
-35
.....- 5.5V
12
~
·55
....... 5.0V
5
25
45
65
Temperature eel
85
8
-55
105 125
-35
-15
/ ~V
~~
~
~
•
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m
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fA
:::J:
~v
-o
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5
25
45 65
Temperature eC)
85
105 125
»
r
Z
Access Time from Column-Address vs. Temperature
-I
RAS Precharge Time vs. Temperature
33
26
25
--II- 4.5V
24
....... 5.0V
23
.....- 5.5V
/
1/
/
v:::;; ~
-
-----
70°C
3'--
j---
100°C
-k- 125°c
,
, ~-t-
:-I
100
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--
--- t:::=::t-- f---
,
-
C
j
10
4.5
4.7
4.9
5.1
5.3
10
4.5
5.5
Vee (V)
1
1_
Jc
4.7
4.9
5.1
5.3
5.5
Vee (V)
-I
m
o
:t
-oZ
»
rZ
o
-I
m
TN-04-23
DT23.pmS - Rev. 2195
7-41
Micron Technology, Inc., reserveslhe right to change products or specifications without notice.
©1995, Micron-Technology, Inc.
MIC:RON
1-·
TN-04-23
4 MEG DRAM
,,,",cwe","
3.3V PRODUCT DC AND AC PARAMETER PERFORMANCE
Access Time from RAS vs. Temperature
Access Time from CAS vs. Temperature
75
15
3.0V
70
--------.-
65
3.3V
3.6V
I60
o
V
,.-/
V
./
V
~ .-/'
V
.-/'
/"
•V
V
=-----
50
t""'
-55
VI--
-35
-15
13
-
105
-I
o
30
m
--------.-
3.3V
/
3.6V
Z
/
V / ' ---;
.....
/
./ V;
22
-55
m
~ ~./
/"
V
~
-35
-15
5
25
45
65
Temperature
85
105 125
-35
-15
/
3.0V
35
-----
----.-
33
...~
V- /
3.3V
3.6V
<,./
~ ~/
~
/
IW~ ~ V
25
~
23
V /! ::/"
V/
V
21
5
25 45 65
Temperature (OC)
85
-55
105 125
Standby Current (TTL) VS. Temperature
-35
-15
5
25 45 65
Temperature (OC)
85
105 125
Standby Current (CMOS) vs. Temperature
140
450
400
--
r----
350
«
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RAS Precharge Time vs. Temperature
V
20
~
---- l------'V
V
~
-----
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-55
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125
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3.0V
v/
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37
28
J:
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10
Access Time from COlumn-Address vs. Temperature
32
3.3V
./"
~ 11
----
85
3.0V
~12
o
~
5
25 45 65
Temperature (OC)
--------.-
14
::[1 I III I I II
~
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~ 55
•
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3.6V
300
--------.-
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U
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TN-D4·23
DT23.pm5 - Rev. 2195
-35
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85
90
60
-55
105 125
7-42
"--",
~
70
~
5
25 45 65
Temperature (OC)
.
80
50
-55
110
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.... - I--- V
150
"'"'
120
3.3V
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100
130
I-------""
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~'"" t-----.
~
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.......
3.3V
3.0V
-//
... /
............... f-..
-feI---
5
25 45
65
Temperature (OC)
3.6V
85
105
125
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1--
TN-04-23
4 MEG DRAM
"'""'C""""
3.3VPRODUCT DC AND AC PARAMETER PERFORMANCE (continued)
Operating Current (FAST PAGE MODE) vs. Temperature
Operating Current vs. Temperature
('PC ~ 40ns Cycle Time, Speed Grade ~ ·7)
('RC ~ 130ns Cycle Time, Speed Grade ~ -7)
--.....
60
55
"""*""
40
3.6V
36
--.....
34 ~
"""*""
38
3.3V
3.0V
....
3.6V
3.3V
3.0V
;( 32
.:;
....
'3
£
30
28
26
40
35
·55
24
22
·55
,
-35
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5
25
45
65
Temperature (OC)
85
105
·35
·15
125
5
25
45
65
Temperature eC)
85
105
125
(Temperature
~
m
O°C)
o
100
I'll
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g
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Iii
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10000
Cycle Times (ns)
7-43
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DT23.pm5 - Rev. 2195
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3.0V
3.3V
f-- -j-f--
TN-Q4-23
3.6V
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•
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Operating Current vs. Cycle Time
1000000
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
o
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m
MII:::I=ICN
TN-04-23
4 MEG DRAM
"'~"'co"' "
1-·
3.3V PRODUCT DC AND AC PARAMETER PERFORMANCE (continued)
Static Refresh vs. Vee
Dynamic Refresh vs. Vee
1000
1000
.-
.<:
~
II:
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70°C
-.~
100°C
.<:
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125°C
~
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100
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e
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100°0
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~1---=~'
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~~-:tT.~.~
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10rnuonnn
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3.1
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3.3
3.4
3.5
3.6
3.6
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Vee (V)
BATTERY BACKUP
m
SELF REFRESH
120
110
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TN-04-23
pT23.pm5- Rev. 2195
7-44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Mic~n
Technology, Inc.
MICRON
TN-04-24
4 MEG DRAM-ACCESS TIME vs. CAPACITANCE
"'~"C'OO,,"
1-·
4 MEG DRAM-ACCESS
TIME vs. CAPACITANCE
TECHNICAL
NOTE
INTRODUCTION
These curves for the 4 Meg DRAM show typical access
times with different capacitive loading. For worst-case
design limits, the system designer should refer to the individual data sheets.
tRAC vs. Capacitance
25°C
62
tRAC vs. Capacitance
85°C
62
I
[
61
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60
__ 5.5V
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u
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57
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56
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57
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60
100
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5.5V
60
100
Capacitance (pF)
Capacitance (pF)
tCAC vs. Capacitance
25°C
tCAC vs. Capacitance
85°C
•
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55
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20
60
100
20
Capacitance (pF)
TN-04-24
DT24.pm5 - Rev. 2/95
60
100
Capacitance (pF)
7-45
Micron Technology, Inc., reserves the nghttochange products or specifications withou tnotlce.
©1995, Micron Technology, Inc.
MICRON
F·
4 MEG DRAM-ACCESS TIME
"'""0","",
'AA vs. Capacitance
25°C
28
25
---
., 24
':'23
26
c(
$ 22
~
21
~
20
19
~
---
27
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'CPA vs. Capacitance
25°C
'CPA vs. Capacitance
85°C
----- -----
100
,---:::' V
,---: j..---"
24
l---:---:
~
----
------
~ 25
9
----- -----
23 ~
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22
i
,
20
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---- ....-- ----
--------
20
28
27
L---:---":
5,5V
........
30
5,5V
24
21
---
60
Capaciiance (pF)
~
22
l>
-II- 4,5V
I
20
100
~
Ll
1
Capacitance (pFj
23
r-
19
~
29
28
-0
----------
----
20
-II- 4,5V
29
9
--' ~
21
r"'
31
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26
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TN-04-24
CAPACITANCE
'AA vs. Capacitance
85°C
28
27
•
VS.
~
5,5V
21
20
20
100
60
60
100
Capacitance (pF)
Capacitance (pF)
0
-I
m
tOE vs. Capacitance
25°C
11
H:
10
9
4,5V
5,5V
I
7
~---
6
5
/
85°C
10
I
., 8
.:.
w
9
tOE vs. Capacitance
11
.-I
.--/
~
9
---/
........ .-----~
~
6
5
toE is less than 5ns with 20Pf load at Vee = 5,5V -
4
/
--- /
..--'~
60
100
20
Capacitance (pF)
TN-Q4-24
DT24.pm5 - Rev. 2195
-------II- 4,5V
4
20
~
60
---
5,5V
100
Capacitance (pF)
7-46
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc.
MICRON
1-·
256K x 16-ACCESS TIME
""'"ococ,,"
VS.
TN-04-26
CAPACITANCE
256K x 16-ACCESS
TIME vs. CAPACITANCE
TECHNICAL
NOTE
INTRODUCTION
worst-case design limits, the system designer should refer
to the individual data sheets.
These curves for the 256K x 16 DRAM show typical access
times at Vcc = 4.5V with different capactive loading. For
tCAC vs. Capacitance
85°C
17
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tRAC vs. Capacitance
85°C
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9
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51
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50
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5
7
7
v/"
25 50 75 100 125 150 175 200
Capacitance (pF)
Capacitance (pF)
/
31
o
/
/
W30
/
29
V
28
/
27
/
26
25
"
/
"
25 50 75 100 125 150 175 200
Capacitance (pF)
TN-04-26
DT26.pm5 - Rev. 2195
»
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tAA vs. Capacitance
85°C
33
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25 50 75 100 125 150 175 200
34
•
7-47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron'Technology, Inc.
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256K x 16-ACCESS TIME
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TN-04-26
DT26.pm5 - Rev. 2/95
7-48
VS.
TN-04-26
CAPACITANCE
MICRON
1-·
TN-04-28
DRAM SOFT ERROR RATE CALCULATIONS
"'""owe"",
TECHNICAL
NOTE
DRAM SOFT ERROR
RATE CALCULATIONS
INTRODUCTION
DRAM SER RATES
Micron technical note TN-04-1S, "DRAM Considerations
for PC Memory Design" , presents a discussion on the use of
parity. This technical note may have led some readers to
conclude that parity is no longer of value. Although this
conclusion is understandable (see Figure 1), the fact is that
the need for parity can be determined only after design
goals have been thoroughly analyzed.
Herein lies the problem: how to get from point A (DRAM
manufacturer's reported soft error rate [SER]) to point B
(system mean time between failures [MTBF]). This article's
purpose is to solve the problem by showing how to take
SER data reported by the manufacturer and determine a
system's memory susceptibility to DRAM soft errors.
The SER data for the Micron 4 Meg DRAM, as reported in
the Micron 4 Meg DRAM Reliability Monitor (dated 2/93),
will be used throughout this article for illustrative
purposes.
DRAM SER is a measurement of a DRAM's susceptibility
to a nonrecurrent, single-bit output error. Although there is
not a defined industry standard for measuring a
component's SER, Micron has adopted a widely accepted
methodology:
•
Accelerated SER testing using an alpha radiation source.
•
Realtime, system-level SER testing. Micron
uses its AMBYX® intelligent burn-in and test
system.
The accelerated test data provides the only practical, real
time means to determine the relative increase or decrease in
the component's SER for various test conditions.
Micron records a DRAM's realtime SER when the device
is operating at a SV Vcc with1S.62S~s cycle rate (refresh
rate). Micron's 4 Meg DRAM Reliability Monitor lists an SER
of 41 FITs at a 90 percent confidence level. A FIT is a failure
in time (1 billion device hours).
Historical Industry SER in DRAMs
10~----------------------------.
SER CALCULATIONS - REFRESH MODE
To begin, let's examine a memory buffer using only one
4MegDRAM(1 Megx4)ata lS~srefreshrate. The system's
MTBF-due-to-soft-error rate is the DRAM's SER rate, 41
FITs. Mean-time-between-failures is calculated by dividing
one billion device hours by 41 FITs, which equals one error
every 24,390,000 system hours or 2,784 years.
Now, let's take the previous example and add three
additional 4 Meg DRAMs for a 16-bit-wide memory array
(2MB). Since there are four components, the SER rate is
increased by the same ratio in order to obtain a system
hourly rating. The system's memory MTBF-due-to-softerror rate is now one billion device hours divided by four
devices (41 FITs per device), equaling one error every
6,098,000 system hours, or 696 years.
Seven, rather than three, additional 4 Meg DRAMs provide a 32-bit wide memory array (4MB). In this case, the
system's MTBF-due-to-soft-error rate is one billion device
hours divided by 8 devices (41 FITs per device), equaling
one error every 3,048,800 system hours or 348 years.
0.1
ffi
0;
"-
~
IL
0.01
0.001 +-------'------'------'--
0.0001 -L-__---'-____-'---__- ' -____-"-__--'-__- - - '
16K
64K
256K
1 Meg
4 Meg
16 Meg
DRAM Density
Figure 1
HISTORICAL DRAM SER
TN-04-28
DT2B.pm5 - Rev. 2195
7-49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
AMBYX is a registered trademark of Micron Systems Integration, Inc.
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TN-04-28
DRAM SOFT ERROR RATE CALCULATIONS
The previous calculations assume a single bank architecture. If any of the above examples had two banks, then SER
would be twice as high and the MTBF would be half of the
single-bank value. For example, a dual bank, 32-bit wide
(8MB) memory system's MTBF-due-to-soft-error rate is one
billion device hours divided by 16 devices (41 FITs per
device), equaling one error every 1,524,400 system hours or
174 years.
as was the case with the refresh SER rate. This is because
only one bank at a time is actively being written or read. The
other bank(s) are in standby (refresh only). For example,
let's determine the operating SER and MTBF for the 32-bit,
dual bank memory array. The operating SER rate is 2,591
FITs (active bank from previous example) plus 328 FITs
(additional bank in standby), which equals 2,919 FITs. The
system's memory MTBF for soft errors is 342,580 system
hours or 39 years.
SER CALCULATION - ACTIVE MODE
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SYSTEM-INDUCED SOFT ERRORS
DRAM memory is not always in refresh mode. Rather, it
is active (accessing data via READs and WRITEs) during a
portion of its ON time. It is necessary to determine the
memory's overall SER, or "operating SER," before determining a system's MTBF-due-to-soft-error rate during
DRAM access.
First, the percentage of time the DRAMs are active and in
refresh must be determined. The next step is to determine
the refresh SER rate. As performed in the previous 32-bit,
single-bank example using eight 4 Meg DRAMs, the refresh
SERrate based on eight devices (41 FITs per device) is 328
FITs.
The active SER rate must now to be determined. This is
where acceleration curves are required. Micron provides
three types in the 4 Meg DRAM Reliability Monitor: checkerboard pattern, solid ones pattern and solid zeros pattern.
The graph that provides the worst-case slope, typically the
checkerboard pattern, is usually selected.
Referring to the 5V checkerboard pattern curve from the
Micron 4 Meg DRAM Reliability Monitor (Figure 2), let's
assume the DRAMs are being cycled at a 200ns (O.2/1s) cycle
rate. The alpha hits at 15/1s is selected from the checkerboard pattern curve-3.4 hits. The alpha hits at 200ns are
then selected from the same curve-160 hits. Taking 160
hits and dividing by 3.4 hits gives a ratio of 47. Thus, the SER
can be expected to increase by a factor of 47 times when
operating at 200ns as compared to refreshing at 15/1s. By
taking the real-time SER at 15/1s and using the ratio from the
acceleration curves just acquired, the SER at 200ns can be
determined at 328 FITs times 47, which equals 15,416 FITs.
SO far, this discussion has focused on DRAM-related soft
errors (i.e., alpha particle induced). System-induced softerror calculations are beyond the scope of this article but
warrant some discussion.
System-induced soft errors are those not generated by the
DRAM memory itself. They are most commonly due to
noise sources such as undershoot/overshoot, as well as
timing issues due to hardware and/ or software problems.
System-induced soft.errors are usually overlooked because
they have been negligible contributors on a well-designed,
clean system. Improvements made in DRAM SER by quality DRAM manufacturers, as well as faster operating speeds
and board design requirements, have shifted the primary
cause of soft errors to the system design itself.
5V Checkerboard Pattern
100
2l
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c.
«
10
MTBF DUE TO SOFT ERRORS
Now, let's assume the 32-bit, single-bank DRAM memory
array is active 15 percent of the time and is in refresh the
remaining 85 percent of the time. The operating SER rate is
nowobtainable-15 percent of 15,416 FITs plus 85 percent
of 328 FITs yields a FIT rate of 2,591 FITs. The system's
memory MTBF for soft errors is obtained by dividing one
billion device hours by 2,591 FITs for an MTBF of 385,950
system hours or 44 years.
For a dual-bank memory non-interleaved array, the operating SER rate would not be twice the single bank amount,
TN·04-28
DT28.pm5 - Rev. 2195
1
lOt
100
Cycle Time (liS)
Figure 2
CHECKERBOARD PATIERN
7-50
Micron Technology, Inc., reserves the right to change products or specifications wrthout notice.
©1995,MlcronTechnology,lnc.
MIC:RON
1-·
"'~"w'"''
TN-04-28
DRAM SOFT ERROR RATE CALCULATIONS
Conventional parity-based systems check for soft errors
stemming from the data, both alpha particles (DRAM) and
data I/O bus noise (system). However, there are other
sources of system-induced soft errors that are overlooked
because they cannot be detected with conventional parity.
For example, noise on the address bus can result in the
wrong data being written to, or read from, the DRAM. The
data itself will be unaffected by the address bus noise, but
the wrong location is accessed. Even though these types of
system soft errors are not checked for, they are just as
harmful as data-I/O induced soft errors.
Parity checking can be useful in the prototype stage by
helping to identify initial design problems. Such parity
checking can include DRAM, address bus and data bus
parity checking. There are strong arguments for eliminating DRAM parity memory and providing parity checking
on the address and data bus only. In either case, the DRAM
parity memory and bus parity checking circuits could be
eliminated once the system's design has been qualified to
meet overall system soft-error requirements.
Even if a DRAM memory's alpha-particle-induced softerror rate is at an acceptable level, some sort of parity
checking may be desired. Bus-parity checking circuits could
remain in the system at a lower cost and provide a greater
safeguard against soft errors than that obtainable with
DRAM parity memory.
Many of today's systems are designed to offer
upgradability from the low-end to high-end of the performance spectrum. For these systems, where the low-end
version does not require DRAM parity memory but the
high-end upgrade does; designing-in flexibility to allow
either choice is advantageous.
SUMMARY
In determining the parity requirements for a given
memory system, the memory designer cannot assume parity is or is not required. Rather, the memory designer must
analyze the system's reliability requirements and determine what soft error rate is expected and what MTBF for
soft errors the system can tolerate.
The memory designer must "engineer" the SERnumbers
to his specific conditions to obtain numbers relevant to the
design itself. Following the procedures outlined in this
technical note will allow any memory system designer to
determine expected memory MTBF-due-to-soft-error rates.
It should be noted that measured and accelerated SER
data provides a "ball-park" number for general expectations. In the last example--a 32-bit, dual-bank memory
array using 4Meg DRAMs-the memory system was shown
to experience one soft error every 39 years.
If a system required an MTBF of at least 38 years per soft
error, the system using 4 Meg DRAMs would suffice technically. But since the expected MTBF is a typical expecta tion
and not an absolute minimum, th(' number should be
guard-banded. There is no industry rule for what go,ml
band to use, but a memory designer~h()uld fed safl'in using
a 25 percent guard band. For the foregoing example, any
system specifying an MTBF of 30 years or less should not
jeopardize its reliability to DRAM-related soft errors by
eliminating parity memory.
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TN-04-28
DT28.pm5 - Rev. 2/95
7-51
Micron TeChnology, Inc., reserves the right
to change products or specifications without notice
©1995, Micron Technology, Inc.
1'111t:I=IgN
TN-04-28
DRAM SOFT ERROR RATE CALCULATIONS
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TN-04-28
DT28.pm5 - Rev. 2f95
7-52
MICRON
1-·
TN-04-29
MAXIMIZING EDO ADVANTAGES
'""ow,n,
MAXIMIZING EDO
ADVANTAGES AT THE
SYSTEM LEVEL
TECHNICAL
NOTE
INTRODUCTION
Extended data-out (EDO) DRAMs, while representing
only a slight modification to conventional FAST PAGE
MODE (FPM) components, can provide substantial advantages at the system level. The primary benefit is that EDO
allows for a shorter PAGE MODE cycle time (or faster data
rate) while accessing data within a single page in memory.
Other advantages include relaxed system timing constraints
and in some cases, less total overhead during page accesses.
In general, the design complexity for an EDO-based system
will be less than that for a system based on FPM components, and much less than that for systems based on any of
the other alternative DRAM technologies now being introduced.
This article reviews the physical differences between
EDO and FPM components and then describes the timing
implications of those differences. This discussion is then
extended to cover the increase in performance and other
advantages at the system level; examples using typical
RAs
system timing are shown. Finally, additional system design
implications are discussed.
EDO vs. FPM-COMPONENT LEVEL
DIFFERENCES
Simply stated, EDO means that data is not disabled when
CAS goes HIGH during a PAGE-MODE READ access.
Instead, data remains available until such time that data
from the subsequent access begins to appear. This is indicated by the presence of a ICOH specification and the lack of
a IOFF specification when compared to conventional FPM
(as shown in Figure 1). Other changes include related
modifications to RAS, OE and WE functionality, to provide
for the disabling of data when necessary and when no
longer accomplished by CAS alone. This related operation
is further detailed in subsequent sections of this article.
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PHYSICAL DIFFERENCE BETWEEN FPM AND EDO
TN-04-29
DT29.pmS - Rev. 2/95
7-53
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'--------------1
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Micron Technology, Inc., reserves the right 10 change products or specifications without notice.
©1995, Micron Technology, Inc.
-
1UIIIl::::I=ICN
1-·
TN-04-29
MAXIMIZING EDO ADVANTAGES
'''"''''''''''
TIMING IMPLICATIONS
The real advantage ofEDO is not necessarily that data can
remain valid once CAS goes HIGH, as shown in Figure 1,
but that CAS is allowed to go HIGH prior to valid data
appearing on the outputs (this is shown, again compared to
conventional FPM, in Figure 2). For FPM devices, the CAS
pulse width (tCAS) is specified to be equal to tCAC since
anything shorter would disable data before it became valid.
In fact, tCAS typically must be longer than tCAC in the
system because many DRAM vendors specify a minimum
tOFF of Ons. With EDO devices, tCAS is no longer limited by
tCAe or the data valid time required by the system and is
therefore typically specified at 10ns for the -6 speed grade.
The shorter tCAS specification associated with EDO allows the CAS or PAGE MODE cycle time to be tightened. As
shown in Figure 2, EDO allows for a portion.of the access
time in one cycle to overlap a part of the access time, as well
as all of the data valid time, for the previous cycle. In
contrast, the only such overlap in a FPM access is the
portion, if any, of the data valid time which is provided by
a nonzero tOFF MIN specification. Specific system timing
will determine the extent of the overlap that can be achieved,
but the following theoretical example will illustrate the
point.
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TIMING IMPLICATIONS OF EDO
TN-Q4..29
DT29.pm5 -Rev. 2195
7-54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC:RON
I~·
.
TN-04-29
MAXIMIZING EDO ADVANTAGES
,"~"co,,'"
time (35ns) and the EDO cycle time (25ns) can be accounted
for by noting that the FPM cycle can be computed as 35ns of
access time (tcpA) plus3ns of data valid time, minus the 3ns
of data valid time that overlaps the next access. The EDO
cycle can be computed as 35ns of access time plus IOns of
data valid time, minus 20ns of overlap with the next access.
Note in this case that in addition to a shorter cycle, the EDO
device also provides a longer data valid window, thereby
simplifying system design.
For now, let's ignore propagation delays from the system clock, system clock resolution, address timing and
signal transition times. Let's assume that we have a -6 FPM
version and a -6 EDO version of an otherwise identical
device. For illustration, the timing for Micron's 256K x 16
DRAMs will be used (see Table 1.) This timing will be used
in all of the examples that follow.
The PAGE MODE cycle timing for the two devices is
shown in Figure 3. The difference between the FPM cycle
'"
Table 1
RELEVANT SPECIFICATIONS FOR
THE MICRON 256K x 16 DRAMS
Parameter
MT4C16257 (FPM)
(ns)
MT4C16270 (EDO)
(ns)
'CAC
MAX
15
15
'CPA
MAX
35
35
30
10
30
10
3
10
3
5
25
'AA
MAX
'CP
MIN
'OFF
MIN
'CAS
MIN
3
15
'ClZ
MIN
3
'COH
MIN
-
'PC
MIN
35
'CSH
MIN
40
'RSH
MIN
'RAl
MIN
60
15
30
'ASC
MIN
0
'CAH
MIN
'RP
MIN
10
40
0
10
'OS
MIN
'DH
MIN
TN-04-29
DT29.pm5 - Rev. 2f95
0
10
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FPM MINIMUM CYCLE TIMES
35
0
10
7-55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
»
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TN-04-29
MAXIMIZING EDO ADVANTAGES
"'""'COO,,"
next access. A PAGE-MODE WRITE access does not benefit
from EDO, but can be executed with the same minimum
cycle times as shown in Figure 5.
The overlapping of accesses described above leads to a
pipelined effect in page mode read accesses, as shown in
Figure 4. Ideally, data from one access is latched by the
controller at the same time the controller fires CAS for the
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TN-04-29
DT29.pm5 - Rev. 2/95
7-56
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MU:::I=ICN
1-·
TN-04-29
MAXIMIZING EDO ADVANTAGES
"'~""oo, '"
SYSTEM PERFORMANCE INCREASE
FROMEDO
the 15ns clock resolution (bursts of three locations were
used strictly for the convenience of graphic illustration).
Note that while a 30ns cycle time can be achieved with EDO,
only a 45ns cycle can be achieved with FPM. Converting the
cycle times to peak burst rates results in 33 MHz for EDO
and 22 MHz for FPM. In this case, EDO provides a 50
To examine the system performance advantage provided
by EDO and factor system clock resolution into the discussion, a noninterleaved design based on a 66 MHz system
clock driven by the positive clock edges only, will be
considered. Figures 6 and 7 show, respectively, the FPM
and EDO PAGE-MODE READ cycle timing resulting from
RAs
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EDO READ CYCLE -66 MHz SYSTEM CLOCK
TN-04-29
DT29.pm5 - Rev. 2195
7-57
Micron Technology, Inc., reserves the right
to change products or specifications without notice
©1995, Micron Technology, Inc.
AIIIIC::I=ICN
1-·
TN-04-29
MAXIMIZING EDO ADVANTAGES
"'""'CO"""
Also shown in Figure 7 is the fact that unlike operation
within a page access, once the page access is terminated by
RAS going HIGH, CAS going HIGH will disable data. This
results in the ability to hide some row precharge time, as
discussed below.
percent improvement in peak burst rate in the system. For
reference, Figures 8 and 9 show the corresponding PAGEMODE WRITE cycle timing. Figure 9 shows that although
the write cycles do not benefit from the EDO behavior itself,
they can still match the cycle times for the EDO READs.
SYSCLK
(66MHz)
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FPM WRITE CYCLE - 66 MHz SYSTEM CLOCK
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Figure 9
EDO WRITE CYCLE - 66 MHz SYSTEM CLOCK
TN-04-29
DT29.pm5- Rev. 2195
7-58
Micron Technology, Inc., reserves the right to change products or _specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-04-29
MAXIMIZING EDO ADVANTAGES
","",CO",,,
Table 2
POPULAR SYSTEM CLOCK RATES AND
RESULTING PAGE MODE CYCLE TIMES
SYSTEM CLOCK
as welL This specification will typically be 40ns for -6 and
-7 speed grades, Another parameter which would be a
limiter if carried over is tRSH, This parameter will also be
respecified for EDO; ideally it would be set equal to the
EDO tCAS specification, There are also several other parameters, many device or vendor specific, that will be
adjusted to accommodate EDO designs,
Figures 7 and 9 reflect the adjusted tCSH and lRSH
specifications and the result is that the page mode overhead
for the EDO devices is equal to that for the FPM devices,
This is seen by noting that the total number of clock cycles
for the page access for the FPM devices is 13, Three locations
of data require three clocks each, for a total of nine, leaving
four as overhead, For the EDO, ten total cycles are needed,
six of which are required for data, again leaving four as
overhead,
PAGE MODE
CYCLE TIME
Frequency
(MHz)
Period
(ns)
FPM
(ns)
EDO
(ns)
50
60
66
80
20,0
16,7
15,0
12,5
40
50
45
50
40
33
30
25
Table 2 lists popular system clock rates along with the
corresponding FPM and EDO PAGE MODE cycle times
that would result from system clock resolution alone, Not
only does EDO provide a faster peak data rate in almost
every case, but an increase in system clock rate is much
more likely to result in a corresponding faster peak burst
rate (shorter PAGE MODE cycle time) when EDO devices
are used, This continuous increase will extend to 90 and 100
MHz systems with the introduction in the near future of
EDO parts, which provide PAGE MODE cycle times down
to 20ns,
Also related to system performance is the fact thatthe use
of EDO typically results in the same total page mode
overhead (row access time plus row precharge time) as with
FPM, This is possible because tCSH, like tCAS, is not physically limiting on the devices as specified for FPM and would
therefore be an artificial limiter if carried over directly from
FPM and applied to EDO devices, Instead, Micron is adjusting the tCSH specification on EDO devices to allow for the
first CAS pulse to go HIGH earlier in the page access, and
it is expected that other vendors will make this adjustment
TN-04-29
DT29.pm5 - Rev. 2195
SYSTEM AOV ANTAGES OF EOO
After reviewing the theoretical FPM and EDO PACE
MODE cycle times listed in Table 2, the twxt logica 1qt!('stion
is, can those cycle times actually lO(' ilchil'vt'd in il I'm I
system, and with how much effort? Thl' anSWl'r is that
achieving these cycle times with EDO devices will require
equal or less design complexity than that required with
FPM devices, The biggest problem in designing with FPM
devices, once the propagation delays from the system clock
are taken into consideration, has been trying to align the
read data valid window around a system clock edge that
can be used to latch that data into the memory controller.
A 50 MHz system clock and the device timing mentioned
earlier will be used to illustrate this point, Typical propagation delays that might be found in a graphics subsystem
with a controller implemented in an ASIC will also be used,
These include a clock-to-Q delay for the controller plus
routing delays, together totaling 12ns, and routing delays
plus setup time back to the controller, together equaling
7ns,
7-59
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc
z
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MICRON
1-·
TN-04-29
MAXIMIZING EDO ADVANTAGES
",",cw"",,,
In Figure 10, the FPM case, the data valid window for the
controller starts 3ns before, and ends 5ns after, a negative
system clock edge, which also means that the window ends
5ns prior to the next positive system clock edge. The choices
here are to work with a skewed and! or inverted internal
SYSCLK
(50MHz)
clock or with internal data delays to extend hold time to
beyond the positive edge, or use an alternate external signal
as a clock to the. data input latch on the controller. Either
way, these multiple! skewed clocks add design complexity.
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Figure 10
FPM READ CYCLE WITH PROPAGATION DELAYS - 50 MHz SYSTEM CLOCK
TN-04-29
DT29.pm5- Rev. 2195
7-60
Micron Technology, Inc., reserves the righllo change products or specifications without notice
©1995, Micron Technology, Inc
MICRON
1-·
TN-04-29
MAXIMIZING EDO ADVANTAGES
"'"",CO"""
Note that the page mode overhead for this example also
happens to be less for EDO than for FPM. Since both
methods use the same number of system clock cycles for
each column (data) access, this overhead savings is seen by
noting that the total number of clocks required for the page
access is ten in the FPM case and nine in the EDO case.
In contrast, when EDO devices are used with the same
system timing, the data valid window begins at the same
point but extends until ICOH (5ns) after the next CAS
falling edge, shown in Figure 11. This total window is equal
to 30ns or 1.5 system clock cycles; therefore, data can easily
be latched in by an existing positive edge of the system
clock with no additional design complexity.
SYSCLK
(50MHz)
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VIHVIL-
\~~--~------~--------~/.
:
tCSH
:
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tRSH
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tpc
~: _t_c_p_: _t_CA_S~ : _ _
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COLUMN B
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,
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,
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Figure 11
EDO READ CYCLE WITH PROPAGATION DELAYS - 50 MHz SYSTEM CLOCK
TN-04-29
DT29.pm5 - Rev. 2195
o
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tCPA
I~
tCAC
:-DQ VIOHVIOL
,
7-61
Micron Technology, Inc., reserves the righllo change products or specificatIOns without notice
©1995, Micron Technology, Inc.
MICRON
TN-04-29
MAXIMIZING EDO ADVANTAGES
,ec~,o,cc'"
1-·
Now that we've shown that EDO can be substantially
faster than FPM, and that at a given speed, an Eoo-based
system can be implemented with equal or less design
complexity, the next question is, can an EDO-based system
be designed to be faster with equal or less design complexity? The answer, again, is "yes." To see this, let's revisit the
66 MHz example (where EDO was previously shown to
provide a 50 percent improvement in peak memory bandwidth), but now typical system propagation delays will be
included. A system clock-to-Q plus trace delay of 9ns and a
delay and setup time back to the controller of 5ns will be
used. The resulting timing is shown in Figures 12 and 13.
SYSCLK
(66MHz)
•
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IRSH
tCSH
tpe
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V'H
CAS
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X
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DATA C
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Figure 12
FPM READ CYCLE WITH PROPAGATION DELAYS - 66 MHz SYSTEM CLOCK
TN-04-29
DT29.pm5 - Rev. 2195
7-62
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
MICRON
1-·
TN-04-29
MAXIMIZING EDO ADVANTAGES
",""ow","
Once again for the FPM case, the data valid window
(13ns) does not line up with an existing positive edge of the
system clock (while meeting the required set-up time) so
one of the design techniques mentioned above will need to
be employed. The data valid window for the EDO case also
does not align with an existing positive clock edge, and will
also require one of the above design techniques. However,
in the EDO case, the data valid window is longer than for
the FPM case (15ns vs 13ns) and is therefore simpler to
design for. Here we have a case where EDO provides a 50
percent improvement in peak memory bandwidth, but
with reduced design complexity.
.~
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:
IASC
•
ICAH:
.:~:.
IpC
IpC
IASC
'
ICAH
:
~:~=~~--RO-'--W----'-,X
COL~MN A
X
COL~MN B
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•
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IASC.
:-----:-----:-----:-----:-----:'
ADDR
ICAH
R~O-W----
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.:
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(66MHz)
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Figure 13
EDO READ CYCLE WITH PROPAGATION DELAYS - 66 MHz SYSTEM CLOCK
TN-04-29
OT29.pm5 --'·Rev. 2195
7-63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-04-29
MAXIMIZING EDO ADVANTAGES
","",00'",
DESIGN IMPLICA nONS
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Address Setup Time: In order to achieve maximum performance with EDO, it is necessary to provide valid column-addresses with sufficient setup time to the falling
edge of CAS so that tAA is not a limiting parameter. This
leaves tcpA as the limiting parameter for PAGE-MODE
READ cycle times. ;:'his is true for FPM as well, but there,
either tCAC or tcpA may be limiting.
With the device timing shown, the column-addresses
should transition after meeting the hold time (tCAH) from
the previous access. This means that the same system clock
edge that drives CAS HIGH will drive the new address.
Since tcpA is typically specified to be Sns longer than tAA,
if the CAS and column address lines transition at the same
time, tCPA will always be limiting. However, the address
lines may be more heavily loaded and may transition later.
This is not an issue unless the address signals take over Sns
longer than the CAS signal to become valid, and will
actually provide additional guardband in meeting tCAH.
OE and WE Operation: In certain situations it is necessary
to disable the data outputs while within a page mode access
(for example, when switching from a READ cycle to a
WRITE cycle or when interleaving banks of memory). For
EDO, since CAS alone will not disable the outputs, either
OE or WE must be used.
As with FPM devices, the data outputs will be disabled
whenever OE goes HIGH. However, if this occurs (for a
specified duration) while CAS is HIGH, the EDO operation
will be suspended. Specifically, the data outputs will be
disabled and will remain that way, regardless of subsequent transitions on OE, until CAS goes LOW again for a
READ cycle. This pulsed operation is beneficial in system
implementations which include multiple banks of memory,
and which may have rows activated in more than one bank
simultaneously. Instead of supplying a separate OE Signal
for each bank, bank-specific CAS signals can be used in
conjunction with a common OE signal to disable the data
TN-04-29
DT29.pm5- Rev. 2195
outputs for a given bank. Alternitively, WE going LOW at
any time will suspend EDO operation; the outputs will be
disabled and will remain disabled until CAS goes LOW for
a READ cycle
Maximum page mode performance is achieved when
executing strictly READ cycles (WE remains HIGH) or
strictly WRITE cycles (WE remains LOW), as shown in the
previous examples. Mixing READ and WRITE within a
page is supported, but this usually requires additional
clock cycles. For switching from a READ to a WRITE cycle,
either OE or WE may be used to disable output data;
depending on the individual device specification, one
method mav be faster than the other. In either case, WE
must go LOW to execute the WRITE. More detailed information on OE and WE operation can be found in the
individual device data sheets.
SUMMARY
EDO is a minor modification over conventional FPM
memory components, with major implications in terms of
system performance and/or simplifying system design
complexity. A very simple physical change at the component level (data not being disabled by CAS going HIGH
within a PAGE-MODE READ access) results in either a
longer data valid window or a shorter PAGE MODE cycle
time and often results in both. As with any componenttype,
there are specific design factors to be considered but in
general, the design complexity of an EDO-based system is
equal to or less than that of an FPM -based system, resulting
in a substantial performance increase with no added design
cost. The performance increase is measured as an increase
in peak memory bandwidth and on components which are
widely available today, this increase can be up to 60 percent
based on device specifications, and up to 100 percent once
actual system clock timing is considered.
7-64
Micron Technology, Inc, reserves the right to change products or speCifications without notice.
©1995, Micron Technology, Inc
UU:::RCN
1-·
TN-04-30
VARIOUS METHODS OF DRAM REFRESH
,eo"""OC""
TECHNICAL
NOTE
VARIOUS METHODS
OF DRAM REFRESH
INTRODUCTION
BURST REFRESH
DRAM refresh is the topic most misunderstood by
designers due to the many ways refresh can be accomplished. This article addresses the most often asked questions about refresh. The two basic means of performing
refresh, distributed and burst, are explained first followed
by the various ways to accomplish refresh: RAS-ONLY
REFRESH, CAS-BEFORE-RAS REFRESH and HIDDEN
REFRESH.
Refresh may be achieved in a burst method by performing a series of refresh cycles, one right after the other until
all rows have been accessed. During refresh other commands are not allowed. Below is a drawing representing
burst and distributed refresh.
For example: a 4 Meg x 1 requires 1,024 consecutive
refresh cycles, each of which will use 130ns (IRC) for a 70ns
device.
1,024 cycles x 130ns = 133,120ns = 0.133ms
16ms - 0.133ms = 15.867ms
Approximately O.13ms would be spent performing refresh,
and the remaining 15.87ms could be spent reading and
writing; then burst refresh would occur again, and so on.
Distributed refresh is the more common of till' I wo rl'fresh categories. The DRAM controller is sl't up to perform
a refresh cycle every 15.6I1s. Usually, this means the controller allows the current cycle to be completed, and then holds
off all instructions while a refresh is performed on the
DRAM. The requested cycle is the.n allowed to resume.
STANDARD AND EXTENDED REFRESH
DRAMs are often referred to as either "standard refresh"
or "extended refresh." Dividing the specified refresh time
by the number of cycles required will determine if the
DRAM is a standard refresh or an extended refresh device.
If the result is 15.611s it is a standard refresh device, while a
result of 12511s indicates an extended refresh device.
Table 1 lists some of the standard DRAMs and their
refresh specifications.
REFRESH CYCLES
Table 1
STANDARD DRAMS AND REFRESH
SPECIFICATIONS
DRAM
REFRESH
TIME
NUMBER OF
CYCLES
REFRESH
RATE
4 Meg x 1
16 ms
1,024
15.6115
256K x 16
Bms
512
15.6115
256Kx 16
(L version)
64 ms
512
125115
4 Meg x4
(2K)
32ms
2,046
15.6115
4 Meg x4
(4K)
64ms
4,096
There are different cycles you can use to refresh DRAMs,
all of which can be used in a distributed or burst method.
There are three types listed in a standard data sheet:
• RAS-ONLY REFRESH
• CAS-BEFORE-RAS REFRESH
• HIDDEN REFRESH
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Distributed
Refresh
Burst
Refresh
n n n n n n n n n n
nnnnnnnnnnn
15.6115
Each pulse represents
a refresh cycle
!nnnnnnn"nn"
Required time to
complete refresh of all rows
Figure 1
BURST AND DISTRIBUTED REFRESH
Distributing the refresh cycles so that they are evenly
spaced is known as distributed refresh. To perform distributed refresh on a standard DRAM, execute a refresh cycle
every 15.611s such that all rows are turned on before repeating the task. When not being refreshed, the DRAM can be
read from or written to.
DT30.pm5 - Rev. 2/95
•
m
DISTRIBUTED REFRESH
TN-04-30
z
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7-65
Micron Technology, Inc., reserv&slhe right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC:RON
1-·
TN-04-30
VARIOUS METHODS OF DRAM REFRESH
",e",,,",,,,
RAS-ONLY REFRESH
To perform a RAS-ONLY REFRESH, a row address is put
on the address lines and then RAS is dropped. When RAS
falls, that row will be refreshed and, as long as CAS is held
high, the DQs will remain open. (See Figure 2.)
It is the DRAM controller's function to provide the addresses to be refreshed and make sure that all rows are
being refreshed in the appropriate amount oftime. The row
order of refreshing does not matter; what is important is
that each row be refreshed in the specified amount of time.
to supply or keep track of row addresses. A drawing of one
CBR REFRESH cycle is shown in Figure 3. CAS must be held
low before and after RAS falls to meet tCSR and tCHR.
Figure 4 shows three CBRREFRESH cycles. In this drawing,
CAS stays low and only RAS toggles. Every time RAS falls
a refresh cycle is performed. CAS may be toggled each time,
but it's not necessary.
CBR POWER SAVINGS
Since CBR REFRESH uses the internal counter and not an
external address, the address buffers arc powered-down.
For power sensitive applications, this can be a benefit,
because there is no additional current used in switching
address lines on a bus, nor will the DRAMs pull extra power
if the address voltage is at an intermediate state.
CAS-BEFORE-RAS REFRESH
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CAS-BEFORE-RAS REFRESH, also known as CBR REFRESH, is a frequently used method of refresh because it is
easy to use and offers the advantage of a power savings. A
CBR REFRESH cycle is performed by dropping CAS and
then dropping RAS. One refresh cycle will be performed
each time RAS falls. WE must be held high while RAS falls.
The DQs will remain open during the cycle .
Here's how CBR REFRESH works. The die contains an
internal counter which is initialized to a random count
when the device is powered up. Each time a CBR REFRESH
is performed, the device refreshes a row based on the
counter, and then the counter is incremented. When CBR
REFRESH is performed again, the next row is refreshed and
the counter is incremented. The counter will automatically
wrap and continue when it reaches the end of its count.
There is no way to reset the counter. The user does not have
l>
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CBR REFRESH IS EASY TO USE
Since CBR REFRESH uses its own internal counter, there
is not a concern about the controller having to supply the
refresh addresses. Virtually all DRAMs support CBR REFRESH and the 15.611s refresh rate, so you can design for
CBR REFRESH at the distributed rate of 15.611s and plug in
many different DRAMs without having to worry about
refresh. For example, the 4 Meg x 4 comes in two versions:
• 2,048 cycles in 32ms
• 4,096 cycles in 64ms
One refresh cycle when RAS falls
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Figure 2
RAS-ONL Y REFRESH
TN-04-30
DT30.pm5 - Rev, 2/95
7-66
Micron Technology, Inc., reserves the right to mange products or specifications without notice.
©1995, Micron Technology. Inc.
MICRON
1-·
TN-04-30
VARIOUS METHODS OF DRAM REFRESH
"'"",co",'"'
minimum of tRP) and then low. Since CAS was low before
RAS went low, the part will execute a CBR REFRESH. In a
READ cycle the output data will remain valid during the
CBR REFRESH. The refresh is not "hidden" in the sense that
you can hide the time it takes to refresh, instead it is hidden
in the sense that data-out will stay on the lines while
performing the function. READ and HIDDEN REFRESH
cycles will take the same amount of time: tRe. The two
cycles together take 2 x tRe. If we were to do a READ and
If CBR REFRESH is used, simply maintain the standard
lS.6lls refresh rate. If RAS-ONLY REFRESH is used, addresses must be supplied as follows:
• AO-AI0 for the 2,048 cycle refresh
• AD-All for the 4,096 cycle refresh.
HIDDEN REFRESH
In HIDDEN REFRESH, the user does a READ or WRITE
cycle and then, leaving CAS low, brings RAS high (for
One refresh cycle
RAS
:---1
~:r-
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'RP
I,
tRAS
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'CSR
CAS
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ONE CAS-BEFORE-RAS REFRESH CYCLE
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One refresh cycle
One refresh cycle
\
\
\
'RP
tRAS
II,
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tRAS
'RP
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Figure 4
THREE CAS-BEFORE-RAS REFRESH CYCLES
TN-04-30
OT30.pm5 - Rev. 2195
7-67
o-I
Micron Technology, Inc., reserves the rJghllo change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-04-30
VARIOUS METHODS OF DRAM REFRESH
",""oc%n,
then follow it with a standard CBR REFRESH (instead of a
HIDDEN REFRESH), this would take the same amount of
time: 2 x IRe.
Figure 5 shows a READ followed by a HIDDEN REFRESH. Figure 6 shows a READ followed by a standard
CBR REFRESH. The only difference between the two is that
data-out is valid during the HIDDEN REFRESH.
SUMMARY
Three different cycles exist to perform refresh on a standard DRAM: RAS-ONLY REFRESH, CAS-BEFORE-RAS
REFRESH, and HIDDEN REFRESH. Each cycle can be used
in a burst or distributed method, whichever best fits the
designer's needs. However, CBR REFRESH is the preferred
choice because of its ease of use and power savings.
(REFRESH)
(READ)
'RAS
'RP
~~'RP
'RAS
1'l
-J~II--
tRCO
,_'R_S"_
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FIGURE 5
READ CYCLE FOLLOWED BY HIDDEN REFRESH
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FIGURE 6
READ CYCLE FOLLOWED. BY CBR REFRESH
TN-04-30
DT30.pmS - Rev. 2/95
7-68
Micron Technology, Inc., reserves the right to change products orspecilicalions wilhoul notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-04-31
4 MEG x 4 PCB LAYOUT
"'"~OCO,,'"'
PCB LAYOUT FOR 4 MEG x4
300 MIL OR 400 MIL SOJ
TECHNICAL
NOTE
INTRODUCTION
The 4 Meg, the 16 Meg and the 64 Meg DRAMs are
experiencing similar packaging trends, in which the first
generation is produced in a larger package than later generations for a given density. A list of DRAM configurations
for the various 4, 16 and 64 Meg DRAMs is provided in
Table 1. For each device type, the initial offering (first
generation) is listed along with the size reduction on later
generations.
Although migrating from a larger to a smaller package
has obvious long term benefits, it can make the memory
designer's job more difficult when designing a printed
circuit board (PCB) layout that can accommodate both
sizes. This technical note demonstrates a PCB layout that
can accommodate 300 mil or 400 mil 4 Meg x 4 SOJ DRAMs
in a 2K refresh version, as well as help point out the need to
layout for future trends. This note applies only to the 2K
refresh version because it has symmetric addressing, so
Ala and A3 can be used interchangeably. Because the 4K
refresh has 2 address bits dedicated as row-only addresses,
additional jumpers would be required .
Figure 1 shows the basic pad layout for l'ilJll'r 4 Meg x 4
DRAM.
Table 1
PACKAGE TRENDS BY CONFIGURATION
Initial Package
Device
Size
Pins
4 Meg x 1
1 Meg x4
350 mil
20/26
20/26
24/28
4 Meg x4
350 mil
400 mil
As Product Matures
Pins
Package
Size
300 mil
300 mil
300 mil
20/26
20/26
24/26
2 Meg x 8
400 mil
28
300 mil
28
16 Meg x 4
500 mil
34
400 mil
32
8 Meg x 8
500 mil
34
400 mil
32
SOJ
SOJ
PCB trlleo
and IlunAI
~.370"
SOJI
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TSOP
SOJ
SOJ
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Figure 1
PCB LAYOUT FOR A 4 MEG
7-69
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TN-04-31
DT31.pm5 - Rev. 2195
z
x 4 SOJ
Micron Technology, Inc., reserves the tight to change products or specifications without notice
©1995,MicronTechnology, Inc
MIC:RON
1-·
TN-04-31
4 MEG x 4 PCB LAYOUT
,''"'0"",'"
In Figure 2, the shaded pads show the 24/28 pin 400 mil
package in the layout. The shading represents a solder
connection from the PCB pad to the package lead. The text
within the shaded pad is the DRAM pin assignment, and
the text outside the pads is the signal coming from the PCB.
The small numbers reflect the DRAM pin numbers. The
three small boxes provide the jumper connection to enable
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Pads are .080" x .025"
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Figure 3
4 MEG x 4, 2K REFRESH
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300 MIL SOJ LAYOUT
Figure 2
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--Add
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pinout
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____ 5
Add
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Add
Add
DRAM
pinout
the 300 mil or 400 mil layout. A dotted line indicates where
the jumper is used to make the correct electrical connection
for the 400 mil package.
In Figure 3, the 24/26 300 mil package fit is shown. Notice
that the inside pads are now shaded instead of the outside
pads. The jumper has been placed in the alternate position
to make the proper connection for the 300 mil package.
-I
m
TN-04-31
DT31.pm5 - Rev. 2/95
7-70
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
,,,"",co",,,,
TN-04-32
REDUCE DRAM MEMORY COSTS WITH CACHE
REDUCE DRAM MEMORY
TECHNICAL
NOTE
COSTS WITH CACHE
[NTRODUCTION
DRAM SPEED
All PCs sold today (x486 and above) have cache memory,
llsually both internal to the processor (11) and external to
the processor (L2). The intended purpose of the cache
memory is to minimize the number of wait-states the DRAMbased main memory imposes on the microprocessor. In
other words, cache memory improves the speed of microprocessor accesses because it is Significantly faster than
DRAM-based main memory.
Today, the performance of the DRAM-based main
memory is not nearly as important to the microprocessor
accesses as it was before the use of cache memories; a side
benefit of incorporating cache that is generally overlooked.
Cache is used during most of the microprocessor accesses
(80 to 96+ percent of the accesses). When cache memory is
accessed, DRAM-based main memory is not accessed. This
means DRAM-based main memory is accessed by the microprocessor a small percentage of the time. This is a dramatic shift from the previous generations of systems that
did not incorporate cache memory.
Two performance factors of the DRAM which dramatically improve when the usage rate of the DRAM is reduced
are speed and soft error rates (SER).
Prior to the employment of cache memory, the DRAM
speed had a Significant effect on the microprocessor's performance and was generally considered to be the bottleneck
in system performance. Figure 1 depicts the historical performance increases obtained as the DRAM speed has improved from 120ns to 80ns. The analysis assumes a 386
microprocessor (no 11 cache), no external cache and 10ns
buffer I trace delay.
DRAM speed grade improvements generally provided
significant microprocessor performance enhancements. This
generated the demand for faster DRAMs and warranted the
extra premium being charged for them.
With the introduction of primary (11) and secondary (L2)
cache memory, the number of microprocessor accesses to
the DRAM main memory have been significantly reduced,
as seen in Figure 2. A microprocessor with internal (11)
cache will generally require 15 to 20 percent of the memory
accesses to go out of the microprocessor and access either an
L2 cache memory or the DRAM main memory. With the
addition of an L2 cache memory, just one to four percent of
the memory accesses are required ·to go to the slower
DRAM main memory.
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70%
60,%
50,%
40,%
30%
20%
10%
0%
20 MHZ
Figure 1
HISTORICAL DRAM MEMORY
PERFORMANCE IN PCS
TN-04-32
DT32.pm5 - Rev. 2/95
Figure 2
MICROPROCESSOR ACCESS
ALLOCATION
7-71
Micron Technology, Inc., rese!V9s\he right to change products or specifications without notice.
©1995, Micron Technology, Inc.
I"IIC:I::II;;~,~
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TN-04-32
REDUCE DRAM MEMORY COSTS WITH CACHE
With only one to four percent of the, memory accesses
now going to DRAM main memory, microprocessor performance improvements obtained by using today's faster
DRAMs are greatly minimized, as is seen in Figure 3. For
example, utilizing SOns DRAMs in a 486-based PC with an
LZ cache and both L1 and LZ caches obtaining an 80 percent
hit rate, the microprocessor's performance would be improved by less than one percent over the employment of
70ns DRAMs.
Excluding cache memory effects, a more in-depth look
into the DRAM's speed performance reveals that the perceived advantages of faster DRAMs in PCs are, in part,
diminished due to the nature of data being clocked. So, the
faster DRAM speed does not affect the microprocessor's
perfOHTtanCe unless it can eliminate a wait-state, as demonstrated in Figure 4.
It should be noted that a faster tRAC (sufficiently fast
enough to eliminate a wait state) only improves the
microprocessor's burst performance by one clock at best.
Whereas, a sufficiently faster tCAC improves the
microprocessor's burst performance by three clocks. And
thus, the impetus behind the growing demand for EDO
DRAMs (see technical note TN-04-Z9, "Maximizing EDO
Advantages at the System Level").
A prudent system designer can generally deliver the best
price/ performance ratio by using 70ns DRAMs rather tha,n
pay speed premiums for 50 and 60ns DRAMs. WIth today s
computing architectures, one should not assume a faster
DRAM equates to noticeable microprocessor performance
improvement.
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MULTIPLE-CLOCKED
MICROPROCESSORS
It is worth noting that the previous analysis is based on
non-multiple-clocked microprocessors. That is, microprocessors in which the data bus is clocking at the same
rate as the microprocessor. The performance effects of
the DRAM are more pronounced on multiple-clocked
microprocessors.
Although the percentage of DRAM main memory accesses remain the same, the amount of time a DRAM access
slows the microprocessor is no longer a one-to-one ratio
due to the multiple microprocessor clocks. This ratio is
different because each wait-state the external memory imposes on the microprocessor equates to sever~l clocks for
the microprocessor (e.g., three clocks for a tnple-clocked
microprocessor) .
A typical PC system with an Ll cache (assume Ll and LZ
each have 80 percent hit rate) will retain 80 percent of the
memory accesses internal to the microprocessor (Ll) and
direct the remaining to external memory. Of this, 80 percent
of the external memory accesses (16 percent of the total
memory accesses) go to the secondary cache. The remaining memory accesses (4 percent of th~ total memor~ accesses) go to DRAM memory. For amultlple-clocked mICroprocessor based system, the LZ cache and DRAM ~em.ory
accesses will require a higher percentage of executIOn tIme
since each external clock translates to a multiple of the
microprocessor's internal clocks.
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Figure 3
DRAM MEMORY PERFORMANCE IN PCs
TN-04-32
DT32.pm5 - Rev. 2/95
7-72
Micron Technology, Inc., reserves the right to change products or speCifi?atlons without notict
©1995, Micron Technology, Inc.
MICRON
1-·
","",CO"""
TN-04-32
REDUCE DRAM MEMORY COSTS WITH CACHE
12
10
8
6
4
2
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33 MHz
Figure 4
DRAM SPEED VS. CLOCKS IN pes
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The difference between a DX4-486 microprocessor
(33 MHz external clock, 100 MHz internal clock) and a 33
MHz DX-486 when using 50ns and 70ns DRAMs is evaluated in Table 1.
This analysis shows that clocked-multiplied microprocessors put more demand on the external memories. For
example, 70ns DRAMs require 8 percent of the memory
accessing time with a typical 33 MHz-486DX but the clocktripled 33 MHz-486DX4 requires 17 percent of the memory
accessing time. Even with this additional demand on the
DRAM memory performance, the performance improvement obtained from using a 50ns DRAM over a 70ns is
negligible. The 50ns DRAM only improves the leadoff cycle
(i.e., one clock and fails to improve the burst rate).
Table 1
EFFECTS OF MULTIPLE-CLOCKED MICROPROCESSORS
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TN·04·32
OT32.pm5 - Rev. 2195
7-73
Micron Technology. Inc., reserves the right to change products or specifications without notice.
©199S, Micron Technology, Inc.
MICRON
1-·
,''"''co",,,,
TN-04-32
REDUCE DRAM MEMORY COSTS WITH CACHE
PERIPHERAL COMPONENTS
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Besides microprocessor accesses, DRAM memory is
accessed by peripheral components. Non-cached peripheral components access the DRAM main memory over
either the ISA or the local bus. As previously discussed,
even without cache memory, faster DRAMs do not necessarily equate to increased performance.
Figure 5 depicts the leadoff and Page-Mode cycles of
today's faster DRAMs while being accessed by peripheral
components over either the ISA or the local bus. As the
DRAM speed improves, the burst rate does not improve
since the speed improvement is not sufficient enough to
reduce the number of clocks required. And in the bus
speeds used the burst rate is already at one clock.
In most cases the leadoff cycle does not change between
speed versions either. The only improvement in DRAM
memory accesses by peripheral components is obtained
when using SOns DRAMs over slower DRAMs at 33 MHz.
Additionally, main memory accesses by peripheral components are typically long streams of data (i.e., Page Mode)
which minimizes the improved leadoff time obtained from
the faster DRAMs. For example, assume a burst of 12S
words. The SOns DRAM-based main memory would only
be O.S percent faster than using 70ns DRAMs in a 33 MHz
local bus. Such a negligible performance increase makes it
difficult to justify speed premiums associated with fast
DRAMs.
information needed to answer this question. However, it is
worth noting that when L1 and L2 cache memory is utilized,
DRAM is accessed only one to four percent of the time. This
leaves the DRAM main memory in the standby mode the
remainder of the time. As mentioned in the same technical
note, SER is highly dependent on the DRAM cycle rate. A
DRAM is less susceptible to soft errors (by approximately a
factor of 20x) when in standby mode (only refresh cycles)
than when being accessed at a fast cycle rate.
Figure 6 depicts a typical 32-bit wide, 4MB, DRAM-based
main memory's mean time between failures (MTBF) over
various utilization rates (READ /WRITE accesses at 200ns).
For example: a system ",rith cache l!lemories obtaining a 96
percent hit rate (SO percent L1 and SO percent L2 Cache
memory hit rates) can expect one DRAM soft error during
125 years of continuous use because it sees only a four
percent utilization rate.
The same DRAM memory would expect one DRAM soft
error every 25 years if only L1 cache (SO percent hit rate or
20 percent utilization rate) was employed. On the other
extreme, the same DRAM memory in a non-cached (no L1
or L2 cache memory) system would see around a 50 percent
to 70 percent utilization rate. These conditions would result
in approximately one DRAM soft error every 10 years.
SUMMARY
The addition of cache memory not only achieves its
objective of minimizing microprocessor wait states, but it
also demands less of the DRAM main memory. With cache
memory, the need for faster DRAMs and parity memory are
all but eliminated in most designs. When improving main
memory speed, focus on DRAM Page Mode speed (lpC)
rather than leadoff (IRAC) speed.
DRAM SOFT ERRORS
There has been much discussion regarding DRAM soft
error rate (SER) with the common question being asked "Do
I need parity?" A previous technical note, TN-04-2S, "DRAM
Soft Error Rate Calculations," (1 Q94), discussed the issue of
parity in detail and provides a system designer with the
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DRAM SPEED vs. LOCALIISA BUS
ACCESSES
TN-04-32
DT32.pm5~
Rev. 2195
Figure 6
DRAM MTBF TO SOFT ERRORS vs.
ACCESS RATE
7-74
Micron Technology, Inc., reseNes the right to change products or speCifications without notice.
©1995, Micron Technology, Inc
MICRON
1-·
TN-41-01
DECREMENT BURSTING WITH THE SGRAM
m~'ocoo""
TECHNICAL
NOTE
DECREMENT BURSTING
WITH THE SGRAM
INTRODUCTION
EXPLICIT COMMAND
Decrement bursting is a useful operation in many graphics applications, especially in a GUI environment. Any
graphics memory device that facilitates this operation, such
as the synchronous graphics RAM (SGRAM), provides
system level benefits including reduced design complexity
and increased performance.
There are several methods that can be used to achieve
full-speed decrement bursting in synchronous DRAM
(SDRAM)/SGRAM based graphics memory implementations. This note describes the various methods and the
tradeoffs associated with each.
One vendor ofSDRAMs ina graphics configuration (256K
x 16) has created an explicit command mode to accomplish
decrement bursting, however this approach has several
drawbacks. One drawback is that this command mode is
additional to the defined command set for SDRAMs/
SGRAMs. This means that both the controller and the
memory devices must contain additional logic to support
the new command mode. Another drawback is that the new
command must be executed every time there is a change in
direction (from incrementing to decrementing, and vice
versa). This results in additional overhead, in the form of
Mode Register accesses. In addition, this new command
mode is not available from other vendors.
Alternatively, the methods described below can be
achieved on any SDRAM/SGRAM with a pipelined architecture, which includes all SGRAMs and all SDRAMs tailored for graphics applications. In addition, these methods
use the existing command sets defined for SDRAMs/
SGRAMs and allow for operation at the maximum burst
rate of the device.
DECREMENT BURSTING
There are several instances in graphics applications where
it is desired to. access a series of pixels (in a line on the
display) from right to left. This might occur when performing overlapping BITBLTs or when scrolling text horizontally within a window.
Pixels are typically mapped in memory such that moving
from right to left in a section of a line on the screen means
moving from a column location with a higher address in a
row in memory to a column with a lower address. To
perform the above operation requires the ability to burst
sequentially from a starting column address to decreasing
(or decrementing) column addresses within a row.
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Figure 1
DECREMENT BURSTING - NEW COLUMN ADDRESS EVERY CYCLE
TN-41-01
GT01.pm5 - Rev. 2195
7-75
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-41-01
DECREMENT BURSTING WITH THE SGRAM
"'"""''"''''
RANDOM COLUMN ACCESS
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SUCCESSIVE BURSTS OF TWO
SDRAMs/SGRAMs with a pipelined architecture can
accept a new read or write command and column address
on each cycle during a burst access within a page. This
provides the capability to sequentially access incrementing
or decrementing column addresses, as well as to randomly
access column locations within a page at the maximum
burst rate of the device.
Providing a new read or write command and column
address on each clock cycle is the most flexible way to
achieve decrement bursting because it can be used regardless of the programmed burst length and burst type. In
addition, this method does not require any Mode Register
accesses, thereby avoiding that additional overhead. An
example is shown in Figure 1.
The only drawback of random column access is that the
address and command busses are used during every clock
cycle. However, this is no different from the way these
operations are performed with conventional FPM DRAMs
or EDO DRAMs and full-speed random access is a significant benefit.
The programmed burst length of two for SDRAMs/
SGRAMs is inherently bidirectional. If the burst starts at the
first location in the block of two; i.e., the least significant
address bit is zero, then the address will increment for the
next access; if the burst starts at the second location in the
block of two; i.e., the least significant address bit is one, then
the address will decrement for the next access. Longer
incrementing bursts can be constructed by issuing successive read or write commands to incrementing even addresses every other clock cycle. Similarly, longer
decrementing bursts can be constructed by issuing successive read or write commands to decrementing odd addresses on every other clock cycle.
In the case where a decrementing burst needs to start at an
even address, the initial command issued for the even
address simply needs to be followed immediately with the
command to the previous (odd) address. After that, a
command would be issued on every other cycle to the
decrementing odd addresses. A similar procedure would
be used to start an incrementing burst from an odd address.
After this initial orientation, if necessary, the address and
command busses are available every other cycle for other
commands. Examples are shown in Figures 2 and 3.
Additional overhead in the form of Mode Register accesses is only required if the burst of two is not the preferred
mode of operation for other accesses.
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Figure 2
DECREMENT BURSTING WITH
SUCCESSIVE BURSTS OF TWO STARTING AT AN ODD COLUMN
ADDRESS
TN-41-01
GT01.pm5- Rev. 2195
DON'T CARE
Figure 3
DECREMENT BURSTING WITH
SUCCESSIVE BURSTS OF TWO STARTING AT AN EVEN COLUMN
ADDRESS
7-76
Micron Technology, Inc., reseNes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC:RON
1-·
TN-41-01
DECREMENT BURSTING WITH THE SGRAM
","""coe,,",
SUCCESSIVE BURSTS OF FOUR OR EIGHT
A programmed burst length of four (eight) is bidirectional if starting at either the first or last location in the block
md the burst type is "interleaved". If the burst starts at the
first location in the block; i.e., the two (three) least significant address bits are all zeroes, then the address will increment for the next three (seven) accesses; if the burst starts at
the last location in the block; i.e., the two (three) least
significant address bits are all ones, then the address will
decrement for the next three (seven) accesses. Longer
incrementing bursts can be constructed by issuing successive read or write commands to every fourth (eighth)
incrementing column address on every fourth (eighth)
clock cycle, and similarly, longer decrementing bursts can
be constructed by issuing successive read or write commands to every fourth (eighth) decrementing column address on every fourth (eighth) clock cycle.
In the case where a decrementing burst needs to start at
a location other than the last in the block, individual commands must be issued on each clock until the lower boundary is reached. A command would then be issued on every
fourth (eighth) cycle to every fourth (eighth) decrementing
column address. A similar procedure would be used to start
an incrementing burst from any address other than the first
address in the block.
After this initial orientation, if necessary, the address and
command busses are available three of four (seven of eight)
clock cycles, for other commands. Examples are shown in
Figures 4 and 5.
Additional overhead in the form of Mode Register accesses is only required if the interleaved burst of four (eight)
is not the preferred mode of operation for other accesses.
SUMMARY
The SGRAM, with it's pipelined architecture, provides
high speed burst access (66-100 MHz) while still offering the
ability to change the column address for each access. This
ability leads to full-speed random, incrementing, or
decrementing burst accesses within a row in memory.
Decrement bursting in particular can be achieved using
one of several different methods which rely only on existing
command modes defined for SDRAM/SGRAMs. Each
method represents a different combination of flexibility,
complexity, overhead, and command and address bus utilization. Regardless ofthemethod sekctl'd in ,1 givl'n ,;ysh'lll,
full-speed decrementing accesses can lll' achil'vl'd wil \HlIII
a dedicated and additional command mode.
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10
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Figure 4
DECREMENT BURSTING WITH SUCCESSIVE BURSTS OF FOUR - STARTING AT THE
LAST COLUMN ADDRESS IN THE BLOCK
TN-41..()1
-
ADDRESs-{
GT01.pm5 - Rev. 2/95
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7-77
Micron Technology, !nc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
:z
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MICRON
1-·
"'"'"'""' "
TN-41-01
DECREMENT BURSTING WITH THE SGRAM
elK
COMMAND
ADDRESS
DQ
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DECREMENT BURSTING WITH SUCCESSIVE BURSTS OF FOUR - STARTING AT THE
SECOND COLUMN ADDRESS IN THE BLOCK
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TN-41-01
GT01.pm5 - Rev. 2/95
7-78
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
TN-88-01
88-PIN DRAM CARDS
'",""'co,,"
88-PIN DRAM CARDS
TECHNICAL
NOTE
INTRODUCTION
Just as SIMMs began a new period in memory placement
and packaging in the 1980s, the 88-pin DRAM card promises to have an equal impact on the industry in the 1990s.
The 88-pin· DRAM card combines the architecture of a
SIMM with an memory card form factor to create a high
density, easy-to-use memory device. No longer do endusers have to disassemble their systems and risk ESD
damage to add more SIMM modules or memory boards.
Finally, a sensible approach to memory packaging has
arrived.
For engineers, Micron's 88-pin DRAM cards offer a significant improvement in the way system designers manage
main and add-in memory. DRAM memory cards require
less system interface logic, they pack more memory into a
given area than SIMM modules and they are better able to
withstand more use and abuse than contemporary memory
upgrade schemes. All this functionality is contained in a
convenient, portable and standardized package.
Standards for the 88-pin DRAM card have been jointly
ratified by the three major standard-setting bodies: PCMCIA,
JEDIA and JEDEC. As a companion to the 68-pin memory
card, or by itself, the 88-pinDRAM card will enhance your
product design or offerings.
DRAM cards provide a rigid and durable enclosure for
the printed circuit board and memory devices contained
within. The card's physical dimensions are 2.126 ±0.004
inches wide by 3.37 ±0.004 inches long by 0.129 ±O.004
inches thick, which is about the same dimension as a credit
card, though three times its thickness.
Once assembled, the strength of the DRAM card surpasses that of SIMM modules. Moreover, since the card's
components are not subjected to direct physical contact by
the user, it can withstand casual, even abusive, handling
much better than a SIMM module. When a SIMM module
is installed, removed or transported, there is a risk of inflicting damage due to ESD. The card is made with a
conductive plastic that allows static charges to be safely
dissipated to the ground pins via a High-Z path.
DRAM cards are designed to ease facilitation. Though
the DRAM cards appear to function like 72-pin SIMM
modules, significant differences favor the DRAM card. For
example, the DRAM card provides its own buffering for
its control lines, relieving the system board. Furthermore,
buffering enhances system performance, both from noise
reduction and reduced capacitive loading of the control
lines.
The DRAM cards are preferable to SIMMs in small
profile notebook and palmtop computers, because the cards
offer a twofold improvement in board area usage. Proper
choice of receptacle connector for the system board provides the ability for hot insertion or removal, which is
impossible for a SIMM module. And the DRAM card's size
and ruggedness make it ideal for mainframe or industrial
applications.
TN-sa-01
CT01.pm5 - Rev. 2/95
PRESENCE-DETECT BITS
TOTAL MEMORY SIZE
PD1
PD2
PD3
PD4
1
1
1
1
n/a
n/a
256K
0
0
0
0
1MB
2MB
512K
1
0
0
0
2MB
4MB
1 Meg
0
1
0
0
4MB
8MB
2 Meg
1
1
0
0
8MB
16MB
4 Meg
0
0
1
0
16MB
32MB
8 Meg
1
0
1
0
32MB
64MB
16 Meg
0
1
1
0
64MB
128MB
7-79
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MEMORY ADDRESS RANGE
no card installed
-I
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Table 1
MEMORY ADDRESS RANGE
DRAM ADDRESS
SPACE PER BANK
•
PD5=O
PD5 = 1
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995. Micron Technology, Inc.
u II::1=1CN
TN-88-01
88-PIN DRAM CARDS
m~,""""c
1-·
PRESENCE-DETECT DEFINITIONS FOR
THE 88-PIN DRAM CARD
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It is necessary to clarify the presence-detect definitions
for the 88-pin DRAM cards. The eight presence-detect pins
are divided into four groups, consisting of memory size
(four bits), number of DRAM banks (1 bit), DRAM access
timing (two bits) and refresh control (I bit). As shown in
Table 1, presence-detect bits are defined as a = ground,
1 = open.
Presence-detect bits POI, PD2, PD3 and PD4 relate to the
byte size of the card or its memory address range. The PD5
presence-detect indicates the number of memory banks
present on the card. The card will be provided with either
one or two banks (32-bit version) or two or four banks
(I6-bit version).
For 32-bit applications, PD5' s definition relates to whether
one or two banks are present. Each bank is defined by two
RAS lines. In other words, both RAS lines should be
activated simultaneously for a 32-bit word access. When
PD5 = 0, there is one bank present, activated by RASa and
RAS2. When PD5 = 1, there are two banks present. Bank 1
is activated by RASa and RAS2 while Bank 2 is activated by
RASI and RAS3.
For 16-bit applications, PD5' s definition relates to whether
two or four banks are present. Each bank is defined by a
single RAS lines. When PD5 = 0, two banks are present,
activated by RAsa and RAS2. WhenPD5 = 1, two additional
banks are present, activated by RASI and RAS3. A logical
progression within the system's address space would be
RASa, RAS2, RASI and RAS3 in that order. For a 32-bit data
bank interpreted as an 16-bit card, RAS relates to the data
bus as shown in Table 2.
The PD6 and PD7 presence-detects indicate the access
time of the card from RAS true to data-out. They are defined
in Table 3.
The PD8 presence-detect is related to the refresh type of
the card, either SELF REFRESH when PD8 = 0, or an
extended refresh when PD8 = 1. Presently, all DRAM cards
will leave PD8 open, indicating that the system should
provide refreshing, preferably a CAS-BEFORE-RAS type of
refresh. This allows an address-independent refresh, which
allows interchangeability among different card types.
Table 3
DATA-OUT ACCESS TIME
Table 2
RAS RELATION TO DATA BUS
RASO
00-017
ACCESS TIME
Bank 1
RAS1
018-031
Bank 2
RAS2
00-017
Bank 3
RAS3
018-031
Bank 4
PD7
PD6
100ns
(or 50ns for future cards)
0
0
80ns
0
1
70ns
1
0
60ns
1
1
-t
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TN-88-01
CT01.pmS- Rev. 2/95
7-80
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC:~CN
1-·
,....
TN-88-01
88-PIN DRAM CARDS
'"
Table 4
32-BIT PRODUCT OFFERINGS
PRODUCT NUMBER
(32-BIT SERIES)
MEMORY
SIZE (MB)
WORD LENGTH
(BITS)
POWER
SUPPLY
SPEED
MT8D88C.132-xx
4
16,32
5V
60-80ns
MT8D88C132V-xx
4
16,32
3.3V
70-80ns
MT16D88C232-xx
8
16,32
5V
60-80ns
MT16D88C232V-xx
8
16,32
3.3V
70-80ns
MT8D88C432V-xx
16
16,32
3.3V
60-80ns
MT16D88C832V-xx
32
16,32
3.3V
60-80ns
PRODUCT OFFERING
ations. Micron has invested considerable time and effort
into developing superior card frames, covers and components. Our custom design services break down the significant entry barriers to this burgeoning market and will get
your product to market on time and on budget. Design
services include:
DRAM cards are offered through Micron. The current
product spectrum provides memory sizes from 4MB to
32MB with x16/x32 data path, and both 5V and 3.3V
operation. Micron's product offering is shown in Table 4.
The series is provided with speed grades from 80ns to 60ns.
This is specified with a -8, -7 or -6 suffix to the part number
where "xx" is shown. The cards use low-power, extendedrefresh DRAMs. Cards using a 3.3V supply have their part
number appended with a "V" option.
In addition, all versions of the standard DRAM card are
available in a two-inch-Iong, bufferless version. Contact
Micron for further details
•
•
•
•
•
•
•
•
•
•
SERVICES
Micron stands ready to help customers who wish to enter
the IC DRAM card market with proprietary solutions. Our
staff engineers are well-versed in the design of boards for
the entire PCMCIA/JEDEC/JEIDA arena. If one of our
standard products does not meet your current needs, we
are ready and able to design a custom solution for you.
For customers desiring a standard product under private
label, Micron can supply current products labeled and
marked in virtually any manner the customer wishes. Simply supply us with the desired artwork and markingsMicron will do the rest.
Often overlooked by companies considering entrance
into the DRAM card market are the mechanical consider-
TN·88-o1
CT01.pm5 - Rev. 2f95
Design from concept
Schematic capture
Board layout
Enclosure design
Thermal and signal noise analysis
Custom marking
Comprehensive testing
Connector redesign
ASIC solutions
Packaging solutions
Applications engineering assistance is also available
from 8 a.m. to 5 p.m. Mountain Time by calling 208368-3900.
The DRAM card arena is very fast-paced. Product development and introduction will quickly outdate current
information. When contemplating a design in this arena,
please call us for the latest product datasheets and design
guidelines.
7-81
Micron Technology, Inc., reserves the right to cha~e products or specifications wilhout notice.
<01995, Micron Technology,lnc.
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88-PIN DRAM CARDS
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CT01.pm5- Rev. 2/95
7-82
PRODUCT RELIABILITy ................................ .
OVERVIEW
appears below, where h(t) is the hazard rate or the
probability of a component failing at to + 1 in time if it has
survived at time to'
The reliability curve in Figure 1 is divided into three
segments: infant mortality, random failures and wearout.
The term "infant mortality" refers to those ICs that would
fail early in their lives due to manufacturing defects. To
screen out such failures, Micron evaluates all our products
using intelligent burn-in. This unique AMBYX@intelligent
burn-in/ test system developed by Micron is described in the
following section.
Product reliability is a product's ability to function
within given performance limits, under specified operating
conditions over time. This section contains a brief overview
of some of the issues that affect the reliability of Ie
devices and briefly describes Micron's reliability program.
For a more in-depth discussion of reliability, please
refer to Micron's Quality/Reliability literature.
RELIABILITY GOALS
When we discuss reliability goals of semiconductor lCs,
we typically refer to the traditional reliability curve of
component life. The reliability curve, or "bathtub curve,"
Infant
Mortality
Wearout
Random Failures
Cumulative
Failure Rate
F(t)
I-------Useful Life - - - - -.. 1
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MTBF Applies in this Range
r-
:;
-tIJ
Time
Infant
Mortality
Hazard Rate
h(t)
Wearout
.
.
Useful Life
MTBF Applies in this Range
Random Failures
Time
Figure 1
RELIABILITY CURVE
RELIABILITY
Rev. 2/95
8-1
Micron Technology, Inc., reserv9sIhe right to change products or specifications without notice.
©1995, Micron Technology, Inc.
AMBYX is a registered trademark of Micron Technology, Inc.
MICRON'S AMBYX® INTELLIGENT
BURN-IN AND TEST SYSTEM
II
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Burn-in refers to the process of accelerating failures that
occur during the infant mortality phase of component life
to remove the inherently weaker devices. The process has
been regarded as critical for ensuring product reliability
since the beginning of the semiconductor industry. To
effectively screen out infant mortalities, Micron believes it
is critical to functionally test devices several times during
the burn-in cycle without removing them from the burnin oven. In 1986, when we were unable to find a system
that met our requirements, we introduced the concept of
"intelligent" burn-in and developed the AMBYX intelligent
burn-in and test system. Today, ,·ve use . AJvfBYX
.
to test
every component product we make.
With AMBYX, we can determine if the failure rate
curves of individual product lots reach the random failure
region of the bathtub curve by the end of the burn-in
cycle. We subject product lots that do not exhibit a stable
failure rate to additional burn-in. This burn-in flow also
brings to our attention the slightest variation in a product's
failure rate.
Since AMBYX allows us to test devices for functionality
without removing them from the burn-in oven, we
effectively eliminate failures resulting from handling,
thereby minimizing "noise" from the test results. During
the test phase, output produced by the devices under test
is compared to the pattern expected. If a discrepancy
occurs, AMBYX records the failure and provides the bit
address, device address, board address, temperature, Vee
voltage, test pattern and time set.
During the burn-in cycle itself, devices are functionally
tested in four intervals. The first test begins at room
temperature. Then we ramp up the oven to 85°C for more
functional testing. This enables us to detect thermal
intermittent failures, another unique feature of intelligent
burn-in. We conduct the next test at 125°C - any device
that does not pass this sequence is eliminated. As the
burn-in process continues, the devices are dynamically
stressed at high temperature and voltage for a given
number of hours. At the end of this period, we functionally
test all devices again, followed by another burn-in cycle
and further tests. This sequence is repeated four times on
every device in every production lot. These test results
allow us to identify individual failureS after each burn-in
cycle.
There are tvvo irnportant reasons why :Lviicron conducts
the last two burn-in and test periods (or "quarters") at
lower Vcc than the first two portions. First, we want the
several million device hours that we accumulate weekly
on production lots to be conducted at stress conditions
identical to the conditions for the extended high-temperature-operating-life (HTOL) test used by IC manufacturers
to compute random field failure rates. Second, we want to
be sure we are not introducing new failure modes unrelated to normal wearout, such as VOS, by testing them at
extremely elevated conditions.
Trend charts, such as the one shown in Figure 2, alert us
to trends in lot failure rates. When we detect an upward
trend in a failure rate, we correlate the lots that need
additional burn-in with all the variables that might be
influencing the increased rate.
The overall benefits of intelligent burn-in are wide
ranging. Intelligent burn-in allows us to identify early-life
failures and failure mechanisms as they would actually
occur in customer applications. It also allows us to identify problem lots that, if undetected, could contribute
substantially to infant mortalities.
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------ ......... -...
1\
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10
20
i
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\
30
40
WorkWeek
Figure 2
AMBYX FOURTH QUARTER FAILURES
RELIABILITY
Aev.2195
8-2
Micron Technology, Inc., reserves the right to change products or specificatlOns without notioe
©1995, Micron Technology, Inc.
AMBYX is a registered trademark of Micron Technology,lnc
MICRON
1-·
PRODUCT RELIABILITY
OVERVIEW
'''""'CO"''''
ENVIRONMENTAL PROCESS
MONITOR PROGRAM
Micron's environmental process monitor (EPM) program
is designed to ensure the reliability of our standard products.
Under this program, we subject weekly samples of our
various product and package types to a battery of stress
tests.
During these tests, we stress the devices for many hours
under conditions designed to simulate years of normal field
use. We then apply equations derived from intricate
engineering models to the data collected from the accelerated
tests. From these calculations, we are able to predict failure
rates under normal use. Table 1 shows the conditions for
these tests, known as environmental stress tests. The EPM
program described in Table 1 is for Micron's 3.3V 16 Meg
DRAM.
Table 1
SAMPLE ENVIRONMENTAL PROCESS MONITOR - 16 MEG DRAM
TEST NAME AND DESCRIPTION
TEST DURATION
BIWEEKLY SAMPLE SIZE
HIGH TEMPERATURE OPERATING LIFE
(125°C, 4.3V, Checkerboard/Checkerboard Complement Pattern)
1,008 Hours
50 Devices
TEMPERATURE AND HUMIDITY
(85°C, 85% RH, 4V, Alternating Bias)
1,008 Hours
50 Devices
AUTOCLAVE (121°C, 100% RH, 15 PSI, No Bias)
96 Hours
50 Devices
LOW TEMPERATURE LIFE
(-25°C, 4.5V, Checkerboard/Checkerboard Complement Pattern)
1,008 Hours
15 Devices
TEMPERATURE CYCLE
(-40°C for 15 min., +85°C for 15 min, air to air)
1,000 Cycles
50 Devices
700 Cycles
50 Devices
THERMAL SHOCK
(-55°C for 5 min., +125°C for 5 min., liquid to liquid)
HIGH TEMPERATURE STORAGE (150°C, No Bias)
ELECTROSTATIC DISCHARGE (+ and-)
SYSTEM SOFT ERROR
(3V, 0.3ms, Checkerboard/Checkerboard Complement Patterns)
RELIABILITY
Rev. 2/95
50 Devices
40 Devices
-
Vcc LATCH-UP (MIN voltage, 25°C)
NOTE:
1,008 Hours
MIL-STD-3015.7
168 Hours
10 Devices
1,020 Devices
Samples used in the EPM program are taken from five different lots at finished goods. Before being subjected
to environmental testing, all surface-mount products are run twice through an infrared (IR) ref low furnace,
reaching a peak temperature of 240°C.
8-3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
II
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FAILURE RATE CALCULATION
The failure rate during theusefullife of a device is expressed
as percent failures per thousand device hours or as FITs
(failures in time, per billion device hours). Using Micron's 16
Meg DRAM as an example, the failure rate is calculated as
follows:
Failure Rate =
Thus, the failure rate of the Micron 16 Meg DRAM family
is computed as follows:
= 1.454 X 10-"
(1.125 x 106 )(56)
Pn
Device hours x AF
where: total device hours at test conditions = 1.125 X 106.
Equivalent device hours at typical use conditions
(50°C, 3.3V Vee) using an acceleration factor of
56 equals 56 (1.125 x 106) = 63 X 106 •
where: Pn = Poisson Statistic (at a given confidence
level). In our example given seven device
failure, Pn = 0.916 at 60 percent confidence
level.
To translate this failure rate into percent failures per
thousand device hours, we multiply the failure rate obtained
from the equation above by 105:
Device hours = sample size multiplied by test time
(in hours) In our example, device hours equal
1.125 x 106 in an accelerated environment.
From the table below, device hours equal:
Failure Rate = (1.454 x 10-8) x 105 = 0.001454% or 0.0015%
per lK device hours
To state the failure rate in FITs, we multiply the failure rate
obtained from the equation above by 109 :
(1,125 x 168) + 0,125 x 168) +0,122 x 168)
+ 0,115 x 168) + 0,106 x 168) + 0,105 x 168)
= l,125,264 or 1.125 x 106
II
0.916
Failure Rate =
Failure Rate = (1.454 x 10-8) x 109 = 1.454 or 15 FITs.
AF = acceleration factor between the stress
environment and typical use conditions. For
the 16 Meg DRAM, the acceleration factor
between 125°C, 4.3V (HTOL stress conditions)
and 50°C, 3.3V (typical operating conditions)
equals 56. (Calculation of this acceleration
factor is described in the following section.)
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Table 2
HIGH TEMPERATURE OPERATING LIFE (HTOL)
Sample No.
168 Hours
336 Hours
504 Hours
672 Hours
840 Hours
1,008 HDurs
1
010225
010225
010225
010225
010225
010225
2
3
010307
010307
010307
010306
010306
010306
010527
010527
010524
010522
010513
010513
4
010066
010066
010066
010062
010062
010061
Total
0/1125
1/1125
0/1122
0/1115
0/1106
011105
RELIABILITY
Rev. 2195
8-4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
ACCELERA nON FACTOR CALCULAnON
ACCELERATION FACTOR DUE TO VOLTAGE
STRESS
The acceleration factor due to voltage stress is computed
using the following model:
Again, using the 16 Meg DRAM as our example, the
acceleration factor between high temperature operating life
stress conditions (125°C, 4.3V) and typical operating
conditions (50°C, 3.3V) is computed using the following
models:
ACCELERATION FACTOR DUE TO TEMPERATURE
STRESS
The acceleration factor due to temperature stress is
computed using the Arrhenius equation, which is stated as
follows:
where:
Vs and Vo = stress voltage and typical operating voltage,
respectively, in volts
~ = constant, the value of which was derived
experimentally by running several sessions
of Micron's intelligent burn-in test sequence
at different voltages on large numbers of the
device. (For the 16 Meg DRAM used in our
example, ~ equals 2).
Boltzmann's constant, which is equal to
8.617 x 10-5 eV /K.
To and Ts = typical operating and stress
temperatures, respectively, in kelvins.
E = activation energy in eV. (For oxide defects,
which is the most common failure mechanism
for the 16 Meg DRAM used in our example.
The activation energy is determined to be
O.3eV.)
where: k
=
Thus, the voltage acceleration factor for the 16 Meg DRAM
between 4.3V (stress condition) and 3.3V (typical opcratir.g
condition) is computed to be 7.39.
Finally, the overall acceleration factor due to temperature
and voltage stress is calculated as the product of the
two respective acceleration factors or:
AFoverall = AFtemperature X AF voltage
Using these values, the temperature acceleration factor
between 125°C and 50°C is computed to be 7.62.
=
7.62 X 7.39
=56
•
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RELIABILITY
Rev. 2/95
8-5
Micron Technology, Inc., reserves the right to change products or specifications Without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PRODUCT RELIABILITY
OVERVIEW
"'"",,"G""
OUTGOING PRODUCT QUALITY
Before being sent to our finished goods area, where
products are prepared for shipping, a special unit within the
quality assurance department takes a sample from each
production lot. These samples are subjected to visual and
electrical testing to measure the acceptable quality level
(AQL) of all outgoing product. Test flows for new products
that have not met required production volume and ppm
levels are more comprehensive than for mature products.
Over a period of time, as a product matures, the objective is
to eliminate those tests which devices never fail. AQL testing,
although it is performed on only a small percentage of each
product, is much more exhaustive. Conducted at spec
conditions without guard band for every known timing..
pattern and background, itis a sanity check on the production
test flow. Its purpose is to detect subtle shifts in defect
mechanisms which the production test flow may not catch.
•
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Visual testing for mechanical defects consists of visual
inspection of the sample devices for any physical irregularities
that could negatively affect device performance. If a sample
device is found to have, for example, a bent lead, a package
irregularity or excess solder, the entire lot is returned to our
test area for a 100 percent visual inspection.
Electrical testing of the sample devices is performed using
automatic test equipment (ATE) systems. Testing is
conducted at O°C, or room temperature (-25°C) and at 70°C.
Should an electrical failure occur, a quality assurance engineer
further evaluates the failing device. After completing this
analysis, the quality assurance engineer determines which
production monitor/test should have caught the failure,
and the devices are retested beginning at that point in the test
flow. These are important steps to preserve the integrity of
our test process.
AUTOMATED DATA CAPTURE AND
ANALYSIS
Micron has developed a sophisticated data capture and
analysis system with a computer network tailored to the
needs of quality IC manufacturing. Figure 3 shows the
various functional areas that provide the input to our VAX
data bases.
:;!
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Experimental desiqn
and evaluation
• ~orrelation reports
• XlR charts, P charts
• Automatic e-mail
notification
Mainframe Computer
360 Gigabyte Hard Disk
Reliability
Performance
Assembly
Yield
Figure 3
STATISTICAL CORRELATION
RELIABILITY
Rev. 2195
8-6
Micron Technology, Inc., reserves the right 10 change products or specifications without notice
©1995, Micron Technology, Inc.
DATA CAPTURE
Automated, real-time data capture makes real-time
charting (X and R charts, etc.) of all critical operations and
processes possible and ensures that appropriate personnel
know of any unexpected variation on a timely basis. As
production lots move through each manufacturing step,
detailed information (including step number, lot number,
machine number, date/time, and operator number) is
entered into the production data base. Automated, highlyprogrammable measurement systems capture a host of
parameters associated with equipment, on-line process
material and environmental variables.
Another regularly produced report analyzes a userselected set of database parametrics against an index, such as
manufacturing yield. Lots are divided into three subgroups
(upper yielding, middle yielding and lower yielding). The
report then correlates the yields with all electrical parametric
values taken on individual lots at wafer sort. It helps us
determine which processing step may have caused the yields
to vary among the three subgroups.
STATISTICAL PROCESS CONTROL (SPC) CHARTS
Micron employs SPC control charts throughout the
company to monitor and evaluate critical process parameters,
such as critical dimensions (CDs), oxide thickness, chemical
vapor depositions (CVDs), particle counts, temperature and
humidity, and many other critical process and product
quality parameters.
STATISTICAL TECHNIQUES AND TOOLS
By using highly flexible, on-line data extraction programs,
system users can tap this vast data base and design their own
correlation and trend analyses. Because we can correlate
process variables to product performance, we can make online projections of the quality of our finished product for a
given lot or process run. In addition, we can estimate the
impact of process improvements on quality well in advance
and can make the impact of process deviations more visible
to our engineers. This approach allows us to model yield and
quality parameters based on on-line parameters. We then
use this model to predict the final product results through
the following means:
OVERLAYS OR WAFER MAPS
Maps, which are produced for all wafers during prol1l',
show various parameters as a function of position on till'
wafer and are very useful for problem isolation. Mr
COLD FINAL
-tD
Cold Final
Parametric and functional tests are conducted at -5°C. Parametric tests are performed to detect opens, shorts, and
input/ output leakage, and to determine whether input/ output high and low levels and standby and operating
currents are within specified limits. Functional tests include low and high Vee margin, Vee bump, speed
verification, dynamic (distributed and disturbed) and static refresh, long tRAS and tCAS lows, and a full range of
algorithms and data backgrounds to verify AC parameters.
Marking
Devices are marked with ink with the following information: year, special process designator, part type, package
type and speed grade.
Scanner
Devices are optically scanned by an automated scanning machine for bent leads, incorrect splay, coplanarity
failures and tweeze failures. Passing and failing parts are then sorted into appropriate bins.
Visual Inspection
All devices determined functional are visually inspected for cosmetic defects such as bent leads, poor marks,
broken packages and poor solder. Defective products are removed and repaired, if possible. Data on the type of
defects found is carefully recorded and used for improving the manufacturing processes in both assembly and test.
AQL
A quality assurance monitoring program overseas the electrical and environmental performance of all production
lots. New products which have not met required production volume and ppm levels are held at this stage until it
is confirmed that electrical and environmental test results meet Micron's requirements.
Packaging
Devices are prepared for shipping. They may remain in tubes or they may be mecbanically placed in tape-and-reel
packages, ready for application in automatic pick-and-place machines. Products will be either dry-packed in
vacuum sealed bags, or placed in black antistatic bags.
Finished Goods
Devices are shipped through a system that maintains lot identity.
*This flow is general and is based on DRAM products.
RELIABILITY
Rev.2f95
8-10
Micron Technolcgy, Inc., reserves the right 10 change products or spec1flcatlons wit houtnotice,
©1995, Micron Technology, Inc,
AMBYX is a registered trademark of Micron Technology, Inc
PACKAGE INFORMATION ............................ ..
I
PACKAGE SELECTION GUIDE
PACKAGE TYPE
PLASTIC SOJ
REFERENCE CODE
PIN COUNT
WIDTH
PAGE
OA-1
300 mil
9-1
300 mil
9-2
OA-3
20/26
24/26
24/28
400 mil
9-3
OA-4
28
300 mil
9-4
OA-5
28
400 mil
9-5
OA-6
34
500 mil
9-6
OA-7
40
400 mil
9-7
DA-8
42
400 mil
no
;;:ru
08-1
20/26
24/26
300 mil
9-9
08-2
300 mil
9-10
08-3
28
300 mil
9-11
08-4
40/44
44/50
400 mil
9-12
08-5
400 mil
9-13
OC-1
100
14mm x20mm
9-14
REFERENCE CODE
PIN COUNT
HEIGHT
PAGE
OA-2
TSOP
TQFP
PACKAGE TYPE
MODUlESIMM
00-1 to 00-2
30
0.5"
9-15
00-3 to 00-4
30
0.8"
9-16
00-5 to 00-10
72
1.0"
9-17
00-11 to 00-12
72
1.19"
9-20
00-13 to 00-18
72
1.0"
9-21
9-25
MODULE DlMM
OE-1 to OE-3
72
1.0"
OE-4
72
1.25"
9-26
OE-5
72
1.0"
9-27
OE-6
72
1.25"
9-27
OE-7 to OE-18
168
1.0"
9-28
DRAM CARD
OF-1
88
3.37"
9-38
OF-2
88
2.0"
9-39
OF-3
88
3.37"
9-40
OF-4
88
2.0"
9-41
MICRON
1-·
PACKAGING
PLASTIC SOJ
",,""w," "
20/26-PIN PLASTIC SOJ (300 mil)
DA-1
1--------
:~;~ 1~;:~~l---------I·1
DODD
.305 (7.75)
.299 (7.59)
.340 (8.64)
.330 (8.38)
o
.050 (1.27) TYP
' - - - - - - .600 (15.24) TYP
.025 (0.64)
X30'TYP
----~..1
r-1=r"l"irr=rff"l"irr=====rff""FliF'fIril"l
SEATING PLANE - .020 (0.51)
.015 (0.38)
.275 (6.99)
.260 (6.60)
.040 (1.02)
R .030 (0.76)
•;g
o
~
C)
m
-Z
-n
o:a
s:
~
oz
-
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
9-1
Rev. 2195
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PACKAGING
PLASTIC SOJ
,","",'00. '"
24/26-PIN PLASTIC SOJ (300 mil)
DA-2
.6
.09 ----------~~~I
~------------ .6;5g;.25l
DODD
.305 (7.75)
299 (7.59)
.340 (8.64)
.330 (8.38)
I
PIN #1 INDEX
I
.050 (1.27) TYP
~
.600 (15.24)TYP
I I--- I
----I
•;g
o
II
---II--
~
G)
.020 (0.51)
.015 (0.38)
.025 (0.64)
MIN
m
-z
"o
:IJ
s:
-o~
z
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
9-2
Rev. 2/95
Micron Technology, Inc., reserves the right to change products or speclflcations without notice
©1995, Micron Technology, Inc
MIC:RON
PACKAGING
PLASTIC SOJ
"'~"""'"'
1-·
24/28-PIN PLASTIC SOJ (400 mil)
DA-3
1 - - - - - - - ;:; i~:;ii
------~·-II
"]
DOD
0
.050 (1.27) TVP
PIN #1 INDEX
f------
.650 (1651)
-------1
.025 (0.64)
X 30° TYP
II
-II-
.020 (0.51)
.015 (0.38)
.380 (9.65)
.360 (9.14)
•
~
o
~
C)
m
-z
."
o:Jl
s:
~
oz
-
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
Aev.2195
9-3
Micron Technology, Inc., reserves the right
to
change products or specifications without notIce.
©1995, Micron Technology, Inc.
MIC:RON
1-·
PACKAGING
PLASTIC SOJ
,,,"",coe,,",
28-PIN PLASTIC SOJ (300 mil)
DA-4
1 - - - - - - .729 (18.52) _ _ _ _--1"1
.723 (18.36)
DODD
~II
j II
.299 (i.59)
.340 (8.64)
.330 (8.38)
I
~O
.050 (1.27) TYP
PIN #1 INDEX
.038 (0.97)
.037 (0.94) MAX DAMBAR PROTRUSION
•;g
SEATING PLANE -
~I
.020 (0.51)
I- .015 (0.38)
.275 (6.99)
.260 (6.60)
o
~
C)
m
--n
Z
o
:Il
S
-o~
z
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
Rev.2f95
9-4
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc
MIC::RON
1-·
PACKAGING
PLASTIC SOJ
","",,,m '"
28-PIN PLASTIC SOJ (400 mil)
DA-5
1 - - - - - - - .729 (18.52) _ _ _ _~.-II
.723 (18.36)
DODD
.050 (1.27) TYP
•;g
SEATING PLANE .380 (9.65)
.360 (9.14)
.037 (0.94) MAX
DAM BAR PROTRUSION
o
~
G')
m
z
-
."
o:0
3:
-o~
z
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
Aev.2195
9-5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology, Inc.
MICRON
1-·
PACKAGING
PLASTIC SOJ
"""'''"''
34-PIN PLASTIC SOJ (500 mil)
DA-6
PIN #1 INDEX
.050 (1.27) TYP _
.037 (0.94) MAX DAM BAR PROTRUSION
-
•
.032 (0.81)
.026 (0.66)
.146 (3.71)
.136 (3.45)
l
r
.115 (2.92)
.105 (2.67)
.030 (0.76)
MIN
--'---clf-.-------,
--'--°1111====9111
SEATING PLANE -
~
_11_
I Ij I -
.020 (0.51)
.015 (0.38)
R .040 (1.02)
.030 (0.76)
o
~
C)
.477 (12.12)
.457 (1161)-
j
~
m
-Z
-n
o
J:I
S
!ioz
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
Rev. 2195
9-6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC:RON
1-·
PACKAGING
PLASTIC SOJ
"'"Me",,"
40-PINPLASTIC SOJ(400mil)
DA-7
1 - - - - - - - - ~g;; ~;~:~:l - - - - - - - - I I..~I
t
r· L
.405 (10.29)
.399 (10.13)
.445 (11.30)
35
05
.4
)
PIN#lINDEX
.050 (1.27) TYP
1--------
.025(0.64)
X 300 TYP
.950(24.13)
.
L~.
,.032.(0,81)
.
.026 (0.66)
r
SEATING PLANE - - -
~ ~
.037 (0.94) MAX
.
DAMBAR PROTRUSION
--II-.
.020 (0.51)
.015 (0.38)
.150 (3.81)
.138 (3.51)
.105 (2.67)
~Or90_(_2.2_9_)_ _- ,
II
t~±t
MIN
•
~
o
~
C)
m
-z
"T1
o
::a
s:
-o~
z
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
9-7
Rev. 2/95
Micron Technology, Inc., reselVes the right to change products or specifications withl>ut notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PACKAGING
PLASTIC SOJ
"o<'''coo,''
42-PIN PLASTICSOJ (400 mil)
DA-8
~~------------------ ~:~~i~::~l------------------'~~.
0000000000000000
399 (10 13)
445{11 30)
435(;105)
I
.
I
I e=~
D
DUD DUD
~~
o
DUD DUD 0
~
I
.I
.050 {1.27} TYP
1.000 (25.40)
r
D
.148 (3.76)
.025 (0.64)
X300TYP
.138 (3.51)
.032 (0.81)
.
~
II
. .
•;g
t
SEATING PLANE
~ ~
.037(0.94) MAX
~ ~
DAM BAR PROTRUSION
.020(0.51)
.015 (0.38)
o
~
C)
m
-z
."
o
::c
3:
-o~
z
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
Rev.21g5
9-8
Micron Technology, Inc., reserves the right to change products or specifications wfthoul nolice.
©1995, Micron Technology, Inc.
MICRON
1- •
PACKAGING
PLASTIC TSOP
"'"",co", '"
20/26-PIN PLASTIC TSOP (300 mil)
D8-1
7.;;-7~(1_='7._7:20:;:.)-----1
-.-----.:.;.60::
.673 (17.10)
-I -
1
SEE DETAIL A
.037 (0.95)
t
.367 (9.32)
.359 (9.12)
.302 (7.67)
.298 (7.57)
m°"""TT""T1;--;r-"T,----TT""TT'""TT""TT"--,,'--t
_11_
PIN #1 INDEX
.050 (1.27)
TYP
.007 (0.18)
.005 (0.12)
.020 (0.50)
.012 (0.30)
=~-~-~jQ
.04~i~20) IOI.::::~~:) PLANE _t_g
1.01010.""
I~ t_
__
.00810.20)
.002 (0.05)
--=
DETAIL A
.032 (0.81)
~0.60)
1.024
.016 (DAD)
•;g
o
~
G)
m
-z
"TI
o
::c
s:
!fo
z
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
9-9
Rev. 2/95
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron TechnOlogy, Inc.
MU::I=ICN
1-·
PACKAGING
PLASTIC TSOP
","""en"
24/26-PIN PLASTIC TSOP (300 mil)
D8-2
1
-·------~·6=77~(1~7.2~0~).------~~1
.673 (17.10)
-I -
--/
.037 (0.95)
/~\
\
I
.359 (9.12)
~
I
10B B B B B B B B B B B "T~ j
_I 1_
-11-
/B
PIN #1 INDEX
.050 (1.27)
TYP
•;g
I
/
1 "')'32'
.302 (7.67)
SEE DETAIL A
_11_
.007 (0.18)
.005 (0.12)
.020 (0.50)
.012 (0.30)
t
.047 (1.20)
MAX
o
~
[.010 (0.25) [
101·004 (0.10) 1
SEATING PLANE
t
t
::;-:::~
_ _-j-+--'----l
.008 ;0.20)
.002 (0.05)
-=I
DETAIL A
.032 (0.81)
:1:0)
.016 (0.40)
C)
m
-z
II
o
::D
S
-o~
z
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
9-10
Aev.2!95
Micron Technology, Inc., reserves the rlghllo change products or specifications withoul notice.
©1995, Micron Technology, Jnc.
MIC:I""""'IlCN
1-·
I"""t
"C"
PACKAGING
PLASTIC TSOP
,
28-PIN PLASTIC TSOP (300 mil)
DB-3
.727 (18.46)
- - - - .723 (18.36)
---~··1-.037 (0.95\
SEEDETAILA
r- /
-~
1
.340 (8.64)
1 .330 (8.38)
I
\
\
J
/
.305 (7.75)
.299 (7.59)
~~~~~~~~.___l
PIN #1 INDEX
.050 (1.27)
TYP
_11_
14
-11-
.020 (0.50)
.012 (0.30)
.007 (0.18)
.005 (0.12)
MnnnnnnnnnnnnnH
j
.047 (1.20) - '
1.010 (0.25>1
101·004(0.10)1
I
MAX
f+----'SEATING PLANE
.008 (0.20)
.002 (0.05)
-.---t-+"--l
J
DETAIL A
GAGE PLANE
_·-t.024 (0.60)
.016 (0.40)
.032 (0.81)
•;g
n
~
G)
m
-z
'TI
o
:::D
s:
NOTE:
1. All dimensions in inches (millimeters)
~ or typical IoI(here noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
Aev.2195
9-11
Micron Technology, Inc., l'9$erves the right to change products or specifications without notice.
@1995,MlcronTechnology,lnc.
-oz~
MICRON
1-·
PACKAGING
PLASTIC TSOP
",",",co,,,,
40/44-PIN PLASTIC TSOP (400 mil)
D8-4
_ _ _ _ .727 (18.46) _ _ _~I
.723 (18.36)
__ /
-
SEE DETAIL A
.032 (0.81)
(L86)
1 .467
.459 (11.66)
.402 (10.21)
.398 (10.11)
/
PIN #1 INDEX
LoBBBBBBBBBB
-I 1-
.0315 (0.80)
TYP
BBBBBBBBBB
I
I
j
_11_
-11-
.007(0.18)
.005 (0.12)
.018 (0.45)
.010 (0.25)
1.010 (0.25) 1
t
•
I
IQI·004 (0.10) 1
.047 (1.20)
MAX
I
.00810.20)
.002 (0.05)
~
1-
R------.C
GAGE PLANE
SEATING PLANE =-:::-':::---+-l-'---.J
DETAIL A
~0.60)
---=::1.024
.016 (0.40)
.032 (0.81)
o
~
C)
m
-z
."
o
:0
:s:
-o~
z
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
9-12
Rev. 2/95
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron TechnolOgy, Inc.
MIC:RON
1-·
PACKAGING
PLASTIC TSOP
"'""'00","
44/50-PIN PLASTIC TSOP (400 mil)
D8-5
_ - - - - .827 (21.01) _ _ _ _ _ 1
.823 (20.91)
__ /
-I -
.035 (0.88)
SEE DETAIL A
,
/
t.86)
1 .467
.459 (11.66)
.402 (10.21)
.398 (10.11)
~~"IT1""I"UU""'-j
0
J'i-rn-rrr
PIN #1 INDEX
.0315 (0.80)
TYP
_11_ .007
(0.18)
.005 (0.12)
-11.018 (0.45)
.012 (0.30)
h Q9Jj t;1 Q Q tj FJ Qtu
1.010 (0.25) I
101.004 (0.10) 1
.047 (1.20)
MAX
+
+
SEATING PLANE --,-------I------P----J
.008)0.20)
.002 (0.05)
-=
I: 1 : 0 )
.016 (OAO)
.032 (0.81)
DETAIL A
•
~
o
~
C)
m
-z
'TI
o
::D
s:
!io
z
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and h:mgth do not include mold protrusion; allowable mold protrusion is .01" per side.
PACKAGING
9-13
Rev. 2195
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology. Inc.
MIt:r!""aCN
1-·
~ ~
c
PACKAGING
PLASTIC TQFP
,
100-PIN PLASTIC TQFP
DC-1
GAGE PLANE
.0098 (0.25)11
i
Pin #1 INDEX
+
•
~
_ ..1 - - - -
o
~
n
---I$;f---
--L .030 (0.75)
.018 (0.45)
-.l I
.795 (20.20)
.783 (19.90)
.870 (22.10)
.862 (21.90)
L
.0256 (0.65)
.0150(0.38)
.0087 (0.22)
.634(16.10) _ _ _ _ I
.626 (15.90)
"-z
m
"T1
o
:EI
s:
-oz~
NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is.01" per side.
PACKAGING
Rev. 2195
9-14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995,MlcronTechnology,lnc.
30-PIN SIMM
00-1
.200 (5.08)
MAX
I-I
Jl
.054 (1.37)
.047 (1.19)
.080 (2.03)
.100 (2.54)
.070 (1.78)
TYP
TYP
•
30-PIN SIMM
00-2
~
o
.200 (5.08)
MAX
I-I
~
~
C)
~- ~
.054 (1.37)
.047(1.19)
.080 (2.03)
.100 (2.54)
.070 (1.78)
TYP
TYP
."
o
::D
3:
-o~
z
NOTE:
PACKAGING
Rev. 2195
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
.
9-15
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
MIC:r"""aCN
1-·
..... ,
PACKAGING
SIMM MODULE
,
30~PIN
SIMM
00-3
_I' I_
3.510(89.15)
3.490 (88.65)
I
'
[llJ'
'125(3-r!r~4
! O
'I - 1
~
~-
a J ] '
--
.250(6.35) _ _ _
.400 (10.16)
~~~I"!I"!I"!
t_l_ ~PIN1
.080 (2.03)
_11_
_11_
.100 (2.54)
TYP
.070 (1.78)
TYP
•
.200 (5.08)
~~ (3.37)
MAX
.810~0.57)
.790 (20.07)
I
_TY....,.p_ _ _--'~_
I
.054 (1.37)
.047(1.19)
t
3O-PIN SIMM
00-4
~
o
~
G')
I,
3.510 (89.15)
3.490 (88.65)
_I' I_
DJD'I
~ '125(3-r!r~~iDJlJ]'
0 '
'
.,'.,'.
Z
o
~
I
I
."
"
--
.250(6. 351__,
'Q-
,~
'"
~~
_
t~J:; ~PIN1
~
,
'.
~(l:
j(\:
~
.200 (5.08)
;;~ (3.37)
_I
.400(10.16)
MAX
I
I
.810 (20.57)
.790(20.07)
_TY....,.P_ _ _- - ' _
t
I
~
a
z
NOTE:
PACKAGING
R~v.~
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-16
Micron Technology, Inc•• reserves the right to change products or specifications without notice.
@1995,MlcronTechnology,lnc.
MIC:I"""IICN
1-·
..... "
PACKAGING
SIMM MODULE
"
72~PIN
SIMM
00-5
I
4.260 (108.20)
4.240 (107.70)
I
.200 (S.08)
MAX
.
~:J===~£~I~ft
I '\
__
.080 (2.03)
I I
~ 1.7S(44.45)TYP--
PIN 1 . 2 5 0 (6.35)
-
I
-
.050 (1.27)
TYP
I
~I I~ TYP
.133(3.38)
...,.- -
I~I
1
054 137
:0471:19)
.040 (1.02)
TYP
1-~3.7S(95.25)--1
•
'~:J==~=~I·~f+ ~- ~
72-PIN SIMM
00-6
I
I
~
I I
_ _ ~ 1.75(44.45)TYP-_ . .
.080 (2.03)
I
4.260 (108.20)
4.240(107.70)
PIN 1
.250 (6.35)
I
--: _
.050 (1.27)
TYP
_
I
_
-I
.040 (1.02)
TYP
1--3.75(95.25)--1
.200 (S.08)
~I
1_,133(3.38)
TYP
.
.
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:047(1:19)
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PACKAGING
SIMM MODULE
,
72-PIN SIMM
00-7
.200 (5.08)
::~~g~:~l-----------I-'II-:iv~ (3.38)
.125 (3.18)
TVP
.250 (6.35
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~'fDDq,D~
t
-!!- -II-~J!.080 (2.03)
1.75 ( 4 4 . 4 5 ) T V P - ! - !
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.250 (6.35)
.050 (1.27)
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040 (1 02)
TVP
MAX
1
1.01025.
~
.990 (25. 15)
l..
I
.400(10.16)
TVP
I
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.054 (1.37)
.047(1.19)
.235 (5.97)
MIN
3.75 (95.25)
•;g
72-PIN SIMM
00-8
n
.350 (8.98)
MAX
~
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m
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.125 (3.18)
TVP
DDDDl
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.250 (6.35
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-=-!.080 (2.03)
3:
1.75 (44.45) T V p - I - 1
PIN 1
.250 (6.35)
-11- -II.050 (1.27)
TVP
.040 (1.02)
TVP
1
1.010
25
~
.990 (25. 15)
l..
(~0.16)
.400
TVP
I
I
.235 (5.97)
MIN
I
I
.054 (1.37)
.047(1.19)
3.75 (95.25)
!f-
oz
NOTE:
PACKAGING
Rev. 2/95
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-18
Micron Technology, Inc., reserves the right bJ change products or spectficalions without notice,
©1995, MiCron Technology,lnc.
72-PIN SIMM
00-9
_I 'I
- - - - - - - - - - ::~1~g~~~~l
1
.200 (5.08)
MAX
I-I
_.133(3.38)
TYP
r----------------------~
'::.=lowwwwpwwwp1L=*+ ~-1-
.080 (2.03)
~ . _ _.
~II- ~II-
1.75(44.45)TYP-I-1
~1
.250 (6.35)
1 - - - - - - - - - 3 . 7 5 (95.25)
.050 (1.27)
.040 (1.02)
TYP
TYP
.054 (1.37)
.047 (1.19)
.235 (5.97)
MIN
---------1
•
72-PIN SIMM
00-10
~
_I 1- ~~
_ _ _ _ _ _ _ _ _ _ 4.260(108.20) _ _ _ _ _ _ _ _ __
1
4.240 (107.70)
.350 (8.98)
MAX
(3.38)
125(3T~~_oDDDDDDDDD1_1 -L
0
.400 (\0.1.:: (j25.15)
7
~~I
--=-1.080 (2.03)
~1.75(44.45)TYp-I-I
~1
.250 (6.35)
.235 (5.97)
.050 (1.27)
TYP
.040 (1.02)
TYP
0
~
G')
m
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-
II
.054 (1.37)
.047 (1.19)
MIN
1---------3.75 (95.25)---------1
0
lJ
s:
-0~
Z
NOTE:
PACKAGING
Rev.2f95
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-19
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PACKAGING
SIMM MODULE
",",me"""
72-PIN SIMM
00-11
I
4.260 (108.20)
4.240 (107.70)
I
DODODD
125(3T~8~ lo~
.250(6.35) )
IDII~~~ ~~~]DDq.I_1
.200 (5.08)
MAX
I-I
1
T
D rmmmrmmmmmmmnrn n mmmmmmmmmmmrm I I 400Tr~16) j
_1_t ,·(44.45)TVP-I-1
75
.080 (2.03)
PIN 1
.250 (6.35)
-11- -11- 1-11_
TYP TVP TYP
.050 (1.27)
.040 (1.02)
~-~
.054 (1.37)
.047 (1.19)
.133 (3.38)
1----3.75(95.25)----1
III
72-PIN SIMM
00-12
.054 (1.37)
.047 (1.19)
NOTE:
PACKAGING
Rev. 2/95
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-20
Micron Technology, Inc., reserves the right to change products or sp eCITlcations without notica.
©1995, Micron Technology, Inc.
MICRON
1-·
PACKAGING
SIMM MODULE
","",,,,,,,
72-PIN SIMM
00-13
FRONT VIEW
1:~~ggg~~gl--------1
DDDDDDDD
_I - ~~
r------------------~~
.125 (3.18)
TYP
o
. . . . . . . . . . . . . . 0• • • • • • • . " • • • • • •
~....
o••••••••
~
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.040 (1.02)
TYP
TYP
MAX
~
.990(25.15)
~ ~" l.. 400~g16) j
••
-11- -11.050 (1.27)
EJI
.350 (8.98)
(3.38)
.235 (5.97)
MIN
I-I
I
.054 (1.37)
.047 (1.19)
1-------3.75(95.25)-------1
BACK VIEW
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NOTE:
PACKAGING
Aev.2195
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-21
Micron Technology, Inc., reserves the nght to change products or specifications without notice.
©1995, Micron Technology, Inc.
MU::::I=ICN
1-·
PACKAGING
SIMM MODULE
"""'co"'''
72-PIN TSOPSIMM
00-14
4.240 ( 1 0 7 . 7 0 ) .
DODD DODD
'125(3'1B)~
o
--h .
TYP
W •.
-I
4.260 (10B.20)
I
0
0
0
0
0
0
0
0
I
105 (2 67)
-:i$~ (3.3B)
II
8}
~rr-
1.010 (25.65)
1
.990(25.15)
-1-r1400_\~~16)1
"IJt~~~I,l,~;:~1
.OBO (2.03)
PIN 1
.250 (6.35)
.05~~27)
~I
~~
.04~~~02)
1 - - - - - - - - 3.75(95.25) - - - - - - - - 1
II
72-PIN TSOP SIMM
;g
00-15
o
~
G')
1~~g !~g~~gl--------_-I-I_ .133 (3.3B)
TYP
m
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.150 (3.81)
MAX
-11~
-~
:D
.054 (1.37)
.047 (1.19)
s::
~
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1--------3.75(95.25) - - - - - - - - 1
NOTE:
PACKAGING
Rev. 2195
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-22
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995,MicronTechnology, Inc.
MIC:I"""IIICN
1-·
1"""'1,
PACKAGING
SIMM MODULE
,
72"PINSIMM
00-16
g~g~:~l--------"----_-I-I- :iv~(3.38)
.125 (~.18)
'lYP
~
C)
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::D
s:
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NOTE:
PACKAGING
Rev. 2195
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
UII::::F=lCN
1-·
PACKAGING
DIMM MODULE
","",c"""
72-PIN TSOP DIMM
DE-1
1-.-----
------·1
FRONT VIEW
D D ----'-,
.079(2.00)R"--.....
(3X)
"'---....
2.360(59.94)
2.340
(59.44)
MAX
-11-
1.010 (25.65)
.071 (1.80)
(2X)
.700 (17.78)
TYP
(B
.125(3.18)1...1-
.071
.100 (2.54)
0
(~~~)(;~~~ IJJ~
197 (5.00)
I
PIN 1
=I(l: =It:~ ~
TYP
TYP
_ - - - 1 . 7 5 0 (44.45)
!
CD
0
'00'1'"
.043 (1.10)
.035 (0.90)
PIN 71 (PIN 72 on backside)
---~I
- - - - - 2 . 0 3 4 (51.66) - - - - -
•
72-PIN TSOP DIMM
DE-2
1_.-----
~
------·1
o
FRONT VIEW
2.360
2.340 (59.94)
(59.44)
.079 (2.00) R "--......
(3X)
."'---....
.071 (1.80)
(2X)
LI_
.071 (1.80) Apt
I
.125 (3.18)
.079 (2.00):::
-
.197 (5.00)
1
_
D
D
1\
I.
_
PIN 1
.040 (1.02)
TYP
1.750 (44.45)
_ - - - - 2.034 (51.66)
NOTE:
PACKAGING
Rev. 2195
----;-r
--r-
MAX
-11-
.700 (17.78)
TYP
!
CD
.050 (1.27)
TYP
""'I'"
m
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:c
.043 (1.10)
.035 (0.90)
PIN 71 (PIN 72 on backside)
---~I
s:
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--,.--~-
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-25
~
G')
o
"
1.010(25.65)
-11--11- \1L
~
.150 (3.81)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PACKAGING
DIMM MODULE
"""'''''"'
72-PIN TSOP DIMM
DE-3
FRONT VIEW
2.360 (59.44)
(59.94)
2.340
.150 (3.81)
-----~'I
MAX
n·nnnJ=t.
~('~l~~~
.071 (1.80)
~
U
(2X)
®
.125(3.18f-+-:
U
U
0
0
t II~~
.071 (1.80)T'yp
.079 (2.00)::::
.197 (5.00)
i
U
0
.040 (1.02)
TYP
I
~
I
----'---1.010(25.65)
.990(25.15)
.700(17.78)
CD
0
~II- ~IIPIN 1
·1
.
Tr
\1--'---------'L
.050 (1 27)
TYP
.043 (1.10)
.035 (0.90)
PIN 71 (PIN 72 on backside)
1.750 (44.45)
'
1
2.034 (51.66) - - - - _ 1
•
•;g
~
1-
72-PIN DIMM
DE-4
o
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FRONT VIEW
'j
.190 (4.83)
_ _ _ _ _ 2.360 (59.94) _ _ _ _ _
2.340 (59.44)
m
1-----,--
-Z
-uMAX.
.079 (2.00) R ~
(3X)
~
."
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-I
.071 (1.80)
(2X)
l:J
1.260 (32.00)
1.240 (31.50)
.700 (17.78)
TYP.
s:
I
m
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s:
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NOTE:
PACKAGING
Rev. 2195
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
MICRON
1-·
PACKAGING
DIMM MODULE
"""COO""
168-PIN TSOP DIMM
DE-16
FRONT VIEW
I
5.260 (133.80)
I
~6~rX6:
5.240 (133.10)
079(20fJx~~~
,~_
1
""'1}jj [JDDDD~DDDD~,~~,,~
."'i3.00JTY"t--111
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TYP
rf~rrmTni II Trrrnrrnmnmunmmn I ~mmrnmmrii('
.250 (6.35) TYP
.039(1.00)R(2X) -
PIN 1
I~-----
4.550(115.57)
--
-
j
--
.039 (1.00)
.050 (1.27)
TVP
TYP
j
~I
II
:~:
.046(1.17)
PIN 84
------1
BACK VIEW
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m
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s::
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NOTE:
PACKAGING
Aev.2195
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,MicronTechnology, Inc
IC:RCN
.
PACKAGING
DIMM MODULE
,,,"",we,,",
168-PIN DIMM
DE-17
FRONT VIEW
;:~~6!~;~:~6l-----------1
.079(2.00)R~
I
(2X)
118
13ig~:
(i)
j
DDDDD0 0 DO [J [J
0
0
0
0
0
0
0
0
0
0
.200 (5.GS)
MAX
I
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0
T
1.010 (2S.65)
I
.990 25.,5)
j
.118 (3.00) TIP
~I -
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.118 (3.00)
TYP
1----------
4.550 (115.57)
-11- -11-
.039 (1.00) R{2X) .039 (1.00)
TYP
~t
\
\.:i:~;l(2X)
.050 (1.27)
TYP
.054(1.37)
.046(1.17)
PIN 84 (PIN 168 on backside)
---------1
-
168-PIN TSOP DIMM
DE-18
~
0
FRONT VIEW
:~~~~~~~~~~~~~~~~~~~~~_;:_~:_6i_~;;_:~_61~~~~~~~~~~~~~~~~~~~~~~--iII ____-'- ~n:' ~
,,:::::,1
~I
0DDDDD[J[JDD[]rl~~t _~_ ~
_
.118(3.00)
'\ ~
_11_ -11-
-.039(1.QO)R(2X) .039 (1.00)
TYP
TYP
1_ _ _ _ _ _ _ _ _ _
I ~128t(325)12X)g~:g~~
0
1
::III
.118(3.00).."
.050(1.27)
TYP
",."
PIN 84 (PIN 168 on backside)
4.550(115.57) - - - - - - - - - -
;;::;.
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NOTE:
PACKAGING
Rev. 2/95
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc,
MIC:RON
1-·
PACKAGING
IC DRAM CARD
'CC~"W""'
88-PIN DRAM CARD
DF-1
II
3.378 (85.80)
3.362 (85.40)
-
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---11--
2.130 (54.10) _ _ _---;.~I
2.124 (53.95)
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....-- .126 (3.20)
1
t
.063 (1.60)
•. 059 (1.50)
.063 (1.60)
.059 (1.50)
m
.041 (1.05)
.037 (0.95)
s:
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NOTE:
PACKAGING
Rev. 2/95
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-38
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology. Inc.
MIC::RON
1-·
PACKAGING
IC DRAM CARD
"","cwe, ,,
SS-PIN REDUCED-LENGTH DRAM CARD
DF-2
2.005 (50.93)
1.995 (50.67)
[1'-----_-------'f [1413J;~501
I..
2.130 (54.10)
2.124 (53.95)
II
.041 (1.05)
- - - - .037 (0.95)
____
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~
.134 (3.40)
.126 (3.20)
/88
.063 (1.60)
.059 (1.50)
_
+
.063 (1.60)
, -t .059 (1.50)
44
.039 (1.0) TYP
1.697 (43.10) _____I
1.689 (42.90)
•
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NOTE:
PACKAGING
Rev. 2/95
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
PACKAGING
IC DRAM CARD
"'""0'""""
88-PIN DRAM CARD
DF-3
3.378 (85.80)
3.362 (85.40)
II
-t .413 (10.50)
~================~~II
~
o
•
MIN
.041(1.05)
2.130 (54.10) _ _ _ _
- _-_ --- .037 (0.95)
-
II
.134 (3.40)
- - .126 (3.20)
- - - - 2.124 (53.95)
~
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.093 (2.35)
.096 (2.45)
C)
m
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,
T
45",
88
:c::::~~~~~~~~~~~/~-' .063 (1.60)
1./ ......
'44-'
.059 (1.50)
.039 (1.0) TYP
:__--1.697143.10\--__ 1
1.689 (42.90)
S
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NOTE:
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
PACKAGING
Rev. 2/95
9-40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc
MICRON
1-·
.
m~"c,oo""
PACKAGING
IC DRAM CARD
SS-PIN REDUCED-LENGTH DRAM CARD
DF-4
2.005 (50.93)
1.995 (50.67)
============~r~[---1t.413J:~.50)
J--L:::::=l
I
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2.130 (54.10)
2.124 (53.95)
II
.041 (1.05)
--- - - .037 (0.95)
- - - -....
1
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45"
.093 (2.35) _
.096 (2.45)
88
-t- ~/
'-44
)
\.
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.134 (3.40)
.126 (3.20)
1
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.059 (1.50)
-t-
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, .....1 - - _ _
•;g
m
1.697 (43.1 0) _ _-<"~I
1.689 (42.90)
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3:
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NOTE:
PACKAGING
Rev. 2195
1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
9-41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
•;g
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PACKAGING
Rev. 2195
9-42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
I
SALES AND SERVICE INFORMATION .......... .
I'.IIlI:::RgN
SALES AND SERVICE INFORMts~?~
STANDARD SHIPPING
BAR CODE LABELS
CUSTOMER
SERVICE NOTE
INTRODUCTION
(Z) -
Micron Technology, Inc., has implemented standard bar
code labels which accompany all shipments. These labels
conform to EIA Standard 556.
The bar code labels allow customers to scan individual
Micron containers for quick order verification. Figure 1
shows an example of the standard bar code label for master
containers. Each individual box and/or container also has
its own individual bar code label (see CSN-02).
(K) (P) -
ADDITIONAL SALES INFORMATION
Ship-To-Name: Customer's name and ship-to address
Ship-From-Name: Micron name and address
Master container package count
Package weight
BAR CODE INFORMATION
The information provided on the label is:
(4S) - Invoice/Packing Slip Number
(Q) - Quantity in master container
(4S) PKG ID:
Special: Reserved for individual customer
requirements
Trans ID: Customer purchase order number
Customer Product ID: Customer part number.
If a customer part number is not designated,
the Micron part number will be printed.
+188505
SHIP_TO-".!AME
ADDRESS
CITY,ST
(Z) SPECIAL:
MICRON TECH
2805 E COLUMBIA
BOISE, . IDAHO
83706
PACKAGE COUNT:
1 OF 1
50.0 EA
PACKAGE WEIGHT:
4 LB.
Figure 1
STANDARD BAR CODE LABEL
CSN-01
RBV.2f95
10-1
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc,
•
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.
SALES AND SERVICE INFOR~~~?o~
CUSTOMER
SERVICE NOTE
INDIVIDUAL BOX AND
CONTAINER BAR CODE
LABELS
INTRODUCTION
BAR CODE INFORMATION
Micron Technology, Inc., provides a standard bar code
label on each individual box or container. The standard bar
code label allows scanning of Micron shipping containers at
a receiving dock for quick order verification.
Figure 1 shows an example of the standard bar code label
used on individual boxes.
The information provided on the label is:
Labell: Individual box number (in a multibox shipment)
Actual box number printed
Micron part number/speed/customer code
Part type/rev / quantity / date code of oldest lot*
UD/MX IE
OUS
1US
2US
III
en
»
r-
Figure 1
LABEL 1
m
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Z
C
REEL
*Indicates that more than one date code is contained on the reel.
en
m
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m
CSN-02
Rev.219S
10-2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
1"I1C:I=:II~c~
SALES AND SERVICE INFOR~~1j~~
CUSTOMER
SERVICE NOTE
SURFACE-MOUNT
PRODUCT LABELING
[NTRODUCTION
HUMIDITY INDICATOR CARD (HIC)
Micron Technology, Inc., provides a Humidity Indicator
:::ard (HIC) with all surface-mount products.
Figure 1 shows an example of the standard HIe. Figure 2
,hows approximate labeling of tape-and-reel packaged
products.
The Humidity Indicator Card is hermetically sealed in
drypack and provides an indication of the RH level of the
contents.
HUMIDITY INDICATOR
~1ilIiiJIi1illiiJli1illiiJli1illiiJli1illiiJli1illiiJli1illiiJli1illiiJli1illiiJli~ ----
Heat-sealed moisture
barrier bag
Desiccant (In sealed bag)
UlllJ IlrlllUIlQ qmlnlllll't) lOSt)
und If\(Jllllurn pftlcntillonli
C=~
--+----+--
L - _ - . - - l -~----+--
Micron Marketing Label
Customer Specification Label
Humidity Indicator Card (HIC)
Figure 1
SURFACE-MOUNT PRODUCT HUMIDITY
INDICATOR CARD
Figure 2
TAPE-AND-REEL
PACKAGED PRODUCT LABEL
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CSN-03
Rev. 2195
10-3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
BOX AND TAPE-AND-REEL
QUANTITY AND WEIGHT
CHART
CUSTOMER
SERVICE NOTE
INTRODUCTION
Micron encourages customers to place orders in increments of standard box, tray and reel quantities whenever
possible. The chart below will help determine order
quantities.
2. Process Control-Micron's production tracking system
automatically checks speeds, revs, customer codes and
quantities. When standard box quantities are ordered,
manual errors are eliminated, thus ensuring error-free
shipments.
3. Lot Integrity-lot integrity is kept in tact when box
quantities are not broken up.
4. Fewer returns-fewer errors equal fewer complaints
and returns.
ADDITIONAL SALES INFORMATION
Benefits to Micron's customers by ordering in standard
quantities:
1. Cost Savings-it is less expensive to send a shipment
containing full boxes.
DRAM STANDARD BOX AND TAPE-AND-REEL CHART
PART TYPE
•
QUANTITY
QUANTITY
LBS
QUANTITY
TAPE-ANO-REEL
LBS
TAPE
PER TRAY
PER BOX
PER BOX
PER TUBE
QUANTITY
PER REEL
SIZE
DRAM-MEGS
25
500
-
25
1000
4.1
S.O
-
24mm x 12mm
25
1000
1000
2.7
13.2
4.1
24mmx 12mm
S.O
-
1000
2.7
24mmx 12mm
13.2
25
1000
4.1
24mm x 12mm
13.2
25
1000
4.1
24mmx 12mm
4000
13.2
25
1000
4.1
24mm x 12mm
4000
12.5
25
1000
3.9
24mmx 12mm
4000
12.5
3.9
24mmx 12mm
10.0
500
3-4
44mmx 16mm
1500
12.0
25
n/a
15
1000
1000
500
4-5
44mm x 16mm
-
1500
10.0
15
500
3.51
44mm x 16mm
-
1500
10.0
15
500
3.51
44mmx 16mm
135
1000
9.0
-
500
2.5
44mmx 16mm
MT4C4M4B1-4LC4M4B 1DJ
-
2000
MT4C1004JDJ-4C4001JDJ
-
4000
MT4C1004JTG-4C4001JTG
176
1000
MT4LC4001JDJ
-
4000
»
r-
MT4LC4001 JTG
176
1000
MT4C4004JDJ
-
4000
4000
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MT4LC2MSB 1DJ
n/a
n/a
n/a
n/a
n/a
MT4C16257DJ
MT4C16270DJ
MT4C16257TG
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MT4C4007JDJ
MT4LC4M4ESDJ
MT4LC2MSE7DJ
MT4LClivi16C3TG
MT4LC1 M16C3DJ
13.2
24mmx 12mm
4 MEG SPECIALTV DRAMs
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CSN-04
Rev. 2/95
10-4
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995, Micron Technology, Inc
I"IIC:F::II;~,~
SALES AND SERVICE INFOR~~~~~
MODULE STANDARD BOX AND TAPE-AND-REEL CHART
PART TYPE
TUBE QUANTITY
BOX QUANTITY
LBS PER BOX
MT2D18MfN
MT2D2568M
5
5
400
400
11
11
MT3D19MfN
5
400
10
MT3D2569MfN
400
200
12
MT8D132MfG
5
4
MT8D25632MfG
4
200
MT8D48M
MT8D48N
5
4
400
13
17
MT9D49M
5
4
DRAM MODULES
300
400
12
11
300
18
15
4
20C
15
MT12D136MfG
4
200
15
MT16D232MfG
MT16D51232MfG
4
4
200
200
MT18D236MfG
4
MT20D51240G
4
200
200
15
15
15
MT20D240G
4
200
15
MT24D236MfG
MT8D432MfG
MT12D436MfG
4
4
200
20
200
200
15
15
MT9D49N
MT10D140MfG
15
MT12D436DMfG
4
4
200
15
MT16D832MfG
4
200
15
MT24D836MfG
4
200
15
MT4D51232MfG
MT16D164G
4
3
5
200
150
400
12
16
5
400
12
12
200
12
MT12D136DMfDG
4
4
200
15
MT2D25632MfG
MT16LD(T) 164G
4
3
200
150
10
16
MT8LD(T)264G
3
150
16
MT16LD(T)464G
MT18LD(T) 172G
3
3
150
150
16
MT9LD(T)272G
3
150
16
16
MT18LD(T)472G
3
150
16
MT2D48M
MT3D49M
MT9D136MfG
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CSN-04
Aev.2195
10-5
Micron Technology, Inc., reselVes the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
I'IIIC:I=";~,~
SALES AND SERVICE INFOR~~~~~
CUSTOMER
SERVICE NOTE
ENVIRONMENTAL
PROGRAMS
INTRODUCTION
Micron Technology, Inc., takes a proactive approach to
environmental protection and worker safety. We believe
that this is not only environmentally responsible, but gives
the company a long-term competitive advantage. Environmental protection programs include educating the
workforce about chemical hazards, reduction in toxic chemical usage and air pollutants, recycling, and treating waste
water.
TOXIC CHEMICAL REDUCTION PROGRAM
This is an active program for continuous reduction of
EPA toxic chemicals and other chemicals determined to be
of some risk to employees or the environment. Through this
program, in 1992 Micron eliminated the use of hazardous
ethylene-based glycol ethers in manufacturing and replaced
anhydrous ammonia in storage tanks with a process that
uses aqueous caldurn hydroxide. rv1icron also elirninaied
ozone-depleting chemicals from the manufacturing process in 1992.
CHEMICAL AWARENESS AND
MONITORING
REDUCTION OF AIR POLLUTANTS
Micron has an ongoing program to reduce toxic air
pollutant emissions and is evaluating several different types
of pollution abatement methods for air emissions. Micron
has successfully reduced toxic air pollutant emissions and
fugitive volatile organic compound (VOCl emmisions by
90 percent. Reductions were made in the use of acetone,
toluene, methanol, and isopropyl alcohol. Use of methyl
ethyl ketone was completely eliminated.
The company successfully replaced its solvent-based
cleanroom cleaner with a water-based solution. Because
cleaning procedures were changed and existing wipes were
replaced with more absorbent ones, the water-based cleaner
proved to be more effective than the solvent-based cleaner
and has greatly reduced fugitive VOC emissions.
In converting from "puddle primers" to vapor primer
ovens in our photo process, Micron has reduced HMDS
usage by 90 percent. Micron has also installed high-efficiency purge pumps which exceed EPA specifications on
refrigeration units in order iu eliminate the discharge of
refrigerants into the atmosphere. In addition, portable refrigerant reclaim units are used to recover and recycle
refrigerants during maintenance or when equipment is
retired.
Micron educates and involves its workforce in eliminating hazardous and polluting chemicals and conditions.
Micron currently has several programs in place which
enable the company to minimize hazardous chemical use
while maintaining flexibility in processes and operations.
Examples of these programs include:
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ENVIRONMENTAL TASK FORCE
This internal task force meets weekly to review the effects
of process changes, new construction, and new equipment
on the environment and on worker safety. The group also
revIews regulations and compliance issues, and anticipates
possible impacts of potential regulation changes from legislation.
CHEMICAL APPROVAL SYSTEM
This approval and monitoring system insures that Micron remains in compliance with OSHA and EPA reporting
reqUIrements and tracks chemicals in use. Acting as a
gUidance and training resource, the Chemical Approval
Team gives direction and alternatives, rather than policing,
chemical use. This cooperative method of identifying hazardous chemicals, waste treatment needs and costs, and
safety procedures has proven very effective.
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CSN·05
Rev. 2195
10-6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron TechnOlogy, Inc.
1"I1C:1=:U;;~c~
SALES AND SERVICE INFOR~~?o~
WASTE WATER TREATMENT
Micron has completed the first phase of a three-phase
industrial waste water treatment facility. The system was
designed to remove fluoride from used process water and
allow the water to be reclaimed. By 1997 Micron will reclaim all of its waste water and reduce ground water use by
80 percent. Micron recently won a Water Conservation
Award from the Pacific Northwest Section of the American
Water Works Association for this project.
emissions, and a 53-ton cut in NOx emissions. The system
earned Micron a Certificate of Recognition for Energy Consciousness from the state of Idaho and an award 'for Energy
Innovation from the U. S. Department of Energy in 1991.
Micron is continually working toward reducing emissions through recycling of solvents. We work with suppliers and internally to incorporate chemical recycling systems into processes. Micron is currently redistilling acetone
and isopropyl alcohol on-site to repurify for reuse in the fab.
We are also reviewing methods to recycle resist edge remover and organic strip.
RECYCLING AND ENERGY
CONSERVATION
Several Micron teams have developed systems to recycle
items for sale to outside customers or reuse within the
manufacturing process. These items include sulfuric acid,
gold, various solvents and alcohols, scrap metal, wire,
aluminum and steel cans, buckets and barrels, pallets,
plastic, and cardboard and paper products.
In 1987 Micron engineers developed an alternate cooling
system, the Wet Side Economizer, which saves the company approximately $150,000 annually. The Wet Side Economizer uses cold air rather than refrigeration to cool the
manufacturing complex. The system reduces kWh consumption by 15.1 million, which translates into a 11,174-ton
reduction in CO 2 emissions, a 121-ton reduction in S02
COMMUNITY ASSISTANCE
Micron volunteers lab resources and provides consultation to local companies and community organizations, such
as the Peregrine Fund, to help resolve industrial hygiene
and environmental issues. Micron team members are active
in local environmental and safety organizations and in the
Community Emergency Planning (·ommittee. Team members periodically host training classl', (such as Hazardous
Gas Bottle Handling and Disposal) for local profcssional
organizations. Micron is also a member of tIll' Idaho Association of Commerce and Industry (lAC!) and is very ,,<"IiVI'
in the environmental committec.
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CSN-05
Rev. 2195
10-7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
1"'I1C:l=Ig,~
SALES AND SERVICE INFOR~~~?ts
ELECTRONIC DATA
INTERCHANGE
CUSTOMER
SERVICE NOTE
INTRODUCTION
VALUE ADDED NETWORKS
Electronic Data Interchange (ED!) has become an important data transmission element in today's marketplace.
Micron is ready to serve your EDI needs and encourages
customer participation.
AT&T
AT&T allows our partners to transmit EDI documents
via standard protocol or X.400 (e-mail protocol).
Advantis
Advantis is the result of a merger between the Sears and
IB1.1 netvvorks.
STANDARDS SUPPORTED
X.12
Micron supports versions 002000 through 003040 for all
implemented transaction sets. The addition of new versions
is an automated process which drives off of the standard
diskettes available through Data Interchange Standards
Associa tion.
TRANSMISSION TIMES
Transmission times are 2 a.m., 10 a.m., 1 p.m., 3 p.m.
and 8 p.m. MST weekdays and 1 p.m. MST on weekends.
Additional transmission times can be added easily as
circumstances warrant.
EDIFACT
Micron supports EDIFACT under the 90.1 EDIFICE guidelines (for the Purchase Order [PO], PO Acknowledgment,
PO Change and PO Change Acknowledgment messages)
and EDIFACT version 92.1 for all implemented messages.
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Inbound
850 -PO
860 - PO Change
840 -Request For Quote
(RFQ)
830 -Forecast
846 -Inventory Inquiry /
Advice
867 - Product Transfer &
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ORDCHG - PO Change
Request Message
DELFOR - Delivery
Schedule Message
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EDI Project Leader
Becka Shirrod
208-368-3338
TRANSACTION SETS
Resale
844 - Product Transfer
Account Adjustment
(PTAA)
997 - Functional
Acknowledgment
ORDERS - PO Message
C
MICRON EDI CONTACTS
CSN-06
Rev. 2195
EDI Software Development
Tony Holden
208-368-3855
STEPS TO IMPLEMENTATION
Outbound
855 - PO Acknowledgment
865 - PO Change
Acknowledgment
843 - Response to RFQ
The following are typical steps taken as Micron begins
exchanging EDI data with a new trading partner:
• Micron receives an implementation guide from a
trading partner
• Micron's EDI team contacts the trading partner's EDI
coordinator to set up a trading partnership and coordinate the transmission and receipt of test documents
• Micron receives a test EDI document from the
partner's VAN and responds with the necessary
acknowledgments
• Once both parties agree everything is working properly, parallel testing with EDI and paper documents
begins
• Micron insures an EDI agreement has been signed and
returned to the trading partner
• Paper documents are replaced with EDI documents
(full production).
856 - Advanced Ship Notice
810 - Invoice
832 - Price/Saies Catalog
849 - Response to PTAA
ORDRSP - PO Response
Message
INVOIC - Invoice Message
LEAD TIMES FOR FULL PRODUCTION
X.12
DESADV - Despatch
Advice Message
One Month
10-8
EDIFACT
Two Months
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology,lnc.
I"IICRgN
SALES AND SERVICE INFOR~~~~~
RETURNED MATERIAL
AUTHORIZATION (RMA)
PROCEDURES
CUSTOMER
SERVICE NOTE
HOW TO RETURN PRODUCT TO
MICRON
• Obtain an RMA number (see "How to Obtain an
RMA" below).
• Package product taking all antistatic precautions.
• Write RMA number on outside of box for proper
routing.
• Ship package prepaid to:
Micron Technology, Inc.
Attn.: RMA Area
2805 East Columbia Road
P.O. Box6
Boise, ID 83706-0006
• If RMA is being shipped from outside of the United
States, please note that Boise, Idaho, is a customs port
city; reference Port City Code 2907.
Provide the following information:
• Micron part number, including speed and package
• Type of failure
• Name of engineer who witnessed failure or requested
failure analysis report
• One of the following: PO number, invoice number, or
sales order number
• Preferred reimbursement method: replacement parts,
credit only, or refund.
FAILURE ANALYSIS STANDARDS FOR RETURNED
MATERIAL AUTHORIZATIONS:
• Upon receipt of an RMA for failure .111alysis, Micron's
Quality Assurance Department will provid,· an initi.11
response within 48 hours.
• Micron's Quality Assurance Department will issue a
completed failure analysis report within three weeks
of receiving an RMA.
HOW TO OBTAIN AN RMA
NONFAILURE-RELATED RETURNS:
• If you buy direct, contact your Micron sales representative at 208-368-3900.
• If you buy through a Micron sales representative,
contact that sales representative.
• If you buy through Distribution, contact the
distributor.
Provide the following information:
• Micron part number, including speed and package
• Reason for return
• One of the following: PO number, invoice number, or
sales order number
• Preferred reimbursement method: replacement parts,
credit only, or refund.
FAILURE-RELATED RETURNS AND/OR APPLICATION PROBLEMS:
• Contact Micron Application Engineering Department
at 208-368-3950.
CSN-07
Rev. 2/95
10-9
MICRON ACCOUNTING PROCEDURES
FOR RETURNED MATERIAL
AUTHORIZATIONS
II
• Replacements: Replacement parts are shipped after
receipt of the RMA parts. The credit memo will be
applied directly to the replacement invoice, unless a
tax is involved, in which case a credit memo will be
sent out along with an additional billing invoice. A
new invoice will be sent when the replacement
amount is greater than the returned amount. If this is
not compatible with your accounts payable procedures, please advise your sales representative upon
RMArequest.
• Credit: A credit memo is sent out for the amount of
the return upon arrival of the RMA parts. This credit
memo number should be referenced when sending in
payment information if intended to be used.
• Refund: A check request is submitted to Micron
Accounts Payable upon receipt of RMA parts. A
refund check is sent upon completion of the check
request approval process.
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Micron Technology, Inc., reserves the righllo change products or speciflcabons without notice.
©1995, Micron Technology. Inc.
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I'4ICI=U;;;!N
CUSTOMER
SERVICE NOTE
SALES AND SERVICE INFOR~~~~~
ISO 9001
CERTIFICATION
INTRODUCTION
Micron Technology, Inc., was certified to ISO 9001 in the
United States and Europe on February 1, 1994, by KEMA
Registered Quality, Inc. The certification is also recognized
by EQNET, the European Network for Quality System
Assessment and Certification. Through this network, our
KEMA certification is recognized by: AENOR Spain, AFAQ
France, AIB-Vincotte Belgium, BSI QA United Kingdom,
CISQItaly, DS Denmark, ELOT Greece, IPQ Portugal, NCS
Norway, NSAI Ireland, OQS Austria, SFS Finland, SIS
Sweden and SQS Switzerland.
ISO 9001 CERTIFICATION DEFINED
II1II
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ISO 9001 is one of a series of three international standards
dealing with quality systems that can be used for external
quality assurance purposes. It is a model for quality assurance in design/development, manufacturing, testing, installation and servicing. It is the most comprehensive level
of certification in the internationally recognized ISO 9000
family for quality assurance management systems.
ISO 9000 gives customers and suppliers a single set of
guidelines that are accepted worldwide and that can be
followed to achieve a definable level of quality. The certification implies that a company's systems for accepting
orders, reviewing customers' specifications, manufacturing and testing products, and delivering those products to
its customers are quality controlled and should produce
consistent results. A company seeking ISO certification
must be certified as ISO 9001 if it has complete control over
the design of its product with that control being a major
factor in ensuring delivered quality.
A supplier's ability to conform to the ISO 9001 standard
is assessed via the standard's Quality System Requirements-a set of twenty paragraphs each designed to address a specific portion of a quality system: management
responsibility; quality system; contract review; design control; document control; purchasing; purchaser supplied
product; product identification and traceability; process
control; inspection and testing; inspection measuring and
test equipment; inspection and test status; control of nonconforming product; corrective action; handling, storage,
packaging and delivery; quality records; internal quality
audits; training; servicing; and statistical techniques.
Micron's ISO 9001 certificate, number 93119, is valid until
February 1, 1997, at which time Micron must again complete the audit cycle.
In February, 1995, a surveillence audit will be performed
and Micron's certificate is expected to be renewed. At
this point the certificate will reflect the company's name
change (Micron Semiconductor, Inc. has become Micron
Technology, Inc.).
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CSN-08
Rev. 2195
10-10
Micron Technology, Inc., reserves the fight to change products or specifications without notice.
©1995,MlcronTechnology, Inc
MU::F=lCN
1-·
''''
SALES AND SERVICE INFORMATION
CSN-08
00.0000.000
elmel
MEMBER OF THE EUROPEAN NElWORK FOR QUALITY SYSTEM ASSESSMENT AND CERTIFICATION 'EQNET"
CERTI FICATE
Number: 93119
The quality system of:
MICRON SEMICONDUCTOR, INC.
BOISE, IDAHO
including the implementation meets the requirements of the standard:
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This certificate is valid until: February 1, 1997
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Issued for the first time: February 1, 1994'
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dr.ir. J.H. Blom
managing director
The method of operation for quality certification is defined in the KEMA Regulations for Quality System Certification.
Integral publication of this certificate and adjoining reports is allowed.
CSN-OS
Rev. 2195
N.V.KEMA
ACCEPTED BY THE
Utrechtseweg 310, Amhem, Postbus 9035, 6800 ET ARNHEM
Telephone +31 85 56 34 98 Telefax +31 85 45 88 25
DUTCH COUNCIL FOR \<,..=.,>./1..CERTIFICATION
10-11
Micron Technology, Inc., reserves the righ110 change products or speclflcations without notice.
@1995,MicrOnTechnology,lnc.
MICI=ION
1- •
",
SALES AND SERVICE INFORMATION
CSN-09
w
CUSTOMER
SERVICE NOTE
MICRON DATAFAX
INTRODUCTION'
HOW IT WORKS
Micron Technology, Inc., gives customers and potential
customers instant access to technical and sales information
via Micron DataFaxSM, a user-friendly, fax-on-demand system.
Micron DataFax allows. callers to make automated requests for data sheets, prody.ct literature and other product
information during and 'after regular business hours.
Micron DataFax improves'cugtomer support by offering
product information 24-hours-a-day, and shortens the sales
and design-in cycle by offering engineers the most up-todate product information.
Micron DataFax makes ordering product information
quick and easy using the touchtone keypad on your fax
machine. Here's how it works:
1. From your fax machine, call 208-368-5800.
2. Press 1 to order. When requested, enter document
number(s).*
3. The documents you ordered will be sent to the fax
machine you called from.
*An index of the documents available from Micron DataFax
can be found in the last section of this book. This index is
also available through the system itself and is updated
periodically. Follow the voice instructions to receive the
latest revision of the index.
I'IIICI=ION
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CSN.Q9
Rev. 2195
10-12
Micron Technology, Inc., reserves the right to change products or spedfications without nolice.
©1995, Micron Technology, Inc.
Micron DataFax is a service mark of Micron Technology, Inc.
I"IIC:I=II;~,~
CUSTOMER
SERVICE NOTE
SALES AND SERVICE INFORMts~~~
CUSTOMER
COMMENT LINE
INTRODUCTION
Micron Technology, Inc., is committed to achieving the
highest standard in customer satisfaction, and we believe
that giving our customers the opportunity to voice comments and complaints will help us discover ways to better
serve them. To achieve continuous improvement,
we need ongoing constructive customer feedback so we
know exactly what our customers expect and need.
COMMENT LINE INFORMATION
Micron's Comment Line is answered by Customer Service personnel from 8:00 a.m. to 5:00 p.m. MSTweekdays
and is transferred to voice mail during off hours, weekends,
and holidays. You may also fax your comments to us at any
time. Whether you have experienced a recent transaction
with Micron that requires immediate assistance, you want
to provide feedback, or need information on local represen-
tatives in your area, please call or fax. Direct your inquiry
to a customer satisfaction representative. We value your
input!
STANDARDS
At Micron, we are dedicated to serving our customers
and have set a 24-hour standard of returning all calls
received on the Customer Comment Line. If we can't solve
the matter at the time of your call, we will respond with an
update to your question or concern within 24 hours.
Customer Comment Line:
U.S.A. 800-932-4992
IntI. 01-208-368-3410
Fax 208-368-3342
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CSN-10
Rev. 2195
10-13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
PART MARKING
CUSTOMER
SERVICE NOTE
INTRODUCTION
Micron Technology, Inc., utilizes a standard part marking on each product as shown in Figure 1 below. The only
exceptions to this marking are for 32-lead and 52-lead EJ
products on which the pin one designator is assigned a
different location (see Figure 2).
PART lVIARKING INFORMATION
The part marking is right and left justified, and the
character size is a minimum of .035/maximum of .045
inches high. Each part marking contains the following
information: date code, revision letter (if relevant), country
Week Code ~
Year Code
~
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Each part is also laser-scribed with a unique identification number. This identification number was previously
located on the bottom side of the part only. We are currently
adding the laser inscription to the top side as well.* The
top-side inscription will allow for complete traceability of a
component even after soldered onto a printed circuit board.
r
Revision
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~*Country
~
•
Year Code
of
~
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Process Technology
t
~
11111
Pin One
Revision
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**Country of
Origin (Assm.)
c=J
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, - - - - - Device Number
Logo -
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jv1T
t
L Process Technology L
p;~~~~ 1I11111
Package Type
--------
I--....IIIIII
Speed
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, ' - - - - Device Number
TLI I I IIITlI
1
~
Product
Family
=-____- -..
~.
Origin (Assm.)
I'~
t
PinOne
Special Test
Options or Blanks
;
Speed
Figure 1
STANDARD PART MARKiNG
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LASER SCRIBE IDENTIFICATION
Week Code
•
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logo
of origin (assembly), Micron logo; product family, process
technology, device number, package type, pin one designator, speed and special test option (if relevant).
~
Package Type
Special Test
Options or Blanks
Figure 2
32-LEAD AND 52-LEAD EJ PRODUCTS
PART MARKING
* Exceptions: A top-side laser inscription will not be added to the ZIP package. Off-shore assembled products will not be
laser-scribed on the top side.
** May be blank if country of origin is printed on bottom of device.
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CSN·11
Rev, 2/95
10-14
Micron Technology, Inc., reserves the righllo change products or specifications without notice.
©1995, Micron Tachnology, Inc,
I"IIC:I="~N
SALES AND SERVICE INFOR~~~~~
CUSTOMER
SERVICE NOTE
PRODUCT CHANGE
NOTIFICATION (PCN)
SYSTEM
MICRON'S PCN SYSTEM
PCN LETTER DOCUMENTATION
Micron's automated Product Change Notification (PCN)
System provides notification to customers, per mutually
agreed upon requirements, of Micron product or production changes affecting form, fit or function.
PCN letters include the following information:
• PCNnumber
• a detailed description of the change
• a statement of the reason for the change
• supporting qualification data if appropriate
• a description of Micron product(s) affected by the
change
• a list of each Micron part number (along with the
corresponding customer number if available) purchased during the past 12 months or for which there is
current backlog.
CHANGES REQUIRING NOTIFICATION
Product and production
notification include:
• bonding wire
• data sheet
• die coat
• die redesign
• die shrink
• geographic location
• internal connections
• lead frame
• mark change
• mark ink
changes requiring customer
•
•
•
•
•
•
•
•
•
•
metalization
mold compound
package dimensions
packaging
passivation
plating material
plating process
product obsolescence
shipping tube
wafer material
•
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10-15
Micron Technology, Inc., reserves Ine right to change products or -specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
SALES AND SERVICE INFORMATION
PRODUCT NUMBERING
"'"""'''''"'
EXPANDED COMPONENT NUMBERING SYSTEM
AA BB CC DODD
I
FFF -GG
- L l..-1
ZZ ZZ
---.L....L-L
MT4C40010J-7
gE II I T-C:=
I
Processing Codes
70ns Access Time
SOJ Package
1 Meg x 4 _ _ _ _----.J.
AA - PRODUCT LINE IDENTIFIER
FFF - PACKAGE CODES
Micron Product ................................................................ MT
BB - PRODUCT FAMILY
DRAM .................................................................................. 4
SRAM .................................................................................. 5
CC - PROCESS TECHNOLOGY
CMOS .................................................................................. C
Low Voltage CMOS ............................................................ LC
DODD - DEVICE NUMBER
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(Can be modified to indicate variations)
DRAM ............................................................. Width, Density
TPDRAM ......................................................... Width, Density
SRAM .......................................................... Total Bits, Width
Synchronous SRAM ....................................... Density, Width
E - DEVICE VERSIONS
l>
(Alphabetic characters only; located between D and Fwhen
required.)
m
JEDEC Test Mode (4 Meg DRAM) ....................................... J
Errata on Base Part .............................................................. 0
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PLASTIC
DIP ............................................................................ Blank
DIP (Wide Body) .............................................................. W
ZiP .................................................................................... Z
LCC ................................................................................. EJ
SOP/SOIC ...................................................................... SG
OFP ................................................................................. LG
TSOP (Type I) ................................................................ VG
TSOP (Type I, Reversed) ............................................... XG
TSOP (Type II) ................................................................ TG
TSOP (Reversed) ........................................................... RG
TSOP (Longer) ............................................................... TL
SOJ ................................................................................. OJ
SOJ (Reversed) ............................................................. OR
SOJ (Longer) .................................................................. OL
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SALES AND SERVICE INFORMATION
Rev. 2195
10-16
Micron Technology, Inc., reserves the right to change products or spec~ications without notice
©1995, Micron Technology. Inc
MICRON
,-.
SALES AND SERVICE INFORMATION
PRODUCT NUMBERING
'''"'ow",,,,,
EXPANDED COMPONENT NUMBERING SYSTEM (continued)
AA BB CC DDDD
-L-L~
I
fFF -GG
ZZZZ
---L-L --L
MT 4C4001 DJ-7
C~M~AOroMSn ITT
I
TT,--_~__ ~~~~e~~~negs~~::
-
SOJ Package
1 Meg x 4 - - - - - - - - '
DRAMs
Low Power (Extended Refresh) ........................................ L
Low Power (Self Refresh/Extended Refresh) .................... S
SRAMs
Low Volt Data Retention ................................................... L
Low Power .............................................
.. P
Low Power, Low Volt Data Retention .......................... LP
EPI Wafer ........................................................................... E
Operating Temperature Range
DOC to +70°C ............................................................. Blank
-40°C to +S5°C ................................................................ IT
-40°C to +125°C ............................................................. AT
-55°C to +125°C ............................................................. XT
Special Processing
Engineering Sample ........................................................ ES
Mechanical Sample ....................................................... MS
Sample Kit' .................................................................... SK
Tape-and-Reel* .............................................................. TR
Bar Code* .................................. ,.................................... BC
3G - ACCESS TIME
-5 ...................................................................... 5ns or 50ns
-6 ....................................................................... 6ns or 60ns
-7 ...................................................................... 7ns or 70ns
-S ...................................................................... 8ns or SOns
-10 .................................................................. 10ns or 100ns
-12 .................................................................. 12ns or 120ns
-15 .................................................................. 15ns or 150ns
-17 ................................................................................. 17ns
~
................................................................................. w~
-25 ................................................................................. 25ns
~ ................................................................................. ~~
-45 ................................................................................. 45ns
-53 ................................................................................. 53ns
-55 ................................................................................. 55ns
zz ZZ -
PROCESSING CODES
(Multiple processing codes are separated by a space and are
listed in hierarchical order.)
Example:
A DRAM supporting low power, extended refresh (L); low voltage
(V) and the industrial temperature range (IT) would be indicated as
V LIT.
*Used in device order codes; this code is not marked on device.
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Interim .................................................................................. I
Low Voltage ......................................................................... V
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SALES AND SERVICE INFORMATION
Rev. 2/95
10-17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
SALES AND SERVICE INFORMATION
PRODUCT NUMBERING
","'W"""
NEW COMPONENT NUMBERING SYSTEM
AA 88 CC DDDDDD
I
- L 1. 1.
Micron
DRAM
CMOS
1 Meg x 16
TJ
EE
FFF -GG ZZ ZZ
1TT
.....L.....L..L---L
MT4C1M16A1DJ-8 VL
I
~
-
I
-
ivi " .......... ', .. ,."."' ... ,...... ".,"'''" ....... ,'',, .... ,", .. ,""'" .. Megabits
G"" ... " ....... "." .... ,.. ,..... ,.,""""'" ..... ".,," .. ,", .... ,"'" ... Gigabits
Flash """"""""."."""""""""""."".". Density, Configuration
AA - PRODUCT LINE iDENTiFiER
Micron Product """".""" ..... ""., ... ,,",.,,.,,"", ... ,,""", ... ,'" MT
BB - PRODUCT FAMILY
EE - DEVICE VERSIONS
Flash (Dual Supply) " .. """" .. """ .... """ ..... "."" .. ,,",, .. ,,.,," 28
(The first character is an alphabetic character only; the
second character is a numeric character only,)
Specified by individual data sheet
DMM ... "., ....... "... ,"', .... ,""', ... ,""", ... ,."", ..... ,"',.,',., .... ,..... 4
SGRAM "" ..... ,", ..... ,", ....... "', ..... ,"', ......... ,"",, .. "" ... ,"""." 41
Synchronous DRAM ",.""""" .. """ ... ,,""""""",, .. ,,"""",,. 48
SRAM .""" .. """"".,.,.,,,,,,,., .. ,,,,,,,,,.,,,,,,.,.,,,,,,,, ... ,,.,,,,,,,.,,,, .. 5
Synchronous SRAM """"" ... """ .. "."""" .. "",, .... """,,,,"" 58
FFF - PACKAGE CODES
CC - PROCESS TECHNOLOGY
-
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Low Voltage, L?w Power (Extended Refresh)
70ns Access Time
SOJ Package
Data Sheet Defined
CMOS """""'"."'" .. ,.. "', ....... ,"", .. ,."", .. ,,," .. ,,",,.", .......... ,.. C
Low Voltage CMOS "." ...... ""." .. """ ........ "" .... """ ... ,,",,.,, LC
~M~",., .•• ,., ••••• " " ' ••.• " " " ' •.• " " " ' ••• " " " , •••• , " " ' , . , " " " , . " " " B
Low Voltage BiCMOS .... """" .. """" ..... "",,.,,"",, .. ,,""',, ... LB
Flash CMOS """.".""""""""""""." .. """"""",,.,,.,,"""""" F
Low Voltage Flash CMOS .... "." .... """ .... "" ... "."".,,",,",, .. LF
AP Flash CMOS " ....... " ............... " ... "."." .... " .... "" ...... " .. " AF
DDDDDD - DEVICE NUMBER
Depth, Width
Example:
1M16 = 1 megabit deep by 16 bits wide = 16 megabits of total
memory.
Plastic
DIP " ..... ,." .... ,"' ..... ", ... ,""", ..... ,"", ........ " ........... ,..... Blank
DIP (Wide Body) ........................................................."". W
ZiP .......... ,........ ,.......... ,..................................................... Z
LCC ................................................................................. EJ
SOP/SOIC .............................................. ,...................... , SG
QFP ................................................................................. LG
TSOP (Type II) ............................................................,," TG
TSOP (Reversed) ......................................................"". RG
TSOP (Longer) ...........................................................,," TL
SOJ ................................................................................. OJ
SOJ (Wide) ................................................................... OW
SOJ (Reversed) ........................................................"". DR
SOJ (Longer) .................................................................. DL
No Letter "',., ... ",.,'" .. ", ....... ", .... " .. ,., ....... ,......... ,....... ,"" Bits
K .. ,,,.,",, .. ,"', .... ,",, ..... ,, ...... ,",, ...... ,,, ....... ,""",.,.,, ..... ,' Kilobits
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SALES AND SERVICE INFORMATION
Rev. 2195
10-18
Micron Technology, Inc., reserves the right to change products or specifications without nollce
©1995, Micron Technology, Inc
MICRON
1-·
SALES AND SERVICE INFORMATION
PRODUCT NUMBERING
'''"'0''''''
NEW COMPONENT NUMBERING SYSTEM (continued)
AA BB CC DDDDDD EE FFF -GG ZZ ZZ
I
-L -L.-L ---L..
.-L 1. 1.
TJ
11T
MT4C1M16A1DJ .. 8 VL
I
I
~
Micron
DRAM
CMOS
1 Meg x 16
-
_
-
DRAMs
Low Power (Extended Refresh) ..... " ................................. L
Low Power (Self Refresh/Extended Refresh) .................... S
SRAMs
Low Volt Data Retention .................................................. , L
Low Power ......................................... ,
............ P
Low Volt Data Retention, Low Power ............... , , ....... , LP
Flash
3.3V Read (AP) .............................. , ....................... , .,. V
Bottom Boot Block .... '.................................................. , B
Top Boot Block .............................................................. ,' T
EPI Wafer """,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, E
Commercial Testing
O°C to +70°C """"""""""""""'"'''''''''''''''''''''''''''''' Blank
-40°C to +85°C ................................, .................... , IT
-40°C to +125°C ............................................................ ' AT
-55°C to +125°C ............................................................. XT
Special Processing
Engineering Sample ........................................................ ES
Mechanical Sample ....................................................... MS
Sample Kit* .............................................." .................... SK
Tape-and-Reel* ... ,........... ," ........ ,', ..... ,............. " ..... " ... " TR
Bar Code* ""'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' BC
GG - ACCESS TIME
-5 ...................................................................... 5ns or 50ns
-6 ...................................................................... 6ns or 60ns
-7 ...................................................................... 7ns or 70ns
-8 .................. ,"",.,"',.,', .. ' ... ,"",.".,'""""'.,""'" 8ns or 80ns
-9 ...................................................................... 9ns or 90ns
-10 .................................................................. iOns or 100ns
-12 .................................................................. 12ns or 120ns
-15 .................................................................. 15ns or 150ns
-17 .............................................................. ,.................. 17ns
-20 ""'" .. ,"'" ........ ,', ........ ,..... ,"",.,"', ..... ,"',, ..... ,....... ,', .. 20ns
-25 ,"', .. ,,", ................... ,',.,', ... " ............. ,"', .... ," ...... ,',', .. 25ns
-35 """'"'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' 35ns
-45 "'"''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''.. ,", ...... ,' 45ns
-53 "'" .. ,.. "'" ....... ,", .... ,"" ...... """"'" ...... '" ...... " ........ ,'" 53ns
~
.. "." ..... , ...
zz ZZ -
"""
..
"""""""""""""'""""""
.......
"""
Low Voltage, Low Power (Extended Refresh)
70ns Access Time
SOJ Package
Data Sheet Defined
... ,.~~
PROCESSING CODES
(Multiple processing codes are separated by a space and are
listed in hierarchical ordeL)
Example:
A DRAM supporting low power, extended refresh (L); low voltage
(V) and the industrial temperature range (IT) would be indicated as
V LIT.
Interim """""""'"'''''''''''''''''''''''''''''''''''''''''''''''''' .... ,"""', .. I
Low Voltage " ...... "" ... " .. " .... ,.. " .. ,.. ,........ "", .. "", ....... """, ... V
* Used in device order codes; this code is not marked on device.
III
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SALES AND SERVICE INFORMATION
Rev. 2195
10-19
Micron Technology, Inc., reserves the right to change products or Specifications without notice.
©1995, Micron Technology, inc.
UII::::I=ICN
1-'
SALES AND SERVICE INFORMATION
PRODUCT NUMBERING
"'""'"''''
MODULE NUMBERING SYSTEM
AA
BB CDDDEEEFFF GG HH JJ KK
-=r-2rfj
- L -L L L --1--L--..L -L --L --L
MT12LD136xxG-7 L
Micron
12 Components
3,3 Volt
DRAM Module
1 Meg
T~L-
DRAM Low Power
70ns Access Time
Gold Plating
Device Version
' - - - - - - - x36
~
JJ - ACCESS iiiviE
AA - PRODUCT L!NE !DENTIFIER
Micron Product """""""""""",,,,"",,,,"",,,,",,",,",,"""" MT
-10 ............ ,.... "" .... "" .. """"""""""""" .. "" .. " .. """,, .. ,,
-12 """""""""""""'""" " " " " "" " "" .. " " " .. " ...... "" ........
-15 """"""""""'"'''''''''''' .. ",." .. "" .... " ...... "" .. " ...... " ....
-17 """" ...... " .... " ............. " .... "." .. """""""".",, .. ,,""""
-20 ,.,", .. "." ... """ .. ,"""""",.,''',.,''''" ... ,'''''".".,,.,", .... ,"
-25 "''',.,'' """" "', .. ,"',.,,''', .. ,''', ... ,'',., .. ,,',., .. """ .. ,, ...... ,..
-35 ""'" """ .. ,"""""', .. ,"", .. ,', ..... ,", ... "., ..... " ...... ,....... ',.
~"""'." ...... "" .... "" .... " ...... ,.............. ,........... ,.. " .... "" ...
-7 ..... ,.. ,', ..................... '" .... ,..... ,', ... ,", .... ,"" .. " ..... ""',,.,'
-8 ... ,"', .... ,",. """"" """""" .. ,,"',.,"", .. ,"", .. ,", .... ,"', .. ,,"
BB - NUMBER OF MEMORY COMPONENTS
C - PROCESS TECHNOLOGY
LOW VOLTAGE (3,3V) """""""""""""""""""""""""""", L
DDD - RAM FAMILY
DRAM """""""""""""""""'"''''''''''''''''''''''''''''''''"""""",0
DRAM TSOP "'" " " "" " " """ """ " " " " " " " " " " " """ " """ " " , DT
SRAM """"""""""""""""'''''''''',''''''''''''''',,'''''', ........ ,"'''' S
SRAM TSOP ...... "", .. "" .... ""'" .... """",, .. ,,",, ...... ,,",, ........ ST
SYNGHRONOUS SRAM .... "" .... """""" .... """,, .... ,,",, .. ,,'" SY
SYNGHRONOUS SRAM TQFP .. " .. ,"""""" .. """" .. ,,",, .... , SYT
III
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6~s
70ns
80ns
KK - MODULE SPECIAL DESIGNATOR
EEE- DEPTH
FFF-WIDTH
en GG - DEVICE VERSIONS
l> Specified by individual data sheet (Synchronous SRAM only)
r - PACKAGE CODE
m HH Gold
Plated SIMM/DIMM """ .... "" .............. " .... "" .... "" .... " G
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1Ons
12ns
15ns
17ns
20ns
25ns
35ns
~P"""""""""""""""""""""""""" """"""""""""""""",z
SRAM
2V data retention """"""""""""" ... """ .. "" .... "" .... " ..... ,, L
Low Power "",.,"""""', ... ,', .. ,.. ,', ..... ,', ..... ', .... ,.,,, .... ,, ..... ". P
Low Power, 2V data retention ."" .... " ............................. LP
DRAM
Low Power (Extended Refresh) """""""""""."""."."".,, L
EGG, .... ,"""""',., .. ".,"", .. "." ... " ....... ,", .... ", ..... ,", .... "., ..... G
Extended Data Out ........... " .................................... ""."" .. X
Self Refresh .. " ...... " ..... "" .. """""."".""".,,"",,.,,""""",,. S
16 Meg DRAM 4,096 Refresh """""""""""""""""""" .. ' A
SIP ...................................................................................... N
SIMM/DIMM """"', .... ,""""'"""","""",,, .. ,,',",, .. ,,"",','"", M
Small Outline DIMM " ............ " .... "" .. " ........ " ...... " .... "" ...... H
Small Outline Gold DIMM .......... "" ...... " ...... " .... "" .... "" .. , HG
Double-Sided SIMM (1 or 4 Meg x 36 Only) ...... ", .... "" .. OM
Double-Sided SIMM (Gold 1 or 4 Meg x 36 Only) .. " ........ DG
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SALES AND SERVICE INFORMATION
Rev. 2195
10-20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc,
MICRON
1-·
SALES AND SERVICE INFORMATION
PRODUCT NUMBERING
"'","co",,",
DRAM CARD NUMBERING SYSTEM
AA BB
-L.l
ecce
I
DDD EE
FF -G H
.l.-L --.L...L.l
MT8D88C132VH-8S
---=:r-T
IT~"""L
~
I
Micron
8 Components
88-Pin DRAM Card - - - - - ' .
1 Meg - - - - - - - - - '
Special Designator
80ns Access Time
Special Designator
x32
G - ACCESS TIME
-5 .. ,,""', .. ,,", ...... ,', .. ,""',", ...... ,,"""',', .. ,"'"", .. " .... ""', .. 50ns
-6 ,', .... ,"," .. ,""" .... ,"""""""""', ...... ,", .. " .. ,, .. " .. " .. ", .. ," 60ns
AA - Product Line Identifier
Micron Product """"" .. ,"""' ...... ""' .... ,""" .. ,', .. ," .. ,', ...... , MT
BB - NUMBER OF MEMORY COMPONENTS
~"""""""""""""""""""""""""'" """""""""""""""ro~
-8 ", ...... ,", .... ,"", .. ,.. ,"", .. ",""",""""',',,', .. ""'"'''''''''''' 80ns
CCCC - DRAM CARD DESIGNATOR AND PIN COUNT
88-Pin DRAM Card ......................................................, D88C
H- SPECIAL DESIGNATOR
Self Refresh ...... ,.................... ,........ , .. , .... ,.. , , ,
DDD-DEPTH
", .. ,' S
EE-WIDTH
FF - SPECIAL DESIGNATOR
3,3 Volts ...................................................... ,...................... , V
Reduced length (2") .................................. ,.............. ,.......... , H
•
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SALES AND SERVICE INFORMATION
Rev. 2195
10-21
Micron Technology, Inc., reserves the right to change products or specifications'without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
SALES AND SERVICE INFORMATION
PRODUCT NUMBERING
"'~"''''''''
DIE PRODUCT NUMBERING SYSTEM
AA BBCC 000000
-L_Ll
g:~
EEEE
I
F GG -HH
I...L-L ...L
MT4C4001..J D30ADC2-7
I
IT
I
1T ~
I
1 Meg x 4 - - - - - - - - - - ' .
.
AA - PRODUCT LINE IDENTIFIER
EEEE - DIE DATA BASE REVISION
Component Product ......................................................... MT
F-FORM
Die Form .............................................................................. D
Wafer Form (6" Wafer) ....................................................... W
BB - PRODUCT FAMILY
SRAM .................................................................................. 5
DRAM .................................................................................. 4
Synchronous SRAM .......................................................... 58
GG - TESTING LEVELS
Standard Probe (0° to lO°C) ............................................. C1
Hot Speed Probe (0° to lO°C) ........................................... C2
Known Good Die (0° to lO°C) ........................................... C3
KGDPlus® ............................................................................ Cl
CC - PROCESS TECHNOLOGY
CMOS .................................................................................. C
Low Voltage CMOS ............................................................ LC
DDDDDD - DEVICE NUMBER
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70ns Access Time
Hot Speed Probe
Die Form (individual)
D30A Die Data Base
HH - ACCESS TIME
When no alpha character appears as part of this section, the
section is defined as:
DRAM ............................................................. Width, Density
SRAM .......................................................... Total Bits, Width
Synchronous SRAM ......................................... Depth, Width
(Applicable for C2 and C3 only)
-5 ............................................................. 5ns or 50ns
-6 ............................................................. 6ns or 60ns
-7 ............................................................. 7ns or 70ns
-8 ............................................................. 8ns or 80ns
-9 ............................................................. 9ns or 90ns
-10 ........................................................ 10ns or 100ns
-12 ........................................................ 12ns or 120ns
-15 ........................................................ 15ns or 150ns
-17 ....................................................................... 17ns
-20 ....................................................................... 20ns
-25 ....................................................................... 25ns
-35 ....................................................................... 35ns
-45 ....................................................................... 45ns
-50 (SRAM only) .................................................. 50ns
-88 (C2 only) .......................................... speed sorted
When an alpha character occurs as part of this section, the
section is defined as:
Depth, Width
Example:
lM16. 1 megabit deep by 16 bits wide. 16 megabits of total
memory.
No Letter ......................................................................... Bits
K................................................................................ Kilobits
M ............................................................................. Megabits
G............................................................................... Gigabits
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*For more detailed information, refer to the product numbering charts on pages 10-16 through 10-22.
SALES AND SERVICE INFORMATION
Rov.2195
10-23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
ALABAMA
Representative
Southeast Technical Group
101 Washington, Suite 6
Huntsville, AL 35801
Phone -205-534-2376
Fax -205-534-2384
Distributors
Anthem Electronics Incorporated
4920 H, Corporate Drive
Huntsville, AL 35805
Phone - 205-890-0302
Phone - 800-359-3531
Fax -205-890-0130
Hamilton Hallmark
4890 University Square, Suite 1
Huntsville, AL 35816
Phone -205-837-8700
Phone - 800-572-7236
Fax -205-830-2565
Wyle Laboratories
Tower Building, 2nd Floor
7800 Governers Drive West
Huntsville, AL 35807
Phone - 205-830-1119
Fax -205-830-1520
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Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax -407-290-0164
r
ARIZONA
»
m Representative
Associates
en Quatra
4645 South Lakeshore Drive, Suite 1
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SALES AND SERVICE INFORMATION
NORTH AMERICA
'"«mc",,
Tempe, AZ 85282
Phone - 602-820-7050
Fax -602-820-7054
Distributors
Anthem Electronics Incorporated
1555 10th Place, Suite 101
Tempe, AZ 85281
Phone - 602-966-6600
Fax -602-966-4826
Hamilton Hallmark
4637 South 36th Place
Phoenix, AZ 85040
Phone - 602-437-1200
Phone - 800-352-8489
Fax - 602-437-2348
SALES AND SERVICE INFORMATION
Rev. 2195
Wyle Laboratories
4141 E. Raymond Street, Suite 1
Phoenix, AZ 85040
Phone - 602-437-2088
Fax - 602-437-2124
Bay Area Electronic Sales, Inc.
9119 Eden Oak Circle
Loomis, CA 95650
Phone - 916-652-6777
Fax - 916-652-5678
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
Sales Offices.(Southern California)
Micron Sales California, Inc.
10573 W. Pico Blvd. #199
Los Angeles, CA 90064
Los Angeles County
Phone - 714-586-9977
Fax - 714-586-9656
ARKANSAS
Representative
Nova Marketing Incorporated
8350 Meadow Road, Suite 174
Dallas, TX 75231
Phone - 214-265-4600
Fax - 214-265-4668
Orange County
Phone - 310-446-1647
Fax - 310-446-1507
Distributors
Anthem Electronics Incorporated
651 N. Plano Road, Suite 401
Richardson, TX 75081
Phone - 214-238-7100
Fax - 214-238-0237
San Fernando Valley
Phone - 805-681-0136
Fax - 805-681-0146
San Diego
Phone - 619-452-2042
Fax - 619-452-1683
Distributors
Anthem Electronics Incorporated
1160 Ridder Park Drive
San Jose, CA 95131
Phone -408-453-1200
Fax -408-441-4500
Hamilton Hallmark
7079 University Blvd.
Winter Park, FL 32792
Phone - 407-657-3300
Fax -407-678-4414
Anthem Electronics Incorporated
9131 Oakdale Avenue
Chatsworth, CA 91311
Phone - 818-700-1000
Fax - 818-775-1302
Wyle Laboratories
1810 N. Greenville Avenue
Richardson, TX 75081
Phone - 214- 235-9953
Fax - 214-644-5064
Anthem Electronics Incorporated
1 Old Field Drive
East Irvine, CA 92718-2809
Phone -714-768-4444
Fax -714-768-6456
Die Distributor
ChiuSlluulv
7725 N:Or~nge Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
CALIFORNIA
Representatives (Northern California)
Bay Area Electronic Sales, Inc.
2001 Gateway Place, Suite 315 W
San Jose, CA 95110
Phone -408-452-8133
Fax -408-452-8139
10-24
Anthem Electronics Incorporated
580 Menlo Drive, Suite 8
Rocklin, CA 95677
Phone - 916-624-9744
Fax - 916-624-9750
Anthem Electronics Incorporated
9369 Carroll Park Drive
San Diego, CA 92121
Phone - 619-453-9005
Fax - 619-546-7893
Micron Technology, Inc., reserveslhe right to change products or speclfJcations without notice
©1995, Micron Technology, Inc
MICRON
1-·
Hamilton Hallmark
3170 Pullman Street
Costa Mesa, CA 92626
Phone -714-641-4100
Fax - 714-641-4122
Hamilton Hallmark
580 Menlo Drive, Suite 2
Rocklin, CA 95765
Phone - 916-624-9781
Fax - 916-961-0922
Hamilton Hallmark
4545 Viewridge Avenue
San Diego, CA 92123
Phone - 619-571-7540
Fax - 619-277-6136
Hamilton Hallmark
2105 Lundy Avenue
San Jose, CA 95131-1849
Phone -408-435-3500
Fax - 408-435-3535
Hamilton Hallmark
21150 Califa Street
Woodland Hills, CA 91367
Phone - 818-594-0404
Fax - 818-594-8234
Wyle Laboratories
3000 Bowers Avenue
Santa Clara, CA 95051
Phone -408-727-2500
Fax - 408-988-3479
Wyle Laboratories
29A Technology Drive, Suite 100
Irvine, CA 92718
Phone - 714-789-9953
Fax -714-789-9961
Wyle Laboratories
2951 Sunrise Blvd., Suite 175
Rancho Cordova, CA 95742
Phone - 916-638-5282
Fax - 916-638-1491
Wyle Laboratories
9525 Chesapeake Drive
San Diego, CA 92123
Phone - 619-565-9171
Fax - 619-565-0512
Wyle Laboratories
26010 Mureau Road, Suite 150
Calabasas, CA 91302
Phone - 818-880-9000
Fax - 818-880-5510
SALES AND SERVICE INFORMATION
Rev,2195
SALES AND SERVICE INFORMATION
NORTH AMERICA
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Hamilton Hallmark
Suite 600 7575 Transcanada Hwy.
Ville St. Laurent, Quebec H4T IV6
Phone - 514-335-1000
Fax - 514-335-2481
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
CANADA
Sales Office
B.C., Alberta, Saskatchewan
Micron Sales Northwest, Inc.
P.O. Box 902
Woodinville, WA 98072-0902
Phone - 206-486-2775
Fax - 206-486-3960
COLORADO
Representatives
Manitoba, Ontario, Quebec, New Brunswick,
Nova Scotia
Clark-Hurman Associates
20 Regan Road, Unit 14
Brampton, Ontario L7A 1C3
Phone - 905-840-6066
Fax - 905-840-6091
Clark-Hurman Associates
308 Palladium Drive, Suite 200
Kanata, Ontario K2B lAI
Phone - 613-599-5626
Fax - 613-599-5707
Clark-Hurman Associates
78 Donegani, Suite 200
Pointe Claire, Quebec H9R2V4
Phone - 514-426-0453
Fax - 514-426-0455
Distributors
Hamilton Hallmark
8610 Commerce Court
Burnaby, BC V5A 4N6
Phone - 604-420-4101
Fax - 604-420-5376
Hamilton Hallmark
151 Superior Blvd., Unit 1-6
Mississauga, Ontario L5T 2L1
Phone - 905-564-6060
Fax - 905-564-6033
Hamilton Hallmark
190 Colonnade Road
Nepean, Ontario K2E 7)5
Phone - 613-226-1700
Fax - 613-226-1184
10-25
Representative
Wescom Marketing
4860 Ward Road
Wheatridge, CO 80033
Phone - 303-422-8957
Fax - 303-422-9892
Distributors
Anthem Electronics InCllrporat('d
373 Inverness Drive
Englewood, CO 80112
Phone - 303-790-4500
Fax - 303-790-4532
Hamilton Hallmark
12503 E. Euclid Drive, Suite 20
Englewood, CO 80111
Phone - 303-790-1662
Fax - 303-790-4991
Wyle Laboratories
451 E. 124th Street
Thornton, CO 80241
Phone -303-457-9953
Fax - 303-457-4831
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
CONNECTICUT
Representative
Advanced Tech Sales Incorporated
Westview Office Park
Building 2, Suite 1C
850 N. Main Street Extension
Wallingford, CT 06492
Phone - 508-664-0888
Fax - 508-664-5503
Micron Technology, Inc., reserves the right to change products or specifications withOlJI notice.
©1995, Micron Technology, Inc.
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Distributors
Anthem Electronics Incorporated
61 Mattatuck Heights
Waterbury, CT 06705
Phone - 203-575-1575
Fax - 203-596-3232
Distributors
Anthem Electronics Incorporated
7168 A Columbia Gateway Drive
Columbia, MD 21046-2101
Phone - 301-995-6640
Fax - 301-381-4379
Hamilton Hallmark
10491 72nd Street North
Largo, FL 34647
Phone - 813-541-7440
Phone - 800-282-9350
Fax - 813-544-4394
Hamilton Hallmark
125 Commerce Court, Unit 6
Cheshire, CT 06410
Phone - 203-271-2844
Fax - 203-272-1704
Hamilton Hallmark
10240 Old Columbia Road
Columbia, MD 21046
Phone - 410-988-9800
Fax - 410-381-2036
Hamilton Hallmark
7079 University Blvd.
Winter Park, FL 32792
Phone -407-657-3300
Fax - 407-678-4414
Wyle Laboratories
20 Chapin Road, Bldg. 1013
Pinebrook, NJ 07058
Phone - 201-882-8358
Phone - 800-862-9953
Fax - 201-882-9109
Wyle Laboratories
9101 Guilford Road, Suite 120
Columbia, MD 21046
Phone - 301-490-2170
Fax -301-490-2190
Wyle Laboratories
1000 112th Circle North, Suite 800
SI. Petersburg, FL 33716
Phone - 813-576-3004
Fax - 813-579-1518
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
Wyle Laboratories
600 W. Hillsboro Blvd., Suite 300
Deerfield Beach. FL 33441
Phone - 305-420-0500
Fax - 305-428-2134
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax -407-290-0164
DELAWARE
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Omega Electronic Sales Inc.
Four Neshaminy Interplex, Suite 101
Trevose, PA 19053
Phone - 215-244-4000
Fax·215-244-4104
Distributor
Wyle Laboratories
815 Eastgate Drive
MI. Laurel, NJ 08054
Phone - 609-439-911 0
Fax -609-439-9020
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax -407-290-0164
m DISTRICT OF COLUMBIA
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NORTH AMERICA
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Representative
Electronic Engineering &Sales, Inc.
305 Kramer Road
Pasadena, MD 21122
Phone - 410-255-9686
Fax -410-255-9688
SALES AND SERVICE INFORMATION
Rev.2f95
FLORIDA
Representatives
Photon Sales, Inc.
1600 Sarno Road, Suite 21
Melbourne, FL 32935
Phone - 407-259-8999
Fax -407-259-1323
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax -407-290-0164
GEORGIA
Photon Sales, Inc.
715 Florida Street
Orlando, FL 32806
Phone - 407-841-7423
Fax -407-843-1505
Representative
Southeast Technical Group
3500 Parkway Lane, Suite 420
Norcross, GA 30092
Phone - 404-416-6336
Fax - 404-416-6433
Distributors
Anthem Electronics Incorporated
598 S. Northlake Blvd., Suite 1024
Altamonte Springs, FL 32701
Phone - 407-831-0007
Fax - 407-831-6990
Distributors
Anthem Electronics Incorporated
3305 Breckenridge, Suite 108
Duluth, GA 30136
Phone -404-931-3900
Fax - 404-931-3902
Anthem Electronics Incorporated
5200 N.w. 33rd Avenue, Suite 206
Ft. Lauderdale, FL 33309
Phone - 305-484-0990
Fax - 305-484-0951
Hamilton Hallmark
3425 Corporate Way, Suite A and G
Duluth, GA 30136-2552
Phone - 404-623-4400
Fax - 404-476-8806
Hamilton Hallmark
3350 NW 53rd Street, Suite 105-107
Ft. Lauderdale, FL 33309
Phone - 305-484-5482
Fax - 305-484-2995
Wyle Laboratories
6025 The Corners Pkwy, Suite 111
Norcross, GA 30092
Phone -404-441-9045
Fax -404-441-9086
10-26
Micron Technology, Inc., reserves the right to change products or specifications WIthout notice
©1995, Micron Technology. Inc
MICRON
1-·
SALES AND SERVICE INFORMATION
NORTH AMERICA
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Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
Distributors
Anthem Electronics Incorporated
1279 West 2200 South
Salt Lake City, UT 84119
Phone - 801-973-8555
Fax - 801-973-8909
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
HAWAII
Hamilton Hallmark
2105 Lundy Avenue
Sanjose,CA 95131-1849
Phone - 408-435-3500
Fax - 408-435-3535
INDIANA
Representatives
Bay Area Electronics Sales, Inc.
2001 Gateway Place, Suite 315
San jose, CA 95110
Phone - 408-452-8133
Fax -408-452-8139
Bay Area ElectronicsSales, Inc.
571l Reinhold Street
Fair Oaks, CA 95628
Phone - 916-863-0563
Fax - 916-863-0615
Distributors
Anthem Electronics Incorporated
1160 Ridder Park Drive
San jose, CA 95131
Phone - 408-453-1200
Fax - 408-441-4500
Wyle Laboratories
1325 West 2200 South, Suite E
Salt Lake City, UT 84119
Phone - 801-974-9953
Fax - 801-972-2524
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
ILLINOIS
Hamilton Hallmark
2105 Lundy Avenue
San jose, CA 95131-1849
Phone - 408-435-3500
Fax - 408-435-3535
Representatives
Advanced Technical Sales (S. IL)
13755 St. Charles Rock Road
Bridgeton, MO 63044
Phone - 314-291-5003
Fax - 314-291-7958
Wyle Laboratories
3000 Bowers Avenue
Santa Clara, CA 95051
Phone - 408-727-2500
Fax -408-988-3479
Industrial Representatives, Inc. (N. IL)
8430 Gross Point Road
Skokie, IL 60077
Phone - 708-967-8430
Fax - 708-967-5903
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-71 00
Fax - 407-290-0164
Distributors
Anthem Electronics Incorporated
1300 Remington, Suite A
Schaumburg, IL 60173
Phone - 708-884-0200
Fax -708-884-0480
IDAHO
Hamilton Hallmark
1130 Thorndale Avenue
Bensenville, IL 60106
Phone - 708-860-7780
Fax - 708-860-8530
Representative
Contact Micron Semiconductor, Inc.
Component Sales
Phone - 208-368-3900
Fax - 208-368-3488
Micron DataFax - 208-368-5800
SALES AND SERVICE INFORMATION
Rev. 2195
Wyle Laboratories
2055 Army Trail Road, Suite 140
Addison,IL 60101
Phone - 708-620-0969
Fax - 708-620-1610
10-27
Representatives
Scott Electronics, Inc. (5. IN)
7321 Shadeland Station, Suite 256
Indianapolis, IN 46256
Phone -317-841-0010
Fax - 317-841-0107
Scott Electronics, Inc. (N. IN)
Lima Valley Office Village
8109 Lima Road
Fort Wayne, IN 46818-2162
Phone - 219-489-5690
Fax - 219-489-1842
Distributor
Hamilton Hallmark
4275 W. 96th Street
Indianapolis, IN 46268
Phone -317-872-8875
Phone - 800-829-0146
Fax - 317-876-7165
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax -407-290-0164
IOWA
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Advanced Technical Sales
375 Collins Road N.B.
Cedar Rapids, IA 52402
Phone - 319-393-8280
Fax - 319-393-7258
en
Distributors
Anthem Electronics Incorporated
7690 Golden Triangle Drive
Eden Prairie, MN 55344
Phone -612-944-5454
Fax - 612-944-3045
en
Hamilton Hallmark
1130 Thorndale Avenue
Bensonville, IL 60106
Phone - 708-860-7780
Fax - 708-860-8530
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
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NORTH AMERICA
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1130 Thorndale Avenue
Bensenviiie, IL 60106
Phone - 708-860-7780
Fax - 708-860-8530
Wyle Laboratories
451 E. 124th Street
Thornton, CO 80241
Phone - 303-457-9953
Fax - 303-457-4831
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
SALES AND SERVICE INFORMATION
Aav.2195
NEVADA
Representatives
Bay Area Electronics Sales, Inc.
2001 Gateway Place, Suite 315 W.
San Jose, CA 95110
Phone - 408-452-8133
Fax -408-452-8139
Quatra Associates (Clark County)
4645 S. Lakeshore Drive, Suite 1
Tempe, AZ 85282
Phone - 602-820-7050
Fax - 602-820-7054
Hamilton Hallmark
10M Centennial Drive
Peabody, MA 01960
Phone -508-532-9808
Fax - 508-532-9802
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
NEW JERSEY
Distributors
Anthem Electronics Incorporated
580 Menlo Drive, Suite 8
Rocklin, CA 95677
Phone - 916-624-9744
Fax - 916-624-9750
Representatives
Omega Electronic Sales Inc.
Four Neshaminy Interplex, Suite 101
Trevose, PA 19053
Phone - 215-244-4000
Fax - 215-244-4104
Hamilton Hallmark
2105 Lundy Avenue
San Jose, CA 95131-1849
Phone - 408-435-3500
Fax - 408-435-3535
Parallax, Inc. (N. NJ)
734 Walt Whitman Road, Suite 209
Melville, NY 11747
Phone - 516-351-1000
Fax - 516-351-1606
Wyle Laboratories
2951 Sunrise Blvd., Suite 175
Rancho Cordova, CA 95742
Phone - 916-638-5282
Fax - 916-638-1491
Distributors
Anthem Electronics Incorporated
355 Business Center Drive
Horsham, PA 19044
Phone - 215-443-5150
Fax - 215-675-9875
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
NEW HAMPSHIRE
Representative
Advanced Tech Sales Inc.
348 Park Street, Suite 102
North Reading, MA 01864
Phone - 508-664-0888
Fax - 508-664-5503
Distributors
Anthem Electronics Incorporated
36 Jonspin Road
Wilmington, MA 01887
Phone - 508-657-5170
Fax -508-657-6008
10-30
Anthem Electronics Incorporated
26 Chapin Road, Unit K
Pine Brook, NJ 07058
Phone - 201-227-7960
Fax - 201-227-9246
Hamilton Hallmark
1 Keystone Avenue, Bldg. #36
Cherry Hill, NJ 08003
Phone - 609-751-2590
Fax - 609-751-2552
Hamilton Hallmark
10 Lanidex Plaza West
Parsippany, NJ 07054
Phone - 201-515-5300
Fax - 201-515-1601
Wyle Laboratories
20 Chapin Road, Bldg. 1013
Pinebrook, NJ 07058
Phone - 201-882-8358
Phone - 800-862-9953
Fax - 201-882-9109
Micron Technology, Inc., reserves the right to change products or speoifications without notice.
©199S, Micron Technology, Inc.
Wyle Laboratories
815 Eastgate Drive
Mt. Laurel, NJ 08054
Phone - 609-439-911 0
Fax - 609-439-9020
Electra Sales Corporation
6700 Old Collamer Road
East Syracuse, NY 13057
Phone - 315-463-1248
Fax - 315-463-1717
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
Parallax, Inc.
734 Walt Whitman Road, Suite 209
Melville, NY 11747
Phone - 516-351-1000
Fax - 516-351-1606
NEW MEXICO
Representative
Quatra Associates Incorporated
600 Autumnwood Place, S.E.
Albuquerque, NM 87123
Phone - 505-296-6781
Fax - 505-292-2092
Distributors
Anthem Electronics Incorporated
1555 W. 10th Place, Suite 101
Tempe, AZ 85281
Phone - 602-966-6600
Fax - 602-966-4826
Hamilton Hallmark
4637 South 36th Place
Phoenix, AZ 85040
Phone - 602-437-1200
Phone - 800-528-8471
Fax - 602-437-2348
Wyle Laboratories
4141 E. Raymond Street, Suite 1
Phoenix, AZ 85040
Phone - 602-437-2088
Fax - 602-437-2124
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
NEW YORK
Representatives
Electra Sales Corporation
333 Metro Park, Suite MI03
Rochester, NY 14623
Phone - 716-427-7860
Fax -716-427-0614
SALES AND SERVICE INFORMATION
Rev. 2195
NORTH CAROLINA
Representatives
Southeast Technical Group
4408 Ennismore Circle
Raleigh, NC 27613
Phone - 919-781-9857
Fax - 919-420-0274
Southeast Technical Group
1401 N. Arendell Avenue
Zebulon, NC 27597
Phone -919-269-5589
Fax - 919-269-5670
Distributors
Anthem Electronics
47 Mall Drive
Commack, NY 11725-5703
Phone - 516-864-6600
Fax - 516-493-2244
Distributor
Anthem Electronics Incorporated
4805 Green Road, Suite 100
Raleigh, NC 27604
Phone - 919-871-6200
Phone - 800-359-3532
Fax - 919-790-8970
Anthem Electronics Incorporated
26 Chapin Road, Unit K
Pinebrook, NJ 07058
Phone - 201-227-7960
Fax - 201-227-9246
Hamilton Hallmark
5234 Green' 5 Dairy Road
Raleigh, NC 27604
Phone - 919-872-0712
Fax - 919-878-8729
Hamilton Hallmark
3075 Veterans Memorial Hwy.
Ronkonkoma, NY 11779
Phone - 516-737-0600
Fax - 516-737-0838
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
Hamilton Hallmark
933A Motor Parkway
Hauppauge, NY 11788
Phone -516-434-7470
Fax - 516-434-7491
NORTH DAKOTA
Hamilton Hallmark
1057 East Henrietta Road
Rochester, NY 14623
Phone - 716-475-9130
Phone - 800-462-6440
Fax -716-475-9119
Representative
High Technology Sales Associates
4801 W. 81st Street, Suite 115
Bloomington, MN 55437
Phone - 612-844-9933
Fax - 612-844-9930
Wyle Laboratories
20 Chapin Road, Bldg. 1013
Pinebrook, NJ 07058
Phone - 201-882-8358
Phone - 800-862-9953
Fax - 201-882-9109
Distributors
Anthem Electronics Incorporated
7646 Golden Triangle Drive, Suite 160
Eden Prairie, MN 55344
Phone -612-944-5454
Fax - 612-944-3045
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
10-31
Hamilton Hallmark
9401 James Avenue South, Suite 140
Bloomington, MN 55431
Phone - 612-881-2600
Fax - 612-881-9461
Micron
Technology, Inc., reserves the right to change products;~:~;~~f:r~~n~e~~~~~~;~~~~:
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Wyle Laboratories
1325 E 79th Street, Suite 1
Bloomington, MN 55425
Phone - 612-853-2280
Fax -612-853-2298
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax -407-290-0164
OHIO
Representatives
Scott Electronics, Inc.
30 Alpha Park
Cleveland, OH 44143-2240
Phone - 216-473-5050
Fax -216-473-5055
Scott Electronics, Inc.
6728 Loop Road, Suite 202
Centerville, OH 45459
Phone - 513-291-9910
Fax -513-291-9022
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916 Eastwind Drive
Westerville, OH 43081-3379
Phone -614-882-6100
Fax -614-882-0900
Scott Electronics, Inc.
10901 Reed-Hartman Hwy., Suite 301
Cincinnati, OH 45242-2821
Phone -513-791-2513
Fax -513-791-8059
Distributors
Anthem Electronics Incorporated
7646 Golden Triangle Drive, Suite 160
Eden Prairie, MN 55344
Phone - 612-944-5454
Fax - 612-944-3045
c Hamilton Hallmark
Harper Road
en 5821
Solon, OH 44139
- 216-498-1100
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Fax - 216-248-4803
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777 Dearborn Park Lane, Suite L
Worthington, OH 43085
Phone - 614-888-3313
Fax - 614-888-0767
SALES AND SERVICE INFORMATION
Rev. 2195
SALES AND SERVICE INFORMATION
NORTH AMERICA
",'"cW", "
Hamilton Hallmark
7760 Washington Village Drive
Dayton, OH 45459
Phone - 513-439-6735
Phone - 800-423-4688
Fax - 513-439-6711
Wyle Laboratories
1821 Walden Office Square, Suite 332
Schaumburg, IL 60173
Phone - 708-303-1040
Fax - 708-303-1055
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
OKLAHOMA
Representative
Nova Marketing Incorporated
8421 East 61st Street, Suite P #139
Tulsa, OK 74145
Phone - 918-660-5105
Fax - 918-357-1091
Distributor
Hamilton Hallmark
12206 E. 51st Street, Suite 103
Tulsa, OK 74146
Phone - 918-254-6110
Fax - 918-254-6207
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
OREGON
Sales Office
Micron Sales Northwest, Inc.
AmberGlen Business Center
1600 N.w. Compton Drive, Suite 206
Beaverton, OR 97006
Phone -503-531-2010
Fax - 503-531-2011
Distributors
Anthem Electronics Incorporated
9090 S.w. Gemini Drive
Beaverton, OR 97005
Phone -503-643-1114
Fax - 503-626-7928
10-32
Hamilton Hallmark
9750 S.w. Nimbus Avenue
Beaverton, OR 97005
Phone - 503-526-6200
Fax - 503-641-5939
Wyle Laboratories
9640 Sunshine Court, Suite 200, Bldg. G
Beaverton, OR 97005
Phone - 503-643-7900
Fax - 503-646-5466
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
PENNSYLVANIA
Representatives
Omega Electronic Sales Incorporated (E. PA)
Four Neshaminy Interplex, Suite 101
Trevose, PA 19053
Phone - 215-244-4000
Fax - 215-244-4104
Scott Electronics, Inc. (W. PAl
916 Eastwind Drive
Westerville, OH 43081-3379
Phone - 614-882-6100
Fax - 614-882-0900
Distributors
Anthem Electronics Incorporated
355 Business Center Drive
Horsham, PA 19044
Phone - 215-443-5150
Fax - 215-675-9875
Hamilton Hallmark (W. PAl
5821 Harper Road
Solon, OH 44139
Phone -216-498-1100
Fax - 216-248-4803
Wyle Laboratories
815 Eastgate Drive
Mt. Laurel, NJ 08054
Phone - 609-439-9110
Fax - 609-439-9020
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
MICRON
1-·
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SALES AND SERVICE INFORMATION
NORTH AMERICA
PUERTO RICO
SOUTH CAROLINA
Representative
Photon Sales, Inc.
1600 Sarno Road, Suite 21
Melbourne, FL 32935
Phone - 407-259-8999
Fax - 407-259-1323
Representative
Southeast Technical Group
1401 N. Arendell Avenue
Zebulon, NC 27597
Phone - 919-269-5589
Fax - 919-269-5670
Distributors
Anthem Electronics
5200 N.W. 33rd Avenue, Suite 206
Ft. Lauderdale, FL 33309
Phone - 305-484-0900
Fax - 305-484-0951
Distributor
Anthem Electronics Incorporated
4805 Green Road, Suite 100
Raleigh, NC 27604
Phone - 919-871-6200
Phone -800-359-3532
Fax - 919-790-8970
Wyle Laboratories
600 West Hillsboro, Suite 300
Deerfield Beach, FL 33441
Phone - 305-420-0500
Fax - 305-428-2134
Die Distributor
Chip Supply
7725 N. Orange BlossomTrail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
RHODE ISLAND
Representative
Advanced Tech Sales Inc.
348 Park Street, Suite 102
North Reading, MA 01864
Phone - 508-664-0888
Fax - 508-664-5503
Distributors
Anthem Electronics Incorporated
61 Mattatuck Heights
Waterbury, CT 06705
Phone - 203-575-1575
Fax - 203-596-3232
Hamilton Hallmark
125 Commerce Court, Unit 6
Cheshire, CT 06410
Phone - 203-271-2844
Fax - 203-272-1704
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlill\do, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
SALES AND SERVICE INFORMATION
Rev. 2195
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
TENNESSEE
Representative
Southeast Technical Group
101 Washington, Suite 6
Huntsville, AL 35801
Phone - 205-534-2376
Fax - 205-534-2384
Hamilton Hallmark
5234 Green's Dairy Road
Raleigh, NC 27604
Phone - 919-872-0712
Fax - 919-878-8729
Distributors
Hamilton Hallmark
3425 Corporate Way, Suite A and G
Duluth, GA 30136-2552
Phone - 404-623-4400
Fax - 404-476-8806
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
Wyle Laboratories
Tower Building, 2nd Floor
7800 Governers Drive West
Huntsville, AL 35807
Phone - 205-830-1119
Fax - 205-830-1520
soum DAKOTA'
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
Representative
High Technology Sales Associates
4801 W. 81st Street, Suite 115
Bloomington, MN 55437
Phone - 612-844-9933
Fax - 612-844-9930
TEXAS
Distributors
Anthem Electronics Incorporated
7646 Golden Triangle Drive, Suite 160
Eden Prairie, MN 55344
Phone - 612-944-5454
Fax - 612-944-3045 ..
Representatives
Nova Marketing Incorporated
8350 Meadow Road, Suite 174
Dallas, TX 75231
Phone - 214-265-4600
Fax -.214-265-4668
Hamilton Hallmark
9401 James Avenue South, Suite 140
Bloomington, MN 55431
Phone - 612-881-2600
Fax· 612-881-9461
Nova Marketing Incorporated
10701 Corporate Drive, Suite 140
Stafford, TX 77477
Phone -713-240-6082
Fax - 713-240-6094
Wyle Laboratories
1325 East 79th Street, Suite 1
Bloomington, MN 55425
Phone - 612-853-2280
Fax - 612-853-2298
Nova Marketing Incorporated
8310 Capitol of Texas Hwy. North, Suite 180
Austin, TX 78731
Phone - 512-343-2321
Fax - 512-343-2487·
10-33
Micron Technology, Inc.. reserves the right to change products or specifications without notice.
@1995,MlcronTechnoiogy, Inc.
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Quatra Associates, Inc. (El Paso, TX)
600 Autumnwood Place, S.E.
Albuquerque, NM 87123
Phone - 505-296-6781
Fax -505-292-2092
Distributors
Anthem Electronics Incorporated
651 N. Plano Road, Suite 401
Richardson, TX 75081
Phone - 214-238-7100
Fax -214-238-0237
Anthem Electronics Incorporated
14050 Summit Drive, Suite 119
Austin, TX 78728
Phone -512-388-0049
Fax -512-388-0271
Hamilton Hallmark
12211 Technology Blvd.
Austin, TX 78727
Phone - 512-258-8848
Fax -512-258-3777
Hamilton Hallmark
11420 Pagemill Road
Dallas, TX 75243
Phone - 214-553-4300
Fax - 214-553-4395
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Hamilton Hallmark
8000 Westglen
Houston, TX 77063
Phone -713-781-6100
Fax - 713-953-8420
Wyle Laboratories
4030 W. Braker Lane, Suite 420
Austin, TX 78759
Phone - 512-345-8853
Fax - 512-834-0981
Wvle Laboratories
1810 N. Greenville Avenue
Richardson, TX 75081
Phone - 214-235-9953
Fax -214-644-5064
Wyle Laboratories
11001 S. Wilcrest, Suite 100
m Houston,
TX 77099
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NORTH AMERICA
"",cwc, "
Phone -713-879-9953
Fax - 713-879-6540
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone· 407-298-7100
Fax -407-290-0164
SALES AND SERVICE JNFOAMAnON
Aev.2195
UTAH
Representative
Wescom Marketing
3500 S. Main, Suite 100
Salt Lake City, UT 84115
Phone -801-269-0419
Fax - 801-269-0665
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
VIRGINIA
Distributors
Anthem Electronics Incorporated
1279 West 2200 South
Salt Lake City, UT 84119
Phone - 801-973-8555
Fax - 801-973-8909
Representative
Electronic Engineering & Sales, Inc.
305 Kramer Road
Pasadena, MD 21122
Phone -410-255-9686
Fax - 410-255-9688
Hamilton Hallmark
1100 East 6600 South, Suite 120
Salt Lake City, UT 84121
Phone - 801-266-2022
Fax - 801-263-0104
Distributors
Anthem Electronics Incorporated
7168 A Columbia Gateway Drive
Columbia, MD 21046-2101
Phone - 301-995-6640
Fax - 301-381-4379
Wyle Laboratories
1325 West 2200 South, Suite E
Salt Lake City, UT 84119
Phone - 801-974-9953
Fax - 801-972-2524
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
VERMONT
Representative
Advanced Tech Sales Inc.
348 Park Street, Suite 102
North Reading, MA 01864
Phone - 508-664-0888
Fax - 508-664-5503
Distributors
Anthem Electronics Incorporated
36 Jonspin Road
Wilmington, MA 01887
Phone - 508-657-5170
Fax - 508-657-6008
Hamilton Hallmark
10M Centennial Drive
Peabody, MA 01960
Phone -508-532-9808
Fax - 508-532-9713
10-34
Hamilton Hallmark
10240 Old Columbia Road
Columbia, MD 21046
Phone -410-988-9800
Fax - 410-381-2036
Wyle Laboratories
7180 Columbia Gateway Drive, Suite 100
Columbia, MD 21046
Phone -410-312-4844
Fax - 410-312-4953
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
WASHINGTON
Sales Office
Micron Sales Northwest, Inc.
P.O. Box 902
Woodinville, WA 98072-0902
Phone - 206-486-2775
Fax - 206-486-3960
Distributors
Anthem Electronics Incorporated
19017-120th Avenue N.E., Suite 102
Bothell, WA 98011
Phone - 206-483-1700
Fax - 206-486-0571
Micron Technology, inc., reserves the right to change products or specifi?ations without notice.
©1995, Micron Technology, Inc.
I"IIC:RCN
SALES AND SERVICE INFORMATION
NORTH AMERICA
","",co,",
Hamilton Hallmark
l216154th Avenue N.E.
Redmond, WA 98052
Phone - 206-882-7000
Fax - 206-882-7070
Wyle Laboratories
15385 N.E. 90th Street
Redmond, WA 98052-3522
Phone - 206-881-1150
Phone - 800-248-9953
Fax - 206-881-1567
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
WEST VIRGINIA
Representative
Scott Electronics, Inc.
916 Eastwind Drive
Westerville, OH 43081-3379
Phone - 614-882-6100
Fax - 614-882-0900
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
WISCONSIN
Die Distributor
Representatives
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
High Technology Sales Associates (w. WI)
4801 W. 81st Street, Suite 115
Bloomington, MN 55437
Phone - 612-844-9933
Fax - 612-844-9930
Industrial Representatives, Inc. (E. WI)
2831 N. Grandview, Suite 215
Pewaukee, WI 53072
Phone -414-574-9393
Fax - 414-574-9394
Distributors
Anthem Electronics Incorporated
1300 Remington, Suite A
Schaumburg, IL 60173
Phone - 708-884-0200
Fax - 708-884-0480
Hamilton Hallmark
2440 S. 179th Street
New Berlin, WI 53146-2152
Phone - 414-797-7844
Fax - 414-797-9259
Wyle Laboratories
150 N. Patrick Blvd., Suite 150
Brookfield, WI 53045
Phone -414-879-0434
Phone - 800-867-9953
Fax - 414-879-0474
WYOMING
Representative
Contact Micron Semiconductor, Inc.
Component Sales
Phone - 208-368-3900
Fax - 208-368-3488
Micron DataFax - 208-368-5800
Distributors
Anthem Electronics Incorporated
373 Inverness Drive
Englewood, CO 80112
Phone - 303-790-4500
Fax - 303-790-4532
Wyle Laboratories
1325 West 2200 South, Suite E
Salt Lake City, UT 84119
Phone - 801-974-9953
Fax - 801-972-2524
Die Distributor
Chip Supply
7725 N. Orange Blossom Trdii
Orlando, FL 32810-26%
Phone - 407-298-7100
Fax - 407-290-0164
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Macnica, Inc.
Hakusan High-Tech Park
1-22-2 Hakusan
Midori-ku, Yokohama City 226
Phone - 81-45-939-6140
Fax -81-45-939-6141
Sanyo Electric Co. Ltd.
Import Promotion Division
1-1-10 Deno
Taito-ku, Tokyo 110
Phone - 81-3-3837-6345
Fax - 81-3-3837-6379
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
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SALES AND SERVICE INFORMATION
Rev. 2195
SALES AND SERVICE INFORMATION
INTERNATIONAL
,"~""OO, '"'
KOREA
Representative
I & C Microsystems Co. Ltd.
3rd Floor, Jung-Nam Bldg.
191-3 Poi-Dong
Kangnam-Ku
Seoul
Phone - 822-577-9131
Fa~ - 822-577-9130
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
LUXEMBOURG
Representative
Microtron
Generaal De Wittelaan 7
B-2800 Mechelen
Phone - 32-15-212223
Fax - 32-15-210069
Distributor
EBV Elektronik GmbH
Excelsiorlaan 35
B-1930 Zaventem
Belgium
Phone - 32-2 7209936
Fax - 32-2-7208152
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
MALAYSIA
Distributors
Desner (Malaysia) Sdn. Bhd.
23 Jalan Sarikei
53000 Kuala Lumpur
Phone - 60-3-4211123
Fax - 60-3-4219923
Desner (Malaysia) Sdn. Bhd.
39 Persiaran Bukit Kecil5
Taman Sri Nibong
11900 Bayan Lepas
Penang
Phone - 60-4-838352
Fax - 60-4-849370
10-38
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
THE NETHERLANDS
Representative
Microtron
Beneluxweg 37
Postbus 4336
NL-4904 SJ Ooslerhout
Phone - 31-162-060-308
Fax - 31-162-060-633
Distributor
EBV Elektronik GmbH
Planetenbaan 2
NL-3606 AK Maarssenbroek
Phone - 31 34 65-62353
Fax - 31 34 65-64277
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax -407-290-0164
NEW ZEALAND
Distributor
Maxbyte Technologies
35 Kaihuia Street
P.O. Box 28-096
Wellington, 6001
Phone - 642-542-7799
Fax - 644-475-3856
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
NORWAY
Representative
Integrerad Elektronik Komponenter AB
Box 11113, Ulvsundavagen 106
5-161 11 Bromma
Sweden
Phone -46-8-804-685
Fax -46-8-262-286
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
UII::::F=lCN
1-·
SALES AND SERVICE INFORMATION
INTERNATIONAL
"'"''"'"''''
Distributor
Avnet Nortec A!S
Smedsvingen 4B
N-1364 Hvalstad
Phone -47-284-6210
Fax -47-284-6545
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
PHILLIPINES
Distributor
Desner Electronics (FE) Pte. Ltd.
42 Mactaggart Road
#04-01 Mactaggart Bldg.
Singapore 1336
Phone - 65-285-1566
Fax - 65-284-9466
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
PORTUGAL
Distributor
EBV Elektronik
Calle Maria Tubau, 5
28050 Madrid
Phone - 34-1-358-8608
Fax - 34-1-358-8560
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
SINGAPORE
Sales & Customer Service Office
Micron Semiconductor Asia Pacific, Pte Ltd
629 Aljunied Road #07-21
Cititech Industrial Bldg.
Singapore 1438
Phone - 65-841-4066
Fax - 65-841-4166
SALES AND SERVICE INFORMATION
Rev. 2/95
Distributor
Desner Electronics (FE) Pte. Ltd.
42 Mactaggart Road
#04-01 Mactaggart Bldg.
Singapore 1336
Phone - 65-285-1566
Fax - 65-284-9466
Representative
Integrerad Elektronik Komponenter AB
Box 11113, Ulvsundavagen 106
5-16111 Bromma
Phone - 4&-8-804-685
Fax - 46-8-262-286
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
Distributor
Avnet Nortec AB
Englundavagen 7
5-171 27solna
Phone - 46-8-629-1400
Fax - 46-8-627-0280
SLOVENIA
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
Representative
Thomas Neuroth GmbH
Heitzinger Hauptstrasse 22/ A/2
A-1130Wien
Austria
Phone - 43-1-877-5645
Fax - 43-1-876-4920
SOUTH AFRICA
Distributor
Computer Parts cc
CNR Athol and Louis Botha Avenue
Highlands North
Johannesburg 2192
Phone - 27-11-887-2438
Fax - 27-11-887-2514
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
SPAIN
Distributor
EBV Elektronik
Calle Maria Tubau, 5
28050 Madrid
Phone - 34-1-358-8608
Fax - 34-1-358-8560
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
10-39
SWEDEN
SWITZERLAND
Distributors
Avnet E2000 AG
Biihnirainstrasse 11
CH-8801 Thalwil
Phone -411-7 22 13 30
Fax - 411-7 2213 40
EBV Elektronik GmbH
Vorstadtstrasse 37
CH-8953 Dietikon
Phone - 411-7 401090
Fax-411-7415110
Fenner Elektronik AG
Gewerbestralle 10
CH-4450 Sissach
Phone - 416-197 50 00 0
Faxc-416-19717421
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone -407-298-7100
Fax - 407-290-0164
TAIWAN, R.O.c.
Sales & Customer Service Office
Micron Semiconductor Asia Pacific, Inc.
Suite 1010, 10th Floor
333 Keelung Road, Sec 1
Taipei,110
Phone - 886-2-757-6622
Fax - 886-2-757-6656
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
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Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
THAILAND
Distributor
Desner Electronics (Thailand) Co. Ltd.
lIF Silom Palace Building
11th Floor, Room 160/128-129
Silorr Road, Bangkok 10500
Phone - 662-2356492-5
Extension - 128-129
Fax -662-2668040
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax -407-290-0164
SALES AND SERVICE INFORMATION
INTERNATIONAL
UNITED KINGDOM
Sales & Customer Service Office
Micron Europe Limited
Centennial Court
Easthampstead Road
Bracknell
Berkshire RG12 lJA
Phone - 44-344-360055
Fax - 44-344-869504
Representative
Cedar Technologies U.K. Ltd.
Unit One Old Barns
Rycote Lane Farm
Milton Common
Oxfordshire OX9 2NZ
Phone -44-1844-278278
Fax - 44-1844-278378
Distributors
Avnet EMG Access
Jubilee House
Jubilee Road
Letchworth, Hertfordshire SG61QH
Phone - 44-0462-480888
Fax - 44-0462-488567
Macro Group
Burnham Lane
Slough, Berkshire SLl 6LN
Phone -44-628-604383
Fax -44-628-666873
Die Distributor
Chip Supply
7725 N. Orange Blossom Trail
Orlando, FL 32810-2696
Phone - 407-298-7100
Fax - 407-290-0164
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DOCUMENT
NUMBER
FPM DRAMs (continued)
MT4C4001J ....................
MT4C400lJ 5 .................
MT4LC4001J .................
MT4LC4001J 5 ..............
MT4C4004J ....................
MT4C4M4B1 .................
MT4LC4M4B1 ..............
MT4LC4M4B1 5 ...........
MT4LC16M4A7 ............
MT4LC16M4T8 ............
MT4LC2M8Bl ..............
MT4LC2M8Bl 5 ...........
MT4LC8M8El ..............
MT4LC8M8B6 ..............
MT4C16257 ...................
MT4LC16257 ................
MT4LC162575 .............
MT4CIM16C3 ..............
MT4LC1M16C3 ............
MT4LCIM16C3 5 .........
(Rev. 2/95) ............... 1 Meg x 4
(Rev. 2/95) ............... 1 Meg x4
(Rev. 2/95) ............... 1 Meg x 4
(Rev. 2/95) ............... 1 Meg x 4
(Rev. 2/95) ............... 1 Meg x 4
(Rev. 2/95) .............. .4 Meg x 4
(Rev. 2/95) .............. .4 Meg x 4
(Rev. 2/95) .............. .4 Meg x 4
(Rev. 2/95) ............. 16 Meg x 4
(Rev. 2/95) ............. 16 Meg x 4
(Rev. 2/95) ............... 2 Meg x 8
(Rev. 2/95) ............... 2 Meg x 8
(Rev. 2/95) ............... 8 Meg x 8
(Rev. 2/95) ............... 8 Meg x 8
(Rev. 2/95) ................. 256K x 16
(Rev. 2/95) ................. 256K x 16
(Rev. 2/95) ................. 256K x 16
(Rev. 2/95) ............... 1 Meg x 16
(Rev. 2/95) ............... 1 Meg x 16
(Rev. 2/95) ............... 1 Meg x 16
DC .. ..
1KR .. .
4KR ........ .
S
16 pg .......... 106
16 pg .......... 106
14 pg .......... 107
14pg .......... 107
13pg .......... 118
14 pg .......... 114
16 pg .......... 115
16 pg .......... 115
13 pg .......... 122
13 pg .......... 122
16 pg .......... 307
16 pg .......... 307
13 pg .......... 124
13 pg .......... 124
16pg .......... 302
18 pg .......... 311
18 pg .......... 311
16 pg .......... 312
17 pg .......... 308
17 pg .......... 308
... Dual CAS
QC .
..................................... QuadCAS
.. .. 1,024 Refresh
........ 4,096 Refresh
2KR
8KR
5V ..
. .. ........ .... .... ............. ................. 2,048 Refresh
................. 8,192 Refresh
... SELF REFRESH
3.3V.
5V .....................................................................
5V, 5 .................................................................
3.3V ..................................................................
3.3V, 5 ..............................................................
5V,QC .............................................................
5V, 2KR ...........................................................
3.3V, 2KR ........................................................
3.3V, 2KR, S ....................................................
3.3V,8KR ........................................................
3.3V, 4KR .......................................................
3.3V, 2KR ........................................................
3.3V, 2KR, S ....................................................
3.3V,8KR ........................................................
3.3V,4KR ........................................................
5V, DC .............................................................
3.3V, DC ..........................................................
3.3V, DC, 5 ......................................................
5V, DC, 1KR ...................................................
3.3V, DC, 1KR ................................................
3.3V, DC, 1KR, 5 ............................................
............................ 5 volt Vee
......................... 3.3 volt Vee
SGRAM
MT41LC256K32D4 ...... (Rev. 2/95) ................. 256K x 32
MT41 LC256K32D4 5 ... (Rev. 2/95) ................. 256Kx 32
3.3V .................................................................. 15 pg ...... 2700'
3.3V, 5 .............................................................. 15 pg ...... 2700*
S
3.3V .........
. ............................... ....... ........................ .. .... SELF REFRESH
....................... 3.3 volt Vee
DRAM DIE
D22A .............................. (Rev. 7/94)
0l8A .............................. (Rev. 9/94)
D21A .............................. (Rev. 7/94)
D24A.. ""._ ................... (Rev. 7/94)
....................... 4 Meg
...................... .4 Meg
..... ,............... 16 Meg
..................... 16 tv1eg
xl, x4 .................................................................
x8, x16 ...............................................................
x4 .......................................................................
x4, x8, x16 .........................................................
............... 1 Meg x 8
.............. .4 Meg x 8
.............. .4 Meg x 8
.............. .4 Meg x 9
.............. .4 Meg x 9
................. 256K x 32
................. 512K x 32
............... 1 Meg x 32
............... 1 Meg x 32
5V ...... ,..............................................................
5V .....................................................................
5V .....................................................................
5V .....................................................................
5V .....................................................................
5V .....................................................................
5V .....................................................................
5V .....................................................................
5V, S .................................................................
4 pg ........ 2401
4 pg ........ 2400
4 pg ........ 2402
4 pg ........ 2403
DRAM SIMMs
-Z
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MT2D18 ......................... (Rev. 2/95)
MT2D48 ......................... (Rev. 2/95)
MT8D48 ......................... (Rev. 2/95)
MT3D49 ......................... (Rev. 2/95)
MT9D49 ......................... (Rev. 2/95)
MT2D25632 ................... (Rev. 2/95)
MT4D51232 ................... (Rev. 2/95)
MT8D132 ....................... (Rev. 2/95)
MT8D132 S .................... (Rev. 2/95)
S ................................... ..
5V .........
.. .......................................... SELF REFRESH
...5 volt Vee
EDO ................. ..
3.3V ............................................... .
11 pg .......... 400
11 pg .......... 402
l1pg .......... 403
l1pg .......... 406
11 pg .......... 407
13 pg .......... 433
13 pg .......... 433
16 pg .......... 447
16 pg .......... 447
................... Extended Data-Out
............................................. 3.3 volt Vee
'Because this document exceeds the maximum length for effective fax processing, only an abbreviated version can be faxed. Along with the abbreviated fax
version, you will receive a form offering you several alternative ways to receive the complete document, depending on urgency.
MICRON DATAFAX INDEX
Rev. 2195
11-2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology. Inc.
DOCUMENT
NUMBER
DRAM SIMMs (continued)
MT8LD(T)132 ............... (Rev. 2/95)
MT8LD(f)132 S ............ (Rev. 2/95)
MT8LD(T)132 X ........... (Rev. 2/95)
MT8LD(T)132 XS ......... (Rev. 2/95)
MT16D232 ..................... (Rev. 2/95)
MT16D232 S .................. (Rev. 2/95)
MT16LD(D232 ............. (Rev. 2/95)
MT16LD(D232 S .......... (Rev. 2/95)
MT16LD(T)232 X ......... (Rev. 2/95)
MT16LD(D232XS ....... (Rev. 2/95)
MT4LD232 .................... (Rev. 2/95)
MT4LD232 S ................. (Rev. 2/95)
MT4LD232 X ................. (Rev. 2/95)
MT4LD232XS .............. (Rev. 2/95)
MT8D432 ....................... (Rev. 2/95)
MT8D432 S .................... (Rev. 2/95)
MT8LD432 .................... (Rev. 2/95)
MT8LD432 S ................. (Rev. 2/95)
MT8LD432 X ................. (Rev. 2/95)
MT8L0432 XS .............. (Rev. 2/95)
MT16D832 ..................... (Rev. 2/95)
MT16D832 S .................. (Rev. 2/95)
MT16LD832 .................. (Rev. 2/95)
MT16LD832 S ............... (Rev. 2/95)
MT16LD832 X ............... (Rev. 2/95)
MT16LD832XS ............ (Rev. 2/95)
MT9D136 ....................... (Rev. 2/95)
MT18D236 ..................... (Rev. 2/95)
MT12D436 ..................... (Rev. 2/95)
MT12D436 S .................. (Rev. 2/95)
MT24D836 ..................... (Rev. 2/95)
MT24D836 S .................. (Rev. 2/95)
............... 1 Meg x 32
............... 1 Meg x 32
............... 1 Meg x 32
............... 1 Meg x 32
............... 2 Meg x 32
............... 2 Meg x 32
............... 2 Meg x 32
............... 2 Meg x 32
............... 2 Meg x 32
............... 2 Megx32
............... 2 Meg x 32
............... 2 Meg x 32
............... 2 Meg x32
............... 2 Megx32
.............. .4 Meg x 32
............... 4 Meg x32
.............. .4 Meg x 32
.............. .4 Meg x 32
............... 4 Meg x 32
.............. .4 Meg x 32
............... 8 Meg x32
............... 8 Meg x 32
............... 8 Meg x 32
............... 8 Meg x 32
............... 8 Meg x 32
............... 8 Megx32
............... 1 Meg x 36
............... 2 Meg x36
............... 4 Meg x 36
............... 4 Meg x 36
............... 8 Meg x 36
............... 8 Meg x 36
3.3V .................................................................. 24 pg .......... 441
3.3V, S .............................................................. 24 pg .......... 441
3.3V, EDO ................... :................................... 24 pg .......... 441
3.3V, EDO, S ................................................... 24 pg .......... 441
5V ..................................................................... 16 pg .......... 447
5V, S ................................................................. 16 pg .......... 447
3.3V .................................................................. 24 pg .......... 441
3.3V, S ............................... ;.............................. 24 pg .......... 441
3.3V, EDO ....................................................... 24 pg .......... 441
3.3V, EDO, S ................................................... 24 pg .......... 441
3.3V .................................................................. 21 pg .......... 442
3.3V, S .............................................................. 21 pg .......... 442
3.3V, EDO ....................................................... 21 pg .......... 442
3.3V, EDO, S ................................................. :.21 pg .......... 442
5V ....... ~ ... ;.......................................................... 14 pg .......... 412
5V, S ..·..,; ........................................................... 14 pg .......... 412
3.3V .................................................................. 22 pg .......... 441
3.3V, S .............................................................. 22 pg .......... 441
3.3V, EOO ....................................................... 22 PH .......... 441
3.3V, EOO, S ................................................... 22 PH .......... 441
5V ..................................................................... 14pg .......... 412
5V, S ................................................................. 14 pg .......... 412
3.3V .................................................................. 22 pg :......... 443
3.3V, S .............................................................. 22 pg .......... 443
3.3V, EOO ...............................................;....... 22 pg ......... ; 443
3.3V"EDO, S ................................................... 22 pg .......... 443
5V ..................................................................... 13pg .......... 449
5V ..................................................................... 13 pg .......... 449
5V ..................................................................... 16 pg .......... 417
5V, S ................................................................. 16 pg .......... 417
5V ........... ;...............................................: .......... 16 pg .......... 417
5V, S ................................................................. 16 pg .......... 417
•
C
S .. "......................................... ,............................ ,'........ ,'.............. SELF REFRESH
Eoo ............................................................................................ Extended Data-Out ......
5V ......................................................................................................... 5 volt Vee
3.3V .............................................. :.;.......................................................... 3.3 volt Vee
DRAMDIMMs
MT2LD(T)132H ............
MT2LD(T)132H S .........
MT4LD(T)232H ............
MT4LD(T)232H S .........
MT8LD(D432H ............
MT8LD(T)432H S .........
MT16D(T)164 ................
MT16D(T)164 S ............
MT16LD(T)164 .............
MT16LD(T)164 S ..........
MT8LD(D264 ...............
MT8LD(D264 S ............
MT8LD(D264 X ...........
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
............... 1 Meg x 32
............... 1 Meg x 32
............... 2 Meg x 32
............... 2 Meg x 32
.............. .4 Meg x 32
.............. .4 Meg x 32
............... 1 Meg x 64
............... 1 Meg x 64
............... 1 Meg x 64
............... 1 Meg x.64
............... 2 Meg x 64
............... 2 Meg x 64
............... 2 Meg x 64
33·33V ..S.... ·.. ·.. ··· .. ·.. ·· .... ······· .. ·.. ···· .... ··· .. ·.... ·.... ·····
. , ..............................................................
3.3V ..................................................................
3.3V, S ..............................................................
1
446
166 pg .......... 446
pg..........
16 pg .......... 446
16 pg .......... 446
~:~~:S:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: ~~ ~~ :::::::::: ::~
5V ..................................................................... 19pg ....... ;.. 429
5V,S ................................................................. 19pg .......... 429
~:~~:S:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::: ~: ~: :::::::::: ~~
3.3V ........................... ;....................................... 23 pg .......... 437
3.3V, S ........................................... ;.................. 23 pg .......... 437
3.3V, EOO ....................................................... 23 pg .......... 437
S .................................................................................................. SELF REFRESH
Eoo ............................................................................................ Extended Data-Out
5V ......................................................................................................... 5 volt Vee
3.3V ........................................................................................................... 3.3 volt Vee
MICRON DATAFAX INDEX
Rev. 2195
11-3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
@1995,MlcronTechnology,lnc.
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DOCUMENT
NUMBER
DRAM DIMMs (continued)
MT8LD(T)264 X5 .........
MT16D(T)464 ................
MT16LD(T)464 .............
MT16LD(T)4645 ..........
MT16LD(T)464 X .........
MT16LD(T)464 X5 .......
MT18D(T)172 ................
MT18D(T)172 5 ............
MT18LD(T)172 .............
MT18LD(T)172 5 ..........
MT9LD(T)272 ...............
MT9LD(T)272 5 ............
MT9LD(T)272 X ...........
MT9LD(T)272 X5 .........
MT18D(T)472 ................
MT18LD(T)472 .............
MT18LD(T)472 5 ..........
MT18LD(T)472 X .........
MT18LD(T)472 X5 .......
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
S
............... 2 Meg x 64
.............. .4 Meg x 64
.............. .4 Meg x 64
.............. .4 Meg x 64
.............. .4 Meg x 64
.............. .4 Meg x 64
............... 1 Meg x 72
............... 1 Meg x 72
............... 1 Meg x 72
............... 1 Meg x 72
............... 2 Meg x 72
............... 2 Meg x 72
............... 2 Meg x 72
............... 2 Meg x 72
.............. .4 Meg x 72
.............. .4 Meg x 72
.............. .4 Meg x 72
.............. .4 Meg x 72
.............. .4 Meg x 72
." SELF REFRESH
............. 5 volt Vee
5V ................................................. .
3.3V, EDO, 5 ................................................... 23 pg .......... 437
5V ..................................................................... 19 pg .......... 429
DV ..................................................................
M~
3.3V, 5 ..............................................................
3.3V, EDO .......................................................
3.3V, EDO, 5 ...................................................
5V .....................................................................
5V, 5 .................................................................
24 pg .......... 435
24 pg .......... 435
24 pg .......... 435
19pg .......... 451
19 pg .......... 451
.......... i l i
DV ................................................................ M~ .......... ~
3.3V, 5 ..............................................................
3.3V ..................................................................
3.3V, 5 ..............................................................
3.3V, EDO .......................................................
3.3V, EDO, 5 ...................................................
5V .....................................................................
3.3V ..................................................................
3.3V, 5 ..............................................................
3.3V, EDO .......................................................
3.3V, EDO, 5 ...................................................
EDO ..
3.3V ..... .
24 pg .......... 438
23 pg .......... 439
23 pg .......... 439
23 pg .......... 439
23 pg .......... 439
19 pg .......... 451
24 pg .......... 438
24 pg .......... 438
24 pg .......... 438
24 pg .......... 438
..... Extended Data-Out
. .. 3.3 volt Vee
DRAM CARDS
MT8D88C132(5) ...........
MT8D88C132H(5) ........
MT8D88C132V(5) ........
MT8D88C132VH(5) .....
MT16D88C232(5) .........
MT16D88C232H(5) ......
MT16D88C232V(5) ......
MT16D88C232VH(5) '"
MT8D88C432V(5) ........
MT8D88C432VH(5) .....
MT16D88C832V(5) ......
MT16D88C832VH(5) ...
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
(Rev. 2/95)
5V...
............... 1 Meg x 32
............... 1 Meg x 32
............... 1 Meg x 32
............... 1 Meg x 32
............... 2 Meg x 32
............... 2 Meg x 32
............... 2 Meg x 32
............... 2 Meg x 32
.............. .4 Meg x 32
.............. .4 Meg x 32
............... 8 Meg x 32
............... 8 Meg x 32
. ........................... 5 volt Vee
5V .....................................................................
5V .....................................................................
3.3V ..................................................................
3.3V ..................................................................
5V .....................................................................
5V .....................................................................
3.3V ..................................................................
3.3V ..................................................................
3.3V ..................................................................
3.3V ..................................................................
3.3V ..................................................................
3.3V ..................................................................
17 pg .......... 500
17 pg .......... 501
17 pg .......... 502
17 pg .......... 503
17 pg .......... 500
17 pg .......... 501
17 pg .......... 502
17 pg .......... 503
17 pg .......... 502
17 pg .......... 503
17 pg .......... 502
17 pg .......... 503
3.3V.....
............... 3.3 volt Vee
DRAM TECHNICAL NOTES
-Z
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TN-OO-Ol ............ Moisture Absorption in Plastic Packages (Rev. 2/95) ............................................................
TN-00-02 ............ Tape-and-Reel Procedures (Rev. 2/95) ....................................................................................
TN-00-03 ............ Using Gel-Pak®Packaging With Micron Die (Rev. 2/95) ......................................................
TN-04-01 ............ DRAM Power-Up and Refresh Constraints (Rev. 2/95) ........................................................
TN-04-06 ............ OE-Controlled/LATE WRITE Cycles (DRAM) (Rev. 2/95) .................................................
TN-04-12 ............ LPDRAM Extended Refresh Current vs. RA5 Active Time (4 Meg) (Rev. 2/95) ..............
TN-04-15 ............ DRAM Considerations for PC Memory Design (Rev. 2/95) .................................................
TN-04-16 ............ 16 Meg DRAM-2K vs. 4K Refresh Comparison (Rev. 2/95) ..............................................
TN-04-19 ............ Low-Power DRAMs vs. Slow 5RAMs for Main Memory (Rev. 2/95) ................................
TN-04-20 ............ SELF REFRESH DRAMs (Rev. 2/95) ........................................................................................
TN-04-21 ............ Reduce DRAM Cycle Times with Extended Data-Out (Rev. 2/95) .....................................
MICRON DATAFAX INDEX
Rev. 2/95
11-4
1 pg .......... 600
5 pg .......... 601
2 pg .......... 624
1 pg .......... 602
2 pg .......... 603
1 pg .......... 606
6 pg .......... 608
2 pg .......... 609
2 pg .......... 611
2 pg .......... 612
8 pg .......... 613
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
Gel-Pak is a registered trademark of Vichem Corporation.
DOCUMENT
NUMBER
DRAM TECHNICAL NOTES (continued)
TN-04-22 ............ 256K x 16 DRAM Typical Operating Curves (Rev. 2/95) ...................................................... 2 pg .......... 614
TN-04-23 ............ 4 Meg DRAM Typical Operating Curves (Rev. 2/95) ............................................................ 6 pg .......... 615
TN-04-24 ............ 4 Meg DRAM-Access Time vs. Capacitance (Rev. 2/95) .................................................... 2 pg .......... 616
TN-04-26 ............ 256K x 16-Access Time vs. Capacitance (Rev. 2/95) ............................................................ 1 pg .......... 619
TN-04-28 ............ DRAM Soft Error Rate Calculations (Rev. 2/95) .................................................................... 3 pg .......... 621
TN-04-29 ............ Maximizing EDO Advantages at the System Level (Rev. 2/95) ........................................ 12 pg .......... 622
TN-04-30 ............ Various Methods of DRAM Refresh (Rev. 2/95) .................................................................... 4 pg .......... 623
TN-04-31 ............ PCB Layout for 4 Meg x 4 300 Mil or 400 Mil SOJ (Rev. 2/95) ............................................. 2 pg .......... 626
TN-04-32 ............ Reduce DRAM Memory Cost with Cache (Rev. 2/95) .......................................................... 4 pg .......... 627
TN-41-01 ............ Decrement Bursting with the SGRAM (Rev. 2/95) ................................................................ 4 pg .......... 625
TN-88-01 ............ 88-Pin DRAM Cards (Rev. 2/95) ............................................................................................... 3 pg .......... 618
DRAM PRODUCT RELIABILITY
Product Reliability ....... (Rev. 2/95) ...................................................................................................................... 10 pg .......... 701
5VSRAMs
MT5C2561 .....................
MT5C2564 .....................
MT5C2565 .....................
MT5C256K4A1 .............
MT5C2568 .....................
MT5C128K8A1 .............
MT5C64K16A1 .............
(Rev. 11/94)
(Rev. 11/94)
(Rev. 11/94)
(Rev. 11/94)
(Rev. 11/94)
(Rev. 11/94)
(Rev. 11/94)
.............. 256Kx 1
................ 64Kx 4
................ 64K x 4
.............. 256Kx4
................ 32K x 8
.............. 128K x 8
................ 64K x 16
CE only ................................... ;.......................
CE only ...........................................................
CE & OE ..........................................................
CE & OE, Revolutionary Pinout .................
CE & OE ..........................................................
CE & OE, Revolutionary Pinout .................
BE, CE & OE, Revolutionary Pinout ..........
11 pg ........ 1202
11 pg ........ 1208
12 pg ........ 1209
10 pg ........ 1211
12 pg ........ 1215
10 pg ........ 1217
11 pg ........ 1221
...... CHIP ENABLE
..... BYTE ENABLE
OE .............................................. ., ......................................... OUTPUT I·:NAIIII'
REVOLUTIONARY PINOUT ............. CENTER PIN POWI,J{ ANIH ;Jl<
DOCUMENT
NUMBER
SYNCHRONOUSSRAMs
MT58LC64K18B2 .........
MT58LC64K18Ml ........
MT58LC32K32B2 .........
MT58LC32K32C4 .........
MT58LC32K36B2 .........
MT58LC32K36C4.........
MT58LC64K36B2 .........
(Rev.
(Rev.
(Rev.
(Rev.
(Rev.
(Rev.
(Rev.
11/94)
11/94)
11/94)
11/94)
11/94)
11/94)
12/94)
................ 64K x 18
............... 64K x 18
................ 32Kx32
................ 32K x 32
................ 32K x 36
................ 32K x 36
................ 64Kx36
SyncBurst™, Interleaved, Linear ................
SyncBurst, Linear ..........................................
SyncBurst ........................................................
SyncBurst, Interleaved, Pipelined ...............
SyncBurst, Interleaved .................................
SyncBurst, Interleaved, Pipelined ...............
..........................................................................
17 pg ........
17 pg ........
17 pg ........
16 pg ........
14 pg ........
14 pg ........
18pg ........
1502
1502
1512
1513
1508
1509
1514
SRAM MODULES
II
c
~
l>
~
MT8S6432 ......................
MT8LS6432 ...................
MT4S12832 ....................
MT4LS12832 .................
MT4LS12832R ...............
MT8S25632 ............. .......
MT8LS25632 .................
MT8LS25632R ........ .......
MT8LS132 .....................
MT2LSYT3264T1 ..........
MT2LSYT3264T2 ..........
MT2LSYT3264T4 ..........
MT2LSYT3264T6..........
MT2LSYT3264B2 ..........
MT2LSYT3264C4 .........
MT2LSYT3272T1 ..........
MT2LSYT3272T2 ..........
MT2LSYT3272T4 ..........
MT2LSYT3272T6 ..........
MT2LSYT3272B2 ..........
MT2LSYT3272C4 .........
MT4LSY6472T1 ............
MT4LSY6472T2 ............
MT4LSY6472T4 ............
MT4LSY6472T6 ............
MT4LSYT6472B2..
..
MT4LSYT6472C4 .........
(Rev. 11/94) ................ 64K x 32
(Rev. 11 /94) ................ 64K x 32
(Rev. 11/94) .............. 128K x 32
(Rev. 11/94) .............. 128K x 32
(Rev. 9/94) ............... 128Kx32
(Rev. 11 /94) .............. 256K x 32
(Rev. 11 /94) .............. 256K x 32
(Rev. 9/94) ............... 256K x 32
(Rev. 11/94) ............ 1 Meg x 32
(Rev. 11 /94) ............... 32K x 64
(Rev. 11/94) ............... 32Kx64
(Rev. 11/94) ................ 32K x 64
(Rev. 11/94) ............... 32K x 64
(Rev. 11/94) ............... 32K x 64
(Rev. 11 /94) ................ 32K x 64
(Rev. 11/94) ................ 32K x 72
(Rev. 11/94) ................ 32K x 72
(Rev. 11/94) ................ 32Kx72
(Rev. 11/94) ................ 32Kx72
(Rev. 11/94) ................ 32Kx72
(Rev. 11/94) ................ 32K x 72
(Rev. 11/94) ................ 64K x 72
(Rev. 11/94) ................ 64Kx 72
(Rev. 11/94) ................ 64K x 72
(Rev. 11/94) ................ 64Kx 72
(Rev. 11/94) ................ 64K x 72
(Rev. 11/94) ................ 64Kx 72
CE ..................................... .
........ CHIP ENABLE
CE & OE ............................................................ 9 pg ........ 1901
CE&OE ......................................................... ,.. 9pg ........ 1902
CE&OE ............................................................ 9pg ........ 1903
CE&OE ............................................................ 9pg ........ 1904
............................................................................ 9 pg ........ 1909
CE&OE ............................................................ 9pg ........ 1905
CE&OE ............................................................ 9pg ........ 1906
............................................................................ 9 pg ........ 1908
CE & OE ............................................................ 9 pg ........ 1907
SyncBurst, Linear .......................................... 13 pg ........ 3002
SyncBurst, Interleaved ................................. 13 pg ........ 3002
SyncBurst, Interleaved, Pipelined ............... 13 pg ........ 3003
SyncBurst, Linear, Pipelined ....................... 13 pg ........ 3003
SyncBurst, Interleaved, Linear ...................... 7 pg ........ 3000
SyncBurst, Interleaved, Linear, Pipelined ... 7 pg ........ 3001
SyncBurst, Linear .......................................... 14 pg ........ 3006
SyncBurst, Interleaved ................................. 14 pg ........ 3006
SyncBurst, Interleaved, Pipelined ............... 14 pg ........ 3007
SyncBurst, Linear, Pipelined ....................... 14 pg ........ 3007
SyncBurst, Interleaved, Linear ...................... 8 pg ........ 3004
SyncBurst, Interleaved, Linear, Pipelined ... 8 pg ........ 3005
SyncBurst, Linear .......................................... 14 pg ........ 3006
SyncBurst, Interleaved ................................. 14 pg ........ 3006
SyncBurst, Interleaved, Pipelined ............... 14 pg ........ 3007
SyncBurst, Linear, Pipelined ....................... 14 pg ........ 3007
SyncBurst, Interleaved, Linear ...................... 8 pg ........ 3004
SyncBurst, Interleaved, Linear, Pipelined ... 8 pg ........ 3005
OE .
>< SRAM TECHNICAL NOTES
Z
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....................................................... OUTPUT ENABLE
TN-OO-Ol ............ Moisture Absorption in Plastic Packages (Rev. 2/95) ............................................................
TN-00-02 ............ Tape-and-Reel Procedures (Rev. 2/95) ....................................................................................
TN-00-03 ............ Using Gel-Pak® Packaging With Micron Die (Rev. 2/95) .....................................................
TN-05-02 ............ SRAM Bus Contention Design Considerations (Rev. 11/94) ................................................
TN-05-03 ............ 5V SRAM Capacitive Loading (Rev. 11/94) ............................................................................
TN-05-06 ............ 1 Meg Evolutionary Pinout SRAM Typical (5V) Operating Curves (Rev. 11/94) .............
TN-05-07 ............ 256K SRAM Typical (5V) Operating Curves (Rev. 11/94) ....................................................
TN-05-13 ............ 1 Meg Low-Power SRAMs (Rev. 11/94) ..................................................................................
TN-05-14 ............ SRAM Thermal Design Considerations (Rev. 11/94) ............................................................
TN-05-16 ............ A Designer's Guide to 3.3V SRAMs (Rev. 11/94) ...................................................................
TN-05-17 ............ Low-Power Memory Design Using Data Retention (Rev. 11/94) ........................................
MICRON DATAFAX INDEX
Rev. 2195
11-6
1 pg .......... 600
5 pg .......... 601
2 pg .......... 624
4 pg ........ 2000
1 pg ........ 2001
2 pg ........ 2002
2 pg ........ 2003
3 pg ........ 2005
5 pg ........ 2006
6 pg ........ 2010
3 pg ........ 2011
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995, Micron Technology, Inc.
SyncBurst is a trademark of Micron Technology, Inc
DOCUMENT
NUMBER
SRAM TECHNICAL NOTES (continued)
TN-05-19 ............ SRAMs and Low-Voltage Data Retention (Rev. 11/94) ........................................................
TN-05-20 ............ 3.3V SRAM Capacitive Loading (Rev. 11/94) .........................................................................
TN-05-21 ............ High-Speed Memory Design Techniques (Rev. 11/94) .........................................................
TN-05-22 ............ 1 Meg Revolutionary Pinout SRAM Typical (5V) Operating Curves (Rev. 11/94) ...........
TN-05-23 ............ 256K SRAM Typical (3.3V) Operating Curves (Rev. 11/94) .................................................
TN-58-01 ............ SyncBurst™ SRAM Design for Compatibility (Rev. 11/94) .................................................
TN-58-02 ............ Design Tips: 32K x 36 Synchronous SRAM (Rev. 11/94) ......................................................
TN-58-03 ............ SyncBurstTM SRAMs in Asynchronous Designs (Rev. 11/94) ..............................................
TN-58-04 ............ Design Tips: SyncBurst™ SRAM Standards (Rev. 11/94) .....................................................
2 pg ........ 2013
2 pg ........ 2016
6 pg ........ 2015
3 pg ........ 2017
2 pg ........ 2018
8 pg ........ 2014
5 pg ...•.... 2009
5 pg ........ 2012
5 pg ........ 2019
SRAM PRODUCT RELIABILITY
Product Reliability ....... (Rev. 11/94) ................................................................................................................... 11 pg .......... 707
5/12 VOLT FLASH MEMORY
MT28F002 ................ (Rev. 7/94) ......................... 256K x 8
MT28F200 ................ (Rev. 7/94) ..... 128K x 16/256K x 8
MT28F004 ................ (Rev. 7/94) ......................... 512K x 8
MT28F400 ................ (Rev. 7/94) ..... 256K x 16/512K x 8
MT28F008 ................ (Rev. 7/94) ....................... 1 Meg x 8
MT28F400 ES .......... (Rev. 11/94) .......................... .4 Meg
MT28F004 ES .......... (Rev. 11/94) .......................... .4 Meg
BB, AUTO ....................................................... 25 pg ........ 2601
BB, AUTO ............................................... "...... 26 pg ........ 2602
BB, AUTO ............................................... "...... 25 pg ........ 2603
BB, AUTO ....................................................... 21i pg ........ 26()()
SB, AUTO, DPD ..................................... "........ ll'g ........ 2110 11
ERRATA ........................................................... I pg ........ 26()S
ERRATA ........................................................... 1 pg ........ 2605
BB ............... .
SB
AUTO ...... .
DPD ............... .
......................... Boot Block
. Symmetric Block
....... Automated W IE Algorithm
,.... Deep Power Down
3.3/12 VOLT FLASH MEMORY
MT28LF002
MT28LF200
MT28LF004
MT28LF400
MT28LF008
............. (Rev.
............. (Rev.
............. (Rev.
............. (Rev.
............. (Rev.
BB "" ..........................
SB ......
7/94)
7/94)
7/94)
7/94)
7/94)
......................... 256Kx 8
..... 128K x 16/256K x 8
.................... ,.... 512K x 8
..... 256K x 16/512K x 8
....................... 1 Meg x 8
...... " ... Boot Block
.......................... Symmetric Block
BB, AUTO ............................................. ;........... 2 pg ........ 2900
BB, AUTO ......................................................... 3 pg ........ 2901
BB, AUTO ......................................................... 2 pg ........ 2902
BB, AUTO ............................................... "...... 26 pg ........ 2903
SB, AUTO, DPD ............................................... 3 pg ........ 2904
AUTO.
DPD
"". "" .. " .... ".
..,,"" Automated W IE Algorithm
............... Deep Power Down
CUSTOMER SERVICE NOTES
CSN-Ol
CSN-02
CSN-03
CSN-04
CSN-05
CSN-06
CSN-07
CSN-08
CSN-09
CSN-lO
CSN-11
CSN-12
.......................... Standard Shipping Bar Code Labels (Rev. 2/95) ........................................................
.......................... Individual Box and Container Bar Code Labels (Rev. 2/95) .......................... "........
.......................... Surface-Mount Product Labeling (Rev. 2/95) .............................................................
.......................... Box and Tape-and-Reel Quantity and Weight Chart (Rev. 2/95) ............................
.......................... Environmental Programs (Rev. 2/95) ................................................................ "........
.......................... Electronic Data Interchange (Rev. 2/95) ......................................................................
.......................... Return Material Authorization (RMA) Procedures (Rev. 2/95) ...............................
.......................... ISO 9001 Certification (Rev. 2/95) ................................................................................
.......................... Micron DataFax (Rev. 2/95) ...........................................................................................
.......................... Customer Comment Line (Rev. 2/95) ................................................................ "........
.......................... Part Marking (Rev. 2/95) ...............................................................................................
.......................... Product Change Notification (PCN) System (Rev. 2/95) ..........................................
MICRON DATAFAX INDEX
Ro\'.2/95
11-7
1 pg .......... 709
1 pg .......... 710
1 pg .......... 711
2 pg .......... 712
2 pg .......... 713
1 pg .......... 714
1 pg .......... 715
2 pg .......... 716
1 pg .......... 717
1 pg .......... 719
1 pg .......... 720
1 pg .......... 721
Micron Technology, Inc., reserves the right to change products or specifications without nolice.
©1995, Micron Technology, Inc
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DOCUMENT
NUMBER
SALES AND SERVICE INFORMATION
Product Numbering System (Rev. 2/95) ................................................................................................................ 8 pg .......... 703
Ordering Information and Examples (Rev. 2/95) ................................................................................................ 8 pg .......... 703
North American Sales Representatives and Distributors (Rev. 2/95) ............................................................. 17 pg .......... 704
International Sales Representatives and Distributors (Rev. 2/95) ................................................................... 17 pg .......... 704
GENERAL PRODUCT INFORMATION
•
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Literature Order Form (Rev. 11 /94) ....................................................................................................................... 2 pg ........ 2300
Memory Selector Guide (Rev. 5/94) ....................................................................................................................... 3 pg ........ 2301
3.3V DRAM Selector Guide (Rev. 1/95) ................................................................................................................. 3 pg ........ 2317
Design Line, November (Fall), 1992:
Upgrading from 1 Meg to 2 Meg VRAMs
Reduce DRAM Cycle Times with Extended Data-Out ................................................................... 8 pg ........ 2303
Design Line, February (Spring), 1993:
486 Level-2 Cache Design .................................................................................................................... 8 pg ........ 2304
Design Line, 2nd Quarter 1993 (2Q93):
Synchronous DRAMs: Designing to the JEDEC Standard
Converting from x9 Memory Modules to x36 SIMMs ..................................................................... 8 pg ........ 2305
Design Line, 3rd Quarter 1993 (3Q93):
SRAM Thermal Design Considerations
A Designer's Guide to 3.3V SRAMs ................................................................................................. 12 pg ........ 2308
Design Line, 4th Quarter 1993 (4Q93):
Design Tips: 32K x 36 Sync SRAM
Achieving Higher Memory Bandwidth in Graphics Systems ...................................................... 12 pg ........ 2309
Design Line, 1st Quarter 1994 (lQ94):
DRAM Soft Error Rate Calculations
SyncBurst SRAMs in Asynchronous Designs ................................................................................... 8 pg ........ 2310
Design Line, 2nd Quarter 1994 (2Q94):
Maximizing EDO Advantages at the System Level ......................................................................... 8 pg ........ 2311
Design Line, 3rd Quarter 1994 (3Q94):
High-Speed Memory Design Techniques
Various Methods of DRAM Refresh .................................................................................................. 8 pg ........ 2313
Design Line, 4th Quarter 1994 (4Q94):
Reduce DRAM Memory Costs With Cache
Design Tips: SyncBurst SRAM Standards ......................................................................................... 8 pg ........ 2318
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MICRON DATAFAX INDEX
Rev. 2195
11-8
Micron Technology, Inc., reserves the right to change products or specifications without notice
©1995,MlcronTechnology, Inc
NOTES
NOTES
EDO DRAMs ....................................................
.:III
FPM DRAMs .................................................... . .
~C3iRAM
............................................................ ~
DRAM ~IMMs .................................................. _ _
DRAM DIMMs .................................................. _ _
DRAM CARD~ ............... .................. ................ _ _
TECHNICAL NOTE~ ........................................ . .
PRODUCT RELIABILITy................................. _ _
PACKAC3iE INFORMATION .............................. _ _
~ALE~ AND ~ERVICE INFORMATION ...........
IIIIM
MICRON DATAFAX INDEX ..............................
II1II
. . ................................................... EDO DRAMs
. . .................................................... FPM DRAMs
__
........................................................... SGRAM
__
.................................................. DRAM SIMMs
__
.................................................. DRAM DIMMs
__
................................................ DRAM CARDS
. . ....................................... TECHNICAL NOTES
~
................................ PRODUCT RELIABILITY
.1'. . . . . .
. . ............................. PACKAGE INFORMATION
SALES AND SERVICE INFORMATION
IIIII ............................. MICRON DATAFAX INDEX
Micron Technologu, Inc.
2805 East Columbia Road
P.O. Box 6
Boise, Idaho 83707-0006
Tel: 208-368-3900
Fax: 208-368-4431
Customer Comment Line:
U.S.A. 800-932-4992
IntI. 01 -208-368-3410
Fax 208-368-3342
Micron Europe ~imited
Centennial Court
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Tel : 44-1344-360055
Fax: 44-1344-869504
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D-85609 Aschheim
Germany
Tel : 49-89-903-0021
Fax: 49-89-904-3114
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Singapore 1438
Tel : 65-841-4066
Fax: 65-841-4166
Micron Semiconductor Asia Pacinc, Inc.
Suite 1010, 10th Floor
333 Keelung Road, Sec 1
Taipei , 110 Taiwan , ROC
Tel: 886-2-757-6622
Fax: 886-2-757-6656
I'IIIC:F=lg~
™
~
lJiiliiFax·
208·368·5800
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